opcodes/d10v-dis.c

   1 /* Disassemble D10V instructions.
   2    Copyright (C) 1996, 1997 Free Software Foundation, Inc.
   3
   4 This program is free software; you can redistribute it and/or modify
   5 it under the terms of the GNU General Public License as published by
   6 the Free Software Foundation; either version 2 of the License, or
   7 (at your option) any later version.
   8
   9 This program is distributed in the hope that it will be useful,
  10 but WITHOUT ANY WARRANTY; without even the implied warranty of
  11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12 GNU General Public License for more details.
  13
  14 You should have received a copy of the GNU General Public License
  15 along with this program; if not, write to the Free Software
  16 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  17
  18
  19 #include <stdio.h>
  20
  21 #include "opcode/d10v.h"
  22 #include "dis-asm.h"
  23
  24 /* the PC wraps at 18 bits, except for the segment number */
  25 /* so use this mask to keep the parts we want */
  26 #define PC_MASK 0x03003FFF
  27
  28 static void dis_2_short PARAMS ((unsigned long insn, bfd_vma memaddr,
  29                                  struct disassemble_info *info, int order));
  30 static void dis_long PARAMS ((unsigned long insn, bfd_vma memaddr,
  31                               struct disassemble_info *info));
  32
  33 int
  34 print_insn_d10v (memaddr, info)
  35      bfd_vma memaddr;
  36      struct disassemble_info *info;
  37 {
  38   int status;
  39   bfd_byte buffer[4];
  40   unsigned long insn;
  41
  42   status = (*info->read_memory_func) (memaddr, buffer, 4, info);
  43   if (status != 0)
  44     {
  45       (*info->memory_error_func) (status, memaddr, info);
  46       return -1;
  47     }
  48   insn = bfd_getb32 (buffer);
  49
  50   status = insn & FM11;
  51   switch (status) {
  52   case 0:
  53     dis_2_short (insn, memaddr, info, 2);
  54     break;
  55   case FM01:
  56     dis_2_short (insn, memaddr, info, 0);
  57     break;
  58   case FM10:
  59     dis_2_short (insn, memaddr, info, 1);
  60     break;
  61   case FM11:
  62     dis_long (insn, memaddr, info);
  63     break;
  64   }
  65   return 4;
  66 }
  67
  68 static void
  69 print_operand (oper, insn, op, memaddr, info)
  70      struct d10v_operand *oper;
  71      unsigned long insn;
  72      struct d10v_opcode *op;
  73      bfd_vma memaddr;
  74      struct disassemble_info *info;
  75 {
  76   int num, shift;
  77
  78   if (oper->flags == OPERAND_ATMINUS)
  79     {
  80       (*info->fprintf_func) (info->stream, "@-");
  81       return;
  82     }
  83   if (oper->flags == OPERAND_MINUS)
  84     {
  85       (*info->fprintf_func) (info->stream, "-");
  86       return;
  87     }
  88   if (oper->flags == OPERAND_PLUS)
  89     {
  90       (*info->fprintf_func) (info->stream, "+");
  91       return;
  92     }
  93   if (oper->flags == OPERAND_ATSIGN)
  94     {
  95       (*info->fprintf_func) (info->stream, "@");
  96       return;
  97     }
  98   if (oper->flags == OPERAND_ATPAR)
  99     {
 100       (*info->fprintf_func) (info->stream, "@(");
 101       return;
 102     }
 103
 104   shift = oper->shift;
 105
 106   /* the LONG_L format shifts registers over by 15 */
 107   if (op->format == LONG_L && (oper->flags & OPERAND_REG))
 108     shift += 15;
 109
 110   num = (insn >> shift) & (0x7FFFFFFF >> (31 - oper->bits));
 111
 112   if (oper->flags & OPERAND_REG)
 113     {
 114       int i;
 115       int match=0;
 116       num += oper->flags & (OPERAND_ACC|OPERAND_FLAG|OPERAND_CONTROL);
 117       for (i=0;i<reg_name_cnt();i++)
 118         {
 119           if (num == pre_defined_registers[i].value)
 120             {
 121               if (pre_defined_registers[i].pname)
 122                 (*info->fprintf_func) (info->stream, "%s",pre_defined_registers[i].pname);
 123               else
 124                 (*info->fprintf_func) (info->stream, "%s",pre_defined_registers[i].name);
 125               match=1;
 126               break;
 127             }
 128         }
 129       if (match==0)
 130         {
 131           /* this would only get executed if a register was not in the
 132              register table */
 133           if (oper->flags & OPERAND_ACC)
 134             (*info->fprintf_func) (info->stream, "a");
 135           else if (oper->flags & OPERAND_CONTROL)
 136             (*info->fprintf_func) (info->stream, "cr");
 137           else if(oper->flags & OPERAND_REG)
 138             (*info->fprintf_func) (info->stream, "r");
 139           (*info->fprintf_func) (info->stream, "%d",num);
 140         }
 141     }
 142   else
 143     {
 144       /* addresses are right-shifted by 2 */
 145       if (oper->flags & OPERAND_ADDR)
 146         {
 147           long max;
 148           int neg=0;
 149           max = (1 << (oper->bits - 1));
 150           if (num & max)
 151             {
 152               num = -num & ((1 << oper->bits)-1);
 153               neg = 1;
 154             }
 155           num = num<<2;
 156           if (neg)
 157             (*info->print_address_func) ((memaddr - num) & PC_MASK, info);
 158           else
 159             (*info->print_address_func) ((memaddr + num) & PC_MASK, info);
 160         }
 161       else
 162         {
 163           if (oper->flags & OPERAND_SIGNED)
 164             {
 165               int max = (1 << (oper->bits - 1));
 166               if (num & max)
 167                 {
 168                   num = -num & ((1 << oper->bits)-1);
 169                   (*info->fprintf_func) (info->stream, "-");
 170                 }
 171             }
 172           (*info->fprintf_func) (info->stream, "0x%x",num);
 173         }
 174     }
 175 }
 176
 177
 178 static void
 179 dis_long (insn, memaddr, info)
 180      unsigned long insn;
 181      bfd_vma memaddr;
 182      struct disassemble_info *info;
 183 {
 184   int i;
 185   char buf[32];
 186   struct d10v_opcode *op = (struct d10v_opcode *)d10v_opcodes;
 187   struct d10v_operand *oper;
 188   int need_paren = 0;
 189   int match = 0;
 190
 191   while (op->name)
 192     {
 193       if ((op->format & LONG_OPCODE) && ((op->mask & insn) == op->opcode))
 194         {
 195           match = 1;
 196           (*info->fprintf_func) (info->stream, "%s\t", op->name);
 197           for ( i=0; op->operands[i]; i++)
 198             {
 199               oper = (struct d10v_operand *)&d10v_operands[op->operands[i]];
 200               if (oper->flags == OPERAND_ATPAR)
 201                 need_paren = 1;
 202               print_operand (oper, insn, op, memaddr, info);
 203               if (op->operands[i+1] && oper->bits &&
 204                   d10v_operands[op->operands[i+1]].flags != OPERAND_PLUS &&
 205                   d10v_operands[op->operands[i+1]].flags != OPERAND_MINUS)
 206                 (*info->fprintf_func) (info->stream, ", ");
 207             }
 208           break;
 209         }
 210       op++;
 211     }
 212
 213   if (!match)
 214     (*info->fprintf_func) (info->stream, ".long\t0x%08x",insn);
 215
 216   if (need_paren)
 217     (*info->fprintf_func) (info->stream, ")");
 218 }
 219
 220 static void
 221 dis_2_short (insn, memaddr, info, order)
 222      unsigned long insn;
 223      bfd_vma memaddr;
 224      struct disassemble_info *info;
 225      int order;
 226 {
 227   int i,j;
 228   char astr[2][32];
 229   unsigned int ins[2];
 230   struct d10v_opcode *op;
 231   char buf[32];
 232   int match, num_match=0;
 233   struct d10v_operand *oper;
 234   int need_paren = 0;
 235
 236   ins[0] = (insn & 0x3FFFFFFF) >> 15;
 237   ins[1] = insn & 0x00007FFF;
 238
 239   for(j=0;j<2;j++)
 240     {
 241       op = (struct d10v_opcode *)d10v_opcodes;
 242       match=0;
 243       while (op->name)
 244         {
 245           if ((op->format & SHORT_OPCODE) && ((op->mask & ins[j]) == op->opcode))
 246             {
 247               (*info->fprintf_func) (info->stream, "%s\t",op->name);
 248               for (i=0; op->operands[i]; i++)
 249                 {
 250                   oper = (struct d10v_operand *)&d10v_operands[op->operands[i]];
 251                   if (oper->flags == OPERAND_ATPAR)
 252                     need_paren = 1;
 253                   print_operand (oper, ins[j], op, memaddr, info);
 254                   if (op->operands[i+1] && oper->bits &&
 255                   d10v_operands[op->operands[i+1]].flags != OPERAND_PLUS &&
 256                   d10v_operands[op->operands[i+1]].flags != OPERAND_MINUS)
 257                     (*info->fprintf_func) (info->stream, ", ");
 258                 }
 259               match = 1;
 260               num_match++;
 261               break;
 262             }
 263           op++;
 264         }
 265       if (!match)
 266         (*info->fprintf_func) (info->stream, "unknown");
 267
 268       switch (order)
 269         {
 270         case 0:
 271           (*info->fprintf_func) (info->stream, "\t->\t");
 272           order = -1;
 273           break;
 274         case 1:
 275           (*info->fprintf_func) (info->stream, "\t<-\t");
 276           order = -1;
 277           break;
 278         case 2:
 279           (*info->fprintf_func) (info->stream, "\t||\t");
 280           order = -1;
 281           break;
 282         default:
 283           break;
 284         }
 285     }
 286
 287   if (num_match == 0)
 288     (*info->fprintf_func) (info->stream, ".long\t0x%08x",insn);
 289
 290   if (need_paren)
 291     (*info->fprintf_func) (info->stream, ")");
 292 }