1 /* Generic opcode table support for targets using CGEN. -*- C -*-
2 CGEN: Cpu tools GENerator
4 THIS FILE IS USED TO GENERATE fr30-opc.c.
6 Copyright (C) 1998 Free Software Foundation, Inc.
8 This file is part of the GNU Binutils and GDB, the GNU debugger.
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software Foundation, Inc.,
22 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
27 #include "libiberty.h"
33 /* Used by the ifield rtx function. */
34 #define FLD(f) (fields->f)
36 /* The hash functions are recorded here to help keep assembler code out of
37 the disassembler and vice versa. */
39 static int asm_hash_insn_p
PARAMS ((const CGEN_INSN
*));
40 static unsigned int asm_hash_insn
PARAMS ((const char *));
41 static int dis_hash_insn_p
PARAMS ((const CGEN_INSN
*));
42 static unsigned int dis_hash_insn
PARAMS ((const char *, CGEN_INSN_INT
));
44 /* Look up instruction INSN_VALUE and extract its fields.
45 INSN, if non-null, is the insn table entry.
46 Otherwise INSN_VALUE is examined to compute it.
47 LENGTH is the bit length of INSN_VALUE if known, otherwise 0.
48 0 is only valid if `insn == NULL && ! CGEN_INT_INSN_P'.
49 If INSN != NULL, LENGTH must be valid.
50 ALIAS_P is non-zero if alias insns are to be included in the search.
52 The result is a pointer to the insn table entry, or NULL if the instruction
56 fr30_cgen_lookup_insn (od
, insn
, insn_value
, length
, fields
, alias_p
)
58 const CGEN_INSN
*insn
;
59 CGEN_INSN_BYTES insn_value
;
64 unsigned char buf
[CGEN_MAX_INSN_SIZE
];
66 CGEN_INSN_INT base_insn
;
68 CGEN_EXTRACT_INFO
*info
= NULL
;
70 CGEN_EXTRACT_INFO ex_info
;
71 CGEN_EXTRACT_INFO
*info
= &ex_info
;
75 cgen_put_insn_value (od
, buf
, length
, insn_value
);
77 base_insn
= insn_value
; /*???*/
79 ex_info
.dis_info
= NULL
;
80 ex_info
.insn_bytes
= insn_value
;
82 base_insn
= cgen_get_insn_value (od
, buf
, length
);
88 const CGEN_INSN_LIST
*insn_list
;
90 /* The instructions are stored in hash lists.
91 Pick the first one and keep trying until we find the right one. */
93 insn_list
= CGEN_DIS_LOOKUP_INSN (od
, bufp
, base_insn
);
94 while (insn_list
!= NULL
)
96 insn
= insn_list
->insn
;
99 || ! CGEN_INSN_ATTR (insn
, CGEN_INSN_ALIAS
))
101 /* Basic bit mask must be correct. */
102 /* ??? May wish to allow target to defer this check until the
104 if ((base_insn
& CGEN_INSN_BASE_MASK (insn
))
105 == CGEN_INSN_BASE_VALUE (insn
))
107 /* ??? 0 is passed for `pc' */
108 int elength
= (*CGEN_EXTRACT_FN (insn
)) (od
, insn
, info
,
114 if (length
!= 0 && length
!= elength
)
121 insn_list
= CGEN_DIS_NEXT_INSN (insn_list
);
126 /* Sanity check: can't pass an alias insn if ! alias_p. */
128 && CGEN_INSN_ATTR (insn
, CGEN_INSN_ALIAS
))
130 /* Sanity check: length must be correct. */
131 if (length
!= CGEN_INSN_BITSIZE (insn
))
134 /* ??? 0 is passed for `pc' */
135 length
= (*CGEN_EXTRACT_FN (insn
)) (od
, insn
, info
, base_insn
, fields
,
137 /* Sanity check: must succeed.
138 Could relax this later if it ever proves useful. */
147 /* Fill in the operand instances used by INSN whose operands are FIELDS.
148 INDICES is a pointer to a buffer of MAX_OPERAND_INSTANCES ints to be filled
152 fr30_cgen_get_insn_operands (od
, insn
, fields
, indices
)
154 const CGEN_INSN
* insn
;
155 const CGEN_FIELDS
* fields
;
158 const CGEN_OPERAND_INSTANCE
*opinst
;
161 for (i
= 0, opinst
= CGEN_INSN_OPERANDS (insn
);
163 && CGEN_OPERAND_INSTANCE_TYPE (opinst
) != CGEN_OPERAND_INSTANCE_END
;
166 const CGEN_OPERAND
*op
= CGEN_OPERAND_INSTANCE_OPERAND (opinst
);
168 indices
[i
] = CGEN_OPERAND_INSTANCE_INDEX (opinst
);
170 indices
[i
] = fr30_cgen_get_int_operand (CGEN_OPERAND_INDEX (op
),
175 /* Cover function to fr30_cgen_get_insn_operands when either INSN or FIELDS
177 The INSN, INSN_VALUE, and LENGTH arguments are passed to
178 fr30_cgen_lookup_insn unchanged.
180 The result is the insn table entry or NULL if the instruction wasn't
184 fr30_cgen_lookup_get_insn_operands (od
, insn
, insn_value
, length
, indices
)
186 const CGEN_INSN
*insn
;
187 CGEN_INSN_BYTES insn_value
;
193 /* Pass non-zero for ALIAS_P only if INSN != NULL.
194 If INSN == NULL, we want a real insn. */
195 insn
= fr30_cgen_lookup_insn (od
, insn
, insn_value
, length
, &fields
,
200 fr30_cgen_get_insn_operands (od
, insn
, &fields
, indices
);
205 static const CGEN_ATTR_ENTRY MACH_attr
[] =
207 { "base", MACH_BASE
},
208 { "fr30", MACH_FR30
},
213 const CGEN_ATTR_TABLE fr30_cgen_hardware_attr_table
[] =
215 { "CACHE-ADDR", NULL
},
216 { "FUN-ACCESS", NULL
},
222 const CGEN_ATTR_TABLE fr30_cgen_operand_attr_table
[] =
224 { "ABS-ADDR", NULL
},
225 { "HASH-PREFIX", NULL
},
226 { "NEGATIVE", NULL
},
227 { "PCREL-ADDR", NULL
},
229 { "SEM-ONLY", NULL
},
230 { "SIGN-OPT", NULL
},
232 { "UNSIGNED", NULL
},
237 const CGEN_ATTR_TABLE fr30_cgen_insn_attr_table
[] =
240 { "COND-CTI", NULL
},
241 { "DELAY-SLOT", NULL
},
243 { "NOT-IN-DELAY-SLOT", NULL
},
245 { "RELAXABLE", NULL
},
246 { "SKIP-CTI", NULL
},
247 { "UNCOND-CTI", NULL
},
252 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_gr_entries
[] =
275 CGEN_KEYWORD fr30_cgen_opval_h_gr
=
277 & fr30_cgen_opval_h_gr_entries
[0],
281 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_cr_entries
[] =
301 CGEN_KEYWORD fr30_cgen_opval_h_cr
=
303 & fr30_cgen_opval_h_cr_entries
[0],
307 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_dr_entries
[] =
317 CGEN_KEYWORD fr30_cgen_opval_h_dr
=
319 & fr30_cgen_opval_h_dr_entries
[0],
323 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_ps_entries
[] =
328 CGEN_KEYWORD fr30_cgen_opval_h_ps
=
330 & fr30_cgen_opval_h_ps_entries
[0],
334 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r13_entries
[] =
339 CGEN_KEYWORD fr30_cgen_opval_h_r13
=
341 & fr30_cgen_opval_h_r13_entries
[0],
345 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r14_entries
[] =
350 CGEN_KEYWORD fr30_cgen_opval_h_r14
=
352 & fr30_cgen_opval_h_r14_entries
[0],
356 CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r15_entries
[] =
361 CGEN_KEYWORD fr30_cgen_opval_h_r15
=
363 & fr30_cgen_opval_h_r15_entries
[0],
368 /* The hardware table. */
370 #define HW_ENT(n) fr30_cgen_hw_entries[n]
371 static const CGEN_HW_ENTRY fr30_cgen_hw_entries
[] =
373 { HW_H_PC
, & HW_ENT (HW_H_PC
+ 1), "h-pc", CGEN_ASM_KEYWORD
, (PTR
) 0, { 0, 0|(1<<CGEN_HW_PROFILE
)|(1<<CGEN_HW_PC
), { 0 } } },
374 { HW_H_MEMORY
, & HW_ENT (HW_H_MEMORY
+ 1), "h-memory", CGEN_ASM_KEYWORD
, (PTR
) 0, { 0, 0, { 0 } } },
375 { HW_H_SINT
, & HW_ENT (HW_H_SINT
+ 1), "h-sint", CGEN_ASM_KEYWORD
, (PTR
) 0, { 0, 0, { 0 } } },
376 { HW_H_UINT
, & HW_ENT (HW_H_UINT
+ 1), "h-uint", CGEN_ASM_KEYWORD
, (PTR
) 0, { 0, 0, { 0 } } },
377 { HW_H_ADDR
, & HW_ENT (HW_H_ADDR
+ 1), "h-addr", CGEN_ASM_KEYWORD
, (PTR
) 0, { 0, 0, { 0 } } },
378 { HW_H_IADDR
, & HW_ENT (HW_H_IADDR
+ 1), "h-iaddr", CGEN_ASM_KEYWORD
, (PTR
) 0, { 0, 0, { 0 } } },
379 { HW_H_GR
, & HW_ENT (HW_H_GR
+ 1), "h-gr", CGEN_ASM_KEYWORD
, (PTR
) & fr30_cgen_opval_h_gr
, { 0, 0|(1<<CGEN_HW_CACHE_ADDR
)|(1<<CGEN_HW_PROFILE
), { 0 } } },
380 { HW_H_CR
, & HW_ENT (HW_H_CR
+ 1), "h-cr", CGEN_ASM_KEYWORD
, (PTR
) & fr30_cgen_opval_h_cr
, { 0, 0, { 0 } } },
381 { HW_H_DR
, & HW_ENT (HW_H_DR
+ 1), "h-dr", CGEN_ASM_KEYWORD
, (PTR
) & fr30_cgen_opval_h_dr
, { 0, 0|(1<<CGEN_HW_FUN_ACCESS
), { 0 } } },
382 { HW_H_PS
, & HW_ENT (HW_H_PS
+ 1), "h-ps", CGEN_ASM_KEYWORD
, (PTR
) & fr30_cgen_opval_h_ps
, { 0, 0|(1<<CGEN_HW_FUN_ACCESS
), { 0 } } },
383 { HW_H_R13
, & HW_ENT (HW_H_R13
+ 1), "h-r13", CGEN_ASM_KEYWORD
, (PTR
) & fr30_cgen_opval_h_r13
, { 0, 0, { 0 } } },
384 { HW_H_R14
, & HW_ENT (HW_H_R14
+ 1), "h-r14", CGEN_ASM_KEYWORD
, (PTR
) & fr30_cgen_opval_h_r14
, { 0, 0, { 0 } } },
385 { HW_H_R15
, & HW_ENT (HW_H_R15
+ 1), "h-r15", CGEN_ASM_KEYWORD
, (PTR
) & fr30_cgen_opval_h_r15
, { 0, 0, { 0 } } },
386 { HW_H_NBIT
, & HW_ENT (HW_H_NBIT
+ 1), "h-nbit", CGEN_ASM_KEYWORD
, (PTR
) 0, { 0, 0, { 0 } } },
387 { HW_H_ZBIT
, & HW_ENT (HW_H_ZBIT
+ 1), "h-zbit", CGEN_ASM_KEYWORD
, (PTR
) 0, { 0, 0, { 0 } } },
388 { HW_H_VBIT
, & HW_ENT (HW_H_VBIT
+ 1), "h-vbit", CGEN_ASM_KEYWORD
, (PTR
) 0, { 0, 0, { 0 } } },
389 { HW_H_CBIT
, & HW_ENT (HW_H_CBIT
+ 1), "h-cbit", CGEN_ASM_KEYWORD
, (PTR
) 0, { 0, 0, { 0 } } },
390 { HW_H_IBIT
, & HW_ENT (HW_H_IBIT
+ 1), "h-ibit", CGEN_ASM_KEYWORD
, (PTR
) 0, { 0, 0, { 0 } } },
391 { HW_H_SBIT
, & HW_ENT (HW_H_SBIT
+ 1), "h-sbit", CGEN_ASM_KEYWORD
, (PTR
) 0, { 0, 0, { 0 } } },
392 { HW_H_TBIT
, & HW_ENT (HW_H_TBIT
+ 1), "h-tbit", CGEN_ASM_KEYWORD
, (PTR
) 0, { 0, 0, { 0 } } },
393 { HW_H_D0BIT
, & HW_ENT (HW_H_D0BIT
+ 1), "h-d0bit", CGEN_ASM_KEYWORD
, (PTR
) 0, { 0, 0, { 0 } } },
394 { HW_H_D1BIT
, & HW_ENT (HW_H_D1BIT
+ 1), "h-d1bit", CGEN_ASM_KEYWORD
, (PTR
) 0, { 0, 0, { 0 } } },
395 { HW_H_CCR
, & HW_ENT (HW_H_CCR
+ 1), "h-ccr", CGEN_ASM_KEYWORD
, (PTR
) 0, { 0, 0|(1<<CGEN_HW_FUN_ACCESS
), { 0 } } },
396 { HW_H_SCR
, & HW_ENT (HW_H_SCR
+ 1), "h-scr", CGEN_ASM_KEYWORD
, (PTR
) 0, { 0, 0|(1<<CGEN_HW_FUN_ACCESS
), { 0 } } },
397 { HW_H_ILM
, & HW_ENT (HW_H_ILM
+ 1), "h-ilm", CGEN_ASM_KEYWORD
, (PTR
) 0, { 0, 0|(1<<CGEN_HW_FUN_ACCESS
), { 0 } } },
401 /* The instruction field table. */
403 static const CGEN_IFLD fr30_cgen_ifld_table
[] =
405 { FR30_F_NIL
, "f-nil", 0, 0, 0, 0, { 0, 0, { 0 } } },
406 { FR30_F_OP1
, "f-op1", 0, 16, 0, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED
), { 0 } } },
407 { FR30_F_OP2
, "f-op2", 0, 16, 4, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED
), { 0 } } },
408 { FR30_F_OP3
, "f-op3", 0, 16, 8, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED
), { 0 } } },
409 { FR30_F_OP4
, "f-op4", 0, 16, 12, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED
), { 0 } } },
410 { FR30_F_OP5
, "f-op5", 0, 16, 4, 1, { 0, 0|(1<<CGEN_IFLD_UNSIGNED
), { 0 } } },
411 { FR30_F_CC
, "f-cc", 0, 16, 4, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED
), { 0 } } },
412 { FR30_F_CCC
, "f-ccc", 16, 16, 0, 8, { 0, 0|(1<<CGEN_IFLD_UNSIGNED
), { 0 } } },
413 { FR30_F_RJ
, "f-Rj", 0, 16, 8, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED
), { 0 } } },
414 { FR30_F_RI
, "f-Ri", 0, 16, 12, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED
), { 0 } } },
415 { FR30_F_RS1
, "f-Rs1", 0, 16, 8, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED
), { 0 } } },
416 { FR30_F_RS2
, "f-Rs2", 0, 16, 12, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED
), { 0 } } },
417 { FR30_F_RJC
, "f-Rjc", 16, 16, 8, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED
), { 0 } } },
418 { FR30_F_RIC
, "f-Ric", 16, 16, 12, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED
), { 0 } } },
419 { FR30_F_CRJ
, "f-CRj", 16, 16, 8, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED
), { 0 } } },
420 { FR30_F_CRI
, "f-CRi", 16, 16, 12, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED
), { 0 } } },
421 { FR30_F_U4
, "f-u4", 0, 16, 8, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED
), { 0 } } },
422 { FR30_F_U4C
, "f-u4c", 0, 16, 12, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED
), { 0 } } },
423 { FR30_F_I4
, "f-i4", 0, 16, 8, 4, { 0, 0|(1<<CGEN_IFLD_SIGNED
), { 0 } } },
424 { FR30_F_M4
, "f-m4", 0, 16, 8, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED
), { 0 } } },
425 { FR30_F_U8
, "f-u8", 0, 16, 8, 8, { 0, 0|(1<<CGEN_IFLD_UNSIGNED
), { 0 } } },
426 { FR30_F_I8
, "f-i8", 0, 16, 4, 8, { 0, 0|(1<<CGEN_IFLD_UNSIGNED
), { 0 } } },
427 { FR30_F_I20_4
, "f-i20-4", 0, 16, 8, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED
), { 0 } } },
428 { FR30_F_I20_16
, "f-i20-16", 16, 16, 0, 16, { 0, 0|(1<<CGEN_IFLD_UNSIGNED
), { 0 } } },
429 { FR30_F_I32
, "f-i32", 16, 32, 0, 32, { 0, 0|(1<<CGEN_IFLD_SIGN_OPT
)|(1<<CGEN_IFLD_UNSIGNED
), { 0 } } },
430 { FR30_F_UDISP6
, "f-udisp6", 0, 16, 8, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED
), { 0 } } },
431 { FR30_F_DISP8
, "f-disp8", 0, 16, 4, 8, { 0, 0|(1<<CGEN_IFLD_SIGNED
), { 0 } } },
432 { FR30_F_DISP9
, "f-disp9", 0, 16, 4, 8, { 0, 0|(1<<CGEN_IFLD_SIGNED
), { 0 } } },
433 { FR30_F_DISP10
, "f-disp10", 0, 16, 4, 8, { 0, 0|(1<<CGEN_IFLD_SIGNED
), { 0 } } },
434 { FR30_F_S10
, "f-s10", 0, 16, 8, 8, { 0, 0|(1<<CGEN_IFLD_SIGNED
), { 0 } } },
435 { FR30_F_U10
, "f-u10", 0, 16, 8, 8, { 0, 0|(1<<CGEN_IFLD_UNSIGNED
), { 0 } } },
436 { FR30_F_REL9
, "f-rel9", 0, 16, 8, 8, { 0, 0|(1<<CGEN_IFLD_PCREL_ADDR
)|(1<<CGEN_IFLD_SIGNED
), { 0 } } },
437 { FR30_F_DIR8
, "f-dir8", 0, 16, 8, 8, { 0, 0|(1<<CGEN_IFLD_UNSIGNED
), { 0 } } },
438 { FR30_F_DIR9
, "f-dir9", 0, 16, 8, 8, { 0, 0|(1<<CGEN_IFLD_UNSIGNED
), { 0 } } },
439 { FR30_F_DIR10
, "f-dir10", 0, 16, 8, 8, { 0, 0|(1<<CGEN_IFLD_UNSIGNED
), { 0 } } },
440 { FR30_F_REL12
, "f-rel12", 0, 16, 5, 11, { 0, 0|(1<<CGEN_IFLD_PCREL_ADDR
)|(1<<CGEN_IFLD_SIGNED
), { 0 } } },
441 { FR30_F_REGLIST_HI_ST
, "f-reglist_hi_st", 0, 16, 8, 8, { 0, 0|(1<<CGEN_IFLD_UNSIGNED
), { 0 } } },
442 { FR30_F_REGLIST_LOW_ST
, "f-reglist_low_st", 0, 16, 8, 8, { 0, 0|(1<<CGEN_IFLD_UNSIGNED
), { 0 } } },
443 { FR30_F_REGLIST_HI_LD
, "f-reglist_hi_ld", 0, 16, 8, 8, { 0, 0|(1<<CGEN_IFLD_UNSIGNED
), { 0 } } },
444 { FR30_F_REGLIST_LOW_LD
, "f-reglist_low_ld", 0, 16, 8, 8, { 0, 0|(1<<CGEN_IFLD_UNSIGNED
), { 0 } } },
448 /* The operand table. */
450 #define OPERAND(op) CONCAT2 (FR30_OPERAND_,op)
451 #define OP_ENT(op) fr30_cgen_operand_table[OPERAND (op)]
453 const CGEN_OPERAND fr30_cgen_operand_table
[MAX_OPERANDS
] =
455 /* pc: program counter */
456 { "pc", & HW_ENT (HW_H_PC
), 0, 0,
457 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY
), { 0 } } },
458 /* Ri: destination register */
459 { "Ri", & HW_ENT (HW_H_GR
), 12, 4,
460 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED
), { 0 } } },
461 /* Rj: source register */
462 { "Rj", & HW_ENT (HW_H_GR
), 8, 4,
463 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED
), { 0 } } },
464 /* Ric: target register coproc insn */
465 { "Ric", & HW_ENT (HW_H_GR
), 12, 4,
466 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED
), { 0 } } },
467 /* Rjc: source register coproc insn */
468 { "Rjc", & HW_ENT (HW_H_GR
), 8, 4,
469 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED
), { 0 } } },
470 /* CRi: coprocessor register */
471 { "CRi", & HW_ENT (HW_H_CR
), 12, 4,
472 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED
), { 0 } } },
473 /* CRj: coprocessor register */
474 { "CRj", & HW_ENT (HW_H_CR
), 8, 4,
475 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED
), { 0 } } },
476 /* Rs1: dedicated register */
477 { "Rs1", & HW_ENT (HW_H_DR
), 8, 4,
478 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED
), { 0 } } },
479 /* Rs2: dedicated register */
480 { "Rs2", & HW_ENT (HW_H_DR
), 12, 4,
481 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED
), { 0 } } },
482 /* R13: General Register 13 */
483 { "R13", & HW_ENT (HW_H_R13
), 0, 0,
485 /* R14: General Register 14 */
486 { "R14", & HW_ENT (HW_H_R14
), 0, 0,
488 /* R15: General Register 15 */
489 { "R15", & HW_ENT (HW_H_R15
), 0, 0,
491 /* ps: Program Status register */
492 { "ps", & HW_ENT (HW_H_PS
), 0, 0,
494 /* u4: 4 bit unsigned immediate */
495 { "u4", & HW_ENT (HW_H_UINT
), 8, 4,
496 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX
)|(1<<CGEN_OPERAND_UNSIGNED
), { 0 } } },
497 /* u4c: 4 bit unsigned immediate */
498 { "u4c", & HW_ENT (HW_H_UINT
), 12, 4,
499 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX
)|(1<<CGEN_OPERAND_UNSIGNED
), { 0 } } },
500 /* u8: 8 bit unsigned immediate */
501 { "u8", & HW_ENT (HW_H_UINT
), 8, 8,
502 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX
)|(1<<CGEN_OPERAND_UNSIGNED
), { 0 } } },
503 /* i8: 8 bit unsigned immediate */
504 { "i8", & HW_ENT (HW_H_UINT
), 4, 8,
505 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX
)|(1<<CGEN_OPERAND_UNSIGNED
), { 0 } } },
506 /* udisp6: 6 bit unsigned immediate */
507 { "udisp6", & HW_ENT (HW_H_UINT
), 8, 4,
508 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX
)|(1<<CGEN_OPERAND_UNSIGNED
), { 0 } } },
509 /* disp8: 8 bit signed immediate */
510 { "disp8", & HW_ENT (HW_H_SINT
), 4, 8,
511 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX
)|(1<<CGEN_OPERAND_SIGNED
), { 0 } } },
512 /* disp9: 9 bit signed immediate */
513 { "disp9", & HW_ENT (HW_H_SINT
), 4, 8,
514 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX
)|(1<<CGEN_OPERAND_SIGNED
), { 0 } } },
515 /* disp10: 10 bit signed immediate */
516 { "disp10", & HW_ENT (HW_H_SINT
), 4, 8,
517 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX
)|(1<<CGEN_OPERAND_SIGNED
), { 0 } } },
518 /* s10: 10 bit signed immediate */
519 { "s10", & HW_ENT (HW_H_SINT
), 8, 8,
520 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX
)|(1<<CGEN_OPERAND_SIGNED
), { 0 } } },
521 /* u10: 10 bit unsigned immediate */
522 { "u10", & HW_ENT (HW_H_UINT
), 8, 8,
523 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX
)|(1<<CGEN_OPERAND_UNSIGNED
), { 0 } } },
524 /* i32: 32 bit immediate */
525 { "i32", & HW_ENT (HW_H_UINT
), 0, 32,
526 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX
)|(1<<CGEN_OPERAND_SIGN_OPT
)|(1<<CGEN_OPERAND_UNSIGNED
), { 0 } } },
527 /* m4: 4 bit negative immediate */
528 { "m4", & HW_ENT (HW_H_SINT
), 8, 4,
529 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED
), { 0 } } },
530 /* i20: 20 bit immediate */
531 { "i20", & HW_ENT (HW_H_UINT
), 0, 20,
532 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX
)|(1<<CGEN_OPERAND_UNSIGNED
)|(1<<CGEN_OPERAND_VIRTUAL
), { 0 } } },
533 /* dir8: 8 bit direct address */
534 { "dir8", & HW_ENT (HW_H_UINT
), 8, 8,
535 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED
), { 0 } } },
536 /* dir9: 9 bit direct address */
537 { "dir9", & HW_ENT (HW_H_UINT
), 8, 8,
538 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED
), { 0 } } },
539 /* dir10: 10 bit direct address */
540 { "dir10", & HW_ENT (HW_H_UINT
), 8, 8,
541 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED
), { 0 } } },
542 /* label9: 9 bit pc relative address */
543 { "label9", & HW_ENT (HW_H_IADDR
), 8, 8,
544 { 0, 0|(1<<CGEN_OPERAND_PCREL_ADDR
)|(1<<CGEN_OPERAND_SIGNED
), { 0 } } },
545 /* label12: 12 bit pc relative address */
546 { "label12", & HW_ENT (HW_H_IADDR
), 5, 11,
547 { 0, 0|(1<<CGEN_OPERAND_PCREL_ADDR
)|(1<<CGEN_OPERAND_SIGNED
), { 0 } } },
548 /* reglist_low_ld: 8 bit register mask for ldm */
549 { "reglist_low_ld", & HW_ENT (HW_H_UINT
), 8, 8,
550 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED
), { 0 } } },
551 /* reglist_hi_ld: 8 bit register mask for ldm */
552 { "reglist_hi_ld", & HW_ENT (HW_H_UINT
), 8, 8,
553 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED
), { 0 } } },
554 /* reglist_low_st: 8 bit register mask for ldm */
555 { "reglist_low_st", & HW_ENT (HW_H_UINT
), 8, 8,
556 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED
), { 0 } } },
557 /* reglist_hi_st: 8 bit register mask for ldm */
558 { "reglist_hi_st", & HW_ENT (HW_H_UINT
), 8, 8,
559 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED
), { 0 } } },
560 /* cc: condition codes */
561 { "cc", & HW_ENT (HW_H_UINT
), 4, 4,
562 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED
), { 0 } } },
563 /* ccc: coprocessor calc */
564 { "ccc", & HW_ENT (HW_H_UINT
), 0, 8,
565 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX
)|(1<<CGEN_OPERAND_UNSIGNED
), { 0 } } },
566 /* nbit: negative bit */
567 { "nbit", & HW_ENT (HW_H_NBIT
), 0, 0,
568 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY
), { 0 } } },
569 /* vbit: overflow bit */
570 { "vbit", & HW_ENT (HW_H_VBIT
), 0, 0,
571 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY
), { 0 } } },
573 { "zbit", & HW_ENT (HW_H_ZBIT
), 0, 0,
574 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY
), { 0 } } },
575 /* cbit: carry bit */
576 { "cbit", & HW_ENT (HW_H_CBIT
), 0, 0,
577 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY
), { 0 } } },
578 /* ibit: interrupt bit */
579 { "ibit", & HW_ENT (HW_H_IBIT
), 0, 0,
580 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY
), { 0 } } },
581 /* sbit: stack bit */
582 { "sbit", & HW_ENT (HW_H_SBIT
), 0, 0,
583 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY
), { 0 } } },
584 /* tbit: trace trap bit */
585 { "tbit", & HW_ENT (HW_H_TBIT
), 0, 0,
586 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY
), { 0 } } },
587 /* d0bit: division 0 bit */
588 { "d0bit", & HW_ENT (HW_H_D0BIT
), 0, 0,
589 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY
), { 0 } } },
590 /* d1bit: division 1 bit */
591 { "d1bit", & HW_ENT (HW_H_D1BIT
), 0, 0,
592 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY
), { 0 } } },
593 /* ccr: condition code bits */
594 { "ccr", & HW_ENT (HW_H_CCR
), 0, 0,
595 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY
), { 0 } } },
596 /* scr: system condition bits */
597 { "scr", & HW_ENT (HW_H_SCR
), 0, 0,
598 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY
), { 0 } } },
599 /* ilm: condition code bits */
600 { "ilm", & HW_ENT (HW_H_ILM
), 0, 0,
601 { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY
), { 0 } } },
604 /* Operand references. */
606 #define INPUT CGEN_OPERAND_INSTANCE_INPUT
607 #define OUTPUT CGEN_OPERAND_INSTANCE_OUTPUT
608 #define COND_REF CGEN_OPERAND_INSTANCE_COND_REF
610 static const CGEN_OPERAND_INSTANCE fmt_add_ops
[] = {
611 { INPUT
, "Ri", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RI
), 0, 0 },
612 { INPUT
, "Rj", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RJ
), 0, 0 },
613 { OUTPUT
, "vbit", & HW_ENT (HW_H_VBIT
), CGEN_MODE_BI
, 0, 0, 0 },
614 { OUTPUT
, "cbit", & HW_ENT (HW_H_CBIT
), CGEN_MODE_BI
, 0, 0, 0 },
615 { OUTPUT
, "Ri", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RI
), 0, 0 },
616 { OUTPUT
, "zbit", & HW_ENT (HW_H_ZBIT
), CGEN_MODE_BI
, 0, 0, 0 },
617 { OUTPUT
, "nbit", & HW_ENT (HW_H_NBIT
), CGEN_MODE_BI
, 0, 0, 0 },
621 static const CGEN_OPERAND_INSTANCE fmt_addi_ops
[] = {
622 { INPUT
, "Ri", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RI
), 0, 0 },
623 { INPUT
, "u4", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (U4
), 0, 0 },
624 { OUTPUT
, "vbit", & HW_ENT (HW_H_VBIT
), CGEN_MODE_BI
, 0, 0, 0 },
625 { OUTPUT
, "cbit", & HW_ENT (HW_H_CBIT
), CGEN_MODE_BI
, 0, 0, 0 },
626 { OUTPUT
, "Ri", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RI
), 0, 0 },
627 { OUTPUT
, "zbit", & HW_ENT (HW_H_ZBIT
), CGEN_MODE_BI
, 0, 0, 0 },
628 { OUTPUT
, "nbit", & HW_ENT (HW_H_NBIT
), CGEN_MODE_BI
, 0, 0, 0 },
632 static const CGEN_OPERAND_INSTANCE fmt_add2_ops
[] = {
633 { INPUT
, "Ri", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RI
), 0, 0 },
634 { INPUT
, "m4", & HW_ENT (HW_H_SINT
), CGEN_MODE_SI
, & OP_ENT (M4
), 0, 0 },
635 { OUTPUT
, "vbit", & HW_ENT (HW_H_VBIT
), CGEN_MODE_BI
, 0, 0, 0 },
636 { OUTPUT
, "cbit", & HW_ENT (HW_H_CBIT
), CGEN_MODE_BI
, 0, 0, 0 },
637 { OUTPUT
, "Ri", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RI
), 0, 0 },
638 { OUTPUT
, "zbit", & HW_ENT (HW_H_ZBIT
), CGEN_MODE_BI
, 0, 0, 0 },
639 { OUTPUT
, "nbit", & HW_ENT (HW_H_NBIT
), CGEN_MODE_BI
, 0, 0, 0 },
643 static const CGEN_OPERAND_INSTANCE fmt_addc_ops
[] = {
644 { INPUT
, "Ri", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RI
), 0, 0 },
645 { INPUT
, "Rj", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RJ
), 0, 0 },
646 { INPUT
, "cbit", & HW_ENT (HW_H_CBIT
), CGEN_MODE_BI
, 0, 0, 0 },
647 { OUTPUT
, "vbit", & HW_ENT (HW_H_VBIT
), CGEN_MODE_BI
, 0, 0, 0 },
648 { OUTPUT
, "cbit", & HW_ENT (HW_H_CBIT
), CGEN_MODE_BI
, 0, 0, 0 },
649 { OUTPUT
, "Ri", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RI
), 0, 0 },
650 { OUTPUT
, "zbit", & HW_ENT (HW_H_ZBIT
), CGEN_MODE_BI
, 0, 0, 0 },
651 { OUTPUT
, "nbit", & HW_ENT (HW_H_NBIT
), CGEN_MODE_BI
, 0, 0, 0 },
655 static const CGEN_OPERAND_INSTANCE fmt_addn_ops
[] = {
656 { INPUT
, "Ri", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RI
), 0, 0 },
657 { INPUT
, "Rj", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RJ
), 0, 0 },
658 { OUTPUT
, "Ri", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RI
), 0, 0 },
662 static const CGEN_OPERAND_INSTANCE fmt_addni_ops
[] = {
663 { INPUT
, "Ri", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RI
), 0, 0 },
664 { INPUT
, "u4", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (U4
), 0, 0 },
665 { OUTPUT
, "Ri", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RI
), 0, 0 },
669 static const CGEN_OPERAND_INSTANCE fmt_addn2_ops
[] = {
670 { INPUT
, "Ri", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RI
), 0, 0 },
671 { INPUT
, "m4", & HW_ENT (HW_H_SINT
), CGEN_MODE_SI
, & OP_ENT (M4
), 0, 0 },
672 { OUTPUT
, "Ri", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RI
), 0, 0 },
676 static const CGEN_OPERAND_INSTANCE fmt_cmp_ops
[] = {
677 { INPUT
, "Ri", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RI
), 0, 0 },
678 { INPUT
, "Rj", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RJ
), 0, 0 },
679 { OUTPUT
, "vbit", & HW_ENT (HW_H_VBIT
), CGEN_MODE_BI
, 0, 0, 0 },
680 { OUTPUT
, "cbit", & HW_ENT (HW_H_CBIT
), CGEN_MODE_BI
, 0, 0, 0 },
681 { OUTPUT
, "zbit", & HW_ENT (HW_H_ZBIT
), CGEN_MODE_BI
, 0, 0, 0 },
682 { OUTPUT
, "nbit", & HW_ENT (HW_H_NBIT
), CGEN_MODE_BI
, 0, 0, 0 },
686 static const CGEN_OPERAND_INSTANCE fmt_cmpi_ops
[] = {
687 { INPUT
, "Ri", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RI
), 0, 0 },
688 { INPUT
, "u4", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (U4
), 0, 0 },
689 { OUTPUT
, "vbit", & HW_ENT (HW_H_VBIT
), CGEN_MODE_BI
, 0, 0, 0 },
690 { OUTPUT
, "cbit", & HW_ENT (HW_H_CBIT
), CGEN_MODE_BI
, 0, 0, 0 },
691 { OUTPUT
, "zbit", & HW_ENT (HW_H_ZBIT
), CGEN_MODE_BI
, 0, 0, 0 },
692 { OUTPUT
, "nbit", & HW_ENT (HW_H_NBIT
), CGEN_MODE_BI
, 0, 0, 0 },
696 static const CGEN_OPERAND_INSTANCE fmt_cmp2_ops
[] = {
697 { INPUT
, "Ri", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RI
), 0, 0 },
698 { INPUT
, "m4", & HW_ENT (HW_H_SINT
), CGEN_MODE_SI
, & OP_ENT (M4
), 0, 0 },
699 { OUTPUT
, "vbit", & HW_ENT (HW_H_VBIT
), CGEN_MODE_BI
, 0, 0, 0 },
700 { OUTPUT
, "cbit", & HW_ENT (HW_H_CBIT
), CGEN_MODE_BI
, 0, 0, 0 },
701 { OUTPUT
, "zbit", & HW_ENT (HW_H_ZBIT
), CGEN_MODE_BI
, 0, 0, 0 },
702 { OUTPUT
, "nbit", & HW_ENT (HW_H_NBIT
), CGEN_MODE_BI
, 0, 0, 0 },
706 static const CGEN_OPERAND_INSTANCE fmt_and_ops
[] = {
707 { INPUT
, "Ri", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RI
), 0, 0 },
708 { INPUT
, "Rj", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RJ
), 0, 0 },
709 { OUTPUT
, "Ri", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RI
), 0, 0 },
710 { OUTPUT
, "zbit", & HW_ENT (HW_H_ZBIT
), CGEN_MODE_BI
, 0, 0, 0 },
711 { OUTPUT
, "nbit", & HW_ENT (HW_H_NBIT
), CGEN_MODE_BI
, 0, 0, 0 },
715 static const CGEN_OPERAND_INSTANCE fmt_andm_ops
[] = {
716 { INPUT
, "Ri", & HW_ENT (HW_H_GR
), CGEN_MODE_USI
, & OP_ENT (RI
), 0, 0 },
717 { INPUT
, "h_memory_Ri", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
718 { INPUT
, "Rj", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RJ
), 0, 0 },
719 { OUTPUT
, "zbit", & HW_ENT (HW_H_ZBIT
), CGEN_MODE_BI
, 0, 0, 0 },
720 { OUTPUT
, "nbit", & HW_ENT (HW_H_NBIT
), CGEN_MODE_BI
, 0, 0, 0 },
721 { OUTPUT
, "h_memory_Ri", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
725 static const CGEN_OPERAND_INSTANCE fmt_andh_ops
[] = {
726 { INPUT
, "Ri", & HW_ENT (HW_H_GR
), CGEN_MODE_USI
, & OP_ENT (RI
), 0, 0 },
727 { INPUT
, "h_memory_Ri", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_HI
, 0, 0, 0 },
728 { INPUT
, "Rj", & HW_ENT (HW_H_GR
), CGEN_MODE_HI
, & OP_ENT (RJ
), 0, 0 },
729 { OUTPUT
, "zbit", & HW_ENT (HW_H_ZBIT
), CGEN_MODE_BI
, 0, 0, 0 },
730 { OUTPUT
, "nbit", & HW_ENT (HW_H_NBIT
), CGEN_MODE_BI
, 0, 0, 0 },
731 { OUTPUT
, "h_memory_Ri", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_HI
, 0, 0, 0 },
735 static const CGEN_OPERAND_INSTANCE fmt_andb_ops
[] = {
736 { INPUT
, "Ri", & HW_ENT (HW_H_GR
), CGEN_MODE_USI
, & OP_ENT (RI
), 0, 0 },
737 { INPUT
, "h_memory_Ri", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_QI
, 0, 0, 0 },
738 { INPUT
, "Rj", & HW_ENT (HW_H_GR
), CGEN_MODE_QI
, & OP_ENT (RJ
), 0, 0 },
739 { OUTPUT
, "zbit", & HW_ENT (HW_H_ZBIT
), CGEN_MODE_BI
, 0, 0, 0 },
740 { OUTPUT
, "nbit", & HW_ENT (HW_H_NBIT
), CGEN_MODE_BI
, 0, 0, 0 },
741 { OUTPUT
, "h_memory_Ri", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_QI
, 0, 0, 0 },
745 static const CGEN_OPERAND_INSTANCE fmt_bandl_ops
[] = {
746 { INPUT
, "Ri", & HW_ENT (HW_H_GR
), CGEN_MODE_USI
, & OP_ENT (RI
), 0, 0 },
747 { INPUT
, "u4", & HW_ENT (HW_H_UINT
), CGEN_MODE_QI
, & OP_ENT (U4
), 0, 0 },
748 { INPUT
, "h_memory_Ri", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_QI
, 0, 0, 0 },
749 { OUTPUT
, "h_memory_Ri", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_QI
, 0, 0, 0 },
753 static const CGEN_OPERAND_INSTANCE fmt_btstl_ops
[] = {
754 { INPUT
, "u4", & HW_ENT (HW_H_UINT
), CGEN_MODE_QI
, & OP_ENT (U4
), 0, 0 },
755 { INPUT
, "Ri", & HW_ENT (HW_H_GR
), CGEN_MODE_USI
, & OP_ENT (RI
), 0, 0 },
756 { INPUT
, "h_memory_Ri", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_QI
, 0, 0, 0 },
757 { OUTPUT
, "zbit", & HW_ENT (HW_H_ZBIT
), CGEN_MODE_BI
, 0, 0, 0 },
758 { OUTPUT
, "nbit", & HW_ENT (HW_H_NBIT
), CGEN_MODE_BI
, 0, 0, 0 },
762 static const CGEN_OPERAND_INSTANCE fmt_mul_ops
[] = {
763 { INPUT
, "Rj", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RJ
), 0, 0 },
764 { INPUT
, "Ri", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RI
), 0, 0 },
765 { INPUT
, "h_dr_5", & HW_ENT (HW_H_DR
), CGEN_MODE_SI
, 0, 5, 0 },
766 { OUTPUT
, "h_dr_5", & HW_ENT (HW_H_DR
), CGEN_MODE_SI
, 0, 5, 0 },
767 { OUTPUT
, "h_dr_4", & HW_ENT (HW_H_DR
), CGEN_MODE_SI
, 0, 4, 0 },
768 { OUTPUT
, "nbit", & HW_ENT (HW_H_NBIT
), CGEN_MODE_BI
, 0, 0, 0 },
769 { OUTPUT
, "zbit", & HW_ENT (HW_H_ZBIT
), CGEN_MODE_BI
, 0, 0, 0 },
770 { OUTPUT
, "vbit", & HW_ENT (HW_H_VBIT
), CGEN_MODE_BI
, 0, 0, 0 },
774 static const CGEN_OPERAND_INSTANCE fmt_mulu_ops
[] = {
775 { INPUT
, "Rj", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RJ
), 0, 0 },
776 { INPUT
, "Ri", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RI
), 0, 0 },
777 { INPUT
, "h_dr_4", & HW_ENT (HW_H_DR
), CGEN_MODE_SI
, 0, 4, 0 },
778 { INPUT
, "h_dr_5", & HW_ENT (HW_H_DR
), CGEN_MODE_SI
, 0, 5, 0 },
779 { OUTPUT
, "h_dr_5", & HW_ENT (HW_H_DR
), CGEN_MODE_SI
, 0, 5, 0 },
780 { OUTPUT
, "h_dr_4", & HW_ENT (HW_H_DR
), CGEN_MODE_SI
, 0, 4, 0 },
781 { OUTPUT
, "nbit", & HW_ENT (HW_H_NBIT
), CGEN_MODE_BI
, 0, 0, 0 },
782 { OUTPUT
, "zbit", & HW_ENT (HW_H_ZBIT
), CGEN_MODE_BI
, 0, 0, 0 },
783 { OUTPUT
, "vbit", & HW_ENT (HW_H_VBIT
), CGEN_MODE_BI
, 0, 0, 0 },
787 static const CGEN_OPERAND_INSTANCE fmt_mulh_ops
[] = {
788 { INPUT
, "Rj", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RJ
), 0, 0 },
789 { INPUT
, "Ri", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RI
), 0, 0 },
790 { INPUT
, "h_dr_5", & HW_ENT (HW_H_DR
), CGEN_MODE_SI
, 0, 5, 0 },
791 { OUTPUT
, "h_dr_5", & HW_ENT (HW_H_DR
), CGEN_MODE_SI
, 0, 5, 0 },
792 { OUTPUT
, "nbit", & HW_ENT (HW_H_NBIT
), CGEN_MODE_BI
, 0, 0, 0 },
793 { OUTPUT
, "zbit", & HW_ENT (HW_H_ZBIT
), CGEN_MODE_BI
, 0, 0, 0 },
797 static const CGEN_OPERAND_INSTANCE fmt_div0s_ops
[] = {
798 { INPUT
, "h_dr_5", & HW_ENT (HW_H_DR
), CGEN_MODE_SI
, 0, 5, 0 },
799 { INPUT
, "d0bit", & HW_ENT (HW_H_D0BIT
), CGEN_MODE_BI
, 0, 0, 0 },
800 { INPUT
, "Ri", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RI
), 0, 0 },
801 { OUTPUT
, "d0bit", & HW_ENT (HW_H_D0BIT
), CGEN_MODE_BI
, 0, 0, 0 },
802 { OUTPUT
, "d1bit", & HW_ENT (HW_H_D1BIT
), CGEN_MODE_BI
, 0, 0, 0 },
803 { OUTPUT
, "h_dr_4", & HW_ENT (HW_H_DR
), CGEN_MODE_SI
, 0, 4, COND_REF
},
807 static const CGEN_OPERAND_INSTANCE fmt_div0u_ops
[] = {
808 { OUTPUT
, "d0bit", & HW_ENT (HW_H_D0BIT
), CGEN_MODE_BI
, 0, 0, 0 },
809 { OUTPUT
, "d1bit", & HW_ENT (HW_H_D1BIT
), CGEN_MODE_BI
, 0, 0, 0 },
810 { OUTPUT
, "h_dr_4", & HW_ENT (HW_H_DR
), CGEN_MODE_SI
, 0, 4, 0 },
814 static const CGEN_OPERAND_INSTANCE fmt_div1_ops
[] = {
815 { INPUT
, "h_dr_4", & HW_ENT (HW_H_DR
), CGEN_MODE_SI
, 0, 4, 0 },
816 { INPUT
, "h_dr_5", & HW_ENT (HW_H_DR
), CGEN_MODE_SI
, 0, 5, 0 },
817 { INPUT
, "d1bit", & HW_ENT (HW_H_D1BIT
), CGEN_MODE_BI
, 0, 0, 0 },
818 { INPUT
, "Ri", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RI
), 0, COND_REF
},
819 { INPUT
, "cbit", & HW_ENT (HW_H_CBIT
), CGEN_MODE_BI
, 0, 0, COND_REF
},
820 { INPUT
, "d0bit", & HW_ENT (HW_H_D0BIT
), CGEN_MODE_BI
, 0, 0, 0 },
821 { OUTPUT
, "h_dr_4", & HW_ENT (HW_H_DR
), CGEN_MODE_SI
, 0, 4, 0 },
822 { OUTPUT
, "h_dr_5", & HW_ENT (HW_H_DR
), CGEN_MODE_SI
, 0, 5, 0 },
823 { OUTPUT
, "cbit", & HW_ENT (HW_H_CBIT
), CGEN_MODE_BI
, 0, 0, COND_REF
},
824 { OUTPUT
, "zbit", & HW_ENT (HW_H_ZBIT
), CGEN_MODE_BI
, 0, 0, 0 },
828 static const CGEN_OPERAND_INSTANCE fmt_div2_ops
[] = {
829 { INPUT
, "d1bit", & HW_ENT (HW_H_D1BIT
), CGEN_MODE_BI
, 0, 0, 0 },
830 { INPUT
, "h_dr_4", & HW_ENT (HW_H_DR
), CGEN_MODE_SI
, 0, 4, COND_REF
},
831 { INPUT
, "Ri", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RI
), 0, COND_REF
},
832 { INPUT
, "cbit", & HW_ENT (HW_H_CBIT
), CGEN_MODE_BI
, 0, 0, COND_REF
},
833 { OUTPUT
, "cbit", & HW_ENT (HW_H_CBIT
), CGEN_MODE_BI
, 0, 0, COND_REF
},
834 { OUTPUT
, "zbit", & HW_ENT (HW_H_ZBIT
), CGEN_MODE_BI
, 0, 0, COND_REF
},
835 { OUTPUT
, "h_dr_4", & HW_ENT (HW_H_DR
), CGEN_MODE_SI
, 0, 4, COND_REF
},
839 static const CGEN_OPERAND_INSTANCE fmt_div3_ops
[] = {
840 { INPUT
, "zbit", & HW_ENT (HW_H_ZBIT
), CGEN_MODE_BI
, 0, 0, 0 },
841 { INPUT
, "h_dr_5", & HW_ENT (HW_H_DR
), CGEN_MODE_SI
, 0, 5, COND_REF
},
842 { OUTPUT
, "h_dr_5", & HW_ENT (HW_H_DR
), CGEN_MODE_SI
, 0, 5, COND_REF
},
846 static const CGEN_OPERAND_INSTANCE fmt_div4s_ops
[] = {
847 { INPUT
, "d1bit", & HW_ENT (HW_H_D1BIT
), CGEN_MODE_BI
, 0, 0, 0 },
848 { INPUT
, "h_dr_5", & HW_ENT (HW_H_DR
), CGEN_MODE_SI
, 0, 5, COND_REF
},
849 { OUTPUT
, "h_dr_5", & HW_ENT (HW_H_DR
), CGEN_MODE_SI
, 0, 5, COND_REF
},
853 static const CGEN_OPERAND_INSTANCE fmt_lsl_ops
[] = {
854 { INPUT
, "Rj", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RJ
), 0, 0 },
855 { INPUT
, "Ri", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RI
), 0, COND_REF
},
856 { OUTPUT
, "cbit", & HW_ENT (HW_H_CBIT
), CGEN_MODE_BI
, 0, 0, COND_REF
},
857 { OUTPUT
, "Ri", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RI
), 0, COND_REF
},
858 { OUTPUT
, "nbit", & HW_ENT (HW_H_NBIT
), CGEN_MODE_BI
, 0, 0, 0 },
859 { OUTPUT
, "zbit", & HW_ENT (HW_H_ZBIT
), CGEN_MODE_BI
, 0, 0, 0 },
863 static const CGEN_OPERAND_INSTANCE fmt_lsli_ops
[] = {
864 { INPUT
, "u4", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (U4
), 0, 0 },
865 { INPUT
, "Ri", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RI
), 0, COND_REF
},
866 { OUTPUT
, "cbit", & HW_ENT (HW_H_CBIT
), CGEN_MODE_BI
, 0, 0, COND_REF
},
867 { OUTPUT
, "Ri", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RI
), 0, COND_REF
},
868 { OUTPUT
, "nbit", & HW_ENT (HW_H_NBIT
), CGEN_MODE_BI
, 0, 0, 0 },
869 { OUTPUT
, "zbit", & HW_ENT (HW_H_ZBIT
), CGEN_MODE_BI
, 0, 0, 0 },
873 static const CGEN_OPERAND_INSTANCE fmt_ldi8_ops
[] = {
874 { INPUT
, "i8", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (I8
), 0, 0 },
875 { OUTPUT
, "Ri", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RI
), 0, 0 },
879 static const CGEN_OPERAND_INSTANCE fmt_ldi20_ops
[] = {
880 { INPUT
, "i20", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (I20
), 0, 0 },
881 { OUTPUT
, "Ri", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RI
), 0, 0 },
885 static const CGEN_OPERAND_INSTANCE fmt_ldi32_ops
[] = {
886 { INPUT
, "i32", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (I32
), 0, 0 },
887 { OUTPUT
, "Ri", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RI
), 0, 0 },
891 static const CGEN_OPERAND_INSTANCE fmt_ld_ops
[] = {
892 { INPUT
, "Rj", & HW_ENT (HW_H_GR
), CGEN_MODE_USI
, & OP_ENT (RJ
), 0, 0 },
893 { INPUT
, "h_memory_Rj", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
894 { OUTPUT
, "Ri", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RI
), 0, 0 },
898 static const CGEN_OPERAND_INSTANCE fmt_lduh_ops
[] = {
899 { INPUT
, "Rj", & HW_ENT (HW_H_GR
), CGEN_MODE_USI
, & OP_ENT (RJ
), 0, 0 },
900 { INPUT
, "h_memory_Rj", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_UHI
, 0, 0, 0 },
901 { OUTPUT
, "Ri", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RI
), 0, 0 },
905 static const CGEN_OPERAND_INSTANCE fmt_ldub_ops
[] = {
906 { INPUT
, "Rj", & HW_ENT (HW_H_GR
), CGEN_MODE_USI
, & OP_ENT (RJ
), 0, 0 },
907 { INPUT
, "h_memory_Rj", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_UQI
, 0, 0, 0 },
908 { OUTPUT
, "Ri", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RI
), 0, 0 },
912 static const CGEN_OPERAND_INSTANCE fmt_ldr13_ops
[] = {
913 { INPUT
, "Rj", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RJ
), 0, 0 },
914 { INPUT
, "h_gr_13", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 13, 0 },
915 { INPUT
, "h_memory_add__VM_Rj_reg__VM_h_gr_13", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
916 { OUTPUT
, "Ri", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RI
), 0, 0 },
920 static const CGEN_OPERAND_INSTANCE fmt_ldr13uh_ops
[] = {
921 { INPUT
, "Rj", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RJ
), 0, 0 },
922 { INPUT
, "h_gr_13", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 13, 0 },
923 { INPUT
, "h_memory_add__VM_Rj_reg__VM_h_gr_13", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_UHI
, 0, 0, 0 },
924 { OUTPUT
, "Ri", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RI
), 0, 0 },
928 static const CGEN_OPERAND_INSTANCE fmt_ldr13ub_ops
[] = {
929 { INPUT
, "Rj", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RJ
), 0, 0 },
930 { INPUT
, "h_gr_13", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 13, 0 },
931 { INPUT
, "h_memory_add__VM_Rj_reg__VM_h_gr_13", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_UQI
, 0, 0, 0 },
932 { OUTPUT
, "Ri", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RI
), 0, 0 },
936 static const CGEN_OPERAND_INSTANCE fmt_ldr14_ops
[] = {
937 { INPUT
, "disp10", & HW_ENT (HW_H_SINT
), CGEN_MODE_SI
, & OP_ENT (DISP10
), 0, 0 },
938 { INPUT
, "h_gr_14", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 14, 0 },
939 { INPUT
, "h_memory_add__VM_disp10_reg__VM_h_gr_14", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
940 { OUTPUT
, "Ri", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RI
), 0, 0 },
944 static const CGEN_OPERAND_INSTANCE fmt_ldr14uh_ops
[] = {
945 { INPUT
, "disp9", & HW_ENT (HW_H_SINT
), CGEN_MODE_SI
, & OP_ENT (DISP9
), 0, 0 },
946 { INPUT
, "h_gr_14", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 14, 0 },
947 { INPUT
, "h_memory_add__VM_disp9_reg__VM_h_gr_14", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_UHI
, 0, 0, 0 },
948 { OUTPUT
, "Ri", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RI
), 0, 0 },
952 static const CGEN_OPERAND_INSTANCE fmt_ldr14ub_ops
[] = {
953 { INPUT
, "disp8", & HW_ENT (HW_H_SINT
), CGEN_MODE_SI
, & OP_ENT (DISP8
), 0, 0 },
954 { INPUT
, "h_gr_14", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 14, 0 },
955 { INPUT
, "h_memory_add__VM_disp8_reg__VM_h_gr_14", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_UQI
, 0, 0, 0 },
956 { OUTPUT
, "Ri", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RI
), 0, 0 },
960 static const CGEN_OPERAND_INSTANCE fmt_ldr15_ops
[] = {
961 { INPUT
, "udisp6", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (UDISP6
), 0, 0 },
962 { INPUT
, "h_gr_15", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 15, 0 },
963 { INPUT
, "h_memory_add__VM_udisp6_reg__VM_h_gr_15", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
964 { OUTPUT
, "Ri", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RI
), 0, 0 },
968 static const CGEN_OPERAND_INSTANCE fmt_ldr15gr_ops
[] = {
969 { INPUT
, "h_gr_15", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 15, 0 },
970 { INPUT
, "h_memory_reg__VM_h_gr_15", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
971 { INPUT
, "f_Ri", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, 0, 0, COND_REF
},
972 { OUTPUT
, "Ri", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RI
), 0, 0 },
973 { OUTPUT
, "h_gr_15", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 15, COND_REF
},
977 static const CGEN_OPERAND_INSTANCE fmt_ldr15dr_ops
[] = {
978 { INPUT
, "h_gr_15", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 15, 0 },
979 { INPUT
, "h_memory_reg__VM_h_gr_15", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
980 { OUTPUT
, "h_gr_15", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 15, 0 },
981 { OUTPUT
, "Rs2", & HW_ENT (HW_H_DR
), CGEN_MODE_SI
, & OP_ENT (RS2
), 0, 0 },
985 static const CGEN_OPERAND_INSTANCE fmt_ldr15ps_ops
[] = {
986 { INPUT
, "h_gr_15", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 15, 0 },
987 { INPUT
, "h_memory_reg__VM_h_gr_15", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
988 { OUTPUT
, "ps", & HW_ENT (HW_H_PS
), CGEN_MODE_USI
, 0, 0, 0 },
989 { OUTPUT
, "h_gr_15", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 15, 0 },
993 static const CGEN_OPERAND_INSTANCE fmt_st_ops
[] = {
994 { INPUT
, "Rj", & HW_ENT (HW_H_GR
), CGEN_MODE_USI
, & OP_ENT (RJ
), 0, 0 },
995 { INPUT
, "Ri", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RI
), 0, 0 },
996 { OUTPUT
, "h_memory_Rj", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1000 static const CGEN_OPERAND_INSTANCE fmt_sth_ops
[] = {
1001 { INPUT
, "Rj", & HW_ENT (HW_H_GR
), CGEN_MODE_USI
, & OP_ENT (RJ
), 0, 0 },
1002 { INPUT
, "Ri", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RI
), 0, 0 },
1003 { OUTPUT
, "h_memory_Rj", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_HI
, 0, 0, 0 },
1007 static const CGEN_OPERAND_INSTANCE fmt_stb_ops
[] = {
1008 { INPUT
, "Rj", & HW_ENT (HW_H_GR
), CGEN_MODE_USI
, & OP_ENT (RJ
), 0, 0 },
1009 { INPUT
, "Ri", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RI
), 0, 0 },
1010 { OUTPUT
, "h_memory_Rj", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_QI
, 0, 0, 0 },
1014 static const CGEN_OPERAND_INSTANCE fmt_str13_ops
[] = {
1015 { INPUT
, "Rj", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RJ
), 0, 0 },
1016 { INPUT
, "h_gr_13", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 13, 0 },
1017 { INPUT
, "Ri", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RI
), 0, 0 },
1018 { OUTPUT
, "h_memory_add__VM_Rj_reg__VM_h_gr_13", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1022 static const CGEN_OPERAND_INSTANCE fmt_str13h_ops
[] = {
1023 { INPUT
, "Rj", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RJ
), 0, 0 },
1024 { INPUT
, "h_gr_13", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 13, 0 },
1025 { INPUT
, "Ri", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RI
), 0, 0 },
1026 { OUTPUT
, "h_memory_add__VM_Rj_reg__VM_h_gr_13", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_HI
, 0, 0, 0 },
1030 static const CGEN_OPERAND_INSTANCE fmt_str13b_ops
[] = {
1031 { INPUT
, "Rj", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RJ
), 0, 0 },
1032 { INPUT
, "h_gr_13", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 13, 0 },
1033 { INPUT
, "Ri", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RI
), 0, 0 },
1034 { OUTPUT
, "h_memory_add__VM_Rj_reg__VM_h_gr_13", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_QI
, 0, 0, 0 },
1038 static const CGEN_OPERAND_INSTANCE fmt_str14_ops
[] = {
1039 { INPUT
, "disp10", & HW_ENT (HW_H_SINT
), CGEN_MODE_SI
, & OP_ENT (DISP10
), 0, 0 },
1040 { INPUT
, "h_gr_14", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 14, 0 },
1041 { INPUT
, "Ri", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RI
), 0, 0 },
1042 { OUTPUT
, "h_memory_add__VM_disp10_reg__VM_h_gr_14", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1046 static const CGEN_OPERAND_INSTANCE fmt_str14h_ops
[] = {
1047 { INPUT
, "disp9", & HW_ENT (HW_H_SINT
), CGEN_MODE_SI
, & OP_ENT (DISP9
), 0, 0 },
1048 { INPUT
, "h_gr_14", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 14, 0 },
1049 { INPUT
, "Ri", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RI
), 0, 0 },
1050 { OUTPUT
, "h_memory_add__VM_disp9_reg__VM_h_gr_14", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_HI
, 0, 0, 0 },
1054 static const CGEN_OPERAND_INSTANCE fmt_str14b_ops
[] = {
1055 { INPUT
, "disp8", & HW_ENT (HW_H_SINT
), CGEN_MODE_SI
, & OP_ENT (DISP8
), 0, 0 },
1056 { INPUT
, "h_gr_14", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 14, 0 },
1057 { INPUT
, "Ri", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RI
), 0, 0 },
1058 { OUTPUT
, "h_memory_add__VM_disp8_reg__VM_h_gr_14", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_QI
, 0, 0, 0 },
1062 static const CGEN_OPERAND_INSTANCE fmt_str15_ops
[] = {
1063 { INPUT
, "h_gr_15", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 15, 0 },
1064 { INPUT
, "udisp6", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (UDISP6
), 0, 0 },
1065 { INPUT
, "Ri", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RI
), 0, 0 },
1066 { OUTPUT
, "h_memory_add__VM_reg__VM_h_gr_15_udisp6", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1070 static const CGEN_OPERAND_INSTANCE fmt_str15gr_ops
[] = {
1071 { INPUT
, "Ri", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RI
), 0, 0 },
1072 { INPUT
, "h_gr_15", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 15, 0 },
1073 { OUTPUT
, "h_gr_15", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 15, 0 },
1074 { OUTPUT
, "h_memory_reg__VM_h_gr_15", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1078 static const CGEN_OPERAND_INSTANCE fmt_str15dr_ops
[] = {
1079 { INPUT
, "Rs2", & HW_ENT (HW_H_DR
), CGEN_MODE_SI
, & OP_ENT (RS2
), 0, 0 },
1080 { INPUT
, "h_gr_15", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 15, 0 },
1081 { OUTPUT
, "h_gr_15", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 15, 0 },
1082 { OUTPUT
, "h_memory_reg__VM_h_gr_15", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1086 static const CGEN_OPERAND_INSTANCE fmt_str15ps_ops
[] = {
1087 { INPUT
, "h_gr_15", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 15, 0 },
1088 { INPUT
, "ps", & HW_ENT (HW_H_PS
), CGEN_MODE_USI
, 0, 0, 0 },
1089 { OUTPUT
, "h_gr_15", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 15, 0 },
1090 { OUTPUT
, "h_memory_reg__VM_h_gr_15", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1094 static const CGEN_OPERAND_INSTANCE fmt_mov_ops
[] = {
1095 { INPUT
, "Rj", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RJ
), 0, 0 },
1096 { OUTPUT
, "Ri", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RI
), 0, 0 },
1100 static const CGEN_OPERAND_INSTANCE fmt_movdr_ops
[] = {
1101 { INPUT
, "Rs1", & HW_ENT (HW_H_DR
), CGEN_MODE_SI
, & OP_ENT (RS1
), 0, 0 },
1102 { OUTPUT
, "Ri", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RI
), 0, 0 },
1106 static const CGEN_OPERAND_INSTANCE fmt_movps_ops
[] = {
1107 { INPUT
, "ps", & HW_ENT (HW_H_PS
), CGEN_MODE_USI
, 0, 0, 0 },
1108 { OUTPUT
, "Ri", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RI
), 0, 0 },
1112 static const CGEN_OPERAND_INSTANCE fmt_mov2dr_ops
[] = {
1113 { INPUT
, "Ri", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RI
), 0, 0 },
1114 { OUTPUT
, "Rs1", & HW_ENT (HW_H_DR
), CGEN_MODE_SI
, & OP_ENT (RS1
), 0, 0 },
1118 static const CGEN_OPERAND_INSTANCE fmt_mov2ps_ops
[] = {
1119 { INPUT
, "Ri", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RI
), 0, 0 },
1120 { OUTPUT
, "ps", & HW_ENT (HW_H_PS
), CGEN_MODE_USI
, 0, 0, 0 },
1124 static const CGEN_OPERAND_INSTANCE fmt_jmp_ops
[] = {
1125 { INPUT
, "Ri", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RI
), 0, 0 },
1126 { OUTPUT
, "pc", & HW_ENT (HW_H_PC
), CGEN_MODE_USI
, 0, 0, 0 },
1130 static const CGEN_OPERAND_INSTANCE fmt_callr_ops
[] = {
1131 { INPUT
, "pc", & HW_ENT (HW_H_PC
), CGEN_MODE_USI
, 0, 0, 0 },
1132 { INPUT
, "Ri", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RI
), 0, 0 },
1133 { OUTPUT
, "h_dr_1", & HW_ENT (HW_H_DR
), CGEN_MODE_SI
, 0, 1, 0 },
1134 { OUTPUT
, "pc", & HW_ENT (HW_H_PC
), CGEN_MODE_USI
, 0, 0, 0 },
1138 static const CGEN_OPERAND_INSTANCE fmt_call_ops
[] = {
1139 { INPUT
, "pc", & HW_ENT (HW_H_PC
), CGEN_MODE_USI
, 0, 0, 0 },
1140 { INPUT
, "label12", & HW_ENT (HW_H_IADDR
), CGEN_MODE_USI
, & OP_ENT (LABEL12
), 0, 0 },
1141 { OUTPUT
, "h_dr_1", & HW_ENT (HW_H_DR
), CGEN_MODE_SI
, 0, 1, 0 },
1142 { OUTPUT
, "pc", & HW_ENT (HW_H_PC
), CGEN_MODE_USI
, 0, 0, 0 },
1146 static const CGEN_OPERAND_INSTANCE fmt_ret_ops
[] = {
1147 { INPUT
, "h_dr_1", & HW_ENT (HW_H_DR
), CGEN_MODE_SI
, 0, 1, 0 },
1148 { OUTPUT
, "pc", & HW_ENT (HW_H_PC
), CGEN_MODE_USI
, 0, 0, 0 },
1152 static const CGEN_OPERAND_INSTANCE fmt_int_ops
[] = {
1153 { INPUT
, "pc", & HW_ENT (HW_H_PC
), CGEN_MODE_SI
, 0, 0, 0 },
1154 { INPUT
, "u8", & HW_ENT (HW_H_UINT
), CGEN_MODE_SI
, & OP_ENT (U8
), 0, 0 },
1155 { OUTPUT
, "h_dr_2", & HW_ENT (HW_H_DR
), CGEN_MODE_SI
, 0, 2, 0 },
1156 { OUTPUT
, "ibit", & HW_ENT (HW_H_IBIT
), CGEN_MODE_BI
, 0, 0, 0 },
1157 { OUTPUT
, "sbit", & HW_ENT (HW_H_SBIT
), CGEN_MODE_BI
, 0, 0, 0 },
1158 { OUTPUT
, "pc", & HW_ENT (HW_H_PC
), CGEN_MODE_SI
, 0, 0, 0 },
1162 static const CGEN_OPERAND_INSTANCE fmt_inte_ops
[] = {
1163 { INPUT
, "pc", & HW_ENT (HW_H_PC
), CGEN_MODE_SI
, 0, 0, 0 },
1164 { OUTPUT
, "h_dr_2", & HW_ENT (HW_H_DR
), CGEN_MODE_SI
, 0, 2, 0 },
1165 { OUTPUT
, "ibit", & HW_ENT (HW_H_IBIT
), CGEN_MODE_BI
, 0, 0, 0 },
1166 { OUTPUT
, "ilm", & HW_ENT (HW_H_ILM
), CGEN_MODE_UQI
, 0, 0, 0 },
1167 { OUTPUT
, "pc", & HW_ENT (HW_H_PC
), CGEN_MODE_SI
, 0, 0, 0 },
1171 static const CGEN_OPERAND_INSTANCE fmt_reti_ops
[] = {
1172 { INPUT
, "sbit", & HW_ENT (HW_H_SBIT
), CGEN_MODE_BI
, 0, 0, 0 },
1173 { INPUT
, "h_dr_2", & HW_ENT (HW_H_DR
), CGEN_MODE_SI
, 0, 2, COND_REF
},
1174 { INPUT
, "h_memory_reg__VM_h_dr_2", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_USI
, 0, 0, COND_REF
},
1175 { INPUT
, "h_dr_3", & HW_ENT (HW_H_DR
), CGEN_MODE_SI
, 0, 3, COND_REF
},
1176 { INPUT
, "h_memory_reg__VM_h_dr_3", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_USI
, 0, 0, COND_REF
},
1177 { OUTPUT
, "pc", & HW_ENT (HW_H_PC
), CGEN_MODE_USI
, 0, 0, COND_REF
},
1178 { OUTPUT
, "h_dr_2", & HW_ENT (HW_H_DR
), CGEN_MODE_SI
, 0, 2, COND_REF
},
1179 { OUTPUT
, "ps", & HW_ENT (HW_H_PS
), CGEN_MODE_USI
, 0, 0, COND_REF
},
1180 { OUTPUT
, "h_dr_3", & HW_ENT (HW_H_DR
), CGEN_MODE_SI
, 0, 3, COND_REF
},
1184 static const CGEN_OPERAND_INSTANCE fmt_bra_ops
[] = {
1185 { INPUT
, "label9", & HW_ENT (HW_H_IADDR
), CGEN_MODE_USI
, & OP_ENT (LABEL9
), 0, COND_REF
},
1186 { OUTPUT
, "pc", & HW_ENT (HW_H_PC
), CGEN_MODE_USI
, 0, 0, COND_REF
},
1190 static const CGEN_OPERAND_INSTANCE fmt_beq_ops
[] = {
1191 { INPUT
, "zbit", & HW_ENT (HW_H_ZBIT
), CGEN_MODE_BI
, 0, 0, 0 },
1192 { INPUT
, "label9", & HW_ENT (HW_H_IADDR
), CGEN_MODE_USI
, & OP_ENT (LABEL9
), 0, COND_REF
},
1193 { OUTPUT
, "pc", & HW_ENT (HW_H_PC
), CGEN_MODE_USI
, 0, 0, COND_REF
},
1197 static const CGEN_OPERAND_INSTANCE fmt_bc_ops
[] = {
1198 { INPUT
, "cbit", & HW_ENT (HW_H_CBIT
), CGEN_MODE_BI
, 0, 0, 0 },
1199 { INPUT
, "label9", & HW_ENT (HW_H_IADDR
), CGEN_MODE_USI
, & OP_ENT (LABEL9
), 0, COND_REF
},
1200 { OUTPUT
, "pc", & HW_ENT (HW_H_PC
), CGEN_MODE_USI
, 0, 0, COND_REF
},
1204 static const CGEN_OPERAND_INSTANCE fmt_bn_ops
[] = {
1205 { INPUT
, "nbit", & HW_ENT (HW_H_NBIT
), CGEN_MODE_BI
, 0, 0, 0 },
1206 { INPUT
, "label9", & HW_ENT (HW_H_IADDR
), CGEN_MODE_USI
, & OP_ENT (LABEL9
), 0, COND_REF
},
1207 { OUTPUT
, "pc", & HW_ENT (HW_H_PC
), CGEN_MODE_USI
, 0, 0, COND_REF
},
1211 static const CGEN_OPERAND_INSTANCE fmt_bv_ops
[] = {
1212 { INPUT
, "vbit", & HW_ENT (HW_H_VBIT
), CGEN_MODE_BI
, 0, 0, 0 },
1213 { INPUT
, "label9", & HW_ENT (HW_H_IADDR
), CGEN_MODE_USI
, & OP_ENT (LABEL9
), 0, COND_REF
},
1214 { OUTPUT
, "pc", & HW_ENT (HW_H_PC
), CGEN_MODE_USI
, 0, 0, COND_REF
},
1218 static const CGEN_OPERAND_INSTANCE fmt_blt_ops
[] = {
1219 { INPUT
, "vbit", & HW_ENT (HW_H_VBIT
), CGEN_MODE_BI
, 0, 0, 0 },
1220 { INPUT
, "nbit", & HW_ENT (HW_H_NBIT
), CGEN_MODE_BI
, 0, 0, 0 },
1221 { INPUT
, "label9", & HW_ENT (HW_H_IADDR
), CGEN_MODE_USI
, & OP_ENT (LABEL9
), 0, COND_REF
},
1222 { OUTPUT
, "pc", & HW_ENT (HW_H_PC
), CGEN_MODE_USI
, 0, 0, COND_REF
},
1226 static const CGEN_OPERAND_INSTANCE fmt_ble_ops
[] = {
1227 { INPUT
, "vbit", & HW_ENT (HW_H_VBIT
), CGEN_MODE_BI
, 0, 0, 0 },
1228 { INPUT
, "nbit", & HW_ENT (HW_H_NBIT
), CGEN_MODE_BI
, 0, 0, 0 },
1229 { INPUT
, "zbit", & HW_ENT (HW_H_ZBIT
), CGEN_MODE_BI
, 0, 0, 0 },
1230 { INPUT
, "label9", & HW_ENT (HW_H_IADDR
), CGEN_MODE_USI
, & OP_ENT (LABEL9
), 0, COND_REF
},
1231 { OUTPUT
, "pc", & HW_ENT (HW_H_PC
), CGEN_MODE_USI
, 0, 0, COND_REF
},
1235 static const CGEN_OPERAND_INSTANCE fmt_bls_ops
[] = {
1236 { INPUT
, "cbit", & HW_ENT (HW_H_CBIT
), CGEN_MODE_BI
, 0, 0, 0 },
1237 { INPUT
, "zbit", & HW_ENT (HW_H_ZBIT
), CGEN_MODE_BI
, 0, 0, 0 },
1238 { INPUT
, "label9", & HW_ENT (HW_H_IADDR
), CGEN_MODE_USI
, & OP_ENT (LABEL9
), 0, COND_REF
},
1239 { OUTPUT
, "pc", & HW_ENT (HW_H_PC
), CGEN_MODE_USI
, 0, 0, COND_REF
},
1243 static const CGEN_OPERAND_INSTANCE fmt_dmovr13_ops
[] = {
1244 { INPUT
, "dir10", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (DIR10
), 0, 0 },
1245 { INPUT
, "h_gr_13", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 13, 0 },
1246 { OUTPUT
, "h_memory_dir10", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1250 static const CGEN_OPERAND_INSTANCE fmt_dmovr13h_ops
[] = {
1251 { INPUT
, "dir9", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (DIR9
), 0, 0 },
1252 { INPUT
, "h_gr_13", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 13, 0 },
1253 { OUTPUT
, "h_memory_dir9", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_HI
, 0, 0, 0 },
1257 static const CGEN_OPERAND_INSTANCE fmt_dmovr13b_ops
[] = {
1258 { INPUT
, "dir8", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (DIR8
), 0, 0 },
1259 { INPUT
, "h_gr_13", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 13, 0 },
1260 { OUTPUT
, "h_memory_dir8", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_QI
, 0, 0, 0 },
1264 static const CGEN_OPERAND_INSTANCE fmt_dmovr13pi_ops
[] = {
1265 { INPUT
, "dir10", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (DIR10
), 0, 0 },
1266 { INPUT
, "h_gr_13", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 13, 0 },
1267 { INPUT
, "h_memory_reg__VM_h_gr_13", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1268 { OUTPUT
, "h_memory_dir10", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1269 { OUTPUT
, "h_gr_13", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 13, 0 },
1273 static const CGEN_OPERAND_INSTANCE fmt_dmovr13pih_ops
[] = {
1274 { INPUT
, "dir9", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (DIR9
), 0, 0 },
1275 { INPUT
, "h_gr_13", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 13, 0 },
1276 { INPUT
, "h_memory_reg__VM_h_gr_13", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_HI
, 0, 0, 0 },
1277 { OUTPUT
, "h_memory_dir9", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_HI
, 0, 0, 0 },
1278 { OUTPUT
, "h_gr_13", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 13, 0 },
1282 static const CGEN_OPERAND_INSTANCE fmt_dmovr13pib_ops
[] = {
1283 { INPUT
, "dir8", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (DIR8
), 0, 0 },
1284 { INPUT
, "h_gr_13", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 13, 0 },
1285 { INPUT
, "h_memory_reg__VM_h_gr_13", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_QI
, 0, 0, 0 },
1286 { OUTPUT
, "h_memory_dir8", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_QI
, 0, 0, 0 },
1287 { OUTPUT
, "h_gr_13", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 13, 0 },
1291 static const CGEN_OPERAND_INSTANCE fmt_dmovr15pi_ops
[] = {
1292 { INPUT
, "dir10", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (DIR10
), 0, 0 },
1293 { INPUT
, "h_gr_15", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 15, 0 },
1294 { INPUT
, "h_memory_reg__VM_h_gr_15", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1295 { OUTPUT
, "h_memory_dir10", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1296 { OUTPUT
, "h_gr_15", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 15, 0 },
1300 static const CGEN_OPERAND_INSTANCE fmt_dmov2r13_ops
[] = {
1301 { INPUT
, "dir10", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (DIR10
), 0, 0 },
1302 { INPUT
, "h_memory_dir10", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1303 { OUTPUT
, "h_gr_13", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 13, 0 },
1307 static const CGEN_OPERAND_INSTANCE fmt_dmov2r13h_ops
[] = {
1308 { INPUT
, "dir9", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (DIR9
), 0, 0 },
1309 { INPUT
, "h_memory_dir9", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_HI
, 0, 0, 0 },
1310 { OUTPUT
, "h_gr_13", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 13, 0 },
1314 static const CGEN_OPERAND_INSTANCE fmt_dmov2r13b_ops
[] = {
1315 { INPUT
, "dir8", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (DIR8
), 0, 0 },
1316 { INPUT
, "h_memory_dir8", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_QI
, 0, 0, 0 },
1317 { OUTPUT
, "h_gr_13", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 13, 0 },
1321 static const CGEN_OPERAND_INSTANCE fmt_dmov2r13pi_ops
[] = {
1322 { INPUT
, "h_gr_13", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 13, 0 },
1323 { INPUT
, "dir10", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (DIR10
), 0, 0 },
1324 { INPUT
, "h_memory_dir10", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1325 { OUTPUT
, "h_memory_reg__VM_h_gr_13", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1326 { OUTPUT
, "h_gr_13", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 13, 0 },
1330 static const CGEN_OPERAND_INSTANCE fmt_dmov2r13pih_ops
[] = {
1331 { INPUT
, "h_gr_13", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 13, 0 },
1332 { INPUT
, "dir9", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (DIR9
), 0, 0 },
1333 { INPUT
, "h_memory_dir9", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_HI
, 0, 0, 0 },
1334 { OUTPUT
, "h_memory_reg__VM_h_gr_13", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_HI
, 0, 0, 0 },
1335 { OUTPUT
, "h_gr_13", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 13, 0 },
1339 static const CGEN_OPERAND_INSTANCE fmt_dmov2r13pib_ops
[] = {
1340 { INPUT
, "h_gr_13", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 13, 0 },
1341 { INPUT
, "dir8", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (DIR8
), 0, 0 },
1342 { INPUT
, "h_memory_dir8", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_QI
, 0, 0, 0 },
1343 { OUTPUT
, "h_memory_reg__VM_h_gr_13", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_QI
, 0, 0, 0 },
1344 { OUTPUT
, "h_gr_13", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 13, 0 },
1348 static const CGEN_OPERAND_INSTANCE fmt_dmov2r15pd_ops
[] = {
1349 { INPUT
, "h_gr_15", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 15, 0 },
1350 { INPUT
, "dir10", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (DIR10
), 0, 0 },
1351 { INPUT
, "h_memory_dir10", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1352 { OUTPUT
, "h_gr_15", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 15, 0 },
1353 { OUTPUT
, "h_memory_reg__VM_h_gr_15", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1357 static const CGEN_OPERAND_INSTANCE fmt_andccr_ops
[] = {
1358 { INPUT
, "ccr", & HW_ENT (HW_H_CCR
), CGEN_MODE_UQI
, 0, 0, 0 },
1359 { INPUT
, "u8", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (U8
), 0, 0 },
1360 { OUTPUT
, "ccr", & HW_ENT (HW_H_CCR
), CGEN_MODE_UQI
, 0, 0, 0 },
1364 static const CGEN_OPERAND_INSTANCE fmt_stilm_ops
[] = {
1365 { INPUT
, "u8", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (U8
), 0, 0 },
1366 { OUTPUT
, "ilm", & HW_ENT (HW_H_ILM
), CGEN_MODE_UQI
, 0, 0, 0 },
1370 static const CGEN_OPERAND_INSTANCE fmt_addsp_ops
[] = {
1371 { INPUT
, "h_gr_15", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 15, 0 },
1372 { INPUT
, "s10", & HW_ENT (HW_H_SINT
), CGEN_MODE_SI
, & OP_ENT (S10
), 0, 0 },
1373 { OUTPUT
, "h_gr_15", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 15, 0 },
1377 static const CGEN_OPERAND_INSTANCE fmt_extsb_ops
[] = {
1378 { INPUT
, "Ri", & HW_ENT (HW_H_GR
), CGEN_MODE_QI
, & OP_ENT (RI
), 0, 0 },
1379 { OUTPUT
, "Ri", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RI
), 0, 0 },
1383 static const CGEN_OPERAND_INSTANCE fmt_extub_ops
[] = {
1384 { INPUT
, "Ri", & HW_ENT (HW_H_GR
), CGEN_MODE_UQI
, & OP_ENT (RI
), 0, 0 },
1385 { OUTPUT
, "Ri", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RI
), 0, 0 },
1389 static const CGEN_OPERAND_INSTANCE fmt_extsh_ops
[] = {
1390 { INPUT
, "Ri", & HW_ENT (HW_H_GR
), CGEN_MODE_HI
, & OP_ENT (RI
), 0, 0 },
1391 { OUTPUT
, "Ri", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RI
), 0, 0 },
1395 static const CGEN_OPERAND_INSTANCE fmt_extuh_ops
[] = {
1396 { INPUT
, "Ri", & HW_ENT (HW_H_GR
), CGEN_MODE_UHI
, & OP_ENT (RI
), 0, 0 },
1397 { OUTPUT
, "Ri", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RI
), 0, 0 },
1401 static const CGEN_OPERAND_INSTANCE fmt_ldm0_ops
[] = {
1402 { INPUT
, "reglist_low_ld", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (REGLIST_LOW_LD
), 0, 0 },
1403 { INPUT
, "h_gr_15", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 15, COND_REF
},
1404 { INPUT
, "h_memory_reg__VM_h_gr_15", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, COND_REF
},
1405 { OUTPUT
, "h_gr_0", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, COND_REF
},
1406 { OUTPUT
, "h_gr_15", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 15, COND_REF
},
1407 { OUTPUT
, "h_gr_1", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 1, COND_REF
},
1408 { OUTPUT
, "h_gr_2", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 2, COND_REF
},
1409 { OUTPUT
, "h_gr_3", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 3, COND_REF
},
1410 { OUTPUT
, "h_gr_4", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 4, COND_REF
},
1411 { OUTPUT
, "h_gr_5", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 5, COND_REF
},
1412 { OUTPUT
, "h_gr_6", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 6, COND_REF
},
1413 { OUTPUT
, "h_gr_7", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 7, COND_REF
},
1417 static const CGEN_OPERAND_INSTANCE fmt_ldm1_ops
[] = {
1418 { INPUT
, "reglist_hi_ld", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (REGLIST_HI_LD
), 0, 0 },
1419 { INPUT
, "h_gr_15", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 15, COND_REF
},
1420 { INPUT
, "h_memory_reg__VM_h_gr_15", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, COND_REF
},
1421 { OUTPUT
, "h_gr_8", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 8, COND_REF
},
1422 { OUTPUT
, "h_gr_15", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 15, COND_REF
},
1423 { OUTPUT
, "h_gr_9", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 9, COND_REF
},
1424 { OUTPUT
, "h_gr_10", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 10, COND_REF
},
1425 { OUTPUT
, "h_gr_11", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 11, COND_REF
},
1426 { OUTPUT
, "h_gr_12", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 12, COND_REF
},
1427 { OUTPUT
, "h_gr_13", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 13, COND_REF
},
1428 { OUTPUT
, "h_gr_14", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 14, COND_REF
},
1432 static const CGEN_OPERAND_INSTANCE fmt_stm0_ops
[] = {
1433 { INPUT
, "reglist_low_st", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (REGLIST_LOW_ST
), 0, 0 },
1434 { INPUT
, "h_gr_15", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 15, COND_REF
},
1435 { INPUT
, "h_gr_7", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 7, COND_REF
},
1436 { INPUT
, "h_gr_6", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 6, COND_REF
},
1437 { INPUT
, "h_gr_5", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 5, COND_REF
},
1438 { INPUT
, "h_gr_4", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 4, COND_REF
},
1439 { INPUT
, "h_gr_3", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 3, COND_REF
},
1440 { INPUT
, "h_gr_2", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 2, COND_REF
},
1441 { INPUT
, "h_gr_1", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 1, COND_REF
},
1442 { INPUT
, "h_gr_0", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 0, COND_REF
},
1443 { OUTPUT
, "h_gr_15", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 15, COND_REF
},
1444 { OUTPUT
, "h_memory_reg__VM_h_gr_15", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, COND_REF
},
1448 static const CGEN_OPERAND_INSTANCE fmt_stm1_ops
[] = {
1449 { INPUT
, "reglist_hi_st", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (REGLIST_HI_ST
), 0, 0 },
1450 { INPUT
, "h_gr_15", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 15, COND_REF
},
1451 { INPUT
, "h_gr_14", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 14, COND_REF
},
1452 { INPUT
, "h_gr_13", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 13, COND_REF
},
1453 { INPUT
, "h_gr_12", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 12, COND_REF
},
1454 { INPUT
, "h_gr_11", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 11, COND_REF
},
1455 { INPUT
, "h_gr_10", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 10, COND_REF
},
1456 { INPUT
, "h_gr_9", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 9, COND_REF
},
1457 { INPUT
, "h_gr_8", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 8, COND_REF
},
1458 { OUTPUT
, "h_gr_15", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 15, COND_REF
},
1459 { OUTPUT
, "h_memory_reg__VM_h_gr_15", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, COND_REF
},
1463 static const CGEN_OPERAND_INSTANCE fmt_enter_ops
[] = {
1464 { INPUT
, "h_gr_15", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 15, 0 },
1465 { INPUT
, "h_gr_14", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 14, 0 },
1466 { INPUT
, "u10", & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (U10
), 0, 0 },
1467 { OUTPUT
, "h_memory_tmp", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1468 { OUTPUT
, "h_gr_14", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 14, 0 },
1469 { OUTPUT
, "h_gr_15", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 15, 0 },
1473 static const CGEN_OPERAND_INSTANCE fmt_leave_ops
[] = {
1474 { INPUT
, "h_gr_14", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 14, 0 },
1475 { INPUT
, "h_gr_15", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 15, 0 },
1476 { INPUT
, "h_memory_sub__VM_reg__VM_h_gr_15_const__WI_4", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0, 0 },
1477 { OUTPUT
, "h_gr_15", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 15, 0 },
1478 { OUTPUT
, "h_gr_14", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 14, 0 },
1482 static const CGEN_OPERAND_INSTANCE fmt_xchb_ops
[] = {
1483 { INPUT
, "Ri", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RI
), 0, 0 },
1484 { INPUT
, "Rj", & HW_ENT (HW_H_GR
), CGEN_MODE_USI
, & OP_ENT (RJ
), 0, 0 },
1485 { INPUT
, "h_memory_Rj", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_UQI
, 0, 0, 0 },
1486 { OUTPUT
, "Ri", & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (RI
), 0, 0 },
1487 { OUTPUT
, "h_memory_Rj", & HW_ENT (HW_H_MEMORY
), CGEN_MODE_UQI
, 0, 0, 0 },
1495 /* Instruction formats. */
1497 #define F(f) & fr30_cgen_ifld_table[CONCAT2 (FR30_,f)]
1499 static const CGEN_IFMT fmt_add
= {
1500 16, 16, 0xff00, { F (F_OP1
), F (F_OP2
), F (F_RJ
), F (F_RI
), 0 }
1503 static const CGEN_IFMT fmt_addi
= {
1504 16, 16, 0xff00, { F (F_OP1
), F (F_OP2
), F (F_U4
), F (F_RI
), 0 }
1507 static const CGEN_IFMT fmt_add2
= {
1508 16, 16, 0xff00, { F (F_OP1
), F (F_OP2
), F (F_M4
), F (F_RI
), 0 }
1511 static const CGEN_IFMT fmt_addc
= {
1512 16, 16, 0xff00, { F (F_OP1
), F (F_OP2
), F (F_RJ
), F (F_RI
), 0 }
1515 static const CGEN_IFMT fmt_addn
= {
1516 16, 16, 0xff00, { F (F_OP1
), F (F_OP2
), F (F_RJ
), F (F_RI
), 0 }
1519 static const CGEN_IFMT fmt_addni
= {
1520 16, 16, 0xff00, { F (F_OP1
), F (F_OP2
), F (F_U4
), F (F_RI
), 0 }
1523 static const CGEN_IFMT fmt_addn2
= {
1524 16, 16, 0xff00, { F (F_OP1
), F (F_OP2
), F (F_M4
), F (F_RI
), 0 }
1527 static const CGEN_IFMT fmt_cmp
= {
1528 16, 16, 0xff00, { F (F_OP1
), F (F_OP2
), F (F_RJ
), F (F_RI
), 0 }
1531 static const CGEN_IFMT fmt_cmpi
= {
1532 16, 16, 0xff00, { F (F_OP1
), F (F_OP2
), F (F_U4
), F (F_RI
), 0 }
1535 static const CGEN_IFMT fmt_cmp2
= {
1536 16, 16, 0xff00, { F (F_OP1
), F (F_OP2
), F (F_M4
), F (F_RI
), 0 }
1539 static const CGEN_IFMT fmt_and
= {
1540 16, 16, 0xff00, { F (F_OP1
), F (F_OP2
), F (F_RJ
), F (F_RI
), 0 }
1543 static const CGEN_IFMT fmt_andm
= {
1544 16, 16, 0xff00, { F (F_OP1
), F (F_OP2
), F (F_RJ
), F (F_RI
), 0 }
1547 static const CGEN_IFMT fmt_andh
= {
1548 16, 16, 0xff00, { F (F_OP1
), F (F_OP2
), F (F_RJ
), F (F_RI
), 0 }
1551 static const CGEN_IFMT fmt_andb
= {
1552 16, 16, 0xff00, { F (F_OP1
), F (F_OP2
), F (F_RJ
), F (F_RI
), 0 }
1555 static const CGEN_IFMT fmt_bandl
= {
1556 16, 16, 0xff00, { F (F_OP1
), F (F_OP2
), F (F_U4
), F (F_RI
), 0 }
1559 static const CGEN_IFMT fmt_btstl
= {
1560 16, 16, 0xff00, { F (F_OP1
), F (F_OP2
), F (F_U4
), F (F_RI
), 0 }
1563 static const CGEN_IFMT fmt_mul
= {
1564 16, 16, 0xff00, { F (F_OP1
), F (F_OP2
), F (F_RJ
), F (F_RI
), 0 }
1567 static const CGEN_IFMT fmt_mulu
= {
1568 16, 16, 0xff00, { F (F_OP1
), F (F_OP2
), F (F_RJ
), F (F_RI
), 0 }
1571 static const CGEN_IFMT fmt_mulh
= {
1572 16, 16, 0xff00, { F (F_OP1
), F (F_OP2
), F (F_RJ
), F (F_RI
), 0 }
1575 static const CGEN_IFMT fmt_div0s
= {
1576 16, 16, 0xfff0, { F (F_OP1
), F (F_OP2
), F (F_OP3
), F (F_RI
), 0 }
1579 static const CGEN_IFMT fmt_div0u
= {
1580 16, 16, 0xfff0, { F (F_OP1
), F (F_OP2
), F (F_OP3
), F (F_RI
), 0 }
1583 static const CGEN_IFMT fmt_div1
= {
1584 16, 16, 0xfff0, { F (F_OP1
), F (F_OP2
), F (F_OP3
), F (F_RI
), 0 }
1587 static const CGEN_IFMT fmt_div2
= {
1588 16, 16, 0xfff0, { F (F_OP1
), F (F_OP2
), F (F_OP3
), F (F_RI
), 0 }
1591 static const CGEN_IFMT fmt_div3
= {
1592 16, 16, 0xffff, { F (F_OP1
), F (F_OP2
), F (F_OP3
), F (F_OP4
), 0 }
1595 static const CGEN_IFMT fmt_div4s
= {
1596 16, 16, 0xffff, { F (F_OP1
), F (F_OP2
), F (F_OP3
), F (F_OP4
), 0 }
1599 static const CGEN_IFMT fmt_lsl
= {
1600 16, 16, 0xff00, { F (F_OP1
), F (F_OP2
), F (F_RJ
), F (F_RI
), 0 }
1603 static const CGEN_IFMT fmt_lsli
= {
1604 16, 16, 0xff00, { F (F_OP1
), F (F_OP2
), F (F_U4
), F (F_RI
), 0 }
1607 static const CGEN_IFMT fmt_ldi8
= {
1608 16, 16, 0xf000, { F (F_OP1
), F (F_I8
), F (F_RI
), 0 }
1611 static const CGEN_IFMT fmt_ldi20
= {
1612 16, 32, 0xff00, { F (F_OP1
), F (F_I20
), F (F_OP2
), F (F_RI
), 0 }
1615 static const CGEN_IFMT fmt_ldi32
= {
1616 16, 48, 0xfff0, { F (F_OP1
), F (F_I32
), F (F_OP2
), F (F_OP3
), F (F_RI
), 0 }
1619 static const CGEN_IFMT fmt_ld
= {
1620 16, 16, 0xff00, { F (F_OP1
), F (F_OP2
), F (F_RJ
), F (F_RI
), 0 }
1623 static const CGEN_IFMT fmt_lduh
= {
1624 16, 16, 0xff00, { F (F_OP1
), F (F_OP2
), F (F_RJ
), F (F_RI
), 0 }
1627 static const CGEN_IFMT fmt_ldub
= {
1628 16, 16, 0xff00, { F (F_OP1
), F (F_OP2
), F (F_RJ
), F (F_RI
), 0 }
1631 static const CGEN_IFMT fmt_ldr13
= {
1632 16, 16, 0xff00, { F (F_OP1
), F (F_OP2
), F (F_RJ
), F (F_RI
), 0 }
1635 static const CGEN_IFMT fmt_ldr13uh
= {
1636 16, 16, 0xff00, { F (F_OP1
), F (F_OP2
), F (F_RJ
), F (F_RI
), 0 }
1639 static const CGEN_IFMT fmt_ldr13ub
= {
1640 16, 16, 0xff00, { F (F_OP1
), F (F_OP2
), F (F_RJ
), F (F_RI
), 0 }
1643 static const CGEN_IFMT fmt_ldr14
= {
1644 16, 16, 0xf000, { F (F_OP1
), F (F_DISP10
), F (F_RI
), 0 }
1647 static const CGEN_IFMT fmt_ldr14uh
= {
1648 16, 16, 0xf000, { F (F_OP1
), F (F_DISP9
), F (F_RI
), 0 }
1651 static const CGEN_IFMT fmt_ldr14ub
= {
1652 16, 16, 0xf000, { F (F_OP1
), F (F_DISP8
), F (F_RI
), 0 }
1655 static const CGEN_IFMT fmt_ldr15
= {
1656 16, 16, 0xff00, { F (F_OP1
), F (F_OP2
), F (F_UDISP6
), F (F_RI
), 0 }
1659 static const CGEN_IFMT fmt_ldr15gr
= {
1660 16, 16, 0xfff0, { F (F_OP1
), F (F_OP2
), F (F_OP3
), F (F_RI
), 0 }
1663 static const CGEN_IFMT fmt_ldr15dr
= {
1664 16, 16, 0xfff0, { F (F_OP1
), F (F_OP2
), F (F_OP3
), F (F_RS2
), 0 }
1667 static const CGEN_IFMT fmt_ldr15ps
= {
1668 16, 16, 0xffff, { F (F_OP1
), F (F_OP2
), F (F_OP3
), F (F_OP4
), 0 }
1671 static const CGEN_IFMT fmt_st
= {
1672 16, 16, 0xff00, { F (F_OP1
), F (F_OP2
), F (F_RJ
), F (F_RI
), 0 }
1675 static const CGEN_IFMT fmt_sth
= {
1676 16, 16, 0xff00, { F (F_OP1
), F (F_OP2
), F (F_RJ
), F (F_RI
), 0 }
1679 static const CGEN_IFMT fmt_stb
= {
1680 16, 16, 0xff00, { F (F_OP1
), F (F_OP2
), F (F_RJ
), F (F_RI
), 0 }
1683 static const CGEN_IFMT fmt_str13
= {
1684 16, 16, 0xff00, { F (F_OP1
), F (F_OP2
), F (F_RJ
), F (F_RI
), 0 }
1687 static const CGEN_IFMT fmt_str13h
= {
1688 16, 16, 0xff00, { F (F_OP1
), F (F_OP2
), F (F_RJ
), F (F_RI
), 0 }
1691 static const CGEN_IFMT fmt_str13b
= {
1692 16, 16, 0xff00, { F (F_OP1
), F (F_OP2
), F (F_RJ
), F (F_RI
), 0 }
1695 static const CGEN_IFMT fmt_str14
= {
1696 16, 16, 0xf000, { F (F_OP1
), F (F_DISP10
), F (F_RI
), 0 }
1699 static const CGEN_IFMT fmt_str14h
= {
1700 16, 16, 0xf000, { F (F_OP1
), F (F_DISP9
), F (F_RI
), 0 }
1703 static const CGEN_IFMT fmt_str14b
= {
1704 16, 16, 0xf000, { F (F_OP1
), F (F_DISP8
), F (F_RI
), 0 }
1707 static const CGEN_IFMT fmt_str15
= {
1708 16, 16, 0xff00, { F (F_OP1
), F (F_OP2
), F (F_UDISP6
), F (F_RI
), 0 }
1711 static const CGEN_IFMT fmt_str15gr
= {
1712 16, 16, 0xfff0, { F (F_OP1
), F (F_OP2
), F (F_OP3
), F (F_RI
), 0 }
1715 static const CGEN_IFMT fmt_str15dr
= {
1716 16, 16, 0xfff0, { F (F_OP1
), F (F_OP2
), F (F_OP3
), F (F_RS2
), 0 }
1719 static const CGEN_IFMT fmt_str15ps
= {
1720 16, 16, 0xffff, { F (F_OP1
), F (F_OP2
), F (F_OP3
), F (F_OP4
), 0 }
1723 static const CGEN_IFMT fmt_mov
= {
1724 16, 16, 0xff00, { F (F_OP1
), F (F_OP2
), F (F_RJ
), F (F_RI
), 0 }
1727 static const CGEN_IFMT fmt_movdr
= {
1728 16, 16, 0xff00, { F (F_OP1
), F (F_OP2
), F (F_RS1
), F (F_RI
), 0 }
1731 static const CGEN_IFMT fmt_movps
= {
1732 16, 16, 0xfff0, { F (F_OP1
), F (F_OP2
), F (F_OP3
), F (F_RI
), 0 }
1735 static const CGEN_IFMT fmt_mov2dr
= {
1736 16, 16, 0xff00, { F (F_OP1
), F (F_OP2
), F (F_RS1
), F (F_RI
), 0 }
1739 static const CGEN_IFMT fmt_mov2ps
= {
1740 16, 16, 0xfff0, { F (F_OP1
), F (F_OP2
), F (F_OP3
), F (F_RI
), 0 }
1743 static const CGEN_IFMT fmt_jmp
= {
1744 16, 16, 0xfff0, { F (F_OP1
), F (F_OP2
), F (F_OP3
), F (F_RI
), 0 }
1747 static const CGEN_IFMT fmt_callr
= {
1748 16, 16, 0xfff0, { F (F_OP1
), F (F_OP2
), F (F_OP3
), F (F_RI
), 0 }
1751 static const CGEN_IFMT fmt_call
= {
1752 16, 16, 0xf800, { F (F_OP1
), F (F_OP5
), F (F_REL12
), 0 }
1755 static const CGEN_IFMT fmt_ret
= {
1756 16, 16, 0xffff, { F (F_OP1
), F (F_OP2
), F (F_OP3
), F (F_OP4
), 0 }
1759 static const CGEN_IFMT fmt_int
= {
1760 16, 16, 0xff00, { F (F_OP1
), F (F_OP2
), F (F_U8
), 0 }
1763 static const CGEN_IFMT fmt_inte
= {
1764 16, 16, 0xffff, { F (F_OP1
), F (F_OP2
), F (F_OP3
), F (F_OP4
), 0 }
1767 static const CGEN_IFMT fmt_reti
= {
1768 16, 16, 0xffff, { F (F_OP1
), F (F_OP2
), F (F_OP3
), F (F_OP4
), 0 }
1771 static const CGEN_IFMT fmt_bra
= {
1772 16, 16, 0xff00, { F (F_OP1
), F (F_CC
), F (F_REL9
), 0 }
1775 static const CGEN_IFMT fmt_beq
= {
1776 16, 16, 0xff00, { F (F_OP1
), F (F_CC
), F (F_REL9
), 0 }
1779 static const CGEN_IFMT fmt_bc
= {
1780 16, 16, 0xff00, { F (F_OP1
), F (F_CC
), F (F_REL9
), 0 }
1783 static const CGEN_IFMT fmt_bn
= {
1784 16, 16, 0xff00, { F (F_OP1
), F (F_CC
), F (F_REL9
), 0 }
1787 static const CGEN_IFMT fmt_bv
= {
1788 16, 16, 0xff00, { F (F_OP1
), F (F_CC
), F (F_REL9
), 0 }
1791 static const CGEN_IFMT fmt_blt
= {
1792 16, 16, 0xff00, { F (F_OP1
), F (F_CC
), F (F_REL9
), 0 }
1795 static const CGEN_IFMT fmt_ble
= {
1796 16, 16, 0xff00, { F (F_OP1
), F (F_CC
), F (F_REL9
), 0 }
1799 static const CGEN_IFMT fmt_bls
= {
1800 16, 16, 0xff00, { F (F_OP1
), F (F_CC
), F (F_REL9
), 0 }
1803 static const CGEN_IFMT fmt_dmovr13
= {
1804 16, 16, 0xff00, { F (F_OP1
), F (F_OP2
), F (F_DIR10
), 0 }
1807 static const CGEN_IFMT fmt_dmovr13h
= {
1808 16, 16, 0xff00, { F (F_OP1
), F (F_OP2
), F (F_DIR9
), 0 }
1811 static const CGEN_IFMT fmt_dmovr13b
= {
1812 16, 16, 0xff00, { F (F_OP1
), F (F_OP2
), F (F_DIR8
), 0 }
1815 static const CGEN_IFMT fmt_dmovr13pi
= {
1816 16, 16, 0xff00, { F (F_OP1
), F (F_OP2
), F (F_DIR10
), 0 }
1819 static const CGEN_IFMT fmt_dmovr13pih
= {
1820 16, 16, 0xff00, { F (F_OP1
), F (F_OP2
), F (F_DIR9
), 0 }
1823 static const CGEN_IFMT fmt_dmovr13pib
= {
1824 16, 16, 0xff00, { F (F_OP1
), F (F_OP2
), F (F_DIR8
), 0 }
1827 static const CGEN_IFMT fmt_dmovr15pi
= {
1828 16, 16, 0xff00, { F (F_OP1
), F (F_OP2
), F (F_DIR10
), 0 }
1831 static const CGEN_IFMT fmt_dmov2r13
= {
1832 16, 16, 0xff00, { F (F_OP1
), F (F_OP2
), F (F_DIR10
), 0 }
1835 static const CGEN_IFMT fmt_dmov2r13h
= {
1836 16, 16, 0xff00, { F (F_OP1
), F (F_OP2
), F (F_DIR9
), 0 }
1839 static const CGEN_IFMT fmt_dmov2r13b
= {
1840 16, 16, 0xff00, { F (F_OP1
), F (F_OP2
), F (F_DIR8
), 0 }
1843 static const CGEN_IFMT fmt_dmov2r13pi
= {
1844 16, 16, 0xff00, { F (F_OP1
), F (F_OP2
), F (F_DIR10
), 0 }
1847 static const CGEN_IFMT fmt_dmov2r13pih
= {
1848 16, 16, 0xff00, { F (F_OP1
), F (F_OP2
), F (F_DIR9
), 0 }
1851 static const CGEN_IFMT fmt_dmov2r13pib
= {
1852 16, 16, 0xff00, { F (F_OP1
), F (F_OP2
), F (F_DIR8
), 0 }
1855 static const CGEN_IFMT fmt_dmov2r15pd
= {
1856 16, 16, 0xff00, { F (F_OP1
), F (F_OP2
), F (F_DIR10
), 0 }
1859 static const CGEN_IFMT fmt_ldres
= {
1860 16, 16, 0xff00, { F (F_OP1
), F (F_OP2
), F (F_U4
), F (F_RI
), 0 }
1863 static const CGEN_IFMT fmt_copop
= {
1864 16, 32, 0xfff0, { F (F_OP1
), F (F_CCC
), F (F_OP2
), F (F_OP3
), F (F_CRJ
), F (F_U4C
), F (F_CRI
), 0 }
1867 static const CGEN_IFMT fmt_copld
= {
1868 16, 32, 0xfff0, { F (F_OP1
), F (F_CCC
), F (F_OP2
), F (F_OP3
), F (F_RJC
), F (F_U4C
), F (F_CRI
), 0 }
1871 static const CGEN_IFMT fmt_copst
= {
1872 16, 32, 0xfff0, { F (F_OP1
), F (F_CCC
), F (F_OP2
), F (F_OP3
), F (F_CRJ
), F (F_U4C
), F (F_RIC
), 0 }
1875 static const CGEN_IFMT fmt_nop
= {
1876 16, 16, 0xffff, { F (F_OP1
), F (F_OP2
), F (F_OP3
), F (F_OP4
), 0 }
1879 static const CGEN_IFMT fmt_andccr
= {
1880 16, 16, 0xff00, { F (F_OP1
), F (F_OP2
), F (F_U8
), 0 }
1883 static const CGEN_IFMT fmt_stilm
= {
1884 16, 16, 0xff00, { F (F_OP1
), F (F_OP2
), F (F_U8
), 0 }
1887 static const CGEN_IFMT fmt_addsp
= {
1888 16, 16, 0xff00, { F (F_OP1
), F (F_OP2
), F (F_S10
), 0 }
1891 static const CGEN_IFMT fmt_extsb
= {
1892 16, 16, 0xfff0, { F (F_OP1
), F (F_OP2
), F (F_OP3
), F (F_RI
), 0 }
1895 static const CGEN_IFMT fmt_extub
= {
1896 16, 16, 0xfff0, { F (F_OP1
), F (F_OP2
), F (F_OP3
), F (F_RI
), 0 }
1899 static const CGEN_IFMT fmt_extsh
= {
1900 16, 16, 0xfff0, { F (F_OP1
), F (F_OP2
), F (F_OP3
), F (F_RI
), 0 }
1903 static const CGEN_IFMT fmt_extuh
= {
1904 16, 16, 0xfff0, { F (F_OP1
), F (F_OP2
), F (F_OP3
), F (F_RI
), 0 }
1907 static const CGEN_IFMT fmt_ldm0
= {
1908 16, 16, 0xff00, { F (F_OP1
), F (F_OP2
), F (F_REGLIST_LOW_LD
), 0 }
1911 static const CGEN_IFMT fmt_ldm1
= {
1912 16, 16, 0xff00, { F (F_OP1
), F (F_OP2
), F (F_REGLIST_HI_LD
), 0 }
1915 static const CGEN_IFMT fmt_stm0
= {
1916 16, 16, 0xff00, { F (F_OP1
), F (F_OP2
), F (F_REGLIST_LOW_ST
), 0 }
1919 static const CGEN_IFMT fmt_stm1
= {
1920 16, 16, 0xff00, { F (F_OP1
), F (F_OP2
), F (F_REGLIST_HI_ST
), 0 }
1923 static const CGEN_IFMT fmt_enter
= {
1924 16, 16, 0xff00, { F (F_OP1
), F (F_OP2
), F (F_U10
), 0 }
1927 static const CGEN_IFMT fmt_leave
= {
1928 16, 16, 0xffff, { F (F_OP1
), F (F_OP2
), F (F_OP3
), F (F_OP4
), 0 }
1931 static const CGEN_IFMT fmt_xchb
= {
1932 16, 16, 0xff00, { F (F_OP1
), F (F_OP2
), F (F_RJ
), F (F_RI
), 0 }
1937 #define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
1938 #define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
1939 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
1941 /* The instruction table.
1942 This is currently non-static because the simulator accesses it
1945 const CGEN_INSN fr30_cgen_insn_table_entries
[MAX_INSNS
] =
1947 /* Special null first entry.
1948 A `num' value of zero is thus invalid.
1949 Also, the special `invalid' insn resides here. */
1954 FR30_INSN_ADD
, "add", "add",
1955 { { MNEM
, ' ', OP (RJ
), ',', OP (RI
), 0 } },
1956 & fmt_add
, { 0xa600 },
1957 (PTR
) & fmt_add_ops
[0],
1963 FR30_INSN_ADDI
, "addi", "add",
1964 { { MNEM
, ' ', OP (U4
), ',', OP (RI
), 0 } },
1965 & fmt_addi
, { 0xa400 },
1966 (PTR
) & fmt_addi_ops
[0],
1972 FR30_INSN_ADD2
, "add2", "add2",
1973 { { MNEM
, ' ', OP (M4
), ',', OP (RI
), 0 } },
1974 & fmt_add2
, { 0xa500 },
1975 (PTR
) & fmt_add2_ops
[0],
1981 FR30_INSN_ADDC
, "addc", "addc",
1982 { { MNEM
, ' ', OP (RJ
), ',', OP (RI
), 0 } },
1983 & fmt_addc
, { 0xa700 },
1984 (PTR
) & fmt_addc_ops
[0],
1990 FR30_INSN_ADDN
, "addn", "addn",
1991 { { MNEM
, ' ', OP (RJ
), ',', OP (RI
), 0 } },
1992 & fmt_addn
, { 0xa200 },
1993 (PTR
) & fmt_addn_ops
[0],
1999 FR30_INSN_ADDNI
, "addni", "addn",
2000 { { MNEM
, ' ', OP (U4
), ',', OP (RI
), 0 } },
2001 & fmt_addni
, { 0xa000 },
2002 (PTR
) & fmt_addni_ops
[0],
2008 FR30_INSN_ADDN2
, "addn2", "addn2",
2009 { { MNEM
, ' ', OP (M4
), ',', OP (RI
), 0 } },
2010 & fmt_addn2
, { 0xa100 },
2011 (PTR
) & fmt_addn2_ops
[0],
2017 FR30_INSN_SUB
, "sub", "sub",
2018 { { MNEM
, ' ', OP (RJ
), ',', OP (RI
), 0 } },
2019 & fmt_add
, { 0xac00 },
2020 (PTR
) & fmt_add_ops
[0],
2026 FR30_INSN_SUBC
, "subc", "subc",
2027 { { MNEM
, ' ', OP (RJ
), ',', OP (RI
), 0 } },
2028 & fmt_addc
, { 0xad00 },
2029 (PTR
) & fmt_addc_ops
[0],
2035 FR30_INSN_SUBN
, "subn", "subn",
2036 { { MNEM
, ' ', OP (RJ
), ',', OP (RI
), 0 } },
2037 & fmt_addn
, { 0xae00 },
2038 (PTR
) & fmt_addn_ops
[0],
2044 FR30_INSN_CMP
, "cmp", "cmp",
2045 { { MNEM
, ' ', OP (RJ
), ',', OP (RI
), 0 } },
2046 & fmt_cmp
, { 0xaa00 },
2047 (PTR
) & fmt_cmp_ops
[0],
2053 FR30_INSN_CMPI
, "cmpi", "cmp",
2054 { { MNEM
, ' ', OP (U4
), ',', OP (RI
), 0 } },
2055 & fmt_cmpi
, { 0xa800 },
2056 (PTR
) & fmt_cmpi_ops
[0],
2062 FR30_INSN_CMP2
, "cmp2", "cmp2",
2063 { { MNEM
, ' ', OP (M4
), ',', OP (RI
), 0 } },
2064 & fmt_cmp2
, { 0xa900 },
2065 (PTR
) & fmt_cmp2_ops
[0],
2071 FR30_INSN_AND
, "and", "and",
2072 { { MNEM
, ' ', OP (RJ
), ',', OP (RI
), 0 } },
2073 & fmt_and
, { 0x8200 },
2074 (PTR
) & fmt_and_ops
[0],
2080 FR30_INSN_OR
, "or", "or",
2081 { { MNEM
, ' ', OP (RJ
), ',', OP (RI
), 0 } },
2082 & fmt_and
, { 0x9200 },
2083 (PTR
) & fmt_and_ops
[0],
2089 FR30_INSN_EOR
, "eor", "eor",
2090 { { MNEM
, ' ', OP (RJ
), ',', OP (RI
), 0 } },
2091 & fmt_and
, { 0x9a00 },
2092 (PTR
) & fmt_and_ops
[0],
2098 FR30_INSN_ANDM
, "andm", "and",
2099 { { MNEM
, ' ', OP (RJ
), ',', '@', OP (RI
), 0 } },
2100 & fmt_andm
, { 0x8400 },
2101 (PTR
) & fmt_andm_ops
[0],
2107 FR30_INSN_ANDH
, "andh", "andh",
2108 { { MNEM
, ' ', OP (RJ
), ',', '@', OP (RI
), 0 } },
2109 & fmt_andh
, { 0x8500 },
2110 (PTR
) & fmt_andh_ops
[0],
2116 FR30_INSN_ANDB
, "andb", "andb",
2117 { { MNEM
, ' ', OP (RJ
), ',', '@', OP (RI
), 0 } },
2118 & fmt_andb
, { 0x8600 },
2119 (PTR
) & fmt_andb_ops
[0],
2125 FR30_INSN_ORM
, "orm", "or",
2126 { { MNEM
, ' ', OP (RJ
), ',', '@', OP (RI
), 0 } },
2127 & fmt_andm
, { 0x9400 },
2128 (PTR
) & fmt_andm_ops
[0],
2134 FR30_INSN_ORH
, "orh", "orh",
2135 { { MNEM
, ' ', OP (RJ
), ',', '@', OP (RI
), 0 } },
2136 & fmt_andh
, { 0x9500 },
2137 (PTR
) & fmt_andh_ops
[0],
2143 FR30_INSN_ORB
, "orb", "orb",
2144 { { MNEM
, ' ', OP (RJ
), ',', '@', OP (RI
), 0 } },
2145 & fmt_andb
, { 0x9600 },
2146 (PTR
) & fmt_andb_ops
[0],
2152 FR30_INSN_EORM
, "eorm", "eor",
2153 { { MNEM
, ' ', OP (RJ
), ',', '@', OP (RI
), 0 } },
2154 & fmt_andm
, { 0x9c00 },
2155 (PTR
) & fmt_andm_ops
[0],
2161 FR30_INSN_EORH
, "eorh", "eorh",
2162 { { MNEM
, ' ', OP (RJ
), ',', '@', OP (RI
), 0 } },
2163 & fmt_andh
, { 0x9d00 },
2164 (PTR
) & fmt_andh_ops
[0],
2170 FR30_INSN_EORB
, "eorb", "eorb",
2171 { { MNEM
, ' ', OP (RJ
), ',', '@', OP (RI
), 0 } },
2172 & fmt_andb
, { 0x9e00 },
2173 (PTR
) & fmt_andb_ops
[0],
2176 /* bandl $u4,@$Ri */
2179 FR30_INSN_BANDL
, "bandl", "bandl",
2180 { { MNEM
, ' ', OP (U4
), ',', '@', OP (RI
), 0 } },
2181 & fmt_bandl
, { 0x8000 },
2182 (PTR
) & fmt_bandl_ops
[0],
2188 FR30_INSN_BORL
, "borl", "borl",
2189 { { MNEM
, ' ', OP (U4
), ',', '@', OP (RI
), 0 } },
2190 & fmt_bandl
, { 0x9000 },
2191 (PTR
) & fmt_bandl_ops
[0],
2194 /* beorl $u4,@$Ri */
2197 FR30_INSN_BEORL
, "beorl", "beorl",
2198 { { MNEM
, ' ', OP (U4
), ',', '@', OP (RI
), 0 } },
2199 & fmt_bandl
, { 0x9800 },
2200 (PTR
) & fmt_bandl_ops
[0],
2203 /* bandh $u4,@$Ri */
2206 FR30_INSN_BANDH
, "bandh", "bandh",
2207 { { MNEM
, ' ', OP (U4
), ',', '@', OP (RI
), 0 } },
2208 & fmt_bandl
, { 0x8100 },
2209 (PTR
) & fmt_bandl_ops
[0],
2215 FR30_INSN_BORH
, "borh", "borh",
2216 { { MNEM
, ' ', OP (U4
), ',', '@', OP (RI
), 0 } },
2217 & fmt_bandl
, { 0x9100 },
2218 (PTR
) & fmt_bandl_ops
[0],
2221 /* beorh $u4,@$Ri */
2224 FR30_INSN_BEORH
, "beorh", "beorh",
2225 { { MNEM
, ' ', OP (U4
), ',', '@', OP (RI
), 0 } },
2226 & fmt_bandl
, { 0x9900 },
2227 (PTR
) & fmt_bandl_ops
[0],
2230 /* btstl $u4,@$Ri */
2233 FR30_INSN_BTSTL
, "btstl", "btstl",
2234 { { MNEM
, ' ', OP (U4
), ',', '@', OP (RI
), 0 } },
2235 & fmt_btstl
, { 0x8800 },
2236 (PTR
) & fmt_btstl_ops
[0],
2239 /* btsth $u4,@$Ri */
2242 FR30_INSN_BTSTH
, "btsth", "btsth",
2243 { { MNEM
, ' ', OP (U4
), ',', '@', OP (RI
), 0 } },
2244 & fmt_btstl
, { 0x8900 },
2245 (PTR
) & fmt_btstl_ops
[0],
2251 FR30_INSN_MUL
, "mul", "mul",
2252 { { MNEM
, ' ', OP (RJ
), ',', OP (RI
), 0 } },
2253 & fmt_mul
, { 0xaf00 },
2254 (PTR
) & fmt_mul_ops
[0],
2260 FR30_INSN_MULU
, "mulu", "mulu",
2261 { { MNEM
, ' ', OP (RJ
), ',', OP (RI
), 0 } },
2262 & fmt_mulu
, { 0xab00 },
2263 (PTR
) & fmt_mulu_ops
[0],
2269 FR30_INSN_MULH
, "mulh", "mulh",
2270 { { MNEM
, ' ', OP (RJ
), ',', OP (RI
), 0 } },
2271 & fmt_mulh
, { 0xbf00 },
2272 (PTR
) & fmt_mulh_ops
[0],
2278 FR30_INSN_MULUH
, "muluh", "muluh",
2279 { { MNEM
, ' ', OP (RJ
), ',', OP (RI
), 0 } },
2280 & fmt_mulh
, { 0xbb00 },
2281 (PTR
) & fmt_mulh_ops
[0],
2287 FR30_INSN_DIV0S
, "div0s", "div0s",
2288 { { MNEM
, ' ', OP (RI
), 0 } },
2289 & fmt_div0s
, { 0x9740 },
2290 (PTR
) & fmt_div0s_ops
[0],
2296 FR30_INSN_DIV0U
, "div0u", "div0u",
2297 { { MNEM
, ' ', OP (RI
), 0 } },
2298 & fmt_div0u
, { 0x9750 },
2299 (PTR
) & fmt_div0u_ops
[0],
2305 FR30_INSN_DIV1
, "div1", "div1",
2306 { { MNEM
, ' ', OP (RI
), 0 } },
2307 & fmt_div1
, { 0x9760 },
2308 (PTR
) & fmt_div1_ops
[0],
2314 FR30_INSN_DIV2
, "div2", "div2",
2315 { { MNEM
, ' ', OP (RI
), 0 } },
2316 & fmt_div2
, { 0x9770 },
2317 (PTR
) & fmt_div2_ops
[0],
2323 FR30_INSN_DIV3
, "div3", "div3",
2325 & fmt_div3
, { 0x9f60 },
2326 (PTR
) & fmt_div3_ops
[0],
2332 FR30_INSN_DIV4S
, "div4s", "div4s",
2334 & fmt_div4s
, { 0x9f70 },
2335 (PTR
) & fmt_div4s_ops
[0],
2341 FR30_INSN_LSL
, "lsl", "lsl",
2342 { { MNEM
, ' ', OP (RJ
), ',', OP (RI
), 0 } },
2343 & fmt_lsl
, { 0xb600 },
2344 (PTR
) & fmt_lsl_ops
[0],
2350 FR30_INSN_LSLI
, "lsli", "lsl",
2351 { { MNEM
, ' ', OP (U4
), ',', OP (RI
), 0 } },
2352 & fmt_lsli
, { 0xb400 },
2353 (PTR
) & fmt_lsli_ops
[0],
2359 FR30_INSN_LSL2
, "lsl2", "lsl2",
2360 { { MNEM
, ' ', OP (U4
), ',', OP (RI
), 0 } },
2361 & fmt_lsli
, { 0xb500 },
2362 (PTR
) & fmt_lsli_ops
[0],
2368 FR30_INSN_LSR
, "lsr", "lsr",
2369 { { MNEM
, ' ', OP (RJ
), ',', OP (RI
), 0 } },
2370 & fmt_lsl
, { 0xb200 },
2371 (PTR
) & fmt_lsl_ops
[0],
2377 FR30_INSN_LSRI
, "lsri", "lsr",
2378 { { MNEM
, ' ', OP (U4
), ',', OP (RI
), 0 } },
2379 & fmt_lsli
, { 0xb000 },
2380 (PTR
) & fmt_lsli_ops
[0],
2386 FR30_INSN_LSR2
, "lsr2", "lsr2",
2387 { { MNEM
, ' ', OP (U4
), ',', OP (RI
), 0 } },
2388 & fmt_lsli
, { 0xb100 },
2389 (PTR
) & fmt_lsli_ops
[0],
2395 FR30_INSN_ASR
, "asr", "asr",
2396 { { MNEM
, ' ', OP (RJ
), ',', OP (RI
), 0 } },
2397 & fmt_lsl
, { 0xba00 },
2398 (PTR
) & fmt_lsl_ops
[0],
2404 FR30_INSN_ASRI
, "asri", "asr",
2405 { { MNEM
, ' ', OP (U4
), ',', OP (RI
), 0 } },
2406 & fmt_lsli
, { 0xb800 },
2407 (PTR
) & fmt_lsli_ops
[0],
2413 FR30_INSN_ASR2
, "asr2", "asr2",
2414 { { MNEM
, ' ', OP (U4
), ',', OP (RI
), 0 } },
2415 & fmt_lsli
, { 0xb900 },
2416 (PTR
) & fmt_lsli_ops
[0],
2422 FR30_INSN_LDI8
, "ldi8", "ldi:8",
2423 { { MNEM
, ' ', OP (I8
), ',', OP (RI
), 0 } },
2424 & fmt_ldi8
, { 0xc000 },
2425 (PTR
) & fmt_ldi8_ops
[0],
2428 /* ldi:20 $i20,$Ri */
2431 FR30_INSN_LDI20
, "ldi20", "ldi:20",
2432 { { MNEM
, ' ', OP (I20
), ',', OP (RI
), 0 } },
2433 & fmt_ldi20
, { 0x9b00 },
2434 (PTR
) & fmt_ldi20_ops
[0],
2435 { 0, 0|A(NOT_IN_DELAY_SLOT
), { 0 } }
2437 /* ldi:32 $i32,$Ri */
2440 FR30_INSN_LDI32
, "ldi32", "ldi:32",
2441 { { MNEM
, ' ', OP (I32
), ',', OP (RI
), 0 } },
2442 & fmt_ldi32
, { 0x9f80 },
2443 (PTR
) & fmt_ldi32_ops
[0],
2449 FR30_INSN_LD
, "ld", "ld",
2450 { { MNEM
, ' ', '@', OP (RJ
), ',', OP (RI
), 0 } },
2451 & fmt_ld
, { 0x400 },
2452 (PTR
) & fmt_ld_ops
[0],
2458 FR30_INSN_LDUH
, "lduh", "lduh",
2459 { { MNEM
, ' ', '@', OP (RJ
), ',', OP (RI
), 0 } },
2460 & fmt_lduh
, { 0x500 },
2461 (PTR
) & fmt_lduh_ops
[0],
2467 FR30_INSN_LDUB
, "ldub", "ldub",
2468 { { MNEM
, ' ', '@', OP (RJ
), ',', OP (RI
), 0 } },
2469 & fmt_ldub
, { 0x600 },
2470 (PTR
) & fmt_ldub_ops
[0],
2473 /* ld @($R13,$Rj),$Ri */
2476 FR30_INSN_LDR13
, "ldr13", "ld",
2477 { { MNEM
, ' ', '@', '(', OP (R13
), ',', OP (RJ
), ')', ',', OP (RI
), 0 } },
2478 & fmt_ldr13
, { 0x0 },
2479 (PTR
) & fmt_ldr13_ops
[0],
2482 /* lduh @($R13,$Rj),$Ri */
2485 FR30_INSN_LDR13UH
, "ldr13uh", "lduh",
2486 { { MNEM
, ' ', '@', '(', OP (R13
), ',', OP (RJ
), ')', ',', OP (RI
), 0 } },
2487 & fmt_ldr13uh
, { 0x100 },
2488 (PTR
) & fmt_ldr13uh_ops
[0],
2491 /* ldub @($R13,$Rj),$Ri */
2494 FR30_INSN_LDR13UB
, "ldr13ub", "ldub",
2495 { { MNEM
, ' ', '@', '(', OP (R13
), ',', OP (RJ
), ')', ',', OP (RI
), 0 } },
2496 & fmt_ldr13ub
, { 0x200 },
2497 (PTR
) & fmt_ldr13ub_ops
[0],
2500 /* ld @($R14,$disp10),$Ri */
2503 FR30_INSN_LDR14
, "ldr14", "ld",
2504 { { MNEM
, ' ', '@', '(', OP (R14
), ',', OP (DISP10
), ')', ',', OP (RI
), 0 } },
2505 & fmt_ldr14
, { 0x2000 },
2506 (PTR
) & fmt_ldr14_ops
[0],
2509 /* lduh @($R14,$disp9),$Ri */
2512 FR30_INSN_LDR14UH
, "ldr14uh", "lduh",
2513 { { MNEM
, ' ', '@', '(', OP (R14
), ',', OP (DISP9
), ')', ',', OP (RI
), 0 } },
2514 & fmt_ldr14uh
, { 0x4000 },
2515 (PTR
) & fmt_ldr14uh_ops
[0],
2518 /* ldub @($R14,$disp8),$Ri */
2521 FR30_INSN_LDR14UB
, "ldr14ub", "ldub",
2522 { { MNEM
, ' ', '@', '(', OP (R14
), ',', OP (DISP8
), ')', ',', OP (RI
), 0 } },
2523 & fmt_ldr14ub
, { 0x6000 },
2524 (PTR
) & fmt_ldr14ub_ops
[0],
2527 /* ld @($R15,$udisp6),$Ri */
2530 FR30_INSN_LDR15
, "ldr15", "ld",
2531 { { MNEM
, ' ', '@', '(', OP (R15
), ',', OP (UDISP6
), ')', ',', OP (RI
), 0 } },
2532 & fmt_ldr15
, { 0x300 },
2533 (PTR
) & fmt_ldr15_ops
[0],
2539 FR30_INSN_LDR15GR
, "ldr15gr", "ld",
2540 { { MNEM
, ' ', '@', OP (R15
), '+', ',', OP (RI
), 0 } },
2541 & fmt_ldr15gr
, { 0x700 },
2542 (PTR
) & fmt_ldr15gr_ops
[0],
2545 /* ld @$R15+,$Rs2 */
2548 FR30_INSN_LDR15DR
, "ldr15dr", "ld",
2549 { { MNEM
, ' ', '@', OP (R15
), '+', ',', OP (RS2
), 0 } },
2550 & fmt_ldr15dr
, { 0x780 },
2551 (PTR
) & fmt_ldr15dr_ops
[0],
2557 FR30_INSN_LDR15PS
, "ldr15ps", "ld",
2558 { { MNEM
, ' ', '@', OP (R15
), '+', ',', OP (PS
), 0 } },
2559 & fmt_ldr15ps
, { 0x790 },
2560 (PTR
) & fmt_ldr15ps_ops
[0],
2566 FR30_INSN_ST
, "st", "st",
2567 { { MNEM
, ' ', OP (RI
), ',', '@', OP (RJ
), 0 } },
2568 & fmt_st
, { 0x1400 },
2569 (PTR
) & fmt_st_ops
[0],
2575 FR30_INSN_STH
, "sth", "sth",
2576 { { MNEM
, ' ', OP (RI
), ',', '@', OP (RJ
), 0 } },
2577 & fmt_sth
, { 0x1500 },
2578 (PTR
) & fmt_sth_ops
[0],
2584 FR30_INSN_STB
, "stb", "stb",
2585 { { MNEM
, ' ', OP (RI
), ',', '@', OP (RJ
), 0 } },
2586 & fmt_stb
, { 0x1600 },
2587 (PTR
) & fmt_stb_ops
[0],
2590 /* st $Ri,@($R13,$Rj) */
2593 FR30_INSN_STR13
, "str13", "st",
2594 { { MNEM
, ' ', OP (RI
), ',', '@', '(', OP (R13
), ',', OP (RJ
), ')', 0 } },
2595 & fmt_str13
, { 0x1000 },
2596 (PTR
) & fmt_str13_ops
[0],
2599 /* sth $Ri,@($R13,$Rj) */
2602 FR30_INSN_STR13H
, "str13h", "sth",
2603 { { MNEM
, ' ', OP (RI
), ',', '@', '(', OP (R13
), ',', OP (RJ
), ')', 0 } },
2604 & fmt_str13h
, { 0x1100 },
2605 (PTR
) & fmt_str13h_ops
[0],
2608 /* stb $Ri,@($R13,$Rj) */
2611 FR30_INSN_STR13B
, "str13b", "stb",
2612 { { MNEM
, ' ', OP (RI
), ',', '@', '(', OP (R13
), ',', OP (RJ
), ')', 0 } },
2613 & fmt_str13b
, { 0x1200 },
2614 (PTR
) & fmt_str13b_ops
[0],
2617 /* st $Ri,@($R14,$disp10) */
2620 FR30_INSN_STR14
, "str14", "st",
2621 { { MNEM
, ' ', OP (RI
), ',', '@', '(', OP (R14
), ',', OP (DISP10
), ')', 0 } },
2622 & fmt_str14
, { 0x3000 },
2623 (PTR
) & fmt_str14_ops
[0],
2626 /* sth $Ri,@($R14,$disp9) */
2629 FR30_INSN_STR14H
, "str14h", "sth",
2630 { { MNEM
, ' ', OP (RI
), ',', '@', '(', OP (R14
), ',', OP (DISP9
), ')', 0 } },
2631 & fmt_str14h
, { 0x5000 },
2632 (PTR
) & fmt_str14h_ops
[0],
2635 /* stb $Ri,@($R14,$disp8) */
2638 FR30_INSN_STR14B
, "str14b", "stb",
2639 { { MNEM
, ' ', OP (RI
), ',', '@', '(', OP (R14
), ',', OP (DISP8
), ')', 0 } },
2640 & fmt_str14b
, { 0x7000 },
2641 (PTR
) & fmt_str14b_ops
[0],
2644 /* st $Ri,@($R15,$udisp6) */
2647 FR30_INSN_STR15
, "str15", "st",
2648 { { MNEM
, ' ', OP (RI
), ',', '@', '(', OP (R15
), ',', OP (UDISP6
), ')', 0 } },
2649 & fmt_str15
, { 0x1300 },
2650 (PTR
) & fmt_str15_ops
[0],
2656 FR30_INSN_STR15GR
, "str15gr", "st",
2657 { { MNEM
, ' ', OP (RI
), ',', '@', '-', OP (R15
), 0 } },
2658 & fmt_str15gr
, { 0x1700 },
2659 (PTR
) & fmt_str15gr_ops
[0],
2662 /* st $Rs2,@-$R15 */
2665 FR30_INSN_STR15DR
, "str15dr", "st",
2666 { { MNEM
, ' ', OP (RS2
), ',', '@', '-', OP (R15
), 0 } },
2667 & fmt_str15dr
, { 0x1780 },
2668 (PTR
) & fmt_str15dr_ops
[0],
2674 FR30_INSN_STR15PS
, "str15ps", "st",
2675 { { MNEM
, ' ', OP (PS
), ',', '@', '-', OP (R15
), 0 } },
2676 & fmt_str15ps
, { 0x1790 },
2677 (PTR
) & fmt_str15ps_ops
[0],
2683 FR30_INSN_MOV
, "mov", "mov",
2684 { { MNEM
, ' ', OP (RJ
), ',', OP (RI
), 0 } },
2685 & fmt_mov
, { 0x8b00 },
2686 (PTR
) & fmt_mov_ops
[0],
2692 FR30_INSN_MOVDR
, "movdr", "mov",
2693 { { MNEM
, ' ', OP (RS1
), ',', OP (RI
), 0 } },
2694 & fmt_movdr
, { 0xb700 },
2695 (PTR
) & fmt_movdr_ops
[0],
2701 FR30_INSN_MOVPS
, "movps", "mov",
2702 { { MNEM
, ' ', OP (PS
), ',', OP (RI
), 0 } },
2703 & fmt_movps
, { 0x1710 },
2704 (PTR
) & fmt_movps_ops
[0],
2710 FR30_INSN_MOV2DR
, "mov2dr", "mov",
2711 { { MNEM
, ' ', OP (RI
), ',', OP (RS1
), 0 } },
2712 & fmt_mov2dr
, { 0xb300 },
2713 (PTR
) & fmt_mov2dr_ops
[0],
2719 FR30_INSN_MOV2PS
, "mov2ps", "mov",
2720 { { MNEM
, ' ', OP (RI
), ',', OP (PS
), 0 } },
2721 & fmt_mov2ps
, { 0x710 },
2722 (PTR
) & fmt_mov2ps_ops
[0],
2728 FR30_INSN_JMP
, "jmp", "jmp",
2729 { { MNEM
, ' ', '@', OP (RI
), 0 } },
2730 & fmt_jmp
, { 0x9700 },
2731 (PTR
) & fmt_jmp_ops
[0],
2732 { 0, 0|A(UNCOND_CTI
), { 0 } }
2737 FR30_INSN_JMPD
, "jmpd", "jmp:d",
2738 { { MNEM
, ' ', '@', OP (RI
), 0 } },
2739 & fmt_jmp
, { 0x9f00 },
2740 (PTR
) & fmt_jmp_ops
[0],
2741 { 0, 0|A(NOT_IN_DELAY_SLOT
)|A(DELAY_SLOT
)|A(UNCOND_CTI
), { 0 } }
2746 FR30_INSN_CALLR
, "callr", "call",
2747 { { MNEM
, ' ', '@', OP (RI
), 0 } },
2748 & fmt_callr
, { 0x9710 },
2749 (PTR
) & fmt_callr_ops
[0],
2750 { 0, 0|A(UNCOND_CTI
), { 0 } }
2755 FR30_INSN_CALLRD
, "callrd", "call:d",
2756 { { MNEM
, ' ', '@', OP (RI
), 0 } },
2757 & fmt_callr
, { 0x9f10 },
2758 (PTR
) & fmt_callr_ops
[0],
2759 { 0, 0|A(DELAY_SLOT
)|A(UNCOND_CTI
), { 0 } }
2764 FR30_INSN_CALL
, "call", "call",
2765 { { MNEM
, ' ', OP (LABEL12
), 0 } },
2766 & fmt_call
, { 0xd000 },
2767 (PTR
) & fmt_call_ops
[0],
2768 { 0, 0|A(UNCOND_CTI
), { 0 } }
2770 /* call:d $label12 */
2773 FR30_INSN_CALLD
, "calld", "call:d",
2774 { { MNEM
, ' ', OP (LABEL12
), 0 } },
2775 & fmt_call
, { 0xd800 },
2776 (PTR
) & fmt_call_ops
[0],
2777 { 0, 0|A(DELAY_SLOT
)|A(UNCOND_CTI
), { 0 } }
2782 FR30_INSN_RET
, "ret", "ret",
2784 & fmt_ret
, { 0x9720 },
2785 (PTR
) & fmt_ret_ops
[0],
2786 { 0, 0|A(UNCOND_CTI
), { 0 } }
2791 FR30_INSN_RET_D
, "ret:d", "ret:d",
2793 & fmt_ret
, { 0x9f20 },
2794 (PTR
) & fmt_ret_ops
[0],
2795 { 0, 0|A(DELAY_SLOT
)|A(UNCOND_CTI
), { 0 } }
2800 FR30_INSN_INT
, "int", "int",
2801 { { MNEM
, ' ', OP (U8
), 0 } },
2802 & fmt_int
, { 0x1f00 },
2803 (PTR
) & fmt_int_ops
[0],
2804 { 0, 0|A(UNCOND_CTI
), { 0 } }
2809 FR30_INSN_INTE
, "inte", "inte",
2811 & fmt_inte
, { 0x9f30 },
2812 (PTR
) & fmt_inte_ops
[0],
2813 { 0, 0|A(UNCOND_CTI
), { 0 } }
2818 FR30_INSN_RETI
, "reti", "reti",
2820 & fmt_reti
, { 0x9730 },
2821 (PTR
) & fmt_reti_ops
[0],
2822 { 0, 0|A(COND_CTI
)|A(COND_CTI
), { 0 } }
2827 FR30_INSN_BRA
, "bra", "bra",
2828 { { MNEM
, ' ', OP (LABEL9
), 0 } },
2829 & fmt_bra
, { 0xe000 },
2830 (PTR
) & fmt_bra_ops
[0],
2831 { 0, 0|A(COND_CTI
)|A(COND_CTI
), { 0 } }
2836 FR30_INSN_BRAD
, "brad", "bra:d",
2837 { { MNEM
, ' ', OP (LABEL9
), 0 } },
2838 & fmt_bra
, { 0xf000 },
2839 (PTR
) & fmt_bra_ops
[0],
2840 { 0, 0|A(COND_CTI
)|A(DELAY_SLOT
)|A(COND_CTI
), { 0 } }
2845 FR30_INSN_BNO
, "bno", "bno",
2846 { { MNEM
, ' ', OP (LABEL9
), 0 } },
2847 & fmt_bra
, { 0xe100 },
2848 (PTR
) & fmt_bra_ops
[0],
2849 { 0, 0|A(COND_CTI
)|A(COND_CTI
), { 0 } }
2854 FR30_INSN_BNOD
, "bnod", "bno:d",
2855 { { MNEM
, ' ', OP (LABEL9
), 0 } },
2856 & fmt_bra
, { 0xf100 },
2857 (PTR
) & fmt_bra_ops
[0],
2858 { 0, 0|A(COND_CTI
)|A(DELAY_SLOT
)|A(COND_CTI
), { 0 } }
2863 FR30_INSN_BEQ
, "beq", "beq",
2864 { { MNEM
, ' ', OP (LABEL9
), 0 } },
2865 & fmt_beq
, { 0xe200 },
2866 (PTR
) & fmt_beq_ops
[0],
2867 { 0, 0|A(COND_CTI
)|A(COND_CTI
), { 0 } }
2872 FR30_INSN_BEQD
, "beqd", "beq:d",
2873 { { MNEM
, ' ', OP (LABEL9
), 0 } },
2874 & fmt_beq
, { 0xf200 },
2875 (PTR
) & fmt_beq_ops
[0],
2876 { 0, 0|A(COND_CTI
)|A(DELAY_SLOT
)|A(COND_CTI
), { 0 } }
2881 FR30_INSN_BNE
, "bne", "bne",
2882 { { MNEM
, ' ', OP (LABEL9
), 0 } },
2883 & fmt_beq
, { 0xe300 },
2884 (PTR
) & fmt_beq_ops
[0],
2885 { 0, 0|A(COND_CTI
)|A(COND_CTI
), { 0 } }
2890 FR30_INSN_BNED
, "bned", "bne:d",
2891 { { MNEM
, ' ', OP (LABEL9
), 0 } },
2892 & fmt_beq
, { 0xf300 },
2893 (PTR
) & fmt_beq_ops
[0],
2894 { 0, 0|A(COND_CTI
)|A(DELAY_SLOT
)|A(COND_CTI
), { 0 } }
2899 FR30_INSN_BC
, "bc", "bc",
2900 { { MNEM
, ' ', OP (LABEL9
), 0 } },
2901 & fmt_bc
, { 0xe400 },
2902 (PTR
) & fmt_bc_ops
[0],
2903 { 0, 0|A(COND_CTI
)|A(COND_CTI
), { 0 } }
2908 FR30_INSN_BCD
, "bcd", "bc:d",
2909 { { MNEM
, ' ', OP (LABEL9
), 0 } },
2910 & fmt_bc
, { 0xf400 },
2911 (PTR
) & fmt_bc_ops
[0],
2912 { 0, 0|A(COND_CTI
)|A(DELAY_SLOT
)|A(COND_CTI
), { 0 } }
2917 FR30_INSN_BNC
, "bnc", "bnc",
2918 { { MNEM
, ' ', OP (LABEL9
), 0 } },
2919 & fmt_bc
, { 0xe500 },
2920 (PTR
) & fmt_bc_ops
[0],
2921 { 0, 0|A(COND_CTI
)|A(COND_CTI
), { 0 } }
2926 FR30_INSN_BNCD
, "bncd", "bnc:d",
2927 { { MNEM
, ' ', OP (LABEL9
), 0 } },
2928 & fmt_bc
, { 0xf500 },
2929 (PTR
) & fmt_bc_ops
[0],
2930 { 0, 0|A(COND_CTI
)|A(DELAY_SLOT
)|A(COND_CTI
), { 0 } }
2935 FR30_INSN_BN
, "bn", "bn",
2936 { { MNEM
, ' ', OP (LABEL9
), 0 } },
2937 & fmt_bn
, { 0xe600 },
2938 (PTR
) & fmt_bn_ops
[0],
2939 { 0, 0|A(COND_CTI
)|A(COND_CTI
), { 0 } }
2944 FR30_INSN_BND
, "bnd", "bn:d",
2945 { { MNEM
, ' ', OP (LABEL9
), 0 } },
2946 & fmt_bn
, { 0xf600 },
2947 (PTR
) & fmt_bn_ops
[0],
2948 { 0, 0|A(COND_CTI
)|A(DELAY_SLOT
)|A(COND_CTI
), { 0 } }
2953 FR30_INSN_BP
, "bp", "bp",
2954 { { MNEM
, ' ', OP (LABEL9
), 0 } },
2955 & fmt_bn
, { 0xe700 },
2956 (PTR
) & fmt_bn_ops
[0],
2957 { 0, 0|A(COND_CTI
)|A(COND_CTI
), { 0 } }
2962 FR30_INSN_BPD
, "bpd", "bp:d",
2963 { { MNEM
, ' ', OP (LABEL9
), 0 } },
2964 & fmt_bn
, { 0xf700 },
2965 (PTR
) & fmt_bn_ops
[0],
2966 { 0, 0|A(COND_CTI
)|A(DELAY_SLOT
)|A(COND_CTI
), { 0 } }
2971 FR30_INSN_BV
, "bv", "bv",
2972 { { MNEM
, ' ', OP (LABEL9
), 0 } },
2973 & fmt_bv
, { 0xe800 },
2974 (PTR
) & fmt_bv_ops
[0],
2975 { 0, 0|A(COND_CTI
)|A(COND_CTI
), { 0 } }
2980 FR30_INSN_BVD
, "bvd", "bv:d",
2981 { { MNEM
, ' ', OP (LABEL9
), 0 } },
2982 & fmt_bv
, { 0xf800 },
2983 (PTR
) & fmt_bv_ops
[0],
2984 { 0, 0|A(COND_CTI
)|A(DELAY_SLOT
)|A(COND_CTI
), { 0 } }
2989 FR30_INSN_BNV
, "bnv", "bnv",
2990 { { MNEM
, ' ', OP (LABEL9
), 0 } },
2991 & fmt_bv
, { 0xe900 },
2992 (PTR
) & fmt_bv_ops
[0],
2993 { 0, 0|A(COND_CTI
)|A(COND_CTI
), { 0 } }
2998 FR30_INSN_BNVD
, "bnvd", "bnv:d",
2999 { { MNEM
, ' ', OP (LABEL9
), 0 } },
3000 & fmt_bv
, { 0xf900 },
3001 (PTR
) & fmt_bv_ops
[0],
3002 { 0, 0|A(COND_CTI
)|A(DELAY_SLOT
)|A(COND_CTI
), { 0 } }
3007 FR30_INSN_BLT
, "blt", "blt",
3008 { { MNEM
, ' ', OP (LABEL9
), 0 } },
3009 & fmt_blt
, { 0xea00 },
3010 (PTR
) & fmt_blt_ops
[0],
3011 { 0, 0|A(COND_CTI
)|A(COND_CTI
), { 0 } }
3016 FR30_INSN_BLTD
, "bltd", "blt:d",
3017 { { MNEM
, ' ', OP (LABEL9
), 0 } },
3018 & fmt_blt
, { 0xfa00 },
3019 (PTR
) & fmt_blt_ops
[0],
3020 { 0, 0|A(COND_CTI
)|A(DELAY_SLOT
)|A(COND_CTI
), { 0 } }
3025 FR30_INSN_BGE
, "bge", "bge",
3026 { { MNEM
, ' ', OP (LABEL9
), 0 } },
3027 & fmt_blt
, { 0xeb00 },
3028 (PTR
) & fmt_blt_ops
[0],
3029 { 0, 0|A(COND_CTI
)|A(COND_CTI
), { 0 } }
3034 FR30_INSN_BGED
, "bged", "bge:d",
3035 { { MNEM
, ' ', OP (LABEL9
), 0 } },
3036 & fmt_blt
, { 0xfb00 },
3037 (PTR
) & fmt_blt_ops
[0],
3038 { 0, 0|A(COND_CTI
)|A(DELAY_SLOT
)|A(COND_CTI
), { 0 } }
3043 FR30_INSN_BLE
, "ble", "ble",
3044 { { MNEM
, ' ', OP (LABEL9
), 0 } },
3045 & fmt_ble
, { 0xec00 },
3046 (PTR
) & fmt_ble_ops
[0],
3047 { 0, 0|A(COND_CTI
)|A(COND_CTI
), { 0 } }
3052 FR30_INSN_BLED
, "bled", "ble:d",
3053 { { MNEM
, ' ', OP (LABEL9
), 0 } },
3054 & fmt_ble
, { 0xfc00 },
3055 (PTR
) & fmt_ble_ops
[0],
3056 { 0, 0|A(COND_CTI
)|A(DELAY_SLOT
)|A(COND_CTI
), { 0 } }
3061 FR30_INSN_BGT
, "bgt", "bgt",
3062 { { MNEM
, ' ', OP (LABEL9
), 0 } },
3063 & fmt_ble
, { 0xed00 },
3064 (PTR
) & fmt_ble_ops
[0],
3065 { 0, 0|A(COND_CTI
)|A(COND_CTI
), { 0 } }
3070 FR30_INSN_BGTD
, "bgtd", "bgt:d",
3071 { { MNEM
, ' ', OP (LABEL9
), 0 } },
3072 & fmt_ble
, { 0xfd00 },
3073 (PTR
) & fmt_ble_ops
[0],
3074 { 0, 0|A(COND_CTI
)|A(DELAY_SLOT
)|A(COND_CTI
), { 0 } }
3079 FR30_INSN_BLS
, "bls", "bls",
3080 { { MNEM
, ' ', OP (LABEL9
), 0 } },
3081 & fmt_bls
, { 0xee00 },
3082 (PTR
) & fmt_bls_ops
[0],
3083 { 0, 0|A(COND_CTI
)|A(COND_CTI
), { 0 } }
3088 FR30_INSN_BLSD
, "blsd", "bls:d",
3089 { { MNEM
, ' ', OP (LABEL9
), 0 } },
3090 & fmt_bls
, { 0xfe00 },
3091 (PTR
) & fmt_bls_ops
[0],
3092 { 0, 0|A(COND_CTI
)|A(DELAY_SLOT
)|A(COND_CTI
), { 0 } }
3097 FR30_INSN_BHI
, "bhi", "bhi",
3098 { { MNEM
, ' ', OP (LABEL9
), 0 } },
3099 & fmt_bls
, { 0xef00 },
3100 (PTR
) & fmt_bls_ops
[0],
3101 { 0, 0|A(COND_CTI
)|A(COND_CTI
), { 0 } }
3106 FR30_INSN_BHID
, "bhid", "bhi:d",
3107 { { MNEM
, ' ', OP (LABEL9
), 0 } },
3108 & fmt_bls
, { 0xff00 },
3109 (PTR
) & fmt_bls_ops
[0],
3110 { 0, 0|A(COND_CTI
)|A(DELAY_SLOT
)|A(COND_CTI
), { 0 } }
3112 /* dmov $R13,@$dir10 */
3115 FR30_INSN_DMOVR13
, "dmovr13", "dmov",
3116 { { MNEM
, ' ', OP (R13
), ',', '@', OP (DIR10
), 0 } },
3117 & fmt_dmovr13
, { 0x1800 },
3118 (PTR
) & fmt_dmovr13_ops
[0],
3121 /* dmovh $R13,@$dir9 */
3124 FR30_INSN_DMOVR13H
, "dmovr13h", "dmovh",
3125 { { MNEM
, ' ', OP (R13
), ',', '@', OP (DIR9
), 0 } },
3126 & fmt_dmovr13h
, { 0x1900 },
3127 (PTR
) & fmt_dmovr13h_ops
[0],
3130 /* dmovb $R13,@$dir8 */
3133 FR30_INSN_DMOVR13B
, "dmovr13b", "dmovb",
3134 { { MNEM
, ' ', OP (R13
), ',', '@', OP (DIR8
), 0 } },
3135 & fmt_dmovr13b
, { 0x1a00 },
3136 (PTR
) & fmt_dmovr13b_ops
[0],
3139 /* dmov @$R13+,@$dir10 */
3142 FR30_INSN_DMOVR13PI
, "dmovr13pi", "dmov",
3143 { { MNEM
, ' ', '@', OP (R13
), '+', ',', '@', OP (DIR10
), 0 } },
3144 & fmt_dmovr13pi
, { 0x1c00 },
3145 (PTR
) & fmt_dmovr13pi_ops
[0],
3148 /* dmovh @$R13+,@$dir9 */
3151 FR30_INSN_DMOVR13PIH
, "dmovr13pih", "dmovh",
3152 { { MNEM
, ' ', '@', OP (R13
), '+', ',', '@', OP (DIR9
), 0 } },
3153 & fmt_dmovr13pih
, { 0x1d00 },
3154 (PTR
) & fmt_dmovr13pih_ops
[0],
3157 /* dmovb @$R13+,@$dir8 */
3160 FR30_INSN_DMOVR13PIB
, "dmovr13pib", "dmovb",
3161 { { MNEM
, ' ', '@', OP (R13
), '+', ',', '@', OP (DIR8
), 0 } },
3162 & fmt_dmovr13pib
, { 0x1e00 },
3163 (PTR
) & fmt_dmovr13pib_ops
[0],
3166 /* dmov @$R15+,@$dir10 */
3169 FR30_INSN_DMOVR15PI
, "dmovr15pi", "dmov",
3170 { { MNEM
, ' ', '@', OP (R15
), '+', ',', '@', OP (DIR10
), 0 } },
3171 & fmt_dmovr15pi
, { 0x1b00 },
3172 (PTR
) & fmt_dmovr15pi_ops
[0],
3175 /* dmov @$dir10,$R13 */
3178 FR30_INSN_DMOV2R13
, "dmov2r13", "dmov",
3179 { { MNEM
, ' ', '@', OP (DIR10
), ',', OP (R13
), 0 } },
3180 & fmt_dmov2r13
, { 0x800 },
3181 (PTR
) & fmt_dmov2r13_ops
[0],
3184 /* dmovh @$dir9,$R13 */
3187 FR30_INSN_DMOV2R13H
, "dmov2r13h", "dmovh",
3188 { { MNEM
, ' ', '@', OP (DIR9
), ',', OP (R13
), 0 } },
3189 & fmt_dmov2r13h
, { 0x900 },
3190 (PTR
) & fmt_dmov2r13h_ops
[0],
3193 /* dmovb @$dir8,$R13 */
3196 FR30_INSN_DMOV2R13B
, "dmov2r13b", "dmovb",
3197 { { MNEM
, ' ', '@', OP (DIR8
), ',', OP (R13
), 0 } },
3198 & fmt_dmov2r13b
, { 0xa00 },
3199 (PTR
) & fmt_dmov2r13b_ops
[0],
3202 /* dmov @$dir10,@$R13+ */
3205 FR30_INSN_DMOV2R13PI
, "dmov2r13pi", "dmov",
3206 { { MNEM
, ' ', '@', OP (DIR10
), ',', '@', OP (R13
), '+', 0 } },
3207 & fmt_dmov2r13pi
, { 0xc00 },
3208 (PTR
) & fmt_dmov2r13pi_ops
[0],
3211 /* dmovh @$dir9,@$R13+ */
3214 FR30_INSN_DMOV2R13PIH
, "dmov2r13pih", "dmovh",
3215 { { MNEM
, ' ', '@', OP (DIR9
), ',', '@', OP (R13
), '+', 0 } },
3216 & fmt_dmov2r13pih
, { 0xd00 },
3217 (PTR
) & fmt_dmov2r13pih_ops
[0],
3220 /* dmovb @$dir8,@$R13+ */
3223 FR30_INSN_DMOV2R13PIB
, "dmov2r13pib", "dmovb",
3224 { { MNEM
, ' ', '@', OP (DIR8
), ',', '@', OP (R13
), '+', 0 } },
3225 & fmt_dmov2r13pib
, { 0xe00 },
3226 (PTR
) & fmt_dmov2r13pib_ops
[0],
3229 /* dmov @$dir10,@-$R15 */
3232 FR30_INSN_DMOV2R15PD
, "dmov2r15pd", "dmov",
3233 { { MNEM
, ' ', '@', OP (DIR10
), ',', '@', '-', OP (R15
), 0 } },
3234 & fmt_dmov2r15pd
, { 0xb00 },
3235 (PTR
) & fmt_dmov2r15pd_ops
[0],
3238 /* ldres @$Ri+,$u4 */
3241 FR30_INSN_LDRES
, "ldres", "ldres",
3242 { { MNEM
, ' ', '@', OP (RI
), '+', ',', OP (U4
), 0 } },
3243 & fmt_ldres
, { 0xbc00 },
3247 /* stres $u4,@$Ri+ */
3250 FR30_INSN_STRES
, "stres", "stres",
3251 { { MNEM
, ' ', OP (U4
), ',', '@', OP (RI
), '+', 0 } },
3252 & fmt_ldres
, { 0xbd00 },
3256 /* copop $u4c,$ccc,$CRj,$CRi */
3259 FR30_INSN_COPOP
, "copop", "copop",
3260 { { MNEM
, ' ', OP (U4C
), ',', OP (CCC
), ',', OP (CRJ
), ',', OP (CRI
), 0 } },
3261 & fmt_copop
, { 0x9fc0 },
3265 /* copld $u4c,$ccc,$Rjc,$CRi */
3268 FR30_INSN_COPLD
, "copld", "copld",
3269 { { MNEM
, ' ', OP (U4C
), ',', OP (CCC
), ',', OP (RJC
), ',', OP (CRI
), 0 } },
3270 & fmt_copld
, { 0x9fd0 },
3274 /* copst $u4c,$ccc,$CRj,$Ric */
3277 FR30_INSN_COPST
, "copst", "copst",
3278 { { MNEM
, ' ', OP (U4C
), ',', OP (CCC
), ',', OP (CRJ
), ',', OP (RIC
), 0 } },
3279 & fmt_copst
, { 0x9fe0 },
3283 /* copsv $u4c,$ccc,$CRj,$Ric */
3286 FR30_INSN_COPSV
, "copsv", "copsv",
3287 { { MNEM
, ' ', OP (U4C
), ',', OP (CCC
), ',', OP (CRJ
), ',', OP (RIC
), 0 } },
3288 & fmt_copst
, { 0x9ff0 },
3295 FR30_INSN_NOP
, "nop", "nop",
3297 & fmt_nop
, { 0x9fa0 },
3304 FR30_INSN_ANDCCR
, "andccr", "andccr",
3305 { { MNEM
, ' ', OP (U8
), 0 } },
3306 & fmt_andccr
, { 0x8300 },
3307 (PTR
) & fmt_andccr_ops
[0],
3313 FR30_INSN_ORCCR
, "orccr", "orccr",
3314 { { MNEM
, ' ', OP (U8
), 0 } },
3315 & fmt_andccr
, { 0x9300 },
3316 (PTR
) & fmt_andccr_ops
[0],
3322 FR30_INSN_STILM
, "stilm", "stilm",
3323 { { MNEM
, ' ', OP (U8
), 0 } },
3324 & fmt_stilm
, { 0x8700 },
3325 (PTR
) & fmt_stilm_ops
[0],
3331 FR30_INSN_ADDSP
, "addsp", "addsp",
3332 { { MNEM
, ' ', OP (S10
), 0 } },
3333 & fmt_addsp
, { 0xa300 },
3334 (PTR
) & fmt_addsp_ops
[0],
3340 FR30_INSN_EXTSB
, "extsb", "extsb",
3341 { { MNEM
, ' ', OP (RI
), 0 } },
3342 & fmt_extsb
, { 0x9780 },
3343 (PTR
) & fmt_extsb_ops
[0],
3349 FR30_INSN_EXTUB
, "extub", "extub",
3350 { { MNEM
, ' ', OP (RI
), 0 } },
3351 & fmt_extub
, { 0x9790 },
3352 (PTR
) & fmt_extub_ops
[0],
3358 FR30_INSN_EXTSH
, "extsh", "extsh",
3359 { { MNEM
, ' ', OP (RI
), 0 } },
3360 & fmt_extsh
, { 0x97a0 },
3361 (PTR
) & fmt_extsh_ops
[0],
3367 FR30_INSN_EXTUH
, "extuh", "extuh",
3368 { { MNEM
, ' ', OP (RI
), 0 } },
3369 & fmt_extuh
, { 0x97b0 },
3370 (PTR
) & fmt_extuh_ops
[0],
3373 /* ldm0 ($reglist_low_ld) */
3376 FR30_INSN_LDM0
, "ldm0", "ldm0",
3377 { { MNEM
, ' ', '(', OP (REGLIST_LOW_LD
), ')', 0 } },
3378 & fmt_ldm0
, { 0x8c00 },
3379 (PTR
) & fmt_ldm0_ops
[0],
3382 /* ldm1 ($reglist_hi_ld) */
3385 FR30_INSN_LDM1
, "ldm1", "ldm1",
3386 { { MNEM
, ' ', '(', OP (REGLIST_HI_LD
), ')', 0 } },
3387 & fmt_ldm1
, { 0x8d00 },
3388 (PTR
) & fmt_ldm1_ops
[0],
3391 /* stm0 ($reglist_low_st) */
3394 FR30_INSN_STM0
, "stm0", "stm0",
3395 { { MNEM
, ' ', '(', OP (REGLIST_LOW_ST
), ')', 0 } },
3396 & fmt_stm0
, { 0x8e00 },
3397 (PTR
) & fmt_stm0_ops
[0],
3400 /* stm1 ($reglist_hi_st) */
3403 FR30_INSN_STM1
, "stm1", "stm1",
3404 { { MNEM
, ' ', '(', OP (REGLIST_HI_ST
), ')', 0 } },
3405 & fmt_stm1
, { 0x8f00 },
3406 (PTR
) & fmt_stm1_ops
[0],
3412 FR30_INSN_ENTER
, "enter", "enter",
3413 { { MNEM
, ' ', OP (U10
), 0 } },
3414 & fmt_enter
, { 0xf00 },
3415 (PTR
) & fmt_enter_ops
[0],
3421 FR30_INSN_LEAVE
, "leave", "leave",
3423 & fmt_leave
, { 0x9f90 },
3424 (PTR
) & fmt_leave_ops
[0],
3430 FR30_INSN_XCHB
, "xchb", "xchb",
3431 { { MNEM
, ' ', '@', OP (RJ
), ',', OP (RI
), 0 } },
3432 & fmt_xchb
, { 0x8a00 },
3433 (PTR
) & fmt_xchb_ops
[0],
3442 static const CGEN_INSN_TABLE insn_table
=
3444 & fr30_cgen_insn_table_entries
[0],
3450 /* Formats for ALIAS macro-insns. */
3452 #define F(f) & fr30_cgen_ifld_table[CONCAT2 (FR30_,f)]
3454 static const CGEN_IFMT fmt_ldi8m
= {
3455 16, 16, 0xf000, { F (F_OP1
), F (F_I8
), F (F_RI
), 0 }
3458 static const CGEN_IFMT fmt_ldi20m
= {
3459 16, 32, 0xff00, { F (F_OP1
), F (F_I20
), F (F_OP2
), F (F_RI
), 0 }
3462 static const CGEN_IFMT fmt_ldi32m
= {
3463 16, 48, 0xfff0, { F (F_OP1
), F (F_I32
), F (F_OP2
), F (F_OP3
), F (F_RI
), 0 }
3468 /* Each non-simple macro entry points to an array of expansion possibilities. */
3470 #define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
3471 #define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
3472 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
3474 /* The macro instruction table. */
3476 static const CGEN_INSN macro_insn_table_entries
[] =
3481 -1, "ldi8m", "ldi8",
3482 { { MNEM
, ' ', OP (I8
), ',', OP (RI
), 0 } },
3483 & fmt_ldi8m
, { 0xc000 },
3485 { 0, 0|A(NO_DIS
)|A(ALIAS
), { 0 } }
3487 /* ldi20 $i20,$Ri */
3490 -1, "ldi20m", "ldi20",
3491 { { MNEM
, ' ', OP (I20
), ',', OP (RI
), 0 } },
3492 & fmt_ldi20m
, { 0x9b00 },
3494 { 0, 0|A(NO_DIS
)|A(ALIAS
), { 0 } }
3496 /* ldi32 $i32,$Ri */
3499 -1, "ldi32m", "ldi32",
3500 { { MNEM
, ' ', OP (I32
), ',', OP (RI
), 0 } },
3501 & fmt_ldi32m
, { 0x9f80 },
3503 { 0, 0|A(NO_DIS
)|A(ALIAS
), { 0 } }
3511 static const CGEN_INSN_TABLE macro_insn_table
=
3513 & macro_insn_table_entries
[0],
3515 (sizeof (macro_insn_table_entries
) /
3516 sizeof (macro_insn_table_entries
[0])),
3525 /* Return non-zero if INSN is to be added to the hash table.
3526 Targets are free to override CGEN_{ASM,DIS}_HASH_P in the .opc file. */
3529 asm_hash_insn_p (insn
)
3530 const CGEN_INSN
* insn
;
3532 return CGEN_ASM_HASH_P (insn
);
3536 dis_hash_insn_p (insn
)
3537 const CGEN_INSN
* insn
;
3539 /* If building the hash table and the NO-DIS attribute is present,
3541 if (CGEN_INSN_ATTR (insn
, CGEN_INSN_NO_DIS
))
3543 return CGEN_DIS_HASH_P (insn
);
3546 /* The result is the hash value of the insn.
3547 Targets are free to override CGEN_{ASM,DIS}_HASH in the .opc file. */
3550 asm_hash_insn (mnem
)
3553 return CGEN_ASM_HASH (mnem
);
3556 /* BUF is a pointer to the insn's bytes in target order.
3557 VALUE is an integer of the first CGEN_BASE_INSN_BITSIZE bits,
3561 dis_hash_insn (buf
, value
)
3563 CGEN_INSN_INT value
;
3565 return CGEN_DIS_HASH (buf
, value
);
3568 /* Initialize an opcode table and return a descriptor.
3569 It's much like opening a file, and must be the first function called. */
3572 fr30_cgen_opcode_open (mach
, endian
)
3574 enum cgen_endian endian
;
3576 CGEN_OPCODE_TABLE
* table
= (CGEN_OPCODE_TABLE
*) xmalloc (sizeof (CGEN_OPCODE_TABLE
));
3585 memset (table
, 0, sizeof (*table
));
3587 CGEN_OPCODE_MACH (table
) = mach
;
3588 CGEN_OPCODE_ENDIAN (table
) = endian
;
3589 /* FIXME: for the sparc case we can determine insn-endianness statically.
3590 The worry here is where both data and insn endian can be independently
3591 chosen, in which case this function will need another argument.
3592 Actually, will want to allow for more arguments in the future anyway. */
3593 CGEN_OPCODE_INSN_ENDIAN (table
) = endian
;
3595 CGEN_OPCODE_HW_LIST (table
) = & fr30_cgen_hw_entries
[0];
3597 CGEN_OPCODE_IFLD_TABLE (table
) = & fr30_cgen_ifld_table
[0];
3599 CGEN_OPCODE_OPERAND_TABLE (table
) = & fr30_cgen_operand_table
[0];
3601 * CGEN_OPCODE_INSN_TABLE (table
) = insn_table
;
3603 * CGEN_OPCODE_MACRO_INSN_TABLE (table
) = macro_insn_table
;
3605 CGEN_OPCODE_ASM_HASH_P (table
) = asm_hash_insn_p
;
3606 CGEN_OPCODE_ASM_HASH (table
) = asm_hash_insn
;
3607 CGEN_OPCODE_ASM_HASH_SIZE (table
) = CGEN_ASM_HASH_SIZE
;
3609 CGEN_OPCODE_DIS_HASH_P (table
) = dis_hash_insn_p
;
3610 CGEN_OPCODE_DIS_HASH (table
) = dis_hash_insn
;
3611 CGEN_OPCODE_DIS_HASH_SIZE (table
) = CGEN_DIS_HASH_SIZE
;
3613 return (CGEN_OPCODE_DESC
) table
;
3616 /* Close an opcode table. */
3619 fr30_cgen_opcode_close (desc
)
3620 CGEN_OPCODE_DESC desc
;
3625 /* Getting values from cgen_fields is handled by a collection of functions.
3626 They are distinguished by the type of the VALUE argument they return.
3627 TODO: floating point, inlining support, remove cases where result type
3631 fr30_cgen_get_int_operand (opindex
, fields
)
3633 const CGEN_FIELDS
* fields
;
3639 case FR30_OPERAND_RI
:
3640 value
= fields
->f_Ri
;
3642 case FR30_OPERAND_RJ
:
3643 value
= fields
->f_Rj
;
3645 case FR30_OPERAND_RIC
:
3646 value
= fields
->f_Ric
;
3648 case FR30_OPERAND_RJC
:
3649 value
= fields
->f_Rjc
;
3651 case FR30_OPERAND_CRI
:
3652 value
= fields
->f_CRi
;
3654 case FR30_OPERAND_CRJ
:
3655 value
= fields
->f_CRj
;
3657 case FR30_OPERAND_RS1
:
3658 value
= fields
->f_Rs1
;
3660 case FR30_OPERAND_RS2
:
3661 value
= fields
->f_Rs2
;
3663 case FR30_OPERAND_R13
:
3664 value
= fields
->f_nil
;
3666 case FR30_OPERAND_R14
:
3667 value
= fields
->f_nil
;
3669 case FR30_OPERAND_R15
:
3670 value
= fields
->f_nil
;
3672 case FR30_OPERAND_PS
:
3673 value
= fields
->f_nil
;
3675 case FR30_OPERAND_U4
:
3676 value
= fields
->f_u4
;
3678 case FR30_OPERAND_U4C
:
3679 value
= fields
->f_u4c
;
3681 case FR30_OPERAND_U8
:
3682 value
= fields
->f_u8
;
3684 case FR30_OPERAND_I8
:
3685 value
= fields
->f_i8
;
3687 case FR30_OPERAND_UDISP6
:
3688 value
= fields
->f_udisp6
;
3690 case FR30_OPERAND_DISP8
:
3691 value
= fields
->f_disp8
;
3693 case FR30_OPERAND_DISP9
:
3694 value
= fields
->f_disp9
;
3696 case FR30_OPERAND_DISP10
:
3697 value
= fields
->f_disp10
;
3699 case FR30_OPERAND_S10
:
3700 value
= fields
->f_s10
;
3702 case FR30_OPERAND_U10
:
3703 value
= fields
->f_u10
;
3705 case FR30_OPERAND_I32
:
3706 value
= fields
->f_i32
;
3708 case FR30_OPERAND_M4
:
3709 value
= fields
->f_m4
;
3711 case FR30_OPERAND_I20
:
3712 value
= fields
->f_i20
;
3714 case FR30_OPERAND_DIR8
:
3715 value
= fields
->f_dir8
;
3717 case FR30_OPERAND_DIR9
:
3718 value
= fields
->f_dir9
;
3720 case FR30_OPERAND_DIR10
:
3721 value
= fields
->f_dir10
;
3723 case FR30_OPERAND_LABEL9
:
3724 value
= fields
->f_rel9
;
3726 case FR30_OPERAND_LABEL12
:
3727 value
= fields
->f_rel12
;
3729 case FR30_OPERAND_REGLIST_LOW_LD
:
3730 value
= fields
->f_reglist_low_ld
;
3732 case FR30_OPERAND_REGLIST_HI_LD
:
3733 value
= fields
->f_reglist_hi_ld
;
3735 case FR30_OPERAND_REGLIST_LOW_ST
:
3736 value
= fields
->f_reglist_low_st
;
3738 case FR30_OPERAND_REGLIST_HI_ST
:
3739 value
= fields
->f_reglist_hi_st
;
3741 case FR30_OPERAND_CC
:
3742 value
= fields
->f_cc
;
3744 case FR30_OPERAND_CCC
:
3745 value
= fields
->f_ccc
;
3749 /* xgettext:c-format */
3750 fprintf (stderr
, _("Unrecognized field %d while getting int operand.\n"),
3759 fr30_cgen_get_vma_operand (opindex
, fields
)
3761 const CGEN_FIELDS
* fields
;
3767 case FR30_OPERAND_RI
:
3768 value
= fields
->f_Ri
;
3770 case FR30_OPERAND_RJ
:
3771 value
= fields
->f_Rj
;
3773 case FR30_OPERAND_RIC
:
3774 value
= fields
->f_Ric
;
3776 case FR30_OPERAND_RJC
:
3777 value
= fields
->f_Rjc
;
3779 case FR30_OPERAND_CRI
:
3780 value
= fields
->f_CRi
;
3782 case FR30_OPERAND_CRJ
:
3783 value
= fields
->f_CRj
;
3785 case FR30_OPERAND_RS1
:
3786 value
= fields
->f_Rs1
;
3788 case FR30_OPERAND_RS2
:
3789 value
= fields
->f_Rs2
;
3791 case FR30_OPERAND_R13
:
3792 value
= fields
->f_nil
;
3794 case FR30_OPERAND_R14
:
3795 value
= fields
->f_nil
;
3797 case FR30_OPERAND_R15
:
3798 value
= fields
->f_nil
;
3800 case FR30_OPERAND_PS
:
3801 value
= fields
->f_nil
;
3803 case FR30_OPERAND_U4
:
3804 value
= fields
->f_u4
;
3806 case FR30_OPERAND_U4C
:
3807 value
= fields
->f_u4c
;
3809 case FR30_OPERAND_U8
:
3810 value
= fields
->f_u8
;
3812 case FR30_OPERAND_I8
:
3813 value
= fields
->f_i8
;
3815 case FR30_OPERAND_UDISP6
:
3816 value
= fields
->f_udisp6
;
3818 case FR30_OPERAND_DISP8
:
3819 value
= fields
->f_disp8
;
3821 case FR30_OPERAND_DISP9
:
3822 value
= fields
->f_disp9
;
3824 case FR30_OPERAND_DISP10
:
3825 value
= fields
->f_disp10
;
3827 case FR30_OPERAND_S10
:
3828 value
= fields
->f_s10
;
3830 case FR30_OPERAND_U10
:
3831 value
= fields
->f_u10
;
3833 case FR30_OPERAND_I32
:
3834 value
= fields
->f_i32
;
3836 case FR30_OPERAND_M4
:
3837 value
= fields
->f_m4
;
3839 case FR30_OPERAND_I20
:
3840 value
= fields
->f_i20
;
3842 case FR30_OPERAND_DIR8
:
3843 value
= fields
->f_dir8
;
3845 case FR30_OPERAND_DIR9
:
3846 value
= fields
->f_dir9
;
3848 case FR30_OPERAND_DIR10
:
3849 value
= fields
->f_dir10
;
3851 case FR30_OPERAND_LABEL9
:
3852 value
= fields
->f_rel9
;
3854 case FR30_OPERAND_LABEL12
:
3855 value
= fields
->f_rel12
;
3857 case FR30_OPERAND_REGLIST_LOW_LD
:
3858 value
= fields
->f_reglist_low_ld
;
3860 case FR30_OPERAND_REGLIST_HI_LD
:
3861 value
= fields
->f_reglist_hi_ld
;
3863 case FR30_OPERAND_REGLIST_LOW_ST
:
3864 value
= fields
->f_reglist_low_st
;
3866 case FR30_OPERAND_REGLIST_HI_ST
:
3867 value
= fields
->f_reglist_hi_st
;
3869 case FR30_OPERAND_CC
:
3870 value
= fields
->f_cc
;
3872 case FR30_OPERAND_CCC
:
3873 value
= fields
->f_ccc
;
3877 /* xgettext:c-format */
3878 fprintf (stderr
, _("Unrecognized field %d while getting vma operand.\n"),
3886 /* Stuffing values in cgen_fields is handled by a collection of functions.
3887 They are distinguished by the type of the VALUE argument they accept.
3888 TODO: floating point, inlining support, remove cases where argument type
3892 fr30_cgen_set_int_operand (opindex
, fields
, value
)
3894 CGEN_FIELDS
* fields
;
3899 case FR30_OPERAND_RI
:
3900 fields
->f_Ri
= value
;
3902 case FR30_OPERAND_RJ
:
3903 fields
->f_Rj
= value
;
3905 case FR30_OPERAND_RIC
:
3906 fields
->f_Ric
= value
;
3908 case FR30_OPERAND_RJC
:
3909 fields
->f_Rjc
= value
;
3911 case FR30_OPERAND_CRI
:
3912 fields
->f_CRi
= value
;
3914 case FR30_OPERAND_CRJ
:
3915 fields
->f_CRj
= value
;
3917 case FR30_OPERAND_RS1
:
3918 fields
->f_Rs1
= value
;
3920 case FR30_OPERAND_RS2
:
3921 fields
->f_Rs2
= value
;
3923 case FR30_OPERAND_R13
:
3924 fields
->f_nil
= value
;
3926 case FR30_OPERAND_R14
:
3927 fields
->f_nil
= value
;
3929 case FR30_OPERAND_R15
:
3930 fields
->f_nil
= value
;
3932 case FR30_OPERAND_PS
:
3933 fields
->f_nil
= value
;
3935 case FR30_OPERAND_U4
:
3936 fields
->f_u4
= value
;
3938 case FR30_OPERAND_U4C
:
3939 fields
->f_u4c
= value
;
3941 case FR30_OPERAND_U8
:
3942 fields
->f_u8
= value
;
3944 case FR30_OPERAND_I8
:
3945 fields
->f_i8
= value
;
3947 case FR30_OPERAND_UDISP6
:
3948 fields
->f_udisp6
= value
;
3950 case FR30_OPERAND_DISP8
:
3951 fields
->f_disp8
= value
;
3953 case FR30_OPERAND_DISP9
:
3954 fields
->f_disp9
= value
;
3956 case FR30_OPERAND_DISP10
:
3957 fields
->f_disp10
= value
;
3959 case FR30_OPERAND_S10
:
3960 fields
->f_s10
= value
;
3962 case FR30_OPERAND_U10
:
3963 fields
->f_u10
= value
;
3965 case FR30_OPERAND_I32
:
3966 fields
->f_i32
= value
;
3968 case FR30_OPERAND_M4
:
3969 fields
->f_m4
= value
;
3971 case FR30_OPERAND_I20
:
3972 fields
->f_i20
= value
;
3974 case FR30_OPERAND_DIR8
:
3975 fields
->f_dir8
= value
;
3977 case FR30_OPERAND_DIR9
:
3978 fields
->f_dir9
= value
;
3980 case FR30_OPERAND_DIR10
:
3981 fields
->f_dir10
= value
;
3983 case FR30_OPERAND_LABEL9
:
3984 fields
->f_rel9
= value
;
3986 case FR30_OPERAND_LABEL12
:
3987 fields
->f_rel12
= value
;
3989 case FR30_OPERAND_REGLIST_LOW_LD
:
3990 fields
->f_reglist_low_ld
= value
;
3992 case FR30_OPERAND_REGLIST_HI_LD
:
3993 fields
->f_reglist_hi_ld
= value
;
3995 case FR30_OPERAND_REGLIST_LOW_ST
:
3996 fields
->f_reglist_low_st
= value
;
3998 case FR30_OPERAND_REGLIST_HI_ST
:
3999 fields
->f_reglist_hi_st
= value
;
4001 case FR30_OPERAND_CC
:
4002 fields
->f_cc
= value
;
4004 case FR30_OPERAND_CCC
:
4005 fields
->f_ccc
= value
;
4009 /* xgettext:c-format */
4010 fprintf (stderr
, _("Unrecognized field %d while setting int operand.\n"),
4017 fr30_cgen_set_vma_operand (opindex
, fields
, value
)
4019 CGEN_FIELDS
* fields
;
4024 case FR30_OPERAND_RI
:
4025 fields
->f_Ri
= value
;
4027 case FR30_OPERAND_RJ
:
4028 fields
->f_Rj
= value
;
4030 case FR30_OPERAND_RIC
:
4031 fields
->f_Ric
= value
;
4033 case FR30_OPERAND_RJC
:
4034 fields
->f_Rjc
= value
;
4036 case FR30_OPERAND_CRI
:
4037 fields
->f_CRi
= value
;
4039 case FR30_OPERAND_CRJ
:
4040 fields
->f_CRj
= value
;
4042 case FR30_OPERAND_RS1
:
4043 fields
->f_Rs1
= value
;
4045 case FR30_OPERAND_RS2
:
4046 fields
->f_Rs2
= value
;
4048 case FR30_OPERAND_R13
:
4049 fields
->f_nil
= value
;
4051 case FR30_OPERAND_R14
:
4052 fields
->f_nil
= value
;
4054 case FR30_OPERAND_R15
:
4055 fields
->f_nil
= value
;
4057 case FR30_OPERAND_PS
:
4058 fields
->f_nil
= value
;
4060 case FR30_OPERAND_U4
:
4061 fields
->f_u4
= value
;
4063 case FR30_OPERAND_U4C
:
4064 fields
->f_u4c
= value
;
4066 case FR30_OPERAND_U8
:
4067 fields
->f_u8
= value
;
4069 case FR30_OPERAND_I8
:
4070 fields
->f_i8
= value
;
4072 case FR30_OPERAND_UDISP6
:
4073 fields
->f_udisp6
= value
;
4075 case FR30_OPERAND_DISP8
:
4076 fields
->f_disp8
= value
;
4078 case FR30_OPERAND_DISP9
:
4079 fields
->f_disp9
= value
;
4081 case FR30_OPERAND_DISP10
:
4082 fields
->f_disp10
= value
;
4084 case FR30_OPERAND_S10
:
4085 fields
->f_s10
= value
;
4087 case FR30_OPERAND_U10
:
4088 fields
->f_u10
= value
;
4090 case FR30_OPERAND_I32
:
4091 fields
->f_i32
= value
;
4093 case FR30_OPERAND_M4
:
4094 fields
->f_m4
= value
;
4096 case FR30_OPERAND_I20
:
4097 fields
->f_i20
= value
;
4099 case FR30_OPERAND_DIR8
:
4100 fields
->f_dir8
= value
;
4102 case FR30_OPERAND_DIR9
:
4103 fields
->f_dir9
= value
;
4105 case FR30_OPERAND_DIR10
:
4106 fields
->f_dir10
= value
;
4108 case FR30_OPERAND_LABEL9
:
4109 fields
->f_rel9
= value
;
4111 case FR30_OPERAND_LABEL12
:
4112 fields
->f_rel12
= value
;
4114 case FR30_OPERAND_REGLIST_LOW_LD
:
4115 fields
->f_reglist_low_ld
= value
;
4117 case FR30_OPERAND_REGLIST_HI_LD
:
4118 fields
->f_reglist_hi_ld
= value
;
4120 case FR30_OPERAND_REGLIST_LOW_ST
:
4121 fields
->f_reglist_low_st
= value
;
4123 case FR30_OPERAND_REGLIST_HI_ST
:
4124 fields
->f_reglist_hi_st
= value
;
4126 case FR30_OPERAND_CC
:
4127 fields
->f_cc
= value
;
4129 case FR30_OPERAND_CCC
:
4130 fields
->f_ccc
= value
;
4134 /* xgettext:c-format */
4135 fprintf (stderr
, _("Unrecognized field %d while setting vma operand.\n"),