opcodes/fr30-opc.h

   1 /* Instruction description for fr30.
   2
   3 THIS FILE IS MACHINE GENERATED WITH CGEN.
   4
   5 Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
   6
   7 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
   8
   9 This program is free software; you can redistribute it and/or modify
  10 it under the terms of the GNU General Public License as published by
  11 the Free Software Foundation; either version 2, or (at your option)
  12 any later version.
  13
  14 This program is distributed in the hope that it will be useful,
  15 but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 GNU General Public License for more details.
  18
  19 You should have received a copy of the GNU General Public License along
  20 with this program; if not, write to the Free Software Foundation, Inc.,
  21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  22
  23 */
  24
  25 #ifndef FR30_OPC_H
  26 #define FR30_OPC_H
  27
  28 #define CGEN_ARCH fr30
  29
  30 /* Given symbol S, return fr30_cgen_<S>.  */
  31 #define CGEN_SYM(s) CONCAT3 (fr30,_cgen_,s)
  32
  33 /* Selected cpu families.  */
  34 #define HAVE_CPU_FR30BF
  35
  36 #define CGEN_INSN_LSB0_P 0
  37 #define CGEN_WORD_BITSIZE 32
  38 #define CGEN_DEFAULT_INSN_BITSIZE 16
  39 #define CGEN_BASE_INSN_BITSIZE 16
  40 #define CGEN_MIN_INSN_BITSIZE 16
  41 #define CGEN_MAX_INSN_BITSIZE 48
  42 #define CGEN_DEFAULT_INSN_SIZE (CGEN_DEFAULT_INSN_BITSIZE / 8)
  43 #define CGEN_BASE_INSN_SIZE (CGEN_BASE_INSN_BITSIZE / 8)
  44 #define CGEN_MIN_INSN_SIZE (CGEN_MIN_INSN_BITSIZE / 8)
  45 #define CGEN_MAX_INSN_SIZE (CGEN_MAX_INSN_BITSIZE / 8)
  46 #define CGEN_INT_INSN_P 0
  47
  48 /* FIXME: Need to compute CGEN_MAX_SYNTAX_BYTES.  */
  49
  50 /* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
  51    e.g. In "b,a foo" the ",a" is an operand.  If mnemonics have operands
  52    we can't hash on everything up to the space.  */
  53 #define CGEN_MNEMONIC_OPERANDS
  54 /* Maximum number of operands any insn or macro-insn has.  */
  55 #define CGEN_MAX_INSN_OPERANDS 16
  56
  57 /* Maximum number of fields in an instruction.  */
  58 #define CGEN_MAX_IFMT_OPERANDS 7
  59
  60 /* Enums.  */
  61
  62 /* Enum declaration for insn op1 enums.  */
  63 typedef enum insn_op1 {
  64   OP1_0, OP1_1, OP1_2, OP1_3
  65  , OP1_4, OP1_5, OP1_6, OP1_7
  66  , OP1_8, OP1_9, OP1_A, OP1_B
  67  , OP1_C, OP1_D, OP1_E, OP1_F
  68 } INSN_OP1;
  69
  70 /* Enum declaration for insn op2 enums.  */
  71 typedef enum insn_op2 {
  72   OP2_0, OP2_1, OP2_2, OP2_3
  73  , OP2_4, OP2_5, OP2_6, OP2_7
  74  , OP2_8, OP2_9, OP2_A, OP2_B
  75  , OP2_C, OP2_D, OP2_E, OP2_F
  76 } INSN_OP2;
  77
  78 /* Enum declaration for insn op3 enums.  */
  79 typedef enum insn_op3 {
  80   OP3_0, OP3_1, OP3_2, OP3_3
  81  , OP3_4, OP3_5, OP3_6, OP3_7
  82  , OP3_8, OP3_9, OP3_A, OP3_B
  83  , OP3_C, OP3_D, OP3_E, OP3_F
  84 } INSN_OP3;
  85
  86 /* Enum declaration for insn op4 enums.  */
  87 typedef enum insn_op4 {
  88   OP4_0
  89 } INSN_OP4;
  90
  91 /* Enum declaration for insn op5 enums.  */
  92 typedef enum insn_op5 {
  93   OP5_0, OP5_1
  94 } INSN_OP5;
  95
  96 /* Enum declaration for insn cc enums.  */
  97 typedef enum insn_cc {
  98   CC_RA, CC_NO, CC_EQ, CC_NE
  99  , CC_C, CC_NC, CC_N, CC_P
 100  , CC_V, CC_NV, CC_LT, CC_GE
 101  , CC_LE, CC_GT, CC_LS, CC_HI
 102 } INSN_CC;
 103
 104 /* Enum declaration for general registers.  */
 105 typedef enum h_gr {
 106   H_GR_R0 = 0, H_GR_R1 = 1, H_GR_R2 = 2, H_GR_R3 = 3
 107  , H_GR_R4 = 4, H_GR_R5 = 5, H_GR_R6 = 6, H_GR_R7 = 7
 108  , H_GR_R8 = 8, H_GR_R9 = 9, H_GR_R10 = 10, H_GR_R11 = 11
 109  , H_GR_R12 = 12, H_GR_R13 = 13, H_GR_R14 = 14, H_GR_R15 = 15
 110  , H_GR_AC = 13, H_GR_FP = 14, H_GR_SP = 15
 111 } H_GR;
 112
 113 /* Enum declaration for coprocessor registers.  */
 114 typedef enum h_cr {
 115   H_CR_CR0, H_CR_CR1, H_CR_CR2, H_CR_CR3
 116  , H_CR_CR4, H_CR_CR5, H_CR_CR6, H_CR_CR7
 117  , H_CR_CR8, H_CR_CR9, H_CR_CR10, H_CR_CR11
 118  , H_CR_CR12, H_CR_CR13, H_CR_CR14, H_CR_CR15
 119 } H_CR;
 120
 121 /* Enum declaration for dedicated registers.  */
 122 typedef enum h_dr {
 123   H_DR_TBR, H_DR_RP, H_DR_SSP, H_DR_USP
 124  , H_DR_MDH, H_DR_MDL
 125 } H_DR;
 126
 127 /* Enum declaration for program status.  */
 128 typedef enum h_ps {
 129   H_PS_PS
 130 } H_PS;
 131
 132 /* Enum declaration for General Register 13 explicitely required.  */
 133 typedef enum h_r13 {
 134   H_R13_R13
 135 } H_R13;
 136
 137 /* Enum declaration for General Register 14 explicitely required.  */
 138 typedef enum h_r14 {
 139   H_R14_R14
 140 } H_R14;
 141
 142 /* Enum declaration for General Register 15 explicitely required.  */
 143 typedef enum h_r15 {
 144   H_R15_R15
 145 } H_R15;
 146
 147 /* Attributes.  */
 148
 149 /* Enum declaration for machine type selection.  */
 150 typedef enum mach_attr {
 151   MACH_BASE, MACH_FR30, MACH_MAX
 152 } MACH_ATTR;
 153
 154 /* Number of architecture variants.  */
 155 #define MAX_MACHS ((int) MACH_MAX)
 156
 157 /* Ifield attribute indices.  */
 158
 159 /* Enum declaration for cgen_ifld attrs.  */
 160 typedef enum cgen_ifld_attr {
 161   CGEN_IFLD_MACH, CGEN_IFLD_VIRTUAL, CGEN_IFLD_UNSIGNED, CGEN_IFLD_PCREL_ADDR
 162  , CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED, CGEN_IFLD_SIGN_OPT
 163 } CGEN_IFLD_ATTR;
 164
 165 /* Number of non-boolean elements in cgen_ifld.  */
 166 #define CGEN_IFLD_NBOOL_ATTRS ((int) CGEN_IFLD_VIRTUAL)
 167
 168 /* Enum declaration for fr30 ifield types.  */
 169 typedef enum ifield_type {
 170   FR30_F_NIL, FR30_F_OP1, FR30_F_OP2, FR30_F_OP3
 171  , FR30_F_OP4, FR30_F_OP5, FR30_F_CC, FR30_F_CCC
 172  , FR30_F_RJ, FR30_F_RI, FR30_F_RS1, FR30_F_RS2
 173  , FR30_F_RJC, FR30_F_RIC, FR30_F_CRJ, FR30_F_CRI
 174  , FR30_F_U4, FR30_F_U4C, FR30_F_I4, FR30_F_M4
 175  , FR30_F_U8, FR30_F_I8, FR30_F_I20_4, FR30_F_I20_16
 176  , FR30_F_I20, FR30_F_I32, FR30_F_UDISP6, FR30_F_DISP8
 177  , FR30_F_DISP9, FR30_F_DISP10, FR30_F_S10, FR30_F_U10
 178  , FR30_F_REL9, FR30_F_DIR8, FR30_F_DIR9, FR30_F_DIR10
 179  , FR30_F_REL12, FR30_F_REGLIST_HI_ST, FR30_F_REGLIST_LOW_ST, FR30_F_REGLIST_HI_LD
 180  , FR30_F_REGLIST_LOW_LD, FR30_F_MAX
 181 } IFIELD_TYPE;
 182
 183 #define MAX_IFLD ((int) FR30_F_MAX)
 184
 185 /* Hardware attribute indices.  */
 186
 187 /* Enum declaration for cgen_hw attrs.  */
 188 typedef enum cgen_hw_attr {
 189   CGEN_HW_MACH, CGEN_HW_VIRTUAL, CGEN_HW_UNSIGNED, CGEN_HW_SIGNED
 190  , CGEN_HW_CACHE_ADDR, CGEN_HW_FUN_ACCESS, CGEN_HW_PC, CGEN_HW_PROFILE
 191 } CGEN_HW_ATTR;
 192
 193 /* Number of non-boolean elements in cgen_hw.  */
 194 #define CGEN_HW_NBOOL_ATTRS ((int) CGEN_HW_VIRTUAL)
 195
 196 /* Enum declaration for fr30 hardware types.  */
 197 typedef enum hw_type {
 198   HW_H_PC, HW_H_MEMORY, HW_H_SINT, HW_H_UINT
 199  , HW_H_ADDR, HW_H_IADDR, HW_H_GR, HW_H_CR
 200  , HW_H_DR, HW_H_PS, HW_H_R13, HW_H_R14
 201  , HW_H_R15, HW_H_NBIT, HW_H_ZBIT, HW_H_VBIT
 202  , HW_H_CBIT, HW_H_IBIT, HW_H_SBIT, HW_H_TBIT
 203  , HW_H_D0BIT, HW_H_D1BIT, HW_H_CCR, HW_H_SCR
 204  , HW_H_ILM, HW_MAX
 205 } HW_TYPE;
 206
 207 #define MAX_HW ((int) HW_MAX)
 208
 209 /* Operand attribute indices.  */
 210
 211 /* Enum declaration for cgen_operand attrs.  */
 212 typedef enum cgen_operand_attr {
 213   CGEN_OPERAND_MACH, CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_UNSIGNED, CGEN_OPERAND_PCREL_ADDR
 214  , CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX
 215  , CGEN_OPERAND_SEM_ONLY, CGEN_OPERAND_HASH_PREFIX
 216 } CGEN_OPERAND_ATTR;
 217
 218 /* Number of non-boolean elements in cgen_operand.  */
 219 #define CGEN_OPERAND_NBOOL_ATTRS ((int) CGEN_OPERAND_VIRTUAL)
 220
 221 /* Enum declaration for fr30 operand types.  */
 222 typedef enum cgen_operand_type {
 223   FR30_OPERAND_PC, FR30_OPERAND_RI, FR30_OPERAND_RJ, FR30_OPERAND_RIC
 224  , FR30_OPERAND_RJC, FR30_OPERAND_CRI, FR30_OPERAND_CRJ, FR30_OPERAND_RS1
 225  , FR30_OPERAND_RS2, FR30_OPERAND_R13, FR30_OPERAND_R14, FR30_OPERAND_R15
 226  , FR30_OPERAND_PS, FR30_OPERAND_U4, FR30_OPERAND_U4C, FR30_OPERAND_U8
 227  , FR30_OPERAND_I8, FR30_OPERAND_UDISP6, FR30_OPERAND_DISP8, FR30_OPERAND_DISP9
 228  , FR30_OPERAND_DISP10, FR30_OPERAND_S10, FR30_OPERAND_U10, FR30_OPERAND_I32
 229  , FR30_OPERAND_M4, FR30_OPERAND_I20, FR30_OPERAND_DIR8, FR30_OPERAND_DIR9
 230  , FR30_OPERAND_DIR10, FR30_OPERAND_LABEL9, FR30_OPERAND_LABEL12, FR30_OPERAND_REGLIST_LOW_LD
 231  , FR30_OPERAND_REGLIST_HI_LD, FR30_OPERAND_REGLIST_LOW_ST, FR30_OPERAND_REGLIST_HI_ST, FR30_OPERAND_CC
 232  , FR30_OPERAND_CCC, FR30_OPERAND_NBIT, FR30_OPERAND_VBIT, FR30_OPERAND_ZBIT
 233  , FR30_OPERAND_CBIT, FR30_OPERAND_IBIT, FR30_OPERAND_SBIT, FR30_OPERAND_TBIT
 234  , FR30_OPERAND_D0BIT, FR30_OPERAND_D1BIT, FR30_OPERAND_CCR, FR30_OPERAND_SCR
 235  , FR30_OPERAND_ILM, FR30_OPERAND_MAX
 236 } CGEN_OPERAND_TYPE;
 237
 238 /* Number of operands types.  */
 239 #define MAX_OPERANDS ((int) FR30_OPERAND_MAX)
 240
 241 /* Maximum number of operands referenced by any insn.  */
 242 #define MAX_OPERAND_INSTANCES 12
 243
 244 /* Insn attribute indices.  */
 245
 246 /* Enum declaration for cgen_insn attrs.  */
 247 typedef enum cgen_insn_attr {
 248   CGEN_INSN_MACH, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI
 249  , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAX
 250  , CGEN_INSN_ALIAS, CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_NOT_IN_DELAY_SLOT
 251 } CGEN_INSN_ATTR;
 252
 253 /* Number of non-boolean elements in cgen_insn.  */
 254 #define CGEN_INSN_NBOOL_ATTRS ((int) CGEN_INSN_VIRTUAL)
 255
 256 /* Enum declaration for fr30 instruction types.  */
 257 typedef enum cgen_insn_type {
 258   FR30_INSN_INVALID, FR30_INSN_ADD, FR30_INSN_ADDI, FR30_INSN_ADD2
 259  , FR30_INSN_ADDC, FR30_INSN_ADDN, FR30_INSN_ADDNI, FR30_INSN_ADDN2
 260  , FR30_INSN_SUB, FR30_INSN_SUBC, FR30_INSN_SUBN, FR30_INSN_CMP
 261  , FR30_INSN_CMPI, FR30_INSN_CMP2, FR30_INSN_AND, FR30_INSN_OR
 262  , FR30_INSN_EOR, FR30_INSN_ANDM, FR30_INSN_ANDH, FR30_INSN_ANDB
 263  , FR30_INSN_ORM, FR30_INSN_ORH, FR30_INSN_ORB, FR30_INSN_EORM
 264  , FR30_INSN_EORH, FR30_INSN_EORB, FR30_INSN_BANDL, FR30_INSN_BORL
 265  , FR30_INSN_BEORL, FR30_INSN_BANDH, FR30_INSN_BORH, FR30_INSN_BEORH
 266  , FR30_INSN_BTSTL, FR30_INSN_BTSTH, FR30_INSN_MUL, FR30_INSN_MULU
 267  , FR30_INSN_MULH, FR30_INSN_MULUH, FR30_INSN_DIV0S, FR30_INSN_DIV0U
 268  , FR30_INSN_DIV1, FR30_INSN_DIV2, FR30_INSN_DIV3, FR30_INSN_DIV4S
 269  , FR30_INSN_LSL, FR30_INSN_LSLI, FR30_INSN_LSL2, FR30_INSN_LSR
 270  , FR30_INSN_LSRI, FR30_INSN_LSR2, FR30_INSN_ASR, FR30_INSN_ASRI
 271  , FR30_INSN_ASR2, FR30_INSN_LDI8, FR30_INSN_LDI20, FR30_INSN_LDI32
 272  , FR30_INSN_LD, FR30_INSN_LDUH, FR30_INSN_LDUB, FR30_INSN_LDR13
 273  , FR30_INSN_LDR13UH, FR30_INSN_LDR13UB, FR30_INSN_LDR14, FR30_INSN_LDR14UH
 274  , FR30_INSN_LDR14UB, FR30_INSN_LDR15, FR30_INSN_LDR15GR, FR30_INSN_LDR15DR
 275  , FR30_INSN_LDR15PS, FR30_INSN_ST, FR30_INSN_STH, FR30_INSN_STB
 276  , FR30_INSN_STR13, FR30_INSN_STR13H, FR30_INSN_STR13B, FR30_INSN_STR14
 277  , FR30_INSN_STR14H, FR30_INSN_STR14B, FR30_INSN_STR15, FR30_INSN_STR15GR
 278  , FR30_INSN_STR15DR, FR30_INSN_STR15PS, FR30_INSN_MOV, FR30_INSN_MOVDR
 279  , FR30_INSN_MOVPS, FR30_INSN_MOV2DR, FR30_INSN_MOV2PS, FR30_INSN_JMP
 280  , FR30_INSN_JMPD, FR30_INSN_CALLR, FR30_INSN_CALLRD, FR30_INSN_CALL
 281  , FR30_INSN_CALLD, FR30_INSN_RET, FR30_INSN_RET_D, FR30_INSN_INT
 282  , FR30_INSN_INTE, FR30_INSN_RETI, FR30_INSN_BRAD, FR30_INSN_BRA
 283  , FR30_INSN_BNOD, FR30_INSN_BNO, FR30_INSN_BEQD, FR30_INSN_BEQ
 284  , FR30_INSN_BNED, FR30_INSN_BNE, FR30_INSN_BCD, FR30_INSN_BC
 285  , FR30_INSN_BNCD, FR30_INSN_BNC, FR30_INSN_BND, FR30_INSN_BN
 286  , FR30_INSN_BPD, FR30_INSN_BP, FR30_INSN_BVD, FR30_INSN_BV
 287  , FR30_INSN_BNVD, FR30_INSN_BNV, FR30_INSN_BLTD, FR30_INSN_BLT
 288  , FR30_INSN_BGED, FR30_INSN_BGE, FR30_INSN_BLED, FR30_INSN_BLE
 289  , FR30_INSN_BGTD, FR30_INSN_BGT, FR30_INSN_BLSD, FR30_INSN_BLS
 290  , FR30_INSN_BHID, FR30_INSN_BHI, FR30_INSN_DMOVR13, FR30_INSN_DMOVR13H
 291  , FR30_INSN_DMOVR13B, FR30_INSN_DMOVR13PI, FR30_INSN_DMOVR13PIH, FR30_INSN_DMOVR13PIB
 292  , FR30_INSN_DMOVR15PI, FR30_INSN_DMOV2R13, FR30_INSN_DMOV2R13H, FR30_INSN_DMOV2R13B
 293  , FR30_INSN_DMOV2R13PI, FR30_INSN_DMOV2R13PIH, FR30_INSN_DMOV2R13PIB, FR30_INSN_DMOV2R15PD
 294  , FR30_INSN_LDRES, FR30_INSN_STRES, FR30_INSN_COPOP, FR30_INSN_COPLD
 295  , FR30_INSN_COPST, FR30_INSN_COPSV, FR30_INSN_NOP, FR30_INSN_ANDCCR
 296  , FR30_INSN_ORCCR, FR30_INSN_STILM, FR30_INSN_ADDSP, FR30_INSN_EXTSB
 297  , FR30_INSN_EXTUB, FR30_INSN_EXTSH, FR30_INSN_EXTUH, FR30_INSN_LDM0
 298  , FR30_INSN_LDM1, FR30_INSN_STM0, FR30_INSN_STM1, FR30_INSN_ENTER
 299  , FR30_INSN_LEAVE, FR30_INSN_XCHB, FR30_INSN_MAX
 300 } CGEN_INSN_TYPE;
 301
 302 /* Index of `invalid' insn place holder.  */
 303 #define CGEN_INSN_INVALID FR30_INSN_INVALID
 304 /* Total number of insns in table.  */
 305 #define MAX_INSNS ((int) FR30_INSN_MAX)
 306
 307 /* cgen.h uses things we just defined.  */
 308 #include "opcode/cgen.h"
 309
 310 /* This struct records data prior to insertion or after extraction.  */
 311 struct cgen_fields
 312 {
 313   long f_nil;
 314   long f_op1;
 315   long f_op2;
 316   long f_op3;
 317   long f_op4;
 318   long f_op5;
 319   long f_cc;
 320   long f_ccc;
 321   long f_Rj;
 322   long f_Ri;
 323   long f_Rs1;
 324   long f_Rs2;
 325   long f_Rjc;
 326   long f_Ric;
 327   long f_CRj;
 328   long f_CRi;
 329   long f_u4;
 330   long f_u4c;
 331   long f_i4;
 332   long f_m4;
 333   long f_u8;
 334   long f_i8;
 335   long f_i20_4;
 336   long f_i20_16;
 337   long f_i20;
 338   long f_i32;
 339   long f_udisp6;
 340   long f_disp8;
 341   long f_disp9;
 342   long f_disp10;
 343   long f_s10;
 344   long f_u10;
 345   long f_rel9;
 346   long f_dir8;
 347   long f_dir9;
 348   long f_dir10;
 349   long f_rel12;
 350   long f_reglist_hi_st;
 351   long f_reglist_low_st;
 352   long f_reglist_hi_ld;
 353   long f_reglist_low_ld;
 354   int length;
 355 };
 356
 357 /* Attributes.  */
 358 extern const CGEN_ATTR_TABLE fr30_cgen_hw_attr_table[];
 359 extern const CGEN_ATTR_TABLE fr30_cgen_operand_attr_table[];
 360 extern const CGEN_ATTR_TABLE fr30_cgen_insn_attr_table[];
 361
 362 /* Hardware decls.  */
 363
 364 extern CGEN_KEYWORD fr30_cgen_opval_h_gr;
 365 extern CGEN_KEYWORD fr30_cgen_opval_h_cr;
 366 extern CGEN_KEYWORD fr30_cgen_opval_h_dr;
 367 extern CGEN_KEYWORD fr30_cgen_opval_h_ps;
 368 extern CGEN_KEYWORD fr30_cgen_opval_h_r13;
 369 extern CGEN_KEYWORD fr30_cgen_opval_h_r14;
 370 extern CGEN_KEYWORD fr30_cgen_opval_h_r15;
 371
 372 #define CGEN_INIT_PARSE(od) \
 373 {\
 374 }
 375 #define CGEN_INIT_INSERT(od) \
 376 {\
 377 }
 378 #define CGEN_INIT_EXTRACT(od) \
 379 {\
 380 }
 381 #define CGEN_INIT_PRINT(od) \
 382 {\
 383 }
 384
 385 /* -- opc.h */
 386
 387 /* ??? This can be improved upon.  */
 388 #undef CGEN_DIS_HASH_SIZE
 389 #define CGEN_DIS_HASH_SIZE 16
 390 #undef CGEN_DIS_HASH
 391 #define CGEN_DIS_HASH(buffer, value) (((unsigned char *) (buffer))[0] >> 4)
 392
 393 /* -- */
 394
 395
 396 #endif /* FR30_OPC_H */