1 /* Instruction description for fr30.
3 THIS FILE IS MACHINE GENERATED WITH CGEN.
5 Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
7 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License along
20 with this program; if not, write to the Free Software Foundation, Inc.,
21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
28 #define CGEN_ARCH fr30
30 /* Given symbol S, return fr30_cgen_<s>. */
31 #define CGEN_SYM(s) CONCAT3 (fr30,_cgen_,s)
33 /* Selected cpu families. */
34 #define HAVE_CPU_FR30BF
36 #define CGEN_INSN_LSB0_P 0
37 #define CGEN_WORD_BITSIZE 32
38 #define CGEN_DEFAULT_INSN_BITSIZE 16
39 #define CGEN_BASE_INSN_BITSIZE 16
40 #define CGEN_MIN_INSN_BITSIZE 16
41 #define CGEN_MAX_INSN_BITSIZE 16
42 #define CGEN_DEFAULT_INSN_SIZE (CGEN_DEFAULT_INSN_BITSIZE / 8)
43 #define CGEN_BASE_INSN_SIZE (CGEN_BASE_INSN_BITSIZE / 8)
44 #define CGEN_MIN_INSN_SIZE (CGEN_MIN_INSN_BITSIZE / 8)
45 #define CGEN_MAX_INSN_SIZE (CGEN_MAX_INSN_BITSIZE / 8)
46 #define CGEN_INT_INSN_P 1
48 /* FIXME: Need to compute CGEN_MAX_SYNTAX_BYTES. */
50 /* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
51 e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands
52 we can't hash on everything up to the space. */
53 #define CGEN_MNEMONIC_OPERANDS
54 /* Maximum number of operands any insn or macro-insn has. */
55 #define CGEN_MAX_INSN_OPERANDS 16
59 /* Enum declaration for insn op1 enums. */
60 typedef enum insn_op1
{
61 OP1_0
, OP1_1
, OP1_2
, OP1_3
62 , OP1_4
, OP1_5
, OP1_6
, OP1_7
63 , OP1_8
, OP1_9
, OP1_A
, OP1_B
64 , OP1_C
, OP1_D
, OP1_E
, OP1_F
67 /* Enum declaration for insn op2 enums. */
68 typedef enum insn_op2
{
69 OP2_0
, OP2_1
, OP2_2
, OP2_3
70 , OP2_4
, OP2_5
, OP2_6
, OP2_7
71 , OP2_8
, OP2_9
, OP2_A
, OP2_B
72 , OP2_C
, OP2_D
, OP2_E
, OP2_F
75 /* Enum declaration for insn op3 enums. */
76 typedef enum insn_op3
{
77 OP3_0
, OP3_1
, OP3_2
, OP3_3
78 , OP3_4
, OP3_5
, OP3_6
, OP3_7
79 , OP3_8
, OP3_9
, OP3_A
, OP3_B
80 , OP3_C
, OP3_D
, OP3_E
, OP3_F
83 /* Enum declaration for insn op4 enums. */
84 typedef enum insn_op4
{
88 /* Enum declaration for insn op5 enums. */
89 typedef enum insn_op5
{
93 /* Enum declaration for insn cc enums. */
94 typedef enum insn_cc
{
95 CC_RA
, CC_NO
, CC_EQ
, CC_NE
96 , CC_C
, CC_NC
, CC_N
, CC_P
97 , CC_V
, CC_NV
, CC_LT
, CC_GE
98 , CC_LE
, CC_GT
, CC_LS
, CC_HI
101 /* Enum declaration for general registers. */
103 H_GR_AC
= 13, H_GR_FP
= 14, H_GR_SP
= 15, H_GR_R0
= 0
104 , H_GR_R1
= 1, H_GR_R2
= 2, H_GR_R3
= 3, H_GR_R4
= 4
105 , H_GR_R5
= 5, H_GR_R6
= 6, H_GR_R7
= 7, H_GR_R8
= 8
106 , H_GR_R9
= 9, H_GR_R10
= 10, H_GR_R11
= 11, H_GR_R12
= 12
107 , H_GR_R13
= 13, H_GR_R14
= 14, H_GR_R15
= 15
110 /* Enum declaration for dedicated registers. */
112 H_DR_TBR
, H_DR_RP
, H_DR_SSP
, H_DR_USP
116 /* Enum declaration for program status. */
121 /* Enum declaration for General Register 13 explicitely required. */
126 /* Enum declaration for General Register 14 explicitely required. */
131 /* Enum declaration for General Register 15 explicitely required. */
136 /* Enum declaration for fr30 operand types. */
137 typedef enum cgen_operand_type
{
138 FR30_OPERAND_PC
, FR30_OPERAND_RI
, FR30_OPERAND_RJ
, FR30_OPERAND_RS1
139 , FR30_OPERAND_RS2
, FR30_OPERAND_R13
, FR30_OPERAND_R14
, FR30_OPERAND_R15
140 , FR30_OPERAND_PS
, FR30_OPERAND_U4
, FR30_OPERAND_M4
, FR30_OPERAND_U8
141 , FR30_OPERAND_I8
, FR30_OPERAND_UDISP6
, FR30_OPERAND_DISP8
, FR30_OPERAND_DISP9
142 , FR30_OPERAND_DISP10
, FR30_OPERAND_S10
, FR30_OPERAND_U10
, FR30_OPERAND_DIR8
143 , FR30_OPERAND_DIR9
, FR30_OPERAND_DIR10
, FR30_OPERAND_LABEL9
, FR30_OPERAND_LABEL12
144 , FR30_OPERAND_CC
, FR30_OPERAND_NBIT
, FR30_OPERAND_VBIT
, FR30_OPERAND_ZBIT
145 , FR30_OPERAND_CBIT
, FR30_OPERAND_MAX
148 /* Non-boolean attributes. */
150 /* Enum declaration for machine type selection. */
151 typedef enum mach_attr
{
152 MACH_BASE
, MACH_FR30
, MACH_MAX
155 /* Number of architecture variants. */
156 #define MAX_MACHS ((int) MACH_MAX)
158 /* Number of operands types. */
159 #define MAX_OPERANDS ((int) FR30_OPERAND_MAX)
161 /* Maximum number of operands referenced by any insn. */
162 #define MAX_OPERAND_INSTANCES 8
164 /* Hardware, operand and instruction attribute indices. */
166 /* Enum declaration for cgen_hw attrs. */
167 typedef enum cgen_hw_attr
{
168 CGEN_HW_CACHE_ADDR
, CGEN_HW_PC
, CGEN_HW_PROFILE
171 /* Number of non-boolean elements in cgen_hw. */
172 #define CGEN_HW_NBOOL_ATTRS ((int) CGEN_HW_CACHE_ADDR)
174 /* Enum declaration for cgen_operand attrs. */
175 typedef enum cgen_operand_attr
{
176 CGEN_OPERAND_ABS_ADDR
, CGEN_OPERAND_HASH_PREFIX
, CGEN_OPERAND_NEGATIVE
, CGEN_OPERAND_PCREL_ADDR
177 , CGEN_OPERAND_RELAX
, CGEN_OPERAND_SEM_ONLY
, CGEN_OPERAND_SIGN_OPT
, CGEN_OPERAND_SIGNED
178 , CGEN_OPERAND_UNSIGNED
181 /* Number of non-boolean elements in cgen_operand. */
182 #define CGEN_OPERAND_NBOOL_ATTRS ((int) CGEN_OPERAND_ABS_ADDR)
184 /* Enum declaration for cgen_insn attrs. */
185 typedef enum cgen_insn_attr
{
186 CGEN_INSN_ALIAS
, CGEN_INSN_COND_CTI
, CGEN_INSN_NO_DIS
, CGEN_INSN_RELAX
187 , CGEN_INSN_RELAXABLE
, CGEN_INSN_SKIP_CTI
, CGEN_INSN_UNCOND_CTI
, CGEN_INSN_VIRTUAL
190 /* Number of non-boolean elements in cgen_insn. */
191 #define CGEN_INSN_NBOOL_ATTRS ((int) CGEN_INSN_ALIAS)
193 /* Enum declaration for fr30 instruction types. */
194 typedef enum cgen_insn_type
{
195 FR30_INSN_INVALID
, FR30_INSN_ADD
, FR30_INSN_ADDI
, FR30_INSN_ADD2
196 , FR30_INSN_ADDC
, FR30_INSN_ADDN
, FR30_INSN_ADDNI
, FR30_INSN_ADDN2
197 , FR30_INSN_SUB
, FR30_INSN_SUBC
, FR30_INSN_SUBN
, FR30_INSN_CMP
198 , FR30_INSN_CMPI
, FR30_INSN_CMP2
, FR30_INSN_AND
, FR30_INSN_OR
199 , FR30_INSN_EOR
, FR30_INSN_ANDM
, FR30_INSN_ANDH
, FR30_INSN_ANDB
200 , FR30_INSN_ORM
, FR30_INSN_ORH
, FR30_INSN_ORB
, FR30_INSN_EORM
201 , FR30_INSN_EORH
, FR30_INSN_EORB
, FR30_INSN_BANDL
, FR30_INSN_BORL
202 , FR30_INSN_BEORL
, FR30_INSN_BANDH
, FR30_INSN_BORH
, FR30_INSN_BEORH
203 , FR30_INSN_BTSTL
, FR30_INSN_BTSTH
, FR30_INSN_MUL
, FR30_INSN_MULU
204 , FR30_INSN_MULH
, FR30_INSN_MULUH
, FR30_INSN_DIV0S
, FR30_INSN_DIV0U
205 , FR30_INSN_DIV1
, FR30_INSN_DIV2
, FR30_INSN_DIV3
, FR30_INSN_DIV4S
206 , FR30_INSN_LSL
, FR30_INSN_LSLI
, FR30_INSN_LSL2
, FR30_INSN_LSR
207 , FR30_INSN_LSRI
, FR30_INSN_LSR2
, FR30_INSN_ASR
, FR30_INSN_ASRI
208 , FR30_INSN_ASR2
, FR30_INSN_LDI_8
, FR30_INSN_LD
, FR30_INSN_LDUH
209 , FR30_INSN_LDUB
, FR30_INSN_LDR13
, FR30_INSN_LDR13UH
, FR30_INSN_LDR13UB
210 , FR30_INSN_LDR14
, FR30_INSN_LDR14UH
, FR30_INSN_LDR14UB
, FR30_INSN_LDR15
211 , FR30_INSN_LDR15GR
, FR30_INSN_LDR15DR
, FR30_INSN_LDR15PS
, FR30_INSN_ST
212 , FR30_INSN_STH
, FR30_INSN_STB
, FR30_INSN_STR13
, FR30_INSN_STR13H
213 , FR30_INSN_STR13B
, FR30_INSN_STR14
, FR30_INSN_STR14H
, FR30_INSN_STR14B
214 , FR30_INSN_STR15
, FR30_INSN_STR15GR
, FR30_INSN_STR15DR
, FR30_INSN_STR15PS
215 , FR30_INSN_MOV
, FR30_INSN_MOVDR
, FR30_INSN_MOVPS
, FR30_INSN_MOV2DR
216 , FR30_INSN_MOV2PS
, FR30_INSN_JMP
, FR30_INSN_JMPD
, FR30_INSN_CALL
217 , FR30_INSN_CALLD
, FR30_INSN_CALLR
, FR30_INSN_CALLRD
, FR30_INSN_RET
218 , FR30_INSN_RETD
, FR30_INSN_INT
, FR30_INSN_INTE
, FR30_INSN_RETI
219 , FR30_INSN_BRA
, FR30_INSN_BNO
, FR30_INSN_BEQ
, FR30_INSN_BNE
220 , FR30_INSN_BC
, FR30_INSN_BNC
, FR30_INSN_BN
, FR30_INSN_BP
221 , FR30_INSN_BV
, FR30_INSN_BNV
, FR30_INSN_BLT
, FR30_INSN_BGE
222 , FR30_INSN_BLE
, FR30_INSN_BGT
, FR30_INSN_BLS
, FR30_INSN_BHI
223 , FR30_INSN_BRAD
, FR30_INSN_BNOD
, FR30_INSN_BEQD
, FR30_INSN_BNED
224 , FR30_INSN_BCD
, FR30_INSN_BNCD
, FR30_INSN_BND
, FR30_INSN_BPD
225 , FR30_INSN_BVD
, FR30_INSN_BNVD
, FR30_INSN_BLTD
, FR30_INSN_BGED
226 , FR30_INSN_BLED
, FR30_INSN_BGTD
, FR30_INSN_BLSD
, FR30_INSN_BHID
227 , FR30_INSN_DMOV2R13
, FR30_INSN_DMOV2R13H
, FR30_INSN_DMOV2R13B
, FR30_INSN_DMOVR13
228 , FR30_INSN_DMOVR13H
, FR30_INSN_DMOVR13B
, FR30_INSN_DMOV2R13PI
, FR30_INSN_DMOV2R13PIH
229 , FR30_INSN_DMOV2R13PIB
, FR30_INSN_DMOVR13PI
, FR30_INSN_DMOVR13PIH
, FR30_INSN_DMOVR13PIB
230 , FR30_INSN_DMOV2R15PD
, FR30_INSN_DMOVR15PI
, FR30_INSN_LDRES
, FR30_INSN_STRES
231 , FR30_INSN_NOP
, FR30_INSN_ANDCCR
, FR30_INSN_ORCCR
, FR30_INSN_STILM
232 , FR30_INSN_ADDSP
, FR30_INSN_EXTSB
, FR30_INSN_EXTUB
, FR30_INSN_EXTSH
233 , FR30_INSN_EXTUH
, FR30_INSN_ENTER
, FR30_INSN_LEAVE
, FR30_INSN_XCHB
237 /* Index of `invalid' insn place holder. */
238 #define CGEN_INSN_INVALID FR30_INSN_INVALID
239 /* Total number of insns in table. */
240 #define MAX_INSNS ((int) FR30_INSN_MAX)
242 /* cgen.h uses things we just defined. */
243 #include "opcode/cgen.h"
245 /* This struct records data prior to insertion or after extraction. */
279 extern const CGEN_ATTR_TABLE fr30_cgen_hw_attr_table
[];
280 extern const CGEN_ATTR_TABLE fr30_cgen_operand_attr_table
[];
281 extern const CGEN_ATTR_TABLE fr30_cgen_insn_attr_table
[];
283 /* Enum declaration for fr30 hardware types. */
284 typedef enum hw_type
{
285 HW_H_PC
, HW_H_MEMORY
, HW_H_SINT
, HW_H_UINT
286 , HW_H_ADDR
, HW_H_IADDR
, HW_H_GR
, HW_H_DR
287 , HW_H_PS
, HW_H_R13
, HW_H_R14
, HW_H_R15
288 , HW_H_NBIT
, HW_H_ZBIT
, HW_H_VBIT
, HW_H_CBIT
292 #define MAX_HW ((int) HW_MAX)
294 /* Hardware decls. */
296 extern CGEN_KEYWORD fr30_cgen_opval_h_gr
;
297 extern CGEN_KEYWORD fr30_cgen_opval_h_dr
;
298 extern CGEN_KEYWORD fr30_cgen_opval_h_ps
;
299 extern CGEN_KEYWORD fr30_cgen_opval_h_r13
;
300 extern CGEN_KEYWORD fr30_cgen_opval_h_r14
;
301 extern CGEN_KEYWORD fr30_cgen_opval_h_r15
;
303 #define CGEN_INIT_PARSE(od) \
306 #define CGEN_INIT_INSERT(od) \
309 #define CGEN_INIT_EXTRACT(od) \
312 #define CGEN_INIT_PRINT(od) \
318 #endif /* FR30_OPC_H */