* hppa-dis.c (print_insn_hppa): Remove unnecessary test in 'E'
[deliverable/binutils-gdb.git] / opcodes / hppa-dis.c
1 /* Disassembler for the PA-RISC. Somewhat derived from sparc-pinsn.c.
2 Copyright 1989, 1990, 1992, 1993 Free Software Foundation, Inc.
3
4 Contributed by the Center for Software Science at the
5 University of Utah (pa-gdb-bugs@cs.utah.edu).
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
20
21 #include <ansidecl.h>
22 #include "sysdep.h"
23 #include "dis-asm.h"
24 #include "libhppa.h"
25 #include "opcode/hppa.h"
26
27 /* Integer register names, indexed by the numbers which appear in the
28 opcodes. */
29 static const char *const reg_names[] =
30 {"flags", "r1", "rp", "r3", "r4", "r5", "r6", "r7", "r8", "r9",
31 "r10", "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19",
32 "r20", "r21", "r22", "r23", "r24", "r25", "r26", "dp", "ret0", "ret1",
33 "sp", "r31"};
34
35 /* Floating point register names, indexed by the numbers which appear in the
36 opcodes. */
37 static const char *const fp_reg_names[] =
38 {"fpsr", "fpe2", "fpe4", "fpe6",
39 "fr4", "fr5", "fr6", "fr7", "fr8",
40 "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
41 "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23",
42 "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31"};
43
44 typedef unsigned int CORE_ADDR;
45
46 /* Get at various relevent fields of an instruction word. */
47
48 #define MASK_5 0x1f
49 #define MASK_11 0x7ff
50 #define MASK_14 0x3fff
51 #define MASK_21 0x1fffff
52
53 /* This macro gets bit fields using HP's numbering (MSB = 0) */
54
55 #define GET_FIELD(X, FROM, TO) \
56 ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))
57
58 /* Some of these have been converted to 2-d arrays because they
59 consume less storage this way. If the maintenance becomes a
60 problem, convert them back to const 1-d pointer arrays. */
61 static const char control_reg[][6] = {
62 "rctr", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7",
63 "pidr1", "pidr2", "ccr", "sar", "pidr3", "pidr4",
64 "iva", "eiem", "itmr", "pcsq", "pcoq", "iir", "isr",
65 "ior", "ipsw", "eirr", "tr0", "tr1", "tr2", "tr3",
66 "tr4", "tr5", "tr6", "tr7"
67 };
68
69 static const char compare_cond_names[][5] = {
70 "", ",=", ",<", ",<=", ",<<", ",<<=", ",sv",
71 ",od", ",tr", ",<>", ",>=", ",>", ",>>=",
72 ",>>", ",nsv", ",ev"
73 };
74 static const char add_cond_names[][5] = {
75 "", ",=", ",<", ",<=", ",nuv", ",znv", ",sv",
76 ",od", ",tr", ",<>", ",>=", ",>", ",uv",
77 ",vnz", ",nsv", ",ev"
78 };
79 static const char *const logical_cond_names[] = {
80 "", ",=", ",<", ",<=", 0, 0, 0, ",od",
81 ",tr", ",<>", ",>=", ",>", 0, 0, 0, ",ev"};
82 static const char *const unit_cond_names[] = {
83 "", 0, ",sbz", ",shz", ",sdc", 0, ",sbc", ",shc",
84 ",tr", 0, ",nbz", ",nhz", ",ndc", 0, ",nbc", ",nhc"
85 };
86 static const char shift_cond_names[][4] = {
87 "", ",=", ",<", ",od", ",tr", ",<>", ",>=", ",ev"
88 };
89 static const char index_compl_names[][4] = {"", ",m", ",s", ",sm"};
90 static const char short_ldst_compl_names[][4] = {"", ",ma", "", ",mb"};
91 static const char *const short_bytes_compl_names[] = {
92 "", ",b,m", ",e", ",e,m"
93 };
94 static const char *const float_format_names[] = {",sgl", ",dbl", "", ",quad"};
95 static const char float_comp_names[][8] =
96 {
97 ",false?", ",false", ",?", ",!<=>", ",=", ",=t", ",?=", ",!<>",
98 ",!?>=", ",<", ",?<", ",!>=", ",!?>", ",<=", ",?<=", ",!>",
99 ",!?<=", ",>", ",?>", ",!<=", ",!?<", ",>=", ",?>=", ",!<",
100 ",!?=", ",<>", ",!=", ",!=t", ",!?", ",<=>", ",true?", ",true"
101 };
102
103 /* For a bunch of different instructions form an index into a
104 completer name table. */
105 #define GET_COMPL(insn) (GET_FIELD (insn, 26, 26) | \
106 GET_FIELD (insn, 18, 18) << 1)
107
108 #define GET_COND(insn) (GET_FIELD ((insn), 16, 18) + \
109 (GET_FIELD ((insn), 19, 19) ? 8 : 0))
110
111 /* Utility function to print registers. Put these first, so gcc's function
112 inlining can do its stuff. */
113
114 #define fputs_filtered(STR,F) (*info->fprintf_func) (info->stream, "%s", STR)
115
116 static void
117 fput_reg (reg, info)
118 unsigned reg;
119 disassemble_info *info;
120 {
121 (*info->fprintf_func) (info->stream, reg ? reg_names[reg] : "r0");
122 }
123
124 static void
125 fput_fp_reg (reg, info)
126 unsigned reg;
127 disassemble_info *info;
128 {
129 (*info->fprintf_func) (info->stream, reg ? fp_reg_names[reg] : "fr0");
130 }
131
132 static void
133 fput_fp_reg_r (reg, info)
134 unsigned reg;
135 disassemble_info *info;
136 {
137 /* Special case floating point exception registers. */
138 if (reg < 4)
139 (*info->fprintf_func) (info->stream, "fpe%d", reg * 2 + 1);
140 else
141 (*info->fprintf_func) (info->stream, "%sR", reg ? fp_reg_names[reg]
142 : "fr0");
143 }
144
145 static void
146 fput_creg (reg, info)
147 unsigned reg;
148 disassemble_info *info;
149 {
150 (*info->fprintf_func) (info->stream, control_reg[reg]);
151 }
152
153 /* print constants with sign */
154
155 static void
156 fput_const (num, info)
157 unsigned num;
158 disassemble_info *info;
159 {
160 if ((int)num < 0)
161 (*info->fprintf_func) (info->stream, "-%x", -(int)num);
162 else
163 (*info->fprintf_func) (info->stream, "%x", num);
164 }
165
166 /* Routines to extract various sized constants out of hppa
167 instructions. */
168
169 /* extract a 3-bit space register number from a be, ble, mtsp or mfsp */
170 static int
171 extract_3 (word)
172 unsigned word;
173 {
174 return GET_FIELD (word, 18, 18) << 2 | GET_FIELD (word, 16, 17);
175 }
176
177 static int
178 extract_5_load (word)
179 unsigned word;
180 {
181 return low_sign_extend (word >> 16 & MASK_5, 5);
182 }
183
184 /* extract the immediate field from a st{bhw}s instruction */
185 static int
186 extract_5_store (word)
187 unsigned word;
188 {
189 return low_sign_extend (word & MASK_5, 5);
190 }
191
192 /* extract the immediate field from a break instruction */
193 static unsigned
194 extract_5r_store (word)
195 unsigned word;
196 {
197 return (word & MASK_5);
198 }
199
200 /* extract the immediate field from a {sr}sm instruction */
201 static unsigned
202 extract_5R_store (word)
203 unsigned word;
204 {
205 return (word >> 16 & MASK_5);
206 }
207
208 /* extract the immediate field from a bb instruction */
209 static unsigned
210 extract_5Q_store (word)
211 unsigned word;
212 {
213 return (word >> 21 & MASK_5);
214 }
215
216 /* extract an 11 bit immediate field */
217 static int
218 extract_11 (word)
219 unsigned word;
220 {
221 return low_sign_extend (word & MASK_11, 11);
222 }
223
224 /* extract a 14 bit immediate field */
225 static int
226 extract_14 (word)
227 unsigned word;
228 {
229 return low_sign_extend (word & MASK_14, 14);
230 }
231
232 /* extract a 21 bit constant */
233
234 static int
235 extract_21 (word)
236 unsigned word;
237 {
238 int val;
239
240 word &= MASK_21;
241 word <<= 11;
242 val = GET_FIELD (word, 20, 20);
243 val <<= 11;
244 val |= GET_FIELD (word, 9, 19);
245 val <<= 2;
246 val |= GET_FIELD (word, 5, 6);
247 val <<= 5;
248 val |= GET_FIELD (word, 0, 4);
249 val <<= 2;
250 val |= GET_FIELD (word, 7, 8);
251 return sign_extend (val, 21) << 11;
252 }
253
254 /* extract a 12 bit constant from branch instructions */
255
256 static int
257 extract_12 (word)
258 unsigned word;
259 {
260 return sign_extend (GET_FIELD (word, 19, 28) |
261 GET_FIELD (word, 29, 29) << 10 |
262 (word & 0x1) << 11, 12) << 2;
263 }
264
265 /* extract a 17 bit constant from branch instructions, returning the
266 19 bit signed value. */
267
268 static int
269 extract_17 (word)
270 unsigned word;
271 {
272 return sign_extend (GET_FIELD (word, 19, 28) |
273 GET_FIELD (word, 29, 29) << 10 |
274 GET_FIELD (word, 11, 15) << 11 |
275 (word & 0x1) << 16, 17) << 2;
276 }
277
278 /* Print one instruction. */
279 int
280 print_insn_hppa (memaddr, info)
281 bfd_vma memaddr;
282 disassemble_info *info;
283 {
284 bfd_byte buffer[4];
285 unsigned int insn, i;
286
287 {
288 int status =
289 (*info->read_memory_func) (memaddr, buffer, sizeof (buffer), info);
290 if (status != 0)
291 {
292 (*info->memory_error_func) (status, memaddr, info);
293 return -1;
294 }
295 }
296
297 insn = bfd_getb32 (buffer);
298
299 for (i = 0; i < NUMOPCODES; ++i)
300 {
301 const struct pa_opcode *opcode = &pa_opcodes[i];
302 if ((insn & opcode->mask) == opcode->match)
303 {
304 register const char *s;
305
306 (*info->fprintf_func) (info->stream, "%s", opcode->name);
307
308 if (!strchr ("cfCY<?!@-+&U>~nHNZFIMadu|", opcode->args[0]))
309 (*info->fprintf_func) (info->stream, " ");
310 for (s = opcode->args; *s != '\0'; ++s)
311 {
312 switch (*s)
313 {
314 case 'x':
315 fput_reg (GET_FIELD (insn, 11, 15), info);
316 break;
317 case 'X':
318 if (GET_FIELD (insn, 25, 25))
319 fput_fp_reg_r (GET_FIELD (insn, 11, 15), info);
320 else
321 fput_fp_reg (GET_FIELD (insn, 11, 15), info);
322 break;
323 case 'b':
324 fput_reg (GET_FIELD (insn, 6, 10), info);
325 break;
326 case '^':
327 fput_creg (GET_FIELD (insn, 6, 10), info);
328 break;
329 case 'E':
330 fput_fp_reg (GET_FIELD (insn, 6, 10), info);
331 case 't':
332 fput_reg (GET_FIELD (insn, 27, 31), info);
333 break;
334 case 'v':
335 if (GET_FIELD (insn, 25, 25))
336 fput_fp_reg_r (GET_FIELD (insn, 27, 31), info);
337 else
338 fput_fp_reg (GET_FIELD (insn, 27, 31), info);
339 break;
340 case 'y':
341 fput_fp_reg (GET_FIELD (insn, 27, 31), info);
342 break;
343 case '4':
344 {
345 int reg = GET_FIELD (insn, 6, 10);
346
347 reg |= (GET_FIELD (insn, 26, 26) << 4);
348 fput_fp_reg (reg, info);
349 break;
350 }
351 case '6':
352 {
353 int reg = GET_FIELD (insn, 11, 15);
354
355 reg |= (GET_FIELD (insn, 26, 26) << 4);
356 fput_fp_reg (reg, info);
357 break;
358 }
359 case '7':
360 {
361 int reg = GET_FIELD (insn, 27, 31);
362
363 reg |= (GET_FIELD (insn, 26, 26) << 4);
364 fput_fp_reg (reg, info);
365 break;
366 }
367 case '8':
368 {
369 int reg = GET_FIELD (insn, 16, 20);
370
371 reg |= (GET_FIELD (insn, 26, 26) << 4);
372 fput_fp_reg (reg, info);
373 break;
374 }
375 case '9':
376 {
377 int reg = GET_FIELD (insn, 21, 25);
378
379 reg |= (GET_FIELD (insn, 26, 26) << 4);
380 fput_fp_reg (reg, info);
381 break;
382 }
383 case '5':
384 fput_const (extract_5_load (insn), info);
385 break;
386 case 's':
387 (*info->fprintf_func) (info->stream,
388 "sr%d", GET_FIELD (insn, 16, 17));
389 break;
390 case 'S':
391 (*info->fprintf_func) (info->stream, "sr%d", extract_3 (insn));
392 break;
393 case 'c':
394 (*info->fprintf_func) (info->stream, "%s ",
395 index_compl_names[GET_COMPL (insn)]);
396 break;
397 case 'C':
398 (*info->fprintf_func) (info->stream, "%s ",
399 short_ldst_compl_names[GET_COMPL (insn)]);
400 break;
401 case 'Y':
402 (*info->fprintf_func) (info->stream, "%s ",
403 short_bytes_compl_names[GET_COMPL (insn)]);
404 break;
405 /* these four conditions are for the set of instructions
406 which distinguish true/false conditions by opcode rather
407 than by the 'f' bit (sigh): comb, comib, addb, addib */
408 case '<':
409 fputs_filtered (compare_cond_names[GET_FIELD (insn, 16, 18)],
410 info);
411 break;
412 case '?':
413 fputs_filtered (compare_cond_names[GET_FIELD (insn, 16, 18)
414 + GET_FIELD (insn, 4, 4) * 8], info);
415 break;
416 case '@':
417 fputs_filtered (add_cond_names[GET_FIELD (insn, 16, 18)
418 + GET_FIELD (insn, 4, 4) * 8], info);
419 break;
420 case 'a':
421 (*info->fprintf_func) (info->stream, "%s ",
422 compare_cond_names[GET_COND (insn)]);
423 break;
424 case 'd':
425 (*info->fprintf_func) (info->stream, "%s ",
426 add_cond_names[GET_COND (insn)]);
427 break;
428 case '!':
429 (*info->fprintf_func) (info->stream, "%s",
430 add_cond_names[GET_FIELD (insn, 16, 18)]);
431 break;
432
433 case '&':
434 (*info->fprintf_func) (info->stream, "%s ",
435 logical_cond_names[GET_COND (insn)]);
436 break;
437 case 'U':
438 (*info->fprintf_func) (info->stream, "%s ",
439 unit_cond_names[GET_COND (insn)]);
440 break;
441 case '|':
442 case '>':
443 case '~':
444 (*info->fprintf_func)
445 (info->stream, "%s",
446 shift_cond_names[GET_FIELD (insn, 16, 18)]);
447
448 /* If the next character in args is 'n', it will handle
449 putting out the space. */
450 if (s[1] != 'n')
451 (*info->fprintf_func) (info->stream, " ");
452 break;
453 case 'V':
454 fput_const (extract_5_store (insn), info);
455 break;
456 case 'r':
457 fput_const (extract_5r_store (insn), info);
458 break;
459 case 'R':
460 fput_const (extract_5R_store (insn), info);
461 break;
462 case 'Q':
463 fput_const (extract_5Q_store (insn), info);
464 break;
465 case 'i':
466 fput_const (extract_11 (insn), info);
467 break;
468 case 'j':
469 fput_const (extract_14 (insn), info);
470 break;
471 case 'k':
472 fput_const (extract_21 (insn), info);
473 break;
474 case 'n':
475 if (insn & 0x2)
476 (*info->fprintf_func) (info->stream, ",n ");
477 else
478 (*info->fprintf_func) (info->stream, " ");
479 break;
480 case 'N':
481 if ((insn & 0x20) && s[1])
482 (*info->fprintf_func) (info->stream, ",n ");
483 else if (insn & 0x20)
484 (*info->fprintf_func) (info->stream, ",n");
485 else if (s[1])
486 (*info->fprintf_func) (info->stream, " ");
487 break;
488 case 'w':
489 (*info->print_address_func) (memaddr + 8 + extract_12 (insn),
490 info);
491 break;
492 case 'W':
493 /* 17 bit PC-relative branch. */
494 (*info->print_address_func) ((memaddr + 8
495 + extract_17 (insn)),
496 info);
497 break;
498 case 'z':
499 /* 17 bit displacement. This is an offset from a register
500 so it gets disasssembled as just a number, not any sort
501 of address. */
502 fput_const (extract_17 (insn), info);
503 break;
504 case 'p':
505 (*info->fprintf_func) (info->stream, "%d",
506 31 - GET_FIELD (insn, 22, 26));
507 break;
508 case 'P':
509 (*info->fprintf_func) (info->stream, "%d",
510 GET_FIELD (insn, 22, 26));
511 break;
512 case 'T':
513 (*info->fprintf_func) (info->stream, "%d",
514 32 - GET_FIELD (insn, 27, 31));
515 break;
516 case 'A':
517 fput_const (GET_FIELD (insn, 6, 18), info);
518 break;
519 case 'Z':
520 if (GET_FIELD (insn, 26, 26))
521 (*info->fprintf_func) (info->stream, ",m ");
522 else
523 (*info->fprintf_func) (info->stream, " ");
524 break;
525 case 'D':
526 fput_const (GET_FIELD (insn, 6, 31), info);
527 break;
528 case 'f':
529 (*info->fprintf_func) (info->stream, ",%d", GET_FIELD (insn, 23, 25));
530 break;
531 case 'O':
532 fput_const ((GET_FIELD (insn, 6,20) << 5 |
533 GET_FIELD (insn, 27, 31)), info);
534 break;
535 case 'o':
536 fput_const (GET_FIELD (insn, 6, 20), info);
537 break;
538 case '3':
539 {
540 int reg = GET_FIELD (insn, 21, 22);
541 reg |= GET_FIELD (insn, 16, 18) << 2;
542 if (GET_FIELD (insn, 23, 23) != 0)
543 fput_fp_reg_r (reg, info);
544 else
545 fput_fp_reg (reg, info);
546 break;
547 }
548
549 case '2':
550 fput_const ((GET_FIELD (insn, 6, 22) << 5 |
551 GET_FIELD (insn, 27, 31)), info);
552 break;
553 case '1':
554 fput_const ((GET_FIELD (insn, 11, 20) << 5 |
555 GET_FIELD (insn, 27, 31)), info);
556 break;
557 case '0':
558 fput_const ((GET_FIELD (insn, 16, 20) << 5 |
559 GET_FIELD (insn, 27, 31)), info);
560 break;
561 case 'u':
562 (*info->fprintf_func) (info->stream, ",%d", GET_FIELD (insn, 23, 25));
563 break;
564 case 'F':
565 /* if no destination completer and not before a completer
566 for fcmp, need a space here */
567 if (GET_FIELD (insn, 21, 22) == 1 || s[1] == 'M')
568 fputs_filtered (float_format_names[GET_FIELD (insn, 19, 20)],
569 info);
570 else
571 (*info->fprintf_func) (info->stream, "%s ",
572 float_format_names[GET_FIELD
573 (insn, 19, 20)]);
574 break;
575 case 'G':
576 (*info->fprintf_func) (info->stream, "%s ",
577 float_format_names[GET_FIELD (insn,
578 17, 18)]);
579 break;
580 case 'H':
581 if (GET_FIELD (insn, 26, 26) == 1)
582 (*info->fprintf_func) (info->stream, "%s ",
583 float_format_names[0]);
584 else
585 (*info->fprintf_func) (info->stream, "%s ",
586 float_format_names[1]);
587 break;
588 case 'I':
589 /* if no destination completer and not before a completer
590 for fcmp, need a space here */
591 if (GET_FIELD (insn, 21, 22) == 1 || s[1] == 'M')
592 fputs_filtered (float_format_names[GET_FIELD (insn, 20, 20)],
593 info);
594 else
595 (*info->fprintf_func) (info->stream, "%s ",
596 float_format_names[GET_FIELD
597 (insn, 20, 20)]);
598 break;
599 case 'J':
600 if (GET_FIELD (insn, 24, 24))
601 fput_fp_reg_r (GET_FIELD (insn, 6, 10), info);
602 else
603 fput_fp_reg (GET_FIELD (insn, 6, 10), info);
604
605 break;
606 case 'K':
607 if (GET_FIELD (insn, 19, 19))
608 fput_fp_reg_r (GET_FIELD (insn, 11, 15), info);
609 else
610 fput_fp_reg (GET_FIELD (insn, 11, 15), info);
611 break;
612 case 'M':
613 (*info->fprintf_func) (info->stream, "%s ",
614 float_comp_names[GET_FIELD
615 (insn, 27, 31)]);
616 break;
617 default:
618 (*info->fprintf_func) (info->stream, "%c", *s);
619 break;
620 }
621 }
622 return sizeof(insn);
623 }
624 }
625 (*info->fprintf_func) (info->stream, "#%8x", insn);
626 return sizeof(insn);
627 }
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