opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
   3    2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013
   4    Free Software Foundation, Inc.
   5
   6    This file is part of the GNU opcodes library.
   7
   8    This library is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3, or (at your option)
  11    any later version.
  12
  13    It is distributed in the hope that it will be useful, but WITHOUT
  14    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  16    License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; if not, write to the Free Software
  20    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  21    MA 02110-1301, USA.  */
  22
  23
  24 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  25    July 1988
  26     modified by John Hassey (hassey@dg-rtp.dg.com)
  27     x86-64 support added by Jan Hubicka (jh@suse.cz)
  28     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  29
  30 /* The main tables describing the instructions is essentially a copy
  31    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  32    Programmers Manual.  Usually, there is a capital letter, followed
  33    by a small letter.  The capital letter tell the addressing mode,
  34    and the small letter tells about the operand size.  Refer to
  35    the Intel manual for details.  */
  36
  37 #include "sysdep.h"
  38 #include "dis-asm.h"
  39 #include "opintl.h"
  40 #include "opcode/i386.h"
  41 #include "libiberty.h"
  42
  43 #include <setjmp.h>
  44
  45 static int print_insn (bfd_vma, disassemble_info *);
  46 static void dofloat (int);
  47 static void OP_ST (int, int);
  48 static void OP_STi (int, int);
  49 static int putop (const char *, int);
  50 static void oappend (const char *);
  51 static void append_seg (void);
  52 static void OP_indirE (int, int);
  53 static void print_operand_value (char *, int, bfd_vma);
  54 static void OP_E_register (int, int);
  55 static void OP_E_memory (int, int);
  56 static void print_displacement (char *, bfd_vma);
  57 static void OP_E (int, int);
  58 static void OP_G (int, int);
  59 static bfd_vma get64 (void);
  60 static bfd_signed_vma get32 (void);
  61 static bfd_signed_vma get32s (void);
  62 static int get16 (void);
  63 static void set_op (bfd_vma, int);
  64 static void OP_Skip_MODRM (int, int);
  65 static void OP_REG (int, int);
  66 static void OP_IMREG (int, int);
  67 static void OP_I (int, int);
  68 static void OP_I64 (int, int);
  69 static void OP_sI (int, int);
  70 static void OP_J (int, int);
  71 static void OP_SEG (int, int);
  72 static void OP_DIR (int, int);
  73 static void OP_OFF (int, int);
  74 static void OP_OFF64 (int, int);
  75 static void ptr_reg (int, int);
  76 static void OP_ESreg (int, int);
  77 static void OP_DSreg (int, int);
  78 static void OP_C (int, int);
  79 static void OP_D (int, int);
  80 static void OP_T (int, int);
  81 static void OP_R (int, int);
  82 static void OP_MMX (int, int);
  83 static void OP_XMM (int, int);
  84 static void OP_EM (int, int);
  85 static void OP_EX (int, int);
  86 static void OP_EMC (int,int);
  87 static void OP_MXC (int,int);
  88 static void OP_MS (int, int);
  89 static void OP_XS (int, int);
  90 static void OP_M (int, int);
  91 static void OP_VEX (int, int);
  92 static void OP_EX_Vex (int, int);
  93 static void OP_EX_VexW (int, int);
  94 static void OP_EX_VexImmW (int, int);
  95 static void OP_XMM_Vex (int, int);
  96 static void OP_XMM_VexW (int, int);
  97 static void OP_Rounding (int, int);
  98 static void OP_REG_VexI4 (int, int);
  99 static void PCLMUL_Fixup (int, int);
 100 static void VEXI4_Fixup (int, int);
 101 static void VZERO_Fixup (int, int);
 102 static void VCMP_Fixup (int, int);
 103 static void VPCMP_Fixup (int, int);
 104 static void OP_0f07 (int, int);
 105 static void OP_Monitor (int, int);
 106 static void OP_Mwait (int, int);
 107 static void NOP_Fixup1 (int, int);
 108 static void NOP_Fixup2 (int, int);
 109 static void OP_3DNowSuffix (int, int);
 110 static void CMP_Fixup (int, int);
 111 static void BadOp (void);
 112 static void REP_Fixup (int, int);
 113 static void BND_Fixup (int, int);
 114 static void HLE_Fixup1 (int, int);
 115 static void HLE_Fixup2 (int, int);
 116 static void HLE_Fixup3 (int, int);
 117 static void CMPXCHG8B_Fixup (int, int);
 118 static void XMM_Fixup (int, int);
 119 static void CRC32_Fixup (int, int);
 120 static void FXSAVE_Fixup (int, int);
 121 static void OP_LWPCB_E (int, int);
 122 static void OP_LWP_E (int, int);
 123 static void OP_Vex_2src_1 (int, int);
 124 static void OP_Vex_2src_2 (int, int);
 125
 126 static void MOVBE_Fixup (int, int);
 127
 128 static void OP_Mask (int, int);
 129
 130 struct dis_private {
 131   /* Points to first byte not fetched.  */
 132   bfd_byte *max_fetched;
 133   bfd_byte the_buffer[MAX_MNEM_SIZE];
 134   bfd_vma insn_start;
 135   int orig_sizeflag;
 136   jmp_buf bailout;
 137 };
 138
 139 enum address_mode
 140 {
 141   mode_16bit,
 142   mode_32bit,
 143   mode_64bit
 144 };
 145
 146 enum address_mode address_mode;
 147
 148 /* Flags for the prefixes for the current instruction.  See below.  */
 149 static int prefixes;
 150
 151 /* REX prefix the current instruction.  See below.  */
 152 static int rex;
 153 /* Bits of REX we've already used.  */
 154 static int rex_used;
 155 /* REX bits in original REX prefix ignored.  */
 156 static int rex_ignored;
 157 /* Mark parts used in the REX prefix.  When we are testing for
 158    empty prefix (for 8bit register REX extension), just mask it
 159    out.  Otherwise test for REX bit is excuse for existence of REX
 160    only in case value is nonzero.  */
 161 #define USED_REX(value)                                 \
 162   {                                                     \
 163     if (value)                                          \
 164       {                                                 \
 165         if ((rex & value))                              \
 166           rex_used |= (value) | REX_OPCODE;             \
 167       }                                                 \
 168     else                                                \
 169       rex_used |= REX_OPCODE;                           \
 170   }
 171
 172 /* Flags for prefixes which we somehow handled when printing the
 173    current instruction.  */
 174 static int used_prefixes;
 175
 176 /* Flags stored in PREFIXES.  */
 177 #define PREFIX_REPZ 1
 178 #define PREFIX_REPNZ 2
 179 #define PREFIX_LOCK 4
 180 #define PREFIX_CS 8
 181 #define PREFIX_SS 0x10
 182 #define PREFIX_DS 0x20
 183 #define PREFIX_ES 0x40
 184 #define PREFIX_FS 0x80
 185 #define PREFIX_GS 0x100
 186 #define PREFIX_DATA 0x200
 187 #define PREFIX_ADDR 0x400
 188 #define PREFIX_FWAIT 0x800
 189
 190 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 191    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 192    on error.  */
 193 #define FETCH_DATA(info, addr) \
 194   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 195    ? 1 : fetch_data ((info), (addr)))
 196
 197 static int
 198 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 199 {
 200   int status;
 201   struct dis_private *priv = (struct dis_private *) info->private_data;
 202   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 203
 204   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 205     status = (*info->read_memory_func) (start,
 206                                         priv->max_fetched,
 207                                         addr - priv->max_fetched,
 208                                         info);
 209   else
 210     status = -1;
 211   if (status != 0)
 212     {
 213       /* If we did manage to read at least one byte, then
 214          print_insn_i386 will do something sensible.  Otherwise, print
 215          an error.  We do that here because this is where we know
 216          STATUS.  */
 217       if (priv->max_fetched == priv->the_buffer)
 218         (*info->memory_error_func) (status, start, info);
 219       longjmp (priv->bailout, 1);
 220     }
 221   else
 222     priv->max_fetched = addr;
 223   return 1;
 224 }
 225
 226 #define XX { NULL, 0 }
 227 #define Bad_Opcode NULL, { { NULL, 0 } }
 228
 229 #define Eb { OP_E, b_mode }
 230 #define Ebnd { OP_E, bnd_mode }
 231 #define EbS { OP_E, b_swap_mode }
 232 #define Ev { OP_E, v_mode }
 233 #define Ev_bnd { OP_E, v_bnd_mode }
 234 #define EvS { OP_E, v_swap_mode }
 235 #define Ed { OP_E, d_mode }
 236 #define Edq { OP_E, dq_mode }
 237 #define Edqw { OP_E, dqw_mode }
 238 #define Edqb { OP_E, dqb_mode }
 239 #define Edqd { OP_E, dqd_mode }
 240 #define Eq { OP_E, q_mode }
 241 #define indirEv { OP_indirE, stack_v_mode }
 242 #define indirEp { OP_indirE, f_mode }
 243 #define stackEv { OP_E, stack_v_mode }
 244 #define Em { OP_E, m_mode }
 245 #define Ew { OP_E, w_mode }
 246 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 247 #define Ma { OP_M, a_mode }
 248 #define Mb { OP_M, b_mode }
 249 #define Md { OP_M, d_mode }
 250 #define Mo { OP_M, o_mode }
 251 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 252 #define Mq { OP_M, q_mode }
 253 #define Mx { OP_M, x_mode }
 254 #define Mxmm { OP_M, xmm_mode }
 255 #define Gb { OP_G, b_mode }
 256 #define Gbnd { OP_G, bnd_mode }
 257 #define Gv { OP_G, v_mode }
 258 #define Gd { OP_G, d_mode }
 259 #define Gdq { OP_G, dq_mode }
 260 #define Gm { OP_G, m_mode }
 261 #define Gw { OP_G, w_mode }
 262 #define Rd { OP_R, d_mode }
 263 #define Rdq { OP_R, dq_mode }
 264 #define Rm { OP_R, m_mode }
 265 #define Ib { OP_I, b_mode }
 266 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 267 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 268 #define Iv { OP_I, v_mode }
 269 #define sIv { OP_sI, v_mode }
 270 #define Iq { OP_I, q_mode }
 271 #define Iv64 { OP_I64, v_mode }
 272 #define Iw { OP_I, w_mode }
 273 #define I1 { OP_I, const_1_mode }
 274 #define Jb { OP_J, b_mode }
 275 #define Jv { OP_J, v_mode }
 276 #define Cm { OP_C, m_mode }
 277 #define Dm { OP_D, m_mode }
 278 #define Td { OP_T, d_mode }
 279 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 280
 281 #define RMeAX { OP_REG, eAX_reg }
 282 #define RMeBX { OP_REG, eBX_reg }
 283 #define RMeCX { OP_REG, eCX_reg }
 284 #define RMeDX { OP_REG, eDX_reg }
 285 #define RMeSP { OP_REG, eSP_reg }
 286 #define RMeBP { OP_REG, eBP_reg }
 287 #define RMeSI { OP_REG, eSI_reg }
 288 #define RMeDI { OP_REG, eDI_reg }
 289 #define RMrAX { OP_REG, rAX_reg }
 290 #define RMrBX { OP_REG, rBX_reg }
 291 #define RMrCX { OP_REG, rCX_reg }
 292 #define RMrDX { OP_REG, rDX_reg }
 293 #define RMrSP { OP_REG, rSP_reg }
 294 #define RMrBP { OP_REG, rBP_reg }
 295 #define RMrSI { OP_REG, rSI_reg }
 296 #define RMrDI { OP_REG, rDI_reg }
 297 #define RMAL { OP_REG, al_reg }
 298 #define RMCL { OP_REG, cl_reg }
 299 #define RMDL { OP_REG, dl_reg }
 300 #define RMBL { OP_REG, bl_reg }
 301 #define RMAH { OP_REG, ah_reg }
 302 #define RMCH { OP_REG, ch_reg }
 303 #define RMDH { OP_REG, dh_reg }
 304 #define RMBH { OP_REG, bh_reg }
 305 #define RMAX { OP_REG, ax_reg }
 306 #define RMDX { OP_REG, dx_reg }
 307
 308 #define eAX { OP_IMREG, eAX_reg }
 309 #define eBX { OP_IMREG, eBX_reg }
 310 #define eCX { OP_IMREG, eCX_reg }
 311 #define eDX { OP_IMREG, eDX_reg }
 312 #define eSP { OP_IMREG, eSP_reg }
 313 #define eBP { OP_IMREG, eBP_reg }
 314 #define eSI { OP_IMREG, eSI_reg }
 315 #define eDI { OP_IMREG, eDI_reg }
 316 #define AL { OP_IMREG, al_reg }
 317 #define CL { OP_IMREG, cl_reg }
 318 #define DL { OP_IMREG, dl_reg }
 319 #define BL { OP_IMREG, bl_reg }
 320 #define AH { OP_IMREG, ah_reg }
 321 #define CH { OP_IMREG, ch_reg }
 322 #define DH { OP_IMREG, dh_reg }
 323 #define BH { OP_IMREG, bh_reg }
 324 #define AX { OP_IMREG, ax_reg }
 325 #define DX { OP_IMREG, dx_reg }
 326 #define zAX { OP_IMREG, z_mode_ax_reg }
 327 #define indirDX { OP_IMREG, indir_dx_reg }
 328
 329 #define Sw { OP_SEG, w_mode }
 330 #define Sv { OP_SEG, v_mode }
 331 #define Ap { OP_DIR, 0 }
 332 #define Ob { OP_OFF64, b_mode }
 333 #define Ov { OP_OFF64, v_mode }
 334 #define Xb { OP_DSreg, eSI_reg }
 335 #define Xv { OP_DSreg, eSI_reg }
 336 #define Xz { OP_DSreg, eSI_reg }
 337 #define Yb { OP_ESreg, eDI_reg }
 338 #define Yv { OP_ESreg, eDI_reg }
 339 #define DSBX { OP_DSreg, eBX_reg }
 340
 341 #define es { OP_REG, es_reg }
 342 #define ss { OP_REG, ss_reg }
 343 #define cs { OP_REG, cs_reg }
 344 #define ds { OP_REG, ds_reg }
 345 #define fs { OP_REG, fs_reg }
 346 #define gs { OP_REG, gs_reg }
 347
 348 #define MX { OP_MMX, 0 }
 349 #define XM { OP_XMM, 0 }
 350 #define XMScalar { OP_XMM, scalar_mode }
 351 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 352 #define XMM { OP_XMM, xmm_mode }
 353 #define XMxmmq { OP_XMM, xmmq_mode }
 354 #define EM { OP_EM, v_mode }
 355 #define EMS { OP_EM, v_swap_mode }
 356 #define EMd { OP_EM, d_mode }
 357 #define EMx { OP_EM, x_mode }
 358 #define EXw { OP_EX, w_mode }
 359 #define EXd { OP_EX, d_mode }
 360 #define EXdScalar { OP_EX, d_scalar_mode }
 361 #define EXdS { OP_EX, d_swap_mode }
 362 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
 363 #define EXq { OP_EX, q_mode }
 364 #define EXqScalar { OP_EX, q_scalar_mode }
 365 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
 366 #define EXqS { OP_EX, q_swap_mode }
 367 #define EXx { OP_EX, x_mode }
 368 #define EXxS { OP_EX, x_swap_mode }
 369 #define EXxmm { OP_EX, xmm_mode }
 370 #define EXymm { OP_EX, ymm_mode }
 371 #define EXxmmq { OP_EX, xmmq_mode }
 372 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 373 #define EXxmm_mb { OP_EX, xmm_mb_mode }
 374 #define EXxmm_mw { OP_EX, xmm_mw_mode }
 375 #define EXxmm_md { OP_EX, xmm_md_mode }
 376 #define EXxmm_mq { OP_EX, xmm_mq_mode }
 377 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
 378 #define EXxmmdw { OP_EX, xmmdw_mode }
 379 #define EXxmmqd { OP_EX, xmmqd_mode }
 380 #define EXymmq { OP_EX, ymmq_mode }
 381 #define EXVexWdq { OP_EX, vex_w_dq_mode }
 382 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 383 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 384 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 385 #define MS { OP_MS, v_mode }
 386 #define XS { OP_XS, v_mode }
 387 #define EMCq { OP_EMC, q_mode }
 388 #define MXC { OP_MXC, 0 }
 389 #define OPSUF { OP_3DNowSuffix, 0 }
 390 #define CMP { CMP_Fixup, 0 }
 391 #define XMM0 { XMM_Fixup, 0 }
 392 #define FXSAVE { FXSAVE_Fixup, 0 }
 393 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
 394 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
 395
 396 #define Vex { OP_VEX, vex_mode }
 397 #define VexScalar { OP_VEX, vex_scalar_mode }
 398 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 399 #define Vex128 { OP_VEX, vex128_mode }
 400 #define Vex256 { OP_VEX, vex256_mode }
 401 #define VexGdq { OP_VEX, dq_mode }
 402 #define VexI4 { VEXI4_Fixup, 0}
 403 #define EXdVex { OP_EX_Vex, d_mode }
 404 #define EXdVexS { OP_EX_Vex, d_swap_mode }
 405 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
 406 #define EXqVex { OP_EX_Vex, q_mode }
 407 #define EXqVexS { OP_EX_Vex, q_swap_mode }
 408 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
 409 #define EXVexW { OP_EX_VexW, x_mode }
 410 #define EXdVexW { OP_EX_VexW, d_mode }
 411 #define EXqVexW { OP_EX_VexW, q_mode }
 412 #define EXVexImmW { OP_EX_VexImmW, x_mode }
 413 #define XMVex { OP_XMM_Vex, 0 }
 414 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
 415 #define XMVexW { OP_XMM_VexW, 0 }
 416 #define XMVexI4 { OP_REG_VexI4, x_mode }
 417 #define PCLMUL { PCLMUL_Fixup, 0 }
 418 #define VZERO { VZERO_Fixup, 0 }
 419 #define VCMP { VCMP_Fixup, 0 }
 420 #define VPCMP { VPCMP_Fixup, 0 }
 421
 422 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 423 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 424
 425 #define XMask { OP_Mask, mask_mode }
 426 #define MaskG { OP_G, mask_mode }
 427 #define MaskE { OP_E, mask_mode }
 428 #define MaskR { OP_R, mask_mode }
 429 #define MaskVex { OP_VEX, mask_mode }
 430
 431 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 432 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 433
 434 /* Used handle "rep" prefix for string instructions.  */
 435 #define Xbr { REP_Fixup, eSI_reg }
 436 #define Xvr { REP_Fixup, eSI_reg }
 437 #define Ybr { REP_Fixup, eDI_reg }
 438 #define Yvr { REP_Fixup, eDI_reg }
 439 #define Yzr { REP_Fixup, eDI_reg }
 440 #define indirDXr { REP_Fixup, indir_dx_reg }
 441 #define ALr { REP_Fixup, al_reg }
 442 #define eAXr { REP_Fixup, eAX_reg }
 443
 444 /* Used handle HLE prefix for lockable instructions.  */
 445 #define Ebh1 { HLE_Fixup1, b_mode }
 446 #define Evh1 { HLE_Fixup1, v_mode }
 447 #define Ebh2 { HLE_Fixup2, b_mode }
 448 #define Evh2 { HLE_Fixup2, v_mode }
 449 #define Ebh3 { HLE_Fixup3, b_mode }
 450 #define Evh3 { HLE_Fixup3, v_mode }
 451
 452 #define BND { BND_Fixup, 0 }
 453
 454 #define cond_jump_flag { NULL, cond_jump_mode }
 455 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 456
 457 /* bits in sizeflag */
 458 #define SUFFIX_ALWAYS 4
 459 #define AFLAG 2
 460 #define DFLAG 1
 461
 462 enum
 463 {
 464   /* byte operand */
 465   b_mode = 1,
 466   /* byte operand with operand swapped */
 467   b_swap_mode,
 468   /* byte operand, sign extend like 'T' suffix */
 469   b_T_mode,
 470   /* operand size depends on prefixes */
 471   v_mode,
 472   /* operand size depends on prefixes with operand swapped */
 473   v_swap_mode,
 474   /* word operand */
 475   w_mode,
 476   /* double word operand  */
 477   d_mode,
 478   /* double word operand with operand swapped */
 479   d_swap_mode,
 480   /* quad word operand */
 481   q_mode,
 482   /* quad word operand with operand swapped */
 483   q_swap_mode,
 484   /* ten-byte operand */
 485   t_mode,
 486   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 487      broadcast enabled.  */
 488   x_mode,
 489   /* Similar to x_mode, but with different EVEX mem shifts.  */
 490   evex_x_gscat_mode,
 491   /* Similar to x_mode, but with disabled broadcast.  */
 492   evex_x_nobcst_mode,
 493   /* Similar to x_mode, but with operands swapped and disabled broadcast
 494      in EVEX.  */
 495   x_swap_mode,
 496   /* 16-byte XMM operand */
 497   xmm_mode,
 498   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 499      memory operand (depending on vector length).  Broadcast isn't
 500      allowed.  */
 501   xmmq_mode,
 502   /* Same as xmmq_mode, but broadcast is allowed.  */
 503   evex_half_bcst_xmmq_mode,
 504   /* XMM register or byte memory operand */
 505   xmm_mb_mode,
 506   /* XMM register or word memory operand */
 507   xmm_mw_mode,
 508   /* XMM register or double word memory operand */
 509   xmm_md_mode,
 510   /* XMM register or quad word memory operand */
 511   xmm_mq_mode,
 512   /* XMM register or double/quad word memory operand, depending on
 513      VEX.W.  */
 514   xmm_mdq_mode,
 515   /* 16-byte XMM, word, double word or quad word operand.  */
 516   xmmdw_mode,
 517   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 518   xmmqd_mode,
 519   /* 32-byte YMM operand */
 520   ymm_mode,
 521   /* quad word, ymmword or zmmword memory operand.  */
 522   ymmq_mode,
 523   /* 32-byte YMM or 16-byte word operand */
 524   ymmxmm_mode,
 525   /* d_mode in 32bit, q_mode in 64bit mode.  */
 526   m_mode,
 527   /* pair of v_mode operands */
 528   a_mode,
 529   cond_jump_mode,
 530   loop_jcxz_mode,
 531   v_bnd_mode,
 532   /* operand size depends on REX prefixes.  */
 533   dq_mode,
 534   /* registers like dq_mode, memory like w_mode.  */
 535   dqw_mode,
 536   bnd_mode,
 537   /* 4- or 6-byte pointer operand */
 538   f_mode,
 539   const_1_mode,
 540   /* v_mode for stack-related opcodes.  */
 541   stack_v_mode,
 542   /* non-quad operand size depends on prefixes */
 543   z_mode,
 544   /* 16-byte operand */
 545   o_mode,
 546   /* registers like dq_mode, memory like b_mode.  */
 547   dqb_mode,
 548   /* registers like dq_mode, memory like d_mode.  */
 549   dqd_mode,
 550   /* normal vex mode */
 551   vex_mode,
 552   /* 128bit vex mode */
 553   vex128_mode,
 554   /* 256bit vex mode */
 555   vex256_mode,
 556   /* operand size depends on the VEX.W bit.  */
 557   vex_w_dq_mode,
 558
 559   /* Similar to vex_w_dq_mode, with VSIB dword indices.  */
 560   vex_vsib_d_w_dq_mode,
 561   /* Similar to vex_w_dq_mode, with VSIB qword indices.  */
 562   vex_vsib_q_w_dq_mode,
 563
 564   /* scalar, ignore vector length.  */
 565   scalar_mode,
 566   /* like d_mode, ignore vector length.  */
 567   d_scalar_mode,
 568   /* like d_swap_mode, ignore vector length.  */
 569   d_scalar_swap_mode,
 570   /* like q_mode, ignore vector length.  */
 571   q_scalar_mode,
 572   /* like q_swap_mode, ignore vector length.  */
 573   q_scalar_swap_mode,
 574   /* like vex_mode, ignore vector length.  */
 575   vex_scalar_mode,
 576   /* like vex_w_dq_mode, ignore vector length.  */
 577   vex_scalar_w_dq_mode,
 578
 579   /* Static rounding.  */
 580   evex_rounding_mode,
 581   /* Supress all exceptions.  */
 582   evex_sae_mode,
 583
 584   /* Mask register operand.  */
 585   mask_mode,
 586
 587   es_reg,
 588   cs_reg,
 589   ss_reg,
 590   ds_reg,
 591   fs_reg,
 592   gs_reg,
 593
 594   eAX_reg,
 595   eCX_reg,
 596   eDX_reg,
 597   eBX_reg,
 598   eSP_reg,
 599   eBP_reg,
 600   eSI_reg,
 601   eDI_reg,
 602
 603   al_reg,
 604   cl_reg,
 605   dl_reg,
 606   bl_reg,
 607   ah_reg,
 608   ch_reg,
 609   dh_reg,
 610   bh_reg,
 611
 612   ax_reg,
 613   cx_reg,
 614   dx_reg,
 615   bx_reg,
 616   sp_reg,
 617   bp_reg,
 618   si_reg,
 619   di_reg,
 620
 621   rAX_reg,
 622   rCX_reg,
 623   rDX_reg,
 624   rBX_reg,
 625   rSP_reg,
 626   rBP_reg,
 627   rSI_reg,
 628   rDI_reg,
 629
 630   z_mode_ax_reg,
 631   indir_dx_reg
 632 };
 633
 634 enum
 635 {
 636   FLOATCODE = 1,
 637   USE_REG_TABLE,
 638   USE_MOD_TABLE,
 639   USE_RM_TABLE,
 640   USE_PREFIX_TABLE,
 641   USE_X86_64_TABLE,
 642   USE_3BYTE_TABLE,
 643   USE_XOP_8F_TABLE,
 644   USE_VEX_C4_TABLE,
 645   USE_VEX_C5_TABLE,
 646   USE_VEX_LEN_TABLE,
 647   USE_VEX_W_TABLE,
 648   USE_EVEX_TABLE
 649 };
 650
 651 #define FLOAT                   NULL, { { NULL, FLOATCODE } }
 652
 653 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }
 654 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 655 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 656 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 657 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 658 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 659 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 660 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 661 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 662 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 663 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 664 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 665 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 666
 667 enum
 668 {
 669   REG_80 = 0,
 670   REG_81,
 671   REG_82,
 672   REG_8F,
 673   REG_C0,
 674   REG_C1,
 675   REG_C6,
 676   REG_C7,
 677   REG_D0,
 678   REG_D1,
 679   REG_D2,
 680   REG_D3,
 681   REG_F6,
 682   REG_F7,
 683   REG_FE,
 684   REG_FF,
 685   REG_0F00,
 686   REG_0F01,
 687   REG_0F0D,
 688   REG_0F18,
 689   REG_0F71,
 690   REG_0F72,
 691   REG_0F73,
 692   REG_0FA6,
 693   REG_0FA7,
 694   REG_0FAE,
 695   REG_0FBA,
 696   REG_0FC7,
 697   REG_VEX_0F71,
 698   REG_VEX_0F72,
 699   REG_VEX_0F73,
 700   REG_VEX_0FAE,
 701   REG_VEX_0F38F3,
 702   REG_XOP_LWPCB,
 703   REG_XOP_LWP,
 704   REG_XOP_TBM_01,
 705   REG_XOP_TBM_02,
 706
 707   REG_EVEX_0F72,
 708   REG_EVEX_0F73,
 709   REG_EVEX_0F38C6,
 710   REG_EVEX_0F38C7
 711 };
 712
 713 enum
 714 {
 715   MOD_8D = 0,
 716   MOD_C6_REG_7,
 717   MOD_C7_REG_7,
 718   MOD_FF_REG_3,
 719   MOD_FF_REG_5,
 720   MOD_0F01_REG_0,
 721   MOD_0F01_REG_1,
 722   MOD_0F01_REG_2,
 723   MOD_0F01_REG_3,
 724   MOD_0F01_REG_7,
 725   MOD_0F12_PREFIX_0,
 726   MOD_0F13,
 727   MOD_0F16_PREFIX_0,
 728   MOD_0F17,
 729   MOD_0F18_REG_0,
 730   MOD_0F18_REG_1,
 731   MOD_0F18_REG_2,
 732   MOD_0F18_REG_3,
 733   MOD_0F18_REG_4,
 734   MOD_0F18_REG_5,
 735   MOD_0F18_REG_6,
 736   MOD_0F18_REG_7,
 737   MOD_0F1A_PREFIX_0,
 738   MOD_0F1B_PREFIX_0,
 739   MOD_0F1B_PREFIX_1,
 740   MOD_0F20,
 741   MOD_0F21,
 742   MOD_0F22,
 743   MOD_0F23,
 744   MOD_0F24,
 745   MOD_0F26,
 746   MOD_0F2B_PREFIX_0,
 747   MOD_0F2B_PREFIX_1,
 748   MOD_0F2B_PREFIX_2,
 749   MOD_0F2B_PREFIX_3,
 750   MOD_0F51,
 751   MOD_0F71_REG_2,
 752   MOD_0F71_REG_4,
 753   MOD_0F71_REG_6,
 754   MOD_0F72_REG_2,
 755   MOD_0F72_REG_4,
 756   MOD_0F72_REG_6,
 757   MOD_0F73_REG_2,
 758   MOD_0F73_REG_3,
 759   MOD_0F73_REG_6,
 760   MOD_0F73_REG_7,
 761   MOD_0FAE_REG_0,
 762   MOD_0FAE_REG_1,
 763   MOD_0FAE_REG_2,
 764   MOD_0FAE_REG_3,
 765   MOD_0FAE_REG_4,
 766   MOD_0FAE_REG_5,
 767   MOD_0FAE_REG_6,
 768   MOD_0FAE_REG_7,
 769   MOD_0FB2,
 770   MOD_0FB4,
 771   MOD_0FB5,
 772   MOD_0FC7_REG_3,
 773   MOD_0FC7_REG_4,
 774   MOD_0FC7_REG_5,
 775   MOD_0FC7_REG_6,
 776   MOD_0FC7_REG_7,
 777   MOD_0FD7,
 778   MOD_0FE7_PREFIX_2,
 779   MOD_0FF0_PREFIX_3,
 780   MOD_0F382A_PREFIX_2,
 781   MOD_62_32BIT,
 782   MOD_C4_32BIT,
 783   MOD_C5_32BIT,
 784   MOD_VEX_0F12_PREFIX_0,
 785   MOD_VEX_0F13,
 786   MOD_VEX_0F16_PREFIX_0,
 787   MOD_VEX_0F17,
 788   MOD_VEX_0F2B,
 789   MOD_VEX_0F50,
 790   MOD_VEX_0F71_REG_2,
 791   MOD_VEX_0F71_REG_4,
 792   MOD_VEX_0F71_REG_6,
 793   MOD_VEX_0F72_REG_2,
 794   MOD_VEX_0F72_REG_4,
 795   MOD_VEX_0F72_REG_6,
 796   MOD_VEX_0F73_REG_2,
 797   MOD_VEX_0F73_REG_3,
 798   MOD_VEX_0F73_REG_6,
 799   MOD_VEX_0F73_REG_7,
 800   MOD_VEX_0FAE_REG_2,
 801   MOD_VEX_0FAE_REG_3,
 802   MOD_VEX_0FD7_PREFIX_2,
 803   MOD_VEX_0FE7_PREFIX_2,
 804   MOD_VEX_0FF0_PREFIX_3,
 805   MOD_VEX_0F381A_PREFIX_2,
 806   MOD_VEX_0F382A_PREFIX_2,
 807   MOD_VEX_0F382C_PREFIX_2,
 808   MOD_VEX_0F382D_PREFIX_2,
 809   MOD_VEX_0F382E_PREFIX_2,
 810   MOD_VEX_0F382F_PREFIX_2,
 811   MOD_VEX_0F385A_PREFIX_2,
 812   MOD_VEX_0F388C_PREFIX_2,
 813   MOD_VEX_0F388E_PREFIX_2,
 814
 815   MOD_EVEX_0F10_PREFIX_1,
 816   MOD_EVEX_0F10_PREFIX_3,
 817   MOD_EVEX_0F11_PREFIX_1,
 818   MOD_EVEX_0F11_PREFIX_3,
 819   MOD_EVEX_0F12_PREFIX_0,
 820   MOD_EVEX_0F16_PREFIX_0,
 821   MOD_EVEX_0F38C6_REG_1,
 822   MOD_EVEX_0F38C6_REG_2,
 823   MOD_EVEX_0F38C6_REG_5,
 824   MOD_EVEX_0F38C6_REG_6,
 825   MOD_EVEX_0F38C7_REG_1,
 826   MOD_EVEX_0F38C7_REG_2,
 827   MOD_EVEX_0F38C7_REG_5,
 828   MOD_EVEX_0F38C7_REG_6
 829 };
 830
 831 enum
 832 {
 833   RM_C6_REG_7 = 0,
 834   RM_C7_REG_7,
 835   RM_0F01_REG_0,
 836   RM_0F01_REG_1,
 837   RM_0F01_REG_2,
 838   RM_0F01_REG_3,
 839   RM_0F01_REG_7,
 840   RM_0FAE_REG_5,
 841   RM_0FAE_REG_6,
 842   RM_0FAE_REG_7
 843 };
 844
 845 enum
 846 {
 847   PREFIX_90 = 0,
 848   PREFIX_0F10,
 849   PREFIX_0F11,
 850   PREFIX_0F12,
 851   PREFIX_0F16,
 852   PREFIX_0F1A,
 853   PREFIX_0F1B,
 854   PREFIX_0F2A,
 855   PREFIX_0F2B,
 856   PREFIX_0F2C,
 857   PREFIX_0F2D,
 858   PREFIX_0F2E,
 859   PREFIX_0F2F,
 860   PREFIX_0F51,
 861   PREFIX_0F52,
 862   PREFIX_0F53,
 863   PREFIX_0F58,
 864   PREFIX_0F59,
 865   PREFIX_0F5A,
 866   PREFIX_0F5B,
 867   PREFIX_0F5C,
 868   PREFIX_0F5D,
 869   PREFIX_0F5E,
 870   PREFIX_0F5F,
 871   PREFIX_0F60,
 872   PREFIX_0F61,
 873   PREFIX_0F62,
 874   PREFIX_0F6C,
 875   PREFIX_0F6D,
 876   PREFIX_0F6F,
 877   PREFIX_0F70,
 878   PREFIX_0F73_REG_3,
 879   PREFIX_0F73_REG_7,
 880   PREFIX_0F78,
 881   PREFIX_0F79,
 882   PREFIX_0F7C,
 883   PREFIX_0F7D,
 884   PREFIX_0F7E,
 885   PREFIX_0F7F,
 886   PREFIX_0FAE_REG_0,
 887   PREFIX_0FAE_REG_1,
 888   PREFIX_0FAE_REG_2,
 889   PREFIX_0FAE_REG_3,
 890   PREFIX_0FAE_REG_7,
 891   PREFIX_0FB8,
 892   PREFIX_0FBC,
 893   PREFIX_0FBD,
 894   PREFIX_0FC2,
 895   PREFIX_0FC3,
 896   PREFIX_0FC7_REG_6,
 897   PREFIX_0FD0,
 898   PREFIX_0FD6,
 899   PREFIX_0FE6,
 900   PREFIX_0FE7,
 901   PREFIX_0FF0,
 902   PREFIX_0FF7,
 903   PREFIX_0F3810,
 904   PREFIX_0F3814,
 905   PREFIX_0F3815,
 906   PREFIX_0F3817,
 907   PREFIX_0F3820,
 908   PREFIX_0F3821,
 909   PREFIX_0F3822,
 910   PREFIX_0F3823,
 911   PREFIX_0F3824,
 912   PREFIX_0F3825,
 913   PREFIX_0F3828,
 914   PREFIX_0F3829,
 915   PREFIX_0F382A,
 916   PREFIX_0F382B,
 917   PREFIX_0F3830,
 918   PREFIX_0F3831,
 919   PREFIX_0F3832,
 920   PREFIX_0F3833,
 921   PREFIX_0F3834,
 922   PREFIX_0F3835,
 923   PREFIX_0F3837,
 924   PREFIX_0F3838,
 925   PREFIX_0F3839,
 926   PREFIX_0F383A,
 927   PREFIX_0F383B,
 928   PREFIX_0F383C,
 929   PREFIX_0F383D,
 930   PREFIX_0F383E,
 931   PREFIX_0F383F,
 932   PREFIX_0F3840,
 933   PREFIX_0F3841,
 934   PREFIX_0F3880,
 935   PREFIX_0F3881,
 936   PREFIX_0F3882,
 937   PREFIX_0F38C8,
 938   PREFIX_0F38C9,
 939   PREFIX_0F38CA,
 940   PREFIX_0F38CB,
 941   PREFIX_0F38CC,
 942   PREFIX_0F38CD,
 943   PREFIX_0F38DB,
 944   PREFIX_0F38DC,
 945   PREFIX_0F38DD,
 946   PREFIX_0F38DE,
 947   PREFIX_0F38DF,
 948   PREFIX_0F38F0,
 949   PREFIX_0F38F1,
 950   PREFIX_0F38F6,
 951   PREFIX_0F3A08,
 952   PREFIX_0F3A09,
 953   PREFIX_0F3A0A,
 954   PREFIX_0F3A0B,
 955   PREFIX_0F3A0C,
 956   PREFIX_0F3A0D,
 957   PREFIX_0F3A0E,
 958   PREFIX_0F3A14,
 959   PREFIX_0F3A15,
 960   PREFIX_0F3A16,
 961   PREFIX_0F3A17,
 962   PREFIX_0F3A20,
 963   PREFIX_0F3A21,
 964   PREFIX_0F3A22,
 965   PREFIX_0F3A40,
 966   PREFIX_0F3A41,
 967   PREFIX_0F3A42,
 968   PREFIX_0F3A44,
 969   PREFIX_0F3A60,
 970   PREFIX_0F3A61,
 971   PREFIX_0F3A62,
 972   PREFIX_0F3A63,
 973   PREFIX_0F3ACC,
 974   PREFIX_0F3ADF,
 975   PREFIX_VEX_0F10,
 976   PREFIX_VEX_0F11,
 977   PREFIX_VEX_0F12,
 978   PREFIX_VEX_0F16,
 979   PREFIX_VEX_0F2A,
 980   PREFIX_VEX_0F2C,
 981   PREFIX_VEX_0F2D,
 982   PREFIX_VEX_0F2E,
 983   PREFIX_VEX_0F2F,
 984   PREFIX_VEX_0F41,
 985   PREFIX_VEX_0F42,
 986   PREFIX_VEX_0F44,
 987   PREFIX_VEX_0F45,
 988   PREFIX_VEX_0F46,
 989   PREFIX_VEX_0F47,
 990   PREFIX_VEX_0F4B,
 991   PREFIX_VEX_0F51,
 992   PREFIX_VEX_0F52,
 993   PREFIX_VEX_0F53,
 994   PREFIX_VEX_0F58,
 995   PREFIX_VEX_0F59,
 996   PREFIX_VEX_0F5A,
 997   PREFIX_VEX_0F5B,
 998   PREFIX_VEX_0F5C,
 999   PREFIX_VEX_0F5D,
1000   PREFIX_VEX_0F5E,
1001   PREFIX_VEX_0F5F,
1002   PREFIX_VEX_0F60,
1003   PREFIX_VEX_0F61,
1004   PREFIX_VEX_0F62,
1005   PREFIX_VEX_0F63,
1006   PREFIX_VEX_0F64,
1007   PREFIX_VEX_0F65,
1008   PREFIX_VEX_0F66,
1009   PREFIX_VEX_0F67,
1010   PREFIX_VEX_0F68,
1011   PREFIX_VEX_0F69,
1012   PREFIX_VEX_0F6A,
1013   PREFIX_VEX_0F6B,
1014   PREFIX_VEX_0F6C,
1015   PREFIX_VEX_0F6D,
1016   PREFIX_VEX_0F6E,
1017   PREFIX_VEX_0F6F,
1018   PREFIX_VEX_0F70,
1019   PREFIX_VEX_0F71_REG_2,
1020   PREFIX_VEX_0F71_REG_4,
1021   PREFIX_VEX_0F71_REG_6,
1022   PREFIX_VEX_0F72_REG_2,
1023   PREFIX_VEX_0F72_REG_4,
1024   PREFIX_VEX_0F72_REG_6,
1025   PREFIX_VEX_0F73_REG_2,
1026   PREFIX_VEX_0F73_REG_3,
1027   PREFIX_VEX_0F73_REG_6,
1028   PREFIX_VEX_0F73_REG_7,
1029   PREFIX_VEX_0F74,
1030   PREFIX_VEX_0F75,
1031   PREFIX_VEX_0F76,
1032   PREFIX_VEX_0F77,
1033   PREFIX_VEX_0F7C,
1034   PREFIX_VEX_0F7D,
1035   PREFIX_VEX_0F7E,
1036   PREFIX_VEX_0F7F,
1037   PREFIX_VEX_0F90,
1038   PREFIX_VEX_0F91,
1039   PREFIX_VEX_0F92,
1040   PREFIX_VEX_0F93,
1041   PREFIX_VEX_0F98,
1042   PREFIX_VEX_0FC2,
1043   PREFIX_VEX_0FC4,
1044   PREFIX_VEX_0FC5,
1045   PREFIX_VEX_0FD0,
1046   PREFIX_VEX_0FD1,
1047   PREFIX_VEX_0FD2,
1048   PREFIX_VEX_0FD3,
1049   PREFIX_VEX_0FD4,
1050   PREFIX_VEX_0FD5,
1051   PREFIX_VEX_0FD6,
1052   PREFIX_VEX_0FD7,
1053   PREFIX_VEX_0FD8,
1054   PREFIX_VEX_0FD9,
1055   PREFIX_VEX_0FDA,
1056   PREFIX_VEX_0FDB,
1057   PREFIX_VEX_0FDC,
1058   PREFIX_VEX_0FDD,
1059   PREFIX_VEX_0FDE,
1060   PREFIX_VEX_0FDF,
1061   PREFIX_VEX_0FE0,
1062   PREFIX_VEX_0FE1,
1063   PREFIX_VEX_0FE2,
1064   PREFIX_VEX_0FE3,
1065   PREFIX_VEX_0FE4,
1066   PREFIX_VEX_0FE5,
1067   PREFIX_VEX_0FE6,
1068   PREFIX_VEX_0FE7,
1069   PREFIX_VEX_0FE8,
1070   PREFIX_VEX_0FE9,
1071   PREFIX_VEX_0FEA,
1072   PREFIX_VEX_0FEB,
1073   PREFIX_VEX_0FEC,
1074   PREFIX_VEX_0FED,
1075   PREFIX_VEX_0FEE,
1076   PREFIX_VEX_0FEF,
1077   PREFIX_VEX_0FF0,
1078   PREFIX_VEX_0FF1,
1079   PREFIX_VEX_0FF2,
1080   PREFIX_VEX_0FF3,
1081   PREFIX_VEX_0FF4,
1082   PREFIX_VEX_0FF5,
1083   PREFIX_VEX_0FF6,
1084   PREFIX_VEX_0FF7,
1085   PREFIX_VEX_0FF8,
1086   PREFIX_VEX_0FF9,
1087   PREFIX_VEX_0FFA,
1088   PREFIX_VEX_0FFB,
1089   PREFIX_VEX_0FFC,
1090   PREFIX_VEX_0FFD,
1091   PREFIX_VEX_0FFE,
1092   PREFIX_VEX_0F3800,
1093   PREFIX_VEX_0F3801,
1094   PREFIX_VEX_0F3802,
1095   PREFIX_VEX_0F3803,
1096   PREFIX_VEX_0F3804,
1097   PREFIX_VEX_0F3805,
1098   PREFIX_VEX_0F3806,
1099   PREFIX_VEX_0F3807,
1100   PREFIX_VEX_0F3808,
1101   PREFIX_VEX_0F3809,
1102   PREFIX_VEX_0F380A,
1103   PREFIX_VEX_0F380B,
1104   PREFIX_VEX_0F380C,
1105   PREFIX_VEX_0F380D,
1106   PREFIX_VEX_0F380E,
1107   PREFIX_VEX_0F380F,
1108   PREFIX_VEX_0F3813,
1109   PREFIX_VEX_0F3816,
1110   PREFIX_VEX_0F3817,
1111   PREFIX_VEX_0F3818,
1112   PREFIX_VEX_0F3819,
1113   PREFIX_VEX_0F381A,
1114   PREFIX_VEX_0F381C,
1115   PREFIX_VEX_0F381D,
1116   PREFIX_VEX_0F381E,
1117   PREFIX_VEX_0F3820,
1118   PREFIX_VEX_0F3821,
1119   PREFIX_VEX_0F3822,
1120   PREFIX_VEX_0F3823,
1121   PREFIX_VEX_0F3824,
1122   PREFIX_VEX_0F3825,
1123   PREFIX_VEX_0F3828,
1124   PREFIX_VEX_0F3829,
1125   PREFIX_VEX_0F382A,
1126   PREFIX_VEX_0F382B,
1127   PREFIX_VEX_0F382C,
1128   PREFIX_VEX_0F382D,
1129   PREFIX_VEX_0F382E,
1130   PREFIX_VEX_0F382F,
1131   PREFIX_VEX_0F3830,
1132   PREFIX_VEX_0F3831,
1133   PREFIX_VEX_0F3832,
1134   PREFIX_VEX_0F3833,
1135   PREFIX_VEX_0F3834,
1136   PREFIX_VEX_0F3835,
1137   PREFIX_VEX_0F3836,
1138   PREFIX_VEX_0F3837,
1139   PREFIX_VEX_0F3838,
1140   PREFIX_VEX_0F3839,
1141   PREFIX_VEX_0F383A,
1142   PREFIX_VEX_0F383B,
1143   PREFIX_VEX_0F383C,
1144   PREFIX_VEX_0F383D,
1145   PREFIX_VEX_0F383E,
1146   PREFIX_VEX_0F383F,
1147   PREFIX_VEX_0F3840,
1148   PREFIX_VEX_0F3841,
1149   PREFIX_VEX_0F3845,
1150   PREFIX_VEX_0F3846,
1151   PREFIX_VEX_0F3847,
1152   PREFIX_VEX_0F3858,
1153   PREFIX_VEX_0F3859,
1154   PREFIX_VEX_0F385A,
1155   PREFIX_VEX_0F3878,
1156   PREFIX_VEX_0F3879,
1157   PREFIX_VEX_0F388C,
1158   PREFIX_VEX_0F388E,
1159   PREFIX_VEX_0F3890,
1160   PREFIX_VEX_0F3891,
1161   PREFIX_VEX_0F3892,
1162   PREFIX_VEX_0F3893,
1163   PREFIX_VEX_0F3896,
1164   PREFIX_VEX_0F3897,
1165   PREFIX_VEX_0F3898,
1166   PREFIX_VEX_0F3899,
1167   PREFIX_VEX_0F389A,
1168   PREFIX_VEX_0F389B,
1169   PREFIX_VEX_0F389C,
1170   PREFIX_VEX_0F389D,
1171   PREFIX_VEX_0F389E,
1172   PREFIX_VEX_0F389F,
1173   PREFIX_VEX_0F38A6,
1174   PREFIX_VEX_0F38A7,
1175   PREFIX_VEX_0F38A8,
1176   PREFIX_VEX_0F38A9,
1177   PREFIX_VEX_0F38AA,
1178   PREFIX_VEX_0F38AB,
1179   PREFIX_VEX_0F38AC,
1180   PREFIX_VEX_0F38AD,
1181   PREFIX_VEX_0F38AE,
1182   PREFIX_VEX_0F38AF,
1183   PREFIX_VEX_0F38B6,
1184   PREFIX_VEX_0F38B7,
1185   PREFIX_VEX_0F38B8,
1186   PREFIX_VEX_0F38B9,
1187   PREFIX_VEX_0F38BA,
1188   PREFIX_VEX_0F38BB,
1189   PREFIX_VEX_0F38BC,
1190   PREFIX_VEX_0F38BD,
1191   PREFIX_VEX_0F38BE,
1192   PREFIX_VEX_0F38BF,
1193   PREFIX_VEX_0F38DB,
1194   PREFIX_VEX_0F38DC,
1195   PREFIX_VEX_0F38DD,
1196   PREFIX_VEX_0F38DE,
1197   PREFIX_VEX_0F38DF,
1198   PREFIX_VEX_0F38F2,
1199   PREFIX_VEX_0F38F3_REG_1,
1200   PREFIX_VEX_0F38F3_REG_2,
1201   PREFIX_VEX_0F38F3_REG_3,
1202   PREFIX_VEX_0F38F5,
1203   PREFIX_VEX_0F38F6,
1204   PREFIX_VEX_0F38F7,
1205   PREFIX_VEX_0F3A00,
1206   PREFIX_VEX_0F3A01,
1207   PREFIX_VEX_0F3A02,
1208   PREFIX_VEX_0F3A04,
1209   PREFIX_VEX_0F3A05,
1210   PREFIX_VEX_0F3A06,
1211   PREFIX_VEX_0F3A08,
1212   PREFIX_VEX_0F3A09,
1213   PREFIX_VEX_0F3A0A,
1214   PREFIX_VEX_0F3A0B,
1215   PREFIX_VEX_0F3A0C,
1216   PREFIX_VEX_0F3A0D,
1217   PREFIX_VEX_0F3A0E,
1218   PREFIX_VEX_0F3A0F,
1219   PREFIX_VEX_0F3A14,
1220   PREFIX_VEX_0F3A15,
1221   PREFIX_VEX_0F3A16,
1222   PREFIX_VEX_0F3A17,
1223   PREFIX_VEX_0F3A18,
1224   PREFIX_VEX_0F3A19,
1225   PREFIX_VEX_0F3A1D,
1226   PREFIX_VEX_0F3A20,
1227   PREFIX_VEX_0F3A21,
1228   PREFIX_VEX_0F3A22,
1229   PREFIX_VEX_0F3A30,
1230   PREFIX_VEX_0F3A32,
1231   PREFIX_VEX_0F3A38,
1232   PREFIX_VEX_0F3A39,
1233   PREFIX_VEX_0F3A40,
1234   PREFIX_VEX_0F3A41,
1235   PREFIX_VEX_0F3A42,
1236   PREFIX_VEX_0F3A44,
1237   PREFIX_VEX_0F3A46,
1238   PREFIX_VEX_0F3A48,
1239   PREFIX_VEX_0F3A49,
1240   PREFIX_VEX_0F3A4A,
1241   PREFIX_VEX_0F3A4B,
1242   PREFIX_VEX_0F3A4C,
1243   PREFIX_VEX_0F3A5C,
1244   PREFIX_VEX_0F3A5D,
1245   PREFIX_VEX_0F3A5E,
1246   PREFIX_VEX_0F3A5F,
1247   PREFIX_VEX_0F3A60,
1248   PREFIX_VEX_0F3A61,
1249   PREFIX_VEX_0F3A62,
1250   PREFIX_VEX_0F3A63,
1251   PREFIX_VEX_0F3A68,
1252   PREFIX_VEX_0F3A69,
1253   PREFIX_VEX_0F3A6A,
1254   PREFIX_VEX_0F3A6B,
1255   PREFIX_VEX_0F3A6C,
1256   PREFIX_VEX_0F3A6D,
1257   PREFIX_VEX_0F3A6E,
1258   PREFIX_VEX_0F3A6F,
1259   PREFIX_VEX_0F3A78,
1260   PREFIX_VEX_0F3A79,
1261   PREFIX_VEX_0F3A7A,
1262   PREFIX_VEX_0F3A7B,
1263   PREFIX_VEX_0F3A7C,
1264   PREFIX_VEX_0F3A7D,
1265   PREFIX_VEX_0F3A7E,
1266   PREFIX_VEX_0F3A7F,
1267   PREFIX_VEX_0F3ADF,
1268   PREFIX_VEX_0F3AF0,
1269
1270   PREFIX_EVEX_0F10,
1271   PREFIX_EVEX_0F11,
1272   PREFIX_EVEX_0F12,
1273   PREFIX_EVEX_0F13,
1274   PREFIX_EVEX_0F14,
1275   PREFIX_EVEX_0F15,
1276   PREFIX_EVEX_0F16,
1277   PREFIX_EVEX_0F17,
1278   PREFIX_EVEX_0F28,
1279   PREFIX_EVEX_0F29,
1280   PREFIX_EVEX_0F2A,
1281   PREFIX_EVEX_0F2B,
1282   PREFIX_EVEX_0F2C,
1283   PREFIX_EVEX_0F2D,
1284   PREFIX_EVEX_0F2E,
1285   PREFIX_EVEX_0F2F,
1286   PREFIX_EVEX_0F51,
1287   PREFIX_EVEX_0F58,
1288   PREFIX_EVEX_0F59,
1289   PREFIX_EVEX_0F5A,
1290   PREFIX_EVEX_0F5B,
1291   PREFIX_EVEX_0F5C,
1292   PREFIX_EVEX_0F5D,
1293   PREFIX_EVEX_0F5E,
1294   PREFIX_EVEX_0F5F,
1295   PREFIX_EVEX_0F62,
1296   PREFIX_EVEX_0F66,
1297   PREFIX_EVEX_0F6A,
1298   PREFIX_EVEX_0F6C,
1299   PREFIX_EVEX_0F6D,
1300   PREFIX_EVEX_0F6E,
1301   PREFIX_EVEX_0F6F,
1302   PREFIX_EVEX_0F70,
1303   PREFIX_EVEX_0F72_REG_0,
1304   PREFIX_EVEX_0F72_REG_1,
1305   PREFIX_EVEX_0F72_REG_2,
1306   PREFIX_EVEX_0F72_REG_4,
1307   PREFIX_EVEX_0F72_REG_6,
1308   PREFIX_EVEX_0F73_REG_2,
1309   PREFIX_EVEX_0F73_REG_6,
1310   PREFIX_EVEX_0F76,
1311   PREFIX_EVEX_0F78,
1312   PREFIX_EVEX_0F79,
1313   PREFIX_EVEX_0F7A,
1314   PREFIX_EVEX_0F7B,
1315   PREFIX_EVEX_0F7E,
1316   PREFIX_EVEX_0F7F,
1317   PREFIX_EVEX_0FC2,
1318   PREFIX_EVEX_0FC6,
1319   PREFIX_EVEX_0FD2,
1320   PREFIX_EVEX_0FD3,
1321   PREFIX_EVEX_0FD4,
1322   PREFIX_EVEX_0FD6,
1323   PREFIX_EVEX_0FDB,
1324   PREFIX_EVEX_0FDF,
1325   PREFIX_EVEX_0FE2,
1326   PREFIX_EVEX_0FE6,
1327   PREFIX_EVEX_0FE7,
1328   PREFIX_EVEX_0FEB,
1329   PREFIX_EVEX_0FEF,
1330   PREFIX_EVEX_0FF2,
1331   PREFIX_EVEX_0FF3,
1332   PREFIX_EVEX_0FF4,
1333   PREFIX_EVEX_0FFA,
1334   PREFIX_EVEX_0FFB,
1335   PREFIX_EVEX_0FFE,
1336   PREFIX_EVEX_0F380C,
1337   PREFIX_EVEX_0F380D,
1338   PREFIX_EVEX_0F3811,
1339   PREFIX_EVEX_0F3812,
1340   PREFIX_EVEX_0F3813,
1341   PREFIX_EVEX_0F3814,
1342   PREFIX_EVEX_0F3815,
1343   PREFIX_EVEX_0F3816,
1344   PREFIX_EVEX_0F3818,
1345   PREFIX_EVEX_0F3819,
1346   PREFIX_EVEX_0F381A,
1347   PREFIX_EVEX_0F381B,
1348   PREFIX_EVEX_0F381E,
1349   PREFIX_EVEX_0F381F,
1350   PREFIX_EVEX_0F3821,
1351   PREFIX_EVEX_0F3822,
1352   PREFIX_EVEX_0F3823,
1353   PREFIX_EVEX_0F3824,
1354   PREFIX_EVEX_0F3825,
1355   PREFIX_EVEX_0F3827,
1356   PREFIX_EVEX_0F3828,
1357   PREFIX_EVEX_0F3829,
1358   PREFIX_EVEX_0F382A,
1359   PREFIX_EVEX_0F382C,
1360   PREFIX_EVEX_0F382D,
1361   PREFIX_EVEX_0F3831,
1362   PREFIX_EVEX_0F3832,
1363   PREFIX_EVEX_0F3833,
1364   PREFIX_EVEX_0F3834,
1365   PREFIX_EVEX_0F3835,
1366   PREFIX_EVEX_0F3836,
1367   PREFIX_EVEX_0F3837,
1368   PREFIX_EVEX_0F3839,
1369   PREFIX_EVEX_0F383A,
1370   PREFIX_EVEX_0F383B,
1371   PREFIX_EVEX_0F383D,
1372   PREFIX_EVEX_0F383F,
1373   PREFIX_EVEX_0F3840,
1374   PREFIX_EVEX_0F3842,
1375   PREFIX_EVEX_0F3843,
1376   PREFIX_EVEX_0F3844,
1377   PREFIX_EVEX_0F3845,
1378   PREFIX_EVEX_0F3846,
1379   PREFIX_EVEX_0F3847,
1380   PREFIX_EVEX_0F384C,
1381   PREFIX_EVEX_0F384D,
1382   PREFIX_EVEX_0F384E,
1383   PREFIX_EVEX_0F384F,
1384   PREFIX_EVEX_0F3858,
1385   PREFIX_EVEX_0F3859,
1386   PREFIX_EVEX_0F385A,
1387   PREFIX_EVEX_0F385B,
1388   PREFIX_EVEX_0F3864,
1389   PREFIX_EVEX_0F3865,
1390   PREFIX_EVEX_0F3876,
1391   PREFIX_EVEX_0F3877,
1392   PREFIX_EVEX_0F387C,
1393   PREFIX_EVEX_0F387E,
1394   PREFIX_EVEX_0F387F,
1395   PREFIX_EVEX_0F3888,
1396   PREFIX_EVEX_0F3889,
1397   PREFIX_EVEX_0F388A,
1398   PREFIX_EVEX_0F388B,
1399   PREFIX_EVEX_0F3890,
1400   PREFIX_EVEX_0F3891,
1401   PREFIX_EVEX_0F3892,
1402   PREFIX_EVEX_0F3893,
1403   PREFIX_EVEX_0F3896,
1404   PREFIX_EVEX_0F3897,
1405   PREFIX_EVEX_0F3898,
1406   PREFIX_EVEX_0F3899,
1407   PREFIX_EVEX_0F389A,
1408   PREFIX_EVEX_0F389B,
1409   PREFIX_EVEX_0F389C,
1410   PREFIX_EVEX_0F389D,
1411   PREFIX_EVEX_0F389E,
1412   PREFIX_EVEX_0F389F,
1413   PREFIX_EVEX_0F38A0,
1414   PREFIX_EVEX_0F38A1,
1415   PREFIX_EVEX_0F38A2,
1416   PREFIX_EVEX_0F38A3,
1417   PREFIX_EVEX_0F38A6,
1418   PREFIX_EVEX_0F38A7,
1419   PREFIX_EVEX_0F38A8,
1420   PREFIX_EVEX_0F38A9,
1421   PREFIX_EVEX_0F38AA,
1422   PREFIX_EVEX_0F38AB,
1423   PREFIX_EVEX_0F38AC,
1424   PREFIX_EVEX_0F38AD,
1425   PREFIX_EVEX_0F38AE,
1426   PREFIX_EVEX_0F38AF,
1427   PREFIX_EVEX_0F38B6,
1428   PREFIX_EVEX_0F38B7,
1429   PREFIX_EVEX_0F38B8,
1430   PREFIX_EVEX_0F38B9,
1431   PREFIX_EVEX_0F38BA,
1432   PREFIX_EVEX_0F38BB,
1433   PREFIX_EVEX_0F38BC,
1434   PREFIX_EVEX_0F38BD,
1435   PREFIX_EVEX_0F38BE,
1436   PREFIX_EVEX_0F38BF,
1437   PREFIX_EVEX_0F38C4,
1438   PREFIX_EVEX_0F38C6_REG_1,
1439   PREFIX_EVEX_0F38C6_REG_2,
1440   PREFIX_EVEX_0F38C6_REG_5,
1441   PREFIX_EVEX_0F38C6_REG_6,
1442   PREFIX_EVEX_0F38C7_REG_1,
1443   PREFIX_EVEX_0F38C7_REG_2,
1444   PREFIX_EVEX_0F38C7_REG_5,
1445   PREFIX_EVEX_0F38C7_REG_6,
1446   PREFIX_EVEX_0F38C8,
1447   PREFIX_EVEX_0F38CA,
1448   PREFIX_EVEX_0F38CB,
1449   PREFIX_EVEX_0F38CC,
1450   PREFIX_EVEX_0F38CD,
1451
1452   PREFIX_EVEX_0F3A00,
1453   PREFIX_EVEX_0F3A01,
1454   PREFIX_EVEX_0F3A03,
1455   PREFIX_EVEX_0F3A04,
1456   PREFIX_EVEX_0F3A05,
1457   PREFIX_EVEX_0F3A08,
1458   PREFIX_EVEX_0F3A09,
1459   PREFIX_EVEX_0F3A0A,
1460   PREFIX_EVEX_0F3A0B,
1461   PREFIX_EVEX_0F3A17,
1462   PREFIX_EVEX_0F3A18,
1463   PREFIX_EVEX_0F3A19,
1464   PREFIX_EVEX_0F3A1A,
1465   PREFIX_EVEX_0F3A1B,
1466   PREFIX_EVEX_0F3A1D,
1467   PREFIX_EVEX_0F3A1E,
1468   PREFIX_EVEX_0F3A1F,
1469   PREFIX_EVEX_0F3A21,
1470   PREFIX_EVEX_0F3A23,
1471   PREFIX_EVEX_0F3A25,
1472   PREFIX_EVEX_0F3A26,
1473   PREFIX_EVEX_0F3A27,
1474   PREFIX_EVEX_0F3A38,
1475   PREFIX_EVEX_0F3A39,
1476   PREFIX_EVEX_0F3A3A,
1477   PREFIX_EVEX_0F3A3B,
1478   PREFIX_EVEX_0F3A43,
1479   PREFIX_EVEX_0F3A54,
1480   PREFIX_EVEX_0F3A55,
1481 };
1482
1483 enum
1484 {
1485   X86_64_06 = 0,
1486   X86_64_07,
1487   X86_64_0D,
1488   X86_64_16,
1489   X86_64_17,
1490   X86_64_1E,
1491   X86_64_1F,
1492   X86_64_27,
1493   X86_64_2F,
1494   X86_64_37,
1495   X86_64_3F,
1496   X86_64_60,
1497   X86_64_61,
1498   X86_64_62,
1499   X86_64_63,
1500   X86_64_6D,
1501   X86_64_6F,
1502   X86_64_9A,
1503   X86_64_C4,
1504   X86_64_C5,
1505   X86_64_CE,
1506   X86_64_D4,
1507   X86_64_D5,
1508   X86_64_EA,
1509   X86_64_0F01_REG_0,
1510   X86_64_0F01_REG_1,
1511   X86_64_0F01_REG_2,
1512   X86_64_0F01_REG_3
1513 };
1514
1515 enum
1516 {
1517   THREE_BYTE_0F38 = 0,
1518   THREE_BYTE_0F3A,
1519   THREE_BYTE_0F7A
1520 };
1521
1522 enum
1523 {
1524   XOP_08 = 0,
1525   XOP_09,
1526   XOP_0A
1527 };
1528
1529 enum
1530 {
1531   VEX_0F = 0,
1532   VEX_0F38,
1533   VEX_0F3A
1534 };
1535
1536 enum
1537 {
1538   EVEX_0F = 0,
1539   EVEX_0F38,
1540   EVEX_0F3A
1541 };
1542
1543 enum
1544 {
1545   VEX_LEN_0F10_P_1 = 0,
1546   VEX_LEN_0F10_P_3,
1547   VEX_LEN_0F11_P_1,
1548   VEX_LEN_0F11_P_3,
1549   VEX_LEN_0F12_P_0_M_0,
1550   VEX_LEN_0F12_P_0_M_1,
1551   VEX_LEN_0F12_P_2,
1552   VEX_LEN_0F13_M_0,
1553   VEX_LEN_0F16_P_0_M_0,
1554   VEX_LEN_0F16_P_0_M_1,
1555   VEX_LEN_0F16_P_2,
1556   VEX_LEN_0F17_M_0,
1557   VEX_LEN_0F2A_P_1,
1558   VEX_LEN_0F2A_P_3,
1559   VEX_LEN_0F2C_P_1,
1560   VEX_LEN_0F2C_P_3,
1561   VEX_LEN_0F2D_P_1,
1562   VEX_LEN_0F2D_P_3,
1563   VEX_LEN_0F2E_P_0,
1564   VEX_LEN_0F2E_P_2,
1565   VEX_LEN_0F2F_P_0,
1566   VEX_LEN_0F2F_P_2,
1567   VEX_LEN_0F41_P_0,
1568   VEX_LEN_0F42_P_0,
1569   VEX_LEN_0F44_P_0,
1570   VEX_LEN_0F45_P_0,
1571   VEX_LEN_0F46_P_0,
1572   VEX_LEN_0F47_P_0,
1573   VEX_LEN_0F4B_P_2,
1574   VEX_LEN_0F51_P_1,
1575   VEX_LEN_0F51_P_3,
1576   VEX_LEN_0F52_P_1,
1577   VEX_LEN_0F53_P_1,
1578   VEX_LEN_0F58_P_1,
1579   VEX_LEN_0F58_P_3,
1580   VEX_LEN_0F59_P_1,
1581   VEX_LEN_0F59_P_3,
1582   VEX_LEN_0F5A_P_1,
1583   VEX_LEN_0F5A_P_3,
1584   VEX_LEN_0F5C_P_1,
1585   VEX_LEN_0F5C_P_3,
1586   VEX_LEN_0F5D_P_1,
1587   VEX_LEN_0F5D_P_3,
1588   VEX_LEN_0F5E_P_1,
1589   VEX_LEN_0F5E_P_3,
1590   VEX_LEN_0F5F_P_1,
1591   VEX_LEN_0F5F_P_3,
1592   VEX_LEN_0F6E_P_2,
1593   VEX_LEN_0F7E_P_1,
1594   VEX_LEN_0F7E_P_2,
1595   VEX_LEN_0F90_P_0,
1596   VEX_LEN_0F91_P_0,
1597   VEX_LEN_0F92_P_0,
1598   VEX_LEN_0F93_P_0,
1599   VEX_LEN_0F98_P_0,
1600   VEX_LEN_0FAE_R_2_M_0,
1601   VEX_LEN_0FAE_R_3_M_0,
1602   VEX_LEN_0FC2_P_1,
1603   VEX_LEN_0FC2_P_3,
1604   VEX_LEN_0FC4_P_2,
1605   VEX_LEN_0FC5_P_2,
1606   VEX_LEN_0FD6_P_2,
1607   VEX_LEN_0FF7_P_2,
1608   VEX_LEN_0F3816_P_2,
1609   VEX_LEN_0F3819_P_2,
1610   VEX_LEN_0F381A_P_2_M_0,
1611   VEX_LEN_0F3836_P_2,
1612   VEX_LEN_0F3841_P_2,
1613   VEX_LEN_0F385A_P_2_M_0,
1614   VEX_LEN_0F38DB_P_2,
1615   VEX_LEN_0F38DC_P_2,
1616   VEX_LEN_0F38DD_P_2,
1617   VEX_LEN_0F38DE_P_2,
1618   VEX_LEN_0F38DF_P_2,
1619   VEX_LEN_0F38F2_P_0,
1620   VEX_LEN_0F38F3_R_1_P_0,
1621   VEX_LEN_0F38F3_R_2_P_0,
1622   VEX_LEN_0F38F3_R_3_P_0,
1623   VEX_LEN_0F38F5_P_0,
1624   VEX_LEN_0F38F5_P_1,
1625   VEX_LEN_0F38F5_P_3,
1626   VEX_LEN_0F38F6_P_3,
1627   VEX_LEN_0F38F7_P_0,
1628   VEX_LEN_0F38F7_P_1,
1629   VEX_LEN_0F38F7_P_2,
1630   VEX_LEN_0F38F7_P_3,
1631   VEX_LEN_0F3A00_P_2,
1632   VEX_LEN_0F3A01_P_2,
1633   VEX_LEN_0F3A06_P_2,
1634   VEX_LEN_0F3A0A_P_2,
1635   VEX_LEN_0F3A0B_P_2,
1636   VEX_LEN_0F3A14_P_2,
1637   VEX_LEN_0F3A15_P_2,
1638   VEX_LEN_0F3A16_P_2,
1639   VEX_LEN_0F3A17_P_2,
1640   VEX_LEN_0F3A18_P_2,
1641   VEX_LEN_0F3A19_P_2,
1642   VEX_LEN_0F3A20_P_2,
1643   VEX_LEN_0F3A21_P_2,
1644   VEX_LEN_0F3A22_P_2,
1645   VEX_LEN_0F3A30_P_2,
1646   VEX_LEN_0F3A32_P_2,
1647   VEX_LEN_0F3A38_P_2,
1648   VEX_LEN_0F3A39_P_2,
1649   VEX_LEN_0F3A41_P_2,
1650   VEX_LEN_0F3A44_P_2,
1651   VEX_LEN_0F3A46_P_2,
1652   VEX_LEN_0F3A60_P_2,
1653   VEX_LEN_0F3A61_P_2,
1654   VEX_LEN_0F3A62_P_2,
1655   VEX_LEN_0F3A63_P_2,
1656   VEX_LEN_0F3A6A_P_2,
1657   VEX_LEN_0F3A6B_P_2,
1658   VEX_LEN_0F3A6E_P_2,
1659   VEX_LEN_0F3A6F_P_2,
1660   VEX_LEN_0F3A7A_P_2,
1661   VEX_LEN_0F3A7B_P_2,
1662   VEX_LEN_0F3A7E_P_2,
1663   VEX_LEN_0F3A7F_P_2,
1664   VEX_LEN_0F3ADF_P_2,
1665   VEX_LEN_0F3AF0_P_3,
1666   VEX_LEN_0FXOP_08_CC,
1667   VEX_LEN_0FXOP_08_CD,
1668   VEX_LEN_0FXOP_08_CE,
1669   VEX_LEN_0FXOP_08_CF,
1670   VEX_LEN_0FXOP_08_EC,
1671   VEX_LEN_0FXOP_08_ED,
1672   VEX_LEN_0FXOP_08_EE,
1673   VEX_LEN_0FXOP_08_EF,
1674   VEX_LEN_0FXOP_09_80,
1675   VEX_LEN_0FXOP_09_81
1676 };
1677
1678 enum
1679 {
1680   VEX_W_0F10_P_0 = 0,
1681   VEX_W_0F10_P_1,
1682   VEX_W_0F10_P_2,
1683   VEX_W_0F10_P_3,
1684   VEX_W_0F11_P_0,
1685   VEX_W_0F11_P_1,
1686   VEX_W_0F11_P_2,
1687   VEX_W_0F11_P_3,
1688   VEX_W_0F12_P_0_M_0,
1689   VEX_W_0F12_P_0_M_1,
1690   VEX_W_0F12_P_1,
1691   VEX_W_0F12_P_2,
1692   VEX_W_0F12_P_3,
1693   VEX_W_0F13_M_0,
1694   VEX_W_0F14,
1695   VEX_W_0F15,
1696   VEX_W_0F16_P_0_M_0,
1697   VEX_W_0F16_P_0_M_1,
1698   VEX_W_0F16_P_1,
1699   VEX_W_0F16_P_2,
1700   VEX_W_0F17_M_0,
1701   VEX_W_0F28,
1702   VEX_W_0F29,
1703   VEX_W_0F2B_M_0,
1704   VEX_W_0F2E_P_0,
1705   VEX_W_0F2E_P_2,
1706   VEX_W_0F2F_P_0,
1707   VEX_W_0F2F_P_2,
1708   VEX_W_0F41_P_0_LEN_1,
1709   VEX_W_0F42_P_0_LEN_1,
1710   VEX_W_0F44_P_0_LEN_0,
1711   VEX_W_0F45_P_0_LEN_1,
1712   VEX_W_0F46_P_0_LEN_1,
1713   VEX_W_0F47_P_0_LEN_1,
1714   VEX_W_0F4B_P_2_LEN_1,
1715   VEX_W_0F50_M_0,
1716   VEX_W_0F51_P_0,
1717   VEX_W_0F51_P_1,
1718   VEX_W_0F51_P_2,
1719   VEX_W_0F51_P_3,
1720   VEX_W_0F52_P_0,
1721   VEX_W_0F52_P_1,
1722   VEX_W_0F53_P_0,
1723   VEX_W_0F53_P_1,
1724   VEX_W_0F58_P_0,
1725   VEX_W_0F58_P_1,
1726   VEX_W_0F58_P_2,
1727   VEX_W_0F58_P_3,
1728   VEX_W_0F59_P_0,
1729   VEX_W_0F59_P_1,
1730   VEX_W_0F59_P_2,
1731   VEX_W_0F59_P_3,
1732   VEX_W_0F5A_P_0,
1733   VEX_W_0F5A_P_1,
1734   VEX_W_0F5A_P_3,
1735   VEX_W_0F5B_P_0,
1736   VEX_W_0F5B_P_1,
1737   VEX_W_0F5B_P_2,
1738   VEX_W_0F5C_P_0,
1739   VEX_W_0F5C_P_1,
1740   VEX_W_0F5C_P_2,
1741   VEX_W_0F5C_P_3,
1742   VEX_W_0F5D_P_0,
1743   VEX_W_0F5D_P_1,
1744   VEX_W_0F5D_P_2,
1745   VEX_W_0F5D_P_3,
1746   VEX_W_0F5E_P_0,
1747   VEX_W_0F5E_P_1,
1748   VEX_W_0F5E_P_2,
1749   VEX_W_0F5E_P_3,
1750   VEX_W_0F5F_P_0,
1751   VEX_W_0F5F_P_1,
1752   VEX_W_0F5F_P_2,
1753   VEX_W_0F5F_P_3,
1754   VEX_W_0F60_P_2,
1755   VEX_W_0F61_P_2,
1756   VEX_W_0F62_P_2,
1757   VEX_W_0F63_P_2,
1758   VEX_W_0F64_P_2,
1759   VEX_W_0F65_P_2,
1760   VEX_W_0F66_P_2,
1761   VEX_W_0F67_P_2,
1762   VEX_W_0F68_P_2,
1763   VEX_W_0F69_P_2,
1764   VEX_W_0F6A_P_2,
1765   VEX_W_0F6B_P_2,
1766   VEX_W_0F6C_P_2,
1767   VEX_W_0F6D_P_2,
1768   VEX_W_0F6F_P_1,
1769   VEX_W_0F6F_P_2,
1770   VEX_W_0F70_P_1,
1771   VEX_W_0F70_P_2,
1772   VEX_W_0F70_P_3,
1773   VEX_W_0F71_R_2_P_2,
1774   VEX_W_0F71_R_4_P_2,
1775   VEX_W_0F71_R_6_P_2,
1776   VEX_W_0F72_R_2_P_2,
1777   VEX_W_0F72_R_4_P_2,
1778   VEX_W_0F72_R_6_P_2,
1779   VEX_W_0F73_R_2_P_2,
1780   VEX_W_0F73_R_3_P_2,
1781   VEX_W_0F73_R_6_P_2,
1782   VEX_W_0F73_R_7_P_2,
1783   VEX_W_0F74_P_2,
1784   VEX_W_0F75_P_2,
1785   VEX_W_0F76_P_2,
1786   VEX_W_0F77_P_0,
1787   VEX_W_0F7C_P_2,
1788   VEX_W_0F7C_P_3,
1789   VEX_W_0F7D_P_2,
1790   VEX_W_0F7D_P_3,
1791   VEX_W_0F7E_P_1,
1792   VEX_W_0F7F_P_1,
1793   VEX_W_0F7F_P_2,
1794   VEX_W_0F90_P_0_LEN_0,
1795   VEX_W_0F91_P_0_LEN_0,
1796   VEX_W_0F92_P_0_LEN_0,
1797   VEX_W_0F93_P_0_LEN_0,
1798   VEX_W_0F98_P_0_LEN_0,
1799   VEX_W_0FAE_R_2_M_0,
1800   VEX_W_0FAE_R_3_M_0,
1801   VEX_W_0FC2_P_0,
1802   VEX_W_0FC2_P_1,
1803   VEX_W_0FC2_P_2,
1804   VEX_W_0FC2_P_3,
1805   VEX_W_0FC4_P_2,
1806   VEX_W_0FC5_P_2,
1807   VEX_W_0FD0_P_2,
1808   VEX_W_0FD0_P_3,
1809   VEX_W_0FD1_P_2,
1810   VEX_W_0FD2_P_2,
1811   VEX_W_0FD3_P_2,
1812   VEX_W_0FD4_P_2,
1813   VEX_W_0FD5_P_2,
1814   VEX_W_0FD6_P_2,
1815   VEX_W_0FD7_P_2_M_1,
1816   VEX_W_0FD8_P_2,
1817   VEX_W_0FD9_P_2,
1818   VEX_W_0FDA_P_2,
1819   VEX_W_0FDB_P_2,
1820   VEX_W_0FDC_P_2,
1821   VEX_W_0FDD_P_2,
1822   VEX_W_0FDE_P_2,
1823   VEX_W_0FDF_P_2,
1824   VEX_W_0FE0_P_2,
1825   VEX_W_0FE1_P_2,
1826   VEX_W_0FE2_P_2,
1827   VEX_W_0FE3_P_2,
1828   VEX_W_0FE4_P_2,
1829   VEX_W_0FE5_P_2,
1830   VEX_W_0FE6_P_1,
1831   VEX_W_0FE6_P_2,
1832   VEX_W_0FE6_P_3,
1833   VEX_W_0FE7_P_2_M_0,
1834   VEX_W_0FE8_P_2,
1835   VEX_W_0FE9_P_2,
1836   VEX_W_0FEA_P_2,
1837   VEX_W_0FEB_P_2,
1838   VEX_W_0FEC_P_2,
1839   VEX_W_0FED_P_2,
1840   VEX_W_0FEE_P_2,
1841   VEX_W_0FEF_P_2,
1842   VEX_W_0FF0_P_3_M_0,
1843   VEX_W_0FF1_P_2,
1844   VEX_W_0FF2_P_2,
1845   VEX_W_0FF3_P_2,
1846   VEX_W_0FF4_P_2,
1847   VEX_W_0FF5_P_2,
1848   VEX_W_0FF6_P_2,
1849   VEX_W_0FF7_P_2,
1850   VEX_W_0FF8_P_2,
1851   VEX_W_0FF9_P_2,
1852   VEX_W_0FFA_P_2,
1853   VEX_W_0FFB_P_2,
1854   VEX_W_0FFC_P_2,
1855   VEX_W_0FFD_P_2,
1856   VEX_W_0FFE_P_2,
1857   VEX_W_0F3800_P_2,
1858   VEX_W_0F3801_P_2,
1859   VEX_W_0F3802_P_2,
1860   VEX_W_0F3803_P_2,
1861   VEX_W_0F3804_P_2,
1862   VEX_W_0F3805_P_2,
1863   VEX_W_0F3806_P_2,
1864   VEX_W_0F3807_P_2,
1865   VEX_W_0F3808_P_2,
1866   VEX_W_0F3809_P_2,
1867   VEX_W_0F380A_P_2,
1868   VEX_W_0F380B_P_2,
1869   VEX_W_0F380C_P_2,
1870   VEX_W_0F380D_P_2,
1871   VEX_W_0F380E_P_2,
1872   VEX_W_0F380F_P_2,
1873   VEX_W_0F3816_P_2,
1874   VEX_W_0F3817_P_2,
1875   VEX_W_0F3818_P_2,
1876   VEX_W_0F3819_P_2,
1877   VEX_W_0F381A_P_2_M_0,
1878   VEX_W_0F381C_P_2,
1879   VEX_W_0F381D_P_2,
1880   VEX_W_0F381E_P_2,
1881   VEX_W_0F3820_P_2,
1882   VEX_W_0F3821_P_2,
1883   VEX_W_0F3822_P_2,
1884   VEX_W_0F3823_P_2,
1885   VEX_W_0F3824_P_2,
1886   VEX_W_0F3825_P_2,
1887   VEX_W_0F3828_P_2,
1888   VEX_W_0F3829_P_2,
1889   VEX_W_0F382A_P_2_M_0,
1890   VEX_W_0F382B_P_2,
1891   VEX_W_0F382C_P_2_M_0,
1892   VEX_W_0F382D_P_2_M_0,
1893   VEX_W_0F382E_P_2_M_0,
1894   VEX_W_0F382F_P_2_M_0,
1895   VEX_W_0F3830_P_2,
1896   VEX_W_0F3831_P_2,
1897   VEX_W_0F3832_P_2,
1898   VEX_W_0F3833_P_2,
1899   VEX_W_0F3834_P_2,
1900   VEX_W_0F3835_P_2,
1901   VEX_W_0F3836_P_2,
1902   VEX_W_0F3837_P_2,
1903   VEX_W_0F3838_P_2,
1904   VEX_W_0F3839_P_2,
1905   VEX_W_0F383A_P_2,
1906   VEX_W_0F383B_P_2,
1907   VEX_W_0F383C_P_2,
1908   VEX_W_0F383D_P_2,
1909   VEX_W_0F383E_P_2,
1910   VEX_W_0F383F_P_2,
1911   VEX_W_0F3840_P_2,
1912   VEX_W_0F3841_P_2,
1913   VEX_W_0F3846_P_2,
1914   VEX_W_0F3858_P_2,
1915   VEX_W_0F3859_P_2,
1916   VEX_W_0F385A_P_2_M_0,
1917   VEX_W_0F3878_P_2,
1918   VEX_W_0F3879_P_2,
1919   VEX_W_0F38DB_P_2,
1920   VEX_W_0F38DC_P_2,
1921   VEX_W_0F38DD_P_2,
1922   VEX_W_0F38DE_P_2,
1923   VEX_W_0F38DF_P_2,
1924   VEX_W_0F3A00_P_2,
1925   VEX_W_0F3A01_P_2,
1926   VEX_W_0F3A02_P_2,
1927   VEX_W_0F3A04_P_2,
1928   VEX_W_0F3A05_P_2,
1929   VEX_W_0F3A06_P_2,
1930   VEX_W_0F3A08_P_2,
1931   VEX_W_0F3A09_P_2,
1932   VEX_W_0F3A0A_P_2,
1933   VEX_W_0F3A0B_P_2,
1934   VEX_W_0F3A0C_P_2,
1935   VEX_W_0F3A0D_P_2,
1936   VEX_W_0F3A0E_P_2,
1937   VEX_W_0F3A0F_P_2,
1938   VEX_W_0F3A14_P_2,
1939   VEX_W_0F3A15_P_2,
1940   VEX_W_0F3A18_P_2,
1941   VEX_W_0F3A19_P_2,
1942   VEX_W_0F3A20_P_2,
1943   VEX_W_0F3A21_P_2,
1944   VEX_W_0F3A30_P_2_LEN_0,
1945   VEX_W_0F3A32_P_2_LEN_0,
1946   VEX_W_0F3A38_P_2,
1947   VEX_W_0F3A39_P_2,
1948   VEX_W_0F3A40_P_2,
1949   VEX_W_0F3A41_P_2,
1950   VEX_W_0F3A42_P_2,
1951   VEX_W_0F3A44_P_2,
1952   VEX_W_0F3A46_P_2,
1953   VEX_W_0F3A48_P_2,
1954   VEX_W_0F3A49_P_2,
1955   VEX_W_0F3A4A_P_2,
1956   VEX_W_0F3A4B_P_2,
1957   VEX_W_0F3A4C_P_2,
1958   VEX_W_0F3A60_P_2,
1959   VEX_W_0F3A61_P_2,
1960   VEX_W_0F3A62_P_2,
1961   VEX_W_0F3A63_P_2,
1962   VEX_W_0F3ADF_P_2,
1963
1964   EVEX_W_0F10_P_0,
1965   EVEX_W_0F10_P_1_M_0,
1966   EVEX_W_0F10_P_1_M_1,
1967   EVEX_W_0F10_P_2,
1968   EVEX_W_0F10_P_3_M_0,
1969   EVEX_W_0F10_P_3_M_1,
1970   EVEX_W_0F11_P_0,
1971   EVEX_W_0F11_P_1_M_0,
1972   EVEX_W_0F11_P_1_M_1,
1973   EVEX_W_0F11_P_2,
1974   EVEX_W_0F11_P_3_M_0,
1975   EVEX_W_0F11_P_3_M_1,
1976   EVEX_W_0F12_P_0_M_0,
1977   EVEX_W_0F12_P_0_M_1,
1978   EVEX_W_0F12_P_1,
1979   EVEX_W_0F12_P_2,
1980   EVEX_W_0F12_P_3,
1981   EVEX_W_0F13_P_0,
1982   EVEX_W_0F13_P_2,
1983   EVEX_W_0F14_P_0,
1984   EVEX_W_0F14_P_2,
1985   EVEX_W_0F15_P_0,
1986   EVEX_W_0F15_P_2,
1987   EVEX_W_0F16_P_0_M_0,
1988   EVEX_W_0F16_P_0_M_1,
1989   EVEX_W_0F16_P_1,
1990   EVEX_W_0F16_P_2,
1991   EVEX_W_0F17_P_0,
1992   EVEX_W_0F17_P_2,
1993   EVEX_W_0F28_P_0,
1994   EVEX_W_0F28_P_2,
1995   EVEX_W_0F29_P_0,
1996   EVEX_W_0F29_P_2,
1997   EVEX_W_0F2A_P_1,
1998   EVEX_W_0F2A_P_3,
1999   EVEX_W_0F2B_P_0,
2000   EVEX_W_0F2B_P_2,
2001   EVEX_W_0F2E_P_0,
2002   EVEX_W_0F2E_P_2,
2003   EVEX_W_0F2F_P_0,
2004   EVEX_W_0F2F_P_2,
2005   EVEX_W_0F51_P_0,
2006   EVEX_W_0F51_P_1,
2007   EVEX_W_0F51_P_2,
2008   EVEX_W_0F51_P_3,
2009   EVEX_W_0F58_P_0,
2010   EVEX_W_0F58_P_1,
2011   EVEX_W_0F58_P_2,
2012   EVEX_W_0F58_P_3,
2013   EVEX_W_0F59_P_0,
2014   EVEX_W_0F59_P_1,
2015   EVEX_W_0F59_P_2,
2016   EVEX_W_0F59_P_3,
2017   EVEX_W_0F5A_P_0,
2018   EVEX_W_0F5A_P_1,
2019   EVEX_W_0F5A_P_2,
2020   EVEX_W_0F5A_P_3,
2021   EVEX_W_0F5B_P_0,
2022   EVEX_W_0F5B_P_1,
2023   EVEX_W_0F5B_P_2,
2024   EVEX_W_0F5C_P_0,
2025   EVEX_W_0F5C_P_1,
2026   EVEX_W_0F5C_P_2,
2027   EVEX_W_0F5C_P_3,
2028   EVEX_W_0F5D_P_0,
2029   EVEX_W_0F5D_P_1,
2030   EVEX_W_0F5D_P_2,
2031   EVEX_W_0F5D_P_3,
2032   EVEX_W_0F5E_P_0,
2033   EVEX_W_0F5E_P_1,
2034   EVEX_W_0F5E_P_2,
2035   EVEX_W_0F5E_P_3,
2036   EVEX_W_0F5F_P_0,
2037   EVEX_W_0F5F_P_1,
2038   EVEX_W_0F5F_P_2,
2039   EVEX_W_0F5F_P_3,
2040   EVEX_W_0F62_P_2,
2041   EVEX_W_0F66_P_2,
2042   EVEX_W_0F6A_P_2,
2043   EVEX_W_0F6C_P_2,
2044   EVEX_W_0F6D_P_2,
2045   EVEX_W_0F6E_P_2,
2046   EVEX_W_0F6F_P_1,
2047   EVEX_W_0F6F_P_2,
2048   EVEX_W_0F70_P_2,
2049   EVEX_W_0F72_R_2_P_2,
2050   EVEX_W_0F72_R_6_P_2,
2051   EVEX_W_0F73_R_2_P_2,
2052   EVEX_W_0F73_R_6_P_2,
2053   EVEX_W_0F76_P_2,
2054   EVEX_W_0F78_P_0,
2055   EVEX_W_0F79_P_0,
2056   EVEX_W_0F7A_P_1,
2057   EVEX_W_0F7A_P_3,
2058   EVEX_W_0F7B_P_1,
2059   EVEX_W_0F7B_P_3,
2060   EVEX_W_0F7E_P_1,
2061   EVEX_W_0F7E_P_2,
2062   EVEX_W_0F7F_P_1,
2063   EVEX_W_0F7F_P_2,
2064   EVEX_W_0FC2_P_0,
2065   EVEX_W_0FC2_P_1,
2066   EVEX_W_0FC2_P_2,
2067   EVEX_W_0FC2_P_3,
2068   EVEX_W_0FC6_P_0,
2069   EVEX_W_0FC6_P_2,
2070   EVEX_W_0FD2_P_2,
2071   EVEX_W_0FD3_P_2,
2072   EVEX_W_0FD4_P_2,
2073   EVEX_W_0FD6_P_2,
2074   EVEX_W_0FE6_P_1,
2075   EVEX_W_0FE6_P_2,
2076   EVEX_W_0FE6_P_3,
2077   EVEX_W_0FE7_P_2,
2078   EVEX_W_0FF2_P_2,
2079   EVEX_W_0FF3_P_2,
2080   EVEX_W_0FF4_P_2,
2081   EVEX_W_0FFA_P_2,
2082   EVEX_W_0FFB_P_2,
2083   EVEX_W_0FFE_P_2,
2084   EVEX_W_0F380C_P_2,
2085   EVEX_W_0F380D_P_2,
2086   EVEX_W_0F3811_P_1,
2087   EVEX_W_0F3812_P_1,
2088   EVEX_W_0F3813_P_1,
2089   EVEX_W_0F3813_P_2,
2090   EVEX_W_0F3814_P_1,
2091   EVEX_W_0F3815_P_1,
2092   EVEX_W_0F3818_P_2,
2093   EVEX_W_0F3819_P_2,
2094   EVEX_W_0F381A_P_2,
2095   EVEX_W_0F381B_P_2,
2096   EVEX_W_0F381E_P_2,
2097   EVEX_W_0F381F_P_2,
2098   EVEX_W_0F3821_P_1,
2099   EVEX_W_0F3822_P_1,
2100   EVEX_W_0F3823_P_1,
2101   EVEX_W_0F3824_P_1,
2102   EVEX_W_0F3825_P_1,
2103   EVEX_W_0F3825_P_2,
2104   EVEX_W_0F3828_P_2,
2105   EVEX_W_0F3829_P_2,
2106   EVEX_W_0F382A_P_1,
2107   EVEX_W_0F382A_P_2,
2108   EVEX_W_0F3831_P_1,
2109   EVEX_W_0F3832_P_1,
2110   EVEX_W_0F3833_P_1,
2111   EVEX_W_0F3834_P_1,
2112   EVEX_W_0F3835_P_1,
2113   EVEX_W_0F3835_P_2,
2114   EVEX_W_0F3837_P_2,
2115   EVEX_W_0F383A_P_1,
2116   EVEX_W_0F3840_P_2,
2117   EVEX_W_0F3858_P_2,
2118   EVEX_W_0F3859_P_2,
2119   EVEX_W_0F385A_P_2,
2120   EVEX_W_0F385B_P_2,
2121   EVEX_W_0F3891_P_2,
2122   EVEX_W_0F3893_P_2,
2123   EVEX_W_0F38A1_P_2,
2124   EVEX_W_0F38A3_P_2,
2125   EVEX_W_0F38C7_R_1_P_2,
2126   EVEX_W_0F38C7_R_2_P_2,
2127   EVEX_W_0F38C7_R_5_P_2,
2128   EVEX_W_0F38C7_R_6_P_2,
2129
2130   EVEX_W_0F3A00_P_2,
2131   EVEX_W_0F3A01_P_2,
2132   EVEX_W_0F3A04_P_2,
2133   EVEX_W_0F3A05_P_2,
2134   EVEX_W_0F3A08_P_2,
2135   EVEX_W_0F3A09_P_2,
2136   EVEX_W_0F3A0A_P_2,
2137   EVEX_W_0F3A0B_P_2,
2138   EVEX_W_0F3A18_P_2,
2139   EVEX_W_0F3A19_P_2,
2140   EVEX_W_0F3A1A_P_2,
2141   EVEX_W_0F3A1B_P_2,
2142   EVEX_W_0F3A1D_P_2,
2143   EVEX_W_0F3A21_P_2,
2144   EVEX_W_0F3A23_P_2,
2145   EVEX_W_0F3A38_P_2,
2146   EVEX_W_0F3A39_P_2,
2147   EVEX_W_0F3A3A_P_2,
2148   EVEX_W_0F3A3B_P_2,
2149   EVEX_W_0F3A43_P_2,
2150 };
2151
2152 typedef void (*op_rtn) (int bytemode, int sizeflag);
2153
2154 struct dis386 {
2155   const char *name;
2156   struct
2157     {
2158       op_rtn rtn;
2159       int bytemode;
2160     } op[MAX_OPERANDS];
2161 };
2162
2163 /* Upper case letters in the instruction names here are macros.
2164    'A' => print 'b' if no register operands or suffix_always is true
2165    'B' => print 'b' if suffix_always is true
2166    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2167           size prefix
2168    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2169           suffix_always is true
2170    'E' => print 'e' if 32-bit form of jcxz
2171    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2172    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2173    'H' => print ",pt" or ",pn" branch hint
2174    'I' => honor following macro letter even in Intel mode (implemented only
2175           for some of the macro letters)
2176    'J' => print 'l'
2177    'K' => print 'd' or 'q' if rex prefix is present.
2178    'L' => print 'l' if suffix_always is true
2179    'M' => print 'r' if intel_mnemonic is false.
2180    'N' => print 'n' if instruction has no wait "prefix"
2181    'O' => print 'd' or 'o' (or 'q' in Intel mode)
2182    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2183           or suffix_always is true.  print 'q' if rex prefix is present.
2184    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2185           is true
2186    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2187    'S' => print 'w', 'l' or 'q' if suffix_always is true
2188    'T' => print 'q' in 64bit mode and behave as 'P' otherwise
2189    'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
2190    'V' => print 'q' in 64bit mode and behave as 'S' otherwise
2191    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2192    'X' => print 's', 'd' depending on data16 prefix (for XMM)
2193    'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
2194           suffix_always is true.
2195    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2196    '!' => change condition from true to false or from false to true.
2197    '%' => add 1 upper case letter to the macro.
2198
2199    2 upper case letter macros:
2200    "XY" => print 'x' or 'y' if no register operands or suffix_always
2201            is true.
2202    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2203    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2204            or suffix_always is true
2205    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2206    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2207    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2208    "LW" => print 'd', 'q' depending on the VEX.W bit
2209
2210    Many of the above letters print nothing in Intel mode.  See "putop"
2211    for the details.
2212
2213    Braces '{' and '}', and vertical bars '|', indicate alternative
2214    mnemonic strings for AT&T and Intel.  */
2215
2216 static const struct dis386 dis386[] = {
2217   /* 00 */
2218   { "addB",             { Ebh1, Gb } },
2219   { "addS",             { Evh1, Gv } },
2220   { "addB",             { Gb, EbS } },
2221   { "addS",             { Gv, EvS } },
2222   { "addB",             { AL, Ib } },
2223   { "addS",             { eAX, Iv } },
2224   { X86_64_TABLE (X86_64_06) },
2225   { X86_64_TABLE (X86_64_07) },
2226   /* 08 */
2227   { "orB",              { Ebh1, Gb } },
2228   { "orS",              { Evh1, Gv } },
2229   { "orB",              { Gb, EbS } },
2230   { "orS",              { Gv, EvS } },
2231   { "orB",              { AL, Ib } },
2232   { "orS",              { eAX, Iv } },
2233   { X86_64_TABLE (X86_64_0D) },
2234   { Bad_Opcode },       /* 0x0f extended opcode escape */
2235   /* 10 */
2236   { "adcB",             { Ebh1, Gb } },
2237   { "adcS",             { Evh1, Gv } },
2238   { "adcB",             { Gb, EbS } },
2239   { "adcS",             { Gv, EvS } },
2240   { "adcB",             { AL, Ib } },
2241   { "adcS",             { eAX, Iv } },
2242   { X86_64_TABLE (X86_64_16) },
2243   { X86_64_TABLE (X86_64_17) },
2244   /* 18 */
2245   { "sbbB",             { Ebh1, Gb } },
2246   { "sbbS",             { Evh1, Gv } },
2247   { "sbbB",             { Gb, EbS } },
2248   { "sbbS",             { Gv, EvS } },
2249   { "sbbB",             { AL, Ib } },
2250   { "sbbS",             { eAX, Iv } },
2251   { X86_64_TABLE (X86_64_1E) },
2252   { X86_64_TABLE (X86_64_1F) },
2253   /* 20 */
2254   { "andB",             { Ebh1, Gb } },
2255   { "andS",             { Evh1, Gv } },
2256   { "andB",             { Gb, EbS } },
2257   { "andS",             { Gv, EvS } },
2258   { "andB",             { AL, Ib } },
2259   { "andS",             { eAX, Iv } },
2260   { Bad_Opcode },       /* SEG ES prefix */
2261   { X86_64_TABLE (X86_64_27) },
2262   /* 28 */
2263   { "subB",             { Ebh1, Gb } },
2264   { "subS",             { Evh1, Gv } },
2265   { "subB",             { Gb, EbS } },
2266   { "subS",             { Gv, EvS } },
2267   { "subB",             { AL, Ib } },
2268   { "subS",             { eAX, Iv } },
2269   { Bad_Opcode },       /* SEG CS prefix */
2270   { X86_64_TABLE (X86_64_2F) },
2271   /* 30 */
2272   { "xorB",             { Ebh1, Gb } },
2273   { "xorS",             { Evh1, Gv } },
2274   { "xorB",             { Gb, EbS } },
2275   { "xorS",             { Gv, EvS } },
2276   { "xorB",             { AL, Ib } },
2277   { "xorS",             { eAX, Iv } },
2278   { Bad_Opcode },       /* SEG SS prefix */
2279   { X86_64_TABLE (X86_64_37) },
2280   /* 38 */
2281   { "cmpB",             { Eb, Gb } },
2282   { "cmpS",             { Ev, Gv } },
2283   { "cmpB",             { Gb, EbS } },
2284   { "cmpS",             { Gv, EvS } },
2285   { "cmpB",             { AL, Ib } },
2286   { "cmpS",             { eAX, Iv } },
2287   { Bad_Opcode },       /* SEG DS prefix */
2288   { X86_64_TABLE (X86_64_3F) },
2289   /* 40 */
2290   { "inc{S|}",          { RMeAX } },
2291   { "inc{S|}",          { RMeCX } },
2292   { "inc{S|}",          { RMeDX } },
2293   { "inc{S|}",          { RMeBX } },
2294   { "inc{S|}",          { RMeSP } },
2295   { "inc{S|}",          { RMeBP } },
2296   { "inc{S|}",          { RMeSI } },
2297   { "inc{S|}",          { RMeDI } },
2298   /* 48 */
2299   { "dec{S|}",          { RMeAX } },
2300   { "dec{S|}",          { RMeCX } },
2301   { "dec{S|}",          { RMeDX } },
2302   { "dec{S|}",          { RMeBX } },
2303   { "dec{S|}",          { RMeSP } },
2304   { "dec{S|}",          { RMeBP } },
2305   { "dec{S|}",          { RMeSI } },
2306   { "dec{S|}",          { RMeDI } },
2307   /* 50 */
2308   { "pushV",            { RMrAX } },
2309   { "pushV",            { RMrCX } },
2310   { "pushV",            { RMrDX } },
2311   { "pushV",            { RMrBX } },
2312   { "pushV",            { RMrSP } },
2313   { "pushV",            { RMrBP } },
2314   { "pushV",            { RMrSI } },
2315   { "pushV",            { RMrDI } },
2316   /* 58 */
2317   { "popV",             { RMrAX } },
2318   { "popV",             { RMrCX } },
2319   { "popV",             { RMrDX } },
2320   { "popV",             { RMrBX } },
2321   { "popV",             { RMrSP } },
2322   { "popV",             { RMrBP } },
2323   { "popV",             { RMrSI } },
2324   { "popV",             { RMrDI } },
2325   /* 60 */
2326   { X86_64_TABLE (X86_64_60) },
2327   { X86_64_TABLE (X86_64_61) },
2328   { X86_64_TABLE (X86_64_62) },
2329   { X86_64_TABLE (X86_64_63) },
2330   { Bad_Opcode },       /* seg fs */
2331   { Bad_Opcode },       /* seg gs */
2332   { Bad_Opcode },       /* op size prefix */
2333   { Bad_Opcode },       /* adr size prefix */
2334   /* 68 */
2335   { "pushT",            { sIv } },
2336   { "imulS",            { Gv, Ev, Iv } },
2337   { "pushT",            { sIbT } },
2338   { "imulS",            { Gv, Ev, sIb } },
2339   { "ins{b|}",          { Ybr, indirDX } },
2340   { X86_64_TABLE (X86_64_6D) },
2341   { "outs{b|}",         { indirDXr, Xb } },
2342   { X86_64_TABLE (X86_64_6F) },
2343   /* 70 */
2344   { "joH",              { Jb, BND, cond_jump_flag } },
2345   { "jnoH",             { Jb, BND, cond_jump_flag } },
2346   { "jbH",              { Jb, BND, cond_jump_flag } },
2347   { "jaeH",             { Jb, BND, cond_jump_flag } },
2348   { "jeH",              { Jb, BND, cond_jump_flag } },
2349   { "jneH",             { Jb, BND, cond_jump_flag } },
2350   { "jbeH",             { Jb, BND, cond_jump_flag } },
2351   { "jaH",              { Jb, BND, cond_jump_flag } },
2352   /* 78 */
2353   { "jsH",              { Jb, BND, cond_jump_flag } },
2354   { "jnsH",             { Jb, BND, cond_jump_flag } },
2355   { "jpH",              { Jb, BND, cond_jump_flag } },
2356   { "jnpH",             { Jb, BND, cond_jump_flag } },
2357   { "jlH",              { Jb, BND, cond_jump_flag } },
2358   { "jgeH",             { Jb, BND, cond_jump_flag } },
2359   { "jleH",             { Jb, BND, cond_jump_flag } },
2360   { "jgH",              { Jb, BND, cond_jump_flag } },
2361   /* 80 */
2362   { REG_TABLE (REG_80) },
2363   { REG_TABLE (REG_81) },
2364   { Bad_Opcode },
2365   { REG_TABLE (REG_82) },
2366   { "testB",            { Eb, Gb } },
2367   { "testS",            { Ev, Gv } },
2368   { "xchgB",            { Ebh2, Gb } },
2369   { "xchgS",            { Evh2, Gv } },
2370   /* 88 */
2371   { "movB",             { Ebh3, Gb } },
2372   { "movS",             { Evh3, Gv } },
2373   { "movB",             { Gb, EbS } },
2374   { "movS",             { Gv, EvS } },
2375   { "movD",             { Sv, Sw } },
2376   { MOD_TABLE (MOD_8D) },
2377   { "movD",             { Sw, Sv } },
2378   { REG_TABLE (REG_8F) },
2379   /* 90 */
2380   { PREFIX_TABLE (PREFIX_90) },
2381   { "xchgS",            { RMeCX, eAX } },
2382   { "xchgS",            { RMeDX, eAX } },
2383   { "xchgS",            { RMeBX, eAX } },
2384   { "xchgS",            { RMeSP, eAX } },
2385   { "xchgS",            { RMeBP, eAX } },
2386   { "xchgS",            { RMeSI, eAX } },
2387   { "xchgS",            { RMeDI, eAX } },
2388   /* 98 */
2389   { "cW{t|}R",          { XX } },
2390   { "cR{t|}O",          { XX } },
2391   { X86_64_TABLE (X86_64_9A) },
2392   { Bad_Opcode },       /* fwait */
2393   { "pushfT",           { XX } },
2394   { "popfT",            { XX } },
2395   { "sahf",             { XX } },
2396   { "lahf",             { XX } },
2397   /* a0 */
2398   { "mov%LB",           { AL, Ob } },
2399   { "mov%LS",           { eAX, Ov } },
2400   { "mov%LB",           { Ob, AL } },
2401   { "mov%LS",           { Ov, eAX } },
2402   { "movs{b|}",         { Ybr, Xb } },
2403   { "movs{R|}",         { Yvr, Xv } },
2404   { "cmps{b|}",         { Xb, Yb } },
2405   { "cmps{R|}",         { Xv, Yv } },
2406   /* a8 */
2407   { "testB",            { AL, Ib } },
2408   { "testS",            { eAX, Iv } },
2409   { "stosB",            { Ybr, AL } },
2410   { "stosS",            { Yvr, eAX } },
2411   { "lodsB",            { ALr, Xb } },
2412   { "lodsS",            { eAXr, Xv } },
2413   { "scasB",            { AL, Yb } },
2414   { "scasS",            { eAX, Yv } },
2415   /* b0 */
2416   { "movB",             { RMAL, Ib } },
2417   { "movB",             { RMCL, Ib } },
2418   { "movB",             { RMDL, Ib } },
2419   { "movB",             { RMBL, Ib } },
2420   { "movB",             { RMAH, Ib } },
2421   { "movB",             { RMCH, Ib } },
2422   { "movB",             { RMDH, Ib } },
2423   { "movB",             { RMBH, Ib } },
2424   /* b8 */
2425   { "mov%LV",           { RMeAX, Iv64 } },
2426   { "mov%LV",           { RMeCX, Iv64 } },
2427   { "mov%LV",           { RMeDX, Iv64 } },
2428   { "mov%LV",           { RMeBX, Iv64 } },
2429   { "mov%LV",           { RMeSP, Iv64 } },
2430   { "mov%LV",           { RMeBP, Iv64 } },
2431   { "mov%LV",           { RMeSI, Iv64 } },
2432   { "mov%LV",           { RMeDI, Iv64 } },
2433   /* c0 */
2434   { REG_TABLE (REG_C0) },
2435   { REG_TABLE (REG_C1) },
2436   { "retT",             { Iw, BND } },
2437   { "retT",             { BND } },
2438   { X86_64_TABLE (X86_64_C4) },
2439   { X86_64_TABLE (X86_64_C5) },
2440   { REG_TABLE (REG_C6) },
2441   { REG_TABLE (REG_C7) },
2442   /* c8 */
2443   { "enterT",           { Iw, Ib } },
2444   { "leaveT",           { XX } },
2445   { "Jret{|f}P",        { Iw } },
2446   { "Jret{|f}P",        { XX } },
2447   { "int3",             { XX } },
2448   { "int",              { Ib } },
2449   { X86_64_TABLE (X86_64_CE) },
2450   { "iretP",            { XX } },
2451   /* d0 */
2452   { REG_TABLE (REG_D0) },
2453   { REG_TABLE (REG_D1) },
2454   { REG_TABLE (REG_D2) },
2455   { REG_TABLE (REG_D3) },
2456   { X86_64_TABLE (X86_64_D4) },
2457   { X86_64_TABLE (X86_64_D5) },
2458   { Bad_Opcode },
2459   { "xlat",             { DSBX } },
2460   /* d8 */
2461   { FLOAT },
2462   { FLOAT },
2463   { FLOAT },
2464   { FLOAT },
2465   { FLOAT },
2466   { FLOAT },
2467   { FLOAT },
2468   { FLOAT },
2469   /* e0 */
2470   { "loopneFH",         { Jb, XX, loop_jcxz_flag } },
2471   { "loopeFH",          { Jb, XX, loop_jcxz_flag } },
2472   { "loopFH",           { Jb, XX, loop_jcxz_flag } },
2473   { "jEcxzH",           { Jb, XX, loop_jcxz_flag } },
2474   { "inB",              { AL, Ib } },
2475   { "inG",              { zAX, Ib } },
2476   { "outB",             { Ib, AL } },
2477   { "outG",             { Ib, zAX } },
2478   /* e8 */
2479   { "callT",            { Jv, BND } },
2480   { "jmpT",             { Jv, BND } },
2481   { X86_64_TABLE (X86_64_EA) },
2482   { "jmp",              { Jb, BND } },
2483   { "inB",              { AL, indirDX } },
2484   { "inG",              { zAX, indirDX } },
2485   { "outB",             { indirDX, AL } },
2486   { "outG",             { indirDX, zAX } },
2487   /* f0 */
2488   { Bad_Opcode },       /* lock prefix */
2489   { "icebp",            { XX } },
2490   { Bad_Opcode },       /* repne */
2491   { Bad_Opcode },       /* repz */
2492   { "hlt",              { XX } },
2493   { "cmc",              { XX } },
2494   { REG_TABLE (REG_F6) },
2495   { REG_TABLE (REG_F7) },
2496   /* f8 */
2497   { "clc",              { XX } },
2498   { "stc",              { XX } },
2499   { "cli",              { XX } },
2500   { "sti",              { XX } },
2501   { "cld",              { XX } },
2502   { "std",              { XX } },
2503   { REG_TABLE (REG_FE) },
2504   { REG_TABLE (REG_FF) },
2505 };
2506
2507 static const struct dis386 dis386_twobyte[] = {
2508   /* 00 */
2509   { REG_TABLE (REG_0F00 ) },
2510   { REG_TABLE (REG_0F01 ) },
2511   { "larS",             { Gv, Ew } },
2512   { "lslS",             { Gv, Ew } },
2513   { Bad_Opcode },
2514   { "syscall",          { XX } },
2515   { "clts",             { XX } },
2516   { "sysretP",          { XX } },
2517   /* 08 */
2518   { "invd",             { XX } },
2519   { "wbinvd",           { XX } },
2520   { Bad_Opcode },
2521   { "ud2",              { XX } },
2522   { Bad_Opcode },
2523   { REG_TABLE (REG_0F0D) },
2524   { "femms",            { XX } },
2525   { "",                 { MX, EM, OPSUF } }, /* See OP_3DNowSuffix.  */
2526   /* 10 */
2527   { PREFIX_TABLE (PREFIX_0F10) },
2528   { PREFIX_TABLE (PREFIX_0F11) },
2529   { PREFIX_TABLE (PREFIX_0F12) },
2530   { MOD_TABLE (MOD_0F13) },
2531   { "unpcklpX",         { XM, EXx } },
2532   { "unpckhpX",         { XM, EXx } },
2533   { PREFIX_TABLE (PREFIX_0F16) },
2534   { MOD_TABLE (MOD_0F17) },
2535   /* 18 */
2536   { REG_TABLE (REG_0F18) },
2537   { "nopQ",             { Ev } },
2538   { PREFIX_TABLE (PREFIX_0F1A) },
2539   { PREFIX_TABLE (PREFIX_0F1B) },
2540   { "nopQ",             { Ev } },
2541   { "nopQ",             { Ev } },
2542   { "nopQ",             { Ev } },
2543   { "nopQ",             { Ev } },
2544   /* 20 */
2545   { MOD_TABLE (MOD_0F20) },
2546   { MOD_TABLE (MOD_0F21) },
2547   { MOD_TABLE (MOD_0F22) },
2548   { MOD_TABLE (MOD_0F23) },
2549   { MOD_TABLE (MOD_0F24) },
2550   { Bad_Opcode },
2551   { MOD_TABLE (MOD_0F26) },
2552   { Bad_Opcode },
2553   /* 28 */
2554   { "movapX",           { XM, EXx } },
2555   { "movapX",           { EXxS, XM } },
2556   { PREFIX_TABLE (PREFIX_0F2A) },
2557   { PREFIX_TABLE (PREFIX_0F2B) },
2558   { PREFIX_TABLE (PREFIX_0F2C) },
2559   { PREFIX_TABLE (PREFIX_0F2D) },
2560   { PREFIX_TABLE (PREFIX_0F2E) },
2561   { PREFIX_TABLE (PREFIX_0F2F) },
2562   /* 30 */
2563   { "wrmsr",            { XX } },
2564   { "rdtsc",            { XX } },
2565   { "rdmsr",            { XX } },
2566   { "rdpmc",            { XX } },
2567   { "sysenter",         { XX } },
2568   { "sysexit",          { XX } },
2569   { Bad_Opcode },
2570   { "getsec",           { XX } },
2571   /* 38 */
2572   { THREE_BYTE_TABLE (THREE_BYTE_0F38) },
2573   { Bad_Opcode },
2574   { THREE_BYTE_TABLE (THREE_BYTE_0F3A) },
2575   { Bad_Opcode },
2576   { Bad_Opcode },
2577   { Bad_Opcode },
2578   { Bad_Opcode },
2579   { Bad_Opcode },
2580   /* 40 */
2581   { "cmovoS",           { Gv, Ev } },
2582   { "cmovnoS",          { Gv, Ev } },
2583   { "cmovbS",           { Gv, Ev } },
2584   { "cmovaeS",          { Gv, Ev } },
2585   { "cmoveS",           { Gv, Ev } },
2586   { "cmovneS",          { Gv, Ev } },
2587   { "cmovbeS",          { Gv, Ev } },
2588   { "cmovaS",           { Gv, Ev } },
2589   /* 48 */
2590   { "cmovsS",           { Gv, Ev } },
2591   { "cmovnsS",          { Gv, Ev } },
2592   { "cmovpS",           { Gv, Ev } },
2593   { "cmovnpS",          { Gv, Ev } },
2594   { "cmovlS",           { Gv, Ev } },
2595   { "cmovgeS",          { Gv, Ev } },
2596   { "cmovleS",          { Gv, Ev } },
2597   { "cmovgS",           { Gv, Ev } },
2598   /* 50 */
2599   { MOD_TABLE (MOD_0F51) },
2600   { PREFIX_TABLE (PREFIX_0F51) },
2601   { PREFIX_TABLE (PREFIX_0F52) },
2602   { PREFIX_TABLE (PREFIX_0F53) },
2603   { "andpX",            { XM, EXx } },
2604   { "andnpX",           { XM, EXx } },
2605   { "orpX",             { XM, EXx } },
2606   { "xorpX",            { XM, EXx } },
2607   /* 58 */
2608   { PREFIX_TABLE (PREFIX_0F58) },
2609   { PREFIX_TABLE (PREFIX_0F59) },
2610   { PREFIX_TABLE (PREFIX_0F5A) },
2611   { PREFIX_TABLE (PREFIX_0F5B) },
2612   { PREFIX_TABLE (PREFIX_0F5C) },
2613   { PREFIX_TABLE (PREFIX_0F5D) },
2614   { PREFIX_TABLE (PREFIX_0F5E) },
2615   { PREFIX_TABLE (PREFIX_0F5F) },
2616   /* 60 */
2617   { PREFIX_TABLE (PREFIX_0F60) },
2618   { PREFIX_TABLE (PREFIX_0F61) },
2619   { PREFIX_TABLE (PREFIX_0F62) },
2620   { "packsswb",         { MX, EM } },
2621   { "pcmpgtb",          { MX, EM } },
2622   { "pcmpgtw",          { MX, EM } },
2623   { "pcmpgtd",          { MX, EM } },
2624   { "packuswb",         { MX, EM } },
2625   /* 68 */
2626   { "punpckhbw",        { MX, EM } },
2627   { "punpckhwd",        { MX, EM } },
2628   { "punpckhdq",        { MX, EM } },
2629   { "packssdw",         { MX, EM } },
2630   { PREFIX_TABLE (PREFIX_0F6C) },
2631   { PREFIX_TABLE (PREFIX_0F6D) },
2632   { "movK",             { MX, Edq } },
2633   { PREFIX_TABLE (PREFIX_0F6F) },
2634   /* 70 */
2635   { PREFIX_TABLE (PREFIX_0F70) },
2636   { REG_TABLE (REG_0F71) },
2637   { REG_TABLE (REG_0F72) },
2638   { REG_TABLE (REG_0F73) },
2639   { "pcmpeqb",          { MX, EM } },
2640   { "pcmpeqw",          { MX, EM } },
2641   { "pcmpeqd",          { MX, EM } },
2642   { "emms",             { XX } },
2643   /* 78 */
2644   { PREFIX_TABLE (PREFIX_0F78) },
2645   { PREFIX_TABLE (PREFIX_0F79) },
2646   { THREE_BYTE_TABLE (THREE_BYTE_0F7A) },
2647   { Bad_Opcode },
2648   { PREFIX_TABLE (PREFIX_0F7C) },
2649   { PREFIX_TABLE (PREFIX_0F7D) },
2650   { PREFIX_TABLE (PREFIX_0F7E) },
2651   { PREFIX_TABLE (PREFIX_0F7F) },
2652   /* 80 */
2653   { "joH",              { Jv, BND, cond_jump_flag } },
2654   { "jnoH",             { Jv, BND, cond_jump_flag } },
2655   { "jbH",              { Jv, BND, cond_jump_flag } },
2656   { "jaeH",             { Jv, BND, cond_jump_flag } },
2657   { "jeH",              { Jv, BND, cond_jump_flag } },
2658   { "jneH",             { Jv, BND, cond_jump_flag } },
2659   { "jbeH",             { Jv, BND, cond_jump_flag } },
2660   { "jaH",              { Jv, BND, cond_jump_flag } },
2661   /* 88 */
2662   { "jsH",              { Jv, BND, cond_jump_flag } },
2663   { "jnsH",             { Jv, BND, cond_jump_flag } },
2664   { "jpH",              { Jv, BND, cond_jump_flag } },
2665   { "jnpH",             { Jv, BND, cond_jump_flag } },
2666   { "jlH",              { Jv, BND, cond_jump_flag } },
2667   { "jgeH",             { Jv, BND, cond_jump_flag } },
2668   { "jleH",             { Jv, BND, cond_jump_flag } },
2669   { "jgH",              { Jv, BND, cond_jump_flag } },
2670   /* 90 */
2671   { "seto",             { Eb } },
2672   { "setno",            { Eb } },
2673   { "setb",             { Eb } },
2674   { "setae",            { Eb } },
2675   { "sete",             { Eb } },
2676   { "setne",            { Eb } },
2677   { "setbe",            { Eb } },
2678   { "seta",             { Eb } },
2679   /* 98 */
2680   { "sets",             { Eb } },
2681   { "setns",            { Eb } },
2682   { "setp",             { Eb } },
2683   { "setnp",            { Eb } },
2684   { "setl",             { Eb } },
2685   { "setge",            { Eb } },
2686   { "setle",            { Eb } },
2687   { "setg",             { Eb } },
2688   /* a0 */
2689   { "pushT",            { fs } },
2690   { "popT",             { fs } },
2691   { "cpuid",            { XX } },
2692   { "btS",              { Ev, Gv } },
2693   { "shldS",            { Ev, Gv, Ib } },
2694   { "shldS",            { Ev, Gv, CL } },
2695   { REG_TABLE (REG_0FA6) },
2696   { REG_TABLE (REG_0FA7) },
2697   /* a8 */
2698   { "pushT",            { gs } },
2699   { "popT",             { gs } },
2700   { "rsm",              { XX } },
2701   { "btsS",             { Evh1, Gv } },
2702   { "shrdS",            { Ev, Gv, Ib } },
2703   { "shrdS",            { Ev, Gv, CL } },
2704   { REG_TABLE (REG_0FAE) },
2705   { "imulS",            { Gv, Ev } },
2706   /* b0 */
2707   { "cmpxchgB",         { Ebh1, Gb } },
2708   { "cmpxchgS",         { Evh1, Gv } },
2709   { MOD_TABLE (MOD_0FB2) },
2710   { "btrS",             { Evh1, Gv } },
2711   { MOD_TABLE (MOD_0FB4) },
2712   { MOD_TABLE (MOD_0FB5) },
2713   { "movz{bR|x}",       { Gv, Eb } },
2714   { "movz{wR|x}",       { Gv, Ew } }, /* yes, there really is movzww ! */
2715   /* b8 */
2716   { PREFIX_TABLE (PREFIX_0FB8) },
2717   { "ud1",              { XX } },
2718   { REG_TABLE (REG_0FBA) },
2719   { "btcS",             { Evh1, Gv } },
2720   { PREFIX_TABLE (PREFIX_0FBC) },
2721   { PREFIX_TABLE (PREFIX_0FBD) },
2722   { "movs{bR|x}",       { Gv, Eb } },
2723   { "movs{wR|x}",       { Gv, Ew } }, /* yes, there really is movsww ! */
2724   /* c0 */
2725   { "xaddB",            { Ebh1, Gb } },
2726   { "xaddS",            { Evh1, Gv } },
2727   { PREFIX_TABLE (PREFIX_0FC2) },
2728   { PREFIX_TABLE (PREFIX_0FC3) },
2729   { "pinsrw",           { MX, Edqw, Ib } },
2730   { "pextrw",           { Gdq, MS, Ib } },
2731   { "shufpX",           { XM, EXx, Ib } },
2732   { REG_TABLE (REG_0FC7) },
2733   /* c8 */
2734   { "bswap",            { RMeAX } },
2735   { "bswap",            { RMeCX } },
2736   { "bswap",            { RMeDX } },
2737   { "bswap",            { RMeBX } },
2738   { "bswap",            { RMeSP } },
2739   { "bswap",            { RMeBP } },
2740   { "bswap",            { RMeSI } },
2741   { "bswap",            { RMeDI } },
2742   /* d0 */
2743   { PREFIX_TABLE (PREFIX_0FD0) },
2744   { "psrlw",            { MX, EM } },
2745   { "psrld",            { MX, EM } },
2746   { "psrlq",            { MX, EM } },
2747   { "paddq",            { MX, EM } },
2748   { "pmullw",           { MX, EM } },
2749   { PREFIX_TABLE (PREFIX_0FD6) },
2750   { MOD_TABLE (MOD_0FD7) },
2751   /* d8 */
2752   { "psubusb",          { MX, EM } },
2753   { "psubusw",          { MX, EM } },
2754   { "pminub",           { MX, EM } },
2755   { "pand",             { MX, EM } },
2756   { "paddusb",          { MX, EM } },
2757   { "paddusw",          { MX, EM } },
2758   { "pmaxub",           { MX, EM } },
2759   { "pandn",            { MX, EM } },
2760   /* e0 */
2761   { "pavgb",            { MX, EM } },
2762   { "psraw",            { MX, EM } },
2763   { "psrad",            { MX, EM } },
2764   { "pavgw",            { MX, EM } },
2765   { "pmulhuw",          { MX, EM } },
2766   { "pmulhw",           { MX, EM } },
2767   { PREFIX_TABLE (PREFIX_0FE6) },
2768   { PREFIX_TABLE (PREFIX_0FE7) },
2769   /* e8 */
2770   { "psubsb",           { MX, EM } },
2771   { "psubsw",           { MX, EM } },
2772   { "pminsw",           { MX, EM } },
2773   { "por",              { MX, EM } },
2774   { "paddsb",           { MX, EM } },
2775   { "paddsw",           { MX, EM } },
2776   { "pmaxsw",           { MX, EM } },
2777   { "pxor",             { MX, EM } },
2778   /* f0 */
2779   { PREFIX_TABLE (PREFIX_0FF0) },
2780   { "psllw",            { MX, EM } },
2781   { "pslld",            { MX, EM } },
2782   { "psllq",            { MX, EM } },
2783   { "pmuludq",          { MX, EM } },
2784   { "pmaddwd",          { MX, EM } },
2785   { "psadbw",           { MX, EM } },
2786   { PREFIX_TABLE (PREFIX_0FF7) },
2787   /* f8 */
2788   { "psubb",            { MX, EM } },
2789   { "psubw",            { MX, EM } },
2790   { "psubd",            { MX, EM } },
2791   { "psubq",            { MX, EM } },
2792   { "paddb",            { MX, EM } },
2793   { "paddw",            { MX, EM } },
2794   { "paddd",            { MX, EM } },
2795   { Bad_Opcode },
2796 };
2797
2798 static const unsigned char onebyte_has_modrm[256] = {
2799   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2800   /*       -------------------------------        */
2801   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2802   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2803   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2804   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2805   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2806   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2807   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2808   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2809   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2810   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2811   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2812   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2813   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2814   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2815   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2816   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
2817   /*       -------------------------------        */
2818   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2819 };
2820
2821 static const unsigned char twobyte_has_modrm[256] = {
2822   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2823   /*       -------------------------------        */
2824   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2825   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2826   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2827   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2828   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2829   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2830   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2831   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2832   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2833   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2834   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2835   /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
2836   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2837   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2838   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2839   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0  /* ff */
2840   /*       -------------------------------        */
2841   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2842 };
2843
2844 static char obuf[100];
2845 static char *obufp;
2846 static char *mnemonicendp;
2847 static char scratchbuf[100];
2848 static unsigned char *start_codep;
2849 static unsigned char *insn_codep;
2850 static unsigned char *codep;
2851 static int last_lock_prefix;
2852 static int last_repz_prefix;
2853 static int last_repnz_prefix;
2854 static int last_data_prefix;
2855 static int last_addr_prefix;
2856 static int last_rex_prefix;
2857 static int last_seg_prefix;
2858 #define MAX_CODE_LENGTH 15
2859 /* We can up to 14 prefixes since the maximum instruction length is
2860    15bytes.  */
2861 static int all_prefixes[MAX_CODE_LENGTH - 1];
2862 static disassemble_info *the_info;
2863 static struct
2864   {
2865     int mod;
2866     int reg;
2867     int rm;
2868   }
2869 modrm;
2870 static unsigned char need_modrm;
2871 static struct
2872   {
2873     int scale;
2874     int index;
2875     int base;
2876   }
2877 sib;
2878 static struct
2879   {
2880     int register_specifier;
2881     int length;
2882     int prefix;
2883     int w;
2884     int evex;
2885     int r;
2886     int v;
2887     int mask_register_specifier;
2888     int zeroing;
2889     int ll;
2890     int b;
2891   }
2892 vex;
2893 static unsigned char need_vex;
2894 static unsigned char need_vex_reg;
2895 static unsigned char vex_w_done;
2896
2897 struct op
2898   {
2899     const char *name;
2900     unsigned int len;
2901   };
2902
2903 /* If we are accessing mod/rm/reg without need_modrm set, then the
2904    values are stale.  Hitting this abort likely indicates that you
2905    need to update onebyte_has_modrm or twobyte_has_modrm.  */
2906 #define MODRM_CHECK  if (!need_modrm) abort ()
2907
2908 static const char **names64;
2909 static const char **names32;
2910 static const char **names16;
2911 static const char **names8;
2912 static const char **names8rex;
2913 static const char **names_seg;
2914 static const char *index64;
2915 static const char *index32;
2916 static const char **index16;
2917 static const char **names_bnd;
2918
2919 static const char *intel_names64[] = {
2920   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2921   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2922 };
2923 static const char *intel_names32[] = {
2924   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
2925   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
2926 };
2927 static const char *intel_names16[] = {
2928   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
2929   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
2930 };
2931 static const char *intel_names8[] = {
2932   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2933 };
2934 static const char *intel_names8rex[] = {
2935   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2936   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2937 };
2938 static const char *intel_names_seg[] = {
2939   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2940 };
2941 static const char *intel_index64 = "riz";
2942 static const char *intel_index32 = "eiz";
2943 static const char *intel_index16[] = {
2944   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2945 };
2946
2947 static const char *att_names64[] = {
2948   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2949   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2950 };
2951 static const char *att_names32[] = {
2952   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2953   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2954 };
2955 static const char *att_names16[] = {
2956   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2957   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2958 };
2959 static const char *att_names8[] = {
2960   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2961 };
2962 static const char *att_names8rex[] = {
2963   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2964   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2965 };
2966 static const char *att_names_seg[] = {
2967   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2968 };
2969 static const char *att_index64 = "%riz";
2970 static const char *att_index32 = "%eiz";
2971 static const char *att_index16[] = {
2972   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2973 };
2974
2975 static const char **names_mm;
2976 static const char *intel_names_mm[] = {
2977   "mm0", "mm1", "mm2", "mm3",
2978   "mm4", "mm5", "mm6", "mm7"
2979 };
2980 static const char *att_names_mm[] = {
2981   "%mm0", "%mm1", "%mm2", "%mm3",
2982   "%mm4", "%mm5", "%mm6", "%mm7"
2983 };
2984
2985 static const char *intel_names_bnd[] = {
2986   "bnd0", "bnd1", "bnd2", "bnd3"
2987 };
2988
2989 static const char *att_names_bnd[] = {
2990   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
2991 };
2992
2993 static const char **names_xmm;
2994 static const char *intel_names_xmm[] = {
2995   "xmm0", "xmm1", "xmm2", "xmm3",
2996   "xmm4", "xmm5", "xmm6", "xmm7",
2997   "xmm8", "xmm9", "xmm10", "xmm11",
2998   "xmm12", "xmm13", "xmm14", "xmm15",
2999   "xmm16", "xmm17", "xmm18", "xmm19",
3000   "xmm20", "xmm21", "xmm22", "xmm23",
3001   "xmm24", "xmm25", "xmm26", "xmm27",
3002   "xmm28", "xmm29", "xmm30", "xmm31"
3003 };
3004 static const char *att_names_xmm[] = {
3005   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3006   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3007   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3008   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3009   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3010   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3011   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3012   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3013 };
3014
3015 static const char **names_ymm;
3016 static const char *intel_names_ymm[] = {
3017   "ymm0", "ymm1", "ymm2", "ymm3",
3018   "ymm4", "ymm5", "ymm6", "ymm7",
3019   "ymm8", "ymm9", "ymm10", "ymm11",
3020   "ymm12", "ymm13", "ymm14", "ymm15",
3021   "ymm16", "ymm17", "ymm18", "ymm19",
3022   "ymm20", "ymm21", "ymm22", "ymm23",
3023   "ymm24", "ymm25", "ymm26", "ymm27",
3024   "ymm28", "ymm29", "ymm30", "ymm31"
3025 };
3026 static const char *att_names_ymm[] = {
3027   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3028   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3029   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3030   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3031   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3032   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3033   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3034   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3035 };
3036
3037 static const char **names_zmm;
3038 static const char *intel_names_zmm[] = {
3039   "zmm0", "zmm1", "zmm2", "zmm3",
3040   "zmm4", "zmm5", "zmm6", "zmm7",
3041   "zmm8", "zmm9", "zmm10", "zmm11",
3042   "zmm12", "zmm13", "zmm14", "zmm15",
3043   "zmm16", "zmm17", "zmm18", "zmm19",
3044   "zmm20", "zmm21", "zmm22", "zmm23",
3045   "zmm24", "zmm25", "zmm26", "zmm27",
3046   "zmm28", "zmm29", "zmm30", "zmm31"
3047 };
3048 static const char *att_names_zmm[] = {
3049   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3050   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3051   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3052   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3053   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3054   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3055   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3056   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3057 };
3058
3059 static const char **names_mask;
3060 static const char *intel_names_mask[] = {
3061   "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3062 };
3063 static const char *att_names_mask[] = {
3064   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3065 };
3066
3067 static const char *names_rounding[] =
3068 {
3069   "{rn-sae}",
3070   "{rd-sae}",
3071   "{ru-sae}",
3072   "{rz-sae}"
3073 };
3074
3075 static const struct dis386 reg_table[][8] = {
3076   /* REG_80 */
3077   {
3078     { "addA",   { Ebh1, Ib } },
3079     { "orA",    { Ebh1, Ib } },
3080     { "adcA",   { Ebh1, Ib } },
3081     { "sbbA",   { Ebh1, Ib } },
3082     { "andA",   { Ebh1, Ib } },
3083     { "subA",   { Ebh1, Ib } },
3084     { "xorA",   { Ebh1, Ib } },
3085     { "cmpA",   { Eb, Ib } },
3086   },
3087   /* REG_81 */
3088   {
3089     { "addQ",   { Evh1, Iv } },
3090     { "orQ",    { Evh1, Iv } },
3091     { "adcQ",   { Evh1, Iv } },
3092     { "sbbQ",   { Evh1, Iv } },
3093     { "andQ",   { Evh1, Iv } },
3094     { "subQ",   { Evh1, Iv } },
3095     { "xorQ",   { Evh1, Iv } },
3096     { "cmpQ",   { Ev, Iv } },
3097   },
3098   /* REG_82 */
3099   {
3100     { "addQ",   { Evh1, sIb } },
3101     { "orQ",    { Evh1, sIb } },
3102     { "adcQ",   { Evh1, sIb } },
3103     { "sbbQ",   { Evh1, sIb } },
3104     { "andQ",   { Evh1, sIb } },
3105     { "subQ",   { Evh1, sIb } },
3106     { "xorQ",   { Evh1, sIb } },
3107     { "cmpQ",   { Ev, sIb } },
3108   },
3109   /* REG_8F */
3110   {
3111     { "popU",   { stackEv } },
3112     { XOP_8F_TABLE (XOP_09) },
3113     { Bad_Opcode },
3114     { Bad_Opcode },
3115     { Bad_Opcode },
3116     { XOP_8F_TABLE (XOP_09) },
3117   },
3118   /* REG_C0 */
3119   {
3120     { "rolA",   { Eb, Ib } },
3121     { "rorA",   { Eb, Ib } },
3122     { "rclA",   { Eb, Ib } },
3123     { "rcrA",   { Eb, Ib } },
3124     { "shlA",   { Eb, Ib } },
3125     { "shrA",   { Eb, Ib } },
3126     { Bad_Opcode },
3127     { "sarA",   { Eb, Ib } },
3128   },
3129   /* REG_C1 */
3130   {
3131     { "rolQ",   { Ev, Ib } },
3132     { "rorQ",   { Ev, Ib } },
3133     { "rclQ",   { Ev, Ib } },
3134     { "rcrQ",   { Ev, Ib } },
3135     { "shlQ",   { Ev, Ib } },
3136     { "shrQ",   { Ev, Ib } },
3137     { Bad_Opcode },
3138     { "sarQ",   { Ev, Ib } },
3139   },
3140   /* REG_C6 */
3141   {
3142     { "movA",   { Ebh3, Ib } },
3143     { Bad_Opcode },
3144     { Bad_Opcode },
3145     { Bad_Opcode },
3146     { Bad_Opcode },
3147     { Bad_Opcode },
3148     { Bad_Opcode },
3149     { MOD_TABLE (MOD_C6_REG_7) },
3150   },
3151   /* REG_C7 */
3152   {
3153     { "movQ",   { Evh3, Iv } },
3154     { Bad_Opcode },
3155     { Bad_Opcode },
3156     { Bad_Opcode },
3157     { Bad_Opcode },
3158     { Bad_Opcode },
3159     { Bad_Opcode },
3160     { MOD_TABLE (MOD_C7_REG_7) },
3161   },
3162   /* REG_D0 */
3163   {
3164     { "rolA",   { Eb, I1 } },
3165     { "rorA",   { Eb, I1 } },
3166     { "rclA",   { Eb, I1 } },
3167     { "rcrA",   { Eb, I1 } },
3168     { "shlA",   { Eb, I1 } },
3169     { "shrA",   { Eb, I1 } },
3170     { Bad_Opcode },
3171     { "sarA",   { Eb, I1 } },
3172   },
3173   /* REG_D1 */
3174   {
3175     { "rolQ",   { Ev, I1 } },
3176     { "rorQ",   { Ev, I1 } },
3177     { "rclQ",   { Ev, I1 } },
3178     { "rcrQ",   { Ev, I1 } },
3179     { "shlQ",   { Ev, I1 } },
3180     { "shrQ",   { Ev, I1 } },
3181     { Bad_Opcode },
3182     { "sarQ",   { Ev, I1 } },
3183   },
3184   /* REG_D2 */
3185   {
3186     { "rolA",   { Eb, CL } },
3187     { "rorA",   { Eb, CL } },
3188     { "rclA",   { Eb, CL } },
3189     { "rcrA",   { Eb, CL } },
3190     { "shlA",   { Eb, CL } },
3191     { "shrA",   { Eb, CL } },
3192     { Bad_Opcode },
3193     { "sarA",   { Eb, CL } },
3194   },
3195   /* REG_D3 */
3196   {
3197     { "rolQ",   { Ev, CL } },
3198     { "rorQ",   { Ev, CL } },
3199     { "rclQ",   { Ev, CL } },
3200     { "rcrQ",   { Ev, CL } },
3201     { "shlQ",   { Ev, CL } },
3202     { "shrQ",   { Ev, CL } },
3203     { Bad_Opcode },
3204     { "sarQ",   { Ev, CL } },
3205   },
3206   /* REG_F6 */
3207   {
3208     { "testA",  { Eb, Ib } },
3209     { Bad_Opcode },
3210     { "notA",   { Ebh1 } },
3211     { "negA",   { Ebh1 } },
3212     { "mulA",   { Eb } },       /* Don't print the implicit %al register,  */
3213     { "imulA",  { Eb } },       /* to distinguish these opcodes from other */
3214     { "divA",   { Eb } },       /* mul/imul opcodes.  Do the same for div  */
3215     { "idivA",  { Eb } },       /* and idiv for consistency.               */
3216   },
3217   /* REG_F7 */
3218   {
3219     { "testQ",  { Ev, Iv } },
3220     { Bad_Opcode },
3221     { "notQ",   { Evh1 } },
3222     { "negQ",   { Evh1 } },
3223     { "mulQ",   { Ev } },       /* Don't print the implicit register.  */
3224     { "imulQ",  { Ev } },
3225     { "divQ",   { Ev } },
3226     { "idivQ",  { Ev } },
3227   },
3228   /* REG_FE */
3229   {
3230     { "incA",   { Ebh1 } },
3231     { "decA",   { Ebh1 } },
3232   },
3233   /* REG_FF */
3234   {
3235     { "incQ",   { Evh1 } },
3236     { "decQ",   { Evh1 } },
3237     { "call{T|}", { indirEv, BND } },
3238     { MOD_TABLE (MOD_FF_REG_3) },
3239     { "jmp{T|}", { indirEv, BND } },
3240     { MOD_TABLE (MOD_FF_REG_5) },
3241     { "pushU",  { stackEv } },
3242     { Bad_Opcode },
3243   },
3244   /* REG_0F00 */
3245   {
3246     { "sldtD",  { Sv } },
3247     { "strD",   { Sv } },
3248     { "lldt",   { Ew } },
3249     { "ltr",    { Ew } },
3250     { "verr",   { Ew } },
3251     { "verw",   { Ew } },
3252     { Bad_Opcode },
3253     { Bad_Opcode },
3254   },
3255   /* REG_0F01 */
3256   {
3257     { MOD_TABLE (MOD_0F01_REG_0) },
3258     { MOD_TABLE (MOD_0F01_REG_1) },
3259     { MOD_TABLE (MOD_0F01_REG_2) },
3260     { MOD_TABLE (MOD_0F01_REG_3) },
3261     { "smswD",  { Sv } },
3262     { Bad_Opcode },
3263     { "lmsw",   { Ew } },
3264     { MOD_TABLE (MOD_0F01_REG_7) },
3265   },
3266   /* REG_0F0D */
3267   {
3268     { "prefetch",       { Mb } },
3269     { "prefetchw",      { Mb } },
3270     { "prefetchwt1",    { Mb } },
3271     { "prefetch",       { Mb } },
3272     { "prefetch",       { Mb } },
3273     { "prefetch",       { Mb } },
3274     { "prefetch",       { Mb } },
3275     { "prefetch",       { Mb } },
3276   },
3277   /* REG_0F18 */
3278   {
3279     { MOD_TABLE (MOD_0F18_REG_0) },
3280     { MOD_TABLE (MOD_0F18_REG_1) },
3281     { MOD_TABLE (MOD_0F18_REG_2) },
3282     { MOD_TABLE (MOD_0F18_REG_3) },
3283     { MOD_TABLE (MOD_0F18_REG_4) },
3284     { MOD_TABLE (MOD_0F18_REG_5) },
3285     { MOD_TABLE (MOD_0F18_REG_6) },
3286     { MOD_TABLE (MOD_0F18_REG_7) },
3287   },
3288   /* REG_0F71 */
3289   {
3290     { Bad_Opcode },
3291     { Bad_Opcode },
3292     { MOD_TABLE (MOD_0F71_REG_2) },
3293     { Bad_Opcode },
3294     { MOD_TABLE (MOD_0F71_REG_4) },
3295     { Bad_Opcode },
3296     { MOD_TABLE (MOD_0F71_REG_6) },
3297   },
3298   /* REG_0F72 */
3299   {
3300     { Bad_Opcode },
3301     { Bad_Opcode },
3302     { MOD_TABLE (MOD_0F72_REG_2) },
3303     { Bad_Opcode },
3304     { MOD_TABLE (MOD_0F72_REG_4) },
3305     { Bad_Opcode },
3306     { MOD_TABLE (MOD_0F72_REG_6) },
3307   },
3308   /* REG_0F73 */
3309   {
3310     { Bad_Opcode },
3311     { Bad_Opcode },
3312     { MOD_TABLE (MOD_0F73_REG_2) },
3313     { MOD_TABLE (MOD_0F73_REG_3) },
3314     { Bad_Opcode },
3315     { Bad_Opcode },
3316     { MOD_TABLE (MOD_0F73_REG_6) },
3317     { MOD_TABLE (MOD_0F73_REG_7) },
3318   },
3319   /* REG_0FA6 */
3320   {
3321     { "montmul",        { { OP_0f07, 0 } } },
3322     { "xsha1",          { { OP_0f07, 0 } } },
3323     { "xsha256",        { { OP_0f07, 0 } } },
3324   },
3325   /* REG_0FA7 */
3326   {
3327     { "xstore-rng",     { { OP_0f07, 0 } } },
3328     { "xcrypt-ecb",     { { OP_0f07, 0 } } },
3329     { "xcrypt-cbc",     { { OP_0f07, 0 } } },
3330     { "xcrypt-ctr",     { { OP_0f07, 0 } } },
3331     { "xcrypt-cfb",     { { OP_0f07, 0 } } },
3332     { "xcrypt-ofb",     { { OP_0f07, 0 } } },
3333   },
3334   /* REG_0FAE */
3335   {
3336     { MOD_TABLE (MOD_0FAE_REG_0) },
3337     { MOD_TABLE (MOD_0FAE_REG_1) },
3338     { MOD_TABLE (MOD_0FAE_REG_2) },
3339     { MOD_TABLE (MOD_0FAE_REG_3) },
3340     { MOD_TABLE (MOD_0FAE_REG_4) },
3341     { MOD_TABLE (MOD_0FAE_REG_5) },
3342     { MOD_TABLE (MOD_0FAE_REG_6) },
3343     { MOD_TABLE (MOD_0FAE_REG_7) },
3344   },
3345   /* REG_0FBA */
3346   {
3347     { Bad_Opcode },
3348     { Bad_Opcode },
3349     { Bad_Opcode },
3350     { Bad_Opcode },
3351     { "btQ",    { Ev, Ib } },
3352     { "btsQ",   { Evh1, Ib } },
3353     { "btrQ",   { Evh1, Ib } },
3354     { "btcQ",   { Evh1, Ib } },
3355   },
3356   /* REG_0FC7 */
3357   {
3358     { Bad_Opcode },
3359     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } },
3360     { Bad_Opcode },
3361     { MOD_TABLE (MOD_0FC7_REG_3) },
3362     { MOD_TABLE (MOD_0FC7_REG_4) },
3363     { MOD_TABLE (MOD_0FC7_REG_5) },
3364     { MOD_TABLE (MOD_0FC7_REG_6) },
3365     { MOD_TABLE (MOD_0FC7_REG_7) },
3366   },
3367   /* REG_VEX_0F71 */
3368   {
3369     { Bad_Opcode },
3370     { Bad_Opcode },
3371     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3372     { Bad_Opcode },
3373     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3374     { Bad_Opcode },
3375     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3376   },
3377   /* REG_VEX_0F72 */
3378   {
3379     { Bad_Opcode },
3380     { Bad_Opcode },
3381     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3382     { Bad_Opcode },
3383     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3384     { Bad_Opcode },
3385     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3386   },
3387   /* REG_VEX_0F73 */
3388   {
3389     { Bad_Opcode },
3390     { Bad_Opcode },
3391     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3392     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3393     { Bad_Opcode },
3394     { Bad_Opcode },
3395     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3396     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3397   },
3398   /* REG_VEX_0FAE */
3399   {
3400     { Bad_Opcode },
3401     { Bad_Opcode },
3402     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3403     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3404   },
3405   /* REG_VEX_0F38F3 */
3406   {
3407     { Bad_Opcode },
3408     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3409     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3410     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3411   },
3412   /* REG_XOP_LWPCB */
3413   {
3414     { "llwpcb", { { OP_LWPCB_E, 0 } } },
3415     { "slwpcb", { { OP_LWPCB_E, 0 } } },
3416   },
3417   /* REG_XOP_LWP */
3418   {
3419     { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq } },
3420     { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq } },
3421   },
3422   /* REG_XOP_TBM_01 */
3423   {
3424     { Bad_Opcode },
3425     { "blcfill",        { { OP_LWP_E, 0 }, Ev } },
3426     { "blsfill",        { { OP_LWP_E, 0 }, Ev } },
3427     { "blcs",   { { OP_LWP_E, 0 }, Ev } },
3428     { "tzmsk",  { { OP_LWP_E, 0 }, Ev } },
3429     { "blcic",  { { OP_LWP_E, 0 }, Ev } },
3430     { "blsic",  { { OP_LWP_E, 0 }, Ev } },
3431     { "t1mskc", { { OP_LWP_E, 0 }, Ev } },
3432   },
3433   /* REG_XOP_TBM_02 */
3434   {
3435     { Bad_Opcode },
3436     { "blcmsk", { { OP_LWP_E, 0 }, Ev } },
3437     { Bad_Opcode },
3438     { Bad_Opcode },
3439     { Bad_Opcode },
3440     { Bad_Opcode },
3441     { "blci",   { { OP_LWP_E, 0 }, Ev } },
3442   },
3443 #define NEED_REG_TABLE
3444 #include "i386-dis-evex.h"
3445 #undef NEED_REG_TABLE
3446 };
3447
3448 static const struct dis386 prefix_table[][4] = {
3449   /* PREFIX_90 */
3450   {
3451     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
3452     { "pause", { XX } },
3453     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
3454   },
3455
3456   /* PREFIX_0F10 */
3457   {
3458     { "movups", { XM, EXx } },
3459     { "movss",  { XM, EXd } },
3460     { "movupd", { XM, EXx } },
3461     { "movsd",  { XM, EXq } },
3462   },
3463
3464   /* PREFIX_0F11 */
3465   {
3466     { "movups", { EXxS, XM } },
3467     { "movss",  { EXdS, XM } },
3468     { "movupd", { EXxS, XM } },
3469     { "movsd",  { EXqS, XM } },
3470   },
3471
3472   /* PREFIX_0F12 */
3473   {
3474     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3475     { "movsldup", { XM, EXx } },
3476     { "movlpd", { XM, EXq } },
3477     { "movddup", { XM, EXq } },
3478   },
3479
3480   /* PREFIX_0F16 */
3481   {
3482     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3483     { "movshdup", { XM, EXx } },
3484     { "movhpd", { XM, EXq } },
3485   },
3486
3487   /* PREFIX_0F1A */
3488   {
3489     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3490     { "bndcl",  { Gbnd, Ev_bnd } },
3491     { "bndmov", { Gbnd, Ebnd } },
3492     { "bndcu",  { Gbnd, Ev_bnd } },
3493   },
3494
3495   /* PREFIX_0F1B */
3496   {
3497     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3498     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3499     { "bndmov", { Ebnd, Gbnd } },
3500     { "bndcn",  { Gbnd, Ev_bnd } },
3501   },
3502
3503   /* PREFIX_0F2A */
3504   {
3505     { "cvtpi2ps", { XM, EMCq } },
3506     { "cvtsi2ss%LQ", { XM, Ev } },
3507     { "cvtpi2pd", { XM, EMCq } },
3508     { "cvtsi2sd%LQ", { XM, Ev } },
3509   },
3510
3511   /* PREFIX_0F2B */
3512   {
3513     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3514     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3515     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3516     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3517   },
3518
3519   /* PREFIX_0F2C */
3520   {
3521     { "cvttps2pi", { MXC, EXq } },
3522     { "cvttss2siY", { Gv, EXd } },
3523     { "cvttpd2pi", { MXC, EXx } },
3524     { "cvttsd2siY", { Gv, EXq } },
3525   },
3526
3527   /* PREFIX_0F2D */
3528   {
3529     { "cvtps2pi", { MXC, EXq } },
3530     { "cvtss2siY", { Gv, EXd } },
3531     { "cvtpd2pi", { MXC, EXx } },
3532     { "cvtsd2siY", { Gv, EXq } },
3533   },
3534
3535   /* PREFIX_0F2E */
3536   {
3537     { "ucomiss",{ XM, EXd } },
3538     { Bad_Opcode },
3539     { "ucomisd",{ XM, EXq } },
3540   },
3541
3542   /* PREFIX_0F2F */
3543   {
3544     { "comiss", { XM, EXd } },
3545     { Bad_Opcode },
3546     { "comisd", { XM, EXq } },
3547   },
3548
3549   /* PREFIX_0F51 */
3550   {
3551     { "sqrtps", { XM, EXx } },
3552     { "sqrtss", { XM, EXd } },
3553     { "sqrtpd", { XM, EXx } },
3554     { "sqrtsd", { XM, EXq } },
3555   },
3556
3557   /* PREFIX_0F52 */
3558   {
3559     { "rsqrtps",{ XM, EXx } },
3560     { "rsqrtss",{ XM, EXd } },
3561   },
3562
3563   /* PREFIX_0F53 */
3564   {
3565     { "rcpps",  { XM, EXx } },
3566     { "rcpss",  { XM, EXd } },
3567   },
3568
3569   /* PREFIX_0F58 */
3570   {
3571     { "addps", { XM, EXx } },
3572     { "addss", { XM, EXd } },
3573     { "addpd", { XM, EXx } },
3574     { "addsd", { XM, EXq } },
3575   },
3576
3577   /* PREFIX_0F59 */
3578   {
3579     { "mulps",  { XM, EXx } },
3580     { "mulss",  { XM, EXd } },
3581     { "mulpd",  { XM, EXx } },
3582     { "mulsd",  { XM, EXq } },
3583   },
3584
3585   /* PREFIX_0F5A */
3586   {
3587     { "cvtps2pd", { XM, EXq } },
3588     { "cvtss2sd", { XM, EXd } },
3589     { "cvtpd2ps", { XM, EXx } },
3590     { "cvtsd2ss", { XM, EXq } },
3591   },
3592
3593   /* PREFIX_0F5B */
3594   {
3595     { "cvtdq2ps", { XM, EXx } },
3596     { "cvttps2dq", { XM, EXx } },
3597     { "cvtps2dq", { XM, EXx } },
3598   },
3599
3600   /* PREFIX_0F5C */
3601   {
3602     { "subps",  { XM, EXx } },
3603     { "subss",  { XM, EXd } },
3604     { "subpd",  { XM, EXx } },
3605     { "subsd",  { XM, EXq } },
3606   },
3607
3608   /* PREFIX_0F5D */
3609   {
3610     { "minps",  { XM, EXx } },
3611     { "minss",  { XM, EXd } },
3612     { "minpd",  { XM, EXx } },
3613     { "minsd",  { XM, EXq } },
3614   },
3615
3616   /* PREFIX_0F5E */
3617   {
3618     { "divps",  { XM, EXx } },
3619     { "divss",  { XM, EXd } },
3620     { "divpd",  { XM, EXx } },
3621     { "divsd",  { XM, EXq } },
3622   },
3623
3624   /* PREFIX_0F5F */
3625   {
3626     { "maxps",  { XM, EXx } },
3627     { "maxss",  { XM, EXd } },
3628     { "maxpd",  { XM, EXx } },
3629     { "maxsd",  { XM, EXq } },
3630   },
3631
3632   /* PREFIX_0F60 */
3633   {
3634     { "punpcklbw",{ MX, EMd } },
3635     { Bad_Opcode },
3636     { "punpcklbw",{ MX, EMx } },
3637   },
3638
3639   /* PREFIX_0F61 */
3640   {
3641     { "punpcklwd",{ MX, EMd } },
3642     { Bad_Opcode },
3643     { "punpcklwd",{ MX, EMx } },
3644   },
3645
3646   /* PREFIX_0F62 */
3647   {
3648     { "punpckldq",{ MX, EMd } },
3649     { Bad_Opcode },
3650     { "punpckldq",{ MX, EMx } },
3651   },
3652
3653   /* PREFIX_0F6C */
3654   {
3655     { Bad_Opcode },
3656     { Bad_Opcode },
3657     { "punpcklqdq", { XM, EXx } },
3658   },
3659
3660   /* PREFIX_0F6D */
3661   {
3662     { Bad_Opcode },
3663     { Bad_Opcode },
3664     { "punpckhqdq", { XM, EXx } },
3665   },
3666
3667   /* PREFIX_0F6F */
3668   {
3669     { "movq",   { MX, EM } },
3670     { "movdqu", { XM, EXx } },
3671     { "movdqa", { XM, EXx } },
3672   },
3673
3674   /* PREFIX_0F70 */
3675   {
3676     { "pshufw", { MX, EM, Ib } },
3677     { "pshufhw",{ XM, EXx, Ib } },
3678     { "pshufd", { XM, EXx, Ib } },
3679     { "pshuflw",{ XM, EXx, Ib } },
3680   },
3681
3682   /* PREFIX_0F73_REG_3 */
3683   {
3684     { Bad_Opcode },
3685     { Bad_Opcode },
3686     { "psrldq", { XS, Ib } },
3687   },
3688
3689   /* PREFIX_0F73_REG_7 */
3690   {
3691     { Bad_Opcode },
3692     { Bad_Opcode },
3693     { "pslldq", { XS, Ib } },
3694   },
3695
3696   /* PREFIX_0F78 */
3697   {
3698     {"vmread",  { Em, Gm } },
3699     { Bad_Opcode },
3700     {"extrq",   { XS, Ib, Ib } },
3701     {"insertq", { XM, XS, Ib, Ib } },
3702   },
3703
3704   /* PREFIX_0F79 */
3705   {
3706     {"vmwrite", { Gm, Em } },
3707     { Bad_Opcode },
3708     {"extrq",   { XM, XS } },
3709     {"insertq", { XM, XS } },
3710   },
3711
3712   /* PREFIX_0F7C */
3713   {
3714     { Bad_Opcode },
3715     { Bad_Opcode },
3716     { "haddpd", { XM, EXx } },
3717     { "haddps", { XM, EXx } },
3718   },
3719
3720   /* PREFIX_0F7D */
3721   {
3722     { Bad_Opcode },
3723     { Bad_Opcode },
3724     { "hsubpd", { XM, EXx } },
3725     { "hsubps", { XM, EXx } },
3726   },
3727
3728   /* PREFIX_0F7E */
3729   {
3730     { "movK",   { Edq, MX } },
3731     { "movq",   { XM, EXq } },
3732     { "movK",   { Edq, XM } },
3733   },
3734
3735   /* PREFIX_0F7F */
3736   {
3737     { "movq",   { EMS, MX } },
3738     { "movdqu", { EXxS, XM } },
3739     { "movdqa", { EXxS, XM } },
3740   },
3741
3742   /* PREFIX_0FAE_REG_0 */
3743   {
3744     { Bad_Opcode },
3745     { "rdfsbase", { Ev } },
3746   },
3747
3748   /* PREFIX_0FAE_REG_1 */
3749   {
3750     { Bad_Opcode },
3751     { "rdgsbase", { Ev } },
3752   },
3753
3754   /* PREFIX_0FAE_REG_2 */
3755   {
3756     { Bad_Opcode },
3757     { "wrfsbase", { Ev } },
3758   },
3759
3760   /* PREFIX_0FAE_REG_3 */
3761   {
3762     { Bad_Opcode },
3763     { "wrgsbase", { Ev } },
3764   },
3765
3766   /* PREFIX_0FAE_REG_7 */
3767   {
3768     { "clflush",        { Mb } },
3769     { Bad_Opcode },
3770     { "clflushopt",     { Mb } },
3771   },
3772
3773   /* PREFIX_0FB8 */
3774   {
3775     { Bad_Opcode },
3776     { "popcntS", { Gv, Ev } },
3777   },
3778
3779   /* PREFIX_0FBC */
3780   {
3781     { "bsfS",   { Gv, Ev } },
3782     { "tzcntS", { Gv, Ev } },
3783     { "bsfS",   { Gv, Ev } },
3784   },
3785
3786   /* PREFIX_0FBD */
3787   {
3788     { "bsrS",   { Gv, Ev } },
3789     { "lzcntS", { Gv, Ev } },
3790     { "bsrS",   { Gv, Ev } },
3791   },
3792
3793   /* PREFIX_0FC2 */
3794   {
3795     { "cmpps",  { XM, EXx, CMP } },
3796     { "cmpss",  { XM, EXd, CMP } },
3797     { "cmppd",  { XM, EXx, CMP } },
3798     { "cmpsd",  { XM, EXq, CMP } },
3799   },
3800
3801   /* PREFIX_0FC3 */
3802   {
3803     { "movntiS", { Ma, Gv } },
3804   },
3805
3806   /* PREFIX_0FC7_REG_6 */
3807   {
3808     { "vmptrld",{ Mq } },
3809     { "vmxon",  { Mq } },
3810     { "vmclear",{ Mq } },
3811   },
3812
3813   /* PREFIX_0FD0 */
3814   {
3815     { Bad_Opcode },
3816     { Bad_Opcode },
3817     { "addsubpd", { XM, EXx } },
3818     { "addsubps", { XM, EXx } },
3819   },
3820
3821   /* PREFIX_0FD6 */
3822   {
3823     { Bad_Opcode },
3824     { "movq2dq",{ XM, MS } },
3825     { "movq",   { EXqS, XM } },
3826     { "movdq2q",{ MX, XS } },
3827   },
3828
3829   /* PREFIX_0FE6 */
3830   {
3831     { Bad_Opcode },
3832     { "cvtdq2pd", { XM, EXq } },
3833     { "cvttpd2dq", { XM, EXx } },
3834     { "cvtpd2dq", { XM, EXx } },
3835   },
3836
3837   /* PREFIX_0FE7 */
3838   {
3839     { "movntq", { Mq, MX } },
3840     { Bad_Opcode },
3841     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
3842   },
3843
3844   /* PREFIX_0FF0 */
3845   {
3846     { Bad_Opcode },
3847     { Bad_Opcode },
3848     { Bad_Opcode },
3849     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
3850   },
3851
3852   /* PREFIX_0FF7 */
3853   {
3854     { "maskmovq", { MX, MS } },
3855     { Bad_Opcode },
3856     { "maskmovdqu", { XM, XS } },
3857   },
3858
3859   /* PREFIX_0F3810 */
3860   {
3861     { Bad_Opcode },
3862     { Bad_Opcode },
3863     { "pblendvb", { XM, EXx, XMM0 } },
3864   },
3865
3866   /* PREFIX_0F3814 */
3867   {
3868     { Bad_Opcode },
3869     { Bad_Opcode },
3870     { "blendvps", { XM, EXx, XMM0 } },
3871   },
3872
3873   /* PREFIX_0F3815 */
3874   {
3875     { Bad_Opcode },
3876     { Bad_Opcode },
3877     { "blendvpd", { XM, EXx, XMM0 } },
3878   },
3879
3880   /* PREFIX_0F3817 */
3881   {
3882     { Bad_Opcode },
3883     { Bad_Opcode },
3884     { "ptest",  { XM, EXx } },
3885   },
3886
3887   /* PREFIX_0F3820 */
3888   {
3889     { Bad_Opcode },
3890     { Bad_Opcode },
3891     { "pmovsxbw", { XM, EXq } },
3892   },
3893
3894   /* PREFIX_0F3821 */
3895   {
3896     { Bad_Opcode },
3897     { Bad_Opcode },
3898     { "pmovsxbd", { XM, EXd } },
3899   },
3900
3901   /* PREFIX_0F3822 */
3902   {
3903     { Bad_Opcode },
3904     { Bad_Opcode },
3905     { "pmovsxbq", { XM, EXw } },
3906   },
3907
3908   /* PREFIX_0F3823 */
3909   {
3910     { Bad_Opcode },
3911     { Bad_Opcode },
3912     { "pmovsxwd", { XM, EXq } },
3913   },
3914
3915   /* PREFIX_0F3824 */
3916   {
3917     { Bad_Opcode },
3918     { Bad_Opcode },
3919     { "pmovsxwq", { XM, EXd } },
3920   },
3921
3922   /* PREFIX_0F3825 */
3923   {
3924     { Bad_Opcode },
3925     { Bad_Opcode },
3926     { "pmovsxdq", { XM, EXq } },
3927   },
3928
3929   /* PREFIX_0F3828 */
3930   {
3931     { Bad_Opcode },
3932     { Bad_Opcode },
3933     { "pmuldq", { XM, EXx } },
3934   },
3935
3936   /* PREFIX_0F3829 */
3937   {
3938     { Bad_Opcode },
3939     { Bad_Opcode },
3940     { "pcmpeqq", { XM, EXx } },
3941   },
3942
3943   /* PREFIX_0F382A */
3944   {
3945     { Bad_Opcode },
3946     { Bad_Opcode },
3947     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
3948   },
3949
3950   /* PREFIX_0F382B */
3951   {
3952     { Bad_Opcode },
3953     { Bad_Opcode },
3954     { "packusdw", { XM, EXx } },
3955   },
3956
3957   /* PREFIX_0F3830 */
3958   {
3959     { Bad_Opcode },
3960     { Bad_Opcode },
3961     { "pmovzxbw", { XM, EXq } },
3962   },
3963
3964   /* PREFIX_0F3831 */
3965   {
3966     { Bad_Opcode },
3967     { Bad_Opcode },
3968     { "pmovzxbd", { XM, EXd } },
3969   },
3970
3971   /* PREFIX_0F3832 */
3972   {
3973     { Bad_Opcode },
3974     { Bad_Opcode },
3975     { "pmovzxbq", { XM, EXw } },
3976   },
3977
3978   /* PREFIX_0F3833 */
3979   {
3980     { Bad_Opcode },
3981     { Bad_Opcode },
3982     { "pmovzxwd", { XM, EXq } },
3983   },
3984
3985   /* PREFIX_0F3834 */
3986   {
3987     { Bad_Opcode },
3988     { Bad_Opcode },
3989     { "pmovzxwq", { XM, EXd } },
3990   },
3991
3992   /* PREFIX_0F3835 */
3993   {
3994     { Bad_Opcode },
3995     { Bad_Opcode },
3996     { "pmovzxdq", { XM, EXq } },
3997   },
3998
3999   /* PREFIX_0F3837 */
4000   {
4001     { Bad_Opcode },
4002     { Bad_Opcode },
4003     { "pcmpgtq", { XM, EXx } },
4004   },
4005
4006   /* PREFIX_0F3838 */
4007   {
4008     { Bad_Opcode },
4009     { Bad_Opcode },
4010     { "pminsb", { XM, EXx } },
4011   },
4012
4013   /* PREFIX_0F3839 */
4014   {
4015     { Bad_Opcode },
4016     { Bad_Opcode },
4017     { "pminsd", { XM, EXx } },
4018   },
4019
4020   /* PREFIX_0F383A */
4021   {
4022     { Bad_Opcode },
4023     { Bad_Opcode },
4024     { "pminuw", { XM, EXx } },
4025   },
4026
4027   /* PREFIX_0F383B */
4028   {
4029     { Bad_Opcode },
4030     { Bad_Opcode },
4031     { "pminud", { XM, EXx } },
4032   },
4033
4034   /* PREFIX_0F383C */
4035   {
4036     { Bad_Opcode },
4037     { Bad_Opcode },
4038     { "pmaxsb", { XM, EXx } },
4039   },
4040
4041   /* PREFIX_0F383D */
4042   {
4043     { Bad_Opcode },
4044     { Bad_Opcode },
4045     { "pmaxsd", { XM, EXx } },
4046   },
4047
4048   /* PREFIX_0F383E */
4049   {
4050     { Bad_Opcode },
4051     { Bad_Opcode },
4052     { "pmaxuw", { XM, EXx } },
4053   },
4054
4055   /* PREFIX_0F383F */
4056   {
4057     { Bad_Opcode },
4058     { Bad_Opcode },
4059     { "pmaxud", { XM, EXx } },
4060   },
4061
4062   /* PREFIX_0F3840 */
4063   {
4064     { Bad_Opcode },
4065     { Bad_Opcode },
4066     { "pmulld", { XM, EXx } },
4067   },
4068
4069   /* PREFIX_0F3841 */
4070   {
4071     { Bad_Opcode },
4072     { Bad_Opcode },
4073     { "phminposuw", { XM, EXx } },
4074   },
4075
4076   /* PREFIX_0F3880 */
4077   {
4078     { Bad_Opcode },
4079     { Bad_Opcode },
4080     { "invept", { Gm, Mo } },
4081   },
4082
4083   /* PREFIX_0F3881 */
4084   {
4085     { Bad_Opcode },
4086     { Bad_Opcode },
4087     { "invvpid", { Gm, Mo } },
4088   },
4089
4090   /* PREFIX_0F3882 */
4091   {
4092     { Bad_Opcode },
4093     { Bad_Opcode },
4094     { "invpcid", { Gm, M } },
4095   },
4096
4097   /* PREFIX_0F38C8 */
4098   {
4099     { "sha1nexte", { XM, EXxmm } },
4100   },
4101
4102   /* PREFIX_0F38C9 */
4103   {
4104     { "sha1msg1", { XM, EXxmm } },
4105   },
4106
4107   /* PREFIX_0F38CA */
4108   {
4109     { "sha1msg2", { XM, EXxmm } },
4110   },
4111
4112   /* PREFIX_0F38CB */
4113   {
4114     { "sha256rnds2", { XM, EXxmm, XMM0 } },
4115   },
4116
4117   /* PREFIX_0F38CC */
4118   {
4119     { "sha256msg1", { XM, EXxmm } },
4120   },
4121
4122   /* PREFIX_0F38CD */
4123   {
4124     { "sha256msg2", { XM, EXxmm } },
4125   },
4126
4127   /* PREFIX_0F38DB */
4128   {
4129     { Bad_Opcode },
4130     { Bad_Opcode },
4131     { "aesimc", { XM, EXx } },
4132   },
4133
4134   /* PREFIX_0F38DC */
4135   {
4136     { Bad_Opcode },
4137     { Bad_Opcode },
4138     { "aesenc", { XM, EXx } },
4139   },
4140
4141   /* PREFIX_0F38DD */
4142   {
4143     { Bad_Opcode },
4144     { Bad_Opcode },
4145     { "aesenclast", { XM, EXx } },
4146   },
4147
4148   /* PREFIX_0F38DE */
4149   {
4150     { Bad_Opcode },
4151     { Bad_Opcode },
4152     { "aesdec", { XM, EXx } },
4153   },
4154
4155   /* PREFIX_0F38DF */
4156   {
4157     { Bad_Opcode },
4158     { Bad_Opcode },
4159     { "aesdeclast", { XM, EXx } },
4160   },
4161
4162   /* PREFIX_0F38F0 */
4163   {
4164     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
4165     { Bad_Opcode },
4166     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
4167     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } } },
4168   },
4169
4170   /* PREFIX_0F38F1 */
4171   {
4172     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
4173     { Bad_Opcode },
4174     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
4175     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } } },
4176   },
4177
4178   /* PREFIX_0F38F6 */
4179   {
4180     { Bad_Opcode },
4181     { "adoxS",  { Gdq, Edq} },
4182     { "adcxS",  { Gdq, Edq} },
4183     { Bad_Opcode },
4184   },
4185
4186   /* PREFIX_0F3A08 */
4187   {
4188     { Bad_Opcode },
4189     { Bad_Opcode },
4190     { "roundps", { XM, EXx, Ib } },
4191   },
4192
4193   /* PREFIX_0F3A09 */
4194   {
4195     { Bad_Opcode },
4196     { Bad_Opcode },
4197     { "roundpd", { XM, EXx, Ib } },
4198   },
4199
4200   /* PREFIX_0F3A0A */
4201   {
4202     { Bad_Opcode },
4203     { Bad_Opcode },
4204     { "roundss", { XM, EXd, Ib } },
4205   },
4206
4207   /* PREFIX_0F3A0B */
4208   {
4209     { Bad_Opcode },
4210     { Bad_Opcode },
4211     { "roundsd", { XM, EXq, Ib } },
4212   },
4213
4214   /* PREFIX_0F3A0C */
4215   {
4216     { Bad_Opcode },
4217     { Bad_Opcode },
4218     { "blendps", { XM, EXx, Ib } },
4219   },
4220
4221   /* PREFIX_0F3A0D */
4222   {
4223     { Bad_Opcode },
4224     { Bad_Opcode },
4225     { "blendpd", { XM, EXx, Ib } },
4226   },
4227
4228   /* PREFIX_0F3A0E */
4229   {
4230     { Bad_Opcode },
4231     { Bad_Opcode },
4232     { "pblendw", { XM, EXx, Ib } },
4233   },
4234
4235   /* PREFIX_0F3A14 */
4236   {
4237     { Bad_Opcode },
4238     { Bad_Opcode },
4239     { "pextrb", { Edqb, XM, Ib } },
4240   },
4241
4242   /* PREFIX_0F3A15 */
4243   {
4244     { Bad_Opcode },
4245     { Bad_Opcode },
4246     { "pextrw", { Edqw, XM, Ib } },
4247   },
4248
4249   /* PREFIX_0F3A16 */
4250   {
4251     { Bad_Opcode },
4252     { Bad_Opcode },
4253     { "pextrK", { Edq, XM, Ib } },
4254   },
4255
4256   /* PREFIX_0F3A17 */
4257   {
4258     { Bad_Opcode },
4259     { Bad_Opcode },
4260     { "extractps", { Edqd, XM, Ib } },
4261   },
4262
4263   /* PREFIX_0F3A20 */
4264   {
4265     { Bad_Opcode },
4266     { Bad_Opcode },
4267     { "pinsrb", { XM, Edqb, Ib } },
4268   },
4269
4270   /* PREFIX_0F3A21 */
4271   {
4272     { Bad_Opcode },
4273     { Bad_Opcode },
4274     { "insertps", { XM, EXd, Ib } },
4275   },
4276
4277   /* PREFIX_0F3A22 */
4278   {
4279     { Bad_Opcode },
4280     { Bad_Opcode },
4281     { "pinsrK", { XM, Edq, Ib } },
4282   },
4283
4284   /* PREFIX_0F3A40 */
4285   {
4286     { Bad_Opcode },
4287     { Bad_Opcode },
4288     { "dpps",   { XM, EXx, Ib } },
4289   },
4290
4291   /* PREFIX_0F3A41 */
4292   {
4293     { Bad_Opcode },
4294     { Bad_Opcode },
4295     { "dppd",   { XM, EXx, Ib } },
4296   },
4297
4298   /* PREFIX_0F3A42 */
4299   {
4300     { Bad_Opcode },
4301     { Bad_Opcode },
4302     { "mpsadbw", { XM, EXx, Ib } },
4303   },
4304
4305   /* PREFIX_0F3A44 */
4306   {
4307     { Bad_Opcode },
4308     { Bad_Opcode },
4309     { "pclmulqdq", { XM, EXx, PCLMUL } },
4310   },
4311
4312   /* PREFIX_0F3A60 */
4313   {
4314     { Bad_Opcode },
4315     { Bad_Opcode },
4316     { "pcmpestrm", { XM, EXx, Ib } },
4317   },
4318
4319   /* PREFIX_0F3A61 */
4320   {
4321     { Bad_Opcode },
4322     { Bad_Opcode },
4323     { "pcmpestri", { XM, EXx, Ib } },
4324   },
4325
4326   /* PREFIX_0F3A62 */
4327   {
4328     { Bad_Opcode },
4329     { Bad_Opcode },
4330     { "pcmpistrm", { XM, EXx, Ib } },
4331   },
4332
4333   /* PREFIX_0F3A63 */
4334   {
4335     { Bad_Opcode },
4336     { Bad_Opcode },
4337     { "pcmpistri", { XM, EXx, Ib } },
4338   },
4339
4340   /* PREFIX_0F3ACC */
4341   {
4342     { "sha1rnds4", { XM, EXxmm, Ib } },
4343   },
4344
4345   /* PREFIX_0F3ADF */
4346   {
4347     { Bad_Opcode },
4348     { Bad_Opcode },
4349     { "aeskeygenassist", { XM, EXx, Ib } },
4350   },
4351
4352   /* PREFIX_VEX_0F10 */
4353   {
4354     { VEX_W_TABLE (VEX_W_0F10_P_0) },
4355     { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) },
4356     { VEX_W_TABLE (VEX_W_0F10_P_2) },
4357     { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) },
4358   },
4359
4360   /* PREFIX_VEX_0F11 */
4361   {
4362     { VEX_W_TABLE (VEX_W_0F11_P_0) },
4363     { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) },
4364     { VEX_W_TABLE (VEX_W_0F11_P_2) },
4365     { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) },
4366   },
4367
4368   /* PREFIX_VEX_0F12 */
4369   {
4370     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4371     { VEX_W_TABLE (VEX_W_0F12_P_1) },
4372     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
4373     { VEX_W_TABLE (VEX_W_0F12_P_3) },
4374   },
4375
4376   /* PREFIX_VEX_0F16 */
4377   {
4378     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4379     { VEX_W_TABLE (VEX_W_0F16_P_1) },
4380     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
4381   },
4382
4383   /* PREFIX_VEX_0F2A */
4384   {
4385     { Bad_Opcode },
4386     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) },
4387     { Bad_Opcode },
4388     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) },
4389   },
4390
4391   /* PREFIX_VEX_0F2C */
4392   {
4393     { Bad_Opcode },
4394     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) },
4395     { Bad_Opcode },
4396     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) },
4397   },
4398
4399   /* PREFIX_VEX_0F2D */
4400   {
4401     { Bad_Opcode },
4402     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) },
4403     { Bad_Opcode },
4404     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) },
4405   },
4406
4407   /* PREFIX_VEX_0F2E */
4408   {
4409     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) },
4410     { Bad_Opcode },
4411     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) },
4412   },
4413
4414   /* PREFIX_VEX_0F2F */
4415   {
4416     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) },
4417     { Bad_Opcode },
4418     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) },
4419   },
4420
4421   /* PREFIX_VEX_0F41 */
4422   {
4423     { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4424   },
4425
4426   /* PREFIX_VEX_0F42 */
4427   {
4428     { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4429   },
4430
4431   /* PREFIX_VEX_0F44 */
4432   {
4433     { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4434   },
4435
4436   /* PREFIX_VEX_0F45 */
4437   {
4438     { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4439   },
4440
4441   /* PREFIX_VEX_0F46 */
4442   {
4443     { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4444   },
4445
4446   /* PREFIX_VEX_0F47 */
4447   {
4448     { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4449   },
4450
4451   /* PREFIX_VEX_0F4B */
4452   {
4453     { Bad_Opcode },
4454     { Bad_Opcode },
4455     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4456   },
4457
4458   /* PREFIX_VEX_0F51 */
4459   {
4460     { VEX_W_TABLE (VEX_W_0F51_P_0) },
4461     { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) },
4462     { VEX_W_TABLE (VEX_W_0F51_P_2) },
4463     { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) },
4464   },
4465
4466   /* PREFIX_VEX_0F52 */
4467   {
4468     { VEX_W_TABLE (VEX_W_0F52_P_0) },
4469     { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) },
4470   },
4471
4472   /* PREFIX_VEX_0F53 */
4473   {
4474     { VEX_W_TABLE (VEX_W_0F53_P_0) },
4475     { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) },
4476   },
4477
4478   /* PREFIX_VEX_0F58 */
4479   {
4480     { VEX_W_TABLE (VEX_W_0F58_P_0) },
4481     { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) },
4482     { VEX_W_TABLE (VEX_W_0F58_P_2) },
4483     { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) },
4484   },
4485
4486   /* PREFIX_VEX_0F59 */
4487   {
4488     { VEX_W_TABLE (VEX_W_0F59_P_0) },
4489     { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) },
4490     { VEX_W_TABLE (VEX_W_0F59_P_2) },
4491     { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) },
4492   },
4493
4494   /* PREFIX_VEX_0F5A */
4495   {
4496     { VEX_W_TABLE (VEX_W_0F5A_P_0) },
4497     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) },
4498     { "vcvtpd2ps%XY", { XMM, EXx } },
4499     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) },
4500   },
4501
4502   /* PREFIX_VEX_0F5B */
4503   {
4504     { VEX_W_TABLE (VEX_W_0F5B_P_0) },
4505     { VEX_W_TABLE (VEX_W_0F5B_P_1) },
4506     { VEX_W_TABLE (VEX_W_0F5B_P_2) },
4507   },
4508
4509   /* PREFIX_VEX_0F5C */
4510   {
4511     { VEX_W_TABLE (VEX_W_0F5C_P_0) },
4512     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) },
4513     { VEX_W_TABLE (VEX_W_0F5C_P_2) },
4514     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) },
4515   },
4516
4517   /* PREFIX_VEX_0F5D */
4518   {
4519     { VEX_W_TABLE (VEX_W_0F5D_P_0) },
4520     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) },
4521     { VEX_W_TABLE (VEX_W_0F5D_P_2) },
4522     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) },
4523   },
4524
4525   /* PREFIX_VEX_0F5E */
4526   {
4527     { VEX_W_TABLE (VEX_W_0F5E_P_0) },
4528     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) },
4529     { VEX_W_TABLE (VEX_W_0F5E_P_2) },
4530     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) },
4531   },
4532
4533   /* PREFIX_VEX_0F5F */
4534   {
4535     { VEX_W_TABLE (VEX_W_0F5F_P_0) },
4536     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) },
4537     { VEX_W_TABLE (VEX_W_0F5F_P_2) },
4538     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) },
4539   },
4540
4541   /* PREFIX_VEX_0F60 */
4542   {
4543     { Bad_Opcode },
4544     { Bad_Opcode },
4545     { VEX_W_TABLE (VEX_W_0F60_P_2) },
4546   },
4547
4548   /* PREFIX_VEX_0F61 */
4549   {
4550     { Bad_Opcode },
4551     { Bad_Opcode },
4552     { VEX_W_TABLE (VEX_W_0F61_P_2) },
4553   },
4554
4555   /* PREFIX_VEX_0F62 */
4556   {
4557     { Bad_Opcode },
4558     { Bad_Opcode },
4559     { VEX_W_TABLE (VEX_W_0F62_P_2) },
4560   },
4561
4562   /* PREFIX_VEX_0F63 */
4563   {
4564     { Bad_Opcode },
4565     { Bad_Opcode },
4566     { VEX_W_TABLE (VEX_W_0F63_P_2) },
4567   },
4568
4569   /* PREFIX_VEX_0F64 */
4570   {
4571     { Bad_Opcode },
4572     { Bad_Opcode },
4573     { VEX_W_TABLE (VEX_W_0F64_P_2) },
4574   },
4575
4576   /* PREFIX_VEX_0F65 */
4577   {
4578     { Bad_Opcode },
4579     { Bad_Opcode },
4580     { VEX_W_TABLE (VEX_W_0F65_P_2) },
4581   },
4582
4583   /* PREFIX_VEX_0F66 */
4584   {
4585     { Bad_Opcode },
4586     { Bad_Opcode },
4587     { VEX_W_TABLE (VEX_W_0F66_P_2) },
4588   },
4589
4590   /* PREFIX_VEX_0F67 */
4591   {
4592     { Bad_Opcode },
4593     { Bad_Opcode },
4594     { VEX_W_TABLE (VEX_W_0F67_P_2) },
4595   },
4596
4597   /* PREFIX_VEX_0F68 */
4598   {
4599     { Bad_Opcode },
4600     { Bad_Opcode },
4601     { VEX_W_TABLE (VEX_W_0F68_P_2) },
4602   },
4603
4604   /* PREFIX_VEX_0F69 */
4605   {
4606     { Bad_Opcode },
4607     { Bad_Opcode },
4608     { VEX_W_TABLE (VEX_W_0F69_P_2) },
4609   },
4610
4611   /* PREFIX_VEX_0F6A */
4612   {
4613     { Bad_Opcode },
4614     { Bad_Opcode },
4615     { VEX_W_TABLE (VEX_W_0F6A_P_2) },
4616   },
4617
4618   /* PREFIX_VEX_0F6B */
4619   {
4620     { Bad_Opcode },
4621     { Bad_Opcode },
4622     { VEX_W_TABLE (VEX_W_0F6B_P_2) },
4623   },
4624
4625   /* PREFIX_VEX_0F6C */
4626   {
4627     { Bad_Opcode },
4628     { Bad_Opcode },
4629     { VEX_W_TABLE (VEX_W_0F6C_P_2) },
4630   },
4631
4632   /* PREFIX_VEX_0F6D */
4633   {
4634     { Bad_Opcode },
4635     { Bad_Opcode },
4636     { VEX_W_TABLE (VEX_W_0F6D_P_2) },
4637   },
4638
4639   /* PREFIX_VEX_0F6E */
4640   {
4641     { Bad_Opcode },
4642     { Bad_Opcode },
4643     { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
4644   },
4645
4646   /* PREFIX_VEX_0F6F */
4647   {
4648     { Bad_Opcode },
4649     { VEX_W_TABLE (VEX_W_0F6F_P_1) },
4650     { VEX_W_TABLE (VEX_W_0F6F_P_2) },
4651   },
4652
4653   /* PREFIX_VEX_0F70 */
4654   {
4655     { Bad_Opcode },
4656     { VEX_W_TABLE (VEX_W_0F70_P_1) },
4657     { VEX_W_TABLE (VEX_W_0F70_P_2) },
4658     { VEX_W_TABLE (VEX_W_0F70_P_3) },
4659   },
4660
4661   /* PREFIX_VEX_0F71_REG_2 */
4662   {
4663     { Bad_Opcode },
4664     { Bad_Opcode },
4665     { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) },
4666   },
4667
4668   /* PREFIX_VEX_0F71_REG_4 */
4669   {
4670     { Bad_Opcode },
4671     { Bad_Opcode },
4672     { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) },
4673   },
4674
4675   /* PREFIX_VEX_0F71_REG_6 */
4676   {
4677     { Bad_Opcode },
4678     { Bad_Opcode },
4679     { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) },
4680   },
4681
4682   /* PREFIX_VEX_0F72_REG_2 */
4683   {
4684     { Bad_Opcode },
4685     { Bad_Opcode },
4686     { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) },
4687   },
4688
4689   /* PREFIX_VEX_0F72_REG_4 */
4690   {
4691     { Bad_Opcode },
4692     { Bad_Opcode },
4693     { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) },
4694   },
4695
4696   /* PREFIX_VEX_0F72_REG_6 */
4697   {
4698     { Bad_Opcode },
4699     { Bad_Opcode },
4700     { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) },
4701   },
4702
4703   /* PREFIX_VEX_0F73_REG_2 */
4704   {
4705     { Bad_Opcode },
4706     { Bad_Opcode },
4707     { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) },
4708   },
4709
4710   /* PREFIX_VEX_0F73_REG_3 */
4711   {
4712     { Bad_Opcode },
4713     { Bad_Opcode },
4714     { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) },
4715   },
4716
4717   /* PREFIX_VEX_0F73_REG_6 */
4718   {
4719     { Bad_Opcode },
4720     { Bad_Opcode },
4721     { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) },
4722   },
4723
4724   /* PREFIX_VEX_0F73_REG_7 */
4725   {
4726     { Bad_Opcode },
4727     { Bad_Opcode },
4728     { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) },
4729   },
4730
4731   /* PREFIX_VEX_0F74 */
4732   {
4733     { Bad_Opcode },
4734     { Bad_Opcode },
4735     { VEX_W_TABLE (VEX_W_0F74_P_2) },
4736   },
4737
4738   /* PREFIX_VEX_0F75 */
4739   {
4740     { Bad_Opcode },
4741     { Bad_Opcode },
4742     { VEX_W_TABLE (VEX_W_0F75_P_2) },
4743   },
4744
4745   /* PREFIX_VEX_0F76 */
4746   {
4747     { Bad_Opcode },
4748     { Bad_Opcode },
4749     { VEX_W_TABLE (VEX_W_0F76_P_2) },
4750   },
4751
4752   /* PREFIX_VEX_0F77 */
4753   {
4754     { VEX_W_TABLE (VEX_W_0F77_P_0) },
4755   },
4756
4757   /* PREFIX_VEX_0F7C */
4758   {
4759     { Bad_Opcode },
4760     { Bad_Opcode },
4761     { VEX_W_TABLE (VEX_W_0F7C_P_2) },
4762     { VEX_W_TABLE (VEX_W_0F7C_P_3) },
4763   },
4764
4765   /* PREFIX_VEX_0F7D */
4766   {
4767     { Bad_Opcode },
4768     { Bad_Opcode },
4769     { VEX_W_TABLE (VEX_W_0F7D_P_2) },
4770     { VEX_W_TABLE (VEX_W_0F7D_P_3) },
4771   },
4772
4773   /* PREFIX_VEX_0F7E */
4774   {
4775     { Bad_Opcode },
4776     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
4777     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
4778   },
4779
4780   /* PREFIX_VEX_0F7F */
4781   {
4782     { Bad_Opcode },
4783     { VEX_W_TABLE (VEX_W_0F7F_P_1) },
4784     { VEX_W_TABLE (VEX_W_0F7F_P_2) },
4785   },
4786
4787   /* PREFIX_VEX_0F90 */
4788   {
4789     { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
4790   },
4791
4792   /* PREFIX_VEX_0F91 */
4793   {
4794     { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
4795   },
4796
4797   /* PREFIX_VEX_0F92 */
4798   {
4799     { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
4800   },
4801
4802   /* PREFIX_VEX_0F93 */
4803   {
4804     { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
4805   },
4806
4807   /* PREFIX_VEX_0F98 */
4808   {
4809     { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
4810   },
4811
4812   /* PREFIX_VEX_0FC2 */
4813   {
4814     { VEX_W_TABLE (VEX_W_0FC2_P_0) },
4815     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) },
4816     { VEX_W_TABLE (VEX_W_0FC2_P_2) },
4817     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) },
4818   },
4819
4820   /* PREFIX_VEX_0FC4 */
4821   {
4822     { Bad_Opcode },
4823     { Bad_Opcode },
4824     { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
4825   },
4826
4827   /* PREFIX_VEX_0FC5 */
4828   {
4829     { Bad_Opcode },
4830     { Bad_Opcode },
4831     { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
4832   },
4833
4834   /* PREFIX_VEX_0FD0 */
4835   {
4836     { Bad_Opcode },
4837     { Bad_Opcode },
4838     { VEX_W_TABLE (VEX_W_0FD0_P_2) },
4839     { VEX_W_TABLE (VEX_W_0FD0_P_3) },
4840   },
4841
4842   /* PREFIX_VEX_0FD1 */
4843   {
4844     { Bad_Opcode },
4845     { Bad_Opcode },
4846     { VEX_W_TABLE (VEX_W_0FD1_P_2) },
4847   },
4848
4849   /* PREFIX_VEX_0FD2 */
4850   {
4851     { Bad_Opcode },
4852     { Bad_Opcode },
4853     { VEX_W_TABLE (VEX_W_0FD2_P_2) },
4854   },
4855
4856   /* PREFIX_VEX_0FD3 */
4857   {
4858     { Bad_Opcode },
4859     { Bad_Opcode },
4860     { VEX_W_TABLE (VEX_W_0FD3_P_2) },
4861   },
4862
4863   /* PREFIX_VEX_0FD4 */
4864   {
4865     { Bad_Opcode },
4866     { Bad_Opcode },
4867     { VEX_W_TABLE (VEX_W_0FD4_P_2) },
4868   },
4869
4870   /* PREFIX_VEX_0FD5 */
4871   {
4872     { Bad_Opcode },
4873     { Bad_Opcode },
4874     { VEX_W_TABLE (VEX_W_0FD5_P_2) },
4875   },
4876
4877   /* PREFIX_VEX_0FD6 */
4878   {
4879     { Bad_Opcode },
4880     { Bad_Opcode },
4881     { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
4882   },
4883
4884   /* PREFIX_VEX_0FD7 */
4885   {
4886     { Bad_Opcode },
4887     { Bad_Opcode },
4888     { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
4889   },
4890
4891   /* PREFIX_VEX_0FD8 */
4892   {
4893     { Bad_Opcode },
4894     { Bad_Opcode },
4895     { VEX_W_TABLE (VEX_W_0FD8_P_2) },
4896   },
4897
4898   /* PREFIX_VEX_0FD9 */
4899   {
4900     { Bad_Opcode },
4901     { Bad_Opcode },
4902     { VEX_W_TABLE (VEX_W_0FD9_P_2) },
4903   },
4904
4905   /* PREFIX_VEX_0FDA */
4906   {
4907     { Bad_Opcode },
4908     { Bad_Opcode },
4909     { VEX_W_TABLE (VEX_W_0FDA_P_2) },
4910   },
4911
4912   /* PREFIX_VEX_0FDB */
4913   {
4914     { Bad_Opcode },
4915     { Bad_Opcode },
4916     { VEX_W_TABLE (VEX_W_0FDB_P_2) },
4917   },
4918
4919   /* PREFIX_VEX_0FDC */
4920   {
4921     { Bad_Opcode },
4922     { Bad_Opcode },
4923     { VEX_W_TABLE (VEX_W_0FDC_P_2) },
4924   },
4925
4926   /* PREFIX_VEX_0FDD */
4927   {
4928     { Bad_Opcode },
4929     { Bad_Opcode },
4930     { VEX_W_TABLE (VEX_W_0FDD_P_2) },
4931   },
4932
4933   /* PREFIX_VEX_0FDE */
4934   {
4935     { Bad_Opcode },
4936     { Bad_Opcode },
4937     { VEX_W_TABLE (VEX_W_0FDE_P_2) },
4938   },
4939
4940   /* PREFIX_VEX_0FDF */
4941   {
4942     { Bad_Opcode },
4943     { Bad_Opcode },
4944     { VEX_W_TABLE (VEX_W_0FDF_P_2) },
4945   },
4946
4947   /* PREFIX_VEX_0FE0 */
4948   {
4949     { Bad_Opcode },
4950     { Bad_Opcode },
4951     { VEX_W_TABLE (VEX_W_0FE0_P_2) },
4952   },
4953
4954   /* PREFIX_VEX_0FE1 */
4955   {
4956     { Bad_Opcode },
4957     { Bad_Opcode },
4958     { VEX_W_TABLE (VEX_W_0FE1_P_2) },
4959   },
4960
4961   /* PREFIX_VEX_0FE2 */
4962   {
4963     { Bad_Opcode },
4964     { Bad_Opcode },
4965     { VEX_W_TABLE (VEX_W_0FE2_P_2) },
4966   },
4967
4968   /* PREFIX_VEX_0FE3 */
4969   {
4970     { Bad_Opcode },
4971     { Bad_Opcode },
4972     { VEX_W_TABLE (VEX_W_0FE3_P_2) },
4973   },
4974
4975   /* PREFIX_VEX_0FE4 */
4976   {
4977     { Bad_Opcode },
4978     { Bad_Opcode },
4979     { VEX_W_TABLE (VEX_W_0FE4_P_2) },
4980   },
4981
4982   /* PREFIX_VEX_0FE5 */
4983   {
4984     { Bad_Opcode },
4985     { Bad_Opcode },
4986     { VEX_W_TABLE (VEX_W_0FE5_P_2) },
4987   },
4988
4989   /* PREFIX_VEX_0FE6 */
4990   {
4991     { Bad_Opcode },
4992     { VEX_W_TABLE (VEX_W_0FE6_P_1) },
4993     { VEX_W_TABLE (VEX_W_0FE6_P_2) },
4994     { VEX_W_TABLE (VEX_W_0FE6_P_3) },
4995   },
4996
4997   /* PREFIX_VEX_0FE7 */
4998   {
4999     { Bad_Opcode },
5000     { Bad_Opcode },
5001     { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5002   },
5003
5004   /* PREFIX_VEX_0FE8 */
5005   {
5006     { Bad_Opcode },
5007     { Bad_Opcode },
5008     { VEX_W_TABLE (VEX_W_0FE8_P_2) },
5009   },
5010
5011   /* PREFIX_VEX_0FE9 */
5012   {
5013     { Bad_Opcode },
5014     { Bad_Opcode },
5015     { VEX_W_TABLE (VEX_W_0FE9_P_2) },
5016   },
5017
5018   /* PREFIX_VEX_0FEA */
5019   {
5020     { Bad_Opcode },
5021     { Bad_Opcode },
5022     { VEX_W_TABLE (VEX_W_0FEA_P_2) },
5023   },
5024
5025   /* PREFIX_VEX_0FEB */
5026   {
5027     { Bad_Opcode },
5028     { Bad_Opcode },
5029     { VEX_W_TABLE (VEX_W_0FEB_P_2) },
5030   },
5031
5032   /* PREFIX_VEX_0FEC */
5033   {
5034     { Bad_Opcode },
5035     { Bad_Opcode },
5036     { VEX_W_TABLE (VEX_W_0FEC_P_2) },
5037   },
5038
5039   /* PREFIX_VEX_0FED */
5040   {
5041     { Bad_Opcode },
5042     { Bad_Opcode },
5043     { VEX_W_TABLE (VEX_W_0FED_P_2) },
5044   },
5045
5046   /* PREFIX_VEX_0FEE */
5047   {
5048     { Bad_Opcode },
5049     { Bad_Opcode },
5050     { VEX_W_TABLE (VEX_W_0FEE_P_2) },
5051   },
5052
5053   /* PREFIX_VEX_0FEF */
5054   {
5055     { Bad_Opcode },
5056     { Bad_Opcode },
5057     { VEX_W_TABLE (VEX_W_0FEF_P_2) },
5058   },
5059
5060   /* PREFIX_VEX_0FF0 */
5061   {
5062     { Bad_Opcode },
5063     { Bad_Opcode },
5064     { Bad_Opcode },
5065     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5066   },
5067
5068   /* PREFIX_VEX_0FF1 */
5069   {
5070     { Bad_Opcode },
5071     { Bad_Opcode },
5072     { VEX_W_TABLE (VEX_W_0FF1_P_2) },
5073   },
5074
5075   /* PREFIX_VEX_0FF2 */
5076   {
5077     { Bad_Opcode },
5078     { Bad_Opcode },
5079     { VEX_W_TABLE (VEX_W_0FF2_P_2) },
5080   },
5081
5082   /* PREFIX_VEX_0FF3 */
5083   {
5084     { Bad_Opcode },
5085     { Bad_Opcode },
5086     { VEX_W_TABLE (VEX_W_0FF3_P_2) },
5087   },
5088
5089   /* PREFIX_VEX_0FF4 */
5090   {
5091     { Bad_Opcode },
5092     { Bad_Opcode },
5093     { VEX_W_TABLE (VEX_W_0FF4_P_2) },
5094   },
5095
5096   /* PREFIX_VEX_0FF5 */
5097   {
5098     { Bad_Opcode },
5099     { Bad_Opcode },
5100     { VEX_W_TABLE (VEX_W_0FF5_P_2) },
5101   },
5102
5103   /* PREFIX_VEX_0FF6 */
5104   {
5105     { Bad_Opcode },
5106     { Bad_Opcode },
5107     { VEX_W_TABLE (VEX_W_0FF6_P_2) },
5108   },
5109
5110   /* PREFIX_VEX_0FF7 */
5111   {
5112     { Bad_Opcode },
5113     { Bad_Opcode },
5114     { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5115   },
5116
5117   /* PREFIX_VEX_0FF8 */
5118   {
5119     { Bad_Opcode },
5120     { Bad_Opcode },
5121     { VEX_W_TABLE (VEX_W_0FF8_P_2) },
5122   },
5123
5124   /* PREFIX_VEX_0FF9 */
5125   {
5126     { Bad_Opcode },
5127     { Bad_Opcode },
5128     { VEX_W_TABLE (VEX_W_0FF9_P_2) },
5129   },
5130
5131   /* PREFIX_VEX_0FFA */
5132   {
5133     { Bad_Opcode },
5134     { Bad_Opcode },
5135     { VEX_W_TABLE (VEX_W_0FFA_P_2) },
5136   },
5137
5138   /* PREFIX_VEX_0FFB */
5139   {
5140     { Bad_Opcode },
5141     { Bad_Opcode },
5142     { VEX_W_TABLE (VEX_W_0FFB_P_2) },
5143   },
5144
5145   /* PREFIX_VEX_0FFC */
5146   {
5147     { Bad_Opcode },
5148     { Bad_Opcode },
5149     { VEX_W_TABLE (VEX_W_0FFC_P_2) },
5150   },
5151
5152   /* PREFIX_VEX_0FFD */
5153   {
5154     { Bad_Opcode },
5155     { Bad_Opcode },
5156     { VEX_W_TABLE (VEX_W_0FFD_P_2) },
5157   },
5158
5159   /* PREFIX_VEX_0FFE */
5160   {
5161     { Bad_Opcode },
5162     { Bad_Opcode },
5163     { VEX_W_TABLE (VEX_W_0FFE_P_2) },
5164   },
5165
5166   /* PREFIX_VEX_0F3800 */
5167   {
5168     { Bad_Opcode },
5169     { Bad_Opcode },
5170     { VEX_W_TABLE (VEX_W_0F3800_P_2) },
5171   },
5172
5173   /* PREFIX_VEX_0F3801 */
5174   {
5175     { Bad_Opcode },
5176     { Bad_Opcode },
5177     { VEX_W_TABLE (VEX_W_0F3801_P_2) },
5178   },
5179
5180   /* PREFIX_VEX_0F3802 */
5181   {
5182     { Bad_Opcode },
5183     { Bad_Opcode },
5184     { VEX_W_TABLE (VEX_W_0F3802_P_2) },
5185   },
5186
5187   /* PREFIX_VEX_0F3803 */
5188   {
5189     { Bad_Opcode },
5190     { Bad_Opcode },
5191     { VEX_W_TABLE (VEX_W_0F3803_P_2) },
5192   },
5193
5194   /* PREFIX_VEX_0F3804 */
5195   {
5196     { Bad_Opcode },
5197     { Bad_Opcode },
5198     { VEX_W_TABLE (VEX_W_0F3804_P_2) },
5199   },
5200
5201   /* PREFIX_VEX_0F3805 */
5202   {
5203     { Bad_Opcode },
5204     { Bad_Opcode },
5205     { VEX_W_TABLE (VEX_W_0F3805_P_2) },
5206   },
5207
5208   /* PREFIX_VEX_0F3806 */
5209   {
5210     { Bad_Opcode },
5211     { Bad_Opcode },
5212     { VEX_W_TABLE (VEX_W_0F3806_P_2) },
5213   },
5214
5215   /* PREFIX_VEX_0F3807 */
5216   {
5217     { Bad_Opcode },
5218     { Bad_Opcode },
5219     { VEX_W_TABLE (VEX_W_0F3807_P_2) },
5220   },
5221
5222   /* PREFIX_VEX_0F3808 */
5223   {
5224     { Bad_Opcode },
5225     { Bad_Opcode },
5226     { VEX_W_TABLE (VEX_W_0F3808_P_2) },
5227   },
5228
5229   /* PREFIX_VEX_0F3809 */
5230   {
5231     { Bad_Opcode },
5232     { Bad_Opcode },
5233     { VEX_W_TABLE (VEX_W_0F3809_P_2) },
5234   },
5235
5236   /* PREFIX_VEX_0F380A */
5237   {
5238     { Bad_Opcode },
5239     { Bad_Opcode },
5240     { VEX_W_TABLE (VEX_W_0F380A_P_2) },
5241   },
5242
5243   /* PREFIX_VEX_0F380B */
5244   {
5245     { Bad_Opcode },
5246     { Bad_Opcode },
5247     { VEX_W_TABLE (VEX_W_0F380B_P_2) },
5248   },
5249
5250   /* PREFIX_VEX_0F380C */
5251   {
5252     { Bad_Opcode },
5253     { Bad_Opcode },
5254     { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5255   },
5256
5257   /* PREFIX_VEX_0F380D */
5258   {
5259     { Bad_Opcode },
5260     { Bad_Opcode },
5261     { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5262   },
5263
5264   /* PREFIX_VEX_0F380E */
5265   {
5266     { Bad_Opcode },
5267     { Bad_Opcode },
5268     { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5269   },
5270
5271   /* PREFIX_VEX_0F380F */
5272   {
5273     { Bad_Opcode },
5274     { Bad_Opcode },
5275     { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5276   },
5277
5278   /* PREFIX_VEX_0F3813 */
5279   {
5280     { Bad_Opcode },
5281     { Bad_Opcode },
5282     { "vcvtph2ps", { XM, EXxmmq } },
5283   },
5284
5285   /* PREFIX_VEX_0F3816 */
5286   {
5287     { Bad_Opcode },
5288     { Bad_Opcode },
5289     { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5290   },
5291
5292   /* PREFIX_VEX_0F3817 */
5293   {
5294     { Bad_Opcode },
5295     { Bad_Opcode },
5296     { VEX_W_TABLE (VEX_W_0F3817_P_2) },
5297   },
5298
5299   /* PREFIX_VEX_0F3818 */
5300   {
5301     { Bad_Opcode },
5302     { Bad_Opcode },
5303     { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5304   },
5305
5306   /* PREFIX_VEX_0F3819 */
5307   {
5308     { Bad_Opcode },
5309     { Bad_Opcode },
5310     { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5311   },
5312
5313   /* PREFIX_VEX_0F381A */
5314   {
5315     { Bad_Opcode },
5316     { Bad_Opcode },
5317     { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5318   },
5319
5320   /* PREFIX_VEX_0F381C */
5321   {
5322     { Bad_Opcode },
5323     { Bad_Opcode },
5324     { VEX_W_TABLE (VEX_W_0F381C_P_2) },
5325   },
5326
5327   /* PREFIX_VEX_0F381D */
5328   {
5329     { Bad_Opcode },
5330     { Bad_Opcode },
5331     { VEX_W_TABLE (VEX_W_0F381D_P_2) },
5332   },
5333
5334   /* PREFIX_VEX_0F381E */
5335   {
5336     { Bad_Opcode },
5337     { Bad_Opcode },
5338     { VEX_W_TABLE (VEX_W_0F381E_P_2) },
5339   },
5340
5341   /* PREFIX_VEX_0F3820 */
5342   {
5343     { Bad_Opcode },
5344     { Bad_Opcode },
5345     { VEX_W_TABLE (VEX_W_0F3820_P_2) },
5346   },
5347
5348   /* PREFIX_VEX_0F3821 */
5349   {
5350     { Bad_Opcode },
5351     { Bad_Opcode },
5352     { VEX_W_TABLE (VEX_W_0F3821_P_2) },
5353   },
5354
5355   /* PREFIX_VEX_0F3822 */
5356   {
5357     { Bad_Opcode },
5358     { Bad_Opcode },
5359     { VEX_W_TABLE (VEX_W_0F3822_P_2) },
5360   },
5361
5362   /* PREFIX_VEX_0F3823 */
5363   {
5364     { Bad_Opcode },
5365     { Bad_Opcode },
5366     { VEX_W_TABLE (VEX_W_0F3823_P_2) },
5367   },
5368
5369   /* PREFIX_VEX_0F3824 */
5370   {
5371     { Bad_Opcode },
5372     { Bad_Opcode },
5373     { VEX_W_TABLE (VEX_W_0F3824_P_2) },
5374   },
5375
5376   /* PREFIX_VEX_0F3825 */
5377   {
5378     { Bad_Opcode },
5379     { Bad_Opcode },
5380     { VEX_W_TABLE (VEX_W_0F3825_P_2) },
5381   },
5382
5383   /* PREFIX_VEX_0F3828 */
5384   {
5385     { Bad_Opcode },
5386     { Bad_Opcode },
5387     { VEX_W_TABLE (VEX_W_0F3828_P_2) },
5388   },
5389
5390   /* PREFIX_VEX_0F3829 */
5391   {
5392     { Bad_Opcode },
5393     { Bad_Opcode },
5394     { VEX_W_TABLE (VEX_W_0F3829_P_2) },
5395   },
5396
5397   /* PREFIX_VEX_0F382A */
5398   {
5399     { Bad_Opcode },
5400     { Bad_Opcode },
5401     { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5402   },
5403
5404   /* PREFIX_VEX_0F382B */
5405   {
5406     { Bad_Opcode },
5407     { Bad_Opcode },
5408     { VEX_W_TABLE (VEX_W_0F382B_P_2) },
5409   },
5410
5411   /* PREFIX_VEX_0F382C */
5412   {
5413     { Bad_Opcode },
5414     { Bad_Opcode },
5415      { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5416   },
5417
5418   /* PREFIX_VEX_0F382D */
5419   {
5420     { Bad_Opcode },
5421     { Bad_Opcode },
5422      { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5423   },
5424
5425   /* PREFIX_VEX_0F382E */
5426   {
5427     { Bad_Opcode },
5428     { Bad_Opcode },
5429      { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5430   },
5431
5432   /* PREFIX_VEX_0F382F */
5433   {
5434     { Bad_Opcode },
5435     { Bad_Opcode },
5436      { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5437   },
5438
5439   /* PREFIX_VEX_0F3830 */
5440   {
5441     { Bad_Opcode },
5442     { Bad_Opcode },
5443     { VEX_W_TABLE (VEX_W_0F3830_P_2) },
5444   },
5445
5446   /* PREFIX_VEX_0F3831 */
5447   {
5448     { Bad_Opcode },
5449     { Bad_Opcode },
5450     { VEX_W_TABLE (VEX_W_0F3831_P_2) },
5451   },
5452
5453   /* PREFIX_VEX_0F3832 */
5454   {
5455     { Bad_Opcode },
5456     { Bad_Opcode },
5457     { VEX_W_TABLE (VEX_W_0F3832_P_2) },
5458   },
5459
5460   /* PREFIX_VEX_0F3833 */
5461   {
5462     { Bad_Opcode },
5463     { Bad_Opcode },
5464     { VEX_W_TABLE (VEX_W_0F3833_P_2) },
5465   },
5466
5467   /* PREFIX_VEX_0F3834 */
5468   {
5469     { Bad_Opcode },
5470     { Bad_Opcode },
5471     { VEX_W_TABLE (VEX_W_0F3834_P_2) },
5472   },
5473
5474   /* PREFIX_VEX_0F3835 */
5475   {
5476     { Bad_Opcode },
5477     { Bad_Opcode },
5478     { VEX_W_TABLE (VEX_W_0F3835_P_2) },
5479   },
5480
5481   /* PREFIX_VEX_0F3836 */
5482   {
5483     { Bad_Opcode },
5484     { Bad_Opcode },
5485     { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5486   },
5487
5488   /* PREFIX_VEX_0F3837 */
5489   {
5490     { Bad_Opcode },
5491     { Bad_Opcode },
5492     { VEX_W_TABLE (VEX_W_0F3837_P_2) },
5493   },
5494
5495   /* PREFIX_VEX_0F3838 */
5496   {
5497     { Bad_Opcode },
5498     { Bad_Opcode },
5499     { VEX_W_TABLE (VEX_W_0F3838_P_2) },
5500   },
5501
5502   /* PREFIX_VEX_0F3839 */
5503   {
5504     { Bad_Opcode },
5505     { Bad_Opcode },
5506     { VEX_W_TABLE (VEX_W_0F3839_P_2) },
5507   },
5508
5509   /* PREFIX_VEX_0F383A */
5510   {
5511     { Bad_Opcode },
5512     { Bad_Opcode },
5513     { VEX_W_TABLE (VEX_W_0F383A_P_2) },
5514   },
5515
5516   /* PREFIX_VEX_0F383B */
5517   {
5518     { Bad_Opcode },
5519     { Bad_Opcode },
5520     { VEX_W_TABLE (VEX_W_0F383B_P_2) },
5521   },
5522
5523   /* PREFIX_VEX_0F383C */
5524   {
5525     { Bad_Opcode },
5526     { Bad_Opcode },
5527     { VEX_W_TABLE (VEX_W_0F383C_P_2) },
5528   },
5529
5530   /* PREFIX_VEX_0F383D */
5531   {
5532     { Bad_Opcode },
5533     { Bad_Opcode },
5534     { VEX_W_TABLE (VEX_W_0F383D_P_2) },
5535   },
5536
5537   /* PREFIX_VEX_0F383E */
5538   {
5539     { Bad_Opcode },
5540     { Bad_Opcode },
5541     { VEX_W_TABLE (VEX_W_0F383E_P_2) },
5542   },
5543
5544   /* PREFIX_VEX_0F383F */
5545   {
5546     { Bad_Opcode },
5547     { Bad_Opcode },
5548     { VEX_W_TABLE (VEX_W_0F383F_P_2) },
5549   },
5550
5551   /* PREFIX_VEX_0F3840 */
5552   {
5553     { Bad_Opcode },
5554     { Bad_Opcode },
5555     { VEX_W_TABLE (VEX_W_0F3840_P_2) },
5556   },
5557
5558   /* PREFIX_VEX_0F3841 */
5559   {
5560     { Bad_Opcode },
5561     { Bad_Opcode },
5562     { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
5563   },
5564
5565   /* PREFIX_VEX_0F3845 */
5566   {
5567     { Bad_Opcode },
5568     { Bad_Opcode },
5569     { "vpsrlv%LW", { XM, Vex, EXx } },
5570   },
5571
5572   /* PREFIX_VEX_0F3846 */
5573   {
5574     { Bad_Opcode },
5575     { Bad_Opcode },
5576     { VEX_W_TABLE (VEX_W_0F3846_P_2) },
5577   },
5578
5579   /* PREFIX_VEX_0F3847 */
5580   {
5581     { Bad_Opcode },
5582     { Bad_Opcode },
5583     { "vpsllv%LW", { XM, Vex, EXx } },
5584   },
5585
5586   /* PREFIX_VEX_0F3858 */
5587   {
5588     { Bad_Opcode },
5589     { Bad_Opcode },
5590     { VEX_W_TABLE (VEX_W_0F3858_P_2) },
5591   },
5592
5593   /* PREFIX_VEX_0F3859 */
5594   {
5595     { Bad_Opcode },
5596     { Bad_Opcode },
5597     { VEX_W_TABLE (VEX_W_0F3859_P_2) },
5598   },
5599
5600   /* PREFIX_VEX_0F385A */
5601   {
5602     { Bad_Opcode },
5603     { Bad_Opcode },
5604     { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
5605   },
5606
5607   /* PREFIX_VEX_0F3878 */
5608   {
5609     { Bad_Opcode },
5610     { Bad_Opcode },
5611     { VEX_W_TABLE (VEX_W_0F3878_P_2) },
5612   },
5613
5614   /* PREFIX_VEX_0F3879 */
5615   {
5616     { Bad_Opcode },
5617     { Bad_Opcode },
5618     { VEX_W_TABLE (VEX_W_0F3879_P_2) },
5619   },
5620
5621   /* PREFIX_VEX_0F388C */
5622   {
5623     { Bad_Opcode },
5624     { Bad_Opcode },
5625     { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
5626   },
5627
5628   /* PREFIX_VEX_0F388E */
5629   {
5630     { Bad_Opcode },
5631     { Bad_Opcode },
5632     { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
5633   },
5634
5635   /* PREFIX_VEX_0F3890 */
5636   {
5637     { Bad_Opcode },
5638     { Bad_Opcode },
5639     { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex } },
5640   },
5641
5642   /* PREFIX_VEX_0F3891 */
5643   {
5644     { Bad_Opcode },
5645     { Bad_Opcode },
5646     { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ } },
5647   },
5648
5649   /* PREFIX_VEX_0F3892 */
5650   {
5651     { Bad_Opcode },
5652     { Bad_Opcode },
5653     { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex } },
5654   },
5655
5656   /* PREFIX_VEX_0F3893 */
5657   {
5658     { Bad_Opcode },
5659     { Bad_Opcode },
5660     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ } },
5661   },
5662
5663   /* PREFIX_VEX_0F3896 */
5664   {
5665     { Bad_Opcode },
5666     { Bad_Opcode },
5667     { "vfmaddsub132p%XW", { XM, Vex, EXx } },
5668   },
5669
5670   /* PREFIX_VEX_0F3897 */
5671   {
5672     { Bad_Opcode },
5673     { Bad_Opcode },
5674     { "vfmsubadd132p%XW", { XM, Vex, EXx } },
5675   },
5676
5677   /* PREFIX_VEX_0F3898 */
5678   {
5679     { Bad_Opcode },
5680     { Bad_Opcode },
5681     { "vfmadd132p%XW", { XM, Vex, EXx } },
5682   },
5683
5684   /* PREFIX_VEX_0F3899 */
5685   {
5686     { Bad_Opcode },
5687     { Bad_Opcode },
5688     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5689   },
5690
5691   /* PREFIX_VEX_0F389A */
5692   {
5693     { Bad_Opcode },
5694     { Bad_Opcode },
5695     { "vfmsub132p%XW", { XM, Vex, EXx } },
5696   },
5697
5698   /* PREFIX_VEX_0F389B */
5699   {
5700     { Bad_Opcode },
5701     { Bad_Opcode },
5702     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5703   },
5704
5705   /* PREFIX_VEX_0F389C */
5706   {
5707     { Bad_Opcode },
5708     { Bad_Opcode },
5709     { "vfnmadd132p%XW", { XM, Vex, EXx } },
5710   },
5711
5712   /* PREFIX_VEX_0F389D */
5713   {
5714     { Bad_Opcode },
5715     { Bad_Opcode },
5716     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5717   },
5718
5719   /* PREFIX_VEX_0F389E */
5720   {
5721     { Bad_Opcode },
5722     { Bad_Opcode },
5723     { "vfnmsub132p%XW", { XM, Vex, EXx } },
5724   },
5725
5726   /* PREFIX_VEX_0F389F */
5727   {
5728     { Bad_Opcode },
5729     { Bad_Opcode },
5730     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5731   },
5732
5733   /* PREFIX_VEX_0F38A6 */
5734   {
5735     { Bad_Opcode },
5736     { Bad_Opcode },
5737     { "vfmaddsub213p%XW", { XM, Vex, EXx } },
5738     { Bad_Opcode },
5739   },
5740
5741   /* PREFIX_VEX_0F38A7 */
5742   {
5743     { Bad_Opcode },
5744     { Bad_Opcode },
5745     { "vfmsubadd213p%XW", { XM, Vex, EXx } },
5746   },
5747
5748   /* PREFIX_VEX_0F38A8 */
5749   {
5750     { Bad_Opcode },
5751     { Bad_Opcode },
5752     { "vfmadd213p%XW", { XM, Vex, EXx } },
5753   },
5754
5755   /* PREFIX_VEX_0F38A9 */
5756   {
5757     { Bad_Opcode },
5758     { Bad_Opcode },
5759     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5760   },
5761
5762   /* PREFIX_VEX_0F38AA */
5763   {
5764     { Bad_Opcode },
5765     { Bad_Opcode },
5766     { "vfmsub213p%XW", { XM, Vex, EXx } },
5767   },
5768
5769   /* PREFIX_VEX_0F38AB */
5770   {
5771     { Bad_Opcode },
5772     { Bad_Opcode },
5773     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5774   },
5775
5776   /* PREFIX_VEX_0F38AC */
5777   {
5778     { Bad_Opcode },
5779     { Bad_Opcode },
5780     { "vfnmadd213p%XW", { XM, Vex, EXx } },
5781   },
5782
5783   /* PREFIX_VEX_0F38AD */
5784   {
5785     { Bad_Opcode },
5786     { Bad_Opcode },
5787     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5788   },
5789
5790   /* PREFIX_VEX_0F38AE */
5791   {
5792     { Bad_Opcode },
5793     { Bad_Opcode },
5794     { "vfnmsub213p%XW", { XM, Vex, EXx } },
5795   },
5796
5797   /* PREFIX_VEX_0F38AF */
5798   {
5799     { Bad_Opcode },
5800     { Bad_Opcode },
5801     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5802   },
5803
5804   /* PREFIX_VEX_0F38B6 */
5805   {
5806     { Bad_Opcode },
5807     { Bad_Opcode },
5808     { "vfmaddsub231p%XW", { XM, Vex, EXx } },
5809   },
5810
5811   /* PREFIX_VEX_0F38B7 */
5812   {
5813     { Bad_Opcode },
5814     { Bad_Opcode },
5815     { "vfmsubadd231p%XW", { XM, Vex, EXx } },
5816   },
5817
5818   /* PREFIX_VEX_0F38B8 */
5819   {
5820     { Bad_Opcode },
5821     { Bad_Opcode },
5822     { "vfmadd231p%XW", { XM, Vex, EXx } },
5823   },
5824
5825   /* PREFIX_VEX_0F38B9 */
5826   {
5827     { Bad_Opcode },
5828     { Bad_Opcode },
5829     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5830   },
5831
5832   /* PREFIX_VEX_0F38BA */
5833   {
5834     { Bad_Opcode },
5835     { Bad_Opcode },
5836     { "vfmsub231p%XW", { XM, Vex, EXx } },
5837   },
5838
5839   /* PREFIX_VEX_0F38BB */
5840   {
5841     { Bad_Opcode },
5842     { Bad_Opcode },
5843     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5844   },
5845
5846   /* PREFIX_VEX_0F38BC */
5847   {
5848     { Bad_Opcode },
5849     { Bad_Opcode },
5850     { "vfnmadd231p%XW", { XM, Vex, EXx } },
5851   },
5852
5853   /* PREFIX_VEX_0F38BD */
5854   {
5855     { Bad_Opcode },
5856     { Bad_Opcode },
5857     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5858   },
5859
5860   /* PREFIX_VEX_0F38BE */
5861   {
5862     { Bad_Opcode },
5863     { Bad_Opcode },
5864     { "vfnmsub231p%XW", { XM, Vex, EXx } },
5865   },
5866
5867   /* PREFIX_VEX_0F38BF */
5868   {
5869     { Bad_Opcode },
5870     { Bad_Opcode },
5871     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5872   },
5873
5874   /* PREFIX_VEX_0F38DB */
5875   {
5876     { Bad_Opcode },
5877     { Bad_Opcode },
5878     { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
5879   },
5880
5881   /* PREFIX_VEX_0F38DC */
5882   {
5883     { Bad_Opcode },
5884     { Bad_Opcode },
5885     { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2) },
5886   },
5887
5888   /* PREFIX_VEX_0F38DD */
5889   {
5890     { Bad_Opcode },
5891     { Bad_Opcode },
5892     { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2) },
5893   },
5894
5895   /* PREFIX_VEX_0F38DE */
5896   {
5897     { Bad_Opcode },
5898     { Bad_Opcode },
5899     { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2) },
5900   },
5901
5902   /* PREFIX_VEX_0F38DF */
5903   {
5904     { Bad_Opcode },
5905     { Bad_Opcode },
5906     { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2) },
5907   },
5908
5909   /* PREFIX_VEX_0F38F2 */
5910   {
5911     { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
5912   },
5913
5914   /* PREFIX_VEX_0F38F3_REG_1 */
5915   {
5916     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
5917   },
5918
5919   /* PREFIX_VEX_0F38F3_REG_2 */
5920   {
5921     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
5922   },
5923
5924   /* PREFIX_VEX_0F38F3_REG_3 */
5925   {
5926     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
5927   },
5928
5929   /* PREFIX_VEX_0F38F5 */
5930   {
5931     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
5932     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
5933     { Bad_Opcode },
5934     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
5935   },
5936
5937   /* PREFIX_VEX_0F38F6 */
5938   {
5939     { Bad_Opcode },
5940     { Bad_Opcode },
5941     { Bad_Opcode },
5942     { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
5943   },
5944
5945   /* PREFIX_VEX_0F38F7 */
5946   {
5947     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
5948     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
5949     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
5950     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
5951   },
5952
5953   /* PREFIX_VEX_0F3A00 */
5954   {
5955     { Bad_Opcode },
5956     { Bad_Opcode },
5957     { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
5958   },
5959
5960   /* PREFIX_VEX_0F3A01 */
5961   {
5962     { Bad_Opcode },
5963     { Bad_Opcode },
5964     { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
5965   },
5966
5967   /* PREFIX_VEX_0F3A02 */
5968   {
5969     { Bad_Opcode },
5970     { Bad_Opcode },
5971     { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
5972   },
5973
5974   /* PREFIX_VEX_0F3A04 */
5975   {
5976     { Bad_Opcode },
5977     { Bad_Opcode },
5978     { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
5979   },
5980
5981   /* PREFIX_VEX_0F3A05 */
5982   {
5983     { Bad_Opcode },
5984     { Bad_Opcode },
5985     { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
5986   },
5987
5988   /* PREFIX_VEX_0F3A06 */
5989   {
5990     { Bad_Opcode },
5991     { Bad_Opcode },
5992     { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
5993   },
5994
5995   /* PREFIX_VEX_0F3A08 */
5996   {
5997     { Bad_Opcode },
5998     { Bad_Opcode },
5999     { VEX_W_TABLE (VEX_W_0F3A08_P_2) },
6000   },
6001
6002   /* PREFIX_VEX_0F3A09 */
6003   {
6004     { Bad_Opcode },
6005     { Bad_Opcode },
6006     { VEX_W_TABLE (VEX_W_0F3A09_P_2) },
6007   },
6008
6009   /* PREFIX_VEX_0F3A0A */
6010   {
6011     { Bad_Opcode },
6012     { Bad_Opcode },
6013     { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) },
6014   },
6015
6016   /* PREFIX_VEX_0F3A0B */
6017   {
6018     { Bad_Opcode },
6019     { Bad_Opcode },
6020     { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) },
6021   },
6022
6023   /* PREFIX_VEX_0F3A0C */
6024   {
6025     { Bad_Opcode },
6026     { Bad_Opcode },
6027     { VEX_W_TABLE (VEX_W_0F3A0C_P_2) },
6028   },
6029
6030   /* PREFIX_VEX_0F3A0D */
6031   {
6032     { Bad_Opcode },
6033     { Bad_Opcode },
6034     { VEX_W_TABLE (VEX_W_0F3A0D_P_2) },
6035   },
6036
6037   /* PREFIX_VEX_0F3A0E */
6038   {
6039     { Bad_Opcode },
6040     { Bad_Opcode },
6041     { VEX_W_TABLE (VEX_W_0F3A0E_P_2) },
6042   },
6043
6044   /* PREFIX_VEX_0F3A0F */
6045   {
6046     { Bad_Opcode },
6047     { Bad_Opcode },
6048     { VEX_W_TABLE (VEX_W_0F3A0F_P_2) },
6049   },
6050
6051   /* PREFIX_VEX_0F3A14 */
6052   {
6053     { Bad_Opcode },
6054     { Bad_Opcode },
6055     { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6056   },
6057
6058   /* PREFIX_VEX_0F3A15 */
6059   {
6060     { Bad_Opcode },
6061     { Bad_Opcode },
6062     { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6063   },
6064
6065   /* PREFIX_VEX_0F3A16 */
6066   {
6067     { Bad_Opcode },
6068     { Bad_Opcode },
6069     { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6070   },
6071
6072   /* PREFIX_VEX_0F3A17 */
6073   {
6074     { Bad_Opcode },
6075     { Bad_Opcode },
6076     { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6077   },
6078
6079   /* PREFIX_VEX_0F3A18 */
6080   {
6081     { Bad_Opcode },
6082     { Bad_Opcode },
6083     { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6084   },
6085
6086   /* PREFIX_VEX_0F3A19 */
6087   {
6088     { Bad_Opcode },
6089     { Bad_Opcode },
6090     { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6091   },
6092
6093   /* PREFIX_VEX_0F3A1D */
6094   {
6095     { Bad_Opcode },
6096     { Bad_Opcode },
6097     { "vcvtps2ph", { EXxmmq, XM, Ib } },
6098   },
6099
6100   /* PREFIX_VEX_0F3A20 */
6101   {
6102     { Bad_Opcode },
6103     { Bad_Opcode },
6104     { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6105   },
6106
6107   /* PREFIX_VEX_0F3A21 */
6108   {
6109     { Bad_Opcode },
6110     { Bad_Opcode },
6111     { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6112   },
6113
6114   /* PREFIX_VEX_0F3A22 */
6115   {
6116     { Bad_Opcode },
6117     { Bad_Opcode },
6118     { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6119   },
6120
6121   /* PREFIX_VEX_0F3A30 */
6122   {
6123     { Bad_Opcode },
6124     { Bad_Opcode },
6125     { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6126   },
6127
6128   /* PREFIX_VEX_0F3A32 */
6129   {
6130     { Bad_Opcode },
6131     { Bad_Opcode },
6132     { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6133   },
6134
6135   /* PREFIX_VEX_0F3A38 */
6136   {
6137     { Bad_Opcode },
6138     { Bad_Opcode },
6139     { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6140   },
6141
6142   /* PREFIX_VEX_0F3A39 */
6143   {
6144     { Bad_Opcode },
6145     { Bad_Opcode },
6146     { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6147   },
6148
6149   /* PREFIX_VEX_0F3A40 */
6150   {
6151     { Bad_Opcode },
6152     { Bad_Opcode },
6153     { VEX_W_TABLE (VEX_W_0F3A40_P_2) },
6154   },
6155
6156   /* PREFIX_VEX_0F3A41 */
6157   {
6158     { Bad_Opcode },
6159     { Bad_Opcode },
6160     { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6161   },
6162
6163   /* PREFIX_VEX_0F3A42 */
6164   {
6165     { Bad_Opcode },
6166     { Bad_Opcode },
6167     { VEX_W_TABLE (VEX_W_0F3A42_P_2) },
6168   },
6169
6170   /* PREFIX_VEX_0F3A44 */
6171   {
6172     { Bad_Opcode },
6173     { Bad_Opcode },
6174     { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2) },
6175   },
6176
6177   /* PREFIX_VEX_0F3A46 */
6178   {
6179     { Bad_Opcode },
6180     { Bad_Opcode },
6181     { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6182   },
6183
6184   /* PREFIX_VEX_0F3A48 */
6185   {
6186     { Bad_Opcode },
6187     { Bad_Opcode },
6188     { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6189   },
6190
6191   /* PREFIX_VEX_0F3A49 */
6192   {
6193     { Bad_Opcode },
6194     { Bad_Opcode },
6195     { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6196   },
6197
6198   /* PREFIX_VEX_0F3A4A */
6199   {
6200     { Bad_Opcode },
6201     { Bad_Opcode },
6202     { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6203   },
6204
6205   /* PREFIX_VEX_0F3A4B */
6206   {
6207     { Bad_Opcode },
6208     { Bad_Opcode },
6209     { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6210   },
6211
6212   /* PREFIX_VEX_0F3A4C */
6213   {
6214     { Bad_Opcode },
6215     { Bad_Opcode },
6216     { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6217   },
6218
6219   /* PREFIX_VEX_0F3A5C */
6220   {
6221     { Bad_Opcode },
6222     { Bad_Opcode },
6223     { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6224   },
6225
6226   /* PREFIX_VEX_0F3A5D */
6227   {
6228     { Bad_Opcode },
6229     { Bad_Opcode },
6230     { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6231   },
6232
6233   /* PREFIX_VEX_0F3A5E */
6234   {
6235     { Bad_Opcode },
6236     { Bad_Opcode },
6237     { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6238   },
6239
6240   /* PREFIX_VEX_0F3A5F */
6241   {
6242     { Bad_Opcode },
6243     { Bad_Opcode },
6244     { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6245   },
6246
6247   /* PREFIX_VEX_0F3A60 */
6248   {
6249     { Bad_Opcode },
6250     { Bad_Opcode },
6251     { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6252     { Bad_Opcode },
6253   },
6254
6255   /* PREFIX_VEX_0F3A61 */
6256   {
6257     { Bad_Opcode },
6258     { Bad_Opcode },
6259     { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6260   },
6261
6262   /* PREFIX_VEX_0F3A62 */
6263   {
6264     { Bad_Opcode },
6265     { Bad_Opcode },
6266     { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6267   },
6268
6269   /* PREFIX_VEX_0F3A63 */
6270   {
6271     { Bad_Opcode },
6272     { Bad_Opcode },
6273     { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6274   },
6275
6276   /* PREFIX_VEX_0F3A68 */
6277   {
6278     { Bad_Opcode },
6279     { Bad_Opcode },
6280     { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6281   },
6282
6283   /* PREFIX_VEX_0F3A69 */
6284   {
6285     { Bad_Opcode },
6286     { Bad_Opcode },
6287     { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6288   },
6289
6290   /* PREFIX_VEX_0F3A6A */
6291   {
6292     { Bad_Opcode },
6293     { Bad_Opcode },
6294     { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6295   },
6296
6297   /* PREFIX_VEX_0F3A6B */
6298   {
6299     { Bad_Opcode },
6300     { Bad_Opcode },
6301     { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6302   },
6303
6304   /* PREFIX_VEX_0F3A6C */
6305   {
6306     { Bad_Opcode },
6307     { Bad_Opcode },
6308     { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6309   },
6310
6311   /* PREFIX_VEX_0F3A6D */
6312   {
6313     { Bad_Opcode },
6314     { Bad_Opcode },
6315     { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6316   },
6317
6318   /* PREFIX_VEX_0F3A6E */
6319   {
6320     { Bad_Opcode },
6321     { Bad_Opcode },
6322     { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6323   },
6324
6325   /* PREFIX_VEX_0F3A6F */
6326   {
6327     { Bad_Opcode },
6328     { Bad_Opcode },
6329     { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6330   },
6331
6332   /* PREFIX_VEX_0F3A78 */
6333   {
6334     { Bad_Opcode },
6335     { Bad_Opcode },
6336     { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6337   },
6338
6339   /* PREFIX_VEX_0F3A79 */
6340   {
6341     { Bad_Opcode },
6342     { Bad_Opcode },
6343     { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6344   },
6345
6346   /* PREFIX_VEX_0F3A7A */
6347   {
6348     { Bad_Opcode },
6349     { Bad_Opcode },
6350     { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6351   },
6352
6353   /* PREFIX_VEX_0F3A7B */
6354   {
6355     { Bad_Opcode },
6356     { Bad_Opcode },
6357     { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6358   },
6359
6360   /* PREFIX_VEX_0F3A7C */
6361   {
6362     { Bad_Opcode },
6363     { Bad_Opcode },
6364     { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6365     { Bad_Opcode },
6366   },
6367
6368   /* PREFIX_VEX_0F3A7D */
6369   {
6370     { Bad_Opcode },
6371     { Bad_Opcode },
6372     { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6373   },
6374
6375   /* PREFIX_VEX_0F3A7E */
6376   {
6377     { Bad_Opcode },
6378     { Bad_Opcode },
6379     { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6380   },
6381
6382   /* PREFIX_VEX_0F3A7F */
6383   {
6384     { Bad_Opcode },
6385     { Bad_Opcode },
6386     { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6387   },
6388
6389   /* PREFIX_VEX_0F3ADF */
6390   {
6391     { Bad_Opcode },
6392     { Bad_Opcode },
6393     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6394   },
6395
6396   /* PREFIX_VEX_0F3AF0 */
6397   {
6398     { Bad_Opcode },
6399     { Bad_Opcode },
6400     { Bad_Opcode },
6401     { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6402   },
6403
6404 #define NEED_PREFIX_TABLE
6405 #include "i386-dis-evex.h"
6406 #undef NEED_PREFIX_TABLE
6407 };
6408
6409 static const struct dis386 x86_64_table[][2] = {
6410   /* X86_64_06 */
6411   {
6412     { "pushP", { es } },
6413   },
6414
6415   /* X86_64_07 */
6416   {
6417     { "popP", { es } },
6418   },
6419
6420   /* X86_64_0D */
6421   {
6422     { "pushP", { cs } },
6423   },
6424
6425   /* X86_64_16 */
6426   {
6427     { "pushP", { ss } },
6428   },
6429
6430   /* X86_64_17 */
6431   {
6432     { "popP", { ss } },
6433   },
6434
6435   /* X86_64_1E */
6436   {
6437     { "pushP", { ds } },
6438   },
6439
6440   /* X86_64_1F */
6441   {
6442     { "popP", { ds } },
6443   },
6444
6445   /* X86_64_27 */
6446   {
6447     { "daa", { XX } },
6448   },
6449
6450   /* X86_64_2F */
6451   {
6452     { "das", { XX } },
6453   },
6454
6455   /* X86_64_37 */
6456   {
6457     { "aaa", { XX } },
6458   },
6459
6460   /* X86_64_3F */
6461   {
6462     { "aas", { XX } },
6463   },
6464
6465   /* X86_64_60 */
6466   {
6467     { "pushaP", { XX } },
6468   },
6469
6470   /* X86_64_61 */
6471   {
6472     { "popaP", { XX } },
6473   },
6474
6475   /* X86_64_62 */
6476   {
6477     { MOD_TABLE (MOD_62_32BIT) },
6478     { EVEX_TABLE (EVEX_0F) },
6479   },
6480
6481   /* X86_64_63 */
6482   {
6483     { "arpl", { Ew, Gw } },
6484     { "movs{lq|xd}", { Gv, Ed } },
6485   },
6486
6487   /* X86_64_6D */
6488   {
6489     { "ins{R|}", { Yzr, indirDX } },
6490     { "ins{G|}", { Yzr, indirDX } },
6491   },
6492
6493   /* X86_64_6F */
6494   {
6495     { "outs{R|}", { indirDXr, Xz } },
6496     { "outs{G|}", { indirDXr, Xz } },
6497   },
6498
6499   /* X86_64_9A */
6500   {
6501     { "Jcall{T|}", { Ap } },
6502   },
6503
6504   /* X86_64_C4 */
6505   {
6506     { MOD_TABLE (MOD_C4_32BIT) },
6507     { VEX_C4_TABLE (VEX_0F) },
6508   },
6509
6510   /* X86_64_C5 */
6511   {
6512     { MOD_TABLE (MOD_C5_32BIT) },
6513     { VEX_C5_TABLE (VEX_0F) },
6514   },
6515
6516   /* X86_64_CE */
6517   {
6518     { "into", { XX } },
6519   },
6520
6521   /* X86_64_D4 */
6522   {
6523     { "aam", { Ib } },
6524   },
6525
6526   /* X86_64_D5 */
6527   {
6528     { "aad", { Ib } },
6529   },
6530
6531   /* X86_64_EA */
6532   {
6533     { "Jjmp{T|}", { Ap } },
6534   },
6535
6536   /* X86_64_0F01_REG_0 */
6537   {
6538     { "sgdt{Q|IQ}", { M } },
6539     { "sgdt", { M } },
6540   },
6541
6542   /* X86_64_0F01_REG_1 */
6543   {
6544     { "sidt{Q|IQ}", { M } },
6545     { "sidt", { M } },
6546   },
6547
6548   /* X86_64_0F01_REG_2 */
6549   {
6550     { "lgdt{Q|Q}", { M } },
6551     { "lgdt", { M } },
6552   },
6553
6554   /* X86_64_0F01_REG_3 */
6555   {
6556     { "lidt{Q|Q}", { M } },
6557     { "lidt", { M } },
6558   },
6559 };
6560
6561 static const struct dis386 three_byte_table[][256] = {
6562
6563   /* THREE_BYTE_0F38 */
6564   {
6565     /* 00 */
6566     { "pshufb",         { MX, EM } },
6567     { "phaddw",         { MX, EM } },
6568     { "phaddd",         { MX, EM } },
6569     { "phaddsw",        { MX, EM } },
6570     { "pmaddubsw",      { MX, EM } },
6571     { "phsubw",         { MX, EM } },
6572     { "phsubd",         { MX, EM } },
6573     { "phsubsw",        { MX, EM } },
6574     /* 08 */
6575     { "psignb",         { MX, EM } },
6576     { "psignw",         { MX, EM } },
6577     { "psignd",         { MX, EM } },
6578     { "pmulhrsw",       { MX, EM } },
6579     { Bad_Opcode },
6580     { Bad_Opcode },
6581     { Bad_Opcode },
6582     { Bad_Opcode },
6583     /* 10 */
6584     { PREFIX_TABLE (PREFIX_0F3810) },
6585     { Bad_Opcode },
6586     { Bad_Opcode },
6587     { Bad_Opcode },
6588     { PREFIX_TABLE (PREFIX_0F3814) },
6589     { PREFIX_TABLE (PREFIX_0F3815) },
6590     { Bad_Opcode },
6591     { PREFIX_TABLE (PREFIX_0F3817) },
6592     /* 18 */
6593     { Bad_Opcode },
6594     { Bad_Opcode },
6595     { Bad_Opcode },
6596     { Bad_Opcode },
6597     { "pabsb",          { MX, EM } },
6598     { "pabsw",          { MX, EM } },
6599     { "pabsd",          { MX, EM } },
6600     { Bad_Opcode },
6601     /* 20 */
6602     { PREFIX_TABLE (PREFIX_0F3820) },
6603     { PREFIX_TABLE (PREFIX_0F3821) },
6604     { PREFIX_TABLE (PREFIX_0F3822) },
6605     { PREFIX_TABLE (PREFIX_0F3823) },
6606     { PREFIX_TABLE (PREFIX_0F3824) },
6607     { PREFIX_TABLE (PREFIX_0F3825) },
6608     { Bad_Opcode },
6609     { Bad_Opcode },
6610     /* 28 */
6611     { PREFIX_TABLE (PREFIX_0F3828) },
6612     { PREFIX_TABLE (PREFIX_0F3829) },
6613     { PREFIX_TABLE (PREFIX_0F382A) },
6614     { PREFIX_TABLE (PREFIX_0F382B) },
6615     { Bad_Opcode },
6616     { Bad_Opcode },
6617     { Bad_Opcode },
6618     { Bad_Opcode },
6619     /* 30 */
6620     { PREFIX_TABLE (PREFIX_0F3830) },
6621     { PREFIX_TABLE (PREFIX_0F3831) },
6622     { PREFIX_TABLE (PREFIX_0F3832) },
6623     { PREFIX_TABLE (PREFIX_0F3833) },
6624     { PREFIX_TABLE (PREFIX_0F3834) },
6625     { PREFIX_TABLE (PREFIX_0F3835) },
6626     { Bad_Opcode },
6627     { PREFIX_TABLE (PREFIX_0F3837) },
6628     /* 38 */
6629     { PREFIX_TABLE (PREFIX_0F3838) },
6630     { PREFIX_TABLE (PREFIX_0F3839) },
6631     { PREFIX_TABLE (PREFIX_0F383A) },
6632     { PREFIX_TABLE (PREFIX_0F383B) },
6633     { PREFIX_TABLE (PREFIX_0F383C) },
6634     { PREFIX_TABLE (PREFIX_0F383D) },
6635     { PREFIX_TABLE (PREFIX_0F383E) },
6636     { PREFIX_TABLE (PREFIX_0F383F) },
6637     /* 40 */
6638     { PREFIX_TABLE (PREFIX_0F3840) },
6639     { PREFIX_TABLE (PREFIX_0F3841) },
6640     { Bad_Opcode },
6641     { Bad_Opcode },
6642     { Bad_Opcode },
6643     { Bad_Opcode },
6644     { Bad_Opcode },
6645     { Bad_Opcode },
6646     /* 48 */
6647     { Bad_Opcode },
6648     { Bad_Opcode },
6649     { Bad_Opcode },
6650     { Bad_Opcode },
6651     { Bad_Opcode },
6652     { Bad_Opcode },
6653     { Bad_Opcode },
6654     { Bad_Opcode },
6655     /* 50 */
6656     { Bad_Opcode },
6657     { Bad_Opcode },
6658     { Bad_Opcode },
6659     { Bad_Opcode },
6660     { Bad_Opcode },
6661     { Bad_Opcode },
6662     { Bad_Opcode },
6663     { Bad_Opcode },
6664     /* 58 */
6665     { Bad_Opcode },
6666     { Bad_Opcode },
6667     { Bad_Opcode },
6668     { Bad_Opcode },
6669     { Bad_Opcode },
6670     { Bad_Opcode },
6671     { Bad_Opcode },
6672     { Bad_Opcode },
6673     /* 60 */
6674     { Bad_Opcode },
6675     { Bad_Opcode },
6676     { Bad_Opcode },
6677     { Bad_Opcode },
6678     { Bad_Opcode },
6679     { Bad_Opcode },
6680     { Bad_Opcode },
6681     { Bad_Opcode },
6682     /* 68 */
6683     { Bad_Opcode },
6684     { Bad_Opcode },
6685     { Bad_Opcode },
6686     { Bad_Opcode },
6687     { Bad_Opcode },
6688     { Bad_Opcode },
6689     { Bad_Opcode },
6690     { Bad_Opcode },
6691     /* 70 */
6692     { Bad_Opcode },
6693     { Bad_Opcode },
6694     { Bad_Opcode },
6695     { Bad_Opcode },
6696     { Bad_Opcode },
6697     { Bad_Opcode },
6698     { Bad_Opcode },
6699     { Bad_Opcode },
6700     /* 78 */
6701     { Bad_Opcode },
6702     { Bad_Opcode },
6703     { Bad_Opcode },
6704     { Bad_Opcode },
6705     { Bad_Opcode },
6706     { Bad_Opcode },
6707     { Bad_Opcode },
6708     { Bad_Opcode },
6709     /* 80 */
6710     { PREFIX_TABLE (PREFIX_0F3880) },
6711     { PREFIX_TABLE (PREFIX_0F3881) },
6712     { PREFIX_TABLE (PREFIX_0F3882) },
6713     { Bad_Opcode },
6714     { Bad_Opcode },
6715     { Bad_Opcode },
6716     { Bad_Opcode },
6717     { Bad_Opcode },
6718     /* 88 */
6719     { Bad_Opcode },
6720     { Bad_Opcode },
6721     { Bad_Opcode },
6722     { Bad_Opcode },
6723     { Bad_Opcode },
6724     { Bad_Opcode },
6725     { Bad_Opcode },
6726     { Bad_Opcode },
6727     /* 90 */
6728     { Bad_Opcode },
6729     { Bad_Opcode },
6730     { Bad_Opcode },
6731     { Bad_Opcode },
6732     { Bad_Opcode },
6733     { Bad_Opcode },
6734     { Bad_Opcode },
6735     { Bad_Opcode },
6736     /* 98 */
6737     { Bad_Opcode },
6738     { Bad_Opcode },
6739     { Bad_Opcode },
6740     { Bad_Opcode },
6741     { Bad_Opcode },
6742     { Bad_Opcode },
6743     { Bad_Opcode },
6744     { Bad_Opcode },
6745     /* a0 */
6746     { Bad_Opcode },
6747     { Bad_Opcode },
6748     { Bad_Opcode },
6749     { Bad_Opcode },
6750     { Bad_Opcode },
6751     { Bad_Opcode },
6752     { Bad_Opcode },
6753     { Bad_Opcode },
6754     /* a8 */
6755     { Bad_Opcode },
6756     { Bad_Opcode },
6757     { Bad_Opcode },
6758     { Bad_Opcode },
6759     { Bad_Opcode },
6760     { Bad_Opcode },
6761     { Bad_Opcode },
6762     { Bad_Opcode },
6763     /* b0 */
6764     { Bad_Opcode },
6765     { Bad_Opcode },
6766     { Bad_Opcode },
6767     { Bad_Opcode },
6768     { Bad_Opcode },
6769     { Bad_Opcode },
6770     { Bad_Opcode },
6771     { Bad_Opcode },
6772     /* b8 */
6773     { Bad_Opcode },
6774     { Bad_Opcode },
6775     { Bad_Opcode },
6776     { Bad_Opcode },
6777     { Bad_Opcode },
6778     { Bad_Opcode },
6779     { Bad_Opcode },
6780     { Bad_Opcode },
6781     /* c0 */
6782     { Bad_Opcode },
6783     { Bad_Opcode },
6784     { Bad_Opcode },
6785     { Bad_Opcode },
6786     { Bad_Opcode },
6787     { Bad_Opcode },
6788     { Bad_Opcode },
6789     { Bad_Opcode },
6790     /* c8 */
6791     { PREFIX_TABLE (PREFIX_0F38C8) },
6792     { PREFIX_TABLE (PREFIX_0F38C9) },
6793     { PREFIX_TABLE (PREFIX_0F38CA) },
6794     { PREFIX_TABLE (PREFIX_0F38CB) },
6795     { PREFIX_TABLE (PREFIX_0F38CC) },
6796     { PREFIX_TABLE (PREFIX_0F38CD) },
6797     { Bad_Opcode },
6798     { Bad_Opcode },
6799     /* d0 */
6800     { Bad_Opcode },
6801     { Bad_Opcode },
6802     { Bad_Opcode },
6803     { Bad_Opcode },
6804     { Bad_Opcode },
6805     { Bad_Opcode },
6806     { Bad_Opcode },
6807     { Bad_Opcode },
6808     /* d8 */
6809     { Bad_Opcode },
6810     { Bad_Opcode },
6811     { Bad_Opcode },
6812     { PREFIX_TABLE (PREFIX_0F38DB) },
6813     { PREFIX_TABLE (PREFIX_0F38DC) },
6814     { PREFIX_TABLE (PREFIX_0F38DD) },
6815     { PREFIX_TABLE (PREFIX_0F38DE) },
6816     { PREFIX_TABLE (PREFIX_0F38DF) },
6817     /* e0 */
6818     { Bad_Opcode },
6819     { Bad_Opcode },
6820     { Bad_Opcode },
6821     { Bad_Opcode },
6822     { Bad_Opcode },
6823     { Bad_Opcode },
6824     { Bad_Opcode },
6825     { Bad_Opcode },
6826     /* e8 */
6827     { Bad_Opcode },
6828     { Bad_Opcode },
6829     { Bad_Opcode },
6830     { Bad_Opcode },
6831     { Bad_Opcode },
6832     { Bad_Opcode },
6833     { Bad_Opcode },
6834     { Bad_Opcode },
6835     /* f0 */
6836     { PREFIX_TABLE (PREFIX_0F38F0) },
6837     { PREFIX_TABLE (PREFIX_0F38F1) },
6838     { Bad_Opcode },
6839     { Bad_Opcode },
6840     { Bad_Opcode },
6841     { Bad_Opcode },
6842     { PREFIX_TABLE (PREFIX_0F38F6) },
6843     { Bad_Opcode },
6844     /* f8 */
6845     { Bad_Opcode },
6846     { Bad_Opcode },
6847     { Bad_Opcode },
6848     { Bad_Opcode },
6849     { Bad_Opcode },
6850     { Bad_Opcode },
6851     { Bad_Opcode },
6852     { Bad_Opcode },
6853   },
6854   /* THREE_BYTE_0F3A */
6855   {
6856     /* 00 */
6857     { Bad_Opcode },
6858     { Bad_Opcode },
6859     { Bad_Opcode },
6860     { Bad_Opcode },
6861     { Bad_Opcode },
6862     { Bad_Opcode },
6863     { Bad_Opcode },
6864     { Bad_Opcode },
6865     /* 08 */
6866     { PREFIX_TABLE (PREFIX_0F3A08) },
6867     { PREFIX_TABLE (PREFIX_0F3A09) },
6868     { PREFIX_TABLE (PREFIX_0F3A0A) },
6869     { PREFIX_TABLE (PREFIX_0F3A0B) },
6870     { PREFIX_TABLE (PREFIX_0F3A0C) },
6871     { PREFIX_TABLE (PREFIX_0F3A0D) },
6872     { PREFIX_TABLE (PREFIX_0F3A0E) },
6873     { "palignr",        { MX, EM, Ib } },
6874     /* 10 */
6875     { Bad_Opcode },
6876     { Bad_Opcode },
6877     { Bad_Opcode },
6878     { Bad_Opcode },
6879     { PREFIX_TABLE (PREFIX_0F3A14) },
6880     { PREFIX_TABLE (PREFIX_0F3A15) },
6881     { PREFIX_TABLE (PREFIX_0F3A16) },
6882     { PREFIX_TABLE (PREFIX_0F3A17) },
6883     /* 18 */
6884     { Bad_Opcode },
6885     { Bad_Opcode },
6886     { Bad_Opcode },
6887     { Bad_Opcode },
6888     { Bad_Opcode },
6889     { Bad_Opcode },
6890     { Bad_Opcode },
6891     { Bad_Opcode },
6892     /* 20 */
6893     { PREFIX_TABLE (PREFIX_0F3A20) },
6894     { PREFIX_TABLE (PREFIX_0F3A21) },
6895     { PREFIX_TABLE (PREFIX_0F3A22) },
6896     { Bad_Opcode },
6897     { Bad_Opcode },
6898     { Bad_Opcode },
6899     { Bad_Opcode },
6900     { Bad_Opcode },
6901     /* 28 */
6902     { Bad_Opcode },
6903     { Bad_Opcode },
6904     { Bad_Opcode },
6905     { Bad_Opcode },
6906     { Bad_Opcode },
6907     { Bad_Opcode },
6908     { Bad_Opcode },
6909     { Bad_Opcode },
6910     /* 30 */
6911     { Bad_Opcode },
6912     { Bad_Opcode },
6913     { Bad_Opcode },
6914     { Bad_Opcode },
6915     { Bad_Opcode },
6916     { Bad_Opcode },
6917     { Bad_Opcode },
6918     { Bad_Opcode },
6919     /* 38 */
6920     { Bad_Opcode },
6921     { Bad_Opcode },
6922     { Bad_Opcode },
6923     { Bad_Opcode },
6924     { Bad_Opcode },
6925     { Bad_Opcode },
6926     { Bad_Opcode },
6927     { Bad_Opcode },
6928     /* 40 */
6929     { PREFIX_TABLE (PREFIX_0F3A40) },
6930     { PREFIX_TABLE (PREFIX_0F3A41) },
6931     { PREFIX_TABLE (PREFIX_0F3A42) },
6932     { Bad_Opcode },
6933     { PREFIX_TABLE (PREFIX_0F3A44) },
6934     { Bad_Opcode },
6935     { Bad_Opcode },
6936     { Bad_Opcode },
6937     /* 48 */
6938     { Bad_Opcode },
6939     { Bad_Opcode },
6940     { Bad_Opcode },
6941     { Bad_Opcode },
6942     { Bad_Opcode },
6943     { Bad_Opcode },
6944     { Bad_Opcode },
6945     { Bad_Opcode },
6946     /* 50 */
6947     { Bad_Opcode },
6948     { Bad_Opcode },
6949     { Bad_Opcode },
6950     { Bad_Opcode },
6951     { Bad_Opcode },
6952     { Bad_Opcode },
6953     { Bad_Opcode },
6954     { Bad_Opcode },
6955     /* 58 */
6956     { Bad_Opcode },
6957     { Bad_Opcode },
6958     { Bad_Opcode },
6959     { Bad_Opcode },
6960     { Bad_Opcode },
6961     { Bad_Opcode },
6962     { Bad_Opcode },
6963     { Bad_Opcode },
6964     /* 60 */
6965     { PREFIX_TABLE (PREFIX_0F3A60) },
6966     { PREFIX_TABLE (PREFIX_0F3A61) },
6967     { PREFIX_TABLE (PREFIX_0F3A62) },
6968     { PREFIX_TABLE (PREFIX_0F3A63) },
6969     { Bad_Opcode },
6970     { Bad_Opcode },
6971     { Bad_Opcode },
6972     { Bad_Opcode },
6973     /* 68 */
6974     { Bad_Opcode },
6975     { Bad_Opcode },
6976     { Bad_Opcode },
6977     { Bad_Opcode },
6978     { Bad_Opcode },
6979     { Bad_Opcode },
6980     { Bad_Opcode },
6981     { Bad_Opcode },
6982     /* 70 */
6983     { Bad_Opcode },
6984     { Bad_Opcode },
6985     { Bad_Opcode },
6986     { Bad_Opcode },
6987     { Bad_Opcode },
6988     { Bad_Opcode },
6989     { Bad_Opcode },
6990     { Bad_Opcode },
6991     /* 78 */
6992     { Bad_Opcode },
6993     { Bad_Opcode },
6994     { Bad_Opcode },
6995     { Bad_Opcode },
6996     { Bad_Opcode },
6997     { Bad_Opcode },
6998     { Bad_Opcode },
6999     { Bad_Opcode },
7000     /* 80 */
7001     { Bad_Opcode },
7002     { Bad_Opcode },
7003     { Bad_Opcode },
7004     { Bad_Opcode },
7005     { Bad_Opcode },
7006     { Bad_Opcode },
7007     { Bad_Opcode },
7008     { Bad_Opcode },
7009     /* 88 */
7010     { Bad_Opcode },
7011     { Bad_Opcode },
7012     { Bad_Opcode },
7013     { Bad_Opcode },
7014     { Bad_Opcode },
7015     { Bad_Opcode },
7016     { Bad_Opcode },
7017     { Bad_Opcode },
7018     /* 90 */
7019     { Bad_Opcode },
7020     { Bad_Opcode },
7021     { Bad_Opcode },
7022     { Bad_Opcode },
7023     { Bad_Opcode },
7024     { Bad_Opcode },
7025     { Bad_Opcode },
7026     { Bad_Opcode },
7027     /* 98 */
7028     { Bad_Opcode },
7029     { Bad_Opcode },
7030     { Bad_Opcode },
7031     { Bad_Opcode },
7032     { Bad_Opcode },
7033     { Bad_Opcode },
7034     { Bad_Opcode },
7035     { Bad_Opcode },
7036     /* a0 */
7037     { Bad_Opcode },
7038     { Bad_Opcode },
7039     { Bad_Opcode },
7040     { Bad_Opcode },
7041     { Bad_Opcode },
7042     { Bad_Opcode },
7043     { Bad_Opcode },
7044     { Bad_Opcode },
7045     /* a8 */
7046     { Bad_Opcode },
7047     { Bad_Opcode },
7048     { Bad_Opcode },
7049     { Bad_Opcode },
7050     { Bad_Opcode },
7051     { Bad_Opcode },
7052     { Bad_Opcode },
7053     { Bad_Opcode },
7054     /* b0 */
7055     { Bad_Opcode },
7056     { Bad_Opcode },
7057     { Bad_Opcode },
7058     { Bad_Opcode },
7059     { Bad_Opcode },
7060     { Bad_Opcode },
7061     { Bad_Opcode },
7062     { Bad_Opcode },
7063     /* b8 */
7064     { Bad_Opcode },
7065     { Bad_Opcode },
7066     { Bad_Opcode },
7067     { Bad_Opcode },
7068     { Bad_Opcode },
7069     { Bad_Opcode },
7070     { Bad_Opcode },
7071     { Bad_Opcode },
7072     /* c0 */
7073     { Bad_Opcode },
7074     { Bad_Opcode },
7075     { Bad_Opcode },
7076     { Bad_Opcode },
7077     { Bad_Opcode },
7078     { Bad_Opcode },
7079     { Bad_Opcode },
7080     { Bad_Opcode },
7081     /* c8 */
7082     { Bad_Opcode },
7083     { Bad_Opcode },
7084     { Bad_Opcode },
7085     { Bad_Opcode },
7086     { PREFIX_TABLE (PREFIX_0F3ACC) },
7087     { Bad_Opcode },
7088     { Bad_Opcode },
7089     { Bad_Opcode },
7090     /* d0 */
7091     { Bad_Opcode },
7092     { Bad_Opcode },
7093     { Bad_Opcode },
7094     { Bad_Opcode },
7095     { Bad_Opcode },
7096     { Bad_Opcode },
7097     { Bad_Opcode },
7098     { Bad_Opcode },
7099     /* d8 */
7100     { Bad_Opcode },
7101     { Bad_Opcode },
7102     { Bad_Opcode },
7103     { Bad_Opcode },
7104     { Bad_Opcode },
7105     { Bad_Opcode },
7106     { Bad_Opcode },
7107     { PREFIX_TABLE (PREFIX_0F3ADF) },
7108     /* e0 */
7109     { Bad_Opcode },
7110     { Bad_Opcode },
7111     { Bad_Opcode },
7112     { Bad_Opcode },
7113     { Bad_Opcode },
7114     { Bad_Opcode },
7115     { Bad_Opcode },
7116     { Bad_Opcode },
7117     /* e8 */
7118     { Bad_Opcode },
7119     { Bad_Opcode },
7120     { Bad_Opcode },
7121     { Bad_Opcode },
7122     { Bad_Opcode },
7123     { Bad_Opcode },
7124     { Bad_Opcode },
7125     { Bad_Opcode },
7126     /* f0 */
7127     { Bad_Opcode },
7128     { Bad_Opcode },
7129     { Bad_Opcode },
7130     { Bad_Opcode },
7131     { Bad_Opcode },
7132     { Bad_Opcode },
7133     { Bad_Opcode },
7134     { Bad_Opcode },
7135     /* f8 */
7136     { Bad_Opcode },
7137     { Bad_Opcode },
7138     { Bad_Opcode },
7139     { Bad_Opcode },
7140     { Bad_Opcode },
7141     { Bad_Opcode },
7142     { Bad_Opcode },
7143     { Bad_Opcode },
7144   },
7145
7146   /* THREE_BYTE_0F7A */
7147   {
7148     /* 00 */
7149     { Bad_Opcode },
7150     { Bad_Opcode },
7151     { Bad_Opcode },
7152     { Bad_Opcode },
7153     { Bad_Opcode },
7154     { Bad_Opcode },
7155     { Bad_Opcode },
7156     { Bad_Opcode },
7157     /* 08 */
7158     { Bad_Opcode },
7159     { Bad_Opcode },
7160     { Bad_Opcode },
7161     { Bad_Opcode },
7162     { Bad_Opcode },
7163     { Bad_Opcode },
7164     { Bad_Opcode },
7165     { Bad_Opcode },
7166     /* 10 */
7167     { Bad_Opcode },
7168     { Bad_Opcode },
7169     { Bad_Opcode },
7170     { Bad_Opcode },
7171     { Bad_Opcode },
7172     { Bad_Opcode },
7173     { Bad_Opcode },
7174     { Bad_Opcode },
7175     /* 18 */
7176     { Bad_Opcode },
7177     { Bad_Opcode },
7178     { Bad_Opcode },
7179     { Bad_Opcode },
7180     { Bad_Opcode },
7181     { Bad_Opcode },
7182     { Bad_Opcode },
7183     { Bad_Opcode },
7184     /* 20 */
7185     { "ptest",          { XX } },
7186     { Bad_Opcode },
7187     { Bad_Opcode },
7188     { Bad_Opcode },
7189     { Bad_Opcode },
7190     { Bad_Opcode },
7191     { Bad_Opcode },
7192     { Bad_Opcode },
7193     /* 28 */
7194     { Bad_Opcode },
7195     { Bad_Opcode },
7196     { Bad_Opcode },
7197     { Bad_Opcode },
7198     { Bad_Opcode },
7199     { Bad_Opcode },
7200     { Bad_Opcode },
7201     { Bad_Opcode },
7202     /* 30 */
7203     { Bad_Opcode },
7204     { Bad_Opcode },
7205     { Bad_Opcode },
7206     { Bad_Opcode },
7207     { Bad_Opcode },
7208     { Bad_Opcode },
7209     { Bad_Opcode },
7210     { Bad_Opcode },
7211     /* 38 */
7212     { Bad_Opcode },
7213     { Bad_Opcode },
7214     { Bad_Opcode },
7215     { Bad_Opcode },
7216     { Bad_Opcode },
7217     { Bad_Opcode },
7218     { Bad_Opcode },
7219     { Bad_Opcode },
7220     /* 40 */
7221     { Bad_Opcode },
7222     { "phaddbw",        { XM, EXq } },
7223     { "phaddbd",        { XM, EXq } },
7224     { "phaddbq",        { XM, EXq } },
7225     { Bad_Opcode },
7226     { Bad_Opcode },
7227     { "phaddwd",        { XM, EXq } },
7228     { "phaddwq",        { XM, EXq } },
7229     /* 48 */
7230     { Bad_Opcode },
7231     { Bad_Opcode },
7232     { Bad_Opcode },
7233     { "phadddq",        { XM, EXq } },
7234     { Bad_Opcode },
7235     { Bad_Opcode },
7236     { Bad_Opcode },
7237     { Bad_Opcode },
7238     /* 50 */
7239     { Bad_Opcode },
7240     { "phaddubw",       { XM, EXq } },
7241     { "phaddubd",       { XM, EXq } },
7242     { "phaddubq",       { XM, EXq } },
7243     { Bad_Opcode },
7244     { Bad_Opcode },
7245     { "phadduwd",       { XM, EXq } },
7246     { "phadduwq",       { XM, EXq } },
7247     /* 58 */
7248     { Bad_Opcode },
7249     { Bad_Opcode },
7250     { Bad_Opcode },
7251     { "phaddudq",       { XM, EXq } },
7252     { Bad_Opcode },
7253     { Bad_Opcode },
7254     { Bad_Opcode },
7255     { Bad_Opcode },
7256     /* 60 */
7257     { Bad_Opcode },
7258     { "phsubbw",        { XM, EXq } },
7259     { "phsubbd",        { XM, EXq } },
7260     { "phsubbq",        { XM, EXq } },
7261     { Bad_Opcode },
7262     { Bad_Opcode },
7263     { Bad_Opcode },
7264     { Bad_Opcode },
7265     /* 68 */
7266     { Bad_Opcode },
7267     { Bad_Opcode },
7268     { Bad_Opcode },
7269     { Bad_Opcode },
7270     { Bad_Opcode },
7271     { Bad_Opcode },
7272     { Bad_Opcode },
7273     { Bad_Opcode },
7274     /* 70 */
7275     { Bad_Opcode },
7276     { Bad_Opcode },
7277     { Bad_Opcode },
7278     { Bad_Opcode },
7279     { Bad_Opcode },
7280     { Bad_Opcode },
7281     { Bad_Opcode },
7282     { Bad_Opcode },
7283     /* 78 */
7284     { Bad_Opcode },
7285     { Bad_Opcode },
7286     { Bad_Opcode },
7287     { Bad_Opcode },
7288     { Bad_Opcode },
7289     { Bad_Opcode },
7290     { Bad_Opcode },
7291     { Bad_Opcode },
7292     /* 80 */
7293     { Bad_Opcode },
7294     { Bad_Opcode },
7295     { Bad_Opcode },
7296     { Bad_Opcode },
7297     { Bad_Opcode },
7298     { Bad_Opcode },
7299     { Bad_Opcode },
7300     { Bad_Opcode },
7301     /* 88 */
7302     { Bad_Opcode },
7303     { Bad_Opcode },
7304     { Bad_Opcode },
7305     { Bad_Opcode },
7306     { Bad_Opcode },
7307     { Bad_Opcode },
7308     { Bad_Opcode },
7309     { Bad_Opcode },
7310     /* 90 */
7311     { Bad_Opcode },
7312     { Bad_Opcode },
7313     { Bad_Opcode },
7314     { Bad_Opcode },
7315     { Bad_Opcode },
7316     { Bad_Opcode },
7317     { Bad_Opcode },
7318     { Bad_Opcode },
7319     /* 98 */
7320     { Bad_Opcode },
7321     { Bad_Opcode },
7322     { Bad_Opcode },
7323     { Bad_Opcode },
7324     { Bad_Opcode },
7325     { Bad_Opcode },
7326     { Bad_Opcode },
7327     { Bad_Opcode },
7328     /* a0 */
7329     { Bad_Opcode },
7330     { Bad_Opcode },
7331     { Bad_Opcode },
7332     { Bad_Opcode },
7333     { Bad_Opcode },
7334     { Bad_Opcode },
7335     { Bad_Opcode },
7336     { Bad_Opcode },
7337     /* a8 */
7338     { Bad_Opcode },
7339     { Bad_Opcode },
7340     { Bad_Opcode },
7341     { Bad_Opcode },
7342     { Bad_Opcode },
7343     { Bad_Opcode },
7344     { Bad_Opcode },
7345     { Bad_Opcode },
7346     /* b0 */
7347     { Bad_Opcode },
7348     { Bad_Opcode },
7349     { Bad_Opcode },
7350     { Bad_Opcode },
7351     { Bad_Opcode },
7352     { Bad_Opcode },
7353     { Bad_Opcode },
7354     { Bad_Opcode },
7355     /* b8 */
7356     { Bad_Opcode },
7357     { Bad_Opcode },
7358     { Bad_Opcode },
7359     { Bad_Opcode },
7360     { Bad_Opcode },
7361     { Bad_Opcode },
7362     { Bad_Opcode },
7363     { Bad_Opcode },
7364     /* c0 */
7365     { Bad_Opcode },
7366     { Bad_Opcode },
7367     { Bad_Opcode },
7368     { Bad_Opcode },
7369     { Bad_Opcode },
7370     { Bad_Opcode },
7371     { Bad_Opcode },
7372     { Bad_Opcode },
7373     /* c8 */
7374     { Bad_Opcode },
7375     { Bad_Opcode },
7376     { Bad_Opcode },
7377     { Bad_Opcode },
7378     { Bad_Opcode },
7379     { Bad_Opcode },
7380     { Bad_Opcode },
7381     { Bad_Opcode },
7382     /* d0 */
7383     { Bad_Opcode },
7384     { Bad_Opcode },
7385     { Bad_Opcode },
7386     { Bad_Opcode },
7387     { Bad_Opcode },
7388     { Bad_Opcode },
7389     { Bad_Opcode },
7390     { Bad_Opcode },
7391     /* d8 */
7392     { Bad_Opcode },
7393     { Bad_Opcode },
7394     { Bad_Opcode },
7395     { Bad_Opcode },
7396     { Bad_Opcode },
7397     { Bad_Opcode },
7398     { Bad_Opcode },
7399     { Bad_Opcode },
7400     /* e0 */
7401     { Bad_Opcode },
7402     { Bad_Opcode },
7403     { Bad_Opcode },
7404     { Bad_Opcode },
7405     { Bad_Opcode },
7406     { Bad_Opcode },
7407     { Bad_Opcode },
7408     { Bad_Opcode },
7409     /* e8 */
7410     { Bad_Opcode },
7411     { Bad_Opcode },
7412     { Bad_Opcode },
7413     { Bad_Opcode },
7414     { Bad_Opcode },
7415     { Bad_Opcode },
7416     { Bad_Opcode },
7417     { Bad_Opcode },
7418     /* f0 */
7419     { Bad_Opcode },
7420     { Bad_Opcode },
7421     { Bad_Opcode },
7422     { Bad_Opcode },
7423     { Bad_Opcode },
7424     { Bad_Opcode },
7425     { Bad_Opcode },
7426     { Bad_Opcode },
7427     /* f8 */
7428     { Bad_Opcode },
7429     { Bad_Opcode },
7430     { Bad_Opcode },
7431     { Bad_Opcode },
7432     { Bad_Opcode },
7433     { Bad_Opcode },
7434     { Bad_Opcode },
7435     { Bad_Opcode },
7436   },
7437 };
7438
7439 static const struct dis386 xop_table[][256] = {
7440   /* XOP_08 */
7441   {
7442     /* 00 */
7443     { Bad_Opcode },
7444     { Bad_Opcode },
7445     { Bad_Opcode },
7446     { Bad_Opcode },
7447     { Bad_Opcode },
7448     { Bad_Opcode },
7449     { Bad_Opcode },
7450     { Bad_Opcode },
7451     /* 08 */
7452     { Bad_Opcode },
7453     { Bad_Opcode },
7454     { Bad_Opcode },
7455     { Bad_Opcode },
7456     { Bad_Opcode },
7457     { Bad_Opcode },
7458     { Bad_Opcode },
7459     { Bad_Opcode },
7460     /* 10 */
7461     { Bad_Opcode },
7462     { Bad_Opcode },
7463     { Bad_Opcode },
7464     { Bad_Opcode },
7465     { Bad_Opcode },
7466     { Bad_Opcode },
7467     { Bad_Opcode },
7468     { Bad_Opcode },
7469     /* 18 */
7470     { Bad_Opcode },
7471     { Bad_Opcode },
7472     { Bad_Opcode },
7473     { Bad_Opcode },
7474     { Bad_Opcode },
7475     { Bad_Opcode },
7476     { Bad_Opcode },
7477     { Bad_Opcode },
7478     /* 20 */
7479     { Bad_Opcode },
7480     { Bad_Opcode },
7481     { Bad_Opcode },
7482     { Bad_Opcode },
7483     { Bad_Opcode },
7484     { Bad_Opcode },
7485     { Bad_Opcode },
7486     { Bad_Opcode },
7487     /* 28 */
7488     { Bad_Opcode },
7489     { Bad_Opcode },
7490     { Bad_Opcode },
7491     { Bad_Opcode },
7492     { Bad_Opcode },
7493     { Bad_Opcode },
7494     { Bad_Opcode },
7495     { Bad_Opcode },
7496     /* 30 */
7497     { Bad_Opcode },
7498     { Bad_Opcode },
7499     { Bad_Opcode },
7500     { Bad_Opcode },
7501     { Bad_Opcode },
7502     { Bad_Opcode },
7503     { Bad_Opcode },
7504     { Bad_Opcode },
7505     /* 38 */
7506     { Bad_Opcode },
7507     { Bad_Opcode },
7508     { Bad_Opcode },
7509     { Bad_Opcode },
7510     { Bad_Opcode },
7511     { Bad_Opcode },
7512     { Bad_Opcode },
7513     { Bad_Opcode },
7514     /* 40 */
7515     { Bad_Opcode },
7516     { Bad_Opcode },
7517     { Bad_Opcode },
7518     { Bad_Opcode },
7519     { Bad_Opcode },
7520     { Bad_Opcode },
7521     { Bad_Opcode },
7522     { Bad_Opcode },
7523     /* 48 */
7524     { Bad_Opcode },
7525     { Bad_Opcode },
7526     { Bad_Opcode },
7527     { Bad_Opcode },
7528     { Bad_Opcode },
7529     { Bad_Opcode },
7530     { Bad_Opcode },
7531     { Bad_Opcode },
7532     /* 50 */
7533     { Bad_Opcode },
7534     { Bad_Opcode },
7535     { Bad_Opcode },
7536     { Bad_Opcode },
7537     { Bad_Opcode },
7538     { Bad_Opcode },
7539     { Bad_Opcode },
7540     { Bad_Opcode },
7541     /* 58 */
7542     { Bad_Opcode },
7543     { Bad_Opcode },
7544     { Bad_Opcode },
7545     { Bad_Opcode },
7546     { Bad_Opcode },
7547     { Bad_Opcode },
7548     { Bad_Opcode },
7549     { Bad_Opcode },
7550     /* 60 */
7551     { Bad_Opcode },
7552     { Bad_Opcode },
7553     { Bad_Opcode },
7554     { Bad_Opcode },
7555     { Bad_Opcode },
7556     { Bad_Opcode },
7557     { Bad_Opcode },
7558     { Bad_Opcode },
7559     /* 68 */
7560     { Bad_Opcode },
7561     { Bad_Opcode },
7562     { Bad_Opcode },
7563     { Bad_Opcode },
7564     { Bad_Opcode },
7565     { Bad_Opcode },
7566     { Bad_Opcode },
7567     { Bad_Opcode },
7568     /* 70 */
7569     { Bad_Opcode },
7570     { Bad_Opcode },
7571     { Bad_Opcode },
7572     { Bad_Opcode },
7573     { Bad_Opcode },
7574     { Bad_Opcode },
7575     { Bad_Opcode },
7576     { Bad_Opcode },
7577     /* 78 */
7578     { Bad_Opcode },
7579     { Bad_Opcode },
7580     { Bad_Opcode },
7581     { Bad_Opcode },
7582     { Bad_Opcode },
7583     { Bad_Opcode },
7584     { Bad_Opcode },
7585     { Bad_Opcode },
7586     /* 80 */
7587     { Bad_Opcode },
7588     { Bad_Opcode },
7589     { Bad_Opcode },
7590     { Bad_Opcode },
7591     { Bad_Opcode },
7592     { "vpmacssww",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7593     { "vpmacsswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7594     { "vpmacssdql",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7595     /* 88 */
7596     { Bad_Opcode },
7597     { Bad_Opcode },
7598     { Bad_Opcode },
7599     { Bad_Opcode },
7600     { Bad_Opcode },
7601     { Bad_Opcode },
7602     { "vpmacssdd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7603     { "vpmacssdqh",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7604     /* 90 */
7605     { Bad_Opcode },
7606     { Bad_Opcode },
7607     { Bad_Opcode },
7608     { Bad_Opcode },
7609     { Bad_Opcode },
7610     { "vpmacsww",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7611     { "vpmacswd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7612     { "vpmacsdql",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7613     /* 98 */
7614     { Bad_Opcode },
7615     { Bad_Opcode },
7616     { Bad_Opcode },
7617     { Bad_Opcode },
7618     { Bad_Opcode },
7619     { Bad_Opcode },
7620     { "vpmacsdd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7621     { "vpmacsdqh",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7622     /* a0 */
7623     { Bad_Opcode },
7624     { Bad_Opcode },
7625     { "vpcmov",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7626     { "vpperm",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7627     { Bad_Opcode },
7628     { Bad_Opcode },
7629     { "vpmadcsswd",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7630     { Bad_Opcode },
7631     /* a8 */
7632     { Bad_Opcode },
7633     { Bad_Opcode },
7634     { Bad_Opcode },
7635     { Bad_Opcode },
7636     { Bad_Opcode },
7637     { Bad_Opcode },
7638     { Bad_Opcode },
7639     { Bad_Opcode },
7640     /* b0 */
7641     { Bad_Opcode },
7642     { Bad_Opcode },
7643     { Bad_Opcode },
7644     { Bad_Opcode },
7645     { Bad_Opcode },
7646     { Bad_Opcode },
7647     { "vpmadcswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7648     { Bad_Opcode },
7649     /* b8 */
7650     { Bad_Opcode },
7651     { Bad_Opcode },
7652     { Bad_Opcode },
7653     { Bad_Opcode },
7654     { Bad_Opcode },
7655     { Bad_Opcode },
7656     { Bad_Opcode },
7657     { Bad_Opcode },
7658     /* c0 */
7659     { "vprotb",         { XM, Vex_2src_1, Ib } },
7660     { "vprotw",         { XM, Vex_2src_1, Ib } },
7661     { "vprotd",         { XM, Vex_2src_1, Ib } },
7662     { "vprotq",         { XM, Vex_2src_1, Ib } },
7663     { Bad_Opcode },
7664     { Bad_Opcode },
7665     { Bad_Opcode },
7666     { Bad_Opcode },
7667     /* c8 */
7668     { Bad_Opcode },
7669     { Bad_Opcode },
7670     { Bad_Opcode },
7671     { Bad_Opcode },
7672     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
7673     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
7674     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
7675     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
7676     /* d0 */
7677     { Bad_Opcode },
7678     { Bad_Opcode },
7679     { Bad_Opcode },
7680     { Bad_Opcode },
7681     { Bad_Opcode },
7682     { Bad_Opcode },
7683     { Bad_Opcode },
7684     { Bad_Opcode },
7685     /* d8 */
7686     { Bad_Opcode },
7687     { Bad_Opcode },
7688     { Bad_Opcode },
7689     { Bad_Opcode },
7690     { Bad_Opcode },
7691     { Bad_Opcode },
7692     { Bad_Opcode },
7693     { Bad_Opcode },
7694     /* e0 */
7695     { Bad_Opcode },
7696     { Bad_Opcode },
7697     { Bad_Opcode },
7698     { Bad_Opcode },
7699     { Bad_Opcode },
7700     { Bad_Opcode },
7701     { Bad_Opcode },
7702     { Bad_Opcode },
7703     /* e8 */
7704     { Bad_Opcode },
7705     { Bad_Opcode },
7706     { Bad_Opcode },
7707     { Bad_Opcode },
7708     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
7709     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
7710     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
7711     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
7712     /* f0 */
7713     { Bad_Opcode },
7714     { Bad_Opcode },
7715     { Bad_Opcode },
7716     { Bad_Opcode },
7717     { Bad_Opcode },
7718     { Bad_Opcode },
7719     { Bad_Opcode },
7720     { Bad_Opcode },
7721     /* f8 */
7722     { Bad_Opcode },
7723     { Bad_Opcode },
7724     { Bad_Opcode },
7725     { Bad_Opcode },
7726     { Bad_Opcode },
7727     { Bad_Opcode },
7728     { Bad_Opcode },
7729     { Bad_Opcode },
7730   },
7731   /* XOP_09 */
7732   {
7733     /* 00 */
7734     { Bad_Opcode },
7735     { REG_TABLE (REG_XOP_TBM_01) },
7736     { REG_TABLE (REG_XOP_TBM_02) },
7737     { Bad_Opcode },
7738     { Bad_Opcode },
7739     { Bad_Opcode },
7740     { Bad_Opcode },
7741     { Bad_Opcode },
7742     /* 08 */
7743     { Bad_Opcode },
7744     { Bad_Opcode },
7745     { Bad_Opcode },
7746     { Bad_Opcode },
7747     { Bad_Opcode },
7748     { Bad_Opcode },
7749     { Bad_Opcode },
7750     { Bad_Opcode },
7751     /* 10 */
7752     { Bad_Opcode },
7753     { Bad_Opcode },
7754     { REG_TABLE (REG_XOP_LWPCB) },
7755     { Bad_Opcode },
7756     { Bad_Opcode },
7757     { Bad_Opcode },
7758     { Bad_Opcode },
7759     { Bad_Opcode },
7760     /* 18 */
7761     { Bad_Opcode },
7762     { Bad_Opcode },
7763     { Bad_Opcode },
7764     { Bad_Opcode },
7765     { Bad_Opcode },
7766     { Bad_Opcode },
7767     { Bad_Opcode },
7768     { Bad_Opcode },
7769     /* 20 */
7770     { Bad_Opcode },
7771     { Bad_Opcode },
7772     { Bad_Opcode },
7773     { Bad_Opcode },
7774     { Bad_Opcode },
7775     { Bad_Opcode },
7776     { Bad_Opcode },
7777     { Bad_Opcode },
7778     /* 28 */
7779     { Bad_Opcode },
7780     { Bad_Opcode },
7781     { Bad_Opcode },
7782     { Bad_Opcode },
7783     { Bad_Opcode },
7784     { Bad_Opcode },
7785     { Bad_Opcode },
7786     { Bad_Opcode },
7787     /* 30 */
7788     { Bad_Opcode },
7789     { Bad_Opcode },
7790     { Bad_Opcode },
7791     { Bad_Opcode },
7792     { Bad_Opcode },
7793     { Bad_Opcode },
7794     { Bad_Opcode },
7795     { Bad_Opcode },
7796     /* 38 */
7797     { Bad_Opcode },
7798     { Bad_Opcode },
7799     { Bad_Opcode },
7800     { Bad_Opcode },
7801     { Bad_Opcode },
7802     { Bad_Opcode },
7803     { Bad_Opcode },
7804     { Bad_Opcode },
7805     /* 40 */
7806     { Bad_Opcode },
7807     { Bad_Opcode },
7808     { Bad_Opcode },
7809     { Bad_Opcode },
7810     { Bad_Opcode },
7811     { Bad_Opcode },
7812     { Bad_Opcode },
7813     { Bad_Opcode },
7814     /* 48 */
7815     { Bad_Opcode },
7816     { Bad_Opcode },
7817     { Bad_Opcode },
7818     { Bad_Opcode },
7819     { Bad_Opcode },
7820     { Bad_Opcode },
7821     { Bad_Opcode },
7822     { Bad_Opcode },
7823     /* 50 */
7824     { Bad_Opcode },
7825     { Bad_Opcode },
7826     { Bad_Opcode },
7827     { Bad_Opcode },
7828     { Bad_Opcode },
7829     { Bad_Opcode },
7830     { Bad_Opcode },
7831     { Bad_Opcode },
7832     /* 58 */
7833     { Bad_Opcode },
7834     { Bad_Opcode },
7835     { Bad_Opcode },
7836     { Bad_Opcode },
7837     { Bad_Opcode },
7838     { Bad_Opcode },
7839     { Bad_Opcode },
7840     { Bad_Opcode },
7841     /* 60 */
7842     { Bad_Opcode },
7843     { Bad_Opcode },
7844     { Bad_Opcode },
7845     { Bad_Opcode },
7846     { Bad_Opcode },
7847     { Bad_Opcode },
7848     { Bad_Opcode },
7849     { Bad_Opcode },
7850     /* 68 */
7851     { Bad_Opcode },
7852     { Bad_Opcode },
7853     { Bad_Opcode },
7854     { Bad_Opcode },
7855     { Bad_Opcode },
7856     { Bad_Opcode },
7857     { Bad_Opcode },
7858     { Bad_Opcode },
7859     /* 70 */
7860     { Bad_Opcode },
7861     { Bad_Opcode },
7862     { Bad_Opcode },
7863     { Bad_Opcode },
7864     { Bad_Opcode },
7865     { Bad_Opcode },
7866     { Bad_Opcode },
7867     { Bad_Opcode },
7868     /* 78 */
7869     { Bad_Opcode },
7870     { Bad_Opcode },
7871     { Bad_Opcode },
7872     { Bad_Opcode },
7873     { Bad_Opcode },
7874     { Bad_Opcode },
7875     { Bad_Opcode },
7876     { Bad_Opcode },
7877     /* 80 */
7878     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
7879     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
7880     { "vfrczss",        { XM, EXd } },
7881     { "vfrczsd",        { XM, EXq } },
7882     { Bad_Opcode },
7883     { Bad_Opcode },
7884     { Bad_Opcode },
7885     { Bad_Opcode },
7886     /* 88 */
7887     { Bad_Opcode },
7888     { Bad_Opcode },
7889     { Bad_Opcode },
7890     { Bad_Opcode },
7891     { Bad_Opcode },
7892     { Bad_Opcode },
7893     { Bad_Opcode },
7894     { Bad_Opcode },
7895     /* 90 */
7896     { "vprotb",         { XM, Vex_2src_1, Vex_2src_2 } },
7897     { "vprotw",         { XM, Vex_2src_1, Vex_2src_2 } },
7898     { "vprotd",         { XM, Vex_2src_1, Vex_2src_2 } },
7899     { "vprotq",         { XM, Vex_2src_1, Vex_2src_2 } },
7900     { "vpshlb",         { XM, Vex_2src_1, Vex_2src_2 } },
7901     { "vpshlw",         { XM, Vex_2src_1, Vex_2src_2 } },
7902     { "vpshld",         { XM, Vex_2src_1, Vex_2src_2 } },
7903     { "vpshlq",         { XM, Vex_2src_1, Vex_2src_2 } },
7904     /* 98 */
7905     { "vpshab",         { XM, Vex_2src_1, Vex_2src_2 } },
7906     { "vpshaw",         { XM, Vex_2src_1, Vex_2src_2 } },
7907     { "vpshad",         { XM, Vex_2src_1, Vex_2src_2 } },
7908     { "vpshaq",         { XM, Vex_2src_1, Vex_2src_2 } },
7909     { Bad_Opcode },
7910     { Bad_Opcode },
7911     { Bad_Opcode },
7912     { Bad_Opcode },
7913     /* a0 */
7914     { Bad_Opcode },
7915     { Bad_Opcode },
7916     { Bad_Opcode },
7917     { Bad_Opcode },
7918     { Bad_Opcode },
7919     { Bad_Opcode },
7920     { Bad_Opcode },
7921     { Bad_Opcode },
7922     /* a8 */
7923     { Bad_Opcode },
7924     { Bad_Opcode },
7925     { Bad_Opcode },
7926     { Bad_Opcode },
7927     { Bad_Opcode },
7928     { Bad_Opcode },
7929     { Bad_Opcode },
7930     { Bad_Opcode },
7931     /* b0 */
7932     { Bad_Opcode },
7933     { Bad_Opcode },
7934     { Bad_Opcode },
7935     { Bad_Opcode },
7936     { Bad_Opcode },
7937     { Bad_Opcode },
7938     { Bad_Opcode },
7939     { Bad_Opcode },
7940     /* b8 */
7941     { Bad_Opcode },
7942     { Bad_Opcode },
7943     { Bad_Opcode },
7944     { Bad_Opcode },
7945     { Bad_Opcode },
7946     { Bad_Opcode },
7947     { Bad_Opcode },
7948     { Bad_Opcode },
7949     /* c0 */
7950     { Bad_Opcode },
7951     { "vphaddbw",       { XM, EXxmm } },
7952     { "vphaddbd",       { XM, EXxmm } },
7953     { "vphaddbq",       { XM, EXxmm } },
7954     { Bad_Opcode },
7955     { Bad_Opcode },
7956     { "vphaddwd",       { XM, EXxmm } },
7957     { "vphaddwq",       { XM, EXxmm } },
7958     /* c8 */
7959     { Bad_Opcode },
7960     { Bad_Opcode },
7961     { Bad_Opcode },
7962     { "vphadddq",       { XM, EXxmm } },
7963     { Bad_Opcode },
7964     { Bad_Opcode },
7965     { Bad_Opcode },
7966     { Bad_Opcode },
7967     /* d0 */
7968     { Bad_Opcode },
7969     { "vphaddubw",      { XM, EXxmm } },
7970     { "vphaddubd",      { XM, EXxmm } },
7971     { "vphaddubq",      { XM, EXxmm } },
7972     { Bad_Opcode },
7973     { Bad_Opcode },
7974     { "vphadduwd",      { XM, EXxmm } },
7975     { "vphadduwq",      { XM, EXxmm } },
7976     /* d8 */
7977     { Bad_Opcode },
7978     { Bad_Opcode },
7979     { Bad_Opcode },
7980     { "vphaddudq",      { XM, EXxmm } },
7981     { Bad_Opcode },
7982     { Bad_Opcode },
7983     { Bad_Opcode },
7984     { Bad_Opcode },
7985     /* e0 */
7986     { Bad_Opcode },
7987     { "vphsubbw",       { XM, EXxmm } },
7988     { "vphsubwd",       { XM, EXxmm } },
7989     { "vphsubdq",       { XM, EXxmm } },
7990     { Bad_Opcode },
7991     { Bad_Opcode },
7992     { Bad_Opcode },
7993     { Bad_Opcode },
7994     /* e8 */
7995     { Bad_Opcode },
7996     { Bad_Opcode },
7997     { Bad_Opcode },
7998     { Bad_Opcode },
7999     { Bad_Opcode },
8000     { Bad_Opcode },
8001     { Bad_Opcode },
8002     { Bad_Opcode },
8003     /* f0 */
8004     { Bad_Opcode },
8005     { Bad_Opcode },
8006     { Bad_Opcode },
8007     { Bad_Opcode },
8008     { Bad_Opcode },
8009     { Bad_Opcode },
8010     { Bad_Opcode },
8011     { Bad_Opcode },
8012     /* f8 */
8013     { Bad_Opcode },
8014     { Bad_Opcode },
8015     { Bad_Opcode },
8016     { Bad_Opcode },
8017     { Bad_Opcode },
8018     { Bad_Opcode },
8019     { Bad_Opcode },
8020     { Bad_Opcode },
8021   },
8022   /* XOP_0A */
8023   {
8024     /* 00 */
8025     { Bad_Opcode },
8026     { Bad_Opcode },
8027     { Bad_Opcode },
8028     { Bad_Opcode },
8029     { Bad_Opcode },
8030     { Bad_Opcode },
8031     { Bad_Opcode },
8032     { Bad_Opcode },
8033     /* 08 */
8034     { Bad_Opcode },
8035     { Bad_Opcode },
8036     { Bad_Opcode },
8037     { Bad_Opcode },
8038     { Bad_Opcode },
8039     { Bad_Opcode },
8040     { Bad_Opcode },
8041     { Bad_Opcode },
8042     /* 10 */
8043     { "bextr",  { Gv, Ev, Iq } },
8044     { Bad_Opcode },
8045     { REG_TABLE (REG_XOP_LWP) },
8046     { Bad_Opcode },
8047     { Bad_Opcode },
8048     { Bad_Opcode },
8049     { Bad_Opcode },
8050     { Bad_Opcode },
8051     /* 18 */
8052     { Bad_Opcode },
8053     { Bad_Opcode },
8054     { Bad_Opcode },
8055     { Bad_Opcode },
8056     { Bad_Opcode },
8057     { Bad_Opcode },
8058     { Bad_Opcode },
8059     { Bad_Opcode },
8060     /* 20 */
8061     { Bad_Opcode },
8062     { Bad_Opcode },
8063     { Bad_Opcode },
8064     { Bad_Opcode },
8065     { Bad_Opcode },
8066     { Bad_Opcode },
8067     { Bad_Opcode },
8068     { Bad_Opcode },
8069     /* 28 */
8070     { Bad_Opcode },
8071     { Bad_Opcode },
8072     { Bad_Opcode },
8073     { Bad_Opcode },
8074     { Bad_Opcode },
8075     { Bad_Opcode },
8076     { Bad_Opcode },
8077     { Bad_Opcode },
8078     /* 30 */
8079     { Bad_Opcode },
8080     { Bad_Opcode },
8081     { Bad_Opcode },
8082     { Bad_Opcode },
8083     { Bad_Opcode },
8084     { Bad_Opcode },
8085     { Bad_Opcode },
8086     { Bad_Opcode },
8087     /* 38 */
8088     { Bad_Opcode },
8089     { Bad_Opcode },
8090     { Bad_Opcode },
8091     { Bad_Opcode },
8092     { Bad_Opcode },
8093     { Bad_Opcode },
8094     { Bad_Opcode },
8095     { Bad_Opcode },
8096     /* 40 */
8097     { Bad_Opcode },
8098     { Bad_Opcode },
8099     { Bad_Opcode },
8100     { Bad_Opcode },
8101     { Bad_Opcode },
8102     { Bad_Opcode },
8103     { Bad_Opcode },
8104     { Bad_Opcode },
8105     /* 48 */
8106     { Bad_Opcode },
8107     { Bad_Opcode },
8108     { Bad_Opcode },
8109     { Bad_Opcode },
8110     { Bad_Opcode },
8111     { Bad_Opcode },
8112     { Bad_Opcode },
8113     { Bad_Opcode },
8114     /* 50 */
8115     { Bad_Opcode },
8116     { Bad_Opcode },
8117     { Bad_Opcode },
8118     { Bad_Opcode },
8119     { Bad_Opcode },
8120     { Bad_Opcode },
8121     { Bad_Opcode },
8122     { Bad_Opcode },
8123     /* 58 */
8124     { Bad_Opcode },
8125     { Bad_Opcode },
8126     { Bad_Opcode },
8127     { Bad_Opcode },
8128     { Bad_Opcode },
8129     { Bad_Opcode },
8130     { Bad_Opcode },
8131     { Bad_Opcode },
8132     /* 60 */
8133     { Bad_Opcode },
8134     { Bad_Opcode },
8135     { Bad_Opcode },
8136     { Bad_Opcode },
8137     { Bad_Opcode },
8138     { Bad_Opcode },
8139     { Bad_Opcode },
8140     { Bad_Opcode },
8141     /* 68 */
8142     { Bad_Opcode },
8143     { Bad_Opcode },
8144     { Bad_Opcode },
8145     { Bad_Opcode },
8146     { Bad_Opcode },
8147     { Bad_Opcode },
8148     { Bad_Opcode },
8149     { Bad_Opcode },
8150     /* 70 */
8151     { Bad_Opcode },
8152     { Bad_Opcode },
8153     { Bad_Opcode },
8154     { Bad_Opcode },
8155     { Bad_Opcode },
8156     { Bad_Opcode },
8157     { Bad_Opcode },
8158     { Bad_Opcode },
8159     /* 78 */
8160     { Bad_Opcode },
8161     { Bad_Opcode },
8162     { Bad_Opcode },
8163     { Bad_Opcode },
8164     { Bad_Opcode },
8165     { Bad_Opcode },
8166     { Bad_Opcode },
8167     { Bad_Opcode },
8168     /* 80 */
8169     { Bad_Opcode },
8170     { Bad_Opcode },
8171     { Bad_Opcode },
8172     { Bad_Opcode },
8173     { Bad_Opcode },
8174     { Bad_Opcode },
8175     { Bad_Opcode },
8176     { Bad_Opcode },
8177     /* 88 */
8178     { Bad_Opcode },
8179     { Bad_Opcode },
8180     { Bad_Opcode },
8181     { Bad_Opcode },
8182     { Bad_Opcode },
8183     { Bad_Opcode },
8184     { Bad_Opcode },
8185     { Bad_Opcode },
8186     /* 90 */
8187     { Bad_Opcode },
8188     { Bad_Opcode },
8189     { Bad_Opcode },
8190     { Bad_Opcode },
8191     { Bad_Opcode },
8192     { Bad_Opcode },
8193     { Bad_Opcode },
8194     { Bad_Opcode },
8195     /* 98 */
8196     { Bad_Opcode },
8197     { Bad_Opcode },
8198     { Bad_Opcode },
8199     { Bad_Opcode },
8200     { Bad_Opcode },
8201     { Bad_Opcode },
8202     { Bad_Opcode },
8203     { Bad_Opcode },
8204     /* a0 */
8205     { Bad_Opcode },
8206     { Bad_Opcode },
8207     { Bad_Opcode },
8208     { Bad_Opcode },
8209     { Bad_Opcode },
8210     { Bad_Opcode },
8211     { Bad_Opcode },
8212     { Bad_Opcode },
8213     /* a8 */
8214     { Bad_Opcode },
8215     { Bad_Opcode },
8216     { Bad_Opcode },
8217     { Bad_Opcode },
8218     { Bad_Opcode },
8219     { Bad_Opcode },
8220     { Bad_Opcode },
8221     { Bad_Opcode },
8222     /* b0 */
8223     { Bad_Opcode },
8224     { Bad_Opcode },
8225     { Bad_Opcode },
8226     { Bad_Opcode },
8227     { Bad_Opcode },
8228     { Bad_Opcode },
8229     { Bad_Opcode },
8230     { Bad_Opcode },
8231     /* b8 */
8232     { Bad_Opcode },
8233     { Bad_Opcode },
8234     { Bad_Opcode },
8235     { Bad_Opcode },
8236     { Bad_Opcode },
8237     { Bad_Opcode },
8238     { Bad_Opcode },
8239     { Bad_Opcode },
8240     /* c0 */
8241     { Bad_Opcode },
8242     { Bad_Opcode },
8243     { Bad_Opcode },
8244     { Bad_Opcode },
8245     { Bad_Opcode },
8246     { Bad_Opcode },
8247     { Bad_Opcode },
8248     { Bad_Opcode },
8249     /* c8 */
8250     { Bad_Opcode },
8251     { Bad_Opcode },
8252     { Bad_Opcode },
8253     { Bad_Opcode },
8254     { Bad_Opcode },
8255     { Bad_Opcode },
8256     { Bad_Opcode },
8257     { Bad_Opcode },
8258     /* d0 */
8259     { Bad_Opcode },
8260     { Bad_Opcode },
8261     { Bad_Opcode },
8262     { Bad_Opcode },
8263     { Bad_Opcode },
8264     { Bad_Opcode },
8265     { Bad_Opcode },
8266     { Bad_Opcode },
8267     /* d8 */
8268     { Bad_Opcode },
8269     { Bad_Opcode },
8270     { Bad_Opcode },
8271     { Bad_Opcode },
8272     { Bad_Opcode },
8273     { Bad_Opcode },
8274     { Bad_Opcode },
8275     { Bad_Opcode },
8276     /* e0 */
8277     { Bad_Opcode },
8278     { Bad_Opcode },
8279     { Bad_Opcode },
8280     { Bad_Opcode },
8281     { Bad_Opcode },
8282     { Bad_Opcode },
8283     { Bad_Opcode },
8284     { Bad_Opcode },
8285     /* e8 */
8286     { Bad_Opcode },
8287     { Bad_Opcode },
8288     { Bad_Opcode },
8289     { Bad_Opcode },
8290     { Bad_Opcode },
8291     { Bad_Opcode },
8292     { Bad_Opcode },
8293     { Bad_Opcode },
8294     /* f0 */
8295     { Bad_Opcode },
8296     { Bad_Opcode },
8297     { Bad_Opcode },
8298     { Bad_Opcode },
8299     { Bad_Opcode },
8300     { Bad_Opcode },
8301     { Bad_Opcode },
8302     { Bad_Opcode },
8303     /* f8 */
8304     { Bad_Opcode },
8305     { Bad_Opcode },
8306     { Bad_Opcode },
8307     { Bad_Opcode },
8308     { Bad_Opcode },
8309     { Bad_Opcode },
8310     { Bad_Opcode },
8311     { Bad_Opcode },
8312   },
8313 };
8314
8315 static const struct dis386 vex_table[][256] = {
8316   /* VEX_0F */
8317   {
8318     /* 00 */
8319     { Bad_Opcode },
8320     { Bad_Opcode },
8321     { Bad_Opcode },
8322     { Bad_Opcode },
8323     { Bad_Opcode },
8324     { Bad_Opcode },
8325     { Bad_Opcode },
8326     { Bad_Opcode },
8327     /* 08 */
8328     { Bad_Opcode },
8329     { Bad_Opcode },
8330     { Bad_Opcode },
8331     { Bad_Opcode },
8332     { Bad_Opcode },
8333     { Bad_Opcode },
8334     { Bad_Opcode },
8335     { Bad_Opcode },
8336     /* 10 */
8337     { PREFIX_TABLE (PREFIX_VEX_0F10) },
8338     { PREFIX_TABLE (PREFIX_VEX_0F11) },
8339     { PREFIX_TABLE (PREFIX_VEX_0F12) },
8340     { MOD_TABLE (MOD_VEX_0F13) },
8341     { VEX_W_TABLE (VEX_W_0F14) },
8342     { VEX_W_TABLE (VEX_W_0F15) },
8343     { PREFIX_TABLE (PREFIX_VEX_0F16) },
8344     { MOD_TABLE (MOD_VEX_0F17) },
8345     /* 18 */
8346     { Bad_Opcode },
8347     { Bad_Opcode },
8348     { Bad_Opcode },
8349     { Bad_Opcode },
8350     { Bad_Opcode },
8351     { Bad_Opcode },
8352     { Bad_Opcode },
8353     { Bad_Opcode },
8354     /* 20 */
8355     { Bad_Opcode },
8356     { Bad_Opcode },
8357     { Bad_Opcode },
8358     { Bad_Opcode },
8359     { Bad_Opcode },
8360     { Bad_Opcode },
8361     { Bad_Opcode },
8362     { Bad_Opcode },
8363     /* 28 */
8364     { VEX_W_TABLE (VEX_W_0F28) },
8365     { VEX_W_TABLE (VEX_W_0F29) },
8366     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8367     { MOD_TABLE (MOD_VEX_0F2B) },
8368     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8369     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8370     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8371     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8372     /* 30 */
8373     { Bad_Opcode },
8374     { Bad_Opcode },
8375     { Bad_Opcode },
8376     { Bad_Opcode },
8377     { Bad_Opcode },
8378     { Bad_Opcode },
8379     { Bad_Opcode },
8380     { Bad_Opcode },
8381     /* 38 */
8382     { Bad_Opcode },
8383     { Bad_Opcode },
8384     { Bad_Opcode },
8385     { Bad_Opcode },
8386     { Bad_Opcode },
8387     { Bad_Opcode },
8388     { Bad_Opcode },
8389     { Bad_Opcode },
8390     /* 40 */
8391     { Bad_Opcode },
8392     { PREFIX_TABLE (PREFIX_VEX_0F41) },
8393     { PREFIX_TABLE (PREFIX_VEX_0F42) },
8394     { Bad_Opcode },
8395     { PREFIX_TABLE (PREFIX_VEX_0F44) },
8396     { PREFIX_TABLE (PREFIX_VEX_0F45) },
8397     { PREFIX_TABLE (PREFIX_VEX_0F46) },
8398     { PREFIX_TABLE (PREFIX_VEX_0F47) },
8399     /* 48 */
8400     { Bad_Opcode },
8401     { Bad_Opcode },
8402     { Bad_Opcode },
8403     { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8404     { Bad_Opcode },
8405     { Bad_Opcode },
8406     { Bad_Opcode },
8407     { Bad_Opcode },
8408     /* 50 */
8409     { MOD_TABLE (MOD_VEX_0F50) },
8410     { PREFIX_TABLE (PREFIX_VEX_0F51) },
8411     { PREFIX_TABLE (PREFIX_VEX_0F52) },
8412     { PREFIX_TABLE (PREFIX_VEX_0F53) },
8413     { "vandpX",         { XM, Vex, EXx } },
8414     { "vandnpX",        { XM, Vex, EXx } },
8415     { "vorpX",          { XM, Vex, EXx } },
8416     { "vxorpX",         { XM, Vex, EXx } },
8417     /* 58 */
8418     { PREFIX_TABLE (PREFIX_VEX_0F58) },
8419     { PREFIX_TABLE (PREFIX_VEX_0F59) },
8420     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8421     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8422     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8423     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8424     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8425     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8426     /* 60 */
8427     { PREFIX_TABLE (PREFIX_VEX_0F60) },
8428     { PREFIX_TABLE (PREFIX_VEX_0F61) },
8429     { PREFIX_TABLE (PREFIX_VEX_0F62) },
8430     { PREFIX_TABLE (PREFIX_VEX_0F63) },
8431     { PREFIX_TABLE (PREFIX_VEX_0F64) },
8432     { PREFIX_TABLE (PREFIX_VEX_0F65) },
8433     { PREFIX_TABLE (PREFIX_VEX_0F66) },
8434     { PREFIX_TABLE (PREFIX_VEX_0F67) },
8435     /* 68 */
8436     { PREFIX_TABLE (PREFIX_VEX_0F68) },
8437     { PREFIX_TABLE (PREFIX_VEX_0F69) },
8438     { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8439     { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8440     { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8441     { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8442     { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8443     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8444     /* 70 */
8445     { PREFIX_TABLE (PREFIX_VEX_0F70) },
8446     { REG_TABLE (REG_VEX_0F71) },
8447     { REG_TABLE (REG_VEX_0F72) },
8448     { REG_TABLE (REG_VEX_0F73) },
8449     { PREFIX_TABLE (PREFIX_VEX_0F74) },
8450     { PREFIX_TABLE (PREFIX_VEX_0F75) },
8451     { PREFIX_TABLE (PREFIX_VEX_0F76) },
8452     { PREFIX_TABLE (PREFIX_VEX_0F77) },
8453     /* 78 */
8454     { Bad_Opcode },
8455     { Bad_Opcode },
8456     { Bad_Opcode },
8457     { Bad_Opcode },
8458     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8459     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8460     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8461     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8462     /* 80 */
8463     { Bad_Opcode },
8464     { Bad_Opcode },
8465     { Bad_Opcode },
8466     { Bad_Opcode },
8467     { Bad_Opcode },
8468     { Bad_Opcode },
8469     { Bad_Opcode },
8470     { Bad_Opcode },
8471     /* 88 */
8472     { Bad_Opcode },
8473     { Bad_Opcode },
8474     { Bad_Opcode },
8475     { Bad_Opcode },
8476     { Bad_Opcode },
8477     { Bad_Opcode },
8478     { Bad_Opcode },
8479     { Bad_Opcode },
8480     /* 90 */
8481     { PREFIX_TABLE (PREFIX_VEX_0F90) },
8482     { PREFIX_TABLE (PREFIX_VEX_0F91) },
8483     { PREFIX_TABLE (PREFIX_VEX_0F92) },
8484     { PREFIX_TABLE (PREFIX_VEX_0F93) },
8485     { Bad_Opcode },
8486     { Bad_Opcode },
8487     { Bad_Opcode },
8488     { Bad_Opcode },
8489     /* 98 */
8490     { PREFIX_TABLE (PREFIX_VEX_0F98) },
8491     { Bad_Opcode },
8492     { Bad_Opcode },
8493     { Bad_Opcode },
8494     { Bad_Opcode },
8495     { Bad_Opcode },
8496     { Bad_Opcode },
8497     { Bad_Opcode },
8498     /* a0 */
8499     { Bad_Opcode },
8500     { Bad_Opcode },
8501     { Bad_Opcode },
8502     { Bad_Opcode },
8503     { Bad_Opcode },
8504     { Bad_Opcode },
8505     { Bad_Opcode },
8506     { Bad_Opcode },
8507     /* a8 */
8508     { Bad_Opcode },
8509     { Bad_Opcode },
8510     { Bad_Opcode },
8511     { Bad_Opcode },
8512     { Bad_Opcode },
8513     { Bad_Opcode },
8514     { REG_TABLE (REG_VEX_0FAE) },
8515     { Bad_Opcode },
8516     /* b0 */
8517     { Bad_Opcode },
8518     { Bad_Opcode },
8519     { Bad_Opcode },
8520     { Bad_Opcode },
8521     { Bad_Opcode },
8522     { Bad_Opcode },
8523     { Bad_Opcode },
8524     { Bad_Opcode },
8525     /* b8 */
8526     { Bad_Opcode },
8527     { Bad_Opcode },
8528     { Bad_Opcode },
8529     { Bad_Opcode },
8530     { Bad_Opcode },
8531     { Bad_Opcode },
8532     { Bad_Opcode },
8533     { Bad_Opcode },
8534     /* c0 */
8535     { Bad_Opcode },
8536     { Bad_Opcode },
8537     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8538     { Bad_Opcode },
8539     { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8540     { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8541     { "vshufpX",        { XM, Vex, EXx, Ib } },
8542     { Bad_Opcode },
8543     /* c8 */
8544     { Bad_Opcode },
8545     { Bad_Opcode },
8546     { Bad_Opcode },
8547     { Bad_Opcode },
8548     { Bad_Opcode },
8549     { Bad_Opcode },
8550     { Bad_Opcode },
8551     { Bad_Opcode },
8552     /* d0 */
8553     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8554     { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8555     { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8556     { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8557     { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8558     { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8559     { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8560     { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8561     /* d8 */
8562     { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8563     { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8564     { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8565     { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8566     { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8567     { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8568     { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8569     { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8570     /* e0 */
8571     { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8572     { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8573     { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8574     { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8575     { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8576     { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8577     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8578     { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8579     /* e8 */
8580     { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8581     { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8582     { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8583     { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8584     { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8585     { PREFIX_TABLE (PREFIX_VEX_0FED) },
8586     { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8587     { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8588     /* f0 */
8589     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8590     { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8591     { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8592     { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8593     { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8594     { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8595     { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8596     { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8597     /* f8 */
8598     { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8599     { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8600     { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8601     { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8602     { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8603     { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8604     { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8605     { Bad_Opcode },
8606   },
8607   /* VEX_0F38 */
8608   {
8609     /* 00 */
8610     { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8611     { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8612     { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8613     { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8614     { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8615     { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8616     { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8617     { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8618     /* 08 */
8619     { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8620     { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8621     { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8622     { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8623     { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8624     { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8625     { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8626     { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8627     /* 10 */
8628     { Bad_Opcode },
8629     { Bad_Opcode },
8630     { Bad_Opcode },
8631     { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8632     { Bad_Opcode },
8633     { Bad_Opcode },
8634     { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8635     { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8636     /* 18 */
8637     { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8638     { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8639     { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8640     { Bad_Opcode },
8641     { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8642     { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8643     { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8644     { Bad_Opcode },
8645     /* 20 */
8646     { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8647     { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8648     { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8649     { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8650     { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8651     { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8652     { Bad_Opcode },
8653     { Bad_Opcode },
8654     /* 28 */
8655     { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8656     { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8657     { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8658     { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8659     { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8660     { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8661     { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8662     { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8663     /* 30 */
8664     { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8665     { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8666     { PREFIX_TABLE (PREFIX_VEX_0F3832) },
8667     { PREFIX_TABLE (PREFIX_VEX_0F3833) },
8668     { PREFIX_TABLE (PREFIX_VEX_0F3834) },
8669     { PREFIX_TABLE (PREFIX_VEX_0F3835) },
8670     { PREFIX_TABLE (PREFIX_VEX_0F3836) },
8671     { PREFIX_TABLE (PREFIX_VEX_0F3837) },
8672     /* 38 */
8673     { PREFIX_TABLE (PREFIX_VEX_0F3838) },
8674     { PREFIX_TABLE (PREFIX_VEX_0F3839) },
8675     { PREFIX_TABLE (PREFIX_VEX_0F383A) },
8676     { PREFIX_TABLE (PREFIX_VEX_0F383B) },
8677     { PREFIX_TABLE (PREFIX_VEX_0F383C) },
8678     { PREFIX_TABLE (PREFIX_VEX_0F383D) },
8679     { PREFIX_TABLE (PREFIX_VEX_0F383E) },
8680     { PREFIX_TABLE (PREFIX_VEX_0F383F) },
8681     /* 40 */
8682     { PREFIX_TABLE (PREFIX_VEX_0F3840) },
8683     { PREFIX_TABLE (PREFIX_VEX_0F3841) },
8684     { Bad_Opcode },
8685     { Bad_Opcode },
8686     { Bad_Opcode },
8687     { PREFIX_TABLE (PREFIX_VEX_0F3845) },
8688     { PREFIX_TABLE (PREFIX_VEX_0F3846) },
8689     { PREFIX_TABLE (PREFIX_VEX_0F3847) },
8690     /* 48 */
8691     { Bad_Opcode },
8692     { Bad_Opcode },
8693     { Bad_Opcode },
8694     { Bad_Opcode },
8695     { Bad_Opcode },
8696     { Bad_Opcode },
8697     { Bad_Opcode },
8698     { Bad_Opcode },
8699     /* 50 */
8700     { Bad_Opcode },
8701     { Bad_Opcode },
8702     { Bad_Opcode },
8703     { Bad_Opcode },
8704     { Bad_Opcode },
8705     { Bad_Opcode },
8706     { Bad_Opcode },
8707     { Bad_Opcode },
8708     /* 58 */
8709     { PREFIX_TABLE (PREFIX_VEX_0F3858) },
8710     { PREFIX_TABLE (PREFIX_VEX_0F3859) },
8711     { PREFIX_TABLE (PREFIX_VEX_0F385A) },
8712     { Bad_Opcode },
8713     { Bad_Opcode },
8714     { Bad_Opcode },
8715     { Bad_Opcode },
8716     { Bad_Opcode },
8717     /* 60 */
8718     { Bad_Opcode },
8719     { Bad_Opcode },
8720     { Bad_Opcode },
8721     { Bad_Opcode },
8722     { Bad_Opcode },
8723     { Bad_Opcode },
8724     { Bad_Opcode },
8725     { Bad_Opcode },
8726     /* 68 */
8727     { Bad_Opcode },
8728     { Bad_Opcode },
8729     { Bad_Opcode },
8730     { Bad_Opcode },
8731     { Bad_Opcode },
8732     { Bad_Opcode },
8733     { Bad_Opcode },
8734     { Bad_Opcode },
8735     /* 70 */
8736     { Bad_Opcode },
8737     { Bad_Opcode },
8738     { Bad_Opcode },
8739     { Bad_Opcode },
8740     { Bad_Opcode },
8741     { Bad_Opcode },
8742     { Bad_Opcode },
8743     { Bad_Opcode },
8744     /* 78 */
8745     { PREFIX_TABLE (PREFIX_VEX_0F3878) },
8746     { PREFIX_TABLE (PREFIX_VEX_0F3879) },
8747     { Bad_Opcode },
8748     { Bad_Opcode },
8749     { Bad_Opcode },
8750     { Bad_Opcode },
8751     { Bad_Opcode },
8752     { Bad_Opcode },
8753     /* 80 */
8754     { Bad_Opcode },
8755     { Bad_Opcode },
8756     { Bad_Opcode },
8757     { Bad_Opcode },
8758     { Bad_Opcode },
8759     { Bad_Opcode },
8760     { Bad_Opcode },
8761     { Bad_Opcode },
8762     /* 88 */
8763     { Bad_Opcode },
8764     { Bad_Opcode },
8765     { Bad_Opcode },
8766     { Bad_Opcode },
8767     { PREFIX_TABLE (PREFIX_VEX_0F388C) },
8768     { Bad_Opcode },
8769     { PREFIX_TABLE (PREFIX_VEX_0F388E) },
8770     { Bad_Opcode },
8771     /* 90 */
8772     { PREFIX_TABLE (PREFIX_VEX_0F3890) },
8773     { PREFIX_TABLE (PREFIX_VEX_0F3891) },
8774     { PREFIX_TABLE (PREFIX_VEX_0F3892) },
8775     { PREFIX_TABLE (PREFIX_VEX_0F3893) },
8776     { Bad_Opcode },
8777     { Bad_Opcode },
8778     { PREFIX_TABLE (PREFIX_VEX_0F3896) },
8779     { PREFIX_TABLE (PREFIX_VEX_0F3897) },
8780     /* 98 */
8781     { PREFIX_TABLE (PREFIX_VEX_0F3898) },
8782     { PREFIX_TABLE (PREFIX_VEX_0F3899) },
8783     { PREFIX_TABLE (PREFIX_VEX_0F389A) },
8784     { PREFIX_TABLE (PREFIX_VEX_0F389B) },
8785     { PREFIX_TABLE (PREFIX_VEX_0F389C) },
8786     { PREFIX_TABLE (PREFIX_VEX_0F389D) },
8787     { PREFIX_TABLE (PREFIX_VEX_0F389E) },
8788     { PREFIX_TABLE (PREFIX_VEX_0F389F) },
8789     /* a0 */
8790     { Bad_Opcode },
8791     { Bad_Opcode },
8792     { Bad_Opcode },
8793     { Bad_Opcode },
8794     { Bad_Opcode },
8795     { Bad_Opcode },
8796     { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
8797     { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
8798     /* a8 */
8799     { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
8800     { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
8801     { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
8802     { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
8803     { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
8804     { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
8805     { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
8806     { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
8807     /* b0 */
8808     { Bad_Opcode },
8809     { Bad_Opcode },
8810     { Bad_Opcode },
8811     { Bad_Opcode },
8812     { Bad_Opcode },
8813     { Bad_Opcode },
8814     { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
8815     { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
8816     /* b8 */
8817     { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
8818     { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
8819     { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
8820     { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
8821     { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
8822     { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
8823     { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
8824     { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
8825     /* c0 */
8826     { Bad_Opcode },
8827     { Bad_Opcode },
8828     { Bad_Opcode },
8829     { Bad_Opcode },
8830     { Bad_Opcode },
8831     { Bad_Opcode },
8832     { Bad_Opcode },
8833     { Bad_Opcode },
8834     /* c8 */
8835     { Bad_Opcode },
8836     { Bad_Opcode },
8837     { Bad_Opcode },
8838     { Bad_Opcode },
8839     { Bad_Opcode },
8840     { Bad_Opcode },
8841     { Bad_Opcode },
8842     { Bad_Opcode },
8843     /* d0 */
8844     { Bad_Opcode },
8845     { Bad_Opcode },
8846     { Bad_Opcode },
8847     { Bad_Opcode },
8848     { Bad_Opcode },
8849     { Bad_Opcode },
8850     { Bad_Opcode },
8851     { Bad_Opcode },
8852     /* d8 */
8853     { Bad_Opcode },
8854     { Bad_Opcode },
8855     { Bad_Opcode },
8856     { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
8857     { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
8858     { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
8859     { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
8860     { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
8861     /* e0 */
8862     { Bad_Opcode },
8863     { Bad_Opcode },
8864     { Bad_Opcode },
8865     { Bad_Opcode },
8866     { Bad_Opcode },
8867     { Bad_Opcode },
8868     { Bad_Opcode },
8869     { Bad_Opcode },
8870     /* e8 */
8871     { Bad_Opcode },
8872     { Bad_Opcode },
8873     { Bad_Opcode },
8874     { Bad_Opcode },
8875     { Bad_Opcode },
8876     { Bad_Opcode },
8877     { Bad_Opcode },
8878     { Bad_Opcode },
8879     /* f0 */
8880     { Bad_Opcode },
8881     { Bad_Opcode },
8882     { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
8883     { REG_TABLE (REG_VEX_0F38F3) },
8884     { Bad_Opcode },
8885     { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
8886     { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
8887     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
8888     /* f8 */
8889     { Bad_Opcode },
8890     { Bad_Opcode },
8891     { Bad_Opcode },
8892     { Bad_Opcode },
8893     { Bad_Opcode },
8894     { Bad_Opcode },
8895     { Bad_Opcode },
8896     { Bad_Opcode },
8897   },
8898   /* VEX_0F3A */
8899   {
8900     /* 00 */
8901     { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
8902     { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
8903     { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
8904     { Bad_Opcode },
8905     { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
8906     { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
8907     { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
8908     { Bad_Opcode },
8909     /* 08 */
8910     { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
8911     { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
8912     { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
8913     { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
8914     { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
8915     { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
8916     { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
8917     { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
8918     /* 10 */
8919     { Bad_Opcode },
8920     { Bad_Opcode },
8921     { Bad_Opcode },
8922     { Bad_Opcode },
8923     { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
8924     { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
8925     { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
8926     { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
8927     /* 18 */
8928     { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
8929     { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
8930     { Bad_Opcode },
8931     { Bad_Opcode },
8932     { Bad_Opcode },
8933     { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
8934     { Bad_Opcode },
8935     { Bad_Opcode },
8936     /* 20 */
8937     { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
8938     { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
8939     { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
8940     { Bad_Opcode },
8941     { Bad_Opcode },
8942     { Bad_Opcode },
8943     { Bad_Opcode },
8944     { Bad_Opcode },
8945     /* 28 */
8946     { Bad_Opcode },
8947     { Bad_Opcode },
8948     { Bad_Opcode },
8949     { Bad_Opcode },
8950     { Bad_Opcode },
8951     { Bad_Opcode },
8952     { Bad_Opcode },
8953     { Bad_Opcode },
8954     /* 30 */
8955     { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
8956     { Bad_Opcode },
8957     { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
8958     { Bad_Opcode },
8959     { Bad_Opcode },
8960     { Bad_Opcode },
8961     { Bad_Opcode },
8962     { Bad_Opcode },
8963     /* 38 */
8964     { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
8965     { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
8966     { Bad_Opcode },
8967     { Bad_Opcode },
8968     { Bad_Opcode },
8969     { Bad_Opcode },
8970     { Bad_Opcode },
8971     { Bad_Opcode },
8972     /* 40 */
8973     { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
8974     { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
8975     { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
8976     { Bad_Opcode },
8977     { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
8978     { Bad_Opcode },
8979     { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
8980     { Bad_Opcode },
8981     /* 48 */
8982     { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
8983     { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
8984     { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
8985     { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
8986     { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
8987     { Bad_Opcode },
8988     { Bad_Opcode },
8989     { Bad_Opcode },
8990     /* 50 */
8991     { Bad_Opcode },
8992     { Bad_Opcode },
8993     { Bad_Opcode },
8994     { Bad_Opcode },
8995     { Bad_Opcode },
8996     { Bad_Opcode },
8997     { Bad_Opcode },
8998     { Bad_Opcode },
8999     /* 58 */
9000     { Bad_Opcode },
9001     { Bad_Opcode },
9002     { Bad_Opcode },
9003     { Bad_Opcode },
9004     { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9005     { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9006     { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9007     { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9008     /* 60 */
9009     { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9010     { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9011     { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9012     { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9013     { Bad_Opcode },
9014     { Bad_Opcode },
9015     { Bad_Opcode },
9016     { Bad_Opcode },
9017     /* 68 */
9018     { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9019     { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9020     { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9021     { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9022     { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9023     { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9024     { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9025     { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9026     /* 70 */
9027     { Bad_Opcode },
9028     { Bad_Opcode },
9029     { Bad_Opcode },
9030     { Bad_Opcode },
9031     { Bad_Opcode },
9032     { Bad_Opcode },
9033     { Bad_Opcode },
9034     { Bad_Opcode },
9035     /* 78 */
9036     { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9037     { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9038     { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9039     { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9040     { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9041     { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9042     { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9043     { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9044     /* 80 */
9045     { Bad_Opcode },
9046     { Bad_Opcode },
9047     { Bad_Opcode },
9048     { Bad_Opcode },
9049     { Bad_Opcode },
9050     { Bad_Opcode },
9051     { Bad_Opcode },
9052     { Bad_Opcode },
9053     /* 88 */
9054     { Bad_Opcode },
9055     { Bad_Opcode },
9056     { Bad_Opcode },
9057     { Bad_Opcode },
9058     { Bad_Opcode },
9059     { Bad_Opcode },
9060     { Bad_Opcode },
9061     { Bad_Opcode },
9062     /* 90 */
9063     { Bad_Opcode },
9064     { Bad_Opcode },
9065     { Bad_Opcode },
9066     { Bad_Opcode },
9067     { Bad_Opcode },
9068     { Bad_Opcode },
9069     { Bad_Opcode },
9070     { Bad_Opcode },
9071     /* 98 */
9072     { Bad_Opcode },
9073     { Bad_Opcode },
9074     { Bad_Opcode },
9075     { Bad_Opcode },
9076     { Bad_Opcode },
9077     { Bad_Opcode },
9078     { Bad_Opcode },
9079     { Bad_Opcode },
9080     /* a0 */
9081     { Bad_Opcode },
9082     { Bad_Opcode },
9083     { Bad_Opcode },
9084     { Bad_Opcode },
9085     { Bad_Opcode },
9086     { Bad_Opcode },
9087     { Bad_Opcode },
9088     { Bad_Opcode },
9089     /* a8 */
9090     { Bad_Opcode },
9091     { Bad_Opcode },
9092     { Bad_Opcode },
9093     { Bad_Opcode },
9094     { Bad_Opcode },
9095     { Bad_Opcode },
9096     { Bad_Opcode },
9097     { Bad_Opcode },
9098     /* b0 */
9099     { Bad_Opcode },
9100     { Bad_Opcode },
9101     { Bad_Opcode },
9102     { Bad_Opcode },
9103     { Bad_Opcode },
9104     { Bad_Opcode },
9105     { Bad_Opcode },
9106     { Bad_Opcode },
9107     /* b8 */
9108     { Bad_Opcode },
9109     { Bad_Opcode },
9110     { Bad_Opcode },
9111     { Bad_Opcode },
9112     { Bad_Opcode },
9113     { Bad_Opcode },
9114     { Bad_Opcode },
9115     { Bad_Opcode },
9116     /* c0 */
9117     { Bad_Opcode },
9118     { Bad_Opcode },
9119     { Bad_Opcode },
9120     { Bad_Opcode },
9121     { Bad_Opcode },
9122     { Bad_Opcode },
9123     { Bad_Opcode },
9124     { Bad_Opcode },
9125     /* c8 */
9126     { Bad_Opcode },
9127     { Bad_Opcode },
9128     { Bad_Opcode },
9129     { Bad_Opcode },
9130     { Bad_Opcode },
9131     { Bad_Opcode },
9132     { Bad_Opcode },
9133     { Bad_Opcode },
9134     /* d0 */
9135     { Bad_Opcode },
9136     { Bad_Opcode },
9137     { Bad_Opcode },
9138     { Bad_Opcode },
9139     { Bad_Opcode },
9140     { Bad_Opcode },
9141     { Bad_Opcode },
9142     { Bad_Opcode },
9143     /* d8 */
9144     { Bad_Opcode },
9145     { Bad_Opcode },
9146     { Bad_Opcode },
9147     { Bad_Opcode },
9148     { Bad_Opcode },
9149     { Bad_Opcode },
9150     { Bad_Opcode },
9151     { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9152     /* e0 */
9153     { Bad_Opcode },
9154     { Bad_Opcode },
9155     { Bad_Opcode },
9156     { Bad_Opcode },
9157     { Bad_Opcode },
9158     { Bad_Opcode },
9159     { Bad_Opcode },
9160     { Bad_Opcode },
9161     /* e8 */
9162     { Bad_Opcode },
9163     { Bad_Opcode },
9164     { Bad_Opcode },
9165     { Bad_Opcode },
9166     { Bad_Opcode },
9167     { Bad_Opcode },
9168     { Bad_Opcode },
9169     { Bad_Opcode },
9170     /* f0 */
9171     { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9172     { Bad_Opcode },
9173     { Bad_Opcode },
9174     { Bad_Opcode },
9175     { Bad_Opcode },
9176     { Bad_Opcode },
9177     { Bad_Opcode },
9178     { Bad_Opcode },
9179     /* f8 */
9180     { Bad_Opcode },
9181     { Bad_Opcode },
9182     { Bad_Opcode },
9183     { Bad_Opcode },
9184     { Bad_Opcode },
9185     { Bad_Opcode },
9186     { Bad_Opcode },
9187     { Bad_Opcode },
9188   },
9189 };
9190
9191 #define NEED_OPCODE_TABLE
9192 #include "i386-dis-evex.h"
9193 #undef NEED_OPCODE_TABLE
9194 static const struct dis386 vex_len_table[][2] = {
9195   /* VEX_LEN_0F10_P_1 */
9196   {
9197     { VEX_W_TABLE (VEX_W_0F10_P_1) },
9198     { VEX_W_TABLE (VEX_W_0F10_P_1) },
9199   },
9200
9201   /* VEX_LEN_0F10_P_3 */
9202   {
9203     { VEX_W_TABLE (VEX_W_0F10_P_3) },
9204     { VEX_W_TABLE (VEX_W_0F10_P_3) },
9205   },
9206
9207   /* VEX_LEN_0F11_P_1 */
9208   {
9209     { VEX_W_TABLE (VEX_W_0F11_P_1) },
9210     { VEX_W_TABLE (VEX_W_0F11_P_1) },
9211   },
9212
9213   /* VEX_LEN_0F11_P_3 */
9214   {
9215     { VEX_W_TABLE (VEX_W_0F11_P_3) },
9216     { VEX_W_TABLE (VEX_W_0F11_P_3) },
9217   },
9218
9219   /* VEX_LEN_0F12_P_0_M_0 */
9220   {
9221     { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) },
9222   },
9223
9224   /* VEX_LEN_0F12_P_0_M_1 */
9225   {
9226     { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) },
9227   },
9228
9229   /* VEX_LEN_0F12_P_2 */
9230   {
9231     { VEX_W_TABLE (VEX_W_0F12_P_2) },
9232   },
9233
9234   /* VEX_LEN_0F13_M_0 */
9235   {
9236     { VEX_W_TABLE (VEX_W_0F13_M_0) },
9237   },
9238
9239   /* VEX_LEN_0F16_P_0_M_0 */
9240   {
9241     { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) },
9242   },
9243
9244   /* VEX_LEN_0F16_P_0_M_1 */
9245   {
9246     { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) },
9247   },
9248
9249   /* VEX_LEN_0F16_P_2 */
9250   {
9251     { VEX_W_TABLE (VEX_W_0F16_P_2) },
9252   },
9253
9254   /* VEX_LEN_0F17_M_0 */
9255   {
9256     { VEX_W_TABLE (VEX_W_0F17_M_0) },
9257   },
9258
9259   /* VEX_LEN_0F2A_P_1 */
9260   {
9261     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev } },
9262     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev } },
9263   },
9264
9265   /* VEX_LEN_0F2A_P_3 */
9266   {
9267     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev } },
9268     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev } },
9269   },
9270
9271   /* VEX_LEN_0F2C_P_1 */
9272   {
9273     { "vcvttss2siY",    { Gv, EXdScalar } },
9274     { "vcvttss2siY",    { Gv, EXdScalar } },
9275   },
9276
9277   /* VEX_LEN_0F2C_P_3 */
9278   {
9279     { "vcvttsd2siY",    { Gv, EXqScalar } },
9280     { "vcvttsd2siY",    { Gv, EXqScalar } },
9281   },
9282
9283   /* VEX_LEN_0F2D_P_1 */
9284   {
9285     { "vcvtss2siY",     { Gv, EXdScalar } },
9286     { "vcvtss2siY",     { Gv, EXdScalar } },
9287   },
9288
9289   /* VEX_LEN_0F2D_P_3 */
9290   {
9291     { "vcvtsd2siY",     { Gv, EXqScalar } },
9292     { "vcvtsd2siY",     { Gv, EXqScalar } },
9293   },
9294
9295   /* VEX_LEN_0F2E_P_0 */
9296   {
9297     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9298     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9299   },
9300
9301   /* VEX_LEN_0F2E_P_2 */
9302   {
9303     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9304     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9305   },
9306
9307   /* VEX_LEN_0F2F_P_0 */
9308   {
9309     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9310     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9311   },
9312
9313   /* VEX_LEN_0F2F_P_2 */
9314   {
9315     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9316     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9317   },
9318
9319   /* VEX_LEN_0F41_P_0 */
9320   {
9321     { Bad_Opcode },
9322     { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9323   },
9324   /* VEX_LEN_0F42_P_0 */
9325   {
9326     { Bad_Opcode },
9327     { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9328   },
9329   /* VEX_LEN_0F44_P_0 */
9330   {
9331     { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9332   },
9333   /* VEX_LEN_0F45_P_0 */
9334   {
9335     { Bad_Opcode },
9336     { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9337   },
9338   /* VEX_LEN_0F46_P_0 */
9339   {
9340     { Bad_Opcode },
9341     { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9342   },
9343   /* VEX_LEN_0F47_P_0 */
9344   {
9345     { Bad_Opcode },
9346     { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9347   },
9348   /* VEX_LEN_0F4B_P_2 */
9349   {
9350     { Bad_Opcode },
9351     { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9352   },
9353
9354   /* VEX_LEN_0F51_P_1 */
9355   {
9356     { VEX_W_TABLE (VEX_W_0F51_P_1) },
9357     { VEX_W_TABLE (VEX_W_0F51_P_1) },
9358   },
9359
9360   /* VEX_LEN_0F51_P_3 */
9361   {
9362     { VEX_W_TABLE (VEX_W_0F51_P_3) },
9363     { VEX_W_TABLE (VEX_W_0F51_P_3) },
9364   },
9365
9366   /* VEX_LEN_0F52_P_1 */
9367   {
9368     { VEX_W_TABLE (VEX_W_0F52_P_1) },
9369     { VEX_W_TABLE (VEX_W_0F52_P_1) },
9370   },
9371
9372   /* VEX_LEN_0F53_P_1 */
9373   {
9374     { VEX_W_TABLE (VEX_W_0F53_P_1) },
9375     { VEX_W_TABLE (VEX_W_0F53_P_1) },
9376   },
9377
9378   /* VEX_LEN_0F58_P_1 */
9379   {
9380     { VEX_W_TABLE (VEX_W_0F58_P_1) },
9381     { VEX_W_TABLE (VEX_W_0F58_P_1) },
9382   },
9383
9384   /* VEX_LEN_0F58_P_3 */
9385   {
9386     { VEX_W_TABLE (VEX_W_0F58_P_3) },
9387     { VEX_W_TABLE (VEX_W_0F58_P_3) },
9388   },
9389
9390   /* VEX_LEN_0F59_P_1 */
9391   {
9392     { VEX_W_TABLE (VEX_W_0F59_P_1) },
9393     { VEX_W_TABLE (VEX_W_0F59_P_1) },
9394   },
9395
9396   /* VEX_LEN_0F59_P_3 */
9397   {
9398     { VEX_W_TABLE (VEX_W_0F59_P_3) },
9399     { VEX_W_TABLE (VEX_W_0F59_P_3) },
9400   },
9401
9402   /* VEX_LEN_0F5A_P_1 */
9403   {
9404     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9405     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9406   },
9407
9408   /* VEX_LEN_0F5A_P_3 */
9409   {
9410     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9411     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9412   },
9413
9414   /* VEX_LEN_0F5C_P_1 */
9415   {
9416     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9417     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9418   },
9419
9420   /* VEX_LEN_0F5C_P_3 */
9421   {
9422     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9423     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9424   },
9425
9426   /* VEX_LEN_0F5D_P_1 */
9427   {
9428     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9429     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9430   },
9431
9432   /* VEX_LEN_0F5D_P_3 */
9433   {
9434     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9435     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9436   },
9437
9438   /* VEX_LEN_0F5E_P_1 */
9439   {
9440     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9441     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9442   },
9443
9444   /* VEX_LEN_0F5E_P_3 */
9445   {
9446     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9447     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9448   },
9449
9450   /* VEX_LEN_0F5F_P_1 */
9451   {
9452     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9453     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9454   },
9455
9456   /* VEX_LEN_0F5F_P_3 */
9457   {
9458     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9459     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9460   },
9461
9462   /* VEX_LEN_0F6E_P_2 */
9463   {
9464     { "vmovK",          { XMScalar, Edq } },
9465     { "vmovK",          { XMScalar, Edq } },
9466   },
9467
9468   /* VEX_LEN_0F7E_P_1 */
9469   {
9470     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9471     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9472   },
9473
9474   /* VEX_LEN_0F7E_P_2 */
9475   {
9476     { "vmovK",          { Edq, XMScalar } },
9477     { "vmovK",          { Edq, XMScalar } },
9478   },
9479
9480   /* VEX_LEN_0F90_P_0 */
9481   {
9482     { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9483   },
9484
9485   /* VEX_LEN_0F91_P_0 */
9486   {
9487     { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9488   },
9489
9490   /* VEX_LEN_0F92_P_0 */
9491   {
9492     { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9493   },
9494
9495   /* VEX_LEN_0F93_P_0 */
9496   {
9497     { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9498   },
9499
9500   /* VEX_LEN_0F98_P_0 */
9501   {
9502     { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9503   },
9504
9505   /* VEX_LEN_0FAE_R_2_M_0 */
9506   {
9507     { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) },
9508   },
9509
9510   /* VEX_LEN_0FAE_R_3_M_0 */
9511   {
9512     { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) },
9513   },
9514
9515   /* VEX_LEN_0FC2_P_1 */
9516   {
9517     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9518     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9519   },
9520
9521   /* VEX_LEN_0FC2_P_3 */
9522   {
9523     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9524     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9525   },
9526
9527   /* VEX_LEN_0FC4_P_2 */
9528   {
9529     { VEX_W_TABLE (VEX_W_0FC4_P_2) },
9530   },
9531
9532   /* VEX_LEN_0FC5_P_2 */
9533   {
9534     { VEX_W_TABLE (VEX_W_0FC5_P_2) },
9535   },
9536
9537   /* VEX_LEN_0FD6_P_2 */
9538   {
9539     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9540     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9541   },
9542
9543   /* VEX_LEN_0FF7_P_2 */
9544   {
9545     { VEX_W_TABLE (VEX_W_0FF7_P_2) },
9546   },
9547
9548   /* VEX_LEN_0F3816_P_2 */
9549   {
9550     { Bad_Opcode },
9551     { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9552   },
9553
9554   /* VEX_LEN_0F3819_P_2 */
9555   {
9556     { Bad_Opcode },
9557     { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9558   },
9559
9560   /* VEX_LEN_0F381A_P_2_M_0 */
9561   {
9562     { Bad_Opcode },
9563     { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9564   },
9565
9566   /* VEX_LEN_0F3836_P_2 */
9567   {
9568     { Bad_Opcode },
9569     { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9570   },
9571
9572   /* VEX_LEN_0F3841_P_2 */
9573   {
9574     { VEX_W_TABLE (VEX_W_0F3841_P_2) },
9575   },
9576
9577   /* VEX_LEN_0F385A_P_2_M_0 */
9578   {
9579     { Bad_Opcode },
9580     { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
9581   },
9582
9583   /* VEX_LEN_0F38DB_P_2 */
9584   {
9585     { VEX_W_TABLE (VEX_W_0F38DB_P_2) },
9586   },
9587
9588   /* VEX_LEN_0F38DC_P_2 */
9589   {
9590     { VEX_W_TABLE (VEX_W_0F38DC_P_2) },
9591   },
9592
9593   /* VEX_LEN_0F38DD_P_2 */
9594   {
9595     { VEX_W_TABLE (VEX_W_0F38DD_P_2) },
9596   },
9597
9598   /* VEX_LEN_0F38DE_P_2 */
9599   {
9600     { VEX_W_TABLE (VEX_W_0F38DE_P_2) },
9601   },
9602
9603   /* VEX_LEN_0F38DF_P_2 */
9604   {
9605     { VEX_W_TABLE (VEX_W_0F38DF_P_2) },
9606   },
9607
9608   /* VEX_LEN_0F38F2_P_0 */
9609   {
9610     { "andnS",          { Gdq, VexGdq, Edq } },
9611   },
9612
9613   /* VEX_LEN_0F38F3_R_1_P_0 */
9614   {
9615     { "blsrS",          { VexGdq, Edq } },
9616   },
9617
9618   /* VEX_LEN_0F38F3_R_2_P_0 */
9619   {
9620     { "blsmskS",        { VexGdq, Edq } },
9621   },
9622
9623   /* VEX_LEN_0F38F3_R_3_P_0 */
9624   {
9625     { "blsiS",          { VexGdq, Edq } },
9626   },
9627
9628   /* VEX_LEN_0F38F5_P_0 */
9629   {
9630     { "bzhiS",          { Gdq, Edq, VexGdq } },
9631   },
9632
9633   /* VEX_LEN_0F38F5_P_1 */
9634   {
9635     { "pextS",          { Gdq, VexGdq, Edq } },
9636   },
9637
9638   /* VEX_LEN_0F38F5_P_3 */
9639   {
9640     { "pdepS",          { Gdq, VexGdq, Edq } },
9641   },
9642
9643   /* VEX_LEN_0F38F6_P_3 */
9644   {
9645     { "mulxS",          { Gdq, VexGdq, Edq } },
9646   },
9647
9648   /* VEX_LEN_0F38F7_P_0 */
9649   {
9650     { "bextrS",         { Gdq, Edq, VexGdq } },
9651   },
9652
9653   /* VEX_LEN_0F38F7_P_1 */
9654   {
9655     { "sarxS",          { Gdq, Edq, VexGdq } },
9656   },
9657
9658   /* VEX_LEN_0F38F7_P_2 */
9659   {
9660     { "shlxS",          { Gdq, Edq, VexGdq } },
9661   },
9662
9663   /* VEX_LEN_0F38F7_P_3 */
9664   {
9665     { "shrxS",          { Gdq, Edq, VexGdq } },
9666   },
9667
9668   /* VEX_LEN_0F3A00_P_2 */
9669   {
9670     { Bad_Opcode },
9671     { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
9672   },
9673
9674   /* VEX_LEN_0F3A01_P_2 */
9675   {
9676     { Bad_Opcode },
9677     { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
9678   },
9679
9680   /* VEX_LEN_0F3A06_P_2 */
9681   {
9682     { Bad_Opcode },
9683     { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
9684   },
9685
9686   /* VEX_LEN_0F3A0A_P_2 */
9687   {
9688     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
9689     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
9690   },
9691
9692   /* VEX_LEN_0F3A0B_P_2 */
9693   {
9694     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
9695     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
9696   },
9697
9698   /* VEX_LEN_0F3A14_P_2 */
9699   {
9700     { VEX_W_TABLE (VEX_W_0F3A14_P_2) },
9701   },
9702
9703   /* VEX_LEN_0F3A15_P_2 */
9704   {
9705     { VEX_W_TABLE (VEX_W_0F3A15_P_2) },
9706   },
9707
9708   /* VEX_LEN_0F3A16_P_2  */
9709   {
9710     { "vpextrK",        { Edq, XM, Ib } },
9711   },
9712
9713   /* VEX_LEN_0F3A17_P_2 */
9714   {
9715     { "vextractps",     { Edqd, XM, Ib } },
9716   },
9717
9718   /* VEX_LEN_0F3A18_P_2 */
9719   {
9720     { Bad_Opcode },
9721     { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
9722   },
9723
9724   /* VEX_LEN_0F3A19_P_2 */
9725   {
9726     { Bad_Opcode },
9727     { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
9728   },
9729
9730   /* VEX_LEN_0F3A20_P_2 */
9731   {
9732     { VEX_W_TABLE (VEX_W_0F3A20_P_2) },
9733   },
9734
9735   /* VEX_LEN_0F3A21_P_2 */
9736   {
9737     { VEX_W_TABLE (VEX_W_0F3A21_P_2) },
9738   },
9739
9740   /* VEX_LEN_0F3A22_P_2 */
9741   {
9742     { "vpinsrK",        { XM, Vex128, Edq, Ib } },
9743   },
9744
9745   /* VEX_LEN_0F3A30_P_2 */
9746   {
9747     { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
9748   },
9749
9750   /* VEX_LEN_0F3A32_P_2 */
9751   {
9752     { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
9753   },
9754
9755   /* VEX_LEN_0F3A38_P_2 */
9756   {
9757     { Bad_Opcode },
9758     { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
9759   },
9760
9761   /* VEX_LEN_0F3A39_P_2 */
9762   {
9763     { Bad_Opcode },
9764     { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
9765   },
9766
9767   /* VEX_LEN_0F3A41_P_2 */
9768   {
9769     { VEX_W_TABLE (VEX_W_0F3A41_P_2) },
9770   },
9771
9772   /* VEX_LEN_0F3A44_P_2 */
9773   {
9774     { VEX_W_TABLE (VEX_W_0F3A44_P_2) },
9775   },
9776
9777   /* VEX_LEN_0F3A46_P_2 */
9778   {
9779     { Bad_Opcode },
9780     { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
9781   },
9782
9783   /* VEX_LEN_0F3A60_P_2 */
9784   {
9785     { VEX_W_TABLE (VEX_W_0F3A60_P_2) },
9786   },
9787
9788   /* VEX_LEN_0F3A61_P_2 */
9789   {
9790     { VEX_W_TABLE (VEX_W_0F3A61_P_2) },
9791   },
9792
9793   /* VEX_LEN_0F3A62_P_2 */
9794   {
9795     { VEX_W_TABLE (VEX_W_0F3A62_P_2) },
9796   },
9797
9798   /* VEX_LEN_0F3A63_P_2 */
9799   {
9800     { VEX_W_TABLE (VEX_W_0F3A63_P_2) },
9801   },
9802
9803   /* VEX_LEN_0F3A6A_P_2 */
9804   {
9805     { "vfmaddss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9806   },
9807
9808   /* VEX_LEN_0F3A6B_P_2 */
9809   {
9810     { "vfmaddsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9811   },
9812
9813   /* VEX_LEN_0F3A6E_P_2 */
9814   {
9815     { "vfmsubss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9816   },
9817
9818   /* VEX_LEN_0F3A6F_P_2 */
9819   {
9820     { "vfmsubsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9821   },
9822
9823   /* VEX_LEN_0F3A7A_P_2 */
9824   {
9825     { "vfnmaddss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9826   },
9827
9828   /* VEX_LEN_0F3A7B_P_2 */
9829   {
9830     { "vfnmaddsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9831   },
9832
9833   /* VEX_LEN_0F3A7E_P_2 */
9834   {
9835     { "vfnmsubss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9836   },
9837
9838   /* VEX_LEN_0F3A7F_P_2 */
9839   {
9840     { "vfnmsubsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9841   },
9842
9843   /* VEX_LEN_0F3ADF_P_2 */
9844   {
9845     { VEX_W_TABLE (VEX_W_0F3ADF_P_2) },
9846   },
9847
9848   /* VEX_LEN_0F3AF0_P_3 */
9849   {
9850     { "rorxS",          { Gdq, Edq, Ib } },
9851   },
9852
9853   /* VEX_LEN_0FXOP_08_CC */
9854   {
9855      { "vpcomb",        { XM, Vex128, EXx, Ib } },
9856   },
9857
9858   /* VEX_LEN_0FXOP_08_CD */
9859   {
9860      { "vpcomw",        { XM, Vex128, EXx, Ib } },
9861   },
9862
9863   /* VEX_LEN_0FXOP_08_CE */
9864   {
9865      { "vpcomd",        { XM, Vex128, EXx, Ib } },
9866   },
9867
9868   /* VEX_LEN_0FXOP_08_CF */
9869   {
9870      { "vpcomq",        { XM, Vex128, EXx, Ib } },
9871   },
9872
9873   /* VEX_LEN_0FXOP_08_EC */
9874   {
9875      { "vpcomub",       { XM, Vex128, EXx, Ib } },
9876   },
9877
9878   /* VEX_LEN_0FXOP_08_ED */
9879   {
9880      { "vpcomuw",       { XM, Vex128, EXx, Ib } },
9881   },
9882
9883   /* VEX_LEN_0FXOP_08_EE */
9884   {
9885      { "vpcomud",       { XM, Vex128, EXx, Ib } },
9886   },
9887
9888   /* VEX_LEN_0FXOP_08_EF */
9889   {
9890      { "vpcomuq",       { XM, Vex128, EXx, Ib } },
9891   },
9892
9893   /* VEX_LEN_0FXOP_09_80 */
9894   {
9895     { "vfrczps",        { XM, EXxmm } },
9896     { "vfrczps",        { XM, EXymmq } },
9897   },
9898
9899   /* VEX_LEN_0FXOP_09_81 */
9900   {
9901     { "vfrczpd",        { XM, EXxmm } },
9902     { "vfrczpd",        { XM, EXymmq } },
9903   },
9904 };
9905
9906 static const struct dis386 vex_w_table[][2] = {
9907   {
9908     /* VEX_W_0F10_P_0 */
9909     { "vmovups",        { XM, EXx } },
9910   },
9911   {
9912     /* VEX_W_0F10_P_1 */
9913     { "vmovss",         { XMVexScalar, VexScalar, EXdScalar } },
9914   },
9915   {
9916     /* VEX_W_0F10_P_2 */
9917     { "vmovupd",        { XM, EXx } },
9918   },
9919   {
9920     /* VEX_W_0F10_P_3 */
9921     { "vmovsd",         { XMVexScalar, VexScalar, EXqScalar } },
9922   },
9923   {
9924     /* VEX_W_0F11_P_0 */
9925     { "vmovups",        { EXxS, XM } },
9926   },
9927   {
9928     /* VEX_W_0F11_P_1 */
9929     { "vmovss",         { EXdVexScalarS, VexScalar, XMScalar } },
9930   },
9931   {
9932     /* VEX_W_0F11_P_2 */
9933     { "vmovupd",        { EXxS, XM } },
9934   },
9935   {
9936     /* VEX_W_0F11_P_3 */
9937     { "vmovsd",         { EXqVexScalarS, VexScalar, XMScalar } },
9938   },
9939   {
9940     /* VEX_W_0F12_P_0_M_0 */
9941     { "vmovlps",        { XM, Vex128, EXq } },
9942   },
9943   {
9944     /* VEX_W_0F12_P_0_M_1 */
9945     { "vmovhlps",       { XM, Vex128, EXq } },
9946   },
9947   {
9948     /* VEX_W_0F12_P_1 */
9949     { "vmovsldup",      { XM, EXx } },
9950   },
9951   {
9952     /* VEX_W_0F12_P_2 */
9953     { "vmovlpd",        { XM, Vex128, EXq } },
9954   },
9955   {
9956     /* VEX_W_0F12_P_3 */
9957     { "vmovddup",       { XM, EXymmq } },
9958   },
9959   {
9960     /* VEX_W_0F13_M_0 */
9961     { "vmovlpX",        { EXq, XM } },
9962   },
9963   {
9964     /* VEX_W_0F14 */
9965     { "vunpcklpX",      { XM, Vex, EXx } },
9966   },
9967   {
9968     /* VEX_W_0F15 */
9969     { "vunpckhpX",      { XM, Vex, EXx } },
9970   },
9971   {
9972     /* VEX_W_0F16_P_0_M_0 */
9973     { "vmovhps",        { XM, Vex128, EXq } },
9974   },
9975   {
9976     /* VEX_W_0F16_P_0_M_1 */
9977     { "vmovlhps",       { XM, Vex128, EXq } },
9978   },
9979   {
9980     /* VEX_W_0F16_P_1 */
9981     { "vmovshdup",      { XM, EXx } },
9982   },
9983   {
9984     /* VEX_W_0F16_P_2 */
9985     { "vmovhpd",        { XM, Vex128, EXq } },
9986   },
9987   {
9988     /* VEX_W_0F17_M_0 */
9989     { "vmovhpX",        { EXq, XM } },
9990   },
9991   {
9992     /* VEX_W_0F28 */
9993     { "vmovapX",        { XM, EXx } },
9994   },
9995   {
9996     /* VEX_W_0F29 */
9997     { "vmovapX",        { EXxS, XM } },
9998   },
9999   {
10000     /* VEX_W_0F2B_M_0 */
10001     { "vmovntpX",       { Mx, XM } },
10002   },
10003   {
10004     /* VEX_W_0F2E_P_0 */
10005     { "vucomiss",       { XMScalar, EXdScalar } },
10006   },
10007   {
10008     /* VEX_W_0F2E_P_2 */
10009     { "vucomisd",       { XMScalar, EXqScalar } },
10010   },
10011   {
10012     /* VEX_W_0F2F_P_0 */
10013     { "vcomiss",        { XMScalar, EXdScalar } },
10014   },
10015   {
10016     /* VEX_W_0F2F_P_2 */
10017     { "vcomisd",        { XMScalar, EXqScalar } },
10018   },
10019   {
10020     /* VEX_W_0F41_P_0_LEN_1 */
10021     { "kandw",          { MaskG, MaskVex, MaskR } },
10022   },
10023   {
10024     /* VEX_W_0F42_P_0_LEN_1 */
10025     { "kandnw",         { MaskG, MaskVex, MaskR } },
10026   },
10027   {
10028     /* VEX_W_0F44_P_0_LEN_0 */
10029     { "knotw",          { MaskG, MaskR } },
10030   },
10031   {
10032     /* VEX_W_0F45_P_0_LEN_1 */
10033     { "korw",           { MaskG, MaskVex, MaskR } },
10034   },
10035   {
10036     /* VEX_W_0F46_P_0_LEN_1 */
10037     { "kxnorw",         { MaskG, MaskVex, MaskR } },
10038   },
10039   {
10040     /* VEX_W_0F47_P_0_LEN_1 */
10041     { "kxorw",          { MaskG, MaskVex, MaskR } },
10042   },
10043   {
10044     /* VEX_W_0F4B_P_2_LEN_1 */
10045     { "kunpckbw",       { MaskG, MaskVex, MaskR } },
10046   },
10047   {
10048     /* VEX_W_0F50_M_0 */
10049     { "vmovmskpX",      { Gdq, XS } },
10050   },
10051   {
10052     /* VEX_W_0F51_P_0 */
10053     { "vsqrtps",        { XM, EXx } },
10054   },
10055   {
10056     /* VEX_W_0F51_P_1 */
10057     { "vsqrtss",        { XMScalar, VexScalar, EXdScalar } },
10058   },
10059   {
10060     /* VEX_W_0F51_P_2  */
10061     { "vsqrtpd",        { XM, EXx } },
10062   },
10063   {
10064     /* VEX_W_0F51_P_3 */
10065     { "vsqrtsd",        { XMScalar, VexScalar, EXqScalar } },
10066   },
10067   {
10068     /* VEX_W_0F52_P_0 */
10069     { "vrsqrtps",       { XM, EXx } },
10070   },
10071   {
10072     /* VEX_W_0F52_P_1 */
10073     { "vrsqrtss",       { XMScalar, VexScalar, EXdScalar } },
10074   },
10075   {
10076     /* VEX_W_0F53_P_0  */
10077     { "vrcpps",         { XM, EXx } },
10078   },
10079   {
10080     /* VEX_W_0F53_P_1  */
10081     { "vrcpss",         { XMScalar, VexScalar, EXdScalar } },
10082   },
10083   {
10084     /* VEX_W_0F58_P_0  */
10085     { "vaddps",         { XM, Vex, EXx } },
10086   },
10087   {
10088     /* VEX_W_0F58_P_1  */
10089     { "vaddss",         { XMScalar, VexScalar, EXdScalar } },
10090   },
10091   {
10092     /* VEX_W_0F58_P_2  */
10093     { "vaddpd",         { XM, Vex, EXx } },
10094   },
10095   {
10096     /* VEX_W_0F58_P_3  */
10097     { "vaddsd",         { XMScalar, VexScalar, EXqScalar } },
10098   },
10099   {
10100     /* VEX_W_0F59_P_0  */
10101     { "vmulps",         { XM, Vex, EXx } },
10102   },
10103   {
10104     /* VEX_W_0F59_P_1  */
10105     { "vmulss",         { XMScalar, VexScalar, EXdScalar } },
10106   },
10107   {
10108     /* VEX_W_0F59_P_2  */
10109     { "vmulpd",         { XM, Vex, EXx } },
10110   },
10111   {
10112     /* VEX_W_0F59_P_3  */
10113     { "vmulsd",         { XMScalar, VexScalar, EXqScalar } },
10114   },
10115   {
10116     /* VEX_W_0F5A_P_0  */
10117     { "vcvtps2pd",      { XM, EXxmmq } },
10118   },
10119   {
10120     /* VEX_W_0F5A_P_1  */
10121     { "vcvtss2sd",      { XMScalar, VexScalar, EXdScalar } },
10122   },
10123   {
10124     /* VEX_W_0F5A_P_3  */
10125     { "vcvtsd2ss",      { XMScalar, VexScalar, EXqScalar } },
10126   },
10127   {
10128     /* VEX_W_0F5B_P_0  */
10129     { "vcvtdq2ps",      { XM, EXx } },
10130   },
10131   {
10132     /* VEX_W_0F5B_P_1  */
10133     { "vcvttps2dq",     { XM, EXx } },
10134   },
10135   {
10136     /* VEX_W_0F5B_P_2  */
10137     { "vcvtps2dq",      { XM, EXx } },
10138   },
10139   {
10140     /* VEX_W_0F5C_P_0  */
10141     { "vsubps",         { XM, Vex, EXx } },
10142   },
10143   {
10144     /* VEX_W_0F5C_P_1  */
10145     { "vsubss",         { XMScalar, VexScalar, EXdScalar } },
10146   },
10147   {
10148     /* VEX_W_0F5C_P_2  */
10149     { "vsubpd",         { XM, Vex, EXx } },
10150   },
10151   {
10152     /* VEX_W_0F5C_P_3  */
10153     { "vsubsd",         { XMScalar, VexScalar, EXqScalar } },
10154   },
10155   {
10156     /* VEX_W_0F5D_P_0  */
10157     { "vminps",         { XM, Vex, EXx } },
10158   },
10159   {
10160     /* VEX_W_0F5D_P_1  */
10161     { "vminss",         { XMScalar, VexScalar, EXdScalar } },
10162   },
10163   {
10164     /* VEX_W_0F5D_P_2  */
10165     { "vminpd",         { XM, Vex, EXx } },
10166   },
10167   {
10168     /* VEX_W_0F5D_P_3  */
10169     { "vminsd",         { XMScalar, VexScalar, EXqScalar } },
10170   },
10171   {
10172     /* VEX_W_0F5E_P_0  */
10173     { "vdivps",         { XM, Vex, EXx } },
10174   },
10175   {
10176     /* VEX_W_0F5E_P_1  */
10177     { "vdivss",         { XMScalar, VexScalar, EXdScalar } },
10178   },
10179   {
10180     /* VEX_W_0F5E_P_2  */
10181     { "vdivpd",         { XM, Vex, EXx } },
10182   },
10183   {
10184     /* VEX_W_0F5E_P_3  */
10185     { "vdivsd",         { XMScalar, VexScalar, EXqScalar } },
10186   },
10187   {
10188     /* VEX_W_0F5F_P_0  */
10189     { "vmaxps",         { XM, Vex, EXx } },
10190   },
10191   {
10192     /* VEX_W_0F5F_P_1  */
10193     { "vmaxss",         { XMScalar, VexScalar, EXdScalar } },
10194   },
10195   {
10196     /* VEX_W_0F5F_P_2  */
10197     { "vmaxpd",         { XM, Vex, EXx } },
10198   },
10199   {
10200     /* VEX_W_0F5F_P_3  */
10201     { "vmaxsd",         { XMScalar, VexScalar, EXqScalar } },
10202   },
10203   {
10204     /* VEX_W_0F60_P_2  */
10205     { "vpunpcklbw",     { XM, Vex, EXx } },
10206   },
10207   {
10208     /* VEX_W_0F61_P_2  */
10209     { "vpunpcklwd",     { XM, Vex, EXx } },
10210   },
10211   {
10212     /* VEX_W_0F62_P_2  */
10213     { "vpunpckldq",     { XM, Vex, EXx } },
10214   },
10215   {
10216     /* VEX_W_0F63_P_2  */
10217     { "vpacksswb",      { XM, Vex, EXx } },
10218   },
10219   {
10220     /* VEX_W_0F64_P_2  */
10221     { "vpcmpgtb",       { XM, Vex, EXx } },
10222   },
10223   {
10224     /* VEX_W_0F65_P_2  */
10225     { "vpcmpgtw",       { XM, Vex, EXx } },
10226   },
10227   {
10228     /* VEX_W_0F66_P_2  */
10229     { "vpcmpgtd",       { XM, Vex, EXx } },
10230   },
10231   {
10232     /* VEX_W_0F67_P_2  */
10233     { "vpackuswb",      { XM, Vex, EXx } },
10234   },
10235   {
10236     /* VEX_W_0F68_P_2  */
10237     { "vpunpckhbw",     { XM, Vex, EXx } },
10238   },
10239   {
10240     /* VEX_W_0F69_P_2  */
10241     { "vpunpckhwd",     { XM, Vex, EXx } },
10242   },
10243   {
10244     /* VEX_W_0F6A_P_2  */
10245     { "vpunpckhdq",     { XM, Vex, EXx } },
10246   },
10247   {
10248     /* VEX_W_0F6B_P_2  */
10249     { "vpackssdw",      { XM, Vex, EXx } },
10250   },
10251   {
10252     /* VEX_W_0F6C_P_2  */
10253     { "vpunpcklqdq",    { XM, Vex, EXx } },
10254   },
10255   {
10256     /* VEX_W_0F6D_P_2  */
10257     { "vpunpckhqdq",    { XM, Vex, EXx } },
10258   },
10259   {
10260     /* VEX_W_0F6F_P_1  */
10261     { "vmovdqu",        { XM, EXx } },
10262   },
10263   {
10264     /* VEX_W_0F6F_P_2  */
10265     { "vmovdqa",        { XM, EXx } },
10266   },
10267   {
10268     /* VEX_W_0F70_P_1 */
10269     { "vpshufhw",       { XM, EXx, Ib } },
10270   },
10271   {
10272     /* VEX_W_0F70_P_2 */
10273     { "vpshufd",        { XM, EXx, Ib } },
10274   },
10275   {
10276     /* VEX_W_0F70_P_3 */
10277     { "vpshuflw",       { XM, EXx, Ib } },
10278   },
10279   {
10280     /* VEX_W_0F71_R_2_P_2  */
10281     { "vpsrlw",         { Vex, XS, Ib } },
10282   },
10283   {
10284     /* VEX_W_0F71_R_4_P_2  */
10285     { "vpsraw",         { Vex, XS, Ib } },
10286   },
10287   {
10288     /* VEX_W_0F71_R_6_P_2  */
10289     { "vpsllw",         { Vex, XS, Ib } },
10290   },
10291   {
10292     /* VEX_W_0F72_R_2_P_2  */
10293     { "vpsrld",         { Vex, XS, Ib } },
10294   },
10295   {
10296     /* VEX_W_0F72_R_4_P_2  */
10297     { "vpsrad",         { Vex, XS, Ib } },
10298   },
10299   {
10300     /* VEX_W_0F72_R_6_P_2  */
10301     { "vpslld",         { Vex, XS, Ib } },
10302   },
10303   {
10304     /* VEX_W_0F73_R_2_P_2  */
10305     { "vpsrlq",         { Vex, XS, Ib } },
10306   },
10307   {
10308     /* VEX_W_0F73_R_3_P_2  */
10309     { "vpsrldq",        { Vex, XS, Ib } },
10310   },
10311   {
10312     /* VEX_W_0F73_R_6_P_2  */
10313     { "vpsllq",         { Vex, XS, Ib } },
10314   },
10315   {
10316     /* VEX_W_0F73_R_7_P_2  */
10317     { "vpslldq",        { Vex, XS, Ib } },
10318   },
10319   {
10320     /* VEX_W_0F74_P_2 */
10321     { "vpcmpeqb",       { XM, Vex, EXx } },
10322   },
10323   {
10324     /* VEX_W_0F75_P_2 */
10325     { "vpcmpeqw",       { XM, Vex, EXx } },
10326   },
10327   {
10328     /* VEX_W_0F76_P_2 */
10329     { "vpcmpeqd",       { XM, Vex, EXx } },
10330   },
10331   {
10332     /* VEX_W_0F77_P_0 */
10333     { "",               { VZERO } },
10334   },
10335   {
10336     /* VEX_W_0F7C_P_2 */
10337     { "vhaddpd",        { XM, Vex, EXx } },
10338   },
10339   {
10340     /* VEX_W_0F7C_P_3 */
10341     { "vhaddps",        { XM, Vex, EXx } },
10342   },
10343   {
10344     /* VEX_W_0F7D_P_2 */
10345     { "vhsubpd",        { XM, Vex, EXx } },
10346   },
10347   {
10348     /* VEX_W_0F7D_P_3 */
10349     { "vhsubps",        { XM, Vex, EXx } },
10350   },
10351   {
10352     /* VEX_W_0F7E_P_1 */
10353     { "vmovq",          { XMScalar, EXqScalar } },
10354   },
10355   {
10356     /* VEX_W_0F7F_P_1 */
10357     { "vmovdqu",        { EXxS, XM } },
10358   },
10359   {
10360     /* VEX_W_0F7F_P_2 */
10361     { "vmovdqa",        { EXxS, XM } },
10362   },
10363   {
10364     /* VEX_W_0F90_P_0_LEN_0 */
10365     { "kmovw",          { MaskG, MaskE } },
10366   },
10367   {
10368     /* VEX_W_0F91_P_0_LEN_0 */
10369     { "kmovw",          { Ew, MaskG } },
10370   },
10371   {
10372     /* VEX_W_0F92_P_0_LEN_0 */
10373     { "kmovw",          { MaskG, Rdq } },
10374   },
10375   {
10376     /* VEX_W_0F93_P_0_LEN_0 */
10377     { "kmovw",          { Gdq, MaskR } },
10378   },
10379   {
10380     /* VEX_W_0F98_P_0_LEN_0 */
10381     { "kortestw",       { MaskG, MaskR } },
10382   },
10383   {
10384     /* VEX_W_0FAE_R_2_M_0 */
10385     { "vldmxcsr",       { Md } },
10386   },
10387   {
10388     /* VEX_W_0FAE_R_3_M_0 */
10389     { "vstmxcsr",       { Md } },
10390   },
10391   {
10392     /* VEX_W_0FC2_P_0 */
10393     { "vcmpps",         { XM, Vex, EXx, VCMP } },
10394   },
10395   {
10396     /* VEX_W_0FC2_P_1 */
10397     { "vcmpss",         { XMScalar, VexScalar, EXdScalar, VCMP } },
10398   },
10399   {
10400     /* VEX_W_0FC2_P_2 */
10401     { "vcmppd",         { XM, Vex, EXx, VCMP } },
10402   },
10403   {
10404     /* VEX_W_0FC2_P_3 */
10405     { "vcmpsd",         { XMScalar, VexScalar, EXqScalar, VCMP } },
10406   },
10407   {
10408     /* VEX_W_0FC4_P_2 */
10409     { "vpinsrw",        { XM, Vex128, Edqw, Ib } },
10410   },
10411   {
10412     /* VEX_W_0FC5_P_2 */
10413     { "vpextrw",        { Gdq, XS, Ib } },
10414   },
10415   {
10416     /* VEX_W_0FD0_P_2 */
10417     { "vaddsubpd",      { XM, Vex, EXx } },
10418   },
10419   {
10420     /* VEX_W_0FD0_P_3 */
10421     { "vaddsubps",      { XM, Vex, EXx } },
10422   },
10423   {
10424     /* VEX_W_0FD1_P_2 */
10425     { "vpsrlw",         { XM, Vex, EXxmm } },
10426   },
10427   {
10428     /* VEX_W_0FD2_P_2 */
10429     { "vpsrld",         { XM, Vex, EXxmm } },
10430   },
10431   {
10432     /* VEX_W_0FD3_P_2 */
10433     { "vpsrlq",         { XM, Vex, EXxmm } },
10434   },
10435   {
10436     /* VEX_W_0FD4_P_2 */
10437     { "vpaddq",         { XM, Vex, EXx } },
10438   },
10439   {
10440     /* VEX_W_0FD5_P_2 */
10441     { "vpmullw",        { XM, Vex, EXx } },
10442   },
10443   {
10444     /* VEX_W_0FD6_P_2 */
10445     { "vmovq",          { EXqScalarS, XMScalar } },
10446   },
10447   {
10448     /* VEX_W_0FD7_P_2_M_1 */
10449     { "vpmovmskb",      { Gdq, XS } },
10450   },
10451   {
10452     /* VEX_W_0FD8_P_2 */
10453     { "vpsubusb",       { XM, Vex, EXx } },
10454   },
10455   {
10456     /* VEX_W_0FD9_P_2 */
10457     { "vpsubusw",       { XM, Vex, EXx } },
10458   },
10459   {
10460     /* VEX_W_0FDA_P_2 */
10461     { "vpminub",        { XM, Vex, EXx } },
10462   },
10463   {
10464     /* VEX_W_0FDB_P_2 */
10465     { "vpand",          { XM, Vex, EXx } },
10466   },
10467   {
10468     /* VEX_W_0FDC_P_2 */
10469     { "vpaddusb",       { XM, Vex, EXx } },
10470   },
10471   {
10472     /* VEX_W_0FDD_P_2 */
10473     { "vpaddusw",       { XM, Vex, EXx } },
10474   },
10475   {
10476     /* VEX_W_0FDE_P_2 */
10477     { "vpmaxub",        { XM, Vex, EXx } },
10478   },
10479   {
10480     /* VEX_W_0FDF_P_2 */
10481     { "vpandn",         { XM, Vex, EXx } },
10482   },
10483   {
10484     /* VEX_W_0FE0_P_2  */
10485     { "vpavgb",         { XM, Vex, EXx } },
10486   },
10487   {
10488     /* VEX_W_0FE1_P_2  */
10489     { "vpsraw",         { XM, Vex, EXxmm } },
10490   },
10491   {
10492     /* VEX_W_0FE2_P_2  */
10493     { "vpsrad",         { XM, Vex, EXxmm } },
10494   },
10495   {
10496     /* VEX_W_0FE3_P_2  */
10497     { "vpavgw",         { XM, Vex, EXx } },
10498   },
10499   {
10500     /* VEX_W_0FE4_P_2  */
10501     { "vpmulhuw",       { XM, Vex, EXx } },
10502   },
10503   {
10504     /* VEX_W_0FE5_P_2  */
10505     { "vpmulhw",        { XM, Vex, EXx } },
10506   },
10507   {
10508     /* VEX_W_0FE6_P_1  */
10509     { "vcvtdq2pd",      { XM, EXxmmq } },
10510   },
10511   {
10512     /* VEX_W_0FE6_P_2  */
10513     { "vcvttpd2dq%XY",  { XMM, EXx } },
10514   },
10515   {
10516     /* VEX_W_0FE6_P_3  */
10517     { "vcvtpd2dq%XY",   { XMM, EXx } },
10518   },
10519   {
10520     /* VEX_W_0FE7_P_2_M_0 */
10521     { "vmovntdq",       { Mx, XM } },
10522   },
10523   {
10524     /* VEX_W_0FE8_P_2  */
10525     { "vpsubsb",        { XM, Vex, EXx } },
10526   },
10527   {
10528     /* VEX_W_0FE9_P_2  */
10529     { "vpsubsw",        { XM, Vex, EXx } },
10530   },
10531   {
10532     /* VEX_W_0FEA_P_2  */
10533     { "vpminsw",        { XM, Vex, EXx } },
10534   },
10535   {
10536     /* VEX_W_0FEB_P_2  */
10537     { "vpor",           { XM, Vex, EXx } },
10538   },
10539   {
10540     /* VEX_W_0FEC_P_2  */
10541     { "vpaddsb",        { XM, Vex, EXx } },
10542   },
10543   {
10544     /* VEX_W_0FED_P_2  */
10545     { "vpaddsw",        { XM, Vex, EXx } },
10546   },
10547   {
10548     /* VEX_W_0FEE_P_2  */
10549     { "vpmaxsw",        { XM, Vex, EXx } },
10550   },
10551   {
10552     /* VEX_W_0FEF_P_2  */
10553     { "vpxor",          { XM, Vex, EXx } },
10554   },
10555   {
10556     /* VEX_W_0FF0_P_3_M_0 */
10557     { "vlddqu",         { XM, M } },
10558   },
10559   {
10560     /* VEX_W_0FF1_P_2 */
10561     { "vpsllw",         { XM, Vex, EXxmm } },
10562   },
10563   {
10564     /* VEX_W_0FF2_P_2 */
10565     { "vpslld",         { XM, Vex, EXxmm } },
10566   },
10567   {
10568     /* VEX_W_0FF3_P_2 */
10569     { "vpsllq",         { XM, Vex, EXxmm } },
10570   },
10571   {
10572     /* VEX_W_0FF4_P_2 */
10573     { "vpmuludq",       { XM, Vex, EXx } },
10574   },
10575   {
10576     /* VEX_W_0FF5_P_2 */
10577     { "vpmaddwd",       { XM, Vex, EXx } },
10578   },
10579   {
10580     /* VEX_W_0FF6_P_2 */
10581     { "vpsadbw",        { XM, Vex, EXx } },
10582   },
10583   {
10584     /* VEX_W_0FF7_P_2 */
10585     { "vmaskmovdqu",    { XM, XS } },
10586   },
10587   {
10588     /* VEX_W_0FF8_P_2 */
10589     { "vpsubb",         { XM, Vex, EXx } },
10590   },
10591   {
10592     /* VEX_W_0FF9_P_2 */
10593     { "vpsubw",         { XM, Vex, EXx } },
10594   },
10595   {
10596     /* VEX_W_0FFA_P_2 */
10597     { "vpsubd",         { XM, Vex, EXx } },
10598   },
10599   {
10600     /* VEX_W_0FFB_P_2 */
10601     { "vpsubq",         { XM, Vex, EXx } },
10602   },
10603   {
10604     /* VEX_W_0FFC_P_2 */
10605     { "vpaddb",         { XM, Vex, EXx } },
10606   },
10607   {
10608     /* VEX_W_0FFD_P_2 */
10609     { "vpaddw",         { XM, Vex, EXx } },
10610   },
10611   {
10612     /* VEX_W_0FFE_P_2 */
10613     { "vpaddd",         { XM, Vex, EXx } },
10614   },
10615   {
10616     /* VEX_W_0F3800_P_2  */
10617     { "vpshufb",        { XM, Vex, EXx } },
10618   },
10619   {
10620     /* VEX_W_0F3801_P_2  */
10621     { "vphaddw",        { XM, Vex, EXx } },
10622   },
10623   {
10624     /* VEX_W_0F3802_P_2  */
10625     { "vphaddd",        { XM, Vex, EXx } },
10626   },
10627   {
10628     /* VEX_W_0F3803_P_2  */
10629     { "vphaddsw",       { XM, Vex, EXx } },
10630   },
10631   {
10632     /* VEX_W_0F3804_P_2  */
10633     { "vpmaddubsw",     { XM, Vex, EXx } },
10634   },
10635   {
10636     /* VEX_W_0F3805_P_2  */
10637     { "vphsubw",        { XM, Vex, EXx } },
10638   },
10639   {
10640     /* VEX_W_0F3806_P_2  */
10641     { "vphsubd",        { XM, Vex, EXx } },
10642   },
10643   {
10644     /* VEX_W_0F3807_P_2  */
10645     { "vphsubsw",       { XM, Vex, EXx } },
10646   },
10647   {
10648     /* VEX_W_0F3808_P_2  */
10649     { "vpsignb",        { XM, Vex, EXx } },
10650   },
10651   {
10652     /* VEX_W_0F3809_P_2  */
10653     { "vpsignw",        { XM, Vex, EXx } },
10654   },
10655   {
10656     /* VEX_W_0F380A_P_2  */
10657     { "vpsignd",        { XM, Vex, EXx } },
10658   },
10659   {
10660     /* VEX_W_0F380B_P_2  */
10661     { "vpmulhrsw",      { XM, Vex, EXx } },
10662   },
10663   {
10664     /* VEX_W_0F380C_P_2  */
10665     { "vpermilps",      { XM, Vex, EXx } },
10666   },
10667   {
10668     /* VEX_W_0F380D_P_2  */
10669     { "vpermilpd",      { XM, Vex, EXx } },
10670   },
10671   {
10672     /* VEX_W_0F380E_P_2  */
10673     { "vtestps",        { XM, EXx } },
10674   },
10675   {
10676     /* VEX_W_0F380F_P_2  */
10677     { "vtestpd",        { XM, EXx } },
10678   },
10679   {
10680     /* VEX_W_0F3816_P_2  */
10681     { "vpermps",        { XM, Vex, EXx } },
10682   },
10683   {
10684     /* VEX_W_0F3817_P_2 */
10685     { "vptest",         { XM, EXx } },
10686   },
10687   {
10688     /* VEX_W_0F3818_P_2 */
10689     { "vbroadcastss",   { XM, EXxmm_md } },
10690   },
10691   {
10692     /* VEX_W_0F3819_P_2 */
10693     { "vbroadcastsd",   { XM, EXxmm_mq } },
10694   },
10695   {
10696     /* VEX_W_0F381A_P_2_M_0 */
10697     { "vbroadcastf128", { XM, Mxmm } },
10698   },
10699   {
10700     /* VEX_W_0F381C_P_2 */
10701     { "vpabsb",         { XM, EXx } },
10702   },
10703   {
10704     /* VEX_W_0F381D_P_2 */
10705     { "vpabsw",         { XM, EXx } },
10706   },
10707   {
10708     /* VEX_W_0F381E_P_2 */
10709     { "vpabsd",         { XM, EXx } },
10710   },
10711   {
10712     /* VEX_W_0F3820_P_2 */
10713     { "vpmovsxbw",      { XM, EXxmmq } },
10714   },
10715   {
10716     /* VEX_W_0F3821_P_2 */
10717     { "vpmovsxbd",      { XM, EXxmmqd } },
10718   },
10719   {
10720     /* VEX_W_0F3822_P_2 */
10721     { "vpmovsxbq",      { XM, EXxmmdw } },
10722   },
10723   {
10724     /* VEX_W_0F3823_P_2 */
10725     { "vpmovsxwd",      { XM, EXxmmq } },
10726   },
10727   {
10728     /* VEX_W_0F3824_P_2 */
10729     { "vpmovsxwq",      { XM, EXxmmqd } },
10730   },
10731   {
10732     /* VEX_W_0F3825_P_2 */
10733     { "vpmovsxdq",      { XM, EXxmmq } },
10734   },
10735   {
10736     /* VEX_W_0F3828_P_2 */
10737     { "vpmuldq",        { XM, Vex, EXx } },
10738   },
10739   {
10740     /* VEX_W_0F3829_P_2 */
10741     { "vpcmpeqq",       { XM, Vex, EXx } },
10742   },
10743   {
10744     /* VEX_W_0F382A_P_2_M_0 */
10745     { "vmovntdqa",      { XM, Mx } },
10746   },
10747   {
10748     /* VEX_W_0F382B_P_2 */
10749     { "vpackusdw",      { XM, Vex, EXx } },
10750   },
10751   {
10752     /* VEX_W_0F382C_P_2_M_0 */
10753     { "vmaskmovps",     { XM, Vex, Mx } },
10754   },
10755   {
10756     /* VEX_W_0F382D_P_2_M_0 */
10757     { "vmaskmovpd",     { XM, Vex, Mx } },
10758   },
10759   {
10760     /* VEX_W_0F382E_P_2_M_0 */
10761     { "vmaskmovps",     { Mx, Vex, XM } },
10762   },
10763   {
10764     /* VEX_W_0F382F_P_2_M_0 */
10765     { "vmaskmovpd",     { Mx, Vex, XM } },
10766   },
10767   {
10768     /* VEX_W_0F3830_P_2 */
10769     { "vpmovzxbw",      { XM, EXxmmq } },
10770   },
10771   {
10772     /* VEX_W_0F3831_P_2 */
10773     { "vpmovzxbd",      { XM, EXxmmqd } },
10774   },
10775   {
10776     /* VEX_W_0F3832_P_2 */
10777     { "vpmovzxbq",      { XM, EXxmmdw } },
10778   },
10779   {
10780     /* VEX_W_0F3833_P_2 */
10781     { "vpmovzxwd",      { XM, EXxmmq } },
10782   },
10783   {
10784     /* VEX_W_0F3834_P_2 */
10785     { "vpmovzxwq",      { XM, EXxmmqd } },
10786   },
10787   {
10788     /* VEX_W_0F3835_P_2 */
10789     { "vpmovzxdq",      { XM, EXxmmq } },
10790   },
10791   {
10792     /* VEX_W_0F3836_P_2  */
10793     { "vpermd",         { XM, Vex, EXx } },
10794   },
10795   {
10796     /* VEX_W_0F3837_P_2 */
10797     { "vpcmpgtq",       { XM, Vex, EXx } },
10798   },
10799   {
10800     /* VEX_W_0F3838_P_2 */
10801     { "vpminsb",        { XM, Vex, EXx } },
10802   },
10803   {
10804     /* VEX_W_0F3839_P_2 */
10805     { "vpminsd",        { XM, Vex, EXx } },
10806   },
10807   {
10808     /* VEX_W_0F383A_P_2 */
10809     { "vpminuw",        { XM, Vex, EXx } },
10810   },
10811   {
10812     /* VEX_W_0F383B_P_2 */
10813     { "vpminud",        { XM, Vex, EXx } },
10814   },
10815   {
10816     /* VEX_W_0F383C_P_2 */
10817     { "vpmaxsb",        { XM, Vex, EXx } },
10818   },
10819   {
10820     /* VEX_W_0F383D_P_2 */
10821     { "vpmaxsd",        { XM, Vex, EXx } },
10822   },
10823   {
10824     /* VEX_W_0F383E_P_2 */
10825     { "vpmaxuw",        { XM, Vex, EXx } },
10826   },
10827   {
10828     /* VEX_W_0F383F_P_2 */
10829     { "vpmaxud",        { XM, Vex, EXx } },
10830   },
10831   {
10832     /* VEX_W_0F3840_P_2 */
10833     { "vpmulld",        { XM, Vex, EXx } },
10834   },
10835   {
10836     /* VEX_W_0F3841_P_2 */
10837     { "vphminposuw",    { XM, EXx } },
10838   },
10839   {
10840     /* VEX_W_0F3846_P_2 */
10841     { "vpsravd",        { XM, Vex, EXx } },
10842   },
10843   {
10844     /* VEX_W_0F3858_P_2 */
10845     { "vpbroadcastd", { XM, EXxmm_md } },
10846   },
10847   {
10848     /* VEX_W_0F3859_P_2 */
10849     { "vpbroadcastq",   { XM, EXxmm_mq } },
10850   },
10851   {
10852     /* VEX_W_0F385A_P_2_M_0 */
10853     { "vbroadcasti128", { XM, Mxmm } },
10854   },
10855   {
10856     /* VEX_W_0F3878_P_2 */
10857     { "vpbroadcastb",   { XM, EXxmm_mb } },
10858   },
10859   {
10860     /* VEX_W_0F3879_P_2 */
10861     { "vpbroadcastw",   { XM, EXxmm_mw } },
10862   },
10863   {
10864     /* VEX_W_0F38DB_P_2 */
10865     { "vaesimc",        { XM, EXx } },
10866   },
10867   {
10868     /* VEX_W_0F38DC_P_2 */
10869     { "vaesenc",        { XM, Vex128, EXx } },
10870   },
10871   {
10872     /* VEX_W_0F38DD_P_2 */
10873     { "vaesenclast",    { XM, Vex128, EXx } },
10874   },
10875   {
10876     /* VEX_W_0F38DE_P_2 */
10877     { "vaesdec",        { XM, Vex128, EXx } },
10878   },
10879   {
10880     /* VEX_W_0F38DF_P_2 */
10881     { "vaesdeclast",    { XM, Vex128, EXx } },
10882   },
10883   {
10884     /* VEX_W_0F3A00_P_2 */
10885     { Bad_Opcode },
10886     { "vpermq",         { XM, EXx, Ib } },
10887   },
10888   {
10889     /* VEX_W_0F3A01_P_2 */
10890     { Bad_Opcode },
10891     { "vpermpd",        { XM, EXx, Ib } },
10892   },
10893   {
10894     /* VEX_W_0F3A02_P_2 */
10895     { "vpblendd",       { XM, Vex, EXx, Ib } },
10896   },
10897   {
10898     /* VEX_W_0F3A04_P_2 */
10899     { "vpermilps",      { XM, EXx, Ib } },
10900   },
10901   {
10902     /* VEX_W_0F3A05_P_2 */
10903     { "vpermilpd",      { XM, EXx, Ib } },
10904   },
10905   {
10906     /* VEX_W_0F3A06_P_2 */
10907     { "vperm2f128",     { XM, Vex256, EXx, Ib } },
10908   },
10909   {
10910     /* VEX_W_0F3A08_P_2 */
10911     { "vroundps",       { XM, EXx, Ib } },
10912   },
10913   {
10914     /* VEX_W_0F3A09_P_2 */
10915     { "vroundpd",       { XM, EXx, Ib } },
10916   },
10917   {
10918     /* VEX_W_0F3A0A_P_2 */
10919     { "vroundss",       { XMScalar, VexScalar, EXdScalar, Ib } },
10920   },
10921   {
10922     /* VEX_W_0F3A0B_P_2 */
10923     { "vroundsd",       { XMScalar, VexScalar, EXqScalar, Ib } },
10924   },
10925   {
10926     /* VEX_W_0F3A0C_P_2 */
10927     { "vblendps",       { XM, Vex, EXx, Ib } },
10928   },
10929   {
10930     /* VEX_W_0F3A0D_P_2 */
10931     { "vblendpd",       { XM, Vex, EXx, Ib } },
10932   },
10933   {
10934     /* VEX_W_0F3A0E_P_2 */
10935     { "vpblendw",       { XM, Vex, EXx, Ib } },
10936   },
10937   {
10938     /* VEX_W_0F3A0F_P_2 */
10939     { "vpalignr",       { XM, Vex, EXx, Ib } },
10940   },
10941   {
10942     /* VEX_W_0F3A14_P_2 */
10943     { "vpextrb",        { Edqb, XM, Ib } },
10944   },
10945   {
10946     /* VEX_W_0F3A15_P_2 */
10947     { "vpextrw",        { Edqw, XM, Ib } },
10948   },
10949   {
10950     /* VEX_W_0F3A18_P_2 */
10951     { "vinsertf128",    { XM, Vex256, EXxmm, Ib } },
10952   },
10953   {
10954     /* VEX_W_0F3A19_P_2 */
10955     { "vextractf128",   { EXxmm, XM, Ib } },
10956   },
10957   {
10958     /* VEX_W_0F3A20_P_2 */
10959     { "vpinsrb",        { XM, Vex128, Edqb, Ib } },
10960   },
10961   {
10962     /* VEX_W_0F3A21_P_2 */
10963     { "vinsertps",      { XM, Vex128, EXd, Ib } },
10964   },
10965   {
10966     /* VEX_W_0F3A30_P_2 */
10967     { Bad_Opcode },
10968     { "kshiftrw",       { MaskG, MaskR, Ib } },
10969   },
10970   {
10971     /* VEX_W_0F3A32_P_2 */
10972     { Bad_Opcode },
10973     { "kshiftlw",       { MaskG, MaskR, Ib } },
10974   },
10975   {
10976     /* VEX_W_0F3A38_P_2 */
10977     { "vinserti128",    { XM, Vex256, EXxmm, Ib } },
10978   },
10979   {
10980     /* VEX_W_0F3A39_P_2 */
10981     { "vextracti128",   { EXxmm, XM, Ib } },
10982   },
10983   {
10984     /* VEX_W_0F3A40_P_2 */
10985     { "vdpps",          { XM, Vex, EXx, Ib } },
10986   },
10987   {
10988     /* VEX_W_0F3A41_P_2 */
10989     { "vdppd",          { XM, Vex128, EXx, Ib } },
10990   },
10991   {
10992     /* VEX_W_0F3A42_P_2 */
10993     { "vmpsadbw",       { XM, Vex, EXx, Ib } },
10994   },
10995   {
10996     /* VEX_W_0F3A44_P_2 */
10997     { "vpclmulqdq",     { XM, Vex128, EXx, PCLMUL } },
10998   },
10999   {
11000     /* VEX_W_0F3A46_P_2 */
11001     { "vperm2i128",     { XM, Vex256, EXx, Ib } },
11002   },
11003   {
11004     /* VEX_W_0F3A48_P_2 */
11005     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
11006     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
11007   },
11008   {
11009     /* VEX_W_0F3A49_P_2 */
11010     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
11011     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
11012   },
11013   {
11014     /* VEX_W_0F3A4A_P_2 */
11015     { "vblendvps",      { XM, Vex, EXx, XMVexI4 } },
11016   },
11017   {
11018     /* VEX_W_0F3A4B_P_2 */
11019     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 } },
11020   },
11021   {
11022     /* VEX_W_0F3A4C_P_2 */
11023     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 } },
11024   },
11025   {
11026     /* VEX_W_0F3A60_P_2 */
11027     { "vpcmpestrm",     { XM, EXx, Ib } },
11028   },
11029   {
11030     /* VEX_W_0F3A61_P_2 */
11031     { "vpcmpestri",     { XM, EXx, Ib } },
11032   },
11033   {
11034     /* VEX_W_0F3A62_P_2 */
11035     { "vpcmpistrm",     { XM, EXx, Ib } },
11036   },
11037   {
11038     /* VEX_W_0F3A63_P_2 */
11039     { "vpcmpistri",     { XM, EXx, Ib } },
11040   },
11041   {
11042     /* VEX_W_0F3ADF_P_2 */
11043     { "vaeskeygenassist", { XM, EXx, Ib } },
11044   },
11045 #define NEED_VEX_W_TABLE
11046 #include "i386-dis-evex.h"
11047 #undef NEED_VEX_W_TABLE
11048 };
11049
11050 static const struct dis386 mod_table[][2] = {
11051   {
11052     /* MOD_8D */
11053     { "leaS",           { Gv, M } },
11054   },
11055   {
11056     /* MOD_C6_REG_7 */
11057     { Bad_Opcode },
11058     { RM_TABLE (RM_C6_REG_7) },
11059   },
11060   {
11061     /* MOD_C7_REG_7 */
11062     { Bad_Opcode },
11063     { RM_TABLE (RM_C7_REG_7) },
11064   },
11065   {
11066     /* MOD_FF_REG_3 */
11067     { "Jcall{T|}", { indirEp } },
11068   },
11069   {
11070     /* MOD_FF_REG_5 */
11071     { "Jjmp{T|}", { indirEp } },
11072   },
11073   {
11074     /* MOD_0F01_REG_0 */
11075     { X86_64_TABLE (X86_64_0F01_REG_0) },
11076     { RM_TABLE (RM_0F01_REG_0) },
11077   },
11078   {
11079     /* MOD_0F01_REG_1 */
11080     { X86_64_TABLE (X86_64_0F01_REG_1) },
11081     { RM_TABLE (RM_0F01_REG_1) },
11082   },
11083   {
11084     /* MOD_0F01_REG_2 */
11085     { X86_64_TABLE (X86_64_0F01_REG_2) },
11086     { RM_TABLE (RM_0F01_REG_2) },
11087   },
11088   {
11089     /* MOD_0F01_REG_3 */
11090     { X86_64_TABLE (X86_64_0F01_REG_3) },
11091     { RM_TABLE (RM_0F01_REG_3) },
11092   },
11093   {
11094     /* MOD_0F01_REG_7 */
11095     { "invlpg",         { Mb } },
11096     { RM_TABLE (RM_0F01_REG_7) },
11097   },
11098   {
11099     /* MOD_0F12_PREFIX_0 */
11100     { "movlps",         { XM, EXq } },
11101     { "movhlps",        { XM, EXq } },
11102   },
11103   {
11104     /* MOD_0F13 */
11105     { "movlpX",         { EXq, XM } },
11106   },
11107   {
11108     /* MOD_0F16_PREFIX_0 */
11109     { "movhps",         { XM, EXq } },
11110     { "movlhps",        { XM, EXq } },
11111   },
11112   {
11113     /* MOD_0F17 */
11114     { "movhpX",         { EXq, XM } },
11115   },
11116   {
11117     /* MOD_0F18_REG_0 */
11118     { "prefetchnta",    { Mb } },
11119   },
11120   {
11121     /* MOD_0F18_REG_1 */
11122     { "prefetcht0",     { Mb } },
11123   },
11124   {
11125     /* MOD_0F18_REG_2 */
11126     { "prefetcht1",     { Mb } },
11127   },
11128   {
11129     /* MOD_0F18_REG_3 */
11130     { "prefetcht2",     { Mb } },
11131   },
11132   {
11133     /* MOD_0F18_REG_4 */
11134     { "nop/reserved",   { Mb } },
11135   },
11136   {
11137     /* MOD_0F18_REG_5 */
11138     { "nop/reserved",   { Mb } },
11139   },
11140   {
11141     /* MOD_0F18_REG_6 */
11142     { "nop/reserved",   { Mb } },
11143   },
11144   {
11145     /* MOD_0F18_REG_7 */
11146     { "nop/reserved",   { Mb } },
11147   },
11148   {
11149     /* MOD_0F1A_PREFIX_0 */
11150     { "bndldx",         { Gbnd, Ev_bnd } },
11151     { "nopQ",           { Ev } },
11152   },
11153   {
11154     /* MOD_0F1B_PREFIX_0 */
11155     { "bndstx",         { Ev_bnd, Gbnd } },
11156     { "nopQ",           { Ev } },
11157   },
11158   {
11159     /* MOD_0F1B_PREFIX_1 */
11160     { "bndmk",          { Gbnd, Ev_bnd } },
11161     { "nopQ",           { Ev } },
11162   },
11163   {
11164     /* MOD_0F20 */
11165     { Bad_Opcode },
11166     { "movZ",           { Rm, Cm } },
11167   },
11168   {
11169     /* MOD_0F21 */
11170     { Bad_Opcode },
11171     { "movZ",           { Rm, Dm } },
11172   },
11173   {
11174     /* MOD_0F22 */
11175     { Bad_Opcode },
11176     { "movZ",           { Cm, Rm } },
11177   },
11178   {
11179     /* MOD_0F23 */
11180     { Bad_Opcode },
11181     { "movZ",           { Dm, Rm } },
11182   },
11183   {
11184     /* MOD_0F24 */
11185     { Bad_Opcode },
11186     { "movL",           { Rd, Td } },
11187   },
11188   {
11189     /* MOD_0F26 */
11190     { Bad_Opcode },
11191     { "movL",           { Td, Rd } },
11192   },
11193   {
11194     /* MOD_0F2B_PREFIX_0 */
11195     {"movntps",         { Mx, XM } },
11196   },
11197   {
11198     /* MOD_0F2B_PREFIX_1 */
11199     {"movntss",         { Md, XM } },
11200   },
11201   {
11202     /* MOD_0F2B_PREFIX_2 */
11203     {"movntpd",         { Mx, XM } },
11204   },
11205   {
11206     /* MOD_0F2B_PREFIX_3 */
11207     {"movntsd",         { Mq, XM } },
11208   },
11209   {
11210     /* MOD_0F51 */
11211     { Bad_Opcode },
11212     { "movmskpX",       { Gdq, XS } },
11213   },
11214   {
11215     /* MOD_0F71_REG_2 */
11216     { Bad_Opcode },
11217     { "psrlw",          { MS, Ib } },
11218   },
11219   {
11220     /* MOD_0F71_REG_4 */
11221     { Bad_Opcode },
11222     { "psraw",          { MS, Ib } },
11223   },
11224   {
11225     /* MOD_0F71_REG_6 */
11226     { Bad_Opcode },
11227     { "psllw",          { MS, Ib } },
11228   },
11229   {
11230     /* MOD_0F72_REG_2 */
11231     { Bad_Opcode },
11232     { "psrld",          { MS, Ib } },
11233   },
11234   {
11235     /* MOD_0F72_REG_4 */
11236     { Bad_Opcode },
11237     { "psrad",          { MS, Ib } },
11238   },
11239   {
11240     /* MOD_0F72_REG_6 */
11241     { Bad_Opcode },
11242     { "pslld",          { MS, Ib } },
11243   },
11244   {
11245     /* MOD_0F73_REG_2 */
11246     { Bad_Opcode },
11247     { "psrlq",          { MS, Ib } },
11248   },
11249   {
11250     /* MOD_0F73_REG_3 */
11251     { Bad_Opcode },
11252     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
11253   },
11254   {
11255     /* MOD_0F73_REG_6 */
11256     { Bad_Opcode },
11257     { "psllq",          { MS, Ib } },
11258   },
11259   {
11260     /* MOD_0F73_REG_7 */
11261     { Bad_Opcode },
11262     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
11263   },
11264   {
11265     /* MOD_0FAE_REG_0 */
11266     { "fxsave",         { FXSAVE } },
11267     { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
11268   },
11269   {
11270     /* MOD_0FAE_REG_1 */
11271     { "fxrstor",        { FXSAVE } },
11272     { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
11273   },
11274   {
11275     /* MOD_0FAE_REG_2 */
11276     { "ldmxcsr",        { Md } },
11277     { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
11278   },
11279   {
11280     /* MOD_0FAE_REG_3 */
11281     { "stmxcsr",        { Md } },
11282     { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
11283   },
11284   {
11285     /* MOD_0FAE_REG_4 */
11286     { "xsave",          { FXSAVE } },
11287   },
11288   {
11289     /* MOD_0FAE_REG_5 */
11290     { "xrstor",         { FXSAVE } },
11291     { RM_TABLE (RM_0FAE_REG_5) },
11292   },
11293   {
11294     /* MOD_0FAE_REG_6 */
11295     { "xsaveopt",       { FXSAVE } },
11296     { RM_TABLE (RM_0FAE_REG_6) },
11297   },
11298   {
11299     /* MOD_0FAE_REG_7 */
11300     { PREFIX_TABLE (PREFIX_0FAE_REG_7) },
11301     { RM_TABLE (RM_0FAE_REG_7) },
11302   },
11303   {
11304     /* MOD_0FB2 */
11305     { "lssS",           { Gv, Mp } },
11306   },
11307   {
11308     /* MOD_0FB4 */
11309     { "lfsS",           { Gv, Mp } },
11310   },
11311   {
11312     /* MOD_0FB5 */
11313     { "lgsS",           { Gv, Mp } },
11314   },
11315   {
11316     /* MOD_0FC7_REG_3 */
11317     { "xrstors",                { FXSAVE } },
11318   },
11319   {
11320     /* MOD_0FC7_REG_4 */
11321     { "xsavec",         { FXSAVE } },
11322   },
11323   {
11324     /* MOD_0FC7_REG_5 */
11325     { "xsaves",         { FXSAVE } },
11326   },
11327   {
11328     /* MOD_0FC7_REG_6 */
11329     { PREFIX_TABLE (PREFIX_0FC7_REG_6) },
11330     { "rdrand",         { Ev } },
11331   },
11332   {
11333     /* MOD_0FC7_REG_7 */
11334     { "vmptrst",        { Mq } },
11335     { "rdseed",         { Ev } },
11336   },
11337   {
11338     /* MOD_0FD7 */
11339     { Bad_Opcode },
11340     { "pmovmskb",       { Gdq, MS } },
11341   },
11342   {
11343     /* MOD_0FE7_PREFIX_2 */
11344     { "movntdq",        { Mx, XM } },
11345   },
11346   {
11347     /* MOD_0FF0_PREFIX_3 */
11348     { "lddqu",          { XM, M } },
11349   },
11350   {
11351     /* MOD_0F382A_PREFIX_2 */
11352     { "movntdqa",       { XM, Mx } },
11353   },
11354   {
11355     /* MOD_62_32BIT */
11356     { "bound{S|}",      { Gv, Ma } },
11357     { EVEX_TABLE (EVEX_0F) },
11358   },
11359   {
11360     /* MOD_C4_32BIT */
11361     { "lesS",           { Gv, Mp } },
11362     { VEX_C4_TABLE (VEX_0F) },
11363   },
11364   {
11365     /* MOD_C5_32BIT */
11366     { "ldsS",           { Gv, Mp } },
11367     { VEX_C5_TABLE (VEX_0F) },
11368   },
11369   {
11370     /* MOD_VEX_0F12_PREFIX_0 */
11371     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
11372     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
11373   },
11374   {
11375     /* MOD_VEX_0F13 */
11376     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
11377   },
11378   {
11379     /* MOD_VEX_0F16_PREFIX_0 */
11380     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
11381     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
11382   },
11383   {
11384     /* MOD_VEX_0F17 */
11385     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
11386   },
11387   {
11388     /* MOD_VEX_0F2B */
11389     { VEX_W_TABLE (VEX_W_0F2B_M_0) },
11390   },
11391   {
11392     /* MOD_VEX_0F50 */
11393     { Bad_Opcode },
11394     { VEX_W_TABLE (VEX_W_0F50_M_0) },
11395   },
11396   {
11397     /* MOD_VEX_0F71_REG_2 */
11398     { Bad_Opcode },
11399     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
11400   },
11401   {
11402     /* MOD_VEX_0F71_REG_4 */
11403     { Bad_Opcode },
11404     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
11405   },
11406   {
11407     /* MOD_VEX_0F71_REG_6 */
11408     { Bad_Opcode },
11409     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
11410   },
11411   {
11412     /* MOD_VEX_0F72_REG_2 */
11413     { Bad_Opcode },
11414     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
11415   },
11416   {
11417     /* MOD_VEX_0F72_REG_4 */
11418     { Bad_Opcode },
11419     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
11420   },
11421   {
11422     /* MOD_VEX_0F72_REG_6 */
11423     { Bad_Opcode },
11424     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
11425   },
11426   {
11427     /* MOD_VEX_0F73_REG_2 */
11428     { Bad_Opcode },
11429     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
11430   },
11431   {
11432     /* MOD_VEX_0F73_REG_3 */
11433     { Bad_Opcode },
11434     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
11435   },
11436   {
11437     /* MOD_VEX_0F73_REG_6 */
11438     { Bad_Opcode },
11439     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
11440   },
11441   {
11442     /* MOD_VEX_0F73_REG_7 */
11443     { Bad_Opcode },
11444     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
11445   },
11446   {
11447     /* MOD_VEX_0FAE_REG_2 */
11448     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
11449   },
11450   {
11451     /* MOD_VEX_0FAE_REG_3 */
11452     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
11453   },
11454   {
11455     /* MOD_VEX_0FD7_PREFIX_2 */
11456     { Bad_Opcode },
11457     { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) },
11458   },
11459   {
11460     /* MOD_VEX_0FE7_PREFIX_2 */
11461     { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) },
11462   },
11463   {
11464     /* MOD_VEX_0FF0_PREFIX_3 */
11465     { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) },
11466   },
11467   {
11468     /* MOD_VEX_0F381A_PREFIX_2 */
11469     { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
11470   },
11471   {
11472     /* MOD_VEX_0F382A_PREFIX_2 */
11473     { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) },
11474   },
11475   {
11476     /* MOD_VEX_0F382C_PREFIX_2 */
11477     { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
11478   },
11479   {
11480     /* MOD_VEX_0F382D_PREFIX_2 */
11481     { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
11482   },
11483   {
11484     /* MOD_VEX_0F382E_PREFIX_2 */
11485     { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
11486   },
11487   {
11488     /* MOD_VEX_0F382F_PREFIX_2 */
11489     { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
11490   },
11491   {
11492     /* MOD_VEX_0F385A_PREFIX_2 */
11493     { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
11494   },
11495   {
11496     /* MOD_VEX_0F388C_PREFIX_2 */
11497     { "vpmaskmov%LW",   { XM, Vex, Mx } },
11498   },
11499   {
11500     /* MOD_VEX_0F388E_PREFIX_2 */
11501     { "vpmaskmov%LW",   { Mx, Vex, XM } },
11502   },
11503 #define NEED_MOD_TABLE
11504 #include "i386-dis-evex.h"
11505 #undef NEED_MOD_TABLE
11506 };
11507
11508 static const struct dis386 rm_table[][8] = {
11509   {
11510     /* RM_C6_REG_7 */
11511     { "xabort",         { Skip_MODRM, Ib } },
11512   },
11513   {
11514     /* RM_C7_REG_7 */
11515     { "xbeginT",        { Skip_MODRM, Jv } },
11516   },
11517   {
11518     /* RM_0F01_REG_0 */
11519     { Bad_Opcode },
11520     { "vmcall",         { Skip_MODRM } },
11521     { "vmlaunch",       { Skip_MODRM } },
11522     { "vmresume",       { Skip_MODRM } },
11523     { "vmxoff",         { Skip_MODRM } },
11524   },
11525   {
11526     /* RM_0F01_REG_1 */
11527     { "monitor",        { { OP_Monitor, 0 } } },
11528     { "mwait",          { { OP_Mwait, 0 } } },
11529     { "clac",           { Skip_MODRM } },
11530     { "stac",           { Skip_MODRM } },
11531   },
11532   {
11533     /* RM_0F01_REG_2 */
11534     { "xgetbv",         { Skip_MODRM } },
11535     { "xsetbv",         { Skip_MODRM } },
11536     { Bad_Opcode },
11537     { Bad_Opcode },
11538     { "vmfunc",         { Skip_MODRM } },
11539     { "xend",           { Skip_MODRM } },
11540     { "xtest",          { Skip_MODRM } },
11541     { Bad_Opcode },
11542   },
11543   {
11544     /* RM_0F01_REG_3 */
11545     { "vmrun",          { Skip_MODRM } },
11546     { "vmmcall",        { Skip_MODRM } },
11547     { "vmload",         { Skip_MODRM } },
11548     { "vmsave",         { Skip_MODRM } },
11549     { "stgi",           { Skip_MODRM } },
11550     { "clgi",           { Skip_MODRM } },
11551     { "skinit",         { Skip_MODRM } },
11552     { "invlpga",        { Skip_MODRM } },
11553   },
11554   {
11555     /* RM_0F01_REG_7 */
11556     { "swapgs",         { Skip_MODRM } },
11557     { "rdtscp",         { Skip_MODRM } },
11558   },
11559   {
11560     /* RM_0FAE_REG_5 */
11561     { "lfence",         { Skip_MODRM } },
11562   },
11563   {
11564     /* RM_0FAE_REG_6 */
11565     { "mfence",         { Skip_MODRM } },
11566   },
11567   {
11568     /* RM_0FAE_REG_7 */
11569     { "sfence",         { Skip_MODRM } },
11570   },
11571 };
11572
11573 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
11574
11575 /* We use the high bit to indicate different name for the same
11576    prefix.  */
11577 #define ADDR16_PREFIX   (0x67 | 0x100)
11578 #define ADDR32_PREFIX   (0x67 | 0x200)
11579 #define DATA16_PREFIX   (0x66 | 0x100)
11580 #define DATA32_PREFIX   (0x66 | 0x200)
11581 #define REP_PREFIX      (0xf3 | 0x100)
11582 #define XACQUIRE_PREFIX (0xf2 | 0x200)
11583 #define XRELEASE_PREFIX (0xf3 | 0x400)
11584 #define BND_PREFIX      (0xf2 | 0x400)
11585
11586 static int
11587 ckprefix (void)
11588 {
11589   int newrex, i, length;
11590   rex = 0;
11591   rex_ignored = 0;
11592   prefixes = 0;
11593   used_prefixes = 0;
11594   rex_used = 0;
11595   last_lock_prefix = -1;
11596   last_repz_prefix = -1;
11597   last_repnz_prefix = -1;
11598   last_data_prefix = -1;
11599   last_addr_prefix = -1;
11600   last_rex_prefix = -1;
11601   last_seg_prefix = -1;
11602   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
11603     all_prefixes[i] = 0;
11604   i = 0;
11605   length = 0;
11606   /* The maximum instruction length is 15bytes.  */
11607   while (length < MAX_CODE_LENGTH - 1)
11608     {
11609       FETCH_DATA (the_info, codep + 1);
11610       newrex = 0;
11611       switch (*codep)
11612         {
11613         /* REX prefixes family.  */
11614         case 0x40:
11615         case 0x41:
11616         case 0x42:
11617         case 0x43:
11618         case 0x44:
11619         case 0x45:
11620         case 0x46:
11621         case 0x47:
11622         case 0x48:
11623         case 0x49:
11624         case 0x4a:
11625         case 0x4b:
11626         case 0x4c:
11627         case 0x4d:
11628         case 0x4e:
11629         case 0x4f:
11630           if (address_mode == mode_64bit)
11631             newrex = *codep;
11632           else
11633             return 1;
11634           last_rex_prefix = i;
11635           break;
11636         case 0xf3:
11637           prefixes |= PREFIX_REPZ;
11638           last_repz_prefix = i;
11639           break;
11640         case 0xf2:
11641           prefixes |= PREFIX_REPNZ;
11642           last_repnz_prefix = i;
11643           break;
11644         case 0xf0:
11645           prefixes |= PREFIX_LOCK;
11646           last_lock_prefix = i;
11647           break;
11648         case 0x2e:
11649           prefixes |= PREFIX_CS;
11650           last_seg_prefix = i;
11651           break;
11652         case 0x36:
11653           prefixes |= PREFIX_SS;
11654           last_seg_prefix = i;
11655           break;
11656         case 0x3e:
11657           prefixes |= PREFIX_DS;
11658           last_seg_prefix = i;
11659           break;
11660         case 0x26:
11661           prefixes |= PREFIX_ES;
11662           last_seg_prefix = i;
11663           break;
11664         case 0x64:
11665           prefixes |= PREFIX_FS;
11666           last_seg_prefix = i;
11667           break;
11668         case 0x65:
11669           prefixes |= PREFIX_GS;
11670           last_seg_prefix = i;
11671           break;
11672         case 0x66:
11673           prefixes |= PREFIX_DATA;
11674           last_data_prefix = i;
11675           break;
11676         case 0x67:
11677           prefixes |= PREFIX_ADDR;
11678           last_addr_prefix = i;
11679           break;
11680         case FWAIT_OPCODE:
11681           /* fwait is really an instruction.  If there are prefixes
11682              before the fwait, they belong to the fwait, *not* to the
11683              following instruction.  */
11684           if (prefixes || rex)
11685             {
11686               prefixes |= PREFIX_FWAIT;
11687               codep++;
11688               /* This ensures that the previous REX prefixes are noticed
11689                  as unused prefixes, as in the return case below.  */
11690               rex_used = rex;
11691               return 1;
11692             }
11693           prefixes = PREFIX_FWAIT;
11694           break;
11695         default:
11696           return 1;
11697         }
11698       /* Rex is ignored when followed by another prefix.  */
11699       if (rex)
11700         {
11701           rex_used = rex;
11702           return 1;
11703         }
11704       if (*codep != FWAIT_OPCODE)
11705         all_prefixes[i++] = *codep;
11706       rex = newrex;
11707       codep++;
11708       length++;
11709     }
11710   return 0;
11711 }
11712
11713 static int
11714 seg_prefix (int pref)
11715 {
11716   switch (pref)
11717     {
11718     case 0x2e:
11719       return PREFIX_CS;
11720     case 0x36:
11721       return PREFIX_SS;
11722     case 0x3e:
11723       return PREFIX_DS;
11724     case 0x26:
11725       return PREFIX_ES;
11726     case 0x64:
11727       return PREFIX_FS;
11728     case 0x65:
11729       return PREFIX_GS;
11730     default:
11731       return 0;
11732     }
11733 }
11734
11735 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
11736    prefix byte.  */
11737
11738 static const char *
11739 prefix_name (int pref, int sizeflag)
11740 {
11741   static const char *rexes [16] =
11742     {
11743       "rex",            /* 0x40 */
11744       "rex.B",          /* 0x41 */
11745       "rex.X",          /* 0x42 */
11746       "rex.XB",         /* 0x43 */
11747       "rex.R",          /* 0x44 */
11748       "rex.RB",         /* 0x45 */
11749       "rex.RX",         /* 0x46 */
11750       "rex.RXB",        /* 0x47 */
11751       "rex.W",          /* 0x48 */
11752       "rex.WB",         /* 0x49 */
11753       "rex.WX",         /* 0x4a */
11754       "rex.WXB",        /* 0x4b */
11755       "rex.WR",         /* 0x4c */
11756       "rex.WRB",        /* 0x4d */
11757       "rex.WRX",        /* 0x4e */
11758       "rex.WRXB",       /* 0x4f */
11759     };
11760
11761   switch (pref)
11762     {
11763     /* REX prefixes family.  */
11764     case 0x40:
11765     case 0x41:
11766     case 0x42:
11767     case 0x43:
11768     case 0x44:
11769     case 0x45:
11770     case 0x46:
11771     case 0x47:
11772     case 0x48:
11773     case 0x49:
11774     case 0x4a:
11775     case 0x4b:
11776     case 0x4c:
11777     case 0x4d:
11778     case 0x4e:
11779     case 0x4f:
11780       return rexes [pref - 0x40];
11781     case 0xf3:
11782       return "repz";
11783     case 0xf2:
11784       return "repnz";
11785     case 0xf0:
11786       return "lock";
11787     case 0x2e:
11788       return "cs";
11789     case 0x36:
11790       return "ss";
11791     case 0x3e:
11792       return "ds";
11793     case 0x26:
11794       return "es";
11795     case 0x64:
11796       return "fs";
11797     case 0x65:
11798       return "gs";
11799     case 0x66:
11800       return (sizeflag & DFLAG) ? "data16" : "data32";
11801     case 0x67:
11802       if (address_mode == mode_64bit)
11803         return (sizeflag & AFLAG) ? "addr32" : "addr64";
11804       else
11805         return (sizeflag & AFLAG) ? "addr16" : "addr32";
11806     case FWAIT_OPCODE:
11807       return "fwait";
11808     case ADDR16_PREFIX:
11809       return "addr16";
11810     case ADDR32_PREFIX:
11811       return "addr32";
11812     case DATA16_PREFIX:
11813       return "data16";
11814     case DATA32_PREFIX:
11815       return "data32";
11816     case REP_PREFIX:
11817       return "rep";
11818     case XACQUIRE_PREFIX:
11819       return "xacquire";
11820     case XRELEASE_PREFIX:
11821       return "xrelease";
11822     case BND_PREFIX:
11823       return "bnd";
11824     default:
11825       return NULL;
11826     }
11827 }
11828
11829 static char op_out[MAX_OPERANDS][100];
11830 static int op_ad, op_index[MAX_OPERANDS];
11831 static int two_source_ops;
11832 static bfd_vma op_address[MAX_OPERANDS];
11833 static bfd_vma op_riprel[MAX_OPERANDS];
11834 static bfd_vma start_pc;
11835
11836 /*
11837  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
11838  *   (see topic "Redundant prefixes" in the "Differences from 8086"
11839  *   section of the "Virtual 8086 Mode" chapter.)
11840  * 'pc' should be the address of this instruction, it will
11841  *   be used to print the target address if this is a relative jump or call
11842  * The function returns the length of this instruction in bytes.
11843  */
11844
11845 static char intel_syntax;
11846 static char intel_mnemonic = !SYSV386_COMPAT;
11847 static char open_char;
11848 static char close_char;
11849 static char separator_char;
11850 static char scale_char;
11851
11852 /* Here for backwards compatibility.  When gdb stops using
11853    print_insn_i386_att and print_insn_i386_intel these functions can
11854    disappear, and print_insn_i386 be merged into print_insn.  */
11855 int
11856 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
11857 {
11858   intel_syntax = 0;
11859
11860   return print_insn (pc, info);
11861 }
11862
11863 int
11864 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
11865 {
11866   intel_syntax = 1;
11867
11868   return print_insn (pc, info);
11869 }
11870
11871 int
11872 print_insn_i386 (bfd_vma pc, disassemble_info *info)
11873 {
11874   intel_syntax = -1;
11875
11876   return print_insn (pc, info);
11877 }
11878
11879 void
11880 print_i386_disassembler_options (FILE *stream)
11881 {
11882   fprintf (stream, _("\n\
11883 The following i386/x86-64 specific disassembler options are supported for use\n\
11884 with the -M switch (multiple options should be separated by commas):\n"));
11885
11886   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
11887   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
11888   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
11889   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
11890   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
11891   fprintf (stream, _("  att-mnemonic\n"
11892                      "              Display instruction in AT&T mnemonic\n"));
11893   fprintf (stream, _("  intel-mnemonic\n"
11894                      "              Display instruction in Intel mnemonic\n"));
11895   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
11896   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
11897   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
11898   fprintf (stream, _("  data32      Assume 32bit data size\n"));
11899   fprintf (stream, _("  data16      Assume 16bit data size\n"));
11900   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
11901 }
11902
11903 /* Bad opcode.  */
11904 static const struct dis386 bad_opcode = { "(bad)", { XX } };
11905
11906 /* Get a pointer to struct dis386 with a valid name.  */
11907
11908 static const struct dis386 *
11909 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
11910 {
11911   int vindex, vex_table_index;
11912
11913   if (dp->name != NULL)
11914     return dp;
11915
11916   switch (dp->op[0].bytemode)
11917     {
11918     case USE_REG_TABLE:
11919       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
11920       break;
11921
11922     case USE_MOD_TABLE:
11923       vindex = modrm.mod == 0x3 ? 1 : 0;
11924       dp = &mod_table[dp->op[1].bytemode][vindex];
11925       break;
11926
11927     case USE_RM_TABLE:
11928       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
11929       break;
11930
11931     case USE_PREFIX_TABLE:
11932       if (need_vex)
11933         {
11934           /* The prefix in VEX is implicit.  */
11935           switch (vex.prefix)
11936             {
11937             case 0:
11938               vindex = 0;
11939               break;
11940             case REPE_PREFIX_OPCODE:
11941               vindex = 1;
11942               break;
11943             case DATA_PREFIX_OPCODE:
11944               vindex = 2;
11945               break;
11946             case REPNE_PREFIX_OPCODE:
11947               vindex = 3;
11948               break;
11949             default:
11950               abort ();
11951               break;
11952             }
11953         }
11954       else
11955         {
11956           vindex = 0;
11957           used_prefixes |= (prefixes & PREFIX_REPZ);
11958           if (prefixes & PREFIX_REPZ)
11959             {
11960               vindex = 1;
11961               all_prefixes[last_repz_prefix] = 0;
11962             }
11963           else
11964             {
11965               /* We should check PREFIX_REPNZ and PREFIX_REPZ before
11966                  PREFIX_DATA.  */
11967               used_prefixes |= (prefixes & PREFIX_REPNZ);
11968               if (prefixes & PREFIX_REPNZ)
11969                 {
11970                   vindex = 3;
11971                   all_prefixes[last_repnz_prefix] = 0;
11972                 }
11973               else
11974                 {
11975                   used_prefixes |= (prefixes & PREFIX_DATA);
11976                   if (prefixes & PREFIX_DATA)
11977                     {
11978                       vindex = 2;
11979                       all_prefixes[last_data_prefix] = 0;
11980                     }
11981                 }
11982             }
11983         }
11984       dp = &prefix_table[dp->op[1].bytemode][vindex];
11985       break;
11986
11987     case USE_X86_64_TABLE:
11988       vindex = address_mode == mode_64bit ? 1 : 0;
11989       dp = &x86_64_table[dp->op[1].bytemode][vindex];
11990       break;
11991
11992     case USE_3BYTE_TABLE:
11993       FETCH_DATA (info, codep + 2);
11994       vindex = *codep++;
11995       dp = &three_byte_table[dp->op[1].bytemode][vindex];
11996       modrm.mod = (*codep >> 6) & 3;
11997       modrm.reg = (*codep >> 3) & 7;
11998       modrm.rm = *codep & 7;
11999       break;
12000
12001     case USE_VEX_LEN_TABLE:
12002       if (!need_vex)
12003         abort ();
12004
12005       switch (vex.length)
12006         {
12007         case 128:
12008           vindex = 0;
12009           break;
12010         case 256:
12011           vindex = 1;
12012           break;
12013         default:
12014           abort ();
12015           break;
12016         }
12017
12018       dp = &vex_len_table[dp->op[1].bytemode][vindex];
12019       break;
12020
12021     case USE_XOP_8F_TABLE:
12022       FETCH_DATA (info, codep + 3);
12023       /* All bits in the REX prefix are ignored.  */
12024       rex_ignored = rex;
12025       rex = ~(*codep >> 5) & 0x7;
12026
12027       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
12028       switch ((*codep & 0x1f))
12029         {
12030         default:
12031           dp = &bad_opcode;
12032           return dp;
12033         case 0x8:
12034           vex_table_index = XOP_08;
12035           break;
12036         case 0x9:
12037           vex_table_index = XOP_09;
12038           break;
12039         case 0xa:
12040           vex_table_index = XOP_0A;
12041           break;
12042         }
12043       codep++;
12044       vex.w = *codep & 0x80;
12045       if (vex.w && address_mode == mode_64bit)
12046         rex |= REX_W;
12047
12048       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12049       if (address_mode != mode_64bit
12050           && vex.register_specifier > 0x7)
12051         {
12052           dp = &bad_opcode;
12053           return dp;
12054         }
12055
12056       vex.length = (*codep & 0x4) ? 256 : 128;
12057       switch ((*codep & 0x3))
12058         {
12059         case 0:
12060           vex.prefix = 0;
12061           break;
12062         case 1:
12063           vex.prefix = DATA_PREFIX_OPCODE;
12064           break;
12065         case 2:
12066           vex.prefix = REPE_PREFIX_OPCODE;
12067           break;
12068         case 3:
12069           vex.prefix = REPNE_PREFIX_OPCODE;
12070           break;
12071         }
12072       need_vex = 1;
12073       need_vex_reg = 1;
12074       codep++;
12075       vindex = *codep++;
12076       dp = &xop_table[vex_table_index][vindex];
12077
12078       FETCH_DATA (info, codep + 1);
12079       modrm.mod = (*codep >> 6) & 3;
12080       modrm.reg = (*codep >> 3) & 7;
12081       modrm.rm = *codep & 7;
12082       break;
12083
12084     case USE_VEX_C4_TABLE:
12085       /* VEX prefix.  */
12086       FETCH_DATA (info, codep + 3);
12087       /* All bits in the REX prefix are ignored.  */
12088       rex_ignored = rex;
12089       rex = ~(*codep >> 5) & 0x7;
12090       switch ((*codep & 0x1f))
12091         {
12092         default:
12093           dp = &bad_opcode;
12094           return dp;
12095         case 0x1:
12096           vex_table_index = VEX_0F;
12097           break;
12098         case 0x2:
12099           vex_table_index = VEX_0F38;
12100           break;
12101         case 0x3:
12102           vex_table_index = VEX_0F3A;
12103           break;
12104         }
12105       codep++;
12106       vex.w = *codep & 0x80;
12107       if (vex.w && address_mode == mode_64bit)
12108         rex |= REX_W;
12109
12110       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12111       if (address_mode != mode_64bit
12112           && vex.register_specifier > 0x7)
12113         {
12114           dp = &bad_opcode;
12115           return dp;
12116         }
12117
12118       vex.length = (*codep & 0x4) ? 256 : 128;
12119       switch ((*codep & 0x3))
12120         {
12121         case 0:
12122           vex.prefix = 0;
12123           break;
12124         case 1:
12125           vex.prefix = DATA_PREFIX_OPCODE;
12126           break;
12127         case 2:
12128           vex.prefix = REPE_PREFIX_OPCODE;
12129           break;
12130         case 3:
12131           vex.prefix = REPNE_PREFIX_OPCODE;
12132           break;
12133         }
12134       need_vex = 1;
12135       need_vex_reg = 1;
12136       codep++;
12137       vindex = *codep++;
12138       dp = &vex_table[vex_table_index][vindex];
12139       /* There is no MODRM byte for VEX [82|77].  */
12140       if (vindex != 0x77 && vindex != 0x82)
12141         {
12142           FETCH_DATA (info, codep + 1);
12143           modrm.mod = (*codep >> 6) & 3;
12144           modrm.reg = (*codep >> 3) & 7;
12145           modrm.rm = *codep & 7;
12146         }
12147       break;
12148
12149     case USE_VEX_C5_TABLE:
12150       /* VEX prefix.  */
12151       FETCH_DATA (info, codep + 2);
12152       /* All bits in the REX prefix are ignored.  */
12153       rex_ignored = rex;
12154       rex = (*codep & 0x80) ? 0 : REX_R;
12155
12156       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12157       if (address_mode != mode_64bit
12158           && vex.register_specifier > 0x7)
12159         {
12160           dp = &bad_opcode;
12161           return dp;
12162         }
12163
12164       vex.w = 0;
12165
12166       vex.length = (*codep & 0x4) ? 256 : 128;
12167       switch ((*codep & 0x3))
12168         {
12169         case 0:
12170           vex.prefix = 0;
12171           break;
12172         case 1:
12173           vex.prefix = DATA_PREFIX_OPCODE;
12174           break;
12175         case 2:
12176           vex.prefix = REPE_PREFIX_OPCODE;
12177           break;
12178         case 3:
12179           vex.prefix = REPNE_PREFIX_OPCODE;
12180           break;
12181         }
12182       need_vex = 1;
12183       need_vex_reg = 1;
12184       codep++;
12185       vindex = *codep++;
12186       dp = &vex_table[dp->op[1].bytemode][vindex];
12187       /* There is no MODRM byte for VEX [82|77].  */
12188       if (vindex != 0x77 && vindex != 0x82)
12189         {
12190           FETCH_DATA (info, codep + 1);
12191           modrm.mod = (*codep >> 6) & 3;
12192           modrm.reg = (*codep >> 3) & 7;
12193           modrm.rm = *codep & 7;
12194         }
12195       break;
12196
12197     case USE_VEX_W_TABLE:
12198       if (!need_vex)
12199         abort ();
12200
12201       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
12202       break;
12203
12204     case USE_EVEX_TABLE:
12205       two_source_ops = 0;
12206       /* EVEX prefix.  */
12207       vex.evex = 1;
12208       FETCH_DATA (info, codep + 4);
12209       /* All bits in the REX prefix are ignored.  */
12210       rex_ignored = rex;
12211       /* The first byte after 0x62.  */
12212       rex = ~(*codep >> 5) & 0x7;
12213       vex.r = *codep & 0x10;
12214       switch ((*codep & 0xf))
12215         {
12216         default:
12217           return &bad_opcode;
12218         case 0x1:
12219           vex_table_index = EVEX_0F;
12220           break;
12221         case 0x2:
12222           vex_table_index = EVEX_0F38;
12223           break;
12224         case 0x3:
12225           vex_table_index = EVEX_0F3A;
12226           break;
12227         }
12228
12229       /* The second byte after 0x62.  */
12230       codep++;
12231       vex.w = *codep & 0x80;
12232       if (vex.w && address_mode == mode_64bit)
12233         rex |= REX_W;
12234
12235       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12236       if (address_mode != mode_64bit)
12237         {
12238           /* In 16/32-bit mode silently ignore following bits.  */
12239           rex &= ~REX_B;
12240           vex.r = 1;
12241           vex.v = 1;
12242           vex.register_specifier &= 0x7;
12243         }
12244
12245       /* The U bit.  */
12246       if (!(*codep & 0x4))
12247         return &bad_opcode;
12248
12249       switch ((*codep & 0x3))
12250         {
12251         case 0:
12252           vex.prefix = 0;
12253           break;
12254         case 1:
12255           vex.prefix = DATA_PREFIX_OPCODE;
12256           break;
12257         case 2:
12258           vex.prefix = REPE_PREFIX_OPCODE;
12259           break;
12260         case 3:
12261           vex.prefix = REPNE_PREFIX_OPCODE;
12262           break;
12263         }
12264
12265       /* The third byte after 0x62.  */
12266       codep++;
12267
12268       /* Remember the static rounding bits.  */
12269       vex.ll = (*codep >> 5) & 3;
12270       vex.b = (*codep & 0x10) != 0;
12271
12272       vex.v = *codep & 0x8;
12273       vex.mask_register_specifier = *codep & 0x7;
12274       vex.zeroing = *codep & 0x80;
12275
12276       need_vex = 1;
12277       need_vex_reg = 1;
12278       codep++;
12279       vindex = *codep++;
12280       dp = &evex_table[vex_table_index][vindex];
12281       FETCH_DATA (info, codep + 1);
12282       modrm.mod = (*codep >> 6) & 3;
12283       modrm.reg = (*codep >> 3) & 7;
12284       modrm.rm = *codep & 7;
12285
12286       /* Set vector length.  */
12287       if (modrm.mod == 3 && vex.b)
12288         vex.length = 512;
12289       else
12290         {
12291           switch (vex.ll)
12292             {
12293             case 0x0:
12294               vex.length = 128;
12295               break;
12296             case 0x1:
12297               vex.length = 256;
12298               break;
12299             case 0x2:
12300               vex.length = 512;
12301               break;
12302             default:
12303               return &bad_opcode;
12304             }
12305         }
12306       break;
12307
12308     case 0:
12309       dp = &bad_opcode;
12310       break;
12311
12312     default:
12313       abort ();
12314     }
12315
12316   if (dp->name != NULL)
12317     return dp;
12318   else
12319     return get_valid_dis386 (dp, info);
12320 }
12321
12322 static void
12323 get_sib (disassemble_info *info, int sizeflag)
12324 {
12325   /* If modrm.mod == 3, operand must be register.  */
12326   if (need_modrm
12327       && ((sizeflag & AFLAG) || address_mode == mode_64bit)
12328       && modrm.mod != 3
12329       && modrm.rm == 4)
12330     {
12331       FETCH_DATA (info, codep + 2);
12332       sib.index = (codep [1] >> 3) & 7;
12333       sib.scale = (codep [1] >> 6) & 3;
12334       sib.base = codep [1] & 7;
12335     }
12336 }
12337
12338 static int
12339 print_insn (bfd_vma pc, disassemble_info *info)
12340 {
12341   const struct dis386 *dp;
12342   int i;
12343   char *op_txt[MAX_OPERANDS];
12344   int needcomma;
12345   int sizeflag;
12346   const char *p;
12347   struct dis_private priv;
12348   int prefix_length;
12349   int default_prefixes;
12350
12351   priv.orig_sizeflag = AFLAG | DFLAG;
12352   if ((info->mach & bfd_mach_i386_i386) != 0)
12353     address_mode = mode_32bit;
12354   else if (info->mach == bfd_mach_i386_i8086)
12355     {
12356       address_mode = mode_16bit;
12357       priv.orig_sizeflag = 0;
12358     }
12359   else
12360     address_mode = mode_64bit;
12361
12362   if (intel_syntax == (char) -1)
12363     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
12364
12365   for (p = info->disassembler_options; p != NULL; )
12366     {
12367       if (CONST_STRNEQ (p, "x86-64"))
12368         {
12369           address_mode = mode_64bit;
12370           priv.orig_sizeflag = AFLAG | DFLAG;
12371         }
12372       else if (CONST_STRNEQ (p, "i386"))
12373         {
12374           address_mode = mode_32bit;
12375           priv.orig_sizeflag = AFLAG | DFLAG;
12376         }
12377       else if (CONST_STRNEQ (p, "i8086"))
12378         {
12379           address_mode = mode_16bit;
12380           priv.orig_sizeflag = 0;
12381         }
12382       else if (CONST_STRNEQ (p, "intel"))
12383         {
12384           intel_syntax = 1;
12385           if (CONST_STRNEQ (p + 5, "-mnemonic"))
12386             intel_mnemonic = 1;
12387         }
12388       else if (CONST_STRNEQ (p, "att"))
12389         {
12390           intel_syntax = 0;
12391           if (CONST_STRNEQ (p + 3, "-mnemonic"))
12392             intel_mnemonic = 0;
12393         }
12394       else if (CONST_STRNEQ (p, "addr"))
12395         {
12396           if (address_mode == mode_64bit)
12397             {
12398               if (p[4] == '3' && p[5] == '2')
12399                 priv.orig_sizeflag &= ~AFLAG;
12400               else if (p[4] == '6' && p[5] == '4')
12401                 priv.orig_sizeflag |= AFLAG;
12402             }
12403           else
12404             {
12405               if (p[4] == '1' && p[5] == '6')
12406                 priv.orig_sizeflag &= ~AFLAG;
12407               else if (p[4] == '3' && p[5] == '2')
12408                 priv.orig_sizeflag |= AFLAG;
12409             }
12410         }
12411       else if (CONST_STRNEQ (p, "data"))
12412         {
12413           if (p[4] == '1' && p[5] == '6')
12414             priv.orig_sizeflag &= ~DFLAG;
12415           else if (p[4] == '3' && p[5] == '2')
12416             priv.orig_sizeflag |= DFLAG;
12417         }
12418       else if (CONST_STRNEQ (p, "suffix"))
12419         priv.orig_sizeflag |= SUFFIX_ALWAYS;
12420
12421       p = strchr (p, ',');
12422       if (p != NULL)
12423         p++;
12424     }
12425
12426   if (intel_syntax)
12427     {
12428       names64 = intel_names64;
12429       names32 = intel_names32;
12430       names16 = intel_names16;
12431       names8 = intel_names8;
12432       names8rex = intel_names8rex;
12433       names_seg = intel_names_seg;
12434       names_mm = intel_names_mm;
12435       names_bnd = intel_names_bnd;
12436       names_xmm = intel_names_xmm;
12437       names_ymm = intel_names_ymm;
12438       names_zmm = intel_names_zmm;
12439       index64 = intel_index64;
12440       index32 = intel_index32;
12441       names_mask = intel_names_mask;
12442       index16 = intel_index16;
12443       open_char = '[';
12444       close_char = ']';
12445       separator_char = '+';
12446       scale_char = '*';
12447     }
12448   else
12449     {
12450       names64 = att_names64;
12451       names32 = att_names32;
12452       names16 = att_names16;
12453       names8 = att_names8;
12454       names8rex = att_names8rex;
12455       names_seg = att_names_seg;
12456       names_mm = att_names_mm;
12457       names_bnd = att_names_bnd;
12458       names_xmm = att_names_xmm;
12459       names_ymm = att_names_ymm;
12460       names_zmm = att_names_zmm;
12461       index64 = att_index64;
12462       index32 = att_index32;
12463       names_mask = att_names_mask;
12464       index16 = att_index16;
12465       open_char = '(';
12466       close_char =  ')';
12467       separator_char = ',';
12468       scale_char = ',';
12469     }
12470
12471   /* The output looks better if we put 7 bytes on a line, since that
12472      puts most long word instructions on a single line.  Use 8 bytes
12473      for Intel L1OM.  */
12474   if ((info->mach & bfd_mach_l1om) != 0)
12475     info->bytes_per_line = 8;
12476   else
12477     info->bytes_per_line = 7;
12478
12479   info->private_data = &priv;
12480   priv.max_fetched = priv.the_buffer;
12481   priv.insn_start = pc;
12482
12483   obuf[0] = 0;
12484   for (i = 0; i < MAX_OPERANDS; ++i)
12485     {
12486       op_out[i][0] = 0;
12487       op_index[i] = -1;
12488     }
12489
12490   the_info = info;
12491   start_pc = pc;
12492   start_codep = priv.the_buffer;
12493   codep = priv.the_buffer;
12494
12495   if (setjmp (priv.bailout) != 0)
12496     {
12497       const char *name;
12498
12499       /* Getting here means we tried for data but didn't get it.  That
12500          means we have an incomplete instruction of some sort.  Just
12501          print the first byte as a prefix or a .byte pseudo-op.  */
12502       if (codep > priv.the_buffer)
12503         {
12504           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
12505           if (name != NULL)
12506             (*info->fprintf_func) (info->stream, "%s", name);
12507           else
12508             {
12509               /* Just print the first byte as a .byte instruction.  */
12510               (*info->fprintf_func) (info->stream, ".byte 0x%x",
12511                                      (unsigned int) priv.the_buffer[0]);
12512             }
12513
12514           return 1;
12515         }
12516
12517       return -1;
12518     }
12519
12520   obufp = obuf;
12521   sizeflag = priv.orig_sizeflag;
12522
12523   if (!ckprefix () || rex_used)
12524     {
12525       /* Too many prefixes or unused REX prefixes.  */
12526       for (i = 0;
12527            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
12528            i++)
12529         (*info->fprintf_func) (info->stream, "%s%s",
12530                                i == 0 ? "" : " ",
12531                                prefix_name (all_prefixes[i], sizeflag));
12532       return i;
12533     }
12534
12535   insn_codep = codep;
12536
12537   FETCH_DATA (info, codep + 1);
12538   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
12539
12540   if (((prefixes & PREFIX_FWAIT)
12541        && ((*codep < 0xd8) || (*codep > 0xdf))))
12542     {
12543       (*info->fprintf_func) (info->stream, "fwait");
12544       return 1;
12545     }
12546
12547   if (*codep == 0x0f)
12548     {
12549       unsigned char threebyte;
12550       FETCH_DATA (info, codep + 2);
12551       threebyte = *++codep;
12552       dp = &dis386_twobyte[threebyte];
12553       need_modrm = twobyte_has_modrm[*codep];
12554       codep++;
12555     }
12556   else
12557     {
12558       dp = &dis386[*codep];
12559       need_modrm = onebyte_has_modrm[*codep];
12560       codep++;
12561     }
12562
12563   if ((prefixes & PREFIX_REPZ))
12564     used_prefixes |= PREFIX_REPZ;
12565   if ((prefixes & PREFIX_REPNZ))
12566     used_prefixes |= PREFIX_REPNZ;
12567   if ((prefixes & PREFIX_LOCK))
12568     used_prefixes |= PREFIX_LOCK;
12569
12570   default_prefixes = 0;
12571   if (prefixes & PREFIX_ADDR)
12572     {
12573       sizeflag ^= AFLAG;
12574       if (dp->op[2].bytemode != loop_jcxz_mode || intel_syntax)
12575         {
12576           if ((sizeflag & AFLAG) || address_mode == mode_64bit)
12577             all_prefixes[last_addr_prefix] = ADDR32_PREFIX;
12578           else
12579             all_prefixes[last_addr_prefix] = ADDR16_PREFIX;
12580           default_prefixes |= PREFIX_ADDR;
12581         }
12582     }
12583
12584   if ((prefixes & PREFIX_DATA))
12585     {
12586       sizeflag ^= DFLAG;
12587       if (dp->op[2].bytemode == cond_jump_mode
12588           && dp->op[0].bytemode == v_mode
12589           && !intel_syntax)
12590         {
12591           if (sizeflag & DFLAG)
12592             all_prefixes[last_data_prefix] = DATA32_PREFIX;
12593           else
12594             all_prefixes[last_data_prefix] = DATA16_PREFIX;
12595           default_prefixes |= PREFIX_DATA;
12596         }
12597       else if (rex & REX_W)
12598         {
12599           /* REX_W will override PREFIX_DATA.  */
12600           default_prefixes |= PREFIX_DATA;
12601         }
12602     }
12603
12604   if (need_modrm)
12605     {
12606       FETCH_DATA (info, codep + 1);
12607       modrm.mod = (*codep >> 6) & 3;
12608       modrm.reg = (*codep >> 3) & 7;
12609       modrm.rm = *codep & 7;
12610     }
12611
12612   need_vex = 0;
12613   need_vex_reg = 0;
12614   vex_w_done = 0;
12615   vex.evex = 0;
12616
12617   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
12618     {
12619       get_sib (info, sizeflag);
12620       dofloat (sizeflag);
12621     }
12622   else
12623     {
12624       dp = get_valid_dis386 (dp, info);
12625       if (dp != NULL && putop (dp->name, sizeflag) == 0)
12626         {
12627           get_sib (info, sizeflag);
12628           for (i = 0; i < MAX_OPERANDS; ++i)
12629             {
12630               obufp = op_out[i];
12631               op_ad = MAX_OPERANDS - 1 - i;
12632               if (dp->op[i].rtn)
12633                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
12634               /* For EVEX instruction after the last operand masking
12635                  should be printed.  */
12636               if (i == 0 && vex.evex)
12637                 {
12638                   /* Don't print {%k0}.  */
12639                   if (vex.mask_register_specifier)
12640                     {
12641                       oappend ("{");
12642                       oappend (names_mask[vex.mask_register_specifier]);
12643                       oappend ("}");
12644                     }
12645                   if (vex.zeroing)
12646                     oappend ("{z}");
12647                 }
12648             }
12649         }
12650     }
12651
12652   /* See if any prefixes were not used.  If so, print the first one
12653      separately.  If we don't do this, we'll wind up printing an
12654      instruction stream which does not precisely correspond to the
12655      bytes we are disassembling.  */
12656   if ((prefixes & ~(used_prefixes | default_prefixes)) != 0)
12657     {
12658       for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12659         if (all_prefixes[i])
12660           {
12661             const char *name;
12662             name = prefix_name (all_prefixes[i], priv.orig_sizeflag);
12663             if (name == NULL)
12664               name = INTERNAL_DISASSEMBLER_ERROR;
12665             (*info->fprintf_func) (info->stream, "%s", name);
12666             return 1;
12667           }
12668     }
12669
12670   /* Check if the REX prefix is used.  */
12671   if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)
12672     all_prefixes[last_rex_prefix] = 0;
12673
12674   /* Check if the SEG prefix is used.  */
12675   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
12676                    | PREFIX_FS | PREFIX_GS)) != 0
12677       && (used_prefixes
12678           & seg_prefix (all_prefixes[last_seg_prefix])) != 0)
12679     all_prefixes[last_seg_prefix] = 0;
12680
12681   /* Check if the ADDR prefix is used.  */
12682   if ((prefixes & PREFIX_ADDR) != 0
12683       && (used_prefixes & PREFIX_ADDR) != 0)
12684     all_prefixes[last_addr_prefix] = 0;
12685
12686   /* Check if the DATA prefix is used.  */
12687   if ((prefixes & PREFIX_DATA) != 0
12688       && (used_prefixes & PREFIX_DATA) != 0)
12689     all_prefixes[last_data_prefix] = 0;
12690
12691   prefix_length = 0;
12692   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12693     if (all_prefixes[i])
12694       {
12695         const char *name;
12696         name = prefix_name (all_prefixes[i], sizeflag);
12697         if (name == NULL)
12698           abort ();
12699         prefix_length += strlen (name) + 1;
12700         (*info->fprintf_func) (info->stream, "%s ", name);
12701       }
12702
12703   /* Check maximum code length.  */
12704   if ((codep - start_codep) > MAX_CODE_LENGTH)
12705     {
12706       (*info->fprintf_func) (info->stream, "(bad)");
12707       return MAX_CODE_LENGTH;
12708     }
12709
12710   obufp = mnemonicendp;
12711   for (i = strlen (obuf) + prefix_length; i < 6; i++)
12712     oappend (" ");
12713   oappend (" ");
12714   (*info->fprintf_func) (info->stream, "%s", obuf);
12715
12716   /* The enter and bound instructions are printed with operands in the same
12717      order as the intel book; everything else is printed in reverse order.  */
12718   if (intel_syntax || two_source_ops)
12719     {
12720       bfd_vma riprel;
12721
12722       for (i = 0; i < MAX_OPERANDS; ++i)
12723         op_txt[i] = op_out[i];
12724
12725       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
12726         {
12727           op_ad = op_index[i];
12728           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
12729           op_index[MAX_OPERANDS - 1 - i] = op_ad;
12730           riprel = op_riprel[i];
12731           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
12732           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
12733         }
12734     }
12735   else
12736     {
12737       for (i = 0; i < MAX_OPERANDS; ++i)
12738         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
12739     }
12740
12741   needcomma = 0;
12742   for (i = 0; i < MAX_OPERANDS; ++i)
12743     if (*op_txt[i])
12744       {
12745         if (needcomma)
12746           (*info->fprintf_func) (info->stream, ",");
12747         if (op_index[i] != -1 && !op_riprel[i])
12748           (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
12749         else
12750           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
12751         needcomma = 1;
12752       }
12753
12754   for (i = 0; i < MAX_OPERANDS; i++)
12755     if (op_index[i] != -1 && op_riprel[i])
12756       {
12757         (*info->fprintf_func) (info->stream, "        # ");
12758         (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep
12759                                                 + op_address[op_index[i]]), info);
12760         break;
12761       }
12762   return codep - priv.the_buffer;
12763 }
12764
12765 static const char *float_mem[] = {
12766   /* d8 */
12767   "fadd{s|}",
12768   "fmul{s|}",
12769   "fcom{s|}",
12770   "fcomp{s|}",
12771   "fsub{s|}",
12772   "fsubr{s|}",
12773   "fdiv{s|}",
12774   "fdivr{s|}",
12775   /* d9 */
12776   "fld{s|}",
12777   "(bad)",
12778   "fst{s|}",
12779   "fstp{s|}",
12780   "fldenvIC",
12781   "fldcw",
12782   "fNstenvIC",
12783   "fNstcw",
12784   /* da */
12785   "fiadd{l|}",
12786   "fimul{l|}",
12787   "ficom{l|}",
12788   "ficomp{l|}",
12789   "fisub{l|}",
12790   "fisubr{l|}",
12791   "fidiv{l|}",
12792   "fidivr{l|}",
12793   /* db */
12794   "fild{l|}",
12795   "fisttp{l|}",
12796   "fist{l|}",
12797   "fistp{l|}",
12798   "(bad)",
12799   "fld{t||t|}",
12800   "(bad)",
12801   "fstp{t||t|}",
12802   /* dc */
12803   "fadd{l|}",
12804   "fmul{l|}",
12805   "fcom{l|}",
12806   "fcomp{l|}",
12807   "fsub{l|}",
12808   "fsubr{l|}",
12809   "fdiv{l|}",
12810   "fdivr{l|}",
12811   /* dd */
12812   "fld{l|}",
12813   "fisttp{ll|}",
12814   "fst{l||}",
12815   "fstp{l|}",
12816   "frstorIC",
12817   "(bad)",
12818   "fNsaveIC",
12819   "fNstsw",
12820   /* de */
12821   "fiadd",
12822   "fimul",
12823   "ficom",
12824   "ficomp",
12825   "fisub",
12826   "fisubr",
12827   "fidiv",
12828   "fidivr",
12829   /* df */
12830   "fild",
12831   "fisttp",
12832   "fist",
12833   "fistp",
12834   "fbld",
12835   "fild{ll|}",
12836   "fbstp",
12837   "fistp{ll|}",
12838 };
12839
12840 static const unsigned char float_mem_mode[] = {
12841   /* d8 */
12842   d_mode,
12843   d_mode,
12844   d_mode,
12845   d_mode,
12846   d_mode,
12847   d_mode,
12848   d_mode,
12849   d_mode,
12850   /* d9 */
12851   d_mode,
12852   0,
12853   d_mode,
12854   d_mode,
12855   0,
12856   w_mode,
12857   0,
12858   w_mode,
12859   /* da */
12860   d_mode,
12861   d_mode,
12862   d_mode,
12863   d_mode,
12864   d_mode,
12865   d_mode,
12866   d_mode,
12867   d_mode,
12868   /* db */
12869   d_mode,
12870   d_mode,
12871   d_mode,
12872   d_mode,
12873   0,
12874   t_mode,
12875   0,
12876   t_mode,
12877   /* dc */
12878   q_mode,
12879   q_mode,
12880   q_mode,
12881   q_mode,
12882   q_mode,
12883   q_mode,
12884   q_mode,
12885   q_mode,
12886   /* dd */
12887   q_mode,
12888   q_mode,
12889   q_mode,
12890   q_mode,
12891   0,
12892   0,
12893   0,
12894   w_mode,
12895   /* de */
12896   w_mode,
12897   w_mode,
12898   w_mode,
12899   w_mode,
12900   w_mode,
12901   w_mode,
12902   w_mode,
12903   w_mode,
12904   /* df */
12905   w_mode,
12906   w_mode,
12907   w_mode,
12908   w_mode,
12909   t_mode,
12910   q_mode,
12911   t_mode,
12912   q_mode
12913 };
12914
12915 #define ST { OP_ST, 0 }
12916 #define STi { OP_STi, 0 }
12917
12918 #define FGRPd9_2 NULL, { { NULL, 0 } }
12919 #define FGRPd9_4 NULL, { { NULL, 1 } }
12920 #define FGRPd9_5 NULL, { { NULL, 2 } }
12921 #define FGRPd9_6 NULL, { { NULL, 3 } }
12922 #define FGRPd9_7 NULL, { { NULL, 4 } }
12923 #define FGRPda_5 NULL, { { NULL, 5 } }
12924 #define FGRPdb_4 NULL, { { NULL, 6 } }
12925 #define FGRPde_3 NULL, { { NULL, 7 } }
12926 #define FGRPdf_4 NULL, { { NULL, 8 } }
12927
12928 static const struct dis386 float_reg[][8] = {
12929   /* d8 */
12930   {
12931     { "fadd",   { ST, STi } },
12932     { "fmul",   { ST, STi } },
12933     { "fcom",   { STi } },
12934     { "fcomp",  { STi } },
12935     { "fsub",   { ST, STi } },
12936     { "fsubr",  { ST, STi } },
12937     { "fdiv",   { ST, STi } },
12938     { "fdivr",  { ST, STi } },
12939   },
12940   /* d9 */
12941   {
12942     { "fld",    { STi } },
12943     { "fxch",   { STi } },
12944     { FGRPd9_2 },
12945     { Bad_Opcode },
12946     { FGRPd9_4 },
12947     { FGRPd9_5 },
12948     { FGRPd9_6 },
12949     { FGRPd9_7 },
12950   },
12951   /* da */
12952   {
12953     { "fcmovb", { ST, STi } },
12954     { "fcmove", { ST, STi } },
12955     { "fcmovbe",{ ST, STi } },
12956     { "fcmovu", { ST, STi } },
12957     { Bad_Opcode },
12958     { FGRPda_5 },
12959     { Bad_Opcode },
12960     { Bad_Opcode },
12961   },
12962   /* db */
12963   {
12964     { "fcmovnb",{ ST, STi } },
12965     { "fcmovne",{ ST, STi } },
12966     { "fcmovnbe",{ ST, STi } },
12967     { "fcmovnu",{ ST, STi } },
12968     { FGRPdb_4 },
12969     { "fucomi", { ST, STi } },
12970     { "fcomi",  { ST, STi } },
12971     { Bad_Opcode },
12972   },
12973   /* dc */
12974   {
12975     { "fadd",   { STi, ST } },
12976     { "fmul",   { STi, ST } },
12977     { Bad_Opcode },
12978     { Bad_Opcode },
12979     { "fsub!M", { STi, ST } },
12980     { "fsubM",  { STi, ST } },
12981     { "fdiv!M", { STi, ST } },
12982     { "fdivM",  { STi, ST } },
12983   },
12984   /* dd */
12985   {
12986     { "ffree",  { STi } },
12987     { Bad_Opcode },
12988     { "fst",    { STi } },
12989     { "fstp",   { STi } },
12990     { "fucom",  { STi } },
12991     { "fucomp", { STi } },
12992     { Bad_Opcode },
12993     { Bad_Opcode },
12994   },
12995   /* de */
12996   {
12997     { "faddp",  { STi, ST } },
12998     { "fmulp",  { STi, ST } },
12999     { Bad_Opcode },
13000     { FGRPde_3 },
13001     { "fsub!Mp", { STi, ST } },
13002     { "fsubMp", { STi, ST } },
13003     { "fdiv!Mp", { STi, ST } },
13004     { "fdivMp", { STi, ST } },
13005   },
13006   /* df */
13007   {
13008     { "ffreep", { STi } },
13009     { Bad_Opcode },
13010     { Bad_Opcode },
13011     { Bad_Opcode },
13012     { FGRPdf_4 },
13013     { "fucomip", { ST, STi } },
13014     { "fcomip", { ST, STi } },
13015     { Bad_Opcode },
13016   },
13017 };
13018
13019 static char *fgrps[][8] = {
13020   /* d9_2  0 */
13021   {
13022     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13023   },
13024
13025   /* d9_4  1 */
13026   {
13027     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
13028   },
13029
13030   /* d9_5  2 */
13031   {
13032     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
13033   },
13034
13035   /* d9_6  3 */
13036   {
13037     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
13038   },
13039
13040   /* d9_7  4 */
13041   {
13042     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
13043   },
13044
13045   /* da_5  5 */
13046   {
13047     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13048   },
13049
13050   /* db_4  6 */
13051   {
13052     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
13053     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
13054   },
13055
13056   /* de_3  7 */
13057   {
13058     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13059   },
13060
13061   /* df_4  8 */
13062   {
13063     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13064   },
13065 };
13066
13067 static void
13068 swap_operand (void)
13069 {
13070   mnemonicendp[0] = '.';
13071   mnemonicendp[1] = 's';
13072   mnemonicendp += 2;
13073 }
13074
13075 static void
13076 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
13077                int sizeflag ATTRIBUTE_UNUSED)
13078 {
13079   /* Skip mod/rm byte.  */
13080   MODRM_CHECK;
13081   codep++;
13082 }
13083
13084 static void
13085 dofloat (int sizeflag)
13086 {
13087   const struct dis386 *dp;
13088   unsigned char floatop;
13089
13090   floatop = codep[-1];
13091
13092   if (modrm.mod != 3)
13093     {
13094       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
13095
13096       putop (float_mem[fp_indx], sizeflag);
13097       obufp = op_out[0];
13098       op_ad = 2;
13099       OP_E (float_mem_mode[fp_indx], sizeflag);
13100       return;
13101     }
13102   /* Skip mod/rm byte.  */
13103   MODRM_CHECK;
13104   codep++;
13105
13106   dp = &float_reg[floatop - 0xd8][modrm.reg];
13107   if (dp->name == NULL)
13108     {
13109       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
13110
13111       /* Instruction fnstsw is only one with strange arg.  */
13112       if (floatop == 0xdf && codep[-1] == 0xe0)
13113         strcpy (op_out[0], names16[0]);
13114     }
13115   else
13116     {
13117       putop (dp->name, sizeflag);
13118
13119       obufp = op_out[0];
13120       op_ad = 2;
13121       if (dp->op[0].rtn)
13122         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
13123
13124       obufp = op_out[1];
13125       op_ad = 1;
13126       if (dp->op[1].rtn)
13127         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
13128     }
13129 }
13130
13131 /* Like oappend (below), but S is a string starting with '%'.
13132    In Intel syntax, the '%' is elided.  */
13133 static void
13134 oappend_maybe_intel (const char *s)
13135 {
13136   oappend (s + intel_syntax);
13137 }
13138
13139 static void
13140 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13141 {
13142   oappend_maybe_intel ("%st");
13143 }
13144
13145 static void
13146 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13147 {
13148   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
13149   oappend_maybe_intel (scratchbuf);
13150 }
13151
13152 /* Capital letters in template are macros.  */
13153 static int
13154 putop (const char *in_template, int sizeflag)
13155 {
13156   const char *p;
13157   int alt = 0;
13158   int cond = 1;
13159   unsigned int l = 0, len = 1;
13160   char last[4];
13161
13162 #define SAVE_LAST(c)                    \
13163   if (l < len && l < sizeof (last))     \
13164     last[l++] = c;                      \
13165   else                                  \
13166     abort ();
13167
13168   for (p = in_template; *p; p++)
13169     {
13170       switch (*p)
13171         {
13172         default:
13173           *obufp++ = *p;
13174           break;
13175         case '%':
13176           len++;
13177           break;
13178         case '!':
13179           cond = 0;
13180           break;
13181         case '{':
13182           alt = 0;
13183           if (intel_syntax)
13184             {
13185               while (*++p != '|')
13186                 if (*p == '}' || *p == '\0')
13187                   abort ();
13188             }
13189           /* Fall through.  */
13190         case 'I':
13191           alt = 1;
13192           continue;
13193         case '|':
13194           while (*++p != '}')
13195             {
13196               if (*p == '\0')
13197                 abort ();
13198             }
13199           break;
13200         case '}':
13201           break;
13202         case 'A':
13203           if (intel_syntax)
13204             break;
13205           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13206             *obufp++ = 'b';
13207           break;
13208         case 'B':
13209           if (l == 0 && len == 1)
13210             {
13211 case_B:
13212               if (intel_syntax)
13213                 break;
13214               if (sizeflag & SUFFIX_ALWAYS)
13215                 *obufp++ = 'b';
13216             }
13217           else
13218             {
13219               if (l != 1
13220                   || len != 2
13221                   || last[0] != 'L')
13222                 {
13223                   SAVE_LAST (*p);
13224                   break;
13225                 }
13226
13227               if (address_mode == mode_64bit
13228                   && !(prefixes & PREFIX_ADDR))
13229                 {
13230                   *obufp++ = 'a';
13231                   *obufp++ = 'b';
13232                   *obufp++ = 's';
13233                 }
13234
13235               goto case_B;
13236             }
13237           break;
13238         case 'C':
13239           if (intel_syntax && !alt)
13240             break;
13241           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
13242             {
13243               if (sizeflag & DFLAG)
13244                 *obufp++ = intel_syntax ? 'd' : 'l';
13245               else
13246                 *obufp++ = intel_syntax ? 'w' : 's';
13247               used_prefixes |= (prefixes & PREFIX_DATA);
13248             }
13249           break;
13250         case 'D':
13251           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
13252             break;
13253           USED_REX (REX_W);
13254           if (modrm.mod == 3)
13255             {
13256               if (rex & REX_W)
13257                 *obufp++ = 'q';
13258               else
13259                 {
13260                   if (sizeflag & DFLAG)
13261                     *obufp++ = intel_syntax ? 'd' : 'l';
13262                   else
13263                     *obufp++ = 'w';
13264                   used_prefixes |= (prefixes & PREFIX_DATA);
13265                 }
13266             }
13267           else
13268             *obufp++ = 'w';
13269           break;
13270         case 'E':               /* For jcxz/jecxz */
13271           if (address_mode == mode_64bit)
13272             {
13273               if (sizeflag & AFLAG)
13274                 *obufp++ = 'r';
13275               else
13276                 *obufp++ = 'e';
13277             }
13278           else
13279             if (sizeflag & AFLAG)
13280               *obufp++ = 'e';
13281           used_prefixes |= (prefixes & PREFIX_ADDR);
13282           break;
13283         case 'F':
13284           if (intel_syntax)
13285             break;
13286           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
13287             {
13288               if (sizeflag & AFLAG)
13289                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
13290               else
13291                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
13292               used_prefixes |= (prefixes & PREFIX_ADDR);
13293             }
13294           break;
13295         case 'G':
13296           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
13297             break;
13298           if ((rex & REX_W) || (sizeflag & DFLAG))
13299             *obufp++ = 'l';
13300           else
13301             *obufp++ = 'w';
13302           if (!(rex & REX_W))
13303             used_prefixes |= (prefixes & PREFIX_DATA);
13304           break;
13305         case 'H':
13306           if (intel_syntax)
13307             break;
13308           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
13309               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
13310             {
13311               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
13312               *obufp++ = ',';
13313               *obufp++ = 'p';
13314               if (prefixes & PREFIX_DS)
13315                 *obufp++ = 't';
13316               else
13317                 *obufp++ = 'n';
13318             }
13319           break;
13320         case 'J':
13321           if (intel_syntax)
13322             break;
13323           *obufp++ = 'l';
13324           break;
13325         case 'K':
13326           USED_REX (REX_W);
13327           if (rex & REX_W)
13328             *obufp++ = 'q';
13329           else
13330             *obufp++ = 'd';
13331           break;
13332         case 'Z':
13333           if (intel_syntax)
13334             break;
13335           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
13336             {
13337               *obufp++ = 'q';
13338               break;
13339             }
13340           /* Fall through.  */
13341           goto case_L;
13342         case 'L':
13343           if (l != 0 || len != 1)
13344             {
13345               SAVE_LAST (*p);
13346               break;
13347             }
13348 case_L:
13349           if (intel_syntax)
13350             break;
13351           if (sizeflag & SUFFIX_ALWAYS)
13352             *obufp++ = 'l';
13353           break;
13354         case 'M':
13355           if (intel_mnemonic != cond)
13356             *obufp++ = 'r';
13357           break;
13358         case 'N':
13359           if ((prefixes & PREFIX_FWAIT) == 0)
13360             *obufp++ = 'n';
13361           else
13362             used_prefixes |= PREFIX_FWAIT;
13363           break;
13364         case 'O':
13365           USED_REX (REX_W);
13366           if (rex & REX_W)
13367             *obufp++ = 'o';
13368           else if (intel_syntax && (sizeflag & DFLAG))
13369             *obufp++ = 'q';
13370           else
13371             *obufp++ = 'd';
13372           if (!(rex & REX_W))
13373             used_prefixes |= (prefixes & PREFIX_DATA);
13374           break;
13375         case 'T':
13376           if (!intel_syntax
13377               && address_mode == mode_64bit
13378               && ((sizeflag & DFLAG) || (rex & REX_W)))
13379             {
13380               *obufp++ = 'q';
13381               break;
13382             }
13383           /* Fall through.  */
13384         case 'P':
13385           if (intel_syntax)
13386             {
13387               if ((rex & REX_W) == 0
13388                   && (prefixes & PREFIX_DATA))
13389                 {
13390                   if ((sizeflag & DFLAG) == 0)
13391                     *obufp++ = 'w';
13392                    used_prefixes |= (prefixes & PREFIX_DATA);
13393                 }
13394               break;
13395             }
13396           if ((prefixes & PREFIX_DATA)
13397               || (rex & REX_W)
13398               || (sizeflag & SUFFIX_ALWAYS))
13399             {
13400               USED_REX (REX_W);
13401               if (rex & REX_W)
13402                 *obufp++ = 'q';
13403               else
13404                 {
13405                    if (sizeflag & DFLAG)
13406                       *obufp++ = 'l';
13407                    else
13408                      *obufp++ = 'w';
13409                    used_prefixes |= (prefixes & PREFIX_DATA);
13410                 }
13411             }
13412           break;
13413         case 'U':
13414           if (intel_syntax)
13415             break;
13416           if (address_mode == mode_64bit
13417               && ((sizeflag & DFLAG) || (rex & REX_W)))
13418             {
13419               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13420                 *obufp++ = 'q';
13421               break;
13422             }
13423           /* Fall through.  */
13424           goto case_Q;
13425         case 'Q':
13426           if (l == 0 && len == 1)
13427             {
13428 case_Q:
13429               if (intel_syntax && !alt)
13430                 break;
13431               USED_REX (REX_W);
13432               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13433                 {
13434                   if (rex & REX_W)
13435                     *obufp++ = 'q';
13436                   else
13437                     {
13438                       if (sizeflag & DFLAG)
13439                         *obufp++ = intel_syntax ? 'd' : 'l';
13440                       else
13441                         *obufp++ = 'w';
13442                       used_prefixes |= (prefixes & PREFIX_DATA);
13443                     }
13444                 }
13445             }
13446           else
13447             {
13448               if (l != 1 || len != 2 || last[0] != 'L')
13449                 {
13450                   SAVE_LAST (*p);
13451                   break;
13452                 }
13453               if (intel_syntax
13454                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
13455                 break;
13456               if ((rex & REX_W))
13457                 {
13458                   USED_REX (REX_W);
13459                   *obufp++ = 'q';
13460                 }
13461               else
13462                 *obufp++ = 'l';
13463             }
13464           break;
13465         case 'R':
13466           USED_REX (REX_W);
13467           if (rex & REX_W)
13468             *obufp++ = 'q';
13469           else if (sizeflag & DFLAG)
13470             {
13471               if (intel_syntax)
13472                   *obufp++ = 'd';
13473               else
13474                   *obufp++ = 'l';
13475             }
13476           else
13477             *obufp++ = 'w';
13478           if (intel_syntax && !p[1]
13479               && ((rex & REX_W) || (sizeflag & DFLAG)))
13480             *obufp++ = 'e';
13481           if (!(rex & REX_W))
13482             used_prefixes |= (prefixes & PREFIX_DATA);
13483           break;
13484         case 'V':
13485           if (l == 0 && len == 1)
13486             {
13487               if (intel_syntax)
13488                 break;
13489               if (address_mode == mode_64bit
13490                   && ((sizeflag & DFLAG) || (rex & REX_W)))
13491                 {
13492                   if (sizeflag & SUFFIX_ALWAYS)
13493                     *obufp++ = 'q';
13494                   break;
13495                 }
13496             }
13497           else
13498             {
13499               if (l != 1
13500                   || len != 2
13501                   || last[0] != 'L')
13502                 {
13503                   SAVE_LAST (*p);
13504                   break;
13505                 }
13506
13507               if (rex & REX_W)
13508                 {
13509                   *obufp++ = 'a';
13510                   *obufp++ = 'b';
13511                   *obufp++ = 's';
13512                 }
13513             }
13514           /* Fall through.  */
13515           goto case_S;
13516         case 'S':
13517           if (l == 0 && len == 1)
13518             {
13519 case_S:
13520               if (intel_syntax)
13521                 break;
13522               if (sizeflag & SUFFIX_ALWAYS)
13523                 {
13524                   if (rex & REX_W)
13525                     *obufp++ = 'q';
13526                   else
13527                     {
13528                       if (sizeflag & DFLAG)
13529                         *obufp++ = 'l';
13530                       else
13531                         *obufp++ = 'w';
13532                       used_prefixes |= (prefixes & PREFIX_DATA);
13533                     }
13534                 }
13535             }
13536           else
13537             {
13538               if (l != 1
13539                   || len != 2
13540                   || last[0] != 'L')
13541                 {
13542                   SAVE_LAST (*p);
13543                   break;
13544                 }
13545
13546               if (address_mode == mode_64bit
13547                   && !(prefixes & PREFIX_ADDR))
13548                 {
13549                   *obufp++ = 'a';
13550                   *obufp++ = 'b';
13551                   *obufp++ = 's';
13552                 }
13553
13554               goto case_S;
13555             }
13556           break;
13557         case 'X':
13558           if (l != 0 || len != 1)
13559             {
13560               SAVE_LAST (*p);
13561               break;
13562             }
13563           if (need_vex && vex.prefix)
13564             {
13565               if (vex.prefix == DATA_PREFIX_OPCODE)
13566                 *obufp++ = 'd';
13567               else
13568                 *obufp++ = 's';
13569             }
13570           else
13571             {
13572               if (prefixes & PREFIX_DATA)
13573                 *obufp++ = 'd';
13574               else
13575                 *obufp++ = 's';
13576               used_prefixes |= (prefixes & PREFIX_DATA);
13577             }
13578           break;
13579         case 'Y':
13580           if (l == 0 && len == 1)
13581             {
13582               if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
13583                 break;
13584               if (rex & REX_W)
13585                 {
13586                   USED_REX (REX_W);
13587                   *obufp++ = 'q';
13588                 }
13589               break;
13590             }
13591           else
13592             {
13593               if (l != 1 || len != 2 || last[0] != 'X')
13594                 {
13595                   SAVE_LAST (*p);
13596                   break;
13597                 }
13598               if (!need_vex)
13599                 abort ();
13600               if (intel_syntax
13601                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
13602                 break;
13603               switch (vex.length)
13604                 {
13605                 case 128:
13606                   *obufp++ = 'x';
13607                   break;
13608                 case 256:
13609                   *obufp++ = 'y';
13610                   break;
13611                 default:
13612                   abort ();
13613                 }
13614             }
13615           break;
13616         case 'W':
13617           if (l == 0 && len == 1)
13618             {
13619               /* operand size flag for cwtl, cbtw */
13620               USED_REX (REX_W);
13621               if (rex & REX_W)
13622                 {
13623                   if (intel_syntax)
13624                     *obufp++ = 'd';
13625                   else
13626                     *obufp++ = 'l';
13627                 }
13628               else if (sizeflag & DFLAG)
13629                 *obufp++ = 'w';
13630               else
13631                 *obufp++ = 'b';
13632               if (!(rex & REX_W))
13633                 used_prefixes |= (prefixes & PREFIX_DATA);
13634             }
13635           else
13636             {
13637               if (l != 1
13638                   || len != 2
13639                   || (last[0] != 'X'
13640                       && last[0] != 'L'))
13641                 {
13642                   SAVE_LAST (*p);
13643                   break;
13644                 }
13645               if (!need_vex)
13646                 abort ();
13647               if (last[0] == 'X')
13648                 *obufp++ = vex.w ? 'd': 's';
13649               else
13650                 *obufp++ = vex.w ? 'q': 'd';
13651             }
13652           break;
13653         }
13654       alt = 0;
13655     }
13656   *obufp = 0;
13657   mnemonicendp = obufp;
13658   return 0;
13659 }
13660
13661 static void
13662 oappend (const char *s)
13663 {
13664   obufp = stpcpy (obufp, s);
13665 }
13666
13667 static void
13668 append_seg (void)
13669 {
13670   if (prefixes & PREFIX_CS)
13671     {
13672       used_prefixes |= PREFIX_CS;
13673       oappend_maybe_intel ("%cs:");
13674     }
13675   if (prefixes & PREFIX_DS)
13676     {
13677       used_prefixes |= PREFIX_DS;
13678       oappend_maybe_intel ("%ds:");
13679     }
13680   if (prefixes & PREFIX_SS)
13681     {
13682       used_prefixes |= PREFIX_SS;
13683       oappend_maybe_intel ("%ss:");
13684     }
13685   if (prefixes & PREFIX_ES)
13686     {
13687       used_prefixes |= PREFIX_ES;
13688       oappend_maybe_intel ("%es:");
13689     }
13690   if (prefixes & PREFIX_FS)
13691     {
13692       used_prefixes |= PREFIX_FS;
13693       oappend_maybe_intel ("%fs:");
13694     }
13695   if (prefixes & PREFIX_GS)
13696     {
13697       used_prefixes |= PREFIX_GS;
13698       oappend_maybe_intel ("%gs:");
13699     }
13700 }
13701
13702 static void
13703 OP_indirE (int bytemode, int sizeflag)
13704 {
13705   if (!intel_syntax)
13706     oappend ("*");
13707   OP_E (bytemode, sizeflag);
13708 }
13709
13710 static void
13711 print_operand_value (char *buf, int hex, bfd_vma disp)
13712 {
13713   if (address_mode == mode_64bit)
13714     {
13715       if (hex)
13716         {
13717           char tmp[30];
13718           int i;
13719           buf[0] = '0';
13720           buf[1] = 'x';
13721           sprintf_vma (tmp, disp);
13722           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
13723           strcpy (buf + 2, tmp + i);
13724         }
13725       else
13726         {
13727           bfd_signed_vma v = disp;
13728           char tmp[30];
13729           int i;
13730           if (v < 0)
13731             {
13732               *(buf++) = '-';
13733               v = -disp;
13734               /* Check for possible overflow on 0x8000000000000000.  */
13735               if (v < 0)
13736                 {
13737                   strcpy (buf, "9223372036854775808");
13738                   return;
13739                 }
13740             }
13741           if (!v)
13742             {
13743               strcpy (buf, "0");
13744               return;
13745             }
13746
13747           i = 0;
13748           tmp[29] = 0;
13749           while (v)
13750             {
13751               tmp[28 - i] = (v % 10) + '0';
13752               v /= 10;
13753               i++;
13754             }
13755           strcpy (buf, tmp + 29 - i);
13756         }
13757     }
13758   else
13759     {
13760       if (hex)
13761         sprintf (buf, "0x%x", (unsigned int) disp);
13762       else
13763         sprintf (buf, "%d", (int) disp);
13764     }
13765 }
13766
13767 /* Put DISP in BUF as signed hex number.  */
13768
13769 static void
13770 print_displacement (char *buf, bfd_vma disp)
13771 {
13772   bfd_signed_vma val = disp;
13773   char tmp[30];
13774   int i, j = 0;
13775
13776   if (val < 0)
13777     {
13778       buf[j++] = '-';
13779       val = -disp;
13780
13781       /* Check for possible overflow.  */
13782       if (val < 0)
13783         {
13784           switch (address_mode)
13785             {
13786             case mode_64bit:
13787               strcpy (buf + j, "0x8000000000000000");
13788               break;
13789             case mode_32bit:
13790               strcpy (buf + j, "0x80000000");
13791               break;
13792             case mode_16bit:
13793               strcpy (buf + j, "0x8000");
13794               break;
13795             }
13796           return;
13797         }
13798     }
13799
13800   buf[j++] = '0';
13801   buf[j++] = 'x';
13802
13803   sprintf_vma (tmp, (bfd_vma) val);
13804   for (i = 0; tmp[i] == '0'; i++)
13805     continue;
13806   if (tmp[i] == '\0')
13807     i--;
13808   strcpy (buf + j, tmp + i);
13809 }
13810
13811 static void
13812 intel_operand_size (int bytemode, int sizeflag)
13813 {
13814   if (vex.evex
13815       && vex.b
13816       && (bytemode == x_mode
13817           || bytemode == evex_half_bcst_xmmq_mode))
13818     {
13819       if (vex.w)
13820         oappend ("QWORD PTR ");
13821       else
13822         oappend ("DWORD PTR ");
13823       return;
13824     }
13825   switch (bytemode)
13826     {
13827     case b_mode:
13828     case b_swap_mode:
13829     case dqb_mode:
13830       oappend ("BYTE PTR ");
13831       break;
13832     case w_mode:
13833     case dqw_mode:
13834       oappend ("WORD PTR ");
13835       break;
13836     case stack_v_mode:
13837       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
13838         {
13839           oappend ("QWORD PTR ");
13840           break;
13841         }
13842       /* FALLTHRU */
13843     case v_mode:
13844     case v_swap_mode:
13845     case dq_mode:
13846       USED_REX (REX_W);
13847       if (rex & REX_W)
13848         oappend ("QWORD PTR ");
13849       else
13850         {
13851           if ((sizeflag & DFLAG) || bytemode == dq_mode)
13852             oappend ("DWORD PTR ");
13853           else
13854             oappend ("WORD PTR ");
13855           used_prefixes |= (prefixes & PREFIX_DATA);
13856         }
13857       break;
13858     case z_mode:
13859       if ((rex & REX_W) || (sizeflag & DFLAG))
13860         *obufp++ = 'D';
13861       oappend ("WORD PTR ");
13862       if (!(rex & REX_W))
13863         used_prefixes |= (prefixes & PREFIX_DATA);
13864       break;
13865     case a_mode:
13866       if (sizeflag & DFLAG)
13867         oappend ("QWORD PTR ");
13868       else
13869         oappend ("DWORD PTR ");
13870       used_prefixes |= (prefixes & PREFIX_DATA);
13871       break;
13872     case d_mode:
13873     case d_scalar_mode:
13874     case d_scalar_swap_mode:
13875     case d_swap_mode:
13876     case dqd_mode:
13877       oappend ("DWORD PTR ");
13878       break;
13879     case q_mode:
13880     case q_scalar_mode:
13881     case q_scalar_swap_mode:
13882     case q_swap_mode:
13883       oappend ("QWORD PTR ");
13884       break;
13885     case m_mode:
13886       if (address_mode == mode_64bit)
13887         oappend ("QWORD PTR ");
13888       else
13889         oappend ("DWORD PTR ");
13890       break;
13891     case f_mode:
13892       if (sizeflag & DFLAG)
13893         oappend ("FWORD PTR ");
13894       else
13895         oappend ("DWORD PTR ");
13896       used_prefixes |= (prefixes & PREFIX_DATA);
13897       break;
13898     case t_mode:
13899       oappend ("TBYTE PTR ");
13900       break;
13901     case x_mode:
13902     case x_swap_mode:
13903     case evex_x_gscat_mode:
13904     case evex_x_nobcst_mode:
13905       if (need_vex)
13906         {
13907           switch (vex.length)
13908             {
13909             case 128:
13910               oappend ("XMMWORD PTR ");
13911               break;
13912             case 256:
13913               oappend ("YMMWORD PTR ");
13914               break;
13915             case 512:
13916               oappend ("ZMMWORD PTR ");
13917               break;
13918             default:
13919               abort ();
13920             }
13921         }
13922       else
13923         oappend ("XMMWORD PTR ");
13924       break;
13925     case xmm_mode:
13926       oappend ("XMMWORD PTR ");
13927       break;
13928     case ymm_mode:
13929       oappend ("YMMWORD PTR ");
13930       break;
13931     case xmmq_mode:
13932     case evex_half_bcst_xmmq_mode:
13933       if (!need_vex)
13934         abort ();
13935
13936       switch (vex.length)
13937         {
13938         case 128:
13939           oappend ("QWORD PTR ");
13940           break;
13941         case 256:
13942           oappend ("XMMWORD PTR ");
13943           break;
13944         case 512:
13945           oappend ("YMMWORD PTR ");
13946           break;
13947         default:
13948           abort ();
13949         }
13950       break;
13951     case xmm_mb_mode:
13952       if (!need_vex)
13953         abort ();
13954
13955       switch (vex.length)
13956         {
13957         case 128:
13958         case 256:
13959         case 512:
13960           oappend ("BYTE PTR ");
13961           break;
13962         default:
13963           abort ();
13964         }
13965       break;
13966     case xmm_mw_mode:
13967       if (!need_vex)
13968         abort ();
13969
13970       switch (vex.length)
13971         {
13972         case 128:
13973         case 256:
13974         case 512:
13975           oappend ("WORD PTR ");
13976           break;
13977         default:
13978           abort ();
13979         }
13980       break;
13981     case xmm_md_mode:
13982       if (!need_vex)
13983         abort ();
13984
13985       switch (vex.length)
13986         {
13987         case 128:
13988         case 256:
13989         case 512:
13990           oappend ("DWORD PTR ");
13991           break;
13992         default:
13993           abort ();
13994         }
13995       break;
13996     case xmm_mq_mode:
13997       if (!need_vex)
13998         abort ();
13999
14000       switch (vex.length)
14001         {
14002         case 128:
14003         case 256:
14004         case 512:
14005           oappend ("QWORD PTR ");
14006           break;
14007         default:
14008           abort ();
14009         }
14010       break;
14011     case xmmdw_mode:
14012       if (!need_vex)
14013         abort ();
14014
14015       switch (vex.length)
14016         {
14017         case 128:
14018           oappend ("WORD PTR ");
14019           break;
14020         case 256:
14021           oappend ("DWORD PTR ");
14022           break;
14023         case 512:
14024           oappend ("QWORD PTR ");
14025           break;
14026         default:
14027           abort ();
14028         }
14029       break;
14030     case xmmqd_mode:
14031       if (!need_vex)
14032         abort ();
14033
14034       switch (vex.length)
14035         {
14036         case 128:
14037           oappend ("DWORD PTR ");
14038           break;
14039         case 256:
14040           oappend ("QWORD PTR ");
14041           break;
14042         case 512:
14043           oappend ("XMMWORD PTR ");
14044           break;
14045         default:
14046           abort ();
14047         }
14048       break;
14049     case ymmq_mode:
14050       if (!need_vex)
14051         abort ();
14052
14053       switch (vex.length)
14054         {
14055         case 128:
14056           oappend ("QWORD PTR ");
14057           break;
14058         case 256:
14059           oappend ("YMMWORD PTR ");
14060           break;
14061         case 512:
14062           oappend ("ZMMWORD PTR ");
14063           break;
14064         default:
14065           abort ();
14066         }
14067       break;
14068     case ymmxmm_mode:
14069       if (!need_vex)
14070         abort ();
14071
14072       switch (vex.length)
14073         {
14074         case 128:
14075         case 256:
14076           oappend ("XMMWORD PTR ");
14077           break;
14078         default:
14079           abort ();
14080         }
14081       break;
14082     case o_mode:
14083       oappend ("OWORD PTR ");
14084       break;
14085     case xmm_mdq_mode:
14086     case vex_w_dq_mode:
14087     case vex_scalar_w_dq_mode:
14088       if (!need_vex)
14089         abort ();
14090
14091       if (vex.w)
14092         oappend ("QWORD PTR ");
14093       else
14094         oappend ("DWORD PTR ");
14095       break;
14096     case vex_vsib_d_w_dq_mode:
14097     case vex_vsib_q_w_dq_mode:
14098       if (!need_vex)
14099         abort ();
14100
14101       if (!vex.evex)
14102         {
14103           if (vex.w)
14104             oappend ("QWORD PTR ");
14105           else
14106             oappend ("DWORD PTR ");
14107         }
14108       else
14109         {
14110           if (vex.length != 512)
14111             abort ();
14112           oappend ("ZMMWORD PTR ");
14113         }
14114       break;
14115     case mask_mode:
14116       if (!need_vex)
14117         abort ();
14118       /* Currently the only instructions, which allows either mask or
14119          memory operand, are AVX512's KMOVW instructions.  They need
14120          Word-sized operand.  */
14121       if (vex.w || vex.length != 128)
14122         abort ();
14123       oappend ("WORD PTR ");
14124       break;
14125     case v_bnd_mode:
14126     default:
14127       break;
14128     }
14129 }
14130
14131 static void
14132 OP_E_register (int bytemode, int sizeflag)
14133 {
14134   int reg = modrm.rm;
14135   const char **names;
14136
14137   USED_REX (REX_B);
14138   if ((rex & REX_B))
14139     reg += 8;
14140
14141   if ((sizeflag & SUFFIX_ALWAYS)
14142       && (bytemode == b_swap_mode || bytemode == v_swap_mode))
14143     swap_operand ();
14144
14145   switch (bytemode)
14146     {
14147     case b_mode:
14148     case b_swap_mode:
14149       USED_REX (0);
14150       if (rex)
14151         names = names8rex;
14152       else
14153         names = names8;
14154       break;
14155     case w_mode:
14156       names = names16;
14157       break;
14158     case d_mode:
14159       names = names32;
14160       break;
14161     case q_mode:
14162       names = names64;
14163       break;
14164     case m_mode:
14165     case v_bnd_mode:
14166       names = address_mode == mode_64bit ? names64 : names32;
14167       break;
14168     case bnd_mode:
14169       names = names_bnd;
14170       break;
14171     case stack_v_mode:
14172       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14173         {
14174           names = names64;
14175           break;
14176         }
14177       bytemode = v_mode;
14178       /* FALLTHRU */
14179     case v_mode:
14180     case v_swap_mode:
14181     case dq_mode:
14182     case dqb_mode:
14183     case dqd_mode:
14184     case dqw_mode:
14185       USED_REX (REX_W);
14186       if (rex & REX_W)
14187         names = names64;
14188       else
14189         {
14190           if ((sizeflag & DFLAG)
14191               || (bytemode != v_mode
14192                   && bytemode != v_swap_mode))
14193             names = names32;
14194           else
14195             names = names16;
14196           used_prefixes |= (prefixes & PREFIX_DATA);
14197         }
14198       break;
14199     case mask_mode:
14200       names = names_mask;
14201       break;
14202     case 0:
14203       return;
14204     default:
14205       oappend (INTERNAL_DISASSEMBLER_ERROR);
14206       return;
14207     }
14208   oappend (names[reg]);
14209 }
14210
14211 static void
14212 OP_E_memory (int bytemode, int sizeflag)
14213 {
14214   bfd_vma disp = 0;
14215   int add = (rex & REX_B) ? 8 : 0;
14216   int riprel = 0;
14217   int shift;
14218
14219   if (vex.evex)
14220     {
14221       /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0.  */
14222       if (vex.b
14223           && bytemode != x_mode
14224           && bytemode != evex_half_bcst_xmmq_mode)
14225         {
14226           BadOp ();
14227           return;
14228         }
14229       switch (bytemode)
14230         {
14231         case vex_vsib_d_w_dq_mode:
14232         case vex_vsib_q_w_dq_mode:
14233         case evex_x_gscat_mode:
14234         case xmm_mdq_mode:
14235           shift = vex.w ? 3 : 2;
14236           break;
14237         case x_mode:
14238         case evex_half_bcst_xmmq_mode:
14239           if (vex.b)
14240             {
14241               shift = vex.w ? 3 : 2;
14242               break;
14243             }
14244           /* Fall through if vex.b == 0.  */
14245         case xmmqd_mode:
14246         case xmmdw_mode:
14247         case xmmq_mode:
14248         case ymmq_mode:
14249         case evex_x_nobcst_mode:
14250         case x_swap_mode:
14251           switch (vex.length)
14252             {
14253             case 128:
14254               shift = 4;
14255               break;
14256             case 256:
14257               shift = 5;
14258               break;
14259             case 512:
14260               shift = 6;
14261               break;
14262             default:
14263               abort ();
14264             }
14265           break;
14266         case ymm_mode:
14267           shift = 5;
14268           break;
14269         case xmm_mode:
14270           shift = 4;
14271           break;
14272         case xmm_mq_mode:
14273         case q_mode:
14274         case q_scalar_mode:
14275         case q_swap_mode:
14276         case q_scalar_swap_mode:
14277           shift = 3;
14278           break;
14279         case dqd_mode:
14280         case xmm_md_mode:
14281         case d_mode:
14282         case d_scalar_mode:
14283         case d_swap_mode:
14284         case d_scalar_swap_mode:
14285           shift = 2;
14286           break;
14287         case xmm_mw_mode:
14288           shift = 1;
14289           break;
14290         case xmm_mb_mode:
14291           shift = 0;
14292           break;
14293         default:
14294           abort ();
14295         }
14296       /* Make necessary corrections to shift for modes that need it.
14297          For these modes we currently have shift 4, 5 or 6 depending on
14298          vex.length (it corresponds to xmmword, ymmword or zmmword
14299          operand).  We might want to make it 3, 4 or 5 (e.g. for
14300          xmmq_mode).  In case of broadcast enabled the corrections
14301          aren't needed, as element size is always 32 or 64 bits.  */
14302       if (bytemode == xmmq_mode
14303           || (bytemode == evex_half_bcst_xmmq_mode
14304               && !vex.b))
14305         shift -= 1;
14306       else if (bytemode == xmmqd_mode)
14307         shift -= 2;
14308       else if (bytemode == xmmdw_mode)
14309         shift -= 3;
14310     }
14311   else
14312     shift = 0;
14313
14314   USED_REX (REX_B);
14315   if (intel_syntax)
14316     intel_operand_size (bytemode, sizeflag);
14317   append_seg ();
14318
14319   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14320     {
14321       /* 32/64 bit address mode */
14322       int havedisp;
14323       int havesib;
14324       int havebase;
14325       int haveindex;
14326       int needindex;
14327       int base, rbase;
14328       int vindex = 0;
14329       int scale = 0;
14330       int addr32flag = !((sizeflag & AFLAG)
14331                          || bytemode == v_bnd_mode
14332                          || bytemode == bnd_mode);
14333       const char **indexes64 = names64;
14334       const char **indexes32 = names32;
14335
14336       havesib = 0;
14337       havebase = 1;
14338       haveindex = 0;
14339       base = modrm.rm;
14340
14341       if (base == 4)
14342         {
14343           havesib = 1;
14344           vindex = sib.index;
14345           USED_REX (REX_X);
14346           if (rex & REX_X)
14347             vindex += 8;
14348           switch (bytemode)
14349             {
14350             case vex_vsib_d_w_dq_mode:
14351             case vex_vsib_q_w_dq_mode:
14352               if (!need_vex)
14353                 abort ();
14354               if (vex.evex)
14355                 {
14356                   if (!vex.v)
14357                     vindex += 16;
14358                 }
14359
14360               haveindex = 1;
14361               switch (vex.length)
14362                 {
14363                 case 128:
14364                   indexes64 = indexes32 = names_xmm;
14365                   break;
14366                 case 256:
14367                   if (!vex.w || bytemode == vex_vsib_q_w_dq_mode)
14368                     indexes64 = indexes32 = names_ymm;
14369                   else
14370                     indexes64 = indexes32 = names_xmm;
14371                   break;
14372                 case 512:
14373                   if (!vex.w || bytemode == vex_vsib_q_w_dq_mode)
14374                     indexes64 = indexes32 = names_zmm;
14375                   else
14376                     indexes64 = indexes32 = names_ymm;
14377                   break;
14378                 default:
14379                   abort ();
14380                 }
14381               break;
14382             default:
14383               haveindex = vindex != 4;
14384               break;
14385             }
14386           scale = sib.scale;
14387           base = sib.base;
14388           codep++;
14389         }
14390       rbase = base + add;
14391
14392       switch (modrm.mod)
14393         {
14394         case 0:
14395           if (base == 5)
14396             {
14397               havebase = 0;
14398               if (address_mode == mode_64bit && !havesib)
14399                 riprel = 1;
14400               disp = get32s ();
14401             }
14402           break;
14403         case 1:
14404           FETCH_DATA (the_info, codep + 1);
14405           disp = *codep++;
14406           if ((disp & 0x80) != 0)
14407             disp -= 0x100;
14408           if (vex.evex && shift > 0)
14409             disp <<= shift;
14410           break;
14411         case 2:
14412           disp = get32s ();
14413           break;
14414         }
14415
14416       /* In 32bit mode, we need index register to tell [offset] from
14417          [eiz*1 + offset].  */
14418       needindex = (havesib
14419                    && !havebase
14420                    && !haveindex
14421                    && address_mode == mode_32bit);
14422       havedisp = (havebase
14423                   || needindex
14424                   || (havesib && (haveindex || scale != 0)));
14425
14426       if (!intel_syntax)
14427         if (modrm.mod != 0 || base == 5)
14428           {
14429             if (havedisp || riprel)
14430               print_displacement (scratchbuf, disp);
14431             else
14432               print_operand_value (scratchbuf, 1, disp);
14433             oappend (scratchbuf);
14434             if (riprel)
14435               {
14436                 set_op (disp, 1);
14437                 oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)");
14438               }
14439           }
14440
14441       if ((havebase || haveindex || riprel)
14442           && (bytemode != v_bnd_mode)
14443           && (bytemode != bnd_mode))
14444         used_prefixes |= PREFIX_ADDR;
14445
14446       if (havedisp || (intel_syntax && riprel))
14447         {
14448           *obufp++ = open_char;
14449           if (intel_syntax && riprel)
14450             {
14451               set_op (disp, 1);
14452               oappend (sizeflag & AFLAG ? "rip" : "eip");
14453             }
14454           *obufp = '\0';
14455           if (havebase)
14456             oappend (address_mode == mode_64bit && !addr32flag
14457                      ? names64[rbase] : names32[rbase]);
14458           if (havesib)
14459             {
14460               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
14461                  print index to tell base + index from base.  */
14462               if (scale != 0
14463                   || needindex
14464                   || haveindex
14465                   || (havebase && base != ESP_REG_NUM))
14466                 {
14467                   if (!intel_syntax || havebase)
14468                     {
14469                       *obufp++ = separator_char;
14470                       *obufp = '\0';
14471                     }
14472                   if (haveindex)
14473                     oappend (address_mode == mode_64bit && !addr32flag
14474                              ? indexes64[vindex] : indexes32[vindex]);
14475                   else
14476                     oappend (address_mode == mode_64bit && !addr32flag
14477                              ? index64 : index32);
14478
14479                   *obufp++ = scale_char;
14480                   *obufp = '\0';
14481                   sprintf (scratchbuf, "%d", 1 << scale);
14482                   oappend (scratchbuf);
14483                 }
14484             }
14485           if (intel_syntax
14486               && (disp || modrm.mod != 0 || base == 5))
14487             {
14488               if (!havedisp || (bfd_signed_vma) disp >= 0)
14489                 {
14490                   *obufp++ = '+';
14491                   *obufp = '\0';
14492                 }
14493               else if (modrm.mod != 1 && disp != -disp)
14494                 {
14495                   *obufp++ = '-';
14496                   *obufp = '\0';
14497                   disp = - (bfd_signed_vma) disp;
14498                 }
14499
14500               if (havedisp)
14501                 print_displacement (scratchbuf, disp);
14502               else
14503                 print_operand_value (scratchbuf, 1, disp);
14504               oappend (scratchbuf);
14505             }
14506
14507           *obufp++ = close_char;
14508           *obufp = '\0';
14509         }
14510       else if (intel_syntax)
14511         {
14512           if (modrm.mod != 0 || base == 5)
14513             {
14514               if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
14515                               | PREFIX_ES | PREFIX_FS | PREFIX_GS))
14516                 ;
14517               else
14518                 {
14519                   oappend (names_seg[ds_reg - es_reg]);
14520                   oappend (":");
14521                 }
14522               print_operand_value (scratchbuf, 1, disp);
14523               oappend (scratchbuf);
14524             }
14525         }
14526     }
14527   else
14528     {
14529       /* 16 bit address mode */
14530       used_prefixes |= prefixes & PREFIX_ADDR;
14531       switch (modrm.mod)
14532         {
14533         case 0:
14534           if (modrm.rm == 6)
14535             {
14536               disp = get16 ();
14537               if ((disp & 0x8000) != 0)
14538                 disp -= 0x10000;
14539             }
14540           break;
14541         case 1:
14542           FETCH_DATA (the_info, codep + 1);
14543           disp = *codep++;
14544           if ((disp & 0x80) != 0)
14545             disp -= 0x100;
14546           break;
14547         case 2:
14548           disp = get16 ();
14549           if ((disp & 0x8000) != 0)
14550             disp -= 0x10000;
14551           break;
14552         }
14553
14554       if (!intel_syntax)
14555         if (modrm.mod != 0 || modrm.rm == 6)
14556           {
14557             print_displacement (scratchbuf, disp);
14558             oappend (scratchbuf);
14559           }
14560
14561       if (modrm.mod != 0 || modrm.rm != 6)
14562         {
14563           *obufp++ = open_char;
14564           *obufp = '\0';
14565           oappend (index16[modrm.rm]);
14566           if (intel_syntax
14567               && (disp || modrm.mod != 0 || modrm.rm == 6))
14568             {
14569               if ((bfd_signed_vma) disp >= 0)
14570                 {
14571                   *obufp++ = '+';
14572                   *obufp = '\0';
14573                 }
14574               else if (modrm.mod != 1)
14575                 {
14576                   *obufp++ = '-';
14577                   *obufp = '\0';
14578                   disp = - (bfd_signed_vma) disp;
14579                 }
14580
14581               print_displacement (scratchbuf, disp);
14582               oappend (scratchbuf);
14583             }
14584
14585           *obufp++ = close_char;
14586           *obufp = '\0';
14587         }
14588       else if (intel_syntax)
14589         {
14590           if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
14591                           | PREFIX_ES | PREFIX_FS | PREFIX_GS))
14592             ;
14593           else
14594             {
14595               oappend (names_seg[ds_reg - es_reg]);
14596               oappend (":");
14597             }
14598           print_operand_value (scratchbuf, 1, disp & 0xffff);
14599           oappend (scratchbuf);
14600         }
14601     }
14602   if (vex.evex && vex.b
14603       && (bytemode == x_mode
14604           || bytemode == evex_half_bcst_xmmq_mode))
14605     {
14606       if (vex.w || bytemode == evex_half_bcst_xmmq_mode)
14607         oappend ("{1to8}");
14608       else
14609         oappend ("{1to16}");
14610     }
14611 }
14612
14613 static void
14614 OP_E (int bytemode, int sizeflag)
14615 {
14616   /* Skip mod/rm byte.  */
14617   MODRM_CHECK;
14618   codep++;
14619
14620   if (modrm.mod == 3)
14621     OP_E_register (bytemode, sizeflag);
14622   else
14623     OP_E_memory (bytemode, sizeflag);
14624 }
14625
14626 static void
14627 OP_G (int bytemode, int sizeflag)
14628 {
14629   int add = 0;
14630   USED_REX (REX_R);
14631   if (rex & REX_R)
14632     add += 8;
14633   switch (bytemode)
14634     {
14635     case b_mode:
14636       USED_REX (0);
14637       if (rex)
14638         oappend (names8rex[modrm.reg + add]);
14639       else
14640         oappend (names8[modrm.reg + add]);
14641       break;
14642     case w_mode:
14643       oappend (names16[modrm.reg + add]);
14644       break;
14645     case d_mode:
14646       oappend (names32[modrm.reg + add]);
14647       break;
14648     case q_mode:
14649       oappend (names64[modrm.reg + add]);
14650       break;
14651     case bnd_mode:
14652       oappend (names_bnd[modrm.reg]);
14653       break;
14654     case v_mode:
14655     case dq_mode:
14656     case dqb_mode:
14657     case dqd_mode:
14658     case dqw_mode:
14659       USED_REX (REX_W);
14660       if (rex & REX_W)
14661         oappend (names64[modrm.reg + add]);
14662       else
14663         {
14664           if ((sizeflag & DFLAG) || bytemode != v_mode)
14665             oappend (names32[modrm.reg + add]);
14666           else
14667             oappend (names16[modrm.reg + add]);
14668           used_prefixes |= (prefixes & PREFIX_DATA);
14669         }
14670       break;
14671     case m_mode:
14672       if (address_mode == mode_64bit)
14673         oappend (names64[modrm.reg + add]);
14674       else
14675         oappend (names32[modrm.reg + add]);
14676       break;
14677     case mask_mode:
14678       oappend (names_mask[modrm.reg + add]);
14679       break;
14680     default:
14681       oappend (INTERNAL_DISASSEMBLER_ERROR);
14682       break;
14683     }
14684 }
14685
14686 static bfd_vma
14687 get64 (void)
14688 {
14689   bfd_vma x;
14690 #ifdef BFD64
14691   unsigned int a;
14692   unsigned int b;
14693
14694   FETCH_DATA (the_info, codep + 8);
14695   a = *codep++ & 0xff;
14696   a |= (*codep++ & 0xff) << 8;
14697   a |= (*codep++ & 0xff) << 16;
14698   a |= (*codep++ & 0xff) << 24;
14699   b = *codep++ & 0xff;
14700   b |= (*codep++ & 0xff) << 8;
14701   b |= (*codep++ & 0xff) << 16;
14702   b |= (*codep++ & 0xff) << 24;
14703   x = a + ((bfd_vma) b << 32);
14704 #else
14705   abort ();
14706   x = 0;
14707 #endif
14708   return x;
14709 }
14710
14711 static bfd_signed_vma
14712 get32 (void)
14713 {
14714   bfd_signed_vma x = 0;
14715
14716   FETCH_DATA (the_info, codep + 4);
14717   x = *codep++ & (bfd_signed_vma) 0xff;
14718   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14719   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14720   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14721   return x;
14722 }
14723
14724 static bfd_signed_vma
14725 get32s (void)
14726 {
14727   bfd_signed_vma x = 0;
14728
14729   FETCH_DATA (the_info, codep + 4);
14730   x = *codep++ & (bfd_signed_vma) 0xff;
14731   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14732   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14733   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14734
14735   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
14736
14737   return x;
14738 }
14739
14740 static int
14741 get16 (void)
14742 {
14743   int x = 0;
14744
14745   FETCH_DATA (the_info, codep + 2);
14746   x = *codep++ & 0xff;
14747   x |= (*codep++ & 0xff) << 8;
14748   return x;
14749 }
14750
14751 static void
14752 set_op (bfd_vma op, int riprel)
14753 {
14754   op_index[op_ad] = op_ad;
14755   if (address_mode == mode_64bit)
14756     {
14757       op_address[op_ad] = op;
14758       op_riprel[op_ad] = riprel;
14759     }
14760   else
14761     {
14762       /* Mask to get a 32-bit address.  */
14763       op_address[op_ad] = op & 0xffffffff;
14764       op_riprel[op_ad] = riprel & 0xffffffff;
14765     }
14766 }
14767
14768 static void
14769 OP_REG (int code, int sizeflag)
14770 {
14771   const char *s;
14772   int add;
14773
14774   switch (code)
14775     {
14776     case es_reg: case ss_reg: case cs_reg:
14777     case ds_reg: case fs_reg: case gs_reg:
14778       oappend (names_seg[code - es_reg]);
14779       return;
14780     }
14781
14782   USED_REX (REX_B);
14783   if (rex & REX_B)
14784     add = 8;
14785   else
14786     add = 0;
14787
14788   switch (code)
14789     {
14790     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14791     case sp_reg: case bp_reg: case si_reg: case di_reg:
14792       s = names16[code - ax_reg + add];
14793       break;
14794     case al_reg: case ah_reg: case cl_reg: case ch_reg:
14795     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14796       USED_REX (0);
14797       if (rex)
14798         s = names8rex[code - al_reg + add];
14799       else
14800         s = names8[code - al_reg];
14801       break;
14802     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
14803     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
14804       if (address_mode == mode_64bit
14805           && ((sizeflag & DFLAG) || (rex & REX_W)))
14806         {
14807           s = names64[code - rAX_reg + add];
14808           break;
14809         }
14810       code += eAX_reg - rAX_reg;
14811       /* Fall through.  */
14812     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14813     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14814       USED_REX (REX_W);
14815       if (rex & REX_W)
14816         s = names64[code - eAX_reg + add];
14817       else
14818         {
14819           if (sizeflag & DFLAG)
14820             s = names32[code - eAX_reg + add];
14821           else
14822             s = names16[code - eAX_reg + add];
14823           used_prefixes |= (prefixes & PREFIX_DATA);
14824         }
14825       break;
14826     default:
14827       s = INTERNAL_DISASSEMBLER_ERROR;
14828       break;
14829     }
14830   oappend (s);
14831 }
14832
14833 static void
14834 OP_IMREG (int code, int sizeflag)
14835 {
14836   const char *s;
14837
14838   switch (code)
14839     {
14840     case indir_dx_reg:
14841       if (intel_syntax)
14842         s = "dx";
14843       else
14844         s = "(%dx)";
14845       break;
14846     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14847     case sp_reg: case bp_reg: case si_reg: case di_reg:
14848       s = names16[code - ax_reg];
14849       break;
14850     case es_reg: case ss_reg: case cs_reg:
14851     case ds_reg: case fs_reg: case gs_reg:
14852       s = names_seg[code - es_reg];
14853       break;
14854     case al_reg: case ah_reg: case cl_reg: case ch_reg:
14855     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14856       USED_REX (0);
14857       if (rex)
14858         s = names8rex[code - al_reg];
14859       else
14860         s = names8[code - al_reg];
14861       break;
14862     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14863     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14864       USED_REX (REX_W);
14865       if (rex & REX_W)
14866         s = names64[code - eAX_reg];
14867       else
14868         {
14869           if (sizeflag & DFLAG)
14870             s = names32[code - eAX_reg];
14871           else
14872             s = names16[code - eAX_reg];
14873           used_prefixes |= (prefixes & PREFIX_DATA);
14874         }
14875       break;
14876     case z_mode_ax_reg:
14877       if ((rex & REX_W) || (sizeflag & DFLAG))
14878         s = *names32;
14879       else
14880         s = *names16;
14881       if (!(rex & REX_W))
14882         used_prefixes |= (prefixes & PREFIX_DATA);
14883       break;
14884     default:
14885       s = INTERNAL_DISASSEMBLER_ERROR;
14886       break;
14887     }
14888   oappend (s);
14889 }
14890
14891 static void
14892 OP_I (int bytemode, int sizeflag)
14893 {
14894   bfd_signed_vma op;
14895   bfd_signed_vma mask = -1;
14896
14897   switch (bytemode)
14898     {
14899     case b_mode:
14900       FETCH_DATA (the_info, codep + 1);
14901       op = *codep++;
14902       mask = 0xff;
14903       break;
14904     case q_mode:
14905       if (address_mode == mode_64bit)
14906         {
14907           op = get32s ();
14908           break;
14909         }
14910       /* Fall through.  */
14911     case v_mode:
14912       USED_REX (REX_W);
14913       if (rex & REX_W)
14914         op = get32s ();
14915       else
14916         {
14917           if (sizeflag & DFLAG)
14918             {
14919               op = get32 ();
14920               mask = 0xffffffff;
14921             }
14922           else
14923             {
14924               op = get16 ();
14925               mask = 0xfffff;
14926             }
14927           used_prefixes |= (prefixes & PREFIX_DATA);
14928         }
14929       break;
14930     case w_mode:
14931       mask = 0xfffff;
14932       op = get16 ();
14933       break;
14934     case const_1_mode:
14935       if (intel_syntax)
14936         oappend ("1");
14937       return;
14938     default:
14939       oappend (INTERNAL_DISASSEMBLER_ERROR);
14940       return;
14941     }
14942
14943   op &= mask;
14944   scratchbuf[0] = '$';
14945   print_operand_value (scratchbuf + 1, 1, op);
14946   oappend_maybe_intel (scratchbuf);
14947   scratchbuf[0] = '\0';
14948 }
14949
14950 static void
14951 OP_I64 (int bytemode, int sizeflag)
14952 {
14953   bfd_signed_vma op;
14954   bfd_signed_vma mask = -1;
14955
14956   if (address_mode != mode_64bit)
14957     {
14958       OP_I (bytemode, sizeflag);
14959       return;
14960     }
14961
14962   switch (bytemode)
14963     {
14964     case b_mode:
14965       FETCH_DATA (the_info, codep + 1);
14966       op = *codep++;
14967       mask = 0xff;
14968       break;
14969     case v_mode:
14970       USED_REX (REX_W);
14971       if (rex & REX_W)
14972         op = get64 ();
14973       else
14974         {
14975           if (sizeflag & DFLAG)
14976             {
14977               op = get32 ();
14978               mask = 0xffffffff;
14979             }
14980           else
14981             {
14982               op = get16 ();
14983               mask = 0xfffff;
14984             }
14985           used_prefixes |= (prefixes & PREFIX_DATA);
14986         }
14987       break;
14988     case w_mode:
14989       mask = 0xfffff;
14990       op = get16 ();
14991       break;
14992     default:
14993       oappend (INTERNAL_DISASSEMBLER_ERROR);
14994       return;
14995     }
14996
14997   op &= mask;
14998   scratchbuf[0] = '$';
14999   print_operand_value (scratchbuf + 1, 1, op);
15000   oappend_maybe_intel (scratchbuf);
15001   scratchbuf[0] = '\0';
15002 }
15003
15004 static void
15005 OP_sI (int bytemode, int sizeflag)
15006 {
15007   bfd_signed_vma op;
15008
15009   switch (bytemode)
15010     {
15011     case b_mode:
15012     case b_T_mode:
15013       FETCH_DATA (the_info, codep + 1);
15014       op = *codep++;
15015       if ((op & 0x80) != 0)
15016         op -= 0x100;
15017       if (bytemode == b_T_mode)
15018         {
15019           if (address_mode != mode_64bit
15020               || !((sizeflag & DFLAG) || (rex & REX_W)))
15021             {
15022               /* The operand-size prefix is overridden by a REX prefix.  */
15023               if ((sizeflag & DFLAG) || (rex & REX_W))
15024                 op &= 0xffffffff;
15025               else
15026                 op &= 0xffff;
15027           }
15028         }
15029       else
15030         {
15031           if (!(rex & REX_W))
15032             {
15033               if (sizeflag & DFLAG)
15034                 op &= 0xffffffff;
15035               else
15036                 op &= 0xffff;
15037             }
15038         }
15039       break;
15040     case v_mode:
15041       /* The operand-size prefix is overridden by a REX prefix.  */
15042       if ((sizeflag & DFLAG) || (rex & REX_W))
15043         op = get32s ();
15044       else
15045         op = get16 ();
15046       break;
15047     default:
15048       oappend (INTERNAL_DISASSEMBLER_ERROR);
15049       return;
15050     }
15051
15052   scratchbuf[0] = '$';
15053   print_operand_value (scratchbuf + 1, 1, op);
15054   oappend_maybe_intel (scratchbuf);
15055 }
15056
15057 static void
15058 OP_J (int bytemode, int sizeflag)
15059 {
15060   bfd_vma disp;
15061   bfd_vma mask = -1;
15062   bfd_vma segment = 0;
15063
15064   switch (bytemode)
15065     {
15066     case b_mode:
15067       FETCH_DATA (the_info, codep + 1);
15068       disp = *codep++;
15069       if ((disp & 0x80) != 0)
15070         disp -= 0x100;
15071       break;
15072     case v_mode:
15073       USED_REX (REX_W);
15074       if ((sizeflag & DFLAG) || (rex & REX_W))
15075         disp = get32s ();
15076       else
15077         {
15078           disp = get16 ();
15079           if ((disp & 0x8000) != 0)
15080             disp -= 0x10000;
15081           /* In 16bit mode, address is wrapped around at 64k within
15082              the same segment.  Otherwise, a data16 prefix on a jump
15083              instruction means that the pc is masked to 16 bits after
15084              the displacement is added!  */
15085           mask = 0xffff;
15086           if ((prefixes & PREFIX_DATA) == 0)
15087             segment = ((start_pc + codep - start_codep)
15088                        & ~((bfd_vma) 0xffff));
15089         }
15090       if (!(rex & REX_W))
15091         used_prefixes |= (prefixes & PREFIX_DATA);
15092       break;
15093     default:
15094       oappend (INTERNAL_DISASSEMBLER_ERROR);
15095       return;
15096     }
15097   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
15098   set_op (disp, 0);
15099   print_operand_value (scratchbuf, 1, disp);
15100   oappend (scratchbuf);
15101 }
15102
15103 static void
15104 OP_SEG (int bytemode, int sizeflag)
15105 {
15106   if (bytemode == w_mode)
15107     oappend (names_seg[modrm.reg]);
15108   else
15109     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
15110 }
15111
15112 static void
15113 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
15114 {
15115   int seg, offset;
15116
15117   if (sizeflag & DFLAG)
15118     {
15119       offset = get32 ();
15120       seg = get16 ();
15121     }
15122   else
15123     {
15124       offset = get16 ();
15125       seg = get16 ();
15126     }
15127   used_prefixes |= (prefixes & PREFIX_DATA);
15128   if (intel_syntax)
15129     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
15130   else
15131     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
15132   oappend (scratchbuf);
15133 }
15134
15135 static void
15136 OP_OFF (int bytemode, int sizeflag)
15137 {
15138   bfd_vma off;
15139
15140   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
15141     intel_operand_size (bytemode, sizeflag);
15142   append_seg ();
15143
15144   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
15145     off = get32 ();
15146   else
15147     off = get16 ();
15148
15149   if (intel_syntax)
15150     {
15151       if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
15152                         | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
15153         {
15154           oappend (names_seg[ds_reg - es_reg]);
15155           oappend (":");
15156         }
15157     }
15158   print_operand_value (scratchbuf, 1, off);
15159   oappend (scratchbuf);
15160 }
15161
15162 static void
15163 OP_OFF64 (int bytemode, int sizeflag)
15164 {
15165   bfd_vma off;
15166
15167   if (address_mode != mode_64bit
15168       || (prefixes & PREFIX_ADDR))
15169     {
15170       OP_OFF (bytemode, sizeflag);
15171       return;
15172     }
15173
15174   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
15175     intel_operand_size (bytemode, sizeflag);
15176   append_seg ();
15177
15178   off = get64 ();
15179
15180   if (intel_syntax)
15181     {
15182       if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
15183                         | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
15184         {
15185           oappend (names_seg[ds_reg - es_reg]);
15186           oappend (":");
15187         }
15188     }
15189   print_operand_value (scratchbuf, 1, off);
15190   oappend (scratchbuf);
15191 }
15192
15193 static void
15194 ptr_reg (int code, int sizeflag)
15195 {
15196   const char *s;
15197
15198   *obufp++ = open_char;
15199   used_prefixes |= (prefixes & PREFIX_ADDR);
15200   if (address_mode == mode_64bit)
15201     {
15202       if (!(sizeflag & AFLAG))
15203         s = names32[code - eAX_reg];
15204       else
15205         s = names64[code - eAX_reg];
15206     }
15207   else if (sizeflag & AFLAG)
15208     s = names32[code - eAX_reg];
15209   else
15210     s = names16[code - eAX_reg];
15211   oappend (s);
15212   *obufp++ = close_char;
15213   *obufp = 0;
15214 }
15215
15216 static void
15217 OP_ESreg (int code, int sizeflag)
15218 {
15219   if (intel_syntax)
15220     {
15221       switch (codep[-1])
15222         {
15223         case 0x6d:      /* insw/insl */
15224           intel_operand_size (z_mode, sizeflag);
15225           break;
15226         case 0xa5:      /* movsw/movsl/movsq */
15227         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15228         case 0xab:      /* stosw/stosl */
15229         case 0xaf:      /* scasw/scasl */
15230           intel_operand_size (v_mode, sizeflag);
15231           break;
15232         default:
15233           intel_operand_size (b_mode, sizeflag);
15234         }
15235     }
15236   oappend_maybe_intel ("%es:");
15237   ptr_reg (code, sizeflag);
15238 }
15239
15240 static void
15241 OP_DSreg (int code, int sizeflag)
15242 {
15243   if (intel_syntax)
15244     {
15245       switch (codep[-1])
15246         {
15247         case 0x6f:      /* outsw/outsl */
15248           intel_operand_size (z_mode, sizeflag);
15249           break;
15250         case 0xa5:      /* movsw/movsl/movsq */
15251         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15252         case 0xad:      /* lodsw/lodsl/lodsq */
15253           intel_operand_size (v_mode, sizeflag);
15254           break;
15255         default:
15256           intel_operand_size (b_mode, sizeflag);
15257         }
15258     }
15259   if ((prefixes
15260        & (PREFIX_CS
15261           | PREFIX_DS
15262           | PREFIX_SS
15263           | PREFIX_ES
15264           | PREFIX_FS
15265           | PREFIX_GS)) == 0)
15266     prefixes |= PREFIX_DS;
15267   append_seg ();
15268   ptr_reg (code, sizeflag);
15269 }
15270
15271 static void
15272 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15273 {
15274   int add;
15275   if (rex & REX_R)
15276     {
15277       USED_REX (REX_R);
15278       add = 8;
15279     }
15280   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
15281     {
15282       all_prefixes[last_lock_prefix] = 0;
15283       used_prefixes |= PREFIX_LOCK;
15284       add = 8;
15285     }
15286   else
15287     add = 0;
15288   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
15289   oappend_maybe_intel (scratchbuf);
15290 }
15291
15292 static void
15293 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15294 {
15295   int add;
15296   USED_REX (REX_R);
15297   if (rex & REX_R)
15298     add = 8;
15299   else
15300     add = 0;
15301   if (intel_syntax)
15302     sprintf (scratchbuf, "db%d", modrm.reg + add);
15303   else
15304     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
15305   oappend (scratchbuf);
15306 }
15307
15308 static void
15309 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15310 {
15311   sprintf (scratchbuf, "%%tr%d", modrm.reg);
15312   oappend_maybe_intel (scratchbuf);
15313 }
15314
15315 static void
15316 OP_R (int bytemode, int sizeflag)
15317 {
15318   if (modrm.mod == 3)
15319     OP_E (bytemode, sizeflag);
15320   else
15321     BadOp ();
15322 }
15323
15324 static void
15325 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15326 {
15327   int reg = modrm.reg;
15328   const char **names;
15329
15330   used_prefixes |= (prefixes & PREFIX_DATA);
15331   if (prefixes & PREFIX_DATA)
15332     {
15333       names = names_xmm;
15334       USED_REX (REX_R);
15335       if (rex & REX_R)
15336         reg += 8;
15337     }
15338   else
15339     names = names_mm;
15340   oappend (names[reg]);
15341 }
15342
15343 static void
15344 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15345 {
15346   int reg = modrm.reg;
15347   const char **names;
15348
15349   USED_REX (REX_R);
15350   if (rex & REX_R)
15351     reg += 8;
15352   if (vex.evex)
15353     {
15354       if (!vex.r)
15355         reg += 16;
15356     }
15357
15358   if (need_vex
15359       && bytemode != xmm_mode
15360       && bytemode != xmmq_mode
15361       && bytemode != evex_half_bcst_xmmq_mode
15362       && bytemode != ymm_mode
15363       && bytemode != scalar_mode)
15364     {
15365       switch (vex.length)
15366         {
15367         case 128:
15368           names = names_xmm;
15369           break;
15370         case 256:
15371           if (vex.w || bytemode != vex_vsib_q_w_dq_mode)
15372             names = names_ymm;
15373           else
15374             names = names_xmm;
15375           break;
15376         case 512:
15377           names = names_zmm;
15378           break;
15379         default:
15380           abort ();
15381         }
15382     }
15383   else if (bytemode == xmmq_mode
15384            || bytemode == evex_half_bcst_xmmq_mode)
15385     {
15386       switch (vex.length)
15387         {
15388         case 128:
15389         case 256:
15390           names = names_xmm;
15391           break;
15392         case 512:
15393           names = names_ymm;
15394           break;
15395         default:
15396           abort ();
15397         }
15398     }
15399   else if (bytemode == ymm_mode)
15400     names = names_ymm;
15401   else
15402     names = names_xmm;
15403   oappend (names[reg]);
15404 }
15405
15406 static void
15407 OP_EM (int bytemode, int sizeflag)
15408 {
15409   int reg;
15410   const char **names;
15411
15412   if (modrm.mod != 3)
15413     {
15414       if (intel_syntax
15415           && (bytemode == v_mode || bytemode == v_swap_mode))
15416         {
15417           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15418           used_prefixes |= (prefixes & PREFIX_DATA);
15419         }
15420       OP_E (bytemode, sizeflag);
15421       return;
15422     }
15423
15424   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
15425     swap_operand ();
15426
15427   /* Skip mod/rm byte.  */
15428   MODRM_CHECK;
15429   codep++;
15430   used_prefixes |= (prefixes & PREFIX_DATA);
15431   reg = modrm.rm;
15432   if (prefixes & PREFIX_DATA)
15433     {
15434       names = names_xmm;
15435       USED_REX (REX_B);
15436       if (rex & REX_B)
15437         reg += 8;
15438     }
15439   else
15440     names = names_mm;
15441   oappend (names[reg]);
15442 }
15443
15444 /* cvt* are the only instructions in sse2 which have
15445    both SSE and MMX operands and also have 0x66 prefix
15446    in their opcode. 0x66 was originally used to differentiate
15447    between SSE and MMX instruction(operands). So we have to handle the
15448    cvt* separately using OP_EMC and OP_MXC */
15449 static void
15450 OP_EMC (int bytemode, int sizeflag)
15451 {
15452   if (modrm.mod != 3)
15453     {
15454       if (intel_syntax && bytemode == v_mode)
15455         {
15456           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15457           used_prefixes |= (prefixes & PREFIX_DATA);
15458         }
15459       OP_E (bytemode, sizeflag);
15460       return;
15461     }
15462
15463   /* Skip mod/rm byte.  */
15464   MODRM_CHECK;
15465   codep++;
15466   used_prefixes |= (prefixes & PREFIX_DATA);
15467   oappend (names_mm[modrm.rm]);
15468 }
15469
15470 static void
15471 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15472 {
15473   used_prefixes |= (prefixes & PREFIX_DATA);
15474   oappend (names_mm[modrm.reg]);
15475 }
15476
15477 static void
15478 OP_EX (int bytemode, int sizeflag)
15479 {
15480   int reg;
15481   const char **names;
15482
15483   /* Skip mod/rm byte.  */
15484   MODRM_CHECK;
15485   codep++;
15486
15487   if (modrm.mod != 3)
15488     {
15489       OP_E_memory (bytemode, sizeflag);
15490       return;
15491     }
15492
15493   reg = modrm.rm;
15494   USED_REX (REX_B);
15495   if (rex & REX_B)
15496     reg += 8;
15497   if (vex.evex)
15498     {
15499       USED_REX (REX_X);
15500       if ((rex & REX_X))
15501         reg += 16;
15502     }
15503
15504   if ((sizeflag & SUFFIX_ALWAYS)
15505       && (bytemode == x_swap_mode
15506           || bytemode == d_swap_mode
15507           || bytemode == d_scalar_swap_mode
15508           || bytemode == q_swap_mode
15509           || bytemode == q_scalar_swap_mode))
15510     swap_operand ();
15511
15512   if (need_vex
15513       && bytemode != xmm_mode
15514       && bytemode != xmmdw_mode
15515       && bytemode != xmmqd_mode
15516       && bytemode != xmm_mb_mode
15517       && bytemode != xmm_mw_mode
15518       && bytemode != xmm_md_mode
15519       && bytemode != xmm_mq_mode
15520       && bytemode != xmm_mdq_mode
15521       && bytemode != xmmq_mode
15522       && bytemode != evex_half_bcst_xmmq_mode
15523       && bytemode != ymm_mode
15524       && bytemode != d_scalar_mode
15525       && bytemode != d_scalar_swap_mode
15526       && bytemode != q_scalar_mode
15527       && bytemode != q_scalar_swap_mode
15528       && bytemode != vex_scalar_w_dq_mode)
15529     {
15530       switch (vex.length)
15531         {
15532         case 128:
15533           names = names_xmm;
15534           break;
15535         case 256:
15536           names = names_ymm;
15537           break;
15538         case 512:
15539           names = names_zmm;
15540           break;
15541         default:
15542           abort ();
15543         }
15544     }
15545   else if (bytemode == xmmq_mode
15546            || bytemode == evex_half_bcst_xmmq_mode)
15547     {
15548       switch (vex.length)
15549         {
15550         case 128:
15551         case 256:
15552           names = names_xmm;
15553           break;
15554         case 512:
15555           names = names_ymm;
15556           break;
15557         default:
15558           abort ();
15559         }
15560     }
15561   else if (bytemode == ymm_mode)
15562     names = names_ymm;
15563   else
15564     names = names_xmm;
15565   oappend (names[reg]);
15566 }
15567
15568 static void
15569 OP_MS (int bytemode, int sizeflag)
15570 {
15571   if (modrm.mod == 3)
15572     OP_EM (bytemode, sizeflag);
15573   else
15574     BadOp ();
15575 }
15576
15577 static void
15578 OP_XS (int bytemode, int sizeflag)
15579 {
15580   if (modrm.mod == 3)
15581     OP_EX (bytemode, sizeflag);
15582   else
15583     BadOp ();
15584 }
15585
15586 static void
15587 OP_M (int bytemode, int sizeflag)
15588 {
15589   if (modrm.mod == 3)
15590     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
15591     BadOp ();
15592   else
15593     OP_E (bytemode, sizeflag);
15594 }
15595
15596 static void
15597 OP_0f07 (int bytemode, int sizeflag)
15598 {
15599   if (modrm.mod != 3 || modrm.rm != 0)
15600     BadOp ();
15601   else
15602     OP_E (bytemode, sizeflag);
15603 }
15604
15605 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
15606    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
15607
15608 static void
15609 NOP_Fixup1 (int bytemode, int sizeflag)
15610 {
15611   if ((prefixes & PREFIX_DATA) != 0
15612       || (rex != 0
15613           && rex != 0x48
15614           && address_mode == mode_64bit))
15615     OP_REG (bytemode, sizeflag);
15616   else
15617     strcpy (obuf, "nop");
15618 }
15619
15620 static void
15621 NOP_Fixup2 (int bytemode, int sizeflag)
15622 {
15623   if ((prefixes & PREFIX_DATA) != 0
15624       || (rex != 0
15625           && rex != 0x48
15626           && address_mode == mode_64bit))
15627     OP_IMREG (bytemode, sizeflag);
15628 }
15629
15630 static const char *const Suffix3DNow[] = {
15631 /* 00 */        NULL,           NULL,           NULL,           NULL,
15632 /* 04 */        NULL,           NULL,           NULL,           NULL,
15633 /* 08 */        NULL,           NULL,           NULL,           NULL,
15634 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
15635 /* 10 */        NULL,           NULL,           NULL,           NULL,
15636 /* 14 */        NULL,           NULL,           NULL,           NULL,
15637 /* 18 */        NULL,           NULL,           NULL,           NULL,
15638 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
15639 /* 20 */        NULL,           NULL,           NULL,           NULL,
15640 /* 24 */        NULL,           NULL,           NULL,           NULL,
15641 /* 28 */        NULL,           NULL,           NULL,           NULL,
15642 /* 2C */        NULL,           NULL,           NULL,           NULL,
15643 /* 30 */        NULL,           NULL,           NULL,           NULL,
15644 /* 34 */        NULL,           NULL,           NULL,           NULL,
15645 /* 38 */        NULL,           NULL,           NULL,           NULL,
15646 /* 3C */        NULL,           NULL,           NULL,           NULL,
15647 /* 40 */        NULL,           NULL,           NULL,           NULL,
15648 /* 44 */        NULL,           NULL,           NULL,           NULL,
15649 /* 48 */        NULL,           NULL,           NULL,           NULL,
15650 /* 4C */        NULL,           NULL,           NULL,           NULL,
15651 /* 50 */        NULL,           NULL,           NULL,           NULL,
15652 /* 54 */        NULL,           NULL,           NULL,           NULL,
15653 /* 58 */        NULL,           NULL,           NULL,           NULL,
15654 /* 5C */        NULL,           NULL,           NULL,           NULL,
15655 /* 60 */        NULL,           NULL,           NULL,           NULL,
15656 /* 64 */        NULL,           NULL,           NULL,           NULL,
15657 /* 68 */        NULL,           NULL,           NULL,           NULL,
15658 /* 6C */        NULL,           NULL,           NULL,           NULL,
15659 /* 70 */        NULL,           NULL,           NULL,           NULL,
15660 /* 74 */        NULL,           NULL,           NULL,           NULL,
15661 /* 78 */        NULL,           NULL,           NULL,           NULL,
15662 /* 7C */        NULL,           NULL,           NULL,           NULL,
15663 /* 80 */        NULL,           NULL,           NULL,           NULL,
15664 /* 84 */        NULL,           NULL,           NULL,           NULL,
15665 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
15666 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
15667 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
15668 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
15669 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
15670 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
15671 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
15672 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
15673 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
15674 /* AC */        NULL,           NULL,           "pfacc",        NULL,
15675 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
15676 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
15677 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
15678 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
15679 /* C0 */        NULL,           NULL,           NULL,           NULL,
15680 /* C4 */        NULL,           NULL,           NULL,           NULL,
15681 /* C8 */        NULL,           NULL,           NULL,           NULL,
15682 /* CC */        NULL,           NULL,           NULL,           NULL,
15683 /* D0 */        NULL,           NULL,           NULL,           NULL,
15684 /* D4 */        NULL,           NULL,           NULL,           NULL,
15685 /* D8 */        NULL,           NULL,           NULL,           NULL,
15686 /* DC */        NULL,           NULL,           NULL,           NULL,
15687 /* E0 */        NULL,           NULL,           NULL,           NULL,
15688 /* E4 */        NULL,           NULL,           NULL,           NULL,
15689 /* E8 */        NULL,           NULL,           NULL,           NULL,
15690 /* EC */        NULL,           NULL,           NULL,           NULL,
15691 /* F0 */        NULL,           NULL,           NULL,           NULL,
15692 /* F4 */        NULL,           NULL,           NULL,           NULL,
15693 /* F8 */        NULL,           NULL,           NULL,           NULL,
15694 /* FC */        NULL,           NULL,           NULL,           NULL,
15695 };
15696
15697 static void
15698 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15699 {
15700   const char *mnemonic;
15701
15702   FETCH_DATA (the_info, codep + 1);
15703   /* AMD 3DNow! instructions are specified by an opcode suffix in the
15704      place where an 8-bit immediate would normally go.  ie. the last
15705      byte of the instruction.  */
15706   obufp = mnemonicendp;
15707   mnemonic = Suffix3DNow[*codep++ & 0xff];
15708   if (mnemonic)
15709     oappend (mnemonic);
15710   else
15711     {
15712       /* Since a variable sized modrm/sib chunk is between the start
15713          of the opcode (0x0f0f) and the opcode suffix, we need to do
15714          all the modrm processing first, and don't know until now that
15715          we have a bad opcode.  This necessitates some cleaning up.  */
15716       op_out[0][0] = '\0';
15717       op_out[1][0] = '\0';
15718       BadOp ();
15719     }
15720   mnemonicendp = obufp;
15721 }
15722
15723 static struct op simd_cmp_op[] =
15724 {
15725   { STRING_COMMA_LEN ("eq") },
15726   { STRING_COMMA_LEN ("lt") },
15727   { STRING_COMMA_LEN ("le") },
15728   { STRING_COMMA_LEN ("unord") },
15729   { STRING_COMMA_LEN ("neq") },
15730   { STRING_COMMA_LEN ("nlt") },
15731   { STRING_COMMA_LEN ("nle") },
15732   { STRING_COMMA_LEN ("ord") }
15733 };
15734
15735 static void
15736 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15737 {
15738   unsigned int cmp_type;
15739
15740   FETCH_DATA (the_info, codep + 1);
15741   cmp_type = *codep++ & 0xff;
15742   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
15743     {
15744       char suffix [3];
15745       char *p = mnemonicendp - 2;
15746       suffix[0] = p[0];
15747       suffix[1] = p[1];
15748       suffix[2] = '\0';
15749       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
15750       mnemonicendp += simd_cmp_op[cmp_type].len;
15751     }
15752   else
15753     {
15754       /* We have a reserved extension byte.  Output it directly.  */
15755       scratchbuf[0] = '$';
15756       print_operand_value (scratchbuf + 1, 1, cmp_type);
15757       oappend_maybe_intel (scratchbuf);
15758       scratchbuf[0] = '\0';
15759     }
15760 }
15761
15762 static void
15763 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
15764           int sizeflag ATTRIBUTE_UNUSED)
15765 {
15766   /* mwait %eax,%ecx  */
15767   if (!intel_syntax)
15768     {
15769       const char **names = (address_mode == mode_64bit
15770                             ? names64 : names32);
15771       strcpy (op_out[0], names[0]);
15772       strcpy (op_out[1], names[1]);
15773       two_source_ops = 1;
15774     }
15775   /* Skip mod/rm byte.  */
15776   MODRM_CHECK;
15777   codep++;
15778 }
15779
15780 static void
15781 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
15782             int sizeflag ATTRIBUTE_UNUSED)
15783 {
15784   /* monitor %eax,%ecx,%edx"  */
15785   if (!intel_syntax)
15786     {
15787       const char **op1_names;
15788       const char **names = (address_mode == mode_64bit
15789                             ? names64 : names32);
15790
15791       if (!(prefixes & PREFIX_ADDR))
15792         op1_names = (address_mode == mode_16bit
15793                      ? names16 : names);
15794       else
15795         {
15796           /* Remove "addr16/addr32".  */
15797           all_prefixes[last_addr_prefix] = 0;
15798           op1_names = (address_mode != mode_32bit
15799                        ? names32 : names16);
15800           used_prefixes |= PREFIX_ADDR;
15801         }
15802       strcpy (op_out[0], op1_names[0]);
15803       strcpy (op_out[1], names[1]);
15804       strcpy (op_out[2], names[2]);
15805       two_source_ops = 1;
15806     }
15807   /* Skip mod/rm byte.  */
15808   MODRM_CHECK;
15809   codep++;
15810 }
15811
15812 static void
15813 BadOp (void)
15814 {
15815   /* Throw away prefixes and 1st. opcode byte.  */
15816   codep = insn_codep + 1;
15817   oappend ("(bad)");
15818 }
15819
15820 static void
15821 REP_Fixup (int bytemode, int sizeflag)
15822 {
15823   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
15824      lods and stos.  */
15825   if (prefixes & PREFIX_REPZ)
15826     all_prefixes[last_repz_prefix] = REP_PREFIX;
15827
15828   switch (bytemode)
15829     {
15830     case al_reg:
15831     case eAX_reg:
15832     case indir_dx_reg:
15833       OP_IMREG (bytemode, sizeflag);
15834       break;
15835     case eDI_reg:
15836       OP_ESreg (bytemode, sizeflag);
15837       break;
15838     case eSI_reg:
15839       OP_DSreg (bytemode, sizeflag);
15840       break;
15841     default:
15842       abort ();
15843       break;
15844     }
15845 }
15846
15847 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
15848    "bnd".  */
15849
15850 static void
15851 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15852 {
15853   if (prefixes & PREFIX_REPNZ)
15854     all_prefixes[last_repnz_prefix] = BND_PREFIX;
15855 }
15856
15857 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
15858    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
15859  */
15860
15861 static void
15862 HLE_Fixup1 (int bytemode, int sizeflag)
15863 {
15864   if (modrm.mod != 3
15865       && (prefixes & PREFIX_LOCK) != 0)
15866     {
15867       if (prefixes & PREFIX_REPZ)
15868         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15869       if (prefixes & PREFIX_REPNZ)
15870         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15871     }
15872
15873   OP_E (bytemode, sizeflag);
15874 }
15875
15876 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
15877    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
15878  */
15879
15880 static void
15881 HLE_Fixup2 (int bytemode, int sizeflag)
15882 {
15883   if (modrm.mod != 3)
15884     {
15885       if (prefixes & PREFIX_REPZ)
15886         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15887       if (prefixes & PREFIX_REPNZ)
15888         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15889     }
15890
15891   OP_E (bytemode, sizeflag);
15892 }
15893
15894 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
15895    "xrelease" for memory operand.  No check for LOCK prefix.   */
15896
15897 static void
15898 HLE_Fixup3 (int bytemode, int sizeflag)
15899 {
15900   if (modrm.mod != 3
15901       && last_repz_prefix > last_repnz_prefix
15902       && (prefixes & PREFIX_REPZ) != 0)
15903     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15904
15905   OP_E (bytemode, sizeflag);
15906 }
15907
15908 static void
15909 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
15910 {
15911   USED_REX (REX_W);
15912   if (rex & REX_W)
15913     {
15914       /* Change cmpxchg8b to cmpxchg16b.  */
15915       char *p = mnemonicendp - 2;
15916       mnemonicendp = stpcpy (p, "16b");
15917       bytemode = o_mode;
15918     }
15919   else if ((prefixes & PREFIX_LOCK) != 0)
15920     {
15921       if (prefixes & PREFIX_REPZ)
15922         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15923       if (prefixes & PREFIX_REPNZ)
15924         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15925     }
15926
15927   OP_M (bytemode, sizeflag);
15928 }
15929
15930 static void
15931 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
15932 {
15933   const char **names;
15934
15935   if (need_vex)
15936     {
15937       switch (vex.length)
15938         {
15939         case 128:
15940           names = names_xmm;
15941           break;
15942         case 256:
15943           names = names_ymm;
15944           break;
15945         default:
15946           abort ();
15947         }
15948     }
15949   else
15950     names = names_xmm;
15951   oappend (names[reg]);
15952 }
15953
15954 static void
15955 CRC32_Fixup (int bytemode, int sizeflag)
15956 {
15957   /* Add proper suffix to "crc32".  */
15958   char *p = mnemonicendp;
15959
15960   switch (bytemode)
15961     {
15962     case b_mode:
15963       if (intel_syntax)
15964         goto skip;
15965
15966       *p++ = 'b';
15967       break;
15968     case v_mode:
15969       if (intel_syntax)
15970         goto skip;
15971
15972       USED_REX (REX_W);
15973       if (rex & REX_W)
15974         *p++ = 'q';
15975       else
15976         {
15977           if (sizeflag & DFLAG)
15978             *p++ = 'l';
15979           else
15980             *p++ = 'w';
15981           used_prefixes |= (prefixes & PREFIX_DATA);
15982         }
15983       break;
15984     default:
15985       oappend (INTERNAL_DISASSEMBLER_ERROR);
15986       break;
15987     }
15988   mnemonicendp = p;
15989   *p = '\0';
15990
15991 skip:
15992   if (modrm.mod == 3)
15993     {
15994       int add;
15995
15996       /* Skip mod/rm byte.  */
15997       MODRM_CHECK;
15998       codep++;
15999
16000       USED_REX (REX_B);
16001       add = (rex & REX_B) ? 8 : 0;
16002       if (bytemode == b_mode)
16003         {
16004           USED_REX (0);
16005           if (rex)
16006             oappend (names8rex[modrm.rm + add]);
16007           else
16008             oappend (names8[modrm.rm + add]);
16009         }
16010       else
16011         {
16012           USED_REX (REX_W);
16013           if (rex & REX_W)
16014             oappend (names64[modrm.rm + add]);
16015           else if ((prefixes & PREFIX_DATA))
16016             oappend (names16[modrm.rm + add]);
16017           else
16018             oappend (names32[modrm.rm + add]);
16019         }
16020     }
16021   else
16022     OP_E (bytemode, sizeflag);
16023 }
16024
16025 static void
16026 FXSAVE_Fixup (int bytemode, int sizeflag)
16027 {
16028   /* Add proper suffix to "fxsave" and "fxrstor".  */
16029   USED_REX (REX_W);
16030   if (rex & REX_W)
16031     {
16032       char *p = mnemonicendp;
16033       *p++ = '6';
16034       *p++ = '4';
16035       *p = '\0';
16036       mnemonicendp = p;
16037     }
16038   OP_M (bytemode, sizeflag);
16039 }
16040
16041 /* Display the destination register operand for instructions with
16042    VEX. */
16043
16044 static void
16045 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16046 {
16047   int reg;
16048   const char **names;
16049
16050   if (!need_vex)
16051     abort ();
16052
16053   if (!need_vex_reg)
16054     return;
16055
16056   reg = vex.register_specifier;
16057   if (vex.evex)
16058     {
16059       if (!vex.v)
16060         reg += 16;
16061     }
16062
16063   if (bytemode == vex_scalar_mode)
16064     {
16065       oappend (names_xmm[reg]);
16066       return;
16067     }
16068
16069   switch (vex.length)
16070     {
16071     case 128:
16072       switch (bytemode)
16073         {
16074         case vex_mode:
16075         case vex128_mode:
16076         case vex_vsib_q_w_dq_mode:
16077           names = names_xmm;
16078           break;
16079         case dq_mode:
16080           if (vex.w)
16081             names = names64;
16082           else
16083             names = names32;
16084           break;
16085         case mask_mode:
16086           names = names_mask;
16087           break;
16088         default:
16089           abort ();
16090           return;
16091         }
16092       break;
16093     case 256:
16094       switch (bytemode)
16095         {
16096         case vex_mode:
16097         case vex256_mode:
16098           names = names_ymm;
16099           break;
16100         case vex_vsib_q_w_dq_mode:
16101           names = vex.w ? names_ymm : names_xmm;
16102           break;
16103         case mask_mode:
16104           names = names_mask;
16105           break;
16106         default:
16107           abort ();
16108           return;
16109         }
16110       break;
16111     case 512:
16112       names = names_zmm;
16113       break;
16114     default:
16115       abort ();
16116       break;
16117     }
16118   oappend (names[reg]);
16119 }
16120
16121 /* Get the VEX immediate byte without moving codep.  */
16122
16123 static unsigned char
16124 get_vex_imm8 (int sizeflag, int opnum)
16125 {
16126   int bytes_before_imm = 0;
16127
16128   if (modrm.mod != 3)
16129     {
16130       /* There are SIB/displacement bytes.  */
16131       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
16132         {
16133           /* 32/64 bit address mode */
16134           int base = modrm.rm;
16135
16136           /* Check SIB byte.  */
16137           if (base == 4)
16138             {
16139               FETCH_DATA (the_info, codep + 1);
16140               base = *codep & 7;
16141               /* When decoding the third source, don't increase
16142                  bytes_before_imm as this has already been incremented
16143                  by one in OP_E_memory while decoding the second
16144                  source operand.  */
16145               if (opnum == 0)
16146                 bytes_before_imm++;
16147             }
16148
16149           /* Don't increase bytes_before_imm when decoding the third source,
16150              it has already been incremented by OP_E_memory while decoding
16151              the second source operand.  */
16152           if (opnum == 0)
16153             {
16154               switch (modrm.mod)
16155                 {
16156                   case 0:
16157                     /* When modrm.rm == 5 or modrm.rm == 4 and base in
16158                        SIB == 5, there is a 4 byte displacement.  */
16159                     if (base != 5)
16160                       /* No displacement. */
16161                       break;
16162                   case 2:
16163                     /* 4 byte displacement.  */
16164                     bytes_before_imm += 4;
16165                     break;
16166                   case 1:
16167                     /* 1 byte displacement.  */
16168                     bytes_before_imm++;
16169                     break;
16170                 }
16171             }
16172         }
16173       else
16174         {
16175           /* 16 bit address mode */
16176           /* Don't increase bytes_before_imm when decoding the third source,
16177              it has already been incremented by OP_E_memory while decoding
16178              the second source operand.  */
16179           if (opnum == 0)
16180             {
16181               switch (modrm.mod)
16182                 {
16183                 case 0:
16184                   /* When modrm.rm == 6, there is a 2 byte displacement.  */
16185                   if (modrm.rm != 6)
16186                     /* No displacement. */
16187                     break;
16188                 case 2:
16189                   /* 2 byte displacement.  */
16190                   bytes_before_imm += 2;
16191                   break;
16192                 case 1:
16193                   /* 1 byte displacement: when decoding the third source,
16194                      don't increase bytes_before_imm as this has already
16195                      been incremented by one in OP_E_memory while decoding
16196                      the second source operand.  */
16197                   if (opnum == 0)
16198                     bytes_before_imm++;
16199
16200                   break;
16201                 }
16202             }
16203         }
16204     }
16205
16206   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
16207   return codep [bytes_before_imm];
16208 }
16209
16210 static void
16211 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
16212 {
16213   const char **names;
16214
16215   if (reg == -1 && modrm.mod != 3)
16216     {
16217       OP_E_memory (bytemode, sizeflag);
16218       return;
16219     }
16220   else
16221     {
16222       if (reg == -1)
16223         {
16224           reg = modrm.rm;
16225           USED_REX (REX_B);
16226           if (rex & REX_B)
16227             reg += 8;
16228         }
16229       else if (reg > 7 && address_mode != mode_64bit)
16230         BadOp ();
16231     }
16232
16233   switch (vex.length)
16234     {
16235     case 128:
16236       names = names_xmm;
16237       break;
16238     case 256:
16239       names = names_ymm;
16240       break;
16241     default:
16242       abort ();
16243     }
16244   oappend (names[reg]);
16245 }
16246
16247 static void
16248 OP_EX_VexImmW (int bytemode, int sizeflag)
16249 {
16250   int reg = -1;
16251   static unsigned char vex_imm8;
16252
16253   if (vex_w_done == 0)
16254     {
16255       vex_w_done = 1;
16256
16257       /* Skip mod/rm byte.  */
16258       MODRM_CHECK;
16259       codep++;
16260
16261       vex_imm8 = get_vex_imm8 (sizeflag, 0);
16262
16263       if (vex.w)
16264           reg = vex_imm8 >> 4;
16265
16266       OP_EX_VexReg (bytemode, sizeflag, reg);
16267     }
16268   else if (vex_w_done == 1)
16269     {
16270       vex_w_done = 2;
16271
16272       if (!vex.w)
16273           reg = vex_imm8 >> 4;
16274
16275       OP_EX_VexReg (bytemode, sizeflag, reg);
16276     }
16277   else
16278     {
16279       /* Output the imm8 directly.  */
16280       scratchbuf[0] = '$';
16281       print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
16282       oappend_maybe_intel (scratchbuf);
16283       scratchbuf[0] = '\0';
16284       codep++;
16285     }
16286 }
16287
16288 static void
16289 OP_Vex_2src (int bytemode, int sizeflag)
16290 {
16291   if (modrm.mod == 3)
16292     {
16293       int reg = modrm.rm;
16294       USED_REX (REX_B);
16295       if (rex & REX_B)
16296         reg += 8;
16297       oappend (names_xmm[reg]);
16298     }
16299   else
16300     {
16301       if (intel_syntax
16302           && (bytemode == v_mode || bytemode == v_swap_mode))
16303         {
16304           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16305           used_prefixes |= (prefixes & PREFIX_DATA);
16306         }
16307       OP_E (bytemode, sizeflag);
16308     }
16309 }
16310
16311 static void
16312 OP_Vex_2src_1 (int bytemode, int sizeflag)
16313 {
16314   if (modrm.mod == 3)
16315     {
16316       /* Skip mod/rm byte.   */
16317       MODRM_CHECK;
16318       codep++;
16319     }
16320
16321   if (vex.w)
16322     oappend (names_xmm[vex.register_specifier]);
16323   else
16324     OP_Vex_2src (bytemode, sizeflag);
16325 }
16326
16327 static void
16328 OP_Vex_2src_2 (int bytemode, int sizeflag)
16329 {
16330   if (vex.w)
16331     OP_Vex_2src (bytemode, sizeflag);
16332   else
16333     oappend (names_xmm[vex.register_specifier]);
16334 }
16335
16336 static void
16337 OP_EX_VexW (int bytemode, int sizeflag)
16338 {
16339   int reg = -1;
16340
16341   if (!vex_w_done)
16342     {
16343       vex_w_done = 1;
16344
16345       /* Skip mod/rm byte.  */
16346       MODRM_CHECK;
16347       codep++;
16348
16349       if (vex.w)
16350         reg = get_vex_imm8 (sizeflag, 0) >> 4;
16351     }
16352   else
16353     {
16354       if (!vex.w)
16355         reg = get_vex_imm8 (sizeflag, 1) >> 4;
16356     }
16357
16358   OP_EX_VexReg (bytemode, sizeflag, reg);
16359 }
16360
16361 static void
16362 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,
16363              int sizeflag ATTRIBUTE_UNUSED)
16364 {
16365   /* Skip the immediate byte and check for invalid bits.  */
16366   FETCH_DATA (the_info, codep + 1);
16367   if (*codep++ & 0xf)
16368     BadOp ();
16369 }
16370
16371 static void
16372 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16373 {
16374   int reg;
16375   const char **names;
16376
16377   FETCH_DATA (the_info, codep + 1);
16378   reg = *codep++;
16379
16380   if (bytemode != x_mode)
16381     abort ();
16382
16383   if (reg & 0xf)
16384       BadOp ();
16385
16386   reg >>= 4;
16387   if (reg > 7 && address_mode != mode_64bit)
16388     BadOp ();
16389
16390   switch (vex.length)
16391     {
16392     case 128:
16393       names = names_xmm;
16394       break;
16395     case 256:
16396       names = names_ymm;
16397       break;
16398     default:
16399       abort ();
16400     }
16401   oappend (names[reg]);
16402 }
16403
16404 static void
16405 OP_XMM_VexW (int bytemode, int sizeflag)
16406 {
16407   /* Turn off the REX.W bit since it is used for swapping operands
16408      now.  */
16409   rex &= ~REX_W;
16410   OP_XMM (bytemode, sizeflag);
16411 }
16412
16413 static void
16414 OP_EX_Vex (int bytemode, int sizeflag)
16415 {
16416   if (modrm.mod != 3)
16417     {
16418       if (vex.register_specifier != 0)
16419         BadOp ();
16420       need_vex_reg = 0;
16421     }
16422   OP_EX (bytemode, sizeflag);
16423 }
16424
16425 static void
16426 OP_XMM_Vex (int bytemode, int sizeflag)
16427 {
16428   if (modrm.mod != 3)
16429     {
16430       if (vex.register_specifier != 0)
16431         BadOp ();
16432       need_vex_reg = 0;
16433     }
16434   OP_XMM (bytemode, sizeflag);
16435 }
16436
16437 static void
16438 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16439 {
16440   switch (vex.length)
16441     {
16442     case 128:
16443       mnemonicendp = stpcpy (obuf, "vzeroupper");
16444       break;
16445     case 256:
16446       mnemonicendp = stpcpy (obuf, "vzeroall");
16447       break;
16448     default:
16449       abort ();
16450     }
16451 }
16452
16453 static struct op vex_cmp_op[] =
16454 {
16455   { STRING_COMMA_LEN ("eq") },
16456   { STRING_COMMA_LEN ("lt") },
16457   { STRING_COMMA_LEN ("le") },
16458   { STRING_COMMA_LEN ("unord") },
16459   { STRING_COMMA_LEN ("neq") },
16460   { STRING_COMMA_LEN ("nlt") },
16461   { STRING_COMMA_LEN ("nle") },
16462   { STRING_COMMA_LEN ("ord") },
16463   { STRING_COMMA_LEN ("eq_uq") },
16464   { STRING_COMMA_LEN ("nge") },
16465   { STRING_COMMA_LEN ("ngt") },
16466   { STRING_COMMA_LEN ("false") },
16467   { STRING_COMMA_LEN ("neq_oq") },
16468   { STRING_COMMA_LEN ("ge") },
16469   { STRING_COMMA_LEN ("gt") },
16470   { STRING_COMMA_LEN ("true") },
16471   { STRING_COMMA_LEN ("eq_os") },
16472   { STRING_COMMA_LEN ("lt_oq") },
16473   { STRING_COMMA_LEN ("le_oq") },
16474   { STRING_COMMA_LEN ("unord_s") },
16475   { STRING_COMMA_LEN ("neq_us") },
16476   { STRING_COMMA_LEN ("nlt_uq") },
16477   { STRING_COMMA_LEN ("nle_uq") },
16478   { STRING_COMMA_LEN ("ord_s") },
16479   { STRING_COMMA_LEN ("eq_us") },
16480   { STRING_COMMA_LEN ("nge_uq") },
16481   { STRING_COMMA_LEN ("ngt_uq") },
16482   { STRING_COMMA_LEN ("false_os") },
16483   { STRING_COMMA_LEN ("neq_os") },
16484   { STRING_COMMA_LEN ("ge_oq") },
16485   { STRING_COMMA_LEN ("gt_oq") },
16486   { STRING_COMMA_LEN ("true_us") },
16487 };
16488
16489 static void
16490 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16491 {
16492   unsigned int cmp_type;
16493
16494   FETCH_DATA (the_info, codep + 1);
16495   cmp_type = *codep++ & 0xff;
16496   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
16497     {
16498       char suffix [3];
16499       char *p = mnemonicendp - 2;
16500       suffix[0] = p[0];
16501       suffix[1] = p[1];
16502       suffix[2] = '\0';
16503       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
16504       mnemonicendp += vex_cmp_op[cmp_type].len;
16505     }
16506   else
16507     {
16508       /* We have a reserved extension byte.  Output it directly.  */
16509       scratchbuf[0] = '$';
16510       print_operand_value (scratchbuf + 1, 1, cmp_type);
16511       oappend_maybe_intel (scratchbuf);
16512       scratchbuf[0] = '\0';
16513     }
16514 }
16515
16516 static void
16517 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
16518              int sizeflag ATTRIBUTE_UNUSED)
16519 {
16520   unsigned int cmp_type;
16521
16522   if (!vex.evex)
16523     abort ();
16524
16525   FETCH_DATA (the_info, codep + 1);
16526   cmp_type = *codep++ & 0xff;
16527   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
16528      If it's the case, print suffix, otherwise - print the immediate.  */
16529   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
16530       && cmp_type != 3
16531       && cmp_type != 7)
16532     {
16533       char suffix [3];
16534       char *p = mnemonicendp - 2;
16535
16536       /* vpcmp* can have both one- and two-lettered suffix.  */
16537       if (p[0] == 'p')
16538         {
16539           p++;
16540           suffix[0] = p[0];
16541           suffix[1] = '\0';
16542         }
16543       else
16544         {
16545           suffix[0] = p[0];
16546           suffix[1] = p[1];
16547           suffix[2] = '\0';
16548         }
16549
16550       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16551       mnemonicendp += simd_cmp_op[cmp_type].len;
16552     }
16553   else
16554     {
16555       /* We have a reserved extension byte.  Output it directly.  */
16556       scratchbuf[0] = '$';
16557       print_operand_value (scratchbuf + 1, 1, cmp_type);
16558       oappend_maybe_intel (scratchbuf);
16559       scratchbuf[0] = '\0';
16560     }
16561 }
16562
16563 static const struct op pclmul_op[] =
16564 {
16565   { STRING_COMMA_LEN ("lql") },
16566   { STRING_COMMA_LEN ("hql") },
16567   { STRING_COMMA_LEN ("lqh") },
16568   { STRING_COMMA_LEN ("hqh") }
16569 };
16570
16571 static void
16572 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
16573               int sizeflag ATTRIBUTE_UNUSED)
16574 {
16575   unsigned int pclmul_type;
16576
16577   FETCH_DATA (the_info, codep + 1);
16578   pclmul_type = *codep++ & 0xff;
16579   switch (pclmul_type)
16580     {
16581     case 0x10:
16582       pclmul_type = 2;
16583       break;
16584     case 0x11:
16585       pclmul_type = 3;
16586       break;
16587     default:
16588       break;
16589     }
16590   if (pclmul_type < ARRAY_SIZE (pclmul_op))
16591     {
16592       char suffix [4];
16593       char *p = mnemonicendp - 3;
16594       suffix[0] = p[0];
16595       suffix[1] = p[1];
16596       suffix[2] = p[2];
16597       suffix[3] = '\0';
16598       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
16599       mnemonicendp += pclmul_op[pclmul_type].len;
16600     }
16601   else
16602     {
16603       /* We have a reserved extension byte.  Output it directly.  */
16604       scratchbuf[0] = '$';
16605       print_operand_value (scratchbuf + 1, 1, pclmul_type);
16606       oappend_maybe_intel (scratchbuf);
16607       scratchbuf[0] = '\0';
16608     }
16609 }
16610
16611 static void
16612 MOVBE_Fixup (int bytemode, int sizeflag)
16613 {
16614   /* Add proper suffix to "movbe".  */
16615   char *p = mnemonicendp;
16616
16617   switch (bytemode)
16618     {
16619     case v_mode:
16620       if (intel_syntax)
16621         goto skip;
16622
16623       USED_REX (REX_W);
16624       if (sizeflag & SUFFIX_ALWAYS)
16625         {
16626           if (rex & REX_W)
16627             *p++ = 'q';
16628           else
16629             {
16630               if (sizeflag & DFLAG)
16631                 *p++ = 'l';
16632               else
16633                 *p++ = 'w';
16634               used_prefixes |= (prefixes & PREFIX_DATA);
16635             }
16636         }
16637       break;
16638     default:
16639       oappend (INTERNAL_DISASSEMBLER_ERROR);
16640       break;
16641     }
16642   mnemonicendp = p;
16643   *p = '\0';
16644
16645 skip:
16646   OP_M (bytemode, sizeflag);
16647 }
16648
16649 static void
16650 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16651 {
16652   int reg;
16653   const char **names;
16654
16655   /* Skip mod/rm byte.  */
16656   MODRM_CHECK;
16657   codep++;
16658
16659   if (vex.w)
16660     names = names64;
16661   else
16662     names = names32;
16663
16664   reg = modrm.rm;
16665   USED_REX (REX_B);
16666   if (rex & REX_B)
16667     reg += 8;
16668
16669   oappend (names[reg]);
16670 }
16671
16672 static void
16673 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16674 {
16675   const char **names;
16676
16677   if (vex.w)
16678     names = names64;
16679   else
16680     names = names32;
16681
16682   oappend (names[vex.register_specifier]);
16683 }
16684
16685 static void
16686 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16687 {
16688   if (!vex.evex
16689       || bytemode != mask_mode)
16690     abort ();
16691
16692   USED_REX (REX_R);
16693   if ((rex & REX_R) != 0 || !vex.r)
16694     {
16695       BadOp ();
16696       return;
16697     }
16698
16699   oappend (names_mask [modrm.reg]);
16700 }
16701
16702 static void
16703 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16704 {
16705   if (!vex.evex
16706       || (bytemode != evex_rounding_mode
16707           && bytemode != evex_sae_mode))
16708     abort ();
16709   if (modrm.mod == 3 && vex.b)
16710     switch (bytemode)
16711       {
16712       case evex_rounding_mode:
16713         oappend (names_rounding[vex.ll]);
16714         break;
16715       case evex_sae_mode:
16716         oappend ("{sae}");
16717         break;
16718       default:
16719         break;
16720       }
16721 }