opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2016 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "dis-asm.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40
  41 #include <setjmp.h>
  42
  43 static int print_insn (bfd_vma, disassemble_info *);
  44 static void dofloat (int);
  45 static void OP_ST (int, int);
  46 static void OP_STi (int, int);
  47 static int putop (const char *, int);
  48 static void oappend (const char *);
  49 static void append_seg (void);
  50 static void OP_indirE (int, int);
  51 static void print_operand_value (char *, int, bfd_vma);
  52 static void OP_E_register (int, int);
  53 static void OP_E_memory (int, int);
  54 static void print_displacement (char *, bfd_vma);
  55 static void OP_E (int, int);
  56 static void OP_G (int, int);
  57 static bfd_vma get64 (void);
  58 static bfd_signed_vma get32 (void);
  59 static bfd_signed_vma get32s (void);
  60 static int get16 (void);
  61 static void set_op (bfd_vma, int);
  62 static void OP_Skip_MODRM (int, int);
  63 static void OP_REG (int, int);
  64 static void OP_IMREG (int, int);
  65 static void OP_I (int, int);
  66 static void OP_I64 (int, int);
  67 static void OP_sI (int, int);
  68 static void OP_J (int, int);
  69 static void OP_SEG (int, int);
  70 static void OP_DIR (int, int);
  71 static void OP_OFF (int, int);
  72 static void OP_OFF64 (int, int);
  73 static void ptr_reg (int, int);
  74 static void OP_ESreg (int, int);
  75 static void OP_DSreg (int, int);
  76 static void OP_C (int, int);
  77 static void OP_D (int, int);
  78 static void OP_T (int, int);
  79 static void OP_R (int, int);
  80 static void OP_MMX (int, int);
  81 static void OP_XMM (int, int);
  82 static void OP_EM (int, int);
  83 static void OP_EX (int, int);
  84 static void OP_EMC (int,int);
  85 static void OP_MXC (int,int);
  86 static void OP_MS (int, int);
  87 static void OP_XS (int, int);
  88 static void OP_M (int, int);
  89 static void OP_VEX (int, int);
  90 static void OP_EX_Vex (int, int);
  91 static void OP_EX_VexW (int, int);
  92 static void OP_EX_VexImmW (int, int);
  93 static void OP_XMM_Vex (int, int);
  94 static void OP_XMM_VexW (int, int);
  95 static void OP_Rounding (int, int);
  96 static void OP_REG_VexI4 (int, int);
  97 static void PCLMUL_Fixup (int, int);
  98 static void VEXI4_Fixup (int, int);
  99 static void VZERO_Fixup (int, int);
 100 static void VCMP_Fixup (int, int);
 101 static void VPCMP_Fixup (int, int);
 102 static void OP_0f07 (int, int);
 103 static void OP_Monitor (int, int);
 104 static void OP_Mwait (int, int);
 105 static void OP_Mwaitx (int, int);
 106 static void NOP_Fixup1 (int, int);
 107 static void NOP_Fixup2 (int, int);
 108 static void OP_3DNowSuffix (int, int);
 109 static void CMP_Fixup (int, int);
 110 static void BadOp (void);
 111 static void REP_Fixup (int, int);
 112 static void BND_Fixup (int, int);
 113 static void HLE_Fixup1 (int, int);
 114 static void HLE_Fixup2 (int, int);
 115 static void HLE_Fixup3 (int, int);
 116 static void CMPXCHG8B_Fixup (int, int);
 117 static void XMM_Fixup (int, int);
 118 static void CRC32_Fixup (int, int);
 119 static void FXSAVE_Fixup (int, int);
 120 static void OP_LWPCB_E (int, int);
 121 static void OP_LWP_E (int, int);
 122 static void OP_Vex_2src_1 (int, int);
 123 static void OP_Vex_2src_2 (int, int);
 124
 125 static void MOVBE_Fixup (int, int);
 126
 127 static void OP_Mask (int, int);
 128
 129 struct dis_private {
 130   /* Points to first byte not fetched.  */
 131   bfd_byte *max_fetched;
 132   bfd_byte the_buffer[MAX_MNEM_SIZE];
 133   bfd_vma insn_start;
 134   int orig_sizeflag;
 135   OPCODES_SIGJMP_BUF bailout;
 136 };
 137
 138 enum address_mode
 139 {
 140   mode_16bit,
 141   mode_32bit,
 142   mode_64bit
 143 };
 144
 145 enum address_mode address_mode;
 146
 147 /* Flags for the prefixes for the current instruction.  See below.  */
 148 static int prefixes;
 149
 150 /* REX prefix the current instruction.  See below.  */
 151 static int rex;
 152 /* Bits of REX we've already used.  */
 153 static int rex_used;
 154 /* REX bits in original REX prefix ignored.  */
 155 static int rex_ignored;
 156 /* Mark parts used in the REX prefix.  When we are testing for
 157    empty prefix (for 8bit register REX extension), just mask it
 158    out.  Otherwise test for REX bit is excuse for existence of REX
 159    only in case value is nonzero.  */
 160 #define USED_REX(value)                                 \
 161   {                                                     \
 162     if (value)                                          \
 163       {                                                 \
 164         if ((rex & value))                              \
 165           rex_used |= (value) | REX_OPCODE;             \
 166       }                                                 \
 167     else                                                \
 168       rex_used |= REX_OPCODE;                           \
 169   }
 170
 171 /* Flags for prefixes which we somehow handled when printing the
 172    current instruction.  */
 173 static int used_prefixes;
 174
 175 /* Flags stored in PREFIXES.  */
 176 #define PREFIX_REPZ 1
 177 #define PREFIX_REPNZ 2
 178 #define PREFIX_LOCK 4
 179 #define PREFIX_CS 8
 180 #define PREFIX_SS 0x10
 181 #define PREFIX_DS 0x20
 182 #define PREFIX_ES 0x40
 183 #define PREFIX_FS 0x80
 184 #define PREFIX_GS 0x100
 185 #define PREFIX_DATA 0x200
 186 #define PREFIX_ADDR 0x400
 187 #define PREFIX_FWAIT 0x800
 188
 189 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 190    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 191    on error.  */
 192 #define FETCH_DATA(info, addr) \
 193   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 194    ? 1 : fetch_data ((info), (addr)))
 195
 196 static int
 197 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 198 {
 199   int status;
 200   struct dis_private *priv = (struct dis_private *) info->private_data;
 201   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 202
 203   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 204     status = (*info->read_memory_func) (start,
 205                                         priv->max_fetched,
 206                                         addr - priv->max_fetched,
 207                                         info);
 208   else
 209     status = -1;
 210   if (status != 0)
 211     {
 212       /* If we did manage to read at least one byte, then
 213          print_insn_i386 will do something sensible.  Otherwise, print
 214          an error.  We do that here because this is where we know
 215          STATUS.  */
 216       if (priv->max_fetched == priv->the_buffer)
 217         (*info->memory_error_func) (status, start, info);
 218       OPCODES_SIGLONGJMP (priv->bailout, 1);
 219     }
 220   else
 221     priv->max_fetched = addr;
 222   return 1;
 223 }
 224
 225 /* Possible values for prefix requirement.  */
 226 #define PREFIX_IGNORED_SHIFT    16
 227 #define PREFIX_IGNORED_REPZ     (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
 228 #define PREFIX_IGNORED_REPNZ    (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
 229 #define PREFIX_IGNORED_DATA     (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
 230 #define PREFIX_IGNORED_ADDR     (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
 231 #define PREFIX_IGNORED_LOCK     (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
 232
 233 /* Opcode prefixes.  */
 234 #define PREFIX_OPCODE           (PREFIX_REPZ \
 235                                  | PREFIX_REPNZ \
 236                                  | PREFIX_DATA)
 237
 238 /* Prefixes ignored.  */
 239 #define PREFIX_IGNORED          (PREFIX_IGNORED_REPZ \
 240                                  | PREFIX_IGNORED_REPNZ \
 241                                  | PREFIX_IGNORED_DATA)
 242
 243 #define XX { NULL, 0 }
 244 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
 245
 246 #define Eb { OP_E, b_mode }
 247 #define Ebnd { OP_E, bnd_mode }
 248 #define EbS { OP_E, b_swap_mode }
 249 #define Ev { OP_E, v_mode }
 250 #define Ev_bnd { OP_E, v_bnd_mode }
 251 #define EvS { OP_E, v_swap_mode }
 252 #define Ed { OP_E, d_mode }
 253 #define Edq { OP_E, dq_mode }
 254 #define Edqw { OP_E, dqw_mode }
 255 #define EdqwS { OP_E, dqw_swap_mode }
 256 #define Edqb { OP_E, dqb_mode }
 257 #define Edb { OP_E, db_mode }
 258 #define Edw { OP_E, dw_mode }
 259 #define Edqd { OP_E, dqd_mode }
 260 #define Eq { OP_E, q_mode }
 261 #define indirEv { OP_indirE, indir_v_mode }
 262 #define indirEp { OP_indirE, f_mode }
 263 #define stackEv { OP_E, stack_v_mode }
 264 #define Em { OP_E, m_mode }
 265 #define Ew { OP_E, w_mode }
 266 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 267 #define Ma { OP_M, a_mode }
 268 #define Mb { OP_M, b_mode }
 269 #define Md { OP_M, d_mode }
 270 #define Mo { OP_M, o_mode }
 271 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 272 #define Mq { OP_M, q_mode }
 273 #define Mx { OP_M, x_mode }
 274 #define Mxmm { OP_M, xmm_mode }
 275 #define Gb { OP_G, b_mode }
 276 #define Gbnd { OP_G, bnd_mode }
 277 #define Gv { OP_G, v_mode }
 278 #define Gd { OP_G, d_mode }
 279 #define Gdq { OP_G, dq_mode }
 280 #define Gm { OP_G, m_mode }
 281 #define Gw { OP_G, w_mode }
 282 #define Rd { OP_R, d_mode }
 283 #define Rdq { OP_R, dq_mode }
 284 #define Rm { OP_R, m_mode }
 285 #define Ib { OP_I, b_mode }
 286 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 287 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 288 #define Iv { OP_I, v_mode }
 289 #define sIv { OP_sI, v_mode }
 290 #define Iq { OP_I, q_mode }
 291 #define Iv64 { OP_I64, v_mode }
 292 #define Iw { OP_I, w_mode }
 293 #define I1 { OP_I, const_1_mode }
 294 #define Jb { OP_J, b_mode }
 295 #define Jv { OP_J, v_mode }
 296 #define Cm { OP_C, m_mode }
 297 #define Dm { OP_D, m_mode }
 298 #define Td { OP_T, d_mode }
 299 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 300
 301 #define RMeAX { OP_REG, eAX_reg }
 302 #define RMeBX { OP_REG, eBX_reg }
 303 #define RMeCX { OP_REG, eCX_reg }
 304 #define RMeDX { OP_REG, eDX_reg }
 305 #define RMeSP { OP_REG, eSP_reg }
 306 #define RMeBP { OP_REG, eBP_reg }
 307 #define RMeSI { OP_REG, eSI_reg }
 308 #define RMeDI { OP_REG, eDI_reg }
 309 #define RMrAX { OP_REG, rAX_reg }
 310 #define RMrBX { OP_REG, rBX_reg }
 311 #define RMrCX { OP_REG, rCX_reg }
 312 #define RMrDX { OP_REG, rDX_reg }
 313 #define RMrSP { OP_REG, rSP_reg }
 314 #define RMrBP { OP_REG, rBP_reg }
 315 #define RMrSI { OP_REG, rSI_reg }
 316 #define RMrDI { OP_REG, rDI_reg }
 317 #define RMAL { OP_REG, al_reg }
 318 #define RMCL { OP_REG, cl_reg }
 319 #define RMDL { OP_REG, dl_reg }
 320 #define RMBL { OP_REG, bl_reg }
 321 #define RMAH { OP_REG, ah_reg }
 322 #define RMCH { OP_REG, ch_reg }
 323 #define RMDH { OP_REG, dh_reg }
 324 #define RMBH { OP_REG, bh_reg }
 325 #define RMAX { OP_REG, ax_reg }
 326 #define RMDX { OP_REG, dx_reg }
 327
 328 #define eAX { OP_IMREG, eAX_reg }
 329 #define eBX { OP_IMREG, eBX_reg }
 330 #define eCX { OP_IMREG, eCX_reg }
 331 #define eDX { OP_IMREG, eDX_reg }
 332 #define eSP { OP_IMREG, eSP_reg }
 333 #define eBP { OP_IMREG, eBP_reg }
 334 #define eSI { OP_IMREG, eSI_reg }
 335 #define eDI { OP_IMREG, eDI_reg }
 336 #define AL { OP_IMREG, al_reg }
 337 #define CL { OP_IMREG, cl_reg }
 338 #define DL { OP_IMREG, dl_reg }
 339 #define BL { OP_IMREG, bl_reg }
 340 #define AH { OP_IMREG, ah_reg }
 341 #define CH { OP_IMREG, ch_reg }
 342 #define DH { OP_IMREG, dh_reg }
 343 #define BH { OP_IMREG, bh_reg }
 344 #define AX { OP_IMREG, ax_reg }
 345 #define DX { OP_IMREG, dx_reg }
 346 #define zAX { OP_IMREG, z_mode_ax_reg }
 347 #define indirDX { OP_IMREG, indir_dx_reg }
 348
 349 #define Sw { OP_SEG, w_mode }
 350 #define Sv { OP_SEG, v_mode }
 351 #define Ap { OP_DIR, 0 }
 352 #define Ob { OP_OFF64, b_mode }
 353 #define Ov { OP_OFF64, v_mode }
 354 #define Xb { OP_DSreg, eSI_reg }
 355 #define Xv { OP_DSreg, eSI_reg }
 356 #define Xz { OP_DSreg, eSI_reg }
 357 #define Yb { OP_ESreg, eDI_reg }
 358 #define Yv { OP_ESreg, eDI_reg }
 359 #define DSBX { OP_DSreg, eBX_reg }
 360
 361 #define es { OP_REG, es_reg }
 362 #define ss { OP_REG, ss_reg }
 363 #define cs { OP_REG, cs_reg }
 364 #define ds { OP_REG, ds_reg }
 365 #define fs { OP_REG, fs_reg }
 366 #define gs { OP_REG, gs_reg }
 367
 368 #define MX { OP_MMX, 0 }
 369 #define XM { OP_XMM, 0 }
 370 #define XMScalar { OP_XMM, scalar_mode }
 371 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 372 #define XMM { OP_XMM, xmm_mode }
 373 #define XMxmmq { OP_XMM, xmmq_mode }
 374 #define EM { OP_EM, v_mode }
 375 #define EMS { OP_EM, v_swap_mode }
 376 #define EMd { OP_EM, d_mode }
 377 #define EMx { OP_EM, x_mode }
 378 #define EXw { OP_EX, w_mode }
 379 #define EXd { OP_EX, d_mode }
 380 #define EXdScalar { OP_EX, d_scalar_mode }
 381 #define EXdS { OP_EX, d_swap_mode }
 382 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
 383 #define EXq { OP_EX, q_mode }
 384 #define EXqScalar { OP_EX, q_scalar_mode }
 385 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
 386 #define EXqS { OP_EX, q_swap_mode }
 387 #define EXx { OP_EX, x_mode }
 388 #define EXxS { OP_EX, x_swap_mode }
 389 #define EXxmm { OP_EX, xmm_mode }
 390 #define EXymm { OP_EX, ymm_mode }
 391 #define EXxmmq { OP_EX, xmmq_mode }
 392 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 393 #define EXxmm_mb { OP_EX, xmm_mb_mode }
 394 #define EXxmm_mw { OP_EX, xmm_mw_mode }
 395 #define EXxmm_md { OP_EX, xmm_md_mode }
 396 #define EXxmm_mq { OP_EX, xmm_mq_mode }
 397 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
 398 #define EXxmmdw { OP_EX, xmmdw_mode }
 399 #define EXxmmqd { OP_EX, xmmqd_mode }
 400 #define EXymmq { OP_EX, ymmq_mode }
 401 #define EXVexWdq { OP_EX, vex_w_dq_mode }
 402 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 403 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 404 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 405 #define MS { OP_MS, v_mode }
 406 #define XS { OP_XS, v_mode }
 407 #define EMCq { OP_EMC, q_mode }
 408 #define MXC { OP_MXC, 0 }
 409 #define OPSUF { OP_3DNowSuffix, 0 }
 410 #define CMP { CMP_Fixup, 0 }
 411 #define XMM0 { XMM_Fixup, 0 }
 412 #define FXSAVE { FXSAVE_Fixup, 0 }
 413 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
 414 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
 415
 416 #define Vex { OP_VEX, vex_mode }
 417 #define VexScalar { OP_VEX, vex_scalar_mode }
 418 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 419 #define Vex128 { OP_VEX, vex128_mode }
 420 #define Vex256 { OP_VEX, vex256_mode }
 421 #define VexGdq { OP_VEX, dq_mode }
 422 #define VexI4 { VEXI4_Fixup, 0}
 423 #define EXdVex { OP_EX_Vex, d_mode }
 424 #define EXdVexS { OP_EX_Vex, d_swap_mode }
 425 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
 426 #define EXqVex { OP_EX_Vex, q_mode }
 427 #define EXqVexS { OP_EX_Vex, q_swap_mode }
 428 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
 429 #define EXVexW { OP_EX_VexW, x_mode }
 430 #define EXdVexW { OP_EX_VexW, d_mode }
 431 #define EXqVexW { OP_EX_VexW, q_mode }
 432 #define EXVexImmW { OP_EX_VexImmW, x_mode }
 433 #define XMVex { OP_XMM_Vex, 0 }
 434 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
 435 #define XMVexW { OP_XMM_VexW, 0 }
 436 #define XMVexI4 { OP_REG_VexI4, x_mode }
 437 #define PCLMUL { PCLMUL_Fixup, 0 }
 438 #define VZERO { VZERO_Fixup, 0 }
 439 #define VCMP { VCMP_Fixup, 0 }
 440 #define VPCMP { VPCMP_Fixup, 0 }
 441
 442 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 443 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 444
 445 #define XMask { OP_Mask, mask_mode }
 446 #define MaskG { OP_G, mask_mode }
 447 #define MaskE { OP_E, mask_mode }
 448 #define MaskBDE { OP_E, mask_bd_mode }
 449 #define MaskR { OP_R, mask_mode }
 450 #define MaskVex { OP_VEX, mask_mode }
 451
 452 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 453 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
 454 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 455 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
 456
 457 /* Used handle "rep" prefix for string instructions.  */
 458 #define Xbr { REP_Fixup, eSI_reg }
 459 #define Xvr { REP_Fixup, eSI_reg }
 460 #define Ybr { REP_Fixup, eDI_reg }
 461 #define Yvr { REP_Fixup, eDI_reg }
 462 #define Yzr { REP_Fixup, eDI_reg }
 463 #define indirDXr { REP_Fixup, indir_dx_reg }
 464 #define ALr { REP_Fixup, al_reg }
 465 #define eAXr { REP_Fixup, eAX_reg }
 466
 467 /* Used handle HLE prefix for lockable instructions.  */
 468 #define Ebh1 { HLE_Fixup1, b_mode }
 469 #define Evh1 { HLE_Fixup1, v_mode }
 470 #define Ebh2 { HLE_Fixup2, b_mode }
 471 #define Evh2 { HLE_Fixup2, v_mode }
 472 #define Ebh3 { HLE_Fixup3, b_mode }
 473 #define Evh3 { HLE_Fixup3, v_mode }
 474
 475 #define BND { BND_Fixup, 0 }
 476
 477 #define cond_jump_flag { NULL, cond_jump_mode }
 478 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 479
 480 /* bits in sizeflag */
 481 #define SUFFIX_ALWAYS 4
 482 #define AFLAG 2
 483 #define DFLAG 1
 484
 485 enum
 486 {
 487   /* byte operand */
 488   b_mode = 1,
 489   /* byte operand with operand swapped */
 490   b_swap_mode,
 491   /* byte operand, sign extend like 'T' suffix */
 492   b_T_mode,
 493   /* operand size depends on prefixes */
 494   v_mode,
 495   /* operand size depends on prefixes with operand swapped */
 496   v_swap_mode,
 497   /* word operand */
 498   w_mode,
 499   /* double word operand  */
 500   d_mode,
 501   /* double word operand with operand swapped */
 502   d_swap_mode,
 503   /* quad word operand */
 504   q_mode,
 505   /* quad word operand with operand swapped */
 506   q_swap_mode,
 507   /* ten-byte operand */
 508   t_mode,
 509   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 510      broadcast enabled.  */
 511   x_mode,
 512   /* Similar to x_mode, but with different EVEX mem shifts.  */
 513   evex_x_gscat_mode,
 514   /* Similar to x_mode, but with disabled broadcast.  */
 515   evex_x_nobcst_mode,
 516   /* Similar to x_mode, but with operands swapped and disabled broadcast
 517      in EVEX.  */
 518   x_swap_mode,
 519   /* 16-byte XMM operand */
 520   xmm_mode,
 521   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 522      memory operand (depending on vector length).  Broadcast isn't
 523      allowed.  */
 524   xmmq_mode,
 525   /* Same as xmmq_mode, but broadcast is allowed.  */
 526   evex_half_bcst_xmmq_mode,
 527   /* XMM register or byte memory operand */
 528   xmm_mb_mode,
 529   /* XMM register or word memory operand */
 530   xmm_mw_mode,
 531   /* XMM register or double word memory operand */
 532   xmm_md_mode,
 533   /* XMM register or quad word memory operand */
 534   xmm_mq_mode,
 535   /* XMM register or double/quad word memory operand, depending on
 536      VEX.W.  */
 537   xmm_mdq_mode,
 538   /* 16-byte XMM, word, double word or quad word operand.  */
 539   xmmdw_mode,
 540   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 541   xmmqd_mode,
 542   /* 32-byte YMM operand */
 543   ymm_mode,
 544   /* quad word, ymmword or zmmword memory operand.  */
 545   ymmq_mode,
 546   /* 32-byte YMM or 16-byte word operand */
 547   ymmxmm_mode,
 548   /* d_mode in 32bit, q_mode in 64bit mode.  */
 549   m_mode,
 550   /* pair of v_mode operands */
 551   a_mode,
 552   cond_jump_mode,
 553   loop_jcxz_mode,
 554   v_bnd_mode,
 555   /* operand size depends on REX prefixes.  */
 556   dq_mode,
 557   /* registers like dq_mode, memory like w_mode.  */
 558   dqw_mode,
 559   dqw_swap_mode,
 560   bnd_mode,
 561   /* 4- or 6-byte pointer operand */
 562   f_mode,
 563   const_1_mode,
 564   /* v_mode for indirect branch opcodes.  */
 565   indir_v_mode,
 566   /* v_mode for stack-related opcodes.  */
 567   stack_v_mode,
 568   /* non-quad operand size depends on prefixes */
 569   z_mode,
 570   /* 16-byte operand */
 571   o_mode,
 572   /* registers like dq_mode, memory like b_mode.  */
 573   dqb_mode,
 574   /* registers like d_mode, memory like b_mode.  */
 575   db_mode,
 576   /* registers like d_mode, memory like w_mode.  */
 577   dw_mode,
 578   /* registers like dq_mode, memory like d_mode.  */
 579   dqd_mode,
 580   /* normal vex mode */
 581   vex_mode,
 582   /* 128bit vex mode */
 583   vex128_mode,
 584   /* 256bit vex mode */
 585   vex256_mode,
 586   /* operand size depends on the VEX.W bit.  */
 587   vex_w_dq_mode,
 588
 589   /* Similar to vex_w_dq_mode, with VSIB dword indices.  */
 590   vex_vsib_d_w_dq_mode,
 591   /* Similar to vex_vsib_d_w_dq_mode, with smaller memory.  */
 592   vex_vsib_d_w_d_mode,
 593   /* Similar to vex_w_dq_mode, with VSIB qword indices.  */
 594   vex_vsib_q_w_dq_mode,
 595   /* Similar to vex_vsib_q_w_dq_mode, with smaller memory.  */
 596   vex_vsib_q_w_d_mode,
 597
 598   /* scalar, ignore vector length.  */
 599   scalar_mode,
 600   /* like d_mode, ignore vector length.  */
 601   d_scalar_mode,
 602   /* like d_swap_mode, ignore vector length.  */
 603   d_scalar_swap_mode,
 604   /* like q_mode, ignore vector length.  */
 605   q_scalar_mode,
 606   /* like q_swap_mode, ignore vector length.  */
 607   q_scalar_swap_mode,
 608   /* like vex_mode, ignore vector length.  */
 609   vex_scalar_mode,
 610   /* like vex_w_dq_mode, ignore vector length.  */
 611   vex_scalar_w_dq_mode,
 612
 613   /* Static rounding.  */
 614   evex_rounding_mode,
 615   /* Supress all exceptions.  */
 616   evex_sae_mode,
 617
 618   /* Mask register operand.  */
 619   mask_mode,
 620   /* Mask register operand.  */
 621   mask_bd_mode,
 622
 623   es_reg,
 624   cs_reg,
 625   ss_reg,
 626   ds_reg,
 627   fs_reg,
 628   gs_reg,
 629
 630   eAX_reg,
 631   eCX_reg,
 632   eDX_reg,
 633   eBX_reg,
 634   eSP_reg,
 635   eBP_reg,
 636   eSI_reg,
 637   eDI_reg,
 638
 639   al_reg,
 640   cl_reg,
 641   dl_reg,
 642   bl_reg,
 643   ah_reg,
 644   ch_reg,
 645   dh_reg,
 646   bh_reg,
 647
 648   ax_reg,
 649   cx_reg,
 650   dx_reg,
 651   bx_reg,
 652   sp_reg,
 653   bp_reg,
 654   si_reg,
 655   di_reg,
 656
 657   rAX_reg,
 658   rCX_reg,
 659   rDX_reg,
 660   rBX_reg,
 661   rSP_reg,
 662   rBP_reg,
 663   rSI_reg,
 664   rDI_reg,
 665
 666   z_mode_ax_reg,
 667   indir_dx_reg
 668 };
 669
 670 enum
 671 {
 672   FLOATCODE = 1,
 673   USE_REG_TABLE,
 674   USE_MOD_TABLE,
 675   USE_RM_TABLE,
 676   USE_PREFIX_TABLE,
 677   USE_X86_64_TABLE,
 678   USE_3BYTE_TABLE,
 679   USE_XOP_8F_TABLE,
 680   USE_VEX_C4_TABLE,
 681   USE_VEX_C5_TABLE,
 682   USE_VEX_LEN_TABLE,
 683   USE_VEX_W_TABLE,
 684   USE_EVEX_TABLE
 685 };
 686
 687 #define FLOAT                   NULL, { { NULL, FLOATCODE } }, 0
 688
 689 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }, 0
 690 #define DIS386_PREFIX(T, I, P)          NULL, { { NULL, (T)}, { NULL,  (I) } }, P
 691 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 692 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 693 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 694 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 695 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 696 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 697 #define THREE_BYTE_TABLE_PREFIX(I, P)   DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
 698 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 699 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 700 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 701 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 702 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 703 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 704
 705 enum
 706 {
 707   REG_80 = 0,
 708   REG_81,
 709   REG_82,
 710   REG_8F,
 711   REG_C0,
 712   REG_C1,
 713   REG_C6,
 714   REG_C7,
 715   REG_D0,
 716   REG_D1,
 717   REG_D2,
 718   REG_D3,
 719   REG_F6,
 720   REG_F7,
 721   REG_FE,
 722   REG_FF,
 723   REG_0F00,
 724   REG_0F01,
 725   REG_0F0D,
 726   REG_0F18,
 727   REG_0F71,
 728   REG_0F72,
 729   REG_0F73,
 730   REG_0FA6,
 731   REG_0FA7,
 732   REG_0FAE,
 733   REG_0FBA,
 734   REG_0FC7,
 735   REG_VEX_0F71,
 736   REG_VEX_0F72,
 737   REG_VEX_0F73,
 738   REG_VEX_0FAE,
 739   REG_VEX_0F38F3,
 740   REG_XOP_LWPCB,
 741   REG_XOP_LWP,
 742   REG_XOP_TBM_01,
 743   REG_XOP_TBM_02,
 744
 745   REG_EVEX_0F71,
 746   REG_EVEX_0F72,
 747   REG_EVEX_0F73,
 748   REG_EVEX_0F38C6,
 749   REG_EVEX_0F38C7
 750 };
 751
 752 enum
 753 {
 754   MOD_8D = 0,
 755   MOD_C6_REG_7,
 756   MOD_C7_REG_7,
 757   MOD_FF_REG_3,
 758   MOD_FF_REG_5,
 759   MOD_0F01_REG_0,
 760   MOD_0F01_REG_1,
 761   MOD_0F01_REG_2,
 762   MOD_0F01_REG_3,
 763   MOD_0F01_REG_5,
 764   MOD_0F01_REG_7,
 765   MOD_0F12_PREFIX_0,
 766   MOD_0F13,
 767   MOD_0F16_PREFIX_0,
 768   MOD_0F17,
 769   MOD_0F18_REG_0,
 770   MOD_0F18_REG_1,
 771   MOD_0F18_REG_2,
 772   MOD_0F18_REG_3,
 773   MOD_0F18_REG_4,
 774   MOD_0F18_REG_5,
 775   MOD_0F18_REG_6,
 776   MOD_0F18_REG_7,
 777   MOD_0F1A_PREFIX_0,
 778   MOD_0F1B_PREFIX_0,
 779   MOD_0F1B_PREFIX_1,
 780   MOD_0F24,
 781   MOD_0F26,
 782   MOD_0F2B_PREFIX_0,
 783   MOD_0F2B_PREFIX_1,
 784   MOD_0F2B_PREFIX_2,
 785   MOD_0F2B_PREFIX_3,
 786   MOD_0F51,
 787   MOD_0F71_REG_2,
 788   MOD_0F71_REG_4,
 789   MOD_0F71_REG_6,
 790   MOD_0F72_REG_2,
 791   MOD_0F72_REG_4,
 792   MOD_0F72_REG_6,
 793   MOD_0F73_REG_2,
 794   MOD_0F73_REG_3,
 795   MOD_0F73_REG_6,
 796   MOD_0F73_REG_7,
 797   MOD_0FAE_REG_0,
 798   MOD_0FAE_REG_1,
 799   MOD_0FAE_REG_2,
 800   MOD_0FAE_REG_3,
 801   MOD_0FAE_REG_4,
 802   MOD_0FAE_REG_5,
 803   MOD_0FAE_REG_6,
 804   MOD_0FAE_REG_7,
 805   MOD_0FB2,
 806   MOD_0FB4,
 807   MOD_0FB5,
 808   MOD_0FC3,
 809   MOD_0FC7_REG_3,
 810   MOD_0FC7_REG_4,
 811   MOD_0FC7_REG_5,
 812   MOD_0FC7_REG_6,
 813   MOD_0FC7_REG_7,
 814   MOD_0FD7,
 815   MOD_0FE7_PREFIX_2,
 816   MOD_0FF0_PREFIX_3,
 817   MOD_0F382A_PREFIX_2,
 818   MOD_62_32BIT,
 819   MOD_C4_32BIT,
 820   MOD_C5_32BIT,
 821   MOD_VEX_0F12_PREFIX_0,
 822   MOD_VEX_0F13,
 823   MOD_VEX_0F16_PREFIX_0,
 824   MOD_VEX_0F17,
 825   MOD_VEX_0F2B,
 826   MOD_VEX_W_0_0F41_P_0_LEN_1,
 827   MOD_VEX_W_1_0F41_P_0_LEN_1,
 828   MOD_VEX_W_0_0F41_P_2_LEN_1,
 829   MOD_VEX_W_1_0F41_P_2_LEN_1,
 830   MOD_VEX_W_0_0F42_P_0_LEN_1,
 831   MOD_VEX_W_1_0F42_P_0_LEN_1,
 832   MOD_VEX_W_0_0F42_P_2_LEN_1,
 833   MOD_VEX_W_1_0F42_P_2_LEN_1,
 834   MOD_VEX_W_0_0F44_P_0_LEN_1,
 835   MOD_VEX_W_1_0F44_P_0_LEN_1,
 836   MOD_VEX_W_0_0F44_P_2_LEN_1,
 837   MOD_VEX_W_1_0F44_P_2_LEN_1,
 838   MOD_VEX_W_0_0F45_P_0_LEN_1,
 839   MOD_VEX_W_1_0F45_P_0_LEN_1,
 840   MOD_VEX_W_0_0F45_P_2_LEN_1,
 841   MOD_VEX_W_1_0F45_P_2_LEN_1,
 842   MOD_VEX_W_0_0F46_P_0_LEN_1,
 843   MOD_VEX_W_1_0F46_P_0_LEN_1,
 844   MOD_VEX_W_0_0F46_P_2_LEN_1,
 845   MOD_VEX_W_1_0F46_P_2_LEN_1,
 846   MOD_VEX_W_0_0F47_P_0_LEN_1,
 847   MOD_VEX_W_1_0F47_P_0_LEN_1,
 848   MOD_VEX_W_0_0F47_P_2_LEN_1,
 849   MOD_VEX_W_1_0F47_P_2_LEN_1,
 850   MOD_VEX_W_0_0F4A_P_0_LEN_1,
 851   MOD_VEX_W_1_0F4A_P_0_LEN_1,
 852   MOD_VEX_W_0_0F4A_P_2_LEN_1,
 853   MOD_VEX_W_1_0F4A_P_2_LEN_1,
 854   MOD_VEX_W_0_0F4B_P_0_LEN_1,
 855   MOD_VEX_W_1_0F4B_P_0_LEN_1,
 856   MOD_VEX_W_0_0F4B_P_2_LEN_1,
 857   MOD_VEX_0F50,
 858   MOD_VEX_0F71_REG_2,
 859   MOD_VEX_0F71_REG_4,
 860   MOD_VEX_0F71_REG_6,
 861   MOD_VEX_0F72_REG_2,
 862   MOD_VEX_0F72_REG_4,
 863   MOD_VEX_0F72_REG_6,
 864   MOD_VEX_0F73_REG_2,
 865   MOD_VEX_0F73_REG_3,
 866   MOD_VEX_0F73_REG_6,
 867   MOD_VEX_0F73_REG_7,
 868   MOD_VEX_W_0_0F91_P_0_LEN_0,
 869   MOD_VEX_W_1_0F91_P_0_LEN_0,
 870   MOD_VEX_W_0_0F91_P_2_LEN_0,
 871   MOD_VEX_W_1_0F91_P_2_LEN_0,
 872   MOD_VEX_W_0_0F92_P_0_LEN_0,
 873   MOD_VEX_W_0_0F92_P_2_LEN_0,
 874   MOD_VEX_W_0_0F92_P_3_LEN_0,
 875   MOD_VEX_W_1_0F92_P_3_LEN_0,
 876   MOD_VEX_W_0_0F93_P_0_LEN_0,
 877   MOD_VEX_W_0_0F93_P_2_LEN_0,
 878   MOD_VEX_W_0_0F93_P_3_LEN_0,
 879   MOD_VEX_W_1_0F93_P_3_LEN_0,
 880   MOD_VEX_W_0_0F98_P_0_LEN_0,
 881   MOD_VEX_W_1_0F98_P_0_LEN_0,
 882   MOD_VEX_W_0_0F98_P_2_LEN_0,
 883   MOD_VEX_W_1_0F98_P_2_LEN_0,
 884   MOD_VEX_W_0_0F99_P_0_LEN_0,
 885   MOD_VEX_W_1_0F99_P_0_LEN_0,
 886   MOD_VEX_W_0_0F99_P_2_LEN_0,
 887   MOD_VEX_W_1_0F99_P_2_LEN_0,
 888   MOD_VEX_0FAE_REG_2,
 889   MOD_VEX_0FAE_REG_3,
 890   MOD_VEX_0FD7_PREFIX_2,
 891   MOD_VEX_0FE7_PREFIX_2,
 892   MOD_VEX_0FF0_PREFIX_3,
 893   MOD_VEX_0F381A_PREFIX_2,
 894   MOD_VEX_0F382A_PREFIX_2,
 895   MOD_VEX_0F382C_PREFIX_2,
 896   MOD_VEX_0F382D_PREFIX_2,
 897   MOD_VEX_0F382E_PREFIX_2,
 898   MOD_VEX_0F382F_PREFIX_2,
 899   MOD_VEX_0F385A_PREFIX_2,
 900   MOD_VEX_0F388C_PREFIX_2,
 901   MOD_VEX_0F388E_PREFIX_2,
 902   MOD_VEX_W_0_0F3A30_P_2_LEN_0,
 903   MOD_VEX_W_1_0F3A30_P_2_LEN_0,
 904   MOD_VEX_W_0_0F3A31_P_2_LEN_0,
 905   MOD_VEX_W_1_0F3A31_P_2_LEN_0,
 906   MOD_VEX_W_0_0F3A32_P_2_LEN_0,
 907   MOD_VEX_W_1_0F3A32_P_2_LEN_0,
 908   MOD_VEX_W_0_0F3A33_P_2_LEN_0,
 909   MOD_VEX_W_1_0F3A33_P_2_LEN_0,
 910
 911   MOD_EVEX_0F10_PREFIX_1,
 912   MOD_EVEX_0F10_PREFIX_3,
 913   MOD_EVEX_0F11_PREFIX_1,
 914   MOD_EVEX_0F11_PREFIX_3,
 915   MOD_EVEX_0F12_PREFIX_0,
 916   MOD_EVEX_0F16_PREFIX_0,
 917   MOD_EVEX_0F38C6_REG_1,
 918   MOD_EVEX_0F38C6_REG_2,
 919   MOD_EVEX_0F38C6_REG_5,
 920   MOD_EVEX_0F38C6_REG_6,
 921   MOD_EVEX_0F38C7_REG_1,
 922   MOD_EVEX_0F38C7_REG_2,
 923   MOD_EVEX_0F38C7_REG_5,
 924   MOD_EVEX_0F38C7_REG_6
 925 };
 926
 927 enum
 928 {
 929   RM_C6_REG_7 = 0,
 930   RM_C7_REG_7,
 931   RM_0F01_REG_0,
 932   RM_0F01_REG_1,
 933   RM_0F01_REG_2,
 934   RM_0F01_REG_3,
 935   RM_0F01_REG_5,
 936   RM_0F01_REG_7,
 937   RM_0FAE_REG_5,
 938   RM_0FAE_REG_6,
 939   RM_0FAE_REG_7
 940 };
 941
 942 enum
 943 {
 944   PREFIX_90 = 0,
 945   PREFIX_0F10,
 946   PREFIX_0F11,
 947   PREFIX_0F12,
 948   PREFIX_0F16,
 949   PREFIX_0F1A,
 950   PREFIX_0F1B,
 951   PREFIX_0F2A,
 952   PREFIX_0F2B,
 953   PREFIX_0F2C,
 954   PREFIX_0F2D,
 955   PREFIX_0F2E,
 956   PREFIX_0F2F,
 957   PREFIX_0F51,
 958   PREFIX_0F52,
 959   PREFIX_0F53,
 960   PREFIX_0F58,
 961   PREFIX_0F59,
 962   PREFIX_0F5A,
 963   PREFIX_0F5B,
 964   PREFIX_0F5C,
 965   PREFIX_0F5D,
 966   PREFIX_0F5E,
 967   PREFIX_0F5F,
 968   PREFIX_0F60,
 969   PREFIX_0F61,
 970   PREFIX_0F62,
 971   PREFIX_0F6C,
 972   PREFIX_0F6D,
 973   PREFIX_0F6F,
 974   PREFIX_0F70,
 975   PREFIX_0F73_REG_3,
 976   PREFIX_0F73_REG_7,
 977   PREFIX_0F78,
 978   PREFIX_0F79,
 979   PREFIX_0F7C,
 980   PREFIX_0F7D,
 981   PREFIX_0F7E,
 982   PREFIX_0F7F,
 983   PREFIX_0FAE_REG_0,
 984   PREFIX_0FAE_REG_1,
 985   PREFIX_0FAE_REG_2,
 986   PREFIX_0FAE_REG_3,
 987   PREFIX_MOD_0_0FAE_REG_4,
 988   PREFIX_MOD_3_0FAE_REG_4,
 989   PREFIX_0FAE_REG_6,
 990   PREFIX_0FAE_REG_7,
 991   PREFIX_RM_0_0FAE_REG_7,
 992   PREFIX_0FB8,
 993   PREFIX_0FBC,
 994   PREFIX_0FBD,
 995   PREFIX_0FC2,
 996   PREFIX_MOD_0_0FC3,
 997   PREFIX_MOD_0_0FC7_REG_6,
 998   PREFIX_MOD_3_0FC7_REG_6,
 999   PREFIX_MOD_3_0FC7_REG_7,
1000   PREFIX_0FD0,
1001   PREFIX_0FD6,
1002   PREFIX_0FE6,
1003   PREFIX_0FE7,
1004   PREFIX_0FF0,
1005   PREFIX_0FF7,
1006   PREFIX_0F3810,
1007   PREFIX_0F3814,
1008   PREFIX_0F3815,
1009   PREFIX_0F3817,
1010   PREFIX_0F3820,
1011   PREFIX_0F3821,
1012   PREFIX_0F3822,
1013   PREFIX_0F3823,
1014   PREFIX_0F3824,
1015   PREFIX_0F3825,
1016   PREFIX_0F3828,
1017   PREFIX_0F3829,
1018   PREFIX_0F382A,
1019   PREFIX_0F382B,
1020   PREFIX_0F3830,
1021   PREFIX_0F3831,
1022   PREFIX_0F3832,
1023   PREFIX_0F3833,
1024   PREFIX_0F3834,
1025   PREFIX_0F3835,
1026   PREFIX_0F3837,
1027   PREFIX_0F3838,
1028   PREFIX_0F3839,
1029   PREFIX_0F383A,
1030   PREFIX_0F383B,
1031   PREFIX_0F383C,
1032   PREFIX_0F383D,
1033   PREFIX_0F383E,
1034   PREFIX_0F383F,
1035   PREFIX_0F3840,
1036   PREFIX_0F3841,
1037   PREFIX_0F3880,
1038   PREFIX_0F3881,
1039   PREFIX_0F3882,
1040   PREFIX_0F38C8,
1041   PREFIX_0F38C9,
1042   PREFIX_0F38CA,
1043   PREFIX_0F38CB,
1044   PREFIX_0F38CC,
1045   PREFIX_0F38CD,
1046   PREFIX_0F38DB,
1047   PREFIX_0F38DC,
1048   PREFIX_0F38DD,
1049   PREFIX_0F38DE,
1050   PREFIX_0F38DF,
1051   PREFIX_0F38F0,
1052   PREFIX_0F38F1,
1053   PREFIX_0F38F6,
1054   PREFIX_0F3A08,
1055   PREFIX_0F3A09,
1056   PREFIX_0F3A0A,
1057   PREFIX_0F3A0B,
1058   PREFIX_0F3A0C,
1059   PREFIX_0F3A0D,
1060   PREFIX_0F3A0E,
1061   PREFIX_0F3A14,
1062   PREFIX_0F3A15,
1063   PREFIX_0F3A16,
1064   PREFIX_0F3A17,
1065   PREFIX_0F3A20,
1066   PREFIX_0F3A21,
1067   PREFIX_0F3A22,
1068   PREFIX_0F3A40,
1069   PREFIX_0F3A41,
1070   PREFIX_0F3A42,
1071   PREFIX_0F3A44,
1072   PREFIX_0F3A60,
1073   PREFIX_0F3A61,
1074   PREFIX_0F3A62,
1075   PREFIX_0F3A63,
1076   PREFIX_0F3ACC,
1077   PREFIX_0F3ADF,
1078   PREFIX_VEX_0F10,
1079   PREFIX_VEX_0F11,
1080   PREFIX_VEX_0F12,
1081   PREFIX_VEX_0F16,
1082   PREFIX_VEX_0F2A,
1083   PREFIX_VEX_0F2C,
1084   PREFIX_VEX_0F2D,
1085   PREFIX_VEX_0F2E,
1086   PREFIX_VEX_0F2F,
1087   PREFIX_VEX_0F41,
1088   PREFIX_VEX_0F42,
1089   PREFIX_VEX_0F44,
1090   PREFIX_VEX_0F45,
1091   PREFIX_VEX_0F46,
1092   PREFIX_VEX_0F47,
1093   PREFIX_VEX_0F4A,
1094   PREFIX_VEX_0F4B,
1095   PREFIX_VEX_0F51,
1096   PREFIX_VEX_0F52,
1097   PREFIX_VEX_0F53,
1098   PREFIX_VEX_0F58,
1099   PREFIX_VEX_0F59,
1100   PREFIX_VEX_0F5A,
1101   PREFIX_VEX_0F5B,
1102   PREFIX_VEX_0F5C,
1103   PREFIX_VEX_0F5D,
1104   PREFIX_VEX_0F5E,
1105   PREFIX_VEX_0F5F,
1106   PREFIX_VEX_0F60,
1107   PREFIX_VEX_0F61,
1108   PREFIX_VEX_0F62,
1109   PREFIX_VEX_0F63,
1110   PREFIX_VEX_0F64,
1111   PREFIX_VEX_0F65,
1112   PREFIX_VEX_0F66,
1113   PREFIX_VEX_0F67,
1114   PREFIX_VEX_0F68,
1115   PREFIX_VEX_0F69,
1116   PREFIX_VEX_0F6A,
1117   PREFIX_VEX_0F6B,
1118   PREFIX_VEX_0F6C,
1119   PREFIX_VEX_0F6D,
1120   PREFIX_VEX_0F6E,
1121   PREFIX_VEX_0F6F,
1122   PREFIX_VEX_0F70,
1123   PREFIX_VEX_0F71_REG_2,
1124   PREFIX_VEX_0F71_REG_4,
1125   PREFIX_VEX_0F71_REG_6,
1126   PREFIX_VEX_0F72_REG_2,
1127   PREFIX_VEX_0F72_REG_4,
1128   PREFIX_VEX_0F72_REG_6,
1129   PREFIX_VEX_0F73_REG_2,
1130   PREFIX_VEX_0F73_REG_3,
1131   PREFIX_VEX_0F73_REG_6,
1132   PREFIX_VEX_0F73_REG_7,
1133   PREFIX_VEX_0F74,
1134   PREFIX_VEX_0F75,
1135   PREFIX_VEX_0F76,
1136   PREFIX_VEX_0F77,
1137   PREFIX_VEX_0F7C,
1138   PREFIX_VEX_0F7D,
1139   PREFIX_VEX_0F7E,
1140   PREFIX_VEX_0F7F,
1141   PREFIX_VEX_0F90,
1142   PREFIX_VEX_0F91,
1143   PREFIX_VEX_0F92,
1144   PREFIX_VEX_0F93,
1145   PREFIX_VEX_0F98,
1146   PREFIX_VEX_0F99,
1147   PREFIX_VEX_0FC2,
1148   PREFIX_VEX_0FC4,
1149   PREFIX_VEX_0FC5,
1150   PREFIX_VEX_0FD0,
1151   PREFIX_VEX_0FD1,
1152   PREFIX_VEX_0FD2,
1153   PREFIX_VEX_0FD3,
1154   PREFIX_VEX_0FD4,
1155   PREFIX_VEX_0FD5,
1156   PREFIX_VEX_0FD6,
1157   PREFIX_VEX_0FD7,
1158   PREFIX_VEX_0FD8,
1159   PREFIX_VEX_0FD9,
1160   PREFIX_VEX_0FDA,
1161   PREFIX_VEX_0FDB,
1162   PREFIX_VEX_0FDC,
1163   PREFIX_VEX_0FDD,
1164   PREFIX_VEX_0FDE,
1165   PREFIX_VEX_0FDF,
1166   PREFIX_VEX_0FE0,
1167   PREFIX_VEX_0FE1,
1168   PREFIX_VEX_0FE2,
1169   PREFIX_VEX_0FE3,
1170   PREFIX_VEX_0FE4,
1171   PREFIX_VEX_0FE5,
1172   PREFIX_VEX_0FE6,
1173   PREFIX_VEX_0FE7,
1174   PREFIX_VEX_0FE8,
1175   PREFIX_VEX_0FE9,
1176   PREFIX_VEX_0FEA,
1177   PREFIX_VEX_0FEB,
1178   PREFIX_VEX_0FEC,
1179   PREFIX_VEX_0FED,
1180   PREFIX_VEX_0FEE,
1181   PREFIX_VEX_0FEF,
1182   PREFIX_VEX_0FF0,
1183   PREFIX_VEX_0FF1,
1184   PREFIX_VEX_0FF2,
1185   PREFIX_VEX_0FF3,
1186   PREFIX_VEX_0FF4,
1187   PREFIX_VEX_0FF5,
1188   PREFIX_VEX_0FF6,
1189   PREFIX_VEX_0FF7,
1190   PREFIX_VEX_0FF8,
1191   PREFIX_VEX_0FF9,
1192   PREFIX_VEX_0FFA,
1193   PREFIX_VEX_0FFB,
1194   PREFIX_VEX_0FFC,
1195   PREFIX_VEX_0FFD,
1196   PREFIX_VEX_0FFE,
1197   PREFIX_VEX_0F3800,
1198   PREFIX_VEX_0F3801,
1199   PREFIX_VEX_0F3802,
1200   PREFIX_VEX_0F3803,
1201   PREFIX_VEX_0F3804,
1202   PREFIX_VEX_0F3805,
1203   PREFIX_VEX_0F3806,
1204   PREFIX_VEX_0F3807,
1205   PREFIX_VEX_0F3808,
1206   PREFIX_VEX_0F3809,
1207   PREFIX_VEX_0F380A,
1208   PREFIX_VEX_0F380B,
1209   PREFIX_VEX_0F380C,
1210   PREFIX_VEX_0F380D,
1211   PREFIX_VEX_0F380E,
1212   PREFIX_VEX_0F380F,
1213   PREFIX_VEX_0F3813,
1214   PREFIX_VEX_0F3816,
1215   PREFIX_VEX_0F3817,
1216   PREFIX_VEX_0F3818,
1217   PREFIX_VEX_0F3819,
1218   PREFIX_VEX_0F381A,
1219   PREFIX_VEX_0F381C,
1220   PREFIX_VEX_0F381D,
1221   PREFIX_VEX_0F381E,
1222   PREFIX_VEX_0F3820,
1223   PREFIX_VEX_0F3821,
1224   PREFIX_VEX_0F3822,
1225   PREFIX_VEX_0F3823,
1226   PREFIX_VEX_0F3824,
1227   PREFIX_VEX_0F3825,
1228   PREFIX_VEX_0F3828,
1229   PREFIX_VEX_0F3829,
1230   PREFIX_VEX_0F382A,
1231   PREFIX_VEX_0F382B,
1232   PREFIX_VEX_0F382C,
1233   PREFIX_VEX_0F382D,
1234   PREFIX_VEX_0F382E,
1235   PREFIX_VEX_0F382F,
1236   PREFIX_VEX_0F3830,
1237   PREFIX_VEX_0F3831,
1238   PREFIX_VEX_0F3832,
1239   PREFIX_VEX_0F3833,
1240   PREFIX_VEX_0F3834,
1241   PREFIX_VEX_0F3835,
1242   PREFIX_VEX_0F3836,
1243   PREFIX_VEX_0F3837,
1244   PREFIX_VEX_0F3838,
1245   PREFIX_VEX_0F3839,
1246   PREFIX_VEX_0F383A,
1247   PREFIX_VEX_0F383B,
1248   PREFIX_VEX_0F383C,
1249   PREFIX_VEX_0F383D,
1250   PREFIX_VEX_0F383E,
1251   PREFIX_VEX_0F383F,
1252   PREFIX_VEX_0F3840,
1253   PREFIX_VEX_0F3841,
1254   PREFIX_VEX_0F3845,
1255   PREFIX_VEX_0F3846,
1256   PREFIX_VEX_0F3847,
1257   PREFIX_VEX_0F3858,
1258   PREFIX_VEX_0F3859,
1259   PREFIX_VEX_0F385A,
1260   PREFIX_VEX_0F3878,
1261   PREFIX_VEX_0F3879,
1262   PREFIX_VEX_0F388C,
1263   PREFIX_VEX_0F388E,
1264   PREFIX_VEX_0F3890,
1265   PREFIX_VEX_0F3891,
1266   PREFIX_VEX_0F3892,
1267   PREFIX_VEX_0F3893,
1268   PREFIX_VEX_0F3896,
1269   PREFIX_VEX_0F3897,
1270   PREFIX_VEX_0F3898,
1271   PREFIX_VEX_0F3899,
1272   PREFIX_VEX_0F389A,
1273   PREFIX_VEX_0F389B,
1274   PREFIX_VEX_0F389C,
1275   PREFIX_VEX_0F389D,
1276   PREFIX_VEX_0F389E,
1277   PREFIX_VEX_0F389F,
1278   PREFIX_VEX_0F38A6,
1279   PREFIX_VEX_0F38A7,
1280   PREFIX_VEX_0F38A8,
1281   PREFIX_VEX_0F38A9,
1282   PREFIX_VEX_0F38AA,
1283   PREFIX_VEX_0F38AB,
1284   PREFIX_VEX_0F38AC,
1285   PREFIX_VEX_0F38AD,
1286   PREFIX_VEX_0F38AE,
1287   PREFIX_VEX_0F38AF,
1288   PREFIX_VEX_0F38B6,
1289   PREFIX_VEX_0F38B7,
1290   PREFIX_VEX_0F38B8,
1291   PREFIX_VEX_0F38B9,
1292   PREFIX_VEX_0F38BA,
1293   PREFIX_VEX_0F38BB,
1294   PREFIX_VEX_0F38BC,
1295   PREFIX_VEX_0F38BD,
1296   PREFIX_VEX_0F38BE,
1297   PREFIX_VEX_0F38BF,
1298   PREFIX_VEX_0F38DB,
1299   PREFIX_VEX_0F38DC,
1300   PREFIX_VEX_0F38DD,
1301   PREFIX_VEX_0F38DE,
1302   PREFIX_VEX_0F38DF,
1303   PREFIX_VEX_0F38F2,
1304   PREFIX_VEX_0F38F3_REG_1,
1305   PREFIX_VEX_0F38F3_REG_2,
1306   PREFIX_VEX_0F38F3_REG_3,
1307   PREFIX_VEX_0F38F5,
1308   PREFIX_VEX_0F38F6,
1309   PREFIX_VEX_0F38F7,
1310   PREFIX_VEX_0F3A00,
1311   PREFIX_VEX_0F3A01,
1312   PREFIX_VEX_0F3A02,
1313   PREFIX_VEX_0F3A04,
1314   PREFIX_VEX_0F3A05,
1315   PREFIX_VEX_0F3A06,
1316   PREFIX_VEX_0F3A08,
1317   PREFIX_VEX_0F3A09,
1318   PREFIX_VEX_0F3A0A,
1319   PREFIX_VEX_0F3A0B,
1320   PREFIX_VEX_0F3A0C,
1321   PREFIX_VEX_0F3A0D,
1322   PREFIX_VEX_0F3A0E,
1323   PREFIX_VEX_0F3A0F,
1324   PREFIX_VEX_0F3A14,
1325   PREFIX_VEX_0F3A15,
1326   PREFIX_VEX_0F3A16,
1327   PREFIX_VEX_0F3A17,
1328   PREFIX_VEX_0F3A18,
1329   PREFIX_VEX_0F3A19,
1330   PREFIX_VEX_0F3A1D,
1331   PREFIX_VEX_0F3A20,
1332   PREFIX_VEX_0F3A21,
1333   PREFIX_VEX_0F3A22,
1334   PREFIX_VEX_0F3A30,
1335   PREFIX_VEX_0F3A31,
1336   PREFIX_VEX_0F3A32,
1337   PREFIX_VEX_0F3A33,
1338   PREFIX_VEX_0F3A38,
1339   PREFIX_VEX_0F3A39,
1340   PREFIX_VEX_0F3A40,
1341   PREFIX_VEX_0F3A41,
1342   PREFIX_VEX_0F3A42,
1343   PREFIX_VEX_0F3A44,
1344   PREFIX_VEX_0F3A46,
1345   PREFIX_VEX_0F3A48,
1346   PREFIX_VEX_0F3A49,
1347   PREFIX_VEX_0F3A4A,
1348   PREFIX_VEX_0F3A4B,
1349   PREFIX_VEX_0F3A4C,
1350   PREFIX_VEX_0F3A5C,
1351   PREFIX_VEX_0F3A5D,
1352   PREFIX_VEX_0F3A5E,
1353   PREFIX_VEX_0F3A5F,
1354   PREFIX_VEX_0F3A60,
1355   PREFIX_VEX_0F3A61,
1356   PREFIX_VEX_0F3A62,
1357   PREFIX_VEX_0F3A63,
1358   PREFIX_VEX_0F3A68,
1359   PREFIX_VEX_0F3A69,
1360   PREFIX_VEX_0F3A6A,
1361   PREFIX_VEX_0F3A6B,
1362   PREFIX_VEX_0F3A6C,
1363   PREFIX_VEX_0F3A6D,
1364   PREFIX_VEX_0F3A6E,
1365   PREFIX_VEX_0F3A6F,
1366   PREFIX_VEX_0F3A78,
1367   PREFIX_VEX_0F3A79,
1368   PREFIX_VEX_0F3A7A,
1369   PREFIX_VEX_0F3A7B,
1370   PREFIX_VEX_0F3A7C,
1371   PREFIX_VEX_0F3A7D,
1372   PREFIX_VEX_0F3A7E,
1373   PREFIX_VEX_0F3A7F,
1374   PREFIX_VEX_0F3ADF,
1375   PREFIX_VEX_0F3AF0,
1376
1377   PREFIX_EVEX_0F10,
1378   PREFIX_EVEX_0F11,
1379   PREFIX_EVEX_0F12,
1380   PREFIX_EVEX_0F13,
1381   PREFIX_EVEX_0F14,
1382   PREFIX_EVEX_0F15,
1383   PREFIX_EVEX_0F16,
1384   PREFIX_EVEX_0F17,
1385   PREFIX_EVEX_0F28,
1386   PREFIX_EVEX_0F29,
1387   PREFIX_EVEX_0F2A,
1388   PREFIX_EVEX_0F2B,
1389   PREFIX_EVEX_0F2C,
1390   PREFIX_EVEX_0F2D,
1391   PREFIX_EVEX_0F2E,
1392   PREFIX_EVEX_0F2F,
1393   PREFIX_EVEX_0F51,
1394   PREFIX_EVEX_0F54,
1395   PREFIX_EVEX_0F55,
1396   PREFIX_EVEX_0F56,
1397   PREFIX_EVEX_0F57,
1398   PREFIX_EVEX_0F58,
1399   PREFIX_EVEX_0F59,
1400   PREFIX_EVEX_0F5A,
1401   PREFIX_EVEX_0F5B,
1402   PREFIX_EVEX_0F5C,
1403   PREFIX_EVEX_0F5D,
1404   PREFIX_EVEX_0F5E,
1405   PREFIX_EVEX_0F5F,
1406   PREFIX_EVEX_0F60,
1407   PREFIX_EVEX_0F61,
1408   PREFIX_EVEX_0F62,
1409   PREFIX_EVEX_0F63,
1410   PREFIX_EVEX_0F64,
1411   PREFIX_EVEX_0F65,
1412   PREFIX_EVEX_0F66,
1413   PREFIX_EVEX_0F67,
1414   PREFIX_EVEX_0F68,
1415   PREFIX_EVEX_0F69,
1416   PREFIX_EVEX_0F6A,
1417   PREFIX_EVEX_0F6B,
1418   PREFIX_EVEX_0F6C,
1419   PREFIX_EVEX_0F6D,
1420   PREFIX_EVEX_0F6E,
1421   PREFIX_EVEX_0F6F,
1422   PREFIX_EVEX_0F70,
1423   PREFIX_EVEX_0F71_REG_2,
1424   PREFIX_EVEX_0F71_REG_4,
1425   PREFIX_EVEX_0F71_REG_6,
1426   PREFIX_EVEX_0F72_REG_0,
1427   PREFIX_EVEX_0F72_REG_1,
1428   PREFIX_EVEX_0F72_REG_2,
1429   PREFIX_EVEX_0F72_REG_4,
1430   PREFIX_EVEX_0F72_REG_6,
1431   PREFIX_EVEX_0F73_REG_2,
1432   PREFIX_EVEX_0F73_REG_3,
1433   PREFIX_EVEX_0F73_REG_6,
1434   PREFIX_EVEX_0F73_REG_7,
1435   PREFIX_EVEX_0F74,
1436   PREFIX_EVEX_0F75,
1437   PREFIX_EVEX_0F76,
1438   PREFIX_EVEX_0F78,
1439   PREFIX_EVEX_0F79,
1440   PREFIX_EVEX_0F7A,
1441   PREFIX_EVEX_0F7B,
1442   PREFIX_EVEX_0F7E,
1443   PREFIX_EVEX_0F7F,
1444   PREFIX_EVEX_0FC2,
1445   PREFIX_EVEX_0FC4,
1446   PREFIX_EVEX_0FC5,
1447   PREFIX_EVEX_0FC6,
1448   PREFIX_EVEX_0FD1,
1449   PREFIX_EVEX_0FD2,
1450   PREFIX_EVEX_0FD3,
1451   PREFIX_EVEX_0FD4,
1452   PREFIX_EVEX_0FD5,
1453   PREFIX_EVEX_0FD6,
1454   PREFIX_EVEX_0FD8,
1455   PREFIX_EVEX_0FD9,
1456   PREFIX_EVEX_0FDA,
1457   PREFIX_EVEX_0FDB,
1458   PREFIX_EVEX_0FDC,
1459   PREFIX_EVEX_0FDD,
1460   PREFIX_EVEX_0FDE,
1461   PREFIX_EVEX_0FDF,
1462   PREFIX_EVEX_0FE0,
1463   PREFIX_EVEX_0FE1,
1464   PREFIX_EVEX_0FE2,
1465   PREFIX_EVEX_0FE3,
1466   PREFIX_EVEX_0FE4,
1467   PREFIX_EVEX_0FE5,
1468   PREFIX_EVEX_0FE6,
1469   PREFIX_EVEX_0FE7,
1470   PREFIX_EVEX_0FE8,
1471   PREFIX_EVEX_0FE9,
1472   PREFIX_EVEX_0FEA,
1473   PREFIX_EVEX_0FEB,
1474   PREFIX_EVEX_0FEC,
1475   PREFIX_EVEX_0FED,
1476   PREFIX_EVEX_0FEE,
1477   PREFIX_EVEX_0FEF,
1478   PREFIX_EVEX_0FF1,
1479   PREFIX_EVEX_0FF2,
1480   PREFIX_EVEX_0FF3,
1481   PREFIX_EVEX_0FF4,
1482   PREFIX_EVEX_0FF5,
1483   PREFIX_EVEX_0FF6,
1484   PREFIX_EVEX_0FF8,
1485   PREFIX_EVEX_0FF9,
1486   PREFIX_EVEX_0FFA,
1487   PREFIX_EVEX_0FFB,
1488   PREFIX_EVEX_0FFC,
1489   PREFIX_EVEX_0FFD,
1490   PREFIX_EVEX_0FFE,
1491   PREFIX_EVEX_0F3800,
1492   PREFIX_EVEX_0F3804,
1493   PREFIX_EVEX_0F380B,
1494   PREFIX_EVEX_0F380C,
1495   PREFIX_EVEX_0F380D,
1496   PREFIX_EVEX_0F3810,
1497   PREFIX_EVEX_0F3811,
1498   PREFIX_EVEX_0F3812,
1499   PREFIX_EVEX_0F3813,
1500   PREFIX_EVEX_0F3814,
1501   PREFIX_EVEX_0F3815,
1502   PREFIX_EVEX_0F3816,
1503   PREFIX_EVEX_0F3818,
1504   PREFIX_EVEX_0F3819,
1505   PREFIX_EVEX_0F381A,
1506   PREFIX_EVEX_0F381B,
1507   PREFIX_EVEX_0F381C,
1508   PREFIX_EVEX_0F381D,
1509   PREFIX_EVEX_0F381E,
1510   PREFIX_EVEX_0F381F,
1511   PREFIX_EVEX_0F3820,
1512   PREFIX_EVEX_0F3821,
1513   PREFIX_EVEX_0F3822,
1514   PREFIX_EVEX_0F3823,
1515   PREFIX_EVEX_0F3824,
1516   PREFIX_EVEX_0F3825,
1517   PREFIX_EVEX_0F3826,
1518   PREFIX_EVEX_0F3827,
1519   PREFIX_EVEX_0F3828,
1520   PREFIX_EVEX_0F3829,
1521   PREFIX_EVEX_0F382A,
1522   PREFIX_EVEX_0F382B,
1523   PREFIX_EVEX_0F382C,
1524   PREFIX_EVEX_0F382D,
1525   PREFIX_EVEX_0F3830,
1526   PREFIX_EVEX_0F3831,
1527   PREFIX_EVEX_0F3832,
1528   PREFIX_EVEX_0F3833,
1529   PREFIX_EVEX_0F3834,
1530   PREFIX_EVEX_0F3835,
1531   PREFIX_EVEX_0F3836,
1532   PREFIX_EVEX_0F3837,
1533   PREFIX_EVEX_0F3838,
1534   PREFIX_EVEX_0F3839,
1535   PREFIX_EVEX_0F383A,
1536   PREFIX_EVEX_0F383B,
1537   PREFIX_EVEX_0F383C,
1538   PREFIX_EVEX_0F383D,
1539   PREFIX_EVEX_0F383E,
1540   PREFIX_EVEX_0F383F,
1541   PREFIX_EVEX_0F3840,
1542   PREFIX_EVEX_0F3842,
1543   PREFIX_EVEX_0F3843,
1544   PREFIX_EVEX_0F3844,
1545   PREFIX_EVEX_0F3845,
1546   PREFIX_EVEX_0F3846,
1547   PREFIX_EVEX_0F3847,
1548   PREFIX_EVEX_0F384C,
1549   PREFIX_EVEX_0F384D,
1550   PREFIX_EVEX_0F384E,
1551   PREFIX_EVEX_0F384F,
1552   PREFIX_EVEX_0F3858,
1553   PREFIX_EVEX_0F3859,
1554   PREFIX_EVEX_0F385A,
1555   PREFIX_EVEX_0F385B,
1556   PREFIX_EVEX_0F3864,
1557   PREFIX_EVEX_0F3865,
1558   PREFIX_EVEX_0F3866,
1559   PREFIX_EVEX_0F3875,
1560   PREFIX_EVEX_0F3876,
1561   PREFIX_EVEX_0F3877,
1562   PREFIX_EVEX_0F3878,
1563   PREFIX_EVEX_0F3879,
1564   PREFIX_EVEX_0F387A,
1565   PREFIX_EVEX_0F387B,
1566   PREFIX_EVEX_0F387C,
1567   PREFIX_EVEX_0F387D,
1568   PREFIX_EVEX_0F387E,
1569   PREFIX_EVEX_0F387F,
1570   PREFIX_EVEX_0F3883,
1571   PREFIX_EVEX_0F3888,
1572   PREFIX_EVEX_0F3889,
1573   PREFIX_EVEX_0F388A,
1574   PREFIX_EVEX_0F388B,
1575   PREFIX_EVEX_0F388D,
1576   PREFIX_EVEX_0F3890,
1577   PREFIX_EVEX_0F3891,
1578   PREFIX_EVEX_0F3892,
1579   PREFIX_EVEX_0F3893,
1580   PREFIX_EVEX_0F3896,
1581   PREFIX_EVEX_0F3897,
1582   PREFIX_EVEX_0F3898,
1583   PREFIX_EVEX_0F3899,
1584   PREFIX_EVEX_0F389A,
1585   PREFIX_EVEX_0F389B,
1586   PREFIX_EVEX_0F389C,
1587   PREFIX_EVEX_0F389D,
1588   PREFIX_EVEX_0F389E,
1589   PREFIX_EVEX_0F389F,
1590   PREFIX_EVEX_0F38A0,
1591   PREFIX_EVEX_0F38A1,
1592   PREFIX_EVEX_0F38A2,
1593   PREFIX_EVEX_0F38A3,
1594   PREFIX_EVEX_0F38A6,
1595   PREFIX_EVEX_0F38A7,
1596   PREFIX_EVEX_0F38A8,
1597   PREFIX_EVEX_0F38A9,
1598   PREFIX_EVEX_0F38AA,
1599   PREFIX_EVEX_0F38AB,
1600   PREFIX_EVEX_0F38AC,
1601   PREFIX_EVEX_0F38AD,
1602   PREFIX_EVEX_0F38AE,
1603   PREFIX_EVEX_0F38AF,
1604   PREFIX_EVEX_0F38B4,
1605   PREFIX_EVEX_0F38B5,
1606   PREFIX_EVEX_0F38B6,
1607   PREFIX_EVEX_0F38B7,
1608   PREFIX_EVEX_0F38B8,
1609   PREFIX_EVEX_0F38B9,
1610   PREFIX_EVEX_0F38BA,
1611   PREFIX_EVEX_0F38BB,
1612   PREFIX_EVEX_0F38BC,
1613   PREFIX_EVEX_0F38BD,
1614   PREFIX_EVEX_0F38BE,
1615   PREFIX_EVEX_0F38BF,
1616   PREFIX_EVEX_0F38C4,
1617   PREFIX_EVEX_0F38C6_REG_1,
1618   PREFIX_EVEX_0F38C6_REG_2,
1619   PREFIX_EVEX_0F38C6_REG_5,
1620   PREFIX_EVEX_0F38C6_REG_6,
1621   PREFIX_EVEX_0F38C7_REG_1,
1622   PREFIX_EVEX_0F38C7_REG_2,
1623   PREFIX_EVEX_0F38C7_REG_5,
1624   PREFIX_EVEX_0F38C7_REG_6,
1625   PREFIX_EVEX_0F38C8,
1626   PREFIX_EVEX_0F38CA,
1627   PREFIX_EVEX_0F38CB,
1628   PREFIX_EVEX_0F38CC,
1629   PREFIX_EVEX_0F38CD,
1630
1631   PREFIX_EVEX_0F3A00,
1632   PREFIX_EVEX_0F3A01,
1633   PREFIX_EVEX_0F3A03,
1634   PREFIX_EVEX_0F3A04,
1635   PREFIX_EVEX_0F3A05,
1636   PREFIX_EVEX_0F3A08,
1637   PREFIX_EVEX_0F3A09,
1638   PREFIX_EVEX_0F3A0A,
1639   PREFIX_EVEX_0F3A0B,
1640   PREFIX_EVEX_0F3A0F,
1641   PREFIX_EVEX_0F3A14,
1642   PREFIX_EVEX_0F3A15,
1643   PREFIX_EVEX_0F3A16,
1644   PREFIX_EVEX_0F3A17,
1645   PREFIX_EVEX_0F3A18,
1646   PREFIX_EVEX_0F3A19,
1647   PREFIX_EVEX_0F3A1A,
1648   PREFIX_EVEX_0F3A1B,
1649   PREFIX_EVEX_0F3A1D,
1650   PREFIX_EVEX_0F3A1E,
1651   PREFIX_EVEX_0F3A1F,
1652   PREFIX_EVEX_0F3A20,
1653   PREFIX_EVEX_0F3A21,
1654   PREFIX_EVEX_0F3A22,
1655   PREFIX_EVEX_0F3A23,
1656   PREFIX_EVEX_0F3A25,
1657   PREFIX_EVEX_0F3A26,
1658   PREFIX_EVEX_0F3A27,
1659   PREFIX_EVEX_0F3A38,
1660   PREFIX_EVEX_0F3A39,
1661   PREFIX_EVEX_0F3A3A,
1662   PREFIX_EVEX_0F3A3B,
1663   PREFIX_EVEX_0F3A3E,
1664   PREFIX_EVEX_0F3A3F,
1665   PREFIX_EVEX_0F3A42,
1666   PREFIX_EVEX_0F3A43,
1667   PREFIX_EVEX_0F3A50,
1668   PREFIX_EVEX_0F3A51,
1669   PREFIX_EVEX_0F3A54,
1670   PREFIX_EVEX_0F3A55,
1671   PREFIX_EVEX_0F3A56,
1672   PREFIX_EVEX_0F3A57,
1673   PREFIX_EVEX_0F3A66,
1674   PREFIX_EVEX_0F3A67
1675 };
1676
1677 enum
1678 {
1679   X86_64_06 = 0,
1680   X86_64_07,
1681   X86_64_0D,
1682   X86_64_16,
1683   X86_64_17,
1684   X86_64_1E,
1685   X86_64_1F,
1686   X86_64_27,
1687   X86_64_2F,
1688   X86_64_37,
1689   X86_64_3F,
1690   X86_64_60,
1691   X86_64_61,
1692   X86_64_62,
1693   X86_64_63,
1694   X86_64_6D,
1695   X86_64_6F,
1696   X86_64_9A,
1697   X86_64_C4,
1698   X86_64_C5,
1699   X86_64_CE,
1700   X86_64_D4,
1701   X86_64_D5,
1702   X86_64_E8,
1703   X86_64_E9,
1704   X86_64_EA,
1705   X86_64_0F01_REG_0,
1706   X86_64_0F01_REG_1,
1707   X86_64_0F01_REG_2,
1708   X86_64_0F01_REG_3
1709 };
1710
1711 enum
1712 {
1713   THREE_BYTE_0F38 = 0,
1714   THREE_BYTE_0F3A,
1715   THREE_BYTE_0F7A
1716 };
1717
1718 enum
1719 {
1720   XOP_08 = 0,
1721   XOP_09,
1722   XOP_0A
1723 };
1724
1725 enum
1726 {
1727   VEX_0F = 0,
1728   VEX_0F38,
1729   VEX_0F3A
1730 };
1731
1732 enum
1733 {
1734   EVEX_0F = 0,
1735   EVEX_0F38,
1736   EVEX_0F3A
1737 };
1738
1739 enum
1740 {
1741   VEX_LEN_0F10_P_1 = 0,
1742   VEX_LEN_0F10_P_3,
1743   VEX_LEN_0F11_P_1,
1744   VEX_LEN_0F11_P_3,
1745   VEX_LEN_0F12_P_0_M_0,
1746   VEX_LEN_0F12_P_0_M_1,
1747   VEX_LEN_0F12_P_2,
1748   VEX_LEN_0F13_M_0,
1749   VEX_LEN_0F16_P_0_M_0,
1750   VEX_LEN_0F16_P_0_M_1,
1751   VEX_LEN_0F16_P_2,
1752   VEX_LEN_0F17_M_0,
1753   VEX_LEN_0F2A_P_1,
1754   VEX_LEN_0F2A_P_3,
1755   VEX_LEN_0F2C_P_1,
1756   VEX_LEN_0F2C_P_3,
1757   VEX_LEN_0F2D_P_1,
1758   VEX_LEN_0F2D_P_3,
1759   VEX_LEN_0F2E_P_0,
1760   VEX_LEN_0F2E_P_2,
1761   VEX_LEN_0F2F_P_0,
1762   VEX_LEN_0F2F_P_2,
1763   VEX_LEN_0F41_P_0,
1764   VEX_LEN_0F41_P_2,
1765   VEX_LEN_0F42_P_0,
1766   VEX_LEN_0F42_P_2,
1767   VEX_LEN_0F44_P_0,
1768   VEX_LEN_0F44_P_2,
1769   VEX_LEN_0F45_P_0,
1770   VEX_LEN_0F45_P_2,
1771   VEX_LEN_0F46_P_0,
1772   VEX_LEN_0F46_P_2,
1773   VEX_LEN_0F47_P_0,
1774   VEX_LEN_0F47_P_2,
1775   VEX_LEN_0F4A_P_0,
1776   VEX_LEN_0F4A_P_2,
1777   VEX_LEN_0F4B_P_0,
1778   VEX_LEN_0F4B_P_2,
1779   VEX_LEN_0F51_P_1,
1780   VEX_LEN_0F51_P_3,
1781   VEX_LEN_0F52_P_1,
1782   VEX_LEN_0F53_P_1,
1783   VEX_LEN_0F58_P_1,
1784   VEX_LEN_0F58_P_3,
1785   VEX_LEN_0F59_P_1,
1786   VEX_LEN_0F59_P_3,
1787   VEX_LEN_0F5A_P_1,
1788   VEX_LEN_0F5A_P_3,
1789   VEX_LEN_0F5C_P_1,
1790   VEX_LEN_0F5C_P_3,
1791   VEX_LEN_0F5D_P_1,
1792   VEX_LEN_0F5D_P_3,
1793   VEX_LEN_0F5E_P_1,
1794   VEX_LEN_0F5E_P_3,
1795   VEX_LEN_0F5F_P_1,
1796   VEX_LEN_0F5F_P_3,
1797   VEX_LEN_0F6E_P_2,
1798   VEX_LEN_0F7E_P_1,
1799   VEX_LEN_0F7E_P_2,
1800   VEX_LEN_0F90_P_0,
1801   VEX_LEN_0F90_P_2,
1802   VEX_LEN_0F91_P_0,
1803   VEX_LEN_0F91_P_2,
1804   VEX_LEN_0F92_P_0,
1805   VEX_LEN_0F92_P_2,
1806   VEX_LEN_0F92_P_3,
1807   VEX_LEN_0F93_P_0,
1808   VEX_LEN_0F93_P_2,
1809   VEX_LEN_0F93_P_3,
1810   VEX_LEN_0F98_P_0,
1811   VEX_LEN_0F98_P_2,
1812   VEX_LEN_0F99_P_0,
1813   VEX_LEN_0F99_P_2,
1814   VEX_LEN_0FAE_R_2_M_0,
1815   VEX_LEN_0FAE_R_3_M_0,
1816   VEX_LEN_0FC2_P_1,
1817   VEX_LEN_0FC2_P_3,
1818   VEX_LEN_0FC4_P_2,
1819   VEX_LEN_0FC5_P_2,
1820   VEX_LEN_0FD6_P_2,
1821   VEX_LEN_0FF7_P_2,
1822   VEX_LEN_0F3816_P_2,
1823   VEX_LEN_0F3819_P_2,
1824   VEX_LEN_0F381A_P_2_M_0,
1825   VEX_LEN_0F3836_P_2,
1826   VEX_LEN_0F3841_P_2,
1827   VEX_LEN_0F385A_P_2_M_0,
1828   VEX_LEN_0F38DB_P_2,
1829   VEX_LEN_0F38DC_P_2,
1830   VEX_LEN_0F38DD_P_2,
1831   VEX_LEN_0F38DE_P_2,
1832   VEX_LEN_0F38DF_P_2,
1833   VEX_LEN_0F38F2_P_0,
1834   VEX_LEN_0F38F3_R_1_P_0,
1835   VEX_LEN_0F38F3_R_2_P_0,
1836   VEX_LEN_0F38F3_R_3_P_0,
1837   VEX_LEN_0F38F5_P_0,
1838   VEX_LEN_0F38F5_P_1,
1839   VEX_LEN_0F38F5_P_3,
1840   VEX_LEN_0F38F6_P_3,
1841   VEX_LEN_0F38F7_P_0,
1842   VEX_LEN_0F38F7_P_1,
1843   VEX_LEN_0F38F7_P_2,
1844   VEX_LEN_0F38F7_P_3,
1845   VEX_LEN_0F3A00_P_2,
1846   VEX_LEN_0F3A01_P_2,
1847   VEX_LEN_0F3A06_P_2,
1848   VEX_LEN_0F3A0A_P_2,
1849   VEX_LEN_0F3A0B_P_2,
1850   VEX_LEN_0F3A14_P_2,
1851   VEX_LEN_0F3A15_P_2,
1852   VEX_LEN_0F3A16_P_2,
1853   VEX_LEN_0F3A17_P_2,
1854   VEX_LEN_0F3A18_P_2,
1855   VEX_LEN_0F3A19_P_2,
1856   VEX_LEN_0F3A20_P_2,
1857   VEX_LEN_0F3A21_P_2,
1858   VEX_LEN_0F3A22_P_2,
1859   VEX_LEN_0F3A30_P_2,
1860   VEX_LEN_0F3A31_P_2,
1861   VEX_LEN_0F3A32_P_2,
1862   VEX_LEN_0F3A33_P_2,
1863   VEX_LEN_0F3A38_P_2,
1864   VEX_LEN_0F3A39_P_2,
1865   VEX_LEN_0F3A41_P_2,
1866   VEX_LEN_0F3A44_P_2,
1867   VEX_LEN_0F3A46_P_2,
1868   VEX_LEN_0F3A60_P_2,
1869   VEX_LEN_0F3A61_P_2,
1870   VEX_LEN_0F3A62_P_2,
1871   VEX_LEN_0F3A63_P_2,
1872   VEX_LEN_0F3A6A_P_2,
1873   VEX_LEN_0F3A6B_P_2,
1874   VEX_LEN_0F3A6E_P_2,
1875   VEX_LEN_0F3A6F_P_2,
1876   VEX_LEN_0F3A7A_P_2,
1877   VEX_LEN_0F3A7B_P_2,
1878   VEX_LEN_0F3A7E_P_2,
1879   VEX_LEN_0F3A7F_P_2,
1880   VEX_LEN_0F3ADF_P_2,
1881   VEX_LEN_0F3AF0_P_3,
1882   VEX_LEN_0FXOP_08_CC,
1883   VEX_LEN_0FXOP_08_CD,
1884   VEX_LEN_0FXOP_08_CE,
1885   VEX_LEN_0FXOP_08_CF,
1886   VEX_LEN_0FXOP_08_EC,
1887   VEX_LEN_0FXOP_08_ED,
1888   VEX_LEN_0FXOP_08_EE,
1889   VEX_LEN_0FXOP_08_EF,
1890   VEX_LEN_0FXOP_09_80,
1891   VEX_LEN_0FXOP_09_81
1892 };
1893
1894 enum
1895 {
1896   VEX_W_0F10_P_0 = 0,
1897   VEX_W_0F10_P_1,
1898   VEX_W_0F10_P_2,
1899   VEX_W_0F10_P_3,
1900   VEX_W_0F11_P_0,
1901   VEX_W_0F11_P_1,
1902   VEX_W_0F11_P_2,
1903   VEX_W_0F11_P_3,
1904   VEX_W_0F12_P_0_M_0,
1905   VEX_W_0F12_P_0_M_1,
1906   VEX_W_0F12_P_1,
1907   VEX_W_0F12_P_2,
1908   VEX_W_0F12_P_3,
1909   VEX_W_0F13_M_0,
1910   VEX_W_0F14,
1911   VEX_W_0F15,
1912   VEX_W_0F16_P_0_M_0,
1913   VEX_W_0F16_P_0_M_1,
1914   VEX_W_0F16_P_1,
1915   VEX_W_0F16_P_2,
1916   VEX_W_0F17_M_0,
1917   VEX_W_0F28,
1918   VEX_W_0F29,
1919   VEX_W_0F2B_M_0,
1920   VEX_W_0F2E_P_0,
1921   VEX_W_0F2E_P_2,
1922   VEX_W_0F2F_P_0,
1923   VEX_W_0F2F_P_2,
1924   VEX_W_0F41_P_0_LEN_1,
1925   VEX_W_0F41_P_2_LEN_1,
1926   VEX_W_0F42_P_0_LEN_1,
1927   VEX_W_0F42_P_2_LEN_1,
1928   VEX_W_0F44_P_0_LEN_0,
1929   VEX_W_0F44_P_2_LEN_0,
1930   VEX_W_0F45_P_0_LEN_1,
1931   VEX_W_0F45_P_2_LEN_1,
1932   VEX_W_0F46_P_0_LEN_1,
1933   VEX_W_0F46_P_2_LEN_1,
1934   VEX_W_0F47_P_0_LEN_1,
1935   VEX_W_0F47_P_2_LEN_1,
1936   VEX_W_0F4A_P_0_LEN_1,
1937   VEX_W_0F4A_P_2_LEN_1,
1938   VEX_W_0F4B_P_0_LEN_1,
1939   VEX_W_0F4B_P_2_LEN_1,
1940   VEX_W_0F50_M_0,
1941   VEX_W_0F51_P_0,
1942   VEX_W_0F51_P_1,
1943   VEX_W_0F51_P_2,
1944   VEX_W_0F51_P_3,
1945   VEX_W_0F52_P_0,
1946   VEX_W_0F52_P_1,
1947   VEX_W_0F53_P_0,
1948   VEX_W_0F53_P_1,
1949   VEX_W_0F58_P_0,
1950   VEX_W_0F58_P_1,
1951   VEX_W_0F58_P_2,
1952   VEX_W_0F58_P_3,
1953   VEX_W_0F59_P_0,
1954   VEX_W_0F59_P_1,
1955   VEX_W_0F59_P_2,
1956   VEX_W_0F59_P_3,
1957   VEX_W_0F5A_P_0,
1958   VEX_W_0F5A_P_1,
1959   VEX_W_0F5A_P_3,
1960   VEX_W_0F5B_P_0,
1961   VEX_W_0F5B_P_1,
1962   VEX_W_0F5B_P_2,
1963   VEX_W_0F5C_P_0,
1964   VEX_W_0F5C_P_1,
1965   VEX_W_0F5C_P_2,
1966   VEX_W_0F5C_P_3,
1967   VEX_W_0F5D_P_0,
1968   VEX_W_0F5D_P_1,
1969   VEX_W_0F5D_P_2,
1970   VEX_W_0F5D_P_3,
1971   VEX_W_0F5E_P_0,
1972   VEX_W_0F5E_P_1,
1973   VEX_W_0F5E_P_2,
1974   VEX_W_0F5E_P_3,
1975   VEX_W_0F5F_P_0,
1976   VEX_W_0F5F_P_1,
1977   VEX_W_0F5F_P_2,
1978   VEX_W_0F5F_P_3,
1979   VEX_W_0F60_P_2,
1980   VEX_W_0F61_P_2,
1981   VEX_W_0F62_P_2,
1982   VEX_W_0F63_P_2,
1983   VEX_W_0F64_P_2,
1984   VEX_W_0F65_P_2,
1985   VEX_W_0F66_P_2,
1986   VEX_W_0F67_P_2,
1987   VEX_W_0F68_P_2,
1988   VEX_W_0F69_P_2,
1989   VEX_W_0F6A_P_2,
1990   VEX_W_0F6B_P_2,
1991   VEX_W_0F6C_P_2,
1992   VEX_W_0F6D_P_2,
1993   VEX_W_0F6F_P_1,
1994   VEX_W_0F6F_P_2,
1995   VEX_W_0F70_P_1,
1996   VEX_W_0F70_P_2,
1997   VEX_W_0F70_P_3,
1998   VEX_W_0F71_R_2_P_2,
1999   VEX_W_0F71_R_4_P_2,
2000   VEX_W_0F71_R_6_P_2,
2001   VEX_W_0F72_R_2_P_2,
2002   VEX_W_0F72_R_4_P_2,
2003   VEX_W_0F72_R_6_P_2,
2004   VEX_W_0F73_R_2_P_2,
2005   VEX_W_0F73_R_3_P_2,
2006   VEX_W_0F73_R_6_P_2,
2007   VEX_W_0F73_R_7_P_2,
2008   VEX_W_0F74_P_2,
2009   VEX_W_0F75_P_2,
2010   VEX_W_0F76_P_2,
2011   VEX_W_0F77_P_0,
2012   VEX_W_0F7C_P_2,
2013   VEX_W_0F7C_P_3,
2014   VEX_W_0F7D_P_2,
2015   VEX_W_0F7D_P_3,
2016   VEX_W_0F7E_P_1,
2017   VEX_W_0F7F_P_1,
2018   VEX_W_0F7F_P_2,
2019   VEX_W_0F90_P_0_LEN_0,
2020   VEX_W_0F90_P_2_LEN_0,
2021   VEX_W_0F91_P_0_LEN_0,
2022   VEX_W_0F91_P_2_LEN_0,
2023   VEX_W_0F92_P_0_LEN_0,
2024   VEX_W_0F92_P_2_LEN_0,
2025   VEX_W_0F92_P_3_LEN_0,
2026   VEX_W_0F93_P_0_LEN_0,
2027   VEX_W_0F93_P_2_LEN_0,
2028   VEX_W_0F93_P_3_LEN_0,
2029   VEX_W_0F98_P_0_LEN_0,
2030   VEX_W_0F98_P_2_LEN_0,
2031   VEX_W_0F99_P_0_LEN_0,
2032   VEX_W_0F99_P_2_LEN_0,
2033   VEX_W_0FAE_R_2_M_0,
2034   VEX_W_0FAE_R_3_M_0,
2035   VEX_W_0FC2_P_0,
2036   VEX_W_0FC2_P_1,
2037   VEX_W_0FC2_P_2,
2038   VEX_W_0FC2_P_3,
2039   VEX_W_0FC4_P_2,
2040   VEX_W_0FC5_P_2,
2041   VEX_W_0FD0_P_2,
2042   VEX_W_0FD0_P_3,
2043   VEX_W_0FD1_P_2,
2044   VEX_W_0FD2_P_2,
2045   VEX_W_0FD3_P_2,
2046   VEX_W_0FD4_P_2,
2047   VEX_W_0FD5_P_2,
2048   VEX_W_0FD6_P_2,
2049   VEX_W_0FD7_P_2_M_1,
2050   VEX_W_0FD8_P_2,
2051   VEX_W_0FD9_P_2,
2052   VEX_W_0FDA_P_2,
2053   VEX_W_0FDB_P_2,
2054   VEX_W_0FDC_P_2,
2055   VEX_W_0FDD_P_2,
2056   VEX_W_0FDE_P_2,
2057   VEX_W_0FDF_P_2,
2058   VEX_W_0FE0_P_2,
2059   VEX_W_0FE1_P_2,
2060   VEX_W_0FE2_P_2,
2061   VEX_W_0FE3_P_2,
2062   VEX_W_0FE4_P_2,
2063   VEX_W_0FE5_P_2,
2064   VEX_W_0FE6_P_1,
2065   VEX_W_0FE6_P_2,
2066   VEX_W_0FE6_P_3,
2067   VEX_W_0FE7_P_2_M_0,
2068   VEX_W_0FE8_P_2,
2069   VEX_W_0FE9_P_2,
2070   VEX_W_0FEA_P_2,
2071   VEX_W_0FEB_P_2,
2072   VEX_W_0FEC_P_2,
2073   VEX_W_0FED_P_2,
2074   VEX_W_0FEE_P_2,
2075   VEX_W_0FEF_P_2,
2076   VEX_W_0FF0_P_3_M_0,
2077   VEX_W_0FF1_P_2,
2078   VEX_W_0FF2_P_2,
2079   VEX_W_0FF3_P_2,
2080   VEX_W_0FF4_P_2,
2081   VEX_W_0FF5_P_2,
2082   VEX_W_0FF6_P_2,
2083   VEX_W_0FF7_P_2,
2084   VEX_W_0FF8_P_2,
2085   VEX_W_0FF9_P_2,
2086   VEX_W_0FFA_P_2,
2087   VEX_W_0FFB_P_2,
2088   VEX_W_0FFC_P_2,
2089   VEX_W_0FFD_P_2,
2090   VEX_W_0FFE_P_2,
2091   VEX_W_0F3800_P_2,
2092   VEX_W_0F3801_P_2,
2093   VEX_W_0F3802_P_2,
2094   VEX_W_0F3803_P_2,
2095   VEX_W_0F3804_P_2,
2096   VEX_W_0F3805_P_2,
2097   VEX_W_0F3806_P_2,
2098   VEX_W_0F3807_P_2,
2099   VEX_W_0F3808_P_2,
2100   VEX_W_0F3809_P_2,
2101   VEX_W_0F380A_P_2,
2102   VEX_W_0F380B_P_2,
2103   VEX_W_0F380C_P_2,
2104   VEX_W_0F380D_P_2,
2105   VEX_W_0F380E_P_2,
2106   VEX_W_0F380F_P_2,
2107   VEX_W_0F3816_P_2,
2108   VEX_W_0F3817_P_2,
2109   VEX_W_0F3818_P_2,
2110   VEX_W_0F3819_P_2,
2111   VEX_W_0F381A_P_2_M_0,
2112   VEX_W_0F381C_P_2,
2113   VEX_W_0F381D_P_2,
2114   VEX_W_0F381E_P_2,
2115   VEX_W_0F3820_P_2,
2116   VEX_W_0F3821_P_2,
2117   VEX_W_0F3822_P_2,
2118   VEX_W_0F3823_P_2,
2119   VEX_W_0F3824_P_2,
2120   VEX_W_0F3825_P_2,
2121   VEX_W_0F3828_P_2,
2122   VEX_W_0F3829_P_2,
2123   VEX_W_0F382A_P_2_M_0,
2124   VEX_W_0F382B_P_2,
2125   VEX_W_0F382C_P_2_M_0,
2126   VEX_W_0F382D_P_2_M_0,
2127   VEX_W_0F382E_P_2_M_0,
2128   VEX_W_0F382F_P_2_M_0,
2129   VEX_W_0F3830_P_2,
2130   VEX_W_0F3831_P_2,
2131   VEX_W_0F3832_P_2,
2132   VEX_W_0F3833_P_2,
2133   VEX_W_0F3834_P_2,
2134   VEX_W_0F3835_P_2,
2135   VEX_W_0F3836_P_2,
2136   VEX_W_0F3837_P_2,
2137   VEX_W_0F3838_P_2,
2138   VEX_W_0F3839_P_2,
2139   VEX_W_0F383A_P_2,
2140   VEX_W_0F383B_P_2,
2141   VEX_W_0F383C_P_2,
2142   VEX_W_0F383D_P_2,
2143   VEX_W_0F383E_P_2,
2144   VEX_W_0F383F_P_2,
2145   VEX_W_0F3840_P_2,
2146   VEX_W_0F3841_P_2,
2147   VEX_W_0F3846_P_2,
2148   VEX_W_0F3858_P_2,
2149   VEX_W_0F3859_P_2,
2150   VEX_W_0F385A_P_2_M_0,
2151   VEX_W_0F3878_P_2,
2152   VEX_W_0F3879_P_2,
2153   VEX_W_0F38DB_P_2,
2154   VEX_W_0F38DC_P_2,
2155   VEX_W_0F38DD_P_2,
2156   VEX_W_0F38DE_P_2,
2157   VEX_W_0F38DF_P_2,
2158   VEX_W_0F3A00_P_2,
2159   VEX_W_0F3A01_P_2,
2160   VEX_W_0F3A02_P_2,
2161   VEX_W_0F3A04_P_2,
2162   VEX_W_0F3A05_P_2,
2163   VEX_W_0F3A06_P_2,
2164   VEX_W_0F3A08_P_2,
2165   VEX_W_0F3A09_P_2,
2166   VEX_W_0F3A0A_P_2,
2167   VEX_W_0F3A0B_P_2,
2168   VEX_W_0F3A0C_P_2,
2169   VEX_W_0F3A0D_P_2,
2170   VEX_W_0F3A0E_P_2,
2171   VEX_W_0F3A0F_P_2,
2172   VEX_W_0F3A14_P_2,
2173   VEX_W_0F3A15_P_2,
2174   VEX_W_0F3A18_P_2,
2175   VEX_W_0F3A19_P_2,
2176   VEX_W_0F3A20_P_2,
2177   VEX_W_0F3A21_P_2,
2178   VEX_W_0F3A30_P_2_LEN_0,
2179   VEX_W_0F3A31_P_2_LEN_0,
2180   VEX_W_0F3A32_P_2_LEN_0,
2181   VEX_W_0F3A33_P_2_LEN_0,
2182   VEX_W_0F3A38_P_2,
2183   VEX_W_0F3A39_P_2,
2184   VEX_W_0F3A40_P_2,
2185   VEX_W_0F3A41_P_2,
2186   VEX_W_0F3A42_P_2,
2187   VEX_W_0F3A44_P_2,
2188   VEX_W_0F3A46_P_2,
2189   VEX_W_0F3A48_P_2,
2190   VEX_W_0F3A49_P_2,
2191   VEX_W_0F3A4A_P_2,
2192   VEX_W_0F3A4B_P_2,
2193   VEX_W_0F3A4C_P_2,
2194   VEX_W_0F3A60_P_2,
2195   VEX_W_0F3A61_P_2,
2196   VEX_W_0F3A62_P_2,
2197   VEX_W_0F3A63_P_2,
2198   VEX_W_0F3ADF_P_2,
2199
2200   EVEX_W_0F10_P_0,
2201   EVEX_W_0F10_P_1_M_0,
2202   EVEX_W_0F10_P_1_M_1,
2203   EVEX_W_0F10_P_2,
2204   EVEX_W_0F10_P_3_M_0,
2205   EVEX_W_0F10_P_3_M_1,
2206   EVEX_W_0F11_P_0,
2207   EVEX_W_0F11_P_1_M_0,
2208   EVEX_W_0F11_P_1_M_1,
2209   EVEX_W_0F11_P_2,
2210   EVEX_W_0F11_P_3_M_0,
2211   EVEX_W_0F11_P_3_M_1,
2212   EVEX_W_0F12_P_0_M_0,
2213   EVEX_W_0F12_P_0_M_1,
2214   EVEX_W_0F12_P_1,
2215   EVEX_W_0F12_P_2,
2216   EVEX_W_0F12_P_3,
2217   EVEX_W_0F13_P_0,
2218   EVEX_W_0F13_P_2,
2219   EVEX_W_0F14_P_0,
2220   EVEX_W_0F14_P_2,
2221   EVEX_W_0F15_P_0,
2222   EVEX_W_0F15_P_2,
2223   EVEX_W_0F16_P_0_M_0,
2224   EVEX_W_0F16_P_0_M_1,
2225   EVEX_W_0F16_P_1,
2226   EVEX_W_0F16_P_2,
2227   EVEX_W_0F17_P_0,
2228   EVEX_W_0F17_P_2,
2229   EVEX_W_0F28_P_0,
2230   EVEX_W_0F28_P_2,
2231   EVEX_W_0F29_P_0,
2232   EVEX_W_0F29_P_2,
2233   EVEX_W_0F2A_P_1,
2234   EVEX_W_0F2A_P_3,
2235   EVEX_W_0F2B_P_0,
2236   EVEX_W_0F2B_P_2,
2237   EVEX_W_0F2E_P_0,
2238   EVEX_W_0F2E_P_2,
2239   EVEX_W_0F2F_P_0,
2240   EVEX_W_0F2F_P_2,
2241   EVEX_W_0F51_P_0,
2242   EVEX_W_0F51_P_1,
2243   EVEX_W_0F51_P_2,
2244   EVEX_W_0F51_P_3,
2245   EVEX_W_0F54_P_0,
2246   EVEX_W_0F54_P_2,
2247   EVEX_W_0F55_P_0,
2248   EVEX_W_0F55_P_2,
2249   EVEX_W_0F56_P_0,
2250   EVEX_W_0F56_P_2,
2251   EVEX_W_0F57_P_0,
2252   EVEX_W_0F57_P_2,
2253   EVEX_W_0F58_P_0,
2254   EVEX_W_0F58_P_1,
2255   EVEX_W_0F58_P_2,
2256   EVEX_W_0F58_P_3,
2257   EVEX_W_0F59_P_0,
2258   EVEX_W_0F59_P_1,
2259   EVEX_W_0F59_P_2,
2260   EVEX_W_0F59_P_3,
2261   EVEX_W_0F5A_P_0,
2262   EVEX_W_0F5A_P_1,
2263   EVEX_W_0F5A_P_2,
2264   EVEX_W_0F5A_P_3,
2265   EVEX_W_0F5B_P_0,
2266   EVEX_W_0F5B_P_1,
2267   EVEX_W_0F5B_P_2,
2268   EVEX_W_0F5C_P_0,
2269   EVEX_W_0F5C_P_1,
2270   EVEX_W_0F5C_P_2,
2271   EVEX_W_0F5C_P_3,
2272   EVEX_W_0F5D_P_0,
2273   EVEX_W_0F5D_P_1,
2274   EVEX_W_0F5D_P_2,
2275   EVEX_W_0F5D_P_3,
2276   EVEX_W_0F5E_P_0,
2277   EVEX_W_0F5E_P_1,
2278   EVEX_W_0F5E_P_2,
2279   EVEX_W_0F5E_P_3,
2280   EVEX_W_0F5F_P_0,
2281   EVEX_W_0F5F_P_1,
2282   EVEX_W_0F5F_P_2,
2283   EVEX_W_0F5F_P_3,
2284   EVEX_W_0F62_P_2,
2285   EVEX_W_0F66_P_2,
2286   EVEX_W_0F6A_P_2,
2287   EVEX_W_0F6B_P_2,
2288   EVEX_W_0F6C_P_2,
2289   EVEX_W_0F6D_P_2,
2290   EVEX_W_0F6E_P_2,
2291   EVEX_W_0F6F_P_1,
2292   EVEX_W_0F6F_P_2,
2293   EVEX_W_0F6F_P_3,
2294   EVEX_W_0F70_P_2,
2295   EVEX_W_0F72_R_2_P_2,
2296   EVEX_W_0F72_R_6_P_2,
2297   EVEX_W_0F73_R_2_P_2,
2298   EVEX_W_0F73_R_6_P_2,
2299   EVEX_W_0F76_P_2,
2300   EVEX_W_0F78_P_0,
2301   EVEX_W_0F78_P_2,
2302   EVEX_W_0F79_P_0,
2303   EVEX_W_0F79_P_2,
2304   EVEX_W_0F7A_P_1,
2305   EVEX_W_0F7A_P_2,
2306   EVEX_W_0F7A_P_3,
2307   EVEX_W_0F7B_P_1,
2308   EVEX_W_0F7B_P_2,
2309   EVEX_W_0F7B_P_3,
2310   EVEX_W_0F7E_P_1,
2311   EVEX_W_0F7E_P_2,
2312   EVEX_W_0F7F_P_1,
2313   EVEX_W_0F7F_P_2,
2314   EVEX_W_0F7F_P_3,
2315   EVEX_W_0FC2_P_0,
2316   EVEX_W_0FC2_P_1,
2317   EVEX_W_0FC2_P_2,
2318   EVEX_W_0FC2_P_3,
2319   EVEX_W_0FC6_P_0,
2320   EVEX_W_0FC6_P_2,
2321   EVEX_W_0FD2_P_2,
2322   EVEX_W_0FD3_P_2,
2323   EVEX_W_0FD4_P_2,
2324   EVEX_W_0FD6_P_2,
2325   EVEX_W_0FE6_P_1,
2326   EVEX_W_0FE6_P_2,
2327   EVEX_W_0FE6_P_3,
2328   EVEX_W_0FE7_P_2,
2329   EVEX_W_0FF2_P_2,
2330   EVEX_W_0FF3_P_2,
2331   EVEX_W_0FF4_P_2,
2332   EVEX_W_0FFA_P_2,
2333   EVEX_W_0FFB_P_2,
2334   EVEX_W_0FFE_P_2,
2335   EVEX_W_0F380C_P_2,
2336   EVEX_W_0F380D_P_2,
2337   EVEX_W_0F3810_P_1,
2338   EVEX_W_0F3810_P_2,
2339   EVEX_W_0F3811_P_1,
2340   EVEX_W_0F3811_P_2,
2341   EVEX_W_0F3812_P_1,
2342   EVEX_W_0F3812_P_2,
2343   EVEX_W_0F3813_P_1,
2344   EVEX_W_0F3813_P_2,
2345   EVEX_W_0F3814_P_1,
2346   EVEX_W_0F3815_P_1,
2347   EVEX_W_0F3818_P_2,
2348   EVEX_W_0F3819_P_2,
2349   EVEX_W_0F381A_P_2,
2350   EVEX_W_0F381B_P_2,
2351   EVEX_W_0F381E_P_2,
2352   EVEX_W_0F381F_P_2,
2353   EVEX_W_0F3820_P_1,
2354   EVEX_W_0F3821_P_1,
2355   EVEX_W_0F3822_P_1,
2356   EVEX_W_0F3823_P_1,
2357   EVEX_W_0F3824_P_1,
2358   EVEX_W_0F3825_P_1,
2359   EVEX_W_0F3825_P_2,
2360   EVEX_W_0F3826_P_1,
2361   EVEX_W_0F3826_P_2,
2362   EVEX_W_0F3828_P_1,
2363   EVEX_W_0F3828_P_2,
2364   EVEX_W_0F3829_P_1,
2365   EVEX_W_0F3829_P_2,
2366   EVEX_W_0F382A_P_1,
2367   EVEX_W_0F382A_P_2,
2368   EVEX_W_0F382B_P_2,
2369   EVEX_W_0F3830_P_1,
2370   EVEX_W_0F3831_P_1,
2371   EVEX_W_0F3832_P_1,
2372   EVEX_W_0F3833_P_1,
2373   EVEX_W_0F3834_P_1,
2374   EVEX_W_0F3835_P_1,
2375   EVEX_W_0F3835_P_2,
2376   EVEX_W_0F3837_P_2,
2377   EVEX_W_0F3838_P_1,
2378   EVEX_W_0F3839_P_1,
2379   EVEX_W_0F383A_P_1,
2380   EVEX_W_0F3840_P_2,
2381   EVEX_W_0F3858_P_2,
2382   EVEX_W_0F3859_P_2,
2383   EVEX_W_0F385A_P_2,
2384   EVEX_W_0F385B_P_2,
2385   EVEX_W_0F3866_P_2,
2386   EVEX_W_0F3875_P_2,
2387   EVEX_W_0F3878_P_2,
2388   EVEX_W_0F3879_P_2,
2389   EVEX_W_0F387A_P_2,
2390   EVEX_W_0F387B_P_2,
2391   EVEX_W_0F387D_P_2,
2392   EVEX_W_0F3883_P_2,
2393   EVEX_W_0F388D_P_2,
2394   EVEX_W_0F3891_P_2,
2395   EVEX_W_0F3893_P_2,
2396   EVEX_W_0F38A1_P_2,
2397   EVEX_W_0F38A3_P_2,
2398   EVEX_W_0F38C7_R_1_P_2,
2399   EVEX_W_0F38C7_R_2_P_2,
2400   EVEX_W_0F38C7_R_5_P_2,
2401   EVEX_W_0F38C7_R_6_P_2,
2402
2403   EVEX_W_0F3A00_P_2,
2404   EVEX_W_0F3A01_P_2,
2405   EVEX_W_0F3A04_P_2,
2406   EVEX_W_0F3A05_P_2,
2407   EVEX_W_0F3A08_P_2,
2408   EVEX_W_0F3A09_P_2,
2409   EVEX_W_0F3A0A_P_2,
2410   EVEX_W_0F3A0B_P_2,
2411   EVEX_W_0F3A16_P_2,
2412   EVEX_W_0F3A18_P_2,
2413   EVEX_W_0F3A19_P_2,
2414   EVEX_W_0F3A1A_P_2,
2415   EVEX_W_0F3A1B_P_2,
2416   EVEX_W_0F3A1D_P_2,
2417   EVEX_W_0F3A21_P_2,
2418   EVEX_W_0F3A22_P_2,
2419   EVEX_W_0F3A23_P_2,
2420   EVEX_W_0F3A38_P_2,
2421   EVEX_W_0F3A39_P_2,
2422   EVEX_W_0F3A3A_P_2,
2423   EVEX_W_0F3A3B_P_2,
2424   EVEX_W_0F3A3E_P_2,
2425   EVEX_W_0F3A3F_P_2,
2426   EVEX_W_0F3A42_P_2,
2427   EVEX_W_0F3A43_P_2,
2428   EVEX_W_0F3A50_P_2,
2429   EVEX_W_0F3A51_P_2,
2430   EVEX_W_0F3A56_P_2,
2431   EVEX_W_0F3A57_P_2,
2432   EVEX_W_0F3A66_P_2,
2433   EVEX_W_0F3A67_P_2
2434 };
2435
2436 typedef void (*op_rtn) (int bytemode, int sizeflag);
2437
2438 struct dis386 {
2439   const char *name;
2440   struct
2441     {
2442       op_rtn rtn;
2443       int bytemode;
2444     } op[MAX_OPERANDS];
2445   unsigned int prefix_requirement;
2446 };
2447
2448 /* Upper case letters in the instruction names here are macros.
2449    'A' => print 'b' if no register operands or suffix_always is true
2450    'B' => print 'b' if suffix_always is true
2451    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2452           size prefix
2453    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2454           suffix_always is true
2455    'E' => print 'e' if 32-bit form of jcxz
2456    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2457    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2458    'H' => print ",pt" or ",pn" branch hint
2459    'I' => honor following macro letter even in Intel mode (implemented only
2460           for some of the macro letters)
2461    'J' => print 'l'
2462    'K' => print 'd' or 'q' if rex prefix is present.
2463    'L' => print 'l' if suffix_always is true
2464    'M' => print 'r' if intel_mnemonic is false.
2465    'N' => print 'n' if instruction has no wait "prefix"
2466    'O' => print 'd' or 'o' (or 'q' in Intel mode)
2467    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2468           or suffix_always is true.  print 'q' if rex prefix is present.
2469    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2470           is true
2471    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2472    'S' => print 'w', 'l' or 'q' if suffix_always is true
2473    'T' => print 'q' in 64bit mode if instruction has no operand size
2474           prefix and behave as 'P' otherwise
2475    'U' => print 'q' in 64bit mode if instruction has no operand size
2476           prefix and behave as 'Q' otherwise
2477    'V' => print 'q' in 64bit mode if instruction has no operand size
2478           prefix and behave as 'S' otherwise
2479    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2480    'X' => print 's', 'd' depending on data16 prefix (for XMM)
2481    'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
2482           suffix_always is true.
2483    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2484    '!' => change condition from true to false or from false to true.
2485    '%' => add 1 upper case letter to the macro.
2486    '^' => print 'w' or 'l' depending on operand size prefix or
2487           suffix_always is true (lcall/ljmp).
2488    '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2489           on operand size prefix.
2490    '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2491           has no operand size prefix for AMD64 ISA, behave as 'P'
2492           otherwise
2493
2494    2 upper case letter macros:
2495    "XY" => print 'x' or 'y' if suffix_always is true or no register
2496            operands and no broadcast.
2497    "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2498            register operands and no broadcast.
2499    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2500    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2501            or suffix_always is true
2502    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2503    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2504    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2505    "LW" => print 'd', 'q' depending on the VEX.W bit
2506    "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2507            an operand size prefix, or suffix_always is true.  print
2508            'q' if rex prefix is present.
2509
2510    Many of the above letters print nothing in Intel mode.  See "putop"
2511    for the details.
2512
2513    Braces '{' and '}', and vertical bars '|', indicate alternative
2514    mnemonic strings for AT&T and Intel.  */
2515
2516 static const struct dis386 dis386[] = {
2517   /* 00 */
2518   { "addB",             { Ebh1, Gb }, 0 },
2519   { "addS",             { Evh1, Gv }, 0 },
2520   { "addB",             { Gb, EbS }, 0 },
2521   { "addS",             { Gv, EvS }, 0 },
2522   { "addB",             { AL, Ib }, 0 },
2523   { "addS",             { eAX, Iv }, 0 },
2524   { X86_64_TABLE (X86_64_06) },
2525   { X86_64_TABLE (X86_64_07) },
2526   /* 08 */
2527   { "orB",              { Ebh1, Gb }, 0 },
2528   { "orS",              { Evh1, Gv }, 0 },
2529   { "orB",              { Gb, EbS }, 0 },
2530   { "orS",              { Gv, EvS }, 0 },
2531   { "orB",              { AL, Ib }, 0 },
2532   { "orS",              { eAX, Iv }, 0 },
2533   { X86_64_TABLE (X86_64_0D) },
2534   { Bad_Opcode },       /* 0x0f extended opcode escape */
2535   /* 10 */
2536   { "adcB",             { Ebh1, Gb }, 0 },
2537   { "adcS",             { Evh1, Gv }, 0 },
2538   { "adcB",             { Gb, EbS }, 0 },
2539   { "adcS",             { Gv, EvS }, 0 },
2540   { "adcB",             { AL, Ib }, 0 },
2541   { "adcS",             { eAX, Iv }, 0 },
2542   { X86_64_TABLE (X86_64_16) },
2543   { X86_64_TABLE (X86_64_17) },
2544   /* 18 */
2545   { "sbbB",             { Ebh1, Gb }, 0 },
2546   { "sbbS",             { Evh1, Gv }, 0 },
2547   { "sbbB",             { Gb, EbS }, 0 },
2548   { "sbbS",             { Gv, EvS }, 0 },
2549   { "sbbB",             { AL, Ib }, 0 },
2550   { "sbbS",             { eAX, Iv }, 0 },
2551   { X86_64_TABLE (X86_64_1E) },
2552   { X86_64_TABLE (X86_64_1F) },
2553   /* 20 */
2554   { "andB",             { Ebh1, Gb }, 0 },
2555   { "andS",             { Evh1, Gv }, 0 },
2556   { "andB",             { Gb, EbS }, 0 },
2557   { "andS",             { Gv, EvS }, 0 },
2558   { "andB",             { AL, Ib }, 0 },
2559   { "andS",             { eAX, Iv }, 0 },
2560   { Bad_Opcode },       /* SEG ES prefix */
2561   { X86_64_TABLE (X86_64_27) },
2562   /* 28 */
2563   { "subB",             { Ebh1, Gb }, 0 },
2564   { "subS",             { Evh1, Gv }, 0 },
2565   { "subB",             { Gb, EbS }, 0 },
2566   { "subS",             { Gv, EvS }, 0 },
2567   { "subB",             { AL, Ib }, 0 },
2568   { "subS",             { eAX, Iv }, 0 },
2569   { Bad_Opcode },       /* SEG CS prefix */
2570   { X86_64_TABLE (X86_64_2F) },
2571   /* 30 */
2572   { "xorB",             { Ebh1, Gb }, 0 },
2573   { "xorS",             { Evh1, Gv }, 0 },
2574   { "xorB",             { Gb, EbS }, 0 },
2575   { "xorS",             { Gv, EvS }, 0 },
2576   { "xorB",             { AL, Ib }, 0 },
2577   { "xorS",             { eAX, Iv }, 0 },
2578   { Bad_Opcode },       /* SEG SS prefix */
2579   { X86_64_TABLE (X86_64_37) },
2580   /* 38 */
2581   { "cmpB",             { Eb, Gb }, 0 },
2582   { "cmpS",             { Ev, Gv }, 0 },
2583   { "cmpB",             { Gb, EbS }, 0 },
2584   { "cmpS",             { Gv, EvS }, 0 },
2585   { "cmpB",             { AL, Ib }, 0 },
2586   { "cmpS",             { eAX, Iv }, 0 },
2587   { Bad_Opcode },       /* SEG DS prefix */
2588   { X86_64_TABLE (X86_64_3F) },
2589   /* 40 */
2590   { "inc{S|}",          { RMeAX }, 0 },
2591   { "inc{S|}",          { RMeCX }, 0 },
2592   { "inc{S|}",          { RMeDX }, 0 },
2593   { "inc{S|}",          { RMeBX }, 0 },
2594   { "inc{S|}",          { RMeSP }, 0 },
2595   { "inc{S|}",          { RMeBP }, 0 },
2596   { "inc{S|}",          { RMeSI }, 0 },
2597   { "inc{S|}",          { RMeDI }, 0 },
2598   /* 48 */
2599   { "dec{S|}",          { RMeAX }, 0 },
2600   { "dec{S|}",          { RMeCX }, 0 },
2601   { "dec{S|}",          { RMeDX }, 0 },
2602   { "dec{S|}",          { RMeBX }, 0 },
2603   { "dec{S|}",          { RMeSP }, 0 },
2604   { "dec{S|}",          { RMeBP }, 0 },
2605   { "dec{S|}",          { RMeSI }, 0 },
2606   { "dec{S|}",          { RMeDI }, 0 },
2607   /* 50 */
2608   { "pushV",            { RMrAX }, 0 },
2609   { "pushV",            { RMrCX }, 0 },
2610   { "pushV",            { RMrDX }, 0 },
2611   { "pushV",            { RMrBX }, 0 },
2612   { "pushV",            { RMrSP }, 0 },
2613   { "pushV",            { RMrBP }, 0 },
2614   { "pushV",            { RMrSI }, 0 },
2615   { "pushV",            { RMrDI }, 0 },
2616   /* 58 */
2617   { "popV",             { RMrAX }, 0 },
2618   { "popV",             { RMrCX }, 0 },
2619   { "popV",             { RMrDX }, 0 },
2620   { "popV",             { RMrBX }, 0 },
2621   { "popV",             { RMrSP }, 0 },
2622   { "popV",             { RMrBP }, 0 },
2623   { "popV",             { RMrSI }, 0 },
2624   { "popV",             { RMrDI }, 0 },
2625   /* 60 */
2626   { X86_64_TABLE (X86_64_60) },
2627   { X86_64_TABLE (X86_64_61) },
2628   { X86_64_TABLE (X86_64_62) },
2629   { X86_64_TABLE (X86_64_63) },
2630   { Bad_Opcode },       /* seg fs */
2631   { Bad_Opcode },       /* seg gs */
2632   { Bad_Opcode },       /* op size prefix */
2633   { Bad_Opcode },       /* adr size prefix */
2634   /* 68 */
2635   { "pushT",            { sIv }, 0 },
2636   { "imulS",            { Gv, Ev, Iv }, 0 },
2637   { "pushT",            { sIbT }, 0 },
2638   { "imulS",            { Gv, Ev, sIb }, 0 },
2639   { "ins{b|}",          { Ybr, indirDX }, 0 },
2640   { X86_64_TABLE (X86_64_6D) },
2641   { "outs{b|}",         { indirDXr, Xb }, 0 },
2642   { X86_64_TABLE (X86_64_6F) },
2643   /* 70 */
2644   { "joH",              { Jb, BND, cond_jump_flag }, 0 },
2645   { "jnoH",             { Jb, BND, cond_jump_flag }, 0 },
2646   { "jbH",              { Jb, BND, cond_jump_flag }, 0 },
2647   { "jaeH",             { Jb, BND, cond_jump_flag }, 0 },
2648   { "jeH",              { Jb, BND, cond_jump_flag }, 0 },
2649   { "jneH",             { Jb, BND, cond_jump_flag }, 0 },
2650   { "jbeH",             { Jb, BND, cond_jump_flag }, 0 },
2651   { "jaH",              { Jb, BND, cond_jump_flag }, 0 },
2652   /* 78 */
2653   { "jsH",              { Jb, BND, cond_jump_flag }, 0 },
2654   { "jnsH",             { Jb, BND, cond_jump_flag }, 0 },
2655   { "jpH",              { Jb, BND, cond_jump_flag }, 0 },
2656   { "jnpH",             { Jb, BND, cond_jump_flag }, 0 },
2657   { "jlH",              { Jb, BND, cond_jump_flag }, 0 },
2658   { "jgeH",             { Jb, BND, cond_jump_flag }, 0 },
2659   { "jleH",             { Jb, BND, cond_jump_flag }, 0 },
2660   { "jgH",              { Jb, BND, cond_jump_flag }, 0 },
2661   /* 80 */
2662   { REG_TABLE (REG_80) },
2663   { REG_TABLE (REG_81) },
2664   { Bad_Opcode },
2665   { REG_TABLE (REG_82) },
2666   { "testB",            { Eb, Gb }, 0 },
2667   { "testS",            { Ev, Gv }, 0 },
2668   { "xchgB",            { Ebh2, Gb }, 0 },
2669   { "xchgS",            { Evh2, Gv }, 0 },
2670   /* 88 */
2671   { "movB",             { Ebh3, Gb }, 0 },
2672   { "movS",             { Evh3, Gv }, 0 },
2673   { "movB",             { Gb, EbS }, 0 },
2674   { "movS",             { Gv, EvS }, 0 },
2675   { "movD",             { Sv, Sw }, 0 },
2676   { MOD_TABLE (MOD_8D) },
2677   { "movD",             { Sw, Sv }, 0 },
2678   { REG_TABLE (REG_8F) },
2679   /* 90 */
2680   { PREFIX_TABLE (PREFIX_90) },
2681   { "xchgS",            { RMeCX, eAX }, 0 },
2682   { "xchgS",            { RMeDX, eAX }, 0 },
2683   { "xchgS",            { RMeBX, eAX }, 0 },
2684   { "xchgS",            { RMeSP, eAX }, 0 },
2685   { "xchgS",            { RMeBP, eAX }, 0 },
2686   { "xchgS",            { RMeSI, eAX }, 0 },
2687   { "xchgS",            { RMeDI, eAX }, 0 },
2688   /* 98 */
2689   { "cW{t|}R",          { XX }, 0 },
2690   { "cR{t|}O",          { XX }, 0 },
2691   { X86_64_TABLE (X86_64_9A) },
2692   { Bad_Opcode },       /* fwait */
2693   { "pushfT",           { XX }, 0 },
2694   { "popfT",            { XX }, 0 },
2695   { "sahf",             { XX }, 0 },
2696   { "lahf",             { XX }, 0 },
2697   /* a0 */
2698   { "mov%LB",           { AL, Ob }, 0 },
2699   { "mov%LS",           { eAX, Ov }, 0 },
2700   { "mov%LB",           { Ob, AL }, 0 },
2701   { "mov%LS",           { Ov, eAX }, 0 },
2702   { "movs{b|}",         { Ybr, Xb }, 0 },
2703   { "movs{R|}",         { Yvr, Xv }, 0 },
2704   { "cmps{b|}",         { Xb, Yb }, 0 },
2705   { "cmps{R|}",         { Xv, Yv }, 0 },
2706   /* a8 */
2707   { "testB",            { AL, Ib }, 0 },
2708   { "testS",            { eAX, Iv }, 0 },
2709   { "stosB",            { Ybr, AL }, 0 },
2710   { "stosS",            { Yvr, eAX }, 0 },
2711   { "lodsB",            { ALr, Xb }, 0 },
2712   { "lodsS",            { eAXr, Xv }, 0 },
2713   { "scasB",            { AL, Yb }, 0 },
2714   { "scasS",            { eAX, Yv }, 0 },
2715   /* b0 */
2716   { "movB",             { RMAL, Ib }, 0 },
2717   { "movB",             { RMCL, Ib }, 0 },
2718   { "movB",             { RMDL, Ib }, 0 },
2719   { "movB",             { RMBL, Ib }, 0 },
2720   { "movB",             { RMAH, Ib }, 0 },
2721   { "movB",             { RMCH, Ib }, 0 },
2722   { "movB",             { RMDH, Ib }, 0 },
2723   { "movB",             { RMBH, Ib }, 0 },
2724   /* b8 */
2725   { "mov%LV",           { RMeAX, Iv64 }, 0 },
2726   { "mov%LV",           { RMeCX, Iv64 }, 0 },
2727   { "mov%LV",           { RMeDX, Iv64 }, 0 },
2728   { "mov%LV",           { RMeBX, Iv64 }, 0 },
2729   { "mov%LV",           { RMeSP, Iv64 }, 0 },
2730   { "mov%LV",           { RMeBP, Iv64 }, 0 },
2731   { "mov%LV",           { RMeSI, Iv64 }, 0 },
2732   { "mov%LV",           { RMeDI, Iv64 }, 0 },
2733   /* c0 */
2734   { REG_TABLE (REG_C0) },
2735   { REG_TABLE (REG_C1) },
2736   { "retT",             { Iw, BND }, 0 },
2737   { "retT",             { BND }, 0 },
2738   { X86_64_TABLE (X86_64_C4) },
2739   { X86_64_TABLE (X86_64_C5) },
2740   { REG_TABLE (REG_C6) },
2741   { REG_TABLE (REG_C7) },
2742   /* c8 */
2743   { "enterT",           { Iw, Ib }, 0 },
2744   { "leaveT",           { XX }, 0 },
2745   { "Jret{|f}P",        { Iw }, 0 },
2746   { "Jret{|f}P",        { XX }, 0 },
2747   { "int3",             { XX }, 0 },
2748   { "int",              { Ib }, 0 },
2749   { X86_64_TABLE (X86_64_CE) },
2750   { "iret%LP",          { XX }, 0 },
2751   /* d0 */
2752   { REG_TABLE (REG_D0) },
2753   { REG_TABLE (REG_D1) },
2754   { REG_TABLE (REG_D2) },
2755   { REG_TABLE (REG_D3) },
2756   { X86_64_TABLE (X86_64_D4) },
2757   { X86_64_TABLE (X86_64_D5) },
2758   { Bad_Opcode },
2759   { "xlat",             { DSBX }, 0 },
2760   /* d8 */
2761   { FLOAT },
2762   { FLOAT },
2763   { FLOAT },
2764   { FLOAT },
2765   { FLOAT },
2766   { FLOAT },
2767   { FLOAT },
2768   { FLOAT },
2769   /* e0 */
2770   { "loopneFH",         { Jb, XX, loop_jcxz_flag }, 0 },
2771   { "loopeFH",          { Jb, XX, loop_jcxz_flag }, 0 },
2772   { "loopFH",           { Jb, XX, loop_jcxz_flag }, 0 },
2773   { "jEcxzH",           { Jb, XX, loop_jcxz_flag }, 0 },
2774   { "inB",              { AL, Ib }, 0 },
2775   { "inG",              { zAX, Ib }, 0 },
2776   { "outB",             { Ib, AL }, 0 },
2777   { "outG",             { Ib, zAX }, 0 },
2778   /* e8 */
2779   { X86_64_TABLE (X86_64_E8) },
2780   { X86_64_TABLE (X86_64_E9) },
2781   { X86_64_TABLE (X86_64_EA) },
2782   { "jmp",              { Jb, BND }, 0 },
2783   { "inB",              { AL, indirDX }, 0 },
2784   { "inG",              { zAX, indirDX }, 0 },
2785   { "outB",             { indirDX, AL }, 0 },
2786   { "outG",             { indirDX, zAX }, 0 },
2787   /* f0 */
2788   { Bad_Opcode },       /* lock prefix */
2789   { "icebp",            { XX }, 0 },
2790   { Bad_Opcode },       /* repne */
2791   { Bad_Opcode },       /* repz */
2792   { "hlt",              { XX }, 0 },
2793   { "cmc",              { XX }, 0 },
2794   { REG_TABLE (REG_F6) },
2795   { REG_TABLE (REG_F7) },
2796   /* f8 */
2797   { "clc",              { XX }, 0 },
2798   { "stc",              { XX }, 0 },
2799   { "cli",              { XX }, 0 },
2800   { "sti",              { XX }, 0 },
2801   { "cld",              { XX }, 0 },
2802   { "std",              { XX }, 0 },
2803   { REG_TABLE (REG_FE) },
2804   { REG_TABLE (REG_FF) },
2805 };
2806
2807 static const struct dis386 dis386_twobyte[] = {
2808   /* 00 */
2809   { REG_TABLE (REG_0F00 ) },
2810   { REG_TABLE (REG_0F01 ) },
2811   { "larS",             { Gv, Ew }, 0 },
2812   { "lslS",             { Gv, Ew }, 0 },
2813   { Bad_Opcode },
2814   { "syscall",          { XX }, 0 },
2815   { "clts",             { XX }, 0 },
2816   { "sysret%LP",                { XX }, 0 },
2817   /* 08 */
2818   { "invd",             { XX }, 0 },
2819   { "wbinvd",           { XX }, 0 },
2820   { Bad_Opcode },
2821   { "ud2",              { XX }, 0 },
2822   { Bad_Opcode },
2823   { REG_TABLE (REG_0F0D) },
2824   { "femms",            { XX }, 0 },
2825   { "",                 { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix.  */
2826   /* 10 */
2827   { PREFIX_TABLE (PREFIX_0F10) },
2828   { PREFIX_TABLE (PREFIX_0F11) },
2829   { PREFIX_TABLE (PREFIX_0F12) },
2830   { MOD_TABLE (MOD_0F13) },
2831   { "unpcklpX",         { XM, EXx }, PREFIX_OPCODE },
2832   { "unpckhpX",         { XM, EXx }, PREFIX_OPCODE },
2833   { PREFIX_TABLE (PREFIX_0F16) },
2834   { MOD_TABLE (MOD_0F17) },
2835   /* 18 */
2836   { REG_TABLE (REG_0F18) },
2837   { "nopQ",             { Ev }, 0 },
2838   { PREFIX_TABLE (PREFIX_0F1A) },
2839   { PREFIX_TABLE (PREFIX_0F1B) },
2840   { "nopQ",             { Ev }, 0 },
2841   { "nopQ",             { Ev }, 0 },
2842   { "nopQ",             { Ev }, 0 },
2843   { "nopQ",             { Ev }, 0 },
2844   /* 20 */
2845   { "movZ",             { Rm, Cm }, 0 },
2846   { "movZ",             { Rm, Dm }, 0 },
2847   { "movZ",             { Cm, Rm }, 0 },
2848   { "movZ",             { Dm, Rm }, 0 },
2849   { MOD_TABLE (MOD_0F24) },
2850   { Bad_Opcode },
2851   { MOD_TABLE (MOD_0F26) },
2852   { Bad_Opcode },
2853   /* 28 */
2854   { "movapX",           { XM, EXx }, PREFIX_OPCODE },
2855   { "movapX",           { EXxS, XM }, PREFIX_OPCODE },
2856   { PREFIX_TABLE (PREFIX_0F2A) },
2857   { PREFIX_TABLE (PREFIX_0F2B) },
2858   { PREFIX_TABLE (PREFIX_0F2C) },
2859   { PREFIX_TABLE (PREFIX_0F2D) },
2860   { PREFIX_TABLE (PREFIX_0F2E) },
2861   { PREFIX_TABLE (PREFIX_0F2F) },
2862   /* 30 */
2863   { "wrmsr",            { XX }, 0 },
2864   { "rdtsc",            { XX }, 0 },
2865   { "rdmsr",            { XX }, 0 },
2866   { "rdpmc",            { XX }, 0 },
2867   { "sysenter",         { XX }, 0 },
2868   { "sysexit",          { XX }, 0 },
2869   { Bad_Opcode },
2870   { "getsec",           { XX }, 0 },
2871   /* 38 */
2872   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2873   { Bad_Opcode },
2874   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2875   { Bad_Opcode },
2876   { Bad_Opcode },
2877   { Bad_Opcode },
2878   { Bad_Opcode },
2879   { Bad_Opcode },
2880   /* 40 */
2881   { "cmovoS",           { Gv, Ev }, 0 },
2882   { "cmovnoS",          { Gv, Ev }, 0 },
2883   { "cmovbS",           { Gv, Ev }, 0 },
2884   { "cmovaeS",          { Gv, Ev }, 0 },
2885   { "cmoveS",           { Gv, Ev }, 0 },
2886   { "cmovneS",          { Gv, Ev }, 0 },
2887   { "cmovbeS",          { Gv, Ev }, 0 },
2888   { "cmovaS",           { Gv, Ev }, 0 },
2889   /* 48 */
2890   { "cmovsS",           { Gv, Ev }, 0 },
2891   { "cmovnsS",          { Gv, Ev }, 0 },
2892   { "cmovpS",           { Gv, Ev }, 0 },
2893   { "cmovnpS",          { Gv, Ev }, 0 },
2894   { "cmovlS",           { Gv, Ev }, 0 },
2895   { "cmovgeS",          { Gv, Ev }, 0 },
2896   { "cmovleS",          { Gv, Ev }, 0 },
2897   { "cmovgS",           { Gv, Ev }, 0 },
2898   /* 50 */
2899   { MOD_TABLE (MOD_0F51) },
2900   { PREFIX_TABLE (PREFIX_0F51) },
2901   { PREFIX_TABLE (PREFIX_0F52) },
2902   { PREFIX_TABLE (PREFIX_0F53) },
2903   { "andpX",            { XM, EXx }, PREFIX_OPCODE },
2904   { "andnpX",           { XM, EXx }, PREFIX_OPCODE },
2905   { "orpX",             { XM, EXx }, PREFIX_OPCODE },
2906   { "xorpX",            { XM, EXx }, PREFIX_OPCODE },
2907   /* 58 */
2908   { PREFIX_TABLE (PREFIX_0F58) },
2909   { PREFIX_TABLE (PREFIX_0F59) },
2910   { PREFIX_TABLE (PREFIX_0F5A) },
2911   { PREFIX_TABLE (PREFIX_0F5B) },
2912   { PREFIX_TABLE (PREFIX_0F5C) },
2913   { PREFIX_TABLE (PREFIX_0F5D) },
2914   { PREFIX_TABLE (PREFIX_0F5E) },
2915   { PREFIX_TABLE (PREFIX_0F5F) },
2916   /* 60 */
2917   { PREFIX_TABLE (PREFIX_0F60) },
2918   { PREFIX_TABLE (PREFIX_0F61) },
2919   { PREFIX_TABLE (PREFIX_0F62) },
2920   { "packsswb",         { MX, EM }, PREFIX_OPCODE },
2921   { "pcmpgtb",          { MX, EM }, PREFIX_OPCODE },
2922   { "pcmpgtw",          { MX, EM }, PREFIX_OPCODE },
2923   { "pcmpgtd",          { MX, EM }, PREFIX_OPCODE },
2924   { "packuswb",         { MX, EM }, PREFIX_OPCODE },
2925   /* 68 */
2926   { "punpckhbw",        { MX, EM }, PREFIX_OPCODE },
2927   { "punpckhwd",        { MX, EM }, PREFIX_OPCODE },
2928   { "punpckhdq",        { MX, EM }, PREFIX_OPCODE },
2929   { "packssdw",         { MX, EM }, PREFIX_OPCODE },
2930   { PREFIX_TABLE (PREFIX_0F6C) },
2931   { PREFIX_TABLE (PREFIX_0F6D) },
2932   { "movK",             { MX, Edq }, PREFIX_OPCODE },
2933   { PREFIX_TABLE (PREFIX_0F6F) },
2934   /* 70 */
2935   { PREFIX_TABLE (PREFIX_0F70) },
2936   { REG_TABLE (REG_0F71) },
2937   { REG_TABLE (REG_0F72) },
2938   { REG_TABLE (REG_0F73) },
2939   { "pcmpeqb",          { MX, EM }, PREFIX_OPCODE },
2940   { "pcmpeqw",          { MX, EM }, PREFIX_OPCODE },
2941   { "pcmpeqd",          { MX, EM }, PREFIX_OPCODE },
2942   { "emms",             { XX }, PREFIX_OPCODE },
2943   /* 78 */
2944   { PREFIX_TABLE (PREFIX_0F78) },
2945   { PREFIX_TABLE (PREFIX_0F79) },
2946   { THREE_BYTE_TABLE (THREE_BYTE_0F7A) },
2947   { Bad_Opcode },
2948   { PREFIX_TABLE (PREFIX_0F7C) },
2949   { PREFIX_TABLE (PREFIX_0F7D) },
2950   { PREFIX_TABLE (PREFIX_0F7E) },
2951   { PREFIX_TABLE (PREFIX_0F7F) },
2952   /* 80 */
2953   { "joH",              { Jv, BND, cond_jump_flag }, 0 },
2954   { "jnoH",             { Jv, BND, cond_jump_flag }, 0 },
2955   { "jbH",              { Jv, BND, cond_jump_flag }, 0 },
2956   { "jaeH",             { Jv, BND, cond_jump_flag }, 0 },
2957   { "jeH",              { Jv, BND, cond_jump_flag }, 0 },
2958   { "jneH",             { Jv, BND, cond_jump_flag }, 0 },
2959   { "jbeH",             { Jv, BND, cond_jump_flag }, 0 },
2960   { "jaH",              { Jv, BND, cond_jump_flag }, 0 },
2961   /* 88 */
2962   { "jsH",              { Jv, BND, cond_jump_flag }, 0 },
2963   { "jnsH",             { Jv, BND, cond_jump_flag }, 0 },
2964   { "jpH",              { Jv, BND, cond_jump_flag }, 0 },
2965   { "jnpH",             { Jv, BND, cond_jump_flag }, 0 },
2966   { "jlH",              { Jv, BND, cond_jump_flag }, 0 },
2967   { "jgeH",             { Jv, BND, cond_jump_flag }, 0 },
2968   { "jleH",             { Jv, BND, cond_jump_flag }, 0 },
2969   { "jgH",              { Jv, BND, cond_jump_flag }, 0 },
2970   /* 90 */
2971   { "seto",             { Eb }, 0 },
2972   { "setno",            { Eb }, 0 },
2973   { "setb",             { Eb }, 0 },
2974   { "setae",            { Eb }, 0 },
2975   { "sete",             { Eb }, 0 },
2976   { "setne",            { Eb }, 0 },
2977   { "setbe",            { Eb }, 0 },
2978   { "seta",             { Eb }, 0 },
2979   /* 98 */
2980   { "sets",             { Eb }, 0 },
2981   { "setns",            { Eb }, 0 },
2982   { "setp",             { Eb }, 0 },
2983   { "setnp",            { Eb }, 0 },
2984   { "setl",             { Eb }, 0 },
2985   { "setge",            { Eb }, 0 },
2986   { "setle",            { Eb }, 0 },
2987   { "setg",             { Eb }, 0 },
2988   /* a0 */
2989   { "pushT",            { fs }, 0 },
2990   { "popT",             { fs }, 0 },
2991   { "cpuid",            { XX }, 0 },
2992   { "btS",              { Ev, Gv }, 0 },
2993   { "shldS",            { Ev, Gv, Ib }, 0 },
2994   { "shldS",            { Ev, Gv, CL }, 0 },
2995   { REG_TABLE (REG_0FA6) },
2996   { REG_TABLE (REG_0FA7) },
2997   /* a8 */
2998   { "pushT",            { gs }, 0 },
2999   { "popT",             { gs }, 0 },
3000   { "rsm",              { XX }, 0 },
3001   { "btsS",             { Evh1, Gv }, 0 },
3002   { "shrdS",            { Ev, Gv, Ib }, 0 },
3003   { "shrdS",            { Ev, Gv, CL }, 0 },
3004   { REG_TABLE (REG_0FAE) },
3005   { "imulS",            { Gv, Ev }, 0 },
3006   /* b0 */
3007   { "cmpxchgB",         { Ebh1, Gb }, 0 },
3008   { "cmpxchgS",         { Evh1, Gv }, 0 },
3009   { MOD_TABLE (MOD_0FB2) },
3010   { "btrS",             { Evh1, Gv }, 0 },
3011   { MOD_TABLE (MOD_0FB4) },
3012   { MOD_TABLE (MOD_0FB5) },
3013   { "movz{bR|x}",       { Gv, Eb }, 0 },
3014   { "movz{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
3015   /* b8 */
3016   { PREFIX_TABLE (PREFIX_0FB8) },
3017   { "ud1",              { XX }, 0 },
3018   { REG_TABLE (REG_0FBA) },
3019   { "btcS",             { Evh1, Gv }, 0 },
3020   { PREFIX_TABLE (PREFIX_0FBC) },
3021   { PREFIX_TABLE (PREFIX_0FBD) },
3022   { "movs{bR|x}",       { Gv, Eb }, 0 },
3023   { "movs{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
3024   /* c0 */
3025   { "xaddB",            { Ebh1, Gb }, 0 },
3026   { "xaddS",            { Evh1, Gv }, 0 },
3027   { PREFIX_TABLE (PREFIX_0FC2) },
3028   { MOD_TABLE (MOD_0FC3) },
3029   { "pinsrw",           { MX, Edqw, Ib }, PREFIX_OPCODE },
3030   { "pextrw",           { Gdq, MS, Ib }, PREFIX_OPCODE },
3031   { "shufpX",           { XM, EXx, Ib }, PREFIX_OPCODE },
3032   { REG_TABLE (REG_0FC7) },
3033   /* c8 */
3034   { "bswap",            { RMeAX }, 0 },
3035   { "bswap",            { RMeCX }, 0 },
3036   { "bswap",            { RMeDX }, 0 },
3037   { "bswap",            { RMeBX }, 0 },
3038   { "bswap",            { RMeSP }, 0 },
3039   { "bswap",            { RMeBP }, 0 },
3040   { "bswap",            { RMeSI }, 0 },
3041   { "bswap",            { RMeDI }, 0 },
3042   /* d0 */
3043   { PREFIX_TABLE (PREFIX_0FD0) },
3044   { "psrlw",            { MX, EM }, PREFIX_OPCODE },
3045   { "psrld",            { MX, EM }, PREFIX_OPCODE },
3046   { "psrlq",            { MX, EM }, PREFIX_OPCODE },
3047   { "paddq",            { MX, EM }, PREFIX_OPCODE },
3048   { "pmullw",           { MX, EM }, PREFIX_OPCODE },
3049   { PREFIX_TABLE (PREFIX_0FD6) },
3050   { MOD_TABLE (MOD_0FD7) },
3051   /* d8 */
3052   { "psubusb",          { MX, EM }, PREFIX_OPCODE },
3053   { "psubusw",          { MX, EM }, PREFIX_OPCODE },
3054   { "pminub",           { MX, EM }, PREFIX_OPCODE },
3055   { "pand",             { MX, EM }, PREFIX_OPCODE },
3056   { "paddusb",          { MX, EM }, PREFIX_OPCODE },
3057   { "paddusw",          { MX, EM }, PREFIX_OPCODE },
3058   { "pmaxub",           { MX, EM }, PREFIX_OPCODE },
3059   { "pandn",            { MX, EM }, PREFIX_OPCODE },
3060   /* e0 */
3061   { "pavgb",            { MX, EM }, PREFIX_OPCODE },
3062   { "psraw",            { MX, EM }, PREFIX_OPCODE },
3063   { "psrad",            { MX, EM }, PREFIX_OPCODE },
3064   { "pavgw",            { MX, EM }, PREFIX_OPCODE },
3065   { "pmulhuw",          { MX, EM }, PREFIX_OPCODE },
3066   { "pmulhw",           { MX, EM }, PREFIX_OPCODE },
3067   { PREFIX_TABLE (PREFIX_0FE6) },
3068   { PREFIX_TABLE (PREFIX_0FE7) },
3069   /* e8 */
3070   { "psubsb",           { MX, EM }, PREFIX_OPCODE },
3071   { "psubsw",           { MX, EM }, PREFIX_OPCODE },
3072   { "pminsw",           { MX, EM }, PREFIX_OPCODE },
3073   { "por",              { MX, EM }, PREFIX_OPCODE },
3074   { "paddsb",           { MX, EM }, PREFIX_OPCODE },
3075   { "paddsw",           { MX, EM }, PREFIX_OPCODE },
3076   { "pmaxsw",           { MX, EM }, PREFIX_OPCODE },
3077   { "pxor",             { MX, EM }, PREFIX_OPCODE },
3078   /* f0 */
3079   { PREFIX_TABLE (PREFIX_0FF0) },
3080   { "psllw",            { MX, EM }, PREFIX_OPCODE },
3081   { "pslld",            { MX, EM }, PREFIX_OPCODE },
3082   { "psllq",            { MX, EM }, PREFIX_OPCODE },
3083   { "pmuludq",          { MX, EM }, PREFIX_OPCODE },
3084   { "pmaddwd",          { MX, EM }, PREFIX_OPCODE },
3085   { "psadbw",           { MX, EM }, PREFIX_OPCODE },
3086   { PREFIX_TABLE (PREFIX_0FF7) },
3087   /* f8 */
3088   { "psubb",            { MX, EM }, PREFIX_OPCODE },
3089   { "psubw",            { MX, EM }, PREFIX_OPCODE },
3090   { "psubd",            { MX, EM }, PREFIX_OPCODE },
3091   { "psubq",            { MX, EM }, PREFIX_OPCODE },
3092   { "paddb",            { MX, EM }, PREFIX_OPCODE },
3093   { "paddw",            { MX, EM }, PREFIX_OPCODE },
3094   { "paddd",            { MX, EM }, PREFIX_OPCODE },
3095   { Bad_Opcode },
3096 };
3097
3098 static const unsigned char onebyte_has_modrm[256] = {
3099   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3100   /*       -------------------------------        */
3101   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
3102   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
3103   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
3104   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
3105   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
3106   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
3107   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
3108   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
3109   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
3110   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
3111   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
3112   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
3113   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
3114   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
3115   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
3116   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
3117   /*       -------------------------------        */
3118   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3119 };
3120
3121 static const unsigned char twobyte_has_modrm[256] = {
3122   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3123   /*       -------------------------------        */
3124   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
3125   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
3126   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
3127   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
3128   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
3129   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
3130   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
3131   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
3132   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
3133   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
3134   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
3135   /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
3136   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
3137   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
3138   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
3139   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0  /* ff */
3140   /*       -------------------------------        */
3141   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3142 };
3143
3144 static char obuf[100];
3145 static char *obufp;
3146 static char *mnemonicendp;
3147 static char scratchbuf[100];
3148 static unsigned char *start_codep;
3149 static unsigned char *insn_codep;
3150 static unsigned char *codep;
3151 static unsigned char *end_codep;
3152 static int last_lock_prefix;
3153 static int last_repz_prefix;
3154 static int last_repnz_prefix;
3155 static int last_data_prefix;
3156 static int last_addr_prefix;
3157 static int last_rex_prefix;
3158 static int last_seg_prefix;
3159 static int fwait_prefix;
3160 /* The active segment register prefix.  */
3161 static int active_seg_prefix;
3162 #define MAX_CODE_LENGTH 15
3163 /* We can up to 14 prefixes since the maximum instruction length is
3164    15bytes.  */
3165 static int all_prefixes[MAX_CODE_LENGTH - 1];
3166 static disassemble_info *the_info;
3167 static struct
3168   {
3169     int mod;
3170     int reg;
3171     int rm;
3172   }
3173 modrm;
3174 static unsigned char need_modrm;
3175 static struct
3176   {
3177     int scale;
3178     int index;
3179     int base;
3180   }
3181 sib;
3182 static struct
3183   {
3184     int register_specifier;
3185     int length;
3186     int prefix;
3187     int w;
3188     int evex;
3189     int r;
3190     int v;
3191     int mask_register_specifier;
3192     int zeroing;
3193     int ll;
3194     int b;
3195   }
3196 vex;
3197 static unsigned char need_vex;
3198 static unsigned char need_vex_reg;
3199 static unsigned char vex_w_done;
3200
3201 struct op
3202   {
3203     const char *name;
3204     unsigned int len;
3205   };
3206
3207 /* If we are accessing mod/rm/reg without need_modrm set, then the
3208    values are stale.  Hitting this abort likely indicates that you
3209    need to update onebyte_has_modrm or twobyte_has_modrm.  */
3210 #define MODRM_CHECK  if (!need_modrm) abort ()
3211
3212 static const char **names64;
3213 static const char **names32;
3214 static const char **names16;
3215 static const char **names8;
3216 static const char **names8rex;
3217 static const char **names_seg;
3218 static const char *index64;
3219 static const char *index32;
3220 static const char **index16;
3221 static const char **names_bnd;
3222
3223 static const char *intel_names64[] = {
3224   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3225   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3226 };
3227 static const char *intel_names32[] = {
3228   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3229   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3230 };
3231 static const char *intel_names16[] = {
3232   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3233   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3234 };
3235 static const char *intel_names8[] = {
3236   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3237 };
3238 static const char *intel_names8rex[] = {
3239   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3240   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3241 };
3242 static const char *intel_names_seg[] = {
3243   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3244 };
3245 static const char *intel_index64 = "riz";
3246 static const char *intel_index32 = "eiz";
3247 static const char *intel_index16[] = {
3248   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3249 };
3250
3251 static const char *att_names64[] = {
3252   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3253   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3254 };
3255 static const char *att_names32[] = {
3256   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3257   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3258 };
3259 static const char *att_names16[] = {
3260   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3261   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3262 };
3263 static const char *att_names8[] = {
3264   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3265 };
3266 static const char *att_names8rex[] = {
3267   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3268   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3269 };
3270 static const char *att_names_seg[] = {
3271   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3272 };
3273 static const char *att_index64 = "%riz";
3274 static const char *att_index32 = "%eiz";
3275 static const char *att_index16[] = {
3276   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3277 };
3278
3279 static const char **names_mm;
3280 static const char *intel_names_mm[] = {
3281   "mm0", "mm1", "mm2", "mm3",
3282   "mm4", "mm5", "mm6", "mm7"
3283 };
3284 static const char *att_names_mm[] = {
3285   "%mm0", "%mm1", "%mm2", "%mm3",
3286   "%mm4", "%mm5", "%mm6", "%mm7"
3287 };
3288
3289 static const char *intel_names_bnd[] = {
3290   "bnd0", "bnd1", "bnd2", "bnd3"
3291 };
3292
3293 static const char *att_names_bnd[] = {
3294   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3295 };
3296
3297 static const char **names_xmm;
3298 static const char *intel_names_xmm[] = {
3299   "xmm0", "xmm1", "xmm2", "xmm3",
3300   "xmm4", "xmm5", "xmm6", "xmm7",
3301   "xmm8", "xmm9", "xmm10", "xmm11",
3302   "xmm12", "xmm13", "xmm14", "xmm15",
3303   "xmm16", "xmm17", "xmm18", "xmm19",
3304   "xmm20", "xmm21", "xmm22", "xmm23",
3305   "xmm24", "xmm25", "xmm26", "xmm27",
3306   "xmm28", "xmm29", "xmm30", "xmm31"
3307 };
3308 static const char *att_names_xmm[] = {
3309   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3310   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3311   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3312   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3313   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3314   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3315   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3316   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3317 };
3318
3319 static const char **names_ymm;
3320 static const char *intel_names_ymm[] = {
3321   "ymm0", "ymm1", "ymm2", "ymm3",
3322   "ymm4", "ymm5", "ymm6", "ymm7",
3323   "ymm8", "ymm9", "ymm10", "ymm11",
3324   "ymm12", "ymm13", "ymm14", "ymm15",
3325   "ymm16", "ymm17", "ymm18", "ymm19",
3326   "ymm20", "ymm21", "ymm22", "ymm23",
3327   "ymm24", "ymm25", "ymm26", "ymm27",
3328   "ymm28", "ymm29", "ymm30", "ymm31"
3329 };
3330 static const char *att_names_ymm[] = {
3331   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3332   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3333   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3334   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3335   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3336   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3337   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3338   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3339 };
3340
3341 static const char **names_zmm;
3342 static const char *intel_names_zmm[] = {
3343   "zmm0", "zmm1", "zmm2", "zmm3",
3344   "zmm4", "zmm5", "zmm6", "zmm7",
3345   "zmm8", "zmm9", "zmm10", "zmm11",
3346   "zmm12", "zmm13", "zmm14", "zmm15",
3347   "zmm16", "zmm17", "zmm18", "zmm19",
3348   "zmm20", "zmm21", "zmm22", "zmm23",
3349   "zmm24", "zmm25", "zmm26", "zmm27",
3350   "zmm28", "zmm29", "zmm30", "zmm31"
3351 };
3352 static const char *att_names_zmm[] = {
3353   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3354   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3355   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3356   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3357   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3358   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3359   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3360   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3361 };
3362
3363 static const char **names_mask;
3364 static const char *intel_names_mask[] = {
3365   "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3366 };
3367 static const char *att_names_mask[] = {
3368   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3369 };
3370
3371 static const char *names_rounding[] =
3372 {
3373   "{rn-sae}",
3374   "{rd-sae}",
3375   "{ru-sae}",
3376   "{rz-sae}"
3377 };
3378
3379 static const struct dis386 reg_table[][8] = {
3380   /* REG_80 */
3381   {
3382     { "addA",   { Ebh1, Ib }, 0 },
3383     { "orA",    { Ebh1, Ib }, 0 },
3384     { "adcA",   { Ebh1, Ib }, 0 },
3385     { "sbbA",   { Ebh1, Ib }, 0 },
3386     { "andA",   { Ebh1, Ib }, 0 },
3387     { "subA",   { Ebh1, Ib }, 0 },
3388     { "xorA",   { Ebh1, Ib }, 0 },
3389     { "cmpA",   { Eb, Ib }, 0 },
3390   },
3391   /* REG_81 */
3392   {
3393     { "addQ",   { Evh1, Iv }, 0 },
3394     { "orQ",    { Evh1, Iv }, 0 },
3395     { "adcQ",   { Evh1, Iv }, 0 },
3396     { "sbbQ",   { Evh1, Iv }, 0 },
3397     { "andQ",   { Evh1, Iv }, 0 },
3398     { "subQ",   { Evh1, Iv }, 0 },
3399     { "xorQ",   { Evh1, Iv }, 0 },
3400     { "cmpQ",   { Ev, Iv }, 0 },
3401   },
3402   /* REG_82 */
3403   {
3404     { "addQ",   { Evh1, sIb }, 0 },
3405     { "orQ",    { Evh1, sIb }, 0 },
3406     { "adcQ",   { Evh1, sIb }, 0 },
3407     { "sbbQ",   { Evh1, sIb }, 0 },
3408     { "andQ",   { Evh1, sIb }, 0 },
3409     { "subQ",   { Evh1, sIb }, 0 },
3410     { "xorQ",   { Evh1, sIb }, 0 },
3411     { "cmpQ",   { Ev, sIb }, 0 },
3412   },
3413   /* REG_8F */
3414   {
3415     { "popU",   { stackEv }, 0 },
3416     { XOP_8F_TABLE (XOP_09) },
3417     { Bad_Opcode },
3418     { Bad_Opcode },
3419     { Bad_Opcode },
3420     { XOP_8F_TABLE (XOP_09) },
3421   },
3422   /* REG_C0 */
3423   {
3424     { "rolA",   { Eb, Ib }, 0 },
3425     { "rorA",   { Eb, Ib }, 0 },
3426     { "rclA",   { Eb, Ib }, 0 },
3427     { "rcrA",   { Eb, Ib }, 0 },
3428     { "shlA",   { Eb, Ib }, 0 },
3429     { "shrA",   { Eb, Ib }, 0 },
3430     { Bad_Opcode },
3431     { "sarA",   { Eb, Ib }, 0 },
3432   },
3433   /* REG_C1 */
3434   {
3435     { "rolQ",   { Ev, Ib }, 0 },
3436     { "rorQ",   { Ev, Ib }, 0 },
3437     { "rclQ",   { Ev, Ib }, 0 },
3438     { "rcrQ",   { Ev, Ib }, 0 },
3439     { "shlQ",   { Ev, Ib }, 0 },
3440     { "shrQ",   { Ev, Ib }, 0 },
3441     { Bad_Opcode },
3442     { "sarQ",   { Ev, Ib }, 0 },
3443   },
3444   /* REG_C6 */
3445   {
3446     { "movA",   { Ebh3, Ib }, 0 },
3447     { Bad_Opcode },
3448     { Bad_Opcode },
3449     { Bad_Opcode },
3450     { Bad_Opcode },
3451     { Bad_Opcode },
3452     { Bad_Opcode },
3453     { MOD_TABLE (MOD_C6_REG_7) },
3454   },
3455   /* REG_C7 */
3456   {
3457     { "movQ",   { Evh3, Iv }, 0 },
3458     { Bad_Opcode },
3459     { Bad_Opcode },
3460     { Bad_Opcode },
3461     { Bad_Opcode },
3462     { Bad_Opcode },
3463     { Bad_Opcode },
3464     { MOD_TABLE (MOD_C7_REG_7) },
3465   },
3466   /* REG_D0 */
3467   {
3468     { "rolA",   { Eb, I1 }, 0 },
3469     { "rorA",   { Eb, I1 }, 0 },
3470     { "rclA",   { Eb, I1 }, 0 },
3471     { "rcrA",   { Eb, I1 }, 0 },
3472     { "shlA",   { Eb, I1 }, 0 },
3473     { "shrA",   { Eb, I1 }, 0 },
3474     { Bad_Opcode },
3475     { "sarA",   { Eb, I1 }, 0 },
3476   },
3477   /* REG_D1 */
3478   {
3479     { "rolQ",   { Ev, I1 }, 0 },
3480     { "rorQ",   { Ev, I1 }, 0 },
3481     { "rclQ",   { Ev, I1 }, 0 },
3482     { "rcrQ",   { Ev, I1 }, 0 },
3483     { "shlQ",   { Ev, I1 }, 0 },
3484     { "shrQ",   { Ev, I1 }, 0 },
3485     { Bad_Opcode },
3486     { "sarQ",   { Ev, I1 }, 0 },
3487   },
3488   /* REG_D2 */
3489   {
3490     { "rolA",   { Eb, CL }, 0 },
3491     { "rorA",   { Eb, CL }, 0 },
3492     { "rclA",   { Eb, CL }, 0 },
3493     { "rcrA",   { Eb, CL }, 0 },
3494     { "shlA",   { Eb, CL }, 0 },
3495     { "shrA",   { Eb, CL }, 0 },
3496     { Bad_Opcode },
3497     { "sarA",   { Eb, CL }, 0 },
3498   },
3499   /* REG_D3 */
3500   {
3501     { "rolQ",   { Ev, CL }, 0 },
3502     { "rorQ",   { Ev, CL }, 0 },
3503     { "rclQ",   { Ev, CL }, 0 },
3504     { "rcrQ",   { Ev, CL }, 0 },
3505     { "shlQ",   { Ev, CL }, 0 },
3506     { "shrQ",   { Ev, CL }, 0 },
3507     { Bad_Opcode },
3508     { "sarQ",   { Ev, CL }, 0 },
3509   },
3510   /* REG_F6 */
3511   {
3512     { "testA",  { Eb, Ib }, 0 },
3513     { Bad_Opcode },
3514     { "notA",   { Ebh1 }, 0 },
3515     { "negA",   { Ebh1 }, 0 },
3516     { "mulA",   { Eb }, 0 },    /* Don't print the implicit %al register,  */
3517     { "imulA",  { Eb }, 0 },    /* to distinguish these opcodes from other */
3518     { "divA",   { Eb }, 0 },    /* mul/imul opcodes.  Do the same for div  */
3519     { "idivA",  { Eb }, 0 },    /* and idiv for consistency.               */
3520   },
3521   /* REG_F7 */
3522   {
3523     { "testQ",  { Ev, Iv }, 0 },
3524     { Bad_Opcode },
3525     { "notQ",   { Evh1 }, 0 },
3526     { "negQ",   { Evh1 }, 0 },
3527     { "mulQ",   { Ev }, 0 },    /* Don't print the implicit register.  */
3528     { "imulQ",  { Ev }, 0 },
3529     { "divQ",   { Ev }, 0 },
3530     { "idivQ",  { Ev }, 0 },
3531   },
3532   /* REG_FE */
3533   {
3534     { "incA",   { Ebh1 }, 0 },
3535     { "decA",   { Ebh1 }, 0 },
3536   },
3537   /* REG_FF */
3538   {
3539     { "incQ",   { Evh1 }, 0 },
3540     { "decQ",   { Evh1 }, 0 },
3541     { "call{&|}", { indirEv, BND }, 0 },
3542     { MOD_TABLE (MOD_FF_REG_3) },
3543     { "jmp{&|}", { indirEv, BND }, 0 },
3544     { MOD_TABLE (MOD_FF_REG_5) },
3545     { "pushU",  { stackEv }, 0 },
3546     { Bad_Opcode },
3547   },
3548   /* REG_0F00 */
3549   {
3550     { "sldtD",  { Sv }, 0 },
3551     { "strD",   { Sv }, 0 },
3552     { "lldt",   { Ew }, 0 },
3553     { "ltr",    { Ew }, 0 },
3554     { "verr",   { Ew }, 0 },
3555     { "verw",   { Ew }, 0 },
3556     { Bad_Opcode },
3557     { Bad_Opcode },
3558   },
3559   /* REG_0F01 */
3560   {
3561     { MOD_TABLE (MOD_0F01_REG_0) },
3562     { MOD_TABLE (MOD_0F01_REG_1) },
3563     { MOD_TABLE (MOD_0F01_REG_2) },
3564     { MOD_TABLE (MOD_0F01_REG_3) },
3565     { "smswD",  { Sv }, 0 },
3566     { MOD_TABLE (MOD_0F01_REG_5) },
3567     { "lmsw",   { Ew }, 0 },
3568     { MOD_TABLE (MOD_0F01_REG_7) },
3569   },
3570   /* REG_0F0D */
3571   {
3572     { "prefetch",       { Mb }, 0 },
3573     { "prefetchw",      { Mb }, 0 },
3574     { "prefetchwt1",    { Mb }, 0 },
3575     { "prefetch",       { Mb }, 0 },
3576     { "prefetch",       { Mb }, 0 },
3577     { "prefetch",       { Mb }, 0 },
3578     { "prefetch",       { Mb }, 0 },
3579     { "prefetch",       { Mb }, 0 },
3580   },
3581   /* REG_0F18 */
3582   {
3583     { MOD_TABLE (MOD_0F18_REG_0) },
3584     { MOD_TABLE (MOD_0F18_REG_1) },
3585     { MOD_TABLE (MOD_0F18_REG_2) },
3586     { MOD_TABLE (MOD_0F18_REG_3) },
3587     { MOD_TABLE (MOD_0F18_REG_4) },
3588     { MOD_TABLE (MOD_0F18_REG_5) },
3589     { MOD_TABLE (MOD_0F18_REG_6) },
3590     { MOD_TABLE (MOD_0F18_REG_7) },
3591   },
3592   /* REG_0F71 */
3593   {
3594     { Bad_Opcode },
3595     { Bad_Opcode },
3596     { MOD_TABLE (MOD_0F71_REG_2) },
3597     { Bad_Opcode },
3598     { MOD_TABLE (MOD_0F71_REG_4) },
3599     { Bad_Opcode },
3600     { MOD_TABLE (MOD_0F71_REG_6) },
3601   },
3602   /* REG_0F72 */
3603   {
3604     { Bad_Opcode },
3605     { Bad_Opcode },
3606     { MOD_TABLE (MOD_0F72_REG_2) },
3607     { Bad_Opcode },
3608     { MOD_TABLE (MOD_0F72_REG_4) },
3609     { Bad_Opcode },
3610     { MOD_TABLE (MOD_0F72_REG_6) },
3611   },
3612   /* REG_0F73 */
3613   {
3614     { Bad_Opcode },
3615     { Bad_Opcode },
3616     { MOD_TABLE (MOD_0F73_REG_2) },
3617     { MOD_TABLE (MOD_0F73_REG_3) },
3618     { Bad_Opcode },
3619     { Bad_Opcode },
3620     { MOD_TABLE (MOD_0F73_REG_6) },
3621     { MOD_TABLE (MOD_0F73_REG_7) },
3622   },
3623   /* REG_0FA6 */
3624   {
3625     { "montmul",        { { OP_0f07, 0 } }, 0 },
3626     { "xsha1",          { { OP_0f07, 0 } }, 0 },
3627     { "xsha256",        { { OP_0f07, 0 } }, 0 },
3628   },
3629   /* REG_0FA7 */
3630   {
3631     { "xstore-rng",     { { OP_0f07, 0 } }, 0 },
3632     { "xcrypt-ecb",     { { OP_0f07, 0 } }, 0 },
3633     { "xcrypt-cbc",     { { OP_0f07, 0 } }, 0 },
3634     { "xcrypt-ctr",     { { OP_0f07, 0 } }, 0 },
3635     { "xcrypt-cfb",     { { OP_0f07, 0 } }, 0 },
3636     { "xcrypt-ofb",     { { OP_0f07, 0 } }, 0 },
3637   },
3638   /* REG_0FAE */
3639   {
3640     { MOD_TABLE (MOD_0FAE_REG_0) },
3641     { MOD_TABLE (MOD_0FAE_REG_1) },
3642     { MOD_TABLE (MOD_0FAE_REG_2) },
3643     { MOD_TABLE (MOD_0FAE_REG_3) },
3644     { MOD_TABLE (MOD_0FAE_REG_4) },
3645     { MOD_TABLE (MOD_0FAE_REG_5) },
3646     { MOD_TABLE (MOD_0FAE_REG_6) },
3647     { MOD_TABLE (MOD_0FAE_REG_7) },
3648   },
3649   /* REG_0FBA */
3650   {
3651     { Bad_Opcode },
3652     { Bad_Opcode },
3653     { Bad_Opcode },
3654     { Bad_Opcode },
3655     { "btQ",    { Ev, Ib }, 0 },
3656     { "btsQ",   { Evh1, Ib }, 0 },
3657     { "btrQ",   { Evh1, Ib }, 0 },
3658     { "btcQ",   { Evh1, Ib }, 0 },
3659   },
3660   /* REG_0FC7 */
3661   {
3662     { Bad_Opcode },
3663     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
3664     { Bad_Opcode },
3665     { MOD_TABLE (MOD_0FC7_REG_3) },
3666     { MOD_TABLE (MOD_0FC7_REG_4) },
3667     { MOD_TABLE (MOD_0FC7_REG_5) },
3668     { MOD_TABLE (MOD_0FC7_REG_6) },
3669     { MOD_TABLE (MOD_0FC7_REG_7) },
3670   },
3671   /* REG_VEX_0F71 */
3672   {
3673     { Bad_Opcode },
3674     { Bad_Opcode },
3675     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3676     { Bad_Opcode },
3677     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3678     { Bad_Opcode },
3679     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3680   },
3681   /* REG_VEX_0F72 */
3682   {
3683     { Bad_Opcode },
3684     { Bad_Opcode },
3685     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3686     { Bad_Opcode },
3687     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3688     { Bad_Opcode },
3689     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3690   },
3691   /* REG_VEX_0F73 */
3692   {
3693     { Bad_Opcode },
3694     { Bad_Opcode },
3695     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3696     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3697     { Bad_Opcode },
3698     { Bad_Opcode },
3699     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3700     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3701   },
3702   /* REG_VEX_0FAE */
3703   {
3704     { Bad_Opcode },
3705     { Bad_Opcode },
3706     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3707     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3708   },
3709   /* REG_VEX_0F38F3 */
3710   {
3711     { Bad_Opcode },
3712     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3713     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3714     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3715   },
3716   /* REG_XOP_LWPCB */
3717   {
3718     { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3719     { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3720   },
3721   /* REG_XOP_LWP */
3722   {
3723     { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3724     { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3725   },
3726   /* REG_XOP_TBM_01 */
3727   {
3728     { Bad_Opcode },
3729     { "blcfill",        { { OP_LWP_E, 0 }, Ev }, 0 },
3730     { "blsfill",        { { OP_LWP_E, 0 }, Ev }, 0 },
3731     { "blcs",   { { OP_LWP_E, 0 }, Ev }, 0 },
3732     { "tzmsk",  { { OP_LWP_E, 0 }, Ev }, 0 },
3733     { "blcic",  { { OP_LWP_E, 0 }, Ev }, 0 },
3734     { "blsic",  { { OP_LWP_E, 0 }, Ev }, 0 },
3735     { "t1mskc", { { OP_LWP_E, 0 }, Ev }, 0 },
3736   },
3737   /* REG_XOP_TBM_02 */
3738   {
3739     { Bad_Opcode },
3740     { "blcmsk", { { OP_LWP_E, 0 }, Ev }, 0 },
3741     { Bad_Opcode },
3742     { Bad_Opcode },
3743     { Bad_Opcode },
3744     { Bad_Opcode },
3745     { "blci",   { { OP_LWP_E, 0 }, Ev }, 0 },
3746   },
3747 #define NEED_REG_TABLE
3748 #include "i386-dis-evex.h"
3749 #undef NEED_REG_TABLE
3750 };
3751
3752 static const struct dis386 prefix_table[][4] = {
3753   /* PREFIX_90 */
3754   {
3755     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3756     { "pause", { XX }, 0 },
3757     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3758     { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3759   },
3760
3761   /* PREFIX_0F10 */
3762   {
3763     { "movups", { XM, EXx }, PREFIX_OPCODE },
3764     { "movss",  { XM, EXd }, PREFIX_OPCODE },
3765     { "movupd", { XM, EXx }, PREFIX_OPCODE },
3766     { "movsd",  { XM, EXq }, PREFIX_OPCODE },
3767   },
3768
3769   /* PREFIX_0F11 */
3770   {
3771     { "movups", { EXxS, XM }, PREFIX_OPCODE },
3772     { "movss",  { EXdS, XM }, PREFIX_OPCODE },
3773     { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3774     { "movsd",  { EXqS, XM }, PREFIX_OPCODE },
3775   },
3776
3777   /* PREFIX_0F12 */
3778   {
3779     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3780     { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3781     { "movlpd", { XM, EXq }, PREFIX_OPCODE },
3782     { "movddup", { XM, EXq }, PREFIX_OPCODE },
3783   },
3784
3785   /* PREFIX_0F16 */
3786   {
3787     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3788     { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3789     { "movhpd", { XM, EXq }, PREFIX_OPCODE },
3790   },
3791
3792   /* PREFIX_0F1A */
3793   {
3794     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3795     { "bndcl",  { Gbnd, Ev_bnd }, 0 },
3796     { "bndmov", { Gbnd, Ebnd }, 0 },
3797     { "bndcu",  { Gbnd, Ev_bnd }, 0 },
3798   },
3799
3800   /* PREFIX_0F1B */
3801   {
3802     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3803     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3804     { "bndmov", { Ebnd, Gbnd }, 0 },
3805     { "bndcn",  { Gbnd, Ev_bnd }, 0 },
3806   },
3807
3808   /* PREFIX_0F2A */
3809   {
3810     { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3811     { "cvtsi2ss%LQ", { XM, Ev }, PREFIX_OPCODE },
3812     { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3813     { "cvtsi2sd%LQ", { XM, Ev }, 0 },
3814   },
3815
3816   /* PREFIX_0F2B */
3817   {
3818     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3819     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3820     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3821     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3822   },
3823
3824   /* PREFIX_0F2C */
3825   {
3826     { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3827     { "cvttss2siY", { Gv, EXd }, PREFIX_OPCODE },
3828     { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3829     { "cvttsd2siY", { Gv, EXq }, PREFIX_OPCODE },
3830   },
3831
3832   /* PREFIX_0F2D */
3833   {
3834     { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3835     { "cvtss2siY", { Gv, EXd }, PREFIX_OPCODE },
3836     { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3837     { "cvtsd2siY", { Gv, EXq }, PREFIX_OPCODE },
3838   },
3839
3840   /* PREFIX_0F2E */
3841   {
3842     { "ucomiss",{ XM, EXd }, 0 },
3843     { Bad_Opcode },
3844     { "ucomisd",{ XM, EXq }, 0 },
3845   },
3846
3847   /* PREFIX_0F2F */
3848   {
3849     { "comiss", { XM, EXd }, 0 },
3850     { Bad_Opcode },
3851     { "comisd", { XM, EXq }, 0 },
3852   },
3853
3854   /* PREFIX_0F51 */
3855   {
3856     { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3857     { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3858     { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3859     { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3860   },
3861
3862   /* PREFIX_0F52 */
3863   {
3864     { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3865     { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3866   },
3867
3868   /* PREFIX_0F53 */
3869   {
3870     { "rcpps",  { XM, EXx }, PREFIX_OPCODE },
3871     { "rcpss",  { XM, EXd }, PREFIX_OPCODE },
3872   },
3873
3874   /* PREFIX_0F58 */
3875   {
3876     { "addps", { XM, EXx }, PREFIX_OPCODE },
3877     { "addss", { XM, EXd }, PREFIX_OPCODE },
3878     { "addpd", { XM, EXx }, PREFIX_OPCODE },
3879     { "addsd", { XM, EXq }, PREFIX_OPCODE },
3880   },
3881
3882   /* PREFIX_0F59 */
3883   {
3884     { "mulps",  { XM, EXx }, PREFIX_OPCODE },
3885     { "mulss",  { XM, EXd }, PREFIX_OPCODE },
3886     { "mulpd",  { XM, EXx }, PREFIX_OPCODE },
3887     { "mulsd",  { XM, EXq }, PREFIX_OPCODE },
3888   },
3889
3890   /* PREFIX_0F5A */
3891   {
3892     { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3893     { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3894     { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3895     { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3896   },
3897
3898   /* PREFIX_0F5B */
3899   {
3900     { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3901     { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3902     { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3903   },
3904
3905   /* PREFIX_0F5C */
3906   {
3907     { "subps",  { XM, EXx }, PREFIX_OPCODE },
3908     { "subss",  { XM, EXd }, PREFIX_OPCODE },
3909     { "subpd",  { XM, EXx }, PREFIX_OPCODE },
3910     { "subsd",  { XM, EXq }, PREFIX_OPCODE },
3911   },
3912
3913   /* PREFIX_0F5D */
3914   {
3915     { "minps",  { XM, EXx }, PREFIX_OPCODE },
3916     { "minss",  { XM, EXd }, PREFIX_OPCODE },
3917     { "minpd",  { XM, EXx }, PREFIX_OPCODE },
3918     { "minsd",  { XM, EXq }, PREFIX_OPCODE },
3919   },
3920
3921   /* PREFIX_0F5E */
3922   {
3923     { "divps",  { XM, EXx }, PREFIX_OPCODE },
3924     { "divss",  { XM, EXd }, PREFIX_OPCODE },
3925     { "divpd",  { XM, EXx }, PREFIX_OPCODE },
3926     { "divsd",  { XM, EXq }, PREFIX_OPCODE },
3927   },
3928
3929   /* PREFIX_0F5F */
3930   {
3931     { "maxps",  { XM, EXx }, PREFIX_OPCODE },
3932     { "maxss",  { XM, EXd }, PREFIX_OPCODE },
3933     { "maxpd",  { XM, EXx }, PREFIX_OPCODE },
3934     { "maxsd",  { XM, EXq }, PREFIX_OPCODE },
3935   },
3936
3937   /* PREFIX_0F60 */
3938   {
3939     { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3940     { Bad_Opcode },
3941     { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3942   },
3943
3944   /* PREFIX_0F61 */
3945   {
3946     { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3947     { Bad_Opcode },
3948     { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3949   },
3950
3951   /* PREFIX_0F62 */
3952   {
3953     { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3954     { Bad_Opcode },
3955     { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3956   },
3957
3958   /* PREFIX_0F6C */
3959   {
3960     { Bad_Opcode },
3961     { Bad_Opcode },
3962     { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE },
3963   },
3964
3965   /* PREFIX_0F6D */
3966   {
3967     { Bad_Opcode },
3968     { Bad_Opcode },
3969     { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE },
3970   },
3971
3972   /* PREFIX_0F6F */
3973   {
3974     { "movq",   { MX, EM }, PREFIX_OPCODE },
3975     { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3976     { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3977   },
3978
3979   /* PREFIX_0F70 */
3980   {
3981     { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3982     { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3983     { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3984     { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3985   },
3986
3987   /* PREFIX_0F73_REG_3 */
3988   {
3989     { Bad_Opcode },
3990     { Bad_Opcode },
3991     { "psrldq", { XS, Ib }, 0 },
3992   },
3993
3994   /* PREFIX_0F73_REG_7 */
3995   {
3996     { Bad_Opcode },
3997     { Bad_Opcode },
3998     { "pslldq", { XS, Ib }, 0 },
3999   },
4000
4001   /* PREFIX_0F78 */
4002   {
4003     {"vmread",  { Em, Gm }, 0 },
4004     { Bad_Opcode },
4005     {"extrq",   { XS, Ib, Ib }, 0 },
4006     {"insertq", { XM, XS, Ib, Ib }, 0 },
4007   },
4008
4009   /* PREFIX_0F79 */
4010   {
4011     {"vmwrite", { Gm, Em }, 0 },
4012     { Bad_Opcode },
4013     {"extrq",   { XM, XS }, 0 },
4014     {"insertq", { XM, XS }, 0 },
4015   },
4016
4017   /* PREFIX_0F7C */
4018   {
4019     { Bad_Opcode },
4020     { Bad_Opcode },
4021     { "haddpd", { XM, EXx }, PREFIX_OPCODE },
4022     { "haddps", { XM, EXx }, PREFIX_OPCODE },
4023   },
4024
4025   /* PREFIX_0F7D */
4026   {
4027     { Bad_Opcode },
4028     { Bad_Opcode },
4029     { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
4030     { "hsubps", { XM, EXx }, PREFIX_OPCODE },
4031   },
4032
4033   /* PREFIX_0F7E */
4034   {
4035     { "movK",   { Edq, MX }, PREFIX_OPCODE },
4036     { "movq",   { XM, EXq }, PREFIX_OPCODE },
4037     { "movK",   { Edq, XM }, PREFIX_OPCODE },
4038   },
4039
4040   /* PREFIX_0F7F */
4041   {
4042     { "movq",   { EMS, MX }, PREFIX_OPCODE },
4043     { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
4044     { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
4045   },
4046
4047   /* PREFIX_0FAE_REG_0 */
4048   {
4049     { Bad_Opcode },
4050     { "rdfsbase", { Ev }, 0 },
4051   },
4052
4053   /* PREFIX_0FAE_REG_1 */
4054   {
4055     { Bad_Opcode },
4056     { "rdgsbase", { Ev }, 0 },
4057   },
4058
4059   /* PREFIX_0FAE_REG_2 */
4060   {
4061     { Bad_Opcode },
4062     { "wrfsbase", { Ev }, 0 },
4063   },
4064
4065   /* PREFIX_0FAE_REG_3 */
4066   {
4067     { Bad_Opcode },
4068     { "wrgsbase", { Ev }, 0 },
4069   },
4070
4071   /* PREFIX_MOD_0_0FAE_REG_4 */
4072   {
4073     { "xsave",  { FXSAVE }, 0 },
4074     { "ptwrite%LQ", { Edq }, 0 },
4075   },
4076
4077   /* PREFIX_MOD_3_0FAE_REG_4 */
4078   {
4079     { Bad_Opcode },
4080     { "ptwrite%LQ", { Edq }, 0 },
4081   },
4082
4083   /* PREFIX_0FAE_REG_6 */
4084   {
4085     { "xsaveopt",      { FXSAVE }, 0 },
4086     { Bad_Opcode },
4087     { "clwb",   { Mb }, 0 },
4088   },
4089
4090   /* PREFIX_0FAE_REG_7 */
4091   {
4092     { "clflush",        { Mb }, 0 },
4093     { Bad_Opcode },
4094     { "clflushopt",     { Mb }, 0 },
4095   },
4096
4097   /* PREFIX_RM_0_0FAE_REG_7 */
4098   {
4099     { "sfence",         { Skip_MODRM }, 0 },
4100     { Bad_Opcode },
4101     { "pcommit",                { Skip_MODRM }, 0 },
4102   },
4103
4104   /* PREFIX_0FB8 */
4105   {
4106     { Bad_Opcode },
4107     { "popcntS", { Gv, Ev }, 0 },
4108   },
4109
4110   /* PREFIX_0FBC */
4111   {
4112     { "bsfS",   { Gv, Ev }, 0 },
4113     { "tzcntS", { Gv, Ev }, 0 },
4114     { "bsfS",   { Gv, Ev }, 0 },
4115   },
4116
4117   /* PREFIX_0FBD */
4118   {
4119     { "bsrS",   { Gv, Ev }, 0 },
4120     { "lzcntS", { Gv, Ev }, 0 },
4121     { "bsrS",   { Gv, Ev }, 0 },
4122   },
4123
4124   /* PREFIX_0FC2 */
4125   {
4126     { "cmpps",  { XM, EXx, CMP }, PREFIX_OPCODE },
4127     { "cmpss",  { XM, EXd, CMP }, PREFIX_OPCODE },
4128     { "cmppd",  { XM, EXx, CMP }, PREFIX_OPCODE },
4129     { "cmpsd",  { XM, EXq, CMP }, PREFIX_OPCODE },
4130   },
4131
4132   /* PREFIX_MOD_0_0FC3 */
4133   {
4134     { "movntiS", { Ev, Gv }, PREFIX_OPCODE },
4135   },
4136
4137   /* PREFIX_MOD_0_0FC7_REG_6 */
4138   {
4139     { "vmptrld",{ Mq }, 0 },
4140     { "vmxon",  { Mq }, 0 },
4141     { "vmclear",{ Mq }, 0 },
4142   },
4143
4144   /* PREFIX_MOD_3_0FC7_REG_6 */
4145   {
4146     { "rdrand", { Ev }, 0 },
4147     { Bad_Opcode },
4148     { "rdrand", { Ev }, 0 }
4149   },
4150
4151   /* PREFIX_MOD_3_0FC7_REG_7 */
4152   {
4153     { "rdseed", { Ev }, 0 },
4154     { "rdpid",  { Em }, 0 },
4155     { "rdseed", { Ev }, 0 },
4156   },
4157
4158   /* PREFIX_0FD0 */
4159   {
4160     { Bad_Opcode },
4161     { Bad_Opcode },
4162     { "addsubpd", { XM, EXx }, 0 },
4163     { "addsubps", { XM, EXx }, 0 },
4164   },
4165
4166   /* PREFIX_0FD6 */
4167   {
4168     { Bad_Opcode },
4169     { "movq2dq",{ XM, MS }, 0 },
4170     { "movq",   { EXqS, XM }, 0 },
4171     { "movdq2q",{ MX, XS }, 0 },
4172   },
4173
4174   /* PREFIX_0FE6 */
4175   {
4176     { Bad_Opcode },
4177     { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
4178     { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
4179     { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
4180   },
4181
4182   /* PREFIX_0FE7 */
4183   {
4184     { "movntq", { Mq, MX }, PREFIX_OPCODE },
4185     { Bad_Opcode },
4186     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
4187   },
4188
4189   /* PREFIX_0FF0 */
4190   {
4191     { Bad_Opcode },
4192     { Bad_Opcode },
4193     { Bad_Opcode },
4194     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4195   },
4196
4197   /* PREFIX_0FF7 */
4198   {
4199     { "maskmovq", { MX, MS }, PREFIX_OPCODE },
4200     { Bad_Opcode },
4201     { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
4202   },
4203
4204   /* PREFIX_0F3810 */
4205   {
4206     { Bad_Opcode },
4207     { Bad_Opcode },
4208     { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4209   },
4210
4211   /* PREFIX_0F3814 */
4212   {
4213     { Bad_Opcode },
4214     { Bad_Opcode },
4215     { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4216   },
4217
4218   /* PREFIX_0F3815 */
4219   {
4220     { Bad_Opcode },
4221     { Bad_Opcode },
4222     { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4223   },
4224
4225   /* PREFIX_0F3817 */
4226   {
4227     { Bad_Opcode },
4228     { Bad_Opcode },
4229     { "ptest",  { XM, EXx }, PREFIX_OPCODE },
4230   },
4231
4232   /* PREFIX_0F3820 */
4233   {
4234     { Bad_Opcode },
4235     { Bad_Opcode },
4236     { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE },
4237   },
4238
4239   /* PREFIX_0F3821 */
4240   {
4241     { Bad_Opcode },
4242     { Bad_Opcode },
4243     { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE },
4244   },
4245
4246   /* PREFIX_0F3822 */
4247   {
4248     { Bad_Opcode },
4249     { Bad_Opcode },
4250     { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE },
4251   },
4252
4253   /* PREFIX_0F3823 */
4254   {
4255     { Bad_Opcode },
4256     { Bad_Opcode },
4257     { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE },
4258   },
4259
4260   /* PREFIX_0F3824 */
4261   {
4262     { Bad_Opcode },
4263     { Bad_Opcode },
4264     { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE },
4265   },
4266
4267   /* PREFIX_0F3825 */
4268   {
4269     { Bad_Opcode },
4270     { Bad_Opcode },
4271     { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE },
4272   },
4273
4274   /* PREFIX_0F3828 */
4275   {
4276     { Bad_Opcode },
4277     { Bad_Opcode },
4278     { "pmuldq", { XM, EXx }, PREFIX_OPCODE },
4279   },
4280
4281   /* PREFIX_0F3829 */
4282   {
4283     { Bad_Opcode },
4284     { Bad_Opcode },
4285     { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE },
4286   },
4287
4288   /* PREFIX_0F382A */
4289   {
4290     { Bad_Opcode },
4291     { Bad_Opcode },
4292     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4293   },
4294
4295   /* PREFIX_0F382B */
4296   {
4297     { Bad_Opcode },
4298     { Bad_Opcode },
4299     { "packusdw", { XM, EXx }, PREFIX_OPCODE },
4300   },
4301
4302   /* PREFIX_0F3830 */
4303   {
4304     { Bad_Opcode },
4305     { Bad_Opcode },
4306     { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE },
4307   },
4308
4309   /* PREFIX_0F3831 */
4310   {
4311     { Bad_Opcode },
4312     { Bad_Opcode },
4313     { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE },
4314   },
4315
4316   /* PREFIX_0F3832 */
4317   {
4318     { Bad_Opcode },
4319     { Bad_Opcode },
4320     { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE },
4321   },
4322
4323   /* PREFIX_0F3833 */
4324   {
4325     { Bad_Opcode },
4326     { Bad_Opcode },
4327     { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE },
4328   },
4329
4330   /* PREFIX_0F3834 */
4331   {
4332     { Bad_Opcode },
4333     { Bad_Opcode },
4334     { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE },
4335   },
4336
4337   /* PREFIX_0F3835 */
4338   {
4339     { Bad_Opcode },
4340     { Bad_Opcode },
4341     { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE },
4342   },
4343
4344   /* PREFIX_0F3837 */
4345   {
4346     { Bad_Opcode },
4347     { Bad_Opcode },
4348     { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE },
4349   },
4350
4351   /* PREFIX_0F3838 */
4352   {
4353     { Bad_Opcode },
4354     { Bad_Opcode },
4355     { "pminsb", { XM, EXx }, PREFIX_OPCODE },
4356   },
4357
4358   /* PREFIX_0F3839 */
4359   {
4360     { Bad_Opcode },
4361     { Bad_Opcode },
4362     { "pminsd", { XM, EXx }, PREFIX_OPCODE },
4363   },
4364
4365   /* PREFIX_0F383A */
4366   {
4367     { Bad_Opcode },
4368     { Bad_Opcode },
4369     { "pminuw", { XM, EXx }, PREFIX_OPCODE },
4370   },
4371
4372   /* PREFIX_0F383B */
4373   {
4374     { Bad_Opcode },
4375     { Bad_Opcode },
4376     { "pminud", { XM, EXx }, PREFIX_OPCODE },
4377   },
4378
4379   /* PREFIX_0F383C */
4380   {
4381     { Bad_Opcode },
4382     { Bad_Opcode },
4383     { "pmaxsb", { XM, EXx }, PREFIX_OPCODE },
4384   },
4385
4386   /* PREFIX_0F383D */
4387   {
4388     { Bad_Opcode },
4389     { Bad_Opcode },
4390     { "pmaxsd", { XM, EXx }, PREFIX_OPCODE },
4391   },
4392
4393   /* PREFIX_0F383E */
4394   {
4395     { Bad_Opcode },
4396     { Bad_Opcode },
4397     { "pmaxuw", { XM, EXx }, PREFIX_OPCODE },
4398   },
4399
4400   /* PREFIX_0F383F */
4401   {
4402     { Bad_Opcode },
4403     { Bad_Opcode },
4404     { "pmaxud", { XM, EXx }, PREFIX_OPCODE },
4405   },
4406
4407   /* PREFIX_0F3840 */
4408   {
4409     { Bad_Opcode },
4410     { Bad_Opcode },
4411     { "pmulld", { XM, EXx }, PREFIX_OPCODE },
4412   },
4413
4414   /* PREFIX_0F3841 */
4415   {
4416     { Bad_Opcode },
4417     { Bad_Opcode },
4418     { "phminposuw", { XM, EXx }, PREFIX_OPCODE },
4419   },
4420
4421   /* PREFIX_0F3880 */
4422   {
4423     { Bad_Opcode },
4424     { Bad_Opcode },
4425     { "invept", { Gm, Mo }, PREFIX_OPCODE },
4426   },
4427
4428   /* PREFIX_0F3881 */
4429   {
4430     { Bad_Opcode },
4431     { Bad_Opcode },
4432     { "invvpid", { Gm, Mo }, PREFIX_OPCODE },
4433   },
4434
4435   /* PREFIX_0F3882 */
4436   {
4437     { Bad_Opcode },
4438     { Bad_Opcode },
4439     { "invpcid", { Gm, M }, PREFIX_OPCODE },
4440   },
4441
4442   /* PREFIX_0F38C8 */
4443   {
4444     { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4445   },
4446
4447   /* PREFIX_0F38C9 */
4448   {
4449     { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4450   },
4451
4452   /* PREFIX_0F38CA */
4453   {
4454     { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4455   },
4456
4457   /* PREFIX_0F38CB */
4458   {
4459     { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4460   },
4461
4462   /* PREFIX_0F38CC */
4463   {
4464     { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4465   },
4466
4467   /* PREFIX_0F38CD */
4468   {
4469     { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4470   },
4471
4472   /* PREFIX_0F38DB */
4473   {
4474     { Bad_Opcode },
4475     { Bad_Opcode },
4476     { "aesimc", { XM, EXx }, PREFIX_OPCODE },
4477   },
4478
4479   /* PREFIX_0F38DC */
4480   {
4481     { Bad_Opcode },
4482     { Bad_Opcode },
4483     { "aesenc", { XM, EXx }, PREFIX_OPCODE },
4484   },
4485
4486   /* PREFIX_0F38DD */
4487   {
4488     { Bad_Opcode },
4489     { Bad_Opcode },
4490     { "aesenclast", { XM, EXx }, PREFIX_OPCODE },
4491   },
4492
4493   /* PREFIX_0F38DE */
4494   {
4495     { Bad_Opcode },
4496     { Bad_Opcode },
4497     { "aesdec", { XM, EXx }, PREFIX_OPCODE },
4498   },
4499
4500   /* PREFIX_0F38DF */
4501   {
4502     { Bad_Opcode },
4503     { Bad_Opcode },
4504     { "aesdeclast", { XM, EXx }, PREFIX_OPCODE },
4505   },
4506
4507   /* PREFIX_0F38F0 */
4508   {
4509     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4510     { Bad_Opcode },
4511     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4512     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE },
4513   },
4514
4515   /* PREFIX_0F38F1 */
4516   {
4517     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4518     { Bad_Opcode },
4519     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4520     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE },
4521   },
4522
4523   /* PREFIX_0F38F6 */
4524   {
4525     { Bad_Opcode },
4526     { "adoxS",  { Gdq, Edq}, PREFIX_OPCODE },
4527     { "adcxS",  { Gdq, Edq}, PREFIX_OPCODE },
4528     { Bad_Opcode },
4529   },
4530
4531   /* PREFIX_0F3A08 */
4532   {
4533     { Bad_Opcode },
4534     { Bad_Opcode },
4535     { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE },
4536   },
4537
4538   /* PREFIX_0F3A09 */
4539   {
4540     { Bad_Opcode },
4541     { Bad_Opcode },
4542     { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4543   },
4544
4545   /* PREFIX_0F3A0A */
4546   {
4547     { Bad_Opcode },
4548     { Bad_Opcode },
4549     { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE },
4550   },
4551
4552   /* PREFIX_0F3A0B */
4553   {
4554     { Bad_Opcode },
4555     { Bad_Opcode },
4556     { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE },
4557   },
4558
4559   /* PREFIX_0F3A0C */
4560   {
4561     { Bad_Opcode },
4562     { Bad_Opcode },
4563     { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE },
4564   },
4565
4566   /* PREFIX_0F3A0D */
4567   {
4568     { Bad_Opcode },
4569     { Bad_Opcode },
4570     { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4571   },
4572
4573   /* PREFIX_0F3A0E */
4574   {
4575     { Bad_Opcode },
4576     { Bad_Opcode },
4577     { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE },
4578   },
4579
4580   /* PREFIX_0F3A14 */
4581   {
4582     { Bad_Opcode },
4583     { Bad_Opcode },
4584     { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE },
4585   },
4586
4587   /* PREFIX_0F3A15 */
4588   {
4589     { Bad_Opcode },
4590     { Bad_Opcode },
4591     { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE },
4592   },
4593
4594   /* PREFIX_0F3A16 */
4595   {
4596     { Bad_Opcode },
4597     { Bad_Opcode },
4598     { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE },
4599   },
4600
4601   /* PREFIX_0F3A17 */
4602   {
4603     { Bad_Opcode },
4604     { Bad_Opcode },
4605     { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE },
4606   },
4607
4608   /* PREFIX_0F3A20 */
4609   {
4610     { Bad_Opcode },
4611     { Bad_Opcode },
4612     { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE },
4613   },
4614
4615   /* PREFIX_0F3A21 */
4616   {
4617     { Bad_Opcode },
4618     { Bad_Opcode },
4619     { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE },
4620   },
4621
4622   /* PREFIX_0F3A22 */
4623   {
4624     { Bad_Opcode },
4625     { Bad_Opcode },
4626     { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE },
4627   },
4628
4629   /* PREFIX_0F3A40 */
4630   {
4631     { Bad_Opcode },
4632     { Bad_Opcode },
4633     { "dpps",   { XM, EXx, Ib }, PREFIX_OPCODE },
4634   },
4635
4636   /* PREFIX_0F3A41 */
4637   {
4638     { Bad_Opcode },
4639     { Bad_Opcode },
4640     { "dppd",   { XM, EXx, Ib }, PREFIX_OPCODE },
4641   },
4642
4643   /* PREFIX_0F3A42 */
4644   {
4645     { Bad_Opcode },
4646     { Bad_Opcode },
4647     { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE },
4648   },
4649
4650   /* PREFIX_0F3A44 */
4651   {
4652     { Bad_Opcode },
4653     { Bad_Opcode },
4654     { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE },
4655   },
4656
4657   /* PREFIX_0F3A60 */
4658   {
4659     { Bad_Opcode },
4660     { Bad_Opcode },
4661     { "pcmpestrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4662   },
4663
4664   /* PREFIX_0F3A61 */
4665   {
4666     { Bad_Opcode },
4667     { Bad_Opcode },
4668     { "pcmpestri", { XM, EXx, Ib }, PREFIX_OPCODE },
4669   },
4670
4671   /* PREFIX_0F3A62 */
4672   {
4673     { Bad_Opcode },
4674     { Bad_Opcode },
4675     { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4676   },
4677
4678   /* PREFIX_0F3A63 */
4679   {
4680     { Bad_Opcode },
4681     { Bad_Opcode },
4682     { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE },
4683   },
4684
4685   /* PREFIX_0F3ACC */
4686   {
4687     { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4688   },
4689
4690   /* PREFIX_0F3ADF */
4691   {
4692     { Bad_Opcode },
4693     { Bad_Opcode },
4694     { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE },
4695   },
4696
4697   /* PREFIX_VEX_0F10 */
4698   {
4699     { VEX_W_TABLE (VEX_W_0F10_P_0) },
4700     { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) },
4701     { VEX_W_TABLE (VEX_W_0F10_P_2) },
4702     { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) },
4703   },
4704
4705   /* PREFIX_VEX_0F11 */
4706   {
4707     { VEX_W_TABLE (VEX_W_0F11_P_0) },
4708     { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) },
4709     { VEX_W_TABLE (VEX_W_0F11_P_2) },
4710     { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) },
4711   },
4712
4713   /* PREFIX_VEX_0F12 */
4714   {
4715     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4716     { VEX_W_TABLE (VEX_W_0F12_P_1) },
4717     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
4718     { VEX_W_TABLE (VEX_W_0F12_P_3) },
4719   },
4720
4721   /* PREFIX_VEX_0F16 */
4722   {
4723     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4724     { VEX_W_TABLE (VEX_W_0F16_P_1) },
4725     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
4726   },
4727
4728   /* PREFIX_VEX_0F2A */
4729   {
4730     { Bad_Opcode },
4731     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) },
4732     { Bad_Opcode },
4733     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) },
4734   },
4735
4736   /* PREFIX_VEX_0F2C */
4737   {
4738     { Bad_Opcode },
4739     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) },
4740     { Bad_Opcode },
4741     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) },
4742   },
4743
4744   /* PREFIX_VEX_0F2D */
4745   {
4746     { Bad_Opcode },
4747     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) },
4748     { Bad_Opcode },
4749     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) },
4750   },
4751
4752   /* PREFIX_VEX_0F2E */
4753   {
4754     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) },
4755     { Bad_Opcode },
4756     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) },
4757   },
4758
4759   /* PREFIX_VEX_0F2F */
4760   {
4761     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) },
4762     { Bad_Opcode },
4763     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) },
4764   },
4765
4766   /* PREFIX_VEX_0F41 */
4767   {
4768     { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4769     { Bad_Opcode },
4770     { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4771   },
4772
4773   /* PREFIX_VEX_0F42 */
4774   {
4775     { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4776     { Bad_Opcode },
4777     { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4778   },
4779
4780   /* PREFIX_VEX_0F44 */
4781   {
4782     { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4783     { Bad_Opcode },
4784     { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4785   },
4786
4787   /* PREFIX_VEX_0F45 */
4788   {
4789     { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4790     { Bad_Opcode },
4791     { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4792   },
4793
4794   /* PREFIX_VEX_0F46 */
4795   {
4796     { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4797     { Bad_Opcode },
4798     { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4799   },
4800
4801   /* PREFIX_VEX_0F47 */
4802   {
4803     { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4804     { Bad_Opcode },
4805     { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
4806   },
4807
4808   /* PREFIX_VEX_0F4A */
4809   {
4810     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
4811     { Bad_Opcode },
4812     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
4813   },
4814
4815   /* PREFIX_VEX_0F4B */
4816   {
4817     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
4818     { Bad_Opcode },
4819     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4820   },
4821
4822   /* PREFIX_VEX_0F51 */
4823   {
4824     { VEX_W_TABLE (VEX_W_0F51_P_0) },
4825     { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) },
4826     { VEX_W_TABLE (VEX_W_0F51_P_2) },
4827     { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) },
4828   },
4829
4830   /* PREFIX_VEX_0F52 */
4831   {
4832     { VEX_W_TABLE (VEX_W_0F52_P_0) },
4833     { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) },
4834   },
4835
4836   /* PREFIX_VEX_0F53 */
4837   {
4838     { VEX_W_TABLE (VEX_W_0F53_P_0) },
4839     { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) },
4840   },
4841
4842   /* PREFIX_VEX_0F58 */
4843   {
4844     { VEX_W_TABLE (VEX_W_0F58_P_0) },
4845     { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) },
4846     { VEX_W_TABLE (VEX_W_0F58_P_2) },
4847     { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) },
4848   },
4849
4850   /* PREFIX_VEX_0F59 */
4851   {
4852     { VEX_W_TABLE (VEX_W_0F59_P_0) },
4853     { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) },
4854     { VEX_W_TABLE (VEX_W_0F59_P_2) },
4855     { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) },
4856   },
4857
4858   /* PREFIX_VEX_0F5A */
4859   {
4860     { VEX_W_TABLE (VEX_W_0F5A_P_0) },
4861     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) },
4862     { "vcvtpd2ps%XY", { XMM, EXx }, 0 },
4863     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) },
4864   },
4865
4866   /* PREFIX_VEX_0F5B */
4867   {
4868     { VEX_W_TABLE (VEX_W_0F5B_P_0) },
4869     { VEX_W_TABLE (VEX_W_0F5B_P_1) },
4870     { VEX_W_TABLE (VEX_W_0F5B_P_2) },
4871   },
4872
4873   /* PREFIX_VEX_0F5C */
4874   {
4875     { VEX_W_TABLE (VEX_W_0F5C_P_0) },
4876     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) },
4877     { VEX_W_TABLE (VEX_W_0F5C_P_2) },
4878     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) },
4879   },
4880
4881   /* PREFIX_VEX_0F5D */
4882   {
4883     { VEX_W_TABLE (VEX_W_0F5D_P_0) },
4884     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) },
4885     { VEX_W_TABLE (VEX_W_0F5D_P_2) },
4886     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) },
4887   },
4888
4889   /* PREFIX_VEX_0F5E */
4890   {
4891     { VEX_W_TABLE (VEX_W_0F5E_P_0) },
4892     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) },
4893     { VEX_W_TABLE (VEX_W_0F5E_P_2) },
4894     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) },
4895   },
4896
4897   /* PREFIX_VEX_0F5F */
4898   {
4899     { VEX_W_TABLE (VEX_W_0F5F_P_0) },
4900     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) },
4901     { VEX_W_TABLE (VEX_W_0F5F_P_2) },
4902     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) },
4903   },
4904
4905   /* PREFIX_VEX_0F60 */
4906   {
4907     { Bad_Opcode },
4908     { Bad_Opcode },
4909     { VEX_W_TABLE (VEX_W_0F60_P_2) },
4910   },
4911
4912   /* PREFIX_VEX_0F61 */
4913   {
4914     { Bad_Opcode },
4915     { Bad_Opcode },
4916     { VEX_W_TABLE (VEX_W_0F61_P_2) },
4917   },
4918
4919   /* PREFIX_VEX_0F62 */
4920   {
4921     { Bad_Opcode },
4922     { Bad_Opcode },
4923     { VEX_W_TABLE (VEX_W_0F62_P_2) },
4924   },
4925
4926   /* PREFIX_VEX_0F63 */
4927   {
4928     { Bad_Opcode },
4929     { Bad_Opcode },
4930     { VEX_W_TABLE (VEX_W_0F63_P_2) },
4931   },
4932
4933   /* PREFIX_VEX_0F64 */
4934   {
4935     { Bad_Opcode },
4936     { Bad_Opcode },
4937     { VEX_W_TABLE (VEX_W_0F64_P_2) },
4938   },
4939
4940   /* PREFIX_VEX_0F65 */
4941   {
4942     { Bad_Opcode },
4943     { Bad_Opcode },
4944     { VEX_W_TABLE (VEX_W_0F65_P_2) },
4945   },
4946
4947   /* PREFIX_VEX_0F66 */
4948   {
4949     { Bad_Opcode },
4950     { Bad_Opcode },
4951     { VEX_W_TABLE (VEX_W_0F66_P_2) },
4952   },
4953
4954   /* PREFIX_VEX_0F67 */
4955   {
4956     { Bad_Opcode },
4957     { Bad_Opcode },
4958     { VEX_W_TABLE (VEX_W_0F67_P_2) },
4959   },
4960
4961   /* PREFIX_VEX_0F68 */
4962   {
4963     { Bad_Opcode },
4964     { Bad_Opcode },
4965     { VEX_W_TABLE (VEX_W_0F68_P_2) },
4966   },
4967
4968   /* PREFIX_VEX_0F69 */
4969   {
4970     { Bad_Opcode },
4971     { Bad_Opcode },
4972     { VEX_W_TABLE (VEX_W_0F69_P_2) },
4973   },
4974
4975   /* PREFIX_VEX_0F6A */
4976   {
4977     { Bad_Opcode },
4978     { Bad_Opcode },
4979     { VEX_W_TABLE (VEX_W_0F6A_P_2) },
4980   },
4981
4982   /* PREFIX_VEX_0F6B */
4983   {
4984     { Bad_Opcode },
4985     { Bad_Opcode },
4986     { VEX_W_TABLE (VEX_W_0F6B_P_2) },
4987   },
4988
4989   /* PREFIX_VEX_0F6C */
4990   {
4991     { Bad_Opcode },
4992     { Bad_Opcode },
4993     { VEX_W_TABLE (VEX_W_0F6C_P_2) },
4994   },
4995
4996   /* PREFIX_VEX_0F6D */
4997   {
4998     { Bad_Opcode },
4999     { Bad_Opcode },
5000     { VEX_W_TABLE (VEX_W_0F6D_P_2) },
5001   },
5002
5003   /* PREFIX_VEX_0F6E */
5004   {
5005     { Bad_Opcode },
5006     { Bad_Opcode },
5007     { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
5008   },
5009
5010   /* PREFIX_VEX_0F6F */
5011   {
5012     { Bad_Opcode },
5013     { VEX_W_TABLE (VEX_W_0F6F_P_1) },
5014     { VEX_W_TABLE (VEX_W_0F6F_P_2) },
5015   },
5016
5017   /* PREFIX_VEX_0F70 */
5018   {
5019     { Bad_Opcode },
5020     { VEX_W_TABLE (VEX_W_0F70_P_1) },
5021     { VEX_W_TABLE (VEX_W_0F70_P_2) },
5022     { VEX_W_TABLE (VEX_W_0F70_P_3) },
5023   },
5024
5025   /* PREFIX_VEX_0F71_REG_2 */
5026   {
5027     { Bad_Opcode },
5028     { Bad_Opcode },
5029     { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) },
5030   },
5031
5032   /* PREFIX_VEX_0F71_REG_4 */
5033   {
5034     { Bad_Opcode },
5035     { Bad_Opcode },
5036     { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) },
5037   },
5038
5039   /* PREFIX_VEX_0F71_REG_6 */
5040   {
5041     { Bad_Opcode },
5042     { Bad_Opcode },
5043     { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) },
5044   },
5045
5046   /* PREFIX_VEX_0F72_REG_2 */
5047   {
5048     { Bad_Opcode },
5049     { Bad_Opcode },
5050     { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) },
5051   },
5052
5053   /* PREFIX_VEX_0F72_REG_4 */
5054   {
5055     { Bad_Opcode },
5056     { Bad_Opcode },
5057     { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) },
5058   },
5059
5060   /* PREFIX_VEX_0F72_REG_6 */
5061   {
5062     { Bad_Opcode },
5063     { Bad_Opcode },
5064     { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) },
5065   },
5066
5067   /* PREFIX_VEX_0F73_REG_2 */
5068   {
5069     { Bad_Opcode },
5070     { Bad_Opcode },
5071     { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) },
5072   },
5073
5074   /* PREFIX_VEX_0F73_REG_3 */
5075   {
5076     { Bad_Opcode },
5077     { Bad_Opcode },
5078     { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) },
5079   },
5080
5081   /* PREFIX_VEX_0F73_REG_6 */
5082   {
5083     { Bad_Opcode },
5084     { Bad_Opcode },
5085     { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) },
5086   },
5087
5088   /* PREFIX_VEX_0F73_REG_7 */
5089   {
5090     { Bad_Opcode },
5091     { Bad_Opcode },
5092     { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) },
5093   },
5094
5095   /* PREFIX_VEX_0F74 */
5096   {
5097     { Bad_Opcode },
5098     { Bad_Opcode },
5099     { VEX_W_TABLE (VEX_W_0F74_P_2) },
5100   },
5101
5102   /* PREFIX_VEX_0F75 */
5103   {
5104     { Bad_Opcode },
5105     { Bad_Opcode },
5106     { VEX_W_TABLE (VEX_W_0F75_P_2) },
5107   },
5108
5109   /* PREFIX_VEX_0F76 */
5110   {
5111     { Bad_Opcode },
5112     { Bad_Opcode },
5113     { VEX_W_TABLE (VEX_W_0F76_P_2) },
5114   },
5115
5116   /* PREFIX_VEX_0F77 */
5117   {
5118     { VEX_W_TABLE (VEX_W_0F77_P_0) },
5119   },
5120
5121   /* PREFIX_VEX_0F7C */
5122   {
5123     { Bad_Opcode },
5124     { Bad_Opcode },
5125     { VEX_W_TABLE (VEX_W_0F7C_P_2) },
5126     { VEX_W_TABLE (VEX_W_0F7C_P_3) },
5127   },
5128
5129   /* PREFIX_VEX_0F7D */
5130   {
5131     { Bad_Opcode },
5132     { Bad_Opcode },
5133     { VEX_W_TABLE (VEX_W_0F7D_P_2) },
5134     { VEX_W_TABLE (VEX_W_0F7D_P_3) },
5135   },
5136
5137   /* PREFIX_VEX_0F7E */
5138   {
5139     { Bad_Opcode },
5140     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
5141     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
5142   },
5143
5144   /* PREFIX_VEX_0F7F */
5145   {
5146     { Bad_Opcode },
5147     { VEX_W_TABLE (VEX_W_0F7F_P_1) },
5148     { VEX_W_TABLE (VEX_W_0F7F_P_2) },
5149   },
5150
5151   /* PREFIX_VEX_0F90 */
5152   {
5153     { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
5154     { Bad_Opcode },
5155     { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
5156   },
5157
5158   /* PREFIX_VEX_0F91 */
5159   {
5160     { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
5161     { Bad_Opcode },
5162     { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
5163   },
5164
5165   /* PREFIX_VEX_0F92 */
5166   {
5167     { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
5168     { Bad_Opcode },
5169     { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
5170     { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
5171   },
5172
5173   /* PREFIX_VEX_0F93 */
5174   {
5175     { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
5176     { Bad_Opcode },
5177     { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
5178     { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
5179   },
5180
5181   /* PREFIX_VEX_0F98 */
5182   {
5183     { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
5184     { Bad_Opcode },
5185     { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
5186   },
5187
5188   /* PREFIX_VEX_0F99 */
5189   {
5190     { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5191     { Bad_Opcode },
5192     { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5193   },
5194
5195   /* PREFIX_VEX_0FC2 */
5196   {
5197     { VEX_W_TABLE (VEX_W_0FC2_P_0) },
5198     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) },
5199     { VEX_W_TABLE (VEX_W_0FC2_P_2) },
5200     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) },
5201   },
5202
5203   /* PREFIX_VEX_0FC4 */
5204   {
5205     { Bad_Opcode },
5206     { Bad_Opcode },
5207     { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5208   },
5209
5210   /* PREFIX_VEX_0FC5 */
5211   {
5212     { Bad_Opcode },
5213     { Bad_Opcode },
5214     { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5215   },
5216
5217   /* PREFIX_VEX_0FD0 */
5218   {
5219     { Bad_Opcode },
5220     { Bad_Opcode },
5221     { VEX_W_TABLE (VEX_W_0FD0_P_2) },
5222     { VEX_W_TABLE (VEX_W_0FD0_P_3) },
5223   },
5224
5225   /* PREFIX_VEX_0FD1 */
5226   {
5227     { Bad_Opcode },
5228     { Bad_Opcode },
5229     { VEX_W_TABLE (VEX_W_0FD1_P_2) },
5230   },
5231
5232   /* PREFIX_VEX_0FD2 */
5233   {
5234     { Bad_Opcode },
5235     { Bad_Opcode },
5236     { VEX_W_TABLE (VEX_W_0FD2_P_2) },
5237   },
5238
5239   /* PREFIX_VEX_0FD3 */
5240   {
5241     { Bad_Opcode },
5242     { Bad_Opcode },
5243     { VEX_W_TABLE (VEX_W_0FD3_P_2) },
5244   },
5245
5246   /* PREFIX_VEX_0FD4 */
5247   {
5248     { Bad_Opcode },
5249     { Bad_Opcode },
5250     { VEX_W_TABLE (VEX_W_0FD4_P_2) },
5251   },
5252
5253   /* PREFIX_VEX_0FD5 */
5254   {
5255     { Bad_Opcode },
5256     { Bad_Opcode },
5257     { VEX_W_TABLE (VEX_W_0FD5_P_2) },
5258   },
5259
5260   /* PREFIX_VEX_0FD6 */
5261   {
5262     { Bad_Opcode },
5263     { Bad_Opcode },
5264     { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5265   },
5266
5267   /* PREFIX_VEX_0FD7 */
5268   {
5269     { Bad_Opcode },
5270     { Bad_Opcode },
5271     { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5272   },
5273
5274   /* PREFIX_VEX_0FD8 */
5275   {
5276     { Bad_Opcode },
5277     { Bad_Opcode },
5278     { VEX_W_TABLE (VEX_W_0FD8_P_2) },
5279   },
5280
5281   /* PREFIX_VEX_0FD9 */
5282   {
5283     { Bad_Opcode },
5284     { Bad_Opcode },
5285     { VEX_W_TABLE (VEX_W_0FD9_P_2) },
5286   },
5287
5288   /* PREFIX_VEX_0FDA */
5289   {
5290     { Bad_Opcode },
5291     { Bad_Opcode },
5292     { VEX_W_TABLE (VEX_W_0FDA_P_2) },
5293   },
5294
5295   /* PREFIX_VEX_0FDB */
5296   {
5297     { Bad_Opcode },
5298     { Bad_Opcode },
5299     { VEX_W_TABLE (VEX_W_0FDB_P_2) },
5300   },
5301
5302   /* PREFIX_VEX_0FDC */
5303   {
5304     { Bad_Opcode },
5305     { Bad_Opcode },
5306     { VEX_W_TABLE (VEX_W_0FDC_P_2) },
5307   },
5308
5309   /* PREFIX_VEX_0FDD */
5310   {
5311     { Bad_Opcode },
5312     { Bad_Opcode },
5313     { VEX_W_TABLE (VEX_W_0FDD_P_2) },
5314   },
5315
5316   /* PREFIX_VEX_0FDE */
5317   {
5318     { Bad_Opcode },
5319     { Bad_Opcode },
5320     { VEX_W_TABLE (VEX_W_0FDE_P_2) },
5321   },
5322
5323   /* PREFIX_VEX_0FDF */
5324   {
5325     { Bad_Opcode },
5326     { Bad_Opcode },
5327     { VEX_W_TABLE (VEX_W_0FDF_P_2) },
5328   },
5329
5330   /* PREFIX_VEX_0FE0 */
5331   {
5332     { Bad_Opcode },
5333     { Bad_Opcode },
5334     { VEX_W_TABLE (VEX_W_0FE0_P_2) },
5335   },
5336
5337   /* PREFIX_VEX_0FE1 */
5338   {
5339     { Bad_Opcode },
5340     { Bad_Opcode },
5341     { VEX_W_TABLE (VEX_W_0FE1_P_2) },
5342   },
5343
5344   /* PREFIX_VEX_0FE2 */
5345   {
5346     { Bad_Opcode },
5347     { Bad_Opcode },
5348     { VEX_W_TABLE (VEX_W_0FE2_P_2) },
5349   },
5350
5351   /* PREFIX_VEX_0FE3 */
5352   {
5353     { Bad_Opcode },
5354     { Bad_Opcode },
5355     { VEX_W_TABLE (VEX_W_0FE3_P_2) },
5356   },
5357
5358   /* PREFIX_VEX_0FE4 */
5359   {
5360     { Bad_Opcode },
5361     { Bad_Opcode },
5362     { VEX_W_TABLE (VEX_W_0FE4_P_2) },
5363   },
5364
5365   /* PREFIX_VEX_0FE5 */
5366   {
5367     { Bad_Opcode },
5368     { Bad_Opcode },
5369     { VEX_W_TABLE (VEX_W_0FE5_P_2) },
5370   },
5371
5372   /* PREFIX_VEX_0FE6 */
5373   {
5374     { Bad_Opcode },
5375     { VEX_W_TABLE (VEX_W_0FE6_P_1) },
5376     { VEX_W_TABLE (VEX_W_0FE6_P_2) },
5377     { VEX_W_TABLE (VEX_W_0FE6_P_3) },
5378   },
5379
5380   /* PREFIX_VEX_0FE7 */
5381   {
5382     { Bad_Opcode },
5383     { Bad_Opcode },
5384     { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5385   },
5386
5387   /* PREFIX_VEX_0FE8 */
5388   {
5389     { Bad_Opcode },
5390     { Bad_Opcode },
5391     { VEX_W_TABLE (VEX_W_0FE8_P_2) },
5392   },
5393
5394   /* PREFIX_VEX_0FE9 */
5395   {
5396     { Bad_Opcode },
5397     { Bad_Opcode },
5398     { VEX_W_TABLE (VEX_W_0FE9_P_2) },
5399   },
5400
5401   /* PREFIX_VEX_0FEA */
5402   {
5403     { Bad_Opcode },
5404     { Bad_Opcode },
5405     { VEX_W_TABLE (VEX_W_0FEA_P_2) },
5406   },
5407
5408   /* PREFIX_VEX_0FEB */
5409   {
5410     { Bad_Opcode },
5411     { Bad_Opcode },
5412     { VEX_W_TABLE (VEX_W_0FEB_P_2) },
5413   },
5414
5415   /* PREFIX_VEX_0FEC */
5416   {
5417     { Bad_Opcode },
5418     { Bad_Opcode },
5419     { VEX_W_TABLE (VEX_W_0FEC_P_2) },
5420   },
5421
5422   /* PREFIX_VEX_0FED */
5423   {
5424     { Bad_Opcode },
5425     { Bad_Opcode },
5426     { VEX_W_TABLE (VEX_W_0FED_P_2) },
5427   },
5428
5429   /* PREFIX_VEX_0FEE */
5430   {
5431     { Bad_Opcode },
5432     { Bad_Opcode },
5433     { VEX_W_TABLE (VEX_W_0FEE_P_2) },
5434   },
5435
5436   /* PREFIX_VEX_0FEF */
5437   {
5438     { Bad_Opcode },
5439     { Bad_Opcode },
5440     { VEX_W_TABLE (VEX_W_0FEF_P_2) },
5441   },
5442
5443   /* PREFIX_VEX_0FF0 */
5444   {
5445     { Bad_Opcode },
5446     { Bad_Opcode },
5447     { Bad_Opcode },
5448     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5449   },
5450
5451   /* PREFIX_VEX_0FF1 */
5452   {
5453     { Bad_Opcode },
5454     { Bad_Opcode },
5455     { VEX_W_TABLE (VEX_W_0FF1_P_2) },
5456   },
5457
5458   /* PREFIX_VEX_0FF2 */
5459   {
5460     { Bad_Opcode },
5461     { Bad_Opcode },
5462     { VEX_W_TABLE (VEX_W_0FF2_P_2) },
5463   },
5464
5465   /* PREFIX_VEX_0FF3 */
5466   {
5467     { Bad_Opcode },
5468     { Bad_Opcode },
5469     { VEX_W_TABLE (VEX_W_0FF3_P_2) },
5470   },
5471
5472   /* PREFIX_VEX_0FF4 */
5473   {
5474     { Bad_Opcode },
5475     { Bad_Opcode },
5476     { VEX_W_TABLE (VEX_W_0FF4_P_2) },
5477   },
5478
5479   /* PREFIX_VEX_0FF5 */
5480   {
5481     { Bad_Opcode },
5482     { Bad_Opcode },
5483     { VEX_W_TABLE (VEX_W_0FF5_P_2) },
5484   },
5485
5486   /* PREFIX_VEX_0FF6 */
5487   {
5488     { Bad_Opcode },
5489     { Bad_Opcode },
5490     { VEX_W_TABLE (VEX_W_0FF6_P_2) },
5491   },
5492
5493   /* PREFIX_VEX_0FF7 */
5494   {
5495     { Bad_Opcode },
5496     { Bad_Opcode },
5497     { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5498   },
5499
5500   /* PREFIX_VEX_0FF8 */
5501   {
5502     { Bad_Opcode },
5503     { Bad_Opcode },
5504     { VEX_W_TABLE (VEX_W_0FF8_P_2) },
5505   },
5506
5507   /* PREFIX_VEX_0FF9 */
5508   {
5509     { Bad_Opcode },
5510     { Bad_Opcode },
5511     { VEX_W_TABLE (VEX_W_0FF9_P_2) },
5512   },
5513
5514   /* PREFIX_VEX_0FFA */
5515   {
5516     { Bad_Opcode },
5517     { Bad_Opcode },
5518     { VEX_W_TABLE (VEX_W_0FFA_P_2) },
5519   },
5520
5521   /* PREFIX_VEX_0FFB */
5522   {
5523     { Bad_Opcode },
5524     { Bad_Opcode },
5525     { VEX_W_TABLE (VEX_W_0FFB_P_2) },
5526   },
5527
5528   /* PREFIX_VEX_0FFC */
5529   {
5530     { Bad_Opcode },
5531     { Bad_Opcode },
5532     { VEX_W_TABLE (VEX_W_0FFC_P_2) },
5533   },
5534
5535   /* PREFIX_VEX_0FFD */
5536   {
5537     { Bad_Opcode },
5538     { Bad_Opcode },
5539     { VEX_W_TABLE (VEX_W_0FFD_P_2) },
5540   },
5541
5542   /* PREFIX_VEX_0FFE */
5543   {
5544     { Bad_Opcode },
5545     { Bad_Opcode },
5546     { VEX_W_TABLE (VEX_W_0FFE_P_2) },
5547   },
5548
5549   /* PREFIX_VEX_0F3800 */
5550   {
5551     { Bad_Opcode },
5552     { Bad_Opcode },
5553     { VEX_W_TABLE (VEX_W_0F3800_P_2) },
5554   },
5555
5556   /* PREFIX_VEX_0F3801 */
5557   {
5558     { Bad_Opcode },
5559     { Bad_Opcode },
5560     { VEX_W_TABLE (VEX_W_0F3801_P_2) },
5561   },
5562
5563   /* PREFIX_VEX_0F3802 */
5564   {
5565     { Bad_Opcode },
5566     { Bad_Opcode },
5567     { VEX_W_TABLE (VEX_W_0F3802_P_2) },
5568   },
5569
5570   /* PREFIX_VEX_0F3803 */
5571   {
5572     { Bad_Opcode },
5573     { Bad_Opcode },
5574     { VEX_W_TABLE (VEX_W_0F3803_P_2) },
5575   },
5576
5577   /* PREFIX_VEX_0F3804 */
5578   {
5579     { Bad_Opcode },
5580     { Bad_Opcode },
5581     { VEX_W_TABLE (VEX_W_0F3804_P_2) },
5582   },
5583
5584   /* PREFIX_VEX_0F3805 */
5585   {
5586     { Bad_Opcode },
5587     { Bad_Opcode },
5588     { VEX_W_TABLE (VEX_W_0F3805_P_2) },
5589   },
5590
5591   /* PREFIX_VEX_0F3806 */
5592   {
5593     { Bad_Opcode },
5594     { Bad_Opcode },
5595     { VEX_W_TABLE (VEX_W_0F3806_P_2) },
5596   },
5597
5598   /* PREFIX_VEX_0F3807 */
5599   {
5600     { Bad_Opcode },
5601     { Bad_Opcode },
5602     { VEX_W_TABLE (VEX_W_0F3807_P_2) },
5603   },
5604
5605   /* PREFIX_VEX_0F3808 */
5606   {
5607     { Bad_Opcode },
5608     { Bad_Opcode },
5609     { VEX_W_TABLE (VEX_W_0F3808_P_2) },
5610   },
5611
5612   /* PREFIX_VEX_0F3809 */
5613   {
5614     { Bad_Opcode },
5615     { Bad_Opcode },
5616     { VEX_W_TABLE (VEX_W_0F3809_P_2) },
5617   },
5618
5619   /* PREFIX_VEX_0F380A */
5620   {
5621     { Bad_Opcode },
5622     { Bad_Opcode },
5623     { VEX_W_TABLE (VEX_W_0F380A_P_2) },
5624   },
5625
5626   /* PREFIX_VEX_0F380B */
5627   {
5628     { Bad_Opcode },
5629     { Bad_Opcode },
5630     { VEX_W_TABLE (VEX_W_0F380B_P_2) },
5631   },
5632
5633   /* PREFIX_VEX_0F380C */
5634   {
5635     { Bad_Opcode },
5636     { Bad_Opcode },
5637     { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5638   },
5639
5640   /* PREFIX_VEX_0F380D */
5641   {
5642     { Bad_Opcode },
5643     { Bad_Opcode },
5644     { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5645   },
5646
5647   /* PREFIX_VEX_0F380E */
5648   {
5649     { Bad_Opcode },
5650     { Bad_Opcode },
5651     { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5652   },
5653
5654   /* PREFIX_VEX_0F380F */
5655   {
5656     { Bad_Opcode },
5657     { Bad_Opcode },
5658     { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5659   },
5660
5661   /* PREFIX_VEX_0F3813 */
5662   {
5663     { Bad_Opcode },
5664     { Bad_Opcode },
5665     { "vcvtph2ps", { XM, EXxmmq }, 0 },
5666   },
5667
5668   /* PREFIX_VEX_0F3816 */
5669   {
5670     { Bad_Opcode },
5671     { Bad_Opcode },
5672     { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5673   },
5674
5675   /* PREFIX_VEX_0F3817 */
5676   {
5677     { Bad_Opcode },
5678     { Bad_Opcode },
5679     { VEX_W_TABLE (VEX_W_0F3817_P_2) },
5680   },
5681
5682   /* PREFIX_VEX_0F3818 */
5683   {
5684     { Bad_Opcode },
5685     { Bad_Opcode },
5686     { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5687   },
5688
5689   /* PREFIX_VEX_0F3819 */
5690   {
5691     { Bad_Opcode },
5692     { Bad_Opcode },
5693     { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5694   },
5695
5696   /* PREFIX_VEX_0F381A */
5697   {
5698     { Bad_Opcode },
5699     { Bad_Opcode },
5700     { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5701   },
5702
5703   /* PREFIX_VEX_0F381C */
5704   {
5705     { Bad_Opcode },
5706     { Bad_Opcode },
5707     { VEX_W_TABLE (VEX_W_0F381C_P_2) },
5708   },
5709
5710   /* PREFIX_VEX_0F381D */
5711   {
5712     { Bad_Opcode },
5713     { Bad_Opcode },
5714     { VEX_W_TABLE (VEX_W_0F381D_P_2) },
5715   },
5716
5717   /* PREFIX_VEX_0F381E */
5718   {
5719     { Bad_Opcode },
5720     { Bad_Opcode },
5721     { VEX_W_TABLE (VEX_W_0F381E_P_2) },
5722   },
5723
5724   /* PREFIX_VEX_0F3820 */
5725   {
5726     { Bad_Opcode },
5727     { Bad_Opcode },
5728     { VEX_W_TABLE (VEX_W_0F3820_P_2) },
5729   },
5730
5731   /* PREFIX_VEX_0F3821 */
5732   {
5733     { Bad_Opcode },
5734     { Bad_Opcode },
5735     { VEX_W_TABLE (VEX_W_0F3821_P_2) },
5736   },
5737
5738   /* PREFIX_VEX_0F3822 */
5739   {
5740     { Bad_Opcode },
5741     { Bad_Opcode },
5742     { VEX_W_TABLE (VEX_W_0F3822_P_2) },
5743   },
5744
5745   /* PREFIX_VEX_0F3823 */
5746   {
5747     { Bad_Opcode },
5748     { Bad_Opcode },
5749     { VEX_W_TABLE (VEX_W_0F3823_P_2) },
5750   },
5751
5752   /* PREFIX_VEX_0F3824 */
5753   {
5754     { Bad_Opcode },
5755     { Bad_Opcode },
5756     { VEX_W_TABLE (VEX_W_0F3824_P_2) },
5757   },
5758
5759   /* PREFIX_VEX_0F3825 */
5760   {
5761     { Bad_Opcode },
5762     { Bad_Opcode },
5763     { VEX_W_TABLE (VEX_W_0F3825_P_2) },
5764   },
5765
5766   /* PREFIX_VEX_0F3828 */
5767   {
5768     { Bad_Opcode },
5769     { Bad_Opcode },
5770     { VEX_W_TABLE (VEX_W_0F3828_P_2) },
5771   },
5772
5773   /* PREFIX_VEX_0F3829 */
5774   {
5775     { Bad_Opcode },
5776     { Bad_Opcode },
5777     { VEX_W_TABLE (VEX_W_0F3829_P_2) },
5778   },
5779
5780   /* PREFIX_VEX_0F382A */
5781   {
5782     { Bad_Opcode },
5783     { Bad_Opcode },
5784     { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5785   },
5786
5787   /* PREFIX_VEX_0F382B */
5788   {
5789     { Bad_Opcode },
5790     { Bad_Opcode },
5791     { VEX_W_TABLE (VEX_W_0F382B_P_2) },
5792   },
5793
5794   /* PREFIX_VEX_0F382C */
5795   {
5796     { Bad_Opcode },
5797     { Bad_Opcode },
5798      { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5799   },
5800
5801   /* PREFIX_VEX_0F382D */
5802   {
5803     { Bad_Opcode },
5804     { Bad_Opcode },
5805      { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5806   },
5807
5808   /* PREFIX_VEX_0F382E */
5809   {
5810     { Bad_Opcode },
5811     { Bad_Opcode },
5812      { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5813   },
5814
5815   /* PREFIX_VEX_0F382F */
5816   {
5817     { Bad_Opcode },
5818     { Bad_Opcode },
5819      { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5820   },
5821
5822   /* PREFIX_VEX_0F3830 */
5823   {
5824     { Bad_Opcode },
5825     { Bad_Opcode },
5826     { VEX_W_TABLE (VEX_W_0F3830_P_2) },
5827   },
5828
5829   /* PREFIX_VEX_0F3831 */
5830   {
5831     { Bad_Opcode },
5832     { Bad_Opcode },
5833     { VEX_W_TABLE (VEX_W_0F3831_P_2) },
5834   },
5835
5836   /* PREFIX_VEX_0F3832 */
5837   {
5838     { Bad_Opcode },
5839     { Bad_Opcode },
5840     { VEX_W_TABLE (VEX_W_0F3832_P_2) },
5841   },
5842
5843   /* PREFIX_VEX_0F3833 */
5844   {
5845     { Bad_Opcode },
5846     { Bad_Opcode },
5847     { VEX_W_TABLE (VEX_W_0F3833_P_2) },
5848   },
5849
5850   /* PREFIX_VEX_0F3834 */
5851   {
5852     { Bad_Opcode },
5853     { Bad_Opcode },
5854     { VEX_W_TABLE (VEX_W_0F3834_P_2) },
5855   },
5856
5857   /* PREFIX_VEX_0F3835 */
5858   {
5859     { Bad_Opcode },
5860     { Bad_Opcode },
5861     { VEX_W_TABLE (VEX_W_0F3835_P_2) },
5862   },
5863
5864   /* PREFIX_VEX_0F3836 */
5865   {
5866     { Bad_Opcode },
5867     { Bad_Opcode },
5868     { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5869   },
5870
5871   /* PREFIX_VEX_0F3837 */
5872   {
5873     { Bad_Opcode },
5874     { Bad_Opcode },
5875     { VEX_W_TABLE (VEX_W_0F3837_P_2) },
5876   },
5877
5878   /* PREFIX_VEX_0F3838 */
5879   {
5880     { Bad_Opcode },
5881     { Bad_Opcode },
5882     { VEX_W_TABLE (VEX_W_0F3838_P_2) },
5883   },
5884
5885   /* PREFIX_VEX_0F3839 */
5886   {
5887     { Bad_Opcode },
5888     { Bad_Opcode },
5889     { VEX_W_TABLE (VEX_W_0F3839_P_2) },
5890   },
5891
5892   /* PREFIX_VEX_0F383A */
5893   {
5894     { Bad_Opcode },
5895     { Bad_Opcode },
5896     { VEX_W_TABLE (VEX_W_0F383A_P_2) },
5897   },
5898
5899   /* PREFIX_VEX_0F383B */
5900   {
5901     { Bad_Opcode },
5902     { Bad_Opcode },
5903     { VEX_W_TABLE (VEX_W_0F383B_P_2) },
5904   },
5905
5906   /* PREFIX_VEX_0F383C */
5907   {
5908     { Bad_Opcode },
5909     { Bad_Opcode },
5910     { VEX_W_TABLE (VEX_W_0F383C_P_2) },
5911   },
5912
5913   /* PREFIX_VEX_0F383D */
5914   {
5915     { Bad_Opcode },
5916     { Bad_Opcode },
5917     { VEX_W_TABLE (VEX_W_0F383D_P_2) },
5918   },
5919
5920   /* PREFIX_VEX_0F383E */
5921   {
5922     { Bad_Opcode },
5923     { Bad_Opcode },
5924     { VEX_W_TABLE (VEX_W_0F383E_P_2) },
5925   },
5926
5927   /* PREFIX_VEX_0F383F */
5928   {
5929     { Bad_Opcode },
5930     { Bad_Opcode },
5931     { VEX_W_TABLE (VEX_W_0F383F_P_2) },
5932   },
5933
5934   /* PREFIX_VEX_0F3840 */
5935   {
5936     { Bad_Opcode },
5937     { Bad_Opcode },
5938     { VEX_W_TABLE (VEX_W_0F3840_P_2) },
5939   },
5940
5941   /* PREFIX_VEX_0F3841 */
5942   {
5943     { Bad_Opcode },
5944     { Bad_Opcode },
5945     { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
5946   },
5947
5948   /* PREFIX_VEX_0F3845 */
5949   {
5950     { Bad_Opcode },
5951     { Bad_Opcode },
5952     { "vpsrlv%LW", { XM, Vex, EXx }, 0 },
5953   },
5954
5955   /* PREFIX_VEX_0F3846 */
5956   {
5957     { Bad_Opcode },
5958     { Bad_Opcode },
5959     { VEX_W_TABLE (VEX_W_0F3846_P_2) },
5960   },
5961
5962   /* PREFIX_VEX_0F3847 */
5963   {
5964     { Bad_Opcode },
5965     { Bad_Opcode },
5966     { "vpsllv%LW", { XM, Vex, EXx }, 0 },
5967   },
5968
5969   /* PREFIX_VEX_0F3858 */
5970   {
5971     { Bad_Opcode },
5972     { Bad_Opcode },
5973     { VEX_W_TABLE (VEX_W_0F3858_P_2) },
5974   },
5975
5976   /* PREFIX_VEX_0F3859 */
5977   {
5978     { Bad_Opcode },
5979     { Bad_Opcode },
5980     { VEX_W_TABLE (VEX_W_0F3859_P_2) },
5981   },
5982
5983   /* PREFIX_VEX_0F385A */
5984   {
5985     { Bad_Opcode },
5986     { Bad_Opcode },
5987     { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
5988   },
5989
5990   /* PREFIX_VEX_0F3878 */
5991   {
5992     { Bad_Opcode },
5993     { Bad_Opcode },
5994     { VEX_W_TABLE (VEX_W_0F3878_P_2) },
5995   },
5996
5997   /* PREFIX_VEX_0F3879 */
5998   {
5999     { Bad_Opcode },
6000     { Bad_Opcode },
6001     { VEX_W_TABLE (VEX_W_0F3879_P_2) },
6002   },
6003
6004   /* PREFIX_VEX_0F388C */
6005   {
6006     { Bad_Opcode },
6007     { Bad_Opcode },
6008     { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
6009   },
6010
6011   /* PREFIX_VEX_0F388E */
6012   {
6013     { Bad_Opcode },
6014     { Bad_Opcode },
6015     { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
6016   },
6017
6018   /* PREFIX_VEX_0F3890 */
6019   {
6020     { Bad_Opcode },
6021     { Bad_Opcode },
6022     { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 },
6023   },
6024
6025   /* PREFIX_VEX_0F3891 */
6026   {
6027     { Bad_Opcode },
6028     { Bad_Opcode },
6029     { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6030   },
6031
6032   /* PREFIX_VEX_0F3892 */
6033   {
6034     { Bad_Opcode },
6035     { Bad_Opcode },
6036     { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 },
6037   },
6038
6039   /* PREFIX_VEX_0F3893 */
6040   {
6041     { Bad_Opcode },
6042     { Bad_Opcode },
6043     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6044   },
6045
6046   /* PREFIX_VEX_0F3896 */
6047   {
6048     { Bad_Opcode },
6049     { Bad_Opcode },
6050     { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 },
6051   },
6052
6053   /* PREFIX_VEX_0F3897 */
6054   {
6055     { Bad_Opcode },
6056     { Bad_Opcode },
6057     { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 },
6058   },
6059
6060   /* PREFIX_VEX_0F3898 */
6061   {
6062     { Bad_Opcode },
6063     { Bad_Opcode },
6064     { "vfmadd132p%XW", { XM, Vex, EXx }, 0 },
6065   },
6066
6067   /* PREFIX_VEX_0F3899 */
6068   {
6069     { Bad_Opcode },
6070     { Bad_Opcode },
6071     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6072   },
6073
6074   /* PREFIX_VEX_0F389A */
6075   {
6076     { Bad_Opcode },
6077     { Bad_Opcode },
6078     { "vfmsub132p%XW", { XM, Vex, EXx }, 0 },
6079   },
6080
6081   /* PREFIX_VEX_0F389B */
6082   {
6083     { Bad_Opcode },
6084     { Bad_Opcode },
6085     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6086   },
6087
6088   /* PREFIX_VEX_0F389C */
6089   {
6090     { Bad_Opcode },
6091     { Bad_Opcode },
6092     { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 },
6093   },
6094
6095   /* PREFIX_VEX_0F389D */
6096   {
6097     { Bad_Opcode },
6098     { Bad_Opcode },
6099     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6100   },
6101
6102   /* PREFIX_VEX_0F389E */
6103   {
6104     { Bad_Opcode },
6105     { Bad_Opcode },
6106     { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 },
6107   },
6108
6109   /* PREFIX_VEX_0F389F */
6110   {
6111     { Bad_Opcode },
6112     { Bad_Opcode },
6113     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6114   },
6115
6116   /* PREFIX_VEX_0F38A6 */
6117   {
6118     { Bad_Opcode },
6119     { Bad_Opcode },
6120     { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 },
6121     { Bad_Opcode },
6122   },
6123
6124   /* PREFIX_VEX_0F38A7 */
6125   {
6126     { Bad_Opcode },
6127     { Bad_Opcode },
6128     { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 },
6129   },
6130
6131   /* PREFIX_VEX_0F38A8 */
6132   {
6133     { Bad_Opcode },
6134     { Bad_Opcode },
6135     { "vfmadd213p%XW", { XM, Vex, EXx }, 0 },
6136   },
6137
6138   /* PREFIX_VEX_0F38A9 */
6139   {
6140     { Bad_Opcode },
6141     { Bad_Opcode },
6142     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6143   },
6144
6145   /* PREFIX_VEX_0F38AA */
6146   {
6147     { Bad_Opcode },
6148     { Bad_Opcode },
6149     { "vfmsub213p%XW", { XM, Vex, EXx }, 0 },
6150   },
6151
6152   /* PREFIX_VEX_0F38AB */
6153   {
6154     { Bad_Opcode },
6155     { Bad_Opcode },
6156     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6157   },
6158
6159   /* PREFIX_VEX_0F38AC */
6160   {
6161     { Bad_Opcode },
6162     { Bad_Opcode },
6163     { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 },
6164   },
6165
6166   /* PREFIX_VEX_0F38AD */
6167   {
6168     { Bad_Opcode },
6169     { Bad_Opcode },
6170     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6171   },
6172
6173   /* PREFIX_VEX_0F38AE */
6174   {
6175     { Bad_Opcode },
6176     { Bad_Opcode },
6177     { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 },
6178   },
6179
6180   /* PREFIX_VEX_0F38AF */
6181   {
6182     { Bad_Opcode },
6183     { Bad_Opcode },
6184     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6185   },
6186
6187   /* PREFIX_VEX_0F38B6 */
6188   {
6189     { Bad_Opcode },
6190     { Bad_Opcode },
6191     { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 },
6192   },
6193
6194   /* PREFIX_VEX_0F38B7 */
6195   {
6196     { Bad_Opcode },
6197     { Bad_Opcode },
6198     { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 },
6199   },
6200
6201   /* PREFIX_VEX_0F38B8 */
6202   {
6203     { Bad_Opcode },
6204     { Bad_Opcode },
6205     { "vfmadd231p%XW", { XM, Vex, EXx }, 0 },
6206   },
6207
6208   /* PREFIX_VEX_0F38B9 */
6209   {
6210     { Bad_Opcode },
6211     { Bad_Opcode },
6212     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6213   },
6214
6215   /* PREFIX_VEX_0F38BA */
6216   {
6217     { Bad_Opcode },
6218     { Bad_Opcode },
6219     { "vfmsub231p%XW", { XM, Vex, EXx }, 0 },
6220   },
6221
6222   /* PREFIX_VEX_0F38BB */
6223   {
6224     { Bad_Opcode },
6225     { Bad_Opcode },
6226     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6227   },
6228
6229   /* PREFIX_VEX_0F38BC */
6230   {
6231     { Bad_Opcode },
6232     { Bad_Opcode },
6233     { "vfnmadd231p%XW", { XM, Vex, EXx }, 0 },
6234   },
6235
6236   /* PREFIX_VEX_0F38BD */
6237   {
6238     { Bad_Opcode },
6239     { Bad_Opcode },
6240     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6241   },
6242
6243   /* PREFIX_VEX_0F38BE */
6244   {
6245     { Bad_Opcode },
6246     { Bad_Opcode },
6247     { "vfnmsub231p%XW", { XM, Vex, EXx }, 0 },
6248   },
6249
6250   /* PREFIX_VEX_0F38BF */
6251   {
6252     { Bad_Opcode },
6253     { Bad_Opcode },
6254     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6255   },
6256
6257   /* PREFIX_VEX_0F38DB */
6258   {
6259     { Bad_Opcode },
6260     { Bad_Opcode },
6261     { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6262   },
6263
6264   /* PREFIX_VEX_0F38DC */
6265   {
6266     { Bad_Opcode },
6267     { Bad_Opcode },
6268     { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2) },
6269   },
6270
6271   /* PREFIX_VEX_0F38DD */
6272   {
6273     { Bad_Opcode },
6274     { Bad_Opcode },
6275     { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2) },
6276   },
6277
6278   /* PREFIX_VEX_0F38DE */
6279   {
6280     { Bad_Opcode },
6281     { Bad_Opcode },
6282     { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2) },
6283   },
6284
6285   /* PREFIX_VEX_0F38DF */
6286   {
6287     { Bad_Opcode },
6288     { Bad_Opcode },
6289     { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2) },
6290   },
6291
6292   /* PREFIX_VEX_0F38F2 */
6293   {
6294     { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6295   },
6296
6297   /* PREFIX_VEX_0F38F3_REG_1 */
6298   {
6299     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6300   },
6301
6302   /* PREFIX_VEX_0F38F3_REG_2 */
6303   {
6304     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6305   },
6306
6307   /* PREFIX_VEX_0F38F3_REG_3 */
6308   {
6309     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6310   },
6311
6312   /* PREFIX_VEX_0F38F5 */
6313   {
6314     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6315     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6316     { Bad_Opcode },
6317     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6318   },
6319
6320   /* PREFIX_VEX_0F38F6 */
6321   {
6322     { Bad_Opcode },
6323     { Bad_Opcode },
6324     { Bad_Opcode },
6325     { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6326   },
6327
6328   /* PREFIX_VEX_0F38F7 */
6329   {
6330     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6331     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6332     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6333     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6334   },
6335
6336   /* PREFIX_VEX_0F3A00 */
6337   {
6338     { Bad_Opcode },
6339     { Bad_Opcode },
6340     { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6341   },
6342
6343   /* PREFIX_VEX_0F3A01 */
6344   {
6345     { Bad_Opcode },
6346     { Bad_Opcode },
6347     { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6348   },
6349
6350   /* PREFIX_VEX_0F3A02 */
6351   {
6352     { Bad_Opcode },
6353     { Bad_Opcode },
6354     { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6355   },
6356
6357   /* PREFIX_VEX_0F3A04 */
6358   {
6359     { Bad_Opcode },
6360     { Bad_Opcode },
6361     { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6362   },
6363
6364   /* PREFIX_VEX_0F3A05 */
6365   {
6366     { Bad_Opcode },
6367     { Bad_Opcode },
6368     { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6369   },
6370
6371   /* PREFIX_VEX_0F3A06 */
6372   {
6373     { Bad_Opcode },
6374     { Bad_Opcode },
6375     { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6376   },
6377
6378   /* PREFIX_VEX_0F3A08 */
6379   {
6380     { Bad_Opcode },
6381     { Bad_Opcode },
6382     { VEX_W_TABLE (VEX_W_0F3A08_P_2) },
6383   },
6384
6385   /* PREFIX_VEX_0F3A09 */
6386   {
6387     { Bad_Opcode },
6388     { Bad_Opcode },
6389     { VEX_W_TABLE (VEX_W_0F3A09_P_2) },
6390   },
6391
6392   /* PREFIX_VEX_0F3A0A */
6393   {
6394     { Bad_Opcode },
6395     { Bad_Opcode },
6396     { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) },
6397   },
6398
6399   /* PREFIX_VEX_0F3A0B */
6400   {
6401     { Bad_Opcode },
6402     { Bad_Opcode },
6403     { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) },
6404   },
6405
6406   /* PREFIX_VEX_0F3A0C */
6407   {
6408     { Bad_Opcode },
6409     { Bad_Opcode },
6410     { VEX_W_TABLE (VEX_W_0F3A0C_P_2) },
6411   },
6412
6413   /* PREFIX_VEX_0F3A0D */
6414   {
6415     { Bad_Opcode },
6416     { Bad_Opcode },
6417     { VEX_W_TABLE (VEX_W_0F3A0D_P_2) },
6418   },
6419
6420   /* PREFIX_VEX_0F3A0E */
6421   {
6422     { Bad_Opcode },
6423     { Bad_Opcode },
6424     { VEX_W_TABLE (VEX_W_0F3A0E_P_2) },
6425   },
6426
6427   /* PREFIX_VEX_0F3A0F */
6428   {
6429     { Bad_Opcode },
6430     { Bad_Opcode },
6431     { VEX_W_TABLE (VEX_W_0F3A0F_P_2) },
6432   },
6433
6434   /* PREFIX_VEX_0F3A14 */
6435   {
6436     { Bad_Opcode },
6437     { Bad_Opcode },
6438     { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6439   },
6440
6441   /* PREFIX_VEX_0F3A15 */
6442   {
6443     { Bad_Opcode },
6444     { Bad_Opcode },
6445     { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6446   },
6447
6448   /* PREFIX_VEX_0F3A16 */
6449   {
6450     { Bad_Opcode },
6451     { Bad_Opcode },
6452     { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6453   },
6454
6455   /* PREFIX_VEX_0F3A17 */
6456   {
6457     { Bad_Opcode },
6458     { Bad_Opcode },
6459     { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6460   },
6461
6462   /* PREFIX_VEX_0F3A18 */
6463   {
6464     { Bad_Opcode },
6465     { Bad_Opcode },
6466     { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6467   },
6468
6469   /* PREFIX_VEX_0F3A19 */
6470   {
6471     { Bad_Opcode },
6472     { Bad_Opcode },
6473     { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6474   },
6475
6476   /* PREFIX_VEX_0F3A1D */
6477   {
6478     { Bad_Opcode },
6479     { Bad_Opcode },
6480     { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 },
6481   },
6482
6483   /* PREFIX_VEX_0F3A20 */
6484   {
6485     { Bad_Opcode },
6486     { Bad_Opcode },
6487     { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6488   },
6489
6490   /* PREFIX_VEX_0F3A21 */
6491   {
6492     { Bad_Opcode },
6493     { Bad_Opcode },
6494     { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6495   },
6496
6497   /* PREFIX_VEX_0F3A22 */
6498   {
6499     { Bad_Opcode },
6500     { Bad_Opcode },
6501     { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6502   },
6503
6504   /* PREFIX_VEX_0F3A30 */
6505   {
6506     { Bad_Opcode },
6507     { Bad_Opcode },
6508     { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6509   },
6510
6511   /* PREFIX_VEX_0F3A31 */
6512   {
6513     { Bad_Opcode },
6514     { Bad_Opcode },
6515     { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6516   },
6517
6518   /* PREFIX_VEX_0F3A32 */
6519   {
6520     { Bad_Opcode },
6521     { Bad_Opcode },
6522     { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6523   },
6524
6525   /* PREFIX_VEX_0F3A33 */
6526   {
6527     { Bad_Opcode },
6528     { Bad_Opcode },
6529     { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6530   },
6531
6532   /* PREFIX_VEX_0F3A38 */
6533   {
6534     { Bad_Opcode },
6535     { Bad_Opcode },
6536     { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6537   },
6538
6539   /* PREFIX_VEX_0F3A39 */
6540   {
6541     { Bad_Opcode },
6542     { Bad_Opcode },
6543     { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6544   },
6545
6546   /* PREFIX_VEX_0F3A40 */
6547   {
6548     { Bad_Opcode },
6549     { Bad_Opcode },
6550     { VEX_W_TABLE (VEX_W_0F3A40_P_2) },
6551   },
6552
6553   /* PREFIX_VEX_0F3A41 */
6554   {
6555     { Bad_Opcode },
6556     { Bad_Opcode },
6557     { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6558   },
6559
6560   /* PREFIX_VEX_0F3A42 */
6561   {
6562     { Bad_Opcode },
6563     { Bad_Opcode },
6564     { VEX_W_TABLE (VEX_W_0F3A42_P_2) },
6565   },
6566
6567   /* PREFIX_VEX_0F3A44 */
6568   {
6569     { Bad_Opcode },
6570     { Bad_Opcode },
6571     { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2) },
6572   },
6573
6574   /* PREFIX_VEX_0F3A46 */
6575   {
6576     { Bad_Opcode },
6577     { Bad_Opcode },
6578     { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6579   },
6580
6581   /* PREFIX_VEX_0F3A48 */
6582   {
6583     { Bad_Opcode },
6584     { Bad_Opcode },
6585     { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6586   },
6587
6588   /* PREFIX_VEX_0F3A49 */
6589   {
6590     { Bad_Opcode },
6591     { Bad_Opcode },
6592     { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6593   },
6594
6595   /* PREFIX_VEX_0F3A4A */
6596   {
6597     { Bad_Opcode },
6598     { Bad_Opcode },
6599     { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6600   },
6601
6602   /* PREFIX_VEX_0F3A4B */
6603   {
6604     { Bad_Opcode },
6605     { Bad_Opcode },
6606     { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6607   },
6608
6609   /* PREFIX_VEX_0F3A4C */
6610   {
6611     { Bad_Opcode },
6612     { Bad_Opcode },
6613     { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6614   },
6615
6616   /* PREFIX_VEX_0F3A5C */
6617   {
6618     { Bad_Opcode },
6619     { Bad_Opcode },
6620     { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6621   },
6622
6623   /* PREFIX_VEX_0F3A5D */
6624   {
6625     { Bad_Opcode },
6626     { Bad_Opcode },
6627     { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6628   },
6629
6630   /* PREFIX_VEX_0F3A5E */
6631   {
6632     { Bad_Opcode },
6633     { Bad_Opcode },
6634     { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6635   },
6636
6637   /* PREFIX_VEX_0F3A5F */
6638   {
6639     { Bad_Opcode },
6640     { Bad_Opcode },
6641     { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6642   },
6643
6644   /* PREFIX_VEX_0F3A60 */
6645   {
6646     { Bad_Opcode },
6647     { Bad_Opcode },
6648     { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6649     { Bad_Opcode },
6650   },
6651
6652   /* PREFIX_VEX_0F3A61 */
6653   {
6654     { Bad_Opcode },
6655     { Bad_Opcode },
6656     { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6657   },
6658
6659   /* PREFIX_VEX_0F3A62 */
6660   {
6661     { Bad_Opcode },
6662     { Bad_Opcode },
6663     { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6664   },
6665
6666   /* PREFIX_VEX_0F3A63 */
6667   {
6668     { Bad_Opcode },
6669     { Bad_Opcode },
6670     { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6671   },
6672
6673   /* PREFIX_VEX_0F3A68 */
6674   {
6675     { Bad_Opcode },
6676     { Bad_Opcode },
6677     { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6678   },
6679
6680   /* PREFIX_VEX_0F3A69 */
6681   {
6682     { Bad_Opcode },
6683     { Bad_Opcode },
6684     { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6685   },
6686
6687   /* PREFIX_VEX_0F3A6A */
6688   {
6689     { Bad_Opcode },
6690     { Bad_Opcode },
6691     { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6692   },
6693
6694   /* PREFIX_VEX_0F3A6B */
6695   {
6696     { Bad_Opcode },
6697     { Bad_Opcode },
6698     { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6699   },
6700
6701   /* PREFIX_VEX_0F3A6C */
6702   {
6703     { Bad_Opcode },
6704     { Bad_Opcode },
6705     { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6706   },
6707
6708   /* PREFIX_VEX_0F3A6D */
6709   {
6710     { Bad_Opcode },
6711     { Bad_Opcode },
6712     { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6713   },
6714
6715   /* PREFIX_VEX_0F3A6E */
6716   {
6717     { Bad_Opcode },
6718     { Bad_Opcode },
6719     { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6720   },
6721
6722   /* PREFIX_VEX_0F3A6F */
6723   {
6724     { Bad_Opcode },
6725     { Bad_Opcode },
6726     { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6727   },
6728
6729   /* PREFIX_VEX_0F3A78 */
6730   {
6731     { Bad_Opcode },
6732     { Bad_Opcode },
6733     { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6734   },
6735
6736   /* PREFIX_VEX_0F3A79 */
6737   {
6738     { Bad_Opcode },
6739     { Bad_Opcode },
6740     { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6741   },
6742
6743   /* PREFIX_VEX_0F3A7A */
6744   {
6745     { Bad_Opcode },
6746     { Bad_Opcode },
6747     { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6748   },
6749
6750   /* PREFIX_VEX_0F3A7B */
6751   {
6752     { Bad_Opcode },
6753     { Bad_Opcode },
6754     { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6755   },
6756
6757   /* PREFIX_VEX_0F3A7C */
6758   {
6759     { Bad_Opcode },
6760     { Bad_Opcode },
6761     { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6762     { Bad_Opcode },
6763   },
6764
6765   /* PREFIX_VEX_0F3A7D */
6766   {
6767     { Bad_Opcode },
6768     { Bad_Opcode },
6769     { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6770   },
6771
6772   /* PREFIX_VEX_0F3A7E */
6773   {
6774     { Bad_Opcode },
6775     { Bad_Opcode },
6776     { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6777   },
6778
6779   /* PREFIX_VEX_0F3A7F */
6780   {
6781     { Bad_Opcode },
6782     { Bad_Opcode },
6783     { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6784   },
6785
6786   /* PREFIX_VEX_0F3ADF */
6787   {
6788     { Bad_Opcode },
6789     { Bad_Opcode },
6790     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6791   },
6792
6793   /* PREFIX_VEX_0F3AF0 */
6794   {
6795     { Bad_Opcode },
6796     { Bad_Opcode },
6797     { Bad_Opcode },
6798     { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6799   },
6800
6801 #define NEED_PREFIX_TABLE
6802 #include "i386-dis-evex.h"
6803 #undef NEED_PREFIX_TABLE
6804 };
6805
6806 static const struct dis386 x86_64_table[][2] = {
6807   /* X86_64_06 */
6808   {
6809     { "pushP", { es }, 0 },
6810   },
6811
6812   /* X86_64_07 */
6813   {
6814     { "popP", { es }, 0 },
6815   },
6816
6817   /* X86_64_0D */
6818   {
6819     { "pushP", { cs }, 0 },
6820   },
6821
6822   /* X86_64_16 */
6823   {
6824     { "pushP", { ss }, 0 },
6825   },
6826
6827   /* X86_64_17 */
6828   {
6829     { "popP", { ss }, 0 },
6830   },
6831
6832   /* X86_64_1E */
6833   {
6834     { "pushP", { ds }, 0 },
6835   },
6836
6837   /* X86_64_1F */
6838   {
6839     { "popP", { ds }, 0 },
6840   },
6841
6842   /* X86_64_27 */
6843   {
6844     { "daa", { XX }, 0 },
6845   },
6846
6847   /* X86_64_2F */
6848   {
6849     { "das", { XX }, 0 },
6850   },
6851
6852   /* X86_64_37 */
6853   {
6854     { "aaa", { XX }, 0 },
6855   },
6856
6857   /* X86_64_3F */
6858   {
6859     { "aas", { XX }, 0 },
6860   },
6861
6862   /* X86_64_60 */
6863   {
6864     { "pushaP", { XX }, 0 },
6865   },
6866
6867   /* X86_64_61 */
6868   {
6869     { "popaP", { XX }, 0 },
6870   },
6871
6872   /* X86_64_62 */
6873   {
6874     { MOD_TABLE (MOD_62_32BIT) },
6875     { EVEX_TABLE (EVEX_0F) },
6876   },
6877
6878   /* X86_64_63 */
6879   {
6880     { "arpl", { Ew, Gw }, 0 },
6881     { "movs{lq|xd}", { Gv, Ed }, 0 },
6882   },
6883
6884   /* X86_64_6D */
6885   {
6886     { "ins{R|}", { Yzr, indirDX }, 0 },
6887     { "ins{G|}", { Yzr, indirDX }, 0 },
6888   },
6889
6890   /* X86_64_6F */
6891   {
6892     { "outs{R|}", { indirDXr, Xz }, 0 },
6893     { "outs{G|}", { indirDXr, Xz }, 0 },
6894   },
6895
6896   /* X86_64_9A */
6897   {
6898     { "Jcall{T|}", { Ap }, 0 },
6899   },
6900
6901   /* X86_64_C4 */
6902   {
6903     { MOD_TABLE (MOD_C4_32BIT) },
6904     { VEX_C4_TABLE (VEX_0F) },
6905   },
6906
6907   /* X86_64_C5 */
6908   {
6909     { MOD_TABLE (MOD_C5_32BIT) },
6910     { VEX_C5_TABLE (VEX_0F) },
6911   },
6912
6913   /* X86_64_CE */
6914   {
6915     { "into", { XX }, 0 },
6916   },
6917
6918   /* X86_64_D4 */
6919   {
6920     { "aam", { Ib }, 0 },
6921   },
6922
6923   /* X86_64_D5 */
6924   {
6925     { "aad", { Ib }, 0 },
6926   },
6927
6928   /* X86_64_E8 */
6929   {
6930     { "callP",          { Jv, BND }, 0 },
6931     { "call@",          { Jv, BND }, 0 }
6932   },
6933
6934   /* X86_64_E9 */
6935   {
6936     { "jmpP",           { Jv, BND }, 0 },
6937     { "jmp@",           { Jv, BND }, 0 }
6938   },
6939
6940   /* X86_64_EA */
6941   {
6942     { "Jjmp{T|}", { Ap }, 0 },
6943   },
6944
6945   /* X86_64_0F01_REG_0 */
6946   {
6947     { "sgdt{Q|IQ}", { M }, 0 },
6948     { "sgdt", { M }, 0 },
6949   },
6950
6951   /* X86_64_0F01_REG_1 */
6952   {
6953     { "sidt{Q|IQ}", { M }, 0 },
6954     { "sidt", { M }, 0 },
6955   },
6956
6957   /* X86_64_0F01_REG_2 */
6958   {
6959     { "lgdt{Q|Q}", { M }, 0 },
6960     { "lgdt", { M }, 0 },
6961   },
6962
6963   /* X86_64_0F01_REG_3 */
6964   {
6965     { "lidt{Q|Q}", { M }, 0 },
6966     { "lidt", { M }, 0 },
6967   },
6968 };
6969
6970 static const struct dis386 three_byte_table[][256] = {
6971
6972   /* THREE_BYTE_0F38 */
6973   {
6974     /* 00 */
6975     { "pshufb",         { MX, EM }, PREFIX_OPCODE },
6976     { "phaddw",         { MX, EM }, PREFIX_OPCODE },
6977     { "phaddd",         { MX, EM }, PREFIX_OPCODE },
6978     { "phaddsw",        { MX, EM }, PREFIX_OPCODE },
6979     { "pmaddubsw",      { MX, EM }, PREFIX_OPCODE },
6980     { "phsubw",         { MX, EM }, PREFIX_OPCODE },
6981     { "phsubd",         { MX, EM }, PREFIX_OPCODE },
6982     { "phsubsw",        { MX, EM }, PREFIX_OPCODE },
6983     /* 08 */
6984     { "psignb",         { MX, EM }, PREFIX_OPCODE },
6985     { "psignw",         { MX, EM }, PREFIX_OPCODE },
6986     { "psignd",         { MX, EM }, PREFIX_OPCODE },
6987     { "pmulhrsw",       { MX, EM }, PREFIX_OPCODE },
6988     { Bad_Opcode },
6989     { Bad_Opcode },
6990     { Bad_Opcode },
6991     { Bad_Opcode },
6992     /* 10 */
6993     { PREFIX_TABLE (PREFIX_0F3810) },
6994     { Bad_Opcode },
6995     { Bad_Opcode },
6996     { Bad_Opcode },
6997     { PREFIX_TABLE (PREFIX_0F3814) },
6998     { PREFIX_TABLE (PREFIX_0F3815) },
6999     { Bad_Opcode },
7000     { PREFIX_TABLE (PREFIX_0F3817) },
7001     /* 18 */
7002     { Bad_Opcode },
7003     { Bad_Opcode },
7004     { Bad_Opcode },
7005     { Bad_Opcode },
7006     { "pabsb",          { MX, EM }, PREFIX_OPCODE },
7007     { "pabsw",          { MX, EM }, PREFIX_OPCODE },
7008     { "pabsd",          { MX, EM }, PREFIX_OPCODE },
7009     { Bad_Opcode },
7010     /* 20 */
7011     { PREFIX_TABLE (PREFIX_0F3820) },
7012     { PREFIX_TABLE (PREFIX_0F3821) },
7013     { PREFIX_TABLE (PREFIX_0F3822) },
7014     { PREFIX_TABLE (PREFIX_0F3823) },
7015     { PREFIX_TABLE (PREFIX_0F3824) },
7016     { PREFIX_TABLE (PREFIX_0F3825) },
7017     { Bad_Opcode },
7018     { Bad_Opcode },
7019     /* 28 */
7020     { PREFIX_TABLE (PREFIX_0F3828) },
7021     { PREFIX_TABLE (PREFIX_0F3829) },
7022     { PREFIX_TABLE (PREFIX_0F382A) },
7023     { PREFIX_TABLE (PREFIX_0F382B) },
7024     { Bad_Opcode },
7025     { Bad_Opcode },
7026     { Bad_Opcode },
7027     { Bad_Opcode },
7028     /* 30 */
7029     { PREFIX_TABLE (PREFIX_0F3830) },
7030     { PREFIX_TABLE (PREFIX_0F3831) },
7031     { PREFIX_TABLE (PREFIX_0F3832) },
7032     { PREFIX_TABLE (PREFIX_0F3833) },
7033     { PREFIX_TABLE (PREFIX_0F3834) },
7034     { PREFIX_TABLE (PREFIX_0F3835) },
7035     { Bad_Opcode },
7036     { PREFIX_TABLE (PREFIX_0F3837) },
7037     /* 38 */
7038     { PREFIX_TABLE (PREFIX_0F3838) },
7039     { PREFIX_TABLE (PREFIX_0F3839) },
7040     { PREFIX_TABLE (PREFIX_0F383A) },
7041     { PREFIX_TABLE (PREFIX_0F383B) },
7042     { PREFIX_TABLE (PREFIX_0F383C) },
7043     { PREFIX_TABLE (PREFIX_0F383D) },
7044     { PREFIX_TABLE (PREFIX_0F383E) },
7045     { PREFIX_TABLE (PREFIX_0F383F) },
7046     /* 40 */
7047     { PREFIX_TABLE (PREFIX_0F3840) },
7048     { PREFIX_TABLE (PREFIX_0F3841) },
7049     { Bad_Opcode },
7050     { Bad_Opcode },
7051     { Bad_Opcode },
7052     { Bad_Opcode },
7053     { Bad_Opcode },
7054     { Bad_Opcode },
7055     /* 48 */
7056     { Bad_Opcode },
7057     { Bad_Opcode },
7058     { Bad_Opcode },
7059     { Bad_Opcode },
7060     { Bad_Opcode },
7061     { Bad_Opcode },
7062     { Bad_Opcode },
7063     { Bad_Opcode },
7064     /* 50 */
7065     { Bad_Opcode },
7066     { Bad_Opcode },
7067     { Bad_Opcode },
7068     { Bad_Opcode },
7069     { Bad_Opcode },
7070     { Bad_Opcode },
7071     { Bad_Opcode },
7072     { Bad_Opcode },
7073     /* 58 */
7074     { Bad_Opcode },
7075     { Bad_Opcode },
7076     { Bad_Opcode },
7077     { Bad_Opcode },
7078     { Bad_Opcode },
7079     { Bad_Opcode },
7080     { Bad_Opcode },
7081     { Bad_Opcode },
7082     /* 60 */
7083     { Bad_Opcode },
7084     { Bad_Opcode },
7085     { Bad_Opcode },
7086     { Bad_Opcode },
7087     { Bad_Opcode },
7088     { Bad_Opcode },
7089     { Bad_Opcode },
7090     { Bad_Opcode },
7091     /* 68 */
7092     { Bad_Opcode },
7093     { Bad_Opcode },
7094     { Bad_Opcode },
7095     { Bad_Opcode },
7096     { Bad_Opcode },
7097     { Bad_Opcode },
7098     { Bad_Opcode },
7099     { Bad_Opcode },
7100     /* 70 */
7101     { Bad_Opcode },
7102     { Bad_Opcode },
7103     { Bad_Opcode },
7104     { Bad_Opcode },
7105     { Bad_Opcode },
7106     { Bad_Opcode },
7107     { Bad_Opcode },
7108     { Bad_Opcode },
7109     /* 78 */
7110     { Bad_Opcode },
7111     { Bad_Opcode },
7112     { Bad_Opcode },
7113     { Bad_Opcode },
7114     { Bad_Opcode },
7115     { Bad_Opcode },
7116     { Bad_Opcode },
7117     { Bad_Opcode },
7118     /* 80 */
7119     { PREFIX_TABLE (PREFIX_0F3880) },
7120     { PREFIX_TABLE (PREFIX_0F3881) },
7121     { PREFIX_TABLE (PREFIX_0F3882) },
7122     { Bad_Opcode },
7123     { Bad_Opcode },
7124     { Bad_Opcode },
7125     { Bad_Opcode },
7126     { Bad_Opcode },
7127     /* 88 */
7128     { Bad_Opcode },
7129     { Bad_Opcode },
7130     { Bad_Opcode },
7131     { Bad_Opcode },
7132     { Bad_Opcode },
7133     { Bad_Opcode },
7134     { Bad_Opcode },
7135     { Bad_Opcode },
7136     /* 90 */
7137     { Bad_Opcode },
7138     { Bad_Opcode },
7139     { Bad_Opcode },
7140     { Bad_Opcode },
7141     { Bad_Opcode },
7142     { Bad_Opcode },
7143     { Bad_Opcode },
7144     { Bad_Opcode },
7145     /* 98 */
7146     { Bad_Opcode },
7147     { Bad_Opcode },
7148     { Bad_Opcode },
7149     { Bad_Opcode },
7150     { Bad_Opcode },
7151     { Bad_Opcode },
7152     { Bad_Opcode },
7153     { Bad_Opcode },
7154     /* a0 */
7155     { Bad_Opcode },
7156     { Bad_Opcode },
7157     { Bad_Opcode },
7158     { Bad_Opcode },
7159     { Bad_Opcode },
7160     { Bad_Opcode },
7161     { Bad_Opcode },
7162     { Bad_Opcode },
7163     /* a8 */
7164     { Bad_Opcode },
7165     { Bad_Opcode },
7166     { Bad_Opcode },
7167     { Bad_Opcode },
7168     { Bad_Opcode },
7169     { Bad_Opcode },
7170     { Bad_Opcode },
7171     { Bad_Opcode },
7172     /* b0 */
7173     { Bad_Opcode },
7174     { Bad_Opcode },
7175     { Bad_Opcode },
7176     { Bad_Opcode },
7177     { Bad_Opcode },
7178     { Bad_Opcode },
7179     { Bad_Opcode },
7180     { Bad_Opcode },
7181     /* b8 */
7182     { Bad_Opcode },
7183     { Bad_Opcode },
7184     { Bad_Opcode },
7185     { Bad_Opcode },
7186     { Bad_Opcode },
7187     { Bad_Opcode },
7188     { Bad_Opcode },
7189     { Bad_Opcode },
7190     /* c0 */
7191     { Bad_Opcode },
7192     { Bad_Opcode },
7193     { Bad_Opcode },
7194     { Bad_Opcode },
7195     { Bad_Opcode },
7196     { Bad_Opcode },
7197     { Bad_Opcode },
7198     { Bad_Opcode },
7199     /* c8 */
7200     { PREFIX_TABLE (PREFIX_0F38C8) },
7201     { PREFIX_TABLE (PREFIX_0F38C9) },
7202     { PREFIX_TABLE (PREFIX_0F38CA) },
7203     { PREFIX_TABLE (PREFIX_0F38CB) },
7204     { PREFIX_TABLE (PREFIX_0F38CC) },
7205     { PREFIX_TABLE (PREFIX_0F38CD) },
7206     { Bad_Opcode },
7207     { Bad_Opcode },
7208     /* d0 */
7209     { Bad_Opcode },
7210     { Bad_Opcode },
7211     { Bad_Opcode },
7212     { Bad_Opcode },
7213     { Bad_Opcode },
7214     { Bad_Opcode },
7215     { Bad_Opcode },
7216     { Bad_Opcode },
7217     /* d8 */
7218     { Bad_Opcode },
7219     { Bad_Opcode },
7220     { Bad_Opcode },
7221     { PREFIX_TABLE (PREFIX_0F38DB) },
7222     { PREFIX_TABLE (PREFIX_0F38DC) },
7223     { PREFIX_TABLE (PREFIX_0F38DD) },
7224     { PREFIX_TABLE (PREFIX_0F38DE) },
7225     { PREFIX_TABLE (PREFIX_0F38DF) },
7226     /* e0 */
7227     { Bad_Opcode },
7228     { Bad_Opcode },
7229     { Bad_Opcode },
7230     { Bad_Opcode },
7231     { Bad_Opcode },
7232     { Bad_Opcode },
7233     { Bad_Opcode },
7234     { Bad_Opcode },
7235     /* e8 */
7236     { Bad_Opcode },
7237     { Bad_Opcode },
7238     { Bad_Opcode },
7239     { Bad_Opcode },
7240     { Bad_Opcode },
7241     { Bad_Opcode },
7242     { Bad_Opcode },
7243     { Bad_Opcode },
7244     /* f0 */
7245     { PREFIX_TABLE (PREFIX_0F38F0) },
7246     { PREFIX_TABLE (PREFIX_0F38F1) },
7247     { Bad_Opcode },
7248     { Bad_Opcode },
7249     { Bad_Opcode },
7250     { Bad_Opcode },
7251     { PREFIX_TABLE (PREFIX_0F38F6) },
7252     { Bad_Opcode },
7253     /* f8 */
7254     { Bad_Opcode },
7255     { Bad_Opcode },
7256     { Bad_Opcode },
7257     { Bad_Opcode },
7258     { Bad_Opcode },
7259     { Bad_Opcode },
7260     { Bad_Opcode },
7261     { Bad_Opcode },
7262   },
7263   /* THREE_BYTE_0F3A */
7264   {
7265     /* 00 */
7266     { Bad_Opcode },
7267     { Bad_Opcode },
7268     { Bad_Opcode },
7269     { Bad_Opcode },
7270     { Bad_Opcode },
7271     { Bad_Opcode },
7272     { Bad_Opcode },
7273     { Bad_Opcode },
7274     /* 08 */
7275     { PREFIX_TABLE (PREFIX_0F3A08) },
7276     { PREFIX_TABLE (PREFIX_0F3A09) },
7277     { PREFIX_TABLE (PREFIX_0F3A0A) },
7278     { PREFIX_TABLE (PREFIX_0F3A0B) },
7279     { PREFIX_TABLE (PREFIX_0F3A0C) },
7280     { PREFIX_TABLE (PREFIX_0F3A0D) },
7281     { PREFIX_TABLE (PREFIX_0F3A0E) },
7282     { "palignr",        { MX, EM, Ib }, PREFIX_OPCODE },
7283     /* 10 */
7284     { Bad_Opcode },
7285     { Bad_Opcode },
7286     { Bad_Opcode },
7287     { Bad_Opcode },
7288     { PREFIX_TABLE (PREFIX_0F3A14) },
7289     { PREFIX_TABLE (PREFIX_0F3A15) },
7290     { PREFIX_TABLE (PREFIX_0F3A16) },
7291     { PREFIX_TABLE (PREFIX_0F3A17) },
7292     /* 18 */
7293     { Bad_Opcode },
7294     { Bad_Opcode },
7295     { Bad_Opcode },
7296     { Bad_Opcode },
7297     { Bad_Opcode },
7298     { Bad_Opcode },
7299     { Bad_Opcode },
7300     { Bad_Opcode },
7301     /* 20 */
7302     { PREFIX_TABLE (PREFIX_0F3A20) },
7303     { PREFIX_TABLE (PREFIX_0F3A21) },
7304     { PREFIX_TABLE (PREFIX_0F3A22) },
7305     { Bad_Opcode },
7306     { Bad_Opcode },
7307     { Bad_Opcode },
7308     { Bad_Opcode },
7309     { Bad_Opcode },
7310     /* 28 */
7311     { Bad_Opcode },
7312     { Bad_Opcode },
7313     { Bad_Opcode },
7314     { Bad_Opcode },
7315     { Bad_Opcode },
7316     { Bad_Opcode },
7317     { Bad_Opcode },
7318     { Bad_Opcode },
7319     /* 30 */
7320     { Bad_Opcode },
7321     { Bad_Opcode },
7322     { Bad_Opcode },
7323     { Bad_Opcode },
7324     { Bad_Opcode },
7325     { Bad_Opcode },
7326     { Bad_Opcode },
7327     { Bad_Opcode },
7328     /* 38 */
7329     { Bad_Opcode },
7330     { Bad_Opcode },
7331     { Bad_Opcode },
7332     { Bad_Opcode },
7333     { Bad_Opcode },
7334     { Bad_Opcode },
7335     { Bad_Opcode },
7336     { Bad_Opcode },
7337     /* 40 */
7338     { PREFIX_TABLE (PREFIX_0F3A40) },
7339     { PREFIX_TABLE (PREFIX_0F3A41) },
7340     { PREFIX_TABLE (PREFIX_0F3A42) },
7341     { Bad_Opcode },
7342     { PREFIX_TABLE (PREFIX_0F3A44) },
7343     { Bad_Opcode },
7344     { Bad_Opcode },
7345     { Bad_Opcode },
7346     /* 48 */
7347     { Bad_Opcode },
7348     { Bad_Opcode },
7349     { Bad_Opcode },
7350     { Bad_Opcode },
7351     { Bad_Opcode },
7352     { Bad_Opcode },
7353     { Bad_Opcode },
7354     { Bad_Opcode },
7355     /* 50 */
7356     { Bad_Opcode },
7357     { Bad_Opcode },
7358     { Bad_Opcode },
7359     { Bad_Opcode },
7360     { Bad_Opcode },
7361     { Bad_Opcode },
7362     { Bad_Opcode },
7363     { Bad_Opcode },
7364     /* 58 */
7365     { Bad_Opcode },
7366     { Bad_Opcode },
7367     { Bad_Opcode },
7368     { Bad_Opcode },
7369     { Bad_Opcode },
7370     { Bad_Opcode },
7371     { Bad_Opcode },
7372     { Bad_Opcode },
7373     /* 60 */
7374     { PREFIX_TABLE (PREFIX_0F3A60) },
7375     { PREFIX_TABLE (PREFIX_0F3A61) },
7376     { PREFIX_TABLE (PREFIX_0F3A62) },
7377     { PREFIX_TABLE (PREFIX_0F3A63) },
7378     { Bad_Opcode },
7379     { Bad_Opcode },
7380     { Bad_Opcode },
7381     { Bad_Opcode },
7382     /* 68 */
7383     { Bad_Opcode },
7384     { Bad_Opcode },
7385     { Bad_Opcode },
7386     { Bad_Opcode },
7387     { Bad_Opcode },
7388     { Bad_Opcode },
7389     { Bad_Opcode },
7390     { Bad_Opcode },
7391     /* 70 */
7392     { Bad_Opcode },
7393     { Bad_Opcode },
7394     { Bad_Opcode },
7395     { Bad_Opcode },
7396     { Bad_Opcode },
7397     { Bad_Opcode },
7398     { Bad_Opcode },
7399     { Bad_Opcode },
7400     /* 78 */
7401     { Bad_Opcode },
7402     { Bad_Opcode },
7403     { Bad_Opcode },
7404     { Bad_Opcode },
7405     { Bad_Opcode },
7406     { Bad_Opcode },
7407     { Bad_Opcode },
7408     { Bad_Opcode },
7409     /* 80 */
7410     { Bad_Opcode },
7411     { Bad_Opcode },
7412     { Bad_Opcode },
7413     { Bad_Opcode },
7414     { Bad_Opcode },
7415     { Bad_Opcode },
7416     { Bad_Opcode },
7417     { Bad_Opcode },
7418     /* 88 */
7419     { Bad_Opcode },
7420     { Bad_Opcode },
7421     { Bad_Opcode },
7422     { Bad_Opcode },
7423     { Bad_Opcode },
7424     { Bad_Opcode },
7425     { Bad_Opcode },
7426     { Bad_Opcode },
7427     /* 90 */
7428     { Bad_Opcode },
7429     { Bad_Opcode },
7430     { Bad_Opcode },
7431     { Bad_Opcode },
7432     { Bad_Opcode },
7433     { Bad_Opcode },
7434     { Bad_Opcode },
7435     { Bad_Opcode },
7436     /* 98 */
7437     { Bad_Opcode },
7438     { Bad_Opcode },
7439     { Bad_Opcode },
7440     { Bad_Opcode },
7441     { Bad_Opcode },
7442     { Bad_Opcode },
7443     { Bad_Opcode },
7444     { Bad_Opcode },
7445     /* a0 */
7446     { Bad_Opcode },
7447     { Bad_Opcode },
7448     { Bad_Opcode },
7449     { Bad_Opcode },
7450     { Bad_Opcode },
7451     { Bad_Opcode },
7452     { Bad_Opcode },
7453     { Bad_Opcode },
7454     /* a8 */
7455     { Bad_Opcode },
7456     { Bad_Opcode },
7457     { Bad_Opcode },
7458     { Bad_Opcode },
7459     { Bad_Opcode },
7460     { Bad_Opcode },
7461     { Bad_Opcode },
7462     { Bad_Opcode },
7463     /* b0 */
7464     { Bad_Opcode },
7465     { Bad_Opcode },
7466     { Bad_Opcode },
7467     { Bad_Opcode },
7468     { Bad_Opcode },
7469     { Bad_Opcode },
7470     { Bad_Opcode },
7471     { Bad_Opcode },
7472     /* b8 */
7473     { Bad_Opcode },
7474     { Bad_Opcode },
7475     { Bad_Opcode },
7476     { Bad_Opcode },
7477     { Bad_Opcode },
7478     { Bad_Opcode },
7479     { Bad_Opcode },
7480     { Bad_Opcode },
7481     /* c0 */
7482     { Bad_Opcode },
7483     { Bad_Opcode },
7484     { Bad_Opcode },
7485     { Bad_Opcode },
7486     { Bad_Opcode },
7487     { Bad_Opcode },
7488     { Bad_Opcode },
7489     { Bad_Opcode },
7490     /* c8 */
7491     { Bad_Opcode },
7492     { Bad_Opcode },
7493     { Bad_Opcode },
7494     { Bad_Opcode },
7495     { PREFIX_TABLE (PREFIX_0F3ACC) },
7496     { Bad_Opcode },
7497     { Bad_Opcode },
7498     { Bad_Opcode },
7499     /* d0 */
7500     { Bad_Opcode },
7501     { Bad_Opcode },
7502     { Bad_Opcode },
7503     { Bad_Opcode },
7504     { Bad_Opcode },
7505     { Bad_Opcode },
7506     { Bad_Opcode },
7507     { Bad_Opcode },
7508     /* d8 */
7509     { Bad_Opcode },
7510     { Bad_Opcode },
7511     { Bad_Opcode },
7512     { Bad_Opcode },
7513     { Bad_Opcode },
7514     { Bad_Opcode },
7515     { Bad_Opcode },
7516     { PREFIX_TABLE (PREFIX_0F3ADF) },
7517     /* e0 */
7518     { Bad_Opcode },
7519     { Bad_Opcode },
7520     { Bad_Opcode },
7521     { Bad_Opcode },
7522     { Bad_Opcode },
7523     { Bad_Opcode },
7524     { Bad_Opcode },
7525     { Bad_Opcode },
7526     /* e8 */
7527     { Bad_Opcode },
7528     { Bad_Opcode },
7529     { Bad_Opcode },
7530     { Bad_Opcode },
7531     { Bad_Opcode },
7532     { Bad_Opcode },
7533     { Bad_Opcode },
7534     { Bad_Opcode },
7535     /* f0 */
7536     { Bad_Opcode },
7537     { Bad_Opcode },
7538     { Bad_Opcode },
7539     { Bad_Opcode },
7540     { Bad_Opcode },
7541     { Bad_Opcode },
7542     { Bad_Opcode },
7543     { Bad_Opcode },
7544     /* f8 */
7545     { Bad_Opcode },
7546     { Bad_Opcode },
7547     { Bad_Opcode },
7548     { Bad_Opcode },
7549     { Bad_Opcode },
7550     { Bad_Opcode },
7551     { Bad_Opcode },
7552     { Bad_Opcode },
7553   },
7554
7555   /* THREE_BYTE_0F7A */
7556   {
7557     /* 00 */
7558     { Bad_Opcode },
7559     { Bad_Opcode },
7560     { Bad_Opcode },
7561     { Bad_Opcode },
7562     { Bad_Opcode },
7563     { Bad_Opcode },
7564     { Bad_Opcode },
7565     { Bad_Opcode },
7566     /* 08 */
7567     { Bad_Opcode },
7568     { Bad_Opcode },
7569     { Bad_Opcode },
7570     { Bad_Opcode },
7571     { Bad_Opcode },
7572     { Bad_Opcode },
7573     { Bad_Opcode },
7574     { Bad_Opcode },
7575     /* 10 */
7576     { Bad_Opcode },
7577     { Bad_Opcode },
7578     { Bad_Opcode },
7579     { Bad_Opcode },
7580     { Bad_Opcode },
7581     { Bad_Opcode },
7582     { Bad_Opcode },
7583     { Bad_Opcode },
7584     /* 18 */
7585     { Bad_Opcode },
7586     { Bad_Opcode },
7587     { Bad_Opcode },
7588     { Bad_Opcode },
7589     { Bad_Opcode },
7590     { Bad_Opcode },
7591     { Bad_Opcode },
7592     { Bad_Opcode },
7593     /* 20 */
7594     { Bad_Opcode },
7595     { Bad_Opcode },
7596     { Bad_Opcode },
7597     { Bad_Opcode },
7598     { Bad_Opcode },
7599     { Bad_Opcode },
7600     { Bad_Opcode },
7601     { Bad_Opcode },
7602     /* 28 */
7603     { Bad_Opcode },
7604     { Bad_Opcode },
7605     { Bad_Opcode },
7606     { Bad_Opcode },
7607     { Bad_Opcode },
7608     { Bad_Opcode },
7609     { Bad_Opcode },
7610     { Bad_Opcode },
7611     /* 30 */
7612     { Bad_Opcode },
7613     { Bad_Opcode },
7614     { Bad_Opcode },
7615     { Bad_Opcode },
7616     { Bad_Opcode },
7617     { Bad_Opcode },
7618     { Bad_Opcode },
7619     { Bad_Opcode },
7620     /* 38 */
7621     { Bad_Opcode },
7622     { Bad_Opcode },
7623     { Bad_Opcode },
7624     { Bad_Opcode },
7625     { Bad_Opcode },
7626     { Bad_Opcode },
7627     { Bad_Opcode },
7628     { Bad_Opcode },
7629     /* 40 */
7630     { Bad_Opcode },
7631     { "phaddbw",        { XM, EXq }, PREFIX_OPCODE },
7632     { "phaddbd",        { XM, EXq }, PREFIX_OPCODE },
7633     { "phaddbq",        { XM, EXq }, PREFIX_OPCODE },
7634     { Bad_Opcode },
7635     { Bad_Opcode },
7636     { "phaddwd",        { XM, EXq }, PREFIX_OPCODE },
7637     { "phaddwq",        { XM, EXq }, PREFIX_OPCODE },
7638     /* 48 */
7639     { Bad_Opcode },
7640     { Bad_Opcode },
7641     { Bad_Opcode },
7642     { "phadddq",        { XM, EXq }, PREFIX_OPCODE },
7643     { Bad_Opcode },
7644     { Bad_Opcode },
7645     { Bad_Opcode },
7646     { Bad_Opcode },
7647     /* 50 */
7648     { Bad_Opcode },
7649     { "phaddubw",       { XM, EXq }, PREFIX_OPCODE },
7650     { "phaddubd",       { XM, EXq }, PREFIX_OPCODE },
7651     { "phaddubq",       { XM, EXq }, PREFIX_OPCODE },
7652     { Bad_Opcode },
7653     { Bad_Opcode },
7654     { "phadduwd",       { XM, EXq }, PREFIX_OPCODE },
7655     { "phadduwq",       { XM, EXq }, PREFIX_OPCODE },
7656     /* 58 */
7657     { Bad_Opcode },
7658     { Bad_Opcode },
7659     { Bad_Opcode },
7660     { "phaddudq",       { XM, EXq }, PREFIX_OPCODE },
7661     { Bad_Opcode },
7662     { Bad_Opcode },
7663     { Bad_Opcode },
7664     { Bad_Opcode },
7665     /* 60 */
7666     { Bad_Opcode },
7667     { "phsubbw",        { XM, EXq }, PREFIX_OPCODE },
7668     { "phsubbd",        { XM, EXq }, PREFIX_OPCODE },
7669     { "phsubbq",        { XM, EXq }, PREFIX_OPCODE },
7670     { Bad_Opcode },
7671     { Bad_Opcode },
7672     { Bad_Opcode },
7673     { Bad_Opcode },
7674     /* 68 */
7675     { Bad_Opcode },
7676     { Bad_Opcode },
7677     { Bad_Opcode },
7678     { Bad_Opcode },
7679     { Bad_Opcode },
7680     { Bad_Opcode },
7681     { Bad_Opcode },
7682     { Bad_Opcode },
7683     /* 70 */
7684     { Bad_Opcode },
7685     { Bad_Opcode },
7686     { Bad_Opcode },
7687     { Bad_Opcode },
7688     { Bad_Opcode },
7689     { Bad_Opcode },
7690     { Bad_Opcode },
7691     { Bad_Opcode },
7692     /* 78 */
7693     { Bad_Opcode },
7694     { Bad_Opcode },
7695     { Bad_Opcode },
7696     { Bad_Opcode },
7697     { Bad_Opcode },
7698     { Bad_Opcode },
7699     { Bad_Opcode },
7700     { Bad_Opcode },
7701     /* 80 */
7702     { Bad_Opcode },
7703     { Bad_Opcode },
7704     { Bad_Opcode },
7705     { Bad_Opcode },
7706     { Bad_Opcode },
7707     { Bad_Opcode },
7708     { Bad_Opcode },
7709     { Bad_Opcode },
7710     /* 88 */
7711     { Bad_Opcode },
7712     { Bad_Opcode },
7713     { Bad_Opcode },
7714     { Bad_Opcode },
7715     { Bad_Opcode },
7716     { Bad_Opcode },
7717     { Bad_Opcode },
7718     { Bad_Opcode },
7719     /* 90 */
7720     { Bad_Opcode },
7721     { Bad_Opcode },
7722     { Bad_Opcode },
7723     { Bad_Opcode },
7724     { Bad_Opcode },
7725     { Bad_Opcode },
7726     { Bad_Opcode },
7727     { Bad_Opcode },
7728     /* 98 */
7729     { Bad_Opcode },
7730     { Bad_Opcode },
7731     { Bad_Opcode },
7732     { Bad_Opcode },
7733     { Bad_Opcode },
7734     { Bad_Opcode },
7735     { Bad_Opcode },
7736     { Bad_Opcode },
7737     /* a0 */
7738     { Bad_Opcode },
7739     { Bad_Opcode },
7740     { Bad_Opcode },
7741     { Bad_Opcode },
7742     { Bad_Opcode },
7743     { Bad_Opcode },
7744     { Bad_Opcode },
7745     { Bad_Opcode },
7746     /* a8 */
7747     { Bad_Opcode },
7748     { Bad_Opcode },
7749     { Bad_Opcode },
7750     { Bad_Opcode },
7751     { Bad_Opcode },
7752     { Bad_Opcode },
7753     { Bad_Opcode },
7754     { Bad_Opcode },
7755     /* b0 */
7756     { Bad_Opcode },
7757     { Bad_Opcode },
7758     { Bad_Opcode },
7759     { Bad_Opcode },
7760     { Bad_Opcode },
7761     { Bad_Opcode },
7762     { Bad_Opcode },
7763     { Bad_Opcode },
7764     /* b8 */
7765     { Bad_Opcode },
7766     { Bad_Opcode },
7767     { Bad_Opcode },
7768     { Bad_Opcode },
7769     { Bad_Opcode },
7770     { Bad_Opcode },
7771     { Bad_Opcode },
7772     { Bad_Opcode },
7773     /* c0 */
7774     { Bad_Opcode },
7775     { Bad_Opcode },
7776     { Bad_Opcode },
7777     { Bad_Opcode },
7778     { Bad_Opcode },
7779     { Bad_Opcode },
7780     { Bad_Opcode },
7781     { Bad_Opcode },
7782     /* c8 */
7783     { Bad_Opcode },
7784     { Bad_Opcode },
7785     { Bad_Opcode },
7786     { Bad_Opcode },
7787     { Bad_Opcode },
7788     { Bad_Opcode },
7789     { Bad_Opcode },
7790     { Bad_Opcode },
7791     /* d0 */
7792     { Bad_Opcode },
7793     { Bad_Opcode },
7794     { Bad_Opcode },
7795     { Bad_Opcode },
7796     { Bad_Opcode },
7797     { Bad_Opcode },
7798     { Bad_Opcode },
7799     { Bad_Opcode },
7800     /* d8 */
7801     { Bad_Opcode },
7802     { Bad_Opcode },
7803     { Bad_Opcode },
7804     { Bad_Opcode },
7805     { Bad_Opcode },
7806     { Bad_Opcode },
7807     { Bad_Opcode },
7808     { Bad_Opcode },
7809     /* e0 */
7810     { Bad_Opcode },
7811     { Bad_Opcode },
7812     { Bad_Opcode },
7813     { Bad_Opcode },
7814     { Bad_Opcode },
7815     { Bad_Opcode },
7816     { Bad_Opcode },
7817     { Bad_Opcode },
7818     /* e8 */
7819     { Bad_Opcode },
7820     { Bad_Opcode },
7821     { Bad_Opcode },
7822     { Bad_Opcode },
7823     { Bad_Opcode },
7824     { Bad_Opcode },
7825     { Bad_Opcode },
7826     { Bad_Opcode },
7827     /* f0 */
7828     { Bad_Opcode },
7829     { Bad_Opcode },
7830     { Bad_Opcode },
7831     { Bad_Opcode },
7832     { Bad_Opcode },
7833     { Bad_Opcode },
7834     { Bad_Opcode },
7835     { Bad_Opcode },
7836     /* f8 */
7837     { Bad_Opcode },
7838     { Bad_Opcode },
7839     { Bad_Opcode },
7840     { Bad_Opcode },
7841     { Bad_Opcode },
7842     { Bad_Opcode },
7843     { Bad_Opcode },
7844     { Bad_Opcode },
7845   },
7846 };
7847
7848 static const struct dis386 xop_table[][256] = {
7849   /* XOP_08 */
7850   {
7851     /* 00 */
7852     { Bad_Opcode },
7853     { Bad_Opcode },
7854     { Bad_Opcode },
7855     { Bad_Opcode },
7856     { Bad_Opcode },
7857     { Bad_Opcode },
7858     { Bad_Opcode },
7859     { Bad_Opcode },
7860     /* 08 */
7861     { Bad_Opcode },
7862     { Bad_Opcode },
7863     { Bad_Opcode },
7864     { Bad_Opcode },
7865     { Bad_Opcode },
7866     { Bad_Opcode },
7867     { Bad_Opcode },
7868     { Bad_Opcode },
7869     /* 10 */
7870     { Bad_Opcode },
7871     { Bad_Opcode },
7872     { Bad_Opcode },
7873     { Bad_Opcode },
7874     { Bad_Opcode },
7875     { Bad_Opcode },
7876     { Bad_Opcode },
7877     { Bad_Opcode },
7878     /* 18 */
7879     { Bad_Opcode },
7880     { Bad_Opcode },
7881     { Bad_Opcode },
7882     { Bad_Opcode },
7883     { Bad_Opcode },
7884     { Bad_Opcode },
7885     { Bad_Opcode },
7886     { Bad_Opcode },
7887     /* 20 */
7888     { Bad_Opcode },
7889     { Bad_Opcode },
7890     { Bad_Opcode },
7891     { Bad_Opcode },
7892     { Bad_Opcode },
7893     { Bad_Opcode },
7894     { Bad_Opcode },
7895     { Bad_Opcode },
7896     /* 28 */
7897     { Bad_Opcode },
7898     { Bad_Opcode },
7899     { Bad_Opcode },
7900     { Bad_Opcode },
7901     { Bad_Opcode },
7902     { Bad_Opcode },
7903     { Bad_Opcode },
7904     { Bad_Opcode },
7905     /* 30 */
7906     { Bad_Opcode },
7907     { Bad_Opcode },
7908     { Bad_Opcode },
7909     { Bad_Opcode },
7910     { Bad_Opcode },
7911     { Bad_Opcode },
7912     { Bad_Opcode },
7913     { Bad_Opcode },
7914     /* 38 */
7915     { Bad_Opcode },
7916     { Bad_Opcode },
7917     { Bad_Opcode },
7918     { Bad_Opcode },
7919     { Bad_Opcode },
7920     { Bad_Opcode },
7921     { Bad_Opcode },
7922     { Bad_Opcode },
7923     /* 40 */
7924     { Bad_Opcode },
7925     { Bad_Opcode },
7926     { Bad_Opcode },
7927     { Bad_Opcode },
7928     { Bad_Opcode },
7929     { Bad_Opcode },
7930     { Bad_Opcode },
7931     { Bad_Opcode },
7932     /* 48 */
7933     { Bad_Opcode },
7934     { Bad_Opcode },
7935     { Bad_Opcode },
7936     { Bad_Opcode },
7937     { Bad_Opcode },
7938     { Bad_Opcode },
7939     { Bad_Opcode },
7940     { Bad_Opcode },
7941     /* 50 */
7942     { Bad_Opcode },
7943     { Bad_Opcode },
7944     { Bad_Opcode },
7945     { Bad_Opcode },
7946     { Bad_Opcode },
7947     { Bad_Opcode },
7948     { Bad_Opcode },
7949     { Bad_Opcode },
7950     /* 58 */
7951     { Bad_Opcode },
7952     { Bad_Opcode },
7953     { Bad_Opcode },
7954     { Bad_Opcode },
7955     { Bad_Opcode },
7956     { Bad_Opcode },
7957     { Bad_Opcode },
7958     { Bad_Opcode },
7959     /* 60 */
7960     { Bad_Opcode },
7961     { Bad_Opcode },
7962     { Bad_Opcode },
7963     { Bad_Opcode },
7964     { Bad_Opcode },
7965     { Bad_Opcode },
7966     { Bad_Opcode },
7967     { Bad_Opcode },
7968     /* 68 */
7969     { Bad_Opcode },
7970     { Bad_Opcode },
7971     { Bad_Opcode },
7972     { Bad_Opcode },
7973     { Bad_Opcode },
7974     { Bad_Opcode },
7975     { Bad_Opcode },
7976     { Bad_Opcode },
7977     /* 70 */
7978     { Bad_Opcode },
7979     { Bad_Opcode },
7980     { Bad_Opcode },
7981     { Bad_Opcode },
7982     { Bad_Opcode },
7983     { Bad_Opcode },
7984     { Bad_Opcode },
7985     { Bad_Opcode },
7986     /* 78 */
7987     { Bad_Opcode },
7988     { Bad_Opcode },
7989     { Bad_Opcode },
7990     { Bad_Opcode },
7991     { Bad_Opcode },
7992     { Bad_Opcode },
7993     { Bad_Opcode },
7994     { Bad_Opcode },
7995     /* 80 */
7996     { Bad_Opcode },
7997     { Bad_Opcode },
7998     { Bad_Opcode },
7999     { Bad_Opcode },
8000     { Bad_Opcode },
8001     { "vpmacssww",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
8002     { "vpmacsswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
8003     { "vpmacssdql",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
8004     /* 88 */
8005     { Bad_Opcode },
8006     { Bad_Opcode },
8007     { Bad_Opcode },
8008     { Bad_Opcode },
8009     { Bad_Opcode },
8010     { Bad_Opcode },
8011     { "vpmacssdd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
8012     { "vpmacssdqh",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
8013     /* 90 */
8014     { Bad_Opcode },
8015     { Bad_Opcode },
8016     { Bad_Opcode },
8017     { Bad_Opcode },
8018     { Bad_Opcode },
8019     { "vpmacsww",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
8020     { "vpmacswd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
8021     { "vpmacsdql",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
8022     /* 98 */
8023     { Bad_Opcode },
8024     { Bad_Opcode },
8025     { Bad_Opcode },
8026     { Bad_Opcode },
8027     { Bad_Opcode },
8028     { Bad_Opcode },
8029     { "vpmacsdd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
8030     { "vpmacsdqh",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
8031     /* a0 */
8032     { Bad_Opcode },
8033     { Bad_Opcode },
8034     { "vpcmov",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
8035     { "vpperm",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
8036     { Bad_Opcode },
8037     { Bad_Opcode },
8038     { "vpmadcsswd",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
8039     { Bad_Opcode },
8040     /* a8 */
8041     { Bad_Opcode },
8042     { Bad_Opcode },
8043     { Bad_Opcode },
8044     { Bad_Opcode },
8045     { Bad_Opcode },
8046     { Bad_Opcode },
8047     { Bad_Opcode },
8048     { Bad_Opcode },
8049     /* b0 */
8050     { Bad_Opcode },
8051     { Bad_Opcode },
8052     { Bad_Opcode },
8053     { Bad_Opcode },
8054     { Bad_Opcode },
8055     { Bad_Opcode },
8056     { "vpmadcswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
8057     { Bad_Opcode },
8058     /* b8 */
8059     { Bad_Opcode },
8060     { Bad_Opcode },
8061     { Bad_Opcode },
8062     { Bad_Opcode },
8063     { Bad_Opcode },
8064     { Bad_Opcode },
8065     { Bad_Opcode },
8066     { Bad_Opcode },
8067     /* c0 */
8068     { "vprotb",         { XM, Vex_2src_1, Ib }, 0 },
8069     { "vprotw",         { XM, Vex_2src_1, Ib }, 0 },
8070     { "vprotd",         { XM, Vex_2src_1, Ib }, 0 },
8071     { "vprotq",         { XM, Vex_2src_1, Ib }, 0 },
8072     { Bad_Opcode },
8073     { Bad_Opcode },
8074     { Bad_Opcode },
8075     { Bad_Opcode },
8076     /* c8 */
8077     { Bad_Opcode },
8078     { Bad_Opcode },
8079     { Bad_Opcode },
8080     { Bad_Opcode },
8081     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
8082     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
8083     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
8084     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
8085     /* d0 */
8086     { Bad_Opcode },
8087     { Bad_Opcode },
8088     { Bad_Opcode },
8089     { Bad_Opcode },
8090     { Bad_Opcode },
8091     { Bad_Opcode },
8092     { Bad_Opcode },
8093     { Bad_Opcode },
8094     /* d8 */
8095     { Bad_Opcode },
8096     { Bad_Opcode },
8097     { Bad_Opcode },
8098     { Bad_Opcode },
8099     { Bad_Opcode },
8100     { Bad_Opcode },
8101     { Bad_Opcode },
8102     { Bad_Opcode },
8103     /* e0 */
8104     { Bad_Opcode },
8105     { Bad_Opcode },
8106     { Bad_Opcode },
8107     { Bad_Opcode },
8108     { Bad_Opcode },
8109     { Bad_Opcode },
8110     { Bad_Opcode },
8111     { Bad_Opcode },
8112     /* e8 */
8113     { Bad_Opcode },
8114     { Bad_Opcode },
8115     { Bad_Opcode },
8116     { Bad_Opcode },
8117     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
8118     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
8119     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
8120     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
8121     /* f0 */
8122     { Bad_Opcode },
8123     { Bad_Opcode },
8124     { Bad_Opcode },
8125     { Bad_Opcode },
8126     { Bad_Opcode },
8127     { Bad_Opcode },
8128     { Bad_Opcode },
8129     { Bad_Opcode },
8130     /* f8 */
8131     { Bad_Opcode },
8132     { Bad_Opcode },
8133     { Bad_Opcode },
8134     { Bad_Opcode },
8135     { Bad_Opcode },
8136     { Bad_Opcode },
8137     { Bad_Opcode },
8138     { Bad_Opcode },
8139   },
8140   /* XOP_09 */
8141   {
8142     /* 00 */
8143     { Bad_Opcode },
8144     { REG_TABLE (REG_XOP_TBM_01) },
8145     { REG_TABLE (REG_XOP_TBM_02) },
8146     { Bad_Opcode },
8147     { Bad_Opcode },
8148     { Bad_Opcode },
8149     { Bad_Opcode },
8150     { Bad_Opcode },
8151     /* 08 */
8152     { Bad_Opcode },
8153     { Bad_Opcode },
8154     { Bad_Opcode },
8155     { Bad_Opcode },
8156     { Bad_Opcode },
8157     { Bad_Opcode },
8158     { Bad_Opcode },
8159     { Bad_Opcode },
8160     /* 10 */
8161     { Bad_Opcode },
8162     { Bad_Opcode },
8163     { REG_TABLE (REG_XOP_LWPCB) },
8164     { Bad_Opcode },
8165     { Bad_Opcode },
8166     { Bad_Opcode },
8167     { Bad_Opcode },
8168     { Bad_Opcode },
8169     /* 18 */
8170     { Bad_Opcode },
8171     { Bad_Opcode },
8172     { Bad_Opcode },
8173     { Bad_Opcode },
8174     { Bad_Opcode },
8175     { Bad_Opcode },
8176     { Bad_Opcode },
8177     { Bad_Opcode },
8178     /* 20 */
8179     { Bad_Opcode },
8180     { Bad_Opcode },
8181     { Bad_Opcode },
8182     { Bad_Opcode },
8183     { Bad_Opcode },
8184     { Bad_Opcode },
8185     { Bad_Opcode },
8186     { Bad_Opcode },
8187     /* 28 */
8188     { Bad_Opcode },
8189     { Bad_Opcode },
8190     { Bad_Opcode },
8191     { Bad_Opcode },
8192     { Bad_Opcode },
8193     { Bad_Opcode },
8194     { Bad_Opcode },
8195     { Bad_Opcode },
8196     /* 30 */
8197     { Bad_Opcode },
8198     { Bad_Opcode },
8199     { Bad_Opcode },
8200     { Bad_Opcode },
8201     { Bad_Opcode },
8202     { Bad_Opcode },
8203     { Bad_Opcode },
8204     { Bad_Opcode },
8205     /* 38 */
8206     { Bad_Opcode },
8207     { Bad_Opcode },
8208     { Bad_Opcode },
8209     { Bad_Opcode },
8210     { Bad_Opcode },
8211     { Bad_Opcode },
8212     { Bad_Opcode },
8213     { Bad_Opcode },
8214     /* 40 */
8215     { Bad_Opcode },
8216     { Bad_Opcode },
8217     { Bad_Opcode },
8218     { Bad_Opcode },
8219     { Bad_Opcode },
8220     { Bad_Opcode },
8221     { Bad_Opcode },
8222     { Bad_Opcode },
8223     /* 48 */
8224     { Bad_Opcode },
8225     { Bad_Opcode },
8226     { Bad_Opcode },
8227     { Bad_Opcode },
8228     { Bad_Opcode },
8229     { Bad_Opcode },
8230     { Bad_Opcode },
8231     { Bad_Opcode },
8232     /* 50 */
8233     { Bad_Opcode },
8234     { Bad_Opcode },
8235     { Bad_Opcode },
8236     { Bad_Opcode },
8237     { Bad_Opcode },
8238     { Bad_Opcode },
8239     { Bad_Opcode },
8240     { Bad_Opcode },
8241     /* 58 */
8242     { Bad_Opcode },
8243     { Bad_Opcode },
8244     { Bad_Opcode },
8245     { Bad_Opcode },
8246     { Bad_Opcode },
8247     { Bad_Opcode },
8248     { Bad_Opcode },
8249     { Bad_Opcode },
8250     /* 60 */
8251     { Bad_Opcode },
8252     { Bad_Opcode },
8253     { Bad_Opcode },
8254     { Bad_Opcode },
8255     { Bad_Opcode },
8256     { Bad_Opcode },
8257     { Bad_Opcode },
8258     { Bad_Opcode },
8259     /* 68 */
8260     { Bad_Opcode },
8261     { Bad_Opcode },
8262     { Bad_Opcode },
8263     { Bad_Opcode },
8264     { Bad_Opcode },
8265     { Bad_Opcode },
8266     { Bad_Opcode },
8267     { Bad_Opcode },
8268     /* 70 */
8269     { Bad_Opcode },
8270     { Bad_Opcode },
8271     { Bad_Opcode },
8272     { Bad_Opcode },
8273     { Bad_Opcode },
8274     { Bad_Opcode },
8275     { Bad_Opcode },
8276     { Bad_Opcode },
8277     /* 78 */
8278     { Bad_Opcode },
8279     { Bad_Opcode },
8280     { Bad_Opcode },
8281     { Bad_Opcode },
8282     { Bad_Opcode },
8283     { Bad_Opcode },
8284     { Bad_Opcode },
8285     { Bad_Opcode },
8286     /* 80 */
8287     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
8288     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
8289     { "vfrczss",        { XM, EXd }, 0 },
8290     { "vfrczsd",        { XM, EXq }, 0 },
8291     { Bad_Opcode },
8292     { Bad_Opcode },
8293     { Bad_Opcode },
8294     { Bad_Opcode },
8295     /* 88 */
8296     { Bad_Opcode },
8297     { Bad_Opcode },
8298     { Bad_Opcode },
8299     { Bad_Opcode },
8300     { Bad_Opcode },
8301     { Bad_Opcode },
8302     { Bad_Opcode },
8303     { Bad_Opcode },
8304     /* 90 */
8305     { "vprotb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8306     { "vprotw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8307     { "vprotd",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8308     { "vprotq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8309     { "vpshlb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8310     { "vpshlw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8311     { "vpshld",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8312     { "vpshlq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8313     /* 98 */
8314     { "vpshab",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8315     { "vpshaw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8316     { "vpshad",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8317     { "vpshaq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8318     { Bad_Opcode },
8319     { Bad_Opcode },
8320     { Bad_Opcode },
8321     { Bad_Opcode },
8322     /* a0 */
8323     { Bad_Opcode },
8324     { Bad_Opcode },
8325     { Bad_Opcode },
8326     { Bad_Opcode },
8327     { Bad_Opcode },
8328     { Bad_Opcode },
8329     { Bad_Opcode },
8330     { Bad_Opcode },
8331     /* a8 */
8332     { Bad_Opcode },
8333     { Bad_Opcode },
8334     { Bad_Opcode },
8335     { Bad_Opcode },
8336     { Bad_Opcode },
8337     { Bad_Opcode },
8338     { Bad_Opcode },
8339     { Bad_Opcode },
8340     /* b0 */
8341     { Bad_Opcode },
8342     { Bad_Opcode },
8343     { Bad_Opcode },
8344     { Bad_Opcode },
8345     { Bad_Opcode },
8346     { Bad_Opcode },
8347     { Bad_Opcode },
8348     { Bad_Opcode },
8349     /* b8 */
8350     { Bad_Opcode },
8351     { Bad_Opcode },
8352     { Bad_Opcode },
8353     { Bad_Opcode },
8354     { Bad_Opcode },
8355     { Bad_Opcode },
8356     { Bad_Opcode },
8357     { Bad_Opcode },
8358     /* c0 */
8359     { Bad_Opcode },
8360     { "vphaddbw",       { XM, EXxmm }, 0 },
8361     { "vphaddbd",       { XM, EXxmm }, 0 },
8362     { "vphaddbq",       { XM, EXxmm }, 0 },
8363     { Bad_Opcode },
8364     { Bad_Opcode },
8365     { "vphaddwd",       { XM, EXxmm }, 0 },
8366     { "vphaddwq",       { XM, EXxmm }, 0 },
8367     /* c8 */
8368     { Bad_Opcode },
8369     { Bad_Opcode },
8370     { Bad_Opcode },
8371     { "vphadddq",       { XM, EXxmm }, 0 },
8372     { Bad_Opcode },
8373     { Bad_Opcode },
8374     { Bad_Opcode },
8375     { Bad_Opcode },
8376     /* d0 */
8377     { Bad_Opcode },
8378     { "vphaddubw",      { XM, EXxmm }, 0 },
8379     { "vphaddubd",      { XM, EXxmm }, 0 },
8380     { "vphaddubq",      { XM, EXxmm }, 0 },
8381     { Bad_Opcode },
8382     { Bad_Opcode },
8383     { "vphadduwd",      { XM, EXxmm }, 0 },
8384     { "vphadduwq",      { XM, EXxmm }, 0 },
8385     /* d8 */
8386     { Bad_Opcode },
8387     { Bad_Opcode },
8388     { Bad_Opcode },
8389     { "vphaddudq",      { XM, EXxmm }, 0 },
8390     { Bad_Opcode },
8391     { Bad_Opcode },
8392     { Bad_Opcode },
8393     { Bad_Opcode },
8394     /* e0 */
8395     { Bad_Opcode },
8396     { "vphsubbw",       { XM, EXxmm }, 0 },
8397     { "vphsubwd",       { XM, EXxmm }, 0 },
8398     { "vphsubdq",       { XM, EXxmm }, 0 },
8399     { Bad_Opcode },
8400     { Bad_Opcode },
8401     { Bad_Opcode },
8402     { Bad_Opcode },
8403     /* e8 */
8404     { Bad_Opcode },
8405     { Bad_Opcode },
8406     { Bad_Opcode },
8407     { Bad_Opcode },
8408     { Bad_Opcode },
8409     { Bad_Opcode },
8410     { Bad_Opcode },
8411     { Bad_Opcode },
8412     /* f0 */
8413     { Bad_Opcode },
8414     { Bad_Opcode },
8415     { Bad_Opcode },
8416     { Bad_Opcode },
8417     { Bad_Opcode },
8418     { Bad_Opcode },
8419     { Bad_Opcode },
8420     { Bad_Opcode },
8421     /* f8 */
8422     { Bad_Opcode },
8423     { Bad_Opcode },
8424     { Bad_Opcode },
8425     { Bad_Opcode },
8426     { Bad_Opcode },
8427     { Bad_Opcode },
8428     { Bad_Opcode },
8429     { Bad_Opcode },
8430   },
8431   /* XOP_0A */
8432   {
8433     /* 00 */
8434     { Bad_Opcode },
8435     { Bad_Opcode },
8436     { Bad_Opcode },
8437     { Bad_Opcode },
8438     { Bad_Opcode },
8439     { Bad_Opcode },
8440     { Bad_Opcode },
8441     { Bad_Opcode },
8442     /* 08 */
8443     { Bad_Opcode },
8444     { Bad_Opcode },
8445     { Bad_Opcode },
8446     { Bad_Opcode },
8447     { Bad_Opcode },
8448     { Bad_Opcode },
8449     { Bad_Opcode },
8450     { Bad_Opcode },
8451     /* 10 */
8452     { "bextr",  { Gv, Ev, Iq }, 0 },
8453     { Bad_Opcode },
8454     { REG_TABLE (REG_XOP_LWP) },
8455     { Bad_Opcode },
8456     { Bad_Opcode },
8457     { Bad_Opcode },
8458     { Bad_Opcode },
8459     { Bad_Opcode },
8460     /* 18 */
8461     { Bad_Opcode },
8462     { Bad_Opcode },
8463     { Bad_Opcode },
8464     { Bad_Opcode },
8465     { Bad_Opcode },
8466     { Bad_Opcode },
8467     { Bad_Opcode },
8468     { Bad_Opcode },
8469     /* 20 */
8470     { Bad_Opcode },
8471     { Bad_Opcode },
8472     { Bad_Opcode },
8473     { Bad_Opcode },
8474     { Bad_Opcode },
8475     { Bad_Opcode },
8476     { Bad_Opcode },
8477     { Bad_Opcode },
8478     /* 28 */
8479     { Bad_Opcode },
8480     { Bad_Opcode },
8481     { Bad_Opcode },
8482     { Bad_Opcode },
8483     { Bad_Opcode },
8484     { Bad_Opcode },
8485     { Bad_Opcode },
8486     { Bad_Opcode },
8487     /* 30 */
8488     { Bad_Opcode },
8489     { Bad_Opcode },
8490     { Bad_Opcode },
8491     { Bad_Opcode },
8492     { Bad_Opcode },
8493     { Bad_Opcode },
8494     { Bad_Opcode },
8495     { Bad_Opcode },
8496     /* 38 */
8497     { Bad_Opcode },
8498     { Bad_Opcode },
8499     { Bad_Opcode },
8500     { Bad_Opcode },
8501     { Bad_Opcode },
8502     { Bad_Opcode },
8503     { Bad_Opcode },
8504     { Bad_Opcode },
8505     /* 40 */
8506     { Bad_Opcode },
8507     { Bad_Opcode },
8508     { Bad_Opcode },
8509     { Bad_Opcode },
8510     { Bad_Opcode },
8511     { Bad_Opcode },
8512     { Bad_Opcode },
8513     { Bad_Opcode },
8514     /* 48 */
8515     { Bad_Opcode },
8516     { Bad_Opcode },
8517     { Bad_Opcode },
8518     { Bad_Opcode },
8519     { Bad_Opcode },
8520     { Bad_Opcode },
8521     { Bad_Opcode },
8522     { Bad_Opcode },
8523     /* 50 */
8524     { Bad_Opcode },
8525     { Bad_Opcode },
8526     { Bad_Opcode },
8527     { Bad_Opcode },
8528     { Bad_Opcode },
8529     { Bad_Opcode },
8530     { Bad_Opcode },
8531     { Bad_Opcode },
8532     /* 58 */
8533     { Bad_Opcode },
8534     { Bad_Opcode },
8535     { Bad_Opcode },
8536     { Bad_Opcode },
8537     { Bad_Opcode },
8538     { Bad_Opcode },
8539     { Bad_Opcode },
8540     { Bad_Opcode },
8541     /* 60 */
8542     { Bad_Opcode },
8543     { Bad_Opcode },
8544     { Bad_Opcode },
8545     { Bad_Opcode },
8546     { Bad_Opcode },
8547     { Bad_Opcode },
8548     { Bad_Opcode },
8549     { Bad_Opcode },
8550     /* 68 */
8551     { Bad_Opcode },
8552     { Bad_Opcode },
8553     { Bad_Opcode },
8554     { Bad_Opcode },
8555     { Bad_Opcode },
8556     { Bad_Opcode },
8557     { Bad_Opcode },
8558     { Bad_Opcode },
8559     /* 70 */
8560     { Bad_Opcode },
8561     { Bad_Opcode },
8562     { Bad_Opcode },
8563     { Bad_Opcode },
8564     { Bad_Opcode },
8565     { Bad_Opcode },
8566     { Bad_Opcode },
8567     { Bad_Opcode },
8568     /* 78 */
8569     { Bad_Opcode },
8570     { Bad_Opcode },
8571     { Bad_Opcode },
8572     { Bad_Opcode },
8573     { Bad_Opcode },
8574     { Bad_Opcode },
8575     { Bad_Opcode },
8576     { Bad_Opcode },
8577     /* 80 */
8578     { Bad_Opcode },
8579     { Bad_Opcode },
8580     { Bad_Opcode },
8581     { Bad_Opcode },
8582     { Bad_Opcode },
8583     { Bad_Opcode },
8584     { Bad_Opcode },
8585     { Bad_Opcode },
8586     /* 88 */
8587     { Bad_Opcode },
8588     { Bad_Opcode },
8589     { Bad_Opcode },
8590     { Bad_Opcode },
8591     { Bad_Opcode },
8592     { Bad_Opcode },
8593     { Bad_Opcode },
8594     { Bad_Opcode },
8595     /* 90 */
8596     { Bad_Opcode },
8597     { Bad_Opcode },
8598     { Bad_Opcode },
8599     { Bad_Opcode },
8600     { Bad_Opcode },
8601     { Bad_Opcode },
8602     { Bad_Opcode },
8603     { Bad_Opcode },
8604     /* 98 */
8605     { Bad_Opcode },
8606     { Bad_Opcode },
8607     { Bad_Opcode },
8608     { Bad_Opcode },
8609     { Bad_Opcode },
8610     { Bad_Opcode },
8611     { Bad_Opcode },
8612     { Bad_Opcode },
8613     /* a0 */
8614     { Bad_Opcode },
8615     { Bad_Opcode },
8616     { Bad_Opcode },
8617     { Bad_Opcode },
8618     { Bad_Opcode },
8619     { Bad_Opcode },
8620     { Bad_Opcode },
8621     { Bad_Opcode },
8622     /* a8 */
8623     { Bad_Opcode },
8624     { Bad_Opcode },
8625     { Bad_Opcode },
8626     { Bad_Opcode },
8627     { Bad_Opcode },
8628     { Bad_Opcode },
8629     { Bad_Opcode },
8630     { Bad_Opcode },
8631     /* b0 */
8632     { Bad_Opcode },
8633     { Bad_Opcode },
8634     { Bad_Opcode },
8635     { Bad_Opcode },
8636     { Bad_Opcode },
8637     { Bad_Opcode },
8638     { Bad_Opcode },
8639     { Bad_Opcode },
8640     /* b8 */
8641     { Bad_Opcode },
8642     { Bad_Opcode },
8643     { Bad_Opcode },
8644     { Bad_Opcode },
8645     { Bad_Opcode },
8646     { Bad_Opcode },
8647     { Bad_Opcode },
8648     { Bad_Opcode },
8649     /* c0 */
8650     { Bad_Opcode },
8651     { Bad_Opcode },
8652     { Bad_Opcode },
8653     { Bad_Opcode },
8654     { Bad_Opcode },
8655     { Bad_Opcode },
8656     { Bad_Opcode },
8657     { Bad_Opcode },
8658     /* c8 */
8659     { Bad_Opcode },
8660     { Bad_Opcode },
8661     { Bad_Opcode },
8662     { Bad_Opcode },
8663     { Bad_Opcode },
8664     { Bad_Opcode },
8665     { Bad_Opcode },
8666     { Bad_Opcode },
8667     /* d0 */
8668     { Bad_Opcode },
8669     { Bad_Opcode },
8670     { Bad_Opcode },
8671     { Bad_Opcode },
8672     { Bad_Opcode },
8673     { Bad_Opcode },
8674     { Bad_Opcode },
8675     { Bad_Opcode },
8676     /* d8 */
8677     { Bad_Opcode },
8678     { Bad_Opcode },
8679     { Bad_Opcode },
8680     { Bad_Opcode },
8681     { Bad_Opcode },
8682     { Bad_Opcode },
8683     { Bad_Opcode },
8684     { Bad_Opcode },
8685     /* e0 */
8686     { Bad_Opcode },
8687     { Bad_Opcode },
8688     { Bad_Opcode },
8689     { Bad_Opcode },
8690     { Bad_Opcode },
8691     { Bad_Opcode },
8692     { Bad_Opcode },
8693     { Bad_Opcode },
8694     /* e8 */
8695     { Bad_Opcode },
8696     { Bad_Opcode },
8697     { Bad_Opcode },
8698     { Bad_Opcode },
8699     { Bad_Opcode },
8700     { Bad_Opcode },
8701     { Bad_Opcode },
8702     { Bad_Opcode },
8703     /* f0 */
8704     { Bad_Opcode },
8705     { Bad_Opcode },
8706     { Bad_Opcode },
8707     { Bad_Opcode },
8708     { Bad_Opcode },
8709     { Bad_Opcode },
8710     { Bad_Opcode },
8711     { Bad_Opcode },
8712     /* f8 */
8713     { Bad_Opcode },
8714     { Bad_Opcode },
8715     { Bad_Opcode },
8716     { Bad_Opcode },
8717     { Bad_Opcode },
8718     { Bad_Opcode },
8719     { Bad_Opcode },
8720     { Bad_Opcode },
8721   },
8722 };
8723
8724 static const struct dis386 vex_table[][256] = {
8725   /* VEX_0F */
8726   {
8727     /* 00 */
8728     { Bad_Opcode },
8729     { Bad_Opcode },
8730     { Bad_Opcode },
8731     { Bad_Opcode },
8732     { Bad_Opcode },
8733     { Bad_Opcode },
8734     { Bad_Opcode },
8735     { Bad_Opcode },
8736     /* 08 */
8737     { Bad_Opcode },
8738     { Bad_Opcode },
8739     { Bad_Opcode },
8740     { Bad_Opcode },
8741     { Bad_Opcode },
8742     { Bad_Opcode },
8743     { Bad_Opcode },
8744     { Bad_Opcode },
8745     /* 10 */
8746     { PREFIX_TABLE (PREFIX_VEX_0F10) },
8747     { PREFIX_TABLE (PREFIX_VEX_0F11) },
8748     { PREFIX_TABLE (PREFIX_VEX_0F12) },
8749     { MOD_TABLE (MOD_VEX_0F13) },
8750     { VEX_W_TABLE (VEX_W_0F14) },
8751     { VEX_W_TABLE (VEX_W_0F15) },
8752     { PREFIX_TABLE (PREFIX_VEX_0F16) },
8753     { MOD_TABLE (MOD_VEX_0F17) },
8754     /* 18 */
8755     { Bad_Opcode },
8756     { Bad_Opcode },
8757     { Bad_Opcode },
8758     { Bad_Opcode },
8759     { Bad_Opcode },
8760     { Bad_Opcode },
8761     { Bad_Opcode },
8762     { Bad_Opcode },
8763     /* 20 */
8764     { Bad_Opcode },
8765     { Bad_Opcode },
8766     { Bad_Opcode },
8767     { Bad_Opcode },
8768     { Bad_Opcode },
8769     { Bad_Opcode },
8770     { Bad_Opcode },
8771     { Bad_Opcode },
8772     /* 28 */
8773     { VEX_W_TABLE (VEX_W_0F28) },
8774     { VEX_W_TABLE (VEX_W_0F29) },
8775     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8776     { MOD_TABLE (MOD_VEX_0F2B) },
8777     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8778     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8779     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8780     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8781     /* 30 */
8782     { Bad_Opcode },
8783     { Bad_Opcode },
8784     { Bad_Opcode },
8785     { Bad_Opcode },
8786     { Bad_Opcode },
8787     { Bad_Opcode },
8788     { Bad_Opcode },
8789     { Bad_Opcode },
8790     /* 38 */
8791     { Bad_Opcode },
8792     { Bad_Opcode },
8793     { Bad_Opcode },
8794     { Bad_Opcode },
8795     { Bad_Opcode },
8796     { Bad_Opcode },
8797     { Bad_Opcode },
8798     { Bad_Opcode },
8799     /* 40 */
8800     { Bad_Opcode },
8801     { PREFIX_TABLE (PREFIX_VEX_0F41) },
8802     { PREFIX_TABLE (PREFIX_VEX_0F42) },
8803     { Bad_Opcode },
8804     { PREFIX_TABLE (PREFIX_VEX_0F44) },
8805     { PREFIX_TABLE (PREFIX_VEX_0F45) },
8806     { PREFIX_TABLE (PREFIX_VEX_0F46) },
8807     { PREFIX_TABLE (PREFIX_VEX_0F47) },
8808     /* 48 */
8809     { Bad_Opcode },
8810     { Bad_Opcode },
8811     { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8812     { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8813     { Bad_Opcode },
8814     { Bad_Opcode },
8815     { Bad_Opcode },
8816     { Bad_Opcode },
8817     /* 50 */
8818     { MOD_TABLE (MOD_VEX_0F50) },
8819     { PREFIX_TABLE (PREFIX_VEX_0F51) },
8820     { PREFIX_TABLE (PREFIX_VEX_0F52) },
8821     { PREFIX_TABLE (PREFIX_VEX_0F53) },
8822     { "vandpX",         { XM, Vex, EXx }, 0 },
8823     { "vandnpX",        { XM, Vex, EXx }, 0 },
8824     { "vorpX",          { XM, Vex, EXx }, 0 },
8825     { "vxorpX",         { XM, Vex, EXx }, 0 },
8826     /* 58 */
8827     { PREFIX_TABLE (PREFIX_VEX_0F58) },
8828     { PREFIX_TABLE (PREFIX_VEX_0F59) },
8829     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8830     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8831     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8832     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8833     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8834     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8835     /* 60 */
8836     { PREFIX_TABLE (PREFIX_VEX_0F60) },
8837     { PREFIX_TABLE (PREFIX_VEX_0F61) },
8838     { PREFIX_TABLE (PREFIX_VEX_0F62) },
8839     { PREFIX_TABLE (PREFIX_VEX_0F63) },
8840     { PREFIX_TABLE (PREFIX_VEX_0F64) },
8841     { PREFIX_TABLE (PREFIX_VEX_0F65) },
8842     { PREFIX_TABLE (PREFIX_VEX_0F66) },
8843     { PREFIX_TABLE (PREFIX_VEX_0F67) },
8844     /* 68 */
8845     { PREFIX_TABLE (PREFIX_VEX_0F68) },
8846     { PREFIX_TABLE (PREFIX_VEX_0F69) },
8847     { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8848     { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8849     { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8850     { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8851     { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8852     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8853     /* 70 */
8854     { PREFIX_TABLE (PREFIX_VEX_0F70) },
8855     { REG_TABLE (REG_VEX_0F71) },
8856     { REG_TABLE (REG_VEX_0F72) },
8857     { REG_TABLE (REG_VEX_0F73) },
8858     { PREFIX_TABLE (PREFIX_VEX_0F74) },
8859     { PREFIX_TABLE (PREFIX_VEX_0F75) },
8860     { PREFIX_TABLE (PREFIX_VEX_0F76) },
8861     { PREFIX_TABLE (PREFIX_VEX_0F77) },
8862     /* 78 */
8863     { Bad_Opcode },
8864     { Bad_Opcode },
8865     { Bad_Opcode },
8866     { Bad_Opcode },
8867     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8868     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8869     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8870     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8871     /* 80 */
8872     { Bad_Opcode },
8873     { Bad_Opcode },
8874     { Bad_Opcode },
8875     { Bad_Opcode },
8876     { Bad_Opcode },
8877     { Bad_Opcode },
8878     { Bad_Opcode },
8879     { Bad_Opcode },
8880     /* 88 */
8881     { Bad_Opcode },
8882     { Bad_Opcode },
8883     { Bad_Opcode },
8884     { Bad_Opcode },
8885     { Bad_Opcode },
8886     { Bad_Opcode },
8887     { Bad_Opcode },
8888     { Bad_Opcode },
8889     /* 90 */
8890     { PREFIX_TABLE (PREFIX_VEX_0F90) },
8891     { PREFIX_TABLE (PREFIX_VEX_0F91) },
8892     { PREFIX_TABLE (PREFIX_VEX_0F92) },
8893     { PREFIX_TABLE (PREFIX_VEX_0F93) },
8894     { Bad_Opcode },
8895     { Bad_Opcode },
8896     { Bad_Opcode },
8897     { Bad_Opcode },
8898     /* 98 */
8899     { PREFIX_TABLE (PREFIX_VEX_0F98) },
8900     { PREFIX_TABLE (PREFIX_VEX_0F99) },
8901     { Bad_Opcode },
8902     { Bad_Opcode },
8903     { Bad_Opcode },
8904     { Bad_Opcode },
8905     { Bad_Opcode },
8906     { Bad_Opcode },
8907     /* a0 */
8908     { Bad_Opcode },
8909     { Bad_Opcode },
8910     { Bad_Opcode },
8911     { Bad_Opcode },
8912     { Bad_Opcode },
8913     { Bad_Opcode },
8914     { Bad_Opcode },
8915     { Bad_Opcode },
8916     /* a8 */
8917     { Bad_Opcode },
8918     { Bad_Opcode },
8919     { Bad_Opcode },
8920     { Bad_Opcode },
8921     { Bad_Opcode },
8922     { Bad_Opcode },
8923     { REG_TABLE (REG_VEX_0FAE) },
8924     { Bad_Opcode },
8925     /* b0 */
8926     { Bad_Opcode },
8927     { Bad_Opcode },
8928     { Bad_Opcode },
8929     { Bad_Opcode },
8930     { Bad_Opcode },
8931     { Bad_Opcode },
8932     { Bad_Opcode },
8933     { Bad_Opcode },
8934     /* b8 */
8935     { Bad_Opcode },
8936     { Bad_Opcode },
8937     { Bad_Opcode },
8938     { Bad_Opcode },
8939     { Bad_Opcode },
8940     { Bad_Opcode },
8941     { Bad_Opcode },
8942     { Bad_Opcode },
8943     /* c0 */
8944     { Bad_Opcode },
8945     { Bad_Opcode },
8946     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8947     { Bad_Opcode },
8948     { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8949     { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8950     { "vshufpX",        { XM, Vex, EXx, Ib }, 0 },
8951     { Bad_Opcode },
8952     /* c8 */
8953     { Bad_Opcode },
8954     { Bad_Opcode },
8955     { Bad_Opcode },
8956     { Bad_Opcode },
8957     { Bad_Opcode },
8958     { Bad_Opcode },
8959     { Bad_Opcode },
8960     { Bad_Opcode },
8961     /* d0 */
8962     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8963     { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8964     { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8965     { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8966     { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8967     { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8968     { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8969     { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8970     /* d8 */
8971     { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8972     { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8973     { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8974     { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8975     { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8976     { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8977     { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8978     { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8979     /* e0 */
8980     { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8981     { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8982     { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8983     { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8984     { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8985     { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8986     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8987     { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8988     /* e8 */
8989     { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8990     { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8991     { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8992     { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8993     { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8994     { PREFIX_TABLE (PREFIX_VEX_0FED) },
8995     { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8996     { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8997     /* f0 */
8998     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8999     { PREFIX_TABLE (PREFIX_VEX_0FF1) },
9000     { PREFIX_TABLE (PREFIX_VEX_0FF2) },
9001     { PREFIX_TABLE (PREFIX_VEX_0FF3) },
9002     { PREFIX_TABLE (PREFIX_VEX_0FF4) },
9003     { PREFIX_TABLE (PREFIX_VEX_0FF5) },
9004     { PREFIX_TABLE (PREFIX_VEX_0FF6) },
9005     { PREFIX_TABLE (PREFIX_VEX_0FF7) },
9006     /* f8 */
9007     { PREFIX_TABLE (PREFIX_VEX_0FF8) },
9008     { PREFIX_TABLE (PREFIX_VEX_0FF9) },
9009     { PREFIX_TABLE (PREFIX_VEX_0FFA) },
9010     { PREFIX_TABLE (PREFIX_VEX_0FFB) },
9011     { PREFIX_TABLE (PREFIX_VEX_0FFC) },
9012     { PREFIX_TABLE (PREFIX_VEX_0FFD) },
9013     { PREFIX_TABLE (PREFIX_VEX_0FFE) },
9014     { Bad_Opcode },
9015   },
9016   /* VEX_0F38 */
9017   {
9018     /* 00 */
9019     { PREFIX_TABLE (PREFIX_VEX_0F3800) },
9020     { PREFIX_TABLE (PREFIX_VEX_0F3801) },
9021     { PREFIX_TABLE (PREFIX_VEX_0F3802) },
9022     { PREFIX_TABLE (PREFIX_VEX_0F3803) },
9023     { PREFIX_TABLE (PREFIX_VEX_0F3804) },
9024     { PREFIX_TABLE (PREFIX_VEX_0F3805) },
9025     { PREFIX_TABLE (PREFIX_VEX_0F3806) },
9026     { PREFIX_TABLE (PREFIX_VEX_0F3807) },
9027     /* 08 */
9028     { PREFIX_TABLE (PREFIX_VEX_0F3808) },
9029     { PREFIX_TABLE (PREFIX_VEX_0F3809) },
9030     { PREFIX_TABLE (PREFIX_VEX_0F380A) },
9031     { PREFIX_TABLE (PREFIX_VEX_0F380B) },
9032     { PREFIX_TABLE (PREFIX_VEX_0F380C) },
9033     { PREFIX_TABLE (PREFIX_VEX_0F380D) },
9034     { PREFIX_TABLE (PREFIX_VEX_0F380E) },
9035     { PREFIX_TABLE (PREFIX_VEX_0F380F) },
9036     /* 10 */
9037     { Bad_Opcode },
9038     { Bad_Opcode },
9039     { Bad_Opcode },
9040     { PREFIX_TABLE (PREFIX_VEX_0F3813) },
9041     { Bad_Opcode },
9042     { Bad_Opcode },
9043     { PREFIX_TABLE (PREFIX_VEX_0F3816) },
9044     { PREFIX_TABLE (PREFIX_VEX_0F3817) },
9045     /* 18 */
9046     { PREFIX_TABLE (PREFIX_VEX_0F3818) },
9047     { PREFIX_TABLE (PREFIX_VEX_0F3819) },
9048     { PREFIX_TABLE (PREFIX_VEX_0F381A) },
9049     { Bad_Opcode },
9050     { PREFIX_TABLE (PREFIX_VEX_0F381C) },
9051     { PREFIX_TABLE (PREFIX_VEX_0F381D) },
9052     { PREFIX_TABLE (PREFIX_VEX_0F381E) },
9053     { Bad_Opcode },
9054     /* 20 */
9055     { PREFIX_TABLE (PREFIX_VEX_0F3820) },
9056     { PREFIX_TABLE (PREFIX_VEX_0F3821) },
9057     { PREFIX_TABLE (PREFIX_VEX_0F3822) },
9058     { PREFIX_TABLE (PREFIX_VEX_0F3823) },
9059     { PREFIX_TABLE (PREFIX_VEX_0F3824) },
9060     { PREFIX_TABLE (PREFIX_VEX_0F3825) },
9061     { Bad_Opcode },
9062     { Bad_Opcode },
9063     /* 28 */
9064     { PREFIX_TABLE (PREFIX_VEX_0F3828) },
9065     { PREFIX_TABLE (PREFIX_VEX_0F3829) },
9066     { PREFIX_TABLE (PREFIX_VEX_0F382A) },
9067     { PREFIX_TABLE (PREFIX_VEX_0F382B) },
9068     { PREFIX_TABLE (PREFIX_VEX_0F382C) },
9069     { PREFIX_TABLE (PREFIX_VEX_0F382D) },
9070     { PREFIX_TABLE (PREFIX_VEX_0F382E) },
9071     { PREFIX_TABLE (PREFIX_VEX_0F382F) },
9072     /* 30 */
9073     { PREFIX_TABLE (PREFIX_VEX_0F3830) },
9074     { PREFIX_TABLE (PREFIX_VEX_0F3831) },
9075     { PREFIX_TABLE (PREFIX_VEX_0F3832) },
9076     { PREFIX_TABLE (PREFIX_VEX_0F3833) },
9077     { PREFIX_TABLE (PREFIX_VEX_0F3834) },
9078     { PREFIX_TABLE (PREFIX_VEX_0F3835) },
9079     { PREFIX_TABLE (PREFIX_VEX_0F3836) },
9080     { PREFIX_TABLE (PREFIX_VEX_0F3837) },
9081     /* 38 */
9082     { PREFIX_TABLE (PREFIX_VEX_0F3838) },
9083     { PREFIX_TABLE (PREFIX_VEX_0F3839) },
9084     { PREFIX_TABLE (PREFIX_VEX_0F383A) },
9085     { PREFIX_TABLE (PREFIX_VEX_0F383B) },
9086     { PREFIX_TABLE (PREFIX_VEX_0F383C) },
9087     { PREFIX_TABLE (PREFIX_VEX_0F383D) },
9088     { PREFIX_TABLE (PREFIX_VEX_0F383E) },
9089     { PREFIX_TABLE (PREFIX_VEX_0F383F) },
9090     /* 40 */
9091     { PREFIX_TABLE (PREFIX_VEX_0F3840) },
9092     { PREFIX_TABLE (PREFIX_VEX_0F3841) },
9093     { Bad_Opcode },
9094     { Bad_Opcode },
9095     { Bad_Opcode },
9096     { PREFIX_TABLE (PREFIX_VEX_0F3845) },
9097     { PREFIX_TABLE (PREFIX_VEX_0F3846) },
9098     { PREFIX_TABLE (PREFIX_VEX_0F3847) },
9099     /* 48 */
9100     { Bad_Opcode },
9101     { Bad_Opcode },
9102     { Bad_Opcode },
9103     { Bad_Opcode },
9104     { Bad_Opcode },
9105     { Bad_Opcode },
9106     { Bad_Opcode },
9107     { Bad_Opcode },
9108     /* 50 */
9109     { Bad_Opcode },
9110     { Bad_Opcode },
9111     { Bad_Opcode },
9112     { Bad_Opcode },
9113     { Bad_Opcode },
9114     { Bad_Opcode },
9115     { Bad_Opcode },
9116     { Bad_Opcode },
9117     /* 58 */
9118     { PREFIX_TABLE (PREFIX_VEX_0F3858) },
9119     { PREFIX_TABLE (PREFIX_VEX_0F3859) },
9120     { PREFIX_TABLE (PREFIX_VEX_0F385A) },
9121     { Bad_Opcode },
9122     { Bad_Opcode },
9123     { Bad_Opcode },
9124     { Bad_Opcode },
9125     { Bad_Opcode },
9126     /* 60 */
9127     { Bad_Opcode },
9128     { Bad_Opcode },
9129     { Bad_Opcode },
9130     { Bad_Opcode },
9131     { Bad_Opcode },
9132     { Bad_Opcode },
9133     { Bad_Opcode },
9134     { Bad_Opcode },
9135     /* 68 */
9136     { Bad_Opcode },
9137     { Bad_Opcode },
9138     { Bad_Opcode },
9139     { Bad_Opcode },
9140     { Bad_Opcode },
9141     { Bad_Opcode },
9142     { Bad_Opcode },
9143     { Bad_Opcode },
9144     /* 70 */
9145     { Bad_Opcode },
9146     { Bad_Opcode },
9147     { Bad_Opcode },
9148     { Bad_Opcode },
9149     { Bad_Opcode },
9150     { Bad_Opcode },
9151     { Bad_Opcode },
9152     { Bad_Opcode },
9153     /* 78 */
9154     { PREFIX_TABLE (PREFIX_VEX_0F3878) },
9155     { PREFIX_TABLE (PREFIX_VEX_0F3879) },
9156     { Bad_Opcode },
9157     { Bad_Opcode },
9158     { Bad_Opcode },
9159     { Bad_Opcode },
9160     { Bad_Opcode },
9161     { Bad_Opcode },
9162     /* 80 */
9163     { Bad_Opcode },
9164     { Bad_Opcode },
9165     { Bad_Opcode },
9166     { Bad_Opcode },
9167     { Bad_Opcode },
9168     { Bad_Opcode },
9169     { Bad_Opcode },
9170     { Bad_Opcode },
9171     /* 88 */
9172     { Bad_Opcode },
9173     { Bad_Opcode },
9174     { Bad_Opcode },
9175     { Bad_Opcode },
9176     { PREFIX_TABLE (PREFIX_VEX_0F388C) },
9177     { Bad_Opcode },
9178     { PREFIX_TABLE (PREFIX_VEX_0F388E) },
9179     { Bad_Opcode },
9180     /* 90 */
9181     { PREFIX_TABLE (PREFIX_VEX_0F3890) },
9182     { PREFIX_TABLE (PREFIX_VEX_0F3891) },
9183     { PREFIX_TABLE (PREFIX_VEX_0F3892) },
9184     { PREFIX_TABLE (PREFIX_VEX_0F3893) },
9185     { Bad_Opcode },
9186     { Bad_Opcode },
9187     { PREFIX_TABLE (PREFIX_VEX_0F3896) },
9188     { PREFIX_TABLE (PREFIX_VEX_0F3897) },
9189     /* 98 */
9190     { PREFIX_TABLE (PREFIX_VEX_0F3898) },
9191     { PREFIX_TABLE (PREFIX_VEX_0F3899) },
9192     { PREFIX_TABLE (PREFIX_VEX_0F389A) },
9193     { PREFIX_TABLE (PREFIX_VEX_0F389B) },
9194     { PREFIX_TABLE (PREFIX_VEX_0F389C) },
9195     { PREFIX_TABLE (PREFIX_VEX_0F389D) },
9196     { PREFIX_TABLE (PREFIX_VEX_0F389E) },
9197     { PREFIX_TABLE (PREFIX_VEX_0F389F) },
9198     /* a0 */
9199     { Bad_Opcode },
9200     { Bad_Opcode },
9201     { Bad_Opcode },
9202     { Bad_Opcode },
9203     { Bad_Opcode },
9204     { Bad_Opcode },
9205     { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
9206     { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
9207     /* a8 */
9208     { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
9209     { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
9210     { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
9211     { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
9212     { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
9213     { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
9214     { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
9215     { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
9216     /* b0 */
9217     { Bad_Opcode },
9218     { Bad_Opcode },
9219     { Bad_Opcode },
9220     { Bad_Opcode },
9221     { Bad_Opcode },
9222     { Bad_Opcode },
9223     { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
9224     { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
9225     /* b8 */
9226     { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
9227     { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
9228     { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
9229     { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
9230     { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
9231     { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
9232     { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
9233     { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
9234     /* c0 */
9235     { Bad_Opcode },
9236     { Bad_Opcode },
9237     { Bad_Opcode },
9238     { Bad_Opcode },
9239     { Bad_Opcode },
9240     { Bad_Opcode },
9241     { Bad_Opcode },
9242     { Bad_Opcode },
9243     /* c8 */
9244     { Bad_Opcode },
9245     { Bad_Opcode },
9246     { Bad_Opcode },
9247     { Bad_Opcode },
9248     { Bad_Opcode },
9249     { Bad_Opcode },
9250     { Bad_Opcode },
9251     { Bad_Opcode },
9252     /* d0 */
9253     { Bad_Opcode },
9254     { Bad_Opcode },
9255     { Bad_Opcode },
9256     { Bad_Opcode },
9257     { Bad_Opcode },
9258     { Bad_Opcode },
9259     { Bad_Opcode },
9260     { Bad_Opcode },
9261     /* d8 */
9262     { Bad_Opcode },
9263     { Bad_Opcode },
9264     { Bad_Opcode },
9265     { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
9266     { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
9267     { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
9268     { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
9269     { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
9270     /* e0 */
9271     { Bad_Opcode },
9272     { Bad_Opcode },
9273     { Bad_Opcode },
9274     { Bad_Opcode },
9275     { Bad_Opcode },
9276     { Bad_Opcode },
9277     { Bad_Opcode },
9278     { Bad_Opcode },
9279     /* e8 */
9280     { Bad_Opcode },
9281     { Bad_Opcode },
9282     { Bad_Opcode },
9283     { Bad_Opcode },
9284     { Bad_Opcode },
9285     { Bad_Opcode },
9286     { Bad_Opcode },
9287     { Bad_Opcode },
9288     /* f0 */
9289     { Bad_Opcode },
9290     { Bad_Opcode },
9291     { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
9292     { REG_TABLE (REG_VEX_0F38F3) },
9293     { Bad_Opcode },
9294     { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
9295     { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
9296     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
9297     /* f8 */
9298     { Bad_Opcode },
9299     { Bad_Opcode },
9300     { Bad_Opcode },
9301     { Bad_Opcode },
9302     { Bad_Opcode },
9303     { Bad_Opcode },
9304     { Bad_Opcode },
9305     { Bad_Opcode },
9306   },
9307   /* VEX_0F3A */
9308   {
9309     /* 00 */
9310     { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
9311     { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
9312     { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
9313     { Bad_Opcode },
9314     { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
9315     { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
9316     { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
9317     { Bad_Opcode },
9318     /* 08 */
9319     { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
9320     { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
9321     { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
9322     { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
9323     { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
9324     { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
9325     { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
9326     { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
9327     /* 10 */
9328     { Bad_Opcode },
9329     { Bad_Opcode },
9330     { Bad_Opcode },
9331     { Bad_Opcode },
9332     { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
9333     { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
9334     { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
9335     { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
9336     /* 18 */
9337     { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
9338     { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
9339     { Bad_Opcode },
9340     { Bad_Opcode },
9341     { Bad_Opcode },
9342     { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
9343     { Bad_Opcode },
9344     { Bad_Opcode },
9345     /* 20 */
9346     { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
9347     { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
9348     { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
9349     { Bad_Opcode },
9350     { Bad_Opcode },
9351     { Bad_Opcode },
9352     { Bad_Opcode },
9353     { Bad_Opcode },
9354     /* 28 */
9355     { Bad_Opcode },
9356     { Bad_Opcode },
9357     { Bad_Opcode },
9358     { Bad_Opcode },
9359     { Bad_Opcode },
9360     { Bad_Opcode },
9361     { Bad_Opcode },
9362     { Bad_Opcode },
9363     /* 30 */
9364     { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
9365     { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
9366     { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
9367     { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
9368     { Bad_Opcode },
9369     { Bad_Opcode },
9370     { Bad_Opcode },
9371     { Bad_Opcode },
9372     /* 38 */
9373     { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
9374     { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
9375     { Bad_Opcode },
9376     { Bad_Opcode },
9377     { Bad_Opcode },
9378     { Bad_Opcode },
9379     { Bad_Opcode },
9380     { Bad_Opcode },
9381     /* 40 */
9382     { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
9383     { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
9384     { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
9385     { Bad_Opcode },
9386     { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
9387     { Bad_Opcode },
9388     { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
9389     { Bad_Opcode },
9390     /* 48 */
9391     { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
9392     { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
9393     { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
9394     { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
9395     { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
9396     { Bad_Opcode },
9397     { Bad_Opcode },
9398     { Bad_Opcode },
9399     /* 50 */
9400     { Bad_Opcode },
9401     { Bad_Opcode },
9402     { Bad_Opcode },
9403     { Bad_Opcode },
9404     { Bad_Opcode },
9405     { Bad_Opcode },
9406     { Bad_Opcode },
9407     { Bad_Opcode },
9408     /* 58 */
9409     { Bad_Opcode },
9410     { Bad_Opcode },
9411     { Bad_Opcode },
9412     { Bad_Opcode },
9413     { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9414     { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9415     { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9416     { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9417     /* 60 */
9418     { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9419     { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9420     { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9421     { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9422     { Bad_Opcode },
9423     { Bad_Opcode },
9424     { Bad_Opcode },
9425     { Bad_Opcode },
9426     /* 68 */
9427     { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9428     { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9429     { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9430     { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9431     { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9432     { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9433     { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9434     { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9435     /* 70 */
9436     { Bad_Opcode },
9437     { Bad_Opcode },
9438     { Bad_Opcode },
9439     { Bad_Opcode },
9440     { Bad_Opcode },
9441     { Bad_Opcode },
9442     { Bad_Opcode },
9443     { Bad_Opcode },
9444     /* 78 */
9445     { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9446     { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9447     { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9448     { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9449     { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9450     { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9451     { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9452     { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9453     /* 80 */
9454     { Bad_Opcode },
9455     { Bad_Opcode },
9456     { Bad_Opcode },
9457     { Bad_Opcode },
9458     { Bad_Opcode },
9459     { Bad_Opcode },
9460     { Bad_Opcode },
9461     { Bad_Opcode },
9462     /* 88 */
9463     { Bad_Opcode },
9464     { Bad_Opcode },
9465     { Bad_Opcode },
9466     { Bad_Opcode },
9467     { Bad_Opcode },
9468     { Bad_Opcode },
9469     { Bad_Opcode },
9470     { Bad_Opcode },
9471     /* 90 */
9472     { Bad_Opcode },
9473     { Bad_Opcode },
9474     { Bad_Opcode },
9475     { Bad_Opcode },
9476     { Bad_Opcode },
9477     { Bad_Opcode },
9478     { Bad_Opcode },
9479     { Bad_Opcode },
9480     /* 98 */
9481     { Bad_Opcode },
9482     { Bad_Opcode },
9483     { Bad_Opcode },
9484     { Bad_Opcode },
9485     { Bad_Opcode },
9486     { Bad_Opcode },
9487     { Bad_Opcode },
9488     { Bad_Opcode },
9489     /* a0 */
9490     { Bad_Opcode },
9491     { Bad_Opcode },
9492     { Bad_Opcode },
9493     { Bad_Opcode },
9494     { Bad_Opcode },
9495     { Bad_Opcode },
9496     { Bad_Opcode },
9497     { Bad_Opcode },
9498     /* a8 */
9499     { Bad_Opcode },
9500     { Bad_Opcode },
9501     { Bad_Opcode },
9502     { Bad_Opcode },
9503     { Bad_Opcode },
9504     { Bad_Opcode },
9505     { Bad_Opcode },
9506     { Bad_Opcode },
9507     /* b0 */
9508     { Bad_Opcode },
9509     { Bad_Opcode },
9510     { Bad_Opcode },
9511     { Bad_Opcode },
9512     { Bad_Opcode },
9513     { Bad_Opcode },
9514     { Bad_Opcode },
9515     { Bad_Opcode },
9516     /* b8 */
9517     { Bad_Opcode },
9518     { Bad_Opcode },
9519     { Bad_Opcode },
9520     { Bad_Opcode },
9521     { Bad_Opcode },
9522     { Bad_Opcode },
9523     { Bad_Opcode },
9524     { Bad_Opcode },
9525     /* c0 */
9526     { Bad_Opcode },
9527     { Bad_Opcode },
9528     { Bad_Opcode },
9529     { Bad_Opcode },
9530     { Bad_Opcode },
9531     { Bad_Opcode },
9532     { Bad_Opcode },
9533     { Bad_Opcode },
9534     /* c8 */
9535     { Bad_Opcode },
9536     { Bad_Opcode },
9537     { Bad_Opcode },
9538     { Bad_Opcode },
9539     { Bad_Opcode },
9540     { Bad_Opcode },
9541     { Bad_Opcode },
9542     { Bad_Opcode },
9543     /* d0 */
9544     { Bad_Opcode },
9545     { Bad_Opcode },
9546     { Bad_Opcode },
9547     { Bad_Opcode },
9548     { Bad_Opcode },
9549     { Bad_Opcode },
9550     { Bad_Opcode },
9551     { Bad_Opcode },
9552     /* d8 */
9553     { Bad_Opcode },
9554     { Bad_Opcode },
9555     { Bad_Opcode },
9556     { Bad_Opcode },
9557     { Bad_Opcode },
9558     { Bad_Opcode },
9559     { Bad_Opcode },
9560     { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9561     /* e0 */
9562     { Bad_Opcode },
9563     { Bad_Opcode },
9564     { Bad_Opcode },
9565     { Bad_Opcode },
9566     { Bad_Opcode },
9567     { Bad_Opcode },
9568     { Bad_Opcode },
9569     { Bad_Opcode },
9570     /* e8 */
9571     { Bad_Opcode },
9572     { Bad_Opcode },
9573     { Bad_Opcode },
9574     { Bad_Opcode },
9575     { Bad_Opcode },
9576     { Bad_Opcode },
9577     { Bad_Opcode },
9578     { Bad_Opcode },
9579     /* f0 */
9580     { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9581     { Bad_Opcode },
9582     { Bad_Opcode },
9583     { Bad_Opcode },
9584     { Bad_Opcode },
9585     { Bad_Opcode },
9586     { Bad_Opcode },
9587     { Bad_Opcode },
9588     /* f8 */
9589     { Bad_Opcode },
9590     { Bad_Opcode },
9591     { Bad_Opcode },
9592     { Bad_Opcode },
9593     { Bad_Opcode },
9594     { Bad_Opcode },
9595     { Bad_Opcode },
9596     { Bad_Opcode },
9597   },
9598 };
9599
9600 #define NEED_OPCODE_TABLE
9601 #include "i386-dis-evex.h"
9602 #undef NEED_OPCODE_TABLE
9603 static const struct dis386 vex_len_table[][2] = {
9604   /* VEX_LEN_0F10_P_1 */
9605   {
9606     { VEX_W_TABLE (VEX_W_0F10_P_1) },
9607     { VEX_W_TABLE (VEX_W_0F10_P_1) },
9608   },
9609
9610   /* VEX_LEN_0F10_P_3 */
9611   {
9612     { VEX_W_TABLE (VEX_W_0F10_P_3) },
9613     { VEX_W_TABLE (VEX_W_0F10_P_3) },
9614   },
9615
9616   /* VEX_LEN_0F11_P_1 */
9617   {
9618     { VEX_W_TABLE (VEX_W_0F11_P_1) },
9619     { VEX_W_TABLE (VEX_W_0F11_P_1) },
9620   },
9621
9622   /* VEX_LEN_0F11_P_3 */
9623   {
9624     { VEX_W_TABLE (VEX_W_0F11_P_3) },
9625     { VEX_W_TABLE (VEX_W_0F11_P_3) },
9626   },
9627
9628   /* VEX_LEN_0F12_P_0_M_0 */
9629   {
9630     { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) },
9631   },
9632
9633   /* VEX_LEN_0F12_P_0_M_1 */
9634   {
9635     { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) },
9636   },
9637
9638   /* VEX_LEN_0F12_P_2 */
9639   {
9640     { VEX_W_TABLE (VEX_W_0F12_P_2) },
9641   },
9642
9643   /* VEX_LEN_0F13_M_0 */
9644   {
9645     { VEX_W_TABLE (VEX_W_0F13_M_0) },
9646   },
9647
9648   /* VEX_LEN_0F16_P_0_M_0 */
9649   {
9650     { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) },
9651   },
9652
9653   /* VEX_LEN_0F16_P_0_M_1 */
9654   {
9655     { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) },
9656   },
9657
9658   /* VEX_LEN_0F16_P_2 */
9659   {
9660     { VEX_W_TABLE (VEX_W_0F16_P_2) },
9661   },
9662
9663   /* VEX_LEN_0F17_M_0 */
9664   {
9665     { VEX_W_TABLE (VEX_W_0F17_M_0) },
9666   },
9667
9668   /* VEX_LEN_0F2A_P_1 */
9669   {
9670     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9671     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9672   },
9673
9674   /* VEX_LEN_0F2A_P_3 */
9675   {
9676     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9677     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9678   },
9679
9680   /* VEX_LEN_0F2C_P_1 */
9681   {
9682     { "vcvttss2siY",    { Gv, EXdScalar }, 0 },
9683     { "vcvttss2siY",    { Gv, EXdScalar }, 0 },
9684   },
9685
9686   /* VEX_LEN_0F2C_P_3 */
9687   {
9688     { "vcvttsd2siY",    { Gv, EXqScalar }, 0 },
9689     { "vcvttsd2siY",    { Gv, EXqScalar }, 0 },
9690   },
9691
9692   /* VEX_LEN_0F2D_P_1 */
9693   {
9694     { "vcvtss2siY",     { Gv, EXdScalar }, 0 },
9695     { "vcvtss2siY",     { Gv, EXdScalar }, 0 },
9696   },
9697
9698   /* VEX_LEN_0F2D_P_3 */
9699   {
9700     { "vcvtsd2siY",     { Gv, EXqScalar }, 0 },
9701     { "vcvtsd2siY",     { Gv, EXqScalar }, 0 },
9702   },
9703
9704   /* VEX_LEN_0F2E_P_0 */
9705   {
9706     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9707     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9708   },
9709
9710   /* VEX_LEN_0F2E_P_2 */
9711   {
9712     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9713     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9714   },
9715
9716   /* VEX_LEN_0F2F_P_0 */
9717   {
9718     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9719     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9720   },
9721
9722   /* VEX_LEN_0F2F_P_2 */
9723   {
9724     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9725     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9726   },
9727
9728   /* VEX_LEN_0F41_P_0 */
9729   {
9730     { Bad_Opcode },
9731     { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9732   },
9733   /* VEX_LEN_0F41_P_2 */
9734   {
9735     { Bad_Opcode },
9736     { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9737   },
9738   /* VEX_LEN_0F42_P_0 */
9739   {
9740     { Bad_Opcode },
9741     { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9742   },
9743   /* VEX_LEN_0F42_P_2 */
9744   {
9745     { Bad_Opcode },
9746     { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9747   },
9748   /* VEX_LEN_0F44_P_0 */
9749   {
9750     { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9751   },
9752   /* VEX_LEN_0F44_P_2 */
9753   {
9754     { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9755   },
9756   /* VEX_LEN_0F45_P_0 */
9757   {
9758     { Bad_Opcode },
9759     { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9760   },
9761   /* VEX_LEN_0F45_P_2 */
9762   {
9763     { Bad_Opcode },
9764     { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9765   },
9766   /* VEX_LEN_0F46_P_0 */
9767   {
9768     { Bad_Opcode },
9769     { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9770   },
9771   /* VEX_LEN_0F46_P_2 */
9772   {
9773     { Bad_Opcode },
9774     { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9775   },
9776   /* VEX_LEN_0F47_P_0 */
9777   {
9778     { Bad_Opcode },
9779     { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9780   },
9781   /* VEX_LEN_0F47_P_2 */
9782   {
9783     { Bad_Opcode },
9784     { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9785   },
9786   /* VEX_LEN_0F4A_P_0 */
9787   {
9788     { Bad_Opcode },
9789     { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9790   },
9791   /* VEX_LEN_0F4A_P_2 */
9792   {
9793     { Bad_Opcode },
9794     { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9795   },
9796   /* VEX_LEN_0F4B_P_0 */
9797   {
9798     { Bad_Opcode },
9799     { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9800   },
9801   /* VEX_LEN_0F4B_P_2 */
9802   {
9803     { Bad_Opcode },
9804     { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9805   },
9806
9807   /* VEX_LEN_0F51_P_1 */
9808   {
9809     { VEX_W_TABLE (VEX_W_0F51_P_1) },
9810     { VEX_W_TABLE (VEX_W_0F51_P_1) },
9811   },
9812
9813   /* VEX_LEN_0F51_P_3 */
9814   {
9815     { VEX_W_TABLE (VEX_W_0F51_P_3) },
9816     { VEX_W_TABLE (VEX_W_0F51_P_3) },
9817   },
9818
9819   /* VEX_LEN_0F52_P_1 */
9820   {
9821     { VEX_W_TABLE (VEX_W_0F52_P_1) },
9822     { VEX_W_TABLE (VEX_W_0F52_P_1) },
9823   },
9824
9825   /* VEX_LEN_0F53_P_1 */
9826   {
9827     { VEX_W_TABLE (VEX_W_0F53_P_1) },
9828     { VEX_W_TABLE (VEX_W_0F53_P_1) },
9829   },
9830
9831   /* VEX_LEN_0F58_P_1 */
9832   {
9833     { VEX_W_TABLE (VEX_W_0F58_P_1) },
9834     { VEX_W_TABLE (VEX_W_0F58_P_1) },
9835   },
9836
9837   /* VEX_LEN_0F58_P_3 */
9838   {
9839     { VEX_W_TABLE (VEX_W_0F58_P_3) },
9840     { VEX_W_TABLE (VEX_W_0F58_P_3) },
9841   },
9842
9843   /* VEX_LEN_0F59_P_1 */
9844   {
9845     { VEX_W_TABLE (VEX_W_0F59_P_1) },
9846     { VEX_W_TABLE (VEX_W_0F59_P_1) },
9847   },
9848
9849   /* VEX_LEN_0F59_P_3 */
9850   {
9851     { VEX_W_TABLE (VEX_W_0F59_P_3) },
9852     { VEX_W_TABLE (VEX_W_0F59_P_3) },
9853   },
9854
9855   /* VEX_LEN_0F5A_P_1 */
9856   {
9857     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9858     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9859   },
9860
9861   /* VEX_LEN_0F5A_P_3 */
9862   {
9863     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9864     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9865   },
9866
9867   /* VEX_LEN_0F5C_P_1 */
9868   {
9869     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9870     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9871   },
9872
9873   /* VEX_LEN_0F5C_P_3 */
9874   {
9875     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9876     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9877   },
9878
9879   /* VEX_LEN_0F5D_P_1 */
9880   {
9881     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9882     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9883   },
9884
9885   /* VEX_LEN_0F5D_P_3 */
9886   {
9887     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9888     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9889   },
9890
9891   /* VEX_LEN_0F5E_P_1 */
9892   {
9893     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9894     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9895   },
9896
9897   /* VEX_LEN_0F5E_P_3 */
9898   {
9899     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9900     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9901   },
9902
9903   /* VEX_LEN_0F5F_P_1 */
9904   {
9905     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9906     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9907   },
9908
9909   /* VEX_LEN_0F5F_P_3 */
9910   {
9911     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9912     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9913   },
9914
9915   /* VEX_LEN_0F6E_P_2 */
9916   {
9917     { "vmovK",          { XMScalar, Edq }, 0 },
9918     { "vmovK",          { XMScalar, Edq }, 0 },
9919   },
9920
9921   /* VEX_LEN_0F7E_P_1 */
9922   {
9923     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9924     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9925   },
9926
9927   /* VEX_LEN_0F7E_P_2 */
9928   {
9929     { "vmovK",          { Edq, XMScalar }, 0 },
9930     { "vmovK",          { Edq, XMScalar }, 0 },
9931   },
9932
9933   /* VEX_LEN_0F90_P_0 */
9934   {
9935     { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9936   },
9937
9938   /* VEX_LEN_0F90_P_2 */
9939   {
9940     { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9941   },
9942
9943   /* VEX_LEN_0F91_P_0 */
9944   {
9945     { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9946   },
9947
9948   /* VEX_LEN_0F91_P_2 */
9949   {
9950     { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
9951   },
9952
9953   /* VEX_LEN_0F92_P_0 */
9954   {
9955     { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9956   },
9957
9958   /* VEX_LEN_0F92_P_2 */
9959   {
9960     { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
9961   },
9962
9963   /* VEX_LEN_0F92_P_3 */
9964   {
9965     { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0) },
9966   },
9967
9968   /* VEX_LEN_0F93_P_0 */
9969   {
9970     { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9971   },
9972
9973   /* VEX_LEN_0F93_P_2 */
9974   {
9975     { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
9976   },
9977
9978   /* VEX_LEN_0F93_P_3 */
9979   {
9980     { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0) },
9981   },
9982
9983   /* VEX_LEN_0F98_P_0 */
9984   {
9985     { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9986   },
9987
9988   /* VEX_LEN_0F98_P_2 */
9989   {
9990     { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
9991   },
9992
9993   /* VEX_LEN_0F99_P_0 */
9994   {
9995     { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
9996   },
9997
9998   /* VEX_LEN_0F99_P_2 */
9999   {
10000     { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
10001   },
10002
10003   /* VEX_LEN_0FAE_R_2_M_0 */
10004   {
10005     { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) },
10006   },
10007
10008   /* VEX_LEN_0FAE_R_3_M_0 */
10009   {
10010     { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) },
10011   },
10012
10013   /* VEX_LEN_0FC2_P_1 */
10014   {
10015     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
10016     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
10017   },
10018
10019   /* VEX_LEN_0FC2_P_3 */
10020   {
10021     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
10022     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
10023   },
10024
10025   /* VEX_LEN_0FC4_P_2 */
10026   {
10027     { VEX_W_TABLE (VEX_W_0FC4_P_2) },
10028   },
10029
10030   /* VEX_LEN_0FC5_P_2 */
10031   {
10032     { VEX_W_TABLE (VEX_W_0FC5_P_2) },
10033   },
10034
10035   /* VEX_LEN_0FD6_P_2 */
10036   {
10037     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
10038     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
10039   },
10040
10041   /* VEX_LEN_0FF7_P_2 */
10042   {
10043     { VEX_W_TABLE (VEX_W_0FF7_P_2) },
10044   },
10045
10046   /* VEX_LEN_0F3816_P_2 */
10047   {
10048     { Bad_Opcode },
10049     { VEX_W_TABLE (VEX_W_0F3816_P_2) },
10050   },
10051
10052   /* VEX_LEN_0F3819_P_2 */
10053   {
10054     { Bad_Opcode },
10055     { VEX_W_TABLE (VEX_W_0F3819_P_2) },
10056   },
10057
10058   /* VEX_LEN_0F381A_P_2_M_0 */
10059   {
10060     { Bad_Opcode },
10061     { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
10062   },
10063
10064   /* VEX_LEN_0F3836_P_2 */
10065   {
10066     { Bad_Opcode },
10067     { VEX_W_TABLE (VEX_W_0F3836_P_2) },
10068   },
10069
10070   /* VEX_LEN_0F3841_P_2 */
10071   {
10072     { VEX_W_TABLE (VEX_W_0F3841_P_2) },
10073   },
10074
10075   /* VEX_LEN_0F385A_P_2_M_0 */
10076   {
10077     { Bad_Opcode },
10078     { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
10079   },
10080
10081   /* VEX_LEN_0F38DB_P_2 */
10082   {
10083     { VEX_W_TABLE (VEX_W_0F38DB_P_2) },
10084   },
10085
10086   /* VEX_LEN_0F38DC_P_2 */
10087   {
10088     { VEX_W_TABLE (VEX_W_0F38DC_P_2) },
10089   },
10090
10091   /* VEX_LEN_0F38DD_P_2 */
10092   {
10093     { VEX_W_TABLE (VEX_W_0F38DD_P_2) },
10094   },
10095
10096   /* VEX_LEN_0F38DE_P_2 */
10097   {
10098     { VEX_W_TABLE (VEX_W_0F38DE_P_2) },
10099   },
10100
10101   /* VEX_LEN_0F38DF_P_2 */
10102   {
10103     { VEX_W_TABLE (VEX_W_0F38DF_P_2) },
10104   },
10105
10106   /* VEX_LEN_0F38F2_P_0 */
10107   {
10108     { "andnS",          { Gdq, VexGdq, Edq }, 0 },
10109   },
10110
10111   /* VEX_LEN_0F38F3_R_1_P_0 */
10112   {
10113     { "blsrS",          { VexGdq, Edq }, 0 },
10114   },
10115
10116   /* VEX_LEN_0F38F3_R_2_P_0 */
10117   {
10118     { "blsmskS",        { VexGdq, Edq }, 0 },
10119   },
10120
10121   /* VEX_LEN_0F38F3_R_3_P_0 */
10122   {
10123     { "blsiS",          { VexGdq, Edq }, 0 },
10124   },
10125
10126   /* VEX_LEN_0F38F5_P_0 */
10127   {
10128     { "bzhiS",          { Gdq, Edq, VexGdq }, 0 },
10129   },
10130
10131   /* VEX_LEN_0F38F5_P_1 */
10132   {
10133     { "pextS",          { Gdq, VexGdq, Edq }, 0 },
10134   },
10135
10136   /* VEX_LEN_0F38F5_P_3 */
10137   {
10138     { "pdepS",          { Gdq, VexGdq, Edq }, 0 },
10139   },
10140
10141   /* VEX_LEN_0F38F6_P_3 */
10142   {
10143     { "mulxS",          { Gdq, VexGdq, Edq }, 0 },
10144   },
10145
10146   /* VEX_LEN_0F38F7_P_0 */
10147   {
10148     { "bextrS",         { Gdq, Edq, VexGdq }, 0 },
10149   },
10150
10151   /* VEX_LEN_0F38F7_P_1 */
10152   {
10153     { "sarxS",          { Gdq, Edq, VexGdq }, 0 },
10154   },
10155
10156   /* VEX_LEN_0F38F7_P_2 */
10157   {
10158     { "shlxS",          { Gdq, Edq, VexGdq }, 0 },
10159   },
10160
10161   /* VEX_LEN_0F38F7_P_3 */
10162   {
10163     { "shrxS",          { Gdq, Edq, VexGdq }, 0 },
10164   },
10165
10166   /* VEX_LEN_0F3A00_P_2 */
10167   {
10168     { Bad_Opcode },
10169     { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
10170   },
10171
10172   /* VEX_LEN_0F3A01_P_2 */
10173   {
10174     { Bad_Opcode },
10175     { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
10176   },
10177
10178   /* VEX_LEN_0F3A06_P_2 */
10179   {
10180     { Bad_Opcode },
10181     { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
10182   },
10183
10184   /* VEX_LEN_0F3A0A_P_2 */
10185   {
10186     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
10187     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
10188   },
10189
10190   /* VEX_LEN_0F3A0B_P_2 */
10191   {
10192     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
10193     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
10194   },
10195
10196   /* VEX_LEN_0F3A14_P_2 */
10197   {
10198     { VEX_W_TABLE (VEX_W_0F3A14_P_2) },
10199   },
10200
10201   /* VEX_LEN_0F3A15_P_2 */
10202   {
10203     { VEX_W_TABLE (VEX_W_0F3A15_P_2) },
10204   },
10205
10206   /* VEX_LEN_0F3A16_P_2  */
10207   {
10208     { "vpextrK",        { Edq, XM, Ib }, 0 },
10209   },
10210
10211   /* VEX_LEN_0F3A17_P_2 */
10212   {
10213     { "vextractps",     { Edqd, XM, Ib }, 0 },
10214   },
10215
10216   /* VEX_LEN_0F3A18_P_2 */
10217   {
10218     { Bad_Opcode },
10219     { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
10220   },
10221
10222   /* VEX_LEN_0F3A19_P_2 */
10223   {
10224     { Bad_Opcode },
10225     { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
10226   },
10227
10228   /* VEX_LEN_0F3A20_P_2 */
10229   {
10230     { VEX_W_TABLE (VEX_W_0F3A20_P_2) },
10231   },
10232
10233   /* VEX_LEN_0F3A21_P_2 */
10234   {
10235     { VEX_W_TABLE (VEX_W_0F3A21_P_2) },
10236   },
10237
10238   /* VEX_LEN_0F3A22_P_2 */
10239   {
10240     { "vpinsrK",        { XM, Vex128, Edq, Ib }, 0 },
10241   },
10242
10243   /* VEX_LEN_0F3A30_P_2 */
10244   {
10245     { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
10246   },
10247
10248   /* VEX_LEN_0F3A31_P_2 */
10249   {
10250     { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
10251   },
10252
10253   /* VEX_LEN_0F3A32_P_2 */
10254   {
10255     { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
10256   },
10257
10258   /* VEX_LEN_0F3A33_P_2 */
10259   {
10260     { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
10261   },
10262
10263   /* VEX_LEN_0F3A38_P_2 */
10264   {
10265     { Bad_Opcode },
10266     { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
10267   },
10268
10269   /* VEX_LEN_0F3A39_P_2 */
10270   {
10271     { Bad_Opcode },
10272     { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
10273   },
10274
10275   /* VEX_LEN_0F3A41_P_2 */
10276   {
10277     { VEX_W_TABLE (VEX_W_0F3A41_P_2) },
10278   },
10279
10280   /* VEX_LEN_0F3A44_P_2 */
10281   {
10282     { VEX_W_TABLE (VEX_W_0F3A44_P_2) },
10283   },
10284
10285   /* VEX_LEN_0F3A46_P_2 */
10286   {
10287     { Bad_Opcode },
10288     { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
10289   },
10290
10291   /* VEX_LEN_0F3A60_P_2 */
10292   {
10293     { VEX_W_TABLE (VEX_W_0F3A60_P_2) },
10294   },
10295
10296   /* VEX_LEN_0F3A61_P_2 */
10297   {
10298     { VEX_W_TABLE (VEX_W_0F3A61_P_2) },
10299   },
10300
10301   /* VEX_LEN_0F3A62_P_2 */
10302   {
10303     { VEX_W_TABLE (VEX_W_0F3A62_P_2) },
10304   },
10305
10306   /* VEX_LEN_0F3A63_P_2 */
10307   {
10308     { VEX_W_TABLE (VEX_W_0F3A63_P_2) },
10309   },
10310
10311   /* VEX_LEN_0F3A6A_P_2 */
10312   {
10313     { "vfmaddss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10314   },
10315
10316   /* VEX_LEN_0F3A6B_P_2 */
10317   {
10318     { "vfmaddsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10319   },
10320
10321   /* VEX_LEN_0F3A6E_P_2 */
10322   {
10323     { "vfmsubss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10324   },
10325
10326   /* VEX_LEN_0F3A6F_P_2 */
10327   {
10328     { "vfmsubsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10329   },
10330
10331   /* VEX_LEN_0F3A7A_P_2 */
10332   {
10333     { "vfnmaddss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10334   },
10335
10336   /* VEX_LEN_0F3A7B_P_2 */
10337   {
10338     { "vfnmaddsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10339   },
10340
10341   /* VEX_LEN_0F3A7E_P_2 */
10342   {
10343     { "vfnmsubss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10344   },
10345
10346   /* VEX_LEN_0F3A7F_P_2 */
10347   {
10348     { "vfnmsubsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10349   },
10350
10351   /* VEX_LEN_0F3ADF_P_2 */
10352   {
10353     { VEX_W_TABLE (VEX_W_0F3ADF_P_2) },
10354   },
10355
10356   /* VEX_LEN_0F3AF0_P_3 */
10357   {
10358     { "rorxS",          { Gdq, Edq, Ib }, 0 },
10359   },
10360
10361   /* VEX_LEN_0FXOP_08_CC */
10362   {
10363      { "vpcomb",        { XM, Vex128, EXx, Ib }, 0 },
10364   },
10365
10366   /* VEX_LEN_0FXOP_08_CD */
10367   {
10368      { "vpcomw",        { XM, Vex128, EXx, Ib }, 0 },
10369   },
10370
10371   /* VEX_LEN_0FXOP_08_CE */
10372   {
10373      { "vpcomd",        { XM, Vex128, EXx, Ib }, 0 },
10374   },
10375
10376   /* VEX_LEN_0FXOP_08_CF */
10377   {
10378      { "vpcomq",        { XM, Vex128, EXx, Ib }, 0 },
10379   },
10380
10381   /* VEX_LEN_0FXOP_08_EC */
10382   {
10383      { "vpcomub",       { XM, Vex128, EXx, Ib }, 0 },
10384   },
10385
10386   /* VEX_LEN_0FXOP_08_ED */
10387   {
10388      { "vpcomuw",       { XM, Vex128, EXx, Ib }, 0 },
10389   },
10390
10391   /* VEX_LEN_0FXOP_08_EE */
10392   {
10393      { "vpcomud",       { XM, Vex128, EXx, Ib }, 0 },
10394   },
10395
10396   /* VEX_LEN_0FXOP_08_EF */
10397   {
10398      { "vpcomuq",       { XM, Vex128, EXx, Ib }, 0 },
10399   },
10400
10401   /* VEX_LEN_0FXOP_09_80 */
10402   {
10403     { "vfrczps",        { XM, EXxmm }, 0 },
10404     { "vfrczps",        { XM, EXymmq }, 0 },
10405   },
10406
10407   /* VEX_LEN_0FXOP_09_81 */
10408   {
10409     { "vfrczpd",        { XM, EXxmm }, 0 },
10410     { "vfrczpd",        { XM, EXymmq }, 0 },
10411   },
10412 };
10413
10414 static const struct dis386 vex_w_table[][2] = {
10415   {
10416     /* VEX_W_0F10_P_0 */
10417     { "vmovups",        { XM, EXx }, 0 },
10418   },
10419   {
10420     /* VEX_W_0F10_P_1 */
10421     { "vmovss",         { XMVexScalar, VexScalar, EXdScalar }, 0 },
10422   },
10423   {
10424     /* VEX_W_0F10_P_2 */
10425     { "vmovupd",        { XM, EXx }, 0 },
10426   },
10427   {
10428     /* VEX_W_0F10_P_3 */
10429     { "vmovsd",         { XMVexScalar, VexScalar, EXqScalar }, 0 },
10430   },
10431   {
10432     /* VEX_W_0F11_P_0 */
10433     { "vmovups",        { EXxS, XM }, 0 },
10434   },
10435   {
10436     /* VEX_W_0F11_P_1 */
10437     { "vmovss",         { EXdVexScalarS, VexScalar, XMScalar }, 0 },
10438   },
10439   {
10440     /* VEX_W_0F11_P_2 */
10441     { "vmovupd",        { EXxS, XM }, 0 },
10442   },
10443   {
10444     /* VEX_W_0F11_P_3 */
10445     { "vmovsd",         { EXqVexScalarS, VexScalar, XMScalar }, 0 },
10446   },
10447   {
10448     /* VEX_W_0F12_P_0_M_0 */
10449     { "vmovlps",        { XM, Vex128, EXq }, 0 },
10450   },
10451   {
10452     /* VEX_W_0F12_P_0_M_1 */
10453     { "vmovhlps",       { XM, Vex128, EXq }, 0 },
10454   },
10455   {
10456     /* VEX_W_0F12_P_1 */
10457     { "vmovsldup",      { XM, EXx }, 0 },
10458   },
10459   {
10460     /* VEX_W_0F12_P_2 */
10461     { "vmovlpd",        { XM, Vex128, EXq }, 0 },
10462   },
10463   {
10464     /* VEX_W_0F12_P_3 */
10465     { "vmovddup",       { XM, EXymmq }, 0 },
10466   },
10467   {
10468     /* VEX_W_0F13_M_0 */
10469     { "vmovlpX",        { EXq, XM }, 0 },
10470   },
10471   {
10472     /* VEX_W_0F14 */
10473     { "vunpcklpX",      { XM, Vex, EXx }, 0 },
10474   },
10475   {
10476     /* VEX_W_0F15 */
10477     { "vunpckhpX",      { XM, Vex, EXx }, 0 },
10478   },
10479   {
10480     /* VEX_W_0F16_P_0_M_0 */
10481     { "vmovhps",        { XM, Vex128, EXq }, 0 },
10482   },
10483   {
10484     /* VEX_W_0F16_P_0_M_1 */
10485     { "vmovlhps",       { XM, Vex128, EXq }, 0 },
10486   },
10487   {
10488     /* VEX_W_0F16_P_1 */
10489     { "vmovshdup",      { XM, EXx }, 0 },
10490   },
10491   {
10492     /* VEX_W_0F16_P_2 */
10493     { "vmovhpd",        { XM, Vex128, EXq }, 0 },
10494   },
10495   {
10496     /* VEX_W_0F17_M_0 */
10497     { "vmovhpX",        { EXq, XM }, 0 },
10498   },
10499   {
10500     /* VEX_W_0F28 */
10501     { "vmovapX",        { XM, EXx }, 0 },
10502   },
10503   {
10504     /* VEX_W_0F29 */
10505     { "vmovapX",        { EXxS, XM }, 0 },
10506   },
10507   {
10508     /* VEX_W_0F2B_M_0 */
10509     { "vmovntpX",       { Mx, XM }, 0 },
10510   },
10511   {
10512     /* VEX_W_0F2E_P_0 */
10513     { "vucomiss",       { XMScalar, EXdScalar }, 0 },
10514   },
10515   {
10516     /* VEX_W_0F2E_P_2 */
10517     { "vucomisd",       { XMScalar, EXqScalar }, 0 },
10518   },
10519   {
10520     /* VEX_W_0F2F_P_0 */
10521     { "vcomiss",        { XMScalar, EXdScalar }, 0 },
10522   },
10523   {
10524     /* VEX_W_0F2F_P_2 */
10525     { "vcomisd",        { XMScalar, EXqScalar }, 0 },
10526   },
10527   {
10528     /* VEX_W_0F41_P_0_LEN_1 */
10529     { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
10530     { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) },
10531   },
10532   {
10533     /* VEX_W_0F41_P_2_LEN_1 */
10534     { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) },
10535     { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) }
10536   },
10537   {
10538     /* VEX_W_0F42_P_0_LEN_1 */
10539     { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) },
10540     { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) },
10541   },
10542   {
10543     /* VEX_W_0F42_P_2_LEN_1 */
10544     { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) },
10545     { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) },
10546   },
10547   {
10548     /* VEX_W_0F44_P_0_LEN_0 */
10549     { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) },
10550     { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) },
10551   },
10552   {
10553     /* VEX_W_0F44_P_2_LEN_0 */
10554     { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) },
10555     { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) },
10556   },
10557   {
10558     /* VEX_W_0F45_P_0_LEN_1 */
10559     { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) },
10560     { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) },
10561   },
10562   {
10563     /* VEX_W_0F45_P_2_LEN_1 */
10564     { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) },
10565     { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) },
10566   },
10567   {
10568     /* VEX_W_0F46_P_0_LEN_1 */
10569     { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) },
10570     { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) },
10571   },
10572   {
10573     /* VEX_W_0F46_P_2_LEN_1 */
10574     { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) },
10575     { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) },
10576   },
10577   {
10578     /* VEX_W_0F47_P_0_LEN_1 */
10579     { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) },
10580     { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) },
10581   },
10582   {
10583     /* VEX_W_0F47_P_2_LEN_1 */
10584     { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) },
10585     { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) },
10586   },
10587   {
10588     /* VEX_W_0F4A_P_0_LEN_1 */
10589     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) },
10590     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) },
10591   },
10592   {
10593     /* VEX_W_0F4A_P_2_LEN_1 */
10594     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) },
10595     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) },
10596   },
10597   {
10598     /* VEX_W_0F4B_P_0_LEN_1 */
10599     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) },
10600     { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) },
10601   },
10602   {
10603     /* VEX_W_0F4B_P_2_LEN_1 */
10604     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
10605   },
10606   {
10607     /* VEX_W_0F50_M_0 */
10608     { "vmovmskpX",      { Gdq, XS }, 0 },
10609   },
10610   {
10611     /* VEX_W_0F51_P_0 */
10612     { "vsqrtps",        { XM, EXx }, 0 },
10613   },
10614   {
10615     /* VEX_W_0F51_P_1 */
10616     { "vsqrtss",        { XMScalar, VexScalar, EXdScalar }, 0 },
10617   },
10618   {
10619     /* VEX_W_0F51_P_2  */
10620     { "vsqrtpd",        { XM, EXx }, 0 },
10621   },
10622   {
10623     /* VEX_W_0F51_P_3 */
10624     { "vsqrtsd",        { XMScalar, VexScalar, EXqScalar }, 0 },
10625   },
10626   {
10627     /* VEX_W_0F52_P_0 */
10628     { "vrsqrtps",       { XM, EXx }, 0 },
10629   },
10630   {
10631     /* VEX_W_0F52_P_1 */
10632     { "vrsqrtss",       { XMScalar, VexScalar, EXdScalar }, 0 },
10633   },
10634   {
10635     /* VEX_W_0F53_P_0  */
10636     { "vrcpps",         { XM, EXx }, 0 },
10637   },
10638   {
10639     /* VEX_W_0F53_P_1  */
10640     { "vrcpss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10641   },
10642   {
10643     /* VEX_W_0F58_P_0  */
10644     { "vaddps",         { XM, Vex, EXx }, 0 },
10645   },
10646   {
10647     /* VEX_W_0F58_P_1  */
10648     { "vaddss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10649   },
10650   {
10651     /* VEX_W_0F58_P_2  */
10652     { "vaddpd",         { XM, Vex, EXx }, 0 },
10653   },
10654   {
10655     /* VEX_W_0F58_P_3  */
10656     { "vaddsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10657   },
10658   {
10659     /* VEX_W_0F59_P_0  */
10660     { "vmulps",         { XM, Vex, EXx }, 0 },
10661   },
10662   {
10663     /* VEX_W_0F59_P_1  */
10664     { "vmulss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10665   },
10666   {
10667     /* VEX_W_0F59_P_2  */
10668     { "vmulpd",         { XM, Vex, EXx }, 0 },
10669   },
10670   {
10671     /* VEX_W_0F59_P_3  */
10672     { "vmulsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10673   },
10674   {
10675     /* VEX_W_0F5A_P_0  */
10676     { "vcvtps2pd",      { XM, EXxmmq }, 0 },
10677   },
10678   {
10679     /* VEX_W_0F5A_P_1  */
10680     { "vcvtss2sd",      { XMScalar, VexScalar, EXdScalar }, 0 },
10681   },
10682   {
10683     /* VEX_W_0F5A_P_3  */
10684     { "vcvtsd2ss",      { XMScalar, VexScalar, EXqScalar }, 0 },
10685   },
10686   {
10687     /* VEX_W_0F5B_P_0  */
10688     { "vcvtdq2ps",      { XM, EXx }, 0 },
10689   },
10690   {
10691     /* VEX_W_0F5B_P_1  */
10692     { "vcvttps2dq",     { XM, EXx }, 0 },
10693   },
10694   {
10695     /* VEX_W_0F5B_P_2  */
10696     { "vcvtps2dq",      { XM, EXx }, 0 },
10697   },
10698   {
10699     /* VEX_W_0F5C_P_0  */
10700     { "vsubps",         { XM, Vex, EXx }, 0 },
10701   },
10702   {
10703     /* VEX_W_0F5C_P_1  */
10704     { "vsubss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10705   },
10706   {
10707     /* VEX_W_0F5C_P_2  */
10708     { "vsubpd",         { XM, Vex, EXx }, 0 },
10709   },
10710   {
10711     /* VEX_W_0F5C_P_3  */
10712     { "vsubsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10713   },
10714   {
10715     /* VEX_W_0F5D_P_0  */
10716     { "vminps",         { XM, Vex, EXx }, 0 },
10717   },
10718   {
10719     /* VEX_W_0F5D_P_1  */
10720     { "vminss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10721   },
10722   {
10723     /* VEX_W_0F5D_P_2  */
10724     { "vminpd",         { XM, Vex, EXx }, 0 },
10725   },
10726   {
10727     /* VEX_W_0F5D_P_3  */
10728     { "vminsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10729   },
10730   {
10731     /* VEX_W_0F5E_P_0  */
10732     { "vdivps",         { XM, Vex, EXx }, 0 },
10733   },
10734   {
10735     /* VEX_W_0F5E_P_1  */
10736     { "vdivss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10737   },
10738   {
10739     /* VEX_W_0F5E_P_2  */
10740     { "vdivpd",         { XM, Vex, EXx }, 0 },
10741   },
10742   {
10743     /* VEX_W_0F5E_P_3  */
10744     { "vdivsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10745   },
10746   {
10747     /* VEX_W_0F5F_P_0  */
10748     { "vmaxps",         { XM, Vex, EXx }, 0 },
10749   },
10750   {
10751     /* VEX_W_0F5F_P_1  */
10752     { "vmaxss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10753   },
10754   {
10755     /* VEX_W_0F5F_P_2  */
10756     { "vmaxpd",         { XM, Vex, EXx }, 0 },
10757   },
10758   {
10759     /* VEX_W_0F5F_P_3  */
10760     { "vmaxsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10761   },
10762   {
10763     /* VEX_W_0F60_P_2  */
10764     { "vpunpcklbw",     { XM, Vex, EXx }, 0 },
10765   },
10766   {
10767     /* VEX_W_0F61_P_2  */
10768     { "vpunpcklwd",     { XM, Vex, EXx }, 0 },
10769   },
10770   {
10771     /* VEX_W_0F62_P_2  */
10772     { "vpunpckldq",     { XM, Vex, EXx }, 0 },
10773   },
10774   {
10775     /* VEX_W_0F63_P_2  */
10776     { "vpacksswb",      { XM, Vex, EXx }, 0 },
10777   },
10778   {
10779     /* VEX_W_0F64_P_2  */
10780     { "vpcmpgtb",       { XM, Vex, EXx }, 0 },
10781   },
10782   {
10783     /* VEX_W_0F65_P_2  */
10784     { "vpcmpgtw",       { XM, Vex, EXx }, 0 },
10785   },
10786   {
10787     /* VEX_W_0F66_P_2  */
10788     { "vpcmpgtd",       { XM, Vex, EXx }, 0 },
10789   },
10790   {
10791     /* VEX_W_0F67_P_2  */
10792     { "vpackuswb",      { XM, Vex, EXx }, 0 },
10793   },
10794   {
10795     /* VEX_W_0F68_P_2  */
10796     { "vpunpckhbw",     { XM, Vex, EXx }, 0 },
10797   },
10798   {
10799     /* VEX_W_0F69_P_2  */
10800     { "vpunpckhwd",     { XM, Vex, EXx }, 0 },
10801   },
10802   {
10803     /* VEX_W_0F6A_P_2  */
10804     { "vpunpckhdq",     { XM, Vex, EXx }, 0 },
10805   },
10806   {
10807     /* VEX_W_0F6B_P_2  */
10808     { "vpackssdw",      { XM, Vex, EXx }, 0 },
10809   },
10810   {
10811     /* VEX_W_0F6C_P_2  */
10812     { "vpunpcklqdq",    { XM, Vex, EXx }, 0 },
10813   },
10814   {
10815     /* VEX_W_0F6D_P_2  */
10816     { "vpunpckhqdq",    { XM, Vex, EXx }, 0 },
10817   },
10818   {
10819     /* VEX_W_0F6F_P_1  */
10820     { "vmovdqu",        { XM, EXx }, 0 },
10821   },
10822   {
10823     /* VEX_W_0F6F_P_2  */
10824     { "vmovdqa",        { XM, EXx }, 0 },
10825   },
10826   {
10827     /* VEX_W_0F70_P_1 */
10828     { "vpshufhw",       { XM, EXx, Ib }, 0 },
10829   },
10830   {
10831     /* VEX_W_0F70_P_2 */
10832     { "vpshufd",        { XM, EXx, Ib }, 0 },
10833   },
10834   {
10835     /* VEX_W_0F70_P_3 */
10836     { "vpshuflw",       { XM, EXx, Ib }, 0 },
10837   },
10838   {
10839     /* VEX_W_0F71_R_2_P_2  */
10840     { "vpsrlw",         { Vex, XS, Ib }, 0 },
10841   },
10842   {
10843     /* VEX_W_0F71_R_4_P_2  */
10844     { "vpsraw",         { Vex, XS, Ib }, 0 },
10845   },
10846   {
10847     /* VEX_W_0F71_R_6_P_2  */
10848     { "vpsllw",         { Vex, XS, Ib }, 0 },
10849   },
10850   {
10851     /* VEX_W_0F72_R_2_P_2  */
10852     { "vpsrld",         { Vex, XS, Ib }, 0 },
10853   },
10854   {
10855     /* VEX_W_0F72_R_4_P_2  */
10856     { "vpsrad",         { Vex, XS, Ib }, 0 },
10857   },
10858   {
10859     /* VEX_W_0F72_R_6_P_2  */
10860     { "vpslld",         { Vex, XS, Ib }, 0 },
10861   },
10862   {
10863     /* VEX_W_0F73_R_2_P_2  */
10864     { "vpsrlq",         { Vex, XS, Ib }, 0 },
10865   },
10866   {
10867     /* VEX_W_0F73_R_3_P_2  */
10868     { "vpsrldq",        { Vex, XS, Ib }, 0 },
10869   },
10870   {
10871     /* VEX_W_0F73_R_6_P_2  */
10872     { "vpsllq",         { Vex, XS, Ib }, 0 },
10873   },
10874   {
10875     /* VEX_W_0F73_R_7_P_2  */
10876     { "vpslldq",        { Vex, XS, Ib }, 0 },
10877   },
10878   {
10879     /* VEX_W_0F74_P_2 */
10880     { "vpcmpeqb",       { XM, Vex, EXx }, 0 },
10881   },
10882   {
10883     /* VEX_W_0F75_P_2 */
10884     { "vpcmpeqw",       { XM, Vex, EXx }, 0 },
10885   },
10886   {
10887     /* VEX_W_0F76_P_2 */
10888     { "vpcmpeqd",       { XM, Vex, EXx }, 0 },
10889   },
10890   {
10891     /* VEX_W_0F77_P_0 */
10892     { "",               { VZERO }, 0 },
10893   },
10894   {
10895     /* VEX_W_0F7C_P_2 */
10896     { "vhaddpd",        { XM, Vex, EXx }, 0 },
10897   },
10898   {
10899     /* VEX_W_0F7C_P_3 */
10900     { "vhaddps",        { XM, Vex, EXx }, 0 },
10901   },
10902   {
10903     /* VEX_W_0F7D_P_2 */
10904     { "vhsubpd",        { XM, Vex, EXx }, 0 },
10905   },
10906   {
10907     /* VEX_W_0F7D_P_3 */
10908     { "vhsubps",        { XM, Vex, EXx }, 0 },
10909   },
10910   {
10911     /* VEX_W_0F7E_P_1 */
10912     { "vmovq",          { XMScalar, EXqScalar }, 0 },
10913   },
10914   {
10915     /* VEX_W_0F7F_P_1 */
10916     { "vmovdqu",        { EXxS, XM }, 0 },
10917   },
10918   {
10919     /* VEX_W_0F7F_P_2 */
10920     { "vmovdqa",        { EXxS, XM }, 0 },
10921   },
10922   {
10923     /* VEX_W_0F90_P_0_LEN_0 */
10924     { "kmovw",          { MaskG, MaskE }, 0 },
10925     { "kmovq",          { MaskG, MaskE }, 0 },
10926   },
10927   {
10928     /* VEX_W_0F90_P_2_LEN_0 */
10929     { "kmovb",          { MaskG, MaskBDE }, 0 },
10930     { "kmovd",          { MaskG, MaskBDE }, 0 },
10931   },
10932   {
10933     /* VEX_W_0F91_P_0_LEN_0 */
10934     { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
10935     { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
10936   },
10937   {
10938     /* VEX_W_0F91_P_2_LEN_0 */
10939     { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
10940     { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
10941   },
10942   {
10943     /* VEX_W_0F92_P_0_LEN_0 */
10944     { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
10945   },
10946   {
10947     /* VEX_W_0F92_P_2_LEN_0 */
10948     { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
10949   },
10950   {
10951     /* VEX_W_0F92_P_3_LEN_0 */
10952     { MOD_TABLE (MOD_VEX_W_0_0F92_P_3_LEN_0) },
10953     { MOD_TABLE (MOD_VEX_W_1_0F92_P_3_LEN_0) },
10954   },
10955   {
10956     /* VEX_W_0F93_P_0_LEN_0 */
10957     { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
10958   },
10959   {
10960     /* VEX_W_0F93_P_2_LEN_0 */
10961     { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
10962   },
10963   {
10964     /* VEX_W_0F93_P_3_LEN_0 */
10965     { MOD_TABLE (MOD_VEX_W_0_0F93_P_3_LEN_0) },
10966     { MOD_TABLE (MOD_VEX_W_1_0F93_P_3_LEN_0) },
10967   },
10968   {
10969     /* VEX_W_0F98_P_0_LEN_0 */
10970     { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
10971     { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
10972   },
10973   {
10974     /* VEX_W_0F98_P_2_LEN_0 */
10975     { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
10976     { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
10977   },
10978   {
10979     /* VEX_W_0F99_P_0_LEN_0 */
10980     { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
10981     { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
10982   },
10983   {
10984     /* VEX_W_0F99_P_2_LEN_0 */
10985     { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
10986     { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
10987   },
10988   {
10989     /* VEX_W_0FAE_R_2_M_0 */
10990     { "vldmxcsr",       { Md }, 0 },
10991   },
10992   {
10993     /* VEX_W_0FAE_R_3_M_0 */
10994     { "vstmxcsr",       { Md }, 0 },
10995   },
10996   {
10997     /* VEX_W_0FC2_P_0 */
10998     { "vcmpps",         { XM, Vex, EXx, VCMP }, 0 },
10999   },
11000   {
11001     /* VEX_W_0FC2_P_1 */
11002     { "vcmpss",         { XMScalar, VexScalar, EXdScalar, VCMP }, 0 },
11003   },
11004   {
11005     /* VEX_W_0FC2_P_2 */
11006     { "vcmppd",         { XM, Vex, EXx, VCMP }, 0 },
11007   },
11008   {
11009     /* VEX_W_0FC2_P_3 */
11010     { "vcmpsd",         { XMScalar, VexScalar, EXqScalar, VCMP }, 0 },
11011   },
11012   {
11013     /* VEX_W_0FC4_P_2 */
11014     { "vpinsrw",        { XM, Vex128, Edqw, Ib }, 0 },
11015   },
11016   {
11017     /* VEX_W_0FC5_P_2 */
11018     { "vpextrw",        { Gdq, XS, Ib }, 0 },
11019   },
11020   {
11021     /* VEX_W_0FD0_P_2 */
11022     { "vaddsubpd",      { XM, Vex, EXx }, 0 },
11023   },
11024   {
11025     /* VEX_W_0FD0_P_3 */
11026     { "vaddsubps",      { XM, Vex, EXx }, 0 },
11027   },
11028   {
11029     /* VEX_W_0FD1_P_2 */
11030     { "vpsrlw",         { XM, Vex, EXxmm }, 0 },
11031   },
11032   {
11033     /* VEX_W_0FD2_P_2 */
11034     { "vpsrld",         { XM, Vex, EXxmm }, 0 },
11035   },
11036   {
11037     /* VEX_W_0FD3_P_2 */
11038     { "vpsrlq",         { XM, Vex, EXxmm }, 0 },
11039   },
11040   {
11041     /* VEX_W_0FD4_P_2 */
11042     { "vpaddq",         { XM, Vex, EXx }, 0 },
11043   },
11044   {
11045     /* VEX_W_0FD5_P_2 */
11046     { "vpmullw",        { XM, Vex, EXx }, 0 },
11047   },
11048   {
11049     /* VEX_W_0FD6_P_2 */
11050     { "vmovq",          { EXqScalarS, XMScalar }, 0 },
11051   },
11052   {
11053     /* VEX_W_0FD7_P_2_M_1 */
11054     { "vpmovmskb",      { Gdq, XS }, 0 },
11055   },
11056   {
11057     /* VEX_W_0FD8_P_2 */
11058     { "vpsubusb",       { XM, Vex, EXx }, 0 },
11059   },
11060   {
11061     /* VEX_W_0FD9_P_2 */
11062     { "vpsubusw",       { XM, Vex, EXx }, 0 },
11063   },
11064   {
11065     /* VEX_W_0FDA_P_2 */
11066     { "vpminub",        { XM, Vex, EXx }, 0 },
11067   },
11068   {
11069     /* VEX_W_0FDB_P_2 */
11070     { "vpand",          { XM, Vex, EXx }, 0 },
11071   },
11072   {
11073     /* VEX_W_0FDC_P_2 */
11074     { "vpaddusb",       { XM, Vex, EXx }, 0 },
11075   },
11076   {
11077     /* VEX_W_0FDD_P_2 */
11078     { "vpaddusw",       { XM, Vex, EXx }, 0 },
11079   },
11080   {
11081     /* VEX_W_0FDE_P_2 */
11082     { "vpmaxub",        { XM, Vex, EXx }, 0 },
11083   },
11084   {
11085     /* VEX_W_0FDF_P_2 */
11086     { "vpandn",         { XM, Vex, EXx }, 0 },
11087   },
11088   {
11089     /* VEX_W_0FE0_P_2  */
11090     { "vpavgb",         { XM, Vex, EXx }, 0 },
11091   },
11092   {
11093     /* VEX_W_0FE1_P_2  */
11094     { "vpsraw",         { XM, Vex, EXxmm }, 0 },
11095   },
11096   {
11097     /* VEX_W_0FE2_P_2  */
11098     { "vpsrad",         { XM, Vex, EXxmm }, 0 },
11099   },
11100   {
11101     /* VEX_W_0FE3_P_2  */
11102     { "vpavgw",         { XM, Vex, EXx }, 0 },
11103   },
11104   {
11105     /* VEX_W_0FE4_P_2  */
11106     { "vpmulhuw",       { XM, Vex, EXx }, 0 },
11107   },
11108   {
11109     /* VEX_W_0FE5_P_2  */
11110     { "vpmulhw",        { XM, Vex, EXx }, 0 },
11111   },
11112   {
11113     /* VEX_W_0FE6_P_1  */
11114     { "vcvtdq2pd",      { XM, EXxmmq }, 0 },
11115   },
11116   {
11117     /* VEX_W_0FE6_P_2  */
11118     { "vcvttpd2dq%XY",  { XMM, EXx }, 0 },
11119   },
11120   {
11121     /* VEX_W_0FE6_P_3  */
11122     { "vcvtpd2dq%XY",   { XMM, EXx }, 0 },
11123   },
11124   {
11125     /* VEX_W_0FE7_P_2_M_0 */
11126     { "vmovntdq",       { Mx, XM }, 0 },
11127   },
11128   {
11129     /* VEX_W_0FE8_P_2  */
11130     { "vpsubsb",        { XM, Vex, EXx }, 0 },
11131   },
11132   {
11133     /* VEX_W_0FE9_P_2  */
11134     { "vpsubsw",        { XM, Vex, EXx }, 0 },
11135   },
11136   {
11137     /* VEX_W_0FEA_P_2  */
11138     { "vpminsw",        { XM, Vex, EXx }, 0 },
11139   },
11140   {
11141     /* VEX_W_0FEB_P_2  */
11142     { "vpor",           { XM, Vex, EXx }, 0 },
11143   },
11144   {
11145     /* VEX_W_0FEC_P_2  */
11146     { "vpaddsb",        { XM, Vex, EXx }, 0 },
11147   },
11148   {
11149     /* VEX_W_0FED_P_2  */
11150     { "vpaddsw",        { XM, Vex, EXx }, 0 },
11151   },
11152   {
11153     /* VEX_W_0FEE_P_2  */
11154     { "vpmaxsw",        { XM, Vex, EXx }, 0 },
11155   },
11156   {
11157     /* VEX_W_0FEF_P_2  */
11158     { "vpxor",          { XM, Vex, EXx }, 0 },
11159   },
11160   {
11161     /* VEX_W_0FF0_P_3_M_0 */
11162     { "vlddqu",         { XM, M }, 0 },
11163   },
11164   {
11165     /* VEX_W_0FF1_P_2 */
11166     { "vpsllw",         { XM, Vex, EXxmm }, 0 },
11167   },
11168   {
11169     /* VEX_W_0FF2_P_2 */
11170     { "vpslld",         { XM, Vex, EXxmm }, 0 },
11171   },
11172   {
11173     /* VEX_W_0FF3_P_2 */
11174     { "vpsllq",         { XM, Vex, EXxmm }, 0 },
11175   },
11176   {
11177     /* VEX_W_0FF4_P_2 */
11178     { "vpmuludq",       { XM, Vex, EXx }, 0 },
11179   },
11180   {
11181     /* VEX_W_0FF5_P_2 */
11182     { "vpmaddwd",       { XM, Vex, EXx }, 0 },
11183   },
11184   {
11185     /* VEX_W_0FF6_P_2 */
11186     { "vpsadbw",        { XM, Vex, EXx }, 0 },
11187   },
11188   {
11189     /* VEX_W_0FF7_P_2 */
11190     { "vmaskmovdqu",    { XM, XS }, 0 },
11191   },
11192   {
11193     /* VEX_W_0FF8_P_2 */
11194     { "vpsubb",         { XM, Vex, EXx }, 0 },
11195   },
11196   {
11197     /* VEX_W_0FF9_P_2 */
11198     { "vpsubw",         { XM, Vex, EXx }, 0 },
11199   },
11200   {
11201     /* VEX_W_0FFA_P_2 */
11202     { "vpsubd",         { XM, Vex, EXx }, 0 },
11203   },
11204   {
11205     /* VEX_W_0FFB_P_2 */
11206     { "vpsubq",         { XM, Vex, EXx }, 0 },
11207   },
11208   {
11209     /* VEX_W_0FFC_P_2 */
11210     { "vpaddb",         { XM, Vex, EXx }, 0 },
11211   },
11212   {
11213     /* VEX_W_0FFD_P_2 */
11214     { "vpaddw",         { XM, Vex, EXx }, 0 },
11215   },
11216   {
11217     /* VEX_W_0FFE_P_2 */
11218     { "vpaddd",         { XM, Vex, EXx }, 0 },
11219   },
11220   {
11221     /* VEX_W_0F3800_P_2  */
11222     { "vpshufb",        { XM, Vex, EXx }, 0 },
11223   },
11224   {
11225     /* VEX_W_0F3801_P_2  */
11226     { "vphaddw",        { XM, Vex, EXx }, 0 },
11227   },
11228   {
11229     /* VEX_W_0F3802_P_2  */
11230     { "vphaddd",        { XM, Vex, EXx }, 0 },
11231   },
11232   {
11233     /* VEX_W_0F3803_P_2  */
11234     { "vphaddsw",       { XM, Vex, EXx }, 0 },
11235   },
11236   {
11237     /* VEX_W_0F3804_P_2  */
11238     { "vpmaddubsw",     { XM, Vex, EXx }, 0 },
11239   },
11240   {
11241     /* VEX_W_0F3805_P_2  */
11242     { "vphsubw",        { XM, Vex, EXx }, 0 },
11243   },
11244   {
11245     /* VEX_W_0F3806_P_2  */
11246     { "vphsubd",        { XM, Vex, EXx }, 0 },
11247   },
11248   {
11249     /* VEX_W_0F3807_P_2  */
11250     { "vphsubsw",       { XM, Vex, EXx }, 0 },
11251   },
11252   {
11253     /* VEX_W_0F3808_P_2  */
11254     { "vpsignb",        { XM, Vex, EXx }, 0 },
11255   },
11256   {
11257     /* VEX_W_0F3809_P_2  */
11258     { "vpsignw",        { XM, Vex, EXx }, 0 },
11259   },
11260   {
11261     /* VEX_W_0F380A_P_2  */
11262     { "vpsignd",        { XM, Vex, EXx }, 0 },
11263   },
11264   {
11265     /* VEX_W_0F380B_P_2  */
11266     { "vpmulhrsw",      { XM, Vex, EXx }, 0 },
11267   },
11268   {
11269     /* VEX_W_0F380C_P_2  */
11270     { "vpermilps",      { XM, Vex, EXx }, 0 },
11271   },
11272   {
11273     /* VEX_W_0F380D_P_2  */
11274     { "vpermilpd",      { XM, Vex, EXx }, 0 },
11275   },
11276   {
11277     /* VEX_W_0F380E_P_2  */
11278     { "vtestps",        { XM, EXx }, 0 },
11279   },
11280   {
11281     /* VEX_W_0F380F_P_2  */
11282     { "vtestpd",        { XM, EXx }, 0 },
11283   },
11284   {
11285     /* VEX_W_0F3816_P_2  */
11286     { "vpermps",        { XM, Vex, EXx }, 0 },
11287   },
11288   {
11289     /* VEX_W_0F3817_P_2 */
11290     { "vptest",         { XM, EXx }, 0 },
11291   },
11292   {
11293     /* VEX_W_0F3818_P_2 */
11294     { "vbroadcastss",   { XM, EXxmm_md }, 0 },
11295   },
11296   {
11297     /* VEX_W_0F3819_P_2 */
11298     { "vbroadcastsd",   { XM, EXxmm_mq }, 0 },
11299   },
11300   {
11301     /* VEX_W_0F381A_P_2_M_0 */
11302     { "vbroadcastf128", { XM, Mxmm }, 0 },
11303   },
11304   {
11305     /* VEX_W_0F381C_P_2 */
11306     { "vpabsb",         { XM, EXx }, 0 },
11307   },
11308   {
11309     /* VEX_W_0F381D_P_2 */
11310     { "vpabsw",         { XM, EXx }, 0 },
11311   },
11312   {
11313     /* VEX_W_0F381E_P_2 */
11314     { "vpabsd",         { XM, EXx }, 0 },
11315   },
11316   {
11317     /* VEX_W_0F3820_P_2 */
11318     { "vpmovsxbw",      { XM, EXxmmq }, 0 },
11319   },
11320   {
11321     /* VEX_W_0F3821_P_2 */
11322     { "vpmovsxbd",      { XM, EXxmmqd }, 0 },
11323   },
11324   {
11325     /* VEX_W_0F3822_P_2 */
11326     { "vpmovsxbq",      { XM, EXxmmdw }, 0 },
11327   },
11328   {
11329     /* VEX_W_0F3823_P_2 */
11330     { "vpmovsxwd",      { XM, EXxmmq }, 0 },
11331   },
11332   {
11333     /* VEX_W_0F3824_P_2 */
11334     { "vpmovsxwq",      { XM, EXxmmqd }, 0 },
11335   },
11336   {
11337     /* VEX_W_0F3825_P_2 */
11338     { "vpmovsxdq",      { XM, EXxmmq }, 0 },
11339   },
11340   {
11341     /* VEX_W_0F3828_P_2 */
11342     { "vpmuldq",        { XM, Vex, EXx }, 0 },
11343   },
11344   {
11345     /* VEX_W_0F3829_P_2 */
11346     { "vpcmpeqq",       { XM, Vex, EXx }, 0 },
11347   },
11348   {
11349     /* VEX_W_0F382A_P_2_M_0 */
11350     { "vmovntdqa",      { XM, Mx }, 0 },
11351   },
11352   {
11353     /* VEX_W_0F382B_P_2 */
11354     { "vpackusdw",      { XM, Vex, EXx }, 0 },
11355   },
11356   {
11357     /* VEX_W_0F382C_P_2_M_0 */
11358     { "vmaskmovps",     { XM, Vex, Mx }, 0 },
11359   },
11360   {
11361     /* VEX_W_0F382D_P_2_M_0 */
11362     { "vmaskmovpd",     { XM, Vex, Mx }, 0 },
11363   },
11364   {
11365     /* VEX_W_0F382E_P_2_M_0 */
11366     { "vmaskmovps",     { Mx, Vex, XM }, 0 },
11367   },
11368   {
11369     /* VEX_W_0F382F_P_2_M_0 */
11370     { "vmaskmovpd",     { Mx, Vex, XM }, 0 },
11371   },
11372   {
11373     /* VEX_W_0F3830_P_2 */
11374     { "vpmovzxbw",      { XM, EXxmmq }, 0 },
11375   },
11376   {
11377     /* VEX_W_0F3831_P_2 */
11378     { "vpmovzxbd",      { XM, EXxmmqd }, 0 },
11379   },
11380   {
11381     /* VEX_W_0F3832_P_2 */
11382     { "vpmovzxbq",      { XM, EXxmmdw }, 0 },
11383   },
11384   {
11385     /* VEX_W_0F3833_P_2 */
11386     { "vpmovzxwd",      { XM, EXxmmq }, 0 },
11387   },
11388   {
11389     /* VEX_W_0F3834_P_2 */
11390     { "vpmovzxwq",      { XM, EXxmmqd }, 0 },
11391   },
11392   {
11393     /* VEX_W_0F3835_P_2 */
11394     { "vpmovzxdq",      { XM, EXxmmq }, 0 },
11395   },
11396   {
11397     /* VEX_W_0F3836_P_2  */
11398     { "vpermd",         { XM, Vex, EXx }, 0 },
11399   },
11400   {
11401     /* VEX_W_0F3837_P_2 */
11402     { "vpcmpgtq",       { XM, Vex, EXx }, 0 },
11403   },
11404   {
11405     /* VEX_W_0F3838_P_2 */
11406     { "vpminsb",        { XM, Vex, EXx }, 0 },
11407   },
11408   {
11409     /* VEX_W_0F3839_P_2 */
11410     { "vpminsd",        { XM, Vex, EXx }, 0 },
11411   },
11412   {
11413     /* VEX_W_0F383A_P_2 */
11414     { "vpminuw",        { XM, Vex, EXx }, 0 },
11415   },
11416   {
11417     /* VEX_W_0F383B_P_2 */
11418     { "vpminud",        { XM, Vex, EXx }, 0 },
11419   },
11420   {
11421     /* VEX_W_0F383C_P_2 */
11422     { "vpmaxsb",        { XM, Vex, EXx }, 0 },
11423   },
11424   {
11425     /* VEX_W_0F383D_P_2 */
11426     { "vpmaxsd",        { XM, Vex, EXx }, 0 },
11427   },
11428   {
11429     /* VEX_W_0F383E_P_2 */
11430     { "vpmaxuw",        { XM, Vex, EXx }, 0 },
11431   },
11432   {
11433     /* VEX_W_0F383F_P_2 */
11434     { "vpmaxud",        { XM, Vex, EXx }, 0 },
11435   },
11436   {
11437     /* VEX_W_0F3840_P_2 */
11438     { "vpmulld",        { XM, Vex, EXx }, 0 },
11439   },
11440   {
11441     /* VEX_W_0F3841_P_2 */
11442     { "vphminposuw",    { XM, EXx }, 0 },
11443   },
11444   {
11445     /* VEX_W_0F3846_P_2 */
11446     { "vpsravd",        { XM, Vex, EXx }, 0 },
11447   },
11448   {
11449     /* VEX_W_0F3858_P_2 */
11450     { "vpbroadcastd", { XM, EXxmm_md }, 0 },
11451   },
11452   {
11453     /* VEX_W_0F3859_P_2 */
11454     { "vpbroadcastq",   { XM, EXxmm_mq }, 0 },
11455   },
11456   {
11457     /* VEX_W_0F385A_P_2_M_0 */
11458     { "vbroadcasti128", { XM, Mxmm }, 0 },
11459   },
11460   {
11461     /* VEX_W_0F3878_P_2 */
11462     { "vpbroadcastb",   { XM, EXxmm_mb }, 0 },
11463   },
11464   {
11465     /* VEX_W_0F3879_P_2 */
11466     { "vpbroadcastw",   { XM, EXxmm_mw }, 0 },
11467   },
11468   {
11469     /* VEX_W_0F38DB_P_2 */
11470     { "vaesimc",        { XM, EXx }, 0 },
11471   },
11472   {
11473     /* VEX_W_0F38DC_P_2 */
11474     { "vaesenc",        { XM, Vex128, EXx }, 0 },
11475   },
11476   {
11477     /* VEX_W_0F38DD_P_2 */
11478     { "vaesenclast",    { XM, Vex128, EXx }, 0 },
11479   },
11480   {
11481     /* VEX_W_0F38DE_P_2 */
11482     { "vaesdec",        { XM, Vex128, EXx }, 0 },
11483   },
11484   {
11485     /* VEX_W_0F38DF_P_2 */
11486     { "vaesdeclast",    { XM, Vex128, EXx }, 0 },
11487   },
11488   {
11489     /* VEX_W_0F3A00_P_2 */
11490     { Bad_Opcode },
11491     { "vpermq",         { XM, EXx, Ib }, 0 },
11492   },
11493   {
11494     /* VEX_W_0F3A01_P_2 */
11495     { Bad_Opcode },
11496     { "vpermpd",        { XM, EXx, Ib }, 0 },
11497   },
11498   {
11499     /* VEX_W_0F3A02_P_2 */
11500     { "vpblendd",       { XM, Vex, EXx, Ib }, 0 },
11501   },
11502   {
11503     /* VEX_W_0F3A04_P_2 */
11504     { "vpermilps",      { XM, EXx, Ib }, 0 },
11505   },
11506   {
11507     /* VEX_W_0F3A05_P_2 */
11508     { "vpermilpd",      { XM, EXx, Ib }, 0 },
11509   },
11510   {
11511     /* VEX_W_0F3A06_P_2 */
11512     { "vperm2f128",     { XM, Vex256, EXx, Ib }, 0 },
11513   },
11514   {
11515     /* VEX_W_0F3A08_P_2 */
11516     { "vroundps",       { XM, EXx, Ib }, 0 },
11517   },
11518   {
11519     /* VEX_W_0F3A09_P_2 */
11520     { "vroundpd",       { XM, EXx, Ib }, 0 },
11521   },
11522   {
11523     /* VEX_W_0F3A0A_P_2 */
11524     { "vroundss",       { XMScalar, VexScalar, EXdScalar, Ib }, 0 },
11525   },
11526   {
11527     /* VEX_W_0F3A0B_P_2 */
11528     { "vroundsd",       { XMScalar, VexScalar, EXqScalar, Ib }, 0 },
11529   },
11530   {
11531     /* VEX_W_0F3A0C_P_2 */
11532     { "vblendps",       { XM, Vex, EXx, Ib }, 0 },
11533   },
11534   {
11535     /* VEX_W_0F3A0D_P_2 */
11536     { "vblendpd",       { XM, Vex, EXx, Ib }, 0 },
11537   },
11538   {
11539     /* VEX_W_0F3A0E_P_2 */
11540     { "vpblendw",       { XM, Vex, EXx, Ib }, 0 },
11541   },
11542   {
11543     /* VEX_W_0F3A0F_P_2 */
11544     { "vpalignr",       { XM, Vex, EXx, Ib }, 0 },
11545   },
11546   {
11547     /* VEX_W_0F3A14_P_2 */
11548     { "vpextrb",        { Edqb, XM, Ib }, 0 },
11549   },
11550   {
11551     /* VEX_W_0F3A15_P_2 */
11552     { "vpextrw",        { Edqw, XM, Ib }, 0 },
11553   },
11554   {
11555     /* VEX_W_0F3A18_P_2 */
11556     { "vinsertf128",    { XM, Vex256, EXxmm, Ib }, 0 },
11557   },
11558   {
11559     /* VEX_W_0F3A19_P_2 */
11560     { "vextractf128",   { EXxmm, XM, Ib }, 0 },
11561   },
11562   {
11563     /* VEX_W_0F3A20_P_2 */
11564     { "vpinsrb",        { XM, Vex128, Edqb, Ib }, 0 },
11565   },
11566   {
11567     /* VEX_W_0F3A21_P_2 */
11568     { "vinsertps",      { XM, Vex128, EXd, Ib }, 0 },
11569   },
11570   {
11571     /* VEX_W_0F3A30_P_2_LEN_0 */
11572     { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) },
11573     { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) },
11574   },
11575   {
11576     /* VEX_W_0F3A31_P_2_LEN_0 */
11577     { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) },
11578     { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) },
11579   },
11580   {
11581     /* VEX_W_0F3A32_P_2_LEN_0 */
11582     { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) },
11583     { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) },
11584   },
11585   {
11586     /* VEX_W_0F3A33_P_2_LEN_0 */
11587     { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) },
11588     { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) },
11589   },
11590   {
11591     /* VEX_W_0F3A38_P_2 */
11592     { "vinserti128",    { XM, Vex256, EXxmm, Ib }, 0 },
11593   },
11594   {
11595     /* VEX_W_0F3A39_P_2 */
11596     { "vextracti128",   { EXxmm, XM, Ib }, 0 },
11597   },
11598   {
11599     /* VEX_W_0F3A40_P_2 */
11600     { "vdpps",          { XM, Vex, EXx, Ib }, 0 },
11601   },
11602   {
11603     /* VEX_W_0F3A41_P_2 */
11604     { "vdppd",          { XM, Vex128, EXx, Ib }, 0 },
11605   },
11606   {
11607     /* VEX_W_0F3A42_P_2 */
11608     { "vmpsadbw",       { XM, Vex, EXx, Ib }, 0 },
11609   },
11610   {
11611     /* VEX_W_0F3A44_P_2 */
11612     { "vpclmulqdq",     { XM, Vex128, EXx, PCLMUL }, 0 },
11613   },
11614   {
11615     /* VEX_W_0F3A46_P_2 */
11616     { "vperm2i128",     { XM, Vex256, EXx, Ib }, 0 },
11617   },
11618   {
11619     /* VEX_W_0F3A48_P_2 */
11620     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11621     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11622   },
11623   {
11624     /* VEX_W_0F3A49_P_2 */
11625     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11626     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11627   },
11628   {
11629     /* VEX_W_0F3A4A_P_2 */
11630     { "vblendvps",      { XM, Vex, EXx, XMVexI4 }, 0 },
11631   },
11632   {
11633     /* VEX_W_0F3A4B_P_2 */
11634     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 }, 0 },
11635   },
11636   {
11637     /* VEX_W_0F3A4C_P_2 */
11638     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 }, 0 },
11639   },
11640   {
11641     /* VEX_W_0F3A60_P_2 */
11642     { "vpcmpestrm",     { XM, EXx, Ib }, 0 },
11643   },
11644   {
11645     /* VEX_W_0F3A61_P_2 */
11646     { "vpcmpestri",     { XM, EXx, Ib }, 0 },
11647   },
11648   {
11649     /* VEX_W_0F3A62_P_2 */
11650     { "vpcmpistrm",     { XM, EXx, Ib }, 0 },
11651   },
11652   {
11653     /* VEX_W_0F3A63_P_2 */
11654     { "vpcmpistri",     { XM, EXx, Ib }, 0 },
11655   },
11656   {
11657     /* VEX_W_0F3ADF_P_2 */
11658     { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
11659   },
11660 #define NEED_VEX_W_TABLE
11661 #include "i386-dis-evex.h"
11662 #undef NEED_VEX_W_TABLE
11663 };
11664
11665 static const struct dis386 mod_table[][2] = {
11666   {
11667     /* MOD_8D */
11668     { "leaS",           { Gv, M }, 0 },
11669   },
11670   {
11671     /* MOD_C6_REG_7 */
11672     { Bad_Opcode },
11673     { RM_TABLE (RM_C6_REG_7) },
11674   },
11675   {
11676     /* MOD_C7_REG_7 */
11677     { Bad_Opcode },
11678     { RM_TABLE (RM_C7_REG_7) },
11679   },
11680   {
11681     /* MOD_FF_REG_3 */
11682     { "Jcall^", { indirEp }, 0 },
11683   },
11684   {
11685     /* MOD_FF_REG_5 */
11686     { "Jjmp^", { indirEp }, 0 },
11687   },
11688   {
11689     /* MOD_0F01_REG_0 */
11690     { X86_64_TABLE (X86_64_0F01_REG_0) },
11691     { RM_TABLE (RM_0F01_REG_0) },
11692   },
11693   {
11694     /* MOD_0F01_REG_1 */
11695     { X86_64_TABLE (X86_64_0F01_REG_1) },
11696     { RM_TABLE (RM_0F01_REG_1) },
11697   },
11698   {
11699     /* MOD_0F01_REG_2 */
11700     { X86_64_TABLE (X86_64_0F01_REG_2) },
11701     { RM_TABLE (RM_0F01_REG_2) },
11702   },
11703   {
11704     /* MOD_0F01_REG_3 */
11705     { X86_64_TABLE (X86_64_0F01_REG_3) },
11706     { RM_TABLE (RM_0F01_REG_3) },
11707   },
11708   {
11709     /* MOD_0F01_REG_5 */
11710     { Bad_Opcode },
11711     { RM_TABLE (RM_0F01_REG_5) },
11712   },
11713   {
11714     /* MOD_0F01_REG_7 */
11715     { "invlpg",         { Mb }, 0 },
11716     { RM_TABLE (RM_0F01_REG_7) },
11717   },
11718   {
11719     /* MOD_0F12_PREFIX_0 */
11720     { "movlps",         { XM, EXq }, PREFIX_OPCODE },
11721     { "movhlps",        { XM, EXq }, PREFIX_OPCODE },
11722   },
11723   {
11724     /* MOD_0F13 */
11725     { "movlpX",         { EXq, XM }, PREFIX_OPCODE },
11726   },
11727   {
11728     /* MOD_0F16_PREFIX_0 */
11729     { "movhps",         { XM, EXq }, 0 },
11730     { "movlhps",        { XM, EXq }, 0 },
11731   },
11732   {
11733     /* MOD_0F17 */
11734     { "movhpX",         { EXq, XM }, PREFIX_OPCODE },
11735   },
11736   {
11737     /* MOD_0F18_REG_0 */
11738     { "prefetchnta",    { Mb }, 0 },
11739   },
11740   {
11741     /* MOD_0F18_REG_1 */
11742     { "prefetcht0",     { Mb }, 0 },
11743   },
11744   {
11745     /* MOD_0F18_REG_2 */
11746     { "prefetcht1",     { Mb }, 0 },
11747   },
11748   {
11749     /* MOD_0F18_REG_3 */
11750     { "prefetcht2",     { Mb }, 0 },
11751   },
11752   {
11753     /* MOD_0F18_REG_4 */
11754     { "nop/reserved",   { Mb }, 0 },
11755   },
11756   {
11757     /* MOD_0F18_REG_5 */
11758     { "nop/reserved",   { Mb }, 0 },
11759   },
11760   {
11761     /* MOD_0F18_REG_6 */
11762     { "nop/reserved",   { Mb }, 0 },
11763   },
11764   {
11765     /* MOD_0F18_REG_7 */
11766     { "nop/reserved",   { Mb }, 0 },
11767   },
11768   {
11769     /* MOD_0F1A_PREFIX_0 */
11770     { "bndldx",         { Gbnd, Ev_bnd }, 0 },
11771     { "nopQ",           { Ev }, 0 },
11772   },
11773   {
11774     /* MOD_0F1B_PREFIX_0 */
11775     { "bndstx",         { Ev_bnd, Gbnd }, 0 },
11776     { "nopQ",           { Ev }, 0 },
11777   },
11778   {
11779     /* MOD_0F1B_PREFIX_1 */
11780     { "bndmk",          { Gbnd, Ev_bnd }, 0 },
11781     { "nopQ",           { Ev }, 0 },
11782   },
11783   {
11784     /* MOD_0F24 */
11785     { Bad_Opcode },
11786     { "movL",           { Rd, Td }, 0 },
11787   },
11788   {
11789     /* MOD_0F26 */
11790     { Bad_Opcode },
11791     { "movL",           { Td, Rd }, 0 },
11792   },
11793   {
11794     /* MOD_0F2B_PREFIX_0 */
11795     {"movntps",         { Mx, XM }, PREFIX_OPCODE },
11796   },
11797   {
11798     /* MOD_0F2B_PREFIX_1 */
11799     {"movntss",         { Md, XM }, PREFIX_OPCODE },
11800   },
11801   {
11802     /* MOD_0F2B_PREFIX_2 */
11803     {"movntpd",         { Mx, XM }, PREFIX_OPCODE },
11804   },
11805   {
11806     /* MOD_0F2B_PREFIX_3 */
11807     {"movntsd",         { Mq, XM }, PREFIX_OPCODE },
11808   },
11809   {
11810     /* MOD_0F51 */
11811     { Bad_Opcode },
11812     { "movmskpX",       { Gdq, XS }, PREFIX_OPCODE },
11813   },
11814   {
11815     /* MOD_0F71_REG_2 */
11816     { Bad_Opcode },
11817     { "psrlw",          { MS, Ib }, 0 },
11818   },
11819   {
11820     /* MOD_0F71_REG_4 */
11821     { Bad_Opcode },
11822     { "psraw",          { MS, Ib }, 0 },
11823   },
11824   {
11825     /* MOD_0F71_REG_6 */
11826     { Bad_Opcode },
11827     { "psllw",          { MS, Ib }, 0 },
11828   },
11829   {
11830     /* MOD_0F72_REG_2 */
11831     { Bad_Opcode },
11832     { "psrld",          { MS, Ib }, 0 },
11833   },
11834   {
11835     /* MOD_0F72_REG_4 */
11836     { Bad_Opcode },
11837     { "psrad",          { MS, Ib }, 0 },
11838   },
11839   {
11840     /* MOD_0F72_REG_6 */
11841     { Bad_Opcode },
11842     { "pslld",          { MS, Ib }, 0 },
11843   },
11844   {
11845     /* MOD_0F73_REG_2 */
11846     { Bad_Opcode },
11847     { "psrlq",          { MS, Ib }, 0 },
11848   },
11849   {
11850     /* MOD_0F73_REG_3 */
11851     { Bad_Opcode },
11852     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
11853   },
11854   {
11855     /* MOD_0F73_REG_6 */
11856     { Bad_Opcode },
11857     { "psllq",          { MS, Ib }, 0 },
11858   },
11859   {
11860     /* MOD_0F73_REG_7 */
11861     { Bad_Opcode },
11862     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
11863   },
11864   {
11865     /* MOD_0FAE_REG_0 */
11866     { "fxsave",         { FXSAVE }, 0 },
11867     { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
11868   },
11869   {
11870     /* MOD_0FAE_REG_1 */
11871     { "fxrstor",        { FXSAVE }, 0 },
11872     { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
11873   },
11874   {
11875     /* MOD_0FAE_REG_2 */
11876     { "ldmxcsr",        { Md }, 0 },
11877     { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
11878   },
11879   {
11880     /* MOD_0FAE_REG_3 */
11881     { "stmxcsr",        { Md }, 0 },
11882     { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
11883   },
11884   {
11885     /* MOD_0FAE_REG_4 */
11886     { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_4) },
11887     { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_4) },
11888   },
11889   {
11890     /* MOD_0FAE_REG_5 */
11891     { "xrstor",         { FXSAVE }, 0 },
11892     { RM_TABLE (RM_0FAE_REG_5) },
11893   },
11894   {
11895     /* MOD_0FAE_REG_6 */
11896     { PREFIX_TABLE (PREFIX_0FAE_REG_6) },
11897     { RM_TABLE (RM_0FAE_REG_6) },
11898   },
11899   {
11900     /* MOD_0FAE_REG_7 */
11901     { PREFIX_TABLE (PREFIX_0FAE_REG_7) },
11902     { RM_TABLE (RM_0FAE_REG_7) },
11903   },
11904   {
11905     /* MOD_0FB2 */
11906     { "lssS",           { Gv, Mp }, 0 },
11907   },
11908   {
11909     /* MOD_0FB4 */
11910     { "lfsS",           { Gv, Mp }, 0 },
11911   },
11912   {
11913     /* MOD_0FB5 */
11914     { "lgsS",           { Gv, Mp }, 0 },
11915   },
11916   {
11917     /* MOD_0FC3 */
11918     { PREFIX_TABLE (PREFIX_MOD_0_0FC3) },
11919   },
11920   {
11921     /* MOD_0FC7_REG_3 */
11922     { "xrstors",        { FXSAVE }, 0 },
11923   },
11924   {
11925     /* MOD_0FC7_REG_4 */
11926     { "xsavec",         { FXSAVE }, 0 },
11927   },
11928   {
11929     /* MOD_0FC7_REG_5 */
11930     { "xsaves",         { FXSAVE }, 0 },
11931   },
11932   {
11933     /* MOD_0FC7_REG_6 */
11934     { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6) },
11935     { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6) }
11936   },
11937   {
11938     /* MOD_0FC7_REG_7 */
11939     { "vmptrst",        { Mq }, 0 },
11940     { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7) }
11941   },
11942   {
11943     /* MOD_0FD7 */
11944     { Bad_Opcode },
11945     { "pmovmskb",       { Gdq, MS }, 0 },
11946   },
11947   {
11948     /* MOD_0FE7_PREFIX_2 */
11949     { "movntdq",        { Mx, XM }, 0 },
11950   },
11951   {
11952     /* MOD_0FF0_PREFIX_3 */
11953     { "lddqu",          { XM, M }, 0 },
11954   },
11955   {
11956     /* MOD_0F382A_PREFIX_2 */
11957     { "movntdqa",       { XM, Mx }, 0 },
11958   },
11959   {
11960     /* MOD_62_32BIT */
11961     { "bound{S|}",      { Gv, Ma }, 0 },
11962     { EVEX_TABLE (EVEX_0F) },
11963   },
11964   {
11965     /* MOD_C4_32BIT */
11966     { "lesS",           { Gv, Mp }, 0 },
11967     { VEX_C4_TABLE (VEX_0F) },
11968   },
11969   {
11970     /* MOD_C5_32BIT */
11971     { "ldsS",           { Gv, Mp }, 0 },
11972     { VEX_C5_TABLE (VEX_0F) },
11973   },
11974   {
11975     /* MOD_VEX_0F12_PREFIX_0 */
11976     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
11977     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
11978   },
11979   {
11980     /* MOD_VEX_0F13 */
11981     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
11982   },
11983   {
11984     /* MOD_VEX_0F16_PREFIX_0 */
11985     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
11986     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
11987   },
11988   {
11989     /* MOD_VEX_0F17 */
11990     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
11991   },
11992   {
11993     /* MOD_VEX_0F2B */
11994     { VEX_W_TABLE (VEX_W_0F2B_M_0) },
11995   },
11996   {
11997     /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
11998     { Bad_Opcode },
11999     { "kandw",          { MaskG, MaskVex, MaskR }, 0 },
12000   },
12001   {
12002     /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
12003     { Bad_Opcode },
12004     { "kandq",          { MaskG, MaskVex, MaskR }, 0 },
12005   },
12006   {
12007     /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
12008     { Bad_Opcode },
12009     { "kandb",          { MaskG, MaskVex, MaskR }, 0 },
12010   },
12011   {
12012     /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
12013     { Bad_Opcode },
12014     { "kandd",          { MaskG, MaskVex, MaskR }, 0 },
12015   },
12016   {
12017     /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
12018     { Bad_Opcode },
12019     { "kandnw",         { MaskG, MaskVex, MaskR }, 0 },
12020   },
12021   {
12022     /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
12023     { Bad_Opcode },
12024     { "kandnq",         { MaskG, MaskVex, MaskR }, 0 },
12025   },
12026   {
12027     /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
12028     { Bad_Opcode },
12029     { "kandnb",         { MaskG, MaskVex, MaskR }, 0 },
12030   },
12031   {
12032     /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
12033     { Bad_Opcode },
12034     { "kandnd",         { MaskG, MaskVex, MaskR }, 0 },
12035   },
12036   {
12037     /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
12038     { Bad_Opcode },
12039     { "knotw",          { MaskG, MaskR }, 0 },
12040   },
12041   {
12042     /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
12043     { Bad_Opcode },
12044     { "knotq",          { MaskG, MaskR }, 0 },
12045   },
12046   {
12047     /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
12048     { Bad_Opcode },
12049     { "knotb",          { MaskG, MaskR }, 0 },
12050   },
12051   {
12052     /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
12053     { Bad_Opcode },
12054     { "knotd",          { MaskG, MaskR }, 0 },
12055   },
12056   {
12057     /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
12058     { Bad_Opcode },
12059     { "korw",       { MaskG, MaskVex, MaskR }, 0 },
12060   },
12061   {
12062     /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
12063     { Bad_Opcode },
12064     { "korq",       { MaskG, MaskVex, MaskR }, 0 },
12065   },
12066   {
12067     /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
12068     { Bad_Opcode },
12069     { "korb",       { MaskG, MaskVex, MaskR }, 0 },
12070   },
12071   {
12072     /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
12073     { Bad_Opcode },
12074     { "kord",       { MaskG, MaskVex, MaskR }, 0 },
12075   },
12076  {
12077     /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
12078     { Bad_Opcode },
12079     { "kxnorw",     { MaskG, MaskVex, MaskR }, 0 },
12080   },
12081   {
12082     /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
12083     { Bad_Opcode },
12084     { "kxnorq",     { MaskG, MaskVex, MaskR }, 0 },
12085   },
12086   {
12087     /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
12088     { Bad_Opcode },
12089     { "kxnorb",     { MaskG, MaskVex, MaskR }, 0 },
12090   },
12091   {
12092     /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
12093     { Bad_Opcode },
12094     { "kxnord",     { MaskG, MaskVex, MaskR }, 0 },
12095   },
12096   {
12097     /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
12098     { Bad_Opcode },
12099     { "kxorw",      { MaskG, MaskVex, MaskR }, 0 },
12100   },
12101   {
12102     /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
12103     { Bad_Opcode },
12104     { "kxorq",      { MaskG, MaskVex, MaskR }, 0 },
12105   },
12106   {
12107     /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
12108     { Bad_Opcode },
12109     { "kxorb",      { MaskG, MaskVex, MaskR }, 0 },
12110   },
12111   {
12112     /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
12113     { Bad_Opcode },
12114     { "kxord",      { MaskG, MaskVex, MaskR }, 0 },
12115   },
12116   {
12117     /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
12118     { Bad_Opcode },
12119     { "kaddw",          { MaskG, MaskVex, MaskR }, 0 },
12120   },
12121   {
12122     /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
12123     { Bad_Opcode },
12124     { "kaddq",          { MaskG, MaskVex, MaskR }, 0 },
12125   },
12126   {
12127     /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
12128     { Bad_Opcode },
12129     { "kaddb",          { MaskG, MaskVex, MaskR }, 0 },
12130   },
12131   {
12132     /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
12133     { Bad_Opcode },
12134     { "kaddd",          { MaskG, MaskVex, MaskR }, 0 },
12135   },
12136   {
12137     /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
12138     { Bad_Opcode },
12139     { "kunpckwd",   { MaskG, MaskVex, MaskR }, 0 },
12140   },
12141   {
12142     /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
12143     { Bad_Opcode },
12144     { "kunpckdq",   { MaskG, MaskVex, MaskR }, 0 },
12145   },
12146   {
12147     /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
12148     { Bad_Opcode },
12149     { "kunpckbw",   { MaskG, MaskVex, MaskR }, 0 },
12150   },
12151   {
12152     /* MOD_VEX_0F50 */
12153     { Bad_Opcode },
12154     { VEX_W_TABLE (VEX_W_0F50_M_0) },
12155   },
12156   {
12157     /* MOD_VEX_0F71_REG_2 */
12158     { Bad_Opcode },
12159     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
12160   },
12161   {
12162     /* MOD_VEX_0F71_REG_4 */
12163     { Bad_Opcode },
12164     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
12165   },
12166   {
12167     /* MOD_VEX_0F71_REG_6 */
12168     { Bad_Opcode },
12169     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
12170   },
12171   {
12172     /* MOD_VEX_0F72_REG_2 */
12173     { Bad_Opcode },
12174     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
12175   },
12176   {
12177     /* MOD_VEX_0F72_REG_4 */
12178     { Bad_Opcode },
12179     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
12180   },
12181   {
12182     /* MOD_VEX_0F72_REG_6 */
12183     { Bad_Opcode },
12184     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
12185   },
12186   {
12187     /* MOD_VEX_0F73_REG_2 */
12188     { Bad_Opcode },
12189     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
12190   },
12191   {
12192     /* MOD_VEX_0F73_REG_3 */
12193     { Bad_Opcode },
12194     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
12195   },
12196   {
12197     /* MOD_VEX_0F73_REG_6 */
12198     { Bad_Opcode },
12199     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
12200   },
12201   {
12202     /* MOD_VEX_0F73_REG_7 */
12203     { Bad_Opcode },
12204     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
12205   },
12206   {
12207     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
12208     { "kmovw",          { Ew, MaskG }, 0 },
12209     { Bad_Opcode },
12210   },
12211   {
12212     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
12213     { "kmovq",          { Eq, MaskG }, 0 },
12214     { Bad_Opcode },
12215   },
12216   {
12217     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
12218     { "kmovb",          { Eb, MaskG }, 0 },
12219     { Bad_Opcode },
12220   },
12221   {
12222     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
12223     { "kmovd",          { Ed, MaskG }, 0 },
12224     { Bad_Opcode },
12225   },
12226   {
12227     /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
12228     { Bad_Opcode },
12229     { "kmovw",          { MaskG, Rdq }, 0 },
12230   },
12231   {
12232     /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
12233     { Bad_Opcode },
12234     { "kmovb",          { MaskG, Rdq }, 0 },
12235   },
12236   {
12237     /* MOD_VEX_W_0_0F92_P_3_LEN_0 */
12238     { Bad_Opcode },
12239     { "kmovd",          { MaskG, Rdq }, 0 },
12240   },
12241   {
12242     /* MOD_VEX_W_1_0F92_P_3_LEN_0 */
12243     { Bad_Opcode },
12244     { "kmovq",          { MaskG, Rdq }, 0 },
12245   },
12246   {
12247     /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
12248     { Bad_Opcode },
12249     { "kmovw",          { Gdq, MaskR }, 0 },
12250   },
12251   {
12252     /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
12253     { Bad_Opcode },
12254     { "kmovb",          { Gdq, MaskR }, 0 },
12255   },
12256   {
12257     /* MOD_VEX_W_0_0F93_P_3_LEN_0 */
12258     { Bad_Opcode },
12259     { "kmovd",          { Gdq, MaskR }, 0 },
12260   },
12261   {
12262     /* MOD_VEX_W_1_0F93_P_3_LEN_0 */
12263     { Bad_Opcode },
12264     { "kmovq",          { Gdq, MaskR }, 0 },
12265   },
12266   {
12267     /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
12268     { Bad_Opcode },
12269     { "kortestw", { MaskG, MaskR }, 0 },
12270   },
12271   {
12272     /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
12273     { Bad_Opcode },
12274     { "kortestq", { MaskG, MaskR }, 0 },
12275   },
12276   {
12277     /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
12278     { Bad_Opcode },
12279     { "kortestb", { MaskG, MaskR }, 0 },
12280   },
12281   {
12282     /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
12283     { Bad_Opcode },
12284     { "kortestd", { MaskG, MaskR }, 0 },
12285   },
12286   {
12287     /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
12288     { Bad_Opcode },
12289     { "ktestw", { MaskG, MaskR }, 0 },
12290   },
12291   {
12292     /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
12293     { Bad_Opcode },
12294     { "ktestq", { MaskG, MaskR }, 0 },
12295   },
12296   {
12297     /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
12298     { Bad_Opcode },
12299     { "ktestb", { MaskG, MaskR }, 0 },
12300   },
12301   {
12302     /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
12303     { Bad_Opcode },
12304     { "ktestd", { MaskG, MaskR }, 0 },
12305   },
12306   {
12307     /* MOD_VEX_0FAE_REG_2 */
12308     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
12309   },
12310   {
12311     /* MOD_VEX_0FAE_REG_3 */
12312     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
12313   },
12314   {
12315     /* MOD_VEX_0FD7_PREFIX_2 */
12316     { Bad_Opcode },
12317     { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) },
12318   },
12319   {
12320     /* MOD_VEX_0FE7_PREFIX_2 */
12321     { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) },
12322   },
12323   {
12324     /* MOD_VEX_0FF0_PREFIX_3 */
12325     { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) },
12326   },
12327   {
12328     /* MOD_VEX_0F381A_PREFIX_2 */
12329     { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
12330   },
12331   {
12332     /* MOD_VEX_0F382A_PREFIX_2 */
12333     { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) },
12334   },
12335   {
12336     /* MOD_VEX_0F382C_PREFIX_2 */
12337     { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
12338   },
12339   {
12340     /* MOD_VEX_0F382D_PREFIX_2 */
12341     { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
12342   },
12343   {
12344     /* MOD_VEX_0F382E_PREFIX_2 */
12345     { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
12346   },
12347   {
12348     /* MOD_VEX_0F382F_PREFIX_2 */
12349     { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
12350   },
12351   {
12352     /* MOD_VEX_0F385A_PREFIX_2 */
12353     { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
12354   },
12355   {
12356     /* MOD_VEX_0F388C_PREFIX_2 */
12357     { "vpmaskmov%LW",   { XM, Vex, Mx }, 0 },
12358   },
12359   {
12360     /* MOD_VEX_0F388E_PREFIX_2 */
12361     { "vpmaskmov%LW",   { Mx, Vex, XM }, 0 },
12362   },
12363   {
12364     /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
12365     { Bad_Opcode },
12366     { "kshiftrb",       { MaskG, MaskR, Ib }, 0 },
12367   },
12368   {
12369     /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
12370     { Bad_Opcode },
12371     { "kshiftrw",       { MaskG, MaskR, Ib }, 0 },
12372   },
12373   {
12374     /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
12375     { Bad_Opcode },
12376     { "kshiftrd",       { MaskG, MaskR, Ib }, 0 },
12377   },
12378   {
12379     /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
12380     { Bad_Opcode },
12381     { "kshiftrq",       { MaskG, MaskR, Ib }, 0 },
12382   },
12383   {
12384     /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
12385     { Bad_Opcode },
12386     { "kshiftlb",       { MaskG, MaskR, Ib }, 0 },
12387   },
12388   {
12389     /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
12390     { Bad_Opcode },
12391     { "kshiftlw",       { MaskG, MaskR, Ib }, 0 },
12392   },
12393   {
12394     /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
12395     { Bad_Opcode },
12396     { "kshiftld",       { MaskG, MaskR, Ib }, 0 },
12397   },
12398   {
12399     /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
12400     { Bad_Opcode },
12401     { "kshiftlq",       { MaskG, MaskR, Ib }, 0 },
12402   },
12403 #define NEED_MOD_TABLE
12404 #include "i386-dis-evex.h"
12405 #undef NEED_MOD_TABLE
12406 };
12407
12408 static const struct dis386 rm_table[][8] = {
12409   {
12410     /* RM_C6_REG_7 */
12411     { "xabort",         { Skip_MODRM, Ib }, 0 },
12412   },
12413   {
12414     /* RM_C7_REG_7 */
12415     { "xbeginT",        { Skip_MODRM, Jv }, 0 },
12416   },
12417   {
12418     /* RM_0F01_REG_0 */
12419     { Bad_Opcode },
12420     { "vmcall",         { Skip_MODRM }, 0 },
12421     { "vmlaunch",       { Skip_MODRM }, 0 },
12422     { "vmresume",       { Skip_MODRM }, 0 },
12423     { "vmxoff",         { Skip_MODRM }, 0 },
12424   },
12425   {
12426     /* RM_0F01_REG_1 */
12427     { "monitor",        { { OP_Monitor, 0 } }, 0 },
12428     { "mwait",          { { OP_Mwait, 0 } }, 0 },
12429     { "clac",           { Skip_MODRM }, 0 },
12430     { "stac",           { Skip_MODRM }, 0 },
12431     { Bad_Opcode },
12432     { Bad_Opcode },
12433     { Bad_Opcode },
12434     { "encls",          { Skip_MODRM }, 0 },
12435   },
12436   {
12437     /* RM_0F01_REG_2 */
12438     { "xgetbv",         { Skip_MODRM }, 0 },
12439     { "xsetbv",         { Skip_MODRM }, 0 },
12440     { Bad_Opcode },
12441     { Bad_Opcode },
12442     { "vmfunc",         { Skip_MODRM }, 0 },
12443     { "xend",           { Skip_MODRM }, 0 },
12444     { "xtest",          { Skip_MODRM }, 0 },
12445     { "enclu",          { Skip_MODRM }, 0 },
12446   },
12447   {
12448     /* RM_0F01_REG_3 */
12449     { "vmrun",          { Skip_MODRM }, 0 },
12450     { "vmmcall",        { Skip_MODRM }, 0 },
12451     { "vmload",         { Skip_MODRM }, 0 },
12452     { "vmsave",         { Skip_MODRM }, 0 },
12453     { "stgi",           { Skip_MODRM }, 0 },
12454     { "clgi",           { Skip_MODRM }, 0 },
12455     { "skinit",         { Skip_MODRM }, 0 },
12456     { "invlpga",        { Skip_MODRM }, 0 },
12457   },
12458   {
12459     /* RM_0F01_REG_5 */
12460     { Bad_Opcode },
12461     { Bad_Opcode },
12462     { Bad_Opcode },
12463     { Bad_Opcode },
12464     { Bad_Opcode },
12465     { Bad_Opcode },
12466     { "rdpkru",         { Skip_MODRM }, 0 },
12467     { "wrpkru",         { Skip_MODRM }, 0 },
12468   },
12469   {
12470     /* RM_0F01_REG_7 */
12471     { "swapgs",         { Skip_MODRM }, 0  },
12472     { "rdtscp",         { Skip_MODRM }, 0  },
12473     { "monitorx",       { { OP_Monitor, 0 } }, 0  },
12474     { "mwaitx",         { { OP_Mwaitx,  0 } }, 0  },
12475     { "clzero",         { Skip_MODRM }, 0  },
12476   },
12477   {
12478     /* RM_0FAE_REG_5 */
12479     { "lfence",         { Skip_MODRM }, 0 },
12480   },
12481   {
12482     /* RM_0FAE_REG_6 */
12483     { "mfence",         { Skip_MODRM }, 0 },
12484   },
12485   {
12486     /* RM_0FAE_REG_7 */
12487     { PREFIX_TABLE (PREFIX_RM_0_0FAE_REG_7) },
12488   },
12489 };
12490
12491 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
12492
12493 /* We use the high bit to indicate different name for the same
12494    prefix.  */
12495 #define REP_PREFIX      (0xf3 | 0x100)
12496 #define XACQUIRE_PREFIX (0xf2 | 0x200)
12497 #define XRELEASE_PREFIX (0xf3 | 0x400)
12498 #define BND_PREFIX      (0xf2 | 0x400)
12499
12500 static int
12501 ckprefix (void)
12502 {
12503   int newrex, i, length;
12504   rex = 0;
12505   rex_ignored = 0;
12506   prefixes = 0;
12507   used_prefixes = 0;
12508   rex_used = 0;
12509   last_lock_prefix = -1;
12510   last_repz_prefix = -1;
12511   last_repnz_prefix = -1;
12512   last_data_prefix = -1;
12513   last_addr_prefix = -1;
12514   last_rex_prefix = -1;
12515   last_seg_prefix = -1;
12516   fwait_prefix = -1;
12517   active_seg_prefix = 0;
12518   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12519     all_prefixes[i] = 0;
12520   i = 0;
12521   length = 0;
12522   /* The maximum instruction length is 15bytes.  */
12523   while (length < MAX_CODE_LENGTH - 1)
12524     {
12525       FETCH_DATA (the_info, codep + 1);
12526       newrex = 0;
12527       switch (*codep)
12528         {
12529         /* REX prefixes family.  */
12530         case 0x40:
12531         case 0x41:
12532         case 0x42:
12533         case 0x43:
12534         case 0x44:
12535         case 0x45:
12536         case 0x46:
12537         case 0x47:
12538         case 0x48:
12539         case 0x49:
12540         case 0x4a:
12541         case 0x4b:
12542         case 0x4c:
12543         case 0x4d:
12544         case 0x4e:
12545         case 0x4f:
12546           if (address_mode == mode_64bit)
12547             newrex = *codep;
12548           else
12549             return 1;
12550           last_rex_prefix = i;
12551           break;
12552         case 0xf3:
12553           prefixes |= PREFIX_REPZ;
12554           last_repz_prefix = i;
12555           break;
12556         case 0xf2:
12557           prefixes |= PREFIX_REPNZ;
12558           last_repnz_prefix = i;
12559           break;
12560         case 0xf0:
12561           prefixes |= PREFIX_LOCK;
12562           last_lock_prefix = i;
12563           break;
12564         case 0x2e:
12565           prefixes |= PREFIX_CS;
12566           last_seg_prefix = i;
12567           active_seg_prefix = PREFIX_CS;
12568           break;
12569         case 0x36:
12570           prefixes |= PREFIX_SS;
12571           last_seg_prefix = i;
12572           active_seg_prefix = PREFIX_SS;
12573           break;
12574         case 0x3e:
12575           prefixes |= PREFIX_DS;
12576           last_seg_prefix = i;
12577           active_seg_prefix = PREFIX_DS;
12578           break;
12579         case 0x26:
12580           prefixes |= PREFIX_ES;
12581           last_seg_prefix = i;
12582           active_seg_prefix = PREFIX_ES;
12583           break;
12584         case 0x64:
12585           prefixes |= PREFIX_FS;
12586           last_seg_prefix = i;
12587           active_seg_prefix = PREFIX_FS;
12588           break;
12589         case 0x65:
12590           prefixes |= PREFIX_GS;
12591           last_seg_prefix = i;
12592           active_seg_prefix = PREFIX_GS;
12593           break;
12594         case 0x66:
12595           prefixes |= PREFIX_DATA;
12596           last_data_prefix = i;
12597           break;
12598         case 0x67:
12599           prefixes |= PREFIX_ADDR;
12600           last_addr_prefix = i;
12601           break;
12602         case FWAIT_OPCODE:
12603           /* fwait is really an instruction.  If there are prefixes
12604              before the fwait, they belong to the fwait, *not* to the
12605              following instruction.  */
12606           fwait_prefix = i;
12607           if (prefixes || rex)
12608             {
12609               prefixes |= PREFIX_FWAIT;
12610               codep++;
12611               /* This ensures that the previous REX prefixes are noticed
12612                  as unused prefixes, as in the return case below.  */
12613               rex_used = rex;
12614               return 1;
12615             }
12616           prefixes = PREFIX_FWAIT;
12617           break;
12618         default:
12619           return 1;
12620         }
12621       /* Rex is ignored when followed by another prefix.  */
12622       if (rex)
12623         {
12624           rex_used = rex;
12625           return 1;
12626         }
12627       if (*codep != FWAIT_OPCODE)
12628         all_prefixes[i++] = *codep;
12629       rex = newrex;
12630       codep++;
12631       length++;
12632     }
12633   return 0;
12634 }
12635
12636 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
12637    prefix byte.  */
12638
12639 static const char *
12640 prefix_name (int pref, int sizeflag)
12641 {
12642   static const char *rexes [16] =
12643     {
12644       "rex",            /* 0x40 */
12645       "rex.B",          /* 0x41 */
12646       "rex.X",          /* 0x42 */
12647       "rex.XB",         /* 0x43 */
12648       "rex.R",          /* 0x44 */
12649       "rex.RB",         /* 0x45 */
12650       "rex.RX",         /* 0x46 */
12651       "rex.RXB",        /* 0x47 */
12652       "rex.W",          /* 0x48 */
12653       "rex.WB",         /* 0x49 */
12654       "rex.WX",         /* 0x4a */
12655       "rex.WXB",        /* 0x4b */
12656       "rex.WR",         /* 0x4c */
12657       "rex.WRB",        /* 0x4d */
12658       "rex.WRX",        /* 0x4e */
12659       "rex.WRXB",       /* 0x4f */
12660     };
12661
12662   switch (pref)
12663     {
12664     /* REX prefixes family.  */
12665     case 0x40:
12666     case 0x41:
12667     case 0x42:
12668     case 0x43:
12669     case 0x44:
12670     case 0x45:
12671     case 0x46:
12672     case 0x47:
12673     case 0x48:
12674     case 0x49:
12675     case 0x4a:
12676     case 0x4b:
12677     case 0x4c:
12678     case 0x4d:
12679     case 0x4e:
12680     case 0x4f:
12681       return rexes [pref - 0x40];
12682     case 0xf3:
12683       return "repz";
12684     case 0xf2:
12685       return "repnz";
12686     case 0xf0:
12687       return "lock";
12688     case 0x2e:
12689       return "cs";
12690     case 0x36:
12691       return "ss";
12692     case 0x3e:
12693       return "ds";
12694     case 0x26:
12695       return "es";
12696     case 0x64:
12697       return "fs";
12698     case 0x65:
12699       return "gs";
12700     case 0x66:
12701       return (sizeflag & DFLAG) ? "data16" : "data32";
12702     case 0x67:
12703       if (address_mode == mode_64bit)
12704         return (sizeflag & AFLAG) ? "addr32" : "addr64";
12705       else
12706         return (sizeflag & AFLAG) ? "addr16" : "addr32";
12707     case FWAIT_OPCODE:
12708       return "fwait";
12709     case REP_PREFIX:
12710       return "rep";
12711     case XACQUIRE_PREFIX:
12712       return "xacquire";
12713     case XRELEASE_PREFIX:
12714       return "xrelease";
12715     case BND_PREFIX:
12716       return "bnd";
12717     default:
12718       return NULL;
12719     }
12720 }
12721
12722 static char op_out[MAX_OPERANDS][100];
12723 static int op_ad, op_index[MAX_OPERANDS];
12724 static int two_source_ops;
12725 static bfd_vma op_address[MAX_OPERANDS];
12726 static bfd_vma op_riprel[MAX_OPERANDS];
12727 static bfd_vma start_pc;
12728
12729 /*
12730  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
12731  *   (see topic "Redundant prefixes" in the "Differences from 8086"
12732  *   section of the "Virtual 8086 Mode" chapter.)
12733  * 'pc' should be the address of this instruction, it will
12734  *   be used to print the target address if this is a relative jump or call
12735  * The function returns the length of this instruction in bytes.
12736  */
12737
12738 static char intel_syntax;
12739 static char intel_mnemonic = !SYSV386_COMPAT;
12740 static char open_char;
12741 static char close_char;
12742 static char separator_char;
12743 static char scale_char;
12744
12745 enum x86_64_isa
12746 {
12747   amd64 = 0,
12748   intel64
12749 };
12750
12751 static enum x86_64_isa isa64;
12752
12753 /* Here for backwards compatibility.  When gdb stops using
12754    print_insn_i386_att and print_insn_i386_intel these functions can
12755    disappear, and print_insn_i386 be merged into print_insn.  */
12756 int
12757 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
12758 {
12759   intel_syntax = 0;
12760
12761   return print_insn (pc, info);
12762 }
12763
12764 int
12765 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
12766 {
12767   intel_syntax = 1;
12768
12769   return print_insn (pc, info);
12770 }
12771
12772 int
12773 print_insn_i386 (bfd_vma pc, disassemble_info *info)
12774 {
12775   intel_syntax = -1;
12776
12777   return print_insn (pc, info);
12778 }
12779
12780 void
12781 print_i386_disassembler_options (FILE *stream)
12782 {
12783   fprintf (stream, _("\n\
12784 The following i386/x86-64 specific disassembler options are supported for use\n\
12785 with the -M switch (multiple options should be separated by commas):\n"));
12786
12787   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
12788   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
12789   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
12790   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
12791   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
12792   fprintf (stream, _("  att-mnemonic\n"
12793                      "              Display instruction in AT&T mnemonic\n"));
12794   fprintf (stream, _("  intel-mnemonic\n"
12795                      "              Display instruction in Intel mnemonic\n"));
12796   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
12797   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
12798   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
12799   fprintf (stream, _("  data32      Assume 32bit data size\n"));
12800   fprintf (stream, _("  data16      Assume 16bit data size\n"));
12801   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
12802   fprintf (stream, _("  amd64       Display instruction in AMD64 ISA\n"));
12803   fprintf (stream, _("  intel64     Display instruction in Intel64 ISA\n"));
12804 }
12805
12806 /* Bad opcode.  */
12807 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
12808
12809 /* Get a pointer to struct dis386 with a valid name.  */
12810
12811 static const struct dis386 *
12812 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
12813 {
12814   int vindex, vex_table_index;
12815
12816   if (dp->name != NULL)
12817     return dp;
12818
12819   switch (dp->op[0].bytemode)
12820     {
12821     case USE_REG_TABLE:
12822       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
12823       break;
12824
12825     case USE_MOD_TABLE:
12826       vindex = modrm.mod == 0x3 ? 1 : 0;
12827       dp = &mod_table[dp->op[1].bytemode][vindex];
12828       break;
12829
12830     case USE_RM_TABLE:
12831       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
12832       break;
12833
12834     case USE_PREFIX_TABLE:
12835       if (need_vex)
12836         {
12837           /* The prefix in VEX is implicit.  */
12838           switch (vex.prefix)
12839             {
12840             case 0:
12841               vindex = 0;
12842               break;
12843             case REPE_PREFIX_OPCODE:
12844               vindex = 1;
12845               break;
12846             case DATA_PREFIX_OPCODE:
12847               vindex = 2;
12848               break;
12849             case REPNE_PREFIX_OPCODE:
12850               vindex = 3;
12851               break;
12852             default:
12853               abort ();
12854               break;
12855             }
12856         }
12857       else
12858         {
12859           int last_prefix = -1;
12860           int prefix = 0;
12861           vindex = 0;
12862           /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
12863              When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
12864              last one wins.  */
12865           if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
12866             {
12867               if (last_repz_prefix > last_repnz_prefix)
12868                 {
12869                   vindex = 1;
12870                   prefix = PREFIX_REPZ;
12871                   last_prefix = last_repz_prefix;
12872                 }
12873               else
12874                 {
12875                   vindex = 3;
12876                   prefix = PREFIX_REPNZ;
12877                   last_prefix = last_repnz_prefix;
12878                 }
12879
12880               /* Check if prefix should be ignored.  */
12881               if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
12882                      & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
12883                    & prefix) != 0)
12884                 vindex = 0;
12885             }
12886
12887           if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
12888             {
12889               vindex = 2;
12890               prefix = PREFIX_DATA;
12891               last_prefix = last_data_prefix;
12892             }
12893
12894           if (vindex != 0)
12895             {
12896               used_prefixes |= prefix;
12897               all_prefixes[last_prefix] = 0;
12898             }
12899         }
12900       dp = &prefix_table[dp->op[1].bytemode][vindex];
12901       break;
12902
12903     case USE_X86_64_TABLE:
12904       vindex = address_mode == mode_64bit ? 1 : 0;
12905       dp = &x86_64_table[dp->op[1].bytemode][vindex];
12906       break;
12907
12908     case USE_3BYTE_TABLE:
12909       FETCH_DATA (info, codep + 2);
12910       vindex = *codep++;
12911       dp = &three_byte_table[dp->op[1].bytemode][vindex];
12912       end_codep = codep;
12913       modrm.mod = (*codep >> 6) & 3;
12914       modrm.reg = (*codep >> 3) & 7;
12915       modrm.rm = *codep & 7;
12916       break;
12917
12918     case USE_VEX_LEN_TABLE:
12919       if (!need_vex)
12920         abort ();
12921
12922       switch (vex.length)
12923         {
12924         case 128:
12925           vindex = 0;
12926           break;
12927         case 256:
12928           vindex = 1;
12929           break;
12930         default:
12931           abort ();
12932           break;
12933         }
12934
12935       dp = &vex_len_table[dp->op[1].bytemode][vindex];
12936       break;
12937
12938     case USE_XOP_8F_TABLE:
12939       FETCH_DATA (info, codep + 3);
12940       /* All bits in the REX prefix are ignored.  */
12941       rex_ignored = rex;
12942       rex = ~(*codep >> 5) & 0x7;
12943
12944       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
12945       switch ((*codep & 0x1f))
12946         {
12947         default:
12948           dp = &bad_opcode;
12949           return dp;
12950         case 0x8:
12951           vex_table_index = XOP_08;
12952           break;
12953         case 0x9:
12954           vex_table_index = XOP_09;
12955           break;
12956         case 0xa:
12957           vex_table_index = XOP_0A;
12958           break;
12959         }
12960       codep++;
12961       vex.w = *codep & 0x80;
12962       if (vex.w && address_mode == mode_64bit)
12963         rex |= REX_W;
12964
12965       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12966       if (address_mode != mode_64bit
12967           && vex.register_specifier > 0x7)
12968         {
12969           dp = &bad_opcode;
12970           return dp;
12971         }
12972
12973       vex.length = (*codep & 0x4) ? 256 : 128;
12974       switch ((*codep & 0x3))
12975         {
12976         case 0:
12977           vex.prefix = 0;
12978           break;
12979         case 1:
12980           vex.prefix = DATA_PREFIX_OPCODE;
12981           break;
12982         case 2:
12983           vex.prefix = REPE_PREFIX_OPCODE;
12984           break;
12985         case 3:
12986           vex.prefix = REPNE_PREFIX_OPCODE;
12987           break;
12988         }
12989       need_vex = 1;
12990       need_vex_reg = 1;
12991       codep++;
12992       vindex = *codep++;
12993       dp = &xop_table[vex_table_index][vindex];
12994
12995       end_codep = codep;
12996       FETCH_DATA (info, codep + 1);
12997       modrm.mod = (*codep >> 6) & 3;
12998       modrm.reg = (*codep >> 3) & 7;
12999       modrm.rm = *codep & 7;
13000       break;
13001
13002     case USE_VEX_C4_TABLE:
13003       /* VEX prefix.  */
13004       FETCH_DATA (info, codep + 3);
13005       /* All bits in the REX prefix are ignored.  */
13006       rex_ignored = rex;
13007       rex = ~(*codep >> 5) & 0x7;
13008       switch ((*codep & 0x1f))
13009         {
13010         default:
13011           dp = &bad_opcode;
13012           return dp;
13013         case 0x1:
13014           vex_table_index = VEX_0F;
13015           break;
13016         case 0x2:
13017           vex_table_index = VEX_0F38;
13018           break;
13019         case 0x3:
13020           vex_table_index = VEX_0F3A;
13021           break;
13022         }
13023       codep++;
13024       vex.w = *codep & 0x80;
13025       if (address_mode == mode_64bit)
13026         {
13027           if (vex.w)
13028             rex |= REX_W;
13029           vex.register_specifier = (~(*codep >> 3)) & 0xf;
13030         }
13031       else
13032         {
13033           /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
13034              is ignored, other REX bits are 0 and the highest bit in
13035              VEX.vvvv is also ignored.  */
13036           rex = 0;
13037           vex.register_specifier = (~(*codep >> 3)) & 0x7;
13038         }
13039       vex.length = (*codep & 0x4) ? 256 : 128;
13040       switch ((*codep & 0x3))
13041         {
13042         case 0:
13043           vex.prefix = 0;
13044           break;
13045         case 1:
13046           vex.prefix = DATA_PREFIX_OPCODE;
13047           break;
13048         case 2:
13049           vex.prefix = REPE_PREFIX_OPCODE;
13050           break;
13051         case 3:
13052           vex.prefix = REPNE_PREFIX_OPCODE;
13053           break;
13054         }
13055       need_vex = 1;
13056       need_vex_reg = 1;
13057       codep++;
13058       vindex = *codep++;
13059       dp = &vex_table[vex_table_index][vindex];
13060       end_codep = codep;
13061       /* There is no MODRM byte for VEX [82|77].  */
13062       if (vindex != 0x77 && vindex != 0x82)
13063         {
13064           FETCH_DATA (info, codep + 1);
13065           modrm.mod = (*codep >> 6) & 3;
13066           modrm.reg = (*codep >> 3) & 7;
13067           modrm.rm = *codep & 7;
13068         }
13069       break;
13070
13071     case USE_VEX_C5_TABLE:
13072       /* VEX prefix.  */
13073       FETCH_DATA (info, codep + 2);
13074       /* All bits in the REX prefix are ignored.  */
13075       rex_ignored = rex;
13076       rex = (*codep & 0x80) ? 0 : REX_R;
13077
13078       /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
13079          VEX.vvvv is 1.  */
13080       vex.register_specifier = (~(*codep >> 3)) & 0xf;
13081       vex.w = 0;
13082       vex.length = (*codep & 0x4) ? 256 : 128;
13083       switch ((*codep & 0x3))
13084         {
13085         case 0:
13086           vex.prefix = 0;
13087           break;
13088         case 1:
13089           vex.prefix = DATA_PREFIX_OPCODE;
13090           break;
13091         case 2:
13092           vex.prefix = REPE_PREFIX_OPCODE;
13093           break;
13094         case 3:
13095           vex.prefix = REPNE_PREFIX_OPCODE;
13096           break;
13097         }
13098       need_vex = 1;
13099       need_vex_reg = 1;
13100       codep++;
13101       vindex = *codep++;
13102       dp = &vex_table[dp->op[1].bytemode][vindex];
13103       end_codep = codep;
13104       /* There is no MODRM byte for VEX [82|77].  */
13105       if (vindex != 0x77 && vindex != 0x82)
13106         {
13107           FETCH_DATA (info, codep + 1);
13108           modrm.mod = (*codep >> 6) & 3;
13109           modrm.reg = (*codep >> 3) & 7;
13110           modrm.rm = *codep & 7;
13111         }
13112       break;
13113
13114     case USE_VEX_W_TABLE:
13115       if (!need_vex)
13116         abort ();
13117
13118       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
13119       break;
13120
13121     case USE_EVEX_TABLE:
13122       two_source_ops = 0;
13123       /* EVEX prefix.  */
13124       vex.evex = 1;
13125       FETCH_DATA (info, codep + 4);
13126       /* All bits in the REX prefix are ignored.  */
13127       rex_ignored = rex;
13128       /* The first byte after 0x62.  */
13129       rex = ~(*codep >> 5) & 0x7;
13130       vex.r = *codep & 0x10;
13131       switch ((*codep & 0xf))
13132         {
13133         default:
13134           return &bad_opcode;
13135         case 0x1:
13136           vex_table_index = EVEX_0F;
13137           break;
13138         case 0x2:
13139           vex_table_index = EVEX_0F38;
13140           break;
13141         case 0x3:
13142           vex_table_index = EVEX_0F3A;
13143           break;
13144         }
13145
13146       /* The second byte after 0x62.  */
13147       codep++;
13148       vex.w = *codep & 0x80;
13149       if (vex.w && address_mode == mode_64bit)
13150         rex |= REX_W;
13151
13152       vex.register_specifier = (~(*codep >> 3)) & 0xf;
13153       if (address_mode != mode_64bit)
13154         {
13155           /* In 16/32-bit mode silently ignore following bits.  */
13156           rex &= ~REX_B;
13157           vex.r = 1;
13158           vex.v = 1;
13159           vex.register_specifier &= 0x7;
13160         }
13161
13162       /* The U bit.  */
13163       if (!(*codep & 0x4))
13164         return &bad_opcode;
13165
13166       switch ((*codep & 0x3))
13167         {
13168         case 0:
13169           vex.prefix = 0;
13170           break;
13171         case 1:
13172           vex.prefix = DATA_PREFIX_OPCODE;
13173           break;
13174         case 2:
13175           vex.prefix = REPE_PREFIX_OPCODE;
13176           break;
13177         case 3:
13178           vex.prefix = REPNE_PREFIX_OPCODE;
13179           break;
13180         }
13181
13182       /* The third byte after 0x62.  */
13183       codep++;
13184
13185       /* Remember the static rounding bits.  */
13186       vex.ll = (*codep >> 5) & 3;
13187       vex.b = (*codep & 0x10) != 0;
13188
13189       vex.v = *codep & 0x8;
13190       vex.mask_register_specifier = *codep & 0x7;
13191       vex.zeroing = *codep & 0x80;
13192
13193       need_vex = 1;
13194       need_vex_reg = 1;
13195       codep++;
13196       vindex = *codep++;
13197       dp = &evex_table[vex_table_index][vindex];
13198       end_codep = codep;
13199       FETCH_DATA (info, codep + 1);
13200       modrm.mod = (*codep >> 6) & 3;
13201       modrm.reg = (*codep >> 3) & 7;
13202       modrm.rm = *codep & 7;
13203
13204       /* Set vector length.  */
13205       if (modrm.mod == 3 && vex.b)
13206         vex.length = 512;
13207       else
13208         {
13209           switch (vex.ll)
13210             {
13211             case 0x0:
13212               vex.length = 128;
13213               break;
13214             case 0x1:
13215               vex.length = 256;
13216               break;
13217             case 0x2:
13218               vex.length = 512;
13219               break;
13220             default:
13221               return &bad_opcode;
13222             }
13223         }
13224       break;
13225
13226     case 0:
13227       dp = &bad_opcode;
13228       break;
13229
13230     default:
13231       abort ();
13232     }
13233
13234   if (dp->name != NULL)
13235     return dp;
13236   else
13237     return get_valid_dis386 (dp, info);
13238 }
13239
13240 static void
13241 get_sib (disassemble_info *info, int sizeflag)
13242 {
13243   /* If modrm.mod == 3, operand must be register.  */
13244   if (need_modrm
13245       && ((sizeflag & AFLAG) || address_mode == mode_64bit)
13246       && modrm.mod != 3
13247       && modrm.rm == 4)
13248     {
13249       FETCH_DATA (info, codep + 2);
13250       sib.index = (codep [1] >> 3) & 7;
13251       sib.scale = (codep [1] >> 6) & 3;
13252       sib.base = codep [1] & 7;
13253     }
13254 }
13255
13256 static int
13257 print_insn (bfd_vma pc, disassemble_info *info)
13258 {
13259   const struct dis386 *dp;
13260   int i;
13261   char *op_txt[MAX_OPERANDS];
13262   int needcomma;
13263   int sizeflag, orig_sizeflag;
13264   const char *p;
13265   struct dis_private priv;
13266   int prefix_length;
13267
13268   priv.orig_sizeflag = AFLAG | DFLAG;
13269   if ((info->mach & bfd_mach_i386_i386) != 0)
13270     address_mode = mode_32bit;
13271   else if (info->mach == bfd_mach_i386_i8086)
13272     {
13273       address_mode = mode_16bit;
13274       priv.orig_sizeflag = 0;
13275     }
13276   else
13277     address_mode = mode_64bit;
13278
13279   if (intel_syntax == (char) -1)
13280     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
13281
13282   for (p = info->disassembler_options; p != NULL; )
13283     {
13284       if (CONST_STRNEQ (p, "amd64"))
13285         isa64 = amd64;
13286       else if (CONST_STRNEQ (p, "intel64"))
13287         isa64 = intel64;
13288       else if (CONST_STRNEQ (p, "x86-64"))
13289         {
13290           address_mode = mode_64bit;
13291           priv.orig_sizeflag = AFLAG | DFLAG;
13292         }
13293       else if (CONST_STRNEQ (p, "i386"))
13294         {
13295           address_mode = mode_32bit;
13296           priv.orig_sizeflag = AFLAG | DFLAG;
13297         }
13298       else if (CONST_STRNEQ (p, "i8086"))
13299         {
13300           address_mode = mode_16bit;
13301           priv.orig_sizeflag = 0;
13302         }
13303       else if (CONST_STRNEQ (p, "intel"))
13304         {
13305           intel_syntax = 1;
13306           if (CONST_STRNEQ (p + 5, "-mnemonic"))
13307             intel_mnemonic = 1;
13308         }
13309       else if (CONST_STRNEQ (p, "att"))
13310         {
13311           intel_syntax = 0;
13312           if (CONST_STRNEQ (p + 3, "-mnemonic"))
13313             intel_mnemonic = 0;
13314         }
13315       else if (CONST_STRNEQ (p, "addr"))
13316         {
13317           if (address_mode == mode_64bit)
13318             {
13319               if (p[4] == '3' && p[5] == '2')
13320                 priv.orig_sizeflag &= ~AFLAG;
13321               else if (p[4] == '6' && p[5] == '4')
13322                 priv.orig_sizeflag |= AFLAG;
13323             }
13324           else
13325             {
13326               if (p[4] == '1' && p[5] == '6')
13327                 priv.orig_sizeflag &= ~AFLAG;
13328               else if (p[4] == '3' && p[5] == '2')
13329                 priv.orig_sizeflag |= AFLAG;
13330             }
13331         }
13332       else if (CONST_STRNEQ (p, "data"))
13333         {
13334           if (p[4] == '1' && p[5] == '6')
13335             priv.orig_sizeflag &= ~DFLAG;
13336           else if (p[4] == '3' && p[5] == '2')
13337             priv.orig_sizeflag |= DFLAG;
13338         }
13339       else if (CONST_STRNEQ (p, "suffix"))
13340         priv.orig_sizeflag |= SUFFIX_ALWAYS;
13341
13342       p = strchr (p, ',');
13343       if (p != NULL)
13344         p++;
13345     }
13346
13347   if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
13348     {
13349       (*info->fprintf_func) (info->stream,
13350                              _("64-bit address is disabled"));
13351       return -1;
13352     }
13353
13354   if (intel_syntax)
13355     {
13356       names64 = intel_names64;
13357       names32 = intel_names32;
13358       names16 = intel_names16;
13359       names8 = intel_names8;
13360       names8rex = intel_names8rex;
13361       names_seg = intel_names_seg;
13362       names_mm = intel_names_mm;
13363       names_bnd = intel_names_bnd;
13364       names_xmm = intel_names_xmm;
13365       names_ymm = intel_names_ymm;
13366       names_zmm = intel_names_zmm;
13367       index64 = intel_index64;
13368       index32 = intel_index32;
13369       names_mask = intel_names_mask;
13370       index16 = intel_index16;
13371       open_char = '[';
13372       close_char = ']';
13373       separator_char = '+';
13374       scale_char = '*';
13375     }
13376   else
13377     {
13378       names64 = att_names64;
13379       names32 = att_names32;
13380       names16 = att_names16;
13381       names8 = att_names8;
13382       names8rex = att_names8rex;
13383       names_seg = att_names_seg;
13384       names_mm = att_names_mm;
13385       names_bnd = att_names_bnd;
13386       names_xmm = att_names_xmm;
13387       names_ymm = att_names_ymm;
13388       names_zmm = att_names_zmm;
13389       index64 = att_index64;
13390       index32 = att_index32;
13391       names_mask = att_names_mask;
13392       index16 = att_index16;
13393       open_char = '(';
13394       close_char =  ')';
13395       separator_char = ',';
13396       scale_char = ',';
13397     }
13398
13399   /* The output looks better if we put 7 bytes on a line, since that
13400      puts most long word instructions on a single line.  Use 8 bytes
13401      for Intel L1OM.  */
13402   if ((info->mach & bfd_mach_l1om) != 0)
13403     info->bytes_per_line = 8;
13404   else
13405     info->bytes_per_line = 7;
13406
13407   info->private_data = &priv;
13408   priv.max_fetched = priv.the_buffer;
13409   priv.insn_start = pc;
13410
13411   obuf[0] = 0;
13412   for (i = 0; i < MAX_OPERANDS; ++i)
13413     {
13414       op_out[i][0] = 0;
13415       op_index[i] = -1;
13416     }
13417
13418   the_info = info;
13419   start_pc = pc;
13420   start_codep = priv.the_buffer;
13421   codep = priv.the_buffer;
13422
13423   if (OPCODES_SIGSETJMP (priv.bailout) != 0)
13424     {
13425       const char *name;
13426
13427       /* Getting here means we tried for data but didn't get it.  That
13428          means we have an incomplete instruction of some sort.  Just
13429          print the first byte as a prefix or a .byte pseudo-op.  */
13430       if (codep > priv.the_buffer)
13431         {
13432           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
13433           if (name != NULL)
13434             (*info->fprintf_func) (info->stream, "%s", name);
13435           else
13436             {
13437               /* Just print the first byte as a .byte instruction.  */
13438               (*info->fprintf_func) (info->stream, ".byte 0x%x",
13439                                      (unsigned int) priv.the_buffer[0]);
13440             }
13441
13442           return 1;
13443         }
13444
13445       return -1;
13446     }
13447
13448   obufp = obuf;
13449   sizeflag = priv.orig_sizeflag;
13450
13451   if (!ckprefix () || rex_used)
13452     {
13453       /* Too many prefixes or unused REX prefixes.  */
13454       for (i = 0;
13455            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
13456            i++)
13457         (*info->fprintf_func) (info->stream, "%s%s",
13458                                i == 0 ? "" : " ",
13459                                prefix_name (all_prefixes[i], sizeflag));
13460       return i;
13461     }
13462
13463   insn_codep = codep;
13464
13465   FETCH_DATA (info, codep + 1);
13466   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
13467
13468   if (((prefixes & PREFIX_FWAIT)
13469        && ((*codep < 0xd8) || (*codep > 0xdf))))
13470     {
13471       /* Handle prefixes before fwait.  */
13472       for (i = 0; i < fwait_prefix && all_prefixes[i];
13473            i++)
13474         (*info->fprintf_func) (info->stream, "%s ",
13475                                prefix_name (all_prefixes[i], sizeflag));
13476       (*info->fprintf_func) (info->stream, "fwait");
13477       return i + 1;
13478     }
13479
13480   if (*codep == 0x0f)
13481     {
13482       unsigned char threebyte;
13483
13484       codep++;
13485       FETCH_DATA (info, codep + 1);
13486       threebyte = *codep;
13487       dp = &dis386_twobyte[threebyte];
13488       need_modrm = twobyte_has_modrm[*codep];
13489       codep++;
13490     }
13491   else
13492     {
13493       dp = &dis386[*codep];
13494       need_modrm = onebyte_has_modrm[*codep];
13495       codep++;
13496     }
13497
13498   /* Save sizeflag for printing the extra prefixes later before updating
13499      it for mnemonic and operand processing.  The prefix names depend
13500      only on the address mode.  */
13501   orig_sizeflag = sizeflag;
13502   if (prefixes & PREFIX_ADDR)
13503     sizeflag ^= AFLAG;
13504   if ((prefixes & PREFIX_DATA))
13505     sizeflag ^= DFLAG;
13506
13507   end_codep = codep;
13508   if (need_modrm)
13509     {
13510       FETCH_DATA (info, codep + 1);
13511       modrm.mod = (*codep >> 6) & 3;
13512       modrm.reg = (*codep >> 3) & 7;
13513       modrm.rm = *codep & 7;
13514     }
13515
13516   need_vex = 0;
13517   need_vex_reg = 0;
13518   vex_w_done = 0;
13519   vex.evex = 0;
13520
13521   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
13522     {
13523       get_sib (info, sizeflag);
13524       dofloat (sizeflag);
13525     }
13526   else
13527     {
13528       dp = get_valid_dis386 (dp, info);
13529       if (dp != NULL && putop (dp->name, sizeflag) == 0)
13530         {
13531           get_sib (info, sizeflag);
13532           for (i = 0; i < MAX_OPERANDS; ++i)
13533             {
13534               obufp = op_out[i];
13535               op_ad = MAX_OPERANDS - 1 - i;
13536               if (dp->op[i].rtn)
13537                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
13538               /* For EVEX instruction after the last operand masking
13539                  should be printed.  */
13540               if (i == 0 && vex.evex)
13541                 {
13542                   /* Don't print {%k0}.  */
13543                   if (vex.mask_register_specifier)
13544                     {
13545                       oappend ("{");
13546                       oappend (names_mask[vex.mask_register_specifier]);
13547                       oappend ("}");
13548                     }
13549                   if (vex.zeroing)
13550                     oappend ("{z}");
13551                 }
13552             }
13553         }
13554     }
13555
13556   /* Check if the REX prefix is used.  */
13557   if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)
13558     all_prefixes[last_rex_prefix] = 0;
13559
13560   /* Check if the SEG prefix is used.  */
13561   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
13562                    | PREFIX_FS | PREFIX_GS)) != 0
13563       && (used_prefixes & active_seg_prefix) != 0)
13564     all_prefixes[last_seg_prefix] = 0;
13565
13566   /* Check if the ADDR prefix is used.  */
13567   if ((prefixes & PREFIX_ADDR) != 0
13568       && (used_prefixes & PREFIX_ADDR) != 0)
13569     all_prefixes[last_addr_prefix] = 0;
13570
13571   /* Check if the DATA prefix is used.  */
13572   if ((prefixes & PREFIX_DATA) != 0
13573       && (used_prefixes & PREFIX_DATA) != 0)
13574     all_prefixes[last_data_prefix] = 0;
13575
13576   /* Print the extra prefixes.  */
13577   prefix_length = 0;
13578   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
13579     if (all_prefixes[i])
13580       {
13581         const char *name;
13582         name = prefix_name (all_prefixes[i], orig_sizeflag);
13583         if (name == NULL)
13584           abort ();
13585         prefix_length += strlen (name) + 1;
13586         (*info->fprintf_func) (info->stream, "%s ", name);
13587       }
13588
13589   /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
13590      unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
13591      used by putop and MMX/SSE operand and may be overriden by the
13592      PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
13593      separately.  */
13594   if (dp->prefix_requirement == PREFIX_OPCODE
13595       && dp != &bad_opcode
13596       && (((prefixes
13597             & (PREFIX_REPZ | PREFIX_REPNZ)) != 0
13598            && (used_prefixes
13599                & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
13600           || ((((prefixes
13601                  & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
13602                 == PREFIX_DATA)
13603                && (used_prefixes & PREFIX_DATA) == 0))))
13604     {
13605       (*info->fprintf_func) (info->stream, "(bad)");
13606       return end_codep - priv.the_buffer;
13607     }
13608
13609   /* Check maximum code length.  */
13610   if ((codep - start_codep) > MAX_CODE_LENGTH)
13611     {
13612       (*info->fprintf_func) (info->stream, "(bad)");
13613       return MAX_CODE_LENGTH;
13614     }
13615
13616   obufp = mnemonicendp;
13617   for (i = strlen (obuf) + prefix_length; i < 6; i++)
13618     oappend (" ");
13619   oappend (" ");
13620   (*info->fprintf_func) (info->stream, "%s", obuf);
13621
13622   /* The enter and bound instructions are printed with operands in the same
13623      order as the intel book; everything else is printed in reverse order.  */
13624   if (intel_syntax || two_source_ops)
13625     {
13626       bfd_vma riprel;
13627
13628       for (i = 0; i < MAX_OPERANDS; ++i)
13629         op_txt[i] = op_out[i];
13630
13631       if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
13632           && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
13633         {
13634           op_txt[2] = op_out[3];
13635           op_txt[3] = op_out[2];
13636         }
13637
13638       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
13639         {
13640           op_ad = op_index[i];
13641           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
13642           op_index[MAX_OPERANDS - 1 - i] = op_ad;
13643           riprel = op_riprel[i];
13644           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
13645           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
13646         }
13647     }
13648   else
13649     {
13650       for (i = 0; i < MAX_OPERANDS; ++i)
13651         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
13652     }
13653
13654   needcomma = 0;
13655   for (i = 0; i < MAX_OPERANDS; ++i)
13656     if (*op_txt[i])
13657       {
13658         if (needcomma)
13659           (*info->fprintf_func) (info->stream, ",");
13660         if (op_index[i] != -1 && !op_riprel[i])
13661           (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
13662         else
13663           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
13664         needcomma = 1;
13665       }
13666
13667   for (i = 0; i < MAX_OPERANDS; i++)
13668     if (op_index[i] != -1 && op_riprel[i])
13669       {
13670         (*info->fprintf_func) (info->stream, "        # ");
13671         (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
13672                                                 + op_address[op_index[i]]), info);
13673         break;
13674       }
13675   return codep - priv.the_buffer;
13676 }
13677
13678 static const char *float_mem[] = {
13679   /* d8 */
13680   "fadd{s|}",
13681   "fmul{s|}",
13682   "fcom{s|}",
13683   "fcomp{s|}",
13684   "fsub{s|}",
13685   "fsubr{s|}",
13686   "fdiv{s|}",
13687   "fdivr{s|}",
13688   /* d9 */
13689   "fld{s|}",
13690   "(bad)",
13691   "fst{s|}",
13692   "fstp{s|}",
13693   "fldenvIC",
13694   "fldcw",
13695   "fNstenvIC",
13696   "fNstcw",
13697   /* da */
13698   "fiadd{l|}",
13699   "fimul{l|}",
13700   "ficom{l|}",
13701   "ficomp{l|}",
13702   "fisub{l|}",
13703   "fisubr{l|}",
13704   "fidiv{l|}",
13705   "fidivr{l|}",
13706   /* db */
13707   "fild{l|}",
13708   "fisttp{l|}",
13709   "fist{l|}",
13710   "fistp{l|}",
13711   "(bad)",
13712   "fld{t||t|}",
13713   "(bad)",
13714   "fstp{t||t|}",
13715   /* dc */
13716   "fadd{l|}",
13717   "fmul{l|}",
13718   "fcom{l|}",
13719   "fcomp{l|}",
13720   "fsub{l|}",
13721   "fsubr{l|}",
13722   "fdiv{l|}",
13723   "fdivr{l|}",
13724   /* dd */
13725   "fld{l|}",
13726   "fisttp{ll|}",
13727   "fst{l||}",
13728   "fstp{l|}",
13729   "frstorIC",
13730   "(bad)",
13731   "fNsaveIC",
13732   "fNstsw",
13733   /* de */
13734   "fiadd",
13735   "fimul",
13736   "ficom",
13737   "ficomp",
13738   "fisub",
13739   "fisubr",
13740   "fidiv",
13741   "fidivr",
13742   /* df */
13743   "fild",
13744   "fisttp",
13745   "fist",
13746   "fistp",
13747   "fbld",
13748   "fild{ll|}",
13749   "fbstp",
13750   "fistp{ll|}",
13751 };
13752
13753 static const unsigned char float_mem_mode[] = {
13754   /* d8 */
13755   d_mode,
13756   d_mode,
13757   d_mode,
13758   d_mode,
13759   d_mode,
13760   d_mode,
13761   d_mode,
13762   d_mode,
13763   /* d9 */
13764   d_mode,
13765   0,
13766   d_mode,
13767   d_mode,
13768   0,
13769   w_mode,
13770   0,
13771   w_mode,
13772   /* da */
13773   d_mode,
13774   d_mode,
13775   d_mode,
13776   d_mode,
13777   d_mode,
13778   d_mode,
13779   d_mode,
13780   d_mode,
13781   /* db */
13782   d_mode,
13783   d_mode,
13784   d_mode,
13785   d_mode,
13786   0,
13787   t_mode,
13788   0,
13789   t_mode,
13790   /* dc */
13791   q_mode,
13792   q_mode,
13793   q_mode,
13794   q_mode,
13795   q_mode,
13796   q_mode,
13797   q_mode,
13798   q_mode,
13799   /* dd */
13800   q_mode,
13801   q_mode,
13802   q_mode,
13803   q_mode,
13804   0,
13805   0,
13806   0,
13807   w_mode,
13808   /* de */
13809   w_mode,
13810   w_mode,
13811   w_mode,
13812   w_mode,
13813   w_mode,
13814   w_mode,
13815   w_mode,
13816   w_mode,
13817   /* df */
13818   w_mode,
13819   w_mode,
13820   w_mode,
13821   w_mode,
13822   t_mode,
13823   q_mode,
13824   t_mode,
13825   q_mode
13826 };
13827
13828 #define ST { OP_ST, 0 }
13829 #define STi { OP_STi, 0 }
13830
13831 #define FGRPd9_2 NULL, { { NULL, 0 } }, 0
13832 #define FGRPd9_4 NULL, { { NULL, 1 } }, 0
13833 #define FGRPd9_5 NULL, { { NULL, 2 } }, 0
13834 #define FGRPd9_6 NULL, { { NULL, 3 } }, 0
13835 #define FGRPd9_7 NULL, { { NULL, 4 } }, 0
13836 #define FGRPda_5 NULL, { { NULL, 5 } }, 0
13837 #define FGRPdb_4 NULL, { { NULL, 6 } }, 0
13838 #define FGRPde_3 NULL, { { NULL, 7 } }, 0
13839 #define FGRPdf_4 NULL, { { NULL, 8 } }, 0
13840
13841 static const struct dis386 float_reg[][8] = {
13842   /* d8 */
13843   {
13844     { "fadd",   { ST, STi }, 0 },
13845     { "fmul",   { ST, STi }, 0 },
13846     { "fcom",   { STi }, 0 },
13847     { "fcomp",  { STi }, 0 },
13848     { "fsub",   { ST, STi }, 0 },
13849     { "fsubr",  { ST, STi }, 0 },
13850     { "fdiv",   { ST, STi }, 0 },
13851     { "fdivr",  { ST, STi }, 0 },
13852   },
13853   /* d9 */
13854   {
13855     { "fld",    { STi }, 0 },
13856     { "fxch",   { STi }, 0 },
13857     { FGRPd9_2 },
13858     { Bad_Opcode },
13859     { FGRPd9_4 },
13860     { FGRPd9_5 },
13861     { FGRPd9_6 },
13862     { FGRPd9_7 },
13863   },
13864   /* da */
13865   {
13866     { "fcmovb", { ST, STi }, 0 },
13867     { "fcmove", { ST, STi }, 0 },
13868     { "fcmovbe",{ ST, STi }, 0 },
13869     { "fcmovu", { ST, STi }, 0 },
13870     { Bad_Opcode },
13871     { FGRPda_5 },
13872     { Bad_Opcode },
13873     { Bad_Opcode },
13874   },
13875   /* db */
13876   {
13877     { "fcmovnb",{ ST, STi }, 0 },
13878     { "fcmovne",{ ST, STi }, 0 },
13879     { "fcmovnbe",{ ST, STi }, 0 },
13880     { "fcmovnu",{ ST, STi }, 0 },
13881     { FGRPdb_4 },
13882     { "fucomi", { ST, STi }, 0 },
13883     { "fcomi",  { ST, STi }, 0 },
13884     { Bad_Opcode },
13885   },
13886   /* dc */
13887   {
13888     { "fadd",   { STi, ST }, 0 },
13889     { "fmul",   { STi, ST }, 0 },
13890     { Bad_Opcode },
13891     { Bad_Opcode },
13892     { "fsub!M", { STi, ST }, 0 },
13893     { "fsubM",  { STi, ST }, 0 },
13894     { "fdiv!M", { STi, ST }, 0 },
13895     { "fdivM",  { STi, ST }, 0 },
13896   },
13897   /* dd */
13898   {
13899     { "ffree",  { STi }, 0 },
13900     { Bad_Opcode },
13901     { "fst",    { STi }, 0 },
13902     { "fstp",   { STi }, 0 },
13903     { "fucom",  { STi }, 0 },
13904     { "fucomp", { STi }, 0 },
13905     { Bad_Opcode },
13906     { Bad_Opcode },
13907   },
13908   /* de */
13909   {
13910     { "faddp",  { STi, ST }, 0 },
13911     { "fmulp",  { STi, ST }, 0 },
13912     { Bad_Opcode },
13913     { FGRPde_3 },
13914     { "fsub!Mp", { STi, ST }, 0 },
13915     { "fsubMp", { STi, ST }, 0 },
13916     { "fdiv!Mp", { STi, ST }, 0 },
13917     { "fdivMp", { STi, ST }, 0 },
13918   },
13919   /* df */
13920   {
13921     { "ffreep", { STi }, 0 },
13922     { Bad_Opcode },
13923     { Bad_Opcode },
13924     { Bad_Opcode },
13925     { FGRPdf_4 },
13926     { "fucomip", { ST, STi }, 0 },
13927     { "fcomip", { ST, STi }, 0 },
13928     { Bad_Opcode },
13929   },
13930 };
13931
13932 static char *fgrps[][8] = {
13933   /* d9_2  0 */
13934   {
13935     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13936   },
13937
13938   /* d9_4  1 */
13939   {
13940     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
13941   },
13942
13943   /* d9_5  2 */
13944   {
13945     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
13946   },
13947
13948   /* d9_6  3 */
13949   {
13950     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
13951   },
13952
13953   /* d9_7  4 */
13954   {
13955     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
13956   },
13957
13958   /* da_5  5 */
13959   {
13960     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13961   },
13962
13963   /* db_4  6 */
13964   {
13965     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
13966     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
13967   },
13968
13969   /* de_3  7 */
13970   {
13971     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13972   },
13973
13974   /* df_4  8 */
13975   {
13976     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13977   },
13978 };
13979
13980 static void
13981 swap_operand (void)
13982 {
13983   mnemonicendp[0] = '.';
13984   mnemonicendp[1] = 's';
13985   mnemonicendp += 2;
13986 }
13987
13988 static void
13989 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
13990                int sizeflag ATTRIBUTE_UNUSED)
13991 {
13992   /* Skip mod/rm byte.  */
13993   MODRM_CHECK;
13994   codep++;
13995 }
13996
13997 static void
13998 dofloat (int sizeflag)
13999 {
14000   const struct dis386 *dp;
14001   unsigned char floatop;
14002
14003   floatop = codep[-1];
14004
14005   if (modrm.mod != 3)
14006     {
14007       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
14008
14009       putop (float_mem[fp_indx], sizeflag);
14010       obufp = op_out[0];
14011       op_ad = 2;
14012       OP_E (float_mem_mode[fp_indx], sizeflag);
14013       return;
14014     }
14015   /* Skip mod/rm byte.  */
14016   MODRM_CHECK;
14017   codep++;
14018
14019   dp = &float_reg[floatop - 0xd8][modrm.reg];
14020   if (dp->name == NULL)
14021     {
14022       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
14023
14024       /* Instruction fnstsw is only one with strange arg.  */
14025       if (floatop == 0xdf && codep[-1] == 0xe0)
14026         strcpy (op_out[0], names16[0]);
14027     }
14028   else
14029     {
14030       putop (dp->name, sizeflag);
14031
14032       obufp = op_out[0];
14033       op_ad = 2;
14034       if (dp->op[0].rtn)
14035         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
14036
14037       obufp = op_out[1];
14038       op_ad = 1;
14039       if (dp->op[1].rtn)
14040         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
14041     }
14042 }
14043
14044 /* Like oappend (below), but S is a string starting with '%'.
14045    In Intel syntax, the '%' is elided.  */
14046 static void
14047 oappend_maybe_intel (const char *s)
14048 {
14049   oappend (s + intel_syntax);
14050 }
14051
14052 static void
14053 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14054 {
14055   oappend_maybe_intel ("%st");
14056 }
14057
14058 static void
14059 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14060 {
14061   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
14062   oappend_maybe_intel (scratchbuf);
14063 }
14064
14065 /* Capital letters in template are macros.  */
14066 static int
14067 putop (const char *in_template, int sizeflag)
14068 {
14069   const char *p;
14070   int alt = 0;
14071   int cond = 1;
14072   unsigned int l = 0, len = 1;
14073   char last[4];
14074
14075 #define SAVE_LAST(c)                    \
14076   if (l < len && l < sizeof (last))     \
14077     last[l++] = c;                      \
14078   else                                  \
14079     abort ();
14080
14081   for (p = in_template; *p; p++)
14082     {
14083       switch (*p)
14084         {
14085         default:
14086           *obufp++ = *p;
14087           break;
14088         case '%':
14089           len++;
14090           break;
14091         case '!':
14092           cond = 0;
14093           break;
14094         case '{':
14095           if (intel_syntax)
14096             {
14097               while (*++p != '|')
14098                 if (*p == '}' || *p == '\0')
14099                   abort ();
14100             }
14101           /* Fall through.  */
14102         case 'I':
14103           alt = 1;
14104           continue;
14105         case '|':
14106           while (*++p != '}')
14107             {
14108               if (*p == '\0')
14109                 abort ();
14110             }
14111           break;
14112         case '}':
14113           break;
14114         case 'A':
14115           if (intel_syntax)
14116             break;
14117           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
14118             *obufp++ = 'b';
14119           break;
14120         case 'B':
14121           if (l == 0 && len == 1)
14122             {
14123 case_B:
14124               if (intel_syntax)
14125                 break;
14126               if (sizeflag & SUFFIX_ALWAYS)
14127                 *obufp++ = 'b';
14128             }
14129           else
14130             {
14131               if (l != 1
14132                   || len != 2
14133                   || last[0] != 'L')
14134                 {
14135                   SAVE_LAST (*p);
14136                   break;
14137                 }
14138
14139               if (address_mode == mode_64bit
14140                   && !(prefixes & PREFIX_ADDR))
14141                 {
14142                   *obufp++ = 'a';
14143                   *obufp++ = 'b';
14144                   *obufp++ = 's';
14145                 }
14146
14147               goto case_B;
14148             }
14149           break;
14150         case 'C':
14151           if (intel_syntax && !alt)
14152             break;
14153           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
14154             {
14155               if (sizeflag & DFLAG)
14156                 *obufp++ = intel_syntax ? 'd' : 'l';
14157               else
14158                 *obufp++ = intel_syntax ? 'w' : 's';
14159               used_prefixes |= (prefixes & PREFIX_DATA);
14160             }
14161           break;
14162         case 'D':
14163           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
14164             break;
14165           USED_REX (REX_W);
14166           if (modrm.mod == 3)
14167             {
14168               if (rex & REX_W)
14169                 *obufp++ = 'q';
14170               else
14171                 {
14172                   if (sizeflag & DFLAG)
14173                     *obufp++ = intel_syntax ? 'd' : 'l';
14174                   else
14175                     *obufp++ = 'w';
14176                   used_prefixes |= (prefixes & PREFIX_DATA);
14177                 }
14178             }
14179           else
14180             *obufp++ = 'w';
14181           break;
14182         case 'E':               /* For jcxz/jecxz */
14183           if (address_mode == mode_64bit)
14184             {
14185               if (sizeflag & AFLAG)
14186                 *obufp++ = 'r';
14187               else
14188                 *obufp++ = 'e';
14189             }
14190           else
14191             if (sizeflag & AFLAG)
14192               *obufp++ = 'e';
14193           used_prefixes |= (prefixes & PREFIX_ADDR);
14194           break;
14195         case 'F':
14196           if (intel_syntax)
14197             break;
14198           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
14199             {
14200               if (sizeflag & AFLAG)
14201                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
14202               else
14203                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
14204               used_prefixes |= (prefixes & PREFIX_ADDR);
14205             }
14206           break;
14207         case 'G':
14208           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
14209             break;
14210           if ((rex & REX_W) || (sizeflag & DFLAG))
14211             *obufp++ = 'l';
14212           else
14213             *obufp++ = 'w';
14214           if (!(rex & REX_W))
14215             used_prefixes |= (prefixes & PREFIX_DATA);
14216           break;
14217         case 'H':
14218           if (intel_syntax)
14219             break;
14220           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
14221               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
14222             {
14223               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
14224               *obufp++ = ',';
14225               *obufp++ = 'p';
14226               if (prefixes & PREFIX_DS)
14227                 *obufp++ = 't';
14228               else
14229                 *obufp++ = 'n';
14230             }
14231           break;
14232         case 'J':
14233           if (intel_syntax)
14234             break;
14235           *obufp++ = 'l';
14236           break;
14237         case 'K':
14238           USED_REX (REX_W);
14239           if (rex & REX_W)
14240             *obufp++ = 'q';
14241           else
14242             *obufp++ = 'd';
14243           break;
14244         case 'Z':
14245           if (l != 0 || len != 1)
14246             {
14247               if (l != 1 || len != 2 || last[0] != 'X')
14248                 {
14249                   SAVE_LAST (*p);
14250                   break;
14251                 }
14252               if (!need_vex || !vex.evex)
14253                 abort ();
14254               if (intel_syntax
14255                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
14256                 break;
14257               switch (vex.length)
14258                 {
14259                 case 128:
14260                   *obufp++ = 'x';
14261                   break;
14262                 case 256:
14263                   *obufp++ = 'y';
14264                   break;
14265                 case 512:
14266                   *obufp++ = 'z';
14267                   break;
14268                 default:
14269                   abort ();
14270                 }
14271               break;
14272             }
14273           if (intel_syntax)
14274             break;
14275           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
14276             {
14277               *obufp++ = 'q';
14278               break;
14279             }
14280           /* Fall through.  */
14281           goto case_L;
14282         case 'L':
14283           if (l != 0 || len != 1)
14284             {
14285               SAVE_LAST (*p);
14286               break;
14287             }
14288 case_L:
14289           if (intel_syntax)
14290             break;
14291           if (sizeflag & SUFFIX_ALWAYS)
14292             *obufp++ = 'l';
14293           break;
14294         case 'M':
14295           if (intel_mnemonic != cond)
14296             *obufp++ = 'r';
14297           break;
14298         case 'N':
14299           if ((prefixes & PREFIX_FWAIT) == 0)
14300             *obufp++ = 'n';
14301           else
14302             used_prefixes |= PREFIX_FWAIT;
14303           break;
14304         case 'O':
14305           USED_REX (REX_W);
14306           if (rex & REX_W)
14307             *obufp++ = 'o';
14308           else if (intel_syntax && (sizeflag & DFLAG))
14309             *obufp++ = 'q';
14310           else
14311             *obufp++ = 'd';
14312           if (!(rex & REX_W))
14313             used_prefixes |= (prefixes & PREFIX_DATA);
14314           break;
14315         case '&':
14316           if (!intel_syntax
14317               && address_mode == mode_64bit
14318               && isa64 == intel64)
14319             {
14320               *obufp++ = 'q';
14321               break;
14322             }
14323           /* Fall through.  */
14324         case 'T':
14325           if (!intel_syntax
14326               && address_mode == mode_64bit
14327               && ((sizeflag & DFLAG) || (rex & REX_W)))
14328             {
14329               *obufp++ = 'q';
14330               break;
14331             }
14332           /* Fall through.  */
14333           goto case_P;
14334         case 'P':
14335           if (l == 0 && len == 1)
14336             {
14337 case_P:
14338               if (intel_syntax)
14339                 {
14340                   if ((rex & REX_W) == 0
14341                       && (prefixes & PREFIX_DATA))
14342                     {
14343                       if ((sizeflag & DFLAG) == 0)
14344                         *obufp++ = 'w';
14345                       used_prefixes |= (prefixes & PREFIX_DATA);
14346                     }
14347                   break;
14348                 }
14349               if ((prefixes & PREFIX_DATA)
14350                   || (rex & REX_W)
14351                   || (sizeflag & SUFFIX_ALWAYS))
14352                 {
14353                   USED_REX (REX_W);
14354                   if (rex & REX_W)
14355                     *obufp++ = 'q';
14356                   else
14357                     {
14358                       if (sizeflag & DFLAG)
14359                         *obufp++ = 'l';
14360                       else
14361                         *obufp++ = 'w';
14362                       used_prefixes |= (prefixes & PREFIX_DATA);
14363                     }
14364                 }
14365             }
14366           else
14367             {
14368               if (l != 1 || len != 2 || last[0] != 'L')
14369                 {
14370                   SAVE_LAST (*p);
14371                   break;
14372                 }
14373
14374               if ((prefixes & PREFIX_DATA)
14375                   || (rex & REX_W)
14376                   || (sizeflag & SUFFIX_ALWAYS))
14377                 {
14378                   USED_REX (REX_W);
14379                   if (rex & REX_W)
14380                     *obufp++ = 'q';
14381                   else
14382                     {
14383                       if (sizeflag & DFLAG)
14384                         *obufp++ = intel_syntax ? 'd' : 'l';
14385                       else
14386                         *obufp++ = 'w';
14387                       used_prefixes |= (prefixes & PREFIX_DATA);
14388                     }
14389                 }
14390             }
14391           break;
14392         case 'U':
14393           if (intel_syntax)
14394             break;
14395           if (address_mode == mode_64bit
14396               && ((sizeflag & DFLAG) || (rex & REX_W)))
14397             {
14398               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
14399                 *obufp++ = 'q';
14400               break;
14401             }
14402           /* Fall through.  */
14403           goto case_Q;
14404         case 'Q':
14405           if (l == 0 && len == 1)
14406             {
14407 case_Q:
14408               if (intel_syntax && !alt)
14409                 break;
14410               USED_REX (REX_W);
14411               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
14412                 {
14413                   if (rex & REX_W)
14414                     *obufp++ = 'q';
14415                   else
14416                     {
14417                       if (sizeflag & DFLAG)
14418                         *obufp++ = intel_syntax ? 'd' : 'l';
14419                       else
14420                         *obufp++ = 'w';
14421                       used_prefixes |= (prefixes & PREFIX_DATA);
14422                     }
14423                 }
14424             }
14425           else
14426             {
14427               if (l != 1 || len != 2 || last[0] != 'L')
14428                 {
14429                   SAVE_LAST (*p);
14430                   break;
14431                 }
14432               if (intel_syntax
14433                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
14434                 break;
14435               if ((rex & REX_W))
14436                 {
14437                   USED_REX (REX_W);
14438                   *obufp++ = 'q';
14439                 }
14440               else
14441                 *obufp++ = 'l';
14442             }
14443           break;
14444         case 'R':
14445           USED_REX (REX_W);
14446           if (rex & REX_W)
14447             *obufp++ = 'q';
14448           else if (sizeflag & DFLAG)
14449             {
14450               if (intel_syntax)
14451                   *obufp++ = 'd';
14452               else
14453                   *obufp++ = 'l';
14454             }
14455           else
14456             *obufp++ = 'w';
14457           if (intel_syntax && !p[1]
14458               && ((rex & REX_W) || (sizeflag & DFLAG)))
14459             *obufp++ = 'e';
14460           if (!(rex & REX_W))
14461             used_prefixes |= (prefixes & PREFIX_DATA);
14462           break;
14463         case 'V':
14464           if (l == 0 && len == 1)
14465             {
14466               if (intel_syntax)
14467                 break;
14468               if (address_mode == mode_64bit
14469                   && ((sizeflag & DFLAG) || (rex & REX_W)))
14470                 {
14471                   if (sizeflag & SUFFIX_ALWAYS)
14472                     *obufp++ = 'q';
14473                   break;
14474                 }
14475             }
14476           else
14477             {
14478               if (l != 1
14479                   || len != 2
14480                   || last[0] != 'L')
14481                 {
14482                   SAVE_LAST (*p);
14483                   break;
14484                 }
14485
14486               if (rex & REX_W)
14487                 {
14488                   *obufp++ = 'a';
14489                   *obufp++ = 'b';
14490                   *obufp++ = 's';
14491                 }
14492             }
14493           /* Fall through.  */
14494           goto case_S;
14495         case 'S':
14496           if (l == 0 && len == 1)
14497             {
14498 case_S:
14499               if (intel_syntax)
14500                 break;
14501               if (sizeflag & SUFFIX_ALWAYS)
14502                 {
14503                   if (rex & REX_W)
14504                     *obufp++ = 'q';
14505                   else
14506                     {
14507                       if (sizeflag & DFLAG)
14508                         *obufp++ = 'l';
14509                       else
14510                         *obufp++ = 'w';
14511                       used_prefixes |= (prefixes & PREFIX_DATA);
14512                     }
14513                 }
14514             }
14515           else
14516             {
14517               if (l != 1
14518                   || len != 2
14519                   || last[0] != 'L')
14520                 {
14521                   SAVE_LAST (*p);
14522                   break;
14523                 }
14524
14525               if (address_mode == mode_64bit
14526                   && !(prefixes & PREFIX_ADDR))
14527                 {
14528                   *obufp++ = 'a';
14529                   *obufp++ = 'b';
14530                   *obufp++ = 's';
14531                 }
14532
14533               goto case_S;
14534             }
14535           break;
14536         case 'X':
14537           if (l != 0 || len != 1)
14538             {
14539               SAVE_LAST (*p);
14540               break;
14541             }
14542           if (need_vex && vex.prefix)
14543             {
14544               if (vex.prefix == DATA_PREFIX_OPCODE)
14545                 *obufp++ = 'd';
14546               else
14547                 *obufp++ = 's';
14548             }
14549           else
14550             {
14551               if (prefixes & PREFIX_DATA)
14552                 *obufp++ = 'd';
14553               else
14554                 *obufp++ = 's';
14555               used_prefixes |= (prefixes & PREFIX_DATA);
14556             }
14557           break;
14558         case 'Y':
14559           if (l == 0 && len == 1)
14560             {
14561               if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
14562                 break;
14563               if (rex & REX_W)
14564                 {
14565                   USED_REX (REX_W);
14566                   *obufp++ = 'q';
14567                 }
14568               break;
14569             }
14570           else
14571             {
14572               if (l != 1 || len != 2 || last[0] != 'X')
14573                 {
14574                   SAVE_LAST (*p);
14575                   break;
14576                 }
14577               if (!need_vex)
14578                 abort ();
14579               if (intel_syntax
14580                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
14581                 break;
14582               switch (vex.length)
14583                 {
14584                 case 128:
14585                   *obufp++ = 'x';
14586                   break;
14587                 case 256:
14588                   *obufp++ = 'y';
14589                   break;
14590                 case 512:
14591                   if (!vex.evex)
14592                 default:
14593                     abort ();
14594                 }
14595             }
14596           break;
14597         case 'W':
14598           if (l == 0 && len == 1)
14599             {
14600               /* operand size flag for cwtl, cbtw */
14601               USED_REX (REX_W);
14602               if (rex & REX_W)
14603                 {
14604                   if (intel_syntax)
14605                     *obufp++ = 'd';
14606                   else
14607                     *obufp++ = 'l';
14608                 }
14609               else if (sizeflag & DFLAG)
14610                 *obufp++ = 'w';
14611               else
14612                 *obufp++ = 'b';
14613               if (!(rex & REX_W))
14614                 used_prefixes |= (prefixes & PREFIX_DATA);
14615             }
14616           else
14617             {
14618               if (l != 1
14619                   || len != 2
14620                   || (last[0] != 'X'
14621                       && last[0] != 'L'))
14622                 {
14623                   SAVE_LAST (*p);
14624                   break;
14625                 }
14626               if (!need_vex)
14627                 abort ();
14628               if (last[0] == 'X')
14629                 *obufp++ = vex.w ? 'd': 's';
14630               else
14631                 *obufp++ = vex.w ? 'q': 'd';
14632             }
14633           break;
14634         case '^':
14635           if (intel_syntax)
14636             break;
14637           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
14638             {
14639               if (sizeflag & DFLAG)
14640                 *obufp++ = 'l';
14641               else
14642                 *obufp++ = 'w';
14643               used_prefixes |= (prefixes & PREFIX_DATA);
14644             }
14645           break;
14646         case '@':
14647           if (intel_syntax)
14648             break;
14649           if (address_mode == mode_64bit
14650               && (isa64 == intel64
14651                   || ((sizeflag & DFLAG) || (rex & REX_W))))
14652               *obufp++ = 'q';
14653           else if ((prefixes & PREFIX_DATA))
14654             {
14655               if (!(sizeflag & DFLAG))
14656                 *obufp++ = 'w';
14657               used_prefixes |= (prefixes & PREFIX_DATA);
14658             }
14659           break;
14660         }
14661       alt = 0;
14662     }
14663   *obufp = 0;
14664   mnemonicendp = obufp;
14665   return 0;
14666 }
14667
14668 static void
14669 oappend (const char *s)
14670 {
14671   obufp = stpcpy (obufp, s);
14672 }
14673
14674 static void
14675 append_seg (void)
14676 {
14677   /* Only print the active segment register.  */
14678   if (!active_seg_prefix)
14679     return;
14680
14681   used_prefixes |= active_seg_prefix;
14682   switch (active_seg_prefix)
14683     {
14684     case PREFIX_CS:
14685       oappend_maybe_intel ("%cs:");
14686       break;
14687     case PREFIX_DS:
14688       oappend_maybe_intel ("%ds:");
14689       break;
14690     case PREFIX_SS:
14691       oappend_maybe_intel ("%ss:");
14692       break;
14693     case PREFIX_ES:
14694       oappend_maybe_intel ("%es:");
14695       break;
14696     case PREFIX_FS:
14697       oappend_maybe_intel ("%fs:");
14698       break;
14699     case PREFIX_GS:
14700       oappend_maybe_intel ("%gs:");
14701       break;
14702     default:
14703       break;
14704     }
14705 }
14706
14707 static void
14708 OP_indirE (int bytemode, int sizeflag)
14709 {
14710   if (!intel_syntax)
14711     oappend ("*");
14712   OP_E (bytemode, sizeflag);
14713 }
14714
14715 static void
14716 print_operand_value (char *buf, int hex, bfd_vma disp)
14717 {
14718   if (address_mode == mode_64bit)
14719     {
14720       if (hex)
14721         {
14722           char tmp[30];
14723           int i;
14724           buf[0] = '0';
14725           buf[1] = 'x';
14726           sprintf_vma (tmp, disp);
14727           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
14728           strcpy (buf + 2, tmp + i);
14729         }
14730       else
14731         {
14732           bfd_signed_vma v = disp;
14733           char tmp[30];
14734           int i;
14735           if (v < 0)
14736             {
14737               *(buf++) = '-';
14738               v = -disp;
14739               /* Check for possible overflow on 0x8000000000000000.  */
14740               if (v < 0)
14741                 {
14742                   strcpy (buf, "9223372036854775808");
14743                   return;
14744                 }
14745             }
14746           if (!v)
14747             {
14748               strcpy (buf, "0");
14749               return;
14750             }
14751
14752           i = 0;
14753           tmp[29] = 0;
14754           while (v)
14755             {
14756               tmp[28 - i] = (v % 10) + '0';
14757               v /= 10;
14758               i++;
14759             }
14760           strcpy (buf, tmp + 29 - i);
14761         }
14762     }
14763   else
14764     {
14765       if (hex)
14766         sprintf (buf, "0x%x", (unsigned int) disp);
14767       else
14768         sprintf (buf, "%d", (int) disp);
14769     }
14770 }
14771
14772 /* Put DISP in BUF as signed hex number.  */
14773
14774 static void
14775 print_displacement (char *buf, bfd_vma disp)
14776 {
14777   bfd_signed_vma val = disp;
14778   char tmp[30];
14779   int i, j = 0;
14780
14781   if (val < 0)
14782     {
14783       buf[j++] = '-';
14784       val = -disp;
14785
14786       /* Check for possible overflow.  */
14787       if (val < 0)
14788         {
14789           switch (address_mode)
14790             {
14791             case mode_64bit:
14792               strcpy (buf + j, "0x8000000000000000");
14793               break;
14794             case mode_32bit:
14795               strcpy (buf + j, "0x80000000");
14796               break;
14797             case mode_16bit:
14798               strcpy (buf + j, "0x8000");
14799               break;
14800             }
14801           return;
14802         }
14803     }
14804
14805   buf[j++] = '0';
14806   buf[j++] = 'x';
14807
14808   sprintf_vma (tmp, (bfd_vma) val);
14809   for (i = 0; tmp[i] == '0'; i++)
14810     continue;
14811   if (tmp[i] == '\0')
14812     i--;
14813   strcpy (buf + j, tmp + i);
14814 }
14815
14816 static void
14817 intel_operand_size (int bytemode, int sizeflag)
14818 {
14819   if (vex.evex
14820       && vex.b
14821       && (bytemode == x_mode
14822           || bytemode == evex_half_bcst_xmmq_mode))
14823     {
14824       if (vex.w)
14825         oappend ("QWORD PTR ");
14826       else
14827         oappend ("DWORD PTR ");
14828       return;
14829     }
14830   switch (bytemode)
14831     {
14832     case b_mode:
14833     case b_swap_mode:
14834     case dqb_mode:
14835     case db_mode:
14836       oappend ("BYTE PTR ");
14837       break;
14838     case w_mode:
14839     case dw_mode:
14840     case dqw_mode:
14841     case dqw_swap_mode:
14842       oappend ("WORD PTR ");
14843       break;
14844     case indir_v_mode:
14845       if (address_mode == mode_64bit && isa64 == intel64)
14846         {
14847           oappend ("QWORD PTR ");
14848           break;
14849         }
14850       /* Fall through.  */
14851     case stack_v_mode:
14852       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14853         {
14854           oappend ("QWORD PTR ");
14855           break;
14856         }
14857       /* Fall through.  */
14858     case v_mode:
14859     case v_swap_mode:
14860     case dq_mode:
14861       USED_REX (REX_W);
14862       if (rex & REX_W)
14863         oappend ("QWORD PTR ");
14864       else
14865         {
14866           if ((sizeflag & DFLAG) || bytemode == dq_mode)
14867             oappend ("DWORD PTR ");
14868           else
14869             oappend ("WORD PTR ");
14870           used_prefixes |= (prefixes & PREFIX_DATA);
14871         }
14872       break;
14873     case z_mode:
14874       if ((rex & REX_W) || (sizeflag & DFLAG))
14875         *obufp++ = 'D';
14876       oappend ("WORD PTR ");
14877       if (!(rex & REX_W))
14878         used_prefixes |= (prefixes & PREFIX_DATA);
14879       break;
14880     case a_mode:
14881       if (sizeflag & DFLAG)
14882         oappend ("QWORD PTR ");
14883       else
14884         oappend ("DWORD PTR ");
14885       used_prefixes |= (prefixes & PREFIX_DATA);
14886       break;
14887     case d_mode:
14888     case d_scalar_mode:
14889     case d_scalar_swap_mode:
14890     case d_swap_mode:
14891     case dqd_mode:
14892       oappend ("DWORD PTR ");
14893       break;
14894     case q_mode:
14895     case q_scalar_mode:
14896     case q_scalar_swap_mode:
14897     case q_swap_mode:
14898       oappend ("QWORD PTR ");
14899       break;
14900     case m_mode:
14901       if (address_mode == mode_64bit)
14902         oappend ("QWORD PTR ");
14903       else
14904         oappend ("DWORD PTR ");
14905       break;
14906     case f_mode:
14907       if (sizeflag & DFLAG)
14908         oappend ("FWORD PTR ");
14909       else
14910         oappend ("DWORD PTR ");
14911       used_prefixes |= (prefixes & PREFIX_DATA);
14912       break;
14913     case t_mode:
14914       oappend ("TBYTE PTR ");
14915       break;
14916     case x_mode:
14917     case x_swap_mode:
14918     case evex_x_gscat_mode:
14919     case evex_x_nobcst_mode:
14920       if (need_vex)
14921         {
14922           switch (vex.length)
14923             {
14924             case 128:
14925               oappend ("XMMWORD PTR ");
14926               break;
14927             case 256:
14928               oappend ("YMMWORD PTR ");
14929               break;
14930             case 512:
14931               oappend ("ZMMWORD PTR ");
14932               break;
14933             default:
14934               abort ();
14935             }
14936         }
14937       else
14938         oappend ("XMMWORD PTR ");
14939       break;
14940     case xmm_mode:
14941       oappend ("XMMWORD PTR ");
14942       break;
14943     case ymm_mode:
14944       oappend ("YMMWORD PTR ");
14945       break;
14946     case xmmq_mode:
14947     case evex_half_bcst_xmmq_mode:
14948       if (!need_vex)
14949         abort ();
14950
14951       switch (vex.length)
14952         {
14953         case 128:
14954           oappend ("QWORD PTR ");
14955           break;
14956         case 256:
14957           oappend ("XMMWORD PTR ");
14958           break;
14959         case 512:
14960           oappend ("YMMWORD PTR ");
14961           break;
14962         default:
14963           abort ();
14964         }
14965       break;
14966     case xmm_mb_mode:
14967       if (!need_vex)
14968         abort ();
14969
14970       switch (vex.length)
14971         {
14972         case 128:
14973         case 256:
14974         case 512:
14975           oappend ("BYTE PTR ");
14976           break;
14977         default:
14978           abort ();
14979         }
14980       break;
14981     case xmm_mw_mode:
14982       if (!need_vex)
14983         abort ();
14984
14985       switch (vex.length)
14986         {
14987         case 128:
14988         case 256:
14989         case 512:
14990           oappend ("WORD PTR ");
14991           break;
14992         default:
14993           abort ();
14994         }
14995       break;
14996     case xmm_md_mode:
14997       if (!need_vex)
14998         abort ();
14999
15000       switch (vex.length)
15001         {
15002         case 128:
15003         case 256:
15004         case 512:
15005           oappend ("DWORD PTR ");
15006           break;
15007         default:
15008           abort ();
15009         }
15010       break;
15011     case xmm_mq_mode:
15012       if (!need_vex)
15013         abort ();
15014
15015       switch (vex.length)
15016         {
15017         case 128:
15018         case 256:
15019         case 512:
15020           oappend ("QWORD PTR ");
15021           break;
15022         default:
15023           abort ();
15024         }
15025       break;
15026     case xmmdw_mode:
15027       if (!need_vex)
15028         abort ();
15029
15030       switch (vex.length)
15031         {
15032         case 128:
15033           oappend ("WORD PTR ");
15034           break;
15035         case 256:
15036           oappend ("DWORD PTR ");
15037           break;
15038         case 512:
15039           oappend ("QWORD PTR ");
15040           break;
15041         default:
15042           abort ();
15043         }
15044       break;
15045     case xmmqd_mode:
15046       if (!need_vex)
15047         abort ();
15048
15049       switch (vex.length)
15050         {
15051         case 128:
15052           oappend ("DWORD PTR ");
15053           break;
15054         case 256:
15055           oappend ("QWORD PTR ");
15056           break;
15057         case 512:
15058           oappend ("XMMWORD PTR ");
15059           break;
15060         default:
15061           abort ();
15062         }
15063       break;
15064     case ymmq_mode:
15065       if (!need_vex)
15066         abort ();
15067
15068       switch (vex.length)
15069         {
15070         case 128:
15071           oappend ("QWORD PTR ");
15072           break;
15073         case 256:
15074           oappend ("YMMWORD PTR ");
15075           break;
15076         case 512:
15077           oappend ("ZMMWORD PTR ");
15078           break;
15079         default:
15080           abort ();
15081         }
15082       break;
15083     case ymmxmm_mode:
15084       if (!need_vex)
15085         abort ();
15086
15087       switch (vex.length)
15088         {
15089         case 128:
15090         case 256:
15091           oappend ("XMMWORD PTR ");
15092           break;
15093         default:
15094           abort ();
15095         }
15096       break;
15097     case o_mode:
15098       oappend ("OWORD PTR ");
15099       break;
15100     case xmm_mdq_mode:
15101     case vex_w_dq_mode:
15102     case vex_scalar_w_dq_mode:
15103       if (!need_vex)
15104         abort ();
15105
15106       if (vex.w)
15107         oappend ("QWORD PTR ");
15108       else
15109         oappend ("DWORD PTR ");
15110       break;
15111     case vex_vsib_d_w_dq_mode:
15112     case vex_vsib_q_w_dq_mode:
15113       if (!need_vex)
15114         abort ();
15115
15116       if (!vex.evex)
15117         {
15118           if (vex.w)
15119             oappend ("QWORD PTR ");
15120           else
15121             oappend ("DWORD PTR ");
15122         }
15123       else
15124         {
15125           switch (vex.length)
15126             {
15127             case 128:
15128               oappend ("XMMWORD PTR ");
15129               break;
15130             case 256:
15131               oappend ("YMMWORD PTR ");
15132               break;
15133             case 512:
15134               oappend ("ZMMWORD PTR ");
15135               break;
15136             default:
15137               abort ();
15138             }
15139         }
15140       break;
15141     case vex_vsib_q_w_d_mode:
15142     case vex_vsib_d_w_d_mode:
15143       if (!need_vex || !vex.evex)
15144         abort ();
15145
15146       switch (vex.length)
15147         {
15148         case 128:
15149           oappend ("QWORD PTR ");
15150           break;
15151         case 256:
15152           oappend ("XMMWORD PTR ");
15153           break;
15154         case 512:
15155           oappend ("YMMWORD PTR ");
15156           break;
15157         default:
15158           abort ();
15159         }
15160
15161       break;
15162     case mask_bd_mode:
15163       if (!need_vex || vex.length != 128)
15164         abort ();
15165       if (vex.w)
15166         oappend ("DWORD PTR ");
15167       else
15168         oappend ("BYTE PTR ");
15169       break;
15170     case mask_mode:
15171       if (!need_vex)
15172         abort ();
15173       if (vex.w)
15174         oappend ("QWORD PTR ");
15175       else
15176         oappend ("WORD PTR ");
15177       break;
15178     case v_bnd_mode:
15179     default:
15180       break;
15181     }
15182 }
15183
15184 static void
15185 OP_E_register (int bytemode, int sizeflag)
15186 {
15187   int reg = modrm.rm;
15188   const char **names;
15189
15190   USED_REX (REX_B);
15191   if ((rex & REX_B))
15192     reg += 8;
15193
15194   if ((sizeflag & SUFFIX_ALWAYS)
15195       && (bytemode == b_swap_mode
15196           || bytemode == v_swap_mode
15197           || bytemode == dqw_swap_mode))
15198     swap_operand ();
15199
15200   switch (bytemode)
15201     {
15202     case b_mode:
15203     case b_swap_mode:
15204       USED_REX (0);
15205       if (rex)
15206         names = names8rex;
15207       else
15208         names = names8;
15209       break;
15210     case w_mode:
15211       names = names16;
15212       break;
15213     case d_mode:
15214     case dw_mode:
15215     case db_mode:
15216       names = names32;
15217       break;
15218     case q_mode:
15219       names = names64;
15220       break;
15221     case m_mode:
15222     case v_bnd_mode:
15223       names = address_mode == mode_64bit ? names64 : names32;
15224       break;
15225     case bnd_mode:
15226       names = names_bnd;
15227       break;
15228     case indir_v_mode:
15229       if (address_mode == mode_64bit && isa64 == intel64)
15230         {
15231           names = names64;
15232           break;
15233         }
15234       /* Fall through.  */
15235     case stack_v_mode:
15236       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
15237         {
15238           names = names64;
15239           break;
15240         }
15241       bytemode = v_mode;
15242       /* Fall through.  */
15243     case v_mode:
15244     case v_swap_mode:
15245     case dq_mode:
15246     case dqb_mode:
15247     case dqd_mode:
15248     case dqw_mode:
15249     case dqw_swap_mode:
15250       USED_REX (REX_W);
15251       if (rex & REX_W)
15252         names = names64;
15253       else
15254         {
15255           if ((sizeflag & DFLAG)
15256               || (bytemode != v_mode
15257                   && bytemode != v_swap_mode))
15258             names = names32;
15259           else
15260             names = names16;
15261           used_prefixes |= (prefixes & PREFIX_DATA);
15262         }
15263       break;
15264     case mask_bd_mode:
15265     case mask_mode:
15266       if (reg > 0x7)
15267         {
15268           oappend ("(bad)");
15269           return;
15270         }
15271       names = names_mask;
15272       break;
15273     case 0:
15274       return;
15275     default:
15276       oappend (INTERNAL_DISASSEMBLER_ERROR);
15277       return;
15278     }
15279   oappend (names[reg]);
15280 }
15281
15282 static void
15283 OP_E_memory (int bytemode, int sizeflag)
15284 {
15285   bfd_vma disp = 0;
15286   int add = (rex & REX_B) ? 8 : 0;
15287   int riprel = 0;
15288   int shift;
15289
15290   if (vex.evex)
15291     {
15292       /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0.  */
15293       if (vex.b
15294           && bytemode != x_mode
15295           && bytemode != xmmq_mode
15296           && bytemode != evex_half_bcst_xmmq_mode)
15297         {
15298           BadOp ();
15299           return;
15300         }
15301       switch (bytemode)
15302         {
15303         case dqw_mode:
15304         case dw_mode:
15305         case dqw_swap_mode:
15306           shift = 1;
15307           break;
15308         case dqb_mode:
15309         case db_mode:
15310           shift = 0;
15311           break;
15312         case vex_vsib_d_w_dq_mode:
15313         case vex_vsib_d_w_d_mode:
15314         case vex_vsib_q_w_dq_mode:
15315         case vex_vsib_q_w_d_mode:
15316         case evex_x_gscat_mode:
15317         case xmm_mdq_mode:
15318           shift = vex.w ? 3 : 2;
15319           break;
15320         case x_mode:
15321         case evex_half_bcst_xmmq_mode:
15322         case xmmq_mode:
15323           if (vex.b)
15324             {
15325               shift = vex.w ? 3 : 2;
15326               break;
15327             }
15328           /* Fall through.  */
15329         case xmmqd_mode:
15330         case xmmdw_mode:
15331         case ymmq_mode:
15332         case evex_x_nobcst_mode:
15333         case x_swap_mode:
15334           switch (vex.length)
15335             {
15336             case 128:
15337               shift = 4;
15338               break;
15339             case 256:
15340               shift = 5;
15341               break;
15342             case 512:
15343               shift = 6;
15344               break;
15345             default:
15346               abort ();
15347             }
15348           break;
15349         case ymm_mode:
15350           shift = 5;
15351           break;
15352         case xmm_mode:
15353           shift = 4;
15354           break;
15355         case xmm_mq_mode:
15356         case q_mode:
15357         case q_scalar_mode:
15358         case q_swap_mode:
15359         case q_scalar_swap_mode:
15360           shift = 3;
15361           break;
15362         case dqd_mode:
15363         case xmm_md_mode:
15364         case d_mode:
15365         case d_scalar_mode:
15366         case d_swap_mode:
15367         case d_scalar_swap_mode:
15368           shift = 2;
15369           break;
15370         case xmm_mw_mode:
15371           shift = 1;
15372           break;
15373         case xmm_mb_mode:
15374           shift = 0;
15375           break;
15376         default:
15377           abort ();
15378         }
15379       /* Make necessary corrections to shift for modes that need it.
15380          For these modes we currently have shift 4, 5 or 6 depending on
15381          vex.length (it corresponds to xmmword, ymmword or zmmword
15382          operand).  We might want to make it 3, 4 or 5 (e.g. for
15383          xmmq_mode).  In case of broadcast enabled the corrections
15384          aren't needed, as element size is always 32 or 64 bits.  */
15385       if (!vex.b
15386           && (bytemode == xmmq_mode
15387               || bytemode == evex_half_bcst_xmmq_mode))
15388         shift -= 1;
15389       else if (bytemode == xmmqd_mode)
15390         shift -= 2;
15391       else if (bytemode == xmmdw_mode)
15392         shift -= 3;
15393       else if (bytemode == ymmq_mode && vex.length == 128)
15394         shift -= 1;
15395     }
15396   else
15397     shift = 0;
15398
15399   USED_REX (REX_B);
15400   if (intel_syntax)
15401     intel_operand_size (bytemode, sizeflag);
15402   append_seg ();
15403
15404   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
15405     {
15406       /* 32/64 bit address mode */
15407       int havedisp;
15408       int havesib;
15409       int havebase;
15410       int haveindex;
15411       int needindex;
15412       int base, rbase;
15413       int vindex = 0;
15414       int scale = 0;
15415       int addr32flag = !((sizeflag & AFLAG)
15416                          || bytemode == v_bnd_mode
15417                          || bytemode == bnd_mode);
15418       const char **indexes64 = names64;
15419       const char **indexes32 = names32;
15420
15421       havesib = 0;
15422       havebase = 1;
15423       haveindex = 0;
15424       base = modrm.rm;
15425
15426       if (base == 4)
15427         {
15428           havesib = 1;
15429           vindex = sib.index;
15430           USED_REX (REX_X);
15431           if (rex & REX_X)
15432             vindex += 8;
15433           switch (bytemode)
15434             {
15435             case vex_vsib_d_w_dq_mode:
15436             case vex_vsib_d_w_d_mode:
15437             case vex_vsib_q_w_dq_mode:
15438             case vex_vsib_q_w_d_mode:
15439               if (!need_vex)
15440                 abort ();
15441               if (vex.evex)
15442                 {
15443                   if (!vex.v)
15444                     vindex += 16;
15445                 }
15446
15447               haveindex = 1;
15448               switch (vex.length)
15449                 {
15450                 case 128:
15451                   indexes64 = indexes32 = names_xmm;
15452                   break;
15453                 case 256:
15454                   if (!vex.w
15455                       || bytemode == vex_vsib_q_w_dq_mode
15456                       || bytemode == vex_vsib_q_w_d_mode)
15457                     indexes64 = indexes32 = names_ymm;
15458                   else
15459                     indexes64 = indexes32 = names_xmm;
15460                   break;
15461                 case 512:
15462                   if (!vex.w
15463                       || bytemode == vex_vsib_q_w_dq_mode
15464                       || bytemode == vex_vsib_q_w_d_mode)
15465                     indexes64 = indexes32 = names_zmm;
15466                   else
15467                     indexes64 = indexes32 = names_ymm;
15468                   break;
15469                 default:
15470                   abort ();
15471                 }
15472               break;
15473             default:
15474               haveindex = vindex != 4;
15475               break;
15476             }
15477           scale = sib.scale;
15478           base = sib.base;
15479           codep++;
15480         }
15481       rbase = base + add;
15482
15483       switch (modrm.mod)
15484         {
15485         case 0:
15486           if (base == 5)
15487             {
15488               havebase = 0;
15489               if (address_mode == mode_64bit && !havesib)
15490                 riprel = 1;
15491               disp = get32s ();
15492             }
15493           break;
15494         case 1:
15495           FETCH_DATA (the_info, codep + 1);
15496           disp = *codep++;
15497           if ((disp & 0x80) != 0)
15498             disp -= 0x100;
15499           if (vex.evex && shift > 0)
15500             disp <<= shift;
15501           break;
15502         case 2:
15503           disp = get32s ();
15504           break;
15505         }
15506
15507       /* In 32bit mode, we need index register to tell [offset] from
15508          [eiz*1 + offset].  */
15509       needindex = (havesib
15510                    && !havebase
15511                    && !haveindex
15512                    && address_mode == mode_32bit);
15513       havedisp = (havebase
15514                   || needindex
15515                   || (havesib && (haveindex || scale != 0)));
15516
15517       if (!intel_syntax)
15518         if (modrm.mod != 0 || base == 5)
15519           {
15520             if (havedisp || riprel)
15521               print_displacement (scratchbuf, disp);
15522             else
15523               print_operand_value (scratchbuf, 1, disp);
15524             oappend (scratchbuf);
15525             if (riprel)
15526               {
15527                 set_op (disp, 1);
15528                 oappend (!addr32flag ? "(%rip)" : "(%eip)");
15529               }
15530           }
15531
15532       if ((havebase || haveindex || riprel)
15533           && (bytemode != v_bnd_mode)
15534           && (bytemode != bnd_mode))
15535         used_prefixes |= PREFIX_ADDR;
15536
15537       if (havedisp || (intel_syntax && riprel))
15538         {
15539           *obufp++ = open_char;
15540           if (intel_syntax && riprel)
15541             {
15542               set_op (disp, 1);
15543               oappend (!addr32flag ? "rip" : "eip");
15544             }
15545           *obufp = '\0';
15546           if (havebase)
15547             oappend (address_mode == mode_64bit && !addr32flag
15548                      ? names64[rbase] : names32[rbase]);
15549           if (havesib)
15550             {
15551               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
15552                  print index to tell base + index from base.  */
15553               if (scale != 0
15554                   || needindex
15555                   || haveindex
15556                   || (havebase && base != ESP_REG_NUM))
15557                 {
15558                   if (!intel_syntax || havebase)
15559                     {
15560                       *obufp++ = separator_char;
15561                       *obufp = '\0';
15562                     }
15563                   if (haveindex)
15564                     oappend (address_mode == mode_64bit && !addr32flag
15565                              ? indexes64[vindex] : indexes32[vindex]);
15566                   else
15567                     oappend (address_mode == mode_64bit && !addr32flag
15568                              ? index64 : index32);
15569
15570                   *obufp++ = scale_char;
15571                   *obufp = '\0';
15572                   sprintf (scratchbuf, "%d", 1 << scale);
15573                   oappend (scratchbuf);
15574                 }
15575             }
15576           if (intel_syntax
15577               && (disp || modrm.mod != 0 || base == 5))
15578             {
15579               if (!havedisp || (bfd_signed_vma) disp >= 0)
15580                 {
15581                   *obufp++ = '+';
15582                   *obufp = '\0';
15583                 }
15584               else if (modrm.mod != 1 && disp != -disp)
15585                 {
15586                   *obufp++ = '-';
15587                   *obufp = '\0';
15588                   disp = - (bfd_signed_vma) disp;
15589                 }
15590
15591               if (havedisp)
15592                 print_displacement (scratchbuf, disp);
15593               else
15594                 print_operand_value (scratchbuf, 1, disp);
15595               oappend (scratchbuf);
15596             }
15597
15598           *obufp++ = close_char;
15599           *obufp = '\0';
15600         }
15601       else if (intel_syntax)
15602         {
15603           if (modrm.mod != 0 || base == 5)
15604             {
15605               if (!active_seg_prefix)
15606                 {
15607                   oappend (names_seg[ds_reg - es_reg]);
15608                   oappend (":");
15609                 }
15610               print_operand_value (scratchbuf, 1, disp);
15611               oappend (scratchbuf);
15612             }
15613         }
15614     }
15615   else
15616     {
15617       /* 16 bit address mode */
15618       used_prefixes |= prefixes & PREFIX_ADDR;
15619       switch (modrm.mod)
15620         {
15621         case 0:
15622           if (modrm.rm == 6)
15623             {
15624               disp = get16 ();
15625               if ((disp & 0x8000) != 0)
15626                 disp -= 0x10000;
15627             }
15628           break;
15629         case 1:
15630           FETCH_DATA (the_info, codep + 1);
15631           disp = *codep++;
15632           if ((disp & 0x80) != 0)
15633             disp -= 0x100;
15634           break;
15635         case 2:
15636           disp = get16 ();
15637           if ((disp & 0x8000) != 0)
15638             disp -= 0x10000;
15639           break;
15640         }
15641
15642       if (!intel_syntax)
15643         if (modrm.mod != 0 || modrm.rm == 6)
15644           {
15645             print_displacement (scratchbuf, disp);
15646             oappend (scratchbuf);
15647           }
15648
15649       if (modrm.mod != 0 || modrm.rm != 6)
15650         {
15651           *obufp++ = open_char;
15652           *obufp = '\0';
15653           oappend (index16[modrm.rm]);
15654           if (intel_syntax
15655               && (disp || modrm.mod != 0 || modrm.rm == 6))
15656             {
15657               if ((bfd_signed_vma) disp >= 0)
15658                 {
15659                   *obufp++ = '+';
15660                   *obufp = '\0';
15661                 }
15662               else if (modrm.mod != 1)
15663                 {
15664                   *obufp++ = '-';
15665                   *obufp = '\0';
15666                   disp = - (bfd_signed_vma) disp;
15667                 }
15668
15669               print_displacement (scratchbuf, disp);
15670               oappend (scratchbuf);
15671             }
15672
15673           *obufp++ = close_char;
15674           *obufp = '\0';
15675         }
15676       else if (intel_syntax)
15677         {
15678           if (!active_seg_prefix)
15679             {
15680               oappend (names_seg[ds_reg - es_reg]);
15681               oappend (":");
15682             }
15683           print_operand_value (scratchbuf, 1, disp & 0xffff);
15684           oappend (scratchbuf);
15685         }
15686     }
15687   if (vex.evex && vex.b
15688       && (bytemode == x_mode
15689           || bytemode == xmmq_mode
15690           || bytemode == evex_half_bcst_xmmq_mode))
15691     {
15692       if (vex.w
15693           || bytemode == xmmq_mode
15694           || bytemode == evex_half_bcst_xmmq_mode)
15695         {
15696           switch (vex.length)
15697             {
15698             case 128:
15699               oappend ("{1to2}");
15700               break;
15701             case 256:
15702               oappend ("{1to4}");
15703               break;
15704             case 512:
15705               oappend ("{1to8}");
15706               break;
15707             default:
15708               abort ();
15709             }
15710         }
15711       else
15712         {
15713           switch (vex.length)
15714             {
15715             case 128:
15716               oappend ("{1to4}");
15717               break;
15718             case 256:
15719               oappend ("{1to8}");
15720               break;
15721             case 512:
15722               oappend ("{1to16}");
15723               break;
15724             default:
15725               abort ();
15726             }
15727         }
15728     }
15729 }
15730
15731 static void
15732 OP_E (int bytemode, int sizeflag)
15733 {
15734   /* Skip mod/rm byte.  */
15735   MODRM_CHECK;
15736   codep++;
15737
15738   if (modrm.mod == 3)
15739     OP_E_register (bytemode, sizeflag);
15740   else
15741     OP_E_memory (bytemode, sizeflag);
15742 }
15743
15744 static void
15745 OP_G (int bytemode, int sizeflag)
15746 {
15747   int add = 0;
15748   USED_REX (REX_R);
15749   if (rex & REX_R)
15750     add += 8;
15751   switch (bytemode)
15752     {
15753     case b_mode:
15754       USED_REX (0);
15755       if (rex)
15756         oappend (names8rex[modrm.reg + add]);
15757       else
15758         oappend (names8[modrm.reg + add]);
15759       break;
15760     case w_mode:
15761       oappend (names16[modrm.reg + add]);
15762       break;
15763     case d_mode:
15764     case db_mode:
15765     case dw_mode:
15766       oappend (names32[modrm.reg + add]);
15767       break;
15768     case q_mode:
15769       oappend (names64[modrm.reg + add]);
15770       break;
15771     case bnd_mode:
15772       oappend (names_bnd[modrm.reg]);
15773       break;
15774     case v_mode:
15775     case dq_mode:
15776     case dqb_mode:
15777     case dqd_mode:
15778     case dqw_mode:
15779     case dqw_swap_mode:
15780       USED_REX (REX_W);
15781       if (rex & REX_W)
15782         oappend (names64[modrm.reg + add]);
15783       else
15784         {
15785           if ((sizeflag & DFLAG) || bytemode != v_mode)
15786             oappend (names32[modrm.reg + add]);
15787           else
15788             oappend (names16[modrm.reg + add]);
15789           used_prefixes |= (prefixes & PREFIX_DATA);
15790         }
15791       break;
15792     case m_mode:
15793       if (address_mode == mode_64bit)
15794         oappend (names64[modrm.reg + add]);
15795       else
15796         oappend (names32[modrm.reg + add]);
15797       break;
15798     case mask_bd_mode:
15799     case mask_mode:
15800       if ((modrm.reg + add) > 0x7)
15801         {
15802           oappend ("(bad)");
15803           return;
15804         }
15805       oappend (names_mask[modrm.reg + add]);
15806       break;
15807     default:
15808       oappend (INTERNAL_DISASSEMBLER_ERROR);
15809       break;
15810     }
15811 }
15812
15813 static bfd_vma
15814 get64 (void)
15815 {
15816   bfd_vma x;
15817 #ifdef BFD64
15818   unsigned int a;
15819   unsigned int b;
15820
15821   FETCH_DATA (the_info, codep + 8);
15822   a = *codep++ & 0xff;
15823   a |= (*codep++ & 0xff) << 8;
15824   a |= (*codep++ & 0xff) << 16;
15825   a |= (*codep++ & 0xffu) << 24;
15826   b = *codep++ & 0xff;
15827   b |= (*codep++ & 0xff) << 8;
15828   b |= (*codep++ & 0xff) << 16;
15829   b |= (*codep++ & 0xffu) << 24;
15830   x = a + ((bfd_vma) b << 32);
15831 #else
15832   abort ();
15833   x = 0;
15834 #endif
15835   return x;
15836 }
15837
15838 static bfd_signed_vma
15839 get32 (void)
15840 {
15841   bfd_signed_vma x = 0;
15842
15843   FETCH_DATA (the_info, codep + 4);
15844   x = *codep++ & (bfd_signed_vma) 0xff;
15845   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15846   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15847   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15848   return x;
15849 }
15850
15851 static bfd_signed_vma
15852 get32s (void)
15853 {
15854   bfd_signed_vma x = 0;
15855
15856   FETCH_DATA (the_info, codep + 4);
15857   x = *codep++ & (bfd_signed_vma) 0xff;
15858   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15859   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15860   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15861
15862   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
15863
15864   return x;
15865 }
15866
15867 static int
15868 get16 (void)
15869 {
15870   int x = 0;
15871
15872   FETCH_DATA (the_info, codep + 2);
15873   x = *codep++ & 0xff;
15874   x |= (*codep++ & 0xff) << 8;
15875   return x;
15876 }
15877
15878 static void
15879 set_op (bfd_vma op, int riprel)
15880 {
15881   op_index[op_ad] = op_ad;
15882   if (address_mode == mode_64bit)
15883     {
15884       op_address[op_ad] = op;
15885       op_riprel[op_ad] = riprel;
15886     }
15887   else
15888     {
15889       /* Mask to get a 32-bit address.  */
15890       op_address[op_ad] = op & 0xffffffff;
15891       op_riprel[op_ad] = riprel & 0xffffffff;
15892     }
15893 }
15894
15895 static void
15896 OP_REG (int code, int sizeflag)
15897 {
15898   const char *s;
15899   int add;
15900
15901   switch (code)
15902     {
15903     case es_reg: case ss_reg: case cs_reg:
15904     case ds_reg: case fs_reg: case gs_reg:
15905       oappend (names_seg[code - es_reg]);
15906       return;
15907     }
15908
15909   USED_REX (REX_B);
15910   if (rex & REX_B)
15911     add = 8;
15912   else
15913     add = 0;
15914
15915   switch (code)
15916     {
15917     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15918     case sp_reg: case bp_reg: case si_reg: case di_reg:
15919       s = names16[code - ax_reg + add];
15920       break;
15921     case al_reg: case ah_reg: case cl_reg: case ch_reg:
15922     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15923       USED_REX (0);
15924       if (rex)
15925         s = names8rex[code - al_reg + add];
15926       else
15927         s = names8[code - al_reg];
15928       break;
15929     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
15930     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
15931       if (address_mode == mode_64bit
15932           && ((sizeflag & DFLAG) || (rex & REX_W)))
15933         {
15934           s = names64[code - rAX_reg + add];
15935           break;
15936         }
15937       code += eAX_reg - rAX_reg;
15938       /* Fall through.  */
15939     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15940     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15941       USED_REX (REX_W);
15942       if (rex & REX_W)
15943         s = names64[code - eAX_reg + add];
15944       else
15945         {
15946           if (sizeflag & DFLAG)
15947             s = names32[code - eAX_reg + add];
15948           else
15949             s = names16[code - eAX_reg + add];
15950           used_prefixes |= (prefixes & PREFIX_DATA);
15951         }
15952       break;
15953     default:
15954       s = INTERNAL_DISASSEMBLER_ERROR;
15955       break;
15956     }
15957   oappend (s);
15958 }
15959
15960 static void
15961 OP_IMREG (int code, int sizeflag)
15962 {
15963   const char *s;
15964
15965   switch (code)
15966     {
15967     case indir_dx_reg:
15968       if (intel_syntax)
15969         s = "dx";
15970       else
15971         s = "(%dx)";
15972       break;
15973     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15974     case sp_reg: case bp_reg: case si_reg: case di_reg:
15975       s = names16[code - ax_reg];
15976       break;
15977     case es_reg: case ss_reg: case cs_reg:
15978     case ds_reg: case fs_reg: case gs_reg:
15979       s = names_seg[code - es_reg];
15980       break;
15981     case al_reg: case ah_reg: case cl_reg: case ch_reg:
15982     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15983       USED_REX (0);
15984       if (rex)
15985         s = names8rex[code - al_reg];
15986       else
15987         s = names8[code - al_reg];
15988       break;
15989     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15990     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15991       USED_REX (REX_W);
15992       if (rex & REX_W)
15993         s = names64[code - eAX_reg];
15994       else
15995         {
15996           if (sizeflag & DFLAG)
15997             s = names32[code - eAX_reg];
15998           else
15999             s = names16[code - eAX_reg];
16000           used_prefixes |= (prefixes & PREFIX_DATA);
16001         }
16002       break;
16003     case z_mode_ax_reg:
16004       if ((rex & REX_W) || (sizeflag & DFLAG))
16005         s = *names32;
16006       else
16007         s = *names16;
16008       if (!(rex & REX_W))
16009         used_prefixes |= (prefixes & PREFIX_DATA);
16010       break;
16011     default:
16012       s = INTERNAL_DISASSEMBLER_ERROR;
16013       break;
16014     }
16015   oappend (s);
16016 }
16017
16018 static void
16019 OP_I (int bytemode, int sizeflag)
16020 {
16021   bfd_signed_vma op;
16022   bfd_signed_vma mask = -1;
16023
16024   switch (bytemode)
16025     {
16026     case b_mode:
16027       FETCH_DATA (the_info, codep + 1);
16028       op = *codep++;
16029       mask = 0xff;
16030       break;
16031     case q_mode:
16032       if (address_mode == mode_64bit)
16033         {
16034           op = get32s ();
16035           break;
16036         }
16037       /* Fall through.  */
16038     case v_mode:
16039       USED_REX (REX_W);
16040       if (rex & REX_W)
16041         op = get32s ();
16042       else
16043         {
16044           if (sizeflag & DFLAG)
16045             {
16046               op = get32 ();
16047               mask = 0xffffffff;
16048             }
16049           else
16050             {
16051               op = get16 ();
16052               mask = 0xfffff;
16053             }
16054           used_prefixes |= (prefixes & PREFIX_DATA);
16055         }
16056       break;
16057     case w_mode:
16058       mask = 0xfffff;
16059       op = get16 ();
16060       break;
16061     case const_1_mode:
16062       if (intel_syntax)
16063         oappend ("1");
16064       return;
16065     default:
16066       oappend (INTERNAL_DISASSEMBLER_ERROR);
16067       return;
16068     }
16069
16070   op &= mask;
16071   scratchbuf[0] = '$';
16072   print_operand_value (scratchbuf + 1, 1, op);
16073   oappend_maybe_intel (scratchbuf);
16074   scratchbuf[0] = '\0';
16075 }
16076
16077 static void
16078 OP_I64 (int bytemode, int sizeflag)
16079 {
16080   bfd_signed_vma op;
16081   bfd_signed_vma mask = -1;
16082
16083   if (address_mode != mode_64bit)
16084     {
16085       OP_I (bytemode, sizeflag);
16086       return;
16087     }
16088
16089   switch (bytemode)
16090     {
16091     case b_mode:
16092       FETCH_DATA (the_info, codep + 1);
16093       op = *codep++;
16094       mask = 0xff;
16095       break;
16096     case v_mode:
16097       USED_REX (REX_W);
16098       if (rex & REX_W)
16099         op = get64 ();
16100       else
16101         {
16102           if (sizeflag & DFLAG)
16103             {
16104               op = get32 ();
16105               mask = 0xffffffff;
16106             }
16107           else
16108             {
16109               op = get16 ();
16110               mask = 0xfffff;
16111             }
16112           used_prefixes |= (prefixes & PREFIX_DATA);
16113         }
16114       break;
16115     case w_mode:
16116       mask = 0xfffff;
16117       op = get16 ();
16118       break;
16119     default:
16120       oappend (INTERNAL_DISASSEMBLER_ERROR);
16121       return;
16122     }
16123
16124   op &= mask;
16125   scratchbuf[0] = '$';
16126   print_operand_value (scratchbuf + 1, 1, op);
16127   oappend_maybe_intel (scratchbuf);
16128   scratchbuf[0] = '\0';
16129 }
16130
16131 static void
16132 OP_sI (int bytemode, int sizeflag)
16133 {
16134   bfd_signed_vma op;
16135
16136   switch (bytemode)
16137     {
16138     case b_mode:
16139     case b_T_mode:
16140       FETCH_DATA (the_info, codep + 1);
16141       op = *codep++;
16142       if ((op & 0x80) != 0)
16143         op -= 0x100;
16144       if (bytemode == b_T_mode)
16145         {
16146           if (address_mode != mode_64bit
16147               || !((sizeflag & DFLAG) || (rex & REX_W)))
16148             {
16149               /* The operand-size prefix is overridden by a REX prefix.  */
16150               if ((sizeflag & DFLAG) || (rex & REX_W))
16151                 op &= 0xffffffff;
16152               else
16153                 op &= 0xffff;
16154           }
16155         }
16156       else
16157         {
16158           if (!(rex & REX_W))
16159             {
16160               if (sizeflag & DFLAG)
16161                 op &= 0xffffffff;
16162               else
16163                 op &= 0xffff;
16164             }
16165         }
16166       break;
16167     case v_mode:
16168       /* The operand-size prefix is overridden by a REX prefix.  */
16169       if ((sizeflag & DFLAG) || (rex & REX_W))
16170         op = get32s ();
16171       else
16172         op = get16 ();
16173       break;
16174     default:
16175       oappend (INTERNAL_DISASSEMBLER_ERROR);
16176       return;
16177     }
16178
16179   scratchbuf[0] = '$';
16180   print_operand_value (scratchbuf + 1, 1, op);
16181   oappend_maybe_intel (scratchbuf);
16182 }
16183
16184 static void
16185 OP_J (int bytemode, int sizeflag)
16186 {
16187   bfd_vma disp;
16188   bfd_vma mask = -1;
16189   bfd_vma segment = 0;
16190
16191   switch (bytemode)
16192     {
16193     case b_mode:
16194       FETCH_DATA (the_info, codep + 1);
16195       disp = *codep++;
16196       if ((disp & 0x80) != 0)
16197         disp -= 0x100;
16198       break;
16199     case v_mode:
16200       if (isa64 == amd64)
16201         USED_REX (REX_W);
16202       if ((sizeflag & DFLAG)
16203           || (address_mode == mode_64bit
16204               && (isa64 != amd64 || (rex & REX_W))))
16205         disp = get32s ();
16206       else
16207         {
16208           disp = get16 ();
16209           if ((disp & 0x8000) != 0)
16210             disp -= 0x10000;
16211           /* In 16bit mode, address is wrapped around at 64k within
16212              the same segment.  Otherwise, a data16 prefix on a jump
16213              instruction means that the pc is masked to 16 bits after
16214              the displacement is added!  */
16215           mask = 0xffff;
16216           if ((prefixes & PREFIX_DATA) == 0)
16217             segment = ((start_pc + (codep - start_codep))
16218                        & ~((bfd_vma) 0xffff));
16219         }
16220       if (address_mode != mode_64bit
16221           || (isa64 == amd64 && !(rex & REX_W)))
16222         used_prefixes |= (prefixes & PREFIX_DATA);
16223       break;
16224     default:
16225       oappend (INTERNAL_DISASSEMBLER_ERROR);
16226       return;
16227     }
16228   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
16229   set_op (disp, 0);
16230   print_operand_value (scratchbuf, 1, disp);
16231   oappend (scratchbuf);
16232 }
16233
16234 static void
16235 OP_SEG (int bytemode, int sizeflag)
16236 {
16237   if (bytemode == w_mode)
16238     oappend (names_seg[modrm.reg]);
16239   else
16240     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
16241 }
16242
16243 static void
16244 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
16245 {
16246   int seg, offset;
16247
16248   if (sizeflag & DFLAG)
16249     {
16250       offset = get32 ();
16251       seg = get16 ();
16252     }
16253   else
16254     {
16255       offset = get16 ();
16256       seg = get16 ();
16257     }
16258   used_prefixes |= (prefixes & PREFIX_DATA);
16259   if (intel_syntax)
16260     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
16261   else
16262     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
16263   oappend (scratchbuf);
16264 }
16265
16266 static void
16267 OP_OFF (int bytemode, int sizeflag)
16268 {
16269   bfd_vma off;
16270
16271   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
16272     intel_operand_size (bytemode, sizeflag);
16273   append_seg ();
16274
16275   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
16276     off = get32 ();
16277   else
16278     off = get16 ();
16279
16280   if (intel_syntax)
16281     {
16282       if (!active_seg_prefix)
16283         {
16284           oappend (names_seg[ds_reg - es_reg]);
16285           oappend (":");
16286         }
16287     }
16288   print_operand_value (scratchbuf, 1, off);
16289   oappend (scratchbuf);
16290 }
16291
16292 static void
16293 OP_OFF64 (int bytemode, int sizeflag)
16294 {
16295   bfd_vma off;
16296
16297   if (address_mode != mode_64bit
16298       || (prefixes & PREFIX_ADDR))
16299     {
16300       OP_OFF (bytemode, sizeflag);
16301       return;
16302     }
16303
16304   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
16305     intel_operand_size (bytemode, sizeflag);
16306   append_seg ();
16307
16308   off = get64 ();
16309
16310   if (intel_syntax)
16311     {
16312       if (!active_seg_prefix)
16313         {
16314           oappend (names_seg[ds_reg - es_reg]);
16315           oappend (":");
16316         }
16317     }
16318   print_operand_value (scratchbuf, 1, off);
16319   oappend (scratchbuf);
16320 }
16321
16322 static void
16323 ptr_reg (int code, int sizeflag)
16324 {
16325   const char *s;
16326
16327   *obufp++ = open_char;
16328   used_prefixes |= (prefixes & PREFIX_ADDR);
16329   if (address_mode == mode_64bit)
16330     {
16331       if (!(sizeflag & AFLAG))
16332         s = names32[code - eAX_reg];
16333       else
16334         s = names64[code - eAX_reg];
16335     }
16336   else if (sizeflag & AFLAG)
16337     s = names32[code - eAX_reg];
16338   else
16339     s = names16[code - eAX_reg];
16340   oappend (s);
16341   *obufp++ = close_char;
16342   *obufp = 0;
16343 }
16344
16345 static void
16346 OP_ESreg (int code, int sizeflag)
16347 {
16348   if (intel_syntax)
16349     {
16350       switch (codep[-1])
16351         {
16352         case 0x6d:      /* insw/insl */
16353           intel_operand_size (z_mode, sizeflag);
16354           break;
16355         case 0xa5:      /* movsw/movsl/movsq */
16356         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
16357         case 0xab:      /* stosw/stosl */
16358         case 0xaf:      /* scasw/scasl */
16359           intel_operand_size (v_mode, sizeflag);
16360           break;
16361         default:
16362           intel_operand_size (b_mode, sizeflag);
16363         }
16364     }
16365   oappend_maybe_intel ("%es:");
16366   ptr_reg (code, sizeflag);
16367 }
16368
16369 static void
16370 OP_DSreg (int code, int sizeflag)
16371 {
16372   if (intel_syntax)
16373     {
16374       switch (codep[-1])
16375         {
16376         case 0x6f:      /* outsw/outsl */
16377           intel_operand_size (z_mode, sizeflag);
16378           break;
16379         case 0xa5:      /* movsw/movsl/movsq */
16380         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
16381         case 0xad:      /* lodsw/lodsl/lodsq */
16382           intel_operand_size (v_mode, sizeflag);
16383           break;
16384         default:
16385           intel_operand_size (b_mode, sizeflag);
16386         }
16387     }
16388   /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
16389      default segment register DS is printed.  */
16390   if (!active_seg_prefix)
16391     active_seg_prefix = PREFIX_DS;
16392   append_seg ();
16393   ptr_reg (code, sizeflag);
16394 }
16395
16396 static void
16397 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16398 {
16399   int add;
16400   if (rex & REX_R)
16401     {
16402       USED_REX (REX_R);
16403       add = 8;
16404     }
16405   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
16406     {
16407       all_prefixes[last_lock_prefix] = 0;
16408       used_prefixes |= PREFIX_LOCK;
16409       add = 8;
16410     }
16411   else
16412     add = 0;
16413   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
16414   oappend_maybe_intel (scratchbuf);
16415 }
16416
16417 static void
16418 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16419 {
16420   int add;
16421   USED_REX (REX_R);
16422   if (rex & REX_R)
16423     add = 8;
16424   else
16425     add = 0;
16426   if (intel_syntax)
16427     sprintf (scratchbuf, "db%d", modrm.reg + add);
16428   else
16429     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
16430   oappend (scratchbuf);
16431 }
16432
16433 static void
16434 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16435 {
16436   sprintf (scratchbuf, "%%tr%d", modrm.reg);
16437   oappend_maybe_intel (scratchbuf);
16438 }
16439
16440 static void
16441 OP_R (int bytemode, int sizeflag)
16442 {
16443   /* Skip mod/rm byte.  */
16444   MODRM_CHECK;
16445   codep++;
16446   OP_E_register (bytemode, sizeflag);
16447 }
16448
16449 static void
16450 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16451 {
16452   int reg = modrm.reg;
16453   const char **names;
16454
16455   used_prefixes |= (prefixes & PREFIX_DATA);
16456   if (prefixes & PREFIX_DATA)
16457     {
16458       names = names_xmm;
16459       USED_REX (REX_R);
16460       if (rex & REX_R)
16461         reg += 8;
16462     }
16463   else
16464     names = names_mm;
16465   oappend (names[reg]);
16466 }
16467
16468 static void
16469 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16470 {
16471   int reg = modrm.reg;
16472   const char **names;
16473
16474   USED_REX (REX_R);
16475   if (rex & REX_R)
16476     reg += 8;
16477   if (vex.evex)
16478     {
16479       if (!vex.r)
16480         reg += 16;
16481     }
16482
16483   if (need_vex
16484       && bytemode != xmm_mode
16485       && bytemode != xmmq_mode
16486       && bytemode != evex_half_bcst_xmmq_mode
16487       && bytemode != ymm_mode
16488       && bytemode != scalar_mode)
16489     {
16490       switch (vex.length)
16491         {
16492         case 128:
16493           names = names_xmm;
16494           break;
16495         case 256:
16496           if (vex.w
16497               || (bytemode != vex_vsib_q_w_dq_mode
16498                   && bytemode != vex_vsib_q_w_d_mode))
16499             names = names_ymm;
16500           else
16501             names = names_xmm;
16502           break;
16503         case 512:
16504           names = names_zmm;
16505           break;
16506         default:
16507           abort ();
16508         }
16509     }
16510   else if (bytemode == xmmq_mode
16511            || bytemode == evex_half_bcst_xmmq_mode)
16512     {
16513       switch (vex.length)
16514         {
16515         case 128:
16516         case 256:
16517           names = names_xmm;
16518           break;
16519         case 512:
16520           names = names_ymm;
16521           break;
16522         default:
16523           abort ();
16524         }
16525     }
16526   else if (bytemode == ymm_mode)
16527     names = names_ymm;
16528   else
16529     names = names_xmm;
16530   oappend (names[reg]);
16531 }
16532
16533 static void
16534 OP_EM (int bytemode, int sizeflag)
16535 {
16536   int reg;
16537   const char **names;
16538
16539   if (modrm.mod != 3)
16540     {
16541       if (intel_syntax
16542           && (bytemode == v_mode || bytemode == v_swap_mode))
16543         {
16544           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16545           used_prefixes |= (prefixes & PREFIX_DATA);
16546         }
16547       OP_E (bytemode, sizeflag);
16548       return;
16549     }
16550
16551   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
16552     swap_operand ();
16553
16554   /* Skip mod/rm byte.  */
16555   MODRM_CHECK;
16556   codep++;
16557   used_prefixes |= (prefixes & PREFIX_DATA);
16558   reg = modrm.rm;
16559   if (prefixes & PREFIX_DATA)
16560     {
16561       names = names_xmm;
16562       USED_REX (REX_B);
16563       if (rex & REX_B)
16564         reg += 8;
16565     }
16566   else
16567     names = names_mm;
16568   oappend (names[reg]);
16569 }
16570
16571 /* cvt* are the only instructions in sse2 which have
16572    both SSE and MMX operands and also have 0x66 prefix
16573    in their opcode. 0x66 was originally used to differentiate
16574    between SSE and MMX instruction(operands). So we have to handle the
16575    cvt* separately using OP_EMC and OP_MXC */
16576 static void
16577 OP_EMC (int bytemode, int sizeflag)
16578 {
16579   if (modrm.mod != 3)
16580     {
16581       if (intel_syntax && bytemode == v_mode)
16582         {
16583           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16584           used_prefixes |= (prefixes & PREFIX_DATA);
16585         }
16586       OP_E (bytemode, sizeflag);
16587       return;
16588     }
16589
16590   /* Skip mod/rm byte.  */
16591   MODRM_CHECK;
16592   codep++;
16593   used_prefixes |= (prefixes & PREFIX_DATA);
16594   oappend (names_mm[modrm.rm]);
16595 }
16596
16597 static void
16598 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16599 {
16600   used_prefixes |= (prefixes & PREFIX_DATA);
16601   oappend (names_mm[modrm.reg]);
16602 }
16603
16604 static void
16605 OP_EX (int bytemode, int sizeflag)
16606 {
16607   int reg;
16608   const char **names;
16609
16610   /* Skip mod/rm byte.  */
16611   MODRM_CHECK;
16612   codep++;
16613
16614   if (modrm.mod != 3)
16615     {
16616       OP_E_memory (bytemode, sizeflag);
16617       return;
16618     }
16619
16620   reg = modrm.rm;
16621   USED_REX (REX_B);
16622   if (rex & REX_B)
16623     reg += 8;
16624   if (vex.evex)
16625     {
16626       USED_REX (REX_X);
16627       if ((rex & REX_X))
16628         reg += 16;
16629     }
16630
16631   if ((sizeflag & SUFFIX_ALWAYS)
16632       && (bytemode == x_swap_mode
16633           || bytemode == d_swap_mode
16634           || bytemode == dqw_swap_mode
16635           || bytemode == d_scalar_swap_mode
16636           || bytemode == q_swap_mode
16637           || bytemode == q_scalar_swap_mode))
16638     swap_operand ();
16639
16640   if (need_vex
16641       && bytemode != xmm_mode
16642       && bytemode != xmmdw_mode
16643       && bytemode != xmmqd_mode
16644       && bytemode != xmm_mb_mode
16645       && bytemode != xmm_mw_mode
16646       && bytemode != xmm_md_mode
16647       && bytemode != xmm_mq_mode
16648       && bytemode != xmm_mdq_mode
16649       && bytemode != xmmq_mode
16650       && bytemode != evex_half_bcst_xmmq_mode
16651       && bytemode != ymm_mode
16652       && bytemode != d_scalar_mode
16653       && bytemode != d_scalar_swap_mode
16654       && bytemode != q_scalar_mode
16655       && bytemode != q_scalar_swap_mode
16656       && bytemode != vex_scalar_w_dq_mode)
16657     {
16658       switch (vex.length)
16659         {
16660         case 128:
16661           names = names_xmm;
16662           break;
16663         case 256:
16664           names = names_ymm;
16665           break;
16666         case 512:
16667           names = names_zmm;
16668           break;
16669         default:
16670           abort ();
16671         }
16672     }
16673   else if (bytemode == xmmq_mode
16674            || bytemode == evex_half_bcst_xmmq_mode)
16675     {
16676       switch (vex.length)
16677         {
16678         case 128:
16679         case 256:
16680           names = names_xmm;
16681           break;
16682         case 512:
16683           names = names_ymm;
16684           break;
16685         default:
16686           abort ();
16687         }
16688     }
16689   else if (bytemode == ymm_mode)
16690     names = names_ymm;
16691   else
16692     names = names_xmm;
16693   oappend (names[reg]);
16694 }
16695
16696 static void
16697 OP_MS (int bytemode, int sizeflag)
16698 {
16699   if (modrm.mod == 3)
16700     OP_EM (bytemode, sizeflag);
16701   else
16702     BadOp ();
16703 }
16704
16705 static void
16706 OP_XS (int bytemode, int sizeflag)
16707 {
16708   if (modrm.mod == 3)
16709     OP_EX (bytemode, sizeflag);
16710   else
16711     BadOp ();
16712 }
16713
16714 static void
16715 OP_M (int bytemode, int sizeflag)
16716 {
16717   if (modrm.mod == 3)
16718     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
16719     BadOp ();
16720   else
16721     OP_E (bytemode, sizeflag);
16722 }
16723
16724 static void
16725 OP_0f07 (int bytemode, int sizeflag)
16726 {
16727   if (modrm.mod != 3 || modrm.rm != 0)
16728     BadOp ();
16729   else
16730     OP_E (bytemode, sizeflag);
16731 }
16732
16733 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
16734    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
16735
16736 static void
16737 NOP_Fixup1 (int bytemode, int sizeflag)
16738 {
16739   if ((prefixes & PREFIX_DATA) != 0
16740       || (rex != 0
16741           && rex != 0x48
16742           && address_mode == mode_64bit))
16743     OP_REG (bytemode, sizeflag);
16744   else
16745     strcpy (obuf, "nop");
16746 }
16747
16748 static void
16749 NOP_Fixup2 (int bytemode, int sizeflag)
16750 {
16751   if ((prefixes & PREFIX_DATA) != 0
16752       || (rex != 0
16753           && rex != 0x48
16754           && address_mode == mode_64bit))
16755     OP_IMREG (bytemode, sizeflag);
16756 }
16757
16758 static const char *const Suffix3DNow[] = {
16759 /* 00 */        NULL,           NULL,           NULL,           NULL,
16760 /* 04 */        NULL,           NULL,           NULL,           NULL,
16761 /* 08 */        NULL,           NULL,           NULL,           NULL,
16762 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
16763 /* 10 */        NULL,           NULL,           NULL,           NULL,
16764 /* 14 */        NULL,           NULL,           NULL,           NULL,
16765 /* 18 */        NULL,           NULL,           NULL,           NULL,
16766 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
16767 /* 20 */        NULL,           NULL,           NULL,           NULL,
16768 /* 24 */        NULL,           NULL,           NULL,           NULL,
16769 /* 28 */        NULL,           NULL,           NULL,           NULL,
16770 /* 2C */        NULL,           NULL,           NULL,           NULL,
16771 /* 30 */        NULL,           NULL,           NULL,           NULL,
16772 /* 34 */        NULL,           NULL,           NULL,           NULL,
16773 /* 38 */        NULL,           NULL,           NULL,           NULL,
16774 /* 3C */        NULL,           NULL,           NULL,           NULL,
16775 /* 40 */        NULL,           NULL,           NULL,           NULL,
16776 /* 44 */        NULL,           NULL,           NULL,           NULL,
16777 /* 48 */        NULL,           NULL,           NULL,           NULL,
16778 /* 4C */        NULL,           NULL,           NULL,           NULL,
16779 /* 50 */        NULL,           NULL,           NULL,           NULL,
16780 /* 54 */        NULL,           NULL,           NULL,           NULL,
16781 /* 58 */        NULL,           NULL,           NULL,           NULL,
16782 /* 5C */        NULL,           NULL,           NULL,           NULL,
16783 /* 60 */        NULL,           NULL,           NULL,           NULL,
16784 /* 64 */        NULL,           NULL,           NULL,           NULL,
16785 /* 68 */        NULL,           NULL,           NULL,           NULL,
16786 /* 6C */        NULL,           NULL,           NULL,           NULL,
16787 /* 70 */        NULL,           NULL,           NULL,           NULL,
16788 /* 74 */        NULL,           NULL,           NULL,           NULL,
16789 /* 78 */        NULL,           NULL,           NULL,           NULL,
16790 /* 7C */        NULL,           NULL,           NULL,           NULL,
16791 /* 80 */        NULL,           NULL,           NULL,           NULL,
16792 /* 84 */        NULL,           NULL,           NULL,           NULL,
16793 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
16794 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
16795 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
16796 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
16797 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
16798 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
16799 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
16800 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
16801 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
16802 /* AC */        NULL,           NULL,           "pfacc",        NULL,
16803 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
16804 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
16805 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
16806 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
16807 /* C0 */        NULL,           NULL,           NULL,           NULL,
16808 /* C4 */        NULL,           NULL,           NULL,           NULL,
16809 /* C8 */        NULL,           NULL,           NULL,           NULL,
16810 /* CC */        NULL,           NULL,           NULL,           NULL,
16811 /* D0 */        NULL,           NULL,           NULL,           NULL,
16812 /* D4 */        NULL,           NULL,           NULL,           NULL,
16813 /* D8 */        NULL,           NULL,           NULL,           NULL,
16814 /* DC */        NULL,           NULL,           NULL,           NULL,
16815 /* E0 */        NULL,           NULL,           NULL,           NULL,
16816 /* E4 */        NULL,           NULL,           NULL,           NULL,
16817 /* E8 */        NULL,           NULL,           NULL,           NULL,
16818 /* EC */        NULL,           NULL,           NULL,           NULL,
16819 /* F0 */        NULL,           NULL,           NULL,           NULL,
16820 /* F4 */        NULL,           NULL,           NULL,           NULL,
16821 /* F8 */        NULL,           NULL,           NULL,           NULL,
16822 /* FC */        NULL,           NULL,           NULL,           NULL,
16823 };
16824
16825 static void
16826 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16827 {
16828   const char *mnemonic;
16829
16830   FETCH_DATA (the_info, codep + 1);
16831   /* AMD 3DNow! instructions are specified by an opcode suffix in the
16832      place where an 8-bit immediate would normally go.  ie. the last
16833      byte of the instruction.  */
16834   obufp = mnemonicendp;
16835   mnemonic = Suffix3DNow[*codep++ & 0xff];
16836   if (mnemonic)
16837     oappend (mnemonic);
16838   else
16839     {
16840       /* Since a variable sized modrm/sib chunk is between the start
16841          of the opcode (0x0f0f) and the opcode suffix, we need to do
16842          all the modrm processing first, and don't know until now that
16843          we have a bad opcode.  This necessitates some cleaning up.  */
16844       op_out[0][0] = '\0';
16845       op_out[1][0] = '\0';
16846       BadOp ();
16847     }
16848   mnemonicendp = obufp;
16849 }
16850
16851 static struct op simd_cmp_op[] =
16852 {
16853   { STRING_COMMA_LEN ("eq") },
16854   { STRING_COMMA_LEN ("lt") },
16855   { STRING_COMMA_LEN ("le") },
16856   { STRING_COMMA_LEN ("unord") },
16857   { STRING_COMMA_LEN ("neq") },
16858   { STRING_COMMA_LEN ("nlt") },
16859   { STRING_COMMA_LEN ("nle") },
16860   { STRING_COMMA_LEN ("ord") }
16861 };
16862
16863 static void
16864 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16865 {
16866   unsigned int cmp_type;
16867
16868   FETCH_DATA (the_info, codep + 1);
16869   cmp_type = *codep++ & 0xff;
16870   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
16871     {
16872       char suffix [3];
16873       char *p = mnemonicendp - 2;
16874       suffix[0] = p[0];
16875       suffix[1] = p[1];
16876       suffix[2] = '\0';
16877       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16878       mnemonicendp += simd_cmp_op[cmp_type].len;
16879     }
16880   else
16881     {
16882       /* We have a reserved extension byte.  Output it directly.  */
16883       scratchbuf[0] = '$';
16884       print_operand_value (scratchbuf + 1, 1, cmp_type);
16885       oappend_maybe_intel (scratchbuf);
16886       scratchbuf[0] = '\0';
16887     }
16888 }
16889
16890 static void
16891 OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED,
16892           int sizeflag ATTRIBUTE_UNUSED)
16893 {
16894   /* mwaitx %eax,%ecx,%ebx */
16895   if (!intel_syntax)
16896     {
16897       const char **names = (address_mode == mode_64bit
16898                             ? names64 : names32);
16899       strcpy (op_out[0], names[0]);
16900       strcpy (op_out[1], names[1]);
16901       strcpy (op_out[2], names[3]);
16902       two_source_ops = 1;
16903     }
16904   /* Skip mod/rm byte.  */
16905   MODRM_CHECK;
16906   codep++;
16907 }
16908
16909 static void
16910 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
16911           int sizeflag ATTRIBUTE_UNUSED)
16912 {
16913   /* mwait %eax,%ecx  */
16914   if (!intel_syntax)
16915     {
16916       const char **names = (address_mode == mode_64bit
16917                             ? names64 : names32);
16918       strcpy (op_out[0], names[0]);
16919       strcpy (op_out[1], names[1]);
16920       two_source_ops = 1;
16921     }
16922   /* Skip mod/rm byte.  */
16923   MODRM_CHECK;
16924   codep++;
16925 }
16926
16927 static void
16928 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
16929             int sizeflag ATTRIBUTE_UNUSED)
16930 {
16931   /* monitor %eax,%ecx,%edx"  */
16932   if (!intel_syntax)
16933     {
16934       const char **op1_names;
16935       const char **names = (address_mode == mode_64bit
16936                             ? names64 : names32);
16937
16938       if (!(prefixes & PREFIX_ADDR))
16939         op1_names = (address_mode == mode_16bit
16940                      ? names16 : names);
16941       else
16942         {
16943           /* Remove "addr16/addr32".  */
16944           all_prefixes[last_addr_prefix] = 0;
16945           op1_names = (address_mode != mode_32bit
16946                        ? names32 : names16);
16947           used_prefixes |= PREFIX_ADDR;
16948         }
16949       strcpy (op_out[0], op1_names[0]);
16950       strcpy (op_out[1], names[1]);
16951       strcpy (op_out[2], names[2]);
16952       two_source_ops = 1;
16953     }
16954   /* Skip mod/rm byte.  */
16955   MODRM_CHECK;
16956   codep++;
16957 }
16958
16959 static void
16960 BadOp (void)
16961 {
16962   /* Throw away prefixes and 1st. opcode byte.  */
16963   codep = insn_codep + 1;
16964   oappend ("(bad)");
16965 }
16966
16967 static void
16968 REP_Fixup (int bytemode, int sizeflag)
16969 {
16970   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
16971      lods and stos.  */
16972   if (prefixes & PREFIX_REPZ)
16973     all_prefixes[last_repz_prefix] = REP_PREFIX;
16974
16975   switch (bytemode)
16976     {
16977     case al_reg:
16978     case eAX_reg:
16979     case indir_dx_reg:
16980       OP_IMREG (bytemode, sizeflag);
16981       break;
16982     case eDI_reg:
16983       OP_ESreg (bytemode, sizeflag);
16984       break;
16985     case eSI_reg:
16986       OP_DSreg (bytemode, sizeflag);
16987       break;
16988     default:
16989       abort ();
16990       break;
16991     }
16992 }
16993
16994 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
16995    "bnd".  */
16996
16997 static void
16998 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16999 {
17000   if (prefixes & PREFIX_REPNZ)
17001     all_prefixes[last_repnz_prefix] = BND_PREFIX;
17002 }
17003
17004 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
17005    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
17006  */
17007
17008 static void
17009 HLE_Fixup1 (int bytemode, int sizeflag)
17010 {
17011   if (modrm.mod != 3
17012       && (prefixes & PREFIX_LOCK) != 0)
17013     {
17014       if (prefixes & PREFIX_REPZ)
17015         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
17016       if (prefixes & PREFIX_REPNZ)
17017         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
17018     }
17019
17020   OP_E (bytemode, sizeflag);
17021 }
17022
17023 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
17024    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
17025  */
17026
17027 static void
17028 HLE_Fixup2 (int bytemode, int sizeflag)
17029 {
17030   if (modrm.mod != 3)
17031     {
17032       if (prefixes & PREFIX_REPZ)
17033         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
17034       if (prefixes & PREFIX_REPNZ)
17035         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
17036     }
17037
17038   OP_E (bytemode, sizeflag);
17039 }
17040
17041 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
17042    "xrelease" for memory operand.  No check for LOCK prefix.   */
17043
17044 static void
17045 HLE_Fixup3 (int bytemode, int sizeflag)
17046 {
17047   if (modrm.mod != 3
17048       && last_repz_prefix > last_repnz_prefix
17049       && (prefixes & PREFIX_REPZ) != 0)
17050     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
17051
17052   OP_E (bytemode, sizeflag);
17053 }
17054
17055 static void
17056 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
17057 {
17058   USED_REX (REX_W);
17059   if (rex & REX_W)
17060     {
17061       /* Change cmpxchg8b to cmpxchg16b.  */
17062       char *p = mnemonicendp - 2;
17063       mnemonicendp = stpcpy (p, "16b");
17064       bytemode = o_mode;
17065     }
17066   else if ((prefixes & PREFIX_LOCK) != 0)
17067     {
17068       if (prefixes & PREFIX_REPZ)
17069         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
17070       if (prefixes & PREFIX_REPNZ)
17071         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
17072     }
17073
17074   OP_M (bytemode, sizeflag);
17075 }
17076
17077 static void
17078 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
17079 {
17080   const char **names;
17081
17082   if (need_vex)
17083     {
17084       switch (vex.length)
17085         {
17086         case 128:
17087           names = names_xmm;
17088           break;
17089         case 256:
17090           names = names_ymm;
17091           break;
17092         default:
17093           abort ();
17094         }
17095     }
17096   else
17097     names = names_xmm;
17098   oappend (names[reg]);
17099 }
17100
17101 static void
17102 CRC32_Fixup (int bytemode, int sizeflag)
17103 {
17104   /* Add proper suffix to "crc32".  */
17105   char *p = mnemonicendp;
17106
17107   switch (bytemode)
17108     {
17109     case b_mode:
17110       if (intel_syntax)
17111         goto skip;
17112
17113       *p++ = 'b';
17114       break;
17115     case v_mode:
17116       if (intel_syntax)
17117         goto skip;
17118
17119       USED_REX (REX_W);
17120       if (rex & REX_W)
17121         *p++ = 'q';
17122       else
17123         {
17124           if (sizeflag & DFLAG)
17125             *p++ = 'l';
17126           else
17127             *p++ = 'w';
17128           used_prefixes |= (prefixes & PREFIX_DATA);
17129         }
17130       break;
17131     default:
17132       oappend (INTERNAL_DISASSEMBLER_ERROR);
17133       break;
17134     }
17135   mnemonicendp = p;
17136   *p = '\0';
17137
17138 skip:
17139   if (modrm.mod == 3)
17140     {
17141       int add;
17142
17143       /* Skip mod/rm byte.  */
17144       MODRM_CHECK;
17145       codep++;
17146
17147       USED_REX (REX_B);
17148       add = (rex & REX_B) ? 8 : 0;
17149       if (bytemode == b_mode)
17150         {
17151           USED_REX (0);
17152           if (rex)
17153             oappend (names8rex[modrm.rm + add]);
17154           else
17155             oappend (names8[modrm.rm + add]);
17156         }
17157       else
17158         {
17159           USED_REX (REX_W);
17160           if (rex & REX_W)
17161             oappend (names64[modrm.rm + add]);
17162           else if ((prefixes & PREFIX_DATA))
17163             oappend (names16[modrm.rm + add]);
17164           else
17165             oappend (names32[modrm.rm + add]);
17166         }
17167     }
17168   else
17169     OP_E (bytemode, sizeflag);
17170 }
17171
17172 static void
17173 FXSAVE_Fixup (int bytemode, int sizeflag)
17174 {
17175   /* Add proper suffix to "fxsave" and "fxrstor".  */
17176   USED_REX (REX_W);
17177   if (rex & REX_W)
17178     {
17179       char *p = mnemonicendp;
17180       *p++ = '6';
17181       *p++ = '4';
17182       *p = '\0';
17183       mnemonicendp = p;
17184     }
17185   OP_M (bytemode, sizeflag);
17186 }
17187
17188 /* Display the destination register operand for instructions with
17189    VEX. */
17190
17191 static void
17192 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17193 {
17194   int reg;
17195   const char **names;
17196
17197   if (!need_vex)
17198     abort ();
17199
17200   if (!need_vex_reg)
17201     return;
17202
17203   reg = vex.register_specifier;
17204   if (vex.evex)
17205     {
17206       if (!vex.v)
17207         reg += 16;
17208     }
17209
17210   if (bytemode == vex_scalar_mode)
17211     {
17212       oappend (names_xmm[reg]);
17213       return;
17214     }
17215
17216   switch (vex.length)
17217     {
17218     case 128:
17219       switch (bytemode)
17220         {
17221         case vex_mode:
17222         case vex128_mode:
17223         case vex_vsib_q_w_dq_mode:
17224         case vex_vsib_q_w_d_mode:
17225           names = names_xmm;
17226           break;
17227         case dq_mode:
17228           if (vex.w)
17229             names = names64;
17230           else
17231             names = names32;
17232           break;
17233         case mask_bd_mode:
17234         case mask_mode:
17235           if (reg > 0x7)
17236             {
17237               oappend ("(bad)");
17238               return;
17239             }
17240           names = names_mask;
17241           break;
17242         default:
17243           abort ();
17244           return;
17245         }
17246       break;
17247     case 256:
17248       switch (bytemode)
17249         {
17250         case vex_mode:
17251         case vex256_mode:
17252           names = names_ymm;
17253           break;
17254         case vex_vsib_q_w_dq_mode:
17255         case vex_vsib_q_w_d_mode:
17256           names = vex.w ? names_ymm : names_xmm;
17257           break;
17258         case mask_bd_mode:
17259         case mask_mode:
17260           if (reg > 0x7)
17261             {
17262               oappend ("(bad)");
17263               return;
17264             }
17265           names = names_mask;
17266           break;
17267         default:
17268           abort ();
17269           return;
17270         }
17271       break;
17272     case 512:
17273       names = names_zmm;
17274       break;
17275     default:
17276       abort ();
17277       break;
17278     }
17279   oappend (names[reg]);
17280 }
17281
17282 /* Get the VEX immediate byte without moving codep.  */
17283
17284 static unsigned char
17285 get_vex_imm8 (int sizeflag, int opnum)
17286 {
17287   int bytes_before_imm = 0;
17288
17289   if (modrm.mod != 3)
17290     {
17291       /* There are SIB/displacement bytes.  */
17292       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
17293         {
17294           /* 32/64 bit address mode */
17295           int base = modrm.rm;
17296
17297           /* Check SIB byte.  */
17298           if (base == 4)
17299             {
17300               FETCH_DATA (the_info, codep + 1);
17301               base = *codep & 7;
17302               /* When decoding the third source, don't increase
17303                  bytes_before_imm as this has already been incremented
17304                  by one in OP_E_memory while decoding the second
17305                  source operand.  */
17306               if (opnum == 0)
17307                 bytes_before_imm++;
17308             }
17309
17310           /* Don't increase bytes_before_imm when decoding the third source,
17311              it has already been incremented by OP_E_memory while decoding
17312              the second source operand.  */
17313           if (opnum == 0)
17314             {
17315               switch (modrm.mod)
17316                 {
17317                   case 0:
17318                     /* When modrm.rm == 5 or modrm.rm == 4 and base in
17319                        SIB == 5, there is a 4 byte displacement.  */
17320                     if (base != 5)
17321                       /* No displacement. */
17322                       break;
17323                     /* Fall through.  */
17324                   case 2:
17325                     /* 4 byte displacement.  */
17326                     bytes_before_imm += 4;
17327                     break;
17328                   case 1:
17329                     /* 1 byte displacement.  */
17330                     bytes_before_imm++;
17331                     break;
17332                 }
17333             }
17334         }
17335       else
17336         {
17337           /* 16 bit address mode */
17338           /* Don't increase bytes_before_imm when decoding the third source,
17339              it has already been incremented by OP_E_memory while decoding
17340              the second source operand.  */
17341           if (opnum == 0)
17342             {
17343               switch (modrm.mod)
17344                 {
17345                 case 0:
17346                   /* When modrm.rm == 6, there is a 2 byte displacement.  */
17347                   if (modrm.rm != 6)
17348                     /* No displacement. */
17349                     break;
17350                   /* Fall through.  */
17351                 case 2:
17352                   /* 2 byte displacement.  */
17353                   bytes_before_imm += 2;
17354                   break;
17355                 case 1:
17356                   /* 1 byte displacement: when decoding the third source,
17357                      don't increase bytes_before_imm as this has already
17358                      been incremented by one in OP_E_memory while decoding
17359                      the second source operand.  */
17360                   if (opnum == 0)
17361                     bytes_before_imm++;
17362
17363                   break;
17364                 }
17365             }
17366         }
17367     }
17368
17369   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
17370   return codep [bytes_before_imm];
17371 }
17372
17373 static void
17374 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
17375 {
17376   const char **names;
17377
17378   if (reg == -1 && modrm.mod != 3)
17379     {
17380       OP_E_memory (bytemode, sizeflag);
17381       return;
17382     }
17383   else
17384     {
17385       if (reg == -1)
17386         {
17387           reg = modrm.rm;
17388           USED_REX (REX_B);
17389           if (rex & REX_B)
17390             reg += 8;
17391         }
17392       else if (reg > 7 && address_mode != mode_64bit)
17393         BadOp ();
17394     }
17395
17396   switch (vex.length)
17397     {
17398     case 128:
17399       names = names_xmm;
17400       break;
17401     case 256:
17402       names = names_ymm;
17403       break;
17404     default:
17405       abort ();
17406     }
17407   oappend (names[reg]);
17408 }
17409
17410 static void
17411 OP_EX_VexImmW (int bytemode, int sizeflag)
17412 {
17413   int reg = -1;
17414   static unsigned char vex_imm8;
17415
17416   if (vex_w_done == 0)
17417     {
17418       vex_w_done = 1;
17419
17420       /* Skip mod/rm byte.  */
17421       MODRM_CHECK;
17422       codep++;
17423
17424       vex_imm8 = get_vex_imm8 (sizeflag, 0);
17425
17426       if (vex.w)
17427           reg = vex_imm8 >> 4;
17428
17429       OP_EX_VexReg (bytemode, sizeflag, reg);
17430     }
17431   else if (vex_w_done == 1)
17432     {
17433       vex_w_done = 2;
17434
17435       if (!vex.w)
17436           reg = vex_imm8 >> 4;
17437
17438       OP_EX_VexReg (bytemode, sizeflag, reg);
17439     }
17440   else
17441     {
17442       /* Output the imm8 directly.  */
17443       scratchbuf[0] = '$';
17444       print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
17445       oappend_maybe_intel (scratchbuf);
17446       scratchbuf[0] = '\0';
17447       codep++;
17448     }
17449 }
17450
17451 static void
17452 OP_Vex_2src (int bytemode, int sizeflag)
17453 {
17454   if (modrm.mod == 3)
17455     {
17456       int reg = modrm.rm;
17457       USED_REX (REX_B);
17458       if (rex & REX_B)
17459         reg += 8;
17460       oappend (names_xmm[reg]);
17461     }
17462   else
17463     {
17464       if (intel_syntax
17465           && (bytemode == v_mode || bytemode == v_swap_mode))
17466         {
17467           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
17468           used_prefixes |= (prefixes & PREFIX_DATA);
17469         }
17470       OP_E (bytemode, sizeflag);
17471     }
17472 }
17473
17474 static void
17475 OP_Vex_2src_1 (int bytemode, int sizeflag)
17476 {
17477   if (modrm.mod == 3)
17478     {
17479       /* Skip mod/rm byte.   */
17480       MODRM_CHECK;
17481       codep++;
17482     }
17483
17484   if (vex.w)
17485     oappend (names_xmm[vex.register_specifier]);
17486   else
17487     OP_Vex_2src (bytemode, sizeflag);
17488 }
17489
17490 static void
17491 OP_Vex_2src_2 (int bytemode, int sizeflag)
17492 {
17493   if (vex.w)
17494     OP_Vex_2src (bytemode, sizeflag);
17495   else
17496     oappend (names_xmm[vex.register_specifier]);
17497 }
17498
17499 static void
17500 OP_EX_VexW (int bytemode, int sizeflag)
17501 {
17502   int reg = -1;
17503
17504   if (!vex_w_done)
17505     {
17506       vex_w_done = 1;
17507
17508       /* Skip mod/rm byte.  */
17509       MODRM_CHECK;
17510       codep++;
17511
17512       if (vex.w)
17513         reg = get_vex_imm8 (sizeflag, 0) >> 4;
17514     }
17515   else
17516     {
17517       if (!vex.w)
17518         reg = get_vex_imm8 (sizeflag, 1) >> 4;
17519     }
17520
17521   OP_EX_VexReg (bytemode, sizeflag, reg);
17522 }
17523
17524 static void
17525 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,
17526              int sizeflag ATTRIBUTE_UNUSED)
17527 {
17528   /* Skip the immediate byte and check for invalid bits.  */
17529   FETCH_DATA (the_info, codep + 1);
17530   if (*codep++ & 0xf)
17531     BadOp ();
17532 }
17533
17534 static void
17535 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17536 {
17537   int reg;
17538   const char **names;
17539
17540   FETCH_DATA (the_info, codep + 1);
17541   reg = *codep++;
17542
17543   if (bytemode != x_mode)
17544     abort ();
17545
17546   if (reg & 0xf)
17547       BadOp ();
17548
17549   reg >>= 4;
17550   if (reg > 7 && address_mode != mode_64bit)
17551     BadOp ();
17552
17553   switch (vex.length)
17554     {
17555     case 128:
17556       names = names_xmm;
17557       break;
17558     case 256:
17559       names = names_ymm;
17560       break;
17561     default:
17562       abort ();
17563     }
17564   oappend (names[reg]);
17565 }
17566
17567 static void
17568 OP_XMM_VexW (int bytemode, int sizeflag)
17569 {
17570   /* Turn off the REX.W bit since it is used for swapping operands
17571      now.  */
17572   rex &= ~REX_W;
17573   OP_XMM (bytemode, sizeflag);
17574 }
17575
17576 static void
17577 OP_EX_Vex (int bytemode, int sizeflag)
17578 {
17579   if (modrm.mod != 3)
17580     {
17581       if (vex.register_specifier != 0)
17582         BadOp ();
17583       need_vex_reg = 0;
17584     }
17585   OP_EX (bytemode, sizeflag);
17586 }
17587
17588 static void
17589 OP_XMM_Vex (int bytemode, int sizeflag)
17590 {
17591   if (modrm.mod != 3)
17592     {
17593       if (vex.register_specifier != 0)
17594         BadOp ();
17595       need_vex_reg = 0;
17596     }
17597   OP_XMM (bytemode, sizeflag);
17598 }
17599
17600 static void
17601 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17602 {
17603   switch (vex.length)
17604     {
17605     case 128:
17606       mnemonicendp = stpcpy (obuf, "vzeroupper");
17607       break;
17608     case 256:
17609       mnemonicendp = stpcpy (obuf, "vzeroall");
17610       break;
17611     default:
17612       abort ();
17613     }
17614 }
17615
17616 static struct op vex_cmp_op[] =
17617 {
17618   { STRING_COMMA_LEN ("eq") },
17619   { STRING_COMMA_LEN ("lt") },
17620   { STRING_COMMA_LEN ("le") },
17621   { STRING_COMMA_LEN ("unord") },
17622   { STRING_COMMA_LEN ("neq") },
17623   { STRING_COMMA_LEN ("nlt") },
17624   { STRING_COMMA_LEN ("nle") },
17625   { STRING_COMMA_LEN ("ord") },
17626   { STRING_COMMA_LEN ("eq_uq") },
17627   { STRING_COMMA_LEN ("nge") },
17628   { STRING_COMMA_LEN ("ngt") },
17629   { STRING_COMMA_LEN ("false") },
17630   { STRING_COMMA_LEN ("neq_oq") },
17631   { STRING_COMMA_LEN ("ge") },
17632   { STRING_COMMA_LEN ("gt") },
17633   { STRING_COMMA_LEN ("true") },
17634   { STRING_COMMA_LEN ("eq_os") },
17635   { STRING_COMMA_LEN ("lt_oq") },
17636   { STRING_COMMA_LEN ("le_oq") },
17637   { STRING_COMMA_LEN ("unord_s") },
17638   { STRING_COMMA_LEN ("neq_us") },
17639   { STRING_COMMA_LEN ("nlt_uq") },
17640   { STRING_COMMA_LEN ("nle_uq") },
17641   { STRING_COMMA_LEN ("ord_s") },
17642   { STRING_COMMA_LEN ("eq_us") },
17643   { STRING_COMMA_LEN ("nge_uq") },
17644   { STRING_COMMA_LEN ("ngt_uq") },
17645   { STRING_COMMA_LEN ("false_os") },
17646   { STRING_COMMA_LEN ("neq_os") },
17647   { STRING_COMMA_LEN ("ge_oq") },
17648   { STRING_COMMA_LEN ("gt_oq") },
17649   { STRING_COMMA_LEN ("true_us") },
17650 };
17651
17652 static void
17653 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17654 {
17655   unsigned int cmp_type;
17656
17657   FETCH_DATA (the_info, codep + 1);
17658   cmp_type = *codep++ & 0xff;
17659   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
17660     {
17661       char suffix [3];
17662       char *p = mnemonicendp - 2;
17663       suffix[0] = p[0];
17664       suffix[1] = p[1];
17665       suffix[2] = '\0';
17666       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
17667       mnemonicendp += vex_cmp_op[cmp_type].len;
17668     }
17669   else
17670     {
17671       /* We have a reserved extension byte.  Output it directly.  */
17672       scratchbuf[0] = '$';
17673       print_operand_value (scratchbuf + 1, 1, cmp_type);
17674       oappend_maybe_intel (scratchbuf);
17675       scratchbuf[0] = '\0';
17676     }
17677 }
17678
17679 static void
17680 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
17681              int sizeflag ATTRIBUTE_UNUSED)
17682 {
17683   unsigned int cmp_type;
17684
17685   if (!vex.evex)
17686     abort ();
17687
17688   FETCH_DATA (the_info, codep + 1);
17689   cmp_type = *codep++ & 0xff;
17690   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
17691      If it's the case, print suffix, otherwise - print the immediate.  */
17692   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
17693       && cmp_type != 3
17694       && cmp_type != 7)
17695     {
17696       char suffix [3];
17697       char *p = mnemonicendp - 2;
17698
17699       /* vpcmp* can have both one- and two-lettered suffix.  */
17700       if (p[0] == 'p')
17701         {
17702           p++;
17703           suffix[0] = p[0];
17704           suffix[1] = '\0';
17705         }
17706       else
17707         {
17708           suffix[0] = p[0];
17709           suffix[1] = p[1];
17710           suffix[2] = '\0';
17711         }
17712
17713       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
17714       mnemonicendp += simd_cmp_op[cmp_type].len;
17715     }
17716   else
17717     {
17718       /* We have a reserved extension byte.  Output it directly.  */
17719       scratchbuf[0] = '$';
17720       print_operand_value (scratchbuf + 1, 1, cmp_type);
17721       oappend_maybe_intel (scratchbuf);
17722       scratchbuf[0] = '\0';
17723     }
17724 }
17725
17726 static const struct op pclmul_op[] =
17727 {
17728   { STRING_COMMA_LEN ("lql") },
17729   { STRING_COMMA_LEN ("hql") },
17730   { STRING_COMMA_LEN ("lqh") },
17731   { STRING_COMMA_LEN ("hqh") }
17732 };
17733
17734 static void
17735 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
17736               int sizeflag ATTRIBUTE_UNUSED)
17737 {
17738   unsigned int pclmul_type;
17739
17740   FETCH_DATA (the_info, codep + 1);
17741   pclmul_type = *codep++ & 0xff;
17742   switch (pclmul_type)
17743     {
17744     case 0x10:
17745       pclmul_type = 2;
17746       break;
17747     case 0x11:
17748       pclmul_type = 3;
17749       break;
17750     default:
17751       break;
17752     }
17753   if (pclmul_type < ARRAY_SIZE (pclmul_op))
17754     {
17755       char suffix [4];
17756       char *p = mnemonicendp - 3;
17757       suffix[0] = p[0];
17758       suffix[1] = p[1];
17759       suffix[2] = p[2];
17760       suffix[3] = '\0';
17761       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
17762       mnemonicendp += pclmul_op[pclmul_type].len;
17763     }
17764   else
17765     {
17766       /* We have a reserved extension byte.  Output it directly.  */
17767       scratchbuf[0] = '$';
17768       print_operand_value (scratchbuf + 1, 1, pclmul_type);
17769       oappend_maybe_intel (scratchbuf);
17770       scratchbuf[0] = '\0';
17771     }
17772 }
17773
17774 static void
17775 MOVBE_Fixup (int bytemode, int sizeflag)
17776 {
17777   /* Add proper suffix to "movbe".  */
17778   char *p = mnemonicendp;
17779
17780   switch (bytemode)
17781     {
17782     case v_mode:
17783       if (intel_syntax)
17784         goto skip;
17785
17786       USED_REX (REX_W);
17787       if (sizeflag & SUFFIX_ALWAYS)
17788         {
17789           if (rex & REX_W)
17790             *p++ = 'q';
17791           else
17792             {
17793               if (sizeflag & DFLAG)
17794                 *p++ = 'l';
17795               else
17796                 *p++ = 'w';
17797               used_prefixes |= (prefixes & PREFIX_DATA);
17798             }
17799         }
17800       break;
17801     default:
17802       oappend (INTERNAL_DISASSEMBLER_ERROR);
17803       break;
17804     }
17805   mnemonicendp = p;
17806   *p = '\0';
17807
17808 skip:
17809   OP_M (bytemode, sizeflag);
17810 }
17811
17812 static void
17813 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17814 {
17815   int reg;
17816   const char **names;
17817
17818   /* Skip mod/rm byte.  */
17819   MODRM_CHECK;
17820   codep++;
17821
17822   if (vex.w)
17823     names = names64;
17824   else
17825     names = names32;
17826
17827   reg = modrm.rm;
17828   USED_REX (REX_B);
17829   if (rex & REX_B)
17830     reg += 8;
17831
17832   oappend (names[reg]);
17833 }
17834
17835 static void
17836 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17837 {
17838   const char **names;
17839
17840   if (vex.w)
17841     names = names64;
17842   else
17843     names = names32;
17844
17845   oappend (names[vex.register_specifier]);
17846 }
17847
17848 static void
17849 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17850 {
17851   if (!vex.evex
17852       || (bytemode != mask_mode && bytemode != mask_bd_mode))
17853     abort ();
17854
17855   USED_REX (REX_R);
17856   if ((rex & REX_R) != 0 || !vex.r)
17857     {
17858       BadOp ();
17859       return;
17860     }
17861
17862   oappend (names_mask [modrm.reg]);
17863 }
17864
17865 static void
17866 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17867 {
17868   if (!vex.evex
17869       || (bytemode != evex_rounding_mode
17870           && bytemode != evex_sae_mode))
17871     abort ();
17872   if (modrm.mod == 3 && vex.b)
17873     switch (bytemode)
17874       {
17875       case evex_rounding_mode:
17876         oappend (names_rounding[vex.ll]);
17877         break;
17878       case evex_sae_mode:
17879         oappend ("{sae}");
17880         break;
17881       default:
17882         break;
17883       }
17884 }