opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2017 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "dis-asm.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40
  41 #include <setjmp.h>
  42
  43 static int print_insn (bfd_vma, disassemble_info *);
  44 static void dofloat (int);
  45 static void OP_ST (int, int);
  46 static void OP_STi (int, int);
  47 static int putop (const char *, int);
  48 static void oappend (const char *);
  49 static void append_seg (void);
  50 static void OP_indirE (int, int);
  51 static void print_operand_value (char *, int, bfd_vma);
  52 static void OP_E_register (int, int);
  53 static void OP_E_memory (int, int);
  54 static void print_displacement (char *, bfd_vma);
  55 static void OP_E (int, int);
  56 static void OP_G (int, int);
  57 static bfd_vma get64 (void);
  58 static bfd_signed_vma get32 (void);
  59 static bfd_signed_vma get32s (void);
  60 static int get16 (void);
  61 static void set_op (bfd_vma, int);
  62 static void OP_Skip_MODRM (int, int);
  63 static void OP_REG (int, int);
  64 static void OP_IMREG (int, int);
  65 static void OP_I (int, int);
  66 static void OP_I64 (int, int);
  67 static void OP_sI (int, int);
  68 static void OP_J (int, int);
  69 static void OP_SEG (int, int);
  70 static void OP_DIR (int, int);
  71 static void OP_OFF (int, int);
  72 static void OP_OFF64 (int, int);
  73 static void ptr_reg (int, int);
  74 static void OP_ESreg (int, int);
  75 static void OP_DSreg (int, int);
  76 static void OP_C (int, int);
  77 static void OP_D (int, int);
  78 static void OP_T (int, int);
  79 static void OP_R (int, int);
  80 static void OP_MMX (int, int);
  81 static void OP_XMM (int, int);
  82 static void OP_EM (int, int);
  83 static void OP_EX (int, int);
  84 static void OP_EMC (int,int);
  85 static void OP_MXC (int,int);
  86 static void OP_MS (int, int);
  87 static void OP_XS (int, int);
  88 static void OP_M (int, int);
  89 static void OP_VEX (int, int);
  90 static void OP_EX_Vex (int, int);
  91 static void OP_EX_VexW (int, int);
  92 static void OP_EX_VexImmW (int, int);
  93 static void OP_XMM_Vex (int, int);
  94 static void OP_XMM_VexW (int, int);
  95 static void OP_Rounding (int, int);
  96 static void OP_REG_VexI4 (int, int);
  97 static void PCLMUL_Fixup (int, int);
  98 static void VEXI4_Fixup (int, int);
  99 static void VZERO_Fixup (int, int);
 100 static void VCMP_Fixup (int, int);
 101 static void VPCMP_Fixup (int, int);
 102 static void OP_0f07 (int, int);
 103 static void OP_Monitor (int, int);
 104 static void OP_Mwait (int, int);
 105 static void OP_Mwaitx (int, int);
 106 static void NOP_Fixup1 (int, int);
 107 static void NOP_Fixup2 (int, int);
 108 static void OP_3DNowSuffix (int, int);
 109 static void CMP_Fixup (int, int);
 110 static void BadOp (void);
 111 static void REP_Fixup (int, int);
 112 static void BND_Fixup (int, int);
 113 static void HLE_Fixup1 (int, int);
 114 static void HLE_Fixup2 (int, int);
 115 static void HLE_Fixup3 (int, int);
 116 static void CMPXCHG8B_Fixup (int, int);
 117 static void XMM_Fixup (int, int);
 118 static void CRC32_Fixup (int, int);
 119 static void FXSAVE_Fixup (int, int);
 120 static void PCMPESTR_Fixup (int, int);
 121 static void OP_LWPCB_E (int, int);
 122 static void OP_LWP_E (int, int);
 123 static void OP_Vex_2src_1 (int, int);
 124 static void OP_Vex_2src_2 (int, int);
 125
 126 static void MOVBE_Fixup (int, int);
 127
 128 static void OP_Mask (int, int);
 129
 130 struct dis_private {
 131   /* Points to first byte not fetched.  */
 132   bfd_byte *max_fetched;
 133   bfd_byte the_buffer[MAX_MNEM_SIZE];
 134   bfd_vma insn_start;
 135   int orig_sizeflag;
 136   OPCODES_SIGJMP_BUF bailout;
 137 };
 138
 139 enum address_mode
 140 {
 141   mode_16bit,
 142   mode_32bit,
 143   mode_64bit
 144 };
 145
 146 enum address_mode address_mode;
 147
 148 /* Flags for the prefixes for the current instruction.  See below.  */
 149 static int prefixes;
 150
 151 /* REX prefix the current instruction.  See below.  */
 152 static int rex;
 153 /* Bits of REX we've already used.  */
 154 static int rex_used;
 155 /* REX bits in original REX prefix ignored.  */
 156 static int rex_ignored;
 157 /* Mark parts used in the REX prefix.  When we are testing for
 158    empty prefix (for 8bit register REX extension), just mask it
 159    out.  Otherwise test for REX bit is excuse for existence of REX
 160    only in case value is nonzero.  */
 161 #define USED_REX(value)                                 \
 162   {                                                     \
 163     if (value)                                          \
 164       {                                                 \
 165         if ((rex & value))                              \
 166           rex_used |= (value) | REX_OPCODE;             \
 167       }                                                 \
 168     else                                                \
 169       rex_used |= REX_OPCODE;                           \
 170   }
 171
 172 /* Flags for prefixes which we somehow handled when printing the
 173    current instruction.  */
 174 static int used_prefixes;
 175
 176 /* Flags stored in PREFIXES.  */
 177 #define PREFIX_REPZ 1
 178 #define PREFIX_REPNZ 2
 179 #define PREFIX_LOCK 4
 180 #define PREFIX_CS 8
 181 #define PREFIX_SS 0x10
 182 #define PREFIX_DS 0x20
 183 #define PREFIX_ES 0x40
 184 #define PREFIX_FS 0x80
 185 #define PREFIX_GS 0x100
 186 #define PREFIX_DATA 0x200
 187 #define PREFIX_ADDR 0x400
 188 #define PREFIX_FWAIT 0x800
 189
 190 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 191    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 192    on error.  */
 193 #define FETCH_DATA(info, addr) \
 194   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 195    ? 1 : fetch_data ((info), (addr)))
 196
 197 static int
 198 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 199 {
 200   int status;
 201   struct dis_private *priv = (struct dis_private *) info->private_data;
 202   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 203
 204   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 205     status = (*info->read_memory_func) (start,
 206                                         priv->max_fetched,
 207                                         addr - priv->max_fetched,
 208                                         info);
 209   else
 210     status = -1;
 211   if (status != 0)
 212     {
 213       /* If we did manage to read at least one byte, then
 214          print_insn_i386 will do something sensible.  Otherwise, print
 215          an error.  We do that here because this is where we know
 216          STATUS.  */
 217       if (priv->max_fetched == priv->the_buffer)
 218         (*info->memory_error_func) (status, start, info);
 219       OPCODES_SIGLONGJMP (priv->bailout, 1);
 220     }
 221   else
 222     priv->max_fetched = addr;
 223   return 1;
 224 }
 225
 226 /* Possible values for prefix requirement.  */
 227 #define PREFIX_IGNORED_SHIFT    16
 228 #define PREFIX_IGNORED_REPZ     (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
 229 #define PREFIX_IGNORED_REPNZ    (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
 230 #define PREFIX_IGNORED_DATA     (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
 231 #define PREFIX_IGNORED_ADDR     (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
 232 #define PREFIX_IGNORED_LOCK     (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
 233
 234 /* Opcode prefixes.  */
 235 #define PREFIX_OPCODE           (PREFIX_REPZ \
 236                                  | PREFIX_REPNZ \
 237                                  | PREFIX_DATA)
 238
 239 /* Prefixes ignored.  */
 240 #define PREFIX_IGNORED          (PREFIX_IGNORED_REPZ \
 241                                  | PREFIX_IGNORED_REPNZ \
 242                                  | PREFIX_IGNORED_DATA)
 243
 244 #define XX { NULL, 0 }
 245 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
 246
 247 #define Eb { OP_E, b_mode }
 248 #define Ebnd { OP_E, bnd_mode }
 249 #define EbS { OP_E, b_swap_mode }
 250 #define Ev { OP_E, v_mode }
 251 #define Ev_bnd { OP_E, v_bnd_mode }
 252 #define EvS { OP_E, v_swap_mode }
 253 #define Ed { OP_E, d_mode }
 254 #define Edq { OP_E, dq_mode }
 255 #define Edqw { OP_E, dqw_mode }
 256 #define Edqb { OP_E, dqb_mode }
 257 #define Edb { OP_E, db_mode }
 258 #define Edw { OP_E, dw_mode }
 259 #define Edqd { OP_E, dqd_mode }
 260 #define Eq { OP_E, q_mode }
 261 #define indirEv { OP_indirE, indir_v_mode }
 262 #define indirEp { OP_indirE, f_mode }
 263 #define stackEv { OP_E, stack_v_mode }
 264 #define Em { OP_E, m_mode }
 265 #define Ew { OP_E, w_mode }
 266 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 267 #define Ma { OP_M, a_mode }
 268 #define Mb { OP_M, b_mode }
 269 #define Md { OP_M, d_mode }
 270 #define Mo { OP_M, o_mode }
 271 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 272 #define Mq { OP_M, q_mode }
 273 #define Mx { OP_M, x_mode }
 274 #define Mxmm { OP_M, xmm_mode }
 275 #define Gb { OP_G, b_mode }
 276 #define Gbnd { OP_G, bnd_mode }
 277 #define Gv { OP_G, v_mode }
 278 #define Gd { OP_G, d_mode }
 279 #define Gdq { OP_G, dq_mode }
 280 #define Gm { OP_G, m_mode }
 281 #define Gw { OP_G, w_mode }
 282 #define Rd { OP_R, d_mode }
 283 #define Rdq { OP_R, dq_mode }
 284 #define Rm { OP_R, m_mode }
 285 #define Ib { OP_I, b_mode }
 286 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 287 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 288 #define Iv { OP_I, v_mode }
 289 #define sIv { OP_sI, v_mode }
 290 #define Iq { OP_I, q_mode }
 291 #define Iv64 { OP_I64, v_mode }
 292 #define Iw { OP_I, w_mode }
 293 #define I1 { OP_I, const_1_mode }
 294 #define Jb { OP_J, b_mode }
 295 #define Jv { OP_J, v_mode }
 296 #define Cm { OP_C, m_mode }
 297 #define Dm { OP_D, m_mode }
 298 #define Td { OP_T, d_mode }
 299 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 300
 301 #define RMeAX { OP_REG, eAX_reg }
 302 #define RMeBX { OP_REG, eBX_reg }
 303 #define RMeCX { OP_REG, eCX_reg }
 304 #define RMeDX { OP_REG, eDX_reg }
 305 #define RMeSP { OP_REG, eSP_reg }
 306 #define RMeBP { OP_REG, eBP_reg }
 307 #define RMeSI { OP_REG, eSI_reg }
 308 #define RMeDI { OP_REG, eDI_reg }
 309 #define RMrAX { OP_REG, rAX_reg }
 310 #define RMrBX { OP_REG, rBX_reg }
 311 #define RMrCX { OP_REG, rCX_reg }
 312 #define RMrDX { OP_REG, rDX_reg }
 313 #define RMrSP { OP_REG, rSP_reg }
 314 #define RMrBP { OP_REG, rBP_reg }
 315 #define RMrSI { OP_REG, rSI_reg }
 316 #define RMrDI { OP_REG, rDI_reg }
 317 #define RMAL { OP_REG, al_reg }
 318 #define RMCL { OP_REG, cl_reg }
 319 #define RMDL { OP_REG, dl_reg }
 320 #define RMBL { OP_REG, bl_reg }
 321 #define RMAH { OP_REG, ah_reg }
 322 #define RMCH { OP_REG, ch_reg }
 323 #define RMDH { OP_REG, dh_reg }
 324 #define RMBH { OP_REG, bh_reg }
 325 #define RMAX { OP_REG, ax_reg }
 326 #define RMDX { OP_REG, dx_reg }
 327
 328 #define eAX { OP_IMREG, eAX_reg }
 329 #define eBX { OP_IMREG, eBX_reg }
 330 #define eCX { OP_IMREG, eCX_reg }
 331 #define eDX { OP_IMREG, eDX_reg }
 332 #define eSP { OP_IMREG, eSP_reg }
 333 #define eBP { OP_IMREG, eBP_reg }
 334 #define eSI { OP_IMREG, eSI_reg }
 335 #define eDI { OP_IMREG, eDI_reg }
 336 #define AL { OP_IMREG, al_reg }
 337 #define CL { OP_IMREG, cl_reg }
 338 #define DL { OP_IMREG, dl_reg }
 339 #define BL { OP_IMREG, bl_reg }
 340 #define AH { OP_IMREG, ah_reg }
 341 #define CH { OP_IMREG, ch_reg }
 342 #define DH { OP_IMREG, dh_reg }
 343 #define BH { OP_IMREG, bh_reg }
 344 #define AX { OP_IMREG, ax_reg }
 345 #define DX { OP_IMREG, dx_reg }
 346 #define zAX { OP_IMREG, z_mode_ax_reg }
 347 #define indirDX { OP_IMREG, indir_dx_reg }
 348
 349 #define Sw { OP_SEG, w_mode }
 350 #define Sv { OP_SEG, v_mode }
 351 #define Ap { OP_DIR, 0 }
 352 #define Ob { OP_OFF64, b_mode }
 353 #define Ov { OP_OFF64, v_mode }
 354 #define Xb { OP_DSreg, eSI_reg }
 355 #define Xv { OP_DSreg, eSI_reg }
 356 #define Xz { OP_DSreg, eSI_reg }
 357 #define Yb { OP_ESreg, eDI_reg }
 358 #define Yv { OP_ESreg, eDI_reg }
 359 #define DSBX { OP_DSreg, eBX_reg }
 360
 361 #define es { OP_REG, es_reg }
 362 #define ss { OP_REG, ss_reg }
 363 #define cs { OP_REG, cs_reg }
 364 #define ds { OP_REG, ds_reg }
 365 #define fs { OP_REG, fs_reg }
 366 #define gs { OP_REG, gs_reg }
 367
 368 #define MX { OP_MMX, 0 }
 369 #define XM { OP_XMM, 0 }
 370 #define XMScalar { OP_XMM, scalar_mode }
 371 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 372 #define XMM { OP_XMM, xmm_mode }
 373 #define XMxmmq { OP_XMM, xmmq_mode }
 374 #define EM { OP_EM, v_mode }
 375 #define EMS { OP_EM, v_swap_mode }
 376 #define EMd { OP_EM, d_mode }
 377 #define EMx { OP_EM, x_mode }
 378 #define EXw { OP_EX, w_mode }
 379 #define EXd { OP_EX, d_mode }
 380 #define EXdScalar { OP_EX, d_scalar_mode }
 381 #define EXdS { OP_EX, d_swap_mode }
 382 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
 383 #define EXq { OP_EX, q_mode }
 384 #define EXqScalar { OP_EX, q_scalar_mode }
 385 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
 386 #define EXqS { OP_EX, q_swap_mode }
 387 #define EXx { OP_EX, x_mode }
 388 #define EXxS { OP_EX, x_swap_mode }
 389 #define EXxmm { OP_EX, xmm_mode }
 390 #define EXymm { OP_EX, ymm_mode }
 391 #define EXxmmq { OP_EX, xmmq_mode }
 392 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 393 #define EXxmm_mb { OP_EX, xmm_mb_mode }
 394 #define EXxmm_mw { OP_EX, xmm_mw_mode }
 395 #define EXxmm_md { OP_EX, xmm_md_mode }
 396 #define EXxmm_mq { OP_EX, xmm_mq_mode }
 397 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
 398 #define EXxmmdw { OP_EX, xmmdw_mode }
 399 #define EXxmmqd { OP_EX, xmmqd_mode }
 400 #define EXymmq { OP_EX, ymmq_mode }
 401 #define EXVexWdq { OP_EX, vex_w_dq_mode }
 402 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 403 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 404 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 405 #define MS { OP_MS, v_mode }
 406 #define XS { OP_XS, v_mode }
 407 #define EMCq { OP_EMC, q_mode }
 408 #define MXC { OP_MXC, 0 }
 409 #define OPSUF { OP_3DNowSuffix, 0 }
 410 #define CMP { CMP_Fixup, 0 }
 411 #define XMM0 { XMM_Fixup, 0 }
 412 #define FXSAVE { FXSAVE_Fixup, 0 }
 413 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
 414 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
 415
 416 #define Vex { OP_VEX, vex_mode }
 417 #define VexScalar { OP_VEX, vex_scalar_mode }
 418 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 419 #define Vex128 { OP_VEX, vex128_mode }
 420 #define Vex256 { OP_VEX, vex256_mode }
 421 #define VexGdq { OP_VEX, dq_mode }
 422 #define VexI4 { VEXI4_Fixup, 0}
 423 #define EXdVex { OP_EX_Vex, d_mode }
 424 #define EXdVexS { OP_EX_Vex, d_swap_mode }
 425 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
 426 #define EXqVex { OP_EX_Vex, q_mode }
 427 #define EXqVexS { OP_EX_Vex, q_swap_mode }
 428 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
 429 #define EXVexW { OP_EX_VexW, x_mode }
 430 #define EXdVexW { OP_EX_VexW, d_mode }
 431 #define EXqVexW { OP_EX_VexW, q_mode }
 432 #define EXVexImmW { OP_EX_VexImmW, x_mode }
 433 #define XMVex { OP_XMM_Vex, 0 }
 434 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
 435 #define XMVexW { OP_XMM_VexW, 0 }
 436 #define XMVexI4 { OP_REG_VexI4, x_mode }
 437 #define PCLMUL { PCLMUL_Fixup, 0 }
 438 #define VZERO { VZERO_Fixup, 0 }
 439 #define VCMP { VCMP_Fixup, 0 }
 440 #define VPCMP { VPCMP_Fixup, 0 }
 441
 442 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 443 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 444
 445 #define XMask { OP_Mask, mask_mode }
 446 #define MaskG { OP_G, mask_mode }
 447 #define MaskE { OP_E, mask_mode }
 448 #define MaskBDE { OP_E, mask_bd_mode }
 449 #define MaskR { OP_R, mask_mode }
 450 #define MaskVex { OP_VEX, mask_mode }
 451
 452 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 453 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
 454 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 455 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
 456
 457 /* Used handle "rep" prefix for string instructions.  */
 458 #define Xbr { REP_Fixup, eSI_reg }
 459 #define Xvr { REP_Fixup, eSI_reg }
 460 #define Ybr { REP_Fixup, eDI_reg }
 461 #define Yvr { REP_Fixup, eDI_reg }
 462 #define Yzr { REP_Fixup, eDI_reg }
 463 #define indirDXr { REP_Fixup, indir_dx_reg }
 464 #define ALr { REP_Fixup, al_reg }
 465 #define eAXr { REP_Fixup, eAX_reg }
 466
 467 /* Used handle HLE prefix for lockable instructions.  */
 468 #define Ebh1 { HLE_Fixup1, b_mode }
 469 #define Evh1 { HLE_Fixup1, v_mode }
 470 #define Ebh2 { HLE_Fixup2, b_mode }
 471 #define Evh2 { HLE_Fixup2, v_mode }
 472 #define Ebh3 { HLE_Fixup3, b_mode }
 473 #define Evh3 { HLE_Fixup3, v_mode }
 474
 475 #define BND { BND_Fixup, 0 }
 476
 477 #define cond_jump_flag { NULL, cond_jump_mode }
 478 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 479
 480 /* bits in sizeflag */
 481 #define SUFFIX_ALWAYS 4
 482 #define AFLAG 2
 483 #define DFLAG 1
 484
 485 enum
 486 {
 487   /* byte operand */
 488   b_mode = 1,
 489   /* byte operand with operand swapped */
 490   b_swap_mode,
 491   /* byte operand, sign extend like 'T' suffix */
 492   b_T_mode,
 493   /* operand size depends on prefixes */
 494   v_mode,
 495   /* operand size depends on prefixes with operand swapped */
 496   v_swap_mode,
 497   /* word operand */
 498   w_mode,
 499   /* double word operand  */
 500   d_mode,
 501   /* double word operand with operand swapped */
 502   d_swap_mode,
 503   /* quad word operand */
 504   q_mode,
 505   /* quad word operand with operand swapped */
 506   q_swap_mode,
 507   /* ten-byte operand */
 508   t_mode,
 509   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 510      broadcast enabled.  */
 511   x_mode,
 512   /* Similar to x_mode, but with different EVEX mem shifts.  */
 513   evex_x_gscat_mode,
 514   /* Similar to x_mode, but with disabled broadcast.  */
 515   evex_x_nobcst_mode,
 516   /* Similar to x_mode, but with operands swapped and disabled broadcast
 517      in EVEX.  */
 518   x_swap_mode,
 519   /* 16-byte XMM operand */
 520   xmm_mode,
 521   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 522      memory operand (depending on vector length).  Broadcast isn't
 523      allowed.  */
 524   xmmq_mode,
 525   /* Same as xmmq_mode, but broadcast is allowed.  */
 526   evex_half_bcst_xmmq_mode,
 527   /* XMM register or byte memory operand */
 528   xmm_mb_mode,
 529   /* XMM register or word memory operand */
 530   xmm_mw_mode,
 531   /* XMM register or double word memory operand */
 532   xmm_md_mode,
 533   /* XMM register or quad word memory operand */
 534   xmm_mq_mode,
 535   /* XMM register or double/quad word memory operand, depending on
 536      VEX.W.  */
 537   xmm_mdq_mode,
 538   /* 16-byte XMM, word, double word or quad word operand.  */
 539   xmmdw_mode,
 540   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 541   xmmqd_mode,
 542   /* 32-byte YMM operand */
 543   ymm_mode,
 544   /* quad word, ymmword or zmmword memory operand.  */
 545   ymmq_mode,
 546   /* 32-byte YMM or 16-byte word operand */
 547   ymmxmm_mode,
 548   /* d_mode in 32bit, q_mode in 64bit mode.  */
 549   m_mode,
 550   /* pair of v_mode operands */
 551   a_mode,
 552   cond_jump_mode,
 553   loop_jcxz_mode,
 554   v_bnd_mode,
 555   /* operand size depends on REX prefixes.  */
 556   dq_mode,
 557   /* registers like dq_mode, memory like w_mode.  */
 558   dqw_mode,
 559   bnd_mode,
 560   /* 4- or 6-byte pointer operand */
 561   f_mode,
 562   const_1_mode,
 563   /* v_mode for indirect branch opcodes.  */
 564   indir_v_mode,
 565   /* v_mode for stack-related opcodes.  */
 566   stack_v_mode,
 567   /* non-quad operand size depends on prefixes */
 568   z_mode,
 569   /* 16-byte operand */
 570   o_mode,
 571   /* registers like dq_mode, memory like b_mode.  */
 572   dqb_mode,
 573   /* registers like d_mode, memory like b_mode.  */
 574   db_mode,
 575   /* registers like d_mode, memory like w_mode.  */
 576   dw_mode,
 577   /* registers like dq_mode, memory like d_mode.  */
 578   dqd_mode,
 579   /* normal vex mode */
 580   vex_mode,
 581   /* 128bit vex mode */
 582   vex128_mode,
 583   /* 256bit vex mode */
 584   vex256_mode,
 585   /* operand size depends on the VEX.W bit.  */
 586   vex_w_dq_mode,
 587
 588   /* Similar to vex_w_dq_mode, with VSIB dword indices.  */
 589   vex_vsib_d_w_dq_mode,
 590   /* Similar to vex_vsib_d_w_dq_mode, with smaller memory.  */
 591   vex_vsib_d_w_d_mode,
 592   /* Similar to vex_w_dq_mode, with VSIB qword indices.  */
 593   vex_vsib_q_w_dq_mode,
 594   /* Similar to vex_vsib_q_w_dq_mode, with smaller memory.  */
 595   vex_vsib_q_w_d_mode,
 596
 597   /* scalar, ignore vector length.  */
 598   scalar_mode,
 599   /* like d_mode, ignore vector length.  */
 600   d_scalar_mode,
 601   /* like d_swap_mode, ignore vector length.  */
 602   d_scalar_swap_mode,
 603   /* like q_mode, ignore vector length.  */
 604   q_scalar_mode,
 605   /* like q_swap_mode, ignore vector length.  */
 606   q_scalar_swap_mode,
 607   /* like vex_mode, ignore vector length.  */
 608   vex_scalar_mode,
 609   /* like vex_w_dq_mode, ignore vector length.  */
 610   vex_scalar_w_dq_mode,
 611
 612   /* Static rounding.  */
 613   evex_rounding_mode,
 614   /* Supress all exceptions.  */
 615   evex_sae_mode,
 616
 617   /* Mask register operand.  */
 618   mask_mode,
 619   /* Mask register operand.  */
 620   mask_bd_mode,
 621
 622   es_reg,
 623   cs_reg,
 624   ss_reg,
 625   ds_reg,
 626   fs_reg,
 627   gs_reg,
 628
 629   eAX_reg,
 630   eCX_reg,
 631   eDX_reg,
 632   eBX_reg,
 633   eSP_reg,
 634   eBP_reg,
 635   eSI_reg,
 636   eDI_reg,
 637
 638   al_reg,
 639   cl_reg,
 640   dl_reg,
 641   bl_reg,
 642   ah_reg,
 643   ch_reg,
 644   dh_reg,
 645   bh_reg,
 646
 647   ax_reg,
 648   cx_reg,
 649   dx_reg,
 650   bx_reg,
 651   sp_reg,
 652   bp_reg,
 653   si_reg,
 654   di_reg,
 655
 656   rAX_reg,
 657   rCX_reg,
 658   rDX_reg,
 659   rBX_reg,
 660   rSP_reg,
 661   rBP_reg,
 662   rSI_reg,
 663   rDI_reg,
 664
 665   z_mode_ax_reg,
 666   indir_dx_reg
 667 };
 668
 669 enum
 670 {
 671   FLOATCODE = 1,
 672   USE_REG_TABLE,
 673   USE_MOD_TABLE,
 674   USE_RM_TABLE,
 675   USE_PREFIX_TABLE,
 676   USE_X86_64_TABLE,
 677   USE_3BYTE_TABLE,
 678   USE_XOP_8F_TABLE,
 679   USE_VEX_C4_TABLE,
 680   USE_VEX_C5_TABLE,
 681   USE_VEX_LEN_TABLE,
 682   USE_VEX_W_TABLE,
 683   USE_EVEX_TABLE
 684 };
 685
 686 #define FLOAT                   NULL, { { NULL, FLOATCODE } }, 0
 687
 688 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }, 0
 689 #define DIS386_PREFIX(T, I, P)          NULL, { { NULL, (T)}, { NULL,  (I) } }, P
 690 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 691 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 692 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 693 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 694 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 695 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 696 #define THREE_BYTE_TABLE_PREFIX(I, P)   DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
 697 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 698 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 699 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 700 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 701 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 702 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 703
 704 enum
 705 {
 706   REG_80 = 0,
 707   REG_81,
 708   REG_83,
 709   REG_8F,
 710   REG_C0,
 711   REG_C1,
 712   REG_C6,
 713   REG_C7,
 714   REG_D0,
 715   REG_D1,
 716   REG_D2,
 717   REG_D3,
 718   REG_F6,
 719   REG_F7,
 720   REG_FE,
 721   REG_FF,
 722   REG_0F00,
 723   REG_0F01,
 724   REG_0F0D,
 725   REG_0F18,
 726   REG_0F1E_MOD_3,
 727   REG_0F71,
 728   REG_0F72,
 729   REG_0F73,
 730   REG_0FA6,
 731   REG_0FA7,
 732   REG_0FAE,
 733   REG_0FBA,
 734   REG_0FC7,
 735   REG_VEX_0F71,
 736   REG_VEX_0F72,
 737   REG_VEX_0F73,
 738   REG_VEX_0FAE,
 739   REG_VEX_0F38F3,
 740   REG_XOP_LWPCB,
 741   REG_XOP_LWP,
 742   REG_XOP_TBM_01,
 743   REG_XOP_TBM_02,
 744
 745   REG_EVEX_0F71,
 746   REG_EVEX_0F72,
 747   REG_EVEX_0F73,
 748   REG_EVEX_0F38C6,
 749   REG_EVEX_0F38C7
 750 };
 751
 752 enum
 753 {
 754   MOD_8D = 0,
 755   MOD_C6_REG_7,
 756   MOD_C7_REG_7,
 757   MOD_FF_REG_3,
 758   MOD_FF_REG_5,
 759   MOD_0F01_REG_0,
 760   MOD_0F01_REG_1,
 761   MOD_0F01_REG_2,
 762   MOD_0F01_REG_3,
 763   MOD_0F01_REG_5,
 764   MOD_0F01_REG_7,
 765   MOD_0F12_PREFIX_0,
 766   MOD_0F13,
 767   MOD_0F16_PREFIX_0,
 768   MOD_0F17,
 769   MOD_0F18_REG_0,
 770   MOD_0F18_REG_1,
 771   MOD_0F18_REG_2,
 772   MOD_0F18_REG_3,
 773   MOD_0F18_REG_4,
 774   MOD_0F18_REG_5,
 775   MOD_0F18_REG_6,
 776   MOD_0F18_REG_7,
 777   MOD_0F1A_PREFIX_0,
 778   MOD_0F1B_PREFIX_0,
 779   MOD_0F1B_PREFIX_1,
 780   MOD_0F1E_PREFIX_1,
 781   MOD_0F24,
 782   MOD_0F26,
 783   MOD_0F2B_PREFIX_0,
 784   MOD_0F2B_PREFIX_1,
 785   MOD_0F2B_PREFIX_2,
 786   MOD_0F2B_PREFIX_3,
 787   MOD_0F51,
 788   MOD_0F71_REG_2,
 789   MOD_0F71_REG_4,
 790   MOD_0F71_REG_6,
 791   MOD_0F72_REG_2,
 792   MOD_0F72_REG_4,
 793   MOD_0F72_REG_6,
 794   MOD_0F73_REG_2,
 795   MOD_0F73_REG_3,
 796   MOD_0F73_REG_6,
 797   MOD_0F73_REG_7,
 798   MOD_0FAE_REG_0,
 799   MOD_0FAE_REG_1,
 800   MOD_0FAE_REG_2,
 801   MOD_0FAE_REG_3,
 802   MOD_0FAE_REG_4,
 803   MOD_0FAE_REG_5,
 804   MOD_0FAE_REG_6,
 805   MOD_0FAE_REG_7,
 806   MOD_0FB2,
 807   MOD_0FB4,
 808   MOD_0FB5,
 809   MOD_0FC3,
 810   MOD_0FC7_REG_3,
 811   MOD_0FC7_REG_4,
 812   MOD_0FC7_REG_5,
 813   MOD_0FC7_REG_6,
 814   MOD_0FC7_REG_7,
 815   MOD_0FD7,
 816   MOD_0FE7_PREFIX_2,
 817   MOD_0FF0_PREFIX_3,
 818   MOD_0F382A_PREFIX_2,
 819   MOD_0F38F5_PREFIX_2,
 820   MOD_0F38F6_PREFIX_0,
 821   MOD_62_32BIT,
 822   MOD_C4_32BIT,
 823   MOD_C5_32BIT,
 824   MOD_VEX_0F12_PREFIX_0,
 825   MOD_VEX_0F13,
 826   MOD_VEX_0F16_PREFIX_0,
 827   MOD_VEX_0F17,
 828   MOD_VEX_0F2B,
 829   MOD_VEX_W_0_0F41_P_0_LEN_1,
 830   MOD_VEX_W_1_0F41_P_0_LEN_1,
 831   MOD_VEX_W_0_0F41_P_2_LEN_1,
 832   MOD_VEX_W_1_0F41_P_2_LEN_1,
 833   MOD_VEX_W_0_0F42_P_0_LEN_1,
 834   MOD_VEX_W_1_0F42_P_0_LEN_1,
 835   MOD_VEX_W_0_0F42_P_2_LEN_1,
 836   MOD_VEX_W_1_0F42_P_2_LEN_1,
 837   MOD_VEX_W_0_0F44_P_0_LEN_1,
 838   MOD_VEX_W_1_0F44_P_0_LEN_1,
 839   MOD_VEX_W_0_0F44_P_2_LEN_1,
 840   MOD_VEX_W_1_0F44_P_2_LEN_1,
 841   MOD_VEX_W_0_0F45_P_0_LEN_1,
 842   MOD_VEX_W_1_0F45_P_0_LEN_1,
 843   MOD_VEX_W_0_0F45_P_2_LEN_1,
 844   MOD_VEX_W_1_0F45_P_2_LEN_1,
 845   MOD_VEX_W_0_0F46_P_0_LEN_1,
 846   MOD_VEX_W_1_0F46_P_0_LEN_1,
 847   MOD_VEX_W_0_0F46_P_2_LEN_1,
 848   MOD_VEX_W_1_0F46_P_2_LEN_1,
 849   MOD_VEX_W_0_0F47_P_0_LEN_1,
 850   MOD_VEX_W_1_0F47_P_0_LEN_1,
 851   MOD_VEX_W_0_0F47_P_2_LEN_1,
 852   MOD_VEX_W_1_0F47_P_2_LEN_1,
 853   MOD_VEX_W_0_0F4A_P_0_LEN_1,
 854   MOD_VEX_W_1_0F4A_P_0_LEN_1,
 855   MOD_VEX_W_0_0F4A_P_2_LEN_1,
 856   MOD_VEX_W_1_0F4A_P_2_LEN_1,
 857   MOD_VEX_W_0_0F4B_P_0_LEN_1,
 858   MOD_VEX_W_1_0F4B_P_0_LEN_1,
 859   MOD_VEX_W_0_0F4B_P_2_LEN_1,
 860   MOD_VEX_0F50,
 861   MOD_VEX_0F71_REG_2,
 862   MOD_VEX_0F71_REG_4,
 863   MOD_VEX_0F71_REG_6,
 864   MOD_VEX_0F72_REG_2,
 865   MOD_VEX_0F72_REG_4,
 866   MOD_VEX_0F72_REG_6,
 867   MOD_VEX_0F73_REG_2,
 868   MOD_VEX_0F73_REG_3,
 869   MOD_VEX_0F73_REG_6,
 870   MOD_VEX_0F73_REG_7,
 871   MOD_VEX_W_0_0F91_P_0_LEN_0,
 872   MOD_VEX_W_1_0F91_P_0_LEN_0,
 873   MOD_VEX_W_0_0F91_P_2_LEN_0,
 874   MOD_VEX_W_1_0F91_P_2_LEN_0,
 875   MOD_VEX_W_0_0F92_P_0_LEN_0,
 876   MOD_VEX_W_0_0F92_P_2_LEN_0,
 877   MOD_VEX_W_0_0F92_P_3_LEN_0,
 878   MOD_VEX_W_1_0F92_P_3_LEN_0,
 879   MOD_VEX_W_0_0F93_P_0_LEN_0,
 880   MOD_VEX_W_0_0F93_P_2_LEN_0,
 881   MOD_VEX_W_0_0F93_P_3_LEN_0,
 882   MOD_VEX_W_1_0F93_P_3_LEN_0,
 883   MOD_VEX_W_0_0F98_P_0_LEN_0,
 884   MOD_VEX_W_1_0F98_P_0_LEN_0,
 885   MOD_VEX_W_0_0F98_P_2_LEN_0,
 886   MOD_VEX_W_1_0F98_P_2_LEN_0,
 887   MOD_VEX_W_0_0F99_P_0_LEN_0,
 888   MOD_VEX_W_1_0F99_P_0_LEN_0,
 889   MOD_VEX_W_0_0F99_P_2_LEN_0,
 890   MOD_VEX_W_1_0F99_P_2_LEN_0,
 891   MOD_VEX_0FAE_REG_2,
 892   MOD_VEX_0FAE_REG_3,
 893   MOD_VEX_0FD7_PREFIX_2,
 894   MOD_VEX_0FE7_PREFIX_2,
 895   MOD_VEX_0FF0_PREFIX_3,
 896   MOD_VEX_0F381A_PREFIX_2,
 897   MOD_VEX_0F382A_PREFIX_2,
 898   MOD_VEX_0F382C_PREFIX_2,
 899   MOD_VEX_0F382D_PREFIX_2,
 900   MOD_VEX_0F382E_PREFIX_2,
 901   MOD_VEX_0F382F_PREFIX_2,
 902   MOD_VEX_0F385A_PREFIX_2,
 903   MOD_VEX_0F388C_PREFIX_2,
 904   MOD_VEX_0F388E_PREFIX_2,
 905   MOD_VEX_W_0_0F3A30_P_2_LEN_0,
 906   MOD_VEX_W_1_0F3A30_P_2_LEN_0,
 907   MOD_VEX_W_0_0F3A31_P_2_LEN_0,
 908   MOD_VEX_W_1_0F3A31_P_2_LEN_0,
 909   MOD_VEX_W_0_0F3A32_P_2_LEN_0,
 910   MOD_VEX_W_1_0F3A32_P_2_LEN_0,
 911   MOD_VEX_W_0_0F3A33_P_2_LEN_0,
 912   MOD_VEX_W_1_0F3A33_P_2_LEN_0,
 913
 914   MOD_EVEX_0F10_PREFIX_1,
 915   MOD_EVEX_0F10_PREFIX_3,
 916   MOD_EVEX_0F11_PREFIX_1,
 917   MOD_EVEX_0F11_PREFIX_3,
 918   MOD_EVEX_0F12_PREFIX_0,
 919   MOD_EVEX_0F16_PREFIX_0,
 920   MOD_EVEX_0F38C6_REG_1,
 921   MOD_EVEX_0F38C6_REG_2,
 922   MOD_EVEX_0F38C6_REG_5,
 923   MOD_EVEX_0F38C6_REG_6,
 924   MOD_EVEX_0F38C7_REG_1,
 925   MOD_EVEX_0F38C7_REG_2,
 926   MOD_EVEX_0F38C7_REG_5,
 927   MOD_EVEX_0F38C7_REG_6
 928 };
 929
 930 enum
 931 {
 932   RM_C6_REG_7 = 0,
 933   RM_C7_REG_7,
 934   RM_0F01_REG_0,
 935   RM_0F01_REG_1,
 936   RM_0F01_REG_2,
 937   RM_0F01_REG_3,
 938   RM_0F01_REG_5,
 939   RM_0F01_REG_7,
 940   RM_0F1E_MOD_3_REG_7,
 941   RM_0FAE_REG_5,
 942   RM_0FAE_REG_6,
 943   RM_0FAE_REG_7
 944 };
 945
 946 enum
 947 {
 948   PREFIX_90 = 0,
 949   PREFIX_MOD_0_0F01_REG_5,
 950   PREFIX_MOD_3_0F01_REG_5_RM_1,
 951   PREFIX_MOD_3_0F01_REG_5_RM_2,
 952   PREFIX_0F10,
 953   PREFIX_0F11,
 954   PREFIX_0F12,
 955   PREFIX_0F16,
 956   PREFIX_0F1A,
 957   PREFIX_0F1B,
 958   PREFIX_0F1E,
 959   PREFIX_0F2A,
 960   PREFIX_0F2B,
 961   PREFIX_0F2C,
 962   PREFIX_0F2D,
 963   PREFIX_0F2E,
 964   PREFIX_0F2F,
 965   PREFIX_0F51,
 966   PREFIX_0F52,
 967   PREFIX_0F53,
 968   PREFIX_0F58,
 969   PREFIX_0F59,
 970   PREFIX_0F5A,
 971   PREFIX_0F5B,
 972   PREFIX_0F5C,
 973   PREFIX_0F5D,
 974   PREFIX_0F5E,
 975   PREFIX_0F5F,
 976   PREFIX_0F60,
 977   PREFIX_0F61,
 978   PREFIX_0F62,
 979   PREFIX_0F6C,
 980   PREFIX_0F6D,
 981   PREFIX_0F6F,
 982   PREFIX_0F70,
 983   PREFIX_0F73_REG_3,
 984   PREFIX_0F73_REG_7,
 985   PREFIX_0F78,
 986   PREFIX_0F79,
 987   PREFIX_0F7C,
 988   PREFIX_0F7D,
 989   PREFIX_0F7E,
 990   PREFIX_0F7F,
 991   PREFIX_0FAE_REG_0,
 992   PREFIX_0FAE_REG_1,
 993   PREFIX_0FAE_REG_2,
 994   PREFIX_0FAE_REG_3,
 995   PREFIX_MOD_0_0FAE_REG_4,
 996   PREFIX_MOD_3_0FAE_REG_4,
 997   PREFIX_MOD_0_0FAE_REG_5,
 998   PREFIX_0FAE_REG_6,
 999   PREFIX_0FAE_REG_7,
1000   PREFIX_0FB8,
1001   PREFIX_0FBC,
1002   PREFIX_0FBD,
1003   PREFIX_0FC2,
1004   PREFIX_MOD_0_0FC3,
1005   PREFIX_MOD_0_0FC7_REG_6,
1006   PREFIX_MOD_3_0FC7_REG_6,
1007   PREFIX_MOD_3_0FC7_REG_7,
1008   PREFIX_0FD0,
1009   PREFIX_0FD6,
1010   PREFIX_0FE6,
1011   PREFIX_0FE7,
1012   PREFIX_0FF0,
1013   PREFIX_0FF7,
1014   PREFIX_0F3810,
1015   PREFIX_0F3814,
1016   PREFIX_0F3815,
1017   PREFIX_0F3817,
1018   PREFIX_0F3820,
1019   PREFIX_0F3821,
1020   PREFIX_0F3822,
1021   PREFIX_0F3823,
1022   PREFIX_0F3824,
1023   PREFIX_0F3825,
1024   PREFIX_0F3828,
1025   PREFIX_0F3829,
1026   PREFIX_0F382A,
1027   PREFIX_0F382B,
1028   PREFIX_0F3830,
1029   PREFIX_0F3831,
1030   PREFIX_0F3832,
1031   PREFIX_0F3833,
1032   PREFIX_0F3834,
1033   PREFIX_0F3835,
1034   PREFIX_0F3837,
1035   PREFIX_0F3838,
1036   PREFIX_0F3839,
1037   PREFIX_0F383A,
1038   PREFIX_0F383B,
1039   PREFIX_0F383C,
1040   PREFIX_0F383D,
1041   PREFIX_0F383E,
1042   PREFIX_0F383F,
1043   PREFIX_0F3840,
1044   PREFIX_0F3841,
1045   PREFIX_0F3880,
1046   PREFIX_0F3881,
1047   PREFIX_0F3882,
1048   PREFIX_0F38C8,
1049   PREFIX_0F38C9,
1050   PREFIX_0F38CA,
1051   PREFIX_0F38CB,
1052   PREFIX_0F38CC,
1053   PREFIX_0F38CD,
1054   PREFIX_0F38DB,
1055   PREFIX_0F38DC,
1056   PREFIX_0F38DD,
1057   PREFIX_0F38DE,
1058   PREFIX_0F38DF,
1059   PREFIX_0F38F0,
1060   PREFIX_0F38F1,
1061   PREFIX_0F38F5,
1062   PREFIX_0F38F6,
1063   PREFIX_0F3A08,
1064   PREFIX_0F3A09,
1065   PREFIX_0F3A0A,
1066   PREFIX_0F3A0B,
1067   PREFIX_0F3A0C,
1068   PREFIX_0F3A0D,
1069   PREFIX_0F3A0E,
1070   PREFIX_0F3A14,
1071   PREFIX_0F3A15,
1072   PREFIX_0F3A16,
1073   PREFIX_0F3A17,
1074   PREFIX_0F3A20,
1075   PREFIX_0F3A21,
1076   PREFIX_0F3A22,
1077   PREFIX_0F3A40,
1078   PREFIX_0F3A41,
1079   PREFIX_0F3A42,
1080   PREFIX_0F3A44,
1081   PREFIX_0F3A60,
1082   PREFIX_0F3A61,
1083   PREFIX_0F3A62,
1084   PREFIX_0F3A63,
1085   PREFIX_0F3ACC,
1086   PREFIX_0F3ADF,
1087   PREFIX_VEX_0F10,
1088   PREFIX_VEX_0F11,
1089   PREFIX_VEX_0F12,
1090   PREFIX_VEX_0F16,
1091   PREFIX_VEX_0F2A,
1092   PREFIX_VEX_0F2C,
1093   PREFIX_VEX_0F2D,
1094   PREFIX_VEX_0F2E,
1095   PREFIX_VEX_0F2F,
1096   PREFIX_VEX_0F41,
1097   PREFIX_VEX_0F42,
1098   PREFIX_VEX_0F44,
1099   PREFIX_VEX_0F45,
1100   PREFIX_VEX_0F46,
1101   PREFIX_VEX_0F47,
1102   PREFIX_VEX_0F4A,
1103   PREFIX_VEX_0F4B,
1104   PREFIX_VEX_0F51,
1105   PREFIX_VEX_0F52,
1106   PREFIX_VEX_0F53,
1107   PREFIX_VEX_0F58,
1108   PREFIX_VEX_0F59,
1109   PREFIX_VEX_0F5A,
1110   PREFIX_VEX_0F5B,
1111   PREFIX_VEX_0F5C,
1112   PREFIX_VEX_0F5D,
1113   PREFIX_VEX_0F5E,
1114   PREFIX_VEX_0F5F,
1115   PREFIX_VEX_0F60,
1116   PREFIX_VEX_0F61,
1117   PREFIX_VEX_0F62,
1118   PREFIX_VEX_0F63,
1119   PREFIX_VEX_0F64,
1120   PREFIX_VEX_0F65,
1121   PREFIX_VEX_0F66,
1122   PREFIX_VEX_0F67,
1123   PREFIX_VEX_0F68,
1124   PREFIX_VEX_0F69,
1125   PREFIX_VEX_0F6A,
1126   PREFIX_VEX_0F6B,
1127   PREFIX_VEX_0F6C,
1128   PREFIX_VEX_0F6D,
1129   PREFIX_VEX_0F6E,
1130   PREFIX_VEX_0F6F,
1131   PREFIX_VEX_0F70,
1132   PREFIX_VEX_0F71_REG_2,
1133   PREFIX_VEX_0F71_REG_4,
1134   PREFIX_VEX_0F71_REG_6,
1135   PREFIX_VEX_0F72_REG_2,
1136   PREFIX_VEX_0F72_REG_4,
1137   PREFIX_VEX_0F72_REG_6,
1138   PREFIX_VEX_0F73_REG_2,
1139   PREFIX_VEX_0F73_REG_3,
1140   PREFIX_VEX_0F73_REG_6,
1141   PREFIX_VEX_0F73_REG_7,
1142   PREFIX_VEX_0F74,
1143   PREFIX_VEX_0F75,
1144   PREFIX_VEX_0F76,
1145   PREFIX_VEX_0F77,
1146   PREFIX_VEX_0F7C,
1147   PREFIX_VEX_0F7D,
1148   PREFIX_VEX_0F7E,
1149   PREFIX_VEX_0F7F,
1150   PREFIX_VEX_0F90,
1151   PREFIX_VEX_0F91,
1152   PREFIX_VEX_0F92,
1153   PREFIX_VEX_0F93,
1154   PREFIX_VEX_0F98,
1155   PREFIX_VEX_0F99,
1156   PREFIX_VEX_0FC2,
1157   PREFIX_VEX_0FC4,
1158   PREFIX_VEX_0FC5,
1159   PREFIX_VEX_0FD0,
1160   PREFIX_VEX_0FD1,
1161   PREFIX_VEX_0FD2,
1162   PREFIX_VEX_0FD3,
1163   PREFIX_VEX_0FD4,
1164   PREFIX_VEX_0FD5,
1165   PREFIX_VEX_0FD6,
1166   PREFIX_VEX_0FD7,
1167   PREFIX_VEX_0FD8,
1168   PREFIX_VEX_0FD9,
1169   PREFIX_VEX_0FDA,
1170   PREFIX_VEX_0FDB,
1171   PREFIX_VEX_0FDC,
1172   PREFIX_VEX_0FDD,
1173   PREFIX_VEX_0FDE,
1174   PREFIX_VEX_0FDF,
1175   PREFIX_VEX_0FE0,
1176   PREFIX_VEX_0FE1,
1177   PREFIX_VEX_0FE2,
1178   PREFIX_VEX_0FE3,
1179   PREFIX_VEX_0FE4,
1180   PREFIX_VEX_0FE5,
1181   PREFIX_VEX_0FE6,
1182   PREFIX_VEX_0FE7,
1183   PREFIX_VEX_0FE8,
1184   PREFIX_VEX_0FE9,
1185   PREFIX_VEX_0FEA,
1186   PREFIX_VEX_0FEB,
1187   PREFIX_VEX_0FEC,
1188   PREFIX_VEX_0FED,
1189   PREFIX_VEX_0FEE,
1190   PREFIX_VEX_0FEF,
1191   PREFIX_VEX_0FF0,
1192   PREFIX_VEX_0FF1,
1193   PREFIX_VEX_0FF2,
1194   PREFIX_VEX_0FF3,
1195   PREFIX_VEX_0FF4,
1196   PREFIX_VEX_0FF5,
1197   PREFIX_VEX_0FF6,
1198   PREFIX_VEX_0FF7,
1199   PREFIX_VEX_0FF8,
1200   PREFIX_VEX_0FF9,
1201   PREFIX_VEX_0FFA,
1202   PREFIX_VEX_0FFB,
1203   PREFIX_VEX_0FFC,
1204   PREFIX_VEX_0FFD,
1205   PREFIX_VEX_0FFE,
1206   PREFIX_VEX_0F3800,
1207   PREFIX_VEX_0F3801,
1208   PREFIX_VEX_0F3802,
1209   PREFIX_VEX_0F3803,
1210   PREFIX_VEX_0F3804,
1211   PREFIX_VEX_0F3805,
1212   PREFIX_VEX_0F3806,
1213   PREFIX_VEX_0F3807,
1214   PREFIX_VEX_0F3808,
1215   PREFIX_VEX_0F3809,
1216   PREFIX_VEX_0F380A,
1217   PREFIX_VEX_0F380B,
1218   PREFIX_VEX_0F380C,
1219   PREFIX_VEX_0F380D,
1220   PREFIX_VEX_0F380E,
1221   PREFIX_VEX_0F380F,
1222   PREFIX_VEX_0F3813,
1223   PREFIX_VEX_0F3816,
1224   PREFIX_VEX_0F3817,
1225   PREFIX_VEX_0F3818,
1226   PREFIX_VEX_0F3819,
1227   PREFIX_VEX_0F381A,
1228   PREFIX_VEX_0F381C,
1229   PREFIX_VEX_0F381D,
1230   PREFIX_VEX_0F381E,
1231   PREFIX_VEX_0F3820,
1232   PREFIX_VEX_0F3821,
1233   PREFIX_VEX_0F3822,
1234   PREFIX_VEX_0F3823,
1235   PREFIX_VEX_0F3824,
1236   PREFIX_VEX_0F3825,
1237   PREFIX_VEX_0F3828,
1238   PREFIX_VEX_0F3829,
1239   PREFIX_VEX_0F382A,
1240   PREFIX_VEX_0F382B,
1241   PREFIX_VEX_0F382C,
1242   PREFIX_VEX_0F382D,
1243   PREFIX_VEX_0F382E,
1244   PREFIX_VEX_0F382F,
1245   PREFIX_VEX_0F3830,
1246   PREFIX_VEX_0F3831,
1247   PREFIX_VEX_0F3832,
1248   PREFIX_VEX_0F3833,
1249   PREFIX_VEX_0F3834,
1250   PREFIX_VEX_0F3835,
1251   PREFIX_VEX_0F3836,
1252   PREFIX_VEX_0F3837,
1253   PREFIX_VEX_0F3838,
1254   PREFIX_VEX_0F3839,
1255   PREFIX_VEX_0F383A,
1256   PREFIX_VEX_0F383B,
1257   PREFIX_VEX_0F383C,
1258   PREFIX_VEX_0F383D,
1259   PREFIX_VEX_0F383E,
1260   PREFIX_VEX_0F383F,
1261   PREFIX_VEX_0F3840,
1262   PREFIX_VEX_0F3841,
1263   PREFIX_VEX_0F3845,
1264   PREFIX_VEX_0F3846,
1265   PREFIX_VEX_0F3847,
1266   PREFIX_VEX_0F3858,
1267   PREFIX_VEX_0F3859,
1268   PREFIX_VEX_0F385A,
1269   PREFIX_VEX_0F3878,
1270   PREFIX_VEX_0F3879,
1271   PREFIX_VEX_0F388C,
1272   PREFIX_VEX_0F388E,
1273   PREFIX_VEX_0F3890,
1274   PREFIX_VEX_0F3891,
1275   PREFIX_VEX_0F3892,
1276   PREFIX_VEX_0F3893,
1277   PREFIX_VEX_0F3896,
1278   PREFIX_VEX_0F3897,
1279   PREFIX_VEX_0F3898,
1280   PREFIX_VEX_0F3899,
1281   PREFIX_VEX_0F389A,
1282   PREFIX_VEX_0F389B,
1283   PREFIX_VEX_0F389C,
1284   PREFIX_VEX_0F389D,
1285   PREFIX_VEX_0F389E,
1286   PREFIX_VEX_0F389F,
1287   PREFIX_VEX_0F38A6,
1288   PREFIX_VEX_0F38A7,
1289   PREFIX_VEX_0F38A8,
1290   PREFIX_VEX_0F38A9,
1291   PREFIX_VEX_0F38AA,
1292   PREFIX_VEX_0F38AB,
1293   PREFIX_VEX_0F38AC,
1294   PREFIX_VEX_0F38AD,
1295   PREFIX_VEX_0F38AE,
1296   PREFIX_VEX_0F38AF,
1297   PREFIX_VEX_0F38B6,
1298   PREFIX_VEX_0F38B7,
1299   PREFIX_VEX_0F38B8,
1300   PREFIX_VEX_0F38B9,
1301   PREFIX_VEX_0F38BA,
1302   PREFIX_VEX_0F38BB,
1303   PREFIX_VEX_0F38BC,
1304   PREFIX_VEX_0F38BD,
1305   PREFIX_VEX_0F38BE,
1306   PREFIX_VEX_0F38BF,
1307   PREFIX_VEX_0F38DB,
1308   PREFIX_VEX_0F38DC,
1309   PREFIX_VEX_0F38DD,
1310   PREFIX_VEX_0F38DE,
1311   PREFIX_VEX_0F38DF,
1312   PREFIX_VEX_0F38F2,
1313   PREFIX_VEX_0F38F3_REG_1,
1314   PREFIX_VEX_0F38F3_REG_2,
1315   PREFIX_VEX_0F38F3_REG_3,
1316   PREFIX_VEX_0F38F5,
1317   PREFIX_VEX_0F38F6,
1318   PREFIX_VEX_0F38F7,
1319   PREFIX_VEX_0F3A00,
1320   PREFIX_VEX_0F3A01,
1321   PREFIX_VEX_0F3A02,
1322   PREFIX_VEX_0F3A04,
1323   PREFIX_VEX_0F3A05,
1324   PREFIX_VEX_0F3A06,
1325   PREFIX_VEX_0F3A08,
1326   PREFIX_VEX_0F3A09,
1327   PREFIX_VEX_0F3A0A,
1328   PREFIX_VEX_0F3A0B,
1329   PREFIX_VEX_0F3A0C,
1330   PREFIX_VEX_0F3A0D,
1331   PREFIX_VEX_0F3A0E,
1332   PREFIX_VEX_0F3A0F,
1333   PREFIX_VEX_0F3A14,
1334   PREFIX_VEX_0F3A15,
1335   PREFIX_VEX_0F3A16,
1336   PREFIX_VEX_0F3A17,
1337   PREFIX_VEX_0F3A18,
1338   PREFIX_VEX_0F3A19,
1339   PREFIX_VEX_0F3A1D,
1340   PREFIX_VEX_0F3A20,
1341   PREFIX_VEX_0F3A21,
1342   PREFIX_VEX_0F3A22,
1343   PREFIX_VEX_0F3A30,
1344   PREFIX_VEX_0F3A31,
1345   PREFIX_VEX_0F3A32,
1346   PREFIX_VEX_0F3A33,
1347   PREFIX_VEX_0F3A38,
1348   PREFIX_VEX_0F3A39,
1349   PREFIX_VEX_0F3A40,
1350   PREFIX_VEX_0F3A41,
1351   PREFIX_VEX_0F3A42,
1352   PREFIX_VEX_0F3A44,
1353   PREFIX_VEX_0F3A46,
1354   PREFIX_VEX_0F3A48,
1355   PREFIX_VEX_0F3A49,
1356   PREFIX_VEX_0F3A4A,
1357   PREFIX_VEX_0F3A4B,
1358   PREFIX_VEX_0F3A4C,
1359   PREFIX_VEX_0F3A5C,
1360   PREFIX_VEX_0F3A5D,
1361   PREFIX_VEX_0F3A5E,
1362   PREFIX_VEX_0F3A5F,
1363   PREFIX_VEX_0F3A60,
1364   PREFIX_VEX_0F3A61,
1365   PREFIX_VEX_0F3A62,
1366   PREFIX_VEX_0F3A63,
1367   PREFIX_VEX_0F3A68,
1368   PREFIX_VEX_0F3A69,
1369   PREFIX_VEX_0F3A6A,
1370   PREFIX_VEX_0F3A6B,
1371   PREFIX_VEX_0F3A6C,
1372   PREFIX_VEX_0F3A6D,
1373   PREFIX_VEX_0F3A6E,
1374   PREFIX_VEX_0F3A6F,
1375   PREFIX_VEX_0F3A78,
1376   PREFIX_VEX_0F3A79,
1377   PREFIX_VEX_0F3A7A,
1378   PREFIX_VEX_0F3A7B,
1379   PREFIX_VEX_0F3A7C,
1380   PREFIX_VEX_0F3A7D,
1381   PREFIX_VEX_0F3A7E,
1382   PREFIX_VEX_0F3A7F,
1383   PREFIX_VEX_0F3ADF,
1384   PREFIX_VEX_0F3AF0,
1385
1386   PREFIX_EVEX_0F10,
1387   PREFIX_EVEX_0F11,
1388   PREFIX_EVEX_0F12,
1389   PREFIX_EVEX_0F13,
1390   PREFIX_EVEX_0F14,
1391   PREFIX_EVEX_0F15,
1392   PREFIX_EVEX_0F16,
1393   PREFIX_EVEX_0F17,
1394   PREFIX_EVEX_0F28,
1395   PREFIX_EVEX_0F29,
1396   PREFIX_EVEX_0F2A,
1397   PREFIX_EVEX_0F2B,
1398   PREFIX_EVEX_0F2C,
1399   PREFIX_EVEX_0F2D,
1400   PREFIX_EVEX_0F2E,
1401   PREFIX_EVEX_0F2F,
1402   PREFIX_EVEX_0F51,
1403   PREFIX_EVEX_0F54,
1404   PREFIX_EVEX_0F55,
1405   PREFIX_EVEX_0F56,
1406   PREFIX_EVEX_0F57,
1407   PREFIX_EVEX_0F58,
1408   PREFIX_EVEX_0F59,
1409   PREFIX_EVEX_0F5A,
1410   PREFIX_EVEX_0F5B,
1411   PREFIX_EVEX_0F5C,
1412   PREFIX_EVEX_0F5D,
1413   PREFIX_EVEX_0F5E,
1414   PREFIX_EVEX_0F5F,
1415   PREFIX_EVEX_0F60,
1416   PREFIX_EVEX_0F61,
1417   PREFIX_EVEX_0F62,
1418   PREFIX_EVEX_0F63,
1419   PREFIX_EVEX_0F64,
1420   PREFIX_EVEX_0F65,
1421   PREFIX_EVEX_0F66,
1422   PREFIX_EVEX_0F67,
1423   PREFIX_EVEX_0F68,
1424   PREFIX_EVEX_0F69,
1425   PREFIX_EVEX_0F6A,
1426   PREFIX_EVEX_0F6B,
1427   PREFIX_EVEX_0F6C,
1428   PREFIX_EVEX_0F6D,
1429   PREFIX_EVEX_0F6E,
1430   PREFIX_EVEX_0F6F,
1431   PREFIX_EVEX_0F70,
1432   PREFIX_EVEX_0F71_REG_2,
1433   PREFIX_EVEX_0F71_REG_4,
1434   PREFIX_EVEX_0F71_REG_6,
1435   PREFIX_EVEX_0F72_REG_0,
1436   PREFIX_EVEX_0F72_REG_1,
1437   PREFIX_EVEX_0F72_REG_2,
1438   PREFIX_EVEX_0F72_REG_4,
1439   PREFIX_EVEX_0F72_REG_6,
1440   PREFIX_EVEX_0F73_REG_2,
1441   PREFIX_EVEX_0F73_REG_3,
1442   PREFIX_EVEX_0F73_REG_6,
1443   PREFIX_EVEX_0F73_REG_7,
1444   PREFIX_EVEX_0F74,
1445   PREFIX_EVEX_0F75,
1446   PREFIX_EVEX_0F76,
1447   PREFIX_EVEX_0F78,
1448   PREFIX_EVEX_0F79,
1449   PREFIX_EVEX_0F7A,
1450   PREFIX_EVEX_0F7B,
1451   PREFIX_EVEX_0F7E,
1452   PREFIX_EVEX_0F7F,
1453   PREFIX_EVEX_0FC2,
1454   PREFIX_EVEX_0FC4,
1455   PREFIX_EVEX_0FC5,
1456   PREFIX_EVEX_0FC6,
1457   PREFIX_EVEX_0FD1,
1458   PREFIX_EVEX_0FD2,
1459   PREFIX_EVEX_0FD3,
1460   PREFIX_EVEX_0FD4,
1461   PREFIX_EVEX_0FD5,
1462   PREFIX_EVEX_0FD6,
1463   PREFIX_EVEX_0FD8,
1464   PREFIX_EVEX_0FD9,
1465   PREFIX_EVEX_0FDA,
1466   PREFIX_EVEX_0FDB,
1467   PREFIX_EVEX_0FDC,
1468   PREFIX_EVEX_0FDD,
1469   PREFIX_EVEX_0FDE,
1470   PREFIX_EVEX_0FDF,
1471   PREFIX_EVEX_0FE0,
1472   PREFIX_EVEX_0FE1,
1473   PREFIX_EVEX_0FE2,
1474   PREFIX_EVEX_0FE3,
1475   PREFIX_EVEX_0FE4,
1476   PREFIX_EVEX_0FE5,
1477   PREFIX_EVEX_0FE6,
1478   PREFIX_EVEX_0FE7,
1479   PREFIX_EVEX_0FE8,
1480   PREFIX_EVEX_0FE9,
1481   PREFIX_EVEX_0FEA,
1482   PREFIX_EVEX_0FEB,
1483   PREFIX_EVEX_0FEC,
1484   PREFIX_EVEX_0FED,
1485   PREFIX_EVEX_0FEE,
1486   PREFIX_EVEX_0FEF,
1487   PREFIX_EVEX_0FF1,
1488   PREFIX_EVEX_0FF2,
1489   PREFIX_EVEX_0FF3,
1490   PREFIX_EVEX_0FF4,
1491   PREFIX_EVEX_0FF5,
1492   PREFIX_EVEX_0FF6,
1493   PREFIX_EVEX_0FF8,
1494   PREFIX_EVEX_0FF9,
1495   PREFIX_EVEX_0FFA,
1496   PREFIX_EVEX_0FFB,
1497   PREFIX_EVEX_0FFC,
1498   PREFIX_EVEX_0FFD,
1499   PREFIX_EVEX_0FFE,
1500   PREFIX_EVEX_0F3800,
1501   PREFIX_EVEX_0F3804,
1502   PREFIX_EVEX_0F380B,
1503   PREFIX_EVEX_0F380C,
1504   PREFIX_EVEX_0F380D,
1505   PREFIX_EVEX_0F3810,
1506   PREFIX_EVEX_0F3811,
1507   PREFIX_EVEX_0F3812,
1508   PREFIX_EVEX_0F3813,
1509   PREFIX_EVEX_0F3814,
1510   PREFIX_EVEX_0F3815,
1511   PREFIX_EVEX_0F3816,
1512   PREFIX_EVEX_0F3818,
1513   PREFIX_EVEX_0F3819,
1514   PREFIX_EVEX_0F381A,
1515   PREFIX_EVEX_0F381B,
1516   PREFIX_EVEX_0F381C,
1517   PREFIX_EVEX_0F381D,
1518   PREFIX_EVEX_0F381E,
1519   PREFIX_EVEX_0F381F,
1520   PREFIX_EVEX_0F3820,
1521   PREFIX_EVEX_0F3821,
1522   PREFIX_EVEX_0F3822,
1523   PREFIX_EVEX_0F3823,
1524   PREFIX_EVEX_0F3824,
1525   PREFIX_EVEX_0F3825,
1526   PREFIX_EVEX_0F3826,
1527   PREFIX_EVEX_0F3827,
1528   PREFIX_EVEX_0F3828,
1529   PREFIX_EVEX_0F3829,
1530   PREFIX_EVEX_0F382A,
1531   PREFIX_EVEX_0F382B,
1532   PREFIX_EVEX_0F382C,
1533   PREFIX_EVEX_0F382D,
1534   PREFIX_EVEX_0F3830,
1535   PREFIX_EVEX_0F3831,
1536   PREFIX_EVEX_0F3832,
1537   PREFIX_EVEX_0F3833,
1538   PREFIX_EVEX_0F3834,
1539   PREFIX_EVEX_0F3835,
1540   PREFIX_EVEX_0F3836,
1541   PREFIX_EVEX_0F3837,
1542   PREFIX_EVEX_0F3838,
1543   PREFIX_EVEX_0F3839,
1544   PREFIX_EVEX_0F383A,
1545   PREFIX_EVEX_0F383B,
1546   PREFIX_EVEX_0F383C,
1547   PREFIX_EVEX_0F383D,
1548   PREFIX_EVEX_0F383E,
1549   PREFIX_EVEX_0F383F,
1550   PREFIX_EVEX_0F3840,
1551   PREFIX_EVEX_0F3842,
1552   PREFIX_EVEX_0F3843,
1553   PREFIX_EVEX_0F3844,
1554   PREFIX_EVEX_0F3845,
1555   PREFIX_EVEX_0F3846,
1556   PREFIX_EVEX_0F3847,
1557   PREFIX_EVEX_0F384C,
1558   PREFIX_EVEX_0F384D,
1559   PREFIX_EVEX_0F384E,
1560   PREFIX_EVEX_0F384F,
1561   PREFIX_EVEX_0F3852,
1562   PREFIX_EVEX_0F3853,
1563   PREFIX_EVEX_0F3855,
1564   PREFIX_EVEX_0F3858,
1565   PREFIX_EVEX_0F3859,
1566   PREFIX_EVEX_0F385A,
1567   PREFIX_EVEX_0F385B,
1568   PREFIX_EVEX_0F3864,
1569   PREFIX_EVEX_0F3865,
1570   PREFIX_EVEX_0F3866,
1571   PREFIX_EVEX_0F3875,
1572   PREFIX_EVEX_0F3876,
1573   PREFIX_EVEX_0F3877,
1574   PREFIX_EVEX_0F3878,
1575   PREFIX_EVEX_0F3879,
1576   PREFIX_EVEX_0F387A,
1577   PREFIX_EVEX_0F387B,
1578   PREFIX_EVEX_0F387C,
1579   PREFIX_EVEX_0F387D,
1580   PREFIX_EVEX_0F387E,
1581   PREFIX_EVEX_0F387F,
1582   PREFIX_EVEX_0F3883,
1583   PREFIX_EVEX_0F3888,
1584   PREFIX_EVEX_0F3889,
1585   PREFIX_EVEX_0F388A,
1586   PREFIX_EVEX_0F388B,
1587   PREFIX_EVEX_0F388D,
1588   PREFIX_EVEX_0F3890,
1589   PREFIX_EVEX_0F3891,
1590   PREFIX_EVEX_0F3892,
1591   PREFIX_EVEX_0F3893,
1592   PREFIX_EVEX_0F3896,
1593   PREFIX_EVEX_0F3897,
1594   PREFIX_EVEX_0F3898,
1595   PREFIX_EVEX_0F3899,
1596   PREFIX_EVEX_0F389A,
1597   PREFIX_EVEX_0F389B,
1598   PREFIX_EVEX_0F389C,
1599   PREFIX_EVEX_0F389D,
1600   PREFIX_EVEX_0F389E,
1601   PREFIX_EVEX_0F389F,
1602   PREFIX_EVEX_0F38A0,
1603   PREFIX_EVEX_0F38A1,
1604   PREFIX_EVEX_0F38A2,
1605   PREFIX_EVEX_0F38A3,
1606   PREFIX_EVEX_0F38A6,
1607   PREFIX_EVEX_0F38A7,
1608   PREFIX_EVEX_0F38A8,
1609   PREFIX_EVEX_0F38A9,
1610   PREFIX_EVEX_0F38AA,
1611   PREFIX_EVEX_0F38AB,
1612   PREFIX_EVEX_0F38AC,
1613   PREFIX_EVEX_0F38AD,
1614   PREFIX_EVEX_0F38AE,
1615   PREFIX_EVEX_0F38AF,
1616   PREFIX_EVEX_0F38B4,
1617   PREFIX_EVEX_0F38B5,
1618   PREFIX_EVEX_0F38B6,
1619   PREFIX_EVEX_0F38B7,
1620   PREFIX_EVEX_0F38B8,
1621   PREFIX_EVEX_0F38B9,
1622   PREFIX_EVEX_0F38BA,
1623   PREFIX_EVEX_0F38BB,
1624   PREFIX_EVEX_0F38BC,
1625   PREFIX_EVEX_0F38BD,
1626   PREFIX_EVEX_0F38BE,
1627   PREFIX_EVEX_0F38BF,
1628   PREFIX_EVEX_0F38C4,
1629   PREFIX_EVEX_0F38C6_REG_1,
1630   PREFIX_EVEX_0F38C6_REG_2,
1631   PREFIX_EVEX_0F38C6_REG_5,
1632   PREFIX_EVEX_0F38C6_REG_6,
1633   PREFIX_EVEX_0F38C7_REG_1,
1634   PREFIX_EVEX_0F38C7_REG_2,
1635   PREFIX_EVEX_0F38C7_REG_5,
1636   PREFIX_EVEX_0F38C7_REG_6,
1637   PREFIX_EVEX_0F38C8,
1638   PREFIX_EVEX_0F38CA,
1639   PREFIX_EVEX_0F38CB,
1640   PREFIX_EVEX_0F38CC,
1641   PREFIX_EVEX_0F38CD,
1642
1643   PREFIX_EVEX_0F3A00,
1644   PREFIX_EVEX_0F3A01,
1645   PREFIX_EVEX_0F3A03,
1646   PREFIX_EVEX_0F3A04,
1647   PREFIX_EVEX_0F3A05,
1648   PREFIX_EVEX_0F3A08,
1649   PREFIX_EVEX_0F3A09,
1650   PREFIX_EVEX_0F3A0A,
1651   PREFIX_EVEX_0F3A0B,
1652   PREFIX_EVEX_0F3A0F,
1653   PREFIX_EVEX_0F3A14,
1654   PREFIX_EVEX_0F3A15,
1655   PREFIX_EVEX_0F3A16,
1656   PREFIX_EVEX_0F3A17,
1657   PREFIX_EVEX_0F3A18,
1658   PREFIX_EVEX_0F3A19,
1659   PREFIX_EVEX_0F3A1A,
1660   PREFIX_EVEX_0F3A1B,
1661   PREFIX_EVEX_0F3A1D,
1662   PREFIX_EVEX_0F3A1E,
1663   PREFIX_EVEX_0F3A1F,
1664   PREFIX_EVEX_0F3A20,
1665   PREFIX_EVEX_0F3A21,
1666   PREFIX_EVEX_0F3A22,
1667   PREFIX_EVEX_0F3A23,
1668   PREFIX_EVEX_0F3A25,
1669   PREFIX_EVEX_0F3A26,
1670   PREFIX_EVEX_0F3A27,
1671   PREFIX_EVEX_0F3A38,
1672   PREFIX_EVEX_0F3A39,
1673   PREFIX_EVEX_0F3A3A,
1674   PREFIX_EVEX_0F3A3B,
1675   PREFIX_EVEX_0F3A3E,
1676   PREFIX_EVEX_0F3A3F,
1677   PREFIX_EVEX_0F3A42,
1678   PREFIX_EVEX_0F3A43,
1679   PREFIX_EVEX_0F3A50,
1680   PREFIX_EVEX_0F3A51,
1681   PREFIX_EVEX_0F3A54,
1682   PREFIX_EVEX_0F3A55,
1683   PREFIX_EVEX_0F3A56,
1684   PREFIX_EVEX_0F3A57,
1685   PREFIX_EVEX_0F3A66,
1686   PREFIX_EVEX_0F3A67
1687 };
1688
1689 enum
1690 {
1691   X86_64_06 = 0,
1692   X86_64_07,
1693   X86_64_0D,
1694   X86_64_16,
1695   X86_64_17,
1696   X86_64_1E,
1697   X86_64_1F,
1698   X86_64_27,
1699   X86_64_2F,
1700   X86_64_37,
1701   X86_64_3F,
1702   X86_64_60,
1703   X86_64_61,
1704   X86_64_62,
1705   X86_64_63,
1706   X86_64_6D,
1707   X86_64_6F,
1708   X86_64_82,
1709   X86_64_9A,
1710   X86_64_C4,
1711   X86_64_C5,
1712   X86_64_CE,
1713   X86_64_D4,
1714   X86_64_D5,
1715   X86_64_E8,
1716   X86_64_E9,
1717   X86_64_EA,
1718   X86_64_0F01_REG_0,
1719   X86_64_0F01_REG_1,
1720   X86_64_0F01_REG_2,
1721   X86_64_0F01_REG_3
1722 };
1723
1724 enum
1725 {
1726   THREE_BYTE_0F38 = 0,
1727   THREE_BYTE_0F3A
1728 };
1729
1730 enum
1731 {
1732   XOP_08 = 0,
1733   XOP_09,
1734   XOP_0A
1735 };
1736
1737 enum
1738 {
1739   VEX_0F = 0,
1740   VEX_0F38,
1741   VEX_0F3A
1742 };
1743
1744 enum
1745 {
1746   EVEX_0F = 0,
1747   EVEX_0F38,
1748   EVEX_0F3A
1749 };
1750
1751 enum
1752 {
1753   VEX_LEN_0F10_P_1 = 0,
1754   VEX_LEN_0F10_P_3,
1755   VEX_LEN_0F11_P_1,
1756   VEX_LEN_0F11_P_3,
1757   VEX_LEN_0F12_P_0_M_0,
1758   VEX_LEN_0F12_P_0_M_1,
1759   VEX_LEN_0F12_P_2,
1760   VEX_LEN_0F13_M_0,
1761   VEX_LEN_0F16_P_0_M_0,
1762   VEX_LEN_0F16_P_0_M_1,
1763   VEX_LEN_0F16_P_2,
1764   VEX_LEN_0F17_M_0,
1765   VEX_LEN_0F2A_P_1,
1766   VEX_LEN_0F2A_P_3,
1767   VEX_LEN_0F2C_P_1,
1768   VEX_LEN_0F2C_P_3,
1769   VEX_LEN_0F2D_P_1,
1770   VEX_LEN_0F2D_P_3,
1771   VEX_LEN_0F2E_P_0,
1772   VEX_LEN_0F2E_P_2,
1773   VEX_LEN_0F2F_P_0,
1774   VEX_LEN_0F2F_P_2,
1775   VEX_LEN_0F41_P_0,
1776   VEX_LEN_0F41_P_2,
1777   VEX_LEN_0F42_P_0,
1778   VEX_LEN_0F42_P_2,
1779   VEX_LEN_0F44_P_0,
1780   VEX_LEN_0F44_P_2,
1781   VEX_LEN_0F45_P_0,
1782   VEX_LEN_0F45_P_2,
1783   VEX_LEN_0F46_P_0,
1784   VEX_LEN_0F46_P_2,
1785   VEX_LEN_0F47_P_0,
1786   VEX_LEN_0F47_P_2,
1787   VEX_LEN_0F4A_P_0,
1788   VEX_LEN_0F4A_P_2,
1789   VEX_LEN_0F4B_P_0,
1790   VEX_LEN_0F4B_P_2,
1791   VEX_LEN_0F51_P_1,
1792   VEX_LEN_0F51_P_3,
1793   VEX_LEN_0F52_P_1,
1794   VEX_LEN_0F53_P_1,
1795   VEX_LEN_0F58_P_1,
1796   VEX_LEN_0F58_P_3,
1797   VEX_LEN_0F59_P_1,
1798   VEX_LEN_0F59_P_3,
1799   VEX_LEN_0F5A_P_1,
1800   VEX_LEN_0F5A_P_3,
1801   VEX_LEN_0F5C_P_1,
1802   VEX_LEN_0F5C_P_3,
1803   VEX_LEN_0F5D_P_1,
1804   VEX_LEN_0F5D_P_3,
1805   VEX_LEN_0F5E_P_1,
1806   VEX_LEN_0F5E_P_3,
1807   VEX_LEN_0F5F_P_1,
1808   VEX_LEN_0F5F_P_3,
1809   VEX_LEN_0F6E_P_2,
1810   VEX_LEN_0F7E_P_1,
1811   VEX_LEN_0F7E_P_2,
1812   VEX_LEN_0F90_P_0,
1813   VEX_LEN_0F90_P_2,
1814   VEX_LEN_0F91_P_0,
1815   VEX_LEN_0F91_P_2,
1816   VEX_LEN_0F92_P_0,
1817   VEX_LEN_0F92_P_2,
1818   VEX_LEN_0F92_P_3,
1819   VEX_LEN_0F93_P_0,
1820   VEX_LEN_0F93_P_2,
1821   VEX_LEN_0F93_P_3,
1822   VEX_LEN_0F98_P_0,
1823   VEX_LEN_0F98_P_2,
1824   VEX_LEN_0F99_P_0,
1825   VEX_LEN_0F99_P_2,
1826   VEX_LEN_0FAE_R_2_M_0,
1827   VEX_LEN_0FAE_R_3_M_0,
1828   VEX_LEN_0FC2_P_1,
1829   VEX_LEN_0FC2_P_3,
1830   VEX_LEN_0FC4_P_2,
1831   VEX_LEN_0FC5_P_2,
1832   VEX_LEN_0FD6_P_2,
1833   VEX_LEN_0FF7_P_2,
1834   VEX_LEN_0F3816_P_2,
1835   VEX_LEN_0F3819_P_2,
1836   VEX_LEN_0F381A_P_2_M_0,
1837   VEX_LEN_0F3836_P_2,
1838   VEX_LEN_0F3841_P_2,
1839   VEX_LEN_0F385A_P_2_M_0,
1840   VEX_LEN_0F38DB_P_2,
1841   VEX_LEN_0F38DC_P_2,
1842   VEX_LEN_0F38DD_P_2,
1843   VEX_LEN_0F38DE_P_2,
1844   VEX_LEN_0F38DF_P_2,
1845   VEX_LEN_0F38F2_P_0,
1846   VEX_LEN_0F38F3_R_1_P_0,
1847   VEX_LEN_0F38F3_R_2_P_0,
1848   VEX_LEN_0F38F3_R_3_P_0,
1849   VEX_LEN_0F38F5_P_0,
1850   VEX_LEN_0F38F5_P_1,
1851   VEX_LEN_0F38F5_P_3,
1852   VEX_LEN_0F38F6_P_3,
1853   VEX_LEN_0F38F7_P_0,
1854   VEX_LEN_0F38F7_P_1,
1855   VEX_LEN_0F38F7_P_2,
1856   VEX_LEN_0F38F7_P_3,
1857   VEX_LEN_0F3A00_P_2,
1858   VEX_LEN_0F3A01_P_2,
1859   VEX_LEN_0F3A06_P_2,
1860   VEX_LEN_0F3A0A_P_2,
1861   VEX_LEN_0F3A0B_P_2,
1862   VEX_LEN_0F3A14_P_2,
1863   VEX_LEN_0F3A15_P_2,
1864   VEX_LEN_0F3A16_P_2,
1865   VEX_LEN_0F3A17_P_2,
1866   VEX_LEN_0F3A18_P_2,
1867   VEX_LEN_0F3A19_P_2,
1868   VEX_LEN_0F3A20_P_2,
1869   VEX_LEN_0F3A21_P_2,
1870   VEX_LEN_0F3A22_P_2,
1871   VEX_LEN_0F3A30_P_2,
1872   VEX_LEN_0F3A31_P_2,
1873   VEX_LEN_0F3A32_P_2,
1874   VEX_LEN_0F3A33_P_2,
1875   VEX_LEN_0F3A38_P_2,
1876   VEX_LEN_0F3A39_P_2,
1877   VEX_LEN_0F3A41_P_2,
1878   VEX_LEN_0F3A44_P_2,
1879   VEX_LEN_0F3A46_P_2,
1880   VEX_LEN_0F3A60_P_2,
1881   VEX_LEN_0F3A61_P_2,
1882   VEX_LEN_0F3A62_P_2,
1883   VEX_LEN_0F3A63_P_2,
1884   VEX_LEN_0F3A6A_P_2,
1885   VEX_LEN_0F3A6B_P_2,
1886   VEX_LEN_0F3A6E_P_2,
1887   VEX_LEN_0F3A6F_P_2,
1888   VEX_LEN_0F3A7A_P_2,
1889   VEX_LEN_0F3A7B_P_2,
1890   VEX_LEN_0F3A7E_P_2,
1891   VEX_LEN_0F3A7F_P_2,
1892   VEX_LEN_0F3ADF_P_2,
1893   VEX_LEN_0F3AF0_P_3,
1894   VEX_LEN_0FXOP_08_CC,
1895   VEX_LEN_0FXOP_08_CD,
1896   VEX_LEN_0FXOP_08_CE,
1897   VEX_LEN_0FXOP_08_CF,
1898   VEX_LEN_0FXOP_08_EC,
1899   VEX_LEN_0FXOP_08_ED,
1900   VEX_LEN_0FXOP_08_EE,
1901   VEX_LEN_0FXOP_08_EF,
1902   VEX_LEN_0FXOP_09_80,
1903   VEX_LEN_0FXOP_09_81
1904 };
1905
1906 enum
1907 {
1908   VEX_W_0F10_P_0 = 0,
1909   VEX_W_0F10_P_1,
1910   VEX_W_0F10_P_2,
1911   VEX_W_0F10_P_3,
1912   VEX_W_0F11_P_0,
1913   VEX_W_0F11_P_1,
1914   VEX_W_0F11_P_2,
1915   VEX_W_0F11_P_3,
1916   VEX_W_0F12_P_0_M_0,
1917   VEX_W_0F12_P_0_M_1,
1918   VEX_W_0F12_P_1,
1919   VEX_W_0F12_P_2,
1920   VEX_W_0F12_P_3,
1921   VEX_W_0F13_M_0,
1922   VEX_W_0F14,
1923   VEX_W_0F15,
1924   VEX_W_0F16_P_0_M_0,
1925   VEX_W_0F16_P_0_M_1,
1926   VEX_W_0F16_P_1,
1927   VEX_W_0F16_P_2,
1928   VEX_W_0F17_M_0,
1929   VEX_W_0F28,
1930   VEX_W_0F29,
1931   VEX_W_0F2B_M_0,
1932   VEX_W_0F2E_P_0,
1933   VEX_W_0F2E_P_2,
1934   VEX_W_0F2F_P_0,
1935   VEX_W_0F2F_P_2,
1936   VEX_W_0F41_P_0_LEN_1,
1937   VEX_W_0F41_P_2_LEN_1,
1938   VEX_W_0F42_P_0_LEN_1,
1939   VEX_W_0F42_P_2_LEN_1,
1940   VEX_W_0F44_P_0_LEN_0,
1941   VEX_W_0F44_P_2_LEN_0,
1942   VEX_W_0F45_P_0_LEN_1,
1943   VEX_W_0F45_P_2_LEN_1,
1944   VEX_W_0F46_P_0_LEN_1,
1945   VEX_W_0F46_P_2_LEN_1,
1946   VEX_W_0F47_P_0_LEN_1,
1947   VEX_W_0F47_P_2_LEN_1,
1948   VEX_W_0F4A_P_0_LEN_1,
1949   VEX_W_0F4A_P_2_LEN_1,
1950   VEX_W_0F4B_P_0_LEN_1,
1951   VEX_W_0F4B_P_2_LEN_1,
1952   VEX_W_0F50_M_0,
1953   VEX_W_0F51_P_0,
1954   VEX_W_0F51_P_1,
1955   VEX_W_0F51_P_2,
1956   VEX_W_0F51_P_3,
1957   VEX_W_0F52_P_0,
1958   VEX_W_0F52_P_1,
1959   VEX_W_0F53_P_0,
1960   VEX_W_0F53_P_1,
1961   VEX_W_0F58_P_0,
1962   VEX_W_0F58_P_1,
1963   VEX_W_0F58_P_2,
1964   VEX_W_0F58_P_3,
1965   VEX_W_0F59_P_0,
1966   VEX_W_0F59_P_1,
1967   VEX_W_0F59_P_2,
1968   VEX_W_0F59_P_3,
1969   VEX_W_0F5A_P_0,
1970   VEX_W_0F5A_P_1,
1971   VEX_W_0F5A_P_3,
1972   VEX_W_0F5B_P_0,
1973   VEX_W_0F5B_P_1,
1974   VEX_W_0F5B_P_2,
1975   VEX_W_0F5C_P_0,
1976   VEX_W_0F5C_P_1,
1977   VEX_W_0F5C_P_2,
1978   VEX_W_0F5C_P_3,
1979   VEX_W_0F5D_P_0,
1980   VEX_W_0F5D_P_1,
1981   VEX_W_0F5D_P_2,
1982   VEX_W_0F5D_P_3,
1983   VEX_W_0F5E_P_0,
1984   VEX_W_0F5E_P_1,
1985   VEX_W_0F5E_P_2,
1986   VEX_W_0F5E_P_3,
1987   VEX_W_0F5F_P_0,
1988   VEX_W_0F5F_P_1,
1989   VEX_W_0F5F_P_2,
1990   VEX_W_0F5F_P_3,
1991   VEX_W_0F60_P_2,
1992   VEX_W_0F61_P_2,
1993   VEX_W_0F62_P_2,
1994   VEX_W_0F63_P_2,
1995   VEX_W_0F64_P_2,
1996   VEX_W_0F65_P_2,
1997   VEX_W_0F66_P_2,
1998   VEX_W_0F67_P_2,
1999   VEX_W_0F68_P_2,
2000   VEX_W_0F69_P_2,
2001   VEX_W_0F6A_P_2,
2002   VEX_W_0F6B_P_2,
2003   VEX_W_0F6C_P_2,
2004   VEX_W_0F6D_P_2,
2005   VEX_W_0F6F_P_1,
2006   VEX_W_0F6F_P_2,
2007   VEX_W_0F70_P_1,
2008   VEX_W_0F70_P_2,
2009   VEX_W_0F70_P_3,
2010   VEX_W_0F71_R_2_P_2,
2011   VEX_W_0F71_R_4_P_2,
2012   VEX_W_0F71_R_6_P_2,
2013   VEX_W_0F72_R_2_P_2,
2014   VEX_W_0F72_R_4_P_2,
2015   VEX_W_0F72_R_6_P_2,
2016   VEX_W_0F73_R_2_P_2,
2017   VEX_W_0F73_R_3_P_2,
2018   VEX_W_0F73_R_6_P_2,
2019   VEX_W_0F73_R_7_P_2,
2020   VEX_W_0F74_P_2,
2021   VEX_W_0F75_P_2,
2022   VEX_W_0F76_P_2,
2023   VEX_W_0F77_P_0,
2024   VEX_W_0F7C_P_2,
2025   VEX_W_0F7C_P_3,
2026   VEX_W_0F7D_P_2,
2027   VEX_W_0F7D_P_3,
2028   VEX_W_0F7E_P_1,
2029   VEX_W_0F7F_P_1,
2030   VEX_W_0F7F_P_2,
2031   VEX_W_0F90_P_0_LEN_0,
2032   VEX_W_0F90_P_2_LEN_0,
2033   VEX_W_0F91_P_0_LEN_0,
2034   VEX_W_0F91_P_2_LEN_0,
2035   VEX_W_0F92_P_0_LEN_0,
2036   VEX_W_0F92_P_2_LEN_0,
2037   VEX_W_0F92_P_3_LEN_0,
2038   VEX_W_0F93_P_0_LEN_0,
2039   VEX_W_0F93_P_2_LEN_0,
2040   VEX_W_0F93_P_3_LEN_0,
2041   VEX_W_0F98_P_0_LEN_0,
2042   VEX_W_0F98_P_2_LEN_0,
2043   VEX_W_0F99_P_0_LEN_0,
2044   VEX_W_0F99_P_2_LEN_0,
2045   VEX_W_0FAE_R_2_M_0,
2046   VEX_W_0FAE_R_3_M_0,
2047   VEX_W_0FC2_P_0,
2048   VEX_W_0FC2_P_1,
2049   VEX_W_0FC2_P_2,
2050   VEX_W_0FC2_P_3,
2051   VEX_W_0FC4_P_2,
2052   VEX_W_0FC5_P_2,
2053   VEX_W_0FD0_P_2,
2054   VEX_W_0FD0_P_3,
2055   VEX_W_0FD1_P_2,
2056   VEX_W_0FD2_P_2,
2057   VEX_W_0FD3_P_2,
2058   VEX_W_0FD4_P_2,
2059   VEX_W_0FD5_P_2,
2060   VEX_W_0FD6_P_2,
2061   VEX_W_0FD7_P_2_M_1,
2062   VEX_W_0FD8_P_2,
2063   VEX_W_0FD9_P_2,
2064   VEX_W_0FDA_P_2,
2065   VEX_W_0FDB_P_2,
2066   VEX_W_0FDC_P_2,
2067   VEX_W_0FDD_P_2,
2068   VEX_W_0FDE_P_2,
2069   VEX_W_0FDF_P_2,
2070   VEX_W_0FE0_P_2,
2071   VEX_W_0FE1_P_2,
2072   VEX_W_0FE2_P_2,
2073   VEX_W_0FE3_P_2,
2074   VEX_W_0FE4_P_2,
2075   VEX_W_0FE5_P_2,
2076   VEX_W_0FE6_P_1,
2077   VEX_W_0FE6_P_2,
2078   VEX_W_0FE6_P_3,
2079   VEX_W_0FE7_P_2_M_0,
2080   VEX_W_0FE8_P_2,
2081   VEX_W_0FE9_P_2,
2082   VEX_W_0FEA_P_2,
2083   VEX_W_0FEB_P_2,
2084   VEX_W_0FEC_P_2,
2085   VEX_W_0FED_P_2,
2086   VEX_W_0FEE_P_2,
2087   VEX_W_0FEF_P_2,
2088   VEX_W_0FF0_P_3_M_0,
2089   VEX_W_0FF1_P_2,
2090   VEX_W_0FF2_P_2,
2091   VEX_W_0FF3_P_2,
2092   VEX_W_0FF4_P_2,
2093   VEX_W_0FF5_P_2,
2094   VEX_W_0FF6_P_2,
2095   VEX_W_0FF7_P_2,
2096   VEX_W_0FF8_P_2,
2097   VEX_W_0FF9_P_2,
2098   VEX_W_0FFA_P_2,
2099   VEX_W_0FFB_P_2,
2100   VEX_W_0FFC_P_2,
2101   VEX_W_0FFD_P_2,
2102   VEX_W_0FFE_P_2,
2103   VEX_W_0F3800_P_2,
2104   VEX_W_0F3801_P_2,
2105   VEX_W_0F3802_P_2,
2106   VEX_W_0F3803_P_2,
2107   VEX_W_0F3804_P_2,
2108   VEX_W_0F3805_P_2,
2109   VEX_W_0F3806_P_2,
2110   VEX_W_0F3807_P_2,
2111   VEX_W_0F3808_P_2,
2112   VEX_W_0F3809_P_2,
2113   VEX_W_0F380A_P_2,
2114   VEX_W_0F380B_P_2,
2115   VEX_W_0F380C_P_2,
2116   VEX_W_0F380D_P_2,
2117   VEX_W_0F380E_P_2,
2118   VEX_W_0F380F_P_2,
2119   VEX_W_0F3816_P_2,
2120   VEX_W_0F3817_P_2,
2121   VEX_W_0F3818_P_2,
2122   VEX_W_0F3819_P_2,
2123   VEX_W_0F381A_P_2_M_0,
2124   VEX_W_0F381C_P_2,
2125   VEX_W_0F381D_P_2,
2126   VEX_W_0F381E_P_2,
2127   VEX_W_0F3820_P_2,
2128   VEX_W_0F3821_P_2,
2129   VEX_W_0F3822_P_2,
2130   VEX_W_0F3823_P_2,
2131   VEX_W_0F3824_P_2,
2132   VEX_W_0F3825_P_2,
2133   VEX_W_0F3828_P_2,
2134   VEX_W_0F3829_P_2,
2135   VEX_W_0F382A_P_2_M_0,
2136   VEX_W_0F382B_P_2,
2137   VEX_W_0F382C_P_2_M_0,
2138   VEX_W_0F382D_P_2_M_0,
2139   VEX_W_0F382E_P_2_M_0,
2140   VEX_W_0F382F_P_2_M_0,
2141   VEX_W_0F3830_P_2,
2142   VEX_W_0F3831_P_2,
2143   VEX_W_0F3832_P_2,
2144   VEX_W_0F3833_P_2,
2145   VEX_W_0F3834_P_2,
2146   VEX_W_0F3835_P_2,
2147   VEX_W_0F3836_P_2,
2148   VEX_W_0F3837_P_2,
2149   VEX_W_0F3838_P_2,
2150   VEX_W_0F3839_P_2,
2151   VEX_W_0F383A_P_2,
2152   VEX_W_0F383B_P_2,
2153   VEX_W_0F383C_P_2,
2154   VEX_W_0F383D_P_2,
2155   VEX_W_0F383E_P_2,
2156   VEX_W_0F383F_P_2,
2157   VEX_W_0F3840_P_2,
2158   VEX_W_0F3841_P_2,
2159   VEX_W_0F3846_P_2,
2160   VEX_W_0F3858_P_2,
2161   VEX_W_0F3859_P_2,
2162   VEX_W_0F385A_P_2_M_0,
2163   VEX_W_0F3878_P_2,
2164   VEX_W_0F3879_P_2,
2165   VEX_W_0F38DB_P_2,
2166   VEX_W_0F38DC_P_2,
2167   VEX_W_0F38DD_P_2,
2168   VEX_W_0F38DE_P_2,
2169   VEX_W_0F38DF_P_2,
2170   VEX_W_0F3A00_P_2,
2171   VEX_W_0F3A01_P_2,
2172   VEX_W_0F3A02_P_2,
2173   VEX_W_0F3A04_P_2,
2174   VEX_W_0F3A05_P_2,
2175   VEX_W_0F3A06_P_2,
2176   VEX_W_0F3A08_P_2,
2177   VEX_W_0F3A09_P_2,
2178   VEX_W_0F3A0A_P_2,
2179   VEX_W_0F3A0B_P_2,
2180   VEX_W_0F3A0C_P_2,
2181   VEX_W_0F3A0D_P_2,
2182   VEX_W_0F3A0E_P_2,
2183   VEX_W_0F3A0F_P_2,
2184   VEX_W_0F3A14_P_2,
2185   VEX_W_0F3A15_P_2,
2186   VEX_W_0F3A18_P_2,
2187   VEX_W_0F3A19_P_2,
2188   VEX_W_0F3A20_P_2,
2189   VEX_W_0F3A21_P_2,
2190   VEX_W_0F3A30_P_2_LEN_0,
2191   VEX_W_0F3A31_P_2_LEN_0,
2192   VEX_W_0F3A32_P_2_LEN_0,
2193   VEX_W_0F3A33_P_2_LEN_0,
2194   VEX_W_0F3A38_P_2,
2195   VEX_W_0F3A39_P_2,
2196   VEX_W_0F3A40_P_2,
2197   VEX_W_0F3A41_P_2,
2198   VEX_W_0F3A42_P_2,
2199   VEX_W_0F3A44_P_2,
2200   VEX_W_0F3A46_P_2,
2201   VEX_W_0F3A48_P_2,
2202   VEX_W_0F3A49_P_2,
2203   VEX_W_0F3A4A_P_2,
2204   VEX_W_0F3A4B_P_2,
2205   VEX_W_0F3A4C_P_2,
2206   VEX_W_0F3A62_P_2,
2207   VEX_W_0F3A63_P_2,
2208   VEX_W_0F3ADF_P_2,
2209
2210   EVEX_W_0F10_P_0,
2211   EVEX_W_0F10_P_1_M_0,
2212   EVEX_W_0F10_P_1_M_1,
2213   EVEX_W_0F10_P_2,
2214   EVEX_W_0F10_P_3_M_0,
2215   EVEX_W_0F10_P_3_M_1,
2216   EVEX_W_0F11_P_0,
2217   EVEX_W_0F11_P_1_M_0,
2218   EVEX_W_0F11_P_1_M_1,
2219   EVEX_W_0F11_P_2,
2220   EVEX_W_0F11_P_3_M_0,
2221   EVEX_W_0F11_P_3_M_1,
2222   EVEX_W_0F12_P_0_M_0,
2223   EVEX_W_0F12_P_0_M_1,
2224   EVEX_W_0F12_P_1,
2225   EVEX_W_0F12_P_2,
2226   EVEX_W_0F12_P_3,
2227   EVEX_W_0F13_P_0,
2228   EVEX_W_0F13_P_2,
2229   EVEX_W_0F14_P_0,
2230   EVEX_W_0F14_P_2,
2231   EVEX_W_0F15_P_0,
2232   EVEX_W_0F15_P_2,
2233   EVEX_W_0F16_P_0_M_0,
2234   EVEX_W_0F16_P_0_M_1,
2235   EVEX_W_0F16_P_1,
2236   EVEX_W_0F16_P_2,
2237   EVEX_W_0F17_P_0,
2238   EVEX_W_0F17_P_2,
2239   EVEX_W_0F28_P_0,
2240   EVEX_W_0F28_P_2,
2241   EVEX_W_0F29_P_0,
2242   EVEX_W_0F29_P_2,
2243   EVEX_W_0F2A_P_1,
2244   EVEX_W_0F2A_P_3,
2245   EVEX_W_0F2B_P_0,
2246   EVEX_W_0F2B_P_2,
2247   EVEX_W_0F2E_P_0,
2248   EVEX_W_0F2E_P_2,
2249   EVEX_W_0F2F_P_0,
2250   EVEX_W_0F2F_P_2,
2251   EVEX_W_0F51_P_0,
2252   EVEX_W_0F51_P_1,
2253   EVEX_W_0F51_P_2,
2254   EVEX_W_0F51_P_3,
2255   EVEX_W_0F54_P_0,
2256   EVEX_W_0F54_P_2,
2257   EVEX_W_0F55_P_0,
2258   EVEX_W_0F55_P_2,
2259   EVEX_W_0F56_P_0,
2260   EVEX_W_0F56_P_2,
2261   EVEX_W_0F57_P_0,
2262   EVEX_W_0F57_P_2,
2263   EVEX_W_0F58_P_0,
2264   EVEX_W_0F58_P_1,
2265   EVEX_W_0F58_P_2,
2266   EVEX_W_0F58_P_3,
2267   EVEX_W_0F59_P_0,
2268   EVEX_W_0F59_P_1,
2269   EVEX_W_0F59_P_2,
2270   EVEX_W_0F59_P_3,
2271   EVEX_W_0F5A_P_0,
2272   EVEX_W_0F5A_P_1,
2273   EVEX_W_0F5A_P_2,
2274   EVEX_W_0F5A_P_3,
2275   EVEX_W_0F5B_P_0,
2276   EVEX_W_0F5B_P_1,
2277   EVEX_W_0F5B_P_2,
2278   EVEX_W_0F5C_P_0,
2279   EVEX_W_0F5C_P_1,
2280   EVEX_W_0F5C_P_2,
2281   EVEX_W_0F5C_P_3,
2282   EVEX_W_0F5D_P_0,
2283   EVEX_W_0F5D_P_1,
2284   EVEX_W_0F5D_P_2,
2285   EVEX_W_0F5D_P_3,
2286   EVEX_W_0F5E_P_0,
2287   EVEX_W_0F5E_P_1,
2288   EVEX_W_0F5E_P_2,
2289   EVEX_W_0F5E_P_3,
2290   EVEX_W_0F5F_P_0,
2291   EVEX_W_0F5F_P_1,
2292   EVEX_W_0F5F_P_2,
2293   EVEX_W_0F5F_P_3,
2294   EVEX_W_0F62_P_2,
2295   EVEX_W_0F66_P_2,
2296   EVEX_W_0F6A_P_2,
2297   EVEX_W_0F6B_P_2,
2298   EVEX_W_0F6C_P_2,
2299   EVEX_W_0F6D_P_2,
2300   EVEX_W_0F6E_P_2,
2301   EVEX_W_0F6F_P_1,
2302   EVEX_W_0F6F_P_2,
2303   EVEX_W_0F6F_P_3,
2304   EVEX_W_0F70_P_2,
2305   EVEX_W_0F72_R_2_P_2,
2306   EVEX_W_0F72_R_6_P_2,
2307   EVEX_W_0F73_R_2_P_2,
2308   EVEX_W_0F73_R_6_P_2,
2309   EVEX_W_0F76_P_2,
2310   EVEX_W_0F78_P_0,
2311   EVEX_W_0F78_P_2,
2312   EVEX_W_0F79_P_0,
2313   EVEX_W_0F79_P_2,
2314   EVEX_W_0F7A_P_1,
2315   EVEX_W_0F7A_P_2,
2316   EVEX_W_0F7A_P_3,
2317   EVEX_W_0F7B_P_1,
2318   EVEX_W_0F7B_P_2,
2319   EVEX_W_0F7B_P_3,
2320   EVEX_W_0F7E_P_1,
2321   EVEX_W_0F7E_P_2,
2322   EVEX_W_0F7F_P_1,
2323   EVEX_W_0F7F_P_2,
2324   EVEX_W_0F7F_P_3,
2325   EVEX_W_0FC2_P_0,
2326   EVEX_W_0FC2_P_1,
2327   EVEX_W_0FC2_P_2,
2328   EVEX_W_0FC2_P_3,
2329   EVEX_W_0FC6_P_0,
2330   EVEX_W_0FC6_P_2,
2331   EVEX_W_0FD2_P_2,
2332   EVEX_W_0FD3_P_2,
2333   EVEX_W_0FD4_P_2,
2334   EVEX_W_0FD6_P_2,
2335   EVEX_W_0FE6_P_1,
2336   EVEX_W_0FE6_P_2,
2337   EVEX_W_0FE6_P_3,
2338   EVEX_W_0FE7_P_2,
2339   EVEX_W_0FF2_P_2,
2340   EVEX_W_0FF3_P_2,
2341   EVEX_W_0FF4_P_2,
2342   EVEX_W_0FFA_P_2,
2343   EVEX_W_0FFB_P_2,
2344   EVEX_W_0FFE_P_2,
2345   EVEX_W_0F380C_P_2,
2346   EVEX_W_0F380D_P_2,
2347   EVEX_W_0F3810_P_1,
2348   EVEX_W_0F3810_P_2,
2349   EVEX_W_0F3811_P_1,
2350   EVEX_W_0F3811_P_2,
2351   EVEX_W_0F3812_P_1,
2352   EVEX_W_0F3812_P_2,
2353   EVEX_W_0F3813_P_1,
2354   EVEX_W_0F3813_P_2,
2355   EVEX_W_0F3814_P_1,
2356   EVEX_W_0F3815_P_1,
2357   EVEX_W_0F3818_P_2,
2358   EVEX_W_0F3819_P_2,
2359   EVEX_W_0F381A_P_2,
2360   EVEX_W_0F381B_P_2,
2361   EVEX_W_0F381E_P_2,
2362   EVEX_W_0F381F_P_2,
2363   EVEX_W_0F3820_P_1,
2364   EVEX_W_0F3821_P_1,
2365   EVEX_W_0F3822_P_1,
2366   EVEX_W_0F3823_P_1,
2367   EVEX_W_0F3824_P_1,
2368   EVEX_W_0F3825_P_1,
2369   EVEX_W_0F3825_P_2,
2370   EVEX_W_0F3826_P_1,
2371   EVEX_W_0F3826_P_2,
2372   EVEX_W_0F3828_P_1,
2373   EVEX_W_0F3828_P_2,
2374   EVEX_W_0F3829_P_1,
2375   EVEX_W_0F3829_P_2,
2376   EVEX_W_0F382A_P_1,
2377   EVEX_W_0F382A_P_2,
2378   EVEX_W_0F382B_P_2,
2379   EVEX_W_0F3830_P_1,
2380   EVEX_W_0F3831_P_1,
2381   EVEX_W_0F3832_P_1,
2382   EVEX_W_0F3833_P_1,
2383   EVEX_W_0F3834_P_1,
2384   EVEX_W_0F3835_P_1,
2385   EVEX_W_0F3835_P_2,
2386   EVEX_W_0F3837_P_2,
2387   EVEX_W_0F3838_P_1,
2388   EVEX_W_0F3839_P_1,
2389   EVEX_W_0F383A_P_1,
2390   EVEX_W_0F3840_P_2,
2391   EVEX_W_0F3855_P_2,
2392   EVEX_W_0F3858_P_2,
2393   EVEX_W_0F3859_P_2,
2394   EVEX_W_0F385A_P_2,
2395   EVEX_W_0F385B_P_2,
2396   EVEX_W_0F3866_P_2,
2397   EVEX_W_0F3875_P_2,
2398   EVEX_W_0F3878_P_2,
2399   EVEX_W_0F3879_P_2,
2400   EVEX_W_0F387A_P_2,
2401   EVEX_W_0F387B_P_2,
2402   EVEX_W_0F387D_P_2,
2403   EVEX_W_0F3883_P_2,
2404   EVEX_W_0F388D_P_2,
2405   EVEX_W_0F3891_P_2,
2406   EVEX_W_0F3893_P_2,
2407   EVEX_W_0F38A1_P_2,
2408   EVEX_W_0F38A3_P_2,
2409   EVEX_W_0F38C7_R_1_P_2,
2410   EVEX_W_0F38C7_R_2_P_2,
2411   EVEX_W_0F38C7_R_5_P_2,
2412   EVEX_W_0F38C7_R_6_P_2,
2413
2414   EVEX_W_0F3A00_P_2,
2415   EVEX_W_0F3A01_P_2,
2416   EVEX_W_0F3A04_P_2,
2417   EVEX_W_0F3A05_P_2,
2418   EVEX_W_0F3A08_P_2,
2419   EVEX_W_0F3A09_P_2,
2420   EVEX_W_0F3A0A_P_2,
2421   EVEX_W_0F3A0B_P_2,
2422   EVEX_W_0F3A16_P_2,
2423   EVEX_W_0F3A18_P_2,
2424   EVEX_W_0F3A19_P_2,
2425   EVEX_W_0F3A1A_P_2,
2426   EVEX_W_0F3A1B_P_2,
2427   EVEX_W_0F3A1D_P_2,
2428   EVEX_W_0F3A21_P_2,
2429   EVEX_W_0F3A22_P_2,
2430   EVEX_W_0F3A23_P_2,
2431   EVEX_W_0F3A38_P_2,
2432   EVEX_W_0F3A39_P_2,
2433   EVEX_W_0F3A3A_P_2,
2434   EVEX_W_0F3A3B_P_2,
2435   EVEX_W_0F3A3E_P_2,
2436   EVEX_W_0F3A3F_P_2,
2437   EVEX_W_0F3A42_P_2,
2438   EVEX_W_0F3A43_P_2,
2439   EVEX_W_0F3A50_P_2,
2440   EVEX_W_0F3A51_P_2,
2441   EVEX_W_0F3A56_P_2,
2442   EVEX_W_0F3A57_P_2,
2443   EVEX_W_0F3A66_P_2,
2444   EVEX_W_0F3A67_P_2
2445 };
2446
2447 typedef void (*op_rtn) (int bytemode, int sizeflag);
2448
2449 struct dis386 {
2450   const char *name;
2451   struct
2452     {
2453       op_rtn rtn;
2454       int bytemode;
2455     } op[MAX_OPERANDS];
2456   unsigned int prefix_requirement;
2457 };
2458
2459 /* Upper case letters in the instruction names here are macros.
2460    'A' => print 'b' if no register operands or suffix_always is true
2461    'B' => print 'b' if suffix_always is true
2462    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2463           size prefix
2464    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2465           suffix_always is true
2466    'E' => print 'e' if 32-bit form of jcxz
2467    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2468    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2469    'H' => print ",pt" or ",pn" branch hint
2470    'I' => honor following macro letter even in Intel mode (implemented only
2471           for some of the macro letters)
2472    'J' => print 'l'
2473    'K' => print 'd' or 'q' if rex prefix is present.
2474    'L' => print 'l' if suffix_always is true
2475    'M' => print 'r' if intel_mnemonic is false.
2476    'N' => print 'n' if instruction has no wait "prefix"
2477    'O' => print 'd' or 'o' (or 'q' in Intel mode)
2478    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2479           or suffix_always is true.  print 'q' if rex prefix is present.
2480    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2481           is true
2482    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2483    'S' => print 'w', 'l' or 'q' if suffix_always is true
2484    'T' => print 'q' in 64bit mode if instruction has no operand size
2485           prefix and behave as 'P' otherwise
2486    'U' => print 'q' in 64bit mode if instruction has no operand size
2487           prefix and behave as 'Q' otherwise
2488    'V' => print 'q' in 64bit mode if instruction has no operand size
2489           prefix and behave as 'S' otherwise
2490    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2491    'X' => print 's', 'd' depending on data16 prefix (for XMM)
2492    'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
2493           suffix_always is true.
2494    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2495    '!' => change condition from true to false or from false to true.
2496    '%' => add 1 upper case letter to the macro.
2497    '^' => print 'w' or 'l' depending on operand size prefix or
2498           suffix_always is true (lcall/ljmp).
2499    '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2500           on operand size prefix.
2501    '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2502           has no operand size prefix for AMD64 ISA, behave as 'P'
2503           otherwise
2504
2505    2 upper case letter macros:
2506    "XY" => print 'x' or 'y' if suffix_always is true or no register
2507            operands and no broadcast.
2508    "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2509            register operands and no broadcast.
2510    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2511    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2512            or suffix_always is true
2513    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2514    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2515    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2516    "LW" => print 'd', 'q' depending on the VEX.W bit
2517    "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2518            an operand size prefix, or suffix_always is true.  print
2519            'q' if rex prefix is present.
2520
2521    Many of the above letters print nothing in Intel mode.  See "putop"
2522    for the details.
2523
2524    Braces '{' and '}', and vertical bars '|', indicate alternative
2525    mnemonic strings for AT&T and Intel.  */
2526
2527 static const struct dis386 dis386[] = {
2528   /* 00 */
2529   { "addB",             { Ebh1, Gb }, 0 },
2530   { "addS",             { Evh1, Gv }, 0 },
2531   { "addB",             { Gb, EbS }, 0 },
2532   { "addS",             { Gv, EvS }, 0 },
2533   { "addB",             { AL, Ib }, 0 },
2534   { "addS",             { eAX, Iv }, 0 },
2535   { X86_64_TABLE (X86_64_06) },
2536   { X86_64_TABLE (X86_64_07) },
2537   /* 08 */
2538   { "orB",              { Ebh1, Gb }, 0 },
2539   { "orS",              { Evh1, Gv }, 0 },
2540   { "orB",              { Gb, EbS }, 0 },
2541   { "orS",              { Gv, EvS }, 0 },
2542   { "orB",              { AL, Ib }, 0 },
2543   { "orS",              { eAX, Iv }, 0 },
2544   { X86_64_TABLE (X86_64_0D) },
2545   { Bad_Opcode },       /* 0x0f extended opcode escape */
2546   /* 10 */
2547   { "adcB",             { Ebh1, Gb }, 0 },
2548   { "adcS",             { Evh1, Gv }, 0 },
2549   { "adcB",             { Gb, EbS }, 0 },
2550   { "adcS",             { Gv, EvS }, 0 },
2551   { "adcB",             { AL, Ib }, 0 },
2552   { "adcS",             { eAX, Iv }, 0 },
2553   { X86_64_TABLE (X86_64_16) },
2554   { X86_64_TABLE (X86_64_17) },
2555   /* 18 */
2556   { "sbbB",             { Ebh1, Gb }, 0 },
2557   { "sbbS",             { Evh1, Gv }, 0 },
2558   { "sbbB",             { Gb, EbS }, 0 },
2559   { "sbbS",             { Gv, EvS }, 0 },
2560   { "sbbB",             { AL, Ib }, 0 },
2561   { "sbbS",             { eAX, Iv }, 0 },
2562   { X86_64_TABLE (X86_64_1E) },
2563   { X86_64_TABLE (X86_64_1F) },
2564   /* 20 */
2565   { "andB",             { Ebh1, Gb }, 0 },
2566   { "andS",             { Evh1, Gv }, 0 },
2567   { "andB",             { Gb, EbS }, 0 },
2568   { "andS",             { Gv, EvS }, 0 },
2569   { "andB",             { AL, Ib }, 0 },
2570   { "andS",             { eAX, Iv }, 0 },
2571   { Bad_Opcode },       /* SEG ES prefix */
2572   { X86_64_TABLE (X86_64_27) },
2573   /* 28 */
2574   { "subB",             { Ebh1, Gb }, 0 },
2575   { "subS",             { Evh1, Gv }, 0 },
2576   { "subB",             { Gb, EbS }, 0 },
2577   { "subS",             { Gv, EvS }, 0 },
2578   { "subB",             { AL, Ib }, 0 },
2579   { "subS",             { eAX, Iv }, 0 },
2580   { Bad_Opcode },       /* SEG CS prefix */
2581   { X86_64_TABLE (X86_64_2F) },
2582   /* 30 */
2583   { "xorB",             { Ebh1, Gb }, 0 },
2584   { "xorS",             { Evh1, Gv }, 0 },
2585   { "xorB",             { Gb, EbS }, 0 },
2586   { "xorS",             { Gv, EvS }, 0 },
2587   { "xorB",             { AL, Ib }, 0 },
2588   { "xorS",             { eAX, Iv }, 0 },
2589   { Bad_Opcode },       /* SEG SS prefix */
2590   { X86_64_TABLE (X86_64_37) },
2591   /* 38 */
2592   { "cmpB",             { Eb, Gb }, 0 },
2593   { "cmpS",             { Ev, Gv }, 0 },
2594   { "cmpB",             { Gb, EbS }, 0 },
2595   { "cmpS",             { Gv, EvS }, 0 },
2596   { "cmpB",             { AL, Ib }, 0 },
2597   { "cmpS",             { eAX, Iv }, 0 },
2598   { Bad_Opcode },       /* SEG DS prefix */
2599   { X86_64_TABLE (X86_64_3F) },
2600   /* 40 */
2601   { "inc{S|}",          { RMeAX }, 0 },
2602   { "inc{S|}",          { RMeCX }, 0 },
2603   { "inc{S|}",          { RMeDX }, 0 },
2604   { "inc{S|}",          { RMeBX }, 0 },
2605   { "inc{S|}",          { RMeSP }, 0 },
2606   { "inc{S|}",          { RMeBP }, 0 },
2607   { "inc{S|}",          { RMeSI }, 0 },
2608   { "inc{S|}",          { RMeDI }, 0 },
2609   /* 48 */
2610   { "dec{S|}",          { RMeAX }, 0 },
2611   { "dec{S|}",          { RMeCX }, 0 },
2612   { "dec{S|}",          { RMeDX }, 0 },
2613   { "dec{S|}",          { RMeBX }, 0 },
2614   { "dec{S|}",          { RMeSP }, 0 },
2615   { "dec{S|}",          { RMeBP }, 0 },
2616   { "dec{S|}",          { RMeSI }, 0 },
2617   { "dec{S|}",          { RMeDI }, 0 },
2618   /* 50 */
2619   { "pushV",            { RMrAX }, 0 },
2620   { "pushV",            { RMrCX }, 0 },
2621   { "pushV",            { RMrDX }, 0 },
2622   { "pushV",            { RMrBX }, 0 },
2623   { "pushV",            { RMrSP }, 0 },
2624   { "pushV",            { RMrBP }, 0 },
2625   { "pushV",            { RMrSI }, 0 },
2626   { "pushV",            { RMrDI }, 0 },
2627   /* 58 */
2628   { "popV",             { RMrAX }, 0 },
2629   { "popV",             { RMrCX }, 0 },
2630   { "popV",             { RMrDX }, 0 },
2631   { "popV",             { RMrBX }, 0 },
2632   { "popV",             { RMrSP }, 0 },
2633   { "popV",             { RMrBP }, 0 },
2634   { "popV",             { RMrSI }, 0 },
2635   { "popV",             { RMrDI }, 0 },
2636   /* 60 */
2637   { X86_64_TABLE (X86_64_60) },
2638   { X86_64_TABLE (X86_64_61) },
2639   { X86_64_TABLE (X86_64_62) },
2640   { X86_64_TABLE (X86_64_63) },
2641   { Bad_Opcode },       /* seg fs */
2642   { Bad_Opcode },       /* seg gs */
2643   { Bad_Opcode },       /* op size prefix */
2644   { Bad_Opcode },       /* adr size prefix */
2645   /* 68 */
2646   { "pushT",            { sIv }, 0 },
2647   { "imulS",            { Gv, Ev, Iv }, 0 },
2648   { "pushT",            { sIbT }, 0 },
2649   { "imulS",            { Gv, Ev, sIb }, 0 },
2650   { "ins{b|}",          { Ybr, indirDX }, 0 },
2651   { X86_64_TABLE (X86_64_6D) },
2652   { "outs{b|}",         { indirDXr, Xb }, 0 },
2653   { X86_64_TABLE (X86_64_6F) },
2654   /* 70 */
2655   { "joH",              { Jb, BND, cond_jump_flag }, 0 },
2656   { "jnoH",             { Jb, BND, cond_jump_flag }, 0 },
2657   { "jbH",              { Jb, BND, cond_jump_flag }, 0 },
2658   { "jaeH",             { Jb, BND, cond_jump_flag }, 0 },
2659   { "jeH",              { Jb, BND, cond_jump_flag }, 0 },
2660   { "jneH",             { Jb, BND, cond_jump_flag }, 0 },
2661   { "jbeH",             { Jb, BND, cond_jump_flag }, 0 },
2662   { "jaH",              { Jb, BND, cond_jump_flag }, 0 },
2663   /* 78 */
2664   { "jsH",              { Jb, BND, cond_jump_flag }, 0 },
2665   { "jnsH",             { Jb, BND, cond_jump_flag }, 0 },
2666   { "jpH",              { Jb, BND, cond_jump_flag }, 0 },
2667   { "jnpH",             { Jb, BND, cond_jump_flag }, 0 },
2668   { "jlH",              { Jb, BND, cond_jump_flag }, 0 },
2669   { "jgeH",             { Jb, BND, cond_jump_flag }, 0 },
2670   { "jleH",             { Jb, BND, cond_jump_flag }, 0 },
2671   { "jgH",              { Jb, BND, cond_jump_flag }, 0 },
2672   /* 80 */
2673   { REG_TABLE (REG_80) },
2674   { REG_TABLE (REG_81) },
2675   { X86_64_TABLE (X86_64_82) },
2676   { REG_TABLE (REG_83) },
2677   { "testB",            { Eb, Gb }, 0 },
2678   { "testS",            { Ev, Gv }, 0 },
2679   { "xchgB",            { Ebh2, Gb }, 0 },
2680   { "xchgS",            { Evh2, Gv }, 0 },
2681   /* 88 */
2682   { "movB",             { Ebh3, Gb }, 0 },
2683   { "movS",             { Evh3, Gv }, 0 },
2684   { "movB",             { Gb, EbS }, 0 },
2685   { "movS",             { Gv, EvS }, 0 },
2686   { "movD",             { Sv, Sw }, 0 },
2687   { MOD_TABLE (MOD_8D) },
2688   { "movD",             { Sw, Sv }, 0 },
2689   { REG_TABLE (REG_8F) },
2690   /* 90 */
2691   { PREFIX_TABLE (PREFIX_90) },
2692   { "xchgS",            { RMeCX, eAX }, 0 },
2693   { "xchgS",            { RMeDX, eAX }, 0 },
2694   { "xchgS",            { RMeBX, eAX }, 0 },
2695   { "xchgS",            { RMeSP, eAX }, 0 },
2696   { "xchgS",            { RMeBP, eAX }, 0 },
2697   { "xchgS",            { RMeSI, eAX }, 0 },
2698   { "xchgS",            { RMeDI, eAX }, 0 },
2699   /* 98 */
2700   { "cW{t|}R",          { XX }, 0 },
2701   { "cR{t|}O",          { XX }, 0 },
2702   { X86_64_TABLE (X86_64_9A) },
2703   { Bad_Opcode },       /* fwait */
2704   { "pushfT",           { XX }, 0 },
2705   { "popfT",            { XX }, 0 },
2706   { "sahf",             { XX }, 0 },
2707   { "lahf",             { XX }, 0 },
2708   /* a0 */
2709   { "mov%LB",           { AL, Ob }, 0 },
2710   { "mov%LS",           { eAX, Ov }, 0 },
2711   { "mov%LB",           { Ob, AL }, 0 },
2712   { "mov%LS",           { Ov, eAX }, 0 },
2713   { "movs{b|}",         { Ybr, Xb }, 0 },
2714   { "movs{R|}",         { Yvr, Xv }, 0 },
2715   { "cmps{b|}",         { Xb, Yb }, 0 },
2716   { "cmps{R|}",         { Xv, Yv }, 0 },
2717   /* a8 */
2718   { "testB",            { AL, Ib }, 0 },
2719   { "testS",            { eAX, Iv }, 0 },
2720   { "stosB",            { Ybr, AL }, 0 },
2721   { "stosS",            { Yvr, eAX }, 0 },
2722   { "lodsB",            { ALr, Xb }, 0 },
2723   { "lodsS",            { eAXr, Xv }, 0 },
2724   { "scasB",            { AL, Yb }, 0 },
2725   { "scasS",            { eAX, Yv }, 0 },
2726   /* b0 */
2727   { "movB",             { RMAL, Ib }, 0 },
2728   { "movB",             { RMCL, Ib }, 0 },
2729   { "movB",             { RMDL, Ib }, 0 },
2730   { "movB",             { RMBL, Ib }, 0 },
2731   { "movB",             { RMAH, Ib }, 0 },
2732   { "movB",             { RMCH, Ib }, 0 },
2733   { "movB",             { RMDH, Ib }, 0 },
2734   { "movB",             { RMBH, Ib }, 0 },
2735   /* b8 */
2736   { "mov%LV",           { RMeAX, Iv64 }, 0 },
2737   { "mov%LV",           { RMeCX, Iv64 }, 0 },
2738   { "mov%LV",           { RMeDX, Iv64 }, 0 },
2739   { "mov%LV",           { RMeBX, Iv64 }, 0 },
2740   { "mov%LV",           { RMeSP, Iv64 }, 0 },
2741   { "mov%LV",           { RMeBP, Iv64 }, 0 },
2742   { "mov%LV",           { RMeSI, Iv64 }, 0 },
2743   { "mov%LV",           { RMeDI, Iv64 }, 0 },
2744   /* c0 */
2745   { REG_TABLE (REG_C0) },
2746   { REG_TABLE (REG_C1) },
2747   { "retT",             { Iw, BND }, 0 },
2748   { "retT",             { BND }, 0 },
2749   { X86_64_TABLE (X86_64_C4) },
2750   { X86_64_TABLE (X86_64_C5) },
2751   { REG_TABLE (REG_C6) },
2752   { REG_TABLE (REG_C7) },
2753   /* c8 */
2754   { "enterT",           { Iw, Ib }, 0 },
2755   { "leaveT",           { XX }, 0 },
2756   { "Jret{|f}P",        { Iw }, 0 },
2757   { "Jret{|f}P",        { XX }, 0 },
2758   { "int3",             { XX }, 0 },
2759   { "int",              { Ib }, 0 },
2760   { X86_64_TABLE (X86_64_CE) },
2761   { "iret%LP",          { XX }, 0 },
2762   /* d0 */
2763   { REG_TABLE (REG_D0) },
2764   { REG_TABLE (REG_D1) },
2765   { REG_TABLE (REG_D2) },
2766   { REG_TABLE (REG_D3) },
2767   { X86_64_TABLE (X86_64_D4) },
2768   { X86_64_TABLE (X86_64_D5) },
2769   { Bad_Opcode },
2770   { "xlat",             { DSBX }, 0 },
2771   /* d8 */
2772   { FLOAT },
2773   { FLOAT },
2774   { FLOAT },
2775   { FLOAT },
2776   { FLOAT },
2777   { FLOAT },
2778   { FLOAT },
2779   { FLOAT },
2780   /* e0 */
2781   { "loopneFH",         { Jb, XX, loop_jcxz_flag }, 0 },
2782   { "loopeFH",          { Jb, XX, loop_jcxz_flag }, 0 },
2783   { "loopFH",           { Jb, XX, loop_jcxz_flag }, 0 },
2784   { "jEcxzH",           { Jb, XX, loop_jcxz_flag }, 0 },
2785   { "inB",              { AL, Ib }, 0 },
2786   { "inG",              { zAX, Ib }, 0 },
2787   { "outB",             { Ib, AL }, 0 },
2788   { "outG",             { Ib, zAX }, 0 },
2789   /* e8 */
2790   { X86_64_TABLE (X86_64_E8) },
2791   { X86_64_TABLE (X86_64_E9) },
2792   { X86_64_TABLE (X86_64_EA) },
2793   { "jmp",              { Jb, BND }, 0 },
2794   { "inB",              { AL, indirDX }, 0 },
2795   { "inG",              { zAX, indirDX }, 0 },
2796   { "outB",             { indirDX, AL }, 0 },
2797   { "outG",             { indirDX, zAX }, 0 },
2798   /* f0 */
2799   { Bad_Opcode },       /* lock prefix */
2800   { "icebp",            { XX }, 0 },
2801   { Bad_Opcode },       /* repne */
2802   { Bad_Opcode },       /* repz */
2803   { "hlt",              { XX }, 0 },
2804   { "cmc",              { XX }, 0 },
2805   { REG_TABLE (REG_F6) },
2806   { REG_TABLE (REG_F7) },
2807   /* f8 */
2808   { "clc",              { XX }, 0 },
2809   { "stc",              { XX }, 0 },
2810   { "cli",              { XX }, 0 },
2811   { "sti",              { XX }, 0 },
2812   { "cld",              { XX }, 0 },
2813   { "std",              { XX }, 0 },
2814   { REG_TABLE (REG_FE) },
2815   { REG_TABLE (REG_FF) },
2816 };
2817
2818 static const struct dis386 dis386_twobyte[] = {
2819   /* 00 */
2820   { REG_TABLE (REG_0F00 ) },
2821   { REG_TABLE (REG_0F01 ) },
2822   { "larS",             { Gv, Ew }, 0 },
2823   { "lslS",             { Gv, Ew }, 0 },
2824   { Bad_Opcode },
2825   { "syscall",          { XX }, 0 },
2826   { "clts",             { XX }, 0 },
2827   { "sysret%LP",                { XX }, 0 },
2828   /* 08 */
2829   { "invd",             { XX }, 0 },
2830   { "wbinvd",           { XX }, 0 },
2831   { Bad_Opcode },
2832   { "ud2",              { XX }, 0 },
2833   { Bad_Opcode },
2834   { REG_TABLE (REG_0F0D) },
2835   { "femms",            { XX }, 0 },
2836   { "",                 { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix.  */
2837   /* 10 */
2838   { PREFIX_TABLE (PREFIX_0F10) },
2839   { PREFIX_TABLE (PREFIX_0F11) },
2840   { PREFIX_TABLE (PREFIX_0F12) },
2841   { MOD_TABLE (MOD_0F13) },
2842   { "unpcklpX",         { XM, EXx }, PREFIX_OPCODE },
2843   { "unpckhpX",         { XM, EXx }, PREFIX_OPCODE },
2844   { PREFIX_TABLE (PREFIX_0F16) },
2845   { MOD_TABLE (MOD_0F17) },
2846   /* 18 */
2847   { REG_TABLE (REG_0F18) },
2848   { "nopQ",             { Ev }, 0 },
2849   { PREFIX_TABLE (PREFIX_0F1A) },
2850   { PREFIX_TABLE (PREFIX_0F1B) },
2851   { "nopQ",             { Ev }, 0 },
2852   { "nopQ",             { Ev }, 0 },
2853   { PREFIX_TABLE (PREFIX_0F1E) },
2854   { "nopQ",             { Ev }, 0 },
2855   /* 20 */
2856   { "movZ",             { Rm, Cm }, 0 },
2857   { "movZ",             { Rm, Dm }, 0 },
2858   { "movZ",             { Cm, Rm }, 0 },
2859   { "movZ",             { Dm, Rm }, 0 },
2860   { MOD_TABLE (MOD_0F24) },
2861   { Bad_Opcode },
2862   { MOD_TABLE (MOD_0F26) },
2863   { Bad_Opcode },
2864   /* 28 */
2865   { "movapX",           { XM, EXx }, PREFIX_OPCODE },
2866   { "movapX",           { EXxS, XM }, PREFIX_OPCODE },
2867   { PREFIX_TABLE (PREFIX_0F2A) },
2868   { PREFIX_TABLE (PREFIX_0F2B) },
2869   { PREFIX_TABLE (PREFIX_0F2C) },
2870   { PREFIX_TABLE (PREFIX_0F2D) },
2871   { PREFIX_TABLE (PREFIX_0F2E) },
2872   { PREFIX_TABLE (PREFIX_0F2F) },
2873   /* 30 */
2874   { "wrmsr",            { XX }, 0 },
2875   { "rdtsc",            { XX }, 0 },
2876   { "rdmsr",            { XX }, 0 },
2877   { "rdpmc",            { XX }, 0 },
2878   { "sysenter",         { XX }, 0 },
2879   { "sysexit",          { XX }, 0 },
2880   { Bad_Opcode },
2881   { "getsec",           { XX }, 0 },
2882   /* 38 */
2883   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2884   { Bad_Opcode },
2885   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2886   { Bad_Opcode },
2887   { Bad_Opcode },
2888   { Bad_Opcode },
2889   { Bad_Opcode },
2890   { Bad_Opcode },
2891   /* 40 */
2892   { "cmovoS",           { Gv, Ev }, 0 },
2893   { "cmovnoS",          { Gv, Ev }, 0 },
2894   { "cmovbS",           { Gv, Ev }, 0 },
2895   { "cmovaeS",          { Gv, Ev }, 0 },
2896   { "cmoveS",           { Gv, Ev }, 0 },
2897   { "cmovneS",          { Gv, Ev }, 0 },
2898   { "cmovbeS",          { Gv, Ev }, 0 },
2899   { "cmovaS",           { Gv, Ev }, 0 },
2900   /* 48 */
2901   { "cmovsS",           { Gv, Ev }, 0 },
2902   { "cmovnsS",          { Gv, Ev }, 0 },
2903   { "cmovpS",           { Gv, Ev }, 0 },
2904   { "cmovnpS",          { Gv, Ev }, 0 },
2905   { "cmovlS",           { Gv, Ev }, 0 },
2906   { "cmovgeS",          { Gv, Ev }, 0 },
2907   { "cmovleS",          { Gv, Ev }, 0 },
2908   { "cmovgS",           { Gv, Ev }, 0 },
2909   /* 50 */
2910   { MOD_TABLE (MOD_0F51) },
2911   { PREFIX_TABLE (PREFIX_0F51) },
2912   { PREFIX_TABLE (PREFIX_0F52) },
2913   { PREFIX_TABLE (PREFIX_0F53) },
2914   { "andpX",            { XM, EXx }, PREFIX_OPCODE },
2915   { "andnpX",           { XM, EXx }, PREFIX_OPCODE },
2916   { "orpX",             { XM, EXx }, PREFIX_OPCODE },
2917   { "xorpX",            { XM, EXx }, PREFIX_OPCODE },
2918   /* 58 */
2919   { PREFIX_TABLE (PREFIX_0F58) },
2920   { PREFIX_TABLE (PREFIX_0F59) },
2921   { PREFIX_TABLE (PREFIX_0F5A) },
2922   { PREFIX_TABLE (PREFIX_0F5B) },
2923   { PREFIX_TABLE (PREFIX_0F5C) },
2924   { PREFIX_TABLE (PREFIX_0F5D) },
2925   { PREFIX_TABLE (PREFIX_0F5E) },
2926   { PREFIX_TABLE (PREFIX_0F5F) },
2927   /* 60 */
2928   { PREFIX_TABLE (PREFIX_0F60) },
2929   { PREFIX_TABLE (PREFIX_0F61) },
2930   { PREFIX_TABLE (PREFIX_0F62) },
2931   { "packsswb",         { MX, EM }, PREFIX_OPCODE },
2932   { "pcmpgtb",          { MX, EM }, PREFIX_OPCODE },
2933   { "pcmpgtw",          { MX, EM }, PREFIX_OPCODE },
2934   { "pcmpgtd",          { MX, EM }, PREFIX_OPCODE },
2935   { "packuswb",         { MX, EM }, PREFIX_OPCODE },
2936   /* 68 */
2937   { "punpckhbw",        { MX, EM }, PREFIX_OPCODE },
2938   { "punpckhwd",        { MX, EM }, PREFIX_OPCODE },
2939   { "punpckhdq",        { MX, EM }, PREFIX_OPCODE },
2940   { "packssdw",         { MX, EM }, PREFIX_OPCODE },
2941   { PREFIX_TABLE (PREFIX_0F6C) },
2942   { PREFIX_TABLE (PREFIX_0F6D) },
2943   { "movK",             { MX, Edq }, PREFIX_OPCODE },
2944   { PREFIX_TABLE (PREFIX_0F6F) },
2945   /* 70 */
2946   { PREFIX_TABLE (PREFIX_0F70) },
2947   { REG_TABLE (REG_0F71) },
2948   { REG_TABLE (REG_0F72) },
2949   { REG_TABLE (REG_0F73) },
2950   { "pcmpeqb",          { MX, EM }, PREFIX_OPCODE },
2951   { "pcmpeqw",          { MX, EM }, PREFIX_OPCODE },
2952   { "pcmpeqd",          { MX, EM }, PREFIX_OPCODE },
2953   { "emms",             { XX }, PREFIX_OPCODE },
2954   /* 78 */
2955   { PREFIX_TABLE (PREFIX_0F78) },
2956   { PREFIX_TABLE (PREFIX_0F79) },
2957   { Bad_Opcode },
2958   { Bad_Opcode },
2959   { PREFIX_TABLE (PREFIX_0F7C) },
2960   { PREFIX_TABLE (PREFIX_0F7D) },
2961   { PREFIX_TABLE (PREFIX_0F7E) },
2962   { PREFIX_TABLE (PREFIX_0F7F) },
2963   /* 80 */
2964   { "joH",              { Jv, BND, cond_jump_flag }, 0 },
2965   { "jnoH",             { Jv, BND, cond_jump_flag }, 0 },
2966   { "jbH",              { Jv, BND, cond_jump_flag }, 0 },
2967   { "jaeH",             { Jv, BND, cond_jump_flag }, 0 },
2968   { "jeH",              { Jv, BND, cond_jump_flag }, 0 },
2969   { "jneH",             { Jv, BND, cond_jump_flag }, 0 },
2970   { "jbeH",             { Jv, BND, cond_jump_flag }, 0 },
2971   { "jaH",              { Jv, BND, cond_jump_flag }, 0 },
2972   /* 88 */
2973   { "jsH",              { Jv, BND, cond_jump_flag }, 0 },
2974   { "jnsH",             { Jv, BND, cond_jump_flag }, 0 },
2975   { "jpH",              { Jv, BND, cond_jump_flag }, 0 },
2976   { "jnpH",             { Jv, BND, cond_jump_flag }, 0 },
2977   { "jlH",              { Jv, BND, cond_jump_flag }, 0 },
2978   { "jgeH",             { Jv, BND, cond_jump_flag }, 0 },
2979   { "jleH",             { Jv, BND, cond_jump_flag }, 0 },
2980   { "jgH",              { Jv, BND, cond_jump_flag }, 0 },
2981   /* 90 */
2982   { "seto",             { Eb }, 0 },
2983   { "setno",            { Eb }, 0 },
2984   { "setb",             { Eb }, 0 },
2985   { "setae",            { Eb }, 0 },
2986   { "sete",             { Eb }, 0 },
2987   { "setne",            { Eb }, 0 },
2988   { "setbe",            { Eb }, 0 },
2989   { "seta",             { Eb }, 0 },
2990   /* 98 */
2991   { "sets",             { Eb }, 0 },
2992   { "setns",            { Eb }, 0 },
2993   { "setp",             { Eb }, 0 },
2994   { "setnp",            { Eb }, 0 },
2995   { "setl",             { Eb }, 0 },
2996   { "setge",            { Eb }, 0 },
2997   { "setle",            { Eb }, 0 },
2998   { "setg",             { Eb }, 0 },
2999   /* a0 */
3000   { "pushT",            { fs }, 0 },
3001   { "popT",             { fs }, 0 },
3002   { "cpuid",            { XX }, 0 },
3003   { "btS",              { Ev, Gv }, 0 },
3004   { "shldS",            { Ev, Gv, Ib }, 0 },
3005   { "shldS",            { Ev, Gv, CL }, 0 },
3006   { REG_TABLE (REG_0FA6) },
3007   { REG_TABLE (REG_0FA7) },
3008   /* a8 */
3009   { "pushT",            { gs }, 0 },
3010   { "popT",             { gs }, 0 },
3011   { "rsm",              { XX }, 0 },
3012   { "btsS",             { Evh1, Gv }, 0 },
3013   { "shrdS",            { Ev, Gv, Ib }, 0 },
3014   { "shrdS",            { Ev, Gv, CL }, 0 },
3015   { REG_TABLE (REG_0FAE) },
3016   { "imulS",            { Gv, Ev }, 0 },
3017   /* b0 */
3018   { "cmpxchgB",         { Ebh1, Gb }, 0 },
3019   { "cmpxchgS",         { Evh1, Gv }, 0 },
3020   { MOD_TABLE (MOD_0FB2) },
3021   { "btrS",             { Evh1, Gv }, 0 },
3022   { MOD_TABLE (MOD_0FB4) },
3023   { MOD_TABLE (MOD_0FB5) },
3024   { "movz{bR|x}",       { Gv, Eb }, 0 },
3025   { "movz{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
3026   /* b8 */
3027   { PREFIX_TABLE (PREFIX_0FB8) },
3028   { "ud1",              { XX }, 0 },
3029   { REG_TABLE (REG_0FBA) },
3030   { "btcS",             { Evh1, Gv }, 0 },
3031   { PREFIX_TABLE (PREFIX_0FBC) },
3032   { PREFIX_TABLE (PREFIX_0FBD) },
3033   { "movs{bR|x}",       { Gv, Eb }, 0 },
3034   { "movs{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
3035   /* c0 */
3036   { "xaddB",            { Ebh1, Gb }, 0 },
3037   { "xaddS",            { Evh1, Gv }, 0 },
3038   { PREFIX_TABLE (PREFIX_0FC2) },
3039   { MOD_TABLE (MOD_0FC3) },
3040   { "pinsrw",           { MX, Edqw, Ib }, PREFIX_OPCODE },
3041   { "pextrw",           { Gdq, MS, Ib }, PREFIX_OPCODE },
3042   { "shufpX",           { XM, EXx, Ib }, PREFIX_OPCODE },
3043   { REG_TABLE (REG_0FC7) },
3044   /* c8 */
3045   { "bswap",            { RMeAX }, 0 },
3046   { "bswap",            { RMeCX }, 0 },
3047   { "bswap",            { RMeDX }, 0 },
3048   { "bswap",            { RMeBX }, 0 },
3049   { "bswap",            { RMeSP }, 0 },
3050   { "bswap",            { RMeBP }, 0 },
3051   { "bswap",            { RMeSI }, 0 },
3052   { "bswap",            { RMeDI }, 0 },
3053   /* d0 */
3054   { PREFIX_TABLE (PREFIX_0FD0) },
3055   { "psrlw",            { MX, EM }, PREFIX_OPCODE },
3056   { "psrld",            { MX, EM }, PREFIX_OPCODE },
3057   { "psrlq",            { MX, EM }, PREFIX_OPCODE },
3058   { "paddq",            { MX, EM }, PREFIX_OPCODE },
3059   { "pmullw",           { MX, EM }, PREFIX_OPCODE },
3060   { PREFIX_TABLE (PREFIX_0FD6) },
3061   { MOD_TABLE (MOD_0FD7) },
3062   /* d8 */
3063   { "psubusb",          { MX, EM }, PREFIX_OPCODE },
3064   { "psubusw",          { MX, EM }, PREFIX_OPCODE },
3065   { "pminub",           { MX, EM }, PREFIX_OPCODE },
3066   { "pand",             { MX, EM }, PREFIX_OPCODE },
3067   { "paddusb",          { MX, EM }, PREFIX_OPCODE },
3068   { "paddusw",          { MX, EM }, PREFIX_OPCODE },
3069   { "pmaxub",           { MX, EM }, PREFIX_OPCODE },
3070   { "pandn",            { MX, EM }, PREFIX_OPCODE },
3071   /* e0 */
3072   { "pavgb",            { MX, EM }, PREFIX_OPCODE },
3073   { "psraw",            { MX, EM }, PREFIX_OPCODE },
3074   { "psrad",            { MX, EM }, PREFIX_OPCODE },
3075   { "pavgw",            { MX, EM }, PREFIX_OPCODE },
3076   { "pmulhuw",          { MX, EM }, PREFIX_OPCODE },
3077   { "pmulhw",           { MX, EM }, PREFIX_OPCODE },
3078   { PREFIX_TABLE (PREFIX_0FE6) },
3079   { PREFIX_TABLE (PREFIX_0FE7) },
3080   /* e8 */
3081   { "psubsb",           { MX, EM }, PREFIX_OPCODE },
3082   { "psubsw",           { MX, EM }, PREFIX_OPCODE },
3083   { "pminsw",           { MX, EM }, PREFIX_OPCODE },
3084   { "por",              { MX, EM }, PREFIX_OPCODE },
3085   { "paddsb",           { MX, EM }, PREFIX_OPCODE },
3086   { "paddsw",           { MX, EM }, PREFIX_OPCODE },
3087   { "pmaxsw",           { MX, EM }, PREFIX_OPCODE },
3088   { "pxor",             { MX, EM }, PREFIX_OPCODE },
3089   /* f0 */
3090   { PREFIX_TABLE (PREFIX_0FF0) },
3091   { "psllw",            { MX, EM }, PREFIX_OPCODE },
3092   { "pslld",            { MX, EM }, PREFIX_OPCODE },
3093   { "psllq",            { MX, EM }, PREFIX_OPCODE },
3094   { "pmuludq",          { MX, EM }, PREFIX_OPCODE },
3095   { "pmaddwd",          { MX, EM }, PREFIX_OPCODE },
3096   { "psadbw",           { MX, EM }, PREFIX_OPCODE },
3097   { PREFIX_TABLE (PREFIX_0FF7) },
3098   /* f8 */
3099   { "psubb",            { MX, EM }, PREFIX_OPCODE },
3100   { "psubw",            { MX, EM }, PREFIX_OPCODE },
3101   { "psubd",            { MX, EM }, PREFIX_OPCODE },
3102   { "psubq",            { MX, EM }, PREFIX_OPCODE },
3103   { "paddb",            { MX, EM }, PREFIX_OPCODE },
3104   { "paddw",            { MX, EM }, PREFIX_OPCODE },
3105   { "paddd",            { MX, EM }, PREFIX_OPCODE },
3106   { Bad_Opcode },
3107 };
3108
3109 static const unsigned char onebyte_has_modrm[256] = {
3110   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3111   /*       -------------------------------        */
3112   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
3113   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
3114   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
3115   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
3116   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
3117   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
3118   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
3119   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
3120   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
3121   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
3122   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
3123   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
3124   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
3125   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
3126   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
3127   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
3128   /*       -------------------------------        */
3129   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3130 };
3131
3132 static const unsigned char twobyte_has_modrm[256] = {
3133   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3134   /*       -------------------------------        */
3135   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
3136   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
3137   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
3138   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
3139   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
3140   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
3141   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
3142   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
3143   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
3144   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
3145   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
3146   /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
3147   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
3148   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
3149   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
3150   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0  /* ff */
3151   /*       -------------------------------        */
3152   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3153 };
3154
3155 static char obuf[100];
3156 static char *obufp;
3157 static char *mnemonicendp;
3158 static char scratchbuf[100];
3159 static unsigned char *start_codep;
3160 static unsigned char *insn_codep;
3161 static unsigned char *codep;
3162 static unsigned char *end_codep;
3163 static int last_lock_prefix;
3164 static int last_repz_prefix;
3165 static int last_repnz_prefix;
3166 static int last_data_prefix;
3167 static int last_addr_prefix;
3168 static int last_rex_prefix;
3169 static int last_seg_prefix;
3170 static int fwait_prefix;
3171 /* The active segment register prefix.  */
3172 static int active_seg_prefix;
3173 #define MAX_CODE_LENGTH 15
3174 /* We can up to 14 prefixes since the maximum instruction length is
3175    15bytes.  */
3176 static int all_prefixes[MAX_CODE_LENGTH - 1];
3177 static disassemble_info *the_info;
3178 static struct
3179   {
3180     int mod;
3181     int reg;
3182     int rm;
3183   }
3184 modrm;
3185 static unsigned char need_modrm;
3186 static struct
3187   {
3188     int scale;
3189     int index;
3190     int base;
3191   }
3192 sib;
3193 static struct
3194   {
3195     int register_specifier;
3196     int length;
3197     int prefix;
3198     int w;
3199     int evex;
3200     int r;
3201     int v;
3202     int mask_register_specifier;
3203     int zeroing;
3204     int ll;
3205     int b;
3206   }
3207 vex;
3208 static unsigned char need_vex;
3209 static unsigned char need_vex_reg;
3210 static unsigned char vex_w_done;
3211
3212 struct op
3213   {
3214     const char *name;
3215     unsigned int len;
3216   };
3217
3218 /* If we are accessing mod/rm/reg without need_modrm set, then the
3219    values are stale.  Hitting this abort likely indicates that you
3220    need to update onebyte_has_modrm or twobyte_has_modrm.  */
3221 #define MODRM_CHECK  if (!need_modrm) abort ()
3222
3223 static const char **names64;
3224 static const char **names32;
3225 static const char **names16;
3226 static const char **names8;
3227 static const char **names8rex;
3228 static const char **names_seg;
3229 static const char *index64;
3230 static const char *index32;
3231 static const char **index16;
3232 static const char **names_bnd;
3233
3234 static const char *intel_names64[] = {
3235   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3236   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3237 };
3238 static const char *intel_names32[] = {
3239   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3240   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3241 };
3242 static const char *intel_names16[] = {
3243   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3244   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3245 };
3246 static const char *intel_names8[] = {
3247   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3248 };
3249 static const char *intel_names8rex[] = {
3250   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3251   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3252 };
3253 static const char *intel_names_seg[] = {
3254   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3255 };
3256 static const char *intel_index64 = "riz";
3257 static const char *intel_index32 = "eiz";
3258 static const char *intel_index16[] = {
3259   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3260 };
3261
3262 static const char *att_names64[] = {
3263   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3264   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3265 };
3266 static const char *att_names32[] = {
3267   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3268   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3269 };
3270 static const char *att_names16[] = {
3271   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3272   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3273 };
3274 static const char *att_names8[] = {
3275   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3276 };
3277 static const char *att_names8rex[] = {
3278   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3279   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3280 };
3281 static const char *att_names_seg[] = {
3282   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3283 };
3284 static const char *att_index64 = "%riz";
3285 static const char *att_index32 = "%eiz";
3286 static const char *att_index16[] = {
3287   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3288 };
3289
3290 static const char **names_mm;
3291 static const char *intel_names_mm[] = {
3292   "mm0", "mm1", "mm2", "mm3",
3293   "mm4", "mm5", "mm6", "mm7"
3294 };
3295 static const char *att_names_mm[] = {
3296   "%mm0", "%mm1", "%mm2", "%mm3",
3297   "%mm4", "%mm5", "%mm6", "%mm7"
3298 };
3299
3300 static const char *intel_names_bnd[] = {
3301   "bnd0", "bnd1", "bnd2", "bnd3"
3302 };
3303
3304 static const char *att_names_bnd[] = {
3305   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3306 };
3307
3308 static const char **names_xmm;
3309 static const char *intel_names_xmm[] = {
3310   "xmm0", "xmm1", "xmm2", "xmm3",
3311   "xmm4", "xmm5", "xmm6", "xmm7",
3312   "xmm8", "xmm9", "xmm10", "xmm11",
3313   "xmm12", "xmm13", "xmm14", "xmm15",
3314   "xmm16", "xmm17", "xmm18", "xmm19",
3315   "xmm20", "xmm21", "xmm22", "xmm23",
3316   "xmm24", "xmm25", "xmm26", "xmm27",
3317   "xmm28", "xmm29", "xmm30", "xmm31"
3318 };
3319 static const char *att_names_xmm[] = {
3320   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3321   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3322   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3323   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3324   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3325   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3326   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3327   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3328 };
3329
3330 static const char **names_ymm;
3331 static const char *intel_names_ymm[] = {
3332   "ymm0", "ymm1", "ymm2", "ymm3",
3333   "ymm4", "ymm5", "ymm6", "ymm7",
3334   "ymm8", "ymm9", "ymm10", "ymm11",
3335   "ymm12", "ymm13", "ymm14", "ymm15",
3336   "ymm16", "ymm17", "ymm18", "ymm19",
3337   "ymm20", "ymm21", "ymm22", "ymm23",
3338   "ymm24", "ymm25", "ymm26", "ymm27",
3339   "ymm28", "ymm29", "ymm30", "ymm31"
3340 };
3341 static const char *att_names_ymm[] = {
3342   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3343   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3344   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3345   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3346   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3347   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3348   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3349   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3350 };
3351
3352 static const char **names_zmm;
3353 static const char *intel_names_zmm[] = {
3354   "zmm0", "zmm1", "zmm2", "zmm3",
3355   "zmm4", "zmm5", "zmm6", "zmm7",
3356   "zmm8", "zmm9", "zmm10", "zmm11",
3357   "zmm12", "zmm13", "zmm14", "zmm15",
3358   "zmm16", "zmm17", "zmm18", "zmm19",
3359   "zmm20", "zmm21", "zmm22", "zmm23",
3360   "zmm24", "zmm25", "zmm26", "zmm27",
3361   "zmm28", "zmm29", "zmm30", "zmm31"
3362 };
3363 static const char *att_names_zmm[] = {
3364   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3365   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3366   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3367   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3368   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3369   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3370   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3371   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3372 };
3373
3374 static const char **names_mask;
3375 static const char *intel_names_mask[] = {
3376   "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3377 };
3378 static const char *att_names_mask[] = {
3379   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3380 };
3381
3382 static const char *names_rounding[] =
3383 {
3384   "{rn-sae}",
3385   "{rd-sae}",
3386   "{ru-sae}",
3387   "{rz-sae}"
3388 };
3389
3390 static const struct dis386 reg_table[][8] = {
3391   /* REG_80 */
3392   {
3393     { "addA",   { Ebh1, Ib }, 0 },
3394     { "orA",    { Ebh1, Ib }, 0 },
3395     { "adcA",   { Ebh1, Ib }, 0 },
3396     { "sbbA",   { Ebh1, Ib }, 0 },
3397     { "andA",   { Ebh1, Ib }, 0 },
3398     { "subA",   { Ebh1, Ib }, 0 },
3399     { "xorA",   { Ebh1, Ib }, 0 },
3400     { "cmpA",   { Eb, Ib }, 0 },
3401   },
3402   /* REG_81 */
3403   {
3404     { "addQ",   { Evh1, Iv }, 0 },
3405     { "orQ",    { Evh1, Iv }, 0 },
3406     { "adcQ",   { Evh1, Iv }, 0 },
3407     { "sbbQ",   { Evh1, Iv }, 0 },
3408     { "andQ",   { Evh1, Iv }, 0 },
3409     { "subQ",   { Evh1, Iv }, 0 },
3410     { "xorQ",   { Evh1, Iv }, 0 },
3411     { "cmpQ",   { Ev, Iv }, 0 },
3412   },
3413   /* REG_83 */
3414   {
3415     { "addQ",   { Evh1, sIb }, 0 },
3416     { "orQ",    { Evh1, sIb }, 0 },
3417     { "adcQ",   { Evh1, sIb }, 0 },
3418     { "sbbQ",   { Evh1, sIb }, 0 },
3419     { "andQ",   { Evh1, sIb }, 0 },
3420     { "subQ",   { Evh1, sIb }, 0 },
3421     { "xorQ",   { Evh1, sIb }, 0 },
3422     { "cmpQ",   { Ev, sIb }, 0 },
3423   },
3424   /* REG_8F */
3425   {
3426     { "popU",   { stackEv }, 0 },
3427     { XOP_8F_TABLE (XOP_09) },
3428     { Bad_Opcode },
3429     { Bad_Opcode },
3430     { Bad_Opcode },
3431     { XOP_8F_TABLE (XOP_09) },
3432   },
3433   /* REG_C0 */
3434   {
3435     { "rolA",   { Eb, Ib }, 0 },
3436     { "rorA",   { Eb, Ib }, 0 },
3437     { "rclA",   { Eb, Ib }, 0 },
3438     { "rcrA",   { Eb, Ib }, 0 },
3439     { "shlA",   { Eb, Ib }, 0 },
3440     { "shrA",   { Eb, Ib }, 0 },
3441     { Bad_Opcode },
3442     { "sarA",   { Eb, Ib }, 0 },
3443   },
3444   /* REG_C1 */
3445   {
3446     { "rolQ",   { Ev, Ib }, 0 },
3447     { "rorQ",   { Ev, Ib }, 0 },
3448     { "rclQ",   { Ev, Ib }, 0 },
3449     { "rcrQ",   { Ev, Ib }, 0 },
3450     { "shlQ",   { Ev, Ib }, 0 },
3451     { "shrQ",   { Ev, Ib }, 0 },
3452     { Bad_Opcode },
3453     { "sarQ",   { Ev, Ib }, 0 },
3454   },
3455   /* REG_C6 */
3456   {
3457     { "movA",   { Ebh3, Ib }, 0 },
3458     { Bad_Opcode },
3459     { Bad_Opcode },
3460     { Bad_Opcode },
3461     { Bad_Opcode },
3462     { Bad_Opcode },
3463     { Bad_Opcode },
3464     { MOD_TABLE (MOD_C6_REG_7) },
3465   },
3466   /* REG_C7 */
3467   {
3468     { "movQ",   { Evh3, Iv }, 0 },
3469     { Bad_Opcode },
3470     { Bad_Opcode },
3471     { Bad_Opcode },
3472     { Bad_Opcode },
3473     { Bad_Opcode },
3474     { Bad_Opcode },
3475     { MOD_TABLE (MOD_C7_REG_7) },
3476   },
3477   /* REG_D0 */
3478   {
3479     { "rolA",   { Eb, I1 }, 0 },
3480     { "rorA",   { Eb, I1 }, 0 },
3481     { "rclA",   { Eb, I1 }, 0 },
3482     { "rcrA",   { Eb, I1 }, 0 },
3483     { "shlA",   { Eb, I1 }, 0 },
3484     { "shrA",   { Eb, I1 }, 0 },
3485     { Bad_Opcode },
3486     { "sarA",   { Eb, I1 }, 0 },
3487   },
3488   /* REG_D1 */
3489   {
3490     { "rolQ",   { Ev, I1 }, 0 },
3491     { "rorQ",   { Ev, I1 }, 0 },
3492     { "rclQ",   { Ev, I1 }, 0 },
3493     { "rcrQ",   { Ev, I1 }, 0 },
3494     { "shlQ",   { Ev, I1 }, 0 },
3495     { "shrQ",   { Ev, I1 }, 0 },
3496     { Bad_Opcode },
3497     { "sarQ",   { Ev, I1 }, 0 },
3498   },
3499   /* REG_D2 */
3500   {
3501     { "rolA",   { Eb, CL }, 0 },
3502     { "rorA",   { Eb, CL }, 0 },
3503     { "rclA",   { Eb, CL }, 0 },
3504     { "rcrA",   { Eb, CL }, 0 },
3505     { "shlA",   { Eb, CL }, 0 },
3506     { "shrA",   { Eb, CL }, 0 },
3507     { Bad_Opcode },
3508     { "sarA",   { Eb, CL }, 0 },
3509   },
3510   /* REG_D3 */
3511   {
3512     { "rolQ",   { Ev, CL }, 0 },
3513     { "rorQ",   { Ev, CL }, 0 },
3514     { "rclQ",   { Ev, CL }, 0 },
3515     { "rcrQ",   { Ev, CL }, 0 },
3516     { "shlQ",   { Ev, CL }, 0 },
3517     { "shrQ",   { Ev, CL }, 0 },
3518     { Bad_Opcode },
3519     { "sarQ",   { Ev, CL }, 0 },
3520   },
3521   /* REG_F6 */
3522   {
3523     { "testA",  { Eb, Ib }, 0 },
3524     { "testA",  { Eb, Ib }, 0 },
3525     { "notA",   { Ebh1 }, 0 },
3526     { "negA",   { Ebh1 }, 0 },
3527     { "mulA",   { Eb }, 0 },    /* Don't print the implicit %al register,  */
3528     { "imulA",  { Eb }, 0 },    /* to distinguish these opcodes from other */
3529     { "divA",   { Eb }, 0 },    /* mul/imul opcodes.  Do the same for div  */
3530     { "idivA",  { Eb }, 0 },    /* and idiv for consistency.               */
3531   },
3532   /* REG_F7 */
3533   {
3534     { "testQ",  { Ev, Iv }, 0 },
3535     { "testQ",  { Ev, Iv }, 0 },
3536     { "notQ",   { Evh1 }, 0 },
3537     { "negQ",   { Evh1 }, 0 },
3538     { "mulQ",   { Ev }, 0 },    /* Don't print the implicit register.  */
3539     { "imulQ",  { Ev }, 0 },
3540     { "divQ",   { Ev }, 0 },
3541     { "idivQ",  { Ev }, 0 },
3542   },
3543   /* REG_FE */
3544   {
3545     { "incA",   { Ebh1 }, 0 },
3546     { "decA",   { Ebh1 }, 0 },
3547   },
3548   /* REG_FF */
3549   {
3550     { "incQ",   { Evh1 }, 0 },
3551     { "decQ",   { Evh1 }, 0 },
3552     { "call{&|}", { indirEv, BND }, 0 },
3553     { MOD_TABLE (MOD_FF_REG_3) },
3554     { "jmp{&|}", { indirEv, BND }, 0 },
3555     { MOD_TABLE (MOD_FF_REG_5) },
3556     { "pushU",  { stackEv }, 0 },
3557     { Bad_Opcode },
3558   },
3559   /* REG_0F00 */
3560   {
3561     { "sldtD",  { Sv }, 0 },
3562     { "strD",   { Sv }, 0 },
3563     { "lldt",   { Ew }, 0 },
3564     { "ltr",    { Ew }, 0 },
3565     { "verr",   { Ew }, 0 },
3566     { "verw",   { Ew }, 0 },
3567     { Bad_Opcode },
3568     { Bad_Opcode },
3569   },
3570   /* REG_0F01 */
3571   {
3572     { MOD_TABLE (MOD_0F01_REG_0) },
3573     { MOD_TABLE (MOD_0F01_REG_1) },
3574     { MOD_TABLE (MOD_0F01_REG_2) },
3575     { MOD_TABLE (MOD_0F01_REG_3) },
3576     { "smswD",  { Sv }, 0 },
3577     { MOD_TABLE (MOD_0F01_REG_5) },
3578     { "lmsw",   { Ew }, 0 },
3579     { MOD_TABLE (MOD_0F01_REG_7) },
3580   },
3581   /* REG_0F0D */
3582   {
3583     { "prefetch",       { Mb }, 0 },
3584     { "prefetchw",      { Mb }, 0 },
3585     { "prefetchwt1",    { Mb }, 0 },
3586     { "prefetch",       { Mb }, 0 },
3587     { "prefetch",       { Mb }, 0 },
3588     { "prefetch",       { Mb }, 0 },
3589     { "prefetch",       { Mb }, 0 },
3590     { "prefetch",       { Mb }, 0 },
3591   },
3592   /* REG_0F18 */
3593   {
3594     { MOD_TABLE (MOD_0F18_REG_0) },
3595     { MOD_TABLE (MOD_0F18_REG_1) },
3596     { MOD_TABLE (MOD_0F18_REG_2) },
3597     { MOD_TABLE (MOD_0F18_REG_3) },
3598     { MOD_TABLE (MOD_0F18_REG_4) },
3599     { MOD_TABLE (MOD_0F18_REG_5) },
3600     { MOD_TABLE (MOD_0F18_REG_6) },
3601     { MOD_TABLE (MOD_0F18_REG_7) },
3602   },
3603   /* REG_0F1E_MOD_3 */
3604   {
3605     { "nopQ",           { Ev }, 0 },
3606     { "rdsspK",         { Rdq }, PREFIX_OPCODE },
3607     { "nopQ",           { Ev }, 0 },
3608     { "nopQ",           { Ev }, 0 },
3609     { "nopQ",           { Ev }, 0 },
3610     { "nopQ",           { Ev }, 0 },
3611     { "nopQ",           { Ev }, 0 },
3612     { RM_TABLE (RM_0F1E_MOD_3_REG_7) },
3613   },
3614   /* REG_0F71 */
3615   {
3616     { Bad_Opcode },
3617     { Bad_Opcode },
3618     { MOD_TABLE (MOD_0F71_REG_2) },
3619     { Bad_Opcode },
3620     { MOD_TABLE (MOD_0F71_REG_4) },
3621     { Bad_Opcode },
3622     { MOD_TABLE (MOD_0F71_REG_6) },
3623   },
3624   /* REG_0F72 */
3625   {
3626     { Bad_Opcode },
3627     { Bad_Opcode },
3628     { MOD_TABLE (MOD_0F72_REG_2) },
3629     { Bad_Opcode },
3630     { MOD_TABLE (MOD_0F72_REG_4) },
3631     { Bad_Opcode },
3632     { MOD_TABLE (MOD_0F72_REG_6) },
3633   },
3634   /* REG_0F73 */
3635   {
3636     { Bad_Opcode },
3637     { Bad_Opcode },
3638     { MOD_TABLE (MOD_0F73_REG_2) },
3639     { MOD_TABLE (MOD_0F73_REG_3) },
3640     { Bad_Opcode },
3641     { Bad_Opcode },
3642     { MOD_TABLE (MOD_0F73_REG_6) },
3643     { MOD_TABLE (MOD_0F73_REG_7) },
3644   },
3645   /* REG_0FA6 */
3646   {
3647     { "montmul",        { { OP_0f07, 0 } }, 0 },
3648     { "xsha1",          { { OP_0f07, 0 } }, 0 },
3649     { "xsha256",        { { OP_0f07, 0 } }, 0 },
3650   },
3651   /* REG_0FA7 */
3652   {
3653     { "xstore-rng",     { { OP_0f07, 0 } }, 0 },
3654     { "xcrypt-ecb",     { { OP_0f07, 0 } }, 0 },
3655     { "xcrypt-cbc",     { { OP_0f07, 0 } }, 0 },
3656     { "xcrypt-ctr",     { { OP_0f07, 0 } }, 0 },
3657     { "xcrypt-cfb",     { { OP_0f07, 0 } }, 0 },
3658     { "xcrypt-ofb",     { { OP_0f07, 0 } }, 0 },
3659   },
3660   /* REG_0FAE */
3661   {
3662     { MOD_TABLE (MOD_0FAE_REG_0) },
3663     { MOD_TABLE (MOD_0FAE_REG_1) },
3664     { MOD_TABLE (MOD_0FAE_REG_2) },
3665     { MOD_TABLE (MOD_0FAE_REG_3) },
3666     { MOD_TABLE (MOD_0FAE_REG_4) },
3667     { MOD_TABLE (MOD_0FAE_REG_5) },
3668     { MOD_TABLE (MOD_0FAE_REG_6) },
3669     { MOD_TABLE (MOD_0FAE_REG_7) },
3670   },
3671   /* REG_0FBA */
3672   {
3673     { Bad_Opcode },
3674     { Bad_Opcode },
3675     { Bad_Opcode },
3676     { Bad_Opcode },
3677     { "btQ",    { Ev, Ib }, 0 },
3678     { "btsQ",   { Evh1, Ib }, 0 },
3679     { "btrQ",   { Evh1, Ib }, 0 },
3680     { "btcQ",   { Evh1, Ib }, 0 },
3681   },
3682   /* REG_0FC7 */
3683   {
3684     { Bad_Opcode },
3685     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
3686     { Bad_Opcode },
3687     { MOD_TABLE (MOD_0FC7_REG_3) },
3688     { MOD_TABLE (MOD_0FC7_REG_4) },
3689     { MOD_TABLE (MOD_0FC7_REG_5) },
3690     { MOD_TABLE (MOD_0FC7_REG_6) },
3691     { MOD_TABLE (MOD_0FC7_REG_7) },
3692   },
3693   /* REG_VEX_0F71 */
3694   {
3695     { Bad_Opcode },
3696     { Bad_Opcode },
3697     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3698     { Bad_Opcode },
3699     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3700     { Bad_Opcode },
3701     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3702   },
3703   /* REG_VEX_0F72 */
3704   {
3705     { Bad_Opcode },
3706     { Bad_Opcode },
3707     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3708     { Bad_Opcode },
3709     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3710     { Bad_Opcode },
3711     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3712   },
3713   /* REG_VEX_0F73 */
3714   {
3715     { Bad_Opcode },
3716     { Bad_Opcode },
3717     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3718     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3719     { Bad_Opcode },
3720     { Bad_Opcode },
3721     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3722     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3723   },
3724   /* REG_VEX_0FAE */
3725   {
3726     { Bad_Opcode },
3727     { Bad_Opcode },
3728     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3729     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3730   },
3731   /* REG_VEX_0F38F3 */
3732   {
3733     { Bad_Opcode },
3734     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3735     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3736     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3737   },
3738   /* REG_XOP_LWPCB */
3739   {
3740     { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3741     { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3742   },
3743   /* REG_XOP_LWP */
3744   {
3745     { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3746     { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3747   },
3748   /* REG_XOP_TBM_01 */
3749   {
3750     { Bad_Opcode },
3751     { "blcfill",        { { OP_LWP_E, 0 }, Ev }, 0 },
3752     { "blsfill",        { { OP_LWP_E, 0 }, Ev }, 0 },
3753     { "blcs",   { { OP_LWP_E, 0 }, Ev }, 0 },
3754     { "tzmsk",  { { OP_LWP_E, 0 }, Ev }, 0 },
3755     { "blcic",  { { OP_LWP_E, 0 }, Ev }, 0 },
3756     { "blsic",  { { OP_LWP_E, 0 }, Ev }, 0 },
3757     { "t1mskc", { { OP_LWP_E, 0 }, Ev }, 0 },
3758   },
3759   /* REG_XOP_TBM_02 */
3760   {
3761     { Bad_Opcode },
3762     { "blcmsk", { { OP_LWP_E, 0 }, Ev }, 0 },
3763     { Bad_Opcode },
3764     { Bad_Opcode },
3765     { Bad_Opcode },
3766     { Bad_Opcode },
3767     { "blci",   { { OP_LWP_E, 0 }, Ev }, 0 },
3768   },
3769 #define NEED_REG_TABLE
3770 #include "i386-dis-evex.h"
3771 #undef NEED_REG_TABLE
3772 };
3773
3774 static const struct dis386 prefix_table[][4] = {
3775   /* PREFIX_90 */
3776   {
3777     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3778     { "pause", { XX }, 0 },
3779     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3780     { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3781   },
3782
3783   /* PREFIX_MOD_0_0F01_REG_5 */
3784   {
3785     { Bad_Opcode },
3786     { "rstorssp",       { Mq }, PREFIX_OPCODE },
3787   },
3788
3789   /* PREFIX_MOD_3_0F01_REG_5_RM_1 */
3790   {
3791     { Bad_Opcode },
3792     { "incsspK",        { Skip_MODRM }, PREFIX_OPCODE },
3793   },
3794
3795   /* PREFIX_MOD_3_0F01_REG_5_RM_2 */
3796   {
3797     { Bad_Opcode },
3798     { "savessp",        { Skip_MODRM }, PREFIX_OPCODE },
3799   },
3800
3801   /* PREFIX_0F10 */
3802   {
3803     { "movups", { XM, EXx }, PREFIX_OPCODE },
3804     { "movss",  { XM, EXd }, PREFIX_OPCODE },
3805     { "movupd", { XM, EXx }, PREFIX_OPCODE },
3806     { "movsd",  { XM, EXq }, PREFIX_OPCODE },
3807   },
3808
3809   /* PREFIX_0F11 */
3810   {
3811     { "movups", { EXxS, XM }, PREFIX_OPCODE },
3812     { "movss",  { EXdS, XM }, PREFIX_OPCODE },
3813     { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3814     { "movsd",  { EXqS, XM }, PREFIX_OPCODE },
3815   },
3816
3817   /* PREFIX_0F12 */
3818   {
3819     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3820     { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3821     { "movlpd", { XM, EXq }, PREFIX_OPCODE },
3822     { "movddup", { XM, EXq }, PREFIX_OPCODE },
3823   },
3824
3825   /* PREFIX_0F16 */
3826   {
3827     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3828     { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3829     { "movhpd", { XM, EXq }, PREFIX_OPCODE },
3830   },
3831
3832   /* PREFIX_0F1A */
3833   {
3834     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3835     { "bndcl",  { Gbnd, Ev_bnd }, 0 },
3836     { "bndmov", { Gbnd, Ebnd }, 0 },
3837     { "bndcu",  { Gbnd, Ev_bnd }, 0 },
3838   },
3839
3840   /* PREFIX_0F1B */
3841   {
3842     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3843     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3844     { "bndmov", { Ebnd, Gbnd }, 0 },
3845     { "bndcn",  { Gbnd, Ev_bnd }, 0 },
3846   },
3847
3848   /* PREFIX_0F1E */
3849   {
3850     { "nopQ",   { Ev }, PREFIX_OPCODE },
3851     { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3852     { "nopQ",   { Ev }, PREFIX_OPCODE },
3853     { "nopQ",   { Ev }, PREFIX_OPCODE },
3854   },
3855
3856   /* PREFIX_0F2A */
3857   {
3858     { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3859     { "cvtsi2ss%LQ", { XM, Ev }, PREFIX_OPCODE },
3860     { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3861     { "cvtsi2sd%LQ", { XM, Ev }, 0 },
3862   },
3863
3864   /* PREFIX_0F2B */
3865   {
3866     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3867     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3868     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3869     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3870   },
3871
3872   /* PREFIX_0F2C */
3873   {
3874     { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3875     { "cvttss2siY", { Gv, EXd }, PREFIX_OPCODE },
3876     { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3877     { "cvttsd2siY", { Gv, EXq }, PREFIX_OPCODE },
3878   },
3879
3880   /* PREFIX_0F2D */
3881   {
3882     { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3883     { "cvtss2siY", { Gv, EXd }, PREFIX_OPCODE },
3884     { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3885     { "cvtsd2siY", { Gv, EXq }, PREFIX_OPCODE },
3886   },
3887
3888   /* PREFIX_0F2E */
3889   {
3890     { "ucomiss",{ XM, EXd }, 0 },
3891     { Bad_Opcode },
3892     { "ucomisd",{ XM, EXq }, 0 },
3893   },
3894
3895   /* PREFIX_0F2F */
3896   {
3897     { "comiss", { XM, EXd }, 0 },
3898     { Bad_Opcode },
3899     { "comisd", { XM, EXq }, 0 },
3900   },
3901
3902   /* PREFIX_0F51 */
3903   {
3904     { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3905     { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3906     { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3907     { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3908   },
3909
3910   /* PREFIX_0F52 */
3911   {
3912     { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3913     { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3914   },
3915
3916   /* PREFIX_0F53 */
3917   {
3918     { "rcpps",  { XM, EXx }, PREFIX_OPCODE },
3919     { "rcpss",  { XM, EXd }, PREFIX_OPCODE },
3920   },
3921
3922   /* PREFIX_0F58 */
3923   {
3924     { "addps", { XM, EXx }, PREFIX_OPCODE },
3925     { "addss", { XM, EXd }, PREFIX_OPCODE },
3926     { "addpd", { XM, EXx }, PREFIX_OPCODE },
3927     { "addsd", { XM, EXq }, PREFIX_OPCODE },
3928   },
3929
3930   /* PREFIX_0F59 */
3931   {
3932     { "mulps",  { XM, EXx }, PREFIX_OPCODE },
3933     { "mulss",  { XM, EXd }, PREFIX_OPCODE },
3934     { "mulpd",  { XM, EXx }, PREFIX_OPCODE },
3935     { "mulsd",  { XM, EXq }, PREFIX_OPCODE },
3936   },
3937
3938   /* PREFIX_0F5A */
3939   {
3940     { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3941     { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3942     { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3943     { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3944   },
3945
3946   /* PREFIX_0F5B */
3947   {
3948     { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3949     { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3950     { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3951   },
3952
3953   /* PREFIX_0F5C */
3954   {
3955     { "subps",  { XM, EXx }, PREFIX_OPCODE },
3956     { "subss",  { XM, EXd }, PREFIX_OPCODE },
3957     { "subpd",  { XM, EXx }, PREFIX_OPCODE },
3958     { "subsd",  { XM, EXq }, PREFIX_OPCODE },
3959   },
3960
3961   /* PREFIX_0F5D */
3962   {
3963     { "minps",  { XM, EXx }, PREFIX_OPCODE },
3964     { "minss",  { XM, EXd }, PREFIX_OPCODE },
3965     { "minpd",  { XM, EXx }, PREFIX_OPCODE },
3966     { "minsd",  { XM, EXq }, PREFIX_OPCODE },
3967   },
3968
3969   /* PREFIX_0F5E */
3970   {
3971     { "divps",  { XM, EXx }, PREFIX_OPCODE },
3972     { "divss",  { XM, EXd }, PREFIX_OPCODE },
3973     { "divpd",  { XM, EXx }, PREFIX_OPCODE },
3974     { "divsd",  { XM, EXq }, PREFIX_OPCODE },
3975   },
3976
3977   /* PREFIX_0F5F */
3978   {
3979     { "maxps",  { XM, EXx }, PREFIX_OPCODE },
3980     { "maxss",  { XM, EXd }, PREFIX_OPCODE },
3981     { "maxpd",  { XM, EXx }, PREFIX_OPCODE },
3982     { "maxsd",  { XM, EXq }, PREFIX_OPCODE },
3983   },
3984
3985   /* PREFIX_0F60 */
3986   {
3987     { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3988     { Bad_Opcode },
3989     { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3990   },
3991
3992   /* PREFIX_0F61 */
3993   {
3994     { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3995     { Bad_Opcode },
3996     { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3997   },
3998
3999   /* PREFIX_0F62 */
4000   {
4001     { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
4002     { Bad_Opcode },
4003     { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
4004   },
4005
4006   /* PREFIX_0F6C */
4007   {
4008     { Bad_Opcode },
4009     { Bad_Opcode },
4010     { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE },
4011   },
4012
4013   /* PREFIX_0F6D */
4014   {
4015     { Bad_Opcode },
4016     { Bad_Opcode },
4017     { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE },
4018   },
4019
4020   /* PREFIX_0F6F */
4021   {
4022     { "movq",   { MX, EM }, PREFIX_OPCODE },
4023     { "movdqu", { XM, EXx }, PREFIX_OPCODE },
4024     { "movdqa", { XM, EXx }, PREFIX_OPCODE },
4025   },
4026
4027   /* PREFIX_0F70 */
4028   {
4029     { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
4030     { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
4031     { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
4032     { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
4033   },
4034
4035   /* PREFIX_0F73_REG_3 */
4036   {
4037     { Bad_Opcode },
4038     { Bad_Opcode },
4039     { "psrldq", { XS, Ib }, 0 },
4040   },
4041
4042   /* PREFIX_0F73_REG_7 */
4043   {
4044     { Bad_Opcode },
4045     { Bad_Opcode },
4046     { "pslldq", { XS, Ib }, 0 },
4047   },
4048
4049   /* PREFIX_0F78 */
4050   {
4051     {"vmread",  { Em, Gm }, 0 },
4052     { Bad_Opcode },
4053     {"extrq",   { XS, Ib, Ib }, 0 },
4054     {"insertq", { XM, XS, Ib, Ib }, 0 },
4055   },
4056
4057   /* PREFIX_0F79 */
4058   {
4059     {"vmwrite", { Gm, Em }, 0 },
4060     { Bad_Opcode },
4061     {"extrq",   { XM, XS }, 0 },
4062     {"insertq", { XM, XS }, 0 },
4063   },
4064
4065   /* PREFIX_0F7C */
4066   {
4067     { Bad_Opcode },
4068     { Bad_Opcode },
4069     { "haddpd", { XM, EXx }, PREFIX_OPCODE },
4070     { "haddps", { XM, EXx }, PREFIX_OPCODE },
4071   },
4072
4073   /* PREFIX_0F7D */
4074   {
4075     { Bad_Opcode },
4076     { Bad_Opcode },
4077     { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
4078     { "hsubps", { XM, EXx }, PREFIX_OPCODE },
4079   },
4080
4081   /* PREFIX_0F7E */
4082   {
4083     { "movK",   { Edq, MX }, PREFIX_OPCODE },
4084     { "movq",   { XM, EXq }, PREFIX_OPCODE },
4085     { "movK",   { Edq, XM }, PREFIX_OPCODE },
4086   },
4087
4088   /* PREFIX_0F7F */
4089   {
4090     { "movq",   { EMS, MX }, PREFIX_OPCODE },
4091     { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
4092     { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
4093   },
4094
4095   /* PREFIX_0FAE_REG_0 */
4096   {
4097     { Bad_Opcode },
4098     { "rdfsbase", { Ev }, 0 },
4099   },
4100
4101   /* PREFIX_0FAE_REG_1 */
4102   {
4103     { Bad_Opcode },
4104     { "rdgsbase", { Ev }, 0 },
4105   },
4106
4107   /* PREFIX_0FAE_REG_2 */
4108   {
4109     { Bad_Opcode },
4110     { "wrfsbase", { Ev }, 0 },
4111   },
4112
4113   /* PREFIX_0FAE_REG_3 */
4114   {
4115     { Bad_Opcode },
4116     { "wrgsbase", { Ev }, 0 },
4117   },
4118
4119   /* PREFIX_MOD_0_0FAE_REG_4 */
4120   {
4121     { "xsave",  { FXSAVE }, 0 },
4122     { "ptwrite%LQ", { Edq }, 0 },
4123   },
4124
4125   /* PREFIX_MOD_3_0FAE_REG_4 */
4126   {
4127     { Bad_Opcode },
4128     { "ptwrite%LQ", { Edq }, 0 },
4129   },
4130
4131   /* PREFIX_MOD_0_0FAE_REG_5 */
4132   {
4133     { "xrstor",         { FXSAVE }, PREFIX_OPCODE },
4134     { "setssbsy",       { Mq }, PREFIX_OPCODE },
4135   },
4136
4137   /* PREFIX_0FAE_REG_6 */
4138   {
4139     { "xsaveopt",       { FXSAVE }, PREFIX_OPCODE },
4140     { "clrssbsy",       { Mq }, PREFIX_OPCODE },
4141     { "clwb",   { Mb }, PREFIX_OPCODE },
4142   },
4143
4144   /* PREFIX_0FAE_REG_7 */
4145   {
4146     { "clflush",        { Mb }, 0 },
4147     { Bad_Opcode },
4148     { "clflushopt",     { Mb }, 0 },
4149   },
4150
4151   /* PREFIX_0FB8 */
4152   {
4153     { Bad_Opcode },
4154     { "popcntS", { Gv, Ev }, 0 },
4155   },
4156
4157   /* PREFIX_0FBC */
4158   {
4159     { "bsfS",   { Gv, Ev }, 0 },
4160     { "tzcntS", { Gv, Ev }, 0 },
4161     { "bsfS",   { Gv, Ev }, 0 },
4162   },
4163
4164   /* PREFIX_0FBD */
4165   {
4166     { "bsrS",   { Gv, Ev }, 0 },
4167     { "lzcntS", { Gv, Ev }, 0 },
4168     { "bsrS",   { Gv, Ev }, 0 },
4169   },
4170
4171   /* PREFIX_0FC2 */
4172   {
4173     { "cmpps",  { XM, EXx, CMP }, PREFIX_OPCODE },
4174     { "cmpss",  { XM, EXd, CMP }, PREFIX_OPCODE },
4175     { "cmppd",  { XM, EXx, CMP }, PREFIX_OPCODE },
4176     { "cmpsd",  { XM, EXq, CMP }, PREFIX_OPCODE },
4177   },
4178
4179   /* PREFIX_MOD_0_0FC3 */
4180   {
4181     { "movntiS", { Ev, Gv }, PREFIX_OPCODE },
4182   },
4183
4184   /* PREFIX_MOD_0_0FC7_REG_6 */
4185   {
4186     { "vmptrld",{ Mq }, 0 },
4187     { "vmxon",  { Mq }, 0 },
4188     { "vmclear",{ Mq }, 0 },
4189   },
4190
4191   /* PREFIX_MOD_3_0FC7_REG_6 */
4192   {
4193     { "rdrand", { Ev }, 0 },
4194     { Bad_Opcode },
4195     { "rdrand", { Ev }, 0 }
4196   },
4197
4198   /* PREFIX_MOD_3_0FC7_REG_7 */
4199   {
4200     { "rdseed", { Ev }, 0 },
4201     { "rdpid",  { Em }, 0 },
4202     { "rdseed", { Ev }, 0 },
4203   },
4204
4205   /* PREFIX_0FD0 */
4206   {
4207     { Bad_Opcode },
4208     { Bad_Opcode },
4209     { "addsubpd", { XM, EXx }, 0 },
4210     { "addsubps", { XM, EXx }, 0 },
4211   },
4212
4213   /* PREFIX_0FD6 */
4214   {
4215     { Bad_Opcode },
4216     { "movq2dq",{ XM, MS }, 0 },
4217     { "movq",   { EXqS, XM }, 0 },
4218     { "movdq2q",{ MX, XS }, 0 },
4219   },
4220
4221   /* PREFIX_0FE6 */
4222   {
4223     { Bad_Opcode },
4224     { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
4225     { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
4226     { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
4227   },
4228
4229   /* PREFIX_0FE7 */
4230   {
4231     { "movntq", { Mq, MX }, PREFIX_OPCODE },
4232     { Bad_Opcode },
4233     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
4234   },
4235
4236   /* PREFIX_0FF0 */
4237   {
4238     { Bad_Opcode },
4239     { Bad_Opcode },
4240     { Bad_Opcode },
4241     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4242   },
4243
4244   /* PREFIX_0FF7 */
4245   {
4246     { "maskmovq", { MX, MS }, PREFIX_OPCODE },
4247     { Bad_Opcode },
4248     { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
4249   },
4250
4251   /* PREFIX_0F3810 */
4252   {
4253     { Bad_Opcode },
4254     { Bad_Opcode },
4255     { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4256   },
4257
4258   /* PREFIX_0F3814 */
4259   {
4260     { Bad_Opcode },
4261     { Bad_Opcode },
4262     { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4263   },
4264
4265   /* PREFIX_0F3815 */
4266   {
4267     { Bad_Opcode },
4268     { Bad_Opcode },
4269     { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4270   },
4271
4272   /* PREFIX_0F3817 */
4273   {
4274     { Bad_Opcode },
4275     { Bad_Opcode },
4276     { "ptest",  { XM, EXx }, PREFIX_OPCODE },
4277   },
4278
4279   /* PREFIX_0F3820 */
4280   {
4281     { Bad_Opcode },
4282     { Bad_Opcode },
4283     { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE },
4284   },
4285
4286   /* PREFIX_0F3821 */
4287   {
4288     { Bad_Opcode },
4289     { Bad_Opcode },
4290     { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE },
4291   },
4292
4293   /* PREFIX_0F3822 */
4294   {
4295     { Bad_Opcode },
4296     { Bad_Opcode },
4297     { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE },
4298   },
4299
4300   /* PREFIX_0F3823 */
4301   {
4302     { Bad_Opcode },
4303     { Bad_Opcode },
4304     { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE },
4305   },
4306
4307   /* PREFIX_0F3824 */
4308   {
4309     { Bad_Opcode },
4310     { Bad_Opcode },
4311     { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE },
4312   },
4313
4314   /* PREFIX_0F3825 */
4315   {
4316     { Bad_Opcode },
4317     { Bad_Opcode },
4318     { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE },
4319   },
4320
4321   /* PREFIX_0F3828 */
4322   {
4323     { Bad_Opcode },
4324     { Bad_Opcode },
4325     { "pmuldq", { XM, EXx }, PREFIX_OPCODE },
4326   },
4327
4328   /* PREFIX_0F3829 */
4329   {
4330     { Bad_Opcode },
4331     { Bad_Opcode },
4332     { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE },
4333   },
4334
4335   /* PREFIX_0F382A */
4336   {
4337     { Bad_Opcode },
4338     { Bad_Opcode },
4339     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4340   },
4341
4342   /* PREFIX_0F382B */
4343   {
4344     { Bad_Opcode },
4345     { Bad_Opcode },
4346     { "packusdw", { XM, EXx }, PREFIX_OPCODE },
4347   },
4348
4349   /* PREFIX_0F3830 */
4350   {
4351     { Bad_Opcode },
4352     { Bad_Opcode },
4353     { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE },
4354   },
4355
4356   /* PREFIX_0F3831 */
4357   {
4358     { Bad_Opcode },
4359     { Bad_Opcode },
4360     { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE },
4361   },
4362
4363   /* PREFIX_0F3832 */
4364   {
4365     { Bad_Opcode },
4366     { Bad_Opcode },
4367     { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE },
4368   },
4369
4370   /* PREFIX_0F3833 */
4371   {
4372     { Bad_Opcode },
4373     { Bad_Opcode },
4374     { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE },
4375   },
4376
4377   /* PREFIX_0F3834 */
4378   {
4379     { Bad_Opcode },
4380     { Bad_Opcode },
4381     { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE },
4382   },
4383
4384   /* PREFIX_0F3835 */
4385   {
4386     { Bad_Opcode },
4387     { Bad_Opcode },
4388     { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE },
4389   },
4390
4391   /* PREFIX_0F3837 */
4392   {
4393     { Bad_Opcode },
4394     { Bad_Opcode },
4395     { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE },
4396   },
4397
4398   /* PREFIX_0F3838 */
4399   {
4400     { Bad_Opcode },
4401     { Bad_Opcode },
4402     { "pminsb", { XM, EXx }, PREFIX_OPCODE },
4403   },
4404
4405   /* PREFIX_0F3839 */
4406   {
4407     { Bad_Opcode },
4408     { Bad_Opcode },
4409     { "pminsd", { XM, EXx }, PREFIX_OPCODE },
4410   },
4411
4412   /* PREFIX_0F383A */
4413   {
4414     { Bad_Opcode },
4415     { Bad_Opcode },
4416     { "pminuw", { XM, EXx }, PREFIX_OPCODE },
4417   },
4418
4419   /* PREFIX_0F383B */
4420   {
4421     { Bad_Opcode },
4422     { Bad_Opcode },
4423     { "pminud", { XM, EXx }, PREFIX_OPCODE },
4424   },
4425
4426   /* PREFIX_0F383C */
4427   {
4428     { Bad_Opcode },
4429     { Bad_Opcode },
4430     { "pmaxsb", { XM, EXx }, PREFIX_OPCODE },
4431   },
4432
4433   /* PREFIX_0F383D */
4434   {
4435     { Bad_Opcode },
4436     { Bad_Opcode },
4437     { "pmaxsd", { XM, EXx }, PREFIX_OPCODE },
4438   },
4439
4440   /* PREFIX_0F383E */
4441   {
4442     { Bad_Opcode },
4443     { Bad_Opcode },
4444     { "pmaxuw", { XM, EXx }, PREFIX_OPCODE },
4445   },
4446
4447   /* PREFIX_0F383F */
4448   {
4449     { Bad_Opcode },
4450     { Bad_Opcode },
4451     { "pmaxud", { XM, EXx }, PREFIX_OPCODE },
4452   },
4453
4454   /* PREFIX_0F3840 */
4455   {
4456     { Bad_Opcode },
4457     { Bad_Opcode },
4458     { "pmulld", { XM, EXx }, PREFIX_OPCODE },
4459   },
4460
4461   /* PREFIX_0F3841 */
4462   {
4463     { Bad_Opcode },
4464     { Bad_Opcode },
4465     { "phminposuw", { XM, EXx }, PREFIX_OPCODE },
4466   },
4467
4468   /* PREFIX_0F3880 */
4469   {
4470     { Bad_Opcode },
4471     { Bad_Opcode },
4472     { "invept", { Gm, Mo }, PREFIX_OPCODE },
4473   },
4474
4475   /* PREFIX_0F3881 */
4476   {
4477     { Bad_Opcode },
4478     { Bad_Opcode },
4479     { "invvpid", { Gm, Mo }, PREFIX_OPCODE },
4480   },
4481
4482   /* PREFIX_0F3882 */
4483   {
4484     { Bad_Opcode },
4485     { Bad_Opcode },
4486     { "invpcid", { Gm, M }, PREFIX_OPCODE },
4487   },
4488
4489   /* PREFIX_0F38C8 */
4490   {
4491     { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4492   },
4493
4494   /* PREFIX_0F38C9 */
4495   {
4496     { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4497   },
4498
4499   /* PREFIX_0F38CA */
4500   {
4501     { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4502   },
4503
4504   /* PREFIX_0F38CB */
4505   {
4506     { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4507   },
4508
4509   /* PREFIX_0F38CC */
4510   {
4511     { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4512   },
4513
4514   /* PREFIX_0F38CD */
4515   {
4516     { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4517   },
4518
4519   /* PREFIX_0F38DB */
4520   {
4521     { Bad_Opcode },
4522     { Bad_Opcode },
4523     { "aesimc", { XM, EXx }, PREFIX_OPCODE },
4524   },
4525
4526   /* PREFIX_0F38DC */
4527   {
4528     { Bad_Opcode },
4529     { Bad_Opcode },
4530     { "aesenc", { XM, EXx }, PREFIX_OPCODE },
4531   },
4532
4533   /* PREFIX_0F38DD */
4534   {
4535     { Bad_Opcode },
4536     { Bad_Opcode },
4537     { "aesenclast", { XM, EXx }, PREFIX_OPCODE },
4538   },
4539
4540   /* PREFIX_0F38DE */
4541   {
4542     { Bad_Opcode },
4543     { Bad_Opcode },
4544     { "aesdec", { XM, EXx }, PREFIX_OPCODE },
4545   },
4546
4547   /* PREFIX_0F38DF */
4548   {
4549     { Bad_Opcode },
4550     { Bad_Opcode },
4551     { "aesdeclast", { XM, EXx }, PREFIX_OPCODE },
4552   },
4553
4554   /* PREFIX_0F38F0 */
4555   {
4556     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4557     { Bad_Opcode },
4558     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4559     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE },
4560   },
4561
4562   /* PREFIX_0F38F1 */
4563   {
4564     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4565     { Bad_Opcode },
4566     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4567     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE },
4568   },
4569
4570   /* PREFIX_0F38F5 */
4571   {
4572     { Bad_Opcode },
4573     { Bad_Opcode },
4574     { MOD_TABLE (MOD_0F38F5_PREFIX_2) },
4575   },
4576
4577   /* PREFIX_0F38F6 */
4578   {
4579     { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
4580     { "adoxS",  { Gdq, Edq}, PREFIX_OPCODE },
4581     { "adcxS",  { Gdq, Edq}, PREFIX_OPCODE },
4582     { Bad_Opcode },
4583   },
4584
4585   /* PREFIX_0F3A08 */
4586   {
4587     { Bad_Opcode },
4588     { Bad_Opcode },
4589     { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE },
4590   },
4591
4592   /* PREFIX_0F3A09 */
4593   {
4594     { Bad_Opcode },
4595     { Bad_Opcode },
4596     { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4597   },
4598
4599   /* PREFIX_0F3A0A */
4600   {
4601     { Bad_Opcode },
4602     { Bad_Opcode },
4603     { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE },
4604   },
4605
4606   /* PREFIX_0F3A0B */
4607   {
4608     { Bad_Opcode },
4609     { Bad_Opcode },
4610     { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE },
4611   },
4612
4613   /* PREFIX_0F3A0C */
4614   {
4615     { Bad_Opcode },
4616     { Bad_Opcode },
4617     { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE },
4618   },
4619
4620   /* PREFIX_0F3A0D */
4621   {
4622     { Bad_Opcode },
4623     { Bad_Opcode },
4624     { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4625   },
4626
4627   /* PREFIX_0F3A0E */
4628   {
4629     { Bad_Opcode },
4630     { Bad_Opcode },
4631     { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE },
4632   },
4633
4634   /* PREFIX_0F3A14 */
4635   {
4636     { Bad_Opcode },
4637     { Bad_Opcode },
4638     { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE },
4639   },
4640
4641   /* PREFIX_0F3A15 */
4642   {
4643     { Bad_Opcode },
4644     { Bad_Opcode },
4645     { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE },
4646   },
4647
4648   /* PREFIX_0F3A16 */
4649   {
4650     { Bad_Opcode },
4651     { Bad_Opcode },
4652     { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE },
4653   },
4654
4655   /* PREFIX_0F3A17 */
4656   {
4657     { Bad_Opcode },
4658     { Bad_Opcode },
4659     { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE },
4660   },
4661
4662   /* PREFIX_0F3A20 */
4663   {
4664     { Bad_Opcode },
4665     { Bad_Opcode },
4666     { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE },
4667   },
4668
4669   /* PREFIX_0F3A21 */
4670   {
4671     { Bad_Opcode },
4672     { Bad_Opcode },
4673     { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE },
4674   },
4675
4676   /* PREFIX_0F3A22 */
4677   {
4678     { Bad_Opcode },
4679     { Bad_Opcode },
4680     { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE },
4681   },
4682
4683   /* PREFIX_0F3A40 */
4684   {
4685     { Bad_Opcode },
4686     { Bad_Opcode },
4687     { "dpps",   { XM, EXx, Ib }, PREFIX_OPCODE },
4688   },
4689
4690   /* PREFIX_0F3A41 */
4691   {
4692     { Bad_Opcode },
4693     { Bad_Opcode },
4694     { "dppd",   { XM, EXx, Ib }, PREFIX_OPCODE },
4695   },
4696
4697   /* PREFIX_0F3A42 */
4698   {
4699     { Bad_Opcode },
4700     { Bad_Opcode },
4701     { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE },
4702   },
4703
4704   /* PREFIX_0F3A44 */
4705   {
4706     { Bad_Opcode },
4707     { Bad_Opcode },
4708     { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE },
4709   },
4710
4711   /* PREFIX_0F3A60 */
4712   {
4713     { Bad_Opcode },
4714     { Bad_Opcode },
4715     { "pcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4716   },
4717
4718   /* PREFIX_0F3A61 */
4719   {
4720     { Bad_Opcode },
4721     { Bad_Opcode },
4722     { "pcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4723   },
4724
4725   /* PREFIX_0F3A62 */
4726   {
4727     { Bad_Opcode },
4728     { Bad_Opcode },
4729     { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4730   },
4731
4732   /* PREFIX_0F3A63 */
4733   {
4734     { Bad_Opcode },
4735     { Bad_Opcode },
4736     { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE },
4737   },
4738
4739   /* PREFIX_0F3ACC */
4740   {
4741     { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4742   },
4743
4744   /* PREFIX_0F3ADF */
4745   {
4746     { Bad_Opcode },
4747     { Bad_Opcode },
4748     { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE },
4749   },
4750
4751   /* PREFIX_VEX_0F10 */
4752   {
4753     { VEX_W_TABLE (VEX_W_0F10_P_0) },
4754     { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) },
4755     { VEX_W_TABLE (VEX_W_0F10_P_2) },
4756     { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) },
4757   },
4758
4759   /* PREFIX_VEX_0F11 */
4760   {
4761     { VEX_W_TABLE (VEX_W_0F11_P_0) },
4762     { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) },
4763     { VEX_W_TABLE (VEX_W_0F11_P_2) },
4764     { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) },
4765   },
4766
4767   /* PREFIX_VEX_0F12 */
4768   {
4769     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4770     { VEX_W_TABLE (VEX_W_0F12_P_1) },
4771     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
4772     { VEX_W_TABLE (VEX_W_0F12_P_3) },
4773   },
4774
4775   /* PREFIX_VEX_0F16 */
4776   {
4777     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4778     { VEX_W_TABLE (VEX_W_0F16_P_1) },
4779     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
4780   },
4781
4782   /* PREFIX_VEX_0F2A */
4783   {
4784     { Bad_Opcode },
4785     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) },
4786     { Bad_Opcode },
4787     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) },
4788   },
4789
4790   /* PREFIX_VEX_0F2C */
4791   {
4792     { Bad_Opcode },
4793     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) },
4794     { Bad_Opcode },
4795     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) },
4796   },
4797
4798   /* PREFIX_VEX_0F2D */
4799   {
4800     { Bad_Opcode },
4801     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) },
4802     { Bad_Opcode },
4803     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) },
4804   },
4805
4806   /* PREFIX_VEX_0F2E */
4807   {
4808     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) },
4809     { Bad_Opcode },
4810     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) },
4811   },
4812
4813   /* PREFIX_VEX_0F2F */
4814   {
4815     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) },
4816     { Bad_Opcode },
4817     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) },
4818   },
4819
4820   /* PREFIX_VEX_0F41 */
4821   {
4822     { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4823     { Bad_Opcode },
4824     { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4825   },
4826
4827   /* PREFIX_VEX_0F42 */
4828   {
4829     { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4830     { Bad_Opcode },
4831     { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4832   },
4833
4834   /* PREFIX_VEX_0F44 */
4835   {
4836     { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4837     { Bad_Opcode },
4838     { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4839   },
4840
4841   /* PREFIX_VEX_0F45 */
4842   {
4843     { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4844     { Bad_Opcode },
4845     { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4846   },
4847
4848   /* PREFIX_VEX_0F46 */
4849   {
4850     { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4851     { Bad_Opcode },
4852     { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4853   },
4854
4855   /* PREFIX_VEX_0F47 */
4856   {
4857     { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4858     { Bad_Opcode },
4859     { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
4860   },
4861
4862   /* PREFIX_VEX_0F4A */
4863   {
4864     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
4865     { Bad_Opcode },
4866     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
4867   },
4868
4869   /* PREFIX_VEX_0F4B */
4870   {
4871     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
4872     { Bad_Opcode },
4873     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4874   },
4875
4876   /* PREFIX_VEX_0F51 */
4877   {
4878     { VEX_W_TABLE (VEX_W_0F51_P_0) },
4879     { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) },
4880     { VEX_W_TABLE (VEX_W_0F51_P_2) },
4881     { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) },
4882   },
4883
4884   /* PREFIX_VEX_0F52 */
4885   {
4886     { VEX_W_TABLE (VEX_W_0F52_P_0) },
4887     { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) },
4888   },
4889
4890   /* PREFIX_VEX_0F53 */
4891   {
4892     { VEX_W_TABLE (VEX_W_0F53_P_0) },
4893     { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) },
4894   },
4895
4896   /* PREFIX_VEX_0F58 */
4897   {
4898     { VEX_W_TABLE (VEX_W_0F58_P_0) },
4899     { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) },
4900     { VEX_W_TABLE (VEX_W_0F58_P_2) },
4901     { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) },
4902   },
4903
4904   /* PREFIX_VEX_0F59 */
4905   {
4906     { VEX_W_TABLE (VEX_W_0F59_P_0) },
4907     { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) },
4908     { VEX_W_TABLE (VEX_W_0F59_P_2) },
4909     { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) },
4910   },
4911
4912   /* PREFIX_VEX_0F5A */
4913   {
4914     { VEX_W_TABLE (VEX_W_0F5A_P_0) },
4915     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) },
4916     { "vcvtpd2ps%XY", { XMM, EXx }, 0 },
4917     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) },
4918   },
4919
4920   /* PREFIX_VEX_0F5B */
4921   {
4922     { VEX_W_TABLE (VEX_W_0F5B_P_0) },
4923     { VEX_W_TABLE (VEX_W_0F5B_P_1) },
4924     { VEX_W_TABLE (VEX_W_0F5B_P_2) },
4925   },
4926
4927   /* PREFIX_VEX_0F5C */
4928   {
4929     { VEX_W_TABLE (VEX_W_0F5C_P_0) },
4930     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) },
4931     { VEX_W_TABLE (VEX_W_0F5C_P_2) },
4932     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) },
4933   },
4934
4935   /* PREFIX_VEX_0F5D */
4936   {
4937     { VEX_W_TABLE (VEX_W_0F5D_P_0) },
4938     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) },
4939     { VEX_W_TABLE (VEX_W_0F5D_P_2) },
4940     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) },
4941   },
4942
4943   /* PREFIX_VEX_0F5E */
4944   {
4945     { VEX_W_TABLE (VEX_W_0F5E_P_0) },
4946     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) },
4947     { VEX_W_TABLE (VEX_W_0F5E_P_2) },
4948     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) },
4949   },
4950
4951   /* PREFIX_VEX_0F5F */
4952   {
4953     { VEX_W_TABLE (VEX_W_0F5F_P_0) },
4954     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) },
4955     { VEX_W_TABLE (VEX_W_0F5F_P_2) },
4956     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) },
4957   },
4958
4959   /* PREFIX_VEX_0F60 */
4960   {
4961     { Bad_Opcode },
4962     { Bad_Opcode },
4963     { VEX_W_TABLE (VEX_W_0F60_P_2) },
4964   },
4965
4966   /* PREFIX_VEX_0F61 */
4967   {
4968     { Bad_Opcode },
4969     { Bad_Opcode },
4970     { VEX_W_TABLE (VEX_W_0F61_P_2) },
4971   },
4972
4973   /* PREFIX_VEX_0F62 */
4974   {
4975     { Bad_Opcode },
4976     { Bad_Opcode },
4977     { VEX_W_TABLE (VEX_W_0F62_P_2) },
4978   },
4979
4980   /* PREFIX_VEX_0F63 */
4981   {
4982     { Bad_Opcode },
4983     { Bad_Opcode },
4984     { VEX_W_TABLE (VEX_W_0F63_P_2) },
4985   },
4986
4987   /* PREFIX_VEX_0F64 */
4988   {
4989     { Bad_Opcode },
4990     { Bad_Opcode },
4991     { VEX_W_TABLE (VEX_W_0F64_P_2) },
4992   },
4993
4994   /* PREFIX_VEX_0F65 */
4995   {
4996     { Bad_Opcode },
4997     { Bad_Opcode },
4998     { VEX_W_TABLE (VEX_W_0F65_P_2) },
4999   },
5000
5001   /* PREFIX_VEX_0F66 */
5002   {
5003     { Bad_Opcode },
5004     { Bad_Opcode },
5005     { VEX_W_TABLE (VEX_W_0F66_P_2) },
5006   },
5007
5008   /* PREFIX_VEX_0F67 */
5009   {
5010     { Bad_Opcode },
5011     { Bad_Opcode },
5012     { VEX_W_TABLE (VEX_W_0F67_P_2) },
5013   },
5014
5015   /* PREFIX_VEX_0F68 */
5016   {
5017     { Bad_Opcode },
5018     { Bad_Opcode },
5019     { VEX_W_TABLE (VEX_W_0F68_P_2) },
5020   },
5021
5022   /* PREFIX_VEX_0F69 */
5023   {
5024     { Bad_Opcode },
5025     { Bad_Opcode },
5026     { VEX_W_TABLE (VEX_W_0F69_P_2) },
5027   },
5028
5029   /* PREFIX_VEX_0F6A */
5030   {
5031     { Bad_Opcode },
5032     { Bad_Opcode },
5033     { VEX_W_TABLE (VEX_W_0F6A_P_2) },
5034   },
5035
5036   /* PREFIX_VEX_0F6B */
5037   {
5038     { Bad_Opcode },
5039     { Bad_Opcode },
5040     { VEX_W_TABLE (VEX_W_0F6B_P_2) },
5041   },
5042
5043   /* PREFIX_VEX_0F6C */
5044   {
5045     { Bad_Opcode },
5046     { Bad_Opcode },
5047     { VEX_W_TABLE (VEX_W_0F6C_P_2) },
5048   },
5049
5050   /* PREFIX_VEX_0F6D */
5051   {
5052     { Bad_Opcode },
5053     { Bad_Opcode },
5054     { VEX_W_TABLE (VEX_W_0F6D_P_2) },
5055   },
5056
5057   /* PREFIX_VEX_0F6E */
5058   {
5059     { Bad_Opcode },
5060     { Bad_Opcode },
5061     { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
5062   },
5063
5064   /* PREFIX_VEX_0F6F */
5065   {
5066     { Bad_Opcode },
5067     { VEX_W_TABLE (VEX_W_0F6F_P_1) },
5068     { VEX_W_TABLE (VEX_W_0F6F_P_2) },
5069   },
5070
5071   /* PREFIX_VEX_0F70 */
5072   {
5073     { Bad_Opcode },
5074     { VEX_W_TABLE (VEX_W_0F70_P_1) },
5075     { VEX_W_TABLE (VEX_W_0F70_P_2) },
5076     { VEX_W_TABLE (VEX_W_0F70_P_3) },
5077   },
5078
5079   /* PREFIX_VEX_0F71_REG_2 */
5080   {
5081     { Bad_Opcode },
5082     { Bad_Opcode },
5083     { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) },
5084   },
5085
5086   /* PREFIX_VEX_0F71_REG_4 */
5087   {
5088     { Bad_Opcode },
5089     { Bad_Opcode },
5090     { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) },
5091   },
5092
5093   /* PREFIX_VEX_0F71_REG_6 */
5094   {
5095     { Bad_Opcode },
5096     { Bad_Opcode },
5097     { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) },
5098   },
5099
5100   /* PREFIX_VEX_0F72_REG_2 */
5101   {
5102     { Bad_Opcode },
5103     { Bad_Opcode },
5104     { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) },
5105   },
5106
5107   /* PREFIX_VEX_0F72_REG_4 */
5108   {
5109     { Bad_Opcode },
5110     { Bad_Opcode },
5111     { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) },
5112   },
5113
5114   /* PREFIX_VEX_0F72_REG_6 */
5115   {
5116     { Bad_Opcode },
5117     { Bad_Opcode },
5118     { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) },
5119   },
5120
5121   /* PREFIX_VEX_0F73_REG_2 */
5122   {
5123     { Bad_Opcode },
5124     { Bad_Opcode },
5125     { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) },
5126   },
5127
5128   /* PREFIX_VEX_0F73_REG_3 */
5129   {
5130     { Bad_Opcode },
5131     { Bad_Opcode },
5132     { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) },
5133   },
5134
5135   /* PREFIX_VEX_0F73_REG_6 */
5136   {
5137     { Bad_Opcode },
5138     { Bad_Opcode },
5139     { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) },
5140   },
5141
5142   /* PREFIX_VEX_0F73_REG_7 */
5143   {
5144     { Bad_Opcode },
5145     { Bad_Opcode },
5146     { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) },
5147   },
5148
5149   /* PREFIX_VEX_0F74 */
5150   {
5151     { Bad_Opcode },
5152     { Bad_Opcode },
5153     { VEX_W_TABLE (VEX_W_0F74_P_2) },
5154   },
5155
5156   /* PREFIX_VEX_0F75 */
5157   {
5158     { Bad_Opcode },
5159     { Bad_Opcode },
5160     { VEX_W_TABLE (VEX_W_0F75_P_2) },
5161   },
5162
5163   /* PREFIX_VEX_0F76 */
5164   {
5165     { Bad_Opcode },
5166     { Bad_Opcode },
5167     { VEX_W_TABLE (VEX_W_0F76_P_2) },
5168   },
5169
5170   /* PREFIX_VEX_0F77 */
5171   {
5172     { VEX_W_TABLE (VEX_W_0F77_P_0) },
5173   },
5174
5175   /* PREFIX_VEX_0F7C */
5176   {
5177     { Bad_Opcode },
5178     { Bad_Opcode },
5179     { VEX_W_TABLE (VEX_W_0F7C_P_2) },
5180     { VEX_W_TABLE (VEX_W_0F7C_P_3) },
5181   },
5182
5183   /* PREFIX_VEX_0F7D */
5184   {
5185     { Bad_Opcode },
5186     { Bad_Opcode },
5187     { VEX_W_TABLE (VEX_W_0F7D_P_2) },
5188     { VEX_W_TABLE (VEX_W_0F7D_P_3) },
5189   },
5190
5191   /* PREFIX_VEX_0F7E */
5192   {
5193     { Bad_Opcode },
5194     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
5195     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
5196   },
5197
5198   /* PREFIX_VEX_0F7F */
5199   {
5200     { Bad_Opcode },
5201     { VEX_W_TABLE (VEX_W_0F7F_P_1) },
5202     { VEX_W_TABLE (VEX_W_0F7F_P_2) },
5203   },
5204
5205   /* PREFIX_VEX_0F90 */
5206   {
5207     { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
5208     { Bad_Opcode },
5209     { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
5210   },
5211
5212   /* PREFIX_VEX_0F91 */
5213   {
5214     { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
5215     { Bad_Opcode },
5216     { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
5217   },
5218
5219   /* PREFIX_VEX_0F92 */
5220   {
5221     { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
5222     { Bad_Opcode },
5223     { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
5224     { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
5225   },
5226
5227   /* PREFIX_VEX_0F93 */
5228   {
5229     { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
5230     { Bad_Opcode },
5231     { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
5232     { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
5233   },
5234
5235   /* PREFIX_VEX_0F98 */
5236   {
5237     { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
5238     { Bad_Opcode },
5239     { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
5240   },
5241
5242   /* PREFIX_VEX_0F99 */
5243   {
5244     { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5245     { Bad_Opcode },
5246     { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5247   },
5248
5249   /* PREFIX_VEX_0FC2 */
5250   {
5251     { VEX_W_TABLE (VEX_W_0FC2_P_0) },
5252     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) },
5253     { VEX_W_TABLE (VEX_W_0FC2_P_2) },
5254     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) },
5255   },
5256
5257   /* PREFIX_VEX_0FC4 */
5258   {
5259     { Bad_Opcode },
5260     { Bad_Opcode },
5261     { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5262   },
5263
5264   /* PREFIX_VEX_0FC5 */
5265   {
5266     { Bad_Opcode },
5267     { Bad_Opcode },
5268     { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5269   },
5270
5271   /* PREFIX_VEX_0FD0 */
5272   {
5273     { Bad_Opcode },
5274     { Bad_Opcode },
5275     { VEX_W_TABLE (VEX_W_0FD0_P_2) },
5276     { VEX_W_TABLE (VEX_W_0FD0_P_3) },
5277   },
5278
5279   /* PREFIX_VEX_0FD1 */
5280   {
5281     { Bad_Opcode },
5282     { Bad_Opcode },
5283     { VEX_W_TABLE (VEX_W_0FD1_P_2) },
5284   },
5285
5286   /* PREFIX_VEX_0FD2 */
5287   {
5288     { Bad_Opcode },
5289     { Bad_Opcode },
5290     { VEX_W_TABLE (VEX_W_0FD2_P_2) },
5291   },
5292
5293   /* PREFIX_VEX_0FD3 */
5294   {
5295     { Bad_Opcode },
5296     { Bad_Opcode },
5297     { VEX_W_TABLE (VEX_W_0FD3_P_2) },
5298   },
5299
5300   /* PREFIX_VEX_0FD4 */
5301   {
5302     { Bad_Opcode },
5303     { Bad_Opcode },
5304     { VEX_W_TABLE (VEX_W_0FD4_P_2) },
5305   },
5306
5307   /* PREFIX_VEX_0FD5 */
5308   {
5309     { Bad_Opcode },
5310     { Bad_Opcode },
5311     { VEX_W_TABLE (VEX_W_0FD5_P_2) },
5312   },
5313
5314   /* PREFIX_VEX_0FD6 */
5315   {
5316     { Bad_Opcode },
5317     { Bad_Opcode },
5318     { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5319   },
5320
5321   /* PREFIX_VEX_0FD7 */
5322   {
5323     { Bad_Opcode },
5324     { Bad_Opcode },
5325     { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5326   },
5327
5328   /* PREFIX_VEX_0FD8 */
5329   {
5330     { Bad_Opcode },
5331     { Bad_Opcode },
5332     { VEX_W_TABLE (VEX_W_0FD8_P_2) },
5333   },
5334
5335   /* PREFIX_VEX_0FD9 */
5336   {
5337     { Bad_Opcode },
5338     { Bad_Opcode },
5339     { VEX_W_TABLE (VEX_W_0FD9_P_2) },
5340   },
5341
5342   /* PREFIX_VEX_0FDA */
5343   {
5344     { Bad_Opcode },
5345     { Bad_Opcode },
5346     { VEX_W_TABLE (VEX_W_0FDA_P_2) },
5347   },
5348
5349   /* PREFIX_VEX_0FDB */
5350   {
5351     { Bad_Opcode },
5352     { Bad_Opcode },
5353     { VEX_W_TABLE (VEX_W_0FDB_P_2) },
5354   },
5355
5356   /* PREFIX_VEX_0FDC */
5357   {
5358     { Bad_Opcode },
5359     { Bad_Opcode },
5360     { VEX_W_TABLE (VEX_W_0FDC_P_2) },
5361   },
5362
5363   /* PREFIX_VEX_0FDD */
5364   {
5365     { Bad_Opcode },
5366     { Bad_Opcode },
5367     { VEX_W_TABLE (VEX_W_0FDD_P_2) },
5368   },
5369
5370   /* PREFIX_VEX_0FDE */
5371   {
5372     { Bad_Opcode },
5373     { Bad_Opcode },
5374     { VEX_W_TABLE (VEX_W_0FDE_P_2) },
5375   },
5376
5377   /* PREFIX_VEX_0FDF */
5378   {
5379     { Bad_Opcode },
5380     { Bad_Opcode },
5381     { VEX_W_TABLE (VEX_W_0FDF_P_2) },
5382   },
5383
5384   /* PREFIX_VEX_0FE0 */
5385   {
5386     { Bad_Opcode },
5387     { Bad_Opcode },
5388     { VEX_W_TABLE (VEX_W_0FE0_P_2) },
5389   },
5390
5391   /* PREFIX_VEX_0FE1 */
5392   {
5393     { Bad_Opcode },
5394     { Bad_Opcode },
5395     { VEX_W_TABLE (VEX_W_0FE1_P_2) },
5396   },
5397
5398   /* PREFIX_VEX_0FE2 */
5399   {
5400     { Bad_Opcode },
5401     { Bad_Opcode },
5402     { VEX_W_TABLE (VEX_W_0FE2_P_2) },
5403   },
5404
5405   /* PREFIX_VEX_0FE3 */
5406   {
5407     { Bad_Opcode },
5408     { Bad_Opcode },
5409     { VEX_W_TABLE (VEX_W_0FE3_P_2) },
5410   },
5411
5412   /* PREFIX_VEX_0FE4 */
5413   {
5414     { Bad_Opcode },
5415     { Bad_Opcode },
5416     { VEX_W_TABLE (VEX_W_0FE4_P_2) },
5417   },
5418
5419   /* PREFIX_VEX_0FE5 */
5420   {
5421     { Bad_Opcode },
5422     { Bad_Opcode },
5423     { VEX_W_TABLE (VEX_W_0FE5_P_2) },
5424   },
5425
5426   /* PREFIX_VEX_0FE6 */
5427   {
5428     { Bad_Opcode },
5429     { VEX_W_TABLE (VEX_W_0FE6_P_1) },
5430     { VEX_W_TABLE (VEX_W_0FE6_P_2) },
5431     { VEX_W_TABLE (VEX_W_0FE6_P_3) },
5432   },
5433
5434   /* PREFIX_VEX_0FE7 */
5435   {
5436     { Bad_Opcode },
5437     { Bad_Opcode },
5438     { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5439   },
5440
5441   /* PREFIX_VEX_0FE8 */
5442   {
5443     { Bad_Opcode },
5444     { Bad_Opcode },
5445     { VEX_W_TABLE (VEX_W_0FE8_P_2) },
5446   },
5447
5448   /* PREFIX_VEX_0FE9 */
5449   {
5450     { Bad_Opcode },
5451     { Bad_Opcode },
5452     { VEX_W_TABLE (VEX_W_0FE9_P_2) },
5453   },
5454
5455   /* PREFIX_VEX_0FEA */
5456   {
5457     { Bad_Opcode },
5458     { Bad_Opcode },
5459     { VEX_W_TABLE (VEX_W_0FEA_P_2) },
5460   },
5461
5462   /* PREFIX_VEX_0FEB */
5463   {
5464     { Bad_Opcode },
5465     { Bad_Opcode },
5466     { VEX_W_TABLE (VEX_W_0FEB_P_2) },
5467   },
5468
5469   /* PREFIX_VEX_0FEC */
5470   {
5471     { Bad_Opcode },
5472     { Bad_Opcode },
5473     { VEX_W_TABLE (VEX_W_0FEC_P_2) },
5474   },
5475
5476   /* PREFIX_VEX_0FED */
5477   {
5478     { Bad_Opcode },
5479     { Bad_Opcode },
5480     { VEX_W_TABLE (VEX_W_0FED_P_2) },
5481   },
5482
5483   /* PREFIX_VEX_0FEE */
5484   {
5485     { Bad_Opcode },
5486     { Bad_Opcode },
5487     { VEX_W_TABLE (VEX_W_0FEE_P_2) },
5488   },
5489
5490   /* PREFIX_VEX_0FEF */
5491   {
5492     { Bad_Opcode },
5493     { Bad_Opcode },
5494     { VEX_W_TABLE (VEX_W_0FEF_P_2) },
5495   },
5496
5497   /* PREFIX_VEX_0FF0 */
5498   {
5499     { Bad_Opcode },
5500     { Bad_Opcode },
5501     { Bad_Opcode },
5502     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5503   },
5504
5505   /* PREFIX_VEX_0FF1 */
5506   {
5507     { Bad_Opcode },
5508     { Bad_Opcode },
5509     { VEX_W_TABLE (VEX_W_0FF1_P_2) },
5510   },
5511
5512   /* PREFIX_VEX_0FF2 */
5513   {
5514     { Bad_Opcode },
5515     { Bad_Opcode },
5516     { VEX_W_TABLE (VEX_W_0FF2_P_2) },
5517   },
5518
5519   /* PREFIX_VEX_0FF3 */
5520   {
5521     { Bad_Opcode },
5522     { Bad_Opcode },
5523     { VEX_W_TABLE (VEX_W_0FF3_P_2) },
5524   },
5525
5526   /* PREFIX_VEX_0FF4 */
5527   {
5528     { Bad_Opcode },
5529     { Bad_Opcode },
5530     { VEX_W_TABLE (VEX_W_0FF4_P_2) },
5531   },
5532
5533   /* PREFIX_VEX_0FF5 */
5534   {
5535     { Bad_Opcode },
5536     { Bad_Opcode },
5537     { VEX_W_TABLE (VEX_W_0FF5_P_2) },
5538   },
5539
5540   /* PREFIX_VEX_0FF6 */
5541   {
5542     { Bad_Opcode },
5543     { Bad_Opcode },
5544     { VEX_W_TABLE (VEX_W_0FF6_P_2) },
5545   },
5546
5547   /* PREFIX_VEX_0FF7 */
5548   {
5549     { Bad_Opcode },
5550     { Bad_Opcode },
5551     { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5552   },
5553
5554   /* PREFIX_VEX_0FF8 */
5555   {
5556     { Bad_Opcode },
5557     { Bad_Opcode },
5558     { VEX_W_TABLE (VEX_W_0FF8_P_2) },
5559   },
5560
5561   /* PREFIX_VEX_0FF9 */
5562   {
5563     { Bad_Opcode },
5564     { Bad_Opcode },
5565     { VEX_W_TABLE (VEX_W_0FF9_P_2) },
5566   },
5567
5568   /* PREFIX_VEX_0FFA */
5569   {
5570     { Bad_Opcode },
5571     { Bad_Opcode },
5572     { VEX_W_TABLE (VEX_W_0FFA_P_2) },
5573   },
5574
5575   /* PREFIX_VEX_0FFB */
5576   {
5577     { Bad_Opcode },
5578     { Bad_Opcode },
5579     { VEX_W_TABLE (VEX_W_0FFB_P_2) },
5580   },
5581
5582   /* PREFIX_VEX_0FFC */
5583   {
5584     { Bad_Opcode },
5585     { Bad_Opcode },
5586     { VEX_W_TABLE (VEX_W_0FFC_P_2) },
5587   },
5588
5589   /* PREFIX_VEX_0FFD */
5590   {
5591     { Bad_Opcode },
5592     { Bad_Opcode },
5593     { VEX_W_TABLE (VEX_W_0FFD_P_2) },
5594   },
5595
5596   /* PREFIX_VEX_0FFE */
5597   {
5598     { Bad_Opcode },
5599     { Bad_Opcode },
5600     { VEX_W_TABLE (VEX_W_0FFE_P_2) },
5601   },
5602
5603   /* PREFIX_VEX_0F3800 */
5604   {
5605     { Bad_Opcode },
5606     { Bad_Opcode },
5607     { VEX_W_TABLE (VEX_W_0F3800_P_2) },
5608   },
5609
5610   /* PREFIX_VEX_0F3801 */
5611   {
5612     { Bad_Opcode },
5613     { Bad_Opcode },
5614     { VEX_W_TABLE (VEX_W_0F3801_P_2) },
5615   },
5616
5617   /* PREFIX_VEX_0F3802 */
5618   {
5619     { Bad_Opcode },
5620     { Bad_Opcode },
5621     { VEX_W_TABLE (VEX_W_0F3802_P_2) },
5622   },
5623
5624   /* PREFIX_VEX_0F3803 */
5625   {
5626     { Bad_Opcode },
5627     { Bad_Opcode },
5628     { VEX_W_TABLE (VEX_W_0F3803_P_2) },
5629   },
5630
5631   /* PREFIX_VEX_0F3804 */
5632   {
5633     { Bad_Opcode },
5634     { Bad_Opcode },
5635     { VEX_W_TABLE (VEX_W_0F3804_P_2) },
5636   },
5637
5638   /* PREFIX_VEX_0F3805 */
5639   {
5640     { Bad_Opcode },
5641     { Bad_Opcode },
5642     { VEX_W_TABLE (VEX_W_0F3805_P_2) },
5643   },
5644
5645   /* PREFIX_VEX_0F3806 */
5646   {
5647     { Bad_Opcode },
5648     { Bad_Opcode },
5649     { VEX_W_TABLE (VEX_W_0F3806_P_2) },
5650   },
5651
5652   /* PREFIX_VEX_0F3807 */
5653   {
5654     { Bad_Opcode },
5655     { Bad_Opcode },
5656     { VEX_W_TABLE (VEX_W_0F3807_P_2) },
5657   },
5658
5659   /* PREFIX_VEX_0F3808 */
5660   {
5661     { Bad_Opcode },
5662     { Bad_Opcode },
5663     { VEX_W_TABLE (VEX_W_0F3808_P_2) },
5664   },
5665
5666   /* PREFIX_VEX_0F3809 */
5667   {
5668     { Bad_Opcode },
5669     { Bad_Opcode },
5670     { VEX_W_TABLE (VEX_W_0F3809_P_2) },
5671   },
5672
5673   /* PREFIX_VEX_0F380A */
5674   {
5675     { Bad_Opcode },
5676     { Bad_Opcode },
5677     { VEX_W_TABLE (VEX_W_0F380A_P_2) },
5678   },
5679
5680   /* PREFIX_VEX_0F380B */
5681   {
5682     { Bad_Opcode },
5683     { Bad_Opcode },
5684     { VEX_W_TABLE (VEX_W_0F380B_P_2) },
5685   },
5686
5687   /* PREFIX_VEX_0F380C */
5688   {
5689     { Bad_Opcode },
5690     { Bad_Opcode },
5691     { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5692   },
5693
5694   /* PREFIX_VEX_0F380D */
5695   {
5696     { Bad_Opcode },
5697     { Bad_Opcode },
5698     { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5699   },
5700
5701   /* PREFIX_VEX_0F380E */
5702   {
5703     { Bad_Opcode },
5704     { Bad_Opcode },
5705     { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5706   },
5707
5708   /* PREFIX_VEX_0F380F */
5709   {
5710     { Bad_Opcode },
5711     { Bad_Opcode },
5712     { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5713   },
5714
5715   /* PREFIX_VEX_0F3813 */
5716   {
5717     { Bad_Opcode },
5718     { Bad_Opcode },
5719     { "vcvtph2ps", { XM, EXxmmq }, 0 },
5720   },
5721
5722   /* PREFIX_VEX_0F3816 */
5723   {
5724     { Bad_Opcode },
5725     { Bad_Opcode },
5726     { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5727   },
5728
5729   /* PREFIX_VEX_0F3817 */
5730   {
5731     { Bad_Opcode },
5732     { Bad_Opcode },
5733     { VEX_W_TABLE (VEX_W_0F3817_P_2) },
5734   },
5735
5736   /* PREFIX_VEX_0F3818 */
5737   {
5738     { Bad_Opcode },
5739     { Bad_Opcode },
5740     { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5741   },
5742
5743   /* PREFIX_VEX_0F3819 */
5744   {
5745     { Bad_Opcode },
5746     { Bad_Opcode },
5747     { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5748   },
5749
5750   /* PREFIX_VEX_0F381A */
5751   {
5752     { Bad_Opcode },
5753     { Bad_Opcode },
5754     { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5755   },
5756
5757   /* PREFIX_VEX_0F381C */
5758   {
5759     { Bad_Opcode },
5760     { Bad_Opcode },
5761     { VEX_W_TABLE (VEX_W_0F381C_P_2) },
5762   },
5763
5764   /* PREFIX_VEX_0F381D */
5765   {
5766     { Bad_Opcode },
5767     { Bad_Opcode },
5768     { VEX_W_TABLE (VEX_W_0F381D_P_2) },
5769   },
5770
5771   /* PREFIX_VEX_0F381E */
5772   {
5773     { Bad_Opcode },
5774     { Bad_Opcode },
5775     { VEX_W_TABLE (VEX_W_0F381E_P_2) },
5776   },
5777
5778   /* PREFIX_VEX_0F3820 */
5779   {
5780     { Bad_Opcode },
5781     { Bad_Opcode },
5782     { VEX_W_TABLE (VEX_W_0F3820_P_2) },
5783   },
5784
5785   /* PREFIX_VEX_0F3821 */
5786   {
5787     { Bad_Opcode },
5788     { Bad_Opcode },
5789     { VEX_W_TABLE (VEX_W_0F3821_P_2) },
5790   },
5791
5792   /* PREFIX_VEX_0F3822 */
5793   {
5794     { Bad_Opcode },
5795     { Bad_Opcode },
5796     { VEX_W_TABLE (VEX_W_0F3822_P_2) },
5797   },
5798
5799   /* PREFIX_VEX_0F3823 */
5800   {
5801     { Bad_Opcode },
5802     { Bad_Opcode },
5803     { VEX_W_TABLE (VEX_W_0F3823_P_2) },
5804   },
5805
5806   /* PREFIX_VEX_0F3824 */
5807   {
5808     { Bad_Opcode },
5809     { Bad_Opcode },
5810     { VEX_W_TABLE (VEX_W_0F3824_P_2) },
5811   },
5812
5813   /* PREFIX_VEX_0F3825 */
5814   {
5815     { Bad_Opcode },
5816     { Bad_Opcode },
5817     { VEX_W_TABLE (VEX_W_0F3825_P_2) },
5818   },
5819
5820   /* PREFIX_VEX_0F3828 */
5821   {
5822     { Bad_Opcode },
5823     { Bad_Opcode },
5824     { VEX_W_TABLE (VEX_W_0F3828_P_2) },
5825   },
5826
5827   /* PREFIX_VEX_0F3829 */
5828   {
5829     { Bad_Opcode },
5830     { Bad_Opcode },
5831     { VEX_W_TABLE (VEX_W_0F3829_P_2) },
5832   },
5833
5834   /* PREFIX_VEX_0F382A */
5835   {
5836     { Bad_Opcode },
5837     { Bad_Opcode },
5838     { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5839   },
5840
5841   /* PREFIX_VEX_0F382B */
5842   {
5843     { Bad_Opcode },
5844     { Bad_Opcode },
5845     { VEX_W_TABLE (VEX_W_0F382B_P_2) },
5846   },
5847
5848   /* PREFIX_VEX_0F382C */
5849   {
5850     { Bad_Opcode },
5851     { Bad_Opcode },
5852      { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5853   },
5854
5855   /* PREFIX_VEX_0F382D */
5856   {
5857     { Bad_Opcode },
5858     { Bad_Opcode },
5859      { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5860   },
5861
5862   /* PREFIX_VEX_0F382E */
5863   {
5864     { Bad_Opcode },
5865     { Bad_Opcode },
5866      { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5867   },
5868
5869   /* PREFIX_VEX_0F382F */
5870   {
5871     { Bad_Opcode },
5872     { Bad_Opcode },
5873      { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5874   },
5875
5876   /* PREFIX_VEX_0F3830 */
5877   {
5878     { Bad_Opcode },
5879     { Bad_Opcode },
5880     { VEX_W_TABLE (VEX_W_0F3830_P_2) },
5881   },
5882
5883   /* PREFIX_VEX_0F3831 */
5884   {
5885     { Bad_Opcode },
5886     { Bad_Opcode },
5887     { VEX_W_TABLE (VEX_W_0F3831_P_2) },
5888   },
5889
5890   /* PREFIX_VEX_0F3832 */
5891   {
5892     { Bad_Opcode },
5893     { Bad_Opcode },
5894     { VEX_W_TABLE (VEX_W_0F3832_P_2) },
5895   },
5896
5897   /* PREFIX_VEX_0F3833 */
5898   {
5899     { Bad_Opcode },
5900     { Bad_Opcode },
5901     { VEX_W_TABLE (VEX_W_0F3833_P_2) },
5902   },
5903
5904   /* PREFIX_VEX_0F3834 */
5905   {
5906     { Bad_Opcode },
5907     { Bad_Opcode },
5908     { VEX_W_TABLE (VEX_W_0F3834_P_2) },
5909   },
5910
5911   /* PREFIX_VEX_0F3835 */
5912   {
5913     { Bad_Opcode },
5914     { Bad_Opcode },
5915     { VEX_W_TABLE (VEX_W_0F3835_P_2) },
5916   },
5917
5918   /* PREFIX_VEX_0F3836 */
5919   {
5920     { Bad_Opcode },
5921     { Bad_Opcode },
5922     { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5923   },
5924
5925   /* PREFIX_VEX_0F3837 */
5926   {
5927     { Bad_Opcode },
5928     { Bad_Opcode },
5929     { VEX_W_TABLE (VEX_W_0F3837_P_2) },
5930   },
5931
5932   /* PREFIX_VEX_0F3838 */
5933   {
5934     { Bad_Opcode },
5935     { Bad_Opcode },
5936     { VEX_W_TABLE (VEX_W_0F3838_P_2) },
5937   },
5938
5939   /* PREFIX_VEX_0F3839 */
5940   {
5941     { Bad_Opcode },
5942     { Bad_Opcode },
5943     { VEX_W_TABLE (VEX_W_0F3839_P_2) },
5944   },
5945
5946   /* PREFIX_VEX_0F383A */
5947   {
5948     { Bad_Opcode },
5949     { Bad_Opcode },
5950     { VEX_W_TABLE (VEX_W_0F383A_P_2) },
5951   },
5952
5953   /* PREFIX_VEX_0F383B */
5954   {
5955     { Bad_Opcode },
5956     { Bad_Opcode },
5957     { VEX_W_TABLE (VEX_W_0F383B_P_2) },
5958   },
5959
5960   /* PREFIX_VEX_0F383C */
5961   {
5962     { Bad_Opcode },
5963     { Bad_Opcode },
5964     { VEX_W_TABLE (VEX_W_0F383C_P_2) },
5965   },
5966
5967   /* PREFIX_VEX_0F383D */
5968   {
5969     { Bad_Opcode },
5970     { Bad_Opcode },
5971     { VEX_W_TABLE (VEX_W_0F383D_P_2) },
5972   },
5973
5974   /* PREFIX_VEX_0F383E */
5975   {
5976     { Bad_Opcode },
5977     { Bad_Opcode },
5978     { VEX_W_TABLE (VEX_W_0F383E_P_2) },
5979   },
5980
5981   /* PREFIX_VEX_0F383F */
5982   {
5983     { Bad_Opcode },
5984     { Bad_Opcode },
5985     { VEX_W_TABLE (VEX_W_0F383F_P_2) },
5986   },
5987
5988   /* PREFIX_VEX_0F3840 */
5989   {
5990     { Bad_Opcode },
5991     { Bad_Opcode },
5992     { VEX_W_TABLE (VEX_W_0F3840_P_2) },
5993   },
5994
5995   /* PREFIX_VEX_0F3841 */
5996   {
5997     { Bad_Opcode },
5998     { Bad_Opcode },
5999     { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
6000   },
6001
6002   /* PREFIX_VEX_0F3845 */
6003   {
6004     { Bad_Opcode },
6005     { Bad_Opcode },
6006     { "vpsrlv%LW", { XM, Vex, EXx }, 0 },
6007   },
6008
6009   /* PREFIX_VEX_0F3846 */
6010   {
6011     { Bad_Opcode },
6012     { Bad_Opcode },
6013     { VEX_W_TABLE (VEX_W_0F3846_P_2) },
6014   },
6015
6016   /* PREFIX_VEX_0F3847 */
6017   {
6018     { Bad_Opcode },
6019     { Bad_Opcode },
6020     { "vpsllv%LW", { XM, Vex, EXx }, 0 },
6021   },
6022
6023   /* PREFIX_VEX_0F3858 */
6024   {
6025     { Bad_Opcode },
6026     { Bad_Opcode },
6027     { VEX_W_TABLE (VEX_W_0F3858_P_2) },
6028   },
6029
6030   /* PREFIX_VEX_0F3859 */
6031   {
6032     { Bad_Opcode },
6033     { Bad_Opcode },
6034     { VEX_W_TABLE (VEX_W_0F3859_P_2) },
6035   },
6036
6037   /* PREFIX_VEX_0F385A */
6038   {
6039     { Bad_Opcode },
6040     { Bad_Opcode },
6041     { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
6042   },
6043
6044   /* PREFIX_VEX_0F3878 */
6045   {
6046     { Bad_Opcode },
6047     { Bad_Opcode },
6048     { VEX_W_TABLE (VEX_W_0F3878_P_2) },
6049   },
6050
6051   /* PREFIX_VEX_0F3879 */
6052   {
6053     { Bad_Opcode },
6054     { Bad_Opcode },
6055     { VEX_W_TABLE (VEX_W_0F3879_P_2) },
6056   },
6057
6058   /* PREFIX_VEX_0F388C */
6059   {
6060     { Bad_Opcode },
6061     { Bad_Opcode },
6062     { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
6063   },
6064
6065   /* PREFIX_VEX_0F388E */
6066   {
6067     { Bad_Opcode },
6068     { Bad_Opcode },
6069     { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
6070   },
6071
6072   /* PREFIX_VEX_0F3890 */
6073   {
6074     { Bad_Opcode },
6075     { Bad_Opcode },
6076     { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 },
6077   },
6078
6079   /* PREFIX_VEX_0F3891 */
6080   {
6081     { Bad_Opcode },
6082     { Bad_Opcode },
6083     { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6084   },
6085
6086   /* PREFIX_VEX_0F3892 */
6087   {
6088     { Bad_Opcode },
6089     { Bad_Opcode },
6090     { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 },
6091   },
6092
6093   /* PREFIX_VEX_0F3893 */
6094   {
6095     { Bad_Opcode },
6096     { Bad_Opcode },
6097     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6098   },
6099
6100   /* PREFIX_VEX_0F3896 */
6101   {
6102     { Bad_Opcode },
6103     { Bad_Opcode },
6104     { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 },
6105   },
6106
6107   /* PREFIX_VEX_0F3897 */
6108   {
6109     { Bad_Opcode },
6110     { Bad_Opcode },
6111     { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 },
6112   },
6113
6114   /* PREFIX_VEX_0F3898 */
6115   {
6116     { Bad_Opcode },
6117     { Bad_Opcode },
6118     { "vfmadd132p%XW", { XM, Vex, EXx }, 0 },
6119   },
6120
6121   /* PREFIX_VEX_0F3899 */
6122   {
6123     { Bad_Opcode },
6124     { Bad_Opcode },
6125     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6126   },
6127
6128   /* PREFIX_VEX_0F389A */
6129   {
6130     { Bad_Opcode },
6131     { Bad_Opcode },
6132     { "vfmsub132p%XW", { XM, Vex, EXx }, 0 },
6133   },
6134
6135   /* PREFIX_VEX_0F389B */
6136   {
6137     { Bad_Opcode },
6138     { Bad_Opcode },
6139     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6140   },
6141
6142   /* PREFIX_VEX_0F389C */
6143   {
6144     { Bad_Opcode },
6145     { Bad_Opcode },
6146     { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 },
6147   },
6148
6149   /* PREFIX_VEX_0F389D */
6150   {
6151     { Bad_Opcode },
6152     { Bad_Opcode },
6153     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6154   },
6155
6156   /* PREFIX_VEX_0F389E */
6157   {
6158     { Bad_Opcode },
6159     { Bad_Opcode },
6160     { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 },
6161   },
6162
6163   /* PREFIX_VEX_0F389F */
6164   {
6165     { Bad_Opcode },
6166     { Bad_Opcode },
6167     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6168   },
6169
6170   /* PREFIX_VEX_0F38A6 */
6171   {
6172     { Bad_Opcode },
6173     { Bad_Opcode },
6174     { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 },
6175     { Bad_Opcode },
6176   },
6177
6178   /* PREFIX_VEX_0F38A7 */
6179   {
6180     { Bad_Opcode },
6181     { Bad_Opcode },
6182     { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 },
6183   },
6184
6185   /* PREFIX_VEX_0F38A8 */
6186   {
6187     { Bad_Opcode },
6188     { Bad_Opcode },
6189     { "vfmadd213p%XW", { XM, Vex, EXx }, 0 },
6190   },
6191
6192   /* PREFIX_VEX_0F38A9 */
6193   {
6194     { Bad_Opcode },
6195     { Bad_Opcode },
6196     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6197   },
6198
6199   /* PREFIX_VEX_0F38AA */
6200   {
6201     { Bad_Opcode },
6202     { Bad_Opcode },
6203     { "vfmsub213p%XW", { XM, Vex, EXx }, 0 },
6204   },
6205
6206   /* PREFIX_VEX_0F38AB */
6207   {
6208     { Bad_Opcode },
6209     { Bad_Opcode },
6210     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6211   },
6212
6213   /* PREFIX_VEX_0F38AC */
6214   {
6215     { Bad_Opcode },
6216     { Bad_Opcode },
6217     { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 },
6218   },
6219
6220   /* PREFIX_VEX_0F38AD */
6221   {
6222     { Bad_Opcode },
6223     { Bad_Opcode },
6224     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6225   },
6226
6227   /* PREFIX_VEX_0F38AE */
6228   {
6229     { Bad_Opcode },
6230     { Bad_Opcode },
6231     { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 },
6232   },
6233
6234   /* PREFIX_VEX_0F38AF */
6235   {
6236     { Bad_Opcode },
6237     { Bad_Opcode },
6238     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6239   },
6240
6241   /* PREFIX_VEX_0F38B6 */
6242   {
6243     { Bad_Opcode },
6244     { Bad_Opcode },
6245     { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 },
6246   },
6247
6248   /* PREFIX_VEX_0F38B7 */
6249   {
6250     { Bad_Opcode },
6251     { Bad_Opcode },
6252     { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 },
6253   },
6254
6255   /* PREFIX_VEX_0F38B8 */
6256   {
6257     { Bad_Opcode },
6258     { Bad_Opcode },
6259     { "vfmadd231p%XW", { XM, Vex, EXx }, 0 },
6260   },
6261
6262   /* PREFIX_VEX_0F38B9 */
6263   {
6264     { Bad_Opcode },
6265     { Bad_Opcode },
6266     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6267   },
6268
6269   /* PREFIX_VEX_0F38BA */
6270   {
6271     { Bad_Opcode },
6272     { Bad_Opcode },
6273     { "vfmsub231p%XW", { XM, Vex, EXx }, 0 },
6274   },
6275
6276   /* PREFIX_VEX_0F38BB */
6277   {
6278     { Bad_Opcode },
6279     { Bad_Opcode },
6280     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6281   },
6282
6283   /* PREFIX_VEX_0F38BC */
6284   {
6285     { Bad_Opcode },
6286     { Bad_Opcode },
6287     { "vfnmadd231p%XW", { XM, Vex, EXx }, 0 },
6288   },
6289
6290   /* PREFIX_VEX_0F38BD */
6291   {
6292     { Bad_Opcode },
6293     { Bad_Opcode },
6294     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6295   },
6296
6297   /* PREFIX_VEX_0F38BE */
6298   {
6299     { Bad_Opcode },
6300     { Bad_Opcode },
6301     { "vfnmsub231p%XW", { XM, Vex, EXx }, 0 },
6302   },
6303
6304   /* PREFIX_VEX_0F38BF */
6305   {
6306     { Bad_Opcode },
6307     { Bad_Opcode },
6308     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6309   },
6310
6311   /* PREFIX_VEX_0F38DB */
6312   {
6313     { Bad_Opcode },
6314     { Bad_Opcode },
6315     { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6316   },
6317
6318   /* PREFIX_VEX_0F38DC */
6319   {
6320     { Bad_Opcode },
6321     { Bad_Opcode },
6322     { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2) },
6323   },
6324
6325   /* PREFIX_VEX_0F38DD */
6326   {
6327     { Bad_Opcode },
6328     { Bad_Opcode },
6329     { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2) },
6330   },
6331
6332   /* PREFIX_VEX_0F38DE */
6333   {
6334     { Bad_Opcode },
6335     { Bad_Opcode },
6336     { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2) },
6337   },
6338
6339   /* PREFIX_VEX_0F38DF */
6340   {
6341     { Bad_Opcode },
6342     { Bad_Opcode },
6343     { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2) },
6344   },
6345
6346   /* PREFIX_VEX_0F38F2 */
6347   {
6348     { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6349   },
6350
6351   /* PREFIX_VEX_0F38F3_REG_1 */
6352   {
6353     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6354   },
6355
6356   /* PREFIX_VEX_0F38F3_REG_2 */
6357   {
6358     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6359   },
6360
6361   /* PREFIX_VEX_0F38F3_REG_3 */
6362   {
6363     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6364   },
6365
6366   /* PREFIX_VEX_0F38F5 */
6367   {
6368     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6369     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6370     { Bad_Opcode },
6371     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6372   },
6373
6374   /* PREFIX_VEX_0F38F6 */
6375   {
6376     { Bad_Opcode },
6377     { Bad_Opcode },
6378     { Bad_Opcode },
6379     { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6380   },
6381
6382   /* PREFIX_VEX_0F38F7 */
6383   {
6384     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6385     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6386     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6387     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6388   },
6389
6390   /* PREFIX_VEX_0F3A00 */
6391   {
6392     { Bad_Opcode },
6393     { Bad_Opcode },
6394     { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6395   },
6396
6397   /* PREFIX_VEX_0F3A01 */
6398   {
6399     { Bad_Opcode },
6400     { Bad_Opcode },
6401     { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6402   },
6403
6404   /* PREFIX_VEX_0F3A02 */
6405   {
6406     { Bad_Opcode },
6407     { Bad_Opcode },
6408     { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6409   },
6410
6411   /* PREFIX_VEX_0F3A04 */
6412   {
6413     { Bad_Opcode },
6414     { Bad_Opcode },
6415     { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6416   },
6417
6418   /* PREFIX_VEX_0F3A05 */
6419   {
6420     { Bad_Opcode },
6421     { Bad_Opcode },
6422     { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6423   },
6424
6425   /* PREFIX_VEX_0F3A06 */
6426   {
6427     { Bad_Opcode },
6428     { Bad_Opcode },
6429     { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6430   },
6431
6432   /* PREFIX_VEX_0F3A08 */
6433   {
6434     { Bad_Opcode },
6435     { Bad_Opcode },
6436     { VEX_W_TABLE (VEX_W_0F3A08_P_2) },
6437   },
6438
6439   /* PREFIX_VEX_0F3A09 */
6440   {
6441     { Bad_Opcode },
6442     { Bad_Opcode },
6443     { VEX_W_TABLE (VEX_W_0F3A09_P_2) },
6444   },
6445
6446   /* PREFIX_VEX_0F3A0A */
6447   {
6448     { Bad_Opcode },
6449     { Bad_Opcode },
6450     { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) },
6451   },
6452
6453   /* PREFIX_VEX_0F3A0B */
6454   {
6455     { Bad_Opcode },
6456     { Bad_Opcode },
6457     { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) },
6458   },
6459
6460   /* PREFIX_VEX_0F3A0C */
6461   {
6462     { Bad_Opcode },
6463     { Bad_Opcode },
6464     { VEX_W_TABLE (VEX_W_0F3A0C_P_2) },
6465   },
6466
6467   /* PREFIX_VEX_0F3A0D */
6468   {
6469     { Bad_Opcode },
6470     { Bad_Opcode },
6471     { VEX_W_TABLE (VEX_W_0F3A0D_P_2) },
6472   },
6473
6474   /* PREFIX_VEX_0F3A0E */
6475   {
6476     { Bad_Opcode },
6477     { Bad_Opcode },
6478     { VEX_W_TABLE (VEX_W_0F3A0E_P_2) },
6479   },
6480
6481   /* PREFIX_VEX_0F3A0F */
6482   {
6483     { Bad_Opcode },
6484     { Bad_Opcode },
6485     { VEX_W_TABLE (VEX_W_0F3A0F_P_2) },
6486   },
6487
6488   /* PREFIX_VEX_0F3A14 */
6489   {
6490     { Bad_Opcode },
6491     { Bad_Opcode },
6492     { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6493   },
6494
6495   /* PREFIX_VEX_0F3A15 */
6496   {
6497     { Bad_Opcode },
6498     { Bad_Opcode },
6499     { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6500   },
6501
6502   /* PREFIX_VEX_0F3A16 */
6503   {
6504     { Bad_Opcode },
6505     { Bad_Opcode },
6506     { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6507   },
6508
6509   /* PREFIX_VEX_0F3A17 */
6510   {
6511     { Bad_Opcode },
6512     { Bad_Opcode },
6513     { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6514   },
6515
6516   /* PREFIX_VEX_0F3A18 */
6517   {
6518     { Bad_Opcode },
6519     { Bad_Opcode },
6520     { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6521   },
6522
6523   /* PREFIX_VEX_0F3A19 */
6524   {
6525     { Bad_Opcode },
6526     { Bad_Opcode },
6527     { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6528   },
6529
6530   /* PREFIX_VEX_0F3A1D */
6531   {
6532     { Bad_Opcode },
6533     { Bad_Opcode },
6534     { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 },
6535   },
6536
6537   /* PREFIX_VEX_0F3A20 */
6538   {
6539     { Bad_Opcode },
6540     { Bad_Opcode },
6541     { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6542   },
6543
6544   /* PREFIX_VEX_0F3A21 */
6545   {
6546     { Bad_Opcode },
6547     { Bad_Opcode },
6548     { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6549   },
6550
6551   /* PREFIX_VEX_0F3A22 */
6552   {
6553     { Bad_Opcode },
6554     { Bad_Opcode },
6555     { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6556   },
6557
6558   /* PREFIX_VEX_0F3A30 */
6559   {
6560     { Bad_Opcode },
6561     { Bad_Opcode },
6562     { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6563   },
6564
6565   /* PREFIX_VEX_0F3A31 */
6566   {
6567     { Bad_Opcode },
6568     { Bad_Opcode },
6569     { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6570   },
6571
6572   /* PREFIX_VEX_0F3A32 */
6573   {
6574     { Bad_Opcode },
6575     { Bad_Opcode },
6576     { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6577   },
6578
6579   /* PREFIX_VEX_0F3A33 */
6580   {
6581     { Bad_Opcode },
6582     { Bad_Opcode },
6583     { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6584   },
6585
6586   /* PREFIX_VEX_0F3A38 */
6587   {
6588     { Bad_Opcode },
6589     { Bad_Opcode },
6590     { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6591   },
6592
6593   /* PREFIX_VEX_0F3A39 */
6594   {
6595     { Bad_Opcode },
6596     { Bad_Opcode },
6597     { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6598   },
6599
6600   /* PREFIX_VEX_0F3A40 */
6601   {
6602     { Bad_Opcode },
6603     { Bad_Opcode },
6604     { VEX_W_TABLE (VEX_W_0F3A40_P_2) },
6605   },
6606
6607   /* PREFIX_VEX_0F3A41 */
6608   {
6609     { Bad_Opcode },
6610     { Bad_Opcode },
6611     { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6612   },
6613
6614   /* PREFIX_VEX_0F3A42 */
6615   {
6616     { Bad_Opcode },
6617     { Bad_Opcode },
6618     { VEX_W_TABLE (VEX_W_0F3A42_P_2) },
6619   },
6620
6621   /* PREFIX_VEX_0F3A44 */
6622   {
6623     { Bad_Opcode },
6624     { Bad_Opcode },
6625     { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2) },
6626   },
6627
6628   /* PREFIX_VEX_0F3A46 */
6629   {
6630     { Bad_Opcode },
6631     { Bad_Opcode },
6632     { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6633   },
6634
6635   /* PREFIX_VEX_0F3A48 */
6636   {
6637     { Bad_Opcode },
6638     { Bad_Opcode },
6639     { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6640   },
6641
6642   /* PREFIX_VEX_0F3A49 */
6643   {
6644     { Bad_Opcode },
6645     { Bad_Opcode },
6646     { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6647   },
6648
6649   /* PREFIX_VEX_0F3A4A */
6650   {
6651     { Bad_Opcode },
6652     { Bad_Opcode },
6653     { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6654   },
6655
6656   /* PREFIX_VEX_0F3A4B */
6657   {
6658     { Bad_Opcode },
6659     { Bad_Opcode },
6660     { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6661   },
6662
6663   /* PREFIX_VEX_0F3A4C */
6664   {
6665     { Bad_Opcode },
6666     { Bad_Opcode },
6667     { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6668   },
6669
6670   /* PREFIX_VEX_0F3A5C */
6671   {
6672     { Bad_Opcode },
6673     { Bad_Opcode },
6674     { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6675   },
6676
6677   /* PREFIX_VEX_0F3A5D */
6678   {
6679     { Bad_Opcode },
6680     { Bad_Opcode },
6681     { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6682   },
6683
6684   /* PREFIX_VEX_0F3A5E */
6685   {
6686     { Bad_Opcode },
6687     { Bad_Opcode },
6688     { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6689   },
6690
6691   /* PREFIX_VEX_0F3A5F */
6692   {
6693     { Bad_Opcode },
6694     { Bad_Opcode },
6695     { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6696   },
6697
6698   /* PREFIX_VEX_0F3A60 */
6699   {
6700     { Bad_Opcode },
6701     { Bad_Opcode },
6702     { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6703     { Bad_Opcode },
6704   },
6705
6706   /* PREFIX_VEX_0F3A61 */
6707   {
6708     { Bad_Opcode },
6709     { Bad_Opcode },
6710     { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6711   },
6712
6713   /* PREFIX_VEX_0F3A62 */
6714   {
6715     { Bad_Opcode },
6716     { Bad_Opcode },
6717     { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6718   },
6719
6720   /* PREFIX_VEX_0F3A63 */
6721   {
6722     { Bad_Opcode },
6723     { Bad_Opcode },
6724     { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6725   },
6726
6727   /* PREFIX_VEX_0F3A68 */
6728   {
6729     { Bad_Opcode },
6730     { Bad_Opcode },
6731     { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6732   },
6733
6734   /* PREFIX_VEX_0F3A69 */
6735   {
6736     { Bad_Opcode },
6737     { Bad_Opcode },
6738     { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6739   },
6740
6741   /* PREFIX_VEX_0F3A6A */
6742   {
6743     { Bad_Opcode },
6744     { Bad_Opcode },
6745     { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6746   },
6747
6748   /* PREFIX_VEX_0F3A6B */
6749   {
6750     { Bad_Opcode },
6751     { Bad_Opcode },
6752     { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6753   },
6754
6755   /* PREFIX_VEX_0F3A6C */
6756   {
6757     { Bad_Opcode },
6758     { Bad_Opcode },
6759     { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6760   },
6761
6762   /* PREFIX_VEX_0F3A6D */
6763   {
6764     { Bad_Opcode },
6765     { Bad_Opcode },
6766     { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6767   },
6768
6769   /* PREFIX_VEX_0F3A6E */
6770   {
6771     { Bad_Opcode },
6772     { Bad_Opcode },
6773     { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6774   },
6775
6776   /* PREFIX_VEX_0F3A6F */
6777   {
6778     { Bad_Opcode },
6779     { Bad_Opcode },
6780     { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6781   },
6782
6783   /* PREFIX_VEX_0F3A78 */
6784   {
6785     { Bad_Opcode },
6786     { Bad_Opcode },
6787     { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6788   },
6789
6790   /* PREFIX_VEX_0F3A79 */
6791   {
6792     { Bad_Opcode },
6793     { Bad_Opcode },
6794     { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6795   },
6796
6797   /* PREFIX_VEX_0F3A7A */
6798   {
6799     { Bad_Opcode },
6800     { Bad_Opcode },
6801     { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6802   },
6803
6804   /* PREFIX_VEX_0F3A7B */
6805   {
6806     { Bad_Opcode },
6807     { Bad_Opcode },
6808     { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6809   },
6810
6811   /* PREFIX_VEX_0F3A7C */
6812   {
6813     { Bad_Opcode },
6814     { Bad_Opcode },
6815     { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6816     { Bad_Opcode },
6817   },
6818
6819   /* PREFIX_VEX_0F3A7D */
6820   {
6821     { Bad_Opcode },
6822     { Bad_Opcode },
6823     { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6824   },
6825
6826   /* PREFIX_VEX_0F3A7E */
6827   {
6828     { Bad_Opcode },
6829     { Bad_Opcode },
6830     { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6831   },
6832
6833   /* PREFIX_VEX_0F3A7F */
6834   {
6835     { Bad_Opcode },
6836     { Bad_Opcode },
6837     { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6838   },
6839
6840   /* PREFIX_VEX_0F3ADF */
6841   {
6842     { Bad_Opcode },
6843     { Bad_Opcode },
6844     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6845   },
6846
6847   /* PREFIX_VEX_0F3AF0 */
6848   {
6849     { Bad_Opcode },
6850     { Bad_Opcode },
6851     { Bad_Opcode },
6852     { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6853   },
6854
6855 #define NEED_PREFIX_TABLE
6856 #include "i386-dis-evex.h"
6857 #undef NEED_PREFIX_TABLE
6858 };
6859
6860 static const struct dis386 x86_64_table[][2] = {
6861   /* X86_64_06 */
6862   {
6863     { "pushP", { es }, 0 },
6864   },
6865
6866   /* X86_64_07 */
6867   {
6868     { "popP", { es }, 0 },
6869   },
6870
6871   /* X86_64_0D */
6872   {
6873     { "pushP", { cs }, 0 },
6874   },
6875
6876   /* X86_64_16 */
6877   {
6878     { "pushP", { ss }, 0 },
6879   },
6880
6881   /* X86_64_17 */
6882   {
6883     { "popP", { ss }, 0 },
6884   },
6885
6886   /* X86_64_1E */
6887   {
6888     { "pushP", { ds }, 0 },
6889   },
6890
6891   /* X86_64_1F */
6892   {
6893     { "popP", { ds }, 0 },
6894   },
6895
6896   /* X86_64_27 */
6897   {
6898     { "daa", { XX }, 0 },
6899   },
6900
6901   /* X86_64_2F */
6902   {
6903     { "das", { XX }, 0 },
6904   },
6905
6906   /* X86_64_37 */
6907   {
6908     { "aaa", { XX }, 0 },
6909   },
6910
6911   /* X86_64_3F */
6912   {
6913     { "aas", { XX }, 0 },
6914   },
6915
6916   /* X86_64_60 */
6917   {
6918     { "pushaP", { XX }, 0 },
6919   },
6920
6921   /* X86_64_61 */
6922   {
6923     { "popaP", { XX }, 0 },
6924   },
6925
6926   /* X86_64_62 */
6927   {
6928     { MOD_TABLE (MOD_62_32BIT) },
6929     { EVEX_TABLE (EVEX_0F) },
6930   },
6931
6932   /* X86_64_63 */
6933   {
6934     { "arpl", { Ew, Gw }, 0 },
6935     { "movs{lq|xd}", { Gv, Ed }, 0 },
6936   },
6937
6938   /* X86_64_6D */
6939   {
6940     { "ins{R|}", { Yzr, indirDX }, 0 },
6941     { "ins{G|}", { Yzr, indirDX }, 0 },
6942   },
6943
6944   /* X86_64_6F */
6945   {
6946     { "outs{R|}", { indirDXr, Xz }, 0 },
6947     { "outs{G|}", { indirDXr, Xz }, 0 },
6948   },
6949
6950   /* X86_64_82 */
6951   {
6952     /* Opcode 0x82 is an alias of of opcode 0x80 in 32-bit mode.  */
6953     { REG_TABLE (REG_80) },
6954   },
6955
6956   /* X86_64_9A */
6957   {
6958     { "Jcall{T|}", { Ap }, 0 },
6959   },
6960
6961   /* X86_64_C4 */
6962   {
6963     { MOD_TABLE (MOD_C4_32BIT) },
6964     { VEX_C4_TABLE (VEX_0F) },
6965   },
6966
6967   /* X86_64_C5 */
6968   {
6969     { MOD_TABLE (MOD_C5_32BIT) },
6970     { VEX_C5_TABLE (VEX_0F) },
6971   },
6972
6973   /* X86_64_CE */
6974   {
6975     { "into", { XX }, 0 },
6976   },
6977
6978   /* X86_64_D4 */
6979   {
6980     { "aam", { Ib }, 0 },
6981   },
6982
6983   /* X86_64_D5 */
6984   {
6985     { "aad", { Ib }, 0 },
6986   },
6987
6988   /* X86_64_E8 */
6989   {
6990     { "callP",          { Jv, BND }, 0 },
6991     { "call@",          { Jv, BND }, 0 }
6992   },
6993
6994   /* X86_64_E9 */
6995   {
6996     { "jmpP",           { Jv, BND }, 0 },
6997     { "jmp@",           { Jv, BND }, 0 }
6998   },
6999
7000   /* X86_64_EA */
7001   {
7002     { "Jjmp{T|}", { Ap }, 0 },
7003   },
7004
7005   /* X86_64_0F01_REG_0 */
7006   {
7007     { "sgdt{Q|IQ}", { M }, 0 },
7008     { "sgdt", { M }, 0 },
7009   },
7010
7011   /* X86_64_0F01_REG_1 */
7012   {
7013     { "sidt{Q|IQ}", { M }, 0 },
7014     { "sidt", { M }, 0 },
7015   },
7016
7017   /* X86_64_0F01_REG_2 */
7018   {
7019     { "lgdt{Q|Q}", { M }, 0 },
7020     { "lgdt", { M }, 0 },
7021   },
7022
7023   /* X86_64_0F01_REG_3 */
7024   {
7025     { "lidt{Q|Q}", { M }, 0 },
7026     { "lidt", { M }, 0 },
7027   },
7028 };
7029
7030 static const struct dis386 three_byte_table[][256] = {
7031
7032   /* THREE_BYTE_0F38 */
7033   {
7034     /* 00 */
7035     { "pshufb",         { MX, EM }, PREFIX_OPCODE },
7036     { "phaddw",         { MX, EM }, PREFIX_OPCODE },
7037     { "phaddd",         { MX, EM }, PREFIX_OPCODE },
7038     { "phaddsw",        { MX, EM }, PREFIX_OPCODE },
7039     { "pmaddubsw",      { MX, EM }, PREFIX_OPCODE },
7040     { "phsubw",         { MX, EM }, PREFIX_OPCODE },
7041     { "phsubd",         { MX, EM }, PREFIX_OPCODE },
7042     { "phsubsw",        { MX, EM }, PREFIX_OPCODE },
7043     /* 08 */
7044     { "psignb",         { MX, EM }, PREFIX_OPCODE },
7045     { "psignw",         { MX, EM }, PREFIX_OPCODE },
7046     { "psignd",         { MX, EM }, PREFIX_OPCODE },
7047     { "pmulhrsw",       { MX, EM }, PREFIX_OPCODE },
7048     { Bad_Opcode },
7049     { Bad_Opcode },
7050     { Bad_Opcode },
7051     { Bad_Opcode },
7052     /* 10 */
7053     { PREFIX_TABLE (PREFIX_0F3810) },
7054     { Bad_Opcode },
7055     { Bad_Opcode },
7056     { Bad_Opcode },
7057     { PREFIX_TABLE (PREFIX_0F3814) },
7058     { PREFIX_TABLE (PREFIX_0F3815) },
7059     { Bad_Opcode },
7060     { PREFIX_TABLE (PREFIX_0F3817) },
7061     /* 18 */
7062     { Bad_Opcode },
7063     { Bad_Opcode },
7064     { Bad_Opcode },
7065     { Bad_Opcode },
7066     { "pabsb",          { MX, EM }, PREFIX_OPCODE },
7067     { "pabsw",          { MX, EM }, PREFIX_OPCODE },
7068     { "pabsd",          { MX, EM }, PREFIX_OPCODE },
7069     { Bad_Opcode },
7070     /* 20 */
7071     { PREFIX_TABLE (PREFIX_0F3820) },
7072     { PREFIX_TABLE (PREFIX_0F3821) },
7073     { PREFIX_TABLE (PREFIX_0F3822) },
7074     { PREFIX_TABLE (PREFIX_0F3823) },
7075     { PREFIX_TABLE (PREFIX_0F3824) },
7076     { PREFIX_TABLE (PREFIX_0F3825) },
7077     { Bad_Opcode },
7078     { Bad_Opcode },
7079     /* 28 */
7080     { PREFIX_TABLE (PREFIX_0F3828) },
7081     { PREFIX_TABLE (PREFIX_0F3829) },
7082     { PREFIX_TABLE (PREFIX_0F382A) },
7083     { PREFIX_TABLE (PREFIX_0F382B) },
7084     { Bad_Opcode },
7085     { Bad_Opcode },
7086     { Bad_Opcode },
7087     { Bad_Opcode },
7088     /* 30 */
7089     { PREFIX_TABLE (PREFIX_0F3830) },
7090     { PREFIX_TABLE (PREFIX_0F3831) },
7091     { PREFIX_TABLE (PREFIX_0F3832) },
7092     { PREFIX_TABLE (PREFIX_0F3833) },
7093     { PREFIX_TABLE (PREFIX_0F3834) },
7094     { PREFIX_TABLE (PREFIX_0F3835) },
7095     { Bad_Opcode },
7096     { PREFIX_TABLE (PREFIX_0F3837) },
7097     /* 38 */
7098     { PREFIX_TABLE (PREFIX_0F3838) },
7099     { PREFIX_TABLE (PREFIX_0F3839) },
7100     { PREFIX_TABLE (PREFIX_0F383A) },
7101     { PREFIX_TABLE (PREFIX_0F383B) },
7102     { PREFIX_TABLE (PREFIX_0F383C) },
7103     { PREFIX_TABLE (PREFIX_0F383D) },
7104     { PREFIX_TABLE (PREFIX_0F383E) },
7105     { PREFIX_TABLE (PREFIX_0F383F) },
7106     /* 40 */
7107     { PREFIX_TABLE (PREFIX_0F3840) },
7108     { PREFIX_TABLE (PREFIX_0F3841) },
7109     { Bad_Opcode },
7110     { Bad_Opcode },
7111     { Bad_Opcode },
7112     { Bad_Opcode },
7113     { Bad_Opcode },
7114     { Bad_Opcode },
7115     /* 48 */
7116     { Bad_Opcode },
7117     { Bad_Opcode },
7118     { Bad_Opcode },
7119     { Bad_Opcode },
7120     { Bad_Opcode },
7121     { Bad_Opcode },
7122     { Bad_Opcode },
7123     { Bad_Opcode },
7124     /* 50 */
7125     { Bad_Opcode },
7126     { Bad_Opcode },
7127     { Bad_Opcode },
7128     { Bad_Opcode },
7129     { Bad_Opcode },
7130     { Bad_Opcode },
7131     { Bad_Opcode },
7132     { Bad_Opcode },
7133     /* 58 */
7134     { Bad_Opcode },
7135     { Bad_Opcode },
7136     { Bad_Opcode },
7137     { Bad_Opcode },
7138     { Bad_Opcode },
7139     { Bad_Opcode },
7140     { Bad_Opcode },
7141     { Bad_Opcode },
7142     /* 60 */
7143     { Bad_Opcode },
7144     { Bad_Opcode },
7145     { Bad_Opcode },
7146     { Bad_Opcode },
7147     { Bad_Opcode },
7148     { Bad_Opcode },
7149     { Bad_Opcode },
7150     { Bad_Opcode },
7151     /* 68 */
7152     { Bad_Opcode },
7153     { Bad_Opcode },
7154     { Bad_Opcode },
7155     { Bad_Opcode },
7156     { Bad_Opcode },
7157     { Bad_Opcode },
7158     { Bad_Opcode },
7159     { Bad_Opcode },
7160     /* 70 */
7161     { Bad_Opcode },
7162     { Bad_Opcode },
7163     { Bad_Opcode },
7164     { Bad_Opcode },
7165     { Bad_Opcode },
7166     { Bad_Opcode },
7167     { Bad_Opcode },
7168     { Bad_Opcode },
7169     /* 78 */
7170     { Bad_Opcode },
7171     { Bad_Opcode },
7172     { Bad_Opcode },
7173     { Bad_Opcode },
7174     { Bad_Opcode },
7175     { Bad_Opcode },
7176     { Bad_Opcode },
7177     { Bad_Opcode },
7178     /* 80 */
7179     { PREFIX_TABLE (PREFIX_0F3880) },
7180     { PREFIX_TABLE (PREFIX_0F3881) },
7181     { PREFIX_TABLE (PREFIX_0F3882) },
7182     { Bad_Opcode },
7183     { Bad_Opcode },
7184     { Bad_Opcode },
7185     { Bad_Opcode },
7186     { Bad_Opcode },
7187     /* 88 */
7188     { Bad_Opcode },
7189     { Bad_Opcode },
7190     { Bad_Opcode },
7191     { Bad_Opcode },
7192     { Bad_Opcode },
7193     { Bad_Opcode },
7194     { Bad_Opcode },
7195     { Bad_Opcode },
7196     /* 90 */
7197     { Bad_Opcode },
7198     { Bad_Opcode },
7199     { Bad_Opcode },
7200     { Bad_Opcode },
7201     { Bad_Opcode },
7202     { Bad_Opcode },
7203     { Bad_Opcode },
7204     { Bad_Opcode },
7205     /* 98 */
7206     { Bad_Opcode },
7207     { Bad_Opcode },
7208     { Bad_Opcode },
7209     { Bad_Opcode },
7210     { Bad_Opcode },
7211     { Bad_Opcode },
7212     { Bad_Opcode },
7213     { Bad_Opcode },
7214     /* a0 */
7215     { Bad_Opcode },
7216     { Bad_Opcode },
7217     { Bad_Opcode },
7218     { Bad_Opcode },
7219     { Bad_Opcode },
7220     { Bad_Opcode },
7221     { Bad_Opcode },
7222     { Bad_Opcode },
7223     /* a8 */
7224     { Bad_Opcode },
7225     { Bad_Opcode },
7226     { Bad_Opcode },
7227     { Bad_Opcode },
7228     { Bad_Opcode },
7229     { Bad_Opcode },
7230     { Bad_Opcode },
7231     { Bad_Opcode },
7232     /* b0 */
7233     { Bad_Opcode },
7234     { Bad_Opcode },
7235     { Bad_Opcode },
7236     { Bad_Opcode },
7237     { Bad_Opcode },
7238     { Bad_Opcode },
7239     { Bad_Opcode },
7240     { Bad_Opcode },
7241     /* b8 */
7242     { Bad_Opcode },
7243     { Bad_Opcode },
7244     { Bad_Opcode },
7245     { Bad_Opcode },
7246     { Bad_Opcode },
7247     { Bad_Opcode },
7248     { Bad_Opcode },
7249     { Bad_Opcode },
7250     /* c0 */
7251     { Bad_Opcode },
7252     { Bad_Opcode },
7253     { Bad_Opcode },
7254     { Bad_Opcode },
7255     { Bad_Opcode },
7256     { Bad_Opcode },
7257     { Bad_Opcode },
7258     { Bad_Opcode },
7259     /* c8 */
7260     { PREFIX_TABLE (PREFIX_0F38C8) },
7261     { PREFIX_TABLE (PREFIX_0F38C9) },
7262     { PREFIX_TABLE (PREFIX_0F38CA) },
7263     { PREFIX_TABLE (PREFIX_0F38CB) },
7264     { PREFIX_TABLE (PREFIX_0F38CC) },
7265     { PREFIX_TABLE (PREFIX_0F38CD) },
7266     { Bad_Opcode },
7267     { Bad_Opcode },
7268     /* d0 */
7269     { Bad_Opcode },
7270     { Bad_Opcode },
7271     { Bad_Opcode },
7272     { Bad_Opcode },
7273     { Bad_Opcode },
7274     { Bad_Opcode },
7275     { Bad_Opcode },
7276     { Bad_Opcode },
7277     /* d8 */
7278     { Bad_Opcode },
7279     { Bad_Opcode },
7280     { Bad_Opcode },
7281     { PREFIX_TABLE (PREFIX_0F38DB) },
7282     { PREFIX_TABLE (PREFIX_0F38DC) },
7283     { PREFIX_TABLE (PREFIX_0F38DD) },
7284     { PREFIX_TABLE (PREFIX_0F38DE) },
7285     { PREFIX_TABLE (PREFIX_0F38DF) },
7286     /* e0 */
7287     { Bad_Opcode },
7288     { Bad_Opcode },
7289     { Bad_Opcode },
7290     { Bad_Opcode },
7291     { Bad_Opcode },
7292     { Bad_Opcode },
7293     { Bad_Opcode },
7294     { Bad_Opcode },
7295     /* e8 */
7296     { Bad_Opcode },
7297     { Bad_Opcode },
7298     { Bad_Opcode },
7299     { Bad_Opcode },
7300     { Bad_Opcode },
7301     { Bad_Opcode },
7302     { Bad_Opcode },
7303     { Bad_Opcode },
7304     /* f0 */
7305     { PREFIX_TABLE (PREFIX_0F38F0) },
7306     { PREFIX_TABLE (PREFIX_0F38F1) },
7307     { Bad_Opcode },
7308     { Bad_Opcode },
7309     { Bad_Opcode },
7310     { PREFIX_TABLE (PREFIX_0F38F5) },
7311     { PREFIX_TABLE (PREFIX_0F38F6) },
7312     { Bad_Opcode },
7313     /* f8 */
7314     { Bad_Opcode },
7315     { Bad_Opcode },
7316     { Bad_Opcode },
7317     { Bad_Opcode },
7318     { Bad_Opcode },
7319     { Bad_Opcode },
7320     { Bad_Opcode },
7321     { Bad_Opcode },
7322   },
7323   /* THREE_BYTE_0F3A */
7324   {
7325     /* 00 */
7326     { Bad_Opcode },
7327     { Bad_Opcode },
7328     { Bad_Opcode },
7329     { Bad_Opcode },
7330     { Bad_Opcode },
7331     { Bad_Opcode },
7332     { Bad_Opcode },
7333     { Bad_Opcode },
7334     /* 08 */
7335     { PREFIX_TABLE (PREFIX_0F3A08) },
7336     { PREFIX_TABLE (PREFIX_0F3A09) },
7337     { PREFIX_TABLE (PREFIX_0F3A0A) },
7338     { PREFIX_TABLE (PREFIX_0F3A0B) },
7339     { PREFIX_TABLE (PREFIX_0F3A0C) },
7340     { PREFIX_TABLE (PREFIX_0F3A0D) },
7341     { PREFIX_TABLE (PREFIX_0F3A0E) },
7342     { "palignr",        { MX, EM, Ib }, PREFIX_OPCODE },
7343     /* 10 */
7344     { Bad_Opcode },
7345     { Bad_Opcode },
7346     { Bad_Opcode },
7347     { Bad_Opcode },
7348     { PREFIX_TABLE (PREFIX_0F3A14) },
7349     { PREFIX_TABLE (PREFIX_0F3A15) },
7350     { PREFIX_TABLE (PREFIX_0F3A16) },
7351     { PREFIX_TABLE (PREFIX_0F3A17) },
7352     /* 18 */
7353     { Bad_Opcode },
7354     { Bad_Opcode },
7355     { Bad_Opcode },
7356     { Bad_Opcode },
7357     { Bad_Opcode },
7358     { Bad_Opcode },
7359     { Bad_Opcode },
7360     { Bad_Opcode },
7361     /* 20 */
7362     { PREFIX_TABLE (PREFIX_0F3A20) },
7363     { PREFIX_TABLE (PREFIX_0F3A21) },
7364     { PREFIX_TABLE (PREFIX_0F3A22) },
7365     { Bad_Opcode },
7366     { Bad_Opcode },
7367     { Bad_Opcode },
7368     { Bad_Opcode },
7369     { Bad_Opcode },
7370     /* 28 */
7371     { Bad_Opcode },
7372     { Bad_Opcode },
7373     { Bad_Opcode },
7374     { Bad_Opcode },
7375     { Bad_Opcode },
7376     { Bad_Opcode },
7377     { Bad_Opcode },
7378     { Bad_Opcode },
7379     /* 30 */
7380     { Bad_Opcode },
7381     { Bad_Opcode },
7382     { Bad_Opcode },
7383     { Bad_Opcode },
7384     { Bad_Opcode },
7385     { Bad_Opcode },
7386     { Bad_Opcode },
7387     { Bad_Opcode },
7388     /* 38 */
7389     { Bad_Opcode },
7390     { Bad_Opcode },
7391     { Bad_Opcode },
7392     { Bad_Opcode },
7393     { Bad_Opcode },
7394     { Bad_Opcode },
7395     { Bad_Opcode },
7396     { Bad_Opcode },
7397     /* 40 */
7398     { PREFIX_TABLE (PREFIX_0F3A40) },
7399     { PREFIX_TABLE (PREFIX_0F3A41) },
7400     { PREFIX_TABLE (PREFIX_0F3A42) },
7401     { Bad_Opcode },
7402     { PREFIX_TABLE (PREFIX_0F3A44) },
7403     { Bad_Opcode },
7404     { Bad_Opcode },
7405     { Bad_Opcode },
7406     /* 48 */
7407     { Bad_Opcode },
7408     { Bad_Opcode },
7409     { Bad_Opcode },
7410     { Bad_Opcode },
7411     { Bad_Opcode },
7412     { Bad_Opcode },
7413     { Bad_Opcode },
7414     { Bad_Opcode },
7415     /* 50 */
7416     { Bad_Opcode },
7417     { Bad_Opcode },
7418     { Bad_Opcode },
7419     { Bad_Opcode },
7420     { Bad_Opcode },
7421     { Bad_Opcode },
7422     { Bad_Opcode },
7423     { Bad_Opcode },
7424     /* 58 */
7425     { Bad_Opcode },
7426     { Bad_Opcode },
7427     { Bad_Opcode },
7428     { Bad_Opcode },
7429     { Bad_Opcode },
7430     { Bad_Opcode },
7431     { Bad_Opcode },
7432     { Bad_Opcode },
7433     /* 60 */
7434     { PREFIX_TABLE (PREFIX_0F3A60) },
7435     { PREFIX_TABLE (PREFIX_0F3A61) },
7436     { PREFIX_TABLE (PREFIX_0F3A62) },
7437     { PREFIX_TABLE (PREFIX_0F3A63) },
7438     { Bad_Opcode },
7439     { Bad_Opcode },
7440     { Bad_Opcode },
7441     { Bad_Opcode },
7442     /* 68 */
7443     { Bad_Opcode },
7444     { Bad_Opcode },
7445     { Bad_Opcode },
7446     { Bad_Opcode },
7447     { Bad_Opcode },
7448     { Bad_Opcode },
7449     { Bad_Opcode },
7450     { Bad_Opcode },
7451     /* 70 */
7452     { Bad_Opcode },
7453     { Bad_Opcode },
7454     { Bad_Opcode },
7455     { Bad_Opcode },
7456     { Bad_Opcode },
7457     { Bad_Opcode },
7458     { Bad_Opcode },
7459     { Bad_Opcode },
7460     /* 78 */
7461     { Bad_Opcode },
7462     { Bad_Opcode },
7463     { Bad_Opcode },
7464     { Bad_Opcode },
7465     { Bad_Opcode },
7466     { Bad_Opcode },
7467     { Bad_Opcode },
7468     { Bad_Opcode },
7469     /* 80 */
7470     { Bad_Opcode },
7471     { Bad_Opcode },
7472     { Bad_Opcode },
7473     { Bad_Opcode },
7474     { Bad_Opcode },
7475     { Bad_Opcode },
7476     { Bad_Opcode },
7477     { Bad_Opcode },
7478     /* 88 */
7479     { Bad_Opcode },
7480     { Bad_Opcode },
7481     { Bad_Opcode },
7482     { Bad_Opcode },
7483     { Bad_Opcode },
7484     { Bad_Opcode },
7485     { Bad_Opcode },
7486     { Bad_Opcode },
7487     /* 90 */
7488     { Bad_Opcode },
7489     { Bad_Opcode },
7490     { Bad_Opcode },
7491     { Bad_Opcode },
7492     { Bad_Opcode },
7493     { Bad_Opcode },
7494     { Bad_Opcode },
7495     { Bad_Opcode },
7496     /* 98 */
7497     { Bad_Opcode },
7498     { Bad_Opcode },
7499     { Bad_Opcode },
7500     { Bad_Opcode },
7501     { Bad_Opcode },
7502     { Bad_Opcode },
7503     { Bad_Opcode },
7504     { Bad_Opcode },
7505     /* a0 */
7506     { Bad_Opcode },
7507     { Bad_Opcode },
7508     { Bad_Opcode },
7509     { Bad_Opcode },
7510     { Bad_Opcode },
7511     { Bad_Opcode },
7512     { Bad_Opcode },
7513     { Bad_Opcode },
7514     /* a8 */
7515     { Bad_Opcode },
7516     { Bad_Opcode },
7517     { Bad_Opcode },
7518     { Bad_Opcode },
7519     { Bad_Opcode },
7520     { Bad_Opcode },
7521     { Bad_Opcode },
7522     { Bad_Opcode },
7523     /* b0 */
7524     { Bad_Opcode },
7525     { Bad_Opcode },
7526     { Bad_Opcode },
7527     { Bad_Opcode },
7528     { Bad_Opcode },
7529     { Bad_Opcode },
7530     { Bad_Opcode },
7531     { Bad_Opcode },
7532     /* b8 */
7533     { Bad_Opcode },
7534     { Bad_Opcode },
7535     { Bad_Opcode },
7536     { Bad_Opcode },
7537     { Bad_Opcode },
7538     { Bad_Opcode },
7539     { Bad_Opcode },
7540     { Bad_Opcode },
7541     /* c0 */
7542     { Bad_Opcode },
7543     { Bad_Opcode },
7544     { Bad_Opcode },
7545     { Bad_Opcode },
7546     { Bad_Opcode },
7547     { Bad_Opcode },
7548     { Bad_Opcode },
7549     { Bad_Opcode },
7550     /* c8 */
7551     { Bad_Opcode },
7552     { Bad_Opcode },
7553     { Bad_Opcode },
7554     { Bad_Opcode },
7555     { PREFIX_TABLE (PREFIX_0F3ACC) },
7556     { Bad_Opcode },
7557     { Bad_Opcode },
7558     { Bad_Opcode },
7559     /* d0 */
7560     { Bad_Opcode },
7561     { Bad_Opcode },
7562     { Bad_Opcode },
7563     { Bad_Opcode },
7564     { Bad_Opcode },
7565     { Bad_Opcode },
7566     { Bad_Opcode },
7567     { Bad_Opcode },
7568     /* d8 */
7569     { Bad_Opcode },
7570     { Bad_Opcode },
7571     { Bad_Opcode },
7572     { Bad_Opcode },
7573     { Bad_Opcode },
7574     { Bad_Opcode },
7575     { Bad_Opcode },
7576     { PREFIX_TABLE (PREFIX_0F3ADF) },
7577     /* e0 */
7578     { Bad_Opcode },
7579     { Bad_Opcode },
7580     { Bad_Opcode },
7581     { Bad_Opcode },
7582     { Bad_Opcode },
7583     { Bad_Opcode },
7584     { Bad_Opcode },
7585     { Bad_Opcode },
7586     /* e8 */
7587     { Bad_Opcode },
7588     { Bad_Opcode },
7589     { Bad_Opcode },
7590     { Bad_Opcode },
7591     { Bad_Opcode },
7592     { Bad_Opcode },
7593     { Bad_Opcode },
7594     { Bad_Opcode },
7595     /* f0 */
7596     { Bad_Opcode },
7597     { Bad_Opcode },
7598     { Bad_Opcode },
7599     { Bad_Opcode },
7600     { Bad_Opcode },
7601     { Bad_Opcode },
7602     { Bad_Opcode },
7603     { Bad_Opcode },
7604     /* f8 */
7605     { Bad_Opcode },
7606     { Bad_Opcode },
7607     { Bad_Opcode },
7608     { Bad_Opcode },
7609     { Bad_Opcode },
7610     { Bad_Opcode },
7611     { Bad_Opcode },
7612     { Bad_Opcode },
7613   },
7614 };
7615
7616 static const struct dis386 xop_table[][256] = {
7617   /* XOP_08 */
7618   {
7619     /* 00 */
7620     { Bad_Opcode },
7621     { Bad_Opcode },
7622     { Bad_Opcode },
7623     { Bad_Opcode },
7624     { Bad_Opcode },
7625     { Bad_Opcode },
7626     { Bad_Opcode },
7627     { Bad_Opcode },
7628     /* 08 */
7629     { Bad_Opcode },
7630     { Bad_Opcode },
7631     { Bad_Opcode },
7632     { Bad_Opcode },
7633     { Bad_Opcode },
7634     { Bad_Opcode },
7635     { Bad_Opcode },
7636     { Bad_Opcode },
7637     /* 10 */
7638     { Bad_Opcode },
7639     { Bad_Opcode },
7640     { Bad_Opcode },
7641     { Bad_Opcode },
7642     { Bad_Opcode },
7643     { Bad_Opcode },
7644     { Bad_Opcode },
7645     { Bad_Opcode },
7646     /* 18 */
7647     { Bad_Opcode },
7648     { Bad_Opcode },
7649     { Bad_Opcode },
7650     { Bad_Opcode },
7651     { Bad_Opcode },
7652     { Bad_Opcode },
7653     { Bad_Opcode },
7654     { Bad_Opcode },
7655     /* 20 */
7656     { Bad_Opcode },
7657     { Bad_Opcode },
7658     { Bad_Opcode },
7659     { Bad_Opcode },
7660     { Bad_Opcode },
7661     { Bad_Opcode },
7662     { Bad_Opcode },
7663     { Bad_Opcode },
7664     /* 28 */
7665     { Bad_Opcode },
7666     { Bad_Opcode },
7667     { Bad_Opcode },
7668     { Bad_Opcode },
7669     { Bad_Opcode },
7670     { Bad_Opcode },
7671     { Bad_Opcode },
7672     { Bad_Opcode },
7673     /* 30 */
7674     { Bad_Opcode },
7675     { Bad_Opcode },
7676     { Bad_Opcode },
7677     { Bad_Opcode },
7678     { Bad_Opcode },
7679     { Bad_Opcode },
7680     { Bad_Opcode },
7681     { Bad_Opcode },
7682     /* 38 */
7683     { Bad_Opcode },
7684     { Bad_Opcode },
7685     { Bad_Opcode },
7686     { Bad_Opcode },
7687     { Bad_Opcode },
7688     { Bad_Opcode },
7689     { Bad_Opcode },
7690     { Bad_Opcode },
7691     /* 40 */
7692     { Bad_Opcode },
7693     { Bad_Opcode },
7694     { Bad_Opcode },
7695     { Bad_Opcode },
7696     { Bad_Opcode },
7697     { Bad_Opcode },
7698     { Bad_Opcode },
7699     { Bad_Opcode },
7700     /* 48 */
7701     { Bad_Opcode },
7702     { Bad_Opcode },
7703     { Bad_Opcode },
7704     { Bad_Opcode },
7705     { Bad_Opcode },
7706     { Bad_Opcode },
7707     { Bad_Opcode },
7708     { Bad_Opcode },
7709     /* 50 */
7710     { Bad_Opcode },
7711     { Bad_Opcode },
7712     { Bad_Opcode },
7713     { Bad_Opcode },
7714     { Bad_Opcode },
7715     { Bad_Opcode },
7716     { Bad_Opcode },
7717     { Bad_Opcode },
7718     /* 58 */
7719     { Bad_Opcode },
7720     { Bad_Opcode },
7721     { Bad_Opcode },
7722     { Bad_Opcode },
7723     { Bad_Opcode },
7724     { Bad_Opcode },
7725     { Bad_Opcode },
7726     { Bad_Opcode },
7727     /* 60 */
7728     { Bad_Opcode },
7729     { Bad_Opcode },
7730     { Bad_Opcode },
7731     { Bad_Opcode },
7732     { Bad_Opcode },
7733     { Bad_Opcode },
7734     { Bad_Opcode },
7735     { Bad_Opcode },
7736     /* 68 */
7737     { Bad_Opcode },
7738     { Bad_Opcode },
7739     { Bad_Opcode },
7740     { Bad_Opcode },
7741     { Bad_Opcode },
7742     { Bad_Opcode },
7743     { Bad_Opcode },
7744     { Bad_Opcode },
7745     /* 70 */
7746     { Bad_Opcode },
7747     { Bad_Opcode },
7748     { Bad_Opcode },
7749     { Bad_Opcode },
7750     { Bad_Opcode },
7751     { Bad_Opcode },
7752     { Bad_Opcode },
7753     { Bad_Opcode },
7754     /* 78 */
7755     { Bad_Opcode },
7756     { Bad_Opcode },
7757     { Bad_Opcode },
7758     { Bad_Opcode },
7759     { Bad_Opcode },
7760     { Bad_Opcode },
7761     { Bad_Opcode },
7762     { Bad_Opcode },
7763     /* 80 */
7764     { Bad_Opcode },
7765     { Bad_Opcode },
7766     { Bad_Opcode },
7767     { Bad_Opcode },
7768     { Bad_Opcode },
7769     { "vpmacssww",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7770     { "vpmacsswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7771     { "vpmacssdql",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7772     /* 88 */
7773     { Bad_Opcode },
7774     { Bad_Opcode },
7775     { Bad_Opcode },
7776     { Bad_Opcode },
7777     { Bad_Opcode },
7778     { Bad_Opcode },
7779     { "vpmacssdd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7780     { "vpmacssdqh",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7781     /* 90 */
7782     { Bad_Opcode },
7783     { Bad_Opcode },
7784     { Bad_Opcode },
7785     { Bad_Opcode },
7786     { Bad_Opcode },
7787     { "vpmacsww",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7788     { "vpmacswd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7789     { "vpmacsdql",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7790     /* 98 */
7791     { Bad_Opcode },
7792     { Bad_Opcode },
7793     { Bad_Opcode },
7794     { Bad_Opcode },
7795     { Bad_Opcode },
7796     { Bad_Opcode },
7797     { "vpmacsdd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7798     { "vpmacsdqh",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7799     /* a0 */
7800     { Bad_Opcode },
7801     { Bad_Opcode },
7802     { "vpcmov",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7803     { "vpperm",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7804     { Bad_Opcode },
7805     { Bad_Opcode },
7806     { "vpmadcsswd",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7807     { Bad_Opcode },
7808     /* a8 */
7809     { Bad_Opcode },
7810     { Bad_Opcode },
7811     { Bad_Opcode },
7812     { Bad_Opcode },
7813     { Bad_Opcode },
7814     { Bad_Opcode },
7815     { Bad_Opcode },
7816     { Bad_Opcode },
7817     /* b0 */
7818     { Bad_Opcode },
7819     { Bad_Opcode },
7820     { Bad_Opcode },
7821     { Bad_Opcode },
7822     { Bad_Opcode },
7823     { Bad_Opcode },
7824     { "vpmadcswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7825     { Bad_Opcode },
7826     /* b8 */
7827     { Bad_Opcode },
7828     { Bad_Opcode },
7829     { Bad_Opcode },
7830     { Bad_Opcode },
7831     { Bad_Opcode },
7832     { Bad_Opcode },
7833     { Bad_Opcode },
7834     { Bad_Opcode },
7835     /* c0 */
7836     { "vprotb",         { XM, Vex_2src_1, Ib }, 0 },
7837     { "vprotw",         { XM, Vex_2src_1, Ib }, 0 },
7838     { "vprotd",         { XM, Vex_2src_1, Ib }, 0 },
7839     { "vprotq",         { XM, Vex_2src_1, Ib }, 0 },
7840     { Bad_Opcode },
7841     { Bad_Opcode },
7842     { Bad_Opcode },
7843     { Bad_Opcode },
7844     /* c8 */
7845     { Bad_Opcode },
7846     { Bad_Opcode },
7847     { Bad_Opcode },
7848     { Bad_Opcode },
7849     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
7850     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
7851     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
7852     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
7853     /* d0 */
7854     { Bad_Opcode },
7855     { Bad_Opcode },
7856     { Bad_Opcode },
7857     { Bad_Opcode },
7858     { Bad_Opcode },
7859     { Bad_Opcode },
7860     { Bad_Opcode },
7861     { Bad_Opcode },
7862     /* d8 */
7863     { Bad_Opcode },
7864     { Bad_Opcode },
7865     { Bad_Opcode },
7866     { Bad_Opcode },
7867     { Bad_Opcode },
7868     { Bad_Opcode },
7869     { Bad_Opcode },
7870     { Bad_Opcode },
7871     /* e0 */
7872     { Bad_Opcode },
7873     { Bad_Opcode },
7874     { Bad_Opcode },
7875     { Bad_Opcode },
7876     { Bad_Opcode },
7877     { Bad_Opcode },
7878     { Bad_Opcode },
7879     { Bad_Opcode },
7880     /* e8 */
7881     { Bad_Opcode },
7882     { Bad_Opcode },
7883     { Bad_Opcode },
7884     { Bad_Opcode },
7885     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
7886     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
7887     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
7888     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
7889     /* f0 */
7890     { Bad_Opcode },
7891     { Bad_Opcode },
7892     { Bad_Opcode },
7893     { Bad_Opcode },
7894     { Bad_Opcode },
7895     { Bad_Opcode },
7896     { Bad_Opcode },
7897     { Bad_Opcode },
7898     /* f8 */
7899     { Bad_Opcode },
7900     { Bad_Opcode },
7901     { Bad_Opcode },
7902     { Bad_Opcode },
7903     { Bad_Opcode },
7904     { Bad_Opcode },
7905     { Bad_Opcode },
7906     { Bad_Opcode },
7907   },
7908   /* XOP_09 */
7909   {
7910     /* 00 */
7911     { Bad_Opcode },
7912     { REG_TABLE (REG_XOP_TBM_01) },
7913     { REG_TABLE (REG_XOP_TBM_02) },
7914     { Bad_Opcode },
7915     { Bad_Opcode },
7916     { Bad_Opcode },
7917     { Bad_Opcode },
7918     { Bad_Opcode },
7919     /* 08 */
7920     { Bad_Opcode },
7921     { Bad_Opcode },
7922     { Bad_Opcode },
7923     { Bad_Opcode },
7924     { Bad_Opcode },
7925     { Bad_Opcode },
7926     { Bad_Opcode },
7927     { Bad_Opcode },
7928     /* 10 */
7929     { Bad_Opcode },
7930     { Bad_Opcode },
7931     { REG_TABLE (REG_XOP_LWPCB) },
7932     { Bad_Opcode },
7933     { Bad_Opcode },
7934     { Bad_Opcode },
7935     { Bad_Opcode },
7936     { Bad_Opcode },
7937     /* 18 */
7938     { Bad_Opcode },
7939     { Bad_Opcode },
7940     { Bad_Opcode },
7941     { Bad_Opcode },
7942     { Bad_Opcode },
7943     { Bad_Opcode },
7944     { Bad_Opcode },
7945     { Bad_Opcode },
7946     /* 20 */
7947     { Bad_Opcode },
7948     { Bad_Opcode },
7949     { Bad_Opcode },
7950     { Bad_Opcode },
7951     { Bad_Opcode },
7952     { Bad_Opcode },
7953     { Bad_Opcode },
7954     { Bad_Opcode },
7955     /* 28 */
7956     { Bad_Opcode },
7957     { Bad_Opcode },
7958     { Bad_Opcode },
7959     { Bad_Opcode },
7960     { Bad_Opcode },
7961     { Bad_Opcode },
7962     { Bad_Opcode },
7963     { Bad_Opcode },
7964     /* 30 */
7965     { Bad_Opcode },
7966     { Bad_Opcode },
7967     { Bad_Opcode },
7968     { Bad_Opcode },
7969     { Bad_Opcode },
7970     { Bad_Opcode },
7971     { Bad_Opcode },
7972     { Bad_Opcode },
7973     /* 38 */
7974     { Bad_Opcode },
7975     { Bad_Opcode },
7976     { Bad_Opcode },
7977     { Bad_Opcode },
7978     { Bad_Opcode },
7979     { Bad_Opcode },
7980     { Bad_Opcode },
7981     { Bad_Opcode },
7982     /* 40 */
7983     { Bad_Opcode },
7984     { Bad_Opcode },
7985     { Bad_Opcode },
7986     { Bad_Opcode },
7987     { Bad_Opcode },
7988     { Bad_Opcode },
7989     { Bad_Opcode },
7990     { Bad_Opcode },
7991     /* 48 */
7992     { Bad_Opcode },
7993     { Bad_Opcode },
7994     { Bad_Opcode },
7995     { Bad_Opcode },
7996     { Bad_Opcode },
7997     { Bad_Opcode },
7998     { Bad_Opcode },
7999     { Bad_Opcode },
8000     /* 50 */
8001     { Bad_Opcode },
8002     { Bad_Opcode },
8003     { Bad_Opcode },
8004     { Bad_Opcode },
8005     { Bad_Opcode },
8006     { Bad_Opcode },
8007     { Bad_Opcode },
8008     { Bad_Opcode },
8009     /* 58 */
8010     { Bad_Opcode },
8011     { Bad_Opcode },
8012     { Bad_Opcode },
8013     { Bad_Opcode },
8014     { Bad_Opcode },
8015     { Bad_Opcode },
8016     { Bad_Opcode },
8017     { Bad_Opcode },
8018     /* 60 */
8019     { Bad_Opcode },
8020     { Bad_Opcode },
8021     { Bad_Opcode },
8022     { Bad_Opcode },
8023     { Bad_Opcode },
8024     { Bad_Opcode },
8025     { Bad_Opcode },
8026     { Bad_Opcode },
8027     /* 68 */
8028     { Bad_Opcode },
8029     { Bad_Opcode },
8030     { Bad_Opcode },
8031     { Bad_Opcode },
8032     { Bad_Opcode },
8033     { Bad_Opcode },
8034     { Bad_Opcode },
8035     { Bad_Opcode },
8036     /* 70 */
8037     { Bad_Opcode },
8038     { Bad_Opcode },
8039     { Bad_Opcode },
8040     { Bad_Opcode },
8041     { Bad_Opcode },
8042     { Bad_Opcode },
8043     { Bad_Opcode },
8044     { Bad_Opcode },
8045     /* 78 */
8046     { Bad_Opcode },
8047     { Bad_Opcode },
8048     { Bad_Opcode },
8049     { Bad_Opcode },
8050     { Bad_Opcode },
8051     { Bad_Opcode },
8052     { Bad_Opcode },
8053     { Bad_Opcode },
8054     /* 80 */
8055     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
8056     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
8057     { "vfrczss",        { XM, EXd }, 0 },
8058     { "vfrczsd",        { XM, EXq }, 0 },
8059     { Bad_Opcode },
8060     { Bad_Opcode },
8061     { Bad_Opcode },
8062     { Bad_Opcode },
8063     /* 88 */
8064     { Bad_Opcode },
8065     { Bad_Opcode },
8066     { Bad_Opcode },
8067     { Bad_Opcode },
8068     { Bad_Opcode },
8069     { Bad_Opcode },
8070     { Bad_Opcode },
8071     { Bad_Opcode },
8072     /* 90 */
8073     { "vprotb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8074     { "vprotw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8075     { "vprotd",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8076     { "vprotq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8077     { "vpshlb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8078     { "vpshlw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8079     { "vpshld",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8080     { "vpshlq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8081     /* 98 */
8082     { "vpshab",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8083     { "vpshaw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8084     { "vpshad",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8085     { "vpshaq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8086     { Bad_Opcode },
8087     { Bad_Opcode },
8088     { Bad_Opcode },
8089     { Bad_Opcode },
8090     /* a0 */
8091     { Bad_Opcode },
8092     { Bad_Opcode },
8093     { Bad_Opcode },
8094     { Bad_Opcode },
8095     { Bad_Opcode },
8096     { Bad_Opcode },
8097     { Bad_Opcode },
8098     { Bad_Opcode },
8099     /* a8 */
8100     { Bad_Opcode },
8101     { Bad_Opcode },
8102     { Bad_Opcode },
8103     { Bad_Opcode },
8104     { Bad_Opcode },
8105     { Bad_Opcode },
8106     { Bad_Opcode },
8107     { Bad_Opcode },
8108     /* b0 */
8109     { Bad_Opcode },
8110     { Bad_Opcode },
8111     { Bad_Opcode },
8112     { Bad_Opcode },
8113     { Bad_Opcode },
8114     { Bad_Opcode },
8115     { Bad_Opcode },
8116     { Bad_Opcode },
8117     /* b8 */
8118     { Bad_Opcode },
8119     { Bad_Opcode },
8120     { Bad_Opcode },
8121     { Bad_Opcode },
8122     { Bad_Opcode },
8123     { Bad_Opcode },
8124     { Bad_Opcode },
8125     { Bad_Opcode },
8126     /* c0 */
8127     { Bad_Opcode },
8128     { "vphaddbw",       { XM, EXxmm }, 0 },
8129     { "vphaddbd",       { XM, EXxmm }, 0 },
8130     { "vphaddbq",       { XM, EXxmm }, 0 },
8131     { Bad_Opcode },
8132     { Bad_Opcode },
8133     { "vphaddwd",       { XM, EXxmm }, 0 },
8134     { "vphaddwq",       { XM, EXxmm }, 0 },
8135     /* c8 */
8136     { Bad_Opcode },
8137     { Bad_Opcode },
8138     { Bad_Opcode },
8139     { "vphadddq",       { XM, EXxmm }, 0 },
8140     { Bad_Opcode },
8141     { Bad_Opcode },
8142     { Bad_Opcode },
8143     { Bad_Opcode },
8144     /* d0 */
8145     { Bad_Opcode },
8146     { "vphaddubw",      { XM, EXxmm }, 0 },
8147     { "vphaddubd",      { XM, EXxmm }, 0 },
8148     { "vphaddubq",      { XM, EXxmm }, 0 },
8149     { Bad_Opcode },
8150     { Bad_Opcode },
8151     { "vphadduwd",      { XM, EXxmm }, 0 },
8152     { "vphadduwq",      { XM, EXxmm }, 0 },
8153     /* d8 */
8154     { Bad_Opcode },
8155     { Bad_Opcode },
8156     { Bad_Opcode },
8157     { "vphaddudq",      { XM, EXxmm }, 0 },
8158     { Bad_Opcode },
8159     { Bad_Opcode },
8160     { Bad_Opcode },
8161     { Bad_Opcode },
8162     /* e0 */
8163     { Bad_Opcode },
8164     { "vphsubbw",       { XM, EXxmm }, 0 },
8165     { "vphsubwd",       { XM, EXxmm }, 0 },
8166     { "vphsubdq",       { XM, EXxmm }, 0 },
8167     { Bad_Opcode },
8168     { Bad_Opcode },
8169     { Bad_Opcode },
8170     { Bad_Opcode },
8171     /* e8 */
8172     { Bad_Opcode },
8173     { Bad_Opcode },
8174     { Bad_Opcode },
8175     { Bad_Opcode },
8176     { Bad_Opcode },
8177     { Bad_Opcode },
8178     { Bad_Opcode },
8179     { Bad_Opcode },
8180     /* f0 */
8181     { Bad_Opcode },
8182     { Bad_Opcode },
8183     { Bad_Opcode },
8184     { Bad_Opcode },
8185     { Bad_Opcode },
8186     { Bad_Opcode },
8187     { Bad_Opcode },
8188     { Bad_Opcode },
8189     /* f8 */
8190     { Bad_Opcode },
8191     { Bad_Opcode },
8192     { Bad_Opcode },
8193     { Bad_Opcode },
8194     { Bad_Opcode },
8195     { Bad_Opcode },
8196     { Bad_Opcode },
8197     { Bad_Opcode },
8198   },
8199   /* XOP_0A */
8200   {
8201     /* 00 */
8202     { Bad_Opcode },
8203     { Bad_Opcode },
8204     { Bad_Opcode },
8205     { Bad_Opcode },
8206     { Bad_Opcode },
8207     { Bad_Opcode },
8208     { Bad_Opcode },
8209     { Bad_Opcode },
8210     /* 08 */
8211     { Bad_Opcode },
8212     { Bad_Opcode },
8213     { Bad_Opcode },
8214     { Bad_Opcode },
8215     { Bad_Opcode },
8216     { Bad_Opcode },
8217     { Bad_Opcode },
8218     { Bad_Opcode },
8219     /* 10 */
8220     { "bextr",  { Gv, Ev, Iq }, 0 },
8221     { Bad_Opcode },
8222     { REG_TABLE (REG_XOP_LWP) },
8223     { Bad_Opcode },
8224     { Bad_Opcode },
8225     { Bad_Opcode },
8226     { Bad_Opcode },
8227     { Bad_Opcode },
8228     /* 18 */
8229     { Bad_Opcode },
8230     { Bad_Opcode },
8231     { Bad_Opcode },
8232     { Bad_Opcode },
8233     { Bad_Opcode },
8234     { Bad_Opcode },
8235     { Bad_Opcode },
8236     { Bad_Opcode },
8237     /* 20 */
8238     { Bad_Opcode },
8239     { Bad_Opcode },
8240     { Bad_Opcode },
8241     { Bad_Opcode },
8242     { Bad_Opcode },
8243     { Bad_Opcode },
8244     { Bad_Opcode },
8245     { Bad_Opcode },
8246     /* 28 */
8247     { Bad_Opcode },
8248     { Bad_Opcode },
8249     { Bad_Opcode },
8250     { Bad_Opcode },
8251     { Bad_Opcode },
8252     { Bad_Opcode },
8253     { Bad_Opcode },
8254     { Bad_Opcode },
8255     /* 30 */
8256     { Bad_Opcode },
8257     { Bad_Opcode },
8258     { Bad_Opcode },
8259     { Bad_Opcode },
8260     { Bad_Opcode },
8261     { Bad_Opcode },
8262     { Bad_Opcode },
8263     { Bad_Opcode },
8264     /* 38 */
8265     { Bad_Opcode },
8266     { Bad_Opcode },
8267     { Bad_Opcode },
8268     { Bad_Opcode },
8269     { Bad_Opcode },
8270     { Bad_Opcode },
8271     { Bad_Opcode },
8272     { Bad_Opcode },
8273     /* 40 */
8274     { Bad_Opcode },
8275     { Bad_Opcode },
8276     { Bad_Opcode },
8277     { Bad_Opcode },
8278     { Bad_Opcode },
8279     { Bad_Opcode },
8280     { Bad_Opcode },
8281     { Bad_Opcode },
8282     /* 48 */
8283     { Bad_Opcode },
8284     { Bad_Opcode },
8285     { Bad_Opcode },
8286     { Bad_Opcode },
8287     { Bad_Opcode },
8288     { Bad_Opcode },
8289     { Bad_Opcode },
8290     { Bad_Opcode },
8291     /* 50 */
8292     { Bad_Opcode },
8293     { Bad_Opcode },
8294     { Bad_Opcode },
8295     { Bad_Opcode },
8296     { Bad_Opcode },
8297     { Bad_Opcode },
8298     { Bad_Opcode },
8299     { Bad_Opcode },
8300     /* 58 */
8301     { Bad_Opcode },
8302     { Bad_Opcode },
8303     { Bad_Opcode },
8304     { Bad_Opcode },
8305     { Bad_Opcode },
8306     { Bad_Opcode },
8307     { Bad_Opcode },
8308     { Bad_Opcode },
8309     /* 60 */
8310     { Bad_Opcode },
8311     { Bad_Opcode },
8312     { Bad_Opcode },
8313     { Bad_Opcode },
8314     { Bad_Opcode },
8315     { Bad_Opcode },
8316     { Bad_Opcode },
8317     { Bad_Opcode },
8318     /* 68 */
8319     { Bad_Opcode },
8320     { Bad_Opcode },
8321     { Bad_Opcode },
8322     { Bad_Opcode },
8323     { Bad_Opcode },
8324     { Bad_Opcode },
8325     { Bad_Opcode },
8326     { Bad_Opcode },
8327     /* 70 */
8328     { Bad_Opcode },
8329     { Bad_Opcode },
8330     { Bad_Opcode },
8331     { Bad_Opcode },
8332     { Bad_Opcode },
8333     { Bad_Opcode },
8334     { Bad_Opcode },
8335     { Bad_Opcode },
8336     /* 78 */
8337     { Bad_Opcode },
8338     { Bad_Opcode },
8339     { Bad_Opcode },
8340     { Bad_Opcode },
8341     { Bad_Opcode },
8342     { Bad_Opcode },
8343     { Bad_Opcode },
8344     { Bad_Opcode },
8345     /* 80 */
8346     { Bad_Opcode },
8347     { Bad_Opcode },
8348     { Bad_Opcode },
8349     { Bad_Opcode },
8350     { Bad_Opcode },
8351     { Bad_Opcode },
8352     { Bad_Opcode },
8353     { Bad_Opcode },
8354     /* 88 */
8355     { Bad_Opcode },
8356     { Bad_Opcode },
8357     { Bad_Opcode },
8358     { Bad_Opcode },
8359     { Bad_Opcode },
8360     { Bad_Opcode },
8361     { Bad_Opcode },
8362     { Bad_Opcode },
8363     /* 90 */
8364     { Bad_Opcode },
8365     { Bad_Opcode },
8366     { Bad_Opcode },
8367     { Bad_Opcode },
8368     { Bad_Opcode },
8369     { Bad_Opcode },
8370     { Bad_Opcode },
8371     { Bad_Opcode },
8372     /* 98 */
8373     { Bad_Opcode },
8374     { Bad_Opcode },
8375     { Bad_Opcode },
8376     { Bad_Opcode },
8377     { Bad_Opcode },
8378     { Bad_Opcode },
8379     { Bad_Opcode },
8380     { Bad_Opcode },
8381     /* a0 */
8382     { Bad_Opcode },
8383     { Bad_Opcode },
8384     { Bad_Opcode },
8385     { Bad_Opcode },
8386     { Bad_Opcode },
8387     { Bad_Opcode },
8388     { Bad_Opcode },
8389     { Bad_Opcode },
8390     /* a8 */
8391     { Bad_Opcode },
8392     { Bad_Opcode },
8393     { Bad_Opcode },
8394     { Bad_Opcode },
8395     { Bad_Opcode },
8396     { Bad_Opcode },
8397     { Bad_Opcode },
8398     { Bad_Opcode },
8399     /* b0 */
8400     { Bad_Opcode },
8401     { Bad_Opcode },
8402     { Bad_Opcode },
8403     { Bad_Opcode },
8404     { Bad_Opcode },
8405     { Bad_Opcode },
8406     { Bad_Opcode },
8407     { Bad_Opcode },
8408     /* b8 */
8409     { Bad_Opcode },
8410     { Bad_Opcode },
8411     { Bad_Opcode },
8412     { Bad_Opcode },
8413     { Bad_Opcode },
8414     { Bad_Opcode },
8415     { Bad_Opcode },
8416     { Bad_Opcode },
8417     /* c0 */
8418     { Bad_Opcode },
8419     { Bad_Opcode },
8420     { Bad_Opcode },
8421     { Bad_Opcode },
8422     { Bad_Opcode },
8423     { Bad_Opcode },
8424     { Bad_Opcode },
8425     { Bad_Opcode },
8426     /* c8 */
8427     { Bad_Opcode },
8428     { Bad_Opcode },
8429     { Bad_Opcode },
8430     { Bad_Opcode },
8431     { Bad_Opcode },
8432     { Bad_Opcode },
8433     { Bad_Opcode },
8434     { Bad_Opcode },
8435     /* d0 */
8436     { Bad_Opcode },
8437     { Bad_Opcode },
8438     { Bad_Opcode },
8439     { Bad_Opcode },
8440     { Bad_Opcode },
8441     { Bad_Opcode },
8442     { Bad_Opcode },
8443     { Bad_Opcode },
8444     /* d8 */
8445     { Bad_Opcode },
8446     { Bad_Opcode },
8447     { Bad_Opcode },
8448     { Bad_Opcode },
8449     { Bad_Opcode },
8450     { Bad_Opcode },
8451     { Bad_Opcode },
8452     { Bad_Opcode },
8453     /* e0 */
8454     { Bad_Opcode },
8455     { Bad_Opcode },
8456     { Bad_Opcode },
8457     { Bad_Opcode },
8458     { Bad_Opcode },
8459     { Bad_Opcode },
8460     { Bad_Opcode },
8461     { Bad_Opcode },
8462     /* e8 */
8463     { Bad_Opcode },
8464     { Bad_Opcode },
8465     { Bad_Opcode },
8466     { Bad_Opcode },
8467     { Bad_Opcode },
8468     { Bad_Opcode },
8469     { Bad_Opcode },
8470     { Bad_Opcode },
8471     /* f0 */
8472     { Bad_Opcode },
8473     { Bad_Opcode },
8474     { Bad_Opcode },
8475     { Bad_Opcode },
8476     { Bad_Opcode },
8477     { Bad_Opcode },
8478     { Bad_Opcode },
8479     { Bad_Opcode },
8480     /* f8 */
8481     { Bad_Opcode },
8482     { Bad_Opcode },
8483     { Bad_Opcode },
8484     { Bad_Opcode },
8485     { Bad_Opcode },
8486     { Bad_Opcode },
8487     { Bad_Opcode },
8488     { Bad_Opcode },
8489   },
8490 };
8491
8492 static const struct dis386 vex_table[][256] = {
8493   /* VEX_0F */
8494   {
8495     /* 00 */
8496     { Bad_Opcode },
8497     { Bad_Opcode },
8498     { Bad_Opcode },
8499     { Bad_Opcode },
8500     { Bad_Opcode },
8501     { Bad_Opcode },
8502     { Bad_Opcode },
8503     { Bad_Opcode },
8504     /* 08 */
8505     { Bad_Opcode },
8506     { Bad_Opcode },
8507     { Bad_Opcode },
8508     { Bad_Opcode },
8509     { Bad_Opcode },
8510     { Bad_Opcode },
8511     { Bad_Opcode },
8512     { Bad_Opcode },
8513     /* 10 */
8514     { PREFIX_TABLE (PREFIX_VEX_0F10) },
8515     { PREFIX_TABLE (PREFIX_VEX_0F11) },
8516     { PREFIX_TABLE (PREFIX_VEX_0F12) },
8517     { MOD_TABLE (MOD_VEX_0F13) },
8518     { VEX_W_TABLE (VEX_W_0F14) },
8519     { VEX_W_TABLE (VEX_W_0F15) },
8520     { PREFIX_TABLE (PREFIX_VEX_0F16) },
8521     { MOD_TABLE (MOD_VEX_0F17) },
8522     /* 18 */
8523     { Bad_Opcode },
8524     { Bad_Opcode },
8525     { Bad_Opcode },
8526     { Bad_Opcode },
8527     { Bad_Opcode },
8528     { Bad_Opcode },
8529     { Bad_Opcode },
8530     { Bad_Opcode },
8531     /* 20 */
8532     { Bad_Opcode },
8533     { Bad_Opcode },
8534     { Bad_Opcode },
8535     { Bad_Opcode },
8536     { Bad_Opcode },
8537     { Bad_Opcode },
8538     { Bad_Opcode },
8539     { Bad_Opcode },
8540     /* 28 */
8541     { VEX_W_TABLE (VEX_W_0F28) },
8542     { VEX_W_TABLE (VEX_W_0F29) },
8543     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8544     { MOD_TABLE (MOD_VEX_0F2B) },
8545     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8546     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8547     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8548     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8549     /* 30 */
8550     { Bad_Opcode },
8551     { Bad_Opcode },
8552     { Bad_Opcode },
8553     { Bad_Opcode },
8554     { Bad_Opcode },
8555     { Bad_Opcode },
8556     { Bad_Opcode },
8557     { Bad_Opcode },
8558     /* 38 */
8559     { Bad_Opcode },
8560     { Bad_Opcode },
8561     { Bad_Opcode },
8562     { Bad_Opcode },
8563     { Bad_Opcode },
8564     { Bad_Opcode },
8565     { Bad_Opcode },
8566     { Bad_Opcode },
8567     /* 40 */
8568     { Bad_Opcode },
8569     { PREFIX_TABLE (PREFIX_VEX_0F41) },
8570     { PREFIX_TABLE (PREFIX_VEX_0F42) },
8571     { Bad_Opcode },
8572     { PREFIX_TABLE (PREFIX_VEX_0F44) },
8573     { PREFIX_TABLE (PREFIX_VEX_0F45) },
8574     { PREFIX_TABLE (PREFIX_VEX_0F46) },
8575     { PREFIX_TABLE (PREFIX_VEX_0F47) },
8576     /* 48 */
8577     { Bad_Opcode },
8578     { Bad_Opcode },
8579     { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8580     { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8581     { Bad_Opcode },
8582     { Bad_Opcode },
8583     { Bad_Opcode },
8584     { Bad_Opcode },
8585     /* 50 */
8586     { MOD_TABLE (MOD_VEX_0F50) },
8587     { PREFIX_TABLE (PREFIX_VEX_0F51) },
8588     { PREFIX_TABLE (PREFIX_VEX_0F52) },
8589     { PREFIX_TABLE (PREFIX_VEX_0F53) },
8590     { "vandpX",         { XM, Vex, EXx }, 0 },
8591     { "vandnpX",        { XM, Vex, EXx }, 0 },
8592     { "vorpX",          { XM, Vex, EXx }, 0 },
8593     { "vxorpX",         { XM, Vex, EXx }, 0 },
8594     /* 58 */
8595     { PREFIX_TABLE (PREFIX_VEX_0F58) },
8596     { PREFIX_TABLE (PREFIX_VEX_0F59) },
8597     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8598     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8599     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8600     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8601     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8602     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8603     /* 60 */
8604     { PREFIX_TABLE (PREFIX_VEX_0F60) },
8605     { PREFIX_TABLE (PREFIX_VEX_0F61) },
8606     { PREFIX_TABLE (PREFIX_VEX_0F62) },
8607     { PREFIX_TABLE (PREFIX_VEX_0F63) },
8608     { PREFIX_TABLE (PREFIX_VEX_0F64) },
8609     { PREFIX_TABLE (PREFIX_VEX_0F65) },
8610     { PREFIX_TABLE (PREFIX_VEX_0F66) },
8611     { PREFIX_TABLE (PREFIX_VEX_0F67) },
8612     /* 68 */
8613     { PREFIX_TABLE (PREFIX_VEX_0F68) },
8614     { PREFIX_TABLE (PREFIX_VEX_0F69) },
8615     { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8616     { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8617     { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8618     { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8619     { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8620     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8621     /* 70 */
8622     { PREFIX_TABLE (PREFIX_VEX_0F70) },
8623     { REG_TABLE (REG_VEX_0F71) },
8624     { REG_TABLE (REG_VEX_0F72) },
8625     { REG_TABLE (REG_VEX_0F73) },
8626     { PREFIX_TABLE (PREFIX_VEX_0F74) },
8627     { PREFIX_TABLE (PREFIX_VEX_0F75) },
8628     { PREFIX_TABLE (PREFIX_VEX_0F76) },
8629     { PREFIX_TABLE (PREFIX_VEX_0F77) },
8630     /* 78 */
8631     { Bad_Opcode },
8632     { Bad_Opcode },
8633     { Bad_Opcode },
8634     { Bad_Opcode },
8635     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8636     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8637     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8638     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8639     /* 80 */
8640     { Bad_Opcode },
8641     { Bad_Opcode },
8642     { Bad_Opcode },
8643     { Bad_Opcode },
8644     { Bad_Opcode },
8645     { Bad_Opcode },
8646     { Bad_Opcode },
8647     { Bad_Opcode },
8648     /* 88 */
8649     { Bad_Opcode },
8650     { Bad_Opcode },
8651     { Bad_Opcode },
8652     { Bad_Opcode },
8653     { Bad_Opcode },
8654     { Bad_Opcode },
8655     { Bad_Opcode },
8656     { Bad_Opcode },
8657     /* 90 */
8658     { PREFIX_TABLE (PREFIX_VEX_0F90) },
8659     { PREFIX_TABLE (PREFIX_VEX_0F91) },
8660     { PREFIX_TABLE (PREFIX_VEX_0F92) },
8661     { PREFIX_TABLE (PREFIX_VEX_0F93) },
8662     { Bad_Opcode },
8663     { Bad_Opcode },
8664     { Bad_Opcode },
8665     { Bad_Opcode },
8666     /* 98 */
8667     { PREFIX_TABLE (PREFIX_VEX_0F98) },
8668     { PREFIX_TABLE (PREFIX_VEX_0F99) },
8669     { Bad_Opcode },
8670     { Bad_Opcode },
8671     { Bad_Opcode },
8672     { Bad_Opcode },
8673     { Bad_Opcode },
8674     { Bad_Opcode },
8675     /* a0 */
8676     { Bad_Opcode },
8677     { Bad_Opcode },
8678     { Bad_Opcode },
8679     { Bad_Opcode },
8680     { Bad_Opcode },
8681     { Bad_Opcode },
8682     { Bad_Opcode },
8683     { Bad_Opcode },
8684     /* a8 */
8685     { Bad_Opcode },
8686     { Bad_Opcode },
8687     { Bad_Opcode },
8688     { Bad_Opcode },
8689     { Bad_Opcode },
8690     { Bad_Opcode },
8691     { REG_TABLE (REG_VEX_0FAE) },
8692     { Bad_Opcode },
8693     /* b0 */
8694     { Bad_Opcode },
8695     { Bad_Opcode },
8696     { Bad_Opcode },
8697     { Bad_Opcode },
8698     { Bad_Opcode },
8699     { Bad_Opcode },
8700     { Bad_Opcode },
8701     { Bad_Opcode },
8702     /* b8 */
8703     { Bad_Opcode },
8704     { Bad_Opcode },
8705     { Bad_Opcode },
8706     { Bad_Opcode },
8707     { Bad_Opcode },
8708     { Bad_Opcode },
8709     { Bad_Opcode },
8710     { Bad_Opcode },
8711     /* c0 */
8712     { Bad_Opcode },
8713     { Bad_Opcode },
8714     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8715     { Bad_Opcode },
8716     { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8717     { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8718     { "vshufpX",        { XM, Vex, EXx, Ib }, 0 },
8719     { Bad_Opcode },
8720     /* c8 */
8721     { Bad_Opcode },
8722     { Bad_Opcode },
8723     { Bad_Opcode },
8724     { Bad_Opcode },
8725     { Bad_Opcode },
8726     { Bad_Opcode },
8727     { Bad_Opcode },
8728     { Bad_Opcode },
8729     /* d0 */
8730     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8731     { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8732     { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8733     { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8734     { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8735     { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8736     { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8737     { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8738     /* d8 */
8739     { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8740     { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8741     { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8742     { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8743     { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8744     { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8745     { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8746     { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8747     /* e0 */
8748     { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8749     { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8750     { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8751     { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8752     { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8753     { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8754     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8755     { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8756     /* e8 */
8757     { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8758     { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8759     { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8760     { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8761     { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8762     { PREFIX_TABLE (PREFIX_VEX_0FED) },
8763     { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8764     { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8765     /* f0 */
8766     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8767     { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8768     { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8769     { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8770     { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8771     { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8772     { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8773     { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8774     /* f8 */
8775     { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8776     { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8777     { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8778     { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8779     { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8780     { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8781     { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8782     { Bad_Opcode },
8783   },
8784   /* VEX_0F38 */
8785   {
8786     /* 00 */
8787     { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8788     { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8789     { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8790     { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8791     { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8792     { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8793     { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8794     { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8795     /* 08 */
8796     { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8797     { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8798     { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8799     { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8800     { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8801     { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8802     { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8803     { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8804     /* 10 */
8805     { Bad_Opcode },
8806     { Bad_Opcode },
8807     { Bad_Opcode },
8808     { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8809     { Bad_Opcode },
8810     { Bad_Opcode },
8811     { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8812     { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8813     /* 18 */
8814     { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8815     { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8816     { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8817     { Bad_Opcode },
8818     { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8819     { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8820     { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8821     { Bad_Opcode },
8822     /* 20 */
8823     { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8824     { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8825     { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8826     { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8827     { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8828     { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8829     { Bad_Opcode },
8830     { Bad_Opcode },
8831     /* 28 */
8832     { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8833     { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8834     { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8835     { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8836     { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8837     { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8838     { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8839     { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8840     /* 30 */
8841     { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8842     { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8843     { PREFIX_TABLE (PREFIX_VEX_0F3832) },
8844     { PREFIX_TABLE (PREFIX_VEX_0F3833) },
8845     { PREFIX_TABLE (PREFIX_VEX_0F3834) },
8846     { PREFIX_TABLE (PREFIX_VEX_0F3835) },
8847     { PREFIX_TABLE (PREFIX_VEX_0F3836) },
8848     { PREFIX_TABLE (PREFIX_VEX_0F3837) },
8849     /* 38 */
8850     { PREFIX_TABLE (PREFIX_VEX_0F3838) },
8851     { PREFIX_TABLE (PREFIX_VEX_0F3839) },
8852     { PREFIX_TABLE (PREFIX_VEX_0F383A) },
8853     { PREFIX_TABLE (PREFIX_VEX_0F383B) },
8854     { PREFIX_TABLE (PREFIX_VEX_0F383C) },
8855     { PREFIX_TABLE (PREFIX_VEX_0F383D) },
8856     { PREFIX_TABLE (PREFIX_VEX_0F383E) },
8857     { PREFIX_TABLE (PREFIX_VEX_0F383F) },
8858     /* 40 */
8859     { PREFIX_TABLE (PREFIX_VEX_0F3840) },
8860     { PREFIX_TABLE (PREFIX_VEX_0F3841) },
8861     { Bad_Opcode },
8862     { Bad_Opcode },
8863     { Bad_Opcode },
8864     { PREFIX_TABLE (PREFIX_VEX_0F3845) },
8865     { PREFIX_TABLE (PREFIX_VEX_0F3846) },
8866     { PREFIX_TABLE (PREFIX_VEX_0F3847) },
8867     /* 48 */
8868     { Bad_Opcode },
8869     { Bad_Opcode },
8870     { Bad_Opcode },
8871     { Bad_Opcode },
8872     { Bad_Opcode },
8873     { Bad_Opcode },
8874     { Bad_Opcode },
8875     { Bad_Opcode },
8876     /* 50 */
8877     { Bad_Opcode },
8878     { Bad_Opcode },
8879     { Bad_Opcode },
8880     { Bad_Opcode },
8881     { Bad_Opcode },
8882     { Bad_Opcode },
8883     { Bad_Opcode },
8884     { Bad_Opcode },
8885     /* 58 */
8886     { PREFIX_TABLE (PREFIX_VEX_0F3858) },
8887     { PREFIX_TABLE (PREFIX_VEX_0F3859) },
8888     { PREFIX_TABLE (PREFIX_VEX_0F385A) },
8889     { Bad_Opcode },
8890     { Bad_Opcode },
8891     { Bad_Opcode },
8892     { Bad_Opcode },
8893     { Bad_Opcode },
8894     /* 60 */
8895     { Bad_Opcode },
8896     { Bad_Opcode },
8897     { Bad_Opcode },
8898     { Bad_Opcode },
8899     { Bad_Opcode },
8900     { Bad_Opcode },
8901     { Bad_Opcode },
8902     { Bad_Opcode },
8903     /* 68 */
8904     { Bad_Opcode },
8905     { Bad_Opcode },
8906     { Bad_Opcode },
8907     { Bad_Opcode },
8908     { Bad_Opcode },
8909     { Bad_Opcode },
8910     { Bad_Opcode },
8911     { Bad_Opcode },
8912     /* 70 */
8913     { Bad_Opcode },
8914     { Bad_Opcode },
8915     { Bad_Opcode },
8916     { Bad_Opcode },
8917     { Bad_Opcode },
8918     { Bad_Opcode },
8919     { Bad_Opcode },
8920     { Bad_Opcode },
8921     /* 78 */
8922     { PREFIX_TABLE (PREFIX_VEX_0F3878) },
8923     { PREFIX_TABLE (PREFIX_VEX_0F3879) },
8924     { Bad_Opcode },
8925     { Bad_Opcode },
8926     { Bad_Opcode },
8927     { Bad_Opcode },
8928     { Bad_Opcode },
8929     { Bad_Opcode },
8930     /* 80 */
8931     { Bad_Opcode },
8932     { Bad_Opcode },
8933     { Bad_Opcode },
8934     { Bad_Opcode },
8935     { Bad_Opcode },
8936     { Bad_Opcode },
8937     { Bad_Opcode },
8938     { Bad_Opcode },
8939     /* 88 */
8940     { Bad_Opcode },
8941     { Bad_Opcode },
8942     { Bad_Opcode },
8943     { Bad_Opcode },
8944     { PREFIX_TABLE (PREFIX_VEX_0F388C) },
8945     { Bad_Opcode },
8946     { PREFIX_TABLE (PREFIX_VEX_0F388E) },
8947     { Bad_Opcode },
8948     /* 90 */
8949     { PREFIX_TABLE (PREFIX_VEX_0F3890) },
8950     { PREFIX_TABLE (PREFIX_VEX_0F3891) },
8951     { PREFIX_TABLE (PREFIX_VEX_0F3892) },
8952     { PREFIX_TABLE (PREFIX_VEX_0F3893) },
8953     { Bad_Opcode },
8954     { Bad_Opcode },
8955     { PREFIX_TABLE (PREFIX_VEX_0F3896) },
8956     { PREFIX_TABLE (PREFIX_VEX_0F3897) },
8957     /* 98 */
8958     { PREFIX_TABLE (PREFIX_VEX_0F3898) },
8959     { PREFIX_TABLE (PREFIX_VEX_0F3899) },
8960     { PREFIX_TABLE (PREFIX_VEX_0F389A) },
8961     { PREFIX_TABLE (PREFIX_VEX_0F389B) },
8962     { PREFIX_TABLE (PREFIX_VEX_0F389C) },
8963     { PREFIX_TABLE (PREFIX_VEX_0F389D) },
8964     { PREFIX_TABLE (PREFIX_VEX_0F389E) },
8965     { PREFIX_TABLE (PREFIX_VEX_0F389F) },
8966     /* a0 */
8967     { Bad_Opcode },
8968     { Bad_Opcode },
8969     { Bad_Opcode },
8970     { Bad_Opcode },
8971     { Bad_Opcode },
8972     { Bad_Opcode },
8973     { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
8974     { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
8975     /* a8 */
8976     { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
8977     { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
8978     { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
8979     { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
8980     { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
8981     { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
8982     { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
8983     { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
8984     /* b0 */
8985     { Bad_Opcode },
8986     { Bad_Opcode },
8987     { Bad_Opcode },
8988     { Bad_Opcode },
8989     { Bad_Opcode },
8990     { Bad_Opcode },
8991     { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
8992     { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
8993     /* b8 */
8994     { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
8995     { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
8996     { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
8997     { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
8998     { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
8999     { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
9000     { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
9001     { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
9002     /* c0 */
9003     { Bad_Opcode },
9004     { Bad_Opcode },
9005     { Bad_Opcode },
9006     { Bad_Opcode },
9007     { Bad_Opcode },
9008     { Bad_Opcode },
9009     { Bad_Opcode },
9010     { Bad_Opcode },
9011     /* c8 */
9012     { Bad_Opcode },
9013     { Bad_Opcode },
9014     { Bad_Opcode },
9015     { Bad_Opcode },
9016     { Bad_Opcode },
9017     { Bad_Opcode },
9018     { Bad_Opcode },
9019     { Bad_Opcode },
9020     /* d0 */
9021     { Bad_Opcode },
9022     { Bad_Opcode },
9023     { Bad_Opcode },
9024     { Bad_Opcode },
9025     { Bad_Opcode },
9026     { Bad_Opcode },
9027     { Bad_Opcode },
9028     { Bad_Opcode },
9029     /* d8 */
9030     { Bad_Opcode },
9031     { Bad_Opcode },
9032     { Bad_Opcode },
9033     { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
9034     { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
9035     { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
9036     { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
9037     { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
9038     /* e0 */
9039     { Bad_Opcode },
9040     { Bad_Opcode },
9041     { Bad_Opcode },
9042     { Bad_Opcode },
9043     { Bad_Opcode },
9044     { Bad_Opcode },
9045     { Bad_Opcode },
9046     { Bad_Opcode },
9047     /* e8 */
9048     { Bad_Opcode },
9049     { Bad_Opcode },
9050     { Bad_Opcode },
9051     { Bad_Opcode },
9052     { Bad_Opcode },
9053     { Bad_Opcode },
9054     { Bad_Opcode },
9055     { Bad_Opcode },
9056     /* f0 */
9057     { Bad_Opcode },
9058     { Bad_Opcode },
9059     { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
9060     { REG_TABLE (REG_VEX_0F38F3) },
9061     { Bad_Opcode },
9062     { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
9063     { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
9064     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
9065     /* f8 */
9066     { Bad_Opcode },
9067     { Bad_Opcode },
9068     { Bad_Opcode },
9069     { Bad_Opcode },
9070     { Bad_Opcode },
9071     { Bad_Opcode },
9072     { Bad_Opcode },
9073     { Bad_Opcode },
9074   },
9075   /* VEX_0F3A */
9076   {
9077     /* 00 */
9078     { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
9079     { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
9080     { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
9081     { Bad_Opcode },
9082     { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
9083     { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
9084     { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
9085     { Bad_Opcode },
9086     /* 08 */
9087     { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
9088     { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
9089     { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
9090     { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
9091     { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
9092     { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
9093     { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
9094     { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
9095     /* 10 */
9096     { Bad_Opcode },
9097     { Bad_Opcode },
9098     { Bad_Opcode },
9099     { Bad_Opcode },
9100     { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
9101     { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
9102     { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
9103     { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
9104     /* 18 */
9105     { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
9106     { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
9107     { Bad_Opcode },
9108     { Bad_Opcode },
9109     { Bad_Opcode },
9110     { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
9111     { Bad_Opcode },
9112     { Bad_Opcode },
9113     /* 20 */
9114     { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
9115     { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
9116     { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
9117     { Bad_Opcode },
9118     { Bad_Opcode },
9119     { Bad_Opcode },
9120     { Bad_Opcode },
9121     { Bad_Opcode },
9122     /* 28 */
9123     { Bad_Opcode },
9124     { Bad_Opcode },
9125     { Bad_Opcode },
9126     { Bad_Opcode },
9127     { Bad_Opcode },
9128     { Bad_Opcode },
9129     { Bad_Opcode },
9130     { Bad_Opcode },
9131     /* 30 */
9132     { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
9133     { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
9134     { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
9135     { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
9136     { Bad_Opcode },
9137     { Bad_Opcode },
9138     { Bad_Opcode },
9139     { Bad_Opcode },
9140     /* 38 */
9141     { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
9142     { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
9143     { Bad_Opcode },
9144     { Bad_Opcode },
9145     { Bad_Opcode },
9146     { Bad_Opcode },
9147     { Bad_Opcode },
9148     { Bad_Opcode },
9149     /* 40 */
9150     { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
9151     { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
9152     { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
9153     { Bad_Opcode },
9154     { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
9155     { Bad_Opcode },
9156     { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
9157     { Bad_Opcode },
9158     /* 48 */
9159     { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
9160     { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
9161     { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
9162     { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
9163     { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
9164     { Bad_Opcode },
9165     { Bad_Opcode },
9166     { Bad_Opcode },
9167     /* 50 */
9168     { Bad_Opcode },
9169     { Bad_Opcode },
9170     { Bad_Opcode },
9171     { Bad_Opcode },
9172     { Bad_Opcode },
9173     { Bad_Opcode },
9174     { Bad_Opcode },
9175     { Bad_Opcode },
9176     /* 58 */
9177     { Bad_Opcode },
9178     { Bad_Opcode },
9179     { Bad_Opcode },
9180     { Bad_Opcode },
9181     { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9182     { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9183     { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9184     { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9185     /* 60 */
9186     { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9187     { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9188     { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9189     { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9190     { Bad_Opcode },
9191     { Bad_Opcode },
9192     { Bad_Opcode },
9193     { Bad_Opcode },
9194     /* 68 */
9195     { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9196     { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9197     { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9198     { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9199     { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9200     { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9201     { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9202     { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9203     /* 70 */
9204     { Bad_Opcode },
9205     { Bad_Opcode },
9206     { Bad_Opcode },
9207     { Bad_Opcode },
9208     { Bad_Opcode },
9209     { Bad_Opcode },
9210     { Bad_Opcode },
9211     { Bad_Opcode },
9212     /* 78 */
9213     { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9214     { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9215     { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9216     { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9217     { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9218     { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9219     { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9220     { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9221     /* 80 */
9222     { Bad_Opcode },
9223     { Bad_Opcode },
9224     { Bad_Opcode },
9225     { Bad_Opcode },
9226     { Bad_Opcode },
9227     { Bad_Opcode },
9228     { Bad_Opcode },
9229     { Bad_Opcode },
9230     /* 88 */
9231     { Bad_Opcode },
9232     { Bad_Opcode },
9233     { Bad_Opcode },
9234     { Bad_Opcode },
9235     { Bad_Opcode },
9236     { Bad_Opcode },
9237     { Bad_Opcode },
9238     { Bad_Opcode },
9239     /* 90 */
9240     { Bad_Opcode },
9241     { Bad_Opcode },
9242     { Bad_Opcode },
9243     { Bad_Opcode },
9244     { Bad_Opcode },
9245     { Bad_Opcode },
9246     { Bad_Opcode },
9247     { Bad_Opcode },
9248     /* 98 */
9249     { Bad_Opcode },
9250     { Bad_Opcode },
9251     { Bad_Opcode },
9252     { Bad_Opcode },
9253     { Bad_Opcode },
9254     { Bad_Opcode },
9255     { Bad_Opcode },
9256     { Bad_Opcode },
9257     /* a0 */
9258     { Bad_Opcode },
9259     { Bad_Opcode },
9260     { Bad_Opcode },
9261     { Bad_Opcode },
9262     { Bad_Opcode },
9263     { Bad_Opcode },
9264     { Bad_Opcode },
9265     { Bad_Opcode },
9266     /* a8 */
9267     { Bad_Opcode },
9268     { Bad_Opcode },
9269     { Bad_Opcode },
9270     { Bad_Opcode },
9271     { Bad_Opcode },
9272     { Bad_Opcode },
9273     { Bad_Opcode },
9274     { Bad_Opcode },
9275     /* b0 */
9276     { Bad_Opcode },
9277     { Bad_Opcode },
9278     { Bad_Opcode },
9279     { Bad_Opcode },
9280     { Bad_Opcode },
9281     { Bad_Opcode },
9282     { Bad_Opcode },
9283     { Bad_Opcode },
9284     /* b8 */
9285     { Bad_Opcode },
9286     { Bad_Opcode },
9287     { Bad_Opcode },
9288     { Bad_Opcode },
9289     { Bad_Opcode },
9290     { Bad_Opcode },
9291     { Bad_Opcode },
9292     { Bad_Opcode },
9293     /* c0 */
9294     { Bad_Opcode },
9295     { Bad_Opcode },
9296     { Bad_Opcode },
9297     { Bad_Opcode },
9298     { Bad_Opcode },
9299     { Bad_Opcode },
9300     { Bad_Opcode },
9301     { Bad_Opcode },
9302     /* c8 */
9303     { Bad_Opcode },
9304     { Bad_Opcode },
9305     { Bad_Opcode },
9306     { Bad_Opcode },
9307     { Bad_Opcode },
9308     { Bad_Opcode },
9309     { Bad_Opcode },
9310     { Bad_Opcode },
9311     /* d0 */
9312     { Bad_Opcode },
9313     { Bad_Opcode },
9314     { Bad_Opcode },
9315     { Bad_Opcode },
9316     { Bad_Opcode },
9317     { Bad_Opcode },
9318     { Bad_Opcode },
9319     { Bad_Opcode },
9320     /* d8 */
9321     { Bad_Opcode },
9322     { Bad_Opcode },
9323     { Bad_Opcode },
9324     { Bad_Opcode },
9325     { Bad_Opcode },
9326     { Bad_Opcode },
9327     { Bad_Opcode },
9328     { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9329     /* e0 */
9330     { Bad_Opcode },
9331     { Bad_Opcode },
9332     { Bad_Opcode },
9333     { Bad_Opcode },
9334     { Bad_Opcode },
9335     { Bad_Opcode },
9336     { Bad_Opcode },
9337     { Bad_Opcode },
9338     /* e8 */
9339     { Bad_Opcode },
9340     { Bad_Opcode },
9341     { Bad_Opcode },
9342     { Bad_Opcode },
9343     { Bad_Opcode },
9344     { Bad_Opcode },
9345     { Bad_Opcode },
9346     { Bad_Opcode },
9347     /* f0 */
9348     { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9349     { Bad_Opcode },
9350     { Bad_Opcode },
9351     { Bad_Opcode },
9352     { Bad_Opcode },
9353     { Bad_Opcode },
9354     { Bad_Opcode },
9355     { Bad_Opcode },
9356     /* f8 */
9357     { Bad_Opcode },
9358     { Bad_Opcode },
9359     { Bad_Opcode },
9360     { Bad_Opcode },
9361     { Bad_Opcode },
9362     { Bad_Opcode },
9363     { Bad_Opcode },
9364     { Bad_Opcode },
9365   },
9366 };
9367
9368 #define NEED_OPCODE_TABLE
9369 #include "i386-dis-evex.h"
9370 #undef NEED_OPCODE_TABLE
9371 static const struct dis386 vex_len_table[][2] = {
9372   /* VEX_LEN_0F10_P_1 */
9373   {
9374     { VEX_W_TABLE (VEX_W_0F10_P_1) },
9375     { VEX_W_TABLE (VEX_W_0F10_P_1) },
9376   },
9377
9378   /* VEX_LEN_0F10_P_3 */
9379   {
9380     { VEX_W_TABLE (VEX_W_0F10_P_3) },
9381     { VEX_W_TABLE (VEX_W_0F10_P_3) },
9382   },
9383
9384   /* VEX_LEN_0F11_P_1 */
9385   {
9386     { VEX_W_TABLE (VEX_W_0F11_P_1) },
9387     { VEX_W_TABLE (VEX_W_0F11_P_1) },
9388   },
9389
9390   /* VEX_LEN_0F11_P_3 */
9391   {
9392     { VEX_W_TABLE (VEX_W_0F11_P_3) },
9393     { VEX_W_TABLE (VEX_W_0F11_P_3) },
9394   },
9395
9396   /* VEX_LEN_0F12_P_0_M_0 */
9397   {
9398     { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) },
9399   },
9400
9401   /* VEX_LEN_0F12_P_0_M_1 */
9402   {
9403     { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) },
9404   },
9405
9406   /* VEX_LEN_0F12_P_2 */
9407   {
9408     { VEX_W_TABLE (VEX_W_0F12_P_2) },
9409   },
9410
9411   /* VEX_LEN_0F13_M_0 */
9412   {
9413     { VEX_W_TABLE (VEX_W_0F13_M_0) },
9414   },
9415
9416   /* VEX_LEN_0F16_P_0_M_0 */
9417   {
9418     { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) },
9419   },
9420
9421   /* VEX_LEN_0F16_P_0_M_1 */
9422   {
9423     { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) },
9424   },
9425
9426   /* VEX_LEN_0F16_P_2 */
9427   {
9428     { VEX_W_TABLE (VEX_W_0F16_P_2) },
9429   },
9430
9431   /* VEX_LEN_0F17_M_0 */
9432   {
9433     { VEX_W_TABLE (VEX_W_0F17_M_0) },
9434   },
9435
9436   /* VEX_LEN_0F2A_P_1 */
9437   {
9438     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9439     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9440   },
9441
9442   /* VEX_LEN_0F2A_P_3 */
9443   {
9444     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9445     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9446   },
9447
9448   /* VEX_LEN_0F2C_P_1 */
9449   {
9450     { "vcvttss2siY",    { Gv, EXdScalar }, 0 },
9451     { "vcvttss2siY",    { Gv, EXdScalar }, 0 },
9452   },
9453
9454   /* VEX_LEN_0F2C_P_3 */
9455   {
9456     { "vcvttsd2siY",    { Gv, EXqScalar }, 0 },
9457     { "vcvttsd2siY",    { Gv, EXqScalar }, 0 },
9458   },
9459
9460   /* VEX_LEN_0F2D_P_1 */
9461   {
9462     { "vcvtss2siY",     { Gv, EXdScalar }, 0 },
9463     { "vcvtss2siY",     { Gv, EXdScalar }, 0 },
9464   },
9465
9466   /* VEX_LEN_0F2D_P_3 */
9467   {
9468     { "vcvtsd2siY",     { Gv, EXqScalar }, 0 },
9469     { "vcvtsd2siY",     { Gv, EXqScalar }, 0 },
9470   },
9471
9472   /* VEX_LEN_0F2E_P_0 */
9473   {
9474     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9475     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9476   },
9477
9478   /* VEX_LEN_0F2E_P_2 */
9479   {
9480     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9481     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9482   },
9483
9484   /* VEX_LEN_0F2F_P_0 */
9485   {
9486     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9487     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9488   },
9489
9490   /* VEX_LEN_0F2F_P_2 */
9491   {
9492     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9493     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9494   },
9495
9496   /* VEX_LEN_0F41_P_0 */
9497   {
9498     { Bad_Opcode },
9499     { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9500   },
9501   /* VEX_LEN_0F41_P_2 */
9502   {
9503     { Bad_Opcode },
9504     { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9505   },
9506   /* VEX_LEN_0F42_P_0 */
9507   {
9508     { Bad_Opcode },
9509     { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9510   },
9511   /* VEX_LEN_0F42_P_2 */
9512   {
9513     { Bad_Opcode },
9514     { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9515   },
9516   /* VEX_LEN_0F44_P_0 */
9517   {
9518     { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9519   },
9520   /* VEX_LEN_0F44_P_2 */
9521   {
9522     { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9523   },
9524   /* VEX_LEN_0F45_P_0 */
9525   {
9526     { Bad_Opcode },
9527     { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9528   },
9529   /* VEX_LEN_0F45_P_2 */
9530   {
9531     { Bad_Opcode },
9532     { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9533   },
9534   /* VEX_LEN_0F46_P_0 */
9535   {
9536     { Bad_Opcode },
9537     { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9538   },
9539   /* VEX_LEN_0F46_P_2 */
9540   {
9541     { Bad_Opcode },
9542     { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9543   },
9544   /* VEX_LEN_0F47_P_0 */
9545   {
9546     { Bad_Opcode },
9547     { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9548   },
9549   /* VEX_LEN_0F47_P_2 */
9550   {
9551     { Bad_Opcode },
9552     { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9553   },
9554   /* VEX_LEN_0F4A_P_0 */
9555   {
9556     { Bad_Opcode },
9557     { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9558   },
9559   /* VEX_LEN_0F4A_P_2 */
9560   {
9561     { Bad_Opcode },
9562     { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9563   },
9564   /* VEX_LEN_0F4B_P_0 */
9565   {
9566     { Bad_Opcode },
9567     { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9568   },
9569   /* VEX_LEN_0F4B_P_2 */
9570   {
9571     { Bad_Opcode },
9572     { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9573   },
9574
9575   /* VEX_LEN_0F51_P_1 */
9576   {
9577     { VEX_W_TABLE (VEX_W_0F51_P_1) },
9578     { VEX_W_TABLE (VEX_W_0F51_P_1) },
9579   },
9580
9581   /* VEX_LEN_0F51_P_3 */
9582   {
9583     { VEX_W_TABLE (VEX_W_0F51_P_3) },
9584     { VEX_W_TABLE (VEX_W_0F51_P_3) },
9585   },
9586
9587   /* VEX_LEN_0F52_P_1 */
9588   {
9589     { VEX_W_TABLE (VEX_W_0F52_P_1) },
9590     { VEX_W_TABLE (VEX_W_0F52_P_1) },
9591   },
9592
9593   /* VEX_LEN_0F53_P_1 */
9594   {
9595     { VEX_W_TABLE (VEX_W_0F53_P_1) },
9596     { VEX_W_TABLE (VEX_W_0F53_P_1) },
9597   },
9598
9599   /* VEX_LEN_0F58_P_1 */
9600   {
9601     { VEX_W_TABLE (VEX_W_0F58_P_1) },
9602     { VEX_W_TABLE (VEX_W_0F58_P_1) },
9603   },
9604
9605   /* VEX_LEN_0F58_P_3 */
9606   {
9607     { VEX_W_TABLE (VEX_W_0F58_P_3) },
9608     { VEX_W_TABLE (VEX_W_0F58_P_3) },
9609   },
9610
9611   /* VEX_LEN_0F59_P_1 */
9612   {
9613     { VEX_W_TABLE (VEX_W_0F59_P_1) },
9614     { VEX_W_TABLE (VEX_W_0F59_P_1) },
9615   },
9616
9617   /* VEX_LEN_0F59_P_3 */
9618   {
9619     { VEX_W_TABLE (VEX_W_0F59_P_3) },
9620     { VEX_W_TABLE (VEX_W_0F59_P_3) },
9621   },
9622
9623   /* VEX_LEN_0F5A_P_1 */
9624   {
9625     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9626     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9627   },
9628
9629   /* VEX_LEN_0F5A_P_3 */
9630   {
9631     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9632     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9633   },
9634
9635   /* VEX_LEN_0F5C_P_1 */
9636   {
9637     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9638     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9639   },
9640
9641   /* VEX_LEN_0F5C_P_3 */
9642   {
9643     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9644     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9645   },
9646
9647   /* VEX_LEN_0F5D_P_1 */
9648   {
9649     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9650     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9651   },
9652
9653   /* VEX_LEN_0F5D_P_3 */
9654   {
9655     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9656     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9657   },
9658
9659   /* VEX_LEN_0F5E_P_1 */
9660   {
9661     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9662     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9663   },
9664
9665   /* VEX_LEN_0F5E_P_3 */
9666   {
9667     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9668     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9669   },
9670
9671   /* VEX_LEN_0F5F_P_1 */
9672   {
9673     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9674     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9675   },
9676
9677   /* VEX_LEN_0F5F_P_3 */
9678   {
9679     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9680     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9681   },
9682
9683   /* VEX_LEN_0F6E_P_2 */
9684   {
9685     { "vmovK",          { XMScalar, Edq }, 0 },
9686     { "vmovK",          { XMScalar, Edq }, 0 },
9687   },
9688
9689   /* VEX_LEN_0F7E_P_1 */
9690   {
9691     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9692     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9693   },
9694
9695   /* VEX_LEN_0F7E_P_2 */
9696   {
9697     { "vmovK",          { Edq, XMScalar }, 0 },
9698     { "vmovK",          { Edq, XMScalar }, 0 },
9699   },
9700
9701   /* VEX_LEN_0F90_P_0 */
9702   {
9703     { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9704   },
9705
9706   /* VEX_LEN_0F90_P_2 */
9707   {
9708     { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9709   },
9710
9711   /* VEX_LEN_0F91_P_0 */
9712   {
9713     { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9714   },
9715
9716   /* VEX_LEN_0F91_P_2 */
9717   {
9718     { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
9719   },
9720
9721   /* VEX_LEN_0F92_P_0 */
9722   {
9723     { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9724   },
9725
9726   /* VEX_LEN_0F92_P_2 */
9727   {
9728     { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
9729   },
9730
9731   /* VEX_LEN_0F92_P_3 */
9732   {
9733     { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0) },
9734   },
9735
9736   /* VEX_LEN_0F93_P_0 */
9737   {
9738     { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9739   },
9740
9741   /* VEX_LEN_0F93_P_2 */
9742   {
9743     { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
9744   },
9745
9746   /* VEX_LEN_0F93_P_3 */
9747   {
9748     { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0) },
9749   },
9750
9751   /* VEX_LEN_0F98_P_0 */
9752   {
9753     { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9754   },
9755
9756   /* VEX_LEN_0F98_P_2 */
9757   {
9758     { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
9759   },
9760
9761   /* VEX_LEN_0F99_P_0 */
9762   {
9763     { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
9764   },
9765
9766   /* VEX_LEN_0F99_P_2 */
9767   {
9768     { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
9769   },
9770
9771   /* VEX_LEN_0FAE_R_2_M_0 */
9772   {
9773     { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) },
9774   },
9775
9776   /* VEX_LEN_0FAE_R_3_M_0 */
9777   {
9778     { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) },
9779   },
9780
9781   /* VEX_LEN_0FC2_P_1 */
9782   {
9783     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9784     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9785   },
9786
9787   /* VEX_LEN_0FC2_P_3 */
9788   {
9789     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9790     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9791   },
9792
9793   /* VEX_LEN_0FC4_P_2 */
9794   {
9795     { VEX_W_TABLE (VEX_W_0FC4_P_2) },
9796   },
9797
9798   /* VEX_LEN_0FC5_P_2 */
9799   {
9800     { VEX_W_TABLE (VEX_W_0FC5_P_2) },
9801   },
9802
9803   /* VEX_LEN_0FD6_P_2 */
9804   {
9805     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9806     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9807   },
9808
9809   /* VEX_LEN_0FF7_P_2 */
9810   {
9811     { VEX_W_TABLE (VEX_W_0FF7_P_2) },
9812   },
9813
9814   /* VEX_LEN_0F3816_P_2 */
9815   {
9816     { Bad_Opcode },
9817     { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9818   },
9819
9820   /* VEX_LEN_0F3819_P_2 */
9821   {
9822     { Bad_Opcode },
9823     { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9824   },
9825
9826   /* VEX_LEN_0F381A_P_2_M_0 */
9827   {
9828     { Bad_Opcode },
9829     { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9830   },
9831
9832   /* VEX_LEN_0F3836_P_2 */
9833   {
9834     { Bad_Opcode },
9835     { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9836   },
9837
9838   /* VEX_LEN_0F3841_P_2 */
9839   {
9840     { VEX_W_TABLE (VEX_W_0F3841_P_2) },
9841   },
9842
9843   /* VEX_LEN_0F385A_P_2_M_0 */
9844   {
9845     { Bad_Opcode },
9846     { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
9847   },
9848
9849   /* VEX_LEN_0F38DB_P_2 */
9850   {
9851     { VEX_W_TABLE (VEX_W_0F38DB_P_2) },
9852   },
9853
9854   /* VEX_LEN_0F38DC_P_2 */
9855   {
9856     { VEX_W_TABLE (VEX_W_0F38DC_P_2) },
9857   },
9858
9859   /* VEX_LEN_0F38DD_P_2 */
9860   {
9861     { VEX_W_TABLE (VEX_W_0F38DD_P_2) },
9862   },
9863
9864   /* VEX_LEN_0F38DE_P_2 */
9865   {
9866     { VEX_W_TABLE (VEX_W_0F38DE_P_2) },
9867   },
9868
9869   /* VEX_LEN_0F38DF_P_2 */
9870   {
9871     { VEX_W_TABLE (VEX_W_0F38DF_P_2) },
9872   },
9873
9874   /* VEX_LEN_0F38F2_P_0 */
9875   {
9876     { "andnS",          { Gdq, VexGdq, Edq }, 0 },
9877   },
9878
9879   /* VEX_LEN_0F38F3_R_1_P_0 */
9880   {
9881     { "blsrS",          { VexGdq, Edq }, 0 },
9882   },
9883
9884   /* VEX_LEN_0F38F3_R_2_P_0 */
9885   {
9886     { "blsmskS",        { VexGdq, Edq }, 0 },
9887   },
9888
9889   /* VEX_LEN_0F38F3_R_3_P_0 */
9890   {
9891     { "blsiS",          { VexGdq, Edq }, 0 },
9892   },
9893
9894   /* VEX_LEN_0F38F5_P_0 */
9895   {
9896     { "bzhiS",          { Gdq, Edq, VexGdq }, 0 },
9897   },
9898
9899   /* VEX_LEN_0F38F5_P_1 */
9900   {
9901     { "pextS",          { Gdq, VexGdq, Edq }, 0 },
9902   },
9903
9904   /* VEX_LEN_0F38F5_P_3 */
9905   {
9906     { "pdepS",          { Gdq, VexGdq, Edq }, 0 },
9907   },
9908
9909   /* VEX_LEN_0F38F6_P_3 */
9910   {
9911     { "mulxS",          { Gdq, VexGdq, Edq }, 0 },
9912   },
9913
9914   /* VEX_LEN_0F38F7_P_0 */
9915   {
9916     { "bextrS",         { Gdq, Edq, VexGdq }, 0 },
9917   },
9918
9919   /* VEX_LEN_0F38F7_P_1 */
9920   {
9921     { "sarxS",          { Gdq, Edq, VexGdq }, 0 },
9922   },
9923
9924   /* VEX_LEN_0F38F7_P_2 */
9925   {
9926     { "shlxS",          { Gdq, Edq, VexGdq }, 0 },
9927   },
9928
9929   /* VEX_LEN_0F38F7_P_3 */
9930   {
9931     { "shrxS",          { Gdq, Edq, VexGdq }, 0 },
9932   },
9933
9934   /* VEX_LEN_0F3A00_P_2 */
9935   {
9936     { Bad_Opcode },
9937     { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
9938   },
9939
9940   /* VEX_LEN_0F3A01_P_2 */
9941   {
9942     { Bad_Opcode },
9943     { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
9944   },
9945
9946   /* VEX_LEN_0F3A06_P_2 */
9947   {
9948     { Bad_Opcode },
9949     { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
9950   },
9951
9952   /* VEX_LEN_0F3A0A_P_2 */
9953   {
9954     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
9955     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
9956   },
9957
9958   /* VEX_LEN_0F3A0B_P_2 */
9959   {
9960     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
9961     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
9962   },
9963
9964   /* VEX_LEN_0F3A14_P_2 */
9965   {
9966     { VEX_W_TABLE (VEX_W_0F3A14_P_2) },
9967   },
9968
9969   /* VEX_LEN_0F3A15_P_2 */
9970   {
9971     { VEX_W_TABLE (VEX_W_0F3A15_P_2) },
9972   },
9973
9974   /* VEX_LEN_0F3A16_P_2  */
9975   {
9976     { "vpextrK",        { Edq, XM, Ib }, 0 },
9977   },
9978
9979   /* VEX_LEN_0F3A17_P_2 */
9980   {
9981     { "vextractps",     { Edqd, XM, Ib }, 0 },
9982   },
9983
9984   /* VEX_LEN_0F3A18_P_2 */
9985   {
9986     { Bad_Opcode },
9987     { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
9988   },
9989
9990   /* VEX_LEN_0F3A19_P_2 */
9991   {
9992     { Bad_Opcode },
9993     { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
9994   },
9995
9996   /* VEX_LEN_0F3A20_P_2 */
9997   {
9998     { VEX_W_TABLE (VEX_W_0F3A20_P_2) },
9999   },
10000
10001   /* VEX_LEN_0F3A21_P_2 */
10002   {
10003     { VEX_W_TABLE (VEX_W_0F3A21_P_2) },
10004   },
10005
10006   /* VEX_LEN_0F3A22_P_2 */
10007   {
10008     { "vpinsrK",        { XM, Vex128, Edq, Ib }, 0 },
10009   },
10010
10011   /* VEX_LEN_0F3A30_P_2 */
10012   {
10013     { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
10014   },
10015
10016   /* VEX_LEN_0F3A31_P_2 */
10017   {
10018     { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
10019   },
10020
10021   /* VEX_LEN_0F3A32_P_2 */
10022   {
10023     { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
10024   },
10025
10026   /* VEX_LEN_0F3A33_P_2 */
10027   {
10028     { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
10029   },
10030
10031   /* VEX_LEN_0F3A38_P_2 */
10032   {
10033     { Bad_Opcode },
10034     { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
10035   },
10036
10037   /* VEX_LEN_0F3A39_P_2 */
10038   {
10039     { Bad_Opcode },
10040     { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
10041   },
10042
10043   /* VEX_LEN_0F3A41_P_2 */
10044   {
10045     { VEX_W_TABLE (VEX_W_0F3A41_P_2) },
10046   },
10047
10048   /* VEX_LEN_0F3A44_P_2 */
10049   {
10050     { VEX_W_TABLE (VEX_W_0F3A44_P_2) },
10051   },
10052
10053   /* VEX_LEN_0F3A46_P_2 */
10054   {
10055     { Bad_Opcode },
10056     { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
10057   },
10058
10059   /* VEX_LEN_0F3A60_P_2 */
10060   {
10061     { "vpcmpestrm",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
10062   },
10063
10064   /* VEX_LEN_0F3A61_P_2 */
10065   {
10066     { "vpcmpestri",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
10067   },
10068
10069   /* VEX_LEN_0F3A62_P_2 */
10070   {
10071     { VEX_W_TABLE (VEX_W_0F3A62_P_2) },
10072   },
10073
10074   /* VEX_LEN_0F3A63_P_2 */
10075   {
10076     { VEX_W_TABLE (VEX_W_0F3A63_P_2) },
10077   },
10078
10079   /* VEX_LEN_0F3A6A_P_2 */
10080   {
10081     { "vfmaddss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10082   },
10083
10084   /* VEX_LEN_0F3A6B_P_2 */
10085   {
10086     { "vfmaddsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10087   },
10088
10089   /* VEX_LEN_0F3A6E_P_2 */
10090   {
10091     { "vfmsubss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10092   },
10093
10094   /* VEX_LEN_0F3A6F_P_2 */
10095   {
10096     { "vfmsubsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10097   },
10098
10099   /* VEX_LEN_0F3A7A_P_2 */
10100   {
10101     { "vfnmaddss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10102   },
10103
10104   /* VEX_LEN_0F3A7B_P_2 */
10105   {
10106     { "vfnmaddsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10107   },
10108
10109   /* VEX_LEN_0F3A7E_P_2 */
10110   {
10111     { "vfnmsubss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10112   },
10113
10114   /* VEX_LEN_0F3A7F_P_2 */
10115   {
10116     { "vfnmsubsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10117   },
10118
10119   /* VEX_LEN_0F3ADF_P_2 */
10120   {
10121     { VEX_W_TABLE (VEX_W_0F3ADF_P_2) },
10122   },
10123
10124   /* VEX_LEN_0F3AF0_P_3 */
10125   {
10126     { "rorxS",          { Gdq, Edq, Ib }, 0 },
10127   },
10128
10129   /* VEX_LEN_0FXOP_08_CC */
10130   {
10131      { "vpcomb",        { XM, Vex128, EXx, Ib }, 0 },
10132   },
10133
10134   /* VEX_LEN_0FXOP_08_CD */
10135   {
10136      { "vpcomw",        { XM, Vex128, EXx, Ib }, 0 },
10137   },
10138
10139   /* VEX_LEN_0FXOP_08_CE */
10140   {
10141      { "vpcomd",        { XM, Vex128, EXx, Ib }, 0 },
10142   },
10143
10144   /* VEX_LEN_0FXOP_08_CF */
10145   {
10146      { "vpcomq",        { XM, Vex128, EXx, Ib }, 0 },
10147   },
10148
10149   /* VEX_LEN_0FXOP_08_EC */
10150   {
10151      { "vpcomub",       { XM, Vex128, EXx, Ib }, 0 },
10152   },
10153
10154   /* VEX_LEN_0FXOP_08_ED */
10155   {
10156      { "vpcomuw",       { XM, Vex128, EXx, Ib }, 0 },
10157   },
10158
10159   /* VEX_LEN_0FXOP_08_EE */
10160   {
10161      { "vpcomud",       { XM, Vex128, EXx, Ib }, 0 },
10162   },
10163
10164   /* VEX_LEN_0FXOP_08_EF */
10165   {
10166      { "vpcomuq",       { XM, Vex128, EXx, Ib }, 0 },
10167   },
10168
10169   /* VEX_LEN_0FXOP_09_80 */
10170   {
10171     { "vfrczps",        { XM, EXxmm }, 0 },
10172     { "vfrczps",        { XM, EXymmq }, 0 },
10173   },
10174
10175   /* VEX_LEN_0FXOP_09_81 */
10176   {
10177     { "vfrczpd",        { XM, EXxmm }, 0 },
10178     { "vfrczpd",        { XM, EXymmq }, 0 },
10179   },
10180 };
10181
10182 static const struct dis386 vex_w_table[][2] = {
10183   {
10184     /* VEX_W_0F10_P_0 */
10185     { "vmovups",        { XM, EXx }, 0 },
10186   },
10187   {
10188     /* VEX_W_0F10_P_1 */
10189     { "vmovss",         { XMVexScalar, VexScalar, EXdScalar }, 0 },
10190   },
10191   {
10192     /* VEX_W_0F10_P_2 */
10193     { "vmovupd",        { XM, EXx }, 0 },
10194   },
10195   {
10196     /* VEX_W_0F10_P_3 */
10197     { "vmovsd",         { XMVexScalar, VexScalar, EXqScalar }, 0 },
10198   },
10199   {
10200     /* VEX_W_0F11_P_0 */
10201     { "vmovups",        { EXxS, XM }, 0 },
10202   },
10203   {
10204     /* VEX_W_0F11_P_1 */
10205     { "vmovss",         { EXdVexScalarS, VexScalar, XMScalar }, 0 },
10206   },
10207   {
10208     /* VEX_W_0F11_P_2 */
10209     { "vmovupd",        { EXxS, XM }, 0 },
10210   },
10211   {
10212     /* VEX_W_0F11_P_3 */
10213     { "vmovsd",         { EXqVexScalarS, VexScalar, XMScalar }, 0 },
10214   },
10215   {
10216     /* VEX_W_0F12_P_0_M_0 */
10217     { "vmovlps",        { XM, Vex128, EXq }, 0 },
10218   },
10219   {
10220     /* VEX_W_0F12_P_0_M_1 */
10221     { "vmovhlps",       { XM, Vex128, EXq }, 0 },
10222   },
10223   {
10224     /* VEX_W_0F12_P_1 */
10225     { "vmovsldup",      { XM, EXx }, 0 },
10226   },
10227   {
10228     /* VEX_W_0F12_P_2 */
10229     { "vmovlpd",        { XM, Vex128, EXq }, 0 },
10230   },
10231   {
10232     /* VEX_W_0F12_P_3 */
10233     { "vmovddup",       { XM, EXymmq }, 0 },
10234   },
10235   {
10236     /* VEX_W_0F13_M_0 */
10237     { "vmovlpX",        { EXq, XM }, 0 },
10238   },
10239   {
10240     /* VEX_W_0F14 */
10241     { "vunpcklpX",      { XM, Vex, EXx }, 0 },
10242   },
10243   {
10244     /* VEX_W_0F15 */
10245     { "vunpckhpX",      { XM, Vex, EXx }, 0 },
10246   },
10247   {
10248     /* VEX_W_0F16_P_0_M_0 */
10249     { "vmovhps",        { XM, Vex128, EXq }, 0 },
10250   },
10251   {
10252     /* VEX_W_0F16_P_0_M_1 */
10253     { "vmovlhps",       { XM, Vex128, EXq }, 0 },
10254   },
10255   {
10256     /* VEX_W_0F16_P_1 */
10257     { "vmovshdup",      { XM, EXx }, 0 },
10258   },
10259   {
10260     /* VEX_W_0F16_P_2 */
10261     { "vmovhpd",        { XM, Vex128, EXq }, 0 },
10262   },
10263   {
10264     /* VEX_W_0F17_M_0 */
10265     { "vmovhpX",        { EXq, XM }, 0 },
10266   },
10267   {
10268     /* VEX_W_0F28 */
10269     { "vmovapX",        { XM, EXx }, 0 },
10270   },
10271   {
10272     /* VEX_W_0F29 */
10273     { "vmovapX",        { EXxS, XM }, 0 },
10274   },
10275   {
10276     /* VEX_W_0F2B_M_0 */
10277     { "vmovntpX",       { Mx, XM }, 0 },
10278   },
10279   {
10280     /* VEX_W_0F2E_P_0 */
10281     { "vucomiss",       { XMScalar, EXdScalar }, 0 },
10282   },
10283   {
10284     /* VEX_W_0F2E_P_2 */
10285     { "vucomisd",       { XMScalar, EXqScalar }, 0 },
10286   },
10287   {
10288     /* VEX_W_0F2F_P_0 */
10289     { "vcomiss",        { XMScalar, EXdScalar }, 0 },
10290   },
10291   {
10292     /* VEX_W_0F2F_P_2 */
10293     { "vcomisd",        { XMScalar, EXqScalar }, 0 },
10294   },
10295   {
10296     /* VEX_W_0F41_P_0_LEN_1 */
10297     { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
10298     { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) },
10299   },
10300   {
10301     /* VEX_W_0F41_P_2_LEN_1 */
10302     { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) },
10303     { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) }
10304   },
10305   {
10306     /* VEX_W_0F42_P_0_LEN_1 */
10307     { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) },
10308     { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) },
10309   },
10310   {
10311     /* VEX_W_0F42_P_2_LEN_1 */
10312     { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) },
10313     { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) },
10314   },
10315   {
10316     /* VEX_W_0F44_P_0_LEN_0 */
10317     { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) },
10318     { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) },
10319   },
10320   {
10321     /* VEX_W_0F44_P_2_LEN_0 */
10322     { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) },
10323     { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) },
10324   },
10325   {
10326     /* VEX_W_0F45_P_0_LEN_1 */
10327     { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) },
10328     { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) },
10329   },
10330   {
10331     /* VEX_W_0F45_P_2_LEN_1 */
10332     { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) },
10333     { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) },
10334   },
10335   {
10336     /* VEX_W_0F46_P_0_LEN_1 */
10337     { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) },
10338     { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) },
10339   },
10340   {
10341     /* VEX_W_0F46_P_2_LEN_1 */
10342     { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) },
10343     { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) },
10344   },
10345   {
10346     /* VEX_W_0F47_P_0_LEN_1 */
10347     { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) },
10348     { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) },
10349   },
10350   {
10351     /* VEX_W_0F47_P_2_LEN_1 */
10352     { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) },
10353     { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) },
10354   },
10355   {
10356     /* VEX_W_0F4A_P_0_LEN_1 */
10357     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) },
10358     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) },
10359   },
10360   {
10361     /* VEX_W_0F4A_P_2_LEN_1 */
10362     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) },
10363     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) },
10364   },
10365   {
10366     /* VEX_W_0F4B_P_0_LEN_1 */
10367     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) },
10368     { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) },
10369   },
10370   {
10371     /* VEX_W_0F4B_P_2_LEN_1 */
10372     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
10373   },
10374   {
10375     /* VEX_W_0F50_M_0 */
10376     { "vmovmskpX",      { Gdq, XS }, 0 },
10377   },
10378   {
10379     /* VEX_W_0F51_P_0 */
10380     { "vsqrtps",        { XM, EXx }, 0 },
10381   },
10382   {
10383     /* VEX_W_0F51_P_1 */
10384     { "vsqrtss",        { XMScalar, VexScalar, EXdScalar }, 0 },
10385   },
10386   {
10387     /* VEX_W_0F51_P_2  */
10388     { "vsqrtpd",        { XM, EXx }, 0 },
10389   },
10390   {
10391     /* VEX_W_0F51_P_3 */
10392     { "vsqrtsd",        { XMScalar, VexScalar, EXqScalar }, 0 },
10393   },
10394   {
10395     /* VEX_W_0F52_P_0 */
10396     { "vrsqrtps",       { XM, EXx }, 0 },
10397   },
10398   {
10399     /* VEX_W_0F52_P_1 */
10400     { "vrsqrtss",       { XMScalar, VexScalar, EXdScalar }, 0 },
10401   },
10402   {
10403     /* VEX_W_0F53_P_0  */
10404     { "vrcpps",         { XM, EXx }, 0 },
10405   },
10406   {
10407     /* VEX_W_0F53_P_1  */
10408     { "vrcpss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10409   },
10410   {
10411     /* VEX_W_0F58_P_0  */
10412     { "vaddps",         { XM, Vex, EXx }, 0 },
10413   },
10414   {
10415     /* VEX_W_0F58_P_1  */
10416     { "vaddss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10417   },
10418   {
10419     /* VEX_W_0F58_P_2  */
10420     { "vaddpd",         { XM, Vex, EXx }, 0 },
10421   },
10422   {
10423     /* VEX_W_0F58_P_3  */
10424     { "vaddsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10425   },
10426   {
10427     /* VEX_W_0F59_P_0  */
10428     { "vmulps",         { XM, Vex, EXx }, 0 },
10429   },
10430   {
10431     /* VEX_W_0F59_P_1  */
10432     { "vmulss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10433   },
10434   {
10435     /* VEX_W_0F59_P_2  */
10436     { "vmulpd",         { XM, Vex, EXx }, 0 },
10437   },
10438   {
10439     /* VEX_W_0F59_P_3  */
10440     { "vmulsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10441   },
10442   {
10443     /* VEX_W_0F5A_P_0  */
10444     { "vcvtps2pd",      { XM, EXxmmq }, 0 },
10445   },
10446   {
10447     /* VEX_W_0F5A_P_1  */
10448     { "vcvtss2sd",      { XMScalar, VexScalar, EXdScalar }, 0 },
10449   },
10450   {
10451     /* VEX_W_0F5A_P_3  */
10452     { "vcvtsd2ss",      { XMScalar, VexScalar, EXqScalar }, 0 },
10453   },
10454   {
10455     /* VEX_W_0F5B_P_0  */
10456     { "vcvtdq2ps",      { XM, EXx }, 0 },
10457   },
10458   {
10459     /* VEX_W_0F5B_P_1  */
10460     { "vcvttps2dq",     { XM, EXx }, 0 },
10461   },
10462   {
10463     /* VEX_W_0F5B_P_2  */
10464     { "vcvtps2dq",      { XM, EXx }, 0 },
10465   },
10466   {
10467     /* VEX_W_0F5C_P_0  */
10468     { "vsubps",         { XM, Vex, EXx }, 0 },
10469   },
10470   {
10471     /* VEX_W_0F5C_P_1  */
10472     { "vsubss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10473   },
10474   {
10475     /* VEX_W_0F5C_P_2  */
10476     { "vsubpd",         { XM, Vex, EXx }, 0 },
10477   },
10478   {
10479     /* VEX_W_0F5C_P_3  */
10480     { "vsubsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10481   },
10482   {
10483     /* VEX_W_0F5D_P_0  */
10484     { "vminps",         { XM, Vex, EXx }, 0 },
10485   },
10486   {
10487     /* VEX_W_0F5D_P_1  */
10488     { "vminss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10489   },
10490   {
10491     /* VEX_W_0F5D_P_2  */
10492     { "vminpd",         { XM, Vex, EXx }, 0 },
10493   },
10494   {
10495     /* VEX_W_0F5D_P_3  */
10496     { "vminsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10497   },
10498   {
10499     /* VEX_W_0F5E_P_0  */
10500     { "vdivps",         { XM, Vex, EXx }, 0 },
10501   },
10502   {
10503     /* VEX_W_0F5E_P_1  */
10504     { "vdivss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10505   },
10506   {
10507     /* VEX_W_0F5E_P_2  */
10508     { "vdivpd",         { XM, Vex, EXx }, 0 },
10509   },
10510   {
10511     /* VEX_W_0F5E_P_3  */
10512     { "vdivsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10513   },
10514   {
10515     /* VEX_W_0F5F_P_0  */
10516     { "vmaxps",         { XM, Vex, EXx }, 0 },
10517   },
10518   {
10519     /* VEX_W_0F5F_P_1  */
10520     { "vmaxss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10521   },
10522   {
10523     /* VEX_W_0F5F_P_2  */
10524     { "vmaxpd",         { XM, Vex, EXx }, 0 },
10525   },
10526   {
10527     /* VEX_W_0F5F_P_3  */
10528     { "vmaxsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10529   },
10530   {
10531     /* VEX_W_0F60_P_2  */
10532     { "vpunpcklbw",     { XM, Vex, EXx }, 0 },
10533   },
10534   {
10535     /* VEX_W_0F61_P_2  */
10536     { "vpunpcklwd",     { XM, Vex, EXx }, 0 },
10537   },
10538   {
10539     /* VEX_W_0F62_P_2  */
10540     { "vpunpckldq",     { XM, Vex, EXx }, 0 },
10541   },
10542   {
10543     /* VEX_W_0F63_P_2  */
10544     { "vpacksswb",      { XM, Vex, EXx }, 0 },
10545   },
10546   {
10547     /* VEX_W_0F64_P_2  */
10548     { "vpcmpgtb",       { XM, Vex, EXx }, 0 },
10549   },
10550   {
10551     /* VEX_W_0F65_P_2  */
10552     { "vpcmpgtw",       { XM, Vex, EXx }, 0 },
10553   },
10554   {
10555     /* VEX_W_0F66_P_2  */
10556     { "vpcmpgtd",       { XM, Vex, EXx }, 0 },
10557   },
10558   {
10559     /* VEX_W_0F67_P_2  */
10560     { "vpackuswb",      { XM, Vex, EXx }, 0 },
10561   },
10562   {
10563     /* VEX_W_0F68_P_2  */
10564     { "vpunpckhbw",     { XM, Vex, EXx }, 0 },
10565   },
10566   {
10567     /* VEX_W_0F69_P_2  */
10568     { "vpunpckhwd",     { XM, Vex, EXx }, 0 },
10569   },
10570   {
10571     /* VEX_W_0F6A_P_2  */
10572     { "vpunpckhdq",     { XM, Vex, EXx }, 0 },
10573   },
10574   {
10575     /* VEX_W_0F6B_P_2  */
10576     { "vpackssdw",      { XM, Vex, EXx }, 0 },
10577   },
10578   {
10579     /* VEX_W_0F6C_P_2  */
10580     { "vpunpcklqdq",    { XM, Vex, EXx }, 0 },
10581   },
10582   {
10583     /* VEX_W_0F6D_P_2  */
10584     { "vpunpckhqdq",    { XM, Vex, EXx }, 0 },
10585   },
10586   {
10587     /* VEX_W_0F6F_P_1  */
10588     { "vmovdqu",        { XM, EXx }, 0 },
10589   },
10590   {
10591     /* VEX_W_0F6F_P_2  */
10592     { "vmovdqa",        { XM, EXx }, 0 },
10593   },
10594   {
10595     /* VEX_W_0F70_P_1 */
10596     { "vpshufhw",       { XM, EXx, Ib }, 0 },
10597   },
10598   {
10599     /* VEX_W_0F70_P_2 */
10600     { "vpshufd",        { XM, EXx, Ib }, 0 },
10601   },
10602   {
10603     /* VEX_W_0F70_P_3 */
10604     { "vpshuflw",       { XM, EXx, Ib }, 0 },
10605   },
10606   {
10607     /* VEX_W_0F71_R_2_P_2  */
10608     { "vpsrlw",         { Vex, XS, Ib }, 0 },
10609   },
10610   {
10611     /* VEX_W_0F71_R_4_P_2  */
10612     { "vpsraw",         { Vex, XS, Ib }, 0 },
10613   },
10614   {
10615     /* VEX_W_0F71_R_6_P_2  */
10616     { "vpsllw",         { Vex, XS, Ib }, 0 },
10617   },
10618   {
10619     /* VEX_W_0F72_R_2_P_2  */
10620     { "vpsrld",         { Vex, XS, Ib }, 0 },
10621   },
10622   {
10623     /* VEX_W_0F72_R_4_P_2  */
10624     { "vpsrad",         { Vex, XS, Ib }, 0 },
10625   },
10626   {
10627     /* VEX_W_0F72_R_6_P_2  */
10628     { "vpslld",         { Vex, XS, Ib }, 0 },
10629   },
10630   {
10631     /* VEX_W_0F73_R_2_P_2  */
10632     { "vpsrlq",         { Vex, XS, Ib }, 0 },
10633   },
10634   {
10635     /* VEX_W_0F73_R_3_P_2  */
10636     { "vpsrldq",        { Vex, XS, Ib }, 0 },
10637   },
10638   {
10639     /* VEX_W_0F73_R_6_P_2  */
10640     { "vpsllq",         { Vex, XS, Ib }, 0 },
10641   },
10642   {
10643     /* VEX_W_0F73_R_7_P_2  */
10644     { "vpslldq",        { Vex, XS, Ib }, 0 },
10645   },
10646   {
10647     /* VEX_W_0F74_P_2 */
10648     { "vpcmpeqb",       { XM, Vex, EXx }, 0 },
10649   },
10650   {
10651     /* VEX_W_0F75_P_2 */
10652     { "vpcmpeqw",       { XM, Vex, EXx }, 0 },
10653   },
10654   {
10655     /* VEX_W_0F76_P_2 */
10656     { "vpcmpeqd",       { XM, Vex, EXx }, 0 },
10657   },
10658   {
10659     /* VEX_W_0F77_P_0 */
10660     { "",               { VZERO }, 0 },
10661   },
10662   {
10663     /* VEX_W_0F7C_P_2 */
10664     { "vhaddpd",        { XM, Vex, EXx }, 0 },
10665   },
10666   {
10667     /* VEX_W_0F7C_P_3 */
10668     { "vhaddps",        { XM, Vex, EXx }, 0 },
10669   },
10670   {
10671     /* VEX_W_0F7D_P_2 */
10672     { "vhsubpd",        { XM, Vex, EXx }, 0 },
10673   },
10674   {
10675     /* VEX_W_0F7D_P_3 */
10676     { "vhsubps",        { XM, Vex, EXx }, 0 },
10677   },
10678   {
10679     /* VEX_W_0F7E_P_1 */
10680     { "vmovq",          { XMScalar, EXqScalar }, 0 },
10681   },
10682   {
10683     /* VEX_W_0F7F_P_1 */
10684     { "vmovdqu",        { EXxS, XM }, 0 },
10685   },
10686   {
10687     /* VEX_W_0F7F_P_2 */
10688     { "vmovdqa",        { EXxS, XM }, 0 },
10689   },
10690   {
10691     /* VEX_W_0F90_P_0_LEN_0 */
10692     { "kmovw",          { MaskG, MaskE }, 0 },
10693     { "kmovq",          { MaskG, MaskE }, 0 },
10694   },
10695   {
10696     /* VEX_W_0F90_P_2_LEN_0 */
10697     { "kmovb",          { MaskG, MaskBDE }, 0 },
10698     { "kmovd",          { MaskG, MaskBDE }, 0 },
10699   },
10700   {
10701     /* VEX_W_0F91_P_0_LEN_0 */
10702     { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
10703     { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
10704   },
10705   {
10706     /* VEX_W_0F91_P_2_LEN_0 */
10707     { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
10708     { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
10709   },
10710   {
10711     /* VEX_W_0F92_P_0_LEN_0 */
10712     { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
10713   },
10714   {
10715     /* VEX_W_0F92_P_2_LEN_0 */
10716     { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
10717   },
10718   {
10719     /* VEX_W_0F92_P_3_LEN_0 */
10720     { MOD_TABLE (MOD_VEX_W_0_0F92_P_3_LEN_0) },
10721     { MOD_TABLE (MOD_VEX_W_1_0F92_P_3_LEN_0) },
10722   },
10723   {
10724     /* VEX_W_0F93_P_0_LEN_0 */
10725     { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
10726   },
10727   {
10728     /* VEX_W_0F93_P_2_LEN_0 */
10729     { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
10730   },
10731   {
10732     /* VEX_W_0F93_P_3_LEN_0 */
10733     { MOD_TABLE (MOD_VEX_W_0_0F93_P_3_LEN_0) },
10734     { MOD_TABLE (MOD_VEX_W_1_0F93_P_3_LEN_0) },
10735   },
10736   {
10737     /* VEX_W_0F98_P_0_LEN_0 */
10738     { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
10739     { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
10740   },
10741   {
10742     /* VEX_W_0F98_P_2_LEN_0 */
10743     { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
10744     { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
10745   },
10746   {
10747     /* VEX_W_0F99_P_0_LEN_0 */
10748     { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
10749     { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
10750   },
10751   {
10752     /* VEX_W_0F99_P_2_LEN_0 */
10753     { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
10754     { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
10755   },
10756   {
10757     /* VEX_W_0FAE_R_2_M_0 */
10758     { "vldmxcsr",       { Md }, 0 },
10759   },
10760   {
10761     /* VEX_W_0FAE_R_3_M_0 */
10762     { "vstmxcsr",       { Md }, 0 },
10763   },
10764   {
10765     /* VEX_W_0FC2_P_0 */
10766     { "vcmpps",         { XM, Vex, EXx, VCMP }, 0 },
10767   },
10768   {
10769     /* VEX_W_0FC2_P_1 */
10770     { "vcmpss",         { XMScalar, VexScalar, EXdScalar, VCMP }, 0 },
10771   },
10772   {
10773     /* VEX_W_0FC2_P_2 */
10774     { "vcmppd",         { XM, Vex, EXx, VCMP }, 0 },
10775   },
10776   {
10777     /* VEX_W_0FC2_P_3 */
10778     { "vcmpsd",         { XMScalar, VexScalar, EXqScalar, VCMP }, 0 },
10779   },
10780   {
10781     /* VEX_W_0FC4_P_2 */
10782     { "vpinsrw",        { XM, Vex128, Edqw, Ib }, 0 },
10783   },
10784   {
10785     /* VEX_W_0FC5_P_2 */
10786     { "vpextrw",        { Gdq, XS, Ib }, 0 },
10787   },
10788   {
10789     /* VEX_W_0FD0_P_2 */
10790     { "vaddsubpd",      { XM, Vex, EXx }, 0 },
10791   },
10792   {
10793     /* VEX_W_0FD0_P_3 */
10794     { "vaddsubps",      { XM, Vex, EXx }, 0 },
10795   },
10796   {
10797     /* VEX_W_0FD1_P_2 */
10798     { "vpsrlw",         { XM, Vex, EXxmm }, 0 },
10799   },
10800   {
10801     /* VEX_W_0FD2_P_2 */
10802     { "vpsrld",         { XM, Vex, EXxmm }, 0 },
10803   },
10804   {
10805     /* VEX_W_0FD3_P_2 */
10806     { "vpsrlq",         { XM, Vex, EXxmm }, 0 },
10807   },
10808   {
10809     /* VEX_W_0FD4_P_2 */
10810     { "vpaddq",         { XM, Vex, EXx }, 0 },
10811   },
10812   {
10813     /* VEX_W_0FD5_P_2 */
10814     { "vpmullw",        { XM, Vex, EXx }, 0 },
10815   },
10816   {
10817     /* VEX_W_0FD6_P_2 */
10818     { "vmovq",          { EXqScalarS, XMScalar }, 0 },
10819   },
10820   {
10821     /* VEX_W_0FD7_P_2_M_1 */
10822     { "vpmovmskb",      { Gdq, XS }, 0 },
10823   },
10824   {
10825     /* VEX_W_0FD8_P_2 */
10826     { "vpsubusb",       { XM, Vex, EXx }, 0 },
10827   },
10828   {
10829     /* VEX_W_0FD9_P_2 */
10830     { "vpsubusw",       { XM, Vex, EXx }, 0 },
10831   },
10832   {
10833     /* VEX_W_0FDA_P_2 */
10834     { "vpminub",        { XM, Vex, EXx }, 0 },
10835   },
10836   {
10837     /* VEX_W_0FDB_P_2 */
10838     { "vpand",          { XM, Vex, EXx }, 0 },
10839   },
10840   {
10841     /* VEX_W_0FDC_P_2 */
10842     { "vpaddusb",       { XM, Vex, EXx }, 0 },
10843   },
10844   {
10845     /* VEX_W_0FDD_P_2 */
10846     { "vpaddusw",       { XM, Vex, EXx }, 0 },
10847   },
10848   {
10849     /* VEX_W_0FDE_P_2 */
10850     { "vpmaxub",        { XM, Vex, EXx }, 0 },
10851   },
10852   {
10853     /* VEX_W_0FDF_P_2 */
10854     { "vpandn",         { XM, Vex, EXx }, 0 },
10855   },
10856   {
10857     /* VEX_W_0FE0_P_2  */
10858     { "vpavgb",         { XM, Vex, EXx }, 0 },
10859   },
10860   {
10861     /* VEX_W_0FE1_P_2  */
10862     { "vpsraw",         { XM, Vex, EXxmm }, 0 },
10863   },
10864   {
10865     /* VEX_W_0FE2_P_2  */
10866     { "vpsrad",         { XM, Vex, EXxmm }, 0 },
10867   },
10868   {
10869     /* VEX_W_0FE3_P_2  */
10870     { "vpavgw",         { XM, Vex, EXx }, 0 },
10871   },
10872   {
10873     /* VEX_W_0FE4_P_2  */
10874     { "vpmulhuw",       { XM, Vex, EXx }, 0 },
10875   },
10876   {
10877     /* VEX_W_0FE5_P_2  */
10878     { "vpmulhw",        { XM, Vex, EXx }, 0 },
10879   },
10880   {
10881     /* VEX_W_0FE6_P_1  */
10882     { "vcvtdq2pd",      { XM, EXxmmq }, 0 },
10883   },
10884   {
10885     /* VEX_W_0FE6_P_2  */
10886     { "vcvttpd2dq%XY",  { XMM, EXx }, 0 },
10887   },
10888   {
10889     /* VEX_W_0FE6_P_3  */
10890     { "vcvtpd2dq%XY",   { XMM, EXx }, 0 },
10891   },
10892   {
10893     /* VEX_W_0FE7_P_2_M_0 */
10894     { "vmovntdq",       { Mx, XM }, 0 },
10895   },
10896   {
10897     /* VEX_W_0FE8_P_2  */
10898     { "vpsubsb",        { XM, Vex, EXx }, 0 },
10899   },
10900   {
10901     /* VEX_W_0FE9_P_2  */
10902     { "vpsubsw",        { XM, Vex, EXx }, 0 },
10903   },
10904   {
10905     /* VEX_W_0FEA_P_2  */
10906     { "vpminsw",        { XM, Vex, EXx }, 0 },
10907   },
10908   {
10909     /* VEX_W_0FEB_P_2  */
10910     { "vpor",           { XM, Vex, EXx }, 0 },
10911   },
10912   {
10913     /* VEX_W_0FEC_P_2  */
10914     { "vpaddsb",        { XM, Vex, EXx }, 0 },
10915   },
10916   {
10917     /* VEX_W_0FED_P_2  */
10918     { "vpaddsw",        { XM, Vex, EXx }, 0 },
10919   },
10920   {
10921     /* VEX_W_0FEE_P_2  */
10922     { "vpmaxsw",        { XM, Vex, EXx }, 0 },
10923   },
10924   {
10925     /* VEX_W_0FEF_P_2  */
10926     { "vpxor",          { XM, Vex, EXx }, 0 },
10927   },
10928   {
10929     /* VEX_W_0FF0_P_3_M_0 */
10930     { "vlddqu",         { XM, M }, 0 },
10931   },
10932   {
10933     /* VEX_W_0FF1_P_2 */
10934     { "vpsllw",         { XM, Vex, EXxmm }, 0 },
10935   },
10936   {
10937     /* VEX_W_0FF2_P_2 */
10938     { "vpslld",         { XM, Vex, EXxmm }, 0 },
10939   },
10940   {
10941     /* VEX_W_0FF3_P_2 */
10942     { "vpsllq",         { XM, Vex, EXxmm }, 0 },
10943   },
10944   {
10945     /* VEX_W_0FF4_P_2 */
10946     { "vpmuludq",       { XM, Vex, EXx }, 0 },
10947   },
10948   {
10949     /* VEX_W_0FF5_P_2 */
10950     { "vpmaddwd",       { XM, Vex, EXx }, 0 },
10951   },
10952   {
10953     /* VEX_W_0FF6_P_2 */
10954     { "vpsadbw",        { XM, Vex, EXx }, 0 },
10955   },
10956   {
10957     /* VEX_W_0FF7_P_2 */
10958     { "vmaskmovdqu",    { XM, XS }, 0 },
10959   },
10960   {
10961     /* VEX_W_0FF8_P_2 */
10962     { "vpsubb",         { XM, Vex, EXx }, 0 },
10963   },
10964   {
10965     /* VEX_W_0FF9_P_2 */
10966     { "vpsubw",         { XM, Vex, EXx }, 0 },
10967   },
10968   {
10969     /* VEX_W_0FFA_P_2 */
10970     { "vpsubd",         { XM, Vex, EXx }, 0 },
10971   },
10972   {
10973     /* VEX_W_0FFB_P_2 */
10974     { "vpsubq",         { XM, Vex, EXx }, 0 },
10975   },
10976   {
10977     /* VEX_W_0FFC_P_2 */
10978     { "vpaddb",         { XM, Vex, EXx }, 0 },
10979   },
10980   {
10981     /* VEX_W_0FFD_P_2 */
10982     { "vpaddw",         { XM, Vex, EXx }, 0 },
10983   },
10984   {
10985     /* VEX_W_0FFE_P_2 */
10986     { "vpaddd",         { XM, Vex, EXx }, 0 },
10987   },
10988   {
10989     /* VEX_W_0F3800_P_2  */
10990     { "vpshufb",        { XM, Vex, EXx }, 0 },
10991   },
10992   {
10993     /* VEX_W_0F3801_P_2  */
10994     { "vphaddw",        { XM, Vex, EXx }, 0 },
10995   },
10996   {
10997     /* VEX_W_0F3802_P_2  */
10998     { "vphaddd",        { XM, Vex, EXx }, 0 },
10999   },
11000   {
11001     /* VEX_W_0F3803_P_2  */
11002     { "vphaddsw",       { XM, Vex, EXx }, 0 },
11003   },
11004   {
11005     /* VEX_W_0F3804_P_2  */
11006     { "vpmaddubsw",     { XM, Vex, EXx }, 0 },
11007   },
11008   {
11009     /* VEX_W_0F3805_P_2  */
11010     { "vphsubw",        { XM, Vex, EXx }, 0 },
11011   },
11012   {
11013     /* VEX_W_0F3806_P_2  */
11014     { "vphsubd",        { XM, Vex, EXx }, 0 },
11015   },
11016   {
11017     /* VEX_W_0F3807_P_2  */
11018     { "vphsubsw",       { XM, Vex, EXx }, 0 },
11019   },
11020   {
11021     /* VEX_W_0F3808_P_2  */
11022     { "vpsignb",        { XM, Vex, EXx }, 0 },
11023   },
11024   {
11025     /* VEX_W_0F3809_P_2  */
11026     { "vpsignw",        { XM, Vex, EXx }, 0 },
11027   },
11028   {
11029     /* VEX_W_0F380A_P_2  */
11030     { "vpsignd",        { XM, Vex, EXx }, 0 },
11031   },
11032   {
11033     /* VEX_W_0F380B_P_2  */
11034     { "vpmulhrsw",      { XM, Vex, EXx }, 0 },
11035   },
11036   {
11037     /* VEX_W_0F380C_P_2  */
11038     { "vpermilps",      { XM, Vex, EXx }, 0 },
11039   },
11040   {
11041     /* VEX_W_0F380D_P_2  */
11042     { "vpermilpd",      { XM, Vex, EXx }, 0 },
11043   },
11044   {
11045     /* VEX_W_0F380E_P_2  */
11046     { "vtestps",        { XM, EXx }, 0 },
11047   },
11048   {
11049     /* VEX_W_0F380F_P_2  */
11050     { "vtestpd",        { XM, EXx }, 0 },
11051   },
11052   {
11053     /* VEX_W_0F3816_P_2  */
11054     { "vpermps",        { XM, Vex, EXx }, 0 },
11055   },
11056   {
11057     /* VEX_W_0F3817_P_2 */
11058     { "vptest",         { XM, EXx }, 0 },
11059   },
11060   {
11061     /* VEX_W_0F3818_P_2 */
11062     { "vbroadcastss",   { XM, EXxmm_md }, 0 },
11063   },
11064   {
11065     /* VEX_W_0F3819_P_2 */
11066     { "vbroadcastsd",   { XM, EXxmm_mq }, 0 },
11067   },
11068   {
11069     /* VEX_W_0F381A_P_2_M_0 */
11070     { "vbroadcastf128", { XM, Mxmm }, 0 },
11071   },
11072   {
11073     /* VEX_W_0F381C_P_2 */
11074     { "vpabsb",         { XM, EXx }, 0 },
11075   },
11076   {
11077     /* VEX_W_0F381D_P_2 */
11078     { "vpabsw",         { XM, EXx }, 0 },
11079   },
11080   {
11081     /* VEX_W_0F381E_P_2 */
11082     { "vpabsd",         { XM, EXx }, 0 },
11083   },
11084   {
11085     /* VEX_W_0F3820_P_2 */
11086     { "vpmovsxbw",      { XM, EXxmmq }, 0 },
11087   },
11088   {
11089     /* VEX_W_0F3821_P_2 */
11090     { "vpmovsxbd",      { XM, EXxmmqd }, 0 },
11091   },
11092   {
11093     /* VEX_W_0F3822_P_2 */
11094     { "vpmovsxbq",      { XM, EXxmmdw }, 0 },
11095   },
11096   {
11097     /* VEX_W_0F3823_P_2 */
11098     { "vpmovsxwd",      { XM, EXxmmq }, 0 },
11099   },
11100   {
11101     /* VEX_W_0F3824_P_2 */
11102     { "vpmovsxwq",      { XM, EXxmmqd }, 0 },
11103   },
11104   {
11105     /* VEX_W_0F3825_P_2 */
11106     { "vpmovsxdq",      { XM, EXxmmq }, 0 },
11107   },
11108   {
11109     /* VEX_W_0F3828_P_2 */
11110     { "vpmuldq",        { XM, Vex, EXx }, 0 },
11111   },
11112   {
11113     /* VEX_W_0F3829_P_2 */
11114     { "vpcmpeqq",       { XM, Vex, EXx }, 0 },
11115   },
11116   {
11117     /* VEX_W_0F382A_P_2_M_0 */
11118     { "vmovntdqa",      { XM, Mx }, 0 },
11119   },
11120   {
11121     /* VEX_W_0F382B_P_2 */
11122     { "vpackusdw",      { XM, Vex, EXx }, 0 },
11123   },
11124   {
11125     /* VEX_W_0F382C_P_2_M_0 */
11126     { "vmaskmovps",     { XM, Vex, Mx }, 0 },
11127   },
11128   {
11129     /* VEX_W_0F382D_P_2_M_0 */
11130     { "vmaskmovpd",     { XM, Vex, Mx }, 0 },
11131   },
11132   {
11133     /* VEX_W_0F382E_P_2_M_0 */
11134     { "vmaskmovps",     { Mx, Vex, XM }, 0 },
11135   },
11136   {
11137     /* VEX_W_0F382F_P_2_M_0 */
11138     { "vmaskmovpd",     { Mx, Vex, XM }, 0 },
11139   },
11140   {
11141     /* VEX_W_0F3830_P_2 */
11142     { "vpmovzxbw",      { XM, EXxmmq }, 0 },
11143   },
11144   {
11145     /* VEX_W_0F3831_P_2 */
11146     { "vpmovzxbd",      { XM, EXxmmqd }, 0 },
11147   },
11148   {
11149     /* VEX_W_0F3832_P_2 */
11150     { "vpmovzxbq",      { XM, EXxmmdw }, 0 },
11151   },
11152   {
11153     /* VEX_W_0F3833_P_2 */
11154     { "vpmovzxwd",      { XM, EXxmmq }, 0 },
11155   },
11156   {
11157     /* VEX_W_0F3834_P_2 */
11158     { "vpmovzxwq",      { XM, EXxmmqd }, 0 },
11159   },
11160   {
11161     /* VEX_W_0F3835_P_2 */
11162     { "vpmovzxdq",      { XM, EXxmmq }, 0 },
11163   },
11164   {
11165     /* VEX_W_0F3836_P_2  */
11166     { "vpermd",         { XM, Vex, EXx }, 0 },
11167   },
11168   {
11169     /* VEX_W_0F3837_P_2 */
11170     { "vpcmpgtq",       { XM, Vex, EXx }, 0 },
11171   },
11172   {
11173     /* VEX_W_0F3838_P_2 */
11174     { "vpminsb",        { XM, Vex, EXx }, 0 },
11175   },
11176   {
11177     /* VEX_W_0F3839_P_2 */
11178     { "vpminsd",        { XM, Vex, EXx }, 0 },
11179   },
11180   {
11181     /* VEX_W_0F383A_P_2 */
11182     { "vpminuw",        { XM, Vex, EXx }, 0 },
11183   },
11184   {
11185     /* VEX_W_0F383B_P_2 */
11186     { "vpminud",        { XM, Vex, EXx }, 0 },
11187   },
11188   {
11189     /* VEX_W_0F383C_P_2 */
11190     { "vpmaxsb",        { XM, Vex, EXx }, 0 },
11191   },
11192   {
11193     /* VEX_W_0F383D_P_2 */
11194     { "vpmaxsd",        { XM, Vex, EXx }, 0 },
11195   },
11196   {
11197     /* VEX_W_0F383E_P_2 */
11198     { "vpmaxuw",        { XM, Vex, EXx }, 0 },
11199   },
11200   {
11201     /* VEX_W_0F383F_P_2 */
11202     { "vpmaxud",        { XM, Vex, EXx }, 0 },
11203   },
11204   {
11205     /* VEX_W_0F3840_P_2 */
11206     { "vpmulld",        { XM, Vex, EXx }, 0 },
11207   },
11208   {
11209     /* VEX_W_0F3841_P_2 */
11210     { "vphminposuw",    { XM, EXx }, 0 },
11211   },
11212   {
11213     /* VEX_W_0F3846_P_2 */
11214     { "vpsravd",        { XM, Vex, EXx }, 0 },
11215   },
11216   {
11217     /* VEX_W_0F3858_P_2 */
11218     { "vpbroadcastd", { XM, EXxmm_md }, 0 },
11219   },
11220   {
11221     /* VEX_W_0F3859_P_2 */
11222     { "vpbroadcastq",   { XM, EXxmm_mq }, 0 },
11223   },
11224   {
11225     /* VEX_W_0F385A_P_2_M_0 */
11226     { "vbroadcasti128", { XM, Mxmm }, 0 },
11227   },
11228   {
11229     /* VEX_W_0F3878_P_2 */
11230     { "vpbroadcastb",   { XM, EXxmm_mb }, 0 },
11231   },
11232   {
11233     /* VEX_W_0F3879_P_2 */
11234     { "vpbroadcastw",   { XM, EXxmm_mw }, 0 },
11235   },
11236   {
11237     /* VEX_W_0F38DB_P_2 */
11238     { "vaesimc",        { XM, EXx }, 0 },
11239   },
11240   {
11241     /* VEX_W_0F38DC_P_2 */
11242     { "vaesenc",        { XM, Vex128, EXx }, 0 },
11243   },
11244   {
11245     /* VEX_W_0F38DD_P_2 */
11246     { "vaesenclast",    { XM, Vex128, EXx }, 0 },
11247   },
11248   {
11249     /* VEX_W_0F38DE_P_2 */
11250     { "vaesdec",        { XM, Vex128, EXx }, 0 },
11251   },
11252   {
11253     /* VEX_W_0F38DF_P_2 */
11254     { "vaesdeclast",    { XM, Vex128, EXx }, 0 },
11255   },
11256   {
11257     /* VEX_W_0F3A00_P_2 */
11258     { Bad_Opcode },
11259     { "vpermq",         { XM, EXx, Ib }, 0 },
11260   },
11261   {
11262     /* VEX_W_0F3A01_P_2 */
11263     { Bad_Opcode },
11264     { "vpermpd",        { XM, EXx, Ib }, 0 },
11265   },
11266   {
11267     /* VEX_W_0F3A02_P_2 */
11268     { "vpblendd",       { XM, Vex, EXx, Ib }, 0 },
11269   },
11270   {
11271     /* VEX_W_0F3A04_P_2 */
11272     { "vpermilps",      { XM, EXx, Ib }, 0 },
11273   },
11274   {
11275     /* VEX_W_0F3A05_P_2 */
11276     { "vpermilpd",      { XM, EXx, Ib }, 0 },
11277   },
11278   {
11279     /* VEX_W_0F3A06_P_2 */
11280     { "vperm2f128",     { XM, Vex256, EXx, Ib }, 0 },
11281   },
11282   {
11283     /* VEX_W_0F3A08_P_2 */
11284     { "vroundps",       { XM, EXx, Ib }, 0 },
11285   },
11286   {
11287     /* VEX_W_0F3A09_P_2 */
11288     { "vroundpd",       { XM, EXx, Ib }, 0 },
11289   },
11290   {
11291     /* VEX_W_0F3A0A_P_2 */
11292     { "vroundss",       { XMScalar, VexScalar, EXdScalar, Ib }, 0 },
11293   },
11294   {
11295     /* VEX_W_0F3A0B_P_2 */
11296     { "vroundsd",       { XMScalar, VexScalar, EXqScalar, Ib }, 0 },
11297   },
11298   {
11299     /* VEX_W_0F3A0C_P_2 */
11300     { "vblendps",       { XM, Vex, EXx, Ib }, 0 },
11301   },
11302   {
11303     /* VEX_W_0F3A0D_P_2 */
11304     { "vblendpd",       { XM, Vex, EXx, Ib }, 0 },
11305   },
11306   {
11307     /* VEX_W_0F3A0E_P_2 */
11308     { "vpblendw",       { XM, Vex, EXx, Ib }, 0 },
11309   },
11310   {
11311     /* VEX_W_0F3A0F_P_2 */
11312     { "vpalignr",       { XM, Vex, EXx, Ib }, 0 },
11313   },
11314   {
11315     /* VEX_W_0F3A14_P_2 */
11316     { "vpextrb",        { Edqb, XM, Ib }, 0 },
11317   },
11318   {
11319     /* VEX_W_0F3A15_P_2 */
11320     { "vpextrw",        { Edqw, XM, Ib }, 0 },
11321   },
11322   {
11323     /* VEX_W_0F3A18_P_2 */
11324     { "vinsertf128",    { XM, Vex256, EXxmm, Ib }, 0 },
11325   },
11326   {
11327     /* VEX_W_0F3A19_P_2 */
11328     { "vextractf128",   { EXxmm, XM, Ib }, 0 },
11329   },
11330   {
11331     /* VEX_W_0F3A20_P_2 */
11332     { "vpinsrb",        { XM, Vex128, Edqb, Ib }, 0 },
11333   },
11334   {
11335     /* VEX_W_0F3A21_P_2 */
11336     { "vinsertps",      { XM, Vex128, EXd, Ib }, 0 },
11337   },
11338   {
11339     /* VEX_W_0F3A30_P_2_LEN_0 */
11340     { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) },
11341     { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) },
11342   },
11343   {
11344     /* VEX_W_0F3A31_P_2_LEN_0 */
11345     { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) },
11346     { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) },
11347   },
11348   {
11349     /* VEX_W_0F3A32_P_2_LEN_0 */
11350     { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) },
11351     { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) },
11352   },
11353   {
11354     /* VEX_W_0F3A33_P_2_LEN_0 */
11355     { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) },
11356     { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) },
11357   },
11358   {
11359     /* VEX_W_0F3A38_P_2 */
11360     { "vinserti128",    { XM, Vex256, EXxmm, Ib }, 0 },
11361   },
11362   {
11363     /* VEX_W_0F3A39_P_2 */
11364     { "vextracti128",   { EXxmm, XM, Ib }, 0 },
11365   },
11366   {
11367     /* VEX_W_0F3A40_P_2 */
11368     { "vdpps",          { XM, Vex, EXx, Ib }, 0 },
11369   },
11370   {
11371     /* VEX_W_0F3A41_P_2 */
11372     { "vdppd",          { XM, Vex128, EXx, Ib }, 0 },
11373   },
11374   {
11375     /* VEX_W_0F3A42_P_2 */
11376     { "vmpsadbw",       { XM, Vex, EXx, Ib }, 0 },
11377   },
11378   {
11379     /* VEX_W_0F3A44_P_2 */
11380     { "vpclmulqdq",     { XM, Vex128, EXx, PCLMUL }, 0 },
11381   },
11382   {
11383     /* VEX_W_0F3A46_P_2 */
11384     { "vperm2i128",     { XM, Vex256, EXx, Ib }, 0 },
11385   },
11386   {
11387     /* VEX_W_0F3A48_P_2 */
11388     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11389     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11390   },
11391   {
11392     /* VEX_W_0F3A49_P_2 */
11393     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11394     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11395   },
11396   {
11397     /* VEX_W_0F3A4A_P_2 */
11398     { "vblendvps",      { XM, Vex, EXx, XMVexI4 }, 0 },
11399   },
11400   {
11401     /* VEX_W_0F3A4B_P_2 */
11402     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 }, 0 },
11403   },
11404   {
11405     /* VEX_W_0F3A4C_P_2 */
11406     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 }, 0 },
11407   },
11408   {
11409     /* VEX_W_0F3A62_P_2 */
11410     { "vpcmpistrm",     { XM, EXx, Ib }, 0 },
11411   },
11412   {
11413     /* VEX_W_0F3A63_P_2 */
11414     { "vpcmpistri",     { XM, EXx, Ib }, 0 },
11415   },
11416   {
11417     /* VEX_W_0F3ADF_P_2 */
11418     { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
11419   },
11420 #define NEED_VEX_W_TABLE
11421 #include "i386-dis-evex.h"
11422 #undef NEED_VEX_W_TABLE
11423 };
11424
11425 static const struct dis386 mod_table[][2] = {
11426   {
11427     /* MOD_8D */
11428     { "leaS",           { Gv, M }, 0 },
11429   },
11430   {
11431     /* MOD_C6_REG_7 */
11432     { Bad_Opcode },
11433     { RM_TABLE (RM_C6_REG_7) },
11434   },
11435   {
11436     /* MOD_C7_REG_7 */
11437     { Bad_Opcode },
11438     { RM_TABLE (RM_C7_REG_7) },
11439   },
11440   {
11441     /* MOD_FF_REG_3 */
11442     { "Jcall^", { indirEp }, 0 },
11443   },
11444   {
11445     /* MOD_FF_REG_5 */
11446     { "Jjmp^", { indirEp }, 0 },
11447   },
11448   {
11449     /* MOD_0F01_REG_0 */
11450     { X86_64_TABLE (X86_64_0F01_REG_0) },
11451     { RM_TABLE (RM_0F01_REG_0) },
11452   },
11453   {
11454     /* MOD_0F01_REG_1 */
11455     { X86_64_TABLE (X86_64_0F01_REG_1) },
11456     { RM_TABLE (RM_0F01_REG_1) },
11457   },
11458   {
11459     /* MOD_0F01_REG_2 */
11460     { X86_64_TABLE (X86_64_0F01_REG_2) },
11461     { RM_TABLE (RM_0F01_REG_2) },
11462   },
11463   {
11464     /* MOD_0F01_REG_3 */
11465     { X86_64_TABLE (X86_64_0F01_REG_3) },
11466     { RM_TABLE (RM_0F01_REG_3) },
11467   },
11468   {
11469     /* MOD_0F01_REG_5 */
11470     { PREFIX_TABLE (PREFIX_MOD_0_0F01_REG_5) },
11471     { RM_TABLE (RM_0F01_REG_5) },
11472   },
11473   {
11474     /* MOD_0F01_REG_7 */
11475     { "invlpg",         { Mb }, 0 },
11476     { RM_TABLE (RM_0F01_REG_7) },
11477   },
11478   {
11479     /* MOD_0F12_PREFIX_0 */
11480     { "movlps",         { XM, EXq }, PREFIX_OPCODE },
11481     { "movhlps",        { XM, EXq }, PREFIX_OPCODE },
11482   },
11483   {
11484     /* MOD_0F13 */
11485     { "movlpX",         { EXq, XM }, PREFIX_OPCODE },
11486   },
11487   {
11488     /* MOD_0F16_PREFIX_0 */
11489     { "movhps",         { XM, EXq }, 0 },
11490     { "movlhps",        { XM, EXq }, 0 },
11491   },
11492   {
11493     /* MOD_0F17 */
11494     { "movhpX",         { EXq, XM }, PREFIX_OPCODE },
11495   },
11496   {
11497     /* MOD_0F18_REG_0 */
11498     { "prefetchnta",    { Mb }, 0 },
11499   },
11500   {
11501     /* MOD_0F18_REG_1 */
11502     { "prefetcht0",     { Mb }, 0 },
11503   },
11504   {
11505     /* MOD_0F18_REG_2 */
11506     { "prefetcht1",     { Mb }, 0 },
11507   },
11508   {
11509     /* MOD_0F18_REG_3 */
11510     { "prefetcht2",     { Mb }, 0 },
11511   },
11512   {
11513     /* MOD_0F18_REG_4 */
11514     { "nop/reserved",   { Mb }, 0 },
11515   },
11516   {
11517     /* MOD_0F18_REG_5 */
11518     { "nop/reserved",   { Mb }, 0 },
11519   },
11520   {
11521     /* MOD_0F18_REG_6 */
11522     { "nop/reserved",   { Mb }, 0 },
11523   },
11524   {
11525     /* MOD_0F18_REG_7 */
11526     { "nop/reserved",   { Mb }, 0 },
11527   },
11528   {
11529     /* MOD_0F1A_PREFIX_0 */
11530     { "bndldx",         { Gbnd, Ev_bnd }, 0 },
11531     { "nopQ",           { Ev }, 0 },
11532   },
11533   {
11534     /* MOD_0F1B_PREFIX_0 */
11535     { "bndstx",         { Ev_bnd, Gbnd }, 0 },
11536     { "nopQ",           { Ev }, 0 },
11537   },
11538   {
11539     /* MOD_0F1B_PREFIX_1 */
11540     { "bndmk",          { Gbnd, Ev_bnd }, 0 },
11541     { "nopQ",           { Ev }, 0 },
11542   },
11543   {
11544     /* MOD_0F1E_PREFIX_1 */
11545     { "nopQ",           { Ev }, 0 },
11546     { REG_TABLE (REG_0F1E_MOD_3) },
11547   },
11548   {
11549     /* MOD_0F24 */
11550     { Bad_Opcode },
11551     { "movL",           { Rd, Td }, 0 },
11552   },
11553   {
11554     /* MOD_0F26 */
11555     { Bad_Opcode },
11556     { "movL",           { Td, Rd }, 0 },
11557   },
11558   {
11559     /* MOD_0F2B_PREFIX_0 */
11560     {"movntps",         { Mx, XM }, PREFIX_OPCODE },
11561   },
11562   {
11563     /* MOD_0F2B_PREFIX_1 */
11564     {"movntss",         { Md, XM }, PREFIX_OPCODE },
11565   },
11566   {
11567     /* MOD_0F2B_PREFIX_2 */
11568     {"movntpd",         { Mx, XM }, PREFIX_OPCODE },
11569   },
11570   {
11571     /* MOD_0F2B_PREFIX_3 */
11572     {"movntsd",         { Mq, XM }, PREFIX_OPCODE },
11573   },
11574   {
11575     /* MOD_0F51 */
11576     { Bad_Opcode },
11577     { "movmskpX",       { Gdq, XS }, PREFIX_OPCODE },
11578   },
11579   {
11580     /* MOD_0F71_REG_2 */
11581     { Bad_Opcode },
11582     { "psrlw",          { MS, Ib }, 0 },
11583   },
11584   {
11585     /* MOD_0F71_REG_4 */
11586     { Bad_Opcode },
11587     { "psraw",          { MS, Ib }, 0 },
11588   },
11589   {
11590     /* MOD_0F71_REG_6 */
11591     { Bad_Opcode },
11592     { "psllw",          { MS, Ib }, 0 },
11593   },
11594   {
11595     /* MOD_0F72_REG_2 */
11596     { Bad_Opcode },
11597     { "psrld",          { MS, Ib }, 0 },
11598   },
11599   {
11600     /* MOD_0F72_REG_4 */
11601     { Bad_Opcode },
11602     { "psrad",          { MS, Ib }, 0 },
11603   },
11604   {
11605     /* MOD_0F72_REG_6 */
11606     { Bad_Opcode },
11607     { "pslld",          { MS, Ib }, 0 },
11608   },
11609   {
11610     /* MOD_0F73_REG_2 */
11611     { Bad_Opcode },
11612     { "psrlq",          { MS, Ib }, 0 },
11613   },
11614   {
11615     /* MOD_0F73_REG_3 */
11616     { Bad_Opcode },
11617     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
11618   },
11619   {
11620     /* MOD_0F73_REG_6 */
11621     { Bad_Opcode },
11622     { "psllq",          { MS, Ib }, 0 },
11623   },
11624   {
11625     /* MOD_0F73_REG_7 */
11626     { Bad_Opcode },
11627     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
11628   },
11629   {
11630     /* MOD_0FAE_REG_0 */
11631     { "fxsave",         { FXSAVE }, 0 },
11632     { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
11633   },
11634   {
11635     /* MOD_0FAE_REG_1 */
11636     { "fxrstor",        { FXSAVE }, 0 },
11637     { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
11638   },
11639   {
11640     /* MOD_0FAE_REG_2 */
11641     { "ldmxcsr",        { Md }, 0 },
11642     { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
11643   },
11644   {
11645     /* MOD_0FAE_REG_3 */
11646     { "stmxcsr",        { Md }, 0 },
11647     { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
11648   },
11649   {
11650     /* MOD_0FAE_REG_4 */
11651     { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_4) },
11652     { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_4) },
11653   },
11654   {
11655     /* MOD_0FAE_REG_5 */
11656     { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_5) },
11657     { RM_TABLE (RM_0FAE_REG_5) },
11658   },
11659   {
11660     /* MOD_0FAE_REG_6 */
11661     { PREFIX_TABLE (PREFIX_0FAE_REG_6) },
11662     { RM_TABLE (RM_0FAE_REG_6) },
11663   },
11664   {
11665     /* MOD_0FAE_REG_7 */
11666     { PREFIX_TABLE (PREFIX_0FAE_REG_7) },
11667     { RM_TABLE (RM_0FAE_REG_7) },
11668   },
11669   {
11670     /* MOD_0FB2 */
11671     { "lssS",           { Gv, Mp }, 0 },
11672   },
11673   {
11674     /* MOD_0FB4 */
11675     { "lfsS",           { Gv, Mp }, 0 },
11676   },
11677   {
11678     /* MOD_0FB5 */
11679     { "lgsS",           { Gv, Mp }, 0 },
11680   },
11681   {
11682     /* MOD_0FC3 */
11683     { PREFIX_TABLE (PREFIX_MOD_0_0FC3) },
11684   },
11685   {
11686     /* MOD_0FC7_REG_3 */
11687     { "xrstors",        { FXSAVE }, 0 },
11688   },
11689   {
11690     /* MOD_0FC7_REG_4 */
11691     { "xsavec",         { FXSAVE }, 0 },
11692   },
11693   {
11694     /* MOD_0FC7_REG_5 */
11695     { "xsaves",         { FXSAVE }, 0 },
11696   },
11697   {
11698     /* MOD_0FC7_REG_6 */
11699     { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6) },
11700     { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6) }
11701   },
11702   {
11703     /* MOD_0FC7_REG_7 */
11704     { "vmptrst",        { Mq }, 0 },
11705     { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7) }
11706   },
11707   {
11708     /* MOD_0FD7 */
11709     { Bad_Opcode },
11710     { "pmovmskb",       { Gdq, MS }, 0 },
11711   },
11712   {
11713     /* MOD_0FE7_PREFIX_2 */
11714     { "movntdq",        { Mx, XM }, 0 },
11715   },
11716   {
11717     /* MOD_0FF0_PREFIX_3 */
11718     { "lddqu",          { XM, M }, 0 },
11719   },
11720   {
11721     /* MOD_0F382A_PREFIX_2 */
11722     { "movntdqa",       { XM, Mx }, 0 },
11723   },
11724   {
11725     /* MOD_0F38F5_PREFIX_2 */
11726     { "wrussK",         { M, Gdq }, PREFIX_OPCODE },
11727   },
11728   {
11729     /* MOD_0F38F6_PREFIX_0 */
11730     { "wrssK",          { M, Gdq }, PREFIX_OPCODE },
11731   },
11732   {
11733     /* MOD_62_32BIT */
11734     { "bound{S|}",      { Gv, Ma }, 0 },
11735     { EVEX_TABLE (EVEX_0F) },
11736   },
11737   {
11738     /* MOD_C4_32BIT */
11739     { "lesS",           { Gv, Mp }, 0 },
11740     { VEX_C4_TABLE (VEX_0F) },
11741   },
11742   {
11743     /* MOD_C5_32BIT */
11744     { "ldsS",           { Gv, Mp }, 0 },
11745     { VEX_C5_TABLE (VEX_0F) },
11746   },
11747   {
11748     /* MOD_VEX_0F12_PREFIX_0 */
11749     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
11750     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
11751   },
11752   {
11753     /* MOD_VEX_0F13 */
11754     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
11755   },
11756   {
11757     /* MOD_VEX_0F16_PREFIX_0 */
11758     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
11759     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
11760   },
11761   {
11762     /* MOD_VEX_0F17 */
11763     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
11764   },
11765   {
11766     /* MOD_VEX_0F2B */
11767     { VEX_W_TABLE (VEX_W_0F2B_M_0) },
11768   },
11769   {
11770     /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
11771     { Bad_Opcode },
11772     { "kandw",          { MaskG, MaskVex, MaskR }, 0 },
11773   },
11774   {
11775     /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
11776     { Bad_Opcode },
11777     { "kandq",          { MaskG, MaskVex, MaskR }, 0 },
11778   },
11779   {
11780     /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
11781     { Bad_Opcode },
11782     { "kandb",          { MaskG, MaskVex, MaskR }, 0 },
11783   },
11784   {
11785     /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
11786     { Bad_Opcode },
11787     { "kandd",          { MaskG, MaskVex, MaskR }, 0 },
11788   },
11789   {
11790     /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
11791     { Bad_Opcode },
11792     { "kandnw",         { MaskG, MaskVex, MaskR }, 0 },
11793   },
11794   {
11795     /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
11796     { Bad_Opcode },
11797     { "kandnq",         { MaskG, MaskVex, MaskR }, 0 },
11798   },
11799   {
11800     /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
11801     { Bad_Opcode },
11802     { "kandnb",         { MaskG, MaskVex, MaskR }, 0 },
11803   },
11804   {
11805     /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
11806     { Bad_Opcode },
11807     { "kandnd",         { MaskG, MaskVex, MaskR }, 0 },
11808   },
11809   {
11810     /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
11811     { Bad_Opcode },
11812     { "knotw",          { MaskG, MaskR }, 0 },
11813   },
11814   {
11815     /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
11816     { Bad_Opcode },
11817     { "knotq",          { MaskG, MaskR }, 0 },
11818   },
11819   {
11820     /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
11821     { Bad_Opcode },
11822     { "knotb",          { MaskG, MaskR }, 0 },
11823   },
11824   {
11825     /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
11826     { Bad_Opcode },
11827     { "knotd",          { MaskG, MaskR }, 0 },
11828   },
11829   {
11830     /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
11831     { Bad_Opcode },
11832     { "korw",       { MaskG, MaskVex, MaskR }, 0 },
11833   },
11834   {
11835     /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
11836     { Bad_Opcode },
11837     { "korq",       { MaskG, MaskVex, MaskR }, 0 },
11838   },
11839   {
11840     /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
11841     { Bad_Opcode },
11842     { "korb",       { MaskG, MaskVex, MaskR }, 0 },
11843   },
11844   {
11845     /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
11846     { Bad_Opcode },
11847     { "kord",       { MaskG, MaskVex, MaskR }, 0 },
11848   },
11849  {
11850     /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
11851     { Bad_Opcode },
11852     { "kxnorw",     { MaskG, MaskVex, MaskR }, 0 },
11853   },
11854   {
11855     /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
11856     { Bad_Opcode },
11857     { "kxnorq",     { MaskG, MaskVex, MaskR }, 0 },
11858   },
11859   {
11860     /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
11861     { Bad_Opcode },
11862     { "kxnorb",     { MaskG, MaskVex, MaskR }, 0 },
11863   },
11864   {
11865     /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
11866     { Bad_Opcode },
11867     { "kxnord",     { MaskG, MaskVex, MaskR }, 0 },
11868   },
11869   {
11870     /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
11871     { Bad_Opcode },
11872     { "kxorw",      { MaskG, MaskVex, MaskR }, 0 },
11873   },
11874   {
11875     /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
11876     { Bad_Opcode },
11877     { "kxorq",      { MaskG, MaskVex, MaskR }, 0 },
11878   },
11879   {
11880     /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
11881     { Bad_Opcode },
11882     { "kxorb",      { MaskG, MaskVex, MaskR }, 0 },
11883   },
11884   {
11885     /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
11886     { Bad_Opcode },
11887     { "kxord",      { MaskG, MaskVex, MaskR }, 0 },
11888   },
11889   {
11890     /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
11891     { Bad_Opcode },
11892     { "kaddw",          { MaskG, MaskVex, MaskR }, 0 },
11893   },
11894   {
11895     /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
11896     { Bad_Opcode },
11897     { "kaddq",          { MaskG, MaskVex, MaskR }, 0 },
11898   },
11899   {
11900     /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
11901     { Bad_Opcode },
11902     { "kaddb",          { MaskG, MaskVex, MaskR }, 0 },
11903   },
11904   {
11905     /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
11906     { Bad_Opcode },
11907     { "kaddd",          { MaskG, MaskVex, MaskR }, 0 },
11908   },
11909   {
11910     /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
11911     { Bad_Opcode },
11912     { "kunpckwd",   { MaskG, MaskVex, MaskR }, 0 },
11913   },
11914   {
11915     /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
11916     { Bad_Opcode },
11917     { "kunpckdq",   { MaskG, MaskVex, MaskR }, 0 },
11918   },
11919   {
11920     /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
11921     { Bad_Opcode },
11922     { "kunpckbw",   { MaskG, MaskVex, MaskR }, 0 },
11923   },
11924   {
11925     /* MOD_VEX_0F50 */
11926     { Bad_Opcode },
11927     { VEX_W_TABLE (VEX_W_0F50_M_0) },
11928   },
11929   {
11930     /* MOD_VEX_0F71_REG_2 */
11931     { Bad_Opcode },
11932     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
11933   },
11934   {
11935     /* MOD_VEX_0F71_REG_4 */
11936     { Bad_Opcode },
11937     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
11938   },
11939   {
11940     /* MOD_VEX_0F71_REG_6 */
11941     { Bad_Opcode },
11942     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
11943   },
11944   {
11945     /* MOD_VEX_0F72_REG_2 */
11946     { Bad_Opcode },
11947     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
11948   },
11949   {
11950     /* MOD_VEX_0F72_REG_4 */
11951     { Bad_Opcode },
11952     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
11953   },
11954   {
11955     /* MOD_VEX_0F72_REG_6 */
11956     { Bad_Opcode },
11957     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
11958   },
11959   {
11960     /* MOD_VEX_0F73_REG_2 */
11961     { Bad_Opcode },
11962     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
11963   },
11964   {
11965     /* MOD_VEX_0F73_REG_3 */
11966     { Bad_Opcode },
11967     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
11968   },
11969   {
11970     /* MOD_VEX_0F73_REG_6 */
11971     { Bad_Opcode },
11972     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
11973   },
11974   {
11975     /* MOD_VEX_0F73_REG_7 */
11976     { Bad_Opcode },
11977     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
11978   },
11979   {
11980     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
11981     { "kmovw",          { Ew, MaskG }, 0 },
11982     { Bad_Opcode },
11983   },
11984   {
11985     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
11986     { "kmovq",          { Eq, MaskG }, 0 },
11987     { Bad_Opcode },
11988   },
11989   {
11990     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
11991     { "kmovb",          { Eb, MaskG }, 0 },
11992     { Bad_Opcode },
11993   },
11994   {
11995     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
11996     { "kmovd",          { Ed, MaskG }, 0 },
11997     { Bad_Opcode },
11998   },
11999   {
12000     /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
12001     { Bad_Opcode },
12002     { "kmovw",          { MaskG, Rdq }, 0 },
12003   },
12004   {
12005     /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
12006     { Bad_Opcode },
12007     { "kmovb",          { MaskG, Rdq }, 0 },
12008   },
12009   {
12010     /* MOD_VEX_W_0_0F92_P_3_LEN_0 */
12011     { Bad_Opcode },
12012     { "kmovd",          { MaskG, Rdq }, 0 },
12013   },
12014   {
12015     /* MOD_VEX_W_1_0F92_P_3_LEN_0 */
12016     { Bad_Opcode },
12017     { "kmovq",          { MaskG, Rdq }, 0 },
12018   },
12019   {
12020     /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
12021     { Bad_Opcode },
12022     { "kmovw",          { Gdq, MaskR }, 0 },
12023   },
12024   {
12025     /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
12026     { Bad_Opcode },
12027     { "kmovb",          { Gdq, MaskR }, 0 },
12028   },
12029   {
12030     /* MOD_VEX_W_0_0F93_P_3_LEN_0 */
12031     { Bad_Opcode },
12032     { "kmovd",          { Gdq, MaskR }, 0 },
12033   },
12034   {
12035     /* MOD_VEX_W_1_0F93_P_3_LEN_0 */
12036     { Bad_Opcode },
12037     { "kmovq",          { Gdq, MaskR }, 0 },
12038   },
12039   {
12040     /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
12041     { Bad_Opcode },
12042     { "kortestw", { MaskG, MaskR }, 0 },
12043   },
12044   {
12045     /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
12046     { Bad_Opcode },
12047     { "kortestq", { MaskG, MaskR }, 0 },
12048   },
12049   {
12050     /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
12051     { Bad_Opcode },
12052     { "kortestb", { MaskG, MaskR }, 0 },
12053   },
12054   {
12055     /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
12056     { Bad_Opcode },
12057     { "kortestd", { MaskG, MaskR }, 0 },
12058   },
12059   {
12060     /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
12061     { Bad_Opcode },
12062     { "ktestw", { MaskG, MaskR }, 0 },
12063   },
12064   {
12065     /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
12066     { Bad_Opcode },
12067     { "ktestq", { MaskG, MaskR }, 0 },
12068   },
12069   {
12070     /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
12071     { Bad_Opcode },
12072     { "ktestb", { MaskG, MaskR }, 0 },
12073   },
12074   {
12075     /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
12076     { Bad_Opcode },
12077     { "ktestd", { MaskG, MaskR }, 0 },
12078   },
12079   {
12080     /* MOD_VEX_0FAE_REG_2 */
12081     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
12082   },
12083   {
12084     /* MOD_VEX_0FAE_REG_3 */
12085     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
12086   },
12087   {
12088     /* MOD_VEX_0FD7_PREFIX_2 */
12089     { Bad_Opcode },
12090     { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) },
12091   },
12092   {
12093     /* MOD_VEX_0FE7_PREFIX_2 */
12094     { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) },
12095   },
12096   {
12097     /* MOD_VEX_0FF0_PREFIX_3 */
12098     { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) },
12099   },
12100   {
12101     /* MOD_VEX_0F381A_PREFIX_2 */
12102     { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
12103   },
12104   {
12105     /* MOD_VEX_0F382A_PREFIX_2 */
12106     { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) },
12107   },
12108   {
12109     /* MOD_VEX_0F382C_PREFIX_2 */
12110     { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
12111   },
12112   {
12113     /* MOD_VEX_0F382D_PREFIX_2 */
12114     { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
12115   },
12116   {
12117     /* MOD_VEX_0F382E_PREFIX_2 */
12118     { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
12119   },
12120   {
12121     /* MOD_VEX_0F382F_PREFIX_2 */
12122     { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
12123   },
12124   {
12125     /* MOD_VEX_0F385A_PREFIX_2 */
12126     { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
12127   },
12128   {
12129     /* MOD_VEX_0F388C_PREFIX_2 */
12130     { "vpmaskmov%LW",   { XM, Vex, Mx }, 0 },
12131   },
12132   {
12133     /* MOD_VEX_0F388E_PREFIX_2 */
12134     { "vpmaskmov%LW",   { Mx, Vex, XM }, 0 },
12135   },
12136   {
12137     /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
12138     { Bad_Opcode },
12139     { "kshiftrb",       { MaskG, MaskR, Ib }, 0 },
12140   },
12141   {
12142     /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
12143     { Bad_Opcode },
12144     { "kshiftrw",       { MaskG, MaskR, Ib }, 0 },
12145   },
12146   {
12147     /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
12148     { Bad_Opcode },
12149     { "kshiftrd",       { MaskG, MaskR, Ib }, 0 },
12150   },
12151   {
12152     /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
12153     { Bad_Opcode },
12154     { "kshiftrq",       { MaskG, MaskR, Ib }, 0 },
12155   },
12156   {
12157     /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
12158     { Bad_Opcode },
12159     { "kshiftlb",       { MaskG, MaskR, Ib }, 0 },
12160   },
12161   {
12162     /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
12163     { Bad_Opcode },
12164     { "kshiftlw",       { MaskG, MaskR, Ib }, 0 },
12165   },
12166   {
12167     /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
12168     { Bad_Opcode },
12169     { "kshiftld",       { MaskG, MaskR, Ib }, 0 },
12170   },
12171   {
12172     /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
12173     { Bad_Opcode },
12174     { "kshiftlq",       { MaskG, MaskR, Ib }, 0 },
12175   },
12176 #define NEED_MOD_TABLE
12177 #include "i386-dis-evex.h"
12178 #undef NEED_MOD_TABLE
12179 };
12180
12181 static const struct dis386 rm_table[][8] = {
12182   {
12183     /* RM_C6_REG_7 */
12184     { "xabort",         { Skip_MODRM, Ib }, 0 },
12185   },
12186   {
12187     /* RM_C7_REG_7 */
12188     { "xbeginT",        { Skip_MODRM, Jv }, 0 },
12189   },
12190   {
12191     /* RM_0F01_REG_0 */
12192     { Bad_Opcode },
12193     { "vmcall",         { Skip_MODRM }, 0 },
12194     { "vmlaunch",       { Skip_MODRM }, 0 },
12195     { "vmresume",       { Skip_MODRM }, 0 },
12196     { "vmxoff",         { Skip_MODRM }, 0 },
12197   },
12198   {
12199     /* RM_0F01_REG_1 */
12200     { "monitor",        { { OP_Monitor, 0 } }, 0 },
12201     { "mwait",          { { OP_Mwait, 0 } }, 0 },
12202     { "clac",           { Skip_MODRM }, 0 },
12203     { "stac",           { Skip_MODRM }, 0 },
12204     { Bad_Opcode },
12205     { Bad_Opcode },
12206     { Bad_Opcode },
12207     { "encls",          { Skip_MODRM }, 0 },
12208   },
12209   {
12210     /* RM_0F01_REG_2 */
12211     { "xgetbv",         { Skip_MODRM }, 0 },
12212     { "xsetbv",         { Skip_MODRM }, 0 },
12213     { Bad_Opcode },
12214     { Bad_Opcode },
12215     { "vmfunc",         { Skip_MODRM }, 0 },
12216     { "xend",           { Skip_MODRM }, 0 },
12217     { "xtest",          { Skip_MODRM }, 0 },
12218     { "enclu",          { Skip_MODRM }, 0 },
12219   },
12220   {
12221     /* RM_0F01_REG_3 */
12222     { "vmrun",          { Skip_MODRM }, 0 },
12223     { "vmmcall",        { Skip_MODRM }, 0 },
12224     { "vmload",         { Skip_MODRM }, 0 },
12225     { "vmsave",         { Skip_MODRM }, 0 },
12226     { "stgi",           { Skip_MODRM }, 0 },
12227     { "clgi",           { Skip_MODRM }, 0 },
12228     { "skinit",         { Skip_MODRM }, 0 },
12229     { "invlpga",        { Skip_MODRM }, 0 },
12230   },
12231   {
12232     /* RM_0F01_REG_5 */
12233     { Bad_Opcode },
12234     { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_1) },
12235     { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_2) },
12236     { Bad_Opcode },
12237     { Bad_Opcode },
12238     { Bad_Opcode },
12239     { "rdpkru",         { Skip_MODRM }, 0 },
12240     { "wrpkru",         { Skip_MODRM }, 0 },
12241   },
12242   {
12243     /* RM_0F01_REG_7 */
12244     { "swapgs",         { Skip_MODRM }, 0  },
12245     { "rdtscp",         { Skip_MODRM }, 0  },
12246     { "monitorx",       { { OP_Monitor, 0 } }, 0  },
12247     { "mwaitx",         { { OP_Mwaitx,  0 } }, 0  },
12248     { "clzero",         { Skip_MODRM }, 0  },
12249   },
12250   {
12251     /* RM_0F1E_MOD_3_REG_7 */
12252     { "nopQ",           { Ev }, 0 },
12253     { "nopQ",           { Ev }, 0 },
12254     { "endbr64",        { Skip_MODRM },  PREFIX_OPCODE },
12255     { "endbr32",        { Skip_MODRM },  PREFIX_OPCODE },
12256     { "nopQ",           { Ev }, 0 },
12257     { "nopQ",           { Ev }, 0 },
12258     { "nopQ",           { Ev }, 0 },
12259     { "nopQ",           { Ev }, 0 },
12260   },
12261   {
12262     /* RM_0FAE_REG_5 */
12263     { "lfence",         { Skip_MODRM }, 0 },
12264   },
12265   {
12266     /* RM_0FAE_REG_6 */
12267     { "mfence",         { Skip_MODRM }, 0 },
12268   },
12269   {
12270     /* RM_0FAE_REG_7 */
12271     { "sfence",         { Skip_MODRM }, 0 },
12272
12273   },
12274 };
12275
12276 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
12277
12278 /* We use the high bit to indicate different name for the same
12279    prefix.  */
12280 #define REP_PREFIX      (0xf3 | 0x100)
12281 #define XACQUIRE_PREFIX (0xf2 | 0x200)
12282 #define XRELEASE_PREFIX (0xf3 | 0x400)
12283 #define BND_PREFIX      (0xf2 | 0x400)
12284
12285 static int
12286 ckprefix (void)
12287 {
12288   int newrex, i, length;
12289   rex = 0;
12290   rex_ignored = 0;
12291   prefixes = 0;
12292   used_prefixes = 0;
12293   rex_used = 0;
12294   last_lock_prefix = -1;
12295   last_repz_prefix = -1;
12296   last_repnz_prefix = -1;
12297   last_data_prefix = -1;
12298   last_addr_prefix = -1;
12299   last_rex_prefix = -1;
12300   last_seg_prefix = -1;
12301   fwait_prefix = -1;
12302   active_seg_prefix = 0;
12303   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12304     all_prefixes[i] = 0;
12305   i = 0;
12306   length = 0;
12307   /* The maximum instruction length is 15bytes.  */
12308   while (length < MAX_CODE_LENGTH - 1)
12309     {
12310       FETCH_DATA (the_info, codep + 1);
12311       newrex = 0;
12312       switch (*codep)
12313         {
12314         /* REX prefixes family.  */
12315         case 0x40:
12316         case 0x41:
12317         case 0x42:
12318         case 0x43:
12319         case 0x44:
12320         case 0x45:
12321         case 0x46:
12322         case 0x47:
12323         case 0x48:
12324         case 0x49:
12325         case 0x4a:
12326         case 0x4b:
12327         case 0x4c:
12328         case 0x4d:
12329         case 0x4e:
12330         case 0x4f:
12331           if (address_mode == mode_64bit)
12332             newrex = *codep;
12333           else
12334             return 1;
12335           last_rex_prefix = i;
12336           break;
12337         case 0xf3:
12338           prefixes |= PREFIX_REPZ;
12339           last_repz_prefix = i;
12340           break;
12341         case 0xf2:
12342           prefixes |= PREFIX_REPNZ;
12343           last_repnz_prefix = i;
12344           break;
12345         case 0xf0:
12346           prefixes |= PREFIX_LOCK;
12347           last_lock_prefix = i;
12348           break;
12349         case 0x2e:
12350           prefixes |= PREFIX_CS;
12351           last_seg_prefix = i;
12352           active_seg_prefix = PREFIX_CS;
12353           break;
12354         case 0x36:
12355           prefixes |= PREFIX_SS;
12356           last_seg_prefix = i;
12357           active_seg_prefix = PREFIX_SS;
12358           break;
12359         case 0x3e:
12360           prefixes |= PREFIX_DS;
12361           last_seg_prefix = i;
12362           active_seg_prefix = PREFIX_DS;
12363           break;
12364         case 0x26:
12365           prefixes |= PREFIX_ES;
12366           last_seg_prefix = i;
12367           active_seg_prefix = PREFIX_ES;
12368           break;
12369         case 0x64:
12370           prefixes |= PREFIX_FS;
12371           last_seg_prefix = i;
12372           active_seg_prefix = PREFIX_FS;
12373           break;
12374         case 0x65:
12375           prefixes |= PREFIX_GS;
12376           last_seg_prefix = i;
12377           active_seg_prefix = PREFIX_GS;
12378           break;
12379         case 0x66:
12380           prefixes |= PREFIX_DATA;
12381           last_data_prefix = i;
12382           break;
12383         case 0x67:
12384           prefixes |= PREFIX_ADDR;
12385           last_addr_prefix = i;
12386           break;
12387         case FWAIT_OPCODE:
12388           /* fwait is really an instruction.  If there are prefixes
12389              before the fwait, they belong to the fwait, *not* to the
12390              following instruction.  */
12391           fwait_prefix = i;
12392           if (prefixes || rex)
12393             {
12394               prefixes |= PREFIX_FWAIT;
12395               codep++;
12396               /* This ensures that the previous REX prefixes are noticed
12397                  as unused prefixes, as in the return case below.  */
12398               rex_used = rex;
12399               return 1;
12400             }
12401           prefixes = PREFIX_FWAIT;
12402           break;
12403         default:
12404           return 1;
12405         }
12406       /* Rex is ignored when followed by another prefix.  */
12407       if (rex)
12408         {
12409           rex_used = rex;
12410           return 1;
12411         }
12412       if (*codep != FWAIT_OPCODE)
12413         all_prefixes[i++] = *codep;
12414       rex = newrex;
12415       codep++;
12416       length++;
12417     }
12418   return 0;
12419 }
12420
12421 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
12422    prefix byte.  */
12423
12424 static const char *
12425 prefix_name (int pref, int sizeflag)
12426 {
12427   static const char *rexes [16] =
12428     {
12429       "rex",            /* 0x40 */
12430       "rex.B",          /* 0x41 */
12431       "rex.X",          /* 0x42 */
12432       "rex.XB",         /* 0x43 */
12433       "rex.R",          /* 0x44 */
12434       "rex.RB",         /* 0x45 */
12435       "rex.RX",         /* 0x46 */
12436       "rex.RXB",        /* 0x47 */
12437       "rex.W",          /* 0x48 */
12438       "rex.WB",         /* 0x49 */
12439       "rex.WX",         /* 0x4a */
12440       "rex.WXB",        /* 0x4b */
12441       "rex.WR",         /* 0x4c */
12442       "rex.WRB",        /* 0x4d */
12443       "rex.WRX",        /* 0x4e */
12444       "rex.WRXB",       /* 0x4f */
12445     };
12446
12447   switch (pref)
12448     {
12449     /* REX prefixes family.  */
12450     case 0x40:
12451     case 0x41:
12452     case 0x42:
12453     case 0x43:
12454     case 0x44:
12455     case 0x45:
12456     case 0x46:
12457     case 0x47:
12458     case 0x48:
12459     case 0x49:
12460     case 0x4a:
12461     case 0x4b:
12462     case 0x4c:
12463     case 0x4d:
12464     case 0x4e:
12465     case 0x4f:
12466       return rexes [pref - 0x40];
12467     case 0xf3:
12468       return "repz";
12469     case 0xf2:
12470       return "repnz";
12471     case 0xf0:
12472       return "lock";
12473     case 0x2e:
12474       return "cs";
12475     case 0x36:
12476       return "ss";
12477     case 0x3e:
12478       return "ds";
12479     case 0x26:
12480       return "es";
12481     case 0x64:
12482       return "fs";
12483     case 0x65:
12484       return "gs";
12485     case 0x66:
12486       return (sizeflag & DFLAG) ? "data16" : "data32";
12487     case 0x67:
12488       if (address_mode == mode_64bit)
12489         return (sizeflag & AFLAG) ? "addr32" : "addr64";
12490       else
12491         return (sizeflag & AFLAG) ? "addr16" : "addr32";
12492     case FWAIT_OPCODE:
12493       return "fwait";
12494     case REP_PREFIX:
12495       return "rep";
12496     case XACQUIRE_PREFIX:
12497       return "xacquire";
12498     case XRELEASE_PREFIX:
12499       return "xrelease";
12500     case BND_PREFIX:
12501       return "bnd";
12502     default:
12503       return NULL;
12504     }
12505 }
12506
12507 static char op_out[MAX_OPERANDS][100];
12508 static int op_ad, op_index[MAX_OPERANDS];
12509 static int two_source_ops;
12510 static bfd_vma op_address[MAX_OPERANDS];
12511 static bfd_vma op_riprel[MAX_OPERANDS];
12512 static bfd_vma start_pc;
12513
12514 /*
12515  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
12516  *   (see topic "Redundant prefixes" in the "Differences from 8086"
12517  *   section of the "Virtual 8086 Mode" chapter.)
12518  * 'pc' should be the address of this instruction, it will
12519  *   be used to print the target address if this is a relative jump or call
12520  * The function returns the length of this instruction in bytes.
12521  */
12522
12523 static char intel_syntax;
12524 static char intel_mnemonic = !SYSV386_COMPAT;
12525 static char open_char;
12526 static char close_char;
12527 static char separator_char;
12528 static char scale_char;
12529
12530 enum x86_64_isa
12531 {
12532   amd64 = 0,
12533   intel64
12534 };
12535
12536 static enum x86_64_isa isa64;
12537
12538 /* Here for backwards compatibility.  When gdb stops using
12539    print_insn_i386_att and print_insn_i386_intel these functions can
12540    disappear, and print_insn_i386 be merged into print_insn.  */
12541 int
12542 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
12543 {
12544   intel_syntax = 0;
12545
12546   return print_insn (pc, info);
12547 }
12548
12549 int
12550 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
12551 {
12552   intel_syntax = 1;
12553
12554   return print_insn (pc, info);
12555 }
12556
12557 int
12558 print_insn_i386 (bfd_vma pc, disassemble_info *info)
12559 {
12560   intel_syntax = -1;
12561
12562   return print_insn (pc, info);
12563 }
12564
12565 void
12566 print_i386_disassembler_options (FILE *stream)
12567 {
12568   fprintf (stream, _("\n\
12569 The following i386/x86-64 specific disassembler options are supported for use\n\
12570 with the -M switch (multiple options should be separated by commas):\n"));
12571
12572   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
12573   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
12574   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
12575   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
12576   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
12577   fprintf (stream, _("  att-mnemonic\n"
12578                      "              Display instruction in AT&T mnemonic\n"));
12579   fprintf (stream, _("  intel-mnemonic\n"
12580                      "              Display instruction in Intel mnemonic\n"));
12581   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
12582   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
12583   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
12584   fprintf (stream, _("  data32      Assume 32bit data size\n"));
12585   fprintf (stream, _("  data16      Assume 16bit data size\n"));
12586   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
12587   fprintf (stream, _("  amd64       Display instruction in AMD64 ISA\n"));
12588   fprintf (stream, _("  intel64     Display instruction in Intel64 ISA\n"));
12589 }
12590
12591 /* Bad opcode.  */
12592 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
12593
12594 /* Get a pointer to struct dis386 with a valid name.  */
12595
12596 static const struct dis386 *
12597 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
12598 {
12599   int vindex, vex_table_index;
12600
12601   if (dp->name != NULL)
12602     return dp;
12603
12604   switch (dp->op[0].bytemode)
12605     {
12606     case USE_REG_TABLE:
12607       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
12608       break;
12609
12610     case USE_MOD_TABLE:
12611       vindex = modrm.mod == 0x3 ? 1 : 0;
12612       dp = &mod_table[dp->op[1].bytemode][vindex];
12613       break;
12614
12615     case USE_RM_TABLE:
12616       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
12617       break;
12618
12619     case USE_PREFIX_TABLE:
12620       if (need_vex)
12621         {
12622           /* The prefix in VEX is implicit.  */
12623           switch (vex.prefix)
12624             {
12625             case 0:
12626               vindex = 0;
12627               break;
12628             case REPE_PREFIX_OPCODE:
12629               vindex = 1;
12630               break;
12631             case DATA_PREFIX_OPCODE:
12632               vindex = 2;
12633               break;
12634             case REPNE_PREFIX_OPCODE:
12635               vindex = 3;
12636               break;
12637             default:
12638               abort ();
12639               break;
12640             }
12641         }
12642       else
12643         {
12644           int last_prefix = -1;
12645           int prefix = 0;
12646           vindex = 0;
12647           /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
12648              When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
12649              last one wins.  */
12650           if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
12651             {
12652               if (last_repz_prefix > last_repnz_prefix)
12653                 {
12654                   vindex = 1;
12655                   prefix = PREFIX_REPZ;
12656                   last_prefix = last_repz_prefix;
12657                 }
12658               else
12659                 {
12660                   vindex = 3;
12661                   prefix = PREFIX_REPNZ;
12662                   last_prefix = last_repnz_prefix;
12663                 }
12664
12665               /* Check if prefix should be ignored.  */
12666               if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
12667                      & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
12668                    & prefix) != 0)
12669                 vindex = 0;
12670             }
12671
12672           if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
12673             {
12674               vindex = 2;
12675               prefix = PREFIX_DATA;
12676               last_prefix = last_data_prefix;
12677             }
12678
12679           if (vindex != 0)
12680             {
12681               used_prefixes |= prefix;
12682               all_prefixes[last_prefix] = 0;
12683             }
12684         }
12685       dp = &prefix_table[dp->op[1].bytemode][vindex];
12686       break;
12687
12688     case USE_X86_64_TABLE:
12689       vindex = address_mode == mode_64bit ? 1 : 0;
12690       dp = &x86_64_table[dp->op[1].bytemode][vindex];
12691       break;
12692
12693     case USE_3BYTE_TABLE:
12694       FETCH_DATA (info, codep + 2);
12695       vindex = *codep++;
12696       dp = &three_byte_table[dp->op[1].bytemode][vindex];
12697       end_codep = codep;
12698       modrm.mod = (*codep >> 6) & 3;
12699       modrm.reg = (*codep >> 3) & 7;
12700       modrm.rm = *codep & 7;
12701       break;
12702
12703     case USE_VEX_LEN_TABLE:
12704       if (!need_vex)
12705         abort ();
12706
12707       switch (vex.length)
12708         {
12709         case 128:
12710           vindex = 0;
12711           break;
12712         case 256:
12713           vindex = 1;
12714           break;
12715         default:
12716           abort ();
12717           break;
12718         }
12719
12720       dp = &vex_len_table[dp->op[1].bytemode][vindex];
12721       break;
12722
12723     case USE_XOP_8F_TABLE:
12724       FETCH_DATA (info, codep + 3);
12725       /* All bits in the REX prefix are ignored.  */
12726       rex_ignored = rex;
12727       rex = ~(*codep >> 5) & 0x7;
12728
12729       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
12730       switch ((*codep & 0x1f))
12731         {
12732         default:
12733           dp = &bad_opcode;
12734           return dp;
12735         case 0x8:
12736           vex_table_index = XOP_08;
12737           break;
12738         case 0x9:
12739           vex_table_index = XOP_09;
12740           break;
12741         case 0xa:
12742           vex_table_index = XOP_0A;
12743           break;
12744         }
12745       codep++;
12746       vex.w = *codep & 0x80;
12747       if (vex.w && address_mode == mode_64bit)
12748         rex |= REX_W;
12749
12750       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12751       if (address_mode != mode_64bit)
12752         {
12753           /* In 16/32-bit mode REX_B is silently ignored.  */
12754           rex &= ~REX_B;
12755           if (vex.register_specifier > 0x7)
12756             {
12757               dp = &bad_opcode;
12758               return dp;
12759             }
12760         }
12761
12762       vex.length = (*codep & 0x4) ? 256 : 128;
12763       switch ((*codep & 0x3))
12764         {
12765         case 0:
12766           vex.prefix = 0;
12767           break;
12768         case 1:
12769           vex.prefix = DATA_PREFIX_OPCODE;
12770           break;
12771         case 2:
12772           vex.prefix = REPE_PREFIX_OPCODE;
12773           break;
12774         case 3:
12775           vex.prefix = REPNE_PREFIX_OPCODE;
12776           break;
12777         }
12778       need_vex = 1;
12779       need_vex_reg = 1;
12780       codep++;
12781       vindex = *codep++;
12782       dp = &xop_table[vex_table_index][vindex];
12783
12784       end_codep = codep;
12785       FETCH_DATA (info, codep + 1);
12786       modrm.mod = (*codep >> 6) & 3;
12787       modrm.reg = (*codep >> 3) & 7;
12788       modrm.rm = *codep & 7;
12789       break;
12790
12791     case USE_VEX_C4_TABLE:
12792       /* VEX prefix.  */
12793       FETCH_DATA (info, codep + 3);
12794       /* All bits in the REX prefix are ignored.  */
12795       rex_ignored = rex;
12796       rex = ~(*codep >> 5) & 0x7;
12797       switch ((*codep & 0x1f))
12798         {
12799         default:
12800           dp = &bad_opcode;
12801           return dp;
12802         case 0x1:
12803           vex_table_index = VEX_0F;
12804           break;
12805         case 0x2:
12806           vex_table_index = VEX_0F38;
12807           break;
12808         case 0x3:
12809           vex_table_index = VEX_0F3A;
12810           break;
12811         }
12812       codep++;
12813       vex.w = *codep & 0x80;
12814       if (address_mode == mode_64bit)
12815         {
12816           if (vex.w)
12817             rex |= REX_W;
12818           vex.register_specifier = (~(*codep >> 3)) & 0xf;
12819         }
12820       else
12821         {
12822           /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
12823              is ignored, other REX bits are 0 and the highest bit in
12824              VEX.vvvv is also ignored.  */
12825           rex = 0;
12826           vex.register_specifier = (~(*codep >> 3)) & 0x7;
12827         }
12828       vex.length = (*codep & 0x4) ? 256 : 128;
12829       switch ((*codep & 0x3))
12830         {
12831         case 0:
12832           vex.prefix = 0;
12833           break;
12834         case 1:
12835           vex.prefix = DATA_PREFIX_OPCODE;
12836           break;
12837         case 2:
12838           vex.prefix = REPE_PREFIX_OPCODE;
12839           break;
12840         case 3:
12841           vex.prefix = REPNE_PREFIX_OPCODE;
12842           break;
12843         }
12844       need_vex = 1;
12845       need_vex_reg = 1;
12846       codep++;
12847       vindex = *codep++;
12848       dp = &vex_table[vex_table_index][vindex];
12849       end_codep = codep;
12850       /* There is no MODRM byte for VEX0F 77.  */
12851       if (vex_table_index != VEX_0F || vindex != 0x77)
12852         {
12853           FETCH_DATA (info, codep + 1);
12854           modrm.mod = (*codep >> 6) & 3;
12855           modrm.reg = (*codep >> 3) & 7;
12856           modrm.rm = *codep & 7;
12857         }
12858       break;
12859
12860     case USE_VEX_C5_TABLE:
12861       /* VEX prefix.  */
12862       FETCH_DATA (info, codep + 2);
12863       /* All bits in the REX prefix are ignored.  */
12864       rex_ignored = rex;
12865       rex = (*codep & 0x80) ? 0 : REX_R;
12866
12867       /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
12868          VEX.vvvv is 1.  */
12869       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12870       vex.w = 0;
12871       vex.length = (*codep & 0x4) ? 256 : 128;
12872       switch ((*codep & 0x3))
12873         {
12874         case 0:
12875           vex.prefix = 0;
12876           break;
12877         case 1:
12878           vex.prefix = DATA_PREFIX_OPCODE;
12879           break;
12880         case 2:
12881           vex.prefix = REPE_PREFIX_OPCODE;
12882           break;
12883         case 3:
12884           vex.prefix = REPNE_PREFIX_OPCODE;
12885           break;
12886         }
12887       need_vex = 1;
12888       need_vex_reg = 1;
12889       codep++;
12890       vindex = *codep++;
12891       dp = &vex_table[dp->op[1].bytemode][vindex];
12892       end_codep = codep;
12893       /* There is no MODRM byte for VEX 77.  */
12894       if (vindex != 0x77)
12895         {
12896           FETCH_DATA (info, codep + 1);
12897           modrm.mod = (*codep >> 6) & 3;
12898           modrm.reg = (*codep >> 3) & 7;
12899           modrm.rm = *codep & 7;
12900         }
12901       break;
12902
12903     case USE_VEX_W_TABLE:
12904       if (!need_vex)
12905         abort ();
12906
12907       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
12908       break;
12909
12910     case USE_EVEX_TABLE:
12911       two_source_ops = 0;
12912       /* EVEX prefix.  */
12913       vex.evex = 1;
12914       FETCH_DATA (info, codep + 4);
12915       /* All bits in the REX prefix are ignored.  */
12916       rex_ignored = rex;
12917       /* The first byte after 0x62.  */
12918       rex = ~(*codep >> 5) & 0x7;
12919       vex.r = *codep & 0x10;
12920       switch ((*codep & 0xf))
12921         {
12922         default:
12923           return &bad_opcode;
12924         case 0x1:
12925           vex_table_index = EVEX_0F;
12926           break;
12927         case 0x2:
12928           vex_table_index = EVEX_0F38;
12929           break;
12930         case 0x3:
12931           vex_table_index = EVEX_0F3A;
12932           break;
12933         }
12934
12935       /* The second byte after 0x62.  */
12936       codep++;
12937       vex.w = *codep & 0x80;
12938       if (vex.w && address_mode == mode_64bit)
12939         rex |= REX_W;
12940
12941       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12942       if (address_mode != mode_64bit)
12943         {
12944           /* In 16/32-bit mode silently ignore following bits.  */
12945           rex &= ~REX_B;
12946           vex.r = 1;
12947           vex.v = 1;
12948           vex.register_specifier &= 0x7;
12949         }
12950
12951       /* The U bit.  */
12952       if (!(*codep & 0x4))
12953         return &bad_opcode;
12954
12955       switch ((*codep & 0x3))
12956         {
12957         case 0:
12958           vex.prefix = 0;
12959           break;
12960         case 1:
12961           vex.prefix = DATA_PREFIX_OPCODE;
12962           break;
12963         case 2:
12964           vex.prefix = REPE_PREFIX_OPCODE;
12965           break;
12966         case 3:
12967           vex.prefix = REPNE_PREFIX_OPCODE;
12968           break;
12969         }
12970
12971       /* The third byte after 0x62.  */
12972       codep++;
12973
12974       /* Remember the static rounding bits.  */
12975       vex.ll = (*codep >> 5) & 3;
12976       vex.b = (*codep & 0x10) != 0;
12977
12978       vex.v = *codep & 0x8;
12979       vex.mask_register_specifier = *codep & 0x7;
12980       vex.zeroing = *codep & 0x80;
12981
12982       need_vex = 1;
12983       need_vex_reg = 1;
12984       codep++;
12985       vindex = *codep++;
12986       dp = &evex_table[vex_table_index][vindex];
12987       end_codep = codep;
12988       FETCH_DATA (info, codep + 1);
12989       modrm.mod = (*codep >> 6) & 3;
12990       modrm.reg = (*codep >> 3) & 7;
12991       modrm.rm = *codep & 7;
12992
12993       /* Set vector length.  */
12994       if (modrm.mod == 3 && vex.b)
12995         vex.length = 512;
12996       else
12997         {
12998           switch (vex.ll)
12999             {
13000             case 0x0:
13001               vex.length = 128;
13002               break;
13003             case 0x1:
13004               vex.length = 256;
13005               break;
13006             case 0x2:
13007               vex.length = 512;
13008               break;
13009             default:
13010               return &bad_opcode;
13011             }
13012         }
13013       break;
13014
13015     case 0:
13016       dp = &bad_opcode;
13017       break;
13018
13019     default:
13020       abort ();
13021     }
13022
13023   if (dp->name != NULL)
13024     return dp;
13025   else
13026     return get_valid_dis386 (dp, info);
13027 }
13028
13029 static void
13030 get_sib (disassemble_info *info, int sizeflag)
13031 {
13032   /* If modrm.mod == 3, operand must be register.  */
13033   if (need_modrm
13034       && ((sizeflag & AFLAG) || address_mode == mode_64bit)
13035       && modrm.mod != 3
13036       && modrm.rm == 4)
13037     {
13038       FETCH_DATA (info, codep + 2);
13039       sib.index = (codep [1] >> 3) & 7;
13040       sib.scale = (codep [1] >> 6) & 3;
13041       sib.base = codep [1] & 7;
13042     }
13043 }
13044
13045 static int
13046 print_insn (bfd_vma pc, disassemble_info *info)
13047 {
13048   const struct dis386 *dp;
13049   int i;
13050   char *op_txt[MAX_OPERANDS];
13051   int needcomma;
13052   int sizeflag, orig_sizeflag;
13053   const char *p;
13054   struct dis_private priv;
13055   int prefix_length;
13056
13057   priv.orig_sizeflag = AFLAG | DFLAG;
13058   if ((info->mach & bfd_mach_i386_i386) != 0)
13059     address_mode = mode_32bit;
13060   else if (info->mach == bfd_mach_i386_i8086)
13061     {
13062       address_mode = mode_16bit;
13063       priv.orig_sizeflag = 0;
13064     }
13065   else
13066     address_mode = mode_64bit;
13067
13068   if (intel_syntax == (char) -1)
13069     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
13070
13071   for (p = info->disassembler_options; p != NULL; )
13072     {
13073       if (CONST_STRNEQ (p, "amd64"))
13074         isa64 = amd64;
13075       else if (CONST_STRNEQ (p, "intel64"))
13076         isa64 = intel64;
13077       else if (CONST_STRNEQ (p, "x86-64"))
13078         {
13079           address_mode = mode_64bit;
13080           priv.orig_sizeflag = AFLAG | DFLAG;
13081         }
13082       else if (CONST_STRNEQ (p, "i386"))
13083         {
13084           address_mode = mode_32bit;
13085           priv.orig_sizeflag = AFLAG | DFLAG;
13086         }
13087       else if (CONST_STRNEQ (p, "i8086"))
13088         {
13089           address_mode = mode_16bit;
13090           priv.orig_sizeflag = 0;
13091         }
13092       else if (CONST_STRNEQ (p, "intel"))
13093         {
13094           intel_syntax = 1;
13095           if (CONST_STRNEQ (p + 5, "-mnemonic"))
13096             intel_mnemonic = 1;
13097         }
13098       else if (CONST_STRNEQ (p, "att"))
13099         {
13100           intel_syntax = 0;
13101           if (CONST_STRNEQ (p + 3, "-mnemonic"))
13102             intel_mnemonic = 0;
13103         }
13104       else if (CONST_STRNEQ (p, "addr"))
13105         {
13106           if (address_mode == mode_64bit)
13107             {
13108               if (p[4] == '3' && p[5] == '2')
13109                 priv.orig_sizeflag &= ~AFLAG;
13110               else if (p[4] == '6' && p[5] == '4')
13111                 priv.orig_sizeflag |= AFLAG;
13112             }
13113           else
13114             {
13115               if (p[4] == '1' && p[5] == '6')
13116                 priv.orig_sizeflag &= ~AFLAG;
13117               else if (p[4] == '3' && p[5] == '2')
13118                 priv.orig_sizeflag |= AFLAG;
13119             }
13120         }
13121       else if (CONST_STRNEQ (p, "data"))
13122         {
13123           if (p[4] == '1' && p[5] == '6')
13124             priv.orig_sizeflag &= ~DFLAG;
13125           else if (p[4] == '3' && p[5] == '2')
13126             priv.orig_sizeflag |= DFLAG;
13127         }
13128       else if (CONST_STRNEQ (p, "suffix"))
13129         priv.orig_sizeflag |= SUFFIX_ALWAYS;
13130
13131       p = strchr (p, ',');
13132       if (p != NULL)
13133         p++;
13134     }
13135
13136   if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
13137     {
13138       (*info->fprintf_func) (info->stream,
13139                              _("64-bit address is disabled"));
13140       return -1;
13141     }
13142
13143   if (intel_syntax)
13144     {
13145       names64 = intel_names64;
13146       names32 = intel_names32;
13147       names16 = intel_names16;
13148       names8 = intel_names8;
13149       names8rex = intel_names8rex;
13150       names_seg = intel_names_seg;
13151       names_mm = intel_names_mm;
13152       names_bnd = intel_names_bnd;
13153       names_xmm = intel_names_xmm;
13154       names_ymm = intel_names_ymm;
13155       names_zmm = intel_names_zmm;
13156       index64 = intel_index64;
13157       index32 = intel_index32;
13158       names_mask = intel_names_mask;
13159       index16 = intel_index16;
13160       open_char = '[';
13161       close_char = ']';
13162       separator_char = '+';
13163       scale_char = '*';
13164     }
13165   else
13166     {
13167       names64 = att_names64;
13168       names32 = att_names32;
13169       names16 = att_names16;
13170       names8 = att_names8;
13171       names8rex = att_names8rex;
13172       names_seg = att_names_seg;
13173       names_mm = att_names_mm;
13174       names_bnd = att_names_bnd;
13175       names_xmm = att_names_xmm;
13176       names_ymm = att_names_ymm;
13177       names_zmm = att_names_zmm;
13178       index64 = att_index64;
13179       index32 = att_index32;
13180       names_mask = att_names_mask;
13181       index16 = att_index16;
13182       open_char = '(';
13183       close_char =  ')';
13184       separator_char = ',';
13185       scale_char = ',';
13186     }
13187
13188   /* The output looks better if we put 7 bytes on a line, since that
13189      puts most long word instructions on a single line.  Use 8 bytes
13190      for Intel L1OM.  */
13191   if ((info->mach & bfd_mach_l1om) != 0)
13192     info->bytes_per_line = 8;
13193   else
13194     info->bytes_per_line = 7;
13195
13196   info->private_data = &priv;
13197   priv.max_fetched = priv.the_buffer;
13198   priv.insn_start = pc;
13199
13200   obuf[0] = 0;
13201   for (i = 0; i < MAX_OPERANDS; ++i)
13202     {
13203       op_out[i][0] = 0;
13204       op_index[i] = -1;
13205     }
13206
13207   the_info = info;
13208   start_pc = pc;
13209   start_codep = priv.the_buffer;
13210   codep = priv.the_buffer;
13211
13212   if (OPCODES_SIGSETJMP (priv.bailout) != 0)
13213     {
13214       const char *name;
13215
13216       /* Getting here means we tried for data but didn't get it.  That
13217          means we have an incomplete instruction of some sort.  Just
13218          print the first byte as a prefix or a .byte pseudo-op.  */
13219       if (codep > priv.the_buffer)
13220         {
13221           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
13222           if (name != NULL)
13223             (*info->fprintf_func) (info->stream, "%s", name);
13224           else
13225             {
13226               /* Just print the first byte as a .byte instruction.  */
13227               (*info->fprintf_func) (info->stream, ".byte 0x%x",
13228                                      (unsigned int) priv.the_buffer[0]);
13229             }
13230
13231           return 1;
13232         }
13233
13234       return -1;
13235     }
13236
13237   obufp = obuf;
13238   sizeflag = priv.orig_sizeflag;
13239
13240   if (!ckprefix () || rex_used)
13241     {
13242       /* Too many prefixes or unused REX prefixes.  */
13243       for (i = 0;
13244            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
13245            i++)
13246         (*info->fprintf_func) (info->stream, "%s%s",
13247                                i == 0 ? "" : " ",
13248                                prefix_name (all_prefixes[i], sizeflag));
13249       return i;
13250     }
13251
13252   insn_codep = codep;
13253
13254   FETCH_DATA (info, codep + 1);
13255   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
13256
13257   if (((prefixes & PREFIX_FWAIT)
13258        && ((*codep < 0xd8) || (*codep > 0xdf))))
13259     {
13260       /* Handle prefixes before fwait.  */
13261       for (i = 0; i < fwait_prefix && all_prefixes[i];
13262            i++)
13263         (*info->fprintf_func) (info->stream, "%s ",
13264                                prefix_name (all_prefixes[i], sizeflag));
13265       (*info->fprintf_func) (info->stream, "fwait");
13266       return i + 1;
13267     }
13268
13269   if (*codep == 0x0f)
13270     {
13271       unsigned char threebyte;
13272
13273       codep++;
13274       FETCH_DATA (info, codep + 1);
13275       threebyte = *codep;
13276       dp = &dis386_twobyte[threebyte];
13277       need_modrm = twobyte_has_modrm[*codep];
13278       codep++;
13279     }
13280   else
13281     {
13282       dp = &dis386[*codep];
13283       need_modrm = onebyte_has_modrm[*codep];
13284       codep++;
13285     }
13286
13287   /* Save sizeflag for printing the extra prefixes later before updating
13288      it for mnemonic and operand processing.  The prefix names depend
13289      only on the address mode.  */
13290   orig_sizeflag = sizeflag;
13291   if (prefixes & PREFIX_ADDR)
13292     sizeflag ^= AFLAG;
13293   if ((prefixes & PREFIX_DATA))
13294     sizeflag ^= DFLAG;
13295
13296   end_codep = codep;
13297   if (need_modrm)
13298     {
13299       FETCH_DATA (info, codep + 1);
13300       modrm.mod = (*codep >> 6) & 3;
13301       modrm.reg = (*codep >> 3) & 7;
13302       modrm.rm = *codep & 7;
13303     }
13304
13305   need_vex = 0;
13306   need_vex_reg = 0;
13307   vex_w_done = 0;
13308   vex.evex = 0;
13309
13310   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
13311     {
13312       get_sib (info, sizeflag);
13313       dofloat (sizeflag);
13314     }
13315   else
13316     {
13317       dp = get_valid_dis386 (dp, info);
13318       if (dp != NULL && putop (dp->name, sizeflag) == 0)
13319         {
13320           get_sib (info, sizeflag);
13321           for (i = 0; i < MAX_OPERANDS; ++i)
13322             {
13323               obufp = op_out[i];
13324               op_ad = MAX_OPERANDS - 1 - i;
13325               if (dp->op[i].rtn)
13326                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
13327               /* For EVEX instruction after the last operand masking
13328                  should be printed.  */
13329               if (i == 0 && vex.evex)
13330                 {
13331                   /* Don't print {%k0}.  */
13332                   if (vex.mask_register_specifier)
13333                     {
13334                       oappend ("{");
13335                       oappend (names_mask[vex.mask_register_specifier]);
13336                       oappend ("}");
13337                     }
13338                   if (vex.zeroing)
13339                     oappend ("{z}");
13340                 }
13341             }
13342         }
13343     }
13344
13345   /* Check if the REX prefix is used.  */
13346   if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)
13347     all_prefixes[last_rex_prefix] = 0;
13348
13349   /* Check if the SEG prefix is used.  */
13350   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
13351                    | PREFIX_FS | PREFIX_GS)) != 0
13352       && (used_prefixes & active_seg_prefix) != 0)
13353     all_prefixes[last_seg_prefix] = 0;
13354
13355   /* Check if the ADDR prefix is used.  */
13356   if ((prefixes & PREFIX_ADDR) != 0
13357       && (used_prefixes & PREFIX_ADDR) != 0)
13358     all_prefixes[last_addr_prefix] = 0;
13359
13360   /* Check if the DATA prefix is used.  */
13361   if ((prefixes & PREFIX_DATA) != 0
13362       && (used_prefixes & PREFIX_DATA) != 0)
13363     all_prefixes[last_data_prefix] = 0;
13364
13365   /* Print the extra prefixes.  */
13366   prefix_length = 0;
13367   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
13368     if (all_prefixes[i])
13369       {
13370         const char *name;
13371         name = prefix_name (all_prefixes[i], orig_sizeflag);
13372         if (name == NULL)
13373           abort ();
13374         prefix_length += strlen (name) + 1;
13375         (*info->fprintf_func) (info->stream, "%s ", name);
13376       }
13377
13378   /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
13379      unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
13380      used by putop and MMX/SSE operand and may be overriden by the
13381      PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
13382      separately.  */
13383   if (dp->prefix_requirement == PREFIX_OPCODE
13384       && dp != &bad_opcode
13385       && (((prefixes
13386             & (PREFIX_REPZ | PREFIX_REPNZ)) != 0
13387            && (used_prefixes
13388                & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
13389           || ((((prefixes
13390                  & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
13391                 == PREFIX_DATA)
13392                && (used_prefixes & PREFIX_DATA) == 0))))
13393     {
13394       (*info->fprintf_func) (info->stream, "(bad)");
13395       return end_codep - priv.the_buffer;
13396     }
13397
13398   /* Check maximum code length.  */
13399   if ((codep - start_codep) > MAX_CODE_LENGTH)
13400     {
13401       (*info->fprintf_func) (info->stream, "(bad)");
13402       return MAX_CODE_LENGTH;
13403     }
13404
13405   obufp = mnemonicendp;
13406   for (i = strlen (obuf) + prefix_length; i < 6; i++)
13407     oappend (" ");
13408   oappend (" ");
13409   (*info->fprintf_func) (info->stream, "%s", obuf);
13410
13411   /* The enter and bound instructions are printed with operands in the same
13412      order as the intel book; everything else is printed in reverse order.  */
13413   if (intel_syntax || two_source_ops)
13414     {
13415       bfd_vma riprel;
13416
13417       for (i = 0; i < MAX_OPERANDS; ++i)
13418         op_txt[i] = op_out[i];
13419
13420       if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
13421           && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
13422         {
13423           op_txt[2] = op_out[3];
13424           op_txt[3] = op_out[2];
13425         }
13426
13427       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
13428         {
13429           op_ad = op_index[i];
13430           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
13431           op_index[MAX_OPERANDS - 1 - i] = op_ad;
13432           riprel = op_riprel[i];
13433           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
13434           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
13435         }
13436     }
13437   else
13438     {
13439       for (i = 0; i < MAX_OPERANDS; ++i)
13440         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
13441     }
13442
13443   needcomma = 0;
13444   for (i = 0; i < MAX_OPERANDS; ++i)
13445     if (*op_txt[i])
13446       {
13447         if (needcomma)
13448           (*info->fprintf_func) (info->stream, ",");
13449         if (op_index[i] != -1 && !op_riprel[i])
13450           (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
13451         else
13452           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
13453         needcomma = 1;
13454       }
13455
13456   for (i = 0; i < MAX_OPERANDS; i++)
13457     if (op_index[i] != -1 && op_riprel[i])
13458       {
13459         (*info->fprintf_func) (info->stream, "        # ");
13460         (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
13461                                                 + op_address[op_index[i]]), info);
13462         break;
13463       }
13464   return codep - priv.the_buffer;
13465 }
13466
13467 static const char *float_mem[] = {
13468   /* d8 */
13469   "fadd{s|}",
13470   "fmul{s|}",
13471   "fcom{s|}",
13472   "fcomp{s|}",
13473   "fsub{s|}",
13474   "fsubr{s|}",
13475   "fdiv{s|}",
13476   "fdivr{s|}",
13477   /* d9 */
13478   "fld{s|}",
13479   "(bad)",
13480   "fst{s|}",
13481   "fstp{s|}",
13482   "fldenvIC",
13483   "fldcw",
13484   "fNstenvIC",
13485   "fNstcw",
13486   /* da */
13487   "fiadd{l|}",
13488   "fimul{l|}",
13489   "ficom{l|}",
13490   "ficomp{l|}",
13491   "fisub{l|}",
13492   "fisubr{l|}",
13493   "fidiv{l|}",
13494   "fidivr{l|}",
13495   /* db */
13496   "fild{l|}",
13497   "fisttp{l|}",
13498   "fist{l|}",
13499   "fistp{l|}",
13500   "(bad)",
13501   "fld{t||t|}",
13502   "(bad)",
13503   "fstp{t||t|}",
13504   /* dc */
13505   "fadd{l|}",
13506   "fmul{l|}",
13507   "fcom{l|}",
13508   "fcomp{l|}",
13509   "fsub{l|}",
13510   "fsubr{l|}",
13511   "fdiv{l|}",
13512   "fdivr{l|}",
13513   /* dd */
13514   "fld{l|}",
13515   "fisttp{ll|}",
13516   "fst{l||}",
13517   "fstp{l|}",
13518   "frstorIC",
13519   "(bad)",
13520   "fNsaveIC",
13521   "fNstsw",
13522   /* de */
13523   "fiadd",
13524   "fimul",
13525   "ficom",
13526   "ficomp",
13527   "fisub",
13528   "fisubr",
13529   "fidiv",
13530   "fidivr",
13531   /* df */
13532   "fild",
13533   "fisttp",
13534   "fist",
13535   "fistp",
13536   "fbld",
13537   "fild{ll|}",
13538   "fbstp",
13539   "fistp{ll|}",
13540 };
13541
13542 static const unsigned char float_mem_mode[] = {
13543   /* d8 */
13544   d_mode,
13545   d_mode,
13546   d_mode,
13547   d_mode,
13548   d_mode,
13549   d_mode,
13550   d_mode,
13551   d_mode,
13552   /* d9 */
13553   d_mode,
13554   0,
13555   d_mode,
13556   d_mode,
13557   0,
13558   w_mode,
13559   0,
13560   w_mode,
13561   /* da */
13562   d_mode,
13563   d_mode,
13564   d_mode,
13565   d_mode,
13566   d_mode,
13567   d_mode,
13568   d_mode,
13569   d_mode,
13570   /* db */
13571   d_mode,
13572   d_mode,
13573   d_mode,
13574   d_mode,
13575   0,
13576   t_mode,
13577   0,
13578   t_mode,
13579   /* dc */
13580   q_mode,
13581   q_mode,
13582   q_mode,
13583   q_mode,
13584   q_mode,
13585   q_mode,
13586   q_mode,
13587   q_mode,
13588   /* dd */
13589   q_mode,
13590   q_mode,
13591   q_mode,
13592   q_mode,
13593   0,
13594   0,
13595   0,
13596   w_mode,
13597   /* de */
13598   w_mode,
13599   w_mode,
13600   w_mode,
13601   w_mode,
13602   w_mode,
13603   w_mode,
13604   w_mode,
13605   w_mode,
13606   /* df */
13607   w_mode,
13608   w_mode,
13609   w_mode,
13610   w_mode,
13611   t_mode,
13612   q_mode,
13613   t_mode,
13614   q_mode
13615 };
13616
13617 #define ST { OP_ST, 0 }
13618 #define STi { OP_STi, 0 }
13619
13620 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
13621 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
13622 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
13623 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
13624 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
13625 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
13626 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
13627 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
13628 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
13629
13630 static const struct dis386 float_reg[][8] = {
13631   /* d8 */
13632   {
13633     { "fadd",   { ST, STi }, 0 },
13634     { "fmul",   { ST, STi }, 0 },
13635     { "fcom",   { STi }, 0 },
13636     { "fcomp",  { STi }, 0 },
13637     { "fsub",   { ST, STi }, 0 },
13638     { "fsubr",  { ST, STi }, 0 },
13639     { "fdiv",   { ST, STi }, 0 },
13640     { "fdivr",  { ST, STi }, 0 },
13641   },
13642   /* d9 */
13643   {
13644     { "fld",    { STi }, 0 },
13645     { "fxch",   { STi }, 0 },
13646     { FGRPd9_2 },
13647     { Bad_Opcode },
13648     { FGRPd9_4 },
13649     { FGRPd9_5 },
13650     { FGRPd9_6 },
13651     { FGRPd9_7 },
13652   },
13653   /* da */
13654   {
13655     { "fcmovb", { ST, STi }, 0 },
13656     { "fcmove", { ST, STi }, 0 },
13657     { "fcmovbe",{ ST, STi }, 0 },
13658     { "fcmovu", { ST, STi }, 0 },
13659     { Bad_Opcode },
13660     { FGRPda_5 },
13661     { Bad_Opcode },
13662     { Bad_Opcode },
13663   },
13664   /* db */
13665   {
13666     { "fcmovnb",{ ST, STi }, 0 },
13667     { "fcmovne",{ ST, STi }, 0 },
13668     { "fcmovnbe",{ ST, STi }, 0 },
13669     { "fcmovnu",{ ST, STi }, 0 },
13670     { FGRPdb_4 },
13671     { "fucomi", { ST, STi }, 0 },
13672     { "fcomi",  { ST, STi }, 0 },
13673     { Bad_Opcode },
13674   },
13675   /* dc */
13676   {
13677     { "fadd",   { STi, ST }, 0 },
13678     { "fmul",   { STi, ST }, 0 },
13679     { Bad_Opcode },
13680     { Bad_Opcode },
13681     { "fsub!M", { STi, ST }, 0 },
13682     { "fsubM",  { STi, ST }, 0 },
13683     { "fdiv!M", { STi, ST }, 0 },
13684     { "fdivM",  { STi, ST }, 0 },
13685   },
13686   /* dd */
13687   {
13688     { "ffree",  { STi }, 0 },
13689     { Bad_Opcode },
13690     { "fst",    { STi }, 0 },
13691     { "fstp",   { STi }, 0 },
13692     { "fucom",  { STi }, 0 },
13693     { "fucomp", { STi }, 0 },
13694     { Bad_Opcode },
13695     { Bad_Opcode },
13696   },
13697   /* de */
13698   {
13699     { "faddp",  { STi, ST }, 0 },
13700     { "fmulp",  { STi, ST }, 0 },
13701     { Bad_Opcode },
13702     { FGRPde_3 },
13703     { "fsub!Mp", { STi, ST }, 0 },
13704     { "fsubMp", { STi, ST }, 0 },
13705     { "fdiv!Mp", { STi, ST }, 0 },
13706     { "fdivMp", { STi, ST }, 0 },
13707   },
13708   /* df */
13709   {
13710     { "ffreep", { STi }, 0 },
13711     { Bad_Opcode },
13712     { Bad_Opcode },
13713     { Bad_Opcode },
13714     { FGRPdf_4 },
13715     { "fucomip", { ST, STi }, 0 },
13716     { "fcomip", { ST, STi }, 0 },
13717     { Bad_Opcode },
13718   },
13719 };
13720
13721 static char *fgrps[][8] = {
13722   /* Bad opcode 0 */
13723   {
13724     "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13725   },
13726
13727   /* d9_2  1 */
13728   {
13729     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13730   },
13731
13732   /* d9_4  2 */
13733   {
13734     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
13735   },
13736
13737   /* d9_5  3 */
13738   {
13739     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
13740   },
13741
13742   /* d9_6  4 */
13743   {
13744     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
13745   },
13746
13747   /* d9_7  5 */
13748   {
13749     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
13750   },
13751
13752   /* da_5  6 */
13753   {
13754     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13755   },
13756
13757   /* db_4  7 */
13758   {
13759     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
13760     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
13761   },
13762
13763   /* de_3  8 */
13764   {
13765     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13766   },
13767
13768   /* df_4  9 */
13769   {
13770     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13771   },
13772 };
13773
13774 static void
13775 swap_operand (void)
13776 {
13777   mnemonicendp[0] = '.';
13778   mnemonicendp[1] = 's';
13779   mnemonicendp += 2;
13780 }
13781
13782 static void
13783 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
13784                int sizeflag ATTRIBUTE_UNUSED)
13785 {
13786   /* Skip mod/rm byte.  */
13787   MODRM_CHECK;
13788   codep++;
13789 }
13790
13791 static void
13792 dofloat (int sizeflag)
13793 {
13794   const struct dis386 *dp;
13795   unsigned char floatop;
13796
13797   floatop = codep[-1];
13798
13799   if (modrm.mod != 3)
13800     {
13801       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
13802
13803       putop (float_mem[fp_indx], sizeflag);
13804       obufp = op_out[0];
13805       op_ad = 2;
13806       OP_E (float_mem_mode[fp_indx], sizeflag);
13807       return;
13808     }
13809   /* Skip mod/rm byte.  */
13810   MODRM_CHECK;
13811   codep++;
13812
13813   dp = &float_reg[floatop - 0xd8][modrm.reg];
13814   if (dp->name == NULL)
13815     {
13816       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
13817
13818       /* Instruction fnstsw is only one with strange arg.  */
13819       if (floatop == 0xdf && codep[-1] == 0xe0)
13820         strcpy (op_out[0], names16[0]);
13821     }
13822   else
13823     {
13824       putop (dp->name, sizeflag);
13825
13826       obufp = op_out[0];
13827       op_ad = 2;
13828       if (dp->op[0].rtn)
13829         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
13830
13831       obufp = op_out[1];
13832       op_ad = 1;
13833       if (dp->op[1].rtn)
13834         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
13835     }
13836 }
13837
13838 /* Like oappend (below), but S is a string starting with '%'.
13839    In Intel syntax, the '%' is elided.  */
13840 static void
13841 oappend_maybe_intel (const char *s)
13842 {
13843   oappend (s + intel_syntax);
13844 }
13845
13846 static void
13847 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13848 {
13849   oappend_maybe_intel ("%st");
13850 }
13851
13852 static void
13853 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13854 {
13855   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
13856   oappend_maybe_intel (scratchbuf);
13857 }
13858
13859 /* Capital letters in template are macros.  */
13860 static int
13861 putop (const char *in_template, int sizeflag)
13862 {
13863   const char *p;
13864   int alt = 0;
13865   int cond = 1;
13866   unsigned int l = 0, len = 1;
13867   char last[4];
13868
13869 #define SAVE_LAST(c)                    \
13870   if (l < len && l < sizeof (last))     \
13871     last[l++] = c;                      \
13872   else                                  \
13873     abort ();
13874
13875   for (p = in_template; *p; p++)
13876     {
13877       switch (*p)
13878         {
13879         default:
13880           *obufp++ = *p;
13881           break;
13882         case '%':
13883           len++;
13884           break;
13885         case '!':
13886           cond = 0;
13887           break;
13888         case '{':
13889           if (intel_syntax)
13890             {
13891               while (*++p != '|')
13892                 if (*p == '}' || *p == '\0')
13893                   abort ();
13894             }
13895           /* Fall through.  */
13896         case 'I':
13897           alt = 1;
13898           continue;
13899         case '|':
13900           while (*++p != '}')
13901             {
13902               if (*p == '\0')
13903                 abort ();
13904             }
13905           break;
13906         case '}':
13907           break;
13908         case 'A':
13909           if (intel_syntax)
13910             break;
13911           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13912             *obufp++ = 'b';
13913           break;
13914         case 'B':
13915           if (l == 0 && len == 1)
13916             {
13917 case_B:
13918               if (intel_syntax)
13919                 break;
13920               if (sizeflag & SUFFIX_ALWAYS)
13921                 *obufp++ = 'b';
13922             }
13923           else
13924             {
13925               if (l != 1
13926                   || len != 2
13927                   || last[0] != 'L')
13928                 {
13929                   SAVE_LAST (*p);
13930                   break;
13931                 }
13932
13933               if (address_mode == mode_64bit
13934                   && !(prefixes & PREFIX_ADDR))
13935                 {
13936                   *obufp++ = 'a';
13937                   *obufp++ = 'b';
13938                   *obufp++ = 's';
13939                 }
13940
13941               goto case_B;
13942             }
13943           break;
13944         case 'C':
13945           if (intel_syntax && !alt)
13946             break;
13947           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
13948             {
13949               if (sizeflag & DFLAG)
13950                 *obufp++ = intel_syntax ? 'd' : 'l';
13951               else
13952                 *obufp++ = intel_syntax ? 'w' : 's';
13953               used_prefixes |= (prefixes & PREFIX_DATA);
13954             }
13955           break;
13956         case 'D':
13957           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
13958             break;
13959           USED_REX (REX_W);
13960           if (modrm.mod == 3)
13961             {
13962               if (rex & REX_W)
13963                 *obufp++ = 'q';
13964               else
13965                 {
13966                   if (sizeflag & DFLAG)
13967                     *obufp++ = intel_syntax ? 'd' : 'l';
13968                   else
13969                     *obufp++ = 'w';
13970                   used_prefixes |= (prefixes & PREFIX_DATA);
13971                 }
13972             }
13973           else
13974             *obufp++ = 'w';
13975           break;
13976         case 'E':               /* For jcxz/jecxz */
13977           if (address_mode == mode_64bit)
13978             {
13979               if (sizeflag & AFLAG)
13980                 *obufp++ = 'r';
13981               else
13982                 *obufp++ = 'e';
13983             }
13984           else
13985             if (sizeflag & AFLAG)
13986               *obufp++ = 'e';
13987           used_prefixes |= (prefixes & PREFIX_ADDR);
13988           break;
13989         case 'F':
13990           if (intel_syntax)
13991             break;
13992           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
13993             {
13994               if (sizeflag & AFLAG)
13995                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
13996               else
13997                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
13998               used_prefixes |= (prefixes & PREFIX_ADDR);
13999             }
14000           break;
14001         case 'G':
14002           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
14003             break;
14004           if ((rex & REX_W) || (sizeflag & DFLAG))
14005             *obufp++ = 'l';
14006           else
14007             *obufp++ = 'w';
14008           if (!(rex & REX_W))
14009             used_prefixes |= (prefixes & PREFIX_DATA);
14010           break;
14011         case 'H':
14012           if (intel_syntax)
14013             break;
14014           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
14015               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
14016             {
14017               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
14018               *obufp++ = ',';
14019               *obufp++ = 'p';
14020               if (prefixes & PREFIX_DS)
14021                 *obufp++ = 't';
14022               else
14023                 *obufp++ = 'n';
14024             }
14025           break;
14026         case 'J':
14027           if (intel_syntax)
14028             break;
14029           *obufp++ = 'l';
14030           break;
14031         case 'K':
14032           USED_REX (REX_W);
14033           if (rex & REX_W)
14034             *obufp++ = 'q';
14035           else
14036             *obufp++ = 'd';
14037           break;
14038         case 'Z':
14039           if (l != 0 || len != 1)
14040             {
14041               if (l != 1 || len != 2 || last[0] != 'X')
14042                 {
14043                   SAVE_LAST (*p);
14044                   break;
14045                 }
14046               if (!need_vex || !vex.evex)
14047                 abort ();
14048               if (intel_syntax
14049                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
14050                 break;
14051               switch (vex.length)
14052                 {
14053                 case 128:
14054                   *obufp++ = 'x';
14055                   break;
14056                 case 256:
14057                   *obufp++ = 'y';
14058                   break;
14059                 case 512:
14060                   *obufp++ = 'z';
14061                   break;
14062                 default:
14063                   abort ();
14064                 }
14065               break;
14066             }
14067           if (intel_syntax)
14068             break;
14069           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
14070             {
14071               *obufp++ = 'q';
14072               break;
14073             }
14074           /* Fall through.  */
14075           goto case_L;
14076         case 'L':
14077           if (l != 0 || len != 1)
14078             {
14079               SAVE_LAST (*p);
14080               break;
14081             }
14082 case_L:
14083           if (intel_syntax)
14084             break;
14085           if (sizeflag & SUFFIX_ALWAYS)
14086             *obufp++ = 'l';
14087           break;
14088         case 'M':
14089           if (intel_mnemonic != cond)
14090             *obufp++ = 'r';
14091           break;
14092         case 'N':
14093           if ((prefixes & PREFIX_FWAIT) == 0)
14094             *obufp++ = 'n';
14095           else
14096             used_prefixes |= PREFIX_FWAIT;
14097           break;
14098         case 'O':
14099           USED_REX (REX_W);
14100           if (rex & REX_W)
14101             *obufp++ = 'o';
14102           else if (intel_syntax && (sizeflag & DFLAG))
14103             *obufp++ = 'q';
14104           else
14105             *obufp++ = 'd';
14106           if (!(rex & REX_W))
14107             used_prefixes |= (prefixes & PREFIX_DATA);
14108           break;
14109         case '&':
14110           if (!intel_syntax
14111               && address_mode == mode_64bit
14112               && isa64 == intel64)
14113             {
14114               *obufp++ = 'q';
14115               break;
14116             }
14117           /* Fall through.  */
14118         case 'T':
14119           if (!intel_syntax
14120               && address_mode == mode_64bit
14121               && ((sizeflag & DFLAG) || (rex & REX_W)))
14122             {
14123               *obufp++ = 'q';
14124               break;
14125             }
14126           /* Fall through.  */
14127           goto case_P;
14128         case 'P':
14129           if (l == 0 && len == 1)
14130             {
14131 case_P:
14132               if (intel_syntax)
14133                 {
14134                   if ((rex & REX_W) == 0
14135                       && (prefixes & PREFIX_DATA))
14136                     {
14137                       if ((sizeflag & DFLAG) == 0)
14138                         *obufp++ = 'w';
14139                       used_prefixes |= (prefixes & PREFIX_DATA);
14140                     }
14141                   break;
14142                 }
14143               if ((prefixes & PREFIX_DATA)
14144                   || (rex & REX_W)
14145                   || (sizeflag & SUFFIX_ALWAYS))
14146                 {
14147                   USED_REX (REX_W);
14148                   if (rex & REX_W)
14149                     *obufp++ = 'q';
14150                   else
14151                     {
14152                       if (sizeflag & DFLAG)
14153                         *obufp++ = 'l';
14154                       else
14155                         *obufp++ = 'w';
14156                       used_prefixes |= (prefixes & PREFIX_DATA);
14157                     }
14158                 }
14159             }
14160           else
14161             {
14162               if (l != 1 || len != 2 || last[0] != 'L')
14163                 {
14164                   SAVE_LAST (*p);
14165                   break;
14166                 }
14167
14168               if ((prefixes & PREFIX_DATA)
14169                   || (rex & REX_W)
14170                   || (sizeflag & SUFFIX_ALWAYS))
14171                 {
14172                   USED_REX (REX_W);
14173                   if (rex & REX_W)
14174                     *obufp++ = 'q';
14175                   else
14176                     {
14177                       if (sizeflag & DFLAG)
14178                         *obufp++ = intel_syntax ? 'd' : 'l';
14179                       else
14180                         *obufp++ = 'w';
14181                       used_prefixes |= (prefixes & PREFIX_DATA);
14182                     }
14183                 }
14184             }
14185           break;
14186         case 'U':
14187           if (intel_syntax)
14188             break;
14189           if (address_mode == mode_64bit
14190               && ((sizeflag & DFLAG) || (rex & REX_W)))
14191             {
14192               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
14193                 *obufp++ = 'q';
14194               break;
14195             }
14196           /* Fall through.  */
14197           goto case_Q;
14198         case 'Q':
14199           if (l == 0 && len == 1)
14200             {
14201 case_Q:
14202               if (intel_syntax && !alt)
14203                 break;
14204               USED_REX (REX_W);
14205               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
14206                 {
14207                   if (rex & REX_W)
14208                     *obufp++ = 'q';
14209                   else
14210                     {
14211                       if (sizeflag & DFLAG)
14212                         *obufp++ = intel_syntax ? 'd' : 'l';
14213                       else
14214                         *obufp++ = 'w';
14215                       used_prefixes |= (prefixes & PREFIX_DATA);
14216                     }
14217                 }
14218             }
14219           else
14220             {
14221               if (l != 1 || len != 2 || last[0] != 'L')
14222                 {
14223                   SAVE_LAST (*p);
14224                   break;
14225                 }
14226               if (intel_syntax
14227                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
14228                 break;
14229               if ((rex & REX_W))
14230                 {
14231                   USED_REX (REX_W);
14232                   *obufp++ = 'q';
14233                 }
14234               else
14235                 *obufp++ = 'l';
14236             }
14237           break;
14238         case 'R':
14239           USED_REX (REX_W);
14240           if (rex & REX_W)
14241             *obufp++ = 'q';
14242           else if (sizeflag & DFLAG)
14243             {
14244               if (intel_syntax)
14245                   *obufp++ = 'd';
14246               else
14247                   *obufp++ = 'l';
14248             }
14249           else
14250             *obufp++ = 'w';
14251           if (intel_syntax && !p[1]
14252               && ((rex & REX_W) || (sizeflag & DFLAG)))
14253             *obufp++ = 'e';
14254           if (!(rex & REX_W))
14255             used_prefixes |= (prefixes & PREFIX_DATA);
14256           break;
14257         case 'V':
14258           if (l == 0 && len == 1)
14259             {
14260               if (intel_syntax)
14261                 break;
14262               if (address_mode == mode_64bit
14263                   && ((sizeflag & DFLAG) || (rex & REX_W)))
14264                 {
14265                   if (sizeflag & SUFFIX_ALWAYS)
14266                     *obufp++ = 'q';
14267                   break;
14268                 }
14269             }
14270           else
14271             {
14272               if (l != 1
14273                   || len != 2
14274                   || last[0] != 'L')
14275                 {
14276                   SAVE_LAST (*p);
14277                   break;
14278                 }
14279
14280               if (rex & REX_W)
14281                 {
14282                   *obufp++ = 'a';
14283                   *obufp++ = 'b';
14284                   *obufp++ = 's';
14285                 }
14286             }
14287           /* Fall through.  */
14288           goto case_S;
14289         case 'S':
14290           if (l == 0 && len == 1)
14291             {
14292 case_S:
14293               if (intel_syntax)
14294                 break;
14295               if (sizeflag & SUFFIX_ALWAYS)
14296                 {
14297                   if (rex & REX_W)
14298                     *obufp++ = 'q';
14299                   else
14300                     {
14301                       if (sizeflag & DFLAG)
14302                         *obufp++ = 'l';
14303                       else
14304                         *obufp++ = 'w';
14305                       used_prefixes |= (prefixes & PREFIX_DATA);
14306                     }
14307                 }
14308             }
14309           else
14310             {
14311               if (l != 1
14312                   || len != 2
14313                   || last[0] != 'L')
14314                 {
14315                   SAVE_LAST (*p);
14316                   break;
14317                 }
14318
14319               if (address_mode == mode_64bit
14320                   && !(prefixes & PREFIX_ADDR))
14321                 {
14322                   *obufp++ = 'a';
14323                   *obufp++ = 'b';
14324                   *obufp++ = 's';
14325                 }
14326
14327               goto case_S;
14328             }
14329           break;
14330         case 'X':
14331           if (l != 0 || len != 1)
14332             {
14333               SAVE_LAST (*p);
14334               break;
14335             }
14336           if (need_vex && vex.prefix)
14337             {
14338               if (vex.prefix == DATA_PREFIX_OPCODE)
14339                 *obufp++ = 'd';
14340               else
14341                 *obufp++ = 's';
14342             }
14343           else
14344             {
14345               if (prefixes & PREFIX_DATA)
14346                 *obufp++ = 'd';
14347               else
14348                 *obufp++ = 's';
14349               used_prefixes |= (prefixes & PREFIX_DATA);
14350             }
14351           break;
14352         case 'Y':
14353           if (l == 0 && len == 1)
14354             {
14355               if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
14356                 break;
14357               if (rex & REX_W)
14358                 {
14359                   USED_REX (REX_W);
14360                   *obufp++ = 'q';
14361                 }
14362               break;
14363             }
14364           else
14365             {
14366               if (l != 1 || len != 2 || last[0] != 'X')
14367                 {
14368                   SAVE_LAST (*p);
14369                   break;
14370                 }
14371               if (!need_vex)
14372                 abort ();
14373               if (intel_syntax
14374                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
14375                 break;
14376               switch (vex.length)
14377                 {
14378                 case 128:
14379                   *obufp++ = 'x';
14380                   break;
14381                 case 256:
14382                   *obufp++ = 'y';
14383                   break;
14384                 case 512:
14385                   if (!vex.evex)
14386                 default:
14387                     abort ();
14388                 }
14389             }
14390           break;
14391         case 'W':
14392           if (l == 0 && len == 1)
14393             {
14394               /* operand size flag for cwtl, cbtw */
14395               USED_REX (REX_W);
14396               if (rex & REX_W)
14397                 {
14398                   if (intel_syntax)
14399                     *obufp++ = 'd';
14400                   else
14401                     *obufp++ = 'l';
14402                 }
14403               else if (sizeflag & DFLAG)
14404                 *obufp++ = 'w';
14405               else
14406                 *obufp++ = 'b';
14407               if (!(rex & REX_W))
14408                 used_prefixes |= (prefixes & PREFIX_DATA);
14409             }
14410           else
14411             {
14412               if (l != 1
14413                   || len != 2
14414                   || (last[0] != 'X'
14415                       && last[0] != 'L'))
14416                 {
14417                   SAVE_LAST (*p);
14418                   break;
14419                 }
14420               if (!need_vex)
14421                 abort ();
14422               if (last[0] == 'X')
14423                 *obufp++ = vex.w ? 'd': 's';
14424               else
14425                 *obufp++ = vex.w ? 'q': 'd';
14426             }
14427           break;
14428         case '^':
14429           if (intel_syntax)
14430             break;
14431           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
14432             {
14433               if (sizeflag & DFLAG)
14434                 *obufp++ = 'l';
14435               else
14436                 *obufp++ = 'w';
14437               used_prefixes |= (prefixes & PREFIX_DATA);
14438             }
14439           break;
14440         case '@':
14441           if (intel_syntax)
14442             break;
14443           if (address_mode == mode_64bit
14444               && (isa64 == intel64
14445                   || ((sizeflag & DFLAG) || (rex & REX_W))))
14446               *obufp++ = 'q';
14447           else if ((prefixes & PREFIX_DATA))
14448             {
14449               if (!(sizeflag & DFLAG))
14450                 *obufp++ = 'w';
14451               used_prefixes |= (prefixes & PREFIX_DATA);
14452             }
14453           break;
14454         }
14455       alt = 0;
14456     }
14457   *obufp = 0;
14458   mnemonicendp = obufp;
14459   return 0;
14460 }
14461
14462 static void
14463 oappend (const char *s)
14464 {
14465   obufp = stpcpy (obufp, s);
14466 }
14467
14468 static void
14469 append_seg (void)
14470 {
14471   /* Only print the active segment register.  */
14472   if (!active_seg_prefix)
14473     return;
14474
14475   used_prefixes |= active_seg_prefix;
14476   switch (active_seg_prefix)
14477     {
14478     case PREFIX_CS:
14479       oappend_maybe_intel ("%cs:");
14480       break;
14481     case PREFIX_DS:
14482       oappend_maybe_intel ("%ds:");
14483       break;
14484     case PREFIX_SS:
14485       oappend_maybe_intel ("%ss:");
14486       break;
14487     case PREFIX_ES:
14488       oappend_maybe_intel ("%es:");
14489       break;
14490     case PREFIX_FS:
14491       oappend_maybe_intel ("%fs:");
14492       break;
14493     case PREFIX_GS:
14494       oappend_maybe_intel ("%gs:");
14495       break;
14496     default:
14497       break;
14498     }
14499 }
14500
14501 static void
14502 OP_indirE (int bytemode, int sizeflag)
14503 {
14504   if (!intel_syntax)
14505     oappend ("*");
14506   OP_E (bytemode, sizeflag);
14507 }
14508
14509 static void
14510 print_operand_value (char *buf, int hex, bfd_vma disp)
14511 {
14512   if (address_mode == mode_64bit)
14513     {
14514       if (hex)
14515         {
14516           char tmp[30];
14517           int i;
14518           buf[0] = '0';
14519           buf[1] = 'x';
14520           sprintf_vma (tmp, disp);
14521           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
14522           strcpy (buf + 2, tmp + i);
14523         }
14524       else
14525         {
14526           bfd_signed_vma v = disp;
14527           char tmp[30];
14528           int i;
14529           if (v < 0)
14530             {
14531               *(buf++) = '-';
14532               v = -disp;
14533               /* Check for possible overflow on 0x8000000000000000.  */
14534               if (v < 0)
14535                 {
14536                   strcpy (buf, "9223372036854775808");
14537                   return;
14538                 }
14539             }
14540           if (!v)
14541             {
14542               strcpy (buf, "0");
14543               return;
14544             }
14545
14546           i = 0;
14547           tmp[29] = 0;
14548           while (v)
14549             {
14550               tmp[28 - i] = (v % 10) + '0';
14551               v /= 10;
14552               i++;
14553             }
14554           strcpy (buf, tmp + 29 - i);
14555         }
14556     }
14557   else
14558     {
14559       if (hex)
14560         sprintf (buf, "0x%x", (unsigned int) disp);
14561       else
14562         sprintf (buf, "%d", (int) disp);
14563     }
14564 }
14565
14566 /* Put DISP in BUF as signed hex number.  */
14567
14568 static void
14569 print_displacement (char *buf, bfd_vma disp)
14570 {
14571   bfd_signed_vma val = disp;
14572   char tmp[30];
14573   int i, j = 0;
14574
14575   if (val < 0)
14576     {
14577       buf[j++] = '-';
14578       val = -disp;
14579
14580       /* Check for possible overflow.  */
14581       if (val < 0)
14582         {
14583           switch (address_mode)
14584             {
14585             case mode_64bit:
14586               strcpy (buf + j, "0x8000000000000000");
14587               break;
14588             case mode_32bit:
14589               strcpy (buf + j, "0x80000000");
14590               break;
14591             case mode_16bit:
14592               strcpy (buf + j, "0x8000");
14593               break;
14594             }
14595           return;
14596         }
14597     }
14598
14599   buf[j++] = '0';
14600   buf[j++] = 'x';
14601
14602   sprintf_vma (tmp, (bfd_vma) val);
14603   for (i = 0; tmp[i] == '0'; i++)
14604     continue;
14605   if (tmp[i] == '\0')
14606     i--;
14607   strcpy (buf + j, tmp + i);
14608 }
14609
14610 static void
14611 intel_operand_size (int bytemode, int sizeflag)
14612 {
14613   if (vex.evex
14614       && vex.b
14615       && (bytemode == x_mode
14616           || bytemode == evex_half_bcst_xmmq_mode))
14617     {
14618       if (vex.w)
14619         oappend ("QWORD PTR ");
14620       else
14621         oappend ("DWORD PTR ");
14622       return;
14623     }
14624   switch (bytemode)
14625     {
14626     case b_mode:
14627     case b_swap_mode:
14628     case dqb_mode:
14629     case db_mode:
14630       oappend ("BYTE PTR ");
14631       break;
14632     case w_mode:
14633     case dw_mode:
14634     case dqw_mode:
14635       oappend ("WORD PTR ");
14636       break;
14637     case indir_v_mode:
14638       if (address_mode == mode_64bit && isa64 == intel64)
14639         {
14640           oappend ("QWORD PTR ");
14641           break;
14642         }
14643       /* Fall through.  */
14644     case stack_v_mode:
14645       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14646         {
14647           oappend ("QWORD PTR ");
14648           break;
14649         }
14650       /* Fall through.  */
14651     case v_mode:
14652     case v_swap_mode:
14653     case dq_mode:
14654       USED_REX (REX_W);
14655       if (rex & REX_W)
14656         oappend ("QWORD PTR ");
14657       else
14658         {
14659           if ((sizeflag & DFLAG) || bytemode == dq_mode)
14660             oappend ("DWORD PTR ");
14661           else
14662             oappend ("WORD PTR ");
14663           used_prefixes |= (prefixes & PREFIX_DATA);
14664         }
14665       break;
14666     case z_mode:
14667       if ((rex & REX_W) || (sizeflag & DFLAG))
14668         *obufp++ = 'D';
14669       oappend ("WORD PTR ");
14670       if (!(rex & REX_W))
14671         used_prefixes |= (prefixes & PREFIX_DATA);
14672       break;
14673     case a_mode:
14674       if (sizeflag & DFLAG)
14675         oappend ("QWORD PTR ");
14676       else
14677         oappend ("DWORD PTR ");
14678       used_prefixes |= (prefixes & PREFIX_DATA);
14679       break;
14680     case d_mode:
14681     case d_scalar_mode:
14682     case d_scalar_swap_mode:
14683     case d_swap_mode:
14684     case dqd_mode:
14685       oappend ("DWORD PTR ");
14686       break;
14687     case q_mode:
14688     case q_scalar_mode:
14689     case q_scalar_swap_mode:
14690     case q_swap_mode:
14691       oappend ("QWORD PTR ");
14692       break;
14693     case m_mode:
14694       if (address_mode == mode_64bit)
14695         oappend ("QWORD PTR ");
14696       else
14697         oappend ("DWORD PTR ");
14698       break;
14699     case f_mode:
14700       if (sizeflag & DFLAG)
14701         oappend ("FWORD PTR ");
14702       else
14703         oappend ("DWORD PTR ");
14704       used_prefixes |= (prefixes & PREFIX_DATA);
14705       break;
14706     case t_mode:
14707       oappend ("TBYTE PTR ");
14708       break;
14709     case x_mode:
14710     case x_swap_mode:
14711     case evex_x_gscat_mode:
14712     case evex_x_nobcst_mode:
14713       if (need_vex)
14714         {
14715           switch (vex.length)
14716             {
14717             case 128:
14718               oappend ("XMMWORD PTR ");
14719               break;
14720             case 256:
14721               oappend ("YMMWORD PTR ");
14722               break;
14723             case 512:
14724               oappend ("ZMMWORD PTR ");
14725               break;
14726             default:
14727               abort ();
14728             }
14729         }
14730       else
14731         oappend ("XMMWORD PTR ");
14732       break;
14733     case xmm_mode:
14734       oappend ("XMMWORD PTR ");
14735       break;
14736     case ymm_mode:
14737       oappend ("YMMWORD PTR ");
14738       break;
14739     case xmmq_mode:
14740     case evex_half_bcst_xmmq_mode:
14741       if (!need_vex)
14742         abort ();
14743
14744       switch (vex.length)
14745         {
14746         case 128:
14747           oappend ("QWORD PTR ");
14748           break;
14749         case 256:
14750           oappend ("XMMWORD PTR ");
14751           break;
14752         case 512:
14753           oappend ("YMMWORD PTR ");
14754           break;
14755         default:
14756           abort ();
14757         }
14758       break;
14759     case xmm_mb_mode:
14760       if (!need_vex)
14761         abort ();
14762
14763       switch (vex.length)
14764         {
14765         case 128:
14766         case 256:
14767         case 512:
14768           oappend ("BYTE PTR ");
14769           break;
14770         default:
14771           abort ();
14772         }
14773       break;
14774     case xmm_mw_mode:
14775       if (!need_vex)
14776         abort ();
14777
14778       switch (vex.length)
14779         {
14780         case 128:
14781         case 256:
14782         case 512:
14783           oappend ("WORD PTR ");
14784           break;
14785         default:
14786           abort ();
14787         }
14788       break;
14789     case xmm_md_mode:
14790       if (!need_vex)
14791         abort ();
14792
14793       switch (vex.length)
14794         {
14795         case 128:
14796         case 256:
14797         case 512:
14798           oappend ("DWORD PTR ");
14799           break;
14800         default:
14801           abort ();
14802         }
14803       break;
14804     case xmm_mq_mode:
14805       if (!need_vex)
14806         abort ();
14807
14808       switch (vex.length)
14809         {
14810         case 128:
14811         case 256:
14812         case 512:
14813           oappend ("QWORD PTR ");
14814           break;
14815         default:
14816           abort ();
14817         }
14818       break;
14819     case xmmdw_mode:
14820       if (!need_vex)
14821         abort ();
14822
14823       switch (vex.length)
14824         {
14825         case 128:
14826           oappend ("WORD PTR ");
14827           break;
14828         case 256:
14829           oappend ("DWORD PTR ");
14830           break;
14831         case 512:
14832           oappend ("QWORD PTR ");
14833           break;
14834         default:
14835           abort ();
14836         }
14837       break;
14838     case xmmqd_mode:
14839       if (!need_vex)
14840         abort ();
14841
14842       switch (vex.length)
14843         {
14844         case 128:
14845           oappend ("DWORD PTR ");
14846           break;
14847         case 256:
14848           oappend ("QWORD PTR ");
14849           break;
14850         case 512:
14851           oappend ("XMMWORD PTR ");
14852           break;
14853         default:
14854           abort ();
14855         }
14856       break;
14857     case ymmq_mode:
14858       if (!need_vex)
14859         abort ();
14860
14861       switch (vex.length)
14862         {
14863         case 128:
14864           oappend ("QWORD PTR ");
14865           break;
14866         case 256:
14867           oappend ("YMMWORD PTR ");
14868           break;
14869         case 512:
14870           oappend ("ZMMWORD PTR ");
14871           break;
14872         default:
14873           abort ();
14874         }
14875       break;
14876     case ymmxmm_mode:
14877       if (!need_vex)
14878         abort ();
14879
14880       switch (vex.length)
14881         {
14882         case 128:
14883         case 256:
14884           oappend ("XMMWORD PTR ");
14885           break;
14886         default:
14887           abort ();
14888         }
14889       break;
14890     case o_mode:
14891       oappend ("OWORD PTR ");
14892       break;
14893     case xmm_mdq_mode:
14894     case vex_w_dq_mode:
14895     case vex_scalar_w_dq_mode:
14896       if (!need_vex)
14897         abort ();
14898
14899       if (vex.w)
14900         oappend ("QWORD PTR ");
14901       else
14902         oappend ("DWORD PTR ");
14903       break;
14904     case vex_vsib_d_w_dq_mode:
14905     case vex_vsib_q_w_dq_mode:
14906       if (!need_vex)
14907         abort ();
14908
14909       if (!vex.evex)
14910         {
14911           if (vex.w)
14912             oappend ("QWORD PTR ");
14913           else
14914             oappend ("DWORD PTR ");
14915         }
14916       else
14917         {
14918           switch (vex.length)
14919             {
14920             case 128:
14921               oappend ("XMMWORD PTR ");
14922               break;
14923             case 256:
14924               oappend ("YMMWORD PTR ");
14925               break;
14926             case 512:
14927               oappend ("ZMMWORD PTR ");
14928               break;
14929             default:
14930               abort ();
14931             }
14932         }
14933       break;
14934     case vex_vsib_q_w_d_mode:
14935     case vex_vsib_d_w_d_mode:
14936       if (!need_vex || !vex.evex)
14937         abort ();
14938
14939       switch (vex.length)
14940         {
14941         case 128:
14942           oappend ("QWORD PTR ");
14943           break;
14944         case 256:
14945           oappend ("XMMWORD PTR ");
14946           break;
14947         case 512:
14948           oappend ("YMMWORD PTR ");
14949           break;
14950         default:
14951           abort ();
14952         }
14953
14954       break;
14955     case mask_bd_mode:
14956       if (!need_vex || vex.length != 128)
14957         abort ();
14958       if (vex.w)
14959         oappend ("DWORD PTR ");
14960       else
14961         oappend ("BYTE PTR ");
14962       break;
14963     case mask_mode:
14964       if (!need_vex)
14965         abort ();
14966       if (vex.w)
14967         oappend ("QWORD PTR ");
14968       else
14969         oappend ("WORD PTR ");
14970       break;
14971     case v_bnd_mode:
14972     default:
14973       break;
14974     }
14975 }
14976
14977 static void
14978 OP_E_register (int bytemode, int sizeflag)
14979 {
14980   int reg = modrm.rm;
14981   const char **names;
14982
14983   USED_REX (REX_B);
14984   if ((rex & REX_B))
14985     reg += 8;
14986
14987   if ((sizeflag & SUFFIX_ALWAYS)
14988       && (bytemode == b_swap_mode
14989           || bytemode == v_swap_mode))
14990     swap_operand ();
14991
14992   switch (bytemode)
14993     {
14994     case b_mode:
14995     case b_swap_mode:
14996       USED_REX (0);
14997       if (rex)
14998         names = names8rex;
14999       else
15000         names = names8;
15001       break;
15002     case w_mode:
15003       names = names16;
15004       break;
15005     case d_mode:
15006     case dw_mode:
15007     case db_mode:
15008       names = names32;
15009       break;
15010     case q_mode:
15011       names = names64;
15012       break;
15013     case m_mode:
15014     case v_bnd_mode:
15015       names = address_mode == mode_64bit ? names64 : names32;
15016       break;
15017     case bnd_mode:
15018       names = names_bnd;
15019       break;
15020     case indir_v_mode:
15021       if (address_mode == mode_64bit && isa64 == intel64)
15022         {
15023           names = names64;
15024           break;
15025         }
15026       /* Fall through.  */
15027     case stack_v_mode:
15028       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
15029         {
15030           names = names64;
15031           break;
15032         }
15033       bytemode = v_mode;
15034       /* Fall through.  */
15035     case v_mode:
15036     case v_swap_mode:
15037     case dq_mode:
15038     case dqb_mode:
15039     case dqd_mode:
15040     case dqw_mode:
15041       USED_REX (REX_W);
15042       if (rex & REX_W)
15043         names = names64;
15044       else
15045         {
15046           if ((sizeflag & DFLAG)
15047               || (bytemode != v_mode
15048                   && bytemode != v_swap_mode))
15049             names = names32;
15050           else
15051             names = names16;
15052           used_prefixes |= (prefixes & PREFIX_DATA);
15053         }
15054       break;
15055     case mask_bd_mode:
15056     case mask_mode:
15057       if (reg > 0x7)
15058         {
15059           oappend ("(bad)");
15060           return;
15061         }
15062       names = names_mask;
15063       break;
15064     case 0:
15065       return;
15066     default:
15067       oappend (INTERNAL_DISASSEMBLER_ERROR);
15068       return;
15069     }
15070   oappend (names[reg]);
15071 }
15072
15073 static void
15074 OP_E_memory (int bytemode, int sizeflag)
15075 {
15076   bfd_vma disp = 0;
15077   int add = (rex & REX_B) ? 8 : 0;
15078   int riprel = 0;
15079   int shift;
15080
15081   if (vex.evex)
15082     {
15083       /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0.  */
15084       if (vex.b
15085           && bytemode != x_mode
15086           && bytemode != xmmq_mode
15087           && bytemode != evex_half_bcst_xmmq_mode)
15088         {
15089           BadOp ();
15090           return;
15091         }
15092       switch (bytemode)
15093         {
15094         case dqw_mode:
15095         case dw_mode:
15096           shift = 1;
15097           break;
15098         case dqb_mode:
15099         case db_mode:
15100           shift = 0;
15101           break;
15102         case vex_vsib_d_w_dq_mode:
15103         case vex_vsib_d_w_d_mode:
15104         case vex_vsib_q_w_dq_mode:
15105         case vex_vsib_q_w_d_mode:
15106         case evex_x_gscat_mode:
15107         case xmm_mdq_mode:
15108           shift = vex.w ? 3 : 2;
15109           break;
15110         case x_mode:
15111         case evex_half_bcst_xmmq_mode:
15112         case xmmq_mode:
15113           if (vex.b)
15114             {
15115               shift = vex.w ? 3 : 2;
15116               break;
15117             }
15118           /* Fall through.  */
15119         case xmmqd_mode:
15120         case xmmdw_mode:
15121         case ymmq_mode:
15122         case evex_x_nobcst_mode:
15123         case x_swap_mode:
15124           switch (vex.length)
15125             {
15126             case 128:
15127               shift = 4;
15128               break;
15129             case 256:
15130               shift = 5;
15131               break;
15132             case 512:
15133               shift = 6;
15134               break;
15135             default:
15136               abort ();
15137             }
15138           break;
15139         case ymm_mode:
15140           shift = 5;
15141           break;
15142         case xmm_mode:
15143           shift = 4;
15144           break;
15145         case xmm_mq_mode:
15146         case q_mode:
15147         case q_scalar_mode:
15148         case q_swap_mode:
15149         case q_scalar_swap_mode:
15150           shift = 3;
15151           break;
15152         case dqd_mode:
15153         case xmm_md_mode:
15154         case d_mode:
15155         case d_scalar_mode:
15156         case d_swap_mode:
15157         case d_scalar_swap_mode:
15158           shift = 2;
15159           break;
15160         case xmm_mw_mode:
15161           shift = 1;
15162           break;
15163         case xmm_mb_mode:
15164           shift = 0;
15165           break;
15166         default:
15167           abort ();
15168         }
15169       /* Make necessary corrections to shift for modes that need it.
15170          For these modes we currently have shift 4, 5 or 6 depending on
15171          vex.length (it corresponds to xmmword, ymmword or zmmword
15172          operand).  We might want to make it 3, 4 or 5 (e.g. for
15173          xmmq_mode).  In case of broadcast enabled the corrections
15174          aren't needed, as element size is always 32 or 64 bits.  */
15175       if (!vex.b
15176           && (bytemode == xmmq_mode
15177               || bytemode == evex_half_bcst_xmmq_mode))
15178         shift -= 1;
15179       else if (bytemode == xmmqd_mode)
15180         shift -= 2;
15181       else if (bytemode == xmmdw_mode)
15182         shift -= 3;
15183       else if (bytemode == ymmq_mode && vex.length == 128)
15184         shift -= 1;
15185     }
15186   else
15187     shift = 0;
15188
15189   USED_REX (REX_B);
15190   if (intel_syntax)
15191     intel_operand_size (bytemode, sizeflag);
15192   append_seg ();
15193
15194   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
15195     {
15196       /* 32/64 bit address mode */
15197       int havedisp;
15198       int havesib;
15199       int havebase;
15200       int haveindex;
15201       int needindex;
15202       int base, rbase;
15203       int vindex = 0;
15204       int scale = 0;
15205       int addr32flag = !((sizeflag & AFLAG)
15206                          || bytemode == v_bnd_mode
15207                          || bytemode == bnd_mode);
15208       const char **indexes64 = names64;
15209       const char **indexes32 = names32;
15210
15211       havesib = 0;
15212       havebase = 1;
15213       haveindex = 0;
15214       base = modrm.rm;
15215
15216       if (base == 4)
15217         {
15218           havesib = 1;
15219           vindex = sib.index;
15220           USED_REX (REX_X);
15221           if (rex & REX_X)
15222             vindex += 8;
15223           switch (bytemode)
15224             {
15225             case vex_vsib_d_w_dq_mode:
15226             case vex_vsib_d_w_d_mode:
15227             case vex_vsib_q_w_dq_mode:
15228             case vex_vsib_q_w_d_mode:
15229               if (!need_vex)
15230                 abort ();
15231               if (vex.evex)
15232                 {
15233                   if (!vex.v)
15234                     vindex += 16;
15235                 }
15236
15237               haveindex = 1;
15238               switch (vex.length)
15239                 {
15240                 case 128:
15241                   indexes64 = indexes32 = names_xmm;
15242                   break;
15243                 case 256:
15244                   if (!vex.w
15245                       || bytemode == vex_vsib_q_w_dq_mode
15246                       || bytemode == vex_vsib_q_w_d_mode)
15247                     indexes64 = indexes32 = names_ymm;
15248                   else
15249                     indexes64 = indexes32 = names_xmm;
15250                   break;
15251                 case 512:
15252                   if (!vex.w
15253                       || bytemode == vex_vsib_q_w_dq_mode
15254                       || bytemode == vex_vsib_q_w_d_mode)
15255                     indexes64 = indexes32 = names_zmm;
15256                   else
15257                     indexes64 = indexes32 = names_ymm;
15258                   break;
15259                 default:
15260                   abort ();
15261                 }
15262               break;
15263             default:
15264               haveindex = vindex != 4;
15265               break;
15266             }
15267           scale = sib.scale;
15268           base = sib.base;
15269           codep++;
15270         }
15271       rbase = base + add;
15272
15273       switch (modrm.mod)
15274         {
15275         case 0:
15276           if (base == 5)
15277             {
15278               havebase = 0;
15279               if (address_mode == mode_64bit && !havesib)
15280                 riprel = 1;
15281               disp = get32s ();
15282             }
15283           break;
15284         case 1:
15285           FETCH_DATA (the_info, codep + 1);
15286           disp = *codep++;
15287           if ((disp & 0x80) != 0)
15288             disp -= 0x100;
15289           if (vex.evex && shift > 0)
15290             disp <<= shift;
15291           break;
15292         case 2:
15293           disp = get32s ();
15294           break;
15295         }
15296
15297       /* In 32bit mode, we need index register to tell [offset] from
15298          [eiz*1 + offset].  */
15299       needindex = (havesib
15300                    && !havebase
15301                    && !haveindex
15302                    && address_mode == mode_32bit);
15303       havedisp = (havebase
15304                   || needindex
15305                   || (havesib && (haveindex || scale != 0)));
15306
15307       if (!intel_syntax)
15308         if (modrm.mod != 0 || base == 5)
15309           {
15310             if (havedisp || riprel)
15311               print_displacement (scratchbuf, disp);
15312             else
15313               print_operand_value (scratchbuf, 1, disp);
15314             oappend (scratchbuf);
15315             if (riprel)
15316               {
15317                 set_op (disp, 1);
15318                 oappend (!addr32flag ? "(%rip)" : "(%eip)");
15319               }
15320           }
15321
15322       if ((havebase || haveindex || riprel)
15323           && (bytemode != v_bnd_mode)
15324           && (bytemode != bnd_mode))
15325         used_prefixes |= PREFIX_ADDR;
15326
15327       if (havedisp || (intel_syntax && riprel))
15328         {
15329           *obufp++ = open_char;
15330           if (intel_syntax && riprel)
15331             {
15332               set_op (disp, 1);
15333               oappend (!addr32flag ? "rip" : "eip");
15334             }
15335           *obufp = '\0';
15336           if (havebase)
15337             oappend (address_mode == mode_64bit && !addr32flag
15338                      ? names64[rbase] : names32[rbase]);
15339           if (havesib)
15340             {
15341               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
15342                  print index to tell base + index from base.  */
15343               if (scale != 0
15344                   || needindex
15345                   || haveindex
15346                   || (havebase && base != ESP_REG_NUM))
15347                 {
15348                   if (!intel_syntax || havebase)
15349                     {
15350                       *obufp++ = separator_char;
15351                       *obufp = '\0';
15352                     }
15353                   if (haveindex)
15354                     oappend (address_mode == mode_64bit && !addr32flag
15355                              ? indexes64[vindex] : indexes32[vindex]);
15356                   else
15357                     oappend (address_mode == mode_64bit && !addr32flag
15358                              ? index64 : index32);
15359
15360                   *obufp++ = scale_char;
15361                   *obufp = '\0';
15362                   sprintf (scratchbuf, "%d", 1 << scale);
15363                   oappend (scratchbuf);
15364                 }
15365             }
15366           if (intel_syntax
15367               && (disp || modrm.mod != 0 || base == 5))
15368             {
15369               if (!havedisp || (bfd_signed_vma) disp >= 0)
15370                 {
15371                   *obufp++ = '+';
15372                   *obufp = '\0';
15373                 }
15374               else if (modrm.mod != 1 && disp != -disp)
15375                 {
15376                   *obufp++ = '-';
15377                   *obufp = '\0';
15378                   disp = - (bfd_signed_vma) disp;
15379                 }
15380
15381               if (havedisp)
15382                 print_displacement (scratchbuf, disp);
15383               else
15384                 print_operand_value (scratchbuf, 1, disp);
15385               oappend (scratchbuf);
15386             }
15387
15388           *obufp++ = close_char;
15389           *obufp = '\0';
15390         }
15391       else if (intel_syntax)
15392         {
15393           if (modrm.mod != 0 || base == 5)
15394             {
15395               if (!active_seg_prefix)
15396                 {
15397                   oappend (names_seg[ds_reg - es_reg]);
15398                   oappend (":");
15399                 }
15400               print_operand_value (scratchbuf, 1, disp);
15401               oappend (scratchbuf);
15402             }
15403         }
15404     }
15405   else
15406     {
15407       /* 16 bit address mode */
15408       used_prefixes |= prefixes & PREFIX_ADDR;
15409       switch (modrm.mod)
15410         {
15411         case 0:
15412           if (modrm.rm == 6)
15413             {
15414               disp = get16 ();
15415               if ((disp & 0x8000) != 0)
15416                 disp -= 0x10000;
15417             }
15418           break;
15419         case 1:
15420           FETCH_DATA (the_info, codep + 1);
15421           disp = *codep++;
15422           if ((disp & 0x80) != 0)
15423             disp -= 0x100;
15424           break;
15425         case 2:
15426           disp = get16 ();
15427           if ((disp & 0x8000) != 0)
15428             disp -= 0x10000;
15429           break;
15430         }
15431
15432       if (!intel_syntax)
15433         if (modrm.mod != 0 || modrm.rm == 6)
15434           {
15435             print_displacement (scratchbuf, disp);
15436             oappend (scratchbuf);
15437           }
15438
15439       if (modrm.mod != 0 || modrm.rm != 6)
15440         {
15441           *obufp++ = open_char;
15442           *obufp = '\0';
15443           oappend (index16[modrm.rm]);
15444           if (intel_syntax
15445               && (disp || modrm.mod != 0 || modrm.rm == 6))
15446             {
15447               if ((bfd_signed_vma) disp >= 0)
15448                 {
15449                   *obufp++ = '+';
15450                   *obufp = '\0';
15451                 }
15452               else if (modrm.mod != 1)
15453                 {
15454                   *obufp++ = '-';
15455                   *obufp = '\0';
15456                   disp = - (bfd_signed_vma) disp;
15457                 }
15458
15459               print_displacement (scratchbuf, disp);
15460               oappend (scratchbuf);
15461             }
15462
15463           *obufp++ = close_char;
15464           *obufp = '\0';
15465         }
15466       else if (intel_syntax)
15467         {
15468           if (!active_seg_prefix)
15469             {
15470               oappend (names_seg[ds_reg - es_reg]);
15471               oappend (":");
15472             }
15473           print_operand_value (scratchbuf, 1, disp & 0xffff);
15474           oappend (scratchbuf);
15475         }
15476     }
15477   if (vex.evex && vex.b
15478       && (bytemode == x_mode
15479           || bytemode == xmmq_mode
15480           || bytemode == evex_half_bcst_xmmq_mode))
15481     {
15482       if (vex.w
15483           || bytemode == xmmq_mode
15484           || bytemode == evex_half_bcst_xmmq_mode)
15485         {
15486           switch (vex.length)
15487             {
15488             case 128:
15489               oappend ("{1to2}");
15490               break;
15491             case 256:
15492               oappend ("{1to4}");
15493               break;
15494             case 512:
15495               oappend ("{1to8}");
15496               break;
15497             default:
15498               abort ();
15499             }
15500         }
15501       else
15502         {
15503           switch (vex.length)
15504             {
15505             case 128:
15506               oappend ("{1to4}");
15507               break;
15508             case 256:
15509               oappend ("{1to8}");
15510               break;
15511             case 512:
15512               oappend ("{1to16}");
15513               break;
15514             default:
15515               abort ();
15516             }
15517         }
15518     }
15519 }
15520
15521 static void
15522 OP_E (int bytemode, int sizeflag)
15523 {
15524   /* Skip mod/rm byte.  */
15525   MODRM_CHECK;
15526   codep++;
15527
15528   if (modrm.mod == 3)
15529     OP_E_register (bytemode, sizeflag);
15530   else
15531     OP_E_memory (bytemode, sizeflag);
15532 }
15533
15534 static void
15535 OP_G (int bytemode, int sizeflag)
15536 {
15537   int add = 0;
15538   USED_REX (REX_R);
15539   if (rex & REX_R)
15540     add += 8;
15541   switch (bytemode)
15542     {
15543     case b_mode:
15544       USED_REX (0);
15545       if (rex)
15546         oappend (names8rex[modrm.reg + add]);
15547       else
15548         oappend (names8[modrm.reg + add]);
15549       break;
15550     case w_mode:
15551       oappend (names16[modrm.reg + add]);
15552       break;
15553     case d_mode:
15554     case db_mode:
15555     case dw_mode:
15556       oappend (names32[modrm.reg + add]);
15557       break;
15558     case q_mode:
15559       oappend (names64[modrm.reg + add]);
15560       break;
15561     case bnd_mode:
15562       oappend (names_bnd[modrm.reg]);
15563       break;
15564     case v_mode:
15565     case dq_mode:
15566     case dqb_mode:
15567     case dqd_mode:
15568     case dqw_mode:
15569       USED_REX (REX_W);
15570       if (rex & REX_W)
15571         oappend (names64[modrm.reg + add]);
15572       else
15573         {
15574           if ((sizeflag & DFLAG) || bytemode != v_mode)
15575             oappend (names32[modrm.reg + add]);
15576           else
15577             oappend (names16[modrm.reg + add]);
15578           used_prefixes |= (prefixes & PREFIX_DATA);
15579         }
15580       break;
15581     case m_mode:
15582       if (address_mode == mode_64bit)
15583         oappend (names64[modrm.reg + add]);
15584       else
15585         oappend (names32[modrm.reg + add]);
15586       break;
15587     case mask_bd_mode:
15588     case mask_mode:
15589       if ((modrm.reg + add) > 0x7)
15590         {
15591           oappend ("(bad)");
15592           return;
15593         }
15594       oappend (names_mask[modrm.reg + add]);
15595       break;
15596     default:
15597       oappend (INTERNAL_DISASSEMBLER_ERROR);
15598       break;
15599     }
15600 }
15601
15602 static bfd_vma
15603 get64 (void)
15604 {
15605   bfd_vma x;
15606 #ifdef BFD64
15607   unsigned int a;
15608   unsigned int b;
15609
15610   FETCH_DATA (the_info, codep + 8);
15611   a = *codep++ & 0xff;
15612   a |= (*codep++ & 0xff) << 8;
15613   a |= (*codep++ & 0xff) << 16;
15614   a |= (*codep++ & 0xffu) << 24;
15615   b = *codep++ & 0xff;
15616   b |= (*codep++ & 0xff) << 8;
15617   b |= (*codep++ & 0xff) << 16;
15618   b |= (*codep++ & 0xffu) << 24;
15619   x = a + ((bfd_vma) b << 32);
15620 #else
15621   abort ();
15622   x = 0;
15623 #endif
15624   return x;
15625 }
15626
15627 static bfd_signed_vma
15628 get32 (void)
15629 {
15630   bfd_signed_vma x = 0;
15631
15632   FETCH_DATA (the_info, codep + 4);
15633   x = *codep++ & (bfd_signed_vma) 0xff;
15634   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15635   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15636   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15637   return x;
15638 }
15639
15640 static bfd_signed_vma
15641 get32s (void)
15642 {
15643   bfd_signed_vma x = 0;
15644
15645   FETCH_DATA (the_info, codep + 4);
15646   x = *codep++ & (bfd_signed_vma) 0xff;
15647   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15648   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15649   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15650
15651   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
15652
15653   return x;
15654 }
15655
15656 static int
15657 get16 (void)
15658 {
15659   int x = 0;
15660
15661   FETCH_DATA (the_info, codep + 2);
15662   x = *codep++ & 0xff;
15663   x |= (*codep++ & 0xff) << 8;
15664   return x;
15665 }
15666
15667 static void
15668 set_op (bfd_vma op, int riprel)
15669 {
15670   op_index[op_ad] = op_ad;
15671   if (address_mode == mode_64bit)
15672     {
15673       op_address[op_ad] = op;
15674       op_riprel[op_ad] = riprel;
15675     }
15676   else
15677     {
15678       /* Mask to get a 32-bit address.  */
15679       op_address[op_ad] = op & 0xffffffff;
15680       op_riprel[op_ad] = riprel & 0xffffffff;
15681     }
15682 }
15683
15684 static void
15685 OP_REG (int code, int sizeflag)
15686 {
15687   const char *s;
15688   int add;
15689
15690   switch (code)
15691     {
15692     case es_reg: case ss_reg: case cs_reg:
15693     case ds_reg: case fs_reg: case gs_reg:
15694       oappend (names_seg[code - es_reg]);
15695       return;
15696     }
15697
15698   USED_REX (REX_B);
15699   if (rex & REX_B)
15700     add = 8;
15701   else
15702     add = 0;
15703
15704   switch (code)
15705     {
15706     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15707     case sp_reg: case bp_reg: case si_reg: case di_reg:
15708       s = names16[code - ax_reg + add];
15709       break;
15710     case al_reg: case ah_reg: case cl_reg: case ch_reg:
15711     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15712       USED_REX (0);
15713       if (rex)
15714         s = names8rex[code - al_reg + add];
15715       else
15716         s = names8[code - al_reg];
15717       break;
15718     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
15719     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
15720       if (address_mode == mode_64bit
15721           && ((sizeflag & DFLAG) || (rex & REX_W)))
15722         {
15723           s = names64[code - rAX_reg + add];
15724           break;
15725         }
15726       code += eAX_reg - rAX_reg;
15727       /* Fall through.  */
15728     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15729     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15730       USED_REX (REX_W);
15731       if (rex & REX_W)
15732         s = names64[code - eAX_reg + add];
15733       else
15734         {
15735           if (sizeflag & DFLAG)
15736             s = names32[code - eAX_reg + add];
15737           else
15738             s = names16[code - eAX_reg + add];
15739           used_prefixes |= (prefixes & PREFIX_DATA);
15740         }
15741       break;
15742     default:
15743       s = INTERNAL_DISASSEMBLER_ERROR;
15744       break;
15745     }
15746   oappend (s);
15747 }
15748
15749 static void
15750 OP_IMREG (int code, int sizeflag)
15751 {
15752   const char *s;
15753
15754   switch (code)
15755     {
15756     case indir_dx_reg:
15757       if (intel_syntax)
15758         s = "dx";
15759       else
15760         s = "(%dx)";
15761       break;
15762     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15763     case sp_reg: case bp_reg: case si_reg: case di_reg:
15764       s = names16[code - ax_reg];
15765       break;
15766     case es_reg: case ss_reg: case cs_reg:
15767     case ds_reg: case fs_reg: case gs_reg:
15768       s = names_seg[code - es_reg];
15769       break;
15770     case al_reg: case ah_reg: case cl_reg: case ch_reg:
15771     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15772       USED_REX (0);
15773       if (rex)
15774         s = names8rex[code - al_reg];
15775       else
15776         s = names8[code - al_reg];
15777       break;
15778     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15779     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15780       USED_REX (REX_W);
15781       if (rex & REX_W)
15782         s = names64[code - eAX_reg];
15783       else
15784         {
15785           if (sizeflag & DFLAG)
15786             s = names32[code - eAX_reg];
15787           else
15788             s = names16[code - eAX_reg];
15789           used_prefixes |= (prefixes & PREFIX_DATA);
15790         }
15791       break;
15792     case z_mode_ax_reg:
15793       if ((rex & REX_W) || (sizeflag & DFLAG))
15794         s = *names32;
15795       else
15796         s = *names16;
15797       if (!(rex & REX_W))
15798         used_prefixes |= (prefixes & PREFIX_DATA);
15799       break;
15800     default:
15801       s = INTERNAL_DISASSEMBLER_ERROR;
15802       break;
15803     }
15804   oappend (s);
15805 }
15806
15807 static void
15808 OP_I (int bytemode, int sizeflag)
15809 {
15810   bfd_signed_vma op;
15811   bfd_signed_vma mask = -1;
15812
15813   switch (bytemode)
15814     {
15815     case b_mode:
15816       FETCH_DATA (the_info, codep + 1);
15817       op = *codep++;
15818       mask = 0xff;
15819       break;
15820     case q_mode:
15821       if (address_mode == mode_64bit)
15822         {
15823           op = get32s ();
15824           break;
15825         }
15826       /* Fall through.  */
15827     case v_mode:
15828       USED_REX (REX_W);
15829       if (rex & REX_W)
15830         op = get32s ();
15831       else
15832         {
15833           if (sizeflag & DFLAG)
15834             {
15835               op = get32 ();
15836               mask = 0xffffffff;
15837             }
15838           else
15839             {
15840               op = get16 ();
15841               mask = 0xfffff;
15842             }
15843           used_prefixes |= (prefixes & PREFIX_DATA);
15844         }
15845       break;
15846     case w_mode:
15847       mask = 0xfffff;
15848       op = get16 ();
15849       break;
15850     case const_1_mode:
15851       if (intel_syntax)
15852         oappend ("1");
15853       return;
15854     default:
15855       oappend (INTERNAL_DISASSEMBLER_ERROR);
15856       return;
15857     }
15858
15859   op &= mask;
15860   scratchbuf[0] = '$';
15861   print_operand_value (scratchbuf + 1, 1, op);
15862   oappend_maybe_intel (scratchbuf);
15863   scratchbuf[0] = '\0';
15864 }
15865
15866 static void
15867 OP_I64 (int bytemode, int sizeflag)
15868 {
15869   bfd_signed_vma op;
15870   bfd_signed_vma mask = -1;
15871
15872   if (address_mode != mode_64bit)
15873     {
15874       OP_I (bytemode, sizeflag);
15875       return;
15876     }
15877
15878   switch (bytemode)
15879     {
15880     case b_mode:
15881       FETCH_DATA (the_info, codep + 1);
15882       op = *codep++;
15883       mask = 0xff;
15884       break;
15885     case v_mode:
15886       USED_REX (REX_W);
15887       if (rex & REX_W)
15888         op = get64 ();
15889       else
15890         {
15891           if (sizeflag & DFLAG)
15892             {
15893               op = get32 ();
15894               mask = 0xffffffff;
15895             }
15896           else
15897             {
15898               op = get16 ();
15899               mask = 0xfffff;
15900             }
15901           used_prefixes |= (prefixes & PREFIX_DATA);
15902         }
15903       break;
15904     case w_mode:
15905       mask = 0xfffff;
15906       op = get16 ();
15907       break;
15908     default:
15909       oappend (INTERNAL_DISASSEMBLER_ERROR);
15910       return;
15911     }
15912
15913   op &= mask;
15914   scratchbuf[0] = '$';
15915   print_operand_value (scratchbuf + 1, 1, op);
15916   oappend_maybe_intel (scratchbuf);
15917   scratchbuf[0] = '\0';
15918 }
15919
15920 static void
15921 OP_sI (int bytemode, int sizeflag)
15922 {
15923   bfd_signed_vma op;
15924
15925   switch (bytemode)
15926     {
15927     case b_mode:
15928     case b_T_mode:
15929       FETCH_DATA (the_info, codep + 1);
15930       op = *codep++;
15931       if ((op & 0x80) != 0)
15932         op -= 0x100;
15933       if (bytemode == b_T_mode)
15934         {
15935           if (address_mode != mode_64bit
15936               || !((sizeflag & DFLAG) || (rex & REX_W)))
15937             {
15938               /* The operand-size prefix is overridden by a REX prefix.  */
15939               if ((sizeflag & DFLAG) || (rex & REX_W))
15940                 op &= 0xffffffff;
15941               else
15942                 op &= 0xffff;
15943           }
15944         }
15945       else
15946         {
15947           if (!(rex & REX_W))
15948             {
15949               if (sizeflag & DFLAG)
15950                 op &= 0xffffffff;
15951               else
15952                 op &= 0xffff;
15953             }
15954         }
15955       break;
15956     case v_mode:
15957       /* The operand-size prefix is overridden by a REX prefix.  */
15958       if ((sizeflag & DFLAG) || (rex & REX_W))
15959         op = get32s ();
15960       else
15961         op = get16 ();
15962       break;
15963     default:
15964       oappend (INTERNAL_DISASSEMBLER_ERROR);
15965       return;
15966     }
15967
15968   scratchbuf[0] = '$';
15969   print_operand_value (scratchbuf + 1, 1, op);
15970   oappend_maybe_intel (scratchbuf);
15971 }
15972
15973 static void
15974 OP_J (int bytemode, int sizeflag)
15975 {
15976   bfd_vma disp;
15977   bfd_vma mask = -1;
15978   bfd_vma segment = 0;
15979
15980   switch (bytemode)
15981     {
15982     case b_mode:
15983       FETCH_DATA (the_info, codep + 1);
15984       disp = *codep++;
15985       if ((disp & 0x80) != 0)
15986         disp -= 0x100;
15987       break;
15988     case v_mode:
15989       if (isa64 == amd64)
15990         USED_REX (REX_W);
15991       if ((sizeflag & DFLAG)
15992           || (address_mode == mode_64bit
15993               && (isa64 != amd64 || (rex & REX_W))))
15994         disp = get32s ();
15995       else
15996         {
15997           disp = get16 ();
15998           if ((disp & 0x8000) != 0)
15999             disp -= 0x10000;
16000           /* In 16bit mode, address is wrapped around at 64k within
16001              the same segment.  Otherwise, a data16 prefix on a jump
16002              instruction means that the pc is masked to 16 bits after
16003              the displacement is added!  */
16004           mask = 0xffff;
16005           if ((prefixes & PREFIX_DATA) == 0)
16006             segment = ((start_pc + (codep - start_codep))
16007                        & ~((bfd_vma) 0xffff));
16008         }
16009       if (address_mode != mode_64bit
16010           || (isa64 == amd64 && !(rex & REX_W)))
16011         used_prefixes |= (prefixes & PREFIX_DATA);
16012       break;
16013     default:
16014       oappend (INTERNAL_DISASSEMBLER_ERROR);
16015       return;
16016     }
16017   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
16018   set_op (disp, 0);
16019   print_operand_value (scratchbuf, 1, disp);
16020   oappend (scratchbuf);
16021 }
16022
16023 static void
16024 OP_SEG (int bytemode, int sizeflag)
16025 {
16026   if (bytemode == w_mode)
16027     oappend (names_seg[modrm.reg]);
16028   else
16029     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
16030 }
16031
16032 static void
16033 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
16034 {
16035   int seg, offset;
16036
16037   if (sizeflag & DFLAG)
16038     {
16039       offset = get32 ();
16040       seg = get16 ();
16041     }
16042   else
16043     {
16044       offset = get16 ();
16045       seg = get16 ();
16046     }
16047   used_prefixes |= (prefixes & PREFIX_DATA);
16048   if (intel_syntax)
16049     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
16050   else
16051     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
16052   oappend (scratchbuf);
16053 }
16054
16055 static void
16056 OP_OFF (int bytemode, int sizeflag)
16057 {
16058   bfd_vma off;
16059
16060   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
16061     intel_operand_size (bytemode, sizeflag);
16062   append_seg ();
16063
16064   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
16065     off = get32 ();
16066   else
16067     off = get16 ();
16068
16069   if (intel_syntax)
16070     {
16071       if (!active_seg_prefix)
16072         {
16073           oappend (names_seg[ds_reg - es_reg]);
16074           oappend (":");
16075         }
16076     }
16077   print_operand_value (scratchbuf, 1, off);
16078   oappend (scratchbuf);
16079 }
16080
16081 static void
16082 OP_OFF64 (int bytemode, int sizeflag)
16083 {
16084   bfd_vma off;
16085
16086   if (address_mode != mode_64bit
16087       || (prefixes & PREFIX_ADDR))
16088     {
16089       OP_OFF (bytemode, sizeflag);
16090       return;
16091     }
16092
16093   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
16094     intel_operand_size (bytemode, sizeflag);
16095   append_seg ();
16096
16097   off = get64 ();
16098
16099   if (intel_syntax)
16100     {
16101       if (!active_seg_prefix)
16102         {
16103           oappend (names_seg[ds_reg - es_reg]);
16104           oappend (":");
16105         }
16106     }
16107   print_operand_value (scratchbuf, 1, off);
16108   oappend (scratchbuf);
16109 }
16110
16111 static void
16112 ptr_reg (int code, int sizeflag)
16113 {
16114   const char *s;
16115
16116   *obufp++ = open_char;
16117   used_prefixes |= (prefixes & PREFIX_ADDR);
16118   if (address_mode == mode_64bit)
16119     {
16120       if (!(sizeflag & AFLAG))
16121         s = names32[code - eAX_reg];
16122       else
16123         s = names64[code - eAX_reg];
16124     }
16125   else if (sizeflag & AFLAG)
16126     s = names32[code - eAX_reg];
16127   else
16128     s = names16[code - eAX_reg];
16129   oappend (s);
16130   *obufp++ = close_char;
16131   *obufp = 0;
16132 }
16133
16134 static void
16135 OP_ESreg (int code, int sizeflag)
16136 {
16137   if (intel_syntax)
16138     {
16139       switch (codep[-1])
16140         {
16141         case 0x6d:      /* insw/insl */
16142           intel_operand_size (z_mode, sizeflag);
16143           break;
16144         case 0xa5:      /* movsw/movsl/movsq */
16145         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
16146         case 0xab:      /* stosw/stosl */
16147         case 0xaf:      /* scasw/scasl */
16148           intel_operand_size (v_mode, sizeflag);
16149           break;
16150         default:
16151           intel_operand_size (b_mode, sizeflag);
16152         }
16153     }
16154   oappend_maybe_intel ("%es:");
16155   ptr_reg (code, sizeflag);
16156 }
16157
16158 static void
16159 OP_DSreg (int code, int sizeflag)
16160 {
16161   if (intel_syntax)
16162     {
16163       switch (codep[-1])
16164         {
16165         case 0x6f:      /* outsw/outsl */
16166           intel_operand_size (z_mode, sizeflag);
16167           break;
16168         case 0xa5:      /* movsw/movsl/movsq */
16169         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
16170         case 0xad:      /* lodsw/lodsl/lodsq */
16171           intel_operand_size (v_mode, sizeflag);
16172           break;
16173         default:
16174           intel_operand_size (b_mode, sizeflag);
16175         }
16176     }
16177   /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
16178      default segment register DS is printed.  */
16179   if (!active_seg_prefix)
16180     active_seg_prefix = PREFIX_DS;
16181   append_seg ();
16182   ptr_reg (code, sizeflag);
16183 }
16184
16185 static void
16186 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16187 {
16188   int add;
16189   if (rex & REX_R)
16190     {
16191       USED_REX (REX_R);
16192       add = 8;
16193     }
16194   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
16195     {
16196       all_prefixes[last_lock_prefix] = 0;
16197       used_prefixes |= PREFIX_LOCK;
16198       add = 8;
16199     }
16200   else
16201     add = 0;
16202   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
16203   oappend_maybe_intel (scratchbuf);
16204 }
16205
16206 static void
16207 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16208 {
16209   int add;
16210   USED_REX (REX_R);
16211   if (rex & REX_R)
16212     add = 8;
16213   else
16214     add = 0;
16215   if (intel_syntax)
16216     sprintf (scratchbuf, "db%d", modrm.reg + add);
16217   else
16218     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
16219   oappend (scratchbuf);
16220 }
16221
16222 static void
16223 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16224 {
16225   sprintf (scratchbuf, "%%tr%d", modrm.reg);
16226   oappend_maybe_intel (scratchbuf);
16227 }
16228
16229 static void
16230 OP_R (int bytemode, int sizeflag)
16231 {
16232   /* Skip mod/rm byte.  */
16233   MODRM_CHECK;
16234   codep++;
16235   OP_E_register (bytemode, sizeflag);
16236 }
16237
16238 static void
16239 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16240 {
16241   int reg = modrm.reg;
16242   const char **names;
16243
16244   used_prefixes |= (prefixes & PREFIX_DATA);
16245   if (prefixes & PREFIX_DATA)
16246     {
16247       names = names_xmm;
16248       USED_REX (REX_R);
16249       if (rex & REX_R)
16250         reg += 8;
16251     }
16252   else
16253     names = names_mm;
16254   oappend (names[reg]);
16255 }
16256
16257 static void
16258 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16259 {
16260   int reg = modrm.reg;
16261   const char **names;
16262
16263   USED_REX (REX_R);
16264   if (rex & REX_R)
16265     reg += 8;
16266   if (vex.evex)
16267     {
16268       if (!vex.r)
16269         reg += 16;
16270     }
16271
16272   if (need_vex
16273       && bytemode != xmm_mode
16274       && bytemode != xmmq_mode
16275       && bytemode != evex_half_bcst_xmmq_mode
16276       && bytemode != ymm_mode
16277       && bytemode != scalar_mode)
16278     {
16279       switch (vex.length)
16280         {
16281         case 128:
16282           names = names_xmm;
16283           break;
16284         case 256:
16285           if (vex.w
16286               || (bytemode != vex_vsib_q_w_dq_mode
16287                   && bytemode != vex_vsib_q_w_d_mode))
16288             names = names_ymm;
16289           else
16290             names = names_xmm;
16291           break;
16292         case 512:
16293           names = names_zmm;
16294           break;
16295         default:
16296           abort ();
16297         }
16298     }
16299   else if (bytemode == xmmq_mode
16300            || bytemode == evex_half_bcst_xmmq_mode)
16301     {
16302       switch (vex.length)
16303         {
16304         case 128:
16305         case 256:
16306           names = names_xmm;
16307           break;
16308         case 512:
16309           names = names_ymm;
16310           break;
16311         default:
16312           abort ();
16313         }
16314     }
16315   else if (bytemode == ymm_mode)
16316     names = names_ymm;
16317   else
16318     names = names_xmm;
16319   oappend (names[reg]);
16320 }
16321
16322 static void
16323 OP_EM (int bytemode, int sizeflag)
16324 {
16325   int reg;
16326   const char **names;
16327
16328   if (modrm.mod != 3)
16329     {
16330       if (intel_syntax
16331           && (bytemode == v_mode || bytemode == v_swap_mode))
16332         {
16333           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16334           used_prefixes |= (prefixes & PREFIX_DATA);
16335         }
16336       OP_E (bytemode, sizeflag);
16337       return;
16338     }
16339
16340   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
16341     swap_operand ();
16342
16343   /* Skip mod/rm byte.  */
16344   MODRM_CHECK;
16345   codep++;
16346   used_prefixes |= (prefixes & PREFIX_DATA);
16347   reg = modrm.rm;
16348   if (prefixes & PREFIX_DATA)
16349     {
16350       names = names_xmm;
16351       USED_REX (REX_B);
16352       if (rex & REX_B)
16353         reg += 8;
16354     }
16355   else
16356     names = names_mm;
16357   oappend (names[reg]);
16358 }
16359
16360 /* cvt* are the only instructions in sse2 which have
16361    both SSE and MMX operands and also have 0x66 prefix
16362    in their opcode. 0x66 was originally used to differentiate
16363    between SSE and MMX instruction(operands). So we have to handle the
16364    cvt* separately using OP_EMC and OP_MXC */
16365 static void
16366 OP_EMC (int bytemode, int sizeflag)
16367 {
16368   if (modrm.mod != 3)
16369     {
16370       if (intel_syntax && bytemode == v_mode)
16371         {
16372           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16373           used_prefixes |= (prefixes & PREFIX_DATA);
16374         }
16375       OP_E (bytemode, sizeflag);
16376       return;
16377     }
16378
16379   /* Skip mod/rm byte.  */
16380   MODRM_CHECK;
16381   codep++;
16382   used_prefixes |= (prefixes & PREFIX_DATA);
16383   oappend (names_mm[modrm.rm]);
16384 }
16385
16386 static void
16387 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16388 {
16389   used_prefixes |= (prefixes & PREFIX_DATA);
16390   oappend (names_mm[modrm.reg]);
16391 }
16392
16393 static void
16394 OP_EX (int bytemode, int sizeflag)
16395 {
16396   int reg;
16397   const char **names;
16398
16399   /* Skip mod/rm byte.  */
16400   MODRM_CHECK;
16401   codep++;
16402
16403   if (modrm.mod != 3)
16404     {
16405       OP_E_memory (bytemode, sizeflag);
16406       return;
16407     }
16408
16409   reg = modrm.rm;
16410   USED_REX (REX_B);
16411   if (rex & REX_B)
16412     reg += 8;
16413   if (vex.evex)
16414     {
16415       USED_REX (REX_X);
16416       if ((rex & REX_X))
16417         reg += 16;
16418     }
16419
16420   if ((sizeflag & SUFFIX_ALWAYS)
16421       && (bytemode == x_swap_mode
16422           || bytemode == d_swap_mode
16423           || bytemode == d_scalar_swap_mode
16424           || bytemode == q_swap_mode
16425           || bytemode == q_scalar_swap_mode))
16426     swap_operand ();
16427
16428   if (need_vex
16429       && bytemode != xmm_mode
16430       && bytemode != xmmdw_mode
16431       && bytemode != xmmqd_mode
16432       && bytemode != xmm_mb_mode
16433       && bytemode != xmm_mw_mode
16434       && bytemode != xmm_md_mode
16435       && bytemode != xmm_mq_mode
16436       && bytemode != xmm_mdq_mode
16437       && bytemode != xmmq_mode
16438       && bytemode != evex_half_bcst_xmmq_mode
16439       && bytemode != ymm_mode
16440       && bytemode != d_scalar_mode
16441       && bytemode != d_scalar_swap_mode
16442       && bytemode != q_scalar_mode
16443       && bytemode != q_scalar_swap_mode
16444       && bytemode != vex_scalar_w_dq_mode)
16445     {
16446       switch (vex.length)
16447         {
16448         case 128:
16449           names = names_xmm;
16450           break;
16451         case 256:
16452           names = names_ymm;
16453           break;
16454         case 512:
16455           names = names_zmm;
16456           break;
16457         default:
16458           abort ();
16459         }
16460     }
16461   else if (bytemode == xmmq_mode
16462            || bytemode == evex_half_bcst_xmmq_mode)
16463     {
16464       switch (vex.length)
16465         {
16466         case 128:
16467         case 256:
16468           names = names_xmm;
16469           break;
16470         case 512:
16471           names = names_ymm;
16472           break;
16473         default:
16474           abort ();
16475         }
16476     }
16477   else if (bytemode == ymm_mode)
16478     names = names_ymm;
16479   else
16480     names = names_xmm;
16481   oappend (names[reg]);
16482 }
16483
16484 static void
16485 OP_MS (int bytemode, int sizeflag)
16486 {
16487   if (modrm.mod == 3)
16488     OP_EM (bytemode, sizeflag);
16489   else
16490     BadOp ();
16491 }
16492
16493 static void
16494 OP_XS (int bytemode, int sizeflag)
16495 {
16496   if (modrm.mod == 3)
16497     OP_EX (bytemode, sizeflag);
16498   else
16499     BadOp ();
16500 }
16501
16502 static void
16503 OP_M (int bytemode, int sizeflag)
16504 {
16505   if (modrm.mod == 3)
16506     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
16507     BadOp ();
16508   else
16509     OP_E (bytemode, sizeflag);
16510 }
16511
16512 static void
16513 OP_0f07 (int bytemode, int sizeflag)
16514 {
16515   if (modrm.mod != 3 || modrm.rm != 0)
16516     BadOp ();
16517   else
16518     OP_E (bytemode, sizeflag);
16519 }
16520
16521 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
16522    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
16523
16524 static void
16525 NOP_Fixup1 (int bytemode, int sizeflag)
16526 {
16527   if ((prefixes & PREFIX_DATA) != 0
16528       || (rex != 0
16529           && rex != 0x48
16530           && address_mode == mode_64bit))
16531     OP_REG (bytemode, sizeflag);
16532   else
16533     strcpy (obuf, "nop");
16534 }
16535
16536 static void
16537 NOP_Fixup2 (int bytemode, int sizeflag)
16538 {
16539   if ((prefixes & PREFIX_DATA) != 0
16540       || (rex != 0
16541           && rex != 0x48
16542           && address_mode == mode_64bit))
16543     OP_IMREG (bytemode, sizeflag);
16544 }
16545
16546 static const char *const Suffix3DNow[] = {
16547 /* 00 */        NULL,           NULL,           NULL,           NULL,
16548 /* 04 */        NULL,           NULL,           NULL,           NULL,
16549 /* 08 */        NULL,           NULL,           NULL,           NULL,
16550 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
16551 /* 10 */        NULL,           NULL,           NULL,           NULL,
16552 /* 14 */        NULL,           NULL,           NULL,           NULL,
16553 /* 18 */        NULL,           NULL,           NULL,           NULL,
16554 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
16555 /* 20 */        NULL,           NULL,           NULL,           NULL,
16556 /* 24 */        NULL,           NULL,           NULL,           NULL,
16557 /* 28 */        NULL,           NULL,           NULL,           NULL,
16558 /* 2C */        NULL,           NULL,           NULL,           NULL,
16559 /* 30 */        NULL,           NULL,           NULL,           NULL,
16560 /* 34 */        NULL,           NULL,           NULL,           NULL,
16561 /* 38 */        NULL,           NULL,           NULL,           NULL,
16562 /* 3C */        NULL,           NULL,           NULL,           NULL,
16563 /* 40 */        NULL,           NULL,           NULL,           NULL,
16564 /* 44 */        NULL,           NULL,           NULL,           NULL,
16565 /* 48 */        NULL,           NULL,           NULL,           NULL,
16566 /* 4C */        NULL,           NULL,           NULL,           NULL,
16567 /* 50 */        NULL,           NULL,           NULL,           NULL,
16568 /* 54 */        NULL,           NULL,           NULL,           NULL,
16569 /* 58 */        NULL,           NULL,           NULL,           NULL,
16570 /* 5C */        NULL,           NULL,           NULL,           NULL,
16571 /* 60 */        NULL,           NULL,           NULL,           NULL,
16572 /* 64 */        NULL,           NULL,           NULL,           NULL,
16573 /* 68 */        NULL,           NULL,           NULL,           NULL,
16574 /* 6C */        NULL,           NULL,           NULL,           NULL,
16575 /* 70 */        NULL,           NULL,           NULL,           NULL,
16576 /* 74 */        NULL,           NULL,           NULL,           NULL,
16577 /* 78 */        NULL,           NULL,           NULL,           NULL,
16578 /* 7C */        NULL,           NULL,           NULL,           NULL,
16579 /* 80 */        NULL,           NULL,           NULL,           NULL,
16580 /* 84 */        NULL,           NULL,           NULL,           NULL,
16581 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
16582 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
16583 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
16584 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
16585 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
16586 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
16587 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
16588 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
16589 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
16590 /* AC */        NULL,           NULL,           "pfacc",        NULL,
16591 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
16592 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
16593 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
16594 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
16595 /* C0 */        NULL,           NULL,           NULL,           NULL,
16596 /* C4 */        NULL,           NULL,           NULL,           NULL,
16597 /* C8 */        NULL,           NULL,           NULL,           NULL,
16598 /* CC */        NULL,           NULL,           NULL,           NULL,
16599 /* D0 */        NULL,           NULL,           NULL,           NULL,
16600 /* D4 */        NULL,           NULL,           NULL,           NULL,
16601 /* D8 */        NULL,           NULL,           NULL,           NULL,
16602 /* DC */        NULL,           NULL,           NULL,           NULL,
16603 /* E0 */        NULL,           NULL,           NULL,           NULL,
16604 /* E4 */        NULL,           NULL,           NULL,           NULL,
16605 /* E8 */        NULL,           NULL,           NULL,           NULL,
16606 /* EC */        NULL,           NULL,           NULL,           NULL,
16607 /* F0 */        NULL,           NULL,           NULL,           NULL,
16608 /* F4 */        NULL,           NULL,           NULL,           NULL,
16609 /* F8 */        NULL,           NULL,           NULL,           NULL,
16610 /* FC */        NULL,           NULL,           NULL,           NULL,
16611 };
16612
16613 static void
16614 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16615 {
16616   const char *mnemonic;
16617
16618   FETCH_DATA (the_info, codep + 1);
16619   /* AMD 3DNow! instructions are specified by an opcode suffix in the
16620      place where an 8-bit immediate would normally go.  ie. the last
16621      byte of the instruction.  */
16622   obufp = mnemonicendp;
16623   mnemonic = Suffix3DNow[*codep++ & 0xff];
16624   if (mnemonic)
16625     oappend (mnemonic);
16626   else
16627     {
16628       /* Since a variable sized modrm/sib chunk is between the start
16629          of the opcode (0x0f0f) and the opcode suffix, we need to do
16630          all the modrm processing first, and don't know until now that
16631          we have a bad opcode.  This necessitates some cleaning up.  */
16632       op_out[0][0] = '\0';
16633       op_out[1][0] = '\0';
16634       BadOp ();
16635     }
16636   mnemonicendp = obufp;
16637 }
16638
16639 static struct op simd_cmp_op[] =
16640 {
16641   { STRING_COMMA_LEN ("eq") },
16642   { STRING_COMMA_LEN ("lt") },
16643   { STRING_COMMA_LEN ("le") },
16644   { STRING_COMMA_LEN ("unord") },
16645   { STRING_COMMA_LEN ("neq") },
16646   { STRING_COMMA_LEN ("nlt") },
16647   { STRING_COMMA_LEN ("nle") },
16648   { STRING_COMMA_LEN ("ord") }
16649 };
16650
16651 static void
16652 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16653 {
16654   unsigned int cmp_type;
16655
16656   FETCH_DATA (the_info, codep + 1);
16657   cmp_type = *codep++ & 0xff;
16658   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
16659     {
16660       char suffix [3];
16661       char *p = mnemonicendp - 2;
16662       suffix[0] = p[0];
16663       suffix[1] = p[1];
16664       suffix[2] = '\0';
16665       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16666       mnemonicendp += simd_cmp_op[cmp_type].len;
16667     }
16668   else
16669     {
16670       /* We have a reserved extension byte.  Output it directly.  */
16671       scratchbuf[0] = '$';
16672       print_operand_value (scratchbuf + 1, 1, cmp_type);
16673       oappend_maybe_intel (scratchbuf);
16674       scratchbuf[0] = '\0';
16675     }
16676 }
16677
16678 static void
16679 OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED,
16680           int sizeflag ATTRIBUTE_UNUSED)
16681 {
16682   /* mwaitx %eax,%ecx,%ebx */
16683   if (!intel_syntax)
16684     {
16685       const char **names = (address_mode == mode_64bit
16686                             ? names64 : names32);
16687       strcpy (op_out[0], names[0]);
16688       strcpy (op_out[1], names[1]);
16689       strcpy (op_out[2], names[3]);
16690       two_source_ops = 1;
16691     }
16692   /* Skip mod/rm byte.  */
16693   MODRM_CHECK;
16694   codep++;
16695 }
16696
16697 static void
16698 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
16699           int sizeflag ATTRIBUTE_UNUSED)
16700 {
16701   /* mwait %eax,%ecx  */
16702   if (!intel_syntax)
16703     {
16704       const char **names = (address_mode == mode_64bit
16705                             ? names64 : names32);
16706       strcpy (op_out[0], names[0]);
16707       strcpy (op_out[1], names[1]);
16708       two_source_ops = 1;
16709     }
16710   /* Skip mod/rm byte.  */
16711   MODRM_CHECK;
16712   codep++;
16713 }
16714
16715 static void
16716 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
16717             int sizeflag ATTRIBUTE_UNUSED)
16718 {
16719   /* monitor %eax,%ecx,%edx"  */
16720   if (!intel_syntax)
16721     {
16722       const char **op1_names;
16723       const char **names = (address_mode == mode_64bit
16724                             ? names64 : names32);
16725
16726       if (!(prefixes & PREFIX_ADDR))
16727         op1_names = (address_mode == mode_16bit
16728                      ? names16 : names);
16729       else
16730         {
16731           /* Remove "addr16/addr32".  */
16732           all_prefixes[last_addr_prefix] = 0;
16733           op1_names = (address_mode != mode_32bit
16734                        ? names32 : names16);
16735           used_prefixes |= PREFIX_ADDR;
16736         }
16737       strcpy (op_out[0], op1_names[0]);
16738       strcpy (op_out[1], names[1]);
16739       strcpy (op_out[2], names[2]);
16740       two_source_ops = 1;
16741     }
16742   /* Skip mod/rm byte.  */
16743   MODRM_CHECK;
16744   codep++;
16745 }
16746
16747 static void
16748 BadOp (void)
16749 {
16750   /* Throw away prefixes and 1st. opcode byte.  */
16751   codep = insn_codep + 1;
16752   oappend ("(bad)");
16753 }
16754
16755 static void
16756 REP_Fixup (int bytemode, int sizeflag)
16757 {
16758   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
16759      lods and stos.  */
16760   if (prefixes & PREFIX_REPZ)
16761     all_prefixes[last_repz_prefix] = REP_PREFIX;
16762
16763   switch (bytemode)
16764     {
16765     case al_reg:
16766     case eAX_reg:
16767     case indir_dx_reg:
16768       OP_IMREG (bytemode, sizeflag);
16769       break;
16770     case eDI_reg:
16771       OP_ESreg (bytemode, sizeflag);
16772       break;
16773     case eSI_reg:
16774       OP_DSreg (bytemode, sizeflag);
16775       break;
16776     default:
16777       abort ();
16778       break;
16779     }
16780 }
16781
16782 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
16783    "bnd".  */
16784
16785 static void
16786 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16787 {
16788   if (prefixes & PREFIX_REPNZ)
16789     all_prefixes[last_repnz_prefix] = BND_PREFIX;
16790 }
16791
16792 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
16793    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
16794  */
16795
16796 static void
16797 HLE_Fixup1 (int bytemode, int sizeflag)
16798 {
16799   if (modrm.mod != 3
16800       && (prefixes & PREFIX_LOCK) != 0)
16801     {
16802       if (prefixes & PREFIX_REPZ)
16803         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16804       if (prefixes & PREFIX_REPNZ)
16805         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16806     }
16807
16808   OP_E (bytemode, sizeflag);
16809 }
16810
16811 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
16812    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
16813  */
16814
16815 static void
16816 HLE_Fixup2 (int bytemode, int sizeflag)
16817 {
16818   if (modrm.mod != 3)
16819     {
16820       if (prefixes & PREFIX_REPZ)
16821         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16822       if (prefixes & PREFIX_REPNZ)
16823         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16824     }
16825
16826   OP_E (bytemode, sizeflag);
16827 }
16828
16829 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
16830    "xrelease" for memory operand.  No check for LOCK prefix.   */
16831
16832 static void
16833 HLE_Fixup3 (int bytemode, int sizeflag)
16834 {
16835   if (modrm.mod != 3
16836       && last_repz_prefix > last_repnz_prefix
16837       && (prefixes & PREFIX_REPZ) != 0)
16838     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16839
16840   OP_E (bytemode, sizeflag);
16841 }
16842
16843 static void
16844 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
16845 {
16846   USED_REX (REX_W);
16847   if (rex & REX_W)
16848     {
16849       /* Change cmpxchg8b to cmpxchg16b.  */
16850       char *p = mnemonicendp - 2;
16851       mnemonicendp = stpcpy (p, "16b");
16852       bytemode = o_mode;
16853     }
16854   else if ((prefixes & PREFIX_LOCK) != 0)
16855     {
16856       if (prefixes & PREFIX_REPZ)
16857         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16858       if (prefixes & PREFIX_REPNZ)
16859         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16860     }
16861
16862   OP_M (bytemode, sizeflag);
16863 }
16864
16865 static void
16866 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
16867 {
16868   const char **names;
16869
16870   if (need_vex)
16871     {
16872       switch (vex.length)
16873         {
16874         case 128:
16875           names = names_xmm;
16876           break;
16877         case 256:
16878           names = names_ymm;
16879           break;
16880         default:
16881           abort ();
16882         }
16883     }
16884   else
16885     names = names_xmm;
16886   oappend (names[reg]);
16887 }
16888
16889 static void
16890 CRC32_Fixup (int bytemode, int sizeflag)
16891 {
16892   /* Add proper suffix to "crc32".  */
16893   char *p = mnemonicendp;
16894
16895   switch (bytemode)
16896     {
16897     case b_mode:
16898       if (intel_syntax)
16899         goto skip;
16900
16901       *p++ = 'b';
16902       break;
16903     case v_mode:
16904       if (intel_syntax)
16905         goto skip;
16906
16907       USED_REX (REX_W);
16908       if (rex & REX_W)
16909         *p++ = 'q';
16910       else
16911         {
16912           if (sizeflag & DFLAG)
16913             *p++ = 'l';
16914           else
16915             *p++ = 'w';
16916           used_prefixes |= (prefixes & PREFIX_DATA);
16917         }
16918       break;
16919     default:
16920       oappend (INTERNAL_DISASSEMBLER_ERROR);
16921       break;
16922     }
16923   mnemonicendp = p;
16924   *p = '\0';
16925
16926 skip:
16927   if (modrm.mod == 3)
16928     {
16929       int add;
16930
16931       /* Skip mod/rm byte.  */
16932       MODRM_CHECK;
16933       codep++;
16934
16935       USED_REX (REX_B);
16936       add = (rex & REX_B) ? 8 : 0;
16937       if (bytemode == b_mode)
16938         {
16939           USED_REX (0);
16940           if (rex)
16941             oappend (names8rex[modrm.rm + add]);
16942           else
16943             oappend (names8[modrm.rm + add]);
16944         }
16945       else
16946         {
16947           USED_REX (REX_W);
16948           if (rex & REX_W)
16949             oappend (names64[modrm.rm + add]);
16950           else if ((prefixes & PREFIX_DATA))
16951             oappend (names16[modrm.rm + add]);
16952           else
16953             oappend (names32[modrm.rm + add]);
16954         }
16955     }
16956   else
16957     OP_E (bytemode, sizeflag);
16958 }
16959
16960 static void
16961 FXSAVE_Fixup (int bytemode, int sizeflag)
16962 {
16963   /* Add proper suffix to "fxsave" and "fxrstor".  */
16964   USED_REX (REX_W);
16965   if (rex & REX_W)
16966     {
16967       char *p = mnemonicendp;
16968       *p++ = '6';
16969       *p++ = '4';
16970       *p = '\0';
16971       mnemonicendp = p;
16972     }
16973   OP_M (bytemode, sizeflag);
16974 }
16975
16976 static void
16977 PCMPESTR_Fixup (int bytemode, int sizeflag)
16978 {
16979   /* Add proper suffix to "{,v}pcmpestr{i,m}".  */
16980   if (!intel_syntax)
16981     {
16982       char *p = mnemonicendp;
16983
16984       USED_REX (REX_W);
16985       if (rex & REX_W)
16986         *p++ = 'q';
16987       else if (sizeflag & SUFFIX_ALWAYS)
16988         *p++ = 'l';
16989
16990       *p = '\0';
16991       mnemonicendp = p;
16992     }
16993
16994   OP_EX (bytemode, sizeflag);
16995 }
16996
16997 /* Display the destination register operand for instructions with
16998    VEX. */
16999
17000 static void
17001 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17002 {
17003   int reg;
17004   const char **names;
17005
17006   if (!need_vex)
17007     abort ();
17008
17009   if (!need_vex_reg)
17010     return;
17011
17012   reg = vex.register_specifier;
17013   if (vex.evex)
17014     {
17015       if (!vex.v)
17016         reg += 16;
17017     }
17018
17019   if (bytemode == vex_scalar_mode)
17020     {
17021       oappend (names_xmm[reg]);
17022       return;
17023     }
17024
17025   switch (vex.length)
17026     {
17027     case 128:
17028       switch (bytemode)
17029         {
17030         case vex_mode:
17031         case vex128_mode:
17032         case vex_vsib_q_w_dq_mode:
17033         case vex_vsib_q_w_d_mode:
17034           names = names_xmm;
17035           break;
17036         case dq_mode:
17037           if (vex.w)
17038             names = names64;
17039           else
17040             names = names32;
17041           break;
17042         case mask_bd_mode:
17043         case mask_mode:
17044           if (reg > 0x7)
17045             {
17046               oappend ("(bad)");
17047               return;
17048             }
17049           names = names_mask;
17050           break;
17051         default:
17052           abort ();
17053           return;
17054         }
17055       break;
17056     case 256:
17057       switch (bytemode)
17058         {
17059         case vex_mode:
17060         case vex256_mode:
17061           names = names_ymm;
17062           break;
17063         case vex_vsib_q_w_dq_mode:
17064         case vex_vsib_q_w_d_mode:
17065           names = vex.w ? names_ymm : names_xmm;
17066           break;
17067         case mask_bd_mode:
17068         case mask_mode:
17069           if (reg > 0x7)
17070             {
17071               oappend ("(bad)");
17072               return;
17073             }
17074           names = names_mask;
17075           break;
17076         default:
17077           /* See PR binutils/20893 for a reproducer.  */
17078           oappend ("(bad)");
17079           return;
17080         }
17081       break;
17082     case 512:
17083       names = names_zmm;
17084       break;
17085     default:
17086       abort ();
17087       break;
17088     }
17089   oappend (names[reg]);
17090 }
17091
17092 /* Get the VEX immediate byte without moving codep.  */
17093
17094 static unsigned char
17095 get_vex_imm8 (int sizeflag, int opnum)
17096 {
17097   int bytes_before_imm = 0;
17098
17099   if (modrm.mod != 3)
17100     {
17101       /* There are SIB/displacement bytes.  */
17102       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
17103         {
17104           /* 32/64 bit address mode */
17105           int base = modrm.rm;
17106
17107           /* Check SIB byte.  */
17108           if (base == 4)
17109             {
17110               FETCH_DATA (the_info, codep + 1);
17111               base = *codep & 7;
17112               /* When decoding the third source, don't increase
17113                  bytes_before_imm as this has already been incremented
17114                  by one in OP_E_memory while decoding the second
17115                  source operand.  */
17116               if (opnum == 0)
17117                 bytes_before_imm++;
17118             }
17119
17120           /* Don't increase bytes_before_imm when decoding the third source,
17121              it has already been incremented by OP_E_memory while decoding
17122              the second source operand.  */
17123           if (opnum == 0)
17124             {
17125               switch (modrm.mod)
17126                 {
17127                   case 0:
17128                     /* When modrm.rm == 5 or modrm.rm == 4 and base in
17129                        SIB == 5, there is a 4 byte displacement.  */
17130                     if (base != 5)
17131                       /* No displacement. */
17132                       break;
17133                     /* Fall through.  */
17134                   case 2:
17135                     /* 4 byte displacement.  */
17136                     bytes_before_imm += 4;
17137                     break;
17138                   case 1:
17139                     /* 1 byte displacement.  */
17140                     bytes_before_imm++;
17141                     break;
17142                 }
17143             }
17144         }
17145       else
17146         {
17147           /* 16 bit address mode */
17148           /* Don't increase bytes_before_imm when decoding the third source,
17149              it has already been incremented by OP_E_memory while decoding
17150              the second source operand.  */
17151           if (opnum == 0)
17152             {
17153               switch (modrm.mod)
17154                 {
17155                 case 0:
17156                   /* When modrm.rm == 6, there is a 2 byte displacement.  */
17157                   if (modrm.rm != 6)
17158                     /* No displacement. */
17159                     break;
17160                   /* Fall through.  */
17161                 case 2:
17162                   /* 2 byte displacement.  */
17163                   bytes_before_imm += 2;
17164                   break;
17165                 case 1:
17166                   /* 1 byte displacement: when decoding the third source,
17167                      don't increase bytes_before_imm as this has already
17168                      been incremented by one in OP_E_memory while decoding
17169                      the second source operand.  */
17170                   if (opnum == 0)
17171                     bytes_before_imm++;
17172
17173                   break;
17174                 }
17175             }
17176         }
17177     }
17178
17179   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
17180   return codep [bytes_before_imm];
17181 }
17182
17183 static void
17184 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
17185 {
17186   const char **names;
17187
17188   if (reg == -1 && modrm.mod != 3)
17189     {
17190       OP_E_memory (bytemode, sizeflag);
17191       return;
17192     }
17193   else
17194     {
17195       if (reg == -1)
17196         {
17197           reg = modrm.rm;
17198           USED_REX (REX_B);
17199           if (rex & REX_B)
17200             reg += 8;
17201         }
17202       else if (reg > 7 && address_mode != mode_64bit)
17203         BadOp ();
17204     }
17205
17206   switch (vex.length)
17207     {
17208     case 128:
17209       names = names_xmm;
17210       break;
17211     case 256:
17212       names = names_ymm;
17213       break;
17214     default:
17215       abort ();
17216     }
17217   oappend (names[reg]);
17218 }
17219
17220 static void
17221 OP_EX_VexImmW (int bytemode, int sizeflag)
17222 {
17223   int reg = -1;
17224   static unsigned char vex_imm8;
17225
17226   if (vex_w_done == 0)
17227     {
17228       vex_w_done = 1;
17229
17230       /* Skip mod/rm byte.  */
17231       MODRM_CHECK;
17232       codep++;
17233
17234       vex_imm8 = get_vex_imm8 (sizeflag, 0);
17235
17236       if (vex.w)
17237           reg = vex_imm8 >> 4;
17238
17239       OP_EX_VexReg (bytemode, sizeflag, reg);
17240     }
17241   else if (vex_w_done == 1)
17242     {
17243       vex_w_done = 2;
17244
17245       if (!vex.w)
17246           reg = vex_imm8 >> 4;
17247
17248       OP_EX_VexReg (bytemode, sizeflag, reg);
17249     }
17250   else
17251     {
17252       /* Output the imm8 directly.  */
17253       scratchbuf[0] = '$';
17254       print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
17255       oappend_maybe_intel (scratchbuf);
17256       scratchbuf[0] = '\0';
17257       codep++;
17258     }
17259 }
17260
17261 static void
17262 OP_Vex_2src (int bytemode, int sizeflag)
17263 {
17264   if (modrm.mod == 3)
17265     {
17266       int reg = modrm.rm;
17267       USED_REX (REX_B);
17268       if (rex & REX_B)
17269         reg += 8;
17270       oappend (names_xmm[reg]);
17271     }
17272   else
17273     {
17274       if (intel_syntax
17275           && (bytemode == v_mode || bytemode == v_swap_mode))
17276         {
17277           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
17278           used_prefixes |= (prefixes & PREFIX_DATA);
17279         }
17280       OP_E (bytemode, sizeflag);
17281     }
17282 }
17283
17284 static void
17285 OP_Vex_2src_1 (int bytemode, int sizeflag)
17286 {
17287   if (modrm.mod == 3)
17288     {
17289       /* Skip mod/rm byte.   */
17290       MODRM_CHECK;
17291       codep++;
17292     }
17293
17294   if (vex.w)
17295     oappend (names_xmm[vex.register_specifier]);
17296   else
17297     OP_Vex_2src (bytemode, sizeflag);
17298 }
17299
17300 static void
17301 OP_Vex_2src_2 (int bytemode, int sizeflag)
17302 {
17303   if (vex.w)
17304     OP_Vex_2src (bytemode, sizeflag);
17305   else
17306     oappend (names_xmm[vex.register_specifier]);
17307 }
17308
17309 static void
17310 OP_EX_VexW (int bytemode, int sizeflag)
17311 {
17312   int reg = -1;
17313
17314   if (!vex_w_done)
17315     {
17316       vex_w_done = 1;
17317
17318       /* Skip mod/rm byte.  */
17319       MODRM_CHECK;
17320       codep++;
17321
17322       if (vex.w)
17323         reg = get_vex_imm8 (sizeflag, 0) >> 4;
17324     }
17325   else
17326     {
17327       if (!vex.w)
17328         reg = get_vex_imm8 (sizeflag, 1) >> 4;
17329     }
17330
17331   OP_EX_VexReg (bytemode, sizeflag, reg);
17332 }
17333
17334 static void
17335 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,
17336              int sizeflag ATTRIBUTE_UNUSED)
17337 {
17338   /* Skip the immediate byte and check for invalid bits.  */
17339   FETCH_DATA (the_info, codep + 1);
17340   if (*codep++ & 0xf)
17341     BadOp ();
17342 }
17343
17344 static void
17345 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17346 {
17347   int reg;
17348   const char **names;
17349
17350   FETCH_DATA (the_info, codep + 1);
17351   reg = *codep++;
17352
17353   if (bytemode != x_mode)
17354     abort ();
17355
17356   if (reg & 0xf)
17357       BadOp ();
17358
17359   reg >>= 4;
17360   if (reg > 7 && address_mode != mode_64bit)
17361     BadOp ();
17362
17363   switch (vex.length)
17364     {
17365     case 128:
17366       names = names_xmm;
17367       break;
17368     case 256:
17369       names = names_ymm;
17370       break;
17371     default:
17372       abort ();
17373     }
17374   oappend (names[reg]);
17375 }
17376
17377 static void
17378 OP_XMM_VexW (int bytemode, int sizeflag)
17379 {
17380   /* Turn off the REX.W bit since it is used for swapping operands
17381      now.  */
17382   rex &= ~REX_W;
17383   OP_XMM (bytemode, sizeflag);
17384 }
17385
17386 static void
17387 OP_EX_Vex (int bytemode, int sizeflag)
17388 {
17389   if (modrm.mod != 3)
17390     {
17391       if (vex.register_specifier != 0)
17392         BadOp ();
17393       need_vex_reg = 0;
17394     }
17395   OP_EX (bytemode, sizeflag);
17396 }
17397
17398 static void
17399 OP_XMM_Vex (int bytemode, int sizeflag)
17400 {
17401   if (modrm.mod != 3)
17402     {
17403       if (vex.register_specifier != 0)
17404         BadOp ();
17405       need_vex_reg = 0;
17406     }
17407   OP_XMM (bytemode, sizeflag);
17408 }
17409
17410 static void
17411 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17412 {
17413   switch (vex.length)
17414     {
17415     case 128:
17416       mnemonicendp = stpcpy (obuf, "vzeroupper");
17417       break;
17418     case 256:
17419       mnemonicendp = stpcpy (obuf, "vzeroall");
17420       break;
17421     default:
17422       abort ();
17423     }
17424 }
17425
17426 static struct op vex_cmp_op[] =
17427 {
17428   { STRING_COMMA_LEN ("eq") },
17429   { STRING_COMMA_LEN ("lt") },
17430   { STRING_COMMA_LEN ("le") },
17431   { STRING_COMMA_LEN ("unord") },
17432   { STRING_COMMA_LEN ("neq") },
17433   { STRING_COMMA_LEN ("nlt") },
17434   { STRING_COMMA_LEN ("nle") },
17435   { STRING_COMMA_LEN ("ord") },
17436   { STRING_COMMA_LEN ("eq_uq") },
17437   { STRING_COMMA_LEN ("nge") },
17438   { STRING_COMMA_LEN ("ngt") },
17439   { STRING_COMMA_LEN ("false") },
17440   { STRING_COMMA_LEN ("neq_oq") },
17441   { STRING_COMMA_LEN ("ge") },
17442   { STRING_COMMA_LEN ("gt") },
17443   { STRING_COMMA_LEN ("true") },
17444   { STRING_COMMA_LEN ("eq_os") },
17445   { STRING_COMMA_LEN ("lt_oq") },
17446   { STRING_COMMA_LEN ("le_oq") },
17447   { STRING_COMMA_LEN ("unord_s") },
17448   { STRING_COMMA_LEN ("neq_us") },
17449   { STRING_COMMA_LEN ("nlt_uq") },
17450   { STRING_COMMA_LEN ("nle_uq") },
17451   { STRING_COMMA_LEN ("ord_s") },
17452   { STRING_COMMA_LEN ("eq_us") },
17453   { STRING_COMMA_LEN ("nge_uq") },
17454   { STRING_COMMA_LEN ("ngt_uq") },
17455   { STRING_COMMA_LEN ("false_os") },
17456   { STRING_COMMA_LEN ("neq_os") },
17457   { STRING_COMMA_LEN ("ge_oq") },
17458   { STRING_COMMA_LEN ("gt_oq") },
17459   { STRING_COMMA_LEN ("true_us") },
17460 };
17461
17462 static void
17463 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17464 {
17465   unsigned int cmp_type;
17466
17467   FETCH_DATA (the_info, codep + 1);
17468   cmp_type = *codep++ & 0xff;
17469   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
17470     {
17471       char suffix [3];
17472       char *p = mnemonicendp - 2;
17473       suffix[0] = p[0];
17474       suffix[1] = p[1];
17475       suffix[2] = '\0';
17476       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
17477       mnemonicendp += vex_cmp_op[cmp_type].len;
17478     }
17479   else
17480     {
17481       /* We have a reserved extension byte.  Output it directly.  */
17482       scratchbuf[0] = '$';
17483       print_operand_value (scratchbuf + 1, 1, cmp_type);
17484       oappend_maybe_intel (scratchbuf);
17485       scratchbuf[0] = '\0';
17486     }
17487 }
17488
17489 static void
17490 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
17491              int sizeflag ATTRIBUTE_UNUSED)
17492 {
17493   unsigned int cmp_type;
17494
17495   if (!vex.evex)
17496     abort ();
17497
17498   FETCH_DATA (the_info, codep + 1);
17499   cmp_type = *codep++ & 0xff;
17500   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
17501      If it's the case, print suffix, otherwise - print the immediate.  */
17502   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
17503       && cmp_type != 3
17504       && cmp_type != 7)
17505     {
17506       char suffix [3];
17507       char *p = mnemonicendp - 2;
17508
17509       /* vpcmp* can have both one- and two-lettered suffix.  */
17510       if (p[0] == 'p')
17511         {
17512           p++;
17513           suffix[0] = p[0];
17514           suffix[1] = '\0';
17515         }
17516       else
17517         {
17518           suffix[0] = p[0];
17519           suffix[1] = p[1];
17520           suffix[2] = '\0';
17521         }
17522
17523       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
17524       mnemonicendp += simd_cmp_op[cmp_type].len;
17525     }
17526   else
17527     {
17528       /* We have a reserved extension byte.  Output it directly.  */
17529       scratchbuf[0] = '$';
17530       print_operand_value (scratchbuf + 1, 1, cmp_type);
17531       oappend_maybe_intel (scratchbuf);
17532       scratchbuf[0] = '\0';
17533     }
17534 }
17535
17536 static const struct op pclmul_op[] =
17537 {
17538   { STRING_COMMA_LEN ("lql") },
17539   { STRING_COMMA_LEN ("hql") },
17540   { STRING_COMMA_LEN ("lqh") },
17541   { STRING_COMMA_LEN ("hqh") }
17542 };
17543
17544 static void
17545 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
17546               int sizeflag ATTRIBUTE_UNUSED)
17547 {
17548   unsigned int pclmul_type;
17549
17550   FETCH_DATA (the_info, codep + 1);
17551   pclmul_type = *codep++ & 0xff;
17552   switch (pclmul_type)
17553     {
17554     case 0x10:
17555       pclmul_type = 2;
17556       break;
17557     case 0x11:
17558       pclmul_type = 3;
17559       break;
17560     default:
17561       break;
17562     }
17563   if (pclmul_type < ARRAY_SIZE (pclmul_op))
17564     {
17565       char suffix [4];
17566       char *p = mnemonicendp - 3;
17567       suffix[0] = p[0];
17568       suffix[1] = p[1];
17569       suffix[2] = p[2];
17570       suffix[3] = '\0';
17571       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
17572       mnemonicendp += pclmul_op[pclmul_type].len;
17573     }
17574   else
17575     {
17576       /* We have a reserved extension byte.  Output it directly.  */
17577       scratchbuf[0] = '$';
17578       print_operand_value (scratchbuf + 1, 1, pclmul_type);
17579       oappend_maybe_intel (scratchbuf);
17580       scratchbuf[0] = '\0';
17581     }
17582 }
17583
17584 static void
17585 MOVBE_Fixup (int bytemode, int sizeflag)
17586 {
17587   /* Add proper suffix to "movbe".  */
17588   char *p = mnemonicendp;
17589
17590   switch (bytemode)
17591     {
17592     case v_mode:
17593       if (intel_syntax)
17594         goto skip;
17595
17596       USED_REX (REX_W);
17597       if (sizeflag & SUFFIX_ALWAYS)
17598         {
17599           if (rex & REX_W)
17600             *p++ = 'q';
17601           else
17602             {
17603               if (sizeflag & DFLAG)
17604                 *p++ = 'l';
17605               else
17606                 *p++ = 'w';
17607               used_prefixes |= (prefixes & PREFIX_DATA);
17608             }
17609         }
17610       break;
17611     default:
17612       oappend (INTERNAL_DISASSEMBLER_ERROR);
17613       break;
17614     }
17615   mnemonicendp = p;
17616   *p = '\0';
17617
17618 skip:
17619   OP_M (bytemode, sizeflag);
17620 }
17621
17622 static void
17623 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17624 {
17625   int reg;
17626   const char **names;
17627
17628   /* Skip mod/rm byte.  */
17629   MODRM_CHECK;
17630   codep++;
17631
17632   if (vex.w)
17633     names = names64;
17634   else
17635     names = names32;
17636
17637   reg = modrm.rm;
17638   USED_REX (REX_B);
17639   if (rex & REX_B)
17640     reg += 8;
17641
17642   oappend (names[reg]);
17643 }
17644
17645 static void
17646 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17647 {
17648   const char **names;
17649
17650   if (vex.w)
17651     names = names64;
17652   else
17653     names = names32;
17654
17655   oappend (names[vex.register_specifier]);
17656 }
17657
17658 static void
17659 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17660 {
17661   if (!vex.evex
17662       || (bytemode != mask_mode && bytemode != mask_bd_mode))
17663     abort ();
17664
17665   USED_REX (REX_R);
17666   if ((rex & REX_R) != 0 || !vex.r)
17667     {
17668       BadOp ();
17669       return;
17670     }
17671
17672   oappend (names_mask [modrm.reg]);
17673 }
17674
17675 static void
17676 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17677 {
17678   if (!vex.evex
17679       || (bytemode != evex_rounding_mode
17680           && bytemode != evex_sae_mode))
17681     abort ();
17682   if (modrm.mod == 3 && vex.b)
17683     switch (bytemode)
17684       {
17685       case evex_rounding_mode:
17686         oappend (names_rounding[vex.ll]);
17687         break;
17688       case evex_sae_mode:
17689         oappend ("{sae}");
17690         break;
17691       default:
17692         break;
17693       }
17694 }