opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
   3    2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012
   4    Free Software Foundation, Inc.
   5
   6    This file is part of the GNU opcodes library.
   7
   8    This library is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3, or (at your option)
  11    any later version.
  12
  13    It is distributed in the hope that it will be useful, but WITHOUT
  14    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  16    License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; if not, write to the Free Software
  20    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  21    MA 02110-1301, USA.  */
  22
  23
  24 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  25    July 1988
  26     modified by John Hassey (hassey@dg-rtp.dg.com)
  27     x86-64 support added by Jan Hubicka (jh@suse.cz)
  28     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  29
  30 /* The main tables describing the instructions is essentially a copy
  31    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  32    Programmers Manual.  Usually, there is a capital letter, followed
  33    by a small letter.  The capital letter tell the addressing mode,
  34    and the small letter tells about the operand size.  Refer to
  35    the Intel manual for details.  */
  36
  37 #include "sysdep.h"
  38 #include "dis-asm.h"
  39 #include "opintl.h"
  40 #include "opcode/i386.h"
  41 #include "libiberty.h"
  42
  43 #include <setjmp.h>
  44
  45 static int print_insn (bfd_vma, disassemble_info *);
  46 static void dofloat (int);
  47 static void OP_ST (int, int);
  48 static void OP_STi (int, int);
  49 static int putop (const char *, int);
  50 static void oappend (const char *);
  51 static void append_seg (void);
  52 static void OP_indirE (int, int);
  53 static void print_operand_value (char *, int, bfd_vma);
  54 static void OP_E_register (int, int);
  55 static void OP_E_memory (int, int);
  56 static void print_displacement (char *, bfd_vma);
  57 static void OP_E (int, int);
  58 static void OP_G (int, int);
  59 static bfd_vma get64 (void);
  60 static bfd_signed_vma get32 (void);
  61 static bfd_signed_vma get32s (void);
  62 static int get16 (void);
  63 static void set_op (bfd_vma, int);
  64 static void OP_Skip_MODRM (int, int);
  65 static void OP_REG (int, int);
  66 static void OP_IMREG (int, int);
  67 static void OP_I (int, int);
  68 static void OP_I64 (int, int);
  69 static void OP_sI (int, int);
  70 static void OP_J (int, int);
  71 static void OP_SEG (int, int);
  72 static void OP_DIR (int, int);
  73 static void OP_OFF (int, int);
  74 static void OP_OFF64 (int, int);
  75 static void ptr_reg (int, int);
  76 static void OP_ESreg (int, int);
  77 static void OP_DSreg (int, int);
  78 static void OP_C (int, int);
  79 static void OP_D (int, int);
  80 static void OP_T (int, int);
  81 static void OP_R (int, int);
  82 static void OP_MMX (int, int);
  83 static void OP_XMM (int, int);
  84 static void OP_EM (int, int);
  85 static void OP_EX (int, int);
  86 static void OP_EMC (int,int);
  87 static void OP_MXC (int,int);
  88 static void OP_MS (int, int);
  89 static void OP_XS (int, int);
  90 static void OP_M (int, int);
  91 static void OP_VEX (int, int);
  92 static void OP_EX_Vex (int, int);
  93 static void OP_EX_VexW (int, int);
  94 static void OP_EX_VexImmW (int, int);
  95 static void OP_XMM_Vex (int, int);
  96 static void OP_XMM_VexW (int, int);
  97 static void OP_Rounding (int, int);
  98 static void OP_REG_VexI4 (int, int);
  99 static void PCLMUL_Fixup (int, int);
 100 static void VEXI4_Fixup (int, int);
 101 static void VZERO_Fixup (int, int);
 102 static void VCMP_Fixup (int, int);
 103 static void VPCMP_Fixup (int, int);
 104 static void OP_0f07 (int, int);
 105 static void OP_Monitor (int, int);
 106 static void OP_Mwait (int, int);
 107 static void NOP_Fixup1 (int, int);
 108 static void NOP_Fixup2 (int, int);
 109 static void OP_3DNowSuffix (int, int);
 110 static void CMP_Fixup (int, int);
 111 static void BadOp (void);
 112 static void REP_Fixup (int, int);
 113 static void BND_Fixup (int, int);
 114 static void HLE_Fixup1 (int, int);
 115 static void HLE_Fixup2 (int, int);
 116 static void HLE_Fixup3 (int, int);
 117 static void CMPXCHG8B_Fixup (int, int);
 118 static void XMM_Fixup (int, int);
 119 static void CRC32_Fixup (int, int);
 120 static void FXSAVE_Fixup (int, int);
 121 static void OP_LWPCB_E (int, int);
 122 static void OP_LWP_E (int, int);
 123 static void OP_Vex_2src_1 (int, int);
 124 static void OP_Vex_2src_2 (int, int);
 125
 126 static void MOVBE_Fixup (int, int);
 127
 128 static void OP_Mask (int, int);
 129
 130 struct dis_private {
 131   /* Points to first byte not fetched.  */
 132   bfd_byte *max_fetched;
 133   bfd_byte the_buffer[MAX_MNEM_SIZE];
 134   bfd_vma insn_start;
 135   int orig_sizeflag;
 136   jmp_buf bailout;
 137 };
 138
 139 enum address_mode
 140 {
 141   mode_16bit,
 142   mode_32bit,
 143   mode_64bit
 144 };
 145
 146 enum address_mode address_mode;
 147
 148 /* Flags for the prefixes for the current instruction.  See below.  */
 149 static int prefixes;
 150
 151 /* REX prefix the current instruction.  See below.  */
 152 static int rex;
 153 /* Bits of REX we've already used.  */
 154 static int rex_used;
 155 /* REX bits in original REX prefix ignored.  */
 156 static int rex_ignored;
 157 /* Mark parts used in the REX prefix.  When we are testing for
 158    empty prefix (for 8bit register REX extension), just mask it
 159    out.  Otherwise test for REX bit is excuse for existence of REX
 160    only in case value is nonzero.  */
 161 #define USED_REX(value)                                 \
 162   {                                                     \
 163     if (value)                                          \
 164       {                                                 \
 165         if ((rex & value))                              \
 166           rex_used |= (value) | REX_OPCODE;             \
 167       }                                                 \
 168     else                                                \
 169       rex_used |= REX_OPCODE;                           \
 170   }
 171
 172 /* Flags for prefixes which we somehow handled when printing the
 173    current instruction.  */
 174 static int used_prefixes;
 175
 176 /* Flags stored in PREFIXES.  */
 177 #define PREFIX_REPZ 1
 178 #define PREFIX_REPNZ 2
 179 #define PREFIX_LOCK 4
 180 #define PREFIX_CS 8
 181 #define PREFIX_SS 0x10
 182 #define PREFIX_DS 0x20
 183 #define PREFIX_ES 0x40
 184 #define PREFIX_FS 0x80
 185 #define PREFIX_GS 0x100
 186 #define PREFIX_DATA 0x200
 187 #define PREFIX_ADDR 0x400
 188 #define PREFIX_FWAIT 0x800
 189
 190 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 191    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 192    on error.  */
 193 #define FETCH_DATA(info, addr) \
 194   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 195    ? 1 : fetch_data ((info), (addr)))
 196
 197 static int
 198 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 199 {
 200   int status;
 201   struct dis_private *priv = (struct dis_private *) info->private_data;
 202   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 203
 204   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 205     status = (*info->read_memory_func) (start,
 206                                         priv->max_fetched,
 207                                         addr - priv->max_fetched,
 208                                         info);
 209   else
 210     status = -1;
 211   if (status != 0)
 212     {
 213       /* If we did manage to read at least one byte, then
 214          print_insn_i386 will do something sensible.  Otherwise, print
 215          an error.  We do that here because this is where we know
 216          STATUS.  */
 217       if (priv->max_fetched == priv->the_buffer)
 218         (*info->memory_error_func) (status, start, info);
 219       longjmp (priv->bailout, 1);
 220     }
 221   else
 222     priv->max_fetched = addr;
 223   return 1;
 224 }
 225
 226 #define XX { NULL, 0 }
 227 #define Bad_Opcode NULL, { { NULL, 0 } }
 228
 229 #define Eb { OP_E, b_mode }
 230 #define Ebnd { OP_E, bnd_mode }
 231 #define EbS { OP_E, b_swap_mode }
 232 #define Ev { OP_E, v_mode }
 233 #define Ev_bnd { OP_E, v_bnd_mode }
 234 #define EvS { OP_E, v_swap_mode }
 235 #define Ed { OP_E, d_mode }
 236 #define Edq { OP_E, dq_mode }
 237 #define Edqw { OP_E, dqw_mode }
 238 #define Edqb { OP_E, dqb_mode }
 239 #define Edqd { OP_E, dqd_mode }
 240 #define Eq { OP_E, q_mode }
 241 #define indirEv { OP_indirE, stack_v_mode }
 242 #define indirEp { OP_indirE, f_mode }
 243 #define stackEv { OP_E, stack_v_mode }
 244 #define Em { OP_E, m_mode }
 245 #define Ew { OP_E, w_mode }
 246 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 247 #define Ma { OP_M, a_mode }
 248 #define Mb { OP_M, b_mode }
 249 #define Md { OP_M, d_mode }
 250 #define Mo { OP_M, o_mode }
 251 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 252 #define Mq { OP_M, q_mode }
 253 #define Mx { OP_M, x_mode }
 254 #define Mxmm { OP_M, xmm_mode }
 255 #define Gb { OP_G, b_mode }
 256 #define Gbnd { OP_G, bnd_mode }
 257 #define Gv { OP_G, v_mode }
 258 #define Gd { OP_G, d_mode }
 259 #define Gdq { OP_G, dq_mode }
 260 #define Gm { OP_G, m_mode }
 261 #define Gw { OP_G, w_mode }
 262 #define Rd { OP_R, d_mode }
 263 #define Rdq { OP_R, dq_mode }
 264 #define Rm { OP_R, m_mode }
 265 #define Ib { OP_I, b_mode }
 266 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 267 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 268 #define Iv { OP_I, v_mode }
 269 #define sIv { OP_sI, v_mode }
 270 #define Iq { OP_I, q_mode }
 271 #define Iv64 { OP_I64, v_mode }
 272 #define Iw { OP_I, w_mode }
 273 #define I1 { OP_I, const_1_mode }
 274 #define Jb { OP_J, b_mode }
 275 #define Jv { OP_J, v_mode }
 276 #define Cm { OP_C, m_mode }
 277 #define Dm { OP_D, m_mode }
 278 #define Td { OP_T, d_mode }
 279 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 280
 281 #define RMeAX { OP_REG, eAX_reg }
 282 #define RMeBX { OP_REG, eBX_reg }
 283 #define RMeCX { OP_REG, eCX_reg }
 284 #define RMeDX { OP_REG, eDX_reg }
 285 #define RMeSP { OP_REG, eSP_reg }
 286 #define RMeBP { OP_REG, eBP_reg }
 287 #define RMeSI { OP_REG, eSI_reg }
 288 #define RMeDI { OP_REG, eDI_reg }
 289 #define RMrAX { OP_REG, rAX_reg }
 290 #define RMrBX { OP_REG, rBX_reg }
 291 #define RMrCX { OP_REG, rCX_reg }
 292 #define RMrDX { OP_REG, rDX_reg }
 293 #define RMrSP { OP_REG, rSP_reg }
 294 #define RMrBP { OP_REG, rBP_reg }
 295 #define RMrSI { OP_REG, rSI_reg }
 296 #define RMrDI { OP_REG, rDI_reg }
 297 #define RMAL { OP_REG, al_reg }
 298 #define RMCL { OP_REG, cl_reg }
 299 #define RMDL { OP_REG, dl_reg }
 300 #define RMBL { OP_REG, bl_reg }
 301 #define RMAH { OP_REG, ah_reg }
 302 #define RMCH { OP_REG, ch_reg }
 303 #define RMDH { OP_REG, dh_reg }
 304 #define RMBH { OP_REG, bh_reg }
 305 #define RMAX { OP_REG, ax_reg }
 306 #define RMDX { OP_REG, dx_reg }
 307
 308 #define eAX { OP_IMREG, eAX_reg }
 309 #define eBX { OP_IMREG, eBX_reg }
 310 #define eCX { OP_IMREG, eCX_reg }
 311 #define eDX { OP_IMREG, eDX_reg }
 312 #define eSP { OP_IMREG, eSP_reg }
 313 #define eBP { OP_IMREG, eBP_reg }
 314 #define eSI { OP_IMREG, eSI_reg }
 315 #define eDI { OP_IMREG, eDI_reg }
 316 #define AL { OP_IMREG, al_reg }
 317 #define CL { OP_IMREG, cl_reg }
 318 #define DL { OP_IMREG, dl_reg }
 319 #define BL { OP_IMREG, bl_reg }
 320 #define AH { OP_IMREG, ah_reg }
 321 #define CH { OP_IMREG, ch_reg }
 322 #define DH { OP_IMREG, dh_reg }
 323 #define BH { OP_IMREG, bh_reg }
 324 #define AX { OP_IMREG, ax_reg }
 325 #define DX { OP_IMREG, dx_reg }
 326 #define zAX { OP_IMREG, z_mode_ax_reg }
 327 #define indirDX { OP_IMREG, indir_dx_reg }
 328
 329 #define Sw { OP_SEG, w_mode }
 330 #define Sv { OP_SEG, v_mode }
 331 #define Ap { OP_DIR, 0 }
 332 #define Ob { OP_OFF64, b_mode }
 333 #define Ov { OP_OFF64, v_mode }
 334 #define Xb { OP_DSreg, eSI_reg }
 335 #define Xv { OP_DSreg, eSI_reg }
 336 #define Xz { OP_DSreg, eSI_reg }
 337 #define Yb { OP_ESreg, eDI_reg }
 338 #define Yv { OP_ESreg, eDI_reg }
 339 #define DSBX { OP_DSreg, eBX_reg }
 340
 341 #define es { OP_REG, es_reg }
 342 #define ss { OP_REG, ss_reg }
 343 #define cs { OP_REG, cs_reg }
 344 #define ds { OP_REG, ds_reg }
 345 #define fs { OP_REG, fs_reg }
 346 #define gs { OP_REG, gs_reg }
 347
 348 #define MX { OP_MMX, 0 }
 349 #define XM { OP_XMM, 0 }
 350 #define XMScalar { OP_XMM, scalar_mode }
 351 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 352 #define XMM { OP_XMM, xmm_mode }
 353 #define XMxmmq { OP_XMM, xmmq_mode }
 354 #define EM { OP_EM, v_mode }
 355 #define EMS { OP_EM, v_swap_mode }
 356 #define EMd { OP_EM, d_mode }
 357 #define EMx { OP_EM, x_mode }
 358 #define EXw { OP_EX, w_mode }
 359 #define EXd { OP_EX, d_mode }
 360 #define EXdScalar { OP_EX, d_scalar_mode }
 361 #define EXdS { OP_EX, d_swap_mode }
 362 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
 363 #define EXq { OP_EX, q_mode }
 364 #define EXqScalar { OP_EX, q_scalar_mode }
 365 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
 366 #define EXqS { OP_EX, q_swap_mode }
 367 #define EXx { OP_EX, x_mode }
 368 #define EXxS { OP_EX, x_swap_mode }
 369 #define EXxmm { OP_EX, xmm_mode }
 370 #define EXymm { OP_EX, ymm_mode }
 371 #define EXxmmq { OP_EX, xmmq_mode }
 372 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 373 #define EXxmm_mb { OP_EX, xmm_mb_mode }
 374 #define EXxmm_mw { OP_EX, xmm_mw_mode }
 375 #define EXxmm_md { OP_EX, xmm_md_mode }
 376 #define EXxmm_mq { OP_EX, xmm_mq_mode }
 377 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
 378 #define EXxmmdw { OP_EX, xmmdw_mode }
 379 #define EXxmmqd { OP_EX, xmmqd_mode }
 380 #define EXymmq { OP_EX, ymmq_mode }
 381 #define EXVexWdq { OP_EX, vex_w_dq_mode }
 382 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 383 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 384 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 385 #define MS { OP_MS, v_mode }
 386 #define XS { OP_XS, v_mode }
 387 #define EMCq { OP_EMC, q_mode }
 388 #define MXC { OP_MXC, 0 }
 389 #define OPSUF { OP_3DNowSuffix, 0 }
 390 #define CMP { CMP_Fixup, 0 }
 391 #define XMM0 { XMM_Fixup, 0 }
 392 #define FXSAVE { FXSAVE_Fixup, 0 }
 393 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
 394 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
 395
 396 #define Vex { OP_VEX, vex_mode }
 397 #define VexScalar { OP_VEX, vex_scalar_mode }
 398 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 399 #define Vex128 { OP_VEX, vex128_mode }
 400 #define Vex256 { OP_VEX, vex256_mode }
 401 #define VexGdq { OP_VEX, dq_mode }
 402 #define VexI4 { VEXI4_Fixup, 0}
 403 #define EXdVex { OP_EX_Vex, d_mode }
 404 #define EXdVexS { OP_EX_Vex, d_swap_mode }
 405 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
 406 #define EXqVex { OP_EX_Vex, q_mode }
 407 #define EXqVexS { OP_EX_Vex, q_swap_mode }
 408 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
 409 #define EXVexW { OP_EX_VexW, x_mode }
 410 #define EXdVexW { OP_EX_VexW, d_mode }
 411 #define EXqVexW { OP_EX_VexW, q_mode }
 412 #define EXVexImmW { OP_EX_VexImmW, x_mode }
 413 #define XMVex { OP_XMM_Vex, 0 }
 414 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
 415 #define XMVexW { OP_XMM_VexW, 0 }
 416 #define XMVexI4 { OP_REG_VexI4, x_mode }
 417 #define PCLMUL { PCLMUL_Fixup, 0 }
 418 #define VZERO { VZERO_Fixup, 0 }
 419 #define VCMP { VCMP_Fixup, 0 }
 420 #define VPCMP { VPCMP_Fixup, 0 }
 421
 422 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 423 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 424
 425 #define XMask { OP_Mask, mask_mode }
 426 #define MaskG { OP_G, mask_mode }
 427 #define MaskE { OP_E, mask_mode }
 428 #define MaskR { OP_R, mask_mode }
 429 #define MaskVex { OP_VEX, mask_mode }
 430
 431 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 432 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 433
 434 /* Used handle "rep" prefix for string instructions.  */
 435 #define Xbr { REP_Fixup, eSI_reg }
 436 #define Xvr { REP_Fixup, eSI_reg }
 437 #define Ybr { REP_Fixup, eDI_reg }
 438 #define Yvr { REP_Fixup, eDI_reg }
 439 #define Yzr { REP_Fixup, eDI_reg }
 440 #define indirDXr { REP_Fixup, indir_dx_reg }
 441 #define ALr { REP_Fixup, al_reg }
 442 #define eAXr { REP_Fixup, eAX_reg }
 443
 444 /* Used handle HLE prefix for lockable instructions.  */
 445 #define Ebh1 { HLE_Fixup1, b_mode }
 446 #define Evh1 { HLE_Fixup1, v_mode }
 447 #define Ebh2 { HLE_Fixup2, b_mode }
 448 #define Evh2 { HLE_Fixup2, v_mode }
 449 #define Ebh3 { HLE_Fixup3, b_mode }
 450 #define Evh3 { HLE_Fixup3, v_mode }
 451
 452 #define BND { BND_Fixup, 0 }
 453
 454 #define cond_jump_flag { NULL, cond_jump_mode }
 455 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 456
 457 /* bits in sizeflag */
 458 #define SUFFIX_ALWAYS 4
 459 #define AFLAG 2
 460 #define DFLAG 1
 461
 462 enum
 463 {
 464   /* byte operand */
 465   b_mode = 1,
 466   /* byte operand with operand swapped */
 467   b_swap_mode,
 468   /* byte operand, sign extend like 'T' suffix */
 469   b_T_mode,
 470   /* operand size depends on prefixes */
 471   v_mode,
 472   /* operand size depends on prefixes with operand swapped */
 473   v_swap_mode,
 474   /* word operand */
 475   w_mode,
 476   /* double word operand  */
 477   d_mode,
 478   /* double word operand with operand swapped */
 479   d_swap_mode,
 480   /* quad word operand */
 481   q_mode,
 482   /* quad word operand with operand swapped */
 483   q_swap_mode,
 484   /* ten-byte operand */
 485   t_mode,
 486   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 487      broadcast enabled.  */
 488   x_mode,
 489   /* Similar to x_mode, but with different EVEX mem shifts.  */
 490   evex_x_gscat_mode,
 491   /* Similar to x_mode, but with disabled broadcast.  */
 492   evex_x_nobcst_mode,
 493   /* Similar to x_mode, but with operands swapped and disabled broadcast
 494      in EVEX.  */
 495   x_swap_mode,
 496   /* 16-byte XMM operand */
 497   xmm_mode,
 498   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 499      memory operand (depending on vector length).  Broadcast isn't
 500      allowed.  */
 501   xmmq_mode,
 502   /* Same as xmmq_mode, but broadcast is allowed.  */
 503   evex_half_bcst_xmmq_mode,
 504   /* XMM register or byte memory operand */
 505   xmm_mb_mode,
 506   /* XMM register or word memory operand */
 507   xmm_mw_mode,
 508   /* XMM register or double word memory operand */
 509   xmm_md_mode,
 510   /* XMM register or quad word memory operand */
 511   xmm_mq_mode,
 512   /* XMM register or double/quad word memory operand, depending on
 513      VEX.W.  */
 514   xmm_mdq_mode,
 515   /* 16-byte XMM, word, double word or quad word operand.  */
 516   xmmdw_mode,
 517   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 518   xmmqd_mode,
 519   /* 32-byte YMM operand */
 520   ymm_mode,
 521   /* quad word, ymmword or zmmword memory operand.  */
 522   ymmq_mode,
 523   /* 32-byte YMM or 16-byte word operand */
 524   ymmxmm_mode,
 525   /* d_mode in 32bit, q_mode in 64bit mode.  */
 526   m_mode,
 527   /* pair of v_mode operands */
 528   a_mode,
 529   cond_jump_mode,
 530   loop_jcxz_mode,
 531   v_bnd_mode,
 532   /* operand size depends on REX prefixes.  */
 533   dq_mode,
 534   /* registers like dq_mode, memory like w_mode.  */
 535   dqw_mode,
 536   bnd_mode,
 537   /* 4- or 6-byte pointer operand */
 538   f_mode,
 539   const_1_mode,
 540   /* v_mode for stack-related opcodes.  */
 541   stack_v_mode,
 542   /* non-quad operand size depends on prefixes */
 543   z_mode,
 544   /* 16-byte operand */
 545   o_mode,
 546   /* registers like dq_mode, memory like b_mode.  */
 547   dqb_mode,
 548   /* registers like dq_mode, memory like d_mode.  */
 549   dqd_mode,
 550   /* normal vex mode */
 551   vex_mode,
 552   /* 128bit vex mode */
 553   vex128_mode,
 554   /* 256bit vex mode */
 555   vex256_mode,
 556   /* operand size depends on the VEX.W bit.  */
 557   vex_w_dq_mode,
 558
 559   /* Similar to vex_w_dq_mode, with VSIB dword indices.  */
 560   vex_vsib_d_w_dq_mode,
 561   /* Similar to vex_w_dq_mode, with VSIB qword indices.  */
 562   vex_vsib_q_w_dq_mode,
 563
 564   /* scalar, ignore vector length.  */
 565   scalar_mode,
 566   /* like d_mode, ignore vector length.  */
 567   d_scalar_mode,
 568   /* like d_swap_mode, ignore vector length.  */
 569   d_scalar_swap_mode,
 570   /* like q_mode, ignore vector length.  */
 571   q_scalar_mode,
 572   /* like q_swap_mode, ignore vector length.  */
 573   q_scalar_swap_mode,
 574   /* like vex_mode, ignore vector length.  */
 575   vex_scalar_mode,
 576   /* like vex_w_dq_mode, ignore vector length.  */
 577   vex_scalar_w_dq_mode,
 578
 579   /* Static rounding.  */
 580   evex_rounding_mode,
 581   /* Supress all exceptions.  */
 582   evex_sae_mode,
 583
 584   /* Mask register operand.  */
 585   mask_mode,
 586
 587   es_reg,
 588   cs_reg,
 589   ss_reg,
 590   ds_reg,
 591   fs_reg,
 592   gs_reg,
 593
 594   eAX_reg,
 595   eCX_reg,
 596   eDX_reg,
 597   eBX_reg,
 598   eSP_reg,
 599   eBP_reg,
 600   eSI_reg,
 601   eDI_reg,
 602
 603   al_reg,
 604   cl_reg,
 605   dl_reg,
 606   bl_reg,
 607   ah_reg,
 608   ch_reg,
 609   dh_reg,
 610   bh_reg,
 611
 612   ax_reg,
 613   cx_reg,
 614   dx_reg,
 615   bx_reg,
 616   sp_reg,
 617   bp_reg,
 618   si_reg,
 619   di_reg,
 620
 621   rAX_reg,
 622   rCX_reg,
 623   rDX_reg,
 624   rBX_reg,
 625   rSP_reg,
 626   rBP_reg,
 627   rSI_reg,
 628   rDI_reg,
 629
 630   z_mode_ax_reg,
 631   indir_dx_reg
 632 };
 633
 634 enum
 635 {
 636   FLOATCODE = 1,
 637   USE_REG_TABLE,
 638   USE_MOD_TABLE,
 639   USE_RM_TABLE,
 640   USE_PREFIX_TABLE,
 641   USE_X86_64_TABLE,
 642   USE_3BYTE_TABLE,
 643   USE_XOP_8F_TABLE,
 644   USE_VEX_C4_TABLE,
 645   USE_VEX_C5_TABLE,
 646   USE_VEX_LEN_TABLE,
 647   USE_VEX_W_TABLE,
 648   USE_EVEX_TABLE
 649 };
 650
 651 #define FLOAT                   NULL, { { NULL, FLOATCODE } }
 652
 653 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }
 654 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 655 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 656 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 657 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 658 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 659 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 660 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 661 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 662 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 663 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 664 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 665 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 666
 667 enum
 668 {
 669   REG_80 = 0,
 670   REG_81,
 671   REG_82,
 672   REG_8F,
 673   REG_C0,
 674   REG_C1,
 675   REG_C6,
 676   REG_C7,
 677   REG_D0,
 678   REG_D1,
 679   REG_D2,
 680   REG_D3,
 681   REG_F6,
 682   REG_F7,
 683   REG_FE,
 684   REG_FF,
 685   REG_0F00,
 686   REG_0F01,
 687   REG_0F0D,
 688   REG_0F18,
 689   REG_0F71,
 690   REG_0F72,
 691   REG_0F73,
 692   REG_0FA6,
 693   REG_0FA7,
 694   REG_0FAE,
 695   REG_0FBA,
 696   REG_0FC7,
 697   REG_VEX_0F71,
 698   REG_VEX_0F72,
 699   REG_VEX_0F73,
 700   REG_VEX_0FAE,
 701   REG_VEX_0F38F3,
 702   REG_XOP_LWPCB,
 703   REG_XOP_LWP,
 704   REG_XOP_TBM_01,
 705   REG_XOP_TBM_02,
 706
 707   REG_EVEX_0F72,
 708   REG_EVEX_0F73,
 709   REG_EVEX_0F38C6,
 710   REG_EVEX_0F38C7
 711 };
 712
 713 enum
 714 {
 715   MOD_8D = 0,
 716   MOD_C6_REG_7,
 717   MOD_C7_REG_7,
 718   MOD_0F01_REG_0,
 719   MOD_0F01_REG_1,
 720   MOD_0F01_REG_2,
 721   MOD_0F01_REG_3,
 722   MOD_0F01_REG_7,
 723   MOD_0F12_PREFIX_0,
 724   MOD_0F13,
 725   MOD_0F16_PREFIX_0,
 726   MOD_0F17,
 727   MOD_0F18_REG_0,
 728   MOD_0F18_REG_1,
 729   MOD_0F18_REG_2,
 730   MOD_0F18_REG_3,
 731   MOD_0F18_REG_4,
 732   MOD_0F18_REG_5,
 733   MOD_0F18_REG_6,
 734   MOD_0F18_REG_7,
 735   MOD_0F1A_PREFIX_0,
 736   MOD_0F1B_PREFIX_0,
 737   MOD_0F1B_PREFIX_1,
 738   MOD_0F20,
 739   MOD_0F21,
 740   MOD_0F22,
 741   MOD_0F23,
 742   MOD_0F24,
 743   MOD_0F26,
 744   MOD_0F2B_PREFIX_0,
 745   MOD_0F2B_PREFIX_1,
 746   MOD_0F2B_PREFIX_2,
 747   MOD_0F2B_PREFIX_3,
 748   MOD_0F51,
 749   MOD_0F71_REG_2,
 750   MOD_0F71_REG_4,
 751   MOD_0F71_REG_6,
 752   MOD_0F72_REG_2,
 753   MOD_0F72_REG_4,
 754   MOD_0F72_REG_6,
 755   MOD_0F73_REG_2,
 756   MOD_0F73_REG_3,
 757   MOD_0F73_REG_6,
 758   MOD_0F73_REG_7,
 759   MOD_0FAE_REG_0,
 760   MOD_0FAE_REG_1,
 761   MOD_0FAE_REG_2,
 762   MOD_0FAE_REG_3,
 763   MOD_0FAE_REG_4,
 764   MOD_0FAE_REG_5,
 765   MOD_0FAE_REG_6,
 766   MOD_0FAE_REG_7,
 767   MOD_0FB2,
 768   MOD_0FB4,
 769   MOD_0FB5,
 770   MOD_0FC7_REG_6,
 771   MOD_0FC7_REG_7,
 772   MOD_0FD7,
 773   MOD_0FE7_PREFIX_2,
 774   MOD_0FF0_PREFIX_3,
 775   MOD_0F382A_PREFIX_2,
 776   MOD_62_32BIT,
 777   MOD_C4_32BIT,
 778   MOD_C5_32BIT,
 779   MOD_VEX_0F12_PREFIX_0,
 780   MOD_VEX_0F13,
 781   MOD_VEX_0F16_PREFIX_0,
 782   MOD_VEX_0F17,
 783   MOD_VEX_0F2B,
 784   MOD_VEX_0F50,
 785   MOD_VEX_0F71_REG_2,
 786   MOD_VEX_0F71_REG_4,
 787   MOD_VEX_0F71_REG_6,
 788   MOD_VEX_0F72_REG_2,
 789   MOD_VEX_0F72_REG_4,
 790   MOD_VEX_0F72_REG_6,
 791   MOD_VEX_0F73_REG_2,
 792   MOD_VEX_0F73_REG_3,
 793   MOD_VEX_0F73_REG_6,
 794   MOD_VEX_0F73_REG_7,
 795   MOD_VEX_0FAE_REG_2,
 796   MOD_VEX_0FAE_REG_3,
 797   MOD_VEX_0FD7_PREFIX_2,
 798   MOD_VEX_0FE7_PREFIX_2,
 799   MOD_VEX_0FF0_PREFIX_3,
 800   MOD_VEX_0F381A_PREFIX_2,
 801   MOD_VEX_0F382A_PREFIX_2,
 802   MOD_VEX_0F382C_PREFIX_2,
 803   MOD_VEX_0F382D_PREFIX_2,
 804   MOD_VEX_0F382E_PREFIX_2,
 805   MOD_VEX_0F382F_PREFIX_2,
 806   MOD_VEX_0F385A_PREFIX_2,
 807   MOD_VEX_0F388C_PREFIX_2,
 808   MOD_VEX_0F388E_PREFIX_2,
 809
 810   MOD_EVEX_0F10_PREFIX_1,
 811   MOD_EVEX_0F10_PREFIX_3,
 812   MOD_EVEX_0F11_PREFIX_1,
 813   MOD_EVEX_0F11_PREFIX_3,
 814   MOD_EVEX_0F12_PREFIX_0,
 815   MOD_EVEX_0F16_PREFIX_0,
 816   MOD_EVEX_0F38C6_REG_1,
 817   MOD_EVEX_0F38C6_REG_2,
 818   MOD_EVEX_0F38C6_REG_5,
 819   MOD_EVEX_0F38C6_REG_6,
 820   MOD_EVEX_0F38C7_REG_1,
 821   MOD_EVEX_0F38C7_REG_2,
 822   MOD_EVEX_0F38C7_REG_5,
 823   MOD_EVEX_0F38C7_REG_6
 824 };
 825
 826 enum
 827 {
 828   RM_C6_REG_7 = 0,
 829   RM_C7_REG_7,
 830   RM_0F01_REG_0,
 831   RM_0F01_REG_1,
 832   RM_0F01_REG_2,
 833   RM_0F01_REG_3,
 834   RM_0F01_REG_7,
 835   RM_0FAE_REG_5,
 836   RM_0FAE_REG_6,
 837   RM_0FAE_REG_7
 838 };
 839
 840 enum
 841 {
 842   PREFIX_90 = 0,
 843   PREFIX_0F10,
 844   PREFIX_0F11,
 845   PREFIX_0F12,
 846   PREFIX_0F16,
 847   PREFIX_0F1A,
 848   PREFIX_0F1B,
 849   PREFIX_0F2A,
 850   PREFIX_0F2B,
 851   PREFIX_0F2C,
 852   PREFIX_0F2D,
 853   PREFIX_0F2E,
 854   PREFIX_0F2F,
 855   PREFIX_0F51,
 856   PREFIX_0F52,
 857   PREFIX_0F53,
 858   PREFIX_0F58,
 859   PREFIX_0F59,
 860   PREFIX_0F5A,
 861   PREFIX_0F5B,
 862   PREFIX_0F5C,
 863   PREFIX_0F5D,
 864   PREFIX_0F5E,
 865   PREFIX_0F5F,
 866   PREFIX_0F60,
 867   PREFIX_0F61,
 868   PREFIX_0F62,
 869   PREFIX_0F6C,
 870   PREFIX_0F6D,
 871   PREFIX_0F6F,
 872   PREFIX_0F70,
 873   PREFIX_0F73_REG_3,
 874   PREFIX_0F73_REG_7,
 875   PREFIX_0F78,
 876   PREFIX_0F79,
 877   PREFIX_0F7C,
 878   PREFIX_0F7D,
 879   PREFIX_0F7E,
 880   PREFIX_0F7F,
 881   PREFIX_0FAE_REG_0,
 882   PREFIX_0FAE_REG_1,
 883   PREFIX_0FAE_REG_2,
 884   PREFIX_0FAE_REG_3,
 885   PREFIX_0FB8,
 886   PREFIX_0FBC,
 887   PREFIX_0FBD,
 888   PREFIX_0FC2,
 889   PREFIX_0FC3,
 890   PREFIX_0FC7_REG_6,
 891   PREFIX_0FD0,
 892   PREFIX_0FD6,
 893   PREFIX_0FE6,
 894   PREFIX_0FE7,
 895   PREFIX_0FF0,
 896   PREFIX_0FF7,
 897   PREFIX_0F3810,
 898   PREFIX_0F3814,
 899   PREFIX_0F3815,
 900   PREFIX_0F3817,
 901   PREFIX_0F3820,
 902   PREFIX_0F3821,
 903   PREFIX_0F3822,
 904   PREFIX_0F3823,
 905   PREFIX_0F3824,
 906   PREFIX_0F3825,
 907   PREFIX_0F3828,
 908   PREFIX_0F3829,
 909   PREFIX_0F382A,
 910   PREFIX_0F382B,
 911   PREFIX_0F3830,
 912   PREFIX_0F3831,
 913   PREFIX_0F3832,
 914   PREFIX_0F3833,
 915   PREFIX_0F3834,
 916   PREFIX_0F3835,
 917   PREFIX_0F3837,
 918   PREFIX_0F3838,
 919   PREFIX_0F3839,
 920   PREFIX_0F383A,
 921   PREFIX_0F383B,
 922   PREFIX_0F383C,
 923   PREFIX_0F383D,
 924   PREFIX_0F383E,
 925   PREFIX_0F383F,
 926   PREFIX_0F3840,
 927   PREFIX_0F3841,
 928   PREFIX_0F3880,
 929   PREFIX_0F3881,
 930   PREFIX_0F3882,
 931   PREFIX_0F38C8,
 932   PREFIX_0F38C9,
 933   PREFIX_0F38CA,
 934   PREFIX_0F38CB,
 935   PREFIX_0F38CC,
 936   PREFIX_0F38CD,
 937   PREFIX_0F38DB,
 938   PREFIX_0F38DC,
 939   PREFIX_0F38DD,
 940   PREFIX_0F38DE,
 941   PREFIX_0F38DF,
 942   PREFIX_0F38F0,
 943   PREFIX_0F38F1,
 944   PREFIX_0F38F6,
 945   PREFIX_0F3A08,
 946   PREFIX_0F3A09,
 947   PREFIX_0F3A0A,
 948   PREFIX_0F3A0B,
 949   PREFIX_0F3A0C,
 950   PREFIX_0F3A0D,
 951   PREFIX_0F3A0E,
 952   PREFIX_0F3A14,
 953   PREFIX_0F3A15,
 954   PREFIX_0F3A16,
 955   PREFIX_0F3A17,
 956   PREFIX_0F3A20,
 957   PREFIX_0F3A21,
 958   PREFIX_0F3A22,
 959   PREFIX_0F3A40,
 960   PREFIX_0F3A41,
 961   PREFIX_0F3A42,
 962   PREFIX_0F3A44,
 963   PREFIX_0F3A60,
 964   PREFIX_0F3A61,
 965   PREFIX_0F3A62,
 966   PREFIX_0F3A63,
 967   PREFIX_0F3ACC,
 968   PREFIX_0F3ADF,
 969   PREFIX_VEX_0F10,
 970   PREFIX_VEX_0F11,
 971   PREFIX_VEX_0F12,
 972   PREFIX_VEX_0F16,
 973   PREFIX_VEX_0F2A,
 974   PREFIX_VEX_0F2C,
 975   PREFIX_VEX_0F2D,
 976   PREFIX_VEX_0F2E,
 977   PREFIX_VEX_0F2F,
 978   PREFIX_VEX_0F41,
 979   PREFIX_VEX_0F42,
 980   PREFIX_VEX_0F44,
 981   PREFIX_VEX_0F45,
 982   PREFIX_VEX_0F46,
 983   PREFIX_VEX_0F47,
 984   PREFIX_VEX_0F4B,
 985   PREFIX_VEX_0F51,
 986   PREFIX_VEX_0F52,
 987   PREFIX_VEX_0F53,
 988   PREFIX_VEX_0F58,
 989   PREFIX_VEX_0F59,
 990   PREFIX_VEX_0F5A,
 991   PREFIX_VEX_0F5B,
 992   PREFIX_VEX_0F5C,
 993   PREFIX_VEX_0F5D,
 994   PREFIX_VEX_0F5E,
 995   PREFIX_VEX_0F5F,
 996   PREFIX_VEX_0F60,
 997   PREFIX_VEX_0F61,
 998   PREFIX_VEX_0F62,
 999   PREFIX_VEX_0F63,
1000   PREFIX_VEX_0F64,
1001   PREFIX_VEX_0F65,
1002   PREFIX_VEX_0F66,
1003   PREFIX_VEX_0F67,
1004   PREFIX_VEX_0F68,
1005   PREFIX_VEX_0F69,
1006   PREFIX_VEX_0F6A,
1007   PREFIX_VEX_0F6B,
1008   PREFIX_VEX_0F6C,
1009   PREFIX_VEX_0F6D,
1010   PREFIX_VEX_0F6E,
1011   PREFIX_VEX_0F6F,
1012   PREFIX_VEX_0F70,
1013   PREFIX_VEX_0F71_REG_2,
1014   PREFIX_VEX_0F71_REG_4,
1015   PREFIX_VEX_0F71_REG_6,
1016   PREFIX_VEX_0F72_REG_2,
1017   PREFIX_VEX_0F72_REG_4,
1018   PREFIX_VEX_0F72_REG_6,
1019   PREFIX_VEX_0F73_REG_2,
1020   PREFIX_VEX_0F73_REG_3,
1021   PREFIX_VEX_0F73_REG_6,
1022   PREFIX_VEX_0F73_REG_7,
1023   PREFIX_VEX_0F74,
1024   PREFIX_VEX_0F75,
1025   PREFIX_VEX_0F76,
1026   PREFIX_VEX_0F77,
1027   PREFIX_VEX_0F7C,
1028   PREFIX_VEX_0F7D,
1029   PREFIX_VEX_0F7E,
1030   PREFIX_VEX_0F7F,
1031   PREFIX_VEX_0F90,
1032   PREFIX_VEX_0F91,
1033   PREFIX_VEX_0F92,
1034   PREFIX_VEX_0F93,
1035   PREFIX_VEX_0F98,
1036   PREFIX_VEX_0FC2,
1037   PREFIX_VEX_0FC4,
1038   PREFIX_VEX_0FC5,
1039   PREFIX_VEX_0FD0,
1040   PREFIX_VEX_0FD1,
1041   PREFIX_VEX_0FD2,
1042   PREFIX_VEX_0FD3,
1043   PREFIX_VEX_0FD4,
1044   PREFIX_VEX_0FD5,
1045   PREFIX_VEX_0FD6,
1046   PREFIX_VEX_0FD7,
1047   PREFIX_VEX_0FD8,
1048   PREFIX_VEX_0FD9,
1049   PREFIX_VEX_0FDA,
1050   PREFIX_VEX_0FDB,
1051   PREFIX_VEX_0FDC,
1052   PREFIX_VEX_0FDD,
1053   PREFIX_VEX_0FDE,
1054   PREFIX_VEX_0FDF,
1055   PREFIX_VEX_0FE0,
1056   PREFIX_VEX_0FE1,
1057   PREFIX_VEX_0FE2,
1058   PREFIX_VEX_0FE3,
1059   PREFIX_VEX_0FE4,
1060   PREFIX_VEX_0FE5,
1061   PREFIX_VEX_0FE6,
1062   PREFIX_VEX_0FE7,
1063   PREFIX_VEX_0FE8,
1064   PREFIX_VEX_0FE9,
1065   PREFIX_VEX_0FEA,
1066   PREFIX_VEX_0FEB,
1067   PREFIX_VEX_0FEC,
1068   PREFIX_VEX_0FED,
1069   PREFIX_VEX_0FEE,
1070   PREFIX_VEX_0FEF,
1071   PREFIX_VEX_0FF0,
1072   PREFIX_VEX_0FF1,
1073   PREFIX_VEX_0FF2,
1074   PREFIX_VEX_0FF3,
1075   PREFIX_VEX_0FF4,
1076   PREFIX_VEX_0FF5,
1077   PREFIX_VEX_0FF6,
1078   PREFIX_VEX_0FF7,
1079   PREFIX_VEX_0FF8,
1080   PREFIX_VEX_0FF9,
1081   PREFIX_VEX_0FFA,
1082   PREFIX_VEX_0FFB,
1083   PREFIX_VEX_0FFC,
1084   PREFIX_VEX_0FFD,
1085   PREFIX_VEX_0FFE,
1086   PREFIX_VEX_0F3800,
1087   PREFIX_VEX_0F3801,
1088   PREFIX_VEX_0F3802,
1089   PREFIX_VEX_0F3803,
1090   PREFIX_VEX_0F3804,
1091   PREFIX_VEX_0F3805,
1092   PREFIX_VEX_0F3806,
1093   PREFIX_VEX_0F3807,
1094   PREFIX_VEX_0F3808,
1095   PREFIX_VEX_0F3809,
1096   PREFIX_VEX_0F380A,
1097   PREFIX_VEX_0F380B,
1098   PREFIX_VEX_0F380C,
1099   PREFIX_VEX_0F380D,
1100   PREFIX_VEX_0F380E,
1101   PREFIX_VEX_0F380F,
1102   PREFIX_VEX_0F3813,
1103   PREFIX_VEX_0F3816,
1104   PREFIX_VEX_0F3817,
1105   PREFIX_VEX_0F3818,
1106   PREFIX_VEX_0F3819,
1107   PREFIX_VEX_0F381A,
1108   PREFIX_VEX_0F381C,
1109   PREFIX_VEX_0F381D,
1110   PREFIX_VEX_0F381E,
1111   PREFIX_VEX_0F3820,
1112   PREFIX_VEX_0F3821,
1113   PREFIX_VEX_0F3822,
1114   PREFIX_VEX_0F3823,
1115   PREFIX_VEX_0F3824,
1116   PREFIX_VEX_0F3825,
1117   PREFIX_VEX_0F3828,
1118   PREFIX_VEX_0F3829,
1119   PREFIX_VEX_0F382A,
1120   PREFIX_VEX_0F382B,
1121   PREFIX_VEX_0F382C,
1122   PREFIX_VEX_0F382D,
1123   PREFIX_VEX_0F382E,
1124   PREFIX_VEX_0F382F,
1125   PREFIX_VEX_0F3830,
1126   PREFIX_VEX_0F3831,
1127   PREFIX_VEX_0F3832,
1128   PREFIX_VEX_0F3833,
1129   PREFIX_VEX_0F3834,
1130   PREFIX_VEX_0F3835,
1131   PREFIX_VEX_0F3836,
1132   PREFIX_VEX_0F3837,
1133   PREFIX_VEX_0F3838,
1134   PREFIX_VEX_0F3839,
1135   PREFIX_VEX_0F383A,
1136   PREFIX_VEX_0F383B,
1137   PREFIX_VEX_0F383C,
1138   PREFIX_VEX_0F383D,
1139   PREFIX_VEX_0F383E,
1140   PREFIX_VEX_0F383F,
1141   PREFIX_VEX_0F3840,
1142   PREFIX_VEX_0F3841,
1143   PREFIX_VEX_0F3845,
1144   PREFIX_VEX_0F3846,
1145   PREFIX_VEX_0F3847,
1146   PREFIX_VEX_0F3858,
1147   PREFIX_VEX_0F3859,
1148   PREFIX_VEX_0F385A,
1149   PREFIX_VEX_0F3878,
1150   PREFIX_VEX_0F3879,
1151   PREFIX_VEX_0F388C,
1152   PREFIX_VEX_0F388E,
1153   PREFIX_VEX_0F3890,
1154   PREFIX_VEX_0F3891,
1155   PREFIX_VEX_0F3892,
1156   PREFIX_VEX_0F3893,
1157   PREFIX_VEX_0F3896,
1158   PREFIX_VEX_0F3897,
1159   PREFIX_VEX_0F3898,
1160   PREFIX_VEX_0F3899,
1161   PREFIX_VEX_0F389A,
1162   PREFIX_VEX_0F389B,
1163   PREFIX_VEX_0F389C,
1164   PREFIX_VEX_0F389D,
1165   PREFIX_VEX_0F389E,
1166   PREFIX_VEX_0F389F,
1167   PREFIX_VEX_0F38A6,
1168   PREFIX_VEX_0F38A7,
1169   PREFIX_VEX_0F38A8,
1170   PREFIX_VEX_0F38A9,
1171   PREFIX_VEX_0F38AA,
1172   PREFIX_VEX_0F38AB,
1173   PREFIX_VEX_0F38AC,
1174   PREFIX_VEX_0F38AD,
1175   PREFIX_VEX_0F38AE,
1176   PREFIX_VEX_0F38AF,
1177   PREFIX_VEX_0F38B6,
1178   PREFIX_VEX_0F38B7,
1179   PREFIX_VEX_0F38B8,
1180   PREFIX_VEX_0F38B9,
1181   PREFIX_VEX_0F38BA,
1182   PREFIX_VEX_0F38BB,
1183   PREFIX_VEX_0F38BC,
1184   PREFIX_VEX_0F38BD,
1185   PREFIX_VEX_0F38BE,
1186   PREFIX_VEX_0F38BF,
1187   PREFIX_VEX_0F38DB,
1188   PREFIX_VEX_0F38DC,
1189   PREFIX_VEX_0F38DD,
1190   PREFIX_VEX_0F38DE,
1191   PREFIX_VEX_0F38DF,
1192   PREFIX_VEX_0F38F2,
1193   PREFIX_VEX_0F38F3_REG_1,
1194   PREFIX_VEX_0F38F3_REG_2,
1195   PREFIX_VEX_0F38F3_REG_3,
1196   PREFIX_VEX_0F38F5,
1197   PREFIX_VEX_0F38F6,
1198   PREFIX_VEX_0F38F7,
1199   PREFIX_VEX_0F3A00,
1200   PREFIX_VEX_0F3A01,
1201   PREFIX_VEX_0F3A02,
1202   PREFIX_VEX_0F3A04,
1203   PREFIX_VEX_0F3A05,
1204   PREFIX_VEX_0F3A06,
1205   PREFIX_VEX_0F3A08,
1206   PREFIX_VEX_0F3A09,
1207   PREFIX_VEX_0F3A0A,
1208   PREFIX_VEX_0F3A0B,
1209   PREFIX_VEX_0F3A0C,
1210   PREFIX_VEX_0F3A0D,
1211   PREFIX_VEX_0F3A0E,
1212   PREFIX_VEX_0F3A0F,
1213   PREFIX_VEX_0F3A14,
1214   PREFIX_VEX_0F3A15,
1215   PREFIX_VEX_0F3A16,
1216   PREFIX_VEX_0F3A17,
1217   PREFIX_VEX_0F3A18,
1218   PREFIX_VEX_0F3A19,
1219   PREFIX_VEX_0F3A1D,
1220   PREFIX_VEX_0F3A20,
1221   PREFIX_VEX_0F3A21,
1222   PREFIX_VEX_0F3A22,
1223   PREFIX_VEX_0F3A30,
1224   PREFIX_VEX_0F3A32,
1225   PREFIX_VEX_0F3A38,
1226   PREFIX_VEX_0F3A39,
1227   PREFIX_VEX_0F3A40,
1228   PREFIX_VEX_0F3A41,
1229   PREFIX_VEX_0F3A42,
1230   PREFIX_VEX_0F3A44,
1231   PREFIX_VEX_0F3A46,
1232   PREFIX_VEX_0F3A48,
1233   PREFIX_VEX_0F3A49,
1234   PREFIX_VEX_0F3A4A,
1235   PREFIX_VEX_0F3A4B,
1236   PREFIX_VEX_0F3A4C,
1237   PREFIX_VEX_0F3A5C,
1238   PREFIX_VEX_0F3A5D,
1239   PREFIX_VEX_0F3A5E,
1240   PREFIX_VEX_0F3A5F,
1241   PREFIX_VEX_0F3A60,
1242   PREFIX_VEX_0F3A61,
1243   PREFIX_VEX_0F3A62,
1244   PREFIX_VEX_0F3A63,
1245   PREFIX_VEX_0F3A68,
1246   PREFIX_VEX_0F3A69,
1247   PREFIX_VEX_0F3A6A,
1248   PREFIX_VEX_0F3A6B,
1249   PREFIX_VEX_0F3A6C,
1250   PREFIX_VEX_0F3A6D,
1251   PREFIX_VEX_0F3A6E,
1252   PREFIX_VEX_0F3A6F,
1253   PREFIX_VEX_0F3A78,
1254   PREFIX_VEX_0F3A79,
1255   PREFIX_VEX_0F3A7A,
1256   PREFIX_VEX_0F3A7B,
1257   PREFIX_VEX_0F3A7C,
1258   PREFIX_VEX_0F3A7D,
1259   PREFIX_VEX_0F3A7E,
1260   PREFIX_VEX_0F3A7F,
1261   PREFIX_VEX_0F3ADF,
1262   PREFIX_VEX_0F3AF0,
1263
1264   PREFIX_EVEX_0F10,
1265   PREFIX_EVEX_0F11,
1266   PREFIX_EVEX_0F12,
1267   PREFIX_EVEX_0F13,
1268   PREFIX_EVEX_0F14,
1269   PREFIX_EVEX_0F15,
1270   PREFIX_EVEX_0F16,
1271   PREFIX_EVEX_0F17,
1272   PREFIX_EVEX_0F28,
1273   PREFIX_EVEX_0F29,
1274   PREFIX_EVEX_0F2A,
1275   PREFIX_EVEX_0F2B,
1276   PREFIX_EVEX_0F2C,
1277   PREFIX_EVEX_0F2D,
1278   PREFIX_EVEX_0F2E,
1279   PREFIX_EVEX_0F2F,
1280   PREFIX_EVEX_0F51,
1281   PREFIX_EVEX_0F58,
1282   PREFIX_EVEX_0F59,
1283   PREFIX_EVEX_0F5A,
1284   PREFIX_EVEX_0F5B,
1285   PREFIX_EVEX_0F5C,
1286   PREFIX_EVEX_0F5D,
1287   PREFIX_EVEX_0F5E,
1288   PREFIX_EVEX_0F5F,
1289   PREFIX_EVEX_0F62,
1290   PREFIX_EVEX_0F66,
1291   PREFIX_EVEX_0F6A,
1292   PREFIX_EVEX_0F6C,
1293   PREFIX_EVEX_0F6D,
1294   PREFIX_EVEX_0F6E,
1295   PREFIX_EVEX_0F6F,
1296   PREFIX_EVEX_0F70,
1297   PREFIX_EVEX_0F72_REG_0,
1298   PREFIX_EVEX_0F72_REG_1,
1299   PREFIX_EVEX_0F72_REG_2,
1300   PREFIX_EVEX_0F72_REG_4,
1301   PREFIX_EVEX_0F72_REG_6,
1302   PREFIX_EVEX_0F73_REG_2,
1303   PREFIX_EVEX_0F73_REG_6,
1304   PREFIX_EVEX_0F76,
1305   PREFIX_EVEX_0F78,
1306   PREFIX_EVEX_0F79,
1307   PREFIX_EVEX_0F7A,
1308   PREFIX_EVEX_0F7B,
1309   PREFIX_EVEX_0F7E,
1310   PREFIX_EVEX_0F7F,
1311   PREFIX_EVEX_0FC2,
1312   PREFIX_EVEX_0FC6,
1313   PREFIX_EVEX_0FD2,
1314   PREFIX_EVEX_0FD3,
1315   PREFIX_EVEX_0FD4,
1316   PREFIX_EVEX_0FD6,
1317   PREFIX_EVEX_0FDB,
1318   PREFIX_EVEX_0FDF,
1319   PREFIX_EVEX_0FE2,
1320   PREFIX_EVEX_0FE6,
1321   PREFIX_EVEX_0FE7,
1322   PREFIX_EVEX_0FEB,
1323   PREFIX_EVEX_0FEF,
1324   PREFIX_EVEX_0FF2,
1325   PREFIX_EVEX_0FF3,
1326   PREFIX_EVEX_0FF4,
1327   PREFIX_EVEX_0FFA,
1328   PREFIX_EVEX_0FFB,
1329   PREFIX_EVEX_0FFE,
1330   PREFIX_EVEX_0F380C,
1331   PREFIX_EVEX_0F380D,
1332   PREFIX_EVEX_0F3811,
1333   PREFIX_EVEX_0F3812,
1334   PREFIX_EVEX_0F3813,
1335   PREFIX_EVEX_0F3814,
1336   PREFIX_EVEX_0F3815,
1337   PREFIX_EVEX_0F3816,
1338   PREFIX_EVEX_0F3818,
1339   PREFIX_EVEX_0F3819,
1340   PREFIX_EVEX_0F381A,
1341   PREFIX_EVEX_0F381B,
1342   PREFIX_EVEX_0F381E,
1343   PREFIX_EVEX_0F381F,
1344   PREFIX_EVEX_0F3821,
1345   PREFIX_EVEX_0F3822,
1346   PREFIX_EVEX_0F3823,
1347   PREFIX_EVEX_0F3824,
1348   PREFIX_EVEX_0F3825,
1349   PREFIX_EVEX_0F3827,
1350   PREFIX_EVEX_0F3828,
1351   PREFIX_EVEX_0F3829,
1352   PREFIX_EVEX_0F382A,
1353   PREFIX_EVEX_0F382C,
1354   PREFIX_EVEX_0F382D,
1355   PREFIX_EVEX_0F3831,
1356   PREFIX_EVEX_0F3832,
1357   PREFIX_EVEX_0F3833,
1358   PREFIX_EVEX_0F3834,
1359   PREFIX_EVEX_0F3835,
1360   PREFIX_EVEX_0F3836,
1361   PREFIX_EVEX_0F3837,
1362   PREFIX_EVEX_0F3839,
1363   PREFIX_EVEX_0F383A,
1364   PREFIX_EVEX_0F383B,
1365   PREFIX_EVEX_0F383D,
1366   PREFIX_EVEX_0F383F,
1367   PREFIX_EVEX_0F3840,
1368   PREFIX_EVEX_0F3842,
1369   PREFIX_EVEX_0F3843,
1370   PREFIX_EVEX_0F3844,
1371   PREFIX_EVEX_0F3845,
1372   PREFIX_EVEX_0F3846,
1373   PREFIX_EVEX_0F3847,
1374   PREFIX_EVEX_0F384C,
1375   PREFIX_EVEX_0F384D,
1376   PREFIX_EVEX_0F384E,
1377   PREFIX_EVEX_0F384F,
1378   PREFIX_EVEX_0F3858,
1379   PREFIX_EVEX_0F3859,
1380   PREFIX_EVEX_0F385A,
1381   PREFIX_EVEX_0F385B,
1382   PREFIX_EVEX_0F3864,
1383   PREFIX_EVEX_0F3865,
1384   PREFIX_EVEX_0F3876,
1385   PREFIX_EVEX_0F3877,
1386   PREFIX_EVEX_0F387C,
1387   PREFIX_EVEX_0F387E,
1388   PREFIX_EVEX_0F387F,
1389   PREFIX_EVEX_0F3888,
1390   PREFIX_EVEX_0F3889,
1391   PREFIX_EVEX_0F388A,
1392   PREFIX_EVEX_0F388B,
1393   PREFIX_EVEX_0F3890,
1394   PREFIX_EVEX_0F3891,
1395   PREFIX_EVEX_0F3892,
1396   PREFIX_EVEX_0F3893,
1397   PREFIX_EVEX_0F3896,
1398   PREFIX_EVEX_0F3897,
1399   PREFIX_EVEX_0F3898,
1400   PREFIX_EVEX_0F3899,
1401   PREFIX_EVEX_0F389A,
1402   PREFIX_EVEX_0F389B,
1403   PREFIX_EVEX_0F389C,
1404   PREFIX_EVEX_0F389D,
1405   PREFIX_EVEX_0F389E,
1406   PREFIX_EVEX_0F389F,
1407   PREFIX_EVEX_0F38A0,
1408   PREFIX_EVEX_0F38A1,
1409   PREFIX_EVEX_0F38A2,
1410   PREFIX_EVEX_0F38A3,
1411   PREFIX_EVEX_0F38A6,
1412   PREFIX_EVEX_0F38A7,
1413   PREFIX_EVEX_0F38A8,
1414   PREFIX_EVEX_0F38A9,
1415   PREFIX_EVEX_0F38AA,
1416   PREFIX_EVEX_0F38AB,
1417   PREFIX_EVEX_0F38AC,
1418   PREFIX_EVEX_0F38AD,
1419   PREFIX_EVEX_0F38AE,
1420   PREFIX_EVEX_0F38AF,
1421   PREFIX_EVEX_0F38B6,
1422   PREFIX_EVEX_0F38B7,
1423   PREFIX_EVEX_0F38B8,
1424   PREFIX_EVEX_0F38B9,
1425   PREFIX_EVEX_0F38BA,
1426   PREFIX_EVEX_0F38BB,
1427   PREFIX_EVEX_0F38BC,
1428   PREFIX_EVEX_0F38BD,
1429   PREFIX_EVEX_0F38BE,
1430   PREFIX_EVEX_0F38BF,
1431   PREFIX_EVEX_0F38C4,
1432   PREFIX_EVEX_0F38C6_REG_1,
1433   PREFIX_EVEX_0F38C6_REG_2,
1434   PREFIX_EVEX_0F38C6_REG_5,
1435   PREFIX_EVEX_0F38C6_REG_6,
1436   PREFIX_EVEX_0F38C7_REG_1,
1437   PREFIX_EVEX_0F38C7_REG_2,
1438   PREFIX_EVEX_0F38C7_REG_5,
1439   PREFIX_EVEX_0F38C7_REG_6,
1440   PREFIX_EVEX_0F38C8,
1441   PREFIX_EVEX_0F38CA,
1442   PREFIX_EVEX_0F38CB,
1443   PREFIX_EVEX_0F38CC,
1444   PREFIX_EVEX_0F38CD,
1445
1446   PREFIX_EVEX_0F3A00,
1447   PREFIX_EVEX_0F3A01,
1448   PREFIX_EVEX_0F3A03,
1449   PREFIX_EVEX_0F3A04,
1450   PREFIX_EVEX_0F3A05,
1451   PREFIX_EVEX_0F3A08,
1452   PREFIX_EVEX_0F3A09,
1453   PREFIX_EVEX_0F3A0A,
1454   PREFIX_EVEX_0F3A0B,
1455   PREFIX_EVEX_0F3A17,
1456   PREFIX_EVEX_0F3A18,
1457   PREFIX_EVEX_0F3A19,
1458   PREFIX_EVEX_0F3A1A,
1459   PREFIX_EVEX_0F3A1B,
1460   PREFIX_EVEX_0F3A1D,
1461   PREFIX_EVEX_0F3A1E,
1462   PREFIX_EVEX_0F3A1F,
1463   PREFIX_EVEX_0F3A21,
1464   PREFIX_EVEX_0F3A23,
1465   PREFIX_EVEX_0F3A25,
1466   PREFIX_EVEX_0F3A26,
1467   PREFIX_EVEX_0F3A27,
1468   PREFIX_EVEX_0F3A38,
1469   PREFIX_EVEX_0F3A39,
1470   PREFIX_EVEX_0F3A3A,
1471   PREFIX_EVEX_0F3A3B,
1472   PREFIX_EVEX_0F3A43,
1473   PREFIX_EVEX_0F3A54,
1474   PREFIX_EVEX_0F3A55,
1475 };
1476
1477 enum
1478 {
1479   X86_64_06 = 0,
1480   X86_64_07,
1481   X86_64_0D,
1482   X86_64_16,
1483   X86_64_17,
1484   X86_64_1E,
1485   X86_64_1F,
1486   X86_64_27,
1487   X86_64_2F,
1488   X86_64_37,
1489   X86_64_3F,
1490   X86_64_60,
1491   X86_64_61,
1492   X86_64_62,
1493   X86_64_63,
1494   X86_64_6D,
1495   X86_64_6F,
1496   X86_64_9A,
1497   X86_64_C4,
1498   X86_64_C5,
1499   X86_64_CE,
1500   X86_64_D4,
1501   X86_64_D5,
1502   X86_64_EA,
1503   X86_64_0F01_REG_0,
1504   X86_64_0F01_REG_1,
1505   X86_64_0F01_REG_2,
1506   X86_64_0F01_REG_3
1507 };
1508
1509 enum
1510 {
1511   THREE_BYTE_0F38 = 0,
1512   THREE_BYTE_0F3A,
1513   THREE_BYTE_0F7A
1514 };
1515
1516 enum
1517 {
1518   XOP_08 = 0,
1519   XOP_09,
1520   XOP_0A
1521 };
1522
1523 enum
1524 {
1525   VEX_0F = 0,
1526   VEX_0F38,
1527   VEX_0F3A
1528 };
1529
1530 enum
1531 {
1532   EVEX_0F = 0,
1533   EVEX_0F38,
1534   EVEX_0F3A
1535 };
1536
1537 enum
1538 {
1539   VEX_LEN_0F10_P_1 = 0,
1540   VEX_LEN_0F10_P_3,
1541   VEX_LEN_0F11_P_1,
1542   VEX_LEN_0F11_P_3,
1543   VEX_LEN_0F12_P_0_M_0,
1544   VEX_LEN_0F12_P_0_M_1,
1545   VEX_LEN_0F12_P_2,
1546   VEX_LEN_0F13_M_0,
1547   VEX_LEN_0F16_P_0_M_0,
1548   VEX_LEN_0F16_P_0_M_1,
1549   VEX_LEN_0F16_P_2,
1550   VEX_LEN_0F17_M_0,
1551   VEX_LEN_0F2A_P_1,
1552   VEX_LEN_0F2A_P_3,
1553   VEX_LEN_0F2C_P_1,
1554   VEX_LEN_0F2C_P_3,
1555   VEX_LEN_0F2D_P_1,
1556   VEX_LEN_0F2D_P_3,
1557   VEX_LEN_0F2E_P_0,
1558   VEX_LEN_0F2E_P_2,
1559   VEX_LEN_0F2F_P_0,
1560   VEX_LEN_0F2F_P_2,
1561   VEX_LEN_0F41_P_0,
1562   VEX_LEN_0F42_P_0,
1563   VEX_LEN_0F44_P_0,
1564   VEX_LEN_0F45_P_0,
1565   VEX_LEN_0F46_P_0,
1566   VEX_LEN_0F47_P_0,
1567   VEX_LEN_0F4B_P_2,
1568   VEX_LEN_0F51_P_1,
1569   VEX_LEN_0F51_P_3,
1570   VEX_LEN_0F52_P_1,
1571   VEX_LEN_0F53_P_1,
1572   VEX_LEN_0F58_P_1,
1573   VEX_LEN_0F58_P_3,
1574   VEX_LEN_0F59_P_1,
1575   VEX_LEN_0F59_P_3,
1576   VEX_LEN_0F5A_P_1,
1577   VEX_LEN_0F5A_P_3,
1578   VEX_LEN_0F5C_P_1,
1579   VEX_LEN_0F5C_P_3,
1580   VEX_LEN_0F5D_P_1,
1581   VEX_LEN_0F5D_P_3,
1582   VEX_LEN_0F5E_P_1,
1583   VEX_LEN_0F5E_P_3,
1584   VEX_LEN_0F5F_P_1,
1585   VEX_LEN_0F5F_P_3,
1586   VEX_LEN_0F6E_P_2,
1587   VEX_LEN_0F7E_P_1,
1588   VEX_LEN_0F7E_P_2,
1589   VEX_LEN_0F90_P_0,
1590   VEX_LEN_0F91_P_0,
1591   VEX_LEN_0F92_P_0,
1592   VEX_LEN_0F93_P_0,
1593   VEX_LEN_0F98_P_0,
1594   VEX_LEN_0FAE_R_2_M_0,
1595   VEX_LEN_0FAE_R_3_M_0,
1596   VEX_LEN_0FC2_P_1,
1597   VEX_LEN_0FC2_P_3,
1598   VEX_LEN_0FC4_P_2,
1599   VEX_LEN_0FC5_P_2,
1600   VEX_LEN_0FD6_P_2,
1601   VEX_LEN_0FF7_P_2,
1602   VEX_LEN_0F3816_P_2,
1603   VEX_LEN_0F3819_P_2,
1604   VEX_LEN_0F381A_P_2_M_0,
1605   VEX_LEN_0F3836_P_2,
1606   VEX_LEN_0F3841_P_2,
1607   VEX_LEN_0F385A_P_2_M_0,
1608   VEX_LEN_0F38DB_P_2,
1609   VEX_LEN_0F38DC_P_2,
1610   VEX_LEN_0F38DD_P_2,
1611   VEX_LEN_0F38DE_P_2,
1612   VEX_LEN_0F38DF_P_2,
1613   VEX_LEN_0F38F2_P_0,
1614   VEX_LEN_0F38F3_R_1_P_0,
1615   VEX_LEN_0F38F3_R_2_P_0,
1616   VEX_LEN_0F38F3_R_3_P_0,
1617   VEX_LEN_0F38F5_P_0,
1618   VEX_LEN_0F38F5_P_1,
1619   VEX_LEN_0F38F5_P_3,
1620   VEX_LEN_0F38F6_P_3,
1621   VEX_LEN_0F38F7_P_0,
1622   VEX_LEN_0F38F7_P_1,
1623   VEX_LEN_0F38F7_P_2,
1624   VEX_LEN_0F38F7_P_3,
1625   VEX_LEN_0F3A00_P_2,
1626   VEX_LEN_0F3A01_P_2,
1627   VEX_LEN_0F3A06_P_2,
1628   VEX_LEN_0F3A0A_P_2,
1629   VEX_LEN_0F3A0B_P_2,
1630   VEX_LEN_0F3A14_P_2,
1631   VEX_LEN_0F3A15_P_2,
1632   VEX_LEN_0F3A16_P_2,
1633   VEX_LEN_0F3A17_P_2,
1634   VEX_LEN_0F3A18_P_2,
1635   VEX_LEN_0F3A19_P_2,
1636   VEX_LEN_0F3A20_P_2,
1637   VEX_LEN_0F3A21_P_2,
1638   VEX_LEN_0F3A22_P_2,
1639   VEX_LEN_0F3A30_P_2,
1640   VEX_LEN_0F3A32_P_2,
1641   VEX_LEN_0F3A38_P_2,
1642   VEX_LEN_0F3A39_P_2,
1643   VEX_LEN_0F3A41_P_2,
1644   VEX_LEN_0F3A44_P_2,
1645   VEX_LEN_0F3A46_P_2,
1646   VEX_LEN_0F3A60_P_2,
1647   VEX_LEN_0F3A61_P_2,
1648   VEX_LEN_0F3A62_P_2,
1649   VEX_LEN_0F3A63_P_2,
1650   VEX_LEN_0F3A6A_P_2,
1651   VEX_LEN_0F3A6B_P_2,
1652   VEX_LEN_0F3A6E_P_2,
1653   VEX_LEN_0F3A6F_P_2,
1654   VEX_LEN_0F3A7A_P_2,
1655   VEX_LEN_0F3A7B_P_2,
1656   VEX_LEN_0F3A7E_P_2,
1657   VEX_LEN_0F3A7F_P_2,
1658   VEX_LEN_0F3ADF_P_2,
1659   VEX_LEN_0F3AF0_P_3,
1660   VEX_LEN_0FXOP_08_CC,
1661   VEX_LEN_0FXOP_08_CD,
1662   VEX_LEN_0FXOP_08_CE,
1663   VEX_LEN_0FXOP_08_CF,
1664   VEX_LEN_0FXOP_08_EC,
1665   VEX_LEN_0FXOP_08_ED,
1666   VEX_LEN_0FXOP_08_EE,
1667   VEX_LEN_0FXOP_08_EF,
1668   VEX_LEN_0FXOP_09_80,
1669   VEX_LEN_0FXOP_09_81
1670 };
1671
1672 enum
1673 {
1674   VEX_W_0F10_P_0 = 0,
1675   VEX_W_0F10_P_1,
1676   VEX_W_0F10_P_2,
1677   VEX_W_0F10_P_3,
1678   VEX_W_0F11_P_0,
1679   VEX_W_0F11_P_1,
1680   VEX_W_0F11_P_2,
1681   VEX_W_0F11_P_3,
1682   VEX_W_0F12_P_0_M_0,
1683   VEX_W_0F12_P_0_M_1,
1684   VEX_W_0F12_P_1,
1685   VEX_W_0F12_P_2,
1686   VEX_W_0F12_P_3,
1687   VEX_W_0F13_M_0,
1688   VEX_W_0F14,
1689   VEX_W_0F15,
1690   VEX_W_0F16_P_0_M_0,
1691   VEX_W_0F16_P_0_M_1,
1692   VEX_W_0F16_P_1,
1693   VEX_W_0F16_P_2,
1694   VEX_W_0F17_M_0,
1695   VEX_W_0F28,
1696   VEX_W_0F29,
1697   VEX_W_0F2B_M_0,
1698   VEX_W_0F2E_P_0,
1699   VEX_W_0F2E_P_2,
1700   VEX_W_0F2F_P_0,
1701   VEX_W_0F2F_P_2,
1702   VEX_W_0F41_P_0_LEN_1,
1703   VEX_W_0F42_P_0_LEN_1,
1704   VEX_W_0F44_P_0_LEN_0,
1705   VEX_W_0F45_P_0_LEN_1,
1706   VEX_W_0F46_P_0_LEN_1,
1707   VEX_W_0F47_P_0_LEN_1,
1708   VEX_W_0F4B_P_2_LEN_1,
1709   VEX_W_0F50_M_0,
1710   VEX_W_0F51_P_0,
1711   VEX_W_0F51_P_1,
1712   VEX_W_0F51_P_2,
1713   VEX_W_0F51_P_3,
1714   VEX_W_0F52_P_0,
1715   VEX_W_0F52_P_1,
1716   VEX_W_0F53_P_0,
1717   VEX_W_0F53_P_1,
1718   VEX_W_0F58_P_0,
1719   VEX_W_0F58_P_1,
1720   VEX_W_0F58_P_2,
1721   VEX_W_0F58_P_3,
1722   VEX_W_0F59_P_0,
1723   VEX_W_0F59_P_1,
1724   VEX_W_0F59_P_2,
1725   VEX_W_0F59_P_3,
1726   VEX_W_0F5A_P_0,
1727   VEX_W_0F5A_P_1,
1728   VEX_W_0F5A_P_3,
1729   VEX_W_0F5B_P_0,
1730   VEX_W_0F5B_P_1,
1731   VEX_W_0F5B_P_2,
1732   VEX_W_0F5C_P_0,
1733   VEX_W_0F5C_P_1,
1734   VEX_W_0F5C_P_2,
1735   VEX_W_0F5C_P_3,
1736   VEX_W_0F5D_P_0,
1737   VEX_W_0F5D_P_1,
1738   VEX_W_0F5D_P_2,
1739   VEX_W_0F5D_P_3,
1740   VEX_W_0F5E_P_0,
1741   VEX_W_0F5E_P_1,
1742   VEX_W_0F5E_P_2,
1743   VEX_W_0F5E_P_3,
1744   VEX_W_0F5F_P_0,
1745   VEX_W_0F5F_P_1,
1746   VEX_W_0F5F_P_2,
1747   VEX_W_0F5F_P_3,
1748   VEX_W_0F60_P_2,
1749   VEX_W_0F61_P_2,
1750   VEX_W_0F62_P_2,
1751   VEX_W_0F63_P_2,
1752   VEX_W_0F64_P_2,
1753   VEX_W_0F65_P_2,
1754   VEX_W_0F66_P_2,
1755   VEX_W_0F67_P_2,
1756   VEX_W_0F68_P_2,
1757   VEX_W_0F69_P_2,
1758   VEX_W_0F6A_P_2,
1759   VEX_W_0F6B_P_2,
1760   VEX_W_0F6C_P_2,
1761   VEX_W_0F6D_P_2,
1762   VEX_W_0F6F_P_1,
1763   VEX_W_0F6F_P_2,
1764   VEX_W_0F70_P_1,
1765   VEX_W_0F70_P_2,
1766   VEX_W_0F70_P_3,
1767   VEX_W_0F71_R_2_P_2,
1768   VEX_W_0F71_R_4_P_2,
1769   VEX_W_0F71_R_6_P_2,
1770   VEX_W_0F72_R_2_P_2,
1771   VEX_W_0F72_R_4_P_2,
1772   VEX_W_0F72_R_6_P_2,
1773   VEX_W_0F73_R_2_P_2,
1774   VEX_W_0F73_R_3_P_2,
1775   VEX_W_0F73_R_6_P_2,
1776   VEX_W_0F73_R_7_P_2,
1777   VEX_W_0F74_P_2,
1778   VEX_W_0F75_P_2,
1779   VEX_W_0F76_P_2,
1780   VEX_W_0F77_P_0,
1781   VEX_W_0F7C_P_2,
1782   VEX_W_0F7C_P_3,
1783   VEX_W_0F7D_P_2,
1784   VEX_W_0F7D_P_3,
1785   VEX_W_0F7E_P_1,
1786   VEX_W_0F7F_P_1,
1787   VEX_W_0F7F_P_2,
1788   VEX_W_0F90_P_0_LEN_0,
1789   VEX_W_0F91_P_0_LEN_0,
1790   VEX_W_0F92_P_0_LEN_0,
1791   VEX_W_0F93_P_0_LEN_0,
1792   VEX_W_0F98_P_0_LEN_0,
1793   VEX_W_0FAE_R_2_M_0,
1794   VEX_W_0FAE_R_3_M_0,
1795   VEX_W_0FC2_P_0,
1796   VEX_W_0FC2_P_1,
1797   VEX_W_0FC2_P_2,
1798   VEX_W_0FC2_P_3,
1799   VEX_W_0FC4_P_2,
1800   VEX_W_0FC5_P_2,
1801   VEX_W_0FD0_P_2,
1802   VEX_W_0FD0_P_3,
1803   VEX_W_0FD1_P_2,
1804   VEX_W_0FD2_P_2,
1805   VEX_W_0FD3_P_2,
1806   VEX_W_0FD4_P_2,
1807   VEX_W_0FD5_P_2,
1808   VEX_W_0FD6_P_2,
1809   VEX_W_0FD7_P_2_M_1,
1810   VEX_W_0FD8_P_2,
1811   VEX_W_0FD9_P_2,
1812   VEX_W_0FDA_P_2,
1813   VEX_W_0FDB_P_2,
1814   VEX_W_0FDC_P_2,
1815   VEX_W_0FDD_P_2,
1816   VEX_W_0FDE_P_2,
1817   VEX_W_0FDF_P_2,
1818   VEX_W_0FE0_P_2,
1819   VEX_W_0FE1_P_2,
1820   VEX_W_0FE2_P_2,
1821   VEX_W_0FE3_P_2,
1822   VEX_W_0FE4_P_2,
1823   VEX_W_0FE5_P_2,
1824   VEX_W_0FE6_P_1,
1825   VEX_W_0FE6_P_2,
1826   VEX_W_0FE6_P_3,
1827   VEX_W_0FE7_P_2_M_0,
1828   VEX_W_0FE8_P_2,
1829   VEX_W_0FE9_P_2,
1830   VEX_W_0FEA_P_2,
1831   VEX_W_0FEB_P_2,
1832   VEX_W_0FEC_P_2,
1833   VEX_W_0FED_P_2,
1834   VEX_W_0FEE_P_2,
1835   VEX_W_0FEF_P_2,
1836   VEX_W_0FF0_P_3_M_0,
1837   VEX_W_0FF1_P_2,
1838   VEX_W_0FF2_P_2,
1839   VEX_W_0FF3_P_2,
1840   VEX_W_0FF4_P_2,
1841   VEX_W_0FF5_P_2,
1842   VEX_W_0FF6_P_2,
1843   VEX_W_0FF7_P_2,
1844   VEX_W_0FF8_P_2,
1845   VEX_W_0FF9_P_2,
1846   VEX_W_0FFA_P_2,
1847   VEX_W_0FFB_P_2,
1848   VEX_W_0FFC_P_2,
1849   VEX_W_0FFD_P_2,
1850   VEX_W_0FFE_P_2,
1851   VEX_W_0F3800_P_2,
1852   VEX_W_0F3801_P_2,
1853   VEX_W_0F3802_P_2,
1854   VEX_W_0F3803_P_2,
1855   VEX_W_0F3804_P_2,
1856   VEX_W_0F3805_P_2,
1857   VEX_W_0F3806_P_2,
1858   VEX_W_0F3807_P_2,
1859   VEX_W_0F3808_P_2,
1860   VEX_W_0F3809_P_2,
1861   VEX_W_0F380A_P_2,
1862   VEX_W_0F380B_P_2,
1863   VEX_W_0F380C_P_2,
1864   VEX_W_0F380D_P_2,
1865   VEX_W_0F380E_P_2,
1866   VEX_W_0F380F_P_2,
1867   VEX_W_0F3816_P_2,
1868   VEX_W_0F3817_P_2,
1869   VEX_W_0F3818_P_2,
1870   VEX_W_0F3819_P_2,
1871   VEX_W_0F381A_P_2_M_0,
1872   VEX_W_0F381C_P_2,
1873   VEX_W_0F381D_P_2,
1874   VEX_W_0F381E_P_2,
1875   VEX_W_0F3820_P_2,
1876   VEX_W_0F3821_P_2,
1877   VEX_W_0F3822_P_2,
1878   VEX_W_0F3823_P_2,
1879   VEX_W_0F3824_P_2,
1880   VEX_W_0F3825_P_2,
1881   VEX_W_0F3828_P_2,
1882   VEX_W_0F3829_P_2,
1883   VEX_W_0F382A_P_2_M_0,
1884   VEX_W_0F382B_P_2,
1885   VEX_W_0F382C_P_2_M_0,
1886   VEX_W_0F382D_P_2_M_0,
1887   VEX_W_0F382E_P_2_M_0,
1888   VEX_W_0F382F_P_2_M_0,
1889   VEX_W_0F3830_P_2,
1890   VEX_W_0F3831_P_2,
1891   VEX_W_0F3832_P_2,
1892   VEX_W_0F3833_P_2,
1893   VEX_W_0F3834_P_2,
1894   VEX_W_0F3835_P_2,
1895   VEX_W_0F3836_P_2,
1896   VEX_W_0F3837_P_2,
1897   VEX_W_0F3838_P_2,
1898   VEX_W_0F3839_P_2,
1899   VEX_W_0F383A_P_2,
1900   VEX_W_0F383B_P_2,
1901   VEX_W_0F383C_P_2,
1902   VEX_W_0F383D_P_2,
1903   VEX_W_0F383E_P_2,
1904   VEX_W_0F383F_P_2,
1905   VEX_W_0F3840_P_2,
1906   VEX_W_0F3841_P_2,
1907   VEX_W_0F3846_P_2,
1908   VEX_W_0F3858_P_2,
1909   VEX_W_0F3859_P_2,
1910   VEX_W_0F385A_P_2_M_0,
1911   VEX_W_0F3878_P_2,
1912   VEX_W_0F3879_P_2,
1913   VEX_W_0F38DB_P_2,
1914   VEX_W_0F38DC_P_2,
1915   VEX_W_0F38DD_P_2,
1916   VEX_W_0F38DE_P_2,
1917   VEX_W_0F38DF_P_2,
1918   VEX_W_0F3A00_P_2,
1919   VEX_W_0F3A01_P_2,
1920   VEX_W_0F3A02_P_2,
1921   VEX_W_0F3A04_P_2,
1922   VEX_W_0F3A05_P_2,
1923   VEX_W_0F3A06_P_2,
1924   VEX_W_0F3A08_P_2,
1925   VEX_W_0F3A09_P_2,
1926   VEX_W_0F3A0A_P_2,
1927   VEX_W_0F3A0B_P_2,
1928   VEX_W_0F3A0C_P_2,
1929   VEX_W_0F3A0D_P_2,
1930   VEX_W_0F3A0E_P_2,
1931   VEX_W_0F3A0F_P_2,
1932   VEX_W_0F3A14_P_2,
1933   VEX_W_0F3A15_P_2,
1934   VEX_W_0F3A18_P_2,
1935   VEX_W_0F3A19_P_2,
1936   VEX_W_0F3A20_P_2,
1937   VEX_W_0F3A21_P_2,
1938   VEX_W_0F3A30_P_2_LEN_0,
1939   VEX_W_0F3A32_P_2_LEN_0,
1940   VEX_W_0F3A38_P_2,
1941   VEX_W_0F3A39_P_2,
1942   VEX_W_0F3A40_P_2,
1943   VEX_W_0F3A41_P_2,
1944   VEX_W_0F3A42_P_2,
1945   VEX_W_0F3A44_P_2,
1946   VEX_W_0F3A46_P_2,
1947   VEX_W_0F3A48_P_2,
1948   VEX_W_0F3A49_P_2,
1949   VEX_W_0F3A4A_P_2,
1950   VEX_W_0F3A4B_P_2,
1951   VEX_W_0F3A4C_P_2,
1952   VEX_W_0F3A60_P_2,
1953   VEX_W_0F3A61_P_2,
1954   VEX_W_0F3A62_P_2,
1955   VEX_W_0F3A63_P_2,
1956   VEX_W_0F3ADF_P_2,
1957
1958   EVEX_W_0F10_P_0,
1959   EVEX_W_0F10_P_1_M_0,
1960   EVEX_W_0F10_P_1_M_1,
1961   EVEX_W_0F10_P_2,
1962   EVEX_W_0F10_P_3_M_0,
1963   EVEX_W_0F10_P_3_M_1,
1964   EVEX_W_0F11_P_0,
1965   EVEX_W_0F11_P_1_M_0,
1966   EVEX_W_0F11_P_1_M_1,
1967   EVEX_W_0F11_P_2,
1968   EVEX_W_0F11_P_3_M_0,
1969   EVEX_W_0F11_P_3_M_1,
1970   EVEX_W_0F12_P_0_M_0,
1971   EVEX_W_0F12_P_0_M_1,
1972   EVEX_W_0F12_P_1,
1973   EVEX_W_0F12_P_2,
1974   EVEX_W_0F12_P_3,
1975   EVEX_W_0F13_P_0,
1976   EVEX_W_0F13_P_2,
1977   EVEX_W_0F14_P_0,
1978   EVEX_W_0F14_P_2,
1979   EVEX_W_0F15_P_0,
1980   EVEX_W_0F15_P_2,
1981   EVEX_W_0F16_P_0_M_0,
1982   EVEX_W_0F16_P_0_M_1,
1983   EVEX_W_0F16_P_1,
1984   EVEX_W_0F16_P_2,
1985   EVEX_W_0F17_P_0,
1986   EVEX_W_0F17_P_2,
1987   EVEX_W_0F28_P_0,
1988   EVEX_W_0F28_P_2,
1989   EVEX_W_0F29_P_0,
1990   EVEX_W_0F29_P_2,
1991   EVEX_W_0F2A_P_1,
1992   EVEX_W_0F2A_P_3,
1993   EVEX_W_0F2B_P_0,
1994   EVEX_W_0F2B_P_2,
1995   EVEX_W_0F2E_P_0,
1996   EVEX_W_0F2E_P_2,
1997   EVEX_W_0F2F_P_0,
1998   EVEX_W_0F2F_P_2,
1999   EVEX_W_0F51_P_0,
2000   EVEX_W_0F51_P_1,
2001   EVEX_W_0F51_P_2,
2002   EVEX_W_0F51_P_3,
2003   EVEX_W_0F58_P_0,
2004   EVEX_W_0F58_P_1,
2005   EVEX_W_0F58_P_2,
2006   EVEX_W_0F58_P_3,
2007   EVEX_W_0F59_P_0,
2008   EVEX_W_0F59_P_1,
2009   EVEX_W_0F59_P_2,
2010   EVEX_W_0F59_P_3,
2011   EVEX_W_0F5A_P_0,
2012   EVEX_W_0F5A_P_1,
2013   EVEX_W_0F5A_P_2,
2014   EVEX_W_0F5A_P_3,
2015   EVEX_W_0F5B_P_0,
2016   EVEX_W_0F5B_P_1,
2017   EVEX_W_0F5B_P_2,
2018   EVEX_W_0F5C_P_0,
2019   EVEX_W_0F5C_P_1,
2020   EVEX_W_0F5C_P_2,
2021   EVEX_W_0F5C_P_3,
2022   EVEX_W_0F5D_P_0,
2023   EVEX_W_0F5D_P_1,
2024   EVEX_W_0F5D_P_2,
2025   EVEX_W_0F5D_P_3,
2026   EVEX_W_0F5E_P_0,
2027   EVEX_W_0F5E_P_1,
2028   EVEX_W_0F5E_P_2,
2029   EVEX_W_0F5E_P_3,
2030   EVEX_W_0F5F_P_0,
2031   EVEX_W_0F5F_P_1,
2032   EVEX_W_0F5F_P_2,
2033   EVEX_W_0F5F_P_3,
2034   EVEX_W_0F62_P_2,
2035   EVEX_W_0F66_P_2,
2036   EVEX_W_0F6A_P_2,
2037   EVEX_W_0F6C_P_2,
2038   EVEX_W_0F6D_P_2,
2039   EVEX_W_0F6E_P_2,
2040   EVEX_W_0F6F_P_1,
2041   EVEX_W_0F6F_P_2,
2042   EVEX_W_0F70_P_2,
2043   EVEX_W_0F72_R_2_P_2,
2044   EVEX_W_0F72_R_6_P_2,
2045   EVEX_W_0F73_R_2_P_2,
2046   EVEX_W_0F73_R_6_P_2,
2047   EVEX_W_0F76_P_2,
2048   EVEX_W_0F78_P_0,
2049   EVEX_W_0F79_P_0,
2050   EVEX_W_0F7A_P_1,
2051   EVEX_W_0F7A_P_3,
2052   EVEX_W_0F7B_P_1,
2053   EVEX_W_0F7B_P_3,
2054   EVEX_W_0F7E_P_1,
2055   EVEX_W_0F7E_P_2,
2056   EVEX_W_0F7F_P_1,
2057   EVEX_W_0F7F_P_2,
2058   EVEX_W_0FC2_P_0,
2059   EVEX_W_0FC2_P_1,
2060   EVEX_W_0FC2_P_2,
2061   EVEX_W_0FC2_P_3,
2062   EVEX_W_0FC6_P_0,
2063   EVEX_W_0FC6_P_2,
2064   EVEX_W_0FD2_P_2,
2065   EVEX_W_0FD3_P_2,
2066   EVEX_W_0FD4_P_2,
2067   EVEX_W_0FD6_P_2,
2068   EVEX_W_0FE6_P_1,
2069   EVEX_W_0FE6_P_2,
2070   EVEX_W_0FE6_P_3,
2071   EVEX_W_0FE7_P_2,
2072   EVEX_W_0FF2_P_2,
2073   EVEX_W_0FF3_P_2,
2074   EVEX_W_0FF4_P_2,
2075   EVEX_W_0FFA_P_2,
2076   EVEX_W_0FFB_P_2,
2077   EVEX_W_0FFE_P_2,
2078   EVEX_W_0F380C_P_2,
2079   EVEX_W_0F380D_P_2,
2080   EVEX_W_0F3811_P_1,
2081   EVEX_W_0F3812_P_1,
2082   EVEX_W_0F3813_P_1,
2083   EVEX_W_0F3813_P_2,
2084   EVEX_W_0F3814_P_1,
2085   EVEX_W_0F3815_P_1,
2086   EVEX_W_0F3818_P_2,
2087   EVEX_W_0F3819_P_2,
2088   EVEX_W_0F381A_P_2,
2089   EVEX_W_0F381B_P_2,
2090   EVEX_W_0F381E_P_2,
2091   EVEX_W_0F381F_P_2,
2092   EVEX_W_0F3821_P_1,
2093   EVEX_W_0F3822_P_1,
2094   EVEX_W_0F3823_P_1,
2095   EVEX_W_0F3824_P_1,
2096   EVEX_W_0F3825_P_1,
2097   EVEX_W_0F3825_P_2,
2098   EVEX_W_0F3828_P_2,
2099   EVEX_W_0F3829_P_2,
2100   EVEX_W_0F382A_P_1,
2101   EVEX_W_0F382A_P_2,
2102   EVEX_W_0F3831_P_1,
2103   EVEX_W_0F3832_P_1,
2104   EVEX_W_0F3833_P_1,
2105   EVEX_W_0F3834_P_1,
2106   EVEX_W_0F3835_P_1,
2107   EVEX_W_0F3835_P_2,
2108   EVEX_W_0F3837_P_2,
2109   EVEX_W_0F383A_P_1,
2110   EVEX_W_0F3840_P_2,
2111   EVEX_W_0F3858_P_2,
2112   EVEX_W_0F3859_P_2,
2113   EVEX_W_0F385A_P_2,
2114   EVEX_W_0F385B_P_2,
2115   EVEX_W_0F3891_P_2,
2116   EVEX_W_0F3893_P_2,
2117   EVEX_W_0F38A1_P_2,
2118   EVEX_W_0F38A3_P_2,
2119   EVEX_W_0F38C7_R_1_P_2,
2120   EVEX_W_0F38C7_R_2_P_2,
2121   EVEX_W_0F38C7_R_5_P_2,
2122   EVEX_W_0F38C7_R_6_P_2,
2123
2124   EVEX_W_0F3A00_P_2,
2125   EVEX_W_0F3A01_P_2,
2126   EVEX_W_0F3A04_P_2,
2127   EVEX_W_0F3A05_P_2,
2128   EVEX_W_0F3A08_P_2,
2129   EVEX_W_0F3A09_P_2,
2130   EVEX_W_0F3A0A_P_2,
2131   EVEX_W_0F3A0B_P_2,
2132   EVEX_W_0F3A18_P_2,
2133   EVEX_W_0F3A19_P_2,
2134   EVEX_W_0F3A1A_P_2,
2135   EVEX_W_0F3A1B_P_2,
2136   EVEX_W_0F3A1D_P_2,
2137   EVEX_W_0F3A21_P_2,
2138   EVEX_W_0F3A23_P_2,
2139   EVEX_W_0F3A38_P_2,
2140   EVEX_W_0F3A39_P_2,
2141   EVEX_W_0F3A3A_P_2,
2142   EVEX_W_0F3A3B_P_2,
2143   EVEX_W_0F3A43_P_2,
2144 };
2145
2146 typedef void (*op_rtn) (int bytemode, int sizeflag);
2147
2148 struct dis386 {
2149   const char *name;
2150   struct
2151     {
2152       op_rtn rtn;
2153       int bytemode;
2154     } op[MAX_OPERANDS];
2155 };
2156
2157 /* Upper case letters in the instruction names here are macros.
2158    'A' => print 'b' if no register operands or suffix_always is true
2159    'B' => print 'b' if suffix_always is true
2160    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2161           size prefix
2162    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2163           suffix_always is true
2164    'E' => print 'e' if 32-bit form of jcxz
2165    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2166    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2167    'H' => print ",pt" or ",pn" branch hint
2168    'I' => honor following macro letter even in Intel mode (implemented only
2169           for some of the macro letters)
2170    'J' => print 'l'
2171    'K' => print 'd' or 'q' if rex prefix is present.
2172    'L' => print 'l' if suffix_always is true
2173    'M' => print 'r' if intel_mnemonic is false.
2174    'N' => print 'n' if instruction has no wait "prefix"
2175    'O' => print 'd' or 'o' (or 'q' in Intel mode)
2176    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2177           or suffix_always is true.  print 'q' if rex prefix is present.
2178    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2179           is true
2180    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2181    'S' => print 'w', 'l' or 'q' if suffix_always is true
2182    'T' => print 'q' in 64bit mode and behave as 'P' otherwise
2183    'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
2184    'V' => print 'q' in 64bit mode and behave as 'S' otherwise
2185    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2186    'X' => print 's', 'd' depending on data16 prefix (for XMM)
2187    'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
2188           suffix_always is true.
2189    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2190    '!' => change condition from true to false or from false to true.
2191    '%' => add 1 upper case letter to the macro.
2192
2193    2 upper case letter macros:
2194    "XY" => print 'x' or 'y' if no register operands or suffix_always
2195            is true.
2196    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2197    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2198            or suffix_always is true
2199    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2200    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2201    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2202    "LW" => print 'd', 'q' depending on the VEX.W bit
2203
2204    Many of the above letters print nothing in Intel mode.  See "putop"
2205    for the details.
2206
2207    Braces '{' and '}', and vertical bars '|', indicate alternative
2208    mnemonic strings for AT&T and Intel.  */
2209
2210 static const struct dis386 dis386[] = {
2211   /* 00 */
2212   { "addB",             { Ebh1, Gb } },
2213   { "addS",             { Evh1, Gv } },
2214   { "addB",             { Gb, EbS } },
2215   { "addS",             { Gv, EvS } },
2216   { "addB",             { AL, Ib } },
2217   { "addS",             { eAX, Iv } },
2218   { X86_64_TABLE (X86_64_06) },
2219   { X86_64_TABLE (X86_64_07) },
2220   /* 08 */
2221   { "orB",              { Ebh1, Gb } },
2222   { "orS",              { Evh1, Gv } },
2223   { "orB",              { Gb, EbS } },
2224   { "orS",              { Gv, EvS } },
2225   { "orB",              { AL, Ib } },
2226   { "orS",              { eAX, Iv } },
2227   { X86_64_TABLE (X86_64_0D) },
2228   { Bad_Opcode },       /* 0x0f extended opcode escape */
2229   /* 10 */
2230   { "adcB",             { Ebh1, Gb } },
2231   { "adcS",             { Evh1, Gv } },
2232   { "adcB",             { Gb, EbS } },
2233   { "adcS",             { Gv, EvS } },
2234   { "adcB",             { AL, Ib } },
2235   { "adcS",             { eAX, Iv } },
2236   { X86_64_TABLE (X86_64_16) },
2237   { X86_64_TABLE (X86_64_17) },
2238   /* 18 */
2239   { "sbbB",             { Ebh1, Gb } },
2240   { "sbbS",             { Evh1, Gv } },
2241   { "sbbB",             { Gb, EbS } },
2242   { "sbbS",             { Gv, EvS } },
2243   { "sbbB",             { AL, Ib } },
2244   { "sbbS",             { eAX, Iv } },
2245   { X86_64_TABLE (X86_64_1E) },
2246   { X86_64_TABLE (X86_64_1F) },
2247   /* 20 */
2248   { "andB",             { Ebh1, Gb } },
2249   { "andS",             { Evh1, Gv } },
2250   { "andB",             { Gb, EbS } },
2251   { "andS",             { Gv, EvS } },
2252   { "andB",             { AL, Ib } },
2253   { "andS",             { eAX, Iv } },
2254   { Bad_Opcode },       /* SEG ES prefix */
2255   { X86_64_TABLE (X86_64_27) },
2256   /* 28 */
2257   { "subB",             { Ebh1, Gb } },
2258   { "subS",             { Evh1, Gv } },
2259   { "subB",             { Gb, EbS } },
2260   { "subS",             { Gv, EvS } },
2261   { "subB",             { AL, Ib } },
2262   { "subS",             { eAX, Iv } },
2263   { Bad_Opcode },       /* SEG CS prefix */
2264   { X86_64_TABLE (X86_64_2F) },
2265   /* 30 */
2266   { "xorB",             { Ebh1, Gb } },
2267   { "xorS",             { Evh1, Gv } },
2268   { "xorB",             { Gb, EbS } },
2269   { "xorS",             { Gv, EvS } },
2270   { "xorB",             { AL, Ib } },
2271   { "xorS",             { eAX, Iv } },
2272   { Bad_Opcode },       /* SEG SS prefix */
2273   { X86_64_TABLE (X86_64_37) },
2274   /* 38 */
2275   { "cmpB",             { Eb, Gb } },
2276   { "cmpS",             { Ev, Gv } },
2277   { "cmpB",             { Gb, EbS } },
2278   { "cmpS",             { Gv, EvS } },
2279   { "cmpB",             { AL, Ib } },
2280   { "cmpS",             { eAX, Iv } },
2281   { Bad_Opcode },       /* SEG DS prefix */
2282   { X86_64_TABLE (X86_64_3F) },
2283   /* 40 */
2284   { "inc{S|}",          { RMeAX } },
2285   { "inc{S|}",          { RMeCX } },
2286   { "inc{S|}",          { RMeDX } },
2287   { "inc{S|}",          { RMeBX } },
2288   { "inc{S|}",          { RMeSP } },
2289   { "inc{S|}",          { RMeBP } },
2290   { "inc{S|}",          { RMeSI } },
2291   { "inc{S|}",          { RMeDI } },
2292   /* 48 */
2293   { "dec{S|}",          { RMeAX } },
2294   { "dec{S|}",          { RMeCX } },
2295   { "dec{S|}",          { RMeDX } },
2296   { "dec{S|}",          { RMeBX } },
2297   { "dec{S|}",          { RMeSP } },
2298   { "dec{S|}",          { RMeBP } },
2299   { "dec{S|}",          { RMeSI } },
2300   { "dec{S|}",          { RMeDI } },
2301   /* 50 */
2302   { "pushV",            { RMrAX } },
2303   { "pushV",            { RMrCX } },
2304   { "pushV",            { RMrDX } },
2305   { "pushV",            { RMrBX } },
2306   { "pushV",            { RMrSP } },
2307   { "pushV",            { RMrBP } },
2308   { "pushV",            { RMrSI } },
2309   { "pushV",            { RMrDI } },
2310   /* 58 */
2311   { "popV",             { RMrAX } },
2312   { "popV",             { RMrCX } },
2313   { "popV",             { RMrDX } },
2314   { "popV",             { RMrBX } },
2315   { "popV",             { RMrSP } },
2316   { "popV",             { RMrBP } },
2317   { "popV",             { RMrSI } },
2318   { "popV",             { RMrDI } },
2319   /* 60 */
2320   { X86_64_TABLE (X86_64_60) },
2321   { X86_64_TABLE (X86_64_61) },
2322   { X86_64_TABLE (X86_64_62) },
2323   { X86_64_TABLE (X86_64_63) },
2324   { Bad_Opcode },       /* seg fs */
2325   { Bad_Opcode },       /* seg gs */
2326   { Bad_Opcode },       /* op size prefix */
2327   { Bad_Opcode },       /* adr size prefix */
2328   /* 68 */
2329   { "pushT",            { sIv } },
2330   { "imulS",            { Gv, Ev, Iv } },
2331   { "pushT",            { sIbT } },
2332   { "imulS",            { Gv, Ev, sIb } },
2333   { "ins{b|}",          { Ybr, indirDX } },
2334   { X86_64_TABLE (X86_64_6D) },
2335   { "outs{b|}",         { indirDXr, Xb } },
2336   { X86_64_TABLE (X86_64_6F) },
2337   /* 70 */
2338   { "joH",              { Jb, BND, cond_jump_flag } },
2339   { "jnoH",             { Jb, BND, cond_jump_flag } },
2340   { "jbH",              { Jb, BND, cond_jump_flag } },
2341   { "jaeH",             { Jb, BND, cond_jump_flag } },
2342   { "jeH",              { Jb, BND, cond_jump_flag } },
2343   { "jneH",             { Jb, BND, cond_jump_flag } },
2344   { "jbeH",             { Jb, BND, cond_jump_flag } },
2345   { "jaH",              { Jb, BND, cond_jump_flag } },
2346   /* 78 */
2347   { "jsH",              { Jb, BND, cond_jump_flag } },
2348   { "jnsH",             { Jb, BND, cond_jump_flag } },
2349   { "jpH",              { Jb, BND, cond_jump_flag } },
2350   { "jnpH",             { Jb, BND, cond_jump_flag } },
2351   { "jlH",              { Jb, BND, cond_jump_flag } },
2352   { "jgeH",             { Jb, BND, cond_jump_flag } },
2353   { "jleH",             { Jb, BND, cond_jump_flag } },
2354   { "jgH",              { Jb, BND, cond_jump_flag } },
2355   /* 80 */
2356   { REG_TABLE (REG_80) },
2357   { REG_TABLE (REG_81) },
2358   { Bad_Opcode },
2359   { REG_TABLE (REG_82) },
2360   { "testB",            { Eb, Gb } },
2361   { "testS",            { Ev, Gv } },
2362   { "xchgB",            { Ebh2, Gb } },
2363   { "xchgS",            { Evh2, Gv } },
2364   /* 88 */
2365   { "movB",             { Ebh3, Gb } },
2366   { "movS",             { Evh3, Gv } },
2367   { "movB",             { Gb, EbS } },
2368   { "movS",             { Gv, EvS } },
2369   { "movD",             { Sv, Sw } },
2370   { MOD_TABLE (MOD_8D) },
2371   { "movD",             { Sw, Sv } },
2372   { REG_TABLE (REG_8F) },
2373   /* 90 */
2374   { PREFIX_TABLE (PREFIX_90) },
2375   { "xchgS",            { RMeCX, eAX } },
2376   { "xchgS",            { RMeDX, eAX } },
2377   { "xchgS",            { RMeBX, eAX } },
2378   { "xchgS",            { RMeSP, eAX } },
2379   { "xchgS",            { RMeBP, eAX } },
2380   { "xchgS",            { RMeSI, eAX } },
2381   { "xchgS",            { RMeDI, eAX } },
2382   /* 98 */
2383   { "cW{t|}R",          { XX } },
2384   { "cR{t|}O",          { XX } },
2385   { X86_64_TABLE (X86_64_9A) },
2386   { Bad_Opcode },       /* fwait */
2387   { "pushfT",           { XX } },
2388   { "popfT",            { XX } },
2389   { "sahf",             { XX } },
2390   { "lahf",             { XX } },
2391   /* a0 */
2392   { "mov%LB",           { AL, Ob } },
2393   { "mov%LS",           { eAX, Ov } },
2394   { "mov%LB",           { Ob, AL } },
2395   { "mov%LS",           { Ov, eAX } },
2396   { "movs{b|}",         { Ybr, Xb } },
2397   { "movs{R|}",         { Yvr, Xv } },
2398   { "cmps{b|}",         { Xb, Yb } },
2399   { "cmps{R|}",         { Xv, Yv } },
2400   /* a8 */
2401   { "testB",            { AL, Ib } },
2402   { "testS",            { eAX, Iv } },
2403   { "stosB",            { Ybr, AL } },
2404   { "stosS",            { Yvr, eAX } },
2405   { "lodsB",            { ALr, Xb } },
2406   { "lodsS",            { eAXr, Xv } },
2407   { "scasB",            { AL, Yb } },
2408   { "scasS",            { eAX, Yv } },
2409   /* b0 */
2410   { "movB",             { RMAL, Ib } },
2411   { "movB",             { RMCL, Ib } },
2412   { "movB",             { RMDL, Ib } },
2413   { "movB",             { RMBL, Ib } },
2414   { "movB",             { RMAH, Ib } },
2415   { "movB",             { RMCH, Ib } },
2416   { "movB",             { RMDH, Ib } },
2417   { "movB",             { RMBH, Ib } },
2418   /* b8 */
2419   { "mov%LV",           { RMeAX, Iv64 } },
2420   { "mov%LV",           { RMeCX, Iv64 } },
2421   { "mov%LV",           { RMeDX, Iv64 } },
2422   { "mov%LV",           { RMeBX, Iv64 } },
2423   { "mov%LV",           { RMeSP, Iv64 } },
2424   { "mov%LV",           { RMeBP, Iv64 } },
2425   { "mov%LV",           { RMeSI, Iv64 } },
2426   { "mov%LV",           { RMeDI, Iv64 } },
2427   /* c0 */
2428   { REG_TABLE (REG_C0) },
2429   { REG_TABLE (REG_C1) },
2430   { "retT",             { Iw, BND } },
2431   { "retT",             { BND } },
2432   { X86_64_TABLE (X86_64_C4) },
2433   { X86_64_TABLE (X86_64_C5) },
2434   { REG_TABLE (REG_C6) },
2435   { REG_TABLE (REG_C7) },
2436   /* c8 */
2437   { "enterT",           { Iw, Ib } },
2438   { "leaveT",           { XX } },
2439   { "Jret{|f}P",        { Iw } },
2440   { "Jret{|f}P",        { XX } },
2441   { "int3",             { XX } },
2442   { "int",              { Ib } },
2443   { X86_64_TABLE (X86_64_CE) },
2444   { "iretP",            { XX } },
2445   /* d0 */
2446   { REG_TABLE (REG_D0) },
2447   { REG_TABLE (REG_D1) },
2448   { REG_TABLE (REG_D2) },
2449   { REG_TABLE (REG_D3) },
2450   { X86_64_TABLE (X86_64_D4) },
2451   { X86_64_TABLE (X86_64_D5) },
2452   { Bad_Opcode },
2453   { "xlat",             { DSBX } },
2454   /* d8 */
2455   { FLOAT },
2456   { FLOAT },
2457   { FLOAT },
2458   { FLOAT },
2459   { FLOAT },
2460   { FLOAT },
2461   { FLOAT },
2462   { FLOAT },
2463   /* e0 */
2464   { "loopneFH",         { Jb, XX, loop_jcxz_flag } },
2465   { "loopeFH",          { Jb, XX, loop_jcxz_flag } },
2466   { "loopFH",           { Jb, XX, loop_jcxz_flag } },
2467   { "jEcxzH",           { Jb, XX, loop_jcxz_flag } },
2468   { "inB",              { AL, Ib } },
2469   { "inG",              { zAX, Ib } },
2470   { "outB",             { Ib, AL } },
2471   { "outG",             { Ib, zAX } },
2472   /* e8 */
2473   { "callT",            { Jv, BND } },
2474   { "jmpT",             { Jv, BND } },
2475   { X86_64_TABLE (X86_64_EA) },
2476   { "jmp",              { Jb, BND } },
2477   { "inB",              { AL, indirDX } },
2478   { "inG",              { zAX, indirDX } },
2479   { "outB",             { indirDX, AL } },
2480   { "outG",             { indirDX, zAX } },
2481   /* f0 */
2482   { Bad_Opcode },       /* lock prefix */
2483   { "icebp",            { XX } },
2484   { Bad_Opcode },       /* repne */
2485   { Bad_Opcode },       /* repz */
2486   { "hlt",              { XX } },
2487   { "cmc",              { XX } },
2488   { REG_TABLE (REG_F6) },
2489   { REG_TABLE (REG_F7) },
2490   /* f8 */
2491   { "clc",              { XX } },
2492   { "stc",              { XX } },
2493   { "cli",              { XX } },
2494   { "sti",              { XX } },
2495   { "cld",              { XX } },
2496   { "std",              { XX } },
2497   { REG_TABLE (REG_FE) },
2498   { REG_TABLE (REG_FF) },
2499 };
2500
2501 static const struct dis386 dis386_twobyte[] = {
2502   /* 00 */
2503   { REG_TABLE (REG_0F00 ) },
2504   { REG_TABLE (REG_0F01 ) },
2505   { "larS",             { Gv, Ew } },
2506   { "lslS",             { Gv, Ew } },
2507   { Bad_Opcode },
2508   { "syscall",          { XX } },
2509   { "clts",             { XX } },
2510   { "sysretP",          { XX } },
2511   /* 08 */
2512   { "invd",             { XX } },
2513   { "wbinvd",           { XX } },
2514   { Bad_Opcode },
2515   { "ud2",              { XX } },
2516   { Bad_Opcode },
2517   { REG_TABLE (REG_0F0D) },
2518   { "femms",            { XX } },
2519   { "",                 { MX, EM, OPSUF } }, /* See OP_3DNowSuffix.  */
2520   /* 10 */
2521   { PREFIX_TABLE (PREFIX_0F10) },
2522   { PREFIX_TABLE (PREFIX_0F11) },
2523   { PREFIX_TABLE (PREFIX_0F12) },
2524   { MOD_TABLE (MOD_0F13) },
2525   { "unpcklpX",         { XM, EXx } },
2526   { "unpckhpX",         { XM, EXx } },
2527   { PREFIX_TABLE (PREFIX_0F16) },
2528   { MOD_TABLE (MOD_0F17) },
2529   /* 18 */
2530   { REG_TABLE (REG_0F18) },
2531   { "nopQ",             { Ev } },
2532   { PREFIX_TABLE (PREFIX_0F1A) },
2533   { PREFIX_TABLE (PREFIX_0F1B) },
2534   { "nopQ",             { Ev } },
2535   { "nopQ",             { Ev } },
2536   { "nopQ",             { Ev } },
2537   { "nopQ",             { Ev } },
2538   /* 20 */
2539   { MOD_TABLE (MOD_0F20) },
2540   { MOD_TABLE (MOD_0F21) },
2541   { MOD_TABLE (MOD_0F22) },
2542   { MOD_TABLE (MOD_0F23) },
2543   { MOD_TABLE (MOD_0F24) },
2544   { Bad_Opcode },
2545   { MOD_TABLE (MOD_0F26) },
2546   { Bad_Opcode },
2547   /* 28 */
2548   { "movapX",           { XM, EXx } },
2549   { "movapX",           { EXxS, XM } },
2550   { PREFIX_TABLE (PREFIX_0F2A) },
2551   { PREFIX_TABLE (PREFIX_0F2B) },
2552   { PREFIX_TABLE (PREFIX_0F2C) },
2553   { PREFIX_TABLE (PREFIX_0F2D) },
2554   { PREFIX_TABLE (PREFIX_0F2E) },
2555   { PREFIX_TABLE (PREFIX_0F2F) },
2556   /* 30 */
2557   { "wrmsr",            { XX } },
2558   { "rdtsc",            { XX } },
2559   { "rdmsr",            { XX } },
2560   { "rdpmc",            { XX } },
2561   { "sysenter",         { XX } },
2562   { "sysexit",          { XX } },
2563   { Bad_Opcode },
2564   { "getsec",           { XX } },
2565   /* 38 */
2566   { THREE_BYTE_TABLE (THREE_BYTE_0F38) },
2567   { Bad_Opcode },
2568   { THREE_BYTE_TABLE (THREE_BYTE_0F3A) },
2569   { Bad_Opcode },
2570   { Bad_Opcode },
2571   { Bad_Opcode },
2572   { Bad_Opcode },
2573   { Bad_Opcode },
2574   /* 40 */
2575   { "cmovoS",           { Gv, Ev } },
2576   { "cmovnoS",          { Gv, Ev } },
2577   { "cmovbS",           { Gv, Ev } },
2578   { "cmovaeS",          { Gv, Ev } },
2579   { "cmoveS",           { Gv, Ev } },
2580   { "cmovneS",          { Gv, Ev } },
2581   { "cmovbeS",          { Gv, Ev } },
2582   { "cmovaS",           { Gv, Ev } },
2583   /* 48 */
2584   { "cmovsS",           { Gv, Ev } },
2585   { "cmovnsS",          { Gv, Ev } },
2586   { "cmovpS",           { Gv, Ev } },
2587   { "cmovnpS",          { Gv, Ev } },
2588   { "cmovlS",           { Gv, Ev } },
2589   { "cmovgeS",          { Gv, Ev } },
2590   { "cmovleS",          { Gv, Ev } },
2591   { "cmovgS",           { Gv, Ev } },
2592   /* 50 */
2593   { MOD_TABLE (MOD_0F51) },
2594   { PREFIX_TABLE (PREFIX_0F51) },
2595   { PREFIX_TABLE (PREFIX_0F52) },
2596   { PREFIX_TABLE (PREFIX_0F53) },
2597   { "andpX",            { XM, EXx } },
2598   { "andnpX",           { XM, EXx } },
2599   { "orpX",             { XM, EXx } },
2600   { "xorpX",            { XM, EXx } },
2601   /* 58 */
2602   { PREFIX_TABLE (PREFIX_0F58) },
2603   { PREFIX_TABLE (PREFIX_0F59) },
2604   { PREFIX_TABLE (PREFIX_0F5A) },
2605   { PREFIX_TABLE (PREFIX_0F5B) },
2606   { PREFIX_TABLE (PREFIX_0F5C) },
2607   { PREFIX_TABLE (PREFIX_0F5D) },
2608   { PREFIX_TABLE (PREFIX_0F5E) },
2609   { PREFIX_TABLE (PREFIX_0F5F) },
2610   /* 60 */
2611   { PREFIX_TABLE (PREFIX_0F60) },
2612   { PREFIX_TABLE (PREFIX_0F61) },
2613   { PREFIX_TABLE (PREFIX_0F62) },
2614   { "packsswb",         { MX, EM } },
2615   { "pcmpgtb",          { MX, EM } },
2616   { "pcmpgtw",          { MX, EM } },
2617   { "pcmpgtd",          { MX, EM } },
2618   { "packuswb",         { MX, EM } },
2619   /* 68 */
2620   { "punpckhbw",        { MX, EM } },
2621   { "punpckhwd",        { MX, EM } },
2622   { "punpckhdq",        { MX, EM } },
2623   { "packssdw",         { MX, EM } },
2624   { PREFIX_TABLE (PREFIX_0F6C) },
2625   { PREFIX_TABLE (PREFIX_0F6D) },
2626   { "movK",             { MX, Edq } },
2627   { PREFIX_TABLE (PREFIX_0F6F) },
2628   /* 70 */
2629   { PREFIX_TABLE (PREFIX_0F70) },
2630   { REG_TABLE (REG_0F71) },
2631   { REG_TABLE (REG_0F72) },
2632   { REG_TABLE (REG_0F73) },
2633   { "pcmpeqb",          { MX, EM } },
2634   { "pcmpeqw",          { MX, EM } },
2635   { "pcmpeqd",          { MX, EM } },
2636   { "emms",             { XX } },
2637   /* 78 */
2638   { PREFIX_TABLE (PREFIX_0F78) },
2639   { PREFIX_TABLE (PREFIX_0F79) },
2640   { THREE_BYTE_TABLE (THREE_BYTE_0F7A) },
2641   { Bad_Opcode },
2642   { PREFIX_TABLE (PREFIX_0F7C) },
2643   { PREFIX_TABLE (PREFIX_0F7D) },
2644   { PREFIX_TABLE (PREFIX_0F7E) },
2645   { PREFIX_TABLE (PREFIX_0F7F) },
2646   /* 80 */
2647   { "joH",              { Jv, BND, cond_jump_flag } },
2648   { "jnoH",             { Jv, BND, cond_jump_flag } },
2649   { "jbH",              { Jv, BND, cond_jump_flag } },
2650   { "jaeH",             { Jv, BND, cond_jump_flag } },
2651   { "jeH",              { Jv, BND, cond_jump_flag } },
2652   { "jneH",             { Jv, BND, cond_jump_flag } },
2653   { "jbeH",             { Jv, BND, cond_jump_flag } },
2654   { "jaH",              { Jv, BND, cond_jump_flag } },
2655   /* 88 */
2656   { "jsH",              { Jv, BND, cond_jump_flag } },
2657   { "jnsH",             { Jv, BND, cond_jump_flag } },
2658   { "jpH",              { Jv, BND, cond_jump_flag } },
2659   { "jnpH",             { Jv, BND, cond_jump_flag } },
2660   { "jlH",              { Jv, BND, cond_jump_flag } },
2661   { "jgeH",             { Jv, BND, cond_jump_flag } },
2662   { "jleH",             { Jv, BND, cond_jump_flag } },
2663   { "jgH",              { Jv, BND, cond_jump_flag } },
2664   /* 90 */
2665   { "seto",             { Eb } },
2666   { "setno",            { Eb } },
2667   { "setb",             { Eb } },
2668   { "setae",            { Eb } },
2669   { "sete",             { Eb } },
2670   { "setne",            { Eb } },
2671   { "setbe",            { Eb } },
2672   { "seta",             { Eb } },
2673   /* 98 */
2674   { "sets",             { Eb } },
2675   { "setns",            { Eb } },
2676   { "setp",             { Eb } },
2677   { "setnp",            { Eb } },
2678   { "setl",             { Eb } },
2679   { "setge",            { Eb } },
2680   { "setle",            { Eb } },
2681   { "setg",             { Eb } },
2682   /* a0 */
2683   { "pushT",            { fs } },
2684   { "popT",             { fs } },
2685   { "cpuid",            { XX } },
2686   { "btS",              { Ev, Gv } },
2687   { "shldS",            { Ev, Gv, Ib } },
2688   { "shldS",            { Ev, Gv, CL } },
2689   { REG_TABLE (REG_0FA6) },
2690   { REG_TABLE (REG_0FA7) },
2691   /* a8 */
2692   { "pushT",            { gs } },
2693   { "popT",             { gs } },
2694   { "rsm",              { XX } },
2695   { "btsS",             { Evh1, Gv } },
2696   { "shrdS",            { Ev, Gv, Ib } },
2697   { "shrdS",            { Ev, Gv, CL } },
2698   { REG_TABLE (REG_0FAE) },
2699   { "imulS",            { Gv, Ev } },
2700   /* b0 */
2701   { "cmpxchgB",         { Ebh1, Gb } },
2702   { "cmpxchgS",         { Evh1, Gv } },
2703   { MOD_TABLE (MOD_0FB2) },
2704   { "btrS",             { Evh1, Gv } },
2705   { MOD_TABLE (MOD_0FB4) },
2706   { MOD_TABLE (MOD_0FB5) },
2707   { "movz{bR|x}",       { Gv, Eb } },
2708   { "movz{wR|x}",       { Gv, Ew } }, /* yes, there really is movzww ! */
2709   /* b8 */
2710   { PREFIX_TABLE (PREFIX_0FB8) },
2711   { "ud1",              { XX } },
2712   { REG_TABLE (REG_0FBA) },
2713   { "btcS",             { Evh1, Gv } },
2714   { PREFIX_TABLE (PREFIX_0FBC) },
2715   { PREFIX_TABLE (PREFIX_0FBD) },
2716   { "movs{bR|x}",       { Gv, Eb } },
2717   { "movs{wR|x}",       { Gv, Ew } }, /* yes, there really is movsww ! */
2718   /* c0 */
2719   { "xaddB",            { Ebh1, Gb } },
2720   { "xaddS",            { Evh1, Gv } },
2721   { PREFIX_TABLE (PREFIX_0FC2) },
2722   { PREFIX_TABLE (PREFIX_0FC3) },
2723   { "pinsrw",           { MX, Edqw, Ib } },
2724   { "pextrw",           { Gdq, MS, Ib } },
2725   { "shufpX",           { XM, EXx, Ib } },
2726   { REG_TABLE (REG_0FC7) },
2727   /* c8 */
2728   { "bswap",            { RMeAX } },
2729   { "bswap",            { RMeCX } },
2730   { "bswap",            { RMeDX } },
2731   { "bswap",            { RMeBX } },
2732   { "bswap",            { RMeSP } },
2733   { "bswap",            { RMeBP } },
2734   { "bswap",            { RMeSI } },
2735   { "bswap",            { RMeDI } },
2736   /* d0 */
2737   { PREFIX_TABLE (PREFIX_0FD0) },
2738   { "psrlw",            { MX, EM } },
2739   { "psrld",            { MX, EM } },
2740   { "psrlq",            { MX, EM } },
2741   { "paddq",            { MX, EM } },
2742   { "pmullw",           { MX, EM } },
2743   { PREFIX_TABLE (PREFIX_0FD6) },
2744   { MOD_TABLE (MOD_0FD7) },
2745   /* d8 */
2746   { "psubusb",          { MX, EM } },
2747   { "psubusw",          { MX, EM } },
2748   { "pminub",           { MX, EM } },
2749   { "pand",             { MX, EM } },
2750   { "paddusb",          { MX, EM } },
2751   { "paddusw",          { MX, EM } },
2752   { "pmaxub",           { MX, EM } },
2753   { "pandn",            { MX, EM } },
2754   /* e0 */
2755   { "pavgb",            { MX, EM } },
2756   { "psraw",            { MX, EM } },
2757   { "psrad",            { MX, EM } },
2758   { "pavgw",            { MX, EM } },
2759   { "pmulhuw",          { MX, EM } },
2760   { "pmulhw",           { MX, EM } },
2761   { PREFIX_TABLE (PREFIX_0FE6) },
2762   { PREFIX_TABLE (PREFIX_0FE7) },
2763   /* e8 */
2764   { "psubsb",           { MX, EM } },
2765   { "psubsw",           { MX, EM } },
2766   { "pminsw",           { MX, EM } },
2767   { "por",              { MX, EM } },
2768   { "paddsb",           { MX, EM } },
2769   { "paddsw",           { MX, EM } },
2770   { "pmaxsw",           { MX, EM } },
2771   { "pxor",             { MX, EM } },
2772   /* f0 */
2773   { PREFIX_TABLE (PREFIX_0FF0) },
2774   { "psllw",            { MX, EM } },
2775   { "pslld",            { MX, EM } },
2776   { "psllq",            { MX, EM } },
2777   { "pmuludq",          { MX, EM } },
2778   { "pmaddwd",          { MX, EM } },
2779   { "psadbw",           { MX, EM } },
2780   { PREFIX_TABLE (PREFIX_0FF7) },
2781   /* f8 */
2782   { "psubb",            { MX, EM } },
2783   { "psubw",            { MX, EM } },
2784   { "psubd",            { MX, EM } },
2785   { "psubq",            { MX, EM } },
2786   { "paddb",            { MX, EM } },
2787   { "paddw",            { MX, EM } },
2788   { "paddd",            { MX, EM } },
2789   { Bad_Opcode },
2790 };
2791
2792 static const unsigned char onebyte_has_modrm[256] = {
2793   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2794   /*       -------------------------------        */
2795   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2796   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2797   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2798   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2799   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2800   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2801   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2802   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2803   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2804   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2805   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2806   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2807   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2808   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2809   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2810   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
2811   /*       -------------------------------        */
2812   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2813 };
2814
2815 static const unsigned char twobyte_has_modrm[256] = {
2816   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2817   /*       -------------------------------        */
2818   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2819   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2820   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2821   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2822   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2823   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2824   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2825   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2826   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2827   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2828   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2829   /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
2830   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2831   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2832   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2833   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0  /* ff */
2834   /*       -------------------------------        */
2835   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2836 };
2837
2838 static char obuf[100];
2839 static char *obufp;
2840 static char *mnemonicendp;
2841 static char scratchbuf[100];
2842 static unsigned char *start_codep;
2843 static unsigned char *insn_codep;
2844 static unsigned char *codep;
2845 static int last_lock_prefix;
2846 static int last_repz_prefix;
2847 static int last_repnz_prefix;
2848 static int last_data_prefix;
2849 static int last_addr_prefix;
2850 static int last_rex_prefix;
2851 static int last_seg_prefix;
2852 #define MAX_CODE_LENGTH 15
2853 /* We can up to 14 prefixes since the maximum instruction length is
2854    15bytes.  */
2855 static int all_prefixes[MAX_CODE_LENGTH - 1];
2856 static disassemble_info *the_info;
2857 static struct
2858   {
2859     int mod;
2860     int reg;
2861     int rm;
2862   }
2863 modrm;
2864 static unsigned char need_modrm;
2865 static struct
2866   {
2867     int scale;
2868     int index;
2869     int base;
2870   }
2871 sib;
2872 static struct
2873   {
2874     int register_specifier;
2875     int length;
2876     int prefix;
2877     int w;
2878     int evex;
2879     int r;
2880     int v;
2881     int mask_register_specifier;
2882     int zeroing;
2883     int ll;
2884     int b;
2885   }
2886 vex;
2887 static unsigned char need_vex;
2888 static unsigned char need_vex_reg;
2889 static unsigned char vex_w_done;
2890
2891 struct op
2892   {
2893     const char *name;
2894     unsigned int len;
2895   };
2896
2897 /* If we are accessing mod/rm/reg without need_modrm set, then the
2898    values are stale.  Hitting this abort likely indicates that you
2899    need to update onebyte_has_modrm or twobyte_has_modrm.  */
2900 #define MODRM_CHECK  if (!need_modrm) abort ()
2901
2902 static const char **names64;
2903 static const char **names32;
2904 static const char **names16;
2905 static const char **names8;
2906 static const char **names8rex;
2907 static const char **names_seg;
2908 static const char *index64;
2909 static const char *index32;
2910 static const char **index16;
2911 static const char **names_bnd;
2912
2913 static const char *intel_names64[] = {
2914   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2915   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2916 };
2917 static const char *intel_names32[] = {
2918   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
2919   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
2920 };
2921 static const char *intel_names16[] = {
2922   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
2923   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
2924 };
2925 static const char *intel_names8[] = {
2926   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2927 };
2928 static const char *intel_names8rex[] = {
2929   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2930   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2931 };
2932 static const char *intel_names_seg[] = {
2933   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2934 };
2935 static const char *intel_index64 = "riz";
2936 static const char *intel_index32 = "eiz";
2937 static const char *intel_index16[] = {
2938   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2939 };
2940
2941 static const char *att_names64[] = {
2942   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2943   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2944 };
2945 static const char *att_names32[] = {
2946   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2947   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2948 };
2949 static const char *att_names16[] = {
2950   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2951   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2952 };
2953 static const char *att_names8[] = {
2954   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2955 };
2956 static const char *att_names8rex[] = {
2957   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2958   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2959 };
2960 static const char *att_names_seg[] = {
2961   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2962 };
2963 static const char *att_index64 = "%riz";
2964 static const char *att_index32 = "%eiz";
2965 static const char *att_index16[] = {
2966   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2967 };
2968
2969 static const char **names_mm;
2970 static const char *intel_names_mm[] = {
2971   "mm0", "mm1", "mm2", "mm3",
2972   "mm4", "mm5", "mm6", "mm7"
2973 };
2974 static const char *att_names_mm[] = {
2975   "%mm0", "%mm1", "%mm2", "%mm3",
2976   "%mm4", "%mm5", "%mm6", "%mm7"
2977 };
2978
2979 static const char *intel_names_bnd[] = {
2980   "bnd0", "bnd1", "bnd2", "bnd3"
2981 };
2982
2983 static const char *att_names_bnd[] = {
2984   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
2985 };
2986
2987 static const char **names_xmm;
2988 static const char *intel_names_xmm[] = {
2989   "xmm0", "xmm1", "xmm2", "xmm3",
2990   "xmm4", "xmm5", "xmm6", "xmm7",
2991   "xmm8", "xmm9", "xmm10", "xmm11",
2992   "xmm12", "xmm13", "xmm14", "xmm15",
2993   "xmm16", "xmm17", "xmm18", "xmm19",
2994   "xmm20", "xmm21", "xmm22", "xmm23",
2995   "xmm24", "xmm25", "xmm26", "xmm27",
2996   "xmm28", "xmm29", "xmm30", "xmm31"
2997 };
2998 static const char *att_names_xmm[] = {
2999   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3000   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3001   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3002   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3003   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3004   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3005   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3006   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3007 };
3008
3009 static const char **names_ymm;
3010 static const char *intel_names_ymm[] = {
3011   "ymm0", "ymm1", "ymm2", "ymm3",
3012   "ymm4", "ymm5", "ymm6", "ymm7",
3013   "ymm8", "ymm9", "ymm10", "ymm11",
3014   "ymm12", "ymm13", "ymm14", "ymm15",
3015   "ymm16", "ymm17", "ymm18", "ymm19",
3016   "ymm20", "ymm21", "ymm22", "ymm23",
3017   "ymm24", "ymm25", "ymm26", "ymm27",
3018   "ymm28", "ymm29", "ymm30", "ymm31"
3019 };
3020 static const char *att_names_ymm[] = {
3021   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3022   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3023   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3024   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3025   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3026   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3027   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3028   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3029 };
3030
3031 static const char **names_zmm;
3032 static const char *intel_names_zmm[] = {
3033   "zmm0", "zmm1", "zmm2", "zmm3",
3034   "zmm4", "zmm5", "zmm6", "zmm7",
3035   "zmm8", "zmm9", "zmm10", "zmm11",
3036   "zmm12", "zmm13", "zmm14", "zmm15",
3037   "zmm16", "zmm17", "zmm18", "zmm19",
3038   "zmm20", "zmm21", "zmm22", "zmm23",
3039   "zmm24", "zmm25", "zmm26", "zmm27",
3040   "zmm28", "zmm29", "zmm30", "zmm31"
3041 };
3042 static const char *att_names_zmm[] = {
3043   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3044   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3045   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3046   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3047   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3048   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3049   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3050   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3051 };
3052
3053 static const char **names_mask;
3054 static const char *intel_names_mask[] = {
3055   "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3056 };
3057 static const char *att_names_mask[] = {
3058   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3059 };
3060
3061 static const char *names_rounding[] =
3062 {
3063   "{rn-sae}",
3064   "{rd-sae}",
3065   "{ru-sae}",
3066   "{rz-sae}"
3067 };
3068
3069 static const struct dis386 reg_table[][8] = {
3070   /* REG_80 */
3071   {
3072     { "addA",   { Ebh1, Ib } },
3073     { "orA",    { Ebh1, Ib } },
3074     { "adcA",   { Ebh1, Ib } },
3075     { "sbbA",   { Ebh1, Ib } },
3076     { "andA",   { Ebh1, Ib } },
3077     { "subA",   { Ebh1, Ib } },
3078     { "xorA",   { Ebh1, Ib } },
3079     { "cmpA",   { Eb, Ib } },
3080   },
3081   /* REG_81 */
3082   {
3083     { "addQ",   { Evh1, Iv } },
3084     { "orQ",    { Evh1, Iv } },
3085     { "adcQ",   { Evh1, Iv } },
3086     { "sbbQ",   { Evh1, Iv } },
3087     { "andQ",   { Evh1, Iv } },
3088     { "subQ",   { Evh1, Iv } },
3089     { "xorQ",   { Evh1, Iv } },
3090     { "cmpQ",   { Ev, Iv } },
3091   },
3092   /* REG_82 */
3093   {
3094     { "addQ",   { Evh1, sIb } },
3095     { "orQ",    { Evh1, sIb } },
3096     { "adcQ",   { Evh1, sIb } },
3097     { "sbbQ",   { Evh1, sIb } },
3098     { "andQ",   { Evh1, sIb } },
3099     { "subQ",   { Evh1, sIb } },
3100     { "xorQ",   { Evh1, sIb } },
3101     { "cmpQ",   { Ev, sIb } },
3102   },
3103   /* REG_8F */
3104   {
3105     { "popU",   { stackEv } },
3106     { XOP_8F_TABLE (XOP_09) },
3107     { Bad_Opcode },
3108     { Bad_Opcode },
3109     { Bad_Opcode },
3110     { XOP_8F_TABLE (XOP_09) },
3111   },
3112   /* REG_C0 */
3113   {
3114     { "rolA",   { Eb, Ib } },
3115     { "rorA",   { Eb, Ib } },
3116     { "rclA",   { Eb, Ib } },
3117     { "rcrA",   { Eb, Ib } },
3118     { "shlA",   { Eb, Ib } },
3119     { "shrA",   { Eb, Ib } },
3120     { Bad_Opcode },
3121     { "sarA",   { Eb, Ib } },
3122   },
3123   /* REG_C1 */
3124   {
3125     { "rolQ",   { Ev, Ib } },
3126     { "rorQ",   { Ev, Ib } },
3127     { "rclQ",   { Ev, Ib } },
3128     { "rcrQ",   { Ev, Ib } },
3129     { "shlQ",   { Ev, Ib } },
3130     { "shrQ",   { Ev, Ib } },
3131     { Bad_Opcode },
3132     { "sarQ",   { Ev, Ib } },
3133   },
3134   /* REG_C6 */
3135   {
3136     { "movA",   { Ebh3, Ib } },
3137     { Bad_Opcode },
3138     { Bad_Opcode },
3139     { Bad_Opcode },
3140     { Bad_Opcode },
3141     { Bad_Opcode },
3142     { Bad_Opcode },
3143     { MOD_TABLE (MOD_C6_REG_7) },
3144   },
3145   /* REG_C7 */
3146   {
3147     { "movQ",   { Evh3, Iv } },
3148     { Bad_Opcode },
3149     { Bad_Opcode },
3150     { Bad_Opcode },
3151     { Bad_Opcode },
3152     { Bad_Opcode },
3153     { Bad_Opcode },
3154     { MOD_TABLE (MOD_C7_REG_7) },
3155   },
3156   /* REG_D0 */
3157   {
3158     { "rolA",   { Eb, I1 } },
3159     { "rorA",   { Eb, I1 } },
3160     { "rclA",   { Eb, I1 } },
3161     { "rcrA",   { Eb, I1 } },
3162     { "shlA",   { Eb, I1 } },
3163     { "shrA",   { Eb, I1 } },
3164     { Bad_Opcode },
3165     { "sarA",   { Eb, I1 } },
3166   },
3167   /* REG_D1 */
3168   {
3169     { "rolQ",   { Ev, I1 } },
3170     { "rorQ",   { Ev, I1 } },
3171     { "rclQ",   { Ev, I1 } },
3172     { "rcrQ",   { Ev, I1 } },
3173     { "shlQ",   { Ev, I1 } },
3174     { "shrQ",   { Ev, I1 } },
3175     { Bad_Opcode },
3176     { "sarQ",   { Ev, I1 } },
3177   },
3178   /* REG_D2 */
3179   {
3180     { "rolA",   { Eb, CL } },
3181     { "rorA",   { Eb, CL } },
3182     { "rclA",   { Eb, CL } },
3183     { "rcrA",   { Eb, CL } },
3184     { "shlA",   { Eb, CL } },
3185     { "shrA",   { Eb, CL } },
3186     { Bad_Opcode },
3187     { "sarA",   { Eb, CL } },
3188   },
3189   /* REG_D3 */
3190   {
3191     { "rolQ",   { Ev, CL } },
3192     { "rorQ",   { Ev, CL } },
3193     { "rclQ",   { Ev, CL } },
3194     { "rcrQ",   { Ev, CL } },
3195     { "shlQ",   { Ev, CL } },
3196     { "shrQ",   { Ev, CL } },
3197     { Bad_Opcode },
3198     { "sarQ",   { Ev, CL } },
3199   },
3200   /* REG_F6 */
3201   {
3202     { "testA",  { Eb, Ib } },
3203     { Bad_Opcode },
3204     { "notA",   { Ebh1 } },
3205     { "negA",   { Ebh1 } },
3206     { "mulA",   { Eb } },       /* Don't print the implicit %al register,  */
3207     { "imulA",  { Eb } },       /* to distinguish these opcodes from other */
3208     { "divA",   { Eb } },       /* mul/imul opcodes.  Do the same for div  */
3209     { "idivA",  { Eb } },       /* and idiv for consistency.               */
3210   },
3211   /* REG_F7 */
3212   {
3213     { "testQ",  { Ev, Iv } },
3214     { Bad_Opcode },
3215     { "notQ",   { Evh1 } },
3216     { "negQ",   { Evh1 } },
3217     { "mulQ",   { Ev } },       /* Don't print the implicit register.  */
3218     { "imulQ",  { Ev } },
3219     { "divQ",   { Ev } },
3220     { "idivQ",  { Ev } },
3221   },
3222   /* REG_FE */
3223   {
3224     { "incA",   { Ebh1 } },
3225     { "decA",   { Ebh1 } },
3226   },
3227   /* REG_FF */
3228   {
3229     { "incQ",   { Evh1 } },
3230     { "decQ",   { Evh1 } },
3231     { "call{T|}", { indirEv, BND } },
3232     { "Jcall{T|}", { indirEp } },
3233     { "jmp{T|}", { indirEv, BND } },
3234     { "Jjmp{T|}", { indirEp } },
3235     { "pushU",  { stackEv } },
3236     { Bad_Opcode },
3237   },
3238   /* REG_0F00 */
3239   {
3240     { "sldtD",  { Sv } },
3241     { "strD",   { Sv } },
3242     { "lldt",   { Ew } },
3243     { "ltr",    { Ew } },
3244     { "verr",   { Ew } },
3245     { "verw",   { Ew } },
3246     { Bad_Opcode },
3247     { Bad_Opcode },
3248   },
3249   /* REG_0F01 */
3250   {
3251     { MOD_TABLE (MOD_0F01_REG_0) },
3252     { MOD_TABLE (MOD_0F01_REG_1) },
3253     { MOD_TABLE (MOD_0F01_REG_2) },
3254     { MOD_TABLE (MOD_0F01_REG_3) },
3255     { "smswD",  { Sv } },
3256     { Bad_Opcode },
3257     { "lmsw",   { Ew } },
3258     { MOD_TABLE (MOD_0F01_REG_7) },
3259   },
3260   /* REG_0F0D */
3261   {
3262     { "prefetch",       { Mb } },
3263     { "prefetchw",      { Mb } },
3264     { "prefetchwt1",    { Mb } },
3265     { "prefetch",       { Mb } },
3266     { "prefetch",       { Mb } },
3267     { "prefetch",       { Mb } },
3268     { "prefetch",       { Mb } },
3269     { "prefetch",       { Mb } },
3270   },
3271   /* REG_0F18 */
3272   {
3273     { MOD_TABLE (MOD_0F18_REG_0) },
3274     { MOD_TABLE (MOD_0F18_REG_1) },
3275     { MOD_TABLE (MOD_0F18_REG_2) },
3276     { MOD_TABLE (MOD_0F18_REG_3) },
3277     { MOD_TABLE (MOD_0F18_REG_4) },
3278     { MOD_TABLE (MOD_0F18_REG_5) },
3279     { MOD_TABLE (MOD_0F18_REG_6) },
3280     { MOD_TABLE (MOD_0F18_REG_7) },
3281   },
3282   /* REG_0F71 */
3283   {
3284     { Bad_Opcode },
3285     { Bad_Opcode },
3286     { MOD_TABLE (MOD_0F71_REG_2) },
3287     { Bad_Opcode },
3288     { MOD_TABLE (MOD_0F71_REG_4) },
3289     { Bad_Opcode },
3290     { MOD_TABLE (MOD_0F71_REG_6) },
3291   },
3292   /* REG_0F72 */
3293   {
3294     { Bad_Opcode },
3295     { Bad_Opcode },
3296     { MOD_TABLE (MOD_0F72_REG_2) },
3297     { Bad_Opcode },
3298     { MOD_TABLE (MOD_0F72_REG_4) },
3299     { Bad_Opcode },
3300     { MOD_TABLE (MOD_0F72_REG_6) },
3301   },
3302   /* REG_0F73 */
3303   {
3304     { Bad_Opcode },
3305     { Bad_Opcode },
3306     { MOD_TABLE (MOD_0F73_REG_2) },
3307     { MOD_TABLE (MOD_0F73_REG_3) },
3308     { Bad_Opcode },
3309     { Bad_Opcode },
3310     { MOD_TABLE (MOD_0F73_REG_6) },
3311     { MOD_TABLE (MOD_0F73_REG_7) },
3312   },
3313   /* REG_0FA6 */
3314   {
3315     { "montmul",        { { OP_0f07, 0 } } },
3316     { "xsha1",          { { OP_0f07, 0 } } },
3317     { "xsha256",        { { OP_0f07, 0 } } },
3318   },
3319   /* REG_0FA7 */
3320   {
3321     { "xstore-rng",     { { OP_0f07, 0 } } },
3322     { "xcrypt-ecb",     { { OP_0f07, 0 } } },
3323     { "xcrypt-cbc",     { { OP_0f07, 0 } } },
3324     { "xcrypt-ctr",     { { OP_0f07, 0 } } },
3325     { "xcrypt-cfb",     { { OP_0f07, 0 } } },
3326     { "xcrypt-ofb",     { { OP_0f07, 0 } } },
3327   },
3328   /* REG_0FAE */
3329   {
3330     { MOD_TABLE (MOD_0FAE_REG_0) },
3331     { MOD_TABLE (MOD_0FAE_REG_1) },
3332     { MOD_TABLE (MOD_0FAE_REG_2) },
3333     { MOD_TABLE (MOD_0FAE_REG_3) },
3334     { MOD_TABLE (MOD_0FAE_REG_4) },
3335     { MOD_TABLE (MOD_0FAE_REG_5) },
3336     { MOD_TABLE (MOD_0FAE_REG_6) },
3337     { MOD_TABLE (MOD_0FAE_REG_7) },
3338   },
3339   /* REG_0FBA */
3340   {
3341     { Bad_Opcode },
3342     { Bad_Opcode },
3343     { Bad_Opcode },
3344     { Bad_Opcode },
3345     { "btQ",    { Ev, Ib } },
3346     { "btsQ",   { Evh1, Ib } },
3347     { "btrQ",   { Evh1, Ib } },
3348     { "btcQ",   { Evh1, Ib } },
3349   },
3350   /* REG_0FC7 */
3351   {
3352     { Bad_Opcode },
3353     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } },
3354     { Bad_Opcode },
3355     { Bad_Opcode },
3356     { Bad_Opcode },
3357     { Bad_Opcode },
3358     { MOD_TABLE (MOD_0FC7_REG_6) },
3359     { MOD_TABLE (MOD_0FC7_REG_7) },
3360   },
3361   /* REG_VEX_0F71 */
3362   {
3363     { Bad_Opcode },
3364     { Bad_Opcode },
3365     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3366     { Bad_Opcode },
3367     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3368     { Bad_Opcode },
3369     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3370   },
3371   /* REG_VEX_0F72 */
3372   {
3373     { Bad_Opcode },
3374     { Bad_Opcode },
3375     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3376     { Bad_Opcode },
3377     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3378     { Bad_Opcode },
3379     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3380   },
3381   /* REG_VEX_0F73 */
3382   {
3383     { Bad_Opcode },
3384     { Bad_Opcode },
3385     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3386     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3387     { Bad_Opcode },
3388     { Bad_Opcode },
3389     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3390     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3391   },
3392   /* REG_VEX_0FAE */
3393   {
3394     { Bad_Opcode },
3395     { Bad_Opcode },
3396     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3397     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3398   },
3399   /* REG_VEX_0F38F3 */
3400   {
3401     { Bad_Opcode },
3402     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3403     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3404     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3405   },
3406   /* REG_XOP_LWPCB */
3407   {
3408     { "llwpcb", { { OP_LWPCB_E, 0 } } },
3409     { "slwpcb", { { OP_LWPCB_E, 0 } } },
3410   },
3411   /* REG_XOP_LWP */
3412   {
3413     { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq } },
3414     { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq } },
3415   },
3416   /* REG_XOP_TBM_01 */
3417   {
3418     { Bad_Opcode },
3419     { "blcfill",        { { OP_LWP_E, 0 }, Ev } },
3420     { "blsfill",        { { OP_LWP_E, 0 }, Ev } },
3421     { "blcs",   { { OP_LWP_E, 0 }, Ev } },
3422     { "tzmsk",  { { OP_LWP_E, 0 }, Ev } },
3423     { "blcic",  { { OP_LWP_E, 0 }, Ev } },
3424     { "blsic",  { { OP_LWP_E, 0 }, Ev } },
3425     { "t1mskc", { { OP_LWP_E, 0 }, Ev } },
3426   },
3427   /* REG_XOP_TBM_02 */
3428   {
3429     { Bad_Opcode },
3430     { "blcmsk", { { OP_LWP_E, 0 }, Ev } },
3431     { Bad_Opcode },
3432     { Bad_Opcode },
3433     { Bad_Opcode },
3434     { Bad_Opcode },
3435     { "blci",   { { OP_LWP_E, 0 }, Ev } },
3436   },
3437 #define NEED_REG_TABLE
3438 #include "i386-dis-evex.h"
3439 #undef NEED_REG_TABLE
3440 };
3441
3442 static const struct dis386 prefix_table[][4] = {
3443   /* PREFIX_90 */
3444   {
3445     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
3446     { "pause", { XX } },
3447     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
3448   },
3449
3450   /* PREFIX_0F10 */
3451   {
3452     { "movups", { XM, EXx } },
3453     { "movss",  { XM, EXd } },
3454     { "movupd", { XM, EXx } },
3455     { "movsd",  { XM, EXq } },
3456   },
3457
3458   /* PREFIX_0F11 */
3459   {
3460     { "movups", { EXxS, XM } },
3461     { "movss",  { EXdS, XM } },
3462     { "movupd", { EXxS, XM } },
3463     { "movsd",  { EXqS, XM } },
3464   },
3465
3466   /* PREFIX_0F12 */
3467   {
3468     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3469     { "movsldup", { XM, EXx } },
3470     { "movlpd", { XM, EXq } },
3471     { "movddup", { XM, EXq } },
3472   },
3473
3474   /* PREFIX_0F16 */
3475   {
3476     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3477     { "movshdup", { XM, EXx } },
3478     { "movhpd", { XM, EXq } },
3479   },
3480
3481   /* PREFIX_0F1A */
3482   {
3483     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3484     { "bndcl",  { Gbnd, Ev_bnd } },
3485     { "bndmov", { Gbnd, Ebnd } },
3486     { "bndcu",  { Gbnd, Ev_bnd } },
3487   },
3488
3489   /* PREFIX_0F1B */
3490   {
3491     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3492     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3493     { "bndmov", { Ebnd, Gbnd } },
3494     { "bndcn",  { Gbnd, Ev_bnd } },
3495   },
3496
3497   /* PREFIX_0F2A */
3498   {
3499     { "cvtpi2ps", { XM, EMCq } },
3500     { "cvtsi2ss%LQ", { XM, Ev } },
3501     { "cvtpi2pd", { XM, EMCq } },
3502     { "cvtsi2sd%LQ", { XM, Ev } },
3503   },
3504
3505   /* PREFIX_0F2B */
3506   {
3507     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3508     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3509     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3510     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3511   },
3512
3513   /* PREFIX_0F2C */
3514   {
3515     { "cvttps2pi", { MXC, EXq } },
3516     { "cvttss2siY", { Gv, EXd } },
3517     { "cvttpd2pi", { MXC, EXx } },
3518     { "cvttsd2siY", { Gv, EXq } },
3519   },
3520
3521   /* PREFIX_0F2D */
3522   {
3523     { "cvtps2pi", { MXC, EXq } },
3524     { "cvtss2siY", { Gv, EXd } },
3525     { "cvtpd2pi", { MXC, EXx } },
3526     { "cvtsd2siY", { Gv, EXq } },
3527   },
3528
3529   /* PREFIX_0F2E */
3530   {
3531     { "ucomiss",{ XM, EXd } },
3532     { Bad_Opcode },
3533     { "ucomisd",{ XM, EXq } },
3534   },
3535
3536   /* PREFIX_0F2F */
3537   {
3538     { "comiss", { XM, EXd } },
3539     { Bad_Opcode },
3540     { "comisd", { XM, EXq } },
3541   },
3542
3543   /* PREFIX_0F51 */
3544   {
3545     { "sqrtps", { XM, EXx } },
3546     { "sqrtss", { XM, EXd } },
3547     { "sqrtpd", { XM, EXx } },
3548     { "sqrtsd", { XM, EXq } },
3549   },
3550
3551   /* PREFIX_0F52 */
3552   {
3553     { "rsqrtps",{ XM, EXx } },
3554     { "rsqrtss",{ XM, EXd } },
3555   },
3556
3557   /* PREFIX_0F53 */
3558   {
3559     { "rcpps",  { XM, EXx } },
3560     { "rcpss",  { XM, EXd } },
3561   },
3562
3563   /* PREFIX_0F58 */
3564   {
3565     { "addps", { XM, EXx } },
3566     { "addss", { XM, EXd } },
3567     { "addpd", { XM, EXx } },
3568     { "addsd", { XM, EXq } },
3569   },
3570
3571   /* PREFIX_0F59 */
3572   {
3573     { "mulps",  { XM, EXx } },
3574     { "mulss",  { XM, EXd } },
3575     { "mulpd",  { XM, EXx } },
3576     { "mulsd",  { XM, EXq } },
3577   },
3578
3579   /* PREFIX_0F5A */
3580   {
3581     { "cvtps2pd", { XM, EXq } },
3582     { "cvtss2sd", { XM, EXd } },
3583     { "cvtpd2ps", { XM, EXx } },
3584     { "cvtsd2ss", { XM, EXq } },
3585   },
3586
3587   /* PREFIX_0F5B */
3588   {
3589     { "cvtdq2ps", { XM, EXx } },
3590     { "cvttps2dq", { XM, EXx } },
3591     { "cvtps2dq", { XM, EXx } },
3592   },
3593
3594   /* PREFIX_0F5C */
3595   {
3596     { "subps",  { XM, EXx } },
3597     { "subss",  { XM, EXd } },
3598     { "subpd",  { XM, EXx } },
3599     { "subsd",  { XM, EXq } },
3600   },
3601
3602   /* PREFIX_0F5D */
3603   {
3604     { "minps",  { XM, EXx } },
3605     { "minss",  { XM, EXd } },
3606     { "minpd",  { XM, EXx } },
3607     { "minsd",  { XM, EXq } },
3608   },
3609
3610   /* PREFIX_0F5E */
3611   {
3612     { "divps",  { XM, EXx } },
3613     { "divss",  { XM, EXd } },
3614     { "divpd",  { XM, EXx } },
3615     { "divsd",  { XM, EXq } },
3616   },
3617
3618   /* PREFIX_0F5F */
3619   {
3620     { "maxps",  { XM, EXx } },
3621     { "maxss",  { XM, EXd } },
3622     { "maxpd",  { XM, EXx } },
3623     { "maxsd",  { XM, EXq } },
3624   },
3625
3626   /* PREFIX_0F60 */
3627   {
3628     { "punpcklbw",{ MX, EMd } },
3629     { Bad_Opcode },
3630     { "punpcklbw",{ MX, EMx } },
3631   },
3632
3633   /* PREFIX_0F61 */
3634   {
3635     { "punpcklwd",{ MX, EMd } },
3636     { Bad_Opcode },
3637     { "punpcklwd",{ MX, EMx } },
3638   },
3639
3640   /* PREFIX_0F62 */
3641   {
3642     { "punpckldq",{ MX, EMd } },
3643     { Bad_Opcode },
3644     { "punpckldq",{ MX, EMx } },
3645   },
3646
3647   /* PREFIX_0F6C */
3648   {
3649     { Bad_Opcode },
3650     { Bad_Opcode },
3651     { "punpcklqdq", { XM, EXx } },
3652   },
3653
3654   /* PREFIX_0F6D */
3655   {
3656     { Bad_Opcode },
3657     { Bad_Opcode },
3658     { "punpckhqdq", { XM, EXx } },
3659   },
3660
3661   /* PREFIX_0F6F */
3662   {
3663     { "movq",   { MX, EM } },
3664     { "movdqu", { XM, EXx } },
3665     { "movdqa", { XM, EXx } },
3666   },
3667
3668   /* PREFIX_0F70 */
3669   {
3670     { "pshufw", { MX, EM, Ib } },
3671     { "pshufhw",{ XM, EXx, Ib } },
3672     { "pshufd", { XM, EXx, Ib } },
3673     { "pshuflw",{ XM, EXx, Ib } },
3674   },
3675
3676   /* PREFIX_0F73_REG_3 */
3677   {
3678     { Bad_Opcode },
3679     { Bad_Opcode },
3680     { "psrldq", { XS, Ib } },
3681   },
3682
3683   /* PREFIX_0F73_REG_7 */
3684   {
3685     { Bad_Opcode },
3686     { Bad_Opcode },
3687     { "pslldq", { XS, Ib } },
3688   },
3689
3690   /* PREFIX_0F78 */
3691   {
3692     {"vmread",  { Em, Gm } },
3693     { Bad_Opcode },
3694     {"extrq",   { XS, Ib, Ib } },
3695     {"insertq", { XM, XS, Ib, Ib } },
3696   },
3697
3698   /* PREFIX_0F79 */
3699   {
3700     {"vmwrite", { Gm, Em } },
3701     { Bad_Opcode },
3702     {"extrq",   { XM, XS } },
3703     {"insertq", { XM, XS } },
3704   },
3705
3706   /* PREFIX_0F7C */
3707   {
3708     { Bad_Opcode },
3709     { Bad_Opcode },
3710     { "haddpd", { XM, EXx } },
3711     { "haddps", { XM, EXx } },
3712   },
3713
3714   /* PREFIX_0F7D */
3715   {
3716     { Bad_Opcode },
3717     { Bad_Opcode },
3718     { "hsubpd", { XM, EXx } },
3719     { "hsubps", { XM, EXx } },
3720   },
3721
3722   /* PREFIX_0F7E */
3723   {
3724     { "movK",   { Edq, MX } },
3725     { "movq",   { XM, EXq } },
3726     { "movK",   { Edq, XM } },
3727   },
3728
3729   /* PREFIX_0F7F */
3730   {
3731     { "movq",   { EMS, MX } },
3732     { "movdqu", { EXxS, XM } },
3733     { "movdqa", { EXxS, XM } },
3734   },
3735
3736   /* PREFIX_0FAE_REG_0 */
3737   {
3738     { Bad_Opcode },
3739     { "rdfsbase", { Ev } },
3740   },
3741
3742   /* PREFIX_0FAE_REG_1 */
3743   {
3744     { Bad_Opcode },
3745     { "rdgsbase", { Ev } },
3746   },
3747
3748   /* PREFIX_0FAE_REG_2 */
3749   {
3750     { Bad_Opcode },
3751     { "wrfsbase", { Ev } },
3752   },
3753
3754   /* PREFIX_0FAE_REG_3 */
3755   {
3756     { Bad_Opcode },
3757     { "wrgsbase", { Ev } },
3758   },
3759
3760   /* PREFIX_0FB8 */
3761   {
3762     { Bad_Opcode },
3763     { "popcntS", { Gv, Ev } },
3764   },
3765
3766   /* PREFIX_0FBC */
3767   {
3768     { "bsfS",   { Gv, Ev } },
3769     { "tzcntS", { Gv, Ev } },
3770     { "bsfS",   { Gv, Ev } },
3771   },
3772
3773   /* PREFIX_0FBD */
3774   {
3775     { "bsrS",   { Gv, Ev } },
3776     { "lzcntS", { Gv, Ev } },
3777     { "bsrS",   { Gv, Ev } },
3778   },
3779
3780   /* PREFIX_0FC2 */
3781   {
3782     { "cmpps",  { XM, EXx, CMP } },
3783     { "cmpss",  { XM, EXd, CMP } },
3784     { "cmppd",  { XM, EXx, CMP } },
3785     { "cmpsd",  { XM, EXq, CMP } },
3786   },
3787
3788   /* PREFIX_0FC3 */
3789   {
3790     { "movntiS", { Ma, Gv } },
3791   },
3792
3793   /* PREFIX_0FC7_REG_6 */
3794   {
3795     { "vmptrld",{ Mq } },
3796     { "vmxon",  { Mq } },
3797     { "vmclear",{ Mq } },
3798   },
3799
3800   /* PREFIX_0FD0 */
3801   {
3802     { Bad_Opcode },
3803     { Bad_Opcode },
3804     { "addsubpd", { XM, EXx } },
3805     { "addsubps", { XM, EXx } },
3806   },
3807
3808   /* PREFIX_0FD6 */
3809   {
3810     { Bad_Opcode },
3811     { "movq2dq",{ XM, MS } },
3812     { "movq",   { EXqS, XM } },
3813     { "movdq2q",{ MX, XS } },
3814   },
3815
3816   /* PREFIX_0FE6 */
3817   {
3818     { Bad_Opcode },
3819     { "cvtdq2pd", { XM, EXq } },
3820     { "cvttpd2dq", { XM, EXx } },
3821     { "cvtpd2dq", { XM, EXx } },
3822   },
3823
3824   /* PREFIX_0FE7 */
3825   {
3826     { "movntq", { Mq, MX } },
3827     { Bad_Opcode },
3828     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
3829   },
3830
3831   /* PREFIX_0FF0 */
3832   {
3833     { Bad_Opcode },
3834     { Bad_Opcode },
3835     { Bad_Opcode },
3836     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
3837   },
3838
3839   /* PREFIX_0FF7 */
3840   {
3841     { "maskmovq", { MX, MS } },
3842     { Bad_Opcode },
3843     { "maskmovdqu", { XM, XS } },
3844   },
3845
3846   /* PREFIX_0F3810 */
3847   {
3848     { Bad_Opcode },
3849     { Bad_Opcode },
3850     { "pblendvb", { XM, EXx, XMM0 } },
3851   },
3852
3853   /* PREFIX_0F3814 */
3854   {
3855     { Bad_Opcode },
3856     { Bad_Opcode },
3857     { "blendvps", { XM, EXx, XMM0 } },
3858   },
3859
3860   /* PREFIX_0F3815 */
3861   {
3862     { Bad_Opcode },
3863     { Bad_Opcode },
3864     { "blendvpd", { XM, EXx, XMM0 } },
3865   },
3866
3867   /* PREFIX_0F3817 */
3868   {
3869     { Bad_Opcode },
3870     { Bad_Opcode },
3871     { "ptest",  { XM, EXx } },
3872   },
3873
3874   /* PREFIX_0F3820 */
3875   {
3876     { Bad_Opcode },
3877     { Bad_Opcode },
3878     { "pmovsxbw", { XM, EXq } },
3879   },
3880
3881   /* PREFIX_0F3821 */
3882   {
3883     { Bad_Opcode },
3884     { Bad_Opcode },
3885     { "pmovsxbd", { XM, EXd } },
3886   },
3887
3888   /* PREFIX_0F3822 */
3889   {
3890     { Bad_Opcode },
3891     { Bad_Opcode },
3892     { "pmovsxbq", { XM, EXw } },
3893   },
3894
3895   /* PREFIX_0F3823 */
3896   {
3897     { Bad_Opcode },
3898     { Bad_Opcode },
3899     { "pmovsxwd", { XM, EXq } },
3900   },
3901
3902   /* PREFIX_0F3824 */
3903   {
3904     { Bad_Opcode },
3905     { Bad_Opcode },
3906     { "pmovsxwq", { XM, EXd } },
3907   },
3908
3909   /* PREFIX_0F3825 */
3910   {
3911     { Bad_Opcode },
3912     { Bad_Opcode },
3913     { "pmovsxdq", { XM, EXq } },
3914   },
3915
3916   /* PREFIX_0F3828 */
3917   {
3918     { Bad_Opcode },
3919     { Bad_Opcode },
3920     { "pmuldq", { XM, EXx } },
3921   },
3922
3923   /* PREFIX_0F3829 */
3924   {
3925     { Bad_Opcode },
3926     { Bad_Opcode },
3927     { "pcmpeqq", { XM, EXx } },
3928   },
3929
3930   /* PREFIX_0F382A */
3931   {
3932     { Bad_Opcode },
3933     { Bad_Opcode },
3934     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
3935   },
3936
3937   /* PREFIX_0F382B */
3938   {
3939     { Bad_Opcode },
3940     { Bad_Opcode },
3941     { "packusdw", { XM, EXx } },
3942   },
3943
3944   /* PREFIX_0F3830 */
3945   {
3946     { Bad_Opcode },
3947     { Bad_Opcode },
3948     { "pmovzxbw", { XM, EXq } },
3949   },
3950
3951   /* PREFIX_0F3831 */
3952   {
3953     { Bad_Opcode },
3954     { Bad_Opcode },
3955     { "pmovzxbd", { XM, EXd } },
3956   },
3957
3958   /* PREFIX_0F3832 */
3959   {
3960     { Bad_Opcode },
3961     { Bad_Opcode },
3962     { "pmovzxbq", { XM, EXw } },
3963   },
3964
3965   /* PREFIX_0F3833 */
3966   {
3967     { Bad_Opcode },
3968     { Bad_Opcode },
3969     { "pmovzxwd", { XM, EXq } },
3970   },
3971
3972   /* PREFIX_0F3834 */
3973   {
3974     { Bad_Opcode },
3975     { Bad_Opcode },
3976     { "pmovzxwq", { XM, EXd } },
3977   },
3978
3979   /* PREFIX_0F3835 */
3980   {
3981     { Bad_Opcode },
3982     { Bad_Opcode },
3983     { "pmovzxdq", { XM, EXq } },
3984   },
3985
3986   /* PREFIX_0F3837 */
3987   {
3988     { Bad_Opcode },
3989     { Bad_Opcode },
3990     { "pcmpgtq", { XM, EXx } },
3991   },
3992
3993   /* PREFIX_0F3838 */
3994   {
3995     { Bad_Opcode },
3996     { Bad_Opcode },
3997     { "pminsb", { XM, EXx } },
3998   },
3999
4000   /* PREFIX_0F3839 */
4001   {
4002     { Bad_Opcode },
4003     { Bad_Opcode },
4004     { "pminsd", { XM, EXx } },
4005   },
4006
4007   /* PREFIX_0F383A */
4008   {
4009     { Bad_Opcode },
4010     { Bad_Opcode },
4011     { "pminuw", { XM, EXx } },
4012   },
4013
4014   /* PREFIX_0F383B */
4015   {
4016     { Bad_Opcode },
4017     { Bad_Opcode },
4018     { "pminud", { XM, EXx } },
4019   },
4020
4021   /* PREFIX_0F383C */
4022   {
4023     { Bad_Opcode },
4024     { Bad_Opcode },
4025     { "pmaxsb", { XM, EXx } },
4026   },
4027
4028   /* PREFIX_0F383D */
4029   {
4030     { Bad_Opcode },
4031     { Bad_Opcode },
4032     { "pmaxsd", { XM, EXx } },
4033   },
4034
4035   /* PREFIX_0F383E */
4036   {
4037     { Bad_Opcode },
4038     { Bad_Opcode },
4039     { "pmaxuw", { XM, EXx } },
4040   },
4041
4042   /* PREFIX_0F383F */
4043   {
4044     { Bad_Opcode },
4045     { Bad_Opcode },
4046     { "pmaxud", { XM, EXx } },
4047   },
4048
4049   /* PREFIX_0F3840 */
4050   {
4051     { Bad_Opcode },
4052     { Bad_Opcode },
4053     { "pmulld", { XM, EXx } },
4054   },
4055
4056   /* PREFIX_0F3841 */
4057   {
4058     { Bad_Opcode },
4059     { Bad_Opcode },
4060     { "phminposuw", { XM, EXx } },
4061   },
4062
4063   /* PREFIX_0F3880 */
4064   {
4065     { Bad_Opcode },
4066     { Bad_Opcode },
4067     { "invept", { Gm, Mo } },
4068   },
4069
4070   /* PREFIX_0F3881 */
4071   {
4072     { Bad_Opcode },
4073     { Bad_Opcode },
4074     { "invvpid", { Gm, Mo } },
4075   },
4076
4077   /* PREFIX_0F3882 */
4078   {
4079     { Bad_Opcode },
4080     { Bad_Opcode },
4081     { "invpcid", { Gm, M } },
4082   },
4083
4084   /* PREFIX_0F38C8 */
4085   {
4086     { "sha1nexte", { XM, EXxmm } },
4087   },
4088
4089   /* PREFIX_0F38C9 */
4090   {
4091     { "sha1msg1", { XM, EXxmm } },
4092   },
4093
4094   /* PREFIX_0F38CA */
4095   {
4096     { "sha1msg2", { XM, EXxmm } },
4097   },
4098
4099   /* PREFIX_0F38CB */
4100   {
4101     { "sha256rnds2", { XM, EXxmm, XMM0 } },
4102   },
4103
4104   /* PREFIX_0F38CC */
4105   {
4106     { "sha256msg1", { XM, EXxmm } },
4107   },
4108
4109   /* PREFIX_0F38CD */
4110   {
4111     { "sha256msg2", { XM, EXxmm } },
4112   },
4113
4114   /* PREFIX_0F38DB */
4115   {
4116     { Bad_Opcode },
4117     { Bad_Opcode },
4118     { "aesimc", { XM, EXx } },
4119   },
4120
4121   /* PREFIX_0F38DC */
4122   {
4123     { Bad_Opcode },
4124     { Bad_Opcode },
4125     { "aesenc", { XM, EXx } },
4126   },
4127
4128   /* PREFIX_0F38DD */
4129   {
4130     { Bad_Opcode },
4131     { Bad_Opcode },
4132     { "aesenclast", { XM, EXx } },
4133   },
4134
4135   /* PREFIX_0F38DE */
4136   {
4137     { Bad_Opcode },
4138     { Bad_Opcode },
4139     { "aesdec", { XM, EXx } },
4140   },
4141
4142   /* PREFIX_0F38DF */
4143   {
4144     { Bad_Opcode },
4145     { Bad_Opcode },
4146     { "aesdeclast", { XM, EXx } },
4147   },
4148
4149   /* PREFIX_0F38F0 */
4150   {
4151     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
4152     { Bad_Opcode },
4153     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
4154     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } } },
4155   },
4156
4157   /* PREFIX_0F38F1 */
4158   {
4159     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
4160     { Bad_Opcode },
4161     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
4162     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } } },
4163   },
4164
4165   /* PREFIX_0F38F6 */
4166   {
4167     { Bad_Opcode },
4168     { "adoxS",  { Gdq, Edq} },
4169     { "adcxS",  { Gdq, Edq} },
4170     { Bad_Opcode },
4171   },
4172
4173   /* PREFIX_0F3A08 */
4174   {
4175     { Bad_Opcode },
4176     { Bad_Opcode },
4177     { "roundps", { XM, EXx, Ib } },
4178   },
4179
4180   /* PREFIX_0F3A09 */
4181   {
4182     { Bad_Opcode },
4183     { Bad_Opcode },
4184     { "roundpd", { XM, EXx, Ib } },
4185   },
4186
4187   /* PREFIX_0F3A0A */
4188   {
4189     { Bad_Opcode },
4190     { Bad_Opcode },
4191     { "roundss", { XM, EXd, Ib } },
4192   },
4193
4194   /* PREFIX_0F3A0B */
4195   {
4196     { Bad_Opcode },
4197     { Bad_Opcode },
4198     { "roundsd", { XM, EXq, Ib } },
4199   },
4200
4201   /* PREFIX_0F3A0C */
4202   {
4203     { Bad_Opcode },
4204     { Bad_Opcode },
4205     { "blendps", { XM, EXx, Ib } },
4206   },
4207
4208   /* PREFIX_0F3A0D */
4209   {
4210     { Bad_Opcode },
4211     { Bad_Opcode },
4212     { "blendpd", { XM, EXx, Ib } },
4213   },
4214
4215   /* PREFIX_0F3A0E */
4216   {
4217     { Bad_Opcode },
4218     { Bad_Opcode },
4219     { "pblendw", { XM, EXx, Ib } },
4220   },
4221
4222   /* PREFIX_0F3A14 */
4223   {
4224     { Bad_Opcode },
4225     { Bad_Opcode },
4226     { "pextrb", { Edqb, XM, Ib } },
4227   },
4228
4229   /* PREFIX_0F3A15 */
4230   {
4231     { Bad_Opcode },
4232     { Bad_Opcode },
4233     { "pextrw", { Edqw, XM, Ib } },
4234   },
4235
4236   /* PREFIX_0F3A16 */
4237   {
4238     { Bad_Opcode },
4239     { Bad_Opcode },
4240     { "pextrK", { Edq, XM, Ib } },
4241   },
4242
4243   /* PREFIX_0F3A17 */
4244   {
4245     { Bad_Opcode },
4246     { Bad_Opcode },
4247     { "extractps", { Edqd, XM, Ib } },
4248   },
4249
4250   /* PREFIX_0F3A20 */
4251   {
4252     { Bad_Opcode },
4253     { Bad_Opcode },
4254     { "pinsrb", { XM, Edqb, Ib } },
4255   },
4256
4257   /* PREFIX_0F3A21 */
4258   {
4259     { Bad_Opcode },
4260     { Bad_Opcode },
4261     { "insertps", { XM, EXd, Ib } },
4262   },
4263
4264   /* PREFIX_0F3A22 */
4265   {
4266     { Bad_Opcode },
4267     { Bad_Opcode },
4268     { "pinsrK", { XM, Edq, Ib } },
4269   },
4270
4271   /* PREFIX_0F3A40 */
4272   {
4273     { Bad_Opcode },
4274     { Bad_Opcode },
4275     { "dpps",   { XM, EXx, Ib } },
4276   },
4277
4278   /* PREFIX_0F3A41 */
4279   {
4280     { Bad_Opcode },
4281     { Bad_Opcode },
4282     { "dppd",   { XM, EXx, Ib } },
4283   },
4284
4285   /* PREFIX_0F3A42 */
4286   {
4287     { Bad_Opcode },
4288     { Bad_Opcode },
4289     { "mpsadbw", { XM, EXx, Ib } },
4290   },
4291
4292   /* PREFIX_0F3A44 */
4293   {
4294     { Bad_Opcode },
4295     { Bad_Opcode },
4296     { "pclmulqdq", { XM, EXx, PCLMUL } },
4297   },
4298
4299   /* PREFIX_0F3A60 */
4300   {
4301     { Bad_Opcode },
4302     { Bad_Opcode },
4303     { "pcmpestrm", { XM, EXx, Ib } },
4304   },
4305
4306   /* PREFIX_0F3A61 */
4307   {
4308     { Bad_Opcode },
4309     { Bad_Opcode },
4310     { "pcmpestri", { XM, EXx, Ib } },
4311   },
4312
4313   /* PREFIX_0F3A62 */
4314   {
4315     { Bad_Opcode },
4316     { Bad_Opcode },
4317     { "pcmpistrm", { XM, EXx, Ib } },
4318   },
4319
4320   /* PREFIX_0F3A63 */
4321   {
4322     { Bad_Opcode },
4323     { Bad_Opcode },
4324     { "pcmpistri", { XM, EXx, Ib } },
4325   },
4326
4327   /* PREFIX_0F3ACC */
4328   {
4329     { "sha1rnds4", { XM, EXxmm, Ib } },
4330   },
4331
4332   /* PREFIX_0F3ADF */
4333   {
4334     { Bad_Opcode },
4335     { Bad_Opcode },
4336     { "aeskeygenassist", { XM, EXx, Ib } },
4337   },
4338
4339   /* PREFIX_VEX_0F10 */
4340   {
4341     { VEX_W_TABLE (VEX_W_0F10_P_0) },
4342     { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) },
4343     { VEX_W_TABLE (VEX_W_0F10_P_2) },
4344     { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) },
4345   },
4346
4347   /* PREFIX_VEX_0F11 */
4348   {
4349     { VEX_W_TABLE (VEX_W_0F11_P_0) },
4350     { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) },
4351     { VEX_W_TABLE (VEX_W_0F11_P_2) },
4352     { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) },
4353   },
4354
4355   /* PREFIX_VEX_0F12 */
4356   {
4357     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4358     { VEX_W_TABLE (VEX_W_0F12_P_1) },
4359     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
4360     { VEX_W_TABLE (VEX_W_0F12_P_3) },
4361   },
4362
4363   /* PREFIX_VEX_0F16 */
4364   {
4365     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4366     { VEX_W_TABLE (VEX_W_0F16_P_1) },
4367     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
4368   },
4369
4370   /* PREFIX_VEX_0F2A */
4371   {
4372     { Bad_Opcode },
4373     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) },
4374     { Bad_Opcode },
4375     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) },
4376   },
4377
4378   /* PREFIX_VEX_0F2C */
4379   {
4380     { Bad_Opcode },
4381     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) },
4382     { Bad_Opcode },
4383     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) },
4384   },
4385
4386   /* PREFIX_VEX_0F2D */
4387   {
4388     { Bad_Opcode },
4389     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) },
4390     { Bad_Opcode },
4391     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) },
4392   },
4393
4394   /* PREFIX_VEX_0F2E */
4395   {
4396     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) },
4397     { Bad_Opcode },
4398     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) },
4399   },
4400
4401   /* PREFIX_VEX_0F2F */
4402   {
4403     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) },
4404     { Bad_Opcode },
4405     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) },
4406   },
4407
4408   /* PREFIX_VEX_0F41 */
4409   {
4410     { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4411   },
4412
4413   /* PREFIX_VEX_0F42 */
4414   {
4415     { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4416   },
4417
4418   /* PREFIX_VEX_0F44 */
4419   {
4420     { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4421   },
4422
4423   /* PREFIX_VEX_0F45 */
4424   {
4425     { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4426   },
4427
4428   /* PREFIX_VEX_0F46 */
4429   {
4430     { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4431   },
4432
4433   /* PREFIX_VEX_0F47 */
4434   {
4435     { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4436   },
4437
4438   /* PREFIX_VEX_0F4B */
4439   {
4440     { Bad_Opcode },
4441     { Bad_Opcode },
4442     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4443   },
4444
4445   /* PREFIX_VEX_0F51 */
4446   {
4447     { VEX_W_TABLE (VEX_W_0F51_P_0) },
4448     { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) },
4449     { VEX_W_TABLE (VEX_W_0F51_P_2) },
4450     { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) },
4451   },
4452
4453   /* PREFIX_VEX_0F52 */
4454   {
4455     { VEX_W_TABLE (VEX_W_0F52_P_0) },
4456     { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) },
4457   },
4458
4459   /* PREFIX_VEX_0F53 */
4460   {
4461     { VEX_W_TABLE (VEX_W_0F53_P_0) },
4462     { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) },
4463   },
4464
4465   /* PREFIX_VEX_0F58 */
4466   {
4467     { VEX_W_TABLE (VEX_W_0F58_P_0) },
4468     { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) },
4469     { VEX_W_TABLE (VEX_W_0F58_P_2) },
4470     { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) },
4471   },
4472
4473   /* PREFIX_VEX_0F59 */
4474   {
4475     { VEX_W_TABLE (VEX_W_0F59_P_0) },
4476     { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) },
4477     { VEX_W_TABLE (VEX_W_0F59_P_2) },
4478     { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) },
4479   },
4480
4481   /* PREFIX_VEX_0F5A */
4482   {
4483     { VEX_W_TABLE (VEX_W_0F5A_P_0) },
4484     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) },
4485     { "vcvtpd2ps%XY", { XMM, EXx } },
4486     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) },
4487   },
4488
4489   /* PREFIX_VEX_0F5B */
4490   {
4491     { VEX_W_TABLE (VEX_W_0F5B_P_0) },
4492     { VEX_W_TABLE (VEX_W_0F5B_P_1) },
4493     { VEX_W_TABLE (VEX_W_0F5B_P_2) },
4494   },
4495
4496   /* PREFIX_VEX_0F5C */
4497   {
4498     { VEX_W_TABLE (VEX_W_0F5C_P_0) },
4499     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) },
4500     { VEX_W_TABLE (VEX_W_0F5C_P_2) },
4501     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) },
4502   },
4503
4504   /* PREFIX_VEX_0F5D */
4505   {
4506     { VEX_W_TABLE (VEX_W_0F5D_P_0) },
4507     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) },
4508     { VEX_W_TABLE (VEX_W_0F5D_P_2) },
4509     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) },
4510   },
4511
4512   /* PREFIX_VEX_0F5E */
4513   {
4514     { VEX_W_TABLE (VEX_W_0F5E_P_0) },
4515     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) },
4516     { VEX_W_TABLE (VEX_W_0F5E_P_2) },
4517     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) },
4518   },
4519
4520   /* PREFIX_VEX_0F5F */
4521   {
4522     { VEX_W_TABLE (VEX_W_0F5F_P_0) },
4523     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) },
4524     { VEX_W_TABLE (VEX_W_0F5F_P_2) },
4525     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) },
4526   },
4527
4528   /* PREFIX_VEX_0F60 */
4529   {
4530     { Bad_Opcode },
4531     { Bad_Opcode },
4532     { VEX_W_TABLE (VEX_W_0F60_P_2) },
4533   },
4534
4535   /* PREFIX_VEX_0F61 */
4536   {
4537     { Bad_Opcode },
4538     { Bad_Opcode },
4539     { VEX_W_TABLE (VEX_W_0F61_P_2) },
4540   },
4541
4542   /* PREFIX_VEX_0F62 */
4543   {
4544     { Bad_Opcode },
4545     { Bad_Opcode },
4546     { VEX_W_TABLE (VEX_W_0F62_P_2) },
4547   },
4548
4549   /* PREFIX_VEX_0F63 */
4550   {
4551     { Bad_Opcode },
4552     { Bad_Opcode },
4553     { VEX_W_TABLE (VEX_W_0F63_P_2) },
4554   },
4555
4556   /* PREFIX_VEX_0F64 */
4557   {
4558     { Bad_Opcode },
4559     { Bad_Opcode },
4560     { VEX_W_TABLE (VEX_W_0F64_P_2) },
4561   },
4562
4563   /* PREFIX_VEX_0F65 */
4564   {
4565     { Bad_Opcode },
4566     { Bad_Opcode },
4567     { VEX_W_TABLE (VEX_W_0F65_P_2) },
4568   },
4569
4570   /* PREFIX_VEX_0F66 */
4571   {
4572     { Bad_Opcode },
4573     { Bad_Opcode },
4574     { VEX_W_TABLE (VEX_W_0F66_P_2) },
4575   },
4576
4577   /* PREFIX_VEX_0F67 */
4578   {
4579     { Bad_Opcode },
4580     { Bad_Opcode },
4581     { VEX_W_TABLE (VEX_W_0F67_P_2) },
4582   },
4583
4584   /* PREFIX_VEX_0F68 */
4585   {
4586     { Bad_Opcode },
4587     { Bad_Opcode },
4588     { VEX_W_TABLE (VEX_W_0F68_P_2) },
4589   },
4590
4591   /* PREFIX_VEX_0F69 */
4592   {
4593     { Bad_Opcode },
4594     { Bad_Opcode },
4595     { VEX_W_TABLE (VEX_W_0F69_P_2) },
4596   },
4597
4598   /* PREFIX_VEX_0F6A */
4599   {
4600     { Bad_Opcode },
4601     { Bad_Opcode },
4602     { VEX_W_TABLE (VEX_W_0F6A_P_2) },
4603   },
4604
4605   /* PREFIX_VEX_0F6B */
4606   {
4607     { Bad_Opcode },
4608     { Bad_Opcode },
4609     { VEX_W_TABLE (VEX_W_0F6B_P_2) },
4610   },
4611
4612   /* PREFIX_VEX_0F6C */
4613   {
4614     { Bad_Opcode },
4615     { Bad_Opcode },
4616     { VEX_W_TABLE (VEX_W_0F6C_P_2) },
4617   },
4618
4619   /* PREFIX_VEX_0F6D */
4620   {
4621     { Bad_Opcode },
4622     { Bad_Opcode },
4623     { VEX_W_TABLE (VEX_W_0F6D_P_2) },
4624   },
4625
4626   /* PREFIX_VEX_0F6E */
4627   {
4628     { Bad_Opcode },
4629     { Bad_Opcode },
4630     { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
4631   },
4632
4633   /* PREFIX_VEX_0F6F */
4634   {
4635     { Bad_Opcode },
4636     { VEX_W_TABLE (VEX_W_0F6F_P_1) },
4637     { VEX_W_TABLE (VEX_W_0F6F_P_2) },
4638   },
4639
4640   /* PREFIX_VEX_0F70 */
4641   {
4642     { Bad_Opcode },
4643     { VEX_W_TABLE (VEX_W_0F70_P_1) },
4644     { VEX_W_TABLE (VEX_W_0F70_P_2) },
4645     { VEX_W_TABLE (VEX_W_0F70_P_3) },
4646   },
4647
4648   /* PREFIX_VEX_0F71_REG_2 */
4649   {
4650     { Bad_Opcode },
4651     { Bad_Opcode },
4652     { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) },
4653   },
4654
4655   /* PREFIX_VEX_0F71_REG_4 */
4656   {
4657     { Bad_Opcode },
4658     { Bad_Opcode },
4659     { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) },
4660   },
4661
4662   /* PREFIX_VEX_0F71_REG_6 */
4663   {
4664     { Bad_Opcode },
4665     { Bad_Opcode },
4666     { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) },
4667   },
4668
4669   /* PREFIX_VEX_0F72_REG_2 */
4670   {
4671     { Bad_Opcode },
4672     { Bad_Opcode },
4673     { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) },
4674   },
4675
4676   /* PREFIX_VEX_0F72_REG_4 */
4677   {
4678     { Bad_Opcode },
4679     { Bad_Opcode },
4680     { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) },
4681   },
4682
4683   /* PREFIX_VEX_0F72_REG_6 */
4684   {
4685     { Bad_Opcode },
4686     { Bad_Opcode },
4687     { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) },
4688   },
4689
4690   /* PREFIX_VEX_0F73_REG_2 */
4691   {
4692     { Bad_Opcode },
4693     { Bad_Opcode },
4694     { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) },
4695   },
4696
4697   /* PREFIX_VEX_0F73_REG_3 */
4698   {
4699     { Bad_Opcode },
4700     { Bad_Opcode },
4701     { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) },
4702   },
4703
4704   /* PREFIX_VEX_0F73_REG_6 */
4705   {
4706     { Bad_Opcode },
4707     { Bad_Opcode },
4708     { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) },
4709   },
4710
4711   /* PREFIX_VEX_0F73_REG_7 */
4712   {
4713     { Bad_Opcode },
4714     { Bad_Opcode },
4715     { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) },
4716   },
4717
4718   /* PREFIX_VEX_0F74 */
4719   {
4720     { Bad_Opcode },
4721     { Bad_Opcode },
4722     { VEX_W_TABLE (VEX_W_0F74_P_2) },
4723   },
4724
4725   /* PREFIX_VEX_0F75 */
4726   {
4727     { Bad_Opcode },
4728     { Bad_Opcode },
4729     { VEX_W_TABLE (VEX_W_0F75_P_2) },
4730   },
4731
4732   /* PREFIX_VEX_0F76 */
4733   {
4734     { Bad_Opcode },
4735     { Bad_Opcode },
4736     { VEX_W_TABLE (VEX_W_0F76_P_2) },
4737   },
4738
4739   /* PREFIX_VEX_0F77 */
4740   {
4741     { VEX_W_TABLE (VEX_W_0F77_P_0) },
4742   },
4743
4744   /* PREFIX_VEX_0F7C */
4745   {
4746     { Bad_Opcode },
4747     { Bad_Opcode },
4748     { VEX_W_TABLE (VEX_W_0F7C_P_2) },
4749     { VEX_W_TABLE (VEX_W_0F7C_P_3) },
4750   },
4751
4752   /* PREFIX_VEX_0F7D */
4753   {
4754     { Bad_Opcode },
4755     { Bad_Opcode },
4756     { VEX_W_TABLE (VEX_W_0F7D_P_2) },
4757     { VEX_W_TABLE (VEX_W_0F7D_P_3) },
4758   },
4759
4760   /* PREFIX_VEX_0F7E */
4761   {
4762     { Bad_Opcode },
4763     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
4764     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
4765   },
4766
4767   /* PREFIX_VEX_0F7F */
4768   {
4769     { Bad_Opcode },
4770     { VEX_W_TABLE (VEX_W_0F7F_P_1) },
4771     { VEX_W_TABLE (VEX_W_0F7F_P_2) },
4772   },
4773
4774   /* PREFIX_VEX_0F90 */
4775   {
4776     { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
4777   },
4778
4779   /* PREFIX_VEX_0F91 */
4780   {
4781     { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
4782   },
4783
4784   /* PREFIX_VEX_0F92 */
4785   {
4786     { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
4787   },
4788
4789   /* PREFIX_VEX_0F93 */
4790   {
4791     { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
4792   },
4793
4794   /* PREFIX_VEX_0F98 */
4795   {
4796     { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
4797   },
4798
4799   /* PREFIX_VEX_0FC2 */
4800   {
4801     { VEX_W_TABLE (VEX_W_0FC2_P_0) },
4802     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) },
4803     { VEX_W_TABLE (VEX_W_0FC2_P_2) },
4804     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) },
4805   },
4806
4807   /* PREFIX_VEX_0FC4 */
4808   {
4809     { Bad_Opcode },
4810     { Bad_Opcode },
4811     { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
4812   },
4813
4814   /* PREFIX_VEX_0FC5 */
4815   {
4816     { Bad_Opcode },
4817     { Bad_Opcode },
4818     { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
4819   },
4820
4821   /* PREFIX_VEX_0FD0 */
4822   {
4823     { Bad_Opcode },
4824     { Bad_Opcode },
4825     { VEX_W_TABLE (VEX_W_0FD0_P_2) },
4826     { VEX_W_TABLE (VEX_W_0FD0_P_3) },
4827   },
4828
4829   /* PREFIX_VEX_0FD1 */
4830   {
4831     { Bad_Opcode },
4832     { Bad_Opcode },
4833     { VEX_W_TABLE (VEX_W_0FD1_P_2) },
4834   },
4835
4836   /* PREFIX_VEX_0FD2 */
4837   {
4838     { Bad_Opcode },
4839     { Bad_Opcode },
4840     { VEX_W_TABLE (VEX_W_0FD2_P_2) },
4841   },
4842
4843   /* PREFIX_VEX_0FD3 */
4844   {
4845     { Bad_Opcode },
4846     { Bad_Opcode },
4847     { VEX_W_TABLE (VEX_W_0FD3_P_2) },
4848   },
4849
4850   /* PREFIX_VEX_0FD4 */
4851   {
4852     { Bad_Opcode },
4853     { Bad_Opcode },
4854     { VEX_W_TABLE (VEX_W_0FD4_P_2) },
4855   },
4856
4857   /* PREFIX_VEX_0FD5 */
4858   {
4859     { Bad_Opcode },
4860     { Bad_Opcode },
4861     { VEX_W_TABLE (VEX_W_0FD5_P_2) },
4862   },
4863
4864   /* PREFIX_VEX_0FD6 */
4865   {
4866     { Bad_Opcode },
4867     { Bad_Opcode },
4868     { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
4869   },
4870
4871   /* PREFIX_VEX_0FD7 */
4872   {
4873     { Bad_Opcode },
4874     { Bad_Opcode },
4875     { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
4876   },
4877
4878   /* PREFIX_VEX_0FD8 */
4879   {
4880     { Bad_Opcode },
4881     { Bad_Opcode },
4882     { VEX_W_TABLE (VEX_W_0FD8_P_2) },
4883   },
4884
4885   /* PREFIX_VEX_0FD9 */
4886   {
4887     { Bad_Opcode },
4888     { Bad_Opcode },
4889     { VEX_W_TABLE (VEX_W_0FD9_P_2) },
4890   },
4891
4892   /* PREFIX_VEX_0FDA */
4893   {
4894     { Bad_Opcode },
4895     { Bad_Opcode },
4896     { VEX_W_TABLE (VEX_W_0FDA_P_2) },
4897   },
4898
4899   /* PREFIX_VEX_0FDB */
4900   {
4901     { Bad_Opcode },
4902     { Bad_Opcode },
4903     { VEX_W_TABLE (VEX_W_0FDB_P_2) },
4904   },
4905
4906   /* PREFIX_VEX_0FDC */
4907   {
4908     { Bad_Opcode },
4909     { Bad_Opcode },
4910     { VEX_W_TABLE (VEX_W_0FDC_P_2) },
4911   },
4912
4913   /* PREFIX_VEX_0FDD */
4914   {
4915     { Bad_Opcode },
4916     { Bad_Opcode },
4917     { VEX_W_TABLE (VEX_W_0FDD_P_2) },
4918   },
4919
4920   /* PREFIX_VEX_0FDE */
4921   {
4922     { Bad_Opcode },
4923     { Bad_Opcode },
4924     { VEX_W_TABLE (VEX_W_0FDE_P_2) },
4925   },
4926
4927   /* PREFIX_VEX_0FDF */
4928   {
4929     { Bad_Opcode },
4930     { Bad_Opcode },
4931     { VEX_W_TABLE (VEX_W_0FDF_P_2) },
4932   },
4933
4934   /* PREFIX_VEX_0FE0 */
4935   {
4936     { Bad_Opcode },
4937     { Bad_Opcode },
4938     { VEX_W_TABLE (VEX_W_0FE0_P_2) },
4939   },
4940
4941   /* PREFIX_VEX_0FE1 */
4942   {
4943     { Bad_Opcode },
4944     { Bad_Opcode },
4945     { VEX_W_TABLE (VEX_W_0FE1_P_2) },
4946   },
4947
4948   /* PREFIX_VEX_0FE2 */
4949   {
4950     { Bad_Opcode },
4951     { Bad_Opcode },
4952     { VEX_W_TABLE (VEX_W_0FE2_P_2) },
4953   },
4954
4955   /* PREFIX_VEX_0FE3 */
4956   {
4957     { Bad_Opcode },
4958     { Bad_Opcode },
4959     { VEX_W_TABLE (VEX_W_0FE3_P_2) },
4960   },
4961
4962   /* PREFIX_VEX_0FE4 */
4963   {
4964     { Bad_Opcode },
4965     { Bad_Opcode },
4966     { VEX_W_TABLE (VEX_W_0FE4_P_2) },
4967   },
4968
4969   /* PREFIX_VEX_0FE5 */
4970   {
4971     { Bad_Opcode },
4972     { Bad_Opcode },
4973     { VEX_W_TABLE (VEX_W_0FE5_P_2) },
4974   },
4975
4976   /* PREFIX_VEX_0FE6 */
4977   {
4978     { Bad_Opcode },
4979     { VEX_W_TABLE (VEX_W_0FE6_P_1) },
4980     { VEX_W_TABLE (VEX_W_0FE6_P_2) },
4981     { VEX_W_TABLE (VEX_W_0FE6_P_3) },
4982   },
4983
4984   /* PREFIX_VEX_0FE7 */
4985   {
4986     { Bad_Opcode },
4987     { Bad_Opcode },
4988     { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
4989   },
4990
4991   /* PREFIX_VEX_0FE8 */
4992   {
4993     { Bad_Opcode },
4994     { Bad_Opcode },
4995     { VEX_W_TABLE (VEX_W_0FE8_P_2) },
4996   },
4997
4998   /* PREFIX_VEX_0FE9 */
4999   {
5000     { Bad_Opcode },
5001     { Bad_Opcode },
5002     { VEX_W_TABLE (VEX_W_0FE9_P_2) },
5003   },
5004
5005   /* PREFIX_VEX_0FEA */
5006   {
5007     { Bad_Opcode },
5008     { Bad_Opcode },
5009     { VEX_W_TABLE (VEX_W_0FEA_P_2) },
5010   },
5011
5012   /* PREFIX_VEX_0FEB */
5013   {
5014     { Bad_Opcode },
5015     { Bad_Opcode },
5016     { VEX_W_TABLE (VEX_W_0FEB_P_2) },
5017   },
5018
5019   /* PREFIX_VEX_0FEC */
5020   {
5021     { Bad_Opcode },
5022     { Bad_Opcode },
5023     { VEX_W_TABLE (VEX_W_0FEC_P_2) },
5024   },
5025
5026   /* PREFIX_VEX_0FED */
5027   {
5028     { Bad_Opcode },
5029     { Bad_Opcode },
5030     { VEX_W_TABLE (VEX_W_0FED_P_2) },
5031   },
5032
5033   /* PREFIX_VEX_0FEE */
5034   {
5035     { Bad_Opcode },
5036     { Bad_Opcode },
5037     { VEX_W_TABLE (VEX_W_0FEE_P_2) },
5038   },
5039
5040   /* PREFIX_VEX_0FEF */
5041   {
5042     { Bad_Opcode },
5043     { Bad_Opcode },
5044     { VEX_W_TABLE (VEX_W_0FEF_P_2) },
5045   },
5046
5047   /* PREFIX_VEX_0FF0 */
5048   {
5049     { Bad_Opcode },
5050     { Bad_Opcode },
5051     { Bad_Opcode },
5052     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5053   },
5054
5055   /* PREFIX_VEX_0FF1 */
5056   {
5057     { Bad_Opcode },
5058     { Bad_Opcode },
5059     { VEX_W_TABLE (VEX_W_0FF1_P_2) },
5060   },
5061
5062   /* PREFIX_VEX_0FF2 */
5063   {
5064     { Bad_Opcode },
5065     { Bad_Opcode },
5066     { VEX_W_TABLE (VEX_W_0FF2_P_2) },
5067   },
5068
5069   /* PREFIX_VEX_0FF3 */
5070   {
5071     { Bad_Opcode },
5072     { Bad_Opcode },
5073     { VEX_W_TABLE (VEX_W_0FF3_P_2) },
5074   },
5075
5076   /* PREFIX_VEX_0FF4 */
5077   {
5078     { Bad_Opcode },
5079     { Bad_Opcode },
5080     { VEX_W_TABLE (VEX_W_0FF4_P_2) },
5081   },
5082
5083   /* PREFIX_VEX_0FF5 */
5084   {
5085     { Bad_Opcode },
5086     { Bad_Opcode },
5087     { VEX_W_TABLE (VEX_W_0FF5_P_2) },
5088   },
5089
5090   /* PREFIX_VEX_0FF6 */
5091   {
5092     { Bad_Opcode },
5093     { Bad_Opcode },
5094     { VEX_W_TABLE (VEX_W_0FF6_P_2) },
5095   },
5096
5097   /* PREFIX_VEX_0FF7 */
5098   {
5099     { Bad_Opcode },
5100     { Bad_Opcode },
5101     { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5102   },
5103
5104   /* PREFIX_VEX_0FF8 */
5105   {
5106     { Bad_Opcode },
5107     { Bad_Opcode },
5108     { VEX_W_TABLE (VEX_W_0FF8_P_2) },
5109   },
5110
5111   /* PREFIX_VEX_0FF9 */
5112   {
5113     { Bad_Opcode },
5114     { Bad_Opcode },
5115     { VEX_W_TABLE (VEX_W_0FF9_P_2) },
5116   },
5117
5118   /* PREFIX_VEX_0FFA */
5119   {
5120     { Bad_Opcode },
5121     { Bad_Opcode },
5122     { VEX_W_TABLE (VEX_W_0FFA_P_2) },
5123   },
5124
5125   /* PREFIX_VEX_0FFB */
5126   {
5127     { Bad_Opcode },
5128     { Bad_Opcode },
5129     { VEX_W_TABLE (VEX_W_0FFB_P_2) },
5130   },
5131
5132   /* PREFIX_VEX_0FFC */
5133   {
5134     { Bad_Opcode },
5135     { Bad_Opcode },
5136     { VEX_W_TABLE (VEX_W_0FFC_P_2) },
5137   },
5138
5139   /* PREFIX_VEX_0FFD */
5140   {
5141     { Bad_Opcode },
5142     { Bad_Opcode },
5143     { VEX_W_TABLE (VEX_W_0FFD_P_2) },
5144   },
5145
5146   /* PREFIX_VEX_0FFE */
5147   {
5148     { Bad_Opcode },
5149     { Bad_Opcode },
5150     { VEX_W_TABLE (VEX_W_0FFE_P_2) },
5151   },
5152
5153   /* PREFIX_VEX_0F3800 */
5154   {
5155     { Bad_Opcode },
5156     { Bad_Opcode },
5157     { VEX_W_TABLE (VEX_W_0F3800_P_2) },
5158   },
5159
5160   /* PREFIX_VEX_0F3801 */
5161   {
5162     { Bad_Opcode },
5163     { Bad_Opcode },
5164     { VEX_W_TABLE (VEX_W_0F3801_P_2) },
5165   },
5166
5167   /* PREFIX_VEX_0F3802 */
5168   {
5169     { Bad_Opcode },
5170     { Bad_Opcode },
5171     { VEX_W_TABLE (VEX_W_0F3802_P_2) },
5172   },
5173
5174   /* PREFIX_VEX_0F3803 */
5175   {
5176     { Bad_Opcode },
5177     { Bad_Opcode },
5178     { VEX_W_TABLE (VEX_W_0F3803_P_2) },
5179   },
5180
5181   /* PREFIX_VEX_0F3804 */
5182   {
5183     { Bad_Opcode },
5184     { Bad_Opcode },
5185     { VEX_W_TABLE (VEX_W_0F3804_P_2) },
5186   },
5187
5188   /* PREFIX_VEX_0F3805 */
5189   {
5190     { Bad_Opcode },
5191     { Bad_Opcode },
5192     { VEX_W_TABLE (VEX_W_0F3805_P_2) },
5193   },
5194
5195   /* PREFIX_VEX_0F3806 */
5196   {
5197     { Bad_Opcode },
5198     { Bad_Opcode },
5199     { VEX_W_TABLE (VEX_W_0F3806_P_2) },
5200   },
5201
5202   /* PREFIX_VEX_0F3807 */
5203   {
5204     { Bad_Opcode },
5205     { Bad_Opcode },
5206     { VEX_W_TABLE (VEX_W_0F3807_P_2) },
5207   },
5208
5209   /* PREFIX_VEX_0F3808 */
5210   {
5211     { Bad_Opcode },
5212     { Bad_Opcode },
5213     { VEX_W_TABLE (VEX_W_0F3808_P_2) },
5214   },
5215
5216   /* PREFIX_VEX_0F3809 */
5217   {
5218     { Bad_Opcode },
5219     { Bad_Opcode },
5220     { VEX_W_TABLE (VEX_W_0F3809_P_2) },
5221   },
5222
5223   /* PREFIX_VEX_0F380A */
5224   {
5225     { Bad_Opcode },
5226     { Bad_Opcode },
5227     { VEX_W_TABLE (VEX_W_0F380A_P_2) },
5228   },
5229
5230   /* PREFIX_VEX_0F380B */
5231   {
5232     { Bad_Opcode },
5233     { Bad_Opcode },
5234     { VEX_W_TABLE (VEX_W_0F380B_P_2) },
5235   },
5236
5237   /* PREFIX_VEX_0F380C */
5238   {
5239     { Bad_Opcode },
5240     { Bad_Opcode },
5241     { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5242   },
5243
5244   /* PREFIX_VEX_0F380D */
5245   {
5246     { Bad_Opcode },
5247     { Bad_Opcode },
5248     { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5249   },
5250
5251   /* PREFIX_VEX_0F380E */
5252   {
5253     { Bad_Opcode },
5254     { Bad_Opcode },
5255     { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5256   },
5257
5258   /* PREFIX_VEX_0F380F */
5259   {
5260     { Bad_Opcode },
5261     { Bad_Opcode },
5262     { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5263   },
5264
5265   /* PREFIX_VEX_0F3813 */
5266   {
5267     { Bad_Opcode },
5268     { Bad_Opcode },
5269     { "vcvtph2ps", { XM, EXxmmq } },
5270   },
5271
5272   /* PREFIX_VEX_0F3816 */
5273   {
5274     { Bad_Opcode },
5275     { Bad_Opcode },
5276     { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5277   },
5278
5279   /* PREFIX_VEX_0F3817 */
5280   {
5281     { Bad_Opcode },
5282     { Bad_Opcode },
5283     { VEX_W_TABLE (VEX_W_0F3817_P_2) },
5284   },
5285
5286   /* PREFIX_VEX_0F3818 */
5287   {
5288     { Bad_Opcode },
5289     { Bad_Opcode },
5290     { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5291   },
5292
5293   /* PREFIX_VEX_0F3819 */
5294   {
5295     { Bad_Opcode },
5296     { Bad_Opcode },
5297     { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5298   },
5299
5300   /* PREFIX_VEX_0F381A */
5301   {
5302     { Bad_Opcode },
5303     { Bad_Opcode },
5304     { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5305   },
5306
5307   /* PREFIX_VEX_0F381C */
5308   {
5309     { Bad_Opcode },
5310     { Bad_Opcode },
5311     { VEX_W_TABLE (VEX_W_0F381C_P_2) },
5312   },
5313
5314   /* PREFIX_VEX_0F381D */
5315   {
5316     { Bad_Opcode },
5317     { Bad_Opcode },
5318     { VEX_W_TABLE (VEX_W_0F381D_P_2) },
5319   },
5320
5321   /* PREFIX_VEX_0F381E */
5322   {
5323     { Bad_Opcode },
5324     { Bad_Opcode },
5325     { VEX_W_TABLE (VEX_W_0F381E_P_2) },
5326   },
5327
5328   /* PREFIX_VEX_0F3820 */
5329   {
5330     { Bad_Opcode },
5331     { Bad_Opcode },
5332     { VEX_W_TABLE (VEX_W_0F3820_P_2) },
5333   },
5334
5335   /* PREFIX_VEX_0F3821 */
5336   {
5337     { Bad_Opcode },
5338     { Bad_Opcode },
5339     { VEX_W_TABLE (VEX_W_0F3821_P_2) },
5340   },
5341
5342   /* PREFIX_VEX_0F3822 */
5343   {
5344     { Bad_Opcode },
5345     { Bad_Opcode },
5346     { VEX_W_TABLE (VEX_W_0F3822_P_2) },
5347   },
5348
5349   /* PREFIX_VEX_0F3823 */
5350   {
5351     { Bad_Opcode },
5352     { Bad_Opcode },
5353     { VEX_W_TABLE (VEX_W_0F3823_P_2) },
5354   },
5355
5356   /* PREFIX_VEX_0F3824 */
5357   {
5358     { Bad_Opcode },
5359     { Bad_Opcode },
5360     { VEX_W_TABLE (VEX_W_0F3824_P_2) },
5361   },
5362
5363   /* PREFIX_VEX_0F3825 */
5364   {
5365     { Bad_Opcode },
5366     { Bad_Opcode },
5367     { VEX_W_TABLE (VEX_W_0F3825_P_2) },
5368   },
5369
5370   /* PREFIX_VEX_0F3828 */
5371   {
5372     { Bad_Opcode },
5373     { Bad_Opcode },
5374     { VEX_W_TABLE (VEX_W_0F3828_P_2) },
5375   },
5376
5377   /* PREFIX_VEX_0F3829 */
5378   {
5379     { Bad_Opcode },
5380     { Bad_Opcode },
5381     { VEX_W_TABLE (VEX_W_0F3829_P_2) },
5382   },
5383
5384   /* PREFIX_VEX_0F382A */
5385   {
5386     { Bad_Opcode },
5387     { Bad_Opcode },
5388     { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5389   },
5390
5391   /* PREFIX_VEX_0F382B */
5392   {
5393     { Bad_Opcode },
5394     { Bad_Opcode },
5395     { VEX_W_TABLE (VEX_W_0F382B_P_2) },
5396   },
5397
5398   /* PREFIX_VEX_0F382C */
5399   {
5400     { Bad_Opcode },
5401     { Bad_Opcode },
5402      { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5403   },
5404
5405   /* PREFIX_VEX_0F382D */
5406   {
5407     { Bad_Opcode },
5408     { Bad_Opcode },
5409      { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5410   },
5411
5412   /* PREFIX_VEX_0F382E */
5413   {
5414     { Bad_Opcode },
5415     { Bad_Opcode },
5416      { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5417   },
5418
5419   /* PREFIX_VEX_0F382F */
5420   {
5421     { Bad_Opcode },
5422     { Bad_Opcode },
5423      { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5424   },
5425
5426   /* PREFIX_VEX_0F3830 */
5427   {
5428     { Bad_Opcode },
5429     { Bad_Opcode },
5430     { VEX_W_TABLE (VEX_W_0F3830_P_2) },
5431   },
5432
5433   /* PREFIX_VEX_0F3831 */
5434   {
5435     { Bad_Opcode },
5436     { Bad_Opcode },
5437     { VEX_W_TABLE (VEX_W_0F3831_P_2) },
5438   },
5439
5440   /* PREFIX_VEX_0F3832 */
5441   {
5442     { Bad_Opcode },
5443     { Bad_Opcode },
5444     { VEX_W_TABLE (VEX_W_0F3832_P_2) },
5445   },
5446
5447   /* PREFIX_VEX_0F3833 */
5448   {
5449     { Bad_Opcode },
5450     { Bad_Opcode },
5451     { VEX_W_TABLE (VEX_W_0F3833_P_2) },
5452   },
5453
5454   /* PREFIX_VEX_0F3834 */
5455   {
5456     { Bad_Opcode },
5457     { Bad_Opcode },
5458     { VEX_W_TABLE (VEX_W_0F3834_P_2) },
5459   },
5460
5461   /* PREFIX_VEX_0F3835 */
5462   {
5463     { Bad_Opcode },
5464     { Bad_Opcode },
5465     { VEX_W_TABLE (VEX_W_0F3835_P_2) },
5466   },
5467
5468   /* PREFIX_VEX_0F3836 */
5469   {
5470     { Bad_Opcode },
5471     { Bad_Opcode },
5472     { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5473   },
5474
5475   /* PREFIX_VEX_0F3837 */
5476   {
5477     { Bad_Opcode },
5478     { Bad_Opcode },
5479     { VEX_W_TABLE (VEX_W_0F3837_P_2) },
5480   },
5481
5482   /* PREFIX_VEX_0F3838 */
5483   {
5484     { Bad_Opcode },
5485     { Bad_Opcode },
5486     { VEX_W_TABLE (VEX_W_0F3838_P_2) },
5487   },
5488
5489   /* PREFIX_VEX_0F3839 */
5490   {
5491     { Bad_Opcode },
5492     { Bad_Opcode },
5493     { VEX_W_TABLE (VEX_W_0F3839_P_2) },
5494   },
5495
5496   /* PREFIX_VEX_0F383A */
5497   {
5498     { Bad_Opcode },
5499     { Bad_Opcode },
5500     { VEX_W_TABLE (VEX_W_0F383A_P_2) },
5501   },
5502
5503   /* PREFIX_VEX_0F383B */
5504   {
5505     { Bad_Opcode },
5506     { Bad_Opcode },
5507     { VEX_W_TABLE (VEX_W_0F383B_P_2) },
5508   },
5509
5510   /* PREFIX_VEX_0F383C */
5511   {
5512     { Bad_Opcode },
5513     { Bad_Opcode },
5514     { VEX_W_TABLE (VEX_W_0F383C_P_2) },
5515   },
5516
5517   /* PREFIX_VEX_0F383D */
5518   {
5519     { Bad_Opcode },
5520     { Bad_Opcode },
5521     { VEX_W_TABLE (VEX_W_0F383D_P_2) },
5522   },
5523
5524   /* PREFIX_VEX_0F383E */
5525   {
5526     { Bad_Opcode },
5527     { Bad_Opcode },
5528     { VEX_W_TABLE (VEX_W_0F383E_P_2) },
5529   },
5530
5531   /* PREFIX_VEX_0F383F */
5532   {
5533     { Bad_Opcode },
5534     { Bad_Opcode },
5535     { VEX_W_TABLE (VEX_W_0F383F_P_2) },
5536   },
5537
5538   /* PREFIX_VEX_0F3840 */
5539   {
5540     { Bad_Opcode },
5541     { Bad_Opcode },
5542     { VEX_W_TABLE (VEX_W_0F3840_P_2) },
5543   },
5544
5545   /* PREFIX_VEX_0F3841 */
5546   {
5547     { Bad_Opcode },
5548     { Bad_Opcode },
5549     { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
5550   },
5551
5552   /* PREFIX_VEX_0F3845 */
5553   {
5554     { Bad_Opcode },
5555     { Bad_Opcode },
5556     { "vpsrlv%LW", { XM, Vex, EXx } },
5557   },
5558
5559   /* PREFIX_VEX_0F3846 */
5560   {
5561     { Bad_Opcode },
5562     { Bad_Opcode },
5563     { VEX_W_TABLE (VEX_W_0F3846_P_2) },
5564   },
5565
5566   /* PREFIX_VEX_0F3847 */
5567   {
5568     { Bad_Opcode },
5569     { Bad_Opcode },
5570     { "vpsllv%LW", { XM, Vex, EXx } },
5571   },
5572
5573   /* PREFIX_VEX_0F3858 */
5574   {
5575     { Bad_Opcode },
5576     { Bad_Opcode },
5577     { VEX_W_TABLE (VEX_W_0F3858_P_2) },
5578   },
5579
5580   /* PREFIX_VEX_0F3859 */
5581   {
5582     { Bad_Opcode },
5583     { Bad_Opcode },
5584     { VEX_W_TABLE (VEX_W_0F3859_P_2) },
5585   },
5586
5587   /* PREFIX_VEX_0F385A */
5588   {
5589     { Bad_Opcode },
5590     { Bad_Opcode },
5591     { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
5592   },
5593
5594   /* PREFIX_VEX_0F3878 */
5595   {
5596     { Bad_Opcode },
5597     { Bad_Opcode },
5598     { VEX_W_TABLE (VEX_W_0F3878_P_2) },
5599   },
5600
5601   /* PREFIX_VEX_0F3879 */
5602   {
5603     { Bad_Opcode },
5604     { Bad_Opcode },
5605     { VEX_W_TABLE (VEX_W_0F3879_P_2) },
5606   },
5607
5608   /* PREFIX_VEX_0F388C */
5609   {
5610     { Bad_Opcode },
5611     { Bad_Opcode },
5612     { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
5613   },
5614
5615   /* PREFIX_VEX_0F388E */
5616   {
5617     { Bad_Opcode },
5618     { Bad_Opcode },
5619     { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
5620   },
5621
5622   /* PREFIX_VEX_0F3890 */
5623   {
5624     { Bad_Opcode },
5625     { Bad_Opcode },
5626     { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex } },
5627   },
5628
5629   /* PREFIX_VEX_0F3891 */
5630   {
5631     { Bad_Opcode },
5632     { Bad_Opcode },
5633     { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ } },
5634   },
5635
5636   /* PREFIX_VEX_0F3892 */
5637   {
5638     { Bad_Opcode },
5639     { Bad_Opcode },
5640     { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex } },
5641   },
5642
5643   /* PREFIX_VEX_0F3893 */
5644   {
5645     { Bad_Opcode },
5646     { Bad_Opcode },
5647     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ } },
5648   },
5649
5650   /* PREFIX_VEX_0F3896 */
5651   {
5652     { Bad_Opcode },
5653     { Bad_Opcode },
5654     { "vfmaddsub132p%XW", { XM, Vex, EXx } },
5655   },
5656
5657   /* PREFIX_VEX_0F3897 */
5658   {
5659     { Bad_Opcode },
5660     { Bad_Opcode },
5661     { "vfmsubadd132p%XW", { XM, Vex, EXx } },
5662   },
5663
5664   /* PREFIX_VEX_0F3898 */
5665   {
5666     { Bad_Opcode },
5667     { Bad_Opcode },
5668     { "vfmadd132p%XW", { XM, Vex, EXx } },
5669   },
5670
5671   /* PREFIX_VEX_0F3899 */
5672   {
5673     { Bad_Opcode },
5674     { Bad_Opcode },
5675     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5676   },
5677
5678   /* PREFIX_VEX_0F389A */
5679   {
5680     { Bad_Opcode },
5681     { Bad_Opcode },
5682     { "vfmsub132p%XW", { XM, Vex, EXx } },
5683   },
5684
5685   /* PREFIX_VEX_0F389B */
5686   {
5687     { Bad_Opcode },
5688     { Bad_Opcode },
5689     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5690   },
5691
5692   /* PREFIX_VEX_0F389C */
5693   {
5694     { Bad_Opcode },
5695     { Bad_Opcode },
5696     { "vfnmadd132p%XW", { XM, Vex, EXx } },
5697   },
5698
5699   /* PREFIX_VEX_0F389D */
5700   {
5701     { Bad_Opcode },
5702     { Bad_Opcode },
5703     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5704   },
5705
5706   /* PREFIX_VEX_0F389E */
5707   {
5708     { Bad_Opcode },
5709     { Bad_Opcode },
5710     { "vfnmsub132p%XW", { XM, Vex, EXx } },
5711   },
5712
5713   /* PREFIX_VEX_0F389F */
5714   {
5715     { Bad_Opcode },
5716     { Bad_Opcode },
5717     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5718   },
5719
5720   /* PREFIX_VEX_0F38A6 */
5721   {
5722     { Bad_Opcode },
5723     { Bad_Opcode },
5724     { "vfmaddsub213p%XW", { XM, Vex, EXx } },
5725     { Bad_Opcode },
5726   },
5727
5728   /* PREFIX_VEX_0F38A7 */
5729   {
5730     { Bad_Opcode },
5731     { Bad_Opcode },
5732     { "vfmsubadd213p%XW", { XM, Vex, EXx } },
5733   },
5734
5735   /* PREFIX_VEX_0F38A8 */
5736   {
5737     { Bad_Opcode },
5738     { Bad_Opcode },
5739     { "vfmadd213p%XW", { XM, Vex, EXx } },
5740   },
5741
5742   /* PREFIX_VEX_0F38A9 */
5743   {
5744     { Bad_Opcode },
5745     { Bad_Opcode },
5746     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5747   },
5748
5749   /* PREFIX_VEX_0F38AA */
5750   {
5751     { Bad_Opcode },
5752     { Bad_Opcode },
5753     { "vfmsub213p%XW", { XM, Vex, EXx } },
5754   },
5755
5756   /* PREFIX_VEX_0F38AB */
5757   {
5758     { Bad_Opcode },
5759     { Bad_Opcode },
5760     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5761   },
5762
5763   /* PREFIX_VEX_0F38AC */
5764   {
5765     { Bad_Opcode },
5766     { Bad_Opcode },
5767     { "vfnmadd213p%XW", { XM, Vex, EXx } },
5768   },
5769
5770   /* PREFIX_VEX_0F38AD */
5771   {
5772     { Bad_Opcode },
5773     { Bad_Opcode },
5774     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5775   },
5776
5777   /* PREFIX_VEX_0F38AE */
5778   {
5779     { Bad_Opcode },
5780     { Bad_Opcode },
5781     { "vfnmsub213p%XW", { XM, Vex, EXx } },
5782   },
5783
5784   /* PREFIX_VEX_0F38AF */
5785   {
5786     { Bad_Opcode },
5787     { Bad_Opcode },
5788     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5789   },
5790
5791   /* PREFIX_VEX_0F38B6 */
5792   {
5793     { Bad_Opcode },
5794     { Bad_Opcode },
5795     { "vfmaddsub231p%XW", { XM, Vex, EXx } },
5796   },
5797
5798   /* PREFIX_VEX_0F38B7 */
5799   {
5800     { Bad_Opcode },
5801     { Bad_Opcode },
5802     { "vfmsubadd231p%XW", { XM, Vex, EXx } },
5803   },
5804
5805   /* PREFIX_VEX_0F38B8 */
5806   {
5807     { Bad_Opcode },
5808     { Bad_Opcode },
5809     { "vfmadd231p%XW", { XM, Vex, EXx } },
5810   },
5811
5812   /* PREFIX_VEX_0F38B9 */
5813   {
5814     { Bad_Opcode },
5815     { Bad_Opcode },
5816     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5817   },
5818
5819   /* PREFIX_VEX_0F38BA */
5820   {
5821     { Bad_Opcode },
5822     { Bad_Opcode },
5823     { "vfmsub231p%XW", { XM, Vex, EXx } },
5824   },
5825
5826   /* PREFIX_VEX_0F38BB */
5827   {
5828     { Bad_Opcode },
5829     { Bad_Opcode },
5830     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5831   },
5832
5833   /* PREFIX_VEX_0F38BC */
5834   {
5835     { Bad_Opcode },
5836     { Bad_Opcode },
5837     { "vfnmadd231p%XW", { XM, Vex, EXx } },
5838   },
5839
5840   /* PREFIX_VEX_0F38BD */
5841   {
5842     { Bad_Opcode },
5843     { Bad_Opcode },
5844     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5845   },
5846
5847   /* PREFIX_VEX_0F38BE */
5848   {
5849     { Bad_Opcode },
5850     { Bad_Opcode },
5851     { "vfnmsub231p%XW", { XM, Vex, EXx } },
5852   },
5853
5854   /* PREFIX_VEX_0F38BF */
5855   {
5856     { Bad_Opcode },
5857     { Bad_Opcode },
5858     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5859   },
5860
5861   /* PREFIX_VEX_0F38DB */
5862   {
5863     { Bad_Opcode },
5864     { Bad_Opcode },
5865     { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
5866   },
5867
5868   /* PREFIX_VEX_0F38DC */
5869   {
5870     { Bad_Opcode },
5871     { Bad_Opcode },
5872     { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2) },
5873   },
5874
5875   /* PREFIX_VEX_0F38DD */
5876   {
5877     { Bad_Opcode },
5878     { Bad_Opcode },
5879     { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2) },
5880   },
5881
5882   /* PREFIX_VEX_0F38DE */
5883   {
5884     { Bad_Opcode },
5885     { Bad_Opcode },
5886     { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2) },
5887   },
5888
5889   /* PREFIX_VEX_0F38DF */
5890   {
5891     { Bad_Opcode },
5892     { Bad_Opcode },
5893     { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2) },
5894   },
5895
5896   /* PREFIX_VEX_0F38F2 */
5897   {
5898     { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
5899   },
5900
5901   /* PREFIX_VEX_0F38F3_REG_1 */
5902   {
5903     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
5904   },
5905
5906   /* PREFIX_VEX_0F38F3_REG_2 */
5907   {
5908     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
5909   },
5910
5911   /* PREFIX_VEX_0F38F3_REG_3 */
5912   {
5913     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
5914   },
5915
5916   /* PREFIX_VEX_0F38F5 */
5917   {
5918     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
5919     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
5920     { Bad_Opcode },
5921     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
5922   },
5923
5924   /* PREFIX_VEX_0F38F6 */
5925   {
5926     { Bad_Opcode },
5927     { Bad_Opcode },
5928     { Bad_Opcode },
5929     { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
5930   },
5931
5932   /* PREFIX_VEX_0F38F7 */
5933   {
5934     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
5935     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
5936     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
5937     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
5938   },
5939
5940   /* PREFIX_VEX_0F3A00 */
5941   {
5942     { Bad_Opcode },
5943     { Bad_Opcode },
5944     { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
5945   },
5946
5947   /* PREFIX_VEX_0F3A01 */
5948   {
5949     { Bad_Opcode },
5950     { Bad_Opcode },
5951     { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
5952   },
5953
5954   /* PREFIX_VEX_0F3A02 */
5955   {
5956     { Bad_Opcode },
5957     { Bad_Opcode },
5958     { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
5959   },
5960
5961   /* PREFIX_VEX_0F3A04 */
5962   {
5963     { Bad_Opcode },
5964     { Bad_Opcode },
5965     { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
5966   },
5967
5968   /* PREFIX_VEX_0F3A05 */
5969   {
5970     { Bad_Opcode },
5971     { Bad_Opcode },
5972     { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
5973   },
5974
5975   /* PREFIX_VEX_0F3A06 */
5976   {
5977     { Bad_Opcode },
5978     { Bad_Opcode },
5979     { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
5980   },
5981
5982   /* PREFIX_VEX_0F3A08 */
5983   {
5984     { Bad_Opcode },
5985     { Bad_Opcode },
5986     { VEX_W_TABLE (VEX_W_0F3A08_P_2) },
5987   },
5988
5989   /* PREFIX_VEX_0F3A09 */
5990   {
5991     { Bad_Opcode },
5992     { Bad_Opcode },
5993     { VEX_W_TABLE (VEX_W_0F3A09_P_2) },
5994   },
5995
5996   /* PREFIX_VEX_0F3A0A */
5997   {
5998     { Bad_Opcode },
5999     { Bad_Opcode },
6000     { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) },
6001   },
6002
6003   /* PREFIX_VEX_0F3A0B */
6004   {
6005     { Bad_Opcode },
6006     { Bad_Opcode },
6007     { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) },
6008   },
6009
6010   /* PREFIX_VEX_0F3A0C */
6011   {
6012     { Bad_Opcode },
6013     { Bad_Opcode },
6014     { VEX_W_TABLE (VEX_W_0F3A0C_P_2) },
6015   },
6016
6017   /* PREFIX_VEX_0F3A0D */
6018   {
6019     { Bad_Opcode },
6020     { Bad_Opcode },
6021     { VEX_W_TABLE (VEX_W_0F3A0D_P_2) },
6022   },
6023
6024   /* PREFIX_VEX_0F3A0E */
6025   {
6026     { Bad_Opcode },
6027     { Bad_Opcode },
6028     { VEX_W_TABLE (VEX_W_0F3A0E_P_2) },
6029   },
6030
6031   /* PREFIX_VEX_0F3A0F */
6032   {
6033     { Bad_Opcode },
6034     { Bad_Opcode },
6035     { VEX_W_TABLE (VEX_W_0F3A0F_P_2) },
6036   },
6037
6038   /* PREFIX_VEX_0F3A14 */
6039   {
6040     { Bad_Opcode },
6041     { Bad_Opcode },
6042     { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6043   },
6044
6045   /* PREFIX_VEX_0F3A15 */
6046   {
6047     { Bad_Opcode },
6048     { Bad_Opcode },
6049     { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6050   },
6051
6052   /* PREFIX_VEX_0F3A16 */
6053   {
6054     { Bad_Opcode },
6055     { Bad_Opcode },
6056     { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6057   },
6058
6059   /* PREFIX_VEX_0F3A17 */
6060   {
6061     { Bad_Opcode },
6062     { Bad_Opcode },
6063     { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6064   },
6065
6066   /* PREFIX_VEX_0F3A18 */
6067   {
6068     { Bad_Opcode },
6069     { Bad_Opcode },
6070     { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6071   },
6072
6073   /* PREFIX_VEX_0F3A19 */
6074   {
6075     { Bad_Opcode },
6076     { Bad_Opcode },
6077     { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6078   },
6079
6080   /* PREFIX_VEX_0F3A1D */
6081   {
6082     { Bad_Opcode },
6083     { Bad_Opcode },
6084     { "vcvtps2ph", { EXxmmq, XM, Ib } },
6085   },
6086
6087   /* PREFIX_VEX_0F3A20 */
6088   {
6089     { Bad_Opcode },
6090     { Bad_Opcode },
6091     { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6092   },
6093
6094   /* PREFIX_VEX_0F3A21 */
6095   {
6096     { Bad_Opcode },
6097     { Bad_Opcode },
6098     { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6099   },
6100
6101   /* PREFIX_VEX_0F3A22 */
6102   {
6103     { Bad_Opcode },
6104     { Bad_Opcode },
6105     { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6106   },
6107
6108   /* PREFIX_VEX_0F3A30 */
6109   {
6110     { Bad_Opcode },
6111     { Bad_Opcode },
6112     { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6113   },
6114
6115   /* PREFIX_VEX_0F3A32 */
6116   {
6117     { Bad_Opcode },
6118     { Bad_Opcode },
6119     { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6120   },
6121
6122   /* PREFIX_VEX_0F3A38 */
6123   {
6124     { Bad_Opcode },
6125     { Bad_Opcode },
6126     { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6127   },
6128
6129   /* PREFIX_VEX_0F3A39 */
6130   {
6131     { Bad_Opcode },
6132     { Bad_Opcode },
6133     { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6134   },
6135
6136   /* PREFIX_VEX_0F3A40 */
6137   {
6138     { Bad_Opcode },
6139     { Bad_Opcode },
6140     { VEX_W_TABLE (VEX_W_0F3A40_P_2) },
6141   },
6142
6143   /* PREFIX_VEX_0F3A41 */
6144   {
6145     { Bad_Opcode },
6146     { Bad_Opcode },
6147     { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6148   },
6149
6150   /* PREFIX_VEX_0F3A42 */
6151   {
6152     { Bad_Opcode },
6153     { Bad_Opcode },
6154     { VEX_W_TABLE (VEX_W_0F3A42_P_2) },
6155   },
6156
6157   /* PREFIX_VEX_0F3A44 */
6158   {
6159     { Bad_Opcode },
6160     { Bad_Opcode },
6161     { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2) },
6162   },
6163
6164   /* PREFIX_VEX_0F3A46 */
6165   {
6166     { Bad_Opcode },
6167     { Bad_Opcode },
6168     { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6169   },
6170
6171   /* PREFIX_VEX_0F3A48 */
6172   {
6173     { Bad_Opcode },
6174     { Bad_Opcode },
6175     { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6176   },
6177
6178   /* PREFIX_VEX_0F3A49 */
6179   {
6180     { Bad_Opcode },
6181     { Bad_Opcode },
6182     { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6183   },
6184
6185   /* PREFIX_VEX_0F3A4A */
6186   {
6187     { Bad_Opcode },
6188     { Bad_Opcode },
6189     { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6190   },
6191
6192   /* PREFIX_VEX_0F3A4B */
6193   {
6194     { Bad_Opcode },
6195     { Bad_Opcode },
6196     { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6197   },
6198
6199   /* PREFIX_VEX_0F3A4C */
6200   {
6201     { Bad_Opcode },
6202     { Bad_Opcode },
6203     { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6204   },
6205
6206   /* PREFIX_VEX_0F3A5C */
6207   {
6208     { Bad_Opcode },
6209     { Bad_Opcode },
6210     { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6211   },
6212
6213   /* PREFIX_VEX_0F3A5D */
6214   {
6215     { Bad_Opcode },
6216     { Bad_Opcode },
6217     { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6218   },
6219
6220   /* PREFIX_VEX_0F3A5E */
6221   {
6222     { Bad_Opcode },
6223     { Bad_Opcode },
6224     { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6225   },
6226
6227   /* PREFIX_VEX_0F3A5F */
6228   {
6229     { Bad_Opcode },
6230     { Bad_Opcode },
6231     { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6232   },
6233
6234   /* PREFIX_VEX_0F3A60 */
6235   {
6236     { Bad_Opcode },
6237     { Bad_Opcode },
6238     { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6239     { Bad_Opcode },
6240   },
6241
6242   /* PREFIX_VEX_0F3A61 */
6243   {
6244     { Bad_Opcode },
6245     { Bad_Opcode },
6246     { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6247   },
6248
6249   /* PREFIX_VEX_0F3A62 */
6250   {
6251     { Bad_Opcode },
6252     { Bad_Opcode },
6253     { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6254   },
6255
6256   /* PREFIX_VEX_0F3A63 */
6257   {
6258     { Bad_Opcode },
6259     { Bad_Opcode },
6260     { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6261   },
6262
6263   /* PREFIX_VEX_0F3A68 */
6264   {
6265     { Bad_Opcode },
6266     { Bad_Opcode },
6267     { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6268   },
6269
6270   /* PREFIX_VEX_0F3A69 */
6271   {
6272     { Bad_Opcode },
6273     { Bad_Opcode },
6274     { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6275   },
6276
6277   /* PREFIX_VEX_0F3A6A */
6278   {
6279     { Bad_Opcode },
6280     { Bad_Opcode },
6281     { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6282   },
6283
6284   /* PREFIX_VEX_0F3A6B */
6285   {
6286     { Bad_Opcode },
6287     { Bad_Opcode },
6288     { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6289   },
6290
6291   /* PREFIX_VEX_0F3A6C */
6292   {
6293     { Bad_Opcode },
6294     { Bad_Opcode },
6295     { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6296   },
6297
6298   /* PREFIX_VEX_0F3A6D */
6299   {
6300     { Bad_Opcode },
6301     { Bad_Opcode },
6302     { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6303   },
6304
6305   /* PREFIX_VEX_0F3A6E */
6306   {
6307     { Bad_Opcode },
6308     { Bad_Opcode },
6309     { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6310   },
6311
6312   /* PREFIX_VEX_0F3A6F */
6313   {
6314     { Bad_Opcode },
6315     { Bad_Opcode },
6316     { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6317   },
6318
6319   /* PREFIX_VEX_0F3A78 */
6320   {
6321     { Bad_Opcode },
6322     { Bad_Opcode },
6323     { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6324   },
6325
6326   /* PREFIX_VEX_0F3A79 */
6327   {
6328     { Bad_Opcode },
6329     { Bad_Opcode },
6330     { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6331   },
6332
6333   /* PREFIX_VEX_0F3A7A */
6334   {
6335     { Bad_Opcode },
6336     { Bad_Opcode },
6337     { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6338   },
6339
6340   /* PREFIX_VEX_0F3A7B */
6341   {
6342     { Bad_Opcode },
6343     { Bad_Opcode },
6344     { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6345   },
6346
6347   /* PREFIX_VEX_0F3A7C */
6348   {
6349     { Bad_Opcode },
6350     { Bad_Opcode },
6351     { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6352     { Bad_Opcode },
6353   },
6354
6355   /* PREFIX_VEX_0F3A7D */
6356   {
6357     { Bad_Opcode },
6358     { Bad_Opcode },
6359     { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6360   },
6361
6362   /* PREFIX_VEX_0F3A7E */
6363   {
6364     { Bad_Opcode },
6365     { Bad_Opcode },
6366     { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6367   },
6368
6369   /* PREFIX_VEX_0F3A7F */
6370   {
6371     { Bad_Opcode },
6372     { Bad_Opcode },
6373     { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6374   },
6375
6376   /* PREFIX_VEX_0F3ADF */
6377   {
6378     { Bad_Opcode },
6379     { Bad_Opcode },
6380     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6381   },
6382
6383   /* PREFIX_VEX_0F3AF0 */
6384   {
6385     { Bad_Opcode },
6386     { Bad_Opcode },
6387     { Bad_Opcode },
6388     { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6389   },
6390
6391 #define NEED_PREFIX_TABLE
6392 #include "i386-dis-evex.h"
6393 #undef NEED_PREFIX_TABLE
6394 };
6395
6396 static const struct dis386 x86_64_table[][2] = {
6397   /* X86_64_06 */
6398   {
6399     { "pushP", { es } },
6400   },
6401
6402   /* X86_64_07 */
6403   {
6404     { "popP", { es } },
6405   },
6406
6407   /* X86_64_0D */
6408   {
6409     { "pushP", { cs } },
6410   },
6411
6412   /* X86_64_16 */
6413   {
6414     { "pushP", { ss } },
6415   },
6416
6417   /* X86_64_17 */
6418   {
6419     { "popP", { ss } },
6420   },
6421
6422   /* X86_64_1E */
6423   {
6424     { "pushP", { ds } },
6425   },
6426
6427   /* X86_64_1F */
6428   {
6429     { "popP", { ds } },
6430   },
6431
6432   /* X86_64_27 */
6433   {
6434     { "daa", { XX } },
6435   },
6436
6437   /* X86_64_2F */
6438   {
6439     { "das", { XX } },
6440   },
6441
6442   /* X86_64_37 */
6443   {
6444     { "aaa", { XX } },
6445   },
6446
6447   /* X86_64_3F */
6448   {
6449     { "aas", { XX } },
6450   },
6451
6452   /* X86_64_60 */
6453   {
6454     { "pushaP", { XX } },
6455   },
6456
6457   /* X86_64_61 */
6458   {
6459     { "popaP", { XX } },
6460   },
6461
6462   /* X86_64_62 */
6463   {
6464     { MOD_TABLE (MOD_62_32BIT) },
6465     { EVEX_TABLE (EVEX_0F) },
6466   },
6467
6468   /* X86_64_63 */
6469   {
6470     { "arpl", { Ew, Gw } },
6471     { "movs{lq|xd}", { Gv, Ed } },
6472   },
6473
6474   /* X86_64_6D */
6475   {
6476     { "ins{R|}", { Yzr, indirDX } },
6477     { "ins{G|}", { Yzr, indirDX } },
6478   },
6479
6480   /* X86_64_6F */
6481   {
6482     { "outs{R|}", { indirDXr, Xz } },
6483     { "outs{G|}", { indirDXr, Xz } },
6484   },
6485
6486   /* X86_64_9A */
6487   {
6488     { "Jcall{T|}", { Ap } },
6489   },
6490
6491   /* X86_64_C4 */
6492   {
6493     { MOD_TABLE (MOD_C4_32BIT) },
6494     { VEX_C4_TABLE (VEX_0F) },
6495   },
6496
6497   /* X86_64_C5 */
6498   {
6499     { MOD_TABLE (MOD_C5_32BIT) },
6500     { VEX_C5_TABLE (VEX_0F) },
6501   },
6502
6503   /* X86_64_CE */
6504   {
6505     { "into", { XX } },
6506   },
6507
6508   /* X86_64_D4 */
6509   {
6510     { "aam", { Ib } },
6511   },
6512
6513   /* X86_64_D5 */
6514   {
6515     { "aad", { Ib } },
6516   },
6517
6518   /* X86_64_EA */
6519   {
6520     { "Jjmp{T|}", { Ap } },
6521   },
6522
6523   /* X86_64_0F01_REG_0 */
6524   {
6525     { "sgdt{Q|IQ}", { M } },
6526     { "sgdt", { M } },
6527   },
6528
6529   /* X86_64_0F01_REG_1 */
6530   {
6531     { "sidt{Q|IQ}", { M } },
6532     { "sidt", { M } },
6533   },
6534
6535   /* X86_64_0F01_REG_2 */
6536   {
6537     { "lgdt{Q|Q}", { M } },
6538     { "lgdt", { M } },
6539   },
6540
6541   /* X86_64_0F01_REG_3 */
6542   {
6543     { "lidt{Q|Q}", { M } },
6544     { "lidt", { M } },
6545   },
6546 };
6547
6548 static const struct dis386 three_byte_table[][256] = {
6549
6550   /* THREE_BYTE_0F38 */
6551   {
6552     /* 00 */
6553     { "pshufb",         { MX, EM } },
6554     { "phaddw",         { MX, EM } },
6555     { "phaddd",         { MX, EM } },
6556     { "phaddsw",        { MX, EM } },
6557     { "pmaddubsw",      { MX, EM } },
6558     { "phsubw",         { MX, EM } },
6559     { "phsubd",         { MX, EM } },
6560     { "phsubsw",        { MX, EM } },
6561     /* 08 */
6562     { "psignb",         { MX, EM } },
6563     { "psignw",         { MX, EM } },
6564     { "psignd",         { MX, EM } },
6565     { "pmulhrsw",       { MX, EM } },
6566     { Bad_Opcode },
6567     { Bad_Opcode },
6568     { Bad_Opcode },
6569     { Bad_Opcode },
6570     /* 10 */
6571     { PREFIX_TABLE (PREFIX_0F3810) },
6572     { Bad_Opcode },
6573     { Bad_Opcode },
6574     { Bad_Opcode },
6575     { PREFIX_TABLE (PREFIX_0F3814) },
6576     { PREFIX_TABLE (PREFIX_0F3815) },
6577     { Bad_Opcode },
6578     { PREFIX_TABLE (PREFIX_0F3817) },
6579     /* 18 */
6580     { Bad_Opcode },
6581     { Bad_Opcode },
6582     { Bad_Opcode },
6583     { Bad_Opcode },
6584     { "pabsb",          { MX, EM } },
6585     { "pabsw",          { MX, EM } },
6586     { "pabsd",          { MX, EM } },
6587     { Bad_Opcode },
6588     /* 20 */
6589     { PREFIX_TABLE (PREFIX_0F3820) },
6590     { PREFIX_TABLE (PREFIX_0F3821) },
6591     { PREFIX_TABLE (PREFIX_0F3822) },
6592     { PREFIX_TABLE (PREFIX_0F3823) },
6593     { PREFIX_TABLE (PREFIX_0F3824) },
6594     { PREFIX_TABLE (PREFIX_0F3825) },
6595     { Bad_Opcode },
6596     { Bad_Opcode },
6597     /* 28 */
6598     { PREFIX_TABLE (PREFIX_0F3828) },
6599     { PREFIX_TABLE (PREFIX_0F3829) },
6600     { PREFIX_TABLE (PREFIX_0F382A) },
6601     { PREFIX_TABLE (PREFIX_0F382B) },
6602     { Bad_Opcode },
6603     { Bad_Opcode },
6604     { Bad_Opcode },
6605     { Bad_Opcode },
6606     /* 30 */
6607     { PREFIX_TABLE (PREFIX_0F3830) },
6608     { PREFIX_TABLE (PREFIX_0F3831) },
6609     { PREFIX_TABLE (PREFIX_0F3832) },
6610     { PREFIX_TABLE (PREFIX_0F3833) },
6611     { PREFIX_TABLE (PREFIX_0F3834) },
6612     { PREFIX_TABLE (PREFIX_0F3835) },
6613     { Bad_Opcode },
6614     { PREFIX_TABLE (PREFIX_0F3837) },
6615     /* 38 */
6616     { PREFIX_TABLE (PREFIX_0F3838) },
6617     { PREFIX_TABLE (PREFIX_0F3839) },
6618     { PREFIX_TABLE (PREFIX_0F383A) },
6619     { PREFIX_TABLE (PREFIX_0F383B) },
6620     { PREFIX_TABLE (PREFIX_0F383C) },
6621     { PREFIX_TABLE (PREFIX_0F383D) },
6622     { PREFIX_TABLE (PREFIX_0F383E) },
6623     { PREFIX_TABLE (PREFIX_0F383F) },
6624     /* 40 */
6625     { PREFIX_TABLE (PREFIX_0F3840) },
6626     { PREFIX_TABLE (PREFIX_0F3841) },
6627     { Bad_Opcode },
6628     { Bad_Opcode },
6629     { Bad_Opcode },
6630     { Bad_Opcode },
6631     { Bad_Opcode },
6632     { Bad_Opcode },
6633     /* 48 */
6634     { Bad_Opcode },
6635     { Bad_Opcode },
6636     { Bad_Opcode },
6637     { Bad_Opcode },
6638     { Bad_Opcode },
6639     { Bad_Opcode },
6640     { Bad_Opcode },
6641     { Bad_Opcode },
6642     /* 50 */
6643     { Bad_Opcode },
6644     { Bad_Opcode },
6645     { Bad_Opcode },
6646     { Bad_Opcode },
6647     { Bad_Opcode },
6648     { Bad_Opcode },
6649     { Bad_Opcode },
6650     { Bad_Opcode },
6651     /* 58 */
6652     { Bad_Opcode },
6653     { Bad_Opcode },
6654     { Bad_Opcode },
6655     { Bad_Opcode },
6656     { Bad_Opcode },
6657     { Bad_Opcode },
6658     { Bad_Opcode },
6659     { Bad_Opcode },
6660     /* 60 */
6661     { Bad_Opcode },
6662     { Bad_Opcode },
6663     { Bad_Opcode },
6664     { Bad_Opcode },
6665     { Bad_Opcode },
6666     { Bad_Opcode },
6667     { Bad_Opcode },
6668     { Bad_Opcode },
6669     /* 68 */
6670     { Bad_Opcode },
6671     { Bad_Opcode },
6672     { Bad_Opcode },
6673     { Bad_Opcode },
6674     { Bad_Opcode },
6675     { Bad_Opcode },
6676     { Bad_Opcode },
6677     { Bad_Opcode },
6678     /* 70 */
6679     { Bad_Opcode },
6680     { Bad_Opcode },
6681     { Bad_Opcode },
6682     { Bad_Opcode },
6683     { Bad_Opcode },
6684     { Bad_Opcode },
6685     { Bad_Opcode },
6686     { Bad_Opcode },
6687     /* 78 */
6688     { Bad_Opcode },
6689     { Bad_Opcode },
6690     { Bad_Opcode },
6691     { Bad_Opcode },
6692     { Bad_Opcode },
6693     { Bad_Opcode },
6694     { Bad_Opcode },
6695     { Bad_Opcode },
6696     /* 80 */
6697     { PREFIX_TABLE (PREFIX_0F3880) },
6698     { PREFIX_TABLE (PREFIX_0F3881) },
6699     { PREFIX_TABLE (PREFIX_0F3882) },
6700     { Bad_Opcode },
6701     { Bad_Opcode },
6702     { Bad_Opcode },
6703     { Bad_Opcode },
6704     { Bad_Opcode },
6705     /* 88 */
6706     { Bad_Opcode },
6707     { Bad_Opcode },
6708     { Bad_Opcode },
6709     { Bad_Opcode },
6710     { Bad_Opcode },
6711     { Bad_Opcode },
6712     { Bad_Opcode },
6713     { Bad_Opcode },
6714     /* 90 */
6715     { Bad_Opcode },
6716     { Bad_Opcode },
6717     { Bad_Opcode },
6718     { Bad_Opcode },
6719     { Bad_Opcode },
6720     { Bad_Opcode },
6721     { Bad_Opcode },
6722     { Bad_Opcode },
6723     /* 98 */
6724     { Bad_Opcode },
6725     { Bad_Opcode },
6726     { Bad_Opcode },
6727     { Bad_Opcode },
6728     { Bad_Opcode },
6729     { Bad_Opcode },
6730     { Bad_Opcode },
6731     { Bad_Opcode },
6732     /* a0 */
6733     { Bad_Opcode },
6734     { Bad_Opcode },
6735     { Bad_Opcode },
6736     { Bad_Opcode },
6737     { Bad_Opcode },
6738     { Bad_Opcode },
6739     { Bad_Opcode },
6740     { Bad_Opcode },
6741     /* a8 */
6742     { Bad_Opcode },
6743     { Bad_Opcode },
6744     { Bad_Opcode },
6745     { Bad_Opcode },
6746     { Bad_Opcode },
6747     { Bad_Opcode },
6748     { Bad_Opcode },
6749     { Bad_Opcode },
6750     /* b0 */
6751     { Bad_Opcode },
6752     { Bad_Opcode },
6753     { Bad_Opcode },
6754     { Bad_Opcode },
6755     { Bad_Opcode },
6756     { Bad_Opcode },
6757     { Bad_Opcode },
6758     { Bad_Opcode },
6759     /* b8 */
6760     { Bad_Opcode },
6761     { Bad_Opcode },
6762     { Bad_Opcode },
6763     { Bad_Opcode },
6764     { Bad_Opcode },
6765     { Bad_Opcode },
6766     { Bad_Opcode },
6767     { Bad_Opcode },
6768     /* c0 */
6769     { Bad_Opcode },
6770     { Bad_Opcode },
6771     { Bad_Opcode },
6772     { Bad_Opcode },
6773     { Bad_Opcode },
6774     { Bad_Opcode },
6775     { Bad_Opcode },
6776     { Bad_Opcode },
6777     /* c8 */
6778     { PREFIX_TABLE (PREFIX_0F38C8) },
6779     { PREFIX_TABLE (PREFIX_0F38C9) },
6780     { PREFIX_TABLE (PREFIX_0F38CA) },
6781     { PREFIX_TABLE (PREFIX_0F38CB) },
6782     { PREFIX_TABLE (PREFIX_0F38CC) },
6783     { PREFIX_TABLE (PREFIX_0F38CD) },
6784     { Bad_Opcode },
6785     { Bad_Opcode },
6786     /* d0 */
6787     { Bad_Opcode },
6788     { Bad_Opcode },
6789     { Bad_Opcode },
6790     { Bad_Opcode },
6791     { Bad_Opcode },
6792     { Bad_Opcode },
6793     { Bad_Opcode },
6794     { Bad_Opcode },
6795     /* d8 */
6796     { Bad_Opcode },
6797     { Bad_Opcode },
6798     { Bad_Opcode },
6799     { PREFIX_TABLE (PREFIX_0F38DB) },
6800     { PREFIX_TABLE (PREFIX_0F38DC) },
6801     { PREFIX_TABLE (PREFIX_0F38DD) },
6802     { PREFIX_TABLE (PREFIX_0F38DE) },
6803     { PREFIX_TABLE (PREFIX_0F38DF) },
6804     /* e0 */
6805     { Bad_Opcode },
6806     { Bad_Opcode },
6807     { Bad_Opcode },
6808     { Bad_Opcode },
6809     { Bad_Opcode },
6810     { Bad_Opcode },
6811     { Bad_Opcode },
6812     { Bad_Opcode },
6813     /* e8 */
6814     { Bad_Opcode },
6815     { Bad_Opcode },
6816     { Bad_Opcode },
6817     { Bad_Opcode },
6818     { Bad_Opcode },
6819     { Bad_Opcode },
6820     { Bad_Opcode },
6821     { Bad_Opcode },
6822     /* f0 */
6823     { PREFIX_TABLE (PREFIX_0F38F0) },
6824     { PREFIX_TABLE (PREFIX_0F38F1) },
6825     { Bad_Opcode },
6826     { Bad_Opcode },
6827     { Bad_Opcode },
6828     { Bad_Opcode },
6829     { PREFIX_TABLE (PREFIX_0F38F6) },
6830     { Bad_Opcode },
6831     /* f8 */
6832     { Bad_Opcode },
6833     { Bad_Opcode },
6834     { Bad_Opcode },
6835     { Bad_Opcode },
6836     { Bad_Opcode },
6837     { Bad_Opcode },
6838     { Bad_Opcode },
6839     { Bad_Opcode },
6840   },
6841   /* THREE_BYTE_0F3A */
6842   {
6843     /* 00 */
6844     { Bad_Opcode },
6845     { Bad_Opcode },
6846     { Bad_Opcode },
6847     { Bad_Opcode },
6848     { Bad_Opcode },
6849     { Bad_Opcode },
6850     { Bad_Opcode },
6851     { Bad_Opcode },
6852     /* 08 */
6853     { PREFIX_TABLE (PREFIX_0F3A08) },
6854     { PREFIX_TABLE (PREFIX_0F3A09) },
6855     { PREFIX_TABLE (PREFIX_0F3A0A) },
6856     { PREFIX_TABLE (PREFIX_0F3A0B) },
6857     { PREFIX_TABLE (PREFIX_0F3A0C) },
6858     { PREFIX_TABLE (PREFIX_0F3A0D) },
6859     { PREFIX_TABLE (PREFIX_0F3A0E) },
6860     { "palignr",        { MX, EM, Ib } },
6861     /* 10 */
6862     { Bad_Opcode },
6863     { Bad_Opcode },
6864     { Bad_Opcode },
6865     { Bad_Opcode },
6866     { PREFIX_TABLE (PREFIX_0F3A14) },
6867     { PREFIX_TABLE (PREFIX_0F3A15) },
6868     { PREFIX_TABLE (PREFIX_0F3A16) },
6869     { PREFIX_TABLE (PREFIX_0F3A17) },
6870     /* 18 */
6871     { Bad_Opcode },
6872     { Bad_Opcode },
6873     { Bad_Opcode },
6874     { Bad_Opcode },
6875     { Bad_Opcode },
6876     { Bad_Opcode },
6877     { Bad_Opcode },
6878     { Bad_Opcode },
6879     /* 20 */
6880     { PREFIX_TABLE (PREFIX_0F3A20) },
6881     { PREFIX_TABLE (PREFIX_0F3A21) },
6882     { PREFIX_TABLE (PREFIX_0F3A22) },
6883     { Bad_Opcode },
6884     { Bad_Opcode },
6885     { Bad_Opcode },
6886     { Bad_Opcode },
6887     { Bad_Opcode },
6888     /* 28 */
6889     { Bad_Opcode },
6890     { Bad_Opcode },
6891     { Bad_Opcode },
6892     { Bad_Opcode },
6893     { Bad_Opcode },
6894     { Bad_Opcode },
6895     { Bad_Opcode },
6896     { Bad_Opcode },
6897     /* 30 */
6898     { Bad_Opcode },
6899     { Bad_Opcode },
6900     { Bad_Opcode },
6901     { Bad_Opcode },
6902     { Bad_Opcode },
6903     { Bad_Opcode },
6904     { Bad_Opcode },
6905     { Bad_Opcode },
6906     /* 38 */
6907     { Bad_Opcode },
6908     { Bad_Opcode },
6909     { Bad_Opcode },
6910     { Bad_Opcode },
6911     { Bad_Opcode },
6912     { Bad_Opcode },
6913     { Bad_Opcode },
6914     { Bad_Opcode },
6915     /* 40 */
6916     { PREFIX_TABLE (PREFIX_0F3A40) },
6917     { PREFIX_TABLE (PREFIX_0F3A41) },
6918     { PREFIX_TABLE (PREFIX_0F3A42) },
6919     { Bad_Opcode },
6920     { PREFIX_TABLE (PREFIX_0F3A44) },
6921     { Bad_Opcode },
6922     { Bad_Opcode },
6923     { Bad_Opcode },
6924     /* 48 */
6925     { Bad_Opcode },
6926     { Bad_Opcode },
6927     { Bad_Opcode },
6928     { Bad_Opcode },
6929     { Bad_Opcode },
6930     { Bad_Opcode },
6931     { Bad_Opcode },
6932     { Bad_Opcode },
6933     /* 50 */
6934     { Bad_Opcode },
6935     { Bad_Opcode },
6936     { Bad_Opcode },
6937     { Bad_Opcode },
6938     { Bad_Opcode },
6939     { Bad_Opcode },
6940     { Bad_Opcode },
6941     { Bad_Opcode },
6942     /* 58 */
6943     { Bad_Opcode },
6944     { Bad_Opcode },
6945     { Bad_Opcode },
6946     { Bad_Opcode },
6947     { Bad_Opcode },
6948     { Bad_Opcode },
6949     { Bad_Opcode },
6950     { Bad_Opcode },
6951     /* 60 */
6952     { PREFIX_TABLE (PREFIX_0F3A60) },
6953     { PREFIX_TABLE (PREFIX_0F3A61) },
6954     { PREFIX_TABLE (PREFIX_0F3A62) },
6955     { PREFIX_TABLE (PREFIX_0F3A63) },
6956     { Bad_Opcode },
6957     { Bad_Opcode },
6958     { Bad_Opcode },
6959     { Bad_Opcode },
6960     /* 68 */
6961     { Bad_Opcode },
6962     { Bad_Opcode },
6963     { Bad_Opcode },
6964     { Bad_Opcode },
6965     { Bad_Opcode },
6966     { Bad_Opcode },
6967     { Bad_Opcode },
6968     { Bad_Opcode },
6969     /* 70 */
6970     { Bad_Opcode },
6971     { Bad_Opcode },
6972     { Bad_Opcode },
6973     { Bad_Opcode },
6974     { Bad_Opcode },
6975     { Bad_Opcode },
6976     { Bad_Opcode },
6977     { Bad_Opcode },
6978     /* 78 */
6979     { Bad_Opcode },
6980     { Bad_Opcode },
6981     { Bad_Opcode },
6982     { Bad_Opcode },
6983     { Bad_Opcode },
6984     { Bad_Opcode },
6985     { Bad_Opcode },
6986     { Bad_Opcode },
6987     /* 80 */
6988     { Bad_Opcode },
6989     { Bad_Opcode },
6990     { Bad_Opcode },
6991     { Bad_Opcode },
6992     { Bad_Opcode },
6993     { Bad_Opcode },
6994     { Bad_Opcode },
6995     { Bad_Opcode },
6996     /* 88 */
6997     { Bad_Opcode },
6998     { Bad_Opcode },
6999     { Bad_Opcode },
7000     { Bad_Opcode },
7001     { Bad_Opcode },
7002     { Bad_Opcode },
7003     { Bad_Opcode },
7004     { Bad_Opcode },
7005     /* 90 */
7006     { Bad_Opcode },
7007     { Bad_Opcode },
7008     { Bad_Opcode },
7009     { Bad_Opcode },
7010     { Bad_Opcode },
7011     { Bad_Opcode },
7012     { Bad_Opcode },
7013     { Bad_Opcode },
7014     /* 98 */
7015     { Bad_Opcode },
7016     { Bad_Opcode },
7017     { Bad_Opcode },
7018     { Bad_Opcode },
7019     { Bad_Opcode },
7020     { Bad_Opcode },
7021     { Bad_Opcode },
7022     { Bad_Opcode },
7023     /* a0 */
7024     { Bad_Opcode },
7025     { Bad_Opcode },
7026     { Bad_Opcode },
7027     { Bad_Opcode },
7028     { Bad_Opcode },
7029     { Bad_Opcode },
7030     { Bad_Opcode },
7031     { Bad_Opcode },
7032     /* a8 */
7033     { Bad_Opcode },
7034     { Bad_Opcode },
7035     { Bad_Opcode },
7036     { Bad_Opcode },
7037     { Bad_Opcode },
7038     { Bad_Opcode },
7039     { Bad_Opcode },
7040     { Bad_Opcode },
7041     /* b0 */
7042     { Bad_Opcode },
7043     { Bad_Opcode },
7044     { Bad_Opcode },
7045     { Bad_Opcode },
7046     { Bad_Opcode },
7047     { Bad_Opcode },
7048     { Bad_Opcode },
7049     { Bad_Opcode },
7050     /* b8 */
7051     { Bad_Opcode },
7052     { Bad_Opcode },
7053     { Bad_Opcode },
7054     { Bad_Opcode },
7055     { Bad_Opcode },
7056     { Bad_Opcode },
7057     { Bad_Opcode },
7058     { Bad_Opcode },
7059     /* c0 */
7060     { Bad_Opcode },
7061     { Bad_Opcode },
7062     { Bad_Opcode },
7063     { Bad_Opcode },
7064     { Bad_Opcode },
7065     { Bad_Opcode },
7066     { Bad_Opcode },
7067     { Bad_Opcode },
7068     /* c8 */
7069     { Bad_Opcode },
7070     { Bad_Opcode },
7071     { Bad_Opcode },
7072     { Bad_Opcode },
7073     { PREFIX_TABLE (PREFIX_0F3ACC) },
7074     { Bad_Opcode },
7075     { Bad_Opcode },
7076     { Bad_Opcode },
7077     /* d0 */
7078     { Bad_Opcode },
7079     { Bad_Opcode },
7080     { Bad_Opcode },
7081     { Bad_Opcode },
7082     { Bad_Opcode },
7083     { Bad_Opcode },
7084     { Bad_Opcode },
7085     { Bad_Opcode },
7086     /* d8 */
7087     { Bad_Opcode },
7088     { Bad_Opcode },
7089     { Bad_Opcode },
7090     { Bad_Opcode },
7091     { Bad_Opcode },
7092     { Bad_Opcode },
7093     { Bad_Opcode },
7094     { PREFIX_TABLE (PREFIX_0F3ADF) },
7095     /* e0 */
7096     { Bad_Opcode },
7097     { Bad_Opcode },
7098     { Bad_Opcode },
7099     { Bad_Opcode },
7100     { Bad_Opcode },
7101     { Bad_Opcode },
7102     { Bad_Opcode },
7103     { Bad_Opcode },
7104     /* e8 */
7105     { Bad_Opcode },
7106     { Bad_Opcode },
7107     { Bad_Opcode },
7108     { Bad_Opcode },
7109     { Bad_Opcode },
7110     { Bad_Opcode },
7111     { Bad_Opcode },
7112     { Bad_Opcode },
7113     /* f0 */
7114     { Bad_Opcode },
7115     { Bad_Opcode },
7116     { Bad_Opcode },
7117     { Bad_Opcode },
7118     { Bad_Opcode },
7119     { Bad_Opcode },
7120     { Bad_Opcode },
7121     { Bad_Opcode },
7122     /* f8 */
7123     { Bad_Opcode },
7124     { Bad_Opcode },
7125     { Bad_Opcode },
7126     { Bad_Opcode },
7127     { Bad_Opcode },
7128     { Bad_Opcode },
7129     { Bad_Opcode },
7130     { Bad_Opcode },
7131   },
7132
7133   /* THREE_BYTE_0F7A */
7134   {
7135     /* 00 */
7136     { Bad_Opcode },
7137     { Bad_Opcode },
7138     { Bad_Opcode },
7139     { Bad_Opcode },
7140     { Bad_Opcode },
7141     { Bad_Opcode },
7142     { Bad_Opcode },
7143     { Bad_Opcode },
7144     /* 08 */
7145     { Bad_Opcode },
7146     { Bad_Opcode },
7147     { Bad_Opcode },
7148     { Bad_Opcode },
7149     { Bad_Opcode },
7150     { Bad_Opcode },
7151     { Bad_Opcode },
7152     { Bad_Opcode },
7153     /* 10 */
7154     { Bad_Opcode },
7155     { Bad_Opcode },
7156     { Bad_Opcode },
7157     { Bad_Opcode },
7158     { Bad_Opcode },
7159     { Bad_Opcode },
7160     { Bad_Opcode },
7161     { Bad_Opcode },
7162     /* 18 */
7163     { Bad_Opcode },
7164     { Bad_Opcode },
7165     { Bad_Opcode },
7166     { Bad_Opcode },
7167     { Bad_Opcode },
7168     { Bad_Opcode },
7169     { Bad_Opcode },
7170     { Bad_Opcode },
7171     /* 20 */
7172     { "ptest",          { XX } },
7173     { Bad_Opcode },
7174     { Bad_Opcode },
7175     { Bad_Opcode },
7176     { Bad_Opcode },
7177     { Bad_Opcode },
7178     { Bad_Opcode },
7179     { Bad_Opcode },
7180     /* 28 */
7181     { Bad_Opcode },
7182     { Bad_Opcode },
7183     { Bad_Opcode },
7184     { Bad_Opcode },
7185     { Bad_Opcode },
7186     { Bad_Opcode },
7187     { Bad_Opcode },
7188     { Bad_Opcode },
7189     /* 30 */
7190     { Bad_Opcode },
7191     { Bad_Opcode },
7192     { Bad_Opcode },
7193     { Bad_Opcode },
7194     { Bad_Opcode },
7195     { Bad_Opcode },
7196     { Bad_Opcode },
7197     { Bad_Opcode },
7198     /* 38 */
7199     { Bad_Opcode },
7200     { Bad_Opcode },
7201     { Bad_Opcode },
7202     { Bad_Opcode },
7203     { Bad_Opcode },
7204     { Bad_Opcode },
7205     { Bad_Opcode },
7206     { Bad_Opcode },
7207     /* 40 */
7208     { Bad_Opcode },
7209     { "phaddbw",        { XM, EXq } },
7210     { "phaddbd",        { XM, EXq } },
7211     { "phaddbq",        { XM, EXq } },
7212     { Bad_Opcode },
7213     { Bad_Opcode },
7214     { "phaddwd",        { XM, EXq } },
7215     { "phaddwq",        { XM, EXq } },
7216     /* 48 */
7217     { Bad_Opcode },
7218     { Bad_Opcode },
7219     { Bad_Opcode },
7220     { "phadddq",        { XM, EXq } },
7221     { Bad_Opcode },
7222     { Bad_Opcode },
7223     { Bad_Opcode },
7224     { Bad_Opcode },
7225     /* 50 */
7226     { Bad_Opcode },
7227     { "phaddubw",       { XM, EXq } },
7228     { "phaddubd",       { XM, EXq } },
7229     { "phaddubq",       { XM, EXq } },
7230     { Bad_Opcode },
7231     { Bad_Opcode },
7232     { "phadduwd",       { XM, EXq } },
7233     { "phadduwq",       { XM, EXq } },
7234     /* 58 */
7235     { Bad_Opcode },
7236     { Bad_Opcode },
7237     { Bad_Opcode },
7238     { "phaddudq",       { XM, EXq } },
7239     { Bad_Opcode },
7240     { Bad_Opcode },
7241     { Bad_Opcode },
7242     { Bad_Opcode },
7243     /* 60 */
7244     { Bad_Opcode },
7245     { "phsubbw",        { XM, EXq } },
7246     { "phsubbd",        { XM, EXq } },
7247     { "phsubbq",        { XM, EXq } },
7248     { Bad_Opcode },
7249     { Bad_Opcode },
7250     { Bad_Opcode },
7251     { Bad_Opcode },
7252     /* 68 */
7253     { Bad_Opcode },
7254     { Bad_Opcode },
7255     { Bad_Opcode },
7256     { Bad_Opcode },
7257     { Bad_Opcode },
7258     { Bad_Opcode },
7259     { Bad_Opcode },
7260     { Bad_Opcode },
7261     /* 70 */
7262     { Bad_Opcode },
7263     { Bad_Opcode },
7264     { Bad_Opcode },
7265     { Bad_Opcode },
7266     { Bad_Opcode },
7267     { Bad_Opcode },
7268     { Bad_Opcode },
7269     { Bad_Opcode },
7270     /* 78 */
7271     { Bad_Opcode },
7272     { Bad_Opcode },
7273     { Bad_Opcode },
7274     { Bad_Opcode },
7275     { Bad_Opcode },
7276     { Bad_Opcode },
7277     { Bad_Opcode },
7278     { Bad_Opcode },
7279     /* 80 */
7280     { Bad_Opcode },
7281     { Bad_Opcode },
7282     { Bad_Opcode },
7283     { Bad_Opcode },
7284     { Bad_Opcode },
7285     { Bad_Opcode },
7286     { Bad_Opcode },
7287     { Bad_Opcode },
7288     /* 88 */
7289     { Bad_Opcode },
7290     { Bad_Opcode },
7291     { Bad_Opcode },
7292     { Bad_Opcode },
7293     { Bad_Opcode },
7294     { Bad_Opcode },
7295     { Bad_Opcode },
7296     { Bad_Opcode },
7297     /* 90 */
7298     { Bad_Opcode },
7299     { Bad_Opcode },
7300     { Bad_Opcode },
7301     { Bad_Opcode },
7302     { Bad_Opcode },
7303     { Bad_Opcode },
7304     { Bad_Opcode },
7305     { Bad_Opcode },
7306     /* 98 */
7307     { Bad_Opcode },
7308     { Bad_Opcode },
7309     { Bad_Opcode },
7310     { Bad_Opcode },
7311     { Bad_Opcode },
7312     { Bad_Opcode },
7313     { Bad_Opcode },
7314     { Bad_Opcode },
7315     /* a0 */
7316     { Bad_Opcode },
7317     { Bad_Opcode },
7318     { Bad_Opcode },
7319     { Bad_Opcode },
7320     { Bad_Opcode },
7321     { Bad_Opcode },
7322     { Bad_Opcode },
7323     { Bad_Opcode },
7324     /* a8 */
7325     { Bad_Opcode },
7326     { Bad_Opcode },
7327     { Bad_Opcode },
7328     { Bad_Opcode },
7329     { Bad_Opcode },
7330     { Bad_Opcode },
7331     { Bad_Opcode },
7332     { Bad_Opcode },
7333     /* b0 */
7334     { Bad_Opcode },
7335     { Bad_Opcode },
7336     { Bad_Opcode },
7337     { Bad_Opcode },
7338     { Bad_Opcode },
7339     { Bad_Opcode },
7340     { Bad_Opcode },
7341     { Bad_Opcode },
7342     /* b8 */
7343     { Bad_Opcode },
7344     { Bad_Opcode },
7345     { Bad_Opcode },
7346     { Bad_Opcode },
7347     { Bad_Opcode },
7348     { Bad_Opcode },
7349     { Bad_Opcode },
7350     { Bad_Opcode },
7351     /* c0 */
7352     { Bad_Opcode },
7353     { Bad_Opcode },
7354     { Bad_Opcode },
7355     { Bad_Opcode },
7356     { Bad_Opcode },
7357     { Bad_Opcode },
7358     { Bad_Opcode },
7359     { Bad_Opcode },
7360     /* c8 */
7361     { Bad_Opcode },
7362     { Bad_Opcode },
7363     { Bad_Opcode },
7364     { Bad_Opcode },
7365     { Bad_Opcode },
7366     { Bad_Opcode },
7367     { Bad_Opcode },
7368     { Bad_Opcode },
7369     /* d0 */
7370     { Bad_Opcode },
7371     { Bad_Opcode },
7372     { Bad_Opcode },
7373     { Bad_Opcode },
7374     { Bad_Opcode },
7375     { Bad_Opcode },
7376     { Bad_Opcode },
7377     { Bad_Opcode },
7378     /* d8 */
7379     { Bad_Opcode },
7380     { Bad_Opcode },
7381     { Bad_Opcode },
7382     { Bad_Opcode },
7383     { Bad_Opcode },
7384     { Bad_Opcode },
7385     { Bad_Opcode },
7386     { Bad_Opcode },
7387     /* e0 */
7388     { Bad_Opcode },
7389     { Bad_Opcode },
7390     { Bad_Opcode },
7391     { Bad_Opcode },
7392     { Bad_Opcode },
7393     { Bad_Opcode },
7394     { Bad_Opcode },
7395     { Bad_Opcode },
7396     /* e8 */
7397     { Bad_Opcode },
7398     { Bad_Opcode },
7399     { Bad_Opcode },
7400     { Bad_Opcode },
7401     { Bad_Opcode },
7402     { Bad_Opcode },
7403     { Bad_Opcode },
7404     { Bad_Opcode },
7405     /* f0 */
7406     { Bad_Opcode },
7407     { Bad_Opcode },
7408     { Bad_Opcode },
7409     { Bad_Opcode },
7410     { Bad_Opcode },
7411     { Bad_Opcode },
7412     { Bad_Opcode },
7413     { Bad_Opcode },
7414     /* f8 */
7415     { Bad_Opcode },
7416     { Bad_Opcode },
7417     { Bad_Opcode },
7418     { Bad_Opcode },
7419     { Bad_Opcode },
7420     { Bad_Opcode },
7421     { Bad_Opcode },
7422     { Bad_Opcode },
7423   },
7424 };
7425
7426 static const struct dis386 xop_table[][256] = {
7427   /* XOP_08 */
7428   {
7429     /* 00 */
7430     { Bad_Opcode },
7431     { Bad_Opcode },
7432     { Bad_Opcode },
7433     { Bad_Opcode },
7434     { Bad_Opcode },
7435     { Bad_Opcode },
7436     { Bad_Opcode },
7437     { Bad_Opcode },
7438     /* 08 */
7439     { Bad_Opcode },
7440     { Bad_Opcode },
7441     { Bad_Opcode },
7442     { Bad_Opcode },
7443     { Bad_Opcode },
7444     { Bad_Opcode },
7445     { Bad_Opcode },
7446     { Bad_Opcode },
7447     /* 10 */
7448     { Bad_Opcode },
7449     { Bad_Opcode },
7450     { Bad_Opcode },
7451     { Bad_Opcode },
7452     { Bad_Opcode },
7453     { Bad_Opcode },
7454     { Bad_Opcode },
7455     { Bad_Opcode },
7456     /* 18 */
7457     { Bad_Opcode },
7458     { Bad_Opcode },
7459     { Bad_Opcode },
7460     { Bad_Opcode },
7461     { Bad_Opcode },
7462     { Bad_Opcode },
7463     { Bad_Opcode },
7464     { Bad_Opcode },
7465     /* 20 */
7466     { Bad_Opcode },
7467     { Bad_Opcode },
7468     { Bad_Opcode },
7469     { Bad_Opcode },
7470     { Bad_Opcode },
7471     { Bad_Opcode },
7472     { Bad_Opcode },
7473     { Bad_Opcode },
7474     /* 28 */
7475     { Bad_Opcode },
7476     { Bad_Opcode },
7477     { Bad_Opcode },
7478     { Bad_Opcode },
7479     { Bad_Opcode },
7480     { Bad_Opcode },
7481     { Bad_Opcode },
7482     { Bad_Opcode },
7483     /* 30 */
7484     { Bad_Opcode },
7485     { Bad_Opcode },
7486     { Bad_Opcode },
7487     { Bad_Opcode },
7488     { Bad_Opcode },
7489     { Bad_Opcode },
7490     { Bad_Opcode },
7491     { Bad_Opcode },
7492     /* 38 */
7493     { Bad_Opcode },
7494     { Bad_Opcode },
7495     { Bad_Opcode },
7496     { Bad_Opcode },
7497     { Bad_Opcode },
7498     { Bad_Opcode },
7499     { Bad_Opcode },
7500     { Bad_Opcode },
7501     /* 40 */
7502     { Bad_Opcode },
7503     { Bad_Opcode },
7504     { Bad_Opcode },
7505     { Bad_Opcode },
7506     { Bad_Opcode },
7507     { Bad_Opcode },
7508     { Bad_Opcode },
7509     { Bad_Opcode },
7510     /* 48 */
7511     { Bad_Opcode },
7512     { Bad_Opcode },
7513     { Bad_Opcode },
7514     { Bad_Opcode },
7515     { Bad_Opcode },
7516     { Bad_Opcode },
7517     { Bad_Opcode },
7518     { Bad_Opcode },
7519     /* 50 */
7520     { Bad_Opcode },
7521     { Bad_Opcode },
7522     { Bad_Opcode },
7523     { Bad_Opcode },
7524     { Bad_Opcode },
7525     { Bad_Opcode },
7526     { Bad_Opcode },
7527     { Bad_Opcode },
7528     /* 58 */
7529     { Bad_Opcode },
7530     { Bad_Opcode },
7531     { Bad_Opcode },
7532     { Bad_Opcode },
7533     { Bad_Opcode },
7534     { Bad_Opcode },
7535     { Bad_Opcode },
7536     { Bad_Opcode },
7537     /* 60 */
7538     { Bad_Opcode },
7539     { Bad_Opcode },
7540     { Bad_Opcode },
7541     { Bad_Opcode },
7542     { Bad_Opcode },
7543     { Bad_Opcode },
7544     { Bad_Opcode },
7545     { Bad_Opcode },
7546     /* 68 */
7547     { Bad_Opcode },
7548     { Bad_Opcode },
7549     { Bad_Opcode },
7550     { Bad_Opcode },
7551     { Bad_Opcode },
7552     { Bad_Opcode },
7553     { Bad_Opcode },
7554     { Bad_Opcode },
7555     /* 70 */
7556     { Bad_Opcode },
7557     { Bad_Opcode },
7558     { Bad_Opcode },
7559     { Bad_Opcode },
7560     { Bad_Opcode },
7561     { Bad_Opcode },
7562     { Bad_Opcode },
7563     { Bad_Opcode },
7564     /* 78 */
7565     { Bad_Opcode },
7566     { Bad_Opcode },
7567     { Bad_Opcode },
7568     { Bad_Opcode },
7569     { Bad_Opcode },
7570     { Bad_Opcode },
7571     { Bad_Opcode },
7572     { Bad_Opcode },
7573     /* 80 */
7574     { Bad_Opcode },
7575     { Bad_Opcode },
7576     { Bad_Opcode },
7577     { Bad_Opcode },
7578     { Bad_Opcode },
7579     { "vpmacssww",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7580     { "vpmacsswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7581     { "vpmacssdql",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7582     /* 88 */
7583     { Bad_Opcode },
7584     { Bad_Opcode },
7585     { Bad_Opcode },
7586     { Bad_Opcode },
7587     { Bad_Opcode },
7588     { Bad_Opcode },
7589     { "vpmacssdd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7590     { "vpmacssdqh",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7591     /* 90 */
7592     { Bad_Opcode },
7593     { Bad_Opcode },
7594     { Bad_Opcode },
7595     { Bad_Opcode },
7596     { Bad_Opcode },
7597     { "vpmacsww",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7598     { "vpmacswd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7599     { "vpmacsdql",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7600     /* 98 */
7601     { Bad_Opcode },
7602     { Bad_Opcode },
7603     { Bad_Opcode },
7604     { Bad_Opcode },
7605     { Bad_Opcode },
7606     { Bad_Opcode },
7607     { "vpmacsdd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7608     { "vpmacsdqh",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7609     /* a0 */
7610     { Bad_Opcode },
7611     { Bad_Opcode },
7612     { "vpcmov",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7613     { "vpperm",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7614     { Bad_Opcode },
7615     { Bad_Opcode },
7616     { "vpmadcsswd",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7617     { Bad_Opcode },
7618     /* a8 */
7619     { Bad_Opcode },
7620     { Bad_Opcode },
7621     { Bad_Opcode },
7622     { Bad_Opcode },
7623     { Bad_Opcode },
7624     { Bad_Opcode },
7625     { Bad_Opcode },
7626     { Bad_Opcode },
7627     /* b0 */
7628     { Bad_Opcode },
7629     { Bad_Opcode },
7630     { Bad_Opcode },
7631     { Bad_Opcode },
7632     { Bad_Opcode },
7633     { Bad_Opcode },
7634     { "vpmadcswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7635     { Bad_Opcode },
7636     /* b8 */
7637     { Bad_Opcode },
7638     { Bad_Opcode },
7639     { Bad_Opcode },
7640     { Bad_Opcode },
7641     { Bad_Opcode },
7642     { Bad_Opcode },
7643     { Bad_Opcode },
7644     { Bad_Opcode },
7645     /* c0 */
7646     { "vprotb",         { XM, Vex_2src_1, Ib } },
7647     { "vprotw",         { XM, Vex_2src_1, Ib } },
7648     { "vprotd",         { XM, Vex_2src_1, Ib } },
7649     { "vprotq",         { XM, Vex_2src_1, Ib } },
7650     { Bad_Opcode },
7651     { Bad_Opcode },
7652     { Bad_Opcode },
7653     { Bad_Opcode },
7654     /* c8 */
7655     { Bad_Opcode },
7656     { Bad_Opcode },
7657     { Bad_Opcode },
7658     { Bad_Opcode },
7659     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
7660     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
7661     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
7662     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
7663     /* d0 */
7664     { Bad_Opcode },
7665     { Bad_Opcode },
7666     { Bad_Opcode },
7667     { Bad_Opcode },
7668     { Bad_Opcode },
7669     { Bad_Opcode },
7670     { Bad_Opcode },
7671     { Bad_Opcode },
7672     /* d8 */
7673     { Bad_Opcode },
7674     { Bad_Opcode },
7675     { Bad_Opcode },
7676     { Bad_Opcode },
7677     { Bad_Opcode },
7678     { Bad_Opcode },
7679     { Bad_Opcode },
7680     { Bad_Opcode },
7681     /* e0 */
7682     { Bad_Opcode },
7683     { Bad_Opcode },
7684     { Bad_Opcode },
7685     { Bad_Opcode },
7686     { Bad_Opcode },
7687     { Bad_Opcode },
7688     { Bad_Opcode },
7689     { Bad_Opcode },
7690     /* e8 */
7691     { Bad_Opcode },
7692     { Bad_Opcode },
7693     { Bad_Opcode },
7694     { Bad_Opcode },
7695     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
7696     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
7697     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
7698     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
7699     /* f0 */
7700     { Bad_Opcode },
7701     { Bad_Opcode },
7702     { Bad_Opcode },
7703     { Bad_Opcode },
7704     { Bad_Opcode },
7705     { Bad_Opcode },
7706     { Bad_Opcode },
7707     { Bad_Opcode },
7708     /* f8 */
7709     { Bad_Opcode },
7710     { Bad_Opcode },
7711     { Bad_Opcode },
7712     { Bad_Opcode },
7713     { Bad_Opcode },
7714     { Bad_Opcode },
7715     { Bad_Opcode },
7716     { Bad_Opcode },
7717   },
7718   /* XOP_09 */
7719   {
7720     /* 00 */
7721     { Bad_Opcode },
7722     { REG_TABLE (REG_XOP_TBM_01) },
7723     { REG_TABLE (REG_XOP_TBM_02) },
7724     { Bad_Opcode },
7725     { Bad_Opcode },
7726     { Bad_Opcode },
7727     { Bad_Opcode },
7728     { Bad_Opcode },
7729     /* 08 */
7730     { Bad_Opcode },
7731     { Bad_Opcode },
7732     { Bad_Opcode },
7733     { Bad_Opcode },
7734     { Bad_Opcode },
7735     { Bad_Opcode },
7736     { Bad_Opcode },
7737     { Bad_Opcode },
7738     /* 10 */
7739     { Bad_Opcode },
7740     { Bad_Opcode },
7741     { REG_TABLE (REG_XOP_LWPCB) },
7742     { Bad_Opcode },
7743     { Bad_Opcode },
7744     { Bad_Opcode },
7745     { Bad_Opcode },
7746     { Bad_Opcode },
7747     /* 18 */
7748     { Bad_Opcode },
7749     { Bad_Opcode },
7750     { Bad_Opcode },
7751     { Bad_Opcode },
7752     { Bad_Opcode },
7753     { Bad_Opcode },
7754     { Bad_Opcode },
7755     { Bad_Opcode },
7756     /* 20 */
7757     { Bad_Opcode },
7758     { Bad_Opcode },
7759     { Bad_Opcode },
7760     { Bad_Opcode },
7761     { Bad_Opcode },
7762     { Bad_Opcode },
7763     { Bad_Opcode },
7764     { Bad_Opcode },
7765     /* 28 */
7766     { Bad_Opcode },
7767     { Bad_Opcode },
7768     { Bad_Opcode },
7769     { Bad_Opcode },
7770     { Bad_Opcode },
7771     { Bad_Opcode },
7772     { Bad_Opcode },
7773     { Bad_Opcode },
7774     /* 30 */
7775     { Bad_Opcode },
7776     { Bad_Opcode },
7777     { Bad_Opcode },
7778     { Bad_Opcode },
7779     { Bad_Opcode },
7780     { Bad_Opcode },
7781     { Bad_Opcode },
7782     { Bad_Opcode },
7783     /* 38 */
7784     { Bad_Opcode },
7785     { Bad_Opcode },
7786     { Bad_Opcode },
7787     { Bad_Opcode },
7788     { Bad_Opcode },
7789     { Bad_Opcode },
7790     { Bad_Opcode },
7791     { Bad_Opcode },
7792     /* 40 */
7793     { Bad_Opcode },
7794     { Bad_Opcode },
7795     { Bad_Opcode },
7796     { Bad_Opcode },
7797     { Bad_Opcode },
7798     { Bad_Opcode },
7799     { Bad_Opcode },
7800     { Bad_Opcode },
7801     /* 48 */
7802     { Bad_Opcode },
7803     { Bad_Opcode },
7804     { Bad_Opcode },
7805     { Bad_Opcode },
7806     { Bad_Opcode },
7807     { Bad_Opcode },
7808     { Bad_Opcode },
7809     { Bad_Opcode },
7810     /* 50 */
7811     { Bad_Opcode },
7812     { Bad_Opcode },
7813     { Bad_Opcode },
7814     { Bad_Opcode },
7815     { Bad_Opcode },
7816     { Bad_Opcode },
7817     { Bad_Opcode },
7818     { Bad_Opcode },
7819     /* 58 */
7820     { Bad_Opcode },
7821     { Bad_Opcode },
7822     { Bad_Opcode },
7823     { Bad_Opcode },
7824     { Bad_Opcode },
7825     { Bad_Opcode },
7826     { Bad_Opcode },
7827     { Bad_Opcode },
7828     /* 60 */
7829     { Bad_Opcode },
7830     { Bad_Opcode },
7831     { Bad_Opcode },
7832     { Bad_Opcode },
7833     { Bad_Opcode },
7834     { Bad_Opcode },
7835     { Bad_Opcode },
7836     { Bad_Opcode },
7837     /* 68 */
7838     { Bad_Opcode },
7839     { Bad_Opcode },
7840     { Bad_Opcode },
7841     { Bad_Opcode },
7842     { Bad_Opcode },
7843     { Bad_Opcode },
7844     { Bad_Opcode },
7845     { Bad_Opcode },
7846     /* 70 */
7847     { Bad_Opcode },
7848     { Bad_Opcode },
7849     { Bad_Opcode },
7850     { Bad_Opcode },
7851     { Bad_Opcode },
7852     { Bad_Opcode },
7853     { Bad_Opcode },
7854     { Bad_Opcode },
7855     /* 78 */
7856     { Bad_Opcode },
7857     { Bad_Opcode },
7858     { Bad_Opcode },
7859     { Bad_Opcode },
7860     { Bad_Opcode },
7861     { Bad_Opcode },
7862     { Bad_Opcode },
7863     { Bad_Opcode },
7864     /* 80 */
7865     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
7866     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
7867     { "vfrczss",        { XM, EXd } },
7868     { "vfrczsd",        { XM, EXq } },
7869     { Bad_Opcode },
7870     { Bad_Opcode },
7871     { Bad_Opcode },
7872     { Bad_Opcode },
7873     /* 88 */
7874     { Bad_Opcode },
7875     { Bad_Opcode },
7876     { Bad_Opcode },
7877     { Bad_Opcode },
7878     { Bad_Opcode },
7879     { Bad_Opcode },
7880     { Bad_Opcode },
7881     { Bad_Opcode },
7882     /* 90 */
7883     { "vprotb",         { XM, Vex_2src_1, Vex_2src_2 } },
7884     { "vprotw",         { XM, Vex_2src_1, Vex_2src_2 } },
7885     { "vprotd",         { XM, Vex_2src_1, Vex_2src_2 } },
7886     { "vprotq",         { XM, Vex_2src_1, Vex_2src_2 } },
7887     { "vpshlb",         { XM, Vex_2src_1, Vex_2src_2 } },
7888     { "vpshlw",         { XM, Vex_2src_1, Vex_2src_2 } },
7889     { "vpshld",         { XM, Vex_2src_1, Vex_2src_2 } },
7890     { "vpshlq",         { XM, Vex_2src_1, Vex_2src_2 } },
7891     /* 98 */
7892     { "vpshab",         { XM, Vex_2src_1, Vex_2src_2 } },
7893     { "vpshaw",         { XM, Vex_2src_1, Vex_2src_2 } },
7894     { "vpshad",         { XM, Vex_2src_1, Vex_2src_2 } },
7895     { "vpshaq",         { XM, Vex_2src_1, Vex_2src_2 } },
7896     { Bad_Opcode },
7897     { Bad_Opcode },
7898     { Bad_Opcode },
7899     { Bad_Opcode },
7900     /* a0 */
7901     { Bad_Opcode },
7902     { Bad_Opcode },
7903     { Bad_Opcode },
7904     { Bad_Opcode },
7905     { Bad_Opcode },
7906     { Bad_Opcode },
7907     { Bad_Opcode },
7908     { Bad_Opcode },
7909     /* a8 */
7910     { Bad_Opcode },
7911     { Bad_Opcode },
7912     { Bad_Opcode },
7913     { Bad_Opcode },
7914     { Bad_Opcode },
7915     { Bad_Opcode },
7916     { Bad_Opcode },
7917     { Bad_Opcode },
7918     /* b0 */
7919     { Bad_Opcode },
7920     { Bad_Opcode },
7921     { Bad_Opcode },
7922     { Bad_Opcode },
7923     { Bad_Opcode },
7924     { Bad_Opcode },
7925     { Bad_Opcode },
7926     { Bad_Opcode },
7927     /* b8 */
7928     { Bad_Opcode },
7929     { Bad_Opcode },
7930     { Bad_Opcode },
7931     { Bad_Opcode },
7932     { Bad_Opcode },
7933     { Bad_Opcode },
7934     { Bad_Opcode },
7935     { Bad_Opcode },
7936     /* c0 */
7937     { Bad_Opcode },
7938     { "vphaddbw",       { XM, EXxmm } },
7939     { "vphaddbd",       { XM, EXxmm } },
7940     { "vphaddbq",       { XM, EXxmm } },
7941     { Bad_Opcode },
7942     { Bad_Opcode },
7943     { "vphaddwd",       { XM, EXxmm } },
7944     { "vphaddwq",       { XM, EXxmm } },
7945     /* c8 */
7946     { Bad_Opcode },
7947     { Bad_Opcode },
7948     { Bad_Opcode },
7949     { "vphadddq",       { XM, EXxmm } },
7950     { Bad_Opcode },
7951     { Bad_Opcode },
7952     { Bad_Opcode },
7953     { Bad_Opcode },
7954     /* d0 */
7955     { Bad_Opcode },
7956     { "vphaddubw",      { XM, EXxmm } },
7957     { "vphaddubd",      { XM, EXxmm } },
7958     { "vphaddubq",      { XM, EXxmm } },
7959     { Bad_Opcode },
7960     { Bad_Opcode },
7961     { "vphadduwd",      { XM, EXxmm } },
7962     { "vphadduwq",      { XM, EXxmm } },
7963     /* d8 */
7964     { Bad_Opcode },
7965     { Bad_Opcode },
7966     { Bad_Opcode },
7967     { "vphaddudq",      { XM, EXxmm } },
7968     { Bad_Opcode },
7969     { Bad_Opcode },
7970     { Bad_Opcode },
7971     { Bad_Opcode },
7972     /* e0 */
7973     { Bad_Opcode },
7974     { "vphsubbw",       { XM, EXxmm } },
7975     { "vphsubwd",       { XM, EXxmm } },
7976     { "vphsubdq",       { XM, EXxmm } },
7977     { Bad_Opcode },
7978     { Bad_Opcode },
7979     { Bad_Opcode },
7980     { Bad_Opcode },
7981     /* e8 */
7982     { Bad_Opcode },
7983     { Bad_Opcode },
7984     { Bad_Opcode },
7985     { Bad_Opcode },
7986     { Bad_Opcode },
7987     { Bad_Opcode },
7988     { Bad_Opcode },
7989     { Bad_Opcode },
7990     /* f0 */
7991     { Bad_Opcode },
7992     { Bad_Opcode },
7993     { Bad_Opcode },
7994     { Bad_Opcode },
7995     { Bad_Opcode },
7996     { Bad_Opcode },
7997     { Bad_Opcode },
7998     { Bad_Opcode },
7999     /* f8 */
8000     { Bad_Opcode },
8001     { Bad_Opcode },
8002     { Bad_Opcode },
8003     { Bad_Opcode },
8004     { Bad_Opcode },
8005     { Bad_Opcode },
8006     { Bad_Opcode },
8007     { Bad_Opcode },
8008   },
8009   /* XOP_0A */
8010   {
8011     /* 00 */
8012     { Bad_Opcode },
8013     { Bad_Opcode },
8014     { Bad_Opcode },
8015     { Bad_Opcode },
8016     { Bad_Opcode },
8017     { Bad_Opcode },
8018     { Bad_Opcode },
8019     { Bad_Opcode },
8020     /* 08 */
8021     { Bad_Opcode },
8022     { Bad_Opcode },
8023     { Bad_Opcode },
8024     { Bad_Opcode },
8025     { Bad_Opcode },
8026     { Bad_Opcode },
8027     { Bad_Opcode },
8028     { Bad_Opcode },
8029     /* 10 */
8030     { "bextr",  { Gv, Ev, Iq } },
8031     { Bad_Opcode },
8032     { REG_TABLE (REG_XOP_LWP) },
8033     { Bad_Opcode },
8034     { Bad_Opcode },
8035     { Bad_Opcode },
8036     { Bad_Opcode },
8037     { Bad_Opcode },
8038     /* 18 */
8039     { Bad_Opcode },
8040     { Bad_Opcode },
8041     { Bad_Opcode },
8042     { Bad_Opcode },
8043     { Bad_Opcode },
8044     { Bad_Opcode },
8045     { Bad_Opcode },
8046     { Bad_Opcode },
8047     /* 20 */
8048     { Bad_Opcode },
8049     { Bad_Opcode },
8050     { Bad_Opcode },
8051     { Bad_Opcode },
8052     { Bad_Opcode },
8053     { Bad_Opcode },
8054     { Bad_Opcode },
8055     { Bad_Opcode },
8056     /* 28 */
8057     { Bad_Opcode },
8058     { Bad_Opcode },
8059     { Bad_Opcode },
8060     { Bad_Opcode },
8061     { Bad_Opcode },
8062     { Bad_Opcode },
8063     { Bad_Opcode },
8064     { Bad_Opcode },
8065     /* 30 */
8066     { Bad_Opcode },
8067     { Bad_Opcode },
8068     { Bad_Opcode },
8069     { Bad_Opcode },
8070     { Bad_Opcode },
8071     { Bad_Opcode },
8072     { Bad_Opcode },
8073     { Bad_Opcode },
8074     /* 38 */
8075     { Bad_Opcode },
8076     { Bad_Opcode },
8077     { Bad_Opcode },
8078     { Bad_Opcode },
8079     { Bad_Opcode },
8080     { Bad_Opcode },
8081     { Bad_Opcode },
8082     { Bad_Opcode },
8083     /* 40 */
8084     { Bad_Opcode },
8085     { Bad_Opcode },
8086     { Bad_Opcode },
8087     { Bad_Opcode },
8088     { Bad_Opcode },
8089     { Bad_Opcode },
8090     { Bad_Opcode },
8091     { Bad_Opcode },
8092     /* 48 */
8093     { Bad_Opcode },
8094     { Bad_Opcode },
8095     { Bad_Opcode },
8096     { Bad_Opcode },
8097     { Bad_Opcode },
8098     { Bad_Opcode },
8099     { Bad_Opcode },
8100     { Bad_Opcode },
8101     /* 50 */
8102     { Bad_Opcode },
8103     { Bad_Opcode },
8104     { Bad_Opcode },
8105     { Bad_Opcode },
8106     { Bad_Opcode },
8107     { Bad_Opcode },
8108     { Bad_Opcode },
8109     { Bad_Opcode },
8110     /* 58 */
8111     { Bad_Opcode },
8112     { Bad_Opcode },
8113     { Bad_Opcode },
8114     { Bad_Opcode },
8115     { Bad_Opcode },
8116     { Bad_Opcode },
8117     { Bad_Opcode },
8118     { Bad_Opcode },
8119     /* 60 */
8120     { Bad_Opcode },
8121     { Bad_Opcode },
8122     { Bad_Opcode },
8123     { Bad_Opcode },
8124     { Bad_Opcode },
8125     { Bad_Opcode },
8126     { Bad_Opcode },
8127     { Bad_Opcode },
8128     /* 68 */
8129     { Bad_Opcode },
8130     { Bad_Opcode },
8131     { Bad_Opcode },
8132     { Bad_Opcode },
8133     { Bad_Opcode },
8134     { Bad_Opcode },
8135     { Bad_Opcode },
8136     { Bad_Opcode },
8137     /* 70 */
8138     { Bad_Opcode },
8139     { Bad_Opcode },
8140     { Bad_Opcode },
8141     { Bad_Opcode },
8142     { Bad_Opcode },
8143     { Bad_Opcode },
8144     { Bad_Opcode },
8145     { Bad_Opcode },
8146     /* 78 */
8147     { Bad_Opcode },
8148     { Bad_Opcode },
8149     { Bad_Opcode },
8150     { Bad_Opcode },
8151     { Bad_Opcode },
8152     { Bad_Opcode },
8153     { Bad_Opcode },
8154     { Bad_Opcode },
8155     /* 80 */
8156     { Bad_Opcode },
8157     { Bad_Opcode },
8158     { Bad_Opcode },
8159     { Bad_Opcode },
8160     { Bad_Opcode },
8161     { Bad_Opcode },
8162     { Bad_Opcode },
8163     { Bad_Opcode },
8164     /* 88 */
8165     { Bad_Opcode },
8166     { Bad_Opcode },
8167     { Bad_Opcode },
8168     { Bad_Opcode },
8169     { Bad_Opcode },
8170     { Bad_Opcode },
8171     { Bad_Opcode },
8172     { Bad_Opcode },
8173     /* 90 */
8174     { Bad_Opcode },
8175     { Bad_Opcode },
8176     { Bad_Opcode },
8177     { Bad_Opcode },
8178     { Bad_Opcode },
8179     { Bad_Opcode },
8180     { Bad_Opcode },
8181     { Bad_Opcode },
8182     /* 98 */
8183     { Bad_Opcode },
8184     { Bad_Opcode },
8185     { Bad_Opcode },
8186     { Bad_Opcode },
8187     { Bad_Opcode },
8188     { Bad_Opcode },
8189     { Bad_Opcode },
8190     { Bad_Opcode },
8191     /* a0 */
8192     { Bad_Opcode },
8193     { Bad_Opcode },
8194     { Bad_Opcode },
8195     { Bad_Opcode },
8196     { Bad_Opcode },
8197     { Bad_Opcode },
8198     { Bad_Opcode },
8199     { Bad_Opcode },
8200     /* a8 */
8201     { Bad_Opcode },
8202     { Bad_Opcode },
8203     { Bad_Opcode },
8204     { Bad_Opcode },
8205     { Bad_Opcode },
8206     { Bad_Opcode },
8207     { Bad_Opcode },
8208     { Bad_Opcode },
8209     /* b0 */
8210     { Bad_Opcode },
8211     { Bad_Opcode },
8212     { Bad_Opcode },
8213     { Bad_Opcode },
8214     { Bad_Opcode },
8215     { Bad_Opcode },
8216     { Bad_Opcode },
8217     { Bad_Opcode },
8218     /* b8 */
8219     { Bad_Opcode },
8220     { Bad_Opcode },
8221     { Bad_Opcode },
8222     { Bad_Opcode },
8223     { Bad_Opcode },
8224     { Bad_Opcode },
8225     { Bad_Opcode },
8226     { Bad_Opcode },
8227     /* c0 */
8228     { Bad_Opcode },
8229     { Bad_Opcode },
8230     { Bad_Opcode },
8231     { Bad_Opcode },
8232     { Bad_Opcode },
8233     { Bad_Opcode },
8234     { Bad_Opcode },
8235     { Bad_Opcode },
8236     /* c8 */
8237     { Bad_Opcode },
8238     { Bad_Opcode },
8239     { Bad_Opcode },
8240     { Bad_Opcode },
8241     { Bad_Opcode },
8242     { Bad_Opcode },
8243     { Bad_Opcode },
8244     { Bad_Opcode },
8245     /* d0 */
8246     { Bad_Opcode },
8247     { Bad_Opcode },
8248     { Bad_Opcode },
8249     { Bad_Opcode },
8250     { Bad_Opcode },
8251     { Bad_Opcode },
8252     { Bad_Opcode },
8253     { Bad_Opcode },
8254     /* d8 */
8255     { Bad_Opcode },
8256     { Bad_Opcode },
8257     { Bad_Opcode },
8258     { Bad_Opcode },
8259     { Bad_Opcode },
8260     { Bad_Opcode },
8261     { Bad_Opcode },
8262     { Bad_Opcode },
8263     /* e0 */
8264     { Bad_Opcode },
8265     { Bad_Opcode },
8266     { Bad_Opcode },
8267     { Bad_Opcode },
8268     { Bad_Opcode },
8269     { Bad_Opcode },
8270     { Bad_Opcode },
8271     { Bad_Opcode },
8272     /* e8 */
8273     { Bad_Opcode },
8274     { Bad_Opcode },
8275     { Bad_Opcode },
8276     { Bad_Opcode },
8277     { Bad_Opcode },
8278     { Bad_Opcode },
8279     { Bad_Opcode },
8280     { Bad_Opcode },
8281     /* f0 */
8282     { Bad_Opcode },
8283     { Bad_Opcode },
8284     { Bad_Opcode },
8285     { Bad_Opcode },
8286     { Bad_Opcode },
8287     { Bad_Opcode },
8288     { Bad_Opcode },
8289     { Bad_Opcode },
8290     /* f8 */
8291     { Bad_Opcode },
8292     { Bad_Opcode },
8293     { Bad_Opcode },
8294     { Bad_Opcode },
8295     { Bad_Opcode },
8296     { Bad_Opcode },
8297     { Bad_Opcode },
8298     { Bad_Opcode },
8299   },
8300 };
8301
8302 static const struct dis386 vex_table[][256] = {
8303   /* VEX_0F */
8304   {
8305     /* 00 */
8306     { Bad_Opcode },
8307     { Bad_Opcode },
8308     { Bad_Opcode },
8309     { Bad_Opcode },
8310     { Bad_Opcode },
8311     { Bad_Opcode },
8312     { Bad_Opcode },
8313     { Bad_Opcode },
8314     /* 08 */
8315     { Bad_Opcode },
8316     { Bad_Opcode },
8317     { Bad_Opcode },
8318     { Bad_Opcode },
8319     { Bad_Opcode },
8320     { Bad_Opcode },
8321     { Bad_Opcode },
8322     { Bad_Opcode },
8323     /* 10 */
8324     { PREFIX_TABLE (PREFIX_VEX_0F10) },
8325     { PREFIX_TABLE (PREFIX_VEX_0F11) },
8326     { PREFIX_TABLE (PREFIX_VEX_0F12) },
8327     { MOD_TABLE (MOD_VEX_0F13) },
8328     { VEX_W_TABLE (VEX_W_0F14) },
8329     { VEX_W_TABLE (VEX_W_0F15) },
8330     { PREFIX_TABLE (PREFIX_VEX_0F16) },
8331     { MOD_TABLE (MOD_VEX_0F17) },
8332     /* 18 */
8333     { Bad_Opcode },
8334     { Bad_Opcode },
8335     { Bad_Opcode },
8336     { Bad_Opcode },
8337     { Bad_Opcode },
8338     { Bad_Opcode },
8339     { Bad_Opcode },
8340     { Bad_Opcode },
8341     /* 20 */
8342     { Bad_Opcode },
8343     { Bad_Opcode },
8344     { Bad_Opcode },
8345     { Bad_Opcode },
8346     { Bad_Opcode },
8347     { Bad_Opcode },
8348     { Bad_Opcode },
8349     { Bad_Opcode },
8350     /* 28 */
8351     { VEX_W_TABLE (VEX_W_0F28) },
8352     { VEX_W_TABLE (VEX_W_0F29) },
8353     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8354     { MOD_TABLE (MOD_VEX_0F2B) },
8355     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8356     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8357     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8358     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8359     /* 30 */
8360     { Bad_Opcode },
8361     { Bad_Opcode },
8362     { Bad_Opcode },
8363     { Bad_Opcode },
8364     { Bad_Opcode },
8365     { Bad_Opcode },
8366     { Bad_Opcode },
8367     { Bad_Opcode },
8368     /* 38 */
8369     { Bad_Opcode },
8370     { Bad_Opcode },
8371     { Bad_Opcode },
8372     { Bad_Opcode },
8373     { Bad_Opcode },
8374     { Bad_Opcode },
8375     { Bad_Opcode },
8376     { Bad_Opcode },
8377     /* 40 */
8378     { Bad_Opcode },
8379     { PREFIX_TABLE (PREFIX_VEX_0F41) },
8380     { PREFIX_TABLE (PREFIX_VEX_0F42) },
8381     { Bad_Opcode },
8382     { PREFIX_TABLE (PREFIX_VEX_0F44) },
8383     { PREFIX_TABLE (PREFIX_VEX_0F45) },
8384     { PREFIX_TABLE (PREFIX_VEX_0F46) },
8385     { PREFIX_TABLE (PREFIX_VEX_0F47) },
8386     /* 48 */
8387     { Bad_Opcode },
8388     { Bad_Opcode },
8389     { Bad_Opcode },
8390     { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8391     { Bad_Opcode },
8392     { Bad_Opcode },
8393     { Bad_Opcode },
8394     { Bad_Opcode },
8395     /* 50 */
8396     { MOD_TABLE (MOD_VEX_0F50) },
8397     { PREFIX_TABLE (PREFIX_VEX_0F51) },
8398     { PREFIX_TABLE (PREFIX_VEX_0F52) },
8399     { PREFIX_TABLE (PREFIX_VEX_0F53) },
8400     { "vandpX",         { XM, Vex, EXx } },
8401     { "vandnpX",        { XM, Vex, EXx } },
8402     { "vorpX",          { XM, Vex, EXx } },
8403     { "vxorpX",         { XM, Vex, EXx } },
8404     /* 58 */
8405     { PREFIX_TABLE (PREFIX_VEX_0F58) },
8406     { PREFIX_TABLE (PREFIX_VEX_0F59) },
8407     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8408     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8409     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8410     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8411     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8412     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8413     /* 60 */
8414     { PREFIX_TABLE (PREFIX_VEX_0F60) },
8415     { PREFIX_TABLE (PREFIX_VEX_0F61) },
8416     { PREFIX_TABLE (PREFIX_VEX_0F62) },
8417     { PREFIX_TABLE (PREFIX_VEX_0F63) },
8418     { PREFIX_TABLE (PREFIX_VEX_0F64) },
8419     { PREFIX_TABLE (PREFIX_VEX_0F65) },
8420     { PREFIX_TABLE (PREFIX_VEX_0F66) },
8421     { PREFIX_TABLE (PREFIX_VEX_0F67) },
8422     /* 68 */
8423     { PREFIX_TABLE (PREFIX_VEX_0F68) },
8424     { PREFIX_TABLE (PREFIX_VEX_0F69) },
8425     { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8426     { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8427     { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8428     { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8429     { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8430     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8431     /* 70 */
8432     { PREFIX_TABLE (PREFIX_VEX_0F70) },
8433     { REG_TABLE (REG_VEX_0F71) },
8434     { REG_TABLE (REG_VEX_0F72) },
8435     { REG_TABLE (REG_VEX_0F73) },
8436     { PREFIX_TABLE (PREFIX_VEX_0F74) },
8437     { PREFIX_TABLE (PREFIX_VEX_0F75) },
8438     { PREFIX_TABLE (PREFIX_VEX_0F76) },
8439     { PREFIX_TABLE (PREFIX_VEX_0F77) },
8440     /* 78 */
8441     { Bad_Opcode },
8442     { Bad_Opcode },
8443     { Bad_Opcode },
8444     { Bad_Opcode },
8445     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8446     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8447     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8448     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8449     /* 80 */
8450     { Bad_Opcode },
8451     { Bad_Opcode },
8452     { Bad_Opcode },
8453     { Bad_Opcode },
8454     { Bad_Opcode },
8455     { Bad_Opcode },
8456     { Bad_Opcode },
8457     { Bad_Opcode },
8458     /* 88 */
8459     { Bad_Opcode },
8460     { Bad_Opcode },
8461     { Bad_Opcode },
8462     { Bad_Opcode },
8463     { Bad_Opcode },
8464     { Bad_Opcode },
8465     { Bad_Opcode },
8466     { Bad_Opcode },
8467     /* 90 */
8468     { PREFIX_TABLE (PREFIX_VEX_0F90) },
8469     { PREFIX_TABLE (PREFIX_VEX_0F91) },
8470     { PREFIX_TABLE (PREFIX_VEX_0F92) },
8471     { PREFIX_TABLE (PREFIX_VEX_0F93) },
8472     { Bad_Opcode },
8473     { Bad_Opcode },
8474     { Bad_Opcode },
8475     { Bad_Opcode },
8476     /* 98 */
8477     { PREFIX_TABLE (PREFIX_VEX_0F98) },
8478     { Bad_Opcode },
8479     { Bad_Opcode },
8480     { Bad_Opcode },
8481     { Bad_Opcode },
8482     { Bad_Opcode },
8483     { Bad_Opcode },
8484     { Bad_Opcode },
8485     /* a0 */
8486     { Bad_Opcode },
8487     { Bad_Opcode },
8488     { Bad_Opcode },
8489     { Bad_Opcode },
8490     { Bad_Opcode },
8491     { Bad_Opcode },
8492     { Bad_Opcode },
8493     { Bad_Opcode },
8494     /* a8 */
8495     { Bad_Opcode },
8496     { Bad_Opcode },
8497     { Bad_Opcode },
8498     { Bad_Opcode },
8499     { Bad_Opcode },
8500     { Bad_Opcode },
8501     { REG_TABLE (REG_VEX_0FAE) },
8502     { Bad_Opcode },
8503     /* b0 */
8504     { Bad_Opcode },
8505     { Bad_Opcode },
8506     { Bad_Opcode },
8507     { Bad_Opcode },
8508     { Bad_Opcode },
8509     { Bad_Opcode },
8510     { Bad_Opcode },
8511     { Bad_Opcode },
8512     /* b8 */
8513     { Bad_Opcode },
8514     { Bad_Opcode },
8515     { Bad_Opcode },
8516     { Bad_Opcode },
8517     { Bad_Opcode },
8518     { Bad_Opcode },
8519     { Bad_Opcode },
8520     { Bad_Opcode },
8521     /* c0 */
8522     { Bad_Opcode },
8523     { Bad_Opcode },
8524     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8525     { Bad_Opcode },
8526     { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8527     { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8528     { "vshufpX",        { XM, Vex, EXx, Ib } },
8529     { Bad_Opcode },
8530     /* c8 */
8531     { Bad_Opcode },
8532     { Bad_Opcode },
8533     { Bad_Opcode },
8534     { Bad_Opcode },
8535     { Bad_Opcode },
8536     { Bad_Opcode },
8537     { Bad_Opcode },
8538     { Bad_Opcode },
8539     /* d0 */
8540     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8541     { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8542     { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8543     { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8544     { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8545     { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8546     { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8547     { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8548     /* d8 */
8549     { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8550     { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8551     { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8552     { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8553     { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8554     { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8555     { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8556     { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8557     /* e0 */
8558     { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8559     { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8560     { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8561     { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8562     { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8563     { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8564     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8565     { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8566     /* e8 */
8567     { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8568     { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8569     { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8570     { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8571     { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8572     { PREFIX_TABLE (PREFIX_VEX_0FED) },
8573     { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8574     { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8575     /* f0 */
8576     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8577     { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8578     { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8579     { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8580     { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8581     { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8582     { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8583     { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8584     /* f8 */
8585     { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8586     { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8587     { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8588     { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8589     { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8590     { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8591     { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8592     { Bad_Opcode },
8593   },
8594   /* VEX_0F38 */
8595   {
8596     /* 00 */
8597     { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8598     { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8599     { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8600     { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8601     { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8602     { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8603     { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8604     { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8605     /* 08 */
8606     { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8607     { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8608     { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8609     { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8610     { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8611     { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8612     { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8613     { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8614     /* 10 */
8615     { Bad_Opcode },
8616     { Bad_Opcode },
8617     { Bad_Opcode },
8618     { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8619     { Bad_Opcode },
8620     { Bad_Opcode },
8621     { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8622     { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8623     /* 18 */
8624     { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8625     { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8626     { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8627     { Bad_Opcode },
8628     { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8629     { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8630     { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8631     { Bad_Opcode },
8632     /* 20 */
8633     { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8634     { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8635     { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8636     { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8637     { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8638     { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8639     { Bad_Opcode },
8640     { Bad_Opcode },
8641     /* 28 */
8642     { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8643     { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8644     { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8645     { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8646     { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8647     { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8648     { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8649     { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8650     /* 30 */
8651     { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8652     { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8653     { PREFIX_TABLE (PREFIX_VEX_0F3832) },
8654     { PREFIX_TABLE (PREFIX_VEX_0F3833) },
8655     { PREFIX_TABLE (PREFIX_VEX_0F3834) },
8656     { PREFIX_TABLE (PREFIX_VEX_0F3835) },
8657     { PREFIX_TABLE (PREFIX_VEX_0F3836) },
8658     { PREFIX_TABLE (PREFIX_VEX_0F3837) },
8659     /* 38 */
8660     { PREFIX_TABLE (PREFIX_VEX_0F3838) },
8661     { PREFIX_TABLE (PREFIX_VEX_0F3839) },
8662     { PREFIX_TABLE (PREFIX_VEX_0F383A) },
8663     { PREFIX_TABLE (PREFIX_VEX_0F383B) },
8664     { PREFIX_TABLE (PREFIX_VEX_0F383C) },
8665     { PREFIX_TABLE (PREFIX_VEX_0F383D) },
8666     { PREFIX_TABLE (PREFIX_VEX_0F383E) },
8667     { PREFIX_TABLE (PREFIX_VEX_0F383F) },
8668     /* 40 */
8669     { PREFIX_TABLE (PREFIX_VEX_0F3840) },
8670     { PREFIX_TABLE (PREFIX_VEX_0F3841) },
8671     { Bad_Opcode },
8672     { Bad_Opcode },
8673     { Bad_Opcode },
8674     { PREFIX_TABLE (PREFIX_VEX_0F3845) },
8675     { PREFIX_TABLE (PREFIX_VEX_0F3846) },
8676     { PREFIX_TABLE (PREFIX_VEX_0F3847) },
8677     /* 48 */
8678     { Bad_Opcode },
8679     { Bad_Opcode },
8680     { Bad_Opcode },
8681     { Bad_Opcode },
8682     { Bad_Opcode },
8683     { Bad_Opcode },
8684     { Bad_Opcode },
8685     { Bad_Opcode },
8686     /* 50 */
8687     { Bad_Opcode },
8688     { Bad_Opcode },
8689     { Bad_Opcode },
8690     { Bad_Opcode },
8691     { Bad_Opcode },
8692     { Bad_Opcode },
8693     { Bad_Opcode },
8694     { Bad_Opcode },
8695     /* 58 */
8696     { PREFIX_TABLE (PREFIX_VEX_0F3858) },
8697     { PREFIX_TABLE (PREFIX_VEX_0F3859) },
8698     { PREFIX_TABLE (PREFIX_VEX_0F385A) },
8699     { Bad_Opcode },
8700     { Bad_Opcode },
8701     { Bad_Opcode },
8702     { Bad_Opcode },
8703     { Bad_Opcode },
8704     /* 60 */
8705     { Bad_Opcode },
8706     { Bad_Opcode },
8707     { Bad_Opcode },
8708     { Bad_Opcode },
8709     { Bad_Opcode },
8710     { Bad_Opcode },
8711     { Bad_Opcode },
8712     { Bad_Opcode },
8713     /* 68 */
8714     { Bad_Opcode },
8715     { Bad_Opcode },
8716     { Bad_Opcode },
8717     { Bad_Opcode },
8718     { Bad_Opcode },
8719     { Bad_Opcode },
8720     { Bad_Opcode },
8721     { Bad_Opcode },
8722     /* 70 */
8723     { Bad_Opcode },
8724     { Bad_Opcode },
8725     { Bad_Opcode },
8726     { Bad_Opcode },
8727     { Bad_Opcode },
8728     { Bad_Opcode },
8729     { Bad_Opcode },
8730     { Bad_Opcode },
8731     /* 78 */
8732     { PREFIX_TABLE (PREFIX_VEX_0F3878) },
8733     { PREFIX_TABLE (PREFIX_VEX_0F3879) },
8734     { Bad_Opcode },
8735     { Bad_Opcode },
8736     { Bad_Opcode },
8737     { Bad_Opcode },
8738     { Bad_Opcode },
8739     { Bad_Opcode },
8740     /* 80 */
8741     { Bad_Opcode },
8742     { Bad_Opcode },
8743     { Bad_Opcode },
8744     { Bad_Opcode },
8745     { Bad_Opcode },
8746     { Bad_Opcode },
8747     { Bad_Opcode },
8748     { Bad_Opcode },
8749     /* 88 */
8750     { Bad_Opcode },
8751     { Bad_Opcode },
8752     { Bad_Opcode },
8753     { Bad_Opcode },
8754     { PREFIX_TABLE (PREFIX_VEX_0F388C) },
8755     { Bad_Opcode },
8756     { PREFIX_TABLE (PREFIX_VEX_0F388E) },
8757     { Bad_Opcode },
8758     /* 90 */
8759     { PREFIX_TABLE (PREFIX_VEX_0F3890) },
8760     { PREFIX_TABLE (PREFIX_VEX_0F3891) },
8761     { PREFIX_TABLE (PREFIX_VEX_0F3892) },
8762     { PREFIX_TABLE (PREFIX_VEX_0F3893) },
8763     { Bad_Opcode },
8764     { Bad_Opcode },
8765     { PREFIX_TABLE (PREFIX_VEX_0F3896) },
8766     { PREFIX_TABLE (PREFIX_VEX_0F3897) },
8767     /* 98 */
8768     { PREFIX_TABLE (PREFIX_VEX_0F3898) },
8769     { PREFIX_TABLE (PREFIX_VEX_0F3899) },
8770     { PREFIX_TABLE (PREFIX_VEX_0F389A) },
8771     { PREFIX_TABLE (PREFIX_VEX_0F389B) },
8772     { PREFIX_TABLE (PREFIX_VEX_0F389C) },
8773     { PREFIX_TABLE (PREFIX_VEX_0F389D) },
8774     { PREFIX_TABLE (PREFIX_VEX_0F389E) },
8775     { PREFIX_TABLE (PREFIX_VEX_0F389F) },
8776     /* a0 */
8777     { Bad_Opcode },
8778     { Bad_Opcode },
8779     { Bad_Opcode },
8780     { Bad_Opcode },
8781     { Bad_Opcode },
8782     { Bad_Opcode },
8783     { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
8784     { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
8785     /* a8 */
8786     { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
8787     { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
8788     { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
8789     { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
8790     { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
8791     { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
8792     { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
8793     { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
8794     /* b0 */
8795     { Bad_Opcode },
8796     { Bad_Opcode },
8797     { Bad_Opcode },
8798     { Bad_Opcode },
8799     { Bad_Opcode },
8800     { Bad_Opcode },
8801     { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
8802     { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
8803     /* b8 */
8804     { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
8805     { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
8806     { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
8807     { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
8808     { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
8809     { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
8810     { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
8811     { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
8812     /* c0 */
8813     { Bad_Opcode },
8814     { Bad_Opcode },
8815     { Bad_Opcode },
8816     { Bad_Opcode },
8817     { Bad_Opcode },
8818     { Bad_Opcode },
8819     { Bad_Opcode },
8820     { Bad_Opcode },
8821     /* c8 */
8822     { Bad_Opcode },
8823     { Bad_Opcode },
8824     { Bad_Opcode },
8825     { Bad_Opcode },
8826     { Bad_Opcode },
8827     { Bad_Opcode },
8828     { Bad_Opcode },
8829     { Bad_Opcode },
8830     /* d0 */
8831     { Bad_Opcode },
8832     { Bad_Opcode },
8833     { Bad_Opcode },
8834     { Bad_Opcode },
8835     { Bad_Opcode },
8836     { Bad_Opcode },
8837     { Bad_Opcode },
8838     { Bad_Opcode },
8839     /* d8 */
8840     { Bad_Opcode },
8841     { Bad_Opcode },
8842     { Bad_Opcode },
8843     { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
8844     { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
8845     { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
8846     { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
8847     { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
8848     /* e0 */
8849     { Bad_Opcode },
8850     { Bad_Opcode },
8851     { Bad_Opcode },
8852     { Bad_Opcode },
8853     { Bad_Opcode },
8854     { Bad_Opcode },
8855     { Bad_Opcode },
8856     { Bad_Opcode },
8857     /* e8 */
8858     { Bad_Opcode },
8859     { Bad_Opcode },
8860     { Bad_Opcode },
8861     { Bad_Opcode },
8862     { Bad_Opcode },
8863     { Bad_Opcode },
8864     { Bad_Opcode },
8865     { Bad_Opcode },
8866     /* f0 */
8867     { Bad_Opcode },
8868     { Bad_Opcode },
8869     { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
8870     { REG_TABLE (REG_VEX_0F38F3) },
8871     { Bad_Opcode },
8872     { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
8873     { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
8874     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
8875     /* f8 */
8876     { Bad_Opcode },
8877     { Bad_Opcode },
8878     { Bad_Opcode },
8879     { Bad_Opcode },
8880     { Bad_Opcode },
8881     { Bad_Opcode },
8882     { Bad_Opcode },
8883     { Bad_Opcode },
8884   },
8885   /* VEX_0F3A */
8886   {
8887     /* 00 */
8888     { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
8889     { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
8890     { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
8891     { Bad_Opcode },
8892     { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
8893     { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
8894     { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
8895     { Bad_Opcode },
8896     /* 08 */
8897     { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
8898     { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
8899     { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
8900     { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
8901     { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
8902     { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
8903     { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
8904     { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
8905     /* 10 */
8906     { Bad_Opcode },
8907     { Bad_Opcode },
8908     { Bad_Opcode },
8909     { Bad_Opcode },
8910     { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
8911     { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
8912     { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
8913     { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
8914     /* 18 */
8915     { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
8916     { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
8917     { Bad_Opcode },
8918     { Bad_Opcode },
8919     { Bad_Opcode },
8920     { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
8921     { Bad_Opcode },
8922     { Bad_Opcode },
8923     /* 20 */
8924     { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
8925     { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
8926     { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
8927     { Bad_Opcode },
8928     { Bad_Opcode },
8929     { Bad_Opcode },
8930     { Bad_Opcode },
8931     { Bad_Opcode },
8932     /* 28 */
8933     { Bad_Opcode },
8934     { Bad_Opcode },
8935     { Bad_Opcode },
8936     { Bad_Opcode },
8937     { Bad_Opcode },
8938     { Bad_Opcode },
8939     { Bad_Opcode },
8940     { Bad_Opcode },
8941     /* 30 */
8942     { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
8943     { Bad_Opcode },
8944     { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
8945     { Bad_Opcode },
8946     { Bad_Opcode },
8947     { Bad_Opcode },
8948     { Bad_Opcode },
8949     { Bad_Opcode },
8950     /* 38 */
8951     { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
8952     { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
8953     { Bad_Opcode },
8954     { Bad_Opcode },
8955     { Bad_Opcode },
8956     { Bad_Opcode },
8957     { Bad_Opcode },
8958     { Bad_Opcode },
8959     /* 40 */
8960     { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
8961     { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
8962     { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
8963     { Bad_Opcode },
8964     { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
8965     { Bad_Opcode },
8966     { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
8967     { Bad_Opcode },
8968     /* 48 */
8969     { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
8970     { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
8971     { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
8972     { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
8973     { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
8974     { Bad_Opcode },
8975     { Bad_Opcode },
8976     { Bad_Opcode },
8977     /* 50 */
8978     { Bad_Opcode },
8979     { Bad_Opcode },
8980     { Bad_Opcode },
8981     { Bad_Opcode },
8982     { Bad_Opcode },
8983     { Bad_Opcode },
8984     { Bad_Opcode },
8985     { Bad_Opcode },
8986     /* 58 */
8987     { Bad_Opcode },
8988     { Bad_Opcode },
8989     { Bad_Opcode },
8990     { Bad_Opcode },
8991     { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
8992     { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
8993     { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
8994     { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
8995     /* 60 */
8996     { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
8997     { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
8998     { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
8999     { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9000     { Bad_Opcode },
9001     { Bad_Opcode },
9002     { Bad_Opcode },
9003     { Bad_Opcode },
9004     /* 68 */
9005     { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9006     { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9007     { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9008     { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9009     { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9010     { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9011     { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9012     { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9013     /* 70 */
9014     { Bad_Opcode },
9015     { Bad_Opcode },
9016     { Bad_Opcode },
9017     { Bad_Opcode },
9018     { Bad_Opcode },
9019     { Bad_Opcode },
9020     { Bad_Opcode },
9021     { Bad_Opcode },
9022     /* 78 */
9023     { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9024     { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9025     { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9026     { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9027     { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9028     { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9029     { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9030     { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9031     /* 80 */
9032     { Bad_Opcode },
9033     { Bad_Opcode },
9034     { Bad_Opcode },
9035     { Bad_Opcode },
9036     { Bad_Opcode },
9037     { Bad_Opcode },
9038     { Bad_Opcode },
9039     { Bad_Opcode },
9040     /* 88 */
9041     { Bad_Opcode },
9042     { Bad_Opcode },
9043     { Bad_Opcode },
9044     { Bad_Opcode },
9045     { Bad_Opcode },
9046     { Bad_Opcode },
9047     { Bad_Opcode },
9048     { Bad_Opcode },
9049     /* 90 */
9050     { Bad_Opcode },
9051     { Bad_Opcode },
9052     { Bad_Opcode },
9053     { Bad_Opcode },
9054     { Bad_Opcode },
9055     { Bad_Opcode },
9056     { Bad_Opcode },
9057     { Bad_Opcode },
9058     /* 98 */
9059     { Bad_Opcode },
9060     { Bad_Opcode },
9061     { Bad_Opcode },
9062     { Bad_Opcode },
9063     { Bad_Opcode },
9064     { Bad_Opcode },
9065     { Bad_Opcode },
9066     { Bad_Opcode },
9067     /* a0 */
9068     { Bad_Opcode },
9069     { Bad_Opcode },
9070     { Bad_Opcode },
9071     { Bad_Opcode },
9072     { Bad_Opcode },
9073     { Bad_Opcode },
9074     { Bad_Opcode },
9075     { Bad_Opcode },
9076     /* a8 */
9077     { Bad_Opcode },
9078     { Bad_Opcode },
9079     { Bad_Opcode },
9080     { Bad_Opcode },
9081     { Bad_Opcode },
9082     { Bad_Opcode },
9083     { Bad_Opcode },
9084     { Bad_Opcode },
9085     /* b0 */
9086     { Bad_Opcode },
9087     { Bad_Opcode },
9088     { Bad_Opcode },
9089     { Bad_Opcode },
9090     { Bad_Opcode },
9091     { Bad_Opcode },
9092     { Bad_Opcode },
9093     { Bad_Opcode },
9094     /* b8 */
9095     { Bad_Opcode },
9096     { Bad_Opcode },
9097     { Bad_Opcode },
9098     { Bad_Opcode },
9099     { Bad_Opcode },
9100     { Bad_Opcode },
9101     { Bad_Opcode },
9102     { Bad_Opcode },
9103     /* c0 */
9104     { Bad_Opcode },
9105     { Bad_Opcode },
9106     { Bad_Opcode },
9107     { Bad_Opcode },
9108     { Bad_Opcode },
9109     { Bad_Opcode },
9110     { Bad_Opcode },
9111     { Bad_Opcode },
9112     /* c8 */
9113     { Bad_Opcode },
9114     { Bad_Opcode },
9115     { Bad_Opcode },
9116     { Bad_Opcode },
9117     { Bad_Opcode },
9118     { Bad_Opcode },
9119     { Bad_Opcode },
9120     { Bad_Opcode },
9121     /* d0 */
9122     { Bad_Opcode },
9123     { Bad_Opcode },
9124     { Bad_Opcode },
9125     { Bad_Opcode },
9126     { Bad_Opcode },
9127     { Bad_Opcode },
9128     { Bad_Opcode },
9129     { Bad_Opcode },
9130     /* d8 */
9131     { Bad_Opcode },
9132     { Bad_Opcode },
9133     { Bad_Opcode },
9134     { Bad_Opcode },
9135     { Bad_Opcode },
9136     { Bad_Opcode },
9137     { Bad_Opcode },
9138     { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9139     /* e0 */
9140     { Bad_Opcode },
9141     { Bad_Opcode },
9142     { Bad_Opcode },
9143     { Bad_Opcode },
9144     { Bad_Opcode },
9145     { Bad_Opcode },
9146     { Bad_Opcode },
9147     { Bad_Opcode },
9148     /* e8 */
9149     { Bad_Opcode },
9150     { Bad_Opcode },
9151     { Bad_Opcode },
9152     { Bad_Opcode },
9153     { Bad_Opcode },
9154     { Bad_Opcode },
9155     { Bad_Opcode },
9156     { Bad_Opcode },
9157     /* f0 */
9158     { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9159     { Bad_Opcode },
9160     { Bad_Opcode },
9161     { Bad_Opcode },
9162     { Bad_Opcode },
9163     { Bad_Opcode },
9164     { Bad_Opcode },
9165     { Bad_Opcode },
9166     /* f8 */
9167     { Bad_Opcode },
9168     { Bad_Opcode },
9169     { Bad_Opcode },
9170     { Bad_Opcode },
9171     { Bad_Opcode },
9172     { Bad_Opcode },
9173     { Bad_Opcode },
9174     { Bad_Opcode },
9175   },
9176 };
9177
9178 #define NEED_OPCODE_TABLE
9179 #include "i386-dis-evex.h"
9180 #undef NEED_OPCODE_TABLE
9181 static const struct dis386 vex_len_table[][2] = {
9182   /* VEX_LEN_0F10_P_1 */
9183   {
9184     { VEX_W_TABLE (VEX_W_0F10_P_1) },
9185     { VEX_W_TABLE (VEX_W_0F10_P_1) },
9186   },
9187
9188   /* VEX_LEN_0F10_P_3 */
9189   {
9190     { VEX_W_TABLE (VEX_W_0F10_P_3) },
9191     { VEX_W_TABLE (VEX_W_0F10_P_3) },
9192   },
9193
9194   /* VEX_LEN_0F11_P_1 */
9195   {
9196     { VEX_W_TABLE (VEX_W_0F11_P_1) },
9197     { VEX_W_TABLE (VEX_W_0F11_P_1) },
9198   },
9199
9200   /* VEX_LEN_0F11_P_3 */
9201   {
9202     { VEX_W_TABLE (VEX_W_0F11_P_3) },
9203     { VEX_W_TABLE (VEX_W_0F11_P_3) },
9204   },
9205
9206   /* VEX_LEN_0F12_P_0_M_0 */
9207   {
9208     { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) },
9209   },
9210
9211   /* VEX_LEN_0F12_P_0_M_1 */
9212   {
9213     { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) },
9214   },
9215
9216   /* VEX_LEN_0F12_P_2 */
9217   {
9218     { VEX_W_TABLE (VEX_W_0F12_P_2) },
9219   },
9220
9221   /* VEX_LEN_0F13_M_0 */
9222   {
9223     { VEX_W_TABLE (VEX_W_0F13_M_0) },
9224   },
9225
9226   /* VEX_LEN_0F16_P_0_M_0 */
9227   {
9228     { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) },
9229   },
9230
9231   /* VEX_LEN_0F16_P_0_M_1 */
9232   {
9233     { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) },
9234   },
9235
9236   /* VEX_LEN_0F16_P_2 */
9237   {
9238     { VEX_W_TABLE (VEX_W_0F16_P_2) },
9239   },
9240
9241   /* VEX_LEN_0F17_M_0 */
9242   {
9243     { VEX_W_TABLE (VEX_W_0F17_M_0) },
9244   },
9245
9246   /* VEX_LEN_0F2A_P_1 */
9247   {
9248     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev } },
9249     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev } },
9250   },
9251
9252   /* VEX_LEN_0F2A_P_3 */
9253   {
9254     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev } },
9255     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev } },
9256   },
9257
9258   /* VEX_LEN_0F2C_P_1 */
9259   {
9260     { "vcvttss2siY",    { Gv, EXdScalar } },
9261     { "vcvttss2siY",    { Gv, EXdScalar } },
9262   },
9263
9264   /* VEX_LEN_0F2C_P_3 */
9265   {
9266     { "vcvttsd2siY",    { Gv, EXqScalar } },
9267     { "vcvttsd2siY",    { Gv, EXqScalar } },
9268   },
9269
9270   /* VEX_LEN_0F2D_P_1 */
9271   {
9272     { "vcvtss2siY",     { Gv, EXdScalar } },
9273     { "vcvtss2siY",     { Gv, EXdScalar } },
9274   },
9275
9276   /* VEX_LEN_0F2D_P_3 */
9277   {
9278     { "vcvtsd2siY",     { Gv, EXqScalar } },
9279     { "vcvtsd2siY",     { Gv, EXqScalar } },
9280   },
9281
9282   /* VEX_LEN_0F2E_P_0 */
9283   {
9284     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9285     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9286   },
9287
9288   /* VEX_LEN_0F2E_P_2 */
9289   {
9290     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9291     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9292   },
9293
9294   /* VEX_LEN_0F2F_P_0 */
9295   {
9296     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9297     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9298   },
9299
9300   /* VEX_LEN_0F2F_P_2 */
9301   {
9302     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9303     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9304   },
9305
9306   /* VEX_LEN_0F41_P_0 */
9307   {
9308     { Bad_Opcode },
9309     { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9310   },
9311   /* VEX_LEN_0F42_P_0 */
9312   {
9313     { Bad_Opcode },
9314     { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9315   },
9316   /* VEX_LEN_0F44_P_0 */
9317   {
9318     { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9319   },
9320   /* VEX_LEN_0F45_P_0 */
9321   {
9322     { Bad_Opcode },
9323     { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9324   },
9325   /* VEX_LEN_0F46_P_0 */
9326   {
9327     { Bad_Opcode },
9328     { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9329   },
9330   /* VEX_LEN_0F47_P_0 */
9331   {
9332     { Bad_Opcode },
9333     { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9334   },
9335   /* VEX_LEN_0F4B_P_2 */
9336   {
9337     { Bad_Opcode },
9338     { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9339   },
9340
9341   /* VEX_LEN_0F51_P_1 */
9342   {
9343     { VEX_W_TABLE (VEX_W_0F51_P_1) },
9344     { VEX_W_TABLE (VEX_W_0F51_P_1) },
9345   },
9346
9347   /* VEX_LEN_0F51_P_3 */
9348   {
9349     { VEX_W_TABLE (VEX_W_0F51_P_3) },
9350     { VEX_W_TABLE (VEX_W_0F51_P_3) },
9351   },
9352
9353   /* VEX_LEN_0F52_P_1 */
9354   {
9355     { VEX_W_TABLE (VEX_W_0F52_P_1) },
9356     { VEX_W_TABLE (VEX_W_0F52_P_1) },
9357   },
9358
9359   /* VEX_LEN_0F53_P_1 */
9360   {
9361     { VEX_W_TABLE (VEX_W_0F53_P_1) },
9362     { VEX_W_TABLE (VEX_W_0F53_P_1) },
9363   },
9364
9365   /* VEX_LEN_0F58_P_1 */
9366   {
9367     { VEX_W_TABLE (VEX_W_0F58_P_1) },
9368     { VEX_W_TABLE (VEX_W_0F58_P_1) },
9369   },
9370
9371   /* VEX_LEN_0F58_P_3 */
9372   {
9373     { VEX_W_TABLE (VEX_W_0F58_P_3) },
9374     { VEX_W_TABLE (VEX_W_0F58_P_3) },
9375   },
9376
9377   /* VEX_LEN_0F59_P_1 */
9378   {
9379     { VEX_W_TABLE (VEX_W_0F59_P_1) },
9380     { VEX_W_TABLE (VEX_W_0F59_P_1) },
9381   },
9382
9383   /* VEX_LEN_0F59_P_3 */
9384   {
9385     { VEX_W_TABLE (VEX_W_0F59_P_3) },
9386     { VEX_W_TABLE (VEX_W_0F59_P_3) },
9387   },
9388
9389   /* VEX_LEN_0F5A_P_1 */
9390   {
9391     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9392     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9393   },
9394
9395   /* VEX_LEN_0F5A_P_3 */
9396   {
9397     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9398     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9399   },
9400
9401   /* VEX_LEN_0F5C_P_1 */
9402   {
9403     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9404     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9405   },
9406
9407   /* VEX_LEN_0F5C_P_3 */
9408   {
9409     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9410     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9411   },
9412
9413   /* VEX_LEN_0F5D_P_1 */
9414   {
9415     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9416     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9417   },
9418
9419   /* VEX_LEN_0F5D_P_3 */
9420   {
9421     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9422     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9423   },
9424
9425   /* VEX_LEN_0F5E_P_1 */
9426   {
9427     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9428     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9429   },
9430
9431   /* VEX_LEN_0F5E_P_3 */
9432   {
9433     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9434     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9435   },
9436
9437   /* VEX_LEN_0F5F_P_1 */
9438   {
9439     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9440     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9441   },
9442
9443   /* VEX_LEN_0F5F_P_3 */
9444   {
9445     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9446     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9447   },
9448
9449   /* VEX_LEN_0F6E_P_2 */
9450   {
9451     { "vmovK",          { XMScalar, Edq } },
9452     { "vmovK",          { XMScalar, Edq } },
9453   },
9454
9455   /* VEX_LEN_0F7E_P_1 */
9456   {
9457     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9458     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9459   },
9460
9461   /* VEX_LEN_0F7E_P_2 */
9462   {
9463     { "vmovK",          { Edq, XMScalar } },
9464     { "vmovK",          { Edq, XMScalar } },
9465   },
9466
9467   /* VEX_LEN_0F90_P_0 */
9468   {
9469     { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9470   },
9471
9472   /* VEX_LEN_0F91_P_0 */
9473   {
9474     { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9475   },
9476
9477   /* VEX_LEN_0F92_P_0 */
9478   {
9479     { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9480   },
9481
9482   /* VEX_LEN_0F93_P_0 */
9483   {
9484     { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9485   },
9486
9487   /* VEX_LEN_0F98_P_0 */
9488   {
9489     { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9490   },
9491
9492   /* VEX_LEN_0FAE_R_2_M_0 */
9493   {
9494     { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) },
9495   },
9496
9497   /* VEX_LEN_0FAE_R_3_M_0 */
9498   {
9499     { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) },
9500   },
9501
9502   /* VEX_LEN_0FC2_P_1 */
9503   {
9504     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9505     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9506   },
9507
9508   /* VEX_LEN_0FC2_P_3 */
9509   {
9510     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9511     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9512   },
9513
9514   /* VEX_LEN_0FC4_P_2 */
9515   {
9516     { VEX_W_TABLE (VEX_W_0FC4_P_2) },
9517   },
9518
9519   /* VEX_LEN_0FC5_P_2 */
9520   {
9521     { VEX_W_TABLE (VEX_W_0FC5_P_2) },
9522   },
9523
9524   /* VEX_LEN_0FD6_P_2 */
9525   {
9526     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9527     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9528   },
9529
9530   /* VEX_LEN_0FF7_P_2 */
9531   {
9532     { VEX_W_TABLE (VEX_W_0FF7_P_2) },
9533   },
9534
9535   /* VEX_LEN_0F3816_P_2 */
9536   {
9537     { Bad_Opcode },
9538     { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9539   },
9540
9541   /* VEX_LEN_0F3819_P_2 */
9542   {
9543     { Bad_Opcode },
9544     { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9545   },
9546
9547   /* VEX_LEN_0F381A_P_2_M_0 */
9548   {
9549     { Bad_Opcode },
9550     { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9551   },
9552
9553   /* VEX_LEN_0F3836_P_2 */
9554   {
9555     { Bad_Opcode },
9556     { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9557   },
9558
9559   /* VEX_LEN_0F3841_P_2 */
9560   {
9561     { VEX_W_TABLE (VEX_W_0F3841_P_2) },
9562   },
9563
9564   /* VEX_LEN_0F385A_P_2_M_0 */
9565   {
9566     { Bad_Opcode },
9567     { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
9568   },
9569
9570   /* VEX_LEN_0F38DB_P_2 */
9571   {
9572     { VEX_W_TABLE (VEX_W_0F38DB_P_2) },
9573   },
9574
9575   /* VEX_LEN_0F38DC_P_2 */
9576   {
9577     { VEX_W_TABLE (VEX_W_0F38DC_P_2) },
9578   },
9579
9580   /* VEX_LEN_0F38DD_P_2 */
9581   {
9582     { VEX_W_TABLE (VEX_W_0F38DD_P_2) },
9583   },
9584
9585   /* VEX_LEN_0F38DE_P_2 */
9586   {
9587     { VEX_W_TABLE (VEX_W_0F38DE_P_2) },
9588   },
9589
9590   /* VEX_LEN_0F38DF_P_2 */
9591   {
9592     { VEX_W_TABLE (VEX_W_0F38DF_P_2) },
9593   },
9594
9595   /* VEX_LEN_0F38F2_P_0 */
9596   {
9597     { "andnS",          { Gdq, VexGdq, Edq } },
9598   },
9599
9600   /* VEX_LEN_0F38F3_R_1_P_0 */
9601   {
9602     { "blsrS",          { VexGdq, Edq } },
9603   },
9604
9605   /* VEX_LEN_0F38F3_R_2_P_0 */
9606   {
9607     { "blsmskS",        { VexGdq, Edq } },
9608   },
9609
9610   /* VEX_LEN_0F38F3_R_3_P_0 */
9611   {
9612     { "blsiS",          { VexGdq, Edq } },
9613   },
9614
9615   /* VEX_LEN_0F38F5_P_0 */
9616   {
9617     { "bzhiS",          { Gdq, Edq, VexGdq } },
9618   },
9619
9620   /* VEX_LEN_0F38F5_P_1 */
9621   {
9622     { "pextS",          { Gdq, VexGdq, Edq } },
9623   },
9624
9625   /* VEX_LEN_0F38F5_P_3 */
9626   {
9627     { "pdepS",          { Gdq, VexGdq, Edq } },
9628   },
9629
9630   /* VEX_LEN_0F38F6_P_3 */
9631   {
9632     { "mulxS",          { Gdq, VexGdq, Edq } },
9633   },
9634
9635   /* VEX_LEN_0F38F7_P_0 */
9636   {
9637     { "bextrS",         { Gdq, Edq, VexGdq } },
9638   },
9639
9640   /* VEX_LEN_0F38F7_P_1 */
9641   {
9642     { "sarxS",          { Gdq, Edq, VexGdq } },
9643   },
9644
9645   /* VEX_LEN_0F38F7_P_2 */
9646   {
9647     { "shlxS",          { Gdq, Edq, VexGdq } },
9648   },
9649
9650   /* VEX_LEN_0F38F7_P_3 */
9651   {
9652     { "shrxS",          { Gdq, Edq, VexGdq } },
9653   },
9654
9655   /* VEX_LEN_0F3A00_P_2 */
9656   {
9657     { Bad_Opcode },
9658     { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
9659   },
9660
9661   /* VEX_LEN_0F3A01_P_2 */
9662   {
9663     { Bad_Opcode },
9664     { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
9665   },
9666
9667   /* VEX_LEN_0F3A06_P_2 */
9668   {
9669     { Bad_Opcode },
9670     { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
9671   },
9672
9673   /* VEX_LEN_0F3A0A_P_2 */
9674   {
9675     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
9676     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
9677   },
9678
9679   /* VEX_LEN_0F3A0B_P_2 */
9680   {
9681     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
9682     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
9683   },
9684
9685   /* VEX_LEN_0F3A14_P_2 */
9686   {
9687     { VEX_W_TABLE (VEX_W_0F3A14_P_2) },
9688   },
9689
9690   /* VEX_LEN_0F3A15_P_2 */
9691   {
9692     { VEX_W_TABLE (VEX_W_0F3A15_P_2) },
9693   },
9694
9695   /* VEX_LEN_0F3A16_P_2  */
9696   {
9697     { "vpextrK",        { Edq, XM, Ib } },
9698   },
9699
9700   /* VEX_LEN_0F3A17_P_2 */
9701   {
9702     { "vextractps",     { Edqd, XM, Ib } },
9703   },
9704
9705   /* VEX_LEN_0F3A18_P_2 */
9706   {
9707     { Bad_Opcode },
9708     { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
9709   },
9710
9711   /* VEX_LEN_0F3A19_P_2 */
9712   {
9713     { Bad_Opcode },
9714     { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
9715   },
9716
9717   /* VEX_LEN_0F3A20_P_2 */
9718   {
9719     { VEX_W_TABLE (VEX_W_0F3A20_P_2) },
9720   },
9721
9722   /* VEX_LEN_0F3A21_P_2 */
9723   {
9724     { VEX_W_TABLE (VEX_W_0F3A21_P_2) },
9725   },
9726
9727   /* VEX_LEN_0F3A22_P_2 */
9728   {
9729     { "vpinsrK",        { XM, Vex128, Edq, Ib } },
9730   },
9731
9732   /* VEX_LEN_0F3A30_P_2 */
9733   {
9734     { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
9735   },
9736
9737   /* VEX_LEN_0F3A32_P_2 */
9738   {
9739     { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
9740   },
9741
9742   /* VEX_LEN_0F3A38_P_2 */
9743   {
9744     { Bad_Opcode },
9745     { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
9746   },
9747
9748   /* VEX_LEN_0F3A39_P_2 */
9749   {
9750     { Bad_Opcode },
9751     { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
9752   },
9753
9754   /* VEX_LEN_0F3A41_P_2 */
9755   {
9756     { VEX_W_TABLE (VEX_W_0F3A41_P_2) },
9757   },
9758
9759   /* VEX_LEN_0F3A44_P_2 */
9760   {
9761     { VEX_W_TABLE (VEX_W_0F3A44_P_2) },
9762   },
9763
9764   /* VEX_LEN_0F3A46_P_2 */
9765   {
9766     { Bad_Opcode },
9767     { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
9768   },
9769
9770   /* VEX_LEN_0F3A60_P_2 */
9771   {
9772     { VEX_W_TABLE (VEX_W_0F3A60_P_2) },
9773   },
9774
9775   /* VEX_LEN_0F3A61_P_2 */
9776   {
9777     { VEX_W_TABLE (VEX_W_0F3A61_P_2) },
9778   },
9779
9780   /* VEX_LEN_0F3A62_P_2 */
9781   {
9782     { VEX_W_TABLE (VEX_W_0F3A62_P_2) },
9783   },
9784
9785   /* VEX_LEN_0F3A63_P_2 */
9786   {
9787     { VEX_W_TABLE (VEX_W_0F3A63_P_2) },
9788   },
9789
9790   /* VEX_LEN_0F3A6A_P_2 */
9791   {
9792     { "vfmaddss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9793   },
9794
9795   /* VEX_LEN_0F3A6B_P_2 */
9796   {
9797     { "vfmaddsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9798   },
9799
9800   /* VEX_LEN_0F3A6E_P_2 */
9801   {
9802     { "vfmsubss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9803   },
9804
9805   /* VEX_LEN_0F3A6F_P_2 */
9806   {
9807     { "vfmsubsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9808   },
9809
9810   /* VEX_LEN_0F3A7A_P_2 */
9811   {
9812     { "vfnmaddss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9813   },
9814
9815   /* VEX_LEN_0F3A7B_P_2 */
9816   {
9817     { "vfnmaddsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9818   },
9819
9820   /* VEX_LEN_0F3A7E_P_2 */
9821   {
9822     { "vfnmsubss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9823   },
9824
9825   /* VEX_LEN_0F3A7F_P_2 */
9826   {
9827     { "vfnmsubsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9828   },
9829
9830   /* VEX_LEN_0F3ADF_P_2 */
9831   {
9832     { VEX_W_TABLE (VEX_W_0F3ADF_P_2) },
9833   },
9834
9835   /* VEX_LEN_0F3AF0_P_3 */
9836   {
9837     { "rorxS",          { Gdq, Edq, Ib } },
9838   },
9839
9840   /* VEX_LEN_0FXOP_08_CC */
9841   {
9842      { "vpcomb",        { XM, Vex128, EXx, Ib } },
9843   },
9844
9845   /* VEX_LEN_0FXOP_08_CD */
9846   {
9847      { "vpcomw",        { XM, Vex128, EXx, Ib } },
9848   },
9849
9850   /* VEX_LEN_0FXOP_08_CE */
9851   {
9852      { "vpcomd",        { XM, Vex128, EXx, Ib } },
9853   },
9854
9855   /* VEX_LEN_0FXOP_08_CF */
9856   {
9857      { "vpcomq",        { XM, Vex128, EXx, Ib } },
9858   },
9859
9860   /* VEX_LEN_0FXOP_08_EC */
9861   {
9862      { "vpcomub",       { XM, Vex128, EXx, Ib } },
9863   },
9864
9865   /* VEX_LEN_0FXOP_08_ED */
9866   {
9867      { "vpcomuw",       { XM, Vex128, EXx, Ib } },
9868   },
9869
9870   /* VEX_LEN_0FXOP_08_EE */
9871   {
9872      { "vpcomud",       { XM, Vex128, EXx, Ib } },
9873   },
9874
9875   /* VEX_LEN_0FXOP_08_EF */
9876   {
9877      { "vpcomuq",       { XM, Vex128, EXx, Ib } },
9878   },
9879
9880   /* VEX_LEN_0FXOP_09_80 */
9881   {
9882     { "vfrczps",        { XM, EXxmm } },
9883     { "vfrczps",        { XM, EXymmq } },
9884   },
9885
9886   /* VEX_LEN_0FXOP_09_81 */
9887   {
9888     { "vfrczpd",        { XM, EXxmm } },
9889     { "vfrczpd",        { XM, EXymmq } },
9890   },
9891 };
9892
9893 static const struct dis386 vex_w_table[][2] = {
9894   {
9895     /* VEX_W_0F10_P_0 */
9896     { "vmovups",        { XM, EXx } },
9897   },
9898   {
9899     /* VEX_W_0F10_P_1 */
9900     { "vmovss",         { XMVexScalar, VexScalar, EXdScalar } },
9901   },
9902   {
9903     /* VEX_W_0F10_P_2 */
9904     { "vmovupd",        { XM, EXx } },
9905   },
9906   {
9907     /* VEX_W_0F10_P_3 */
9908     { "vmovsd",         { XMVexScalar, VexScalar, EXqScalar } },
9909   },
9910   {
9911     /* VEX_W_0F11_P_0 */
9912     { "vmovups",        { EXxS, XM } },
9913   },
9914   {
9915     /* VEX_W_0F11_P_1 */
9916     { "vmovss",         { EXdVexScalarS, VexScalar, XMScalar } },
9917   },
9918   {
9919     /* VEX_W_0F11_P_2 */
9920     { "vmovupd",        { EXxS, XM } },
9921   },
9922   {
9923     /* VEX_W_0F11_P_3 */
9924     { "vmovsd",         { EXqVexScalarS, VexScalar, XMScalar } },
9925   },
9926   {
9927     /* VEX_W_0F12_P_0_M_0 */
9928     { "vmovlps",        { XM, Vex128, EXq } },
9929   },
9930   {
9931     /* VEX_W_0F12_P_0_M_1 */
9932     { "vmovhlps",       { XM, Vex128, EXq } },
9933   },
9934   {
9935     /* VEX_W_0F12_P_1 */
9936     { "vmovsldup",      { XM, EXx } },
9937   },
9938   {
9939     /* VEX_W_0F12_P_2 */
9940     { "vmovlpd",        { XM, Vex128, EXq } },
9941   },
9942   {
9943     /* VEX_W_0F12_P_3 */
9944     { "vmovddup",       { XM, EXymmq } },
9945   },
9946   {
9947     /* VEX_W_0F13_M_0 */
9948     { "vmovlpX",        { EXq, XM } },
9949   },
9950   {
9951     /* VEX_W_0F14 */
9952     { "vunpcklpX",      { XM, Vex, EXx } },
9953   },
9954   {
9955     /* VEX_W_0F15 */
9956     { "vunpckhpX",      { XM, Vex, EXx } },
9957   },
9958   {
9959     /* VEX_W_0F16_P_0_M_0 */
9960     { "vmovhps",        { XM, Vex128, EXq } },
9961   },
9962   {
9963     /* VEX_W_0F16_P_0_M_1 */
9964     { "vmovlhps",       { XM, Vex128, EXq } },
9965   },
9966   {
9967     /* VEX_W_0F16_P_1 */
9968     { "vmovshdup",      { XM, EXx } },
9969   },
9970   {
9971     /* VEX_W_0F16_P_2 */
9972     { "vmovhpd",        { XM, Vex128, EXq } },
9973   },
9974   {
9975     /* VEX_W_0F17_M_0 */
9976     { "vmovhpX",        { EXq, XM } },
9977   },
9978   {
9979     /* VEX_W_0F28 */
9980     { "vmovapX",        { XM, EXx } },
9981   },
9982   {
9983     /* VEX_W_0F29 */
9984     { "vmovapX",        { EXxS, XM } },
9985   },
9986   {
9987     /* VEX_W_0F2B_M_0 */
9988     { "vmovntpX",       { Mx, XM } },
9989   },
9990   {
9991     /* VEX_W_0F2E_P_0 */
9992     { "vucomiss",       { XMScalar, EXdScalar } },
9993   },
9994   {
9995     /* VEX_W_0F2E_P_2 */
9996     { "vucomisd",       { XMScalar, EXqScalar } },
9997   },
9998   {
9999     /* VEX_W_0F2F_P_0 */
10000     { "vcomiss",        { XMScalar, EXdScalar } },
10001   },
10002   {
10003     /* VEX_W_0F2F_P_2 */
10004     { "vcomisd",        { XMScalar, EXqScalar } },
10005   },
10006   {
10007     /* VEX_W_0F41_P_0_LEN_1 */
10008     { "kandw",          { MaskG, MaskVex, MaskR } },
10009   },
10010   {
10011     /* VEX_W_0F42_P_0_LEN_1 */
10012     { "kandnw",         { MaskG, MaskVex, MaskR } },
10013   },
10014   {
10015     /* VEX_W_0F44_P_0_LEN_0 */
10016     { "knotw",          { MaskG, MaskR } },
10017   },
10018   {
10019     /* VEX_W_0F45_P_0_LEN_1 */
10020     { "korw",           { MaskG, MaskVex, MaskR } },
10021   },
10022   {
10023     /* VEX_W_0F46_P_0_LEN_1 */
10024     { "kxnorw",         { MaskG, MaskVex, MaskR } },
10025   },
10026   {
10027     /* VEX_W_0F47_P_0_LEN_1 */
10028     { "kxorw",          { MaskG, MaskVex, MaskR } },
10029   },
10030   {
10031     /* VEX_W_0F4B_P_2_LEN_1 */
10032     { "kunpckbw",       { MaskG, MaskVex, MaskR } },
10033   },
10034   {
10035     /* VEX_W_0F50_M_0 */
10036     { "vmovmskpX",      { Gdq, XS } },
10037   },
10038   {
10039     /* VEX_W_0F51_P_0 */
10040     { "vsqrtps",        { XM, EXx } },
10041   },
10042   {
10043     /* VEX_W_0F51_P_1 */
10044     { "vsqrtss",        { XMScalar, VexScalar, EXdScalar } },
10045   },
10046   {
10047     /* VEX_W_0F51_P_2  */
10048     { "vsqrtpd",        { XM, EXx } },
10049   },
10050   {
10051     /* VEX_W_0F51_P_3 */
10052     { "vsqrtsd",        { XMScalar, VexScalar, EXqScalar } },
10053   },
10054   {
10055     /* VEX_W_0F52_P_0 */
10056     { "vrsqrtps",       { XM, EXx } },
10057   },
10058   {
10059     /* VEX_W_0F52_P_1 */
10060     { "vrsqrtss",       { XMScalar, VexScalar, EXdScalar } },
10061   },
10062   {
10063     /* VEX_W_0F53_P_0  */
10064     { "vrcpps",         { XM, EXx } },
10065   },
10066   {
10067     /* VEX_W_0F53_P_1  */
10068     { "vrcpss",         { XMScalar, VexScalar, EXdScalar } },
10069   },
10070   {
10071     /* VEX_W_0F58_P_0  */
10072     { "vaddps",         { XM, Vex, EXx } },
10073   },
10074   {
10075     /* VEX_W_0F58_P_1  */
10076     { "vaddss",         { XMScalar, VexScalar, EXdScalar } },
10077   },
10078   {
10079     /* VEX_W_0F58_P_2  */
10080     { "vaddpd",         { XM, Vex, EXx } },
10081   },
10082   {
10083     /* VEX_W_0F58_P_3  */
10084     { "vaddsd",         { XMScalar, VexScalar, EXqScalar } },
10085   },
10086   {
10087     /* VEX_W_0F59_P_0  */
10088     { "vmulps",         { XM, Vex, EXx } },
10089   },
10090   {
10091     /* VEX_W_0F59_P_1  */
10092     { "vmulss",         { XMScalar, VexScalar, EXdScalar } },
10093   },
10094   {
10095     /* VEX_W_0F59_P_2  */
10096     { "vmulpd",         { XM, Vex, EXx } },
10097   },
10098   {
10099     /* VEX_W_0F59_P_3  */
10100     { "vmulsd",         { XMScalar, VexScalar, EXqScalar } },
10101   },
10102   {
10103     /* VEX_W_0F5A_P_0  */
10104     { "vcvtps2pd",      { XM, EXxmmq } },
10105   },
10106   {
10107     /* VEX_W_0F5A_P_1  */
10108     { "vcvtss2sd",      { XMScalar, VexScalar, EXdScalar } },
10109   },
10110   {
10111     /* VEX_W_0F5A_P_3  */
10112     { "vcvtsd2ss",      { XMScalar, VexScalar, EXqScalar } },
10113   },
10114   {
10115     /* VEX_W_0F5B_P_0  */
10116     { "vcvtdq2ps",      { XM, EXx } },
10117   },
10118   {
10119     /* VEX_W_0F5B_P_1  */
10120     { "vcvttps2dq",     { XM, EXx } },
10121   },
10122   {
10123     /* VEX_W_0F5B_P_2  */
10124     { "vcvtps2dq",      { XM, EXx } },
10125   },
10126   {
10127     /* VEX_W_0F5C_P_0  */
10128     { "vsubps",         { XM, Vex, EXx } },
10129   },
10130   {
10131     /* VEX_W_0F5C_P_1  */
10132     { "vsubss",         { XMScalar, VexScalar, EXdScalar } },
10133   },
10134   {
10135     /* VEX_W_0F5C_P_2  */
10136     { "vsubpd",         { XM, Vex, EXx } },
10137   },
10138   {
10139     /* VEX_W_0F5C_P_3  */
10140     { "vsubsd",         { XMScalar, VexScalar, EXqScalar } },
10141   },
10142   {
10143     /* VEX_W_0F5D_P_0  */
10144     { "vminps",         { XM, Vex, EXx } },
10145   },
10146   {
10147     /* VEX_W_0F5D_P_1  */
10148     { "vminss",         { XMScalar, VexScalar, EXdScalar } },
10149   },
10150   {
10151     /* VEX_W_0F5D_P_2  */
10152     { "vminpd",         { XM, Vex, EXx } },
10153   },
10154   {
10155     /* VEX_W_0F5D_P_3  */
10156     { "vminsd",         { XMScalar, VexScalar, EXqScalar } },
10157   },
10158   {
10159     /* VEX_W_0F5E_P_0  */
10160     { "vdivps",         { XM, Vex, EXx } },
10161   },
10162   {
10163     /* VEX_W_0F5E_P_1  */
10164     { "vdivss",         { XMScalar, VexScalar, EXdScalar } },
10165   },
10166   {
10167     /* VEX_W_0F5E_P_2  */
10168     { "vdivpd",         { XM, Vex, EXx } },
10169   },
10170   {
10171     /* VEX_W_0F5E_P_3  */
10172     { "vdivsd",         { XMScalar, VexScalar, EXqScalar } },
10173   },
10174   {
10175     /* VEX_W_0F5F_P_0  */
10176     { "vmaxps",         { XM, Vex, EXx } },
10177   },
10178   {
10179     /* VEX_W_0F5F_P_1  */
10180     { "vmaxss",         { XMScalar, VexScalar, EXdScalar } },
10181   },
10182   {
10183     /* VEX_W_0F5F_P_2  */
10184     { "vmaxpd",         { XM, Vex, EXx } },
10185   },
10186   {
10187     /* VEX_W_0F5F_P_3  */
10188     { "vmaxsd",         { XMScalar, VexScalar, EXqScalar } },
10189   },
10190   {
10191     /* VEX_W_0F60_P_2  */
10192     { "vpunpcklbw",     { XM, Vex, EXx } },
10193   },
10194   {
10195     /* VEX_W_0F61_P_2  */
10196     { "vpunpcklwd",     { XM, Vex, EXx } },
10197   },
10198   {
10199     /* VEX_W_0F62_P_2  */
10200     { "vpunpckldq",     { XM, Vex, EXx } },
10201   },
10202   {
10203     /* VEX_W_0F63_P_2  */
10204     { "vpacksswb",      { XM, Vex, EXx } },
10205   },
10206   {
10207     /* VEX_W_0F64_P_2  */
10208     { "vpcmpgtb",       { XM, Vex, EXx } },
10209   },
10210   {
10211     /* VEX_W_0F65_P_2  */
10212     { "vpcmpgtw",       { XM, Vex, EXx } },
10213   },
10214   {
10215     /* VEX_W_0F66_P_2  */
10216     { "vpcmpgtd",       { XM, Vex, EXx } },
10217   },
10218   {
10219     /* VEX_W_0F67_P_2  */
10220     { "vpackuswb",      { XM, Vex, EXx } },
10221   },
10222   {
10223     /* VEX_W_0F68_P_2  */
10224     { "vpunpckhbw",     { XM, Vex, EXx } },
10225   },
10226   {
10227     /* VEX_W_0F69_P_2  */
10228     { "vpunpckhwd",     { XM, Vex, EXx } },
10229   },
10230   {
10231     /* VEX_W_0F6A_P_2  */
10232     { "vpunpckhdq",     { XM, Vex, EXx } },
10233   },
10234   {
10235     /* VEX_W_0F6B_P_2  */
10236     { "vpackssdw",      { XM, Vex, EXx } },
10237   },
10238   {
10239     /* VEX_W_0F6C_P_2  */
10240     { "vpunpcklqdq",    { XM, Vex, EXx } },
10241   },
10242   {
10243     /* VEX_W_0F6D_P_2  */
10244     { "vpunpckhqdq",    { XM, Vex, EXx } },
10245   },
10246   {
10247     /* VEX_W_0F6F_P_1  */
10248     { "vmovdqu",        { XM, EXx } },
10249   },
10250   {
10251     /* VEX_W_0F6F_P_2  */
10252     { "vmovdqa",        { XM, EXx } },
10253   },
10254   {
10255     /* VEX_W_0F70_P_1 */
10256     { "vpshufhw",       { XM, EXx, Ib } },
10257   },
10258   {
10259     /* VEX_W_0F70_P_2 */
10260     { "vpshufd",        { XM, EXx, Ib } },
10261   },
10262   {
10263     /* VEX_W_0F70_P_3 */
10264     { "vpshuflw",       { XM, EXx, Ib } },
10265   },
10266   {
10267     /* VEX_W_0F71_R_2_P_2  */
10268     { "vpsrlw",         { Vex, XS, Ib } },
10269   },
10270   {
10271     /* VEX_W_0F71_R_4_P_2  */
10272     { "vpsraw",         { Vex, XS, Ib } },
10273   },
10274   {
10275     /* VEX_W_0F71_R_6_P_2  */
10276     { "vpsllw",         { Vex, XS, Ib } },
10277   },
10278   {
10279     /* VEX_W_0F72_R_2_P_2  */
10280     { "vpsrld",         { Vex, XS, Ib } },
10281   },
10282   {
10283     /* VEX_W_0F72_R_4_P_2  */
10284     { "vpsrad",         { Vex, XS, Ib } },
10285   },
10286   {
10287     /* VEX_W_0F72_R_6_P_2  */
10288     { "vpslld",         { Vex, XS, Ib } },
10289   },
10290   {
10291     /* VEX_W_0F73_R_2_P_2  */
10292     { "vpsrlq",         { Vex, XS, Ib } },
10293   },
10294   {
10295     /* VEX_W_0F73_R_3_P_2  */
10296     { "vpsrldq",        { Vex, XS, Ib } },
10297   },
10298   {
10299     /* VEX_W_0F73_R_6_P_2  */
10300     { "vpsllq",         { Vex, XS, Ib } },
10301   },
10302   {
10303     /* VEX_W_0F73_R_7_P_2  */
10304     { "vpslldq",        { Vex, XS, Ib } },
10305   },
10306   {
10307     /* VEX_W_0F74_P_2 */
10308     { "vpcmpeqb",       { XM, Vex, EXx } },
10309   },
10310   {
10311     /* VEX_W_0F75_P_2 */
10312     { "vpcmpeqw",       { XM, Vex, EXx } },
10313   },
10314   {
10315     /* VEX_W_0F76_P_2 */
10316     { "vpcmpeqd",       { XM, Vex, EXx } },
10317   },
10318   {
10319     /* VEX_W_0F77_P_0 */
10320     { "",               { VZERO } },
10321   },
10322   {
10323     /* VEX_W_0F7C_P_2 */
10324     { "vhaddpd",        { XM, Vex, EXx } },
10325   },
10326   {
10327     /* VEX_W_0F7C_P_3 */
10328     { "vhaddps",        { XM, Vex, EXx } },
10329   },
10330   {
10331     /* VEX_W_0F7D_P_2 */
10332     { "vhsubpd",        { XM, Vex, EXx } },
10333   },
10334   {
10335     /* VEX_W_0F7D_P_3 */
10336     { "vhsubps",        { XM, Vex, EXx } },
10337   },
10338   {
10339     /* VEX_W_0F7E_P_1 */
10340     { "vmovq",          { XMScalar, EXqScalar } },
10341   },
10342   {
10343     /* VEX_W_0F7F_P_1 */
10344     { "vmovdqu",        { EXxS, XM } },
10345   },
10346   {
10347     /* VEX_W_0F7F_P_2 */
10348     { "vmovdqa",        { EXxS, XM } },
10349   },
10350   {
10351     /* VEX_W_0F90_P_0_LEN_0 */
10352     { "kmovw",          { MaskG, MaskE } },
10353   },
10354   {
10355     /* VEX_W_0F91_P_0_LEN_0 */
10356     { "kmovw",          { Ew, MaskG } },
10357   },
10358   {
10359     /* VEX_W_0F92_P_0_LEN_0 */
10360     { "kmovw",          { MaskG, Rdq } },
10361   },
10362   {
10363     /* VEX_W_0F93_P_0_LEN_0 */
10364     { "kmovw",          { Gdq, MaskR } },
10365   },
10366   {
10367     /* VEX_W_0F98_P_0_LEN_0 */
10368     { "kortestw",       { MaskG, MaskR } },
10369   },
10370   {
10371     /* VEX_W_0FAE_R_2_M_0 */
10372     { "vldmxcsr",       { Md } },
10373   },
10374   {
10375     /* VEX_W_0FAE_R_3_M_0 */
10376     { "vstmxcsr",       { Md } },
10377   },
10378   {
10379     /* VEX_W_0FC2_P_0 */
10380     { "vcmpps",         { XM, Vex, EXx, VCMP } },
10381   },
10382   {
10383     /* VEX_W_0FC2_P_1 */
10384     { "vcmpss",         { XMScalar, VexScalar, EXdScalar, VCMP } },
10385   },
10386   {
10387     /* VEX_W_0FC2_P_2 */
10388     { "vcmppd",         { XM, Vex, EXx, VCMP } },
10389   },
10390   {
10391     /* VEX_W_0FC2_P_3 */
10392     { "vcmpsd",         { XMScalar, VexScalar, EXqScalar, VCMP } },
10393   },
10394   {
10395     /* VEX_W_0FC4_P_2 */
10396     { "vpinsrw",        { XM, Vex128, Edqw, Ib } },
10397   },
10398   {
10399     /* VEX_W_0FC5_P_2 */
10400     { "vpextrw",        { Gdq, XS, Ib } },
10401   },
10402   {
10403     /* VEX_W_0FD0_P_2 */
10404     { "vaddsubpd",      { XM, Vex, EXx } },
10405   },
10406   {
10407     /* VEX_W_0FD0_P_3 */
10408     { "vaddsubps",      { XM, Vex, EXx } },
10409   },
10410   {
10411     /* VEX_W_0FD1_P_2 */
10412     { "vpsrlw",         { XM, Vex, EXxmm } },
10413   },
10414   {
10415     /* VEX_W_0FD2_P_2 */
10416     { "vpsrld",         { XM, Vex, EXxmm } },
10417   },
10418   {
10419     /* VEX_W_0FD3_P_2 */
10420     { "vpsrlq",         { XM, Vex, EXxmm } },
10421   },
10422   {
10423     /* VEX_W_0FD4_P_2 */
10424     { "vpaddq",         { XM, Vex, EXx } },
10425   },
10426   {
10427     /* VEX_W_0FD5_P_2 */
10428     { "vpmullw",        { XM, Vex, EXx } },
10429   },
10430   {
10431     /* VEX_W_0FD6_P_2 */
10432     { "vmovq",          { EXqScalarS, XMScalar } },
10433   },
10434   {
10435     /* VEX_W_0FD7_P_2_M_1 */
10436     { "vpmovmskb",      { Gdq, XS } },
10437   },
10438   {
10439     /* VEX_W_0FD8_P_2 */
10440     { "vpsubusb",       { XM, Vex, EXx } },
10441   },
10442   {
10443     /* VEX_W_0FD9_P_2 */
10444     { "vpsubusw",       { XM, Vex, EXx } },
10445   },
10446   {
10447     /* VEX_W_0FDA_P_2 */
10448     { "vpminub",        { XM, Vex, EXx } },
10449   },
10450   {
10451     /* VEX_W_0FDB_P_2 */
10452     { "vpand",          { XM, Vex, EXx } },
10453   },
10454   {
10455     /* VEX_W_0FDC_P_2 */
10456     { "vpaddusb",       { XM, Vex, EXx } },
10457   },
10458   {
10459     /* VEX_W_0FDD_P_2 */
10460     { "vpaddusw",       { XM, Vex, EXx } },
10461   },
10462   {
10463     /* VEX_W_0FDE_P_2 */
10464     { "vpmaxub",        { XM, Vex, EXx } },
10465   },
10466   {
10467     /* VEX_W_0FDF_P_2 */
10468     { "vpandn",         { XM, Vex, EXx } },
10469   },
10470   {
10471     /* VEX_W_0FE0_P_2  */
10472     { "vpavgb",         { XM, Vex, EXx } },
10473   },
10474   {
10475     /* VEX_W_0FE1_P_2  */
10476     { "vpsraw",         { XM, Vex, EXxmm } },
10477   },
10478   {
10479     /* VEX_W_0FE2_P_2  */
10480     { "vpsrad",         { XM, Vex, EXxmm } },
10481   },
10482   {
10483     /* VEX_W_0FE3_P_2  */
10484     { "vpavgw",         { XM, Vex, EXx } },
10485   },
10486   {
10487     /* VEX_W_0FE4_P_2  */
10488     { "vpmulhuw",       { XM, Vex, EXx } },
10489   },
10490   {
10491     /* VEX_W_0FE5_P_2  */
10492     { "vpmulhw",        { XM, Vex, EXx } },
10493   },
10494   {
10495     /* VEX_W_0FE6_P_1  */
10496     { "vcvtdq2pd",      { XM, EXxmmq } },
10497   },
10498   {
10499     /* VEX_W_0FE6_P_2  */
10500     { "vcvttpd2dq%XY",  { XMM, EXx } },
10501   },
10502   {
10503     /* VEX_W_0FE6_P_3  */
10504     { "vcvtpd2dq%XY",   { XMM, EXx } },
10505   },
10506   {
10507     /* VEX_W_0FE7_P_2_M_0 */
10508     { "vmovntdq",       { Mx, XM } },
10509   },
10510   {
10511     /* VEX_W_0FE8_P_2  */
10512     { "vpsubsb",        { XM, Vex, EXx } },
10513   },
10514   {
10515     /* VEX_W_0FE9_P_2  */
10516     { "vpsubsw",        { XM, Vex, EXx } },
10517   },
10518   {
10519     /* VEX_W_0FEA_P_2  */
10520     { "vpminsw",        { XM, Vex, EXx } },
10521   },
10522   {
10523     /* VEX_W_0FEB_P_2  */
10524     { "vpor",           { XM, Vex, EXx } },
10525   },
10526   {
10527     /* VEX_W_0FEC_P_2  */
10528     { "vpaddsb",        { XM, Vex, EXx } },
10529   },
10530   {
10531     /* VEX_W_0FED_P_2  */
10532     { "vpaddsw",        { XM, Vex, EXx } },
10533   },
10534   {
10535     /* VEX_W_0FEE_P_2  */
10536     { "vpmaxsw",        { XM, Vex, EXx } },
10537   },
10538   {
10539     /* VEX_W_0FEF_P_2  */
10540     { "vpxor",          { XM, Vex, EXx } },
10541   },
10542   {
10543     /* VEX_W_0FF0_P_3_M_0 */
10544     { "vlddqu",         { XM, M } },
10545   },
10546   {
10547     /* VEX_W_0FF1_P_2 */
10548     { "vpsllw",         { XM, Vex, EXxmm } },
10549   },
10550   {
10551     /* VEX_W_0FF2_P_2 */
10552     { "vpslld",         { XM, Vex, EXxmm } },
10553   },
10554   {
10555     /* VEX_W_0FF3_P_2 */
10556     { "vpsllq",         { XM, Vex, EXxmm } },
10557   },
10558   {
10559     /* VEX_W_0FF4_P_2 */
10560     { "vpmuludq",       { XM, Vex, EXx } },
10561   },
10562   {
10563     /* VEX_W_0FF5_P_2 */
10564     { "vpmaddwd",       { XM, Vex, EXx } },
10565   },
10566   {
10567     /* VEX_W_0FF6_P_2 */
10568     { "vpsadbw",        { XM, Vex, EXx } },
10569   },
10570   {
10571     /* VEX_W_0FF7_P_2 */
10572     { "vmaskmovdqu",    { XM, XS } },
10573   },
10574   {
10575     /* VEX_W_0FF8_P_2 */
10576     { "vpsubb",         { XM, Vex, EXx } },
10577   },
10578   {
10579     /* VEX_W_0FF9_P_2 */
10580     { "vpsubw",         { XM, Vex, EXx } },
10581   },
10582   {
10583     /* VEX_W_0FFA_P_2 */
10584     { "vpsubd",         { XM, Vex, EXx } },
10585   },
10586   {
10587     /* VEX_W_0FFB_P_2 */
10588     { "vpsubq",         { XM, Vex, EXx } },
10589   },
10590   {
10591     /* VEX_W_0FFC_P_2 */
10592     { "vpaddb",         { XM, Vex, EXx } },
10593   },
10594   {
10595     /* VEX_W_0FFD_P_2 */
10596     { "vpaddw",         { XM, Vex, EXx } },
10597   },
10598   {
10599     /* VEX_W_0FFE_P_2 */
10600     { "vpaddd",         { XM, Vex, EXx } },
10601   },
10602   {
10603     /* VEX_W_0F3800_P_2  */
10604     { "vpshufb",        { XM, Vex, EXx } },
10605   },
10606   {
10607     /* VEX_W_0F3801_P_2  */
10608     { "vphaddw",        { XM, Vex, EXx } },
10609   },
10610   {
10611     /* VEX_W_0F3802_P_2  */
10612     { "vphaddd",        { XM, Vex, EXx } },
10613   },
10614   {
10615     /* VEX_W_0F3803_P_2  */
10616     { "vphaddsw",       { XM, Vex, EXx } },
10617   },
10618   {
10619     /* VEX_W_0F3804_P_2  */
10620     { "vpmaddubsw",     { XM, Vex, EXx } },
10621   },
10622   {
10623     /* VEX_W_0F3805_P_2  */
10624     { "vphsubw",        { XM, Vex, EXx } },
10625   },
10626   {
10627     /* VEX_W_0F3806_P_2  */
10628     { "vphsubd",        { XM, Vex, EXx } },
10629   },
10630   {
10631     /* VEX_W_0F3807_P_2  */
10632     { "vphsubsw",       { XM, Vex, EXx } },
10633   },
10634   {
10635     /* VEX_W_0F3808_P_2  */
10636     { "vpsignb",        { XM, Vex, EXx } },
10637   },
10638   {
10639     /* VEX_W_0F3809_P_2  */
10640     { "vpsignw",        { XM, Vex, EXx } },
10641   },
10642   {
10643     /* VEX_W_0F380A_P_2  */
10644     { "vpsignd",        { XM, Vex, EXx } },
10645   },
10646   {
10647     /* VEX_W_0F380B_P_2  */
10648     { "vpmulhrsw",      { XM, Vex, EXx } },
10649   },
10650   {
10651     /* VEX_W_0F380C_P_2  */
10652     { "vpermilps",      { XM, Vex, EXx } },
10653   },
10654   {
10655     /* VEX_W_0F380D_P_2  */
10656     { "vpermilpd",      { XM, Vex, EXx } },
10657   },
10658   {
10659     /* VEX_W_0F380E_P_2  */
10660     { "vtestps",        { XM, EXx } },
10661   },
10662   {
10663     /* VEX_W_0F380F_P_2  */
10664     { "vtestpd",        { XM, EXx } },
10665   },
10666   {
10667     /* VEX_W_0F3816_P_2  */
10668     { "vpermps",        { XM, Vex, EXx } },
10669   },
10670   {
10671     /* VEX_W_0F3817_P_2 */
10672     { "vptest",         { XM, EXx } },
10673   },
10674   {
10675     /* VEX_W_0F3818_P_2 */
10676     { "vbroadcastss",   { XM, EXxmm_md } },
10677   },
10678   {
10679     /* VEX_W_0F3819_P_2 */
10680     { "vbroadcastsd",   { XM, EXxmm_mq } },
10681   },
10682   {
10683     /* VEX_W_0F381A_P_2_M_0 */
10684     { "vbroadcastf128", { XM, Mxmm } },
10685   },
10686   {
10687     /* VEX_W_0F381C_P_2 */
10688     { "vpabsb",         { XM, EXx } },
10689   },
10690   {
10691     /* VEX_W_0F381D_P_2 */
10692     { "vpabsw",         { XM, EXx } },
10693   },
10694   {
10695     /* VEX_W_0F381E_P_2 */
10696     { "vpabsd",         { XM, EXx } },
10697   },
10698   {
10699     /* VEX_W_0F3820_P_2 */
10700     { "vpmovsxbw",      { XM, EXxmmq } },
10701   },
10702   {
10703     /* VEX_W_0F3821_P_2 */
10704     { "vpmovsxbd",      { XM, EXxmmqd } },
10705   },
10706   {
10707     /* VEX_W_0F3822_P_2 */
10708     { "vpmovsxbq",      { XM, EXxmmdw } },
10709   },
10710   {
10711     /* VEX_W_0F3823_P_2 */
10712     { "vpmovsxwd",      { XM, EXxmmq } },
10713   },
10714   {
10715     /* VEX_W_0F3824_P_2 */
10716     { "vpmovsxwq",      { XM, EXxmmqd } },
10717   },
10718   {
10719     /* VEX_W_0F3825_P_2 */
10720     { "vpmovsxdq",      { XM, EXxmmq } },
10721   },
10722   {
10723     /* VEX_W_0F3828_P_2 */
10724     { "vpmuldq",        { XM, Vex, EXx } },
10725   },
10726   {
10727     /* VEX_W_0F3829_P_2 */
10728     { "vpcmpeqq",       { XM, Vex, EXx } },
10729   },
10730   {
10731     /* VEX_W_0F382A_P_2_M_0 */
10732     { "vmovntdqa",      { XM, Mx } },
10733   },
10734   {
10735     /* VEX_W_0F382B_P_2 */
10736     { "vpackusdw",      { XM, Vex, EXx } },
10737   },
10738   {
10739     /* VEX_W_0F382C_P_2_M_0 */
10740     { "vmaskmovps",     { XM, Vex, Mx } },
10741   },
10742   {
10743     /* VEX_W_0F382D_P_2_M_0 */
10744     { "vmaskmovpd",     { XM, Vex, Mx } },
10745   },
10746   {
10747     /* VEX_W_0F382E_P_2_M_0 */
10748     { "vmaskmovps",     { Mx, Vex, XM } },
10749   },
10750   {
10751     /* VEX_W_0F382F_P_2_M_0 */
10752     { "vmaskmovpd",     { Mx, Vex, XM } },
10753   },
10754   {
10755     /* VEX_W_0F3830_P_2 */
10756     { "vpmovzxbw",      { XM, EXxmmq } },
10757   },
10758   {
10759     /* VEX_W_0F3831_P_2 */
10760     { "vpmovzxbd",      { XM, EXxmmqd } },
10761   },
10762   {
10763     /* VEX_W_0F3832_P_2 */
10764     { "vpmovzxbq",      { XM, EXxmmdw } },
10765   },
10766   {
10767     /* VEX_W_0F3833_P_2 */
10768     { "vpmovzxwd",      { XM, EXxmmq } },
10769   },
10770   {
10771     /* VEX_W_0F3834_P_2 */
10772     { "vpmovzxwq",      { XM, EXxmmqd } },
10773   },
10774   {
10775     /* VEX_W_0F3835_P_2 */
10776     { "vpmovzxdq",      { XM, EXxmmq } },
10777   },
10778   {
10779     /* VEX_W_0F3836_P_2  */
10780     { "vpermd",         { XM, Vex, EXx } },
10781   },
10782   {
10783     /* VEX_W_0F3837_P_2 */
10784     { "vpcmpgtq",       { XM, Vex, EXx } },
10785   },
10786   {
10787     /* VEX_W_0F3838_P_2 */
10788     { "vpminsb",        { XM, Vex, EXx } },
10789   },
10790   {
10791     /* VEX_W_0F3839_P_2 */
10792     { "vpminsd",        { XM, Vex, EXx } },
10793   },
10794   {
10795     /* VEX_W_0F383A_P_2 */
10796     { "vpminuw",        { XM, Vex, EXx } },
10797   },
10798   {
10799     /* VEX_W_0F383B_P_2 */
10800     { "vpminud",        { XM, Vex, EXx } },
10801   },
10802   {
10803     /* VEX_W_0F383C_P_2 */
10804     { "vpmaxsb",        { XM, Vex, EXx } },
10805   },
10806   {
10807     /* VEX_W_0F383D_P_2 */
10808     { "vpmaxsd",        { XM, Vex, EXx } },
10809   },
10810   {
10811     /* VEX_W_0F383E_P_2 */
10812     { "vpmaxuw",        { XM, Vex, EXx } },
10813   },
10814   {
10815     /* VEX_W_0F383F_P_2 */
10816     { "vpmaxud",        { XM, Vex, EXx } },
10817   },
10818   {
10819     /* VEX_W_0F3840_P_2 */
10820     { "vpmulld",        { XM, Vex, EXx } },
10821   },
10822   {
10823     /* VEX_W_0F3841_P_2 */
10824     { "vphminposuw",    { XM, EXx } },
10825   },
10826   {
10827     /* VEX_W_0F3846_P_2 */
10828     { "vpsravd",        { XM, Vex, EXx } },
10829   },
10830   {
10831     /* VEX_W_0F3858_P_2 */
10832     { "vpbroadcastd", { XM, EXxmm_md } },
10833   },
10834   {
10835     /* VEX_W_0F3859_P_2 */
10836     { "vpbroadcastq",   { XM, EXxmm_mq } },
10837   },
10838   {
10839     /* VEX_W_0F385A_P_2_M_0 */
10840     { "vbroadcasti128", { XM, Mxmm } },
10841   },
10842   {
10843     /* VEX_W_0F3878_P_2 */
10844     { "vpbroadcastb",   { XM, EXxmm_mb } },
10845   },
10846   {
10847     /* VEX_W_0F3879_P_2 */
10848     { "vpbroadcastw",   { XM, EXxmm_mw } },
10849   },
10850   {
10851     /* VEX_W_0F38DB_P_2 */
10852     { "vaesimc",        { XM, EXx } },
10853   },
10854   {
10855     /* VEX_W_0F38DC_P_2 */
10856     { "vaesenc",        { XM, Vex128, EXx } },
10857   },
10858   {
10859     /* VEX_W_0F38DD_P_2 */
10860     { "vaesenclast",    { XM, Vex128, EXx } },
10861   },
10862   {
10863     /* VEX_W_0F38DE_P_2 */
10864     { "vaesdec",        { XM, Vex128, EXx } },
10865   },
10866   {
10867     /* VEX_W_0F38DF_P_2 */
10868     { "vaesdeclast",    { XM, Vex128, EXx } },
10869   },
10870   {
10871     /* VEX_W_0F3A00_P_2 */
10872     { Bad_Opcode },
10873     { "vpermq",         { XM, EXx, Ib } },
10874   },
10875   {
10876     /* VEX_W_0F3A01_P_2 */
10877     { Bad_Opcode },
10878     { "vpermpd",        { XM, EXx, Ib } },
10879   },
10880   {
10881     /* VEX_W_0F3A02_P_2 */
10882     { "vpblendd",       { XM, Vex, EXx, Ib } },
10883   },
10884   {
10885     /* VEX_W_0F3A04_P_2 */
10886     { "vpermilps",      { XM, EXx, Ib } },
10887   },
10888   {
10889     /* VEX_W_0F3A05_P_2 */
10890     { "vpermilpd",      { XM, EXx, Ib } },
10891   },
10892   {
10893     /* VEX_W_0F3A06_P_2 */
10894     { "vperm2f128",     { XM, Vex256, EXx, Ib } },
10895   },
10896   {
10897     /* VEX_W_0F3A08_P_2 */
10898     { "vroundps",       { XM, EXx, Ib } },
10899   },
10900   {
10901     /* VEX_W_0F3A09_P_2 */
10902     { "vroundpd",       { XM, EXx, Ib } },
10903   },
10904   {
10905     /* VEX_W_0F3A0A_P_2 */
10906     { "vroundss",       { XMScalar, VexScalar, EXdScalar, Ib } },
10907   },
10908   {
10909     /* VEX_W_0F3A0B_P_2 */
10910     { "vroundsd",       { XMScalar, VexScalar, EXqScalar, Ib } },
10911   },
10912   {
10913     /* VEX_W_0F3A0C_P_2 */
10914     { "vblendps",       { XM, Vex, EXx, Ib } },
10915   },
10916   {
10917     /* VEX_W_0F3A0D_P_2 */
10918     { "vblendpd",       { XM, Vex, EXx, Ib } },
10919   },
10920   {
10921     /* VEX_W_0F3A0E_P_2 */
10922     { "vpblendw",       { XM, Vex, EXx, Ib } },
10923   },
10924   {
10925     /* VEX_W_0F3A0F_P_2 */
10926     { "vpalignr",       { XM, Vex, EXx, Ib } },
10927   },
10928   {
10929     /* VEX_W_0F3A14_P_2 */
10930     { "vpextrb",        { Edqb, XM, Ib } },
10931   },
10932   {
10933     /* VEX_W_0F3A15_P_2 */
10934     { "vpextrw",        { Edqw, XM, Ib } },
10935   },
10936   {
10937     /* VEX_W_0F3A18_P_2 */
10938     { "vinsertf128",    { XM, Vex256, EXxmm, Ib } },
10939   },
10940   {
10941     /* VEX_W_0F3A19_P_2 */
10942     { "vextractf128",   { EXxmm, XM, Ib } },
10943   },
10944   {
10945     /* VEX_W_0F3A20_P_2 */
10946     { "vpinsrb",        { XM, Vex128, Edqb, Ib } },
10947   },
10948   {
10949     /* VEX_W_0F3A21_P_2 */
10950     { "vinsertps",      { XM, Vex128, EXd, Ib } },
10951   },
10952   {
10953     /* VEX_W_0F3A30_P_2 */
10954     { Bad_Opcode },
10955     { "kshiftrw",       { MaskG, MaskR, Ib } },
10956   },
10957   {
10958     /* VEX_W_0F3A32_P_2 */
10959     { Bad_Opcode },
10960     { "kshiftlw",       { MaskG, MaskR, Ib } },
10961   },
10962   {
10963     /* VEX_W_0F3A38_P_2 */
10964     { "vinserti128",    { XM, Vex256, EXxmm, Ib } },
10965   },
10966   {
10967     /* VEX_W_0F3A39_P_2 */
10968     { "vextracti128",   { EXxmm, XM, Ib } },
10969   },
10970   {
10971     /* VEX_W_0F3A40_P_2 */
10972     { "vdpps",          { XM, Vex, EXx, Ib } },
10973   },
10974   {
10975     /* VEX_W_0F3A41_P_2 */
10976     { "vdppd",          { XM, Vex128, EXx, Ib } },
10977   },
10978   {
10979     /* VEX_W_0F3A42_P_2 */
10980     { "vmpsadbw",       { XM, Vex, EXx, Ib } },
10981   },
10982   {
10983     /* VEX_W_0F3A44_P_2 */
10984     { "vpclmulqdq",     { XM, Vex128, EXx, PCLMUL } },
10985   },
10986   {
10987     /* VEX_W_0F3A46_P_2 */
10988     { "vperm2i128",     { XM, Vex256, EXx, Ib } },
10989   },
10990   {
10991     /* VEX_W_0F3A48_P_2 */
10992     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
10993     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
10994   },
10995   {
10996     /* VEX_W_0F3A49_P_2 */
10997     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
10998     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
10999   },
11000   {
11001     /* VEX_W_0F3A4A_P_2 */
11002     { "vblendvps",      { XM, Vex, EXx, XMVexI4 } },
11003   },
11004   {
11005     /* VEX_W_0F3A4B_P_2 */
11006     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 } },
11007   },
11008   {
11009     /* VEX_W_0F3A4C_P_2 */
11010     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 } },
11011   },
11012   {
11013     /* VEX_W_0F3A60_P_2 */
11014     { "vpcmpestrm",     { XM, EXx, Ib } },
11015   },
11016   {
11017     /* VEX_W_0F3A61_P_2 */
11018     { "vpcmpestri",     { XM, EXx, Ib } },
11019   },
11020   {
11021     /* VEX_W_0F3A62_P_2 */
11022     { "vpcmpistrm",     { XM, EXx, Ib } },
11023   },
11024   {
11025     /* VEX_W_0F3A63_P_2 */
11026     { "vpcmpistri",     { XM, EXx, Ib } },
11027   },
11028   {
11029     /* VEX_W_0F3ADF_P_2 */
11030     { "vaeskeygenassist", { XM, EXx, Ib } },
11031   },
11032 #define NEED_VEX_W_TABLE
11033 #include "i386-dis-evex.h"
11034 #undef NEED_VEX_W_TABLE
11035 };
11036
11037 static const struct dis386 mod_table[][2] = {
11038   {
11039     /* MOD_8D */
11040     { "leaS",           { Gv, M } },
11041   },
11042   {
11043     /* MOD_C6_REG_7 */
11044     { Bad_Opcode },
11045     { RM_TABLE (RM_C6_REG_7) },
11046   },
11047   {
11048     /* MOD_C7_REG_7 */
11049     { Bad_Opcode },
11050     { RM_TABLE (RM_C7_REG_7) },
11051   },
11052   {
11053     /* MOD_0F01_REG_0 */
11054     { X86_64_TABLE (X86_64_0F01_REG_0) },
11055     { RM_TABLE (RM_0F01_REG_0) },
11056   },
11057   {
11058     /* MOD_0F01_REG_1 */
11059     { X86_64_TABLE (X86_64_0F01_REG_1) },
11060     { RM_TABLE (RM_0F01_REG_1) },
11061   },
11062   {
11063     /* MOD_0F01_REG_2 */
11064     { X86_64_TABLE (X86_64_0F01_REG_2) },
11065     { RM_TABLE (RM_0F01_REG_2) },
11066   },
11067   {
11068     /* MOD_0F01_REG_3 */
11069     { X86_64_TABLE (X86_64_0F01_REG_3) },
11070     { RM_TABLE (RM_0F01_REG_3) },
11071   },
11072   {
11073     /* MOD_0F01_REG_7 */
11074     { "invlpg",         { Mb } },
11075     { RM_TABLE (RM_0F01_REG_7) },
11076   },
11077   {
11078     /* MOD_0F12_PREFIX_0 */
11079     { "movlps",         { XM, EXq } },
11080     { "movhlps",        { XM, EXq } },
11081   },
11082   {
11083     /* MOD_0F13 */
11084     { "movlpX",         { EXq, XM } },
11085   },
11086   {
11087     /* MOD_0F16_PREFIX_0 */
11088     { "movhps",         { XM, EXq } },
11089     { "movlhps",        { XM, EXq } },
11090   },
11091   {
11092     /* MOD_0F17 */
11093     { "movhpX",         { EXq, XM } },
11094   },
11095   {
11096     /* MOD_0F18_REG_0 */
11097     { "prefetchnta",    { Mb } },
11098   },
11099   {
11100     /* MOD_0F18_REG_1 */
11101     { "prefetcht0",     { Mb } },
11102   },
11103   {
11104     /* MOD_0F18_REG_2 */
11105     { "prefetcht1",     { Mb } },
11106   },
11107   {
11108     /* MOD_0F18_REG_3 */
11109     { "prefetcht2",     { Mb } },
11110   },
11111   {
11112     /* MOD_0F18_REG_4 */
11113     { "nop/reserved",   { Mb } },
11114   },
11115   {
11116     /* MOD_0F18_REG_5 */
11117     { "nop/reserved",   { Mb } },
11118   },
11119   {
11120     /* MOD_0F18_REG_6 */
11121     { "nop/reserved",   { Mb } },
11122   },
11123   {
11124     /* MOD_0F18_REG_7 */
11125     { "nop/reserved",   { Mb } },
11126   },
11127   {
11128     /* MOD_0F1A_PREFIX_0 */
11129     { "bndldx",         { Gbnd, Ev_bnd } },
11130     { "nopQ",           { Ev } },
11131   },
11132   {
11133     /* MOD_0F1B_PREFIX_0 */
11134     { "bndstx",         { Ev_bnd, Gbnd } },
11135     { "nopQ",           { Ev } },
11136   },
11137   {
11138     /* MOD_0F1B_PREFIX_1 */
11139     { "bndmk",          { Gbnd, Ev_bnd } },
11140     { "nopQ",           { Ev } },
11141   },
11142   {
11143     /* MOD_0F20 */
11144     { Bad_Opcode },
11145     { "movZ",           { Rm, Cm } },
11146   },
11147   {
11148     /* MOD_0F21 */
11149     { Bad_Opcode },
11150     { "movZ",           { Rm, Dm } },
11151   },
11152   {
11153     /* MOD_0F22 */
11154     { Bad_Opcode },
11155     { "movZ",           { Cm, Rm } },
11156   },
11157   {
11158     /* MOD_0F23 */
11159     { Bad_Opcode },
11160     { "movZ",           { Dm, Rm } },
11161   },
11162   {
11163     /* MOD_0F24 */
11164     { Bad_Opcode },
11165     { "movL",           { Rd, Td } },
11166   },
11167   {
11168     /* MOD_0F26 */
11169     { Bad_Opcode },
11170     { "movL",           { Td, Rd } },
11171   },
11172   {
11173     /* MOD_0F2B_PREFIX_0 */
11174     {"movntps",         { Mx, XM } },
11175   },
11176   {
11177     /* MOD_0F2B_PREFIX_1 */
11178     {"movntss",         { Md, XM } },
11179   },
11180   {
11181     /* MOD_0F2B_PREFIX_2 */
11182     {"movntpd",         { Mx, XM } },
11183   },
11184   {
11185     /* MOD_0F2B_PREFIX_3 */
11186     {"movntsd",         { Mq, XM } },
11187   },
11188   {
11189     /* MOD_0F51 */
11190     { Bad_Opcode },
11191     { "movmskpX",       { Gdq, XS } },
11192   },
11193   {
11194     /* MOD_0F71_REG_2 */
11195     { Bad_Opcode },
11196     { "psrlw",          { MS, Ib } },
11197   },
11198   {
11199     /* MOD_0F71_REG_4 */
11200     { Bad_Opcode },
11201     { "psraw",          { MS, Ib } },
11202   },
11203   {
11204     /* MOD_0F71_REG_6 */
11205     { Bad_Opcode },
11206     { "psllw",          { MS, Ib } },
11207   },
11208   {
11209     /* MOD_0F72_REG_2 */
11210     { Bad_Opcode },
11211     { "psrld",          { MS, Ib } },
11212   },
11213   {
11214     /* MOD_0F72_REG_4 */
11215     { Bad_Opcode },
11216     { "psrad",          { MS, Ib } },
11217   },
11218   {
11219     /* MOD_0F72_REG_6 */
11220     { Bad_Opcode },
11221     { "pslld",          { MS, Ib } },
11222   },
11223   {
11224     /* MOD_0F73_REG_2 */
11225     { Bad_Opcode },
11226     { "psrlq",          { MS, Ib } },
11227   },
11228   {
11229     /* MOD_0F73_REG_3 */
11230     { Bad_Opcode },
11231     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
11232   },
11233   {
11234     /* MOD_0F73_REG_6 */
11235     { Bad_Opcode },
11236     { "psllq",          { MS, Ib } },
11237   },
11238   {
11239     /* MOD_0F73_REG_7 */
11240     { Bad_Opcode },
11241     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
11242   },
11243   {
11244     /* MOD_0FAE_REG_0 */
11245     { "fxsave",         { FXSAVE } },
11246     { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
11247   },
11248   {
11249     /* MOD_0FAE_REG_1 */
11250     { "fxrstor",        { FXSAVE } },
11251     { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
11252   },
11253   {
11254     /* MOD_0FAE_REG_2 */
11255     { "ldmxcsr",        { Md } },
11256     { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
11257   },
11258   {
11259     /* MOD_0FAE_REG_3 */
11260     { "stmxcsr",        { Md } },
11261     { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
11262   },
11263   {
11264     /* MOD_0FAE_REG_4 */
11265     { "xsave",          { FXSAVE } },
11266   },
11267   {
11268     /* MOD_0FAE_REG_5 */
11269     { "xrstor",         { FXSAVE } },
11270     { RM_TABLE (RM_0FAE_REG_5) },
11271   },
11272   {
11273     /* MOD_0FAE_REG_6 */
11274     { "xsaveopt",       { FXSAVE } },
11275     { RM_TABLE (RM_0FAE_REG_6) },
11276   },
11277   {
11278     /* MOD_0FAE_REG_7 */
11279     { "clflush",        { Mb } },
11280     { RM_TABLE (RM_0FAE_REG_7) },
11281   },
11282   {
11283     /* MOD_0FB2 */
11284     { "lssS",           { Gv, Mp } },
11285   },
11286   {
11287     /* MOD_0FB4 */
11288     { "lfsS",           { Gv, Mp } },
11289   },
11290   {
11291     /* MOD_0FB5 */
11292     { "lgsS",           { Gv, Mp } },
11293   },
11294   {
11295     /* MOD_0FC7_REG_6 */
11296     { PREFIX_TABLE (PREFIX_0FC7_REG_6) },
11297     { "rdrand",         { Ev } },
11298   },
11299   {
11300     /* MOD_0FC7_REG_7 */
11301     { "vmptrst",        { Mq } },
11302     { "rdseed",         { Ev } },
11303   },
11304   {
11305     /* MOD_0FD7 */
11306     { Bad_Opcode },
11307     { "pmovmskb",       { Gdq, MS } },
11308   },
11309   {
11310     /* MOD_0FE7_PREFIX_2 */
11311     { "movntdq",        { Mx, XM } },
11312   },
11313   {
11314     /* MOD_0FF0_PREFIX_3 */
11315     { "lddqu",          { XM, M } },
11316   },
11317   {
11318     /* MOD_0F382A_PREFIX_2 */
11319     { "movntdqa",       { XM, Mx } },
11320   },
11321   {
11322     /* MOD_62_32BIT */
11323     { "bound{S|}",      { Gv, Ma } },
11324     { EVEX_TABLE (EVEX_0F) },
11325   },
11326   {
11327     /* MOD_C4_32BIT */
11328     { "lesS",           { Gv, Mp } },
11329     { VEX_C4_TABLE (VEX_0F) },
11330   },
11331   {
11332     /* MOD_C5_32BIT */
11333     { "ldsS",           { Gv, Mp } },
11334     { VEX_C5_TABLE (VEX_0F) },
11335   },
11336   {
11337     /* MOD_VEX_0F12_PREFIX_0 */
11338     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
11339     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
11340   },
11341   {
11342     /* MOD_VEX_0F13 */
11343     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
11344   },
11345   {
11346     /* MOD_VEX_0F16_PREFIX_0 */
11347     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
11348     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
11349   },
11350   {
11351     /* MOD_VEX_0F17 */
11352     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
11353   },
11354   {
11355     /* MOD_VEX_0F2B */
11356     { VEX_W_TABLE (VEX_W_0F2B_M_0) },
11357   },
11358   {
11359     /* MOD_VEX_0F50 */
11360     { Bad_Opcode },
11361     { VEX_W_TABLE (VEX_W_0F50_M_0) },
11362   },
11363   {
11364     /* MOD_VEX_0F71_REG_2 */
11365     { Bad_Opcode },
11366     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
11367   },
11368   {
11369     /* MOD_VEX_0F71_REG_4 */
11370     { Bad_Opcode },
11371     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
11372   },
11373   {
11374     /* MOD_VEX_0F71_REG_6 */
11375     { Bad_Opcode },
11376     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
11377   },
11378   {
11379     /* MOD_VEX_0F72_REG_2 */
11380     { Bad_Opcode },
11381     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
11382   },
11383   {
11384     /* MOD_VEX_0F72_REG_4 */
11385     { Bad_Opcode },
11386     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
11387   },
11388   {
11389     /* MOD_VEX_0F72_REG_6 */
11390     { Bad_Opcode },
11391     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
11392   },
11393   {
11394     /* MOD_VEX_0F73_REG_2 */
11395     { Bad_Opcode },
11396     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
11397   },
11398   {
11399     /* MOD_VEX_0F73_REG_3 */
11400     { Bad_Opcode },
11401     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
11402   },
11403   {
11404     /* MOD_VEX_0F73_REG_6 */
11405     { Bad_Opcode },
11406     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
11407   },
11408   {
11409     /* MOD_VEX_0F73_REG_7 */
11410     { Bad_Opcode },
11411     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
11412   },
11413   {
11414     /* MOD_VEX_0FAE_REG_2 */
11415     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
11416   },
11417   {
11418     /* MOD_VEX_0FAE_REG_3 */
11419     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
11420   },
11421   {
11422     /* MOD_VEX_0FD7_PREFIX_2 */
11423     { Bad_Opcode },
11424     { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) },
11425   },
11426   {
11427     /* MOD_VEX_0FE7_PREFIX_2 */
11428     { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) },
11429   },
11430   {
11431     /* MOD_VEX_0FF0_PREFIX_3 */
11432     { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) },
11433   },
11434   {
11435     /* MOD_VEX_0F381A_PREFIX_2 */
11436     { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
11437   },
11438   {
11439     /* MOD_VEX_0F382A_PREFIX_2 */
11440     { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) },
11441   },
11442   {
11443     /* MOD_VEX_0F382C_PREFIX_2 */
11444     { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
11445   },
11446   {
11447     /* MOD_VEX_0F382D_PREFIX_2 */
11448     { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
11449   },
11450   {
11451     /* MOD_VEX_0F382E_PREFIX_2 */
11452     { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
11453   },
11454   {
11455     /* MOD_VEX_0F382F_PREFIX_2 */
11456     { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
11457   },
11458   {
11459     /* MOD_VEX_0F385A_PREFIX_2 */
11460     { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
11461   },
11462   {
11463     /* MOD_VEX_0F388C_PREFIX_2 */
11464     { "vpmaskmov%LW",   { XM, Vex, Mx } },
11465   },
11466   {
11467     /* MOD_VEX_0F388E_PREFIX_2 */
11468     { "vpmaskmov%LW",   { Mx, Vex, XM } },
11469   },
11470 #define NEED_MOD_TABLE
11471 #include "i386-dis-evex.h"
11472 #undef NEED_MOD_TABLE
11473 };
11474
11475 static const struct dis386 rm_table[][8] = {
11476   {
11477     /* RM_C6_REG_7 */
11478     { "xabort",         { Skip_MODRM, Ib } },
11479   },
11480   {
11481     /* RM_C7_REG_7 */
11482     { "xbeginT",        { Skip_MODRM, Jv } },
11483   },
11484   {
11485     /* RM_0F01_REG_0 */
11486     { Bad_Opcode },
11487     { "vmcall",         { Skip_MODRM } },
11488     { "vmlaunch",       { Skip_MODRM } },
11489     { "vmresume",       { Skip_MODRM } },
11490     { "vmxoff",         { Skip_MODRM } },
11491   },
11492   {
11493     /* RM_0F01_REG_1 */
11494     { "monitor",        { { OP_Monitor, 0 } } },
11495     { "mwait",          { { OP_Mwait, 0 } } },
11496     { "clac",           { Skip_MODRM } },
11497     { "stac",           { Skip_MODRM } },
11498   },
11499   {
11500     /* RM_0F01_REG_2 */
11501     { "xgetbv",         { Skip_MODRM } },
11502     { "xsetbv",         { Skip_MODRM } },
11503     { Bad_Opcode },
11504     { Bad_Opcode },
11505     { "vmfunc",         { Skip_MODRM } },
11506     { "xend",           { Skip_MODRM } },
11507     { "xtest",          { Skip_MODRM } },
11508     { Bad_Opcode },
11509   },
11510   {
11511     /* RM_0F01_REG_3 */
11512     { "vmrun",          { Skip_MODRM } },
11513     { "vmmcall",        { Skip_MODRM } },
11514     { "vmload",         { Skip_MODRM } },
11515     { "vmsave",         { Skip_MODRM } },
11516     { "stgi",           { Skip_MODRM } },
11517     { "clgi",           { Skip_MODRM } },
11518     { "skinit",         { Skip_MODRM } },
11519     { "invlpga",        { Skip_MODRM } },
11520   },
11521   {
11522     /* RM_0F01_REG_7 */
11523     { "swapgs",         { Skip_MODRM } },
11524     { "rdtscp",         { Skip_MODRM } },
11525   },
11526   {
11527     /* RM_0FAE_REG_5 */
11528     { "lfence",         { Skip_MODRM } },
11529   },
11530   {
11531     /* RM_0FAE_REG_6 */
11532     { "mfence",         { Skip_MODRM } },
11533   },
11534   {
11535     /* RM_0FAE_REG_7 */
11536     { "sfence",         { Skip_MODRM } },
11537   },
11538 };
11539
11540 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
11541
11542 /* We use the high bit to indicate different name for the same
11543    prefix.  */
11544 #define ADDR16_PREFIX   (0x67 | 0x100)
11545 #define ADDR32_PREFIX   (0x67 | 0x200)
11546 #define DATA16_PREFIX   (0x66 | 0x100)
11547 #define DATA32_PREFIX   (0x66 | 0x200)
11548 #define REP_PREFIX      (0xf3 | 0x100)
11549 #define XACQUIRE_PREFIX (0xf2 | 0x200)
11550 #define XRELEASE_PREFIX (0xf3 | 0x400)
11551 #define BND_PREFIX      (0xf2 | 0x400)
11552
11553 static int
11554 ckprefix (void)
11555 {
11556   int newrex, i, length;
11557   rex = 0;
11558   rex_ignored = 0;
11559   prefixes = 0;
11560   used_prefixes = 0;
11561   rex_used = 0;
11562   last_lock_prefix = -1;
11563   last_repz_prefix = -1;
11564   last_repnz_prefix = -1;
11565   last_data_prefix = -1;
11566   last_addr_prefix = -1;
11567   last_rex_prefix = -1;
11568   last_seg_prefix = -1;
11569   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
11570     all_prefixes[i] = 0;
11571   i = 0;
11572   length = 0;
11573   /* The maximum instruction length is 15bytes.  */
11574   while (length < MAX_CODE_LENGTH - 1)
11575     {
11576       FETCH_DATA (the_info, codep + 1);
11577       newrex = 0;
11578       switch (*codep)
11579         {
11580         /* REX prefixes family.  */
11581         case 0x40:
11582         case 0x41:
11583         case 0x42:
11584         case 0x43:
11585         case 0x44:
11586         case 0x45:
11587         case 0x46:
11588         case 0x47:
11589         case 0x48:
11590         case 0x49:
11591         case 0x4a:
11592         case 0x4b:
11593         case 0x4c:
11594         case 0x4d:
11595         case 0x4e:
11596         case 0x4f:
11597           if (address_mode == mode_64bit)
11598             newrex = *codep;
11599           else
11600             return 1;
11601           last_rex_prefix = i;
11602           break;
11603         case 0xf3:
11604           prefixes |= PREFIX_REPZ;
11605           last_repz_prefix = i;
11606           break;
11607         case 0xf2:
11608           prefixes |= PREFIX_REPNZ;
11609           last_repnz_prefix = i;
11610           break;
11611         case 0xf0:
11612           prefixes |= PREFIX_LOCK;
11613           last_lock_prefix = i;
11614           break;
11615         case 0x2e:
11616           prefixes |= PREFIX_CS;
11617           last_seg_prefix = i;
11618           break;
11619         case 0x36:
11620           prefixes |= PREFIX_SS;
11621           last_seg_prefix = i;
11622           break;
11623         case 0x3e:
11624           prefixes |= PREFIX_DS;
11625           last_seg_prefix = i;
11626           break;
11627         case 0x26:
11628           prefixes |= PREFIX_ES;
11629           last_seg_prefix = i;
11630           break;
11631         case 0x64:
11632           prefixes |= PREFIX_FS;
11633           last_seg_prefix = i;
11634           break;
11635         case 0x65:
11636           prefixes |= PREFIX_GS;
11637           last_seg_prefix = i;
11638           break;
11639         case 0x66:
11640           prefixes |= PREFIX_DATA;
11641           last_data_prefix = i;
11642           break;
11643         case 0x67:
11644           prefixes |= PREFIX_ADDR;
11645           last_addr_prefix = i;
11646           break;
11647         case FWAIT_OPCODE:
11648           /* fwait is really an instruction.  If there are prefixes
11649              before the fwait, they belong to the fwait, *not* to the
11650              following instruction.  */
11651           if (prefixes || rex)
11652             {
11653               prefixes |= PREFIX_FWAIT;
11654               codep++;
11655               /* This ensures that the previous REX prefixes are noticed
11656                  as unused prefixes, as in the return case below.  */
11657               rex_used = rex;
11658               return 1;
11659             }
11660           prefixes = PREFIX_FWAIT;
11661           break;
11662         default:
11663           return 1;
11664         }
11665       /* Rex is ignored when followed by another prefix.  */
11666       if (rex)
11667         {
11668           rex_used = rex;
11669           return 1;
11670         }
11671       if (*codep != FWAIT_OPCODE)
11672         all_prefixes[i++] = *codep;
11673       rex = newrex;
11674       codep++;
11675       length++;
11676     }
11677   return 0;
11678 }
11679
11680 static int
11681 seg_prefix (int pref)
11682 {
11683   switch (pref)
11684     {
11685     case 0x2e:
11686       return PREFIX_CS;
11687     case 0x36:
11688       return PREFIX_SS;
11689     case 0x3e:
11690       return PREFIX_DS;
11691     case 0x26:
11692       return PREFIX_ES;
11693     case 0x64:
11694       return PREFIX_FS;
11695     case 0x65:
11696       return PREFIX_GS;
11697     default:
11698       return 0;
11699     }
11700 }
11701
11702 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
11703    prefix byte.  */
11704
11705 static const char *
11706 prefix_name (int pref, int sizeflag)
11707 {
11708   static const char *rexes [16] =
11709     {
11710       "rex",            /* 0x40 */
11711       "rex.B",          /* 0x41 */
11712       "rex.X",          /* 0x42 */
11713       "rex.XB",         /* 0x43 */
11714       "rex.R",          /* 0x44 */
11715       "rex.RB",         /* 0x45 */
11716       "rex.RX",         /* 0x46 */
11717       "rex.RXB",        /* 0x47 */
11718       "rex.W",          /* 0x48 */
11719       "rex.WB",         /* 0x49 */
11720       "rex.WX",         /* 0x4a */
11721       "rex.WXB",        /* 0x4b */
11722       "rex.WR",         /* 0x4c */
11723       "rex.WRB",        /* 0x4d */
11724       "rex.WRX",        /* 0x4e */
11725       "rex.WRXB",       /* 0x4f */
11726     };
11727
11728   switch (pref)
11729     {
11730     /* REX prefixes family.  */
11731     case 0x40:
11732     case 0x41:
11733     case 0x42:
11734     case 0x43:
11735     case 0x44:
11736     case 0x45:
11737     case 0x46:
11738     case 0x47:
11739     case 0x48:
11740     case 0x49:
11741     case 0x4a:
11742     case 0x4b:
11743     case 0x4c:
11744     case 0x4d:
11745     case 0x4e:
11746     case 0x4f:
11747       return rexes [pref - 0x40];
11748     case 0xf3:
11749       return "repz";
11750     case 0xf2:
11751       return "repnz";
11752     case 0xf0:
11753       return "lock";
11754     case 0x2e:
11755       return "cs";
11756     case 0x36:
11757       return "ss";
11758     case 0x3e:
11759       return "ds";
11760     case 0x26:
11761       return "es";
11762     case 0x64:
11763       return "fs";
11764     case 0x65:
11765       return "gs";
11766     case 0x66:
11767       return (sizeflag & DFLAG) ? "data16" : "data32";
11768     case 0x67:
11769       if (address_mode == mode_64bit)
11770         return (sizeflag & AFLAG) ? "addr32" : "addr64";
11771       else
11772         return (sizeflag & AFLAG) ? "addr16" : "addr32";
11773     case FWAIT_OPCODE:
11774       return "fwait";
11775     case ADDR16_PREFIX:
11776       return "addr16";
11777     case ADDR32_PREFIX:
11778       return "addr32";
11779     case DATA16_PREFIX:
11780       return "data16";
11781     case DATA32_PREFIX:
11782       return "data32";
11783     case REP_PREFIX:
11784       return "rep";
11785     case XACQUIRE_PREFIX:
11786       return "xacquire";
11787     case XRELEASE_PREFIX:
11788       return "xrelease";
11789     case BND_PREFIX:
11790       return "bnd";
11791     default:
11792       return NULL;
11793     }
11794 }
11795
11796 static char op_out[MAX_OPERANDS][100];
11797 static int op_ad, op_index[MAX_OPERANDS];
11798 static int two_source_ops;
11799 static bfd_vma op_address[MAX_OPERANDS];
11800 static bfd_vma op_riprel[MAX_OPERANDS];
11801 static bfd_vma start_pc;
11802
11803 /*
11804  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
11805  *   (see topic "Redundant prefixes" in the "Differences from 8086"
11806  *   section of the "Virtual 8086 Mode" chapter.)
11807  * 'pc' should be the address of this instruction, it will
11808  *   be used to print the target address if this is a relative jump or call
11809  * The function returns the length of this instruction in bytes.
11810  */
11811
11812 static char intel_syntax;
11813 static char intel_mnemonic = !SYSV386_COMPAT;
11814 static char open_char;
11815 static char close_char;
11816 static char separator_char;
11817 static char scale_char;
11818
11819 /* Here for backwards compatibility.  When gdb stops using
11820    print_insn_i386_att and print_insn_i386_intel these functions can
11821    disappear, and print_insn_i386 be merged into print_insn.  */
11822 int
11823 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
11824 {
11825   intel_syntax = 0;
11826
11827   return print_insn (pc, info);
11828 }
11829
11830 int
11831 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
11832 {
11833   intel_syntax = 1;
11834
11835   return print_insn (pc, info);
11836 }
11837
11838 int
11839 print_insn_i386 (bfd_vma pc, disassemble_info *info)
11840 {
11841   intel_syntax = -1;
11842
11843   return print_insn (pc, info);
11844 }
11845
11846 void
11847 print_i386_disassembler_options (FILE *stream)
11848 {
11849   fprintf (stream, _("\n\
11850 The following i386/x86-64 specific disassembler options are supported for use\n\
11851 with the -M switch (multiple options should be separated by commas):\n"));
11852
11853   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
11854   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
11855   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
11856   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
11857   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
11858   fprintf (stream, _("  att-mnemonic\n"
11859                      "              Display instruction in AT&T mnemonic\n"));
11860   fprintf (stream, _("  intel-mnemonic\n"
11861                      "              Display instruction in Intel mnemonic\n"));
11862   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
11863   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
11864   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
11865   fprintf (stream, _("  data32      Assume 32bit data size\n"));
11866   fprintf (stream, _("  data16      Assume 16bit data size\n"));
11867   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
11868 }
11869
11870 /* Bad opcode.  */
11871 static const struct dis386 bad_opcode = { "(bad)", { XX } };
11872
11873 /* Get a pointer to struct dis386 with a valid name.  */
11874
11875 static const struct dis386 *
11876 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
11877 {
11878   int vindex, vex_table_index;
11879
11880   if (dp->name != NULL)
11881     return dp;
11882
11883   switch (dp->op[0].bytemode)
11884     {
11885     case USE_REG_TABLE:
11886       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
11887       break;
11888
11889     case USE_MOD_TABLE:
11890       vindex = modrm.mod == 0x3 ? 1 : 0;
11891       dp = &mod_table[dp->op[1].bytemode][vindex];
11892       break;
11893
11894     case USE_RM_TABLE:
11895       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
11896       break;
11897
11898     case USE_PREFIX_TABLE:
11899       if (need_vex)
11900         {
11901           /* The prefix in VEX is implicit.  */
11902           switch (vex.prefix)
11903             {
11904             case 0:
11905               vindex = 0;
11906               break;
11907             case REPE_PREFIX_OPCODE:
11908               vindex = 1;
11909               break;
11910             case DATA_PREFIX_OPCODE:
11911               vindex = 2;
11912               break;
11913             case REPNE_PREFIX_OPCODE:
11914               vindex = 3;
11915               break;
11916             default:
11917               abort ();
11918               break;
11919             }
11920         }
11921       else
11922         {
11923           vindex = 0;
11924           used_prefixes |= (prefixes & PREFIX_REPZ);
11925           if (prefixes & PREFIX_REPZ)
11926             {
11927               vindex = 1;
11928               all_prefixes[last_repz_prefix] = 0;
11929             }
11930           else
11931             {
11932               /* We should check PREFIX_REPNZ and PREFIX_REPZ before
11933                  PREFIX_DATA.  */
11934               used_prefixes |= (prefixes & PREFIX_REPNZ);
11935               if (prefixes & PREFIX_REPNZ)
11936                 {
11937                   vindex = 3;
11938                   all_prefixes[last_repnz_prefix] = 0;
11939                 }
11940               else
11941                 {
11942                   used_prefixes |= (prefixes & PREFIX_DATA);
11943                   if (prefixes & PREFIX_DATA)
11944                     {
11945                       vindex = 2;
11946                       all_prefixes[last_data_prefix] = 0;
11947                     }
11948                 }
11949             }
11950         }
11951       dp = &prefix_table[dp->op[1].bytemode][vindex];
11952       break;
11953
11954     case USE_X86_64_TABLE:
11955       vindex = address_mode == mode_64bit ? 1 : 0;
11956       dp = &x86_64_table[dp->op[1].bytemode][vindex];
11957       break;
11958
11959     case USE_3BYTE_TABLE:
11960       FETCH_DATA (info, codep + 2);
11961       vindex = *codep++;
11962       dp = &three_byte_table[dp->op[1].bytemode][vindex];
11963       modrm.mod = (*codep >> 6) & 3;
11964       modrm.reg = (*codep >> 3) & 7;
11965       modrm.rm = *codep & 7;
11966       break;
11967
11968     case USE_VEX_LEN_TABLE:
11969       if (!need_vex)
11970         abort ();
11971
11972       switch (vex.length)
11973         {
11974         case 128:
11975           vindex = 0;
11976           break;
11977         case 256:
11978           vindex = 1;
11979           break;
11980         default:
11981           abort ();
11982           break;
11983         }
11984
11985       dp = &vex_len_table[dp->op[1].bytemode][vindex];
11986       break;
11987
11988     case USE_XOP_8F_TABLE:
11989       FETCH_DATA (info, codep + 3);
11990       /* All bits in the REX prefix are ignored.  */
11991       rex_ignored = rex;
11992       rex = ~(*codep >> 5) & 0x7;
11993
11994       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
11995       switch ((*codep & 0x1f))
11996         {
11997         default:
11998           dp = &bad_opcode;
11999           return dp;
12000         case 0x8:
12001           vex_table_index = XOP_08;
12002           break;
12003         case 0x9:
12004           vex_table_index = XOP_09;
12005           break;
12006         case 0xa:
12007           vex_table_index = XOP_0A;
12008           break;
12009         }
12010       codep++;
12011       vex.w = *codep & 0x80;
12012       if (vex.w && address_mode == mode_64bit)
12013         rex |= REX_W;
12014
12015       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12016       if (address_mode != mode_64bit
12017           && vex.register_specifier > 0x7)
12018         {
12019           dp = &bad_opcode;
12020           return dp;
12021         }
12022
12023       vex.length = (*codep & 0x4) ? 256 : 128;
12024       switch ((*codep & 0x3))
12025         {
12026         case 0:
12027           vex.prefix = 0;
12028           break;
12029         case 1:
12030           vex.prefix = DATA_PREFIX_OPCODE;
12031           break;
12032         case 2:
12033           vex.prefix = REPE_PREFIX_OPCODE;
12034           break;
12035         case 3:
12036           vex.prefix = REPNE_PREFIX_OPCODE;
12037           break;
12038         }
12039       need_vex = 1;
12040       need_vex_reg = 1;
12041       codep++;
12042       vindex = *codep++;
12043       dp = &xop_table[vex_table_index][vindex];
12044
12045       FETCH_DATA (info, codep + 1);
12046       modrm.mod = (*codep >> 6) & 3;
12047       modrm.reg = (*codep >> 3) & 7;
12048       modrm.rm = *codep & 7;
12049       break;
12050
12051     case USE_VEX_C4_TABLE:
12052       /* VEX prefix.  */
12053       FETCH_DATA (info, codep + 3);
12054       /* All bits in the REX prefix are ignored.  */
12055       rex_ignored = rex;
12056       rex = ~(*codep >> 5) & 0x7;
12057       switch ((*codep & 0x1f))
12058         {
12059         default:
12060           dp = &bad_opcode;
12061           return dp;
12062         case 0x1:
12063           vex_table_index = VEX_0F;
12064           break;
12065         case 0x2:
12066           vex_table_index = VEX_0F38;
12067           break;
12068         case 0x3:
12069           vex_table_index = VEX_0F3A;
12070           break;
12071         }
12072       codep++;
12073       vex.w = *codep & 0x80;
12074       if (vex.w && address_mode == mode_64bit)
12075         rex |= REX_W;
12076
12077       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12078       if (address_mode != mode_64bit
12079           && vex.register_specifier > 0x7)
12080         {
12081           dp = &bad_opcode;
12082           return dp;
12083         }
12084
12085       vex.length = (*codep & 0x4) ? 256 : 128;
12086       switch ((*codep & 0x3))
12087         {
12088         case 0:
12089           vex.prefix = 0;
12090           break;
12091         case 1:
12092           vex.prefix = DATA_PREFIX_OPCODE;
12093           break;
12094         case 2:
12095           vex.prefix = REPE_PREFIX_OPCODE;
12096           break;
12097         case 3:
12098           vex.prefix = REPNE_PREFIX_OPCODE;
12099           break;
12100         }
12101       need_vex = 1;
12102       need_vex_reg = 1;
12103       codep++;
12104       vindex = *codep++;
12105       dp = &vex_table[vex_table_index][vindex];
12106       /* There is no MODRM byte for VEX [82|77].  */
12107       if (vindex != 0x77 && vindex != 0x82)
12108         {
12109           FETCH_DATA (info, codep + 1);
12110           modrm.mod = (*codep >> 6) & 3;
12111           modrm.reg = (*codep >> 3) & 7;
12112           modrm.rm = *codep & 7;
12113         }
12114       break;
12115
12116     case USE_VEX_C5_TABLE:
12117       /* VEX prefix.  */
12118       FETCH_DATA (info, codep + 2);
12119       /* All bits in the REX prefix are ignored.  */
12120       rex_ignored = rex;
12121       rex = (*codep & 0x80) ? 0 : REX_R;
12122
12123       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12124       if (address_mode != mode_64bit
12125           && vex.register_specifier > 0x7)
12126         {
12127           dp = &bad_opcode;
12128           return dp;
12129         }
12130
12131       vex.w = 0;
12132
12133       vex.length = (*codep & 0x4) ? 256 : 128;
12134       switch ((*codep & 0x3))
12135         {
12136         case 0:
12137           vex.prefix = 0;
12138           break;
12139         case 1:
12140           vex.prefix = DATA_PREFIX_OPCODE;
12141           break;
12142         case 2:
12143           vex.prefix = REPE_PREFIX_OPCODE;
12144           break;
12145         case 3:
12146           vex.prefix = REPNE_PREFIX_OPCODE;
12147           break;
12148         }
12149       need_vex = 1;
12150       need_vex_reg = 1;
12151       codep++;
12152       vindex = *codep++;
12153       dp = &vex_table[dp->op[1].bytemode][vindex];
12154       /* There is no MODRM byte for VEX [82|77].  */
12155       if (vindex != 0x77 && vindex != 0x82)
12156         {
12157           FETCH_DATA (info, codep + 1);
12158           modrm.mod = (*codep >> 6) & 3;
12159           modrm.reg = (*codep >> 3) & 7;
12160           modrm.rm = *codep & 7;
12161         }
12162       break;
12163
12164     case USE_VEX_W_TABLE:
12165       if (!need_vex)
12166         abort ();
12167
12168       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
12169       break;
12170
12171     case USE_EVEX_TABLE:
12172       two_source_ops = 0;
12173       /* EVEX prefix.  */
12174       vex.evex = 1;
12175       FETCH_DATA (info, codep + 4);
12176       /* All bits in the REX prefix are ignored.  */
12177       rex_ignored = rex;
12178       /* The first byte after 0x62.  */
12179       rex = ~(*codep >> 5) & 0x7;
12180       vex.r = *codep & 0x10;
12181       switch ((*codep & 0xf))
12182         {
12183         default:
12184           return &bad_opcode;
12185         case 0x1:
12186           vex_table_index = EVEX_0F;
12187           break;
12188         case 0x2:
12189           vex_table_index = EVEX_0F38;
12190           break;
12191         case 0x3:
12192           vex_table_index = EVEX_0F3A;
12193           break;
12194         }
12195
12196       /* The second byte after 0x62.  */
12197       codep++;
12198       vex.w = *codep & 0x80;
12199       if (vex.w && address_mode == mode_64bit)
12200         rex |= REX_W;
12201
12202       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12203       if (address_mode != mode_64bit)
12204         {
12205           /* In 16/32-bit mode silently ignore following bits.  */
12206           rex &= ~REX_B;
12207           vex.r = 1;
12208           vex.v = 1;
12209           vex.register_specifier &= 0x7;
12210         }
12211
12212       /* The U bit.  */
12213       if (!(*codep & 0x4))
12214         return &bad_opcode;
12215
12216       switch ((*codep & 0x3))
12217         {
12218         case 0:
12219           vex.prefix = 0;
12220           break;
12221         case 1:
12222           vex.prefix = DATA_PREFIX_OPCODE;
12223           break;
12224         case 2:
12225           vex.prefix = REPE_PREFIX_OPCODE;
12226           break;
12227         case 3:
12228           vex.prefix = REPNE_PREFIX_OPCODE;
12229           break;
12230         }
12231
12232       /* The third byte after 0x62.  */
12233       codep++;
12234
12235       /* Remember the static rounding bits.  */
12236       vex.ll = (*codep >> 5) & 3;
12237       vex.b = (*codep & 0x10) != 0;
12238
12239       vex.v = *codep & 0x8;
12240       vex.mask_register_specifier = *codep & 0x7;
12241       vex.zeroing = *codep & 0x80;
12242
12243       need_vex = 1;
12244       need_vex_reg = 1;
12245       codep++;
12246       vindex = *codep++;
12247       dp = &evex_table[vex_table_index][vindex];
12248       FETCH_DATA (info, codep + 1);
12249       modrm.mod = (*codep >> 6) & 3;
12250       modrm.reg = (*codep >> 3) & 7;
12251       modrm.rm = *codep & 7;
12252
12253       /* Set vector length.  */
12254       if (modrm.mod == 3 && vex.b)
12255         vex.length = 512;
12256       else
12257         {
12258           switch (vex.ll)
12259             {
12260             case 0x0:
12261               vex.length = 128;
12262               break;
12263             case 0x1:
12264               vex.length = 256;
12265               break;
12266             case 0x2:
12267               vex.length = 512;
12268               break;
12269             default:
12270               return &bad_opcode;
12271             }
12272         }
12273       break;
12274
12275     case 0:
12276       dp = &bad_opcode;
12277       break;
12278
12279     default:
12280       abort ();
12281     }
12282
12283   if (dp->name != NULL)
12284     return dp;
12285   else
12286     return get_valid_dis386 (dp, info);
12287 }
12288
12289 static void
12290 get_sib (disassemble_info *info, int sizeflag)
12291 {
12292   /* If modrm.mod == 3, operand must be register.  */
12293   if (need_modrm
12294       && ((sizeflag & AFLAG) || address_mode == mode_64bit)
12295       && modrm.mod != 3
12296       && modrm.rm == 4)
12297     {
12298       FETCH_DATA (info, codep + 2);
12299       sib.index = (codep [1] >> 3) & 7;
12300       sib.scale = (codep [1] >> 6) & 3;
12301       sib.base = codep [1] & 7;
12302     }
12303 }
12304
12305 static int
12306 print_insn (bfd_vma pc, disassemble_info *info)
12307 {
12308   const struct dis386 *dp;
12309   int i;
12310   char *op_txt[MAX_OPERANDS];
12311   int needcomma;
12312   int sizeflag;
12313   const char *p;
12314   struct dis_private priv;
12315   int prefix_length;
12316   int default_prefixes;
12317
12318   priv.orig_sizeflag = AFLAG | DFLAG;
12319   if ((info->mach & bfd_mach_i386_i386) != 0)
12320     address_mode = mode_32bit;
12321   else if (info->mach == bfd_mach_i386_i8086)
12322     {
12323       address_mode = mode_16bit;
12324       priv.orig_sizeflag = 0;
12325     }
12326   else
12327     address_mode = mode_64bit;
12328
12329   if (intel_syntax == (char) -1)
12330     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
12331
12332   for (p = info->disassembler_options; p != NULL; )
12333     {
12334       if (CONST_STRNEQ (p, "x86-64"))
12335         {
12336           address_mode = mode_64bit;
12337           priv.orig_sizeflag = AFLAG | DFLAG;
12338         }
12339       else if (CONST_STRNEQ (p, "i386"))
12340         {
12341           address_mode = mode_32bit;
12342           priv.orig_sizeflag = AFLAG | DFLAG;
12343         }
12344       else if (CONST_STRNEQ (p, "i8086"))
12345         {
12346           address_mode = mode_16bit;
12347           priv.orig_sizeflag = 0;
12348         }
12349       else if (CONST_STRNEQ (p, "intel"))
12350         {
12351           intel_syntax = 1;
12352           if (CONST_STRNEQ (p + 5, "-mnemonic"))
12353             intel_mnemonic = 1;
12354         }
12355       else if (CONST_STRNEQ (p, "att"))
12356         {
12357           intel_syntax = 0;
12358           if (CONST_STRNEQ (p + 3, "-mnemonic"))
12359             intel_mnemonic = 0;
12360         }
12361       else if (CONST_STRNEQ (p, "addr"))
12362         {
12363           if (address_mode == mode_64bit)
12364             {
12365               if (p[4] == '3' && p[5] == '2')
12366                 priv.orig_sizeflag &= ~AFLAG;
12367               else if (p[4] == '6' && p[5] == '4')
12368                 priv.orig_sizeflag |= AFLAG;
12369             }
12370           else
12371             {
12372               if (p[4] == '1' && p[5] == '6')
12373                 priv.orig_sizeflag &= ~AFLAG;
12374               else if (p[4] == '3' && p[5] == '2')
12375                 priv.orig_sizeflag |= AFLAG;
12376             }
12377         }
12378       else if (CONST_STRNEQ (p, "data"))
12379         {
12380           if (p[4] == '1' && p[5] == '6')
12381             priv.orig_sizeflag &= ~DFLAG;
12382           else if (p[4] == '3' && p[5] == '2')
12383             priv.orig_sizeflag |= DFLAG;
12384         }
12385       else if (CONST_STRNEQ (p, "suffix"))
12386         priv.orig_sizeflag |= SUFFIX_ALWAYS;
12387
12388       p = strchr (p, ',');
12389       if (p != NULL)
12390         p++;
12391     }
12392
12393   if (intel_syntax)
12394     {
12395       names64 = intel_names64;
12396       names32 = intel_names32;
12397       names16 = intel_names16;
12398       names8 = intel_names8;
12399       names8rex = intel_names8rex;
12400       names_seg = intel_names_seg;
12401       names_mm = intel_names_mm;
12402       names_bnd = intel_names_bnd;
12403       names_xmm = intel_names_xmm;
12404       names_ymm = intel_names_ymm;
12405       names_zmm = intel_names_zmm;
12406       index64 = intel_index64;
12407       index32 = intel_index32;
12408       names_mask = intel_names_mask;
12409       index16 = intel_index16;
12410       open_char = '[';
12411       close_char = ']';
12412       separator_char = '+';
12413       scale_char = '*';
12414     }
12415   else
12416     {
12417       names64 = att_names64;
12418       names32 = att_names32;
12419       names16 = att_names16;
12420       names8 = att_names8;
12421       names8rex = att_names8rex;
12422       names_seg = att_names_seg;
12423       names_mm = att_names_mm;
12424       names_bnd = att_names_bnd;
12425       names_xmm = att_names_xmm;
12426       names_ymm = att_names_ymm;
12427       names_zmm = att_names_zmm;
12428       index64 = att_index64;
12429       index32 = att_index32;
12430       names_mask = att_names_mask;
12431       index16 = att_index16;
12432       open_char = '(';
12433       close_char =  ')';
12434       separator_char = ',';
12435       scale_char = ',';
12436     }
12437
12438   /* The output looks better if we put 7 bytes on a line, since that
12439      puts most long word instructions on a single line.  Use 8 bytes
12440      for Intel L1OM.  */
12441   if ((info->mach & bfd_mach_l1om) != 0)
12442     info->bytes_per_line = 8;
12443   else
12444     info->bytes_per_line = 7;
12445
12446   info->private_data = &priv;
12447   priv.max_fetched = priv.the_buffer;
12448   priv.insn_start = pc;
12449
12450   obuf[0] = 0;
12451   for (i = 0; i < MAX_OPERANDS; ++i)
12452     {
12453       op_out[i][0] = 0;
12454       op_index[i] = -1;
12455     }
12456
12457   the_info = info;
12458   start_pc = pc;
12459   start_codep = priv.the_buffer;
12460   codep = priv.the_buffer;
12461
12462   if (setjmp (priv.bailout) != 0)
12463     {
12464       const char *name;
12465
12466       /* Getting here means we tried for data but didn't get it.  That
12467          means we have an incomplete instruction of some sort.  Just
12468          print the first byte as a prefix or a .byte pseudo-op.  */
12469       if (codep > priv.the_buffer)
12470         {
12471           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
12472           if (name != NULL)
12473             (*info->fprintf_func) (info->stream, "%s", name);
12474           else
12475             {
12476               /* Just print the first byte as a .byte instruction.  */
12477               (*info->fprintf_func) (info->stream, ".byte 0x%x",
12478                                      (unsigned int) priv.the_buffer[0]);
12479             }
12480
12481           return 1;
12482         }
12483
12484       return -1;
12485     }
12486
12487   obufp = obuf;
12488   sizeflag = priv.orig_sizeflag;
12489
12490   if (!ckprefix () || rex_used)
12491     {
12492       /* Too many prefixes or unused REX prefixes.  */
12493       for (i = 0;
12494            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
12495            i++)
12496         (*info->fprintf_func) (info->stream, "%s%s",
12497                                i == 0 ? "" : " ",
12498                                prefix_name (all_prefixes[i], sizeflag));
12499       return i;
12500     }
12501
12502   insn_codep = codep;
12503
12504   FETCH_DATA (info, codep + 1);
12505   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
12506
12507   if (((prefixes & PREFIX_FWAIT)
12508        && ((*codep < 0xd8) || (*codep > 0xdf))))
12509     {
12510       (*info->fprintf_func) (info->stream, "fwait");
12511       return 1;
12512     }
12513
12514   if (*codep == 0x0f)
12515     {
12516       unsigned char threebyte;
12517       FETCH_DATA (info, codep + 2);
12518       threebyte = *++codep;
12519       dp = &dis386_twobyte[threebyte];
12520       need_modrm = twobyte_has_modrm[*codep];
12521       codep++;
12522     }
12523   else
12524     {
12525       dp = &dis386[*codep];
12526       need_modrm = onebyte_has_modrm[*codep];
12527       codep++;
12528     }
12529
12530   if ((prefixes & PREFIX_REPZ))
12531     used_prefixes |= PREFIX_REPZ;
12532   if ((prefixes & PREFIX_REPNZ))
12533     used_prefixes |= PREFIX_REPNZ;
12534   if ((prefixes & PREFIX_LOCK))
12535     used_prefixes |= PREFIX_LOCK;
12536
12537   default_prefixes = 0;
12538   if (prefixes & PREFIX_ADDR)
12539     {
12540       sizeflag ^= AFLAG;
12541       if (dp->op[2].bytemode != loop_jcxz_mode || intel_syntax)
12542         {
12543           if ((sizeflag & AFLAG) || address_mode == mode_64bit)
12544             all_prefixes[last_addr_prefix] = ADDR32_PREFIX;
12545           else
12546             all_prefixes[last_addr_prefix] = ADDR16_PREFIX;
12547           default_prefixes |= PREFIX_ADDR;
12548         }
12549     }
12550
12551   if ((prefixes & PREFIX_DATA))
12552     {
12553       sizeflag ^= DFLAG;
12554       if (dp->op[2].bytemode == cond_jump_mode
12555           && dp->op[0].bytemode == v_mode
12556           && !intel_syntax)
12557         {
12558           if (sizeflag & DFLAG)
12559             all_prefixes[last_data_prefix] = DATA32_PREFIX;
12560           else
12561             all_prefixes[last_data_prefix] = DATA16_PREFIX;
12562           default_prefixes |= PREFIX_DATA;
12563         }
12564       else if (rex & REX_W)
12565         {
12566           /* REX_W will override PREFIX_DATA.  */
12567           default_prefixes |= PREFIX_DATA;
12568         }
12569     }
12570
12571   if (need_modrm)
12572     {
12573       FETCH_DATA (info, codep + 1);
12574       modrm.mod = (*codep >> 6) & 3;
12575       modrm.reg = (*codep >> 3) & 7;
12576       modrm.rm = *codep & 7;
12577     }
12578
12579   need_vex = 0;
12580   need_vex_reg = 0;
12581   vex_w_done = 0;
12582   vex.evex = 0;
12583
12584   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
12585     {
12586       get_sib (info, sizeflag);
12587       dofloat (sizeflag);
12588     }
12589   else
12590     {
12591       dp = get_valid_dis386 (dp, info);
12592       if (dp != NULL && putop (dp->name, sizeflag) == 0)
12593         {
12594           get_sib (info, sizeflag);
12595           for (i = 0; i < MAX_OPERANDS; ++i)
12596             {
12597               obufp = op_out[i];
12598               op_ad = MAX_OPERANDS - 1 - i;
12599               if (dp->op[i].rtn)
12600                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
12601               /* For EVEX instruction after the last operand masking
12602                  should be printed.  */
12603               if (i == 0 && vex.evex)
12604                 {
12605                   /* Don't print {%k0}.  */
12606                   if (vex.mask_register_specifier)
12607                     {
12608                       oappend ("{");
12609                       oappend (names_mask[vex.mask_register_specifier]);
12610                       oappend ("}");
12611                     }
12612                   if (vex.zeroing)
12613                     oappend ("{z}");
12614                 }
12615             }
12616         }
12617     }
12618
12619   /* See if any prefixes were not used.  If so, print the first one
12620      separately.  If we don't do this, we'll wind up printing an
12621      instruction stream which does not precisely correspond to the
12622      bytes we are disassembling.  */
12623   if ((prefixes & ~(used_prefixes | default_prefixes)) != 0)
12624     {
12625       for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12626         if (all_prefixes[i])
12627           {
12628             const char *name;
12629             name = prefix_name (all_prefixes[i], priv.orig_sizeflag);
12630             if (name == NULL)
12631               name = INTERNAL_DISASSEMBLER_ERROR;
12632             (*info->fprintf_func) (info->stream, "%s", name);
12633             return 1;
12634           }
12635     }
12636
12637   /* Check if the REX prefix is used.  */
12638   if (rex_ignored == 0 && (rex ^ rex_used) == 0)
12639     all_prefixes[last_rex_prefix] = 0;
12640
12641   /* Check if the SEG prefix is used.  */
12642   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
12643                    | PREFIX_FS | PREFIX_GS)) != 0
12644       && (used_prefixes
12645           & seg_prefix (all_prefixes[last_seg_prefix])) != 0)
12646     all_prefixes[last_seg_prefix] = 0;
12647
12648   /* Check if the ADDR prefix is used.  */
12649   if ((prefixes & PREFIX_ADDR) != 0
12650       && (used_prefixes & PREFIX_ADDR) != 0)
12651     all_prefixes[last_addr_prefix] = 0;
12652
12653   /* Check if the DATA prefix is used.  */
12654   if ((prefixes & PREFIX_DATA) != 0
12655       && (used_prefixes & PREFIX_DATA) != 0)
12656     all_prefixes[last_data_prefix] = 0;
12657
12658   prefix_length = 0;
12659   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12660     if (all_prefixes[i])
12661       {
12662         const char *name;
12663         name = prefix_name (all_prefixes[i], sizeflag);
12664         if (name == NULL)
12665           abort ();
12666         prefix_length += strlen (name) + 1;
12667         (*info->fprintf_func) (info->stream, "%s ", name);
12668       }
12669
12670   /* Check maximum code length.  */
12671   if ((codep - start_codep) > MAX_CODE_LENGTH)
12672     {
12673       (*info->fprintf_func) (info->stream, "(bad)");
12674       return MAX_CODE_LENGTH;
12675     }
12676
12677   obufp = mnemonicendp;
12678   for (i = strlen (obuf) + prefix_length; i < 6; i++)
12679     oappend (" ");
12680   oappend (" ");
12681   (*info->fprintf_func) (info->stream, "%s", obuf);
12682
12683   /* The enter and bound instructions are printed with operands in the same
12684      order as the intel book; everything else is printed in reverse order.  */
12685   if (intel_syntax || two_source_ops)
12686     {
12687       bfd_vma riprel;
12688
12689       for (i = 0; i < MAX_OPERANDS; ++i)
12690         op_txt[i] = op_out[i];
12691
12692       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
12693         {
12694           op_ad = op_index[i];
12695           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
12696           op_index[MAX_OPERANDS - 1 - i] = op_ad;
12697           riprel = op_riprel[i];
12698           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
12699           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
12700         }
12701     }
12702   else
12703     {
12704       for (i = 0; i < MAX_OPERANDS; ++i)
12705         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
12706     }
12707
12708   needcomma = 0;
12709   for (i = 0; i < MAX_OPERANDS; ++i)
12710     if (*op_txt[i])
12711       {
12712         if (needcomma)
12713           (*info->fprintf_func) (info->stream, ",");
12714         if (op_index[i] != -1 && !op_riprel[i])
12715           (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
12716         else
12717           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
12718         needcomma = 1;
12719       }
12720
12721   for (i = 0; i < MAX_OPERANDS; i++)
12722     if (op_index[i] != -1 && op_riprel[i])
12723       {
12724         (*info->fprintf_func) (info->stream, "        # ");
12725         (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep
12726                                                 + op_address[op_index[i]]), info);
12727         break;
12728       }
12729   return codep - priv.the_buffer;
12730 }
12731
12732 static const char *float_mem[] = {
12733   /* d8 */
12734   "fadd{s|}",
12735   "fmul{s|}",
12736   "fcom{s|}",
12737   "fcomp{s|}",
12738   "fsub{s|}",
12739   "fsubr{s|}",
12740   "fdiv{s|}",
12741   "fdivr{s|}",
12742   /* d9 */
12743   "fld{s|}",
12744   "(bad)",
12745   "fst{s|}",
12746   "fstp{s|}",
12747   "fldenvIC",
12748   "fldcw",
12749   "fNstenvIC",
12750   "fNstcw",
12751   /* da */
12752   "fiadd{l|}",
12753   "fimul{l|}",
12754   "ficom{l|}",
12755   "ficomp{l|}",
12756   "fisub{l|}",
12757   "fisubr{l|}",
12758   "fidiv{l|}",
12759   "fidivr{l|}",
12760   /* db */
12761   "fild{l|}",
12762   "fisttp{l|}",
12763   "fist{l|}",
12764   "fistp{l|}",
12765   "(bad)",
12766   "fld{t||t|}",
12767   "(bad)",
12768   "fstp{t||t|}",
12769   /* dc */
12770   "fadd{l|}",
12771   "fmul{l|}",
12772   "fcom{l|}",
12773   "fcomp{l|}",
12774   "fsub{l|}",
12775   "fsubr{l|}",
12776   "fdiv{l|}",
12777   "fdivr{l|}",
12778   /* dd */
12779   "fld{l|}",
12780   "fisttp{ll|}",
12781   "fst{l||}",
12782   "fstp{l|}",
12783   "frstorIC",
12784   "(bad)",
12785   "fNsaveIC",
12786   "fNstsw",
12787   /* de */
12788   "fiadd",
12789   "fimul",
12790   "ficom",
12791   "ficomp",
12792   "fisub",
12793   "fisubr",
12794   "fidiv",
12795   "fidivr",
12796   /* df */
12797   "fild",
12798   "fisttp",
12799   "fist",
12800   "fistp",
12801   "fbld",
12802   "fild{ll|}",
12803   "fbstp",
12804   "fistp{ll|}",
12805 };
12806
12807 static const unsigned char float_mem_mode[] = {
12808   /* d8 */
12809   d_mode,
12810   d_mode,
12811   d_mode,
12812   d_mode,
12813   d_mode,
12814   d_mode,
12815   d_mode,
12816   d_mode,
12817   /* d9 */
12818   d_mode,
12819   0,
12820   d_mode,
12821   d_mode,
12822   0,
12823   w_mode,
12824   0,
12825   w_mode,
12826   /* da */
12827   d_mode,
12828   d_mode,
12829   d_mode,
12830   d_mode,
12831   d_mode,
12832   d_mode,
12833   d_mode,
12834   d_mode,
12835   /* db */
12836   d_mode,
12837   d_mode,
12838   d_mode,
12839   d_mode,
12840   0,
12841   t_mode,
12842   0,
12843   t_mode,
12844   /* dc */
12845   q_mode,
12846   q_mode,
12847   q_mode,
12848   q_mode,
12849   q_mode,
12850   q_mode,
12851   q_mode,
12852   q_mode,
12853   /* dd */
12854   q_mode,
12855   q_mode,
12856   q_mode,
12857   q_mode,
12858   0,
12859   0,
12860   0,
12861   w_mode,
12862   /* de */
12863   w_mode,
12864   w_mode,
12865   w_mode,
12866   w_mode,
12867   w_mode,
12868   w_mode,
12869   w_mode,
12870   w_mode,
12871   /* df */
12872   w_mode,
12873   w_mode,
12874   w_mode,
12875   w_mode,
12876   t_mode,
12877   q_mode,
12878   t_mode,
12879   q_mode
12880 };
12881
12882 #define ST { OP_ST, 0 }
12883 #define STi { OP_STi, 0 }
12884
12885 #define FGRPd9_2 NULL, { { NULL, 0 } }
12886 #define FGRPd9_4 NULL, { { NULL, 1 } }
12887 #define FGRPd9_5 NULL, { { NULL, 2 } }
12888 #define FGRPd9_6 NULL, { { NULL, 3 } }
12889 #define FGRPd9_7 NULL, { { NULL, 4 } }
12890 #define FGRPda_5 NULL, { { NULL, 5 } }
12891 #define FGRPdb_4 NULL, { { NULL, 6 } }
12892 #define FGRPde_3 NULL, { { NULL, 7 } }
12893 #define FGRPdf_4 NULL, { { NULL, 8 } }
12894
12895 static const struct dis386 float_reg[][8] = {
12896   /* d8 */
12897   {
12898     { "fadd",   { ST, STi } },
12899     { "fmul",   { ST, STi } },
12900     { "fcom",   { STi } },
12901     { "fcomp",  { STi } },
12902     { "fsub",   { ST, STi } },
12903     { "fsubr",  { ST, STi } },
12904     { "fdiv",   { ST, STi } },
12905     { "fdivr",  { ST, STi } },
12906   },
12907   /* d9 */
12908   {
12909     { "fld",    { STi } },
12910     { "fxch",   { STi } },
12911     { FGRPd9_2 },
12912     { Bad_Opcode },
12913     { FGRPd9_4 },
12914     { FGRPd9_5 },
12915     { FGRPd9_6 },
12916     { FGRPd9_7 },
12917   },
12918   /* da */
12919   {
12920     { "fcmovb", { ST, STi } },
12921     { "fcmove", { ST, STi } },
12922     { "fcmovbe",{ ST, STi } },
12923     { "fcmovu", { ST, STi } },
12924     { Bad_Opcode },
12925     { FGRPda_5 },
12926     { Bad_Opcode },
12927     { Bad_Opcode },
12928   },
12929   /* db */
12930   {
12931     { "fcmovnb",{ ST, STi } },
12932     { "fcmovne",{ ST, STi } },
12933     { "fcmovnbe",{ ST, STi } },
12934     { "fcmovnu",{ ST, STi } },
12935     { FGRPdb_4 },
12936     { "fucomi", { ST, STi } },
12937     { "fcomi",  { ST, STi } },
12938     { Bad_Opcode },
12939   },
12940   /* dc */
12941   {
12942     { "fadd",   { STi, ST } },
12943     { "fmul",   { STi, ST } },
12944     { Bad_Opcode },
12945     { Bad_Opcode },
12946     { "fsub!M", { STi, ST } },
12947     { "fsubM",  { STi, ST } },
12948     { "fdiv!M", { STi, ST } },
12949     { "fdivM",  { STi, ST } },
12950   },
12951   /* dd */
12952   {
12953     { "ffree",  { STi } },
12954     { Bad_Opcode },
12955     { "fst",    { STi } },
12956     { "fstp",   { STi } },
12957     { "fucom",  { STi } },
12958     { "fucomp", { STi } },
12959     { Bad_Opcode },
12960     { Bad_Opcode },
12961   },
12962   /* de */
12963   {
12964     { "faddp",  { STi, ST } },
12965     { "fmulp",  { STi, ST } },
12966     { Bad_Opcode },
12967     { FGRPde_3 },
12968     { "fsub!Mp", { STi, ST } },
12969     { "fsubMp", { STi, ST } },
12970     { "fdiv!Mp", { STi, ST } },
12971     { "fdivMp", { STi, ST } },
12972   },
12973   /* df */
12974   {
12975     { "ffreep", { STi } },
12976     { Bad_Opcode },
12977     { Bad_Opcode },
12978     { Bad_Opcode },
12979     { FGRPdf_4 },
12980     { "fucomip", { ST, STi } },
12981     { "fcomip", { ST, STi } },
12982     { Bad_Opcode },
12983   },
12984 };
12985
12986 static char *fgrps[][8] = {
12987   /* d9_2  0 */
12988   {
12989     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12990   },
12991
12992   /* d9_4  1 */
12993   {
12994     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
12995   },
12996
12997   /* d9_5  2 */
12998   {
12999     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
13000   },
13001
13002   /* d9_6  3 */
13003   {
13004     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
13005   },
13006
13007   /* d9_7  4 */
13008   {
13009     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
13010   },
13011
13012   /* da_5  5 */
13013   {
13014     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13015   },
13016
13017   /* db_4  6 */
13018   {
13019     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
13020     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
13021   },
13022
13023   /* de_3  7 */
13024   {
13025     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13026   },
13027
13028   /* df_4  8 */
13029   {
13030     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13031   },
13032 };
13033
13034 static void
13035 swap_operand (void)
13036 {
13037   mnemonicendp[0] = '.';
13038   mnemonicendp[1] = 's';
13039   mnemonicendp += 2;
13040 }
13041
13042 static void
13043 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
13044                int sizeflag ATTRIBUTE_UNUSED)
13045 {
13046   /* Skip mod/rm byte.  */
13047   MODRM_CHECK;
13048   codep++;
13049 }
13050
13051 static void
13052 dofloat (int sizeflag)
13053 {
13054   const struct dis386 *dp;
13055   unsigned char floatop;
13056
13057   floatop = codep[-1];
13058
13059   if (modrm.mod != 3)
13060     {
13061       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
13062
13063       putop (float_mem[fp_indx], sizeflag);
13064       obufp = op_out[0];
13065       op_ad = 2;
13066       OP_E (float_mem_mode[fp_indx], sizeflag);
13067       return;
13068     }
13069   /* Skip mod/rm byte.  */
13070   MODRM_CHECK;
13071   codep++;
13072
13073   dp = &float_reg[floatop - 0xd8][modrm.reg];
13074   if (dp->name == NULL)
13075     {
13076       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
13077
13078       /* Instruction fnstsw is only one with strange arg.  */
13079       if (floatop == 0xdf && codep[-1] == 0xe0)
13080         strcpy (op_out[0], names16[0]);
13081     }
13082   else
13083     {
13084       putop (dp->name, sizeflag);
13085
13086       obufp = op_out[0];
13087       op_ad = 2;
13088       if (dp->op[0].rtn)
13089         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
13090
13091       obufp = op_out[1];
13092       op_ad = 1;
13093       if (dp->op[1].rtn)
13094         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
13095     }
13096 }
13097
13098 static void
13099 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13100 {
13101   oappend ("%st" + intel_syntax);
13102 }
13103
13104 static void
13105 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13106 {
13107   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
13108   oappend (scratchbuf + intel_syntax);
13109 }
13110
13111 /* Capital letters in template are macros.  */
13112 static int
13113 putop (const char *in_template, int sizeflag)
13114 {
13115   const char *p;
13116   int alt = 0;
13117   int cond = 1;
13118   unsigned int l = 0, len = 1;
13119   char last[4];
13120
13121 #define SAVE_LAST(c)                    \
13122   if (l < len && l < sizeof (last))     \
13123     last[l++] = c;                      \
13124   else                                  \
13125     abort ();
13126
13127   for (p = in_template; *p; p++)
13128     {
13129       switch (*p)
13130         {
13131         default:
13132           *obufp++ = *p;
13133           break;
13134         case '%':
13135           len++;
13136           break;
13137         case '!':
13138           cond = 0;
13139           break;
13140         case '{':
13141           alt = 0;
13142           if (intel_syntax)
13143             {
13144               while (*++p != '|')
13145                 if (*p == '}' || *p == '\0')
13146                   abort ();
13147             }
13148           /* Fall through.  */
13149         case 'I':
13150           alt = 1;
13151           continue;
13152         case '|':
13153           while (*++p != '}')
13154             {
13155               if (*p == '\0')
13156                 abort ();
13157             }
13158           break;
13159         case '}':
13160           break;
13161         case 'A':
13162           if (intel_syntax)
13163             break;
13164           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13165             *obufp++ = 'b';
13166           break;
13167         case 'B':
13168           if (l == 0 && len == 1)
13169             {
13170 case_B:
13171               if (intel_syntax)
13172                 break;
13173               if (sizeflag & SUFFIX_ALWAYS)
13174                 *obufp++ = 'b';
13175             }
13176           else
13177             {
13178               if (l != 1
13179                   || len != 2
13180                   || last[0] != 'L')
13181                 {
13182                   SAVE_LAST (*p);
13183                   break;
13184                 }
13185
13186               if (address_mode == mode_64bit
13187                   && !(prefixes & PREFIX_ADDR))
13188                 {
13189                   *obufp++ = 'a';
13190                   *obufp++ = 'b';
13191                   *obufp++ = 's';
13192                 }
13193
13194               goto case_B;
13195             }
13196           break;
13197         case 'C':
13198           if (intel_syntax && !alt)
13199             break;
13200           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
13201             {
13202               if (sizeflag & DFLAG)
13203                 *obufp++ = intel_syntax ? 'd' : 'l';
13204               else
13205                 *obufp++ = intel_syntax ? 'w' : 's';
13206               used_prefixes |= (prefixes & PREFIX_DATA);
13207             }
13208           break;
13209         case 'D':
13210           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
13211             break;
13212           USED_REX (REX_W);
13213           if (modrm.mod == 3)
13214             {
13215               if (rex & REX_W)
13216                 *obufp++ = 'q';
13217               else
13218                 {
13219                   if (sizeflag & DFLAG)
13220                     *obufp++ = intel_syntax ? 'd' : 'l';
13221                   else
13222                     *obufp++ = 'w';
13223                   used_prefixes |= (prefixes & PREFIX_DATA);
13224                 }
13225             }
13226           else
13227             *obufp++ = 'w';
13228           break;
13229         case 'E':               /* For jcxz/jecxz */
13230           if (address_mode == mode_64bit)
13231             {
13232               if (sizeflag & AFLAG)
13233                 *obufp++ = 'r';
13234               else
13235                 *obufp++ = 'e';
13236             }
13237           else
13238             if (sizeflag & AFLAG)
13239               *obufp++ = 'e';
13240           used_prefixes |= (prefixes & PREFIX_ADDR);
13241           break;
13242         case 'F':
13243           if (intel_syntax)
13244             break;
13245           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
13246             {
13247               if (sizeflag & AFLAG)
13248                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
13249               else
13250                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
13251               used_prefixes |= (prefixes & PREFIX_ADDR);
13252             }
13253           break;
13254         case 'G':
13255           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
13256             break;
13257           if ((rex & REX_W) || (sizeflag & DFLAG))
13258             *obufp++ = 'l';
13259           else
13260             *obufp++ = 'w';
13261           if (!(rex & REX_W))
13262             used_prefixes |= (prefixes & PREFIX_DATA);
13263           break;
13264         case 'H':
13265           if (intel_syntax)
13266             break;
13267           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
13268               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
13269             {
13270               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
13271               *obufp++ = ',';
13272               *obufp++ = 'p';
13273               if (prefixes & PREFIX_DS)
13274                 *obufp++ = 't';
13275               else
13276                 *obufp++ = 'n';
13277             }
13278           break;
13279         case 'J':
13280           if (intel_syntax)
13281             break;
13282           *obufp++ = 'l';
13283           break;
13284         case 'K':
13285           USED_REX (REX_W);
13286           if (rex & REX_W)
13287             *obufp++ = 'q';
13288           else
13289             *obufp++ = 'd';
13290           break;
13291         case 'Z':
13292           if (intel_syntax)
13293             break;
13294           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
13295             {
13296               *obufp++ = 'q';
13297               break;
13298             }
13299           /* Fall through.  */
13300           goto case_L;
13301         case 'L':
13302           if (l != 0 || len != 1)
13303             {
13304               SAVE_LAST (*p);
13305               break;
13306             }
13307 case_L:
13308           if (intel_syntax)
13309             break;
13310           if (sizeflag & SUFFIX_ALWAYS)
13311             *obufp++ = 'l';
13312           break;
13313         case 'M':
13314           if (intel_mnemonic != cond)
13315             *obufp++ = 'r';
13316           break;
13317         case 'N':
13318           if ((prefixes & PREFIX_FWAIT) == 0)
13319             *obufp++ = 'n';
13320           else
13321             used_prefixes |= PREFIX_FWAIT;
13322           break;
13323         case 'O':
13324           USED_REX (REX_W);
13325           if (rex & REX_W)
13326             *obufp++ = 'o';
13327           else if (intel_syntax && (sizeflag & DFLAG))
13328             *obufp++ = 'q';
13329           else
13330             *obufp++ = 'd';
13331           if (!(rex & REX_W))
13332             used_prefixes |= (prefixes & PREFIX_DATA);
13333           break;
13334         case 'T':
13335           if (!intel_syntax
13336               && address_mode == mode_64bit
13337               && ((sizeflag & DFLAG) || (rex & REX_W)))
13338             {
13339               *obufp++ = 'q';
13340               break;
13341             }
13342           /* Fall through.  */
13343         case 'P':
13344           if (intel_syntax)
13345             {
13346               if ((rex & REX_W) == 0
13347                   && (prefixes & PREFIX_DATA))
13348                 {
13349                   if ((sizeflag & DFLAG) == 0)
13350                     *obufp++ = 'w';
13351                    used_prefixes |= (prefixes & PREFIX_DATA);
13352                 }
13353               break;
13354             }
13355           if ((prefixes & PREFIX_DATA)
13356               || (rex & REX_W)
13357               || (sizeflag & SUFFIX_ALWAYS))
13358             {
13359               USED_REX (REX_W);
13360               if (rex & REX_W)
13361                 *obufp++ = 'q';
13362               else
13363                 {
13364                    if (sizeflag & DFLAG)
13365                       *obufp++ = 'l';
13366                    else
13367                      *obufp++ = 'w';
13368                    used_prefixes |= (prefixes & PREFIX_DATA);
13369                 }
13370             }
13371           break;
13372         case 'U':
13373           if (intel_syntax)
13374             break;
13375           if (address_mode == mode_64bit
13376               && ((sizeflag & DFLAG) || (rex & REX_W)))
13377             {
13378               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13379                 *obufp++ = 'q';
13380               break;
13381             }
13382           /* Fall through.  */
13383           goto case_Q;
13384         case 'Q':
13385           if (l == 0 && len == 1)
13386             {
13387 case_Q:
13388               if (intel_syntax && !alt)
13389                 break;
13390               USED_REX (REX_W);
13391               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13392                 {
13393                   if (rex & REX_W)
13394                     *obufp++ = 'q';
13395                   else
13396                     {
13397                       if (sizeflag & DFLAG)
13398                         *obufp++ = intel_syntax ? 'd' : 'l';
13399                       else
13400                         *obufp++ = 'w';
13401                       used_prefixes |= (prefixes & PREFIX_DATA);
13402                     }
13403                 }
13404             }
13405           else
13406             {
13407               if (l != 1 || len != 2 || last[0] != 'L')
13408                 {
13409                   SAVE_LAST (*p);
13410                   break;
13411                 }
13412               if (intel_syntax
13413                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
13414                 break;
13415               if ((rex & REX_W))
13416                 {
13417                   USED_REX (REX_W);
13418                   *obufp++ = 'q';
13419                 }
13420               else
13421                 *obufp++ = 'l';
13422             }
13423           break;
13424         case 'R':
13425           USED_REX (REX_W);
13426           if (rex & REX_W)
13427             *obufp++ = 'q';
13428           else if (sizeflag & DFLAG)
13429             {
13430               if (intel_syntax)
13431                   *obufp++ = 'd';
13432               else
13433                   *obufp++ = 'l';
13434             }
13435           else
13436             *obufp++ = 'w';
13437           if (intel_syntax && !p[1]
13438               && ((rex & REX_W) || (sizeflag & DFLAG)))
13439             *obufp++ = 'e';
13440           if (!(rex & REX_W))
13441             used_prefixes |= (prefixes & PREFIX_DATA);
13442           break;
13443         case 'V':
13444           if (l == 0 && len == 1)
13445             {
13446               if (intel_syntax)
13447                 break;
13448               if (address_mode == mode_64bit
13449                   && ((sizeflag & DFLAG) || (rex & REX_W)))
13450                 {
13451                   if (sizeflag & SUFFIX_ALWAYS)
13452                     *obufp++ = 'q';
13453                   break;
13454                 }
13455             }
13456           else
13457             {
13458               if (l != 1
13459                   || len != 2
13460                   || last[0] != 'L')
13461                 {
13462                   SAVE_LAST (*p);
13463                   break;
13464                 }
13465
13466               if (rex & REX_W)
13467                 {
13468                   *obufp++ = 'a';
13469                   *obufp++ = 'b';
13470                   *obufp++ = 's';
13471                 }
13472             }
13473           /* Fall through.  */
13474           goto case_S;
13475         case 'S':
13476           if (l == 0 && len == 1)
13477             {
13478 case_S:
13479               if (intel_syntax)
13480                 break;
13481               if (sizeflag & SUFFIX_ALWAYS)
13482                 {
13483                   if (rex & REX_W)
13484                     *obufp++ = 'q';
13485                   else
13486                     {
13487                       if (sizeflag & DFLAG)
13488                         *obufp++ = 'l';
13489                       else
13490                         *obufp++ = 'w';
13491                       used_prefixes |= (prefixes & PREFIX_DATA);
13492                     }
13493                 }
13494             }
13495           else
13496             {
13497               if (l != 1
13498                   || len != 2
13499                   || last[0] != 'L')
13500                 {
13501                   SAVE_LAST (*p);
13502                   break;
13503                 }
13504
13505               if (address_mode == mode_64bit
13506                   && !(prefixes & PREFIX_ADDR))
13507                 {
13508                   *obufp++ = 'a';
13509                   *obufp++ = 'b';
13510                   *obufp++ = 's';
13511                 }
13512
13513               goto case_S;
13514             }
13515           break;
13516         case 'X':
13517           if (l != 0 || len != 1)
13518             {
13519               SAVE_LAST (*p);
13520               break;
13521             }
13522           if (need_vex && vex.prefix)
13523             {
13524               if (vex.prefix == DATA_PREFIX_OPCODE)
13525                 *obufp++ = 'd';
13526               else
13527                 *obufp++ = 's';
13528             }
13529           else
13530             {
13531               if (prefixes & PREFIX_DATA)
13532                 *obufp++ = 'd';
13533               else
13534                 *obufp++ = 's';
13535               used_prefixes |= (prefixes & PREFIX_DATA);
13536             }
13537           break;
13538         case 'Y':
13539           if (l == 0 && len == 1)
13540             {
13541               if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
13542                 break;
13543               if (rex & REX_W)
13544                 {
13545                   USED_REX (REX_W);
13546                   *obufp++ = 'q';
13547                 }
13548               break;
13549             }
13550           else
13551             {
13552               if (l != 1 || len != 2 || last[0] != 'X')
13553                 {
13554                   SAVE_LAST (*p);
13555                   break;
13556                 }
13557               if (!need_vex)
13558                 abort ();
13559               if (intel_syntax
13560                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
13561                 break;
13562               switch (vex.length)
13563                 {
13564                 case 128:
13565                   *obufp++ = 'x';
13566                   break;
13567                 case 256:
13568                   *obufp++ = 'y';
13569                   break;
13570                 default:
13571                   abort ();
13572                 }
13573             }
13574           break;
13575         case 'W':
13576           if (l == 0 && len == 1)
13577             {
13578               /* operand size flag for cwtl, cbtw */
13579               USED_REX (REX_W);
13580               if (rex & REX_W)
13581                 {
13582                   if (intel_syntax)
13583                     *obufp++ = 'd';
13584                   else
13585                     *obufp++ = 'l';
13586                 }
13587               else if (sizeflag & DFLAG)
13588                 *obufp++ = 'w';
13589               else
13590                 *obufp++ = 'b';
13591               if (!(rex & REX_W))
13592                 used_prefixes |= (prefixes & PREFIX_DATA);
13593             }
13594           else
13595             {
13596               if (l != 1
13597                   || len != 2
13598                   || (last[0] != 'X'
13599                       && last[0] != 'L'))
13600                 {
13601                   SAVE_LAST (*p);
13602                   break;
13603                 }
13604               if (!need_vex)
13605                 abort ();
13606               if (last[0] == 'X')
13607                 *obufp++ = vex.w ? 'd': 's';
13608               else
13609                 *obufp++ = vex.w ? 'q': 'd';
13610             }
13611           break;
13612         }
13613       alt = 0;
13614     }
13615   *obufp = 0;
13616   mnemonicendp = obufp;
13617   return 0;
13618 }
13619
13620 static void
13621 oappend (const char *s)
13622 {
13623   obufp = stpcpy (obufp, s);
13624 }
13625
13626 static void
13627 append_seg (void)
13628 {
13629   if (prefixes & PREFIX_CS)
13630     {
13631       used_prefixes |= PREFIX_CS;
13632       oappend ("%cs:" + intel_syntax);
13633     }
13634   if (prefixes & PREFIX_DS)
13635     {
13636       used_prefixes |= PREFIX_DS;
13637       oappend ("%ds:" + intel_syntax);
13638     }
13639   if (prefixes & PREFIX_SS)
13640     {
13641       used_prefixes |= PREFIX_SS;
13642       oappend ("%ss:" + intel_syntax);
13643     }
13644   if (prefixes & PREFIX_ES)
13645     {
13646       used_prefixes |= PREFIX_ES;
13647       oappend ("%es:" + intel_syntax);
13648     }
13649   if (prefixes & PREFIX_FS)
13650     {
13651       used_prefixes |= PREFIX_FS;
13652       oappend ("%fs:" + intel_syntax);
13653     }
13654   if (prefixes & PREFIX_GS)
13655     {
13656       used_prefixes |= PREFIX_GS;
13657       oappend ("%gs:" + intel_syntax);
13658     }
13659 }
13660
13661 static void
13662 OP_indirE (int bytemode, int sizeflag)
13663 {
13664   if (!intel_syntax)
13665     oappend ("*");
13666   OP_E (bytemode, sizeflag);
13667 }
13668
13669 static void
13670 print_operand_value (char *buf, int hex, bfd_vma disp)
13671 {
13672   if (address_mode == mode_64bit)
13673     {
13674       if (hex)
13675         {
13676           char tmp[30];
13677           int i;
13678           buf[0] = '0';
13679           buf[1] = 'x';
13680           sprintf_vma (tmp, disp);
13681           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
13682           strcpy (buf + 2, tmp + i);
13683         }
13684       else
13685         {
13686           bfd_signed_vma v = disp;
13687           char tmp[30];
13688           int i;
13689           if (v < 0)
13690             {
13691               *(buf++) = '-';
13692               v = -disp;
13693               /* Check for possible overflow on 0x8000000000000000.  */
13694               if (v < 0)
13695                 {
13696                   strcpy (buf, "9223372036854775808");
13697                   return;
13698                 }
13699             }
13700           if (!v)
13701             {
13702               strcpy (buf, "0");
13703               return;
13704             }
13705
13706           i = 0;
13707           tmp[29] = 0;
13708           while (v)
13709             {
13710               tmp[28 - i] = (v % 10) + '0';
13711               v /= 10;
13712               i++;
13713             }
13714           strcpy (buf, tmp + 29 - i);
13715         }
13716     }
13717   else
13718     {
13719       if (hex)
13720         sprintf (buf, "0x%x", (unsigned int) disp);
13721       else
13722         sprintf (buf, "%d", (int) disp);
13723     }
13724 }
13725
13726 /* Put DISP in BUF as signed hex number.  */
13727
13728 static void
13729 print_displacement (char *buf, bfd_vma disp)
13730 {
13731   bfd_signed_vma val = disp;
13732   char tmp[30];
13733   int i, j = 0;
13734
13735   if (val < 0)
13736     {
13737       buf[j++] = '-';
13738       val = -disp;
13739
13740       /* Check for possible overflow.  */
13741       if (val < 0)
13742         {
13743           switch (address_mode)
13744             {
13745             case mode_64bit:
13746               strcpy (buf + j, "0x8000000000000000");
13747               break;
13748             case mode_32bit:
13749               strcpy (buf + j, "0x80000000");
13750               break;
13751             case mode_16bit:
13752               strcpy (buf + j, "0x8000");
13753               break;
13754             }
13755           return;
13756         }
13757     }
13758
13759   buf[j++] = '0';
13760   buf[j++] = 'x';
13761
13762   sprintf_vma (tmp, (bfd_vma) val);
13763   for (i = 0; tmp[i] == '0'; i++)
13764     continue;
13765   if (tmp[i] == '\0')
13766     i--;
13767   strcpy (buf + j, tmp + i);
13768 }
13769
13770 static void
13771 intel_operand_size (int bytemode, int sizeflag)
13772 {
13773   if (vex.evex
13774       && vex.b
13775       && (bytemode == x_mode
13776           || bytemode == evex_half_bcst_xmmq_mode))
13777     {
13778       if (vex.w)
13779         oappend ("QWORD PTR ");
13780       else
13781         oappend ("DWORD PTR ");
13782       return;
13783     }
13784   switch (bytemode)
13785     {
13786     case b_mode:
13787     case b_swap_mode:
13788     case dqb_mode:
13789       oappend ("BYTE PTR ");
13790       break;
13791     case w_mode:
13792     case dqw_mode:
13793       oappend ("WORD PTR ");
13794       break;
13795     case stack_v_mode:
13796       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
13797         {
13798           oappend ("QWORD PTR ");
13799           break;
13800         }
13801       /* FALLTHRU */
13802     case v_mode:
13803     case v_bnd_mode:
13804     case v_swap_mode:
13805     case dq_mode:
13806       USED_REX (REX_W);
13807       if (rex & REX_W)
13808         oappend ("QWORD PTR ");
13809       else
13810         {
13811           if ((sizeflag & DFLAG) || bytemode == dq_mode)
13812             oappend ("DWORD PTR ");
13813           else
13814             oappend ("WORD PTR ");
13815           used_prefixes |= (prefixes & PREFIX_DATA);
13816         }
13817       break;
13818     case z_mode:
13819       if ((rex & REX_W) || (sizeflag & DFLAG))
13820         *obufp++ = 'D';
13821       oappend ("WORD PTR ");
13822       if (!(rex & REX_W))
13823         used_prefixes |= (prefixes & PREFIX_DATA);
13824       break;
13825     case a_mode:
13826       if (sizeflag & DFLAG)
13827         oappend ("QWORD PTR ");
13828       else
13829         oappend ("DWORD PTR ");
13830       used_prefixes |= (prefixes & PREFIX_DATA);
13831       break;
13832     case d_mode:
13833     case d_scalar_mode:
13834     case d_scalar_swap_mode:
13835     case d_swap_mode:
13836     case dqd_mode:
13837       oappend ("DWORD PTR ");
13838       break;
13839     case q_mode:
13840     case q_scalar_mode:
13841     case q_scalar_swap_mode:
13842     case q_swap_mode:
13843       oappend ("QWORD PTR ");
13844       break;
13845     case m_mode:
13846       if (address_mode == mode_64bit)
13847         oappend ("QWORD PTR ");
13848       else
13849         oappend ("DWORD PTR ");
13850       break;
13851     case f_mode:
13852       if (sizeflag & DFLAG)
13853         oappend ("FWORD PTR ");
13854       else
13855         oappend ("DWORD PTR ");
13856       used_prefixes |= (prefixes & PREFIX_DATA);
13857       break;
13858     case t_mode:
13859       oappend ("TBYTE PTR ");
13860       break;
13861     case x_mode:
13862     case x_swap_mode:
13863     case evex_x_gscat_mode:
13864     case evex_x_nobcst_mode:
13865       if (need_vex)
13866         {
13867           switch (vex.length)
13868             {
13869             case 128:
13870               oappend ("XMMWORD PTR ");
13871               break;
13872             case 256:
13873               oappend ("YMMWORD PTR ");
13874               break;
13875             case 512:
13876               oappend ("ZMMWORD PTR ");
13877               break;
13878             default:
13879               abort ();
13880             }
13881         }
13882       else
13883         oappend ("XMMWORD PTR ");
13884       break;
13885     case xmm_mode:
13886       oappend ("XMMWORD PTR ");
13887       break;
13888     case ymm_mode:
13889       oappend ("YMMWORD PTR ");
13890       break;
13891     case xmmq_mode:
13892     case evex_half_bcst_xmmq_mode:
13893       if (!need_vex)
13894         abort ();
13895
13896       switch (vex.length)
13897         {
13898         case 128:
13899           oappend ("QWORD PTR ");
13900           break;
13901         case 256:
13902           oappend ("XMMWORD PTR ");
13903           break;
13904         case 512:
13905           oappend ("YMMWORD PTR ");
13906           break;
13907         default:
13908           abort ();
13909         }
13910       break;
13911     case xmm_mb_mode:
13912       if (!need_vex)
13913         abort ();
13914
13915       switch (vex.length)
13916         {
13917         case 128:
13918         case 256:
13919         case 512:
13920           oappend ("BYTE PTR ");
13921           break;
13922         default:
13923           abort ();
13924         }
13925       break;
13926     case xmm_mw_mode:
13927       if (!need_vex)
13928         abort ();
13929
13930       switch (vex.length)
13931         {
13932         case 128:
13933         case 256:
13934         case 512:
13935           oappend ("WORD PTR ");
13936           break;
13937         default:
13938           abort ();
13939         }
13940       break;
13941     case xmm_md_mode:
13942       if (!need_vex)
13943         abort ();
13944
13945       switch (vex.length)
13946         {
13947         case 128:
13948         case 256:
13949         case 512:
13950           oappend ("DWORD PTR ");
13951           break;
13952         default:
13953           abort ();
13954         }
13955       break;
13956     case xmm_mq_mode:
13957       if (!need_vex)
13958         abort ();
13959
13960       switch (vex.length)
13961         {
13962         case 128:
13963         case 256:
13964         case 512:
13965           oappend ("QWORD PTR ");
13966           break;
13967         default:
13968           abort ();
13969         }
13970       break;
13971     case xmmdw_mode:
13972       if (!need_vex)
13973         abort ();
13974
13975       switch (vex.length)
13976         {
13977         case 128:
13978           oappend ("WORD PTR ");
13979           break;
13980         case 256:
13981           oappend ("DWORD PTR ");
13982           break;
13983         case 512:
13984           oappend ("QWORD PTR ");
13985           break;
13986         default:
13987           abort ();
13988         }
13989       break;
13990     case xmmqd_mode:
13991       if (!need_vex)
13992         abort ();
13993
13994       switch (vex.length)
13995         {
13996         case 128:
13997           oappend ("DWORD PTR ");
13998           break;
13999         case 256:
14000           oappend ("QWORD PTR ");
14001           break;
14002         case 512:
14003           oappend ("XMMWORD PTR ");
14004           break;
14005         default:
14006           abort ();
14007         }
14008       break;
14009     case ymmq_mode:
14010       if (!need_vex)
14011         abort ();
14012
14013       switch (vex.length)
14014         {
14015         case 128:
14016           oappend ("QWORD PTR ");
14017           break;
14018         case 256:
14019           oappend ("YMMWORD PTR ");
14020           break;
14021         case 512:
14022           oappend ("ZMMWORD PTR ");
14023           break;
14024         default:
14025           abort ();
14026         }
14027       break;
14028     case ymmxmm_mode:
14029       if (!need_vex)
14030         abort ();
14031
14032       switch (vex.length)
14033         {
14034         case 128:
14035         case 256:
14036           oappend ("XMMWORD PTR ");
14037           break;
14038         default:
14039           abort ();
14040         }
14041       break;
14042     case o_mode:
14043       oappend ("OWORD PTR ");
14044       break;
14045     case xmm_mdq_mode:
14046     case vex_w_dq_mode:
14047     case vex_scalar_w_dq_mode:
14048       if (!need_vex)
14049         abort ();
14050
14051       if (vex.w)
14052         oappend ("QWORD PTR ");
14053       else
14054         oappend ("DWORD PTR ");
14055       break;
14056     case vex_vsib_d_w_dq_mode:
14057     case vex_vsib_q_w_dq_mode:
14058       if (!need_vex)
14059         abort ();
14060
14061       if (!vex.evex)
14062         {
14063           if (vex.w)
14064             oappend ("QWORD PTR ");
14065           else
14066             oappend ("DWORD PTR ");
14067         }
14068       else
14069         {
14070           if (vex.length != 512)
14071             abort ();
14072           oappend ("ZMMWORD PTR ");
14073         }
14074       break;
14075     case mask_mode:
14076       if (!need_vex)
14077         abort ();
14078       /* Currently the only instructions, which allows either mask or
14079          memory operand, are AVX512's KMOVW instructions.  They need
14080          Word-sized operand.  */
14081       if (vex.w || vex.length != 128)
14082         abort ();
14083       oappend ("WORD PTR ");
14084       break;
14085     default:
14086       break;
14087     }
14088 }
14089
14090 static void
14091 OP_E_register (int bytemode, int sizeflag)
14092 {
14093   int reg = modrm.rm;
14094   const char **names;
14095
14096   USED_REX (REX_B);
14097   if ((rex & REX_B))
14098     reg += 8;
14099
14100   if ((sizeflag & SUFFIX_ALWAYS)
14101       && (bytemode == b_swap_mode || bytemode == v_swap_mode))
14102     swap_operand ();
14103
14104   switch (bytemode)
14105     {
14106     case b_mode:
14107     case b_swap_mode:
14108       USED_REX (0);
14109       if (rex)
14110         names = names8rex;
14111       else
14112         names = names8;
14113       break;
14114     case w_mode:
14115       names = names16;
14116       break;
14117     case d_mode:
14118       names = names32;
14119       break;
14120     case q_mode:
14121       names = names64;
14122       break;
14123     case m_mode:
14124       names = address_mode == mode_64bit ? names64 : names32;
14125       break;
14126     case bnd_mode:
14127       names = names_bnd;
14128       break;
14129     case stack_v_mode:
14130       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14131         {
14132           names = names64;
14133           break;
14134         }
14135       bytemode = v_mode;
14136       /* FALLTHRU */
14137     case v_mode:
14138     case v_bnd_mode:
14139     case v_swap_mode:
14140     case dq_mode:
14141     case dqb_mode:
14142     case dqd_mode:
14143     case dqw_mode:
14144       USED_REX (REX_W);
14145       if (rex & REX_W)
14146         names = names64;
14147       else
14148         {
14149           if ((sizeflag & DFLAG)
14150               || (bytemode != v_mode
14151                   && bytemode != v_swap_mode))
14152             names = names32;
14153           else
14154             names = names16;
14155           used_prefixes |= (prefixes & PREFIX_DATA);
14156         }
14157       break;
14158     case mask_mode:
14159       names = names_mask;
14160       break;
14161     case 0:
14162       return;
14163     default:
14164       oappend (INTERNAL_DISASSEMBLER_ERROR);
14165       return;
14166     }
14167   oappend (names[reg]);
14168 }
14169
14170 static void
14171 OP_E_memory (int bytemode, int sizeflag)
14172 {
14173   bfd_vma disp = 0;
14174   int add = (rex & REX_B) ? 8 : 0;
14175   int riprel = 0;
14176   int shift;
14177
14178   if (vex.evex)
14179     {
14180       /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0.  */
14181       if (vex.b
14182           && bytemode != x_mode
14183           && bytemode != evex_half_bcst_xmmq_mode)
14184         {
14185           BadOp ();
14186           return;
14187         }
14188       switch (bytemode)
14189         {
14190         case vex_vsib_d_w_dq_mode:
14191         case evex_x_gscat_mode:
14192         case xmm_mdq_mode:
14193           shift = vex.w ? 3 : 2;
14194           break;
14195         case vex_vsib_q_w_dq_mode:
14196           shift = 3;
14197           break;
14198         case x_mode:
14199         case evex_half_bcst_xmmq_mode:
14200           if (vex.b)
14201             {
14202               shift = vex.w ? 3 : 2;
14203               break;
14204             }
14205           /* Fall through if vex.b == 0.  */
14206         case xmmqd_mode:
14207         case xmmdw_mode:
14208         case xmmq_mode:
14209         case ymmq_mode:
14210         case evex_x_nobcst_mode:
14211         case x_swap_mode:
14212           switch (vex.length)
14213             {
14214             case 128:
14215               shift = 4;
14216               break;
14217             case 256:
14218               shift = 5;
14219               break;
14220             case 512:
14221               shift = 6;
14222               break;
14223             default:
14224               abort ();
14225             }
14226           break;
14227         case ymm_mode:
14228           shift = 5;
14229           break;
14230         case xmm_mode:
14231           shift = 4;
14232           break;
14233         case xmm_mq_mode:
14234         case q_mode:
14235         case q_scalar_mode:
14236         case q_swap_mode:
14237         case q_scalar_swap_mode:
14238           shift = 3;
14239           break;
14240         case dqd_mode:
14241         case xmm_md_mode:
14242         case d_mode:
14243         case d_scalar_mode:
14244         case d_swap_mode:
14245         case d_scalar_swap_mode:
14246           shift = 2;
14247           break;
14248         case xmm_mw_mode:
14249           shift = 1;
14250           break;
14251         case xmm_mb_mode:
14252           shift = 0;
14253           break;
14254         default:
14255           abort ();
14256         }
14257       /* Make necessary corrections to shift for modes that need it.
14258          For these modes we currently have shift 4, 5 or 6 depending on
14259          vex.length (it corresponds to xmmword, ymmword or zmmword
14260          operand).  We might want to make it 3, 4 or 5 (e.g. for
14261          xmmq_mode).  In case of broadcast enabled the corrections
14262          aren't needed, as element size is always 32 or 64 bits.  */
14263       if (bytemode == xmmq_mode
14264           || (bytemode == evex_half_bcst_xmmq_mode
14265               && !vex.b))
14266         shift -= 1;
14267       else if (bytemode == xmmqd_mode)
14268         shift -= 2;
14269       else if (bytemode == xmmdw_mode)
14270         shift -= 3;
14271     }
14272   else
14273     shift = 0;
14274
14275   USED_REX (REX_B);
14276   if (intel_syntax)
14277     intel_operand_size (bytemode, sizeflag);
14278   append_seg ();
14279
14280   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14281     {
14282       /* 32/64 bit address mode */
14283       int havedisp;
14284       int havesib;
14285       int havebase;
14286       int haveindex;
14287       int needindex;
14288       int base, rbase;
14289       int vindex = 0;
14290       int scale = 0;
14291       int addr32flag = !((sizeflag & AFLAG)
14292                          || bytemode == v_bnd_mode
14293                          || bytemode == bnd_mode);
14294       const char **indexes64 = names64;
14295       const char **indexes32 = names32;
14296
14297       havesib = 0;
14298       havebase = 1;
14299       haveindex = 0;
14300       base = modrm.rm;
14301
14302       if (base == 4)
14303         {
14304           havesib = 1;
14305           vindex = sib.index;
14306           USED_REX (REX_X);
14307           if (rex & REX_X)
14308             vindex += 8;
14309           switch (bytemode)
14310             {
14311             case vex_vsib_d_w_dq_mode:
14312             case vex_vsib_q_w_dq_mode:
14313               if (!need_vex)
14314                 abort ();
14315               if (vex.evex)
14316                 {
14317                   if (!vex.v)
14318                     vindex += 16;
14319                 }
14320
14321               haveindex = 1;
14322               switch (vex.length)
14323                 {
14324                 case 128:
14325                   indexes64 = indexes32 = names_xmm;
14326                   break;
14327                 case 256:
14328                   if (!vex.w || bytemode == vex_vsib_q_w_dq_mode)
14329                     indexes64 = indexes32 = names_ymm;
14330                   else
14331                     indexes64 = indexes32 = names_xmm;
14332                   break;
14333                 case 512:
14334                   if (!vex.w || bytemode == vex_vsib_q_w_dq_mode)
14335                     indexes64 = indexes32 = names_zmm;
14336                   else
14337                     indexes64 = indexes32 = names_ymm;
14338                   break;
14339                 default:
14340                   abort ();
14341                 }
14342               break;
14343             default:
14344               haveindex = vindex != 4;
14345               break;
14346             }
14347           scale = sib.scale;
14348           base = sib.base;
14349           codep++;
14350         }
14351       rbase = base + add;
14352
14353       switch (modrm.mod)
14354         {
14355         case 0:
14356           if (base == 5)
14357             {
14358               havebase = 0;
14359               if (address_mode == mode_64bit && !havesib)
14360                 riprel = 1;
14361               disp = get32s ();
14362             }
14363           break;
14364         case 1:
14365           FETCH_DATA (the_info, codep + 1);
14366           disp = *codep++;
14367           if ((disp & 0x80) != 0)
14368             disp -= 0x100;
14369           if (vex.evex && shift > 0)
14370             disp <<= shift;
14371           break;
14372         case 2:
14373           disp = get32s ();
14374           break;
14375         }
14376
14377       /* In 32bit mode, we need index register to tell [offset] from
14378          [eiz*1 + offset].  */
14379       needindex = (havesib
14380                    && !havebase
14381                    && !haveindex
14382                    && address_mode == mode_32bit);
14383       havedisp = (havebase
14384                   || needindex
14385                   || (havesib && (haveindex || scale != 0)));
14386
14387       if (!intel_syntax)
14388         if (modrm.mod != 0 || base == 5)
14389           {
14390             if (havedisp || riprel)
14391               print_displacement (scratchbuf, disp);
14392             else
14393               print_operand_value (scratchbuf, 1, disp);
14394             oappend (scratchbuf);
14395             if (riprel)
14396               {
14397                 set_op (disp, 1);
14398                 oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)");
14399               }
14400           }
14401
14402       if ((havebase || haveindex || riprel)
14403           && (bytemode != v_bnd_mode)
14404           && (bytemode != bnd_mode))
14405         used_prefixes |= PREFIX_ADDR;
14406
14407       if (havedisp || (intel_syntax && riprel))
14408         {
14409           *obufp++ = open_char;
14410           if (intel_syntax && riprel)
14411             {
14412               set_op (disp, 1);
14413               oappend (sizeflag & AFLAG ? "rip" : "eip");
14414             }
14415           *obufp = '\0';
14416           if (havebase)
14417             oappend (address_mode == mode_64bit && !addr32flag
14418                      ? names64[rbase] : names32[rbase]);
14419           if (havesib)
14420             {
14421               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
14422                  print index to tell base + index from base.  */
14423               if (scale != 0
14424                   || needindex
14425                   || haveindex
14426                   || (havebase && base != ESP_REG_NUM))
14427                 {
14428                   if (!intel_syntax || havebase)
14429                     {
14430                       *obufp++ = separator_char;
14431                       *obufp = '\0';
14432                     }
14433                   if (haveindex)
14434                     oappend (address_mode == mode_64bit && !addr32flag
14435                              ? indexes64[vindex] : indexes32[vindex]);
14436                   else
14437                     oappend (address_mode == mode_64bit && !addr32flag
14438                              ? index64 : index32);
14439
14440                   *obufp++ = scale_char;
14441                   *obufp = '\0';
14442                   sprintf (scratchbuf, "%d", 1 << scale);
14443                   oappend (scratchbuf);
14444                 }
14445             }
14446           if (intel_syntax
14447               && (disp || modrm.mod != 0 || base == 5))
14448             {
14449               if (!havedisp || (bfd_signed_vma) disp >= 0)
14450                 {
14451                   *obufp++ = '+';
14452                   *obufp = '\0';
14453                 }
14454               else if (modrm.mod != 1 && disp != -disp)
14455                 {
14456                   *obufp++ = '-';
14457                   *obufp = '\0';
14458                   disp = - (bfd_signed_vma) disp;
14459                 }
14460
14461               if (havedisp)
14462                 print_displacement (scratchbuf, disp);
14463               else
14464                 print_operand_value (scratchbuf, 1, disp);
14465               oappend (scratchbuf);
14466             }
14467
14468           *obufp++ = close_char;
14469           *obufp = '\0';
14470         }
14471       else if (intel_syntax)
14472         {
14473           if (modrm.mod != 0 || base == 5)
14474             {
14475               if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
14476                               | PREFIX_ES | PREFIX_FS | PREFIX_GS))
14477                 ;
14478               else
14479                 {
14480                   oappend (names_seg[ds_reg - es_reg]);
14481                   oappend (":");
14482                 }
14483               print_operand_value (scratchbuf, 1, disp);
14484               oappend (scratchbuf);
14485             }
14486         }
14487     }
14488   else
14489     {
14490       /* 16 bit address mode */
14491       used_prefixes |= prefixes & PREFIX_ADDR;
14492       switch (modrm.mod)
14493         {
14494         case 0:
14495           if (modrm.rm == 6)
14496             {
14497               disp = get16 ();
14498               if ((disp & 0x8000) != 0)
14499                 disp -= 0x10000;
14500             }
14501           break;
14502         case 1:
14503           FETCH_DATA (the_info, codep + 1);
14504           disp = *codep++;
14505           if ((disp & 0x80) != 0)
14506             disp -= 0x100;
14507           break;
14508         case 2:
14509           disp = get16 ();
14510           if ((disp & 0x8000) != 0)
14511             disp -= 0x10000;
14512           break;
14513         }
14514
14515       if (!intel_syntax)
14516         if (modrm.mod != 0 || modrm.rm == 6)
14517           {
14518             print_displacement (scratchbuf, disp);
14519             oappend (scratchbuf);
14520           }
14521
14522       if (modrm.mod != 0 || modrm.rm != 6)
14523         {
14524           *obufp++ = open_char;
14525           *obufp = '\0';
14526           oappend (index16[modrm.rm]);
14527           if (intel_syntax
14528               && (disp || modrm.mod != 0 || modrm.rm == 6))
14529             {
14530               if ((bfd_signed_vma) disp >= 0)
14531                 {
14532                   *obufp++ = '+';
14533                   *obufp = '\0';
14534                 }
14535               else if (modrm.mod != 1)
14536                 {
14537                   *obufp++ = '-';
14538                   *obufp = '\0';
14539                   disp = - (bfd_signed_vma) disp;
14540                 }
14541
14542               print_displacement (scratchbuf, disp);
14543               oappend (scratchbuf);
14544             }
14545
14546           *obufp++ = close_char;
14547           *obufp = '\0';
14548         }
14549       else if (intel_syntax)
14550         {
14551           if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
14552                           | PREFIX_ES | PREFIX_FS | PREFIX_GS))
14553             ;
14554           else
14555             {
14556               oappend (names_seg[ds_reg - es_reg]);
14557               oappend (":");
14558             }
14559           print_operand_value (scratchbuf, 1, disp & 0xffff);
14560           oappend (scratchbuf);
14561         }
14562     }
14563   if (vex.evex && vex.b
14564       && (bytemode == x_mode
14565           || bytemode == evex_half_bcst_xmmq_mode))
14566     {
14567       if (vex.w || bytemode == evex_half_bcst_xmmq_mode)
14568         oappend ("{1to8}");
14569       else
14570         oappend ("{1to16}");
14571     }
14572 }
14573
14574 static void
14575 OP_E (int bytemode, int sizeflag)
14576 {
14577   /* Skip mod/rm byte.  */
14578   MODRM_CHECK;
14579   codep++;
14580
14581   if (modrm.mod == 3)
14582     OP_E_register (bytemode, sizeflag);
14583   else
14584     OP_E_memory (bytemode, sizeflag);
14585 }
14586
14587 static void
14588 OP_G (int bytemode, int sizeflag)
14589 {
14590   int add = 0;
14591   USED_REX (REX_R);
14592   if (rex & REX_R)
14593     add += 8;
14594   switch (bytemode)
14595     {
14596     case b_mode:
14597       USED_REX (0);
14598       if (rex)
14599         oappend (names8rex[modrm.reg + add]);
14600       else
14601         oappend (names8[modrm.reg + add]);
14602       break;
14603     case w_mode:
14604       oappend (names16[modrm.reg + add]);
14605       break;
14606     case d_mode:
14607       oappend (names32[modrm.reg + add]);
14608       break;
14609     case q_mode:
14610       oappend (names64[modrm.reg + add]);
14611       break;
14612     case bnd_mode:
14613       oappend (names_bnd[modrm.reg]);
14614       break;
14615     case v_mode:
14616     case dq_mode:
14617     case dqb_mode:
14618     case dqd_mode:
14619     case dqw_mode:
14620       USED_REX (REX_W);
14621       if (rex & REX_W)
14622         oappend (names64[modrm.reg + add]);
14623       else
14624         {
14625           if ((sizeflag & DFLAG) || bytemode != v_mode)
14626             oappend (names32[modrm.reg + add]);
14627           else
14628             oappend (names16[modrm.reg + add]);
14629           used_prefixes |= (prefixes & PREFIX_DATA);
14630         }
14631       break;
14632     case m_mode:
14633       if (address_mode == mode_64bit)
14634         oappend (names64[modrm.reg + add]);
14635       else
14636         oappend (names32[modrm.reg + add]);
14637       break;
14638     case mask_mode:
14639       oappend (names_mask[modrm.reg + add]);
14640       break;
14641     default:
14642       oappend (INTERNAL_DISASSEMBLER_ERROR);
14643       break;
14644     }
14645 }
14646
14647 static bfd_vma
14648 get64 (void)
14649 {
14650   bfd_vma x;
14651 #ifdef BFD64
14652   unsigned int a;
14653   unsigned int b;
14654
14655   FETCH_DATA (the_info, codep + 8);
14656   a = *codep++ & 0xff;
14657   a |= (*codep++ & 0xff) << 8;
14658   a |= (*codep++ & 0xff) << 16;
14659   a |= (*codep++ & 0xff) << 24;
14660   b = *codep++ & 0xff;
14661   b |= (*codep++ & 0xff) << 8;
14662   b |= (*codep++ & 0xff) << 16;
14663   b |= (*codep++ & 0xff) << 24;
14664   x = a + ((bfd_vma) b << 32);
14665 #else
14666   abort ();
14667   x = 0;
14668 #endif
14669   return x;
14670 }
14671
14672 static bfd_signed_vma
14673 get32 (void)
14674 {
14675   bfd_signed_vma x = 0;
14676
14677   FETCH_DATA (the_info, codep + 4);
14678   x = *codep++ & (bfd_signed_vma) 0xff;
14679   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14680   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14681   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14682   return x;
14683 }
14684
14685 static bfd_signed_vma
14686 get32s (void)
14687 {
14688   bfd_signed_vma x = 0;
14689
14690   FETCH_DATA (the_info, codep + 4);
14691   x = *codep++ & (bfd_signed_vma) 0xff;
14692   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14693   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14694   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14695
14696   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
14697
14698   return x;
14699 }
14700
14701 static int
14702 get16 (void)
14703 {
14704   int x = 0;
14705
14706   FETCH_DATA (the_info, codep + 2);
14707   x = *codep++ & 0xff;
14708   x |= (*codep++ & 0xff) << 8;
14709   return x;
14710 }
14711
14712 static void
14713 set_op (bfd_vma op, int riprel)
14714 {
14715   op_index[op_ad] = op_ad;
14716   if (address_mode == mode_64bit)
14717     {
14718       op_address[op_ad] = op;
14719       op_riprel[op_ad] = riprel;
14720     }
14721   else
14722     {
14723       /* Mask to get a 32-bit address.  */
14724       op_address[op_ad] = op & 0xffffffff;
14725       op_riprel[op_ad] = riprel & 0xffffffff;
14726     }
14727 }
14728
14729 static void
14730 OP_REG (int code, int sizeflag)
14731 {
14732   const char *s;
14733   int add;
14734
14735   switch (code)
14736     {
14737     case es_reg: case ss_reg: case cs_reg:
14738     case ds_reg: case fs_reg: case gs_reg:
14739       oappend (names_seg[code - es_reg]);
14740       return;
14741     }
14742
14743   USED_REX (REX_B);
14744   if (rex & REX_B)
14745     add = 8;
14746   else
14747     add = 0;
14748
14749   switch (code)
14750     {
14751     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14752     case sp_reg: case bp_reg: case si_reg: case di_reg:
14753       s = names16[code - ax_reg + add];
14754       break;
14755     case al_reg: case ah_reg: case cl_reg: case ch_reg:
14756     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14757       USED_REX (0);
14758       if (rex)
14759         s = names8rex[code - al_reg + add];
14760       else
14761         s = names8[code - al_reg];
14762       break;
14763     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
14764     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
14765       if (address_mode == mode_64bit
14766           && ((sizeflag & DFLAG) || (rex & REX_W)))
14767         {
14768           s = names64[code - rAX_reg + add];
14769           break;
14770         }
14771       code += eAX_reg - rAX_reg;
14772       /* Fall through.  */
14773     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14774     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14775       USED_REX (REX_W);
14776       if (rex & REX_W)
14777         s = names64[code - eAX_reg + add];
14778       else
14779         {
14780           if (sizeflag & DFLAG)
14781             s = names32[code - eAX_reg + add];
14782           else
14783             s = names16[code - eAX_reg + add];
14784           used_prefixes |= (prefixes & PREFIX_DATA);
14785         }
14786       break;
14787     default:
14788       s = INTERNAL_DISASSEMBLER_ERROR;
14789       break;
14790     }
14791   oappend (s);
14792 }
14793
14794 static void
14795 OP_IMREG (int code, int sizeflag)
14796 {
14797   const char *s;
14798
14799   switch (code)
14800     {
14801     case indir_dx_reg:
14802       if (intel_syntax)
14803         s = "dx";
14804       else
14805         s = "(%dx)";
14806       break;
14807     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14808     case sp_reg: case bp_reg: case si_reg: case di_reg:
14809       s = names16[code - ax_reg];
14810       break;
14811     case es_reg: case ss_reg: case cs_reg:
14812     case ds_reg: case fs_reg: case gs_reg:
14813       s = names_seg[code - es_reg];
14814       break;
14815     case al_reg: case ah_reg: case cl_reg: case ch_reg:
14816     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14817       USED_REX (0);
14818       if (rex)
14819         s = names8rex[code - al_reg];
14820       else
14821         s = names8[code - al_reg];
14822       break;
14823     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14824     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14825       USED_REX (REX_W);
14826       if (rex & REX_W)
14827         s = names64[code - eAX_reg];
14828       else
14829         {
14830           if (sizeflag & DFLAG)
14831             s = names32[code - eAX_reg];
14832           else
14833             s = names16[code - eAX_reg];
14834           used_prefixes |= (prefixes & PREFIX_DATA);
14835         }
14836       break;
14837     case z_mode_ax_reg:
14838       if ((rex & REX_W) || (sizeflag & DFLAG))
14839         s = *names32;
14840       else
14841         s = *names16;
14842       if (!(rex & REX_W))
14843         used_prefixes |= (prefixes & PREFIX_DATA);
14844       break;
14845     default:
14846       s = INTERNAL_DISASSEMBLER_ERROR;
14847       break;
14848     }
14849   oappend (s);
14850 }
14851
14852 static void
14853 OP_I (int bytemode, int sizeflag)
14854 {
14855   bfd_signed_vma op;
14856   bfd_signed_vma mask = -1;
14857
14858   switch (bytemode)
14859     {
14860     case b_mode:
14861       FETCH_DATA (the_info, codep + 1);
14862       op = *codep++;
14863       mask = 0xff;
14864       break;
14865     case q_mode:
14866       if (address_mode == mode_64bit)
14867         {
14868           op = get32s ();
14869           break;
14870         }
14871       /* Fall through.  */
14872     case v_mode:
14873       USED_REX (REX_W);
14874       if (rex & REX_W)
14875         op = get32s ();
14876       else
14877         {
14878           if (sizeflag & DFLAG)
14879             {
14880               op = get32 ();
14881               mask = 0xffffffff;
14882             }
14883           else
14884             {
14885               op = get16 ();
14886               mask = 0xfffff;
14887             }
14888           used_prefixes |= (prefixes & PREFIX_DATA);
14889         }
14890       break;
14891     case w_mode:
14892       mask = 0xfffff;
14893       op = get16 ();
14894       break;
14895     case const_1_mode:
14896       if (intel_syntax)
14897         oappend ("1");
14898       return;
14899     default:
14900       oappend (INTERNAL_DISASSEMBLER_ERROR);
14901       return;
14902     }
14903
14904   op &= mask;
14905   scratchbuf[0] = '$';
14906   print_operand_value (scratchbuf + 1, 1, op);
14907   oappend (scratchbuf + intel_syntax);
14908   scratchbuf[0] = '\0';
14909 }
14910
14911 static void
14912 OP_I64 (int bytemode, int sizeflag)
14913 {
14914   bfd_signed_vma op;
14915   bfd_signed_vma mask = -1;
14916
14917   if (address_mode != mode_64bit)
14918     {
14919       OP_I (bytemode, sizeflag);
14920       return;
14921     }
14922
14923   switch (bytemode)
14924     {
14925     case b_mode:
14926       FETCH_DATA (the_info, codep + 1);
14927       op = *codep++;
14928       mask = 0xff;
14929       break;
14930     case v_mode:
14931       USED_REX (REX_W);
14932       if (rex & REX_W)
14933         op = get64 ();
14934       else
14935         {
14936           if (sizeflag & DFLAG)
14937             {
14938               op = get32 ();
14939               mask = 0xffffffff;
14940             }
14941           else
14942             {
14943               op = get16 ();
14944               mask = 0xfffff;
14945             }
14946           used_prefixes |= (prefixes & PREFIX_DATA);
14947         }
14948       break;
14949     case w_mode:
14950       mask = 0xfffff;
14951       op = get16 ();
14952       break;
14953     default:
14954       oappend (INTERNAL_DISASSEMBLER_ERROR);
14955       return;
14956     }
14957
14958   op &= mask;
14959   scratchbuf[0] = '$';
14960   print_operand_value (scratchbuf + 1, 1, op);
14961   oappend (scratchbuf + intel_syntax);
14962   scratchbuf[0] = '\0';
14963 }
14964
14965 static void
14966 OP_sI (int bytemode, int sizeflag)
14967 {
14968   bfd_signed_vma op;
14969
14970   switch (bytemode)
14971     {
14972     case b_mode:
14973     case b_T_mode:
14974       FETCH_DATA (the_info, codep + 1);
14975       op = *codep++;
14976       if ((op & 0x80) != 0)
14977         op -= 0x100;
14978       if (bytemode == b_T_mode)
14979         {
14980           if (address_mode != mode_64bit
14981               || !((sizeflag & DFLAG) || (rex & REX_W)))
14982             {
14983               /* The operand-size prefix is overridden by a REX prefix.  */
14984               if ((sizeflag & DFLAG) || (rex & REX_W))
14985                 op &= 0xffffffff;
14986               else
14987                 op &= 0xffff;
14988           }
14989         }
14990       else
14991         {
14992           if (!(rex & REX_W))
14993             {
14994               if (sizeflag & DFLAG)
14995                 op &= 0xffffffff;
14996               else
14997                 op &= 0xffff;
14998             }
14999         }
15000       break;
15001     case v_mode:
15002       /* The operand-size prefix is overridden by a REX prefix.  */
15003       if ((sizeflag & DFLAG) || (rex & REX_W))
15004         op = get32s ();
15005       else
15006         op = get16 ();
15007       break;
15008     default:
15009       oappend (INTERNAL_DISASSEMBLER_ERROR);
15010       return;
15011     }
15012
15013   scratchbuf[0] = '$';
15014   print_operand_value (scratchbuf + 1, 1, op);
15015   oappend (scratchbuf + intel_syntax);
15016 }
15017
15018 static void
15019 OP_J (int bytemode, int sizeflag)
15020 {
15021   bfd_vma disp;
15022   bfd_vma mask = -1;
15023   bfd_vma segment = 0;
15024
15025   switch (bytemode)
15026     {
15027     case b_mode:
15028       FETCH_DATA (the_info, codep + 1);
15029       disp = *codep++;
15030       if ((disp & 0x80) != 0)
15031         disp -= 0x100;
15032       break;
15033     case v_mode:
15034       USED_REX (REX_W);
15035       if ((sizeflag & DFLAG) || (rex & REX_W))
15036         disp = get32s ();
15037       else
15038         {
15039           disp = get16 ();
15040           if ((disp & 0x8000) != 0)
15041             disp -= 0x10000;
15042           /* In 16bit mode, address is wrapped around at 64k within
15043              the same segment.  Otherwise, a data16 prefix on a jump
15044              instruction means that the pc is masked to 16 bits after
15045              the displacement is added!  */
15046           mask = 0xffff;
15047           if ((prefixes & PREFIX_DATA) == 0)
15048             segment = ((start_pc + codep - start_codep)
15049                        & ~((bfd_vma) 0xffff));
15050         }
15051       if (!(rex & REX_W))
15052         used_prefixes |= (prefixes & PREFIX_DATA);
15053       break;
15054     default:
15055       oappend (INTERNAL_DISASSEMBLER_ERROR);
15056       return;
15057     }
15058   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
15059   set_op (disp, 0);
15060   print_operand_value (scratchbuf, 1, disp);
15061   oappend (scratchbuf);
15062 }
15063
15064 static void
15065 OP_SEG (int bytemode, int sizeflag)
15066 {
15067   if (bytemode == w_mode)
15068     oappend (names_seg[modrm.reg]);
15069   else
15070     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
15071 }
15072
15073 static void
15074 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
15075 {
15076   int seg, offset;
15077
15078   if (sizeflag & DFLAG)
15079     {
15080       offset = get32 ();
15081       seg = get16 ();
15082     }
15083   else
15084     {
15085       offset = get16 ();
15086       seg = get16 ();
15087     }
15088   used_prefixes |= (prefixes & PREFIX_DATA);
15089   if (intel_syntax)
15090     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
15091   else
15092     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
15093   oappend (scratchbuf);
15094 }
15095
15096 static void
15097 OP_OFF (int bytemode, int sizeflag)
15098 {
15099   bfd_vma off;
15100
15101   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
15102     intel_operand_size (bytemode, sizeflag);
15103   append_seg ();
15104
15105   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
15106     off = get32 ();
15107   else
15108     off = get16 ();
15109
15110   if (intel_syntax)
15111     {
15112       if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
15113                         | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
15114         {
15115           oappend (names_seg[ds_reg - es_reg]);
15116           oappend (":");
15117         }
15118     }
15119   print_operand_value (scratchbuf, 1, off);
15120   oappend (scratchbuf);
15121 }
15122
15123 static void
15124 OP_OFF64 (int bytemode, int sizeflag)
15125 {
15126   bfd_vma off;
15127
15128   if (address_mode != mode_64bit
15129       || (prefixes & PREFIX_ADDR))
15130     {
15131       OP_OFF (bytemode, sizeflag);
15132       return;
15133     }
15134
15135   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
15136     intel_operand_size (bytemode, sizeflag);
15137   append_seg ();
15138
15139   off = get64 ();
15140
15141   if (intel_syntax)
15142     {
15143       if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
15144                         | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
15145         {
15146           oappend (names_seg[ds_reg - es_reg]);
15147           oappend (":");
15148         }
15149     }
15150   print_operand_value (scratchbuf, 1, off);
15151   oappend (scratchbuf);
15152 }
15153
15154 static void
15155 ptr_reg (int code, int sizeflag)
15156 {
15157   const char *s;
15158
15159   *obufp++ = open_char;
15160   used_prefixes |= (prefixes & PREFIX_ADDR);
15161   if (address_mode == mode_64bit)
15162     {
15163       if (!(sizeflag & AFLAG))
15164         s = names32[code - eAX_reg];
15165       else
15166         s = names64[code - eAX_reg];
15167     }
15168   else if (sizeflag & AFLAG)
15169     s = names32[code - eAX_reg];
15170   else
15171     s = names16[code - eAX_reg];
15172   oappend (s);
15173   *obufp++ = close_char;
15174   *obufp = 0;
15175 }
15176
15177 static void
15178 OP_ESreg (int code, int sizeflag)
15179 {
15180   if (intel_syntax)
15181     {
15182       switch (codep[-1])
15183         {
15184         case 0x6d:      /* insw/insl */
15185           intel_operand_size (z_mode, sizeflag);
15186           break;
15187         case 0xa5:      /* movsw/movsl/movsq */
15188         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15189         case 0xab:      /* stosw/stosl */
15190         case 0xaf:      /* scasw/scasl */
15191           intel_operand_size (v_mode, sizeflag);
15192           break;
15193         default:
15194           intel_operand_size (b_mode, sizeflag);
15195         }
15196     }
15197   oappend ("%es:" + intel_syntax);
15198   ptr_reg (code, sizeflag);
15199 }
15200
15201 static void
15202 OP_DSreg (int code, int sizeflag)
15203 {
15204   if (intel_syntax)
15205     {
15206       switch (codep[-1])
15207         {
15208         case 0x6f:      /* outsw/outsl */
15209           intel_operand_size (z_mode, sizeflag);
15210           break;
15211         case 0xa5:      /* movsw/movsl/movsq */
15212         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15213         case 0xad:      /* lodsw/lodsl/lodsq */
15214           intel_operand_size (v_mode, sizeflag);
15215           break;
15216         default:
15217           intel_operand_size (b_mode, sizeflag);
15218         }
15219     }
15220   if ((prefixes
15221        & (PREFIX_CS
15222           | PREFIX_DS
15223           | PREFIX_SS
15224           | PREFIX_ES
15225           | PREFIX_FS
15226           | PREFIX_GS)) == 0)
15227     prefixes |= PREFIX_DS;
15228   append_seg ();
15229   ptr_reg (code, sizeflag);
15230 }
15231
15232 static void
15233 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15234 {
15235   int add;
15236   if (rex & REX_R)
15237     {
15238       USED_REX (REX_R);
15239       add = 8;
15240     }
15241   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
15242     {
15243       all_prefixes[last_lock_prefix] = 0;
15244       used_prefixes |= PREFIX_LOCK;
15245       add = 8;
15246     }
15247   else
15248     add = 0;
15249   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
15250   oappend (scratchbuf + intel_syntax);
15251 }
15252
15253 static void
15254 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15255 {
15256   int add;
15257   USED_REX (REX_R);
15258   if (rex & REX_R)
15259     add = 8;
15260   else
15261     add = 0;
15262   if (intel_syntax)
15263     sprintf (scratchbuf, "db%d", modrm.reg + add);
15264   else
15265     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
15266   oappend (scratchbuf);
15267 }
15268
15269 static void
15270 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15271 {
15272   sprintf (scratchbuf, "%%tr%d", modrm.reg);
15273   oappend (scratchbuf + intel_syntax);
15274 }
15275
15276 static void
15277 OP_R (int bytemode, int sizeflag)
15278 {
15279   if (modrm.mod == 3)
15280     OP_E (bytemode, sizeflag);
15281   else
15282     BadOp ();
15283 }
15284
15285 static void
15286 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15287 {
15288   int reg = modrm.reg;
15289   const char **names;
15290
15291   used_prefixes |= (prefixes & PREFIX_DATA);
15292   if (prefixes & PREFIX_DATA)
15293     {
15294       names = names_xmm;
15295       USED_REX (REX_R);
15296       if (rex & REX_R)
15297         reg += 8;
15298     }
15299   else
15300     names = names_mm;
15301   oappend (names[reg]);
15302 }
15303
15304 static void
15305 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15306 {
15307   int reg = modrm.reg;
15308   const char **names;
15309
15310   USED_REX (REX_R);
15311   if (rex & REX_R)
15312     reg += 8;
15313   if (vex.evex)
15314     {
15315       if (!vex.r)
15316         reg += 16;
15317     }
15318
15319   if (need_vex
15320       && bytemode != xmm_mode
15321       && bytemode != xmmq_mode
15322       && bytemode != evex_half_bcst_xmmq_mode
15323       && bytemode != ymm_mode
15324       && bytemode != scalar_mode)
15325     {
15326       switch (vex.length)
15327         {
15328         case 128:
15329           names = names_xmm;
15330           break;
15331         case 256:
15332           if (vex.w || bytemode != vex_vsib_q_w_dq_mode)
15333             names = names_ymm;
15334           else
15335             names = names_xmm;
15336           break;
15337         case 512:
15338           names = names_zmm;
15339           break;
15340         default:
15341           abort ();
15342         }
15343     }
15344   else if (bytemode == xmmq_mode
15345            || bytemode == evex_half_bcst_xmmq_mode)
15346     {
15347       switch (vex.length)
15348         {
15349         case 128:
15350         case 256:
15351           names = names_xmm;
15352           break;
15353         case 512:
15354           names = names_ymm;
15355           break;
15356         default:
15357           abort ();
15358         }
15359     }
15360   else if (bytemode == ymm_mode)
15361     names = names_ymm;
15362   else
15363     names = names_xmm;
15364   oappend (names[reg]);
15365 }
15366
15367 static void
15368 OP_EM (int bytemode, int sizeflag)
15369 {
15370   int reg;
15371   const char **names;
15372
15373   if (modrm.mod != 3)
15374     {
15375       if (intel_syntax
15376           && (bytemode == v_mode || bytemode == v_swap_mode))
15377         {
15378           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15379           used_prefixes |= (prefixes & PREFIX_DATA);
15380         }
15381       OP_E (bytemode, sizeflag);
15382       return;
15383     }
15384
15385   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
15386     swap_operand ();
15387
15388   /* Skip mod/rm byte.  */
15389   MODRM_CHECK;
15390   codep++;
15391   used_prefixes |= (prefixes & PREFIX_DATA);
15392   reg = modrm.rm;
15393   if (prefixes & PREFIX_DATA)
15394     {
15395       names = names_xmm;
15396       USED_REX (REX_B);
15397       if (rex & REX_B)
15398         reg += 8;
15399     }
15400   else
15401     names = names_mm;
15402   oappend (names[reg]);
15403 }
15404
15405 /* cvt* are the only instructions in sse2 which have
15406    both SSE and MMX operands and also have 0x66 prefix
15407    in their opcode. 0x66 was originally used to differentiate
15408    between SSE and MMX instruction(operands). So we have to handle the
15409    cvt* separately using OP_EMC and OP_MXC */
15410 static void
15411 OP_EMC (int bytemode, int sizeflag)
15412 {
15413   if (modrm.mod != 3)
15414     {
15415       if (intel_syntax && bytemode == v_mode)
15416         {
15417           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15418           used_prefixes |= (prefixes & PREFIX_DATA);
15419         }
15420       OP_E (bytemode, sizeflag);
15421       return;
15422     }
15423
15424   /* Skip mod/rm byte.  */
15425   MODRM_CHECK;
15426   codep++;
15427   used_prefixes |= (prefixes & PREFIX_DATA);
15428   oappend (names_mm[modrm.rm]);
15429 }
15430
15431 static void
15432 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15433 {
15434   used_prefixes |= (prefixes & PREFIX_DATA);
15435   oappend (names_mm[modrm.reg]);
15436 }
15437
15438 static void
15439 OP_EX (int bytemode, int sizeflag)
15440 {
15441   int reg;
15442   const char **names;
15443
15444   /* Skip mod/rm byte.  */
15445   MODRM_CHECK;
15446   codep++;
15447
15448   if (modrm.mod != 3)
15449     {
15450       OP_E_memory (bytemode, sizeflag);
15451       return;
15452     }
15453
15454   reg = modrm.rm;
15455   USED_REX (REX_B);
15456   if (rex & REX_B)
15457     reg += 8;
15458   if (vex.evex)
15459     {
15460       USED_REX (REX_X);
15461       if ((rex & REX_X))
15462         reg += 16;
15463     }
15464
15465   if ((sizeflag & SUFFIX_ALWAYS)
15466       && (bytemode == x_swap_mode
15467           || bytemode == d_swap_mode
15468           || bytemode == d_scalar_swap_mode
15469           || bytemode == q_swap_mode
15470           || bytemode == q_scalar_swap_mode))
15471     swap_operand ();
15472
15473   if (need_vex
15474       && bytemode != xmm_mode
15475       && bytemode != xmmdw_mode
15476       && bytemode != xmmqd_mode
15477       && bytemode != xmm_mb_mode
15478       && bytemode != xmm_mw_mode
15479       && bytemode != xmm_md_mode
15480       && bytemode != xmm_mq_mode
15481       && bytemode != xmm_mdq_mode
15482       && bytemode != xmmq_mode
15483       && bytemode != evex_half_bcst_xmmq_mode
15484       && bytemode != ymm_mode
15485       && bytemode != d_scalar_mode
15486       && bytemode != d_scalar_swap_mode
15487       && bytemode != q_scalar_mode
15488       && bytemode != q_scalar_swap_mode
15489       && bytemode != vex_scalar_w_dq_mode)
15490     {
15491       switch (vex.length)
15492         {
15493         case 128:
15494           names = names_xmm;
15495           break;
15496         case 256:
15497           names = names_ymm;
15498           break;
15499         case 512:
15500           names = names_zmm;
15501           break;
15502         default:
15503           abort ();
15504         }
15505     }
15506   else if (bytemode == xmmq_mode
15507            || bytemode == evex_half_bcst_xmmq_mode)
15508     {
15509       switch (vex.length)
15510         {
15511         case 128:
15512         case 256:
15513           names = names_xmm;
15514           break;
15515         case 512:
15516           names = names_ymm;
15517           break;
15518         default:
15519           abort ();
15520         }
15521     }
15522   else if (bytemode == ymm_mode)
15523     names = names_ymm;
15524   else
15525     names = names_xmm;
15526   oappend (names[reg]);
15527 }
15528
15529 static void
15530 OP_MS (int bytemode, int sizeflag)
15531 {
15532   if (modrm.mod == 3)
15533     OP_EM (bytemode, sizeflag);
15534   else
15535     BadOp ();
15536 }
15537
15538 static void
15539 OP_XS (int bytemode, int sizeflag)
15540 {
15541   if (modrm.mod == 3)
15542     OP_EX (bytemode, sizeflag);
15543   else
15544     BadOp ();
15545 }
15546
15547 static void
15548 OP_M (int bytemode, int sizeflag)
15549 {
15550   if (modrm.mod == 3)
15551     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
15552     BadOp ();
15553   else
15554     OP_E (bytemode, sizeflag);
15555 }
15556
15557 static void
15558 OP_0f07 (int bytemode, int sizeflag)
15559 {
15560   if (modrm.mod != 3 || modrm.rm != 0)
15561     BadOp ();
15562   else
15563     OP_E (bytemode, sizeflag);
15564 }
15565
15566 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
15567    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
15568
15569 static void
15570 NOP_Fixup1 (int bytemode, int sizeflag)
15571 {
15572   if ((prefixes & PREFIX_DATA) != 0
15573       || (rex != 0
15574           && rex != 0x48
15575           && address_mode == mode_64bit))
15576     OP_REG (bytemode, sizeflag);
15577   else
15578     strcpy (obuf, "nop");
15579 }
15580
15581 static void
15582 NOP_Fixup2 (int bytemode, int sizeflag)
15583 {
15584   if ((prefixes & PREFIX_DATA) != 0
15585       || (rex != 0
15586           && rex != 0x48
15587           && address_mode == mode_64bit))
15588     OP_IMREG (bytemode, sizeflag);
15589 }
15590
15591 static const char *const Suffix3DNow[] = {
15592 /* 00 */        NULL,           NULL,           NULL,           NULL,
15593 /* 04 */        NULL,           NULL,           NULL,           NULL,
15594 /* 08 */        NULL,           NULL,           NULL,           NULL,
15595 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
15596 /* 10 */        NULL,           NULL,           NULL,           NULL,
15597 /* 14 */        NULL,           NULL,           NULL,           NULL,
15598 /* 18 */        NULL,           NULL,           NULL,           NULL,
15599 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
15600 /* 20 */        NULL,           NULL,           NULL,           NULL,
15601 /* 24 */        NULL,           NULL,           NULL,           NULL,
15602 /* 28 */        NULL,           NULL,           NULL,           NULL,
15603 /* 2C */        NULL,           NULL,           NULL,           NULL,
15604 /* 30 */        NULL,           NULL,           NULL,           NULL,
15605 /* 34 */        NULL,           NULL,           NULL,           NULL,
15606 /* 38 */        NULL,           NULL,           NULL,           NULL,
15607 /* 3C */        NULL,           NULL,           NULL,           NULL,
15608 /* 40 */        NULL,           NULL,           NULL,           NULL,
15609 /* 44 */        NULL,           NULL,           NULL,           NULL,
15610 /* 48 */        NULL,           NULL,           NULL,           NULL,
15611 /* 4C */        NULL,           NULL,           NULL,           NULL,
15612 /* 50 */        NULL,           NULL,           NULL,           NULL,
15613 /* 54 */        NULL,           NULL,           NULL,           NULL,
15614 /* 58 */        NULL,           NULL,           NULL,           NULL,
15615 /* 5C */        NULL,           NULL,           NULL,           NULL,
15616 /* 60 */        NULL,           NULL,           NULL,           NULL,
15617 /* 64 */        NULL,           NULL,           NULL,           NULL,
15618 /* 68 */        NULL,           NULL,           NULL,           NULL,
15619 /* 6C */        NULL,           NULL,           NULL,           NULL,
15620 /* 70 */        NULL,           NULL,           NULL,           NULL,
15621 /* 74 */        NULL,           NULL,           NULL,           NULL,
15622 /* 78 */        NULL,           NULL,           NULL,           NULL,
15623 /* 7C */        NULL,           NULL,           NULL,           NULL,
15624 /* 80 */        NULL,           NULL,           NULL,           NULL,
15625 /* 84 */        NULL,           NULL,           NULL,           NULL,
15626 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
15627 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
15628 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
15629 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
15630 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
15631 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
15632 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
15633 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
15634 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
15635 /* AC */        NULL,           NULL,           "pfacc",        NULL,
15636 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
15637 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
15638 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
15639 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
15640 /* C0 */        NULL,           NULL,           NULL,           NULL,
15641 /* C4 */        NULL,           NULL,           NULL,           NULL,
15642 /* C8 */        NULL,           NULL,           NULL,           NULL,
15643 /* CC */        NULL,           NULL,           NULL,           NULL,
15644 /* D0 */        NULL,           NULL,           NULL,           NULL,
15645 /* D4 */        NULL,           NULL,           NULL,           NULL,
15646 /* D8 */        NULL,           NULL,           NULL,           NULL,
15647 /* DC */        NULL,           NULL,           NULL,           NULL,
15648 /* E0 */        NULL,           NULL,           NULL,           NULL,
15649 /* E4 */        NULL,           NULL,           NULL,           NULL,
15650 /* E8 */        NULL,           NULL,           NULL,           NULL,
15651 /* EC */        NULL,           NULL,           NULL,           NULL,
15652 /* F0 */        NULL,           NULL,           NULL,           NULL,
15653 /* F4 */        NULL,           NULL,           NULL,           NULL,
15654 /* F8 */        NULL,           NULL,           NULL,           NULL,
15655 /* FC */        NULL,           NULL,           NULL,           NULL,
15656 };
15657
15658 static void
15659 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15660 {
15661   const char *mnemonic;
15662
15663   FETCH_DATA (the_info, codep + 1);
15664   /* AMD 3DNow! instructions are specified by an opcode suffix in the
15665      place where an 8-bit immediate would normally go.  ie. the last
15666      byte of the instruction.  */
15667   obufp = mnemonicendp;
15668   mnemonic = Suffix3DNow[*codep++ & 0xff];
15669   if (mnemonic)
15670     oappend (mnemonic);
15671   else
15672     {
15673       /* Since a variable sized modrm/sib chunk is between the start
15674          of the opcode (0x0f0f) and the opcode suffix, we need to do
15675          all the modrm processing first, and don't know until now that
15676          we have a bad opcode.  This necessitates some cleaning up.  */
15677       op_out[0][0] = '\0';
15678       op_out[1][0] = '\0';
15679       BadOp ();
15680     }
15681   mnemonicendp = obufp;
15682 }
15683
15684 static struct op simd_cmp_op[] =
15685 {
15686   { STRING_COMMA_LEN ("eq") },
15687   { STRING_COMMA_LEN ("lt") },
15688   { STRING_COMMA_LEN ("le") },
15689   { STRING_COMMA_LEN ("unord") },
15690   { STRING_COMMA_LEN ("neq") },
15691   { STRING_COMMA_LEN ("nlt") },
15692   { STRING_COMMA_LEN ("nle") },
15693   { STRING_COMMA_LEN ("ord") }
15694 };
15695
15696 static void
15697 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15698 {
15699   unsigned int cmp_type;
15700
15701   FETCH_DATA (the_info, codep + 1);
15702   cmp_type = *codep++ & 0xff;
15703   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
15704     {
15705       char suffix [3];
15706       char *p = mnemonicendp - 2;
15707       suffix[0] = p[0];
15708       suffix[1] = p[1];
15709       suffix[2] = '\0';
15710       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
15711       mnemonicendp += simd_cmp_op[cmp_type].len;
15712     }
15713   else
15714     {
15715       /* We have a reserved extension byte.  Output it directly.  */
15716       scratchbuf[0] = '$';
15717       print_operand_value (scratchbuf + 1, 1, cmp_type);
15718       oappend (scratchbuf + intel_syntax);
15719       scratchbuf[0] = '\0';
15720     }
15721 }
15722
15723 static void
15724 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
15725           int sizeflag ATTRIBUTE_UNUSED)
15726 {
15727   /* mwait %eax,%ecx  */
15728   if (!intel_syntax)
15729     {
15730       const char **names = (address_mode == mode_64bit
15731                             ? names64 : names32);
15732       strcpy (op_out[0], names[0]);
15733       strcpy (op_out[1], names[1]);
15734       two_source_ops = 1;
15735     }
15736   /* Skip mod/rm byte.  */
15737   MODRM_CHECK;
15738   codep++;
15739 }
15740
15741 static void
15742 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
15743             int sizeflag ATTRIBUTE_UNUSED)
15744 {
15745   /* monitor %eax,%ecx,%edx"  */
15746   if (!intel_syntax)
15747     {
15748       const char **op1_names;
15749       const char **names = (address_mode == mode_64bit
15750                             ? names64 : names32);
15751
15752       if (!(prefixes & PREFIX_ADDR))
15753         op1_names = (address_mode == mode_16bit
15754                      ? names16 : names);
15755       else
15756         {
15757           /* Remove "addr16/addr32".  */
15758           all_prefixes[last_addr_prefix] = 0;
15759           op1_names = (address_mode != mode_32bit
15760                        ? names32 : names16);
15761           used_prefixes |= PREFIX_ADDR;
15762         }
15763       strcpy (op_out[0], op1_names[0]);
15764       strcpy (op_out[1], names[1]);
15765       strcpy (op_out[2], names[2]);
15766       two_source_ops = 1;
15767     }
15768   /* Skip mod/rm byte.  */
15769   MODRM_CHECK;
15770   codep++;
15771 }
15772
15773 static void
15774 BadOp (void)
15775 {
15776   /* Throw away prefixes and 1st. opcode byte.  */
15777   codep = insn_codep + 1;
15778   oappend ("(bad)");
15779 }
15780
15781 static void
15782 REP_Fixup (int bytemode, int sizeflag)
15783 {
15784   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
15785      lods and stos.  */
15786   if (prefixes & PREFIX_REPZ)
15787     all_prefixes[last_repz_prefix] = REP_PREFIX;
15788
15789   switch (bytemode)
15790     {
15791     case al_reg:
15792     case eAX_reg:
15793     case indir_dx_reg:
15794       OP_IMREG (bytemode, sizeflag);
15795       break;
15796     case eDI_reg:
15797       OP_ESreg (bytemode, sizeflag);
15798       break;
15799     case eSI_reg:
15800       OP_DSreg (bytemode, sizeflag);
15801       break;
15802     default:
15803       abort ();
15804       break;
15805     }
15806 }
15807
15808 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
15809    "bnd".  */
15810
15811 static void
15812 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15813 {
15814   if (prefixes & PREFIX_REPNZ)
15815     all_prefixes[last_repnz_prefix] = BND_PREFIX;
15816 }
15817
15818 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
15819    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
15820  */
15821
15822 static void
15823 HLE_Fixup1 (int bytemode, int sizeflag)
15824 {
15825   if (modrm.mod != 3
15826       && (prefixes & PREFIX_LOCK) != 0)
15827     {
15828       if (prefixes & PREFIX_REPZ)
15829         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15830       if (prefixes & PREFIX_REPNZ)
15831         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15832     }
15833
15834   OP_E (bytemode, sizeflag);
15835 }
15836
15837 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
15838    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
15839  */
15840
15841 static void
15842 HLE_Fixup2 (int bytemode, int sizeflag)
15843 {
15844   if (modrm.mod != 3)
15845     {
15846       if (prefixes & PREFIX_REPZ)
15847         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15848       if (prefixes & PREFIX_REPNZ)
15849         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15850     }
15851
15852   OP_E (bytemode, sizeflag);
15853 }
15854
15855 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
15856    "xrelease" for memory operand.  No check for LOCK prefix.   */
15857
15858 static void
15859 HLE_Fixup3 (int bytemode, int sizeflag)
15860 {
15861   if (modrm.mod != 3
15862       && last_repz_prefix > last_repnz_prefix
15863       && (prefixes & PREFIX_REPZ) != 0)
15864     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15865
15866   OP_E (bytemode, sizeflag);
15867 }
15868
15869 static void
15870 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
15871 {
15872   USED_REX (REX_W);
15873   if (rex & REX_W)
15874     {
15875       /* Change cmpxchg8b to cmpxchg16b.  */
15876       char *p = mnemonicendp - 2;
15877       mnemonicendp = stpcpy (p, "16b");
15878       bytemode = o_mode;
15879     }
15880   else if ((prefixes & PREFIX_LOCK) != 0)
15881     {
15882       if (prefixes & PREFIX_REPZ)
15883         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15884       if (prefixes & PREFIX_REPNZ)
15885         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15886     }
15887
15888   OP_M (bytemode, sizeflag);
15889 }
15890
15891 static void
15892 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
15893 {
15894   const char **names;
15895
15896   if (need_vex)
15897     {
15898       switch (vex.length)
15899         {
15900         case 128:
15901           names = names_xmm;
15902           break;
15903         case 256:
15904           names = names_ymm;
15905           break;
15906         default:
15907           abort ();
15908         }
15909     }
15910   else
15911     names = names_xmm;
15912   oappend (names[reg]);
15913 }
15914
15915 static void
15916 CRC32_Fixup (int bytemode, int sizeflag)
15917 {
15918   /* Add proper suffix to "crc32".  */
15919   char *p = mnemonicendp;
15920
15921   switch (bytemode)
15922     {
15923     case b_mode:
15924       if (intel_syntax)
15925         goto skip;
15926
15927       *p++ = 'b';
15928       break;
15929     case v_mode:
15930       if (intel_syntax)
15931         goto skip;
15932
15933       USED_REX (REX_W);
15934       if (rex & REX_W)
15935         *p++ = 'q';
15936       else
15937         {
15938           if (sizeflag & DFLAG)
15939             *p++ = 'l';
15940           else
15941             *p++ = 'w';
15942           used_prefixes |= (prefixes & PREFIX_DATA);
15943         }
15944       break;
15945     default:
15946       oappend (INTERNAL_DISASSEMBLER_ERROR);
15947       break;
15948     }
15949   mnemonicendp = p;
15950   *p = '\0';
15951
15952 skip:
15953   if (modrm.mod == 3)
15954     {
15955       int add;
15956
15957       /* Skip mod/rm byte.  */
15958       MODRM_CHECK;
15959       codep++;
15960
15961       USED_REX (REX_B);
15962       add = (rex & REX_B) ? 8 : 0;
15963       if (bytemode == b_mode)
15964         {
15965           USED_REX (0);
15966           if (rex)
15967             oappend (names8rex[modrm.rm + add]);
15968           else
15969             oappend (names8[modrm.rm + add]);
15970         }
15971       else
15972         {
15973           USED_REX (REX_W);
15974           if (rex & REX_W)
15975             oappend (names64[modrm.rm + add]);
15976           else if ((prefixes & PREFIX_DATA))
15977             oappend (names16[modrm.rm + add]);
15978           else
15979             oappend (names32[modrm.rm + add]);
15980         }
15981     }
15982   else
15983     OP_E (bytemode, sizeflag);
15984 }
15985
15986 static void
15987 FXSAVE_Fixup (int bytemode, int sizeflag)
15988 {
15989   /* Add proper suffix to "fxsave" and "fxrstor".  */
15990   USED_REX (REX_W);
15991   if (rex & REX_W)
15992     {
15993       char *p = mnemonicendp;
15994       *p++ = '6';
15995       *p++ = '4';
15996       *p = '\0';
15997       mnemonicendp = p;
15998     }
15999   OP_M (bytemode, sizeflag);
16000 }
16001
16002 /* Display the destination register operand for instructions with
16003    VEX. */
16004
16005 static void
16006 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16007 {
16008   int reg;
16009   const char **names;
16010
16011   if (!need_vex)
16012     abort ();
16013
16014   if (!need_vex_reg)
16015     return;
16016
16017   reg = vex.register_specifier;
16018   if (vex.evex)
16019     {
16020       if (!vex.v)
16021         reg += 16;
16022     }
16023
16024   if (bytemode == vex_scalar_mode)
16025     {
16026       oappend (names_xmm[reg]);
16027       return;
16028     }
16029
16030   switch (vex.length)
16031     {
16032     case 128:
16033       switch (bytemode)
16034         {
16035         case vex_mode:
16036         case vex128_mode:
16037         case vex_vsib_q_w_dq_mode:
16038           names = names_xmm;
16039           break;
16040         case dq_mode:
16041           if (vex.w)
16042             names = names64;
16043           else
16044             names = names32;
16045           break;
16046         case mask_mode:
16047           names = names_mask;
16048           break;
16049         default:
16050           abort ();
16051           return;
16052         }
16053       break;
16054     case 256:
16055       switch (bytemode)
16056         {
16057         case vex_mode:
16058         case vex256_mode:
16059           names = names_ymm;
16060           break;
16061         case vex_vsib_q_w_dq_mode:
16062           names = vex.w ? names_ymm : names_xmm;
16063           break;
16064         case mask_mode:
16065           names = names_mask;
16066           break;
16067         default:
16068           abort ();
16069           return;
16070         }
16071       break;
16072     case 512:
16073       names = names_zmm;
16074       break;
16075     default:
16076       abort ();
16077       break;
16078     }
16079   oappend (names[reg]);
16080 }
16081
16082 /* Get the VEX immediate byte without moving codep.  */
16083
16084 static unsigned char
16085 get_vex_imm8 (int sizeflag, int opnum)
16086 {
16087   int bytes_before_imm = 0;
16088
16089   if (modrm.mod != 3)
16090     {
16091       /* There are SIB/displacement bytes.  */
16092       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
16093         {
16094           /* 32/64 bit address mode */
16095           int base = modrm.rm;
16096
16097           /* Check SIB byte.  */
16098           if (base == 4)
16099             {
16100               FETCH_DATA (the_info, codep + 1);
16101               base = *codep & 7;
16102               /* When decoding the third source, don't increase
16103                  bytes_before_imm as this has already been incremented
16104                  by one in OP_E_memory while decoding the second
16105                  source operand.  */
16106               if (opnum == 0)
16107                 bytes_before_imm++;
16108             }
16109
16110           /* Don't increase bytes_before_imm when decoding the third source,
16111              it has already been incremented by OP_E_memory while decoding
16112              the second source operand.  */
16113           if (opnum == 0)
16114             {
16115               switch (modrm.mod)
16116                 {
16117                   case 0:
16118                     /* When modrm.rm == 5 or modrm.rm == 4 and base in
16119                        SIB == 5, there is a 4 byte displacement.  */
16120                     if (base != 5)
16121                       /* No displacement. */
16122                       break;
16123                   case 2:
16124                     /* 4 byte displacement.  */
16125                     bytes_before_imm += 4;
16126                     break;
16127                   case 1:
16128                     /* 1 byte displacement.  */
16129                     bytes_before_imm++;
16130                     break;
16131                 }
16132             }
16133         }
16134       else
16135         {
16136           /* 16 bit address mode */
16137           /* Don't increase bytes_before_imm when decoding the third source,
16138              it has already been incremented by OP_E_memory while decoding
16139              the second source operand.  */
16140           if (opnum == 0)
16141             {
16142               switch (modrm.mod)
16143                 {
16144                 case 0:
16145                   /* When modrm.rm == 6, there is a 2 byte displacement.  */
16146                   if (modrm.rm != 6)
16147                     /* No displacement. */
16148                     break;
16149                 case 2:
16150                   /* 2 byte displacement.  */
16151                   bytes_before_imm += 2;
16152                   break;
16153                 case 1:
16154                   /* 1 byte displacement: when decoding the third source,
16155                      don't increase bytes_before_imm as this has already
16156                      been incremented by one in OP_E_memory while decoding
16157                      the second source operand.  */
16158                   if (opnum == 0)
16159                     bytes_before_imm++;
16160
16161                   break;
16162                 }
16163             }
16164         }
16165     }
16166
16167   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
16168   return codep [bytes_before_imm];
16169 }
16170
16171 static void
16172 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
16173 {
16174   const char **names;
16175
16176   if (reg == -1 && modrm.mod != 3)
16177     {
16178       OP_E_memory (bytemode, sizeflag);
16179       return;
16180     }
16181   else
16182     {
16183       if (reg == -1)
16184         {
16185           reg = modrm.rm;
16186           USED_REX (REX_B);
16187           if (rex & REX_B)
16188             reg += 8;
16189         }
16190       else if (reg > 7 && address_mode != mode_64bit)
16191         BadOp ();
16192     }
16193
16194   switch (vex.length)
16195     {
16196     case 128:
16197       names = names_xmm;
16198       break;
16199     case 256:
16200       names = names_ymm;
16201       break;
16202     default:
16203       abort ();
16204     }
16205   oappend (names[reg]);
16206 }
16207
16208 static void
16209 OP_EX_VexImmW (int bytemode, int sizeflag)
16210 {
16211   int reg = -1;
16212   static unsigned char vex_imm8;
16213
16214   if (vex_w_done == 0)
16215     {
16216       vex_w_done = 1;
16217
16218       /* Skip mod/rm byte.  */
16219       MODRM_CHECK;
16220       codep++;
16221
16222       vex_imm8 = get_vex_imm8 (sizeflag, 0);
16223
16224       if (vex.w)
16225           reg = vex_imm8 >> 4;
16226
16227       OP_EX_VexReg (bytemode, sizeflag, reg);
16228     }
16229   else if (vex_w_done == 1)
16230     {
16231       vex_w_done = 2;
16232
16233       if (!vex.w)
16234           reg = vex_imm8 >> 4;
16235
16236       OP_EX_VexReg (bytemode, sizeflag, reg);
16237     }
16238   else
16239     {
16240       /* Output the imm8 directly.  */
16241       scratchbuf[0] = '$';
16242       print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
16243       oappend (scratchbuf + intel_syntax);
16244       scratchbuf[0] = '\0';
16245       codep++;
16246     }
16247 }
16248
16249 static void
16250 OP_Vex_2src (int bytemode, int sizeflag)
16251 {
16252   if (modrm.mod == 3)
16253     {
16254       int reg = modrm.rm;
16255       USED_REX (REX_B);
16256       if (rex & REX_B)
16257         reg += 8;
16258       oappend (names_xmm[reg]);
16259     }
16260   else
16261     {
16262       if (intel_syntax
16263           && (bytemode == v_mode || bytemode == v_swap_mode))
16264         {
16265           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16266           used_prefixes |= (prefixes & PREFIX_DATA);
16267         }
16268       OP_E (bytemode, sizeflag);
16269     }
16270 }
16271
16272 static void
16273 OP_Vex_2src_1 (int bytemode, int sizeflag)
16274 {
16275   if (modrm.mod == 3)
16276     {
16277       /* Skip mod/rm byte.   */
16278       MODRM_CHECK;
16279       codep++;
16280     }
16281
16282   if (vex.w)
16283     oappend (names_xmm[vex.register_specifier]);
16284   else
16285     OP_Vex_2src (bytemode, sizeflag);
16286 }
16287
16288 static void
16289 OP_Vex_2src_2 (int bytemode, int sizeflag)
16290 {
16291   if (vex.w)
16292     OP_Vex_2src (bytemode, sizeflag);
16293   else
16294     oappend (names_xmm[vex.register_specifier]);
16295 }
16296
16297 static void
16298 OP_EX_VexW (int bytemode, int sizeflag)
16299 {
16300   int reg = -1;
16301
16302   if (!vex_w_done)
16303     {
16304       vex_w_done = 1;
16305
16306       /* Skip mod/rm byte.  */
16307       MODRM_CHECK;
16308       codep++;
16309
16310       if (vex.w)
16311         reg = get_vex_imm8 (sizeflag, 0) >> 4;
16312     }
16313   else
16314     {
16315       if (!vex.w)
16316         reg = get_vex_imm8 (sizeflag, 1) >> 4;
16317     }
16318
16319   OP_EX_VexReg (bytemode, sizeflag, reg);
16320 }
16321
16322 static void
16323 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,
16324              int sizeflag ATTRIBUTE_UNUSED)
16325 {
16326   /* Skip the immediate byte and check for invalid bits.  */
16327   FETCH_DATA (the_info, codep + 1);
16328   if (*codep++ & 0xf)
16329     BadOp ();
16330 }
16331
16332 static void
16333 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16334 {
16335   int reg;
16336   const char **names;
16337
16338   FETCH_DATA (the_info, codep + 1);
16339   reg = *codep++;
16340
16341   if (bytemode != x_mode)
16342     abort ();
16343
16344   if (reg & 0xf)
16345       BadOp ();
16346
16347   reg >>= 4;
16348   if (reg > 7 && address_mode != mode_64bit)
16349     BadOp ();
16350
16351   switch (vex.length)
16352     {
16353     case 128:
16354       names = names_xmm;
16355       break;
16356     case 256:
16357       names = names_ymm;
16358       break;
16359     default:
16360       abort ();
16361     }
16362   oappend (names[reg]);
16363 }
16364
16365 static void
16366 OP_XMM_VexW (int bytemode, int sizeflag)
16367 {
16368   /* Turn off the REX.W bit since it is used for swapping operands
16369      now.  */
16370   rex &= ~REX_W;
16371   OP_XMM (bytemode, sizeflag);
16372 }
16373
16374 static void
16375 OP_EX_Vex (int bytemode, int sizeflag)
16376 {
16377   if (modrm.mod != 3)
16378     {
16379       if (vex.register_specifier != 0)
16380         BadOp ();
16381       need_vex_reg = 0;
16382     }
16383   OP_EX (bytemode, sizeflag);
16384 }
16385
16386 static void
16387 OP_XMM_Vex (int bytemode, int sizeflag)
16388 {
16389   if (modrm.mod != 3)
16390     {
16391       if (vex.register_specifier != 0)
16392         BadOp ();
16393       need_vex_reg = 0;
16394     }
16395   OP_XMM (bytemode, sizeflag);
16396 }
16397
16398 static void
16399 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16400 {
16401   switch (vex.length)
16402     {
16403     case 128:
16404       mnemonicendp = stpcpy (obuf, "vzeroupper");
16405       break;
16406     case 256:
16407       mnemonicendp = stpcpy (obuf, "vzeroall");
16408       break;
16409     default:
16410       abort ();
16411     }
16412 }
16413
16414 static struct op vex_cmp_op[] =
16415 {
16416   { STRING_COMMA_LEN ("eq") },
16417   { STRING_COMMA_LEN ("lt") },
16418   { STRING_COMMA_LEN ("le") },
16419   { STRING_COMMA_LEN ("unord") },
16420   { STRING_COMMA_LEN ("neq") },
16421   { STRING_COMMA_LEN ("nlt") },
16422   { STRING_COMMA_LEN ("nle") },
16423   { STRING_COMMA_LEN ("ord") },
16424   { STRING_COMMA_LEN ("eq_uq") },
16425   { STRING_COMMA_LEN ("nge") },
16426   { STRING_COMMA_LEN ("ngt") },
16427   { STRING_COMMA_LEN ("false") },
16428   { STRING_COMMA_LEN ("neq_oq") },
16429   { STRING_COMMA_LEN ("ge") },
16430   { STRING_COMMA_LEN ("gt") },
16431   { STRING_COMMA_LEN ("true") },
16432   { STRING_COMMA_LEN ("eq_os") },
16433   { STRING_COMMA_LEN ("lt_oq") },
16434   { STRING_COMMA_LEN ("le_oq") },
16435   { STRING_COMMA_LEN ("unord_s") },
16436   { STRING_COMMA_LEN ("neq_us") },
16437   { STRING_COMMA_LEN ("nlt_uq") },
16438   { STRING_COMMA_LEN ("nle_uq") },
16439   { STRING_COMMA_LEN ("ord_s") },
16440   { STRING_COMMA_LEN ("eq_us") },
16441   { STRING_COMMA_LEN ("nge_uq") },
16442   { STRING_COMMA_LEN ("ngt_uq") },
16443   { STRING_COMMA_LEN ("false_os") },
16444   { STRING_COMMA_LEN ("neq_os") },
16445   { STRING_COMMA_LEN ("ge_oq") },
16446   { STRING_COMMA_LEN ("gt_oq") },
16447   { STRING_COMMA_LEN ("true_us") },
16448 };
16449
16450 static void
16451 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16452 {
16453   unsigned int cmp_type;
16454
16455   FETCH_DATA (the_info, codep + 1);
16456   cmp_type = *codep++ & 0xff;
16457   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
16458     {
16459       char suffix [3];
16460       char *p = mnemonicendp - 2;
16461       suffix[0] = p[0];
16462       suffix[1] = p[1];
16463       suffix[2] = '\0';
16464       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
16465       mnemonicendp += vex_cmp_op[cmp_type].len;
16466     }
16467   else
16468     {
16469       /* We have a reserved extension byte.  Output it directly.  */
16470       scratchbuf[0] = '$';
16471       print_operand_value (scratchbuf + 1, 1, cmp_type);
16472       oappend (scratchbuf + intel_syntax);
16473       scratchbuf[0] = '\0';
16474     }
16475 }
16476
16477 static void
16478 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
16479              int sizeflag ATTRIBUTE_UNUSED)
16480 {
16481   unsigned int cmp_type;
16482
16483   if (!vex.evex)
16484     abort ();
16485
16486   FETCH_DATA (the_info, codep + 1);
16487   cmp_type = *codep++ & 0xff;
16488   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
16489      If it's the case, print suffix, otherwise - print the immediate.  */
16490   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
16491       && cmp_type != 3
16492       && cmp_type != 7)
16493     {
16494       char suffix [3];
16495       char *p = mnemonicendp - 2;
16496
16497       /* vpcmp* can have both one- and two-lettered suffix.  */
16498       if (p[0] == 'p')
16499         {
16500           p++;
16501           suffix[0] = p[0];
16502           suffix[1] = '\0';
16503         }
16504       else
16505         {
16506           suffix[0] = p[0];
16507           suffix[1] = p[1];
16508           suffix[2] = '\0';
16509         }
16510
16511       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16512       mnemonicendp += simd_cmp_op[cmp_type].len;
16513     }
16514   else
16515     {
16516       /* We have a reserved extension byte.  Output it directly.  */
16517       scratchbuf[0] = '$';
16518       print_operand_value (scratchbuf + 1, 1, cmp_type);
16519       oappend (scratchbuf + intel_syntax);
16520       scratchbuf[0] = '\0';
16521     }
16522 }
16523
16524 static const struct op pclmul_op[] =
16525 {
16526   { STRING_COMMA_LEN ("lql") },
16527   { STRING_COMMA_LEN ("hql") },
16528   { STRING_COMMA_LEN ("lqh") },
16529   { STRING_COMMA_LEN ("hqh") }
16530 };
16531
16532 static void
16533 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
16534               int sizeflag ATTRIBUTE_UNUSED)
16535 {
16536   unsigned int pclmul_type;
16537
16538   FETCH_DATA (the_info, codep + 1);
16539   pclmul_type = *codep++ & 0xff;
16540   switch (pclmul_type)
16541     {
16542     case 0x10:
16543       pclmul_type = 2;
16544       break;
16545     case 0x11:
16546       pclmul_type = 3;
16547       break;
16548     default:
16549       break;
16550     }
16551   if (pclmul_type < ARRAY_SIZE (pclmul_op))
16552     {
16553       char suffix [4];
16554       char *p = mnemonicendp - 3;
16555       suffix[0] = p[0];
16556       suffix[1] = p[1];
16557       suffix[2] = p[2];
16558       suffix[3] = '\0';
16559       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
16560       mnemonicendp += pclmul_op[pclmul_type].len;
16561     }
16562   else
16563     {
16564       /* We have a reserved extension byte.  Output it directly.  */
16565       scratchbuf[0] = '$';
16566       print_operand_value (scratchbuf + 1, 1, pclmul_type);
16567       oappend (scratchbuf + intel_syntax);
16568       scratchbuf[0] = '\0';
16569     }
16570 }
16571
16572 static void
16573 MOVBE_Fixup (int bytemode, int sizeflag)
16574 {
16575   /* Add proper suffix to "movbe".  */
16576   char *p = mnemonicendp;
16577
16578   switch (bytemode)
16579     {
16580     case v_mode:
16581       if (intel_syntax)
16582         goto skip;
16583
16584       USED_REX (REX_W);
16585       if (sizeflag & SUFFIX_ALWAYS)
16586         {
16587           if (rex & REX_W)
16588             *p++ = 'q';
16589           else
16590             {
16591               if (sizeflag & DFLAG)
16592                 *p++ = 'l';
16593               else
16594                 *p++ = 'w';
16595               used_prefixes |= (prefixes & PREFIX_DATA);
16596             }
16597         }
16598       break;
16599     default:
16600       oappend (INTERNAL_DISASSEMBLER_ERROR);
16601       break;
16602     }
16603   mnemonicendp = p;
16604   *p = '\0';
16605
16606 skip:
16607   OP_M (bytemode, sizeflag);
16608 }
16609
16610 static void
16611 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16612 {
16613   int reg;
16614   const char **names;
16615
16616   /* Skip mod/rm byte.  */
16617   MODRM_CHECK;
16618   codep++;
16619
16620   if (vex.w)
16621     names = names64;
16622   else
16623     names = names32;
16624
16625   reg = modrm.rm;
16626   USED_REX (REX_B);
16627   if (rex & REX_B)
16628     reg += 8;
16629
16630   oappend (names[reg]);
16631 }
16632
16633 static void
16634 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16635 {
16636   const char **names;
16637
16638   if (vex.w)
16639     names = names64;
16640   else
16641     names = names32;
16642
16643   oappend (names[vex.register_specifier]);
16644 }
16645
16646 static void
16647 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16648 {
16649   if (!vex.evex
16650       || bytemode != mask_mode)
16651     abort ();
16652
16653   USED_REX (REX_R);
16654   if ((rex & REX_R) != 0 || !vex.r)
16655     {
16656       BadOp ();
16657       return;
16658     }
16659
16660   oappend (names_mask [modrm.reg]);
16661 }
16662
16663 static void
16664 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16665 {
16666   if (!vex.evex
16667       || (bytemode != evex_rounding_mode
16668           && bytemode != evex_sae_mode))
16669     abort ();
16670   if (modrm.mod == 3 && vex.b)
16671     switch (bytemode)
16672       {
16673       case evex_rounding_mode:
16674         oappend (names_rounding[vex.ll]);
16675         break;
16676       case evex_sae_mode:
16677         oappend ("{sae}");
16678         break;
16679       default:
16680         break;
16681       }
16682 }