1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright (C) 1988-2018 Free Software Foundation, Inc.
4 This file is part of the GNU opcodes library.
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
24 modified by John Hassey (hassey@dg-rtp.dg.com)
25 x86-64 support added by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
28 /* The main tables describing the instructions is essentially a copy
29 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
30 Programmers Manual. Usually, there is a capital letter, followed
31 by a small letter. The capital letter tell the addressing mode,
32 and the small letter tells about the operand size. Refer to
33 the Intel manual for details. */
36 #include "disassemble.h"
38 #include "opcode/i386.h"
39 #include "libiberty.h"
43 static int print_insn (bfd_vma
, disassemble_info
*);
44 static void dofloat (int);
45 static void OP_ST (int, int);
46 static void OP_STi (int, int);
47 static int putop (const char *, int);
48 static void oappend (const char *);
49 static void append_seg (void);
50 static void OP_indirE (int, int);
51 static void print_operand_value (char *, int, bfd_vma
);
52 static void OP_E_register (int, int);
53 static void OP_E_memory (int, int);
54 static void print_displacement (char *, bfd_vma
);
55 static void OP_E (int, int);
56 static void OP_G (int, int);
57 static bfd_vma
get64 (void);
58 static bfd_signed_vma
get32 (void);
59 static bfd_signed_vma
get32s (void);
60 static int get16 (void);
61 static void set_op (bfd_vma
, int);
62 static void OP_Skip_MODRM (int, int);
63 static void OP_REG (int, int);
64 static void OP_IMREG (int, int);
65 static void OP_I (int, int);
66 static void OP_I64 (int, int);
67 static void OP_sI (int, int);
68 static void OP_J (int, int);
69 static void OP_SEG (int, int);
70 static void OP_DIR (int, int);
71 static void OP_OFF (int, int);
72 static void OP_OFF64 (int, int);
73 static void ptr_reg (int, int);
74 static void OP_ESreg (int, int);
75 static void OP_DSreg (int, int);
76 static void OP_C (int, int);
77 static void OP_D (int, int);
78 static void OP_T (int, int);
79 static void OP_R (int, int);
80 static void OP_MMX (int, int);
81 static void OP_XMM (int, int);
82 static void OP_EM (int, int);
83 static void OP_EX (int, int);
84 static void OP_EMC (int,int);
85 static void OP_MXC (int,int);
86 static void OP_MS (int, int);
87 static void OP_XS (int, int);
88 static void OP_M (int, int);
89 static void OP_VEX (int, int);
90 static void OP_EX_Vex (int, int);
91 static void OP_EX_VexW (int, int);
92 static void OP_EX_VexImmW (int, int);
93 static void OP_XMM_Vex (int, int);
94 static void OP_XMM_VexW (int, int);
95 static void OP_Rounding (int, int);
96 static void OP_REG_VexI4 (int, int);
97 static void PCLMUL_Fixup (int, int);
98 static void VZERO_Fixup (int, int);
99 static void VCMP_Fixup (int, int);
100 static void VPCMP_Fixup (int, int);
101 static void VPCOM_Fixup (int, int);
102 static void OP_0f07 (int, int);
103 static void OP_Monitor (int, int);
104 static void OP_Mwait (int, int);
105 static void OP_Mwaitx (int, int);
106 static void NOP_Fixup1 (int, int);
107 static void NOP_Fixup2 (int, int);
108 static void OP_3DNowSuffix (int, int);
109 static void CMP_Fixup (int, int);
110 static void BadOp (void);
111 static void REP_Fixup (int, int);
112 static void BND_Fixup (int, int);
113 static void NOTRACK_Fixup (int, int);
114 static void HLE_Fixup1 (int, int);
115 static void HLE_Fixup2 (int, int);
116 static void HLE_Fixup3 (int, int);
117 static void CMPXCHG8B_Fixup (int, int);
118 static void XMM_Fixup (int, int);
119 static void CRC32_Fixup (int, int);
120 static void FXSAVE_Fixup (int, int);
121 static void PCMPESTR_Fixup (int, int);
122 static void OP_LWPCB_E (int, int);
123 static void OP_LWP_E (int, int);
124 static void OP_Vex_2src_1 (int, int);
125 static void OP_Vex_2src_2 (int, int);
127 static void MOVBE_Fixup (int, int);
129 static void OP_Mask (int, int);
132 /* Points to first byte not fetched. */
133 bfd_byte
*max_fetched
;
134 bfd_byte the_buffer
[MAX_MNEM_SIZE
];
137 OPCODES_SIGJMP_BUF bailout
;
147 enum address_mode address_mode
;
149 /* Flags for the prefixes for the current instruction. See below. */
152 /* REX prefix the current instruction. See below. */
154 /* Bits of REX we've already used. */
156 /* REX bits in original REX prefix ignored. */
157 static int rex_ignored
;
158 /* Mark parts used in the REX prefix. When we are testing for
159 empty prefix (for 8bit register REX extension), just mask it
160 out. Otherwise test for REX bit is excuse for existence of REX
161 only in case value is nonzero. */
162 #define USED_REX(value) \
167 rex_used |= (value) | REX_OPCODE; \
170 rex_used |= REX_OPCODE; \
173 /* Flags for prefixes which we somehow handled when printing the
174 current instruction. */
175 static int used_prefixes
;
177 /* Flags stored in PREFIXES. */
178 #define PREFIX_REPZ 1
179 #define PREFIX_REPNZ 2
180 #define PREFIX_LOCK 4
182 #define PREFIX_SS 0x10
183 #define PREFIX_DS 0x20
184 #define PREFIX_ES 0x40
185 #define PREFIX_FS 0x80
186 #define PREFIX_GS 0x100
187 #define PREFIX_DATA 0x200
188 #define PREFIX_ADDR 0x400
189 #define PREFIX_FWAIT 0x800
191 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
192 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
194 #define FETCH_DATA(info, addr) \
195 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
196 ? 1 : fetch_data ((info), (addr)))
199 fetch_data (struct disassemble_info
*info
, bfd_byte
*addr
)
202 struct dis_private
*priv
= (struct dis_private
*) info
->private_data
;
203 bfd_vma start
= priv
->insn_start
+ (priv
->max_fetched
- priv
->the_buffer
);
205 if (addr
<= priv
->the_buffer
+ MAX_MNEM_SIZE
)
206 status
= (*info
->read_memory_func
) (start
,
208 addr
- priv
->max_fetched
,
214 /* If we did manage to read at least one byte, then
215 print_insn_i386 will do something sensible. Otherwise, print
216 an error. We do that here because this is where we know
218 if (priv
->max_fetched
== priv
->the_buffer
)
219 (*info
->memory_error_func
) (status
, start
, info
);
220 OPCODES_SIGLONGJMP (priv
->bailout
, 1);
223 priv
->max_fetched
= addr
;
227 /* Possible values for prefix requirement. */
228 #define PREFIX_IGNORED_SHIFT 16
229 #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
230 #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
231 #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
232 #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
233 #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
235 /* Opcode prefixes. */
236 #define PREFIX_OPCODE (PREFIX_REPZ \
240 /* Prefixes ignored. */
241 #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \
242 | PREFIX_IGNORED_REPNZ \
243 | PREFIX_IGNORED_DATA)
245 #define XX { NULL, 0 }
246 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
248 #define Eb { OP_E, b_mode }
249 #define Ebnd { OP_E, bnd_mode }
250 #define EbS { OP_E, b_swap_mode }
251 #define EbndS { OP_E, bnd_swap_mode }
252 #define Ev { OP_E, v_mode }
253 #define Eva { OP_E, va_mode }
254 #define Ev_bnd { OP_E, v_bnd_mode }
255 #define EvS { OP_E, v_swap_mode }
256 #define Ed { OP_E, d_mode }
257 #define Edq { OP_E, dq_mode }
258 #define Edqw { OP_E, dqw_mode }
259 #define Edqb { OP_E, dqb_mode }
260 #define Edb { OP_E, db_mode }
261 #define Edw { OP_E, dw_mode }
262 #define Edqd { OP_E, dqd_mode }
263 #define Eq { OP_E, q_mode }
264 #define indirEv { OP_indirE, indir_v_mode }
265 #define indirEp { OP_indirE, f_mode }
266 #define stackEv { OP_E, stack_v_mode }
267 #define Em { OP_E, m_mode }
268 #define Ew { OP_E, w_mode }
269 #define M { OP_M, 0 } /* lea, lgdt, etc. */
270 #define Ma { OP_M, a_mode }
271 #define Mb { OP_M, b_mode }
272 #define Md { OP_M, d_mode }
273 #define Mo { OP_M, o_mode }
274 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
275 #define Mq { OP_M, q_mode }
276 #define Mx { OP_M, x_mode }
277 #define Mxmm { OP_M, xmm_mode }
278 #define Gb { OP_G, b_mode }
279 #define Gbnd { OP_G, bnd_mode }
280 #define Gv { OP_G, v_mode }
281 #define Gd { OP_G, d_mode }
282 #define Gdq { OP_G, dq_mode }
283 #define Gm { OP_G, m_mode }
284 #define Gva { OP_G, va_mode }
285 #define Gw { OP_G, w_mode }
286 #define Rd { OP_R, d_mode }
287 #define Rdq { OP_R, dq_mode }
288 #define Rm { OP_R, m_mode }
289 #define Ib { OP_I, b_mode }
290 #define sIb { OP_sI, b_mode } /* sign extened byte */
291 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
292 #define Iv { OP_I, v_mode }
293 #define sIv { OP_sI, v_mode }
294 #define Iq { OP_I, q_mode }
295 #define Iv64 { OP_I64, v_mode }
296 #define Iw { OP_I, w_mode }
297 #define I1 { OP_I, const_1_mode }
298 #define Jb { OP_J, b_mode }
299 #define Jv { OP_J, v_mode }
300 #define Cm { OP_C, m_mode }
301 #define Dm { OP_D, m_mode }
302 #define Td { OP_T, d_mode }
303 #define Skip_MODRM { OP_Skip_MODRM, 0 }
305 #define RMeAX { OP_REG, eAX_reg }
306 #define RMeBX { OP_REG, eBX_reg }
307 #define RMeCX { OP_REG, eCX_reg }
308 #define RMeDX { OP_REG, eDX_reg }
309 #define RMeSP { OP_REG, eSP_reg }
310 #define RMeBP { OP_REG, eBP_reg }
311 #define RMeSI { OP_REG, eSI_reg }
312 #define RMeDI { OP_REG, eDI_reg }
313 #define RMrAX { OP_REG, rAX_reg }
314 #define RMrBX { OP_REG, rBX_reg }
315 #define RMrCX { OP_REG, rCX_reg }
316 #define RMrDX { OP_REG, rDX_reg }
317 #define RMrSP { OP_REG, rSP_reg }
318 #define RMrBP { OP_REG, rBP_reg }
319 #define RMrSI { OP_REG, rSI_reg }
320 #define RMrDI { OP_REG, rDI_reg }
321 #define RMAL { OP_REG, al_reg }
322 #define RMCL { OP_REG, cl_reg }
323 #define RMDL { OP_REG, dl_reg }
324 #define RMBL { OP_REG, bl_reg }
325 #define RMAH { OP_REG, ah_reg }
326 #define RMCH { OP_REG, ch_reg }
327 #define RMDH { OP_REG, dh_reg }
328 #define RMBH { OP_REG, bh_reg }
329 #define RMAX { OP_REG, ax_reg }
330 #define RMDX { OP_REG, dx_reg }
332 #define eAX { OP_IMREG, eAX_reg }
333 #define eBX { OP_IMREG, eBX_reg }
334 #define eCX { OP_IMREG, eCX_reg }
335 #define eDX { OP_IMREG, eDX_reg }
336 #define eSP { OP_IMREG, eSP_reg }
337 #define eBP { OP_IMREG, eBP_reg }
338 #define eSI { OP_IMREG, eSI_reg }
339 #define eDI { OP_IMREG, eDI_reg }
340 #define AL { OP_IMREG, al_reg }
341 #define CL { OP_IMREG, cl_reg }
342 #define DL { OP_IMREG, dl_reg }
343 #define BL { OP_IMREG, bl_reg }
344 #define AH { OP_IMREG, ah_reg }
345 #define CH { OP_IMREG, ch_reg }
346 #define DH { OP_IMREG, dh_reg }
347 #define BH { OP_IMREG, bh_reg }
348 #define AX { OP_IMREG, ax_reg }
349 #define DX { OP_IMREG, dx_reg }
350 #define zAX { OP_IMREG, z_mode_ax_reg }
351 #define indirDX { OP_IMREG, indir_dx_reg }
353 #define Sw { OP_SEG, w_mode }
354 #define Sv { OP_SEG, v_mode }
355 #define Ap { OP_DIR, 0 }
356 #define Ob { OP_OFF64, b_mode }
357 #define Ov { OP_OFF64, v_mode }
358 #define Xb { OP_DSreg, eSI_reg }
359 #define Xv { OP_DSreg, eSI_reg }
360 #define Xz { OP_DSreg, eSI_reg }
361 #define Yb { OP_ESreg, eDI_reg }
362 #define Yv { OP_ESreg, eDI_reg }
363 #define DSBX { OP_DSreg, eBX_reg }
365 #define es { OP_REG, es_reg }
366 #define ss { OP_REG, ss_reg }
367 #define cs { OP_REG, cs_reg }
368 #define ds { OP_REG, ds_reg }
369 #define fs { OP_REG, fs_reg }
370 #define gs { OP_REG, gs_reg }
372 #define MX { OP_MMX, 0 }
373 #define XM { OP_XMM, 0 }
374 #define XMScalar { OP_XMM, scalar_mode }
375 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
376 #define XMM { OP_XMM, xmm_mode }
377 #define XMxmmq { OP_XMM, xmmq_mode }
378 #define EM { OP_EM, v_mode }
379 #define EMS { OP_EM, v_swap_mode }
380 #define EMd { OP_EM, d_mode }
381 #define EMx { OP_EM, x_mode }
382 #define EXbScalar { OP_EX, b_scalar_mode }
383 #define EXw { OP_EX, w_mode }
384 #define EXwScalar { OP_EX, w_scalar_mode }
385 #define EXd { OP_EX, d_mode }
386 #define EXdScalar { OP_EX, d_scalar_mode }
387 #define EXdS { OP_EX, d_swap_mode }
388 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
389 #define EXq { OP_EX, q_mode }
390 #define EXqScalar { OP_EX, q_scalar_mode }
391 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
392 #define EXqS { OP_EX, q_swap_mode }
393 #define EXx { OP_EX, x_mode }
394 #define EXxS { OP_EX, x_swap_mode }
395 #define EXxmm { OP_EX, xmm_mode }
396 #define EXymm { OP_EX, ymm_mode }
397 #define EXxmmq { OP_EX, xmmq_mode }
398 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
399 #define EXxmm_mb { OP_EX, xmm_mb_mode }
400 #define EXxmm_mw { OP_EX, xmm_mw_mode }
401 #define EXxmm_md { OP_EX, xmm_md_mode }
402 #define EXxmm_mq { OP_EX, xmm_mq_mode }
403 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
404 #define EXxmmdw { OP_EX, xmmdw_mode }
405 #define EXxmmqd { OP_EX, xmmqd_mode }
406 #define EXymmq { OP_EX, ymmq_mode }
407 #define EXVexWdq { OP_EX, vex_w_dq_mode }
408 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
409 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
410 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
411 #define MS { OP_MS, v_mode }
412 #define XS { OP_XS, v_mode }
413 #define EMCq { OP_EMC, q_mode }
414 #define MXC { OP_MXC, 0 }
415 #define OPSUF { OP_3DNowSuffix, 0 }
416 #define CMP { CMP_Fixup, 0 }
417 #define XMM0 { XMM_Fixup, 0 }
418 #define FXSAVE { FXSAVE_Fixup, 0 }
419 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
420 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
422 #define Vex { OP_VEX, vex_mode }
423 #define VexScalar { OP_VEX, vex_scalar_mode }
424 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
425 #define Vex128 { OP_VEX, vex128_mode }
426 #define Vex256 { OP_VEX, vex256_mode }
427 #define VexGdq { OP_VEX, dq_mode }
428 #define EXdVex { OP_EX_Vex, d_mode }
429 #define EXdVexS { OP_EX_Vex, d_swap_mode }
430 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
431 #define EXqVex { OP_EX_Vex, q_mode }
432 #define EXqVexS { OP_EX_Vex, q_swap_mode }
433 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
434 #define EXVexW { OP_EX_VexW, x_mode }
435 #define EXdVexW { OP_EX_VexW, d_mode }
436 #define EXqVexW { OP_EX_VexW, q_mode }
437 #define EXVexImmW { OP_EX_VexImmW, x_mode }
438 #define XMVex { OP_XMM_Vex, 0 }
439 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
440 #define XMVexW { OP_XMM_VexW, 0 }
441 #define XMVexI4 { OP_REG_VexI4, x_mode }
442 #define PCLMUL { PCLMUL_Fixup, 0 }
443 #define VZERO { VZERO_Fixup, 0 }
444 #define VCMP { VCMP_Fixup, 0 }
445 #define VPCMP { VPCMP_Fixup, 0 }
446 #define VPCOM { VPCOM_Fixup, 0 }
448 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
449 #define EXxEVexS { OP_Rounding, evex_sae_mode }
451 #define XMask { OP_Mask, mask_mode }
452 #define MaskG { OP_G, mask_mode }
453 #define MaskE { OP_E, mask_mode }
454 #define MaskBDE { OP_E, mask_bd_mode }
455 #define MaskR { OP_R, mask_mode }
456 #define MaskVex { OP_VEX, mask_mode }
458 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
459 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
460 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
461 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
463 /* Used handle "rep" prefix for string instructions. */
464 #define Xbr { REP_Fixup, eSI_reg }
465 #define Xvr { REP_Fixup, eSI_reg }
466 #define Ybr { REP_Fixup, eDI_reg }
467 #define Yvr { REP_Fixup, eDI_reg }
468 #define Yzr { REP_Fixup, eDI_reg }
469 #define indirDXr { REP_Fixup, indir_dx_reg }
470 #define ALr { REP_Fixup, al_reg }
471 #define eAXr { REP_Fixup, eAX_reg }
473 /* Used handle HLE prefix for lockable instructions. */
474 #define Ebh1 { HLE_Fixup1, b_mode }
475 #define Evh1 { HLE_Fixup1, v_mode }
476 #define Ebh2 { HLE_Fixup2, b_mode }
477 #define Evh2 { HLE_Fixup2, v_mode }
478 #define Ebh3 { HLE_Fixup3, b_mode }
479 #define Evh3 { HLE_Fixup3, v_mode }
481 #define BND { BND_Fixup, 0 }
482 #define NOTRACK { NOTRACK_Fixup, 0 }
484 #define cond_jump_flag { NULL, cond_jump_mode }
485 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
487 /* bits in sizeflag */
488 #define SUFFIX_ALWAYS 4
496 /* byte operand with operand swapped */
498 /* byte operand, sign extend like 'T' suffix */
500 /* operand size depends on prefixes */
502 /* operand size depends on prefixes with operand swapped */
504 /* operand size depends on address prefix */
508 /* double word operand */
510 /* double word operand with operand swapped */
512 /* quad word operand */
514 /* quad word operand with operand swapped */
516 /* ten-byte operand */
518 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
519 broadcast enabled. */
521 /* Similar to x_mode, but with different EVEX mem shifts. */
523 /* Similar to x_mode, but with disabled broadcast. */
525 /* Similar to x_mode, but with operands swapped and disabled broadcast
528 /* 16-byte XMM operand */
530 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
531 memory operand (depending on vector length). Broadcast isn't
534 /* Same as xmmq_mode, but broadcast is allowed. */
535 evex_half_bcst_xmmq_mode
,
536 /* XMM register or byte memory operand */
538 /* XMM register or word memory operand */
540 /* XMM register or double word memory operand */
542 /* XMM register or quad word memory operand */
544 /* XMM register or double/quad word memory operand, depending on
547 /* 16-byte XMM, word, double word or quad word operand. */
549 /* 16-byte XMM, double word, quad word operand or xmm word operand. */
551 /* 32-byte YMM operand */
553 /* quad word, ymmword or zmmword memory operand. */
555 /* 32-byte YMM or 16-byte word operand */
557 /* d_mode in 32bit, q_mode in 64bit mode. */
559 /* pair of v_mode operands */
564 /* operand size depends on REX prefixes. */
566 /* registers like dq_mode, memory like w_mode. */
570 /* bounds operand with operand swapped */
572 /* 4- or 6-byte pointer operand */
575 /* v_mode for indirect branch opcodes. */
577 /* v_mode for stack-related opcodes. */
579 /* non-quad operand size depends on prefixes */
581 /* 16-byte operand */
583 /* registers like dq_mode, memory like b_mode. */
585 /* registers like d_mode, memory like b_mode. */
587 /* registers like d_mode, memory like w_mode. */
589 /* registers like dq_mode, memory like d_mode. */
591 /* normal vex mode */
593 /* 128bit vex mode */
595 /* 256bit vex mode */
597 /* operand size depends on the VEX.W bit. */
600 /* Similar to vex_w_dq_mode, with VSIB dword indices. */
601 vex_vsib_d_w_dq_mode
,
602 /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */
604 /* Similar to vex_w_dq_mode, with VSIB qword indices. */
605 vex_vsib_q_w_dq_mode
,
606 /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */
609 /* scalar, ignore vector length. */
611 /* like b_mode, ignore vector length. */
613 /* like w_mode, ignore vector length. */
615 /* like d_mode, ignore vector length. */
617 /* like d_swap_mode, ignore vector length. */
619 /* like q_mode, ignore vector length. */
621 /* like q_swap_mode, ignore vector length. */
623 /* like vex_mode, ignore vector length. */
625 /* like vex_w_dq_mode, ignore vector length. */
626 vex_scalar_w_dq_mode
,
628 /* Static rounding. */
630 /* Supress all exceptions. */
633 /* Mask register operand. */
635 /* Mask register operand. */
702 #define FLOAT NULL, { { NULL, FLOATCODE } }, 0
704 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0
705 #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P
706 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
707 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
708 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
709 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
710 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
711 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
712 #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
713 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
714 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
715 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
716 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
717 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
718 #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I))
844 MOD_VEX_0F12_PREFIX_0
,
846 MOD_VEX_0F16_PREFIX_0
,
849 MOD_VEX_W_0_0F41_P_0_LEN_1
,
850 MOD_VEX_W_1_0F41_P_0_LEN_1
,
851 MOD_VEX_W_0_0F41_P_2_LEN_1
,
852 MOD_VEX_W_1_0F41_P_2_LEN_1
,
853 MOD_VEX_W_0_0F42_P_0_LEN_1
,
854 MOD_VEX_W_1_0F42_P_0_LEN_1
,
855 MOD_VEX_W_0_0F42_P_2_LEN_1
,
856 MOD_VEX_W_1_0F42_P_2_LEN_1
,
857 MOD_VEX_W_0_0F44_P_0_LEN_1
,
858 MOD_VEX_W_1_0F44_P_0_LEN_1
,
859 MOD_VEX_W_0_0F44_P_2_LEN_1
,
860 MOD_VEX_W_1_0F44_P_2_LEN_1
,
861 MOD_VEX_W_0_0F45_P_0_LEN_1
,
862 MOD_VEX_W_1_0F45_P_0_LEN_1
,
863 MOD_VEX_W_0_0F45_P_2_LEN_1
,
864 MOD_VEX_W_1_0F45_P_2_LEN_1
,
865 MOD_VEX_W_0_0F46_P_0_LEN_1
,
866 MOD_VEX_W_1_0F46_P_0_LEN_1
,
867 MOD_VEX_W_0_0F46_P_2_LEN_1
,
868 MOD_VEX_W_1_0F46_P_2_LEN_1
,
869 MOD_VEX_W_0_0F47_P_0_LEN_1
,
870 MOD_VEX_W_1_0F47_P_0_LEN_1
,
871 MOD_VEX_W_0_0F47_P_2_LEN_1
,
872 MOD_VEX_W_1_0F47_P_2_LEN_1
,
873 MOD_VEX_W_0_0F4A_P_0_LEN_1
,
874 MOD_VEX_W_1_0F4A_P_0_LEN_1
,
875 MOD_VEX_W_0_0F4A_P_2_LEN_1
,
876 MOD_VEX_W_1_0F4A_P_2_LEN_1
,
877 MOD_VEX_W_0_0F4B_P_0_LEN_1
,
878 MOD_VEX_W_1_0F4B_P_0_LEN_1
,
879 MOD_VEX_W_0_0F4B_P_2_LEN_1
,
891 MOD_VEX_W_0_0F91_P_0_LEN_0
,
892 MOD_VEX_W_1_0F91_P_0_LEN_0
,
893 MOD_VEX_W_0_0F91_P_2_LEN_0
,
894 MOD_VEX_W_1_0F91_P_2_LEN_0
,
895 MOD_VEX_W_0_0F92_P_0_LEN_0
,
896 MOD_VEX_W_0_0F92_P_2_LEN_0
,
897 MOD_VEX_W_0_0F92_P_3_LEN_0
,
898 MOD_VEX_W_1_0F92_P_3_LEN_0
,
899 MOD_VEX_W_0_0F93_P_0_LEN_0
,
900 MOD_VEX_W_0_0F93_P_2_LEN_0
,
901 MOD_VEX_W_0_0F93_P_3_LEN_0
,
902 MOD_VEX_W_1_0F93_P_3_LEN_0
,
903 MOD_VEX_W_0_0F98_P_0_LEN_0
,
904 MOD_VEX_W_1_0F98_P_0_LEN_0
,
905 MOD_VEX_W_0_0F98_P_2_LEN_0
,
906 MOD_VEX_W_1_0F98_P_2_LEN_0
,
907 MOD_VEX_W_0_0F99_P_0_LEN_0
,
908 MOD_VEX_W_1_0F99_P_0_LEN_0
,
909 MOD_VEX_W_0_0F99_P_2_LEN_0
,
910 MOD_VEX_W_1_0F99_P_2_LEN_0
,
913 MOD_VEX_0FD7_PREFIX_2
,
914 MOD_VEX_0FE7_PREFIX_2
,
915 MOD_VEX_0FF0_PREFIX_3
,
916 MOD_VEX_0F381A_PREFIX_2
,
917 MOD_VEX_0F382A_PREFIX_2
,
918 MOD_VEX_0F382C_PREFIX_2
,
919 MOD_VEX_0F382D_PREFIX_2
,
920 MOD_VEX_0F382E_PREFIX_2
,
921 MOD_VEX_0F382F_PREFIX_2
,
922 MOD_VEX_0F385A_PREFIX_2
,
923 MOD_VEX_0F388C_PREFIX_2
,
924 MOD_VEX_0F388E_PREFIX_2
,
925 MOD_VEX_W_0_0F3A30_P_2_LEN_0
,
926 MOD_VEX_W_1_0F3A30_P_2_LEN_0
,
927 MOD_VEX_W_0_0F3A31_P_2_LEN_0
,
928 MOD_VEX_W_1_0F3A31_P_2_LEN_0
,
929 MOD_VEX_W_0_0F3A32_P_2_LEN_0
,
930 MOD_VEX_W_1_0F3A32_P_2_LEN_0
,
931 MOD_VEX_W_0_0F3A33_P_2_LEN_0
,
932 MOD_VEX_W_1_0F3A33_P_2_LEN_0
,
934 MOD_EVEX_0F10_PREFIX_1
,
935 MOD_EVEX_0F10_PREFIX_3
,
936 MOD_EVEX_0F11_PREFIX_1
,
937 MOD_EVEX_0F11_PREFIX_3
,
938 MOD_EVEX_0F12_PREFIX_0
,
939 MOD_EVEX_0F16_PREFIX_0
,
940 MOD_EVEX_0F38C6_REG_1
,
941 MOD_EVEX_0F38C6_REG_2
,
942 MOD_EVEX_0F38C6_REG_5
,
943 MOD_EVEX_0F38C6_REG_6
,
944 MOD_EVEX_0F38C7_REG_1
,
945 MOD_EVEX_0F38C7_REG_2
,
946 MOD_EVEX_0F38C7_REG_5
,
947 MOD_EVEX_0F38C7_REG_6
968 PREFIX_MOD_0_0F01_REG_5
,
969 PREFIX_MOD_3_0F01_REG_5_RM_0
,
970 PREFIX_MOD_3_0F01_REG_5_RM_2
,
1016 PREFIX_MOD_0_0FAE_REG_4
,
1017 PREFIX_MOD_3_0FAE_REG_4
,
1018 PREFIX_MOD_0_0FAE_REG_5
,
1019 PREFIX_MOD_3_0FAE_REG_5
,
1020 PREFIX_MOD_0_0FAE_REG_6
,
1021 PREFIX_MOD_1_0FAE_REG_6
,
1028 PREFIX_MOD_0_0FC7_REG_6
,
1029 PREFIX_MOD_3_0FC7_REG_6
,
1030 PREFIX_MOD_3_0FC7_REG_7
,
1160 PREFIX_VEX_0F71_REG_2
,
1161 PREFIX_VEX_0F71_REG_4
,
1162 PREFIX_VEX_0F71_REG_6
,
1163 PREFIX_VEX_0F72_REG_2
,
1164 PREFIX_VEX_0F72_REG_4
,
1165 PREFIX_VEX_0F72_REG_6
,
1166 PREFIX_VEX_0F73_REG_2
,
1167 PREFIX_VEX_0F73_REG_3
,
1168 PREFIX_VEX_0F73_REG_6
,
1169 PREFIX_VEX_0F73_REG_7
,
1342 PREFIX_VEX_0F38F3_REG_1
,
1343 PREFIX_VEX_0F38F3_REG_2
,
1344 PREFIX_VEX_0F38F3_REG_3
,
1463 PREFIX_EVEX_0F71_REG_2
,
1464 PREFIX_EVEX_0F71_REG_4
,
1465 PREFIX_EVEX_0F71_REG_6
,
1466 PREFIX_EVEX_0F72_REG_0
,
1467 PREFIX_EVEX_0F72_REG_1
,
1468 PREFIX_EVEX_0F72_REG_2
,
1469 PREFIX_EVEX_0F72_REG_4
,
1470 PREFIX_EVEX_0F72_REG_6
,
1471 PREFIX_EVEX_0F73_REG_2
,
1472 PREFIX_EVEX_0F73_REG_3
,
1473 PREFIX_EVEX_0F73_REG_6
,
1474 PREFIX_EVEX_0F73_REG_7
,
1670 PREFIX_EVEX_0F38C6_REG_1
,
1671 PREFIX_EVEX_0F38C6_REG_2
,
1672 PREFIX_EVEX_0F38C6_REG_5
,
1673 PREFIX_EVEX_0F38C6_REG_6
,
1674 PREFIX_EVEX_0F38C7_REG_1
,
1675 PREFIX_EVEX_0F38C7_REG_2
,
1676 PREFIX_EVEX_0F38C7_REG_5
,
1677 PREFIX_EVEX_0F38C7_REG_6
,
1779 THREE_BYTE_0F38
= 0,
1806 VEX_LEN_0F10_P_1
= 0,
1810 VEX_LEN_0F12_P_0_M_0
,
1811 VEX_LEN_0F12_P_0_M_1
,
1814 VEX_LEN_0F16_P_0_M_0
,
1815 VEX_LEN_0F16_P_0_M_1
,
1879 VEX_LEN_0FAE_R_2_M_0
,
1880 VEX_LEN_0FAE_R_3_M_0
,
1889 VEX_LEN_0F381A_P_2_M_0
,
1892 VEX_LEN_0F385A_P_2_M_0
,
1895 VEX_LEN_0F38F3_R_1_P_0
,
1896 VEX_LEN_0F38F3_R_2_P_0
,
1897 VEX_LEN_0F38F3_R_3_P_0
,
1942 VEX_LEN_0FXOP_08_CC
,
1943 VEX_LEN_0FXOP_08_CD
,
1944 VEX_LEN_0FXOP_08_CE
,
1945 VEX_LEN_0FXOP_08_CF
,
1946 VEX_LEN_0FXOP_08_EC
,
1947 VEX_LEN_0FXOP_08_ED
,
1948 VEX_LEN_0FXOP_08_EE
,
1949 VEX_LEN_0FXOP_08_EF
,
1950 VEX_LEN_0FXOP_09_80
,
1984 VEX_W_0F41_P_0_LEN_1
,
1985 VEX_W_0F41_P_2_LEN_1
,
1986 VEX_W_0F42_P_0_LEN_1
,
1987 VEX_W_0F42_P_2_LEN_1
,
1988 VEX_W_0F44_P_0_LEN_0
,
1989 VEX_W_0F44_P_2_LEN_0
,
1990 VEX_W_0F45_P_0_LEN_1
,
1991 VEX_W_0F45_P_2_LEN_1
,
1992 VEX_W_0F46_P_0_LEN_1
,
1993 VEX_W_0F46_P_2_LEN_1
,
1994 VEX_W_0F47_P_0_LEN_1
,
1995 VEX_W_0F47_P_2_LEN_1
,
1996 VEX_W_0F4A_P_0_LEN_1
,
1997 VEX_W_0F4A_P_2_LEN_1
,
1998 VEX_W_0F4B_P_0_LEN_1
,
1999 VEX_W_0F4B_P_2_LEN_1
,
2079 VEX_W_0F90_P_0_LEN_0
,
2080 VEX_W_0F90_P_2_LEN_0
,
2081 VEX_W_0F91_P_0_LEN_0
,
2082 VEX_W_0F91_P_2_LEN_0
,
2083 VEX_W_0F92_P_0_LEN_0
,
2084 VEX_W_0F92_P_2_LEN_0
,
2085 VEX_W_0F92_P_3_LEN_0
,
2086 VEX_W_0F93_P_0_LEN_0
,
2087 VEX_W_0F93_P_2_LEN_0
,
2088 VEX_W_0F93_P_3_LEN_0
,
2089 VEX_W_0F98_P_0_LEN_0
,
2090 VEX_W_0F98_P_2_LEN_0
,
2091 VEX_W_0F99_P_0_LEN_0
,
2092 VEX_W_0F99_P_2_LEN_0
,
2171 VEX_W_0F381A_P_2_M_0
,
2183 VEX_W_0F382A_P_2_M_0
,
2185 VEX_W_0F382C_P_2_M_0
,
2186 VEX_W_0F382D_P_2_M_0
,
2187 VEX_W_0F382E_P_2_M_0
,
2188 VEX_W_0F382F_P_2_M_0
,
2210 VEX_W_0F385A_P_2_M_0
,
2235 VEX_W_0F3A30_P_2_LEN_0
,
2236 VEX_W_0F3A31_P_2_LEN_0
,
2237 VEX_W_0F3A32_P_2_LEN_0
,
2238 VEX_W_0F3A33_P_2_LEN_0
,
2257 EVEX_W_0F10_P_1_M_0
,
2258 EVEX_W_0F10_P_1_M_1
,
2260 EVEX_W_0F10_P_3_M_0
,
2261 EVEX_W_0F10_P_3_M_1
,
2263 EVEX_W_0F11_P_1_M_0
,
2264 EVEX_W_0F11_P_1_M_1
,
2266 EVEX_W_0F11_P_3_M_0
,
2267 EVEX_W_0F11_P_3_M_1
,
2268 EVEX_W_0F12_P_0_M_0
,
2269 EVEX_W_0F12_P_0_M_1
,
2279 EVEX_W_0F16_P_0_M_0
,
2280 EVEX_W_0F16_P_0_M_1
,
2351 EVEX_W_0F72_R_2_P_2
,
2352 EVEX_W_0F72_R_6_P_2
,
2353 EVEX_W_0F73_R_2_P_2
,
2354 EVEX_W_0F73_R_6_P_2
,
2462 EVEX_W_0F38C7_R_1_P_2
,
2463 EVEX_W_0F38C7_R_2_P_2
,
2464 EVEX_W_0F38C7_R_5_P_2
,
2465 EVEX_W_0F38C7_R_6_P_2
,
2506 typedef void (*op_rtn
) (int bytemode
, int sizeflag
);
2515 unsigned int prefix_requirement
;
2518 /* Upper case letters in the instruction names here are macros.
2519 'A' => print 'b' if no register operands or suffix_always is true
2520 'B' => print 'b' if suffix_always is true
2521 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2523 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2524 suffix_always is true
2525 'E' => print 'e' if 32-bit form of jcxz
2526 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2527 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2528 'H' => print ",pt" or ",pn" branch hint
2529 'I' => honor following macro letter even in Intel mode (implemented only
2530 for some of the macro letters)
2532 'K' => print 'd' or 'q' if rex prefix is present.
2533 'L' => print 'l' if suffix_always is true
2534 'M' => print 'r' if intel_mnemonic is false.
2535 'N' => print 'n' if instruction has no wait "prefix"
2536 'O' => print 'd' or 'o' (or 'q' in Intel mode)
2537 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2538 or suffix_always is true. print 'q' if rex prefix is present.
2539 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2541 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2542 'S' => print 'w', 'l' or 'q' if suffix_always is true
2543 'T' => print 'q' in 64bit mode if instruction has no operand size
2544 prefix and behave as 'P' otherwise
2545 'U' => print 'q' in 64bit mode if instruction has no operand size
2546 prefix and behave as 'Q' otherwise
2547 'V' => print 'q' in 64bit mode if instruction has no operand size
2548 prefix and behave as 'S' otherwise
2549 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2550 'X' => print 's', 'd' depending on data16 prefix (for XMM)
2552 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2553 '!' => change condition from true to false or from false to true.
2554 '%' => add 1 upper case letter to the macro.
2555 '^' => print 'w' or 'l' depending on operand size prefix or
2556 suffix_always is true (lcall/ljmp).
2557 '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2558 on operand size prefix.
2559 '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2560 has no operand size prefix for AMD64 ISA, behave as 'P'
2563 2 upper case letter macros:
2564 "XY" => print 'x' or 'y' if suffix_always is true or no register
2565 operands and no broadcast.
2566 "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2567 register operands and no broadcast.
2568 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2569 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2570 or suffix_always is true
2571 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2572 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2573 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2574 "LW" => print 'd', 'q' depending on the VEX.W bit
2575 "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2576 an operand size prefix, or suffix_always is true. print
2577 'q' if rex prefix is present.
2579 Many of the above letters print nothing in Intel mode. See "putop"
2582 Braces '{' and '}', and vertical bars '|', indicate alternative
2583 mnemonic strings for AT&T and Intel. */
2585 static const struct dis386 dis386
[] = {
2587 { "addB", { Ebh1
, Gb
}, 0 },
2588 { "addS", { Evh1
, Gv
}, 0 },
2589 { "addB", { Gb
, EbS
}, 0 },
2590 { "addS", { Gv
, EvS
}, 0 },
2591 { "addB", { AL
, Ib
}, 0 },
2592 { "addS", { eAX
, Iv
}, 0 },
2593 { X86_64_TABLE (X86_64_06
) },
2594 { X86_64_TABLE (X86_64_07
) },
2596 { "orB", { Ebh1
, Gb
}, 0 },
2597 { "orS", { Evh1
, Gv
}, 0 },
2598 { "orB", { Gb
, EbS
}, 0 },
2599 { "orS", { Gv
, EvS
}, 0 },
2600 { "orB", { AL
, Ib
}, 0 },
2601 { "orS", { eAX
, Iv
}, 0 },
2602 { X86_64_TABLE (X86_64_0D
) },
2603 { Bad_Opcode
}, /* 0x0f extended opcode escape */
2605 { "adcB", { Ebh1
, Gb
}, 0 },
2606 { "adcS", { Evh1
, Gv
}, 0 },
2607 { "adcB", { Gb
, EbS
}, 0 },
2608 { "adcS", { Gv
, EvS
}, 0 },
2609 { "adcB", { AL
, Ib
}, 0 },
2610 { "adcS", { eAX
, Iv
}, 0 },
2611 { X86_64_TABLE (X86_64_16
) },
2612 { X86_64_TABLE (X86_64_17
) },
2614 { "sbbB", { Ebh1
, Gb
}, 0 },
2615 { "sbbS", { Evh1
, Gv
}, 0 },
2616 { "sbbB", { Gb
, EbS
}, 0 },
2617 { "sbbS", { Gv
, EvS
}, 0 },
2618 { "sbbB", { AL
, Ib
}, 0 },
2619 { "sbbS", { eAX
, Iv
}, 0 },
2620 { X86_64_TABLE (X86_64_1E
) },
2621 { X86_64_TABLE (X86_64_1F
) },
2623 { "andB", { Ebh1
, Gb
}, 0 },
2624 { "andS", { Evh1
, Gv
}, 0 },
2625 { "andB", { Gb
, EbS
}, 0 },
2626 { "andS", { Gv
, EvS
}, 0 },
2627 { "andB", { AL
, Ib
}, 0 },
2628 { "andS", { eAX
, Iv
}, 0 },
2629 { Bad_Opcode
}, /* SEG ES prefix */
2630 { X86_64_TABLE (X86_64_27
) },
2632 { "subB", { Ebh1
, Gb
}, 0 },
2633 { "subS", { Evh1
, Gv
}, 0 },
2634 { "subB", { Gb
, EbS
}, 0 },
2635 { "subS", { Gv
, EvS
}, 0 },
2636 { "subB", { AL
, Ib
}, 0 },
2637 { "subS", { eAX
, Iv
}, 0 },
2638 { Bad_Opcode
}, /* SEG CS prefix */
2639 { X86_64_TABLE (X86_64_2F
) },
2641 { "xorB", { Ebh1
, Gb
}, 0 },
2642 { "xorS", { Evh1
, Gv
}, 0 },
2643 { "xorB", { Gb
, EbS
}, 0 },
2644 { "xorS", { Gv
, EvS
}, 0 },
2645 { "xorB", { AL
, Ib
}, 0 },
2646 { "xorS", { eAX
, Iv
}, 0 },
2647 { Bad_Opcode
}, /* SEG SS prefix */
2648 { X86_64_TABLE (X86_64_37
) },
2650 { "cmpB", { Eb
, Gb
}, 0 },
2651 { "cmpS", { Ev
, Gv
}, 0 },
2652 { "cmpB", { Gb
, EbS
}, 0 },
2653 { "cmpS", { Gv
, EvS
}, 0 },
2654 { "cmpB", { AL
, Ib
}, 0 },
2655 { "cmpS", { eAX
, Iv
}, 0 },
2656 { Bad_Opcode
}, /* SEG DS prefix */
2657 { X86_64_TABLE (X86_64_3F
) },
2659 { "inc{S|}", { RMeAX
}, 0 },
2660 { "inc{S|}", { RMeCX
}, 0 },
2661 { "inc{S|}", { RMeDX
}, 0 },
2662 { "inc{S|}", { RMeBX
}, 0 },
2663 { "inc{S|}", { RMeSP
}, 0 },
2664 { "inc{S|}", { RMeBP
}, 0 },
2665 { "inc{S|}", { RMeSI
}, 0 },
2666 { "inc{S|}", { RMeDI
}, 0 },
2668 { "dec{S|}", { RMeAX
}, 0 },
2669 { "dec{S|}", { RMeCX
}, 0 },
2670 { "dec{S|}", { RMeDX
}, 0 },
2671 { "dec{S|}", { RMeBX
}, 0 },
2672 { "dec{S|}", { RMeSP
}, 0 },
2673 { "dec{S|}", { RMeBP
}, 0 },
2674 { "dec{S|}", { RMeSI
}, 0 },
2675 { "dec{S|}", { RMeDI
}, 0 },
2677 { "pushV", { RMrAX
}, 0 },
2678 { "pushV", { RMrCX
}, 0 },
2679 { "pushV", { RMrDX
}, 0 },
2680 { "pushV", { RMrBX
}, 0 },
2681 { "pushV", { RMrSP
}, 0 },
2682 { "pushV", { RMrBP
}, 0 },
2683 { "pushV", { RMrSI
}, 0 },
2684 { "pushV", { RMrDI
}, 0 },
2686 { "popV", { RMrAX
}, 0 },
2687 { "popV", { RMrCX
}, 0 },
2688 { "popV", { RMrDX
}, 0 },
2689 { "popV", { RMrBX
}, 0 },
2690 { "popV", { RMrSP
}, 0 },
2691 { "popV", { RMrBP
}, 0 },
2692 { "popV", { RMrSI
}, 0 },
2693 { "popV", { RMrDI
}, 0 },
2695 { X86_64_TABLE (X86_64_60
) },
2696 { X86_64_TABLE (X86_64_61
) },
2697 { X86_64_TABLE (X86_64_62
) },
2698 { X86_64_TABLE (X86_64_63
) },
2699 { Bad_Opcode
}, /* seg fs */
2700 { Bad_Opcode
}, /* seg gs */
2701 { Bad_Opcode
}, /* op size prefix */
2702 { Bad_Opcode
}, /* adr size prefix */
2704 { "pushT", { sIv
}, 0 },
2705 { "imulS", { Gv
, Ev
, Iv
}, 0 },
2706 { "pushT", { sIbT
}, 0 },
2707 { "imulS", { Gv
, Ev
, sIb
}, 0 },
2708 { "ins{b|}", { Ybr
, indirDX
}, 0 },
2709 { X86_64_TABLE (X86_64_6D
) },
2710 { "outs{b|}", { indirDXr
, Xb
}, 0 },
2711 { X86_64_TABLE (X86_64_6F
) },
2713 { "joH", { Jb
, BND
, cond_jump_flag
}, 0 },
2714 { "jnoH", { Jb
, BND
, cond_jump_flag
}, 0 },
2715 { "jbH", { Jb
, BND
, cond_jump_flag
}, 0 },
2716 { "jaeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2717 { "jeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2718 { "jneH", { Jb
, BND
, cond_jump_flag
}, 0 },
2719 { "jbeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2720 { "jaH", { Jb
, BND
, cond_jump_flag
}, 0 },
2722 { "jsH", { Jb
, BND
, cond_jump_flag
}, 0 },
2723 { "jnsH", { Jb
, BND
, cond_jump_flag
}, 0 },
2724 { "jpH", { Jb
, BND
, cond_jump_flag
}, 0 },
2725 { "jnpH", { Jb
, BND
, cond_jump_flag
}, 0 },
2726 { "jlH", { Jb
, BND
, cond_jump_flag
}, 0 },
2727 { "jgeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2728 { "jleH", { Jb
, BND
, cond_jump_flag
}, 0 },
2729 { "jgH", { Jb
, BND
, cond_jump_flag
}, 0 },
2731 { REG_TABLE (REG_80
) },
2732 { REG_TABLE (REG_81
) },
2733 { X86_64_TABLE (X86_64_82
) },
2734 { REG_TABLE (REG_83
) },
2735 { "testB", { Eb
, Gb
}, 0 },
2736 { "testS", { Ev
, Gv
}, 0 },
2737 { "xchgB", { Ebh2
, Gb
}, 0 },
2738 { "xchgS", { Evh2
, Gv
}, 0 },
2740 { "movB", { Ebh3
, Gb
}, 0 },
2741 { "movS", { Evh3
, Gv
}, 0 },
2742 { "movB", { Gb
, EbS
}, 0 },
2743 { "movS", { Gv
, EvS
}, 0 },
2744 { "movD", { Sv
, Sw
}, 0 },
2745 { MOD_TABLE (MOD_8D
) },
2746 { "movD", { Sw
, Sv
}, 0 },
2747 { REG_TABLE (REG_8F
) },
2749 { PREFIX_TABLE (PREFIX_90
) },
2750 { "xchgS", { RMeCX
, eAX
}, 0 },
2751 { "xchgS", { RMeDX
, eAX
}, 0 },
2752 { "xchgS", { RMeBX
, eAX
}, 0 },
2753 { "xchgS", { RMeSP
, eAX
}, 0 },
2754 { "xchgS", { RMeBP
, eAX
}, 0 },
2755 { "xchgS", { RMeSI
, eAX
}, 0 },
2756 { "xchgS", { RMeDI
, eAX
}, 0 },
2758 { "cW{t|}R", { XX
}, 0 },
2759 { "cR{t|}O", { XX
}, 0 },
2760 { X86_64_TABLE (X86_64_9A
) },
2761 { Bad_Opcode
}, /* fwait */
2762 { "pushfT", { XX
}, 0 },
2763 { "popfT", { XX
}, 0 },
2764 { "sahf", { XX
}, 0 },
2765 { "lahf", { XX
}, 0 },
2767 { "mov%LB", { AL
, Ob
}, 0 },
2768 { "mov%LS", { eAX
, Ov
}, 0 },
2769 { "mov%LB", { Ob
, AL
}, 0 },
2770 { "mov%LS", { Ov
, eAX
}, 0 },
2771 { "movs{b|}", { Ybr
, Xb
}, 0 },
2772 { "movs{R|}", { Yvr
, Xv
}, 0 },
2773 { "cmps{b|}", { Xb
, Yb
}, 0 },
2774 { "cmps{R|}", { Xv
, Yv
}, 0 },
2776 { "testB", { AL
, Ib
}, 0 },
2777 { "testS", { eAX
, Iv
}, 0 },
2778 { "stosB", { Ybr
, AL
}, 0 },
2779 { "stosS", { Yvr
, eAX
}, 0 },
2780 { "lodsB", { ALr
, Xb
}, 0 },
2781 { "lodsS", { eAXr
, Xv
}, 0 },
2782 { "scasB", { AL
, Yb
}, 0 },
2783 { "scasS", { eAX
, Yv
}, 0 },
2785 { "movB", { RMAL
, Ib
}, 0 },
2786 { "movB", { RMCL
, Ib
}, 0 },
2787 { "movB", { RMDL
, Ib
}, 0 },
2788 { "movB", { RMBL
, Ib
}, 0 },
2789 { "movB", { RMAH
, Ib
}, 0 },
2790 { "movB", { RMCH
, Ib
}, 0 },
2791 { "movB", { RMDH
, Ib
}, 0 },
2792 { "movB", { RMBH
, Ib
}, 0 },
2794 { "mov%LV", { RMeAX
, Iv64
}, 0 },
2795 { "mov%LV", { RMeCX
, Iv64
}, 0 },
2796 { "mov%LV", { RMeDX
, Iv64
}, 0 },
2797 { "mov%LV", { RMeBX
, Iv64
}, 0 },
2798 { "mov%LV", { RMeSP
, Iv64
}, 0 },
2799 { "mov%LV", { RMeBP
, Iv64
}, 0 },
2800 { "mov%LV", { RMeSI
, Iv64
}, 0 },
2801 { "mov%LV", { RMeDI
, Iv64
}, 0 },
2803 { REG_TABLE (REG_C0
) },
2804 { REG_TABLE (REG_C1
) },
2805 { "retT", { Iw
, BND
}, 0 },
2806 { "retT", { BND
}, 0 },
2807 { X86_64_TABLE (X86_64_C4
) },
2808 { X86_64_TABLE (X86_64_C5
) },
2809 { REG_TABLE (REG_C6
) },
2810 { REG_TABLE (REG_C7
) },
2812 { "enterT", { Iw
, Ib
}, 0 },
2813 { "leaveT", { XX
}, 0 },
2814 { "Jret{|f}P", { Iw
}, 0 },
2815 { "Jret{|f}P", { XX
}, 0 },
2816 { "int3", { XX
}, 0 },
2817 { "int", { Ib
}, 0 },
2818 { X86_64_TABLE (X86_64_CE
) },
2819 { "iret%LP", { XX
}, 0 },
2821 { REG_TABLE (REG_D0
) },
2822 { REG_TABLE (REG_D1
) },
2823 { REG_TABLE (REG_D2
) },
2824 { REG_TABLE (REG_D3
) },
2825 { X86_64_TABLE (X86_64_D4
) },
2826 { X86_64_TABLE (X86_64_D5
) },
2828 { "xlat", { DSBX
}, 0 },
2839 { "loopneFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2840 { "loopeFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2841 { "loopFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2842 { "jEcxzH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2843 { "inB", { AL
, Ib
}, 0 },
2844 { "inG", { zAX
, Ib
}, 0 },
2845 { "outB", { Ib
, AL
}, 0 },
2846 { "outG", { Ib
, zAX
}, 0 },
2848 { X86_64_TABLE (X86_64_E8
) },
2849 { X86_64_TABLE (X86_64_E9
) },
2850 { X86_64_TABLE (X86_64_EA
) },
2851 { "jmp", { Jb
, BND
}, 0 },
2852 { "inB", { AL
, indirDX
}, 0 },
2853 { "inG", { zAX
, indirDX
}, 0 },
2854 { "outB", { indirDX
, AL
}, 0 },
2855 { "outG", { indirDX
, zAX
}, 0 },
2857 { Bad_Opcode
}, /* lock prefix */
2858 { "icebp", { XX
}, 0 },
2859 { Bad_Opcode
}, /* repne */
2860 { Bad_Opcode
}, /* repz */
2861 { "hlt", { XX
}, 0 },
2862 { "cmc", { XX
}, 0 },
2863 { REG_TABLE (REG_F6
) },
2864 { REG_TABLE (REG_F7
) },
2866 { "clc", { XX
}, 0 },
2867 { "stc", { XX
}, 0 },
2868 { "cli", { XX
}, 0 },
2869 { "sti", { XX
}, 0 },
2870 { "cld", { XX
}, 0 },
2871 { "std", { XX
}, 0 },
2872 { REG_TABLE (REG_FE
) },
2873 { REG_TABLE (REG_FF
) },
2876 static const struct dis386 dis386_twobyte
[] = {
2878 { REG_TABLE (REG_0F00
) },
2879 { REG_TABLE (REG_0F01
) },
2880 { "larS", { Gv
, Ew
}, 0 },
2881 { "lslS", { Gv
, Ew
}, 0 },
2883 { "syscall", { XX
}, 0 },
2884 { "clts", { XX
}, 0 },
2885 { "sysret%LP", { XX
}, 0 },
2887 { "invd", { XX
}, 0 },
2888 { PREFIX_TABLE (PREFIX_0F09
) },
2890 { "ud2", { XX
}, 0 },
2892 { REG_TABLE (REG_0F0D
) },
2893 { "femms", { XX
}, 0 },
2894 { "", { MX
, EM
, OPSUF
}, 0 }, /* See OP_3DNowSuffix. */
2896 { PREFIX_TABLE (PREFIX_0F10
) },
2897 { PREFIX_TABLE (PREFIX_0F11
) },
2898 { PREFIX_TABLE (PREFIX_0F12
) },
2899 { MOD_TABLE (MOD_0F13
) },
2900 { "unpcklpX", { XM
, EXx
}, PREFIX_OPCODE
},
2901 { "unpckhpX", { XM
, EXx
}, PREFIX_OPCODE
},
2902 { PREFIX_TABLE (PREFIX_0F16
) },
2903 { MOD_TABLE (MOD_0F17
) },
2905 { REG_TABLE (REG_0F18
) },
2906 { "nopQ", { Ev
}, 0 },
2907 { PREFIX_TABLE (PREFIX_0F1A
) },
2908 { PREFIX_TABLE (PREFIX_0F1B
) },
2909 { PREFIX_TABLE (PREFIX_0F1C
) },
2910 { "nopQ", { Ev
}, 0 },
2911 { PREFIX_TABLE (PREFIX_0F1E
) },
2912 { "nopQ", { Ev
}, 0 },
2914 { "movZ", { Rm
, Cm
}, 0 },
2915 { "movZ", { Rm
, Dm
}, 0 },
2916 { "movZ", { Cm
, Rm
}, 0 },
2917 { "movZ", { Dm
, Rm
}, 0 },
2918 { MOD_TABLE (MOD_0F24
) },
2920 { MOD_TABLE (MOD_0F26
) },
2923 { "movapX", { XM
, EXx
}, PREFIX_OPCODE
},
2924 { "movapX", { EXxS
, XM
}, PREFIX_OPCODE
},
2925 { PREFIX_TABLE (PREFIX_0F2A
) },
2926 { PREFIX_TABLE (PREFIX_0F2B
) },
2927 { PREFIX_TABLE (PREFIX_0F2C
) },
2928 { PREFIX_TABLE (PREFIX_0F2D
) },
2929 { PREFIX_TABLE (PREFIX_0F2E
) },
2930 { PREFIX_TABLE (PREFIX_0F2F
) },
2932 { "wrmsr", { XX
}, 0 },
2933 { "rdtsc", { XX
}, 0 },
2934 { "rdmsr", { XX
}, 0 },
2935 { "rdpmc", { XX
}, 0 },
2936 { "sysenter", { XX
}, 0 },
2937 { "sysexit", { XX
}, 0 },
2939 { "getsec", { XX
}, 0 },
2941 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38
, PREFIX_OPCODE
) },
2943 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A
, PREFIX_OPCODE
) },
2950 { "cmovoS", { Gv
, Ev
}, 0 },
2951 { "cmovnoS", { Gv
, Ev
}, 0 },
2952 { "cmovbS", { Gv
, Ev
}, 0 },
2953 { "cmovaeS", { Gv
, Ev
}, 0 },
2954 { "cmoveS", { Gv
, Ev
}, 0 },
2955 { "cmovneS", { Gv
, Ev
}, 0 },
2956 { "cmovbeS", { Gv
, Ev
}, 0 },
2957 { "cmovaS", { Gv
, Ev
}, 0 },
2959 { "cmovsS", { Gv
, Ev
}, 0 },
2960 { "cmovnsS", { Gv
, Ev
}, 0 },
2961 { "cmovpS", { Gv
, Ev
}, 0 },
2962 { "cmovnpS", { Gv
, Ev
}, 0 },
2963 { "cmovlS", { Gv
, Ev
}, 0 },
2964 { "cmovgeS", { Gv
, Ev
}, 0 },
2965 { "cmovleS", { Gv
, Ev
}, 0 },
2966 { "cmovgS", { Gv
, Ev
}, 0 },
2968 { MOD_TABLE (MOD_0F51
) },
2969 { PREFIX_TABLE (PREFIX_0F51
) },
2970 { PREFIX_TABLE (PREFIX_0F52
) },
2971 { PREFIX_TABLE (PREFIX_0F53
) },
2972 { "andpX", { XM
, EXx
}, PREFIX_OPCODE
},
2973 { "andnpX", { XM
, EXx
}, PREFIX_OPCODE
},
2974 { "orpX", { XM
, EXx
}, PREFIX_OPCODE
},
2975 { "xorpX", { XM
, EXx
}, PREFIX_OPCODE
},
2977 { PREFIX_TABLE (PREFIX_0F58
) },
2978 { PREFIX_TABLE (PREFIX_0F59
) },
2979 { PREFIX_TABLE (PREFIX_0F5A
) },
2980 { PREFIX_TABLE (PREFIX_0F5B
) },
2981 { PREFIX_TABLE (PREFIX_0F5C
) },
2982 { PREFIX_TABLE (PREFIX_0F5D
) },
2983 { PREFIX_TABLE (PREFIX_0F5E
) },
2984 { PREFIX_TABLE (PREFIX_0F5F
) },
2986 { PREFIX_TABLE (PREFIX_0F60
) },
2987 { PREFIX_TABLE (PREFIX_0F61
) },
2988 { PREFIX_TABLE (PREFIX_0F62
) },
2989 { "packsswb", { MX
, EM
}, PREFIX_OPCODE
},
2990 { "pcmpgtb", { MX
, EM
}, PREFIX_OPCODE
},
2991 { "pcmpgtw", { MX
, EM
}, PREFIX_OPCODE
},
2992 { "pcmpgtd", { MX
, EM
}, PREFIX_OPCODE
},
2993 { "packuswb", { MX
, EM
}, PREFIX_OPCODE
},
2995 { "punpckhbw", { MX
, EM
}, PREFIX_OPCODE
},
2996 { "punpckhwd", { MX
, EM
}, PREFIX_OPCODE
},
2997 { "punpckhdq", { MX
, EM
}, PREFIX_OPCODE
},
2998 { "packssdw", { MX
, EM
}, PREFIX_OPCODE
},
2999 { PREFIX_TABLE (PREFIX_0F6C
) },
3000 { PREFIX_TABLE (PREFIX_0F6D
) },
3001 { "movK", { MX
, Edq
}, PREFIX_OPCODE
},
3002 { PREFIX_TABLE (PREFIX_0F6F
) },
3004 { PREFIX_TABLE (PREFIX_0F70
) },
3005 { REG_TABLE (REG_0F71
) },
3006 { REG_TABLE (REG_0F72
) },
3007 { REG_TABLE (REG_0F73
) },
3008 { "pcmpeqb", { MX
, EM
}, PREFIX_OPCODE
},
3009 { "pcmpeqw", { MX
, EM
}, PREFIX_OPCODE
},
3010 { "pcmpeqd", { MX
, EM
}, PREFIX_OPCODE
},
3011 { "emms", { XX
}, PREFIX_OPCODE
},
3013 { PREFIX_TABLE (PREFIX_0F78
) },
3014 { PREFIX_TABLE (PREFIX_0F79
) },
3017 { PREFIX_TABLE (PREFIX_0F7C
) },
3018 { PREFIX_TABLE (PREFIX_0F7D
) },
3019 { PREFIX_TABLE (PREFIX_0F7E
) },
3020 { PREFIX_TABLE (PREFIX_0F7F
) },
3022 { "joH", { Jv
, BND
, cond_jump_flag
}, 0 },
3023 { "jnoH", { Jv
, BND
, cond_jump_flag
}, 0 },
3024 { "jbH", { Jv
, BND
, cond_jump_flag
}, 0 },
3025 { "jaeH", { Jv
, BND
, cond_jump_flag
}, 0 },
3026 { "jeH", { Jv
, BND
, cond_jump_flag
}, 0 },
3027 { "jneH", { Jv
, BND
, cond_jump_flag
}, 0 },
3028 { "jbeH", { Jv
, BND
, cond_jump_flag
}, 0 },
3029 { "jaH", { Jv
, BND
, cond_jump_flag
}, 0 },
3031 { "jsH", { Jv
, BND
, cond_jump_flag
}, 0 },
3032 { "jnsH", { Jv
, BND
, cond_jump_flag
}, 0 },
3033 { "jpH", { Jv
, BND
, cond_jump_flag
}, 0 },
3034 { "jnpH", { Jv
, BND
, cond_jump_flag
}, 0 },
3035 { "jlH", { Jv
, BND
, cond_jump_flag
}, 0 },
3036 { "jgeH", { Jv
, BND
, cond_jump_flag
}, 0 },
3037 { "jleH", { Jv
, BND
, cond_jump_flag
}, 0 },
3038 { "jgH", { Jv
, BND
, cond_jump_flag
}, 0 },
3040 { "seto", { Eb
}, 0 },
3041 { "setno", { Eb
}, 0 },
3042 { "setb", { Eb
}, 0 },
3043 { "setae", { Eb
}, 0 },
3044 { "sete", { Eb
}, 0 },
3045 { "setne", { Eb
}, 0 },
3046 { "setbe", { Eb
}, 0 },
3047 { "seta", { Eb
}, 0 },
3049 { "sets", { Eb
}, 0 },
3050 { "setns", { Eb
}, 0 },
3051 { "setp", { Eb
}, 0 },
3052 { "setnp", { Eb
}, 0 },
3053 { "setl", { Eb
}, 0 },
3054 { "setge", { Eb
}, 0 },
3055 { "setle", { Eb
}, 0 },
3056 { "setg", { Eb
}, 0 },
3058 { "pushT", { fs
}, 0 },
3059 { "popT", { fs
}, 0 },
3060 { "cpuid", { XX
}, 0 },
3061 { "btS", { Ev
, Gv
}, 0 },
3062 { "shldS", { Ev
, Gv
, Ib
}, 0 },
3063 { "shldS", { Ev
, Gv
, CL
}, 0 },
3064 { REG_TABLE (REG_0FA6
) },
3065 { REG_TABLE (REG_0FA7
) },
3067 { "pushT", { gs
}, 0 },
3068 { "popT", { gs
}, 0 },
3069 { "rsm", { XX
}, 0 },
3070 { "btsS", { Evh1
, Gv
}, 0 },
3071 { "shrdS", { Ev
, Gv
, Ib
}, 0 },
3072 { "shrdS", { Ev
, Gv
, CL
}, 0 },
3073 { REG_TABLE (REG_0FAE
) },
3074 { "imulS", { Gv
, Ev
}, 0 },
3076 { "cmpxchgB", { Ebh1
, Gb
}, 0 },
3077 { "cmpxchgS", { Evh1
, Gv
}, 0 },
3078 { MOD_TABLE (MOD_0FB2
) },
3079 { "btrS", { Evh1
, Gv
}, 0 },
3080 { MOD_TABLE (MOD_0FB4
) },
3081 { MOD_TABLE (MOD_0FB5
) },
3082 { "movz{bR|x}", { Gv
, Eb
}, 0 },
3083 { "movz{wR|x}", { Gv
, Ew
}, 0 }, /* yes, there really is movzww ! */
3085 { PREFIX_TABLE (PREFIX_0FB8
) },
3086 { "ud1S", { Gv
, Ev
}, 0 },
3087 { REG_TABLE (REG_0FBA
) },
3088 { "btcS", { Evh1
, Gv
}, 0 },
3089 { PREFIX_TABLE (PREFIX_0FBC
) },
3090 { PREFIX_TABLE (PREFIX_0FBD
) },
3091 { "movs{bR|x}", { Gv
, Eb
}, 0 },
3092 { "movs{wR|x}", { Gv
, Ew
}, 0 }, /* yes, there really is movsww ! */
3094 { "xaddB", { Ebh1
, Gb
}, 0 },
3095 { "xaddS", { Evh1
, Gv
}, 0 },
3096 { PREFIX_TABLE (PREFIX_0FC2
) },
3097 { MOD_TABLE (MOD_0FC3
) },
3098 { "pinsrw", { MX
, Edqw
, Ib
}, PREFIX_OPCODE
},
3099 { "pextrw", { Gdq
, MS
, Ib
}, PREFIX_OPCODE
},
3100 { "shufpX", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3101 { REG_TABLE (REG_0FC7
) },
3103 { "bswap", { RMeAX
}, 0 },
3104 { "bswap", { RMeCX
}, 0 },
3105 { "bswap", { RMeDX
}, 0 },
3106 { "bswap", { RMeBX
}, 0 },
3107 { "bswap", { RMeSP
}, 0 },
3108 { "bswap", { RMeBP
}, 0 },
3109 { "bswap", { RMeSI
}, 0 },
3110 { "bswap", { RMeDI
}, 0 },
3112 { PREFIX_TABLE (PREFIX_0FD0
) },
3113 { "psrlw", { MX
, EM
}, PREFIX_OPCODE
},
3114 { "psrld", { MX
, EM
}, PREFIX_OPCODE
},
3115 { "psrlq", { MX
, EM
}, PREFIX_OPCODE
},
3116 { "paddq", { MX
, EM
}, PREFIX_OPCODE
},
3117 { "pmullw", { MX
, EM
}, PREFIX_OPCODE
},
3118 { PREFIX_TABLE (PREFIX_0FD6
) },
3119 { MOD_TABLE (MOD_0FD7
) },
3121 { "psubusb", { MX
, EM
}, PREFIX_OPCODE
},
3122 { "psubusw", { MX
, EM
}, PREFIX_OPCODE
},
3123 { "pminub", { MX
, EM
}, PREFIX_OPCODE
},
3124 { "pand", { MX
, EM
}, PREFIX_OPCODE
},
3125 { "paddusb", { MX
, EM
}, PREFIX_OPCODE
},
3126 { "paddusw", { MX
, EM
}, PREFIX_OPCODE
},
3127 { "pmaxub", { MX
, EM
}, PREFIX_OPCODE
},
3128 { "pandn", { MX
, EM
}, PREFIX_OPCODE
},
3130 { "pavgb", { MX
, EM
}, PREFIX_OPCODE
},
3131 { "psraw", { MX
, EM
}, PREFIX_OPCODE
},
3132 { "psrad", { MX
, EM
}, PREFIX_OPCODE
},
3133 { "pavgw", { MX
, EM
}, PREFIX_OPCODE
},
3134 { "pmulhuw", { MX
, EM
}, PREFIX_OPCODE
},
3135 { "pmulhw", { MX
, EM
}, PREFIX_OPCODE
},
3136 { PREFIX_TABLE (PREFIX_0FE6
) },
3137 { PREFIX_TABLE (PREFIX_0FE7
) },
3139 { "psubsb", { MX
, EM
}, PREFIX_OPCODE
},
3140 { "psubsw", { MX
, EM
}, PREFIX_OPCODE
},
3141 { "pminsw", { MX
, EM
}, PREFIX_OPCODE
},
3142 { "por", { MX
, EM
}, PREFIX_OPCODE
},
3143 { "paddsb", { MX
, EM
}, PREFIX_OPCODE
},
3144 { "paddsw", { MX
, EM
}, PREFIX_OPCODE
},
3145 { "pmaxsw", { MX
, EM
}, PREFIX_OPCODE
},
3146 { "pxor", { MX
, EM
}, PREFIX_OPCODE
},
3148 { PREFIX_TABLE (PREFIX_0FF0
) },
3149 { "psllw", { MX
, EM
}, PREFIX_OPCODE
},
3150 { "pslld", { MX
, EM
}, PREFIX_OPCODE
},
3151 { "psllq", { MX
, EM
}, PREFIX_OPCODE
},
3152 { "pmuludq", { MX
, EM
}, PREFIX_OPCODE
},
3153 { "pmaddwd", { MX
, EM
}, PREFIX_OPCODE
},
3154 { "psadbw", { MX
, EM
}, PREFIX_OPCODE
},
3155 { PREFIX_TABLE (PREFIX_0FF7
) },
3157 { "psubb", { MX
, EM
}, PREFIX_OPCODE
},
3158 { "psubw", { MX
, EM
}, PREFIX_OPCODE
},
3159 { "psubd", { MX
, EM
}, PREFIX_OPCODE
},
3160 { "psubq", { MX
, EM
}, PREFIX_OPCODE
},
3161 { "paddb", { MX
, EM
}, PREFIX_OPCODE
},
3162 { "paddw", { MX
, EM
}, PREFIX_OPCODE
},
3163 { "paddd", { MX
, EM
}, PREFIX_OPCODE
},
3164 { "ud0S", { Gv
, Ev
}, 0 },
3167 static const unsigned char onebyte_has_modrm
[256] = {
3168 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3169 /* ------------------------------- */
3170 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
3171 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
3172 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
3173 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
3174 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
3175 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
3176 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
3177 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
3178 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
3179 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
3180 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
3181 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
3182 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
3183 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
3184 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
3185 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
3186 /* ------------------------------- */
3187 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3190 static const unsigned char twobyte_has_modrm
[256] = {
3191 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3192 /* ------------------------------- */
3193 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
3194 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
3195 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
3196 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
3197 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
3198 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
3199 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
3200 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
3201 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
3202 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
3203 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
3204 /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
3205 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
3206 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
3207 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
3208 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 /* ff */
3209 /* ------------------------------- */
3210 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3213 static char obuf
[100];
3215 static char *mnemonicendp
;
3216 static char scratchbuf
[100];
3217 static unsigned char *start_codep
;
3218 static unsigned char *insn_codep
;
3219 static unsigned char *codep
;
3220 static unsigned char *end_codep
;
3221 static int last_lock_prefix
;
3222 static int last_repz_prefix
;
3223 static int last_repnz_prefix
;
3224 static int last_data_prefix
;
3225 static int last_addr_prefix
;
3226 static int last_rex_prefix
;
3227 static int last_seg_prefix
;
3228 static int fwait_prefix
;
3229 /* The active segment register prefix. */
3230 static int active_seg_prefix
;
3231 #define MAX_CODE_LENGTH 15
3232 /* We can up to 14 prefixes since the maximum instruction length is
3234 static int all_prefixes
[MAX_CODE_LENGTH
- 1];
3235 static disassemble_info
*the_info
;
3243 static unsigned char need_modrm
;
3253 int register_specifier
;
3260 int mask_register_specifier
;
3266 static unsigned char need_vex
;
3267 static unsigned char need_vex_reg
;
3268 static unsigned char vex_w_done
;
3276 /* If we are accessing mod/rm/reg without need_modrm set, then the
3277 values are stale. Hitting this abort likely indicates that you
3278 need to update onebyte_has_modrm or twobyte_has_modrm. */
3279 #define MODRM_CHECK if (!need_modrm) abort ()
3281 static const char **names64
;
3282 static const char **names32
;
3283 static const char **names16
;
3284 static const char **names8
;
3285 static const char **names8rex
;
3286 static const char **names_seg
;
3287 static const char *index64
;
3288 static const char *index32
;
3289 static const char **index16
;
3290 static const char **names_bnd
;
3292 static const char *intel_names64
[] = {
3293 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3294 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3296 static const char *intel_names32
[] = {
3297 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3298 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3300 static const char *intel_names16
[] = {
3301 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3302 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3304 static const char *intel_names8
[] = {
3305 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3307 static const char *intel_names8rex
[] = {
3308 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3309 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3311 static const char *intel_names_seg
[] = {
3312 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3314 static const char *intel_index64
= "riz";
3315 static const char *intel_index32
= "eiz";
3316 static const char *intel_index16
[] = {
3317 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3320 static const char *att_names64
[] = {
3321 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3322 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3324 static const char *att_names32
[] = {
3325 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3326 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3328 static const char *att_names16
[] = {
3329 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3330 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3332 static const char *att_names8
[] = {
3333 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3335 static const char *att_names8rex
[] = {
3336 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3337 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3339 static const char *att_names_seg
[] = {
3340 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3342 static const char *att_index64
= "%riz";
3343 static const char *att_index32
= "%eiz";
3344 static const char *att_index16
[] = {
3345 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3348 static const char **names_mm
;
3349 static const char *intel_names_mm
[] = {
3350 "mm0", "mm1", "mm2", "mm3",
3351 "mm4", "mm5", "mm6", "mm7"
3353 static const char *att_names_mm
[] = {
3354 "%mm0", "%mm1", "%mm2", "%mm3",
3355 "%mm4", "%mm5", "%mm6", "%mm7"
3358 static const char *intel_names_bnd
[] = {
3359 "bnd0", "bnd1", "bnd2", "bnd3"
3362 static const char *att_names_bnd
[] = {
3363 "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3366 static const char **names_xmm
;
3367 static const char *intel_names_xmm
[] = {
3368 "xmm0", "xmm1", "xmm2", "xmm3",
3369 "xmm4", "xmm5", "xmm6", "xmm7",
3370 "xmm8", "xmm9", "xmm10", "xmm11",
3371 "xmm12", "xmm13", "xmm14", "xmm15",
3372 "xmm16", "xmm17", "xmm18", "xmm19",
3373 "xmm20", "xmm21", "xmm22", "xmm23",
3374 "xmm24", "xmm25", "xmm26", "xmm27",
3375 "xmm28", "xmm29", "xmm30", "xmm31"
3377 static const char *att_names_xmm
[] = {
3378 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3379 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3380 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3381 "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3382 "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3383 "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3384 "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3385 "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3388 static const char **names_ymm
;
3389 static const char *intel_names_ymm
[] = {
3390 "ymm0", "ymm1", "ymm2", "ymm3",
3391 "ymm4", "ymm5", "ymm6", "ymm7",
3392 "ymm8", "ymm9", "ymm10", "ymm11",
3393 "ymm12", "ymm13", "ymm14", "ymm15",
3394 "ymm16", "ymm17", "ymm18", "ymm19",
3395 "ymm20", "ymm21", "ymm22", "ymm23",
3396 "ymm24", "ymm25", "ymm26", "ymm27",
3397 "ymm28", "ymm29", "ymm30", "ymm31"
3399 static const char *att_names_ymm
[] = {
3400 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3401 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3402 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3403 "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3404 "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3405 "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3406 "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3407 "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3410 static const char **names_zmm
;
3411 static const char *intel_names_zmm
[] = {
3412 "zmm0", "zmm1", "zmm2", "zmm3",
3413 "zmm4", "zmm5", "zmm6", "zmm7",
3414 "zmm8", "zmm9", "zmm10", "zmm11",
3415 "zmm12", "zmm13", "zmm14", "zmm15",
3416 "zmm16", "zmm17", "zmm18", "zmm19",
3417 "zmm20", "zmm21", "zmm22", "zmm23",
3418 "zmm24", "zmm25", "zmm26", "zmm27",
3419 "zmm28", "zmm29", "zmm30", "zmm31"
3421 static const char *att_names_zmm
[] = {
3422 "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3423 "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3424 "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3425 "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3426 "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3427 "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3428 "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3429 "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3432 static const char **names_mask
;
3433 static const char *intel_names_mask
[] = {
3434 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3436 static const char *att_names_mask
[] = {
3437 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3440 static const char *names_rounding
[] =
3448 static const struct dis386 reg_table
[][8] = {
3451 { "addA", { Ebh1
, Ib
}, 0 },
3452 { "orA", { Ebh1
, Ib
}, 0 },
3453 { "adcA", { Ebh1
, Ib
}, 0 },
3454 { "sbbA", { Ebh1
, Ib
}, 0 },
3455 { "andA", { Ebh1
, Ib
}, 0 },
3456 { "subA", { Ebh1
, Ib
}, 0 },
3457 { "xorA", { Ebh1
, Ib
}, 0 },
3458 { "cmpA", { Eb
, Ib
}, 0 },
3462 { "addQ", { Evh1
, Iv
}, 0 },
3463 { "orQ", { Evh1
, Iv
}, 0 },
3464 { "adcQ", { Evh1
, Iv
}, 0 },
3465 { "sbbQ", { Evh1
, Iv
}, 0 },
3466 { "andQ", { Evh1
, Iv
}, 0 },
3467 { "subQ", { Evh1
, Iv
}, 0 },
3468 { "xorQ", { Evh1
, Iv
}, 0 },
3469 { "cmpQ", { Ev
, Iv
}, 0 },
3473 { "addQ", { Evh1
, sIb
}, 0 },
3474 { "orQ", { Evh1
, sIb
}, 0 },
3475 { "adcQ", { Evh1
, sIb
}, 0 },
3476 { "sbbQ", { Evh1
, sIb
}, 0 },
3477 { "andQ", { Evh1
, sIb
}, 0 },
3478 { "subQ", { Evh1
, sIb
}, 0 },
3479 { "xorQ", { Evh1
, sIb
}, 0 },
3480 { "cmpQ", { Ev
, sIb
}, 0 },
3484 { "popU", { stackEv
}, 0 },
3485 { XOP_8F_TABLE (XOP_09
) },
3489 { XOP_8F_TABLE (XOP_09
) },
3493 { "rolA", { Eb
, Ib
}, 0 },
3494 { "rorA", { Eb
, Ib
}, 0 },
3495 { "rclA", { Eb
, Ib
}, 0 },
3496 { "rcrA", { Eb
, Ib
}, 0 },
3497 { "shlA", { Eb
, Ib
}, 0 },
3498 { "shrA", { Eb
, Ib
}, 0 },
3499 { "shlA", { Eb
, Ib
}, 0 },
3500 { "sarA", { Eb
, Ib
}, 0 },
3504 { "rolQ", { Ev
, Ib
}, 0 },
3505 { "rorQ", { Ev
, Ib
}, 0 },
3506 { "rclQ", { Ev
, Ib
}, 0 },
3507 { "rcrQ", { Ev
, Ib
}, 0 },
3508 { "shlQ", { Ev
, Ib
}, 0 },
3509 { "shrQ", { Ev
, Ib
}, 0 },
3510 { "shlQ", { Ev
, Ib
}, 0 },
3511 { "sarQ", { Ev
, Ib
}, 0 },
3515 { "movA", { Ebh3
, Ib
}, 0 },
3522 { MOD_TABLE (MOD_C6_REG_7
) },
3526 { "movQ", { Evh3
, Iv
}, 0 },
3533 { MOD_TABLE (MOD_C7_REG_7
) },
3537 { "rolA", { Eb
, I1
}, 0 },
3538 { "rorA", { Eb
, I1
}, 0 },
3539 { "rclA", { Eb
, I1
}, 0 },
3540 { "rcrA", { Eb
, I1
}, 0 },
3541 { "shlA", { Eb
, I1
}, 0 },
3542 { "shrA", { Eb
, I1
}, 0 },
3543 { "shlA", { Eb
, I1
}, 0 },
3544 { "sarA", { Eb
, I1
}, 0 },
3548 { "rolQ", { Ev
, I1
}, 0 },
3549 { "rorQ", { Ev
, I1
}, 0 },
3550 { "rclQ", { Ev
, I1
}, 0 },
3551 { "rcrQ", { Ev
, I1
}, 0 },
3552 { "shlQ", { Ev
, I1
}, 0 },
3553 { "shrQ", { Ev
, I1
}, 0 },
3554 { "shlQ", { Ev
, I1
}, 0 },
3555 { "sarQ", { Ev
, I1
}, 0 },
3559 { "rolA", { Eb
, CL
}, 0 },
3560 { "rorA", { Eb
, CL
}, 0 },
3561 { "rclA", { Eb
, CL
}, 0 },
3562 { "rcrA", { Eb
, CL
}, 0 },
3563 { "shlA", { Eb
, CL
}, 0 },
3564 { "shrA", { Eb
, CL
}, 0 },
3565 { "shlA", { Eb
, CL
}, 0 },
3566 { "sarA", { Eb
, CL
}, 0 },
3570 { "rolQ", { Ev
, CL
}, 0 },
3571 { "rorQ", { Ev
, CL
}, 0 },
3572 { "rclQ", { Ev
, CL
}, 0 },
3573 { "rcrQ", { Ev
, CL
}, 0 },
3574 { "shlQ", { Ev
, CL
}, 0 },
3575 { "shrQ", { Ev
, CL
}, 0 },
3576 { "shlQ", { Ev
, CL
}, 0 },
3577 { "sarQ", { Ev
, CL
}, 0 },
3581 { "testA", { Eb
, Ib
}, 0 },
3582 { "testA", { Eb
, Ib
}, 0 },
3583 { "notA", { Ebh1
}, 0 },
3584 { "negA", { Ebh1
}, 0 },
3585 { "mulA", { Eb
}, 0 }, /* Don't print the implicit %al register, */
3586 { "imulA", { Eb
}, 0 }, /* to distinguish these opcodes from other */
3587 { "divA", { Eb
}, 0 }, /* mul/imul opcodes. Do the same for div */
3588 { "idivA", { Eb
}, 0 }, /* and idiv for consistency. */
3592 { "testQ", { Ev
, Iv
}, 0 },
3593 { "testQ", { Ev
, Iv
}, 0 },
3594 { "notQ", { Evh1
}, 0 },
3595 { "negQ", { Evh1
}, 0 },
3596 { "mulQ", { Ev
}, 0 }, /* Don't print the implicit register. */
3597 { "imulQ", { Ev
}, 0 },
3598 { "divQ", { Ev
}, 0 },
3599 { "idivQ", { Ev
}, 0 },
3603 { "incA", { Ebh1
}, 0 },
3604 { "decA", { Ebh1
}, 0 },
3608 { "incQ", { Evh1
}, 0 },
3609 { "decQ", { Evh1
}, 0 },
3610 { "call{&|}", { NOTRACK
, indirEv
, BND
}, 0 },
3611 { MOD_TABLE (MOD_FF_REG_3
) },
3612 { "jmp{&|}", { NOTRACK
, indirEv
, BND
}, 0 },
3613 { MOD_TABLE (MOD_FF_REG_5
) },
3614 { "pushU", { stackEv
}, 0 },
3619 { "sldtD", { Sv
}, 0 },
3620 { "strD", { Sv
}, 0 },
3621 { "lldt", { Ew
}, 0 },
3622 { "ltr", { Ew
}, 0 },
3623 { "verr", { Ew
}, 0 },
3624 { "verw", { Ew
}, 0 },
3630 { MOD_TABLE (MOD_0F01_REG_0
) },
3631 { MOD_TABLE (MOD_0F01_REG_1
) },
3632 { MOD_TABLE (MOD_0F01_REG_2
) },
3633 { MOD_TABLE (MOD_0F01_REG_3
) },
3634 { "smswD", { Sv
}, 0 },
3635 { MOD_TABLE (MOD_0F01_REG_5
) },
3636 { "lmsw", { Ew
}, 0 },
3637 { MOD_TABLE (MOD_0F01_REG_7
) },
3641 { "prefetch", { Mb
}, 0 },
3642 { "prefetchw", { Mb
}, 0 },
3643 { "prefetchwt1", { Mb
}, 0 },
3644 { "prefetch", { Mb
}, 0 },
3645 { "prefetch", { Mb
}, 0 },
3646 { "prefetch", { Mb
}, 0 },
3647 { "prefetch", { Mb
}, 0 },
3648 { "prefetch", { Mb
}, 0 },
3652 { MOD_TABLE (MOD_0F18_REG_0
) },
3653 { MOD_TABLE (MOD_0F18_REG_1
) },
3654 { MOD_TABLE (MOD_0F18_REG_2
) },
3655 { MOD_TABLE (MOD_0F18_REG_3
) },
3656 { MOD_TABLE (MOD_0F18_REG_4
) },
3657 { MOD_TABLE (MOD_0F18_REG_5
) },
3658 { MOD_TABLE (MOD_0F18_REG_6
) },
3659 { MOD_TABLE (MOD_0F18_REG_7
) },
3661 /* REG_0F1C_MOD_0 */
3663 { "cldemote", { Mb
}, 0 },
3664 { "nopQ", { Ev
}, 0 },
3665 { "nopQ", { Ev
}, 0 },
3666 { "nopQ", { Ev
}, 0 },
3667 { "nopQ", { Ev
}, 0 },
3668 { "nopQ", { Ev
}, 0 },
3669 { "nopQ", { Ev
}, 0 },
3670 { "nopQ", { Ev
}, 0 },
3672 /* REG_0F1E_MOD_3 */
3674 { "nopQ", { Ev
}, 0 },
3675 { "rdsspK", { Rdq
}, PREFIX_OPCODE
},
3676 { "nopQ", { Ev
}, 0 },
3677 { "nopQ", { Ev
}, 0 },
3678 { "nopQ", { Ev
}, 0 },
3679 { "nopQ", { Ev
}, 0 },
3680 { "nopQ", { Ev
}, 0 },
3681 { RM_TABLE (RM_0F1E_MOD_3_REG_7
) },
3687 { MOD_TABLE (MOD_0F71_REG_2
) },
3689 { MOD_TABLE (MOD_0F71_REG_4
) },
3691 { MOD_TABLE (MOD_0F71_REG_6
) },
3697 { MOD_TABLE (MOD_0F72_REG_2
) },
3699 { MOD_TABLE (MOD_0F72_REG_4
) },
3701 { MOD_TABLE (MOD_0F72_REG_6
) },
3707 { MOD_TABLE (MOD_0F73_REG_2
) },
3708 { MOD_TABLE (MOD_0F73_REG_3
) },
3711 { MOD_TABLE (MOD_0F73_REG_6
) },
3712 { MOD_TABLE (MOD_0F73_REG_7
) },
3716 { "montmul", { { OP_0f07
, 0 } }, 0 },
3717 { "xsha1", { { OP_0f07
, 0 } }, 0 },
3718 { "xsha256", { { OP_0f07
, 0 } }, 0 },
3722 { "xstore-rng", { { OP_0f07
, 0 } }, 0 },
3723 { "xcrypt-ecb", { { OP_0f07
, 0 } }, 0 },
3724 { "xcrypt-cbc", { { OP_0f07
, 0 } }, 0 },
3725 { "xcrypt-ctr", { { OP_0f07
, 0 } }, 0 },
3726 { "xcrypt-cfb", { { OP_0f07
, 0 } }, 0 },
3727 { "xcrypt-ofb", { { OP_0f07
, 0 } }, 0 },
3731 { MOD_TABLE (MOD_0FAE_REG_0
) },
3732 { MOD_TABLE (MOD_0FAE_REG_1
) },
3733 { MOD_TABLE (MOD_0FAE_REG_2
) },
3734 { MOD_TABLE (MOD_0FAE_REG_3
) },
3735 { MOD_TABLE (MOD_0FAE_REG_4
) },
3736 { MOD_TABLE (MOD_0FAE_REG_5
) },
3737 { MOD_TABLE (MOD_0FAE_REG_6
) },
3738 { MOD_TABLE (MOD_0FAE_REG_7
) },
3746 { "btQ", { Ev
, Ib
}, 0 },
3747 { "btsQ", { Evh1
, Ib
}, 0 },
3748 { "btrQ", { Evh1
, Ib
}, 0 },
3749 { "btcQ", { Evh1
, Ib
}, 0 },
3754 { "cmpxchg8b", { { CMPXCHG8B_Fixup
, q_mode
} }, 0 },
3756 { MOD_TABLE (MOD_0FC7_REG_3
) },
3757 { MOD_TABLE (MOD_0FC7_REG_4
) },
3758 { MOD_TABLE (MOD_0FC7_REG_5
) },
3759 { MOD_TABLE (MOD_0FC7_REG_6
) },
3760 { MOD_TABLE (MOD_0FC7_REG_7
) },
3766 { MOD_TABLE (MOD_VEX_0F71_REG_2
) },
3768 { MOD_TABLE (MOD_VEX_0F71_REG_4
) },
3770 { MOD_TABLE (MOD_VEX_0F71_REG_6
) },
3776 { MOD_TABLE (MOD_VEX_0F72_REG_2
) },
3778 { MOD_TABLE (MOD_VEX_0F72_REG_4
) },
3780 { MOD_TABLE (MOD_VEX_0F72_REG_6
) },
3786 { MOD_TABLE (MOD_VEX_0F73_REG_2
) },
3787 { MOD_TABLE (MOD_VEX_0F73_REG_3
) },
3790 { MOD_TABLE (MOD_VEX_0F73_REG_6
) },
3791 { MOD_TABLE (MOD_VEX_0F73_REG_7
) },
3797 { MOD_TABLE (MOD_VEX_0FAE_REG_2
) },
3798 { MOD_TABLE (MOD_VEX_0FAE_REG_3
) },
3800 /* REG_VEX_0F38F3 */
3803 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1
) },
3804 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2
) },
3805 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3
) },
3809 { "llwpcb", { { OP_LWPCB_E
, 0 } }, 0 },
3810 { "slwpcb", { { OP_LWPCB_E
, 0 } }, 0 },
3814 { "lwpins", { { OP_LWP_E
, 0 }, Ed
, Iq
}, 0 },
3815 { "lwpval", { { OP_LWP_E
, 0 }, Ed
, Iq
}, 0 },
3817 /* REG_XOP_TBM_01 */
3820 { "blcfill", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3821 { "blsfill", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3822 { "blcs", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3823 { "tzmsk", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3824 { "blcic", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3825 { "blsic", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3826 { "t1mskc", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3828 /* REG_XOP_TBM_02 */
3831 { "blcmsk", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3836 { "blci", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3838 #define NEED_REG_TABLE
3839 #include "i386-dis-evex.h"
3840 #undef NEED_REG_TABLE
3843 static const struct dis386 prefix_table
[][4] = {
3846 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} }, 0 },
3847 { "pause", { XX
}, 0 },
3848 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} }, 0 },
3849 { NULL
, { { NULL
, 0 } }, PREFIX_IGNORED
}
3852 /* PREFIX_MOD_0_0F01_REG_5 */
3855 { "rstorssp", { Mq
}, PREFIX_OPCODE
},
3858 /* PREFIX_MOD_3_0F01_REG_5_RM_0 */
3861 { "setssbsy", { Skip_MODRM
}, PREFIX_OPCODE
},
3864 /* PREFIX_MOD_3_0F01_REG_5_RM_2 */
3867 { "saveprevssp", { Skip_MODRM
}, PREFIX_OPCODE
},
3872 { "wbinvd", { XX
}, 0 },
3873 { "wbnoinvd", { XX
}, 0 },
3878 { "movups", { XM
, EXx
}, PREFIX_OPCODE
},
3879 { "movss", { XM
, EXd
}, PREFIX_OPCODE
},
3880 { "movupd", { XM
, EXx
}, PREFIX_OPCODE
},
3881 { "movsd", { XM
, EXq
}, PREFIX_OPCODE
},
3886 { "movups", { EXxS
, XM
}, PREFIX_OPCODE
},
3887 { "movss", { EXdS
, XM
}, PREFIX_OPCODE
},
3888 { "movupd", { EXxS
, XM
}, PREFIX_OPCODE
},
3889 { "movsd", { EXqS
, XM
}, PREFIX_OPCODE
},
3894 { MOD_TABLE (MOD_0F12_PREFIX_0
) },
3895 { "movsldup", { XM
, EXx
}, PREFIX_OPCODE
},
3896 { "movlpd", { XM
, EXq
}, PREFIX_OPCODE
},
3897 { "movddup", { XM
, EXq
}, PREFIX_OPCODE
},
3902 { MOD_TABLE (MOD_0F16_PREFIX_0
) },
3903 { "movshdup", { XM
, EXx
}, PREFIX_OPCODE
},
3904 { "movhpd", { XM
, EXq
}, PREFIX_OPCODE
},
3909 { MOD_TABLE (MOD_0F1A_PREFIX_0
) },
3910 { "bndcl", { Gbnd
, Ev_bnd
}, 0 },
3911 { "bndmov", { Gbnd
, Ebnd
}, 0 },
3912 { "bndcu", { Gbnd
, Ev_bnd
}, 0 },
3917 { MOD_TABLE (MOD_0F1B_PREFIX_0
) },
3918 { MOD_TABLE (MOD_0F1B_PREFIX_1
) },
3919 { "bndmov", { EbndS
, Gbnd
}, 0 },
3920 { "bndcn", { Gbnd
, Ev_bnd
}, 0 },
3925 { MOD_TABLE (MOD_0F1C_PREFIX_0
) },
3926 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3927 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3928 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3933 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3934 { MOD_TABLE (MOD_0F1E_PREFIX_1
) },
3935 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3936 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3941 { "cvtpi2ps", { XM
, EMCq
}, PREFIX_OPCODE
},
3942 { "cvtsi2ss%LQ", { XM
, Ev
}, PREFIX_OPCODE
},
3943 { "cvtpi2pd", { XM
, EMCq
}, PREFIX_OPCODE
},
3944 { "cvtsi2sd%LQ", { XM
, Ev
}, 0 },
3949 { MOD_TABLE (MOD_0F2B_PREFIX_0
) },
3950 { MOD_TABLE (MOD_0F2B_PREFIX_1
) },
3951 { MOD_TABLE (MOD_0F2B_PREFIX_2
) },
3952 { MOD_TABLE (MOD_0F2B_PREFIX_3
) },
3957 { "cvttps2pi", { MXC
, EXq
}, PREFIX_OPCODE
},
3958 { "cvttss2si", { Gv
, EXd
}, PREFIX_OPCODE
},
3959 { "cvttpd2pi", { MXC
, EXx
}, PREFIX_OPCODE
},
3960 { "cvttsd2si", { Gv
, EXq
}, PREFIX_OPCODE
},
3965 { "cvtps2pi", { MXC
, EXq
}, PREFIX_OPCODE
},
3966 { "cvtss2si", { Gv
, EXd
}, PREFIX_OPCODE
},
3967 { "cvtpd2pi", { MXC
, EXx
}, PREFIX_OPCODE
},
3968 { "cvtsd2si", { Gv
, EXq
}, PREFIX_OPCODE
},
3973 { "ucomiss",{ XM
, EXd
}, 0 },
3975 { "ucomisd",{ XM
, EXq
}, 0 },
3980 { "comiss", { XM
, EXd
}, 0 },
3982 { "comisd", { XM
, EXq
}, 0 },
3987 { "sqrtps", { XM
, EXx
}, PREFIX_OPCODE
},
3988 { "sqrtss", { XM
, EXd
}, PREFIX_OPCODE
},
3989 { "sqrtpd", { XM
, EXx
}, PREFIX_OPCODE
},
3990 { "sqrtsd", { XM
, EXq
}, PREFIX_OPCODE
},
3995 { "rsqrtps",{ XM
, EXx
}, PREFIX_OPCODE
},
3996 { "rsqrtss",{ XM
, EXd
}, PREFIX_OPCODE
},
4001 { "rcpps", { XM
, EXx
}, PREFIX_OPCODE
},
4002 { "rcpss", { XM
, EXd
}, PREFIX_OPCODE
},
4007 { "addps", { XM
, EXx
}, PREFIX_OPCODE
},
4008 { "addss", { XM
, EXd
}, PREFIX_OPCODE
},
4009 { "addpd", { XM
, EXx
}, PREFIX_OPCODE
},
4010 { "addsd", { XM
, EXq
}, PREFIX_OPCODE
},
4015 { "mulps", { XM
, EXx
}, PREFIX_OPCODE
},
4016 { "mulss", { XM
, EXd
}, PREFIX_OPCODE
},
4017 { "mulpd", { XM
, EXx
}, PREFIX_OPCODE
},
4018 { "mulsd", { XM
, EXq
}, PREFIX_OPCODE
},
4023 { "cvtps2pd", { XM
, EXq
}, PREFIX_OPCODE
},
4024 { "cvtss2sd", { XM
, EXd
}, PREFIX_OPCODE
},
4025 { "cvtpd2ps", { XM
, EXx
}, PREFIX_OPCODE
},
4026 { "cvtsd2ss", { XM
, EXq
}, PREFIX_OPCODE
},
4031 { "cvtdq2ps", { XM
, EXx
}, PREFIX_OPCODE
},
4032 { "cvttps2dq", { XM
, EXx
}, PREFIX_OPCODE
},
4033 { "cvtps2dq", { XM
, EXx
}, PREFIX_OPCODE
},
4038 { "subps", { XM
, EXx
}, PREFIX_OPCODE
},
4039 { "subss", { XM
, EXd
}, PREFIX_OPCODE
},
4040 { "subpd", { XM
, EXx
}, PREFIX_OPCODE
},
4041 { "subsd", { XM
, EXq
}, PREFIX_OPCODE
},
4046 { "minps", { XM
, EXx
}, PREFIX_OPCODE
},
4047 { "minss", { XM
, EXd
}, PREFIX_OPCODE
},
4048 { "minpd", { XM
, EXx
}, PREFIX_OPCODE
},
4049 { "minsd", { XM
, EXq
}, PREFIX_OPCODE
},
4054 { "divps", { XM
, EXx
}, PREFIX_OPCODE
},
4055 { "divss", { XM
, EXd
}, PREFIX_OPCODE
},
4056 { "divpd", { XM
, EXx
}, PREFIX_OPCODE
},
4057 { "divsd", { XM
, EXq
}, PREFIX_OPCODE
},
4062 { "maxps", { XM
, EXx
}, PREFIX_OPCODE
},
4063 { "maxss", { XM
, EXd
}, PREFIX_OPCODE
},
4064 { "maxpd", { XM
, EXx
}, PREFIX_OPCODE
},
4065 { "maxsd", { XM
, EXq
}, PREFIX_OPCODE
},
4070 { "punpcklbw",{ MX
, EMd
}, PREFIX_OPCODE
},
4072 { "punpcklbw",{ MX
, EMx
}, PREFIX_OPCODE
},
4077 { "punpcklwd",{ MX
, EMd
}, PREFIX_OPCODE
},
4079 { "punpcklwd",{ MX
, EMx
}, PREFIX_OPCODE
},
4084 { "punpckldq",{ MX
, EMd
}, PREFIX_OPCODE
},
4086 { "punpckldq",{ MX
, EMx
}, PREFIX_OPCODE
},
4093 { "punpcklqdq", { XM
, EXx
}, PREFIX_OPCODE
},
4100 { "punpckhqdq", { XM
, EXx
}, PREFIX_OPCODE
},
4105 { "movq", { MX
, EM
}, PREFIX_OPCODE
},
4106 { "movdqu", { XM
, EXx
}, PREFIX_OPCODE
},
4107 { "movdqa", { XM
, EXx
}, PREFIX_OPCODE
},
4112 { "pshufw", { MX
, EM
, Ib
}, PREFIX_OPCODE
},
4113 { "pshufhw",{ XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4114 { "pshufd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4115 { "pshuflw",{ XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4118 /* PREFIX_0F73_REG_3 */
4122 { "psrldq", { XS
, Ib
}, 0 },
4125 /* PREFIX_0F73_REG_7 */
4129 { "pslldq", { XS
, Ib
}, 0 },
4134 {"vmread", { Em
, Gm
}, 0 },
4136 {"extrq", { XS
, Ib
, Ib
}, 0 },
4137 {"insertq", { XM
, XS
, Ib
, Ib
}, 0 },
4142 {"vmwrite", { Gm
, Em
}, 0 },
4144 {"extrq", { XM
, XS
}, 0 },
4145 {"insertq", { XM
, XS
}, 0 },
4152 { "haddpd", { XM
, EXx
}, PREFIX_OPCODE
},
4153 { "haddps", { XM
, EXx
}, PREFIX_OPCODE
},
4160 { "hsubpd", { XM
, EXx
}, PREFIX_OPCODE
},
4161 { "hsubps", { XM
, EXx
}, PREFIX_OPCODE
},
4166 { "movK", { Edq
, MX
}, PREFIX_OPCODE
},
4167 { "movq", { XM
, EXq
}, PREFIX_OPCODE
},
4168 { "movK", { Edq
, XM
}, PREFIX_OPCODE
},
4173 { "movq", { EMS
, MX
}, PREFIX_OPCODE
},
4174 { "movdqu", { EXxS
, XM
}, PREFIX_OPCODE
},
4175 { "movdqa", { EXxS
, XM
}, PREFIX_OPCODE
},
4178 /* PREFIX_0FAE_REG_0 */
4181 { "rdfsbase", { Ev
}, 0 },
4184 /* PREFIX_0FAE_REG_1 */
4187 { "rdgsbase", { Ev
}, 0 },
4190 /* PREFIX_0FAE_REG_2 */
4193 { "wrfsbase", { Ev
}, 0 },
4196 /* PREFIX_0FAE_REG_3 */
4199 { "wrgsbase", { Ev
}, 0 },
4202 /* PREFIX_MOD_0_0FAE_REG_4 */
4204 { "xsave", { FXSAVE
}, 0 },
4205 { "ptwrite%LQ", { Edq
}, 0 },
4208 /* PREFIX_MOD_3_0FAE_REG_4 */
4211 { "ptwrite%LQ", { Edq
}, 0 },
4214 /* PREFIX_MOD_0_0FAE_REG_5 */
4216 { "xrstor", { FXSAVE
}, PREFIX_OPCODE
},
4219 /* PREFIX_MOD_3_0FAE_REG_5 */
4221 { "lfence", { Skip_MODRM
}, 0 },
4222 { "incsspK", { Rdq
}, PREFIX_OPCODE
},
4225 /* PREFIX_MOD_0_0FAE_REG_6 */
4227 { "xsaveopt", { FXSAVE
}, PREFIX_OPCODE
},
4228 { "clrssbsy", { Mq
}, PREFIX_OPCODE
},
4229 { "clwb", { Mb
}, PREFIX_OPCODE
},
4232 /* PREFIX_MOD_1_0FAE_REG_6 */
4234 { RM_TABLE (RM_0FAE_REG_6
) },
4235 { "umonitor", { Eva
}, PREFIX_OPCODE
},
4236 { "tpause", { Edq
}, PREFIX_OPCODE
},
4237 { "umwait", { Edq
}, PREFIX_OPCODE
},
4240 /* PREFIX_0FAE_REG_7 */
4242 { "clflush", { Mb
}, 0 },
4244 { "clflushopt", { Mb
}, 0 },
4250 { "popcntS", { Gv
, Ev
}, 0 },
4255 { "bsfS", { Gv
, Ev
}, 0 },
4256 { "tzcntS", { Gv
, Ev
}, 0 },
4257 { "bsfS", { Gv
, Ev
}, 0 },
4262 { "bsrS", { Gv
, Ev
}, 0 },
4263 { "lzcntS", { Gv
, Ev
}, 0 },
4264 { "bsrS", { Gv
, Ev
}, 0 },
4269 { "cmpps", { XM
, EXx
, CMP
}, PREFIX_OPCODE
},
4270 { "cmpss", { XM
, EXd
, CMP
}, PREFIX_OPCODE
},
4271 { "cmppd", { XM
, EXx
, CMP
}, PREFIX_OPCODE
},
4272 { "cmpsd", { XM
, EXq
, CMP
}, PREFIX_OPCODE
},
4275 /* PREFIX_MOD_0_0FC3 */
4277 { "movntiS", { Ev
, Gv
}, PREFIX_OPCODE
},
4280 /* PREFIX_MOD_0_0FC7_REG_6 */
4282 { "vmptrld",{ Mq
}, 0 },
4283 { "vmxon", { Mq
}, 0 },
4284 { "vmclear",{ Mq
}, 0 },
4287 /* PREFIX_MOD_3_0FC7_REG_6 */
4289 { "rdrand", { Ev
}, 0 },
4291 { "rdrand", { Ev
}, 0 }
4294 /* PREFIX_MOD_3_0FC7_REG_7 */
4296 { "rdseed", { Ev
}, 0 },
4297 { "rdpid", { Em
}, 0 },
4298 { "rdseed", { Ev
}, 0 },
4305 { "addsubpd", { XM
, EXx
}, 0 },
4306 { "addsubps", { XM
, EXx
}, 0 },
4312 { "movq2dq",{ XM
, MS
}, 0 },
4313 { "movq", { EXqS
, XM
}, 0 },
4314 { "movdq2q",{ MX
, XS
}, 0 },
4320 { "cvtdq2pd", { XM
, EXq
}, PREFIX_OPCODE
},
4321 { "cvttpd2dq", { XM
, EXx
}, PREFIX_OPCODE
},
4322 { "cvtpd2dq", { XM
, EXx
}, PREFIX_OPCODE
},
4327 { "movntq", { Mq
, MX
}, PREFIX_OPCODE
},
4329 { MOD_TABLE (MOD_0FE7_PREFIX_2
) },
4337 { MOD_TABLE (MOD_0FF0_PREFIX_3
) },
4342 { "maskmovq", { MX
, MS
}, PREFIX_OPCODE
},
4344 { "maskmovdqu", { XM
, XS
}, PREFIX_OPCODE
},
4351 { "pblendvb", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4358 { "blendvps", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4365 { "blendvpd", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4372 { "ptest", { XM
, EXx
}, PREFIX_OPCODE
},
4379 { "pmovsxbw", { XM
, EXq
}, PREFIX_OPCODE
},
4386 { "pmovsxbd", { XM
, EXd
}, PREFIX_OPCODE
},
4393 { "pmovsxbq", { XM
, EXw
}, PREFIX_OPCODE
},
4400 { "pmovsxwd", { XM
, EXq
}, PREFIX_OPCODE
},
4407 { "pmovsxwq", { XM
, EXd
}, PREFIX_OPCODE
},
4414 { "pmovsxdq", { XM
, EXq
}, PREFIX_OPCODE
},
4421 { "pmuldq", { XM
, EXx
}, PREFIX_OPCODE
},
4428 { "pcmpeqq", { XM
, EXx
}, PREFIX_OPCODE
},
4435 { MOD_TABLE (MOD_0F382A_PREFIX_2
) },
4442 { "packusdw", { XM
, EXx
}, PREFIX_OPCODE
},
4449 { "pmovzxbw", { XM
, EXq
}, PREFIX_OPCODE
},
4456 { "pmovzxbd", { XM
, EXd
}, PREFIX_OPCODE
},
4463 { "pmovzxbq", { XM
, EXw
}, PREFIX_OPCODE
},
4470 { "pmovzxwd", { XM
, EXq
}, PREFIX_OPCODE
},
4477 { "pmovzxwq", { XM
, EXd
}, PREFIX_OPCODE
},
4484 { "pmovzxdq", { XM
, EXq
}, PREFIX_OPCODE
},
4491 { "pcmpgtq", { XM
, EXx
}, PREFIX_OPCODE
},
4498 { "pminsb", { XM
, EXx
}, PREFIX_OPCODE
},
4505 { "pminsd", { XM
, EXx
}, PREFIX_OPCODE
},
4512 { "pminuw", { XM
, EXx
}, PREFIX_OPCODE
},
4519 { "pminud", { XM
, EXx
}, PREFIX_OPCODE
},
4526 { "pmaxsb", { XM
, EXx
}, PREFIX_OPCODE
},
4533 { "pmaxsd", { XM
, EXx
}, PREFIX_OPCODE
},
4540 { "pmaxuw", { XM
, EXx
}, PREFIX_OPCODE
},
4547 { "pmaxud", { XM
, EXx
}, PREFIX_OPCODE
},
4554 { "pmulld", { XM
, EXx
}, PREFIX_OPCODE
},
4561 { "phminposuw", { XM
, EXx
}, PREFIX_OPCODE
},
4568 { "invept", { Gm
, Mo
}, PREFIX_OPCODE
},
4575 { "invvpid", { Gm
, Mo
}, PREFIX_OPCODE
},
4582 { "invpcid", { Gm
, M
}, PREFIX_OPCODE
},
4587 { "sha1nexte", { XM
, EXxmm
}, PREFIX_OPCODE
},
4592 { "sha1msg1", { XM
, EXxmm
}, PREFIX_OPCODE
},
4597 { "sha1msg2", { XM
, EXxmm
}, PREFIX_OPCODE
},
4602 { "sha256rnds2", { XM
, EXxmm
, XMM0
}, PREFIX_OPCODE
},
4607 { "sha256msg1", { XM
, EXxmm
}, PREFIX_OPCODE
},
4612 { "sha256msg2", { XM
, EXxmm
}, PREFIX_OPCODE
},
4619 { "gf2p8mulb", { XM
, EXxmm
}, PREFIX_OPCODE
},
4626 { "aesimc", { XM
, EXx
}, PREFIX_OPCODE
},
4633 { "aesenc", { XM
, EXx
}, PREFIX_OPCODE
},
4640 { "aesenclast", { XM
, EXx
}, PREFIX_OPCODE
},
4647 { "aesdec", { XM
, EXx
}, PREFIX_OPCODE
},
4654 { "aesdeclast", { XM
, EXx
}, PREFIX_OPCODE
},
4659 { "movbeS", { Gv
, { MOVBE_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4661 { "movbeS", { Gv
, { MOVBE_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4662 { "crc32", { Gdq
, { CRC32_Fixup
, b_mode
} }, PREFIX_OPCODE
},
4667 { "movbeS", { { MOVBE_Fixup
, v_mode
}, Gv
}, PREFIX_OPCODE
},
4669 { "movbeS", { { MOVBE_Fixup
, v_mode
}, Gv
}, PREFIX_OPCODE
},
4670 { "crc32", { Gdq
, { CRC32_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4677 { MOD_TABLE (MOD_0F38F5_PREFIX_2
) },
4682 { MOD_TABLE (MOD_0F38F6_PREFIX_0
) },
4683 { "adoxS", { Gdq
, Edq
}, PREFIX_OPCODE
},
4684 { "adcxS", { Gdq
, Edq
}, PREFIX_OPCODE
},
4692 { MOD_TABLE (MOD_0F38F8_PREFIX_2
) },
4697 { MOD_TABLE (MOD_0F38F9_PREFIX_0
) },
4704 { "roundps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4711 { "roundpd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4718 { "roundss", { XM
, EXd
, Ib
}, PREFIX_OPCODE
},
4725 { "roundsd", { XM
, EXq
, Ib
}, PREFIX_OPCODE
},
4732 { "blendps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4739 { "blendpd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4746 { "pblendw", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4753 { "pextrb", { Edqb
, XM
, Ib
}, PREFIX_OPCODE
},
4760 { "pextrw", { Edqw
, XM
, Ib
}, PREFIX_OPCODE
},
4767 { "pextrK", { Edq
, XM
, Ib
}, PREFIX_OPCODE
},
4774 { "extractps", { Edqd
, XM
, Ib
}, PREFIX_OPCODE
},
4781 { "pinsrb", { XM
, Edqb
, Ib
}, PREFIX_OPCODE
},
4788 { "insertps", { XM
, EXd
, Ib
}, PREFIX_OPCODE
},
4795 { "pinsrK", { XM
, Edq
, Ib
}, PREFIX_OPCODE
},
4802 { "dpps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4809 { "dppd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4816 { "mpsadbw", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4823 { "pclmulqdq", { XM
, EXx
, PCLMUL
}, PREFIX_OPCODE
},
4830 { "pcmpestrm", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, PREFIX_OPCODE
},
4837 { "pcmpestri", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, PREFIX_OPCODE
},
4844 { "pcmpistrm", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4851 { "pcmpistri", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4856 { "sha1rnds4", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4863 { "gf2p8affineqb", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4870 { "gf2p8affineinvqb", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4877 { "aeskeygenassist", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4880 /* PREFIX_VEX_0F10 */
4882 { VEX_W_TABLE (VEX_W_0F10_P_0
) },
4883 { VEX_LEN_TABLE (VEX_LEN_0F10_P_1
) },
4884 { VEX_W_TABLE (VEX_W_0F10_P_2
) },
4885 { VEX_LEN_TABLE (VEX_LEN_0F10_P_3
) },
4888 /* PREFIX_VEX_0F11 */
4890 { VEX_W_TABLE (VEX_W_0F11_P_0
) },
4891 { VEX_LEN_TABLE (VEX_LEN_0F11_P_1
) },
4892 { VEX_W_TABLE (VEX_W_0F11_P_2
) },
4893 { VEX_LEN_TABLE (VEX_LEN_0F11_P_3
) },
4896 /* PREFIX_VEX_0F12 */
4898 { MOD_TABLE (MOD_VEX_0F12_PREFIX_0
) },
4899 { VEX_W_TABLE (VEX_W_0F12_P_1
) },
4900 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2
) },
4901 { VEX_W_TABLE (VEX_W_0F12_P_3
) },
4904 /* PREFIX_VEX_0F16 */
4906 { MOD_TABLE (MOD_VEX_0F16_PREFIX_0
) },
4907 { VEX_W_TABLE (VEX_W_0F16_P_1
) },
4908 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2
) },
4911 /* PREFIX_VEX_0F2A */
4914 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1
) },
4916 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3
) },
4919 /* PREFIX_VEX_0F2C */
4922 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1
) },
4924 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3
) },
4927 /* PREFIX_VEX_0F2D */
4930 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1
) },
4932 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3
) },
4935 /* PREFIX_VEX_0F2E */
4937 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0
) },
4939 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2
) },
4942 /* PREFIX_VEX_0F2F */
4944 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0
) },
4946 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2
) },
4949 /* PREFIX_VEX_0F41 */
4951 { VEX_LEN_TABLE (VEX_LEN_0F41_P_0
) },
4953 { VEX_LEN_TABLE (VEX_LEN_0F41_P_2
) },
4956 /* PREFIX_VEX_0F42 */
4958 { VEX_LEN_TABLE (VEX_LEN_0F42_P_0
) },
4960 { VEX_LEN_TABLE (VEX_LEN_0F42_P_2
) },
4963 /* PREFIX_VEX_0F44 */
4965 { VEX_LEN_TABLE (VEX_LEN_0F44_P_0
) },
4967 { VEX_LEN_TABLE (VEX_LEN_0F44_P_2
) },
4970 /* PREFIX_VEX_0F45 */
4972 { VEX_LEN_TABLE (VEX_LEN_0F45_P_0
) },
4974 { VEX_LEN_TABLE (VEX_LEN_0F45_P_2
) },
4977 /* PREFIX_VEX_0F46 */
4979 { VEX_LEN_TABLE (VEX_LEN_0F46_P_0
) },
4981 { VEX_LEN_TABLE (VEX_LEN_0F46_P_2
) },
4984 /* PREFIX_VEX_0F47 */
4986 { VEX_LEN_TABLE (VEX_LEN_0F47_P_0
) },
4988 { VEX_LEN_TABLE (VEX_LEN_0F47_P_2
) },
4991 /* PREFIX_VEX_0F4A */
4993 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0
) },
4995 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2
) },
4998 /* PREFIX_VEX_0F4B */
5000 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0
) },
5002 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2
) },
5005 /* PREFIX_VEX_0F51 */
5007 { VEX_W_TABLE (VEX_W_0F51_P_0
) },
5008 { VEX_LEN_TABLE (VEX_LEN_0F51_P_1
) },
5009 { VEX_W_TABLE (VEX_W_0F51_P_2
) },
5010 { VEX_LEN_TABLE (VEX_LEN_0F51_P_3
) },
5013 /* PREFIX_VEX_0F52 */
5015 { VEX_W_TABLE (VEX_W_0F52_P_0
) },
5016 { VEX_LEN_TABLE (VEX_LEN_0F52_P_1
) },
5019 /* PREFIX_VEX_0F53 */
5021 { VEX_W_TABLE (VEX_W_0F53_P_0
) },
5022 { VEX_LEN_TABLE (VEX_LEN_0F53_P_1
) },
5025 /* PREFIX_VEX_0F58 */
5027 { VEX_W_TABLE (VEX_W_0F58_P_0
) },
5028 { VEX_LEN_TABLE (VEX_LEN_0F58_P_1
) },
5029 { VEX_W_TABLE (VEX_W_0F58_P_2
) },
5030 { VEX_LEN_TABLE (VEX_LEN_0F58_P_3
) },
5033 /* PREFIX_VEX_0F59 */
5035 { VEX_W_TABLE (VEX_W_0F59_P_0
) },
5036 { VEX_LEN_TABLE (VEX_LEN_0F59_P_1
) },
5037 { VEX_W_TABLE (VEX_W_0F59_P_2
) },
5038 { VEX_LEN_TABLE (VEX_LEN_0F59_P_3
) },
5041 /* PREFIX_VEX_0F5A */
5043 { VEX_W_TABLE (VEX_W_0F5A_P_0
) },
5044 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1
) },
5045 { "vcvtpd2ps%XY", { XMM
, EXx
}, 0 },
5046 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3
) },
5049 /* PREFIX_VEX_0F5B */
5051 { VEX_W_TABLE (VEX_W_0F5B_P_0
) },
5052 { VEX_W_TABLE (VEX_W_0F5B_P_1
) },
5053 { VEX_W_TABLE (VEX_W_0F5B_P_2
) },
5056 /* PREFIX_VEX_0F5C */
5058 { VEX_W_TABLE (VEX_W_0F5C_P_0
) },
5059 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1
) },
5060 { VEX_W_TABLE (VEX_W_0F5C_P_2
) },
5061 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3
) },
5064 /* PREFIX_VEX_0F5D */
5066 { VEX_W_TABLE (VEX_W_0F5D_P_0
) },
5067 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1
) },
5068 { VEX_W_TABLE (VEX_W_0F5D_P_2
) },
5069 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3
) },
5072 /* PREFIX_VEX_0F5E */
5074 { VEX_W_TABLE (VEX_W_0F5E_P_0
) },
5075 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1
) },
5076 { VEX_W_TABLE (VEX_W_0F5E_P_2
) },
5077 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3
) },
5080 /* PREFIX_VEX_0F5F */
5082 { VEX_W_TABLE (VEX_W_0F5F_P_0
) },
5083 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1
) },
5084 { VEX_W_TABLE (VEX_W_0F5F_P_2
) },
5085 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3
) },
5088 /* PREFIX_VEX_0F60 */
5092 { VEX_W_TABLE (VEX_W_0F60_P_2
) },
5095 /* PREFIX_VEX_0F61 */
5099 { VEX_W_TABLE (VEX_W_0F61_P_2
) },
5102 /* PREFIX_VEX_0F62 */
5106 { VEX_W_TABLE (VEX_W_0F62_P_2
) },
5109 /* PREFIX_VEX_0F63 */
5113 { VEX_W_TABLE (VEX_W_0F63_P_2
) },
5116 /* PREFIX_VEX_0F64 */
5120 { VEX_W_TABLE (VEX_W_0F64_P_2
) },
5123 /* PREFIX_VEX_0F65 */
5127 { VEX_W_TABLE (VEX_W_0F65_P_2
) },
5130 /* PREFIX_VEX_0F66 */
5134 { VEX_W_TABLE (VEX_W_0F66_P_2
) },
5137 /* PREFIX_VEX_0F67 */
5141 { VEX_W_TABLE (VEX_W_0F67_P_2
) },
5144 /* PREFIX_VEX_0F68 */
5148 { VEX_W_TABLE (VEX_W_0F68_P_2
) },
5151 /* PREFIX_VEX_0F69 */
5155 { VEX_W_TABLE (VEX_W_0F69_P_2
) },
5158 /* PREFIX_VEX_0F6A */
5162 { VEX_W_TABLE (VEX_W_0F6A_P_2
) },
5165 /* PREFIX_VEX_0F6B */
5169 { VEX_W_TABLE (VEX_W_0F6B_P_2
) },
5172 /* PREFIX_VEX_0F6C */
5176 { VEX_W_TABLE (VEX_W_0F6C_P_2
) },
5179 /* PREFIX_VEX_0F6D */
5183 { VEX_W_TABLE (VEX_W_0F6D_P_2
) },
5186 /* PREFIX_VEX_0F6E */
5190 { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2
) },
5193 /* PREFIX_VEX_0F6F */
5196 { VEX_W_TABLE (VEX_W_0F6F_P_1
) },
5197 { VEX_W_TABLE (VEX_W_0F6F_P_2
) },
5200 /* PREFIX_VEX_0F70 */
5203 { VEX_W_TABLE (VEX_W_0F70_P_1
) },
5204 { VEX_W_TABLE (VEX_W_0F70_P_2
) },
5205 { VEX_W_TABLE (VEX_W_0F70_P_3
) },
5208 /* PREFIX_VEX_0F71_REG_2 */
5212 { VEX_W_TABLE (VEX_W_0F71_R_2_P_2
) },
5215 /* PREFIX_VEX_0F71_REG_4 */
5219 { VEX_W_TABLE (VEX_W_0F71_R_4_P_2
) },
5222 /* PREFIX_VEX_0F71_REG_6 */
5226 { VEX_W_TABLE (VEX_W_0F71_R_6_P_2
) },
5229 /* PREFIX_VEX_0F72_REG_2 */
5233 { VEX_W_TABLE (VEX_W_0F72_R_2_P_2
) },
5236 /* PREFIX_VEX_0F72_REG_4 */
5240 { VEX_W_TABLE (VEX_W_0F72_R_4_P_2
) },
5243 /* PREFIX_VEX_0F72_REG_6 */
5247 { VEX_W_TABLE (VEX_W_0F72_R_6_P_2
) },
5250 /* PREFIX_VEX_0F73_REG_2 */
5254 { VEX_W_TABLE (VEX_W_0F73_R_2_P_2
) },
5257 /* PREFIX_VEX_0F73_REG_3 */
5261 { VEX_W_TABLE (VEX_W_0F73_R_3_P_2
) },
5264 /* PREFIX_VEX_0F73_REG_6 */
5268 { VEX_W_TABLE (VEX_W_0F73_R_6_P_2
) },
5271 /* PREFIX_VEX_0F73_REG_7 */
5275 { VEX_W_TABLE (VEX_W_0F73_R_7_P_2
) },
5278 /* PREFIX_VEX_0F74 */
5282 { VEX_W_TABLE (VEX_W_0F74_P_2
) },
5285 /* PREFIX_VEX_0F75 */
5289 { VEX_W_TABLE (VEX_W_0F75_P_2
) },
5292 /* PREFIX_VEX_0F76 */
5296 { VEX_W_TABLE (VEX_W_0F76_P_2
) },
5299 /* PREFIX_VEX_0F77 */
5301 { VEX_W_TABLE (VEX_W_0F77_P_0
) },
5304 /* PREFIX_VEX_0F7C */
5308 { VEX_W_TABLE (VEX_W_0F7C_P_2
) },
5309 { VEX_W_TABLE (VEX_W_0F7C_P_3
) },
5312 /* PREFIX_VEX_0F7D */
5316 { VEX_W_TABLE (VEX_W_0F7D_P_2
) },
5317 { VEX_W_TABLE (VEX_W_0F7D_P_3
) },
5320 /* PREFIX_VEX_0F7E */
5323 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1
) },
5324 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2
) },
5327 /* PREFIX_VEX_0F7F */
5330 { VEX_W_TABLE (VEX_W_0F7F_P_1
) },
5331 { VEX_W_TABLE (VEX_W_0F7F_P_2
) },
5334 /* PREFIX_VEX_0F90 */
5336 { VEX_LEN_TABLE (VEX_LEN_0F90_P_0
) },
5338 { VEX_LEN_TABLE (VEX_LEN_0F90_P_2
) },
5341 /* PREFIX_VEX_0F91 */
5343 { VEX_LEN_TABLE (VEX_LEN_0F91_P_0
) },
5345 { VEX_LEN_TABLE (VEX_LEN_0F91_P_2
) },
5348 /* PREFIX_VEX_0F92 */
5350 { VEX_LEN_TABLE (VEX_LEN_0F92_P_0
) },
5352 { VEX_LEN_TABLE (VEX_LEN_0F92_P_2
) },
5353 { VEX_LEN_TABLE (VEX_LEN_0F92_P_3
) },
5356 /* PREFIX_VEX_0F93 */
5358 { VEX_LEN_TABLE (VEX_LEN_0F93_P_0
) },
5360 { VEX_LEN_TABLE (VEX_LEN_0F93_P_2
) },
5361 { VEX_LEN_TABLE (VEX_LEN_0F93_P_3
) },
5364 /* PREFIX_VEX_0F98 */
5366 { VEX_LEN_TABLE (VEX_LEN_0F98_P_0
) },
5368 { VEX_LEN_TABLE (VEX_LEN_0F98_P_2
) },
5371 /* PREFIX_VEX_0F99 */
5373 { VEX_LEN_TABLE (VEX_LEN_0F99_P_0
) },
5375 { VEX_LEN_TABLE (VEX_LEN_0F99_P_2
) },
5378 /* PREFIX_VEX_0FC2 */
5380 { VEX_W_TABLE (VEX_W_0FC2_P_0
) },
5381 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1
) },
5382 { VEX_W_TABLE (VEX_W_0FC2_P_2
) },
5383 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3
) },
5386 /* PREFIX_VEX_0FC4 */
5390 { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2
) },
5393 /* PREFIX_VEX_0FC5 */
5397 { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2
) },
5400 /* PREFIX_VEX_0FD0 */
5404 { VEX_W_TABLE (VEX_W_0FD0_P_2
) },
5405 { VEX_W_TABLE (VEX_W_0FD0_P_3
) },
5408 /* PREFIX_VEX_0FD1 */
5412 { VEX_W_TABLE (VEX_W_0FD1_P_2
) },
5415 /* PREFIX_VEX_0FD2 */
5419 { VEX_W_TABLE (VEX_W_0FD2_P_2
) },
5422 /* PREFIX_VEX_0FD3 */
5426 { VEX_W_TABLE (VEX_W_0FD3_P_2
) },
5429 /* PREFIX_VEX_0FD4 */
5433 { VEX_W_TABLE (VEX_W_0FD4_P_2
) },
5436 /* PREFIX_VEX_0FD5 */
5440 { VEX_W_TABLE (VEX_W_0FD5_P_2
) },
5443 /* PREFIX_VEX_0FD6 */
5447 { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2
) },
5450 /* PREFIX_VEX_0FD7 */
5454 { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2
) },
5457 /* PREFIX_VEX_0FD8 */
5461 { VEX_W_TABLE (VEX_W_0FD8_P_2
) },
5464 /* PREFIX_VEX_0FD9 */
5468 { VEX_W_TABLE (VEX_W_0FD9_P_2
) },
5471 /* PREFIX_VEX_0FDA */
5475 { VEX_W_TABLE (VEX_W_0FDA_P_2
) },
5478 /* PREFIX_VEX_0FDB */
5482 { VEX_W_TABLE (VEX_W_0FDB_P_2
) },
5485 /* PREFIX_VEX_0FDC */
5489 { VEX_W_TABLE (VEX_W_0FDC_P_2
) },
5492 /* PREFIX_VEX_0FDD */
5496 { VEX_W_TABLE (VEX_W_0FDD_P_2
) },
5499 /* PREFIX_VEX_0FDE */
5503 { VEX_W_TABLE (VEX_W_0FDE_P_2
) },
5506 /* PREFIX_VEX_0FDF */
5510 { VEX_W_TABLE (VEX_W_0FDF_P_2
) },
5513 /* PREFIX_VEX_0FE0 */
5517 { VEX_W_TABLE (VEX_W_0FE0_P_2
) },
5520 /* PREFIX_VEX_0FE1 */
5524 { VEX_W_TABLE (VEX_W_0FE1_P_2
) },
5527 /* PREFIX_VEX_0FE2 */
5531 { VEX_W_TABLE (VEX_W_0FE2_P_2
) },
5534 /* PREFIX_VEX_0FE3 */
5538 { VEX_W_TABLE (VEX_W_0FE3_P_2
) },
5541 /* PREFIX_VEX_0FE4 */
5545 { VEX_W_TABLE (VEX_W_0FE4_P_2
) },
5548 /* PREFIX_VEX_0FE5 */
5552 { VEX_W_TABLE (VEX_W_0FE5_P_2
) },
5555 /* PREFIX_VEX_0FE6 */
5558 { VEX_W_TABLE (VEX_W_0FE6_P_1
) },
5559 { VEX_W_TABLE (VEX_W_0FE6_P_2
) },
5560 { VEX_W_TABLE (VEX_W_0FE6_P_3
) },
5563 /* PREFIX_VEX_0FE7 */
5567 { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2
) },
5570 /* PREFIX_VEX_0FE8 */
5574 { VEX_W_TABLE (VEX_W_0FE8_P_2
) },
5577 /* PREFIX_VEX_0FE9 */
5581 { VEX_W_TABLE (VEX_W_0FE9_P_2
) },
5584 /* PREFIX_VEX_0FEA */
5588 { VEX_W_TABLE (VEX_W_0FEA_P_2
) },
5591 /* PREFIX_VEX_0FEB */
5595 { VEX_W_TABLE (VEX_W_0FEB_P_2
) },
5598 /* PREFIX_VEX_0FEC */
5602 { VEX_W_TABLE (VEX_W_0FEC_P_2
) },
5605 /* PREFIX_VEX_0FED */
5609 { VEX_W_TABLE (VEX_W_0FED_P_2
) },
5612 /* PREFIX_VEX_0FEE */
5616 { VEX_W_TABLE (VEX_W_0FEE_P_2
) },
5619 /* PREFIX_VEX_0FEF */
5623 { VEX_W_TABLE (VEX_W_0FEF_P_2
) },
5626 /* PREFIX_VEX_0FF0 */
5631 { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3
) },
5634 /* PREFIX_VEX_0FF1 */
5638 { VEX_W_TABLE (VEX_W_0FF1_P_2
) },
5641 /* PREFIX_VEX_0FF2 */
5645 { VEX_W_TABLE (VEX_W_0FF2_P_2
) },
5648 /* PREFIX_VEX_0FF3 */
5652 { VEX_W_TABLE (VEX_W_0FF3_P_2
) },
5655 /* PREFIX_VEX_0FF4 */
5659 { VEX_W_TABLE (VEX_W_0FF4_P_2
) },
5662 /* PREFIX_VEX_0FF5 */
5666 { VEX_W_TABLE (VEX_W_0FF5_P_2
) },
5669 /* PREFIX_VEX_0FF6 */
5673 { VEX_W_TABLE (VEX_W_0FF6_P_2
) },
5676 /* PREFIX_VEX_0FF7 */
5680 { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2
) },
5683 /* PREFIX_VEX_0FF8 */
5687 { VEX_W_TABLE (VEX_W_0FF8_P_2
) },
5690 /* PREFIX_VEX_0FF9 */
5694 { VEX_W_TABLE (VEX_W_0FF9_P_2
) },
5697 /* PREFIX_VEX_0FFA */
5701 { VEX_W_TABLE (VEX_W_0FFA_P_2
) },
5704 /* PREFIX_VEX_0FFB */
5708 { VEX_W_TABLE (VEX_W_0FFB_P_2
) },
5711 /* PREFIX_VEX_0FFC */
5715 { VEX_W_TABLE (VEX_W_0FFC_P_2
) },
5718 /* PREFIX_VEX_0FFD */
5722 { VEX_W_TABLE (VEX_W_0FFD_P_2
) },
5725 /* PREFIX_VEX_0FFE */
5729 { VEX_W_TABLE (VEX_W_0FFE_P_2
) },
5732 /* PREFIX_VEX_0F3800 */
5736 { VEX_W_TABLE (VEX_W_0F3800_P_2
) },
5739 /* PREFIX_VEX_0F3801 */
5743 { VEX_W_TABLE (VEX_W_0F3801_P_2
) },
5746 /* PREFIX_VEX_0F3802 */
5750 { VEX_W_TABLE (VEX_W_0F3802_P_2
) },
5753 /* PREFIX_VEX_0F3803 */
5757 { VEX_W_TABLE (VEX_W_0F3803_P_2
) },
5760 /* PREFIX_VEX_0F3804 */
5764 { VEX_W_TABLE (VEX_W_0F3804_P_2
) },
5767 /* PREFIX_VEX_0F3805 */
5771 { VEX_W_TABLE (VEX_W_0F3805_P_2
) },
5774 /* PREFIX_VEX_0F3806 */
5778 { VEX_W_TABLE (VEX_W_0F3806_P_2
) },
5781 /* PREFIX_VEX_0F3807 */
5785 { VEX_W_TABLE (VEX_W_0F3807_P_2
) },
5788 /* PREFIX_VEX_0F3808 */
5792 { VEX_W_TABLE (VEX_W_0F3808_P_2
) },
5795 /* PREFIX_VEX_0F3809 */
5799 { VEX_W_TABLE (VEX_W_0F3809_P_2
) },
5802 /* PREFIX_VEX_0F380A */
5806 { VEX_W_TABLE (VEX_W_0F380A_P_2
) },
5809 /* PREFIX_VEX_0F380B */
5813 { VEX_W_TABLE (VEX_W_0F380B_P_2
) },
5816 /* PREFIX_VEX_0F380C */
5820 { VEX_W_TABLE (VEX_W_0F380C_P_2
) },
5823 /* PREFIX_VEX_0F380D */
5827 { VEX_W_TABLE (VEX_W_0F380D_P_2
) },
5830 /* PREFIX_VEX_0F380E */
5834 { VEX_W_TABLE (VEX_W_0F380E_P_2
) },
5837 /* PREFIX_VEX_0F380F */
5841 { VEX_W_TABLE (VEX_W_0F380F_P_2
) },
5844 /* PREFIX_VEX_0F3813 */
5848 { "vcvtph2ps", { XM
, EXxmmq
}, 0 },
5851 /* PREFIX_VEX_0F3816 */
5855 { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2
) },
5858 /* PREFIX_VEX_0F3817 */
5862 { VEX_W_TABLE (VEX_W_0F3817_P_2
) },
5865 /* PREFIX_VEX_0F3818 */
5869 { VEX_W_TABLE (VEX_W_0F3818_P_2
) },
5872 /* PREFIX_VEX_0F3819 */
5876 { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2
) },
5879 /* PREFIX_VEX_0F381A */
5883 { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2
) },
5886 /* PREFIX_VEX_0F381C */
5890 { VEX_W_TABLE (VEX_W_0F381C_P_2
) },
5893 /* PREFIX_VEX_0F381D */
5897 { VEX_W_TABLE (VEX_W_0F381D_P_2
) },
5900 /* PREFIX_VEX_0F381E */
5904 { VEX_W_TABLE (VEX_W_0F381E_P_2
) },
5907 /* PREFIX_VEX_0F3820 */
5911 { VEX_W_TABLE (VEX_W_0F3820_P_2
) },
5914 /* PREFIX_VEX_0F3821 */
5918 { VEX_W_TABLE (VEX_W_0F3821_P_2
) },
5921 /* PREFIX_VEX_0F3822 */
5925 { VEX_W_TABLE (VEX_W_0F3822_P_2
) },
5928 /* PREFIX_VEX_0F3823 */
5932 { VEX_W_TABLE (VEX_W_0F3823_P_2
) },
5935 /* PREFIX_VEX_0F3824 */
5939 { VEX_W_TABLE (VEX_W_0F3824_P_2
) },
5942 /* PREFIX_VEX_0F3825 */
5946 { VEX_W_TABLE (VEX_W_0F3825_P_2
) },
5949 /* PREFIX_VEX_0F3828 */
5953 { VEX_W_TABLE (VEX_W_0F3828_P_2
) },
5956 /* PREFIX_VEX_0F3829 */
5960 { VEX_W_TABLE (VEX_W_0F3829_P_2
) },
5963 /* PREFIX_VEX_0F382A */
5967 { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2
) },
5970 /* PREFIX_VEX_0F382B */
5974 { VEX_W_TABLE (VEX_W_0F382B_P_2
) },
5977 /* PREFIX_VEX_0F382C */
5981 { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2
) },
5984 /* PREFIX_VEX_0F382D */
5988 { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2
) },
5991 /* PREFIX_VEX_0F382E */
5995 { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2
) },
5998 /* PREFIX_VEX_0F382F */
6002 { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2
) },
6005 /* PREFIX_VEX_0F3830 */
6009 { VEX_W_TABLE (VEX_W_0F3830_P_2
) },
6012 /* PREFIX_VEX_0F3831 */
6016 { VEX_W_TABLE (VEX_W_0F3831_P_2
) },
6019 /* PREFIX_VEX_0F3832 */
6023 { VEX_W_TABLE (VEX_W_0F3832_P_2
) },
6026 /* PREFIX_VEX_0F3833 */
6030 { VEX_W_TABLE (VEX_W_0F3833_P_2
) },
6033 /* PREFIX_VEX_0F3834 */
6037 { VEX_W_TABLE (VEX_W_0F3834_P_2
) },
6040 /* PREFIX_VEX_0F3835 */
6044 { VEX_W_TABLE (VEX_W_0F3835_P_2
) },
6047 /* PREFIX_VEX_0F3836 */
6051 { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2
) },
6054 /* PREFIX_VEX_0F3837 */
6058 { VEX_W_TABLE (VEX_W_0F3837_P_2
) },
6061 /* PREFIX_VEX_0F3838 */
6065 { VEX_W_TABLE (VEX_W_0F3838_P_2
) },
6068 /* PREFIX_VEX_0F3839 */
6072 { VEX_W_TABLE (VEX_W_0F3839_P_2
) },
6075 /* PREFIX_VEX_0F383A */
6079 { VEX_W_TABLE (VEX_W_0F383A_P_2
) },
6082 /* PREFIX_VEX_0F383B */
6086 { VEX_W_TABLE (VEX_W_0F383B_P_2
) },
6089 /* PREFIX_VEX_0F383C */
6093 { VEX_W_TABLE (VEX_W_0F383C_P_2
) },
6096 /* PREFIX_VEX_0F383D */
6100 { VEX_W_TABLE (VEX_W_0F383D_P_2
) },
6103 /* PREFIX_VEX_0F383E */
6107 { VEX_W_TABLE (VEX_W_0F383E_P_2
) },
6110 /* PREFIX_VEX_0F383F */
6114 { VEX_W_TABLE (VEX_W_0F383F_P_2
) },
6117 /* PREFIX_VEX_0F3840 */
6121 { VEX_W_TABLE (VEX_W_0F3840_P_2
) },
6124 /* PREFIX_VEX_0F3841 */
6128 { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2
) },
6131 /* PREFIX_VEX_0F3845 */
6135 { "vpsrlv%LW", { XM
, Vex
, EXx
}, 0 },
6138 /* PREFIX_VEX_0F3846 */
6142 { VEX_W_TABLE (VEX_W_0F3846_P_2
) },
6145 /* PREFIX_VEX_0F3847 */
6149 { "vpsllv%LW", { XM
, Vex
, EXx
}, 0 },
6152 /* PREFIX_VEX_0F3858 */
6156 { VEX_W_TABLE (VEX_W_0F3858_P_2
) },
6159 /* PREFIX_VEX_0F3859 */
6163 { VEX_W_TABLE (VEX_W_0F3859_P_2
) },
6166 /* PREFIX_VEX_0F385A */
6170 { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2
) },
6173 /* PREFIX_VEX_0F3878 */
6177 { VEX_W_TABLE (VEX_W_0F3878_P_2
) },
6180 /* PREFIX_VEX_0F3879 */
6184 { VEX_W_TABLE (VEX_W_0F3879_P_2
) },
6187 /* PREFIX_VEX_0F388C */
6191 { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2
) },
6194 /* PREFIX_VEX_0F388E */
6198 { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2
) },
6201 /* PREFIX_VEX_0F3890 */
6205 { "vpgatherd%LW", { XM
, MVexVSIBDWpX
, Vex
}, 0 },
6208 /* PREFIX_VEX_0F3891 */
6212 { "vpgatherq%LW", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
}, 0 },
6215 /* PREFIX_VEX_0F3892 */
6219 { "vgatherdp%XW", { XM
, MVexVSIBDWpX
, Vex
}, 0 },
6222 /* PREFIX_VEX_0F3893 */
6226 { "vgatherqp%XW", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
}, 0 },
6229 /* PREFIX_VEX_0F3896 */
6233 { "vfmaddsub132p%XW", { XM
, Vex
, EXx
}, 0 },
6236 /* PREFIX_VEX_0F3897 */
6240 { "vfmsubadd132p%XW", { XM
, Vex
, EXx
}, 0 },
6243 /* PREFIX_VEX_0F3898 */
6247 { "vfmadd132p%XW", { XM
, Vex
, EXx
}, 0 },
6250 /* PREFIX_VEX_0F3899 */
6254 { "vfmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6257 /* PREFIX_VEX_0F389A */
6261 { "vfmsub132p%XW", { XM
, Vex
, EXx
}, 0 },
6264 /* PREFIX_VEX_0F389B */
6268 { "vfmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6271 /* PREFIX_VEX_0F389C */
6275 { "vfnmadd132p%XW", { XM
, Vex
, EXx
}, 0 },
6278 /* PREFIX_VEX_0F389D */
6282 { "vfnmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6285 /* PREFIX_VEX_0F389E */
6289 { "vfnmsub132p%XW", { XM
, Vex
, EXx
}, 0 },
6292 /* PREFIX_VEX_0F389F */
6296 { "vfnmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6299 /* PREFIX_VEX_0F38A6 */
6303 { "vfmaddsub213p%XW", { XM
, Vex
, EXx
}, 0 },
6307 /* PREFIX_VEX_0F38A7 */
6311 { "vfmsubadd213p%XW", { XM
, Vex
, EXx
}, 0 },
6314 /* PREFIX_VEX_0F38A8 */
6318 { "vfmadd213p%XW", { XM
, Vex
, EXx
}, 0 },
6321 /* PREFIX_VEX_0F38A9 */
6325 { "vfmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6328 /* PREFIX_VEX_0F38AA */
6332 { "vfmsub213p%XW", { XM
, Vex
, EXx
}, 0 },
6335 /* PREFIX_VEX_0F38AB */
6339 { "vfmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6342 /* PREFIX_VEX_0F38AC */
6346 { "vfnmadd213p%XW", { XM
, Vex
, EXx
}, 0 },
6349 /* PREFIX_VEX_0F38AD */
6353 { "vfnmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6356 /* PREFIX_VEX_0F38AE */
6360 { "vfnmsub213p%XW", { XM
, Vex
, EXx
}, 0 },
6363 /* PREFIX_VEX_0F38AF */
6367 { "vfnmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6370 /* PREFIX_VEX_0F38B6 */
6374 { "vfmaddsub231p%XW", { XM
, Vex
, EXx
}, 0 },
6377 /* PREFIX_VEX_0F38B7 */
6381 { "vfmsubadd231p%XW", { XM
, Vex
, EXx
}, 0 },
6384 /* PREFIX_VEX_0F38B8 */
6388 { "vfmadd231p%XW", { XM
, Vex
, EXx
}, 0 },
6391 /* PREFIX_VEX_0F38B9 */
6395 { "vfmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6398 /* PREFIX_VEX_0F38BA */
6402 { "vfmsub231p%XW", { XM
, Vex
, EXx
}, 0 },
6405 /* PREFIX_VEX_0F38BB */
6409 { "vfmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6412 /* PREFIX_VEX_0F38BC */
6416 { "vfnmadd231p%XW", { XM
, Vex
, EXx
}, 0 },
6419 /* PREFIX_VEX_0F38BD */
6423 { "vfnmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6426 /* PREFIX_VEX_0F38BE */
6430 { "vfnmsub231p%XW", { XM
, Vex
, EXx
}, 0 },
6433 /* PREFIX_VEX_0F38BF */
6437 { "vfnmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6440 /* PREFIX_VEX_0F38CF */
6444 { VEX_W_TABLE (VEX_W_0F38CF_P_2
) },
6447 /* PREFIX_VEX_0F38DB */
6451 { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2
) },
6454 /* PREFIX_VEX_0F38DC */
6458 { "vaesenc", { XM
, Vex
, EXx
}, 0 },
6461 /* PREFIX_VEX_0F38DD */
6465 { "vaesenclast", { XM
, Vex
, EXx
}, 0 },
6468 /* PREFIX_VEX_0F38DE */
6472 { "vaesdec", { XM
, Vex
, EXx
}, 0 },
6475 /* PREFIX_VEX_0F38DF */
6479 { "vaesdeclast", { XM
, Vex
, EXx
}, 0 },
6482 /* PREFIX_VEX_0F38F2 */
6484 { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0
) },
6487 /* PREFIX_VEX_0F38F3_REG_1 */
6489 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0
) },
6492 /* PREFIX_VEX_0F38F3_REG_2 */
6494 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0
) },
6497 /* PREFIX_VEX_0F38F3_REG_3 */
6499 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0
) },
6502 /* PREFIX_VEX_0F38F5 */
6504 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0
) },
6505 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1
) },
6507 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3
) },
6510 /* PREFIX_VEX_0F38F6 */
6515 { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3
) },
6518 /* PREFIX_VEX_0F38F7 */
6520 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0
) },
6521 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1
) },
6522 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2
) },
6523 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3
) },
6526 /* PREFIX_VEX_0F3A00 */
6530 { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2
) },
6533 /* PREFIX_VEX_0F3A01 */
6537 { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2
) },
6540 /* PREFIX_VEX_0F3A02 */
6544 { VEX_W_TABLE (VEX_W_0F3A02_P_2
) },
6547 /* PREFIX_VEX_0F3A04 */
6551 { VEX_W_TABLE (VEX_W_0F3A04_P_2
) },
6554 /* PREFIX_VEX_0F3A05 */
6558 { VEX_W_TABLE (VEX_W_0F3A05_P_2
) },
6561 /* PREFIX_VEX_0F3A06 */
6565 { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2
) },
6568 /* PREFIX_VEX_0F3A08 */
6572 { VEX_W_TABLE (VEX_W_0F3A08_P_2
) },
6575 /* PREFIX_VEX_0F3A09 */
6579 { VEX_W_TABLE (VEX_W_0F3A09_P_2
) },
6582 /* PREFIX_VEX_0F3A0A */
6586 { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2
) },
6589 /* PREFIX_VEX_0F3A0B */
6593 { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2
) },
6596 /* PREFIX_VEX_0F3A0C */
6600 { VEX_W_TABLE (VEX_W_0F3A0C_P_2
) },
6603 /* PREFIX_VEX_0F3A0D */
6607 { VEX_W_TABLE (VEX_W_0F3A0D_P_2
) },
6610 /* PREFIX_VEX_0F3A0E */
6614 { VEX_W_TABLE (VEX_W_0F3A0E_P_2
) },
6617 /* PREFIX_VEX_0F3A0F */
6621 { VEX_W_TABLE (VEX_W_0F3A0F_P_2
) },
6624 /* PREFIX_VEX_0F3A14 */
6628 { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2
) },
6631 /* PREFIX_VEX_0F3A15 */
6635 { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2
) },
6638 /* PREFIX_VEX_0F3A16 */
6642 { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2
) },
6645 /* PREFIX_VEX_0F3A17 */
6649 { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2
) },
6652 /* PREFIX_VEX_0F3A18 */
6656 { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2
) },
6659 /* PREFIX_VEX_0F3A19 */
6663 { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2
) },
6666 /* PREFIX_VEX_0F3A1D */
6670 { "vcvtps2ph", { EXxmmq
, XM
, Ib
}, 0 },
6673 /* PREFIX_VEX_0F3A20 */
6677 { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2
) },
6680 /* PREFIX_VEX_0F3A21 */
6684 { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2
) },
6687 /* PREFIX_VEX_0F3A22 */
6691 { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2
) },
6694 /* PREFIX_VEX_0F3A30 */
6698 { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2
) },
6701 /* PREFIX_VEX_0F3A31 */
6705 { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2
) },
6708 /* PREFIX_VEX_0F3A32 */
6712 { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2
) },
6715 /* PREFIX_VEX_0F3A33 */
6719 { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2
) },
6722 /* PREFIX_VEX_0F3A38 */
6726 { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2
) },
6729 /* PREFIX_VEX_0F3A39 */
6733 { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2
) },
6736 /* PREFIX_VEX_0F3A40 */
6740 { VEX_W_TABLE (VEX_W_0F3A40_P_2
) },
6743 /* PREFIX_VEX_0F3A41 */
6747 { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2
) },
6750 /* PREFIX_VEX_0F3A42 */
6754 { VEX_W_TABLE (VEX_W_0F3A42_P_2
) },
6757 /* PREFIX_VEX_0F3A44 */
6761 { "vpclmulqdq", { XM
, Vex
, EXx
, PCLMUL
}, 0 },
6764 /* PREFIX_VEX_0F3A46 */
6768 { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2
) },
6771 /* PREFIX_VEX_0F3A48 */
6775 { VEX_W_TABLE (VEX_W_0F3A48_P_2
) },
6778 /* PREFIX_VEX_0F3A49 */
6782 { VEX_W_TABLE (VEX_W_0F3A49_P_2
) },
6785 /* PREFIX_VEX_0F3A4A */
6789 { VEX_W_TABLE (VEX_W_0F3A4A_P_2
) },
6792 /* PREFIX_VEX_0F3A4B */
6796 { VEX_W_TABLE (VEX_W_0F3A4B_P_2
) },
6799 /* PREFIX_VEX_0F3A4C */
6803 { VEX_W_TABLE (VEX_W_0F3A4C_P_2
) },
6806 /* PREFIX_VEX_0F3A5C */
6810 { "vfmaddsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6813 /* PREFIX_VEX_0F3A5D */
6817 { "vfmaddsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6820 /* PREFIX_VEX_0F3A5E */
6824 { "vfmsubaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6827 /* PREFIX_VEX_0F3A5F */
6831 { "vfmsubaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6834 /* PREFIX_VEX_0F3A60 */
6838 { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2
) },
6842 /* PREFIX_VEX_0F3A61 */
6846 { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2
) },
6849 /* PREFIX_VEX_0F3A62 */
6853 { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2
) },
6856 /* PREFIX_VEX_0F3A63 */
6860 { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2
) },
6863 /* PREFIX_VEX_0F3A68 */
6867 { "vfmaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6870 /* PREFIX_VEX_0F3A69 */
6874 { "vfmaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6877 /* PREFIX_VEX_0F3A6A */
6881 { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2
) },
6884 /* PREFIX_VEX_0F3A6B */
6888 { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2
) },
6891 /* PREFIX_VEX_0F3A6C */
6895 { "vfmsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6898 /* PREFIX_VEX_0F3A6D */
6902 { "vfmsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6905 /* PREFIX_VEX_0F3A6E */
6909 { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2
) },
6912 /* PREFIX_VEX_0F3A6F */
6916 { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2
) },
6919 /* PREFIX_VEX_0F3A78 */
6923 { "vfnmaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6926 /* PREFIX_VEX_0F3A79 */
6930 { "vfnmaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6933 /* PREFIX_VEX_0F3A7A */
6937 { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2
) },
6940 /* PREFIX_VEX_0F3A7B */
6944 { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2
) },
6947 /* PREFIX_VEX_0F3A7C */
6951 { "vfnmsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6955 /* PREFIX_VEX_0F3A7D */
6959 { "vfnmsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6962 /* PREFIX_VEX_0F3A7E */
6966 { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2
) },
6969 /* PREFIX_VEX_0F3A7F */
6973 { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2
) },
6976 /* PREFIX_VEX_0F3ACE */
6980 { VEX_W_TABLE (VEX_W_0F3ACE_P_2
) },
6983 /* PREFIX_VEX_0F3ACF */
6987 { VEX_W_TABLE (VEX_W_0F3ACF_P_2
) },
6990 /* PREFIX_VEX_0F3ADF */
6994 { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2
) },
6997 /* PREFIX_VEX_0F3AF0 */
7002 { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3
) },
7005 #define NEED_PREFIX_TABLE
7006 #include "i386-dis-evex.h"
7007 #undef NEED_PREFIX_TABLE
7010 static const struct dis386 x86_64_table
[][2] = {
7013 { "pushP", { es
}, 0 },
7018 { "popP", { es
}, 0 },
7023 { "pushP", { cs
}, 0 },
7028 { "pushP", { ss
}, 0 },
7033 { "popP", { ss
}, 0 },
7038 { "pushP", { ds
}, 0 },
7043 { "popP", { ds
}, 0 },
7048 { "daa", { XX
}, 0 },
7053 { "das", { XX
}, 0 },
7058 { "aaa", { XX
}, 0 },
7063 { "aas", { XX
}, 0 },
7068 { "pushaP", { XX
}, 0 },
7073 { "popaP", { XX
}, 0 },
7078 { MOD_TABLE (MOD_62_32BIT
) },
7079 { EVEX_TABLE (EVEX_0F
) },
7084 { "arpl", { Ew
, Gw
}, 0 },
7085 { "movs{lq|xd}", { Gv
, Ed
}, 0 },
7090 { "ins{R|}", { Yzr
, indirDX
}, 0 },
7091 { "ins{G|}", { Yzr
, indirDX
}, 0 },
7096 { "outs{R|}", { indirDXr
, Xz
}, 0 },
7097 { "outs{G|}", { indirDXr
, Xz
}, 0 },
7102 /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode. */
7103 { REG_TABLE (REG_80
) },
7108 { "Jcall{T|}", { Ap
}, 0 },
7113 { MOD_TABLE (MOD_C4_32BIT
) },
7114 { VEX_C4_TABLE (VEX_0F
) },
7119 { MOD_TABLE (MOD_C5_32BIT
) },
7120 { VEX_C5_TABLE (VEX_0F
) },
7125 { "into", { XX
}, 0 },
7130 { "aam", { Ib
}, 0 },
7135 { "aad", { Ib
}, 0 },
7140 { "callP", { Jv
, BND
}, 0 },
7141 { "call@", { Jv
, BND
}, 0 }
7146 { "jmpP", { Jv
, BND
}, 0 },
7147 { "jmp@", { Jv
, BND
}, 0 }
7152 { "Jjmp{T|}", { Ap
}, 0 },
7155 /* X86_64_0F01_REG_0 */
7157 { "sgdt{Q|IQ}", { M
}, 0 },
7158 { "sgdt", { M
}, 0 },
7161 /* X86_64_0F01_REG_1 */
7163 { "sidt{Q|IQ}", { M
}, 0 },
7164 { "sidt", { M
}, 0 },
7167 /* X86_64_0F01_REG_2 */
7169 { "lgdt{Q|Q}", { M
}, 0 },
7170 { "lgdt", { M
}, 0 },
7173 /* X86_64_0F01_REG_3 */
7175 { "lidt{Q|Q}", { M
}, 0 },
7176 { "lidt", { M
}, 0 },
7180 static const struct dis386 three_byte_table
[][256] = {
7182 /* THREE_BYTE_0F38 */
7185 { "pshufb", { MX
, EM
}, PREFIX_OPCODE
},
7186 { "phaddw", { MX
, EM
}, PREFIX_OPCODE
},
7187 { "phaddd", { MX
, EM
}, PREFIX_OPCODE
},
7188 { "phaddsw", { MX
, EM
}, PREFIX_OPCODE
},
7189 { "pmaddubsw", { MX
, EM
}, PREFIX_OPCODE
},
7190 { "phsubw", { MX
, EM
}, PREFIX_OPCODE
},
7191 { "phsubd", { MX
, EM
}, PREFIX_OPCODE
},
7192 { "phsubsw", { MX
, EM
}, PREFIX_OPCODE
},
7194 { "psignb", { MX
, EM
}, PREFIX_OPCODE
},
7195 { "psignw", { MX
, EM
}, PREFIX_OPCODE
},
7196 { "psignd", { MX
, EM
}, PREFIX_OPCODE
},
7197 { "pmulhrsw", { MX
, EM
}, PREFIX_OPCODE
},
7203 { PREFIX_TABLE (PREFIX_0F3810
) },
7207 { PREFIX_TABLE (PREFIX_0F3814
) },
7208 { PREFIX_TABLE (PREFIX_0F3815
) },
7210 { PREFIX_TABLE (PREFIX_0F3817
) },
7216 { "pabsb", { MX
, EM
}, PREFIX_OPCODE
},
7217 { "pabsw", { MX
, EM
}, PREFIX_OPCODE
},
7218 { "pabsd", { MX
, EM
}, PREFIX_OPCODE
},
7221 { PREFIX_TABLE (PREFIX_0F3820
) },
7222 { PREFIX_TABLE (PREFIX_0F3821
) },
7223 { PREFIX_TABLE (PREFIX_0F3822
) },
7224 { PREFIX_TABLE (PREFIX_0F3823
) },
7225 { PREFIX_TABLE (PREFIX_0F3824
) },
7226 { PREFIX_TABLE (PREFIX_0F3825
) },
7230 { PREFIX_TABLE (PREFIX_0F3828
) },
7231 { PREFIX_TABLE (PREFIX_0F3829
) },
7232 { PREFIX_TABLE (PREFIX_0F382A
) },
7233 { PREFIX_TABLE (PREFIX_0F382B
) },
7239 { PREFIX_TABLE (PREFIX_0F3830
) },
7240 { PREFIX_TABLE (PREFIX_0F3831
) },
7241 { PREFIX_TABLE (PREFIX_0F3832
) },
7242 { PREFIX_TABLE (PREFIX_0F3833
) },
7243 { PREFIX_TABLE (PREFIX_0F3834
) },
7244 { PREFIX_TABLE (PREFIX_0F3835
) },
7246 { PREFIX_TABLE (PREFIX_0F3837
) },
7248 { PREFIX_TABLE (PREFIX_0F3838
) },
7249 { PREFIX_TABLE (PREFIX_0F3839
) },
7250 { PREFIX_TABLE (PREFIX_0F383A
) },
7251 { PREFIX_TABLE (PREFIX_0F383B
) },
7252 { PREFIX_TABLE (PREFIX_0F383C
) },
7253 { PREFIX_TABLE (PREFIX_0F383D
) },
7254 { PREFIX_TABLE (PREFIX_0F383E
) },
7255 { PREFIX_TABLE (PREFIX_0F383F
) },
7257 { PREFIX_TABLE (PREFIX_0F3840
) },
7258 { PREFIX_TABLE (PREFIX_0F3841
) },
7329 { PREFIX_TABLE (PREFIX_0F3880
) },
7330 { PREFIX_TABLE (PREFIX_0F3881
) },
7331 { PREFIX_TABLE (PREFIX_0F3882
) },
7410 { PREFIX_TABLE (PREFIX_0F38C8
) },
7411 { PREFIX_TABLE (PREFIX_0F38C9
) },
7412 { PREFIX_TABLE (PREFIX_0F38CA
) },
7413 { PREFIX_TABLE (PREFIX_0F38CB
) },
7414 { PREFIX_TABLE (PREFIX_0F38CC
) },
7415 { PREFIX_TABLE (PREFIX_0F38CD
) },
7417 { PREFIX_TABLE (PREFIX_0F38CF
) },
7431 { PREFIX_TABLE (PREFIX_0F38DB
) },
7432 { PREFIX_TABLE (PREFIX_0F38DC
) },
7433 { PREFIX_TABLE (PREFIX_0F38DD
) },
7434 { PREFIX_TABLE (PREFIX_0F38DE
) },
7435 { PREFIX_TABLE (PREFIX_0F38DF
) },
7455 { PREFIX_TABLE (PREFIX_0F38F0
) },
7456 { PREFIX_TABLE (PREFIX_0F38F1
) },
7460 { PREFIX_TABLE (PREFIX_0F38F5
) },
7461 { PREFIX_TABLE (PREFIX_0F38F6
) },
7464 { PREFIX_TABLE (PREFIX_0F38F8
) },
7465 { PREFIX_TABLE (PREFIX_0F38F9
) },
7473 /* THREE_BYTE_0F3A */
7485 { PREFIX_TABLE (PREFIX_0F3A08
) },
7486 { PREFIX_TABLE (PREFIX_0F3A09
) },
7487 { PREFIX_TABLE (PREFIX_0F3A0A
) },
7488 { PREFIX_TABLE (PREFIX_0F3A0B
) },
7489 { PREFIX_TABLE (PREFIX_0F3A0C
) },
7490 { PREFIX_TABLE (PREFIX_0F3A0D
) },
7491 { PREFIX_TABLE (PREFIX_0F3A0E
) },
7492 { "palignr", { MX
, EM
, Ib
}, PREFIX_OPCODE
},
7498 { PREFIX_TABLE (PREFIX_0F3A14
) },
7499 { PREFIX_TABLE (PREFIX_0F3A15
) },
7500 { PREFIX_TABLE (PREFIX_0F3A16
) },
7501 { PREFIX_TABLE (PREFIX_0F3A17
) },
7512 { PREFIX_TABLE (PREFIX_0F3A20
) },
7513 { PREFIX_TABLE (PREFIX_0F3A21
) },
7514 { PREFIX_TABLE (PREFIX_0F3A22
) },
7548 { PREFIX_TABLE (PREFIX_0F3A40
) },
7549 { PREFIX_TABLE (PREFIX_0F3A41
) },
7550 { PREFIX_TABLE (PREFIX_0F3A42
) },
7552 { PREFIX_TABLE (PREFIX_0F3A44
) },
7584 { PREFIX_TABLE (PREFIX_0F3A60
) },
7585 { PREFIX_TABLE (PREFIX_0F3A61
) },
7586 { PREFIX_TABLE (PREFIX_0F3A62
) },
7587 { PREFIX_TABLE (PREFIX_0F3A63
) },
7705 { PREFIX_TABLE (PREFIX_0F3ACC
) },
7707 { PREFIX_TABLE (PREFIX_0F3ACE
) },
7708 { PREFIX_TABLE (PREFIX_0F3ACF
) },
7726 { PREFIX_TABLE (PREFIX_0F3ADF
) },
7766 static const struct dis386 xop_table
[][256] = {
7919 { "vpmacssww", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7920 { "vpmacsswd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7921 { "vpmacssdql", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7929 { "vpmacssdd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7930 { "vpmacssdqh", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7937 { "vpmacsww", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7938 { "vpmacswd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7939 { "vpmacsdql", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7947 { "vpmacsdd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7948 { "vpmacsdqh", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7952 { "vpcmov", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7953 { "vpperm", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7956 { "vpmadcsswd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7974 { "vpmadcswd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7986 { "vprotb", { XM
, Vex_2src_1
, Ib
}, 0 },
7987 { "vprotw", { XM
, Vex_2src_1
, Ib
}, 0 },
7988 { "vprotd", { XM
, Vex_2src_1
, Ib
}, 0 },
7989 { "vprotq", { XM
, Vex_2src_1
, Ib
}, 0 },
7999 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC
) },
8000 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD
) },
8001 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE
) },
8002 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF
) },
8035 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC
) },
8036 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED
) },
8037 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE
) },
8038 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF
) },
8062 { REG_TABLE (REG_XOP_TBM_01
) },
8063 { REG_TABLE (REG_XOP_TBM_02
) },
8081 { REG_TABLE (REG_XOP_LWPCB
) },
8205 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80
) },
8206 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81
) },
8207 { "vfrczss", { XM
, EXd
}, 0 },
8208 { "vfrczsd", { XM
, EXq
}, 0 },
8223 { "vprotb", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8224 { "vprotw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8225 { "vprotd", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8226 { "vprotq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8227 { "vpshlb", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8228 { "vpshlw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8229 { "vpshld", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8230 { "vpshlq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8232 { "vpshab", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8233 { "vpshaw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8234 { "vpshad", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8235 { "vpshaq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8278 { "vphaddbw", { XM
, EXxmm
}, 0 },
8279 { "vphaddbd", { XM
, EXxmm
}, 0 },
8280 { "vphaddbq", { XM
, EXxmm
}, 0 },
8283 { "vphaddwd", { XM
, EXxmm
}, 0 },
8284 { "vphaddwq", { XM
, EXxmm
}, 0 },
8289 { "vphadddq", { XM
, EXxmm
}, 0 },
8296 { "vphaddubw", { XM
, EXxmm
}, 0 },
8297 { "vphaddubd", { XM
, EXxmm
}, 0 },
8298 { "vphaddubq", { XM
, EXxmm
}, 0 },
8301 { "vphadduwd", { XM
, EXxmm
}, 0 },
8302 { "vphadduwq", { XM
, EXxmm
}, 0 },
8307 { "vphaddudq", { XM
, EXxmm
}, 0 },
8314 { "vphsubbw", { XM
, EXxmm
}, 0 },
8315 { "vphsubwd", { XM
, EXxmm
}, 0 },
8316 { "vphsubdq", { XM
, EXxmm
}, 0 },
8370 { "bextr", { Gv
, Ev
, Iq
}, 0 },
8372 { REG_TABLE (REG_XOP_LWP
) },
8642 static const struct dis386 vex_table
[][256] = {
8664 { PREFIX_TABLE (PREFIX_VEX_0F10
) },
8665 { PREFIX_TABLE (PREFIX_VEX_0F11
) },
8666 { PREFIX_TABLE (PREFIX_VEX_0F12
) },
8667 { MOD_TABLE (MOD_VEX_0F13
) },
8668 { VEX_W_TABLE (VEX_W_0F14
) },
8669 { VEX_W_TABLE (VEX_W_0F15
) },
8670 { PREFIX_TABLE (PREFIX_VEX_0F16
) },
8671 { MOD_TABLE (MOD_VEX_0F17
) },
8691 { VEX_W_TABLE (VEX_W_0F28
) },
8692 { VEX_W_TABLE (VEX_W_0F29
) },
8693 { PREFIX_TABLE (PREFIX_VEX_0F2A
) },
8694 { MOD_TABLE (MOD_VEX_0F2B
) },
8695 { PREFIX_TABLE (PREFIX_VEX_0F2C
) },
8696 { PREFIX_TABLE (PREFIX_VEX_0F2D
) },
8697 { PREFIX_TABLE (PREFIX_VEX_0F2E
) },
8698 { PREFIX_TABLE (PREFIX_VEX_0F2F
) },
8719 { PREFIX_TABLE (PREFIX_VEX_0F41
) },
8720 { PREFIX_TABLE (PREFIX_VEX_0F42
) },
8722 { PREFIX_TABLE (PREFIX_VEX_0F44
) },
8723 { PREFIX_TABLE (PREFIX_VEX_0F45
) },
8724 { PREFIX_TABLE (PREFIX_VEX_0F46
) },
8725 { PREFIX_TABLE (PREFIX_VEX_0F47
) },
8729 { PREFIX_TABLE (PREFIX_VEX_0F4A
) },
8730 { PREFIX_TABLE (PREFIX_VEX_0F4B
) },
8736 { MOD_TABLE (MOD_VEX_0F50
) },
8737 { PREFIX_TABLE (PREFIX_VEX_0F51
) },
8738 { PREFIX_TABLE (PREFIX_VEX_0F52
) },
8739 { PREFIX_TABLE (PREFIX_VEX_0F53
) },
8740 { "vandpX", { XM
, Vex
, EXx
}, 0 },
8741 { "vandnpX", { XM
, Vex
, EXx
}, 0 },
8742 { "vorpX", { XM
, Vex
, EXx
}, 0 },
8743 { "vxorpX", { XM
, Vex
, EXx
}, 0 },
8745 { PREFIX_TABLE (PREFIX_VEX_0F58
) },
8746 { PREFIX_TABLE (PREFIX_VEX_0F59
) },
8747 { PREFIX_TABLE (PREFIX_VEX_0F5A
) },
8748 { PREFIX_TABLE (PREFIX_VEX_0F5B
) },
8749 { PREFIX_TABLE (PREFIX_VEX_0F5C
) },
8750 { PREFIX_TABLE (PREFIX_VEX_0F5D
) },
8751 { PREFIX_TABLE (PREFIX_VEX_0F5E
) },
8752 { PREFIX_TABLE (PREFIX_VEX_0F5F
) },
8754 { PREFIX_TABLE (PREFIX_VEX_0F60
) },
8755 { PREFIX_TABLE (PREFIX_VEX_0F61
) },
8756 { PREFIX_TABLE (PREFIX_VEX_0F62
) },
8757 { PREFIX_TABLE (PREFIX_VEX_0F63
) },
8758 { PREFIX_TABLE (PREFIX_VEX_0F64
) },
8759 { PREFIX_TABLE (PREFIX_VEX_0F65
) },
8760 { PREFIX_TABLE (PREFIX_VEX_0F66
) },
8761 { PREFIX_TABLE (PREFIX_VEX_0F67
) },
8763 { PREFIX_TABLE (PREFIX_VEX_0F68
) },
8764 { PREFIX_TABLE (PREFIX_VEX_0F69
) },
8765 { PREFIX_TABLE (PREFIX_VEX_0F6A
) },
8766 { PREFIX_TABLE (PREFIX_VEX_0F6B
) },
8767 { PREFIX_TABLE (PREFIX_VEX_0F6C
) },
8768 { PREFIX_TABLE (PREFIX_VEX_0F6D
) },
8769 { PREFIX_TABLE (PREFIX_VEX_0F6E
) },
8770 { PREFIX_TABLE (PREFIX_VEX_0F6F
) },
8772 { PREFIX_TABLE (PREFIX_VEX_0F70
) },
8773 { REG_TABLE (REG_VEX_0F71
) },
8774 { REG_TABLE (REG_VEX_0F72
) },
8775 { REG_TABLE (REG_VEX_0F73
) },
8776 { PREFIX_TABLE (PREFIX_VEX_0F74
) },
8777 { PREFIX_TABLE (PREFIX_VEX_0F75
) },
8778 { PREFIX_TABLE (PREFIX_VEX_0F76
) },
8779 { PREFIX_TABLE (PREFIX_VEX_0F77
) },
8785 { PREFIX_TABLE (PREFIX_VEX_0F7C
) },
8786 { PREFIX_TABLE (PREFIX_VEX_0F7D
) },
8787 { PREFIX_TABLE (PREFIX_VEX_0F7E
) },
8788 { PREFIX_TABLE (PREFIX_VEX_0F7F
) },
8808 { PREFIX_TABLE (PREFIX_VEX_0F90
) },
8809 { PREFIX_TABLE (PREFIX_VEX_0F91
) },
8810 { PREFIX_TABLE (PREFIX_VEX_0F92
) },
8811 { PREFIX_TABLE (PREFIX_VEX_0F93
) },
8817 { PREFIX_TABLE (PREFIX_VEX_0F98
) },
8818 { PREFIX_TABLE (PREFIX_VEX_0F99
) },
8841 { REG_TABLE (REG_VEX_0FAE
) },
8864 { PREFIX_TABLE (PREFIX_VEX_0FC2
) },
8866 { PREFIX_TABLE (PREFIX_VEX_0FC4
) },
8867 { PREFIX_TABLE (PREFIX_VEX_0FC5
) },
8868 { "vshufpX", { XM
, Vex
, EXx
, Ib
}, 0 },
8880 { PREFIX_TABLE (PREFIX_VEX_0FD0
) },
8881 { PREFIX_TABLE (PREFIX_VEX_0FD1
) },
8882 { PREFIX_TABLE (PREFIX_VEX_0FD2
) },
8883 { PREFIX_TABLE (PREFIX_VEX_0FD3
) },
8884 { PREFIX_TABLE (PREFIX_VEX_0FD4
) },
8885 { PREFIX_TABLE (PREFIX_VEX_0FD5
) },
8886 { PREFIX_TABLE (PREFIX_VEX_0FD6
) },
8887 { PREFIX_TABLE (PREFIX_VEX_0FD7
) },
8889 { PREFIX_TABLE (PREFIX_VEX_0FD8
) },
8890 { PREFIX_TABLE (PREFIX_VEX_0FD9
) },
8891 { PREFIX_TABLE (PREFIX_VEX_0FDA
) },
8892 { PREFIX_TABLE (PREFIX_VEX_0FDB
) },
8893 { PREFIX_TABLE (PREFIX_VEX_0FDC
) },
8894 { PREFIX_TABLE (PREFIX_VEX_0FDD
) },
8895 { PREFIX_TABLE (PREFIX_VEX_0FDE
) },
8896 { PREFIX_TABLE (PREFIX_VEX_0FDF
) },
8898 { PREFIX_TABLE (PREFIX_VEX_0FE0
) },
8899 { PREFIX_TABLE (PREFIX_VEX_0FE1
) },
8900 { PREFIX_TABLE (PREFIX_VEX_0FE2
) },
8901 { PREFIX_TABLE (PREFIX_VEX_0FE3
) },
8902 { PREFIX_TABLE (PREFIX_VEX_0FE4
) },
8903 { PREFIX_TABLE (PREFIX_VEX_0FE5
) },
8904 { PREFIX_TABLE (PREFIX_VEX_0FE6
) },
8905 { PREFIX_TABLE (PREFIX_VEX_0FE7
) },
8907 { PREFIX_TABLE (PREFIX_VEX_0FE8
) },
8908 { PREFIX_TABLE (PREFIX_VEX_0FE9
) },
8909 { PREFIX_TABLE (PREFIX_VEX_0FEA
) },
8910 { PREFIX_TABLE (PREFIX_VEX_0FEB
) },
8911 { PREFIX_TABLE (PREFIX_VEX_0FEC
) },
8912 { PREFIX_TABLE (PREFIX_VEX_0FED
) },
8913 { PREFIX_TABLE (PREFIX_VEX_0FEE
) },
8914 { PREFIX_TABLE (PREFIX_VEX_0FEF
) },
8916 { PREFIX_TABLE (PREFIX_VEX_0FF0
) },
8917 { PREFIX_TABLE (PREFIX_VEX_0FF1
) },
8918 { PREFIX_TABLE (PREFIX_VEX_0FF2
) },
8919 { PREFIX_TABLE (PREFIX_VEX_0FF3
) },
8920 { PREFIX_TABLE (PREFIX_VEX_0FF4
) },
8921 { PREFIX_TABLE (PREFIX_VEX_0FF5
) },
8922 { PREFIX_TABLE (PREFIX_VEX_0FF6
) },
8923 { PREFIX_TABLE (PREFIX_VEX_0FF7
) },
8925 { PREFIX_TABLE (PREFIX_VEX_0FF8
) },
8926 { PREFIX_TABLE (PREFIX_VEX_0FF9
) },
8927 { PREFIX_TABLE (PREFIX_VEX_0FFA
) },
8928 { PREFIX_TABLE (PREFIX_VEX_0FFB
) },
8929 { PREFIX_TABLE (PREFIX_VEX_0FFC
) },
8930 { PREFIX_TABLE (PREFIX_VEX_0FFD
) },
8931 { PREFIX_TABLE (PREFIX_VEX_0FFE
) },
8937 { PREFIX_TABLE (PREFIX_VEX_0F3800
) },
8938 { PREFIX_TABLE (PREFIX_VEX_0F3801
) },
8939 { PREFIX_TABLE (PREFIX_VEX_0F3802
) },
8940 { PREFIX_TABLE (PREFIX_VEX_0F3803
) },
8941 { PREFIX_TABLE (PREFIX_VEX_0F3804
) },
8942 { PREFIX_TABLE (PREFIX_VEX_0F3805
) },
8943 { PREFIX_TABLE (PREFIX_VEX_0F3806
) },
8944 { PREFIX_TABLE (PREFIX_VEX_0F3807
) },
8946 { PREFIX_TABLE (PREFIX_VEX_0F3808
) },
8947 { PREFIX_TABLE (PREFIX_VEX_0F3809
) },
8948 { PREFIX_TABLE (PREFIX_VEX_0F380A
) },
8949 { PREFIX_TABLE (PREFIX_VEX_0F380B
) },
8950 { PREFIX_TABLE (PREFIX_VEX_0F380C
) },
8951 { PREFIX_TABLE (PREFIX_VEX_0F380D
) },
8952 { PREFIX_TABLE (PREFIX_VEX_0F380E
) },
8953 { PREFIX_TABLE (PREFIX_VEX_0F380F
) },
8958 { PREFIX_TABLE (PREFIX_VEX_0F3813
) },
8961 { PREFIX_TABLE (PREFIX_VEX_0F3816
) },
8962 { PREFIX_TABLE (PREFIX_VEX_0F3817
) },
8964 { PREFIX_TABLE (PREFIX_VEX_0F3818
) },
8965 { PREFIX_TABLE (PREFIX_VEX_0F3819
) },
8966 { PREFIX_TABLE (PREFIX_VEX_0F381A
) },
8968 { PREFIX_TABLE (PREFIX_VEX_0F381C
) },
8969 { PREFIX_TABLE (PREFIX_VEX_0F381D
) },
8970 { PREFIX_TABLE (PREFIX_VEX_0F381E
) },
8973 { PREFIX_TABLE (PREFIX_VEX_0F3820
) },
8974 { PREFIX_TABLE (PREFIX_VEX_0F3821
) },
8975 { PREFIX_TABLE (PREFIX_VEX_0F3822
) },
8976 { PREFIX_TABLE (PREFIX_VEX_0F3823
) },
8977 { PREFIX_TABLE (PREFIX_VEX_0F3824
) },
8978 { PREFIX_TABLE (PREFIX_VEX_0F3825
) },
8982 { PREFIX_TABLE (PREFIX_VEX_0F3828
) },
8983 { PREFIX_TABLE (PREFIX_VEX_0F3829
) },
8984 { PREFIX_TABLE (PREFIX_VEX_0F382A
) },
8985 { PREFIX_TABLE (PREFIX_VEX_0F382B
) },
8986 { PREFIX_TABLE (PREFIX_VEX_0F382C
) },
8987 { PREFIX_TABLE (PREFIX_VEX_0F382D
) },
8988 { PREFIX_TABLE (PREFIX_VEX_0F382E
) },
8989 { PREFIX_TABLE (PREFIX_VEX_0F382F
) },
8991 { PREFIX_TABLE (PREFIX_VEX_0F3830
) },
8992 { PREFIX_TABLE (PREFIX_VEX_0F3831
) },
8993 { PREFIX_TABLE (PREFIX_VEX_0F3832
) },
8994 { PREFIX_TABLE (PREFIX_VEX_0F3833
) },
8995 { PREFIX_TABLE (PREFIX_VEX_0F3834
) },
8996 { PREFIX_TABLE (PREFIX_VEX_0F3835
) },
8997 { PREFIX_TABLE (PREFIX_VEX_0F3836
) },
8998 { PREFIX_TABLE (PREFIX_VEX_0F3837
) },
9000 { PREFIX_TABLE (PREFIX_VEX_0F3838
) },
9001 { PREFIX_TABLE (PREFIX_VEX_0F3839
) },
9002 { PREFIX_TABLE (PREFIX_VEX_0F383A
) },
9003 { PREFIX_TABLE (PREFIX_VEX_0F383B
) },
9004 { PREFIX_TABLE (PREFIX_VEX_0F383C
) },
9005 { PREFIX_TABLE (PREFIX_VEX_0F383D
) },
9006 { PREFIX_TABLE (PREFIX_VEX_0F383E
) },
9007 { PREFIX_TABLE (PREFIX_VEX_0F383F
) },
9009 { PREFIX_TABLE (PREFIX_VEX_0F3840
) },
9010 { PREFIX_TABLE (PREFIX_VEX_0F3841
) },
9014 { PREFIX_TABLE (PREFIX_VEX_0F3845
) },
9015 { PREFIX_TABLE (PREFIX_VEX_0F3846
) },
9016 { PREFIX_TABLE (PREFIX_VEX_0F3847
) },
9036 { PREFIX_TABLE (PREFIX_VEX_0F3858
) },
9037 { PREFIX_TABLE (PREFIX_VEX_0F3859
) },
9038 { PREFIX_TABLE (PREFIX_VEX_0F385A
) },
9072 { PREFIX_TABLE (PREFIX_VEX_0F3878
) },
9073 { PREFIX_TABLE (PREFIX_VEX_0F3879
) },
9094 { PREFIX_TABLE (PREFIX_VEX_0F388C
) },
9096 { PREFIX_TABLE (PREFIX_VEX_0F388E
) },
9099 { PREFIX_TABLE (PREFIX_VEX_0F3890
) },
9100 { PREFIX_TABLE (PREFIX_VEX_0F3891
) },
9101 { PREFIX_TABLE (PREFIX_VEX_0F3892
) },
9102 { PREFIX_TABLE (PREFIX_VEX_0F3893
) },
9105 { PREFIX_TABLE (PREFIX_VEX_0F3896
) },
9106 { PREFIX_TABLE (PREFIX_VEX_0F3897
) },
9108 { PREFIX_TABLE (PREFIX_VEX_0F3898
) },
9109 { PREFIX_TABLE (PREFIX_VEX_0F3899
) },
9110 { PREFIX_TABLE (PREFIX_VEX_0F389A
) },
9111 { PREFIX_TABLE (PREFIX_VEX_0F389B
) },
9112 { PREFIX_TABLE (PREFIX_VEX_0F389C
) },
9113 { PREFIX_TABLE (PREFIX_VEX_0F389D
) },
9114 { PREFIX_TABLE (PREFIX_VEX_0F389E
) },
9115 { PREFIX_TABLE (PREFIX_VEX_0F389F
) },
9123 { PREFIX_TABLE (PREFIX_VEX_0F38A6
) },
9124 { PREFIX_TABLE (PREFIX_VEX_0F38A7
) },
9126 { PREFIX_TABLE (PREFIX_VEX_0F38A8
) },
9127 { PREFIX_TABLE (PREFIX_VEX_0F38A9
) },
9128 { PREFIX_TABLE (PREFIX_VEX_0F38AA
) },
9129 { PREFIX_TABLE (PREFIX_VEX_0F38AB
) },
9130 { PREFIX_TABLE (PREFIX_VEX_0F38AC
) },
9131 { PREFIX_TABLE (PREFIX_VEX_0F38AD
) },
9132 { PREFIX_TABLE (PREFIX_VEX_0F38AE
) },
9133 { PREFIX_TABLE (PREFIX_VEX_0F38AF
) },
9141 { PREFIX_TABLE (PREFIX_VEX_0F38B6
) },
9142 { PREFIX_TABLE (PREFIX_VEX_0F38B7
) },
9144 { PREFIX_TABLE (PREFIX_VEX_0F38B8
) },
9145 { PREFIX_TABLE (PREFIX_VEX_0F38B9
) },
9146 { PREFIX_TABLE (PREFIX_VEX_0F38BA
) },
9147 { PREFIX_TABLE (PREFIX_VEX_0F38BB
) },
9148 { PREFIX_TABLE (PREFIX_VEX_0F38BC
) },
9149 { PREFIX_TABLE (PREFIX_VEX_0F38BD
) },
9150 { PREFIX_TABLE (PREFIX_VEX_0F38BE
) },
9151 { PREFIX_TABLE (PREFIX_VEX_0F38BF
) },
9169 { PREFIX_TABLE (PREFIX_VEX_0F38CF
) },
9183 { PREFIX_TABLE (PREFIX_VEX_0F38DB
) },
9184 { PREFIX_TABLE (PREFIX_VEX_0F38DC
) },
9185 { PREFIX_TABLE (PREFIX_VEX_0F38DD
) },
9186 { PREFIX_TABLE (PREFIX_VEX_0F38DE
) },
9187 { PREFIX_TABLE (PREFIX_VEX_0F38DF
) },
9209 { PREFIX_TABLE (PREFIX_VEX_0F38F2
) },
9210 { REG_TABLE (REG_VEX_0F38F3
) },
9212 { PREFIX_TABLE (PREFIX_VEX_0F38F5
) },
9213 { PREFIX_TABLE (PREFIX_VEX_0F38F6
) },
9214 { PREFIX_TABLE (PREFIX_VEX_0F38F7
) },
9228 { PREFIX_TABLE (PREFIX_VEX_0F3A00
) },
9229 { PREFIX_TABLE (PREFIX_VEX_0F3A01
) },
9230 { PREFIX_TABLE (PREFIX_VEX_0F3A02
) },
9232 { PREFIX_TABLE (PREFIX_VEX_0F3A04
) },
9233 { PREFIX_TABLE (PREFIX_VEX_0F3A05
) },
9234 { PREFIX_TABLE (PREFIX_VEX_0F3A06
) },
9237 { PREFIX_TABLE (PREFIX_VEX_0F3A08
) },
9238 { PREFIX_TABLE (PREFIX_VEX_0F3A09
) },
9239 { PREFIX_TABLE (PREFIX_VEX_0F3A0A
) },
9240 { PREFIX_TABLE (PREFIX_VEX_0F3A0B
) },
9241 { PREFIX_TABLE (PREFIX_VEX_0F3A0C
) },
9242 { PREFIX_TABLE (PREFIX_VEX_0F3A0D
) },
9243 { PREFIX_TABLE (PREFIX_VEX_0F3A0E
) },
9244 { PREFIX_TABLE (PREFIX_VEX_0F3A0F
) },
9250 { PREFIX_TABLE (PREFIX_VEX_0F3A14
) },
9251 { PREFIX_TABLE (PREFIX_VEX_0F3A15
) },
9252 { PREFIX_TABLE (PREFIX_VEX_0F3A16
) },
9253 { PREFIX_TABLE (PREFIX_VEX_0F3A17
) },
9255 { PREFIX_TABLE (PREFIX_VEX_0F3A18
) },
9256 { PREFIX_TABLE (PREFIX_VEX_0F3A19
) },
9260 { PREFIX_TABLE (PREFIX_VEX_0F3A1D
) },
9264 { PREFIX_TABLE (PREFIX_VEX_0F3A20
) },
9265 { PREFIX_TABLE (PREFIX_VEX_0F3A21
) },
9266 { PREFIX_TABLE (PREFIX_VEX_0F3A22
) },
9282 { PREFIX_TABLE (PREFIX_VEX_0F3A30
) },
9283 { PREFIX_TABLE (PREFIX_VEX_0F3A31
) },
9284 { PREFIX_TABLE (PREFIX_VEX_0F3A32
) },
9285 { PREFIX_TABLE (PREFIX_VEX_0F3A33
) },
9291 { PREFIX_TABLE (PREFIX_VEX_0F3A38
) },
9292 { PREFIX_TABLE (PREFIX_VEX_0F3A39
) },
9300 { PREFIX_TABLE (PREFIX_VEX_0F3A40
) },
9301 { PREFIX_TABLE (PREFIX_VEX_0F3A41
) },
9302 { PREFIX_TABLE (PREFIX_VEX_0F3A42
) },
9304 { PREFIX_TABLE (PREFIX_VEX_0F3A44
) },
9306 { PREFIX_TABLE (PREFIX_VEX_0F3A46
) },
9309 { PREFIX_TABLE (PREFIX_VEX_0F3A48
) },
9310 { PREFIX_TABLE (PREFIX_VEX_0F3A49
) },
9311 { PREFIX_TABLE (PREFIX_VEX_0F3A4A
) },
9312 { PREFIX_TABLE (PREFIX_VEX_0F3A4B
) },
9313 { PREFIX_TABLE (PREFIX_VEX_0F3A4C
) },
9331 { PREFIX_TABLE (PREFIX_VEX_0F3A5C
) },
9332 { PREFIX_TABLE (PREFIX_VEX_0F3A5D
) },
9333 { PREFIX_TABLE (PREFIX_VEX_0F3A5E
) },
9334 { PREFIX_TABLE (PREFIX_VEX_0F3A5F
) },
9336 { PREFIX_TABLE (PREFIX_VEX_0F3A60
) },
9337 { PREFIX_TABLE (PREFIX_VEX_0F3A61
) },
9338 { PREFIX_TABLE (PREFIX_VEX_0F3A62
) },
9339 { PREFIX_TABLE (PREFIX_VEX_0F3A63
) },
9345 { PREFIX_TABLE (PREFIX_VEX_0F3A68
) },
9346 { PREFIX_TABLE (PREFIX_VEX_0F3A69
) },
9347 { PREFIX_TABLE (PREFIX_VEX_0F3A6A
) },
9348 { PREFIX_TABLE (PREFIX_VEX_0F3A6B
) },
9349 { PREFIX_TABLE (PREFIX_VEX_0F3A6C
) },
9350 { PREFIX_TABLE (PREFIX_VEX_0F3A6D
) },
9351 { PREFIX_TABLE (PREFIX_VEX_0F3A6E
) },
9352 { PREFIX_TABLE (PREFIX_VEX_0F3A6F
) },
9363 { PREFIX_TABLE (PREFIX_VEX_0F3A78
) },
9364 { PREFIX_TABLE (PREFIX_VEX_0F3A79
) },
9365 { PREFIX_TABLE (PREFIX_VEX_0F3A7A
) },
9366 { PREFIX_TABLE (PREFIX_VEX_0F3A7B
) },
9367 { PREFIX_TABLE (PREFIX_VEX_0F3A7C
) },
9368 { PREFIX_TABLE (PREFIX_VEX_0F3A7D
) },
9369 { PREFIX_TABLE (PREFIX_VEX_0F3A7E
) },
9370 { PREFIX_TABLE (PREFIX_VEX_0F3A7F
) },
9459 { PREFIX_TABLE(PREFIX_VEX_0F3ACE
) },
9460 { PREFIX_TABLE(PREFIX_VEX_0F3ACF
) },
9478 { PREFIX_TABLE (PREFIX_VEX_0F3ADF
) },
9498 { PREFIX_TABLE (PREFIX_VEX_0F3AF0
) },
9518 #define NEED_OPCODE_TABLE
9519 #include "i386-dis-evex.h"
9520 #undef NEED_OPCODE_TABLE
9521 static const struct dis386 vex_len_table
[][2] = {
9522 /* VEX_LEN_0F10_P_1 */
9524 { VEX_W_TABLE (VEX_W_0F10_P_1
) },
9525 { VEX_W_TABLE (VEX_W_0F10_P_1
) },
9528 /* VEX_LEN_0F10_P_3 */
9530 { VEX_W_TABLE (VEX_W_0F10_P_3
) },
9531 { VEX_W_TABLE (VEX_W_0F10_P_3
) },
9534 /* VEX_LEN_0F11_P_1 */
9536 { VEX_W_TABLE (VEX_W_0F11_P_1
) },
9537 { VEX_W_TABLE (VEX_W_0F11_P_1
) },
9540 /* VEX_LEN_0F11_P_3 */
9542 { VEX_W_TABLE (VEX_W_0F11_P_3
) },
9543 { VEX_W_TABLE (VEX_W_0F11_P_3
) },
9546 /* VEX_LEN_0F12_P_0_M_0 */
9548 { VEX_W_TABLE (VEX_W_0F12_P_0_M_0
) },
9551 /* VEX_LEN_0F12_P_0_M_1 */
9553 { VEX_W_TABLE (VEX_W_0F12_P_0_M_1
) },
9556 /* VEX_LEN_0F12_P_2 */
9558 { VEX_W_TABLE (VEX_W_0F12_P_2
) },
9561 /* VEX_LEN_0F13_M_0 */
9563 { VEX_W_TABLE (VEX_W_0F13_M_0
) },
9566 /* VEX_LEN_0F16_P_0_M_0 */
9568 { VEX_W_TABLE (VEX_W_0F16_P_0_M_0
) },
9571 /* VEX_LEN_0F16_P_0_M_1 */
9573 { VEX_W_TABLE (VEX_W_0F16_P_0_M_1
) },
9576 /* VEX_LEN_0F16_P_2 */
9578 { VEX_W_TABLE (VEX_W_0F16_P_2
) },
9581 /* VEX_LEN_0F17_M_0 */
9583 { VEX_W_TABLE (VEX_W_0F17_M_0
) },
9586 /* VEX_LEN_0F2A_P_1 */
9588 { "vcvtsi2ss%LQ", { XMScalar
, VexScalar
, Ev
}, 0 },
9589 { "vcvtsi2ss%LQ", { XMScalar
, VexScalar
, Ev
}, 0 },
9592 /* VEX_LEN_0F2A_P_3 */
9594 { "vcvtsi2sd%LQ", { XMScalar
, VexScalar
, Ev
}, 0 },
9595 { "vcvtsi2sd%LQ", { XMScalar
, VexScalar
, Ev
}, 0 },
9598 /* VEX_LEN_0F2C_P_1 */
9600 { "vcvttss2si", { Gv
, EXdScalar
}, 0 },
9601 { "vcvttss2si", { Gv
, EXdScalar
}, 0 },
9604 /* VEX_LEN_0F2C_P_3 */
9606 { "vcvttsd2si", { Gv
, EXqScalar
}, 0 },
9607 { "vcvttsd2si", { Gv
, EXqScalar
}, 0 },
9610 /* VEX_LEN_0F2D_P_1 */
9612 { "vcvtss2si", { Gv
, EXdScalar
}, 0 },
9613 { "vcvtss2si", { Gv
, EXdScalar
}, 0 },
9616 /* VEX_LEN_0F2D_P_3 */
9618 { "vcvtsd2si", { Gv
, EXqScalar
}, 0 },
9619 { "vcvtsd2si", { Gv
, EXqScalar
}, 0 },
9622 /* VEX_LEN_0F2E_P_0 */
9624 { VEX_W_TABLE (VEX_W_0F2E_P_0
) },
9625 { VEX_W_TABLE (VEX_W_0F2E_P_0
) },
9628 /* VEX_LEN_0F2E_P_2 */
9630 { VEX_W_TABLE (VEX_W_0F2E_P_2
) },
9631 { VEX_W_TABLE (VEX_W_0F2E_P_2
) },
9634 /* VEX_LEN_0F2F_P_0 */
9636 { VEX_W_TABLE (VEX_W_0F2F_P_0
) },
9637 { VEX_W_TABLE (VEX_W_0F2F_P_0
) },
9640 /* VEX_LEN_0F2F_P_2 */
9642 { VEX_W_TABLE (VEX_W_0F2F_P_2
) },
9643 { VEX_W_TABLE (VEX_W_0F2F_P_2
) },
9646 /* VEX_LEN_0F41_P_0 */
9649 { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1
) },
9651 /* VEX_LEN_0F41_P_2 */
9654 { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1
) },
9656 /* VEX_LEN_0F42_P_0 */
9659 { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1
) },
9661 /* VEX_LEN_0F42_P_2 */
9664 { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1
) },
9666 /* VEX_LEN_0F44_P_0 */
9668 { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0
) },
9670 /* VEX_LEN_0F44_P_2 */
9672 { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0
) },
9674 /* VEX_LEN_0F45_P_0 */
9677 { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1
) },
9679 /* VEX_LEN_0F45_P_2 */
9682 { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1
) },
9684 /* VEX_LEN_0F46_P_0 */
9687 { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1
) },
9689 /* VEX_LEN_0F46_P_2 */
9692 { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1
) },
9694 /* VEX_LEN_0F47_P_0 */
9697 { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1
) },
9699 /* VEX_LEN_0F47_P_2 */
9702 { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1
) },
9704 /* VEX_LEN_0F4A_P_0 */
9707 { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1
) },
9709 /* VEX_LEN_0F4A_P_2 */
9712 { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1
) },
9714 /* VEX_LEN_0F4B_P_0 */
9717 { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1
) },
9719 /* VEX_LEN_0F4B_P_2 */
9722 { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1
) },
9725 /* VEX_LEN_0F51_P_1 */
9727 { VEX_W_TABLE (VEX_W_0F51_P_1
) },
9728 { VEX_W_TABLE (VEX_W_0F51_P_1
) },
9731 /* VEX_LEN_0F51_P_3 */
9733 { VEX_W_TABLE (VEX_W_0F51_P_3
) },
9734 { VEX_W_TABLE (VEX_W_0F51_P_3
) },
9737 /* VEX_LEN_0F52_P_1 */
9739 { VEX_W_TABLE (VEX_W_0F52_P_1
) },
9740 { VEX_W_TABLE (VEX_W_0F52_P_1
) },
9743 /* VEX_LEN_0F53_P_1 */
9745 { VEX_W_TABLE (VEX_W_0F53_P_1
) },
9746 { VEX_W_TABLE (VEX_W_0F53_P_1
) },
9749 /* VEX_LEN_0F58_P_1 */
9751 { VEX_W_TABLE (VEX_W_0F58_P_1
) },
9752 { VEX_W_TABLE (VEX_W_0F58_P_1
) },
9755 /* VEX_LEN_0F58_P_3 */
9757 { VEX_W_TABLE (VEX_W_0F58_P_3
) },
9758 { VEX_W_TABLE (VEX_W_0F58_P_3
) },
9761 /* VEX_LEN_0F59_P_1 */
9763 { VEX_W_TABLE (VEX_W_0F59_P_1
) },
9764 { VEX_W_TABLE (VEX_W_0F59_P_1
) },
9767 /* VEX_LEN_0F59_P_3 */
9769 { VEX_W_TABLE (VEX_W_0F59_P_3
) },
9770 { VEX_W_TABLE (VEX_W_0F59_P_3
) },
9773 /* VEX_LEN_0F5A_P_1 */
9775 { VEX_W_TABLE (VEX_W_0F5A_P_1
) },
9776 { VEX_W_TABLE (VEX_W_0F5A_P_1
) },
9779 /* VEX_LEN_0F5A_P_3 */
9781 { VEX_W_TABLE (VEX_W_0F5A_P_3
) },
9782 { VEX_W_TABLE (VEX_W_0F5A_P_3
) },
9785 /* VEX_LEN_0F5C_P_1 */
9787 { VEX_W_TABLE (VEX_W_0F5C_P_1
) },
9788 { VEX_W_TABLE (VEX_W_0F5C_P_1
) },
9791 /* VEX_LEN_0F5C_P_3 */
9793 { VEX_W_TABLE (VEX_W_0F5C_P_3
) },
9794 { VEX_W_TABLE (VEX_W_0F5C_P_3
) },
9797 /* VEX_LEN_0F5D_P_1 */
9799 { VEX_W_TABLE (VEX_W_0F5D_P_1
) },
9800 { VEX_W_TABLE (VEX_W_0F5D_P_1
) },
9803 /* VEX_LEN_0F5D_P_3 */
9805 { VEX_W_TABLE (VEX_W_0F5D_P_3
) },
9806 { VEX_W_TABLE (VEX_W_0F5D_P_3
) },
9809 /* VEX_LEN_0F5E_P_1 */
9811 { VEX_W_TABLE (VEX_W_0F5E_P_1
) },
9812 { VEX_W_TABLE (VEX_W_0F5E_P_1
) },
9815 /* VEX_LEN_0F5E_P_3 */
9817 { VEX_W_TABLE (VEX_W_0F5E_P_3
) },
9818 { VEX_W_TABLE (VEX_W_0F5E_P_3
) },
9821 /* VEX_LEN_0F5F_P_1 */
9823 { VEX_W_TABLE (VEX_W_0F5F_P_1
) },
9824 { VEX_W_TABLE (VEX_W_0F5F_P_1
) },
9827 /* VEX_LEN_0F5F_P_3 */
9829 { VEX_W_TABLE (VEX_W_0F5F_P_3
) },
9830 { VEX_W_TABLE (VEX_W_0F5F_P_3
) },
9833 /* VEX_LEN_0F6E_P_2 */
9835 { "vmovK", { XMScalar
, Edq
}, 0 },
9836 { "vmovK", { XMScalar
, Edq
}, 0 },
9839 /* VEX_LEN_0F7E_P_1 */
9841 { VEX_W_TABLE (VEX_W_0F7E_P_1
) },
9842 { VEX_W_TABLE (VEX_W_0F7E_P_1
) },
9845 /* VEX_LEN_0F7E_P_2 */
9847 { "vmovK", { Edq
, XMScalar
}, 0 },
9848 { "vmovK", { Edq
, XMScalar
}, 0 },
9851 /* VEX_LEN_0F90_P_0 */
9853 { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0
) },
9856 /* VEX_LEN_0F90_P_2 */
9858 { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0
) },
9861 /* VEX_LEN_0F91_P_0 */
9863 { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0
) },
9866 /* VEX_LEN_0F91_P_2 */
9868 { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0
) },
9871 /* VEX_LEN_0F92_P_0 */
9873 { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0
) },
9876 /* VEX_LEN_0F92_P_2 */
9878 { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0
) },
9881 /* VEX_LEN_0F92_P_3 */
9883 { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0
) },
9886 /* VEX_LEN_0F93_P_0 */
9888 { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0
) },
9891 /* VEX_LEN_0F93_P_2 */
9893 { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0
) },
9896 /* VEX_LEN_0F93_P_3 */
9898 { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0
) },
9901 /* VEX_LEN_0F98_P_0 */
9903 { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0
) },
9906 /* VEX_LEN_0F98_P_2 */
9908 { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0
) },
9911 /* VEX_LEN_0F99_P_0 */
9913 { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0
) },
9916 /* VEX_LEN_0F99_P_2 */
9918 { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0
) },
9921 /* VEX_LEN_0FAE_R_2_M_0 */
9923 { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0
) },
9926 /* VEX_LEN_0FAE_R_3_M_0 */
9928 { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0
) },
9931 /* VEX_LEN_0FC2_P_1 */
9933 { VEX_W_TABLE (VEX_W_0FC2_P_1
) },
9934 { VEX_W_TABLE (VEX_W_0FC2_P_1
) },
9937 /* VEX_LEN_0FC2_P_3 */
9939 { VEX_W_TABLE (VEX_W_0FC2_P_3
) },
9940 { VEX_W_TABLE (VEX_W_0FC2_P_3
) },
9943 /* VEX_LEN_0FC4_P_2 */
9945 { VEX_W_TABLE (VEX_W_0FC4_P_2
) },
9948 /* VEX_LEN_0FC5_P_2 */
9950 { VEX_W_TABLE (VEX_W_0FC5_P_2
) },
9953 /* VEX_LEN_0FD6_P_2 */
9955 { VEX_W_TABLE (VEX_W_0FD6_P_2
) },
9956 { VEX_W_TABLE (VEX_W_0FD6_P_2
) },
9959 /* VEX_LEN_0FF7_P_2 */
9961 { VEX_W_TABLE (VEX_W_0FF7_P_2
) },
9964 /* VEX_LEN_0F3816_P_2 */
9967 { VEX_W_TABLE (VEX_W_0F3816_P_2
) },
9970 /* VEX_LEN_0F3819_P_2 */
9973 { VEX_W_TABLE (VEX_W_0F3819_P_2
) },
9976 /* VEX_LEN_0F381A_P_2_M_0 */
9979 { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0
) },
9982 /* VEX_LEN_0F3836_P_2 */
9985 { VEX_W_TABLE (VEX_W_0F3836_P_2
) },
9988 /* VEX_LEN_0F3841_P_2 */
9990 { VEX_W_TABLE (VEX_W_0F3841_P_2
) },
9993 /* VEX_LEN_0F385A_P_2_M_0 */
9996 { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0
) },
9999 /* VEX_LEN_0F38DB_P_2 */
10001 { VEX_W_TABLE (VEX_W_0F38DB_P_2
) },
10004 /* VEX_LEN_0F38F2_P_0 */
10006 { "andnS", { Gdq
, VexGdq
, Edq
}, 0 },
10009 /* VEX_LEN_0F38F3_R_1_P_0 */
10011 { "blsrS", { VexGdq
, Edq
}, 0 },
10014 /* VEX_LEN_0F38F3_R_2_P_0 */
10016 { "blsmskS", { VexGdq
, Edq
}, 0 },
10019 /* VEX_LEN_0F38F3_R_3_P_0 */
10021 { "blsiS", { VexGdq
, Edq
}, 0 },
10024 /* VEX_LEN_0F38F5_P_0 */
10026 { "bzhiS", { Gdq
, Edq
, VexGdq
}, 0 },
10029 /* VEX_LEN_0F38F5_P_1 */
10031 { "pextS", { Gdq
, VexGdq
, Edq
}, 0 },
10034 /* VEX_LEN_0F38F5_P_3 */
10036 { "pdepS", { Gdq
, VexGdq
, Edq
}, 0 },
10039 /* VEX_LEN_0F38F6_P_3 */
10041 { "mulxS", { Gdq
, VexGdq
, Edq
}, 0 },
10044 /* VEX_LEN_0F38F7_P_0 */
10046 { "bextrS", { Gdq
, Edq
, VexGdq
}, 0 },
10049 /* VEX_LEN_0F38F7_P_1 */
10051 { "sarxS", { Gdq
, Edq
, VexGdq
}, 0 },
10054 /* VEX_LEN_0F38F7_P_2 */
10056 { "shlxS", { Gdq
, Edq
, VexGdq
}, 0 },
10059 /* VEX_LEN_0F38F7_P_3 */
10061 { "shrxS", { Gdq
, Edq
, VexGdq
}, 0 },
10064 /* VEX_LEN_0F3A00_P_2 */
10067 { VEX_W_TABLE (VEX_W_0F3A00_P_2
) },
10070 /* VEX_LEN_0F3A01_P_2 */
10073 { VEX_W_TABLE (VEX_W_0F3A01_P_2
) },
10076 /* VEX_LEN_0F3A06_P_2 */
10079 { VEX_W_TABLE (VEX_W_0F3A06_P_2
) },
10082 /* VEX_LEN_0F3A0A_P_2 */
10084 { VEX_W_TABLE (VEX_W_0F3A0A_P_2
) },
10085 { VEX_W_TABLE (VEX_W_0F3A0A_P_2
) },
10088 /* VEX_LEN_0F3A0B_P_2 */
10090 { VEX_W_TABLE (VEX_W_0F3A0B_P_2
) },
10091 { VEX_W_TABLE (VEX_W_0F3A0B_P_2
) },
10094 /* VEX_LEN_0F3A14_P_2 */
10096 { VEX_W_TABLE (VEX_W_0F3A14_P_2
) },
10099 /* VEX_LEN_0F3A15_P_2 */
10101 { VEX_W_TABLE (VEX_W_0F3A15_P_2
) },
10104 /* VEX_LEN_0F3A16_P_2 */
10106 { "vpextrK", { Edq
, XM
, Ib
}, 0 },
10109 /* VEX_LEN_0F3A17_P_2 */
10111 { "vextractps", { Edqd
, XM
, Ib
}, 0 },
10114 /* VEX_LEN_0F3A18_P_2 */
10117 { VEX_W_TABLE (VEX_W_0F3A18_P_2
) },
10120 /* VEX_LEN_0F3A19_P_2 */
10123 { VEX_W_TABLE (VEX_W_0F3A19_P_2
) },
10126 /* VEX_LEN_0F3A20_P_2 */
10128 { VEX_W_TABLE (VEX_W_0F3A20_P_2
) },
10131 /* VEX_LEN_0F3A21_P_2 */
10133 { VEX_W_TABLE (VEX_W_0F3A21_P_2
) },
10136 /* VEX_LEN_0F3A22_P_2 */
10138 { "vpinsrK", { XM
, Vex128
, Edq
, Ib
}, 0 },
10141 /* VEX_LEN_0F3A30_P_2 */
10143 { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0
) },
10146 /* VEX_LEN_0F3A31_P_2 */
10148 { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0
) },
10151 /* VEX_LEN_0F3A32_P_2 */
10153 { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0
) },
10156 /* VEX_LEN_0F3A33_P_2 */
10158 { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0
) },
10161 /* VEX_LEN_0F3A38_P_2 */
10164 { VEX_W_TABLE (VEX_W_0F3A38_P_2
) },
10167 /* VEX_LEN_0F3A39_P_2 */
10170 { VEX_W_TABLE (VEX_W_0F3A39_P_2
) },
10173 /* VEX_LEN_0F3A41_P_2 */
10175 { VEX_W_TABLE (VEX_W_0F3A41_P_2
) },
10178 /* VEX_LEN_0F3A46_P_2 */
10181 { VEX_W_TABLE (VEX_W_0F3A46_P_2
) },
10184 /* VEX_LEN_0F3A60_P_2 */
10186 { "vpcmpestrm", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, 0 },
10189 /* VEX_LEN_0F3A61_P_2 */
10191 { "vpcmpestri", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, 0 },
10194 /* VEX_LEN_0F3A62_P_2 */
10196 { VEX_W_TABLE (VEX_W_0F3A62_P_2
) },
10199 /* VEX_LEN_0F3A63_P_2 */
10201 { VEX_W_TABLE (VEX_W_0F3A63_P_2
) },
10204 /* VEX_LEN_0F3A6A_P_2 */
10206 { "vfmaddss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
}, 0 },
10209 /* VEX_LEN_0F3A6B_P_2 */
10211 { "vfmaddsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
}, 0 },
10214 /* VEX_LEN_0F3A6E_P_2 */
10216 { "vfmsubss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
}, 0 },
10219 /* VEX_LEN_0F3A6F_P_2 */
10221 { "vfmsubsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
}, 0 },
10224 /* VEX_LEN_0F3A7A_P_2 */
10226 { "vfnmaddss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
}, 0 },
10229 /* VEX_LEN_0F3A7B_P_2 */
10231 { "vfnmaddsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
}, 0 },
10234 /* VEX_LEN_0F3A7E_P_2 */
10236 { "vfnmsubss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
}, 0 },
10239 /* VEX_LEN_0F3A7F_P_2 */
10241 { "vfnmsubsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
}, 0 },
10244 /* VEX_LEN_0F3ADF_P_2 */
10246 { VEX_W_TABLE (VEX_W_0F3ADF_P_2
) },
10249 /* VEX_LEN_0F3AF0_P_3 */
10251 { "rorxS", { Gdq
, Edq
, Ib
}, 0 },
10254 /* VEX_LEN_0FXOP_08_CC */
10256 { "vpcomb", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
10259 /* VEX_LEN_0FXOP_08_CD */
10261 { "vpcomw", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
10264 /* VEX_LEN_0FXOP_08_CE */
10266 { "vpcomd", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
10269 /* VEX_LEN_0FXOP_08_CF */
10271 { "vpcomq", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
10274 /* VEX_LEN_0FXOP_08_EC */
10276 { "vpcomub", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
10279 /* VEX_LEN_0FXOP_08_ED */
10281 { "vpcomuw", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
10284 /* VEX_LEN_0FXOP_08_EE */
10286 { "vpcomud", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
10289 /* VEX_LEN_0FXOP_08_EF */
10291 { "vpcomuq", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
10294 /* VEX_LEN_0FXOP_09_80 */
10296 { "vfrczps", { XM
, EXxmm
}, 0 },
10297 { "vfrczps", { XM
, EXymmq
}, 0 },
10300 /* VEX_LEN_0FXOP_09_81 */
10302 { "vfrczpd", { XM
, EXxmm
}, 0 },
10303 { "vfrczpd", { XM
, EXymmq
}, 0 },
10307 static const struct dis386 vex_w_table
[][2] = {
10309 /* VEX_W_0F10_P_0 */
10310 { "vmovups", { XM
, EXx
}, 0 },
10313 /* VEX_W_0F10_P_1 */
10314 { "vmovss", { XMVexScalar
, VexScalar
, EXdScalar
}, 0 },
10317 /* VEX_W_0F10_P_2 */
10318 { "vmovupd", { XM
, EXx
}, 0 },
10321 /* VEX_W_0F10_P_3 */
10322 { "vmovsd", { XMVexScalar
, VexScalar
, EXqScalar
}, 0 },
10325 /* VEX_W_0F11_P_0 */
10326 { "vmovups", { EXxS
, XM
}, 0 },
10329 /* VEX_W_0F11_P_1 */
10330 { "vmovss", { EXdVexScalarS
, VexScalar
, XMScalar
}, 0 },
10333 /* VEX_W_0F11_P_2 */
10334 { "vmovupd", { EXxS
, XM
}, 0 },
10337 /* VEX_W_0F11_P_3 */
10338 { "vmovsd", { EXqVexScalarS
, VexScalar
, XMScalar
}, 0 },
10341 /* VEX_W_0F12_P_0_M_0 */
10342 { "vmovlps", { XM
, Vex128
, EXq
}, 0 },
10345 /* VEX_W_0F12_P_0_M_1 */
10346 { "vmovhlps", { XM
, Vex128
, EXq
}, 0 },
10349 /* VEX_W_0F12_P_1 */
10350 { "vmovsldup", { XM
, EXx
}, 0 },
10353 /* VEX_W_0F12_P_2 */
10354 { "vmovlpd", { XM
, Vex128
, EXq
}, 0 },
10357 /* VEX_W_0F12_P_3 */
10358 { "vmovddup", { XM
, EXymmq
}, 0 },
10361 /* VEX_W_0F13_M_0 */
10362 { "vmovlpX", { EXq
, XM
}, 0 },
10366 { "vunpcklpX", { XM
, Vex
, EXx
}, 0 },
10370 { "vunpckhpX", { XM
, Vex
, EXx
}, 0 },
10373 /* VEX_W_0F16_P_0_M_0 */
10374 { "vmovhps", { XM
, Vex128
, EXq
}, 0 },
10377 /* VEX_W_0F16_P_0_M_1 */
10378 { "vmovlhps", { XM
, Vex128
, EXq
}, 0 },
10381 /* VEX_W_0F16_P_1 */
10382 { "vmovshdup", { XM
, EXx
}, 0 },
10385 /* VEX_W_0F16_P_2 */
10386 { "vmovhpd", { XM
, Vex128
, EXq
}, 0 },
10389 /* VEX_W_0F17_M_0 */
10390 { "vmovhpX", { EXq
, XM
}, 0 },
10394 { "vmovapX", { XM
, EXx
}, 0 },
10398 { "vmovapX", { EXxS
, XM
}, 0 },
10401 /* VEX_W_0F2B_M_0 */
10402 { "vmovntpX", { Mx
, XM
}, 0 },
10405 /* VEX_W_0F2E_P_0 */
10406 { "vucomiss", { XMScalar
, EXdScalar
}, 0 },
10409 /* VEX_W_0F2E_P_2 */
10410 { "vucomisd", { XMScalar
, EXqScalar
}, 0 },
10413 /* VEX_W_0F2F_P_0 */
10414 { "vcomiss", { XMScalar
, EXdScalar
}, 0 },
10417 /* VEX_W_0F2F_P_2 */
10418 { "vcomisd", { XMScalar
, EXqScalar
}, 0 },
10421 /* VEX_W_0F41_P_0_LEN_1 */
10422 { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1
) },
10423 { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1
) },
10426 /* VEX_W_0F41_P_2_LEN_1 */
10427 { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1
) },
10428 { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1
) }
10431 /* VEX_W_0F42_P_0_LEN_1 */
10432 { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1
) },
10433 { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1
) },
10436 /* VEX_W_0F42_P_2_LEN_1 */
10437 { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1
) },
10438 { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1
) },
10441 /* VEX_W_0F44_P_0_LEN_0 */
10442 { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1
) },
10443 { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1
) },
10446 /* VEX_W_0F44_P_2_LEN_0 */
10447 { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1
) },
10448 { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1
) },
10451 /* VEX_W_0F45_P_0_LEN_1 */
10452 { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1
) },
10453 { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1
) },
10456 /* VEX_W_0F45_P_2_LEN_1 */
10457 { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1
) },
10458 { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1
) },
10461 /* VEX_W_0F46_P_0_LEN_1 */
10462 { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1
) },
10463 { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1
) },
10466 /* VEX_W_0F46_P_2_LEN_1 */
10467 { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1
) },
10468 { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1
) },
10471 /* VEX_W_0F47_P_0_LEN_1 */
10472 { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1
) },
10473 { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1
) },
10476 /* VEX_W_0F47_P_2_LEN_1 */
10477 { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1
) },
10478 { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1
) },
10481 /* VEX_W_0F4A_P_0_LEN_1 */
10482 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1
) },
10483 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1
) },
10486 /* VEX_W_0F4A_P_2_LEN_1 */
10487 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1
) },
10488 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1
) },
10491 /* VEX_W_0F4B_P_0_LEN_1 */
10492 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1
) },
10493 { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1
) },
10496 /* VEX_W_0F4B_P_2_LEN_1 */
10497 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1
) },
10500 /* VEX_W_0F50_M_0 */
10501 { "vmovmskpX", { Gdq
, XS
}, 0 },
10504 /* VEX_W_0F51_P_0 */
10505 { "vsqrtps", { XM
, EXx
}, 0 },
10508 /* VEX_W_0F51_P_1 */
10509 { "vsqrtss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10512 /* VEX_W_0F51_P_2 */
10513 { "vsqrtpd", { XM
, EXx
}, 0 },
10516 /* VEX_W_0F51_P_3 */
10517 { "vsqrtsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10520 /* VEX_W_0F52_P_0 */
10521 { "vrsqrtps", { XM
, EXx
}, 0 },
10524 /* VEX_W_0F52_P_1 */
10525 { "vrsqrtss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10528 /* VEX_W_0F53_P_0 */
10529 { "vrcpps", { XM
, EXx
}, 0 },
10532 /* VEX_W_0F53_P_1 */
10533 { "vrcpss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10536 /* VEX_W_0F58_P_0 */
10537 { "vaddps", { XM
, Vex
, EXx
}, 0 },
10540 /* VEX_W_0F58_P_1 */
10541 { "vaddss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10544 /* VEX_W_0F58_P_2 */
10545 { "vaddpd", { XM
, Vex
, EXx
}, 0 },
10548 /* VEX_W_0F58_P_3 */
10549 { "vaddsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10552 /* VEX_W_0F59_P_0 */
10553 { "vmulps", { XM
, Vex
, EXx
}, 0 },
10556 /* VEX_W_0F59_P_1 */
10557 { "vmulss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10560 /* VEX_W_0F59_P_2 */
10561 { "vmulpd", { XM
, Vex
, EXx
}, 0 },
10564 /* VEX_W_0F59_P_3 */
10565 { "vmulsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10568 /* VEX_W_0F5A_P_0 */
10569 { "vcvtps2pd", { XM
, EXxmmq
}, 0 },
10572 /* VEX_W_0F5A_P_1 */
10573 { "vcvtss2sd", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10576 /* VEX_W_0F5A_P_3 */
10577 { "vcvtsd2ss", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10580 /* VEX_W_0F5B_P_0 */
10581 { "vcvtdq2ps", { XM
, EXx
}, 0 },
10584 /* VEX_W_0F5B_P_1 */
10585 { "vcvttps2dq", { XM
, EXx
}, 0 },
10588 /* VEX_W_0F5B_P_2 */
10589 { "vcvtps2dq", { XM
, EXx
}, 0 },
10592 /* VEX_W_0F5C_P_0 */
10593 { "vsubps", { XM
, Vex
, EXx
}, 0 },
10596 /* VEX_W_0F5C_P_1 */
10597 { "vsubss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10600 /* VEX_W_0F5C_P_2 */
10601 { "vsubpd", { XM
, Vex
, EXx
}, 0 },
10604 /* VEX_W_0F5C_P_3 */
10605 { "vsubsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10608 /* VEX_W_0F5D_P_0 */
10609 { "vminps", { XM
, Vex
, EXx
}, 0 },
10612 /* VEX_W_0F5D_P_1 */
10613 { "vminss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10616 /* VEX_W_0F5D_P_2 */
10617 { "vminpd", { XM
, Vex
, EXx
}, 0 },
10620 /* VEX_W_0F5D_P_3 */
10621 { "vminsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10624 /* VEX_W_0F5E_P_0 */
10625 { "vdivps", { XM
, Vex
, EXx
}, 0 },
10628 /* VEX_W_0F5E_P_1 */
10629 { "vdivss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10632 /* VEX_W_0F5E_P_2 */
10633 { "vdivpd", { XM
, Vex
, EXx
}, 0 },
10636 /* VEX_W_0F5E_P_3 */
10637 { "vdivsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10640 /* VEX_W_0F5F_P_0 */
10641 { "vmaxps", { XM
, Vex
, EXx
}, 0 },
10644 /* VEX_W_0F5F_P_1 */
10645 { "vmaxss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10648 /* VEX_W_0F5F_P_2 */
10649 { "vmaxpd", { XM
, Vex
, EXx
}, 0 },
10652 /* VEX_W_0F5F_P_3 */
10653 { "vmaxsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10656 /* VEX_W_0F60_P_2 */
10657 { "vpunpcklbw", { XM
, Vex
, EXx
}, 0 },
10660 /* VEX_W_0F61_P_2 */
10661 { "vpunpcklwd", { XM
, Vex
, EXx
}, 0 },
10664 /* VEX_W_0F62_P_2 */
10665 { "vpunpckldq", { XM
, Vex
, EXx
}, 0 },
10668 /* VEX_W_0F63_P_2 */
10669 { "vpacksswb", { XM
, Vex
, EXx
}, 0 },
10672 /* VEX_W_0F64_P_2 */
10673 { "vpcmpgtb", { XM
, Vex
, EXx
}, 0 },
10676 /* VEX_W_0F65_P_2 */
10677 { "vpcmpgtw", { XM
, Vex
, EXx
}, 0 },
10680 /* VEX_W_0F66_P_2 */
10681 { "vpcmpgtd", { XM
, Vex
, EXx
}, 0 },
10684 /* VEX_W_0F67_P_2 */
10685 { "vpackuswb", { XM
, Vex
, EXx
}, 0 },
10688 /* VEX_W_0F68_P_2 */
10689 { "vpunpckhbw", { XM
, Vex
, EXx
}, 0 },
10692 /* VEX_W_0F69_P_2 */
10693 { "vpunpckhwd", { XM
, Vex
, EXx
}, 0 },
10696 /* VEX_W_0F6A_P_2 */
10697 { "vpunpckhdq", { XM
, Vex
, EXx
}, 0 },
10700 /* VEX_W_0F6B_P_2 */
10701 { "vpackssdw", { XM
, Vex
, EXx
}, 0 },
10704 /* VEX_W_0F6C_P_2 */
10705 { "vpunpcklqdq", { XM
, Vex
, EXx
}, 0 },
10708 /* VEX_W_0F6D_P_2 */
10709 { "vpunpckhqdq", { XM
, Vex
, EXx
}, 0 },
10712 /* VEX_W_0F6F_P_1 */
10713 { "vmovdqu", { XM
, EXx
}, 0 },
10716 /* VEX_W_0F6F_P_2 */
10717 { "vmovdqa", { XM
, EXx
}, 0 },
10720 /* VEX_W_0F70_P_1 */
10721 { "vpshufhw", { XM
, EXx
, Ib
}, 0 },
10724 /* VEX_W_0F70_P_2 */
10725 { "vpshufd", { XM
, EXx
, Ib
}, 0 },
10728 /* VEX_W_0F70_P_3 */
10729 { "vpshuflw", { XM
, EXx
, Ib
}, 0 },
10732 /* VEX_W_0F71_R_2_P_2 */
10733 { "vpsrlw", { Vex
, XS
, Ib
}, 0 },
10736 /* VEX_W_0F71_R_4_P_2 */
10737 { "vpsraw", { Vex
, XS
, Ib
}, 0 },
10740 /* VEX_W_0F71_R_6_P_2 */
10741 { "vpsllw", { Vex
, XS
, Ib
}, 0 },
10744 /* VEX_W_0F72_R_2_P_2 */
10745 { "vpsrld", { Vex
, XS
, Ib
}, 0 },
10748 /* VEX_W_0F72_R_4_P_2 */
10749 { "vpsrad", { Vex
, XS
, Ib
}, 0 },
10752 /* VEX_W_0F72_R_6_P_2 */
10753 { "vpslld", { Vex
, XS
, Ib
}, 0 },
10756 /* VEX_W_0F73_R_2_P_2 */
10757 { "vpsrlq", { Vex
, XS
, Ib
}, 0 },
10760 /* VEX_W_0F73_R_3_P_2 */
10761 { "vpsrldq", { Vex
, XS
, Ib
}, 0 },
10764 /* VEX_W_0F73_R_6_P_2 */
10765 { "vpsllq", { Vex
, XS
, Ib
}, 0 },
10768 /* VEX_W_0F73_R_7_P_2 */
10769 { "vpslldq", { Vex
, XS
, Ib
}, 0 },
10772 /* VEX_W_0F74_P_2 */
10773 { "vpcmpeqb", { XM
, Vex
, EXx
}, 0 },
10776 /* VEX_W_0F75_P_2 */
10777 { "vpcmpeqw", { XM
, Vex
, EXx
}, 0 },
10780 /* VEX_W_0F76_P_2 */
10781 { "vpcmpeqd", { XM
, Vex
, EXx
}, 0 },
10784 /* VEX_W_0F77_P_0 */
10785 { "", { VZERO
}, 0 },
10788 /* VEX_W_0F7C_P_2 */
10789 { "vhaddpd", { XM
, Vex
, EXx
}, 0 },
10792 /* VEX_W_0F7C_P_3 */
10793 { "vhaddps", { XM
, Vex
, EXx
}, 0 },
10796 /* VEX_W_0F7D_P_2 */
10797 { "vhsubpd", { XM
, Vex
, EXx
}, 0 },
10800 /* VEX_W_0F7D_P_3 */
10801 { "vhsubps", { XM
, Vex
, EXx
}, 0 },
10804 /* VEX_W_0F7E_P_1 */
10805 { "vmovq", { XMScalar
, EXqScalar
}, 0 },
10808 /* VEX_W_0F7F_P_1 */
10809 { "vmovdqu", { EXxS
, XM
}, 0 },
10812 /* VEX_W_0F7F_P_2 */
10813 { "vmovdqa", { EXxS
, XM
}, 0 },
10816 /* VEX_W_0F90_P_0_LEN_0 */
10817 { "kmovw", { MaskG
, MaskE
}, 0 },
10818 { "kmovq", { MaskG
, MaskE
}, 0 },
10821 /* VEX_W_0F90_P_2_LEN_0 */
10822 { "kmovb", { MaskG
, MaskBDE
}, 0 },
10823 { "kmovd", { MaskG
, MaskBDE
}, 0 },
10826 /* VEX_W_0F91_P_0_LEN_0 */
10827 { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0
) },
10828 { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0
) },
10831 /* VEX_W_0F91_P_2_LEN_0 */
10832 { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0
) },
10833 { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0
) },
10836 /* VEX_W_0F92_P_0_LEN_0 */
10837 { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0
) },
10840 /* VEX_W_0F92_P_2_LEN_0 */
10841 { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0
) },
10844 /* VEX_W_0F92_P_3_LEN_0 */
10845 { MOD_TABLE (MOD_VEX_W_0_0F92_P_3_LEN_0
) },
10846 { MOD_TABLE (MOD_VEX_W_1_0F92_P_3_LEN_0
) },
10849 /* VEX_W_0F93_P_0_LEN_0 */
10850 { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0
) },
10853 /* VEX_W_0F93_P_2_LEN_0 */
10854 { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0
) },
10857 /* VEX_W_0F93_P_3_LEN_0 */
10858 { MOD_TABLE (MOD_VEX_W_0_0F93_P_3_LEN_0
) },
10859 { MOD_TABLE (MOD_VEX_W_1_0F93_P_3_LEN_0
) },
10862 /* VEX_W_0F98_P_0_LEN_0 */
10863 { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0
) },
10864 { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0
) },
10867 /* VEX_W_0F98_P_2_LEN_0 */
10868 { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0
) },
10869 { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0
) },
10872 /* VEX_W_0F99_P_0_LEN_0 */
10873 { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0
) },
10874 { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0
) },
10877 /* VEX_W_0F99_P_2_LEN_0 */
10878 { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0
) },
10879 { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0
) },
10882 /* VEX_W_0FAE_R_2_M_0 */
10883 { "vldmxcsr", { Md
}, 0 },
10886 /* VEX_W_0FAE_R_3_M_0 */
10887 { "vstmxcsr", { Md
}, 0 },
10890 /* VEX_W_0FC2_P_0 */
10891 { "vcmpps", { XM
, Vex
, EXx
, VCMP
}, 0 },
10894 /* VEX_W_0FC2_P_1 */
10895 { "vcmpss", { XMScalar
, VexScalar
, EXdScalar
, VCMP
}, 0 },
10898 /* VEX_W_0FC2_P_2 */
10899 { "vcmppd", { XM
, Vex
, EXx
, VCMP
}, 0 },
10902 /* VEX_W_0FC2_P_3 */
10903 { "vcmpsd", { XMScalar
, VexScalar
, EXqScalar
, VCMP
}, 0 },
10906 /* VEX_W_0FC4_P_2 */
10907 { "vpinsrw", { XM
, Vex128
, Edqw
, Ib
}, 0 },
10910 /* VEX_W_0FC5_P_2 */
10911 { "vpextrw", { Gdq
, XS
, Ib
}, 0 },
10914 /* VEX_W_0FD0_P_2 */
10915 { "vaddsubpd", { XM
, Vex
, EXx
}, 0 },
10918 /* VEX_W_0FD0_P_3 */
10919 { "vaddsubps", { XM
, Vex
, EXx
}, 0 },
10922 /* VEX_W_0FD1_P_2 */
10923 { "vpsrlw", { XM
, Vex
, EXxmm
}, 0 },
10926 /* VEX_W_0FD2_P_2 */
10927 { "vpsrld", { XM
, Vex
, EXxmm
}, 0 },
10930 /* VEX_W_0FD3_P_2 */
10931 { "vpsrlq", { XM
, Vex
, EXxmm
}, 0 },
10934 /* VEX_W_0FD4_P_2 */
10935 { "vpaddq", { XM
, Vex
, EXx
}, 0 },
10938 /* VEX_W_0FD5_P_2 */
10939 { "vpmullw", { XM
, Vex
, EXx
}, 0 },
10942 /* VEX_W_0FD6_P_2 */
10943 { "vmovq", { EXqScalarS
, XMScalar
}, 0 },
10946 /* VEX_W_0FD7_P_2_M_1 */
10947 { "vpmovmskb", { Gdq
, XS
}, 0 },
10950 /* VEX_W_0FD8_P_2 */
10951 { "vpsubusb", { XM
, Vex
, EXx
}, 0 },
10954 /* VEX_W_0FD9_P_2 */
10955 { "vpsubusw", { XM
, Vex
, EXx
}, 0 },
10958 /* VEX_W_0FDA_P_2 */
10959 { "vpminub", { XM
, Vex
, EXx
}, 0 },
10962 /* VEX_W_0FDB_P_2 */
10963 { "vpand", { XM
, Vex
, EXx
}, 0 },
10966 /* VEX_W_0FDC_P_2 */
10967 { "vpaddusb", { XM
, Vex
, EXx
}, 0 },
10970 /* VEX_W_0FDD_P_2 */
10971 { "vpaddusw", { XM
, Vex
, EXx
}, 0 },
10974 /* VEX_W_0FDE_P_2 */
10975 { "vpmaxub", { XM
, Vex
, EXx
}, 0 },
10978 /* VEX_W_0FDF_P_2 */
10979 { "vpandn", { XM
, Vex
, EXx
}, 0 },
10982 /* VEX_W_0FE0_P_2 */
10983 { "vpavgb", { XM
, Vex
, EXx
}, 0 },
10986 /* VEX_W_0FE1_P_2 */
10987 { "vpsraw", { XM
, Vex
, EXxmm
}, 0 },
10990 /* VEX_W_0FE2_P_2 */
10991 { "vpsrad", { XM
, Vex
, EXxmm
}, 0 },
10994 /* VEX_W_0FE3_P_2 */
10995 { "vpavgw", { XM
, Vex
, EXx
}, 0 },
10998 /* VEX_W_0FE4_P_2 */
10999 { "vpmulhuw", { XM
, Vex
, EXx
}, 0 },
11002 /* VEX_W_0FE5_P_2 */
11003 { "vpmulhw", { XM
, Vex
, EXx
}, 0 },
11006 /* VEX_W_0FE6_P_1 */
11007 { "vcvtdq2pd", { XM
, EXxmmq
}, 0 },
11010 /* VEX_W_0FE6_P_2 */
11011 { "vcvttpd2dq%XY", { XMM
, EXx
}, 0 },
11014 /* VEX_W_0FE6_P_3 */
11015 { "vcvtpd2dq%XY", { XMM
, EXx
}, 0 },
11018 /* VEX_W_0FE7_P_2_M_0 */
11019 { "vmovntdq", { Mx
, XM
}, 0 },
11022 /* VEX_W_0FE8_P_2 */
11023 { "vpsubsb", { XM
, Vex
, EXx
}, 0 },
11026 /* VEX_W_0FE9_P_2 */
11027 { "vpsubsw", { XM
, Vex
, EXx
}, 0 },
11030 /* VEX_W_0FEA_P_2 */
11031 { "vpminsw", { XM
, Vex
, EXx
}, 0 },
11034 /* VEX_W_0FEB_P_2 */
11035 { "vpor", { XM
, Vex
, EXx
}, 0 },
11038 /* VEX_W_0FEC_P_2 */
11039 { "vpaddsb", { XM
, Vex
, EXx
}, 0 },
11042 /* VEX_W_0FED_P_2 */
11043 { "vpaddsw", { XM
, Vex
, EXx
}, 0 },
11046 /* VEX_W_0FEE_P_2 */
11047 { "vpmaxsw", { XM
, Vex
, EXx
}, 0 },
11050 /* VEX_W_0FEF_P_2 */
11051 { "vpxor", { XM
, Vex
, EXx
}, 0 },
11054 /* VEX_W_0FF0_P_3_M_0 */
11055 { "vlddqu", { XM
, M
}, 0 },
11058 /* VEX_W_0FF1_P_2 */
11059 { "vpsllw", { XM
, Vex
, EXxmm
}, 0 },
11062 /* VEX_W_0FF2_P_2 */
11063 { "vpslld", { XM
, Vex
, EXxmm
}, 0 },
11066 /* VEX_W_0FF3_P_2 */
11067 { "vpsllq", { XM
, Vex
, EXxmm
}, 0 },
11070 /* VEX_W_0FF4_P_2 */
11071 { "vpmuludq", { XM
, Vex
, EXx
}, 0 },
11074 /* VEX_W_0FF5_P_2 */
11075 { "vpmaddwd", { XM
, Vex
, EXx
}, 0 },
11078 /* VEX_W_0FF6_P_2 */
11079 { "vpsadbw", { XM
, Vex
, EXx
}, 0 },
11082 /* VEX_W_0FF7_P_2 */
11083 { "vmaskmovdqu", { XM
, XS
}, 0 },
11086 /* VEX_W_0FF8_P_2 */
11087 { "vpsubb", { XM
, Vex
, EXx
}, 0 },
11090 /* VEX_W_0FF9_P_2 */
11091 { "vpsubw", { XM
, Vex
, EXx
}, 0 },
11094 /* VEX_W_0FFA_P_2 */
11095 { "vpsubd", { XM
, Vex
, EXx
}, 0 },
11098 /* VEX_W_0FFB_P_2 */
11099 { "vpsubq", { XM
, Vex
, EXx
}, 0 },
11102 /* VEX_W_0FFC_P_2 */
11103 { "vpaddb", { XM
, Vex
, EXx
}, 0 },
11106 /* VEX_W_0FFD_P_2 */
11107 { "vpaddw", { XM
, Vex
, EXx
}, 0 },
11110 /* VEX_W_0FFE_P_2 */
11111 { "vpaddd", { XM
, Vex
, EXx
}, 0 },
11114 /* VEX_W_0F3800_P_2 */
11115 { "vpshufb", { XM
, Vex
, EXx
}, 0 },
11118 /* VEX_W_0F3801_P_2 */
11119 { "vphaddw", { XM
, Vex
, EXx
}, 0 },
11122 /* VEX_W_0F3802_P_2 */
11123 { "vphaddd", { XM
, Vex
, EXx
}, 0 },
11126 /* VEX_W_0F3803_P_2 */
11127 { "vphaddsw", { XM
, Vex
, EXx
}, 0 },
11130 /* VEX_W_0F3804_P_2 */
11131 { "vpmaddubsw", { XM
, Vex
, EXx
}, 0 },
11134 /* VEX_W_0F3805_P_2 */
11135 { "vphsubw", { XM
, Vex
, EXx
}, 0 },
11138 /* VEX_W_0F3806_P_2 */
11139 { "vphsubd", { XM
, Vex
, EXx
}, 0 },
11142 /* VEX_W_0F3807_P_2 */
11143 { "vphsubsw", { XM
, Vex
, EXx
}, 0 },
11146 /* VEX_W_0F3808_P_2 */
11147 { "vpsignb", { XM
, Vex
, EXx
}, 0 },
11150 /* VEX_W_0F3809_P_2 */
11151 { "vpsignw", { XM
, Vex
, EXx
}, 0 },
11154 /* VEX_W_0F380A_P_2 */
11155 { "vpsignd", { XM
, Vex
, EXx
}, 0 },
11158 /* VEX_W_0F380B_P_2 */
11159 { "vpmulhrsw", { XM
, Vex
, EXx
}, 0 },
11162 /* VEX_W_0F380C_P_2 */
11163 { "vpermilps", { XM
, Vex
, EXx
}, 0 },
11166 /* VEX_W_0F380D_P_2 */
11167 { "vpermilpd", { XM
, Vex
, EXx
}, 0 },
11170 /* VEX_W_0F380E_P_2 */
11171 { "vtestps", { XM
, EXx
}, 0 },
11174 /* VEX_W_0F380F_P_2 */
11175 { "vtestpd", { XM
, EXx
}, 0 },
11178 /* VEX_W_0F3816_P_2 */
11179 { "vpermps", { XM
, Vex
, EXx
}, 0 },
11182 /* VEX_W_0F3817_P_2 */
11183 { "vptest", { XM
, EXx
}, 0 },
11186 /* VEX_W_0F3818_P_2 */
11187 { "vbroadcastss", { XM
, EXxmm_md
}, 0 },
11190 /* VEX_W_0F3819_P_2 */
11191 { "vbroadcastsd", { XM
, EXxmm_mq
}, 0 },
11194 /* VEX_W_0F381A_P_2_M_0 */
11195 { "vbroadcastf128", { XM
, Mxmm
}, 0 },
11198 /* VEX_W_0F381C_P_2 */
11199 { "vpabsb", { XM
, EXx
}, 0 },
11202 /* VEX_W_0F381D_P_2 */
11203 { "vpabsw", { XM
, EXx
}, 0 },
11206 /* VEX_W_0F381E_P_2 */
11207 { "vpabsd", { XM
, EXx
}, 0 },
11210 /* VEX_W_0F3820_P_2 */
11211 { "vpmovsxbw", { XM
, EXxmmq
}, 0 },
11214 /* VEX_W_0F3821_P_2 */
11215 { "vpmovsxbd", { XM
, EXxmmqd
}, 0 },
11218 /* VEX_W_0F3822_P_2 */
11219 { "vpmovsxbq", { XM
, EXxmmdw
}, 0 },
11222 /* VEX_W_0F3823_P_2 */
11223 { "vpmovsxwd", { XM
, EXxmmq
}, 0 },
11226 /* VEX_W_0F3824_P_2 */
11227 { "vpmovsxwq", { XM
, EXxmmqd
}, 0 },
11230 /* VEX_W_0F3825_P_2 */
11231 { "vpmovsxdq", { XM
, EXxmmq
}, 0 },
11234 /* VEX_W_0F3828_P_2 */
11235 { "vpmuldq", { XM
, Vex
, EXx
}, 0 },
11238 /* VEX_W_0F3829_P_2 */
11239 { "vpcmpeqq", { XM
, Vex
, EXx
}, 0 },
11242 /* VEX_W_0F382A_P_2_M_0 */
11243 { "vmovntdqa", { XM
, Mx
}, 0 },
11246 /* VEX_W_0F382B_P_2 */
11247 { "vpackusdw", { XM
, Vex
, EXx
}, 0 },
11250 /* VEX_W_0F382C_P_2_M_0 */
11251 { "vmaskmovps", { XM
, Vex
, Mx
}, 0 },
11254 /* VEX_W_0F382D_P_2_M_0 */
11255 { "vmaskmovpd", { XM
, Vex
, Mx
}, 0 },
11258 /* VEX_W_0F382E_P_2_M_0 */
11259 { "vmaskmovps", { Mx
, Vex
, XM
}, 0 },
11262 /* VEX_W_0F382F_P_2_M_0 */
11263 { "vmaskmovpd", { Mx
, Vex
, XM
}, 0 },
11266 /* VEX_W_0F3830_P_2 */
11267 { "vpmovzxbw", { XM
, EXxmmq
}, 0 },
11270 /* VEX_W_0F3831_P_2 */
11271 { "vpmovzxbd", { XM
, EXxmmqd
}, 0 },
11274 /* VEX_W_0F3832_P_2 */
11275 { "vpmovzxbq", { XM
, EXxmmdw
}, 0 },
11278 /* VEX_W_0F3833_P_2 */
11279 { "vpmovzxwd", { XM
, EXxmmq
}, 0 },
11282 /* VEX_W_0F3834_P_2 */
11283 { "vpmovzxwq", { XM
, EXxmmqd
}, 0 },
11286 /* VEX_W_0F3835_P_2 */
11287 { "vpmovzxdq", { XM
, EXxmmq
}, 0 },
11290 /* VEX_W_0F3836_P_2 */
11291 { "vpermd", { XM
, Vex
, EXx
}, 0 },
11294 /* VEX_W_0F3837_P_2 */
11295 { "vpcmpgtq", { XM
, Vex
, EXx
}, 0 },
11298 /* VEX_W_0F3838_P_2 */
11299 { "vpminsb", { XM
, Vex
, EXx
}, 0 },
11302 /* VEX_W_0F3839_P_2 */
11303 { "vpminsd", { XM
, Vex
, EXx
}, 0 },
11306 /* VEX_W_0F383A_P_2 */
11307 { "vpminuw", { XM
, Vex
, EXx
}, 0 },
11310 /* VEX_W_0F383B_P_2 */
11311 { "vpminud", { XM
, Vex
, EXx
}, 0 },
11314 /* VEX_W_0F383C_P_2 */
11315 { "vpmaxsb", { XM
, Vex
, EXx
}, 0 },
11318 /* VEX_W_0F383D_P_2 */
11319 { "vpmaxsd", { XM
, Vex
, EXx
}, 0 },
11322 /* VEX_W_0F383E_P_2 */
11323 { "vpmaxuw", { XM
, Vex
, EXx
}, 0 },
11326 /* VEX_W_0F383F_P_2 */
11327 { "vpmaxud", { XM
, Vex
, EXx
}, 0 },
11330 /* VEX_W_0F3840_P_2 */
11331 { "vpmulld", { XM
, Vex
, EXx
}, 0 },
11334 /* VEX_W_0F3841_P_2 */
11335 { "vphminposuw", { XM
, EXx
}, 0 },
11338 /* VEX_W_0F3846_P_2 */
11339 { "vpsravd", { XM
, Vex
, EXx
}, 0 },
11342 /* VEX_W_0F3858_P_2 */
11343 { "vpbroadcastd", { XM
, EXxmm_md
}, 0 },
11346 /* VEX_W_0F3859_P_2 */
11347 { "vpbroadcastq", { XM
, EXxmm_mq
}, 0 },
11350 /* VEX_W_0F385A_P_2_M_0 */
11351 { "vbroadcasti128", { XM
, Mxmm
}, 0 },
11354 /* VEX_W_0F3878_P_2 */
11355 { "vpbroadcastb", { XM
, EXxmm_mb
}, 0 },
11358 /* VEX_W_0F3879_P_2 */
11359 { "vpbroadcastw", { XM
, EXxmm_mw
}, 0 },
11362 /* VEX_W_0F38CF_P_2 */
11363 { "vgf2p8mulb", { XM
, Vex
, EXx
}, 0 },
11366 /* VEX_W_0F38DB_P_2 */
11367 { "vaesimc", { XM
, EXx
}, 0 },
11370 /* VEX_W_0F3A00_P_2 */
11372 { "vpermq", { XM
, EXx
, Ib
}, 0 },
11375 /* VEX_W_0F3A01_P_2 */
11377 { "vpermpd", { XM
, EXx
, Ib
}, 0 },
11380 /* VEX_W_0F3A02_P_2 */
11381 { "vpblendd", { XM
, Vex
, EXx
, Ib
}, 0 },
11384 /* VEX_W_0F3A04_P_2 */
11385 { "vpermilps", { XM
, EXx
, Ib
}, 0 },
11388 /* VEX_W_0F3A05_P_2 */
11389 { "vpermilpd", { XM
, EXx
, Ib
}, 0 },
11392 /* VEX_W_0F3A06_P_2 */
11393 { "vperm2f128", { XM
, Vex256
, EXx
, Ib
}, 0 },
11396 /* VEX_W_0F3A08_P_2 */
11397 { "vroundps", { XM
, EXx
, Ib
}, 0 },
11400 /* VEX_W_0F3A09_P_2 */
11401 { "vroundpd", { XM
, EXx
, Ib
}, 0 },
11404 /* VEX_W_0F3A0A_P_2 */
11405 { "vroundss", { XMScalar
, VexScalar
, EXdScalar
, Ib
}, 0 },
11408 /* VEX_W_0F3A0B_P_2 */
11409 { "vroundsd", { XMScalar
, VexScalar
, EXqScalar
, Ib
}, 0 },
11412 /* VEX_W_0F3A0C_P_2 */
11413 { "vblendps", { XM
, Vex
, EXx
, Ib
}, 0 },
11416 /* VEX_W_0F3A0D_P_2 */
11417 { "vblendpd", { XM
, Vex
, EXx
, Ib
}, 0 },
11420 /* VEX_W_0F3A0E_P_2 */
11421 { "vpblendw", { XM
, Vex
, EXx
, Ib
}, 0 },
11424 /* VEX_W_0F3A0F_P_2 */
11425 { "vpalignr", { XM
, Vex
, EXx
, Ib
}, 0 },
11428 /* VEX_W_0F3A14_P_2 */
11429 { "vpextrb", { Edqb
, XM
, Ib
}, 0 },
11432 /* VEX_W_0F3A15_P_2 */
11433 { "vpextrw", { Edqw
, XM
, Ib
}, 0 },
11436 /* VEX_W_0F3A18_P_2 */
11437 { "vinsertf128", { XM
, Vex256
, EXxmm
, Ib
}, 0 },
11440 /* VEX_W_0F3A19_P_2 */
11441 { "vextractf128", { EXxmm
, XM
, Ib
}, 0 },
11444 /* VEX_W_0F3A20_P_2 */
11445 { "vpinsrb", { XM
, Vex128
, Edqb
, Ib
}, 0 },
11448 /* VEX_W_0F3A21_P_2 */
11449 { "vinsertps", { XM
, Vex128
, EXd
, Ib
}, 0 },
11452 /* VEX_W_0F3A30_P_2_LEN_0 */
11453 { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0
) },
11454 { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0
) },
11457 /* VEX_W_0F3A31_P_2_LEN_0 */
11458 { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0
) },
11459 { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0
) },
11462 /* VEX_W_0F3A32_P_2_LEN_0 */
11463 { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0
) },
11464 { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0
) },
11467 /* VEX_W_0F3A33_P_2_LEN_0 */
11468 { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0
) },
11469 { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0
) },
11472 /* VEX_W_0F3A38_P_2 */
11473 { "vinserti128", { XM
, Vex256
, EXxmm
, Ib
}, 0 },
11476 /* VEX_W_0F3A39_P_2 */
11477 { "vextracti128", { EXxmm
, XM
, Ib
}, 0 },
11480 /* VEX_W_0F3A40_P_2 */
11481 { "vdpps", { XM
, Vex
, EXx
, Ib
}, 0 },
11484 /* VEX_W_0F3A41_P_2 */
11485 { "vdppd", { XM
, Vex128
, EXx
, Ib
}, 0 },
11488 /* VEX_W_0F3A42_P_2 */
11489 { "vmpsadbw", { XM
, Vex
, EXx
, Ib
}, 0 },
11492 /* VEX_W_0F3A46_P_2 */
11493 { "vperm2i128", { XM
, Vex256
, EXx
, Ib
}, 0 },
11496 /* VEX_W_0F3A48_P_2 */
11497 { "vpermil2ps", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
11498 { "vpermil2ps", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
11501 /* VEX_W_0F3A49_P_2 */
11502 { "vpermil2pd", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
11503 { "vpermil2pd", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
11506 /* VEX_W_0F3A4A_P_2 */
11507 { "vblendvps", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
11510 /* VEX_W_0F3A4B_P_2 */
11511 { "vblendvpd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
11514 /* VEX_W_0F3A4C_P_2 */
11515 { "vpblendvb", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
11518 /* VEX_W_0F3A62_P_2 */
11519 { "vpcmpistrm", { XM
, EXx
, Ib
}, 0 },
11522 /* VEX_W_0F3A63_P_2 */
11523 { "vpcmpistri", { XM
, EXx
, Ib
}, 0 },
11526 /* VEX_W_0F3ACE_P_2 */
11528 { "vgf2p8affineqb", { XM
, Vex
, EXx
, Ib
}, 0 },
11531 /* VEX_W_0F3ACF_P_2 */
11533 { "vgf2p8affineinvqb", { XM
, Vex
, EXx
, Ib
}, 0 },
11536 /* VEX_W_0F3ADF_P_2 */
11537 { "vaeskeygenassist", { XM
, EXx
, Ib
}, 0 },
11539 #define NEED_VEX_W_TABLE
11540 #include "i386-dis-evex.h"
11541 #undef NEED_VEX_W_TABLE
11544 static const struct dis386 mod_table
[][2] = {
11547 { "leaS", { Gv
, M
}, 0 },
11552 { RM_TABLE (RM_C6_REG_7
) },
11557 { RM_TABLE (RM_C7_REG_7
) },
11561 { "Jcall^", { indirEp
}, 0 },
11565 { "Jjmp^", { indirEp
}, 0 },
11568 /* MOD_0F01_REG_0 */
11569 { X86_64_TABLE (X86_64_0F01_REG_0
) },
11570 { RM_TABLE (RM_0F01_REG_0
) },
11573 /* MOD_0F01_REG_1 */
11574 { X86_64_TABLE (X86_64_0F01_REG_1
) },
11575 { RM_TABLE (RM_0F01_REG_1
) },
11578 /* MOD_0F01_REG_2 */
11579 { X86_64_TABLE (X86_64_0F01_REG_2
) },
11580 { RM_TABLE (RM_0F01_REG_2
) },
11583 /* MOD_0F01_REG_3 */
11584 { X86_64_TABLE (X86_64_0F01_REG_3
) },
11585 { RM_TABLE (RM_0F01_REG_3
) },
11588 /* MOD_0F01_REG_5 */
11589 { PREFIX_TABLE (PREFIX_MOD_0_0F01_REG_5
) },
11590 { RM_TABLE (RM_0F01_REG_5
) },
11593 /* MOD_0F01_REG_7 */
11594 { "invlpg", { Mb
}, 0 },
11595 { RM_TABLE (RM_0F01_REG_7
) },
11598 /* MOD_0F12_PREFIX_0 */
11599 { "movlps", { XM
, EXq
}, PREFIX_OPCODE
},
11600 { "movhlps", { XM
, EXq
}, PREFIX_OPCODE
},
11604 { "movlpX", { EXq
, XM
}, PREFIX_OPCODE
},
11607 /* MOD_0F16_PREFIX_0 */
11608 { "movhps", { XM
, EXq
}, 0 },
11609 { "movlhps", { XM
, EXq
}, 0 },
11613 { "movhpX", { EXq
, XM
}, PREFIX_OPCODE
},
11616 /* MOD_0F18_REG_0 */
11617 { "prefetchnta", { Mb
}, 0 },
11620 /* MOD_0F18_REG_1 */
11621 { "prefetcht0", { Mb
}, 0 },
11624 /* MOD_0F18_REG_2 */
11625 { "prefetcht1", { Mb
}, 0 },
11628 /* MOD_0F18_REG_3 */
11629 { "prefetcht2", { Mb
}, 0 },
11632 /* MOD_0F18_REG_4 */
11633 { "nop/reserved", { Mb
}, 0 },
11636 /* MOD_0F18_REG_5 */
11637 { "nop/reserved", { Mb
}, 0 },
11640 /* MOD_0F18_REG_6 */
11641 { "nop/reserved", { Mb
}, 0 },
11644 /* MOD_0F18_REG_7 */
11645 { "nop/reserved", { Mb
}, 0 },
11648 /* MOD_0F1A_PREFIX_0 */
11649 { "bndldx", { Gbnd
, Ev_bnd
}, 0 },
11650 { "nopQ", { Ev
}, 0 },
11653 /* MOD_0F1B_PREFIX_0 */
11654 { "bndstx", { Ev_bnd
, Gbnd
}, 0 },
11655 { "nopQ", { Ev
}, 0 },
11658 /* MOD_0F1B_PREFIX_1 */
11659 { "bndmk", { Gbnd
, Ev_bnd
}, 0 },
11660 { "nopQ", { Ev
}, 0 },
11663 /* MOD_0F1C_PREFIX_0 */
11664 { REG_TABLE (REG_0F1C_MOD_0
) },
11665 { "nopQ", { Ev
}, 0 },
11668 /* MOD_0F1E_PREFIX_1 */
11669 { "nopQ", { Ev
}, 0 },
11670 { REG_TABLE (REG_0F1E_MOD_3
) },
11675 { "movL", { Rd
, Td
}, 0 },
11680 { "movL", { Td
, Rd
}, 0 },
11683 /* MOD_0F2B_PREFIX_0 */
11684 {"movntps", { Mx
, XM
}, PREFIX_OPCODE
},
11687 /* MOD_0F2B_PREFIX_1 */
11688 {"movntss", { Md
, XM
}, PREFIX_OPCODE
},
11691 /* MOD_0F2B_PREFIX_2 */
11692 {"movntpd", { Mx
, XM
}, PREFIX_OPCODE
},
11695 /* MOD_0F2B_PREFIX_3 */
11696 {"movntsd", { Mq
, XM
}, PREFIX_OPCODE
},
11701 { "movmskpX", { Gdq
, XS
}, PREFIX_OPCODE
},
11704 /* MOD_0F71_REG_2 */
11706 { "psrlw", { MS
, Ib
}, 0 },
11709 /* MOD_0F71_REG_4 */
11711 { "psraw", { MS
, Ib
}, 0 },
11714 /* MOD_0F71_REG_6 */
11716 { "psllw", { MS
, Ib
}, 0 },
11719 /* MOD_0F72_REG_2 */
11721 { "psrld", { MS
, Ib
}, 0 },
11724 /* MOD_0F72_REG_4 */
11726 { "psrad", { MS
, Ib
}, 0 },
11729 /* MOD_0F72_REG_6 */
11731 { "pslld", { MS
, Ib
}, 0 },
11734 /* MOD_0F73_REG_2 */
11736 { "psrlq", { MS
, Ib
}, 0 },
11739 /* MOD_0F73_REG_3 */
11741 { PREFIX_TABLE (PREFIX_0F73_REG_3
) },
11744 /* MOD_0F73_REG_6 */
11746 { "psllq", { MS
, Ib
}, 0 },
11749 /* MOD_0F73_REG_7 */
11751 { PREFIX_TABLE (PREFIX_0F73_REG_7
) },
11754 /* MOD_0FAE_REG_0 */
11755 { "fxsave", { FXSAVE
}, 0 },
11756 { PREFIX_TABLE (PREFIX_0FAE_REG_0
) },
11759 /* MOD_0FAE_REG_1 */
11760 { "fxrstor", { FXSAVE
}, 0 },
11761 { PREFIX_TABLE (PREFIX_0FAE_REG_1
) },
11764 /* MOD_0FAE_REG_2 */
11765 { "ldmxcsr", { Md
}, 0 },
11766 { PREFIX_TABLE (PREFIX_0FAE_REG_2
) },
11769 /* MOD_0FAE_REG_3 */
11770 { "stmxcsr", { Md
}, 0 },
11771 { PREFIX_TABLE (PREFIX_0FAE_REG_3
) },
11774 /* MOD_0FAE_REG_4 */
11775 { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_4
) },
11776 { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_4
) },
11779 /* MOD_0FAE_REG_5 */
11780 { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_5
) },
11781 { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_5
) },
11784 /* MOD_0FAE_REG_6 */
11785 { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_6
) },
11786 { PREFIX_TABLE (PREFIX_MOD_1_0FAE_REG_6
) },
11789 /* MOD_0FAE_REG_7 */
11790 { PREFIX_TABLE (PREFIX_0FAE_REG_7
) },
11791 { RM_TABLE (RM_0FAE_REG_7
) },
11795 { "lssS", { Gv
, Mp
}, 0 },
11799 { "lfsS", { Gv
, Mp
}, 0 },
11803 { "lgsS", { Gv
, Mp
}, 0 },
11807 { PREFIX_TABLE (PREFIX_MOD_0_0FC3
) },
11810 /* MOD_0FC7_REG_3 */
11811 { "xrstors", { FXSAVE
}, 0 },
11814 /* MOD_0FC7_REG_4 */
11815 { "xsavec", { FXSAVE
}, 0 },
11818 /* MOD_0FC7_REG_5 */
11819 { "xsaves", { FXSAVE
}, 0 },
11822 /* MOD_0FC7_REG_6 */
11823 { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6
) },
11824 { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6
) }
11827 /* MOD_0FC7_REG_7 */
11828 { "vmptrst", { Mq
}, 0 },
11829 { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7
) }
11834 { "pmovmskb", { Gdq
, MS
}, 0 },
11837 /* MOD_0FE7_PREFIX_2 */
11838 { "movntdq", { Mx
, XM
}, 0 },
11841 /* MOD_0FF0_PREFIX_3 */
11842 { "lddqu", { XM
, M
}, 0 },
11845 /* MOD_0F382A_PREFIX_2 */
11846 { "movntdqa", { XM
, Mx
}, 0 },
11849 /* MOD_0F38F5_PREFIX_2 */
11850 { "wrussK", { M
, Gdq
}, PREFIX_OPCODE
},
11853 /* MOD_0F38F6_PREFIX_0 */
11854 { "wrssK", { M
, Gdq
}, PREFIX_OPCODE
},
11857 /* MOD_0F38F8_PREFIX_2 */
11858 { "movdir64b", { Gva
, M
}, PREFIX_OPCODE
},
11861 /* MOD_0F38F9_PREFIX_0 */
11862 { "movdiri", { Em
, Gv
}, PREFIX_OPCODE
},
11866 { "bound{S|}", { Gv
, Ma
}, 0 },
11867 { EVEX_TABLE (EVEX_0F
) },
11871 { "lesS", { Gv
, Mp
}, 0 },
11872 { VEX_C4_TABLE (VEX_0F
) },
11876 { "ldsS", { Gv
, Mp
}, 0 },
11877 { VEX_C5_TABLE (VEX_0F
) },
11880 /* MOD_VEX_0F12_PREFIX_0 */
11881 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0
) },
11882 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1
) },
11886 { VEX_LEN_TABLE (VEX_LEN_0F13_M_0
) },
11889 /* MOD_VEX_0F16_PREFIX_0 */
11890 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0
) },
11891 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1
) },
11895 { VEX_LEN_TABLE (VEX_LEN_0F17_M_0
) },
11899 { VEX_W_TABLE (VEX_W_0F2B_M_0
) },
11902 /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
11904 { "kandw", { MaskG
, MaskVex
, MaskR
}, 0 },
11907 /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
11909 { "kandq", { MaskG
, MaskVex
, MaskR
}, 0 },
11912 /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
11914 { "kandb", { MaskG
, MaskVex
, MaskR
}, 0 },
11917 /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
11919 { "kandd", { MaskG
, MaskVex
, MaskR
}, 0 },
11922 /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
11924 { "kandnw", { MaskG
, MaskVex
, MaskR
}, 0 },
11927 /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
11929 { "kandnq", { MaskG
, MaskVex
, MaskR
}, 0 },
11932 /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
11934 { "kandnb", { MaskG
, MaskVex
, MaskR
}, 0 },
11937 /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
11939 { "kandnd", { MaskG
, MaskVex
, MaskR
}, 0 },
11942 /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
11944 { "knotw", { MaskG
, MaskR
}, 0 },
11947 /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
11949 { "knotq", { MaskG
, MaskR
}, 0 },
11952 /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
11954 { "knotb", { MaskG
, MaskR
}, 0 },
11957 /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
11959 { "knotd", { MaskG
, MaskR
}, 0 },
11962 /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
11964 { "korw", { MaskG
, MaskVex
, MaskR
}, 0 },
11967 /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
11969 { "korq", { MaskG
, MaskVex
, MaskR
}, 0 },
11972 /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
11974 { "korb", { MaskG
, MaskVex
, MaskR
}, 0 },
11977 /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
11979 { "kord", { MaskG
, MaskVex
, MaskR
}, 0 },
11982 /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
11984 { "kxnorw", { MaskG
, MaskVex
, MaskR
}, 0 },
11987 /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
11989 { "kxnorq", { MaskG
, MaskVex
, MaskR
}, 0 },
11992 /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
11994 { "kxnorb", { MaskG
, MaskVex
, MaskR
}, 0 },
11997 /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
11999 { "kxnord", { MaskG
, MaskVex
, MaskR
}, 0 },
12002 /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
12004 { "kxorw", { MaskG
, MaskVex
, MaskR
}, 0 },
12007 /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
12009 { "kxorq", { MaskG
, MaskVex
, MaskR
}, 0 },
12012 /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
12014 { "kxorb", { MaskG
, MaskVex
, MaskR
}, 0 },
12017 /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
12019 { "kxord", { MaskG
, MaskVex
, MaskR
}, 0 },
12022 /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
12024 { "kaddw", { MaskG
, MaskVex
, MaskR
}, 0 },
12027 /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
12029 { "kaddq", { MaskG
, MaskVex
, MaskR
}, 0 },
12032 /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
12034 { "kaddb", { MaskG
, MaskVex
, MaskR
}, 0 },
12037 /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
12039 { "kaddd", { MaskG
, MaskVex
, MaskR
}, 0 },
12042 /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
12044 { "kunpckwd", { MaskG
, MaskVex
, MaskR
}, 0 },
12047 /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
12049 { "kunpckdq", { MaskG
, MaskVex
, MaskR
}, 0 },
12052 /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
12054 { "kunpckbw", { MaskG
, MaskVex
, MaskR
}, 0 },
12059 { VEX_W_TABLE (VEX_W_0F50_M_0
) },
12062 /* MOD_VEX_0F71_REG_2 */
12064 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2
) },
12067 /* MOD_VEX_0F71_REG_4 */
12069 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4
) },
12072 /* MOD_VEX_0F71_REG_6 */
12074 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6
) },
12077 /* MOD_VEX_0F72_REG_2 */
12079 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2
) },
12082 /* MOD_VEX_0F72_REG_4 */
12084 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4
) },
12087 /* MOD_VEX_0F72_REG_6 */
12089 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6
) },
12092 /* MOD_VEX_0F73_REG_2 */
12094 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2
) },
12097 /* MOD_VEX_0F73_REG_3 */
12099 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3
) },
12102 /* MOD_VEX_0F73_REG_6 */
12104 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6
) },
12107 /* MOD_VEX_0F73_REG_7 */
12109 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7
) },
12112 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
12113 { "kmovw", { Ew
, MaskG
}, 0 },
12117 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
12118 { "kmovq", { Eq
, MaskG
}, 0 },
12122 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
12123 { "kmovb", { Eb
, MaskG
}, 0 },
12127 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
12128 { "kmovd", { Ed
, MaskG
}, 0 },
12132 /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
12134 { "kmovw", { MaskG
, Rdq
}, 0 },
12137 /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
12139 { "kmovb", { MaskG
, Rdq
}, 0 },
12142 /* MOD_VEX_W_0_0F92_P_3_LEN_0 */
12144 { "kmovd", { MaskG
, Rdq
}, 0 },
12147 /* MOD_VEX_W_1_0F92_P_3_LEN_0 */
12149 { "kmovq", { MaskG
, Rdq
}, 0 },
12152 /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
12154 { "kmovw", { Gdq
, MaskR
}, 0 },
12157 /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
12159 { "kmovb", { Gdq
, MaskR
}, 0 },
12162 /* MOD_VEX_W_0_0F93_P_3_LEN_0 */
12164 { "kmovd", { Gdq
, MaskR
}, 0 },
12167 /* MOD_VEX_W_1_0F93_P_3_LEN_0 */
12169 { "kmovq", { Gdq
, MaskR
}, 0 },
12172 /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
12174 { "kortestw", { MaskG
, MaskR
}, 0 },
12177 /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
12179 { "kortestq", { MaskG
, MaskR
}, 0 },
12182 /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
12184 { "kortestb", { MaskG
, MaskR
}, 0 },
12187 /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
12189 { "kortestd", { MaskG
, MaskR
}, 0 },
12192 /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
12194 { "ktestw", { MaskG
, MaskR
}, 0 },
12197 /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
12199 { "ktestq", { MaskG
, MaskR
}, 0 },
12202 /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
12204 { "ktestb", { MaskG
, MaskR
}, 0 },
12207 /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
12209 { "ktestd", { MaskG
, MaskR
}, 0 },
12212 /* MOD_VEX_0FAE_REG_2 */
12213 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0
) },
12216 /* MOD_VEX_0FAE_REG_3 */
12217 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0
) },
12220 /* MOD_VEX_0FD7_PREFIX_2 */
12222 { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1
) },
12225 /* MOD_VEX_0FE7_PREFIX_2 */
12226 { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0
) },
12229 /* MOD_VEX_0FF0_PREFIX_3 */
12230 { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0
) },
12233 /* MOD_VEX_0F381A_PREFIX_2 */
12234 { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0
) },
12237 /* MOD_VEX_0F382A_PREFIX_2 */
12238 { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0
) },
12241 /* MOD_VEX_0F382C_PREFIX_2 */
12242 { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0
) },
12245 /* MOD_VEX_0F382D_PREFIX_2 */
12246 { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0
) },
12249 /* MOD_VEX_0F382E_PREFIX_2 */
12250 { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0
) },
12253 /* MOD_VEX_0F382F_PREFIX_2 */
12254 { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0
) },
12257 /* MOD_VEX_0F385A_PREFIX_2 */
12258 { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0
) },
12261 /* MOD_VEX_0F388C_PREFIX_2 */
12262 { "vpmaskmov%LW", { XM
, Vex
, Mx
}, 0 },
12265 /* MOD_VEX_0F388E_PREFIX_2 */
12266 { "vpmaskmov%LW", { Mx
, Vex
, XM
}, 0 },
12269 /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
12271 { "kshiftrb", { MaskG
, MaskR
, Ib
}, 0 },
12274 /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
12276 { "kshiftrw", { MaskG
, MaskR
, Ib
}, 0 },
12279 /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
12281 { "kshiftrd", { MaskG
, MaskR
, Ib
}, 0 },
12284 /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
12286 { "kshiftrq", { MaskG
, MaskR
, Ib
}, 0 },
12289 /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
12291 { "kshiftlb", { MaskG
, MaskR
, Ib
}, 0 },
12294 /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
12296 { "kshiftlw", { MaskG
, MaskR
, Ib
}, 0 },
12299 /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
12301 { "kshiftld", { MaskG
, MaskR
, Ib
}, 0 },
12304 /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
12306 { "kshiftlq", { MaskG
, MaskR
, Ib
}, 0 },
12308 #define NEED_MOD_TABLE
12309 #include "i386-dis-evex.h"
12310 #undef NEED_MOD_TABLE
12313 static const struct dis386 rm_table
[][8] = {
12316 { "xabort", { Skip_MODRM
, Ib
}, 0 },
12320 { "xbeginT", { Skip_MODRM
, Jv
}, 0 },
12323 /* RM_0F01_REG_0 */
12325 { "vmcall", { Skip_MODRM
}, 0 },
12326 { "vmlaunch", { Skip_MODRM
}, 0 },
12327 { "vmresume", { Skip_MODRM
}, 0 },
12328 { "vmxoff", { Skip_MODRM
}, 0 },
12329 { "pconfig", { Skip_MODRM
}, 0 },
12332 /* RM_0F01_REG_1 */
12333 { "monitor", { { OP_Monitor
, 0 } }, 0 },
12334 { "mwait", { { OP_Mwait
, 0 } }, 0 },
12335 { "clac", { Skip_MODRM
}, 0 },
12336 { "stac", { Skip_MODRM
}, 0 },
12340 { "encls", { Skip_MODRM
}, 0 },
12343 /* RM_0F01_REG_2 */
12344 { "xgetbv", { Skip_MODRM
}, 0 },
12345 { "xsetbv", { Skip_MODRM
}, 0 },
12348 { "vmfunc", { Skip_MODRM
}, 0 },
12349 { "xend", { Skip_MODRM
}, 0 },
12350 { "xtest", { Skip_MODRM
}, 0 },
12351 { "enclu", { Skip_MODRM
}, 0 },
12354 /* RM_0F01_REG_3 */
12355 { "vmrun", { Skip_MODRM
}, 0 },
12356 { "vmmcall", { Skip_MODRM
}, 0 },
12357 { "vmload", { Skip_MODRM
}, 0 },
12358 { "vmsave", { Skip_MODRM
}, 0 },
12359 { "stgi", { Skip_MODRM
}, 0 },
12360 { "clgi", { Skip_MODRM
}, 0 },
12361 { "skinit", { Skip_MODRM
}, 0 },
12362 { "invlpga", { Skip_MODRM
}, 0 },
12365 /* RM_0F01_REG_5 */
12366 { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_0
) },
12368 { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_2
) },
12372 { "rdpkru", { Skip_MODRM
}, 0 },
12373 { "wrpkru", { Skip_MODRM
}, 0 },
12376 /* RM_0F01_REG_7 */
12377 { "swapgs", { Skip_MODRM
}, 0 },
12378 { "rdtscp", { Skip_MODRM
}, 0 },
12379 { "monitorx", { { OP_Monitor
, 0 } }, 0 },
12380 { "mwaitx", { { OP_Mwaitx
, 0 } }, 0 },
12381 { "clzero", { Skip_MODRM
}, 0 },
12384 /* RM_0F1E_MOD_3_REG_7 */
12385 { "nopQ", { Ev
}, 0 },
12386 { "nopQ", { Ev
}, 0 },
12387 { "endbr64", { Skip_MODRM
}, PREFIX_OPCODE
},
12388 { "endbr32", { Skip_MODRM
}, PREFIX_OPCODE
},
12389 { "nopQ", { Ev
}, 0 },
12390 { "nopQ", { Ev
}, 0 },
12391 { "nopQ", { Ev
}, 0 },
12392 { "nopQ", { Ev
}, 0 },
12395 /* RM_0FAE_REG_6 */
12396 { "mfence", { Skip_MODRM
}, 0 },
12399 /* RM_0FAE_REG_7 */
12400 { "sfence", { Skip_MODRM
}, 0 },
12405 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
12407 /* We use the high bit to indicate different name for the same
12409 #define REP_PREFIX (0xf3 | 0x100)
12410 #define XACQUIRE_PREFIX (0xf2 | 0x200)
12411 #define XRELEASE_PREFIX (0xf3 | 0x400)
12412 #define BND_PREFIX (0xf2 | 0x400)
12413 #define NOTRACK_PREFIX (0x3e | 0x100)
12418 int newrex
, i
, length
;
12424 last_lock_prefix
= -1;
12425 last_repz_prefix
= -1;
12426 last_repnz_prefix
= -1;
12427 last_data_prefix
= -1;
12428 last_addr_prefix
= -1;
12429 last_rex_prefix
= -1;
12430 last_seg_prefix
= -1;
12432 active_seg_prefix
= 0;
12433 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
12434 all_prefixes
[i
] = 0;
12437 /* The maximum instruction length is 15bytes. */
12438 while (length
< MAX_CODE_LENGTH
- 1)
12440 FETCH_DATA (the_info
, codep
+ 1);
12444 /* REX prefixes family. */
12461 if (address_mode
== mode_64bit
)
12465 last_rex_prefix
= i
;
12468 prefixes
|= PREFIX_REPZ
;
12469 last_repz_prefix
= i
;
12472 prefixes
|= PREFIX_REPNZ
;
12473 last_repnz_prefix
= i
;
12476 prefixes
|= PREFIX_LOCK
;
12477 last_lock_prefix
= i
;
12480 prefixes
|= PREFIX_CS
;
12481 last_seg_prefix
= i
;
12482 active_seg_prefix
= PREFIX_CS
;
12485 prefixes
|= PREFIX_SS
;
12486 last_seg_prefix
= i
;
12487 active_seg_prefix
= PREFIX_SS
;
12490 prefixes
|= PREFIX_DS
;
12491 last_seg_prefix
= i
;
12492 active_seg_prefix
= PREFIX_DS
;
12495 prefixes
|= PREFIX_ES
;
12496 last_seg_prefix
= i
;
12497 active_seg_prefix
= PREFIX_ES
;
12500 prefixes
|= PREFIX_FS
;
12501 last_seg_prefix
= i
;
12502 active_seg_prefix
= PREFIX_FS
;
12505 prefixes
|= PREFIX_GS
;
12506 last_seg_prefix
= i
;
12507 active_seg_prefix
= PREFIX_GS
;
12510 prefixes
|= PREFIX_DATA
;
12511 last_data_prefix
= i
;
12514 prefixes
|= PREFIX_ADDR
;
12515 last_addr_prefix
= i
;
12518 /* fwait is really an instruction. If there are prefixes
12519 before the fwait, they belong to the fwait, *not* to the
12520 following instruction. */
12522 if (prefixes
|| rex
)
12524 prefixes
|= PREFIX_FWAIT
;
12526 /* This ensures that the previous REX prefixes are noticed
12527 as unused prefixes, as in the return case below. */
12531 prefixes
= PREFIX_FWAIT
;
12536 /* Rex is ignored when followed by another prefix. */
12542 if (*codep
!= FWAIT_OPCODE
)
12543 all_prefixes
[i
++] = *codep
;
12551 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
12554 static const char *
12555 prefix_name (int pref
, int sizeflag
)
12557 static const char *rexes
[16] =
12560 "rex.B", /* 0x41 */
12561 "rex.X", /* 0x42 */
12562 "rex.XB", /* 0x43 */
12563 "rex.R", /* 0x44 */
12564 "rex.RB", /* 0x45 */
12565 "rex.RX", /* 0x46 */
12566 "rex.RXB", /* 0x47 */
12567 "rex.W", /* 0x48 */
12568 "rex.WB", /* 0x49 */
12569 "rex.WX", /* 0x4a */
12570 "rex.WXB", /* 0x4b */
12571 "rex.WR", /* 0x4c */
12572 "rex.WRB", /* 0x4d */
12573 "rex.WRX", /* 0x4e */
12574 "rex.WRXB", /* 0x4f */
12579 /* REX prefixes family. */
12596 return rexes
[pref
- 0x40];
12616 return (sizeflag
& DFLAG
) ? "data16" : "data32";
12618 if (address_mode
== mode_64bit
)
12619 return (sizeflag
& AFLAG
) ? "addr32" : "addr64";
12621 return (sizeflag
& AFLAG
) ? "addr16" : "addr32";
12626 case XACQUIRE_PREFIX
:
12628 case XRELEASE_PREFIX
:
12632 case NOTRACK_PREFIX
:
12639 static char op_out
[MAX_OPERANDS
][100];
12640 static int op_ad
, op_index
[MAX_OPERANDS
];
12641 static int two_source_ops
;
12642 static bfd_vma op_address
[MAX_OPERANDS
];
12643 static bfd_vma op_riprel
[MAX_OPERANDS
];
12644 static bfd_vma start_pc
;
12647 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
12648 * (see topic "Redundant prefixes" in the "Differences from 8086"
12649 * section of the "Virtual 8086 Mode" chapter.)
12650 * 'pc' should be the address of this instruction, it will
12651 * be used to print the target address if this is a relative jump or call
12652 * The function returns the length of this instruction in bytes.
12655 static char intel_syntax
;
12656 static char intel_mnemonic
= !SYSV386_COMPAT
;
12657 static char open_char
;
12658 static char close_char
;
12659 static char separator_char
;
12660 static char scale_char
;
12668 static enum x86_64_isa isa64
;
12670 /* Here for backwards compatibility. When gdb stops using
12671 print_insn_i386_att and print_insn_i386_intel these functions can
12672 disappear, and print_insn_i386 be merged into print_insn. */
12674 print_insn_i386_att (bfd_vma pc
, disassemble_info
*info
)
12678 return print_insn (pc
, info
);
12682 print_insn_i386_intel (bfd_vma pc
, disassemble_info
*info
)
12686 return print_insn (pc
, info
);
12690 print_insn_i386 (bfd_vma pc
, disassemble_info
*info
)
12694 return print_insn (pc
, info
);
12698 print_i386_disassembler_options (FILE *stream
)
12700 fprintf (stream
, _("\n\
12701 The following i386/x86-64 specific disassembler options are supported for use\n\
12702 with the -M switch (multiple options should be separated by commas):\n"));
12704 fprintf (stream
, _(" x86-64 Disassemble in 64bit mode\n"));
12705 fprintf (stream
, _(" i386 Disassemble in 32bit mode\n"));
12706 fprintf (stream
, _(" i8086 Disassemble in 16bit mode\n"));
12707 fprintf (stream
, _(" att Display instruction in AT&T syntax\n"));
12708 fprintf (stream
, _(" intel Display instruction in Intel syntax\n"));
12709 fprintf (stream
, _(" att-mnemonic\n"
12710 " Display instruction in AT&T mnemonic\n"));
12711 fprintf (stream
, _(" intel-mnemonic\n"
12712 " Display instruction in Intel mnemonic\n"));
12713 fprintf (stream
, _(" addr64 Assume 64bit address size\n"));
12714 fprintf (stream
, _(" addr32 Assume 32bit address size\n"));
12715 fprintf (stream
, _(" addr16 Assume 16bit address size\n"));
12716 fprintf (stream
, _(" data32 Assume 32bit data size\n"));
12717 fprintf (stream
, _(" data16 Assume 16bit data size\n"));
12718 fprintf (stream
, _(" suffix Always display instruction suffix in AT&T syntax\n"));
12719 fprintf (stream
, _(" amd64 Display instruction in AMD64 ISA\n"));
12720 fprintf (stream
, _(" intel64 Display instruction in Intel64 ISA\n"));
12724 static const struct dis386 bad_opcode
= { "(bad)", { XX
}, 0 };
12726 /* Get a pointer to struct dis386 with a valid name. */
12728 static const struct dis386
*
12729 get_valid_dis386 (const struct dis386
*dp
, disassemble_info
*info
)
12731 int vindex
, vex_table_index
;
12733 if (dp
->name
!= NULL
)
12736 switch (dp
->op
[0].bytemode
)
12738 case USE_REG_TABLE
:
12739 dp
= ®_table
[dp
->op
[1].bytemode
][modrm
.reg
];
12742 case USE_MOD_TABLE
:
12743 vindex
= modrm
.mod
== 0x3 ? 1 : 0;
12744 dp
= &mod_table
[dp
->op
[1].bytemode
][vindex
];
12748 dp
= &rm_table
[dp
->op
[1].bytemode
][modrm
.rm
];
12751 case USE_PREFIX_TABLE
:
12754 /* The prefix in VEX is implicit. */
12755 switch (vex
.prefix
)
12760 case REPE_PREFIX_OPCODE
:
12763 case DATA_PREFIX_OPCODE
:
12766 case REPNE_PREFIX_OPCODE
:
12776 int last_prefix
= -1;
12779 /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
12780 When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
12782 if ((prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0)
12784 if (last_repz_prefix
> last_repnz_prefix
)
12787 prefix
= PREFIX_REPZ
;
12788 last_prefix
= last_repz_prefix
;
12793 prefix
= PREFIX_REPNZ
;
12794 last_prefix
= last_repnz_prefix
;
12797 /* Check if prefix should be ignored. */
12798 if ((((prefix_table
[dp
->op
[1].bytemode
][vindex
].prefix_requirement
12799 & PREFIX_IGNORED
) >> PREFIX_IGNORED_SHIFT
)
12804 if (vindex
== 0 && (prefixes
& PREFIX_DATA
) != 0)
12807 prefix
= PREFIX_DATA
;
12808 last_prefix
= last_data_prefix
;
12813 used_prefixes
|= prefix
;
12814 all_prefixes
[last_prefix
] = 0;
12817 dp
= &prefix_table
[dp
->op
[1].bytemode
][vindex
];
12820 case USE_X86_64_TABLE
:
12821 vindex
= address_mode
== mode_64bit
? 1 : 0;
12822 dp
= &x86_64_table
[dp
->op
[1].bytemode
][vindex
];
12825 case USE_3BYTE_TABLE
:
12826 FETCH_DATA (info
, codep
+ 2);
12828 dp
= &three_byte_table
[dp
->op
[1].bytemode
][vindex
];
12830 modrm
.mod
= (*codep
>> 6) & 3;
12831 modrm
.reg
= (*codep
>> 3) & 7;
12832 modrm
.rm
= *codep
& 7;
12835 case USE_VEX_LEN_TABLE
:
12839 switch (vex
.length
)
12852 dp
= &vex_len_table
[dp
->op
[1].bytemode
][vindex
];
12855 case USE_XOP_8F_TABLE
:
12856 FETCH_DATA (info
, codep
+ 3);
12857 /* All bits in the REX prefix are ignored. */
12859 rex
= ~(*codep
>> 5) & 0x7;
12861 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
12862 switch ((*codep
& 0x1f))
12868 vex_table_index
= XOP_08
;
12871 vex_table_index
= XOP_09
;
12874 vex_table_index
= XOP_0A
;
12878 vex
.w
= *codep
& 0x80;
12879 if (vex
.w
&& address_mode
== mode_64bit
)
12882 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
12883 if (address_mode
!= mode_64bit
)
12885 /* In 16/32-bit mode REX_B is silently ignored. */
12889 vex
.length
= (*codep
& 0x4) ? 256 : 128;
12890 switch ((*codep
& 0x3))
12895 vex
.prefix
= DATA_PREFIX_OPCODE
;
12898 vex
.prefix
= REPE_PREFIX_OPCODE
;
12901 vex
.prefix
= REPNE_PREFIX_OPCODE
;
12908 dp
= &xop_table
[vex_table_index
][vindex
];
12911 FETCH_DATA (info
, codep
+ 1);
12912 modrm
.mod
= (*codep
>> 6) & 3;
12913 modrm
.reg
= (*codep
>> 3) & 7;
12914 modrm
.rm
= *codep
& 7;
12917 case USE_VEX_C4_TABLE
:
12919 FETCH_DATA (info
, codep
+ 3);
12920 /* All bits in the REX prefix are ignored. */
12922 rex
= ~(*codep
>> 5) & 0x7;
12923 switch ((*codep
& 0x1f))
12929 vex_table_index
= VEX_0F
;
12932 vex_table_index
= VEX_0F38
;
12935 vex_table_index
= VEX_0F3A
;
12939 vex
.w
= *codep
& 0x80;
12940 if (address_mode
== mode_64bit
)
12947 /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
12948 is ignored, other REX bits are 0 and the highest bit in
12949 VEX.vvvv is also ignored (but we mustn't clear it here). */
12952 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
12953 vex
.length
= (*codep
& 0x4) ? 256 : 128;
12954 switch ((*codep
& 0x3))
12959 vex
.prefix
= DATA_PREFIX_OPCODE
;
12962 vex
.prefix
= REPE_PREFIX_OPCODE
;
12965 vex
.prefix
= REPNE_PREFIX_OPCODE
;
12972 dp
= &vex_table
[vex_table_index
][vindex
];
12974 /* There is no MODRM byte for VEX0F 77. */
12975 if (vex_table_index
!= VEX_0F
|| vindex
!= 0x77)
12977 FETCH_DATA (info
, codep
+ 1);
12978 modrm
.mod
= (*codep
>> 6) & 3;
12979 modrm
.reg
= (*codep
>> 3) & 7;
12980 modrm
.rm
= *codep
& 7;
12984 case USE_VEX_C5_TABLE
:
12986 FETCH_DATA (info
, codep
+ 2);
12987 /* All bits in the REX prefix are ignored. */
12989 rex
= (*codep
& 0x80) ? 0 : REX_R
;
12991 /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
12993 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
12994 vex
.length
= (*codep
& 0x4) ? 256 : 128;
12995 switch ((*codep
& 0x3))
13000 vex
.prefix
= DATA_PREFIX_OPCODE
;
13003 vex
.prefix
= REPE_PREFIX_OPCODE
;
13006 vex
.prefix
= REPNE_PREFIX_OPCODE
;
13013 dp
= &vex_table
[dp
->op
[1].bytemode
][vindex
];
13015 /* There is no MODRM byte for VEX 77. */
13016 if (vindex
!= 0x77)
13018 FETCH_DATA (info
, codep
+ 1);
13019 modrm
.mod
= (*codep
>> 6) & 3;
13020 modrm
.reg
= (*codep
>> 3) & 7;
13021 modrm
.rm
= *codep
& 7;
13025 case USE_VEX_W_TABLE
:
13029 dp
= &vex_w_table
[dp
->op
[1].bytemode
][vex
.w
? 1 : 0];
13032 case USE_EVEX_TABLE
:
13033 two_source_ops
= 0;
13036 FETCH_DATA (info
, codep
+ 4);
13037 /* All bits in the REX prefix are ignored. */
13039 /* The first byte after 0x62. */
13040 rex
= ~(*codep
>> 5) & 0x7;
13041 vex
.r
= *codep
& 0x10;
13042 switch ((*codep
& 0xf))
13045 return &bad_opcode
;
13047 vex_table_index
= EVEX_0F
;
13050 vex_table_index
= EVEX_0F38
;
13053 vex_table_index
= EVEX_0F3A
;
13057 /* The second byte after 0x62. */
13059 vex
.w
= *codep
& 0x80;
13060 if (vex
.w
&& address_mode
== mode_64bit
)
13063 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
13066 if (!(*codep
& 0x4))
13067 return &bad_opcode
;
13069 switch ((*codep
& 0x3))
13074 vex
.prefix
= DATA_PREFIX_OPCODE
;
13077 vex
.prefix
= REPE_PREFIX_OPCODE
;
13080 vex
.prefix
= REPNE_PREFIX_OPCODE
;
13084 /* The third byte after 0x62. */
13087 /* Remember the static rounding bits. */
13088 vex
.ll
= (*codep
>> 5) & 3;
13089 vex
.b
= (*codep
& 0x10) != 0;
13091 vex
.v
= *codep
& 0x8;
13092 vex
.mask_register_specifier
= *codep
& 0x7;
13093 vex
.zeroing
= *codep
& 0x80;
13095 if (address_mode
!= mode_64bit
)
13097 /* In 16/32-bit mode silently ignore following bits. */
13107 dp
= &evex_table
[vex_table_index
][vindex
];
13109 FETCH_DATA (info
, codep
+ 1);
13110 modrm
.mod
= (*codep
>> 6) & 3;
13111 modrm
.reg
= (*codep
>> 3) & 7;
13112 modrm
.rm
= *codep
& 7;
13114 /* Set vector length. */
13115 if (modrm
.mod
== 3 && vex
.b
)
13131 return &bad_opcode
;
13144 if (dp
->name
!= NULL
)
13147 return get_valid_dis386 (dp
, info
);
13151 get_sib (disassemble_info
*info
, int sizeflag
)
13153 /* If modrm.mod == 3, operand must be register. */
13155 && ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
13159 FETCH_DATA (info
, codep
+ 2);
13160 sib
.index
= (codep
[1] >> 3) & 7;
13161 sib
.scale
= (codep
[1] >> 6) & 3;
13162 sib
.base
= codep
[1] & 7;
13167 print_insn (bfd_vma pc
, disassemble_info
*info
)
13169 const struct dis386
*dp
;
13171 char *op_txt
[MAX_OPERANDS
];
13173 int sizeflag
, orig_sizeflag
;
13175 struct dis_private priv
;
13178 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
13179 if ((info
->mach
& bfd_mach_i386_i386
) != 0)
13180 address_mode
= mode_32bit
;
13181 else if (info
->mach
== bfd_mach_i386_i8086
)
13183 address_mode
= mode_16bit
;
13184 priv
.orig_sizeflag
= 0;
13187 address_mode
= mode_64bit
;
13189 if (intel_syntax
== (char) -1)
13190 intel_syntax
= (info
->mach
& bfd_mach_i386_intel_syntax
) != 0;
13192 for (p
= info
->disassembler_options
; p
!= NULL
; )
13194 if (CONST_STRNEQ (p
, "amd64"))
13196 else if (CONST_STRNEQ (p
, "intel64"))
13198 else if (CONST_STRNEQ (p
, "x86-64"))
13200 address_mode
= mode_64bit
;
13201 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
13203 else if (CONST_STRNEQ (p
, "i386"))
13205 address_mode
= mode_32bit
;
13206 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
13208 else if (CONST_STRNEQ (p
, "i8086"))
13210 address_mode
= mode_16bit
;
13211 priv
.orig_sizeflag
= 0;
13213 else if (CONST_STRNEQ (p
, "intel"))
13216 if (CONST_STRNEQ (p
+ 5, "-mnemonic"))
13217 intel_mnemonic
= 1;
13219 else if (CONST_STRNEQ (p
, "att"))
13222 if (CONST_STRNEQ (p
+ 3, "-mnemonic"))
13223 intel_mnemonic
= 0;
13225 else if (CONST_STRNEQ (p
, "addr"))
13227 if (address_mode
== mode_64bit
)
13229 if (p
[4] == '3' && p
[5] == '2')
13230 priv
.orig_sizeflag
&= ~AFLAG
;
13231 else if (p
[4] == '6' && p
[5] == '4')
13232 priv
.orig_sizeflag
|= AFLAG
;
13236 if (p
[4] == '1' && p
[5] == '6')
13237 priv
.orig_sizeflag
&= ~AFLAG
;
13238 else if (p
[4] == '3' && p
[5] == '2')
13239 priv
.orig_sizeflag
|= AFLAG
;
13242 else if (CONST_STRNEQ (p
, "data"))
13244 if (p
[4] == '1' && p
[5] == '6')
13245 priv
.orig_sizeflag
&= ~DFLAG
;
13246 else if (p
[4] == '3' && p
[5] == '2')
13247 priv
.orig_sizeflag
|= DFLAG
;
13249 else if (CONST_STRNEQ (p
, "suffix"))
13250 priv
.orig_sizeflag
|= SUFFIX_ALWAYS
;
13252 p
= strchr (p
, ',');
13257 if (address_mode
== mode_64bit
&& sizeof (bfd_vma
) < 8)
13259 (*info
->fprintf_func
) (info
->stream
,
13260 _("64-bit address is disabled"));
13266 names64
= intel_names64
;
13267 names32
= intel_names32
;
13268 names16
= intel_names16
;
13269 names8
= intel_names8
;
13270 names8rex
= intel_names8rex
;
13271 names_seg
= intel_names_seg
;
13272 names_mm
= intel_names_mm
;
13273 names_bnd
= intel_names_bnd
;
13274 names_xmm
= intel_names_xmm
;
13275 names_ymm
= intel_names_ymm
;
13276 names_zmm
= intel_names_zmm
;
13277 index64
= intel_index64
;
13278 index32
= intel_index32
;
13279 names_mask
= intel_names_mask
;
13280 index16
= intel_index16
;
13283 separator_char
= '+';
13288 names64
= att_names64
;
13289 names32
= att_names32
;
13290 names16
= att_names16
;
13291 names8
= att_names8
;
13292 names8rex
= att_names8rex
;
13293 names_seg
= att_names_seg
;
13294 names_mm
= att_names_mm
;
13295 names_bnd
= att_names_bnd
;
13296 names_xmm
= att_names_xmm
;
13297 names_ymm
= att_names_ymm
;
13298 names_zmm
= att_names_zmm
;
13299 index64
= att_index64
;
13300 index32
= att_index32
;
13301 names_mask
= att_names_mask
;
13302 index16
= att_index16
;
13305 separator_char
= ',';
13309 /* The output looks better if we put 7 bytes on a line, since that
13310 puts most long word instructions on a single line. Use 8 bytes
13312 if ((info
->mach
& bfd_mach_l1om
) != 0)
13313 info
->bytes_per_line
= 8;
13315 info
->bytes_per_line
= 7;
13317 info
->private_data
= &priv
;
13318 priv
.max_fetched
= priv
.the_buffer
;
13319 priv
.insn_start
= pc
;
13322 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
13330 start_codep
= priv
.the_buffer
;
13331 codep
= priv
.the_buffer
;
13333 if (OPCODES_SIGSETJMP (priv
.bailout
) != 0)
13337 /* Getting here means we tried for data but didn't get it. That
13338 means we have an incomplete instruction of some sort. Just
13339 print the first byte as a prefix or a .byte pseudo-op. */
13340 if (codep
> priv
.the_buffer
)
13342 name
= prefix_name (priv
.the_buffer
[0], priv
.orig_sizeflag
);
13344 (*info
->fprintf_func
) (info
->stream
, "%s", name
);
13347 /* Just print the first byte as a .byte instruction. */
13348 (*info
->fprintf_func
) (info
->stream
, ".byte 0x%x",
13349 (unsigned int) priv
.the_buffer
[0]);
13359 sizeflag
= priv
.orig_sizeflag
;
13361 if (!ckprefix () || rex_used
)
13363 /* Too many prefixes or unused REX prefixes. */
13365 i
< (int) ARRAY_SIZE (all_prefixes
) && all_prefixes
[i
];
13367 (*info
->fprintf_func
) (info
->stream
, "%s%s",
13369 prefix_name (all_prefixes
[i
], sizeflag
));
13373 insn_codep
= codep
;
13375 FETCH_DATA (info
, codep
+ 1);
13376 two_source_ops
= (*codep
== 0x62) || (*codep
== 0xc8);
13378 if (((prefixes
& PREFIX_FWAIT
)
13379 && ((*codep
< 0xd8) || (*codep
> 0xdf))))
13381 /* Handle prefixes before fwait. */
13382 for (i
= 0; i
< fwait_prefix
&& all_prefixes
[i
];
13384 (*info
->fprintf_func
) (info
->stream
, "%s ",
13385 prefix_name (all_prefixes
[i
], sizeflag
));
13386 (*info
->fprintf_func
) (info
->stream
, "fwait");
13390 if (*codep
== 0x0f)
13392 unsigned char threebyte
;
13395 FETCH_DATA (info
, codep
+ 1);
13396 threebyte
= *codep
;
13397 dp
= &dis386_twobyte
[threebyte
];
13398 need_modrm
= twobyte_has_modrm
[*codep
];
13403 dp
= &dis386
[*codep
];
13404 need_modrm
= onebyte_has_modrm
[*codep
];
13408 /* Save sizeflag for printing the extra prefixes later before updating
13409 it for mnemonic and operand processing. The prefix names depend
13410 only on the address mode. */
13411 orig_sizeflag
= sizeflag
;
13412 if (prefixes
& PREFIX_ADDR
)
13414 if ((prefixes
& PREFIX_DATA
))
13420 FETCH_DATA (info
, codep
+ 1);
13421 modrm
.mod
= (*codep
>> 6) & 3;
13422 modrm
.reg
= (*codep
>> 3) & 7;
13423 modrm
.rm
= *codep
& 7;
13429 memset (&vex
, 0, sizeof (vex
));
13431 if (dp
->name
== NULL
&& dp
->op
[0].bytemode
== FLOATCODE
)
13433 get_sib (info
, sizeflag
);
13434 dofloat (sizeflag
);
13438 dp
= get_valid_dis386 (dp
, info
);
13439 if (dp
!= NULL
&& putop (dp
->name
, sizeflag
) == 0)
13441 get_sib (info
, sizeflag
);
13442 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
13445 op_ad
= MAX_OPERANDS
- 1 - i
;
13447 (*dp
->op
[i
].rtn
) (dp
->op
[i
].bytemode
, sizeflag
);
13448 /* For EVEX instruction after the last operand masking
13449 should be printed. */
13450 if (i
== 0 && vex
.evex
)
13452 /* Don't print {%k0}. */
13453 if (vex
.mask_register_specifier
)
13456 oappend (names_mask
[vex
.mask_register_specifier
]);
13466 /* Check if the REX prefix is used. */
13467 if (rex_ignored
== 0 && (rex
^ rex_used
) == 0 && last_rex_prefix
>= 0)
13468 all_prefixes
[last_rex_prefix
] = 0;
13470 /* Check if the SEG prefix is used. */
13471 if ((prefixes
& (PREFIX_CS
| PREFIX_SS
| PREFIX_DS
| PREFIX_ES
13472 | PREFIX_FS
| PREFIX_GS
)) != 0
13473 && (used_prefixes
& active_seg_prefix
) != 0)
13474 all_prefixes
[last_seg_prefix
] = 0;
13476 /* Check if the ADDR prefix is used. */
13477 if ((prefixes
& PREFIX_ADDR
) != 0
13478 && (used_prefixes
& PREFIX_ADDR
) != 0)
13479 all_prefixes
[last_addr_prefix
] = 0;
13481 /* Check if the DATA prefix is used. */
13482 if ((prefixes
& PREFIX_DATA
) != 0
13483 && (used_prefixes
& PREFIX_DATA
) != 0)
13484 all_prefixes
[last_data_prefix
] = 0;
13486 /* Print the extra prefixes. */
13488 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
13489 if (all_prefixes
[i
])
13492 name
= prefix_name (all_prefixes
[i
], orig_sizeflag
);
13495 prefix_length
+= strlen (name
) + 1;
13496 (*info
->fprintf_func
) (info
->stream
, "%s ", name
);
13499 /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
13500 unused, opcode is invalid. Since the PREFIX_DATA prefix may be
13501 used by putop and MMX/SSE operand and may be overriden by the
13502 PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
13504 if (dp
->prefix_requirement
== PREFIX_OPCODE
13505 && dp
!= &bad_opcode
13507 & (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0
13509 & (PREFIX_REPZ
| PREFIX_REPNZ
)) == 0)
13511 & (PREFIX_REPZ
| PREFIX_REPNZ
| PREFIX_DATA
))
13513 && (used_prefixes
& PREFIX_DATA
) == 0))))
13515 (*info
->fprintf_func
) (info
->stream
, "(bad)");
13516 return end_codep
- priv
.the_buffer
;
13519 /* Check maximum code length. */
13520 if ((codep
- start_codep
) > MAX_CODE_LENGTH
)
13522 (*info
->fprintf_func
) (info
->stream
, "(bad)");
13523 return MAX_CODE_LENGTH
;
13526 obufp
= mnemonicendp
;
13527 for (i
= strlen (obuf
) + prefix_length
; i
< 6; i
++)
13530 (*info
->fprintf_func
) (info
->stream
, "%s", obuf
);
13532 /* The enter and bound instructions are printed with operands in the same
13533 order as the intel book; everything else is printed in reverse order. */
13534 if (intel_syntax
|| two_source_ops
)
13538 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
13539 op_txt
[i
] = op_out
[i
];
13541 if (intel_syntax
&& dp
&& dp
->op
[2].rtn
== OP_Rounding
13542 && dp
->op
[3].rtn
== OP_E
&& dp
->op
[4].rtn
== NULL
)
13544 op_txt
[2] = op_out
[3];
13545 op_txt
[3] = op_out
[2];
13548 for (i
= 0; i
< (MAX_OPERANDS
>> 1); ++i
)
13550 op_ad
= op_index
[i
];
13551 op_index
[i
] = op_index
[MAX_OPERANDS
- 1 - i
];
13552 op_index
[MAX_OPERANDS
- 1 - i
] = op_ad
;
13553 riprel
= op_riprel
[i
];
13554 op_riprel
[i
] = op_riprel
[MAX_OPERANDS
- 1 - i
];
13555 op_riprel
[MAX_OPERANDS
- 1 - i
] = riprel
;
13560 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
13561 op_txt
[MAX_OPERANDS
- 1 - i
] = op_out
[i
];
13565 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
13569 (*info
->fprintf_func
) (info
->stream
, ",");
13570 if (op_index
[i
] != -1 && !op_riprel
[i
])
13571 (*info
->print_address_func
) ((bfd_vma
) op_address
[op_index
[i
]], info
);
13573 (*info
->fprintf_func
) (info
->stream
, "%s", op_txt
[i
]);
13577 for (i
= 0; i
< MAX_OPERANDS
; i
++)
13578 if (op_index
[i
] != -1 && op_riprel
[i
])
13580 (*info
->fprintf_func
) (info
->stream
, " # ");
13581 (*info
->print_address_func
) ((bfd_vma
) (start_pc
+ (codep
- start_codep
)
13582 + op_address
[op_index
[i
]]), info
);
13585 return codep
- priv
.the_buffer
;
13588 static const char *float_mem
[] = {
13663 static const unsigned char float_mem_mode
[] = {
13738 #define ST { OP_ST, 0 }
13739 #define STi { OP_STi, 0 }
13741 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
13742 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
13743 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
13744 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
13745 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
13746 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
13747 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
13748 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
13749 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
13751 static const struct dis386 float_reg
[][8] = {
13754 { "fadd", { ST
, STi
}, 0 },
13755 { "fmul", { ST
, STi
}, 0 },
13756 { "fcom", { STi
}, 0 },
13757 { "fcomp", { STi
}, 0 },
13758 { "fsub", { ST
, STi
}, 0 },
13759 { "fsubr", { ST
, STi
}, 0 },
13760 { "fdiv", { ST
, STi
}, 0 },
13761 { "fdivr", { ST
, STi
}, 0 },
13765 { "fld", { STi
}, 0 },
13766 { "fxch", { STi
}, 0 },
13776 { "fcmovb", { ST
, STi
}, 0 },
13777 { "fcmove", { ST
, STi
}, 0 },
13778 { "fcmovbe",{ ST
, STi
}, 0 },
13779 { "fcmovu", { ST
, STi
}, 0 },
13787 { "fcmovnb",{ ST
, STi
}, 0 },
13788 { "fcmovne",{ ST
, STi
}, 0 },
13789 { "fcmovnbe",{ ST
, STi
}, 0 },
13790 { "fcmovnu",{ ST
, STi
}, 0 },
13792 { "fucomi", { ST
, STi
}, 0 },
13793 { "fcomi", { ST
, STi
}, 0 },
13798 { "fadd", { STi
, ST
}, 0 },
13799 { "fmul", { STi
, ST
}, 0 },
13802 { "fsub{!M|r}", { STi
, ST
}, 0 },
13803 { "fsub{M|}", { STi
, ST
}, 0 },
13804 { "fdiv{!M|r}", { STi
, ST
}, 0 },
13805 { "fdiv{M|}", { STi
, ST
}, 0 },
13809 { "ffree", { STi
}, 0 },
13811 { "fst", { STi
}, 0 },
13812 { "fstp", { STi
}, 0 },
13813 { "fucom", { STi
}, 0 },
13814 { "fucomp", { STi
}, 0 },
13820 { "faddp", { STi
, ST
}, 0 },
13821 { "fmulp", { STi
, ST
}, 0 },
13824 { "fsub{!M|r}p", { STi
, ST
}, 0 },
13825 { "fsub{M|}p", { STi
, ST
}, 0 },
13826 { "fdiv{!M|r}p", { STi
, ST
}, 0 },
13827 { "fdiv{M|}p", { STi
, ST
}, 0 },
13831 { "ffreep", { STi
}, 0 },
13836 { "fucomip", { ST
, STi
}, 0 },
13837 { "fcomip", { ST
, STi
}, 0 },
13842 static char *fgrps
[][8] = {
13845 "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13850 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13855 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
13860 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
13865 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
13870 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
13875 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13880 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
13881 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
13886 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13891 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13896 swap_operand (void)
13898 mnemonicendp
[0] = '.';
13899 mnemonicendp
[1] = 's';
13904 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED
,
13905 int sizeflag ATTRIBUTE_UNUSED
)
13907 /* Skip mod/rm byte. */
13913 dofloat (int sizeflag
)
13915 const struct dis386
*dp
;
13916 unsigned char floatop
;
13918 floatop
= codep
[-1];
13920 if (modrm
.mod
!= 3)
13922 int fp_indx
= (floatop
- 0xd8) * 8 + modrm
.reg
;
13924 putop (float_mem
[fp_indx
], sizeflag
);
13927 OP_E (float_mem_mode
[fp_indx
], sizeflag
);
13930 /* Skip mod/rm byte. */
13934 dp
= &float_reg
[floatop
- 0xd8][modrm
.reg
];
13935 if (dp
->name
== NULL
)
13937 putop (fgrps
[dp
->op
[0].bytemode
][modrm
.rm
], sizeflag
);
13939 /* Instruction fnstsw is only one with strange arg. */
13940 if (floatop
== 0xdf && codep
[-1] == 0xe0)
13941 strcpy (op_out
[0], names16
[0]);
13945 putop (dp
->name
, sizeflag
);
13950 (*dp
->op
[0].rtn
) (dp
->op
[0].bytemode
, sizeflag
);
13955 (*dp
->op
[1].rtn
) (dp
->op
[1].bytemode
, sizeflag
);
13959 /* Like oappend (below), but S is a string starting with '%'.
13960 In Intel syntax, the '%' is elided. */
13962 oappend_maybe_intel (const char *s
)
13964 oappend (s
+ intel_syntax
);
13968 OP_ST (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
13970 oappend_maybe_intel ("%st");
13974 OP_STi (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
13976 sprintf (scratchbuf
, "%%st(%d)", modrm
.rm
);
13977 oappend_maybe_intel (scratchbuf
);
13980 /* Capital letters in template are macros. */
13982 putop (const char *in_template
, int sizeflag
)
13987 unsigned int l
= 0, len
= 1;
13990 #define SAVE_LAST(c) \
13991 if (l < len && l < sizeof (last)) \
13996 for (p
= in_template
; *p
; p
++)
14012 while (*++p
!= '|')
14013 if (*p
== '}' || *p
== '\0')
14016 /* Fall through. */
14021 while (*++p
!= '}')
14032 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
14036 if (l
== 0 && len
== 1)
14041 if (sizeflag
& SUFFIX_ALWAYS
)
14054 if (address_mode
== mode_64bit
14055 && !(prefixes
& PREFIX_ADDR
))
14066 if (intel_syntax
&& !alt
)
14068 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
14070 if (sizeflag
& DFLAG
)
14071 *obufp
++ = intel_syntax
? 'd' : 'l';
14073 *obufp
++ = intel_syntax
? 'w' : 's';
14074 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14078 if (intel_syntax
|| !(sizeflag
& SUFFIX_ALWAYS
))
14081 if (modrm
.mod
== 3)
14087 if (sizeflag
& DFLAG
)
14088 *obufp
++ = intel_syntax
? 'd' : 'l';
14091 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14097 case 'E': /* For jcxz/jecxz */
14098 if (address_mode
== mode_64bit
)
14100 if (sizeflag
& AFLAG
)
14106 if (sizeflag
& AFLAG
)
14108 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
14113 if ((prefixes
& PREFIX_ADDR
) || (sizeflag
& SUFFIX_ALWAYS
))
14115 if (sizeflag
& AFLAG
)
14116 *obufp
++ = address_mode
== mode_64bit
? 'q' : 'l';
14118 *obufp
++ = address_mode
== mode_64bit
? 'l' : 'w';
14119 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
14123 if (intel_syntax
|| (obufp
[-1] != 's' && !(sizeflag
& SUFFIX_ALWAYS
)))
14125 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
14129 if (!(rex
& REX_W
))
14130 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14135 if ((prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_CS
14136 || (prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_DS
)
14138 used_prefixes
|= prefixes
& (PREFIX_CS
| PREFIX_DS
);
14141 if (prefixes
& PREFIX_DS
)
14160 if (l
!= 0 || len
!= 1)
14162 if (l
!= 1 || len
!= 2 || last
[0] != 'X')
14167 if (!need_vex
|| !vex
.evex
)
14170 || ((modrm
.mod
== 3 || vex
.b
) && !(sizeflag
& SUFFIX_ALWAYS
)))
14172 switch (vex
.length
)
14190 if (address_mode
== mode_64bit
&& (sizeflag
& SUFFIX_ALWAYS
))
14195 /* Fall through. */
14198 if (l
!= 0 || len
!= 1)
14206 if (sizeflag
& SUFFIX_ALWAYS
)
14210 if (intel_mnemonic
!= cond
)
14214 if ((prefixes
& PREFIX_FWAIT
) == 0)
14217 used_prefixes
|= PREFIX_FWAIT
;
14223 else if (intel_syntax
&& (sizeflag
& DFLAG
))
14227 if (!(rex
& REX_W
))
14228 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14232 && address_mode
== mode_64bit
14233 && isa64
== intel64
)
14238 /* Fall through. */
14241 && address_mode
== mode_64bit
14242 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14247 /* Fall through. */
14250 if (l
== 0 && len
== 1)
14255 if ((rex
& REX_W
) == 0
14256 && (prefixes
& PREFIX_DATA
))
14258 if ((sizeflag
& DFLAG
) == 0)
14260 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14264 if ((prefixes
& PREFIX_DATA
)
14266 || (sizeflag
& SUFFIX_ALWAYS
))
14273 if (sizeflag
& DFLAG
)
14277 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14283 if (l
!= 1 || len
!= 2 || last
[0] != 'L')
14289 if ((prefixes
& PREFIX_DATA
)
14291 || (sizeflag
& SUFFIX_ALWAYS
))
14298 if (sizeflag
& DFLAG
)
14299 *obufp
++ = intel_syntax
? 'd' : 'l';
14302 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14310 if (address_mode
== mode_64bit
14311 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14313 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
14317 /* Fall through. */
14320 if (l
== 0 && len
== 1)
14323 if (intel_syntax
&& !alt
)
14326 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
14332 if (sizeflag
& DFLAG
)
14333 *obufp
++ = intel_syntax
? 'd' : 'l';
14336 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14342 if (l
!= 1 || len
!= 2 || last
[0] != 'L')
14348 || (modrm
.mod
== 3 && !(sizeflag
& SUFFIX_ALWAYS
)))
14363 else if (sizeflag
& DFLAG
)
14372 if (intel_syntax
&& !p
[1]
14373 && ((rex
& REX_W
) || (sizeflag
& DFLAG
)))
14375 if (!(rex
& REX_W
))
14376 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14379 if (l
== 0 && len
== 1)
14383 if (address_mode
== mode_64bit
14384 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14386 if (sizeflag
& SUFFIX_ALWAYS
)
14408 /* Fall through. */
14411 if (l
== 0 && len
== 1)
14416 if (sizeflag
& SUFFIX_ALWAYS
)
14422 if (sizeflag
& DFLAG
)
14426 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14440 if (address_mode
== mode_64bit
14441 && !(prefixes
& PREFIX_ADDR
))
14452 if (l
!= 0 || len
!= 1)
14457 if (need_vex
&& vex
.prefix
)
14459 if (vex
.prefix
== DATA_PREFIX_OPCODE
)
14466 if (prefixes
& PREFIX_DATA
)
14470 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14474 if (l
== 0 && len
== 1)
14478 if (l
!= 1 || len
!= 2 || last
[0] != 'X')
14486 || ((modrm
.mod
== 3 || vex
.b
) && !(sizeflag
& SUFFIX_ALWAYS
)))
14488 switch (vex
.length
)
14504 if (l
== 0 && len
== 1)
14506 /* operand size flag for cwtl, cbtw */
14515 else if (sizeflag
& DFLAG
)
14519 if (!(rex
& REX_W
))
14520 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14527 && last
[0] != 'L'))
14534 if (last
[0] == 'X')
14535 *obufp
++ = vex
.w
? 'd': 's';
14537 *obufp
++ = vex
.w
? 'q': 'd';
14543 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
14545 if (sizeflag
& DFLAG
)
14549 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14555 if (address_mode
== mode_64bit
14556 && (isa64
== intel64
14557 || ((sizeflag
& DFLAG
) || (rex
& REX_W
))))
14559 else if ((prefixes
& PREFIX_DATA
))
14561 if (!(sizeflag
& DFLAG
))
14563 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14570 mnemonicendp
= obufp
;
14575 oappend (const char *s
)
14577 obufp
= stpcpy (obufp
, s
);
14583 /* Only print the active segment register. */
14584 if (!active_seg_prefix
)
14587 used_prefixes
|= active_seg_prefix
;
14588 switch (active_seg_prefix
)
14591 oappend_maybe_intel ("%cs:");
14594 oappend_maybe_intel ("%ds:");
14597 oappend_maybe_intel ("%ss:");
14600 oappend_maybe_intel ("%es:");
14603 oappend_maybe_intel ("%fs:");
14606 oappend_maybe_intel ("%gs:");
14614 OP_indirE (int bytemode
, int sizeflag
)
14618 OP_E (bytemode
, sizeflag
);
14622 print_operand_value (char *buf
, int hex
, bfd_vma disp
)
14624 if (address_mode
== mode_64bit
)
14632 sprintf_vma (tmp
, disp
);
14633 for (i
= 0; tmp
[i
] == '0' && tmp
[i
+ 1]; i
++);
14634 strcpy (buf
+ 2, tmp
+ i
);
14638 bfd_signed_vma v
= disp
;
14645 /* Check for possible overflow on 0x8000000000000000. */
14648 strcpy (buf
, "9223372036854775808");
14662 tmp
[28 - i
] = (v
% 10) + '0';
14666 strcpy (buf
, tmp
+ 29 - i
);
14672 sprintf (buf
, "0x%x", (unsigned int) disp
);
14674 sprintf (buf
, "%d", (int) disp
);
14678 /* Put DISP in BUF as signed hex number. */
14681 print_displacement (char *buf
, bfd_vma disp
)
14683 bfd_signed_vma val
= disp
;
14692 /* Check for possible overflow. */
14695 switch (address_mode
)
14698 strcpy (buf
+ j
, "0x8000000000000000");
14701 strcpy (buf
+ j
, "0x80000000");
14704 strcpy (buf
+ j
, "0x8000");
14714 sprintf_vma (tmp
, (bfd_vma
) val
);
14715 for (i
= 0; tmp
[i
] == '0'; i
++)
14717 if (tmp
[i
] == '\0')
14719 strcpy (buf
+ j
, tmp
+ i
);
14723 intel_operand_size (int bytemode
, int sizeflag
)
14727 && (bytemode
== x_mode
14728 || bytemode
== evex_half_bcst_xmmq_mode
))
14731 oappend ("QWORD PTR ");
14733 oappend ("DWORD PTR ");
14742 oappend ("BYTE PTR ");
14747 oappend ("WORD PTR ");
14750 if (address_mode
== mode_64bit
&& isa64
== intel64
)
14752 oappend ("QWORD PTR ");
14755 /* Fall through. */
14757 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14759 oappend ("QWORD PTR ");
14762 /* Fall through. */
14768 oappend ("QWORD PTR ");
14771 if ((sizeflag
& DFLAG
) || bytemode
== dq_mode
)
14772 oappend ("DWORD PTR ");
14774 oappend ("WORD PTR ");
14775 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14779 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
14781 oappend ("WORD PTR ");
14782 if (!(rex
& REX_W
))
14783 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14786 if (sizeflag
& DFLAG
)
14787 oappend ("QWORD PTR ");
14789 oappend ("DWORD PTR ");
14790 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14793 case d_scalar_mode
:
14794 case d_scalar_swap_mode
:
14797 oappend ("DWORD PTR ");
14800 case q_scalar_mode
:
14801 case q_scalar_swap_mode
:
14803 oappend ("QWORD PTR ");
14806 if (address_mode
== mode_64bit
)
14807 oappend ("QWORD PTR ");
14809 oappend ("DWORD PTR ");
14812 if (sizeflag
& DFLAG
)
14813 oappend ("FWORD PTR ");
14815 oappend ("DWORD PTR ");
14816 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14819 oappend ("TBYTE PTR ");
14823 case evex_x_gscat_mode
:
14824 case evex_x_nobcst_mode
:
14825 case b_scalar_mode
:
14826 case w_scalar_mode
:
14829 switch (vex
.length
)
14832 oappend ("XMMWORD PTR ");
14835 oappend ("YMMWORD PTR ");
14838 oappend ("ZMMWORD PTR ");
14845 oappend ("XMMWORD PTR ");
14848 oappend ("XMMWORD PTR ");
14851 oappend ("YMMWORD PTR ");
14854 case evex_half_bcst_xmmq_mode
:
14858 switch (vex
.length
)
14861 oappend ("QWORD PTR ");
14864 oappend ("XMMWORD PTR ");
14867 oappend ("YMMWORD PTR ");
14877 switch (vex
.length
)
14882 oappend ("BYTE PTR ");
14892 switch (vex
.length
)
14897 oappend ("WORD PTR ");
14907 switch (vex
.length
)
14912 oappend ("DWORD PTR ");
14922 switch (vex
.length
)
14927 oappend ("QWORD PTR ");
14937 switch (vex
.length
)
14940 oappend ("WORD PTR ");
14943 oappend ("DWORD PTR ");
14946 oappend ("QWORD PTR ");
14956 switch (vex
.length
)
14959 oappend ("DWORD PTR ");
14962 oappend ("QWORD PTR ");
14965 oappend ("XMMWORD PTR ");
14975 switch (vex
.length
)
14978 oappend ("QWORD PTR ");
14981 oappend ("YMMWORD PTR ");
14984 oappend ("ZMMWORD PTR ");
14994 switch (vex
.length
)
14998 oappend ("XMMWORD PTR ");
15005 oappend ("OWORD PTR ");
15008 case vex_w_dq_mode
:
15009 case vex_scalar_w_dq_mode
:
15014 oappend ("QWORD PTR ");
15016 oappend ("DWORD PTR ");
15018 case vex_vsib_d_w_dq_mode
:
15019 case vex_vsib_q_w_dq_mode
:
15026 oappend ("QWORD PTR ");
15028 oappend ("DWORD PTR ");
15032 switch (vex
.length
)
15035 oappend ("XMMWORD PTR ");
15038 oappend ("YMMWORD PTR ");
15041 oappend ("ZMMWORD PTR ");
15048 case vex_vsib_q_w_d_mode
:
15049 case vex_vsib_d_w_d_mode
:
15050 if (!need_vex
|| !vex
.evex
)
15053 switch (vex
.length
)
15056 oappend ("QWORD PTR ");
15059 oappend ("XMMWORD PTR ");
15062 oappend ("YMMWORD PTR ");
15070 if (!need_vex
|| vex
.length
!= 128)
15073 oappend ("DWORD PTR ");
15075 oappend ("BYTE PTR ");
15081 oappend ("QWORD PTR ");
15083 oappend ("WORD PTR ");
15092 OP_E_register (int bytemode
, int sizeflag
)
15094 int reg
= modrm
.rm
;
15095 const char **names
;
15101 if ((sizeflag
& SUFFIX_ALWAYS
)
15102 && (bytemode
== b_swap_mode
15103 || bytemode
== bnd_swap_mode
15104 || bytemode
== v_swap_mode
))
15130 names
= address_mode
== mode_64bit
? names64
: names32
;
15133 case bnd_swap_mode
:
15142 if (address_mode
== mode_64bit
&& isa64
== intel64
)
15147 /* Fall through. */
15149 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
15155 /* Fall through. */
15167 if ((sizeflag
& DFLAG
)
15168 || (bytemode
!= v_mode
15169 && bytemode
!= v_swap_mode
))
15173 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15177 names
= (address_mode
== mode_64bit
15178 ? names64
: names32
);
15179 if (!(prefixes
& PREFIX_ADDR
))
15180 names
= (address_mode
== mode_16bit
15181 ? names16
: names
);
15184 /* Remove "addr16/addr32". */
15185 all_prefixes
[last_addr_prefix
] = 0;
15186 names
= (address_mode
!= mode_32bit
15187 ? names32
: names16
);
15188 used_prefixes
|= PREFIX_ADDR
;
15198 names
= names_mask
;
15203 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15206 oappend (names
[reg
]);
15210 OP_E_memory (int bytemode
, int sizeflag
)
15213 int add
= (rex
& REX_B
) ? 8 : 0;
15219 /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */
15221 && bytemode
!= x_mode
15222 && bytemode
!= xmmq_mode
15223 && bytemode
!= evex_half_bcst_xmmq_mode
)
15238 case vex_vsib_d_w_dq_mode
:
15239 case vex_vsib_d_w_d_mode
:
15240 case vex_vsib_q_w_dq_mode
:
15241 case vex_vsib_q_w_d_mode
:
15242 case evex_x_gscat_mode
:
15244 shift
= vex
.w
? 3 : 2;
15247 case evex_half_bcst_xmmq_mode
:
15251 shift
= vex
.w
? 3 : 2;
15254 /* Fall through. */
15258 case evex_x_nobcst_mode
:
15260 switch (vex
.length
)
15283 case q_scalar_mode
:
15285 case q_scalar_swap_mode
:
15291 case d_scalar_mode
:
15293 case d_scalar_swap_mode
:
15296 case w_scalar_mode
:
15300 case b_scalar_mode
:
15307 /* Make necessary corrections to shift for modes that need it.
15308 For these modes we currently have shift 4, 5 or 6 depending on
15309 vex.length (it corresponds to xmmword, ymmword or zmmword
15310 operand). We might want to make it 3, 4 or 5 (e.g. for
15311 xmmq_mode). In case of broadcast enabled the corrections
15312 aren't needed, as element size is always 32 or 64 bits. */
15314 && (bytemode
== xmmq_mode
15315 || bytemode
== evex_half_bcst_xmmq_mode
))
15317 else if (bytemode
== xmmqd_mode
)
15319 else if (bytemode
== xmmdw_mode
)
15321 else if (bytemode
== ymmq_mode
&& vex
.length
== 128)
15329 intel_operand_size (bytemode
, sizeflag
);
15332 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
15334 /* 32/64 bit address mode */
15343 int addr32flag
= !((sizeflag
& AFLAG
)
15344 || bytemode
== v_bnd_mode
15345 || bytemode
== bnd_mode
15346 || bytemode
== bnd_swap_mode
);
15347 const char **indexes64
= names64
;
15348 const char **indexes32
= names32
;
15358 vindex
= sib
.index
;
15364 case vex_vsib_d_w_dq_mode
:
15365 case vex_vsib_d_w_d_mode
:
15366 case vex_vsib_q_w_dq_mode
:
15367 case vex_vsib_q_w_d_mode
:
15377 switch (vex
.length
)
15380 indexes64
= indexes32
= names_xmm
;
15384 || bytemode
== vex_vsib_q_w_dq_mode
15385 || bytemode
== vex_vsib_q_w_d_mode
)
15386 indexes64
= indexes32
= names_ymm
;
15388 indexes64
= indexes32
= names_xmm
;
15392 || bytemode
== vex_vsib_q_w_dq_mode
15393 || bytemode
== vex_vsib_q_w_d_mode
)
15394 indexes64
= indexes32
= names_zmm
;
15396 indexes64
= indexes32
= names_ymm
;
15403 haveindex
= vindex
!= 4;
15410 rbase
= base
+ add
;
15418 if (address_mode
== mode_64bit
&& !havesib
)
15424 FETCH_DATA (the_info
, codep
+ 1);
15426 if ((disp
& 0x80) != 0)
15428 if (vex
.evex
&& shift
> 0)
15436 /* In 32bit mode, we need index register to tell [offset] from
15437 [eiz*1 + offset]. */
15438 needindex
= (havesib
15441 && address_mode
== mode_32bit
);
15442 havedisp
= (havebase
15444 || (havesib
&& (haveindex
|| scale
!= 0)));
15447 if (modrm
.mod
!= 0 || base
== 5)
15449 if (havedisp
|| riprel
)
15450 print_displacement (scratchbuf
, disp
);
15452 print_operand_value (scratchbuf
, 1, disp
);
15453 oappend (scratchbuf
);
15457 oappend (!addr32flag
? "(%rip)" : "(%eip)");
15461 if ((havebase
|| haveindex
|| riprel
)
15462 && (bytemode
!= v_bnd_mode
)
15463 && (bytemode
!= bnd_mode
)
15464 && (bytemode
!= bnd_swap_mode
))
15465 used_prefixes
|= PREFIX_ADDR
;
15467 if (havedisp
|| (intel_syntax
&& riprel
))
15469 *obufp
++ = open_char
;
15470 if (intel_syntax
&& riprel
)
15473 oappend (!addr32flag
? "rip" : "eip");
15477 oappend (address_mode
== mode_64bit
&& !addr32flag
15478 ? names64
[rbase
] : names32
[rbase
]);
15481 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
15482 print index to tell base + index from base. */
15486 || (havebase
&& base
!= ESP_REG_NUM
))
15488 if (!intel_syntax
|| havebase
)
15490 *obufp
++ = separator_char
;
15494 oappend (address_mode
== mode_64bit
&& !addr32flag
15495 ? indexes64
[vindex
] : indexes32
[vindex
]);
15497 oappend (address_mode
== mode_64bit
&& !addr32flag
15498 ? index64
: index32
);
15500 *obufp
++ = scale_char
;
15502 sprintf (scratchbuf
, "%d", 1 << scale
);
15503 oappend (scratchbuf
);
15507 && (disp
|| modrm
.mod
!= 0 || base
== 5))
15509 if (!havedisp
|| (bfd_signed_vma
) disp
>= 0)
15514 else if (modrm
.mod
!= 1 && disp
!= -disp
)
15518 disp
= - (bfd_signed_vma
) disp
;
15522 print_displacement (scratchbuf
, disp
);
15524 print_operand_value (scratchbuf
, 1, disp
);
15525 oappend (scratchbuf
);
15528 *obufp
++ = close_char
;
15531 else if (intel_syntax
)
15533 if (modrm
.mod
!= 0 || base
== 5)
15535 if (!active_seg_prefix
)
15537 oappend (names_seg
[ds_reg
- es_reg
]);
15540 print_operand_value (scratchbuf
, 1, disp
);
15541 oappend (scratchbuf
);
15547 /* 16 bit address mode */
15548 used_prefixes
|= prefixes
& PREFIX_ADDR
;
15555 if ((disp
& 0x8000) != 0)
15560 FETCH_DATA (the_info
, codep
+ 1);
15562 if ((disp
& 0x80) != 0)
15564 if (vex
.evex
&& shift
> 0)
15569 if ((disp
& 0x8000) != 0)
15575 if (modrm
.mod
!= 0 || modrm
.rm
== 6)
15577 print_displacement (scratchbuf
, disp
);
15578 oappend (scratchbuf
);
15581 if (modrm
.mod
!= 0 || modrm
.rm
!= 6)
15583 *obufp
++ = open_char
;
15585 oappend (index16
[modrm
.rm
]);
15587 && (disp
|| modrm
.mod
!= 0 || modrm
.rm
== 6))
15589 if ((bfd_signed_vma
) disp
>= 0)
15594 else if (modrm
.mod
!= 1)
15598 disp
= - (bfd_signed_vma
) disp
;
15601 print_displacement (scratchbuf
, disp
);
15602 oappend (scratchbuf
);
15605 *obufp
++ = close_char
;
15608 else if (intel_syntax
)
15610 if (!active_seg_prefix
)
15612 oappend (names_seg
[ds_reg
- es_reg
]);
15615 print_operand_value (scratchbuf
, 1, disp
& 0xffff);
15616 oappend (scratchbuf
);
15619 if (vex
.evex
&& vex
.b
15620 && (bytemode
== x_mode
15621 || bytemode
== xmmq_mode
15622 || bytemode
== evex_half_bcst_xmmq_mode
))
15625 || bytemode
== xmmq_mode
15626 || bytemode
== evex_half_bcst_xmmq_mode
)
15628 switch (vex
.length
)
15631 oappend ("{1to2}");
15634 oappend ("{1to4}");
15637 oappend ("{1to8}");
15645 switch (vex
.length
)
15648 oappend ("{1to4}");
15651 oappend ("{1to8}");
15654 oappend ("{1to16}");
15664 OP_E (int bytemode
, int sizeflag
)
15666 /* Skip mod/rm byte. */
15670 if (modrm
.mod
== 3)
15671 OP_E_register (bytemode
, sizeflag
);
15673 OP_E_memory (bytemode
, sizeflag
);
15677 OP_G (int bytemode
, int sizeflag
)
15680 const char **names
;
15689 oappend (names8rex
[modrm
.reg
+ add
]);
15691 oappend (names8
[modrm
.reg
+ add
]);
15694 oappend (names16
[modrm
.reg
+ add
]);
15699 oappend (names32
[modrm
.reg
+ add
]);
15702 oappend (names64
[modrm
.reg
+ add
]);
15705 if (modrm
.reg
> 0x3)
15710 oappend (names_bnd
[modrm
.reg
]);
15719 oappend (names64
[modrm
.reg
+ add
]);
15722 if ((sizeflag
& DFLAG
) || bytemode
!= v_mode
)
15723 oappend (names32
[modrm
.reg
+ add
]);
15725 oappend (names16
[modrm
.reg
+ add
]);
15726 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15730 names
= (address_mode
== mode_64bit
15731 ? names64
: names32
);
15732 if (!(prefixes
& PREFIX_ADDR
))
15734 if (address_mode
== mode_16bit
)
15739 /* Remove "addr16/addr32". */
15740 all_prefixes
[last_addr_prefix
] = 0;
15741 names
= (address_mode
!= mode_32bit
15742 ? names32
: names16
);
15743 used_prefixes
|= PREFIX_ADDR
;
15745 oappend (names
[modrm
.reg
+ add
]);
15748 if (address_mode
== mode_64bit
)
15749 oappend (names64
[modrm
.reg
+ add
]);
15751 oappend (names32
[modrm
.reg
+ add
]);
15755 if ((modrm
.reg
+ add
) > 0x7)
15760 oappend (names_mask
[modrm
.reg
+ add
]);
15763 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15776 FETCH_DATA (the_info
, codep
+ 8);
15777 a
= *codep
++ & 0xff;
15778 a
|= (*codep
++ & 0xff) << 8;
15779 a
|= (*codep
++ & 0xff) << 16;
15780 a
|= (*codep
++ & 0xffu
) << 24;
15781 b
= *codep
++ & 0xff;
15782 b
|= (*codep
++ & 0xff) << 8;
15783 b
|= (*codep
++ & 0xff) << 16;
15784 b
|= (*codep
++ & 0xffu
) << 24;
15785 x
= a
+ ((bfd_vma
) b
<< 32);
15793 static bfd_signed_vma
15796 bfd_signed_vma x
= 0;
15798 FETCH_DATA (the_info
, codep
+ 4);
15799 x
= *codep
++ & (bfd_signed_vma
) 0xff;
15800 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
15801 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
15802 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
15806 static bfd_signed_vma
15809 bfd_signed_vma x
= 0;
15811 FETCH_DATA (the_info
, codep
+ 4);
15812 x
= *codep
++ & (bfd_signed_vma
) 0xff;
15813 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
15814 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
15815 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
15817 x
= (x
^ ((bfd_signed_vma
) 1 << 31)) - ((bfd_signed_vma
) 1 << 31);
15827 FETCH_DATA (the_info
, codep
+ 2);
15828 x
= *codep
++ & 0xff;
15829 x
|= (*codep
++ & 0xff) << 8;
15834 set_op (bfd_vma op
, int riprel
)
15836 op_index
[op_ad
] = op_ad
;
15837 if (address_mode
== mode_64bit
)
15839 op_address
[op_ad
] = op
;
15840 op_riprel
[op_ad
] = riprel
;
15844 /* Mask to get a 32-bit address. */
15845 op_address
[op_ad
] = op
& 0xffffffff;
15846 op_riprel
[op_ad
] = riprel
& 0xffffffff;
15851 OP_REG (int code
, int sizeflag
)
15858 case es_reg
: case ss_reg
: case cs_reg
:
15859 case ds_reg
: case fs_reg
: case gs_reg
:
15860 oappend (names_seg
[code
- es_reg
]);
15872 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
15873 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
15874 s
= names16
[code
- ax_reg
+ add
];
15876 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
15877 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
15880 s
= names8rex
[code
- al_reg
+ add
];
15882 s
= names8
[code
- al_reg
];
15884 case rAX_reg
: case rCX_reg
: case rDX_reg
: case rBX_reg
:
15885 case rSP_reg
: case rBP_reg
: case rSI_reg
: case rDI_reg
:
15886 if (address_mode
== mode_64bit
15887 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
15889 s
= names64
[code
- rAX_reg
+ add
];
15892 code
+= eAX_reg
- rAX_reg
;
15893 /* Fall through. */
15894 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
15895 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
15898 s
= names64
[code
- eAX_reg
+ add
];
15901 if (sizeflag
& DFLAG
)
15902 s
= names32
[code
- eAX_reg
+ add
];
15904 s
= names16
[code
- eAX_reg
+ add
];
15905 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15909 s
= INTERNAL_DISASSEMBLER_ERROR
;
15916 OP_IMREG (int code
, int sizeflag
)
15928 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
15929 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
15930 s
= names16
[code
- ax_reg
];
15932 case es_reg
: case ss_reg
: case cs_reg
:
15933 case ds_reg
: case fs_reg
: case gs_reg
:
15934 s
= names_seg
[code
- es_reg
];
15936 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
15937 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
15940 s
= names8rex
[code
- al_reg
];
15942 s
= names8
[code
- al_reg
];
15944 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
15945 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
15948 s
= names64
[code
- eAX_reg
];
15951 if (sizeflag
& DFLAG
)
15952 s
= names32
[code
- eAX_reg
];
15954 s
= names16
[code
- eAX_reg
];
15955 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15958 case z_mode_ax_reg
:
15959 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
15963 if (!(rex
& REX_W
))
15964 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15967 s
= INTERNAL_DISASSEMBLER_ERROR
;
15974 OP_I (int bytemode
, int sizeflag
)
15977 bfd_signed_vma mask
= -1;
15982 FETCH_DATA (the_info
, codep
+ 1);
15987 if (address_mode
== mode_64bit
)
15992 /* Fall through. */
15999 if (sizeflag
& DFLAG
)
16009 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16021 oappend (INTERNAL_DISASSEMBLER_ERROR
);
16026 scratchbuf
[0] = '$';
16027 print_operand_value (scratchbuf
+ 1, 1, op
);
16028 oappend_maybe_intel (scratchbuf
);
16029 scratchbuf
[0] = '\0';
16033 OP_I64 (int bytemode
, int sizeflag
)
16036 bfd_signed_vma mask
= -1;
16038 if (address_mode
!= mode_64bit
)
16040 OP_I (bytemode
, sizeflag
);
16047 FETCH_DATA (the_info
, codep
+ 1);
16057 if (sizeflag
& DFLAG
)
16067 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16075 oappend (INTERNAL_DISASSEMBLER_ERROR
);
16080 scratchbuf
[0] = '$';
16081 print_operand_value (scratchbuf
+ 1, 1, op
);
16082 oappend_maybe_intel (scratchbuf
);
16083 scratchbuf
[0] = '\0';
16087 OP_sI (int bytemode
, int sizeflag
)
16095 FETCH_DATA (the_info
, codep
+ 1);
16097 if ((op
& 0x80) != 0)
16099 if (bytemode
== b_T_mode
)
16101 if (address_mode
!= mode_64bit
16102 || !((sizeflag
& DFLAG
) || (rex
& REX_W
)))
16104 /* The operand-size prefix is overridden by a REX prefix. */
16105 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
16113 if (!(rex
& REX_W
))
16115 if (sizeflag
& DFLAG
)
16123 /* The operand-size prefix is overridden by a REX prefix. */
16124 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
16130 oappend (INTERNAL_DISASSEMBLER_ERROR
);
16134 scratchbuf
[0] = '$';
16135 print_operand_value (scratchbuf
+ 1, 1, op
);
16136 oappend_maybe_intel (scratchbuf
);
16140 OP_J (int bytemode
, int sizeflag
)
16144 bfd_vma segment
= 0;
16149 FETCH_DATA (the_info
, codep
+ 1);
16151 if ((disp
& 0x80) != 0)
16155 if (isa64
== amd64
)
16157 if ((sizeflag
& DFLAG
)
16158 || (address_mode
== mode_64bit
16159 && (isa64
!= amd64
|| (rex
& REX_W
))))
16164 if ((disp
& 0x8000) != 0)
16166 /* In 16bit mode, address is wrapped around at 64k within
16167 the same segment. Otherwise, a data16 prefix on a jump
16168 instruction means that the pc is masked to 16 bits after
16169 the displacement is added! */
16171 if ((prefixes
& PREFIX_DATA
) == 0)
16172 segment
= ((start_pc
+ (codep
- start_codep
))
16173 & ~((bfd_vma
) 0xffff));
16175 if (address_mode
!= mode_64bit
16176 || (isa64
== amd64
&& !(rex
& REX_W
)))
16177 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16180 oappend (INTERNAL_DISASSEMBLER_ERROR
);
16183 disp
= ((start_pc
+ (codep
- start_codep
) + disp
) & mask
) | segment
;
16185 print_operand_value (scratchbuf
, 1, disp
);
16186 oappend (scratchbuf
);
16190 OP_SEG (int bytemode
, int sizeflag
)
16192 if (bytemode
== w_mode
)
16193 oappend (names_seg
[modrm
.reg
]);
16195 OP_E (modrm
.mod
== 3 ? bytemode
: w_mode
, sizeflag
);
16199 OP_DIR (int dummy ATTRIBUTE_UNUSED
, int sizeflag
)
16203 if (sizeflag
& DFLAG
)
16213 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16215 sprintf (scratchbuf
, "0x%x:0x%x", seg
, offset
);
16217 sprintf (scratchbuf
, "$0x%x,$0x%x", seg
, offset
);
16218 oappend (scratchbuf
);
16222 OP_OFF (int bytemode
, int sizeflag
)
16226 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
16227 intel_operand_size (bytemode
, sizeflag
);
16230 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
16237 if (!active_seg_prefix
)
16239 oappend (names_seg
[ds_reg
- es_reg
]);
16243 print_operand_value (scratchbuf
, 1, off
);
16244 oappend (scratchbuf
);
16248 OP_OFF64 (int bytemode
, int sizeflag
)
16252 if (address_mode
!= mode_64bit
16253 || (prefixes
& PREFIX_ADDR
))
16255 OP_OFF (bytemode
, sizeflag
);
16259 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
16260 intel_operand_size (bytemode
, sizeflag
);
16267 if (!active_seg_prefix
)
16269 oappend (names_seg
[ds_reg
- es_reg
]);
16273 print_operand_value (scratchbuf
, 1, off
);
16274 oappend (scratchbuf
);
16278 ptr_reg (int code
, int sizeflag
)
16282 *obufp
++ = open_char
;
16283 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
16284 if (address_mode
== mode_64bit
)
16286 if (!(sizeflag
& AFLAG
))
16287 s
= names32
[code
- eAX_reg
];
16289 s
= names64
[code
- eAX_reg
];
16291 else if (sizeflag
& AFLAG
)
16292 s
= names32
[code
- eAX_reg
];
16294 s
= names16
[code
- eAX_reg
];
16296 *obufp
++ = close_char
;
16301 OP_ESreg (int code
, int sizeflag
)
16307 case 0x6d: /* insw/insl */
16308 intel_operand_size (z_mode
, sizeflag
);
16310 case 0xa5: /* movsw/movsl/movsq */
16311 case 0xa7: /* cmpsw/cmpsl/cmpsq */
16312 case 0xab: /* stosw/stosl */
16313 case 0xaf: /* scasw/scasl */
16314 intel_operand_size (v_mode
, sizeflag
);
16317 intel_operand_size (b_mode
, sizeflag
);
16320 oappend_maybe_intel ("%es:");
16321 ptr_reg (code
, sizeflag
);
16325 OP_DSreg (int code
, int sizeflag
)
16331 case 0x6f: /* outsw/outsl */
16332 intel_operand_size (z_mode
, sizeflag
);
16334 case 0xa5: /* movsw/movsl/movsq */
16335 case 0xa7: /* cmpsw/cmpsl/cmpsq */
16336 case 0xad: /* lodsw/lodsl/lodsq */
16337 intel_operand_size (v_mode
, sizeflag
);
16340 intel_operand_size (b_mode
, sizeflag
);
16343 /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
16344 default segment register DS is printed. */
16345 if (!active_seg_prefix
)
16346 active_seg_prefix
= PREFIX_DS
;
16348 ptr_reg (code
, sizeflag
);
16352 OP_C (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16360 else if (address_mode
!= mode_64bit
&& (prefixes
& PREFIX_LOCK
))
16362 all_prefixes
[last_lock_prefix
] = 0;
16363 used_prefixes
|= PREFIX_LOCK
;
16368 sprintf (scratchbuf
, "%%cr%d", modrm
.reg
+ add
);
16369 oappend_maybe_intel (scratchbuf
);
16373 OP_D (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16382 sprintf (scratchbuf
, "db%d", modrm
.reg
+ add
);
16384 sprintf (scratchbuf
, "%%db%d", modrm
.reg
+ add
);
16385 oappend (scratchbuf
);
16389 OP_T (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16391 sprintf (scratchbuf
, "%%tr%d", modrm
.reg
);
16392 oappend_maybe_intel (scratchbuf
);
16396 OP_R (int bytemode
, int sizeflag
)
16398 /* Skip mod/rm byte. */
16401 OP_E_register (bytemode
, sizeflag
);
16405 OP_MMX (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16407 int reg
= modrm
.reg
;
16408 const char **names
;
16410 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16411 if (prefixes
& PREFIX_DATA
)
16420 oappend (names
[reg
]);
16424 OP_XMM (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16426 int reg
= modrm
.reg
;
16427 const char **names
;
16439 && bytemode
!= xmm_mode
16440 && bytemode
!= xmmq_mode
16441 && bytemode
!= evex_half_bcst_xmmq_mode
16442 && bytemode
!= ymm_mode
16443 && bytemode
!= scalar_mode
)
16445 switch (vex
.length
)
16452 || (bytemode
!= vex_vsib_q_w_dq_mode
16453 && bytemode
!= vex_vsib_q_w_d_mode
))
16465 else if (bytemode
== xmmq_mode
16466 || bytemode
== evex_half_bcst_xmmq_mode
)
16468 switch (vex
.length
)
16481 else if (bytemode
== ymm_mode
)
16485 oappend (names
[reg
]);
16489 OP_EM (int bytemode
, int sizeflag
)
16492 const char **names
;
16494 if (modrm
.mod
!= 3)
16497 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
16499 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
16500 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16502 OP_E (bytemode
, sizeflag
);
16506 if ((sizeflag
& SUFFIX_ALWAYS
) && bytemode
== v_swap_mode
)
16509 /* Skip mod/rm byte. */
16512 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16514 if (prefixes
& PREFIX_DATA
)
16523 oappend (names
[reg
]);
16526 /* cvt* are the only instructions in sse2 which have
16527 both SSE and MMX operands and also have 0x66 prefix
16528 in their opcode. 0x66 was originally used to differentiate
16529 between SSE and MMX instruction(operands). So we have to handle the
16530 cvt* separately using OP_EMC and OP_MXC */
16532 OP_EMC (int bytemode
, int sizeflag
)
16534 if (modrm
.mod
!= 3)
16536 if (intel_syntax
&& bytemode
== v_mode
)
16538 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
16539 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16541 OP_E (bytemode
, sizeflag
);
16545 /* Skip mod/rm byte. */
16548 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16549 oappend (names_mm
[modrm
.rm
]);
16553 OP_MXC (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16555 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16556 oappend (names_mm
[modrm
.reg
]);
16560 OP_EX (int bytemode
, int sizeflag
)
16563 const char **names
;
16565 /* Skip mod/rm byte. */
16569 if (modrm
.mod
!= 3)
16571 OP_E_memory (bytemode
, sizeflag
);
16586 if ((sizeflag
& SUFFIX_ALWAYS
)
16587 && (bytemode
== x_swap_mode
16588 || bytemode
== d_swap_mode
16589 || bytemode
== d_scalar_swap_mode
16590 || bytemode
== q_swap_mode
16591 || bytemode
== q_scalar_swap_mode
))
16595 && bytemode
!= xmm_mode
16596 && bytemode
!= xmmdw_mode
16597 && bytemode
!= xmmqd_mode
16598 && bytemode
!= xmm_mb_mode
16599 && bytemode
!= xmm_mw_mode
16600 && bytemode
!= xmm_md_mode
16601 && bytemode
!= xmm_mq_mode
16602 && bytemode
!= xmm_mdq_mode
16603 && bytemode
!= xmmq_mode
16604 && bytemode
!= evex_half_bcst_xmmq_mode
16605 && bytemode
!= ymm_mode
16606 && bytemode
!= d_scalar_mode
16607 && bytemode
!= d_scalar_swap_mode
16608 && bytemode
!= q_scalar_mode
16609 && bytemode
!= q_scalar_swap_mode
16610 && bytemode
!= vex_scalar_w_dq_mode
)
16612 switch (vex
.length
)
16627 else if (bytemode
== xmmq_mode
16628 || bytemode
== evex_half_bcst_xmmq_mode
)
16630 switch (vex
.length
)
16643 else if (bytemode
== ymm_mode
)
16647 oappend (names
[reg
]);
16651 OP_MS (int bytemode
, int sizeflag
)
16653 if (modrm
.mod
== 3)
16654 OP_EM (bytemode
, sizeflag
);
16660 OP_XS (int bytemode
, int sizeflag
)
16662 if (modrm
.mod
== 3)
16663 OP_EX (bytemode
, sizeflag
);
16669 OP_M (int bytemode
, int sizeflag
)
16671 if (modrm
.mod
== 3)
16672 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
16675 OP_E (bytemode
, sizeflag
);
16679 OP_0f07 (int bytemode
, int sizeflag
)
16681 if (modrm
.mod
!= 3 || modrm
.rm
!= 0)
16684 OP_E (bytemode
, sizeflag
);
16687 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
16688 32bit mode and "xchg %rax,%rax" in 64bit mode. */
16691 NOP_Fixup1 (int bytemode
, int sizeflag
)
16693 if ((prefixes
& PREFIX_DATA
) != 0
16696 && address_mode
== mode_64bit
))
16697 OP_REG (bytemode
, sizeflag
);
16699 strcpy (obuf
, "nop");
16703 NOP_Fixup2 (int bytemode
, int sizeflag
)
16705 if ((prefixes
& PREFIX_DATA
) != 0
16708 && address_mode
== mode_64bit
))
16709 OP_IMREG (bytemode
, sizeflag
);
16712 static const char *const Suffix3DNow
[] = {
16713 /* 00 */ NULL
, NULL
, NULL
, NULL
,
16714 /* 04 */ NULL
, NULL
, NULL
, NULL
,
16715 /* 08 */ NULL
, NULL
, NULL
, NULL
,
16716 /* 0C */ "pi2fw", "pi2fd", NULL
, NULL
,
16717 /* 10 */ NULL
, NULL
, NULL
, NULL
,
16718 /* 14 */ NULL
, NULL
, NULL
, NULL
,
16719 /* 18 */ NULL
, NULL
, NULL
, NULL
,
16720 /* 1C */ "pf2iw", "pf2id", NULL
, NULL
,
16721 /* 20 */ NULL
, NULL
, NULL
, NULL
,
16722 /* 24 */ NULL
, NULL
, NULL
, NULL
,
16723 /* 28 */ NULL
, NULL
, NULL
, NULL
,
16724 /* 2C */ NULL
, NULL
, NULL
, NULL
,
16725 /* 30 */ NULL
, NULL
, NULL
, NULL
,
16726 /* 34 */ NULL
, NULL
, NULL
, NULL
,
16727 /* 38 */ NULL
, NULL
, NULL
, NULL
,
16728 /* 3C */ NULL
, NULL
, NULL
, NULL
,
16729 /* 40 */ NULL
, NULL
, NULL
, NULL
,
16730 /* 44 */ NULL
, NULL
, NULL
, NULL
,
16731 /* 48 */ NULL
, NULL
, NULL
, NULL
,
16732 /* 4C */ NULL
, NULL
, NULL
, NULL
,
16733 /* 50 */ NULL
, NULL
, NULL
, NULL
,
16734 /* 54 */ NULL
, NULL
, NULL
, NULL
,
16735 /* 58 */ NULL
, NULL
, NULL
, NULL
,
16736 /* 5C */ NULL
, NULL
, NULL
, NULL
,
16737 /* 60 */ NULL
, NULL
, NULL
, NULL
,
16738 /* 64 */ NULL
, NULL
, NULL
, NULL
,
16739 /* 68 */ NULL
, NULL
, NULL
, NULL
,
16740 /* 6C */ NULL
, NULL
, NULL
, NULL
,
16741 /* 70 */ NULL
, NULL
, NULL
, NULL
,
16742 /* 74 */ NULL
, NULL
, NULL
, NULL
,
16743 /* 78 */ NULL
, NULL
, NULL
, NULL
,
16744 /* 7C */ NULL
, NULL
, NULL
, NULL
,
16745 /* 80 */ NULL
, NULL
, NULL
, NULL
,
16746 /* 84 */ NULL
, NULL
, NULL
, NULL
,
16747 /* 88 */ NULL
, NULL
, "pfnacc", NULL
,
16748 /* 8C */ NULL
, NULL
, "pfpnacc", NULL
,
16749 /* 90 */ "pfcmpge", NULL
, NULL
, NULL
,
16750 /* 94 */ "pfmin", NULL
, "pfrcp", "pfrsqrt",
16751 /* 98 */ NULL
, NULL
, "pfsub", NULL
,
16752 /* 9C */ NULL
, NULL
, "pfadd", NULL
,
16753 /* A0 */ "pfcmpgt", NULL
, NULL
, NULL
,
16754 /* A4 */ "pfmax", NULL
, "pfrcpit1", "pfrsqit1",
16755 /* A8 */ NULL
, NULL
, "pfsubr", NULL
,
16756 /* AC */ NULL
, NULL
, "pfacc", NULL
,
16757 /* B0 */ "pfcmpeq", NULL
, NULL
, NULL
,
16758 /* B4 */ "pfmul", NULL
, "pfrcpit2", "pmulhrw",
16759 /* B8 */ NULL
, NULL
, NULL
, "pswapd",
16760 /* BC */ NULL
, NULL
, NULL
, "pavgusb",
16761 /* C0 */ NULL
, NULL
, NULL
, NULL
,
16762 /* C4 */ NULL
, NULL
, NULL
, NULL
,
16763 /* C8 */ NULL
, NULL
, NULL
, NULL
,
16764 /* CC */ NULL
, NULL
, NULL
, NULL
,
16765 /* D0 */ NULL
, NULL
, NULL
, NULL
,
16766 /* D4 */ NULL
, NULL
, NULL
, NULL
,
16767 /* D8 */ NULL
, NULL
, NULL
, NULL
,
16768 /* DC */ NULL
, NULL
, NULL
, NULL
,
16769 /* E0 */ NULL
, NULL
, NULL
, NULL
,
16770 /* E4 */ NULL
, NULL
, NULL
, NULL
,
16771 /* E8 */ NULL
, NULL
, NULL
, NULL
,
16772 /* EC */ NULL
, NULL
, NULL
, NULL
,
16773 /* F0 */ NULL
, NULL
, NULL
, NULL
,
16774 /* F4 */ NULL
, NULL
, NULL
, NULL
,
16775 /* F8 */ NULL
, NULL
, NULL
, NULL
,
16776 /* FC */ NULL
, NULL
, NULL
, NULL
,
16780 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16782 const char *mnemonic
;
16784 FETCH_DATA (the_info
, codep
+ 1);
16785 /* AMD 3DNow! instructions are specified by an opcode suffix in the
16786 place where an 8-bit immediate would normally go. ie. the last
16787 byte of the instruction. */
16788 obufp
= mnemonicendp
;
16789 mnemonic
= Suffix3DNow
[*codep
++ & 0xff];
16791 oappend (mnemonic
);
16794 /* Since a variable sized modrm/sib chunk is between the start
16795 of the opcode (0x0f0f) and the opcode suffix, we need to do
16796 all the modrm processing first, and don't know until now that
16797 we have a bad opcode. This necessitates some cleaning up. */
16798 op_out
[0][0] = '\0';
16799 op_out
[1][0] = '\0';
16802 mnemonicendp
= obufp
;
16805 static struct op simd_cmp_op
[] =
16807 { STRING_COMMA_LEN ("eq") },
16808 { STRING_COMMA_LEN ("lt") },
16809 { STRING_COMMA_LEN ("le") },
16810 { STRING_COMMA_LEN ("unord") },
16811 { STRING_COMMA_LEN ("neq") },
16812 { STRING_COMMA_LEN ("nlt") },
16813 { STRING_COMMA_LEN ("nle") },
16814 { STRING_COMMA_LEN ("ord") }
16818 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16820 unsigned int cmp_type
;
16822 FETCH_DATA (the_info
, codep
+ 1);
16823 cmp_type
= *codep
++ & 0xff;
16824 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
))
16827 char *p
= mnemonicendp
- 2;
16831 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
16832 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
16836 /* We have a reserved extension byte. Output it directly. */
16837 scratchbuf
[0] = '$';
16838 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
16839 oappend_maybe_intel (scratchbuf
);
16840 scratchbuf
[0] = '\0';
16845 OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED
,
16846 int sizeflag ATTRIBUTE_UNUSED
)
16848 /* mwaitx %eax,%ecx,%ebx */
16851 const char **names
= (address_mode
== mode_64bit
16852 ? names64
: names32
);
16853 strcpy (op_out
[0], names
[0]);
16854 strcpy (op_out
[1], names
[1]);
16855 strcpy (op_out
[2], names
[3]);
16856 two_source_ops
= 1;
16858 /* Skip mod/rm byte. */
16864 OP_Mwait (int bytemode ATTRIBUTE_UNUSED
,
16865 int sizeflag ATTRIBUTE_UNUSED
)
16867 /* mwait %eax,%ecx */
16870 const char **names
= (address_mode
== mode_64bit
16871 ? names64
: names32
);
16872 strcpy (op_out
[0], names
[0]);
16873 strcpy (op_out
[1], names
[1]);
16874 two_source_ops
= 1;
16876 /* Skip mod/rm byte. */
16882 OP_Monitor (int bytemode ATTRIBUTE_UNUSED
,
16883 int sizeflag ATTRIBUTE_UNUSED
)
16885 /* monitor %eax,%ecx,%edx" */
16888 const char **op1_names
;
16889 const char **names
= (address_mode
== mode_64bit
16890 ? names64
: names32
);
16892 if (!(prefixes
& PREFIX_ADDR
))
16893 op1_names
= (address_mode
== mode_16bit
16894 ? names16
: names
);
16897 /* Remove "addr16/addr32". */
16898 all_prefixes
[last_addr_prefix
] = 0;
16899 op1_names
= (address_mode
!= mode_32bit
16900 ? names32
: names16
);
16901 used_prefixes
|= PREFIX_ADDR
;
16903 strcpy (op_out
[0], op1_names
[0]);
16904 strcpy (op_out
[1], names
[1]);
16905 strcpy (op_out
[2], names
[2]);
16906 two_source_ops
= 1;
16908 /* Skip mod/rm byte. */
16916 /* Throw away prefixes and 1st. opcode byte. */
16917 codep
= insn_codep
+ 1;
16922 REP_Fixup (int bytemode
, int sizeflag
)
16924 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
16926 if (prefixes
& PREFIX_REPZ
)
16927 all_prefixes
[last_repz_prefix
] = REP_PREFIX
;
16934 OP_IMREG (bytemode
, sizeflag
);
16937 OP_ESreg (bytemode
, sizeflag
);
16940 OP_DSreg (bytemode
, sizeflag
);
16948 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
16952 BND_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16954 if (prefixes
& PREFIX_REPNZ
)
16955 all_prefixes
[last_repnz_prefix
] = BND_PREFIX
;
16958 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
16962 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED
,
16963 int sizeflag ATTRIBUTE_UNUSED
)
16965 if (active_seg_prefix
== PREFIX_DS
16966 && (address_mode
!= mode_64bit
|| last_data_prefix
< 0))
16968 /* NOTRACK prefix is only valid on indirect branch instructions.
16969 NB: DATA prefix is unsupported for Intel64. */
16970 active_seg_prefix
= 0;
16971 all_prefixes
[last_seg_prefix
] = NOTRACK_PREFIX
;
16975 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
16976 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
16980 HLE_Fixup1 (int bytemode
, int sizeflag
)
16983 && (prefixes
& PREFIX_LOCK
) != 0)
16985 if (prefixes
& PREFIX_REPZ
)
16986 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
16987 if (prefixes
& PREFIX_REPNZ
)
16988 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
16991 OP_E (bytemode
, sizeflag
);
16994 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
16995 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
16999 HLE_Fixup2 (int bytemode
, int sizeflag
)
17001 if (modrm
.mod
!= 3)
17003 if (prefixes
& PREFIX_REPZ
)
17004 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
17005 if (prefixes
& PREFIX_REPNZ
)
17006 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
17009 OP_E (bytemode
, sizeflag
);
17012 /* Similar to OP_E. But the 0xf3 prefixes should be displayed as
17013 "xrelease" for memory operand. No check for LOCK prefix. */
17016 HLE_Fixup3 (int bytemode
, int sizeflag
)
17019 && last_repz_prefix
> last_repnz_prefix
17020 && (prefixes
& PREFIX_REPZ
) != 0)
17021 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
17023 OP_E (bytemode
, sizeflag
);
17027 CMPXCHG8B_Fixup (int bytemode
, int sizeflag
)
17032 /* Change cmpxchg8b to cmpxchg16b. */
17033 char *p
= mnemonicendp
- 2;
17034 mnemonicendp
= stpcpy (p
, "16b");
17037 else if ((prefixes
& PREFIX_LOCK
) != 0)
17039 if (prefixes
& PREFIX_REPZ
)
17040 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
17041 if (prefixes
& PREFIX_REPNZ
)
17042 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
17045 OP_M (bytemode
, sizeflag
);
17049 XMM_Fixup (int reg
, int sizeflag ATTRIBUTE_UNUSED
)
17051 const char **names
;
17055 switch (vex
.length
)
17069 oappend (names
[reg
]);
17073 CRC32_Fixup (int bytemode
, int sizeflag
)
17075 /* Add proper suffix to "crc32". */
17076 char *p
= mnemonicendp
;
17095 if (sizeflag
& DFLAG
)
17099 used_prefixes
|= (prefixes
& PREFIX_DATA
);
17103 oappend (INTERNAL_DISASSEMBLER_ERROR
);
17110 if (modrm
.mod
== 3)
17114 /* Skip mod/rm byte. */
17119 add
= (rex
& REX_B
) ? 8 : 0;
17120 if (bytemode
== b_mode
)
17124 oappend (names8rex
[modrm
.rm
+ add
]);
17126 oappend (names8
[modrm
.rm
+ add
]);
17132 oappend (names64
[modrm
.rm
+ add
]);
17133 else if ((prefixes
& PREFIX_DATA
))
17134 oappend (names16
[modrm
.rm
+ add
]);
17136 oappend (names32
[modrm
.rm
+ add
]);
17140 OP_E (bytemode
, sizeflag
);
17144 FXSAVE_Fixup (int bytemode
, int sizeflag
)
17146 /* Add proper suffix to "fxsave" and "fxrstor". */
17150 char *p
= mnemonicendp
;
17156 OP_M (bytemode
, sizeflag
);
17160 PCMPESTR_Fixup (int bytemode
, int sizeflag
)
17162 /* Add proper suffix to "{,v}pcmpestr{i,m}". */
17165 char *p
= mnemonicendp
;
17170 else if (sizeflag
& SUFFIX_ALWAYS
)
17177 OP_EX (bytemode
, sizeflag
);
17180 /* Display the destination register operand for instructions with
17184 OP_VEX (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
17187 const char **names
;
17195 reg
= vex
.register_specifier
;
17196 if (address_mode
!= mode_64bit
)
17198 else if (vex
.evex
&& !vex
.v
)
17201 if (bytemode
== vex_scalar_mode
)
17203 oappend (names_xmm
[reg
]);
17207 switch (vex
.length
)
17214 case vex_vsib_q_w_dq_mode
:
17215 case vex_vsib_q_w_d_mode
:
17231 names
= names_mask
;
17245 case vex_vsib_q_w_dq_mode
:
17246 case vex_vsib_q_w_d_mode
:
17247 names
= vex
.w
? names_ymm
: names_xmm
;
17256 names
= names_mask
;
17259 /* See PR binutils/20893 for a reproducer. */
17271 oappend (names
[reg
]);
17274 /* Get the VEX immediate byte without moving codep. */
17276 static unsigned char
17277 get_vex_imm8 (int sizeflag
, int opnum
)
17279 int bytes_before_imm
= 0;
17281 if (modrm
.mod
!= 3)
17283 /* There are SIB/displacement bytes. */
17284 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
17286 /* 32/64 bit address mode */
17287 int base
= modrm
.rm
;
17289 /* Check SIB byte. */
17292 FETCH_DATA (the_info
, codep
+ 1);
17294 /* When decoding the third source, don't increase
17295 bytes_before_imm as this has already been incremented
17296 by one in OP_E_memory while decoding the second
17299 bytes_before_imm
++;
17302 /* Don't increase bytes_before_imm when decoding the third source,
17303 it has already been incremented by OP_E_memory while decoding
17304 the second source operand. */
17310 /* When modrm.rm == 5 or modrm.rm == 4 and base in
17311 SIB == 5, there is a 4 byte displacement. */
17313 /* No displacement. */
17315 /* Fall through. */
17317 /* 4 byte displacement. */
17318 bytes_before_imm
+= 4;
17321 /* 1 byte displacement. */
17322 bytes_before_imm
++;
17329 /* 16 bit address mode */
17330 /* Don't increase bytes_before_imm when decoding the third source,
17331 it has already been incremented by OP_E_memory while decoding
17332 the second source operand. */
17338 /* When modrm.rm == 6, there is a 2 byte displacement. */
17340 /* No displacement. */
17342 /* Fall through. */
17344 /* 2 byte displacement. */
17345 bytes_before_imm
+= 2;
17348 /* 1 byte displacement: when decoding the third source,
17349 don't increase bytes_before_imm as this has already
17350 been incremented by one in OP_E_memory while decoding
17351 the second source operand. */
17353 bytes_before_imm
++;
17361 FETCH_DATA (the_info
, codep
+ bytes_before_imm
+ 1);
17362 return codep
[bytes_before_imm
];
17366 OP_EX_VexReg (int bytemode
, int sizeflag
, int reg
)
17368 const char **names
;
17370 if (reg
== -1 && modrm
.mod
!= 3)
17372 OP_E_memory (bytemode
, sizeflag
);
17384 if (address_mode
!= mode_64bit
)
17388 switch (vex
.length
)
17399 oappend (names
[reg
]);
17403 OP_EX_VexImmW (int bytemode
, int sizeflag
)
17406 static unsigned char vex_imm8
;
17408 if (vex_w_done
== 0)
17412 /* Skip mod/rm byte. */
17416 vex_imm8
= get_vex_imm8 (sizeflag
, 0);
17419 reg
= vex_imm8
>> 4;
17421 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
17423 else if (vex_w_done
== 1)
17428 reg
= vex_imm8
>> 4;
17430 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
17434 /* Output the imm8 directly. */
17435 scratchbuf
[0] = '$';
17436 print_operand_value (scratchbuf
+ 1, 1, vex_imm8
& 0xf);
17437 oappend_maybe_intel (scratchbuf
);
17438 scratchbuf
[0] = '\0';
17444 OP_Vex_2src (int bytemode
, int sizeflag
)
17446 if (modrm
.mod
== 3)
17448 int reg
= modrm
.rm
;
17452 oappend (names_xmm
[reg
]);
17457 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
17459 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
17460 used_prefixes
|= (prefixes
& PREFIX_DATA
);
17462 OP_E (bytemode
, sizeflag
);
17467 OP_Vex_2src_1 (int bytemode
, int sizeflag
)
17469 if (modrm
.mod
== 3)
17471 /* Skip mod/rm byte. */
17478 unsigned int reg
= vex
.register_specifier
;
17480 if (address_mode
!= mode_64bit
)
17482 oappend (names_xmm
[reg
]);
17485 OP_Vex_2src (bytemode
, sizeflag
);
17489 OP_Vex_2src_2 (int bytemode
, int sizeflag
)
17492 OP_Vex_2src (bytemode
, sizeflag
);
17495 unsigned int reg
= vex
.register_specifier
;
17497 if (address_mode
!= mode_64bit
)
17499 oappend (names_xmm
[reg
]);
17504 OP_EX_VexW (int bytemode
, int sizeflag
)
17510 /* Skip mod/rm byte. */
17515 reg
= get_vex_imm8 (sizeflag
, 0) >> 4;
17520 reg
= get_vex_imm8 (sizeflag
, 1) >> 4;
17523 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
17531 OP_REG_VexI4 (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
17534 const char **names
;
17536 FETCH_DATA (the_info
, codep
+ 1);
17539 if (bytemode
!= x_mode
)
17543 if (address_mode
!= mode_64bit
)
17546 switch (vex
.length
)
17557 oappend (names
[reg
]);
17561 OP_XMM_VexW (int bytemode
, int sizeflag
)
17563 /* Turn off the REX.W bit since it is used for swapping operands
17566 OP_XMM (bytemode
, sizeflag
);
17570 OP_EX_Vex (int bytemode
, int sizeflag
)
17572 if (modrm
.mod
!= 3)
17574 if (vex
.register_specifier
!= 0)
17578 OP_EX (bytemode
, sizeflag
);
17582 OP_XMM_Vex (int bytemode
, int sizeflag
)
17584 if (modrm
.mod
!= 3)
17586 if (vex
.register_specifier
!= 0)
17590 OP_XMM (bytemode
, sizeflag
);
17594 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
17596 switch (vex
.length
)
17599 mnemonicendp
= stpcpy (obuf
, "vzeroupper");
17602 mnemonicendp
= stpcpy (obuf
, "vzeroall");
17609 static struct op vex_cmp_op
[] =
17611 { STRING_COMMA_LEN ("eq") },
17612 { STRING_COMMA_LEN ("lt") },
17613 { STRING_COMMA_LEN ("le") },
17614 { STRING_COMMA_LEN ("unord") },
17615 { STRING_COMMA_LEN ("neq") },
17616 { STRING_COMMA_LEN ("nlt") },
17617 { STRING_COMMA_LEN ("nle") },
17618 { STRING_COMMA_LEN ("ord") },
17619 { STRING_COMMA_LEN ("eq_uq") },
17620 { STRING_COMMA_LEN ("nge") },
17621 { STRING_COMMA_LEN ("ngt") },
17622 { STRING_COMMA_LEN ("false") },
17623 { STRING_COMMA_LEN ("neq_oq") },
17624 { STRING_COMMA_LEN ("ge") },
17625 { STRING_COMMA_LEN ("gt") },
17626 { STRING_COMMA_LEN ("true") },
17627 { STRING_COMMA_LEN ("eq_os") },
17628 { STRING_COMMA_LEN ("lt_oq") },
17629 { STRING_COMMA_LEN ("le_oq") },
17630 { STRING_COMMA_LEN ("unord_s") },
17631 { STRING_COMMA_LEN ("neq_us") },
17632 { STRING_COMMA_LEN ("nlt_uq") },
17633 { STRING_COMMA_LEN ("nle_uq") },
17634 { STRING_COMMA_LEN ("ord_s") },
17635 { STRING_COMMA_LEN ("eq_us") },
17636 { STRING_COMMA_LEN ("nge_uq") },
17637 { STRING_COMMA_LEN ("ngt_uq") },
17638 { STRING_COMMA_LEN ("false_os") },
17639 { STRING_COMMA_LEN ("neq_os") },
17640 { STRING_COMMA_LEN ("ge_oq") },
17641 { STRING_COMMA_LEN ("gt_oq") },
17642 { STRING_COMMA_LEN ("true_us") },
17646 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
17648 unsigned int cmp_type
;
17650 FETCH_DATA (the_info
, codep
+ 1);
17651 cmp_type
= *codep
++ & 0xff;
17652 if (cmp_type
< ARRAY_SIZE (vex_cmp_op
))
17655 char *p
= mnemonicendp
- 2;
17659 sprintf (p
, "%s%s", vex_cmp_op
[cmp_type
].name
, suffix
);
17660 mnemonicendp
+= vex_cmp_op
[cmp_type
].len
;
17664 /* We have a reserved extension byte. Output it directly. */
17665 scratchbuf
[0] = '$';
17666 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
17667 oappend_maybe_intel (scratchbuf
);
17668 scratchbuf
[0] = '\0';
17673 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
,
17674 int sizeflag ATTRIBUTE_UNUSED
)
17676 unsigned int cmp_type
;
17681 FETCH_DATA (the_info
, codep
+ 1);
17682 cmp_type
= *codep
++ & 0xff;
17683 /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
17684 If it's the case, print suffix, otherwise - print the immediate. */
17685 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
)
17690 char *p
= mnemonicendp
- 2;
17692 /* vpcmp* can have both one- and two-lettered suffix. */
17706 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
17707 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
17711 /* We have a reserved extension byte. Output it directly. */
17712 scratchbuf
[0] = '$';
17713 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
17714 oappend_maybe_intel (scratchbuf
);
17715 scratchbuf
[0] = '\0';
17719 static const struct op xop_cmp_op
[] =
17721 { STRING_COMMA_LEN ("lt") },
17722 { STRING_COMMA_LEN ("le") },
17723 { STRING_COMMA_LEN ("gt") },
17724 { STRING_COMMA_LEN ("ge") },
17725 { STRING_COMMA_LEN ("eq") },
17726 { STRING_COMMA_LEN ("neq") },
17727 { STRING_COMMA_LEN ("false") },
17728 { STRING_COMMA_LEN ("true") }
17732 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED
,
17733 int sizeflag ATTRIBUTE_UNUSED
)
17735 unsigned int cmp_type
;
17737 FETCH_DATA (the_info
, codep
+ 1);
17738 cmp_type
= *codep
++ & 0xff;
17739 if (cmp_type
< ARRAY_SIZE (xop_cmp_op
))
17742 char *p
= mnemonicendp
- 2;
17744 /* vpcom* can have both one- and two-lettered suffix. */
17758 sprintf (p
, "%s%s", xop_cmp_op
[cmp_type
].name
, suffix
);
17759 mnemonicendp
+= xop_cmp_op
[cmp_type
].len
;
17763 /* We have a reserved extension byte. Output it directly. */
17764 scratchbuf
[0] = '$';
17765 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
17766 oappend_maybe_intel (scratchbuf
);
17767 scratchbuf
[0] = '\0';
17771 static const struct op pclmul_op
[] =
17773 { STRING_COMMA_LEN ("lql") },
17774 { STRING_COMMA_LEN ("hql") },
17775 { STRING_COMMA_LEN ("lqh") },
17776 { STRING_COMMA_LEN ("hqh") }
17780 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED
,
17781 int sizeflag ATTRIBUTE_UNUSED
)
17783 unsigned int pclmul_type
;
17785 FETCH_DATA (the_info
, codep
+ 1);
17786 pclmul_type
= *codep
++ & 0xff;
17787 switch (pclmul_type
)
17798 if (pclmul_type
< ARRAY_SIZE (pclmul_op
))
17801 char *p
= mnemonicendp
- 3;
17806 sprintf (p
, "%s%s", pclmul_op
[pclmul_type
].name
, suffix
);
17807 mnemonicendp
+= pclmul_op
[pclmul_type
].len
;
17811 /* We have a reserved extension byte. Output it directly. */
17812 scratchbuf
[0] = '$';
17813 print_operand_value (scratchbuf
+ 1, 1, pclmul_type
);
17814 oappend_maybe_intel (scratchbuf
);
17815 scratchbuf
[0] = '\0';
17820 MOVBE_Fixup (int bytemode
, int sizeflag
)
17822 /* Add proper suffix to "movbe". */
17823 char *p
= mnemonicendp
;
17832 if (sizeflag
& SUFFIX_ALWAYS
)
17838 if (sizeflag
& DFLAG
)
17842 used_prefixes
|= (prefixes
& PREFIX_DATA
);
17847 oappend (INTERNAL_DISASSEMBLER_ERROR
);
17854 OP_M (bytemode
, sizeflag
);
17858 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
17861 const char **names
;
17863 /* Skip mod/rm byte. */
17877 oappend (names
[reg
]);
17881 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
17883 const char **names
;
17884 unsigned int reg
= vex
.register_specifier
;
17891 if (address_mode
!= mode_64bit
)
17893 oappend (names
[reg
]);
17897 OP_Mask (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
17900 || (bytemode
!= mask_mode
&& bytemode
!= mask_bd_mode
))
17904 if ((rex
& REX_R
) != 0 || !vex
.r
)
17910 oappend (names_mask
[modrm
.reg
]);
17914 OP_Rounding (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
17917 || (bytemode
!= evex_rounding_mode
17918 && bytemode
!= evex_sae_mode
))
17920 if (modrm
.mod
== 3 && vex
.b
)
17923 case evex_rounding_mode
:
17924 oappend (names_rounding
[vex
.ll
]);
17926 case evex_sae_mode
: