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[deliverable/binutils-gdb.git] / opcodes / i386-dis.c
1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
5
6 This file is part of the GNU opcodes library.
7
8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
11 any later version.
12
13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
22
23
24 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
25 July 1988
26 modified by John Hassey (hassey@dg-rtp.dg.com)
27 x86-64 support added by Jan Hubicka (jh@suse.cz)
28 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
29
30 /* The main tables describing the instructions is essentially a copy
31 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
32 Programmers Manual. Usually, there is a capital letter, followed
33 by a small letter. The capital letter tell the addressing mode,
34 and the small letter tells about the operand size. Refer to
35 the Intel manual for details. */
36
37 #include "sysdep.h"
38 #include "dis-asm.h"
39 #include "opintl.h"
40 #include "opcode/i386.h"
41 #include "libiberty.h"
42
43 #include <setjmp.h>
44
45 static int fetch_data (struct disassemble_info *, bfd_byte *);
46 static void ckprefix (void);
47 static const char *prefix_name (int, int);
48 static int print_insn (bfd_vma, disassemble_info *);
49 static void dofloat (int);
50 static void OP_ST (int, int);
51 static void OP_STi (int, int);
52 static int putop (const char *, int);
53 static void oappend (const char *);
54 static void append_seg (void);
55 static void OP_indirE (int, int);
56 static void print_operand_value (char *, int, bfd_vma);
57 static void OP_E_register (int, int);
58 static void OP_E_memory (int, int, int);
59 static void OP_E_extended (int, int, int);
60 static void print_displacement (char *, bfd_vma);
61 static void OP_E (int, int);
62 static void OP_G (int, int);
63 static bfd_vma get64 (void);
64 static bfd_signed_vma get32 (void);
65 static bfd_signed_vma get32s (void);
66 static int get16 (void);
67 static void set_op (bfd_vma, int);
68 static void OP_Skip_MODRM (int, int);
69 static void OP_REG (int, int);
70 static void OP_IMREG (int, int);
71 static void OP_I (int, int);
72 static void OP_I64 (int, int);
73 static void OP_sI (int, int);
74 static void OP_J (int, int);
75 static void OP_SEG (int, int);
76 static void OP_DIR (int, int);
77 static void OP_OFF (int, int);
78 static void OP_OFF64 (int, int);
79 static void ptr_reg (int, int);
80 static void OP_ESreg (int, int);
81 static void OP_DSreg (int, int);
82 static void OP_C (int, int);
83 static void OP_D (int, int);
84 static void OP_T (int, int);
85 static void OP_R (int, int);
86 static void OP_MMX (int, int);
87 static void OP_XMM (int, int);
88 static void OP_EM (int, int);
89 static void OP_EX (int, int);
90 static void OP_EMC (int,int);
91 static void OP_MXC (int,int);
92 static void OP_MS (int, int);
93 static void OP_XS (int, int);
94 static void OP_M (int, int);
95 static void OP_VEX (int, int);
96 static void OP_EX_Vex (int, int);
97 static void OP_XMM_Vex (int, int);
98 static void OP_REG_VexI4 (int, int);
99 static void PCLMUL_Fixup (int, int);
100 static void VZERO_Fixup (int, int);
101 static void VCMP_Fixup (int, int);
102 static void OP_0f07 (int, int);
103 static void OP_Monitor (int, int);
104 static void OP_Mwait (int, int);
105 static void NOP_Fixup1 (int, int);
106 static void NOP_Fixup2 (int, int);
107 static void OP_3DNowSuffix (int, int);
108 static void CMP_Fixup (int, int);
109 static void BadOp (void);
110 static void REP_Fixup (int, int);
111 static void CMPXCHG8B_Fixup (int, int);
112 static void XMM_Fixup (int, int);
113 static void CRC32_Fixup (int, int);
114 static void print_drex_arg (unsigned int, int, int);
115 static void OP_DREX4 (int, int);
116 static void OP_DREX3 (int, int);
117 static void OP_DREX_ICMP (int, int);
118 static void OP_DREX_FCMP (int, int);
119 static void MOVBE_Fixup (int, int);
120
121 struct dis_private {
122 /* Points to first byte not fetched. */
123 bfd_byte *max_fetched;
124 bfd_byte the_buffer[MAX_MNEM_SIZE];
125 bfd_vma insn_start;
126 int orig_sizeflag;
127 jmp_buf bailout;
128 };
129
130 enum address_mode
131 {
132 mode_16bit,
133 mode_32bit,
134 mode_64bit
135 };
136
137 enum address_mode address_mode;
138
139 /* Flags for the prefixes for the current instruction. See below. */
140 static int prefixes;
141
142 /* REX prefix the current instruction. See below. */
143 static int rex;
144 /* Bits of REX we've already used. */
145 static int rex_used;
146 /* Original REX prefix. */
147 static int rex_original;
148 /* REX bits in original REX prefix ignored. It may not be the same
149 as rex_original since some bits may not be ignored. */
150 static int rex_ignored;
151 /* Mark parts used in the REX prefix. When we are testing for
152 empty prefix (for 8bit register REX extension), just mask it
153 out. Otherwise test for REX bit is excuse for existence of REX
154 only in case value is nonzero. */
155 #define USED_REX(value) \
156 { \
157 if (value) \
158 { \
159 if ((rex & value)) \
160 rex_used |= (value) | REX_OPCODE; \
161 } \
162 else \
163 rex_used |= REX_OPCODE; \
164 }
165
166 /* Special 'registers' for DREX handling */
167 #define DREX_REG_UNKNOWN 1000 /* not initialized */
168 #define DREX_REG_MEMORY 1001 /* use MODRM/SIB/OFFSET memory */
169
170 /* The DREX byte has the following fields:
171 Bits 7-4 -- DREX.Dest, xmm destination register
172 Bit 3 -- DREX.OC0, operand config bit defines operand order
173 Bit 2 -- DREX.R, equivalent to REX_R bit, to extend ModRM register
174 Bit 1 -- DREX.X, equivalent to REX_X bit, to extend SIB index field
175 Bit 0 -- DREX.W, equivalent to REX_B bit, to extend ModRM r/m field,
176 SIB base field, or opcode reg field. */
177 #define DREX_XMM(drex) ((drex >> 4) & 0xf)
178 #define DREX_OC0(drex) ((drex >> 3) & 0x1)
179
180 /* Flags for prefixes which we somehow handled when printing the
181 current instruction. */
182 static int used_prefixes;
183
184 /* Flags stored in PREFIXES. */
185 #define PREFIX_REPZ 1
186 #define PREFIX_REPNZ 2
187 #define PREFIX_LOCK 4
188 #define PREFIX_CS 8
189 #define PREFIX_SS 0x10
190 #define PREFIX_DS 0x20
191 #define PREFIX_ES 0x40
192 #define PREFIX_FS 0x80
193 #define PREFIX_GS 0x100
194 #define PREFIX_DATA 0x200
195 #define PREFIX_ADDR 0x400
196 #define PREFIX_FWAIT 0x800
197
198 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
199 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
200 on error. */
201 #define FETCH_DATA(info, addr) \
202 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
203 ? 1 : fetch_data ((info), (addr)))
204
205 static int
206 fetch_data (struct disassemble_info *info, bfd_byte *addr)
207 {
208 int status;
209 struct dis_private *priv = (struct dis_private *) info->private_data;
210 bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
211
212 if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
213 status = (*info->read_memory_func) (start,
214 priv->max_fetched,
215 addr - priv->max_fetched,
216 info);
217 else
218 status = -1;
219 if (status != 0)
220 {
221 /* If we did manage to read at least one byte, then
222 print_insn_i386 will do something sensible. Otherwise, print
223 an error. We do that here because this is where we know
224 STATUS. */
225 if (priv->max_fetched == priv->the_buffer)
226 (*info->memory_error_func) (status, start, info);
227 longjmp (priv->bailout, 1);
228 }
229 else
230 priv->max_fetched = addr;
231 return 1;
232 }
233
234 #define XX { NULL, 0 }
235
236 #define Eb { OP_E, b_mode }
237 #define EbS { OP_E, b_swap_mode }
238 #define Ev { OP_E, v_mode }
239 #define EvS { OP_E, v_swap_mode }
240 #define Ed { OP_E, d_mode }
241 #define Edq { OP_E, dq_mode }
242 #define Edqw { OP_E, dqw_mode }
243 #define Edqb { OP_E, dqb_mode }
244 #define Edqd { OP_E, dqd_mode }
245 #define Eq { OP_E, q_mode }
246 #define indirEv { OP_indirE, stack_v_mode }
247 #define indirEp { OP_indirE, f_mode }
248 #define stackEv { OP_E, stack_v_mode }
249 #define Em { OP_E, m_mode }
250 #define Ew { OP_E, w_mode }
251 #define M { OP_M, 0 } /* lea, lgdt, etc. */
252 #define Ma { OP_M, a_mode }
253 #define Mb { OP_M, b_mode }
254 #define Md { OP_M, d_mode }
255 #define Mo { OP_M, o_mode }
256 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
257 #define Mq { OP_M, q_mode }
258 #define Mx { OP_M, x_mode }
259 #define Mxmm { OP_M, xmm_mode }
260 #define Gb { OP_G, b_mode }
261 #define Gv { OP_G, v_mode }
262 #define Gd { OP_G, d_mode }
263 #define Gdq { OP_G, dq_mode }
264 #define Gm { OP_G, m_mode }
265 #define Gw { OP_G, w_mode }
266 #define Rd { OP_R, d_mode }
267 #define Rm { OP_R, m_mode }
268 #define Ib { OP_I, b_mode }
269 #define sIb { OP_sI, b_mode } /* sign extened byte */
270 #define Iv { OP_I, v_mode }
271 #define Iq { OP_I, q_mode }
272 #define Iv64 { OP_I64, v_mode }
273 #define Iw { OP_I, w_mode }
274 #define I1 { OP_I, const_1_mode }
275 #define Jb { OP_J, b_mode }
276 #define Jv { OP_J, v_mode }
277 #define Cm { OP_C, m_mode }
278 #define Dm { OP_D, m_mode }
279 #define Td { OP_T, d_mode }
280 #define Skip_MODRM { OP_Skip_MODRM, 0 }
281
282 #define RMeAX { OP_REG, eAX_reg }
283 #define RMeBX { OP_REG, eBX_reg }
284 #define RMeCX { OP_REG, eCX_reg }
285 #define RMeDX { OP_REG, eDX_reg }
286 #define RMeSP { OP_REG, eSP_reg }
287 #define RMeBP { OP_REG, eBP_reg }
288 #define RMeSI { OP_REG, eSI_reg }
289 #define RMeDI { OP_REG, eDI_reg }
290 #define RMrAX { OP_REG, rAX_reg }
291 #define RMrBX { OP_REG, rBX_reg }
292 #define RMrCX { OP_REG, rCX_reg }
293 #define RMrDX { OP_REG, rDX_reg }
294 #define RMrSP { OP_REG, rSP_reg }
295 #define RMrBP { OP_REG, rBP_reg }
296 #define RMrSI { OP_REG, rSI_reg }
297 #define RMrDI { OP_REG, rDI_reg }
298 #define RMAL { OP_REG, al_reg }
299 #define RMAL { OP_REG, al_reg }
300 #define RMCL { OP_REG, cl_reg }
301 #define RMDL { OP_REG, dl_reg }
302 #define RMBL { OP_REG, bl_reg }
303 #define RMAH { OP_REG, ah_reg }
304 #define RMCH { OP_REG, ch_reg }
305 #define RMDH { OP_REG, dh_reg }
306 #define RMBH { OP_REG, bh_reg }
307 #define RMAX { OP_REG, ax_reg }
308 #define RMDX { OP_REG, dx_reg }
309
310 #define eAX { OP_IMREG, eAX_reg }
311 #define eBX { OP_IMREG, eBX_reg }
312 #define eCX { OP_IMREG, eCX_reg }
313 #define eDX { OP_IMREG, eDX_reg }
314 #define eSP { OP_IMREG, eSP_reg }
315 #define eBP { OP_IMREG, eBP_reg }
316 #define eSI { OP_IMREG, eSI_reg }
317 #define eDI { OP_IMREG, eDI_reg }
318 #define AL { OP_IMREG, al_reg }
319 #define CL { OP_IMREG, cl_reg }
320 #define DL { OP_IMREG, dl_reg }
321 #define BL { OP_IMREG, bl_reg }
322 #define AH { OP_IMREG, ah_reg }
323 #define CH { OP_IMREG, ch_reg }
324 #define DH { OP_IMREG, dh_reg }
325 #define BH { OP_IMREG, bh_reg }
326 #define AX { OP_IMREG, ax_reg }
327 #define DX { OP_IMREG, dx_reg }
328 #define zAX { OP_IMREG, z_mode_ax_reg }
329 #define indirDX { OP_IMREG, indir_dx_reg }
330
331 #define Sw { OP_SEG, w_mode }
332 #define Sv { OP_SEG, v_mode }
333 #define Ap { OP_DIR, 0 }
334 #define Ob { OP_OFF64, b_mode }
335 #define Ov { OP_OFF64, v_mode }
336 #define Xb { OP_DSreg, eSI_reg }
337 #define Xv { OP_DSreg, eSI_reg }
338 #define Xz { OP_DSreg, eSI_reg }
339 #define Yb { OP_ESreg, eDI_reg }
340 #define Yv { OP_ESreg, eDI_reg }
341 #define DSBX { OP_DSreg, eBX_reg }
342
343 #define es { OP_REG, es_reg }
344 #define ss { OP_REG, ss_reg }
345 #define cs { OP_REG, cs_reg }
346 #define ds { OP_REG, ds_reg }
347 #define fs { OP_REG, fs_reg }
348 #define gs { OP_REG, gs_reg }
349
350 #define MX { OP_MMX, 0 }
351 #define XM { OP_XMM, 0 }
352 #define XMM { OP_XMM, xmm_mode }
353 #define EM { OP_EM, v_mode }
354 #define EMS { OP_EM, v_swap_mode }
355 #define EMd { OP_EM, d_mode }
356 #define EMx { OP_EM, x_mode }
357 #define EXw { OP_EX, w_mode }
358 #define EXd { OP_EX, d_mode }
359 #define EXdS { OP_EX, d_swap_mode }
360 #define EXq { OP_EX, q_mode }
361 #define EXqS { OP_EX, q_swap_mode }
362 #define EXx { OP_EX, x_mode }
363 #define EXxS { OP_EX, x_swap_mode }
364 #define EXxmm { OP_EX, xmm_mode }
365 #define EXxmmq { OP_EX, xmmq_mode }
366 #define EXymmq { OP_EX, ymmq_mode }
367 #define EXVexWdq { OP_EX, vex_w_dq_mode }
368 #define MS { OP_MS, v_mode }
369 #define XS { OP_XS, v_mode }
370 #define EMCq { OP_EMC, q_mode }
371 #define MXC { OP_MXC, 0 }
372 #define OPSUF { OP_3DNowSuffix, 0 }
373 #define CMP { CMP_Fixup, 0 }
374 #define XMM0 { XMM_Fixup, 0 }
375
376 #define Vex { OP_VEX, vex_mode }
377 #define Vex128 { OP_VEX, vex128_mode }
378 #define Vex256 { OP_VEX, vex256_mode }
379 #define EXdVex { OP_EX_Vex, d_mode }
380 #define EXdVexS { OP_EX_Vex, d_swap_mode }
381 #define EXqVex { OP_EX_Vex, q_mode }
382 #define EXqVexS { OP_EX_Vex, q_swap_mode }
383 #define XMVex { OP_XMM_Vex, 0 }
384 #define XMVexI4 { OP_REG_VexI4, x_mode }
385 #define PCLMUL { PCLMUL_Fixup, 0 }
386 #define VZERO { VZERO_Fixup, 0 }
387 #define VCMP { VCMP_Fixup, 0 }
388
389 /* Used handle "rep" prefix for string instructions. */
390 #define Xbr { REP_Fixup, eSI_reg }
391 #define Xvr { REP_Fixup, eSI_reg }
392 #define Ybr { REP_Fixup, eDI_reg }
393 #define Yvr { REP_Fixup, eDI_reg }
394 #define Yzr { REP_Fixup, eDI_reg }
395 #define indirDXr { REP_Fixup, indir_dx_reg }
396 #define ALr { REP_Fixup, al_reg }
397 #define eAXr { REP_Fixup, eAX_reg }
398
399 #define cond_jump_flag { NULL, cond_jump_mode }
400 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
401
402 /* bits in sizeflag */
403 #define SUFFIX_ALWAYS 4
404 #define AFLAG 2
405 #define DFLAG 1
406
407 /* byte operand */
408 #define b_mode 1
409 /* byte operand with operand swapped */
410 #define b_swap_mode (b_mode + 1)
411 /* operand size depends on prefixes */
412 #define v_mode (b_swap_mode + 1)
413 /* operand size depends on prefixes with operand swapped */
414 #define v_swap_mode (v_mode + 1)
415 /* word operand */
416 #define w_mode (v_swap_mode + 1)
417 /* double word operand */
418 #define d_mode (w_mode + 1)
419 /* double word operand with operand swapped */
420 #define d_swap_mode (d_mode + 1)
421 /* quad word operand */
422 #define q_mode (d_swap_mode + 1)
423 /* quad word operand with operand swapped */
424 #define q_swap_mode (q_mode + 1)
425 /* ten-byte operand */
426 #define t_mode (q_swap_mode + 1)
427 /* 16-byte XMM or 32-byte YMM operand */
428 #define x_mode (t_mode + 1)
429 /* 16-byte XMM or 32-byte YMM operand with operand swapped */
430 #define x_swap_mode (x_mode + 1)
431 /* 16-byte XMM operand */
432 #define xmm_mode (x_swap_mode + 1)
433 /* 16-byte XMM or quad word operand */
434 #define xmmq_mode (xmm_mode + 1)
435 /* 32-byte YMM or quad word operand */
436 #define ymmq_mode (xmmq_mode + 1)
437 /* d_mode in 32bit, q_mode in 64bit mode. */
438 #define m_mode (ymmq_mode + 1)
439 /* pair of v_mode operands */
440 #define a_mode (m_mode + 1)
441 #define cond_jump_mode (a_mode + 1)
442 #define loop_jcxz_mode (cond_jump_mode + 1)
443 /* operand size depends on REX prefixes. */
444 #define dq_mode (loop_jcxz_mode + 1)
445 /* registers like dq_mode, memory like w_mode. */
446 #define dqw_mode (dq_mode + 1)
447 /* 4- or 6-byte pointer operand */
448 #define f_mode (dqw_mode + 1)
449 #define const_1_mode (f_mode + 1)
450 /* v_mode for stack-related opcodes. */
451 #define stack_v_mode (const_1_mode + 1)
452 /* non-quad operand size depends on prefixes */
453 #define z_mode (stack_v_mode + 1)
454 /* 16-byte operand */
455 #define o_mode (z_mode + 1)
456 /* registers like dq_mode, memory like b_mode. */
457 #define dqb_mode (o_mode + 1)
458 /* registers like dq_mode, memory like d_mode. */
459 #define dqd_mode (dqb_mode + 1)
460 /* normal vex mode */
461 #define vex_mode (dqd_mode + 1)
462 /* 128bit vex mode */
463 #define vex128_mode (vex_mode + 1)
464 /* 256bit vex mode */
465 #define vex256_mode (vex128_mode + 1)
466 /* operand size depends on the VEX.W bit. */
467 #define vex_w_dq_mode (vex256_mode + 1)
468
469 #define es_reg (vex_w_dq_mode + 1)
470 #define cs_reg (es_reg + 1)
471 #define ss_reg (cs_reg + 1)
472 #define ds_reg (ss_reg + 1)
473 #define fs_reg (ds_reg + 1)
474 #define gs_reg (fs_reg + 1)
475
476 #define eAX_reg (gs_reg + 1)
477 #define eCX_reg (eAX_reg + 1)
478 #define eDX_reg (eCX_reg + 1)
479 #define eBX_reg (eDX_reg + 1)
480 #define eSP_reg (eBX_reg + 1)
481 #define eBP_reg (eSP_reg + 1)
482 #define eSI_reg (eBP_reg + 1)
483 #define eDI_reg (eSI_reg + 1)
484
485 #define al_reg (eDI_reg + 1)
486 #define cl_reg (al_reg + 1)
487 #define dl_reg (cl_reg + 1)
488 #define bl_reg (dl_reg + 1)
489 #define ah_reg (bl_reg + 1)
490 #define ch_reg (ah_reg + 1)
491 #define dh_reg (ch_reg + 1)
492 #define bh_reg (dh_reg + 1)
493
494 #define ax_reg (bh_reg + 1)
495 #define cx_reg (ax_reg + 1)
496 #define dx_reg (cx_reg + 1)
497 #define bx_reg (dx_reg + 1)
498 #define sp_reg (bx_reg + 1)
499 #define bp_reg (sp_reg + 1)
500 #define si_reg (bp_reg + 1)
501 #define di_reg (si_reg + 1)
502
503 #define rAX_reg (di_reg + 1)
504 #define rCX_reg (rAX_reg + 1)
505 #define rDX_reg (rCX_reg + 1)
506 #define rBX_reg (rDX_reg + 1)
507 #define rSP_reg (rBX_reg + 1)
508 #define rBP_reg (rSP_reg + 1)
509 #define rSI_reg (rBP_reg + 1)
510 #define rDI_reg (rSI_reg + 1)
511
512 #define z_mode_ax_reg (rDI_reg + 1)
513 #define indir_dx_reg (z_mode_ax_reg + 1)
514
515 #define MAX_BYTEMODE indir_dx_reg
516
517 /* Flags that are OR'ed into the bytemode field to pass extra
518 information. */
519 #define DREX_OC1 0x10000 /* OC1 bit set */
520 #define DREX_NO_OC0 0x20000 /* OC0 bit not used */
521 #define DREX_MASK 0x40000 /* mask to delete */
522
523 #if MAX_BYTEMODE >= DREX_OC1
524 #error MAX_BYTEMODE must be less than DREX_OC1
525 #endif
526
527 #define FLOATCODE 1
528 #define USE_REG_TABLE (FLOATCODE + 1)
529 #define USE_MOD_TABLE (USE_REG_TABLE + 1)
530 #define USE_RM_TABLE (USE_MOD_TABLE + 1)
531 #define USE_PREFIX_TABLE (USE_RM_TABLE + 1)
532 #define USE_X86_64_TABLE (USE_PREFIX_TABLE + 1)
533 #define USE_3BYTE_TABLE (USE_X86_64_TABLE + 1)
534 #define USE_VEX_C4_TABLE (USE_3BYTE_TABLE + 1)
535 #define USE_VEX_C5_TABLE (USE_VEX_C4_TABLE + 1)
536 #define USE_VEX_LEN_TABLE (USE_VEX_C5_TABLE + 1)
537
538 #define FLOAT NULL, { { NULL, FLOATCODE } }
539
540 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }
541 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
542 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
543 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
544 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
545 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
546 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
547 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
548 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
549 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
550
551 #define REG_80 0
552 #define REG_81 (REG_80 + 1)
553 #define REG_82 (REG_81 + 1)
554 #define REG_8F (REG_82 + 1)
555 #define REG_C0 (REG_8F + 1)
556 #define REG_C1 (REG_C0 + 1)
557 #define REG_C6 (REG_C1 + 1)
558 #define REG_C7 (REG_C6 + 1)
559 #define REG_D0 (REG_C7 + 1)
560 #define REG_D1 (REG_D0 + 1)
561 #define REG_D2 (REG_D1 + 1)
562 #define REG_D3 (REG_D2 + 1)
563 #define REG_F6 (REG_D3 + 1)
564 #define REG_F7 (REG_F6 + 1)
565 #define REG_FE (REG_F7 + 1)
566 #define REG_FF (REG_FE + 1)
567 #define REG_0F00 (REG_FF + 1)
568 #define REG_0F01 (REG_0F00 + 1)
569 #define REG_0F0D (REG_0F01 + 1)
570 #define REG_0F18 (REG_0F0D + 1)
571 #define REG_0F71 (REG_0F18 + 1)
572 #define REG_0F72 (REG_0F71 + 1)
573 #define REG_0F73 (REG_0F72 + 1)
574 #define REG_0FA6 (REG_0F73 + 1)
575 #define REG_0FA7 (REG_0FA6 + 1)
576 #define REG_0FAE (REG_0FA7 + 1)
577 #define REG_0FBA (REG_0FAE + 1)
578 #define REG_0FC7 (REG_0FBA + 1)
579 #define REG_VEX_71 (REG_0FC7 + 1)
580 #define REG_VEX_72 (REG_VEX_71 + 1)
581 #define REG_VEX_73 (REG_VEX_72 + 1)
582 #define REG_VEX_AE (REG_VEX_73 + 1)
583
584 #define MOD_8D 0
585 #define MOD_0F01_REG_0 (MOD_8D + 1)
586 #define MOD_0F01_REG_1 (MOD_0F01_REG_0 + 1)
587 #define MOD_0F01_REG_2 (MOD_0F01_REG_1 + 1)
588 #define MOD_0F01_REG_3 (MOD_0F01_REG_2 + 1)
589 #define MOD_0F01_REG_7 (MOD_0F01_REG_3 + 1)
590 #define MOD_0F12_PREFIX_0 (MOD_0F01_REG_7 + 1)
591 #define MOD_0F13 (MOD_0F12_PREFIX_0 + 1)
592 #define MOD_0F16_PREFIX_0 (MOD_0F13 + 1)
593 #define MOD_0F17 (MOD_0F16_PREFIX_0 + 1)
594 #define MOD_0F18_REG_0 (MOD_0F17 + 1)
595 #define MOD_0F18_REG_1 (MOD_0F18_REG_0 + 1)
596 #define MOD_0F18_REG_2 (MOD_0F18_REG_1 + 1)
597 #define MOD_0F18_REG_3 (MOD_0F18_REG_2 + 1)
598 #define MOD_0F20 (MOD_0F18_REG_3 + 1)
599 #define MOD_0F21 (MOD_0F20 + 1)
600 #define MOD_0F22 (MOD_0F21 + 1)
601 #define MOD_0F23 (MOD_0F22 + 1)
602 #define MOD_0F24 (MOD_0F23 + 1)
603 #define MOD_0F26 (MOD_0F24 + 1)
604 #define MOD_0F2B_PREFIX_0 (MOD_0F26 + 1)
605 #define MOD_0F2B_PREFIX_1 (MOD_0F2B_PREFIX_0 + 1)
606 #define MOD_0F2B_PREFIX_2 (MOD_0F2B_PREFIX_1 + 1)
607 #define MOD_0F2B_PREFIX_3 (MOD_0F2B_PREFIX_2 + 1)
608 #define MOD_0F51 (MOD_0F2B_PREFIX_3 + 1)
609 #define MOD_0F71_REG_2 (MOD_0F51 + 1)
610 #define MOD_0F71_REG_4 (MOD_0F71_REG_2 + 1)
611 #define MOD_0F71_REG_6 (MOD_0F71_REG_4 + 1)
612 #define MOD_0F72_REG_2 (MOD_0F71_REG_6 + 1)
613 #define MOD_0F72_REG_4 (MOD_0F72_REG_2 + 1)
614 #define MOD_0F72_REG_6 (MOD_0F72_REG_4 + 1)
615 #define MOD_0F73_REG_2 (MOD_0F72_REG_6 + 1)
616 #define MOD_0F73_REG_3 (MOD_0F73_REG_2 + 1)
617 #define MOD_0F73_REG_6 (MOD_0F73_REG_3 + 1)
618 #define MOD_0F73_REG_7 (MOD_0F73_REG_6 + 1)
619 #define MOD_0FAE_REG_0 (MOD_0F73_REG_7 + 1)
620 #define MOD_0FAE_REG_1 (MOD_0FAE_REG_0 + 1)
621 #define MOD_0FAE_REG_2 (MOD_0FAE_REG_1 + 1)
622 #define MOD_0FAE_REG_3 (MOD_0FAE_REG_2 + 1)
623 #define MOD_0FAE_REG_4 (MOD_0FAE_REG_3 + 1)
624 #define MOD_0FAE_REG_5 (MOD_0FAE_REG_4 + 1)
625 #define MOD_0FAE_REG_6 (MOD_0FAE_REG_5 + 1)
626 #define MOD_0FAE_REG_7 (MOD_0FAE_REG_6 + 1)
627 #define MOD_0FB2 (MOD_0FAE_REG_7 + 1)
628 #define MOD_0FB4 (MOD_0FB2 + 1)
629 #define MOD_0FB5 (MOD_0FB4 + 1)
630 #define MOD_0FC7_REG_6 (MOD_0FB5 + 1)
631 #define MOD_0FC7_REG_7 (MOD_0FC7_REG_6 + 1)
632 #define MOD_0FD7 (MOD_0FC7_REG_7 + 1)
633 #define MOD_0FE7_PREFIX_2 (MOD_0FD7 + 1)
634 #define MOD_0FF0_PREFIX_3 (MOD_0FE7_PREFIX_2 + 1)
635 #define MOD_0F382A_PREFIX_2 (MOD_0FF0_PREFIX_3 + 1)
636 #define MOD_62_32BIT (MOD_0F382A_PREFIX_2 + 1)
637 #define MOD_C4_32BIT (MOD_62_32BIT + 1)
638 #define MOD_C5_32BIT (MOD_C4_32BIT + 1)
639 #define MOD_VEX_12_PREFIX_0 (MOD_C5_32BIT + 1)
640 #define MOD_VEX_13 (MOD_VEX_12_PREFIX_0 + 1)
641 #define MOD_VEX_16_PREFIX_0 (MOD_VEX_13 + 1)
642 #define MOD_VEX_17 (MOD_VEX_16_PREFIX_0 + 1)
643 #define MOD_VEX_2B (MOD_VEX_17 + 1)
644 #define MOD_VEX_51 (MOD_VEX_2B + 1)
645 #define MOD_VEX_71_REG_2 (MOD_VEX_51 + 1)
646 #define MOD_VEX_71_REG_4 (MOD_VEX_71_REG_2 + 1)
647 #define MOD_VEX_71_REG_6 (MOD_VEX_71_REG_4 + 1)
648 #define MOD_VEX_72_REG_2 (MOD_VEX_71_REG_6 + 1)
649 #define MOD_VEX_72_REG_4 (MOD_VEX_72_REG_2 + 1)
650 #define MOD_VEX_72_REG_6 (MOD_VEX_72_REG_4 + 1)
651 #define MOD_VEX_73_REG_2 (MOD_VEX_72_REG_6 + 1)
652 #define MOD_VEX_73_REG_3 (MOD_VEX_73_REG_2 + 1)
653 #define MOD_VEX_73_REG_6 (MOD_VEX_73_REG_3 + 1)
654 #define MOD_VEX_73_REG_7 (MOD_VEX_73_REG_6 + 1)
655 #define MOD_VEX_AE_REG_2 (MOD_VEX_73_REG_7 + 1)
656 #define MOD_VEX_AE_REG_3 (MOD_VEX_AE_REG_2 + 1)
657 #define MOD_VEX_D7_PREFIX_2 (MOD_VEX_AE_REG_3 + 1)
658 #define MOD_VEX_E7_PREFIX_2 (MOD_VEX_D7_PREFIX_2 + 1)
659 #define MOD_VEX_F0_PREFIX_3 (MOD_VEX_E7_PREFIX_2 + 1)
660 #define MOD_VEX_3818_PREFIX_2 (MOD_VEX_F0_PREFIX_3 + 1)
661 #define MOD_VEX_3819_PREFIX_2 (MOD_VEX_3818_PREFIX_2 + 1)
662 #define MOD_VEX_381A_PREFIX_2 (MOD_VEX_3819_PREFIX_2 + 1)
663 #define MOD_VEX_382A_PREFIX_2 (MOD_VEX_381A_PREFIX_2 + 1)
664 #define MOD_VEX_382C_PREFIX_2 (MOD_VEX_382A_PREFIX_2 + 1)
665 #define MOD_VEX_382D_PREFIX_2 (MOD_VEX_382C_PREFIX_2 + 1)
666 #define MOD_VEX_382E_PREFIX_2 (MOD_VEX_382D_PREFIX_2 + 1)
667 #define MOD_VEX_382F_PREFIX_2 (MOD_VEX_382E_PREFIX_2 + 1)
668
669 #define RM_0F01_REG_0 0
670 #define RM_0F01_REG_1 (RM_0F01_REG_0 + 1)
671 #define RM_0F01_REG_2 (RM_0F01_REG_1 + 1)
672 #define RM_0F01_REG_3 (RM_0F01_REG_2 + 1)
673 #define RM_0F01_REG_7 (RM_0F01_REG_3 + 1)
674 #define RM_0FAE_REG_5 (RM_0F01_REG_7 + 1)
675 #define RM_0FAE_REG_6 (RM_0FAE_REG_5 + 1)
676 #define RM_0FAE_REG_7 (RM_0FAE_REG_6 + 1)
677
678 #define PREFIX_90 0
679 #define PREFIX_0F10 (PREFIX_90 + 1)
680 #define PREFIX_0F11 (PREFIX_0F10 + 1)
681 #define PREFIX_0F12 (PREFIX_0F11 + 1)
682 #define PREFIX_0F16 (PREFIX_0F12 + 1)
683 #define PREFIX_0F2A (PREFIX_0F16 + 1)
684 #define PREFIX_0F2B (PREFIX_0F2A + 1)
685 #define PREFIX_0F2C (PREFIX_0F2B + 1)
686 #define PREFIX_0F2D (PREFIX_0F2C + 1)
687 #define PREFIX_0F2E (PREFIX_0F2D + 1)
688 #define PREFIX_0F2F (PREFIX_0F2E + 1)
689 #define PREFIX_0F51 (PREFIX_0F2F + 1)
690 #define PREFIX_0F52 (PREFIX_0F51 + 1)
691 #define PREFIX_0F53 (PREFIX_0F52 + 1)
692 #define PREFIX_0F58 (PREFIX_0F53 + 1)
693 #define PREFIX_0F59 (PREFIX_0F58 + 1)
694 #define PREFIX_0F5A (PREFIX_0F59 + 1)
695 #define PREFIX_0F5B (PREFIX_0F5A + 1)
696 #define PREFIX_0F5C (PREFIX_0F5B + 1)
697 #define PREFIX_0F5D (PREFIX_0F5C + 1)
698 #define PREFIX_0F5E (PREFIX_0F5D + 1)
699 #define PREFIX_0F5F (PREFIX_0F5E + 1)
700 #define PREFIX_0F60 (PREFIX_0F5F + 1)
701 #define PREFIX_0F61 (PREFIX_0F60 + 1)
702 #define PREFIX_0F62 (PREFIX_0F61 + 1)
703 #define PREFIX_0F6C (PREFIX_0F62 + 1)
704 #define PREFIX_0F6D (PREFIX_0F6C + 1)
705 #define PREFIX_0F6F (PREFIX_0F6D + 1)
706 #define PREFIX_0F70 (PREFIX_0F6F + 1)
707 #define PREFIX_0F73_REG_3 (PREFIX_0F70 + 1)
708 #define PREFIX_0F73_REG_7 (PREFIX_0F73_REG_3 + 1)
709 #define PREFIX_0F78 (PREFIX_0F73_REG_7 + 1)
710 #define PREFIX_0F79 (PREFIX_0F78 + 1)
711 #define PREFIX_0F7C (PREFIX_0F79 + 1)
712 #define PREFIX_0F7D (PREFIX_0F7C + 1)
713 #define PREFIX_0F7E (PREFIX_0F7D + 1)
714 #define PREFIX_0F7F (PREFIX_0F7E + 1)
715 #define PREFIX_0FB8 (PREFIX_0F7F + 1)
716 #define PREFIX_0FBD (PREFIX_0FB8 + 1)
717 #define PREFIX_0FC2 (PREFIX_0FBD + 1)
718 #define PREFIX_0FC3 (PREFIX_0FC2 + 1)
719 #define PREFIX_0FC7_REG_6 (PREFIX_0FC3 + 1)
720 #define PREFIX_0FD0 (PREFIX_0FC7_REG_6 + 1)
721 #define PREFIX_0FD6 (PREFIX_0FD0 + 1)
722 #define PREFIX_0FE6 (PREFIX_0FD6 + 1)
723 #define PREFIX_0FE7 (PREFIX_0FE6 + 1)
724 #define PREFIX_0FF0 (PREFIX_0FE7 + 1)
725 #define PREFIX_0FF7 (PREFIX_0FF0 + 1)
726 #define PREFIX_0F3810 (PREFIX_0FF7 + 1)
727 #define PREFIX_0F3814 (PREFIX_0F3810 + 1)
728 #define PREFIX_0F3815 (PREFIX_0F3814 + 1)
729 #define PREFIX_0F3817 (PREFIX_0F3815 + 1)
730 #define PREFIX_0F3820 (PREFIX_0F3817 + 1)
731 #define PREFIX_0F3821 (PREFIX_0F3820 + 1)
732 #define PREFIX_0F3822 (PREFIX_0F3821 + 1)
733 #define PREFIX_0F3823 (PREFIX_0F3822 + 1)
734 #define PREFIX_0F3824 (PREFIX_0F3823 + 1)
735 #define PREFIX_0F3825 (PREFIX_0F3824 + 1)
736 #define PREFIX_0F3828 (PREFIX_0F3825 + 1)
737 #define PREFIX_0F3829 (PREFIX_0F3828 + 1)
738 #define PREFIX_0F382A (PREFIX_0F3829 + 1)
739 #define PREFIX_0F382B (PREFIX_0F382A + 1)
740 #define PREFIX_0F3830 (PREFIX_0F382B + 1)
741 #define PREFIX_0F3831 (PREFIX_0F3830 + 1)
742 #define PREFIX_0F3832 (PREFIX_0F3831 + 1)
743 #define PREFIX_0F3833 (PREFIX_0F3832 + 1)
744 #define PREFIX_0F3834 (PREFIX_0F3833 + 1)
745 #define PREFIX_0F3835 (PREFIX_0F3834 + 1)
746 #define PREFIX_0F3837 (PREFIX_0F3835 + 1)
747 #define PREFIX_0F3838 (PREFIX_0F3837 + 1)
748 #define PREFIX_0F3839 (PREFIX_0F3838 + 1)
749 #define PREFIX_0F383A (PREFIX_0F3839 + 1)
750 #define PREFIX_0F383B (PREFIX_0F383A + 1)
751 #define PREFIX_0F383C (PREFIX_0F383B + 1)
752 #define PREFIX_0F383D (PREFIX_0F383C + 1)
753 #define PREFIX_0F383E (PREFIX_0F383D + 1)
754 #define PREFIX_0F383F (PREFIX_0F383E + 1)
755 #define PREFIX_0F3840 (PREFIX_0F383F + 1)
756 #define PREFIX_0F3841 (PREFIX_0F3840 + 1)
757 #define PREFIX_0F3880 (PREFIX_0F3841 + 1)
758 #define PREFIX_0F3881 (PREFIX_0F3880 + 1)
759 #define PREFIX_0F38DB (PREFIX_0F3881 + 1)
760 #define PREFIX_0F38DC (PREFIX_0F38DB + 1)
761 #define PREFIX_0F38DD (PREFIX_0F38DC + 1)
762 #define PREFIX_0F38DE (PREFIX_0F38DD + 1)
763 #define PREFIX_0F38DF (PREFIX_0F38DE + 1)
764 #define PREFIX_0F38F0 (PREFIX_0F38DF + 1)
765 #define PREFIX_0F38F1 (PREFIX_0F38F0 + 1)
766 #define PREFIX_0F3A08 (PREFIX_0F38F1 + 1)
767 #define PREFIX_0F3A09 (PREFIX_0F3A08 + 1)
768 #define PREFIX_0F3A0A (PREFIX_0F3A09 + 1)
769 #define PREFIX_0F3A0B (PREFIX_0F3A0A + 1)
770 #define PREFIX_0F3A0C (PREFIX_0F3A0B + 1)
771 #define PREFIX_0F3A0D (PREFIX_0F3A0C + 1)
772 #define PREFIX_0F3A0E (PREFIX_0F3A0D + 1)
773 #define PREFIX_0F3A14 (PREFIX_0F3A0E + 1)
774 #define PREFIX_0F3A15 (PREFIX_0F3A14 + 1)
775 #define PREFIX_0F3A16 (PREFIX_0F3A15 + 1)
776 #define PREFIX_0F3A17 (PREFIX_0F3A16 + 1)
777 #define PREFIX_0F3A20 (PREFIX_0F3A17 + 1)
778 #define PREFIX_0F3A21 (PREFIX_0F3A20 + 1)
779 #define PREFIX_0F3A22 (PREFIX_0F3A21 + 1)
780 #define PREFIX_0F3A40 (PREFIX_0F3A22 + 1)
781 #define PREFIX_0F3A41 (PREFIX_0F3A40 + 1)
782 #define PREFIX_0F3A42 (PREFIX_0F3A41 + 1)
783 #define PREFIX_0F3A44 (PREFIX_0F3A42 + 1)
784 #define PREFIX_0F3A60 (PREFIX_0F3A44 + 1)
785 #define PREFIX_0F3A61 (PREFIX_0F3A60 + 1)
786 #define PREFIX_0F3A62 (PREFIX_0F3A61 + 1)
787 #define PREFIX_0F3A63 (PREFIX_0F3A62 + 1)
788 #define PREFIX_0F3ADF (PREFIX_0F3A63 + 1)
789 #define PREFIX_VEX_10 (PREFIX_0F3ADF + 1)
790 #define PREFIX_VEX_11 (PREFIX_VEX_10 + 1)
791 #define PREFIX_VEX_12 (PREFIX_VEX_11 + 1)
792 #define PREFIX_VEX_16 (PREFIX_VEX_12 + 1)
793 #define PREFIX_VEX_2A (PREFIX_VEX_16 + 1)
794 #define PREFIX_VEX_2C (PREFIX_VEX_2A + 1)
795 #define PREFIX_VEX_2D (PREFIX_VEX_2C + 1)
796 #define PREFIX_VEX_2E (PREFIX_VEX_2D + 1)
797 #define PREFIX_VEX_2F (PREFIX_VEX_2E + 1)
798 #define PREFIX_VEX_51 (PREFIX_VEX_2F + 1)
799 #define PREFIX_VEX_52 (PREFIX_VEX_51 + 1)
800 #define PREFIX_VEX_53 (PREFIX_VEX_52 + 1)
801 #define PREFIX_VEX_58 (PREFIX_VEX_53 + 1)
802 #define PREFIX_VEX_59 (PREFIX_VEX_58 + 1)
803 #define PREFIX_VEX_5A (PREFIX_VEX_59 + 1)
804 #define PREFIX_VEX_5B (PREFIX_VEX_5A + 1)
805 #define PREFIX_VEX_5C (PREFIX_VEX_5B + 1)
806 #define PREFIX_VEX_5D (PREFIX_VEX_5C + 1)
807 #define PREFIX_VEX_5E (PREFIX_VEX_5D + 1)
808 #define PREFIX_VEX_5F (PREFIX_VEX_5E + 1)
809 #define PREFIX_VEX_60 (PREFIX_VEX_5F + 1)
810 #define PREFIX_VEX_61 (PREFIX_VEX_60 + 1)
811 #define PREFIX_VEX_62 (PREFIX_VEX_61 + 1)
812 #define PREFIX_VEX_63 (PREFIX_VEX_62 + 1)
813 #define PREFIX_VEX_64 (PREFIX_VEX_63 + 1)
814 #define PREFIX_VEX_65 (PREFIX_VEX_64 + 1)
815 #define PREFIX_VEX_66 (PREFIX_VEX_65 + 1)
816 #define PREFIX_VEX_67 (PREFIX_VEX_66 + 1)
817 #define PREFIX_VEX_68 (PREFIX_VEX_67 + 1)
818 #define PREFIX_VEX_69 (PREFIX_VEX_68 + 1)
819 #define PREFIX_VEX_6A (PREFIX_VEX_69 + 1)
820 #define PREFIX_VEX_6B (PREFIX_VEX_6A + 1)
821 #define PREFIX_VEX_6C (PREFIX_VEX_6B + 1)
822 #define PREFIX_VEX_6D (PREFIX_VEX_6C + 1)
823 #define PREFIX_VEX_6E (PREFIX_VEX_6D + 1)
824 #define PREFIX_VEX_6F (PREFIX_VEX_6E + 1)
825 #define PREFIX_VEX_70 (PREFIX_VEX_6F + 1)
826 #define PREFIX_VEX_71_REG_2 (PREFIX_VEX_70 + 1)
827 #define PREFIX_VEX_71_REG_4 (PREFIX_VEX_71_REG_2 + 1)
828 #define PREFIX_VEX_71_REG_6 (PREFIX_VEX_71_REG_4 + 1)
829 #define PREFIX_VEX_72_REG_2 (PREFIX_VEX_71_REG_6 + 1)
830 #define PREFIX_VEX_72_REG_4 (PREFIX_VEX_72_REG_2 + 1)
831 #define PREFIX_VEX_72_REG_6 (PREFIX_VEX_72_REG_4 + 1)
832 #define PREFIX_VEX_73_REG_2 (PREFIX_VEX_72_REG_6 + 1)
833 #define PREFIX_VEX_73_REG_3 (PREFIX_VEX_73_REG_2 + 1)
834 #define PREFIX_VEX_73_REG_6 (PREFIX_VEX_73_REG_3 + 1)
835 #define PREFIX_VEX_73_REG_7 (PREFIX_VEX_73_REG_6 + 1)
836 #define PREFIX_VEX_74 (PREFIX_VEX_73_REG_7 + 1)
837 #define PREFIX_VEX_75 (PREFIX_VEX_74 + 1)
838 #define PREFIX_VEX_76 (PREFIX_VEX_75 + 1)
839 #define PREFIX_VEX_77 (PREFIX_VEX_76 + 1)
840 #define PREFIX_VEX_7C (PREFIX_VEX_77 + 1)
841 #define PREFIX_VEX_7D (PREFIX_VEX_7C + 1)
842 #define PREFIX_VEX_7E (PREFIX_VEX_7D + 1)
843 #define PREFIX_VEX_7F (PREFIX_VEX_7E + 1)
844 #define PREFIX_VEX_C2 (PREFIX_VEX_7F + 1)
845 #define PREFIX_VEX_C4 (PREFIX_VEX_C2 + 1)
846 #define PREFIX_VEX_C5 (PREFIX_VEX_C4 + 1)
847 #define PREFIX_VEX_D0 (PREFIX_VEX_C5 + 1)
848 #define PREFIX_VEX_D1 (PREFIX_VEX_D0 + 1)
849 #define PREFIX_VEX_D2 (PREFIX_VEX_D1 + 1)
850 #define PREFIX_VEX_D3 (PREFIX_VEX_D2 + 1)
851 #define PREFIX_VEX_D4 (PREFIX_VEX_D3 + 1)
852 #define PREFIX_VEX_D5 (PREFIX_VEX_D4 + 1)
853 #define PREFIX_VEX_D6 (PREFIX_VEX_D5 + 1)
854 #define PREFIX_VEX_D7 (PREFIX_VEX_D6 + 1)
855 #define PREFIX_VEX_D8 (PREFIX_VEX_D7 + 1)
856 #define PREFIX_VEX_D9 (PREFIX_VEX_D8 + 1)
857 #define PREFIX_VEX_DA (PREFIX_VEX_D9 + 1)
858 #define PREFIX_VEX_DB (PREFIX_VEX_DA + 1)
859 #define PREFIX_VEX_DC (PREFIX_VEX_DB + 1)
860 #define PREFIX_VEX_DD (PREFIX_VEX_DC + 1)
861 #define PREFIX_VEX_DE (PREFIX_VEX_DD + 1)
862 #define PREFIX_VEX_DF (PREFIX_VEX_DE + 1)
863 #define PREFIX_VEX_E0 (PREFIX_VEX_DF + 1)
864 #define PREFIX_VEX_E1 (PREFIX_VEX_E0 + 1)
865 #define PREFIX_VEX_E2 (PREFIX_VEX_E1 + 1)
866 #define PREFIX_VEX_E3 (PREFIX_VEX_E2 + 1)
867 #define PREFIX_VEX_E4 (PREFIX_VEX_E3 + 1)
868 #define PREFIX_VEX_E5 (PREFIX_VEX_E4 + 1)
869 #define PREFIX_VEX_E6 (PREFIX_VEX_E5 + 1)
870 #define PREFIX_VEX_E7 (PREFIX_VEX_E6 + 1)
871 #define PREFIX_VEX_E8 (PREFIX_VEX_E7 + 1)
872 #define PREFIX_VEX_E9 (PREFIX_VEX_E8 + 1)
873 #define PREFIX_VEX_EA (PREFIX_VEX_E9 + 1)
874 #define PREFIX_VEX_EB (PREFIX_VEX_EA + 1)
875 #define PREFIX_VEX_EC (PREFIX_VEX_EB + 1)
876 #define PREFIX_VEX_ED (PREFIX_VEX_EC + 1)
877 #define PREFIX_VEX_EE (PREFIX_VEX_ED + 1)
878 #define PREFIX_VEX_EF (PREFIX_VEX_EE + 1)
879 #define PREFIX_VEX_F0 (PREFIX_VEX_EF + 1)
880 #define PREFIX_VEX_F1 (PREFIX_VEX_F0 + 1)
881 #define PREFIX_VEX_F2 (PREFIX_VEX_F1 + 1)
882 #define PREFIX_VEX_F3 (PREFIX_VEX_F2 + 1)
883 #define PREFIX_VEX_F4 (PREFIX_VEX_F3 + 1)
884 #define PREFIX_VEX_F5 (PREFIX_VEX_F4 + 1)
885 #define PREFIX_VEX_F6 (PREFIX_VEX_F5 + 1)
886 #define PREFIX_VEX_F7 (PREFIX_VEX_F6 + 1)
887 #define PREFIX_VEX_F8 (PREFIX_VEX_F7 + 1)
888 #define PREFIX_VEX_F9 (PREFIX_VEX_F8 + 1)
889 #define PREFIX_VEX_FA (PREFIX_VEX_F9 + 1)
890 #define PREFIX_VEX_FB (PREFIX_VEX_FA + 1)
891 #define PREFIX_VEX_FC (PREFIX_VEX_FB + 1)
892 #define PREFIX_VEX_FD (PREFIX_VEX_FC + 1)
893 #define PREFIX_VEX_FE (PREFIX_VEX_FD + 1)
894 #define PREFIX_VEX_3800 (PREFIX_VEX_FE + 1)
895 #define PREFIX_VEX_3801 (PREFIX_VEX_3800 + 1)
896 #define PREFIX_VEX_3802 (PREFIX_VEX_3801 + 1)
897 #define PREFIX_VEX_3803 (PREFIX_VEX_3802 + 1)
898 #define PREFIX_VEX_3804 (PREFIX_VEX_3803 + 1)
899 #define PREFIX_VEX_3805 (PREFIX_VEX_3804 + 1)
900 #define PREFIX_VEX_3806 (PREFIX_VEX_3805 + 1)
901 #define PREFIX_VEX_3807 (PREFIX_VEX_3806 + 1)
902 #define PREFIX_VEX_3808 (PREFIX_VEX_3807 + 1)
903 #define PREFIX_VEX_3809 (PREFIX_VEX_3808 + 1)
904 #define PREFIX_VEX_380A (PREFIX_VEX_3809 + 1)
905 #define PREFIX_VEX_380B (PREFIX_VEX_380A + 1)
906 #define PREFIX_VEX_380C (PREFIX_VEX_380B + 1)
907 #define PREFIX_VEX_380D (PREFIX_VEX_380C + 1)
908 #define PREFIX_VEX_380E (PREFIX_VEX_380D + 1)
909 #define PREFIX_VEX_380F (PREFIX_VEX_380E + 1)
910 #define PREFIX_VEX_3817 (PREFIX_VEX_380F + 1)
911 #define PREFIX_VEX_3818 (PREFIX_VEX_3817 + 1)
912 #define PREFIX_VEX_3819 (PREFIX_VEX_3818 + 1)
913 #define PREFIX_VEX_381A (PREFIX_VEX_3819 + 1)
914 #define PREFIX_VEX_381C (PREFIX_VEX_381A + 1)
915 #define PREFIX_VEX_381D (PREFIX_VEX_381C + 1)
916 #define PREFIX_VEX_381E (PREFIX_VEX_381D + 1)
917 #define PREFIX_VEX_3820 (PREFIX_VEX_381E + 1)
918 #define PREFIX_VEX_3821 (PREFIX_VEX_3820 + 1)
919 #define PREFIX_VEX_3822 (PREFIX_VEX_3821 + 1)
920 #define PREFIX_VEX_3823 (PREFIX_VEX_3822 + 1)
921 #define PREFIX_VEX_3824 (PREFIX_VEX_3823 + 1)
922 #define PREFIX_VEX_3825 (PREFIX_VEX_3824 + 1)
923 #define PREFIX_VEX_3828 (PREFIX_VEX_3825 + 1)
924 #define PREFIX_VEX_3829 (PREFIX_VEX_3828 + 1)
925 #define PREFIX_VEX_382A (PREFIX_VEX_3829 + 1)
926 #define PREFIX_VEX_382B (PREFIX_VEX_382A + 1)
927 #define PREFIX_VEX_382C (PREFIX_VEX_382B + 1)
928 #define PREFIX_VEX_382D (PREFIX_VEX_382C + 1)
929 #define PREFIX_VEX_382E (PREFIX_VEX_382D + 1)
930 #define PREFIX_VEX_382F (PREFIX_VEX_382E + 1)
931 #define PREFIX_VEX_3830 (PREFIX_VEX_382F + 1)
932 #define PREFIX_VEX_3831 (PREFIX_VEX_3830 + 1)
933 #define PREFIX_VEX_3832 (PREFIX_VEX_3831 + 1)
934 #define PREFIX_VEX_3833 (PREFIX_VEX_3832 + 1)
935 #define PREFIX_VEX_3834 (PREFIX_VEX_3833 + 1)
936 #define PREFIX_VEX_3835 (PREFIX_VEX_3834 + 1)
937 #define PREFIX_VEX_3837 (PREFIX_VEX_3835 + 1)
938 #define PREFIX_VEX_3838 (PREFIX_VEX_3837 + 1)
939 #define PREFIX_VEX_3839 (PREFIX_VEX_3838 + 1)
940 #define PREFIX_VEX_383A (PREFIX_VEX_3839 + 1)
941 #define PREFIX_VEX_383B (PREFIX_VEX_383A + 1)
942 #define PREFIX_VEX_383C (PREFIX_VEX_383B + 1)
943 #define PREFIX_VEX_383D (PREFIX_VEX_383C + 1)
944 #define PREFIX_VEX_383E (PREFIX_VEX_383D + 1)
945 #define PREFIX_VEX_383F (PREFIX_VEX_383E + 1)
946 #define PREFIX_VEX_3840 (PREFIX_VEX_383F + 1)
947 #define PREFIX_VEX_3841 (PREFIX_VEX_3840 + 1)
948 #define PREFIX_VEX_3896 (PREFIX_VEX_3841 + 1)
949 #define PREFIX_VEX_3897 (PREFIX_VEX_3896 + 1)
950 #define PREFIX_VEX_3898 (PREFIX_VEX_3897 + 1)
951 #define PREFIX_VEX_3899 (PREFIX_VEX_3898 + 1)
952 #define PREFIX_VEX_389A (PREFIX_VEX_3899 + 1)
953 #define PREFIX_VEX_389B (PREFIX_VEX_389A + 1)
954 #define PREFIX_VEX_389C (PREFIX_VEX_389B + 1)
955 #define PREFIX_VEX_389D (PREFIX_VEX_389C + 1)
956 #define PREFIX_VEX_389E (PREFIX_VEX_389D + 1)
957 #define PREFIX_VEX_389F (PREFIX_VEX_389E + 1)
958 #define PREFIX_VEX_38A6 (PREFIX_VEX_389F + 1)
959 #define PREFIX_VEX_38A7 (PREFIX_VEX_38A6 + 1)
960 #define PREFIX_VEX_38A8 (PREFIX_VEX_38A7 + 1)
961 #define PREFIX_VEX_38A9 (PREFIX_VEX_38A8 + 1)
962 #define PREFIX_VEX_38AA (PREFIX_VEX_38A9 + 1)
963 #define PREFIX_VEX_38AB (PREFIX_VEX_38AA + 1)
964 #define PREFIX_VEX_38AC (PREFIX_VEX_38AB + 1)
965 #define PREFIX_VEX_38AD (PREFIX_VEX_38AC + 1)
966 #define PREFIX_VEX_38AE (PREFIX_VEX_38AD + 1)
967 #define PREFIX_VEX_38AF (PREFIX_VEX_38AE + 1)
968 #define PREFIX_VEX_38B6 (PREFIX_VEX_38AF + 1)
969 #define PREFIX_VEX_38B7 (PREFIX_VEX_38B6 + 1)
970 #define PREFIX_VEX_38B8 (PREFIX_VEX_38B7 + 1)
971 #define PREFIX_VEX_38B9 (PREFIX_VEX_38B8 + 1)
972 #define PREFIX_VEX_38BA (PREFIX_VEX_38B9 + 1)
973 #define PREFIX_VEX_38BB (PREFIX_VEX_38BA + 1)
974 #define PREFIX_VEX_38BC (PREFIX_VEX_38BB + 1)
975 #define PREFIX_VEX_38BD (PREFIX_VEX_38BC + 1)
976 #define PREFIX_VEX_38BE (PREFIX_VEX_38BD + 1)
977 #define PREFIX_VEX_38BF (PREFIX_VEX_38BE + 1)
978 #define PREFIX_VEX_38DB (PREFIX_VEX_38BF + 1)
979 #define PREFIX_VEX_38DC (PREFIX_VEX_38DB + 1)
980 #define PREFIX_VEX_38DD (PREFIX_VEX_38DC + 1)
981 #define PREFIX_VEX_38DE (PREFIX_VEX_38DD + 1)
982 #define PREFIX_VEX_38DF (PREFIX_VEX_38DE + 1)
983 #define PREFIX_VEX_3A04 (PREFIX_VEX_38DF + 1)
984 #define PREFIX_VEX_3A05 (PREFIX_VEX_3A04 + 1)
985 #define PREFIX_VEX_3A06 (PREFIX_VEX_3A05 + 1)
986 #define PREFIX_VEX_3A08 (PREFIX_VEX_3A06 + 1)
987 #define PREFIX_VEX_3A09 (PREFIX_VEX_3A08 + 1)
988 #define PREFIX_VEX_3A0A (PREFIX_VEX_3A09 + 1)
989 #define PREFIX_VEX_3A0B (PREFIX_VEX_3A0A + 1)
990 #define PREFIX_VEX_3A0C (PREFIX_VEX_3A0B + 1)
991 #define PREFIX_VEX_3A0D (PREFIX_VEX_3A0C + 1)
992 #define PREFIX_VEX_3A0E (PREFIX_VEX_3A0D + 1)
993 #define PREFIX_VEX_3A0F (PREFIX_VEX_3A0E + 1)
994 #define PREFIX_VEX_3A14 (PREFIX_VEX_3A0F + 1)
995 #define PREFIX_VEX_3A15 (PREFIX_VEX_3A14 + 1)
996 #define PREFIX_VEX_3A16 (PREFIX_VEX_3A15 + 1)
997 #define PREFIX_VEX_3A17 (PREFIX_VEX_3A16 + 1)
998 #define PREFIX_VEX_3A18 (PREFIX_VEX_3A17 + 1)
999 #define PREFIX_VEX_3A19 (PREFIX_VEX_3A18 + 1)
1000 #define PREFIX_VEX_3A20 (PREFIX_VEX_3A19 + 1)
1001 #define PREFIX_VEX_3A21 (PREFIX_VEX_3A20 + 1)
1002 #define PREFIX_VEX_3A22 (PREFIX_VEX_3A21 + 1)
1003 #define PREFIX_VEX_3A40 (PREFIX_VEX_3A22 + 1)
1004 #define PREFIX_VEX_3A41 (PREFIX_VEX_3A40 + 1)
1005 #define PREFIX_VEX_3A42 (PREFIX_VEX_3A41 + 1)
1006 #define PREFIX_VEX_3A4A (PREFIX_VEX_3A42 + 1)
1007 #define PREFIX_VEX_3A4B (PREFIX_VEX_3A4A + 1)
1008 #define PREFIX_VEX_3A4C (PREFIX_VEX_3A4B + 1)
1009 #define PREFIX_VEX_3A60 (PREFIX_VEX_3A4C + 1)
1010 #define PREFIX_VEX_3A61 (PREFIX_VEX_3A60 + 1)
1011 #define PREFIX_VEX_3A62 (PREFIX_VEX_3A61 + 1)
1012 #define PREFIX_VEX_3A63 (PREFIX_VEX_3A62 + 1)
1013 #define PREFIX_VEX_3ADF (PREFIX_VEX_3A63 + 1)
1014
1015 #define X86_64_06 0
1016 #define X86_64_07 (X86_64_06 + 1)
1017 #define X86_64_0D (X86_64_07 + 1)
1018 #define X86_64_16 (X86_64_0D + 1)
1019 #define X86_64_17 (X86_64_16 + 1)
1020 #define X86_64_1E (X86_64_17 + 1)
1021 #define X86_64_1F (X86_64_1E + 1)
1022 #define X86_64_27 (X86_64_1F + 1)
1023 #define X86_64_2F (X86_64_27 + 1)
1024 #define X86_64_37 (X86_64_2F + 1)
1025 #define X86_64_3F (X86_64_37 + 1)
1026 #define X86_64_60 (X86_64_3F + 1)
1027 #define X86_64_61 (X86_64_60 + 1)
1028 #define X86_64_62 (X86_64_61 + 1)
1029 #define X86_64_63 (X86_64_62 + 1)
1030 #define X86_64_6D (X86_64_63 + 1)
1031 #define X86_64_6F (X86_64_6D + 1)
1032 #define X86_64_9A (X86_64_6F + 1)
1033 #define X86_64_C4 (X86_64_9A + 1)
1034 #define X86_64_C5 (X86_64_C4 + 1)
1035 #define X86_64_CE (X86_64_C5 + 1)
1036 #define X86_64_D4 (X86_64_CE + 1)
1037 #define X86_64_D5 (X86_64_D4 + 1)
1038 #define X86_64_EA (X86_64_D5 + 1)
1039 #define X86_64_0F01_REG_0 (X86_64_EA + 1)
1040 #define X86_64_0F01_REG_1 (X86_64_0F01_REG_0 + 1)
1041 #define X86_64_0F01_REG_2 (X86_64_0F01_REG_1 + 1)
1042 #define X86_64_0F01_REG_3 (X86_64_0F01_REG_2 + 1)
1043
1044 #define THREE_BYTE_0F24 0
1045 #define THREE_BYTE_0F25 (THREE_BYTE_0F24 + 1)
1046 #define THREE_BYTE_0F38 (THREE_BYTE_0F25 + 1)
1047 #define THREE_BYTE_0F3A (THREE_BYTE_0F38 + 1)
1048 #define THREE_BYTE_0F7A (THREE_BYTE_0F3A + 1)
1049 #define THREE_BYTE_0F7B (THREE_BYTE_0F7A + 1)
1050
1051 #define VEX_0F 0
1052 #define VEX_0F38 (VEX_0F + 1)
1053 #define VEX_0F3A (VEX_0F38 + 1)
1054
1055 #define VEX_LEN_10_P_1 0
1056 #define VEX_LEN_10_P_3 (VEX_LEN_10_P_1 + 1)
1057 #define VEX_LEN_11_P_1 (VEX_LEN_10_P_3 + 1)
1058 #define VEX_LEN_11_P_3 (VEX_LEN_11_P_1 + 1)
1059 #define VEX_LEN_12_P_0_M_0 (VEX_LEN_11_P_3 + 1)
1060 #define VEX_LEN_12_P_0_M_1 (VEX_LEN_12_P_0_M_0 + 1)
1061 #define VEX_LEN_12_P_2 (VEX_LEN_12_P_0_M_1 + 1)
1062 #define VEX_LEN_13_M_0 (VEX_LEN_12_P_2 + 1)
1063 #define VEX_LEN_16_P_0_M_0 (VEX_LEN_13_M_0 + 1)
1064 #define VEX_LEN_16_P_0_M_1 (VEX_LEN_16_P_0_M_0 + 1)
1065 #define VEX_LEN_16_P_2 (VEX_LEN_16_P_0_M_1 + 1)
1066 #define VEX_LEN_17_M_0 (VEX_LEN_16_P_2 + 1)
1067 #define VEX_LEN_2A_P_1 (VEX_LEN_17_M_0 + 1)
1068 #define VEX_LEN_2A_P_3 (VEX_LEN_2A_P_1 + 1)
1069 #define VEX_LEN_2B_M_0 (VEX_LEN_2A_P_3 + 1)
1070 #define VEX_LEN_2C_P_1 (VEX_LEN_2B_M_0 + 1)
1071 #define VEX_LEN_2C_P_3 (VEX_LEN_2C_P_1 + 1)
1072 #define VEX_LEN_2D_P_1 (VEX_LEN_2C_P_3 + 1)
1073 #define VEX_LEN_2D_P_3 (VEX_LEN_2D_P_1 + 1)
1074 #define VEX_LEN_2E_P_0 (VEX_LEN_2D_P_3 + 1)
1075 #define VEX_LEN_2E_P_2 (VEX_LEN_2E_P_0 + 1)
1076 #define VEX_LEN_2F_P_0 (VEX_LEN_2E_P_2 + 1)
1077 #define VEX_LEN_2F_P_2 (VEX_LEN_2F_P_0 + 1)
1078 #define VEX_LEN_51_P_1 (VEX_LEN_2F_P_2 + 1)
1079 #define VEX_LEN_51_P_3 (VEX_LEN_51_P_1 + 1)
1080 #define VEX_LEN_52_P_1 (VEX_LEN_51_P_3 + 1)
1081 #define VEX_LEN_53_P_1 (VEX_LEN_52_P_1 + 1)
1082 #define VEX_LEN_58_P_1 (VEX_LEN_53_P_1 + 1)
1083 #define VEX_LEN_58_P_3 (VEX_LEN_58_P_1 + 1)
1084 #define VEX_LEN_59_P_1 (VEX_LEN_58_P_3 + 1)
1085 #define VEX_LEN_59_P_3 (VEX_LEN_59_P_1 + 1)
1086 #define VEX_LEN_5A_P_1 (VEX_LEN_59_P_3 + 1)
1087 #define VEX_LEN_5A_P_3 (VEX_LEN_5A_P_1 + 1)
1088 #define VEX_LEN_5C_P_1 (VEX_LEN_5A_P_3 + 1)
1089 #define VEX_LEN_5C_P_3 (VEX_LEN_5C_P_1 + 1)
1090 #define VEX_LEN_5D_P_1 (VEX_LEN_5C_P_3 + 1)
1091 #define VEX_LEN_5D_P_3 (VEX_LEN_5D_P_1 + 1)
1092 #define VEX_LEN_5E_P_1 (VEX_LEN_5D_P_3 + 1)
1093 #define VEX_LEN_5E_P_3 (VEX_LEN_5E_P_1 + 1)
1094 #define VEX_LEN_5F_P_1 (VEX_LEN_5E_P_3 + 1)
1095 #define VEX_LEN_5F_P_3 (VEX_LEN_5F_P_1 + 1)
1096 #define VEX_LEN_60_P_2 (VEX_LEN_5F_P_3 + 1)
1097 #define VEX_LEN_61_P_2 (VEX_LEN_60_P_2 + 1)
1098 #define VEX_LEN_62_P_2 (VEX_LEN_61_P_2 + 1)
1099 #define VEX_LEN_63_P_2 (VEX_LEN_62_P_2 + 1)
1100 #define VEX_LEN_64_P_2 (VEX_LEN_63_P_2 + 1)
1101 #define VEX_LEN_65_P_2 (VEX_LEN_64_P_2 + 1)
1102 #define VEX_LEN_66_P_2 (VEX_LEN_65_P_2 + 1)
1103 #define VEX_LEN_67_P_2 (VEX_LEN_66_P_2 + 1)
1104 #define VEX_LEN_68_P_2 (VEX_LEN_67_P_2 + 1)
1105 #define VEX_LEN_69_P_2 (VEX_LEN_68_P_2 + 1)
1106 #define VEX_LEN_6A_P_2 (VEX_LEN_69_P_2 + 1)
1107 #define VEX_LEN_6B_P_2 (VEX_LEN_6A_P_2 + 1)
1108 #define VEX_LEN_6C_P_2 (VEX_LEN_6B_P_2 + 1)
1109 #define VEX_LEN_6D_P_2 (VEX_LEN_6C_P_2 + 1)
1110 #define VEX_LEN_6E_P_2 (VEX_LEN_6D_P_2 + 1)
1111 #define VEX_LEN_70_P_1 (VEX_LEN_6E_P_2 + 1)
1112 #define VEX_LEN_70_P_2 (VEX_LEN_70_P_1 + 1)
1113 #define VEX_LEN_70_P_3 (VEX_LEN_70_P_2 + 1)
1114 #define VEX_LEN_71_R_2_P_2 (VEX_LEN_70_P_3 + 1)
1115 #define VEX_LEN_71_R_4_P_2 (VEX_LEN_71_R_2_P_2 + 1)
1116 #define VEX_LEN_71_R_6_P_2 (VEX_LEN_71_R_4_P_2 + 1)
1117 #define VEX_LEN_72_R_2_P_2 (VEX_LEN_71_R_6_P_2 + 1)
1118 #define VEX_LEN_72_R_4_P_2 (VEX_LEN_72_R_2_P_2 + 1)
1119 #define VEX_LEN_72_R_6_P_2 (VEX_LEN_72_R_4_P_2 + 1)
1120 #define VEX_LEN_73_R_2_P_2 (VEX_LEN_72_R_6_P_2 + 1)
1121 #define VEX_LEN_73_R_3_P_2 (VEX_LEN_73_R_2_P_2 + 1)
1122 #define VEX_LEN_73_R_6_P_2 (VEX_LEN_73_R_3_P_2 + 1)
1123 #define VEX_LEN_73_R_7_P_2 (VEX_LEN_73_R_6_P_2 + 1)
1124 #define VEX_LEN_74_P_2 (VEX_LEN_73_R_7_P_2 + 1)
1125 #define VEX_LEN_75_P_2 (VEX_LEN_74_P_2 + 1)
1126 #define VEX_LEN_76_P_2 (VEX_LEN_75_P_2 + 1)
1127 #define VEX_LEN_7E_P_1 (VEX_LEN_76_P_2 + 1)
1128 #define VEX_LEN_7E_P_2 (VEX_LEN_7E_P_1 + 1)
1129 #define VEX_LEN_AE_R_2_M_0 (VEX_LEN_7E_P_2 + 1)
1130 #define VEX_LEN_AE_R_3_M_0 (VEX_LEN_AE_R_2_M_0 + 1)
1131 #define VEX_LEN_C2_P_1 (VEX_LEN_AE_R_3_M_0 + 1)
1132 #define VEX_LEN_C2_P_3 (VEX_LEN_C2_P_1 + 1)
1133 #define VEX_LEN_C4_P_2 (VEX_LEN_C2_P_3 + 1)
1134 #define VEX_LEN_C5_P_2 (VEX_LEN_C4_P_2 + 1)
1135 #define VEX_LEN_D1_P_2 (VEX_LEN_C5_P_2 + 1)
1136 #define VEX_LEN_D2_P_2 (VEX_LEN_D1_P_2 + 1)
1137 #define VEX_LEN_D3_P_2 (VEX_LEN_D2_P_2 + 1)
1138 #define VEX_LEN_D4_P_2 (VEX_LEN_D3_P_2 + 1)
1139 #define VEX_LEN_D5_P_2 (VEX_LEN_D4_P_2 + 1)
1140 #define VEX_LEN_D6_P_2 (VEX_LEN_D5_P_2 + 1)
1141 #define VEX_LEN_D7_P_2_M_1 (VEX_LEN_D6_P_2 + 1)
1142 #define VEX_LEN_D8_P_2 (VEX_LEN_D7_P_2_M_1 + 1)
1143 #define VEX_LEN_D9_P_2 (VEX_LEN_D8_P_2 + 1)
1144 #define VEX_LEN_DA_P_2 (VEX_LEN_D9_P_2 + 1)
1145 #define VEX_LEN_DB_P_2 (VEX_LEN_DA_P_2 + 1)
1146 #define VEX_LEN_DC_P_2 (VEX_LEN_DB_P_2 + 1)
1147 #define VEX_LEN_DD_P_2 (VEX_LEN_DC_P_2 + 1)
1148 #define VEX_LEN_DE_P_2 (VEX_LEN_DD_P_2 + 1)
1149 #define VEX_LEN_DF_P_2 (VEX_LEN_DE_P_2 + 1)
1150 #define VEX_LEN_E0_P_2 (VEX_LEN_DF_P_2 + 1)
1151 #define VEX_LEN_E1_P_2 (VEX_LEN_E0_P_2 + 1)
1152 #define VEX_LEN_E2_P_2 (VEX_LEN_E1_P_2 + 1)
1153 #define VEX_LEN_E3_P_2 (VEX_LEN_E2_P_2 + 1)
1154 #define VEX_LEN_E4_P_2 (VEX_LEN_E3_P_2 + 1)
1155 #define VEX_LEN_E5_P_2 (VEX_LEN_E4_P_2 + 1)
1156 #define VEX_LEN_E7_P_2_M_0 (VEX_LEN_E5_P_2 + 1)
1157 #define VEX_LEN_E8_P_2 (VEX_LEN_E7_P_2_M_0 + 1)
1158 #define VEX_LEN_E9_P_2 (VEX_LEN_E8_P_2 + 1)
1159 #define VEX_LEN_EA_P_2 (VEX_LEN_E9_P_2 + 1)
1160 #define VEX_LEN_EB_P_2 (VEX_LEN_EA_P_2 + 1)
1161 #define VEX_LEN_EC_P_2 (VEX_LEN_EB_P_2 + 1)
1162 #define VEX_LEN_ED_P_2 (VEX_LEN_EC_P_2 + 1)
1163 #define VEX_LEN_EE_P_2 (VEX_LEN_ED_P_2 + 1)
1164 #define VEX_LEN_EF_P_2 (VEX_LEN_EE_P_2 + 1)
1165 #define VEX_LEN_F1_P_2 (VEX_LEN_EF_P_2 + 1)
1166 #define VEX_LEN_F2_P_2 (VEX_LEN_F1_P_2 + 1)
1167 #define VEX_LEN_F3_P_2 (VEX_LEN_F2_P_2 + 1)
1168 #define VEX_LEN_F4_P_2 (VEX_LEN_F3_P_2 + 1)
1169 #define VEX_LEN_F5_P_2 (VEX_LEN_F4_P_2 + 1)
1170 #define VEX_LEN_F6_P_2 (VEX_LEN_F5_P_2 + 1)
1171 #define VEX_LEN_F7_P_2 (VEX_LEN_F6_P_2 + 1)
1172 #define VEX_LEN_F8_P_2 (VEX_LEN_F7_P_2 + 1)
1173 #define VEX_LEN_F9_P_2 (VEX_LEN_F8_P_2 + 1)
1174 #define VEX_LEN_FA_P_2 (VEX_LEN_F9_P_2 + 1)
1175 #define VEX_LEN_FB_P_2 (VEX_LEN_FA_P_2 + 1)
1176 #define VEX_LEN_FC_P_2 (VEX_LEN_FB_P_2 + 1)
1177 #define VEX_LEN_FD_P_2 (VEX_LEN_FC_P_2 + 1)
1178 #define VEX_LEN_FE_P_2 (VEX_LEN_FD_P_2 + 1)
1179 #define VEX_LEN_3800_P_2 (VEX_LEN_FE_P_2 + 1)
1180 #define VEX_LEN_3801_P_2 (VEX_LEN_3800_P_2 + 1)
1181 #define VEX_LEN_3802_P_2 (VEX_LEN_3801_P_2 + 1)
1182 #define VEX_LEN_3803_P_2 (VEX_LEN_3802_P_2 + 1)
1183 #define VEX_LEN_3804_P_2 (VEX_LEN_3803_P_2 + 1)
1184 #define VEX_LEN_3805_P_2 (VEX_LEN_3804_P_2 + 1)
1185 #define VEX_LEN_3806_P_2 (VEX_LEN_3805_P_2 + 1)
1186 #define VEX_LEN_3807_P_2 (VEX_LEN_3806_P_2 + 1)
1187 #define VEX_LEN_3808_P_2 (VEX_LEN_3807_P_2 + 1)
1188 #define VEX_LEN_3809_P_2 (VEX_LEN_3808_P_2 + 1)
1189 #define VEX_LEN_380A_P_2 (VEX_LEN_3809_P_2 + 1)
1190 #define VEX_LEN_380B_P_2 (VEX_LEN_380A_P_2 + 1)
1191 #define VEX_LEN_3819_P_2_M_0 (VEX_LEN_380B_P_2 + 1)
1192 #define VEX_LEN_381A_P_2_M_0 (VEX_LEN_3819_P_2_M_0 + 1)
1193 #define VEX_LEN_381C_P_2 (VEX_LEN_381A_P_2_M_0 + 1)
1194 #define VEX_LEN_381D_P_2 (VEX_LEN_381C_P_2 + 1)
1195 #define VEX_LEN_381E_P_2 (VEX_LEN_381D_P_2 + 1)
1196 #define VEX_LEN_3820_P_2 (VEX_LEN_381E_P_2 + 1)
1197 #define VEX_LEN_3821_P_2 (VEX_LEN_3820_P_2 + 1)
1198 #define VEX_LEN_3822_P_2 (VEX_LEN_3821_P_2 + 1)
1199 #define VEX_LEN_3823_P_2 (VEX_LEN_3822_P_2 + 1)
1200 #define VEX_LEN_3824_P_2 (VEX_LEN_3823_P_2 + 1)
1201 #define VEX_LEN_3825_P_2 (VEX_LEN_3824_P_2 + 1)
1202 #define VEX_LEN_3828_P_2 (VEX_LEN_3825_P_2 + 1)
1203 #define VEX_LEN_3829_P_2 (VEX_LEN_3828_P_2 + 1)
1204 #define VEX_LEN_382A_P_2_M_0 (VEX_LEN_3829_P_2 + 1)
1205 #define VEX_LEN_382B_P_2 (VEX_LEN_382A_P_2_M_0 + 1)
1206 #define VEX_LEN_3830_P_2 (VEX_LEN_382B_P_2 + 1)
1207 #define VEX_LEN_3831_P_2 (VEX_LEN_3830_P_2 + 1)
1208 #define VEX_LEN_3832_P_2 (VEX_LEN_3831_P_2 + 1)
1209 #define VEX_LEN_3833_P_2 (VEX_LEN_3832_P_2 + 1)
1210 #define VEX_LEN_3834_P_2 (VEX_LEN_3833_P_2 + 1)
1211 #define VEX_LEN_3835_P_2 (VEX_LEN_3834_P_2 + 1)
1212 #define VEX_LEN_3837_P_2 (VEX_LEN_3835_P_2 + 1)
1213 #define VEX_LEN_3838_P_2 (VEX_LEN_3837_P_2 + 1)
1214 #define VEX_LEN_3839_P_2 (VEX_LEN_3838_P_2 + 1)
1215 #define VEX_LEN_383A_P_2 (VEX_LEN_3839_P_2 + 1)
1216 #define VEX_LEN_383B_P_2 (VEX_LEN_383A_P_2 + 1)
1217 #define VEX_LEN_383C_P_2 (VEX_LEN_383B_P_2 + 1)
1218 #define VEX_LEN_383D_P_2 (VEX_LEN_383C_P_2 + 1)
1219 #define VEX_LEN_383E_P_2 (VEX_LEN_383D_P_2 + 1)
1220 #define VEX_LEN_383F_P_2 (VEX_LEN_383E_P_2 + 1)
1221 #define VEX_LEN_3840_P_2 (VEX_LEN_383F_P_2 + 1)
1222 #define VEX_LEN_3841_P_2 (VEX_LEN_3840_P_2 + 1)
1223 #define VEX_LEN_38DB_P_2 (VEX_LEN_3841_P_2 + 1)
1224 #define VEX_LEN_38DC_P_2 (VEX_LEN_38DB_P_2 + 1)
1225 #define VEX_LEN_38DD_P_2 (VEX_LEN_38DC_P_2 + 1)
1226 #define VEX_LEN_38DE_P_2 (VEX_LEN_38DD_P_2 + 1)
1227 #define VEX_LEN_38DF_P_2 (VEX_LEN_38DE_P_2 + 1)
1228 #define VEX_LEN_3A06_P_2 (VEX_LEN_38DF_P_2 + 1)
1229 #define VEX_LEN_3A0A_P_2 (VEX_LEN_3A06_P_2 + 1)
1230 #define VEX_LEN_3A0B_P_2 (VEX_LEN_3A0A_P_2 + 1)
1231 #define VEX_LEN_3A0E_P_2 (VEX_LEN_3A0B_P_2 + 1)
1232 #define VEX_LEN_3A0F_P_2 (VEX_LEN_3A0E_P_2 + 1)
1233 #define VEX_LEN_3A14_P_2 (VEX_LEN_3A0F_P_2 + 1)
1234 #define VEX_LEN_3A15_P_2 (VEX_LEN_3A14_P_2 + 1)
1235 #define VEX_LEN_3A16_P_2 (VEX_LEN_3A15_P_2 + 1)
1236 #define VEX_LEN_3A17_P_2 (VEX_LEN_3A16_P_2 + 1)
1237 #define VEX_LEN_3A18_P_2 (VEX_LEN_3A17_P_2 + 1)
1238 #define VEX_LEN_3A19_P_2 (VEX_LEN_3A18_P_2 + 1)
1239 #define VEX_LEN_3A20_P_2 (VEX_LEN_3A19_P_2 + 1)
1240 #define VEX_LEN_3A21_P_2 (VEX_LEN_3A20_P_2 + 1)
1241 #define VEX_LEN_3A22_P_2 (VEX_LEN_3A21_P_2 + 1)
1242 #define VEX_LEN_3A41_P_2 (VEX_LEN_3A22_P_2 + 1)
1243 #define VEX_LEN_3A42_P_2 (VEX_LEN_3A41_P_2 + 1)
1244 #define VEX_LEN_3A4C_P_2 (VEX_LEN_3A42_P_2 + 1)
1245 #define VEX_LEN_3A60_P_2 (VEX_LEN_3A4C_P_2 + 1)
1246 #define VEX_LEN_3A61_P_2 (VEX_LEN_3A60_P_2 + 1)
1247 #define VEX_LEN_3A62_P_2 (VEX_LEN_3A61_P_2 + 1)
1248 #define VEX_LEN_3A63_P_2 (VEX_LEN_3A62_P_2 + 1)
1249 #define VEX_LEN_3ADF_P_2 (VEX_LEN_3A63_P_2 + 1)
1250
1251 typedef void (*op_rtn) (int bytemode, int sizeflag);
1252
1253 struct dis386 {
1254 const char *name;
1255 struct
1256 {
1257 op_rtn rtn;
1258 int bytemode;
1259 } op[MAX_OPERANDS];
1260 };
1261
1262 /* Upper case letters in the instruction names here are macros.
1263 'A' => print 'b' if no register operands or suffix_always is true
1264 'B' => print 'b' if suffix_always is true
1265 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
1266 size prefix
1267 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
1268 suffix_always is true
1269 'E' => print 'e' if 32-bit form of jcxz
1270 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
1271 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
1272 'H' => print ",pt" or ",pn" branch hint
1273 'I' => honor following macro letter even in Intel mode (implemented only
1274 for some of the macro letters)
1275 'J' => print 'l'
1276 'K' => print 'd' or 'q' if rex prefix is present.
1277 'L' => print 'l' if suffix_always is true
1278 'M' => print 'r' if intel_mnemonic is false.
1279 'N' => print 'n' if instruction has no wait "prefix"
1280 'O' => print 'd' or 'o' (or 'q' in Intel mode)
1281 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
1282 or suffix_always is true. print 'q' if rex prefix is present.
1283 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
1284 is true
1285 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
1286 'S' => print 'w', 'l' or 'q' if suffix_always is true
1287 'T' => print 'q' in 64bit mode and behave as 'P' otherwise
1288 'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
1289 'V' => print 'q' in 64bit mode and behave as 'S' otherwise
1290 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
1291 'X' => print 's', 'd' depending on data16 prefix (for XMM)
1292 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
1293 suffix_always is true.
1294 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
1295 '!' => change condition from true to false or from false to true.
1296 '%' => add 1 upper case letter to the macro.
1297
1298 2 upper case letter macros:
1299 "XY" => print 'x' or 'y' if no register operands or suffix_always
1300 is true.
1301 'XW' => print 's', 'd' depending on the VEX.W bit (for FMA)
1302 'LQ' => print 'l' ('d' in Intel mode) or 'q' for memory operand
1303 or suffix_always is true
1304
1305 Many of the above letters print nothing in Intel mode. See "putop"
1306 for the details.
1307
1308 Braces '{' and '}', and vertical bars '|', indicate alternative
1309 mnemonic strings for AT&T and Intel. */
1310
1311 static const struct dis386 dis386[] = {
1312 /* 00 */
1313 { "addB", { Eb, Gb } },
1314 { "addS", { Ev, Gv } },
1315 { "addB", { Gb, Eb } },
1316 { "addS", { Gv, Ev } },
1317 { "addB", { AL, Ib } },
1318 { "addS", { eAX, Iv } },
1319 { X86_64_TABLE (X86_64_06) },
1320 { X86_64_TABLE (X86_64_07) },
1321 /* 08 */
1322 { "orB", { Eb, Gb } },
1323 { "orS", { Ev, Gv } },
1324 { "orB", { Gb, Eb } },
1325 { "orS", { Gv, Ev } },
1326 { "orB", { AL, Ib } },
1327 { "orS", { eAX, Iv } },
1328 { X86_64_TABLE (X86_64_0D) },
1329 { "(bad)", { XX } }, /* 0x0f extended opcode escape */
1330 /* 10 */
1331 { "adcB", { Eb, Gb } },
1332 { "adcS", { Ev, Gv } },
1333 { "adcB", { Gb, Eb } },
1334 { "adcS", { Gv, Ev } },
1335 { "adcB", { AL, Ib } },
1336 { "adcS", { eAX, Iv } },
1337 { X86_64_TABLE (X86_64_16) },
1338 { X86_64_TABLE (X86_64_17) },
1339 /* 18 */
1340 { "sbbB", { Eb, Gb } },
1341 { "sbbS", { Ev, Gv } },
1342 { "sbbB", { Gb, Eb } },
1343 { "sbbS", { Gv, Ev } },
1344 { "sbbB", { AL, Ib } },
1345 { "sbbS", { eAX, Iv } },
1346 { X86_64_TABLE (X86_64_1E) },
1347 { X86_64_TABLE (X86_64_1F) },
1348 /* 20 */
1349 { "andB", { Eb, Gb } },
1350 { "andS", { Ev, Gv } },
1351 { "andB", { Gb, Eb } },
1352 { "andS", { Gv, Ev } },
1353 { "andB", { AL, Ib } },
1354 { "andS", { eAX, Iv } },
1355 { "(bad)", { XX } }, /* SEG ES prefix */
1356 { X86_64_TABLE (X86_64_27) },
1357 /* 28 */
1358 { "subB", { Eb, Gb } },
1359 { "subS", { Ev, Gv } },
1360 { "subB", { Gb, Eb } },
1361 { "subS", { Gv, Ev } },
1362 { "subB", { AL, Ib } },
1363 { "subS", { eAX, Iv } },
1364 { "(bad)", { XX } }, /* SEG CS prefix */
1365 { X86_64_TABLE (X86_64_2F) },
1366 /* 30 */
1367 { "xorB", { Eb, Gb } },
1368 { "xorS", { Ev, Gv } },
1369 { "xorB", { Gb, Eb } },
1370 { "xorS", { Gv, Ev } },
1371 { "xorB", { AL, Ib } },
1372 { "xorS", { eAX, Iv } },
1373 { "(bad)", { XX } }, /* SEG SS prefix */
1374 { X86_64_TABLE (X86_64_37) },
1375 /* 38 */
1376 { "cmpB", { Eb, Gb } },
1377 { "cmpS", { Ev, Gv } },
1378 { "cmpB", { Gb, Eb } },
1379 { "cmpS", { Gv, Ev } },
1380 { "cmpB", { AL, Ib } },
1381 { "cmpS", { eAX, Iv } },
1382 { "(bad)", { XX } }, /* SEG DS prefix */
1383 { X86_64_TABLE (X86_64_3F) },
1384 /* 40 */
1385 { "inc{S|}", { RMeAX } },
1386 { "inc{S|}", { RMeCX } },
1387 { "inc{S|}", { RMeDX } },
1388 { "inc{S|}", { RMeBX } },
1389 { "inc{S|}", { RMeSP } },
1390 { "inc{S|}", { RMeBP } },
1391 { "inc{S|}", { RMeSI } },
1392 { "inc{S|}", { RMeDI } },
1393 /* 48 */
1394 { "dec{S|}", { RMeAX } },
1395 { "dec{S|}", { RMeCX } },
1396 { "dec{S|}", { RMeDX } },
1397 { "dec{S|}", { RMeBX } },
1398 { "dec{S|}", { RMeSP } },
1399 { "dec{S|}", { RMeBP } },
1400 { "dec{S|}", { RMeSI } },
1401 { "dec{S|}", { RMeDI } },
1402 /* 50 */
1403 { "pushV", { RMrAX } },
1404 { "pushV", { RMrCX } },
1405 { "pushV", { RMrDX } },
1406 { "pushV", { RMrBX } },
1407 { "pushV", { RMrSP } },
1408 { "pushV", { RMrBP } },
1409 { "pushV", { RMrSI } },
1410 { "pushV", { RMrDI } },
1411 /* 58 */
1412 { "popV", { RMrAX } },
1413 { "popV", { RMrCX } },
1414 { "popV", { RMrDX } },
1415 { "popV", { RMrBX } },
1416 { "popV", { RMrSP } },
1417 { "popV", { RMrBP } },
1418 { "popV", { RMrSI } },
1419 { "popV", { RMrDI } },
1420 /* 60 */
1421 { X86_64_TABLE (X86_64_60) },
1422 { X86_64_TABLE (X86_64_61) },
1423 { X86_64_TABLE (X86_64_62) },
1424 { X86_64_TABLE (X86_64_63) },
1425 { "(bad)", { XX } }, /* seg fs */
1426 { "(bad)", { XX } }, /* seg gs */
1427 { "(bad)", { XX } }, /* op size prefix */
1428 { "(bad)", { XX } }, /* adr size prefix */
1429 /* 68 */
1430 { "pushT", { Iq } },
1431 { "imulS", { Gv, Ev, Iv } },
1432 { "pushT", { sIb } },
1433 { "imulS", { Gv, Ev, sIb } },
1434 { "ins{b|}", { Ybr, indirDX } },
1435 { X86_64_TABLE (X86_64_6D) },
1436 { "outs{b|}", { indirDXr, Xb } },
1437 { X86_64_TABLE (X86_64_6F) },
1438 /* 70 */
1439 { "joH", { Jb, XX, cond_jump_flag } },
1440 { "jnoH", { Jb, XX, cond_jump_flag } },
1441 { "jbH", { Jb, XX, cond_jump_flag } },
1442 { "jaeH", { Jb, XX, cond_jump_flag } },
1443 { "jeH", { Jb, XX, cond_jump_flag } },
1444 { "jneH", { Jb, XX, cond_jump_flag } },
1445 { "jbeH", { Jb, XX, cond_jump_flag } },
1446 { "jaH", { Jb, XX, cond_jump_flag } },
1447 /* 78 */
1448 { "jsH", { Jb, XX, cond_jump_flag } },
1449 { "jnsH", { Jb, XX, cond_jump_flag } },
1450 { "jpH", { Jb, XX, cond_jump_flag } },
1451 { "jnpH", { Jb, XX, cond_jump_flag } },
1452 { "jlH", { Jb, XX, cond_jump_flag } },
1453 { "jgeH", { Jb, XX, cond_jump_flag } },
1454 { "jleH", { Jb, XX, cond_jump_flag } },
1455 { "jgH", { Jb, XX, cond_jump_flag } },
1456 /* 80 */
1457 { REG_TABLE (REG_80) },
1458 { REG_TABLE (REG_81) },
1459 { "(bad)", { XX } },
1460 { REG_TABLE (REG_82) },
1461 { "testB", { Eb, Gb } },
1462 { "testS", { Ev, Gv } },
1463 { "xchgB", { Eb, Gb } },
1464 { "xchgS", { Ev, Gv } },
1465 /* 88 */
1466 { "movB", { Eb, Gb } },
1467 { "movS", { Ev, Gv } },
1468 { "movB", { Gb, EbS } },
1469 { "movS", { Gv, EvS } },
1470 { "movD", { Sv, Sw } },
1471 { MOD_TABLE (MOD_8D) },
1472 { "movD", { Sw, Sv } },
1473 { REG_TABLE (REG_8F) },
1474 /* 90 */
1475 { PREFIX_TABLE (PREFIX_90) },
1476 { "xchgS", { RMeCX, eAX } },
1477 { "xchgS", { RMeDX, eAX } },
1478 { "xchgS", { RMeBX, eAX } },
1479 { "xchgS", { RMeSP, eAX } },
1480 { "xchgS", { RMeBP, eAX } },
1481 { "xchgS", { RMeSI, eAX } },
1482 { "xchgS", { RMeDI, eAX } },
1483 /* 98 */
1484 { "cW{t|}R", { XX } },
1485 { "cR{t|}O", { XX } },
1486 { X86_64_TABLE (X86_64_9A) },
1487 { "(bad)", { XX } }, /* fwait */
1488 { "pushfT", { XX } },
1489 { "popfT", { XX } },
1490 { "sahf", { XX } },
1491 { "lahf", { XX } },
1492 /* a0 */
1493 { "movB", { AL, Ob } },
1494 { "movS", { eAX, Ov } },
1495 { "movB", { Ob, AL } },
1496 { "movS", { Ov, eAX } },
1497 { "movs{b|}", { Ybr, Xb } },
1498 { "movs{R|}", { Yvr, Xv } },
1499 { "cmps{b|}", { Xb, Yb } },
1500 { "cmps{R|}", { Xv, Yv } },
1501 /* a8 */
1502 { "testB", { AL, Ib } },
1503 { "testS", { eAX, Iv } },
1504 { "stosB", { Ybr, AL } },
1505 { "stosS", { Yvr, eAX } },
1506 { "lodsB", { ALr, Xb } },
1507 { "lodsS", { eAXr, Xv } },
1508 { "scasB", { AL, Yb } },
1509 { "scasS", { eAX, Yv } },
1510 /* b0 */
1511 { "movB", { RMAL, Ib } },
1512 { "movB", { RMCL, Ib } },
1513 { "movB", { RMDL, Ib } },
1514 { "movB", { RMBL, Ib } },
1515 { "movB", { RMAH, Ib } },
1516 { "movB", { RMCH, Ib } },
1517 { "movB", { RMDH, Ib } },
1518 { "movB", { RMBH, Ib } },
1519 /* b8 */
1520 { "movS", { RMeAX, Iv64 } },
1521 { "movS", { RMeCX, Iv64 } },
1522 { "movS", { RMeDX, Iv64 } },
1523 { "movS", { RMeBX, Iv64 } },
1524 { "movS", { RMeSP, Iv64 } },
1525 { "movS", { RMeBP, Iv64 } },
1526 { "movS", { RMeSI, Iv64 } },
1527 { "movS", { RMeDI, Iv64 } },
1528 /* c0 */
1529 { REG_TABLE (REG_C0) },
1530 { REG_TABLE (REG_C1) },
1531 { "retT", { Iw } },
1532 { "retT", { XX } },
1533 { X86_64_TABLE (X86_64_C4) },
1534 { X86_64_TABLE (X86_64_C5) },
1535 { REG_TABLE (REG_C6) },
1536 { REG_TABLE (REG_C7) },
1537 /* c8 */
1538 { "enterT", { Iw, Ib } },
1539 { "leaveT", { XX } },
1540 { "Jret{|f}P", { Iw } },
1541 { "Jret{|f}P", { XX } },
1542 { "int3", { XX } },
1543 { "int", { Ib } },
1544 { X86_64_TABLE (X86_64_CE) },
1545 { "iretP", { XX } },
1546 /* d0 */
1547 { REG_TABLE (REG_D0) },
1548 { REG_TABLE (REG_D1) },
1549 { REG_TABLE (REG_D2) },
1550 { REG_TABLE (REG_D3) },
1551 { X86_64_TABLE (X86_64_D4) },
1552 { X86_64_TABLE (X86_64_D5) },
1553 { "(bad)", { XX } },
1554 { "xlat", { DSBX } },
1555 /* d8 */
1556 { FLOAT },
1557 { FLOAT },
1558 { FLOAT },
1559 { FLOAT },
1560 { FLOAT },
1561 { FLOAT },
1562 { FLOAT },
1563 { FLOAT },
1564 /* e0 */
1565 { "loopneFH", { Jb, XX, loop_jcxz_flag } },
1566 { "loopeFH", { Jb, XX, loop_jcxz_flag } },
1567 { "loopFH", { Jb, XX, loop_jcxz_flag } },
1568 { "jEcxzH", { Jb, XX, loop_jcxz_flag } },
1569 { "inB", { AL, Ib } },
1570 { "inG", { zAX, Ib } },
1571 { "outB", { Ib, AL } },
1572 { "outG", { Ib, zAX } },
1573 /* e8 */
1574 { "callT", { Jv } },
1575 { "jmpT", { Jv } },
1576 { X86_64_TABLE (X86_64_EA) },
1577 { "jmp", { Jb } },
1578 { "inB", { AL, indirDX } },
1579 { "inG", { zAX, indirDX } },
1580 { "outB", { indirDX, AL } },
1581 { "outG", { indirDX, zAX } },
1582 /* f0 */
1583 { "(bad)", { XX } }, /* lock prefix */
1584 { "icebp", { XX } },
1585 { "(bad)", { XX } }, /* repne */
1586 { "(bad)", { XX } }, /* repz */
1587 { "hlt", { XX } },
1588 { "cmc", { XX } },
1589 { REG_TABLE (REG_F6) },
1590 { REG_TABLE (REG_F7) },
1591 /* f8 */
1592 { "clc", { XX } },
1593 { "stc", { XX } },
1594 { "cli", { XX } },
1595 { "sti", { XX } },
1596 { "cld", { XX } },
1597 { "std", { XX } },
1598 { REG_TABLE (REG_FE) },
1599 { REG_TABLE (REG_FF) },
1600 };
1601
1602 static const struct dis386 dis386_twobyte[] = {
1603 /* 00 */
1604 { REG_TABLE (REG_0F00 ) },
1605 { REG_TABLE (REG_0F01 ) },
1606 { "larS", { Gv, Ew } },
1607 { "lslS", { Gv, Ew } },
1608 { "(bad)", { XX } },
1609 { "syscall", { XX } },
1610 { "clts", { XX } },
1611 { "sysretP", { XX } },
1612 /* 08 */
1613 { "invd", { XX } },
1614 { "wbinvd", { XX } },
1615 { "(bad)", { XX } },
1616 { "ud2a", { XX } },
1617 { "(bad)", { XX } },
1618 { REG_TABLE (REG_0F0D) },
1619 { "femms", { XX } },
1620 { "", { MX, EM, OPSUF } }, /* See OP_3DNowSuffix. */
1621 /* 10 */
1622 { PREFIX_TABLE (PREFIX_0F10) },
1623 { PREFIX_TABLE (PREFIX_0F11) },
1624 { PREFIX_TABLE (PREFIX_0F12) },
1625 { MOD_TABLE (MOD_0F13) },
1626 { "unpcklpX", { XM, EXx } },
1627 { "unpckhpX", { XM, EXx } },
1628 { PREFIX_TABLE (PREFIX_0F16) },
1629 { MOD_TABLE (MOD_0F17) },
1630 /* 18 */
1631 { REG_TABLE (REG_0F18) },
1632 { "nopQ", { Ev } },
1633 { "nopQ", { Ev } },
1634 { "nopQ", { Ev } },
1635 { "nopQ", { Ev } },
1636 { "nopQ", { Ev } },
1637 { "nopQ", { Ev } },
1638 { "nopQ", { Ev } },
1639 /* 20 */
1640 { MOD_TABLE (MOD_0F20) },
1641 { MOD_TABLE (MOD_0F21) },
1642 { MOD_TABLE (MOD_0F22) },
1643 { MOD_TABLE (MOD_0F23) },
1644 { MOD_TABLE (MOD_0F24) },
1645 { THREE_BYTE_TABLE (THREE_BYTE_0F25) },
1646 { MOD_TABLE (MOD_0F26) },
1647 { "(bad)", { XX } },
1648 /* 28 */
1649 { "movapX", { XM, EXx } },
1650 { "movapX", { EXxS, XM } },
1651 { PREFIX_TABLE (PREFIX_0F2A) },
1652 { PREFIX_TABLE (PREFIX_0F2B) },
1653 { PREFIX_TABLE (PREFIX_0F2C) },
1654 { PREFIX_TABLE (PREFIX_0F2D) },
1655 { PREFIX_TABLE (PREFIX_0F2E) },
1656 { PREFIX_TABLE (PREFIX_0F2F) },
1657 /* 30 */
1658 { "wrmsr", { XX } },
1659 { "rdtsc", { XX } },
1660 { "rdmsr", { XX } },
1661 { "rdpmc", { XX } },
1662 { "sysenter", { XX } },
1663 { "sysexit", { XX } },
1664 { "(bad)", { XX } },
1665 { "getsec", { XX } },
1666 /* 38 */
1667 { THREE_BYTE_TABLE (THREE_BYTE_0F38) },
1668 { "(bad)", { XX } },
1669 { THREE_BYTE_TABLE (THREE_BYTE_0F3A) },
1670 { "(bad)", { XX } },
1671 { "(bad)", { XX } },
1672 { "(bad)", { XX } },
1673 { "(bad)", { XX } },
1674 { "(bad)", { XX } },
1675 /* 40 */
1676 { "cmovoS", { Gv, Ev } },
1677 { "cmovnoS", { Gv, Ev } },
1678 { "cmovbS", { Gv, Ev } },
1679 { "cmovaeS", { Gv, Ev } },
1680 { "cmoveS", { Gv, Ev } },
1681 { "cmovneS", { Gv, Ev } },
1682 { "cmovbeS", { Gv, Ev } },
1683 { "cmovaS", { Gv, Ev } },
1684 /* 48 */
1685 { "cmovsS", { Gv, Ev } },
1686 { "cmovnsS", { Gv, Ev } },
1687 { "cmovpS", { Gv, Ev } },
1688 { "cmovnpS", { Gv, Ev } },
1689 { "cmovlS", { Gv, Ev } },
1690 { "cmovgeS", { Gv, Ev } },
1691 { "cmovleS", { Gv, Ev } },
1692 { "cmovgS", { Gv, Ev } },
1693 /* 50 */
1694 { MOD_TABLE (MOD_0F51) },
1695 { PREFIX_TABLE (PREFIX_0F51) },
1696 { PREFIX_TABLE (PREFIX_0F52) },
1697 { PREFIX_TABLE (PREFIX_0F53) },
1698 { "andpX", { XM, EXx } },
1699 { "andnpX", { XM, EXx } },
1700 { "orpX", { XM, EXx } },
1701 { "xorpX", { XM, EXx } },
1702 /* 58 */
1703 { PREFIX_TABLE (PREFIX_0F58) },
1704 { PREFIX_TABLE (PREFIX_0F59) },
1705 { PREFIX_TABLE (PREFIX_0F5A) },
1706 { PREFIX_TABLE (PREFIX_0F5B) },
1707 { PREFIX_TABLE (PREFIX_0F5C) },
1708 { PREFIX_TABLE (PREFIX_0F5D) },
1709 { PREFIX_TABLE (PREFIX_0F5E) },
1710 { PREFIX_TABLE (PREFIX_0F5F) },
1711 /* 60 */
1712 { PREFIX_TABLE (PREFIX_0F60) },
1713 { PREFIX_TABLE (PREFIX_0F61) },
1714 { PREFIX_TABLE (PREFIX_0F62) },
1715 { "packsswb", { MX, EM } },
1716 { "pcmpgtb", { MX, EM } },
1717 { "pcmpgtw", { MX, EM } },
1718 { "pcmpgtd", { MX, EM } },
1719 { "packuswb", { MX, EM } },
1720 /* 68 */
1721 { "punpckhbw", { MX, EM } },
1722 { "punpckhwd", { MX, EM } },
1723 { "punpckhdq", { MX, EM } },
1724 { "packssdw", { MX, EM } },
1725 { PREFIX_TABLE (PREFIX_0F6C) },
1726 { PREFIX_TABLE (PREFIX_0F6D) },
1727 { "movK", { MX, Edq } },
1728 { PREFIX_TABLE (PREFIX_0F6F) },
1729 /* 70 */
1730 { PREFIX_TABLE (PREFIX_0F70) },
1731 { REG_TABLE (REG_0F71) },
1732 { REG_TABLE (REG_0F72) },
1733 { REG_TABLE (REG_0F73) },
1734 { "pcmpeqb", { MX, EM } },
1735 { "pcmpeqw", { MX, EM } },
1736 { "pcmpeqd", { MX, EM } },
1737 { "emms", { XX } },
1738 /* 78 */
1739 { PREFIX_TABLE (PREFIX_0F78) },
1740 { PREFIX_TABLE (PREFIX_0F79) },
1741 { THREE_BYTE_TABLE (THREE_BYTE_0F7A) },
1742 { THREE_BYTE_TABLE (THREE_BYTE_0F7B) },
1743 { PREFIX_TABLE (PREFIX_0F7C) },
1744 { PREFIX_TABLE (PREFIX_0F7D) },
1745 { PREFIX_TABLE (PREFIX_0F7E) },
1746 { PREFIX_TABLE (PREFIX_0F7F) },
1747 /* 80 */
1748 { "joH", { Jv, XX, cond_jump_flag } },
1749 { "jnoH", { Jv, XX, cond_jump_flag } },
1750 { "jbH", { Jv, XX, cond_jump_flag } },
1751 { "jaeH", { Jv, XX, cond_jump_flag } },
1752 { "jeH", { Jv, XX, cond_jump_flag } },
1753 { "jneH", { Jv, XX, cond_jump_flag } },
1754 { "jbeH", { Jv, XX, cond_jump_flag } },
1755 { "jaH", { Jv, XX, cond_jump_flag } },
1756 /* 88 */
1757 { "jsH", { Jv, XX, cond_jump_flag } },
1758 { "jnsH", { Jv, XX, cond_jump_flag } },
1759 { "jpH", { Jv, XX, cond_jump_flag } },
1760 { "jnpH", { Jv, XX, cond_jump_flag } },
1761 { "jlH", { Jv, XX, cond_jump_flag } },
1762 { "jgeH", { Jv, XX, cond_jump_flag } },
1763 { "jleH", { Jv, XX, cond_jump_flag } },
1764 { "jgH", { Jv, XX, cond_jump_flag } },
1765 /* 90 */
1766 { "seto", { Eb } },
1767 { "setno", { Eb } },
1768 { "setb", { Eb } },
1769 { "setae", { Eb } },
1770 { "sete", { Eb } },
1771 { "setne", { Eb } },
1772 { "setbe", { Eb } },
1773 { "seta", { Eb } },
1774 /* 98 */
1775 { "sets", { Eb } },
1776 { "setns", { Eb } },
1777 { "setp", { Eb } },
1778 { "setnp", { Eb } },
1779 { "setl", { Eb } },
1780 { "setge", { Eb } },
1781 { "setle", { Eb } },
1782 { "setg", { Eb } },
1783 /* a0 */
1784 { "pushT", { fs } },
1785 { "popT", { fs } },
1786 { "cpuid", { XX } },
1787 { "btS", { Ev, Gv } },
1788 { "shldS", { Ev, Gv, Ib } },
1789 { "shldS", { Ev, Gv, CL } },
1790 { REG_TABLE (REG_0FA6) },
1791 { REG_TABLE (REG_0FA7) },
1792 /* a8 */
1793 { "pushT", { gs } },
1794 { "popT", { gs } },
1795 { "rsm", { XX } },
1796 { "btsS", { Ev, Gv } },
1797 { "shrdS", { Ev, Gv, Ib } },
1798 { "shrdS", { Ev, Gv, CL } },
1799 { REG_TABLE (REG_0FAE) },
1800 { "imulS", { Gv, Ev } },
1801 /* b0 */
1802 { "cmpxchgB", { Eb, Gb } },
1803 { "cmpxchgS", { Ev, Gv } },
1804 { MOD_TABLE (MOD_0FB2) },
1805 { "btrS", { Ev, Gv } },
1806 { MOD_TABLE (MOD_0FB4) },
1807 { MOD_TABLE (MOD_0FB5) },
1808 { "movz{bR|x}", { Gv, Eb } },
1809 { "movz{wR|x}", { Gv, Ew } }, /* yes, there really is movzww ! */
1810 /* b8 */
1811 { PREFIX_TABLE (PREFIX_0FB8) },
1812 { "ud2b", { XX } },
1813 { REG_TABLE (REG_0FBA) },
1814 { "btcS", { Ev, Gv } },
1815 { "bsfS", { Gv, Ev } },
1816 { PREFIX_TABLE (PREFIX_0FBD) },
1817 { "movs{bR|x}", { Gv, Eb } },
1818 { "movs{wR|x}", { Gv, Ew } }, /* yes, there really is movsww ! */
1819 /* c0 */
1820 { "xaddB", { Eb, Gb } },
1821 { "xaddS", { Ev, Gv } },
1822 { PREFIX_TABLE (PREFIX_0FC2) },
1823 { PREFIX_TABLE (PREFIX_0FC3) },
1824 { "pinsrw", { MX, Edqw, Ib } },
1825 { "pextrw", { Gdq, MS, Ib } },
1826 { "shufpX", { XM, EXx, Ib } },
1827 { REG_TABLE (REG_0FC7) },
1828 /* c8 */
1829 { "bswap", { RMeAX } },
1830 { "bswap", { RMeCX } },
1831 { "bswap", { RMeDX } },
1832 { "bswap", { RMeBX } },
1833 { "bswap", { RMeSP } },
1834 { "bswap", { RMeBP } },
1835 { "bswap", { RMeSI } },
1836 { "bswap", { RMeDI } },
1837 /* d0 */
1838 { PREFIX_TABLE (PREFIX_0FD0) },
1839 { "psrlw", { MX, EM } },
1840 { "psrld", { MX, EM } },
1841 { "psrlq", { MX, EM } },
1842 { "paddq", { MX, EM } },
1843 { "pmullw", { MX, EM } },
1844 { PREFIX_TABLE (PREFIX_0FD6) },
1845 { MOD_TABLE (MOD_0FD7) },
1846 /* d8 */
1847 { "psubusb", { MX, EM } },
1848 { "psubusw", { MX, EM } },
1849 { "pminub", { MX, EM } },
1850 { "pand", { MX, EM } },
1851 { "paddusb", { MX, EM } },
1852 { "paddusw", { MX, EM } },
1853 { "pmaxub", { MX, EM } },
1854 { "pandn", { MX, EM } },
1855 /* e0 */
1856 { "pavgb", { MX, EM } },
1857 { "psraw", { MX, EM } },
1858 { "psrad", { MX, EM } },
1859 { "pavgw", { MX, EM } },
1860 { "pmulhuw", { MX, EM } },
1861 { "pmulhw", { MX, EM } },
1862 { PREFIX_TABLE (PREFIX_0FE6) },
1863 { PREFIX_TABLE (PREFIX_0FE7) },
1864 /* e8 */
1865 { "psubsb", { MX, EM } },
1866 { "psubsw", { MX, EM } },
1867 { "pminsw", { MX, EM } },
1868 { "por", { MX, EM } },
1869 { "paddsb", { MX, EM } },
1870 { "paddsw", { MX, EM } },
1871 { "pmaxsw", { MX, EM } },
1872 { "pxor", { MX, EM } },
1873 /* f0 */
1874 { PREFIX_TABLE (PREFIX_0FF0) },
1875 { "psllw", { MX, EM } },
1876 { "pslld", { MX, EM } },
1877 { "psllq", { MX, EM } },
1878 { "pmuludq", { MX, EM } },
1879 { "pmaddwd", { MX, EM } },
1880 { "psadbw", { MX, EM } },
1881 { PREFIX_TABLE (PREFIX_0FF7) },
1882 /* f8 */
1883 { "psubb", { MX, EM } },
1884 { "psubw", { MX, EM } },
1885 { "psubd", { MX, EM } },
1886 { "psubq", { MX, EM } },
1887 { "paddb", { MX, EM } },
1888 { "paddw", { MX, EM } },
1889 { "paddd", { MX, EM } },
1890 { "(bad)", { XX } },
1891 };
1892
1893 static const unsigned char onebyte_has_modrm[256] = {
1894 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1895 /* ------------------------------- */
1896 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
1897 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
1898 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
1899 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
1900 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
1901 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
1902 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
1903 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
1904 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
1905 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
1906 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
1907 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
1908 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
1909 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
1910 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
1911 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
1912 /* ------------------------------- */
1913 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1914 };
1915
1916 static const unsigned char twobyte_has_modrm[256] = {
1917 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1918 /* ------------------------------- */
1919 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
1920 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
1921 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
1922 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
1923 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
1924 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
1925 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
1926 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
1927 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
1928 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
1929 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
1930 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
1931 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
1932 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
1933 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
1934 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
1935 /* ------------------------------- */
1936 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1937 };
1938
1939 static char obuf[100];
1940 static char *obufp;
1941 static char *mnemonicendp;
1942 static char scratchbuf[100];
1943 static unsigned char *start_codep;
1944 static unsigned char *insn_codep;
1945 static unsigned char *codep;
1946 static const char *lock_prefix;
1947 static const char *data_prefix;
1948 static const char *addr_prefix;
1949 static const char *repz_prefix;
1950 static const char *repnz_prefix;
1951 static disassemble_info *the_info;
1952 static struct
1953 {
1954 int mod;
1955 int reg;
1956 int rm;
1957 }
1958 modrm;
1959 static unsigned char need_modrm;
1960 static struct
1961 {
1962 int register_specifier;
1963 int length;
1964 int prefix;
1965 int w;
1966 }
1967 vex;
1968 static unsigned char need_vex;
1969 static unsigned char need_vex_reg;
1970 static unsigned char vex_w_done;
1971
1972 struct op
1973 {
1974 const char *name;
1975 unsigned int len;
1976 };
1977
1978 /* If we are accessing mod/rm/reg without need_modrm set, then the
1979 values are stale. Hitting this abort likely indicates that you
1980 need to update onebyte_has_modrm or twobyte_has_modrm. */
1981 #define MODRM_CHECK if (!need_modrm) abort ()
1982
1983 static const char **names64;
1984 static const char **names32;
1985 static const char **names16;
1986 static const char **names8;
1987 static const char **names8rex;
1988 static const char **names_seg;
1989 static const char *index64;
1990 static const char *index32;
1991 static const char **index16;
1992
1993 static const char *intel_names64[] = {
1994 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
1995 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
1996 };
1997 static const char *intel_names32[] = {
1998 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
1999 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
2000 };
2001 static const char *intel_names16[] = {
2002 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
2003 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
2004 };
2005 static const char *intel_names8[] = {
2006 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2007 };
2008 static const char *intel_names8rex[] = {
2009 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2010 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2011 };
2012 static const char *intel_names_seg[] = {
2013 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2014 };
2015 static const char *intel_index64 = "riz";
2016 static const char *intel_index32 = "eiz";
2017 static const char *intel_index16[] = {
2018 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2019 };
2020
2021 static const char *att_names64[] = {
2022 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2023 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2024 };
2025 static const char *att_names32[] = {
2026 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2027 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2028 };
2029 static const char *att_names16[] = {
2030 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2031 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2032 };
2033 static const char *att_names8[] = {
2034 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2035 };
2036 static const char *att_names8rex[] = {
2037 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2038 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2039 };
2040 static const char *att_names_seg[] = {
2041 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2042 };
2043 static const char *att_index64 = "%riz";
2044 static const char *att_index32 = "%eiz";
2045 static const char *att_index16[] = {
2046 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2047 };
2048
2049 static const struct dis386 reg_table[][8] = {
2050 /* REG_80 */
2051 {
2052 { "addA", { Eb, Ib } },
2053 { "orA", { Eb, Ib } },
2054 { "adcA", { Eb, Ib } },
2055 { "sbbA", { Eb, Ib } },
2056 { "andA", { Eb, Ib } },
2057 { "subA", { Eb, Ib } },
2058 { "xorA", { Eb, Ib } },
2059 { "cmpA", { Eb, Ib } },
2060 },
2061 /* REG_81 */
2062 {
2063 { "addQ", { Ev, Iv } },
2064 { "orQ", { Ev, Iv } },
2065 { "adcQ", { Ev, Iv } },
2066 { "sbbQ", { Ev, Iv } },
2067 { "andQ", { Ev, Iv } },
2068 { "subQ", { Ev, Iv } },
2069 { "xorQ", { Ev, Iv } },
2070 { "cmpQ", { Ev, Iv } },
2071 },
2072 /* REG_82 */
2073 {
2074 { "addQ", { Ev, sIb } },
2075 { "orQ", { Ev, sIb } },
2076 { "adcQ", { Ev, sIb } },
2077 { "sbbQ", { Ev, sIb } },
2078 { "andQ", { Ev, sIb } },
2079 { "subQ", { Ev, sIb } },
2080 { "xorQ", { Ev, sIb } },
2081 { "cmpQ", { Ev, sIb } },
2082 },
2083 /* REG_8F */
2084 {
2085 { "popU", { stackEv } },
2086 { "(bad)", { XX } },
2087 { "(bad)", { XX } },
2088 { "(bad)", { XX } },
2089 { "(bad)", { XX } },
2090 { "(bad)", { XX } },
2091 { "(bad)", { XX } },
2092 { "(bad)", { XX } },
2093 },
2094 /* REG_C0 */
2095 {
2096 { "rolA", { Eb, Ib } },
2097 { "rorA", { Eb, Ib } },
2098 { "rclA", { Eb, Ib } },
2099 { "rcrA", { Eb, Ib } },
2100 { "shlA", { Eb, Ib } },
2101 { "shrA", { Eb, Ib } },
2102 { "(bad)", { XX } },
2103 { "sarA", { Eb, Ib } },
2104 },
2105 /* REG_C1 */
2106 {
2107 { "rolQ", { Ev, Ib } },
2108 { "rorQ", { Ev, Ib } },
2109 { "rclQ", { Ev, Ib } },
2110 { "rcrQ", { Ev, Ib } },
2111 { "shlQ", { Ev, Ib } },
2112 { "shrQ", { Ev, Ib } },
2113 { "(bad)", { XX } },
2114 { "sarQ", { Ev, Ib } },
2115 },
2116 /* REG_C6 */
2117 {
2118 { "movA", { Eb, Ib } },
2119 { "(bad)", { XX } },
2120 { "(bad)", { XX } },
2121 { "(bad)", { XX } },
2122 { "(bad)", { XX } },
2123 { "(bad)", { XX } },
2124 { "(bad)", { XX } },
2125 { "(bad)", { XX } },
2126 },
2127 /* REG_C7 */
2128 {
2129 { "movQ", { Ev, Iv } },
2130 { "(bad)", { XX } },
2131 { "(bad)", { XX } },
2132 { "(bad)", { XX } },
2133 { "(bad)", { XX } },
2134 { "(bad)", { XX } },
2135 { "(bad)", { XX } },
2136 { "(bad)", { XX } },
2137 },
2138 /* REG_D0 */
2139 {
2140 { "rolA", { Eb, I1 } },
2141 { "rorA", { Eb, I1 } },
2142 { "rclA", { Eb, I1 } },
2143 { "rcrA", { Eb, I1 } },
2144 { "shlA", { Eb, I1 } },
2145 { "shrA", { Eb, I1 } },
2146 { "(bad)", { XX } },
2147 { "sarA", { Eb, I1 } },
2148 },
2149 /* REG_D1 */
2150 {
2151 { "rolQ", { Ev, I1 } },
2152 { "rorQ", { Ev, I1 } },
2153 { "rclQ", { Ev, I1 } },
2154 { "rcrQ", { Ev, I1 } },
2155 { "shlQ", { Ev, I1 } },
2156 { "shrQ", { Ev, I1 } },
2157 { "(bad)", { XX } },
2158 { "sarQ", { Ev, I1 } },
2159 },
2160 /* REG_D2 */
2161 {
2162 { "rolA", { Eb, CL } },
2163 { "rorA", { Eb, CL } },
2164 { "rclA", { Eb, CL } },
2165 { "rcrA", { Eb, CL } },
2166 { "shlA", { Eb, CL } },
2167 { "shrA", { Eb, CL } },
2168 { "(bad)", { XX } },
2169 { "sarA", { Eb, CL } },
2170 },
2171 /* REG_D3 */
2172 {
2173 { "rolQ", { Ev, CL } },
2174 { "rorQ", { Ev, CL } },
2175 { "rclQ", { Ev, CL } },
2176 { "rcrQ", { Ev, CL } },
2177 { "shlQ", { Ev, CL } },
2178 { "shrQ", { Ev, CL } },
2179 { "(bad)", { XX } },
2180 { "sarQ", { Ev, CL } },
2181 },
2182 /* REG_F6 */
2183 {
2184 { "testA", { Eb, Ib } },
2185 { "(bad)", { XX } },
2186 { "notA", { Eb } },
2187 { "negA", { Eb } },
2188 { "mulA", { Eb } }, /* Don't print the implicit %al register, */
2189 { "imulA", { Eb } }, /* to distinguish these opcodes from other */
2190 { "divA", { Eb } }, /* mul/imul opcodes. Do the same for div */
2191 { "idivA", { Eb } }, /* and idiv for consistency. */
2192 },
2193 /* REG_F7 */
2194 {
2195 { "testQ", { Ev, Iv } },
2196 { "(bad)", { XX } },
2197 { "notQ", { Ev } },
2198 { "negQ", { Ev } },
2199 { "mulQ", { Ev } }, /* Don't print the implicit register. */
2200 { "imulQ", { Ev } },
2201 { "divQ", { Ev } },
2202 { "idivQ", { Ev } },
2203 },
2204 /* REG_FE */
2205 {
2206 { "incA", { Eb } },
2207 { "decA", { Eb } },
2208 { "(bad)", { XX } },
2209 { "(bad)", { XX } },
2210 { "(bad)", { XX } },
2211 { "(bad)", { XX } },
2212 { "(bad)", { XX } },
2213 { "(bad)", { XX } },
2214 },
2215 /* REG_FF */
2216 {
2217 { "incQ", { Ev } },
2218 { "decQ", { Ev } },
2219 { "callT", { indirEv } },
2220 { "JcallT", { indirEp } },
2221 { "jmpT", { indirEv } },
2222 { "JjmpT", { indirEp } },
2223 { "pushU", { stackEv } },
2224 { "(bad)", { XX } },
2225 },
2226 /* REG_0F00 */
2227 {
2228 { "sldtD", { Sv } },
2229 { "strD", { Sv } },
2230 { "lldt", { Ew } },
2231 { "ltr", { Ew } },
2232 { "verr", { Ew } },
2233 { "verw", { Ew } },
2234 { "(bad)", { XX } },
2235 { "(bad)", { XX } },
2236 },
2237 /* REG_0F01 */
2238 {
2239 { MOD_TABLE (MOD_0F01_REG_0) },
2240 { MOD_TABLE (MOD_0F01_REG_1) },
2241 { MOD_TABLE (MOD_0F01_REG_2) },
2242 { MOD_TABLE (MOD_0F01_REG_3) },
2243 { "smswD", { Sv } },
2244 { "(bad)", { XX } },
2245 { "lmsw", { Ew } },
2246 { MOD_TABLE (MOD_0F01_REG_7) },
2247 },
2248 /* REG_0F0D */
2249 {
2250 { "prefetch", { Eb } },
2251 { "prefetchw", { Eb } },
2252 { "(bad)", { XX } },
2253 { "(bad)", { XX } },
2254 { "(bad)", { XX } },
2255 { "(bad)", { XX } },
2256 { "(bad)", { XX } },
2257 { "(bad)", { XX } },
2258 },
2259 /* REG_0F18 */
2260 {
2261 { MOD_TABLE (MOD_0F18_REG_0) },
2262 { MOD_TABLE (MOD_0F18_REG_1) },
2263 { MOD_TABLE (MOD_0F18_REG_2) },
2264 { MOD_TABLE (MOD_0F18_REG_3) },
2265 { "(bad)", { XX } },
2266 { "(bad)", { XX } },
2267 { "(bad)", { XX } },
2268 { "(bad)", { XX } },
2269 },
2270 /* REG_0F71 */
2271 {
2272 { "(bad)", { XX } },
2273 { "(bad)", { XX } },
2274 { MOD_TABLE (MOD_0F71_REG_2) },
2275 { "(bad)", { XX } },
2276 { MOD_TABLE (MOD_0F71_REG_4) },
2277 { "(bad)", { XX } },
2278 { MOD_TABLE (MOD_0F71_REG_6) },
2279 { "(bad)", { XX } },
2280 },
2281 /* REG_0F72 */
2282 {
2283 { "(bad)", { XX } },
2284 { "(bad)", { XX } },
2285 { MOD_TABLE (MOD_0F72_REG_2) },
2286 { "(bad)", { XX } },
2287 { MOD_TABLE (MOD_0F72_REG_4) },
2288 { "(bad)", { XX } },
2289 { MOD_TABLE (MOD_0F72_REG_6) },
2290 { "(bad)", { XX } },
2291 },
2292 /* REG_0F73 */
2293 {
2294 { "(bad)", { XX } },
2295 { "(bad)", { XX } },
2296 { MOD_TABLE (MOD_0F73_REG_2) },
2297 { MOD_TABLE (MOD_0F73_REG_3) },
2298 { "(bad)", { XX } },
2299 { "(bad)", { XX } },
2300 { MOD_TABLE (MOD_0F73_REG_6) },
2301 { MOD_TABLE (MOD_0F73_REG_7) },
2302 },
2303 /* REG_0FA6 */
2304 {
2305 { "montmul", { { OP_0f07, 0 } } },
2306 { "xsha1", { { OP_0f07, 0 } } },
2307 { "xsha256", { { OP_0f07, 0 } } },
2308 { "(bad)", { { OP_0f07, 0 } } },
2309 { "(bad)", { { OP_0f07, 0 } } },
2310 { "(bad)", { { OP_0f07, 0 } } },
2311 { "(bad)", { { OP_0f07, 0 } } },
2312 { "(bad)", { { OP_0f07, 0 } } },
2313 },
2314 /* REG_0FA7 */
2315 {
2316 { "xstore-rng", { { OP_0f07, 0 } } },
2317 { "xcrypt-ecb", { { OP_0f07, 0 } } },
2318 { "xcrypt-cbc", { { OP_0f07, 0 } } },
2319 { "xcrypt-ctr", { { OP_0f07, 0 } } },
2320 { "xcrypt-cfb", { { OP_0f07, 0 } } },
2321 { "xcrypt-ofb", { { OP_0f07, 0 } } },
2322 { "(bad)", { { OP_0f07, 0 } } },
2323 { "(bad)", { { OP_0f07, 0 } } },
2324 },
2325 /* REG_0FAE */
2326 {
2327 { MOD_TABLE (MOD_0FAE_REG_0) },
2328 { MOD_TABLE (MOD_0FAE_REG_1) },
2329 { MOD_TABLE (MOD_0FAE_REG_2) },
2330 { MOD_TABLE (MOD_0FAE_REG_3) },
2331 { MOD_TABLE (MOD_0FAE_REG_4) },
2332 { MOD_TABLE (MOD_0FAE_REG_5) },
2333 { MOD_TABLE (MOD_0FAE_REG_6) },
2334 { MOD_TABLE (MOD_0FAE_REG_7) },
2335 },
2336 /* REG_0FBA */
2337 {
2338 { "(bad)", { XX } },
2339 { "(bad)", { XX } },
2340 { "(bad)", { XX } },
2341 { "(bad)", { XX } },
2342 { "btQ", { Ev, Ib } },
2343 { "btsQ", { Ev, Ib } },
2344 { "btrQ", { Ev, Ib } },
2345 { "btcQ", { Ev, Ib } },
2346 },
2347 /* REG_0FC7 */
2348 {
2349 { "(bad)", { XX } },
2350 { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } },
2351 { "(bad)", { XX } },
2352 { "(bad)", { XX } },
2353 { "(bad)", { XX } },
2354 { "(bad)", { XX } },
2355 { MOD_TABLE (MOD_0FC7_REG_6) },
2356 { MOD_TABLE (MOD_0FC7_REG_7) },
2357 },
2358 /* REG_VEX_71 */
2359 {
2360 { "(bad)", { XX } },
2361 { "(bad)", { XX } },
2362 { MOD_TABLE (MOD_VEX_71_REG_2) },
2363 { "(bad)", { XX } },
2364 { MOD_TABLE (MOD_VEX_71_REG_4) },
2365 { "(bad)", { XX } },
2366 { MOD_TABLE (MOD_VEX_71_REG_6) },
2367 { "(bad)", { XX } },
2368 },
2369 /* REG_VEX_72 */
2370 {
2371 { "(bad)", { XX } },
2372 { "(bad)", { XX } },
2373 { MOD_TABLE (MOD_VEX_72_REG_2) },
2374 { "(bad)", { XX } },
2375 { MOD_TABLE (MOD_VEX_72_REG_4) },
2376 { "(bad)", { XX } },
2377 { MOD_TABLE (MOD_VEX_72_REG_6) },
2378 { "(bad)", { XX } },
2379 },
2380 /* REG_VEX_73 */
2381 {
2382 { "(bad)", { XX } },
2383 { "(bad)", { XX } },
2384 { MOD_TABLE (MOD_VEX_73_REG_2) },
2385 { MOD_TABLE (MOD_VEX_73_REG_3) },
2386 { "(bad)", { XX } },
2387 { "(bad)", { XX } },
2388 { MOD_TABLE (MOD_VEX_73_REG_6) },
2389 { MOD_TABLE (MOD_VEX_73_REG_7) },
2390 },
2391 /* REG_VEX_AE */
2392 {
2393 { "(bad)", { XX } },
2394 { "(bad)", { XX } },
2395 { MOD_TABLE (MOD_VEX_AE_REG_2) },
2396 { MOD_TABLE (MOD_VEX_AE_REG_3) },
2397 { "(bad)", { XX } },
2398 { "(bad)", { XX } },
2399 { "(bad)", { XX } },
2400 { "(bad)", { XX } },
2401 },
2402 };
2403
2404 static const struct dis386 prefix_table[][4] = {
2405 /* PREFIX_90 */
2406 {
2407 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
2408 { "pause", { XX } },
2409 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
2410 { "(bad)", { XX } },
2411 },
2412
2413 /* PREFIX_0F10 */
2414 {
2415 { "movups", { XM, EXx } },
2416 { "movss", { XM, EXd } },
2417 { "movupd", { XM, EXx } },
2418 { "movsd", { XM, EXq } },
2419 },
2420
2421 /* PREFIX_0F11 */
2422 {
2423 { "movups", { EXxS, XM } },
2424 { "movss", { EXdS, XM } },
2425 { "movupd", { EXxS, XM } },
2426 { "movsd", { EXqS, XM } },
2427 },
2428
2429 /* PREFIX_0F12 */
2430 {
2431 { MOD_TABLE (MOD_0F12_PREFIX_0) },
2432 { "movsldup", { XM, EXx } },
2433 { "movlpd", { XM, EXq } },
2434 { "movddup", { XM, EXq } },
2435 },
2436
2437 /* PREFIX_0F16 */
2438 {
2439 { MOD_TABLE (MOD_0F16_PREFIX_0) },
2440 { "movshdup", { XM, EXx } },
2441 { "movhpd", { XM, EXq } },
2442 { "(bad)", { XX } },
2443 },
2444
2445 /* PREFIX_0F2A */
2446 {
2447 { "cvtpi2ps", { XM, EMCq } },
2448 { "cvtsi2ss%LQ", { XM, Ev } },
2449 { "cvtpi2pd", { XM, EMCq } },
2450 { "cvtsi2sd%LQ", { XM, Ev } },
2451 },
2452
2453 /* PREFIX_0F2B */
2454 {
2455 { MOD_TABLE (MOD_0F2B_PREFIX_0) },
2456 { MOD_TABLE (MOD_0F2B_PREFIX_1) },
2457 { MOD_TABLE (MOD_0F2B_PREFIX_2) },
2458 { MOD_TABLE (MOD_0F2B_PREFIX_3) },
2459 },
2460
2461 /* PREFIX_0F2C */
2462 {
2463 { "cvttps2pi", { MXC, EXq } },
2464 { "cvttss2siY", { Gv, EXd } },
2465 { "cvttpd2pi", { MXC, EXx } },
2466 { "cvttsd2siY", { Gv, EXq } },
2467 },
2468
2469 /* PREFIX_0F2D */
2470 {
2471 { "cvtps2pi", { MXC, EXq } },
2472 { "cvtss2siY", { Gv, EXd } },
2473 { "cvtpd2pi", { MXC, EXx } },
2474 { "cvtsd2siY", { Gv, EXq } },
2475 },
2476
2477 /* PREFIX_0F2E */
2478 {
2479 { "ucomiss",{ XM, EXd } },
2480 { "(bad)", { XX } },
2481 { "ucomisd",{ XM, EXq } },
2482 { "(bad)", { XX } },
2483 },
2484
2485 /* PREFIX_0F2F */
2486 {
2487 { "comiss", { XM, EXd } },
2488 { "(bad)", { XX } },
2489 { "comisd", { XM, EXq } },
2490 { "(bad)", { XX } },
2491 },
2492
2493 /* PREFIX_0F51 */
2494 {
2495 { "sqrtps", { XM, EXx } },
2496 { "sqrtss", { XM, EXd } },
2497 { "sqrtpd", { XM, EXx } },
2498 { "sqrtsd", { XM, EXq } },
2499 },
2500
2501 /* PREFIX_0F52 */
2502 {
2503 { "rsqrtps",{ XM, EXx } },
2504 { "rsqrtss",{ XM, EXd } },
2505 { "(bad)", { XX } },
2506 { "(bad)", { XX } },
2507 },
2508
2509 /* PREFIX_0F53 */
2510 {
2511 { "rcpps", { XM, EXx } },
2512 { "rcpss", { XM, EXd } },
2513 { "(bad)", { XX } },
2514 { "(bad)", { XX } },
2515 },
2516
2517 /* PREFIX_0F58 */
2518 {
2519 { "addps", { XM, EXx } },
2520 { "addss", { XM, EXd } },
2521 { "addpd", { XM, EXx } },
2522 { "addsd", { XM, EXq } },
2523 },
2524
2525 /* PREFIX_0F59 */
2526 {
2527 { "mulps", { XM, EXx } },
2528 { "mulss", { XM, EXd } },
2529 { "mulpd", { XM, EXx } },
2530 { "mulsd", { XM, EXq } },
2531 },
2532
2533 /* PREFIX_0F5A */
2534 {
2535 { "cvtps2pd", { XM, EXq } },
2536 { "cvtss2sd", { XM, EXd } },
2537 { "cvtpd2ps", { XM, EXx } },
2538 { "cvtsd2ss", { XM, EXq } },
2539 },
2540
2541 /* PREFIX_0F5B */
2542 {
2543 { "cvtdq2ps", { XM, EXx } },
2544 { "cvttps2dq", { XM, EXx } },
2545 { "cvtps2dq", { XM, EXx } },
2546 { "(bad)", { XX } },
2547 },
2548
2549 /* PREFIX_0F5C */
2550 {
2551 { "subps", { XM, EXx } },
2552 { "subss", { XM, EXd } },
2553 { "subpd", { XM, EXx } },
2554 { "subsd", { XM, EXq } },
2555 },
2556
2557 /* PREFIX_0F5D */
2558 {
2559 { "minps", { XM, EXx } },
2560 { "minss", { XM, EXd } },
2561 { "minpd", { XM, EXx } },
2562 { "minsd", { XM, EXq } },
2563 },
2564
2565 /* PREFIX_0F5E */
2566 {
2567 { "divps", { XM, EXx } },
2568 { "divss", { XM, EXd } },
2569 { "divpd", { XM, EXx } },
2570 { "divsd", { XM, EXq } },
2571 },
2572
2573 /* PREFIX_0F5F */
2574 {
2575 { "maxps", { XM, EXx } },
2576 { "maxss", { XM, EXd } },
2577 { "maxpd", { XM, EXx } },
2578 { "maxsd", { XM, EXq } },
2579 },
2580
2581 /* PREFIX_0F60 */
2582 {
2583 { "punpcklbw",{ MX, EMd } },
2584 { "(bad)", { XX } },
2585 { "punpcklbw",{ MX, EMx } },
2586 { "(bad)", { XX } },
2587 },
2588
2589 /* PREFIX_0F61 */
2590 {
2591 { "punpcklwd",{ MX, EMd } },
2592 { "(bad)", { XX } },
2593 { "punpcklwd",{ MX, EMx } },
2594 { "(bad)", { XX } },
2595 },
2596
2597 /* PREFIX_0F62 */
2598 {
2599 { "punpckldq",{ MX, EMd } },
2600 { "(bad)", { XX } },
2601 { "punpckldq",{ MX, EMx } },
2602 { "(bad)", { XX } },
2603 },
2604
2605 /* PREFIX_0F6C */
2606 {
2607 { "(bad)", { XX } },
2608 { "(bad)", { XX } },
2609 { "punpcklqdq", { XM, EXx } },
2610 { "(bad)", { XX } },
2611 },
2612
2613 /* PREFIX_0F6D */
2614 {
2615 { "(bad)", { XX } },
2616 { "(bad)", { XX } },
2617 { "punpckhqdq", { XM, EXx } },
2618 { "(bad)", { XX } },
2619 },
2620
2621 /* PREFIX_0F6F */
2622 {
2623 { "movq", { MX, EM } },
2624 { "movdqu", { XM, EXx } },
2625 { "movdqa", { XM, EXx } },
2626 { "(bad)", { XX } },
2627 },
2628
2629 /* PREFIX_0F70 */
2630 {
2631 { "pshufw", { MX, EM, Ib } },
2632 { "pshufhw",{ XM, EXx, Ib } },
2633 { "pshufd", { XM, EXx, Ib } },
2634 { "pshuflw",{ XM, EXx, Ib } },
2635 },
2636
2637 /* PREFIX_0F73_REG_3 */
2638 {
2639 { "(bad)", { XX } },
2640 { "(bad)", { XX } },
2641 { "psrldq", { XS, Ib } },
2642 { "(bad)", { XX } },
2643 },
2644
2645 /* PREFIX_0F73_REG_7 */
2646 {
2647 { "(bad)", { XX } },
2648 { "(bad)", { XX } },
2649 { "pslldq", { XS, Ib } },
2650 { "(bad)", { XX } },
2651 },
2652
2653 /* PREFIX_0F78 */
2654 {
2655 {"vmread", { Em, Gm } },
2656 {"(bad)", { XX } },
2657 {"extrq", { XS, Ib, Ib } },
2658 {"insertq", { XM, XS, Ib, Ib } },
2659 },
2660
2661 /* PREFIX_0F79 */
2662 {
2663 {"vmwrite", { Gm, Em } },
2664 {"(bad)", { XX } },
2665 {"extrq", { XM, XS } },
2666 {"insertq", { XM, XS } },
2667 },
2668
2669 /* PREFIX_0F7C */
2670 {
2671 { "(bad)", { XX } },
2672 { "(bad)", { XX } },
2673 { "haddpd", { XM, EXx } },
2674 { "haddps", { XM, EXx } },
2675 },
2676
2677 /* PREFIX_0F7D */
2678 {
2679 { "(bad)", { XX } },
2680 { "(bad)", { XX } },
2681 { "hsubpd", { XM, EXx } },
2682 { "hsubps", { XM, EXx } },
2683 },
2684
2685 /* PREFIX_0F7E */
2686 {
2687 { "movK", { Edq, MX } },
2688 { "movq", { XM, EXq } },
2689 { "movK", { Edq, XM } },
2690 { "(bad)", { XX } },
2691 },
2692
2693 /* PREFIX_0F7F */
2694 {
2695 { "movq", { EMS, MX } },
2696 { "movdqu", { EXxS, XM } },
2697 { "movdqa", { EXxS, XM } },
2698 { "(bad)", { XX } },
2699 },
2700
2701 /* PREFIX_0FB8 */
2702 {
2703 { "(bad)", { XX } },
2704 { "popcntS", { Gv, Ev } },
2705 { "(bad)", { XX } },
2706 { "(bad)", { XX } },
2707 },
2708
2709 /* PREFIX_0FBD */
2710 {
2711 { "bsrS", { Gv, Ev } },
2712 { "lzcntS", { Gv, Ev } },
2713 { "bsrS", { Gv, Ev } },
2714 { "(bad)", { XX } },
2715 },
2716
2717 /* PREFIX_0FC2 */
2718 {
2719 { "cmpps", { XM, EXx, CMP } },
2720 { "cmpss", { XM, EXd, CMP } },
2721 { "cmppd", { XM, EXx, CMP } },
2722 { "cmpsd", { XM, EXq, CMP } },
2723 },
2724
2725 /* PREFIX_0FC3 */
2726 {
2727 { "movntiS", { Ma, Gv } },
2728 { "(bad)", { XX } },
2729 { "(bad)", { XX } },
2730 { "(bad)", { XX } },
2731 },
2732
2733 /* PREFIX_0FC7_REG_6 */
2734 {
2735 { "vmptrld",{ Mq } },
2736 { "vmxon", { Mq } },
2737 { "vmclear",{ Mq } },
2738 { "(bad)", { XX } },
2739 },
2740
2741 /* PREFIX_0FD0 */
2742 {
2743 { "(bad)", { XX } },
2744 { "(bad)", { XX } },
2745 { "addsubpd", { XM, EXx } },
2746 { "addsubps", { XM, EXx } },
2747 },
2748
2749 /* PREFIX_0FD6 */
2750 {
2751 { "(bad)", { XX } },
2752 { "movq2dq",{ XM, MS } },
2753 { "movq", { EXqS, XM } },
2754 { "movdq2q",{ MX, XS } },
2755 },
2756
2757 /* PREFIX_0FE6 */
2758 {
2759 { "(bad)", { XX } },
2760 { "cvtdq2pd", { XM, EXq } },
2761 { "cvttpd2dq", { XM, EXx } },
2762 { "cvtpd2dq", { XM, EXx } },
2763 },
2764
2765 /* PREFIX_0FE7 */
2766 {
2767 { "movntq", { Mq, MX } },
2768 { "(bad)", { XX } },
2769 { MOD_TABLE (MOD_0FE7_PREFIX_2) },
2770 { "(bad)", { XX } },
2771 },
2772
2773 /* PREFIX_0FF0 */
2774 {
2775 { "(bad)", { XX } },
2776 { "(bad)", { XX } },
2777 { "(bad)", { XX } },
2778 { MOD_TABLE (MOD_0FF0_PREFIX_3) },
2779 },
2780
2781 /* PREFIX_0FF7 */
2782 {
2783 { "maskmovq", { MX, MS } },
2784 { "(bad)", { XX } },
2785 { "maskmovdqu", { XM, XS } },
2786 { "(bad)", { XX } },
2787 },
2788
2789 /* PREFIX_0F3810 */
2790 {
2791 { "(bad)", { XX } },
2792 { "(bad)", { XX } },
2793 { "pblendvb", { XM, EXx, XMM0 } },
2794 { "(bad)", { XX } },
2795 },
2796
2797 /* PREFIX_0F3814 */
2798 {
2799 { "(bad)", { XX } },
2800 { "(bad)", { XX } },
2801 { "blendvps", { XM, EXx, XMM0 } },
2802 { "(bad)", { XX } },
2803 },
2804
2805 /* PREFIX_0F3815 */
2806 {
2807 { "(bad)", { XX } },
2808 { "(bad)", { XX } },
2809 { "blendvpd", { XM, EXx, XMM0 } },
2810 { "(bad)", { XX } },
2811 },
2812
2813 /* PREFIX_0F3817 */
2814 {
2815 { "(bad)", { XX } },
2816 { "(bad)", { XX } },
2817 { "ptest", { XM, EXx } },
2818 { "(bad)", { XX } },
2819 },
2820
2821 /* PREFIX_0F3820 */
2822 {
2823 { "(bad)", { XX } },
2824 { "(bad)", { XX } },
2825 { "pmovsxbw", { XM, EXq } },
2826 { "(bad)", { XX } },
2827 },
2828
2829 /* PREFIX_0F3821 */
2830 {
2831 { "(bad)", { XX } },
2832 { "(bad)", { XX } },
2833 { "pmovsxbd", { XM, EXd } },
2834 { "(bad)", { XX } },
2835 },
2836
2837 /* PREFIX_0F3822 */
2838 {
2839 { "(bad)", { XX } },
2840 { "(bad)", { XX } },
2841 { "pmovsxbq", { XM, EXw } },
2842 { "(bad)", { XX } },
2843 },
2844
2845 /* PREFIX_0F3823 */
2846 {
2847 { "(bad)", { XX } },
2848 { "(bad)", { XX } },
2849 { "pmovsxwd", { XM, EXq } },
2850 { "(bad)", { XX } },
2851 },
2852
2853 /* PREFIX_0F3824 */
2854 {
2855 { "(bad)", { XX } },
2856 { "(bad)", { XX } },
2857 { "pmovsxwq", { XM, EXd } },
2858 { "(bad)", { XX } },
2859 },
2860
2861 /* PREFIX_0F3825 */
2862 {
2863 { "(bad)", { XX } },
2864 { "(bad)", { XX } },
2865 { "pmovsxdq", { XM, EXq } },
2866 { "(bad)", { XX } },
2867 },
2868
2869 /* PREFIX_0F3828 */
2870 {
2871 { "(bad)", { XX } },
2872 { "(bad)", { XX } },
2873 { "pmuldq", { XM, EXx } },
2874 { "(bad)", { XX } },
2875 },
2876
2877 /* PREFIX_0F3829 */
2878 {
2879 { "(bad)", { XX } },
2880 { "(bad)", { XX } },
2881 { "pcmpeqq", { XM, EXx } },
2882 { "(bad)", { XX } },
2883 },
2884
2885 /* PREFIX_0F382A */
2886 {
2887 { "(bad)", { XX } },
2888 { "(bad)", { XX } },
2889 { MOD_TABLE (MOD_0F382A_PREFIX_2) },
2890 { "(bad)", { XX } },
2891 },
2892
2893 /* PREFIX_0F382B */
2894 {
2895 { "(bad)", { XX } },
2896 { "(bad)", { XX } },
2897 { "packusdw", { XM, EXx } },
2898 { "(bad)", { XX } },
2899 },
2900
2901 /* PREFIX_0F3830 */
2902 {
2903 { "(bad)", { XX } },
2904 { "(bad)", { XX } },
2905 { "pmovzxbw", { XM, EXq } },
2906 { "(bad)", { XX } },
2907 },
2908
2909 /* PREFIX_0F3831 */
2910 {
2911 { "(bad)", { XX } },
2912 { "(bad)", { XX } },
2913 { "pmovzxbd", { XM, EXd } },
2914 { "(bad)", { XX } },
2915 },
2916
2917 /* PREFIX_0F3832 */
2918 {
2919 { "(bad)", { XX } },
2920 { "(bad)", { XX } },
2921 { "pmovzxbq", { XM, EXw } },
2922 { "(bad)", { XX } },
2923 },
2924
2925 /* PREFIX_0F3833 */
2926 {
2927 { "(bad)", { XX } },
2928 { "(bad)", { XX } },
2929 { "pmovzxwd", { XM, EXq } },
2930 { "(bad)", { XX } },
2931 },
2932
2933 /* PREFIX_0F3834 */
2934 {
2935 { "(bad)", { XX } },
2936 { "(bad)", { XX } },
2937 { "pmovzxwq", { XM, EXd } },
2938 { "(bad)", { XX } },
2939 },
2940
2941 /* PREFIX_0F3835 */
2942 {
2943 { "(bad)", { XX } },
2944 { "(bad)", { XX } },
2945 { "pmovzxdq", { XM, EXq } },
2946 { "(bad)", { XX } },
2947 },
2948
2949 /* PREFIX_0F3837 */
2950 {
2951 { "(bad)", { XX } },
2952 { "(bad)", { XX } },
2953 { "pcmpgtq", { XM, EXx } },
2954 { "(bad)", { XX } },
2955 },
2956
2957 /* PREFIX_0F3838 */
2958 {
2959 { "(bad)", { XX } },
2960 { "(bad)", { XX } },
2961 { "pminsb", { XM, EXx } },
2962 { "(bad)", { XX } },
2963 },
2964
2965 /* PREFIX_0F3839 */
2966 {
2967 { "(bad)", { XX } },
2968 { "(bad)", { XX } },
2969 { "pminsd", { XM, EXx } },
2970 { "(bad)", { XX } },
2971 },
2972
2973 /* PREFIX_0F383A */
2974 {
2975 { "(bad)", { XX } },
2976 { "(bad)", { XX } },
2977 { "pminuw", { XM, EXx } },
2978 { "(bad)", { XX } },
2979 },
2980
2981 /* PREFIX_0F383B */
2982 {
2983 { "(bad)", { XX } },
2984 { "(bad)", { XX } },
2985 { "pminud", { XM, EXx } },
2986 { "(bad)", { XX } },
2987 },
2988
2989 /* PREFIX_0F383C */
2990 {
2991 { "(bad)", { XX } },
2992 { "(bad)", { XX } },
2993 { "pmaxsb", { XM, EXx } },
2994 { "(bad)", { XX } },
2995 },
2996
2997 /* PREFIX_0F383D */
2998 {
2999 { "(bad)", { XX } },
3000 { "(bad)", { XX } },
3001 { "pmaxsd", { XM, EXx } },
3002 { "(bad)", { XX } },
3003 },
3004
3005 /* PREFIX_0F383E */
3006 {
3007 { "(bad)", { XX } },
3008 { "(bad)", { XX } },
3009 { "pmaxuw", { XM, EXx } },
3010 { "(bad)", { XX } },
3011 },
3012
3013 /* PREFIX_0F383F */
3014 {
3015 { "(bad)", { XX } },
3016 { "(bad)", { XX } },
3017 { "pmaxud", { XM, EXx } },
3018 { "(bad)", { XX } },
3019 },
3020
3021 /* PREFIX_0F3840 */
3022 {
3023 { "(bad)", { XX } },
3024 { "(bad)", { XX } },
3025 { "pmulld", { XM, EXx } },
3026 { "(bad)", { XX } },
3027 },
3028
3029 /* PREFIX_0F3841 */
3030 {
3031 { "(bad)", { XX } },
3032 { "(bad)", { XX } },
3033 { "phminposuw", { XM, EXx } },
3034 { "(bad)", { XX } },
3035 },
3036
3037 /* PREFIX_0F3880 */
3038 {
3039 { "(bad)", { XX } },
3040 { "(bad)", { XX } },
3041 { "invept", { Gm, Mo } },
3042 { "(bad)", { XX } },
3043 },
3044
3045 /* PREFIX_0F3881 */
3046 {
3047 { "(bad)", { XX } },
3048 { "(bad)", { XX } },
3049 { "invvpid", { Gm, Mo } },
3050 { "(bad)", { XX } },
3051 },
3052
3053 /* PREFIX_0F38DB */
3054 {
3055 { "(bad)", { XX } },
3056 { "(bad)", { XX } },
3057 { "aesimc", { XM, EXx } },
3058 { "(bad)", { XX } },
3059 },
3060
3061 /* PREFIX_0F38DC */
3062 {
3063 { "(bad)", { XX } },
3064 { "(bad)", { XX } },
3065 { "aesenc", { XM, EXx } },
3066 { "(bad)", { XX } },
3067 },
3068
3069 /* PREFIX_0F38DD */
3070 {
3071 { "(bad)", { XX } },
3072 { "(bad)", { XX } },
3073 { "aesenclast", { XM, EXx } },
3074 { "(bad)", { XX } },
3075 },
3076
3077 /* PREFIX_0F38DE */
3078 {
3079 { "(bad)", { XX } },
3080 { "(bad)", { XX } },
3081 { "aesdec", { XM, EXx } },
3082 { "(bad)", { XX } },
3083 },
3084
3085 /* PREFIX_0F38DF */
3086 {
3087 { "(bad)", { XX } },
3088 { "(bad)", { XX } },
3089 { "aesdeclast", { XM, EXx } },
3090 { "(bad)", { XX } },
3091 },
3092
3093 /* PREFIX_0F38F0 */
3094 {
3095 { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
3096 { "(bad)", { XX } },
3097 { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
3098 { "crc32", { Gdq, { CRC32_Fixup, b_mode } } },
3099 },
3100
3101 /* PREFIX_0F38F1 */
3102 {
3103 { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
3104 { "(bad)", { XX } },
3105 { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
3106 { "crc32", { Gdq, { CRC32_Fixup, v_mode } } },
3107 },
3108
3109 /* PREFIX_0F3A08 */
3110 {
3111 { "(bad)", { XX } },
3112 { "(bad)", { XX } },
3113 { "roundps", { XM, EXx, Ib } },
3114 { "(bad)", { XX } },
3115 },
3116
3117 /* PREFIX_0F3A09 */
3118 {
3119 { "(bad)", { XX } },
3120 { "(bad)", { XX } },
3121 { "roundpd", { XM, EXx, Ib } },
3122 { "(bad)", { XX } },
3123 },
3124
3125 /* PREFIX_0F3A0A */
3126 {
3127 { "(bad)", { XX } },
3128 { "(bad)", { XX } },
3129 { "roundss", { XM, EXd, Ib } },
3130 { "(bad)", { XX } },
3131 },
3132
3133 /* PREFIX_0F3A0B */
3134 {
3135 { "(bad)", { XX } },
3136 { "(bad)", { XX } },
3137 { "roundsd", { XM, EXq, Ib } },
3138 { "(bad)", { XX } },
3139 },
3140
3141 /* PREFIX_0F3A0C */
3142 {
3143 { "(bad)", { XX } },
3144 { "(bad)", { XX } },
3145 { "blendps", { XM, EXx, Ib } },
3146 { "(bad)", { XX } },
3147 },
3148
3149 /* PREFIX_0F3A0D */
3150 {
3151 { "(bad)", { XX } },
3152 { "(bad)", { XX } },
3153 { "blendpd", { XM, EXx, Ib } },
3154 { "(bad)", { XX } },
3155 },
3156
3157 /* PREFIX_0F3A0E */
3158 {
3159 { "(bad)", { XX } },
3160 { "(bad)", { XX } },
3161 { "pblendw", { XM, EXx, Ib } },
3162 { "(bad)", { XX } },
3163 },
3164
3165 /* PREFIX_0F3A14 */
3166 {
3167 { "(bad)", { XX } },
3168 { "(bad)", { XX } },
3169 { "pextrb", { Edqb, XM, Ib } },
3170 { "(bad)", { XX } },
3171 },
3172
3173 /* PREFIX_0F3A15 */
3174 {
3175 { "(bad)", { XX } },
3176 { "(bad)", { XX } },
3177 { "pextrw", { Edqw, XM, Ib } },
3178 { "(bad)", { XX } },
3179 },
3180
3181 /* PREFIX_0F3A16 */
3182 {
3183 { "(bad)", { XX } },
3184 { "(bad)", { XX } },
3185 { "pextrK", { Edq, XM, Ib } },
3186 { "(bad)", { XX } },
3187 },
3188
3189 /* PREFIX_0F3A17 */
3190 {
3191 { "(bad)", { XX } },
3192 { "(bad)", { XX } },
3193 { "extractps", { Edqd, XM, Ib } },
3194 { "(bad)", { XX } },
3195 },
3196
3197 /* PREFIX_0F3A20 */
3198 {
3199 { "(bad)", { XX } },
3200 { "(bad)", { XX } },
3201 { "pinsrb", { XM, Edqb, Ib } },
3202 { "(bad)", { XX } },
3203 },
3204
3205 /* PREFIX_0F3A21 */
3206 {
3207 { "(bad)", { XX } },
3208 { "(bad)", { XX } },
3209 { "insertps", { XM, EXd, Ib } },
3210 { "(bad)", { XX } },
3211 },
3212
3213 /* PREFIX_0F3A22 */
3214 {
3215 { "(bad)", { XX } },
3216 { "(bad)", { XX } },
3217 { "pinsrK", { XM, Edq, Ib } },
3218 { "(bad)", { XX } },
3219 },
3220
3221 /* PREFIX_0F3A40 */
3222 {
3223 { "(bad)", { XX } },
3224 { "(bad)", { XX } },
3225 { "dpps", { XM, EXx, Ib } },
3226 { "(bad)", { XX } },
3227 },
3228
3229 /* PREFIX_0F3A41 */
3230 {
3231 { "(bad)", { XX } },
3232 { "(bad)", { XX } },
3233 { "dppd", { XM, EXx, Ib } },
3234 { "(bad)", { XX } },
3235 },
3236
3237 /* PREFIX_0F3A42 */
3238 {
3239 { "(bad)", { XX } },
3240 { "(bad)", { XX } },
3241 { "mpsadbw", { XM, EXx, Ib } },
3242 { "(bad)", { XX } },
3243 },
3244
3245 /* PREFIX_0F3A44 */
3246 {
3247 { "(bad)", { XX } },
3248 { "(bad)", { XX } },
3249 { "pclmulqdq", { XM, EXx, PCLMUL } },
3250 { "(bad)", { XX } },
3251 },
3252
3253 /* PREFIX_0F3A60 */
3254 {
3255 { "(bad)", { XX } },
3256 { "(bad)", { XX } },
3257 { "pcmpestrm", { XM, EXx, Ib } },
3258 { "(bad)", { XX } },
3259 },
3260
3261 /* PREFIX_0F3A61 */
3262 {
3263 { "(bad)", { XX } },
3264 { "(bad)", { XX } },
3265 { "pcmpestri", { XM, EXx, Ib } },
3266 { "(bad)", { XX } },
3267 },
3268
3269 /* PREFIX_0F3A62 */
3270 {
3271 { "(bad)", { XX } },
3272 { "(bad)", { XX } },
3273 { "pcmpistrm", { XM, EXx, Ib } },
3274 { "(bad)", { XX } },
3275 },
3276
3277 /* PREFIX_0F3A63 */
3278 {
3279 { "(bad)", { XX } },
3280 { "(bad)", { XX } },
3281 { "pcmpistri", { XM, EXx, Ib } },
3282 { "(bad)", { XX } },
3283 },
3284
3285 /* PREFIX_0F3ADF */
3286 {
3287 { "(bad)", { XX } },
3288 { "(bad)", { XX } },
3289 { "aeskeygenassist", { XM, EXx, Ib } },
3290 { "(bad)", { XX } },
3291 },
3292
3293 /* PREFIX_VEX_10 */
3294 {
3295 { "vmovups", { XM, EXx } },
3296 { VEX_LEN_TABLE (VEX_LEN_10_P_1) },
3297 { "vmovupd", { XM, EXx } },
3298 { VEX_LEN_TABLE (VEX_LEN_10_P_3) },
3299 },
3300
3301 /* PREFIX_VEX_11 */
3302 {
3303 { "vmovups", { EXxS, XM } },
3304 { VEX_LEN_TABLE (VEX_LEN_11_P_1) },
3305 { "vmovupd", { EXxS, XM } },
3306 { VEX_LEN_TABLE (VEX_LEN_11_P_3) },
3307 },
3308
3309 /* PREFIX_VEX_12 */
3310 {
3311 { MOD_TABLE (MOD_VEX_12_PREFIX_0) },
3312 { "vmovsldup", { XM, EXx } },
3313 { VEX_LEN_TABLE (VEX_LEN_12_P_2) },
3314 { "vmovddup", { XM, EXymmq } },
3315 },
3316
3317 /* PREFIX_VEX_16 */
3318 {
3319 { MOD_TABLE (MOD_VEX_16_PREFIX_0) },
3320 { "vmovshdup", { XM, EXx } },
3321 { VEX_LEN_TABLE (VEX_LEN_16_P_2) },
3322 { "(bad)", { XX } },
3323 },
3324
3325 /* PREFIX_VEX_2A */
3326 {
3327 { "(bad)", { XX } },
3328 { VEX_LEN_TABLE (VEX_LEN_2A_P_1) },
3329 { "(bad)", { XX } },
3330 { VEX_LEN_TABLE (VEX_LEN_2A_P_3) },
3331 },
3332
3333 /* PREFIX_VEX_2C */
3334 {
3335 { "(bad)", { XX } },
3336 { VEX_LEN_TABLE (VEX_LEN_2C_P_1) },
3337 { "(bad)", { XX } },
3338 { VEX_LEN_TABLE (VEX_LEN_2C_P_3) },
3339 },
3340
3341 /* PREFIX_VEX_2D */
3342 {
3343 { "(bad)", { XX } },
3344 { VEX_LEN_TABLE (VEX_LEN_2D_P_1) },
3345 { "(bad)", { XX } },
3346 { VEX_LEN_TABLE (VEX_LEN_2D_P_3) },
3347 },
3348
3349 /* PREFIX_VEX_2E */
3350 {
3351 { VEX_LEN_TABLE (VEX_LEN_2E_P_0) },
3352 { "(bad)", { XX } },
3353 { VEX_LEN_TABLE (VEX_LEN_2E_P_2) },
3354 { "(bad)", { XX } },
3355 },
3356
3357 /* PREFIX_VEX_2F */
3358 {
3359 { VEX_LEN_TABLE (VEX_LEN_2F_P_0) },
3360 { "(bad)", { XX } },
3361 { VEX_LEN_TABLE (VEX_LEN_2F_P_2) },
3362 { "(bad)", { XX } },
3363 },
3364
3365 /* PREFIX_VEX_51 */
3366 {
3367 { "vsqrtps", { XM, EXx } },
3368 { VEX_LEN_TABLE (VEX_LEN_51_P_1) },
3369 { "vsqrtpd", { XM, EXx } },
3370 { VEX_LEN_TABLE (VEX_LEN_51_P_3) },
3371 },
3372
3373 /* PREFIX_VEX_52 */
3374 {
3375 { "vrsqrtps", { XM, EXx } },
3376 { VEX_LEN_TABLE (VEX_LEN_52_P_1) },
3377 { "(bad)", { XX } },
3378 { "(bad)", { XX } },
3379 },
3380
3381 /* PREFIX_VEX_53 */
3382 {
3383 { "vrcpps", { XM, EXx } },
3384 { VEX_LEN_TABLE (VEX_LEN_53_P_1) },
3385 { "(bad)", { XX } },
3386 { "(bad)", { XX } },
3387 },
3388
3389 /* PREFIX_VEX_58 */
3390 {
3391 { "vaddps", { XM, Vex, EXx } },
3392 { VEX_LEN_TABLE (VEX_LEN_58_P_1) },
3393 { "vaddpd", { XM, Vex, EXx } },
3394 { VEX_LEN_TABLE (VEX_LEN_58_P_3) },
3395 },
3396
3397 /* PREFIX_VEX_59 */
3398 {
3399 { "vmulps", { XM, Vex, EXx } },
3400 { VEX_LEN_TABLE (VEX_LEN_59_P_1) },
3401 { "vmulpd", { XM, Vex, EXx } },
3402 { VEX_LEN_TABLE (VEX_LEN_59_P_3) },
3403 },
3404
3405 /* PREFIX_VEX_5A */
3406 {
3407 { "vcvtps2pd", { XM, EXxmmq } },
3408 { VEX_LEN_TABLE (VEX_LEN_5A_P_1) },
3409 { "vcvtpd2ps%XY", { XMM, EXx } },
3410 { VEX_LEN_TABLE (VEX_LEN_5A_P_3) },
3411 },
3412
3413 /* PREFIX_VEX_5B */
3414 {
3415 { "vcvtdq2ps", { XM, EXx } },
3416 { "vcvttps2dq", { XM, EXx } },
3417 { "vcvtps2dq", { XM, EXx } },
3418 { "(bad)", { XX } },
3419 },
3420
3421 /* PREFIX_VEX_5C */
3422 {
3423 { "vsubps", { XM, Vex, EXx } },
3424 { VEX_LEN_TABLE (VEX_LEN_5C_P_1) },
3425 { "vsubpd", { XM, Vex, EXx } },
3426 { VEX_LEN_TABLE (VEX_LEN_5C_P_3) },
3427 },
3428
3429 /* PREFIX_VEX_5D */
3430 {
3431 { "vminps", { XM, Vex, EXx } },
3432 { VEX_LEN_TABLE (VEX_LEN_5D_P_1) },
3433 { "vminpd", { XM, Vex, EXx } },
3434 { VEX_LEN_TABLE (VEX_LEN_5D_P_3) },
3435 },
3436
3437 /* PREFIX_VEX_5E */
3438 {
3439 { "vdivps", { XM, Vex, EXx } },
3440 { VEX_LEN_TABLE (VEX_LEN_5E_P_1) },
3441 { "vdivpd", { XM, Vex, EXx } },
3442 { VEX_LEN_TABLE (VEX_LEN_5E_P_3) },
3443 },
3444
3445 /* PREFIX_VEX_5F */
3446 {
3447 { "vmaxps", { XM, Vex, EXx } },
3448 { VEX_LEN_TABLE (VEX_LEN_5F_P_1) },
3449 { "vmaxpd", { XM, Vex, EXx } },
3450 { VEX_LEN_TABLE (VEX_LEN_5F_P_3) },
3451 },
3452
3453 /* PREFIX_VEX_60 */
3454 {
3455 { "(bad)", { XX } },
3456 { "(bad)", { XX } },
3457 { VEX_LEN_TABLE (VEX_LEN_60_P_2) },
3458 { "(bad)", { XX } },
3459 },
3460
3461 /* PREFIX_VEX_61 */
3462 {
3463 { "(bad)", { XX } },
3464 { "(bad)", { XX } },
3465 { VEX_LEN_TABLE (VEX_LEN_61_P_2) },
3466 { "(bad)", { XX } },
3467 },
3468
3469 /* PREFIX_VEX_62 */
3470 {
3471 { "(bad)", { XX } },
3472 { "(bad)", { XX } },
3473 { VEX_LEN_TABLE (VEX_LEN_62_P_2) },
3474 { "(bad)", { XX } },
3475 },
3476
3477 /* PREFIX_VEX_63 */
3478 {
3479 { "(bad)", { XX } },
3480 { "(bad)", { XX } },
3481 { VEX_LEN_TABLE (VEX_LEN_63_P_2) },
3482 { "(bad)", { XX } },
3483 },
3484
3485 /* PREFIX_VEX_64 */
3486 {
3487 { "(bad)", { XX } },
3488 { "(bad)", { XX } },
3489 { VEX_LEN_TABLE (VEX_LEN_64_P_2) },
3490 { "(bad)", { XX } },
3491 },
3492
3493 /* PREFIX_VEX_65 */
3494 {
3495 { "(bad)", { XX } },
3496 { "(bad)", { XX } },
3497 { VEX_LEN_TABLE (VEX_LEN_65_P_2) },
3498 { "(bad)", { XX } },
3499 },
3500
3501 /* PREFIX_VEX_66 */
3502 {
3503 { "(bad)", { XX } },
3504 { "(bad)", { XX } },
3505 { VEX_LEN_TABLE (VEX_LEN_66_P_2) },
3506 { "(bad)", { XX } },
3507 },
3508
3509 /* PREFIX_VEX_67 */
3510 {
3511 { "(bad)", { XX } },
3512 { "(bad)", { XX } },
3513 { VEX_LEN_TABLE (VEX_LEN_67_P_2) },
3514 { "(bad)", { XX } },
3515 },
3516
3517 /* PREFIX_VEX_68 */
3518 {
3519 { "(bad)", { XX } },
3520 { "(bad)", { XX } },
3521 { VEX_LEN_TABLE (VEX_LEN_68_P_2) },
3522 { "(bad)", { XX } },
3523 },
3524
3525 /* PREFIX_VEX_69 */
3526 {
3527 { "(bad)", { XX } },
3528 { "(bad)", { XX } },
3529 { VEX_LEN_TABLE (VEX_LEN_69_P_2) },
3530 { "(bad)", { XX } },
3531 },
3532
3533 /* PREFIX_VEX_6A */
3534 {
3535 { "(bad)", { XX } },
3536 { "(bad)", { XX } },
3537 { VEX_LEN_TABLE (VEX_LEN_6A_P_2) },
3538 { "(bad)", { XX } },
3539 },
3540
3541 /* PREFIX_VEX_6B */
3542 {
3543 { "(bad)", { XX } },
3544 { "(bad)", { XX } },
3545 { VEX_LEN_TABLE (VEX_LEN_6B_P_2) },
3546 { "(bad)", { XX } },
3547 },
3548
3549 /* PREFIX_VEX_6C */
3550 {
3551 { "(bad)", { XX } },
3552 { "(bad)", { XX } },
3553 { VEX_LEN_TABLE (VEX_LEN_6C_P_2) },
3554 { "(bad)", { XX } },
3555 },
3556
3557 /* PREFIX_VEX_6D */
3558 {
3559 { "(bad)", { XX } },
3560 { "(bad)", { XX } },
3561 { VEX_LEN_TABLE (VEX_LEN_6D_P_2) },
3562 { "(bad)", { XX } },
3563 },
3564
3565 /* PREFIX_VEX_6E */
3566 {
3567 { "(bad)", { XX } },
3568 { "(bad)", { XX } },
3569 { VEX_LEN_TABLE (VEX_LEN_6E_P_2) },
3570 { "(bad)", { XX } },
3571 },
3572
3573 /* PREFIX_VEX_6F */
3574 {
3575 { "(bad)", { XX } },
3576 { "vmovdqu", { XM, EXx } },
3577 { "vmovdqa", { XM, EXx } },
3578 { "(bad)", { XX } },
3579 },
3580
3581 /* PREFIX_VEX_70 */
3582 {
3583 { "(bad)", { XX } },
3584 { VEX_LEN_TABLE (VEX_LEN_70_P_1) },
3585 { VEX_LEN_TABLE (VEX_LEN_70_P_2) },
3586 { VEX_LEN_TABLE (VEX_LEN_70_P_3) },
3587 },
3588
3589 /* PREFIX_VEX_71_REG_2 */
3590 {
3591 { "(bad)", { XX } },
3592 { "(bad)", { XX } },
3593 { VEX_LEN_TABLE (VEX_LEN_71_R_2_P_2) },
3594 { "(bad)", { XX } },
3595 },
3596
3597 /* PREFIX_VEX_71_REG_4 */
3598 {
3599 { "(bad)", { XX } },
3600 { "(bad)", { XX } },
3601 { VEX_LEN_TABLE (VEX_LEN_71_R_4_P_2) },
3602 { "(bad)", { XX } },
3603 },
3604
3605 /* PREFIX_VEX_71_REG_6 */
3606 {
3607 { "(bad)", { XX } },
3608 { "(bad)", { XX } },
3609 { VEX_LEN_TABLE (VEX_LEN_71_R_6_P_2) },
3610 { "(bad)", { XX } },
3611 },
3612
3613 /* PREFIX_VEX_72_REG_2 */
3614 {
3615 { "(bad)", { XX } },
3616 { "(bad)", { XX } },
3617 { VEX_LEN_TABLE (VEX_LEN_72_R_2_P_2) },
3618 { "(bad)", { XX } },
3619 },
3620
3621 /* PREFIX_VEX_72_REG_4 */
3622 {
3623 { "(bad)", { XX } },
3624 { "(bad)", { XX } },
3625 { VEX_LEN_TABLE (VEX_LEN_72_R_4_P_2) },
3626 { "(bad)", { XX } },
3627 },
3628
3629 /* PREFIX_VEX_72_REG_6 */
3630 {
3631 { "(bad)", { XX } },
3632 { "(bad)", { XX } },
3633 { VEX_LEN_TABLE (VEX_LEN_72_R_6_P_2) },
3634 { "(bad)", { XX } },
3635 },
3636
3637 /* PREFIX_VEX_73_REG_2 */
3638 {
3639 { "(bad)", { XX } },
3640 { "(bad)", { XX } },
3641 { VEX_LEN_TABLE (VEX_LEN_73_R_2_P_2) },
3642 { "(bad)", { XX } },
3643 },
3644
3645 /* PREFIX_VEX_73_REG_3 */
3646 {
3647 { "(bad)", { XX } },
3648 { "(bad)", { XX } },
3649 { VEX_LEN_TABLE (VEX_LEN_73_R_3_P_2) },
3650 { "(bad)", { XX } },
3651 },
3652
3653 /* PREFIX_VEX_73_REG_6 */
3654 {
3655 { "(bad)", { XX } },
3656 { "(bad)", { XX } },
3657 { VEX_LEN_TABLE (VEX_LEN_73_R_6_P_2) },
3658 { "(bad)", { XX } },
3659 },
3660
3661 /* PREFIX_VEX_73_REG_7 */
3662 {
3663 { "(bad)", { XX } },
3664 { "(bad)", { XX } },
3665 { VEX_LEN_TABLE (VEX_LEN_73_R_7_P_2) },
3666 { "(bad)", { XX } },
3667 },
3668
3669 /* PREFIX_VEX_74 */
3670 {
3671 { "(bad)", { XX } },
3672 { "(bad)", { XX } },
3673 { VEX_LEN_TABLE (VEX_LEN_74_P_2) },
3674 { "(bad)", { XX } },
3675 },
3676
3677 /* PREFIX_VEX_75 */
3678 {
3679 { "(bad)", { XX } },
3680 { "(bad)", { XX } },
3681 { VEX_LEN_TABLE (VEX_LEN_75_P_2) },
3682 { "(bad)", { XX } },
3683 },
3684
3685 /* PREFIX_VEX_76 */
3686 {
3687 { "(bad)", { XX } },
3688 { "(bad)", { XX } },
3689 { VEX_LEN_TABLE (VEX_LEN_76_P_2) },
3690 { "(bad)", { XX } },
3691 },
3692
3693 /* PREFIX_VEX_77 */
3694 {
3695 { "", { VZERO } },
3696 { "(bad)", { XX } },
3697 { "(bad)", { XX } },
3698 { "(bad)", { XX } },
3699 },
3700
3701 /* PREFIX_VEX_7C */
3702 {
3703 { "(bad)", { XX } },
3704 { "(bad)", { XX } },
3705 { "vhaddpd", { XM, Vex, EXx } },
3706 { "vhaddps", { XM, Vex, EXx } },
3707 },
3708
3709 /* PREFIX_VEX_7D */
3710 {
3711 { "(bad)", { XX } },
3712 { "(bad)", { XX } },
3713 { "vhsubpd", { XM, Vex, EXx } },
3714 { "vhsubps", { XM, Vex, EXx } },
3715 },
3716
3717 /* PREFIX_VEX_7E */
3718 {
3719 { "(bad)", { XX } },
3720 { VEX_LEN_TABLE (VEX_LEN_7E_P_1) },
3721 { VEX_LEN_TABLE (VEX_LEN_7E_P_2) },
3722 { "(bad)", { XX } },
3723 },
3724
3725 /* PREFIX_VEX_7F */
3726 {
3727 { "(bad)", { XX } },
3728 { "vmovdqu", { EXxS, XM } },
3729 { "vmovdqa", { EXxS, XM } },
3730 { "(bad)", { XX } },
3731 },
3732
3733 /* PREFIX_VEX_C2 */
3734 {
3735 { "vcmpps", { XM, Vex, EXx, VCMP } },
3736 { VEX_LEN_TABLE (VEX_LEN_C2_P_1) },
3737 { "vcmppd", { XM, Vex, EXx, VCMP } },
3738 { VEX_LEN_TABLE (VEX_LEN_C2_P_3) },
3739 },
3740
3741 /* PREFIX_VEX_C4 */
3742 {
3743 { "(bad)", { XX } },
3744 { "(bad)", { XX } },
3745 { VEX_LEN_TABLE (VEX_LEN_C4_P_2) },
3746 { "(bad)", { XX } },
3747 },
3748
3749 /* PREFIX_VEX_C5 */
3750 {
3751 { "(bad)", { XX } },
3752 { "(bad)", { XX } },
3753 { VEX_LEN_TABLE (VEX_LEN_C5_P_2) },
3754 { "(bad)", { XX } },
3755 },
3756
3757 /* PREFIX_VEX_D0 */
3758 {
3759 { "(bad)", { XX } },
3760 { "(bad)", { XX } },
3761 { "vaddsubpd", { XM, Vex, EXx } },
3762 { "vaddsubps", { XM, Vex, EXx } },
3763 },
3764
3765 /* PREFIX_VEX_D1 */
3766 {
3767 { "(bad)", { XX } },
3768 { "(bad)", { XX } },
3769 { VEX_LEN_TABLE (VEX_LEN_D1_P_2) },
3770 { "(bad)", { XX } },
3771 },
3772
3773 /* PREFIX_VEX_D2 */
3774 {
3775 { "(bad)", { XX } },
3776 { "(bad)", { XX } },
3777 { VEX_LEN_TABLE (VEX_LEN_D2_P_2) },
3778 { "(bad)", { XX } },
3779 },
3780
3781 /* PREFIX_VEX_D3 */
3782 {
3783 { "(bad)", { XX } },
3784 { "(bad)", { XX } },
3785 { VEX_LEN_TABLE (VEX_LEN_D3_P_2) },
3786 { "(bad)", { XX } },
3787 },
3788
3789 /* PREFIX_VEX_D4 */
3790 {
3791 { "(bad)", { XX } },
3792 { "(bad)", { XX } },
3793 { VEX_LEN_TABLE (VEX_LEN_D4_P_2) },
3794 { "(bad)", { XX } },
3795 },
3796
3797 /* PREFIX_VEX_D5 */
3798 {
3799 { "(bad)", { XX } },
3800 { "(bad)", { XX } },
3801 { VEX_LEN_TABLE (VEX_LEN_D5_P_2) },
3802 { "(bad)", { XX } },
3803 },
3804
3805 /* PREFIX_VEX_D6 */
3806 {
3807 { "(bad)", { XX } },
3808 { "(bad)", { XX } },
3809 { VEX_LEN_TABLE (VEX_LEN_D6_P_2) },
3810 { "(bad)", { XX } },
3811 },
3812
3813 /* PREFIX_VEX_D7 */
3814 {
3815 { "(bad)", { XX } },
3816 { "(bad)", { XX } },
3817 { MOD_TABLE (MOD_VEX_D7_PREFIX_2) },
3818 { "(bad)", { XX } },
3819 },
3820
3821 /* PREFIX_VEX_D8 */
3822 {
3823 { "(bad)", { XX } },
3824 { "(bad)", { XX } },
3825 { VEX_LEN_TABLE (VEX_LEN_D8_P_2) },
3826 { "(bad)", { XX } },
3827 },
3828
3829 /* PREFIX_VEX_D9 */
3830 {
3831 { "(bad)", { XX } },
3832 { "(bad)", { XX } },
3833 { VEX_LEN_TABLE (VEX_LEN_D9_P_2) },
3834 { "(bad)", { XX } },
3835 },
3836
3837 /* PREFIX_VEX_DA */
3838 {
3839 { "(bad)", { XX } },
3840 { "(bad)", { XX } },
3841 { VEX_LEN_TABLE (VEX_LEN_DA_P_2) },
3842 { "(bad)", { XX } },
3843 },
3844
3845 /* PREFIX_VEX_DB */
3846 {
3847 { "(bad)", { XX } },
3848 { "(bad)", { XX } },
3849 { VEX_LEN_TABLE (VEX_LEN_DB_P_2) },
3850 { "(bad)", { XX } },
3851 },
3852
3853 /* PREFIX_VEX_DC */
3854 {
3855 { "(bad)", { XX } },
3856 { "(bad)", { XX } },
3857 { VEX_LEN_TABLE (VEX_LEN_DC_P_2) },
3858 { "(bad)", { XX } },
3859 },
3860
3861 /* PREFIX_VEX_DD */
3862 {
3863 { "(bad)", { XX } },
3864 { "(bad)", { XX } },
3865 { VEX_LEN_TABLE (VEX_LEN_DD_P_2) },
3866 { "(bad)", { XX } },
3867 },
3868
3869 /* PREFIX_VEX_DE */
3870 {
3871 { "(bad)", { XX } },
3872 { "(bad)", { XX } },
3873 { VEX_LEN_TABLE (VEX_LEN_DE_P_2) },
3874 { "(bad)", { XX } },
3875 },
3876
3877 /* PREFIX_VEX_DF */
3878 {
3879 { "(bad)", { XX } },
3880 { "(bad)", { XX } },
3881 { VEX_LEN_TABLE (VEX_LEN_DF_P_2) },
3882 { "(bad)", { XX } },
3883 },
3884
3885 /* PREFIX_VEX_E0 */
3886 {
3887 { "(bad)", { XX } },
3888 { "(bad)", { XX } },
3889 { VEX_LEN_TABLE (VEX_LEN_E0_P_2) },
3890 { "(bad)", { XX } },
3891 },
3892
3893 /* PREFIX_VEX_E1 */
3894 {
3895 { "(bad)", { XX } },
3896 { "(bad)", { XX } },
3897 { VEX_LEN_TABLE (VEX_LEN_E1_P_2) },
3898 { "(bad)", { XX } },
3899 },
3900
3901 /* PREFIX_VEX_E2 */
3902 {
3903 { "(bad)", { XX } },
3904 { "(bad)", { XX } },
3905 { VEX_LEN_TABLE (VEX_LEN_E2_P_2) },
3906 { "(bad)", { XX } },
3907 },
3908
3909 /* PREFIX_VEX_E3 */
3910 {
3911 { "(bad)", { XX } },
3912 { "(bad)", { XX } },
3913 { VEX_LEN_TABLE (VEX_LEN_E3_P_2) },
3914 { "(bad)", { XX } },
3915 },
3916
3917 /* PREFIX_VEX_E4 */
3918 {
3919 { "(bad)", { XX } },
3920 { "(bad)", { XX } },
3921 { VEX_LEN_TABLE (VEX_LEN_E4_P_2) },
3922 { "(bad)", { XX } },
3923 },
3924
3925 /* PREFIX_VEX_E5 */
3926 {
3927 { "(bad)", { XX } },
3928 { "(bad)", { XX } },
3929 { VEX_LEN_TABLE (VEX_LEN_E5_P_2) },
3930 { "(bad)", { XX } },
3931 },
3932
3933 /* PREFIX_VEX_E6 */
3934 {
3935 { "(bad)", { XX } },
3936 { "vcvtdq2pd", { XM, EXxmmq } },
3937 { "vcvttpd2dq%XY", { XMM, EXx } },
3938 { "vcvtpd2dq%XY", { XMM, EXx } },
3939 },
3940
3941 /* PREFIX_VEX_E7 */
3942 {
3943 { "(bad)", { XX } },
3944 { "(bad)", { XX } },
3945 { MOD_TABLE (MOD_VEX_E7_PREFIX_2) },
3946 { "(bad)", { XX } },
3947 },
3948
3949 /* PREFIX_VEX_E8 */
3950 {
3951 { "(bad)", { XX } },
3952 { "(bad)", { XX } },
3953 { VEX_LEN_TABLE (VEX_LEN_E8_P_2) },
3954 { "(bad)", { XX } },
3955 },
3956
3957 /* PREFIX_VEX_E9 */
3958 {
3959 { "(bad)", { XX } },
3960 { "(bad)", { XX } },
3961 { VEX_LEN_TABLE (VEX_LEN_E9_P_2) },
3962 { "(bad)", { XX } },
3963 },
3964
3965 /* PREFIX_VEX_EA */
3966 {
3967 { "(bad)", { XX } },
3968 { "(bad)", { XX } },
3969 { VEX_LEN_TABLE (VEX_LEN_EA_P_2) },
3970 { "(bad)", { XX } },
3971 },
3972
3973 /* PREFIX_VEX_EB */
3974 {
3975 { "(bad)", { XX } },
3976 { "(bad)", { XX } },
3977 { VEX_LEN_TABLE (VEX_LEN_EB_P_2) },
3978 { "(bad)", { XX } },
3979 },
3980
3981 /* PREFIX_VEX_EC */
3982 {
3983 { "(bad)", { XX } },
3984 { "(bad)", { XX } },
3985 { VEX_LEN_TABLE (VEX_LEN_EC_P_2) },
3986 { "(bad)", { XX } },
3987 },
3988
3989 /* PREFIX_VEX_ED */
3990 {
3991 { "(bad)", { XX } },
3992 { "(bad)", { XX } },
3993 { VEX_LEN_TABLE (VEX_LEN_ED_P_2) },
3994 { "(bad)", { XX } },
3995 },
3996
3997 /* PREFIX_VEX_EE */
3998 {
3999 { "(bad)", { XX } },
4000 { "(bad)", { XX } },
4001 { VEX_LEN_TABLE (VEX_LEN_EE_P_2) },
4002 { "(bad)", { XX } },
4003 },
4004
4005 /* PREFIX_VEX_EF */
4006 {
4007 { "(bad)", { XX } },
4008 { "(bad)", { XX } },
4009 { VEX_LEN_TABLE (VEX_LEN_EF_P_2) },
4010 { "(bad)", { XX } },
4011 },
4012
4013 /* PREFIX_VEX_F0 */
4014 {
4015 { "(bad)", { XX } },
4016 { "(bad)", { XX } },
4017 { "(bad)", { XX } },
4018 { MOD_TABLE (MOD_VEX_F0_PREFIX_3) },
4019 },
4020
4021 /* PREFIX_VEX_F1 */
4022 {
4023 { "(bad)", { XX } },
4024 { "(bad)", { XX } },
4025 { VEX_LEN_TABLE (VEX_LEN_F1_P_2) },
4026 { "(bad)", { XX } },
4027 },
4028
4029 /* PREFIX_VEX_F2 */
4030 {
4031 { "(bad)", { XX } },
4032 { "(bad)", { XX } },
4033 { VEX_LEN_TABLE (VEX_LEN_F2_P_2) },
4034 { "(bad)", { XX } },
4035 },
4036
4037 /* PREFIX_VEX_F3 */
4038 {
4039 { "(bad)", { XX } },
4040 { "(bad)", { XX } },
4041 { VEX_LEN_TABLE (VEX_LEN_F3_P_2) },
4042 { "(bad)", { XX } },
4043 },
4044
4045 /* PREFIX_VEX_F4 */
4046 {
4047 { "(bad)", { XX } },
4048 { "(bad)", { XX } },
4049 { VEX_LEN_TABLE (VEX_LEN_F4_P_2) },
4050 { "(bad)", { XX } },
4051 },
4052
4053 /* PREFIX_VEX_F5 */
4054 {
4055 { "(bad)", { XX } },
4056 { "(bad)", { XX } },
4057 { VEX_LEN_TABLE (VEX_LEN_F5_P_2) },
4058 { "(bad)", { XX } },
4059 },
4060
4061 /* PREFIX_VEX_F6 */
4062 {
4063 { "(bad)", { XX } },
4064 { "(bad)", { XX } },
4065 { VEX_LEN_TABLE (VEX_LEN_F6_P_2) },
4066 { "(bad)", { XX } },
4067 },
4068
4069 /* PREFIX_VEX_F7 */
4070 {
4071 { "(bad)", { XX } },
4072 { "(bad)", { XX } },
4073 { VEX_LEN_TABLE (VEX_LEN_F7_P_2) },
4074 { "(bad)", { XX } },
4075 },
4076
4077 /* PREFIX_VEX_F8 */
4078 {
4079 { "(bad)", { XX } },
4080 { "(bad)", { XX } },
4081 { VEX_LEN_TABLE (VEX_LEN_F8_P_2) },
4082 { "(bad)", { XX } },
4083 },
4084
4085 /* PREFIX_VEX_F9 */
4086 {
4087 { "(bad)", { XX } },
4088 { "(bad)", { XX } },
4089 { VEX_LEN_TABLE (VEX_LEN_F9_P_2) },
4090 { "(bad)", { XX } },
4091 },
4092
4093 /* PREFIX_VEX_FA */
4094 {
4095 { "(bad)", { XX } },
4096 { "(bad)", { XX } },
4097 { VEX_LEN_TABLE (VEX_LEN_FA_P_2) },
4098 { "(bad)", { XX } },
4099 },
4100
4101 /* PREFIX_VEX_FB */
4102 {
4103 { "(bad)", { XX } },
4104 { "(bad)", { XX } },
4105 { VEX_LEN_TABLE (VEX_LEN_FB_P_2) },
4106 { "(bad)", { XX } },
4107 },
4108
4109 /* PREFIX_VEX_FC */
4110 {
4111 { "(bad)", { XX } },
4112 { "(bad)", { XX } },
4113 { VEX_LEN_TABLE (VEX_LEN_FC_P_2) },
4114 { "(bad)", { XX } },
4115 },
4116
4117 /* PREFIX_VEX_FD */
4118 {
4119 { "(bad)", { XX } },
4120 { "(bad)", { XX } },
4121 { VEX_LEN_TABLE (VEX_LEN_FD_P_2) },
4122 { "(bad)", { XX } },
4123 },
4124
4125 /* PREFIX_VEX_FE */
4126 {
4127 { "(bad)", { XX } },
4128 { "(bad)", { XX } },
4129 { VEX_LEN_TABLE (VEX_LEN_FE_P_2) },
4130 { "(bad)", { XX } },
4131 },
4132
4133 /* PREFIX_VEX_3800 */
4134 {
4135 { "(bad)", { XX } },
4136 { "(bad)", { XX } },
4137 { VEX_LEN_TABLE (VEX_LEN_3800_P_2) },
4138 { "(bad)", { XX } },
4139 },
4140
4141 /* PREFIX_VEX_3801 */
4142 {
4143 { "(bad)", { XX } },
4144 { "(bad)", { XX } },
4145 { VEX_LEN_TABLE (VEX_LEN_3801_P_2) },
4146 { "(bad)", { XX } },
4147 },
4148
4149 /* PREFIX_VEX_3802 */
4150 {
4151 { "(bad)", { XX } },
4152 { "(bad)", { XX } },
4153 { VEX_LEN_TABLE (VEX_LEN_3802_P_2) },
4154 { "(bad)", { XX } },
4155 },
4156
4157 /* PREFIX_VEX_3803 */
4158 {
4159 { "(bad)", { XX } },
4160 { "(bad)", { XX } },
4161 { VEX_LEN_TABLE (VEX_LEN_3803_P_2) },
4162 { "(bad)", { XX } },
4163 },
4164
4165 /* PREFIX_VEX_3804 */
4166 {
4167 { "(bad)", { XX } },
4168 { "(bad)", { XX } },
4169 { VEX_LEN_TABLE (VEX_LEN_3804_P_2) },
4170 { "(bad)", { XX } },
4171 },
4172
4173 /* PREFIX_VEX_3805 */
4174 {
4175 { "(bad)", { XX } },
4176 { "(bad)", { XX } },
4177 { VEX_LEN_TABLE (VEX_LEN_3805_P_2) },
4178 { "(bad)", { XX } },
4179 },
4180
4181 /* PREFIX_VEX_3806 */
4182 {
4183 { "(bad)", { XX } },
4184 { "(bad)", { XX } },
4185 { VEX_LEN_TABLE (VEX_LEN_3806_P_2) },
4186 { "(bad)", { XX } },
4187 },
4188
4189 /* PREFIX_VEX_3807 */
4190 {
4191 { "(bad)", { XX } },
4192 { "(bad)", { XX } },
4193 { VEX_LEN_TABLE (VEX_LEN_3807_P_2) },
4194 { "(bad)", { XX } },
4195 },
4196
4197 /* PREFIX_VEX_3808 */
4198 {
4199 { "(bad)", { XX } },
4200 { "(bad)", { XX } },
4201 { VEX_LEN_TABLE (VEX_LEN_3808_P_2) },
4202 { "(bad)", { XX } },
4203 },
4204
4205 /* PREFIX_VEX_3809 */
4206 {
4207 { "(bad)", { XX } },
4208 { "(bad)", { XX } },
4209 { VEX_LEN_TABLE (VEX_LEN_3809_P_2) },
4210 { "(bad)", { XX } },
4211 },
4212
4213 /* PREFIX_VEX_380A */
4214 {
4215 { "(bad)", { XX } },
4216 { "(bad)", { XX } },
4217 { VEX_LEN_TABLE (VEX_LEN_380A_P_2) },
4218 { "(bad)", { XX } },
4219 },
4220
4221 /* PREFIX_VEX_380B */
4222 {
4223 { "(bad)", { XX } },
4224 { "(bad)", { XX } },
4225 { VEX_LEN_TABLE (VEX_LEN_380B_P_2) },
4226 { "(bad)", { XX } },
4227 },
4228
4229 /* PREFIX_VEX_380C */
4230 {
4231 { "(bad)", { XX } },
4232 { "(bad)", { XX } },
4233 { "vpermilps", { XM, Vex, EXx } },
4234 { "(bad)", { XX } },
4235 },
4236
4237 /* PREFIX_VEX_380D */
4238 {
4239 { "(bad)", { XX } },
4240 { "(bad)", { XX } },
4241 { "vpermilpd", { XM, Vex, EXx } },
4242 { "(bad)", { XX } },
4243 },
4244
4245 /* PREFIX_VEX_380E */
4246 {
4247 { "(bad)", { XX } },
4248 { "(bad)", { XX } },
4249 { "vtestps", { XM, EXx } },
4250 { "(bad)", { XX } },
4251 },
4252
4253 /* PREFIX_VEX_380F */
4254 {
4255 { "(bad)", { XX } },
4256 { "(bad)", { XX } },
4257 { "vtestpd", { XM, EXx } },
4258 { "(bad)", { XX } },
4259 },
4260
4261 /* PREFIX_VEX_3817 */
4262 {
4263 { "(bad)", { XX } },
4264 { "(bad)", { XX } },
4265 { "vptest", { XM, EXx } },
4266 { "(bad)", { XX } },
4267 },
4268
4269 /* PREFIX_VEX_3818 */
4270 {
4271 { "(bad)", { XX } },
4272 { "(bad)", { XX } },
4273 { MOD_TABLE (MOD_VEX_3818_PREFIX_2) },
4274 { "(bad)", { XX } },
4275 },
4276
4277 /* PREFIX_VEX_3819 */
4278 {
4279 { "(bad)", { XX } },
4280 { "(bad)", { XX } },
4281 { MOD_TABLE (MOD_VEX_3819_PREFIX_2) },
4282 { "(bad)", { XX } },
4283 },
4284
4285 /* PREFIX_VEX_381A */
4286 {
4287 { "(bad)", { XX } },
4288 { "(bad)", { XX } },
4289 { MOD_TABLE (MOD_VEX_381A_PREFIX_2) },
4290 { "(bad)", { XX } },
4291 },
4292
4293 /* PREFIX_VEX_381C */
4294 {
4295 { "(bad)", { XX } },
4296 { "(bad)", { XX } },
4297 { VEX_LEN_TABLE (VEX_LEN_381C_P_2) },
4298 { "(bad)", { XX } },
4299 },
4300
4301 /* PREFIX_VEX_381D */
4302 {
4303 { "(bad)", { XX } },
4304 { "(bad)", { XX } },
4305 { VEX_LEN_TABLE (VEX_LEN_381D_P_2) },
4306 { "(bad)", { XX } },
4307 },
4308
4309 /* PREFIX_VEX_381E */
4310 {
4311 { "(bad)", { XX } },
4312 { "(bad)", { XX } },
4313 { VEX_LEN_TABLE (VEX_LEN_381E_P_2) },
4314 { "(bad)", { XX } },
4315 },
4316
4317 /* PREFIX_VEX_3820 */
4318 {
4319 { "(bad)", { XX } },
4320 { "(bad)", { XX } },
4321 { VEX_LEN_TABLE (VEX_LEN_3820_P_2) },
4322 { "(bad)", { XX } },
4323 },
4324
4325 /* PREFIX_VEX_3821 */
4326 {
4327 { "(bad)", { XX } },
4328 { "(bad)", { XX } },
4329 { VEX_LEN_TABLE (VEX_LEN_3821_P_2) },
4330 { "(bad)", { XX } },
4331 },
4332
4333 /* PREFIX_VEX_3822 */
4334 {
4335 { "(bad)", { XX } },
4336 { "(bad)", { XX } },
4337 { VEX_LEN_TABLE (VEX_LEN_3822_P_2) },
4338 { "(bad)", { XX } },
4339 },
4340
4341 /* PREFIX_VEX_3823 */
4342 {
4343 { "(bad)", { XX } },
4344 { "(bad)", { XX } },
4345 { VEX_LEN_TABLE (VEX_LEN_3823_P_2) },
4346 { "(bad)", { XX } },
4347 },
4348
4349 /* PREFIX_VEX_3824 */
4350 {
4351 { "(bad)", { XX } },
4352 { "(bad)", { XX } },
4353 { VEX_LEN_TABLE (VEX_LEN_3824_P_2) },
4354 { "(bad)", { XX } },
4355 },
4356
4357 /* PREFIX_VEX_3825 */
4358 {
4359 { "(bad)", { XX } },
4360 { "(bad)", { XX } },
4361 { VEX_LEN_TABLE (VEX_LEN_3825_P_2) },
4362 { "(bad)", { XX } },
4363 },
4364
4365 /* PREFIX_VEX_3828 */
4366 {
4367 { "(bad)", { XX } },
4368 { "(bad)", { XX } },
4369 { VEX_LEN_TABLE (VEX_LEN_3828_P_2) },
4370 { "(bad)", { XX } },
4371 },
4372
4373 /* PREFIX_VEX_3829 */
4374 {
4375 { "(bad)", { XX } },
4376 { "(bad)", { XX } },
4377 { VEX_LEN_TABLE (VEX_LEN_3829_P_2) },
4378 { "(bad)", { XX } },
4379 },
4380
4381 /* PREFIX_VEX_382A */
4382 {
4383 { "(bad)", { XX } },
4384 { "(bad)", { XX } },
4385 { MOD_TABLE (MOD_VEX_382A_PREFIX_2) },
4386 { "(bad)", { XX } },
4387 },
4388
4389 /* PREFIX_VEX_382B */
4390 {
4391 { "(bad)", { XX } },
4392 { "(bad)", { XX } },
4393 { VEX_LEN_TABLE (VEX_LEN_382B_P_2) },
4394 { "(bad)", { XX } },
4395 },
4396
4397 /* PREFIX_VEX_382C */
4398 {
4399 { "(bad)", { XX } },
4400 { "(bad)", { XX } },
4401 { MOD_TABLE (MOD_VEX_382C_PREFIX_2) },
4402 { "(bad)", { XX } },
4403 },
4404
4405 /* PREFIX_VEX_382D */
4406 {
4407 { "(bad)", { XX } },
4408 { "(bad)", { XX } },
4409 { MOD_TABLE (MOD_VEX_382D_PREFIX_2) },
4410 { "(bad)", { XX } },
4411 },
4412
4413 /* PREFIX_VEX_382E */
4414 {
4415 { "(bad)", { XX } },
4416 { "(bad)", { XX } },
4417 { MOD_TABLE (MOD_VEX_382E_PREFIX_2) },
4418 { "(bad)", { XX } },
4419 },
4420
4421 /* PREFIX_VEX_382F */
4422 {
4423 { "(bad)", { XX } },
4424 { "(bad)", { XX } },
4425 { MOD_TABLE (MOD_VEX_382F_PREFIX_2) },
4426 { "(bad)", { XX } },
4427 },
4428
4429 /* PREFIX_VEX_3830 */
4430 {
4431 { "(bad)", { XX } },
4432 { "(bad)", { XX } },
4433 { VEX_LEN_TABLE (VEX_LEN_3830_P_2) },
4434 { "(bad)", { XX } },
4435 },
4436
4437 /* PREFIX_VEX_3831 */
4438 {
4439 { "(bad)", { XX } },
4440 { "(bad)", { XX } },
4441 { VEX_LEN_TABLE (VEX_LEN_3831_P_2) },
4442 { "(bad)", { XX } },
4443 },
4444
4445 /* PREFIX_VEX_3832 */
4446 {
4447 { "(bad)", { XX } },
4448 { "(bad)", { XX } },
4449 { VEX_LEN_TABLE (VEX_LEN_3832_P_2) },
4450 { "(bad)", { XX } },
4451 },
4452
4453 /* PREFIX_VEX_3833 */
4454 {
4455 { "(bad)", { XX } },
4456 { "(bad)", { XX } },
4457 { VEX_LEN_TABLE (VEX_LEN_3833_P_2) },
4458 { "(bad)", { XX } },
4459 },
4460
4461 /* PREFIX_VEX_3834 */
4462 {
4463 { "(bad)", { XX } },
4464 { "(bad)", { XX } },
4465 { VEX_LEN_TABLE (VEX_LEN_3834_P_2) },
4466 { "(bad)", { XX } },
4467 },
4468
4469 /* PREFIX_VEX_3835 */
4470 {
4471 { "(bad)", { XX } },
4472 { "(bad)", { XX } },
4473 { VEX_LEN_TABLE (VEX_LEN_3835_P_2) },
4474 { "(bad)", { XX } },
4475 },
4476
4477 /* PREFIX_VEX_3837 */
4478 {
4479 { "(bad)", { XX } },
4480 { "(bad)", { XX } },
4481 { VEX_LEN_TABLE (VEX_LEN_3837_P_2) },
4482 { "(bad)", { XX } },
4483 },
4484
4485 /* PREFIX_VEX_3838 */
4486 {
4487 { "(bad)", { XX } },
4488 { "(bad)", { XX } },
4489 { VEX_LEN_TABLE (VEX_LEN_3838_P_2) },
4490 { "(bad)", { XX } },
4491 },
4492
4493 /* PREFIX_VEX_3839 */
4494 {
4495 { "(bad)", { XX } },
4496 { "(bad)", { XX } },
4497 { VEX_LEN_TABLE (VEX_LEN_3839_P_2) },
4498 { "(bad)", { XX } },
4499 },
4500
4501 /* PREFIX_VEX_383A */
4502 {
4503 { "(bad)", { XX } },
4504 { "(bad)", { XX } },
4505 { VEX_LEN_TABLE (VEX_LEN_383A_P_2) },
4506 { "(bad)", { XX } },
4507 },
4508
4509 /* PREFIX_VEX_383B */
4510 {
4511 { "(bad)", { XX } },
4512 { "(bad)", { XX } },
4513 { VEX_LEN_TABLE (VEX_LEN_383B_P_2) },
4514 { "(bad)", { XX } },
4515 },
4516
4517 /* PREFIX_VEX_383C */
4518 {
4519 { "(bad)", { XX } },
4520 { "(bad)", { XX } },
4521 { VEX_LEN_TABLE (VEX_LEN_383C_P_2) },
4522 { "(bad)", { XX } },
4523 },
4524
4525 /* PREFIX_VEX_383D */
4526 {
4527 { "(bad)", { XX } },
4528 { "(bad)", { XX } },
4529 { VEX_LEN_TABLE (VEX_LEN_383D_P_2) },
4530 { "(bad)", { XX } },
4531 },
4532
4533 /* PREFIX_VEX_383E */
4534 {
4535 { "(bad)", { XX } },
4536 { "(bad)", { XX } },
4537 { VEX_LEN_TABLE (VEX_LEN_383E_P_2) },
4538 { "(bad)", { XX } },
4539 },
4540
4541 /* PREFIX_VEX_383F */
4542 {
4543 { "(bad)", { XX } },
4544 { "(bad)", { XX } },
4545 { VEX_LEN_TABLE (VEX_LEN_383F_P_2) },
4546 { "(bad)", { XX } },
4547 },
4548
4549 /* PREFIX_VEX_3840 */
4550 {
4551 { "(bad)", { XX } },
4552 { "(bad)", { XX } },
4553 { VEX_LEN_TABLE (VEX_LEN_3840_P_2) },
4554 { "(bad)", { XX } },
4555 },
4556
4557 /* PREFIX_VEX_3841 */
4558 {
4559 { "(bad)", { XX } },
4560 { "(bad)", { XX } },
4561 { VEX_LEN_TABLE (VEX_LEN_3841_P_2) },
4562 { "(bad)", { XX } },
4563 },
4564
4565 /* PREFIX_VEX_3896 */
4566 {
4567 { "(bad)", { XX } },
4568 { "(bad)", { XX } },
4569 { "vfmaddsub132p%XW", { XM, Vex, EXx } },
4570 { "(bad)", { XX } },
4571 },
4572
4573 /* PREFIX_VEX_3897 */
4574 {
4575 { "(bad)", { XX } },
4576 { "(bad)", { XX } },
4577 { "vfmsubadd132p%XW", { XM, Vex, EXx } },
4578 { "(bad)", { XX } },
4579 },
4580
4581 /* PREFIX_VEX_3898 */
4582 {
4583 { "(bad)", { XX } },
4584 { "(bad)", { XX } },
4585 { "vfmadd132p%XW", { XM, Vex, EXx } },
4586 { "(bad)", { XX } },
4587 },
4588
4589 /* PREFIX_VEX_3899 */
4590 {
4591 { "(bad)", { XX } },
4592 { "(bad)", { XX } },
4593 { "vfmadd132s%XW", { XM, Vex, EXVexWdq } },
4594 { "(bad)", { XX } },
4595 },
4596
4597 /* PREFIX_VEX_389A */
4598 {
4599 { "(bad)", { XX } },
4600 { "(bad)", { XX } },
4601 { "vfmsub132p%XW", { XM, Vex, EXx } },
4602 { "(bad)", { XX } },
4603 },
4604
4605 /* PREFIX_VEX_389B */
4606 {
4607 { "(bad)", { XX } },
4608 { "(bad)", { XX } },
4609 { "vfmsub132s%XW", { XM, Vex, EXVexWdq } },
4610 { "(bad)", { XX } },
4611 },
4612
4613 /* PREFIX_VEX_389C */
4614 {
4615 { "(bad)", { XX } },
4616 { "(bad)", { XX } },
4617 { "vfnmadd132p%XW", { XM, Vex, EXx } },
4618 { "(bad)", { XX } },
4619 },
4620
4621 /* PREFIX_VEX_389D */
4622 {
4623 { "(bad)", { XX } },
4624 { "(bad)", { XX } },
4625 { "vfnmadd132s%XW", { XM, Vex, EXVexWdq } },
4626 { "(bad)", { XX } },
4627 },
4628
4629 /* PREFIX_VEX_389E */
4630 {
4631 { "(bad)", { XX } },
4632 { "(bad)", { XX } },
4633 { "vfnmsub132p%XW", { XM, Vex, EXx } },
4634 { "(bad)", { XX } },
4635 },
4636
4637 /* PREFIX_VEX_389F */
4638 {
4639 { "(bad)", { XX } },
4640 { "(bad)", { XX } },
4641 { "vfnmsub132s%XW", { XM, Vex, EXVexWdq } },
4642 { "(bad)", { XX } },
4643 },
4644
4645 /* PREFIX_VEX_38A6 */
4646 {
4647 { "(bad)", { XX } },
4648 { "(bad)", { XX } },
4649 { "vfmaddsub213p%XW", { XM, Vex, EXx } },
4650 { "(bad)", { XX } },
4651 },
4652
4653 /* PREFIX_VEX_38A7 */
4654 {
4655 { "(bad)", { XX } },
4656 { "(bad)", { XX } },
4657 { "vfmsubadd213p%XW", { XM, Vex, EXx } },
4658 { "(bad)", { XX } },
4659 },
4660
4661 /* PREFIX_VEX_38A8 */
4662 {
4663 { "(bad)", { XX } },
4664 { "(bad)", { XX } },
4665 { "vfmadd213p%XW", { XM, Vex, EXx } },
4666 { "(bad)", { XX } },
4667 },
4668
4669 /* PREFIX_VEX_38A9 */
4670 {
4671 { "(bad)", { XX } },
4672 { "(bad)", { XX } },
4673 { "vfmadd213s%XW", { XM, Vex, EXVexWdq } },
4674 { "(bad)", { XX } },
4675 },
4676
4677 /* PREFIX_VEX_38AA */
4678 {
4679 { "(bad)", { XX } },
4680 { "(bad)", { XX } },
4681 { "vfmsub213p%XW", { XM, Vex, EXx } },
4682 { "(bad)", { XX } },
4683 },
4684
4685 /* PREFIX_VEX_38AB */
4686 {
4687 { "(bad)", { XX } },
4688 { "(bad)", { XX } },
4689 { "vfmsub213s%XW", { XM, Vex, EXVexWdq } },
4690 { "(bad)", { XX } },
4691 },
4692
4693 /* PREFIX_VEX_38AC */
4694 {
4695 { "(bad)", { XX } },
4696 { "(bad)", { XX } },
4697 { "vfnmadd213p%XW", { XM, Vex, EXx } },
4698 { "(bad)", { XX } },
4699 },
4700
4701 /* PREFIX_VEX_38AD */
4702 {
4703 { "(bad)", { XX } },
4704 { "(bad)", { XX } },
4705 { "vfnmadd213s%XW", { XM, Vex, EXVexWdq } },
4706 { "(bad)", { XX } },
4707 },
4708
4709 /* PREFIX_VEX_38AE */
4710 {
4711 { "(bad)", { XX } },
4712 { "(bad)", { XX } },
4713 { "vfnmsub213p%XW", { XM, Vex, EXx } },
4714 { "(bad)", { XX } },
4715 },
4716
4717 /* PREFIX_VEX_38AF */
4718 {
4719 { "(bad)", { XX } },
4720 { "(bad)", { XX } },
4721 { "vfnmsub213s%XW", { XM, Vex, EXVexWdq } },
4722 { "(bad)", { XX } },
4723 },
4724
4725 /* PREFIX_VEX_38B6 */
4726 {
4727 { "(bad)", { XX } },
4728 { "(bad)", { XX } },
4729 { "vfmaddsub231p%XW", { XM, Vex, EXx } },
4730 { "(bad)", { XX } },
4731 },
4732
4733 /* PREFIX_VEX_38B7 */
4734 {
4735 { "(bad)", { XX } },
4736 { "(bad)", { XX } },
4737 { "vfmsubadd231p%XW", { XM, Vex, EXx } },
4738 { "(bad)", { XX } },
4739 },
4740
4741 /* PREFIX_VEX_38B8 */
4742 {
4743 { "(bad)", { XX } },
4744 { "(bad)", { XX } },
4745 { "vfmadd231p%XW", { XM, Vex, EXx } },
4746 { "(bad)", { XX } },
4747 },
4748
4749 /* PREFIX_VEX_38B9 */
4750 {
4751 { "(bad)", { XX } },
4752 { "(bad)", { XX } },
4753 { "vfmadd231s%XW", { XM, Vex, EXVexWdq } },
4754 { "(bad)", { XX } },
4755 },
4756
4757 /* PREFIX_VEX_38BA */
4758 {
4759 { "(bad)", { XX } },
4760 { "(bad)", { XX } },
4761 { "vfmsub231p%XW", { XM, Vex, EXx } },
4762 { "(bad)", { XX } },
4763 },
4764
4765 /* PREFIX_VEX_38BB */
4766 {
4767 { "(bad)", { XX } },
4768 { "(bad)", { XX } },
4769 { "vfmsub231s%XW", { XM, Vex, EXVexWdq } },
4770 { "(bad)", { XX } },
4771 },
4772
4773 /* PREFIX_VEX_38BC */
4774 {
4775 { "(bad)", { XX } },
4776 { "(bad)", { XX } },
4777 { "vfnmadd231p%XW", { XM, Vex, EXx } },
4778 { "(bad)", { XX } },
4779 },
4780
4781 /* PREFIX_VEX_38BD */
4782 {
4783 { "(bad)", { XX } },
4784 { "(bad)", { XX } },
4785 { "vfnmadd231s%XW", { XM, Vex, EXVexWdq } },
4786 { "(bad)", { XX } },
4787 },
4788
4789 /* PREFIX_VEX_38BE */
4790 {
4791 { "(bad)", { XX } },
4792 { "(bad)", { XX } },
4793 { "vfnmsub231p%XW", { XM, Vex, EXx } },
4794 { "(bad)", { XX } },
4795 },
4796
4797 /* PREFIX_VEX_38BF */
4798 {
4799 { "(bad)", { XX } },
4800 { "(bad)", { XX } },
4801 { "vfnmsub231s%XW", { XM, Vex, EXVexWdq } },
4802 { "(bad)", { XX } },
4803 },
4804
4805 /* PREFIX_VEX_38DB */
4806 {
4807 { "(bad)", { XX } },
4808 { "(bad)", { XX } },
4809 { VEX_LEN_TABLE (VEX_LEN_38DB_P_2) },
4810 { "(bad)", { XX } },
4811 },
4812
4813 /* PREFIX_VEX_38DC */
4814 {
4815 { "(bad)", { XX } },
4816 { "(bad)", { XX } },
4817 { VEX_LEN_TABLE (VEX_LEN_38DC_P_2) },
4818 { "(bad)", { XX } },
4819 },
4820
4821 /* PREFIX_VEX_38DD */
4822 {
4823 { "(bad)", { XX } },
4824 { "(bad)", { XX } },
4825 { VEX_LEN_TABLE (VEX_LEN_38DD_P_2) },
4826 { "(bad)", { XX } },
4827 },
4828
4829 /* PREFIX_VEX_38DE */
4830 {
4831 { "(bad)", { XX } },
4832 { "(bad)", { XX } },
4833 { VEX_LEN_TABLE (VEX_LEN_38DE_P_2) },
4834 { "(bad)", { XX } },
4835 },
4836
4837 /* PREFIX_VEX_38DF */
4838 {
4839 { "(bad)", { XX } },
4840 { "(bad)", { XX } },
4841 { VEX_LEN_TABLE (VEX_LEN_38DF_P_2) },
4842 { "(bad)", { XX } },
4843 },
4844
4845 /* PREFIX_VEX_3A04 */
4846 {
4847 { "(bad)", { XX } },
4848 { "(bad)", { XX } },
4849 { "vpermilps", { XM, EXx, Ib } },
4850 { "(bad)", { XX } },
4851 },
4852
4853 /* PREFIX_VEX_3A05 */
4854 {
4855 { "(bad)", { XX } },
4856 { "(bad)", { XX } },
4857 { "vpermilpd", { XM, EXx, Ib } },
4858 { "(bad)", { XX } },
4859 },
4860
4861 /* PREFIX_VEX_3A06 */
4862 {
4863 { "(bad)", { XX } },
4864 { "(bad)", { XX } },
4865 { VEX_LEN_TABLE (VEX_LEN_3A06_P_2) },
4866 { "(bad)", { XX } },
4867 },
4868
4869 /* PREFIX_VEX_3A08 */
4870 {
4871 { "(bad)", { XX } },
4872 { "(bad)", { XX } },
4873 { "vroundps", { XM, EXx, Ib } },
4874 { "(bad)", { XX } },
4875 },
4876
4877 /* PREFIX_VEX_3A09 */
4878 {
4879 { "(bad)", { XX } },
4880 { "(bad)", { XX } },
4881 { "vroundpd", { XM, EXx, Ib } },
4882 { "(bad)", { XX } },
4883 },
4884
4885 /* PREFIX_VEX_3A0A */
4886 {
4887 { "(bad)", { XX } },
4888 { "(bad)", { XX } },
4889 { VEX_LEN_TABLE (VEX_LEN_3A0A_P_2) },
4890 { "(bad)", { XX } },
4891 },
4892
4893 /* PREFIX_VEX_3A0B */
4894 {
4895 { "(bad)", { XX } },
4896 { "(bad)", { XX } },
4897 { VEX_LEN_TABLE (VEX_LEN_3A0B_P_2) },
4898 { "(bad)", { XX } },
4899 },
4900
4901 /* PREFIX_VEX_3A0C */
4902 {
4903 { "(bad)", { XX } },
4904 { "(bad)", { XX } },
4905 { "vblendps", { XM, Vex, EXx, Ib } },
4906 { "(bad)", { XX } },
4907 },
4908
4909 /* PREFIX_VEX_3A0D */
4910 {
4911 { "(bad)", { XX } },
4912 { "(bad)", { XX } },
4913 { "vblendpd", { XM, Vex, EXx, Ib } },
4914 { "(bad)", { XX } },
4915 },
4916
4917 /* PREFIX_VEX_3A0E */
4918 {
4919 { "(bad)", { XX } },
4920 { "(bad)", { XX } },
4921 { VEX_LEN_TABLE (VEX_LEN_3A0E_P_2) },
4922 { "(bad)", { XX } },
4923 },
4924
4925 /* PREFIX_VEX_3A0F */
4926 {
4927 { "(bad)", { XX } },
4928 { "(bad)", { XX } },
4929 { VEX_LEN_TABLE (VEX_LEN_3A0F_P_2) },
4930 { "(bad)", { XX } },
4931 },
4932
4933 /* PREFIX_VEX_3A14 */
4934 {
4935 { "(bad)", { XX } },
4936 { "(bad)", { XX } },
4937 { VEX_LEN_TABLE (VEX_LEN_3A14_P_2) },
4938 { "(bad)", { XX } },
4939 },
4940
4941 /* PREFIX_VEX_3A15 */
4942 {
4943 { "(bad)", { XX } },
4944 { "(bad)", { XX } },
4945 { VEX_LEN_TABLE (VEX_LEN_3A15_P_2) },
4946 { "(bad)", { XX } },
4947 },
4948
4949 /* PREFIX_VEX_3A16 */
4950 {
4951 { "(bad)", { XX } },
4952 { "(bad)", { XX } },
4953 { VEX_LEN_TABLE (VEX_LEN_3A16_P_2) },
4954 { "(bad)", { XX } },
4955 },
4956
4957 /* PREFIX_VEX_3A17 */
4958 {
4959 { "(bad)", { XX } },
4960 { "(bad)", { XX } },
4961 { VEX_LEN_TABLE (VEX_LEN_3A17_P_2) },
4962 { "(bad)", { XX } },
4963 },
4964
4965 /* PREFIX_VEX_3A18 */
4966 {
4967 { "(bad)", { XX } },
4968 { "(bad)", { XX } },
4969 { VEX_LEN_TABLE (VEX_LEN_3A18_P_2) },
4970 { "(bad)", { XX } },
4971 },
4972
4973 /* PREFIX_VEX_3A19 */
4974 {
4975 { "(bad)", { XX } },
4976 { "(bad)", { XX } },
4977 { VEX_LEN_TABLE (VEX_LEN_3A19_P_2) },
4978 { "(bad)", { XX } },
4979 },
4980
4981 /* PREFIX_VEX_3A20 */
4982 {
4983 { "(bad)", { XX } },
4984 { "(bad)", { XX } },
4985 { VEX_LEN_TABLE (VEX_LEN_3A20_P_2) },
4986 { "(bad)", { XX } },
4987 },
4988
4989 /* PREFIX_VEX_3A21 */
4990 {
4991 { "(bad)", { XX } },
4992 { "(bad)", { XX } },
4993 { VEX_LEN_TABLE (VEX_LEN_3A21_P_2) },
4994 { "(bad)", { XX } },
4995 },
4996
4997 /* PREFIX_VEX_3A22 */
4998 {
4999 { "(bad)", { XX } },
5000 { "(bad)", { XX } },
5001 { VEX_LEN_TABLE (VEX_LEN_3A22_P_2) },
5002 { "(bad)", { XX } },
5003 },
5004
5005 /* PREFIX_VEX_3A40 */
5006 {
5007 { "(bad)", { XX } },
5008 { "(bad)", { XX } },
5009 { "vdpps", { XM, Vex, EXx, Ib } },
5010 { "(bad)", { XX } },
5011 },
5012
5013 /* PREFIX_VEX_3A41 */
5014 {
5015 { "(bad)", { XX } },
5016 { "(bad)", { XX } },
5017 { VEX_LEN_TABLE (VEX_LEN_3A41_P_2) },
5018 { "(bad)", { XX } },
5019 },
5020
5021 /* PREFIX_VEX_3A42 */
5022 {
5023 { "(bad)", { XX } },
5024 { "(bad)", { XX } },
5025 { VEX_LEN_TABLE (VEX_LEN_3A42_P_2) },
5026 { "(bad)", { XX } },
5027 },
5028
5029 /* PREFIX_VEX_3A4A */
5030 {
5031 { "(bad)", { XX } },
5032 { "(bad)", { XX } },
5033 { "vblendvps", { XM, Vex, EXx, XMVexI4 } },
5034 { "(bad)", { XX } },
5035 },
5036
5037 /* PREFIX_VEX_3A4B */
5038 {
5039 { "(bad)", { XX } },
5040 { "(bad)", { XX } },
5041 { "vblendvpd", { XM, Vex, EXx, XMVexI4 } },
5042 { "(bad)", { XX } },
5043 },
5044
5045 /* PREFIX_VEX_3A4C */
5046 {
5047 { "(bad)", { XX } },
5048 { "(bad)", { XX } },
5049 { VEX_LEN_TABLE (VEX_LEN_3A4C_P_2) },
5050 { "(bad)", { XX } },
5051 },
5052
5053 /* PREFIX_VEX_3A60 */
5054 {
5055 { "(bad)", { XX } },
5056 { "(bad)", { XX } },
5057 { VEX_LEN_TABLE (VEX_LEN_3A60_P_2) },
5058 { "(bad)", { XX } },
5059 },
5060
5061 /* PREFIX_VEX_3A61 */
5062 {
5063 { "(bad)", { XX } },
5064 { "(bad)", { XX } },
5065 { VEX_LEN_TABLE (VEX_LEN_3A61_P_2) },
5066 { "(bad)", { XX } },
5067 },
5068
5069 /* PREFIX_VEX_3A62 */
5070 {
5071 { "(bad)", { XX } },
5072 { "(bad)", { XX } },
5073 { VEX_LEN_TABLE (VEX_LEN_3A62_P_2) },
5074 { "(bad)", { XX } },
5075 },
5076
5077 /* PREFIX_VEX_3A63 */
5078 {
5079 { "(bad)", { XX } },
5080 { "(bad)", { XX } },
5081 { VEX_LEN_TABLE (VEX_LEN_3A63_P_2) },
5082 { "(bad)", { XX } },
5083 },
5084
5085 /* PREFIX_VEX_3ADF */
5086 {
5087 { "(bad)", { XX } },
5088 { "(bad)", { XX } },
5089 { VEX_LEN_TABLE (VEX_LEN_3ADF_P_2) },
5090 { "(bad)", { XX } },
5091 },
5092 };
5093
5094 static const struct dis386 x86_64_table[][2] = {
5095 /* X86_64_06 */
5096 {
5097 { "push{T|}", { es } },
5098 { "(bad)", { XX } },
5099 },
5100
5101 /* X86_64_07 */
5102 {
5103 { "pop{T|}", { es } },
5104 { "(bad)", { XX } },
5105 },
5106
5107 /* X86_64_0D */
5108 {
5109 { "push{T|}", { cs } },
5110 { "(bad)", { XX } },
5111 },
5112
5113 /* X86_64_16 */
5114 {
5115 { "push{T|}", { ss } },
5116 { "(bad)", { XX } },
5117 },
5118
5119 /* X86_64_17 */
5120 {
5121 { "pop{T|}", { ss } },
5122 { "(bad)", { XX } },
5123 },
5124
5125 /* X86_64_1E */
5126 {
5127 { "push{T|}", { ds } },
5128 { "(bad)", { XX } },
5129 },
5130
5131 /* X86_64_1F */
5132 {
5133 { "pop{T|}", { ds } },
5134 { "(bad)", { XX } },
5135 },
5136
5137 /* X86_64_27 */
5138 {
5139 { "daa", { XX } },
5140 { "(bad)", { XX } },
5141 },
5142
5143 /* X86_64_2F */
5144 {
5145 { "das", { XX } },
5146 { "(bad)", { XX } },
5147 },
5148
5149 /* X86_64_37 */
5150 {
5151 { "aaa", { XX } },
5152 { "(bad)", { XX } },
5153 },
5154
5155 /* X86_64_3F */
5156 {
5157 { "aas", { XX } },
5158 { "(bad)", { XX } },
5159 },
5160
5161 /* X86_64_60 */
5162 {
5163 { "pusha{P|}", { XX } },
5164 { "(bad)", { XX } },
5165 },
5166
5167 /* X86_64_61 */
5168 {
5169 { "popa{P|}", { XX } },
5170 { "(bad)", { XX } },
5171 },
5172
5173 /* X86_64_62 */
5174 {
5175 { MOD_TABLE (MOD_62_32BIT) },
5176 { "(bad)", { XX } },
5177 },
5178
5179 /* X86_64_63 */
5180 {
5181 { "arpl", { Ew, Gw } },
5182 { "movs{lq|xd}", { Gv, Ed } },
5183 },
5184
5185 /* X86_64_6D */
5186 {
5187 { "ins{R|}", { Yzr, indirDX } },
5188 { "ins{G|}", { Yzr, indirDX } },
5189 },
5190
5191 /* X86_64_6F */
5192 {
5193 { "outs{R|}", { indirDXr, Xz } },
5194 { "outs{G|}", { indirDXr, Xz } },
5195 },
5196
5197 /* X86_64_9A */
5198 {
5199 { "Jcall{T|}", { Ap } },
5200 { "(bad)", { XX } },
5201 },
5202
5203 /* X86_64_C4 */
5204 {
5205 { MOD_TABLE (MOD_C4_32BIT) },
5206 { VEX_C4_TABLE (VEX_0F) },
5207 },
5208
5209 /* X86_64_C5 */
5210 {
5211 { MOD_TABLE (MOD_C5_32BIT) },
5212 { VEX_C5_TABLE (VEX_0F) },
5213 },
5214
5215 /* X86_64_CE */
5216 {
5217 { "into", { XX } },
5218 { "(bad)", { XX } },
5219 },
5220
5221 /* X86_64_D4 */
5222 {
5223 { "aam", { sIb } },
5224 { "(bad)", { XX } },
5225 },
5226
5227 /* X86_64_D5 */
5228 {
5229 { "aad", { sIb } },
5230 { "(bad)", { XX } },
5231 },
5232
5233 /* X86_64_EA */
5234 {
5235 { "Jjmp{T|}", { Ap } },
5236 { "(bad)", { XX } },
5237 },
5238
5239 /* X86_64_0F01_REG_0 */
5240 {
5241 { "sgdt{Q|IQ}", { M } },
5242 { "sgdt", { M } },
5243 },
5244
5245 /* X86_64_0F01_REG_1 */
5246 {
5247 { "sidt{Q|IQ}", { M } },
5248 { "sidt", { M } },
5249 },
5250
5251 /* X86_64_0F01_REG_2 */
5252 {
5253 { "lgdt{Q|Q}", { M } },
5254 { "lgdt", { M } },
5255 },
5256
5257 /* X86_64_0F01_REG_3 */
5258 {
5259 { "lidt{Q|Q}", { M } },
5260 { "lidt", { M } },
5261 },
5262 };
5263
5264 static const struct dis386 three_byte_table[][256] = {
5265 /* THREE_BYTE_0F24 */
5266 {
5267 /* 00 */
5268 { "fmaddps", { { OP_DREX4, q_mode } } },
5269 { "fmaddpd", { { OP_DREX4, q_mode } } },
5270 { "fmaddss", { { OP_DREX4, w_mode } } },
5271 { "fmaddsd", { { OP_DREX4, d_mode } } },
5272 { "fmaddps", { { OP_DREX4, DREX_OC1 + q_mode } } },
5273 { "fmaddpd", { { OP_DREX4, DREX_OC1 + q_mode } } },
5274 { "fmaddss", { { OP_DREX4, DREX_OC1 + w_mode } } },
5275 { "fmaddsd", { { OP_DREX4, DREX_OC1 + d_mode } } },
5276 /* 08 */
5277 { "fmsubps", { { OP_DREX4, q_mode } } },
5278 { "fmsubpd", { { OP_DREX4, q_mode } } },
5279 { "fmsubss", { { OP_DREX4, w_mode } } },
5280 { "fmsubsd", { { OP_DREX4, d_mode } } },
5281 { "fmsubps", { { OP_DREX4, DREX_OC1 + q_mode } } },
5282 { "fmsubpd", { { OP_DREX4, DREX_OC1 + q_mode } } },
5283 { "fmsubss", { { OP_DREX4, DREX_OC1 + w_mode } } },
5284 { "fmsubsd", { { OP_DREX4, DREX_OC1 + d_mode } } },
5285 /* 10 */
5286 { "fnmaddps", { { OP_DREX4, q_mode } } },
5287 { "fnmaddpd", { { OP_DREX4, q_mode } } },
5288 { "fnmaddss", { { OP_DREX4, w_mode } } },
5289 { "fnmaddsd", { { OP_DREX4, d_mode } } },
5290 { "fnmaddps", { { OP_DREX4, DREX_OC1 + q_mode } } },
5291 { "fnmaddpd", { { OP_DREX4, DREX_OC1 + q_mode } } },
5292 { "fnmaddss", { { OP_DREX4, DREX_OC1 + w_mode } } },
5293 { "fnmaddsd", { { OP_DREX4, DREX_OC1 + d_mode } } },
5294 /* 18 */
5295 { "fnmsubps", { { OP_DREX4, q_mode } } },
5296 { "fnmsubpd", { { OP_DREX4, q_mode } } },
5297 { "fnmsubss", { { OP_DREX4, w_mode } } },
5298 { "fnmsubsd", { { OP_DREX4, d_mode } } },
5299 { "fnmsubps", { { OP_DREX4, DREX_OC1 + q_mode } } },
5300 { "fnmsubpd", { { OP_DREX4, DREX_OC1 + q_mode } } },
5301 { "fnmsubss", { { OP_DREX4, DREX_OC1 + w_mode } } },
5302 { "fnmsubsd", { { OP_DREX4, DREX_OC1 + d_mode } } },
5303 /* 20 */
5304 { "permps", { { OP_DREX4, q_mode } } },
5305 { "permpd", { { OP_DREX4, q_mode } } },
5306 { "pcmov", { { OP_DREX4, q_mode } } },
5307 { "pperm", { { OP_DREX4, q_mode } } },
5308 { "permps", { { OP_DREX4, DREX_OC1 + q_mode } } },
5309 { "permpd", { { OP_DREX4, DREX_OC1 + q_mode } } },
5310 { "pcmov", { { OP_DREX4, DREX_OC1 + w_mode } } },
5311 { "pperm", { { OP_DREX4, DREX_OC1 + d_mode } } },
5312 /* 28 */
5313 { "(bad)", { XX } },
5314 { "(bad)", { XX } },
5315 { "(bad)", { XX } },
5316 { "(bad)", { XX } },
5317 { "(bad)", { XX } },
5318 { "(bad)", { XX } },
5319 { "(bad)", { XX } },
5320 { "(bad)", { XX } },
5321 /* 30 */
5322 { "(bad)", { XX } },
5323 { "(bad)", { XX } },
5324 { "(bad)", { XX } },
5325 { "(bad)", { XX } },
5326 { "(bad)", { XX } },
5327 { "(bad)", { XX } },
5328 { "(bad)", { XX } },
5329 { "(bad)", { XX } },
5330 /* 38 */
5331 { "(bad)", { XX } },
5332 { "(bad)", { XX } },
5333 { "(bad)", { XX } },
5334 { "(bad)", { XX } },
5335 { "(bad)", { XX } },
5336 { "(bad)", { XX } },
5337 { "(bad)", { XX } },
5338 { "(bad)", { XX } },
5339 /* 40 */
5340 { "protb", { { OP_DREX3, q_mode } } },
5341 { "protw", { { OP_DREX3, q_mode } } },
5342 { "protd", { { OP_DREX3, q_mode } } },
5343 { "protq", { { OP_DREX3, q_mode } } },
5344 { "pshlb", { { OP_DREX3, q_mode } } },
5345 { "pshlw", { { OP_DREX3, q_mode } } },
5346 { "pshld", { { OP_DREX3, q_mode } } },
5347 { "pshlq", { { OP_DREX3, q_mode } } },
5348 /* 48 */
5349 { "pshab", { { OP_DREX3, q_mode } } },
5350 { "pshaw", { { OP_DREX3, q_mode } } },
5351 { "pshad", { { OP_DREX3, q_mode } } },
5352 { "pshaq", { { OP_DREX3, q_mode } } },
5353 { "(bad)", { XX } },
5354 { "(bad)", { XX } },
5355 { "(bad)", { XX } },
5356 { "(bad)", { XX } },
5357 /* 50 */
5358 { "(bad)", { XX } },
5359 { "(bad)", { XX } },
5360 { "(bad)", { XX } },
5361 { "(bad)", { XX } },
5362 { "(bad)", { XX } },
5363 { "(bad)", { XX } },
5364 { "(bad)", { XX } },
5365 { "(bad)", { XX } },
5366 /* 58 */
5367 { "(bad)", { XX } },
5368 { "(bad)", { XX } },
5369 { "(bad)", { XX } },
5370 { "(bad)", { XX } },
5371 { "(bad)", { XX } },
5372 { "(bad)", { XX } },
5373 { "(bad)", { XX } },
5374 { "(bad)", { XX } },
5375 /* 60 */
5376 { "(bad)", { XX } },
5377 { "(bad)", { XX } },
5378 { "(bad)", { XX } },
5379 { "(bad)", { XX } },
5380 { "(bad)", { XX } },
5381 { "(bad)", { XX } },
5382 { "(bad)", { XX } },
5383 { "(bad)", { XX } },
5384 /* 68 */
5385 { "(bad)", { XX } },
5386 { "(bad)", { XX } },
5387 { "(bad)", { XX } },
5388 { "(bad)", { XX } },
5389 { "(bad)", { XX } },
5390 { "(bad)", { XX } },
5391 { "(bad)", { XX } },
5392 { "(bad)", { XX } },
5393 /* 70 */
5394 { "(bad)", { XX } },
5395 { "(bad)", { XX } },
5396 { "(bad)", { XX } },
5397 { "(bad)", { XX } },
5398 { "(bad)", { XX } },
5399 { "(bad)", { XX } },
5400 { "(bad)", { XX } },
5401 { "(bad)", { XX } },
5402 /* 78 */
5403 { "(bad)", { XX } },
5404 { "(bad)", { XX } },
5405 { "(bad)", { XX } },
5406 { "(bad)", { XX } },
5407 { "(bad)", { XX } },
5408 { "(bad)", { XX } },
5409 { "(bad)", { XX } },
5410 { "(bad)", { XX } },
5411 /* 80 */
5412 { "(bad)", { XX } },
5413 { "(bad)", { XX } },
5414 { "(bad)", { XX } },
5415 { "(bad)", { XX } },
5416 { "(bad)", { XX } },
5417 { "pmacssww", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5418 { "pmacsswd", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5419 { "pmacssdql", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5420 /* 88 */
5421 { "(bad)", { XX } },
5422 { "(bad)", { XX } },
5423 { "(bad)", { XX } },
5424 { "(bad)", { XX } },
5425 { "(bad)", { XX } },
5426 { "(bad)", { XX } },
5427 { "pmacssdd", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5428 { "pmacssdqh", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5429 /* 90 */
5430 { "(bad)", { XX } },
5431 { "(bad)", { XX } },
5432 { "(bad)", { XX } },
5433 { "(bad)", { XX } },
5434 { "(bad)", { XX } },
5435 { "pmacsww", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5436 { "pmacswd", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5437 { "pmacsdql", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5438 /* 98 */
5439 { "(bad)", { XX } },
5440 { "(bad)", { XX } },
5441 { "(bad)", { XX } },
5442 { "(bad)", { XX } },
5443 { "(bad)", { XX } },
5444 { "(bad)", { XX } },
5445 { "pmacsdd", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5446 { "pmacsdqh", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5447 /* a0 */
5448 { "(bad)", { XX } },
5449 { "(bad)", { XX } },
5450 { "(bad)", { XX } },
5451 { "(bad)", { XX } },
5452 { "(bad)", { XX } },
5453 { "(bad)", { XX } },
5454 { "pmadcsswd", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5455 { "(bad)", { XX } },
5456 /* a8 */
5457 { "(bad)", { XX } },
5458 { "(bad)", { XX } },
5459 { "(bad)", { XX } },
5460 { "(bad)", { XX } },
5461 { "(bad)", { XX } },
5462 { "(bad)", { XX } },
5463 { "(bad)", { XX } },
5464 { "(bad)", { XX } },
5465 /* b0 */
5466 { "(bad)", { XX } },
5467 { "(bad)", { XX } },
5468 { "(bad)", { XX } },
5469 { "(bad)", { XX } },
5470 { "(bad)", { XX } },
5471 { "(bad)", { XX } },
5472 { "pmadcswd", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5473 { "(bad)", { XX } },
5474 /* b8 */
5475 { "(bad)", { XX } },
5476 { "(bad)", { XX } },
5477 { "(bad)", { XX } },
5478 { "(bad)", { XX } },
5479 { "(bad)", { XX } },
5480 { "(bad)", { XX } },
5481 { "(bad)", { XX } },
5482 { "(bad)", { XX } },
5483 /* c0 */
5484 { "(bad)", { XX } },
5485 { "(bad)", { XX } },
5486 { "(bad)", { XX } },
5487 { "(bad)", { XX } },
5488 { "(bad)", { XX } },
5489 { "(bad)", { XX } },
5490 { "(bad)", { XX } },
5491 { "(bad)", { XX } },
5492 /* c8 */
5493 { "(bad)", { XX } },
5494 { "(bad)", { XX } },
5495 { "(bad)", { XX } },
5496 { "(bad)", { XX } },
5497 { "(bad)", { XX } },
5498 { "(bad)", { XX } },
5499 { "(bad)", { XX } },
5500 { "(bad)", { XX } },
5501 /* d0 */
5502 { "(bad)", { XX } },
5503 { "(bad)", { XX } },
5504 { "(bad)", { XX } },
5505 { "(bad)", { XX } },
5506 { "(bad)", { XX } },
5507 { "(bad)", { XX } },
5508 { "(bad)", { XX } },
5509 { "(bad)", { XX } },
5510 /* d8 */
5511 { "(bad)", { XX } },
5512 { "(bad)", { XX } },
5513 { "(bad)", { XX } },
5514 { "(bad)", { XX } },
5515 { "(bad)", { XX } },
5516 { "(bad)", { XX } },
5517 { "(bad)", { XX } },
5518 { "(bad)", { XX } },
5519 /* e0 */
5520 { "(bad)", { XX } },
5521 { "(bad)", { XX } },
5522 { "(bad)", { XX } },
5523 { "(bad)", { XX } },
5524 { "(bad)", { XX } },
5525 { "(bad)", { XX } },
5526 { "(bad)", { XX } },
5527 { "(bad)", { XX } },
5528 /* e8 */
5529 { "(bad)", { XX } },
5530 { "(bad)", { XX } },
5531 { "(bad)", { XX } },
5532 { "(bad)", { XX } },
5533 { "(bad)", { XX } },
5534 { "(bad)", { XX } },
5535 { "(bad)", { XX } },
5536 { "(bad)", { XX } },
5537 /* f0 */
5538 { "(bad)", { XX } },
5539 { "(bad)", { XX } },
5540 { "(bad)", { XX } },
5541 { "(bad)", { XX } },
5542 { "(bad)", { XX } },
5543 { "(bad)", { XX } },
5544 { "(bad)", { XX } },
5545 { "(bad)", { XX } },
5546 /* f8 */
5547 { "(bad)", { XX } },
5548 { "(bad)", { XX } },
5549 { "(bad)", { XX } },
5550 { "(bad)", { XX } },
5551 { "(bad)", { XX } },
5552 { "(bad)", { XX } },
5553 { "(bad)", { XX } },
5554 { "(bad)", { XX } },
5555 },
5556 /* THREE_BYTE_0F25 */
5557 {
5558 /* 00 */
5559 { "(bad)", { XX } },
5560 { "(bad)", { XX } },
5561 { "(bad)", { XX } },
5562 { "(bad)", { XX } },
5563 { "(bad)", { XX } },
5564 { "(bad)", { XX } },
5565 { "(bad)", { XX } },
5566 { "(bad)", { XX } },
5567 /* 08 */
5568 { "(bad)", { XX } },
5569 { "(bad)", { XX } },
5570 { "(bad)", { XX } },
5571 { "(bad)", { XX } },
5572 { "(bad)", { XX } },
5573 { "(bad)", { XX } },
5574 { "(bad)", { XX } },
5575 { "(bad)", { XX } },
5576 /* 10 */
5577 { "(bad)", { XX } },
5578 { "(bad)", { XX } },
5579 { "(bad)", { XX } },
5580 { "(bad)", { XX } },
5581 { "(bad)", { XX } },
5582 { "(bad)", { XX } },
5583 { "(bad)", { XX } },
5584 { "(bad)", { XX } },
5585 /* 18 */
5586 { "(bad)", { XX } },
5587 { "(bad)", { XX } },
5588 { "(bad)", { XX } },
5589 { "(bad)", { XX } },
5590 { "(bad)", { XX } },
5591 { "(bad)", { XX } },
5592 { "(bad)", { XX } },
5593 { "(bad)", { XX } },
5594 /* 20 */
5595 { "(bad)", { XX } },
5596 { "(bad)", { XX } },
5597 { "(bad)", { XX } },
5598 { "(bad)", { XX } },
5599 { "(bad)", { XX } },
5600 { "(bad)", { XX } },
5601 { "(bad)", { XX } },
5602 { "(bad)", { XX } },
5603 /* 28 */
5604 { "(bad)", { XX } },
5605 { "(bad)", { XX } },
5606 { "(bad)", { XX } },
5607 { "(bad)", { XX } },
5608 { "comps", { { OP_DREX3, q_mode }, { OP_DREX_FCMP, b_mode } } },
5609 { "compd", { { OP_DREX3, q_mode }, { OP_DREX_FCMP, b_mode } } },
5610 { "comss", { { OP_DREX3, w_mode }, { OP_DREX_FCMP, b_mode } } },
5611 { "comsd", { { OP_DREX3, d_mode }, { OP_DREX_FCMP, b_mode } } },
5612 /* 30 */
5613 { "(bad)", { XX } },
5614 { "(bad)", { XX } },
5615 { "(bad)", { XX } },
5616 { "(bad)", { XX } },
5617 { "(bad)", { XX } },
5618 { "(bad)", { XX } },
5619 { "(bad)", { XX } },
5620 { "(bad)", { XX } },
5621 /* 38 */
5622 { "(bad)", { XX } },
5623 { "(bad)", { XX } },
5624 { "(bad)", { XX } },
5625 { "(bad)", { XX } },
5626 { "(bad)", { XX } },
5627 { "(bad)", { XX } },
5628 { "(bad)", { XX } },
5629 { "(bad)", { XX } },
5630 /* 40 */
5631 { "(bad)", { XX } },
5632 { "(bad)", { XX } },
5633 { "(bad)", { XX } },
5634 { "(bad)", { XX } },
5635 { "(bad)", { XX } },
5636 { "(bad)", { XX } },
5637 { "(bad)", { XX } },
5638 { "(bad)", { XX } },
5639 /* 48 */
5640 { "(bad)", { XX } },
5641 { "(bad)", { XX } },
5642 { "(bad)", { XX } },
5643 { "(bad)", { XX } },
5644 { "pcomb", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
5645 { "pcomw", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
5646 { "pcomd", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
5647 { "pcomq", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
5648 /* 50 */
5649 { "(bad)", { XX } },
5650 { "(bad)", { XX } },
5651 { "(bad)", { XX } },
5652 { "(bad)", { XX } },
5653 { "(bad)", { XX } },
5654 { "(bad)", { XX } },
5655 { "(bad)", { XX } },
5656 { "(bad)", { XX } },
5657 /* 58 */
5658 { "(bad)", { XX } },
5659 { "(bad)", { XX } },
5660 { "(bad)", { XX } },
5661 { "(bad)", { XX } },
5662 { "(bad)", { XX } },
5663 { "(bad)", { XX } },
5664 { "(bad)", { XX } },
5665 { "(bad)", { XX } },
5666 /* 60 */
5667 { "(bad)", { XX } },
5668 { "(bad)", { XX } },
5669 { "(bad)", { XX } },
5670 { "(bad)", { XX } },
5671 { "(bad)", { XX } },
5672 { "(bad)", { XX } },
5673 { "(bad)", { XX } },
5674 { "(bad)", { XX } },
5675 /* 68 */
5676 { "(bad)", { XX } },
5677 { "(bad)", { XX } },
5678 { "(bad)", { XX } },
5679 { "(bad)", { XX } },
5680 { "pcomub", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
5681 { "pcomuw", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
5682 { "pcomud", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
5683 { "pcomuq", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
5684 /* 70 */
5685 { "(bad)", { XX } },
5686 { "(bad)", { XX } },
5687 { "(bad)", { XX } },
5688 { "(bad)", { XX } },
5689 { "(bad)", { XX } },
5690 { "(bad)", { XX } },
5691 { "(bad)", { XX } },
5692 { "(bad)", { XX } },
5693 /* 78 */
5694 { "(bad)", { XX } },
5695 { "(bad)", { XX } },
5696 { "(bad)", { XX } },
5697 { "(bad)", { XX } },
5698 { "(bad)", { XX } },
5699 { "(bad)", { XX } },
5700 { "(bad)", { XX } },
5701 { "(bad)", { XX } },
5702 /* 80 */
5703 { "(bad)", { XX } },
5704 { "(bad)", { XX } },
5705 { "(bad)", { XX } },
5706 { "(bad)", { XX } },
5707 { "(bad)", { XX } },
5708 { "(bad)", { XX } },
5709 { "(bad)", { XX } },
5710 { "(bad)", { XX } },
5711 /* 88 */
5712 { "(bad)", { XX } },
5713 { "(bad)", { XX } },
5714 { "(bad)", { XX } },
5715 { "(bad)", { XX } },
5716 { "(bad)", { XX } },
5717 { "(bad)", { XX } },
5718 { "(bad)", { XX } },
5719 { "(bad)", { XX } },
5720 /* 90 */
5721 { "(bad)", { XX } },
5722 { "(bad)", { XX } },
5723 { "(bad)", { XX } },
5724 { "(bad)", { XX } },
5725 { "(bad)", { XX } },
5726 { "(bad)", { XX } },
5727 { "(bad)", { XX } },
5728 { "(bad)", { XX } },
5729 /* 98 */
5730 { "(bad)", { XX } },
5731 { "(bad)", { XX } },
5732 { "(bad)", { XX } },
5733 { "(bad)", { XX } },
5734 { "(bad)", { XX } },
5735 { "(bad)", { XX } },
5736 { "(bad)", { XX } },
5737 { "(bad)", { XX } },
5738 /* a0 */
5739 { "(bad)", { XX } },
5740 { "(bad)", { XX } },
5741 { "(bad)", { XX } },
5742 { "(bad)", { XX } },
5743 { "(bad)", { XX } },
5744 { "(bad)", { XX } },
5745 { "(bad)", { XX } },
5746 { "(bad)", { XX } },
5747 /* a8 */
5748 { "(bad)", { XX } },
5749 { "(bad)", { XX } },
5750 { "(bad)", { XX } },
5751 { "(bad)", { XX } },
5752 { "(bad)", { XX } },
5753 { "(bad)", { XX } },
5754 { "(bad)", { XX } },
5755 { "(bad)", { XX } },
5756 /* b0 */
5757 { "(bad)", { XX } },
5758 { "(bad)", { XX } },
5759 { "(bad)", { XX } },
5760 { "(bad)", { XX } },
5761 { "(bad)", { XX } },
5762 { "(bad)", { XX } },
5763 { "(bad)", { XX } },
5764 { "(bad)", { XX } },
5765 /* b8 */
5766 { "(bad)", { XX } },
5767 { "(bad)", { XX } },
5768 { "(bad)", { XX } },
5769 { "(bad)", { XX } },
5770 { "(bad)", { XX } },
5771 { "(bad)", { XX } },
5772 { "(bad)", { XX } },
5773 { "(bad)", { XX } },
5774 /* c0 */
5775 { "(bad)", { XX } },
5776 { "(bad)", { XX } },
5777 { "(bad)", { XX } },
5778 { "(bad)", { XX } },
5779 { "(bad)", { XX } },
5780 { "(bad)", { XX } },
5781 { "(bad)", { XX } },
5782 { "(bad)", { XX } },
5783 /* c8 */
5784 { "(bad)", { XX } },
5785 { "(bad)", { XX } },
5786 { "(bad)", { XX } },
5787 { "(bad)", { XX } },
5788 { "(bad)", { XX } },
5789 { "(bad)", { XX } },
5790 { "(bad)", { XX } },
5791 { "(bad)", { XX } },
5792 /* d0 */
5793 { "(bad)", { XX } },
5794 { "(bad)", { XX } },
5795 { "(bad)", { XX } },
5796 { "(bad)", { XX } },
5797 { "(bad)", { XX } },
5798 { "(bad)", { XX } },
5799 { "(bad)", { XX } },
5800 { "(bad)", { XX } },
5801 /* d8 */
5802 { "(bad)", { XX } },
5803 { "(bad)", { XX } },
5804 { "(bad)", { XX } },
5805 { "(bad)", { XX } },
5806 { "(bad)", { XX } },
5807 { "(bad)", { XX } },
5808 { "(bad)", { XX } },
5809 { "(bad)", { XX } },
5810 /* e0 */
5811 { "(bad)", { XX } },
5812 { "(bad)", { XX } },
5813 { "(bad)", { XX } },
5814 { "(bad)", { XX } },
5815 { "(bad)", { XX } },
5816 { "(bad)", { XX } },
5817 { "(bad)", { XX } },
5818 { "(bad)", { XX } },
5819 /* e8 */
5820 { "(bad)", { XX } },
5821 { "(bad)", { XX } },
5822 { "(bad)", { XX } },
5823 { "(bad)", { XX } },
5824 { "(bad)", { XX } },
5825 { "(bad)", { XX } },
5826 { "(bad)", { XX } },
5827 { "(bad)", { XX } },
5828 /* f0 */
5829 { "(bad)", { XX } },
5830 { "(bad)", { XX } },
5831 { "(bad)", { XX } },
5832 { "(bad)", { XX } },
5833 { "(bad)", { XX } },
5834 { "(bad)", { XX } },
5835 { "(bad)", { XX } },
5836 { "(bad)", { XX } },
5837 /* f8 */
5838 { "(bad)", { XX } },
5839 { "(bad)", { XX } },
5840 { "(bad)", { XX } },
5841 { "(bad)", { XX } },
5842 { "(bad)", { XX } },
5843 { "(bad)", { XX } },
5844 { "(bad)", { XX } },
5845 { "(bad)", { XX } },
5846 },
5847 /* THREE_BYTE_0F38 */
5848 {
5849 /* 00 */
5850 { "pshufb", { MX, EM } },
5851 { "phaddw", { MX, EM } },
5852 { "phaddd", { MX, EM } },
5853 { "phaddsw", { MX, EM } },
5854 { "pmaddubsw", { MX, EM } },
5855 { "phsubw", { MX, EM } },
5856 { "phsubd", { MX, EM } },
5857 { "phsubsw", { MX, EM } },
5858 /* 08 */
5859 { "psignb", { MX, EM } },
5860 { "psignw", { MX, EM } },
5861 { "psignd", { MX, EM } },
5862 { "pmulhrsw", { MX, EM } },
5863 { "(bad)", { XX } },
5864 { "(bad)", { XX } },
5865 { "(bad)", { XX } },
5866 { "(bad)", { XX } },
5867 /* 10 */
5868 { PREFIX_TABLE (PREFIX_0F3810) },
5869 { "(bad)", { XX } },
5870 { "(bad)", { XX } },
5871 { "(bad)", { XX } },
5872 { PREFIX_TABLE (PREFIX_0F3814) },
5873 { PREFIX_TABLE (PREFIX_0F3815) },
5874 { "(bad)", { XX } },
5875 { PREFIX_TABLE (PREFIX_0F3817) },
5876 /* 18 */
5877 { "(bad)", { XX } },
5878 { "(bad)", { XX } },
5879 { "(bad)", { XX } },
5880 { "(bad)", { XX } },
5881 { "pabsb", { MX, EM } },
5882 { "pabsw", { MX, EM } },
5883 { "pabsd", { MX, EM } },
5884 { "(bad)", { XX } },
5885 /* 20 */
5886 { PREFIX_TABLE (PREFIX_0F3820) },
5887 { PREFIX_TABLE (PREFIX_0F3821) },
5888 { PREFIX_TABLE (PREFIX_0F3822) },
5889 { PREFIX_TABLE (PREFIX_0F3823) },
5890 { PREFIX_TABLE (PREFIX_0F3824) },
5891 { PREFIX_TABLE (PREFIX_0F3825) },
5892 { "(bad)", { XX } },
5893 { "(bad)", { XX } },
5894 /* 28 */
5895 { PREFIX_TABLE (PREFIX_0F3828) },
5896 { PREFIX_TABLE (PREFIX_0F3829) },
5897 { PREFIX_TABLE (PREFIX_0F382A) },
5898 { PREFIX_TABLE (PREFIX_0F382B) },
5899 { "(bad)", { XX } },
5900 { "(bad)", { XX } },
5901 { "(bad)", { XX } },
5902 { "(bad)", { XX } },
5903 /* 30 */
5904 { PREFIX_TABLE (PREFIX_0F3830) },
5905 { PREFIX_TABLE (PREFIX_0F3831) },
5906 { PREFIX_TABLE (PREFIX_0F3832) },
5907 { PREFIX_TABLE (PREFIX_0F3833) },
5908 { PREFIX_TABLE (PREFIX_0F3834) },
5909 { PREFIX_TABLE (PREFIX_0F3835) },
5910 { "(bad)", { XX } },
5911 { PREFIX_TABLE (PREFIX_0F3837) },
5912 /* 38 */
5913 { PREFIX_TABLE (PREFIX_0F3838) },
5914 { PREFIX_TABLE (PREFIX_0F3839) },
5915 { PREFIX_TABLE (PREFIX_0F383A) },
5916 { PREFIX_TABLE (PREFIX_0F383B) },
5917 { PREFIX_TABLE (PREFIX_0F383C) },
5918 { PREFIX_TABLE (PREFIX_0F383D) },
5919 { PREFIX_TABLE (PREFIX_0F383E) },
5920 { PREFIX_TABLE (PREFIX_0F383F) },
5921 /* 40 */
5922 { PREFIX_TABLE (PREFIX_0F3840) },
5923 { PREFIX_TABLE (PREFIX_0F3841) },
5924 { "(bad)", { XX } },
5925 { "(bad)", { XX } },
5926 { "(bad)", { XX } },
5927 { "(bad)", { XX } },
5928 { "(bad)", { XX } },
5929 { "(bad)", { XX } },
5930 /* 48 */
5931 { "(bad)", { XX } },
5932 { "(bad)", { XX } },
5933 { "(bad)", { XX } },
5934 { "(bad)", { XX } },
5935 { "(bad)", { XX } },
5936 { "(bad)", { XX } },
5937 { "(bad)", { XX } },
5938 { "(bad)", { XX } },
5939 /* 50 */
5940 { "(bad)", { XX } },
5941 { "(bad)", { XX } },
5942 { "(bad)", { XX } },
5943 { "(bad)", { XX } },
5944 { "(bad)", { XX } },
5945 { "(bad)", { XX } },
5946 { "(bad)", { XX } },
5947 { "(bad)", { XX } },
5948 /* 58 */
5949 { "(bad)", { XX } },
5950 { "(bad)", { XX } },
5951 { "(bad)", { XX } },
5952 { "(bad)", { XX } },
5953 { "(bad)", { XX } },
5954 { "(bad)", { XX } },
5955 { "(bad)", { XX } },
5956 { "(bad)", { XX } },
5957 /* 60 */
5958 { "(bad)", { XX } },
5959 { "(bad)", { XX } },
5960 { "(bad)", { XX } },
5961 { "(bad)", { XX } },
5962 { "(bad)", { XX } },
5963 { "(bad)", { XX } },
5964 { "(bad)", { XX } },
5965 { "(bad)", { XX } },
5966 /* 68 */
5967 { "(bad)", { XX } },
5968 { "(bad)", { XX } },
5969 { "(bad)", { XX } },
5970 { "(bad)", { XX } },
5971 { "(bad)", { XX } },
5972 { "(bad)", { XX } },
5973 { "(bad)", { XX } },
5974 { "(bad)", { XX } },
5975 /* 70 */
5976 { "(bad)", { XX } },
5977 { "(bad)", { XX } },
5978 { "(bad)", { XX } },
5979 { "(bad)", { XX } },
5980 { "(bad)", { XX } },
5981 { "(bad)", { XX } },
5982 { "(bad)", { XX } },
5983 { "(bad)", { XX } },
5984 /* 78 */
5985 { "(bad)", { XX } },
5986 { "(bad)", { XX } },
5987 { "(bad)", { XX } },
5988 { "(bad)", { XX } },
5989 { "(bad)", { XX } },
5990 { "(bad)", { XX } },
5991 { "(bad)", { XX } },
5992 { "(bad)", { XX } },
5993 /* 80 */
5994 { PREFIX_TABLE (PREFIX_0F3880) },
5995 { PREFIX_TABLE (PREFIX_0F3881) },
5996 { "(bad)", { XX } },
5997 { "(bad)", { XX } },
5998 { "(bad)", { XX } },
5999 { "(bad)", { XX } },
6000 { "(bad)", { XX } },
6001 { "(bad)", { XX } },
6002 /* 88 */
6003 { "(bad)", { XX } },
6004 { "(bad)", { XX } },
6005 { "(bad)", { XX } },
6006 { "(bad)", { XX } },
6007 { "(bad)", { XX } },
6008 { "(bad)", { XX } },
6009 { "(bad)", { XX } },
6010 { "(bad)", { XX } },
6011 /* 90 */
6012 { "(bad)", { XX } },
6013 { "(bad)", { XX } },
6014 { "(bad)", { XX } },
6015 { "(bad)", { XX } },
6016 { "(bad)", { XX } },
6017 { "(bad)", { XX } },
6018 { "(bad)", { XX } },
6019 { "(bad)", { XX } },
6020 /* 98 */
6021 { "(bad)", { XX } },
6022 { "(bad)", { XX } },
6023 { "(bad)", { XX } },
6024 { "(bad)", { XX } },
6025 { "(bad)", { XX } },
6026 { "(bad)", { XX } },
6027 { "(bad)", { XX } },
6028 { "(bad)", { XX } },
6029 /* a0 */
6030 { "(bad)", { XX } },
6031 { "(bad)", { XX } },
6032 { "(bad)", { XX } },
6033 { "(bad)", { XX } },
6034 { "(bad)", { XX } },
6035 { "(bad)", { XX } },
6036 { "(bad)", { XX } },
6037 { "(bad)", { XX } },
6038 /* a8 */
6039 { "(bad)", { XX } },
6040 { "(bad)", { XX } },
6041 { "(bad)", { XX } },
6042 { "(bad)", { XX } },
6043 { "(bad)", { XX } },
6044 { "(bad)", { XX } },
6045 { "(bad)", { XX } },
6046 { "(bad)", { XX } },
6047 /* b0 */
6048 { "(bad)", { XX } },
6049 { "(bad)", { XX } },
6050 { "(bad)", { XX } },
6051 { "(bad)", { XX } },
6052 { "(bad)", { XX } },
6053 { "(bad)", { XX } },
6054 { "(bad)", { XX } },
6055 { "(bad)", { XX } },
6056 /* b8 */
6057 { "(bad)", { XX } },
6058 { "(bad)", { XX } },
6059 { "(bad)", { XX } },
6060 { "(bad)", { XX } },
6061 { "(bad)", { XX } },
6062 { "(bad)", { XX } },
6063 { "(bad)", { XX } },
6064 { "(bad)", { XX } },
6065 /* c0 */
6066 { "(bad)", { XX } },
6067 { "(bad)", { XX } },
6068 { "(bad)", { XX } },
6069 { "(bad)", { XX } },
6070 { "(bad)", { XX } },
6071 { "(bad)", { XX } },
6072 { "(bad)", { XX } },
6073 { "(bad)", { XX } },
6074 /* c8 */
6075 { "(bad)", { XX } },
6076 { "(bad)", { XX } },
6077 { "(bad)", { XX } },
6078 { "(bad)", { XX } },
6079 { "(bad)", { XX } },
6080 { "(bad)", { XX } },
6081 { "(bad)", { XX } },
6082 { "(bad)", { XX } },
6083 /* d0 */
6084 { "(bad)", { XX } },
6085 { "(bad)", { XX } },
6086 { "(bad)", { XX } },
6087 { "(bad)", { XX } },
6088 { "(bad)", { XX } },
6089 { "(bad)", { XX } },
6090 { "(bad)", { XX } },
6091 { "(bad)", { XX } },
6092 /* d8 */
6093 { "(bad)", { XX } },
6094 { "(bad)", { XX } },
6095 { "(bad)", { XX } },
6096 { PREFIX_TABLE (PREFIX_0F38DB) },
6097 { PREFIX_TABLE (PREFIX_0F38DC) },
6098 { PREFIX_TABLE (PREFIX_0F38DD) },
6099 { PREFIX_TABLE (PREFIX_0F38DE) },
6100 { PREFIX_TABLE (PREFIX_0F38DF) },
6101 /* e0 */
6102 { "(bad)", { XX } },
6103 { "(bad)", { XX } },
6104 { "(bad)", { XX } },
6105 { "(bad)", { XX } },
6106 { "(bad)", { XX } },
6107 { "(bad)", { XX } },
6108 { "(bad)", { XX } },
6109 { "(bad)", { XX } },
6110 /* e8 */
6111 { "(bad)", { XX } },
6112 { "(bad)", { XX } },
6113 { "(bad)", { XX } },
6114 { "(bad)", { XX } },
6115 { "(bad)", { XX } },
6116 { "(bad)", { XX } },
6117 { "(bad)", { XX } },
6118 { "(bad)", { XX } },
6119 /* f0 */
6120 { PREFIX_TABLE (PREFIX_0F38F0) },
6121 { PREFIX_TABLE (PREFIX_0F38F1) },
6122 { "(bad)", { XX } },
6123 { "(bad)", { XX } },
6124 { "(bad)", { XX } },
6125 { "(bad)", { XX } },
6126 { "(bad)", { XX } },
6127 { "(bad)", { XX } },
6128 /* f8 */
6129 { "(bad)", { XX } },
6130 { "(bad)", { XX } },
6131 { "(bad)", { XX } },
6132 { "(bad)", { XX } },
6133 { "(bad)", { XX } },
6134 { "(bad)", { XX } },
6135 { "(bad)", { XX } },
6136 { "(bad)", { XX } },
6137 },
6138 /* THREE_BYTE_0F3A */
6139 {
6140 /* 00 */
6141 { "(bad)", { XX } },
6142 { "(bad)", { XX } },
6143 { "(bad)", { XX } },
6144 { "(bad)", { XX } },
6145 { "(bad)", { XX } },
6146 { "(bad)", { XX } },
6147 { "(bad)", { XX } },
6148 { "(bad)", { XX } },
6149 /* 08 */
6150 { PREFIX_TABLE (PREFIX_0F3A08) },
6151 { PREFIX_TABLE (PREFIX_0F3A09) },
6152 { PREFIX_TABLE (PREFIX_0F3A0A) },
6153 { PREFIX_TABLE (PREFIX_0F3A0B) },
6154 { PREFIX_TABLE (PREFIX_0F3A0C) },
6155 { PREFIX_TABLE (PREFIX_0F3A0D) },
6156 { PREFIX_TABLE (PREFIX_0F3A0E) },
6157 { "palignr", { MX, EM, Ib } },
6158 /* 10 */
6159 { "(bad)", { XX } },
6160 { "(bad)", { XX } },
6161 { "(bad)", { XX } },
6162 { "(bad)", { XX } },
6163 { PREFIX_TABLE (PREFIX_0F3A14) },
6164 { PREFIX_TABLE (PREFIX_0F3A15) },
6165 { PREFIX_TABLE (PREFIX_0F3A16) },
6166 { PREFIX_TABLE (PREFIX_0F3A17) },
6167 /* 18 */
6168 { "(bad)", { XX } },
6169 { "(bad)", { XX } },
6170 { "(bad)", { XX } },
6171 { "(bad)", { XX } },
6172 { "(bad)", { XX } },
6173 { "(bad)", { XX } },
6174 { "(bad)", { XX } },
6175 { "(bad)", { XX } },
6176 /* 20 */
6177 { PREFIX_TABLE (PREFIX_0F3A20) },
6178 { PREFIX_TABLE (PREFIX_0F3A21) },
6179 { PREFIX_TABLE (PREFIX_0F3A22) },
6180 { "(bad)", { XX } },
6181 { "(bad)", { XX } },
6182 { "(bad)", { XX } },
6183 { "(bad)", { XX } },
6184 { "(bad)", { XX } },
6185 /* 28 */
6186 { "(bad)", { XX } },
6187 { "(bad)", { XX } },
6188 { "(bad)", { XX } },
6189 { "(bad)", { XX } },
6190 { "(bad)", { XX } },
6191 { "(bad)", { XX } },
6192 { "(bad)", { XX } },
6193 { "(bad)", { XX } },
6194 /* 30 */
6195 { "(bad)", { XX } },
6196 { "(bad)", { XX } },
6197 { "(bad)", { XX } },
6198 { "(bad)", { XX } },
6199 { "(bad)", { XX } },
6200 { "(bad)", { XX } },
6201 { "(bad)", { XX } },
6202 { "(bad)", { XX } },
6203 /* 38 */
6204 { "(bad)", { XX } },
6205 { "(bad)", { XX } },
6206 { "(bad)", { XX } },
6207 { "(bad)", { XX } },
6208 { "(bad)", { XX } },
6209 { "(bad)", { XX } },
6210 { "(bad)", { XX } },
6211 { "(bad)", { XX } },
6212 /* 40 */
6213 { PREFIX_TABLE (PREFIX_0F3A40) },
6214 { PREFIX_TABLE (PREFIX_0F3A41) },
6215 { PREFIX_TABLE (PREFIX_0F3A42) },
6216 { "(bad)", { XX } },
6217 { PREFIX_TABLE (PREFIX_0F3A44) },
6218 { "(bad)", { XX } },
6219 { "(bad)", { XX } },
6220 { "(bad)", { XX } },
6221 /* 48 */
6222 { "(bad)", { XX } },
6223 { "(bad)", { XX } },
6224 { "(bad)", { XX } },
6225 { "(bad)", { XX } },
6226 { "(bad)", { XX } },
6227 { "(bad)", { XX } },
6228 { "(bad)", { XX } },
6229 { "(bad)", { XX } },
6230 /* 50 */
6231 { "(bad)", { XX } },
6232 { "(bad)", { XX } },
6233 { "(bad)", { XX } },
6234 { "(bad)", { XX } },
6235 { "(bad)", { XX } },
6236 { "(bad)", { XX } },
6237 { "(bad)", { XX } },
6238 { "(bad)", { XX } },
6239 /* 58 */
6240 { "(bad)", { XX } },
6241 { "(bad)", { XX } },
6242 { "(bad)", { XX } },
6243 { "(bad)", { XX } },
6244 { "(bad)", { XX } },
6245 { "(bad)", { XX } },
6246 { "(bad)", { XX } },
6247 { "(bad)", { XX } },
6248 /* 60 */
6249 { PREFIX_TABLE (PREFIX_0F3A60) },
6250 { PREFIX_TABLE (PREFIX_0F3A61) },
6251 { PREFIX_TABLE (PREFIX_0F3A62) },
6252 { PREFIX_TABLE (PREFIX_0F3A63) },
6253 { "(bad)", { XX } },
6254 { "(bad)", { XX } },
6255 { "(bad)", { XX } },
6256 { "(bad)", { XX } },
6257 /* 68 */
6258 { "(bad)", { XX } },
6259 { "(bad)", { XX } },
6260 { "(bad)", { XX } },
6261 { "(bad)", { XX } },
6262 { "(bad)", { XX } },
6263 { "(bad)", { XX } },
6264 { "(bad)", { XX } },
6265 { "(bad)", { XX } },
6266 /* 70 */
6267 { "(bad)", { XX } },
6268 { "(bad)", { XX } },
6269 { "(bad)", { XX } },
6270 { "(bad)", { XX } },
6271 { "(bad)", { XX } },
6272 { "(bad)", { XX } },
6273 { "(bad)", { XX } },
6274 { "(bad)", { XX } },
6275 /* 78 */
6276 { "(bad)", { XX } },
6277 { "(bad)", { XX } },
6278 { "(bad)", { XX } },
6279 { "(bad)", { XX } },
6280 { "(bad)", { XX } },
6281 { "(bad)", { XX } },
6282 { "(bad)", { XX } },
6283 { "(bad)", { XX } },
6284 /* 80 */
6285 { "(bad)", { XX } },
6286 { "(bad)", { XX } },
6287 { "(bad)", { XX } },
6288 { "(bad)", { XX } },
6289 { "(bad)", { XX } },
6290 { "(bad)", { XX } },
6291 { "(bad)", { XX } },
6292 { "(bad)", { XX } },
6293 /* 88 */
6294 { "(bad)", { XX } },
6295 { "(bad)", { XX } },
6296 { "(bad)", { XX } },
6297 { "(bad)", { XX } },
6298 { "(bad)", { XX } },
6299 { "(bad)", { XX } },
6300 { "(bad)", { XX } },
6301 { "(bad)", { XX } },
6302 /* 90 */
6303 { "(bad)", { XX } },
6304 { "(bad)", { XX } },
6305 { "(bad)", { XX } },
6306 { "(bad)", { XX } },
6307 { "(bad)", { XX } },
6308 { "(bad)", { XX } },
6309 { "(bad)", { XX } },
6310 { "(bad)", { XX } },
6311 /* 98 */
6312 { "(bad)", { XX } },
6313 { "(bad)", { XX } },
6314 { "(bad)", { XX } },
6315 { "(bad)", { XX } },
6316 { "(bad)", { XX } },
6317 { "(bad)", { XX } },
6318 { "(bad)", { XX } },
6319 { "(bad)", { XX } },
6320 /* a0 */
6321 { "(bad)", { XX } },
6322 { "(bad)", { XX } },
6323 { "(bad)", { XX } },
6324 { "(bad)", { XX } },
6325 { "(bad)", { XX } },
6326 { "(bad)", { XX } },
6327 { "(bad)", { XX } },
6328 { "(bad)", { XX } },
6329 /* a8 */
6330 { "(bad)", { XX } },
6331 { "(bad)", { XX } },
6332 { "(bad)", { XX } },
6333 { "(bad)", { XX } },
6334 { "(bad)", { XX } },
6335 { "(bad)", { XX } },
6336 { "(bad)", { XX } },
6337 { "(bad)", { XX } },
6338 /* b0 */
6339 { "(bad)", { XX } },
6340 { "(bad)", { XX } },
6341 { "(bad)", { XX } },
6342 { "(bad)", { XX } },
6343 { "(bad)", { XX } },
6344 { "(bad)", { XX } },
6345 { "(bad)", { XX } },
6346 { "(bad)", { XX } },
6347 /* b8 */
6348 { "(bad)", { XX } },
6349 { "(bad)", { XX } },
6350 { "(bad)", { XX } },
6351 { "(bad)", { XX } },
6352 { "(bad)", { XX } },
6353 { "(bad)", { XX } },
6354 { "(bad)", { XX } },
6355 { "(bad)", { XX } },
6356 /* c0 */
6357 { "(bad)", { XX } },
6358 { "(bad)", { XX } },
6359 { "(bad)", { XX } },
6360 { "(bad)", { XX } },
6361 { "(bad)", { XX } },
6362 { "(bad)", { XX } },
6363 { "(bad)", { XX } },
6364 { "(bad)", { XX } },
6365 /* c8 */
6366 { "(bad)", { XX } },
6367 { "(bad)", { XX } },
6368 { "(bad)", { XX } },
6369 { "(bad)", { XX } },
6370 { "(bad)", { XX } },
6371 { "(bad)", { XX } },
6372 { "(bad)", { XX } },
6373 { "(bad)", { XX } },
6374 /* d0 */
6375 { "(bad)", { XX } },
6376 { "(bad)", { XX } },
6377 { "(bad)", { XX } },
6378 { "(bad)", { XX } },
6379 { "(bad)", { XX } },
6380 { "(bad)", { XX } },
6381 { "(bad)", { XX } },
6382 { "(bad)", { XX } },
6383 /* d8 */
6384 { "(bad)", { XX } },
6385 { "(bad)", { XX } },
6386 { "(bad)", { XX } },
6387 { "(bad)", { XX } },
6388 { "(bad)", { XX } },
6389 { "(bad)", { XX } },
6390 { "(bad)", { XX } },
6391 { PREFIX_TABLE (PREFIX_0F3ADF) },
6392 /* e0 */
6393 { "(bad)", { XX } },
6394 { "(bad)", { XX } },
6395 { "(bad)", { XX } },
6396 { "(bad)", { XX } },
6397 { "(bad)", { XX } },
6398 { "(bad)", { XX } },
6399 { "(bad)", { XX } },
6400 { "(bad)", { XX } },
6401 /* e8 */
6402 { "(bad)", { XX } },
6403 { "(bad)", { XX } },
6404 { "(bad)", { XX } },
6405 { "(bad)", { XX } },
6406 { "(bad)", { XX } },
6407 { "(bad)", { XX } },
6408 { "(bad)", { XX } },
6409 { "(bad)", { XX } },
6410 /* f0 */
6411 { "(bad)", { XX } },
6412 { "(bad)", { XX } },
6413 { "(bad)", { XX } },
6414 { "(bad)", { XX } },
6415 { "(bad)", { XX } },
6416 { "(bad)", { XX } },
6417 { "(bad)", { XX } },
6418 { "(bad)", { XX } },
6419 /* f8 */
6420 { "(bad)", { XX } },
6421 { "(bad)", { XX } },
6422 { "(bad)", { XX } },
6423 { "(bad)", { XX } },
6424 { "(bad)", { XX } },
6425 { "(bad)", { XX } },
6426 { "(bad)", { XX } },
6427 { "(bad)", { XX } },
6428 },
6429 /* THREE_BYTE_0F7A */
6430 {
6431 /* 00 */
6432 { "(bad)", { XX } },
6433 { "(bad)", { XX } },
6434 { "(bad)", { XX } },
6435 { "(bad)", { XX } },
6436 { "(bad)", { XX } },
6437 { "(bad)", { XX } },
6438 { "(bad)", { XX } },
6439 { "(bad)", { XX } },
6440 /* 08 */
6441 { "(bad)", { XX } },
6442 { "(bad)", { XX } },
6443 { "(bad)", { XX } },
6444 { "(bad)", { XX } },
6445 { "(bad)", { XX } },
6446 { "(bad)", { XX } },
6447 { "(bad)", { XX } },
6448 { "(bad)", { XX } },
6449 /* 10 */
6450 { "frczps", { XM, EXq } },
6451 { "frczpd", { XM, EXq } },
6452 { "frczss", { XM, EXq } },
6453 { "frczsd", { XM, EXq } },
6454 { "(bad)", { XX } },
6455 { "(bad)", { XX } },
6456 { "(bad)", { XX } },
6457 { "(bad)", { XX } },
6458 /* 18 */
6459 { "(bad)", { XX } },
6460 { "(bad)", { XX } },
6461 { "(bad)", { XX } },
6462 { "(bad)", { XX } },
6463 { "(bad)", { XX } },
6464 { "(bad)", { XX } },
6465 { "(bad)", { XX } },
6466 { "(bad)", { XX } },
6467 /* 20 */
6468 { "ptest", { XX } },
6469 { "(bad)", { XX } },
6470 { "(bad)", { XX } },
6471 { "(bad)", { XX } },
6472 { "(bad)", { XX } },
6473 { "(bad)", { XX } },
6474 { "(bad)", { XX } },
6475 { "(bad)", { XX } },
6476 /* 28 */
6477 { "(bad)", { XX } },
6478 { "(bad)", { XX } },
6479 { "(bad)", { XX } },
6480 { "(bad)", { XX } },
6481 { "(bad)", { XX } },
6482 { "(bad)", { XX } },
6483 { "(bad)", { XX } },
6484 { "(bad)", { XX } },
6485 /* 30 */
6486 { "cvtph2ps", { XM, EXd } },
6487 { "cvtps2ph", { EXd, XM } },
6488 { "(bad)", { XX } },
6489 { "(bad)", { XX } },
6490 { "(bad)", { XX } },
6491 { "(bad)", { XX } },
6492 { "(bad)", { XX } },
6493 { "(bad)", { XX } },
6494 /* 38 */
6495 { "(bad)", { XX } },
6496 { "(bad)", { XX } },
6497 { "(bad)", { XX } },
6498 { "(bad)", { XX } },
6499 { "(bad)", { XX } },
6500 { "(bad)", { XX } },
6501 { "(bad)", { XX } },
6502 { "(bad)", { XX } },
6503 /* 40 */
6504 { "(bad)", { XX } },
6505 { "phaddbw", { XM, EXq } },
6506 { "phaddbd", { XM, EXq } },
6507 { "phaddbq", { XM, EXq } },
6508 { "(bad)", { XX } },
6509 { "(bad)", { XX } },
6510 { "phaddwd", { XM, EXq } },
6511 { "phaddwq", { XM, EXq } },
6512 /* 48 */
6513 { "(bad)", { XX } },
6514 { "(bad)", { XX } },
6515 { "(bad)", { XX } },
6516 { "phadddq", { XM, EXq } },
6517 { "(bad)", { XX } },
6518 { "(bad)", { XX } },
6519 { "(bad)", { XX } },
6520 { "(bad)", { XX } },
6521 /* 50 */
6522 { "(bad)", { XX } },
6523 { "phaddubw", { XM, EXq } },
6524 { "phaddubd", { XM, EXq } },
6525 { "phaddubq", { XM, EXq } },
6526 { "(bad)", { XX } },
6527 { "(bad)", { XX } },
6528 { "phadduwd", { XM, EXq } },
6529 { "phadduwq", { XM, EXq } },
6530 /* 58 */
6531 { "(bad)", { XX } },
6532 { "(bad)", { XX } },
6533 { "(bad)", { XX } },
6534 { "phaddudq", { XM, EXq } },
6535 { "(bad)", { XX } },
6536 { "(bad)", { XX } },
6537 { "(bad)", { XX } },
6538 { "(bad)", { XX } },
6539 /* 60 */
6540 { "(bad)", { XX } },
6541 { "phsubbw", { XM, EXq } },
6542 { "phsubbd", { XM, EXq } },
6543 { "phsubbq", { XM, EXq } },
6544 { "(bad)", { XX } },
6545 { "(bad)", { XX } },
6546 { "(bad)", { XX } },
6547 { "(bad)", { XX } },
6548 /* 68 */
6549 { "(bad)", { XX } },
6550 { "(bad)", { XX } },
6551 { "(bad)", { XX } },
6552 { "(bad)", { XX } },
6553 { "(bad)", { XX } },
6554 { "(bad)", { XX } },
6555 { "(bad)", { XX } },
6556 { "(bad)", { XX } },
6557 /* 70 */
6558 { "(bad)", { XX } },
6559 { "(bad)", { XX } },
6560 { "(bad)", { XX } },
6561 { "(bad)", { XX } },
6562 { "(bad)", { XX } },
6563 { "(bad)", { XX } },
6564 { "(bad)", { XX } },
6565 { "(bad)", { XX } },
6566 /* 78 */
6567 { "(bad)", { XX } },
6568 { "(bad)", { XX } },
6569 { "(bad)", { XX } },
6570 { "(bad)", { XX } },
6571 { "(bad)", { XX } },
6572 { "(bad)", { XX } },
6573 { "(bad)", { XX } },
6574 { "(bad)", { XX } },
6575 /* 80 */
6576 { "(bad)", { XX } },
6577 { "(bad)", { XX } },
6578 { "(bad)", { XX } },
6579 { "(bad)", { XX } },
6580 { "(bad)", { XX } },
6581 { "(bad)", { XX } },
6582 { "(bad)", { XX } },
6583 { "(bad)", { XX } },
6584 /* 88 */
6585 { "(bad)", { XX } },
6586 { "(bad)", { XX } },
6587 { "(bad)", { XX } },
6588 { "(bad)", { XX } },
6589 { "(bad)", { XX } },
6590 { "(bad)", { XX } },
6591 { "(bad)", { XX } },
6592 { "(bad)", { XX } },
6593 /* 90 */
6594 { "(bad)", { XX } },
6595 { "(bad)", { XX } },
6596 { "(bad)", { XX } },
6597 { "(bad)", { XX } },
6598 { "(bad)", { XX } },
6599 { "(bad)", { XX } },
6600 { "(bad)", { XX } },
6601 { "(bad)", { XX } },
6602 /* 98 */
6603 { "(bad)", { XX } },
6604 { "(bad)", { XX } },
6605 { "(bad)", { XX } },
6606 { "(bad)", { XX } },
6607 { "(bad)", { XX } },
6608 { "(bad)", { XX } },
6609 { "(bad)", { XX } },
6610 { "(bad)", { XX } },
6611 /* a0 */
6612 { "(bad)", { XX } },
6613 { "(bad)", { XX } },
6614 { "(bad)", { XX } },
6615 { "(bad)", { XX } },
6616 { "(bad)", { XX } },
6617 { "(bad)", { XX } },
6618 { "(bad)", { XX } },
6619 { "(bad)", { XX } },
6620 /* a8 */
6621 { "(bad)", { XX } },
6622 { "(bad)", { XX } },
6623 { "(bad)", { XX } },
6624 { "(bad)", { XX } },
6625 { "(bad)", { XX } },
6626 { "(bad)", { XX } },
6627 { "(bad)", { XX } },
6628 { "(bad)", { XX } },
6629 /* b0 */
6630 { "(bad)", { XX } },
6631 { "(bad)", { XX } },
6632 { "(bad)", { XX } },
6633 { "(bad)", { XX } },
6634 { "(bad)", { XX } },
6635 { "(bad)", { XX } },
6636 { "(bad)", { XX } },
6637 { "(bad)", { XX } },
6638 /* b8 */
6639 { "(bad)", { XX } },
6640 { "(bad)", { XX } },
6641 { "(bad)", { XX } },
6642 { "(bad)", { XX } },
6643 { "(bad)", { XX } },
6644 { "(bad)", { XX } },
6645 { "(bad)", { XX } },
6646 { "(bad)", { XX } },
6647 /* c0 */
6648 { "(bad)", { XX } },
6649 { "(bad)", { XX } },
6650 { "(bad)", { XX } },
6651 { "(bad)", { XX } },
6652 { "(bad)", { XX } },
6653 { "(bad)", { XX } },
6654 { "(bad)", { XX } },
6655 { "(bad)", { XX } },
6656 /* c8 */
6657 { "(bad)", { XX } },
6658 { "(bad)", { XX } },
6659 { "(bad)", { XX } },
6660 { "(bad)", { XX } },
6661 { "(bad)", { XX } },
6662 { "(bad)", { XX } },
6663 { "(bad)", { XX } },
6664 { "(bad)", { XX } },
6665 /* d0 */
6666 { "(bad)", { XX } },
6667 { "(bad)", { XX } },
6668 { "(bad)", { XX } },
6669 { "(bad)", { XX } },
6670 { "(bad)", { XX } },
6671 { "(bad)", { XX } },
6672 { "(bad)", { XX } },
6673 { "(bad)", { XX } },
6674 /* d8 */
6675 { "(bad)", { XX } },
6676 { "(bad)", { XX } },
6677 { "(bad)", { XX } },
6678 { "(bad)", { XX } },
6679 { "(bad)", { XX } },
6680 { "(bad)", { XX } },
6681 { "(bad)", { XX } },
6682 { "(bad)", { XX } },
6683 /* e0 */
6684 { "(bad)", { XX } },
6685 { "(bad)", { XX } },
6686 { "(bad)", { XX } },
6687 { "(bad)", { XX } },
6688 { "(bad)", { XX } },
6689 { "(bad)", { XX } },
6690 { "(bad)", { XX } },
6691 { "(bad)", { XX } },
6692 /* e8 */
6693 { "(bad)", { XX } },
6694 { "(bad)", { XX } },
6695 { "(bad)", { XX } },
6696 { "(bad)", { XX } },
6697 { "(bad)", { XX } },
6698 { "(bad)", { XX } },
6699 { "(bad)", { XX } },
6700 { "(bad)", { XX } },
6701 /* f0 */
6702 { "(bad)", { XX } },
6703 { "(bad)", { XX } },
6704 { "(bad)", { XX } },
6705 { "(bad)", { XX } },
6706 { "(bad)", { XX } },
6707 { "(bad)", { XX } },
6708 { "(bad)", { XX } },
6709 { "(bad)", { XX } },
6710 /* f8 */
6711 { "(bad)", { XX } },
6712 { "(bad)", { XX } },
6713 { "(bad)", { XX } },
6714 { "(bad)", { XX } },
6715 { "(bad)", { XX } },
6716 { "(bad)", { XX } },
6717 { "(bad)", { XX } },
6718 { "(bad)", { XX } },
6719 },
6720 /* THREE_BYTE_0F7B */
6721 {
6722 /* 00 */
6723 { "(bad)", { XX } },
6724 { "(bad)", { XX } },
6725 { "(bad)", { XX } },
6726 { "(bad)", { XX } },
6727 { "(bad)", { XX } },
6728 { "(bad)", { XX } },
6729 { "(bad)", { XX } },
6730 { "(bad)", { XX } },
6731 /* 08 */
6732 { "(bad)", { XX } },
6733 { "(bad)", { XX } },
6734 { "(bad)", { XX } },
6735 { "(bad)", { XX } },
6736 { "(bad)", { XX } },
6737 { "(bad)", { XX } },
6738 { "(bad)", { XX } },
6739 { "(bad)", { XX } },
6740 /* 10 */
6741 { "(bad)", { XX } },
6742 { "(bad)", { XX } },
6743 { "(bad)", { XX } },
6744 { "(bad)", { XX } },
6745 { "(bad)", { XX } },
6746 { "(bad)", { XX } },
6747 { "(bad)", { XX } },
6748 { "(bad)", { XX } },
6749 /* 18 */
6750 { "(bad)", { XX } },
6751 { "(bad)", { XX } },
6752 { "(bad)", { XX } },
6753 { "(bad)", { XX } },
6754 { "(bad)", { XX } },
6755 { "(bad)", { XX } },
6756 { "(bad)", { XX } },
6757 { "(bad)", { XX } },
6758 /* 20 */
6759 { "(bad)", { XX } },
6760 { "(bad)", { XX } },
6761 { "(bad)", { XX } },
6762 { "(bad)", { XX } },
6763 { "(bad)", { XX } },
6764 { "(bad)", { XX } },
6765 { "(bad)", { XX } },
6766 { "(bad)", { XX } },
6767 /* 28 */
6768 { "(bad)", { XX } },
6769 { "(bad)", { XX } },
6770 { "(bad)", { XX } },
6771 { "(bad)", { XX } },
6772 { "(bad)", { XX } },
6773 { "(bad)", { XX } },
6774 { "(bad)", { XX } },
6775 { "(bad)", { XX } },
6776 /* 30 */
6777 { "(bad)", { XX } },
6778 { "(bad)", { XX } },
6779 { "(bad)", { XX } },
6780 { "(bad)", { XX } },
6781 { "(bad)", { XX } },
6782 { "(bad)", { XX } },
6783 { "(bad)", { XX } },
6784 { "(bad)", { XX } },
6785 /* 38 */
6786 { "(bad)", { XX } },
6787 { "(bad)", { XX } },
6788 { "(bad)", { XX } },
6789 { "(bad)", { XX } },
6790 { "(bad)", { XX } },
6791 { "(bad)", { XX } },
6792 { "(bad)", { XX } },
6793 { "(bad)", { XX } },
6794 /* 40 */
6795 { "protb", { XM, EXq, Ib } },
6796 { "protw", { XM, EXq, Ib } },
6797 { "protd", { XM, EXq, Ib } },
6798 { "protq", { XM, EXq, Ib } },
6799 { "pshlb", { XM, EXq, Ib } },
6800 { "pshlw", { XM, EXq, Ib } },
6801 { "pshld", { XM, EXq, Ib } },
6802 { "pshlq", { XM, EXq, Ib } },
6803 /* 48 */
6804 { "pshab", { XM, EXq, Ib } },
6805 { "pshaw", { XM, EXq, Ib } },
6806 { "pshad", { XM, EXq, Ib } },
6807 { "pshaq", { XM, EXq, Ib } },
6808 { "(bad)", { XX } },
6809 { "(bad)", { XX } },
6810 { "(bad)", { XX } },
6811 { "(bad)", { XX } },
6812 /* 50 */
6813 { "(bad)", { XX } },
6814 { "(bad)", { XX } },
6815 { "(bad)", { XX } },
6816 { "(bad)", { XX } },
6817 { "(bad)", { XX } },
6818 { "(bad)", { XX } },
6819 { "(bad)", { XX } },
6820 { "(bad)", { XX } },
6821 /* 58 */
6822 { "(bad)", { XX } },
6823 { "(bad)", { XX } },
6824 { "(bad)", { XX } },
6825 { "(bad)", { XX } },
6826 { "(bad)", { XX } },
6827 { "(bad)", { XX } },
6828 { "(bad)", { XX } },
6829 { "(bad)", { XX } },
6830 /* 60 */
6831 { "(bad)", { XX } },
6832 { "(bad)", { XX } },
6833 { "(bad)", { XX } },
6834 { "(bad)", { XX } },
6835 { "(bad)", { XX } },
6836 { "(bad)", { XX } },
6837 { "(bad)", { XX } },
6838 { "(bad)", { XX } },
6839 /* 68 */
6840 { "(bad)", { XX } },
6841 { "(bad)", { XX } },
6842 { "(bad)", { XX } },
6843 { "(bad)", { XX } },
6844 { "(bad)", { XX } },
6845 { "(bad)", { XX } },
6846 { "(bad)", { XX } },
6847 { "(bad)", { XX } },
6848 /* 70 */
6849 { "(bad)", { XX } },
6850 { "(bad)", { XX } },
6851 { "(bad)", { XX } },
6852 { "(bad)", { XX } },
6853 { "(bad)", { XX } },
6854 { "(bad)", { XX } },
6855 { "(bad)", { XX } },
6856 { "(bad)", { XX } },
6857 /* 78 */
6858 { "(bad)", { XX } },
6859 { "(bad)", { XX } },
6860 { "(bad)", { XX } },
6861 { "(bad)", { XX } },
6862 { "(bad)", { XX } },
6863 { "(bad)", { XX } },
6864 { "(bad)", { XX } },
6865 { "(bad)", { XX } },
6866 /* 80 */
6867 { "(bad)", { XX } },
6868 { "(bad)", { XX } },
6869 { "(bad)", { XX } },
6870 { "(bad)", { XX } },
6871 { "(bad)", { XX } },
6872 { "(bad)", { XX } },
6873 { "(bad)", { XX } },
6874 { "(bad)", { XX } },
6875 /* 88 */
6876 { "(bad)", { XX } },
6877 { "(bad)", { XX } },
6878 { "(bad)", { XX } },
6879 { "(bad)", { XX } },
6880 { "(bad)", { XX } },
6881 { "(bad)", { XX } },
6882 { "(bad)", { XX } },
6883 { "(bad)", { XX } },
6884 /* 90 */
6885 { "(bad)", { XX } },
6886 { "(bad)", { XX } },
6887 { "(bad)", { XX } },
6888 { "(bad)", { XX } },
6889 { "(bad)", { XX } },
6890 { "(bad)", { XX } },
6891 { "(bad)", { XX } },
6892 { "(bad)", { XX } },
6893 /* 98 */
6894 { "(bad)", { XX } },
6895 { "(bad)", { XX } },
6896 { "(bad)", { XX } },
6897 { "(bad)", { XX } },
6898 { "(bad)", { XX } },
6899 { "(bad)", { XX } },
6900 { "(bad)", { XX } },
6901 { "(bad)", { XX } },
6902 /* a0 */
6903 { "(bad)", { XX } },
6904 { "(bad)", { XX } },
6905 { "(bad)", { XX } },
6906 { "(bad)", { XX } },
6907 { "(bad)", { XX } },
6908 { "(bad)", { XX } },
6909 { "(bad)", { XX } },
6910 { "(bad)", { XX } },
6911 /* a8 */
6912 { "(bad)", { XX } },
6913 { "(bad)", { XX } },
6914 { "(bad)", { XX } },
6915 { "(bad)", { XX } },
6916 { "(bad)", { XX } },
6917 { "(bad)", { XX } },
6918 { "(bad)", { XX } },
6919 { "(bad)", { XX } },
6920 /* b0 */
6921 { "(bad)", { XX } },
6922 { "(bad)", { XX } },
6923 { "(bad)", { XX } },
6924 { "(bad)", { XX } },
6925 { "(bad)", { XX } },
6926 { "(bad)", { XX } },
6927 { "(bad)", { XX } },
6928 { "(bad)", { XX } },
6929 /* b8 */
6930 { "(bad)", { XX } },
6931 { "(bad)", { XX } },
6932 { "(bad)", { XX } },
6933 { "(bad)", { XX } },
6934 { "(bad)", { XX } },
6935 { "(bad)", { XX } },
6936 { "(bad)", { XX } },
6937 { "(bad)", { XX } },
6938 /* c0 */
6939 { "(bad)", { XX } },
6940 { "(bad)", { XX } },
6941 { "(bad)", { XX } },
6942 { "(bad)", { XX } },
6943 { "(bad)", { XX } },
6944 { "(bad)", { XX } },
6945 { "(bad)", { XX } },
6946 { "(bad)", { XX } },
6947 /* c8 */
6948 { "(bad)", { XX } },
6949 { "(bad)", { XX } },
6950 { "(bad)", { XX } },
6951 { "(bad)", { XX } },
6952 { "(bad)", { XX } },
6953 { "(bad)", { XX } },
6954 { "(bad)", { XX } },
6955 { "(bad)", { XX } },
6956 /* d0 */
6957 { "(bad)", { XX } },
6958 { "(bad)", { XX } },
6959 { "(bad)", { XX } },
6960 { "(bad)", { XX } },
6961 { "(bad)", { XX } },
6962 { "(bad)", { XX } },
6963 { "(bad)", { XX } },
6964 { "(bad)", { XX } },
6965 /* d8 */
6966 { "(bad)", { XX } },
6967 { "(bad)", { XX } },
6968 { "(bad)", { XX } },
6969 { "(bad)", { XX } },
6970 { "(bad)", { XX } },
6971 { "(bad)", { XX } },
6972 { "(bad)", { XX } },
6973 { "(bad)", { XX } },
6974 /* e0 */
6975 { "(bad)", { XX } },
6976 { "(bad)", { XX } },
6977 { "(bad)", { XX } },
6978 { "(bad)", { XX } },
6979 { "(bad)", { XX } },
6980 { "(bad)", { XX } },
6981 { "(bad)", { XX } },
6982 { "(bad)", { XX } },
6983 /* e8 */
6984 { "(bad)", { XX } },
6985 { "(bad)", { XX } },
6986 { "(bad)", { XX } },
6987 { "(bad)", { XX } },
6988 { "(bad)", { XX } },
6989 { "(bad)", { XX } },
6990 { "(bad)", { XX } },
6991 { "(bad)", { XX } },
6992 /* f0 */
6993 { "(bad)", { XX } },
6994 { "(bad)", { XX } },
6995 { "(bad)", { XX } },
6996 { "(bad)", { XX } },
6997 { "(bad)", { XX } },
6998 { "(bad)", { XX } },
6999 { "(bad)", { XX } },
7000 { "(bad)", { XX } },
7001 /* f8 */
7002 { "(bad)", { XX } },
7003 { "(bad)", { XX } },
7004 { "(bad)", { XX } },
7005 { "(bad)", { XX } },
7006 { "(bad)", { XX } },
7007 { "(bad)", { XX } },
7008 { "(bad)", { XX } },
7009 { "(bad)", { XX } },
7010 },
7011 };
7012
7013 static const struct dis386 vex_table[][256] = {
7014 /* VEX_0F */
7015 {
7016 /* 00 */
7017 { "(bad)", { XX } },
7018 { "(bad)", { XX } },
7019 { "(bad)", { XX } },
7020 { "(bad)", { XX } },
7021 { "(bad)", { XX } },
7022 { "(bad)", { XX } },
7023 { "(bad)", { XX } },
7024 { "(bad)", { XX } },
7025 /* 08 */
7026 { "(bad)", { XX } },
7027 { "(bad)", { XX } },
7028 { "(bad)", { XX } },
7029 { "(bad)", { XX } },
7030 { "(bad)", { XX } },
7031 { "(bad)", { XX } },
7032 { "(bad)", { XX } },
7033 { "(bad)", { XX } },
7034 /* 10 */
7035 { PREFIX_TABLE (PREFIX_VEX_10) },
7036 { PREFIX_TABLE (PREFIX_VEX_11) },
7037 { PREFIX_TABLE (PREFIX_VEX_12) },
7038 { MOD_TABLE (MOD_VEX_13) },
7039 { "vunpcklpX", { XM, Vex, EXx } },
7040 { "vunpckhpX", { XM, Vex, EXx } },
7041 { PREFIX_TABLE (PREFIX_VEX_16) },
7042 { MOD_TABLE (MOD_VEX_17) },
7043 /* 18 */
7044 { "(bad)", { XX } },
7045 { "(bad)", { XX } },
7046 { "(bad)", { XX } },
7047 { "(bad)", { XX } },
7048 { "(bad)", { XX } },
7049 { "(bad)", { XX } },
7050 { "(bad)", { XX } },
7051 { "(bad)", { XX } },
7052 /* 20 */
7053 { "(bad)", { XX } },
7054 { "(bad)", { XX } },
7055 { "(bad)", { XX } },
7056 { "(bad)", { XX } },
7057 { "(bad)", { XX } },
7058 { "(bad)", { XX } },
7059 { "(bad)", { XX } },
7060 { "(bad)", { XX } },
7061 /* 28 */
7062 { "vmovapX", { XM, EXx } },
7063 { "vmovapX", { EXxS, XM } },
7064 { PREFIX_TABLE (PREFIX_VEX_2A) },
7065 { MOD_TABLE (MOD_VEX_2B) },
7066 { PREFIX_TABLE (PREFIX_VEX_2C) },
7067 { PREFIX_TABLE (PREFIX_VEX_2D) },
7068 { PREFIX_TABLE (PREFIX_VEX_2E) },
7069 { PREFIX_TABLE (PREFIX_VEX_2F) },
7070 /* 30 */
7071 { "(bad)", { XX } },
7072 { "(bad)", { XX } },
7073 { "(bad)", { XX } },
7074 { "(bad)", { XX } },
7075 { "(bad)", { XX } },
7076 { "(bad)", { XX } },
7077 { "(bad)", { XX } },
7078 { "(bad)", { XX } },
7079 /* 38 */
7080 { "(bad)", { XX } },
7081 { "(bad)", { XX } },
7082 { "(bad)", { XX } },
7083 { "(bad)", { XX } },
7084 { "(bad)", { XX } },
7085 { "(bad)", { XX } },
7086 { "(bad)", { XX } },
7087 { "(bad)", { XX } },
7088 /* 40 */
7089 { "(bad)", { XX } },
7090 { "(bad)", { XX } },
7091 { "(bad)", { XX } },
7092 { "(bad)", { XX } },
7093 { "(bad)", { XX } },
7094 { "(bad)", { XX } },
7095 { "(bad)", { XX } },
7096 { "(bad)", { XX } },
7097 /* 48 */
7098 { "(bad)", { XX } },
7099 { "(bad)", { XX } },
7100 { "(bad)", { XX } },
7101 { "(bad)", { XX } },
7102 { "(bad)", { XX } },
7103 { "(bad)", { XX } },
7104 { "(bad)", { XX } },
7105 { "(bad)", { XX } },
7106 /* 50 */
7107 { MOD_TABLE (MOD_VEX_51) },
7108 { PREFIX_TABLE (PREFIX_VEX_51) },
7109 { PREFIX_TABLE (PREFIX_VEX_52) },
7110 { PREFIX_TABLE (PREFIX_VEX_53) },
7111 { "vandpX", { XM, Vex, EXx } },
7112 { "vandnpX", { XM, Vex, EXx } },
7113 { "vorpX", { XM, Vex, EXx } },
7114 { "vxorpX", { XM, Vex, EXx } },
7115 /* 58 */
7116 { PREFIX_TABLE (PREFIX_VEX_58) },
7117 { PREFIX_TABLE (PREFIX_VEX_59) },
7118 { PREFIX_TABLE (PREFIX_VEX_5A) },
7119 { PREFIX_TABLE (PREFIX_VEX_5B) },
7120 { PREFIX_TABLE (PREFIX_VEX_5C) },
7121 { PREFIX_TABLE (PREFIX_VEX_5D) },
7122 { PREFIX_TABLE (PREFIX_VEX_5E) },
7123 { PREFIX_TABLE (PREFIX_VEX_5F) },
7124 /* 60 */
7125 { PREFIX_TABLE (PREFIX_VEX_60) },
7126 { PREFIX_TABLE (PREFIX_VEX_61) },
7127 { PREFIX_TABLE (PREFIX_VEX_62) },
7128 { PREFIX_TABLE (PREFIX_VEX_63) },
7129 { PREFIX_TABLE (PREFIX_VEX_64) },
7130 { PREFIX_TABLE (PREFIX_VEX_65) },
7131 { PREFIX_TABLE (PREFIX_VEX_66) },
7132 { PREFIX_TABLE (PREFIX_VEX_67) },
7133 /* 68 */
7134 { PREFIX_TABLE (PREFIX_VEX_68) },
7135 { PREFIX_TABLE (PREFIX_VEX_69) },
7136 { PREFIX_TABLE (PREFIX_VEX_6A) },
7137 { PREFIX_TABLE (PREFIX_VEX_6B) },
7138 { PREFIX_TABLE (PREFIX_VEX_6C) },
7139 { PREFIX_TABLE (PREFIX_VEX_6D) },
7140 { PREFIX_TABLE (PREFIX_VEX_6E) },
7141 { PREFIX_TABLE (PREFIX_VEX_6F) },
7142 /* 70 */
7143 { PREFIX_TABLE (PREFIX_VEX_70) },
7144 { REG_TABLE (REG_VEX_71) },
7145 { REG_TABLE (REG_VEX_72) },
7146 { REG_TABLE (REG_VEX_73) },
7147 { PREFIX_TABLE (PREFIX_VEX_74) },
7148 { PREFIX_TABLE (PREFIX_VEX_75) },
7149 { PREFIX_TABLE (PREFIX_VEX_76) },
7150 { PREFIX_TABLE (PREFIX_VEX_77) },
7151 /* 78 */
7152 { "(bad)", { XX } },
7153 { "(bad)", { XX } },
7154 { "(bad)", { XX } },
7155 { "(bad)", { XX } },
7156 { PREFIX_TABLE (PREFIX_VEX_7C) },
7157 { PREFIX_TABLE (PREFIX_VEX_7D) },
7158 { PREFIX_TABLE (PREFIX_VEX_7E) },
7159 { PREFIX_TABLE (PREFIX_VEX_7F) },
7160 /* 80 */
7161 { "(bad)", { XX } },
7162 { "(bad)", { XX } },
7163 { "(bad)", { XX } },
7164 { "(bad)", { XX } },
7165 { "(bad)", { XX } },
7166 { "(bad)", { XX } },
7167 { "(bad)", { XX } },
7168 { "(bad)", { XX } },
7169 /* 88 */
7170 { "(bad)", { XX } },
7171 { "(bad)", { XX } },
7172 { "(bad)", { XX } },
7173 { "(bad)", { XX } },
7174 { "(bad)", { XX } },
7175 { "(bad)", { XX } },
7176 { "(bad)", { XX } },
7177 { "(bad)", { XX } },
7178 /* 90 */
7179 { "(bad)", { XX } },
7180 { "(bad)", { XX } },
7181 { "(bad)", { XX } },
7182 { "(bad)", { XX } },
7183 { "(bad)", { XX } },
7184 { "(bad)", { XX } },
7185 { "(bad)", { XX } },
7186 { "(bad)", { XX } },
7187 /* 98 */
7188 { "(bad)", { XX } },
7189 { "(bad)", { XX } },
7190 { "(bad)", { XX } },
7191 { "(bad)", { XX } },
7192 { "(bad)", { XX } },
7193 { "(bad)", { XX } },
7194 { "(bad)", { XX } },
7195 { "(bad)", { XX } },
7196 /* a0 */
7197 { "(bad)", { XX } },
7198 { "(bad)", { XX } },
7199 { "(bad)", { XX } },
7200 { "(bad)", { XX } },
7201 { "(bad)", { XX } },
7202 { "(bad)", { XX } },
7203 { "(bad)", { XX } },
7204 { "(bad)", { XX } },
7205 /* a8 */
7206 { "(bad)", { XX } },
7207 { "(bad)", { XX } },
7208 { "(bad)", { XX } },
7209 { "(bad)", { XX } },
7210 { "(bad)", { XX } },
7211 { "(bad)", { XX } },
7212 { REG_TABLE (REG_VEX_AE) },
7213 { "(bad)", { XX } },
7214 /* b0 */
7215 { "(bad)", { XX } },
7216 { "(bad)", { XX } },
7217 { "(bad)", { XX } },
7218 { "(bad)", { XX } },
7219 { "(bad)", { XX } },
7220 { "(bad)", { XX } },
7221 { "(bad)", { XX } },
7222 { "(bad)", { XX } },
7223 /* b8 */
7224 { "(bad)", { XX } },
7225 { "(bad)", { XX } },
7226 { "(bad)", { XX } },
7227 { "(bad)", { XX } },
7228 { "(bad)", { XX } },
7229 { "(bad)", { XX } },
7230 { "(bad)", { XX } },
7231 { "(bad)", { XX } },
7232 /* c0 */
7233 { "(bad)", { XX } },
7234 { "(bad)", { XX } },
7235 { PREFIX_TABLE (PREFIX_VEX_C2) },
7236 { "(bad)", { XX } },
7237 { PREFIX_TABLE (PREFIX_VEX_C4) },
7238 { PREFIX_TABLE (PREFIX_VEX_C5) },
7239 { "vshufpX", { XM, Vex, EXx, Ib } },
7240 { "(bad)", { XX } },
7241 /* c8 */
7242 { "(bad)", { XX } },
7243 { "(bad)", { XX } },
7244 { "(bad)", { XX } },
7245 { "(bad)", { XX } },
7246 { "(bad)", { XX } },
7247 { "(bad)", { XX } },
7248 { "(bad)", { XX } },
7249 { "(bad)", { XX } },
7250 /* d0 */
7251 { PREFIX_TABLE (PREFIX_VEX_D0) },
7252 { PREFIX_TABLE (PREFIX_VEX_D1) },
7253 { PREFIX_TABLE (PREFIX_VEX_D2) },
7254 { PREFIX_TABLE (PREFIX_VEX_D3) },
7255 { PREFIX_TABLE (PREFIX_VEX_D4) },
7256 { PREFIX_TABLE (PREFIX_VEX_D5) },
7257 { PREFIX_TABLE (PREFIX_VEX_D6) },
7258 { PREFIX_TABLE (PREFIX_VEX_D7) },
7259 /* d8 */
7260 { PREFIX_TABLE (PREFIX_VEX_D8) },
7261 { PREFIX_TABLE (PREFIX_VEX_D9) },
7262 { PREFIX_TABLE (PREFIX_VEX_DA) },
7263 { PREFIX_TABLE (PREFIX_VEX_DB) },
7264 { PREFIX_TABLE (PREFIX_VEX_DC) },
7265 { PREFIX_TABLE (PREFIX_VEX_DD) },
7266 { PREFIX_TABLE (PREFIX_VEX_DE) },
7267 { PREFIX_TABLE (PREFIX_VEX_DF) },
7268 /* e0 */
7269 { PREFIX_TABLE (PREFIX_VEX_E0) },
7270 { PREFIX_TABLE (PREFIX_VEX_E1) },
7271 { PREFIX_TABLE (PREFIX_VEX_E2) },
7272 { PREFIX_TABLE (PREFIX_VEX_E3) },
7273 { PREFIX_TABLE (PREFIX_VEX_E4) },
7274 { PREFIX_TABLE (PREFIX_VEX_E5) },
7275 { PREFIX_TABLE (PREFIX_VEX_E6) },
7276 { PREFIX_TABLE (PREFIX_VEX_E7) },
7277 /* e8 */
7278 { PREFIX_TABLE (PREFIX_VEX_E8) },
7279 { PREFIX_TABLE (PREFIX_VEX_E9) },
7280 { PREFIX_TABLE (PREFIX_VEX_EA) },
7281 { PREFIX_TABLE (PREFIX_VEX_EB) },
7282 { PREFIX_TABLE (PREFIX_VEX_EC) },
7283 { PREFIX_TABLE (PREFIX_VEX_ED) },
7284 { PREFIX_TABLE (PREFIX_VEX_EE) },
7285 { PREFIX_TABLE (PREFIX_VEX_EF) },
7286 /* f0 */
7287 { PREFIX_TABLE (PREFIX_VEX_F0) },
7288 { PREFIX_TABLE (PREFIX_VEX_F1) },
7289 { PREFIX_TABLE (PREFIX_VEX_F2) },
7290 { PREFIX_TABLE (PREFIX_VEX_F3) },
7291 { PREFIX_TABLE (PREFIX_VEX_F4) },
7292 { PREFIX_TABLE (PREFIX_VEX_F5) },
7293 { PREFIX_TABLE (PREFIX_VEX_F6) },
7294 { PREFIX_TABLE (PREFIX_VEX_F7) },
7295 /* f8 */
7296 { PREFIX_TABLE (PREFIX_VEX_F8) },
7297 { PREFIX_TABLE (PREFIX_VEX_F9) },
7298 { PREFIX_TABLE (PREFIX_VEX_FA) },
7299 { PREFIX_TABLE (PREFIX_VEX_FB) },
7300 { PREFIX_TABLE (PREFIX_VEX_FC) },
7301 { PREFIX_TABLE (PREFIX_VEX_FD) },
7302 { PREFIX_TABLE (PREFIX_VEX_FE) },
7303 { "(bad)", { XX } },
7304 },
7305 /* VEX_0F38 */
7306 {
7307 /* 00 */
7308 { PREFIX_TABLE (PREFIX_VEX_3800) },
7309 { PREFIX_TABLE (PREFIX_VEX_3801) },
7310 { PREFIX_TABLE (PREFIX_VEX_3802) },
7311 { PREFIX_TABLE (PREFIX_VEX_3803) },
7312 { PREFIX_TABLE (PREFIX_VEX_3804) },
7313 { PREFIX_TABLE (PREFIX_VEX_3805) },
7314 { PREFIX_TABLE (PREFIX_VEX_3806) },
7315 { PREFIX_TABLE (PREFIX_VEX_3807) },
7316 /* 08 */
7317 { PREFIX_TABLE (PREFIX_VEX_3808) },
7318 { PREFIX_TABLE (PREFIX_VEX_3809) },
7319 { PREFIX_TABLE (PREFIX_VEX_380A) },
7320 { PREFIX_TABLE (PREFIX_VEX_380B) },
7321 { PREFIX_TABLE (PREFIX_VEX_380C) },
7322 { PREFIX_TABLE (PREFIX_VEX_380D) },
7323 { PREFIX_TABLE (PREFIX_VEX_380E) },
7324 { PREFIX_TABLE (PREFIX_VEX_380F) },
7325 /* 10 */
7326 { "(bad)", { XX } },
7327 { "(bad)", { XX } },
7328 { "(bad)", { XX } },
7329 { "(bad)", { XX } },
7330 { "(bad)", { XX } },
7331 { "(bad)", { XX } },
7332 { "(bad)", { XX } },
7333 { PREFIX_TABLE (PREFIX_VEX_3817) },
7334 /* 18 */
7335 { PREFIX_TABLE (PREFIX_VEX_3818) },
7336 { PREFIX_TABLE (PREFIX_VEX_3819) },
7337 { PREFIX_TABLE (PREFIX_VEX_381A) },
7338 { "(bad)", { XX } },
7339 { PREFIX_TABLE (PREFIX_VEX_381C) },
7340 { PREFIX_TABLE (PREFIX_VEX_381D) },
7341 { PREFIX_TABLE (PREFIX_VEX_381E) },
7342 { "(bad)", { XX } },
7343 /* 20 */
7344 { PREFIX_TABLE (PREFIX_VEX_3820) },
7345 { PREFIX_TABLE (PREFIX_VEX_3821) },
7346 { PREFIX_TABLE (PREFIX_VEX_3822) },
7347 { PREFIX_TABLE (PREFIX_VEX_3823) },
7348 { PREFIX_TABLE (PREFIX_VEX_3824) },
7349 { PREFIX_TABLE (PREFIX_VEX_3825) },
7350 { "(bad)", { XX } },
7351 { "(bad)", { XX } },
7352 /* 28 */
7353 { PREFIX_TABLE (PREFIX_VEX_3828) },
7354 { PREFIX_TABLE (PREFIX_VEX_3829) },
7355 { PREFIX_TABLE (PREFIX_VEX_382A) },
7356 { PREFIX_TABLE (PREFIX_VEX_382B) },
7357 { PREFIX_TABLE (PREFIX_VEX_382C) },
7358 { PREFIX_TABLE (PREFIX_VEX_382D) },
7359 { PREFIX_TABLE (PREFIX_VEX_382E) },
7360 { PREFIX_TABLE (PREFIX_VEX_382F) },
7361 /* 30 */
7362 { PREFIX_TABLE (PREFIX_VEX_3830) },
7363 { PREFIX_TABLE (PREFIX_VEX_3831) },
7364 { PREFIX_TABLE (PREFIX_VEX_3832) },
7365 { PREFIX_TABLE (PREFIX_VEX_3833) },
7366 { PREFIX_TABLE (PREFIX_VEX_3834) },
7367 { PREFIX_TABLE (PREFIX_VEX_3835) },
7368 { "(bad)", { XX } },
7369 { PREFIX_TABLE (PREFIX_VEX_3837) },
7370 /* 38 */
7371 { PREFIX_TABLE (PREFIX_VEX_3838) },
7372 { PREFIX_TABLE (PREFIX_VEX_3839) },
7373 { PREFIX_TABLE (PREFIX_VEX_383A) },
7374 { PREFIX_TABLE (PREFIX_VEX_383B) },
7375 { PREFIX_TABLE (PREFIX_VEX_383C) },
7376 { PREFIX_TABLE (PREFIX_VEX_383D) },
7377 { PREFIX_TABLE (PREFIX_VEX_383E) },
7378 { PREFIX_TABLE (PREFIX_VEX_383F) },
7379 /* 40 */
7380 { PREFIX_TABLE (PREFIX_VEX_3840) },
7381 { PREFIX_TABLE (PREFIX_VEX_3841) },
7382 { "(bad)", { XX } },
7383 { "(bad)", { XX } },
7384 { "(bad)", { XX } },
7385 { "(bad)", { XX } },
7386 { "(bad)", { XX } },
7387 { "(bad)", { XX } },
7388 /* 48 */
7389 { "(bad)", { XX } },
7390 { "(bad)", { XX } },
7391 { "(bad)", { XX } },
7392 { "(bad)", { XX } },
7393 { "(bad)", { XX } },
7394 { "(bad)", { XX } },
7395 { "(bad)", { XX } },
7396 { "(bad)", { XX } },
7397 /* 50 */
7398 { "(bad)", { XX } },
7399 { "(bad)", { XX } },
7400 { "(bad)", { XX } },
7401 { "(bad)", { XX } },
7402 { "(bad)", { XX } },
7403 { "(bad)", { XX } },
7404 { "(bad)", { XX } },
7405 { "(bad)", { XX } },
7406 /* 58 */
7407 { "(bad)", { XX } },
7408 { "(bad)", { XX } },
7409 { "(bad)", { XX } },
7410 { "(bad)", { XX } },
7411 { "(bad)", { XX } },
7412 { "(bad)", { XX } },
7413 { "(bad)", { XX } },
7414 { "(bad)", { XX } },
7415 /* 60 */
7416 { "(bad)", { XX } },
7417 { "(bad)", { XX } },
7418 { "(bad)", { XX } },
7419 { "(bad)", { XX } },
7420 { "(bad)", { XX } },
7421 { "(bad)", { XX } },
7422 { "(bad)", { XX } },
7423 { "(bad)", { XX } },
7424 /* 68 */
7425 { "(bad)", { XX } },
7426 { "(bad)", { XX } },
7427 { "(bad)", { XX } },
7428 { "(bad)", { XX } },
7429 { "(bad)", { XX } },
7430 { "(bad)", { XX } },
7431 { "(bad)", { XX } },
7432 { "(bad)", { XX } },
7433 /* 70 */
7434 { "(bad)", { XX } },
7435 { "(bad)", { XX } },
7436 { "(bad)", { XX } },
7437 { "(bad)", { XX } },
7438 { "(bad)", { XX } },
7439 { "(bad)", { XX } },
7440 { "(bad)", { XX } },
7441 { "(bad)", { XX } },
7442 /* 78 */
7443 { "(bad)", { XX } },
7444 { "(bad)", { XX } },
7445 { "(bad)", { XX } },
7446 { "(bad)", { XX } },
7447 { "(bad)", { XX } },
7448 { "(bad)", { XX } },
7449 { "(bad)", { XX } },
7450 { "(bad)", { XX } },
7451 /* 80 */
7452 { "(bad)", { XX } },
7453 { "(bad)", { XX } },
7454 { "(bad)", { XX } },
7455 { "(bad)", { XX } },
7456 { "(bad)", { XX } },
7457 { "(bad)", { XX } },
7458 { "(bad)", { XX } },
7459 { "(bad)", { XX } },
7460 /* 88 */
7461 { "(bad)", { XX } },
7462 { "(bad)", { XX } },
7463 { "(bad)", { XX } },
7464 { "(bad)", { XX } },
7465 { "(bad)", { XX } },
7466 { "(bad)", { XX } },
7467 { "(bad)", { XX } },
7468 { "(bad)", { XX } },
7469 /* 90 */
7470 { "(bad)", { XX } },
7471 { "(bad)", { XX } },
7472 { "(bad)", { XX } },
7473 { "(bad)", { XX } },
7474 { "(bad)", { XX } },
7475 { "(bad)", { XX } },
7476 { PREFIX_TABLE (PREFIX_VEX_3896) },
7477 { PREFIX_TABLE (PREFIX_VEX_3897) },
7478 /* 98 */
7479 { PREFIX_TABLE (PREFIX_VEX_3898) },
7480 { PREFIX_TABLE (PREFIX_VEX_3899) },
7481 { PREFIX_TABLE (PREFIX_VEX_389A) },
7482 { PREFIX_TABLE (PREFIX_VEX_389B) },
7483 { PREFIX_TABLE (PREFIX_VEX_389C) },
7484 { PREFIX_TABLE (PREFIX_VEX_389D) },
7485 { PREFIX_TABLE (PREFIX_VEX_389E) },
7486 { PREFIX_TABLE (PREFIX_VEX_389F) },
7487 /* a0 */
7488 { "(bad)", { XX } },
7489 { "(bad)", { XX } },
7490 { "(bad)", { XX } },
7491 { "(bad)", { XX } },
7492 { "(bad)", { XX } },
7493 { "(bad)", { XX } },
7494 { PREFIX_TABLE (PREFIX_VEX_38A6) },
7495 { PREFIX_TABLE (PREFIX_VEX_38A7) },
7496 /* a8 */
7497 { PREFIX_TABLE (PREFIX_VEX_38A8) },
7498 { PREFIX_TABLE (PREFIX_VEX_38A9) },
7499 { PREFIX_TABLE (PREFIX_VEX_38AA) },
7500 { PREFIX_TABLE (PREFIX_VEX_38AB) },
7501 { PREFIX_TABLE (PREFIX_VEX_38AC) },
7502 { PREFIX_TABLE (PREFIX_VEX_38AD) },
7503 { PREFIX_TABLE (PREFIX_VEX_38AE) },
7504 { PREFIX_TABLE (PREFIX_VEX_38AF) },
7505 /* b0 */
7506 { "(bad)", { XX } },
7507 { "(bad)", { XX } },
7508 { "(bad)", { XX } },
7509 { "(bad)", { XX } },
7510 { "(bad)", { XX } },
7511 { "(bad)", { XX } },
7512 { PREFIX_TABLE (PREFIX_VEX_38B6) },
7513 { PREFIX_TABLE (PREFIX_VEX_38B7) },
7514 /* b8 */
7515 { PREFIX_TABLE (PREFIX_VEX_38B8) },
7516 { PREFIX_TABLE (PREFIX_VEX_38B9) },
7517 { PREFIX_TABLE (PREFIX_VEX_38BA) },
7518 { PREFIX_TABLE (PREFIX_VEX_38BB) },
7519 { PREFIX_TABLE (PREFIX_VEX_38BC) },
7520 { PREFIX_TABLE (PREFIX_VEX_38BD) },
7521 { PREFIX_TABLE (PREFIX_VEX_38BE) },
7522 { PREFIX_TABLE (PREFIX_VEX_38BF) },
7523 /* c0 */
7524 { "(bad)", { XX } },
7525 { "(bad)", { XX } },
7526 { "(bad)", { XX } },
7527 { "(bad)", { XX } },
7528 { "(bad)", { XX } },
7529 { "(bad)", { XX } },
7530 { "(bad)", { XX } },
7531 { "(bad)", { XX } },
7532 /* c8 */
7533 { "(bad)", { XX } },
7534 { "(bad)", { XX } },
7535 { "(bad)", { XX } },
7536 { "(bad)", { XX } },
7537 { "(bad)", { XX } },
7538 { "(bad)", { XX } },
7539 { "(bad)", { XX } },
7540 { "(bad)", { XX } },
7541 /* d0 */
7542 { "(bad)", { XX } },
7543 { "(bad)", { XX } },
7544 { "(bad)", { XX } },
7545 { "(bad)", { XX } },
7546 { "(bad)", { XX } },
7547 { "(bad)", { XX } },
7548 { "(bad)", { XX } },
7549 { "(bad)", { XX } },
7550 /* d8 */
7551 { "(bad)", { XX } },
7552 { "(bad)", { XX } },
7553 { "(bad)", { XX } },
7554 { PREFIX_TABLE (PREFIX_VEX_38DB) },
7555 { PREFIX_TABLE (PREFIX_VEX_38DC) },
7556 { PREFIX_TABLE (PREFIX_VEX_38DD) },
7557 { PREFIX_TABLE (PREFIX_VEX_38DE) },
7558 { PREFIX_TABLE (PREFIX_VEX_38DF) },
7559 /* e0 */
7560 { "(bad)", { XX } },
7561 { "(bad)", { XX } },
7562 { "(bad)", { XX } },
7563 { "(bad)", { XX } },
7564 { "(bad)", { XX } },
7565 { "(bad)", { XX } },
7566 { "(bad)", { XX } },
7567 { "(bad)", { XX } },
7568 /* e8 */
7569 { "(bad)", { XX } },
7570 { "(bad)", { XX } },
7571 { "(bad)", { XX } },
7572 { "(bad)", { XX } },
7573 { "(bad)", { XX } },
7574 { "(bad)", { XX } },
7575 { "(bad)", { XX } },
7576 { "(bad)", { XX } },
7577 /* f0 */
7578 { "(bad)", { XX } },
7579 { "(bad)", { XX } },
7580 { "(bad)", { XX } },
7581 { "(bad)", { XX } },
7582 { "(bad)", { XX } },
7583 { "(bad)", { XX } },
7584 { "(bad)", { XX } },
7585 { "(bad)", { XX } },
7586 /* f8 */
7587 { "(bad)", { XX } },
7588 { "(bad)", { XX } },
7589 { "(bad)", { XX } },
7590 { "(bad)", { XX } },
7591 { "(bad)", { XX } },
7592 { "(bad)", { XX } },
7593 { "(bad)", { XX } },
7594 { "(bad)", { XX } },
7595 },
7596 /* VEX_0F3A */
7597 {
7598 /* 00 */
7599 { "(bad)", { XX } },
7600 { "(bad)", { XX } },
7601 { "(bad)", { XX } },
7602 { "(bad)", { XX } },
7603 { PREFIX_TABLE (PREFIX_VEX_3A04) },
7604 { PREFIX_TABLE (PREFIX_VEX_3A05) },
7605 { PREFIX_TABLE (PREFIX_VEX_3A06) },
7606 { "(bad)", { XX } },
7607 /* 08 */
7608 { PREFIX_TABLE (PREFIX_VEX_3A08) },
7609 { PREFIX_TABLE (PREFIX_VEX_3A09) },
7610 { PREFIX_TABLE (PREFIX_VEX_3A0A) },
7611 { PREFIX_TABLE (PREFIX_VEX_3A0B) },
7612 { PREFIX_TABLE (PREFIX_VEX_3A0C) },
7613 { PREFIX_TABLE (PREFIX_VEX_3A0D) },
7614 { PREFIX_TABLE (PREFIX_VEX_3A0E) },
7615 { PREFIX_TABLE (PREFIX_VEX_3A0F) },
7616 /* 10 */
7617 { "(bad)", { XX } },
7618 { "(bad)", { XX } },
7619 { "(bad)", { XX } },
7620 { "(bad)", { XX } },
7621 { PREFIX_TABLE (PREFIX_VEX_3A14) },
7622 { PREFIX_TABLE (PREFIX_VEX_3A15) },
7623 { PREFIX_TABLE (PREFIX_VEX_3A16) },
7624 { PREFIX_TABLE (PREFIX_VEX_3A17) },
7625 /* 18 */
7626 { PREFIX_TABLE (PREFIX_VEX_3A18) },
7627 { PREFIX_TABLE (PREFIX_VEX_3A19) },
7628 { "(bad)", { XX } },
7629 { "(bad)", { XX } },
7630 { "(bad)", { XX } },
7631 { "(bad)", { XX } },
7632 { "(bad)", { XX } },
7633 { "(bad)", { XX } },
7634 /* 20 */
7635 { PREFIX_TABLE (PREFIX_VEX_3A20) },
7636 { PREFIX_TABLE (PREFIX_VEX_3A21) },
7637 { PREFIX_TABLE (PREFIX_VEX_3A22) },
7638 { "(bad)", { XX } },
7639 { "(bad)", { XX } },
7640 { "(bad)", { XX } },
7641 { "(bad)", { XX } },
7642 { "(bad)", { XX } },
7643 /* 28 */
7644 { "(bad)", { XX } },
7645 { "(bad)", { XX } },
7646 { "(bad)", { XX } },
7647 { "(bad)", { XX } },
7648 { "(bad)", { XX } },
7649 { "(bad)", { XX } },
7650 { "(bad)", { XX } },
7651 { "(bad)", { XX } },
7652 /* 30 */
7653 { "(bad)", { XX } },
7654 { "(bad)", { XX } },
7655 { "(bad)", { XX } },
7656 { "(bad)", { XX } },
7657 { "(bad)", { XX } },
7658 { "(bad)", { XX } },
7659 { "(bad)", { XX } },
7660 { "(bad)", { XX } },
7661 /* 38 */
7662 { "(bad)", { XX } },
7663 { "(bad)", { XX } },
7664 { "(bad)", { XX } },
7665 { "(bad)", { XX } },
7666 { "(bad)", { XX } },
7667 { "(bad)", { XX } },
7668 { "(bad)", { XX } },
7669 { "(bad)", { XX } },
7670 /* 40 */
7671 { PREFIX_TABLE (PREFIX_VEX_3A40) },
7672 { PREFIX_TABLE (PREFIX_VEX_3A41) },
7673 { PREFIX_TABLE (PREFIX_VEX_3A42) },
7674 { "(bad)", { XX } },
7675 { "(bad)", { XX } },
7676 { "(bad)", { XX } },
7677 { "(bad)", { XX } },
7678 { "(bad)", { XX } },
7679 /* 48 */
7680 { "(bad)", { XX } },
7681 { "(bad)", { XX } },
7682 { PREFIX_TABLE (PREFIX_VEX_3A4A) },
7683 { PREFIX_TABLE (PREFIX_VEX_3A4B) },
7684 { PREFIX_TABLE (PREFIX_VEX_3A4C) },
7685 { "(bad)", { XX } },
7686 { "(bad)", { XX } },
7687 { "(bad)", { XX } },
7688 /* 50 */
7689 { "(bad)", { XX } },
7690 { "(bad)", { XX } },
7691 { "(bad)", { XX } },
7692 { "(bad)", { XX } },
7693 { "(bad)", { XX } },
7694 { "(bad)", { XX } },
7695 { "(bad)", { XX } },
7696 { "(bad)", { XX } },
7697 /* 58 */
7698 { "(bad)", { XX } },
7699 { "(bad)", { XX } },
7700 { "(bad)", { XX } },
7701 { "(bad)", { XX } },
7702 { "(bad)", { XX } },
7703 { "(bad)", { XX } },
7704 { "(bad)", { XX } },
7705 { "(bad)", { XX } },
7706 /* 60 */
7707 { PREFIX_TABLE (PREFIX_VEX_3A60) },
7708 { PREFIX_TABLE (PREFIX_VEX_3A61) },
7709 { PREFIX_TABLE (PREFIX_VEX_3A62) },
7710 { PREFIX_TABLE (PREFIX_VEX_3A63) },
7711 { "(bad)", { XX } },
7712 { "(bad)", { XX } },
7713 { "(bad)", { XX } },
7714 { "(bad)", { XX } },
7715 /* 68 */
7716 { "(bad)", { XX } },
7717 { "(bad)", { XX } },
7718 { "(bad)", { XX } },
7719 { "(bad)", { XX } },
7720 { "(bad)", { XX } },
7721 { "(bad)", { XX } },
7722 { "(bad)", { XX } },
7723 { "(bad)", { XX } },
7724 /* 70 */
7725 { "(bad)", { XX } },
7726 { "(bad)", { XX } },
7727 { "(bad)", { XX } },
7728 { "(bad)", { XX } },
7729 { "(bad)", { XX } },
7730 { "(bad)", { XX } },
7731 { "(bad)", { XX } },
7732 { "(bad)", { XX } },
7733 /* 78 */
7734 { "(bad)", { XX } },
7735 { "(bad)", { XX } },
7736 { "(bad)", { XX } },
7737 { "(bad)", { XX } },
7738 { "(bad)", { XX } },
7739 { "(bad)", { XX } },
7740 { "(bad)", { XX } },
7741 { "(bad)", { XX } },
7742 /* 80 */
7743 { "(bad)", { XX } },
7744 { "(bad)", { XX } },
7745 { "(bad)", { XX } },
7746 { "(bad)", { XX } },
7747 { "(bad)", { XX } },
7748 { "(bad)", { XX } },
7749 { "(bad)", { XX } },
7750 { "(bad)", { XX } },
7751 /* 88 */
7752 { "(bad)", { XX } },
7753 { "(bad)", { XX } },
7754 { "(bad)", { XX } },
7755 { "(bad)", { XX } },
7756 { "(bad)", { XX } },
7757 { "(bad)", { XX } },
7758 { "(bad)", { XX } },
7759 { "(bad)", { XX } },
7760 /* 90 */
7761 { "(bad)", { XX } },
7762 { "(bad)", { XX } },
7763 { "(bad)", { XX } },
7764 { "(bad)", { XX } },
7765 { "(bad)", { XX } },
7766 { "(bad)", { XX } },
7767 { "(bad)", { XX } },
7768 { "(bad)", { XX } },
7769 /* 98 */
7770 { "(bad)", { XX } },
7771 { "(bad)", { XX } },
7772 { "(bad)", { XX } },
7773 { "(bad)", { XX } },
7774 { "(bad)", { XX } },
7775 { "(bad)", { XX } },
7776 { "(bad)", { XX } },
7777 { "(bad)", { XX } },
7778 /* a0 */
7779 { "(bad)", { XX } },
7780 { "(bad)", { XX } },
7781 { "(bad)", { XX } },
7782 { "(bad)", { XX } },
7783 { "(bad)", { XX } },
7784 { "(bad)", { XX } },
7785 { "(bad)", { XX } },
7786 { "(bad)", { XX } },
7787 /* a8 */
7788 { "(bad)", { XX } },
7789 { "(bad)", { XX } },
7790 { "(bad)", { XX } },
7791 { "(bad)", { XX } },
7792 { "(bad)", { XX } },
7793 { "(bad)", { XX } },
7794 { "(bad)", { XX } },
7795 { "(bad)", { XX } },
7796 /* b0 */
7797 { "(bad)", { XX } },
7798 { "(bad)", { XX } },
7799 { "(bad)", { XX } },
7800 { "(bad)", { XX } },
7801 { "(bad)", { XX } },
7802 { "(bad)", { XX } },
7803 { "(bad)", { XX } },
7804 { "(bad)", { XX } },
7805 /* b8 */
7806 { "(bad)", { XX } },
7807 { "(bad)", { XX } },
7808 { "(bad)", { XX } },
7809 { "(bad)", { XX } },
7810 { "(bad)", { XX } },
7811 { "(bad)", { XX } },
7812 { "(bad)", { XX } },
7813 { "(bad)", { XX } },
7814 /* c0 */
7815 { "(bad)", { XX } },
7816 { "(bad)", { XX } },
7817 { "(bad)", { XX } },
7818 { "(bad)", { XX } },
7819 { "(bad)", { XX } },
7820 { "(bad)", { XX } },
7821 { "(bad)", { XX } },
7822 { "(bad)", { XX } },
7823 /* c8 */
7824 { "(bad)", { XX } },
7825 { "(bad)", { XX } },
7826 { "(bad)", { XX } },
7827 { "(bad)", { XX } },
7828 { "(bad)", { XX } },
7829 { "(bad)", { XX } },
7830 { "(bad)", { XX } },
7831 { "(bad)", { XX } },
7832 /* d0 */
7833 { "(bad)", { XX } },
7834 { "(bad)", { XX } },
7835 { "(bad)", { XX } },
7836 { "(bad)", { XX } },
7837 { "(bad)", { XX } },
7838 { "(bad)", { XX } },
7839 { "(bad)", { XX } },
7840 { "(bad)", { XX } },
7841 /* d8 */
7842 { "(bad)", { XX } },
7843 { "(bad)", { XX } },
7844 { "(bad)", { XX } },
7845 { "(bad)", { XX } },
7846 { "(bad)", { XX } },
7847 { "(bad)", { XX } },
7848 { "(bad)", { XX } },
7849 { PREFIX_TABLE (PREFIX_VEX_3ADF) },
7850 /* e0 */
7851 { "(bad)", { XX } },
7852 { "(bad)", { XX } },
7853 { "(bad)", { XX } },
7854 { "(bad)", { XX } },
7855 { "(bad)", { XX } },
7856 { "(bad)", { XX } },
7857 { "(bad)", { XX } },
7858 { "(bad)", { XX } },
7859 /* e8 */
7860 { "(bad)", { XX } },
7861 { "(bad)", { XX } },
7862 { "(bad)", { XX } },
7863 { "(bad)", { XX } },
7864 { "(bad)", { XX } },
7865 { "(bad)", { XX } },
7866 { "(bad)", { XX } },
7867 { "(bad)", { XX } },
7868 /* f0 */
7869 { "(bad)", { XX } },
7870 { "(bad)", { XX } },
7871 { "(bad)", { XX } },
7872 { "(bad)", { XX } },
7873 { "(bad)", { XX } },
7874 { "(bad)", { XX } },
7875 { "(bad)", { XX } },
7876 { "(bad)", { XX } },
7877 /* f8 */
7878 { "(bad)", { XX } },
7879 { "(bad)", { XX } },
7880 { "(bad)", { XX } },
7881 { "(bad)", { XX } },
7882 { "(bad)", { XX } },
7883 { "(bad)", { XX } },
7884 { "(bad)", { XX } },
7885 { "(bad)", { XX } },
7886 },
7887 };
7888
7889 static const struct dis386 vex_len_table[][2] = {
7890 /* VEX_LEN_10_P_1 */
7891 {
7892 { "vmovss", { XMVex, Vex128, EXd } },
7893 { "(bad)", { XX } },
7894 },
7895
7896 /* VEX_LEN_10_P_3 */
7897 {
7898 { "vmovsd", { XMVex, Vex128, EXq } },
7899 { "(bad)", { XX } },
7900 },
7901
7902 /* VEX_LEN_11_P_1 */
7903 {
7904 { "vmovss", { EXdVexS, Vex128, XM } },
7905 { "(bad)", { XX } },
7906 },
7907
7908 /* VEX_LEN_11_P_3 */
7909 {
7910 { "vmovsd", { EXqVexS, Vex128, XM } },
7911 { "(bad)", { XX } },
7912 },
7913
7914 /* VEX_LEN_12_P_0_M_0 */
7915 {
7916 { "vmovlps", { XM, Vex128, EXq } },
7917 { "(bad)", { XX } },
7918 },
7919
7920 /* VEX_LEN_12_P_0_M_1 */
7921 {
7922 { "vmovhlps", { XM, Vex128, EXq } },
7923 { "(bad)", { XX } },
7924 },
7925
7926 /* VEX_LEN_12_P_2 */
7927 {
7928 { "vmovlpd", { XM, Vex128, EXq } },
7929 { "(bad)", { XX } },
7930 },
7931
7932 /* VEX_LEN_13_M_0 */
7933 {
7934 { "vmovlpX", { EXq, XM } },
7935 { "(bad)", { XX } },
7936 },
7937
7938 /* VEX_LEN_16_P_0_M_0 */
7939 {
7940 { "vmovhps", { XM, Vex128, EXq } },
7941 { "(bad)", { XX } },
7942 },
7943
7944 /* VEX_LEN_16_P_0_M_1 */
7945 {
7946 { "vmovlhps", { XM, Vex128, EXq } },
7947 { "(bad)", { XX } },
7948 },
7949
7950 /* VEX_LEN_16_P_2 */
7951 {
7952 { "vmovhpd", { XM, Vex128, EXq } },
7953 { "(bad)", { XX } },
7954 },
7955
7956 /* VEX_LEN_17_M_0 */
7957 {
7958 { "vmovhpX", { EXq, XM } },
7959 { "(bad)", { XX } },
7960 },
7961
7962 /* VEX_LEN_2A_P_1 */
7963 {
7964 { "vcvtsi2ss%LQ", { XM, Vex128, Ev } },
7965 { "(bad)", { XX } },
7966 },
7967
7968 /* VEX_LEN_2A_P_3 */
7969 {
7970 { "vcvtsi2sd%LQ", { XM, Vex128, Ev } },
7971 { "(bad)", { XX } },
7972 },
7973
7974 /* VEX_LEN_2B_M_0 */
7975 {
7976 { "vmovntpX", { Mx, XM } },
7977 { "(bad)", { XX } },
7978 },
7979
7980 /* VEX_LEN_2C_P_1 */
7981 {
7982 { "vcvttss2siY", { Gv, EXd } },
7983 { "(bad)", { XX } },
7984 },
7985
7986 /* VEX_LEN_2C_P_3 */
7987 {
7988 { "vcvttsd2siY", { Gv, EXq } },
7989 { "(bad)", { XX } },
7990 },
7991
7992 /* VEX_LEN_2D_P_1 */
7993 {
7994 { "vcvtss2siY", { Gv, EXd } },
7995 { "(bad)", { XX } },
7996 },
7997
7998 /* VEX_LEN_2D_P_3 */
7999 {
8000 { "vcvtsd2siY", { Gv, EXq } },
8001 { "(bad)", { XX } },
8002 },
8003
8004 /* VEX_LEN_2E_P_0 */
8005 {
8006 { "vucomiss", { XM, EXd } },
8007 { "(bad)", { XX } },
8008 },
8009
8010 /* VEX_LEN_2E_P_2 */
8011 {
8012 { "vucomisd", { XM, EXq } },
8013 { "(bad)", { XX } },
8014 },
8015
8016 /* VEX_LEN_2F_P_0 */
8017 {
8018 { "vcomiss", { XM, EXd } },
8019 { "(bad)", { XX } },
8020 },
8021
8022 /* VEX_LEN_2F_P_2 */
8023 {
8024 { "vcomisd", { XM, EXq } },
8025 { "(bad)", { XX } },
8026 },
8027
8028 /* VEX_LEN_51_P_1 */
8029 {
8030 { "vsqrtss", { XM, Vex128, EXd } },
8031 { "(bad)", { XX } },
8032 },
8033
8034 /* VEX_LEN_51_P_3 */
8035 {
8036 { "vsqrtsd", { XM, Vex128, EXq } },
8037 { "(bad)", { XX } },
8038 },
8039
8040 /* VEX_LEN_52_P_1 */
8041 {
8042 { "vrsqrtss", { XM, Vex128, EXd } },
8043 { "(bad)", { XX } },
8044 },
8045
8046 /* VEX_LEN_53_P_1 */
8047 {
8048 { "vrcpss", { XM, Vex128, EXd } },
8049 { "(bad)", { XX } },
8050 },
8051
8052 /* VEX_LEN_58_P_1 */
8053 {
8054 { "vaddss", { XM, Vex128, EXd } },
8055 { "(bad)", { XX } },
8056 },
8057
8058 /* VEX_LEN_58_P_3 */
8059 {
8060 { "vaddsd", { XM, Vex128, EXq } },
8061 { "(bad)", { XX } },
8062 },
8063
8064 /* VEX_LEN_59_P_1 */
8065 {
8066 { "vmulss", { XM, Vex128, EXd } },
8067 { "(bad)", { XX } },
8068 },
8069
8070 /* VEX_LEN_59_P_3 */
8071 {
8072 { "vmulsd", { XM, Vex128, EXq } },
8073 { "(bad)", { XX } },
8074 },
8075
8076 /* VEX_LEN_5A_P_1 */
8077 {
8078 { "vcvtss2sd", { XM, Vex128, EXd } },
8079 { "(bad)", { XX } },
8080 },
8081
8082 /* VEX_LEN_5A_P_3 */
8083 {
8084 { "vcvtsd2ss", { XM, Vex128, EXq } },
8085 { "(bad)", { XX } },
8086 },
8087
8088 /* VEX_LEN_5C_P_1 */
8089 {
8090 { "vsubss", { XM, Vex128, EXd } },
8091 { "(bad)", { XX } },
8092 },
8093
8094 /* VEX_LEN_5C_P_3 */
8095 {
8096 { "vsubsd", { XM, Vex128, EXq } },
8097 { "(bad)", { XX } },
8098 },
8099
8100 /* VEX_LEN_5D_P_1 */
8101 {
8102 { "vminss", { XM, Vex128, EXd } },
8103 { "(bad)", { XX } },
8104 },
8105
8106 /* VEX_LEN_5D_P_3 */
8107 {
8108 { "vminsd", { XM, Vex128, EXq } },
8109 { "(bad)", { XX } },
8110 },
8111
8112 /* VEX_LEN_5E_P_1 */
8113 {
8114 { "vdivss", { XM, Vex128, EXd } },
8115 { "(bad)", { XX } },
8116 },
8117
8118 /* VEX_LEN_5E_P_3 */
8119 {
8120 { "vdivsd", { XM, Vex128, EXq } },
8121 { "(bad)", { XX } },
8122 },
8123
8124 /* VEX_LEN_5F_P_1 */
8125 {
8126 { "vmaxss", { XM, Vex128, EXd } },
8127 { "(bad)", { XX } },
8128 },
8129
8130 /* VEX_LEN_5F_P_3 */
8131 {
8132 { "vmaxsd", { XM, Vex128, EXq } },
8133 { "(bad)", { XX } },
8134 },
8135
8136 /* VEX_LEN_60_P_2 */
8137 {
8138 { "vpunpcklbw", { XM, Vex128, EXx } },
8139 { "(bad)", { XX } },
8140 },
8141
8142 /* VEX_LEN_61_P_2 */
8143 {
8144 { "vpunpcklwd", { XM, Vex128, EXx } },
8145 { "(bad)", { XX } },
8146 },
8147
8148 /* VEX_LEN_62_P_2 */
8149 {
8150 { "vpunpckldq", { XM, Vex128, EXx } },
8151 { "(bad)", { XX } },
8152 },
8153
8154 /* VEX_LEN_63_P_2 */
8155 {
8156 { "vpacksswb", { XM, Vex128, EXx } },
8157 { "(bad)", { XX } },
8158 },
8159
8160 /* VEX_LEN_64_P_2 */
8161 {
8162 { "vpcmpgtb", { XM, Vex128, EXx } },
8163 { "(bad)", { XX } },
8164 },
8165
8166 /* VEX_LEN_65_P_2 */
8167 {
8168 { "vpcmpgtw", { XM, Vex128, EXx } },
8169 { "(bad)", { XX } },
8170 },
8171
8172 /* VEX_LEN_66_P_2 */
8173 {
8174 { "vpcmpgtd", { XM, Vex128, EXx } },
8175 { "(bad)", { XX } },
8176 },
8177
8178 /* VEX_LEN_67_P_2 */
8179 {
8180 { "vpackuswb", { XM, Vex128, EXx } },
8181 { "(bad)", { XX } },
8182 },
8183
8184 /* VEX_LEN_68_P_2 */
8185 {
8186 { "vpunpckhbw", { XM, Vex128, EXx } },
8187 { "(bad)", { XX } },
8188 },
8189
8190 /* VEX_LEN_69_P_2 */
8191 {
8192 { "vpunpckhwd", { XM, Vex128, EXx } },
8193 { "(bad)", { XX } },
8194 },
8195
8196 /* VEX_LEN_6A_P_2 */
8197 {
8198 { "vpunpckhdq", { XM, Vex128, EXx } },
8199 { "(bad)", { XX } },
8200 },
8201
8202 /* VEX_LEN_6B_P_2 */
8203 {
8204 { "vpackssdw", { XM, Vex128, EXx } },
8205 { "(bad)", { XX } },
8206 },
8207
8208 /* VEX_LEN_6C_P_2 */
8209 {
8210 { "vpunpcklqdq", { XM, Vex128, EXx } },
8211 { "(bad)", { XX } },
8212 },
8213
8214 /* VEX_LEN_6D_P_2 */
8215 {
8216 { "vpunpckhqdq", { XM, Vex128, EXx } },
8217 { "(bad)", { XX } },
8218 },
8219
8220 /* VEX_LEN_6E_P_2 */
8221 {
8222 { "vmovK", { XM, Edq } },
8223 { "(bad)", { XX } },
8224 },
8225
8226 /* VEX_LEN_70_P_1 */
8227 {
8228 { "vpshufhw", { XM, EXx, Ib } },
8229 { "(bad)", { XX } },
8230 },
8231
8232 /* VEX_LEN_70_P_2 */
8233 {
8234 { "vpshufd", { XM, EXx, Ib } },
8235 { "(bad)", { XX } },
8236 },
8237
8238 /* VEX_LEN_70_P_3 */
8239 {
8240 { "vpshuflw", { XM, EXx, Ib } },
8241 { "(bad)", { XX } },
8242 },
8243
8244 /* VEX_LEN_71_R_2_P_2 */
8245 {
8246 { "vpsrlw", { Vex128, XS, Ib } },
8247 { "(bad)", { XX } },
8248 },
8249
8250 /* VEX_LEN_71_R_4_P_2 */
8251 {
8252 { "vpsraw", { Vex128, XS, Ib } },
8253 { "(bad)", { XX } },
8254 },
8255
8256 /* VEX_LEN_71_R_6_P_2 */
8257 {
8258 { "vpsllw", { Vex128, XS, Ib } },
8259 { "(bad)", { XX } },
8260 },
8261
8262 /* VEX_LEN_72_R_2_P_2 */
8263 {
8264 { "vpsrld", { Vex128, XS, Ib } },
8265 { "(bad)", { XX } },
8266 },
8267
8268 /* VEX_LEN_72_R_4_P_2 */
8269 {
8270 { "vpsrad", { Vex128, XS, Ib } },
8271 { "(bad)", { XX } },
8272 },
8273
8274 /* VEX_LEN_72_R_6_P_2 */
8275 {
8276 { "vpslld", { Vex128, XS, Ib } },
8277 { "(bad)", { XX } },
8278 },
8279
8280 /* VEX_LEN_73_R_2_P_2 */
8281 {
8282 { "vpsrlq", { Vex128, XS, Ib } },
8283 { "(bad)", { XX } },
8284 },
8285
8286 /* VEX_LEN_73_R_3_P_2 */
8287 {
8288 { "vpsrldq", { Vex128, XS, Ib } },
8289 { "(bad)", { XX } },
8290 },
8291
8292 /* VEX_LEN_73_R_6_P_2 */
8293 {
8294 { "vpsllq", { Vex128, XS, Ib } },
8295 { "(bad)", { XX } },
8296 },
8297
8298 /* VEX_LEN_73_R_7_P_2 */
8299 {
8300 { "vpslldq", { Vex128, XS, Ib } },
8301 { "(bad)", { XX } },
8302 },
8303
8304 /* VEX_LEN_74_P_2 */
8305 {
8306 { "vpcmpeqb", { XM, Vex128, EXx } },
8307 { "(bad)", { XX } },
8308 },
8309
8310 /* VEX_LEN_75_P_2 */
8311 {
8312 { "vpcmpeqw", { XM, Vex128, EXx } },
8313 { "(bad)", { XX } },
8314 },
8315
8316 /* VEX_LEN_76_P_2 */
8317 {
8318 { "vpcmpeqd", { XM, Vex128, EXx } },
8319 { "(bad)", { XX } },
8320 },
8321
8322 /* VEX_LEN_7E_P_1 */
8323 {
8324 { "vmovq", { XM, EXq } },
8325 { "(bad)", { XX } },
8326 },
8327
8328 /* VEX_LEN_7E_P_2 */
8329 {
8330 { "vmovK", { Edq, XM } },
8331 { "(bad)", { XX } },
8332 },
8333
8334 /* VEX_LEN_AE_R_2_M0 */
8335 {
8336 { "vldmxcsr", { Md } },
8337 { "(bad)", { XX } },
8338 },
8339
8340 /* VEX_LEN_AE_R_3_M0 */
8341 {
8342 { "vstmxcsr", { Md } },
8343 { "(bad)", { XX } },
8344 },
8345
8346 /* VEX_LEN_C2_P_1 */
8347 {
8348 { "vcmpss", { XM, Vex128, EXd, VCMP } },
8349 { "(bad)", { XX } },
8350 },
8351
8352 /* VEX_LEN_C2_P_3 */
8353 {
8354 { "vcmpsd", { XM, Vex128, EXq, VCMP } },
8355 { "(bad)", { XX } },
8356 },
8357
8358 /* VEX_LEN_C4_P_2 */
8359 {
8360 { "vpinsrw", { XM, Vex128, Edqw, Ib } },
8361 { "(bad)", { XX } },
8362 },
8363
8364 /* VEX_LEN_C5_P_2 */
8365 {
8366 { "vpextrw", { Gdq, XS, Ib } },
8367 { "(bad)", { XX } },
8368 },
8369
8370 /* VEX_LEN_D1_P_2 */
8371 {
8372 { "vpsrlw", { XM, Vex128, EXx } },
8373 { "(bad)", { XX } },
8374 },
8375
8376 /* VEX_LEN_D2_P_2 */
8377 {
8378 { "vpsrld", { XM, Vex128, EXx } },
8379 { "(bad)", { XX } },
8380 },
8381
8382 /* VEX_LEN_D3_P_2 */
8383 {
8384 { "vpsrlq", { XM, Vex128, EXx } },
8385 { "(bad)", { XX } },
8386 },
8387
8388 /* VEX_LEN_D4_P_2 */
8389 {
8390 { "vpaddq", { XM, Vex128, EXx } },
8391 { "(bad)", { XX } },
8392 },
8393
8394 /* VEX_LEN_D5_P_2 */
8395 {
8396 { "vpmullw", { XM, Vex128, EXx } },
8397 { "(bad)", { XX } },
8398 },
8399
8400 /* VEX_LEN_D6_P_2 */
8401 {
8402 { "vmovq", { EXqS, XM } },
8403 { "(bad)", { XX } },
8404 },
8405
8406 /* VEX_LEN_D7_P_2_M_1 */
8407 {
8408 { "vpmovmskb", { Gdq, XS } },
8409 { "(bad)", { XX } },
8410 },
8411
8412 /* VEX_LEN_D8_P_2 */
8413 {
8414 { "vpsubusb", { XM, Vex128, EXx } },
8415 { "(bad)", { XX } },
8416 },
8417
8418 /* VEX_LEN_D9_P_2 */
8419 {
8420 { "vpsubusw", { XM, Vex128, EXx } },
8421 { "(bad)", { XX } },
8422 },
8423
8424 /* VEX_LEN_DA_P_2 */
8425 {
8426 { "vpminub", { XM, Vex128, EXx } },
8427 { "(bad)", { XX } },
8428 },
8429
8430 /* VEX_LEN_DB_P_2 */
8431 {
8432 { "vpand", { XM, Vex128, EXx } },
8433 { "(bad)", { XX } },
8434 },
8435
8436 /* VEX_LEN_DC_P_2 */
8437 {
8438 { "vpaddusb", { XM, Vex128, EXx } },
8439 { "(bad)", { XX } },
8440 },
8441
8442 /* VEX_LEN_DD_P_2 */
8443 {
8444 { "vpaddusw", { XM, Vex128, EXx } },
8445 { "(bad)", { XX } },
8446 },
8447
8448 /* VEX_LEN_DE_P_2 */
8449 {
8450 { "vpmaxub", { XM, Vex128, EXx } },
8451 { "(bad)", { XX } },
8452 },
8453
8454 /* VEX_LEN_DF_P_2 */
8455 {
8456 { "vpandn", { XM, Vex128, EXx } },
8457 { "(bad)", { XX } },
8458 },
8459
8460 /* VEX_LEN_E0_P_2 */
8461 {
8462 { "vpavgb", { XM, Vex128, EXx } },
8463 { "(bad)", { XX } },
8464 },
8465
8466 /* VEX_LEN_E1_P_2 */
8467 {
8468 { "vpsraw", { XM, Vex128, EXx } },
8469 { "(bad)", { XX } },
8470 },
8471
8472 /* VEX_LEN_E2_P_2 */
8473 {
8474 { "vpsrad", { XM, Vex128, EXx } },
8475 { "(bad)", { XX } },
8476 },
8477
8478 /* VEX_LEN_E3_P_2 */
8479 {
8480 { "vpavgw", { XM, Vex128, EXx } },
8481 { "(bad)", { XX } },
8482 },
8483
8484 /* VEX_LEN_E4_P_2 */
8485 {
8486 { "vpmulhuw", { XM, Vex128, EXx } },
8487 { "(bad)", { XX } },
8488 },
8489
8490 /* VEX_LEN_E5_P_2 */
8491 {
8492 { "vpmulhw", { XM, Vex128, EXx } },
8493 { "(bad)", { XX } },
8494 },
8495
8496 /* VEX_LEN_E7_P_2_M_0 */
8497 {
8498 { "vmovntdq", { Mx, XM } },
8499 { "(bad)", { XX } },
8500 },
8501
8502 /* VEX_LEN_E8_P_2 */
8503 {
8504 { "vpsubsb", { XM, Vex128, EXx } },
8505 { "(bad)", { XX } },
8506 },
8507
8508 /* VEX_LEN_E9_P_2 */
8509 {
8510 { "vpsubsw", { XM, Vex128, EXx } },
8511 { "(bad)", { XX } },
8512 },
8513
8514 /* VEX_LEN_EA_P_2 */
8515 {
8516 { "vpminsw", { XM, Vex128, EXx } },
8517 { "(bad)", { XX } },
8518 },
8519
8520 /* VEX_LEN_EB_P_2 */
8521 {
8522 { "vpor", { XM, Vex128, EXx } },
8523 { "(bad)", { XX } },
8524 },
8525
8526 /* VEX_LEN_EC_P_2 */
8527 {
8528 { "vpaddsb", { XM, Vex128, EXx } },
8529 { "(bad)", { XX } },
8530 },
8531
8532 /* VEX_LEN_ED_P_2 */
8533 {
8534 { "vpaddsw", { XM, Vex128, EXx } },
8535 { "(bad)", { XX } },
8536 },
8537
8538 /* VEX_LEN_EE_P_2 */
8539 {
8540 { "vpmaxsw", { XM, Vex128, EXx } },
8541 { "(bad)", { XX } },
8542 },
8543
8544 /* VEX_LEN_EF_P_2 */
8545 {
8546 { "vpxor", { XM, Vex128, EXx } },
8547 { "(bad)", { XX } },
8548 },
8549
8550 /* VEX_LEN_F1_P_2 */
8551 {
8552 { "vpsllw", { XM, Vex128, EXx } },
8553 { "(bad)", { XX } },
8554 },
8555
8556 /* VEX_LEN_F2_P_2 */
8557 {
8558 { "vpslld", { XM, Vex128, EXx } },
8559 { "(bad)", { XX } },
8560 },
8561
8562 /* VEX_LEN_F3_P_2 */
8563 {
8564 { "vpsllq", { XM, Vex128, EXx } },
8565 { "(bad)", { XX } },
8566 },
8567
8568 /* VEX_LEN_F4_P_2 */
8569 {
8570 { "vpmuludq", { XM, Vex128, EXx } },
8571 { "(bad)", { XX } },
8572 },
8573
8574 /* VEX_LEN_F5_P_2 */
8575 {
8576 { "vpmaddwd", { XM, Vex128, EXx } },
8577 { "(bad)", { XX } },
8578 },
8579
8580 /* VEX_LEN_F6_P_2 */
8581 {
8582 { "vpsadbw", { XM, Vex128, EXx } },
8583 { "(bad)", { XX } },
8584 },
8585
8586 /* VEX_LEN_F7_P_2 */
8587 {
8588 { "vmaskmovdqu", { XM, XS } },
8589 { "(bad)", { XX } },
8590 },
8591
8592 /* VEX_LEN_F8_P_2 */
8593 {
8594 { "vpsubb", { XM, Vex128, EXx } },
8595 { "(bad)", { XX } },
8596 },
8597
8598 /* VEX_LEN_F9_P_2 */
8599 {
8600 { "vpsubw", { XM, Vex128, EXx } },
8601 { "(bad)", { XX } },
8602 },
8603
8604 /* VEX_LEN_FA_P_2 */
8605 {
8606 { "vpsubd", { XM, Vex128, EXx } },
8607 { "(bad)", { XX } },
8608 },
8609
8610 /* VEX_LEN_FB_P_2 */
8611 {
8612 { "vpsubq", { XM, Vex128, EXx } },
8613 { "(bad)", { XX } },
8614 },
8615
8616 /* VEX_LEN_FC_P_2 */
8617 {
8618 { "vpaddb", { XM, Vex128, EXx } },
8619 { "(bad)", { XX } },
8620 },
8621
8622 /* VEX_LEN_FD_P_2 */
8623 {
8624 { "vpaddw", { XM, Vex128, EXx } },
8625 { "(bad)", { XX } },
8626 },
8627
8628 /* VEX_LEN_FE_P_2 */
8629 {
8630 { "vpaddd", { XM, Vex128, EXx } },
8631 { "(bad)", { XX } },
8632 },
8633
8634 /* VEX_LEN_3800_P_2 */
8635 {
8636 { "vpshufb", { XM, Vex128, EXx } },
8637 { "(bad)", { XX } },
8638 },
8639
8640 /* VEX_LEN_3801_P_2 */
8641 {
8642 { "vphaddw", { XM, Vex128, EXx } },
8643 { "(bad)", { XX } },
8644 },
8645
8646 /* VEX_LEN_3802_P_2 */
8647 {
8648 { "vphaddd", { XM, Vex128, EXx } },
8649 { "(bad)", { XX } },
8650 },
8651
8652 /* VEX_LEN_3803_P_2 */
8653 {
8654 { "vphaddsw", { XM, Vex128, EXx } },
8655 { "(bad)", { XX } },
8656 },
8657
8658 /* VEX_LEN_3804_P_2 */
8659 {
8660 { "vpmaddubsw", { XM, Vex128, EXx } },
8661 { "(bad)", { XX } },
8662 },
8663
8664 /* VEX_LEN_3805_P_2 */
8665 {
8666 { "vphsubw", { XM, Vex128, EXx } },
8667 { "(bad)", { XX } },
8668 },
8669
8670 /* VEX_LEN_3806_P_2 */
8671 {
8672 { "vphsubd", { XM, Vex128, EXx } },
8673 { "(bad)", { XX } },
8674 },
8675
8676 /* VEX_LEN_3807_P_2 */
8677 {
8678 { "vphsubsw", { XM, Vex128, EXx } },
8679 { "(bad)", { XX } },
8680 },
8681
8682 /* VEX_LEN_3808_P_2 */
8683 {
8684 { "vpsignb", { XM, Vex128, EXx } },
8685 { "(bad)", { XX } },
8686 },
8687
8688 /* VEX_LEN_3809_P_2 */
8689 {
8690 { "vpsignw", { XM, Vex128, EXx } },
8691 { "(bad)", { XX } },
8692 },
8693
8694 /* VEX_LEN_380A_P_2 */
8695 {
8696 { "vpsignd", { XM, Vex128, EXx } },
8697 { "(bad)", { XX } },
8698 },
8699
8700 /* VEX_LEN_380B_P_2 */
8701 {
8702 { "vpmulhrsw", { XM, Vex128, EXx } },
8703 { "(bad)", { XX } },
8704 },
8705
8706 /* VEX_LEN_3819_P_2_M_0 */
8707 {
8708 { "(bad)", { XX } },
8709 { "vbroadcastsd", { XM, Mq } },
8710 },
8711
8712 /* VEX_LEN_381A_P_2_M_0 */
8713 {
8714 { "(bad)", { XX } },
8715 { "vbroadcastf128", { XM, Mxmm } },
8716 },
8717
8718 /* VEX_LEN_381C_P_2 */
8719 {
8720 { "vpabsb", { XM, EXx } },
8721 { "(bad)", { XX } },
8722 },
8723
8724 /* VEX_LEN_381D_P_2 */
8725 {
8726 { "vpabsw", { XM, EXx } },
8727 { "(bad)", { XX } },
8728 },
8729
8730 /* VEX_LEN_381E_P_2 */
8731 {
8732 { "vpabsd", { XM, EXx } },
8733 { "(bad)", { XX } },
8734 },
8735
8736 /* VEX_LEN_3820_P_2 */
8737 {
8738 { "vpmovsxbw", { XM, EXq } },
8739 { "(bad)", { XX } },
8740 },
8741
8742 /* VEX_LEN_3821_P_2 */
8743 {
8744 { "vpmovsxbd", { XM, EXd } },
8745 { "(bad)", { XX } },
8746 },
8747
8748 /* VEX_LEN_3822_P_2 */
8749 {
8750 { "vpmovsxbq", { XM, EXw } },
8751 { "(bad)", { XX } },
8752 },
8753
8754 /* VEX_LEN_3823_P_2 */
8755 {
8756 { "vpmovsxwd", { XM, EXq } },
8757 { "(bad)", { XX } },
8758 },
8759
8760 /* VEX_LEN_3824_P_2 */
8761 {
8762 { "vpmovsxwq", { XM, EXd } },
8763 { "(bad)", { XX } },
8764 },
8765
8766 /* VEX_LEN_3825_P_2 */
8767 {
8768 { "vpmovsxdq", { XM, EXq } },
8769 { "(bad)", { XX } },
8770 },
8771
8772 /* VEX_LEN_3828_P_2 */
8773 {
8774 { "vpmuldq", { XM, Vex128, EXx } },
8775 { "(bad)", { XX } },
8776 },
8777
8778 /* VEX_LEN_3829_P_2 */
8779 {
8780 { "vpcmpeqq", { XM, Vex128, EXx } },
8781 { "(bad)", { XX } },
8782 },
8783
8784 /* VEX_LEN_382A_P_2_M_0 */
8785 {
8786 { "vmovntdqa", { XM, Mx } },
8787 { "(bad)", { XX } },
8788 },
8789
8790 /* VEX_LEN_382B_P_2 */
8791 {
8792 { "vpackusdw", { XM, Vex128, EXx } },
8793 { "(bad)", { XX } },
8794 },
8795
8796 /* VEX_LEN_3830_P_2 */
8797 {
8798 { "vpmovzxbw", { XM, EXq } },
8799 { "(bad)", { XX } },
8800 },
8801
8802 /* VEX_LEN_3831_P_2 */
8803 {
8804 { "vpmovzxbd", { XM, EXd } },
8805 { "(bad)", { XX } },
8806 },
8807
8808 /* VEX_LEN_3832_P_2 */
8809 {
8810 { "vpmovzxbq", { XM, EXw } },
8811 { "(bad)", { XX } },
8812 },
8813
8814 /* VEX_LEN_3833_P_2 */
8815 {
8816 { "vpmovzxwd", { XM, EXq } },
8817 { "(bad)", { XX } },
8818 },
8819
8820 /* VEX_LEN_3834_P_2 */
8821 {
8822 { "vpmovzxwq", { XM, EXd } },
8823 { "(bad)", { XX } },
8824 },
8825
8826 /* VEX_LEN_3835_P_2 */
8827 {
8828 { "vpmovzxdq", { XM, EXq } },
8829 { "(bad)", { XX } },
8830 },
8831
8832 /* VEX_LEN_3837_P_2 */
8833 {
8834 { "vpcmpgtq", { XM, Vex128, EXx } },
8835 { "(bad)", { XX } },
8836 },
8837
8838 /* VEX_LEN_3838_P_2 */
8839 {
8840 { "vpminsb", { XM, Vex128, EXx } },
8841 { "(bad)", { XX } },
8842 },
8843
8844 /* VEX_LEN_3839_P_2 */
8845 {
8846 { "vpminsd", { XM, Vex128, EXx } },
8847 { "(bad)", { XX } },
8848 },
8849
8850 /* VEX_LEN_383A_P_2 */
8851 {
8852 { "vpminuw", { XM, Vex128, EXx } },
8853 { "(bad)", { XX } },
8854 },
8855
8856 /* VEX_LEN_383B_P_2 */
8857 {
8858 { "vpminud", { XM, Vex128, EXx } },
8859 { "(bad)", { XX } },
8860 },
8861
8862 /* VEX_LEN_383C_P_2 */
8863 {
8864 { "vpmaxsb", { XM, Vex128, EXx } },
8865 { "(bad)", { XX } },
8866 },
8867
8868 /* VEX_LEN_383D_P_2 */
8869 {
8870 { "vpmaxsd", { XM, Vex128, EXx } },
8871 { "(bad)", { XX } },
8872 },
8873
8874 /* VEX_LEN_383E_P_2 */
8875 {
8876 { "vpmaxuw", { XM, Vex128, EXx } },
8877 { "(bad)", { XX } },
8878 },
8879
8880 /* VEX_LEN_383F_P_2 */
8881 {
8882 { "vpmaxud", { XM, Vex128, EXx } },
8883 { "(bad)", { XX } },
8884 },
8885
8886 /* VEX_LEN_3840_P_2 */
8887 {
8888 { "vpmulld", { XM, Vex128, EXx } },
8889 { "(bad)", { XX } },
8890 },
8891
8892 /* VEX_LEN_3841_P_2 */
8893 {
8894 { "vphminposuw", { XM, EXx } },
8895 { "(bad)", { XX } },
8896 },
8897
8898 /* VEX_LEN_38DB_P_2 */
8899 {
8900 { "vaesimc", { XM, EXx } },
8901 { "(bad)", { XX } },
8902 },
8903
8904 /* VEX_LEN_38DC_P_2 */
8905 {
8906 { "vaesenc", { XM, Vex128, EXx } },
8907 { "(bad)", { XX } },
8908 },
8909
8910 /* VEX_LEN_38DD_P_2 */
8911 {
8912 { "vaesenclast", { XM, Vex128, EXx } },
8913 { "(bad)", { XX } },
8914 },
8915
8916 /* VEX_LEN_38DE_P_2 */
8917 {
8918 { "vaesdec", { XM, Vex128, EXx } },
8919 { "(bad)", { XX } },
8920 },
8921
8922 /* VEX_LEN_38DF_P_2 */
8923 {
8924 { "vaesdeclast", { XM, Vex128, EXx } },
8925 { "(bad)", { XX } },
8926 },
8927
8928 /* VEX_LEN_3A06_P_2 */
8929 {
8930 { "(bad)", { XX } },
8931 { "vperm2f128", { XM, Vex256, EXx, Ib } },
8932 },
8933
8934 /* VEX_LEN_3A0A_P_2 */
8935 {
8936 { "vroundss", { XM, Vex128, EXd, Ib } },
8937 { "(bad)", { XX } },
8938 },
8939
8940 /* VEX_LEN_3A0B_P_2 */
8941 {
8942 { "vroundsd", { XM, Vex128, EXq, Ib } },
8943 { "(bad)", { XX } },
8944 },
8945
8946 /* VEX_LEN_3A0E_P_2 */
8947 {
8948 { "vpblendw", { XM, Vex128, EXx, Ib } },
8949 { "(bad)", { XX } },
8950 },
8951
8952 /* VEX_LEN_3A0F_P_2 */
8953 {
8954 { "vpalignr", { XM, Vex128, EXx, Ib } },
8955 { "(bad)", { XX } },
8956 },
8957
8958 /* VEX_LEN_3A14_P_2 */
8959 {
8960 { "vpextrb", { Edqb, XM, Ib } },
8961 { "(bad)", { XX } },
8962 },
8963
8964 /* VEX_LEN_3A15_P_2 */
8965 {
8966 { "vpextrw", { Edqw, XM, Ib } },
8967 { "(bad)", { XX } },
8968 },
8969
8970 /* VEX_LEN_3A16_P_2 */
8971 {
8972 { "vpextrK", { Edq, XM, Ib } },
8973 { "(bad)", { XX } },
8974 },
8975
8976 /* VEX_LEN_3A17_P_2 */
8977 {
8978 { "vextractps", { Edqd, XM, Ib } },
8979 { "(bad)", { XX } },
8980 },
8981
8982 /* VEX_LEN_3A18_P_2 */
8983 {
8984 { "(bad)", { XX } },
8985 { "vinsertf128", { XM, Vex256, EXxmm, Ib } },
8986 },
8987
8988 /* VEX_LEN_3A19_P_2 */
8989 {
8990 { "(bad)", { XX } },
8991 { "vextractf128", { EXxmm, XM, Ib } },
8992 },
8993
8994 /* VEX_LEN_3A20_P_2 */
8995 {
8996 { "vpinsrb", { XM, Vex128, Edqb, Ib } },
8997 { "(bad)", { XX } },
8998 },
8999
9000 /* VEX_LEN_3A21_P_2 */
9001 {
9002 { "vinsertps", { XM, Vex128, EXd, Ib } },
9003 { "(bad)", { XX } },
9004 },
9005
9006 /* VEX_LEN_3A22_P_2 */
9007 {
9008 { "vpinsrK", { XM, Vex128, Edq, Ib } },
9009 { "(bad)", { XX } },
9010 },
9011
9012 /* VEX_LEN_3A41_P_2 */
9013 {
9014 { "vdppd", { XM, Vex128, EXx, Ib } },
9015 { "(bad)", { XX } },
9016 },
9017
9018 /* VEX_LEN_3A42_P_2 */
9019 {
9020 { "vmpsadbw", { XM, Vex128, EXx, Ib } },
9021 { "(bad)", { XX } },
9022 },
9023
9024 /* VEX_LEN_3A4C_P_2 */
9025 {
9026 { "vpblendvb", { XM, Vex128, EXx, XMVexI4 } },
9027 { "(bad)", { XX } },
9028 },
9029
9030 /* VEX_LEN_3A60_P_2 */
9031 {
9032 { "vpcmpestrm", { XM, EXx, Ib } },
9033 { "(bad)", { XX } },
9034 },
9035
9036 /* VEX_LEN_3A61_P_2 */
9037 {
9038 { "vpcmpestri", { XM, EXx, Ib } },
9039 { "(bad)", { XX } },
9040 },
9041
9042 /* VEX_LEN_3A62_P_2 */
9043 {
9044 { "vpcmpistrm", { XM, EXx, Ib } },
9045 { "(bad)", { XX } },
9046 },
9047
9048 /* VEX_LEN_3A63_P_2 */
9049 {
9050 { "vpcmpistri", { XM, EXx, Ib } },
9051 { "(bad)", { XX } },
9052 },
9053
9054 /* VEX_LEN_3ADF_P_2 */
9055 {
9056 { "vaeskeygenassist", { XM, EXx, Ib } },
9057 { "(bad)", { XX } },
9058 },
9059 };
9060
9061 static const struct dis386 mod_table[][2] = {
9062 {
9063 /* MOD_8D */
9064 { "leaS", { Gv, M } },
9065 { "(bad)", { XX } },
9066 },
9067 {
9068 /* MOD_0F01_REG_0 */
9069 { X86_64_TABLE (X86_64_0F01_REG_0) },
9070 { RM_TABLE (RM_0F01_REG_0) },
9071 },
9072 {
9073 /* MOD_0F01_REG_1 */
9074 { X86_64_TABLE (X86_64_0F01_REG_1) },
9075 { RM_TABLE (RM_0F01_REG_1) },
9076 },
9077 {
9078 /* MOD_0F01_REG_2 */
9079 { X86_64_TABLE (X86_64_0F01_REG_2) },
9080 { RM_TABLE (RM_0F01_REG_2) },
9081 },
9082 {
9083 /* MOD_0F01_REG_3 */
9084 { X86_64_TABLE (X86_64_0F01_REG_3) },
9085 { RM_TABLE (RM_0F01_REG_3) },
9086 },
9087 {
9088 /* MOD_0F01_REG_7 */
9089 { "invlpg", { Mb } },
9090 { RM_TABLE (RM_0F01_REG_7) },
9091 },
9092 {
9093 /* MOD_0F12_PREFIX_0 */
9094 { "movlps", { XM, EXq } },
9095 { "movhlps", { XM, EXq } },
9096 },
9097 {
9098 /* MOD_0F13 */
9099 { "movlpX", { EXq, XM } },
9100 { "(bad)", { XX } },
9101 },
9102 {
9103 /* MOD_0F16_PREFIX_0 */
9104 { "movhps", { XM, EXq } },
9105 { "movlhps", { XM, EXq } },
9106 },
9107 {
9108 /* MOD_0F17 */
9109 { "movhpX", { EXq, XM } },
9110 { "(bad)", { XX } },
9111 },
9112 {
9113 /* MOD_0F18_REG_0 */
9114 { "prefetchnta", { Mb } },
9115 { "(bad)", { XX } },
9116 },
9117 {
9118 /* MOD_0F18_REG_1 */
9119 { "prefetcht0", { Mb } },
9120 { "(bad)", { XX } },
9121 },
9122 {
9123 /* MOD_0F18_REG_2 */
9124 { "prefetcht1", { Mb } },
9125 { "(bad)", { XX } },
9126 },
9127 {
9128 /* MOD_0F18_REG_3 */
9129 { "prefetcht2", { Mb } },
9130 { "(bad)", { XX } },
9131 },
9132 {
9133 /* MOD_0F20 */
9134 { "(bad)", { XX } },
9135 { "movZ", { Rm, Cm } },
9136 },
9137 {
9138 /* MOD_0F21 */
9139 { "(bad)", { XX } },
9140 { "movZ", { Rm, Dm } },
9141 },
9142 {
9143 /* MOD_0F22 */
9144 { "(bad)", { XX } },
9145 { "movZ", { Cm, Rm } },
9146 },
9147 {
9148 /* MOD_0F23 */
9149 { "(bad)", { XX } },
9150 { "movZ", { Dm, Rm } },
9151 },
9152 {
9153 /* MOD_0F24 */
9154 { THREE_BYTE_TABLE (THREE_BYTE_0F24) },
9155 { "movL", { Rd, Td } },
9156 },
9157 {
9158 /* MOD_0F26 */
9159 { "(bad)", { XX } },
9160 { "movL", { Td, Rd } },
9161 },
9162 {
9163 /* MOD_0F2B_PREFIX_0 */
9164 {"movntps", { Mx, XM } },
9165 { "(bad)", { XX } },
9166 },
9167 {
9168 /* MOD_0F2B_PREFIX_1 */
9169 {"movntss", { Md, XM } },
9170 { "(bad)", { XX } },
9171 },
9172 {
9173 /* MOD_0F2B_PREFIX_2 */
9174 {"movntpd", { Mx, XM } },
9175 { "(bad)", { XX } },
9176 },
9177 {
9178 /* MOD_0F2B_PREFIX_3 */
9179 {"movntsd", { Mq, XM } },
9180 { "(bad)", { XX } },
9181 },
9182 {
9183 /* MOD_0F51 */
9184 { "(bad)", { XX } },
9185 { "movmskpX", { Gdq, XS } },
9186 },
9187 {
9188 /* MOD_0F71_REG_2 */
9189 { "(bad)", { XX } },
9190 { "psrlw", { MS, Ib } },
9191 },
9192 {
9193 /* MOD_0F71_REG_4 */
9194 { "(bad)", { XX } },
9195 { "psraw", { MS, Ib } },
9196 },
9197 {
9198 /* MOD_0F71_REG_6 */
9199 { "(bad)", { XX } },
9200 { "psllw", { MS, Ib } },
9201 },
9202 {
9203 /* MOD_0F72_REG_2 */
9204 { "(bad)", { XX } },
9205 { "psrld", { MS, Ib } },
9206 },
9207 {
9208 /* MOD_0F72_REG_4 */
9209 { "(bad)", { XX } },
9210 { "psrad", { MS, Ib } },
9211 },
9212 {
9213 /* MOD_0F72_REG_6 */
9214 { "(bad)", { XX } },
9215 { "pslld", { MS, Ib } },
9216 },
9217 {
9218 /* MOD_0F73_REG_2 */
9219 { "(bad)", { XX } },
9220 { "psrlq", { MS, Ib } },
9221 },
9222 {
9223 /* MOD_0F73_REG_3 */
9224 { "(bad)", { XX } },
9225 { PREFIX_TABLE (PREFIX_0F73_REG_3) },
9226 },
9227 {
9228 /* MOD_0F73_REG_6 */
9229 { "(bad)", { XX } },
9230 { "psllq", { MS, Ib } },
9231 },
9232 {
9233 /* MOD_0F73_REG_7 */
9234 { "(bad)", { XX } },
9235 { PREFIX_TABLE (PREFIX_0F73_REG_7) },
9236 },
9237 {
9238 /* MOD_0FAE_REG_0 */
9239 { "fxsave", { M } },
9240 { "(bad)", { XX } },
9241 },
9242 {
9243 /* MOD_0FAE_REG_1 */
9244 { "fxrstor", { M } },
9245 { "(bad)", { XX } },
9246 },
9247 {
9248 /* MOD_0FAE_REG_2 */
9249 { "ldmxcsr", { Md } },
9250 { "(bad)", { XX } },
9251 },
9252 {
9253 /* MOD_0FAE_REG_3 */
9254 { "stmxcsr", { Md } },
9255 { "(bad)", { XX } },
9256 },
9257 {
9258 /* MOD_0FAE_REG_4 */
9259 { "xsave", { M } },
9260 { "(bad)", { XX } },
9261 },
9262 {
9263 /* MOD_0FAE_REG_5 */
9264 { "xrstor", { M } },
9265 { RM_TABLE (RM_0FAE_REG_5) },
9266 },
9267 {
9268 /* MOD_0FAE_REG_6 */
9269 { "xsaveopt", { M } },
9270 { RM_TABLE (RM_0FAE_REG_6) },
9271 },
9272 {
9273 /* MOD_0FAE_REG_7 */
9274 { "clflush", { Mb } },
9275 { RM_TABLE (RM_0FAE_REG_7) },
9276 },
9277 {
9278 /* MOD_0FB2 */
9279 { "lssS", { Gv, Mp } },
9280 { "(bad)", { XX } },
9281 },
9282 {
9283 /* MOD_0FB4 */
9284 { "lfsS", { Gv, Mp } },
9285 { "(bad)", { XX } },
9286 },
9287 {
9288 /* MOD_0FB5 */
9289 { "lgsS", { Gv, Mp } },
9290 { "(bad)", { XX } },
9291 },
9292 {
9293 /* MOD_0FC7_REG_6 */
9294 { PREFIX_TABLE (PREFIX_0FC7_REG_6) },
9295 { "(bad)", { XX } },
9296 },
9297 {
9298 /* MOD_0FC7_REG_7 */
9299 { "vmptrst", { Mq } },
9300 { "(bad)", { XX } },
9301 },
9302 {
9303 /* MOD_0FD7 */
9304 { "(bad)", { XX } },
9305 { "pmovmskb", { Gdq, MS } },
9306 },
9307 {
9308 /* MOD_0FE7_PREFIX_2 */
9309 { "movntdq", { Mx, XM } },
9310 { "(bad)", { XX } },
9311 },
9312 {
9313 /* MOD_0FF0_PREFIX_3 */
9314 { "lddqu", { XM, M } },
9315 { "(bad)", { XX } },
9316 },
9317 {
9318 /* MOD_0F382A_PREFIX_2 */
9319 { "movntdqa", { XM, Mx } },
9320 { "(bad)", { XX } },
9321 },
9322 {
9323 /* MOD_62_32BIT */
9324 { "bound{S|}", { Gv, Ma } },
9325 { "(bad)", { XX } },
9326 },
9327 {
9328 /* MOD_C4_32BIT */
9329 { "lesS", { Gv, Mp } },
9330 { VEX_C4_TABLE (VEX_0F) },
9331 },
9332 {
9333 /* MOD_C5_32BIT */
9334 { "ldsS", { Gv, Mp } },
9335 { VEX_C5_TABLE (VEX_0F) },
9336 },
9337 {
9338 /* MOD_VEX_12_PREFIX_0 */
9339 { VEX_LEN_TABLE (VEX_LEN_12_P_0_M_0) },
9340 { VEX_LEN_TABLE (VEX_LEN_12_P_0_M_1) },
9341 },
9342 {
9343 /* MOD_VEX_13 */
9344 { VEX_LEN_TABLE (VEX_LEN_13_M_0) },
9345 { "(bad)", { XX } },
9346 },
9347 {
9348 /* MOD_VEX_16_PREFIX_0 */
9349 { VEX_LEN_TABLE (VEX_LEN_16_P_0_M_0) },
9350 { VEX_LEN_TABLE (VEX_LEN_16_P_0_M_1) },
9351 },
9352 {
9353 /* MOD_VEX_17 */
9354 { VEX_LEN_TABLE (VEX_LEN_17_M_0) },
9355 { "(bad)", { XX } },
9356 },
9357 {
9358 /* MOD_VEX_2B */
9359 { VEX_LEN_TABLE (VEX_LEN_2B_M_0) },
9360 { "(bad)", { XX } },
9361 },
9362 {
9363 /* MOD_VEX_51 */
9364 { "(bad)", { XX } },
9365 { "vmovmskpX", { Gdq, XS } },
9366 },
9367 {
9368 /* MOD_VEX_71_REG_2 */
9369 { "(bad)", { XX } },
9370 { PREFIX_TABLE (PREFIX_VEX_71_REG_2) },
9371 },
9372 {
9373 /* MOD_VEX_71_REG_4 */
9374 { "(bad)", { XX } },
9375 { PREFIX_TABLE (PREFIX_VEX_71_REG_4) },
9376 },
9377 {
9378 /* MOD_VEX_71_REG_6 */
9379 { "(bad)", { XX } },
9380 { PREFIX_TABLE (PREFIX_VEX_71_REG_6) },
9381 },
9382 {
9383 /* MOD_VEX_72_REG_2 */
9384 { "(bad)", { XX } },
9385 { PREFIX_TABLE (PREFIX_VEX_72_REG_2) },
9386 },
9387 {
9388 /* MOD_VEX_72_REG_4 */
9389 { "(bad)", { XX } },
9390 { PREFIX_TABLE (PREFIX_VEX_72_REG_4) },
9391 },
9392 {
9393 /* MOD_VEX_72_REG_6 */
9394 { "(bad)", { XX } },
9395 { PREFIX_TABLE (PREFIX_VEX_72_REG_6) },
9396 },
9397 {
9398 /* MOD_VEX_73_REG_2 */
9399 { "(bad)", { XX } },
9400 { PREFIX_TABLE (PREFIX_VEX_73_REG_2) },
9401 },
9402 {
9403 /* MOD_VEX_73_REG_3 */
9404 { "(bad)", { XX } },
9405 { PREFIX_TABLE (PREFIX_VEX_73_REG_3) },
9406 },
9407 {
9408 /* MOD_VEX_73_REG_6 */
9409 { "(bad)", { XX } },
9410 { PREFIX_TABLE (PREFIX_VEX_73_REG_6) },
9411 },
9412 {
9413 /* MOD_VEX_73_REG_7 */
9414 { "(bad)", { XX } },
9415 { PREFIX_TABLE (PREFIX_VEX_73_REG_7) },
9416 },
9417 {
9418 /* MOD_VEX_AE_REG_2 */
9419 { VEX_LEN_TABLE (VEX_LEN_AE_R_2_M_0) },
9420 { "(bad)", { XX } },
9421 },
9422 {
9423 /* MOD_VEX_AE_REG_3 */
9424 { VEX_LEN_TABLE (VEX_LEN_AE_R_3_M_0) },
9425 { "(bad)", { XX } },
9426 },
9427 {
9428 /* MOD_VEX_D7_PREFIX_2 */
9429 { "(bad)", { XX } },
9430 { VEX_LEN_TABLE (VEX_LEN_D7_P_2_M_1) },
9431 },
9432 {
9433 /* MOD_VEX_E7_PREFIX_2 */
9434 { VEX_LEN_TABLE (VEX_LEN_E7_P_2_M_0) },
9435 { "(bad)", { XX } },
9436 },
9437 {
9438 /* MOD_VEX_F0_PREFIX_3 */
9439 { "vlddqu", { XM, M } },
9440 { "(bad)", { XX } },
9441 },
9442 {
9443 /* MOD_VEX_3818_PREFIX_2 */
9444 { "vbroadcastss", { XM, Md } },
9445 { "(bad)", { XX } },
9446 },
9447 {
9448 /* MOD_VEX_3819_PREFIX_2 */
9449 { VEX_LEN_TABLE (VEX_LEN_3819_P_2_M_0) },
9450 { "(bad)", { XX } },
9451 },
9452 {
9453 /* MOD_VEX_381A_PREFIX_2 */
9454 { VEX_LEN_TABLE (VEX_LEN_381A_P_2_M_0) },
9455 { "(bad)", { XX } },
9456 },
9457 {
9458 /* MOD_VEX_382A_PREFIX_2 */
9459 { VEX_LEN_TABLE (VEX_LEN_382A_P_2_M_0) },
9460 { "(bad)", { XX } },
9461 },
9462 {
9463 /* MOD_VEX_382C_PREFIX_2 */
9464 { "vmaskmovps", { XM, Vex, Mx } },
9465 { "(bad)", { XX } },
9466 },
9467 {
9468 /* MOD_VEX_382D_PREFIX_2 */
9469 { "vmaskmovpd", { XM, Vex, Mx } },
9470 { "(bad)", { XX } },
9471 },
9472 {
9473 /* MOD_VEX_382E_PREFIX_2 */
9474 { "vmaskmovps", { Mx, Vex, XM } },
9475 { "(bad)", { XX } },
9476 },
9477 {
9478 /* MOD_VEX_382F_PREFIX_2 */
9479 { "vmaskmovpd", { Mx, Vex, XM } },
9480 { "(bad)", { XX } },
9481 },
9482 };
9483
9484 static const struct dis386 rm_table[][8] = {
9485 {
9486 /* RM_0F01_REG_0 */
9487 { "(bad)", { XX } },
9488 { "vmcall", { Skip_MODRM } },
9489 { "vmlaunch", { Skip_MODRM } },
9490 { "vmresume", { Skip_MODRM } },
9491 { "vmxoff", { Skip_MODRM } },
9492 { "(bad)", { XX } },
9493 { "(bad)", { XX } },
9494 { "(bad)", { XX } },
9495 },
9496 {
9497 /* RM_0F01_REG_1 */
9498 { "monitor", { { OP_Monitor, 0 } } },
9499 { "mwait", { { OP_Mwait, 0 } } },
9500 { "(bad)", { XX } },
9501 { "(bad)", { XX } },
9502 { "(bad)", { XX } },
9503 { "(bad)", { XX } },
9504 { "(bad)", { XX } },
9505 { "(bad)", { XX } },
9506 },
9507 {
9508 /* RM_0F01_REG_2 */
9509 { "xgetbv", { Skip_MODRM } },
9510 { "xsetbv", { Skip_MODRM } },
9511 { "(bad)", { XX } },
9512 { "(bad)", { XX } },
9513 { "(bad)", { XX } },
9514 { "(bad)", { XX } },
9515 { "(bad)", { XX } },
9516 { "(bad)", { XX } },
9517 },
9518 {
9519 /* RM_0F01_REG_3 */
9520 { "vmrun", { Skip_MODRM } },
9521 { "vmmcall", { Skip_MODRM } },
9522 { "vmload", { Skip_MODRM } },
9523 { "vmsave", { Skip_MODRM } },
9524 { "stgi", { Skip_MODRM } },
9525 { "clgi", { Skip_MODRM } },
9526 { "skinit", { Skip_MODRM } },
9527 { "invlpga", { Skip_MODRM } },
9528 },
9529 {
9530 /* RM_0F01_REG_7 */
9531 { "swapgs", { Skip_MODRM } },
9532 { "rdtscp", { Skip_MODRM } },
9533 { "(bad)", { XX } },
9534 { "(bad)", { XX } },
9535 { "(bad)", { XX } },
9536 { "(bad)", { XX } },
9537 { "(bad)", { XX } },
9538 { "(bad)", { XX } },
9539 },
9540 {
9541 /* RM_0FAE_REG_5 */
9542 { "lfence", { Skip_MODRM } },
9543 { "(bad)", { XX } },
9544 { "(bad)", { XX } },
9545 { "(bad)", { XX } },
9546 { "(bad)", { XX } },
9547 { "(bad)", { XX } },
9548 { "(bad)", { XX } },
9549 { "(bad)", { XX } },
9550 },
9551 {
9552 /* RM_0FAE_REG_6 */
9553 { "mfence", { Skip_MODRM } },
9554 { "(bad)", { XX } },
9555 { "(bad)", { XX } },
9556 { "(bad)", { XX } },
9557 { "(bad)", { XX } },
9558 { "(bad)", { XX } },
9559 { "(bad)", { XX } },
9560 { "(bad)", { XX } },
9561 },
9562 {
9563 /* RM_0FAE_REG_7 */
9564 { "sfence", { Skip_MODRM } },
9565 { "(bad)", { XX } },
9566 { "(bad)", { XX } },
9567 { "(bad)", { XX } },
9568 { "(bad)", { XX } },
9569 { "(bad)", { XX } },
9570 { "(bad)", { XX } },
9571 { "(bad)", { XX } },
9572 },
9573 };
9574
9575 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
9576
9577 static void
9578 ckprefix (void)
9579 {
9580 int newrex;
9581 rex = 0;
9582 rex_original = 0;
9583 rex_ignored = 0;
9584 prefixes = 0;
9585 used_prefixes = 0;
9586 rex_used = 0;
9587 while (1)
9588 {
9589 FETCH_DATA (the_info, codep + 1);
9590 newrex = 0;
9591 switch (*codep)
9592 {
9593 /* REX prefixes family. */
9594 case 0x40:
9595 case 0x41:
9596 case 0x42:
9597 case 0x43:
9598 case 0x44:
9599 case 0x45:
9600 case 0x46:
9601 case 0x47:
9602 case 0x48:
9603 case 0x49:
9604 case 0x4a:
9605 case 0x4b:
9606 case 0x4c:
9607 case 0x4d:
9608 case 0x4e:
9609 case 0x4f:
9610 if (address_mode == mode_64bit)
9611 newrex = *codep;
9612 else
9613 return;
9614 break;
9615 case 0xf3:
9616 prefixes |= PREFIX_REPZ;
9617 break;
9618 case 0xf2:
9619 prefixes |= PREFIX_REPNZ;
9620 break;
9621 case 0xf0:
9622 prefixes |= PREFIX_LOCK;
9623 break;
9624 case 0x2e:
9625 prefixes |= PREFIX_CS;
9626 break;
9627 case 0x36:
9628 prefixes |= PREFIX_SS;
9629 break;
9630 case 0x3e:
9631 prefixes |= PREFIX_DS;
9632 break;
9633 case 0x26:
9634 prefixes |= PREFIX_ES;
9635 break;
9636 case 0x64:
9637 prefixes |= PREFIX_FS;
9638 break;
9639 case 0x65:
9640 prefixes |= PREFIX_GS;
9641 break;
9642 case 0x66:
9643 prefixes |= PREFIX_DATA;
9644 break;
9645 case 0x67:
9646 prefixes |= PREFIX_ADDR;
9647 break;
9648 case FWAIT_OPCODE:
9649 /* fwait is really an instruction. If there are prefixes
9650 before the fwait, they belong to the fwait, *not* to the
9651 following instruction. */
9652 if (prefixes || rex)
9653 {
9654 prefixes |= PREFIX_FWAIT;
9655 codep++;
9656 return;
9657 }
9658 prefixes = PREFIX_FWAIT;
9659 break;
9660 default:
9661 return;
9662 }
9663 /* Rex is ignored when followed by another prefix. */
9664 if (rex)
9665 {
9666 rex_used = rex;
9667 return;
9668 }
9669 rex = newrex;
9670 rex_original = rex;
9671 codep++;
9672 }
9673 }
9674
9675 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
9676 prefix byte. */
9677
9678 static const char *
9679 prefix_name (int pref, int sizeflag)
9680 {
9681 static const char *rexes [16] =
9682 {
9683 "rex", /* 0x40 */
9684 "rex.B", /* 0x41 */
9685 "rex.X", /* 0x42 */
9686 "rex.XB", /* 0x43 */
9687 "rex.R", /* 0x44 */
9688 "rex.RB", /* 0x45 */
9689 "rex.RX", /* 0x46 */
9690 "rex.RXB", /* 0x47 */
9691 "rex.W", /* 0x48 */
9692 "rex.WB", /* 0x49 */
9693 "rex.WX", /* 0x4a */
9694 "rex.WXB", /* 0x4b */
9695 "rex.WR", /* 0x4c */
9696 "rex.WRB", /* 0x4d */
9697 "rex.WRX", /* 0x4e */
9698 "rex.WRXB", /* 0x4f */
9699 };
9700
9701 switch (pref)
9702 {
9703 /* REX prefixes family. */
9704 case 0x40:
9705 case 0x41:
9706 case 0x42:
9707 case 0x43:
9708 case 0x44:
9709 case 0x45:
9710 case 0x46:
9711 case 0x47:
9712 case 0x48:
9713 case 0x49:
9714 case 0x4a:
9715 case 0x4b:
9716 case 0x4c:
9717 case 0x4d:
9718 case 0x4e:
9719 case 0x4f:
9720 return rexes [pref - 0x40];
9721 case 0xf3:
9722 return "repz";
9723 case 0xf2:
9724 return "repnz";
9725 case 0xf0:
9726 return "lock";
9727 case 0x2e:
9728 return "cs";
9729 case 0x36:
9730 return "ss";
9731 case 0x3e:
9732 return "ds";
9733 case 0x26:
9734 return "es";
9735 case 0x64:
9736 return "fs";
9737 case 0x65:
9738 return "gs";
9739 case 0x66:
9740 return (sizeflag & DFLAG) ? "data16" : "data32";
9741 case 0x67:
9742 if (address_mode == mode_64bit)
9743 return (sizeflag & AFLAG) ? "addr32" : "addr64";
9744 else
9745 return (sizeflag & AFLAG) ? "addr16" : "addr32";
9746 case FWAIT_OPCODE:
9747 return "fwait";
9748 default:
9749 return NULL;
9750 }
9751 }
9752
9753 static char op_out[MAX_OPERANDS][100];
9754 static int op_ad, op_index[MAX_OPERANDS];
9755 static int two_source_ops;
9756 static bfd_vma op_address[MAX_OPERANDS];
9757 static bfd_vma op_riprel[MAX_OPERANDS];
9758 static bfd_vma start_pc;
9759
9760 /*
9761 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
9762 * (see topic "Redundant prefixes" in the "Differences from 8086"
9763 * section of the "Virtual 8086 Mode" chapter.)
9764 * 'pc' should be the address of this instruction, it will
9765 * be used to print the target address if this is a relative jump or call
9766 * The function returns the length of this instruction in bytes.
9767 */
9768
9769 static char intel_syntax;
9770 static char intel_mnemonic = !SYSV386_COMPAT;
9771 static char open_char;
9772 static char close_char;
9773 static char separator_char;
9774 static char scale_char;
9775
9776 /* Here for backwards compatibility. When gdb stops using
9777 print_insn_i386_att and print_insn_i386_intel these functions can
9778 disappear, and print_insn_i386 be merged into print_insn. */
9779 int
9780 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
9781 {
9782 intel_syntax = 0;
9783
9784 return print_insn (pc, info);
9785 }
9786
9787 int
9788 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
9789 {
9790 intel_syntax = 1;
9791
9792 return print_insn (pc, info);
9793 }
9794
9795 int
9796 print_insn_i386 (bfd_vma pc, disassemble_info *info)
9797 {
9798 intel_syntax = -1;
9799
9800 return print_insn (pc, info);
9801 }
9802
9803 void
9804 print_i386_disassembler_options (FILE *stream)
9805 {
9806 fprintf (stream, _("\n\
9807 The following i386/x86-64 specific disassembler options are supported for use\n\
9808 with the -M switch (multiple options should be separated by commas):\n"));
9809
9810 fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n"));
9811 fprintf (stream, _(" i386 Disassemble in 32bit mode\n"));
9812 fprintf (stream, _(" i8086 Disassemble in 16bit mode\n"));
9813 fprintf (stream, _(" att Display instruction in AT&T syntax\n"));
9814 fprintf (stream, _(" intel Display instruction in Intel syntax\n"));
9815 fprintf (stream, _(" att-mnemonic\n"
9816 " Display instruction in AT&T mnemonic\n"));
9817 fprintf (stream, _(" intel-mnemonic\n"
9818 " Display instruction in Intel mnemonic\n"));
9819 fprintf (stream, _(" addr64 Assume 64bit address size\n"));
9820 fprintf (stream, _(" addr32 Assume 32bit address size\n"));
9821 fprintf (stream, _(" addr16 Assume 16bit address size\n"));
9822 fprintf (stream, _(" data32 Assume 32bit data size\n"));
9823 fprintf (stream, _(" data16 Assume 16bit data size\n"));
9824 fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n"));
9825 }
9826
9827 /* Get a pointer to struct dis386 with a valid name. */
9828
9829 static const struct dis386 *
9830 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
9831 {
9832 int index, vex_table_index;
9833
9834 if (dp->name != NULL)
9835 return dp;
9836
9837 switch (dp->op[0].bytemode)
9838 {
9839 case USE_REG_TABLE:
9840 dp = &reg_table[dp->op[1].bytemode][modrm.reg];
9841 break;
9842
9843 case USE_MOD_TABLE:
9844 index = modrm.mod == 0x3 ? 1 : 0;
9845 dp = &mod_table[dp->op[1].bytemode][index];
9846 break;
9847
9848 case USE_RM_TABLE:
9849 dp = &rm_table[dp->op[1].bytemode][modrm.rm];
9850 break;
9851
9852 case USE_PREFIX_TABLE:
9853 if (need_vex)
9854 {
9855 /* The prefix in VEX is implicit. */
9856 switch (vex.prefix)
9857 {
9858 case 0:
9859 index = 0;
9860 break;
9861 case REPE_PREFIX_OPCODE:
9862 index = 1;
9863 break;
9864 case DATA_PREFIX_OPCODE:
9865 index = 2;
9866 break;
9867 case REPNE_PREFIX_OPCODE:
9868 index = 3;
9869 break;
9870 default:
9871 abort ();
9872 break;
9873 }
9874 }
9875 else
9876 {
9877 index = 0;
9878 used_prefixes |= (prefixes & PREFIX_REPZ);
9879 if (prefixes & PREFIX_REPZ)
9880 {
9881 index = 1;
9882 repz_prefix = NULL;
9883 }
9884 else
9885 {
9886 /* We should check PREFIX_REPNZ and PREFIX_REPZ before
9887 PREFIX_DATA. */
9888 used_prefixes |= (prefixes & PREFIX_REPNZ);
9889 if (prefixes & PREFIX_REPNZ)
9890 {
9891 index = 3;
9892 repnz_prefix = NULL;
9893 }
9894 else
9895 {
9896 used_prefixes |= (prefixes & PREFIX_DATA);
9897 if (prefixes & PREFIX_DATA)
9898 {
9899 index = 2;
9900 data_prefix = NULL;
9901 }
9902 }
9903 }
9904 }
9905 dp = &prefix_table[dp->op[1].bytemode][index];
9906 break;
9907
9908 case USE_X86_64_TABLE:
9909 index = address_mode == mode_64bit ? 1 : 0;
9910 dp = &x86_64_table[dp->op[1].bytemode][index];
9911 break;
9912
9913 case USE_3BYTE_TABLE:
9914 FETCH_DATA (info, codep + 2);
9915 index = *codep++;
9916 dp = &three_byte_table[dp->op[1].bytemode][index];
9917 modrm.mod = (*codep >> 6) & 3;
9918 modrm.reg = (*codep >> 3) & 7;
9919 modrm.rm = *codep & 7;
9920 break;
9921
9922 case USE_VEX_LEN_TABLE:
9923 if (!need_vex)
9924 abort ();
9925
9926 switch (vex.length)
9927 {
9928 case 128:
9929 index = 0;
9930 break;
9931 case 256:
9932 index = 1;
9933 break;
9934 default:
9935 abort ();
9936 break;
9937 }
9938
9939 dp = &vex_len_table[dp->op[1].bytemode][index];
9940 break;
9941
9942 case USE_VEX_C4_TABLE:
9943 FETCH_DATA (info, codep + 3);
9944 /* All bits in the REX prefix are ignored. */
9945 rex_ignored = rex;
9946 rex = ~(*codep >> 5) & 0x7;
9947 switch ((*codep & 0x1f))
9948 {
9949 default:
9950 BadOp ();
9951 case 0x1:
9952 vex_table_index = 0;
9953 break;
9954 case 0x2:
9955 vex_table_index = 1;
9956 break;
9957 case 0x3:
9958 vex_table_index = 2;
9959 break;
9960 }
9961 codep++;
9962 vex.w = *codep & 0x80;
9963 if (vex.w && address_mode == mode_64bit)
9964 rex |= REX_W;
9965
9966 vex.register_specifier = (~(*codep >> 3)) & 0xf;
9967 if (address_mode != mode_64bit
9968 && vex.register_specifier > 0x7)
9969 BadOp ();
9970
9971 vex.length = (*codep & 0x4) ? 256 : 128;
9972 switch ((*codep & 0x3))
9973 {
9974 case 0:
9975 vex.prefix = 0;
9976 break;
9977 case 1:
9978 vex.prefix = DATA_PREFIX_OPCODE;
9979 break;
9980 case 2:
9981 vex.prefix = REPE_PREFIX_OPCODE;
9982 break;
9983 case 3:
9984 vex.prefix = REPNE_PREFIX_OPCODE;
9985 break;
9986 }
9987 need_vex = 1;
9988 need_vex_reg = 1;
9989 codep++;
9990 index = *codep++;
9991 dp = &vex_table[vex_table_index][index];
9992 /* There is no MODRM byte for VEX [82|77]. */
9993 if (index != 0x77 && index != 0x82)
9994 {
9995 FETCH_DATA (info, codep + 1);
9996 modrm.mod = (*codep >> 6) & 3;
9997 modrm.reg = (*codep >> 3) & 7;
9998 modrm.rm = *codep & 7;
9999 }
10000 break;
10001
10002 case USE_VEX_C5_TABLE:
10003 FETCH_DATA (info, codep + 2);
10004 /* All bits in the REX prefix are ignored. */
10005 rex_ignored = rex;
10006 rex = (*codep & 0x80) ? 0 : REX_R;
10007
10008 vex.register_specifier = (~(*codep >> 3)) & 0xf;
10009 if (address_mode != mode_64bit
10010 && vex.register_specifier > 0x7)
10011 BadOp ();
10012
10013 vex.length = (*codep & 0x4) ? 256 : 128;
10014 switch ((*codep & 0x3))
10015 {
10016 case 0:
10017 vex.prefix = 0;
10018 break;
10019 case 1:
10020 vex.prefix = DATA_PREFIX_OPCODE;
10021 break;
10022 case 2:
10023 vex.prefix = REPE_PREFIX_OPCODE;
10024 break;
10025 case 3:
10026 vex.prefix = REPNE_PREFIX_OPCODE;
10027 break;
10028 }
10029 need_vex = 1;
10030 need_vex_reg = 1;
10031 codep++;
10032 index = *codep++;
10033 dp = &vex_table[dp->op[1].bytemode][index];
10034 /* There is no MODRM byte for VEX [82|77]. */
10035 if (index != 0x77 && index != 0x82)
10036 {
10037 FETCH_DATA (info, codep + 1);
10038 modrm.mod = (*codep >> 6) & 3;
10039 modrm.reg = (*codep >> 3) & 7;
10040 modrm.rm = *codep & 7;
10041 }
10042 break;
10043
10044 default:
10045 oappend (INTERNAL_DISASSEMBLER_ERROR);
10046 return NULL;
10047 }
10048
10049 if (dp->name != NULL)
10050 return dp;
10051 else
10052 return get_valid_dis386 (dp, info);
10053 }
10054
10055 static int
10056 print_insn (bfd_vma pc, disassemble_info *info)
10057 {
10058 const struct dis386 *dp;
10059 int i;
10060 char *op_txt[MAX_OPERANDS];
10061 int needcomma;
10062 int sizeflag;
10063 const char *p;
10064 struct dis_private priv;
10065 unsigned char op;
10066 char prefix_obuf[32];
10067 char *prefix_obufp;
10068
10069 if (info->mach == bfd_mach_x86_64_intel_syntax
10070 || info->mach == bfd_mach_x86_64)
10071 address_mode = mode_64bit;
10072 else
10073 address_mode = mode_32bit;
10074
10075 if (intel_syntax == (char) -1)
10076 intel_syntax = (info->mach == bfd_mach_i386_i386_intel_syntax
10077 || info->mach == bfd_mach_x86_64_intel_syntax);
10078
10079 if (info->mach == bfd_mach_i386_i386
10080 || info->mach == bfd_mach_x86_64
10081 || info->mach == bfd_mach_i386_i386_intel_syntax
10082 || info->mach == bfd_mach_x86_64_intel_syntax)
10083 priv.orig_sizeflag = AFLAG | DFLAG;
10084 else if (info->mach == bfd_mach_i386_i8086)
10085 priv.orig_sizeflag = 0;
10086 else
10087 abort ();
10088
10089 for (p = info->disassembler_options; p != NULL; )
10090 {
10091 if (CONST_STRNEQ (p, "x86-64"))
10092 {
10093 address_mode = mode_64bit;
10094 priv.orig_sizeflag = AFLAG | DFLAG;
10095 }
10096 else if (CONST_STRNEQ (p, "i386"))
10097 {
10098 address_mode = mode_32bit;
10099 priv.orig_sizeflag = AFLAG | DFLAG;
10100 }
10101 else if (CONST_STRNEQ (p, "i8086"))
10102 {
10103 address_mode = mode_16bit;
10104 priv.orig_sizeflag = 0;
10105 }
10106 else if (CONST_STRNEQ (p, "intel"))
10107 {
10108 intel_syntax = 1;
10109 if (CONST_STRNEQ (p + 5, "-mnemonic"))
10110 intel_mnemonic = 1;
10111 }
10112 else if (CONST_STRNEQ (p, "att"))
10113 {
10114 intel_syntax = 0;
10115 if (CONST_STRNEQ (p + 3, "-mnemonic"))
10116 intel_mnemonic = 0;
10117 }
10118 else if (CONST_STRNEQ (p, "addr"))
10119 {
10120 if (address_mode == mode_64bit)
10121 {
10122 if (p[4] == '3' && p[5] == '2')
10123 priv.orig_sizeflag &= ~AFLAG;
10124 else if (p[4] == '6' && p[5] == '4')
10125 priv.orig_sizeflag |= AFLAG;
10126 }
10127 else
10128 {
10129 if (p[4] == '1' && p[5] == '6')
10130 priv.orig_sizeflag &= ~AFLAG;
10131 else if (p[4] == '3' && p[5] == '2')
10132 priv.orig_sizeflag |= AFLAG;
10133 }
10134 }
10135 else if (CONST_STRNEQ (p, "data"))
10136 {
10137 if (p[4] == '1' && p[5] == '6')
10138 priv.orig_sizeflag &= ~DFLAG;
10139 else if (p[4] == '3' && p[5] == '2')
10140 priv.orig_sizeflag |= DFLAG;
10141 }
10142 else if (CONST_STRNEQ (p, "suffix"))
10143 priv.orig_sizeflag |= SUFFIX_ALWAYS;
10144
10145 p = strchr (p, ',');
10146 if (p != NULL)
10147 p++;
10148 }
10149
10150 if (intel_syntax)
10151 {
10152 names64 = intel_names64;
10153 names32 = intel_names32;
10154 names16 = intel_names16;
10155 names8 = intel_names8;
10156 names8rex = intel_names8rex;
10157 names_seg = intel_names_seg;
10158 index64 = intel_index64;
10159 index32 = intel_index32;
10160 index16 = intel_index16;
10161 open_char = '[';
10162 close_char = ']';
10163 separator_char = '+';
10164 scale_char = '*';
10165 }
10166 else
10167 {
10168 names64 = att_names64;
10169 names32 = att_names32;
10170 names16 = att_names16;
10171 names8 = att_names8;
10172 names8rex = att_names8rex;
10173 names_seg = att_names_seg;
10174 index64 = att_index64;
10175 index32 = att_index32;
10176 index16 = att_index16;
10177 open_char = '(';
10178 close_char = ')';
10179 separator_char = ',';
10180 scale_char = ',';
10181 }
10182
10183 /* The output looks better if we put 7 bytes on a line, since that
10184 puts most long word instructions on a single line. */
10185 info->bytes_per_line = 7;
10186
10187 info->private_data = &priv;
10188 priv.max_fetched = priv.the_buffer;
10189 priv.insn_start = pc;
10190
10191 obuf[0] = 0;
10192 for (i = 0; i < MAX_OPERANDS; ++i)
10193 {
10194 op_out[i][0] = 0;
10195 op_index[i] = -1;
10196 }
10197
10198 the_info = info;
10199 start_pc = pc;
10200 start_codep = priv.the_buffer;
10201 codep = priv.the_buffer;
10202
10203 if (setjmp (priv.bailout) != 0)
10204 {
10205 const char *name;
10206
10207 /* Getting here means we tried for data but didn't get it. That
10208 means we have an incomplete instruction of some sort. Just
10209 print the first byte as a prefix or a .byte pseudo-op. */
10210 if (codep > priv.the_buffer)
10211 {
10212 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
10213 if (name != NULL)
10214 (*info->fprintf_func) (info->stream, "%s", name);
10215 else
10216 {
10217 /* Just print the first byte as a .byte instruction. */
10218 (*info->fprintf_func) (info->stream, ".byte 0x%x",
10219 (unsigned int) priv.the_buffer[0]);
10220 }
10221
10222 return 1;
10223 }
10224
10225 return -1;
10226 }
10227
10228 obufp = obuf;
10229 ckprefix ();
10230
10231 insn_codep = codep;
10232 sizeflag = priv.orig_sizeflag;
10233
10234 FETCH_DATA (info, codep + 1);
10235 two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
10236
10237 if (((prefixes & PREFIX_FWAIT)
10238 && ((*codep < 0xd8) || (*codep > 0xdf)))
10239 || (rex && rex_used))
10240 {
10241 const char *name;
10242
10243 /* fwait not followed by floating point instruction, or rex followed
10244 by other prefixes. Print the first prefix. */
10245 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
10246 if (name == NULL)
10247 name = INTERNAL_DISASSEMBLER_ERROR;
10248 (*info->fprintf_func) (info->stream, "%s", name);
10249 return 1;
10250 }
10251
10252 op = 0;
10253 if (*codep == 0x0f)
10254 {
10255 unsigned char threebyte;
10256 FETCH_DATA (info, codep + 2);
10257 threebyte = *++codep;
10258 dp = &dis386_twobyte[threebyte];
10259 need_modrm = twobyte_has_modrm[*codep];
10260 codep++;
10261 }
10262 else
10263 {
10264 dp = &dis386[*codep];
10265 need_modrm = onebyte_has_modrm[*codep];
10266 codep++;
10267 }
10268
10269 if ((prefixes & PREFIX_REPZ))
10270 {
10271 repz_prefix = "repz ";
10272 used_prefixes |= PREFIX_REPZ;
10273 }
10274 else
10275 repz_prefix = NULL;
10276
10277 if ((prefixes & PREFIX_REPNZ))
10278 {
10279 repnz_prefix = "repnz ";
10280 used_prefixes |= PREFIX_REPNZ;
10281 }
10282 else
10283 repnz_prefix = NULL;
10284
10285 if ((prefixes & PREFIX_LOCK))
10286 {
10287 lock_prefix = "lock ";
10288 used_prefixes |= PREFIX_LOCK;
10289 }
10290 else
10291 lock_prefix = NULL;
10292
10293 addr_prefix = NULL;
10294 if (prefixes & PREFIX_ADDR)
10295 {
10296 sizeflag ^= AFLAG;
10297 if (dp->op[2].bytemode != loop_jcxz_mode || intel_syntax)
10298 {
10299 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
10300 addr_prefix = "addr32 ";
10301 else
10302 addr_prefix = "addr16 ";
10303 used_prefixes |= PREFIX_ADDR;
10304 }
10305 }
10306
10307 data_prefix = NULL;
10308 if ((prefixes & PREFIX_DATA))
10309 {
10310 sizeflag ^= DFLAG;
10311 if (dp->op[2].bytemode == cond_jump_mode
10312 && dp->op[0].bytemode == v_mode
10313 && !intel_syntax)
10314 {
10315 if (sizeflag & DFLAG)
10316 data_prefix = "data32 ";
10317 else
10318 data_prefix = "data16 ";
10319 used_prefixes |= PREFIX_DATA;
10320 }
10321 }
10322
10323 if (need_modrm)
10324 {
10325 FETCH_DATA (info, codep + 1);
10326 modrm.mod = (*codep >> 6) & 3;
10327 modrm.reg = (*codep >> 3) & 7;
10328 modrm.rm = *codep & 7;
10329 }
10330
10331 if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
10332 {
10333 dofloat (sizeflag);
10334 }
10335 else
10336 {
10337 need_vex = 0;
10338 need_vex_reg = 0;
10339 vex_w_done = 0;
10340 dp = get_valid_dis386 (dp, info);
10341 if (dp != NULL && putop (dp->name, sizeflag) == 0)
10342 {
10343 for (i = 0; i < MAX_OPERANDS; ++i)
10344 {
10345 obufp = op_out[i];
10346 op_ad = MAX_OPERANDS - 1 - i;
10347 if (dp->op[i].rtn)
10348 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
10349 }
10350 }
10351 }
10352
10353 /* See if any prefixes were not used. If so, print the first one
10354 separately. If we don't do this, we'll wind up printing an
10355 instruction stream which does not precisely correspond to the
10356 bytes we are disassembling. */
10357 if ((prefixes & ~used_prefixes) != 0)
10358 {
10359 const char *name;
10360
10361 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
10362 if (name == NULL)
10363 name = INTERNAL_DISASSEMBLER_ERROR;
10364 (*info->fprintf_func) (info->stream, "%s", name);
10365 return 1;
10366 }
10367 if ((rex_original & ~rex_used) || rex_ignored)
10368 {
10369 const char *name;
10370 name = prefix_name (rex_original, priv.orig_sizeflag);
10371 if (name == NULL)
10372 name = INTERNAL_DISASSEMBLER_ERROR;
10373 (*info->fprintf_func) (info->stream, "%s ", name);
10374 }
10375
10376 prefix_obuf[0] = 0;
10377 prefix_obufp = prefix_obuf;
10378 if (lock_prefix)
10379 prefix_obufp = stpcpy (prefix_obufp, lock_prefix);
10380 if (repz_prefix)
10381 prefix_obufp = stpcpy (prefix_obufp, repz_prefix);
10382 if (repnz_prefix)
10383 prefix_obufp = stpcpy (prefix_obufp, repnz_prefix);
10384 if (addr_prefix)
10385 prefix_obufp = stpcpy (prefix_obufp, addr_prefix);
10386 if (data_prefix)
10387 prefix_obufp = stpcpy (prefix_obufp, data_prefix);
10388
10389 if (prefix_obuf[0] != 0)
10390 (*info->fprintf_func) (info->stream, "%s", prefix_obuf);
10391
10392 obufp = mnemonicendp;
10393 for (i = strlen (obuf) + strlen (prefix_obuf); i < 6; i++)
10394 oappend (" ");
10395 oappend (" ");
10396 (*info->fprintf_func) (info->stream, "%s", obuf);
10397
10398 /* The enter and bound instructions are printed with operands in the same
10399 order as the intel book; everything else is printed in reverse order. */
10400 if (intel_syntax || two_source_ops)
10401 {
10402 bfd_vma riprel;
10403
10404 for (i = 0; i < MAX_OPERANDS; ++i)
10405 op_txt[i] = op_out[i];
10406
10407 for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
10408 {
10409 op_ad = op_index[i];
10410 op_index[i] = op_index[MAX_OPERANDS - 1 - i];
10411 op_index[MAX_OPERANDS - 1 - i] = op_ad;
10412 riprel = op_riprel[i];
10413 op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
10414 op_riprel[MAX_OPERANDS - 1 - i] = riprel;
10415 }
10416 }
10417 else
10418 {
10419 for (i = 0; i < MAX_OPERANDS; ++i)
10420 op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
10421 }
10422
10423 needcomma = 0;
10424 for (i = 0; i < MAX_OPERANDS; ++i)
10425 if (*op_txt[i])
10426 {
10427 if (needcomma)
10428 (*info->fprintf_func) (info->stream, ",");
10429 if (op_index[i] != -1 && !op_riprel[i])
10430 (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
10431 else
10432 (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
10433 needcomma = 1;
10434 }
10435
10436 for (i = 0; i < MAX_OPERANDS; i++)
10437 if (op_index[i] != -1 && op_riprel[i])
10438 {
10439 (*info->fprintf_func) (info->stream, " # ");
10440 (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep
10441 + op_address[op_index[i]]), info);
10442 break;
10443 }
10444 return codep - priv.the_buffer;
10445 }
10446
10447 static const char *float_mem[] = {
10448 /* d8 */
10449 "fadd{s|}",
10450 "fmul{s|}",
10451 "fcom{s|}",
10452 "fcomp{s|}",
10453 "fsub{s|}",
10454 "fsubr{s|}",
10455 "fdiv{s|}",
10456 "fdivr{s|}",
10457 /* d9 */
10458 "fld{s|}",
10459 "(bad)",
10460 "fst{s|}",
10461 "fstp{s|}",
10462 "fldenvIC",
10463 "fldcw",
10464 "fNstenvIC",
10465 "fNstcw",
10466 /* da */
10467 "fiadd{l|}",
10468 "fimul{l|}",
10469 "ficom{l|}",
10470 "ficomp{l|}",
10471 "fisub{l|}",
10472 "fisubr{l|}",
10473 "fidiv{l|}",
10474 "fidivr{l|}",
10475 /* db */
10476 "fild{l|}",
10477 "fisttp{l|}",
10478 "fist{l|}",
10479 "fistp{l|}",
10480 "(bad)",
10481 "fld{t||t|}",
10482 "(bad)",
10483 "fstp{t||t|}",
10484 /* dc */
10485 "fadd{l|}",
10486 "fmul{l|}",
10487 "fcom{l|}",
10488 "fcomp{l|}",
10489 "fsub{l|}",
10490 "fsubr{l|}",
10491 "fdiv{l|}",
10492 "fdivr{l|}",
10493 /* dd */
10494 "fld{l|}",
10495 "fisttp{ll|}",
10496 "fst{l||}",
10497 "fstp{l|}",
10498 "frstorIC",
10499 "(bad)",
10500 "fNsaveIC",
10501 "fNstsw",
10502 /* de */
10503 "fiadd",
10504 "fimul",
10505 "ficom",
10506 "ficomp",
10507 "fisub",
10508 "fisubr",
10509 "fidiv",
10510 "fidivr",
10511 /* df */
10512 "fild",
10513 "fisttp",
10514 "fist",
10515 "fistp",
10516 "fbld",
10517 "fild{ll|}",
10518 "fbstp",
10519 "fistp{ll|}",
10520 };
10521
10522 static const unsigned char float_mem_mode[] = {
10523 /* d8 */
10524 d_mode,
10525 d_mode,
10526 d_mode,
10527 d_mode,
10528 d_mode,
10529 d_mode,
10530 d_mode,
10531 d_mode,
10532 /* d9 */
10533 d_mode,
10534 0,
10535 d_mode,
10536 d_mode,
10537 0,
10538 w_mode,
10539 0,
10540 w_mode,
10541 /* da */
10542 d_mode,
10543 d_mode,
10544 d_mode,
10545 d_mode,
10546 d_mode,
10547 d_mode,
10548 d_mode,
10549 d_mode,
10550 /* db */
10551 d_mode,
10552 d_mode,
10553 d_mode,
10554 d_mode,
10555 0,
10556 t_mode,
10557 0,
10558 t_mode,
10559 /* dc */
10560 q_mode,
10561 q_mode,
10562 q_mode,
10563 q_mode,
10564 q_mode,
10565 q_mode,
10566 q_mode,
10567 q_mode,
10568 /* dd */
10569 q_mode,
10570 q_mode,
10571 q_mode,
10572 q_mode,
10573 0,
10574 0,
10575 0,
10576 w_mode,
10577 /* de */
10578 w_mode,
10579 w_mode,
10580 w_mode,
10581 w_mode,
10582 w_mode,
10583 w_mode,
10584 w_mode,
10585 w_mode,
10586 /* df */
10587 w_mode,
10588 w_mode,
10589 w_mode,
10590 w_mode,
10591 t_mode,
10592 q_mode,
10593 t_mode,
10594 q_mode
10595 };
10596
10597 #define ST { OP_ST, 0 }
10598 #define STi { OP_STi, 0 }
10599
10600 #define FGRPd9_2 NULL, { { NULL, 0 } }
10601 #define FGRPd9_4 NULL, { { NULL, 1 } }
10602 #define FGRPd9_5 NULL, { { NULL, 2 } }
10603 #define FGRPd9_6 NULL, { { NULL, 3 } }
10604 #define FGRPd9_7 NULL, { { NULL, 4 } }
10605 #define FGRPda_5 NULL, { { NULL, 5 } }
10606 #define FGRPdb_4 NULL, { { NULL, 6 } }
10607 #define FGRPde_3 NULL, { { NULL, 7 } }
10608 #define FGRPdf_4 NULL, { { NULL, 8 } }
10609
10610 static const struct dis386 float_reg[][8] = {
10611 /* d8 */
10612 {
10613 { "fadd", { ST, STi } },
10614 { "fmul", { ST, STi } },
10615 { "fcom", { STi } },
10616 { "fcomp", { STi } },
10617 { "fsub", { ST, STi } },
10618 { "fsubr", { ST, STi } },
10619 { "fdiv", { ST, STi } },
10620 { "fdivr", { ST, STi } },
10621 },
10622 /* d9 */
10623 {
10624 { "fld", { STi } },
10625 { "fxch", { STi } },
10626 { FGRPd9_2 },
10627 { "(bad)", { XX } },
10628 { FGRPd9_4 },
10629 { FGRPd9_5 },
10630 { FGRPd9_6 },
10631 { FGRPd9_7 },
10632 },
10633 /* da */
10634 {
10635 { "fcmovb", { ST, STi } },
10636 { "fcmove", { ST, STi } },
10637 { "fcmovbe",{ ST, STi } },
10638 { "fcmovu", { ST, STi } },
10639 { "(bad)", { XX } },
10640 { FGRPda_5 },
10641 { "(bad)", { XX } },
10642 { "(bad)", { XX } },
10643 },
10644 /* db */
10645 {
10646 { "fcmovnb",{ ST, STi } },
10647 { "fcmovne",{ ST, STi } },
10648 { "fcmovnbe",{ ST, STi } },
10649 { "fcmovnu",{ ST, STi } },
10650 { FGRPdb_4 },
10651 { "fucomi", { ST, STi } },
10652 { "fcomi", { ST, STi } },
10653 { "(bad)", { XX } },
10654 },
10655 /* dc */
10656 {
10657 { "fadd", { STi, ST } },
10658 { "fmul", { STi, ST } },
10659 { "(bad)", { XX } },
10660 { "(bad)", { XX } },
10661 { "fsub!M", { STi, ST } },
10662 { "fsubM", { STi, ST } },
10663 { "fdiv!M", { STi, ST } },
10664 { "fdivM", { STi, ST } },
10665 },
10666 /* dd */
10667 {
10668 { "ffree", { STi } },
10669 { "(bad)", { XX } },
10670 { "fst", { STi } },
10671 { "fstp", { STi } },
10672 { "fucom", { STi } },
10673 { "fucomp", { STi } },
10674 { "(bad)", { XX } },
10675 { "(bad)", { XX } },
10676 },
10677 /* de */
10678 {
10679 { "faddp", { STi, ST } },
10680 { "fmulp", { STi, ST } },
10681 { "(bad)", { XX } },
10682 { FGRPde_3 },
10683 { "fsub!Mp", { STi, ST } },
10684 { "fsubMp", { STi, ST } },
10685 { "fdiv!Mp", { STi, ST } },
10686 { "fdivMp", { STi, ST } },
10687 },
10688 /* df */
10689 {
10690 { "ffreep", { STi } },
10691 { "(bad)", { XX } },
10692 { "(bad)", { XX } },
10693 { "(bad)", { XX } },
10694 { FGRPdf_4 },
10695 { "fucomip", { ST, STi } },
10696 { "fcomip", { ST, STi } },
10697 { "(bad)", { XX } },
10698 },
10699 };
10700
10701 static char *fgrps[][8] = {
10702 /* d9_2 0 */
10703 {
10704 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10705 },
10706
10707 /* d9_4 1 */
10708 {
10709 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
10710 },
10711
10712 /* d9_5 2 */
10713 {
10714 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
10715 },
10716
10717 /* d9_6 3 */
10718 {
10719 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
10720 },
10721
10722 /* d9_7 4 */
10723 {
10724 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
10725 },
10726
10727 /* da_5 5 */
10728 {
10729 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10730 },
10731
10732 /* db_4 6 */
10733 {
10734 "feni(287 only)","fdisi(287 only)","fNclex","fNinit",
10735 "fNsetpm(287 only)","(bad)","(bad)","(bad)",
10736 },
10737
10738 /* de_3 7 */
10739 {
10740 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10741 },
10742
10743 /* df_4 8 */
10744 {
10745 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10746 },
10747 };
10748
10749 static void
10750 swap_operand (void)
10751 {
10752 mnemonicendp[0] = '.';
10753 mnemonicendp[1] = 's';
10754 mnemonicendp += 2;
10755 }
10756
10757 static void
10758 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
10759 int sizeflag ATTRIBUTE_UNUSED)
10760 {
10761 /* Skip mod/rm byte. */
10762 MODRM_CHECK;
10763 codep++;
10764 }
10765
10766 static void
10767 dofloat (int sizeflag)
10768 {
10769 const struct dis386 *dp;
10770 unsigned char floatop;
10771
10772 floatop = codep[-1];
10773
10774 if (modrm.mod != 3)
10775 {
10776 int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
10777
10778 putop (float_mem[fp_indx], sizeflag);
10779 obufp = op_out[0];
10780 op_ad = 2;
10781 OP_E (float_mem_mode[fp_indx], sizeflag);
10782 return;
10783 }
10784 /* Skip mod/rm byte. */
10785 MODRM_CHECK;
10786 codep++;
10787
10788 dp = &float_reg[floatop - 0xd8][modrm.reg];
10789 if (dp->name == NULL)
10790 {
10791 putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
10792
10793 /* Instruction fnstsw is only one with strange arg. */
10794 if (floatop == 0xdf && codep[-1] == 0xe0)
10795 strcpy (op_out[0], names16[0]);
10796 }
10797 else
10798 {
10799 putop (dp->name, sizeflag);
10800
10801 obufp = op_out[0];
10802 op_ad = 2;
10803 if (dp->op[0].rtn)
10804 (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
10805
10806 obufp = op_out[1];
10807 op_ad = 1;
10808 if (dp->op[1].rtn)
10809 (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
10810 }
10811 }
10812
10813 static void
10814 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
10815 {
10816 oappend ("%st" + intel_syntax);
10817 }
10818
10819 static void
10820 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
10821 {
10822 sprintf (scratchbuf, "%%st(%d)", modrm.rm);
10823 oappend (scratchbuf + intel_syntax);
10824 }
10825
10826 /* Capital letters in template are macros. */
10827 static int
10828 putop (const char *template, int sizeflag)
10829 {
10830 const char *p;
10831 int alt = 0;
10832 int cond = 1;
10833 unsigned int l = 0, len = 1;
10834 char last[4];
10835
10836 #define SAVE_LAST(c) \
10837 if (l < len && l < sizeof (last)) \
10838 last[l++] = c; \
10839 else \
10840 abort ();
10841
10842 for (p = template; *p; p++)
10843 {
10844 switch (*p)
10845 {
10846 default:
10847 *obufp++ = *p;
10848 break;
10849 case '%':
10850 len++;
10851 break;
10852 case '!':
10853 cond = 0;
10854 break;
10855 case '{':
10856 alt = 0;
10857 if (intel_syntax)
10858 {
10859 while (*++p != '|')
10860 if (*p == '}' || *p == '\0')
10861 abort ();
10862 }
10863 /* Fall through. */
10864 case 'I':
10865 alt = 1;
10866 continue;
10867 case '|':
10868 while (*++p != '}')
10869 {
10870 if (*p == '\0')
10871 abort ();
10872 }
10873 break;
10874 case '}':
10875 break;
10876 case 'A':
10877 if (intel_syntax)
10878 break;
10879 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
10880 *obufp++ = 'b';
10881 break;
10882 case 'B':
10883 if (intel_syntax)
10884 break;
10885 if (sizeflag & SUFFIX_ALWAYS)
10886 *obufp++ = 'b';
10887 break;
10888 case 'C':
10889 if (intel_syntax && !alt)
10890 break;
10891 if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
10892 {
10893 if (sizeflag & DFLAG)
10894 *obufp++ = intel_syntax ? 'd' : 'l';
10895 else
10896 *obufp++ = intel_syntax ? 'w' : 's';
10897 used_prefixes |= (prefixes & PREFIX_DATA);
10898 }
10899 break;
10900 case 'D':
10901 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
10902 break;
10903 USED_REX (REX_W);
10904 if (modrm.mod == 3)
10905 {
10906 if (rex & REX_W)
10907 *obufp++ = 'q';
10908 else if (sizeflag & DFLAG)
10909 *obufp++ = intel_syntax ? 'd' : 'l';
10910 else
10911 *obufp++ = 'w';
10912 used_prefixes |= (prefixes & PREFIX_DATA);
10913 }
10914 else
10915 *obufp++ = 'w';
10916 break;
10917 case 'E': /* For jcxz/jecxz */
10918 if (address_mode == mode_64bit)
10919 {
10920 if (sizeflag & AFLAG)
10921 *obufp++ = 'r';
10922 else
10923 *obufp++ = 'e';
10924 }
10925 else
10926 if (sizeflag & AFLAG)
10927 *obufp++ = 'e';
10928 used_prefixes |= (prefixes & PREFIX_ADDR);
10929 break;
10930 case 'F':
10931 if (intel_syntax)
10932 break;
10933 if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
10934 {
10935 if (sizeflag & AFLAG)
10936 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
10937 else
10938 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
10939 used_prefixes |= (prefixes & PREFIX_ADDR);
10940 }
10941 break;
10942 case 'G':
10943 if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
10944 break;
10945 if ((rex & REX_W) || (sizeflag & DFLAG))
10946 *obufp++ = 'l';
10947 else
10948 *obufp++ = 'w';
10949 if (!(rex & REX_W))
10950 used_prefixes |= (prefixes & PREFIX_DATA);
10951 break;
10952 case 'H':
10953 if (intel_syntax)
10954 break;
10955 if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
10956 || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
10957 {
10958 used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
10959 *obufp++ = ',';
10960 *obufp++ = 'p';
10961 if (prefixes & PREFIX_DS)
10962 *obufp++ = 't';
10963 else
10964 *obufp++ = 'n';
10965 }
10966 break;
10967 case 'J':
10968 if (intel_syntax)
10969 break;
10970 *obufp++ = 'l';
10971 break;
10972 case 'K':
10973 USED_REX (REX_W);
10974 if (rex & REX_W)
10975 *obufp++ = 'q';
10976 else
10977 *obufp++ = 'd';
10978 break;
10979 case 'Z':
10980 if (intel_syntax)
10981 break;
10982 if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
10983 {
10984 *obufp++ = 'q';
10985 break;
10986 }
10987 /* Fall through. */
10988 goto case_L;
10989 case 'L':
10990 if (l != 0 || len != 1)
10991 {
10992 SAVE_LAST (*p);
10993 break;
10994 }
10995 case_L:
10996 if (intel_syntax)
10997 break;
10998 if (sizeflag & SUFFIX_ALWAYS)
10999 *obufp++ = 'l';
11000 break;
11001 case 'M':
11002 if (intel_mnemonic != cond)
11003 *obufp++ = 'r';
11004 break;
11005 case 'N':
11006 if ((prefixes & PREFIX_FWAIT) == 0)
11007 *obufp++ = 'n';
11008 else
11009 used_prefixes |= PREFIX_FWAIT;
11010 break;
11011 case 'O':
11012 USED_REX (REX_W);
11013 if (rex & REX_W)
11014 *obufp++ = 'o';
11015 else if (intel_syntax && (sizeflag & DFLAG))
11016 *obufp++ = 'q';
11017 else
11018 *obufp++ = 'd';
11019 if (!(rex & REX_W))
11020 used_prefixes |= (prefixes & PREFIX_DATA);
11021 break;
11022 case 'T':
11023 if (intel_syntax)
11024 break;
11025 if (address_mode == mode_64bit && (sizeflag & DFLAG))
11026 {
11027 *obufp++ = 'q';
11028 break;
11029 }
11030 /* Fall through. */
11031 case 'P':
11032 if (intel_syntax)
11033 break;
11034 if ((prefixes & PREFIX_DATA)
11035 || (rex & REX_W)
11036 || (sizeflag & SUFFIX_ALWAYS))
11037 {
11038 USED_REX (REX_W);
11039 if (rex & REX_W)
11040 *obufp++ = 'q';
11041 else
11042 {
11043 if (sizeflag & DFLAG)
11044 *obufp++ = 'l';
11045 else
11046 *obufp++ = 'w';
11047 }
11048 used_prefixes |= (prefixes & PREFIX_DATA);
11049 }
11050 break;
11051 case 'U':
11052 if (intel_syntax)
11053 break;
11054 if (address_mode == mode_64bit && (sizeflag & DFLAG))
11055 {
11056 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
11057 *obufp++ = 'q';
11058 break;
11059 }
11060 /* Fall through. */
11061 goto case_Q;
11062 case 'Q':
11063 if (l == 0 && len == 1)
11064 {
11065 case_Q:
11066 if (intel_syntax && !alt)
11067 break;
11068 USED_REX (REX_W);
11069 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
11070 {
11071 if (rex & REX_W)
11072 *obufp++ = 'q';
11073 else
11074 {
11075 if (sizeflag & DFLAG)
11076 *obufp++ = intel_syntax ? 'd' : 'l';
11077 else
11078 *obufp++ = 'w';
11079 }
11080 used_prefixes |= (prefixes & PREFIX_DATA);
11081 }
11082 }
11083 else
11084 {
11085 if (l != 1 || len != 2 || last[0] != 'L')
11086 {
11087 SAVE_LAST (*p);
11088 break;
11089 }
11090 if (intel_syntax
11091 || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
11092 break;
11093 if ((rex & REX_W))
11094 {
11095 USED_REX (REX_W);
11096 *obufp++ = 'q';
11097 }
11098 else
11099 *obufp++ = 'l';
11100 }
11101 break;
11102 case 'R':
11103 USED_REX (REX_W);
11104 if (rex & REX_W)
11105 *obufp++ = 'q';
11106 else if (sizeflag & DFLAG)
11107 {
11108 if (intel_syntax)
11109 *obufp++ = 'd';
11110 else
11111 *obufp++ = 'l';
11112 }
11113 else
11114 *obufp++ = 'w';
11115 if (intel_syntax && !p[1]
11116 && ((rex & REX_W) || (sizeflag & DFLAG)))
11117 *obufp++ = 'e';
11118 if (!(rex & REX_W))
11119 used_prefixes |= (prefixes & PREFIX_DATA);
11120 break;
11121 case 'V':
11122 if (intel_syntax)
11123 break;
11124 if (address_mode == mode_64bit && (sizeflag & DFLAG))
11125 {
11126 if (sizeflag & SUFFIX_ALWAYS)
11127 *obufp++ = 'q';
11128 break;
11129 }
11130 /* Fall through. */
11131 case 'S':
11132 if (intel_syntax)
11133 break;
11134 if (sizeflag & SUFFIX_ALWAYS)
11135 {
11136 if (rex & REX_W)
11137 *obufp++ = 'q';
11138 else
11139 {
11140 if (sizeflag & DFLAG)
11141 *obufp++ = 'l';
11142 else
11143 *obufp++ = 'w';
11144 used_prefixes |= (prefixes & PREFIX_DATA);
11145 }
11146 }
11147 break;
11148 case 'X':
11149 if (l != 0 || len != 1)
11150 {
11151 SAVE_LAST (*p);
11152 break;
11153 }
11154 if (need_vex && vex.prefix)
11155 {
11156 if (vex.prefix == DATA_PREFIX_OPCODE)
11157 *obufp++ = 'd';
11158 else
11159 *obufp++ = 's';
11160 }
11161 else if (prefixes & PREFIX_DATA)
11162 *obufp++ = 'd';
11163 else
11164 *obufp++ = 's';
11165 used_prefixes |= (prefixes & PREFIX_DATA);
11166 break;
11167 case 'Y':
11168 if (l == 0 && len == 1)
11169 {
11170 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
11171 break;
11172 if (rex & REX_W)
11173 {
11174 USED_REX (REX_W);
11175 *obufp++ = 'q';
11176 }
11177 break;
11178 }
11179 else
11180 {
11181 if (l != 1 || len != 2 || last[0] != 'X')
11182 {
11183 SAVE_LAST (*p);
11184 break;
11185 }
11186 if (!need_vex)
11187 abort ();
11188 if (intel_syntax
11189 || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
11190 break;
11191 switch (vex.length)
11192 {
11193 case 128:
11194 *obufp++ = 'x';
11195 break;
11196 case 256:
11197 *obufp++ = 'y';
11198 break;
11199 default:
11200 abort ();
11201 }
11202 }
11203 break;
11204 case 'W':
11205 if (l == 0 && len == 1)
11206 {
11207 /* operand size flag for cwtl, cbtw */
11208 USED_REX (REX_W);
11209 if (rex & REX_W)
11210 {
11211 if (intel_syntax)
11212 *obufp++ = 'd';
11213 else
11214 *obufp++ = 'l';
11215 }
11216 else if (sizeflag & DFLAG)
11217 *obufp++ = 'w';
11218 else
11219 *obufp++ = 'b';
11220 if (!(rex & REX_W))
11221 used_prefixes |= (prefixes & PREFIX_DATA);
11222 }
11223 else
11224 {
11225 if (l != 1 || len != 2 || last[0] != 'X')
11226 {
11227 SAVE_LAST (*p);
11228 break;
11229 }
11230 if (!need_vex)
11231 abort ();
11232 *obufp++ = vex.w ? 'd': 's';
11233 }
11234 break;
11235 }
11236 alt = 0;
11237 }
11238 *obufp = 0;
11239 mnemonicendp = obufp;
11240 return 0;
11241 }
11242
11243 static void
11244 oappend (const char *s)
11245 {
11246 obufp = stpcpy (obufp, s);
11247 }
11248
11249 static void
11250 append_seg (void)
11251 {
11252 if (prefixes & PREFIX_CS)
11253 {
11254 used_prefixes |= PREFIX_CS;
11255 oappend ("%cs:" + intel_syntax);
11256 }
11257 if (prefixes & PREFIX_DS)
11258 {
11259 used_prefixes |= PREFIX_DS;
11260 oappend ("%ds:" + intel_syntax);
11261 }
11262 if (prefixes & PREFIX_SS)
11263 {
11264 used_prefixes |= PREFIX_SS;
11265 oappend ("%ss:" + intel_syntax);
11266 }
11267 if (prefixes & PREFIX_ES)
11268 {
11269 used_prefixes |= PREFIX_ES;
11270 oappend ("%es:" + intel_syntax);
11271 }
11272 if (prefixes & PREFIX_FS)
11273 {
11274 used_prefixes |= PREFIX_FS;
11275 oappend ("%fs:" + intel_syntax);
11276 }
11277 if (prefixes & PREFIX_GS)
11278 {
11279 used_prefixes |= PREFIX_GS;
11280 oappend ("%gs:" + intel_syntax);
11281 }
11282 }
11283
11284 static void
11285 OP_indirE (int bytemode, int sizeflag)
11286 {
11287 if (!intel_syntax)
11288 oappend ("*");
11289 OP_E (bytemode, sizeflag);
11290 }
11291
11292 static void
11293 print_operand_value (char *buf, int hex, bfd_vma disp)
11294 {
11295 if (address_mode == mode_64bit)
11296 {
11297 if (hex)
11298 {
11299 char tmp[30];
11300 int i;
11301 buf[0] = '0';
11302 buf[1] = 'x';
11303 sprintf_vma (tmp, disp);
11304 for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
11305 strcpy (buf + 2, tmp + i);
11306 }
11307 else
11308 {
11309 bfd_signed_vma v = disp;
11310 char tmp[30];
11311 int i;
11312 if (v < 0)
11313 {
11314 *(buf++) = '-';
11315 v = -disp;
11316 /* Check for possible overflow on 0x8000000000000000. */
11317 if (v < 0)
11318 {
11319 strcpy (buf, "9223372036854775808");
11320 return;
11321 }
11322 }
11323 if (!v)
11324 {
11325 strcpy (buf, "0");
11326 return;
11327 }
11328
11329 i = 0;
11330 tmp[29] = 0;
11331 while (v)
11332 {
11333 tmp[28 - i] = (v % 10) + '0';
11334 v /= 10;
11335 i++;
11336 }
11337 strcpy (buf, tmp + 29 - i);
11338 }
11339 }
11340 else
11341 {
11342 if (hex)
11343 sprintf (buf, "0x%x", (unsigned int) disp);
11344 else
11345 sprintf (buf, "%d", (int) disp);
11346 }
11347 }
11348
11349 /* Put DISP in BUF as signed hex number. */
11350
11351 static void
11352 print_displacement (char *buf, bfd_vma disp)
11353 {
11354 bfd_signed_vma val = disp;
11355 char tmp[30];
11356 int i, j = 0;
11357
11358 if (val < 0)
11359 {
11360 buf[j++] = '-';
11361 val = -disp;
11362
11363 /* Check for possible overflow. */
11364 if (val < 0)
11365 {
11366 switch (address_mode)
11367 {
11368 case mode_64bit:
11369 strcpy (buf + j, "0x8000000000000000");
11370 break;
11371 case mode_32bit:
11372 strcpy (buf + j, "0x80000000");
11373 break;
11374 case mode_16bit:
11375 strcpy (buf + j, "0x8000");
11376 break;
11377 }
11378 return;
11379 }
11380 }
11381
11382 buf[j++] = '0';
11383 buf[j++] = 'x';
11384
11385 sprintf_vma (tmp, (bfd_vma) val);
11386 for (i = 0; tmp[i] == '0'; i++)
11387 continue;
11388 if (tmp[i] == '\0')
11389 i--;
11390 strcpy (buf + j, tmp + i);
11391 }
11392
11393 static void
11394 intel_operand_size (int bytemode, int sizeflag)
11395 {
11396 switch (bytemode)
11397 {
11398 case b_mode:
11399 case b_swap_mode:
11400 case dqb_mode:
11401 oappend ("BYTE PTR ");
11402 break;
11403 case w_mode:
11404 case dqw_mode:
11405 oappend ("WORD PTR ");
11406 break;
11407 case stack_v_mode:
11408 if (address_mode == mode_64bit && (sizeflag & DFLAG))
11409 {
11410 oappend ("QWORD PTR ");
11411 used_prefixes |= (prefixes & PREFIX_DATA);
11412 break;
11413 }
11414 /* FALLTHRU */
11415 case v_mode:
11416 case v_swap_mode:
11417 case dq_mode:
11418 USED_REX (REX_W);
11419 if (rex & REX_W)
11420 oappend ("QWORD PTR ");
11421 else if ((sizeflag & DFLAG) || bytemode == dq_mode)
11422 oappend ("DWORD PTR ");
11423 else
11424 oappend ("WORD PTR ");
11425 used_prefixes |= (prefixes & PREFIX_DATA);
11426 break;
11427 case z_mode:
11428 if ((rex & REX_W) || (sizeflag & DFLAG))
11429 *obufp++ = 'D';
11430 oappend ("WORD PTR ");
11431 if (!(rex & REX_W))
11432 used_prefixes |= (prefixes & PREFIX_DATA);
11433 break;
11434 case a_mode:
11435 if (sizeflag & DFLAG)
11436 oappend ("QWORD PTR ");
11437 else
11438 oappend ("DWORD PTR ");
11439 used_prefixes |= (prefixes & PREFIX_DATA);
11440 break;
11441 case d_mode:
11442 case d_swap_mode:
11443 case dqd_mode:
11444 oappend ("DWORD PTR ");
11445 break;
11446 case q_mode:
11447 case q_swap_mode:
11448 oappend ("QWORD PTR ");
11449 break;
11450 case m_mode:
11451 if (address_mode == mode_64bit)
11452 oappend ("QWORD PTR ");
11453 else
11454 oappend ("DWORD PTR ");
11455 break;
11456 case f_mode:
11457 if (sizeflag & DFLAG)
11458 oappend ("FWORD PTR ");
11459 else
11460 oappend ("DWORD PTR ");
11461 used_prefixes |= (prefixes & PREFIX_DATA);
11462 break;
11463 case t_mode:
11464 oappend ("TBYTE PTR ");
11465 break;
11466 case x_mode:
11467 case x_swap_mode:
11468 if (need_vex)
11469 {
11470 switch (vex.length)
11471 {
11472 case 128:
11473 oappend ("XMMWORD PTR ");
11474 break;
11475 case 256:
11476 oappend ("YMMWORD PTR ");
11477 break;
11478 default:
11479 abort ();
11480 }
11481 }
11482 else
11483 oappend ("XMMWORD PTR ");
11484 break;
11485 case xmm_mode:
11486 oappend ("XMMWORD PTR ");
11487 break;
11488 case xmmq_mode:
11489 if (!need_vex)
11490 abort ();
11491
11492 switch (vex.length)
11493 {
11494 case 128:
11495 oappend ("QWORD PTR ");
11496 break;
11497 case 256:
11498 oappend ("XMMWORD PTR ");
11499 break;
11500 default:
11501 abort ();
11502 }
11503 break;
11504 case ymmq_mode:
11505 if (!need_vex)
11506 abort ();
11507
11508 switch (vex.length)
11509 {
11510 case 128:
11511 oappend ("QWORD PTR ");
11512 break;
11513 case 256:
11514 oappend ("YMMWORD PTR ");
11515 break;
11516 default:
11517 abort ();
11518 }
11519 break;
11520 case o_mode:
11521 oappend ("OWORD PTR ");
11522 break;
11523 case vex_w_dq_mode:
11524 if (!need_vex)
11525 abort ();
11526
11527 if (vex.w)
11528 oappend ("QWORD PTR ");
11529 else
11530 oappend ("DWORD PTR ");
11531 break;
11532 default:
11533 break;
11534 }
11535 }
11536
11537 static void
11538 OP_E_register (int bytemode, int sizeflag)
11539 {
11540 int reg = modrm.rm;
11541 const char **names;
11542
11543 USED_REX (REX_B);
11544 if ((rex & REX_B))
11545 reg += 8;
11546
11547 if ((sizeflag & SUFFIX_ALWAYS)
11548 && (bytemode == b_swap_mode || bytemode == v_swap_mode))
11549 swap_operand ();
11550
11551 switch (bytemode)
11552 {
11553 case b_mode:
11554 case b_swap_mode:
11555 USED_REX (0);
11556 if (rex)
11557 names = names8rex;
11558 else
11559 names = names8;
11560 break;
11561 case w_mode:
11562 names = names16;
11563 break;
11564 case d_mode:
11565 names = names32;
11566 break;
11567 case q_mode:
11568 names = names64;
11569 break;
11570 case m_mode:
11571 names = address_mode == mode_64bit ? names64 : names32;
11572 break;
11573 case stack_v_mode:
11574 if (address_mode == mode_64bit && (sizeflag & DFLAG))
11575 {
11576 names = names64;
11577 used_prefixes |= (prefixes & PREFIX_DATA);
11578 break;
11579 }
11580 bytemode = v_mode;
11581 /* FALLTHRU */
11582 case v_mode:
11583 case v_swap_mode:
11584 case dq_mode:
11585 case dqb_mode:
11586 case dqd_mode:
11587 case dqw_mode:
11588 USED_REX (REX_W);
11589 if (rex & REX_W)
11590 names = names64;
11591 else if ((sizeflag & DFLAG)
11592 || (bytemode != v_mode
11593 && bytemode != v_swap_mode))
11594 names = names32;
11595 else
11596 names = names16;
11597 used_prefixes |= (prefixes & PREFIX_DATA);
11598 break;
11599 case 0:
11600 return;
11601 default:
11602 oappend (INTERNAL_DISASSEMBLER_ERROR);
11603 return;
11604 }
11605 oappend (names[reg]);
11606 }
11607
11608 static void
11609 OP_E_memory (int bytemode, int sizeflag, int has_drex)
11610 {
11611 bfd_vma disp = 0;
11612 int add = (rex & REX_B) ? 8 : 0;
11613 int riprel = 0;
11614
11615 USED_REX (REX_B);
11616 if (intel_syntax)
11617 intel_operand_size (bytemode, sizeflag);
11618 append_seg ();
11619
11620 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
11621 {
11622 /* 32/64 bit address mode */
11623 int havedisp;
11624 int havesib;
11625 int havebase;
11626 int haveindex;
11627 int needindex;
11628 int base, rbase;
11629 int index = 0;
11630 int scale = 0;
11631
11632 havesib = 0;
11633 havebase = 1;
11634 haveindex = 0;
11635 base = modrm.rm;
11636
11637 if (base == 4)
11638 {
11639 havesib = 1;
11640 FETCH_DATA (the_info, codep + 1);
11641 index = (*codep >> 3) & 7;
11642 scale = (*codep >> 6) & 3;
11643 base = *codep & 7;
11644 USED_REX (REX_X);
11645 if (rex & REX_X)
11646 index += 8;
11647 haveindex = index != 4;
11648 codep++;
11649 }
11650 rbase = base + add;
11651
11652 /* If we have a DREX byte, skip it now
11653 (it has already been handled) */
11654 if (has_drex)
11655 {
11656 FETCH_DATA (the_info, codep + 1);
11657 codep++;
11658 }
11659
11660 switch (modrm.mod)
11661 {
11662 case 0:
11663 if (base == 5)
11664 {
11665 havebase = 0;
11666 if (address_mode == mode_64bit && !havesib)
11667 riprel = 1;
11668 disp = get32s ();
11669 }
11670 break;
11671 case 1:
11672 FETCH_DATA (the_info, codep + 1);
11673 disp = *codep++;
11674 if ((disp & 0x80) != 0)
11675 disp -= 0x100;
11676 break;
11677 case 2:
11678 disp = get32s ();
11679 break;
11680 }
11681
11682 /* In 32bit mode, we need index register to tell [offset] from
11683 [eiz*1 + offset]. */
11684 needindex = (havesib
11685 && !havebase
11686 && !haveindex
11687 && address_mode == mode_32bit);
11688 havedisp = (havebase
11689 || needindex
11690 || (havesib && (haveindex || scale != 0)));
11691
11692 if (!intel_syntax)
11693 if (modrm.mod != 0 || base == 5)
11694 {
11695 if (havedisp || riprel)
11696 print_displacement (scratchbuf, disp);
11697 else
11698 print_operand_value (scratchbuf, 1, disp);
11699 oappend (scratchbuf);
11700 if (riprel)
11701 {
11702 set_op (disp, 1);
11703 oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)");
11704 }
11705 }
11706
11707 if (havebase || haveindex || riprel)
11708 used_prefixes |= PREFIX_ADDR;
11709
11710 if (havedisp || (intel_syntax && riprel))
11711 {
11712 *obufp++ = open_char;
11713 if (intel_syntax && riprel)
11714 {
11715 set_op (disp, 1);
11716 oappend (sizeflag & AFLAG ? "rip" : "eip");
11717 }
11718 *obufp = '\0';
11719 if (havebase)
11720 oappend (address_mode == mode_64bit && (sizeflag & AFLAG)
11721 ? names64[rbase] : names32[rbase]);
11722 if (havesib)
11723 {
11724 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
11725 print index to tell base + index from base. */
11726 if (scale != 0
11727 || needindex
11728 || haveindex
11729 || (havebase && base != ESP_REG_NUM))
11730 {
11731 if (!intel_syntax || havebase)
11732 {
11733 *obufp++ = separator_char;
11734 *obufp = '\0';
11735 }
11736 if (haveindex)
11737 oappend (address_mode == mode_64bit
11738 && (sizeflag & AFLAG)
11739 ? names64[index] : names32[index]);
11740 else
11741 oappend (address_mode == mode_64bit
11742 && (sizeflag & AFLAG)
11743 ? index64 : index32);
11744
11745 *obufp++ = scale_char;
11746 *obufp = '\0';
11747 sprintf (scratchbuf, "%d", 1 << scale);
11748 oappend (scratchbuf);
11749 }
11750 }
11751 if (intel_syntax
11752 && (disp || modrm.mod != 0 || base == 5))
11753 {
11754 if (!havedisp || (bfd_signed_vma) disp >= 0)
11755 {
11756 *obufp++ = '+';
11757 *obufp = '\0';
11758 }
11759 else if (modrm.mod != 1)
11760 {
11761 *obufp++ = '-';
11762 *obufp = '\0';
11763 disp = - (bfd_signed_vma) disp;
11764 }
11765
11766 if (havedisp)
11767 print_displacement (scratchbuf, disp);
11768 else
11769 print_operand_value (scratchbuf, 1, disp);
11770 oappend (scratchbuf);
11771 }
11772
11773 *obufp++ = close_char;
11774 *obufp = '\0';
11775 }
11776 else if (intel_syntax)
11777 {
11778 if (modrm.mod != 0 || base == 5)
11779 {
11780 if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
11781 | PREFIX_ES | PREFIX_FS | PREFIX_GS))
11782 ;
11783 else
11784 {
11785 oappend (names_seg[ds_reg - es_reg]);
11786 oappend (":");
11787 }
11788 print_operand_value (scratchbuf, 1, disp);
11789 oappend (scratchbuf);
11790 }
11791 }
11792 }
11793 else
11794 { /* 16 bit address mode */
11795 switch (modrm.mod)
11796 {
11797 case 0:
11798 if (modrm.rm == 6)
11799 {
11800 disp = get16 ();
11801 if ((disp & 0x8000) != 0)
11802 disp -= 0x10000;
11803 }
11804 break;
11805 case 1:
11806 FETCH_DATA (the_info, codep + 1);
11807 disp = *codep++;
11808 if ((disp & 0x80) != 0)
11809 disp -= 0x100;
11810 break;
11811 case 2:
11812 disp = get16 ();
11813 if ((disp & 0x8000) != 0)
11814 disp -= 0x10000;
11815 break;
11816 }
11817
11818 if (!intel_syntax)
11819 if (modrm.mod != 0 || modrm.rm == 6)
11820 {
11821 print_displacement (scratchbuf, disp);
11822 oappend (scratchbuf);
11823 }
11824
11825 if (modrm.mod != 0 || modrm.rm != 6)
11826 {
11827 *obufp++ = open_char;
11828 *obufp = '\0';
11829 oappend (index16[modrm.rm]);
11830 if (intel_syntax
11831 && (disp || modrm.mod != 0 || modrm.rm == 6))
11832 {
11833 if ((bfd_signed_vma) disp >= 0)
11834 {
11835 *obufp++ = '+';
11836 *obufp = '\0';
11837 }
11838 else if (modrm.mod != 1)
11839 {
11840 *obufp++ = '-';
11841 *obufp = '\0';
11842 disp = - (bfd_signed_vma) disp;
11843 }
11844
11845 print_displacement (scratchbuf, disp);
11846 oappend (scratchbuf);
11847 }
11848
11849 *obufp++ = close_char;
11850 *obufp = '\0';
11851 }
11852 else if (intel_syntax)
11853 {
11854 if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
11855 | PREFIX_ES | PREFIX_FS | PREFIX_GS))
11856 ;
11857 else
11858 {
11859 oappend (names_seg[ds_reg - es_reg]);
11860 oappend (":");
11861 }
11862 print_operand_value (scratchbuf, 1, disp & 0xffff);
11863 oappend (scratchbuf);
11864 }
11865 }
11866 }
11867
11868 static void
11869 OP_E_extended (int bytemode, int sizeflag, int has_drex)
11870 {
11871 /* Skip mod/rm byte. */
11872 MODRM_CHECK;
11873 codep++;
11874
11875 if (modrm.mod == 3)
11876 OP_E_register (bytemode, sizeflag);
11877 else
11878 OP_E_memory (bytemode, sizeflag, has_drex);
11879 }
11880
11881 static void
11882 OP_E (int bytemode, int sizeflag)
11883 {
11884 OP_E_extended (bytemode, sizeflag, 0);
11885 }
11886
11887
11888 static void
11889 OP_G (int bytemode, int sizeflag)
11890 {
11891 int add = 0;
11892 USED_REX (REX_R);
11893 if (rex & REX_R)
11894 add += 8;
11895 switch (bytemode)
11896 {
11897 case b_mode:
11898 USED_REX (0);
11899 if (rex)
11900 oappend (names8rex[modrm.reg + add]);
11901 else
11902 oappend (names8[modrm.reg + add]);
11903 break;
11904 case w_mode:
11905 oappend (names16[modrm.reg + add]);
11906 break;
11907 case d_mode:
11908 oappend (names32[modrm.reg + add]);
11909 break;
11910 case q_mode:
11911 oappend (names64[modrm.reg + add]);
11912 break;
11913 case v_mode:
11914 case dq_mode:
11915 case dqb_mode:
11916 case dqd_mode:
11917 case dqw_mode:
11918 USED_REX (REX_W);
11919 if (rex & REX_W)
11920 oappend (names64[modrm.reg + add]);
11921 else if ((sizeflag & DFLAG) || bytemode != v_mode)
11922 oappend (names32[modrm.reg + add]);
11923 else
11924 oappend (names16[modrm.reg + add]);
11925 used_prefixes |= (prefixes & PREFIX_DATA);
11926 break;
11927 case m_mode:
11928 if (address_mode == mode_64bit)
11929 oappend (names64[modrm.reg + add]);
11930 else
11931 oappend (names32[modrm.reg + add]);
11932 break;
11933 default:
11934 oappend (INTERNAL_DISASSEMBLER_ERROR);
11935 break;
11936 }
11937 }
11938
11939 static bfd_vma
11940 get64 (void)
11941 {
11942 bfd_vma x;
11943 #ifdef BFD64
11944 unsigned int a;
11945 unsigned int b;
11946
11947 FETCH_DATA (the_info, codep + 8);
11948 a = *codep++ & 0xff;
11949 a |= (*codep++ & 0xff) << 8;
11950 a |= (*codep++ & 0xff) << 16;
11951 a |= (*codep++ & 0xff) << 24;
11952 b = *codep++ & 0xff;
11953 b |= (*codep++ & 0xff) << 8;
11954 b |= (*codep++ & 0xff) << 16;
11955 b |= (*codep++ & 0xff) << 24;
11956 x = a + ((bfd_vma) b << 32);
11957 #else
11958 abort ();
11959 x = 0;
11960 #endif
11961 return x;
11962 }
11963
11964 static bfd_signed_vma
11965 get32 (void)
11966 {
11967 bfd_signed_vma x = 0;
11968
11969 FETCH_DATA (the_info, codep + 4);
11970 x = *codep++ & (bfd_signed_vma) 0xff;
11971 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
11972 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
11973 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
11974 return x;
11975 }
11976
11977 static bfd_signed_vma
11978 get32s (void)
11979 {
11980 bfd_signed_vma x = 0;
11981
11982 FETCH_DATA (the_info, codep + 4);
11983 x = *codep++ & (bfd_signed_vma) 0xff;
11984 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
11985 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
11986 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
11987
11988 x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
11989
11990 return x;
11991 }
11992
11993 static int
11994 get16 (void)
11995 {
11996 int x = 0;
11997
11998 FETCH_DATA (the_info, codep + 2);
11999 x = *codep++ & 0xff;
12000 x |= (*codep++ & 0xff) << 8;
12001 return x;
12002 }
12003
12004 static void
12005 set_op (bfd_vma op, int riprel)
12006 {
12007 op_index[op_ad] = op_ad;
12008 if (address_mode == mode_64bit)
12009 {
12010 op_address[op_ad] = op;
12011 op_riprel[op_ad] = riprel;
12012 }
12013 else
12014 {
12015 /* Mask to get a 32-bit address. */
12016 op_address[op_ad] = op & 0xffffffff;
12017 op_riprel[op_ad] = riprel & 0xffffffff;
12018 }
12019 }
12020
12021 static void
12022 OP_REG (int code, int sizeflag)
12023 {
12024 const char *s;
12025 int add;
12026 USED_REX (REX_B);
12027 if (rex & REX_B)
12028 add = 8;
12029 else
12030 add = 0;
12031
12032 switch (code)
12033 {
12034 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
12035 case sp_reg: case bp_reg: case si_reg: case di_reg:
12036 s = names16[code - ax_reg + add];
12037 break;
12038 case es_reg: case ss_reg: case cs_reg:
12039 case ds_reg: case fs_reg: case gs_reg:
12040 s = names_seg[code - es_reg + add];
12041 break;
12042 case al_reg: case ah_reg: case cl_reg: case ch_reg:
12043 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
12044 USED_REX (0);
12045 if (rex)
12046 s = names8rex[code - al_reg + add];
12047 else
12048 s = names8[code - al_reg];
12049 break;
12050 case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
12051 case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
12052 if (address_mode == mode_64bit && (sizeflag & DFLAG))
12053 {
12054 s = names64[code - rAX_reg + add];
12055 break;
12056 }
12057 code += eAX_reg - rAX_reg;
12058 /* Fall through. */
12059 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
12060 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
12061 USED_REX (REX_W);
12062 if (rex & REX_W)
12063 s = names64[code - eAX_reg + add];
12064 else if (sizeflag & DFLAG)
12065 s = names32[code - eAX_reg + add];
12066 else
12067 s = names16[code - eAX_reg + add];
12068 used_prefixes |= (prefixes & PREFIX_DATA);
12069 break;
12070 default:
12071 s = INTERNAL_DISASSEMBLER_ERROR;
12072 break;
12073 }
12074 oappend (s);
12075 }
12076
12077 static void
12078 OP_IMREG (int code, int sizeflag)
12079 {
12080 const char *s;
12081
12082 switch (code)
12083 {
12084 case indir_dx_reg:
12085 if (intel_syntax)
12086 s = "dx";
12087 else
12088 s = "(%dx)";
12089 break;
12090 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
12091 case sp_reg: case bp_reg: case si_reg: case di_reg:
12092 s = names16[code - ax_reg];
12093 break;
12094 case es_reg: case ss_reg: case cs_reg:
12095 case ds_reg: case fs_reg: case gs_reg:
12096 s = names_seg[code - es_reg];
12097 break;
12098 case al_reg: case ah_reg: case cl_reg: case ch_reg:
12099 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
12100 USED_REX (0);
12101 if (rex)
12102 s = names8rex[code - al_reg];
12103 else
12104 s = names8[code - al_reg];
12105 break;
12106 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
12107 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
12108 USED_REX (REX_W);
12109 if (rex & REX_W)
12110 s = names64[code - eAX_reg];
12111 else if (sizeflag & DFLAG)
12112 s = names32[code - eAX_reg];
12113 else
12114 s = names16[code - eAX_reg];
12115 used_prefixes |= (prefixes & PREFIX_DATA);
12116 break;
12117 case z_mode_ax_reg:
12118 if ((rex & REX_W) || (sizeflag & DFLAG))
12119 s = *names32;
12120 else
12121 s = *names16;
12122 if (!(rex & REX_W))
12123 used_prefixes |= (prefixes & PREFIX_DATA);
12124 break;
12125 default:
12126 s = INTERNAL_DISASSEMBLER_ERROR;
12127 break;
12128 }
12129 oappend (s);
12130 }
12131
12132 static void
12133 OP_I (int bytemode, int sizeflag)
12134 {
12135 bfd_signed_vma op;
12136 bfd_signed_vma mask = -1;
12137
12138 switch (bytemode)
12139 {
12140 case b_mode:
12141 FETCH_DATA (the_info, codep + 1);
12142 op = *codep++;
12143 mask = 0xff;
12144 break;
12145 case q_mode:
12146 if (address_mode == mode_64bit)
12147 {
12148 op = get32s ();
12149 break;
12150 }
12151 /* Fall through. */
12152 case v_mode:
12153 USED_REX (REX_W);
12154 if (rex & REX_W)
12155 op = get32s ();
12156 else if (sizeflag & DFLAG)
12157 {
12158 op = get32 ();
12159 mask = 0xffffffff;
12160 }
12161 else
12162 {
12163 op = get16 ();
12164 mask = 0xfffff;
12165 }
12166 used_prefixes |= (prefixes & PREFIX_DATA);
12167 break;
12168 case w_mode:
12169 mask = 0xfffff;
12170 op = get16 ();
12171 break;
12172 case const_1_mode:
12173 if (intel_syntax)
12174 oappend ("1");
12175 return;
12176 default:
12177 oappend (INTERNAL_DISASSEMBLER_ERROR);
12178 return;
12179 }
12180
12181 op &= mask;
12182 scratchbuf[0] = '$';
12183 print_operand_value (scratchbuf + 1, 1, op);
12184 oappend (scratchbuf + intel_syntax);
12185 scratchbuf[0] = '\0';
12186 }
12187
12188 static void
12189 OP_I64 (int bytemode, int sizeflag)
12190 {
12191 bfd_signed_vma op;
12192 bfd_signed_vma mask = -1;
12193
12194 if (address_mode != mode_64bit)
12195 {
12196 OP_I (bytemode, sizeflag);
12197 return;
12198 }
12199
12200 switch (bytemode)
12201 {
12202 case b_mode:
12203 FETCH_DATA (the_info, codep + 1);
12204 op = *codep++;
12205 mask = 0xff;
12206 break;
12207 case v_mode:
12208 USED_REX (REX_W);
12209 if (rex & REX_W)
12210 op = get64 ();
12211 else if (sizeflag & DFLAG)
12212 {
12213 op = get32 ();
12214 mask = 0xffffffff;
12215 }
12216 else
12217 {
12218 op = get16 ();
12219 mask = 0xfffff;
12220 }
12221 used_prefixes |= (prefixes & PREFIX_DATA);
12222 break;
12223 case w_mode:
12224 mask = 0xfffff;
12225 op = get16 ();
12226 break;
12227 default:
12228 oappend (INTERNAL_DISASSEMBLER_ERROR);
12229 return;
12230 }
12231
12232 op &= mask;
12233 scratchbuf[0] = '$';
12234 print_operand_value (scratchbuf + 1, 1, op);
12235 oappend (scratchbuf + intel_syntax);
12236 scratchbuf[0] = '\0';
12237 }
12238
12239 static void
12240 OP_sI (int bytemode, int sizeflag)
12241 {
12242 bfd_signed_vma op;
12243 bfd_signed_vma mask = -1;
12244
12245 switch (bytemode)
12246 {
12247 case b_mode:
12248 FETCH_DATA (the_info, codep + 1);
12249 op = *codep++;
12250 if ((op & 0x80) != 0)
12251 op -= 0x100;
12252 mask = 0xffffffff;
12253 break;
12254 case v_mode:
12255 USED_REX (REX_W);
12256 if (rex & REX_W)
12257 op = get32s ();
12258 else if (sizeflag & DFLAG)
12259 {
12260 op = get32s ();
12261 mask = 0xffffffff;
12262 }
12263 else
12264 {
12265 mask = 0xffffffff;
12266 op = get16 ();
12267 if ((op & 0x8000) != 0)
12268 op -= 0x10000;
12269 }
12270 used_prefixes |= (prefixes & PREFIX_DATA);
12271 break;
12272 case w_mode:
12273 op = get16 ();
12274 mask = 0xffffffff;
12275 if ((op & 0x8000) != 0)
12276 op -= 0x10000;
12277 break;
12278 default:
12279 oappend (INTERNAL_DISASSEMBLER_ERROR);
12280 return;
12281 }
12282
12283 scratchbuf[0] = '$';
12284 print_operand_value (scratchbuf + 1, 1, op);
12285 oappend (scratchbuf + intel_syntax);
12286 }
12287
12288 static void
12289 OP_J (int bytemode, int sizeflag)
12290 {
12291 bfd_vma disp;
12292 bfd_vma mask = -1;
12293 bfd_vma segment = 0;
12294
12295 switch (bytemode)
12296 {
12297 case b_mode:
12298 FETCH_DATA (the_info, codep + 1);
12299 disp = *codep++;
12300 if ((disp & 0x80) != 0)
12301 disp -= 0x100;
12302 break;
12303 case v_mode:
12304 if ((sizeflag & DFLAG) || (rex & REX_W))
12305 disp = get32s ();
12306 else
12307 {
12308 disp = get16 ();
12309 if ((disp & 0x8000) != 0)
12310 disp -= 0x10000;
12311 /* In 16bit mode, address is wrapped around at 64k within
12312 the same segment. Otherwise, a data16 prefix on a jump
12313 instruction means that the pc is masked to 16 bits after
12314 the displacement is added! */
12315 mask = 0xffff;
12316 if ((prefixes & PREFIX_DATA) == 0)
12317 segment = ((start_pc + codep - start_codep)
12318 & ~((bfd_vma) 0xffff));
12319 }
12320 used_prefixes |= (prefixes & PREFIX_DATA);
12321 break;
12322 default:
12323 oappend (INTERNAL_DISASSEMBLER_ERROR);
12324 return;
12325 }
12326 disp = ((start_pc + codep - start_codep + disp) & mask) | segment;
12327 set_op (disp, 0);
12328 print_operand_value (scratchbuf, 1, disp);
12329 oappend (scratchbuf);
12330 }
12331
12332 static void
12333 OP_SEG (int bytemode, int sizeflag)
12334 {
12335 if (bytemode == w_mode)
12336 oappend (names_seg[modrm.reg]);
12337 else
12338 OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
12339 }
12340
12341 static void
12342 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
12343 {
12344 int seg, offset;
12345
12346 if (sizeflag & DFLAG)
12347 {
12348 offset = get32 ();
12349 seg = get16 ();
12350 }
12351 else
12352 {
12353 offset = get16 ();
12354 seg = get16 ();
12355 }
12356 used_prefixes |= (prefixes & PREFIX_DATA);
12357 if (intel_syntax)
12358 sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
12359 else
12360 sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
12361 oappend (scratchbuf);
12362 }
12363
12364 static void
12365 OP_OFF (int bytemode, int sizeflag)
12366 {
12367 bfd_vma off;
12368
12369 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12370 intel_operand_size (bytemode, sizeflag);
12371 append_seg ();
12372
12373 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
12374 off = get32 ();
12375 else
12376 off = get16 ();
12377
12378 if (intel_syntax)
12379 {
12380 if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
12381 | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
12382 {
12383 oappend (names_seg[ds_reg - es_reg]);
12384 oappend (":");
12385 }
12386 }
12387 print_operand_value (scratchbuf, 1, off);
12388 oappend (scratchbuf);
12389 }
12390
12391 static void
12392 OP_OFF64 (int bytemode, int sizeflag)
12393 {
12394 bfd_vma off;
12395
12396 if (address_mode != mode_64bit
12397 || (prefixes & PREFIX_ADDR))
12398 {
12399 OP_OFF (bytemode, sizeflag);
12400 return;
12401 }
12402
12403 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12404 intel_operand_size (bytemode, sizeflag);
12405 append_seg ();
12406
12407 off = get64 ();
12408
12409 if (intel_syntax)
12410 {
12411 if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
12412 | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
12413 {
12414 oappend (names_seg[ds_reg - es_reg]);
12415 oappend (":");
12416 }
12417 }
12418 print_operand_value (scratchbuf, 1, off);
12419 oappend (scratchbuf);
12420 }
12421
12422 static void
12423 ptr_reg (int code, int sizeflag)
12424 {
12425 const char *s;
12426
12427 *obufp++ = open_char;
12428 used_prefixes |= (prefixes & PREFIX_ADDR);
12429 if (address_mode == mode_64bit)
12430 {
12431 if (!(sizeflag & AFLAG))
12432 s = names32[code - eAX_reg];
12433 else
12434 s = names64[code - eAX_reg];
12435 }
12436 else if (sizeflag & AFLAG)
12437 s = names32[code - eAX_reg];
12438 else
12439 s = names16[code - eAX_reg];
12440 oappend (s);
12441 *obufp++ = close_char;
12442 *obufp = 0;
12443 }
12444
12445 static void
12446 OP_ESreg (int code, int sizeflag)
12447 {
12448 if (intel_syntax)
12449 {
12450 switch (codep[-1])
12451 {
12452 case 0x6d: /* insw/insl */
12453 intel_operand_size (z_mode, sizeflag);
12454 break;
12455 case 0xa5: /* movsw/movsl/movsq */
12456 case 0xa7: /* cmpsw/cmpsl/cmpsq */
12457 case 0xab: /* stosw/stosl */
12458 case 0xaf: /* scasw/scasl */
12459 intel_operand_size (v_mode, sizeflag);
12460 break;
12461 default:
12462 intel_operand_size (b_mode, sizeflag);
12463 }
12464 }
12465 oappend ("%es:" + intel_syntax);
12466 ptr_reg (code, sizeflag);
12467 }
12468
12469 static void
12470 OP_DSreg (int code, int sizeflag)
12471 {
12472 if (intel_syntax)
12473 {
12474 switch (codep[-1])
12475 {
12476 case 0x6f: /* outsw/outsl */
12477 intel_operand_size (z_mode, sizeflag);
12478 break;
12479 case 0xa5: /* movsw/movsl/movsq */
12480 case 0xa7: /* cmpsw/cmpsl/cmpsq */
12481 case 0xad: /* lodsw/lodsl/lodsq */
12482 intel_operand_size (v_mode, sizeflag);
12483 break;
12484 default:
12485 intel_operand_size (b_mode, sizeflag);
12486 }
12487 }
12488 if ((prefixes
12489 & (PREFIX_CS
12490 | PREFIX_DS
12491 | PREFIX_SS
12492 | PREFIX_ES
12493 | PREFIX_FS
12494 | PREFIX_GS)) == 0)
12495 prefixes |= PREFIX_DS;
12496 append_seg ();
12497 ptr_reg (code, sizeflag);
12498 }
12499
12500 static void
12501 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12502 {
12503 int add;
12504 if (rex & REX_R)
12505 {
12506 USED_REX (REX_R);
12507 add = 8;
12508 }
12509 else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
12510 {
12511 lock_prefix = NULL;
12512 used_prefixes |= PREFIX_LOCK;
12513 add = 8;
12514 }
12515 else
12516 add = 0;
12517 sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
12518 oappend (scratchbuf + intel_syntax);
12519 }
12520
12521 static void
12522 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12523 {
12524 int add;
12525 USED_REX (REX_R);
12526 if (rex & REX_R)
12527 add = 8;
12528 else
12529 add = 0;
12530 if (intel_syntax)
12531 sprintf (scratchbuf, "db%d", modrm.reg + add);
12532 else
12533 sprintf (scratchbuf, "%%db%d", modrm.reg + add);
12534 oappend (scratchbuf);
12535 }
12536
12537 static void
12538 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12539 {
12540 sprintf (scratchbuf, "%%tr%d", modrm.reg);
12541 oappend (scratchbuf + intel_syntax);
12542 }
12543
12544 static void
12545 OP_R (int bytemode, int sizeflag)
12546 {
12547 if (modrm.mod == 3)
12548 OP_E (bytemode, sizeflag);
12549 else
12550 BadOp ();
12551 }
12552
12553 static void
12554 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12555 {
12556 used_prefixes |= (prefixes & PREFIX_DATA);
12557 if (prefixes & PREFIX_DATA)
12558 {
12559 int add;
12560 USED_REX (REX_R);
12561 if (rex & REX_R)
12562 add = 8;
12563 else
12564 add = 0;
12565 sprintf (scratchbuf, "%%xmm%d", modrm.reg + add);
12566 }
12567 else
12568 sprintf (scratchbuf, "%%mm%d", modrm.reg);
12569 oappend (scratchbuf + intel_syntax);
12570 }
12571
12572 static void
12573 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
12574 {
12575 int add;
12576 USED_REX (REX_R);
12577 if (rex & REX_R)
12578 add = 8;
12579 else
12580 add = 0;
12581 if (need_vex && bytemode != xmm_mode)
12582 {
12583 switch (vex.length)
12584 {
12585 case 128:
12586 sprintf (scratchbuf, "%%xmm%d", modrm.reg + add);
12587 break;
12588 case 256:
12589 sprintf (scratchbuf, "%%ymm%d", modrm.reg + add);
12590 break;
12591 default:
12592 abort ();
12593 }
12594 }
12595 else
12596 sprintf (scratchbuf, "%%xmm%d", modrm.reg + add);
12597 oappend (scratchbuf + intel_syntax);
12598 }
12599
12600 static void
12601 OP_EM (int bytemode, int sizeflag)
12602 {
12603 if (modrm.mod != 3)
12604 {
12605 if (intel_syntax
12606 && (bytemode == v_mode || bytemode == v_swap_mode))
12607 {
12608 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
12609 used_prefixes |= (prefixes & PREFIX_DATA);
12610 }
12611 OP_E (bytemode, sizeflag);
12612 return;
12613 }
12614
12615 if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
12616 swap_operand ();
12617
12618 /* Skip mod/rm byte. */
12619 MODRM_CHECK;
12620 codep++;
12621 used_prefixes |= (prefixes & PREFIX_DATA);
12622 if (prefixes & PREFIX_DATA)
12623 {
12624 int add;
12625
12626 USED_REX (REX_B);
12627 if (rex & REX_B)
12628 add = 8;
12629 else
12630 add = 0;
12631 sprintf (scratchbuf, "%%xmm%d", modrm.rm + add);
12632 }
12633 else
12634 sprintf (scratchbuf, "%%mm%d", modrm.rm);
12635 oappend (scratchbuf + intel_syntax);
12636 }
12637
12638 /* cvt* are the only instructions in sse2 which have
12639 both SSE and MMX operands and also have 0x66 prefix
12640 in their opcode. 0x66 was originally used to differentiate
12641 between SSE and MMX instruction(operands). So we have to handle the
12642 cvt* separately using OP_EMC and OP_MXC */
12643 static void
12644 OP_EMC (int bytemode, int sizeflag)
12645 {
12646 if (modrm.mod != 3)
12647 {
12648 if (intel_syntax && bytemode == v_mode)
12649 {
12650 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
12651 used_prefixes |= (prefixes & PREFIX_DATA);
12652 }
12653 OP_E (bytemode, sizeflag);
12654 return;
12655 }
12656
12657 /* Skip mod/rm byte. */
12658 MODRM_CHECK;
12659 codep++;
12660 used_prefixes |= (prefixes & PREFIX_DATA);
12661 sprintf (scratchbuf, "%%mm%d", modrm.rm);
12662 oappend (scratchbuf + intel_syntax);
12663 }
12664
12665 static void
12666 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12667 {
12668 used_prefixes |= (prefixes & PREFIX_DATA);
12669 sprintf (scratchbuf, "%%mm%d", modrm.reg);
12670 oappend (scratchbuf + intel_syntax);
12671 }
12672
12673 static void
12674 OP_EX (int bytemode, int sizeflag)
12675 {
12676 int add;
12677 if (modrm.mod != 3)
12678 {
12679 OP_E (bytemode, sizeflag);
12680 return;
12681 }
12682 USED_REX (REX_B);
12683 if (rex & REX_B)
12684 add = 8;
12685 else
12686 add = 0;
12687
12688 if ((sizeflag & SUFFIX_ALWAYS)
12689 && (bytemode == x_swap_mode
12690 || bytemode == d_swap_mode
12691 || bytemode == q_swap_mode))
12692 swap_operand ();
12693
12694 /* Skip mod/rm byte. */
12695 MODRM_CHECK;
12696 codep++;
12697 if (need_vex
12698 && bytemode != xmm_mode
12699 && bytemode != xmmq_mode)
12700 {
12701 switch (vex.length)
12702 {
12703 case 128:
12704 sprintf (scratchbuf, "%%xmm%d", modrm.rm + add);
12705 break;
12706 case 256:
12707 sprintf (scratchbuf, "%%ymm%d", modrm.rm + add);
12708 break;
12709 default:
12710 abort ();
12711 }
12712 }
12713 else
12714 sprintf (scratchbuf, "%%xmm%d", modrm.rm + add);
12715 oappend (scratchbuf + intel_syntax);
12716 }
12717
12718 static void
12719 OP_MS (int bytemode, int sizeflag)
12720 {
12721 if (modrm.mod == 3)
12722 OP_EM (bytemode, sizeflag);
12723 else
12724 BadOp ();
12725 }
12726
12727 static void
12728 OP_XS (int bytemode, int sizeflag)
12729 {
12730 if (modrm.mod == 3)
12731 OP_EX (bytemode, sizeflag);
12732 else
12733 BadOp ();
12734 }
12735
12736 static void
12737 OP_M (int bytemode, int sizeflag)
12738 {
12739 if (modrm.mod == 3)
12740 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
12741 BadOp ();
12742 else
12743 OP_E (bytemode, sizeflag);
12744 }
12745
12746 static void
12747 OP_0f07 (int bytemode, int sizeflag)
12748 {
12749 if (modrm.mod != 3 || modrm.rm != 0)
12750 BadOp ();
12751 else
12752 OP_E (bytemode, sizeflag);
12753 }
12754
12755 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
12756 32bit mode and "xchg %rax,%rax" in 64bit mode. */
12757
12758 static void
12759 NOP_Fixup1 (int bytemode, int sizeflag)
12760 {
12761 if ((prefixes & PREFIX_DATA) != 0
12762 || (rex != 0
12763 && rex != 0x48
12764 && address_mode == mode_64bit))
12765 OP_REG (bytemode, sizeflag);
12766 else
12767 strcpy (obuf, "nop");
12768 }
12769
12770 static void
12771 NOP_Fixup2 (int bytemode, int sizeflag)
12772 {
12773 if ((prefixes & PREFIX_DATA) != 0
12774 || (rex != 0
12775 && rex != 0x48
12776 && address_mode == mode_64bit))
12777 OP_IMREG (bytemode, sizeflag);
12778 }
12779
12780 static const char *const Suffix3DNow[] = {
12781 /* 00 */ NULL, NULL, NULL, NULL,
12782 /* 04 */ NULL, NULL, NULL, NULL,
12783 /* 08 */ NULL, NULL, NULL, NULL,
12784 /* 0C */ "pi2fw", "pi2fd", NULL, NULL,
12785 /* 10 */ NULL, NULL, NULL, NULL,
12786 /* 14 */ NULL, NULL, NULL, NULL,
12787 /* 18 */ NULL, NULL, NULL, NULL,
12788 /* 1C */ "pf2iw", "pf2id", NULL, NULL,
12789 /* 20 */ NULL, NULL, NULL, NULL,
12790 /* 24 */ NULL, NULL, NULL, NULL,
12791 /* 28 */ NULL, NULL, NULL, NULL,
12792 /* 2C */ NULL, NULL, NULL, NULL,
12793 /* 30 */ NULL, NULL, NULL, NULL,
12794 /* 34 */ NULL, NULL, NULL, NULL,
12795 /* 38 */ NULL, NULL, NULL, NULL,
12796 /* 3C */ NULL, NULL, NULL, NULL,
12797 /* 40 */ NULL, NULL, NULL, NULL,
12798 /* 44 */ NULL, NULL, NULL, NULL,
12799 /* 48 */ NULL, NULL, NULL, NULL,
12800 /* 4C */ NULL, NULL, NULL, NULL,
12801 /* 50 */ NULL, NULL, NULL, NULL,
12802 /* 54 */ NULL, NULL, NULL, NULL,
12803 /* 58 */ NULL, NULL, NULL, NULL,
12804 /* 5C */ NULL, NULL, NULL, NULL,
12805 /* 60 */ NULL, NULL, NULL, NULL,
12806 /* 64 */ NULL, NULL, NULL, NULL,
12807 /* 68 */ NULL, NULL, NULL, NULL,
12808 /* 6C */ NULL, NULL, NULL, NULL,
12809 /* 70 */ NULL, NULL, NULL, NULL,
12810 /* 74 */ NULL, NULL, NULL, NULL,
12811 /* 78 */ NULL, NULL, NULL, NULL,
12812 /* 7C */ NULL, NULL, NULL, NULL,
12813 /* 80 */ NULL, NULL, NULL, NULL,
12814 /* 84 */ NULL, NULL, NULL, NULL,
12815 /* 88 */ NULL, NULL, "pfnacc", NULL,
12816 /* 8C */ NULL, NULL, "pfpnacc", NULL,
12817 /* 90 */ "pfcmpge", NULL, NULL, NULL,
12818 /* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt",
12819 /* 98 */ NULL, NULL, "pfsub", NULL,
12820 /* 9C */ NULL, NULL, "pfadd", NULL,
12821 /* A0 */ "pfcmpgt", NULL, NULL, NULL,
12822 /* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1",
12823 /* A8 */ NULL, NULL, "pfsubr", NULL,
12824 /* AC */ NULL, NULL, "pfacc", NULL,
12825 /* B0 */ "pfcmpeq", NULL, NULL, NULL,
12826 /* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw",
12827 /* B8 */ NULL, NULL, NULL, "pswapd",
12828 /* BC */ NULL, NULL, NULL, "pavgusb",
12829 /* C0 */ NULL, NULL, NULL, NULL,
12830 /* C4 */ NULL, NULL, NULL, NULL,
12831 /* C8 */ NULL, NULL, NULL, NULL,
12832 /* CC */ NULL, NULL, NULL, NULL,
12833 /* D0 */ NULL, NULL, NULL, NULL,
12834 /* D4 */ NULL, NULL, NULL, NULL,
12835 /* D8 */ NULL, NULL, NULL, NULL,
12836 /* DC */ NULL, NULL, NULL, NULL,
12837 /* E0 */ NULL, NULL, NULL, NULL,
12838 /* E4 */ NULL, NULL, NULL, NULL,
12839 /* E8 */ NULL, NULL, NULL, NULL,
12840 /* EC */ NULL, NULL, NULL, NULL,
12841 /* F0 */ NULL, NULL, NULL, NULL,
12842 /* F4 */ NULL, NULL, NULL, NULL,
12843 /* F8 */ NULL, NULL, NULL, NULL,
12844 /* FC */ NULL, NULL, NULL, NULL,
12845 };
12846
12847 static void
12848 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12849 {
12850 const char *mnemonic;
12851
12852 FETCH_DATA (the_info, codep + 1);
12853 /* AMD 3DNow! instructions are specified by an opcode suffix in the
12854 place where an 8-bit immediate would normally go. ie. the last
12855 byte of the instruction. */
12856 obufp = mnemonicendp;
12857 mnemonic = Suffix3DNow[*codep++ & 0xff];
12858 if (mnemonic)
12859 oappend (mnemonic);
12860 else
12861 {
12862 /* Since a variable sized modrm/sib chunk is between the start
12863 of the opcode (0x0f0f) and the opcode suffix, we need to do
12864 all the modrm processing first, and don't know until now that
12865 we have a bad opcode. This necessitates some cleaning up. */
12866 op_out[0][0] = '\0';
12867 op_out[1][0] = '\0';
12868 BadOp ();
12869 }
12870 mnemonicendp = obufp;
12871 }
12872
12873 static struct op simd_cmp_op[] =
12874 {
12875 { STRING_COMMA_LEN ("eq") },
12876 { STRING_COMMA_LEN ("lt") },
12877 { STRING_COMMA_LEN ("le") },
12878 { STRING_COMMA_LEN ("unord") },
12879 { STRING_COMMA_LEN ("neq") },
12880 { STRING_COMMA_LEN ("nlt") },
12881 { STRING_COMMA_LEN ("nle") },
12882 { STRING_COMMA_LEN ("ord") }
12883 };
12884
12885 static void
12886 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12887 {
12888 unsigned int cmp_type;
12889
12890 FETCH_DATA (the_info, codep + 1);
12891 cmp_type = *codep++ & 0xff;
12892 if (cmp_type < ARRAY_SIZE (simd_cmp_op))
12893 {
12894 char suffix [3];
12895 char *p = mnemonicendp - 2;
12896 suffix[0] = p[0];
12897 suffix[1] = p[1];
12898 suffix[2] = '\0';
12899 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
12900 mnemonicendp += simd_cmp_op[cmp_type].len;
12901 }
12902 else
12903 {
12904 /* We have a reserved extension byte. Output it directly. */
12905 scratchbuf[0] = '$';
12906 print_operand_value (scratchbuf + 1, 1, cmp_type);
12907 oappend (scratchbuf + intel_syntax);
12908 scratchbuf[0] = '\0';
12909 }
12910 }
12911
12912 static void
12913 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
12914 int sizeflag ATTRIBUTE_UNUSED)
12915 {
12916 /* mwait %eax,%ecx */
12917 if (!intel_syntax)
12918 {
12919 const char **names = (address_mode == mode_64bit
12920 ? names64 : names32);
12921 strcpy (op_out[0], names[0]);
12922 strcpy (op_out[1], names[1]);
12923 two_source_ops = 1;
12924 }
12925 /* Skip mod/rm byte. */
12926 MODRM_CHECK;
12927 codep++;
12928 }
12929
12930 static void
12931 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
12932 int sizeflag ATTRIBUTE_UNUSED)
12933 {
12934 /* monitor %eax,%ecx,%edx" */
12935 if (!intel_syntax)
12936 {
12937 const char **op1_names;
12938 const char **names = (address_mode == mode_64bit
12939 ? names64 : names32);
12940
12941 if (!(prefixes & PREFIX_ADDR))
12942 op1_names = (address_mode == mode_16bit
12943 ? names16 : names);
12944 else
12945 {
12946 /* Remove "addr16/addr32". */
12947 addr_prefix = NULL;
12948 op1_names = (address_mode != mode_32bit
12949 ? names32 : names16);
12950 used_prefixes |= PREFIX_ADDR;
12951 }
12952 strcpy (op_out[0], op1_names[0]);
12953 strcpy (op_out[1], names[1]);
12954 strcpy (op_out[2], names[2]);
12955 two_source_ops = 1;
12956 }
12957 /* Skip mod/rm byte. */
12958 MODRM_CHECK;
12959 codep++;
12960 }
12961
12962 static void
12963 BadOp (void)
12964 {
12965 /* Throw away prefixes and 1st. opcode byte. */
12966 codep = insn_codep + 1;
12967 oappend ("(bad)");
12968 }
12969
12970 static void
12971 REP_Fixup (int bytemode, int sizeflag)
12972 {
12973 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
12974 lods and stos. */
12975 if (prefixes & PREFIX_REPZ)
12976 repz_prefix = "rep ";
12977
12978 switch (bytemode)
12979 {
12980 case al_reg:
12981 case eAX_reg:
12982 case indir_dx_reg:
12983 OP_IMREG (bytemode, sizeflag);
12984 break;
12985 case eDI_reg:
12986 OP_ESreg (bytemode, sizeflag);
12987 break;
12988 case eSI_reg:
12989 OP_DSreg (bytemode, sizeflag);
12990 break;
12991 default:
12992 abort ();
12993 break;
12994 }
12995 }
12996
12997 static void
12998 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
12999 {
13000 USED_REX (REX_W);
13001 if (rex & REX_W)
13002 {
13003 /* Change cmpxchg8b to cmpxchg16b. */
13004 char *p = mnemonicendp - 2;
13005 mnemonicendp = stpcpy (p, "16b");
13006 bytemode = o_mode;
13007 }
13008 OP_M (bytemode, sizeflag);
13009 }
13010
13011 static void
13012 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
13013 {
13014 if (need_vex)
13015 {
13016 switch (vex.length)
13017 {
13018 case 128:
13019 sprintf (scratchbuf, "%%xmm%d", reg);
13020 break;
13021 case 256:
13022 sprintf (scratchbuf, "%%ymm%d", reg);
13023 break;
13024 default:
13025 abort ();
13026 }
13027 }
13028 else
13029 sprintf (scratchbuf, "%%xmm%d", reg);
13030 oappend (scratchbuf + intel_syntax);
13031 }
13032
13033 static void
13034 CRC32_Fixup (int bytemode, int sizeflag)
13035 {
13036 /* Add proper suffix to "crc32". */
13037 char *p = mnemonicendp;
13038
13039 switch (bytemode)
13040 {
13041 case b_mode:
13042 if (intel_syntax)
13043 goto skip;
13044
13045 *p++ = 'b';
13046 break;
13047 case v_mode:
13048 if (intel_syntax)
13049 goto skip;
13050
13051 USED_REX (REX_W);
13052 if (rex & REX_W)
13053 *p++ = 'q';
13054 else if (sizeflag & DFLAG)
13055 *p++ = 'l';
13056 else
13057 *p++ = 'w';
13058 used_prefixes |= (prefixes & PREFIX_DATA);
13059 break;
13060 default:
13061 oappend (INTERNAL_DISASSEMBLER_ERROR);
13062 break;
13063 }
13064 mnemonicendp = p;
13065 *p = '\0';
13066
13067 skip:
13068 if (modrm.mod == 3)
13069 {
13070 int add;
13071
13072 /* Skip mod/rm byte. */
13073 MODRM_CHECK;
13074 codep++;
13075
13076 USED_REX (REX_B);
13077 add = (rex & REX_B) ? 8 : 0;
13078 if (bytemode == b_mode)
13079 {
13080 USED_REX (0);
13081 if (rex)
13082 oappend (names8rex[modrm.rm + add]);
13083 else
13084 oappend (names8[modrm.rm + add]);
13085 }
13086 else
13087 {
13088 USED_REX (REX_W);
13089 if (rex & REX_W)
13090 oappend (names64[modrm.rm + add]);
13091 else if ((prefixes & PREFIX_DATA))
13092 oappend (names16[modrm.rm + add]);
13093 else
13094 oappend (names32[modrm.rm + add]);
13095 }
13096 }
13097 else
13098 OP_E (bytemode, sizeflag);
13099 }
13100
13101 /* Print a DREX argument as either a register or memory operation. */
13102 static void
13103 print_drex_arg (unsigned int reg, int bytemode, int sizeflag)
13104 {
13105 if (reg == DREX_REG_UNKNOWN)
13106 BadOp ();
13107
13108 else if (reg != DREX_REG_MEMORY)
13109 {
13110 sprintf (scratchbuf, "%%xmm%d", reg);
13111 oappend (scratchbuf + intel_syntax);
13112 }
13113
13114 else
13115 OP_E_extended (bytemode, sizeflag, 1);
13116 }
13117
13118 /* SSE5 instructions that have 4 arguments are encoded as:
13119 0f 24 <sub-opcode> <modrm> <optional-sib> <drex> <offset>.
13120
13121 The <sub-opcode> byte has 1 bit (0x4) that is combined with 1 bit in
13122 the DREX field (0x8) to determine how the arguments are laid out.
13123 The destination register must be the same register as one of the
13124 inputs, and it is encoded in the DREX byte. No REX prefix is used
13125 for these instructions, since the DREX field contains the 3 extension
13126 bits provided by the REX prefix.
13127
13128 The bytemode argument adds 2 extra bits for passing extra information:
13129 DREX_OC1 -- Set the OC1 bit to indicate dest == 1st arg
13130 DREX_NO_OC0 -- OC0 in DREX is invalid
13131 (but pretend it is set). */
13132
13133 static void
13134 OP_DREX4 (int flag_bytemode, int sizeflag)
13135 {
13136 unsigned int drex_byte;
13137 unsigned int regs[4];
13138 unsigned int modrm_regmem;
13139 unsigned int modrm_reg;
13140 unsigned int drex_reg;
13141 int bytemode;
13142 int rex_save = rex;
13143 int rex_used_save = rex_used;
13144 int has_sib = 0;
13145 int oc1 = (flag_bytemode & DREX_OC1) ? 2 : 0;
13146 int oc0;
13147 int i;
13148
13149 bytemode = flag_bytemode & ~ DREX_MASK;
13150
13151 for (i = 0; i < 4; i++)
13152 regs[i] = DREX_REG_UNKNOWN;
13153
13154 /* Determine if we have a SIB byte in addition to MODRM before the
13155 DREX byte. */
13156 if (((sizeflag & AFLAG) || address_mode == mode_64bit)
13157 && (modrm.mod != 3)
13158 && (modrm.rm == 4))
13159 has_sib = 1;
13160
13161 /* Get the DREX byte. */
13162 FETCH_DATA (the_info, codep + 2 + has_sib);
13163 drex_byte = codep[has_sib+1];
13164 drex_reg = DREX_XMM (drex_byte);
13165 modrm_reg = modrm.reg + ((drex_byte & REX_R) ? 8 : 0);
13166
13167 /* Is OC0 legal? If not, hardwire oc0 == 1. */
13168 if (flag_bytemode & DREX_NO_OC0)
13169 {
13170 oc0 = 1;
13171 if (DREX_OC0 (drex_byte))
13172 BadOp ();
13173 }
13174 else
13175 oc0 = DREX_OC0 (drex_byte);
13176
13177 if (modrm.mod == 3)
13178 {
13179 /* regmem == register */
13180 modrm_regmem = modrm.rm + ((drex_byte & REX_B) ? 8 : 0);
13181 rex = rex_used = 0;
13182 /* skip modrm/drex since we don't call OP_E_extended */
13183 codep += 2;
13184 }
13185 else
13186 {
13187 /* regmem == memory, fill in appropriate REX bits */
13188 modrm_regmem = DREX_REG_MEMORY;
13189 rex = drex_byte & (REX_B | REX_X | REX_R);
13190 if (rex)
13191 rex |= REX_OPCODE;
13192 rex_used = rex;
13193 }
13194
13195 /* Based on the OC1/OC0 bits, lay out the arguments in the correct
13196 order. */
13197 switch (oc0 + oc1)
13198 {
13199 default:
13200 BadOp ();
13201 return;
13202
13203 case 0:
13204 regs[0] = modrm_regmem;
13205 regs[1] = modrm_reg;
13206 regs[2] = drex_reg;
13207 regs[3] = drex_reg;
13208 break;
13209
13210 case 1:
13211 regs[0] = modrm_reg;
13212 regs[1] = modrm_regmem;
13213 regs[2] = drex_reg;
13214 regs[3] = drex_reg;
13215 break;
13216
13217 case 2:
13218 regs[0] = drex_reg;
13219 regs[1] = modrm_regmem;
13220 regs[2] = modrm_reg;
13221 regs[3] = drex_reg;
13222 break;
13223
13224 case 3:
13225 regs[0] = drex_reg;
13226 regs[1] = modrm_reg;
13227 regs[2] = modrm_regmem;
13228 regs[3] = drex_reg;
13229 break;
13230 }
13231
13232 /* Print out the arguments. */
13233 for (i = 0; i < 4; i++)
13234 {
13235 int j = (intel_syntax) ? 3 - i : i;
13236 if (i > 0)
13237 {
13238 *obufp++ = ',';
13239 *obufp = '\0';
13240 }
13241
13242 print_drex_arg (regs[j], bytemode, sizeflag);
13243 }
13244
13245 rex = rex_save;
13246 rex_used = rex_used_save;
13247 }
13248
13249 /* SSE5 instructions that have 3 arguments, and are encoded as:
13250 0f 24 <sub-opcode> <modrm> <optional-sib> <drex> <offset> (or)
13251 0f 25 <sub-opcode> <modrm> <optional-sib> <drex> <offset> <cmp-byte>
13252
13253 The DREX field has 1 bit (0x8) to determine how the arguments are
13254 laid out. The destination register is encoded in the DREX byte.
13255 No REX prefix is used for these instructions, since the DREX field
13256 contains the 3 extension bits provided by the REX prefix. */
13257
13258 static void
13259 OP_DREX3 (int flag_bytemode, int sizeflag)
13260 {
13261 unsigned int drex_byte;
13262 unsigned int regs[3];
13263 unsigned int modrm_regmem;
13264 unsigned int modrm_reg;
13265 unsigned int drex_reg;
13266 int bytemode;
13267 int rex_save = rex;
13268 int rex_used_save = rex_used;
13269 int has_sib = 0;
13270 int oc0;
13271 int i;
13272
13273 bytemode = flag_bytemode & ~ DREX_MASK;
13274
13275 for (i = 0; i < 3; i++)
13276 regs[i] = DREX_REG_UNKNOWN;
13277
13278 /* Determine if we have a SIB byte in addition to MODRM before the
13279 DREX byte. */
13280 if (((sizeflag & AFLAG) || address_mode == mode_64bit)
13281 && (modrm.mod != 3)
13282 && (modrm.rm == 4))
13283 has_sib = 1;
13284
13285 /* Get the DREX byte. */
13286 FETCH_DATA (the_info, codep + 2 + has_sib);
13287 drex_byte = codep[has_sib+1];
13288 drex_reg = DREX_XMM (drex_byte);
13289 modrm_reg = modrm.reg + ((drex_byte & REX_R) ? 8 : 0);
13290
13291 /* Is OC0 legal? If not, hardwire oc0 == 0 */
13292 oc0 = DREX_OC0 (drex_byte);
13293 if ((flag_bytemode & DREX_NO_OC0) && oc0)
13294 BadOp ();
13295
13296 if (modrm.mod == 3)
13297 {
13298 /* regmem == register */
13299 modrm_regmem = modrm.rm + ((drex_byte & REX_B) ? 8 : 0);
13300 rex = rex_used = 0;
13301 /* skip modrm/drex since we don't call OP_E_extended. */
13302 codep += 2;
13303 }
13304 else
13305 {
13306 /* regmem == memory, fill in appropriate REX bits. */
13307 modrm_regmem = DREX_REG_MEMORY;
13308 rex = drex_byte & (REX_B | REX_X | REX_R);
13309 if (rex)
13310 rex |= REX_OPCODE;
13311 rex_used = rex;
13312 }
13313
13314 /* Based on the OC1/OC0 bits, lay out the arguments in the correct
13315 order. */
13316 switch (oc0)
13317 {
13318 default:
13319 BadOp ();
13320 return;
13321
13322 case 0:
13323 regs[0] = modrm_regmem;
13324 regs[1] = modrm_reg;
13325 regs[2] = drex_reg;
13326 break;
13327
13328 case 1:
13329 regs[0] = modrm_reg;
13330 regs[1] = modrm_regmem;
13331 regs[2] = drex_reg;
13332 break;
13333 }
13334
13335 /* Print out the arguments. */
13336 for (i = 0; i < 3; i++)
13337 {
13338 int j = (intel_syntax) ? 2 - i : i;
13339 if (i > 0)
13340 {
13341 *obufp++ = ',';
13342 *obufp = '\0';
13343 }
13344
13345 print_drex_arg (regs[j], bytemode, sizeflag);
13346 }
13347
13348 rex = rex_save;
13349 rex_used = rex_used_save;
13350 }
13351
13352 /* Emit a floating point comparison for comp<xx> instructions. */
13353
13354 static void
13355 OP_DREX_FCMP (int bytemode ATTRIBUTE_UNUSED,
13356 int sizeflag ATTRIBUTE_UNUSED)
13357 {
13358 unsigned char byte;
13359
13360 static const char *const cmp_test[] = {
13361 "eq",
13362 "lt",
13363 "le",
13364 "unord",
13365 "ne",
13366 "nlt",
13367 "nle",
13368 "ord",
13369 "ueq",
13370 "ult",
13371 "ule",
13372 "false",
13373 "une",
13374 "unlt",
13375 "unle",
13376 "true"
13377 };
13378
13379 FETCH_DATA (the_info, codep + 1);
13380 byte = *codep & 0xff;
13381
13382 if (byte >= ARRAY_SIZE (cmp_test)
13383 || obuf[0] != 'c'
13384 || obuf[1] != 'o'
13385 || obuf[2] != 'm')
13386 {
13387 /* The instruction isn't one we know about, so just append the
13388 extension byte as a numeric value. */
13389 OP_I (b_mode, 0);
13390 }
13391
13392 else
13393 {
13394 sprintf (scratchbuf, "com%s%s", cmp_test[byte], obuf+3);
13395 mnemonicendp = stpcpy (obuf, scratchbuf);
13396 codep++;
13397 }
13398 }
13399
13400 /* Emit an integer point comparison for pcom<xx> instructions,
13401 rewriting the instruction to have the test inside of it. */
13402
13403 static void
13404 OP_DREX_ICMP (int bytemode ATTRIBUTE_UNUSED,
13405 int sizeflag ATTRIBUTE_UNUSED)
13406 {
13407 unsigned char byte;
13408
13409 static const char *const cmp_test[] = {
13410 "lt",
13411 "le",
13412 "gt",
13413 "ge",
13414 "eq",
13415 "ne",
13416 "false",
13417 "true"
13418 };
13419
13420 FETCH_DATA (the_info, codep + 1);
13421 byte = *codep & 0xff;
13422
13423 if (byte >= ARRAY_SIZE (cmp_test)
13424 || obuf[0] != 'p'
13425 || obuf[1] != 'c'
13426 || obuf[2] != 'o'
13427 || obuf[3] != 'm')
13428 {
13429 /* The instruction isn't one we know about, so just print the
13430 comparison test byte as a numeric value. */
13431 OP_I (b_mode, 0);
13432 }
13433
13434 else
13435 {
13436 sprintf (scratchbuf, "pcom%s%s", cmp_test[byte], obuf+4);
13437 mnemonicendp = stpcpy (obuf, scratchbuf);
13438 codep++;
13439 }
13440 }
13441
13442 /* Display the destination register operand for instructions with
13443 VEX. */
13444
13445 static void
13446 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13447 {
13448 if (!need_vex)
13449 abort ();
13450
13451 if (!need_vex_reg)
13452 return;
13453
13454 switch (vex.length)
13455 {
13456 case 128:
13457 switch (bytemode)
13458 {
13459 case vex_mode:
13460 case vex128_mode:
13461 break;
13462 default:
13463 abort ();
13464 return;
13465 }
13466
13467 sprintf (scratchbuf, "%%xmm%d", vex.register_specifier);
13468 break;
13469 case 256:
13470 switch (bytemode)
13471 {
13472 case vex_mode:
13473 case vex256_mode:
13474 break;
13475 default:
13476 abort ();
13477 return;
13478 }
13479
13480 sprintf (scratchbuf, "%%ymm%d", vex.register_specifier);
13481 break;
13482 default:
13483 abort ();
13484 break;
13485 }
13486 oappend (scratchbuf + intel_syntax);
13487 }
13488
13489 static void
13490 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13491 {
13492 int reg;
13493 FETCH_DATA (the_info, codep + 1);
13494 reg = *codep++;
13495
13496 if (bytemode != x_mode)
13497 abort ();
13498
13499 if (reg & 0xf)
13500 BadOp ();
13501
13502 reg >>= 4;
13503 if (reg > 7 && address_mode != mode_64bit)
13504 BadOp ();
13505
13506 switch (vex.length)
13507 {
13508 case 128:
13509 sprintf (scratchbuf, "%%xmm%d", reg);
13510 break;
13511 case 256:
13512 sprintf (scratchbuf, "%%ymm%d", reg);
13513 break;
13514 default:
13515 abort ();
13516 }
13517 oappend (scratchbuf + intel_syntax);
13518 }
13519
13520 static void
13521 OP_EX_Vex (int bytemode, int sizeflag)
13522 {
13523 if (modrm.mod != 3)
13524 {
13525 if (vex.register_specifier != 0)
13526 BadOp ();
13527 need_vex_reg = 0;
13528 }
13529 OP_EX (bytemode, sizeflag);
13530 }
13531
13532 static void
13533 OP_XMM_Vex (int bytemode, int sizeflag)
13534 {
13535 if (modrm.mod != 3)
13536 {
13537 if (vex.register_specifier != 0)
13538 BadOp ();
13539 need_vex_reg = 0;
13540 }
13541 OP_XMM (bytemode, sizeflag);
13542 }
13543
13544 static void
13545 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13546 {
13547 switch (vex.length)
13548 {
13549 case 128:
13550 mnemonicendp = stpcpy (obuf, "vzeroupper");
13551 break;
13552 case 256:
13553 mnemonicendp = stpcpy (obuf, "vzeroall");
13554 break;
13555 default:
13556 abort ();
13557 }
13558 }
13559
13560 static struct op vex_cmp_op[] =
13561 {
13562 { STRING_COMMA_LEN ("eq") },
13563 { STRING_COMMA_LEN ("lt") },
13564 { STRING_COMMA_LEN ("le") },
13565 { STRING_COMMA_LEN ("unord") },
13566 { STRING_COMMA_LEN ("neq") },
13567 { STRING_COMMA_LEN ("nlt") },
13568 { STRING_COMMA_LEN ("nle") },
13569 { STRING_COMMA_LEN ("ord") },
13570 { STRING_COMMA_LEN ("eq_uq") },
13571 { STRING_COMMA_LEN ("nge") },
13572 { STRING_COMMA_LEN ("ngt") },
13573 { STRING_COMMA_LEN ("false") },
13574 { STRING_COMMA_LEN ("neq_oq") },
13575 { STRING_COMMA_LEN ("ge") },
13576 { STRING_COMMA_LEN ("gt") },
13577 { STRING_COMMA_LEN ("true") },
13578 { STRING_COMMA_LEN ("eq_os") },
13579 { STRING_COMMA_LEN ("lt_oq") },
13580 { STRING_COMMA_LEN ("le_oq") },
13581 { STRING_COMMA_LEN ("unord_s") },
13582 { STRING_COMMA_LEN ("neq_us") },
13583 { STRING_COMMA_LEN ("nlt_uq") },
13584 { STRING_COMMA_LEN ("nle_uq") },
13585 { STRING_COMMA_LEN ("ord_s") },
13586 { STRING_COMMA_LEN ("eq_us") },
13587 { STRING_COMMA_LEN ("nge_uq") },
13588 { STRING_COMMA_LEN ("ngt_uq") },
13589 { STRING_COMMA_LEN ("false_os") },
13590 { STRING_COMMA_LEN ("neq_os") },
13591 { STRING_COMMA_LEN ("ge_oq") },
13592 { STRING_COMMA_LEN ("gt_oq") },
13593 { STRING_COMMA_LEN ("true_us") },
13594 };
13595
13596 static void
13597 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13598 {
13599 unsigned int cmp_type;
13600
13601 FETCH_DATA (the_info, codep + 1);
13602 cmp_type = *codep++ & 0xff;
13603 if (cmp_type < ARRAY_SIZE (vex_cmp_op))
13604 {
13605 char suffix [3];
13606 char *p = mnemonicendp - 2;
13607 suffix[0] = p[0];
13608 suffix[1] = p[1];
13609 suffix[2] = '\0';
13610 sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
13611 mnemonicendp += vex_cmp_op[cmp_type].len;
13612 }
13613 else
13614 {
13615 /* We have a reserved extension byte. Output it directly. */
13616 scratchbuf[0] = '$';
13617 print_operand_value (scratchbuf + 1, 1, cmp_type);
13618 oappend (scratchbuf + intel_syntax);
13619 scratchbuf[0] = '\0';
13620 }
13621 }
13622
13623 static const struct op pclmul_op[] =
13624 {
13625 { STRING_COMMA_LEN ("lql") },
13626 { STRING_COMMA_LEN ("hql") },
13627 { STRING_COMMA_LEN ("lqh") },
13628 { STRING_COMMA_LEN ("hqh") }
13629 };
13630
13631 static void
13632 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
13633 int sizeflag ATTRIBUTE_UNUSED)
13634 {
13635 unsigned int pclmul_type;
13636
13637 FETCH_DATA (the_info, codep + 1);
13638 pclmul_type = *codep++ & 0xff;
13639 switch (pclmul_type)
13640 {
13641 case 0x10:
13642 pclmul_type = 2;
13643 break;
13644 case 0x11:
13645 pclmul_type = 3;
13646 break;
13647 default:
13648 break;
13649 }
13650 if (pclmul_type < ARRAY_SIZE (pclmul_op))
13651 {
13652 char suffix [4];
13653 char *p = mnemonicendp - 3;
13654 suffix[0] = p[0];
13655 suffix[1] = p[1];
13656 suffix[2] = p[2];
13657 suffix[3] = '\0';
13658 sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
13659 mnemonicendp += pclmul_op[pclmul_type].len;
13660 }
13661 else
13662 {
13663 /* We have a reserved extension byte. Output it directly. */
13664 scratchbuf[0] = '$';
13665 print_operand_value (scratchbuf + 1, 1, pclmul_type);
13666 oappend (scratchbuf + intel_syntax);
13667 scratchbuf[0] = '\0';
13668 }
13669 }
13670
13671 static void
13672 MOVBE_Fixup (int bytemode, int sizeflag)
13673 {
13674 /* Add proper suffix to "movbe". */
13675 char *p = mnemonicendp;
13676
13677 switch (bytemode)
13678 {
13679 case v_mode:
13680 if (intel_syntax)
13681 goto skip;
13682
13683 USED_REX (REX_W);
13684 if (sizeflag & SUFFIX_ALWAYS)
13685 {
13686 if (rex & REX_W)
13687 *p++ = 'q';
13688 else if (sizeflag & DFLAG)
13689 *p++ = 'l';
13690 else
13691 *p++ = 'w';
13692 }
13693 used_prefixes |= (prefixes & PREFIX_DATA);
13694 break;
13695 default:
13696 oappend (INTERNAL_DISASSEMBLER_ERROR);
13697 break;
13698 }
13699 mnemonicendp = p;
13700 *p = '\0';
13701
13702 skip:
13703 OP_M (bytemode, sizeflag);
13704 }
GDB Binutils - Deliverables
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