1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright (C) 1988-2019 Free Software Foundation, Inc.
4 This file is part of the GNU opcodes library.
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
24 modified by John Hassey (hassey@dg-rtp.dg.com)
25 x86-64 support added by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
28 /* The main tables describing the instructions is essentially a copy
29 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
30 Programmers Manual. Usually, there is a capital letter, followed
31 by a small letter. The capital letter tell the addressing mode,
32 and the small letter tells about the operand size. Refer to
33 the Intel manual for details. */
36 #include "disassemble.h"
38 #include "opcode/i386.h"
39 #include "libiberty.h"
43 static int print_insn (bfd_vma
, disassemble_info
*);
44 static void dofloat (int);
45 static void OP_ST (int, int);
46 static void OP_STi (int, int);
47 static int putop (const char *, int);
48 static void oappend (const char *);
49 static void append_seg (void);
50 static void OP_indirE (int, int);
51 static void print_operand_value (char *, int, bfd_vma
);
52 static void OP_E_register (int, int);
53 static void OP_E_memory (int, int);
54 static void print_displacement (char *, bfd_vma
);
55 static void OP_E (int, int);
56 static void OP_G (int, int);
57 static bfd_vma
get64 (void);
58 static bfd_signed_vma
get32 (void);
59 static bfd_signed_vma
get32s (void);
60 static int get16 (void);
61 static void set_op (bfd_vma
, int);
62 static void OP_Skip_MODRM (int, int);
63 static void OP_REG (int, int);
64 static void OP_IMREG (int, int);
65 static void OP_I (int, int);
66 static void OP_I64 (int, int);
67 static void OP_sI (int, int);
68 static void OP_J (int, int);
69 static void OP_SEG (int, int);
70 static void OP_DIR (int, int);
71 static void OP_OFF (int, int);
72 static void OP_OFF64 (int, int);
73 static void ptr_reg (int, int);
74 static void OP_ESreg (int, int);
75 static void OP_DSreg (int, int);
76 static void OP_C (int, int);
77 static void OP_D (int, int);
78 static void OP_T (int, int);
79 static void OP_R (int, int);
80 static void OP_MMX (int, int);
81 static void OP_XMM (int, int);
82 static void OP_EM (int, int);
83 static void OP_EX (int, int);
84 static void OP_EMC (int,int);
85 static void OP_MXC (int,int);
86 static void OP_MS (int, int);
87 static void OP_XS (int, int);
88 static void OP_M (int, int);
89 static void OP_VEX (int, int);
90 static void OP_EX_Vex (int, int);
91 static void OP_EX_VexW (int, int);
92 static void OP_EX_VexImmW (int, int);
93 static void OP_XMM_Vex (int, int);
94 static void OP_XMM_VexW (int, int);
95 static void OP_Rounding (int, int);
96 static void OP_REG_VexI4 (int, int);
97 static void PCLMUL_Fixup (int, int);
98 static void VCMP_Fixup (int, int);
99 static void VPCMP_Fixup (int, int);
100 static void VPCOM_Fixup (int, int);
101 static void OP_0f07 (int, int);
102 static void OP_Monitor (int, int);
103 static void OP_Mwait (int, int);
104 static void OP_Mwaitx (int, int);
105 static void NOP_Fixup1 (int, int);
106 static void NOP_Fixup2 (int, int);
107 static void OP_3DNowSuffix (int, int);
108 static void CMP_Fixup (int, int);
109 static void BadOp (void);
110 static void REP_Fixup (int, int);
111 static void BND_Fixup (int, int);
112 static void NOTRACK_Fixup (int, int);
113 static void HLE_Fixup1 (int, int);
114 static void HLE_Fixup2 (int, int);
115 static void HLE_Fixup3 (int, int);
116 static void CMPXCHG8B_Fixup (int, int);
117 static void XMM_Fixup (int, int);
118 static void CRC32_Fixup (int, int);
119 static void FXSAVE_Fixup (int, int);
120 static void PCMPESTR_Fixup (int, int);
121 static void OP_LWPCB_E (int, int);
122 static void OP_LWP_E (int, int);
123 static void OP_Vex_2src_1 (int, int);
124 static void OP_Vex_2src_2 (int, int);
126 static void MOVBE_Fixup (int, int);
128 static void OP_Mask (int, int);
131 /* Points to first byte not fetched. */
132 bfd_byte
*max_fetched
;
133 bfd_byte the_buffer
[MAX_MNEM_SIZE
];
136 OPCODES_SIGJMP_BUF bailout
;
146 enum address_mode address_mode
;
148 /* Flags for the prefixes for the current instruction. See below. */
151 /* REX prefix the current instruction. See below. */
153 /* Bits of REX we've already used. */
155 /* REX bits in original REX prefix ignored. */
156 static int rex_ignored
;
157 /* Mark parts used in the REX prefix. When we are testing for
158 empty prefix (for 8bit register REX extension), just mask it
159 out. Otherwise test for REX bit is excuse for existence of REX
160 only in case value is nonzero. */
161 #define USED_REX(value) \
166 rex_used |= (value) | REX_OPCODE; \
169 rex_used |= REX_OPCODE; \
172 /* Flags for prefixes which we somehow handled when printing the
173 current instruction. */
174 static int used_prefixes
;
176 /* Flags stored in PREFIXES. */
177 #define PREFIX_REPZ 1
178 #define PREFIX_REPNZ 2
179 #define PREFIX_LOCK 4
181 #define PREFIX_SS 0x10
182 #define PREFIX_DS 0x20
183 #define PREFIX_ES 0x40
184 #define PREFIX_FS 0x80
185 #define PREFIX_GS 0x100
186 #define PREFIX_DATA 0x200
187 #define PREFIX_ADDR 0x400
188 #define PREFIX_FWAIT 0x800
190 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
191 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
193 #define FETCH_DATA(info, addr) \
194 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
195 ? 1 : fetch_data ((info), (addr)))
198 fetch_data (struct disassemble_info
*info
, bfd_byte
*addr
)
201 struct dis_private
*priv
= (struct dis_private
*) info
->private_data
;
202 bfd_vma start
= priv
->insn_start
+ (priv
->max_fetched
- priv
->the_buffer
);
204 if (addr
<= priv
->the_buffer
+ MAX_MNEM_SIZE
)
205 status
= (*info
->read_memory_func
) (start
,
207 addr
- priv
->max_fetched
,
213 /* If we did manage to read at least one byte, then
214 print_insn_i386 will do something sensible. Otherwise, print
215 an error. We do that here because this is where we know
217 if (priv
->max_fetched
== priv
->the_buffer
)
218 (*info
->memory_error_func
) (status
, start
, info
);
219 OPCODES_SIGLONGJMP (priv
->bailout
, 1);
222 priv
->max_fetched
= addr
;
226 /* Possible values for prefix requirement. */
227 #define PREFIX_IGNORED_SHIFT 16
228 #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
229 #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
230 #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
231 #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
232 #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
234 /* Opcode prefixes. */
235 #define PREFIX_OPCODE (PREFIX_REPZ \
239 /* Prefixes ignored. */
240 #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \
241 | PREFIX_IGNORED_REPNZ \
242 | PREFIX_IGNORED_DATA)
244 #define XX { NULL, 0 }
245 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
247 #define Eb { OP_E, b_mode }
248 #define Ebnd { OP_E, bnd_mode }
249 #define EbS { OP_E, b_swap_mode }
250 #define EbndS { OP_E, bnd_swap_mode }
251 #define Ev { OP_E, v_mode }
252 #define Eva { OP_E, va_mode }
253 #define Ev_bnd { OP_E, v_bnd_mode }
254 #define EvS { OP_E, v_swap_mode }
255 #define Ed { OP_E, d_mode }
256 #define Edq { OP_E, dq_mode }
257 #define Edqw { OP_E, dqw_mode }
258 #define Edqb { OP_E, dqb_mode }
259 #define Edb { OP_E, db_mode }
260 #define Edw { OP_E, dw_mode }
261 #define Edqd { OP_E, dqd_mode }
262 #define Edqa { OP_E, dqa_mode }
263 #define Eq { OP_E, q_mode }
264 #define indirEv { OP_indirE, indir_v_mode }
265 #define indirEp { OP_indirE, f_mode }
266 #define stackEv { OP_E, stack_v_mode }
267 #define Em { OP_E, m_mode }
268 #define Ew { OP_E, w_mode }
269 #define M { OP_M, 0 } /* lea, lgdt, etc. */
270 #define Ma { OP_M, a_mode }
271 #define Mb { OP_M, b_mode }
272 #define Md { OP_M, d_mode }
273 #define Mo { OP_M, o_mode }
274 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
275 #define Mq { OP_M, q_mode }
276 #define Mv_bnd { OP_M, v_bndmk_mode }
277 #define Mx { OP_M, x_mode }
278 #define Mxmm { OP_M, xmm_mode }
279 #define Gb { OP_G, b_mode }
280 #define Gbnd { OP_G, bnd_mode }
281 #define Gv { OP_G, v_mode }
282 #define Gd { OP_G, d_mode }
283 #define Gdq { OP_G, dq_mode }
284 #define Gm { OP_G, m_mode }
285 #define Gva { OP_G, va_mode }
286 #define Gw { OP_G, w_mode }
287 #define Rd { OP_R, d_mode }
288 #define Rdq { OP_R, dq_mode }
289 #define Rm { OP_R, m_mode }
290 #define Ib { OP_I, b_mode }
291 #define sIb { OP_sI, b_mode } /* sign extened byte */
292 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
293 #define Iv { OP_I, v_mode }
294 #define sIv { OP_sI, v_mode }
295 #define Iq { OP_I, q_mode }
296 #define Iv64 { OP_I64, v_mode }
297 #define Iw { OP_I, w_mode }
298 #define I1 { OP_I, const_1_mode }
299 #define Jb { OP_J, b_mode }
300 #define Jv { OP_J, v_mode }
301 #define Cm { OP_C, m_mode }
302 #define Dm { OP_D, m_mode }
303 #define Td { OP_T, d_mode }
304 #define Skip_MODRM { OP_Skip_MODRM, 0 }
306 #define RMeAX { OP_REG, eAX_reg }
307 #define RMeBX { OP_REG, eBX_reg }
308 #define RMeCX { OP_REG, eCX_reg }
309 #define RMeDX { OP_REG, eDX_reg }
310 #define RMeSP { OP_REG, eSP_reg }
311 #define RMeBP { OP_REG, eBP_reg }
312 #define RMeSI { OP_REG, eSI_reg }
313 #define RMeDI { OP_REG, eDI_reg }
314 #define RMrAX { OP_REG, rAX_reg }
315 #define RMrBX { OP_REG, rBX_reg }
316 #define RMrCX { OP_REG, rCX_reg }
317 #define RMrDX { OP_REG, rDX_reg }
318 #define RMrSP { OP_REG, rSP_reg }
319 #define RMrBP { OP_REG, rBP_reg }
320 #define RMrSI { OP_REG, rSI_reg }
321 #define RMrDI { OP_REG, rDI_reg }
322 #define RMAL { OP_REG, al_reg }
323 #define RMCL { OP_REG, cl_reg }
324 #define RMDL { OP_REG, dl_reg }
325 #define RMBL { OP_REG, bl_reg }
326 #define RMAH { OP_REG, ah_reg }
327 #define RMCH { OP_REG, ch_reg }
328 #define RMDH { OP_REG, dh_reg }
329 #define RMBH { OP_REG, bh_reg }
330 #define RMAX { OP_REG, ax_reg }
331 #define RMDX { OP_REG, dx_reg }
333 #define eAX { OP_IMREG, eAX_reg }
334 #define eBX { OP_IMREG, eBX_reg }
335 #define eCX { OP_IMREG, eCX_reg }
336 #define eDX { OP_IMREG, eDX_reg }
337 #define eSP { OP_IMREG, eSP_reg }
338 #define eBP { OP_IMREG, eBP_reg }
339 #define eSI { OP_IMREG, eSI_reg }
340 #define eDI { OP_IMREG, eDI_reg }
341 #define AL { OP_IMREG, al_reg }
342 #define CL { OP_IMREG, cl_reg }
343 #define DL { OP_IMREG, dl_reg }
344 #define BL { OP_IMREG, bl_reg }
345 #define AH { OP_IMREG, ah_reg }
346 #define CH { OP_IMREG, ch_reg }
347 #define DH { OP_IMREG, dh_reg }
348 #define BH { OP_IMREG, bh_reg }
349 #define AX { OP_IMREG, ax_reg }
350 #define DX { OP_IMREG, dx_reg }
351 #define zAX { OP_IMREG, z_mode_ax_reg }
352 #define indirDX { OP_IMREG, indir_dx_reg }
354 #define Sw { OP_SEG, w_mode }
355 #define Sv { OP_SEG, v_mode }
356 #define Ap { OP_DIR, 0 }
357 #define Ob { OP_OFF64, b_mode }
358 #define Ov { OP_OFF64, v_mode }
359 #define Xb { OP_DSreg, eSI_reg }
360 #define Xv { OP_DSreg, eSI_reg }
361 #define Xz { OP_DSreg, eSI_reg }
362 #define Yb { OP_ESreg, eDI_reg }
363 #define Yv { OP_ESreg, eDI_reg }
364 #define DSBX { OP_DSreg, eBX_reg }
366 #define es { OP_REG, es_reg }
367 #define ss { OP_REG, ss_reg }
368 #define cs { OP_REG, cs_reg }
369 #define ds { OP_REG, ds_reg }
370 #define fs { OP_REG, fs_reg }
371 #define gs { OP_REG, gs_reg }
373 #define MX { OP_MMX, 0 }
374 #define XM { OP_XMM, 0 }
375 #define XMScalar { OP_XMM, scalar_mode }
376 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
377 #define XMM { OP_XMM, xmm_mode }
378 #define XMxmmq { OP_XMM, xmmq_mode }
379 #define EM { OP_EM, v_mode }
380 #define EMS { OP_EM, v_swap_mode }
381 #define EMd { OP_EM, d_mode }
382 #define EMx { OP_EM, x_mode }
383 #define EXbScalar { OP_EX, b_scalar_mode }
384 #define EXw { OP_EX, w_mode }
385 #define EXwScalar { OP_EX, w_scalar_mode }
386 #define EXd { OP_EX, d_mode }
387 #define EXdScalar { OP_EX, d_scalar_mode }
388 #define EXdS { OP_EX, d_swap_mode }
389 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
390 #define EXq { OP_EX, q_mode }
391 #define EXqScalar { OP_EX, q_scalar_mode }
392 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
393 #define EXqS { OP_EX, q_swap_mode }
394 #define EXx { OP_EX, x_mode }
395 #define EXxS { OP_EX, x_swap_mode }
396 #define EXxmm { OP_EX, xmm_mode }
397 #define EXymm { OP_EX, ymm_mode }
398 #define EXxmmq { OP_EX, xmmq_mode }
399 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
400 #define EXxmm_mb { OP_EX, xmm_mb_mode }
401 #define EXxmm_mw { OP_EX, xmm_mw_mode }
402 #define EXxmm_md { OP_EX, xmm_md_mode }
403 #define EXxmm_mq { OP_EX, xmm_mq_mode }
404 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
405 #define EXxmmdw { OP_EX, xmmdw_mode }
406 #define EXxmmqd { OP_EX, xmmqd_mode }
407 #define EXymmq { OP_EX, ymmq_mode }
408 #define EXVexWdq { OP_EX, vex_w_dq_mode }
409 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
410 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
411 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
412 #define MS { OP_MS, v_mode }
413 #define XS { OP_XS, v_mode }
414 #define EMCq { OP_EMC, q_mode }
415 #define MXC { OP_MXC, 0 }
416 #define OPSUF { OP_3DNowSuffix, 0 }
417 #define CMP { CMP_Fixup, 0 }
418 #define XMM0 { XMM_Fixup, 0 }
419 #define FXSAVE { FXSAVE_Fixup, 0 }
420 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
421 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
423 #define Vex { OP_VEX, vex_mode }
424 #define VexScalar { OP_VEX, vex_scalar_mode }
425 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
426 #define Vex128 { OP_VEX, vex128_mode }
427 #define Vex256 { OP_VEX, vex256_mode }
428 #define VexGdq { OP_VEX, dq_mode }
429 #define EXdVex { OP_EX_Vex, d_mode }
430 #define EXdVexS { OP_EX_Vex, d_swap_mode }
431 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
432 #define EXqVex { OP_EX_Vex, q_mode }
433 #define EXqVexS { OP_EX_Vex, q_swap_mode }
434 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
435 #define EXVexW { OP_EX_VexW, x_mode }
436 #define EXdVexW { OP_EX_VexW, d_mode }
437 #define EXqVexW { OP_EX_VexW, q_mode }
438 #define EXVexImmW { OP_EX_VexImmW, x_mode }
439 #define XMVex { OP_XMM_Vex, 0 }
440 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
441 #define XMVexW { OP_XMM_VexW, 0 }
442 #define XMVexI4 { OP_REG_VexI4, x_mode }
443 #define PCLMUL { PCLMUL_Fixup, 0 }
444 #define VCMP { VCMP_Fixup, 0 }
445 #define VPCMP { VPCMP_Fixup, 0 }
446 #define VPCOM { VPCOM_Fixup, 0 }
448 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
449 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
450 #define EXxEVexS { OP_Rounding, evex_sae_mode }
452 #define XMask { OP_Mask, mask_mode }
453 #define MaskG { OP_G, mask_mode }
454 #define MaskE { OP_E, mask_mode }
455 #define MaskBDE { OP_E, mask_bd_mode }
456 #define MaskR { OP_R, mask_mode }
457 #define MaskVex { OP_VEX, mask_mode }
459 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
460 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
461 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
462 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
464 /* Used handle "rep" prefix for string instructions. */
465 #define Xbr { REP_Fixup, eSI_reg }
466 #define Xvr { REP_Fixup, eSI_reg }
467 #define Ybr { REP_Fixup, eDI_reg }
468 #define Yvr { REP_Fixup, eDI_reg }
469 #define Yzr { REP_Fixup, eDI_reg }
470 #define indirDXr { REP_Fixup, indir_dx_reg }
471 #define ALr { REP_Fixup, al_reg }
472 #define eAXr { REP_Fixup, eAX_reg }
474 /* Used handle HLE prefix for lockable instructions. */
475 #define Ebh1 { HLE_Fixup1, b_mode }
476 #define Evh1 { HLE_Fixup1, v_mode }
477 #define Ebh2 { HLE_Fixup2, b_mode }
478 #define Evh2 { HLE_Fixup2, v_mode }
479 #define Ebh3 { HLE_Fixup3, b_mode }
480 #define Evh3 { HLE_Fixup3, v_mode }
482 #define BND { BND_Fixup, 0 }
483 #define NOTRACK { NOTRACK_Fixup, 0 }
485 #define cond_jump_flag { NULL, cond_jump_mode }
486 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
488 /* bits in sizeflag */
489 #define SUFFIX_ALWAYS 4
497 /* byte operand with operand swapped */
499 /* byte operand, sign extend like 'T' suffix */
501 /* operand size depends on prefixes */
503 /* operand size depends on prefixes with operand swapped */
505 /* operand size depends on address prefix */
509 /* double word operand */
511 /* double word operand with operand swapped */
513 /* quad word operand */
515 /* quad word operand with operand swapped */
517 /* ten-byte operand */
519 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
520 broadcast enabled. */
522 /* Similar to x_mode, but with different EVEX mem shifts. */
524 /* Similar to x_mode, but with disabled broadcast. */
526 /* Similar to x_mode, but with operands swapped and disabled broadcast
529 /* 16-byte XMM operand */
531 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
532 memory operand (depending on vector length). Broadcast isn't
535 /* Same as xmmq_mode, but broadcast is allowed. */
536 evex_half_bcst_xmmq_mode
,
537 /* XMM register or byte memory operand */
539 /* XMM register or word memory operand */
541 /* XMM register or double word memory operand */
543 /* XMM register or quad word memory operand */
545 /* XMM register or double/quad word memory operand, depending on
548 /* 16-byte XMM, word, double word or quad word operand. */
550 /* 16-byte XMM, double word, quad word operand or xmm word operand. */
552 /* 32-byte YMM operand */
554 /* quad word, ymmword or zmmword memory operand. */
556 /* 32-byte YMM or 16-byte word operand */
558 /* d_mode in 32bit, q_mode in 64bit mode. */
560 /* pair of v_mode operands */
565 /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode. */
567 /* operand size depends on REX prefixes. */
569 /* registers like dq_mode, memory like w_mode. */
573 /* bounds operand with operand swapped */
575 /* 4- or 6-byte pointer operand */
578 /* v_mode for indirect branch opcodes. */
580 /* v_mode for stack-related opcodes. */
582 /* non-quad operand size depends on prefixes */
584 /* 16-byte operand */
586 /* registers like dq_mode, memory like b_mode. */
588 /* registers like d_mode, memory like b_mode. */
590 /* registers like d_mode, memory like w_mode. */
592 /* registers like dq_mode, memory like d_mode. */
594 /* operand size depends on the W bit as well as address mode. */
596 /* normal vex mode */
598 /* 128bit vex mode */
600 /* 256bit vex mode */
602 /* operand size depends on the VEX.W bit. */
605 /* Similar to vex_w_dq_mode, with VSIB dword indices. */
606 vex_vsib_d_w_dq_mode
,
607 /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */
609 /* Similar to vex_w_dq_mode, with VSIB qword indices. */
610 vex_vsib_q_w_dq_mode
,
611 /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */
614 /* scalar, ignore vector length. */
616 /* like b_mode, ignore vector length. */
618 /* like w_mode, ignore vector length. */
620 /* like d_mode, ignore vector length. */
622 /* like d_swap_mode, ignore vector length. */
624 /* like q_mode, ignore vector length. */
626 /* like q_swap_mode, ignore vector length. */
628 /* like vex_mode, ignore vector length. */
630 /* like vex_w_dq_mode, ignore vector length. */
631 vex_scalar_w_dq_mode
,
633 /* Static rounding. */
635 /* Static rounding, 64-bit mode only. */
636 evex_rounding_64_mode
,
637 /* Supress all exceptions. */
640 /* Mask register operand. */
642 /* Mask register operand. */
710 #define FLOAT NULL, { { NULL, FLOATCODE } }, 0
712 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0
713 #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P
714 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
715 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
716 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
717 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
718 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
719 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
720 #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
721 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
722 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
723 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
724 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
725 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
726 #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I))
727 #define EVEX_LEN_TABLE(I) DIS386 (USE_EVEX_LEN_TABLE, (I))
855 MOD_VEX_0F12_PREFIX_0
,
857 MOD_VEX_0F16_PREFIX_0
,
860 MOD_VEX_W_0_0F41_P_0_LEN_1
,
861 MOD_VEX_W_1_0F41_P_0_LEN_1
,
862 MOD_VEX_W_0_0F41_P_2_LEN_1
,
863 MOD_VEX_W_1_0F41_P_2_LEN_1
,
864 MOD_VEX_W_0_0F42_P_0_LEN_1
,
865 MOD_VEX_W_1_0F42_P_0_LEN_1
,
866 MOD_VEX_W_0_0F42_P_2_LEN_1
,
867 MOD_VEX_W_1_0F42_P_2_LEN_1
,
868 MOD_VEX_W_0_0F44_P_0_LEN_1
,
869 MOD_VEX_W_1_0F44_P_0_LEN_1
,
870 MOD_VEX_W_0_0F44_P_2_LEN_1
,
871 MOD_VEX_W_1_0F44_P_2_LEN_1
,
872 MOD_VEX_W_0_0F45_P_0_LEN_1
,
873 MOD_VEX_W_1_0F45_P_0_LEN_1
,
874 MOD_VEX_W_0_0F45_P_2_LEN_1
,
875 MOD_VEX_W_1_0F45_P_2_LEN_1
,
876 MOD_VEX_W_0_0F46_P_0_LEN_1
,
877 MOD_VEX_W_1_0F46_P_0_LEN_1
,
878 MOD_VEX_W_0_0F46_P_2_LEN_1
,
879 MOD_VEX_W_1_0F46_P_2_LEN_1
,
880 MOD_VEX_W_0_0F47_P_0_LEN_1
,
881 MOD_VEX_W_1_0F47_P_0_LEN_1
,
882 MOD_VEX_W_0_0F47_P_2_LEN_1
,
883 MOD_VEX_W_1_0F47_P_2_LEN_1
,
884 MOD_VEX_W_0_0F4A_P_0_LEN_1
,
885 MOD_VEX_W_1_0F4A_P_0_LEN_1
,
886 MOD_VEX_W_0_0F4A_P_2_LEN_1
,
887 MOD_VEX_W_1_0F4A_P_2_LEN_1
,
888 MOD_VEX_W_0_0F4B_P_0_LEN_1
,
889 MOD_VEX_W_1_0F4B_P_0_LEN_1
,
890 MOD_VEX_W_0_0F4B_P_2_LEN_1
,
902 MOD_VEX_W_0_0F91_P_0_LEN_0
,
903 MOD_VEX_W_1_0F91_P_0_LEN_0
,
904 MOD_VEX_W_0_0F91_P_2_LEN_0
,
905 MOD_VEX_W_1_0F91_P_2_LEN_0
,
906 MOD_VEX_W_0_0F92_P_0_LEN_0
,
907 MOD_VEX_W_0_0F92_P_2_LEN_0
,
908 MOD_VEX_0F92_P_3_LEN_0
,
909 MOD_VEX_W_0_0F93_P_0_LEN_0
,
910 MOD_VEX_W_0_0F93_P_2_LEN_0
,
911 MOD_VEX_0F93_P_3_LEN_0
,
912 MOD_VEX_W_0_0F98_P_0_LEN_0
,
913 MOD_VEX_W_1_0F98_P_0_LEN_0
,
914 MOD_VEX_W_0_0F98_P_2_LEN_0
,
915 MOD_VEX_W_1_0F98_P_2_LEN_0
,
916 MOD_VEX_W_0_0F99_P_0_LEN_0
,
917 MOD_VEX_W_1_0F99_P_0_LEN_0
,
918 MOD_VEX_W_0_0F99_P_2_LEN_0
,
919 MOD_VEX_W_1_0F99_P_2_LEN_0
,
922 MOD_VEX_0FD7_PREFIX_2
,
923 MOD_VEX_0FE7_PREFIX_2
,
924 MOD_VEX_0FF0_PREFIX_3
,
925 MOD_VEX_0F381A_PREFIX_2
,
926 MOD_VEX_0F382A_PREFIX_2
,
927 MOD_VEX_0F382C_PREFIX_2
,
928 MOD_VEX_0F382D_PREFIX_2
,
929 MOD_VEX_0F382E_PREFIX_2
,
930 MOD_VEX_0F382F_PREFIX_2
,
931 MOD_VEX_0F385A_PREFIX_2
,
932 MOD_VEX_0F388C_PREFIX_2
,
933 MOD_VEX_0F388E_PREFIX_2
,
934 MOD_VEX_W_0_0F3A30_P_2_LEN_0
,
935 MOD_VEX_W_1_0F3A30_P_2_LEN_0
,
936 MOD_VEX_W_0_0F3A31_P_2_LEN_0
,
937 MOD_VEX_W_1_0F3A31_P_2_LEN_0
,
938 MOD_VEX_W_0_0F3A32_P_2_LEN_0
,
939 MOD_VEX_W_1_0F3A32_P_2_LEN_0
,
940 MOD_VEX_W_0_0F3A33_P_2_LEN_0
,
941 MOD_VEX_W_1_0F3A33_P_2_LEN_0
,
943 MOD_EVEX_0F10_PREFIX_1
,
944 MOD_EVEX_0F10_PREFIX_3
,
945 MOD_EVEX_0F11_PREFIX_1
,
946 MOD_EVEX_0F11_PREFIX_3
,
947 MOD_EVEX_0F12_PREFIX_0
,
948 MOD_EVEX_0F16_PREFIX_0
,
949 MOD_EVEX_0F38C6_REG_1
,
950 MOD_EVEX_0F38C6_REG_2
,
951 MOD_EVEX_0F38C6_REG_5
,
952 MOD_EVEX_0F38C6_REG_6
,
953 MOD_EVEX_0F38C7_REG_1
,
954 MOD_EVEX_0F38C7_REG_2
,
955 MOD_EVEX_0F38C7_REG_5
,
956 MOD_EVEX_0F38C7_REG_6
977 PREFIX_MOD_0_0F01_REG_5
,
978 PREFIX_MOD_3_0F01_REG_5_RM_0
,
979 PREFIX_MOD_3_0F01_REG_5_RM_2
,
1025 PREFIX_MOD_0_0FAE_REG_4
,
1026 PREFIX_MOD_3_0FAE_REG_4
,
1027 PREFIX_MOD_0_0FAE_REG_5
,
1028 PREFIX_MOD_3_0FAE_REG_5
,
1029 PREFIX_MOD_0_0FAE_REG_6
,
1030 PREFIX_MOD_1_0FAE_REG_6
,
1037 PREFIX_MOD_0_0FC7_REG_6
,
1038 PREFIX_MOD_3_0FC7_REG_6
,
1039 PREFIX_MOD_3_0FC7_REG_7
,
1169 PREFIX_VEX_0F71_REG_2
,
1170 PREFIX_VEX_0F71_REG_4
,
1171 PREFIX_VEX_0F71_REG_6
,
1172 PREFIX_VEX_0F72_REG_2
,
1173 PREFIX_VEX_0F72_REG_4
,
1174 PREFIX_VEX_0F72_REG_6
,
1175 PREFIX_VEX_0F73_REG_2
,
1176 PREFIX_VEX_0F73_REG_3
,
1177 PREFIX_VEX_0F73_REG_6
,
1178 PREFIX_VEX_0F73_REG_7
,
1351 PREFIX_VEX_0F38F3_REG_1
,
1352 PREFIX_VEX_0F38F3_REG_2
,
1353 PREFIX_VEX_0F38F3_REG_3
,
1472 PREFIX_EVEX_0F71_REG_2
,
1473 PREFIX_EVEX_0F71_REG_4
,
1474 PREFIX_EVEX_0F71_REG_6
,
1475 PREFIX_EVEX_0F72_REG_0
,
1476 PREFIX_EVEX_0F72_REG_1
,
1477 PREFIX_EVEX_0F72_REG_2
,
1478 PREFIX_EVEX_0F72_REG_4
,
1479 PREFIX_EVEX_0F72_REG_6
,
1480 PREFIX_EVEX_0F73_REG_2
,
1481 PREFIX_EVEX_0F73_REG_3
,
1482 PREFIX_EVEX_0F73_REG_6
,
1483 PREFIX_EVEX_0F73_REG_7
,
1680 PREFIX_EVEX_0F38C6_REG_1
,
1681 PREFIX_EVEX_0F38C6_REG_2
,
1682 PREFIX_EVEX_0F38C6_REG_5
,
1683 PREFIX_EVEX_0F38C6_REG_6
,
1684 PREFIX_EVEX_0F38C7_REG_1
,
1685 PREFIX_EVEX_0F38C7_REG_2
,
1686 PREFIX_EVEX_0F38C7_REG_5
,
1687 PREFIX_EVEX_0F38C7_REG_6
,
1789 THREE_BYTE_0F38
= 0,
1816 VEX_LEN_0F12_P_0_M_0
= 0,
1817 VEX_LEN_0F12_P_0_M_1
,
1820 VEX_LEN_0F16_P_0_M_0
,
1821 VEX_LEN_0F16_P_0_M_1
,
1864 VEX_LEN_0FAE_R_2_M_0
,
1865 VEX_LEN_0FAE_R_3_M_0
,
1872 VEX_LEN_0F381A_P_2_M_0
,
1875 VEX_LEN_0F385A_P_2_M_0
,
1878 VEX_LEN_0F38F3_R_1_P_0
,
1879 VEX_LEN_0F38F3_R_2_P_0
,
1880 VEX_LEN_0F38F3_R_3_P_0
,
1923 VEX_LEN_0FXOP_08_CC
,
1924 VEX_LEN_0FXOP_08_CD
,
1925 VEX_LEN_0FXOP_08_CE
,
1926 VEX_LEN_0FXOP_08_CF
,
1927 VEX_LEN_0FXOP_08_EC
,
1928 VEX_LEN_0FXOP_08_ED
,
1929 VEX_LEN_0FXOP_08_EE
,
1930 VEX_LEN_0FXOP_08_EF
,
1931 VEX_LEN_0FXOP_09_80
,
1937 EVEX_LEN_0F6E_P_2
= 0,
1941 EVEX_LEN_0F3A18_P_2_W_0
,
1942 EVEX_LEN_0F3A18_P_2_W_1
,
1943 EVEX_LEN_0F3A19_P_2_W_0
,
1944 EVEX_LEN_0F3A19_P_2_W_1
,
1945 EVEX_LEN_0F3A1A_P_2_W_0
,
1946 EVEX_LEN_0F3A1A_P_2_W_1
,
1947 EVEX_LEN_0F3A1B_P_2_W_0
,
1948 EVEX_LEN_0F3A1B_P_2_W_1
1953 VEX_W_0F41_P_0_LEN_1
= 0,
1954 VEX_W_0F41_P_2_LEN_1
,
1955 VEX_W_0F42_P_0_LEN_1
,
1956 VEX_W_0F42_P_2_LEN_1
,
1957 VEX_W_0F44_P_0_LEN_0
,
1958 VEX_W_0F44_P_2_LEN_0
,
1959 VEX_W_0F45_P_0_LEN_1
,
1960 VEX_W_0F45_P_2_LEN_1
,
1961 VEX_W_0F46_P_0_LEN_1
,
1962 VEX_W_0F46_P_2_LEN_1
,
1963 VEX_W_0F47_P_0_LEN_1
,
1964 VEX_W_0F47_P_2_LEN_1
,
1965 VEX_W_0F4A_P_0_LEN_1
,
1966 VEX_W_0F4A_P_2_LEN_1
,
1967 VEX_W_0F4B_P_0_LEN_1
,
1968 VEX_W_0F4B_P_2_LEN_1
,
1969 VEX_W_0F90_P_0_LEN_0
,
1970 VEX_W_0F90_P_2_LEN_0
,
1971 VEX_W_0F91_P_0_LEN_0
,
1972 VEX_W_0F91_P_2_LEN_0
,
1973 VEX_W_0F92_P_0_LEN_0
,
1974 VEX_W_0F92_P_2_LEN_0
,
1975 VEX_W_0F93_P_0_LEN_0
,
1976 VEX_W_0F93_P_2_LEN_0
,
1977 VEX_W_0F98_P_0_LEN_0
,
1978 VEX_W_0F98_P_2_LEN_0
,
1979 VEX_W_0F99_P_0_LEN_0
,
1980 VEX_W_0F99_P_2_LEN_0
,
1988 VEX_W_0F381A_P_2_M_0
,
1989 VEX_W_0F382C_P_2_M_0
,
1990 VEX_W_0F382D_P_2_M_0
,
1991 VEX_W_0F382E_P_2_M_0
,
1992 VEX_W_0F382F_P_2_M_0
,
1997 VEX_W_0F385A_P_2_M_0
,
2009 VEX_W_0F3A30_P_2_LEN_0
,
2010 VEX_W_0F3A31_P_2_LEN_0
,
2011 VEX_W_0F3A32_P_2_LEN_0
,
2012 VEX_W_0F3A33_P_2_LEN_0
,
2025 EVEX_W_0F10_P_1_M_0
,
2026 EVEX_W_0F10_P_1_M_1
,
2028 EVEX_W_0F10_P_3_M_0
,
2029 EVEX_W_0F10_P_3_M_1
,
2031 EVEX_W_0F11_P_1_M_0
,
2032 EVEX_W_0F11_P_1_M_1
,
2034 EVEX_W_0F11_P_3_M_0
,
2035 EVEX_W_0F11_P_3_M_1
,
2036 EVEX_W_0F12_P_0_M_0
,
2037 EVEX_W_0F12_P_0_M_1
,
2047 EVEX_W_0F16_P_0_M_0
,
2048 EVEX_W_0F16_P_0_M_1
,
2118 EVEX_W_0F72_R_2_P_2
,
2119 EVEX_W_0F72_R_6_P_2
,
2120 EVEX_W_0F73_R_2_P_2
,
2121 EVEX_W_0F73_R_6_P_2
,
2232 EVEX_W_0F38C7_R_1_P_2
,
2233 EVEX_W_0F38C7_R_2_P_2
,
2234 EVEX_W_0F38C7_R_5_P_2
,
2235 EVEX_W_0F38C7_R_6_P_2
,
2274 typedef void (*op_rtn
) (int bytemode
, int sizeflag
);
2283 unsigned int prefix_requirement
;
2286 /* Upper case letters in the instruction names here are macros.
2287 'A' => print 'b' if no register operands or suffix_always is true
2288 'B' => print 'b' if suffix_always is true
2289 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2291 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2292 suffix_always is true
2293 'E' => print 'e' if 32-bit form of jcxz
2294 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2295 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2296 'H' => print ",pt" or ",pn" branch hint
2297 'I' => honor following macro letter even in Intel mode (implemented only
2298 for some of the macro letters)
2300 'K' => print 'd' or 'q' if rex prefix is present.
2301 'L' => print 'l' if suffix_always is true
2302 'M' => print 'r' if intel_mnemonic is false.
2303 'N' => print 'n' if instruction has no wait "prefix"
2304 'O' => print 'd' or 'o' (or 'q' in Intel mode)
2305 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2306 or suffix_always is true. print 'q' if rex prefix is present.
2307 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2309 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2310 'S' => print 'w', 'l' or 'q' if suffix_always is true
2311 'T' => print 'q' in 64bit mode if instruction has no operand size
2312 prefix and behave as 'P' otherwise
2313 'U' => print 'q' in 64bit mode if instruction has no operand size
2314 prefix and behave as 'Q' otherwise
2315 'V' => print 'q' in 64bit mode if instruction has no operand size
2316 prefix and behave as 'S' otherwise
2317 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2318 'X' => print 's', 'd' depending on data16 prefix (for XMM)
2320 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2321 '!' => change condition from true to false or from false to true.
2322 '%' => add 1 upper case letter to the macro.
2323 '^' => print 'w' or 'l' depending on operand size prefix or
2324 suffix_always is true (lcall/ljmp).
2325 '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2326 on operand size prefix.
2327 '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2328 has no operand size prefix for AMD64 ISA, behave as 'P'
2331 2 upper case letter macros:
2332 "XY" => print 'x' or 'y' if suffix_always is true or no register
2333 operands and no broadcast.
2334 "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2335 register operands and no broadcast.
2336 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2337 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2338 or suffix_always is true
2339 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2340 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2341 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2342 "LW" => print 'd', 'q' depending on the VEX.W bit
2343 "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2344 an operand size prefix, or suffix_always is true. print
2345 'q' if rex prefix is present.
2347 Many of the above letters print nothing in Intel mode. See "putop"
2350 Braces '{' and '}', and vertical bars '|', indicate alternative
2351 mnemonic strings for AT&T and Intel. */
2353 static const struct dis386 dis386
[] = {
2355 { "addB", { Ebh1
, Gb
}, 0 },
2356 { "addS", { Evh1
, Gv
}, 0 },
2357 { "addB", { Gb
, EbS
}, 0 },
2358 { "addS", { Gv
, EvS
}, 0 },
2359 { "addB", { AL
, Ib
}, 0 },
2360 { "addS", { eAX
, Iv
}, 0 },
2361 { X86_64_TABLE (X86_64_06
) },
2362 { X86_64_TABLE (X86_64_07
) },
2364 { "orB", { Ebh1
, Gb
}, 0 },
2365 { "orS", { Evh1
, Gv
}, 0 },
2366 { "orB", { Gb
, EbS
}, 0 },
2367 { "orS", { Gv
, EvS
}, 0 },
2368 { "orB", { AL
, Ib
}, 0 },
2369 { "orS", { eAX
, Iv
}, 0 },
2370 { X86_64_TABLE (X86_64_0D
) },
2371 { Bad_Opcode
}, /* 0x0f extended opcode escape */
2373 { "adcB", { Ebh1
, Gb
}, 0 },
2374 { "adcS", { Evh1
, Gv
}, 0 },
2375 { "adcB", { Gb
, EbS
}, 0 },
2376 { "adcS", { Gv
, EvS
}, 0 },
2377 { "adcB", { AL
, Ib
}, 0 },
2378 { "adcS", { eAX
, Iv
}, 0 },
2379 { X86_64_TABLE (X86_64_16
) },
2380 { X86_64_TABLE (X86_64_17
) },
2382 { "sbbB", { Ebh1
, Gb
}, 0 },
2383 { "sbbS", { Evh1
, Gv
}, 0 },
2384 { "sbbB", { Gb
, EbS
}, 0 },
2385 { "sbbS", { Gv
, EvS
}, 0 },
2386 { "sbbB", { AL
, Ib
}, 0 },
2387 { "sbbS", { eAX
, Iv
}, 0 },
2388 { X86_64_TABLE (X86_64_1E
) },
2389 { X86_64_TABLE (X86_64_1F
) },
2391 { "andB", { Ebh1
, Gb
}, 0 },
2392 { "andS", { Evh1
, Gv
}, 0 },
2393 { "andB", { Gb
, EbS
}, 0 },
2394 { "andS", { Gv
, EvS
}, 0 },
2395 { "andB", { AL
, Ib
}, 0 },
2396 { "andS", { eAX
, Iv
}, 0 },
2397 { Bad_Opcode
}, /* SEG ES prefix */
2398 { X86_64_TABLE (X86_64_27
) },
2400 { "subB", { Ebh1
, Gb
}, 0 },
2401 { "subS", { Evh1
, Gv
}, 0 },
2402 { "subB", { Gb
, EbS
}, 0 },
2403 { "subS", { Gv
, EvS
}, 0 },
2404 { "subB", { AL
, Ib
}, 0 },
2405 { "subS", { eAX
, Iv
}, 0 },
2406 { Bad_Opcode
}, /* SEG CS prefix */
2407 { X86_64_TABLE (X86_64_2F
) },
2409 { "xorB", { Ebh1
, Gb
}, 0 },
2410 { "xorS", { Evh1
, Gv
}, 0 },
2411 { "xorB", { Gb
, EbS
}, 0 },
2412 { "xorS", { Gv
, EvS
}, 0 },
2413 { "xorB", { AL
, Ib
}, 0 },
2414 { "xorS", { eAX
, Iv
}, 0 },
2415 { Bad_Opcode
}, /* SEG SS prefix */
2416 { X86_64_TABLE (X86_64_37
) },
2418 { "cmpB", { Eb
, Gb
}, 0 },
2419 { "cmpS", { Ev
, Gv
}, 0 },
2420 { "cmpB", { Gb
, EbS
}, 0 },
2421 { "cmpS", { Gv
, EvS
}, 0 },
2422 { "cmpB", { AL
, Ib
}, 0 },
2423 { "cmpS", { eAX
, Iv
}, 0 },
2424 { Bad_Opcode
}, /* SEG DS prefix */
2425 { X86_64_TABLE (X86_64_3F
) },
2427 { "inc{S|}", { RMeAX
}, 0 },
2428 { "inc{S|}", { RMeCX
}, 0 },
2429 { "inc{S|}", { RMeDX
}, 0 },
2430 { "inc{S|}", { RMeBX
}, 0 },
2431 { "inc{S|}", { RMeSP
}, 0 },
2432 { "inc{S|}", { RMeBP
}, 0 },
2433 { "inc{S|}", { RMeSI
}, 0 },
2434 { "inc{S|}", { RMeDI
}, 0 },
2436 { "dec{S|}", { RMeAX
}, 0 },
2437 { "dec{S|}", { RMeCX
}, 0 },
2438 { "dec{S|}", { RMeDX
}, 0 },
2439 { "dec{S|}", { RMeBX
}, 0 },
2440 { "dec{S|}", { RMeSP
}, 0 },
2441 { "dec{S|}", { RMeBP
}, 0 },
2442 { "dec{S|}", { RMeSI
}, 0 },
2443 { "dec{S|}", { RMeDI
}, 0 },
2445 { "pushV", { RMrAX
}, 0 },
2446 { "pushV", { RMrCX
}, 0 },
2447 { "pushV", { RMrDX
}, 0 },
2448 { "pushV", { RMrBX
}, 0 },
2449 { "pushV", { RMrSP
}, 0 },
2450 { "pushV", { RMrBP
}, 0 },
2451 { "pushV", { RMrSI
}, 0 },
2452 { "pushV", { RMrDI
}, 0 },
2454 { "popV", { RMrAX
}, 0 },
2455 { "popV", { RMrCX
}, 0 },
2456 { "popV", { RMrDX
}, 0 },
2457 { "popV", { RMrBX
}, 0 },
2458 { "popV", { RMrSP
}, 0 },
2459 { "popV", { RMrBP
}, 0 },
2460 { "popV", { RMrSI
}, 0 },
2461 { "popV", { RMrDI
}, 0 },
2463 { X86_64_TABLE (X86_64_60
) },
2464 { X86_64_TABLE (X86_64_61
) },
2465 { X86_64_TABLE (X86_64_62
) },
2466 { X86_64_TABLE (X86_64_63
) },
2467 { Bad_Opcode
}, /* seg fs */
2468 { Bad_Opcode
}, /* seg gs */
2469 { Bad_Opcode
}, /* op size prefix */
2470 { Bad_Opcode
}, /* adr size prefix */
2472 { "pushT", { sIv
}, 0 },
2473 { "imulS", { Gv
, Ev
, Iv
}, 0 },
2474 { "pushT", { sIbT
}, 0 },
2475 { "imulS", { Gv
, Ev
, sIb
}, 0 },
2476 { "ins{b|}", { Ybr
, indirDX
}, 0 },
2477 { X86_64_TABLE (X86_64_6D
) },
2478 { "outs{b|}", { indirDXr
, Xb
}, 0 },
2479 { X86_64_TABLE (X86_64_6F
) },
2481 { "joH", { Jb
, BND
, cond_jump_flag
}, 0 },
2482 { "jnoH", { Jb
, BND
, cond_jump_flag
}, 0 },
2483 { "jbH", { Jb
, BND
, cond_jump_flag
}, 0 },
2484 { "jaeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2485 { "jeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2486 { "jneH", { Jb
, BND
, cond_jump_flag
}, 0 },
2487 { "jbeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2488 { "jaH", { Jb
, BND
, cond_jump_flag
}, 0 },
2490 { "jsH", { Jb
, BND
, cond_jump_flag
}, 0 },
2491 { "jnsH", { Jb
, BND
, cond_jump_flag
}, 0 },
2492 { "jpH", { Jb
, BND
, cond_jump_flag
}, 0 },
2493 { "jnpH", { Jb
, BND
, cond_jump_flag
}, 0 },
2494 { "jlH", { Jb
, BND
, cond_jump_flag
}, 0 },
2495 { "jgeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2496 { "jleH", { Jb
, BND
, cond_jump_flag
}, 0 },
2497 { "jgH", { Jb
, BND
, cond_jump_flag
}, 0 },
2499 { REG_TABLE (REG_80
) },
2500 { REG_TABLE (REG_81
) },
2501 { X86_64_TABLE (X86_64_82
) },
2502 { REG_TABLE (REG_83
) },
2503 { "testB", { Eb
, Gb
}, 0 },
2504 { "testS", { Ev
, Gv
}, 0 },
2505 { "xchgB", { Ebh2
, Gb
}, 0 },
2506 { "xchgS", { Evh2
, Gv
}, 0 },
2508 { "movB", { Ebh3
, Gb
}, 0 },
2509 { "movS", { Evh3
, Gv
}, 0 },
2510 { "movB", { Gb
, EbS
}, 0 },
2511 { "movS", { Gv
, EvS
}, 0 },
2512 { "movD", { Sv
, Sw
}, 0 },
2513 { MOD_TABLE (MOD_8D
) },
2514 { "movD", { Sw
, Sv
}, 0 },
2515 { REG_TABLE (REG_8F
) },
2517 { PREFIX_TABLE (PREFIX_90
) },
2518 { "xchgS", { RMeCX
, eAX
}, 0 },
2519 { "xchgS", { RMeDX
, eAX
}, 0 },
2520 { "xchgS", { RMeBX
, eAX
}, 0 },
2521 { "xchgS", { RMeSP
, eAX
}, 0 },
2522 { "xchgS", { RMeBP
, eAX
}, 0 },
2523 { "xchgS", { RMeSI
, eAX
}, 0 },
2524 { "xchgS", { RMeDI
, eAX
}, 0 },
2526 { "cW{t|}R", { XX
}, 0 },
2527 { "cR{t|}O", { XX
}, 0 },
2528 { X86_64_TABLE (X86_64_9A
) },
2529 { Bad_Opcode
}, /* fwait */
2530 { "pushfT", { XX
}, 0 },
2531 { "popfT", { XX
}, 0 },
2532 { "sahf", { XX
}, 0 },
2533 { "lahf", { XX
}, 0 },
2535 { "mov%LB", { AL
, Ob
}, 0 },
2536 { "mov%LS", { eAX
, Ov
}, 0 },
2537 { "mov%LB", { Ob
, AL
}, 0 },
2538 { "mov%LS", { Ov
, eAX
}, 0 },
2539 { "movs{b|}", { Ybr
, Xb
}, 0 },
2540 { "movs{R|}", { Yvr
, Xv
}, 0 },
2541 { "cmps{b|}", { Xb
, Yb
}, 0 },
2542 { "cmps{R|}", { Xv
, Yv
}, 0 },
2544 { "testB", { AL
, Ib
}, 0 },
2545 { "testS", { eAX
, Iv
}, 0 },
2546 { "stosB", { Ybr
, AL
}, 0 },
2547 { "stosS", { Yvr
, eAX
}, 0 },
2548 { "lodsB", { ALr
, Xb
}, 0 },
2549 { "lodsS", { eAXr
, Xv
}, 0 },
2550 { "scasB", { AL
, Yb
}, 0 },
2551 { "scasS", { eAX
, Yv
}, 0 },
2553 { "movB", { RMAL
, Ib
}, 0 },
2554 { "movB", { RMCL
, Ib
}, 0 },
2555 { "movB", { RMDL
, Ib
}, 0 },
2556 { "movB", { RMBL
, Ib
}, 0 },
2557 { "movB", { RMAH
, Ib
}, 0 },
2558 { "movB", { RMCH
, Ib
}, 0 },
2559 { "movB", { RMDH
, Ib
}, 0 },
2560 { "movB", { RMBH
, Ib
}, 0 },
2562 { "mov%LV", { RMeAX
, Iv64
}, 0 },
2563 { "mov%LV", { RMeCX
, Iv64
}, 0 },
2564 { "mov%LV", { RMeDX
, Iv64
}, 0 },
2565 { "mov%LV", { RMeBX
, Iv64
}, 0 },
2566 { "mov%LV", { RMeSP
, Iv64
}, 0 },
2567 { "mov%LV", { RMeBP
, Iv64
}, 0 },
2568 { "mov%LV", { RMeSI
, Iv64
}, 0 },
2569 { "mov%LV", { RMeDI
, Iv64
}, 0 },
2571 { REG_TABLE (REG_C0
) },
2572 { REG_TABLE (REG_C1
) },
2573 { "retT", { Iw
, BND
}, 0 },
2574 { "retT", { BND
}, 0 },
2575 { X86_64_TABLE (X86_64_C4
) },
2576 { X86_64_TABLE (X86_64_C5
) },
2577 { REG_TABLE (REG_C6
) },
2578 { REG_TABLE (REG_C7
) },
2580 { "enterT", { Iw
, Ib
}, 0 },
2581 { "leaveT", { XX
}, 0 },
2582 { "Jret{|f}P", { Iw
}, 0 },
2583 { "Jret{|f}P", { XX
}, 0 },
2584 { "int3", { XX
}, 0 },
2585 { "int", { Ib
}, 0 },
2586 { X86_64_TABLE (X86_64_CE
) },
2587 { "iret%LP", { XX
}, 0 },
2589 { REG_TABLE (REG_D0
) },
2590 { REG_TABLE (REG_D1
) },
2591 { REG_TABLE (REG_D2
) },
2592 { REG_TABLE (REG_D3
) },
2593 { X86_64_TABLE (X86_64_D4
) },
2594 { X86_64_TABLE (X86_64_D5
) },
2596 { "xlat", { DSBX
}, 0 },
2607 { "loopneFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2608 { "loopeFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2609 { "loopFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2610 { "jEcxzH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2611 { "inB", { AL
, Ib
}, 0 },
2612 { "inG", { zAX
, Ib
}, 0 },
2613 { "outB", { Ib
, AL
}, 0 },
2614 { "outG", { Ib
, zAX
}, 0 },
2616 { X86_64_TABLE (X86_64_E8
) },
2617 { X86_64_TABLE (X86_64_E9
) },
2618 { X86_64_TABLE (X86_64_EA
) },
2619 { "jmp", { Jb
, BND
}, 0 },
2620 { "inB", { AL
, indirDX
}, 0 },
2621 { "inG", { zAX
, indirDX
}, 0 },
2622 { "outB", { indirDX
, AL
}, 0 },
2623 { "outG", { indirDX
, zAX
}, 0 },
2625 { Bad_Opcode
}, /* lock prefix */
2626 { "icebp", { XX
}, 0 },
2627 { Bad_Opcode
}, /* repne */
2628 { Bad_Opcode
}, /* repz */
2629 { "hlt", { XX
}, 0 },
2630 { "cmc", { XX
}, 0 },
2631 { REG_TABLE (REG_F6
) },
2632 { REG_TABLE (REG_F7
) },
2634 { "clc", { XX
}, 0 },
2635 { "stc", { XX
}, 0 },
2636 { "cli", { XX
}, 0 },
2637 { "sti", { XX
}, 0 },
2638 { "cld", { XX
}, 0 },
2639 { "std", { XX
}, 0 },
2640 { REG_TABLE (REG_FE
) },
2641 { REG_TABLE (REG_FF
) },
2644 static const struct dis386 dis386_twobyte
[] = {
2646 { REG_TABLE (REG_0F00
) },
2647 { REG_TABLE (REG_0F01
) },
2648 { "larS", { Gv
, Ew
}, 0 },
2649 { "lslS", { Gv
, Ew
}, 0 },
2651 { "syscall", { XX
}, 0 },
2652 { "clts", { XX
}, 0 },
2653 { "sysret%LP", { XX
}, 0 },
2655 { "invd", { XX
}, 0 },
2656 { PREFIX_TABLE (PREFIX_0F09
) },
2658 { "ud2", { XX
}, 0 },
2660 { REG_TABLE (REG_0F0D
) },
2661 { "femms", { XX
}, 0 },
2662 { "", { MX
, EM
, OPSUF
}, 0 }, /* See OP_3DNowSuffix. */
2664 { PREFIX_TABLE (PREFIX_0F10
) },
2665 { PREFIX_TABLE (PREFIX_0F11
) },
2666 { PREFIX_TABLE (PREFIX_0F12
) },
2667 { MOD_TABLE (MOD_0F13
) },
2668 { "unpcklpX", { XM
, EXx
}, PREFIX_OPCODE
},
2669 { "unpckhpX", { XM
, EXx
}, PREFIX_OPCODE
},
2670 { PREFIX_TABLE (PREFIX_0F16
) },
2671 { MOD_TABLE (MOD_0F17
) },
2673 { REG_TABLE (REG_0F18
) },
2674 { "nopQ", { Ev
}, 0 },
2675 { PREFIX_TABLE (PREFIX_0F1A
) },
2676 { PREFIX_TABLE (PREFIX_0F1B
) },
2677 { PREFIX_TABLE (PREFIX_0F1C
) },
2678 { "nopQ", { Ev
}, 0 },
2679 { PREFIX_TABLE (PREFIX_0F1E
) },
2680 { "nopQ", { Ev
}, 0 },
2682 { "movZ", { Rm
, Cm
}, 0 },
2683 { "movZ", { Rm
, Dm
}, 0 },
2684 { "movZ", { Cm
, Rm
}, 0 },
2685 { "movZ", { Dm
, Rm
}, 0 },
2686 { MOD_TABLE (MOD_0F24
) },
2688 { MOD_TABLE (MOD_0F26
) },
2691 { "movapX", { XM
, EXx
}, PREFIX_OPCODE
},
2692 { "movapX", { EXxS
, XM
}, PREFIX_OPCODE
},
2693 { PREFIX_TABLE (PREFIX_0F2A
) },
2694 { PREFIX_TABLE (PREFIX_0F2B
) },
2695 { PREFIX_TABLE (PREFIX_0F2C
) },
2696 { PREFIX_TABLE (PREFIX_0F2D
) },
2697 { PREFIX_TABLE (PREFIX_0F2E
) },
2698 { PREFIX_TABLE (PREFIX_0F2F
) },
2700 { "wrmsr", { XX
}, 0 },
2701 { "rdtsc", { XX
}, 0 },
2702 { "rdmsr", { XX
}, 0 },
2703 { "rdpmc", { XX
}, 0 },
2704 { "sysenter", { XX
}, 0 },
2705 { "sysexit", { XX
}, 0 },
2707 { "getsec", { XX
}, 0 },
2709 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38
, PREFIX_OPCODE
) },
2711 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A
, PREFIX_OPCODE
) },
2718 { "cmovoS", { Gv
, Ev
}, 0 },
2719 { "cmovnoS", { Gv
, Ev
}, 0 },
2720 { "cmovbS", { Gv
, Ev
}, 0 },
2721 { "cmovaeS", { Gv
, Ev
}, 0 },
2722 { "cmoveS", { Gv
, Ev
}, 0 },
2723 { "cmovneS", { Gv
, Ev
}, 0 },
2724 { "cmovbeS", { Gv
, Ev
}, 0 },
2725 { "cmovaS", { Gv
, Ev
}, 0 },
2727 { "cmovsS", { Gv
, Ev
}, 0 },
2728 { "cmovnsS", { Gv
, Ev
}, 0 },
2729 { "cmovpS", { Gv
, Ev
}, 0 },
2730 { "cmovnpS", { Gv
, Ev
}, 0 },
2731 { "cmovlS", { Gv
, Ev
}, 0 },
2732 { "cmovgeS", { Gv
, Ev
}, 0 },
2733 { "cmovleS", { Gv
, Ev
}, 0 },
2734 { "cmovgS", { Gv
, Ev
}, 0 },
2736 { MOD_TABLE (MOD_0F51
) },
2737 { PREFIX_TABLE (PREFIX_0F51
) },
2738 { PREFIX_TABLE (PREFIX_0F52
) },
2739 { PREFIX_TABLE (PREFIX_0F53
) },
2740 { "andpX", { XM
, EXx
}, PREFIX_OPCODE
},
2741 { "andnpX", { XM
, EXx
}, PREFIX_OPCODE
},
2742 { "orpX", { XM
, EXx
}, PREFIX_OPCODE
},
2743 { "xorpX", { XM
, EXx
}, PREFIX_OPCODE
},
2745 { PREFIX_TABLE (PREFIX_0F58
) },
2746 { PREFIX_TABLE (PREFIX_0F59
) },
2747 { PREFIX_TABLE (PREFIX_0F5A
) },
2748 { PREFIX_TABLE (PREFIX_0F5B
) },
2749 { PREFIX_TABLE (PREFIX_0F5C
) },
2750 { PREFIX_TABLE (PREFIX_0F5D
) },
2751 { PREFIX_TABLE (PREFIX_0F5E
) },
2752 { PREFIX_TABLE (PREFIX_0F5F
) },
2754 { PREFIX_TABLE (PREFIX_0F60
) },
2755 { PREFIX_TABLE (PREFIX_0F61
) },
2756 { PREFIX_TABLE (PREFIX_0F62
) },
2757 { "packsswb", { MX
, EM
}, PREFIX_OPCODE
},
2758 { "pcmpgtb", { MX
, EM
}, PREFIX_OPCODE
},
2759 { "pcmpgtw", { MX
, EM
}, PREFIX_OPCODE
},
2760 { "pcmpgtd", { MX
, EM
}, PREFIX_OPCODE
},
2761 { "packuswb", { MX
, EM
}, PREFIX_OPCODE
},
2763 { "punpckhbw", { MX
, EM
}, PREFIX_OPCODE
},
2764 { "punpckhwd", { MX
, EM
}, PREFIX_OPCODE
},
2765 { "punpckhdq", { MX
, EM
}, PREFIX_OPCODE
},
2766 { "packssdw", { MX
, EM
}, PREFIX_OPCODE
},
2767 { PREFIX_TABLE (PREFIX_0F6C
) },
2768 { PREFIX_TABLE (PREFIX_0F6D
) },
2769 { "movK", { MX
, Edq
}, PREFIX_OPCODE
},
2770 { PREFIX_TABLE (PREFIX_0F6F
) },
2772 { PREFIX_TABLE (PREFIX_0F70
) },
2773 { REG_TABLE (REG_0F71
) },
2774 { REG_TABLE (REG_0F72
) },
2775 { REG_TABLE (REG_0F73
) },
2776 { "pcmpeqb", { MX
, EM
}, PREFIX_OPCODE
},
2777 { "pcmpeqw", { MX
, EM
}, PREFIX_OPCODE
},
2778 { "pcmpeqd", { MX
, EM
}, PREFIX_OPCODE
},
2779 { "emms", { XX
}, PREFIX_OPCODE
},
2781 { PREFIX_TABLE (PREFIX_0F78
) },
2782 { PREFIX_TABLE (PREFIX_0F79
) },
2785 { PREFIX_TABLE (PREFIX_0F7C
) },
2786 { PREFIX_TABLE (PREFIX_0F7D
) },
2787 { PREFIX_TABLE (PREFIX_0F7E
) },
2788 { PREFIX_TABLE (PREFIX_0F7F
) },
2790 { "joH", { Jv
, BND
, cond_jump_flag
}, 0 },
2791 { "jnoH", { Jv
, BND
, cond_jump_flag
}, 0 },
2792 { "jbH", { Jv
, BND
, cond_jump_flag
}, 0 },
2793 { "jaeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2794 { "jeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2795 { "jneH", { Jv
, BND
, cond_jump_flag
}, 0 },
2796 { "jbeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2797 { "jaH", { Jv
, BND
, cond_jump_flag
}, 0 },
2799 { "jsH", { Jv
, BND
, cond_jump_flag
}, 0 },
2800 { "jnsH", { Jv
, BND
, cond_jump_flag
}, 0 },
2801 { "jpH", { Jv
, BND
, cond_jump_flag
}, 0 },
2802 { "jnpH", { Jv
, BND
, cond_jump_flag
}, 0 },
2803 { "jlH", { Jv
, BND
, cond_jump_flag
}, 0 },
2804 { "jgeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2805 { "jleH", { Jv
, BND
, cond_jump_flag
}, 0 },
2806 { "jgH", { Jv
, BND
, cond_jump_flag
}, 0 },
2808 { "seto", { Eb
}, 0 },
2809 { "setno", { Eb
}, 0 },
2810 { "setb", { Eb
}, 0 },
2811 { "setae", { Eb
}, 0 },
2812 { "sete", { Eb
}, 0 },
2813 { "setne", { Eb
}, 0 },
2814 { "setbe", { Eb
}, 0 },
2815 { "seta", { Eb
}, 0 },
2817 { "sets", { Eb
}, 0 },
2818 { "setns", { Eb
}, 0 },
2819 { "setp", { Eb
}, 0 },
2820 { "setnp", { Eb
}, 0 },
2821 { "setl", { Eb
}, 0 },
2822 { "setge", { Eb
}, 0 },
2823 { "setle", { Eb
}, 0 },
2824 { "setg", { Eb
}, 0 },
2826 { "pushT", { fs
}, 0 },
2827 { "popT", { fs
}, 0 },
2828 { "cpuid", { XX
}, 0 },
2829 { "btS", { Ev
, Gv
}, 0 },
2830 { "shldS", { Ev
, Gv
, Ib
}, 0 },
2831 { "shldS", { Ev
, Gv
, CL
}, 0 },
2832 { REG_TABLE (REG_0FA6
) },
2833 { REG_TABLE (REG_0FA7
) },
2835 { "pushT", { gs
}, 0 },
2836 { "popT", { gs
}, 0 },
2837 { "rsm", { XX
}, 0 },
2838 { "btsS", { Evh1
, Gv
}, 0 },
2839 { "shrdS", { Ev
, Gv
, Ib
}, 0 },
2840 { "shrdS", { Ev
, Gv
, CL
}, 0 },
2841 { REG_TABLE (REG_0FAE
) },
2842 { "imulS", { Gv
, Ev
}, 0 },
2844 { "cmpxchgB", { Ebh1
, Gb
}, 0 },
2845 { "cmpxchgS", { Evh1
, Gv
}, 0 },
2846 { MOD_TABLE (MOD_0FB2
) },
2847 { "btrS", { Evh1
, Gv
}, 0 },
2848 { MOD_TABLE (MOD_0FB4
) },
2849 { MOD_TABLE (MOD_0FB5
) },
2850 { "movz{bR|x}", { Gv
, Eb
}, 0 },
2851 { "movz{wR|x}", { Gv
, Ew
}, 0 }, /* yes, there really is movzww ! */
2853 { PREFIX_TABLE (PREFIX_0FB8
) },
2854 { "ud1S", { Gv
, Ev
}, 0 },
2855 { REG_TABLE (REG_0FBA
) },
2856 { "btcS", { Evh1
, Gv
}, 0 },
2857 { PREFIX_TABLE (PREFIX_0FBC
) },
2858 { PREFIX_TABLE (PREFIX_0FBD
) },
2859 { "movs{bR|x}", { Gv
, Eb
}, 0 },
2860 { "movs{wR|x}", { Gv
, Ew
}, 0 }, /* yes, there really is movsww ! */
2862 { "xaddB", { Ebh1
, Gb
}, 0 },
2863 { "xaddS", { Evh1
, Gv
}, 0 },
2864 { PREFIX_TABLE (PREFIX_0FC2
) },
2865 { MOD_TABLE (MOD_0FC3
) },
2866 { "pinsrw", { MX
, Edqw
, Ib
}, PREFIX_OPCODE
},
2867 { "pextrw", { Gdq
, MS
, Ib
}, PREFIX_OPCODE
},
2868 { "shufpX", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
2869 { REG_TABLE (REG_0FC7
) },
2871 { "bswap", { RMeAX
}, 0 },
2872 { "bswap", { RMeCX
}, 0 },
2873 { "bswap", { RMeDX
}, 0 },
2874 { "bswap", { RMeBX
}, 0 },
2875 { "bswap", { RMeSP
}, 0 },
2876 { "bswap", { RMeBP
}, 0 },
2877 { "bswap", { RMeSI
}, 0 },
2878 { "bswap", { RMeDI
}, 0 },
2880 { PREFIX_TABLE (PREFIX_0FD0
) },
2881 { "psrlw", { MX
, EM
}, PREFIX_OPCODE
},
2882 { "psrld", { MX
, EM
}, PREFIX_OPCODE
},
2883 { "psrlq", { MX
, EM
}, PREFIX_OPCODE
},
2884 { "paddq", { MX
, EM
}, PREFIX_OPCODE
},
2885 { "pmullw", { MX
, EM
}, PREFIX_OPCODE
},
2886 { PREFIX_TABLE (PREFIX_0FD6
) },
2887 { MOD_TABLE (MOD_0FD7
) },
2889 { "psubusb", { MX
, EM
}, PREFIX_OPCODE
},
2890 { "psubusw", { MX
, EM
}, PREFIX_OPCODE
},
2891 { "pminub", { MX
, EM
}, PREFIX_OPCODE
},
2892 { "pand", { MX
, EM
}, PREFIX_OPCODE
},
2893 { "paddusb", { MX
, EM
}, PREFIX_OPCODE
},
2894 { "paddusw", { MX
, EM
}, PREFIX_OPCODE
},
2895 { "pmaxub", { MX
, EM
}, PREFIX_OPCODE
},
2896 { "pandn", { MX
, EM
}, PREFIX_OPCODE
},
2898 { "pavgb", { MX
, EM
}, PREFIX_OPCODE
},
2899 { "psraw", { MX
, EM
}, PREFIX_OPCODE
},
2900 { "psrad", { MX
, EM
}, PREFIX_OPCODE
},
2901 { "pavgw", { MX
, EM
}, PREFIX_OPCODE
},
2902 { "pmulhuw", { MX
, EM
}, PREFIX_OPCODE
},
2903 { "pmulhw", { MX
, EM
}, PREFIX_OPCODE
},
2904 { PREFIX_TABLE (PREFIX_0FE6
) },
2905 { PREFIX_TABLE (PREFIX_0FE7
) },
2907 { "psubsb", { MX
, EM
}, PREFIX_OPCODE
},
2908 { "psubsw", { MX
, EM
}, PREFIX_OPCODE
},
2909 { "pminsw", { MX
, EM
}, PREFIX_OPCODE
},
2910 { "por", { MX
, EM
}, PREFIX_OPCODE
},
2911 { "paddsb", { MX
, EM
}, PREFIX_OPCODE
},
2912 { "paddsw", { MX
, EM
}, PREFIX_OPCODE
},
2913 { "pmaxsw", { MX
, EM
}, PREFIX_OPCODE
},
2914 { "pxor", { MX
, EM
}, PREFIX_OPCODE
},
2916 { PREFIX_TABLE (PREFIX_0FF0
) },
2917 { "psllw", { MX
, EM
}, PREFIX_OPCODE
},
2918 { "pslld", { MX
, EM
}, PREFIX_OPCODE
},
2919 { "psllq", { MX
, EM
}, PREFIX_OPCODE
},
2920 { "pmuludq", { MX
, EM
}, PREFIX_OPCODE
},
2921 { "pmaddwd", { MX
, EM
}, PREFIX_OPCODE
},
2922 { "psadbw", { MX
, EM
}, PREFIX_OPCODE
},
2923 { PREFIX_TABLE (PREFIX_0FF7
) },
2925 { "psubb", { MX
, EM
}, PREFIX_OPCODE
},
2926 { "psubw", { MX
, EM
}, PREFIX_OPCODE
},
2927 { "psubd", { MX
, EM
}, PREFIX_OPCODE
},
2928 { "psubq", { MX
, EM
}, PREFIX_OPCODE
},
2929 { "paddb", { MX
, EM
}, PREFIX_OPCODE
},
2930 { "paddw", { MX
, EM
}, PREFIX_OPCODE
},
2931 { "paddd", { MX
, EM
}, PREFIX_OPCODE
},
2932 { "ud0S", { Gv
, Ev
}, 0 },
2935 static const unsigned char onebyte_has_modrm
[256] = {
2936 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2937 /* ------------------------------- */
2938 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2939 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2940 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2941 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2942 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2943 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2944 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2945 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2946 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2947 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2948 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2949 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2950 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2951 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2952 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2953 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
2954 /* ------------------------------- */
2955 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2958 static const unsigned char twobyte_has_modrm
[256] = {
2959 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2960 /* ------------------------------- */
2961 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2962 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2963 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2964 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2965 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2966 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2967 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2968 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2969 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2970 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2971 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2972 /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2973 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2974 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2975 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2976 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 /* ff */
2977 /* ------------------------------- */
2978 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2981 static char obuf
[100];
2983 static char *mnemonicendp
;
2984 static char scratchbuf
[100];
2985 static unsigned char *start_codep
;
2986 static unsigned char *insn_codep
;
2987 static unsigned char *codep
;
2988 static unsigned char *end_codep
;
2989 static int last_lock_prefix
;
2990 static int last_repz_prefix
;
2991 static int last_repnz_prefix
;
2992 static int last_data_prefix
;
2993 static int last_addr_prefix
;
2994 static int last_rex_prefix
;
2995 static int last_seg_prefix
;
2996 static int fwait_prefix
;
2997 /* The active segment register prefix. */
2998 static int active_seg_prefix
;
2999 #define MAX_CODE_LENGTH 15
3000 /* We can up to 14 prefixes since the maximum instruction length is
3002 static int all_prefixes
[MAX_CODE_LENGTH
- 1];
3003 static disassemble_info
*the_info
;
3011 static unsigned char need_modrm
;
3021 int register_specifier
;
3028 int mask_register_specifier
;
3034 static unsigned char need_vex
;
3035 static unsigned char need_vex_reg
;
3036 static unsigned char vex_w_done
;
3044 /* If we are accessing mod/rm/reg without need_modrm set, then the
3045 values are stale. Hitting this abort likely indicates that you
3046 need to update onebyte_has_modrm or twobyte_has_modrm. */
3047 #define MODRM_CHECK if (!need_modrm) abort ()
3049 static const char **names64
;
3050 static const char **names32
;
3051 static const char **names16
;
3052 static const char **names8
;
3053 static const char **names8rex
;
3054 static const char **names_seg
;
3055 static const char *index64
;
3056 static const char *index32
;
3057 static const char **index16
;
3058 static const char **names_bnd
;
3060 static const char *intel_names64
[] = {
3061 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3062 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3064 static const char *intel_names32
[] = {
3065 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3066 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3068 static const char *intel_names16
[] = {
3069 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3070 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3072 static const char *intel_names8
[] = {
3073 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3075 static const char *intel_names8rex
[] = {
3076 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3077 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3079 static const char *intel_names_seg
[] = {
3080 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3082 static const char *intel_index64
= "riz";
3083 static const char *intel_index32
= "eiz";
3084 static const char *intel_index16
[] = {
3085 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3088 static const char *att_names64
[] = {
3089 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3090 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3092 static const char *att_names32
[] = {
3093 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3094 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3096 static const char *att_names16
[] = {
3097 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3098 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3100 static const char *att_names8
[] = {
3101 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3103 static const char *att_names8rex
[] = {
3104 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3105 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3107 static const char *att_names_seg
[] = {
3108 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3110 static const char *att_index64
= "%riz";
3111 static const char *att_index32
= "%eiz";
3112 static const char *att_index16
[] = {
3113 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3116 static const char **names_mm
;
3117 static const char *intel_names_mm
[] = {
3118 "mm0", "mm1", "mm2", "mm3",
3119 "mm4", "mm5", "mm6", "mm7"
3121 static const char *att_names_mm
[] = {
3122 "%mm0", "%mm1", "%mm2", "%mm3",
3123 "%mm4", "%mm5", "%mm6", "%mm7"
3126 static const char *intel_names_bnd
[] = {
3127 "bnd0", "bnd1", "bnd2", "bnd3"
3130 static const char *att_names_bnd
[] = {
3131 "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3134 static const char **names_xmm
;
3135 static const char *intel_names_xmm
[] = {
3136 "xmm0", "xmm1", "xmm2", "xmm3",
3137 "xmm4", "xmm5", "xmm6", "xmm7",
3138 "xmm8", "xmm9", "xmm10", "xmm11",
3139 "xmm12", "xmm13", "xmm14", "xmm15",
3140 "xmm16", "xmm17", "xmm18", "xmm19",
3141 "xmm20", "xmm21", "xmm22", "xmm23",
3142 "xmm24", "xmm25", "xmm26", "xmm27",
3143 "xmm28", "xmm29", "xmm30", "xmm31"
3145 static const char *att_names_xmm
[] = {
3146 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3147 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3148 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3149 "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3150 "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3151 "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3152 "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3153 "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3156 static const char **names_ymm
;
3157 static const char *intel_names_ymm
[] = {
3158 "ymm0", "ymm1", "ymm2", "ymm3",
3159 "ymm4", "ymm5", "ymm6", "ymm7",
3160 "ymm8", "ymm9", "ymm10", "ymm11",
3161 "ymm12", "ymm13", "ymm14", "ymm15",
3162 "ymm16", "ymm17", "ymm18", "ymm19",
3163 "ymm20", "ymm21", "ymm22", "ymm23",
3164 "ymm24", "ymm25", "ymm26", "ymm27",
3165 "ymm28", "ymm29", "ymm30", "ymm31"
3167 static const char *att_names_ymm
[] = {
3168 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3169 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3170 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3171 "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3172 "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3173 "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3174 "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3175 "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3178 static const char **names_zmm
;
3179 static const char *intel_names_zmm
[] = {
3180 "zmm0", "zmm1", "zmm2", "zmm3",
3181 "zmm4", "zmm5", "zmm6", "zmm7",
3182 "zmm8", "zmm9", "zmm10", "zmm11",
3183 "zmm12", "zmm13", "zmm14", "zmm15",
3184 "zmm16", "zmm17", "zmm18", "zmm19",
3185 "zmm20", "zmm21", "zmm22", "zmm23",
3186 "zmm24", "zmm25", "zmm26", "zmm27",
3187 "zmm28", "zmm29", "zmm30", "zmm31"
3189 static const char *att_names_zmm
[] = {
3190 "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3191 "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3192 "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3193 "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3194 "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3195 "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3196 "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3197 "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3200 static const char **names_mask
;
3201 static const char *intel_names_mask
[] = {
3202 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3204 static const char *att_names_mask
[] = {
3205 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3208 static const char *names_rounding
[] =
3216 static const struct dis386 reg_table
[][8] = {
3219 { "addA", { Ebh1
, Ib
}, 0 },
3220 { "orA", { Ebh1
, Ib
}, 0 },
3221 { "adcA", { Ebh1
, Ib
}, 0 },
3222 { "sbbA", { Ebh1
, Ib
}, 0 },
3223 { "andA", { Ebh1
, Ib
}, 0 },
3224 { "subA", { Ebh1
, Ib
}, 0 },
3225 { "xorA", { Ebh1
, Ib
}, 0 },
3226 { "cmpA", { Eb
, Ib
}, 0 },
3230 { "addQ", { Evh1
, Iv
}, 0 },
3231 { "orQ", { Evh1
, Iv
}, 0 },
3232 { "adcQ", { Evh1
, Iv
}, 0 },
3233 { "sbbQ", { Evh1
, Iv
}, 0 },
3234 { "andQ", { Evh1
, Iv
}, 0 },
3235 { "subQ", { Evh1
, Iv
}, 0 },
3236 { "xorQ", { Evh1
, Iv
}, 0 },
3237 { "cmpQ", { Ev
, Iv
}, 0 },
3241 { "addQ", { Evh1
, sIb
}, 0 },
3242 { "orQ", { Evh1
, sIb
}, 0 },
3243 { "adcQ", { Evh1
, sIb
}, 0 },
3244 { "sbbQ", { Evh1
, sIb
}, 0 },
3245 { "andQ", { Evh1
, sIb
}, 0 },
3246 { "subQ", { Evh1
, sIb
}, 0 },
3247 { "xorQ", { Evh1
, sIb
}, 0 },
3248 { "cmpQ", { Ev
, sIb
}, 0 },
3252 { "popU", { stackEv
}, 0 },
3253 { XOP_8F_TABLE (XOP_09
) },
3257 { XOP_8F_TABLE (XOP_09
) },
3261 { "rolA", { Eb
, Ib
}, 0 },
3262 { "rorA", { Eb
, Ib
}, 0 },
3263 { "rclA", { Eb
, Ib
}, 0 },
3264 { "rcrA", { Eb
, Ib
}, 0 },
3265 { "shlA", { Eb
, Ib
}, 0 },
3266 { "shrA", { Eb
, Ib
}, 0 },
3267 { "shlA", { Eb
, Ib
}, 0 },
3268 { "sarA", { Eb
, Ib
}, 0 },
3272 { "rolQ", { Ev
, Ib
}, 0 },
3273 { "rorQ", { Ev
, Ib
}, 0 },
3274 { "rclQ", { Ev
, Ib
}, 0 },
3275 { "rcrQ", { Ev
, Ib
}, 0 },
3276 { "shlQ", { Ev
, Ib
}, 0 },
3277 { "shrQ", { Ev
, Ib
}, 0 },
3278 { "shlQ", { Ev
, Ib
}, 0 },
3279 { "sarQ", { Ev
, Ib
}, 0 },
3283 { "movA", { Ebh3
, Ib
}, 0 },
3290 { MOD_TABLE (MOD_C6_REG_7
) },
3294 { "movQ", { Evh3
, Iv
}, 0 },
3301 { MOD_TABLE (MOD_C7_REG_7
) },
3305 { "rolA", { Eb
, I1
}, 0 },
3306 { "rorA", { Eb
, I1
}, 0 },
3307 { "rclA", { Eb
, I1
}, 0 },
3308 { "rcrA", { Eb
, I1
}, 0 },
3309 { "shlA", { Eb
, I1
}, 0 },
3310 { "shrA", { Eb
, I1
}, 0 },
3311 { "shlA", { Eb
, I1
}, 0 },
3312 { "sarA", { Eb
, I1
}, 0 },
3316 { "rolQ", { Ev
, I1
}, 0 },
3317 { "rorQ", { Ev
, I1
}, 0 },
3318 { "rclQ", { Ev
, I1
}, 0 },
3319 { "rcrQ", { Ev
, I1
}, 0 },
3320 { "shlQ", { Ev
, I1
}, 0 },
3321 { "shrQ", { Ev
, I1
}, 0 },
3322 { "shlQ", { Ev
, I1
}, 0 },
3323 { "sarQ", { Ev
, I1
}, 0 },
3327 { "rolA", { Eb
, CL
}, 0 },
3328 { "rorA", { Eb
, CL
}, 0 },
3329 { "rclA", { Eb
, CL
}, 0 },
3330 { "rcrA", { Eb
, CL
}, 0 },
3331 { "shlA", { Eb
, CL
}, 0 },
3332 { "shrA", { Eb
, CL
}, 0 },
3333 { "shlA", { Eb
, CL
}, 0 },
3334 { "sarA", { Eb
, CL
}, 0 },
3338 { "rolQ", { Ev
, CL
}, 0 },
3339 { "rorQ", { Ev
, CL
}, 0 },
3340 { "rclQ", { Ev
, CL
}, 0 },
3341 { "rcrQ", { Ev
, CL
}, 0 },
3342 { "shlQ", { Ev
, CL
}, 0 },
3343 { "shrQ", { Ev
, CL
}, 0 },
3344 { "shlQ", { Ev
, CL
}, 0 },
3345 { "sarQ", { Ev
, CL
}, 0 },
3349 { "testA", { Eb
, Ib
}, 0 },
3350 { "testA", { Eb
, Ib
}, 0 },
3351 { "notA", { Ebh1
}, 0 },
3352 { "negA", { Ebh1
}, 0 },
3353 { "mulA", { Eb
}, 0 }, /* Don't print the implicit %al register, */
3354 { "imulA", { Eb
}, 0 }, /* to distinguish these opcodes from other */
3355 { "divA", { Eb
}, 0 }, /* mul/imul opcodes. Do the same for div */
3356 { "idivA", { Eb
}, 0 }, /* and idiv for consistency. */
3360 { "testQ", { Ev
, Iv
}, 0 },
3361 { "testQ", { Ev
, Iv
}, 0 },
3362 { "notQ", { Evh1
}, 0 },
3363 { "negQ", { Evh1
}, 0 },
3364 { "mulQ", { Ev
}, 0 }, /* Don't print the implicit register. */
3365 { "imulQ", { Ev
}, 0 },
3366 { "divQ", { Ev
}, 0 },
3367 { "idivQ", { Ev
}, 0 },
3371 { "incA", { Ebh1
}, 0 },
3372 { "decA", { Ebh1
}, 0 },
3376 { "incQ", { Evh1
}, 0 },
3377 { "decQ", { Evh1
}, 0 },
3378 { "call{&|}", { NOTRACK
, indirEv
, BND
}, 0 },
3379 { MOD_TABLE (MOD_FF_REG_3
) },
3380 { "jmp{&|}", { NOTRACK
, indirEv
, BND
}, 0 },
3381 { MOD_TABLE (MOD_FF_REG_5
) },
3382 { "pushU", { stackEv
}, 0 },
3387 { "sldtD", { Sv
}, 0 },
3388 { "strD", { Sv
}, 0 },
3389 { "lldt", { Ew
}, 0 },
3390 { "ltr", { Ew
}, 0 },
3391 { "verr", { Ew
}, 0 },
3392 { "verw", { Ew
}, 0 },
3398 { MOD_TABLE (MOD_0F01_REG_0
) },
3399 { MOD_TABLE (MOD_0F01_REG_1
) },
3400 { MOD_TABLE (MOD_0F01_REG_2
) },
3401 { MOD_TABLE (MOD_0F01_REG_3
) },
3402 { "smswD", { Sv
}, 0 },
3403 { MOD_TABLE (MOD_0F01_REG_5
) },
3404 { "lmsw", { Ew
}, 0 },
3405 { MOD_TABLE (MOD_0F01_REG_7
) },
3409 { "prefetch", { Mb
}, 0 },
3410 { "prefetchw", { Mb
}, 0 },
3411 { "prefetchwt1", { Mb
}, 0 },
3412 { "prefetch", { Mb
}, 0 },
3413 { "prefetch", { Mb
}, 0 },
3414 { "prefetch", { Mb
}, 0 },
3415 { "prefetch", { Mb
}, 0 },
3416 { "prefetch", { Mb
}, 0 },
3420 { MOD_TABLE (MOD_0F18_REG_0
) },
3421 { MOD_TABLE (MOD_0F18_REG_1
) },
3422 { MOD_TABLE (MOD_0F18_REG_2
) },
3423 { MOD_TABLE (MOD_0F18_REG_3
) },
3424 { MOD_TABLE (MOD_0F18_REG_4
) },
3425 { MOD_TABLE (MOD_0F18_REG_5
) },
3426 { MOD_TABLE (MOD_0F18_REG_6
) },
3427 { MOD_TABLE (MOD_0F18_REG_7
) },
3429 /* REG_0F1C_MOD_0 */
3431 { "cldemote", { Mb
}, 0 },
3432 { "nopQ", { Ev
}, 0 },
3433 { "nopQ", { Ev
}, 0 },
3434 { "nopQ", { Ev
}, 0 },
3435 { "nopQ", { Ev
}, 0 },
3436 { "nopQ", { Ev
}, 0 },
3437 { "nopQ", { Ev
}, 0 },
3438 { "nopQ", { Ev
}, 0 },
3440 /* REG_0F1E_MOD_3 */
3442 { "nopQ", { Ev
}, 0 },
3443 { "rdsspK", { Rdq
}, PREFIX_OPCODE
},
3444 { "nopQ", { Ev
}, 0 },
3445 { "nopQ", { Ev
}, 0 },
3446 { "nopQ", { Ev
}, 0 },
3447 { "nopQ", { Ev
}, 0 },
3448 { "nopQ", { Ev
}, 0 },
3449 { RM_TABLE (RM_0F1E_MOD_3_REG_7
) },
3455 { MOD_TABLE (MOD_0F71_REG_2
) },
3457 { MOD_TABLE (MOD_0F71_REG_4
) },
3459 { MOD_TABLE (MOD_0F71_REG_6
) },
3465 { MOD_TABLE (MOD_0F72_REG_2
) },
3467 { MOD_TABLE (MOD_0F72_REG_4
) },
3469 { MOD_TABLE (MOD_0F72_REG_6
) },
3475 { MOD_TABLE (MOD_0F73_REG_2
) },
3476 { MOD_TABLE (MOD_0F73_REG_3
) },
3479 { MOD_TABLE (MOD_0F73_REG_6
) },
3480 { MOD_TABLE (MOD_0F73_REG_7
) },
3484 { "montmul", { { OP_0f07
, 0 } }, 0 },
3485 { "xsha1", { { OP_0f07
, 0 } }, 0 },
3486 { "xsha256", { { OP_0f07
, 0 } }, 0 },
3490 { "xstore-rng", { { OP_0f07
, 0 } }, 0 },
3491 { "xcrypt-ecb", { { OP_0f07
, 0 } }, 0 },
3492 { "xcrypt-cbc", { { OP_0f07
, 0 } }, 0 },
3493 { "xcrypt-ctr", { { OP_0f07
, 0 } }, 0 },
3494 { "xcrypt-cfb", { { OP_0f07
, 0 } }, 0 },
3495 { "xcrypt-ofb", { { OP_0f07
, 0 } }, 0 },
3499 { MOD_TABLE (MOD_0FAE_REG_0
) },
3500 { MOD_TABLE (MOD_0FAE_REG_1
) },
3501 { MOD_TABLE (MOD_0FAE_REG_2
) },
3502 { MOD_TABLE (MOD_0FAE_REG_3
) },
3503 { MOD_TABLE (MOD_0FAE_REG_4
) },
3504 { MOD_TABLE (MOD_0FAE_REG_5
) },
3505 { MOD_TABLE (MOD_0FAE_REG_6
) },
3506 { MOD_TABLE (MOD_0FAE_REG_7
) },
3514 { "btQ", { Ev
, Ib
}, 0 },
3515 { "btsQ", { Evh1
, Ib
}, 0 },
3516 { "btrQ", { Evh1
, Ib
}, 0 },
3517 { "btcQ", { Evh1
, Ib
}, 0 },
3522 { "cmpxchg8b", { { CMPXCHG8B_Fixup
, q_mode
} }, 0 },
3524 { MOD_TABLE (MOD_0FC7_REG_3
) },
3525 { MOD_TABLE (MOD_0FC7_REG_4
) },
3526 { MOD_TABLE (MOD_0FC7_REG_5
) },
3527 { MOD_TABLE (MOD_0FC7_REG_6
) },
3528 { MOD_TABLE (MOD_0FC7_REG_7
) },
3534 { MOD_TABLE (MOD_VEX_0F71_REG_2
) },
3536 { MOD_TABLE (MOD_VEX_0F71_REG_4
) },
3538 { MOD_TABLE (MOD_VEX_0F71_REG_6
) },
3544 { MOD_TABLE (MOD_VEX_0F72_REG_2
) },
3546 { MOD_TABLE (MOD_VEX_0F72_REG_4
) },
3548 { MOD_TABLE (MOD_VEX_0F72_REG_6
) },
3554 { MOD_TABLE (MOD_VEX_0F73_REG_2
) },
3555 { MOD_TABLE (MOD_VEX_0F73_REG_3
) },
3558 { MOD_TABLE (MOD_VEX_0F73_REG_6
) },
3559 { MOD_TABLE (MOD_VEX_0F73_REG_7
) },
3565 { MOD_TABLE (MOD_VEX_0FAE_REG_2
) },
3566 { MOD_TABLE (MOD_VEX_0FAE_REG_3
) },
3568 /* REG_VEX_0F38F3 */
3571 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1
) },
3572 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2
) },
3573 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3
) },
3577 { "llwpcb", { { OP_LWPCB_E
, 0 } }, 0 },
3578 { "slwpcb", { { OP_LWPCB_E
, 0 } }, 0 },
3582 { "lwpins", { { OP_LWP_E
, 0 }, Ed
, Iq
}, 0 },
3583 { "lwpval", { { OP_LWP_E
, 0 }, Ed
, Iq
}, 0 },
3585 /* REG_XOP_TBM_01 */
3588 { "blcfill", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3589 { "blsfill", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3590 { "blcs", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3591 { "tzmsk", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3592 { "blcic", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3593 { "blsic", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3594 { "t1mskc", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3596 /* REG_XOP_TBM_02 */
3599 { "blcmsk", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3604 { "blci", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3606 #define NEED_REG_TABLE
3607 #include "i386-dis-evex.h"
3608 #undef NEED_REG_TABLE
3611 static const struct dis386 prefix_table
[][4] = {
3614 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} }, 0 },
3615 { "pause", { XX
}, 0 },
3616 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} }, 0 },
3617 { NULL
, { { NULL
, 0 } }, PREFIX_IGNORED
}
3620 /* PREFIX_MOD_0_0F01_REG_5 */
3623 { "rstorssp", { Mq
}, PREFIX_OPCODE
},
3626 /* PREFIX_MOD_3_0F01_REG_5_RM_0 */
3629 { "setssbsy", { Skip_MODRM
}, PREFIX_OPCODE
},
3632 /* PREFIX_MOD_3_0F01_REG_5_RM_2 */
3635 { "saveprevssp", { Skip_MODRM
}, PREFIX_OPCODE
},
3640 { "wbinvd", { XX
}, 0 },
3641 { "wbnoinvd", { XX
}, 0 },
3646 { "movups", { XM
, EXx
}, PREFIX_OPCODE
},
3647 { "movss", { XM
, EXd
}, PREFIX_OPCODE
},
3648 { "movupd", { XM
, EXx
}, PREFIX_OPCODE
},
3649 { "movsd", { XM
, EXq
}, PREFIX_OPCODE
},
3654 { "movups", { EXxS
, XM
}, PREFIX_OPCODE
},
3655 { "movss", { EXdS
, XM
}, PREFIX_OPCODE
},
3656 { "movupd", { EXxS
, XM
}, PREFIX_OPCODE
},
3657 { "movsd", { EXqS
, XM
}, PREFIX_OPCODE
},
3662 { MOD_TABLE (MOD_0F12_PREFIX_0
) },
3663 { "movsldup", { XM
, EXx
}, PREFIX_OPCODE
},
3664 { "movlpd", { XM
, EXq
}, PREFIX_OPCODE
},
3665 { "movddup", { XM
, EXq
}, PREFIX_OPCODE
},
3670 { MOD_TABLE (MOD_0F16_PREFIX_0
) },
3671 { "movshdup", { XM
, EXx
}, PREFIX_OPCODE
},
3672 { "movhpd", { XM
, EXq
}, PREFIX_OPCODE
},
3677 { MOD_TABLE (MOD_0F1A_PREFIX_0
) },
3678 { "bndcl", { Gbnd
, Ev_bnd
}, 0 },
3679 { "bndmov", { Gbnd
, Ebnd
}, 0 },
3680 { "bndcu", { Gbnd
, Ev_bnd
}, 0 },
3685 { MOD_TABLE (MOD_0F1B_PREFIX_0
) },
3686 { MOD_TABLE (MOD_0F1B_PREFIX_1
) },
3687 { "bndmov", { EbndS
, Gbnd
}, 0 },
3688 { "bndcn", { Gbnd
, Ev_bnd
}, 0 },
3693 { MOD_TABLE (MOD_0F1C_PREFIX_0
) },
3694 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3695 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3696 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3701 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3702 { MOD_TABLE (MOD_0F1E_PREFIX_1
) },
3703 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3704 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3709 { "cvtpi2ps", { XM
, EMCq
}, PREFIX_OPCODE
},
3710 { "cvtsi2ss%LQ", { XM
, Ev
}, PREFIX_OPCODE
},
3711 { "cvtpi2pd", { XM
, EMCq
}, PREFIX_OPCODE
},
3712 { "cvtsi2sd%LQ", { XM
, Ev
}, 0 },
3717 { MOD_TABLE (MOD_0F2B_PREFIX_0
) },
3718 { MOD_TABLE (MOD_0F2B_PREFIX_1
) },
3719 { MOD_TABLE (MOD_0F2B_PREFIX_2
) },
3720 { MOD_TABLE (MOD_0F2B_PREFIX_3
) },
3725 { "cvttps2pi", { MXC
, EXq
}, PREFIX_OPCODE
},
3726 { "cvttss2si", { Gv
, EXd
}, PREFIX_OPCODE
},
3727 { "cvttpd2pi", { MXC
, EXx
}, PREFIX_OPCODE
},
3728 { "cvttsd2si", { Gv
, EXq
}, PREFIX_OPCODE
},
3733 { "cvtps2pi", { MXC
, EXq
}, PREFIX_OPCODE
},
3734 { "cvtss2si", { Gv
, EXd
}, PREFIX_OPCODE
},
3735 { "cvtpd2pi", { MXC
, EXx
}, PREFIX_OPCODE
},
3736 { "cvtsd2si", { Gv
, EXq
}, PREFIX_OPCODE
},
3741 { "ucomiss",{ XM
, EXd
}, 0 },
3743 { "ucomisd",{ XM
, EXq
}, 0 },
3748 { "comiss", { XM
, EXd
}, 0 },
3750 { "comisd", { XM
, EXq
}, 0 },
3755 { "sqrtps", { XM
, EXx
}, PREFIX_OPCODE
},
3756 { "sqrtss", { XM
, EXd
}, PREFIX_OPCODE
},
3757 { "sqrtpd", { XM
, EXx
}, PREFIX_OPCODE
},
3758 { "sqrtsd", { XM
, EXq
}, PREFIX_OPCODE
},
3763 { "rsqrtps",{ XM
, EXx
}, PREFIX_OPCODE
},
3764 { "rsqrtss",{ XM
, EXd
}, PREFIX_OPCODE
},
3769 { "rcpps", { XM
, EXx
}, PREFIX_OPCODE
},
3770 { "rcpss", { XM
, EXd
}, PREFIX_OPCODE
},
3775 { "addps", { XM
, EXx
}, PREFIX_OPCODE
},
3776 { "addss", { XM
, EXd
}, PREFIX_OPCODE
},
3777 { "addpd", { XM
, EXx
}, PREFIX_OPCODE
},
3778 { "addsd", { XM
, EXq
}, PREFIX_OPCODE
},
3783 { "mulps", { XM
, EXx
}, PREFIX_OPCODE
},
3784 { "mulss", { XM
, EXd
}, PREFIX_OPCODE
},
3785 { "mulpd", { XM
, EXx
}, PREFIX_OPCODE
},
3786 { "mulsd", { XM
, EXq
}, PREFIX_OPCODE
},
3791 { "cvtps2pd", { XM
, EXq
}, PREFIX_OPCODE
},
3792 { "cvtss2sd", { XM
, EXd
}, PREFIX_OPCODE
},
3793 { "cvtpd2ps", { XM
, EXx
}, PREFIX_OPCODE
},
3794 { "cvtsd2ss", { XM
, EXq
}, PREFIX_OPCODE
},
3799 { "cvtdq2ps", { XM
, EXx
}, PREFIX_OPCODE
},
3800 { "cvttps2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3801 { "cvtps2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3806 { "subps", { XM
, EXx
}, PREFIX_OPCODE
},
3807 { "subss", { XM
, EXd
}, PREFIX_OPCODE
},
3808 { "subpd", { XM
, EXx
}, PREFIX_OPCODE
},
3809 { "subsd", { XM
, EXq
}, PREFIX_OPCODE
},
3814 { "minps", { XM
, EXx
}, PREFIX_OPCODE
},
3815 { "minss", { XM
, EXd
}, PREFIX_OPCODE
},
3816 { "minpd", { XM
, EXx
}, PREFIX_OPCODE
},
3817 { "minsd", { XM
, EXq
}, PREFIX_OPCODE
},
3822 { "divps", { XM
, EXx
}, PREFIX_OPCODE
},
3823 { "divss", { XM
, EXd
}, PREFIX_OPCODE
},
3824 { "divpd", { XM
, EXx
}, PREFIX_OPCODE
},
3825 { "divsd", { XM
, EXq
}, PREFIX_OPCODE
},
3830 { "maxps", { XM
, EXx
}, PREFIX_OPCODE
},
3831 { "maxss", { XM
, EXd
}, PREFIX_OPCODE
},
3832 { "maxpd", { XM
, EXx
}, PREFIX_OPCODE
},
3833 { "maxsd", { XM
, EXq
}, PREFIX_OPCODE
},
3838 { "punpcklbw",{ MX
, EMd
}, PREFIX_OPCODE
},
3840 { "punpcklbw",{ MX
, EMx
}, PREFIX_OPCODE
},
3845 { "punpcklwd",{ MX
, EMd
}, PREFIX_OPCODE
},
3847 { "punpcklwd",{ MX
, EMx
}, PREFIX_OPCODE
},
3852 { "punpckldq",{ MX
, EMd
}, PREFIX_OPCODE
},
3854 { "punpckldq",{ MX
, EMx
}, PREFIX_OPCODE
},
3861 { "punpcklqdq", { XM
, EXx
}, PREFIX_OPCODE
},
3868 { "punpckhqdq", { XM
, EXx
}, PREFIX_OPCODE
},
3873 { "movq", { MX
, EM
}, PREFIX_OPCODE
},
3874 { "movdqu", { XM
, EXx
}, PREFIX_OPCODE
},
3875 { "movdqa", { XM
, EXx
}, PREFIX_OPCODE
},
3880 { "pshufw", { MX
, EM
, Ib
}, PREFIX_OPCODE
},
3881 { "pshufhw",{ XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3882 { "pshufd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3883 { "pshuflw",{ XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3886 /* PREFIX_0F73_REG_3 */
3890 { "psrldq", { XS
, Ib
}, 0 },
3893 /* PREFIX_0F73_REG_7 */
3897 { "pslldq", { XS
, Ib
}, 0 },
3902 {"vmread", { Em
, Gm
}, 0 },
3904 {"extrq", { XS
, Ib
, Ib
}, 0 },
3905 {"insertq", { XM
, XS
, Ib
, Ib
}, 0 },
3910 {"vmwrite", { Gm
, Em
}, 0 },
3912 {"extrq", { XM
, XS
}, 0 },
3913 {"insertq", { XM
, XS
}, 0 },
3920 { "haddpd", { XM
, EXx
}, PREFIX_OPCODE
},
3921 { "haddps", { XM
, EXx
}, PREFIX_OPCODE
},
3928 { "hsubpd", { XM
, EXx
}, PREFIX_OPCODE
},
3929 { "hsubps", { XM
, EXx
}, PREFIX_OPCODE
},
3934 { "movK", { Edq
, MX
}, PREFIX_OPCODE
},
3935 { "movq", { XM
, EXq
}, PREFIX_OPCODE
},
3936 { "movK", { Edq
, XM
}, PREFIX_OPCODE
},
3941 { "movq", { EMS
, MX
}, PREFIX_OPCODE
},
3942 { "movdqu", { EXxS
, XM
}, PREFIX_OPCODE
},
3943 { "movdqa", { EXxS
, XM
}, PREFIX_OPCODE
},
3946 /* PREFIX_0FAE_REG_0 */
3949 { "rdfsbase", { Ev
}, 0 },
3952 /* PREFIX_0FAE_REG_1 */
3955 { "rdgsbase", { Ev
}, 0 },
3958 /* PREFIX_0FAE_REG_2 */
3961 { "wrfsbase", { Ev
}, 0 },
3964 /* PREFIX_0FAE_REG_3 */
3967 { "wrgsbase", { Ev
}, 0 },
3970 /* PREFIX_MOD_0_0FAE_REG_4 */
3972 { "xsave", { FXSAVE
}, 0 },
3973 { "ptwrite%LQ", { Edq
}, 0 },
3976 /* PREFIX_MOD_3_0FAE_REG_4 */
3979 { "ptwrite%LQ", { Edq
}, 0 },
3982 /* PREFIX_MOD_0_0FAE_REG_5 */
3984 { "xrstor", { FXSAVE
}, PREFIX_OPCODE
},
3987 /* PREFIX_MOD_3_0FAE_REG_5 */
3989 { "lfence", { Skip_MODRM
}, 0 },
3990 { "incsspK", { Rdq
}, PREFIX_OPCODE
},
3993 /* PREFIX_MOD_0_0FAE_REG_6 */
3995 { "xsaveopt", { FXSAVE
}, PREFIX_OPCODE
},
3996 { "clrssbsy", { Mq
}, PREFIX_OPCODE
},
3997 { "clwb", { Mb
}, PREFIX_OPCODE
},
4000 /* PREFIX_MOD_1_0FAE_REG_6 */
4002 { RM_TABLE (RM_0FAE_REG_6
) },
4003 { "umonitor", { Eva
}, PREFIX_OPCODE
},
4004 { "tpause", { Edq
}, PREFIX_OPCODE
},
4005 { "umwait", { Edq
}, PREFIX_OPCODE
},
4008 /* PREFIX_0FAE_REG_7 */
4010 { "clflush", { Mb
}, 0 },
4012 { "clflushopt", { Mb
}, 0 },
4018 { "popcntS", { Gv
, Ev
}, 0 },
4023 { "bsfS", { Gv
, Ev
}, 0 },
4024 { "tzcntS", { Gv
, Ev
}, 0 },
4025 { "bsfS", { Gv
, Ev
}, 0 },
4030 { "bsrS", { Gv
, Ev
}, 0 },
4031 { "lzcntS", { Gv
, Ev
}, 0 },
4032 { "bsrS", { Gv
, Ev
}, 0 },
4037 { "cmpps", { XM
, EXx
, CMP
}, PREFIX_OPCODE
},
4038 { "cmpss", { XM
, EXd
, CMP
}, PREFIX_OPCODE
},
4039 { "cmppd", { XM
, EXx
, CMP
}, PREFIX_OPCODE
},
4040 { "cmpsd", { XM
, EXq
, CMP
}, PREFIX_OPCODE
},
4043 /* PREFIX_MOD_0_0FC3 */
4045 { "movntiS", { Ev
, Gv
}, PREFIX_OPCODE
},
4048 /* PREFIX_MOD_0_0FC7_REG_6 */
4050 { "vmptrld",{ Mq
}, 0 },
4051 { "vmxon", { Mq
}, 0 },
4052 { "vmclear",{ Mq
}, 0 },
4055 /* PREFIX_MOD_3_0FC7_REG_6 */
4057 { "rdrand", { Ev
}, 0 },
4059 { "rdrand", { Ev
}, 0 }
4062 /* PREFIX_MOD_3_0FC7_REG_7 */
4064 { "rdseed", { Ev
}, 0 },
4065 { "rdpid", { Em
}, 0 },
4066 { "rdseed", { Ev
}, 0 },
4073 { "addsubpd", { XM
, EXx
}, 0 },
4074 { "addsubps", { XM
, EXx
}, 0 },
4080 { "movq2dq",{ XM
, MS
}, 0 },
4081 { "movq", { EXqS
, XM
}, 0 },
4082 { "movdq2q",{ MX
, XS
}, 0 },
4088 { "cvtdq2pd", { XM
, EXq
}, PREFIX_OPCODE
},
4089 { "cvttpd2dq", { XM
, EXx
}, PREFIX_OPCODE
},
4090 { "cvtpd2dq", { XM
, EXx
}, PREFIX_OPCODE
},
4095 { "movntq", { Mq
, MX
}, PREFIX_OPCODE
},
4097 { MOD_TABLE (MOD_0FE7_PREFIX_2
) },
4105 { MOD_TABLE (MOD_0FF0_PREFIX_3
) },
4110 { "maskmovq", { MX
, MS
}, PREFIX_OPCODE
},
4112 { "maskmovdqu", { XM
, XS
}, PREFIX_OPCODE
},
4119 { "pblendvb", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4126 { "blendvps", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4133 { "blendvpd", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4140 { "ptest", { XM
, EXx
}, PREFIX_OPCODE
},
4147 { "pmovsxbw", { XM
, EXq
}, PREFIX_OPCODE
},
4154 { "pmovsxbd", { XM
, EXd
}, PREFIX_OPCODE
},
4161 { "pmovsxbq", { XM
, EXw
}, PREFIX_OPCODE
},
4168 { "pmovsxwd", { XM
, EXq
}, PREFIX_OPCODE
},
4175 { "pmovsxwq", { XM
, EXd
}, PREFIX_OPCODE
},
4182 { "pmovsxdq", { XM
, EXq
}, PREFIX_OPCODE
},
4189 { "pmuldq", { XM
, EXx
}, PREFIX_OPCODE
},
4196 { "pcmpeqq", { XM
, EXx
}, PREFIX_OPCODE
},
4203 { MOD_TABLE (MOD_0F382A_PREFIX_2
) },
4210 { "packusdw", { XM
, EXx
}, PREFIX_OPCODE
},
4217 { "pmovzxbw", { XM
, EXq
}, PREFIX_OPCODE
},
4224 { "pmovzxbd", { XM
, EXd
}, PREFIX_OPCODE
},
4231 { "pmovzxbq", { XM
, EXw
}, PREFIX_OPCODE
},
4238 { "pmovzxwd", { XM
, EXq
}, PREFIX_OPCODE
},
4245 { "pmovzxwq", { XM
, EXd
}, PREFIX_OPCODE
},
4252 { "pmovzxdq", { XM
, EXq
}, PREFIX_OPCODE
},
4259 { "pcmpgtq", { XM
, EXx
}, PREFIX_OPCODE
},
4266 { "pminsb", { XM
, EXx
}, PREFIX_OPCODE
},
4273 { "pminsd", { XM
, EXx
}, PREFIX_OPCODE
},
4280 { "pminuw", { XM
, EXx
}, PREFIX_OPCODE
},
4287 { "pminud", { XM
, EXx
}, PREFIX_OPCODE
},
4294 { "pmaxsb", { XM
, EXx
}, PREFIX_OPCODE
},
4301 { "pmaxsd", { XM
, EXx
}, PREFIX_OPCODE
},
4308 { "pmaxuw", { XM
, EXx
}, PREFIX_OPCODE
},
4315 { "pmaxud", { XM
, EXx
}, PREFIX_OPCODE
},
4322 { "pmulld", { XM
, EXx
}, PREFIX_OPCODE
},
4329 { "phminposuw", { XM
, EXx
}, PREFIX_OPCODE
},
4336 { "invept", { Gm
, Mo
}, PREFIX_OPCODE
},
4343 { "invvpid", { Gm
, Mo
}, PREFIX_OPCODE
},
4350 { "invpcid", { Gm
, M
}, PREFIX_OPCODE
},
4355 { "sha1nexte", { XM
, EXxmm
}, PREFIX_OPCODE
},
4360 { "sha1msg1", { XM
, EXxmm
}, PREFIX_OPCODE
},
4365 { "sha1msg2", { XM
, EXxmm
}, PREFIX_OPCODE
},
4370 { "sha256rnds2", { XM
, EXxmm
, XMM0
}, PREFIX_OPCODE
},
4375 { "sha256msg1", { XM
, EXxmm
}, PREFIX_OPCODE
},
4380 { "sha256msg2", { XM
, EXxmm
}, PREFIX_OPCODE
},
4387 { "gf2p8mulb", { XM
, EXxmm
}, PREFIX_OPCODE
},
4394 { "aesimc", { XM
, EXx
}, PREFIX_OPCODE
},
4401 { "aesenc", { XM
, EXx
}, PREFIX_OPCODE
},
4408 { "aesenclast", { XM
, EXx
}, PREFIX_OPCODE
},
4415 { "aesdec", { XM
, EXx
}, PREFIX_OPCODE
},
4422 { "aesdeclast", { XM
, EXx
}, PREFIX_OPCODE
},
4427 { "movbeS", { Gv
, { MOVBE_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4429 { "movbeS", { Gv
, { MOVBE_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4430 { "crc32", { Gdq
, { CRC32_Fixup
, b_mode
} }, PREFIX_OPCODE
},
4435 { "movbeS", { { MOVBE_Fixup
, v_mode
}, Gv
}, PREFIX_OPCODE
},
4437 { "movbeS", { { MOVBE_Fixup
, v_mode
}, Gv
}, PREFIX_OPCODE
},
4438 { "crc32", { Gdq
, { CRC32_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4445 { MOD_TABLE (MOD_0F38F5_PREFIX_2
) },
4450 { MOD_TABLE (MOD_0F38F6_PREFIX_0
) },
4451 { "adoxS", { Gdq
, Edq
}, PREFIX_OPCODE
},
4452 { "adcxS", { Gdq
, Edq
}, PREFIX_OPCODE
},
4459 { MOD_TABLE (MOD_0F38F8_PREFIX_1
) },
4460 { MOD_TABLE (MOD_0F38F8_PREFIX_2
) },
4461 { MOD_TABLE (MOD_0F38F8_PREFIX_3
) },
4466 { MOD_TABLE (MOD_0F38F9_PREFIX_0
) },
4473 { "roundps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4480 { "roundpd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4487 { "roundss", { XM
, EXd
, Ib
}, PREFIX_OPCODE
},
4494 { "roundsd", { XM
, EXq
, Ib
}, PREFIX_OPCODE
},
4501 { "blendps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4508 { "blendpd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4515 { "pblendw", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4522 { "pextrb", { Edqb
, XM
, Ib
}, PREFIX_OPCODE
},
4529 { "pextrw", { Edqw
, XM
, Ib
}, PREFIX_OPCODE
},
4536 { "pextrK", { Edq
, XM
, Ib
}, PREFIX_OPCODE
},
4543 { "extractps", { Edqd
, XM
, Ib
}, PREFIX_OPCODE
},
4550 { "pinsrb", { XM
, Edqb
, Ib
}, PREFIX_OPCODE
},
4557 { "insertps", { XM
, EXd
, Ib
}, PREFIX_OPCODE
},
4564 { "pinsrK", { XM
, Edq
, Ib
}, PREFIX_OPCODE
},
4571 { "dpps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4578 { "dppd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4585 { "mpsadbw", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4592 { "pclmulqdq", { XM
, EXx
, PCLMUL
}, PREFIX_OPCODE
},
4599 { "pcmpestrm", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, PREFIX_OPCODE
},
4606 { "pcmpestri", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, PREFIX_OPCODE
},
4613 { "pcmpistrm", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4620 { "pcmpistri", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4625 { "sha1rnds4", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4632 { "gf2p8affineqb", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4639 { "gf2p8affineinvqb", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4646 { "aeskeygenassist", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4649 /* PREFIX_VEX_0F10 */
4651 { "vmovups", { XM
, EXx
}, 0 },
4652 { "vmovss", { XMVexScalar
, VexScalar
, EXdScalar
}, 0 },
4653 { "vmovupd", { XM
, EXx
}, 0 },
4654 { "vmovsd", { XMVexScalar
, VexScalar
, EXqScalar
}, 0 },
4657 /* PREFIX_VEX_0F11 */
4659 { "vmovups", { EXxS
, XM
}, 0 },
4660 { "vmovss", { EXdVexScalarS
, VexScalar
, XMScalar
}, 0 },
4661 { "vmovupd", { EXxS
, XM
}, 0 },
4662 { "vmovsd", { EXqVexScalarS
, VexScalar
, XMScalar
}, 0 },
4665 /* PREFIX_VEX_0F12 */
4667 { MOD_TABLE (MOD_VEX_0F12_PREFIX_0
) },
4668 { "vmovsldup", { XM
, EXx
}, 0 },
4669 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2
) },
4670 { "vmovddup", { XM
, EXymmq
}, 0 },
4673 /* PREFIX_VEX_0F16 */
4675 { MOD_TABLE (MOD_VEX_0F16_PREFIX_0
) },
4676 { "vmovshdup", { XM
, EXx
}, 0 },
4677 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2
) },
4680 /* PREFIX_VEX_0F2A */
4683 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1
) },
4685 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3
) },
4688 /* PREFIX_VEX_0F2C */
4691 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1
) },
4693 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3
) },
4696 /* PREFIX_VEX_0F2D */
4699 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1
) },
4701 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3
) },
4704 /* PREFIX_VEX_0F2E */
4706 { "vucomiss", { XMScalar
, EXdScalar
}, 0 },
4708 { "vucomisd", { XMScalar
, EXqScalar
}, 0 },
4711 /* PREFIX_VEX_0F2F */
4713 { "vcomiss", { XMScalar
, EXdScalar
}, 0 },
4715 { "vcomisd", { XMScalar
, EXqScalar
}, 0 },
4718 /* PREFIX_VEX_0F41 */
4720 { VEX_LEN_TABLE (VEX_LEN_0F41_P_0
) },
4722 { VEX_LEN_TABLE (VEX_LEN_0F41_P_2
) },
4725 /* PREFIX_VEX_0F42 */
4727 { VEX_LEN_TABLE (VEX_LEN_0F42_P_0
) },
4729 { VEX_LEN_TABLE (VEX_LEN_0F42_P_2
) },
4732 /* PREFIX_VEX_0F44 */
4734 { VEX_LEN_TABLE (VEX_LEN_0F44_P_0
) },
4736 { VEX_LEN_TABLE (VEX_LEN_0F44_P_2
) },
4739 /* PREFIX_VEX_0F45 */
4741 { VEX_LEN_TABLE (VEX_LEN_0F45_P_0
) },
4743 { VEX_LEN_TABLE (VEX_LEN_0F45_P_2
) },
4746 /* PREFIX_VEX_0F46 */
4748 { VEX_LEN_TABLE (VEX_LEN_0F46_P_0
) },
4750 { VEX_LEN_TABLE (VEX_LEN_0F46_P_2
) },
4753 /* PREFIX_VEX_0F47 */
4755 { VEX_LEN_TABLE (VEX_LEN_0F47_P_0
) },
4757 { VEX_LEN_TABLE (VEX_LEN_0F47_P_2
) },
4760 /* PREFIX_VEX_0F4A */
4762 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0
) },
4764 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2
) },
4767 /* PREFIX_VEX_0F4B */
4769 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0
) },
4771 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2
) },
4774 /* PREFIX_VEX_0F51 */
4776 { "vsqrtps", { XM
, EXx
}, 0 },
4777 { "vsqrtss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4778 { "vsqrtpd", { XM
, EXx
}, 0 },
4779 { "vsqrtsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4782 /* PREFIX_VEX_0F52 */
4784 { "vrsqrtps", { XM
, EXx
}, 0 },
4785 { "vrsqrtss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4788 /* PREFIX_VEX_0F53 */
4790 { "vrcpps", { XM
, EXx
}, 0 },
4791 { "vrcpss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4794 /* PREFIX_VEX_0F58 */
4796 { "vaddps", { XM
, Vex
, EXx
}, 0 },
4797 { "vaddss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4798 { "vaddpd", { XM
, Vex
, EXx
}, 0 },
4799 { "vaddsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4802 /* PREFIX_VEX_0F59 */
4804 { "vmulps", { XM
, Vex
, EXx
}, 0 },
4805 { "vmulss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4806 { "vmulpd", { XM
, Vex
, EXx
}, 0 },
4807 { "vmulsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4810 /* PREFIX_VEX_0F5A */
4812 { "vcvtps2pd", { XM
, EXxmmq
}, 0 },
4813 { "vcvtss2sd", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4814 { "vcvtpd2ps%XY",{ XMM
, EXx
}, 0 },
4815 { "vcvtsd2ss", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4818 /* PREFIX_VEX_0F5B */
4820 { "vcvtdq2ps", { XM
, EXx
}, 0 },
4821 { "vcvttps2dq", { XM
, EXx
}, 0 },
4822 { "vcvtps2dq", { XM
, EXx
}, 0 },
4825 /* PREFIX_VEX_0F5C */
4827 { "vsubps", { XM
, Vex
, EXx
}, 0 },
4828 { "vsubss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4829 { "vsubpd", { XM
, Vex
, EXx
}, 0 },
4830 { "vsubsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4833 /* PREFIX_VEX_0F5D */
4835 { "vminps", { XM
, Vex
, EXx
}, 0 },
4836 { "vminss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4837 { "vminpd", { XM
, Vex
, EXx
}, 0 },
4838 { "vminsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4841 /* PREFIX_VEX_0F5E */
4843 { "vdivps", { XM
, Vex
, EXx
}, 0 },
4844 { "vdivss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4845 { "vdivpd", { XM
, Vex
, EXx
}, 0 },
4846 { "vdivsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4849 /* PREFIX_VEX_0F5F */
4851 { "vmaxps", { XM
, Vex
, EXx
}, 0 },
4852 { "vmaxss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4853 { "vmaxpd", { XM
, Vex
, EXx
}, 0 },
4854 { "vmaxsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4857 /* PREFIX_VEX_0F60 */
4861 { "vpunpcklbw", { XM
, Vex
, EXx
}, 0 },
4864 /* PREFIX_VEX_0F61 */
4868 { "vpunpcklwd", { XM
, Vex
, EXx
}, 0 },
4871 /* PREFIX_VEX_0F62 */
4875 { "vpunpckldq", { XM
, Vex
, EXx
}, 0 },
4878 /* PREFIX_VEX_0F63 */
4882 { "vpacksswb", { XM
, Vex
, EXx
}, 0 },
4885 /* PREFIX_VEX_0F64 */
4889 { "vpcmpgtb", { XM
, Vex
, EXx
}, 0 },
4892 /* PREFIX_VEX_0F65 */
4896 { "vpcmpgtw", { XM
, Vex
, EXx
}, 0 },
4899 /* PREFIX_VEX_0F66 */
4903 { "vpcmpgtd", { XM
, Vex
, EXx
}, 0 },
4906 /* PREFIX_VEX_0F67 */
4910 { "vpackuswb", { XM
, Vex
, EXx
}, 0 },
4913 /* PREFIX_VEX_0F68 */
4917 { "vpunpckhbw", { XM
, Vex
, EXx
}, 0 },
4920 /* PREFIX_VEX_0F69 */
4924 { "vpunpckhwd", { XM
, Vex
, EXx
}, 0 },
4927 /* PREFIX_VEX_0F6A */
4931 { "vpunpckhdq", { XM
, Vex
, EXx
}, 0 },
4934 /* PREFIX_VEX_0F6B */
4938 { "vpackssdw", { XM
, Vex
, EXx
}, 0 },
4941 /* PREFIX_VEX_0F6C */
4945 { "vpunpcklqdq", { XM
, Vex
, EXx
}, 0 },
4948 /* PREFIX_VEX_0F6D */
4952 { "vpunpckhqdq", { XM
, Vex
, EXx
}, 0 },
4955 /* PREFIX_VEX_0F6E */
4959 { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2
) },
4962 /* PREFIX_VEX_0F6F */
4965 { "vmovdqu", { XM
, EXx
}, 0 },
4966 { "vmovdqa", { XM
, EXx
}, 0 },
4969 /* PREFIX_VEX_0F70 */
4972 { "vpshufhw", { XM
, EXx
, Ib
}, 0 },
4973 { "vpshufd", { XM
, EXx
, Ib
}, 0 },
4974 { "vpshuflw", { XM
, EXx
, Ib
}, 0 },
4977 /* PREFIX_VEX_0F71_REG_2 */
4981 { "vpsrlw", { Vex
, XS
, Ib
}, 0 },
4984 /* PREFIX_VEX_0F71_REG_4 */
4988 { "vpsraw", { Vex
, XS
, Ib
}, 0 },
4991 /* PREFIX_VEX_0F71_REG_6 */
4995 { "vpsllw", { Vex
, XS
, Ib
}, 0 },
4998 /* PREFIX_VEX_0F72_REG_2 */
5002 { "vpsrld", { Vex
, XS
, Ib
}, 0 },
5005 /* PREFIX_VEX_0F72_REG_4 */
5009 { "vpsrad", { Vex
, XS
, Ib
}, 0 },
5012 /* PREFIX_VEX_0F72_REG_6 */
5016 { "vpslld", { Vex
, XS
, Ib
}, 0 },
5019 /* PREFIX_VEX_0F73_REG_2 */
5023 { "vpsrlq", { Vex
, XS
, Ib
}, 0 },
5026 /* PREFIX_VEX_0F73_REG_3 */
5030 { "vpsrldq", { Vex
, XS
, Ib
}, 0 },
5033 /* PREFIX_VEX_0F73_REG_6 */
5037 { "vpsllq", { Vex
, XS
, Ib
}, 0 },
5040 /* PREFIX_VEX_0F73_REG_7 */
5044 { "vpslldq", { Vex
, XS
, Ib
}, 0 },
5047 /* PREFIX_VEX_0F74 */
5051 { "vpcmpeqb", { XM
, Vex
, EXx
}, 0 },
5054 /* PREFIX_VEX_0F75 */
5058 { "vpcmpeqw", { XM
, Vex
, EXx
}, 0 },
5061 /* PREFIX_VEX_0F76 */
5065 { "vpcmpeqd", { XM
, Vex
, EXx
}, 0 },
5068 /* PREFIX_VEX_0F77 */
5070 { VEX_LEN_TABLE (VEX_LEN_0F77_P_0
) },
5073 /* PREFIX_VEX_0F7C */
5077 { "vhaddpd", { XM
, Vex
, EXx
}, 0 },
5078 { "vhaddps", { XM
, Vex
, EXx
}, 0 },
5081 /* PREFIX_VEX_0F7D */
5085 { "vhsubpd", { XM
, Vex
, EXx
}, 0 },
5086 { "vhsubps", { XM
, Vex
, EXx
}, 0 },
5089 /* PREFIX_VEX_0F7E */
5092 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1
) },
5093 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2
) },
5096 /* PREFIX_VEX_0F7F */
5099 { "vmovdqu", { EXxS
, XM
}, 0 },
5100 { "vmovdqa", { EXxS
, XM
}, 0 },
5103 /* PREFIX_VEX_0F90 */
5105 { VEX_LEN_TABLE (VEX_LEN_0F90_P_0
) },
5107 { VEX_LEN_TABLE (VEX_LEN_0F90_P_2
) },
5110 /* PREFIX_VEX_0F91 */
5112 { VEX_LEN_TABLE (VEX_LEN_0F91_P_0
) },
5114 { VEX_LEN_TABLE (VEX_LEN_0F91_P_2
) },
5117 /* PREFIX_VEX_0F92 */
5119 { VEX_LEN_TABLE (VEX_LEN_0F92_P_0
) },
5121 { VEX_LEN_TABLE (VEX_LEN_0F92_P_2
) },
5122 { VEX_LEN_TABLE (VEX_LEN_0F92_P_3
) },
5125 /* PREFIX_VEX_0F93 */
5127 { VEX_LEN_TABLE (VEX_LEN_0F93_P_0
) },
5129 { VEX_LEN_TABLE (VEX_LEN_0F93_P_2
) },
5130 { VEX_LEN_TABLE (VEX_LEN_0F93_P_3
) },
5133 /* PREFIX_VEX_0F98 */
5135 { VEX_LEN_TABLE (VEX_LEN_0F98_P_0
) },
5137 { VEX_LEN_TABLE (VEX_LEN_0F98_P_2
) },
5140 /* PREFIX_VEX_0F99 */
5142 { VEX_LEN_TABLE (VEX_LEN_0F99_P_0
) },
5144 { VEX_LEN_TABLE (VEX_LEN_0F99_P_2
) },
5147 /* PREFIX_VEX_0FC2 */
5149 { "vcmpps", { XM
, Vex
, EXx
, VCMP
}, 0 },
5150 { "vcmpss", { XMScalar
, VexScalar
, EXdScalar
, VCMP
}, 0 },
5151 { "vcmppd", { XM
, Vex
, EXx
, VCMP
}, 0 },
5152 { "vcmpsd", { XMScalar
, VexScalar
, EXqScalar
, VCMP
}, 0 },
5155 /* PREFIX_VEX_0FC4 */
5159 { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2
) },
5162 /* PREFIX_VEX_0FC5 */
5166 { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2
) },
5169 /* PREFIX_VEX_0FD0 */
5173 { "vaddsubpd", { XM
, Vex
, EXx
}, 0 },
5174 { "vaddsubps", { XM
, Vex
, EXx
}, 0 },
5177 /* PREFIX_VEX_0FD1 */
5181 { "vpsrlw", { XM
, Vex
, EXxmm
}, 0 },
5184 /* PREFIX_VEX_0FD2 */
5188 { "vpsrld", { XM
, Vex
, EXxmm
}, 0 },
5191 /* PREFIX_VEX_0FD3 */
5195 { "vpsrlq", { XM
, Vex
, EXxmm
}, 0 },
5198 /* PREFIX_VEX_0FD4 */
5202 { "vpaddq", { XM
, Vex
, EXx
}, 0 },
5205 /* PREFIX_VEX_0FD5 */
5209 { "vpmullw", { XM
, Vex
, EXx
}, 0 },
5212 /* PREFIX_VEX_0FD6 */
5216 { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2
) },
5219 /* PREFIX_VEX_0FD7 */
5223 { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2
) },
5226 /* PREFIX_VEX_0FD8 */
5230 { "vpsubusb", { XM
, Vex
, EXx
}, 0 },
5233 /* PREFIX_VEX_0FD9 */
5237 { "vpsubusw", { XM
, Vex
, EXx
}, 0 },
5240 /* PREFIX_VEX_0FDA */
5244 { "vpminub", { XM
, Vex
, EXx
}, 0 },
5247 /* PREFIX_VEX_0FDB */
5251 { "vpand", { XM
, Vex
, EXx
}, 0 },
5254 /* PREFIX_VEX_0FDC */
5258 { "vpaddusb", { XM
, Vex
, EXx
}, 0 },
5261 /* PREFIX_VEX_0FDD */
5265 { "vpaddusw", { XM
, Vex
, EXx
}, 0 },
5268 /* PREFIX_VEX_0FDE */
5272 { "vpmaxub", { XM
, Vex
, EXx
}, 0 },
5275 /* PREFIX_VEX_0FDF */
5279 { "vpandn", { XM
, Vex
, EXx
}, 0 },
5282 /* PREFIX_VEX_0FE0 */
5286 { "vpavgb", { XM
, Vex
, EXx
}, 0 },
5289 /* PREFIX_VEX_0FE1 */
5293 { "vpsraw", { XM
, Vex
, EXxmm
}, 0 },
5296 /* PREFIX_VEX_0FE2 */
5300 { "vpsrad", { XM
, Vex
, EXxmm
}, 0 },
5303 /* PREFIX_VEX_0FE3 */
5307 { "vpavgw", { XM
, Vex
, EXx
}, 0 },
5310 /* PREFIX_VEX_0FE4 */
5314 { "vpmulhuw", { XM
, Vex
, EXx
}, 0 },
5317 /* PREFIX_VEX_0FE5 */
5321 { "vpmulhw", { XM
, Vex
, EXx
}, 0 },
5324 /* PREFIX_VEX_0FE6 */
5327 { "vcvtdq2pd", { XM
, EXxmmq
}, 0 },
5328 { "vcvttpd2dq%XY", { XMM
, EXx
}, 0 },
5329 { "vcvtpd2dq%XY", { XMM
, EXx
}, 0 },
5332 /* PREFIX_VEX_0FE7 */
5336 { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2
) },
5339 /* PREFIX_VEX_0FE8 */
5343 { "vpsubsb", { XM
, Vex
, EXx
}, 0 },
5346 /* PREFIX_VEX_0FE9 */
5350 { "vpsubsw", { XM
, Vex
, EXx
}, 0 },
5353 /* PREFIX_VEX_0FEA */
5357 { "vpminsw", { XM
, Vex
, EXx
}, 0 },
5360 /* PREFIX_VEX_0FEB */
5364 { "vpor", { XM
, Vex
, EXx
}, 0 },
5367 /* PREFIX_VEX_0FEC */
5371 { "vpaddsb", { XM
, Vex
, EXx
}, 0 },
5374 /* PREFIX_VEX_0FED */
5378 { "vpaddsw", { XM
, Vex
, EXx
}, 0 },
5381 /* PREFIX_VEX_0FEE */
5385 { "vpmaxsw", { XM
, Vex
, EXx
}, 0 },
5388 /* PREFIX_VEX_0FEF */
5392 { "vpxor", { XM
, Vex
, EXx
}, 0 },
5395 /* PREFIX_VEX_0FF0 */
5400 { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3
) },
5403 /* PREFIX_VEX_0FF1 */
5407 { "vpsllw", { XM
, Vex
, EXxmm
}, 0 },
5410 /* PREFIX_VEX_0FF2 */
5414 { "vpslld", { XM
, Vex
, EXxmm
}, 0 },
5417 /* PREFIX_VEX_0FF3 */
5421 { "vpsllq", { XM
, Vex
, EXxmm
}, 0 },
5424 /* PREFIX_VEX_0FF4 */
5428 { "vpmuludq", { XM
, Vex
, EXx
}, 0 },
5431 /* PREFIX_VEX_0FF5 */
5435 { "vpmaddwd", { XM
, Vex
, EXx
}, 0 },
5438 /* PREFIX_VEX_0FF6 */
5442 { "vpsadbw", { XM
, Vex
, EXx
}, 0 },
5445 /* PREFIX_VEX_0FF7 */
5449 { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2
) },
5452 /* PREFIX_VEX_0FF8 */
5456 { "vpsubb", { XM
, Vex
, EXx
}, 0 },
5459 /* PREFIX_VEX_0FF9 */
5463 { "vpsubw", { XM
, Vex
, EXx
}, 0 },
5466 /* PREFIX_VEX_0FFA */
5470 { "vpsubd", { XM
, Vex
, EXx
}, 0 },
5473 /* PREFIX_VEX_0FFB */
5477 { "vpsubq", { XM
, Vex
, EXx
}, 0 },
5480 /* PREFIX_VEX_0FFC */
5484 { "vpaddb", { XM
, Vex
, EXx
}, 0 },
5487 /* PREFIX_VEX_0FFD */
5491 { "vpaddw", { XM
, Vex
, EXx
}, 0 },
5494 /* PREFIX_VEX_0FFE */
5498 { "vpaddd", { XM
, Vex
, EXx
}, 0 },
5501 /* PREFIX_VEX_0F3800 */
5505 { "vpshufb", { XM
, Vex
, EXx
}, 0 },
5508 /* PREFIX_VEX_0F3801 */
5512 { "vphaddw", { XM
, Vex
, EXx
}, 0 },
5515 /* PREFIX_VEX_0F3802 */
5519 { "vphaddd", { XM
, Vex
, EXx
}, 0 },
5522 /* PREFIX_VEX_0F3803 */
5526 { "vphaddsw", { XM
, Vex
, EXx
}, 0 },
5529 /* PREFIX_VEX_0F3804 */
5533 { "vpmaddubsw", { XM
, Vex
, EXx
}, 0 },
5536 /* PREFIX_VEX_0F3805 */
5540 { "vphsubw", { XM
, Vex
, EXx
}, 0 },
5543 /* PREFIX_VEX_0F3806 */
5547 { "vphsubd", { XM
, Vex
, EXx
}, 0 },
5550 /* PREFIX_VEX_0F3807 */
5554 { "vphsubsw", { XM
, Vex
, EXx
}, 0 },
5557 /* PREFIX_VEX_0F3808 */
5561 { "vpsignb", { XM
, Vex
, EXx
}, 0 },
5564 /* PREFIX_VEX_0F3809 */
5568 { "vpsignw", { XM
, Vex
, EXx
}, 0 },
5571 /* PREFIX_VEX_0F380A */
5575 { "vpsignd", { XM
, Vex
, EXx
}, 0 },
5578 /* PREFIX_VEX_0F380B */
5582 { "vpmulhrsw", { XM
, Vex
, EXx
}, 0 },
5585 /* PREFIX_VEX_0F380C */
5589 { VEX_W_TABLE (VEX_W_0F380C_P_2
) },
5592 /* PREFIX_VEX_0F380D */
5596 { VEX_W_TABLE (VEX_W_0F380D_P_2
) },
5599 /* PREFIX_VEX_0F380E */
5603 { VEX_W_TABLE (VEX_W_0F380E_P_2
) },
5606 /* PREFIX_VEX_0F380F */
5610 { VEX_W_TABLE (VEX_W_0F380F_P_2
) },
5613 /* PREFIX_VEX_0F3813 */
5617 { "vcvtph2ps", { XM
, EXxmmq
}, 0 },
5620 /* PREFIX_VEX_0F3816 */
5624 { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2
) },
5627 /* PREFIX_VEX_0F3817 */
5631 { "vptest", { XM
, EXx
}, 0 },
5634 /* PREFIX_VEX_0F3818 */
5638 { VEX_W_TABLE (VEX_W_0F3818_P_2
) },
5641 /* PREFIX_VEX_0F3819 */
5645 { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2
) },
5648 /* PREFIX_VEX_0F381A */
5652 { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2
) },
5655 /* PREFIX_VEX_0F381C */
5659 { "vpabsb", { XM
, EXx
}, 0 },
5662 /* PREFIX_VEX_0F381D */
5666 { "vpabsw", { XM
, EXx
}, 0 },
5669 /* PREFIX_VEX_0F381E */
5673 { "vpabsd", { XM
, EXx
}, 0 },
5676 /* PREFIX_VEX_0F3820 */
5680 { "vpmovsxbw", { XM
, EXxmmq
}, 0 },
5683 /* PREFIX_VEX_0F3821 */
5687 { "vpmovsxbd", { XM
, EXxmmqd
}, 0 },
5690 /* PREFIX_VEX_0F3822 */
5694 { "vpmovsxbq", { XM
, EXxmmdw
}, 0 },
5697 /* PREFIX_VEX_0F3823 */
5701 { "vpmovsxwd", { XM
, EXxmmq
}, 0 },
5704 /* PREFIX_VEX_0F3824 */
5708 { "vpmovsxwq", { XM
, EXxmmqd
}, 0 },
5711 /* PREFIX_VEX_0F3825 */
5715 { "vpmovsxdq", { XM
, EXxmmq
}, 0 },
5718 /* PREFIX_VEX_0F3828 */
5722 { "vpmuldq", { XM
, Vex
, EXx
}, 0 },
5725 /* PREFIX_VEX_0F3829 */
5729 { "vpcmpeqq", { XM
, Vex
, EXx
}, 0 },
5732 /* PREFIX_VEX_0F382A */
5736 { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2
) },
5739 /* PREFIX_VEX_0F382B */
5743 { "vpackusdw", { XM
, Vex
, EXx
}, 0 },
5746 /* PREFIX_VEX_0F382C */
5750 { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2
) },
5753 /* PREFIX_VEX_0F382D */
5757 { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2
) },
5760 /* PREFIX_VEX_0F382E */
5764 { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2
) },
5767 /* PREFIX_VEX_0F382F */
5771 { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2
) },
5774 /* PREFIX_VEX_0F3830 */
5778 { "vpmovzxbw", { XM
, EXxmmq
}, 0 },
5781 /* PREFIX_VEX_0F3831 */
5785 { "vpmovzxbd", { XM
, EXxmmqd
}, 0 },
5788 /* PREFIX_VEX_0F3832 */
5792 { "vpmovzxbq", { XM
, EXxmmdw
}, 0 },
5795 /* PREFIX_VEX_0F3833 */
5799 { "vpmovzxwd", { XM
, EXxmmq
}, 0 },
5802 /* PREFIX_VEX_0F3834 */
5806 { "vpmovzxwq", { XM
, EXxmmqd
}, 0 },
5809 /* PREFIX_VEX_0F3835 */
5813 { "vpmovzxdq", { XM
, EXxmmq
}, 0 },
5816 /* PREFIX_VEX_0F3836 */
5820 { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2
) },
5823 /* PREFIX_VEX_0F3837 */
5827 { "vpcmpgtq", { XM
, Vex
, EXx
}, 0 },
5830 /* PREFIX_VEX_0F3838 */
5834 { "vpminsb", { XM
, Vex
, EXx
}, 0 },
5837 /* PREFIX_VEX_0F3839 */
5841 { "vpminsd", { XM
, Vex
, EXx
}, 0 },
5844 /* PREFIX_VEX_0F383A */
5848 { "vpminuw", { XM
, Vex
, EXx
}, 0 },
5851 /* PREFIX_VEX_0F383B */
5855 { "vpminud", { XM
, Vex
, EXx
}, 0 },
5858 /* PREFIX_VEX_0F383C */
5862 { "vpmaxsb", { XM
, Vex
, EXx
}, 0 },
5865 /* PREFIX_VEX_0F383D */
5869 { "vpmaxsd", { XM
, Vex
, EXx
}, 0 },
5872 /* PREFIX_VEX_0F383E */
5876 { "vpmaxuw", { XM
, Vex
, EXx
}, 0 },
5879 /* PREFIX_VEX_0F383F */
5883 { "vpmaxud", { XM
, Vex
, EXx
}, 0 },
5886 /* PREFIX_VEX_0F3840 */
5890 { "vpmulld", { XM
, Vex
, EXx
}, 0 },
5893 /* PREFIX_VEX_0F3841 */
5897 { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2
) },
5900 /* PREFIX_VEX_0F3845 */
5904 { "vpsrlv%LW", { XM
, Vex
, EXx
}, 0 },
5907 /* PREFIX_VEX_0F3846 */
5911 { VEX_W_TABLE (VEX_W_0F3846_P_2
) },
5914 /* PREFIX_VEX_0F3847 */
5918 { "vpsllv%LW", { XM
, Vex
, EXx
}, 0 },
5921 /* PREFIX_VEX_0F3858 */
5925 { VEX_W_TABLE (VEX_W_0F3858_P_2
) },
5928 /* PREFIX_VEX_0F3859 */
5932 { VEX_W_TABLE (VEX_W_0F3859_P_2
) },
5935 /* PREFIX_VEX_0F385A */
5939 { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2
) },
5942 /* PREFIX_VEX_0F3878 */
5946 { VEX_W_TABLE (VEX_W_0F3878_P_2
) },
5949 /* PREFIX_VEX_0F3879 */
5953 { VEX_W_TABLE (VEX_W_0F3879_P_2
) },
5956 /* PREFIX_VEX_0F388C */
5960 { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2
) },
5963 /* PREFIX_VEX_0F388E */
5967 { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2
) },
5970 /* PREFIX_VEX_0F3890 */
5974 { "vpgatherd%LW", { XM
, MVexVSIBDWpX
, Vex
}, 0 },
5977 /* PREFIX_VEX_0F3891 */
5981 { "vpgatherq%LW", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
}, 0 },
5984 /* PREFIX_VEX_0F3892 */
5988 { "vgatherdp%XW", { XM
, MVexVSIBDWpX
, Vex
}, 0 },
5991 /* PREFIX_VEX_0F3893 */
5995 { "vgatherqp%XW", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
}, 0 },
5998 /* PREFIX_VEX_0F3896 */
6002 { "vfmaddsub132p%XW", { XM
, Vex
, EXx
}, 0 },
6005 /* PREFIX_VEX_0F3897 */
6009 { "vfmsubadd132p%XW", { XM
, Vex
, EXx
}, 0 },
6012 /* PREFIX_VEX_0F3898 */
6016 { "vfmadd132p%XW", { XM
, Vex
, EXx
}, 0 },
6019 /* PREFIX_VEX_0F3899 */
6023 { "vfmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6026 /* PREFIX_VEX_0F389A */
6030 { "vfmsub132p%XW", { XM
, Vex
, EXx
}, 0 },
6033 /* PREFIX_VEX_0F389B */
6037 { "vfmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6040 /* PREFIX_VEX_0F389C */
6044 { "vfnmadd132p%XW", { XM
, Vex
, EXx
}, 0 },
6047 /* PREFIX_VEX_0F389D */
6051 { "vfnmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6054 /* PREFIX_VEX_0F389E */
6058 { "vfnmsub132p%XW", { XM
, Vex
, EXx
}, 0 },
6061 /* PREFIX_VEX_0F389F */
6065 { "vfnmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6068 /* PREFIX_VEX_0F38A6 */
6072 { "vfmaddsub213p%XW", { XM
, Vex
, EXx
}, 0 },
6076 /* PREFIX_VEX_0F38A7 */
6080 { "vfmsubadd213p%XW", { XM
, Vex
, EXx
}, 0 },
6083 /* PREFIX_VEX_0F38A8 */
6087 { "vfmadd213p%XW", { XM
, Vex
, EXx
}, 0 },
6090 /* PREFIX_VEX_0F38A9 */
6094 { "vfmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6097 /* PREFIX_VEX_0F38AA */
6101 { "vfmsub213p%XW", { XM
, Vex
, EXx
}, 0 },
6104 /* PREFIX_VEX_0F38AB */
6108 { "vfmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6111 /* PREFIX_VEX_0F38AC */
6115 { "vfnmadd213p%XW", { XM
, Vex
, EXx
}, 0 },
6118 /* PREFIX_VEX_0F38AD */
6122 { "vfnmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6125 /* PREFIX_VEX_0F38AE */
6129 { "vfnmsub213p%XW", { XM
, Vex
, EXx
}, 0 },
6132 /* PREFIX_VEX_0F38AF */
6136 { "vfnmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6139 /* PREFIX_VEX_0F38B6 */
6143 { "vfmaddsub231p%XW", { XM
, Vex
, EXx
}, 0 },
6146 /* PREFIX_VEX_0F38B7 */
6150 { "vfmsubadd231p%XW", { XM
, Vex
, EXx
}, 0 },
6153 /* PREFIX_VEX_0F38B8 */
6157 { "vfmadd231p%XW", { XM
, Vex
, EXx
}, 0 },
6160 /* PREFIX_VEX_0F38B9 */
6164 { "vfmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6167 /* PREFIX_VEX_0F38BA */
6171 { "vfmsub231p%XW", { XM
, Vex
, EXx
}, 0 },
6174 /* PREFIX_VEX_0F38BB */
6178 { "vfmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6181 /* PREFIX_VEX_0F38BC */
6185 { "vfnmadd231p%XW", { XM
, Vex
, EXx
}, 0 },
6188 /* PREFIX_VEX_0F38BD */
6192 { "vfnmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6195 /* PREFIX_VEX_0F38BE */
6199 { "vfnmsub231p%XW", { XM
, Vex
, EXx
}, 0 },
6202 /* PREFIX_VEX_0F38BF */
6206 { "vfnmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6209 /* PREFIX_VEX_0F38CF */
6213 { VEX_W_TABLE (VEX_W_0F38CF_P_2
) },
6216 /* PREFIX_VEX_0F38DB */
6220 { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2
) },
6223 /* PREFIX_VEX_0F38DC */
6227 { "vaesenc", { XM
, Vex
, EXx
}, 0 },
6230 /* PREFIX_VEX_0F38DD */
6234 { "vaesenclast", { XM
, Vex
, EXx
}, 0 },
6237 /* PREFIX_VEX_0F38DE */
6241 { "vaesdec", { XM
, Vex
, EXx
}, 0 },
6244 /* PREFIX_VEX_0F38DF */
6248 { "vaesdeclast", { XM
, Vex
, EXx
}, 0 },
6251 /* PREFIX_VEX_0F38F2 */
6253 { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0
) },
6256 /* PREFIX_VEX_0F38F3_REG_1 */
6258 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0
) },
6261 /* PREFIX_VEX_0F38F3_REG_2 */
6263 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0
) },
6266 /* PREFIX_VEX_0F38F3_REG_3 */
6268 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0
) },
6271 /* PREFIX_VEX_0F38F5 */
6273 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0
) },
6274 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1
) },
6276 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3
) },
6279 /* PREFIX_VEX_0F38F6 */
6284 { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3
) },
6287 /* PREFIX_VEX_0F38F7 */
6289 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0
) },
6290 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1
) },
6291 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2
) },
6292 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3
) },
6295 /* PREFIX_VEX_0F3A00 */
6299 { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2
) },
6302 /* PREFIX_VEX_0F3A01 */
6306 { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2
) },
6309 /* PREFIX_VEX_0F3A02 */
6313 { VEX_W_TABLE (VEX_W_0F3A02_P_2
) },
6316 /* PREFIX_VEX_0F3A04 */
6320 { VEX_W_TABLE (VEX_W_0F3A04_P_2
) },
6323 /* PREFIX_VEX_0F3A05 */
6327 { VEX_W_TABLE (VEX_W_0F3A05_P_2
) },
6330 /* PREFIX_VEX_0F3A06 */
6334 { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2
) },
6337 /* PREFIX_VEX_0F3A08 */
6341 { "vroundps", { XM
, EXx
, Ib
}, 0 },
6344 /* PREFIX_VEX_0F3A09 */
6348 { "vroundpd", { XM
, EXx
, Ib
}, 0 },
6351 /* PREFIX_VEX_0F3A0A */
6355 { "vroundss", { XMScalar
, VexScalar
, EXdScalar
, Ib
}, 0 },
6358 /* PREFIX_VEX_0F3A0B */
6362 { "vroundsd", { XMScalar
, VexScalar
, EXqScalar
, Ib
}, 0 },
6365 /* PREFIX_VEX_0F3A0C */
6369 { "vblendps", { XM
, Vex
, EXx
, Ib
}, 0 },
6372 /* PREFIX_VEX_0F3A0D */
6376 { "vblendpd", { XM
, Vex
, EXx
, Ib
}, 0 },
6379 /* PREFIX_VEX_0F3A0E */
6383 { "vpblendw", { XM
, Vex
, EXx
, Ib
}, 0 },
6386 /* PREFIX_VEX_0F3A0F */
6390 { "vpalignr", { XM
, Vex
, EXx
, Ib
}, 0 },
6393 /* PREFIX_VEX_0F3A14 */
6397 { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2
) },
6400 /* PREFIX_VEX_0F3A15 */
6404 { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2
) },
6407 /* PREFIX_VEX_0F3A16 */
6411 { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2
) },
6414 /* PREFIX_VEX_0F3A17 */
6418 { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2
) },
6421 /* PREFIX_VEX_0F3A18 */
6425 { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2
) },
6428 /* PREFIX_VEX_0F3A19 */
6432 { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2
) },
6435 /* PREFIX_VEX_0F3A1D */
6439 { "vcvtps2ph", { EXxmmq
, XM
, Ib
}, 0 },
6442 /* PREFIX_VEX_0F3A20 */
6446 { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2
) },
6449 /* PREFIX_VEX_0F3A21 */
6453 { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2
) },
6456 /* PREFIX_VEX_0F3A22 */
6460 { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2
) },
6463 /* PREFIX_VEX_0F3A30 */
6467 { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2
) },
6470 /* PREFIX_VEX_0F3A31 */
6474 { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2
) },
6477 /* PREFIX_VEX_0F3A32 */
6481 { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2
) },
6484 /* PREFIX_VEX_0F3A33 */
6488 { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2
) },
6491 /* PREFIX_VEX_0F3A38 */
6495 { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2
) },
6498 /* PREFIX_VEX_0F3A39 */
6502 { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2
) },
6505 /* PREFIX_VEX_0F3A40 */
6509 { "vdpps", { XM
, Vex
, EXx
, Ib
}, 0 },
6512 /* PREFIX_VEX_0F3A41 */
6516 { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2
) },
6519 /* PREFIX_VEX_0F3A42 */
6523 { "vmpsadbw", { XM
, Vex
, EXx
, Ib
}, 0 },
6526 /* PREFIX_VEX_0F3A44 */
6530 { "vpclmulqdq", { XM
, Vex
, EXx
, PCLMUL
}, 0 },
6533 /* PREFIX_VEX_0F3A46 */
6537 { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2
) },
6540 /* PREFIX_VEX_0F3A48 */
6544 { VEX_W_TABLE (VEX_W_0F3A48_P_2
) },
6547 /* PREFIX_VEX_0F3A49 */
6551 { VEX_W_TABLE (VEX_W_0F3A49_P_2
) },
6554 /* PREFIX_VEX_0F3A4A */
6558 { VEX_W_TABLE (VEX_W_0F3A4A_P_2
) },
6561 /* PREFIX_VEX_0F3A4B */
6565 { VEX_W_TABLE (VEX_W_0F3A4B_P_2
) },
6568 /* PREFIX_VEX_0F3A4C */
6572 { VEX_W_TABLE (VEX_W_0F3A4C_P_2
) },
6575 /* PREFIX_VEX_0F3A5C */
6579 { "vfmaddsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6582 /* PREFIX_VEX_0F3A5D */
6586 { "vfmaddsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6589 /* PREFIX_VEX_0F3A5E */
6593 { "vfmsubaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6596 /* PREFIX_VEX_0F3A5F */
6600 { "vfmsubaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6603 /* PREFIX_VEX_0F3A60 */
6607 { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2
) },
6611 /* PREFIX_VEX_0F3A61 */
6615 { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2
) },
6618 /* PREFIX_VEX_0F3A62 */
6622 { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2
) },
6625 /* PREFIX_VEX_0F3A63 */
6629 { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2
) },
6632 /* PREFIX_VEX_0F3A68 */
6636 { "vfmaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6639 /* PREFIX_VEX_0F3A69 */
6643 { "vfmaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6646 /* PREFIX_VEX_0F3A6A */
6650 { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2
) },
6653 /* PREFIX_VEX_0F3A6B */
6657 { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2
) },
6660 /* PREFIX_VEX_0F3A6C */
6664 { "vfmsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6667 /* PREFIX_VEX_0F3A6D */
6671 { "vfmsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6674 /* PREFIX_VEX_0F3A6E */
6678 { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2
) },
6681 /* PREFIX_VEX_0F3A6F */
6685 { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2
) },
6688 /* PREFIX_VEX_0F3A78 */
6692 { "vfnmaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6695 /* PREFIX_VEX_0F3A79 */
6699 { "vfnmaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6702 /* PREFIX_VEX_0F3A7A */
6706 { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2
) },
6709 /* PREFIX_VEX_0F3A7B */
6713 { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2
) },
6716 /* PREFIX_VEX_0F3A7C */
6720 { "vfnmsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6724 /* PREFIX_VEX_0F3A7D */
6728 { "vfnmsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6731 /* PREFIX_VEX_0F3A7E */
6735 { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2
) },
6738 /* PREFIX_VEX_0F3A7F */
6742 { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2
) },
6745 /* PREFIX_VEX_0F3ACE */
6749 { VEX_W_TABLE (VEX_W_0F3ACE_P_2
) },
6752 /* PREFIX_VEX_0F3ACF */
6756 { VEX_W_TABLE (VEX_W_0F3ACF_P_2
) },
6759 /* PREFIX_VEX_0F3ADF */
6763 { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2
) },
6766 /* PREFIX_VEX_0F3AF0 */
6771 { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3
) },
6774 #define NEED_PREFIX_TABLE
6775 #include "i386-dis-evex.h"
6776 #undef NEED_PREFIX_TABLE
6779 static const struct dis386 x86_64_table
[][2] = {
6782 { "pushP", { es
}, 0 },
6787 { "popP", { es
}, 0 },
6792 { "pushP", { cs
}, 0 },
6797 { "pushP", { ss
}, 0 },
6802 { "popP", { ss
}, 0 },
6807 { "pushP", { ds
}, 0 },
6812 { "popP", { ds
}, 0 },
6817 { "daa", { XX
}, 0 },
6822 { "das", { XX
}, 0 },
6827 { "aaa", { XX
}, 0 },
6832 { "aas", { XX
}, 0 },
6837 { "pushaP", { XX
}, 0 },
6842 { "popaP", { XX
}, 0 },
6847 { MOD_TABLE (MOD_62_32BIT
) },
6848 { EVEX_TABLE (EVEX_0F
) },
6853 { "arpl", { Ew
, Gw
}, 0 },
6854 { "movs{lq|xd}", { Gv
, Ed
}, 0 },
6859 { "ins{R|}", { Yzr
, indirDX
}, 0 },
6860 { "ins{G|}", { Yzr
, indirDX
}, 0 },
6865 { "outs{R|}", { indirDXr
, Xz
}, 0 },
6866 { "outs{G|}", { indirDXr
, Xz
}, 0 },
6871 /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode. */
6872 { REG_TABLE (REG_80
) },
6877 { "Jcall{T|}", { Ap
}, 0 },
6882 { MOD_TABLE (MOD_C4_32BIT
) },
6883 { VEX_C4_TABLE (VEX_0F
) },
6888 { MOD_TABLE (MOD_C5_32BIT
) },
6889 { VEX_C5_TABLE (VEX_0F
) },
6894 { "into", { XX
}, 0 },
6899 { "aam", { Ib
}, 0 },
6904 { "aad", { Ib
}, 0 },
6909 { "callP", { Jv
, BND
}, 0 },
6910 { "call@", { Jv
, BND
}, 0 }
6915 { "jmpP", { Jv
, BND
}, 0 },
6916 { "jmp@", { Jv
, BND
}, 0 }
6921 { "Jjmp{T|}", { Ap
}, 0 },
6924 /* X86_64_0F01_REG_0 */
6926 { "sgdt{Q|IQ}", { M
}, 0 },
6927 { "sgdt", { M
}, 0 },
6930 /* X86_64_0F01_REG_1 */
6932 { "sidt{Q|IQ}", { M
}, 0 },
6933 { "sidt", { M
}, 0 },
6936 /* X86_64_0F01_REG_2 */
6938 { "lgdt{Q|Q}", { M
}, 0 },
6939 { "lgdt", { M
}, 0 },
6942 /* X86_64_0F01_REG_3 */
6944 { "lidt{Q|Q}", { M
}, 0 },
6945 { "lidt", { M
}, 0 },
6949 static const struct dis386 three_byte_table
[][256] = {
6951 /* THREE_BYTE_0F38 */
6954 { "pshufb", { MX
, EM
}, PREFIX_OPCODE
},
6955 { "phaddw", { MX
, EM
}, PREFIX_OPCODE
},
6956 { "phaddd", { MX
, EM
}, PREFIX_OPCODE
},
6957 { "phaddsw", { MX
, EM
}, PREFIX_OPCODE
},
6958 { "pmaddubsw", { MX
, EM
}, PREFIX_OPCODE
},
6959 { "phsubw", { MX
, EM
}, PREFIX_OPCODE
},
6960 { "phsubd", { MX
, EM
}, PREFIX_OPCODE
},
6961 { "phsubsw", { MX
, EM
}, PREFIX_OPCODE
},
6963 { "psignb", { MX
, EM
}, PREFIX_OPCODE
},
6964 { "psignw", { MX
, EM
}, PREFIX_OPCODE
},
6965 { "psignd", { MX
, EM
}, PREFIX_OPCODE
},
6966 { "pmulhrsw", { MX
, EM
}, PREFIX_OPCODE
},
6972 { PREFIX_TABLE (PREFIX_0F3810
) },
6976 { PREFIX_TABLE (PREFIX_0F3814
) },
6977 { PREFIX_TABLE (PREFIX_0F3815
) },
6979 { PREFIX_TABLE (PREFIX_0F3817
) },
6985 { "pabsb", { MX
, EM
}, PREFIX_OPCODE
},
6986 { "pabsw", { MX
, EM
}, PREFIX_OPCODE
},
6987 { "pabsd", { MX
, EM
}, PREFIX_OPCODE
},
6990 { PREFIX_TABLE (PREFIX_0F3820
) },
6991 { PREFIX_TABLE (PREFIX_0F3821
) },
6992 { PREFIX_TABLE (PREFIX_0F3822
) },
6993 { PREFIX_TABLE (PREFIX_0F3823
) },
6994 { PREFIX_TABLE (PREFIX_0F3824
) },
6995 { PREFIX_TABLE (PREFIX_0F3825
) },
6999 { PREFIX_TABLE (PREFIX_0F3828
) },
7000 { PREFIX_TABLE (PREFIX_0F3829
) },
7001 { PREFIX_TABLE (PREFIX_0F382A
) },
7002 { PREFIX_TABLE (PREFIX_0F382B
) },
7008 { PREFIX_TABLE (PREFIX_0F3830
) },
7009 { PREFIX_TABLE (PREFIX_0F3831
) },
7010 { PREFIX_TABLE (PREFIX_0F3832
) },
7011 { PREFIX_TABLE (PREFIX_0F3833
) },
7012 { PREFIX_TABLE (PREFIX_0F3834
) },
7013 { PREFIX_TABLE (PREFIX_0F3835
) },
7015 { PREFIX_TABLE (PREFIX_0F3837
) },
7017 { PREFIX_TABLE (PREFIX_0F3838
) },
7018 { PREFIX_TABLE (PREFIX_0F3839
) },
7019 { PREFIX_TABLE (PREFIX_0F383A
) },
7020 { PREFIX_TABLE (PREFIX_0F383B
) },
7021 { PREFIX_TABLE (PREFIX_0F383C
) },
7022 { PREFIX_TABLE (PREFIX_0F383D
) },
7023 { PREFIX_TABLE (PREFIX_0F383E
) },
7024 { PREFIX_TABLE (PREFIX_0F383F
) },
7026 { PREFIX_TABLE (PREFIX_0F3840
) },
7027 { PREFIX_TABLE (PREFIX_0F3841
) },
7098 { PREFIX_TABLE (PREFIX_0F3880
) },
7099 { PREFIX_TABLE (PREFIX_0F3881
) },
7100 { PREFIX_TABLE (PREFIX_0F3882
) },
7179 { PREFIX_TABLE (PREFIX_0F38C8
) },
7180 { PREFIX_TABLE (PREFIX_0F38C9
) },
7181 { PREFIX_TABLE (PREFIX_0F38CA
) },
7182 { PREFIX_TABLE (PREFIX_0F38CB
) },
7183 { PREFIX_TABLE (PREFIX_0F38CC
) },
7184 { PREFIX_TABLE (PREFIX_0F38CD
) },
7186 { PREFIX_TABLE (PREFIX_0F38CF
) },
7200 { PREFIX_TABLE (PREFIX_0F38DB
) },
7201 { PREFIX_TABLE (PREFIX_0F38DC
) },
7202 { PREFIX_TABLE (PREFIX_0F38DD
) },
7203 { PREFIX_TABLE (PREFIX_0F38DE
) },
7204 { PREFIX_TABLE (PREFIX_0F38DF
) },
7224 { PREFIX_TABLE (PREFIX_0F38F0
) },
7225 { PREFIX_TABLE (PREFIX_0F38F1
) },
7229 { PREFIX_TABLE (PREFIX_0F38F5
) },
7230 { PREFIX_TABLE (PREFIX_0F38F6
) },
7233 { PREFIX_TABLE (PREFIX_0F38F8
) },
7234 { PREFIX_TABLE (PREFIX_0F38F9
) },
7242 /* THREE_BYTE_0F3A */
7254 { PREFIX_TABLE (PREFIX_0F3A08
) },
7255 { PREFIX_TABLE (PREFIX_0F3A09
) },
7256 { PREFIX_TABLE (PREFIX_0F3A0A
) },
7257 { PREFIX_TABLE (PREFIX_0F3A0B
) },
7258 { PREFIX_TABLE (PREFIX_0F3A0C
) },
7259 { PREFIX_TABLE (PREFIX_0F3A0D
) },
7260 { PREFIX_TABLE (PREFIX_0F3A0E
) },
7261 { "palignr", { MX
, EM
, Ib
}, PREFIX_OPCODE
},
7267 { PREFIX_TABLE (PREFIX_0F3A14
) },
7268 { PREFIX_TABLE (PREFIX_0F3A15
) },
7269 { PREFIX_TABLE (PREFIX_0F3A16
) },
7270 { PREFIX_TABLE (PREFIX_0F3A17
) },
7281 { PREFIX_TABLE (PREFIX_0F3A20
) },
7282 { PREFIX_TABLE (PREFIX_0F3A21
) },
7283 { PREFIX_TABLE (PREFIX_0F3A22
) },
7317 { PREFIX_TABLE (PREFIX_0F3A40
) },
7318 { PREFIX_TABLE (PREFIX_0F3A41
) },
7319 { PREFIX_TABLE (PREFIX_0F3A42
) },
7321 { PREFIX_TABLE (PREFIX_0F3A44
) },
7353 { PREFIX_TABLE (PREFIX_0F3A60
) },
7354 { PREFIX_TABLE (PREFIX_0F3A61
) },
7355 { PREFIX_TABLE (PREFIX_0F3A62
) },
7356 { PREFIX_TABLE (PREFIX_0F3A63
) },
7474 { PREFIX_TABLE (PREFIX_0F3ACC
) },
7476 { PREFIX_TABLE (PREFIX_0F3ACE
) },
7477 { PREFIX_TABLE (PREFIX_0F3ACF
) },
7495 { PREFIX_TABLE (PREFIX_0F3ADF
) },
7535 static const struct dis386 xop_table
[][256] = {
7688 { "vpmacssww", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7689 { "vpmacsswd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7690 { "vpmacssdql", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7698 { "vpmacssdd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7699 { "vpmacssdqh", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7706 { "vpmacsww", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7707 { "vpmacswd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7708 { "vpmacsdql", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7716 { "vpmacsdd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7717 { "vpmacsdqh", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7721 { "vpcmov", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7722 { "vpperm", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7725 { "vpmadcsswd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7743 { "vpmadcswd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7755 { "vprotb", { XM
, Vex_2src_1
, Ib
}, 0 },
7756 { "vprotw", { XM
, Vex_2src_1
, Ib
}, 0 },
7757 { "vprotd", { XM
, Vex_2src_1
, Ib
}, 0 },
7758 { "vprotq", { XM
, Vex_2src_1
, Ib
}, 0 },
7768 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC
) },
7769 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD
) },
7770 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE
) },
7771 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF
) },
7804 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC
) },
7805 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED
) },
7806 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE
) },
7807 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF
) },
7831 { REG_TABLE (REG_XOP_TBM_01
) },
7832 { REG_TABLE (REG_XOP_TBM_02
) },
7850 { REG_TABLE (REG_XOP_LWPCB
) },
7974 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80
) },
7975 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81
) },
7976 { "vfrczss", { XM
, EXd
}, 0 },
7977 { "vfrczsd", { XM
, EXq
}, 0 },
7992 { "vprotb", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7993 { "vprotw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7994 { "vprotd", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7995 { "vprotq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7996 { "vpshlb", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7997 { "vpshlw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7998 { "vpshld", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7999 { "vpshlq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8001 { "vpshab", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8002 { "vpshaw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8003 { "vpshad", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8004 { "vpshaq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8047 { "vphaddbw", { XM
, EXxmm
}, 0 },
8048 { "vphaddbd", { XM
, EXxmm
}, 0 },
8049 { "vphaddbq", { XM
, EXxmm
}, 0 },
8052 { "vphaddwd", { XM
, EXxmm
}, 0 },
8053 { "vphaddwq", { XM
, EXxmm
}, 0 },
8058 { "vphadddq", { XM
, EXxmm
}, 0 },
8065 { "vphaddubw", { XM
, EXxmm
}, 0 },
8066 { "vphaddubd", { XM
, EXxmm
}, 0 },
8067 { "vphaddubq", { XM
, EXxmm
}, 0 },
8070 { "vphadduwd", { XM
, EXxmm
}, 0 },
8071 { "vphadduwq", { XM
, EXxmm
}, 0 },
8076 { "vphaddudq", { XM
, EXxmm
}, 0 },
8083 { "vphsubbw", { XM
, EXxmm
}, 0 },
8084 { "vphsubwd", { XM
, EXxmm
}, 0 },
8085 { "vphsubdq", { XM
, EXxmm
}, 0 },
8139 { "bextr", { Gv
, Ev
, Iq
}, 0 },
8141 { REG_TABLE (REG_XOP_LWP
) },
8411 static const struct dis386 vex_table
[][256] = {
8433 { PREFIX_TABLE (PREFIX_VEX_0F10
) },
8434 { PREFIX_TABLE (PREFIX_VEX_0F11
) },
8435 { PREFIX_TABLE (PREFIX_VEX_0F12
) },
8436 { MOD_TABLE (MOD_VEX_0F13
) },
8437 { "vunpcklpX", { XM
, Vex
, EXx
}, 0 },
8438 { "vunpckhpX", { XM
, Vex
, EXx
}, 0 },
8439 { PREFIX_TABLE (PREFIX_VEX_0F16
) },
8440 { MOD_TABLE (MOD_VEX_0F17
) },
8460 { "vmovapX", { XM
, EXx
}, 0 },
8461 { "vmovapX", { EXxS
, XM
}, 0 },
8462 { PREFIX_TABLE (PREFIX_VEX_0F2A
) },
8463 { MOD_TABLE (MOD_VEX_0F2B
) },
8464 { PREFIX_TABLE (PREFIX_VEX_0F2C
) },
8465 { PREFIX_TABLE (PREFIX_VEX_0F2D
) },
8466 { PREFIX_TABLE (PREFIX_VEX_0F2E
) },
8467 { PREFIX_TABLE (PREFIX_VEX_0F2F
) },
8488 { PREFIX_TABLE (PREFIX_VEX_0F41
) },
8489 { PREFIX_TABLE (PREFIX_VEX_0F42
) },
8491 { PREFIX_TABLE (PREFIX_VEX_0F44
) },
8492 { PREFIX_TABLE (PREFIX_VEX_0F45
) },
8493 { PREFIX_TABLE (PREFIX_VEX_0F46
) },
8494 { PREFIX_TABLE (PREFIX_VEX_0F47
) },
8498 { PREFIX_TABLE (PREFIX_VEX_0F4A
) },
8499 { PREFIX_TABLE (PREFIX_VEX_0F4B
) },
8505 { MOD_TABLE (MOD_VEX_0F50
) },
8506 { PREFIX_TABLE (PREFIX_VEX_0F51
) },
8507 { PREFIX_TABLE (PREFIX_VEX_0F52
) },
8508 { PREFIX_TABLE (PREFIX_VEX_0F53
) },
8509 { "vandpX", { XM
, Vex
, EXx
}, 0 },
8510 { "vandnpX", { XM
, Vex
, EXx
}, 0 },
8511 { "vorpX", { XM
, Vex
, EXx
}, 0 },
8512 { "vxorpX", { XM
, Vex
, EXx
}, 0 },
8514 { PREFIX_TABLE (PREFIX_VEX_0F58
) },
8515 { PREFIX_TABLE (PREFIX_VEX_0F59
) },
8516 { PREFIX_TABLE (PREFIX_VEX_0F5A
) },
8517 { PREFIX_TABLE (PREFIX_VEX_0F5B
) },
8518 { PREFIX_TABLE (PREFIX_VEX_0F5C
) },
8519 { PREFIX_TABLE (PREFIX_VEX_0F5D
) },
8520 { PREFIX_TABLE (PREFIX_VEX_0F5E
) },
8521 { PREFIX_TABLE (PREFIX_VEX_0F5F
) },
8523 { PREFIX_TABLE (PREFIX_VEX_0F60
) },
8524 { PREFIX_TABLE (PREFIX_VEX_0F61
) },
8525 { PREFIX_TABLE (PREFIX_VEX_0F62
) },
8526 { PREFIX_TABLE (PREFIX_VEX_0F63
) },
8527 { PREFIX_TABLE (PREFIX_VEX_0F64
) },
8528 { PREFIX_TABLE (PREFIX_VEX_0F65
) },
8529 { PREFIX_TABLE (PREFIX_VEX_0F66
) },
8530 { PREFIX_TABLE (PREFIX_VEX_0F67
) },
8532 { PREFIX_TABLE (PREFIX_VEX_0F68
) },
8533 { PREFIX_TABLE (PREFIX_VEX_0F69
) },
8534 { PREFIX_TABLE (PREFIX_VEX_0F6A
) },
8535 { PREFIX_TABLE (PREFIX_VEX_0F6B
) },
8536 { PREFIX_TABLE (PREFIX_VEX_0F6C
) },
8537 { PREFIX_TABLE (PREFIX_VEX_0F6D
) },
8538 { PREFIX_TABLE (PREFIX_VEX_0F6E
) },
8539 { PREFIX_TABLE (PREFIX_VEX_0F6F
) },
8541 { PREFIX_TABLE (PREFIX_VEX_0F70
) },
8542 { REG_TABLE (REG_VEX_0F71
) },
8543 { REG_TABLE (REG_VEX_0F72
) },
8544 { REG_TABLE (REG_VEX_0F73
) },
8545 { PREFIX_TABLE (PREFIX_VEX_0F74
) },
8546 { PREFIX_TABLE (PREFIX_VEX_0F75
) },
8547 { PREFIX_TABLE (PREFIX_VEX_0F76
) },
8548 { PREFIX_TABLE (PREFIX_VEX_0F77
) },
8554 { PREFIX_TABLE (PREFIX_VEX_0F7C
) },
8555 { PREFIX_TABLE (PREFIX_VEX_0F7D
) },
8556 { PREFIX_TABLE (PREFIX_VEX_0F7E
) },
8557 { PREFIX_TABLE (PREFIX_VEX_0F7F
) },
8577 { PREFIX_TABLE (PREFIX_VEX_0F90
) },
8578 { PREFIX_TABLE (PREFIX_VEX_0F91
) },
8579 { PREFIX_TABLE (PREFIX_VEX_0F92
) },
8580 { PREFIX_TABLE (PREFIX_VEX_0F93
) },
8586 { PREFIX_TABLE (PREFIX_VEX_0F98
) },
8587 { PREFIX_TABLE (PREFIX_VEX_0F99
) },
8610 { REG_TABLE (REG_VEX_0FAE
) },
8633 { PREFIX_TABLE (PREFIX_VEX_0FC2
) },
8635 { PREFIX_TABLE (PREFIX_VEX_0FC4
) },
8636 { PREFIX_TABLE (PREFIX_VEX_0FC5
) },
8637 { "vshufpX", { XM
, Vex
, EXx
, Ib
}, 0 },
8649 { PREFIX_TABLE (PREFIX_VEX_0FD0
) },
8650 { PREFIX_TABLE (PREFIX_VEX_0FD1
) },
8651 { PREFIX_TABLE (PREFIX_VEX_0FD2
) },
8652 { PREFIX_TABLE (PREFIX_VEX_0FD3
) },
8653 { PREFIX_TABLE (PREFIX_VEX_0FD4
) },
8654 { PREFIX_TABLE (PREFIX_VEX_0FD5
) },
8655 { PREFIX_TABLE (PREFIX_VEX_0FD6
) },
8656 { PREFIX_TABLE (PREFIX_VEX_0FD7
) },
8658 { PREFIX_TABLE (PREFIX_VEX_0FD8
) },
8659 { PREFIX_TABLE (PREFIX_VEX_0FD9
) },
8660 { PREFIX_TABLE (PREFIX_VEX_0FDA
) },
8661 { PREFIX_TABLE (PREFIX_VEX_0FDB
) },
8662 { PREFIX_TABLE (PREFIX_VEX_0FDC
) },
8663 { PREFIX_TABLE (PREFIX_VEX_0FDD
) },
8664 { PREFIX_TABLE (PREFIX_VEX_0FDE
) },
8665 { PREFIX_TABLE (PREFIX_VEX_0FDF
) },
8667 { PREFIX_TABLE (PREFIX_VEX_0FE0
) },
8668 { PREFIX_TABLE (PREFIX_VEX_0FE1
) },
8669 { PREFIX_TABLE (PREFIX_VEX_0FE2
) },
8670 { PREFIX_TABLE (PREFIX_VEX_0FE3
) },
8671 { PREFIX_TABLE (PREFIX_VEX_0FE4
) },
8672 { PREFIX_TABLE (PREFIX_VEX_0FE5
) },
8673 { PREFIX_TABLE (PREFIX_VEX_0FE6
) },
8674 { PREFIX_TABLE (PREFIX_VEX_0FE7
) },
8676 { PREFIX_TABLE (PREFIX_VEX_0FE8
) },
8677 { PREFIX_TABLE (PREFIX_VEX_0FE9
) },
8678 { PREFIX_TABLE (PREFIX_VEX_0FEA
) },
8679 { PREFIX_TABLE (PREFIX_VEX_0FEB
) },
8680 { PREFIX_TABLE (PREFIX_VEX_0FEC
) },
8681 { PREFIX_TABLE (PREFIX_VEX_0FED
) },
8682 { PREFIX_TABLE (PREFIX_VEX_0FEE
) },
8683 { PREFIX_TABLE (PREFIX_VEX_0FEF
) },
8685 { PREFIX_TABLE (PREFIX_VEX_0FF0
) },
8686 { PREFIX_TABLE (PREFIX_VEX_0FF1
) },
8687 { PREFIX_TABLE (PREFIX_VEX_0FF2
) },
8688 { PREFIX_TABLE (PREFIX_VEX_0FF3
) },
8689 { PREFIX_TABLE (PREFIX_VEX_0FF4
) },
8690 { PREFIX_TABLE (PREFIX_VEX_0FF5
) },
8691 { PREFIX_TABLE (PREFIX_VEX_0FF6
) },
8692 { PREFIX_TABLE (PREFIX_VEX_0FF7
) },
8694 { PREFIX_TABLE (PREFIX_VEX_0FF8
) },
8695 { PREFIX_TABLE (PREFIX_VEX_0FF9
) },
8696 { PREFIX_TABLE (PREFIX_VEX_0FFA
) },
8697 { PREFIX_TABLE (PREFIX_VEX_0FFB
) },
8698 { PREFIX_TABLE (PREFIX_VEX_0FFC
) },
8699 { PREFIX_TABLE (PREFIX_VEX_0FFD
) },
8700 { PREFIX_TABLE (PREFIX_VEX_0FFE
) },
8706 { PREFIX_TABLE (PREFIX_VEX_0F3800
) },
8707 { PREFIX_TABLE (PREFIX_VEX_0F3801
) },
8708 { PREFIX_TABLE (PREFIX_VEX_0F3802
) },
8709 { PREFIX_TABLE (PREFIX_VEX_0F3803
) },
8710 { PREFIX_TABLE (PREFIX_VEX_0F3804
) },
8711 { PREFIX_TABLE (PREFIX_VEX_0F3805
) },
8712 { PREFIX_TABLE (PREFIX_VEX_0F3806
) },
8713 { PREFIX_TABLE (PREFIX_VEX_0F3807
) },
8715 { PREFIX_TABLE (PREFIX_VEX_0F3808
) },
8716 { PREFIX_TABLE (PREFIX_VEX_0F3809
) },
8717 { PREFIX_TABLE (PREFIX_VEX_0F380A
) },
8718 { PREFIX_TABLE (PREFIX_VEX_0F380B
) },
8719 { PREFIX_TABLE (PREFIX_VEX_0F380C
) },
8720 { PREFIX_TABLE (PREFIX_VEX_0F380D
) },
8721 { PREFIX_TABLE (PREFIX_VEX_0F380E
) },
8722 { PREFIX_TABLE (PREFIX_VEX_0F380F
) },
8727 { PREFIX_TABLE (PREFIX_VEX_0F3813
) },
8730 { PREFIX_TABLE (PREFIX_VEX_0F3816
) },
8731 { PREFIX_TABLE (PREFIX_VEX_0F3817
) },
8733 { PREFIX_TABLE (PREFIX_VEX_0F3818
) },
8734 { PREFIX_TABLE (PREFIX_VEX_0F3819
) },
8735 { PREFIX_TABLE (PREFIX_VEX_0F381A
) },
8737 { PREFIX_TABLE (PREFIX_VEX_0F381C
) },
8738 { PREFIX_TABLE (PREFIX_VEX_0F381D
) },
8739 { PREFIX_TABLE (PREFIX_VEX_0F381E
) },
8742 { PREFIX_TABLE (PREFIX_VEX_0F3820
) },
8743 { PREFIX_TABLE (PREFIX_VEX_0F3821
) },
8744 { PREFIX_TABLE (PREFIX_VEX_0F3822
) },
8745 { PREFIX_TABLE (PREFIX_VEX_0F3823
) },
8746 { PREFIX_TABLE (PREFIX_VEX_0F3824
) },
8747 { PREFIX_TABLE (PREFIX_VEX_0F3825
) },
8751 { PREFIX_TABLE (PREFIX_VEX_0F3828
) },
8752 { PREFIX_TABLE (PREFIX_VEX_0F3829
) },
8753 { PREFIX_TABLE (PREFIX_VEX_0F382A
) },
8754 { PREFIX_TABLE (PREFIX_VEX_0F382B
) },
8755 { PREFIX_TABLE (PREFIX_VEX_0F382C
) },
8756 { PREFIX_TABLE (PREFIX_VEX_0F382D
) },
8757 { PREFIX_TABLE (PREFIX_VEX_0F382E
) },
8758 { PREFIX_TABLE (PREFIX_VEX_0F382F
) },
8760 { PREFIX_TABLE (PREFIX_VEX_0F3830
) },
8761 { PREFIX_TABLE (PREFIX_VEX_0F3831
) },
8762 { PREFIX_TABLE (PREFIX_VEX_0F3832
) },
8763 { PREFIX_TABLE (PREFIX_VEX_0F3833
) },
8764 { PREFIX_TABLE (PREFIX_VEX_0F3834
) },
8765 { PREFIX_TABLE (PREFIX_VEX_0F3835
) },
8766 { PREFIX_TABLE (PREFIX_VEX_0F3836
) },
8767 { PREFIX_TABLE (PREFIX_VEX_0F3837
) },
8769 { PREFIX_TABLE (PREFIX_VEX_0F3838
) },
8770 { PREFIX_TABLE (PREFIX_VEX_0F3839
) },
8771 { PREFIX_TABLE (PREFIX_VEX_0F383A
) },
8772 { PREFIX_TABLE (PREFIX_VEX_0F383B
) },
8773 { PREFIX_TABLE (PREFIX_VEX_0F383C
) },
8774 { PREFIX_TABLE (PREFIX_VEX_0F383D
) },
8775 { PREFIX_TABLE (PREFIX_VEX_0F383E
) },
8776 { PREFIX_TABLE (PREFIX_VEX_0F383F
) },
8778 { PREFIX_TABLE (PREFIX_VEX_0F3840
) },
8779 { PREFIX_TABLE (PREFIX_VEX_0F3841
) },
8783 { PREFIX_TABLE (PREFIX_VEX_0F3845
) },
8784 { PREFIX_TABLE (PREFIX_VEX_0F3846
) },
8785 { PREFIX_TABLE (PREFIX_VEX_0F3847
) },
8805 { PREFIX_TABLE (PREFIX_VEX_0F3858
) },
8806 { PREFIX_TABLE (PREFIX_VEX_0F3859
) },
8807 { PREFIX_TABLE (PREFIX_VEX_0F385A
) },
8841 { PREFIX_TABLE (PREFIX_VEX_0F3878
) },
8842 { PREFIX_TABLE (PREFIX_VEX_0F3879
) },
8863 { PREFIX_TABLE (PREFIX_VEX_0F388C
) },
8865 { PREFIX_TABLE (PREFIX_VEX_0F388E
) },
8868 { PREFIX_TABLE (PREFIX_VEX_0F3890
) },
8869 { PREFIX_TABLE (PREFIX_VEX_0F3891
) },
8870 { PREFIX_TABLE (PREFIX_VEX_0F3892
) },
8871 { PREFIX_TABLE (PREFIX_VEX_0F3893
) },
8874 { PREFIX_TABLE (PREFIX_VEX_0F3896
) },
8875 { PREFIX_TABLE (PREFIX_VEX_0F3897
) },
8877 { PREFIX_TABLE (PREFIX_VEX_0F3898
) },
8878 { PREFIX_TABLE (PREFIX_VEX_0F3899
) },
8879 { PREFIX_TABLE (PREFIX_VEX_0F389A
) },
8880 { PREFIX_TABLE (PREFIX_VEX_0F389B
) },
8881 { PREFIX_TABLE (PREFIX_VEX_0F389C
) },
8882 { PREFIX_TABLE (PREFIX_VEX_0F389D
) },
8883 { PREFIX_TABLE (PREFIX_VEX_0F389E
) },
8884 { PREFIX_TABLE (PREFIX_VEX_0F389F
) },
8892 { PREFIX_TABLE (PREFIX_VEX_0F38A6
) },
8893 { PREFIX_TABLE (PREFIX_VEX_0F38A7
) },
8895 { PREFIX_TABLE (PREFIX_VEX_0F38A8
) },
8896 { PREFIX_TABLE (PREFIX_VEX_0F38A9
) },
8897 { PREFIX_TABLE (PREFIX_VEX_0F38AA
) },
8898 { PREFIX_TABLE (PREFIX_VEX_0F38AB
) },
8899 { PREFIX_TABLE (PREFIX_VEX_0F38AC
) },
8900 { PREFIX_TABLE (PREFIX_VEX_0F38AD
) },
8901 { PREFIX_TABLE (PREFIX_VEX_0F38AE
) },
8902 { PREFIX_TABLE (PREFIX_VEX_0F38AF
) },
8910 { PREFIX_TABLE (PREFIX_VEX_0F38B6
) },
8911 { PREFIX_TABLE (PREFIX_VEX_0F38B7
) },
8913 { PREFIX_TABLE (PREFIX_VEX_0F38B8
) },
8914 { PREFIX_TABLE (PREFIX_VEX_0F38B9
) },
8915 { PREFIX_TABLE (PREFIX_VEX_0F38BA
) },
8916 { PREFIX_TABLE (PREFIX_VEX_0F38BB
) },
8917 { PREFIX_TABLE (PREFIX_VEX_0F38BC
) },
8918 { PREFIX_TABLE (PREFIX_VEX_0F38BD
) },
8919 { PREFIX_TABLE (PREFIX_VEX_0F38BE
) },
8920 { PREFIX_TABLE (PREFIX_VEX_0F38BF
) },
8938 { PREFIX_TABLE (PREFIX_VEX_0F38CF
) },
8952 { PREFIX_TABLE (PREFIX_VEX_0F38DB
) },
8953 { PREFIX_TABLE (PREFIX_VEX_0F38DC
) },
8954 { PREFIX_TABLE (PREFIX_VEX_0F38DD
) },
8955 { PREFIX_TABLE (PREFIX_VEX_0F38DE
) },
8956 { PREFIX_TABLE (PREFIX_VEX_0F38DF
) },
8978 { PREFIX_TABLE (PREFIX_VEX_0F38F2
) },
8979 { REG_TABLE (REG_VEX_0F38F3
) },
8981 { PREFIX_TABLE (PREFIX_VEX_0F38F5
) },
8982 { PREFIX_TABLE (PREFIX_VEX_0F38F6
) },
8983 { PREFIX_TABLE (PREFIX_VEX_0F38F7
) },
8997 { PREFIX_TABLE (PREFIX_VEX_0F3A00
) },
8998 { PREFIX_TABLE (PREFIX_VEX_0F3A01
) },
8999 { PREFIX_TABLE (PREFIX_VEX_0F3A02
) },
9001 { PREFIX_TABLE (PREFIX_VEX_0F3A04
) },
9002 { PREFIX_TABLE (PREFIX_VEX_0F3A05
) },
9003 { PREFIX_TABLE (PREFIX_VEX_0F3A06
) },
9006 { PREFIX_TABLE (PREFIX_VEX_0F3A08
) },
9007 { PREFIX_TABLE (PREFIX_VEX_0F3A09
) },
9008 { PREFIX_TABLE (PREFIX_VEX_0F3A0A
) },
9009 { PREFIX_TABLE (PREFIX_VEX_0F3A0B
) },
9010 { PREFIX_TABLE (PREFIX_VEX_0F3A0C
) },
9011 { PREFIX_TABLE (PREFIX_VEX_0F3A0D
) },
9012 { PREFIX_TABLE (PREFIX_VEX_0F3A0E
) },
9013 { PREFIX_TABLE (PREFIX_VEX_0F3A0F
) },
9019 { PREFIX_TABLE (PREFIX_VEX_0F3A14
) },
9020 { PREFIX_TABLE (PREFIX_VEX_0F3A15
) },
9021 { PREFIX_TABLE (PREFIX_VEX_0F3A16
) },
9022 { PREFIX_TABLE (PREFIX_VEX_0F3A17
) },
9024 { PREFIX_TABLE (PREFIX_VEX_0F3A18
) },
9025 { PREFIX_TABLE (PREFIX_VEX_0F3A19
) },
9029 { PREFIX_TABLE (PREFIX_VEX_0F3A1D
) },
9033 { PREFIX_TABLE (PREFIX_VEX_0F3A20
) },
9034 { PREFIX_TABLE (PREFIX_VEX_0F3A21
) },
9035 { PREFIX_TABLE (PREFIX_VEX_0F3A22
) },
9051 { PREFIX_TABLE (PREFIX_VEX_0F3A30
) },
9052 { PREFIX_TABLE (PREFIX_VEX_0F3A31
) },
9053 { PREFIX_TABLE (PREFIX_VEX_0F3A32
) },
9054 { PREFIX_TABLE (PREFIX_VEX_0F3A33
) },
9060 { PREFIX_TABLE (PREFIX_VEX_0F3A38
) },
9061 { PREFIX_TABLE (PREFIX_VEX_0F3A39
) },
9069 { PREFIX_TABLE (PREFIX_VEX_0F3A40
) },
9070 { PREFIX_TABLE (PREFIX_VEX_0F3A41
) },
9071 { PREFIX_TABLE (PREFIX_VEX_0F3A42
) },
9073 { PREFIX_TABLE (PREFIX_VEX_0F3A44
) },
9075 { PREFIX_TABLE (PREFIX_VEX_0F3A46
) },
9078 { PREFIX_TABLE (PREFIX_VEX_0F3A48
) },
9079 { PREFIX_TABLE (PREFIX_VEX_0F3A49
) },
9080 { PREFIX_TABLE (PREFIX_VEX_0F3A4A
) },
9081 { PREFIX_TABLE (PREFIX_VEX_0F3A4B
) },
9082 { PREFIX_TABLE (PREFIX_VEX_0F3A4C
) },
9100 { PREFIX_TABLE (PREFIX_VEX_0F3A5C
) },
9101 { PREFIX_TABLE (PREFIX_VEX_0F3A5D
) },
9102 { PREFIX_TABLE (PREFIX_VEX_0F3A5E
) },
9103 { PREFIX_TABLE (PREFIX_VEX_0F3A5F
) },
9105 { PREFIX_TABLE (PREFIX_VEX_0F3A60
) },
9106 { PREFIX_TABLE (PREFIX_VEX_0F3A61
) },
9107 { PREFIX_TABLE (PREFIX_VEX_0F3A62
) },
9108 { PREFIX_TABLE (PREFIX_VEX_0F3A63
) },
9114 { PREFIX_TABLE (PREFIX_VEX_0F3A68
) },
9115 { PREFIX_TABLE (PREFIX_VEX_0F3A69
) },
9116 { PREFIX_TABLE (PREFIX_VEX_0F3A6A
) },
9117 { PREFIX_TABLE (PREFIX_VEX_0F3A6B
) },
9118 { PREFIX_TABLE (PREFIX_VEX_0F3A6C
) },
9119 { PREFIX_TABLE (PREFIX_VEX_0F3A6D
) },
9120 { PREFIX_TABLE (PREFIX_VEX_0F3A6E
) },
9121 { PREFIX_TABLE (PREFIX_VEX_0F3A6F
) },
9132 { PREFIX_TABLE (PREFIX_VEX_0F3A78
) },
9133 { PREFIX_TABLE (PREFIX_VEX_0F3A79
) },
9134 { PREFIX_TABLE (PREFIX_VEX_0F3A7A
) },
9135 { PREFIX_TABLE (PREFIX_VEX_0F3A7B
) },
9136 { PREFIX_TABLE (PREFIX_VEX_0F3A7C
) },
9137 { PREFIX_TABLE (PREFIX_VEX_0F3A7D
) },
9138 { PREFIX_TABLE (PREFIX_VEX_0F3A7E
) },
9139 { PREFIX_TABLE (PREFIX_VEX_0F3A7F
) },
9228 { PREFIX_TABLE(PREFIX_VEX_0F3ACE
) },
9229 { PREFIX_TABLE(PREFIX_VEX_0F3ACF
) },
9247 { PREFIX_TABLE (PREFIX_VEX_0F3ADF
) },
9267 { PREFIX_TABLE (PREFIX_VEX_0F3AF0
) },
9287 #define NEED_OPCODE_TABLE
9288 #include "i386-dis-evex.h"
9289 #undef NEED_OPCODE_TABLE
9290 static const struct dis386 vex_len_table
[][2] = {
9291 /* VEX_LEN_0F12_P_0_M_0 */
9293 { "vmovlps", { XM
, Vex128
, EXq
}, 0 },
9296 /* VEX_LEN_0F12_P_0_M_1 */
9298 { "vmovhlps", { XM
, Vex128
, EXq
}, 0 },
9301 /* VEX_LEN_0F12_P_2 */
9303 { "vmovlpd", { XM
, Vex128
, EXq
}, 0 },
9306 /* VEX_LEN_0F13_M_0 */
9308 { "vmovlpX", { EXq
, XM
}, 0 },
9311 /* VEX_LEN_0F16_P_0_M_0 */
9313 { "vmovhps", { XM
, Vex128
, EXq
}, 0 },
9316 /* VEX_LEN_0F16_P_0_M_1 */
9318 { "vmovlhps", { XM
, Vex128
, EXq
}, 0 },
9321 /* VEX_LEN_0F16_P_2 */
9323 { "vmovhpd", { XM
, Vex128
, EXq
}, 0 },
9326 /* VEX_LEN_0F17_M_0 */
9328 { "vmovhpX", { EXq
, XM
}, 0 },
9331 /* VEX_LEN_0F2A_P_1 */
9333 { "vcvtsi2ss%LQ", { XMScalar
, VexScalar
, Ev
}, 0 },
9334 { "vcvtsi2ss%LQ", { XMScalar
, VexScalar
, Ev
}, 0 },
9337 /* VEX_LEN_0F2A_P_3 */
9339 { "vcvtsi2sd%LQ", { XMScalar
, VexScalar
, Ev
}, 0 },
9340 { "vcvtsi2sd%LQ", { XMScalar
, VexScalar
, Ev
}, 0 },
9343 /* VEX_LEN_0F2C_P_1 */
9345 { "vcvttss2si", { Gv
, EXdScalar
}, 0 },
9346 { "vcvttss2si", { Gv
, EXdScalar
}, 0 },
9349 /* VEX_LEN_0F2C_P_3 */
9351 { "vcvttsd2si", { Gv
, EXqScalar
}, 0 },
9352 { "vcvttsd2si", { Gv
, EXqScalar
}, 0 },
9355 /* VEX_LEN_0F2D_P_1 */
9357 { "vcvtss2si", { Gv
, EXdScalar
}, 0 },
9358 { "vcvtss2si", { Gv
, EXdScalar
}, 0 },
9361 /* VEX_LEN_0F2D_P_3 */
9363 { "vcvtsd2si", { Gv
, EXqScalar
}, 0 },
9364 { "vcvtsd2si", { Gv
, EXqScalar
}, 0 },
9367 /* VEX_LEN_0F41_P_0 */
9370 { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1
) },
9372 /* VEX_LEN_0F41_P_2 */
9375 { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1
) },
9377 /* VEX_LEN_0F42_P_0 */
9380 { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1
) },
9382 /* VEX_LEN_0F42_P_2 */
9385 { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1
) },
9387 /* VEX_LEN_0F44_P_0 */
9389 { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0
) },
9391 /* VEX_LEN_0F44_P_2 */
9393 { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0
) },
9395 /* VEX_LEN_0F45_P_0 */
9398 { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1
) },
9400 /* VEX_LEN_0F45_P_2 */
9403 { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1
) },
9405 /* VEX_LEN_0F46_P_0 */
9408 { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1
) },
9410 /* VEX_LEN_0F46_P_2 */
9413 { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1
) },
9415 /* VEX_LEN_0F47_P_0 */
9418 { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1
) },
9420 /* VEX_LEN_0F47_P_2 */
9423 { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1
) },
9425 /* VEX_LEN_0F4A_P_0 */
9428 { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1
) },
9430 /* VEX_LEN_0F4A_P_2 */
9433 { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1
) },
9435 /* VEX_LEN_0F4B_P_0 */
9438 { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1
) },
9440 /* VEX_LEN_0F4B_P_2 */
9443 { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1
) },
9446 /* VEX_LEN_0F6E_P_2 */
9448 { "vmovK", { XMScalar
, Edq
}, 0 },
9451 /* VEX_LEN_0F77_P_1 */
9453 { "vzeroupper", { XX
}, 0 },
9454 { "vzeroall", { XX
}, 0 },
9457 /* VEX_LEN_0F7E_P_1 */
9459 { "vmovq", { XMScalar
, EXqScalar
}, 0 },
9462 /* VEX_LEN_0F7E_P_2 */
9464 { "vmovK", { Edq
, XMScalar
}, 0 },
9467 /* VEX_LEN_0F90_P_0 */
9469 { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0
) },
9472 /* VEX_LEN_0F90_P_2 */
9474 { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0
) },
9477 /* VEX_LEN_0F91_P_0 */
9479 { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0
) },
9482 /* VEX_LEN_0F91_P_2 */
9484 { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0
) },
9487 /* VEX_LEN_0F92_P_0 */
9489 { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0
) },
9492 /* VEX_LEN_0F92_P_2 */
9494 { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0
) },
9497 /* VEX_LEN_0F92_P_3 */
9499 { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0
) },
9502 /* VEX_LEN_0F93_P_0 */
9504 { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0
) },
9507 /* VEX_LEN_0F93_P_2 */
9509 { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0
) },
9512 /* VEX_LEN_0F93_P_3 */
9514 { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0
) },
9517 /* VEX_LEN_0F98_P_0 */
9519 { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0
) },
9522 /* VEX_LEN_0F98_P_2 */
9524 { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0
) },
9527 /* VEX_LEN_0F99_P_0 */
9529 { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0
) },
9532 /* VEX_LEN_0F99_P_2 */
9534 { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0
) },
9537 /* VEX_LEN_0FAE_R_2_M_0 */
9539 { "vldmxcsr", { Md
}, 0 },
9542 /* VEX_LEN_0FAE_R_3_M_0 */
9544 { "vstmxcsr", { Md
}, 0 },
9547 /* VEX_LEN_0FC4_P_2 */
9549 { "vpinsrw", { XM
, Vex128
, Edqw
, Ib
}, 0 },
9552 /* VEX_LEN_0FC5_P_2 */
9554 { "vpextrw", { Gdq
, XS
, Ib
}, 0 },
9557 /* VEX_LEN_0FD6_P_2 */
9559 { "vmovq", { EXqScalarS
, XMScalar
}, 0 },
9562 /* VEX_LEN_0FF7_P_2 */
9564 { "vmaskmovdqu", { XM
, XS
}, 0 },
9567 /* VEX_LEN_0F3816_P_2 */
9570 { VEX_W_TABLE (VEX_W_0F3816_P_2
) },
9573 /* VEX_LEN_0F3819_P_2 */
9576 { VEX_W_TABLE (VEX_W_0F3819_P_2
) },
9579 /* VEX_LEN_0F381A_P_2_M_0 */
9582 { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0
) },
9585 /* VEX_LEN_0F3836_P_2 */
9588 { VEX_W_TABLE (VEX_W_0F3836_P_2
) },
9591 /* VEX_LEN_0F3841_P_2 */
9593 { "vphminposuw", { XM
, EXx
}, 0 },
9596 /* VEX_LEN_0F385A_P_2_M_0 */
9599 { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0
) },
9602 /* VEX_LEN_0F38DB_P_2 */
9604 { "vaesimc", { XM
, EXx
}, 0 },
9607 /* VEX_LEN_0F38F2_P_0 */
9609 { "andnS", { Gdq
, VexGdq
, Edq
}, 0 },
9612 /* VEX_LEN_0F38F3_R_1_P_0 */
9614 { "blsrS", { VexGdq
, Edq
}, 0 },
9617 /* VEX_LEN_0F38F3_R_2_P_0 */
9619 { "blsmskS", { VexGdq
, Edq
}, 0 },
9622 /* VEX_LEN_0F38F3_R_3_P_0 */
9624 { "blsiS", { VexGdq
, Edq
}, 0 },
9627 /* VEX_LEN_0F38F5_P_0 */
9629 { "bzhiS", { Gdq
, Edq
, VexGdq
}, 0 },
9632 /* VEX_LEN_0F38F5_P_1 */
9634 { "pextS", { Gdq
, VexGdq
, Edq
}, 0 },
9637 /* VEX_LEN_0F38F5_P_3 */
9639 { "pdepS", { Gdq
, VexGdq
, Edq
}, 0 },
9642 /* VEX_LEN_0F38F6_P_3 */
9644 { "mulxS", { Gdq
, VexGdq
, Edq
}, 0 },
9647 /* VEX_LEN_0F38F7_P_0 */
9649 { "bextrS", { Gdq
, Edq
, VexGdq
}, 0 },
9652 /* VEX_LEN_0F38F7_P_1 */
9654 { "sarxS", { Gdq
, Edq
, VexGdq
}, 0 },
9657 /* VEX_LEN_0F38F7_P_2 */
9659 { "shlxS", { Gdq
, Edq
, VexGdq
}, 0 },
9662 /* VEX_LEN_0F38F7_P_3 */
9664 { "shrxS", { Gdq
, Edq
, VexGdq
}, 0 },
9667 /* VEX_LEN_0F3A00_P_2 */
9670 { VEX_W_TABLE (VEX_W_0F3A00_P_2
) },
9673 /* VEX_LEN_0F3A01_P_2 */
9676 { VEX_W_TABLE (VEX_W_0F3A01_P_2
) },
9679 /* VEX_LEN_0F3A06_P_2 */
9682 { VEX_W_TABLE (VEX_W_0F3A06_P_2
) },
9685 /* VEX_LEN_0F3A14_P_2 */
9687 { "vpextrb", { Edqb
, XM
, Ib
}, 0 },
9690 /* VEX_LEN_0F3A15_P_2 */
9692 { "vpextrw", { Edqw
, XM
, Ib
}, 0 },
9695 /* VEX_LEN_0F3A16_P_2 */
9697 { "vpextrK", { Edq
, XM
, Ib
}, 0 },
9700 /* VEX_LEN_0F3A17_P_2 */
9702 { "vextractps", { Edqd
, XM
, Ib
}, 0 },
9705 /* VEX_LEN_0F3A18_P_2 */
9708 { VEX_W_TABLE (VEX_W_0F3A18_P_2
) },
9711 /* VEX_LEN_0F3A19_P_2 */
9714 { VEX_W_TABLE (VEX_W_0F3A19_P_2
) },
9717 /* VEX_LEN_0F3A20_P_2 */
9719 { "vpinsrb", { XM
, Vex128
, Edqb
, Ib
}, 0 },
9722 /* VEX_LEN_0F3A21_P_2 */
9724 { "vinsertps", { XM
, Vex128
, EXd
, Ib
}, 0 },
9727 /* VEX_LEN_0F3A22_P_2 */
9729 { "vpinsrK", { XM
, Vex128
, Edq
, Ib
}, 0 },
9732 /* VEX_LEN_0F3A30_P_2 */
9734 { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0
) },
9737 /* VEX_LEN_0F3A31_P_2 */
9739 { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0
) },
9742 /* VEX_LEN_0F3A32_P_2 */
9744 { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0
) },
9747 /* VEX_LEN_0F3A33_P_2 */
9749 { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0
) },
9752 /* VEX_LEN_0F3A38_P_2 */
9755 { VEX_W_TABLE (VEX_W_0F3A38_P_2
) },
9758 /* VEX_LEN_0F3A39_P_2 */
9761 { VEX_W_TABLE (VEX_W_0F3A39_P_2
) },
9764 /* VEX_LEN_0F3A41_P_2 */
9766 { "vdppd", { XM
, Vex128
, EXx
, Ib
}, 0 },
9769 /* VEX_LEN_0F3A46_P_2 */
9772 { VEX_W_TABLE (VEX_W_0F3A46_P_2
) },
9775 /* VEX_LEN_0F3A60_P_2 */
9777 { "vpcmpestrm", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, 0 },
9780 /* VEX_LEN_0F3A61_P_2 */
9782 { "vpcmpestri", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, 0 },
9785 /* VEX_LEN_0F3A62_P_2 */
9787 { "vpcmpistrm", { XM
, EXx
, Ib
}, 0 },
9790 /* VEX_LEN_0F3A63_P_2 */
9792 { "vpcmpistri", { XM
, EXx
, Ib
}, 0 },
9795 /* VEX_LEN_0F3A6A_P_2 */
9797 { "vfmaddss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
}, 0 },
9800 /* VEX_LEN_0F3A6B_P_2 */
9802 { "vfmaddsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
}, 0 },
9805 /* VEX_LEN_0F3A6E_P_2 */
9807 { "vfmsubss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
}, 0 },
9810 /* VEX_LEN_0F3A6F_P_2 */
9812 { "vfmsubsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
}, 0 },
9815 /* VEX_LEN_0F3A7A_P_2 */
9817 { "vfnmaddss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
}, 0 },
9820 /* VEX_LEN_0F3A7B_P_2 */
9822 { "vfnmaddsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
}, 0 },
9825 /* VEX_LEN_0F3A7E_P_2 */
9827 { "vfnmsubss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
}, 0 },
9830 /* VEX_LEN_0F3A7F_P_2 */
9832 { "vfnmsubsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
}, 0 },
9835 /* VEX_LEN_0F3ADF_P_2 */
9837 { "vaeskeygenassist", { XM
, EXx
, Ib
}, 0 },
9840 /* VEX_LEN_0F3AF0_P_3 */
9842 { "rorxS", { Gdq
, Edq
, Ib
}, 0 },
9845 /* VEX_LEN_0FXOP_08_CC */
9847 { "vpcomb", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9850 /* VEX_LEN_0FXOP_08_CD */
9852 { "vpcomw", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9855 /* VEX_LEN_0FXOP_08_CE */
9857 { "vpcomd", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9860 /* VEX_LEN_0FXOP_08_CF */
9862 { "vpcomq", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9865 /* VEX_LEN_0FXOP_08_EC */
9867 { "vpcomub", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9870 /* VEX_LEN_0FXOP_08_ED */
9872 { "vpcomuw", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9875 /* VEX_LEN_0FXOP_08_EE */
9877 { "vpcomud", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9880 /* VEX_LEN_0FXOP_08_EF */
9882 { "vpcomuq", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9885 /* VEX_LEN_0FXOP_09_80 */
9887 { "vfrczps", { XM
, EXxmm
}, 0 },
9888 { "vfrczps", { XM
, EXymmq
}, 0 },
9891 /* VEX_LEN_0FXOP_09_81 */
9893 { "vfrczpd", { XM
, EXxmm
}, 0 },
9894 { "vfrczpd", { XM
, EXymmq
}, 0 },
9898 static const struct dis386 evex_len_table
[][3] = {
9899 #define NEED_EVEX_LEN_TABLE
9900 #include "i386-dis-evex.h"
9901 #undef NEED_EVEX_LEN_TABLE
9904 static const struct dis386 vex_w_table
[][2] = {
9906 /* VEX_W_0F41_P_0_LEN_1 */
9907 { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1
) },
9908 { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1
) },
9911 /* VEX_W_0F41_P_2_LEN_1 */
9912 { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1
) },
9913 { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1
) }
9916 /* VEX_W_0F42_P_0_LEN_1 */
9917 { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1
) },
9918 { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1
) },
9921 /* VEX_W_0F42_P_2_LEN_1 */
9922 { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1
) },
9923 { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1
) },
9926 /* VEX_W_0F44_P_0_LEN_0 */
9927 { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1
) },
9928 { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1
) },
9931 /* VEX_W_0F44_P_2_LEN_0 */
9932 { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1
) },
9933 { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1
) },
9936 /* VEX_W_0F45_P_0_LEN_1 */
9937 { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1
) },
9938 { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1
) },
9941 /* VEX_W_0F45_P_2_LEN_1 */
9942 { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1
) },
9943 { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1
) },
9946 /* VEX_W_0F46_P_0_LEN_1 */
9947 { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1
) },
9948 { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1
) },
9951 /* VEX_W_0F46_P_2_LEN_1 */
9952 { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1
) },
9953 { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1
) },
9956 /* VEX_W_0F47_P_0_LEN_1 */
9957 { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1
) },
9958 { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1
) },
9961 /* VEX_W_0F47_P_2_LEN_1 */
9962 { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1
) },
9963 { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1
) },
9966 /* VEX_W_0F4A_P_0_LEN_1 */
9967 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1
) },
9968 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1
) },
9971 /* VEX_W_0F4A_P_2_LEN_1 */
9972 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1
) },
9973 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1
) },
9976 /* VEX_W_0F4B_P_0_LEN_1 */
9977 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1
) },
9978 { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1
) },
9981 /* VEX_W_0F4B_P_2_LEN_1 */
9982 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1
) },
9985 /* VEX_W_0F90_P_0_LEN_0 */
9986 { "kmovw", { MaskG
, MaskE
}, 0 },
9987 { "kmovq", { MaskG
, MaskE
}, 0 },
9990 /* VEX_W_0F90_P_2_LEN_0 */
9991 { "kmovb", { MaskG
, MaskBDE
}, 0 },
9992 { "kmovd", { MaskG
, MaskBDE
}, 0 },
9995 /* VEX_W_0F91_P_0_LEN_0 */
9996 { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0
) },
9997 { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0
) },
10000 /* VEX_W_0F91_P_2_LEN_0 */
10001 { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0
) },
10002 { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0
) },
10005 /* VEX_W_0F92_P_0_LEN_0 */
10006 { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0
) },
10009 /* VEX_W_0F92_P_2_LEN_0 */
10010 { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0
) },
10013 /* VEX_W_0F93_P_0_LEN_0 */
10014 { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0
) },
10017 /* VEX_W_0F93_P_2_LEN_0 */
10018 { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0
) },
10021 /* VEX_W_0F98_P_0_LEN_0 */
10022 { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0
) },
10023 { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0
) },
10026 /* VEX_W_0F98_P_2_LEN_0 */
10027 { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0
) },
10028 { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0
) },
10031 /* VEX_W_0F99_P_0_LEN_0 */
10032 { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0
) },
10033 { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0
) },
10036 /* VEX_W_0F99_P_2_LEN_0 */
10037 { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0
) },
10038 { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0
) },
10041 /* VEX_W_0F380C_P_2 */
10042 { "vpermilps", { XM
, Vex
, EXx
}, 0 },
10045 /* VEX_W_0F380D_P_2 */
10046 { "vpermilpd", { XM
, Vex
, EXx
}, 0 },
10049 /* VEX_W_0F380E_P_2 */
10050 { "vtestps", { XM
, EXx
}, 0 },
10053 /* VEX_W_0F380F_P_2 */
10054 { "vtestpd", { XM
, EXx
}, 0 },
10057 /* VEX_W_0F3816_P_2 */
10058 { "vpermps", { XM
, Vex
, EXx
}, 0 },
10061 /* VEX_W_0F3818_P_2 */
10062 { "vbroadcastss", { XM
, EXxmm_md
}, 0 },
10065 /* VEX_W_0F3819_P_2 */
10066 { "vbroadcastsd", { XM
, EXxmm_mq
}, 0 },
10069 /* VEX_W_0F381A_P_2_M_0 */
10070 { "vbroadcastf128", { XM
, Mxmm
}, 0 },
10073 /* VEX_W_0F382C_P_2_M_0 */
10074 { "vmaskmovps", { XM
, Vex
, Mx
}, 0 },
10077 /* VEX_W_0F382D_P_2_M_0 */
10078 { "vmaskmovpd", { XM
, Vex
, Mx
}, 0 },
10081 /* VEX_W_0F382E_P_2_M_0 */
10082 { "vmaskmovps", { Mx
, Vex
, XM
}, 0 },
10085 /* VEX_W_0F382F_P_2_M_0 */
10086 { "vmaskmovpd", { Mx
, Vex
, XM
}, 0 },
10089 /* VEX_W_0F3836_P_2 */
10090 { "vpermd", { XM
, Vex
, EXx
}, 0 },
10093 /* VEX_W_0F3846_P_2 */
10094 { "vpsravd", { XM
, Vex
, EXx
}, 0 },
10097 /* VEX_W_0F3858_P_2 */
10098 { "vpbroadcastd", { XM
, EXxmm_md
}, 0 },
10101 /* VEX_W_0F3859_P_2 */
10102 { "vpbroadcastq", { XM
, EXxmm_mq
}, 0 },
10105 /* VEX_W_0F385A_P_2_M_0 */
10106 { "vbroadcasti128", { XM
, Mxmm
}, 0 },
10109 /* VEX_W_0F3878_P_2 */
10110 { "vpbroadcastb", { XM
, EXxmm_mb
}, 0 },
10113 /* VEX_W_0F3879_P_2 */
10114 { "vpbroadcastw", { XM
, EXxmm_mw
}, 0 },
10117 /* VEX_W_0F38CF_P_2 */
10118 { "vgf2p8mulb", { XM
, Vex
, EXx
}, 0 },
10121 /* VEX_W_0F3A00_P_2 */
10123 { "vpermq", { XM
, EXx
, Ib
}, 0 },
10126 /* VEX_W_0F3A01_P_2 */
10128 { "vpermpd", { XM
, EXx
, Ib
}, 0 },
10131 /* VEX_W_0F3A02_P_2 */
10132 { "vpblendd", { XM
, Vex
, EXx
, Ib
}, 0 },
10135 /* VEX_W_0F3A04_P_2 */
10136 { "vpermilps", { XM
, EXx
, Ib
}, 0 },
10139 /* VEX_W_0F3A05_P_2 */
10140 { "vpermilpd", { XM
, EXx
, Ib
}, 0 },
10143 /* VEX_W_0F3A06_P_2 */
10144 { "vperm2f128", { XM
, Vex256
, EXx
, Ib
}, 0 },
10147 /* VEX_W_0F3A18_P_2 */
10148 { "vinsertf128", { XM
, Vex256
, EXxmm
, Ib
}, 0 },
10151 /* VEX_W_0F3A19_P_2 */
10152 { "vextractf128", { EXxmm
, XM
, Ib
}, 0 },
10155 /* VEX_W_0F3A30_P_2_LEN_0 */
10156 { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0
) },
10157 { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0
) },
10160 /* VEX_W_0F3A31_P_2_LEN_0 */
10161 { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0
) },
10162 { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0
) },
10165 /* VEX_W_0F3A32_P_2_LEN_0 */
10166 { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0
) },
10167 { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0
) },
10170 /* VEX_W_0F3A33_P_2_LEN_0 */
10171 { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0
) },
10172 { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0
) },
10175 /* VEX_W_0F3A38_P_2 */
10176 { "vinserti128", { XM
, Vex256
, EXxmm
, Ib
}, 0 },
10179 /* VEX_W_0F3A39_P_2 */
10180 { "vextracti128", { EXxmm
, XM
, Ib
}, 0 },
10183 /* VEX_W_0F3A46_P_2 */
10184 { "vperm2i128", { XM
, Vex256
, EXx
, Ib
}, 0 },
10187 /* VEX_W_0F3A48_P_2 */
10188 { "vpermil2ps", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
10189 { "vpermil2ps", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
10192 /* VEX_W_0F3A49_P_2 */
10193 { "vpermil2pd", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
10194 { "vpermil2pd", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
10197 /* VEX_W_0F3A4A_P_2 */
10198 { "vblendvps", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10201 /* VEX_W_0F3A4B_P_2 */
10202 { "vblendvpd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10205 /* VEX_W_0F3A4C_P_2 */
10206 { "vpblendvb", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10209 /* VEX_W_0F3ACE_P_2 */
10211 { "vgf2p8affineqb", { XM
, Vex
, EXx
, Ib
}, 0 },
10214 /* VEX_W_0F3ACF_P_2 */
10216 { "vgf2p8affineinvqb", { XM
, Vex
, EXx
, Ib
}, 0 },
10218 #define NEED_VEX_W_TABLE
10219 #include "i386-dis-evex.h"
10220 #undef NEED_VEX_W_TABLE
10223 static const struct dis386 mod_table
[][2] = {
10226 { "leaS", { Gv
, M
}, 0 },
10231 { RM_TABLE (RM_C6_REG_7
) },
10236 { RM_TABLE (RM_C7_REG_7
) },
10240 { "Jcall^", { indirEp
}, 0 },
10244 { "Jjmp^", { indirEp
}, 0 },
10247 /* MOD_0F01_REG_0 */
10248 { X86_64_TABLE (X86_64_0F01_REG_0
) },
10249 { RM_TABLE (RM_0F01_REG_0
) },
10252 /* MOD_0F01_REG_1 */
10253 { X86_64_TABLE (X86_64_0F01_REG_1
) },
10254 { RM_TABLE (RM_0F01_REG_1
) },
10257 /* MOD_0F01_REG_2 */
10258 { X86_64_TABLE (X86_64_0F01_REG_2
) },
10259 { RM_TABLE (RM_0F01_REG_2
) },
10262 /* MOD_0F01_REG_3 */
10263 { X86_64_TABLE (X86_64_0F01_REG_3
) },
10264 { RM_TABLE (RM_0F01_REG_3
) },
10267 /* MOD_0F01_REG_5 */
10268 { PREFIX_TABLE (PREFIX_MOD_0_0F01_REG_5
) },
10269 { RM_TABLE (RM_0F01_REG_5
) },
10272 /* MOD_0F01_REG_7 */
10273 { "invlpg", { Mb
}, 0 },
10274 { RM_TABLE (RM_0F01_REG_7
) },
10277 /* MOD_0F12_PREFIX_0 */
10278 { "movlps", { XM
, EXq
}, PREFIX_OPCODE
},
10279 { "movhlps", { XM
, EXq
}, PREFIX_OPCODE
},
10283 { "movlpX", { EXq
, XM
}, PREFIX_OPCODE
},
10286 /* MOD_0F16_PREFIX_0 */
10287 { "movhps", { XM
, EXq
}, 0 },
10288 { "movlhps", { XM
, EXq
}, 0 },
10292 { "movhpX", { EXq
, XM
}, PREFIX_OPCODE
},
10295 /* MOD_0F18_REG_0 */
10296 { "prefetchnta", { Mb
}, 0 },
10299 /* MOD_0F18_REG_1 */
10300 { "prefetcht0", { Mb
}, 0 },
10303 /* MOD_0F18_REG_2 */
10304 { "prefetcht1", { Mb
}, 0 },
10307 /* MOD_0F18_REG_3 */
10308 { "prefetcht2", { Mb
}, 0 },
10311 /* MOD_0F18_REG_4 */
10312 { "nop/reserved", { Mb
}, 0 },
10315 /* MOD_0F18_REG_5 */
10316 { "nop/reserved", { Mb
}, 0 },
10319 /* MOD_0F18_REG_6 */
10320 { "nop/reserved", { Mb
}, 0 },
10323 /* MOD_0F18_REG_7 */
10324 { "nop/reserved", { Mb
}, 0 },
10327 /* MOD_0F1A_PREFIX_0 */
10328 { "bndldx", { Gbnd
, Mv_bnd
}, 0 },
10329 { "nopQ", { Ev
}, 0 },
10332 /* MOD_0F1B_PREFIX_0 */
10333 { "bndstx", { Mv_bnd
, Gbnd
}, 0 },
10334 { "nopQ", { Ev
}, 0 },
10337 /* MOD_0F1B_PREFIX_1 */
10338 { "bndmk", { Gbnd
, Mv_bnd
}, 0 },
10339 { "nopQ", { Ev
}, 0 },
10342 /* MOD_0F1C_PREFIX_0 */
10343 { REG_TABLE (REG_0F1C_MOD_0
) },
10344 { "nopQ", { Ev
}, 0 },
10347 /* MOD_0F1E_PREFIX_1 */
10348 { "nopQ", { Ev
}, 0 },
10349 { REG_TABLE (REG_0F1E_MOD_3
) },
10354 { "movL", { Rd
, Td
}, 0 },
10359 { "movL", { Td
, Rd
}, 0 },
10362 /* MOD_0F2B_PREFIX_0 */
10363 {"movntps", { Mx
, XM
}, PREFIX_OPCODE
},
10366 /* MOD_0F2B_PREFIX_1 */
10367 {"movntss", { Md
, XM
}, PREFIX_OPCODE
},
10370 /* MOD_0F2B_PREFIX_2 */
10371 {"movntpd", { Mx
, XM
}, PREFIX_OPCODE
},
10374 /* MOD_0F2B_PREFIX_3 */
10375 {"movntsd", { Mq
, XM
}, PREFIX_OPCODE
},
10380 { "movmskpX", { Gdq
, XS
}, PREFIX_OPCODE
},
10383 /* MOD_0F71_REG_2 */
10385 { "psrlw", { MS
, Ib
}, 0 },
10388 /* MOD_0F71_REG_4 */
10390 { "psraw", { MS
, Ib
}, 0 },
10393 /* MOD_0F71_REG_6 */
10395 { "psllw", { MS
, Ib
}, 0 },
10398 /* MOD_0F72_REG_2 */
10400 { "psrld", { MS
, Ib
}, 0 },
10403 /* MOD_0F72_REG_4 */
10405 { "psrad", { MS
, Ib
}, 0 },
10408 /* MOD_0F72_REG_6 */
10410 { "pslld", { MS
, Ib
}, 0 },
10413 /* MOD_0F73_REG_2 */
10415 { "psrlq", { MS
, Ib
}, 0 },
10418 /* MOD_0F73_REG_3 */
10420 { PREFIX_TABLE (PREFIX_0F73_REG_3
) },
10423 /* MOD_0F73_REG_6 */
10425 { "psllq", { MS
, Ib
}, 0 },
10428 /* MOD_0F73_REG_7 */
10430 { PREFIX_TABLE (PREFIX_0F73_REG_7
) },
10433 /* MOD_0FAE_REG_0 */
10434 { "fxsave", { FXSAVE
}, 0 },
10435 { PREFIX_TABLE (PREFIX_0FAE_REG_0
) },
10438 /* MOD_0FAE_REG_1 */
10439 { "fxrstor", { FXSAVE
}, 0 },
10440 { PREFIX_TABLE (PREFIX_0FAE_REG_1
) },
10443 /* MOD_0FAE_REG_2 */
10444 { "ldmxcsr", { Md
}, 0 },
10445 { PREFIX_TABLE (PREFIX_0FAE_REG_2
) },
10448 /* MOD_0FAE_REG_3 */
10449 { "stmxcsr", { Md
}, 0 },
10450 { PREFIX_TABLE (PREFIX_0FAE_REG_3
) },
10453 /* MOD_0FAE_REG_4 */
10454 { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_4
) },
10455 { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_4
) },
10458 /* MOD_0FAE_REG_5 */
10459 { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_5
) },
10460 { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_5
) },
10463 /* MOD_0FAE_REG_6 */
10464 { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_6
) },
10465 { PREFIX_TABLE (PREFIX_MOD_1_0FAE_REG_6
) },
10468 /* MOD_0FAE_REG_7 */
10469 { PREFIX_TABLE (PREFIX_0FAE_REG_7
) },
10470 { RM_TABLE (RM_0FAE_REG_7
) },
10474 { "lssS", { Gv
, Mp
}, 0 },
10478 { "lfsS", { Gv
, Mp
}, 0 },
10482 { "lgsS", { Gv
, Mp
}, 0 },
10486 { PREFIX_TABLE (PREFIX_MOD_0_0FC3
) },
10489 /* MOD_0FC7_REG_3 */
10490 { "xrstors", { FXSAVE
}, 0 },
10493 /* MOD_0FC7_REG_4 */
10494 { "xsavec", { FXSAVE
}, 0 },
10497 /* MOD_0FC7_REG_5 */
10498 { "xsaves", { FXSAVE
}, 0 },
10501 /* MOD_0FC7_REG_6 */
10502 { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6
) },
10503 { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6
) }
10506 /* MOD_0FC7_REG_7 */
10507 { "vmptrst", { Mq
}, 0 },
10508 { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7
) }
10513 { "pmovmskb", { Gdq
, MS
}, 0 },
10516 /* MOD_0FE7_PREFIX_2 */
10517 { "movntdq", { Mx
, XM
}, 0 },
10520 /* MOD_0FF0_PREFIX_3 */
10521 { "lddqu", { XM
, M
}, 0 },
10524 /* MOD_0F382A_PREFIX_2 */
10525 { "movntdqa", { XM
, Mx
}, 0 },
10528 /* MOD_0F38F5_PREFIX_2 */
10529 { "wrussK", { M
, Gdq
}, PREFIX_OPCODE
},
10532 /* MOD_0F38F6_PREFIX_0 */
10533 { "wrssK", { M
, Gdq
}, PREFIX_OPCODE
},
10536 /* MOD_0F38F8_PREFIX_1 */
10537 { "enqcmds", { Gva
, M
}, PREFIX_OPCODE
},
10540 /* MOD_0F38F8_PREFIX_2 */
10541 { "movdir64b", { Gva
, M
}, PREFIX_OPCODE
},
10544 /* MOD_0F38F8_PREFIX_3 */
10545 { "enqcmd", { Gva
, M
}, PREFIX_OPCODE
},
10548 /* MOD_0F38F9_PREFIX_0 */
10549 { "movdiri", { Em
, Gv
}, PREFIX_OPCODE
},
10553 { "bound{S|}", { Gv
, Ma
}, 0 },
10554 { EVEX_TABLE (EVEX_0F
) },
10558 { "lesS", { Gv
, Mp
}, 0 },
10559 { VEX_C4_TABLE (VEX_0F
) },
10563 { "ldsS", { Gv
, Mp
}, 0 },
10564 { VEX_C5_TABLE (VEX_0F
) },
10567 /* MOD_VEX_0F12_PREFIX_0 */
10568 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0
) },
10569 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1
) },
10573 { VEX_LEN_TABLE (VEX_LEN_0F13_M_0
) },
10576 /* MOD_VEX_0F16_PREFIX_0 */
10577 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0
) },
10578 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1
) },
10582 { VEX_LEN_TABLE (VEX_LEN_0F17_M_0
) },
10586 { "vmovntpX", { Mx
, XM
}, 0 },
10589 /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
10591 { "kandw", { MaskG
, MaskVex
, MaskR
}, 0 },
10594 /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
10596 { "kandq", { MaskG
, MaskVex
, MaskR
}, 0 },
10599 /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
10601 { "kandb", { MaskG
, MaskVex
, MaskR
}, 0 },
10604 /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
10606 { "kandd", { MaskG
, MaskVex
, MaskR
}, 0 },
10609 /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
10611 { "kandnw", { MaskG
, MaskVex
, MaskR
}, 0 },
10614 /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
10616 { "kandnq", { MaskG
, MaskVex
, MaskR
}, 0 },
10619 /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
10621 { "kandnb", { MaskG
, MaskVex
, MaskR
}, 0 },
10624 /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
10626 { "kandnd", { MaskG
, MaskVex
, MaskR
}, 0 },
10629 /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
10631 { "knotw", { MaskG
, MaskR
}, 0 },
10634 /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
10636 { "knotq", { MaskG
, MaskR
}, 0 },
10639 /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
10641 { "knotb", { MaskG
, MaskR
}, 0 },
10644 /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
10646 { "knotd", { MaskG
, MaskR
}, 0 },
10649 /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
10651 { "korw", { MaskG
, MaskVex
, MaskR
}, 0 },
10654 /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
10656 { "korq", { MaskG
, MaskVex
, MaskR
}, 0 },
10659 /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
10661 { "korb", { MaskG
, MaskVex
, MaskR
}, 0 },
10664 /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
10666 { "kord", { MaskG
, MaskVex
, MaskR
}, 0 },
10669 /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
10671 { "kxnorw", { MaskG
, MaskVex
, MaskR
}, 0 },
10674 /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
10676 { "kxnorq", { MaskG
, MaskVex
, MaskR
}, 0 },
10679 /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
10681 { "kxnorb", { MaskG
, MaskVex
, MaskR
}, 0 },
10684 /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
10686 { "kxnord", { MaskG
, MaskVex
, MaskR
}, 0 },
10689 /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
10691 { "kxorw", { MaskG
, MaskVex
, MaskR
}, 0 },
10694 /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
10696 { "kxorq", { MaskG
, MaskVex
, MaskR
}, 0 },
10699 /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
10701 { "kxorb", { MaskG
, MaskVex
, MaskR
}, 0 },
10704 /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
10706 { "kxord", { MaskG
, MaskVex
, MaskR
}, 0 },
10709 /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
10711 { "kaddw", { MaskG
, MaskVex
, MaskR
}, 0 },
10714 /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
10716 { "kaddq", { MaskG
, MaskVex
, MaskR
}, 0 },
10719 /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
10721 { "kaddb", { MaskG
, MaskVex
, MaskR
}, 0 },
10724 /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
10726 { "kaddd", { MaskG
, MaskVex
, MaskR
}, 0 },
10729 /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
10731 { "kunpckwd", { MaskG
, MaskVex
, MaskR
}, 0 },
10734 /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
10736 { "kunpckdq", { MaskG
, MaskVex
, MaskR
}, 0 },
10739 /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
10741 { "kunpckbw", { MaskG
, MaskVex
, MaskR
}, 0 },
10746 { "vmovmskpX", { Gdq
, XS
}, 0 },
10749 /* MOD_VEX_0F71_REG_2 */
10751 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2
) },
10754 /* MOD_VEX_0F71_REG_4 */
10756 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4
) },
10759 /* MOD_VEX_0F71_REG_6 */
10761 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6
) },
10764 /* MOD_VEX_0F72_REG_2 */
10766 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2
) },
10769 /* MOD_VEX_0F72_REG_4 */
10771 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4
) },
10774 /* MOD_VEX_0F72_REG_6 */
10776 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6
) },
10779 /* MOD_VEX_0F73_REG_2 */
10781 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2
) },
10784 /* MOD_VEX_0F73_REG_3 */
10786 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3
) },
10789 /* MOD_VEX_0F73_REG_6 */
10791 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6
) },
10794 /* MOD_VEX_0F73_REG_7 */
10796 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7
) },
10799 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10800 { "kmovw", { Ew
, MaskG
}, 0 },
10804 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10805 { "kmovq", { Eq
, MaskG
}, 0 },
10809 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10810 { "kmovb", { Eb
, MaskG
}, 0 },
10814 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10815 { "kmovd", { Ed
, MaskG
}, 0 },
10819 /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
10821 { "kmovw", { MaskG
, Rdq
}, 0 },
10824 /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
10826 { "kmovb", { MaskG
, Rdq
}, 0 },
10829 /* MOD_VEX_0F92_P_3_LEN_0 */
10831 { "kmovK", { MaskG
, Rdq
}, 0 },
10834 /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
10836 { "kmovw", { Gdq
, MaskR
}, 0 },
10839 /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
10841 { "kmovb", { Gdq
, MaskR
}, 0 },
10844 /* MOD_VEX_0F93_P_3_LEN_0 */
10846 { "kmovK", { Gdq
, MaskR
}, 0 },
10849 /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
10851 { "kortestw", { MaskG
, MaskR
}, 0 },
10854 /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
10856 { "kortestq", { MaskG
, MaskR
}, 0 },
10859 /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
10861 { "kortestb", { MaskG
, MaskR
}, 0 },
10864 /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
10866 { "kortestd", { MaskG
, MaskR
}, 0 },
10869 /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
10871 { "ktestw", { MaskG
, MaskR
}, 0 },
10874 /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
10876 { "ktestq", { MaskG
, MaskR
}, 0 },
10879 /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
10881 { "ktestb", { MaskG
, MaskR
}, 0 },
10884 /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
10886 { "ktestd", { MaskG
, MaskR
}, 0 },
10889 /* MOD_VEX_0FAE_REG_2 */
10890 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0
) },
10893 /* MOD_VEX_0FAE_REG_3 */
10894 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0
) },
10897 /* MOD_VEX_0FD7_PREFIX_2 */
10899 { "vpmovmskb", { Gdq
, XS
}, 0 },
10902 /* MOD_VEX_0FE7_PREFIX_2 */
10903 { "vmovntdq", { Mx
, XM
}, 0 },
10906 /* MOD_VEX_0FF0_PREFIX_3 */
10907 { "vlddqu", { XM
, M
}, 0 },
10910 /* MOD_VEX_0F381A_PREFIX_2 */
10911 { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0
) },
10914 /* MOD_VEX_0F382A_PREFIX_2 */
10915 { "vmovntdqa", { XM
, Mx
}, 0 },
10918 /* MOD_VEX_0F382C_PREFIX_2 */
10919 { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0
) },
10922 /* MOD_VEX_0F382D_PREFIX_2 */
10923 { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0
) },
10926 /* MOD_VEX_0F382E_PREFIX_2 */
10927 { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0
) },
10930 /* MOD_VEX_0F382F_PREFIX_2 */
10931 { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0
) },
10934 /* MOD_VEX_0F385A_PREFIX_2 */
10935 { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0
) },
10938 /* MOD_VEX_0F388C_PREFIX_2 */
10939 { "vpmaskmov%LW", { XM
, Vex
, Mx
}, 0 },
10942 /* MOD_VEX_0F388E_PREFIX_2 */
10943 { "vpmaskmov%LW", { Mx
, Vex
, XM
}, 0 },
10946 /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
10948 { "kshiftrb", { MaskG
, MaskR
, Ib
}, 0 },
10951 /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
10953 { "kshiftrw", { MaskG
, MaskR
, Ib
}, 0 },
10956 /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
10958 { "kshiftrd", { MaskG
, MaskR
, Ib
}, 0 },
10961 /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
10963 { "kshiftrq", { MaskG
, MaskR
, Ib
}, 0 },
10966 /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
10968 { "kshiftlb", { MaskG
, MaskR
, Ib
}, 0 },
10971 /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
10973 { "kshiftlw", { MaskG
, MaskR
, Ib
}, 0 },
10976 /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
10978 { "kshiftld", { MaskG
, MaskR
, Ib
}, 0 },
10981 /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
10983 { "kshiftlq", { MaskG
, MaskR
, Ib
}, 0 },
10985 #define NEED_MOD_TABLE
10986 #include "i386-dis-evex.h"
10987 #undef NEED_MOD_TABLE
10990 static const struct dis386 rm_table
[][8] = {
10993 { "xabort", { Skip_MODRM
, Ib
}, 0 },
10997 { "xbeginT", { Skip_MODRM
, Jv
}, 0 },
11000 /* RM_0F01_REG_0 */
11001 { "enclv", { Skip_MODRM
}, 0 },
11002 { "vmcall", { Skip_MODRM
}, 0 },
11003 { "vmlaunch", { Skip_MODRM
}, 0 },
11004 { "vmresume", { Skip_MODRM
}, 0 },
11005 { "vmxoff", { Skip_MODRM
}, 0 },
11006 { "pconfig", { Skip_MODRM
}, 0 },
11009 /* RM_0F01_REG_1 */
11010 { "monitor", { { OP_Monitor
, 0 } }, 0 },
11011 { "mwait", { { OP_Mwait
, 0 } }, 0 },
11012 { "clac", { Skip_MODRM
}, 0 },
11013 { "stac", { Skip_MODRM
}, 0 },
11017 { "encls", { Skip_MODRM
}, 0 },
11020 /* RM_0F01_REG_2 */
11021 { "xgetbv", { Skip_MODRM
}, 0 },
11022 { "xsetbv", { Skip_MODRM
}, 0 },
11025 { "vmfunc", { Skip_MODRM
}, 0 },
11026 { "xend", { Skip_MODRM
}, 0 },
11027 { "xtest", { Skip_MODRM
}, 0 },
11028 { "enclu", { Skip_MODRM
}, 0 },
11031 /* RM_0F01_REG_3 */
11032 { "vmrun", { Skip_MODRM
}, 0 },
11033 { "vmmcall", { Skip_MODRM
}, 0 },
11034 { "vmload", { Skip_MODRM
}, 0 },
11035 { "vmsave", { Skip_MODRM
}, 0 },
11036 { "stgi", { Skip_MODRM
}, 0 },
11037 { "clgi", { Skip_MODRM
}, 0 },
11038 { "skinit", { Skip_MODRM
}, 0 },
11039 { "invlpga", { Skip_MODRM
}, 0 },
11042 /* RM_0F01_REG_5 */
11043 { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_0
) },
11045 { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_2
) },
11049 { "rdpkru", { Skip_MODRM
}, 0 },
11050 { "wrpkru", { Skip_MODRM
}, 0 },
11053 /* RM_0F01_REG_7 */
11054 { "swapgs", { Skip_MODRM
}, 0 },
11055 { "rdtscp", { Skip_MODRM
}, 0 },
11056 { "monitorx", { { OP_Monitor
, 0 } }, 0 },
11057 { "mwaitx", { { OP_Mwaitx
, 0 } }, 0 },
11058 { "clzero", { Skip_MODRM
}, 0 },
11061 /* RM_0F1E_MOD_3_REG_7 */
11062 { "nopQ", { Ev
}, 0 },
11063 { "nopQ", { Ev
}, 0 },
11064 { "endbr64", { Skip_MODRM
}, PREFIX_OPCODE
},
11065 { "endbr32", { Skip_MODRM
}, PREFIX_OPCODE
},
11066 { "nopQ", { Ev
}, 0 },
11067 { "nopQ", { Ev
}, 0 },
11068 { "nopQ", { Ev
}, 0 },
11069 { "nopQ", { Ev
}, 0 },
11072 /* RM_0FAE_REG_6 */
11073 { "mfence", { Skip_MODRM
}, 0 },
11076 /* RM_0FAE_REG_7 */
11077 { "sfence", { Skip_MODRM
}, 0 },
11082 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
11084 /* We use the high bit to indicate different name for the same
11086 #define REP_PREFIX (0xf3 | 0x100)
11087 #define XACQUIRE_PREFIX (0xf2 | 0x200)
11088 #define XRELEASE_PREFIX (0xf3 | 0x400)
11089 #define BND_PREFIX (0xf2 | 0x400)
11090 #define NOTRACK_PREFIX (0x3e | 0x100)
11095 int newrex
, i
, length
;
11101 last_lock_prefix
= -1;
11102 last_repz_prefix
= -1;
11103 last_repnz_prefix
= -1;
11104 last_data_prefix
= -1;
11105 last_addr_prefix
= -1;
11106 last_rex_prefix
= -1;
11107 last_seg_prefix
= -1;
11109 active_seg_prefix
= 0;
11110 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
11111 all_prefixes
[i
] = 0;
11114 /* The maximum instruction length is 15bytes. */
11115 while (length
< MAX_CODE_LENGTH
- 1)
11117 FETCH_DATA (the_info
, codep
+ 1);
11121 /* REX prefixes family. */
11138 if (address_mode
== mode_64bit
)
11142 last_rex_prefix
= i
;
11145 prefixes
|= PREFIX_REPZ
;
11146 last_repz_prefix
= i
;
11149 prefixes
|= PREFIX_REPNZ
;
11150 last_repnz_prefix
= i
;
11153 prefixes
|= PREFIX_LOCK
;
11154 last_lock_prefix
= i
;
11157 prefixes
|= PREFIX_CS
;
11158 last_seg_prefix
= i
;
11159 active_seg_prefix
= PREFIX_CS
;
11162 prefixes
|= PREFIX_SS
;
11163 last_seg_prefix
= i
;
11164 active_seg_prefix
= PREFIX_SS
;
11167 prefixes
|= PREFIX_DS
;
11168 last_seg_prefix
= i
;
11169 active_seg_prefix
= PREFIX_DS
;
11172 prefixes
|= PREFIX_ES
;
11173 last_seg_prefix
= i
;
11174 active_seg_prefix
= PREFIX_ES
;
11177 prefixes
|= PREFIX_FS
;
11178 last_seg_prefix
= i
;
11179 active_seg_prefix
= PREFIX_FS
;
11182 prefixes
|= PREFIX_GS
;
11183 last_seg_prefix
= i
;
11184 active_seg_prefix
= PREFIX_GS
;
11187 prefixes
|= PREFIX_DATA
;
11188 last_data_prefix
= i
;
11191 prefixes
|= PREFIX_ADDR
;
11192 last_addr_prefix
= i
;
11195 /* fwait is really an instruction. If there are prefixes
11196 before the fwait, they belong to the fwait, *not* to the
11197 following instruction. */
11199 if (prefixes
|| rex
)
11201 prefixes
|= PREFIX_FWAIT
;
11203 /* This ensures that the previous REX prefixes are noticed
11204 as unused prefixes, as in the return case below. */
11208 prefixes
= PREFIX_FWAIT
;
11213 /* Rex is ignored when followed by another prefix. */
11219 if (*codep
!= FWAIT_OPCODE
)
11220 all_prefixes
[i
++] = *codep
;
11228 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
11231 static const char *
11232 prefix_name (int pref
, int sizeflag
)
11234 static const char *rexes
[16] =
11237 "rex.B", /* 0x41 */
11238 "rex.X", /* 0x42 */
11239 "rex.XB", /* 0x43 */
11240 "rex.R", /* 0x44 */
11241 "rex.RB", /* 0x45 */
11242 "rex.RX", /* 0x46 */
11243 "rex.RXB", /* 0x47 */
11244 "rex.W", /* 0x48 */
11245 "rex.WB", /* 0x49 */
11246 "rex.WX", /* 0x4a */
11247 "rex.WXB", /* 0x4b */
11248 "rex.WR", /* 0x4c */
11249 "rex.WRB", /* 0x4d */
11250 "rex.WRX", /* 0x4e */
11251 "rex.WRXB", /* 0x4f */
11256 /* REX prefixes family. */
11273 return rexes
[pref
- 0x40];
11293 return (sizeflag
& DFLAG
) ? "data16" : "data32";
11295 if (address_mode
== mode_64bit
)
11296 return (sizeflag
& AFLAG
) ? "addr32" : "addr64";
11298 return (sizeflag
& AFLAG
) ? "addr16" : "addr32";
11303 case XACQUIRE_PREFIX
:
11305 case XRELEASE_PREFIX
:
11309 case NOTRACK_PREFIX
:
11316 static char op_out
[MAX_OPERANDS
][100];
11317 static int op_ad
, op_index
[MAX_OPERANDS
];
11318 static int two_source_ops
;
11319 static bfd_vma op_address
[MAX_OPERANDS
];
11320 static bfd_vma op_riprel
[MAX_OPERANDS
];
11321 static bfd_vma start_pc
;
11324 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
11325 * (see topic "Redundant prefixes" in the "Differences from 8086"
11326 * section of the "Virtual 8086 Mode" chapter.)
11327 * 'pc' should be the address of this instruction, it will
11328 * be used to print the target address if this is a relative jump or call
11329 * The function returns the length of this instruction in bytes.
11332 static char intel_syntax
;
11333 static char intel_mnemonic
= !SYSV386_COMPAT
;
11334 static char open_char
;
11335 static char close_char
;
11336 static char separator_char
;
11337 static char scale_char
;
11345 static enum x86_64_isa isa64
;
11347 /* Here for backwards compatibility. When gdb stops using
11348 print_insn_i386_att and print_insn_i386_intel these functions can
11349 disappear, and print_insn_i386 be merged into print_insn. */
11351 print_insn_i386_att (bfd_vma pc
, disassemble_info
*info
)
11355 return print_insn (pc
, info
);
11359 print_insn_i386_intel (bfd_vma pc
, disassemble_info
*info
)
11363 return print_insn (pc
, info
);
11367 print_insn_i386 (bfd_vma pc
, disassemble_info
*info
)
11371 return print_insn (pc
, info
);
11375 print_i386_disassembler_options (FILE *stream
)
11377 fprintf (stream
, _("\n\
11378 The following i386/x86-64 specific disassembler options are supported for use\n\
11379 with the -M switch (multiple options should be separated by commas):\n"));
11381 fprintf (stream
, _(" x86-64 Disassemble in 64bit mode\n"));
11382 fprintf (stream
, _(" i386 Disassemble in 32bit mode\n"));
11383 fprintf (stream
, _(" i8086 Disassemble in 16bit mode\n"));
11384 fprintf (stream
, _(" att Display instruction in AT&T syntax\n"));
11385 fprintf (stream
, _(" intel Display instruction in Intel syntax\n"));
11386 fprintf (stream
, _(" att-mnemonic\n"
11387 " Display instruction in AT&T mnemonic\n"));
11388 fprintf (stream
, _(" intel-mnemonic\n"
11389 " Display instruction in Intel mnemonic\n"));
11390 fprintf (stream
, _(" addr64 Assume 64bit address size\n"));
11391 fprintf (stream
, _(" addr32 Assume 32bit address size\n"));
11392 fprintf (stream
, _(" addr16 Assume 16bit address size\n"));
11393 fprintf (stream
, _(" data32 Assume 32bit data size\n"));
11394 fprintf (stream
, _(" data16 Assume 16bit data size\n"));
11395 fprintf (stream
, _(" suffix Always display instruction suffix in AT&T syntax\n"));
11396 fprintf (stream
, _(" amd64 Display instruction in AMD64 ISA\n"));
11397 fprintf (stream
, _(" intel64 Display instruction in Intel64 ISA\n"));
11401 static const struct dis386 bad_opcode
= { "(bad)", { XX
}, 0 };
11403 /* Get a pointer to struct dis386 with a valid name. */
11405 static const struct dis386
*
11406 get_valid_dis386 (const struct dis386
*dp
, disassemble_info
*info
)
11408 int vindex
, vex_table_index
;
11410 if (dp
->name
!= NULL
)
11413 switch (dp
->op
[0].bytemode
)
11415 case USE_REG_TABLE
:
11416 dp
= ®_table
[dp
->op
[1].bytemode
][modrm
.reg
];
11419 case USE_MOD_TABLE
:
11420 vindex
= modrm
.mod
== 0x3 ? 1 : 0;
11421 dp
= &mod_table
[dp
->op
[1].bytemode
][vindex
];
11425 dp
= &rm_table
[dp
->op
[1].bytemode
][modrm
.rm
];
11428 case USE_PREFIX_TABLE
:
11431 /* The prefix in VEX is implicit. */
11432 switch (vex
.prefix
)
11437 case REPE_PREFIX_OPCODE
:
11440 case DATA_PREFIX_OPCODE
:
11443 case REPNE_PREFIX_OPCODE
:
11453 int last_prefix
= -1;
11456 /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
11457 When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
11459 if ((prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0)
11461 if (last_repz_prefix
> last_repnz_prefix
)
11464 prefix
= PREFIX_REPZ
;
11465 last_prefix
= last_repz_prefix
;
11470 prefix
= PREFIX_REPNZ
;
11471 last_prefix
= last_repnz_prefix
;
11474 /* Check if prefix should be ignored. */
11475 if ((((prefix_table
[dp
->op
[1].bytemode
][vindex
].prefix_requirement
11476 & PREFIX_IGNORED
) >> PREFIX_IGNORED_SHIFT
)
11481 if (vindex
== 0 && (prefixes
& PREFIX_DATA
) != 0)
11484 prefix
= PREFIX_DATA
;
11485 last_prefix
= last_data_prefix
;
11490 used_prefixes
|= prefix
;
11491 all_prefixes
[last_prefix
] = 0;
11494 dp
= &prefix_table
[dp
->op
[1].bytemode
][vindex
];
11497 case USE_X86_64_TABLE
:
11498 vindex
= address_mode
== mode_64bit
? 1 : 0;
11499 dp
= &x86_64_table
[dp
->op
[1].bytemode
][vindex
];
11502 case USE_3BYTE_TABLE
:
11503 FETCH_DATA (info
, codep
+ 2);
11505 dp
= &three_byte_table
[dp
->op
[1].bytemode
][vindex
];
11507 modrm
.mod
= (*codep
>> 6) & 3;
11508 modrm
.reg
= (*codep
>> 3) & 7;
11509 modrm
.rm
= *codep
& 7;
11512 case USE_VEX_LEN_TABLE
:
11516 switch (vex
.length
)
11529 dp
= &vex_len_table
[dp
->op
[1].bytemode
][vindex
];
11532 case USE_EVEX_LEN_TABLE
:
11536 switch (vex
.length
)
11552 dp
= &evex_len_table
[dp
->op
[1].bytemode
][vindex
];
11555 case USE_XOP_8F_TABLE
:
11556 FETCH_DATA (info
, codep
+ 3);
11557 /* All bits in the REX prefix are ignored. */
11559 rex
= ~(*codep
>> 5) & 0x7;
11561 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
11562 switch ((*codep
& 0x1f))
11568 vex_table_index
= XOP_08
;
11571 vex_table_index
= XOP_09
;
11574 vex_table_index
= XOP_0A
;
11578 vex
.w
= *codep
& 0x80;
11579 if (vex
.w
&& address_mode
== mode_64bit
)
11582 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11583 if (address_mode
!= mode_64bit
)
11585 /* In 16/32-bit mode REX_B is silently ignored. */
11589 vex
.length
= (*codep
& 0x4) ? 256 : 128;
11590 switch ((*codep
& 0x3))
11595 vex
.prefix
= DATA_PREFIX_OPCODE
;
11598 vex
.prefix
= REPE_PREFIX_OPCODE
;
11601 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11608 dp
= &xop_table
[vex_table_index
][vindex
];
11611 FETCH_DATA (info
, codep
+ 1);
11612 modrm
.mod
= (*codep
>> 6) & 3;
11613 modrm
.reg
= (*codep
>> 3) & 7;
11614 modrm
.rm
= *codep
& 7;
11617 case USE_VEX_C4_TABLE
:
11619 FETCH_DATA (info
, codep
+ 3);
11620 /* All bits in the REX prefix are ignored. */
11622 rex
= ~(*codep
>> 5) & 0x7;
11623 switch ((*codep
& 0x1f))
11629 vex_table_index
= VEX_0F
;
11632 vex_table_index
= VEX_0F38
;
11635 vex_table_index
= VEX_0F3A
;
11639 vex
.w
= *codep
& 0x80;
11640 if (address_mode
== mode_64bit
)
11647 /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
11648 is ignored, other REX bits are 0 and the highest bit in
11649 VEX.vvvv is also ignored (but we mustn't clear it here). */
11652 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11653 vex
.length
= (*codep
& 0x4) ? 256 : 128;
11654 switch ((*codep
& 0x3))
11659 vex
.prefix
= DATA_PREFIX_OPCODE
;
11662 vex
.prefix
= REPE_PREFIX_OPCODE
;
11665 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11672 dp
= &vex_table
[vex_table_index
][vindex
];
11674 /* There is no MODRM byte for VEX0F 77. */
11675 if (vex_table_index
!= VEX_0F
|| vindex
!= 0x77)
11677 FETCH_DATA (info
, codep
+ 1);
11678 modrm
.mod
= (*codep
>> 6) & 3;
11679 modrm
.reg
= (*codep
>> 3) & 7;
11680 modrm
.rm
= *codep
& 7;
11684 case USE_VEX_C5_TABLE
:
11686 FETCH_DATA (info
, codep
+ 2);
11687 /* All bits in the REX prefix are ignored. */
11689 rex
= (*codep
& 0x80) ? 0 : REX_R
;
11691 /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
11693 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11694 vex
.length
= (*codep
& 0x4) ? 256 : 128;
11695 switch ((*codep
& 0x3))
11700 vex
.prefix
= DATA_PREFIX_OPCODE
;
11703 vex
.prefix
= REPE_PREFIX_OPCODE
;
11706 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11713 dp
= &vex_table
[dp
->op
[1].bytemode
][vindex
];
11715 /* There is no MODRM byte for VEX 77. */
11716 if (vindex
!= 0x77)
11718 FETCH_DATA (info
, codep
+ 1);
11719 modrm
.mod
= (*codep
>> 6) & 3;
11720 modrm
.reg
= (*codep
>> 3) & 7;
11721 modrm
.rm
= *codep
& 7;
11725 case USE_VEX_W_TABLE
:
11729 dp
= &vex_w_table
[dp
->op
[1].bytemode
][vex
.w
? 1 : 0];
11732 case USE_EVEX_TABLE
:
11733 two_source_ops
= 0;
11736 FETCH_DATA (info
, codep
+ 4);
11737 /* All bits in the REX prefix are ignored. */
11739 /* The first byte after 0x62. */
11740 rex
= ~(*codep
>> 5) & 0x7;
11741 vex
.r
= *codep
& 0x10;
11742 switch ((*codep
& 0xf))
11745 return &bad_opcode
;
11747 vex_table_index
= EVEX_0F
;
11750 vex_table_index
= EVEX_0F38
;
11753 vex_table_index
= EVEX_0F3A
;
11757 /* The second byte after 0x62. */
11759 vex
.w
= *codep
& 0x80;
11760 if (vex
.w
&& address_mode
== mode_64bit
)
11763 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11766 if (!(*codep
& 0x4))
11767 return &bad_opcode
;
11769 switch ((*codep
& 0x3))
11774 vex
.prefix
= DATA_PREFIX_OPCODE
;
11777 vex
.prefix
= REPE_PREFIX_OPCODE
;
11780 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11784 /* The third byte after 0x62. */
11787 /* Remember the static rounding bits. */
11788 vex
.ll
= (*codep
>> 5) & 3;
11789 vex
.b
= (*codep
& 0x10) != 0;
11791 vex
.v
= *codep
& 0x8;
11792 vex
.mask_register_specifier
= *codep
& 0x7;
11793 vex
.zeroing
= *codep
& 0x80;
11795 if (address_mode
!= mode_64bit
)
11797 /* In 16/32-bit mode silently ignore following bits. */
11807 dp
= &evex_table
[vex_table_index
][vindex
];
11809 FETCH_DATA (info
, codep
+ 1);
11810 modrm
.mod
= (*codep
>> 6) & 3;
11811 modrm
.reg
= (*codep
>> 3) & 7;
11812 modrm
.rm
= *codep
& 7;
11814 /* Set vector length. */
11815 if (modrm
.mod
== 3 && vex
.b
)
11831 return &bad_opcode
;
11844 if (dp
->name
!= NULL
)
11847 return get_valid_dis386 (dp
, info
);
11851 get_sib (disassemble_info
*info
, int sizeflag
)
11853 /* If modrm.mod == 3, operand must be register. */
11855 && ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
11859 FETCH_DATA (info
, codep
+ 2);
11860 sib
.index
= (codep
[1] >> 3) & 7;
11861 sib
.scale
= (codep
[1] >> 6) & 3;
11862 sib
.base
= codep
[1] & 7;
11867 print_insn (bfd_vma pc
, disassemble_info
*info
)
11869 const struct dis386
*dp
;
11871 char *op_txt
[MAX_OPERANDS
];
11873 int sizeflag
, orig_sizeflag
;
11875 struct dis_private priv
;
11878 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
11879 if ((info
->mach
& bfd_mach_i386_i386
) != 0)
11880 address_mode
= mode_32bit
;
11881 else if (info
->mach
== bfd_mach_i386_i8086
)
11883 address_mode
= mode_16bit
;
11884 priv
.orig_sizeflag
= 0;
11887 address_mode
= mode_64bit
;
11889 if (intel_syntax
== (char) -1)
11890 intel_syntax
= (info
->mach
& bfd_mach_i386_intel_syntax
) != 0;
11892 for (p
= info
->disassembler_options
; p
!= NULL
; )
11894 if (CONST_STRNEQ (p
, "amd64"))
11896 else if (CONST_STRNEQ (p
, "intel64"))
11898 else if (CONST_STRNEQ (p
, "x86-64"))
11900 address_mode
= mode_64bit
;
11901 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
11903 else if (CONST_STRNEQ (p
, "i386"))
11905 address_mode
= mode_32bit
;
11906 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
11908 else if (CONST_STRNEQ (p
, "i8086"))
11910 address_mode
= mode_16bit
;
11911 priv
.orig_sizeflag
= 0;
11913 else if (CONST_STRNEQ (p
, "intel"))
11916 if (CONST_STRNEQ (p
+ 5, "-mnemonic"))
11917 intel_mnemonic
= 1;
11919 else if (CONST_STRNEQ (p
, "att"))
11922 if (CONST_STRNEQ (p
+ 3, "-mnemonic"))
11923 intel_mnemonic
= 0;
11925 else if (CONST_STRNEQ (p
, "addr"))
11927 if (address_mode
== mode_64bit
)
11929 if (p
[4] == '3' && p
[5] == '2')
11930 priv
.orig_sizeflag
&= ~AFLAG
;
11931 else if (p
[4] == '6' && p
[5] == '4')
11932 priv
.orig_sizeflag
|= AFLAG
;
11936 if (p
[4] == '1' && p
[5] == '6')
11937 priv
.orig_sizeflag
&= ~AFLAG
;
11938 else if (p
[4] == '3' && p
[5] == '2')
11939 priv
.orig_sizeflag
|= AFLAG
;
11942 else if (CONST_STRNEQ (p
, "data"))
11944 if (p
[4] == '1' && p
[5] == '6')
11945 priv
.orig_sizeflag
&= ~DFLAG
;
11946 else if (p
[4] == '3' && p
[5] == '2')
11947 priv
.orig_sizeflag
|= DFLAG
;
11949 else if (CONST_STRNEQ (p
, "suffix"))
11950 priv
.orig_sizeflag
|= SUFFIX_ALWAYS
;
11952 p
= strchr (p
, ',');
11957 if (address_mode
== mode_64bit
&& sizeof (bfd_vma
) < 8)
11959 (*info
->fprintf_func
) (info
->stream
,
11960 _("64-bit address is disabled"));
11966 names64
= intel_names64
;
11967 names32
= intel_names32
;
11968 names16
= intel_names16
;
11969 names8
= intel_names8
;
11970 names8rex
= intel_names8rex
;
11971 names_seg
= intel_names_seg
;
11972 names_mm
= intel_names_mm
;
11973 names_bnd
= intel_names_bnd
;
11974 names_xmm
= intel_names_xmm
;
11975 names_ymm
= intel_names_ymm
;
11976 names_zmm
= intel_names_zmm
;
11977 index64
= intel_index64
;
11978 index32
= intel_index32
;
11979 names_mask
= intel_names_mask
;
11980 index16
= intel_index16
;
11983 separator_char
= '+';
11988 names64
= att_names64
;
11989 names32
= att_names32
;
11990 names16
= att_names16
;
11991 names8
= att_names8
;
11992 names8rex
= att_names8rex
;
11993 names_seg
= att_names_seg
;
11994 names_mm
= att_names_mm
;
11995 names_bnd
= att_names_bnd
;
11996 names_xmm
= att_names_xmm
;
11997 names_ymm
= att_names_ymm
;
11998 names_zmm
= att_names_zmm
;
11999 index64
= att_index64
;
12000 index32
= att_index32
;
12001 names_mask
= att_names_mask
;
12002 index16
= att_index16
;
12005 separator_char
= ',';
12009 /* The output looks better if we put 7 bytes on a line, since that
12010 puts most long word instructions on a single line. Use 8 bytes
12012 if ((info
->mach
& bfd_mach_l1om
) != 0)
12013 info
->bytes_per_line
= 8;
12015 info
->bytes_per_line
= 7;
12017 info
->private_data
= &priv
;
12018 priv
.max_fetched
= priv
.the_buffer
;
12019 priv
.insn_start
= pc
;
12022 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12030 start_codep
= priv
.the_buffer
;
12031 codep
= priv
.the_buffer
;
12033 if (OPCODES_SIGSETJMP (priv
.bailout
) != 0)
12037 /* Getting here means we tried for data but didn't get it. That
12038 means we have an incomplete instruction of some sort. Just
12039 print the first byte as a prefix or a .byte pseudo-op. */
12040 if (codep
> priv
.the_buffer
)
12042 name
= prefix_name (priv
.the_buffer
[0], priv
.orig_sizeflag
);
12044 (*info
->fprintf_func
) (info
->stream
, "%s", name
);
12047 /* Just print the first byte as a .byte instruction. */
12048 (*info
->fprintf_func
) (info
->stream
, ".byte 0x%x",
12049 (unsigned int) priv
.the_buffer
[0]);
12059 sizeflag
= priv
.orig_sizeflag
;
12061 if (!ckprefix () || rex_used
)
12063 /* Too many prefixes or unused REX prefixes. */
12065 i
< (int) ARRAY_SIZE (all_prefixes
) && all_prefixes
[i
];
12067 (*info
->fprintf_func
) (info
->stream
, "%s%s",
12069 prefix_name (all_prefixes
[i
], sizeflag
));
12073 insn_codep
= codep
;
12075 FETCH_DATA (info
, codep
+ 1);
12076 two_source_ops
= (*codep
== 0x62) || (*codep
== 0xc8);
12078 if (((prefixes
& PREFIX_FWAIT
)
12079 && ((*codep
< 0xd8) || (*codep
> 0xdf))))
12081 /* Handle prefixes before fwait. */
12082 for (i
= 0; i
< fwait_prefix
&& all_prefixes
[i
];
12084 (*info
->fprintf_func
) (info
->stream
, "%s ",
12085 prefix_name (all_prefixes
[i
], sizeflag
));
12086 (*info
->fprintf_func
) (info
->stream
, "fwait");
12090 if (*codep
== 0x0f)
12092 unsigned char threebyte
;
12095 FETCH_DATA (info
, codep
+ 1);
12096 threebyte
= *codep
;
12097 dp
= &dis386_twobyte
[threebyte
];
12098 need_modrm
= twobyte_has_modrm
[*codep
];
12103 dp
= &dis386
[*codep
];
12104 need_modrm
= onebyte_has_modrm
[*codep
];
12108 /* Save sizeflag for printing the extra prefixes later before updating
12109 it for mnemonic and operand processing. The prefix names depend
12110 only on the address mode. */
12111 orig_sizeflag
= sizeflag
;
12112 if (prefixes
& PREFIX_ADDR
)
12114 if ((prefixes
& PREFIX_DATA
))
12120 FETCH_DATA (info
, codep
+ 1);
12121 modrm
.mod
= (*codep
>> 6) & 3;
12122 modrm
.reg
= (*codep
>> 3) & 7;
12123 modrm
.rm
= *codep
& 7;
12129 memset (&vex
, 0, sizeof (vex
));
12131 if (dp
->name
== NULL
&& dp
->op
[0].bytemode
== FLOATCODE
)
12133 get_sib (info
, sizeflag
);
12134 dofloat (sizeflag
);
12138 dp
= get_valid_dis386 (dp
, info
);
12139 if (dp
!= NULL
&& putop (dp
->name
, sizeflag
) == 0)
12141 get_sib (info
, sizeflag
);
12142 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12145 op_ad
= MAX_OPERANDS
- 1 - i
;
12147 (*dp
->op
[i
].rtn
) (dp
->op
[i
].bytemode
, sizeflag
);
12148 /* For EVEX instruction after the last operand masking
12149 should be printed. */
12150 if (i
== 0 && vex
.evex
)
12152 /* Don't print {%k0}. */
12153 if (vex
.mask_register_specifier
)
12156 oappend (names_mask
[vex
.mask_register_specifier
]);
12166 /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
12167 are all 0s in inverted form. */
12168 if (need_vex
&& vex
.register_specifier
!= 0)
12170 (*info
->fprintf_func
) (info
->stream
, "(bad)");
12171 return end_codep
- priv
.the_buffer
;
12174 /* Check if the REX prefix is used. */
12175 if (rex_ignored
== 0 && (rex
^ rex_used
) == 0 && last_rex_prefix
>= 0)
12176 all_prefixes
[last_rex_prefix
] = 0;
12178 /* Check if the SEG prefix is used. */
12179 if ((prefixes
& (PREFIX_CS
| PREFIX_SS
| PREFIX_DS
| PREFIX_ES
12180 | PREFIX_FS
| PREFIX_GS
)) != 0
12181 && (used_prefixes
& active_seg_prefix
) != 0)
12182 all_prefixes
[last_seg_prefix
] = 0;
12184 /* Check if the ADDR prefix is used. */
12185 if ((prefixes
& PREFIX_ADDR
) != 0
12186 && (used_prefixes
& PREFIX_ADDR
) != 0)
12187 all_prefixes
[last_addr_prefix
] = 0;
12189 /* Check if the DATA prefix is used. */
12190 if ((prefixes
& PREFIX_DATA
) != 0
12191 && (used_prefixes
& PREFIX_DATA
) != 0)
12192 all_prefixes
[last_data_prefix
] = 0;
12194 /* Print the extra prefixes. */
12196 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
12197 if (all_prefixes
[i
])
12200 name
= prefix_name (all_prefixes
[i
], orig_sizeflag
);
12203 prefix_length
+= strlen (name
) + 1;
12204 (*info
->fprintf_func
) (info
->stream
, "%s ", name
);
12207 /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
12208 unused, opcode is invalid. Since the PREFIX_DATA prefix may be
12209 used by putop and MMX/SSE operand and may be overriden by the
12210 PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
12212 if (dp
->prefix_requirement
== PREFIX_OPCODE
12213 && dp
!= &bad_opcode
12215 & (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0
12217 & (PREFIX_REPZ
| PREFIX_REPNZ
)) == 0)
12219 & (PREFIX_REPZ
| PREFIX_REPNZ
| PREFIX_DATA
))
12221 && (used_prefixes
& PREFIX_DATA
) == 0))))
12223 (*info
->fprintf_func
) (info
->stream
, "(bad)");
12224 return end_codep
- priv
.the_buffer
;
12227 /* Check maximum code length. */
12228 if ((codep
- start_codep
) > MAX_CODE_LENGTH
)
12230 (*info
->fprintf_func
) (info
->stream
, "(bad)");
12231 return MAX_CODE_LENGTH
;
12234 obufp
= mnemonicendp
;
12235 for (i
= strlen (obuf
) + prefix_length
; i
< 6; i
++)
12238 (*info
->fprintf_func
) (info
->stream
, "%s", obuf
);
12240 /* The enter and bound instructions are printed with operands in the same
12241 order as the intel book; everything else is printed in reverse order. */
12242 if (intel_syntax
|| two_source_ops
)
12246 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12247 op_txt
[i
] = op_out
[i
];
12249 if (intel_syntax
&& dp
&& dp
->op
[2].rtn
== OP_Rounding
12250 && dp
->op
[3].rtn
== OP_E
&& dp
->op
[4].rtn
== NULL
)
12252 op_txt
[2] = op_out
[3];
12253 op_txt
[3] = op_out
[2];
12256 for (i
= 0; i
< (MAX_OPERANDS
>> 1); ++i
)
12258 op_ad
= op_index
[i
];
12259 op_index
[i
] = op_index
[MAX_OPERANDS
- 1 - i
];
12260 op_index
[MAX_OPERANDS
- 1 - i
] = op_ad
;
12261 riprel
= op_riprel
[i
];
12262 op_riprel
[i
] = op_riprel
[MAX_OPERANDS
- 1 - i
];
12263 op_riprel
[MAX_OPERANDS
- 1 - i
] = riprel
;
12268 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12269 op_txt
[MAX_OPERANDS
- 1 - i
] = op_out
[i
];
12273 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12277 (*info
->fprintf_func
) (info
->stream
, ",");
12278 if (op_index
[i
] != -1 && !op_riprel
[i
])
12279 (*info
->print_address_func
) ((bfd_vma
) op_address
[op_index
[i
]], info
);
12281 (*info
->fprintf_func
) (info
->stream
, "%s", op_txt
[i
]);
12285 for (i
= 0; i
< MAX_OPERANDS
; i
++)
12286 if (op_index
[i
] != -1 && op_riprel
[i
])
12288 (*info
->fprintf_func
) (info
->stream
, " # ");
12289 (*info
->print_address_func
) ((bfd_vma
) (start_pc
+ (codep
- start_codep
)
12290 + op_address
[op_index
[i
]]), info
);
12293 return codep
- priv
.the_buffer
;
12296 static const char *float_mem
[] = {
12371 static const unsigned char float_mem_mode
[] = {
12446 #define ST { OP_ST, 0 }
12447 #define STi { OP_STi, 0 }
12449 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
12450 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
12451 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
12452 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
12453 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
12454 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
12455 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
12456 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
12457 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
12459 static const struct dis386 float_reg
[][8] = {
12462 { "fadd", { ST
, STi
}, 0 },
12463 { "fmul", { ST
, STi
}, 0 },
12464 { "fcom", { STi
}, 0 },
12465 { "fcomp", { STi
}, 0 },
12466 { "fsub", { ST
, STi
}, 0 },
12467 { "fsubr", { ST
, STi
}, 0 },
12468 { "fdiv", { ST
, STi
}, 0 },
12469 { "fdivr", { ST
, STi
}, 0 },
12473 { "fld", { STi
}, 0 },
12474 { "fxch", { STi
}, 0 },
12484 { "fcmovb", { ST
, STi
}, 0 },
12485 { "fcmove", { ST
, STi
}, 0 },
12486 { "fcmovbe",{ ST
, STi
}, 0 },
12487 { "fcmovu", { ST
, STi
}, 0 },
12495 { "fcmovnb",{ ST
, STi
}, 0 },
12496 { "fcmovne",{ ST
, STi
}, 0 },
12497 { "fcmovnbe",{ ST
, STi
}, 0 },
12498 { "fcmovnu",{ ST
, STi
}, 0 },
12500 { "fucomi", { ST
, STi
}, 0 },
12501 { "fcomi", { ST
, STi
}, 0 },
12506 { "fadd", { STi
, ST
}, 0 },
12507 { "fmul", { STi
, ST
}, 0 },
12510 { "fsub{!M|r}", { STi
, ST
}, 0 },
12511 { "fsub{M|}", { STi
, ST
}, 0 },
12512 { "fdiv{!M|r}", { STi
, ST
}, 0 },
12513 { "fdiv{M|}", { STi
, ST
}, 0 },
12517 { "ffree", { STi
}, 0 },
12519 { "fst", { STi
}, 0 },
12520 { "fstp", { STi
}, 0 },
12521 { "fucom", { STi
}, 0 },
12522 { "fucomp", { STi
}, 0 },
12528 { "faddp", { STi
, ST
}, 0 },
12529 { "fmulp", { STi
, ST
}, 0 },
12532 { "fsub{!M|r}p", { STi
, ST
}, 0 },
12533 { "fsub{M|}p", { STi
, ST
}, 0 },
12534 { "fdiv{!M|r}p", { STi
, ST
}, 0 },
12535 { "fdiv{M|}p", { STi
, ST
}, 0 },
12539 { "ffreep", { STi
}, 0 },
12544 { "fucomip", { ST
, STi
}, 0 },
12545 { "fcomip", { ST
, STi
}, 0 },
12550 static char *fgrps
[][8] = {
12553 "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12558 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12563 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
12568 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
12573 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
12578 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
12583 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12588 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
12589 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
12594 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12599 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12604 swap_operand (void)
12606 mnemonicendp
[0] = '.';
12607 mnemonicendp
[1] = 's';
12612 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED
,
12613 int sizeflag ATTRIBUTE_UNUSED
)
12615 /* Skip mod/rm byte. */
12621 dofloat (int sizeflag
)
12623 const struct dis386
*dp
;
12624 unsigned char floatop
;
12626 floatop
= codep
[-1];
12628 if (modrm
.mod
!= 3)
12630 int fp_indx
= (floatop
- 0xd8) * 8 + modrm
.reg
;
12632 putop (float_mem
[fp_indx
], sizeflag
);
12635 OP_E (float_mem_mode
[fp_indx
], sizeflag
);
12638 /* Skip mod/rm byte. */
12642 dp
= &float_reg
[floatop
- 0xd8][modrm
.reg
];
12643 if (dp
->name
== NULL
)
12645 putop (fgrps
[dp
->op
[0].bytemode
][modrm
.rm
], sizeflag
);
12647 /* Instruction fnstsw is only one with strange arg. */
12648 if (floatop
== 0xdf && codep
[-1] == 0xe0)
12649 strcpy (op_out
[0], names16
[0]);
12653 putop (dp
->name
, sizeflag
);
12658 (*dp
->op
[0].rtn
) (dp
->op
[0].bytemode
, sizeflag
);
12663 (*dp
->op
[1].rtn
) (dp
->op
[1].bytemode
, sizeflag
);
12667 /* Like oappend (below), but S is a string starting with '%'.
12668 In Intel syntax, the '%' is elided. */
12670 oappend_maybe_intel (const char *s
)
12672 oappend (s
+ intel_syntax
);
12676 OP_ST (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
12678 oappend_maybe_intel ("%st");
12682 OP_STi (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
12684 sprintf (scratchbuf
, "%%st(%d)", modrm
.rm
);
12685 oappend_maybe_intel (scratchbuf
);
12688 /* Capital letters in template are macros. */
12690 putop (const char *in_template
, int sizeflag
)
12695 unsigned int l
= 0, len
= 1;
12698 #define SAVE_LAST(c) \
12699 if (l < len && l < sizeof (last)) \
12704 for (p
= in_template
; *p
; p
++)
12720 while (*++p
!= '|')
12721 if (*p
== '}' || *p
== '\0')
12724 /* Fall through. */
12729 while (*++p
!= '}')
12740 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
12744 if (l
== 0 && len
== 1)
12749 if (sizeflag
& SUFFIX_ALWAYS
)
12762 if (address_mode
== mode_64bit
12763 && !(prefixes
& PREFIX_ADDR
))
12774 if (intel_syntax
&& !alt
)
12776 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
12778 if (sizeflag
& DFLAG
)
12779 *obufp
++ = intel_syntax
? 'd' : 'l';
12781 *obufp
++ = intel_syntax
? 'w' : 's';
12782 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12786 if (intel_syntax
|| !(sizeflag
& SUFFIX_ALWAYS
))
12789 if (modrm
.mod
== 3)
12795 if (sizeflag
& DFLAG
)
12796 *obufp
++ = intel_syntax
? 'd' : 'l';
12799 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12805 case 'E': /* For jcxz/jecxz */
12806 if (address_mode
== mode_64bit
)
12808 if (sizeflag
& AFLAG
)
12814 if (sizeflag
& AFLAG
)
12816 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
12821 if ((prefixes
& PREFIX_ADDR
) || (sizeflag
& SUFFIX_ALWAYS
))
12823 if (sizeflag
& AFLAG
)
12824 *obufp
++ = address_mode
== mode_64bit
? 'q' : 'l';
12826 *obufp
++ = address_mode
== mode_64bit
? 'l' : 'w';
12827 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
12831 if (intel_syntax
|| (obufp
[-1] != 's' && !(sizeflag
& SUFFIX_ALWAYS
)))
12833 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
12837 if (!(rex
& REX_W
))
12838 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12843 if ((prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_CS
12844 || (prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_DS
)
12846 used_prefixes
|= prefixes
& (PREFIX_CS
| PREFIX_DS
);
12849 if (prefixes
& PREFIX_DS
)
12868 if (l
!= 0 || len
!= 1)
12870 if (l
!= 1 || len
!= 2 || last
[0] != 'X')
12875 if (!need_vex
|| !vex
.evex
)
12878 || ((modrm
.mod
== 3 || vex
.b
) && !(sizeflag
& SUFFIX_ALWAYS
)))
12880 switch (vex
.length
)
12898 if (address_mode
== mode_64bit
&& (sizeflag
& SUFFIX_ALWAYS
))
12903 /* Fall through. */
12906 if (l
!= 0 || len
!= 1)
12914 if (sizeflag
& SUFFIX_ALWAYS
)
12918 if (intel_mnemonic
!= cond
)
12922 if ((prefixes
& PREFIX_FWAIT
) == 0)
12925 used_prefixes
|= PREFIX_FWAIT
;
12931 else if (intel_syntax
&& (sizeflag
& DFLAG
))
12935 if (!(rex
& REX_W
))
12936 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12940 && address_mode
== mode_64bit
12941 && isa64
== intel64
)
12946 /* Fall through. */
12949 && address_mode
== mode_64bit
12950 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
12955 /* Fall through. */
12958 if (l
== 0 && len
== 1)
12963 if ((rex
& REX_W
) == 0
12964 && (prefixes
& PREFIX_DATA
))
12966 if ((sizeflag
& DFLAG
) == 0)
12968 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12972 if ((prefixes
& PREFIX_DATA
)
12974 || (sizeflag
& SUFFIX_ALWAYS
))
12981 if (sizeflag
& DFLAG
)
12985 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12991 if (l
!= 1 || len
!= 2 || last
[0] != 'L')
12997 if ((prefixes
& PREFIX_DATA
)
12999 || (sizeflag
& SUFFIX_ALWAYS
))
13006 if (sizeflag
& DFLAG
)
13007 *obufp
++ = intel_syntax
? 'd' : 'l';
13010 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13018 if (address_mode
== mode_64bit
13019 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13021 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
13025 /* Fall through. */
13028 if (l
== 0 && len
== 1)
13031 if (intel_syntax
&& !alt
)
13034 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
13040 if (sizeflag
& DFLAG
)
13041 *obufp
++ = intel_syntax
? 'd' : 'l';
13044 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13050 if (l
!= 1 || len
!= 2 || last
[0] != 'L')
13056 || (modrm
.mod
== 3 && !(sizeflag
& SUFFIX_ALWAYS
)))
13071 else if (sizeflag
& DFLAG
)
13080 if (intel_syntax
&& !p
[1]
13081 && ((rex
& REX_W
) || (sizeflag
& DFLAG
)))
13083 if (!(rex
& REX_W
))
13084 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13087 if (l
== 0 && len
== 1)
13091 if (address_mode
== mode_64bit
13092 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13094 if (sizeflag
& SUFFIX_ALWAYS
)
13116 /* Fall through. */
13119 if (l
== 0 && len
== 1)
13124 if (sizeflag
& SUFFIX_ALWAYS
)
13130 if (sizeflag
& DFLAG
)
13134 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13148 if (address_mode
== mode_64bit
13149 && !(prefixes
& PREFIX_ADDR
))
13160 if (l
!= 0 || len
!= 1)
13165 if (need_vex
&& vex
.prefix
)
13167 if (vex
.prefix
== DATA_PREFIX_OPCODE
)
13174 if (prefixes
& PREFIX_DATA
)
13178 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13182 if (l
== 0 && len
== 1)
13186 if (l
!= 1 || len
!= 2 || last
[0] != 'X')
13194 || ((modrm
.mod
== 3 || vex
.b
) && !(sizeflag
& SUFFIX_ALWAYS
)))
13196 switch (vex
.length
)
13212 if (l
== 0 && len
== 1)
13214 /* operand size flag for cwtl, cbtw */
13223 else if (sizeflag
& DFLAG
)
13227 if (!(rex
& REX_W
))
13228 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13235 && last
[0] != 'L'))
13242 if (last
[0] == 'X')
13243 *obufp
++ = vex
.w
? 'd': 's';
13245 *obufp
++ = vex
.w
? 'q': 'd';
13251 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
13253 if (sizeflag
& DFLAG
)
13257 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13263 if (address_mode
== mode_64bit
13264 && (isa64
== intel64
13265 || ((sizeflag
& DFLAG
) || (rex
& REX_W
))))
13267 else if ((prefixes
& PREFIX_DATA
))
13269 if (!(sizeflag
& DFLAG
))
13271 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13278 mnemonicendp
= obufp
;
13283 oappend (const char *s
)
13285 obufp
= stpcpy (obufp
, s
);
13291 /* Only print the active segment register. */
13292 if (!active_seg_prefix
)
13295 used_prefixes
|= active_seg_prefix
;
13296 switch (active_seg_prefix
)
13299 oappend_maybe_intel ("%cs:");
13302 oappend_maybe_intel ("%ds:");
13305 oappend_maybe_intel ("%ss:");
13308 oappend_maybe_intel ("%es:");
13311 oappend_maybe_intel ("%fs:");
13314 oappend_maybe_intel ("%gs:");
13322 OP_indirE (int bytemode
, int sizeflag
)
13326 OP_E (bytemode
, sizeflag
);
13330 print_operand_value (char *buf
, int hex
, bfd_vma disp
)
13332 if (address_mode
== mode_64bit
)
13340 sprintf_vma (tmp
, disp
);
13341 for (i
= 0; tmp
[i
] == '0' && tmp
[i
+ 1]; i
++);
13342 strcpy (buf
+ 2, tmp
+ i
);
13346 bfd_signed_vma v
= disp
;
13353 /* Check for possible overflow on 0x8000000000000000. */
13356 strcpy (buf
, "9223372036854775808");
13370 tmp
[28 - i
] = (v
% 10) + '0';
13374 strcpy (buf
, tmp
+ 29 - i
);
13380 sprintf (buf
, "0x%x", (unsigned int) disp
);
13382 sprintf (buf
, "%d", (int) disp
);
13386 /* Put DISP in BUF as signed hex number. */
13389 print_displacement (char *buf
, bfd_vma disp
)
13391 bfd_signed_vma val
= disp
;
13400 /* Check for possible overflow. */
13403 switch (address_mode
)
13406 strcpy (buf
+ j
, "0x8000000000000000");
13409 strcpy (buf
+ j
, "0x80000000");
13412 strcpy (buf
+ j
, "0x8000");
13422 sprintf_vma (tmp
, (bfd_vma
) val
);
13423 for (i
= 0; tmp
[i
] == '0'; i
++)
13425 if (tmp
[i
] == '\0')
13427 strcpy (buf
+ j
, tmp
+ i
);
13431 intel_operand_size (int bytemode
, int sizeflag
)
13435 && (bytemode
== x_mode
13436 || bytemode
== evex_half_bcst_xmmq_mode
))
13439 oappend ("QWORD PTR ");
13441 oappend ("DWORD PTR ");
13450 oappend ("BYTE PTR ");
13455 oappend ("WORD PTR ");
13458 if (address_mode
== mode_64bit
&& isa64
== intel64
)
13460 oappend ("QWORD PTR ");
13463 /* Fall through. */
13465 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13467 oappend ("QWORD PTR ");
13470 /* Fall through. */
13476 oappend ("QWORD PTR ");
13479 if ((sizeflag
& DFLAG
) || bytemode
== dq_mode
)
13480 oappend ("DWORD PTR ");
13482 oappend ("WORD PTR ");
13483 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13487 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
13489 oappend ("WORD PTR ");
13490 if (!(rex
& REX_W
))
13491 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13494 if (sizeflag
& DFLAG
)
13495 oappend ("QWORD PTR ");
13497 oappend ("DWORD PTR ");
13498 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13501 case d_scalar_mode
:
13502 case d_scalar_swap_mode
:
13505 oappend ("DWORD PTR ");
13508 case q_scalar_mode
:
13509 case q_scalar_swap_mode
:
13511 oappend ("QWORD PTR ");
13515 if (address_mode
== mode_64bit
)
13516 oappend ("QWORD PTR ");
13518 oappend ("DWORD PTR ");
13521 if (sizeflag
& DFLAG
)
13522 oappend ("FWORD PTR ");
13524 oappend ("DWORD PTR ");
13525 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13528 oappend ("TBYTE PTR ");
13532 case evex_x_gscat_mode
:
13533 case evex_x_nobcst_mode
:
13534 case b_scalar_mode
:
13535 case w_scalar_mode
:
13538 switch (vex
.length
)
13541 oappend ("XMMWORD PTR ");
13544 oappend ("YMMWORD PTR ");
13547 oappend ("ZMMWORD PTR ");
13554 oappend ("XMMWORD PTR ");
13557 oappend ("XMMWORD PTR ");
13560 oappend ("YMMWORD PTR ");
13563 case evex_half_bcst_xmmq_mode
:
13567 switch (vex
.length
)
13570 oappend ("QWORD PTR ");
13573 oappend ("XMMWORD PTR ");
13576 oappend ("YMMWORD PTR ");
13586 switch (vex
.length
)
13591 oappend ("BYTE PTR ");
13601 switch (vex
.length
)
13606 oappend ("WORD PTR ");
13616 switch (vex
.length
)
13621 oappend ("DWORD PTR ");
13631 switch (vex
.length
)
13636 oappend ("QWORD PTR ");
13646 switch (vex
.length
)
13649 oappend ("WORD PTR ");
13652 oappend ("DWORD PTR ");
13655 oappend ("QWORD PTR ");
13665 switch (vex
.length
)
13668 oappend ("DWORD PTR ");
13671 oappend ("QWORD PTR ");
13674 oappend ("XMMWORD PTR ");
13684 switch (vex
.length
)
13687 oappend ("QWORD PTR ");
13690 oappend ("YMMWORD PTR ");
13693 oappend ("ZMMWORD PTR ");
13703 switch (vex
.length
)
13707 oappend ("XMMWORD PTR ");
13714 oappend ("OWORD PTR ");
13717 case vex_w_dq_mode
:
13718 case vex_scalar_w_dq_mode
:
13723 oappend ("QWORD PTR ");
13725 oappend ("DWORD PTR ");
13727 case vex_vsib_d_w_dq_mode
:
13728 case vex_vsib_q_w_dq_mode
:
13735 oappend ("QWORD PTR ");
13737 oappend ("DWORD PTR ");
13741 switch (vex
.length
)
13744 oappend ("XMMWORD PTR ");
13747 oappend ("YMMWORD PTR ");
13750 oappend ("ZMMWORD PTR ");
13757 case vex_vsib_q_w_d_mode
:
13758 case vex_vsib_d_w_d_mode
:
13759 if (!need_vex
|| !vex
.evex
)
13762 switch (vex
.length
)
13765 oappend ("QWORD PTR ");
13768 oappend ("XMMWORD PTR ");
13771 oappend ("YMMWORD PTR ");
13779 if (!need_vex
|| vex
.length
!= 128)
13782 oappend ("DWORD PTR ");
13784 oappend ("BYTE PTR ");
13790 oappend ("QWORD PTR ");
13792 oappend ("WORD PTR ");
13802 OP_E_register (int bytemode
, int sizeflag
)
13804 int reg
= modrm
.rm
;
13805 const char **names
;
13811 if ((sizeflag
& SUFFIX_ALWAYS
)
13812 && (bytemode
== b_swap_mode
13813 || bytemode
== bnd_swap_mode
13814 || bytemode
== v_swap_mode
))
13840 names
= address_mode
== mode_64bit
? names64
: names32
;
13843 case bnd_swap_mode
:
13852 if (address_mode
== mode_64bit
&& isa64
== intel64
)
13857 /* Fall through. */
13859 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13865 /* Fall through. */
13878 if ((sizeflag
& DFLAG
)
13879 || (bytemode
!= v_mode
13880 && bytemode
!= v_swap_mode
))
13884 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13888 names
= (address_mode
== mode_64bit
13889 ? names64
: names32
);
13890 if (!(prefixes
& PREFIX_ADDR
))
13891 names
= (address_mode
== mode_16bit
13892 ? names16
: names
);
13895 /* Remove "addr16/addr32". */
13896 all_prefixes
[last_addr_prefix
] = 0;
13897 names
= (address_mode
!= mode_32bit
13898 ? names32
: names16
);
13899 used_prefixes
|= PREFIX_ADDR
;
13909 names
= names_mask
;
13914 oappend (INTERNAL_DISASSEMBLER_ERROR
);
13917 oappend (names
[reg
]);
13921 OP_E_memory (int bytemode
, int sizeflag
)
13924 int add
= (rex
& REX_B
) ? 8 : 0;
13930 /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */
13932 && bytemode
!= x_mode
13933 && bytemode
!= xmmq_mode
13934 && bytemode
!= evex_half_bcst_xmmq_mode
)
13950 if (address_mode
!= mode_64bit
)
13956 case vex_vsib_d_w_dq_mode
:
13957 case vex_vsib_d_w_d_mode
:
13958 case vex_vsib_q_w_dq_mode
:
13959 case vex_vsib_q_w_d_mode
:
13960 case evex_x_gscat_mode
:
13962 shift
= vex
.w
? 3 : 2;
13965 case evex_half_bcst_xmmq_mode
:
13969 shift
= vex
.w
? 3 : 2;
13972 /* Fall through. */
13976 case evex_x_nobcst_mode
:
13978 switch (vex
.length
)
14001 case q_scalar_mode
:
14003 case q_scalar_swap_mode
:
14009 case d_scalar_mode
:
14011 case d_scalar_swap_mode
:
14014 case w_scalar_mode
:
14018 case b_scalar_mode
:
14023 shift
= address_mode
== mode_64bit
? 3 : 2;
14028 /* Make necessary corrections to shift for modes that need it.
14029 For these modes we currently have shift 4, 5 or 6 depending on
14030 vex.length (it corresponds to xmmword, ymmword or zmmword
14031 operand). We might want to make it 3, 4 or 5 (e.g. for
14032 xmmq_mode). In case of broadcast enabled the corrections
14033 aren't needed, as element size is always 32 or 64 bits. */
14035 && (bytemode
== xmmq_mode
14036 || bytemode
== evex_half_bcst_xmmq_mode
))
14038 else if (bytemode
== xmmqd_mode
)
14040 else if (bytemode
== xmmdw_mode
)
14042 else if (bytemode
== ymmq_mode
&& vex
.length
== 128)
14050 intel_operand_size (bytemode
, sizeflag
);
14053 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
14055 /* 32/64 bit address mode */
14065 int addr32flag
= !((sizeflag
& AFLAG
)
14066 || bytemode
== v_bnd_mode
14067 || bytemode
== v_bndmk_mode
14068 || bytemode
== bnd_mode
14069 || bytemode
== bnd_swap_mode
);
14070 const char **indexes64
= names64
;
14071 const char **indexes32
= names32
;
14081 vindex
= sib
.index
;
14087 case vex_vsib_d_w_dq_mode
:
14088 case vex_vsib_d_w_d_mode
:
14089 case vex_vsib_q_w_dq_mode
:
14090 case vex_vsib_q_w_d_mode
:
14100 switch (vex
.length
)
14103 indexes64
= indexes32
= names_xmm
;
14107 || bytemode
== vex_vsib_q_w_dq_mode
14108 || bytemode
== vex_vsib_q_w_d_mode
)
14109 indexes64
= indexes32
= names_ymm
;
14111 indexes64
= indexes32
= names_xmm
;
14115 || bytemode
== vex_vsib_q_w_dq_mode
14116 || bytemode
== vex_vsib_q_w_d_mode
)
14117 indexes64
= indexes32
= names_zmm
;
14119 indexes64
= indexes32
= names_ymm
;
14126 haveindex
= vindex
!= 4;
14133 rbase
= base
+ add
;
14141 if (address_mode
== mode_64bit
&& !havesib
)
14144 if (riprel
&& bytemode
== v_bndmk_mode
)
14152 FETCH_DATA (the_info
, codep
+ 1);
14154 if ((disp
& 0x80) != 0)
14156 if (vex
.evex
&& shift
> 0)
14169 && address_mode
!= mode_16bit
)
14171 if (address_mode
== mode_64bit
)
14173 /* Display eiz instead of addr32. */
14174 needindex
= addr32flag
;
14179 /* In 32-bit mode, we need index register to tell [offset]
14180 from [eiz*1 + offset]. */
14185 havedisp
= (havebase
14187 || (havesib
&& (haveindex
|| scale
!= 0)));
14190 if (modrm
.mod
!= 0 || base
== 5)
14192 if (havedisp
|| riprel
)
14193 print_displacement (scratchbuf
, disp
);
14195 print_operand_value (scratchbuf
, 1, disp
);
14196 oappend (scratchbuf
);
14200 oappend (!addr32flag
? "(%rip)" : "(%eip)");
14204 if ((havebase
|| haveindex
|| needaddr32
|| riprel
)
14205 && (bytemode
!= v_bnd_mode
)
14206 && (bytemode
!= v_bndmk_mode
)
14207 && (bytemode
!= bnd_mode
)
14208 && (bytemode
!= bnd_swap_mode
))
14209 used_prefixes
|= PREFIX_ADDR
;
14211 if (havedisp
|| (intel_syntax
&& riprel
))
14213 *obufp
++ = open_char
;
14214 if (intel_syntax
&& riprel
)
14217 oappend (!addr32flag
? "rip" : "eip");
14221 oappend (address_mode
== mode_64bit
&& !addr32flag
14222 ? names64
[rbase
] : names32
[rbase
]);
14225 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
14226 print index to tell base + index from base. */
14230 || (havebase
&& base
!= ESP_REG_NUM
))
14232 if (!intel_syntax
|| havebase
)
14234 *obufp
++ = separator_char
;
14238 oappend (address_mode
== mode_64bit
&& !addr32flag
14239 ? indexes64
[vindex
] : indexes32
[vindex
]);
14241 oappend (address_mode
== mode_64bit
&& !addr32flag
14242 ? index64
: index32
);
14244 *obufp
++ = scale_char
;
14246 sprintf (scratchbuf
, "%d", 1 << scale
);
14247 oappend (scratchbuf
);
14251 && (disp
|| modrm
.mod
!= 0 || base
== 5))
14253 if (!havedisp
|| (bfd_signed_vma
) disp
>= 0)
14258 else if (modrm
.mod
!= 1 && disp
!= -disp
)
14262 disp
= - (bfd_signed_vma
) disp
;
14266 print_displacement (scratchbuf
, disp
);
14268 print_operand_value (scratchbuf
, 1, disp
);
14269 oappend (scratchbuf
);
14272 *obufp
++ = close_char
;
14275 else if (intel_syntax
)
14277 if (modrm
.mod
!= 0 || base
== 5)
14279 if (!active_seg_prefix
)
14281 oappend (names_seg
[ds_reg
- es_reg
]);
14284 print_operand_value (scratchbuf
, 1, disp
);
14285 oappend (scratchbuf
);
14291 /* 16 bit address mode */
14292 used_prefixes
|= prefixes
& PREFIX_ADDR
;
14299 if ((disp
& 0x8000) != 0)
14304 FETCH_DATA (the_info
, codep
+ 1);
14306 if ((disp
& 0x80) != 0)
14308 if (vex
.evex
&& shift
> 0)
14313 if ((disp
& 0x8000) != 0)
14319 if (modrm
.mod
!= 0 || modrm
.rm
== 6)
14321 print_displacement (scratchbuf
, disp
);
14322 oappend (scratchbuf
);
14325 if (modrm
.mod
!= 0 || modrm
.rm
!= 6)
14327 *obufp
++ = open_char
;
14329 oappend (index16
[modrm
.rm
]);
14331 && (disp
|| modrm
.mod
!= 0 || modrm
.rm
== 6))
14333 if ((bfd_signed_vma
) disp
>= 0)
14338 else if (modrm
.mod
!= 1)
14342 disp
= - (bfd_signed_vma
) disp
;
14345 print_displacement (scratchbuf
, disp
);
14346 oappend (scratchbuf
);
14349 *obufp
++ = close_char
;
14352 else if (intel_syntax
)
14354 if (!active_seg_prefix
)
14356 oappend (names_seg
[ds_reg
- es_reg
]);
14359 print_operand_value (scratchbuf
, 1, disp
& 0xffff);
14360 oappend (scratchbuf
);
14363 if (vex
.evex
&& vex
.b
14364 && (bytemode
== x_mode
14365 || bytemode
== xmmq_mode
14366 || bytemode
== evex_half_bcst_xmmq_mode
))
14369 || bytemode
== xmmq_mode
14370 || bytemode
== evex_half_bcst_xmmq_mode
)
14372 switch (vex
.length
)
14375 oappend ("{1to2}");
14378 oappend ("{1to4}");
14381 oappend ("{1to8}");
14389 switch (vex
.length
)
14392 oappend ("{1to4}");
14395 oappend ("{1to8}");
14398 oappend ("{1to16}");
14408 OP_E (int bytemode
, int sizeflag
)
14410 /* Skip mod/rm byte. */
14414 if (modrm
.mod
== 3)
14415 OP_E_register (bytemode
, sizeflag
);
14417 OP_E_memory (bytemode
, sizeflag
);
14421 OP_G (int bytemode
, int sizeflag
)
14424 const char **names
;
14433 oappend (names8rex
[modrm
.reg
+ add
]);
14435 oappend (names8
[modrm
.reg
+ add
]);
14438 oappend (names16
[modrm
.reg
+ add
]);
14443 oappend (names32
[modrm
.reg
+ add
]);
14446 oappend (names64
[modrm
.reg
+ add
]);
14449 if (modrm
.reg
> 0x3)
14454 oappend (names_bnd
[modrm
.reg
]);
14463 oappend (names64
[modrm
.reg
+ add
]);
14466 if ((sizeflag
& DFLAG
) || bytemode
!= v_mode
)
14467 oappend (names32
[modrm
.reg
+ add
]);
14469 oappend (names16
[modrm
.reg
+ add
]);
14470 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14474 names
= (address_mode
== mode_64bit
14475 ? names64
: names32
);
14476 if (!(prefixes
& PREFIX_ADDR
))
14478 if (address_mode
== mode_16bit
)
14483 /* Remove "addr16/addr32". */
14484 all_prefixes
[last_addr_prefix
] = 0;
14485 names
= (address_mode
!= mode_32bit
14486 ? names32
: names16
);
14487 used_prefixes
|= PREFIX_ADDR
;
14489 oappend (names
[modrm
.reg
+ add
]);
14492 if (address_mode
== mode_64bit
)
14493 oappend (names64
[modrm
.reg
+ add
]);
14495 oappend (names32
[modrm
.reg
+ add
]);
14499 if ((modrm
.reg
+ add
) > 0x7)
14504 oappend (names_mask
[modrm
.reg
+ add
]);
14507 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14520 FETCH_DATA (the_info
, codep
+ 8);
14521 a
= *codep
++ & 0xff;
14522 a
|= (*codep
++ & 0xff) << 8;
14523 a
|= (*codep
++ & 0xff) << 16;
14524 a
|= (*codep
++ & 0xffu
) << 24;
14525 b
= *codep
++ & 0xff;
14526 b
|= (*codep
++ & 0xff) << 8;
14527 b
|= (*codep
++ & 0xff) << 16;
14528 b
|= (*codep
++ & 0xffu
) << 24;
14529 x
= a
+ ((bfd_vma
) b
<< 32);
14537 static bfd_signed_vma
14540 bfd_signed_vma x
= 0;
14542 FETCH_DATA (the_info
, codep
+ 4);
14543 x
= *codep
++ & (bfd_signed_vma
) 0xff;
14544 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
14545 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
14546 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
14550 static bfd_signed_vma
14553 bfd_signed_vma x
= 0;
14555 FETCH_DATA (the_info
, codep
+ 4);
14556 x
= *codep
++ & (bfd_signed_vma
) 0xff;
14557 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
14558 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
14559 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
14561 x
= (x
^ ((bfd_signed_vma
) 1 << 31)) - ((bfd_signed_vma
) 1 << 31);
14571 FETCH_DATA (the_info
, codep
+ 2);
14572 x
= *codep
++ & 0xff;
14573 x
|= (*codep
++ & 0xff) << 8;
14578 set_op (bfd_vma op
, int riprel
)
14580 op_index
[op_ad
] = op_ad
;
14581 if (address_mode
== mode_64bit
)
14583 op_address
[op_ad
] = op
;
14584 op_riprel
[op_ad
] = riprel
;
14588 /* Mask to get a 32-bit address. */
14589 op_address
[op_ad
] = op
& 0xffffffff;
14590 op_riprel
[op_ad
] = riprel
& 0xffffffff;
14595 OP_REG (int code
, int sizeflag
)
14602 case es_reg
: case ss_reg
: case cs_reg
:
14603 case ds_reg
: case fs_reg
: case gs_reg
:
14604 oappend (names_seg
[code
- es_reg
]);
14616 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
14617 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
14618 s
= names16
[code
- ax_reg
+ add
];
14620 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
14621 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
14624 s
= names8rex
[code
- al_reg
+ add
];
14626 s
= names8
[code
- al_reg
];
14628 case rAX_reg
: case rCX_reg
: case rDX_reg
: case rBX_reg
:
14629 case rSP_reg
: case rBP_reg
: case rSI_reg
: case rDI_reg
:
14630 if (address_mode
== mode_64bit
14631 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14633 s
= names64
[code
- rAX_reg
+ add
];
14636 code
+= eAX_reg
- rAX_reg
;
14637 /* Fall through. */
14638 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
14639 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
14642 s
= names64
[code
- eAX_reg
+ add
];
14645 if (sizeflag
& DFLAG
)
14646 s
= names32
[code
- eAX_reg
+ add
];
14648 s
= names16
[code
- eAX_reg
+ add
];
14649 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14653 s
= INTERNAL_DISASSEMBLER_ERROR
;
14660 OP_IMREG (int code
, int sizeflag
)
14672 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
14673 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
14674 s
= names16
[code
- ax_reg
];
14676 case es_reg
: case ss_reg
: case cs_reg
:
14677 case ds_reg
: case fs_reg
: case gs_reg
:
14678 s
= names_seg
[code
- es_reg
];
14680 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
14681 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
14684 s
= names8rex
[code
- al_reg
];
14686 s
= names8
[code
- al_reg
];
14688 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
14689 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
14692 s
= names64
[code
- eAX_reg
];
14695 if (sizeflag
& DFLAG
)
14696 s
= names32
[code
- eAX_reg
];
14698 s
= names16
[code
- eAX_reg
];
14699 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14702 case z_mode_ax_reg
:
14703 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
14707 if (!(rex
& REX_W
))
14708 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14711 s
= INTERNAL_DISASSEMBLER_ERROR
;
14718 OP_I (int bytemode
, int sizeflag
)
14721 bfd_signed_vma mask
= -1;
14726 FETCH_DATA (the_info
, codep
+ 1);
14731 if (address_mode
== mode_64bit
)
14736 /* Fall through. */
14743 if (sizeflag
& DFLAG
)
14753 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14765 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14770 scratchbuf
[0] = '$';
14771 print_operand_value (scratchbuf
+ 1, 1, op
);
14772 oappend_maybe_intel (scratchbuf
);
14773 scratchbuf
[0] = '\0';
14777 OP_I64 (int bytemode
, int sizeflag
)
14780 bfd_signed_vma mask
= -1;
14782 if (address_mode
!= mode_64bit
)
14784 OP_I (bytemode
, sizeflag
);
14791 FETCH_DATA (the_info
, codep
+ 1);
14801 if (sizeflag
& DFLAG
)
14811 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14819 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14824 scratchbuf
[0] = '$';
14825 print_operand_value (scratchbuf
+ 1, 1, op
);
14826 oappend_maybe_intel (scratchbuf
);
14827 scratchbuf
[0] = '\0';
14831 OP_sI (int bytemode
, int sizeflag
)
14839 FETCH_DATA (the_info
, codep
+ 1);
14841 if ((op
& 0x80) != 0)
14843 if (bytemode
== b_T_mode
)
14845 if (address_mode
!= mode_64bit
14846 || !((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14848 /* The operand-size prefix is overridden by a REX prefix. */
14849 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
14857 if (!(rex
& REX_W
))
14859 if (sizeflag
& DFLAG
)
14867 /* The operand-size prefix is overridden by a REX prefix. */
14868 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
14874 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14878 scratchbuf
[0] = '$';
14879 print_operand_value (scratchbuf
+ 1, 1, op
);
14880 oappend_maybe_intel (scratchbuf
);
14884 OP_J (int bytemode
, int sizeflag
)
14888 bfd_vma segment
= 0;
14893 FETCH_DATA (the_info
, codep
+ 1);
14895 if ((disp
& 0x80) != 0)
14899 if (isa64
== amd64
)
14901 if ((sizeflag
& DFLAG
)
14902 || (address_mode
== mode_64bit
14903 && (isa64
!= amd64
|| (rex
& REX_W
))))
14908 if ((disp
& 0x8000) != 0)
14910 /* In 16bit mode, address is wrapped around at 64k within
14911 the same segment. Otherwise, a data16 prefix on a jump
14912 instruction means that the pc is masked to 16 bits after
14913 the displacement is added! */
14915 if ((prefixes
& PREFIX_DATA
) == 0)
14916 segment
= ((start_pc
+ (codep
- start_codep
))
14917 & ~((bfd_vma
) 0xffff));
14919 if (address_mode
!= mode_64bit
14920 || (isa64
== amd64
&& !(rex
& REX_W
)))
14921 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14924 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14927 disp
= ((start_pc
+ (codep
- start_codep
) + disp
) & mask
) | segment
;
14929 print_operand_value (scratchbuf
, 1, disp
);
14930 oappend (scratchbuf
);
14934 OP_SEG (int bytemode
, int sizeflag
)
14936 if (bytemode
== w_mode
)
14937 oappend (names_seg
[modrm
.reg
]);
14939 OP_E (modrm
.mod
== 3 ? bytemode
: w_mode
, sizeflag
);
14943 OP_DIR (int dummy ATTRIBUTE_UNUSED
, int sizeflag
)
14947 if (sizeflag
& DFLAG
)
14957 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14959 sprintf (scratchbuf
, "0x%x:0x%x", seg
, offset
);
14961 sprintf (scratchbuf
, "$0x%x,$0x%x", seg
, offset
);
14962 oappend (scratchbuf
);
14966 OP_OFF (int bytemode
, int sizeflag
)
14970 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
14971 intel_operand_size (bytemode
, sizeflag
);
14974 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
14981 if (!active_seg_prefix
)
14983 oappend (names_seg
[ds_reg
- es_reg
]);
14987 print_operand_value (scratchbuf
, 1, off
);
14988 oappend (scratchbuf
);
14992 OP_OFF64 (int bytemode
, int sizeflag
)
14996 if (address_mode
!= mode_64bit
14997 || (prefixes
& PREFIX_ADDR
))
14999 OP_OFF (bytemode
, sizeflag
);
15003 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
15004 intel_operand_size (bytemode
, sizeflag
);
15011 if (!active_seg_prefix
)
15013 oappend (names_seg
[ds_reg
- es_reg
]);
15017 print_operand_value (scratchbuf
, 1, off
);
15018 oappend (scratchbuf
);
15022 ptr_reg (int code
, int sizeflag
)
15026 *obufp
++ = open_char
;
15027 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
15028 if (address_mode
== mode_64bit
)
15030 if (!(sizeflag
& AFLAG
))
15031 s
= names32
[code
- eAX_reg
];
15033 s
= names64
[code
- eAX_reg
];
15035 else if (sizeflag
& AFLAG
)
15036 s
= names32
[code
- eAX_reg
];
15038 s
= names16
[code
- eAX_reg
];
15040 *obufp
++ = close_char
;
15045 OP_ESreg (int code
, int sizeflag
)
15051 case 0x6d: /* insw/insl */
15052 intel_operand_size (z_mode
, sizeflag
);
15054 case 0xa5: /* movsw/movsl/movsq */
15055 case 0xa7: /* cmpsw/cmpsl/cmpsq */
15056 case 0xab: /* stosw/stosl */
15057 case 0xaf: /* scasw/scasl */
15058 intel_operand_size (v_mode
, sizeflag
);
15061 intel_operand_size (b_mode
, sizeflag
);
15064 oappend_maybe_intel ("%es:");
15065 ptr_reg (code
, sizeflag
);
15069 OP_DSreg (int code
, int sizeflag
)
15075 case 0x6f: /* outsw/outsl */
15076 intel_operand_size (z_mode
, sizeflag
);
15078 case 0xa5: /* movsw/movsl/movsq */
15079 case 0xa7: /* cmpsw/cmpsl/cmpsq */
15080 case 0xad: /* lodsw/lodsl/lodsq */
15081 intel_operand_size (v_mode
, sizeflag
);
15084 intel_operand_size (b_mode
, sizeflag
);
15087 /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
15088 default segment register DS is printed. */
15089 if (!active_seg_prefix
)
15090 active_seg_prefix
= PREFIX_DS
;
15092 ptr_reg (code
, sizeflag
);
15096 OP_C (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15104 else if (address_mode
!= mode_64bit
&& (prefixes
& PREFIX_LOCK
))
15106 all_prefixes
[last_lock_prefix
] = 0;
15107 used_prefixes
|= PREFIX_LOCK
;
15112 sprintf (scratchbuf
, "%%cr%d", modrm
.reg
+ add
);
15113 oappend_maybe_intel (scratchbuf
);
15117 OP_D (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15126 sprintf (scratchbuf
, "db%d", modrm
.reg
+ add
);
15128 sprintf (scratchbuf
, "%%db%d", modrm
.reg
+ add
);
15129 oappend (scratchbuf
);
15133 OP_T (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15135 sprintf (scratchbuf
, "%%tr%d", modrm
.reg
);
15136 oappend_maybe_intel (scratchbuf
);
15140 OP_R (int bytemode
, int sizeflag
)
15142 /* Skip mod/rm byte. */
15145 OP_E_register (bytemode
, sizeflag
);
15149 OP_MMX (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15151 int reg
= modrm
.reg
;
15152 const char **names
;
15154 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15155 if (prefixes
& PREFIX_DATA
)
15164 oappend (names
[reg
]);
15168 OP_XMM (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
15170 int reg
= modrm
.reg
;
15171 const char **names
;
15183 && bytemode
!= xmm_mode
15184 && bytemode
!= xmmq_mode
15185 && bytemode
!= evex_half_bcst_xmmq_mode
15186 && bytemode
!= ymm_mode
15187 && bytemode
!= scalar_mode
)
15189 switch (vex
.length
)
15196 || (bytemode
!= vex_vsib_q_w_dq_mode
15197 && bytemode
!= vex_vsib_q_w_d_mode
))
15209 else if (bytemode
== xmmq_mode
15210 || bytemode
== evex_half_bcst_xmmq_mode
)
15212 switch (vex
.length
)
15225 else if (bytemode
== ymm_mode
)
15229 oappend (names
[reg
]);
15233 OP_EM (int bytemode
, int sizeflag
)
15236 const char **names
;
15238 if (modrm
.mod
!= 3)
15241 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
15243 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
15244 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15246 OP_E (bytemode
, sizeflag
);
15250 if ((sizeflag
& SUFFIX_ALWAYS
) && bytemode
== v_swap_mode
)
15253 /* Skip mod/rm byte. */
15256 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15258 if (prefixes
& PREFIX_DATA
)
15267 oappend (names
[reg
]);
15270 /* cvt* are the only instructions in sse2 which have
15271 both SSE and MMX operands and also have 0x66 prefix
15272 in their opcode. 0x66 was originally used to differentiate
15273 between SSE and MMX instruction(operands). So we have to handle the
15274 cvt* separately using OP_EMC and OP_MXC */
15276 OP_EMC (int bytemode
, int sizeflag
)
15278 if (modrm
.mod
!= 3)
15280 if (intel_syntax
&& bytemode
== v_mode
)
15282 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
15283 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15285 OP_E (bytemode
, sizeflag
);
15289 /* Skip mod/rm byte. */
15292 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15293 oappend (names_mm
[modrm
.rm
]);
15297 OP_MXC (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15299 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15300 oappend (names_mm
[modrm
.reg
]);
15304 OP_EX (int bytemode
, int sizeflag
)
15307 const char **names
;
15309 /* Skip mod/rm byte. */
15313 if (modrm
.mod
!= 3)
15315 OP_E_memory (bytemode
, sizeflag
);
15330 if ((sizeflag
& SUFFIX_ALWAYS
)
15331 && (bytemode
== x_swap_mode
15332 || bytemode
== d_swap_mode
15333 || bytemode
== d_scalar_swap_mode
15334 || bytemode
== q_swap_mode
15335 || bytemode
== q_scalar_swap_mode
))
15339 && bytemode
!= xmm_mode
15340 && bytemode
!= xmmdw_mode
15341 && bytemode
!= xmmqd_mode
15342 && bytemode
!= xmm_mb_mode
15343 && bytemode
!= xmm_mw_mode
15344 && bytemode
!= xmm_md_mode
15345 && bytemode
!= xmm_mq_mode
15346 && bytemode
!= xmm_mdq_mode
15347 && bytemode
!= xmmq_mode
15348 && bytemode
!= evex_half_bcst_xmmq_mode
15349 && bytemode
!= ymm_mode
15350 && bytemode
!= d_scalar_mode
15351 && bytemode
!= d_scalar_swap_mode
15352 && bytemode
!= q_scalar_mode
15353 && bytemode
!= q_scalar_swap_mode
15354 && bytemode
!= vex_scalar_w_dq_mode
)
15356 switch (vex
.length
)
15371 else if (bytemode
== xmmq_mode
15372 || bytemode
== evex_half_bcst_xmmq_mode
)
15374 switch (vex
.length
)
15387 else if (bytemode
== ymm_mode
)
15391 oappend (names
[reg
]);
15395 OP_MS (int bytemode
, int sizeflag
)
15397 if (modrm
.mod
== 3)
15398 OP_EM (bytemode
, sizeflag
);
15404 OP_XS (int bytemode
, int sizeflag
)
15406 if (modrm
.mod
== 3)
15407 OP_EX (bytemode
, sizeflag
);
15413 OP_M (int bytemode
, int sizeflag
)
15415 if (modrm
.mod
== 3)
15416 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
15419 OP_E (bytemode
, sizeflag
);
15423 OP_0f07 (int bytemode
, int sizeflag
)
15425 if (modrm
.mod
!= 3 || modrm
.rm
!= 0)
15428 OP_E (bytemode
, sizeflag
);
15431 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
15432 32bit mode and "xchg %rax,%rax" in 64bit mode. */
15435 NOP_Fixup1 (int bytemode
, int sizeflag
)
15437 if ((prefixes
& PREFIX_DATA
) != 0
15440 && address_mode
== mode_64bit
))
15441 OP_REG (bytemode
, sizeflag
);
15443 strcpy (obuf
, "nop");
15447 NOP_Fixup2 (int bytemode
, int sizeflag
)
15449 if ((prefixes
& PREFIX_DATA
) != 0
15452 && address_mode
== mode_64bit
))
15453 OP_IMREG (bytemode
, sizeflag
);
15456 static const char *const Suffix3DNow
[] = {
15457 /* 00 */ NULL
, NULL
, NULL
, NULL
,
15458 /* 04 */ NULL
, NULL
, NULL
, NULL
,
15459 /* 08 */ NULL
, NULL
, NULL
, NULL
,
15460 /* 0C */ "pi2fw", "pi2fd", NULL
, NULL
,
15461 /* 10 */ NULL
, NULL
, NULL
, NULL
,
15462 /* 14 */ NULL
, NULL
, NULL
, NULL
,
15463 /* 18 */ NULL
, NULL
, NULL
, NULL
,
15464 /* 1C */ "pf2iw", "pf2id", NULL
, NULL
,
15465 /* 20 */ NULL
, NULL
, NULL
, NULL
,
15466 /* 24 */ NULL
, NULL
, NULL
, NULL
,
15467 /* 28 */ NULL
, NULL
, NULL
, NULL
,
15468 /* 2C */ NULL
, NULL
, NULL
, NULL
,
15469 /* 30 */ NULL
, NULL
, NULL
, NULL
,
15470 /* 34 */ NULL
, NULL
, NULL
, NULL
,
15471 /* 38 */ NULL
, NULL
, NULL
, NULL
,
15472 /* 3C */ NULL
, NULL
, NULL
, NULL
,
15473 /* 40 */ NULL
, NULL
, NULL
, NULL
,
15474 /* 44 */ NULL
, NULL
, NULL
, NULL
,
15475 /* 48 */ NULL
, NULL
, NULL
, NULL
,
15476 /* 4C */ NULL
, NULL
, NULL
, NULL
,
15477 /* 50 */ NULL
, NULL
, NULL
, NULL
,
15478 /* 54 */ NULL
, NULL
, NULL
, NULL
,
15479 /* 58 */ NULL
, NULL
, NULL
, NULL
,
15480 /* 5C */ NULL
, NULL
, NULL
, NULL
,
15481 /* 60 */ NULL
, NULL
, NULL
, NULL
,
15482 /* 64 */ NULL
, NULL
, NULL
, NULL
,
15483 /* 68 */ NULL
, NULL
, NULL
, NULL
,
15484 /* 6C */ NULL
, NULL
, NULL
, NULL
,
15485 /* 70 */ NULL
, NULL
, NULL
, NULL
,
15486 /* 74 */ NULL
, NULL
, NULL
, NULL
,
15487 /* 78 */ NULL
, NULL
, NULL
, NULL
,
15488 /* 7C */ NULL
, NULL
, NULL
, NULL
,
15489 /* 80 */ NULL
, NULL
, NULL
, NULL
,
15490 /* 84 */ NULL
, NULL
, NULL
, NULL
,
15491 /* 88 */ NULL
, NULL
, "pfnacc", NULL
,
15492 /* 8C */ NULL
, NULL
, "pfpnacc", NULL
,
15493 /* 90 */ "pfcmpge", NULL
, NULL
, NULL
,
15494 /* 94 */ "pfmin", NULL
, "pfrcp", "pfrsqrt",
15495 /* 98 */ NULL
, NULL
, "pfsub", NULL
,
15496 /* 9C */ NULL
, NULL
, "pfadd", NULL
,
15497 /* A0 */ "pfcmpgt", NULL
, NULL
, NULL
,
15498 /* A4 */ "pfmax", NULL
, "pfrcpit1", "pfrsqit1",
15499 /* A8 */ NULL
, NULL
, "pfsubr", NULL
,
15500 /* AC */ NULL
, NULL
, "pfacc", NULL
,
15501 /* B0 */ "pfcmpeq", NULL
, NULL
, NULL
,
15502 /* B4 */ "pfmul", NULL
, "pfrcpit2", "pmulhrw",
15503 /* B8 */ NULL
, NULL
, NULL
, "pswapd",
15504 /* BC */ NULL
, NULL
, NULL
, "pavgusb",
15505 /* C0 */ NULL
, NULL
, NULL
, NULL
,
15506 /* C4 */ NULL
, NULL
, NULL
, NULL
,
15507 /* C8 */ NULL
, NULL
, NULL
, NULL
,
15508 /* CC */ NULL
, NULL
, NULL
, NULL
,
15509 /* D0 */ NULL
, NULL
, NULL
, NULL
,
15510 /* D4 */ NULL
, NULL
, NULL
, NULL
,
15511 /* D8 */ NULL
, NULL
, NULL
, NULL
,
15512 /* DC */ NULL
, NULL
, NULL
, NULL
,
15513 /* E0 */ NULL
, NULL
, NULL
, NULL
,
15514 /* E4 */ NULL
, NULL
, NULL
, NULL
,
15515 /* E8 */ NULL
, NULL
, NULL
, NULL
,
15516 /* EC */ NULL
, NULL
, NULL
, NULL
,
15517 /* F0 */ NULL
, NULL
, NULL
, NULL
,
15518 /* F4 */ NULL
, NULL
, NULL
, NULL
,
15519 /* F8 */ NULL
, NULL
, NULL
, NULL
,
15520 /* FC */ NULL
, NULL
, NULL
, NULL
,
15524 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15526 const char *mnemonic
;
15528 FETCH_DATA (the_info
, codep
+ 1);
15529 /* AMD 3DNow! instructions are specified by an opcode suffix in the
15530 place where an 8-bit immediate would normally go. ie. the last
15531 byte of the instruction. */
15532 obufp
= mnemonicendp
;
15533 mnemonic
= Suffix3DNow
[*codep
++ & 0xff];
15535 oappend (mnemonic
);
15538 /* Since a variable sized modrm/sib chunk is between the start
15539 of the opcode (0x0f0f) and the opcode suffix, we need to do
15540 all the modrm processing first, and don't know until now that
15541 we have a bad opcode. This necessitates some cleaning up. */
15542 op_out
[0][0] = '\0';
15543 op_out
[1][0] = '\0';
15546 mnemonicendp
= obufp
;
15549 static struct op simd_cmp_op
[] =
15551 { STRING_COMMA_LEN ("eq") },
15552 { STRING_COMMA_LEN ("lt") },
15553 { STRING_COMMA_LEN ("le") },
15554 { STRING_COMMA_LEN ("unord") },
15555 { STRING_COMMA_LEN ("neq") },
15556 { STRING_COMMA_LEN ("nlt") },
15557 { STRING_COMMA_LEN ("nle") },
15558 { STRING_COMMA_LEN ("ord") }
15562 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15564 unsigned int cmp_type
;
15566 FETCH_DATA (the_info
, codep
+ 1);
15567 cmp_type
= *codep
++ & 0xff;
15568 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
))
15571 char *p
= mnemonicendp
- 2;
15575 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
15576 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
15580 /* We have a reserved extension byte. Output it directly. */
15581 scratchbuf
[0] = '$';
15582 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
15583 oappend_maybe_intel (scratchbuf
);
15584 scratchbuf
[0] = '\0';
15589 OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED
,
15590 int sizeflag ATTRIBUTE_UNUSED
)
15592 /* mwaitx %eax,%ecx,%ebx */
15595 const char **names
= (address_mode
== mode_64bit
15596 ? names64
: names32
);
15597 strcpy (op_out
[0], names
[0]);
15598 strcpy (op_out
[1], names
[1]);
15599 strcpy (op_out
[2], names
[3]);
15600 two_source_ops
= 1;
15602 /* Skip mod/rm byte. */
15608 OP_Mwait (int bytemode ATTRIBUTE_UNUSED
,
15609 int sizeflag ATTRIBUTE_UNUSED
)
15611 /* mwait %eax,%ecx */
15614 const char **names
= (address_mode
== mode_64bit
15615 ? names64
: names32
);
15616 strcpy (op_out
[0], names
[0]);
15617 strcpy (op_out
[1], names
[1]);
15618 two_source_ops
= 1;
15620 /* Skip mod/rm byte. */
15626 OP_Monitor (int bytemode ATTRIBUTE_UNUSED
,
15627 int sizeflag ATTRIBUTE_UNUSED
)
15629 /* monitor %eax,%ecx,%edx" */
15632 const char **op1_names
;
15633 const char **names
= (address_mode
== mode_64bit
15634 ? names64
: names32
);
15636 if (!(prefixes
& PREFIX_ADDR
))
15637 op1_names
= (address_mode
== mode_16bit
15638 ? names16
: names
);
15641 /* Remove "addr16/addr32". */
15642 all_prefixes
[last_addr_prefix
] = 0;
15643 op1_names
= (address_mode
!= mode_32bit
15644 ? names32
: names16
);
15645 used_prefixes
|= PREFIX_ADDR
;
15647 strcpy (op_out
[0], op1_names
[0]);
15648 strcpy (op_out
[1], names
[1]);
15649 strcpy (op_out
[2], names
[2]);
15650 two_source_ops
= 1;
15652 /* Skip mod/rm byte. */
15660 /* Throw away prefixes and 1st. opcode byte. */
15661 codep
= insn_codep
+ 1;
15666 REP_Fixup (int bytemode
, int sizeflag
)
15668 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
15670 if (prefixes
& PREFIX_REPZ
)
15671 all_prefixes
[last_repz_prefix
] = REP_PREFIX
;
15678 OP_IMREG (bytemode
, sizeflag
);
15681 OP_ESreg (bytemode
, sizeflag
);
15684 OP_DSreg (bytemode
, sizeflag
);
15692 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
15696 BND_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15698 if (prefixes
& PREFIX_REPNZ
)
15699 all_prefixes
[last_repnz_prefix
] = BND_PREFIX
;
15702 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
15706 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED
,
15707 int sizeflag ATTRIBUTE_UNUSED
)
15709 if (active_seg_prefix
== PREFIX_DS
15710 && (address_mode
!= mode_64bit
|| last_data_prefix
< 0))
15712 /* NOTRACK prefix is only valid on indirect branch instructions.
15713 NB: DATA prefix is unsupported for Intel64. */
15714 active_seg_prefix
= 0;
15715 all_prefixes
[last_seg_prefix
] = NOTRACK_PREFIX
;
15719 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
15720 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
15724 HLE_Fixup1 (int bytemode
, int sizeflag
)
15727 && (prefixes
& PREFIX_LOCK
) != 0)
15729 if (prefixes
& PREFIX_REPZ
)
15730 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
15731 if (prefixes
& PREFIX_REPNZ
)
15732 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
15735 OP_E (bytemode
, sizeflag
);
15738 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
15739 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
15743 HLE_Fixup2 (int bytemode
, int sizeflag
)
15745 if (modrm
.mod
!= 3)
15747 if (prefixes
& PREFIX_REPZ
)
15748 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
15749 if (prefixes
& PREFIX_REPNZ
)
15750 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
15753 OP_E (bytemode
, sizeflag
);
15756 /* Similar to OP_E. But the 0xf3 prefixes should be displayed as
15757 "xrelease" for memory operand. No check for LOCK prefix. */
15760 HLE_Fixup3 (int bytemode
, int sizeflag
)
15763 && last_repz_prefix
> last_repnz_prefix
15764 && (prefixes
& PREFIX_REPZ
) != 0)
15765 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
15767 OP_E (bytemode
, sizeflag
);
15771 CMPXCHG8B_Fixup (int bytemode
, int sizeflag
)
15776 /* Change cmpxchg8b to cmpxchg16b. */
15777 char *p
= mnemonicendp
- 2;
15778 mnemonicendp
= stpcpy (p
, "16b");
15781 else if ((prefixes
& PREFIX_LOCK
) != 0)
15783 if (prefixes
& PREFIX_REPZ
)
15784 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
15785 if (prefixes
& PREFIX_REPNZ
)
15786 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
15789 OP_M (bytemode
, sizeflag
);
15793 XMM_Fixup (int reg
, int sizeflag ATTRIBUTE_UNUSED
)
15795 const char **names
;
15799 switch (vex
.length
)
15813 oappend (names
[reg
]);
15817 CRC32_Fixup (int bytemode
, int sizeflag
)
15819 /* Add proper suffix to "crc32". */
15820 char *p
= mnemonicendp
;
15839 if (sizeflag
& DFLAG
)
15843 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15847 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15854 if (modrm
.mod
== 3)
15858 /* Skip mod/rm byte. */
15863 add
= (rex
& REX_B
) ? 8 : 0;
15864 if (bytemode
== b_mode
)
15868 oappend (names8rex
[modrm
.rm
+ add
]);
15870 oappend (names8
[modrm
.rm
+ add
]);
15876 oappend (names64
[modrm
.rm
+ add
]);
15877 else if ((prefixes
& PREFIX_DATA
))
15878 oappend (names16
[modrm
.rm
+ add
]);
15880 oappend (names32
[modrm
.rm
+ add
]);
15884 OP_E (bytemode
, sizeflag
);
15888 FXSAVE_Fixup (int bytemode
, int sizeflag
)
15890 /* Add proper suffix to "fxsave" and "fxrstor". */
15894 char *p
= mnemonicendp
;
15900 OP_M (bytemode
, sizeflag
);
15904 PCMPESTR_Fixup (int bytemode
, int sizeflag
)
15906 /* Add proper suffix to "{,v}pcmpestr{i,m}". */
15909 char *p
= mnemonicendp
;
15914 else if (sizeflag
& SUFFIX_ALWAYS
)
15921 OP_EX (bytemode
, sizeflag
);
15924 /* Display the destination register operand for instructions with
15928 OP_VEX (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
15931 const char **names
;
15939 reg
= vex
.register_specifier
;
15940 vex
.register_specifier
= 0;
15941 if (address_mode
!= mode_64bit
)
15943 else if (vex
.evex
&& !vex
.v
)
15946 if (bytemode
== vex_scalar_mode
)
15948 oappend (names_xmm
[reg
]);
15952 switch (vex
.length
)
15959 case vex_vsib_q_w_dq_mode
:
15960 case vex_vsib_q_w_d_mode
:
15976 names
= names_mask
;
15990 case vex_vsib_q_w_dq_mode
:
15991 case vex_vsib_q_w_d_mode
:
15992 names
= vex
.w
? names_ymm
: names_xmm
;
16001 names
= names_mask
;
16004 /* See PR binutils/20893 for a reproducer. */
16016 oappend (names
[reg
]);
16019 /* Get the VEX immediate byte without moving codep. */
16021 static unsigned char
16022 get_vex_imm8 (int sizeflag
, int opnum
)
16024 int bytes_before_imm
= 0;
16026 if (modrm
.mod
!= 3)
16028 /* There are SIB/displacement bytes. */
16029 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
16031 /* 32/64 bit address mode */
16032 int base
= modrm
.rm
;
16034 /* Check SIB byte. */
16037 FETCH_DATA (the_info
, codep
+ 1);
16039 /* When decoding the third source, don't increase
16040 bytes_before_imm as this has already been incremented
16041 by one in OP_E_memory while decoding the second
16044 bytes_before_imm
++;
16047 /* Don't increase bytes_before_imm when decoding the third source,
16048 it has already been incremented by OP_E_memory while decoding
16049 the second source operand. */
16055 /* When modrm.rm == 5 or modrm.rm == 4 and base in
16056 SIB == 5, there is a 4 byte displacement. */
16058 /* No displacement. */
16060 /* Fall through. */
16062 /* 4 byte displacement. */
16063 bytes_before_imm
+= 4;
16066 /* 1 byte displacement. */
16067 bytes_before_imm
++;
16074 /* 16 bit address mode */
16075 /* Don't increase bytes_before_imm when decoding the third source,
16076 it has already been incremented by OP_E_memory while decoding
16077 the second source operand. */
16083 /* When modrm.rm == 6, there is a 2 byte displacement. */
16085 /* No displacement. */
16087 /* Fall through. */
16089 /* 2 byte displacement. */
16090 bytes_before_imm
+= 2;
16093 /* 1 byte displacement: when decoding the third source,
16094 don't increase bytes_before_imm as this has already
16095 been incremented by one in OP_E_memory while decoding
16096 the second source operand. */
16098 bytes_before_imm
++;
16106 FETCH_DATA (the_info
, codep
+ bytes_before_imm
+ 1);
16107 return codep
[bytes_before_imm
];
16111 OP_EX_VexReg (int bytemode
, int sizeflag
, int reg
)
16113 const char **names
;
16115 if (reg
== -1 && modrm
.mod
!= 3)
16117 OP_E_memory (bytemode
, sizeflag
);
16129 if (address_mode
!= mode_64bit
)
16133 switch (vex
.length
)
16144 oappend (names
[reg
]);
16148 OP_EX_VexImmW (int bytemode
, int sizeflag
)
16151 static unsigned char vex_imm8
;
16153 if (vex_w_done
== 0)
16157 /* Skip mod/rm byte. */
16161 vex_imm8
= get_vex_imm8 (sizeflag
, 0);
16164 reg
= vex_imm8
>> 4;
16166 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
16168 else if (vex_w_done
== 1)
16173 reg
= vex_imm8
>> 4;
16175 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
16179 /* Output the imm8 directly. */
16180 scratchbuf
[0] = '$';
16181 print_operand_value (scratchbuf
+ 1, 1, vex_imm8
& 0xf);
16182 oappend_maybe_intel (scratchbuf
);
16183 scratchbuf
[0] = '\0';
16189 OP_Vex_2src (int bytemode
, int sizeflag
)
16191 if (modrm
.mod
== 3)
16193 int reg
= modrm
.rm
;
16197 oappend (names_xmm
[reg
]);
16202 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
16204 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
16205 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16207 OP_E (bytemode
, sizeflag
);
16212 OP_Vex_2src_1 (int bytemode
, int sizeflag
)
16214 if (modrm
.mod
== 3)
16216 /* Skip mod/rm byte. */
16223 unsigned int reg
= vex
.register_specifier
;
16224 vex
.register_specifier
= 0;
16226 if (address_mode
!= mode_64bit
)
16228 oappend (names_xmm
[reg
]);
16231 OP_Vex_2src (bytemode
, sizeflag
);
16235 OP_Vex_2src_2 (int bytemode
, int sizeflag
)
16238 OP_Vex_2src (bytemode
, sizeflag
);
16241 unsigned int reg
= vex
.register_specifier
;
16242 vex
.register_specifier
= 0;
16244 if (address_mode
!= mode_64bit
)
16246 oappend (names_xmm
[reg
]);
16251 OP_EX_VexW (int bytemode
, int sizeflag
)
16257 /* Skip mod/rm byte. */
16262 reg
= get_vex_imm8 (sizeflag
, 0) >> 4;
16267 reg
= get_vex_imm8 (sizeflag
, 1) >> 4;
16270 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
16278 OP_REG_VexI4 (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16281 const char **names
;
16283 FETCH_DATA (the_info
, codep
+ 1);
16286 if (bytemode
!= x_mode
)
16290 if (address_mode
!= mode_64bit
)
16293 switch (vex
.length
)
16304 oappend (names
[reg
]);
16308 OP_XMM_VexW (int bytemode
, int sizeflag
)
16310 /* Turn off the REX.W bit since it is used for swapping operands
16313 OP_XMM (bytemode
, sizeflag
);
16317 OP_EX_Vex (int bytemode
, int sizeflag
)
16319 if (modrm
.mod
!= 3)
16321 OP_EX (bytemode
, sizeflag
);
16325 OP_XMM_Vex (int bytemode
, int sizeflag
)
16327 if (modrm
.mod
!= 3)
16329 OP_XMM (bytemode
, sizeflag
);
16332 static struct op vex_cmp_op
[] =
16334 { STRING_COMMA_LEN ("eq") },
16335 { STRING_COMMA_LEN ("lt") },
16336 { STRING_COMMA_LEN ("le") },
16337 { STRING_COMMA_LEN ("unord") },
16338 { STRING_COMMA_LEN ("neq") },
16339 { STRING_COMMA_LEN ("nlt") },
16340 { STRING_COMMA_LEN ("nle") },
16341 { STRING_COMMA_LEN ("ord") },
16342 { STRING_COMMA_LEN ("eq_uq") },
16343 { STRING_COMMA_LEN ("nge") },
16344 { STRING_COMMA_LEN ("ngt") },
16345 { STRING_COMMA_LEN ("false") },
16346 { STRING_COMMA_LEN ("neq_oq") },
16347 { STRING_COMMA_LEN ("ge") },
16348 { STRING_COMMA_LEN ("gt") },
16349 { STRING_COMMA_LEN ("true") },
16350 { STRING_COMMA_LEN ("eq_os") },
16351 { STRING_COMMA_LEN ("lt_oq") },
16352 { STRING_COMMA_LEN ("le_oq") },
16353 { STRING_COMMA_LEN ("unord_s") },
16354 { STRING_COMMA_LEN ("neq_us") },
16355 { STRING_COMMA_LEN ("nlt_uq") },
16356 { STRING_COMMA_LEN ("nle_uq") },
16357 { STRING_COMMA_LEN ("ord_s") },
16358 { STRING_COMMA_LEN ("eq_us") },
16359 { STRING_COMMA_LEN ("nge_uq") },
16360 { STRING_COMMA_LEN ("ngt_uq") },
16361 { STRING_COMMA_LEN ("false_os") },
16362 { STRING_COMMA_LEN ("neq_os") },
16363 { STRING_COMMA_LEN ("ge_oq") },
16364 { STRING_COMMA_LEN ("gt_oq") },
16365 { STRING_COMMA_LEN ("true_us") },
16369 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16371 unsigned int cmp_type
;
16373 FETCH_DATA (the_info
, codep
+ 1);
16374 cmp_type
= *codep
++ & 0xff;
16375 if (cmp_type
< ARRAY_SIZE (vex_cmp_op
))
16378 char *p
= mnemonicendp
- 2;
16382 sprintf (p
, "%s%s", vex_cmp_op
[cmp_type
].name
, suffix
);
16383 mnemonicendp
+= vex_cmp_op
[cmp_type
].len
;
16387 /* We have a reserved extension byte. Output it directly. */
16388 scratchbuf
[0] = '$';
16389 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
16390 oappend_maybe_intel (scratchbuf
);
16391 scratchbuf
[0] = '\0';
16396 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
,
16397 int sizeflag ATTRIBUTE_UNUSED
)
16399 unsigned int cmp_type
;
16404 FETCH_DATA (the_info
, codep
+ 1);
16405 cmp_type
= *codep
++ & 0xff;
16406 /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
16407 If it's the case, print suffix, otherwise - print the immediate. */
16408 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
)
16413 char *p
= mnemonicendp
- 2;
16415 /* vpcmp* can have both one- and two-lettered suffix. */
16429 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
16430 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
16434 /* We have a reserved extension byte. Output it directly. */
16435 scratchbuf
[0] = '$';
16436 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
16437 oappend_maybe_intel (scratchbuf
);
16438 scratchbuf
[0] = '\0';
16442 static const struct op xop_cmp_op
[] =
16444 { STRING_COMMA_LEN ("lt") },
16445 { STRING_COMMA_LEN ("le") },
16446 { STRING_COMMA_LEN ("gt") },
16447 { STRING_COMMA_LEN ("ge") },
16448 { STRING_COMMA_LEN ("eq") },
16449 { STRING_COMMA_LEN ("neq") },
16450 { STRING_COMMA_LEN ("false") },
16451 { STRING_COMMA_LEN ("true") }
16455 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED
,
16456 int sizeflag ATTRIBUTE_UNUSED
)
16458 unsigned int cmp_type
;
16460 FETCH_DATA (the_info
, codep
+ 1);
16461 cmp_type
= *codep
++ & 0xff;
16462 if (cmp_type
< ARRAY_SIZE (xop_cmp_op
))
16465 char *p
= mnemonicendp
- 2;
16467 /* vpcom* can have both one- and two-lettered suffix. */
16481 sprintf (p
, "%s%s", xop_cmp_op
[cmp_type
].name
, suffix
);
16482 mnemonicendp
+= xop_cmp_op
[cmp_type
].len
;
16486 /* We have a reserved extension byte. Output it directly. */
16487 scratchbuf
[0] = '$';
16488 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
16489 oappend_maybe_intel (scratchbuf
);
16490 scratchbuf
[0] = '\0';
16494 static const struct op pclmul_op
[] =
16496 { STRING_COMMA_LEN ("lql") },
16497 { STRING_COMMA_LEN ("hql") },
16498 { STRING_COMMA_LEN ("lqh") },
16499 { STRING_COMMA_LEN ("hqh") }
16503 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED
,
16504 int sizeflag ATTRIBUTE_UNUSED
)
16506 unsigned int pclmul_type
;
16508 FETCH_DATA (the_info
, codep
+ 1);
16509 pclmul_type
= *codep
++ & 0xff;
16510 switch (pclmul_type
)
16521 if (pclmul_type
< ARRAY_SIZE (pclmul_op
))
16524 char *p
= mnemonicendp
- 3;
16529 sprintf (p
, "%s%s", pclmul_op
[pclmul_type
].name
, suffix
);
16530 mnemonicendp
+= pclmul_op
[pclmul_type
].len
;
16534 /* We have a reserved extension byte. Output it directly. */
16535 scratchbuf
[0] = '$';
16536 print_operand_value (scratchbuf
+ 1, 1, pclmul_type
);
16537 oappend_maybe_intel (scratchbuf
);
16538 scratchbuf
[0] = '\0';
16543 MOVBE_Fixup (int bytemode
, int sizeflag
)
16545 /* Add proper suffix to "movbe". */
16546 char *p
= mnemonicendp
;
16555 if (sizeflag
& SUFFIX_ALWAYS
)
16561 if (sizeflag
& DFLAG
)
16565 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16570 oappend (INTERNAL_DISASSEMBLER_ERROR
);
16577 OP_M (bytemode
, sizeflag
);
16581 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16584 const char **names
;
16586 /* Skip mod/rm byte. */
16600 oappend (names
[reg
]);
16604 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16606 const char **names
;
16607 unsigned int reg
= vex
.register_specifier
;
16608 vex
.register_specifier
= 0;
16615 if (address_mode
!= mode_64bit
)
16617 oappend (names
[reg
]);
16621 OP_Mask (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16624 || (bytemode
!= mask_mode
&& bytemode
!= mask_bd_mode
))
16628 if ((rex
& REX_R
) != 0 || !vex
.r
)
16634 oappend (names_mask
[modrm
.reg
]);
16638 OP_Rounding (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16641 || (bytemode
!= evex_rounding_mode
16642 && bytemode
!= evex_rounding_64_mode
16643 && bytemode
!= evex_sae_mode
))
16645 if (modrm
.mod
== 3 && vex
.b
)
16648 case evex_rounding_64_mode
:
16649 if (address_mode
!= mode_64bit
)
16654 /* Fall through. */
16655 case evex_rounding_mode
:
16656 oappend (names_rounding
[vex
.ll
]);
16658 case evex_sae_mode
: