opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2016 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "dis-asm.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40
  41 #include <setjmp.h>
  42
  43 static int print_insn (bfd_vma, disassemble_info *);
  44 static void dofloat (int);
  45 static void OP_ST (int, int);
  46 static void OP_STi (int, int);
  47 static int putop (const char *, int);
  48 static void oappend (const char *);
  49 static void append_seg (void);
  50 static void OP_indirE (int, int);
  51 static void print_operand_value (char *, int, bfd_vma);
  52 static void OP_E_register (int, int);
  53 static void OP_E_memory (int, int);
  54 static void print_displacement (char *, bfd_vma);
  55 static void OP_E (int, int);
  56 static void OP_G (int, int);
  57 static bfd_vma get64 (void);
  58 static bfd_signed_vma get32 (void);
  59 static bfd_signed_vma get32s (void);
  60 static int get16 (void);
  61 static void set_op (bfd_vma, int);
  62 static void OP_Skip_MODRM (int, int);
  63 static void OP_REG (int, int);
  64 static void OP_IMREG (int, int);
  65 static void OP_I (int, int);
  66 static void OP_I64 (int, int);
  67 static void OP_sI (int, int);
  68 static void OP_J (int, int);
  69 static void OP_SEG (int, int);
  70 static void OP_DIR (int, int);
  71 static void OP_OFF (int, int);
  72 static void OP_OFF64 (int, int);
  73 static void ptr_reg (int, int);
  74 static void OP_ESreg (int, int);
  75 static void OP_DSreg (int, int);
  76 static void OP_C (int, int);
  77 static void OP_D (int, int);
  78 static void OP_T (int, int);
  79 static void OP_R (int, int);
  80 static void OP_MMX (int, int);
  81 static void OP_XMM (int, int);
  82 static void OP_EM (int, int);
  83 static void OP_EX (int, int);
  84 static void OP_EMC (int,int);
  85 static void OP_MXC (int,int);
  86 static void OP_MS (int, int);
  87 static void OP_XS (int, int);
  88 static void OP_M (int, int);
  89 static void OP_VEX (int, int);
  90 static void OP_EX_Vex (int, int);
  91 static void OP_EX_VexW (int, int);
  92 static void OP_EX_VexImmW (int, int);
  93 static void OP_XMM_Vex (int, int);
  94 static void OP_XMM_VexW (int, int);
  95 static void OP_Rounding (int, int);
  96 static void OP_REG_VexI4 (int, int);
  97 static void PCLMUL_Fixup (int, int);
  98 static void VEXI4_Fixup (int, int);
  99 static void VZERO_Fixup (int, int);
 100 static void VCMP_Fixup (int, int);
 101 static void VPCMP_Fixup (int, int);
 102 static void OP_0f07 (int, int);
 103 static void OP_Monitor (int, int);
 104 static void OP_Mwait (int, int);
 105 static void OP_Mwaitx (int, int);
 106 static void NOP_Fixup1 (int, int);
 107 static void NOP_Fixup2 (int, int);
 108 static void OP_3DNowSuffix (int, int);
 109 static void CMP_Fixup (int, int);
 110 static void BadOp (void);
 111 static void REP_Fixup (int, int);
 112 static void BND_Fixup (int, int);
 113 static void HLE_Fixup1 (int, int);
 114 static void HLE_Fixup2 (int, int);
 115 static void HLE_Fixup3 (int, int);
 116 static void CMPXCHG8B_Fixup (int, int);
 117 static void XMM_Fixup (int, int);
 118 static void CRC32_Fixup (int, int);
 119 static void FXSAVE_Fixup (int, int);
 120 static void OP_LWPCB_E (int, int);
 121 static void OP_LWP_E (int, int);
 122 static void OP_Vex_2src_1 (int, int);
 123 static void OP_Vex_2src_2 (int, int);
 124
 125 static void MOVBE_Fixup (int, int);
 126
 127 static void OP_Mask (int, int);
 128
 129 struct dis_private {
 130   /* Points to first byte not fetched.  */
 131   bfd_byte *max_fetched;
 132   bfd_byte the_buffer[MAX_MNEM_SIZE];
 133   bfd_vma insn_start;
 134   int orig_sizeflag;
 135   OPCODES_SIGJMP_BUF bailout;
 136 };
 137
 138 enum address_mode
 139 {
 140   mode_16bit,
 141   mode_32bit,
 142   mode_64bit
 143 };
 144
 145 enum address_mode address_mode;
 146
 147 /* Flags for the prefixes for the current instruction.  See below.  */
 148 static int prefixes;
 149
 150 /* REX prefix the current instruction.  See below.  */
 151 static int rex;
 152 /* Bits of REX we've already used.  */
 153 static int rex_used;
 154 /* REX bits in original REX prefix ignored.  */
 155 static int rex_ignored;
 156 /* Mark parts used in the REX prefix.  When we are testing for
 157    empty prefix (for 8bit register REX extension), just mask it
 158    out.  Otherwise test for REX bit is excuse for existence of REX
 159    only in case value is nonzero.  */
 160 #define USED_REX(value)                                 \
 161   {                                                     \
 162     if (value)                                          \
 163       {                                                 \
 164         if ((rex & value))                              \
 165           rex_used |= (value) | REX_OPCODE;             \
 166       }                                                 \
 167     else                                                \
 168       rex_used |= REX_OPCODE;                           \
 169   }
 170
 171 /* Flags for prefixes which we somehow handled when printing the
 172    current instruction.  */
 173 static int used_prefixes;
 174
 175 /* Flags stored in PREFIXES.  */
 176 #define PREFIX_REPZ 1
 177 #define PREFIX_REPNZ 2
 178 #define PREFIX_LOCK 4
 179 #define PREFIX_CS 8
 180 #define PREFIX_SS 0x10
 181 #define PREFIX_DS 0x20
 182 #define PREFIX_ES 0x40
 183 #define PREFIX_FS 0x80
 184 #define PREFIX_GS 0x100
 185 #define PREFIX_DATA 0x200
 186 #define PREFIX_ADDR 0x400
 187 #define PREFIX_FWAIT 0x800
 188
 189 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 190    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 191    on error.  */
 192 #define FETCH_DATA(info, addr) \
 193   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 194    ? 1 : fetch_data ((info), (addr)))
 195
 196 static int
 197 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 198 {
 199   int status;
 200   struct dis_private *priv = (struct dis_private *) info->private_data;
 201   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 202
 203   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 204     status = (*info->read_memory_func) (start,
 205                                         priv->max_fetched,
 206                                         addr - priv->max_fetched,
 207                                         info);
 208   else
 209     status = -1;
 210   if (status != 0)
 211     {
 212       /* If we did manage to read at least one byte, then
 213          print_insn_i386 will do something sensible.  Otherwise, print
 214          an error.  We do that here because this is where we know
 215          STATUS.  */
 216       if (priv->max_fetched == priv->the_buffer)
 217         (*info->memory_error_func) (status, start, info);
 218       OPCODES_SIGLONGJMP (priv->bailout, 1);
 219     }
 220   else
 221     priv->max_fetched = addr;
 222   return 1;
 223 }
 224
 225 /* Possible values for prefix requirement.  */
 226 #define PREFIX_IGNORED_SHIFT    16
 227 #define PREFIX_IGNORED_REPZ     (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
 228 #define PREFIX_IGNORED_REPNZ    (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
 229 #define PREFIX_IGNORED_DATA     (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
 230 #define PREFIX_IGNORED_ADDR     (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
 231 #define PREFIX_IGNORED_LOCK     (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
 232
 233 /* Opcode prefixes.  */
 234 #define PREFIX_OPCODE           (PREFIX_REPZ \
 235                                  | PREFIX_REPNZ \
 236                                  | PREFIX_DATA)
 237
 238 /* Prefixes ignored.  */
 239 #define PREFIX_IGNORED          (PREFIX_IGNORED_REPZ \
 240                                  | PREFIX_IGNORED_REPNZ \
 241                                  | PREFIX_IGNORED_DATA)
 242
 243 #define XX { NULL, 0 }
 244 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
 245
 246 #define Eb { OP_E, b_mode }
 247 #define Ebnd { OP_E, bnd_mode }
 248 #define EbS { OP_E, b_swap_mode }
 249 #define Ev { OP_E, v_mode }
 250 #define Ev_bnd { OP_E, v_bnd_mode }
 251 #define EvS { OP_E, v_swap_mode }
 252 #define Ed { OP_E, d_mode }
 253 #define Edq { OP_E, dq_mode }
 254 #define Edqw { OP_E, dqw_mode }
 255 #define Edqb { OP_E, dqb_mode }
 256 #define Edb { OP_E, db_mode }
 257 #define Edw { OP_E, dw_mode }
 258 #define Edqd { OP_E, dqd_mode }
 259 #define Eq { OP_E, q_mode }
 260 #define indirEv { OP_indirE, indir_v_mode }
 261 #define indirEp { OP_indirE, f_mode }
 262 #define stackEv { OP_E, stack_v_mode }
 263 #define Em { OP_E, m_mode }
 264 #define Ew { OP_E, w_mode }
 265 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 266 #define Ma { OP_M, a_mode }
 267 #define Mb { OP_M, b_mode }
 268 #define Md { OP_M, d_mode }
 269 #define Mo { OP_M, o_mode }
 270 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 271 #define Mq { OP_M, q_mode }
 272 #define Mx { OP_M, x_mode }
 273 #define Mxmm { OP_M, xmm_mode }
 274 #define Gb { OP_G, b_mode }
 275 #define Gbnd { OP_G, bnd_mode }
 276 #define Gv { OP_G, v_mode }
 277 #define Gd { OP_G, d_mode }
 278 #define Gdq { OP_G, dq_mode }
 279 #define Gm { OP_G, m_mode }
 280 #define Gw { OP_G, w_mode }
 281 #define Rd { OP_R, d_mode }
 282 #define Rdq { OP_R, dq_mode }
 283 #define Rm { OP_R, m_mode }
 284 #define Ib { OP_I, b_mode }
 285 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 286 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 287 #define Iv { OP_I, v_mode }
 288 #define sIv { OP_sI, v_mode }
 289 #define Iq { OP_I, q_mode }
 290 #define Iv64 { OP_I64, v_mode }
 291 #define Iw { OP_I, w_mode }
 292 #define I1 { OP_I, const_1_mode }
 293 #define Jb { OP_J, b_mode }
 294 #define Jv { OP_J, v_mode }
 295 #define Cm { OP_C, m_mode }
 296 #define Dm { OP_D, m_mode }
 297 #define Td { OP_T, d_mode }
 298 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 299
 300 #define RMeAX { OP_REG, eAX_reg }
 301 #define RMeBX { OP_REG, eBX_reg }
 302 #define RMeCX { OP_REG, eCX_reg }
 303 #define RMeDX { OP_REG, eDX_reg }
 304 #define RMeSP { OP_REG, eSP_reg }
 305 #define RMeBP { OP_REG, eBP_reg }
 306 #define RMeSI { OP_REG, eSI_reg }
 307 #define RMeDI { OP_REG, eDI_reg }
 308 #define RMrAX { OP_REG, rAX_reg }
 309 #define RMrBX { OP_REG, rBX_reg }
 310 #define RMrCX { OP_REG, rCX_reg }
 311 #define RMrDX { OP_REG, rDX_reg }
 312 #define RMrSP { OP_REG, rSP_reg }
 313 #define RMrBP { OP_REG, rBP_reg }
 314 #define RMrSI { OP_REG, rSI_reg }
 315 #define RMrDI { OP_REG, rDI_reg }
 316 #define RMAL { OP_REG, al_reg }
 317 #define RMCL { OP_REG, cl_reg }
 318 #define RMDL { OP_REG, dl_reg }
 319 #define RMBL { OP_REG, bl_reg }
 320 #define RMAH { OP_REG, ah_reg }
 321 #define RMCH { OP_REG, ch_reg }
 322 #define RMDH { OP_REG, dh_reg }
 323 #define RMBH { OP_REG, bh_reg }
 324 #define RMAX { OP_REG, ax_reg }
 325 #define RMDX { OP_REG, dx_reg }
 326
 327 #define eAX { OP_IMREG, eAX_reg }
 328 #define eBX { OP_IMREG, eBX_reg }
 329 #define eCX { OP_IMREG, eCX_reg }
 330 #define eDX { OP_IMREG, eDX_reg }
 331 #define eSP { OP_IMREG, eSP_reg }
 332 #define eBP { OP_IMREG, eBP_reg }
 333 #define eSI { OP_IMREG, eSI_reg }
 334 #define eDI { OP_IMREG, eDI_reg }
 335 #define AL { OP_IMREG, al_reg }
 336 #define CL { OP_IMREG, cl_reg }
 337 #define DL { OP_IMREG, dl_reg }
 338 #define BL { OP_IMREG, bl_reg }
 339 #define AH { OP_IMREG, ah_reg }
 340 #define CH { OP_IMREG, ch_reg }
 341 #define DH { OP_IMREG, dh_reg }
 342 #define BH { OP_IMREG, bh_reg }
 343 #define AX { OP_IMREG, ax_reg }
 344 #define DX { OP_IMREG, dx_reg }
 345 #define zAX { OP_IMREG, z_mode_ax_reg }
 346 #define indirDX { OP_IMREG, indir_dx_reg }
 347
 348 #define Sw { OP_SEG, w_mode }
 349 #define Sv { OP_SEG, v_mode }
 350 #define Ap { OP_DIR, 0 }
 351 #define Ob { OP_OFF64, b_mode }
 352 #define Ov { OP_OFF64, v_mode }
 353 #define Xb { OP_DSreg, eSI_reg }
 354 #define Xv { OP_DSreg, eSI_reg }
 355 #define Xz { OP_DSreg, eSI_reg }
 356 #define Yb { OP_ESreg, eDI_reg }
 357 #define Yv { OP_ESreg, eDI_reg }
 358 #define DSBX { OP_DSreg, eBX_reg }
 359
 360 #define es { OP_REG, es_reg }
 361 #define ss { OP_REG, ss_reg }
 362 #define cs { OP_REG, cs_reg }
 363 #define ds { OP_REG, ds_reg }
 364 #define fs { OP_REG, fs_reg }
 365 #define gs { OP_REG, gs_reg }
 366
 367 #define MX { OP_MMX, 0 }
 368 #define XM { OP_XMM, 0 }
 369 #define XMScalar { OP_XMM, scalar_mode }
 370 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 371 #define XMM { OP_XMM, xmm_mode }
 372 #define XMxmmq { OP_XMM, xmmq_mode }
 373 #define EM { OP_EM, v_mode }
 374 #define EMS { OP_EM, v_swap_mode }
 375 #define EMd { OP_EM, d_mode }
 376 #define EMx { OP_EM, x_mode }
 377 #define EXw { OP_EX, w_mode }
 378 #define EXd { OP_EX, d_mode }
 379 #define EXdScalar { OP_EX, d_scalar_mode }
 380 #define EXdS { OP_EX, d_swap_mode }
 381 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
 382 #define EXq { OP_EX, q_mode }
 383 #define EXqScalar { OP_EX, q_scalar_mode }
 384 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
 385 #define EXqS { OP_EX, q_swap_mode }
 386 #define EXx { OP_EX, x_mode }
 387 #define EXxS { OP_EX, x_swap_mode }
 388 #define EXxmm { OP_EX, xmm_mode }
 389 #define EXymm { OP_EX, ymm_mode }
 390 #define EXxmmq { OP_EX, xmmq_mode }
 391 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 392 #define EXxmm_mb { OP_EX, xmm_mb_mode }
 393 #define EXxmm_mw { OP_EX, xmm_mw_mode }
 394 #define EXxmm_md { OP_EX, xmm_md_mode }
 395 #define EXxmm_mq { OP_EX, xmm_mq_mode }
 396 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
 397 #define EXxmmdw { OP_EX, xmmdw_mode }
 398 #define EXxmmqd { OP_EX, xmmqd_mode }
 399 #define EXymmq { OP_EX, ymmq_mode }
 400 #define EXVexWdq { OP_EX, vex_w_dq_mode }
 401 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 402 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 403 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 404 #define MS { OP_MS, v_mode }
 405 #define XS { OP_XS, v_mode }
 406 #define EMCq { OP_EMC, q_mode }
 407 #define MXC { OP_MXC, 0 }
 408 #define OPSUF { OP_3DNowSuffix, 0 }
 409 #define CMP { CMP_Fixup, 0 }
 410 #define XMM0 { XMM_Fixup, 0 }
 411 #define FXSAVE { FXSAVE_Fixup, 0 }
 412 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
 413 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
 414
 415 #define Vex { OP_VEX, vex_mode }
 416 #define VexScalar { OP_VEX, vex_scalar_mode }
 417 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 418 #define Vex128 { OP_VEX, vex128_mode }
 419 #define Vex256 { OP_VEX, vex256_mode }
 420 #define VexGdq { OP_VEX, dq_mode }
 421 #define VexI4 { VEXI4_Fixup, 0}
 422 #define EXdVex { OP_EX_Vex, d_mode }
 423 #define EXdVexS { OP_EX_Vex, d_swap_mode }
 424 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
 425 #define EXqVex { OP_EX_Vex, q_mode }
 426 #define EXqVexS { OP_EX_Vex, q_swap_mode }
 427 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
 428 #define EXVexW { OP_EX_VexW, x_mode }
 429 #define EXdVexW { OP_EX_VexW, d_mode }
 430 #define EXqVexW { OP_EX_VexW, q_mode }
 431 #define EXVexImmW { OP_EX_VexImmW, x_mode }
 432 #define XMVex { OP_XMM_Vex, 0 }
 433 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
 434 #define XMVexW { OP_XMM_VexW, 0 }
 435 #define XMVexI4 { OP_REG_VexI4, x_mode }
 436 #define PCLMUL { PCLMUL_Fixup, 0 }
 437 #define VZERO { VZERO_Fixup, 0 }
 438 #define VCMP { VCMP_Fixup, 0 }
 439 #define VPCMP { VPCMP_Fixup, 0 }
 440
 441 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 442 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 443
 444 #define XMask { OP_Mask, mask_mode }
 445 #define MaskG { OP_G, mask_mode }
 446 #define MaskE { OP_E, mask_mode }
 447 #define MaskBDE { OP_E, mask_bd_mode }
 448 #define MaskR { OP_R, mask_mode }
 449 #define MaskVex { OP_VEX, mask_mode }
 450
 451 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 452 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
 453 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 454 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
 455
 456 /* Used handle "rep" prefix for string instructions.  */
 457 #define Xbr { REP_Fixup, eSI_reg }
 458 #define Xvr { REP_Fixup, eSI_reg }
 459 #define Ybr { REP_Fixup, eDI_reg }
 460 #define Yvr { REP_Fixup, eDI_reg }
 461 #define Yzr { REP_Fixup, eDI_reg }
 462 #define indirDXr { REP_Fixup, indir_dx_reg }
 463 #define ALr { REP_Fixup, al_reg }
 464 #define eAXr { REP_Fixup, eAX_reg }
 465
 466 /* Used handle HLE prefix for lockable instructions.  */
 467 #define Ebh1 { HLE_Fixup1, b_mode }
 468 #define Evh1 { HLE_Fixup1, v_mode }
 469 #define Ebh2 { HLE_Fixup2, b_mode }
 470 #define Evh2 { HLE_Fixup2, v_mode }
 471 #define Ebh3 { HLE_Fixup3, b_mode }
 472 #define Evh3 { HLE_Fixup3, v_mode }
 473
 474 #define BND { BND_Fixup, 0 }
 475
 476 #define cond_jump_flag { NULL, cond_jump_mode }
 477 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 478
 479 /* bits in sizeflag */
 480 #define SUFFIX_ALWAYS 4
 481 #define AFLAG 2
 482 #define DFLAG 1
 483
 484 enum
 485 {
 486   /* byte operand */
 487   b_mode = 1,
 488   /* byte operand with operand swapped */
 489   b_swap_mode,
 490   /* byte operand, sign extend like 'T' suffix */
 491   b_T_mode,
 492   /* operand size depends on prefixes */
 493   v_mode,
 494   /* operand size depends on prefixes with operand swapped */
 495   v_swap_mode,
 496   /* word operand */
 497   w_mode,
 498   /* double word operand  */
 499   d_mode,
 500   /* double word operand with operand swapped */
 501   d_swap_mode,
 502   /* quad word operand */
 503   q_mode,
 504   /* quad word operand with operand swapped */
 505   q_swap_mode,
 506   /* ten-byte operand */
 507   t_mode,
 508   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 509      broadcast enabled.  */
 510   x_mode,
 511   /* Similar to x_mode, but with different EVEX mem shifts.  */
 512   evex_x_gscat_mode,
 513   /* Similar to x_mode, but with disabled broadcast.  */
 514   evex_x_nobcst_mode,
 515   /* Similar to x_mode, but with operands swapped and disabled broadcast
 516      in EVEX.  */
 517   x_swap_mode,
 518   /* 16-byte XMM operand */
 519   xmm_mode,
 520   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 521      memory operand (depending on vector length).  Broadcast isn't
 522      allowed.  */
 523   xmmq_mode,
 524   /* Same as xmmq_mode, but broadcast is allowed.  */
 525   evex_half_bcst_xmmq_mode,
 526   /* XMM register or byte memory operand */
 527   xmm_mb_mode,
 528   /* XMM register or word memory operand */
 529   xmm_mw_mode,
 530   /* XMM register or double word memory operand */
 531   xmm_md_mode,
 532   /* XMM register or quad word memory operand */
 533   xmm_mq_mode,
 534   /* XMM register or double/quad word memory operand, depending on
 535      VEX.W.  */
 536   xmm_mdq_mode,
 537   /* 16-byte XMM, word, double word or quad word operand.  */
 538   xmmdw_mode,
 539   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 540   xmmqd_mode,
 541   /* 32-byte YMM operand */
 542   ymm_mode,
 543   /* quad word, ymmword or zmmword memory operand.  */
 544   ymmq_mode,
 545   /* 32-byte YMM or 16-byte word operand */
 546   ymmxmm_mode,
 547   /* d_mode in 32bit, q_mode in 64bit mode.  */
 548   m_mode,
 549   /* pair of v_mode operands */
 550   a_mode,
 551   cond_jump_mode,
 552   loop_jcxz_mode,
 553   v_bnd_mode,
 554   /* operand size depends on REX prefixes.  */
 555   dq_mode,
 556   /* registers like dq_mode, memory like w_mode.  */
 557   dqw_mode,
 558   bnd_mode,
 559   /* 4- or 6-byte pointer operand */
 560   f_mode,
 561   const_1_mode,
 562   /* v_mode for indirect branch opcodes.  */
 563   indir_v_mode,
 564   /* v_mode for stack-related opcodes.  */
 565   stack_v_mode,
 566   /* non-quad operand size depends on prefixes */
 567   z_mode,
 568   /* 16-byte operand */
 569   o_mode,
 570   /* registers like dq_mode, memory like b_mode.  */
 571   dqb_mode,
 572   /* registers like d_mode, memory like b_mode.  */
 573   db_mode,
 574   /* registers like d_mode, memory like w_mode.  */
 575   dw_mode,
 576   /* registers like dq_mode, memory like d_mode.  */
 577   dqd_mode,
 578   /* normal vex mode */
 579   vex_mode,
 580   /* 128bit vex mode */
 581   vex128_mode,
 582   /* 256bit vex mode */
 583   vex256_mode,
 584   /* operand size depends on the VEX.W bit.  */
 585   vex_w_dq_mode,
 586
 587   /* Similar to vex_w_dq_mode, with VSIB dword indices.  */
 588   vex_vsib_d_w_dq_mode,
 589   /* Similar to vex_vsib_d_w_dq_mode, with smaller memory.  */
 590   vex_vsib_d_w_d_mode,
 591   /* Similar to vex_w_dq_mode, with VSIB qword indices.  */
 592   vex_vsib_q_w_dq_mode,
 593   /* Similar to vex_vsib_q_w_dq_mode, with smaller memory.  */
 594   vex_vsib_q_w_d_mode,
 595
 596   /* scalar, ignore vector length.  */
 597   scalar_mode,
 598   /* like d_mode, ignore vector length.  */
 599   d_scalar_mode,
 600   /* like d_swap_mode, ignore vector length.  */
 601   d_scalar_swap_mode,
 602   /* like q_mode, ignore vector length.  */
 603   q_scalar_mode,
 604   /* like q_swap_mode, ignore vector length.  */
 605   q_scalar_swap_mode,
 606   /* like vex_mode, ignore vector length.  */
 607   vex_scalar_mode,
 608   /* like vex_w_dq_mode, ignore vector length.  */
 609   vex_scalar_w_dq_mode,
 610
 611   /* Static rounding.  */
 612   evex_rounding_mode,
 613   /* Supress all exceptions.  */
 614   evex_sae_mode,
 615
 616   /* Mask register operand.  */
 617   mask_mode,
 618   /* Mask register operand.  */
 619   mask_bd_mode,
 620
 621   es_reg,
 622   cs_reg,
 623   ss_reg,
 624   ds_reg,
 625   fs_reg,
 626   gs_reg,
 627
 628   eAX_reg,
 629   eCX_reg,
 630   eDX_reg,
 631   eBX_reg,
 632   eSP_reg,
 633   eBP_reg,
 634   eSI_reg,
 635   eDI_reg,
 636
 637   al_reg,
 638   cl_reg,
 639   dl_reg,
 640   bl_reg,
 641   ah_reg,
 642   ch_reg,
 643   dh_reg,
 644   bh_reg,
 645
 646   ax_reg,
 647   cx_reg,
 648   dx_reg,
 649   bx_reg,
 650   sp_reg,
 651   bp_reg,
 652   si_reg,
 653   di_reg,
 654
 655   rAX_reg,
 656   rCX_reg,
 657   rDX_reg,
 658   rBX_reg,
 659   rSP_reg,
 660   rBP_reg,
 661   rSI_reg,
 662   rDI_reg,
 663
 664   z_mode_ax_reg,
 665   indir_dx_reg
 666 };
 667
 668 enum
 669 {
 670   FLOATCODE = 1,
 671   USE_REG_TABLE,
 672   USE_MOD_TABLE,
 673   USE_RM_TABLE,
 674   USE_PREFIX_TABLE,
 675   USE_X86_64_TABLE,
 676   USE_3BYTE_TABLE,
 677   USE_XOP_8F_TABLE,
 678   USE_VEX_C4_TABLE,
 679   USE_VEX_C5_TABLE,
 680   USE_VEX_LEN_TABLE,
 681   USE_VEX_W_TABLE,
 682   USE_EVEX_TABLE
 683 };
 684
 685 #define FLOAT                   NULL, { { NULL, FLOATCODE } }, 0
 686
 687 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }, 0
 688 #define DIS386_PREFIX(T, I, P)          NULL, { { NULL, (T)}, { NULL,  (I) } }, P
 689 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 690 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 691 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 692 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 693 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 694 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 695 #define THREE_BYTE_TABLE_PREFIX(I, P)   DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
 696 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 697 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 698 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 699 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 700 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 701 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 702
 703 enum
 704 {
 705   REG_80 = 0,
 706   REG_81,
 707   REG_83,
 708   REG_8F,
 709   REG_C0,
 710   REG_C1,
 711   REG_C6,
 712   REG_C7,
 713   REG_D0,
 714   REG_D1,
 715   REG_D2,
 716   REG_D3,
 717   REG_F6,
 718   REG_F7,
 719   REG_FE,
 720   REG_FF,
 721   REG_0F00,
 722   REG_0F01,
 723   REG_0F0D,
 724   REG_0F18,
 725   REG_0F71,
 726   REG_0F72,
 727   REG_0F73,
 728   REG_0FA6,
 729   REG_0FA7,
 730   REG_0FAE,
 731   REG_0FBA,
 732   REG_0FC7,
 733   REG_VEX_0F71,
 734   REG_VEX_0F72,
 735   REG_VEX_0F73,
 736   REG_VEX_0FAE,
 737   REG_VEX_0F38F3,
 738   REG_XOP_LWPCB,
 739   REG_XOP_LWP,
 740   REG_XOP_TBM_01,
 741   REG_XOP_TBM_02,
 742
 743   REG_EVEX_0F71,
 744   REG_EVEX_0F72,
 745   REG_EVEX_0F73,
 746   REG_EVEX_0F38C6,
 747   REG_EVEX_0F38C7
 748 };
 749
 750 enum
 751 {
 752   MOD_8D = 0,
 753   MOD_C6_REG_7,
 754   MOD_C7_REG_7,
 755   MOD_FF_REG_3,
 756   MOD_FF_REG_5,
 757   MOD_0F01_REG_0,
 758   MOD_0F01_REG_1,
 759   MOD_0F01_REG_2,
 760   MOD_0F01_REG_3,
 761   MOD_0F01_REG_5,
 762   MOD_0F01_REG_7,
 763   MOD_0F12_PREFIX_0,
 764   MOD_0F13,
 765   MOD_0F16_PREFIX_0,
 766   MOD_0F17,
 767   MOD_0F18_REG_0,
 768   MOD_0F18_REG_1,
 769   MOD_0F18_REG_2,
 770   MOD_0F18_REG_3,
 771   MOD_0F18_REG_4,
 772   MOD_0F18_REG_5,
 773   MOD_0F18_REG_6,
 774   MOD_0F18_REG_7,
 775   MOD_0F1A_PREFIX_0,
 776   MOD_0F1B_PREFIX_0,
 777   MOD_0F1B_PREFIX_1,
 778   MOD_0F24,
 779   MOD_0F26,
 780   MOD_0F2B_PREFIX_0,
 781   MOD_0F2B_PREFIX_1,
 782   MOD_0F2B_PREFIX_2,
 783   MOD_0F2B_PREFIX_3,
 784   MOD_0F51,
 785   MOD_0F71_REG_2,
 786   MOD_0F71_REG_4,
 787   MOD_0F71_REG_6,
 788   MOD_0F72_REG_2,
 789   MOD_0F72_REG_4,
 790   MOD_0F72_REG_6,
 791   MOD_0F73_REG_2,
 792   MOD_0F73_REG_3,
 793   MOD_0F73_REG_6,
 794   MOD_0F73_REG_7,
 795   MOD_0FAE_REG_0,
 796   MOD_0FAE_REG_1,
 797   MOD_0FAE_REG_2,
 798   MOD_0FAE_REG_3,
 799   MOD_0FAE_REG_4,
 800   MOD_0FAE_REG_5,
 801   MOD_0FAE_REG_6,
 802   MOD_0FAE_REG_7,
 803   MOD_0FB2,
 804   MOD_0FB4,
 805   MOD_0FB5,
 806   MOD_0FC3,
 807   MOD_0FC7_REG_3,
 808   MOD_0FC7_REG_4,
 809   MOD_0FC7_REG_5,
 810   MOD_0FC7_REG_6,
 811   MOD_0FC7_REG_7,
 812   MOD_0FD7,
 813   MOD_0FE7_PREFIX_2,
 814   MOD_0FF0_PREFIX_3,
 815   MOD_0F382A_PREFIX_2,
 816   MOD_62_32BIT,
 817   MOD_C4_32BIT,
 818   MOD_C5_32BIT,
 819   MOD_VEX_0F12_PREFIX_0,
 820   MOD_VEX_0F13,
 821   MOD_VEX_0F16_PREFIX_0,
 822   MOD_VEX_0F17,
 823   MOD_VEX_0F2B,
 824   MOD_VEX_W_0_0F41_P_0_LEN_1,
 825   MOD_VEX_W_1_0F41_P_0_LEN_1,
 826   MOD_VEX_W_0_0F41_P_2_LEN_1,
 827   MOD_VEX_W_1_0F41_P_2_LEN_1,
 828   MOD_VEX_W_0_0F42_P_0_LEN_1,
 829   MOD_VEX_W_1_0F42_P_0_LEN_1,
 830   MOD_VEX_W_0_0F42_P_2_LEN_1,
 831   MOD_VEX_W_1_0F42_P_2_LEN_1,
 832   MOD_VEX_W_0_0F44_P_0_LEN_1,
 833   MOD_VEX_W_1_0F44_P_0_LEN_1,
 834   MOD_VEX_W_0_0F44_P_2_LEN_1,
 835   MOD_VEX_W_1_0F44_P_2_LEN_1,
 836   MOD_VEX_W_0_0F45_P_0_LEN_1,
 837   MOD_VEX_W_1_0F45_P_0_LEN_1,
 838   MOD_VEX_W_0_0F45_P_2_LEN_1,
 839   MOD_VEX_W_1_0F45_P_2_LEN_1,
 840   MOD_VEX_W_0_0F46_P_0_LEN_1,
 841   MOD_VEX_W_1_0F46_P_0_LEN_1,
 842   MOD_VEX_W_0_0F46_P_2_LEN_1,
 843   MOD_VEX_W_1_0F46_P_2_LEN_1,
 844   MOD_VEX_W_0_0F47_P_0_LEN_1,
 845   MOD_VEX_W_1_0F47_P_0_LEN_1,
 846   MOD_VEX_W_0_0F47_P_2_LEN_1,
 847   MOD_VEX_W_1_0F47_P_2_LEN_1,
 848   MOD_VEX_W_0_0F4A_P_0_LEN_1,
 849   MOD_VEX_W_1_0F4A_P_0_LEN_1,
 850   MOD_VEX_W_0_0F4A_P_2_LEN_1,
 851   MOD_VEX_W_1_0F4A_P_2_LEN_1,
 852   MOD_VEX_W_0_0F4B_P_0_LEN_1,
 853   MOD_VEX_W_1_0F4B_P_0_LEN_1,
 854   MOD_VEX_W_0_0F4B_P_2_LEN_1,
 855   MOD_VEX_0F50,
 856   MOD_VEX_0F71_REG_2,
 857   MOD_VEX_0F71_REG_4,
 858   MOD_VEX_0F71_REG_6,
 859   MOD_VEX_0F72_REG_2,
 860   MOD_VEX_0F72_REG_4,
 861   MOD_VEX_0F72_REG_6,
 862   MOD_VEX_0F73_REG_2,
 863   MOD_VEX_0F73_REG_3,
 864   MOD_VEX_0F73_REG_6,
 865   MOD_VEX_0F73_REG_7,
 866   MOD_VEX_W_0_0F91_P_0_LEN_0,
 867   MOD_VEX_W_1_0F91_P_0_LEN_0,
 868   MOD_VEX_W_0_0F91_P_2_LEN_0,
 869   MOD_VEX_W_1_0F91_P_2_LEN_0,
 870   MOD_VEX_W_0_0F92_P_0_LEN_0,
 871   MOD_VEX_W_0_0F92_P_2_LEN_0,
 872   MOD_VEX_W_0_0F92_P_3_LEN_0,
 873   MOD_VEX_W_1_0F92_P_3_LEN_0,
 874   MOD_VEX_W_0_0F93_P_0_LEN_0,
 875   MOD_VEX_W_0_0F93_P_2_LEN_0,
 876   MOD_VEX_W_0_0F93_P_3_LEN_0,
 877   MOD_VEX_W_1_0F93_P_3_LEN_0,
 878   MOD_VEX_W_0_0F98_P_0_LEN_0,
 879   MOD_VEX_W_1_0F98_P_0_LEN_0,
 880   MOD_VEX_W_0_0F98_P_2_LEN_0,
 881   MOD_VEX_W_1_0F98_P_2_LEN_0,
 882   MOD_VEX_W_0_0F99_P_0_LEN_0,
 883   MOD_VEX_W_1_0F99_P_0_LEN_0,
 884   MOD_VEX_W_0_0F99_P_2_LEN_0,
 885   MOD_VEX_W_1_0F99_P_2_LEN_0,
 886   MOD_VEX_0FAE_REG_2,
 887   MOD_VEX_0FAE_REG_3,
 888   MOD_VEX_0FD7_PREFIX_2,
 889   MOD_VEX_0FE7_PREFIX_2,
 890   MOD_VEX_0FF0_PREFIX_3,
 891   MOD_VEX_0F381A_PREFIX_2,
 892   MOD_VEX_0F382A_PREFIX_2,
 893   MOD_VEX_0F382C_PREFIX_2,
 894   MOD_VEX_0F382D_PREFIX_2,
 895   MOD_VEX_0F382E_PREFIX_2,
 896   MOD_VEX_0F382F_PREFIX_2,
 897   MOD_VEX_0F385A_PREFIX_2,
 898   MOD_VEX_0F388C_PREFIX_2,
 899   MOD_VEX_0F388E_PREFIX_2,
 900   MOD_VEX_W_0_0F3A30_P_2_LEN_0,
 901   MOD_VEX_W_1_0F3A30_P_2_LEN_0,
 902   MOD_VEX_W_0_0F3A31_P_2_LEN_0,
 903   MOD_VEX_W_1_0F3A31_P_2_LEN_0,
 904   MOD_VEX_W_0_0F3A32_P_2_LEN_0,
 905   MOD_VEX_W_1_0F3A32_P_2_LEN_0,
 906   MOD_VEX_W_0_0F3A33_P_2_LEN_0,
 907   MOD_VEX_W_1_0F3A33_P_2_LEN_0,
 908
 909   MOD_EVEX_0F10_PREFIX_1,
 910   MOD_EVEX_0F10_PREFIX_3,
 911   MOD_EVEX_0F11_PREFIX_1,
 912   MOD_EVEX_0F11_PREFIX_3,
 913   MOD_EVEX_0F12_PREFIX_0,
 914   MOD_EVEX_0F16_PREFIX_0,
 915   MOD_EVEX_0F38C6_REG_1,
 916   MOD_EVEX_0F38C6_REG_2,
 917   MOD_EVEX_0F38C6_REG_5,
 918   MOD_EVEX_0F38C6_REG_6,
 919   MOD_EVEX_0F38C7_REG_1,
 920   MOD_EVEX_0F38C7_REG_2,
 921   MOD_EVEX_0F38C7_REG_5,
 922   MOD_EVEX_0F38C7_REG_6
 923 };
 924
 925 enum
 926 {
 927   RM_C6_REG_7 = 0,
 928   RM_C7_REG_7,
 929   RM_0F01_REG_0,
 930   RM_0F01_REG_1,
 931   RM_0F01_REG_2,
 932   RM_0F01_REG_3,
 933   RM_0F01_REG_5,
 934   RM_0F01_REG_7,
 935   RM_0FAE_REG_5,
 936   RM_0FAE_REG_6,
 937   RM_0FAE_REG_7
 938 };
 939
 940 enum
 941 {
 942   PREFIX_90 = 0,
 943   PREFIX_0F10,
 944   PREFIX_0F11,
 945   PREFIX_0F12,
 946   PREFIX_0F16,
 947   PREFIX_0F1A,
 948   PREFIX_0F1B,
 949   PREFIX_0F2A,
 950   PREFIX_0F2B,
 951   PREFIX_0F2C,
 952   PREFIX_0F2D,
 953   PREFIX_0F2E,
 954   PREFIX_0F2F,
 955   PREFIX_0F51,
 956   PREFIX_0F52,
 957   PREFIX_0F53,
 958   PREFIX_0F58,
 959   PREFIX_0F59,
 960   PREFIX_0F5A,
 961   PREFIX_0F5B,
 962   PREFIX_0F5C,
 963   PREFIX_0F5D,
 964   PREFIX_0F5E,
 965   PREFIX_0F5F,
 966   PREFIX_0F60,
 967   PREFIX_0F61,
 968   PREFIX_0F62,
 969   PREFIX_0F6C,
 970   PREFIX_0F6D,
 971   PREFIX_0F6F,
 972   PREFIX_0F70,
 973   PREFIX_0F73_REG_3,
 974   PREFIX_0F73_REG_7,
 975   PREFIX_0F78,
 976   PREFIX_0F79,
 977   PREFIX_0F7C,
 978   PREFIX_0F7D,
 979   PREFIX_0F7E,
 980   PREFIX_0F7F,
 981   PREFIX_0FAE_REG_0,
 982   PREFIX_0FAE_REG_1,
 983   PREFIX_0FAE_REG_2,
 984   PREFIX_0FAE_REG_3,
 985   PREFIX_MOD_0_0FAE_REG_4,
 986   PREFIX_MOD_3_0FAE_REG_4,
 987   PREFIX_0FAE_REG_6,
 988   PREFIX_0FAE_REG_7,
 989   PREFIX_0FB8,
 990   PREFIX_0FBC,
 991   PREFIX_0FBD,
 992   PREFIX_0FC2,
 993   PREFIX_MOD_0_0FC3,
 994   PREFIX_MOD_0_0FC7_REG_6,
 995   PREFIX_MOD_3_0FC7_REG_6,
 996   PREFIX_MOD_3_0FC7_REG_7,
 997   PREFIX_0FD0,
 998   PREFIX_0FD6,
 999   PREFIX_0FE6,
1000   PREFIX_0FE7,
1001   PREFIX_0FF0,
1002   PREFIX_0FF7,
1003   PREFIX_0F3810,
1004   PREFIX_0F3814,
1005   PREFIX_0F3815,
1006   PREFIX_0F3817,
1007   PREFIX_0F3820,
1008   PREFIX_0F3821,
1009   PREFIX_0F3822,
1010   PREFIX_0F3823,
1011   PREFIX_0F3824,
1012   PREFIX_0F3825,
1013   PREFIX_0F3828,
1014   PREFIX_0F3829,
1015   PREFIX_0F382A,
1016   PREFIX_0F382B,
1017   PREFIX_0F3830,
1018   PREFIX_0F3831,
1019   PREFIX_0F3832,
1020   PREFIX_0F3833,
1021   PREFIX_0F3834,
1022   PREFIX_0F3835,
1023   PREFIX_0F3837,
1024   PREFIX_0F3838,
1025   PREFIX_0F3839,
1026   PREFIX_0F383A,
1027   PREFIX_0F383B,
1028   PREFIX_0F383C,
1029   PREFIX_0F383D,
1030   PREFIX_0F383E,
1031   PREFIX_0F383F,
1032   PREFIX_0F3840,
1033   PREFIX_0F3841,
1034   PREFIX_0F3880,
1035   PREFIX_0F3881,
1036   PREFIX_0F3882,
1037   PREFIX_0F38C8,
1038   PREFIX_0F38C9,
1039   PREFIX_0F38CA,
1040   PREFIX_0F38CB,
1041   PREFIX_0F38CC,
1042   PREFIX_0F38CD,
1043   PREFIX_0F38DB,
1044   PREFIX_0F38DC,
1045   PREFIX_0F38DD,
1046   PREFIX_0F38DE,
1047   PREFIX_0F38DF,
1048   PREFIX_0F38F0,
1049   PREFIX_0F38F1,
1050   PREFIX_0F38F6,
1051   PREFIX_0F3A08,
1052   PREFIX_0F3A09,
1053   PREFIX_0F3A0A,
1054   PREFIX_0F3A0B,
1055   PREFIX_0F3A0C,
1056   PREFIX_0F3A0D,
1057   PREFIX_0F3A0E,
1058   PREFIX_0F3A14,
1059   PREFIX_0F3A15,
1060   PREFIX_0F3A16,
1061   PREFIX_0F3A17,
1062   PREFIX_0F3A20,
1063   PREFIX_0F3A21,
1064   PREFIX_0F3A22,
1065   PREFIX_0F3A40,
1066   PREFIX_0F3A41,
1067   PREFIX_0F3A42,
1068   PREFIX_0F3A44,
1069   PREFIX_0F3A60,
1070   PREFIX_0F3A61,
1071   PREFIX_0F3A62,
1072   PREFIX_0F3A63,
1073   PREFIX_0F3ACC,
1074   PREFIX_0F3ADF,
1075   PREFIX_VEX_0F10,
1076   PREFIX_VEX_0F11,
1077   PREFIX_VEX_0F12,
1078   PREFIX_VEX_0F16,
1079   PREFIX_VEX_0F2A,
1080   PREFIX_VEX_0F2C,
1081   PREFIX_VEX_0F2D,
1082   PREFIX_VEX_0F2E,
1083   PREFIX_VEX_0F2F,
1084   PREFIX_VEX_0F41,
1085   PREFIX_VEX_0F42,
1086   PREFIX_VEX_0F44,
1087   PREFIX_VEX_0F45,
1088   PREFIX_VEX_0F46,
1089   PREFIX_VEX_0F47,
1090   PREFIX_VEX_0F4A,
1091   PREFIX_VEX_0F4B,
1092   PREFIX_VEX_0F51,
1093   PREFIX_VEX_0F52,
1094   PREFIX_VEX_0F53,
1095   PREFIX_VEX_0F58,
1096   PREFIX_VEX_0F59,
1097   PREFIX_VEX_0F5A,
1098   PREFIX_VEX_0F5B,
1099   PREFIX_VEX_0F5C,
1100   PREFIX_VEX_0F5D,
1101   PREFIX_VEX_0F5E,
1102   PREFIX_VEX_0F5F,
1103   PREFIX_VEX_0F60,
1104   PREFIX_VEX_0F61,
1105   PREFIX_VEX_0F62,
1106   PREFIX_VEX_0F63,
1107   PREFIX_VEX_0F64,
1108   PREFIX_VEX_0F65,
1109   PREFIX_VEX_0F66,
1110   PREFIX_VEX_0F67,
1111   PREFIX_VEX_0F68,
1112   PREFIX_VEX_0F69,
1113   PREFIX_VEX_0F6A,
1114   PREFIX_VEX_0F6B,
1115   PREFIX_VEX_0F6C,
1116   PREFIX_VEX_0F6D,
1117   PREFIX_VEX_0F6E,
1118   PREFIX_VEX_0F6F,
1119   PREFIX_VEX_0F70,
1120   PREFIX_VEX_0F71_REG_2,
1121   PREFIX_VEX_0F71_REG_4,
1122   PREFIX_VEX_0F71_REG_6,
1123   PREFIX_VEX_0F72_REG_2,
1124   PREFIX_VEX_0F72_REG_4,
1125   PREFIX_VEX_0F72_REG_6,
1126   PREFIX_VEX_0F73_REG_2,
1127   PREFIX_VEX_0F73_REG_3,
1128   PREFIX_VEX_0F73_REG_6,
1129   PREFIX_VEX_0F73_REG_7,
1130   PREFIX_VEX_0F74,
1131   PREFIX_VEX_0F75,
1132   PREFIX_VEX_0F76,
1133   PREFIX_VEX_0F77,
1134   PREFIX_VEX_0F7C,
1135   PREFIX_VEX_0F7D,
1136   PREFIX_VEX_0F7E,
1137   PREFIX_VEX_0F7F,
1138   PREFIX_VEX_0F90,
1139   PREFIX_VEX_0F91,
1140   PREFIX_VEX_0F92,
1141   PREFIX_VEX_0F93,
1142   PREFIX_VEX_0F98,
1143   PREFIX_VEX_0F99,
1144   PREFIX_VEX_0FC2,
1145   PREFIX_VEX_0FC4,
1146   PREFIX_VEX_0FC5,
1147   PREFIX_VEX_0FD0,
1148   PREFIX_VEX_0FD1,
1149   PREFIX_VEX_0FD2,
1150   PREFIX_VEX_0FD3,
1151   PREFIX_VEX_0FD4,
1152   PREFIX_VEX_0FD5,
1153   PREFIX_VEX_0FD6,
1154   PREFIX_VEX_0FD7,
1155   PREFIX_VEX_0FD8,
1156   PREFIX_VEX_0FD9,
1157   PREFIX_VEX_0FDA,
1158   PREFIX_VEX_0FDB,
1159   PREFIX_VEX_0FDC,
1160   PREFIX_VEX_0FDD,
1161   PREFIX_VEX_0FDE,
1162   PREFIX_VEX_0FDF,
1163   PREFIX_VEX_0FE0,
1164   PREFIX_VEX_0FE1,
1165   PREFIX_VEX_0FE2,
1166   PREFIX_VEX_0FE3,
1167   PREFIX_VEX_0FE4,
1168   PREFIX_VEX_0FE5,
1169   PREFIX_VEX_0FE6,
1170   PREFIX_VEX_0FE7,
1171   PREFIX_VEX_0FE8,
1172   PREFIX_VEX_0FE9,
1173   PREFIX_VEX_0FEA,
1174   PREFIX_VEX_0FEB,
1175   PREFIX_VEX_0FEC,
1176   PREFIX_VEX_0FED,
1177   PREFIX_VEX_0FEE,
1178   PREFIX_VEX_0FEF,
1179   PREFIX_VEX_0FF0,
1180   PREFIX_VEX_0FF1,
1181   PREFIX_VEX_0FF2,
1182   PREFIX_VEX_0FF3,
1183   PREFIX_VEX_0FF4,
1184   PREFIX_VEX_0FF5,
1185   PREFIX_VEX_0FF6,
1186   PREFIX_VEX_0FF7,
1187   PREFIX_VEX_0FF8,
1188   PREFIX_VEX_0FF9,
1189   PREFIX_VEX_0FFA,
1190   PREFIX_VEX_0FFB,
1191   PREFIX_VEX_0FFC,
1192   PREFIX_VEX_0FFD,
1193   PREFIX_VEX_0FFE,
1194   PREFIX_VEX_0F3800,
1195   PREFIX_VEX_0F3801,
1196   PREFIX_VEX_0F3802,
1197   PREFIX_VEX_0F3803,
1198   PREFIX_VEX_0F3804,
1199   PREFIX_VEX_0F3805,
1200   PREFIX_VEX_0F3806,
1201   PREFIX_VEX_0F3807,
1202   PREFIX_VEX_0F3808,
1203   PREFIX_VEX_0F3809,
1204   PREFIX_VEX_0F380A,
1205   PREFIX_VEX_0F380B,
1206   PREFIX_VEX_0F380C,
1207   PREFIX_VEX_0F380D,
1208   PREFIX_VEX_0F380E,
1209   PREFIX_VEX_0F380F,
1210   PREFIX_VEX_0F3813,
1211   PREFIX_VEX_0F3816,
1212   PREFIX_VEX_0F3817,
1213   PREFIX_VEX_0F3818,
1214   PREFIX_VEX_0F3819,
1215   PREFIX_VEX_0F381A,
1216   PREFIX_VEX_0F381C,
1217   PREFIX_VEX_0F381D,
1218   PREFIX_VEX_0F381E,
1219   PREFIX_VEX_0F3820,
1220   PREFIX_VEX_0F3821,
1221   PREFIX_VEX_0F3822,
1222   PREFIX_VEX_0F3823,
1223   PREFIX_VEX_0F3824,
1224   PREFIX_VEX_0F3825,
1225   PREFIX_VEX_0F3828,
1226   PREFIX_VEX_0F3829,
1227   PREFIX_VEX_0F382A,
1228   PREFIX_VEX_0F382B,
1229   PREFIX_VEX_0F382C,
1230   PREFIX_VEX_0F382D,
1231   PREFIX_VEX_0F382E,
1232   PREFIX_VEX_0F382F,
1233   PREFIX_VEX_0F3830,
1234   PREFIX_VEX_0F3831,
1235   PREFIX_VEX_0F3832,
1236   PREFIX_VEX_0F3833,
1237   PREFIX_VEX_0F3834,
1238   PREFIX_VEX_0F3835,
1239   PREFIX_VEX_0F3836,
1240   PREFIX_VEX_0F3837,
1241   PREFIX_VEX_0F3838,
1242   PREFIX_VEX_0F3839,
1243   PREFIX_VEX_0F383A,
1244   PREFIX_VEX_0F383B,
1245   PREFIX_VEX_0F383C,
1246   PREFIX_VEX_0F383D,
1247   PREFIX_VEX_0F383E,
1248   PREFIX_VEX_0F383F,
1249   PREFIX_VEX_0F3840,
1250   PREFIX_VEX_0F3841,
1251   PREFIX_VEX_0F3845,
1252   PREFIX_VEX_0F3846,
1253   PREFIX_VEX_0F3847,
1254   PREFIX_VEX_0F3858,
1255   PREFIX_VEX_0F3859,
1256   PREFIX_VEX_0F385A,
1257   PREFIX_VEX_0F3878,
1258   PREFIX_VEX_0F3879,
1259   PREFIX_VEX_0F388C,
1260   PREFIX_VEX_0F388E,
1261   PREFIX_VEX_0F3890,
1262   PREFIX_VEX_0F3891,
1263   PREFIX_VEX_0F3892,
1264   PREFIX_VEX_0F3893,
1265   PREFIX_VEX_0F3896,
1266   PREFIX_VEX_0F3897,
1267   PREFIX_VEX_0F3898,
1268   PREFIX_VEX_0F3899,
1269   PREFIX_VEX_0F389A,
1270   PREFIX_VEX_0F389B,
1271   PREFIX_VEX_0F389C,
1272   PREFIX_VEX_0F389D,
1273   PREFIX_VEX_0F389E,
1274   PREFIX_VEX_0F389F,
1275   PREFIX_VEX_0F38A6,
1276   PREFIX_VEX_0F38A7,
1277   PREFIX_VEX_0F38A8,
1278   PREFIX_VEX_0F38A9,
1279   PREFIX_VEX_0F38AA,
1280   PREFIX_VEX_0F38AB,
1281   PREFIX_VEX_0F38AC,
1282   PREFIX_VEX_0F38AD,
1283   PREFIX_VEX_0F38AE,
1284   PREFIX_VEX_0F38AF,
1285   PREFIX_VEX_0F38B6,
1286   PREFIX_VEX_0F38B7,
1287   PREFIX_VEX_0F38B8,
1288   PREFIX_VEX_0F38B9,
1289   PREFIX_VEX_0F38BA,
1290   PREFIX_VEX_0F38BB,
1291   PREFIX_VEX_0F38BC,
1292   PREFIX_VEX_0F38BD,
1293   PREFIX_VEX_0F38BE,
1294   PREFIX_VEX_0F38BF,
1295   PREFIX_VEX_0F38DB,
1296   PREFIX_VEX_0F38DC,
1297   PREFIX_VEX_0F38DD,
1298   PREFIX_VEX_0F38DE,
1299   PREFIX_VEX_0F38DF,
1300   PREFIX_VEX_0F38F2,
1301   PREFIX_VEX_0F38F3_REG_1,
1302   PREFIX_VEX_0F38F3_REG_2,
1303   PREFIX_VEX_0F38F3_REG_3,
1304   PREFIX_VEX_0F38F5,
1305   PREFIX_VEX_0F38F6,
1306   PREFIX_VEX_0F38F7,
1307   PREFIX_VEX_0F3A00,
1308   PREFIX_VEX_0F3A01,
1309   PREFIX_VEX_0F3A02,
1310   PREFIX_VEX_0F3A04,
1311   PREFIX_VEX_0F3A05,
1312   PREFIX_VEX_0F3A06,
1313   PREFIX_VEX_0F3A08,
1314   PREFIX_VEX_0F3A09,
1315   PREFIX_VEX_0F3A0A,
1316   PREFIX_VEX_0F3A0B,
1317   PREFIX_VEX_0F3A0C,
1318   PREFIX_VEX_0F3A0D,
1319   PREFIX_VEX_0F3A0E,
1320   PREFIX_VEX_0F3A0F,
1321   PREFIX_VEX_0F3A14,
1322   PREFIX_VEX_0F3A15,
1323   PREFIX_VEX_0F3A16,
1324   PREFIX_VEX_0F3A17,
1325   PREFIX_VEX_0F3A18,
1326   PREFIX_VEX_0F3A19,
1327   PREFIX_VEX_0F3A1D,
1328   PREFIX_VEX_0F3A20,
1329   PREFIX_VEX_0F3A21,
1330   PREFIX_VEX_0F3A22,
1331   PREFIX_VEX_0F3A30,
1332   PREFIX_VEX_0F3A31,
1333   PREFIX_VEX_0F3A32,
1334   PREFIX_VEX_0F3A33,
1335   PREFIX_VEX_0F3A38,
1336   PREFIX_VEX_0F3A39,
1337   PREFIX_VEX_0F3A40,
1338   PREFIX_VEX_0F3A41,
1339   PREFIX_VEX_0F3A42,
1340   PREFIX_VEX_0F3A44,
1341   PREFIX_VEX_0F3A46,
1342   PREFIX_VEX_0F3A48,
1343   PREFIX_VEX_0F3A49,
1344   PREFIX_VEX_0F3A4A,
1345   PREFIX_VEX_0F3A4B,
1346   PREFIX_VEX_0F3A4C,
1347   PREFIX_VEX_0F3A5C,
1348   PREFIX_VEX_0F3A5D,
1349   PREFIX_VEX_0F3A5E,
1350   PREFIX_VEX_0F3A5F,
1351   PREFIX_VEX_0F3A60,
1352   PREFIX_VEX_0F3A61,
1353   PREFIX_VEX_0F3A62,
1354   PREFIX_VEX_0F3A63,
1355   PREFIX_VEX_0F3A68,
1356   PREFIX_VEX_0F3A69,
1357   PREFIX_VEX_0F3A6A,
1358   PREFIX_VEX_0F3A6B,
1359   PREFIX_VEX_0F3A6C,
1360   PREFIX_VEX_0F3A6D,
1361   PREFIX_VEX_0F3A6E,
1362   PREFIX_VEX_0F3A6F,
1363   PREFIX_VEX_0F3A78,
1364   PREFIX_VEX_0F3A79,
1365   PREFIX_VEX_0F3A7A,
1366   PREFIX_VEX_0F3A7B,
1367   PREFIX_VEX_0F3A7C,
1368   PREFIX_VEX_0F3A7D,
1369   PREFIX_VEX_0F3A7E,
1370   PREFIX_VEX_0F3A7F,
1371   PREFIX_VEX_0F3ADF,
1372   PREFIX_VEX_0F3AF0,
1373
1374   PREFIX_EVEX_0F10,
1375   PREFIX_EVEX_0F11,
1376   PREFIX_EVEX_0F12,
1377   PREFIX_EVEX_0F13,
1378   PREFIX_EVEX_0F14,
1379   PREFIX_EVEX_0F15,
1380   PREFIX_EVEX_0F16,
1381   PREFIX_EVEX_0F17,
1382   PREFIX_EVEX_0F28,
1383   PREFIX_EVEX_0F29,
1384   PREFIX_EVEX_0F2A,
1385   PREFIX_EVEX_0F2B,
1386   PREFIX_EVEX_0F2C,
1387   PREFIX_EVEX_0F2D,
1388   PREFIX_EVEX_0F2E,
1389   PREFIX_EVEX_0F2F,
1390   PREFIX_EVEX_0F51,
1391   PREFIX_EVEX_0F54,
1392   PREFIX_EVEX_0F55,
1393   PREFIX_EVEX_0F56,
1394   PREFIX_EVEX_0F57,
1395   PREFIX_EVEX_0F58,
1396   PREFIX_EVEX_0F59,
1397   PREFIX_EVEX_0F5A,
1398   PREFIX_EVEX_0F5B,
1399   PREFIX_EVEX_0F5C,
1400   PREFIX_EVEX_0F5D,
1401   PREFIX_EVEX_0F5E,
1402   PREFIX_EVEX_0F5F,
1403   PREFIX_EVEX_0F60,
1404   PREFIX_EVEX_0F61,
1405   PREFIX_EVEX_0F62,
1406   PREFIX_EVEX_0F63,
1407   PREFIX_EVEX_0F64,
1408   PREFIX_EVEX_0F65,
1409   PREFIX_EVEX_0F66,
1410   PREFIX_EVEX_0F67,
1411   PREFIX_EVEX_0F68,
1412   PREFIX_EVEX_0F69,
1413   PREFIX_EVEX_0F6A,
1414   PREFIX_EVEX_0F6B,
1415   PREFIX_EVEX_0F6C,
1416   PREFIX_EVEX_0F6D,
1417   PREFIX_EVEX_0F6E,
1418   PREFIX_EVEX_0F6F,
1419   PREFIX_EVEX_0F70,
1420   PREFIX_EVEX_0F71_REG_2,
1421   PREFIX_EVEX_0F71_REG_4,
1422   PREFIX_EVEX_0F71_REG_6,
1423   PREFIX_EVEX_0F72_REG_0,
1424   PREFIX_EVEX_0F72_REG_1,
1425   PREFIX_EVEX_0F72_REG_2,
1426   PREFIX_EVEX_0F72_REG_4,
1427   PREFIX_EVEX_0F72_REG_6,
1428   PREFIX_EVEX_0F73_REG_2,
1429   PREFIX_EVEX_0F73_REG_3,
1430   PREFIX_EVEX_0F73_REG_6,
1431   PREFIX_EVEX_0F73_REG_7,
1432   PREFIX_EVEX_0F74,
1433   PREFIX_EVEX_0F75,
1434   PREFIX_EVEX_0F76,
1435   PREFIX_EVEX_0F78,
1436   PREFIX_EVEX_0F79,
1437   PREFIX_EVEX_0F7A,
1438   PREFIX_EVEX_0F7B,
1439   PREFIX_EVEX_0F7E,
1440   PREFIX_EVEX_0F7F,
1441   PREFIX_EVEX_0FC2,
1442   PREFIX_EVEX_0FC4,
1443   PREFIX_EVEX_0FC5,
1444   PREFIX_EVEX_0FC6,
1445   PREFIX_EVEX_0FD1,
1446   PREFIX_EVEX_0FD2,
1447   PREFIX_EVEX_0FD3,
1448   PREFIX_EVEX_0FD4,
1449   PREFIX_EVEX_0FD5,
1450   PREFIX_EVEX_0FD6,
1451   PREFIX_EVEX_0FD8,
1452   PREFIX_EVEX_0FD9,
1453   PREFIX_EVEX_0FDA,
1454   PREFIX_EVEX_0FDB,
1455   PREFIX_EVEX_0FDC,
1456   PREFIX_EVEX_0FDD,
1457   PREFIX_EVEX_0FDE,
1458   PREFIX_EVEX_0FDF,
1459   PREFIX_EVEX_0FE0,
1460   PREFIX_EVEX_0FE1,
1461   PREFIX_EVEX_0FE2,
1462   PREFIX_EVEX_0FE3,
1463   PREFIX_EVEX_0FE4,
1464   PREFIX_EVEX_0FE5,
1465   PREFIX_EVEX_0FE6,
1466   PREFIX_EVEX_0FE7,
1467   PREFIX_EVEX_0FE8,
1468   PREFIX_EVEX_0FE9,
1469   PREFIX_EVEX_0FEA,
1470   PREFIX_EVEX_0FEB,
1471   PREFIX_EVEX_0FEC,
1472   PREFIX_EVEX_0FED,
1473   PREFIX_EVEX_0FEE,
1474   PREFIX_EVEX_0FEF,
1475   PREFIX_EVEX_0FF1,
1476   PREFIX_EVEX_0FF2,
1477   PREFIX_EVEX_0FF3,
1478   PREFIX_EVEX_0FF4,
1479   PREFIX_EVEX_0FF5,
1480   PREFIX_EVEX_0FF6,
1481   PREFIX_EVEX_0FF8,
1482   PREFIX_EVEX_0FF9,
1483   PREFIX_EVEX_0FFA,
1484   PREFIX_EVEX_0FFB,
1485   PREFIX_EVEX_0FFC,
1486   PREFIX_EVEX_0FFD,
1487   PREFIX_EVEX_0FFE,
1488   PREFIX_EVEX_0F3800,
1489   PREFIX_EVEX_0F3804,
1490   PREFIX_EVEX_0F380B,
1491   PREFIX_EVEX_0F380C,
1492   PREFIX_EVEX_0F380D,
1493   PREFIX_EVEX_0F3810,
1494   PREFIX_EVEX_0F3811,
1495   PREFIX_EVEX_0F3812,
1496   PREFIX_EVEX_0F3813,
1497   PREFIX_EVEX_0F3814,
1498   PREFIX_EVEX_0F3815,
1499   PREFIX_EVEX_0F3816,
1500   PREFIX_EVEX_0F3818,
1501   PREFIX_EVEX_0F3819,
1502   PREFIX_EVEX_0F381A,
1503   PREFIX_EVEX_0F381B,
1504   PREFIX_EVEX_0F381C,
1505   PREFIX_EVEX_0F381D,
1506   PREFIX_EVEX_0F381E,
1507   PREFIX_EVEX_0F381F,
1508   PREFIX_EVEX_0F3820,
1509   PREFIX_EVEX_0F3821,
1510   PREFIX_EVEX_0F3822,
1511   PREFIX_EVEX_0F3823,
1512   PREFIX_EVEX_0F3824,
1513   PREFIX_EVEX_0F3825,
1514   PREFIX_EVEX_0F3826,
1515   PREFIX_EVEX_0F3827,
1516   PREFIX_EVEX_0F3828,
1517   PREFIX_EVEX_0F3829,
1518   PREFIX_EVEX_0F382A,
1519   PREFIX_EVEX_0F382B,
1520   PREFIX_EVEX_0F382C,
1521   PREFIX_EVEX_0F382D,
1522   PREFIX_EVEX_0F3830,
1523   PREFIX_EVEX_0F3831,
1524   PREFIX_EVEX_0F3832,
1525   PREFIX_EVEX_0F3833,
1526   PREFIX_EVEX_0F3834,
1527   PREFIX_EVEX_0F3835,
1528   PREFIX_EVEX_0F3836,
1529   PREFIX_EVEX_0F3837,
1530   PREFIX_EVEX_0F3838,
1531   PREFIX_EVEX_0F3839,
1532   PREFIX_EVEX_0F383A,
1533   PREFIX_EVEX_0F383B,
1534   PREFIX_EVEX_0F383C,
1535   PREFIX_EVEX_0F383D,
1536   PREFIX_EVEX_0F383E,
1537   PREFIX_EVEX_0F383F,
1538   PREFIX_EVEX_0F3840,
1539   PREFIX_EVEX_0F3842,
1540   PREFIX_EVEX_0F3843,
1541   PREFIX_EVEX_0F3844,
1542   PREFIX_EVEX_0F3845,
1543   PREFIX_EVEX_0F3846,
1544   PREFIX_EVEX_0F3847,
1545   PREFIX_EVEX_0F384C,
1546   PREFIX_EVEX_0F384D,
1547   PREFIX_EVEX_0F384E,
1548   PREFIX_EVEX_0F384F,
1549   PREFIX_EVEX_0F3852,
1550   PREFIX_EVEX_0F3853,
1551   PREFIX_EVEX_0F3858,
1552   PREFIX_EVEX_0F3859,
1553   PREFIX_EVEX_0F385A,
1554   PREFIX_EVEX_0F385B,
1555   PREFIX_EVEX_0F3864,
1556   PREFIX_EVEX_0F3865,
1557   PREFIX_EVEX_0F3866,
1558   PREFIX_EVEX_0F3875,
1559   PREFIX_EVEX_0F3876,
1560   PREFIX_EVEX_0F3877,
1561   PREFIX_EVEX_0F3878,
1562   PREFIX_EVEX_0F3879,
1563   PREFIX_EVEX_0F387A,
1564   PREFIX_EVEX_0F387B,
1565   PREFIX_EVEX_0F387C,
1566   PREFIX_EVEX_0F387D,
1567   PREFIX_EVEX_0F387E,
1568   PREFIX_EVEX_0F387F,
1569   PREFIX_EVEX_0F3883,
1570   PREFIX_EVEX_0F3888,
1571   PREFIX_EVEX_0F3889,
1572   PREFIX_EVEX_0F388A,
1573   PREFIX_EVEX_0F388B,
1574   PREFIX_EVEX_0F388D,
1575   PREFIX_EVEX_0F3890,
1576   PREFIX_EVEX_0F3891,
1577   PREFIX_EVEX_0F3892,
1578   PREFIX_EVEX_0F3893,
1579   PREFIX_EVEX_0F3896,
1580   PREFIX_EVEX_0F3897,
1581   PREFIX_EVEX_0F3898,
1582   PREFIX_EVEX_0F3899,
1583   PREFIX_EVEX_0F389A,
1584   PREFIX_EVEX_0F389B,
1585   PREFIX_EVEX_0F389C,
1586   PREFIX_EVEX_0F389D,
1587   PREFIX_EVEX_0F389E,
1588   PREFIX_EVEX_0F389F,
1589   PREFIX_EVEX_0F38A0,
1590   PREFIX_EVEX_0F38A1,
1591   PREFIX_EVEX_0F38A2,
1592   PREFIX_EVEX_0F38A3,
1593   PREFIX_EVEX_0F38A6,
1594   PREFIX_EVEX_0F38A7,
1595   PREFIX_EVEX_0F38A8,
1596   PREFIX_EVEX_0F38A9,
1597   PREFIX_EVEX_0F38AA,
1598   PREFIX_EVEX_0F38AB,
1599   PREFIX_EVEX_0F38AC,
1600   PREFIX_EVEX_0F38AD,
1601   PREFIX_EVEX_0F38AE,
1602   PREFIX_EVEX_0F38AF,
1603   PREFIX_EVEX_0F38B4,
1604   PREFIX_EVEX_0F38B5,
1605   PREFIX_EVEX_0F38B6,
1606   PREFIX_EVEX_0F38B7,
1607   PREFIX_EVEX_0F38B8,
1608   PREFIX_EVEX_0F38B9,
1609   PREFIX_EVEX_0F38BA,
1610   PREFIX_EVEX_0F38BB,
1611   PREFIX_EVEX_0F38BC,
1612   PREFIX_EVEX_0F38BD,
1613   PREFIX_EVEX_0F38BE,
1614   PREFIX_EVEX_0F38BF,
1615   PREFIX_EVEX_0F38C4,
1616   PREFIX_EVEX_0F38C6_REG_1,
1617   PREFIX_EVEX_0F38C6_REG_2,
1618   PREFIX_EVEX_0F38C6_REG_5,
1619   PREFIX_EVEX_0F38C6_REG_6,
1620   PREFIX_EVEX_0F38C7_REG_1,
1621   PREFIX_EVEX_0F38C7_REG_2,
1622   PREFIX_EVEX_0F38C7_REG_5,
1623   PREFIX_EVEX_0F38C7_REG_6,
1624   PREFIX_EVEX_0F38C8,
1625   PREFIX_EVEX_0F38CA,
1626   PREFIX_EVEX_0F38CB,
1627   PREFIX_EVEX_0F38CC,
1628   PREFIX_EVEX_0F38CD,
1629
1630   PREFIX_EVEX_0F3A00,
1631   PREFIX_EVEX_0F3A01,
1632   PREFIX_EVEX_0F3A03,
1633   PREFIX_EVEX_0F3A04,
1634   PREFIX_EVEX_0F3A05,
1635   PREFIX_EVEX_0F3A08,
1636   PREFIX_EVEX_0F3A09,
1637   PREFIX_EVEX_0F3A0A,
1638   PREFIX_EVEX_0F3A0B,
1639   PREFIX_EVEX_0F3A0F,
1640   PREFIX_EVEX_0F3A14,
1641   PREFIX_EVEX_0F3A15,
1642   PREFIX_EVEX_0F3A16,
1643   PREFIX_EVEX_0F3A17,
1644   PREFIX_EVEX_0F3A18,
1645   PREFIX_EVEX_0F3A19,
1646   PREFIX_EVEX_0F3A1A,
1647   PREFIX_EVEX_0F3A1B,
1648   PREFIX_EVEX_0F3A1D,
1649   PREFIX_EVEX_0F3A1E,
1650   PREFIX_EVEX_0F3A1F,
1651   PREFIX_EVEX_0F3A20,
1652   PREFIX_EVEX_0F3A21,
1653   PREFIX_EVEX_0F3A22,
1654   PREFIX_EVEX_0F3A23,
1655   PREFIX_EVEX_0F3A25,
1656   PREFIX_EVEX_0F3A26,
1657   PREFIX_EVEX_0F3A27,
1658   PREFIX_EVEX_0F3A38,
1659   PREFIX_EVEX_0F3A39,
1660   PREFIX_EVEX_0F3A3A,
1661   PREFIX_EVEX_0F3A3B,
1662   PREFIX_EVEX_0F3A3E,
1663   PREFIX_EVEX_0F3A3F,
1664   PREFIX_EVEX_0F3A42,
1665   PREFIX_EVEX_0F3A43,
1666   PREFIX_EVEX_0F3A50,
1667   PREFIX_EVEX_0F3A51,
1668   PREFIX_EVEX_0F3A54,
1669   PREFIX_EVEX_0F3A55,
1670   PREFIX_EVEX_0F3A56,
1671   PREFIX_EVEX_0F3A57,
1672   PREFIX_EVEX_0F3A66,
1673   PREFIX_EVEX_0F3A67
1674 };
1675
1676 enum
1677 {
1678   X86_64_06 = 0,
1679   X86_64_07,
1680   X86_64_0D,
1681   X86_64_16,
1682   X86_64_17,
1683   X86_64_1E,
1684   X86_64_1F,
1685   X86_64_27,
1686   X86_64_2F,
1687   X86_64_37,
1688   X86_64_3F,
1689   X86_64_60,
1690   X86_64_61,
1691   X86_64_62,
1692   X86_64_63,
1693   X86_64_6D,
1694   X86_64_6F,
1695   X86_64_82,
1696   X86_64_9A,
1697   X86_64_C4,
1698   X86_64_C5,
1699   X86_64_CE,
1700   X86_64_D4,
1701   X86_64_D5,
1702   X86_64_E8,
1703   X86_64_E9,
1704   X86_64_EA,
1705   X86_64_0F01_REG_0,
1706   X86_64_0F01_REG_1,
1707   X86_64_0F01_REG_2,
1708   X86_64_0F01_REG_3
1709 };
1710
1711 enum
1712 {
1713   THREE_BYTE_0F38 = 0,
1714   THREE_BYTE_0F3A
1715 };
1716
1717 enum
1718 {
1719   XOP_08 = 0,
1720   XOP_09,
1721   XOP_0A
1722 };
1723
1724 enum
1725 {
1726   VEX_0F = 0,
1727   VEX_0F38,
1728   VEX_0F3A
1729 };
1730
1731 enum
1732 {
1733   EVEX_0F = 0,
1734   EVEX_0F38,
1735   EVEX_0F3A
1736 };
1737
1738 enum
1739 {
1740   VEX_LEN_0F10_P_1 = 0,
1741   VEX_LEN_0F10_P_3,
1742   VEX_LEN_0F11_P_1,
1743   VEX_LEN_0F11_P_3,
1744   VEX_LEN_0F12_P_0_M_0,
1745   VEX_LEN_0F12_P_0_M_1,
1746   VEX_LEN_0F12_P_2,
1747   VEX_LEN_0F13_M_0,
1748   VEX_LEN_0F16_P_0_M_0,
1749   VEX_LEN_0F16_P_0_M_1,
1750   VEX_LEN_0F16_P_2,
1751   VEX_LEN_0F17_M_0,
1752   VEX_LEN_0F2A_P_1,
1753   VEX_LEN_0F2A_P_3,
1754   VEX_LEN_0F2C_P_1,
1755   VEX_LEN_0F2C_P_3,
1756   VEX_LEN_0F2D_P_1,
1757   VEX_LEN_0F2D_P_3,
1758   VEX_LEN_0F2E_P_0,
1759   VEX_LEN_0F2E_P_2,
1760   VEX_LEN_0F2F_P_0,
1761   VEX_LEN_0F2F_P_2,
1762   VEX_LEN_0F41_P_0,
1763   VEX_LEN_0F41_P_2,
1764   VEX_LEN_0F42_P_0,
1765   VEX_LEN_0F42_P_2,
1766   VEX_LEN_0F44_P_0,
1767   VEX_LEN_0F44_P_2,
1768   VEX_LEN_0F45_P_0,
1769   VEX_LEN_0F45_P_2,
1770   VEX_LEN_0F46_P_0,
1771   VEX_LEN_0F46_P_2,
1772   VEX_LEN_0F47_P_0,
1773   VEX_LEN_0F47_P_2,
1774   VEX_LEN_0F4A_P_0,
1775   VEX_LEN_0F4A_P_2,
1776   VEX_LEN_0F4B_P_0,
1777   VEX_LEN_0F4B_P_2,
1778   VEX_LEN_0F51_P_1,
1779   VEX_LEN_0F51_P_3,
1780   VEX_LEN_0F52_P_1,
1781   VEX_LEN_0F53_P_1,
1782   VEX_LEN_0F58_P_1,
1783   VEX_LEN_0F58_P_3,
1784   VEX_LEN_0F59_P_1,
1785   VEX_LEN_0F59_P_3,
1786   VEX_LEN_0F5A_P_1,
1787   VEX_LEN_0F5A_P_3,
1788   VEX_LEN_0F5C_P_1,
1789   VEX_LEN_0F5C_P_3,
1790   VEX_LEN_0F5D_P_1,
1791   VEX_LEN_0F5D_P_3,
1792   VEX_LEN_0F5E_P_1,
1793   VEX_LEN_0F5E_P_3,
1794   VEX_LEN_0F5F_P_1,
1795   VEX_LEN_0F5F_P_3,
1796   VEX_LEN_0F6E_P_2,
1797   VEX_LEN_0F7E_P_1,
1798   VEX_LEN_0F7E_P_2,
1799   VEX_LEN_0F90_P_0,
1800   VEX_LEN_0F90_P_2,
1801   VEX_LEN_0F91_P_0,
1802   VEX_LEN_0F91_P_2,
1803   VEX_LEN_0F92_P_0,
1804   VEX_LEN_0F92_P_2,
1805   VEX_LEN_0F92_P_3,
1806   VEX_LEN_0F93_P_0,
1807   VEX_LEN_0F93_P_2,
1808   VEX_LEN_0F93_P_3,
1809   VEX_LEN_0F98_P_0,
1810   VEX_LEN_0F98_P_2,
1811   VEX_LEN_0F99_P_0,
1812   VEX_LEN_0F99_P_2,
1813   VEX_LEN_0FAE_R_2_M_0,
1814   VEX_LEN_0FAE_R_3_M_0,
1815   VEX_LEN_0FC2_P_1,
1816   VEX_LEN_0FC2_P_3,
1817   VEX_LEN_0FC4_P_2,
1818   VEX_LEN_0FC5_P_2,
1819   VEX_LEN_0FD6_P_2,
1820   VEX_LEN_0FF7_P_2,
1821   VEX_LEN_0F3816_P_2,
1822   VEX_LEN_0F3819_P_2,
1823   VEX_LEN_0F381A_P_2_M_0,
1824   VEX_LEN_0F3836_P_2,
1825   VEX_LEN_0F3841_P_2,
1826   VEX_LEN_0F385A_P_2_M_0,
1827   VEX_LEN_0F38DB_P_2,
1828   VEX_LEN_0F38DC_P_2,
1829   VEX_LEN_0F38DD_P_2,
1830   VEX_LEN_0F38DE_P_2,
1831   VEX_LEN_0F38DF_P_2,
1832   VEX_LEN_0F38F2_P_0,
1833   VEX_LEN_0F38F3_R_1_P_0,
1834   VEX_LEN_0F38F3_R_2_P_0,
1835   VEX_LEN_0F38F3_R_3_P_0,
1836   VEX_LEN_0F38F5_P_0,
1837   VEX_LEN_0F38F5_P_1,
1838   VEX_LEN_0F38F5_P_3,
1839   VEX_LEN_0F38F6_P_3,
1840   VEX_LEN_0F38F7_P_0,
1841   VEX_LEN_0F38F7_P_1,
1842   VEX_LEN_0F38F7_P_2,
1843   VEX_LEN_0F38F7_P_3,
1844   VEX_LEN_0F3A00_P_2,
1845   VEX_LEN_0F3A01_P_2,
1846   VEX_LEN_0F3A06_P_2,
1847   VEX_LEN_0F3A0A_P_2,
1848   VEX_LEN_0F3A0B_P_2,
1849   VEX_LEN_0F3A14_P_2,
1850   VEX_LEN_0F3A15_P_2,
1851   VEX_LEN_0F3A16_P_2,
1852   VEX_LEN_0F3A17_P_2,
1853   VEX_LEN_0F3A18_P_2,
1854   VEX_LEN_0F3A19_P_2,
1855   VEX_LEN_0F3A20_P_2,
1856   VEX_LEN_0F3A21_P_2,
1857   VEX_LEN_0F3A22_P_2,
1858   VEX_LEN_0F3A30_P_2,
1859   VEX_LEN_0F3A31_P_2,
1860   VEX_LEN_0F3A32_P_2,
1861   VEX_LEN_0F3A33_P_2,
1862   VEX_LEN_0F3A38_P_2,
1863   VEX_LEN_0F3A39_P_2,
1864   VEX_LEN_0F3A41_P_2,
1865   VEX_LEN_0F3A44_P_2,
1866   VEX_LEN_0F3A46_P_2,
1867   VEX_LEN_0F3A60_P_2,
1868   VEX_LEN_0F3A61_P_2,
1869   VEX_LEN_0F3A62_P_2,
1870   VEX_LEN_0F3A63_P_2,
1871   VEX_LEN_0F3A6A_P_2,
1872   VEX_LEN_0F3A6B_P_2,
1873   VEX_LEN_0F3A6E_P_2,
1874   VEX_LEN_0F3A6F_P_2,
1875   VEX_LEN_0F3A7A_P_2,
1876   VEX_LEN_0F3A7B_P_2,
1877   VEX_LEN_0F3A7E_P_2,
1878   VEX_LEN_0F3A7F_P_2,
1879   VEX_LEN_0F3ADF_P_2,
1880   VEX_LEN_0F3AF0_P_3,
1881   VEX_LEN_0FXOP_08_CC,
1882   VEX_LEN_0FXOP_08_CD,
1883   VEX_LEN_0FXOP_08_CE,
1884   VEX_LEN_0FXOP_08_CF,
1885   VEX_LEN_0FXOP_08_EC,
1886   VEX_LEN_0FXOP_08_ED,
1887   VEX_LEN_0FXOP_08_EE,
1888   VEX_LEN_0FXOP_08_EF,
1889   VEX_LEN_0FXOP_09_80,
1890   VEX_LEN_0FXOP_09_81
1891 };
1892
1893 enum
1894 {
1895   VEX_W_0F10_P_0 = 0,
1896   VEX_W_0F10_P_1,
1897   VEX_W_0F10_P_2,
1898   VEX_W_0F10_P_3,
1899   VEX_W_0F11_P_0,
1900   VEX_W_0F11_P_1,
1901   VEX_W_0F11_P_2,
1902   VEX_W_0F11_P_3,
1903   VEX_W_0F12_P_0_M_0,
1904   VEX_W_0F12_P_0_M_1,
1905   VEX_W_0F12_P_1,
1906   VEX_W_0F12_P_2,
1907   VEX_W_0F12_P_3,
1908   VEX_W_0F13_M_0,
1909   VEX_W_0F14,
1910   VEX_W_0F15,
1911   VEX_W_0F16_P_0_M_0,
1912   VEX_W_0F16_P_0_M_1,
1913   VEX_W_0F16_P_1,
1914   VEX_W_0F16_P_2,
1915   VEX_W_0F17_M_0,
1916   VEX_W_0F28,
1917   VEX_W_0F29,
1918   VEX_W_0F2B_M_0,
1919   VEX_W_0F2E_P_0,
1920   VEX_W_0F2E_P_2,
1921   VEX_W_0F2F_P_0,
1922   VEX_W_0F2F_P_2,
1923   VEX_W_0F41_P_0_LEN_1,
1924   VEX_W_0F41_P_2_LEN_1,
1925   VEX_W_0F42_P_0_LEN_1,
1926   VEX_W_0F42_P_2_LEN_1,
1927   VEX_W_0F44_P_0_LEN_0,
1928   VEX_W_0F44_P_2_LEN_0,
1929   VEX_W_0F45_P_0_LEN_1,
1930   VEX_W_0F45_P_2_LEN_1,
1931   VEX_W_0F46_P_0_LEN_1,
1932   VEX_W_0F46_P_2_LEN_1,
1933   VEX_W_0F47_P_0_LEN_1,
1934   VEX_W_0F47_P_2_LEN_1,
1935   VEX_W_0F4A_P_0_LEN_1,
1936   VEX_W_0F4A_P_2_LEN_1,
1937   VEX_W_0F4B_P_0_LEN_1,
1938   VEX_W_0F4B_P_2_LEN_1,
1939   VEX_W_0F50_M_0,
1940   VEX_W_0F51_P_0,
1941   VEX_W_0F51_P_1,
1942   VEX_W_0F51_P_2,
1943   VEX_W_0F51_P_3,
1944   VEX_W_0F52_P_0,
1945   VEX_W_0F52_P_1,
1946   VEX_W_0F53_P_0,
1947   VEX_W_0F53_P_1,
1948   VEX_W_0F58_P_0,
1949   VEX_W_0F58_P_1,
1950   VEX_W_0F58_P_2,
1951   VEX_W_0F58_P_3,
1952   VEX_W_0F59_P_0,
1953   VEX_W_0F59_P_1,
1954   VEX_W_0F59_P_2,
1955   VEX_W_0F59_P_3,
1956   VEX_W_0F5A_P_0,
1957   VEX_W_0F5A_P_1,
1958   VEX_W_0F5A_P_3,
1959   VEX_W_0F5B_P_0,
1960   VEX_W_0F5B_P_1,
1961   VEX_W_0F5B_P_2,
1962   VEX_W_0F5C_P_0,
1963   VEX_W_0F5C_P_1,
1964   VEX_W_0F5C_P_2,
1965   VEX_W_0F5C_P_3,
1966   VEX_W_0F5D_P_0,
1967   VEX_W_0F5D_P_1,
1968   VEX_W_0F5D_P_2,
1969   VEX_W_0F5D_P_3,
1970   VEX_W_0F5E_P_0,
1971   VEX_W_0F5E_P_1,
1972   VEX_W_0F5E_P_2,
1973   VEX_W_0F5E_P_3,
1974   VEX_W_0F5F_P_0,
1975   VEX_W_0F5F_P_1,
1976   VEX_W_0F5F_P_2,
1977   VEX_W_0F5F_P_3,
1978   VEX_W_0F60_P_2,
1979   VEX_W_0F61_P_2,
1980   VEX_W_0F62_P_2,
1981   VEX_W_0F63_P_2,
1982   VEX_W_0F64_P_2,
1983   VEX_W_0F65_P_2,
1984   VEX_W_0F66_P_2,
1985   VEX_W_0F67_P_2,
1986   VEX_W_0F68_P_2,
1987   VEX_W_0F69_P_2,
1988   VEX_W_0F6A_P_2,
1989   VEX_W_0F6B_P_2,
1990   VEX_W_0F6C_P_2,
1991   VEX_W_0F6D_P_2,
1992   VEX_W_0F6F_P_1,
1993   VEX_W_0F6F_P_2,
1994   VEX_W_0F70_P_1,
1995   VEX_W_0F70_P_2,
1996   VEX_W_0F70_P_3,
1997   VEX_W_0F71_R_2_P_2,
1998   VEX_W_0F71_R_4_P_2,
1999   VEX_W_0F71_R_6_P_2,
2000   VEX_W_0F72_R_2_P_2,
2001   VEX_W_0F72_R_4_P_2,
2002   VEX_W_0F72_R_6_P_2,
2003   VEX_W_0F73_R_2_P_2,
2004   VEX_W_0F73_R_3_P_2,
2005   VEX_W_0F73_R_6_P_2,
2006   VEX_W_0F73_R_7_P_2,
2007   VEX_W_0F74_P_2,
2008   VEX_W_0F75_P_2,
2009   VEX_W_0F76_P_2,
2010   VEX_W_0F77_P_0,
2011   VEX_W_0F7C_P_2,
2012   VEX_W_0F7C_P_3,
2013   VEX_W_0F7D_P_2,
2014   VEX_W_0F7D_P_3,
2015   VEX_W_0F7E_P_1,
2016   VEX_W_0F7F_P_1,
2017   VEX_W_0F7F_P_2,
2018   VEX_W_0F90_P_0_LEN_0,
2019   VEX_W_0F90_P_2_LEN_0,
2020   VEX_W_0F91_P_0_LEN_0,
2021   VEX_W_0F91_P_2_LEN_0,
2022   VEX_W_0F92_P_0_LEN_0,
2023   VEX_W_0F92_P_2_LEN_0,
2024   VEX_W_0F92_P_3_LEN_0,
2025   VEX_W_0F93_P_0_LEN_0,
2026   VEX_W_0F93_P_2_LEN_0,
2027   VEX_W_0F93_P_3_LEN_0,
2028   VEX_W_0F98_P_0_LEN_0,
2029   VEX_W_0F98_P_2_LEN_0,
2030   VEX_W_0F99_P_0_LEN_0,
2031   VEX_W_0F99_P_2_LEN_0,
2032   VEX_W_0FAE_R_2_M_0,
2033   VEX_W_0FAE_R_3_M_0,
2034   VEX_W_0FC2_P_0,
2035   VEX_W_0FC2_P_1,
2036   VEX_W_0FC2_P_2,
2037   VEX_W_0FC2_P_3,
2038   VEX_W_0FC4_P_2,
2039   VEX_W_0FC5_P_2,
2040   VEX_W_0FD0_P_2,
2041   VEX_W_0FD0_P_3,
2042   VEX_W_0FD1_P_2,
2043   VEX_W_0FD2_P_2,
2044   VEX_W_0FD3_P_2,
2045   VEX_W_0FD4_P_2,
2046   VEX_W_0FD5_P_2,
2047   VEX_W_0FD6_P_2,
2048   VEX_W_0FD7_P_2_M_1,
2049   VEX_W_0FD8_P_2,
2050   VEX_W_0FD9_P_2,
2051   VEX_W_0FDA_P_2,
2052   VEX_W_0FDB_P_2,
2053   VEX_W_0FDC_P_2,
2054   VEX_W_0FDD_P_2,
2055   VEX_W_0FDE_P_2,
2056   VEX_W_0FDF_P_2,
2057   VEX_W_0FE0_P_2,
2058   VEX_W_0FE1_P_2,
2059   VEX_W_0FE2_P_2,
2060   VEX_W_0FE3_P_2,
2061   VEX_W_0FE4_P_2,
2062   VEX_W_0FE5_P_2,
2063   VEX_W_0FE6_P_1,
2064   VEX_W_0FE6_P_2,
2065   VEX_W_0FE6_P_3,
2066   VEX_W_0FE7_P_2_M_0,
2067   VEX_W_0FE8_P_2,
2068   VEX_W_0FE9_P_2,
2069   VEX_W_0FEA_P_2,
2070   VEX_W_0FEB_P_2,
2071   VEX_W_0FEC_P_2,
2072   VEX_W_0FED_P_2,
2073   VEX_W_0FEE_P_2,
2074   VEX_W_0FEF_P_2,
2075   VEX_W_0FF0_P_3_M_0,
2076   VEX_W_0FF1_P_2,
2077   VEX_W_0FF2_P_2,
2078   VEX_W_0FF3_P_2,
2079   VEX_W_0FF4_P_2,
2080   VEX_W_0FF5_P_2,
2081   VEX_W_0FF6_P_2,
2082   VEX_W_0FF7_P_2,
2083   VEX_W_0FF8_P_2,
2084   VEX_W_0FF9_P_2,
2085   VEX_W_0FFA_P_2,
2086   VEX_W_0FFB_P_2,
2087   VEX_W_0FFC_P_2,
2088   VEX_W_0FFD_P_2,
2089   VEX_W_0FFE_P_2,
2090   VEX_W_0F3800_P_2,
2091   VEX_W_0F3801_P_2,
2092   VEX_W_0F3802_P_2,
2093   VEX_W_0F3803_P_2,
2094   VEX_W_0F3804_P_2,
2095   VEX_W_0F3805_P_2,
2096   VEX_W_0F3806_P_2,
2097   VEX_W_0F3807_P_2,
2098   VEX_W_0F3808_P_2,
2099   VEX_W_0F3809_P_2,
2100   VEX_W_0F380A_P_2,
2101   VEX_W_0F380B_P_2,
2102   VEX_W_0F380C_P_2,
2103   VEX_W_0F380D_P_2,
2104   VEX_W_0F380E_P_2,
2105   VEX_W_0F380F_P_2,
2106   VEX_W_0F3816_P_2,
2107   VEX_W_0F3817_P_2,
2108   VEX_W_0F3818_P_2,
2109   VEX_W_0F3819_P_2,
2110   VEX_W_0F381A_P_2_M_0,
2111   VEX_W_0F381C_P_2,
2112   VEX_W_0F381D_P_2,
2113   VEX_W_0F381E_P_2,
2114   VEX_W_0F3820_P_2,
2115   VEX_W_0F3821_P_2,
2116   VEX_W_0F3822_P_2,
2117   VEX_W_0F3823_P_2,
2118   VEX_W_0F3824_P_2,
2119   VEX_W_0F3825_P_2,
2120   VEX_W_0F3828_P_2,
2121   VEX_W_0F3829_P_2,
2122   VEX_W_0F382A_P_2_M_0,
2123   VEX_W_0F382B_P_2,
2124   VEX_W_0F382C_P_2_M_0,
2125   VEX_W_0F382D_P_2_M_0,
2126   VEX_W_0F382E_P_2_M_0,
2127   VEX_W_0F382F_P_2_M_0,
2128   VEX_W_0F3830_P_2,
2129   VEX_W_0F3831_P_2,
2130   VEX_W_0F3832_P_2,
2131   VEX_W_0F3833_P_2,
2132   VEX_W_0F3834_P_2,
2133   VEX_W_0F3835_P_2,
2134   VEX_W_0F3836_P_2,
2135   VEX_W_0F3837_P_2,
2136   VEX_W_0F3838_P_2,
2137   VEX_W_0F3839_P_2,
2138   VEX_W_0F383A_P_2,
2139   VEX_W_0F383B_P_2,
2140   VEX_W_0F383C_P_2,
2141   VEX_W_0F383D_P_2,
2142   VEX_W_0F383E_P_2,
2143   VEX_W_0F383F_P_2,
2144   VEX_W_0F3840_P_2,
2145   VEX_W_0F3841_P_2,
2146   VEX_W_0F3846_P_2,
2147   VEX_W_0F3858_P_2,
2148   VEX_W_0F3859_P_2,
2149   VEX_W_0F385A_P_2_M_0,
2150   VEX_W_0F3878_P_2,
2151   VEX_W_0F3879_P_2,
2152   VEX_W_0F38DB_P_2,
2153   VEX_W_0F38DC_P_2,
2154   VEX_W_0F38DD_P_2,
2155   VEX_W_0F38DE_P_2,
2156   VEX_W_0F38DF_P_2,
2157   VEX_W_0F3A00_P_2,
2158   VEX_W_0F3A01_P_2,
2159   VEX_W_0F3A02_P_2,
2160   VEX_W_0F3A04_P_2,
2161   VEX_W_0F3A05_P_2,
2162   VEX_W_0F3A06_P_2,
2163   VEX_W_0F3A08_P_2,
2164   VEX_W_0F3A09_P_2,
2165   VEX_W_0F3A0A_P_2,
2166   VEX_W_0F3A0B_P_2,
2167   VEX_W_0F3A0C_P_2,
2168   VEX_W_0F3A0D_P_2,
2169   VEX_W_0F3A0E_P_2,
2170   VEX_W_0F3A0F_P_2,
2171   VEX_W_0F3A14_P_2,
2172   VEX_W_0F3A15_P_2,
2173   VEX_W_0F3A18_P_2,
2174   VEX_W_0F3A19_P_2,
2175   VEX_W_0F3A20_P_2,
2176   VEX_W_0F3A21_P_2,
2177   VEX_W_0F3A30_P_2_LEN_0,
2178   VEX_W_0F3A31_P_2_LEN_0,
2179   VEX_W_0F3A32_P_2_LEN_0,
2180   VEX_W_0F3A33_P_2_LEN_0,
2181   VEX_W_0F3A38_P_2,
2182   VEX_W_0F3A39_P_2,
2183   VEX_W_0F3A40_P_2,
2184   VEX_W_0F3A41_P_2,
2185   VEX_W_0F3A42_P_2,
2186   VEX_W_0F3A44_P_2,
2187   VEX_W_0F3A46_P_2,
2188   VEX_W_0F3A48_P_2,
2189   VEX_W_0F3A49_P_2,
2190   VEX_W_0F3A4A_P_2,
2191   VEX_W_0F3A4B_P_2,
2192   VEX_W_0F3A4C_P_2,
2193   VEX_W_0F3A60_P_2,
2194   VEX_W_0F3A61_P_2,
2195   VEX_W_0F3A62_P_2,
2196   VEX_W_0F3A63_P_2,
2197   VEX_W_0F3ADF_P_2,
2198
2199   EVEX_W_0F10_P_0,
2200   EVEX_W_0F10_P_1_M_0,
2201   EVEX_W_0F10_P_1_M_1,
2202   EVEX_W_0F10_P_2,
2203   EVEX_W_0F10_P_3_M_0,
2204   EVEX_W_0F10_P_3_M_1,
2205   EVEX_W_0F11_P_0,
2206   EVEX_W_0F11_P_1_M_0,
2207   EVEX_W_0F11_P_1_M_1,
2208   EVEX_W_0F11_P_2,
2209   EVEX_W_0F11_P_3_M_0,
2210   EVEX_W_0F11_P_3_M_1,
2211   EVEX_W_0F12_P_0_M_0,
2212   EVEX_W_0F12_P_0_M_1,
2213   EVEX_W_0F12_P_1,
2214   EVEX_W_0F12_P_2,
2215   EVEX_W_0F12_P_3,
2216   EVEX_W_0F13_P_0,
2217   EVEX_W_0F13_P_2,
2218   EVEX_W_0F14_P_0,
2219   EVEX_W_0F14_P_2,
2220   EVEX_W_0F15_P_0,
2221   EVEX_W_0F15_P_2,
2222   EVEX_W_0F16_P_0_M_0,
2223   EVEX_W_0F16_P_0_M_1,
2224   EVEX_W_0F16_P_1,
2225   EVEX_W_0F16_P_2,
2226   EVEX_W_0F17_P_0,
2227   EVEX_W_0F17_P_2,
2228   EVEX_W_0F28_P_0,
2229   EVEX_W_0F28_P_2,
2230   EVEX_W_0F29_P_0,
2231   EVEX_W_0F29_P_2,
2232   EVEX_W_0F2A_P_1,
2233   EVEX_W_0F2A_P_3,
2234   EVEX_W_0F2B_P_0,
2235   EVEX_W_0F2B_P_2,
2236   EVEX_W_0F2E_P_0,
2237   EVEX_W_0F2E_P_2,
2238   EVEX_W_0F2F_P_0,
2239   EVEX_W_0F2F_P_2,
2240   EVEX_W_0F51_P_0,
2241   EVEX_W_0F51_P_1,
2242   EVEX_W_0F51_P_2,
2243   EVEX_W_0F51_P_3,
2244   EVEX_W_0F54_P_0,
2245   EVEX_W_0F54_P_2,
2246   EVEX_W_0F55_P_0,
2247   EVEX_W_0F55_P_2,
2248   EVEX_W_0F56_P_0,
2249   EVEX_W_0F56_P_2,
2250   EVEX_W_0F57_P_0,
2251   EVEX_W_0F57_P_2,
2252   EVEX_W_0F58_P_0,
2253   EVEX_W_0F58_P_1,
2254   EVEX_W_0F58_P_2,
2255   EVEX_W_0F58_P_3,
2256   EVEX_W_0F59_P_0,
2257   EVEX_W_0F59_P_1,
2258   EVEX_W_0F59_P_2,
2259   EVEX_W_0F59_P_3,
2260   EVEX_W_0F5A_P_0,
2261   EVEX_W_0F5A_P_1,
2262   EVEX_W_0F5A_P_2,
2263   EVEX_W_0F5A_P_3,
2264   EVEX_W_0F5B_P_0,
2265   EVEX_W_0F5B_P_1,
2266   EVEX_W_0F5B_P_2,
2267   EVEX_W_0F5C_P_0,
2268   EVEX_W_0F5C_P_1,
2269   EVEX_W_0F5C_P_2,
2270   EVEX_W_0F5C_P_3,
2271   EVEX_W_0F5D_P_0,
2272   EVEX_W_0F5D_P_1,
2273   EVEX_W_0F5D_P_2,
2274   EVEX_W_0F5D_P_3,
2275   EVEX_W_0F5E_P_0,
2276   EVEX_W_0F5E_P_1,
2277   EVEX_W_0F5E_P_2,
2278   EVEX_W_0F5E_P_3,
2279   EVEX_W_0F5F_P_0,
2280   EVEX_W_0F5F_P_1,
2281   EVEX_W_0F5F_P_2,
2282   EVEX_W_0F5F_P_3,
2283   EVEX_W_0F62_P_2,
2284   EVEX_W_0F66_P_2,
2285   EVEX_W_0F6A_P_2,
2286   EVEX_W_0F6B_P_2,
2287   EVEX_W_0F6C_P_2,
2288   EVEX_W_0F6D_P_2,
2289   EVEX_W_0F6E_P_2,
2290   EVEX_W_0F6F_P_1,
2291   EVEX_W_0F6F_P_2,
2292   EVEX_W_0F6F_P_3,
2293   EVEX_W_0F70_P_2,
2294   EVEX_W_0F72_R_2_P_2,
2295   EVEX_W_0F72_R_6_P_2,
2296   EVEX_W_0F73_R_2_P_2,
2297   EVEX_W_0F73_R_6_P_2,
2298   EVEX_W_0F76_P_2,
2299   EVEX_W_0F78_P_0,
2300   EVEX_W_0F78_P_2,
2301   EVEX_W_0F79_P_0,
2302   EVEX_W_0F79_P_2,
2303   EVEX_W_0F7A_P_1,
2304   EVEX_W_0F7A_P_2,
2305   EVEX_W_0F7A_P_3,
2306   EVEX_W_0F7B_P_1,
2307   EVEX_W_0F7B_P_2,
2308   EVEX_W_0F7B_P_3,
2309   EVEX_W_0F7E_P_1,
2310   EVEX_W_0F7E_P_2,
2311   EVEX_W_0F7F_P_1,
2312   EVEX_W_0F7F_P_2,
2313   EVEX_W_0F7F_P_3,
2314   EVEX_W_0FC2_P_0,
2315   EVEX_W_0FC2_P_1,
2316   EVEX_W_0FC2_P_2,
2317   EVEX_W_0FC2_P_3,
2318   EVEX_W_0FC6_P_0,
2319   EVEX_W_0FC6_P_2,
2320   EVEX_W_0FD2_P_2,
2321   EVEX_W_0FD3_P_2,
2322   EVEX_W_0FD4_P_2,
2323   EVEX_W_0FD6_P_2,
2324   EVEX_W_0FE6_P_1,
2325   EVEX_W_0FE6_P_2,
2326   EVEX_W_0FE6_P_3,
2327   EVEX_W_0FE7_P_2,
2328   EVEX_W_0FF2_P_2,
2329   EVEX_W_0FF3_P_2,
2330   EVEX_W_0FF4_P_2,
2331   EVEX_W_0FFA_P_2,
2332   EVEX_W_0FFB_P_2,
2333   EVEX_W_0FFE_P_2,
2334   EVEX_W_0F380C_P_2,
2335   EVEX_W_0F380D_P_2,
2336   EVEX_W_0F3810_P_1,
2337   EVEX_W_0F3810_P_2,
2338   EVEX_W_0F3811_P_1,
2339   EVEX_W_0F3811_P_2,
2340   EVEX_W_0F3812_P_1,
2341   EVEX_W_0F3812_P_2,
2342   EVEX_W_0F3813_P_1,
2343   EVEX_W_0F3813_P_2,
2344   EVEX_W_0F3814_P_1,
2345   EVEX_W_0F3815_P_1,
2346   EVEX_W_0F3818_P_2,
2347   EVEX_W_0F3819_P_2,
2348   EVEX_W_0F381A_P_2,
2349   EVEX_W_0F381B_P_2,
2350   EVEX_W_0F381E_P_2,
2351   EVEX_W_0F381F_P_2,
2352   EVEX_W_0F3820_P_1,
2353   EVEX_W_0F3821_P_1,
2354   EVEX_W_0F3822_P_1,
2355   EVEX_W_0F3823_P_1,
2356   EVEX_W_0F3824_P_1,
2357   EVEX_W_0F3825_P_1,
2358   EVEX_W_0F3825_P_2,
2359   EVEX_W_0F3826_P_1,
2360   EVEX_W_0F3826_P_2,
2361   EVEX_W_0F3828_P_1,
2362   EVEX_W_0F3828_P_2,
2363   EVEX_W_0F3829_P_1,
2364   EVEX_W_0F3829_P_2,
2365   EVEX_W_0F382A_P_1,
2366   EVEX_W_0F382A_P_2,
2367   EVEX_W_0F382B_P_2,
2368   EVEX_W_0F3830_P_1,
2369   EVEX_W_0F3831_P_1,
2370   EVEX_W_0F3832_P_1,
2371   EVEX_W_0F3833_P_1,
2372   EVEX_W_0F3834_P_1,
2373   EVEX_W_0F3835_P_1,
2374   EVEX_W_0F3835_P_2,
2375   EVEX_W_0F3837_P_2,
2376   EVEX_W_0F3838_P_1,
2377   EVEX_W_0F3839_P_1,
2378   EVEX_W_0F383A_P_1,
2379   EVEX_W_0F3840_P_2,
2380   EVEX_W_0F3858_P_2,
2381   EVEX_W_0F3859_P_2,
2382   EVEX_W_0F385A_P_2,
2383   EVEX_W_0F385B_P_2,
2384   EVEX_W_0F3866_P_2,
2385   EVEX_W_0F3875_P_2,
2386   EVEX_W_0F3878_P_2,
2387   EVEX_W_0F3879_P_2,
2388   EVEX_W_0F387A_P_2,
2389   EVEX_W_0F387B_P_2,
2390   EVEX_W_0F387D_P_2,
2391   EVEX_W_0F3883_P_2,
2392   EVEX_W_0F388D_P_2,
2393   EVEX_W_0F3891_P_2,
2394   EVEX_W_0F3893_P_2,
2395   EVEX_W_0F38A1_P_2,
2396   EVEX_W_0F38A3_P_2,
2397   EVEX_W_0F38C7_R_1_P_2,
2398   EVEX_W_0F38C7_R_2_P_2,
2399   EVEX_W_0F38C7_R_5_P_2,
2400   EVEX_W_0F38C7_R_6_P_2,
2401
2402   EVEX_W_0F3A00_P_2,
2403   EVEX_W_0F3A01_P_2,
2404   EVEX_W_0F3A04_P_2,
2405   EVEX_W_0F3A05_P_2,
2406   EVEX_W_0F3A08_P_2,
2407   EVEX_W_0F3A09_P_2,
2408   EVEX_W_0F3A0A_P_2,
2409   EVEX_W_0F3A0B_P_2,
2410   EVEX_W_0F3A16_P_2,
2411   EVEX_W_0F3A18_P_2,
2412   EVEX_W_0F3A19_P_2,
2413   EVEX_W_0F3A1A_P_2,
2414   EVEX_W_0F3A1B_P_2,
2415   EVEX_W_0F3A1D_P_2,
2416   EVEX_W_0F3A21_P_2,
2417   EVEX_W_0F3A22_P_2,
2418   EVEX_W_0F3A23_P_2,
2419   EVEX_W_0F3A38_P_2,
2420   EVEX_W_0F3A39_P_2,
2421   EVEX_W_0F3A3A_P_2,
2422   EVEX_W_0F3A3B_P_2,
2423   EVEX_W_0F3A3E_P_2,
2424   EVEX_W_0F3A3F_P_2,
2425   EVEX_W_0F3A42_P_2,
2426   EVEX_W_0F3A43_P_2,
2427   EVEX_W_0F3A50_P_2,
2428   EVEX_W_0F3A51_P_2,
2429   EVEX_W_0F3A56_P_2,
2430   EVEX_W_0F3A57_P_2,
2431   EVEX_W_0F3A66_P_2,
2432   EVEX_W_0F3A67_P_2
2433 };
2434
2435 typedef void (*op_rtn) (int bytemode, int sizeflag);
2436
2437 struct dis386 {
2438   const char *name;
2439   struct
2440     {
2441       op_rtn rtn;
2442       int bytemode;
2443     } op[MAX_OPERANDS];
2444   unsigned int prefix_requirement;
2445 };
2446
2447 /* Upper case letters in the instruction names here are macros.
2448    'A' => print 'b' if no register operands or suffix_always is true
2449    'B' => print 'b' if suffix_always is true
2450    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2451           size prefix
2452    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2453           suffix_always is true
2454    'E' => print 'e' if 32-bit form of jcxz
2455    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2456    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2457    'H' => print ",pt" or ",pn" branch hint
2458    'I' => honor following macro letter even in Intel mode (implemented only
2459           for some of the macro letters)
2460    'J' => print 'l'
2461    'K' => print 'd' or 'q' if rex prefix is present.
2462    'L' => print 'l' if suffix_always is true
2463    'M' => print 'r' if intel_mnemonic is false.
2464    'N' => print 'n' if instruction has no wait "prefix"
2465    'O' => print 'd' or 'o' (or 'q' in Intel mode)
2466    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2467           or suffix_always is true.  print 'q' if rex prefix is present.
2468    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2469           is true
2470    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2471    'S' => print 'w', 'l' or 'q' if suffix_always is true
2472    'T' => print 'q' in 64bit mode if instruction has no operand size
2473           prefix and behave as 'P' otherwise
2474    'U' => print 'q' in 64bit mode if instruction has no operand size
2475           prefix and behave as 'Q' otherwise
2476    'V' => print 'q' in 64bit mode if instruction has no operand size
2477           prefix and behave as 'S' otherwise
2478    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2479    'X' => print 's', 'd' depending on data16 prefix (for XMM)
2480    'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
2481           suffix_always is true.
2482    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2483    '!' => change condition from true to false or from false to true.
2484    '%' => add 1 upper case letter to the macro.
2485    '^' => print 'w' or 'l' depending on operand size prefix or
2486           suffix_always is true (lcall/ljmp).
2487    '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2488           on operand size prefix.
2489    '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2490           has no operand size prefix for AMD64 ISA, behave as 'P'
2491           otherwise
2492
2493    2 upper case letter macros:
2494    "XY" => print 'x' or 'y' if suffix_always is true or no register
2495            operands and no broadcast.
2496    "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2497            register operands and no broadcast.
2498    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2499    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2500            or suffix_always is true
2501    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2502    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2503    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2504    "LW" => print 'd', 'q' depending on the VEX.W bit
2505    "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2506            an operand size prefix, or suffix_always is true.  print
2507            'q' if rex prefix is present.
2508
2509    Many of the above letters print nothing in Intel mode.  See "putop"
2510    for the details.
2511
2512    Braces '{' and '}', and vertical bars '|', indicate alternative
2513    mnemonic strings for AT&T and Intel.  */
2514
2515 static const struct dis386 dis386[] = {
2516   /* 00 */
2517   { "addB",             { Ebh1, Gb }, 0 },
2518   { "addS",             { Evh1, Gv }, 0 },
2519   { "addB",             { Gb, EbS }, 0 },
2520   { "addS",             { Gv, EvS }, 0 },
2521   { "addB",             { AL, Ib }, 0 },
2522   { "addS",             { eAX, Iv }, 0 },
2523   { X86_64_TABLE (X86_64_06) },
2524   { X86_64_TABLE (X86_64_07) },
2525   /* 08 */
2526   { "orB",              { Ebh1, Gb }, 0 },
2527   { "orS",              { Evh1, Gv }, 0 },
2528   { "orB",              { Gb, EbS }, 0 },
2529   { "orS",              { Gv, EvS }, 0 },
2530   { "orB",              { AL, Ib }, 0 },
2531   { "orS",              { eAX, Iv }, 0 },
2532   { X86_64_TABLE (X86_64_0D) },
2533   { Bad_Opcode },       /* 0x0f extended opcode escape */
2534   /* 10 */
2535   { "adcB",             { Ebh1, Gb }, 0 },
2536   { "adcS",             { Evh1, Gv }, 0 },
2537   { "adcB",             { Gb, EbS }, 0 },
2538   { "adcS",             { Gv, EvS }, 0 },
2539   { "adcB",             { AL, Ib }, 0 },
2540   { "adcS",             { eAX, Iv }, 0 },
2541   { X86_64_TABLE (X86_64_16) },
2542   { X86_64_TABLE (X86_64_17) },
2543   /* 18 */
2544   { "sbbB",             { Ebh1, Gb }, 0 },
2545   { "sbbS",             { Evh1, Gv }, 0 },
2546   { "sbbB",             { Gb, EbS }, 0 },
2547   { "sbbS",             { Gv, EvS }, 0 },
2548   { "sbbB",             { AL, Ib }, 0 },
2549   { "sbbS",             { eAX, Iv }, 0 },
2550   { X86_64_TABLE (X86_64_1E) },
2551   { X86_64_TABLE (X86_64_1F) },
2552   /* 20 */
2553   { "andB",             { Ebh1, Gb }, 0 },
2554   { "andS",             { Evh1, Gv }, 0 },
2555   { "andB",             { Gb, EbS }, 0 },
2556   { "andS",             { Gv, EvS }, 0 },
2557   { "andB",             { AL, Ib }, 0 },
2558   { "andS",             { eAX, Iv }, 0 },
2559   { Bad_Opcode },       /* SEG ES prefix */
2560   { X86_64_TABLE (X86_64_27) },
2561   /* 28 */
2562   { "subB",             { Ebh1, Gb }, 0 },
2563   { "subS",             { Evh1, Gv }, 0 },
2564   { "subB",             { Gb, EbS }, 0 },
2565   { "subS",             { Gv, EvS }, 0 },
2566   { "subB",             { AL, Ib }, 0 },
2567   { "subS",             { eAX, Iv }, 0 },
2568   { Bad_Opcode },       /* SEG CS prefix */
2569   { X86_64_TABLE (X86_64_2F) },
2570   /* 30 */
2571   { "xorB",             { Ebh1, Gb }, 0 },
2572   { "xorS",             { Evh1, Gv }, 0 },
2573   { "xorB",             { Gb, EbS }, 0 },
2574   { "xorS",             { Gv, EvS }, 0 },
2575   { "xorB",             { AL, Ib }, 0 },
2576   { "xorS",             { eAX, Iv }, 0 },
2577   { Bad_Opcode },       /* SEG SS prefix */
2578   { X86_64_TABLE (X86_64_37) },
2579   /* 38 */
2580   { "cmpB",             { Eb, Gb }, 0 },
2581   { "cmpS",             { Ev, Gv }, 0 },
2582   { "cmpB",             { Gb, EbS }, 0 },
2583   { "cmpS",             { Gv, EvS }, 0 },
2584   { "cmpB",             { AL, Ib }, 0 },
2585   { "cmpS",             { eAX, Iv }, 0 },
2586   { Bad_Opcode },       /* SEG DS prefix */
2587   { X86_64_TABLE (X86_64_3F) },
2588   /* 40 */
2589   { "inc{S|}",          { RMeAX }, 0 },
2590   { "inc{S|}",          { RMeCX }, 0 },
2591   { "inc{S|}",          { RMeDX }, 0 },
2592   { "inc{S|}",          { RMeBX }, 0 },
2593   { "inc{S|}",          { RMeSP }, 0 },
2594   { "inc{S|}",          { RMeBP }, 0 },
2595   { "inc{S|}",          { RMeSI }, 0 },
2596   { "inc{S|}",          { RMeDI }, 0 },
2597   /* 48 */
2598   { "dec{S|}",          { RMeAX }, 0 },
2599   { "dec{S|}",          { RMeCX }, 0 },
2600   { "dec{S|}",          { RMeDX }, 0 },
2601   { "dec{S|}",          { RMeBX }, 0 },
2602   { "dec{S|}",          { RMeSP }, 0 },
2603   { "dec{S|}",          { RMeBP }, 0 },
2604   { "dec{S|}",          { RMeSI }, 0 },
2605   { "dec{S|}",          { RMeDI }, 0 },
2606   /* 50 */
2607   { "pushV",            { RMrAX }, 0 },
2608   { "pushV",            { RMrCX }, 0 },
2609   { "pushV",            { RMrDX }, 0 },
2610   { "pushV",            { RMrBX }, 0 },
2611   { "pushV",            { RMrSP }, 0 },
2612   { "pushV",            { RMrBP }, 0 },
2613   { "pushV",            { RMrSI }, 0 },
2614   { "pushV",            { RMrDI }, 0 },
2615   /* 58 */
2616   { "popV",             { RMrAX }, 0 },
2617   { "popV",             { RMrCX }, 0 },
2618   { "popV",             { RMrDX }, 0 },
2619   { "popV",             { RMrBX }, 0 },
2620   { "popV",             { RMrSP }, 0 },
2621   { "popV",             { RMrBP }, 0 },
2622   { "popV",             { RMrSI }, 0 },
2623   { "popV",             { RMrDI }, 0 },
2624   /* 60 */
2625   { X86_64_TABLE (X86_64_60) },
2626   { X86_64_TABLE (X86_64_61) },
2627   { X86_64_TABLE (X86_64_62) },
2628   { X86_64_TABLE (X86_64_63) },
2629   { Bad_Opcode },       /* seg fs */
2630   { Bad_Opcode },       /* seg gs */
2631   { Bad_Opcode },       /* op size prefix */
2632   { Bad_Opcode },       /* adr size prefix */
2633   /* 68 */
2634   { "pushT",            { sIv }, 0 },
2635   { "imulS",            { Gv, Ev, Iv }, 0 },
2636   { "pushT",            { sIbT }, 0 },
2637   { "imulS",            { Gv, Ev, sIb }, 0 },
2638   { "ins{b|}",          { Ybr, indirDX }, 0 },
2639   { X86_64_TABLE (X86_64_6D) },
2640   { "outs{b|}",         { indirDXr, Xb }, 0 },
2641   { X86_64_TABLE (X86_64_6F) },
2642   /* 70 */
2643   { "joH",              { Jb, BND, cond_jump_flag }, 0 },
2644   { "jnoH",             { Jb, BND, cond_jump_flag }, 0 },
2645   { "jbH",              { Jb, BND, cond_jump_flag }, 0 },
2646   { "jaeH",             { Jb, BND, cond_jump_flag }, 0 },
2647   { "jeH",              { Jb, BND, cond_jump_flag }, 0 },
2648   { "jneH",             { Jb, BND, cond_jump_flag }, 0 },
2649   { "jbeH",             { Jb, BND, cond_jump_flag }, 0 },
2650   { "jaH",              { Jb, BND, cond_jump_flag }, 0 },
2651   /* 78 */
2652   { "jsH",              { Jb, BND, cond_jump_flag }, 0 },
2653   { "jnsH",             { Jb, BND, cond_jump_flag }, 0 },
2654   { "jpH",              { Jb, BND, cond_jump_flag }, 0 },
2655   { "jnpH",             { Jb, BND, cond_jump_flag }, 0 },
2656   { "jlH",              { Jb, BND, cond_jump_flag }, 0 },
2657   { "jgeH",             { Jb, BND, cond_jump_flag }, 0 },
2658   { "jleH",             { Jb, BND, cond_jump_flag }, 0 },
2659   { "jgH",              { Jb, BND, cond_jump_flag }, 0 },
2660   /* 80 */
2661   { REG_TABLE (REG_80) },
2662   { REG_TABLE (REG_81) },
2663   { X86_64_TABLE (X86_64_82) },
2664   { REG_TABLE (REG_83) },
2665   { "testB",            { Eb, Gb }, 0 },
2666   { "testS",            { Ev, Gv }, 0 },
2667   { "xchgB",            { Ebh2, Gb }, 0 },
2668   { "xchgS",            { Evh2, Gv }, 0 },
2669   /* 88 */
2670   { "movB",             { Ebh3, Gb }, 0 },
2671   { "movS",             { Evh3, Gv }, 0 },
2672   { "movB",             { Gb, EbS }, 0 },
2673   { "movS",             { Gv, EvS }, 0 },
2674   { "movD",             { Sv, Sw }, 0 },
2675   { MOD_TABLE (MOD_8D) },
2676   { "movD",             { Sw, Sv }, 0 },
2677   { REG_TABLE (REG_8F) },
2678   /* 90 */
2679   { PREFIX_TABLE (PREFIX_90) },
2680   { "xchgS",            { RMeCX, eAX }, 0 },
2681   { "xchgS",            { RMeDX, eAX }, 0 },
2682   { "xchgS",            { RMeBX, eAX }, 0 },
2683   { "xchgS",            { RMeSP, eAX }, 0 },
2684   { "xchgS",            { RMeBP, eAX }, 0 },
2685   { "xchgS",            { RMeSI, eAX }, 0 },
2686   { "xchgS",            { RMeDI, eAX }, 0 },
2687   /* 98 */
2688   { "cW{t|}R",          { XX }, 0 },
2689   { "cR{t|}O",          { XX }, 0 },
2690   { X86_64_TABLE (X86_64_9A) },
2691   { Bad_Opcode },       /* fwait */
2692   { "pushfT",           { XX }, 0 },
2693   { "popfT",            { XX }, 0 },
2694   { "sahf",             { XX }, 0 },
2695   { "lahf",             { XX }, 0 },
2696   /* a0 */
2697   { "mov%LB",           { AL, Ob }, 0 },
2698   { "mov%LS",           { eAX, Ov }, 0 },
2699   { "mov%LB",           { Ob, AL }, 0 },
2700   { "mov%LS",           { Ov, eAX }, 0 },
2701   { "movs{b|}",         { Ybr, Xb }, 0 },
2702   { "movs{R|}",         { Yvr, Xv }, 0 },
2703   { "cmps{b|}",         { Xb, Yb }, 0 },
2704   { "cmps{R|}",         { Xv, Yv }, 0 },
2705   /* a8 */
2706   { "testB",            { AL, Ib }, 0 },
2707   { "testS",            { eAX, Iv }, 0 },
2708   { "stosB",            { Ybr, AL }, 0 },
2709   { "stosS",            { Yvr, eAX }, 0 },
2710   { "lodsB",            { ALr, Xb }, 0 },
2711   { "lodsS",            { eAXr, Xv }, 0 },
2712   { "scasB",            { AL, Yb }, 0 },
2713   { "scasS",            { eAX, Yv }, 0 },
2714   /* b0 */
2715   { "movB",             { RMAL, Ib }, 0 },
2716   { "movB",             { RMCL, Ib }, 0 },
2717   { "movB",             { RMDL, Ib }, 0 },
2718   { "movB",             { RMBL, Ib }, 0 },
2719   { "movB",             { RMAH, Ib }, 0 },
2720   { "movB",             { RMCH, Ib }, 0 },
2721   { "movB",             { RMDH, Ib }, 0 },
2722   { "movB",             { RMBH, Ib }, 0 },
2723   /* b8 */
2724   { "mov%LV",           { RMeAX, Iv64 }, 0 },
2725   { "mov%LV",           { RMeCX, Iv64 }, 0 },
2726   { "mov%LV",           { RMeDX, Iv64 }, 0 },
2727   { "mov%LV",           { RMeBX, Iv64 }, 0 },
2728   { "mov%LV",           { RMeSP, Iv64 }, 0 },
2729   { "mov%LV",           { RMeBP, Iv64 }, 0 },
2730   { "mov%LV",           { RMeSI, Iv64 }, 0 },
2731   { "mov%LV",           { RMeDI, Iv64 }, 0 },
2732   /* c0 */
2733   { REG_TABLE (REG_C0) },
2734   { REG_TABLE (REG_C1) },
2735   { "retT",             { Iw, BND }, 0 },
2736   { "retT",             { BND }, 0 },
2737   { X86_64_TABLE (X86_64_C4) },
2738   { X86_64_TABLE (X86_64_C5) },
2739   { REG_TABLE (REG_C6) },
2740   { REG_TABLE (REG_C7) },
2741   /* c8 */
2742   { "enterT",           { Iw, Ib }, 0 },
2743   { "leaveT",           { XX }, 0 },
2744   { "Jret{|f}P",        { Iw }, 0 },
2745   { "Jret{|f}P",        { XX }, 0 },
2746   { "int3",             { XX }, 0 },
2747   { "int",              { Ib }, 0 },
2748   { X86_64_TABLE (X86_64_CE) },
2749   { "iret%LP",          { XX }, 0 },
2750   /* d0 */
2751   { REG_TABLE (REG_D0) },
2752   { REG_TABLE (REG_D1) },
2753   { REG_TABLE (REG_D2) },
2754   { REG_TABLE (REG_D3) },
2755   { X86_64_TABLE (X86_64_D4) },
2756   { X86_64_TABLE (X86_64_D5) },
2757   { Bad_Opcode },
2758   { "xlat",             { DSBX }, 0 },
2759   /* d8 */
2760   { FLOAT },
2761   { FLOAT },
2762   { FLOAT },
2763   { FLOAT },
2764   { FLOAT },
2765   { FLOAT },
2766   { FLOAT },
2767   { FLOAT },
2768   /* e0 */
2769   { "loopneFH",         { Jb, XX, loop_jcxz_flag }, 0 },
2770   { "loopeFH",          { Jb, XX, loop_jcxz_flag }, 0 },
2771   { "loopFH",           { Jb, XX, loop_jcxz_flag }, 0 },
2772   { "jEcxzH",           { Jb, XX, loop_jcxz_flag }, 0 },
2773   { "inB",              { AL, Ib }, 0 },
2774   { "inG",              { zAX, Ib }, 0 },
2775   { "outB",             { Ib, AL }, 0 },
2776   { "outG",             { Ib, zAX }, 0 },
2777   /* e8 */
2778   { X86_64_TABLE (X86_64_E8) },
2779   { X86_64_TABLE (X86_64_E9) },
2780   { X86_64_TABLE (X86_64_EA) },
2781   { "jmp",              { Jb, BND }, 0 },
2782   { "inB",              { AL, indirDX }, 0 },
2783   { "inG",              { zAX, indirDX }, 0 },
2784   { "outB",             { indirDX, AL }, 0 },
2785   { "outG",             { indirDX, zAX }, 0 },
2786   /* f0 */
2787   { Bad_Opcode },       /* lock prefix */
2788   { "icebp",            { XX }, 0 },
2789   { Bad_Opcode },       /* repne */
2790   { Bad_Opcode },       /* repz */
2791   { "hlt",              { XX }, 0 },
2792   { "cmc",              { XX }, 0 },
2793   { REG_TABLE (REG_F6) },
2794   { REG_TABLE (REG_F7) },
2795   /* f8 */
2796   { "clc",              { XX }, 0 },
2797   { "stc",              { XX }, 0 },
2798   { "cli",              { XX }, 0 },
2799   { "sti",              { XX }, 0 },
2800   { "cld",              { XX }, 0 },
2801   { "std",              { XX }, 0 },
2802   { REG_TABLE (REG_FE) },
2803   { REG_TABLE (REG_FF) },
2804 };
2805
2806 static const struct dis386 dis386_twobyte[] = {
2807   /* 00 */
2808   { REG_TABLE (REG_0F00 ) },
2809   { REG_TABLE (REG_0F01 ) },
2810   { "larS",             { Gv, Ew }, 0 },
2811   { "lslS",             { Gv, Ew }, 0 },
2812   { Bad_Opcode },
2813   { "syscall",          { XX }, 0 },
2814   { "clts",             { XX }, 0 },
2815   { "sysret%LP",                { XX }, 0 },
2816   /* 08 */
2817   { "invd",             { XX }, 0 },
2818   { "wbinvd",           { XX }, 0 },
2819   { Bad_Opcode },
2820   { "ud2",              { XX }, 0 },
2821   { Bad_Opcode },
2822   { REG_TABLE (REG_0F0D) },
2823   { "femms",            { XX }, 0 },
2824   { "",                 { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix.  */
2825   /* 10 */
2826   { PREFIX_TABLE (PREFIX_0F10) },
2827   { PREFIX_TABLE (PREFIX_0F11) },
2828   { PREFIX_TABLE (PREFIX_0F12) },
2829   { MOD_TABLE (MOD_0F13) },
2830   { "unpcklpX",         { XM, EXx }, PREFIX_OPCODE },
2831   { "unpckhpX",         { XM, EXx }, PREFIX_OPCODE },
2832   { PREFIX_TABLE (PREFIX_0F16) },
2833   { MOD_TABLE (MOD_0F17) },
2834   /* 18 */
2835   { REG_TABLE (REG_0F18) },
2836   { "nopQ",             { Ev }, 0 },
2837   { PREFIX_TABLE (PREFIX_0F1A) },
2838   { PREFIX_TABLE (PREFIX_0F1B) },
2839   { "nopQ",             { Ev }, 0 },
2840   { "nopQ",             { Ev }, 0 },
2841   { "nopQ",             { Ev }, 0 },
2842   { "nopQ",             { Ev }, 0 },
2843   /* 20 */
2844   { "movZ",             { Rm, Cm }, 0 },
2845   { "movZ",             { Rm, Dm }, 0 },
2846   { "movZ",             { Cm, Rm }, 0 },
2847   { "movZ",             { Dm, Rm }, 0 },
2848   { MOD_TABLE (MOD_0F24) },
2849   { Bad_Opcode },
2850   { MOD_TABLE (MOD_0F26) },
2851   { Bad_Opcode },
2852   /* 28 */
2853   { "movapX",           { XM, EXx }, PREFIX_OPCODE },
2854   { "movapX",           { EXxS, XM }, PREFIX_OPCODE },
2855   { PREFIX_TABLE (PREFIX_0F2A) },
2856   { PREFIX_TABLE (PREFIX_0F2B) },
2857   { PREFIX_TABLE (PREFIX_0F2C) },
2858   { PREFIX_TABLE (PREFIX_0F2D) },
2859   { PREFIX_TABLE (PREFIX_0F2E) },
2860   { PREFIX_TABLE (PREFIX_0F2F) },
2861   /* 30 */
2862   { "wrmsr",            { XX }, 0 },
2863   { "rdtsc",            { XX }, 0 },
2864   { "rdmsr",            { XX }, 0 },
2865   { "rdpmc",            { XX }, 0 },
2866   { "sysenter",         { XX }, 0 },
2867   { "sysexit",          { XX }, 0 },
2868   { Bad_Opcode },
2869   { "getsec",           { XX }, 0 },
2870   /* 38 */
2871   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2872   { Bad_Opcode },
2873   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2874   { Bad_Opcode },
2875   { Bad_Opcode },
2876   { Bad_Opcode },
2877   { Bad_Opcode },
2878   { Bad_Opcode },
2879   /* 40 */
2880   { "cmovoS",           { Gv, Ev }, 0 },
2881   { "cmovnoS",          { Gv, Ev }, 0 },
2882   { "cmovbS",           { Gv, Ev }, 0 },
2883   { "cmovaeS",          { Gv, Ev }, 0 },
2884   { "cmoveS",           { Gv, Ev }, 0 },
2885   { "cmovneS",          { Gv, Ev }, 0 },
2886   { "cmovbeS",          { Gv, Ev }, 0 },
2887   { "cmovaS",           { Gv, Ev }, 0 },
2888   /* 48 */
2889   { "cmovsS",           { Gv, Ev }, 0 },
2890   { "cmovnsS",          { Gv, Ev }, 0 },
2891   { "cmovpS",           { Gv, Ev }, 0 },
2892   { "cmovnpS",          { Gv, Ev }, 0 },
2893   { "cmovlS",           { Gv, Ev }, 0 },
2894   { "cmovgeS",          { Gv, Ev }, 0 },
2895   { "cmovleS",          { Gv, Ev }, 0 },
2896   { "cmovgS",           { Gv, Ev }, 0 },
2897   /* 50 */
2898   { MOD_TABLE (MOD_0F51) },
2899   { PREFIX_TABLE (PREFIX_0F51) },
2900   { PREFIX_TABLE (PREFIX_0F52) },
2901   { PREFIX_TABLE (PREFIX_0F53) },
2902   { "andpX",            { XM, EXx }, PREFIX_OPCODE },
2903   { "andnpX",           { XM, EXx }, PREFIX_OPCODE },
2904   { "orpX",             { XM, EXx }, PREFIX_OPCODE },
2905   { "xorpX",            { XM, EXx }, PREFIX_OPCODE },
2906   /* 58 */
2907   { PREFIX_TABLE (PREFIX_0F58) },
2908   { PREFIX_TABLE (PREFIX_0F59) },
2909   { PREFIX_TABLE (PREFIX_0F5A) },
2910   { PREFIX_TABLE (PREFIX_0F5B) },
2911   { PREFIX_TABLE (PREFIX_0F5C) },
2912   { PREFIX_TABLE (PREFIX_0F5D) },
2913   { PREFIX_TABLE (PREFIX_0F5E) },
2914   { PREFIX_TABLE (PREFIX_0F5F) },
2915   /* 60 */
2916   { PREFIX_TABLE (PREFIX_0F60) },
2917   { PREFIX_TABLE (PREFIX_0F61) },
2918   { PREFIX_TABLE (PREFIX_0F62) },
2919   { "packsswb",         { MX, EM }, PREFIX_OPCODE },
2920   { "pcmpgtb",          { MX, EM }, PREFIX_OPCODE },
2921   { "pcmpgtw",          { MX, EM }, PREFIX_OPCODE },
2922   { "pcmpgtd",          { MX, EM }, PREFIX_OPCODE },
2923   { "packuswb",         { MX, EM }, PREFIX_OPCODE },
2924   /* 68 */
2925   { "punpckhbw",        { MX, EM }, PREFIX_OPCODE },
2926   { "punpckhwd",        { MX, EM }, PREFIX_OPCODE },
2927   { "punpckhdq",        { MX, EM }, PREFIX_OPCODE },
2928   { "packssdw",         { MX, EM }, PREFIX_OPCODE },
2929   { PREFIX_TABLE (PREFIX_0F6C) },
2930   { PREFIX_TABLE (PREFIX_0F6D) },
2931   { "movK",             { MX, Edq }, PREFIX_OPCODE },
2932   { PREFIX_TABLE (PREFIX_0F6F) },
2933   /* 70 */
2934   { PREFIX_TABLE (PREFIX_0F70) },
2935   { REG_TABLE (REG_0F71) },
2936   { REG_TABLE (REG_0F72) },
2937   { REG_TABLE (REG_0F73) },
2938   { "pcmpeqb",          { MX, EM }, PREFIX_OPCODE },
2939   { "pcmpeqw",          { MX, EM }, PREFIX_OPCODE },
2940   { "pcmpeqd",          { MX, EM }, PREFIX_OPCODE },
2941   { "emms",             { XX }, PREFIX_OPCODE },
2942   /* 78 */
2943   { PREFIX_TABLE (PREFIX_0F78) },
2944   { PREFIX_TABLE (PREFIX_0F79) },
2945   { Bad_Opcode },
2946   { Bad_Opcode },
2947   { PREFIX_TABLE (PREFIX_0F7C) },
2948   { PREFIX_TABLE (PREFIX_0F7D) },
2949   { PREFIX_TABLE (PREFIX_0F7E) },
2950   { PREFIX_TABLE (PREFIX_0F7F) },
2951   /* 80 */
2952   { "joH",              { Jv, BND, cond_jump_flag }, 0 },
2953   { "jnoH",             { Jv, BND, cond_jump_flag }, 0 },
2954   { "jbH",              { Jv, BND, cond_jump_flag }, 0 },
2955   { "jaeH",             { Jv, BND, cond_jump_flag }, 0 },
2956   { "jeH",              { Jv, BND, cond_jump_flag }, 0 },
2957   { "jneH",             { Jv, BND, cond_jump_flag }, 0 },
2958   { "jbeH",             { Jv, BND, cond_jump_flag }, 0 },
2959   { "jaH",              { Jv, BND, cond_jump_flag }, 0 },
2960   /* 88 */
2961   { "jsH",              { Jv, BND, cond_jump_flag }, 0 },
2962   { "jnsH",             { Jv, BND, cond_jump_flag }, 0 },
2963   { "jpH",              { Jv, BND, cond_jump_flag }, 0 },
2964   { "jnpH",             { Jv, BND, cond_jump_flag }, 0 },
2965   { "jlH",              { Jv, BND, cond_jump_flag }, 0 },
2966   { "jgeH",             { Jv, BND, cond_jump_flag }, 0 },
2967   { "jleH",             { Jv, BND, cond_jump_flag }, 0 },
2968   { "jgH",              { Jv, BND, cond_jump_flag }, 0 },
2969   /* 90 */
2970   { "seto",             { Eb }, 0 },
2971   { "setno",            { Eb }, 0 },
2972   { "setb",             { Eb }, 0 },
2973   { "setae",            { Eb }, 0 },
2974   { "sete",             { Eb }, 0 },
2975   { "setne",            { Eb }, 0 },
2976   { "setbe",            { Eb }, 0 },
2977   { "seta",             { Eb }, 0 },
2978   /* 98 */
2979   { "sets",             { Eb }, 0 },
2980   { "setns",            { Eb }, 0 },
2981   { "setp",             { Eb }, 0 },
2982   { "setnp",            { Eb }, 0 },
2983   { "setl",             { Eb }, 0 },
2984   { "setge",            { Eb }, 0 },
2985   { "setle",            { Eb }, 0 },
2986   { "setg",             { Eb }, 0 },
2987   /* a0 */
2988   { "pushT",            { fs }, 0 },
2989   { "popT",             { fs }, 0 },
2990   { "cpuid",            { XX }, 0 },
2991   { "btS",              { Ev, Gv }, 0 },
2992   { "shldS",            { Ev, Gv, Ib }, 0 },
2993   { "shldS",            { Ev, Gv, CL }, 0 },
2994   { REG_TABLE (REG_0FA6) },
2995   { REG_TABLE (REG_0FA7) },
2996   /* a8 */
2997   { "pushT",            { gs }, 0 },
2998   { "popT",             { gs }, 0 },
2999   { "rsm",              { XX }, 0 },
3000   { "btsS",             { Evh1, Gv }, 0 },
3001   { "shrdS",            { Ev, Gv, Ib }, 0 },
3002   { "shrdS",            { Ev, Gv, CL }, 0 },
3003   { REG_TABLE (REG_0FAE) },
3004   { "imulS",            { Gv, Ev }, 0 },
3005   /* b0 */
3006   { "cmpxchgB",         { Ebh1, Gb }, 0 },
3007   { "cmpxchgS",         { Evh1, Gv }, 0 },
3008   { MOD_TABLE (MOD_0FB2) },
3009   { "btrS",             { Evh1, Gv }, 0 },
3010   { MOD_TABLE (MOD_0FB4) },
3011   { MOD_TABLE (MOD_0FB5) },
3012   { "movz{bR|x}",       { Gv, Eb }, 0 },
3013   { "movz{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
3014   /* b8 */
3015   { PREFIX_TABLE (PREFIX_0FB8) },
3016   { "ud1",              { XX }, 0 },
3017   { REG_TABLE (REG_0FBA) },
3018   { "btcS",             { Evh1, Gv }, 0 },
3019   { PREFIX_TABLE (PREFIX_0FBC) },
3020   { PREFIX_TABLE (PREFIX_0FBD) },
3021   { "movs{bR|x}",       { Gv, Eb }, 0 },
3022   { "movs{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
3023   /* c0 */
3024   { "xaddB",            { Ebh1, Gb }, 0 },
3025   { "xaddS",            { Evh1, Gv }, 0 },
3026   { PREFIX_TABLE (PREFIX_0FC2) },
3027   { MOD_TABLE (MOD_0FC3) },
3028   { "pinsrw",           { MX, Edqw, Ib }, PREFIX_OPCODE },
3029   { "pextrw",           { Gdq, MS, Ib }, PREFIX_OPCODE },
3030   { "shufpX",           { XM, EXx, Ib }, PREFIX_OPCODE },
3031   { REG_TABLE (REG_0FC7) },
3032   /* c8 */
3033   { "bswap",            { RMeAX }, 0 },
3034   { "bswap",            { RMeCX }, 0 },
3035   { "bswap",            { RMeDX }, 0 },
3036   { "bswap",            { RMeBX }, 0 },
3037   { "bswap",            { RMeSP }, 0 },
3038   { "bswap",            { RMeBP }, 0 },
3039   { "bswap",            { RMeSI }, 0 },
3040   { "bswap",            { RMeDI }, 0 },
3041   /* d0 */
3042   { PREFIX_TABLE (PREFIX_0FD0) },
3043   { "psrlw",            { MX, EM }, PREFIX_OPCODE },
3044   { "psrld",            { MX, EM }, PREFIX_OPCODE },
3045   { "psrlq",            { MX, EM }, PREFIX_OPCODE },
3046   { "paddq",            { MX, EM }, PREFIX_OPCODE },
3047   { "pmullw",           { MX, EM }, PREFIX_OPCODE },
3048   { PREFIX_TABLE (PREFIX_0FD6) },
3049   { MOD_TABLE (MOD_0FD7) },
3050   /* d8 */
3051   { "psubusb",          { MX, EM }, PREFIX_OPCODE },
3052   { "psubusw",          { MX, EM }, PREFIX_OPCODE },
3053   { "pminub",           { MX, EM }, PREFIX_OPCODE },
3054   { "pand",             { MX, EM }, PREFIX_OPCODE },
3055   { "paddusb",          { MX, EM }, PREFIX_OPCODE },
3056   { "paddusw",          { MX, EM }, PREFIX_OPCODE },
3057   { "pmaxub",           { MX, EM }, PREFIX_OPCODE },
3058   { "pandn",            { MX, EM }, PREFIX_OPCODE },
3059   /* e0 */
3060   { "pavgb",            { MX, EM }, PREFIX_OPCODE },
3061   { "psraw",            { MX, EM }, PREFIX_OPCODE },
3062   { "psrad",            { MX, EM }, PREFIX_OPCODE },
3063   { "pavgw",            { MX, EM }, PREFIX_OPCODE },
3064   { "pmulhuw",          { MX, EM }, PREFIX_OPCODE },
3065   { "pmulhw",           { MX, EM }, PREFIX_OPCODE },
3066   { PREFIX_TABLE (PREFIX_0FE6) },
3067   { PREFIX_TABLE (PREFIX_0FE7) },
3068   /* e8 */
3069   { "psubsb",           { MX, EM }, PREFIX_OPCODE },
3070   { "psubsw",           { MX, EM }, PREFIX_OPCODE },
3071   { "pminsw",           { MX, EM }, PREFIX_OPCODE },
3072   { "por",              { MX, EM }, PREFIX_OPCODE },
3073   { "paddsb",           { MX, EM }, PREFIX_OPCODE },
3074   { "paddsw",           { MX, EM }, PREFIX_OPCODE },
3075   { "pmaxsw",           { MX, EM }, PREFIX_OPCODE },
3076   { "pxor",             { MX, EM }, PREFIX_OPCODE },
3077   /* f0 */
3078   { PREFIX_TABLE (PREFIX_0FF0) },
3079   { "psllw",            { MX, EM }, PREFIX_OPCODE },
3080   { "pslld",            { MX, EM }, PREFIX_OPCODE },
3081   { "psllq",            { MX, EM }, PREFIX_OPCODE },
3082   { "pmuludq",          { MX, EM }, PREFIX_OPCODE },
3083   { "pmaddwd",          { MX, EM }, PREFIX_OPCODE },
3084   { "psadbw",           { MX, EM }, PREFIX_OPCODE },
3085   { PREFIX_TABLE (PREFIX_0FF7) },
3086   /* f8 */
3087   { "psubb",            { MX, EM }, PREFIX_OPCODE },
3088   { "psubw",            { MX, EM }, PREFIX_OPCODE },
3089   { "psubd",            { MX, EM }, PREFIX_OPCODE },
3090   { "psubq",            { MX, EM }, PREFIX_OPCODE },
3091   { "paddb",            { MX, EM }, PREFIX_OPCODE },
3092   { "paddw",            { MX, EM }, PREFIX_OPCODE },
3093   { "paddd",            { MX, EM }, PREFIX_OPCODE },
3094   { Bad_Opcode },
3095 };
3096
3097 static const unsigned char onebyte_has_modrm[256] = {
3098   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3099   /*       -------------------------------        */
3100   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
3101   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
3102   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
3103   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
3104   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
3105   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
3106   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
3107   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
3108   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
3109   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
3110   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
3111   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
3112   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
3113   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
3114   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
3115   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
3116   /*       -------------------------------        */
3117   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3118 };
3119
3120 static const unsigned char twobyte_has_modrm[256] = {
3121   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3122   /*       -------------------------------        */
3123   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
3124   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
3125   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
3126   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
3127   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
3128   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
3129   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
3130   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
3131   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
3132   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
3133   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
3134   /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
3135   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
3136   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
3137   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
3138   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0  /* ff */
3139   /*       -------------------------------        */
3140   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3141 };
3142
3143 static char obuf[100];
3144 static char *obufp;
3145 static char *mnemonicendp;
3146 static char scratchbuf[100];
3147 static unsigned char *start_codep;
3148 static unsigned char *insn_codep;
3149 static unsigned char *codep;
3150 static unsigned char *end_codep;
3151 static int last_lock_prefix;
3152 static int last_repz_prefix;
3153 static int last_repnz_prefix;
3154 static int last_data_prefix;
3155 static int last_addr_prefix;
3156 static int last_rex_prefix;
3157 static int last_seg_prefix;
3158 static int fwait_prefix;
3159 /* The active segment register prefix.  */
3160 static int active_seg_prefix;
3161 #define MAX_CODE_LENGTH 15
3162 /* We can up to 14 prefixes since the maximum instruction length is
3163    15bytes.  */
3164 static int all_prefixes[MAX_CODE_LENGTH - 1];
3165 static disassemble_info *the_info;
3166 static struct
3167   {
3168     int mod;
3169     int reg;
3170     int rm;
3171   }
3172 modrm;
3173 static unsigned char need_modrm;
3174 static struct
3175   {
3176     int scale;
3177     int index;
3178     int base;
3179   }
3180 sib;
3181 static struct
3182   {
3183     int register_specifier;
3184     int length;
3185     int prefix;
3186     int w;
3187     int evex;
3188     int r;
3189     int v;
3190     int mask_register_specifier;
3191     int zeroing;
3192     int ll;
3193     int b;
3194   }
3195 vex;
3196 static unsigned char need_vex;
3197 static unsigned char need_vex_reg;
3198 static unsigned char vex_w_done;
3199
3200 struct op
3201   {
3202     const char *name;
3203     unsigned int len;
3204   };
3205
3206 /* If we are accessing mod/rm/reg without need_modrm set, then the
3207    values are stale.  Hitting this abort likely indicates that you
3208    need to update onebyte_has_modrm or twobyte_has_modrm.  */
3209 #define MODRM_CHECK  if (!need_modrm) abort ()
3210
3211 static const char **names64;
3212 static const char **names32;
3213 static const char **names16;
3214 static const char **names8;
3215 static const char **names8rex;
3216 static const char **names_seg;
3217 static const char *index64;
3218 static const char *index32;
3219 static const char **index16;
3220 static const char **names_bnd;
3221
3222 static const char *intel_names64[] = {
3223   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3224   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3225 };
3226 static const char *intel_names32[] = {
3227   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3228   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3229 };
3230 static const char *intel_names16[] = {
3231   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3232   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3233 };
3234 static const char *intel_names8[] = {
3235   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3236 };
3237 static const char *intel_names8rex[] = {
3238   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3239   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3240 };
3241 static const char *intel_names_seg[] = {
3242   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3243 };
3244 static const char *intel_index64 = "riz";
3245 static const char *intel_index32 = "eiz";
3246 static const char *intel_index16[] = {
3247   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3248 };
3249
3250 static const char *att_names64[] = {
3251   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3252   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3253 };
3254 static const char *att_names32[] = {
3255   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3256   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3257 };
3258 static const char *att_names16[] = {
3259   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3260   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3261 };
3262 static const char *att_names8[] = {
3263   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3264 };
3265 static const char *att_names8rex[] = {
3266   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3267   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3268 };
3269 static const char *att_names_seg[] = {
3270   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3271 };
3272 static const char *att_index64 = "%riz";
3273 static const char *att_index32 = "%eiz";
3274 static const char *att_index16[] = {
3275   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3276 };
3277
3278 static const char **names_mm;
3279 static const char *intel_names_mm[] = {
3280   "mm0", "mm1", "mm2", "mm3",
3281   "mm4", "mm5", "mm6", "mm7"
3282 };
3283 static const char *att_names_mm[] = {
3284   "%mm0", "%mm1", "%mm2", "%mm3",
3285   "%mm4", "%mm5", "%mm6", "%mm7"
3286 };
3287
3288 static const char *intel_names_bnd[] = {
3289   "bnd0", "bnd1", "bnd2", "bnd3"
3290 };
3291
3292 static const char *att_names_bnd[] = {
3293   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3294 };
3295
3296 static const char **names_xmm;
3297 static const char *intel_names_xmm[] = {
3298   "xmm0", "xmm1", "xmm2", "xmm3",
3299   "xmm4", "xmm5", "xmm6", "xmm7",
3300   "xmm8", "xmm9", "xmm10", "xmm11",
3301   "xmm12", "xmm13", "xmm14", "xmm15",
3302   "xmm16", "xmm17", "xmm18", "xmm19",
3303   "xmm20", "xmm21", "xmm22", "xmm23",
3304   "xmm24", "xmm25", "xmm26", "xmm27",
3305   "xmm28", "xmm29", "xmm30", "xmm31"
3306 };
3307 static const char *att_names_xmm[] = {
3308   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3309   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3310   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3311   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3312   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3313   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3314   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3315   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3316 };
3317
3318 static const char **names_ymm;
3319 static const char *intel_names_ymm[] = {
3320   "ymm0", "ymm1", "ymm2", "ymm3",
3321   "ymm4", "ymm5", "ymm6", "ymm7",
3322   "ymm8", "ymm9", "ymm10", "ymm11",
3323   "ymm12", "ymm13", "ymm14", "ymm15",
3324   "ymm16", "ymm17", "ymm18", "ymm19",
3325   "ymm20", "ymm21", "ymm22", "ymm23",
3326   "ymm24", "ymm25", "ymm26", "ymm27",
3327   "ymm28", "ymm29", "ymm30", "ymm31"
3328 };
3329 static const char *att_names_ymm[] = {
3330   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3331   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3332   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3333   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3334   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3335   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3336   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3337   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3338 };
3339
3340 static const char **names_zmm;
3341 static const char *intel_names_zmm[] = {
3342   "zmm0", "zmm1", "zmm2", "zmm3",
3343   "zmm4", "zmm5", "zmm6", "zmm7",
3344   "zmm8", "zmm9", "zmm10", "zmm11",
3345   "zmm12", "zmm13", "zmm14", "zmm15",
3346   "zmm16", "zmm17", "zmm18", "zmm19",
3347   "zmm20", "zmm21", "zmm22", "zmm23",
3348   "zmm24", "zmm25", "zmm26", "zmm27",
3349   "zmm28", "zmm29", "zmm30", "zmm31"
3350 };
3351 static const char *att_names_zmm[] = {
3352   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3353   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3354   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3355   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3356   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3357   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3358   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3359   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3360 };
3361
3362 static const char **names_mask;
3363 static const char *intel_names_mask[] = {
3364   "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3365 };
3366 static const char *att_names_mask[] = {
3367   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3368 };
3369
3370 static const char *names_rounding[] =
3371 {
3372   "{rn-sae}",
3373   "{rd-sae}",
3374   "{ru-sae}",
3375   "{rz-sae}"
3376 };
3377
3378 static const struct dis386 reg_table[][8] = {
3379   /* REG_80 */
3380   {
3381     { "addA",   { Ebh1, Ib }, 0 },
3382     { "orA",    { Ebh1, Ib }, 0 },
3383     { "adcA",   { Ebh1, Ib }, 0 },
3384     { "sbbA",   { Ebh1, Ib }, 0 },
3385     { "andA",   { Ebh1, Ib }, 0 },
3386     { "subA",   { Ebh1, Ib }, 0 },
3387     { "xorA",   { Ebh1, Ib }, 0 },
3388     { "cmpA",   { Eb, Ib }, 0 },
3389   },
3390   /* REG_81 */
3391   {
3392     { "addQ",   { Evh1, Iv }, 0 },
3393     { "orQ",    { Evh1, Iv }, 0 },
3394     { "adcQ",   { Evh1, Iv }, 0 },
3395     { "sbbQ",   { Evh1, Iv }, 0 },
3396     { "andQ",   { Evh1, Iv }, 0 },
3397     { "subQ",   { Evh1, Iv }, 0 },
3398     { "xorQ",   { Evh1, Iv }, 0 },
3399     { "cmpQ",   { Ev, Iv }, 0 },
3400   },
3401   /* REG_83 */
3402   {
3403     { "addQ",   { Evh1, sIb }, 0 },
3404     { "orQ",    { Evh1, sIb }, 0 },
3405     { "adcQ",   { Evh1, sIb }, 0 },
3406     { "sbbQ",   { Evh1, sIb }, 0 },
3407     { "andQ",   { Evh1, sIb }, 0 },
3408     { "subQ",   { Evh1, sIb }, 0 },
3409     { "xorQ",   { Evh1, sIb }, 0 },
3410     { "cmpQ",   { Ev, sIb }, 0 },
3411   },
3412   /* REG_8F */
3413   {
3414     { "popU",   { stackEv }, 0 },
3415     { XOP_8F_TABLE (XOP_09) },
3416     { Bad_Opcode },
3417     { Bad_Opcode },
3418     { Bad_Opcode },
3419     { XOP_8F_TABLE (XOP_09) },
3420   },
3421   /* REG_C0 */
3422   {
3423     { "rolA",   { Eb, Ib }, 0 },
3424     { "rorA",   { Eb, Ib }, 0 },
3425     { "rclA",   { Eb, Ib }, 0 },
3426     { "rcrA",   { Eb, Ib }, 0 },
3427     { "shlA",   { Eb, Ib }, 0 },
3428     { "shrA",   { Eb, Ib }, 0 },
3429     { Bad_Opcode },
3430     { "sarA",   { Eb, Ib }, 0 },
3431   },
3432   /* REG_C1 */
3433   {
3434     { "rolQ",   { Ev, Ib }, 0 },
3435     { "rorQ",   { Ev, Ib }, 0 },
3436     { "rclQ",   { Ev, Ib }, 0 },
3437     { "rcrQ",   { Ev, Ib }, 0 },
3438     { "shlQ",   { Ev, Ib }, 0 },
3439     { "shrQ",   { Ev, Ib }, 0 },
3440     { Bad_Opcode },
3441     { "sarQ",   { Ev, Ib }, 0 },
3442   },
3443   /* REG_C6 */
3444   {
3445     { "movA",   { Ebh3, Ib }, 0 },
3446     { Bad_Opcode },
3447     { Bad_Opcode },
3448     { Bad_Opcode },
3449     { Bad_Opcode },
3450     { Bad_Opcode },
3451     { Bad_Opcode },
3452     { MOD_TABLE (MOD_C6_REG_7) },
3453   },
3454   /* REG_C7 */
3455   {
3456     { "movQ",   { Evh3, Iv }, 0 },
3457     { Bad_Opcode },
3458     { Bad_Opcode },
3459     { Bad_Opcode },
3460     { Bad_Opcode },
3461     { Bad_Opcode },
3462     { Bad_Opcode },
3463     { MOD_TABLE (MOD_C7_REG_7) },
3464   },
3465   /* REG_D0 */
3466   {
3467     { "rolA",   { Eb, I1 }, 0 },
3468     { "rorA",   { Eb, I1 }, 0 },
3469     { "rclA",   { Eb, I1 }, 0 },
3470     { "rcrA",   { Eb, I1 }, 0 },
3471     { "shlA",   { Eb, I1 }, 0 },
3472     { "shrA",   { Eb, I1 }, 0 },
3473     { Bad_Opcode },
3474     { "sarA",   { Eb, I1 }, 0 },
3475   },
3476   /* REG_D1 */
3477   {
3478     { "rolQ",   { Ev, I1 }, 0 },
3479     { "rorQ",   { Ev, I1 }, 0 },
3480     { "rclQ",   { Ev, I1 }, 0 },
3481     { "rcrQ",   { Ev, I1 }, 0 },
3482     { "shlQ",   { Ev, I1 }, 0 },
3483     { "shrQ",   { Ev, I1 }, 0 },
3484     { Bad_Opcode },
3485     { "sarQ",   { Ev, I1 }, 0 },
3486   },
3487   /* REG_D2 */
3488   {
3489     { "rolA",   { Eb, CL }, 0 },
3490     { "rorA",   { Eb, CL }, 0 },
3491     { "rclA",   { Eb, CL }, 0 },
3492     { "rcrA",   { Eb, CL }, 0 },
3493     { "shlA",   { Eb, CL }, 0 },
3494     { "shrA",   { Eb, CL }, 0 },
3495     { Bad_Opcode },
3496     { "sarA",   { Eb, CL }, 0 },
3497   },
3498   /* REG_D3 */
3499   {
3500     { "rolQ",   { Ev, CL }, 0 },
3501     { "rorQ",   { Ev, CL }, 0 },
3502     { "rclQ",   { Ev, CL }, 0 },
3503     { "rcrQ",   { Ev, CL }, 0 },
3504     { "shlQ",   { Ev, CL }, 0 },
3505     { "shrQ",   { Ev, CL }, 0 },
3506     { Bad_Opcode },
3507     { "sarQ",   { Ev, CL }, 0 },
3508   },
3509   /* REG_F6 */
3510   {
3511     { "testA",  { Eb, Ib }, 0 },
3512     { Bad_Opcode },
3513     { "notA",   { Ebh1 }, 0 },
3514     { "negA",   { Ebh1 }, 0 },
3515     { "mulA",   { Eb }, 0 },    /* Don't print the implicit %al register,  */
3516     { "imulA",  { Eb }, 0 },    /* to distinguish these opcodes from other */
3517     { "divA",   { Eb }, 0 },    /* mul/imul opcodes.  Do the same for div  */
3518     { "idivA",  { Eb }, 0 },    /* and idiv for consistency.               */
3519   },
3520   /* REG_F7 */
3521   {
3522     { "testQ",  { Ev, Iv }, 0 },
3523     { Bad_Opcode },
3524     { "notQ",   { Evh1 }, 0 },
3525     { "negQ",   { Evh1 }, 0 },
3526     { "mulQ",   { Ev }, 0 },    /* Don't print the implicit register.  */
3527     { "imulQ",  { Ev }, 0 },
3528     { "divQ",   { Ev }, 0 },
3529     { "idivQ",  { Ev }, 0 },
3530   },
3531   /* REG_FE */
3532   {
3533     { "incA",   { Ebh1 }, 0 },
3534     { "decA",   { Ebh1 }, 0 },
3535   },
3536   /* REG_FF */
3537   {
3538     { "incQ",   { Evh1 }, 0 },
3539     { "decQ",   { Evh1 }, 0 },
3540     { "call{&|}", { indirEv, BND }, 0 },
3541     { MOD_TABLE (MOD_FF_REG_3) },
3542     { "jmp{&|}", { indirEv, BND }, 0 },
3543     { MOD_TABLE (MOD_FF_REG_5) },
3544     { "pushU",  { stackEv }, 0 },
3545     { Bad_Opcode },
3546   },
3547   /* REG_0F00 */
3548   {
3549     { "sldtD",  { Sv }, 0 },
3550     { "strD",   { Sv }, 0 },
3551     { "lldt",   { Ew }, 0 },
3552     { "ltr",    { Ew }, 0 },
3553     { "verr",   { Ew }, 0 },
3554     { "verw",   { Ew }, 0 },
3555     { Bad_Opcode },
3556     { Bad_Opcode },
3557   },
3558   /* REG_0F01 */
3559   {
3560     { MOD_TABLE (MOD_0F01_REG_0) },
3561     { MOD_TABLE (MOD_0F01_REG_1) },
3562     { MOD_TABLE (MOD_0F01_REG_2) },
3563     { MOD_TABLE (MOD_0F01_REG_3) },
3564     { "smswD",  { Sv }, 0 },
3565     { MOD_TABLE (MOD_0F01_REG_5) },
3566     { "lmsw",   { Ew }, 0 },
3567     { MOD_TABLE (MOD_0F01_REG_7) },
3568   },
3569   /* REG_0F0D */
3570   {
3571     { "prefetch",       { Mb }, 0 },
3572     { "prefetchw",      { Mb }, 0 },
3573     { "prefetchwt1",    { Mb }, 0 },
3574     { "prefetch",       { Mb }, 0 },
3575     { "prefetch",       { Mb }, 0 },
3576     { "prefetch",       { Mb }, 0 },
3577     { "prefetch",       { Mb }, 0 },
3578     { "prefetch",       { Mb }, 0 },
3579   },
3580   /* REG_0F18 */
3581   {
3582     { MOD_TABLE (MOD_0F18_REG_0) },
3583     { MOD_TABLE (MOD_0F18_REG_1) },
3584     { MOD_TABLE (MOD_0F18_REG_2) },
3585     { MOD_TABLE (MOD_0F18_REG_3) },
3586     { MOD_TABLE (MOD_0F18_REG_4) },
3587     { MOD_TABLE (MOD_0F18_REG_5) },
3588     { MOD_TABLE (MOD_0F18_REG_6) },
3589     { MOD_TABLE (MOD_0F18_REG_7) },
3590   },
3591   /* REG_0F71 */
3592   {
3593     { Bad_Opcode },
3594     { Bad_Opcode },
3595     { MOD_TABLE (MOD_0F71_REG_2) },
3596     { Bad_Opcode },
3597     { MOD_TABLE (MOD_0F71_REG_4) },
3598     { Bad_Opcode },
3599     { MOD_TABLE (MOD_0F71_REG_6) },
3600   },
3601   /* REG_0F72 */
3602   {
3603     { Bad_Opcode },
3604     { Bad_Opcode },
3605     { MOD_TABLE (MOD_0F72_REG_2) },
3606     { Bad_Opcode },
3607     { MOD_TABLE (MOD_0F72_REG_4) },
3608     { Bad_Opcode },
3609     { MOD_TABLE (MOD_0F72_REG_6) },
3610   },
3611   /* REG_0F73 */
3612   {
3613     { Bad_Opcode },
3614     { Bad_Opcode },
3615     { MOD_TABLE (MOD_0F73_REG_2) },
3616     { MOD_TABLE (MOD_0F73_REG_3) },
3617     { Bad_Opcode },
3618     { Bad_Opcode },
3619     { MOD_TABLE (MOD_0F73_REG_6) },
3620     { MOD_TABLE (MOD_0F73_REG_7) },
3621   },
3622   /* REG_0FA6 */
3623   {
3624     { "montmul",        { { OP_0f07, 0 } }, 0 },
3625     { "xsha1",          { { OP_0f07, 0 } }, 0 },
3626     { "xsha256",        { { OP_0f07, 0 } }, 0 },
3627   },
3628   /* REG_0FA7 */
3629   {
3630     { "xstore-rng",     { { OP_0f07, 0 } }, 0 },
3631     { "xcrypt-ecb",     { { OP_0f07, 0 } }, 0 },
3632     { "xcrypt-cbc",     { { OP_0f07, 0 } }, 0 },
3633     { "xcrypt-ctr",     { { OP_0f07, 0 } }, 0 },
3634     { "xcrypt-cfb",     { { OP_0f07, 0 } }, 0 },
3635     { "xcrypt-ofb",     { { OP_0f07, 0 } }, 0 },
3636   },
3637   /* REG_0FAE */
3638   {
3639     { MOD_TABLE (MOD_0FAE_REG_0) },
3640     { MOD_TABLE (MOD_0FAE_REG_1) },
3641     { MOD_TABLE (MOD_0FAE_REG_2) },
3642     { MOD_TABLE (MOD_0FAE_REG_3) },
3643     { MOD_TABLE (MOD_0FAE_REG_4) },
3644     { MOD_TABLE (MOD_0FAE_REG_5) },
3645     { MOD_TABLE (MOD_0FAE_REG_6) },
3646     { MOD_TABLE (MOD_0FAE_REG_7) },
3647   },
3648   /* REG_0FBA */
3649   {
3650     { Bad_Opcode },
3651     { Bad_Opcode },
3652     { Bad_Opcode },
3653     { Bad_Opcode },
3654     { "btQ",    { Ev, Ib }, 0 },
3655     { "btsQ",   { Evh1, Ib }, 0 },
3656     { "btrQ",   { Evh1, Ib }, 0 },
3657     { "btcQ",   { Evh1, Ib }, 0 },
3658   },
3659   /* REG_0FC7 */
3660   {
3661     { Bad_Opcode },
3662     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
3663     { Bad_Opcode },
3664     { MOD_TABLE (MOD_0FC7_REG_3) },
3665     { MOD_TABLE (MOD_0FC7_REG_4) },
3666     { MOD_TABLE (MOD_0FC7_REG_5) },
3667     { MOD_TABLE (MOD_0FC7_REG_6) },
3668     { MOD_TABLE (MOD_0FC7_REG_7) },
3669   },
3670   /* REG_VEX_0F71 */
3671   {
3672     { Bad_Opcode },
3673     { Bad_Opcode },
3674     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3675     { Bad_Opcode },
3676     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3677     { Bad_Opcode },
3678     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3679   },
3680   /* REG_VEX_0F72 */
3681   {
3682     { Bad_Opcode },
3683     { Bad_Opcode },
3684     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3685     { Bad_Opcode },
3686     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3687     { Bad_Opcode },
3688     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3689   },
3690   /* REG_VEX_0F73 */
3691   {
3692     { Bad_Opcode },
3693     { Bad_Opcode },
3694     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3695     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3696     { Bad_Opcode },
3697     { Bad_Opcode },
3698     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3699     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3700   },
3701   /* REG_VEX_0FAE */
3702   {
3703     { Bad_Opcode },
3704     { Bad_Opcode },
3705     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3706     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3707   },
3708   /* REG_VEX_0F38F3 */
3709   {
3710     { Bad_Opcode },
3711     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3712     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3713     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3714   },
3715   /* REG_XOP_LWPCB */
3716   {
3717     { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3718     { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3719   },
3720   /* REG_XOP_LWP */
3721   {
3722     { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3723     { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3724   },
3725   /* REG_XOP_TBM_01 */
3726   {
3727     { Bad_Opcode },
3728     { "blcfill",        { { OP_LWP_E, 0 }, Ev }, 0 },
3729     { "blsfill",        { { OP_LWP_E, 0 }, Ev }, 0 },
3730     { "blcs",   { { OP_LWP_E, 0 }, Ev }, 0 },
3731     { "tzmsk",  { { OP_LWP_E, 0 }, Ev }, 0 },
3732     { "blcic",  { { OP_LWP_E, 0 }, Ev }, 0 },
3733     { "blsic",  { { OP_LWP_E, 0 }, Ev }, 0 },
3734     { "t1mskc", { { OP_LWP_E, 0 }, Ev }, 0 },
3735   },
3736   /* REG_XOP_TBM_02 */
3737   {
3738     { Bad_Opcode },
3739     { "blcmsk", { { OP_LWP_E, 0 }, Ev }, 0 },
3740     { Bad_Opcode },
3741     { Bad_Opcode },
3742     { Bad_Opcode },
3743     { Bad_Opcode },
3744     { "blci",   { { OP_LWP_E, 0 }, Ev }, 0 },
3745   },
3746 #define NEED_REG_TABLE
3747 #include "i386-dis-evex.h"
3748 #undef NEED_REG_TABLE
3749 };
3750
3751 static const struct dis386 prefix_table[][4] = {
3752   /* PREFIX_90 */
3753   {
3754     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3755     { "pause", { XX }, 0 },
3756     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3757     { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3758   },
3759
3760   /* PREFIX_0F10 */
3761   {
3762     { "movups", { XM, EXx }, PREFIX_OPCODE },
3763     { "movss",  { XM, EXd }, PREFIX_OPCODE },
3764     { "movupd", { XM, EXx }, PREFIX_OPCODE },
3765     { "movsd",  { XM, EXq }, PREFIX_OPCODE },
3766   },
3767
3768   /* PREFIX_0F11 */
3769   {
3770     { "movups", { EXxS, XM }, PREFIX_OPCODE },
3771     { "movss",  { EXdS, XM }, PREFIX_OPCODE },
3772     { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3773     { "movsd",  { EXqS, XM }, PREFIX_OPCODE },
3774   },
3775
3776   /* PREFIX_0F12 */
3777   {
3778     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3779     { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3780     { "movlpd", { XM, EXq }, PREFIX_OPCODE },
3781     { "movddup", { XM, EXq }, PREFIX_OPCODE },
3782   },
3783
3784   /* PREFIX_0F16 */
3785   {
3786     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3787     { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3788     { "movhpd", { XM, EXq }, PREFIX_OPCODE },
3789   },
3790
3791   /* PREFIX_0F1A */
3792   {
3793     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3794     { "bndcl",  { Gbnd, Ev_bnd }, 0 },
3795     { "bndmov", { Gbnd, Ebnd }, 0 },
3796     { "bndcu",  { Gbnd, Ev_bnd }, 0 },
3797   },
3798
3799   /* PREFIX_0F1B */
3800   {
3801     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3802     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3803     { "bndmov", { Ebnd, Gbnd }, 0 },
3804     { "bndcn",  { Gbnd, Ev_bnd }, 0 },
3805   },
3806
3807   /* PREFIX_0F2A */
3808   {
3809     { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3810     { "cvtsi2ss%LQ", { XM, Ev }, PREFIX_OPCODE },
3811     { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3812     { "cvtsi2sd%LQ", { XM, Ev }, 0 },
3813   },
3814
3815   /* PREFIX_0F2B */
3816   {
3817     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3818     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3819     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3820     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3821   },
3822
3823   /* PREFIX_0F2C */
3824   {
3825     { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3826     { "cvttss2siY", { Gv, EXd }, PREFIX_OPCODE },
3827     { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3828     { "cvttsd2siY", { Gv, EXq }, PREFIX_OPCODE },
3829   },
3830
3831   /* PREFIX_0F2D */
3832   {
3833     { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3834     { "cvtss2siY", { Gv, EXd }, PREFIX_OPCODE },
3835     { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3836     { "cvtsd2siY", { Gv, EXq }, PREFIX_OPCODE },
3837   },
3838
3839   /* PREFIX_0F2E */
3840   {
3841     { "ucomiss",{ XM, EXd }, 0 },
3842     { Bad_Opcode },
3843     { "ucomisd",{ XM, EXq }, 0 },
3844   },
3845
3846   /* PREFIX_0F2F */
3847   {
3848     { "comiss", { XM, EXd }, 0 },
3849     { Bad_Opcode },
3850     { "comisd", { XM, EXq }, 0 },
3851   },
3852
3853   /* PREFIX_0F51 */
3854   {
3855     { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3856     { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3857     { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3858     { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3859   },
3860
3861   /* PREFIX_0F52 */
3862   {
3863     { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3864     { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3865   },
3866
3867   /* PREFIX_0F53 */
3868   {
3869     { "rcpps",  { XM, EXx }, PREFIX_OPCODE },
3870     { "rcpss",  { XM, EXd }, PREFIX_OPCODE },
3871   },
3872
3873   /* PREFIX_0F58 */
3874   {
3875     { "addps", { XM, EXx }, PREFIX_OPCODE },
3876     { "addss", { XM, EXd }, PREFIX_OPCODE },
3877     { "addpd", { XM, EXx }, PREFIX_OPCODE },
3878     { "addsd", { XM, EXq }, PREFIX_OPCODE },
3879   },
3880
3881   /* PREFIX_0F59 */
3882   {
3883     { "mulps",  { XM, EXx }, PREFIX_OPCODE },
3884     { "mulss",  { XM, EXd }, PREFIX_OPCODE },
3885     { "mulpd",  { XM, EXx }, PREFIX_OPCODE },
3886     { "mulsd",  { XM, EXq }, PREFIX_OPCODE },
3887   },
3888
3889   /* PREFIX_0F5A */
3890   {
3891     { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3892     { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3893     { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3894     { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3895   },
3896
3897   /* PREFIX_0F5B */
3898   {
3899     { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3900     { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3901     { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3902   },
3903
3904   /* PREFIX_0F5C */
3905   {
3906     { "subps",  { XM, EXx }, PREFIX_OPCODE },
3907     { "subss",  { XM, EXd }, PREFIX_OPCODE },
3908     { "subpd",  { XM, EXx }, PREFIX_OPCODE },
3909     { "subsd",  { XM, EXq }, PREFIX_OPCODE },
3910   },
3911
3912   /* PREFIX_0F5D */
3913   {
3914     { "minps",  { XM, EXx }, PREFIX_OPCODE },
3915     { "minss",  { XM, EXd }, PREFIX_OPCODE },
3916     { "minpd",  { XM, EXx }, PREFIX_OPCODE },
3917     { "minsd",  { XM, EXq }, PREFIX_OPCODE },
3918   },
3919
3920   /* PREFIX_0F5E */
3921   {
3922     { "divps",  { XM, EXx }, PREFIX_OPCODE },
3923     { "divss",  { XM, EXd }, PREFIX_OPCODE },
3924     { "divpd",  { XM, EXx }, PREFIX_OPCODE },
3925     { "divsd",  { XM, EXq }, PREFIX_OPCODE },
3926   },
3927
3928   /* PREFIX_0F5F */
3929   {
3930     { "maxps",  { XM, EXx }, PREFIX_OPCODE },
3931     { "maxss",  { XM, EXd }, PREFIX_OPCODE },
3932     { "maxpd",  { XM, EXx }, PREFIX_OPCODE },
3933     { "maxsd",  { XM, EXq }, PREFIX_OPCODE },
3934   },
3935
3936   /* PREFIX_0F60 */
3937   {
3938     { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3939     { Bad_Opcode },
3940     { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3941   },
3942
3943   /* PREFIX_0F61 */
3944   {
3945     { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3946     { Bad_Opcode },
3947     { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3948   },
3949
3950   /* PREFIX_0F62 */
3951   {
3952     { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3953     { Bad_Opcode },
3954     { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3955   },
3956
3957   /* PREFIX_0F6C */
3958   {
3959     { Bad_Opcode },
3960     { Bad_Opcode },
3961     { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE },
3962   },
3963
3964   /* PREFIX_0F6D */
3965   {
3966     { Bad_Opcode },
3967     { Bad_Opcode },
3968     { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE },
3969   },
3970
3971   /* PREFIX_0F6F */
3972   {
3973     { "movq",   { MX, EM }, PREFIX_OPCODE },
3974     { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3975     { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3976   },
3977
3978   /* PREFIX_0F70 */
3979   {
3980     { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3981     { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3982     { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3983     { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3984   },
3985
3986   /* PREFIX_0F73_REG_3 */
3987   {
3988     { Bad_Opcode },
3989     { Bad_Opcode },
3990     { "psrldq", { XS, Ib }, 0 },
3991   },
3992
3993   /* PREFIX_0F73_REG_7 */
3994   {
3995     { Bad_Opcode },
3996     { Bad_Opcode },
3997     { "pslldq", { XS, Ib }, 0 },
3998   },
3999
4000   /* PREFIX_0F78 */
4001   {
4002     {"vmread",  { Em, Gm }, 0 },
4003     { Bad_Opcode },
4004     {"extrq",   { XS, Ib, Ib }, 0 },
4005     {"insertq", { XM, XS, Ib, Ib }, 0 },
4006   },
4007
4008   /* PREFIX_0F79 */
4009   {
4010     {"vmwrite", { Gm, Em }, 0 },
4011     { Bad_Opcode },
4012     {"extrq",   { XM, XS }, 0 },
4013     {"insertq", { XM, XS }, 0 },
4014   },
4015
4016   /* PREFIX_0F7C */
4017   {
4018     { Bad_Opcode },
4019     { Bad_Opcode },
4020     { "haddpd", { XM, EXx }, PREFIX_OPCODE },
4021     { "haddps", { XM, EXx }, PREFIX_OPCODE },
4022   },
4023
4024   /* PREFIX_0F7D */
4025   {
4026     { Bad_Opcode },
4027     { Bad_Opcode },
4028     { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
4029     { "hsubps", { XM, EXx }, PREFIX_OPCODE },
4030   },
4031
4032   /* PREFIX_0F7E */
4033   {
4034     { "movK",   { Edq, MX }, PREFIX_OPCODE },
4035     { "movq",   { XM, EXq }, PREFIX_OPCODE },
4036     { "movK",   { Edq, XM }, PREFIX_OPCODE },
4037   },
4038
4039   /* PREFIX_0F7F */
4040   {
4041     { "movq",   { EMS, MX }, PREFIX_OPCODE },
4042     { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
4043     { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
4044   },
4045
4046   /* PREFIX_0FAE_REG_0 */
4047   {
4048     { Bad_Opcode },
4049     { "rdfsbase", { Ev }, 0 },
4050   },
4051
4052   /* PREFIX_0FAE_REG_1 */
4053   {
4054     { Bad_Opcode },
4055     { "rdgsbase", { Ev }, 0 },
4056   },
4057
4058   /* PREFIX_0FAE_REG_2 */
4059   {
4060     { Bad_Opcode },
4061     { "wrfsbase", { Ev }, 0 },
4062   },
4063
4064   /* PREFIX_0FAE_REG_3 */
4065   {
4066     { Bad_Opcode },
4067     { "wrgsbase", { Ev }, 0 },
4068   },
4069
4070   /* PREFIX_MOD_0_0FAE_REG_4 */
4071   {
4072     { "xsave",  { FXSAVE }, 0 },
4073     { "ptwrite%LQ", { Edq }, 0 },
4074   },
4075
4076   /* PREFIX_MOD_3_0FAE_REG_4 */
4077   {
4078     { Bad_Opcode },
4079     { "ptwrite%LQ", { Edq }, 0 },
4080   },
4081
4082   /* PREFIX_0FAE_REG_6 */
4083   {
4084     { "xsaveopt",      { FXSAVE }, 0 },
4085     { Bad_Opcode },
4086     { "clwb",   { Mb }, 0 },
4087   },
4088
4089   /* PREFIX_0FAE_REG_7 */
4090   {
4091     { "clflush",        { Mb }, 0 },
4092     { Bad_Opcode },
4093     { "clflushopt",     { Mb }, 0 },
4094   },
4095
4096   /* PREFIX_0FB8 */
4097   {
4098     { Bad_Opcode },
4099     { "popcntS", { Gv, Ev }, 0 },
4100   },
4101
4102   /* PREFIX_0FBC */
4103   {
4104     { "bsfS",   { Gv, Ev }, 0 },
4105     { "tzcntS", { Gv, Ev }, 0 },
4106     { "bsfS",   { Gv, Ev }, 0 },
4107   },
4108
4109   /* PREFIX_0FBD */
4110   {
4111     { "bsrS",   { Gv, Ev }, 0 },
4112     { "lzcntS", { Gv, Ev }, 0 },
4113     { "bsrS",   { Gv, Ev }, 0 },
4114   },
4115
4116   /* PREFIX_0FC2 */
4117   {
4118     { "cmpps",  { XM, EXx, CMP }, PREFIX_OPCODE },
4119     { "cmpss",  { XM, EXd, CMP }, PREFIX_OPCODE },
4120     { "cmppd",  { XM, EXx, CMP }, PREFIX_OPCODE },
4121     { "cmpsd",  { XM, EXq, CMP }, PREFIX_OPCODE },
4122   },
4123
4124   /* PREFIX_MOD_0_0FC3 */
4125   {
4126     { "movntiS", { Ev, Gv }, PREFIX_OPCODE },
4127   },
4128
4129   /* PREFIX_MOD_0_0FC7_REG_6 */
4130   {
4131     { "vmptrld",{ Mq }, 0 },
4132     { "vmxon",  { Mq }, 0 },
4133     { "vmclear",{ Mq }, 0 },
4134   },
4135
4136   /* PREFIX_MOD_3_0FC7_REG_6 */
4137   {
4138     { "rdrand", { Ev }, 0 },
4139     { Bad_Opcode },
4140     { "rdrand", { Ev }, 0 }
4141   },
4142
4143   /* PREFIX_MOD_3_0FC7_REG_7 */
4144   {
4145     { "rdseed", { Ev }, 0 },
4146     { "rdpid",  { Em }, 0 },
4147     { "rdseed", { Ev }, 0 },
4148   },
4149
4150   /* PREFIX_0FD0 */
4151   {
4152     { Bad_Opcode },
4153     { Bad_Opcode },
4154     { "addsubpd", { XM, EXx }, 0 },
4155     { "addsubps", { XM, EXx }, 0 },
4156   },
4157
4158   /* PREFIX_0FD6 */
4159   {
4160     { Bad_Opcode },
4161     { "movq2dq",{ XM, MS }, 0 },
4162     { "movq",   { EXqS, XM }, 0 },
4163     { "movdq2q",{ MX, XS }, 0 },
4164   },
4165
4166   /* PREFIX_0FE6 */
4167   {
4168     { Bad_Opcode },
4169     { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
4170     { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
4171     { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
4172   },
4173
4174   /* PREFIX_0FE7 */
4175   {
4176     { "movntq", { Mq, MX }, PREFIX_OPCODE },
4177     { Bad_Opcode },
4178     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
4179   },
4180
4181   /* PREFIX_0FF0 */
4182   {
4183     { Bad_Opcode },
4184     { Bad_Opcode },
4185     { Bad_Opcode },
4186     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4187   },
4188
4189   /* PREFIX_0FF7 */
4190   {
4191     { "maskmovq", { MX, MS }, PREFIX_OPCODE },
4192     { Bad_Opcode },
4193     { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
4194   },
4195
4196   /* PREFIX_0F3810 */
4197   {
4198     { Bad_Opcode },
4199     { Bad_Opcode },
4200     { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4201   },
4202
4203   /* PREFIX_0F3814 */
4204   {
4205     { Bad_Opcode },
4206     { Bad_Opcode },
4207     { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4208   },
4209
4210   /* PREFIX_0F3815 */
4211   {
4212     { Bad_Opcode },
4213     { Bad_Opcode },
4214     { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4215   },
4216
4217   /* PREFIX_0F3817 */
4218   {
4219     { Bad_Opcode },
4220     { Bad_Opcode },
4221     { "ptest",  { XM, EXx }, PREFIX_OPCODE },
4222   },
4223
4224   /* PREFIX_0F3820 */
4225   {
4226     { Bad_Opcode },
4227     { Bad_Opcode },
4228     { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE },
4229   },
4230
4231   /* PREFIX_0F3821 */
4232   {
4233     { Bad_Opcode },
4234     { Bad_Opcode },
4235     { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE },
4236   },
4237
4238   /* PREFIX_0F3822 */
4239   {
4240     { Bad_Opcode },
4241     { Bad_Opcode },
4242     { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE },
4243   },
4244
4245   /* PREFIX_0F3823 */
4246   {
4247     { Bad_Opcode },
4248     { Bad_Opcode },
4249     { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE },
4250   },
4251
4252   /* PREFIX_0F3824 */
4253   {
4254     { Bad_Opcode },
4255     { Bad_Opcode },
4256     { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE },
4257   },
4258
4259   /* PREFIX_0F3825 */
4260   {
4261     { Bad_Opcode },
4262     { Bad_Opcode },
4263     { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE },
4264   },
4265
4266   /* PREFIX_0F3828 */
4267   {
4268     { Bad_Opcode },
4269     { Bad_Opcode },
4270     { "pmuldq", { XM, EXx }, PREFIX_OPCODE },
4271   },
4272
4273   /* PREFIX_0F3829 */
4274   {
4275     { Bad_Opcode },
4276     { Bad_Opcode },
4277     { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE },
4278   },
4279
4280   /* PREFIX_0F382A */
4281   {
4282     { Bad_Opcode },
4283     { Bad_Opcode },
4284     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4285   },
4286
4287   /* PREFIX_0F382B */
4288   {
4289     { Bad_Opcode },
4290     { Bad_Opcode },
4291     { "packusdw", { XM, EXx }, PREFIX_OPCODE },
4292   },
4293
4294   /* PREFIX_0F3830 */
4295   {
4296     { Bad_Opcode },
4297     { Bad_Opcode },
4298     { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE },
4299   },
4300
4301   /* PREFIX_0F3831 */
4302   {
4303     { Bad_Opcode },
4304     { Bad_Opcode },
4305     { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE },
4306   },
4307
4308   /* PREFIX_0F3832 */
4309   {
4310     { Bad_Opcode },
4311     { Bad_Opcode },
4312     { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE },
4313   },
4314
4315   /* PREFIX_0F3833 */
4316   {
4317     { Bad_Opcode },
4318     { Bad_Opcode },
4319     { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE },
4320   },
4321
4322   /* PREFIX_0F3834 */
4323   {
4324     { Bad_Opcode },
4325     { Bad_Opcode },
4326     { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE },
4327   },
4328
4329   /* PREFIX_0F3835 */
4330   {
4331     { Bad_Opcode },
4332     { Bad_Opcode },
4333     { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE },
4334   },
4335
4336   /* PREFIX_0F3837 */
4337   {
4338     { Bad_Opcode },
4339     { Bad_Opcode },
4340     { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE },
4341   },
4342
4343   /* PREFIX_0F3838 */
4344   {
4345     { Bad_Opcode },
4346     { Bad_Opcode },
4347     { "pminsb", { XM, EXx }, PREFIX_OPCODE },
4348   },
4349
4350   /* PREFIX_0F3839 */
4351   {
4352     { Bad_Opcode },
4353     { Bad_Opcode },
4354     { "pminsd", { XM, EXx }, PREFIX_OPCODE },
4355   },
4356
4357   /* PREFIX_0F383A */
4358   {
4359     { Bad_Opcode },
4360     { Bad_Opcode },
4361     { "pminuw", { XM, EXx }, PREFIX_OPCODE },
4362   },
4363
4364   /* PREFIX_0F383B */
4365   {
4366     { Bad_Opcode },
4367     { Bad_Opcode },
4368     { "pminud", { XM, EXx }, PREFIX_OPCODE },
4369   },
4370
4371   /* PREFIX_0F383C */
4372   {
4373     { Bad_Opcode },
4374     { Bad_Opcode },
4375     { "pmaxsb", { XM, EXx }, PREFIX_OPCODE },
4376   },
4377
4378   /* PREFIX_0F383D */
4379   {
4380     { Bad_Opcode },
4381     { Bad_Opcode },
4382     { "pmaxsd", { XM, EXx }, PREFIX_OPCODE },
4383   },
4384
4385   /* PREFIX_0F383E */
4386   {
4387     { Bad_Opcode },
4388     { Bad_Opcode },
4389     { "pmaxuw", { XM, EXx }, PREFIX_OPCODE },
4390   },
4391
4392   /* PREFIX_0F383F */
4393   {
4394     { Bad_Opcode },
4395     { Bad_Opcode },
4396     { "pmaxud", { XM, EXx }, PREFIX_OPCODE },
4397   },
4398
4399   /* PREFIX_0F3840 */
4400   {
4401     { Bad_Opcode },
4402     { Bad_Opcode },
4403     { "pmulld", { XM, EXx }, PREFIX_OPCODE },
4404   },
4405
4406   /* PREFIX_0F3841 */
4407   {
4408     { Bad_Opcode },
4409     { Bad_Opcode },
4410     { "phminposuw", { XM, EXx }, PREFIX_OPCODE },
4411   },
4412
4413   /* PREFIX_0F3880 */
4414   {
4415     { Bad_Opcode },
4416     { Bad_Opcode },
4417     { "invept", { Gm, Mo }, PREFIX_OPCODE },
4418   },
4419
4420   /* PREFIX_0F3881 */
4421   {
4422     { Bad_Opcode },
4423     { Bad_Opcode },
4424     { "invvpid", { Gm, Mo }, PREFIX_OPCODE },
4425   },
4426
4427   /* PREFIX_0F3882 */
4428   {
4429     { Bad_Opcode },
4430     { Bad_Opcode },
4431     { "invpcid", { Gm, M }, PREFIX_OPCODE },
4432   },
4433
4434   /* PREFIX_0F38C8 */
4435   {
4436     { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4437   },
4438
4439   /* PREFIX_0F38C9 */
4440   {
4441     { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4442   },
4443
4444   /* PREFIX_0F38CA */
4445   {
4446     { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4447   },
4448
4449   /* PREFIX_0F38CB */
4450   {
4451     { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4452   },
4453
4454   /* PREFIX_0F38CC */
4455   {
4456     { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4457   },
4458
4459   /* PREFIX_0F38CD */
4460   {
4461     { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4462   },
4463
4464   /* PREFIX_0F38DB */
4465   {
4466     { Bad_Opcode },
4467     { Bad_Opcode },
4468     { "aesimc", { XM, EXx }, PREFIX_OPCODE },
4469   },
4470
4471   /* PREFIX_0F38DC */
4472   {
4473     { Bad_Opcode },
4474     { Bad_Opcode },
4475     { "aesenc", { XM, EXx }, PREFIX_OPCODE },
4476   },
4477
4478   /* PREFIX_0F38DD */
4479   {
4480     { Bad_Opcode },
4481     { Bad_Opcode },
4482     { "aesenclast", { XM, EXx }, PREFIX_OPCODE },
4483   },
4484
4485   /* PREFIX_0F38DE */
4486   {
4487     { Bad_Opcode },
4488     { Bad_Opcode },
4489     { "aesdec", { XM, EXx }, PREFIX_OPCODE },
4490   },
4491
4492   /* PREFIX_0F38DF */
4493   {
4494     { Bad_Opcode },
4495     { Bad_Opcode },
4496     { "aesdeclast", { XM, EXx }, PREFIX_OPCODE },
4497   },
4498
4499   /* PREFIX_0F38F0 */
4500   {
4501     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4502     { Bad_Opcode },
4503     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4504     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE },
4505   },
4506
4507   /* PREFIX_0F38F1 */
4508   {
4509     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4510     { Bad_Opcode },
4511     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4512     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE },
4513   },
4514
4515   /* PREFIX_0F38F6 */
4516   {
4517     { Bad_Opcode },
4518     { "adoxS",  { Gdq, Edq}, PREFIX_OPCODE },
4519     { "adcxS",  { Gdq, Edq}, PREFIX_OPCODE },
4520     { Bad_Opcode },
4521   },
4522
4523   /* PREFIX_0F3A08 */
4524   {
4525     { Bad_Opcode },
4526     { Bad_Opcode },
4527     { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE },
4528   },
4529
4530   /* PREFIX_0F3A09 */
4531   {
4532     { Bad_Opcode },
4533     { Bad_Opcode },
4534     { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4535   },
4536
4537   /* PREFIX_0F3A0A */
4538   {
4539     { Bad_Opcode },
4540     { Bad_Opcode },
4541     { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE },
4542   },
4543
4544   /* PREFIX_0F3A0B */
4545   {
4546     { Bad_Opcode },
4547     { Bad_Opcode },
4548     { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE },
4549   },
4550
4551   /* PREFIX_0F3A0C */
4552   {
4553     { Bad_Opcode },
4554     { Bad_Opcode },
4555     { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE },
4556   },
4557
4558   /* PREFIX_0F3A0D */
4559   {
4560     { Bad_Opcode },
4561     { Bad_Opcode },
4562     { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4563   },
4564
4565   /* PREFIX_0F3A0E */
4566   {
4567     { Bad_Opcode },
4568     { Bad_Opcode },
4569     { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE },
4570   },
4571
4572   /* PREFIX_0F3A14 */
4573   {
4574     { Bad_Opcode },
4575     { Bad_Opcode },
4576     { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE },
4577   },
4578
4579   /* PREFIX_0F3A15 */
4580   {
4581     { Bad_Opcode },
4582     { Bad_Opcode },
4583     { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE },
4584   },
4585
4586   /* PREFIX_0F3A16 */
4587   {
4588     { Bad_Opcode },
4589     { Bad_Opcode },
4590     { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE },
4591   },
4592
4593   /* PREFIX_0F3A17 */
4594   {
4595     { Bad_Opcode },
4596     { Bad_Opcode },
4597     { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE },
4598   },
4599
4600   /* PREFIX_0F3A20 */
4601   {
4602     { Bad_Opcode },
4603     { Bad_Opcode },
4604     { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE },
4605   },
4606
4607   /* PREFIX_0F3A21 */
4608   {
4609     { Bad_Opcode },
4610     { Bad_Opcode },
4611     { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE },
4612   },
4613
4614   /* PREFIX_0F3A22 */
4615   {
4616     { Bad_Opcode },
4617     { Bad_Opcode },
4618     { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE },
4619   },
4620
4621   /* PREFIX_0F3A40 */
4622   {
4623     { Bad_Opcode },
4624     { Bad_Opcode },
4625     { "dpps",   { XM, EXx, Ib }, PREFIX_OPCODE },
4626   },
4627
4628   /* PREFIX_0F3A41 */
4629   {
4630     { Bad_Opcode },
4631     { Bad_Opcode },
4632     { "dppd",   { XM, EXx, Ib }, PREFIX_OPCODE },
4633   },
4634
4635   /* PREFIX_0F3A42 */
4636   {
4637     { Bad_Opcode },
4638     { Bad_Opcode },
4639     { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE },
4640   },
4641
4642   /* PREFIX_0F3A44 */
4643   {
4644     { Bad_Opcode },
4645     { Bad_Opcode },
4646     { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE },
4647   },
4648
4649   /* PREFIX_0F3A60 */
4650   {
4651     { Bad_Opcode },
4652     { Bad_Opcode },
4653     { "pcmpestrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4654   },
4655
4656   /* PREFIX_0F3A61 */
4657   {
4658     { Bad_Opcode },
4659     { Bad_Opcode },
4660     { "pcmpestri", { XM, EXx, Ib }, PREFIX_OPCODE },
4661   },
4662
4663   /* PREFIX_0F3A62 */
4664   {
4665     { Bad_Opcode },
4666     { Bad_Opcode },
4667     { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4668   },
4669
4670   /* PREFIX_0F3A63 */
4671   {
4672     { Bad_Opcode },
4673     { Bad_Opcode },
4674     { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE },
4675   },
4676
4677   /* PREFIX_0F3ACC */
4678   {
4679     { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4680   },
4681
4682   /* PREFIX_0F3ADF */
4683   {
4684     { Bad_Opcode },
4685     { Bad_Opcode },
4686     { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE },
4687   },
4688
4689   /* PREFIX_VEX_0F10 */
4690   {
4691     { VEX_W_TABLE (VEX_W_0F10_P_0) },
4692     { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) },
4693     { VEX_W_TABLE (VEX_W_0F10_P_2) },
4694     { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) },
4695   },
4696
4697   /* PREFIX_VEX_0F11 */
4698   {
4699     { VEX_W_TABLE (VEX_W_0F11_P_0) },
4700     { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) },
4701     { VEX_W_TABLE (VEX_W_0F11_P_2) },
4702     { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) },
4703   },
4704
4705   /* PREFIX_VEX_0F12 */
4706   {
4707     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4708     { VEX_W_TABLE (VEX_W_0F12_P_1) },
4709     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
4710     { VEX_W_TABLE (VEX_W_0F12_P_3) },
4711   },
4712
4713   /* PREFIX_VEX_0F16 */
4714   {
4715     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4716     { VEX_W_TABLE (VEX_W_0F16_P_1) },
4717     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
4718   },
4719
4720   /* PREFIX_VEX_0F2A */
4721   {
4722     { Bad_Opcode },
4723     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) },
4724     { Bad_Opcode },
4725     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) },
4726   },
4727
4728   /* PREFIX_VEX_0F2C */
4729   {
4730     { Bad_Opcode },
4731     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) },
4732     { Bad_Opcode },
4733     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) },
4734   },
4735
4736   /* PREFIX_VEX_0F2D */
4737   {
4738     { Bad_Opcode },
4739     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) },
4740     { Bad_Opcode },
4741     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) },
4742   },
4743
4744   /* PREFIX_VEX_0F2E */
4745   {
4746     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) },
4747     { Bad_Opcode },
4748     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) },
4749   },
4750
4751   /* PREFIX_VEX_0F2F */
4752   {
4753     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) },
4754     { Bad_Opcode },
4755     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) },
4756   },
4757
4758   /* PREFIX_VEX_0F41 */
4759   {
4760     { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4761     { Bad_Opcode },
4762     { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4763   },
4764
4765   /* PREFIX_VEX_0F42 */
4766   {
4767     { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4768     { Bad_Opcode },
4769     { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4770   },
4771
4772   /* PREFIX_VEX_0F44 */
4773   {
4774     { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4775     { Bad_Opcode },
4776     { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4777   },
4778
4779   /* PREFIX_VEX_0F45 */
4780   {
4781     { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4782     { Bad_Opcode },
4783     { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4784   },
4785
4786   /* PREFIX_VEX_0F46 */
4787   {
4788     { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4789     { Bad_Opcode },
4790     { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4791   },
4792
4793   /* PREFIX_VEX_0F47 */
4794   {
4795     { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4796     { Bad_Opcode },
4797     { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
4798   },
4799
4800   /* PREFIX_VEX_0F4A */
4801   {
4802     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
4803     { Bad_Opcode },
4804     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
4805   },
4806
4807   /* PREFIX_VEX_0F4B */
4808   {
4809     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
4810     { Bad_Opcode },
4811     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4812   },
4813
4814   /* PREFIX_VEX_0F51 */
4815   {
4816     { VEX_W_TABLE (VEX_W_0F51_P_0) },
4817     { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) },
4818     { VEX_W_TABLE (VEX_W_0F51_P_2) },
4819     { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) },
4820   },
4821
4822   /* PREFIX_VEX_0F52 */
4823   {
4824     { VEX_W_TABLE (VEX_W_0F52_P_0) },
4825     { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) },
4826   },
4827
4828   /* PREFIX_VEX_0F53 */
4829   {
4830     { VEX_W_TABLE (VEX_W_0F53_P_0) },
4831     { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) },
4832   },
4833
4834   /* PREFIX_VEX_0F58 */
4835   {
4836     { VEX_W_TABLE (VEX_W_0F58_P_0) },
4837     { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) },
4838     { VEX_W_TABLE (VEX_W_0F58_P_2) },
4839     { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) },
4840   },
4841
4842   /* PREFIX_VEX_0F59 */
4843   {
4844     { VEX_W_TABLE (VEX_W_0F59_P_0) },
4845     { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) },
4846     { VEX_W_TABLE (VEX_W_0F59_P_2) },
4847     { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) },
4848   },
4849
4850   /* PREFIX_VEX_0F5A */
4851   {
4852     { VEX_W_TABLE (VEX_W_0F5A_P_0) },
4853     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) },
4854     { "vcvtpd2ps%XY", { XMM, EXx }, 0 },
4855     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) },
4856   },
4857
4858   /* PREFIX_VEX_0F5B */
4859   {
4860     { VEX_W_TABLE (VEX_W_0F5B_P_0) },
4861     { VEX_W_TABLE (VEX_W_0F5B_P_1) },
4862     { VEX_W_TABLE (VEX_W_0F5B_P_2) },
4863   },
4864
4865   /* PREFIX_VEX_0F5C */
4866   {
4867     { VEX_W_TABLE (VEX_W_0F5C_P_0) },
4868     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) },
4869     { VEX_W_TABLE (VEX_W_0F5C_P_2) },
4870     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) },
4871   },
4872
4873   /* PREFIX_VEX_0F5D */
4874   {
4875     { VEX_W_TABLE (VEX_W_0F5D_P_0) },
4876     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) },
4877     { VEX_W_TABLE (VEX_W_0F5D_P_2) },
4878     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) },
4879   },
4880
4881   /* PREFIX_VEX_0F5E */
4882   {
4883     { VEX_W_TABLE (VEX_W_0F5E_P_0) },
4884     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) },
4885     { VEX_W_TABLE (VEX_W_0F5E_P_2) },
4886     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) },
4887   },
4888
4889   /* PREFIX_VEX_0F5F */
4890   {
4891     { VEX_W_TABLE (VEX_W_0F5F_P_0) },
4892     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) },
4893     { VEX_W_TABLE (VEX_W_0F5F_P_2) },
4894     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) },
4895   },
4896
4897   /* PREFIX_VEX_0F60 */
4898   {
4899     { Bad_Opcode },
4900     { Bad_Opcode },
4901     { VEX_W_TABLE (VEX_W_0F60_P_2) },
4902   },
4903
4904   /* PREFIX_VEX_0F61 */
4905   {
4906     { Bad_Opcode },
4907     { Bad_Opcode },
4908     { VEX_W_TABLE (VEX_W_0F61_P_2) },
4909   },
4910
4911   /* PREFIX_VEX_0F62 */
4912   {
4913     { Bad_Opcode },
4914     { Bad_Opcode },
4915     { VEX_W_TABLE (VEX_W_0F62_P_2) },
4916   },
4917
4918   /* PREFIX_VEX_0F63 */
4919   {
4920     { Bad_Opcode },
4921     { Bad_Opcode },
4922     { VEX_W_TABLE (VEX_W_0F63_P_2) },
4923   },
4924
4925   /* PREFIX_VEX_0F64 */
4926   {
4927     { Bad_Opcode },
4928     { Bad_Opcode },
4929     { VEX_W_TABLE (VEX_W_0F64_P_2) },
4930   },
4931
4932   /* PREFIX_VEX_0F65 */
4933   {
4934     { Bad_Opcode },
4935     { Bad_Opcode },
4936     { VEX_W_TABLE (VEX_W_0F65_P_2) },
4937   },
4938
4939   /* PREFIX_VEX_0F66 */
4940   {
4941     { Bad_Opcode },
4942     { Bad_Opcode },
4943     { VEX_W_TABLE (VEX_W_0F66_P_2) },
4944   },
4945
4946   /* PREFIX_VEX_0F67 */
4947   {
4948     { Bad_Opcode },
4949     { Bad_Opcode },
4950     { VEX_W_TABLE (VEX_W_0F67_P_2) },
4951   },
4952
4953   /* PREFIX_VEX_0F68 */
4954   {
4955     { Bad_Opcode },
4956     { Bad_Opcode },
4957     { VEX_W_TABLE (VEX_W_0F68_P_2) },
4958   },
4959
4960   /* PREFIX_VEX_0F69 */
4961   {
4962     { Bad_Opcode },
4963     { Bad_Opcode },
4964     { VEX_W_TABLE (VEX_W_0F69_P_2) },
4965   },
4966
4967   /* PREFIX_VEX_0F6A */
4968   {
4969     { Bad_Opcode },
4970     { Bad_Opcode },
4971     { VEX_W_TABLE (VEX_W_0F6A_P_2) },
4972   },
4973
4974   /* PREFIX_VEX_0F6B */
4975   {
4976     { Bad_Opcode },
4977     { Bad_Opcode },
4978     { VEX_W_TABLE (VEX_W_0F6B_P_2) },
4979   },
4980
4981   /* PREFIX_VEX_0F6C */
4982   {
4983     { Bad_Opcode },
4984     { Bad_Opcode },
4985     { VEX_W_TABLE (VEX_W_0F6C_P_2) },
4986   },
4987
4988   /* PREFIX_VEX_0F6D */
4989   {
4990     { Bad_Opcode },
4991     { Bad_Opcode },
4992     { VEX_W_TABLE (VEX_W_0F6D_P_2) },
4993   },
4994
4995   /* PREFIX_VEX_0F6E */
4996   {
4997     { Bad_Opcode },
4998     { Bad_Opcode },
4999     { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
5000   },
5001
5002   /* PREFIX_VEX_0F6F */
5003   {
5004     { Bad_Opcode },
5005     { VEX_W_TABLE (VEX_W_0F6F_P_1) },
5006     { VEX_W_TABLE (VEX_W_0F6F_P_2) },
5007   },
5008
5009   /* PREFIX_VEX_0F70 */
5010   {
5011     { Bad_Opcode },
5012     { VEX_W_TABLE (VEX_W_0F70_P_1) },
5013     { VEX_W_TABLE (VEX_W_0F70_P_2) },
5014     { VEX_W_TABLE (VEX_W_0F70_P_3) },
5015   },
5016
5017   /* PREFIX_VEX_0F71_REG_2 */
5018   {
5019     { Bad_Opcode },
5020     { Bad_Opcode },
5021     { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) },
5022   },
5023
5024   /* PREFIX_VEX_0F71_REG_4 */
5025   {
5026     { Bad_Opcode },
5027     { Bad_Opcode },
5028     { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) },
5029   },
5030
5031   /* PREFIX_VEX_0F71_REG_6 */
5032   {
5033     { Bad_Opcode },
5034     { Bad_Opcode },
5035     { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) },
5036   },
5037
5038   /* PREFIX_VEX_0F72_REG_2 */
5039   {
5040     { Bad_Opcode },
5041     { Bad_Opcode },
5042     { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) },
5043   },
5044
5045   /* PREFIX_VEX_0F72_REG_4 */
5046   {
5047     { Bad_Opcode },
5048     { Bad_Opcode },
5049     { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) },
5050   },
5051
5052   /* PREFIX_VEX_0F72_REG_6 */
5053   {
5054     { Bad_Opcode },
5055     { Bad_Opcode },
5056     { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) },
5057   },
5058
5059   /* PREFIX_VEX_0F73_REG_2 */
5060   {
5061     { Bad_Opcode },
5062     { Bad_Opcode },
5063     { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) },
5064   },
5065
5066   /* PREFIX_VEX_0F73_REG_3 */
5067   {
5068     { Bad_Opcode },
5069     { Bad_Opcode },
5070     { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) },
5071   },
5072
5073   /* PREFIX_VEX_0F73_REG_6 */
5074   {
5075     { Bad_Opcode },
5076     { Bad_Opcode },
5077     { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) },
5078   },
5079
5080   /* PREFIX_VEX_0F73_REG_7 */
5081   {
5082     { Bad_Opcode },
5083     { Bad_Opcode },
5084     { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) },
5085   },
5086
5087   /* PREFIX_VEX_0F74 */
5088   {
5089     { Bad_Opcode },
5090     { Bad_Opcode },
5091     { VEX_W_TABLE (VEX_W_0F74_P_2) },
5092   },
5093
5094   /* PREFIX_VEX_0F75 */
5095   {
5096     { Bad_Opcode },
5097     { Bad_Opcode },
5098     { VEX_W_TABLE (VEX_W_0F75_P_2) },
5099   },
5100
5101   /* PREFIX_VEX_0F76 */
5102   {
5103     { Bad_Opcode },
5104     { Bad_Opcode },
5105     { VEX_W_TABLE (VEX_W_0F76_P_2) },
5106   },
5107
5108   /* PREFIX_VEX_0F77 */
5109   {
5110     { VEX_W_TABLE (VEX_W_0F77_P_0) },
5111   },
5112
5113   /* PREFIX_VEX_0F7C */
5114   {
5115     { Bad_Opcode },
5116     { Bad_Opcode },
5117     { VEX_W_TABLE (VEX_W_0F7C_P_2) },
5118     { VEX_W_TABLE (VEX_W_0F7C_P_3) },
5119   },
5120
5121   /* PREFIX_VEX_0F7D */
5122   {
5123     { Bad_Opcode },
5124     { Bad_Opcode },
5125     { VEX_W_TABLE (VEX_W_0F7D_P_2) },
5126     { VEX_W_TABLE (VEX_W_0F7D_P_3) },
5127   },
5128
5129   /* PREFIX_VEX_0F7E */
5130   {
5131     { Bad_Opcode },
5132     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
5133     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
5134   },
5135
5136   /* PREFIX_VEX_0F7F */
5137   {
5138     { Bad_Opcode },
5139     { VEX_W_TABLE (VEX_W_0F7F_P_1) },
5140     { VEX_W_TABLE (VEX_W_0F7F_P_2) },
5141   },
5142
5143   /* PREFIX_VEX_0F90 */
5144   {
5145     { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
5146     { Bad_Opcode },
5147     { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
5148   },
5149
5150   /* PREFIX_VEX_0F91 */
5151   {
5152     { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
5153     { Bad_Opcode },
5154     { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
5155   },
5156
5157   /* PREFIX_VEX_0F92 */
5158   {
5159     { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
5160     { Bad_Opcode },
5161     { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
5162     { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
5163   },
5164
5165   /* PREFIX_VEX_0F93 */
5166   {
5167     { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
5168     { Bad_Opcode },
5169     { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
5170     { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
5171   },
5172
5173   /* PREFIX_VEX_0F98 */
5174   {
5175     { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
5176     { Bad_Opcode },
5177     { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
5178   },
5179
5180   /* PREFIX_VEX_0F99 */
5181   {
5182     { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5183     { Bad_Opcode },
5184     { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5185   },
5186
5187   /* PREFIX_VEX_0FC2 */
5188   {
5189     { VEX_W_TABLE (VEX_W_0FC2_P_0) },
5190     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) },
5191     { VEX_W_TABLE (VEX_W_0FC2_P_2) },
5192     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) },
5193   },
5194
5195   /* PREFIX_VEX_0FC4 */
5196   {
5197     { Bad_Opcode },
5198     { Bad_Opcode },
5199     { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5200   },
5201
5202   /* PREFIX_VEX_0FC5 */
5203   {
5204     { Bad_Opcode },
5205     { Bad_Opcode },
5206     { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5207   },
5208
5209   /* PREFIX_VEX_0FD0 */
5210   {
5211     { Bad_Opcode },
5212     { Bad_Opcode },
5213     { VEX_W_TABLE (VEX_W_0FD0_P_2) },
5214     { VEX_W_TABLE (VEX_W_0FD0_P_3) },
5215   },
5216
5217   /* PREFIX_VEX_0FD1 */
5218   {
5219     { Bad_Opcode },
5220     { Bad_Opcode },
5221     { VEX_W_TABLE (VEX_W_0FD1_P_2) },
5222   },
5223
5224   /* PREFIX_VEX_0FD2 */
5225   {
5226     { Bad_Opcode },
5227     { Bad_Opcode },
5228     { VEX_W_TABLE (VEX_W_0FD2_P_2) },
5229   },
5230
5231   /* PREFIX_VEX_0FD3 */
5232   {
5233     { Bad_Opcode },
5234     { Bad_Opcode },
5235     { VEX_W_TABLE (VEX_W_0FD3_P_2) },
5236   },
5237
5238   /* PREFIX_VEX_0FD4 */
5239   {
5240     { Bad_Opcode },
5241     { Bad_Opcode },
5242     { VEX_W_TABLE (VEX_W_0FD4_P_2) },
5243   },
5244
5245   /* PREFIX_VEX_0FD5 */
5246   {
5247     { Bad_Opcode },
5248     { Bad_Opcode },
5249     { VEX_W_TABLE (VEX_W_0FD5_P_2) },
5250   },
5251
5252   /* PREFIX_VEX_0FD6 */
5253   {
5254     { Bad_Opcode },
5255     { Bad_Opcode },
5256     { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5257   },
5258
5259   /* PREFIX_VEX_0FD7 */
5260   {
5261     { Bad_Opcode },
5262     { Bad_Opcode },
5263     { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5264   },
5265
5266   /* PREFIX_VEX_0FD8 */
5267   {
5268     { Bad_Opcode },
5269     { Bad_Opcode },
5270     { VEX_W_TABLE (VEX_W_0FD8_P_2) },
5271   },
5272
5273   /* PREFIX_VEX_0FD9 */
5274   {
5275     { Bad_Opcode },
5276     { Bad_Opcode },
5277     { VEX_W_TABLE (VEX_W_0FD9_P_2) },
5278   },
5279
5280   /* PREFIX_VEX_0FDA */
5281   {
5282     { Bad_Opcode },
5283     { Bad_Opcode },
5284     { VEX_W_TABLE (VEX_W_0FDA_P_2) },
5285   },
5286
5287   /* PREFIX_VEX_0FDB */
5288   {
5289     { Bad_Opcode },
5290     { Bad_Opcode },
5291     { VEX_W_TABLE (VEX_W_0FDB_P_2) },
5292   },
5293
5294   /* PREFIX_VEX_0FDC */
5295   {
5296     { Bad_Opcode },
5297     { Bad_Opcode },
5298     { VEX_W_TABLE (VEX_W_0FDC_P_2) },
5299   },
5300
5301   /* PREFIX_VEX_0FDD */
5302   {
5303     { Bad_Opcode },
5304     { Bad_Opcode },
5305     { VEX_W_TABLE (VEX_W_0FDD_P_2) },
5306   },
5307
5308   /* PREFIX_VEX_0FDE */
5309   {
5310     { Bad_Opcode },
5311     { Bad_Opcode },
5312     { VEX_W_TABLE (VEX_W_0FDE_P_2) },
5313   },
5314
5315   /* PREFIX_VEX_0FDF */
5316   {
5317     { Bad_Opcode },
5318     { Bad_Opcode },
5319     { VEX_W_TABLE (VEX_W_0FDF_P_2) },
5320   },
5321
5322   /* PREFIX_VEX_0FE0 */
5323   {
5324     { Bad_Opcode },
5325     { Bad_Opcode },
5326     { VEX_W_TABLE (VEX_W_0FE0_P_2) },
5327   },
5328
5329   /* PREFIX_VEX_0FE1 */
5330   {
5331     { Bad_Opcode },
5332     { Bad_Opcode },
5333     { VEX_W_TABLE (VEX_W_0FE1_P_2) },
5334   },
5335
5336   /* PREFIX_VEX_0FE2 */
5337   {
5338     { Bad_Opcode },
5339     { Bad_Opcode },
5340     { VEX_W_TABLE (VEX_W_0FE2_P_2) },
5341   },
5342
5343   /* PREFIX_VEX_0FE3 */
5344   {
5345     { Bad_Opcode },
5346     { Bad_Opcode },
5347     { VEX_W_TABLE (VEX_W_0FE3_P_2) },
5348   },
5349
5350   /* PREFIX_VEX_0FE4 */
5351   {
5352     { Bad_Opcode },
5353     { Bad_Opcode },
5354     { VEX_W_TABLE (VEX_W_0FE4_P_2) },
5355   },
5356
5357   /* PREFIX_VEX_0FE5 */
5358   {
5359     { Bad_Opcode },
5360     { Bad_Opcode },
5361     { VEX_W_TABLE (VEX_W_0FE5_P_2) },
5362   },
5363
5364   /* PREFIX_VEX_0FE6 */
5365   {
5366     { Bad_Opcode },
5367     { VEX_W_TABLE (VEX_W_0FE6_P_1) },
5368     { VEX_W_TABLE (VEX_W_0FE6_P_2) },
5369     { VEX_W_TABLE (VEX_W_0FE6_P_3) },
5370   },
5371
5372   /* PREFIX_VEX_0FE7 */
5373   {
5374     { Bad_Opcode },
5375     { Bad_Opcode },
5376     { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5377   },
5378
5379   /* PREFIX_VEX_0FE8 */
5380   {
5381     { Bad_Opcode },
5382     { Bad_Opcode },
5383     { VEX_W_TABLE (VEX_W_0FE8_P_2) },
5384   },
5385
5386   /* PREFIX_VEX_0FE9 */
5387   {
5388     { Bad_Opcode },
5389     { Bad_Opcode },
5390     { VEX_W_TABLE (VEX_W_0FE9_P_2) },
5391   },
5392
5393   /* PREFIX_VEX_0FEA */
5394   {
5395     { Bad_Opcode },
5396     { Bad_Opcode },
5397     { VEX_W_TABLE (VEX_W_0FEA_P_2) },
5398   },
5399
5400   /* PREFIX_VEX_0FEB */
5401   {
5402     { Bad_Opcode },
5403     { Bad_Opcode },
5404     { VEX_W_TABLE (VEX_W_0FEB_P_2) },
5405   },
5406
5407   /* PREFIX_VEX_0FEC */
5408   {
5409     { Bad_Opcode },
5410     { Bad_Opcode },
5411     { VEX_W_TABLE (VEX_W_0FEC_P_2) },
5412   },
5413
5414   /* PREFIX_VEX_0FED */
5415   {
5416     { Bad_Opcode },
5417     { Bad_Opcode },
5418     { VEX_W_TABLE (VEX_W_0FED_P_2) },
5419   },
5420
5421   /* PREFIX_VEX_0FEE */
5422   {
5423     { Bad_Opcode },
5424     { Bad_Opcode },
5425     { VEX_W_TABLE (VEX_W_0FEE_P_2) },
5426   },
5427
5428   /* PREFIX_VEX_0FEF */
5429   {
5430     { Bad_Opcode },
5431     { Bad_Opcode },
5432     { VEX_W_TABLE (VEX_W_0FEF_P_2) },
5433   },
5434
5435   /* PREFIX_VEX_0FF0 */
5436   {
5437     { Bad_Opcode },
5438     { Bad_Opcode },
5439     { Bad_Opcode },
5440     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5441   },
5442
5443   /* PREFIX_VEX_0FF1 */
5444   {
5445     { Bad_Opcode },
5446     { Bad_Opcode },
5447     { VEX_W_TABLE (VEX_W_0FF1_P_2) },
5448   },
5449
5450   /* PREFIX_VEX_0FF2 */
5451   {
5452     { Bad_Opcode },
5453     { Bad_Opcode },
5454     { VEX_W_TABLE (VEX_W_0FF2_P_2) },
5455   },
5456
5457   /* PREFIX_VEX_0FF3 */
5458   {
5459     { Bad_Opcode },
5460     { Bad_Opcode },
5461     { VEX_W_TABLE (VEX_W_0FF3_P_2) },
5462   },
5463
5464   /* PREFIX_VEX_0FF4 */
5465   {
5466     { Bad_Opcode },
5467     { Bad_Opcode },
5468     { VEX_W_TABLE (VEX_W_0FF4_P_2) },
5469   },
5470
5471   /* PREFIX_VEX_0FF5 */
5472   {
5473     { Bad_Opcode },
5474     { Bad_Opcode },
5475     { VEX_W_TABLE (VEX_W_0FF5_P_2) },
5476   },
5477
5478   /* PREFIX_VEX_0FF6 */
5479   {
5480     { Bad_Opcode },
5481     { Bad_Opcode },
5482     { VEX_W_TABLE (VEX_W_0FF6_P_2) },
5483   },
5484
5485   /* PREFIX_VEX_0FF7 */
5486   {
5487     { Bad_Opcode },
5488     { Bad_Opcode },
5489     { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5490   },
5491
5492   /* PREFIX_VEX_0FF8 */
5493   {
5494     { Bad_Opcode },
5495     { Bad_Opcode },
5496     { VEX_W_TABLE (VEX_W_0FF8_P_2) },
5497   },
5498
5499   /* PREFIX_VEX_0FF9 */
5500   {
5501     { Bad_Opcode },
5502     { Bad_Opcode },
5503     { VEX_W_TABLE (VEX_W_0FF9_P_2) },
5504   },
5505
5506   /* PREFIX_VEX_0FFA */
5507   {
5508     { Bad_Opcode },
5509     { Bad_Opcode },
5510     { VEX_W_TABLE (VEX_W_0FFA_P_2) },
5511   },
5512
5513   /* PREFIX_VEX_0FFB */
5514   {
5515     { Bad_Opcode },
5516     { Bad_Opcode },
5517     { VEX_W_TABLE (VEX_W_0FFB_P_2) },
5518   },
5519
5520   /* PREFIX_VEX_0FFC */
5521   {
5522     { Bad_Opcode },
5523     { Bad_Opcode },
5524     { VEX_W_TABLE (VEX_W_0FFC_P_2) },
5525   },
5526
5527   /* PREFIX_VEX_0FFD */
5528   {
5529     { Bad_Opcode },
5530     { Bad_Opcode },
5531     { VEX_W_TABLE (VEX_W_0FFD_P_2) },
5532   },
5533
5534   /* PREFIX_VEX_0FFE */
5535   {
5536     { Bad_Opcode },
5537     { Bad_Opcode },
5538     { VEX_W_TABLE (VEX_W_0FFE_P_2) },
5539   },
5540
5541   /* PREFIX_VEX_0F3800 */
5542   {
5543     { Bad_Opcode },
5544     { Bad_Opcode },
5545     { VEX_W_TABLE (VEX_W_0F3800_P_2) },
5546   },
5547
5548   /* PREFIX_VEX_0F3801 */
5549   {
5550     { Bad_Opcode },
5551     { Bad_Opcode },
5552     { VEX_W_TABLE (VEX_W_0F3801_P_2) },
5553   },
5554
5555   /* PREFIX_VEX_0F3802 */
5556   {
5557     { Bad_Opcode },
5558     { Bad_Opcode },
5559     { VEX_W_TABLE (VEX_W_0F3802_P_2) },
5560   },
5561
5562   /* PREFIX_VEX_0F3803 */
5563   {
5564     { Bad_Opcode },
5565     { Bad_Opcode },
5566     { VEX_W_TABLE (VEX_W_0F3803_P_2) },
5567   },
5568
5569   /* PREFIX_VEX_0F3804 */
5570   {
5571     { Bad_Opcode },
5572     { Bad_Opcode },
5573     { VEX_W_TABLE (VEX_W_0F3804_P_2) },
5574   },
5575
5576   /* PREFIX_VEX_0F3805 */
5577   {
5578     { Bad_Opcode },
5579     { Bad_Opcode },
5580     { VEX_W_TABLE (VEX_W_0F3805_P_2) },
5581   },
5582
5583   /* PREFIX_VEX_0F3806 */
5584   {
5585     { Bad_Opcode },
5586     { Bad_Opcode },
5587     { VEX_W_TABLE (VEX_W_0F3806_P_2) },
5588   },
5589
5590   /* PREFIX_VEX_0F3807 */
5591   {
5592     { Bad_Opcode },
5593     { Bad_Opcode },
5594     { VEX_W_TABLE (VEX_W_0F3807_P_2) },
5595   },
5596
5597   /* PREFIX_VEX_0F3808 */
5598   {
5599     { Bad_Opcode },
5600     { Bad_Opcode },
5601     { VEX_W_TABLE (VEX_W_0F3808_P_2) },
5602   },
5603
5604   /* PREFIX_VEX_0F3809 */
5605   {
5606     { Bad_Opcode },
5607     { Bad_Opcode },
5608     { VEX_W_TABLE (VEX_W_0F3809_P_2) },
5609   },
5610
5611   /* PREFIX_VEX_0F380A */
5612   {
5613     { Bad_Opcode },
5614     { Bad_Opcode },
5615     { VEX_W_TABLE (VEX_W_0F380A_P_2) },
5616   },
5617
5618   /* PREFIX_VEX_0F380B */
5619   {
5620     { Bad_Opcode },
5621     { Bad_Opcode },
5622     { VEX_W_TABLE (VEX_W_0F380B_P_2) },
5623   },
5624
5625   /* PREFIX_VEX_0F380C */
5626   {
5627     { Bad_Opcode },
5628     { Bad_Opcode },
5629     { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5630   },
5631
5632   /* PREFIX_VEX_0F380D */
5633   {
5634     { Bad_Opcode },
5635     { Bad_Opcode },
5636     { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5637   },
5638
5639   /* PREFIX_VEX_0F380E */
5640   {
5641     { Bad_Opcode },
5642     { Bad_Opcode },
5643     { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5644   },
5645
5646   /* PREFIX_VEX_0F380F */
5647   {
5648     { Bad_Opcode },
5649     { Bad_Opcode },
5650     { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5651   },
5652
5653   /* PREFIX_VEX_0F3813 */
5654   {
5655     { Bad_Opcode },
5656     { Bad_Opcode },
5657     { "vcvtph2ps", { XM, EXxmmq }, 0 },
5658   },
5659
5660   /* PREFIX_VEX_0F3816 */
5661   {
5662     { Bad_Opcode },
5663     { Bad_Opcode },
5664     { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5665   },
5666
5667   /* PREFIX_VEX_0F3817 */
5668   {
5669     { Bad_Opcode },
5670     { Bad_Opcode },
5671     { VEX_W_TABLE (VEX_W_0F3817_P_2) },
5672   },
5673
5674   /* PREFIX_VEX_0F3818 */
5675   {
5676     { Bad_Opcode },
5677     { Bad_Opcode },
5678     { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5679   },
5680
5681   /* PREFIX_VEX_0F3819 */
5682   {
5683     { Bad_Opcode },
5684     { Bad_Opcode },
5685     { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5686   },
5687
5688   /* PREFIX_VEX_0F381A */
5689   {
5690     { Bad_Opcode },
5691     { Bad_Opcode },
5692     { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5693   },
5694
5695   /* PREFIX_VEX_0F381C */
5696   {
5697     { Bad_Opcode },
5698     { Bad_Opcode },
5699     { VEX_W_TABLE (VEX_W_0F381C_P_2) },
5700   },
5701
5702   /* PREFIX_VEX_0F381D */
5703   {
5704     { Bad_Opcode },
5705     { Bad_Opcode },
5706     { VEX_W_TABLE (VEX_W_0F381D_P_2) },
5707   },
5708
5709   /* PREFIX_VEX_0F381E */
5710   {
5711     { Bad_Opcode },
5712     { Bad_Opcode },
5713     { VEX_W_TABLE (VEX_W_0F381E_P_2) },
5714   },
5715
5716   /* PREFIX_VEX_0F3820 */
5717   {
5718     { Bad_Opcode },
5719     { Bad_Opcode },
5720     { VEX_W_TABLE (VEX_W_0F3820_P_2) },
5721   },
5722
5723   /* PREFIX_VEX_0F3821 */
5724   {
5725     { Bad_Opcode },
5726     { Bad_Opcode },
5727     { VEX_W_TABLE (VEX_W_0F3821_P_2) },
5728   },
5729
5730   /* PREFIX_VEX_0F3822 */
5731   {
5732     { Bad_Opcode },
5733     { Bad_Opcode },
5734     { VEX_W_TABLE (VEX_W_0F3822_P_2) },
5735   },
5736
5737   /* PREFIX_VEX_0F3823 */
5738   {
5739     { Bad_Opcode },
5740     { Bad_Opcode },
5741     { VEX_W_TABLE (VEX_W_0F3823_P_2) },
5742   },
5743
5744   /* PREFIX_VEX_0F3824 */
5745   {
5746     { Bad_Opcode },
5747     { Bad_Opcode },
5748     { VEX_W_TABLE (VEX_W_0F3824_P_2) },
5749   },
5750
5751   /* PREFIX_VEX_0F3825 */
5752   {
5753     { Bad_Opcode },
5754     { Bad_Opcode },
5755     { VEX_W_TABLE (VEX_W_0F3825_P_2) },
5756   },
5757
5758   /* PREFIX_VEX_0F3828 */
5759   {
5760     { Bad_Opcode },
5761     { Bad_Opcode },
5762     { VEX_W_TABLE (VEX_W_0F3828_P_2) },
5763   },
5764
5765   /* PREFIX_VEX_0F3829 */
5766   {
5767     { Bad_Opcode },
5768     { Bad_Opcode },
5769     { VEX_W_TABLE (VEX_W_0F3829_P_2) },
5770   },
5771
5772   /* PREFIX_VEX_0F382A */
5773   {
5774     { Bad_Opcode },
5775     { Bad_Opcode },
5776     { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5777   },
5778
5779   /* PREFIX_VEX_0F382B */
5780   {
5781     { Bad_Opcode },
5782     { Bad_Opcode },
5783     { VEX_W_TABLE (VEX_W_0F382B_P_2) },
5784   },
5785
5786   /* PREFIX_VEX_0F382C */
5787   {
5788     { Bad_Opcode },
5789     { Bad_Opcode },
5790      { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5791   },
5792
5793   /* PREFIX_VEX_0F382D */
5794   {
5795     { Bad_Opcode },
5796     { Bad_Opcode },
5797      { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5798   },
5799
5800   /* PREFIX_VEX_0F382E */
5801   {
5802     { Bad_Opcode },
5803     { Bad_Opcode },
5804      { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5805   },
5806
5807   /* PREFIX_VEX_0F382F */
5808   {
5809     { Bad_Opcode },
5810     { Bad_Opcode },
5811      { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5812   },
5813
5814   /* PREFIX_VEX_0F3830 */
5815   {
5816     { Bad_Opcode },
5817     { Bad_Opcode },
5818     { VEX_W_TABLE (VEX_W_0F3830_P_2) },
5819   },
5820
5821   /* PREFIX_VEX_0F3831 */
5822   {
5823     { Bad_Opcode },
5824     { Bad_Opcode },
5825     { VEX_W_TABLE (VEX_W_0F3831_P_2) },
5826   },
5827
5828   /* PREFIX_VEX_0F3832 */
5829   {
5830     { Bad_Opcode },
5831     { Bad_Opcode },
5832     { VEX_W_TABLE (VEX_W_0F3832_P_2) },
5833   },
5834
5835   /* PREFIX_VEX_0F3833 */
5836   {
5837     { Bad_Opcode },
5838     { Bad_Opcode },
5839     { VEX_W_TABLE (VEX_W_0F3833_P_2) },
5840   },
5841
5842   /* PREFIX_VEX_0F3834 */
5843   {
5844     { Bad_Opcode },
5845     { Bad_Opcode },
5846     { VEX_W_TABLE (VEX_W_0F3834_P_2) },
5847   },
5848
5849   /* PREFIX_VEX_0F3835 */
5850   {
5851     { Bad_Opcode },
5852     { Bad_Opcode },
5853     { VEX_W_TABLE (VEX_W_0F3835_P_2) },
5854   },
5855
5856   /* PREFIX_VEX_0F3836 */
5857   {
5858     { Bad_Opcode },
5859     { Bad_Opcode },
5860     { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5861   },
5862
5863   /* PREFIX_VEX_0F3837 */
5864   {
5865     { Bad_Opcode },
5866     { Bad_Opcode },
5867     { VEX_W_TABLE (VEX_W_0F3837_P_2) },
5868   },
5869
5870   /* PREFIX_VEX_0F3838 */
5871   {
5872     { Bad_Opcode },
5873     { Bad_Opcode },
5874     { VEX_W_TABLE (VEX_W_0F3838_P_2) },
5875   },
5876
5877   /* PREFIX_VEX_0F3839 */
5878   {
5879     { Bad_Opcode },
5880     { Bad_Opcode },
5881     { VEX_W_TABLE (VEX_W_0F3839_P_2) },
5882   },
5883
5884   /* PREFIX_VEX_0F383A */
5885   {
5886     { Bad_Opcode },
5887     { Bad_Opcode },
5888     { VEX_W_TABLE (VEX_W_0F383A_P_2) },
5889   },
5890
5891   /* PREFIX_VEX_0F383B */
5892   {
5893     { Bad_Opcode },
5894     { Bad_Opcode },
5895     { VEX_W_TABLE (VEX_W_0F383B_P_2) },
5896   },
5897
5898   /* PREFIX_VEX_0F383C */
5899   {
5900     { Bad_Opcode },
5901     { Bad_Opcode },
5902     { VEX_W_TABLE (VEX_W_0F383C_P_2) },
5903   },
5904
5905   /* PREFIX_VEX_0F383D */
5906   {
5907     { Bad_Opcode },
5908     { Bad_Opcode },
5909     { VEX_W_TABLE (VEX_W_0F383D_P_2) },
5910   },
5911
5912   /* PREFIX_VEX_0F383E */
5913   {
5914     { Bad_Opcode },
5915     { Bad_Opcode },
5916     { VEX_W_TABLE (VEX_W_0F383E_P_2) },
5917   },
5918
5919   /* PREFIX_VEX_0F383F */
5920   {
5921     { Bad_Opcode },
5922     { Bad_Opcode },
5923     { VEX_W_TABLE (VEX_W_0F383F_P_2) },
5924   },
5925
5926   /* PREFIX_VEX_0F3840 */
5927   {
5928     { Bad_Opcode },
5929     { Bad_Opcode },
5930     { VEX_W_TABLE (VEX_W_0F3840_P_2) },
5931   },
5932
5933   /* PREFIX_VEX_0F3841 */
5934   {
5935     { Bad_Opcode },
5936     { Bad_Opcode },
5937     { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
5938   },
5939
5940   /* PREFIX_VEX_0F3845 */
5941   {
5942     { Bad_Opcode },
5943     { Bad_Opcode },
5944     { "vpsrlv%LW", { XM, Vex, EXx }, 0 },
5945   },
5946
5947   /* PREFIX_VEX_0F3846 */
5948   {
5949     { Bad_Opcode },
5950     { Bad_Opcode },
5951     { VEX_W_TABLE (VEX_W_0F3846_P_2) },
5952   },
5953
5954   /* PREFIX_VEX_0F3847 */
5955   {
5956     { Bad_Opcode },
5957     { Bad_Opcode },
5958     { "vpsllv%LW", { XM, Vex, EXx }, 0 },
5959   },
5960
5961   /* PREFIX_VEX_0F3858 */
5962   {
5963     { Bad_Opcode },
5964     { Bad_Opcode },
5965     { VEX_W_TABLE (VEX_W_0F3858_P_2) },
5966   },
5967
5968   /* PREFIX_VEX_0F3859 */
5969   {
5970     { Bad_Opcode },
5971     { Bad_Opcode },
5972     { VEX_W_TABLE (VEX_W_0F3859_P_2) },
5973   },
5974
5975   /* PREFIX_VEX_0F385A */
5976   {
5977     { Bad_Opcode },
5978     { Bad_Opcode },
5979     { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
5980   },
5981
5982   /* PREFIX_VEX_0F3878 */
5983   {
5984     { Bad_Opcode },
5985     { Bad_Opcode },
5986     { VEX_W_TABLE (VEX_W_0F3878_P_2) },
5987   },
5988
5989   /* PREFIX_VEX_0F3879 */
5990   {
5991     { Bad_Opcode },
5992     { Bad_Opcode },
5993     { VEX_W_TABLE (VEX_W_0F3879_P_2) },
5994   },
5995
5996   /* PREFIX_VEX_0F388C */
5997   {
5998     { Bad_Opcode },
5999     { Bad_Opcode },
6000     { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
6001   },
6002
6003   /* PREFIX_VEX_0F388E */
6004   {
6005     { Bad_Opcode },
6006     { Bad_Opcode },
6007     { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
6008   },
6009
6010   /* PREFIX_VEX_0F3890 */
6011   {
6012     { Bad_Opcode },
6013     { Bad_Opcode },
6014     { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 },
6015   },
6016
6017   /* PREFIX_VEX_0F3891 */
6018   {
6019     { Bad_Opcode },
6020     { Bad_Opcode },
6021     { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6022   },
6023
6024   /* PREFIX_VEX_0F3892 */
6025   {
6026     { Bad_Opcode },
6027     { Bad_Opcode },
6028     { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 },
6029   },
6030
6031   /* PREFIX_VEX_0F3893 */
6032   {
6033     { Bad_Opcode },
6034     { Bad_Opcode },
6035     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6036   },
6037
6038   /* PREFIX_VEX_0F3896 */
6039   {
6040     { Bad_Opcode },
6041     { Bad_Opcode },
6042     { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 },
6043   },
6044
6045   /* PREFIX_VEX_0F3897 */
6046   {
6047     { Bad_Opcode },
6048     { Bad_Opcode },
6049     { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 },
6050   },
6051
6052   /* PREFIX_VEX_0F3898 */
6053   {
6054     { Bad_Opcode },
6055     { Bad_Opcode },
6056     { "vfmadd132p%XW", { XM, Vex, EXx }, 0 },
6057   },
6058
6059   /* PREFIX_VEX_0F3899 */
6060   {
6061     { Bad_Opcode },
6062     { Bad_Opcode },
6063     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6064   },
6065
6066   /* PREFIX_VEX_0F389A */
6067   {
6068     { Bad_Opcode },
6069     { Bad_Opcode },
6070     { "vfmsub132p%XW", { XM, Vex, EXx }, 0 },
6071   },
6072
6073   /* PREFIX_VEX_0F389B */
6074   {
6075     { Bad_Opcode },
6076     { Bad_Opcode },
6077     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6078   },
6079
6080   /* PREFIX_VEX_0F389C */
6081   {
6082     { Bad_Opcode },
6083     { Bad_Opcode },
6084     { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 },
6085   },
6086
6087   /* PREFIX_VEX_0F389D */
6088   {
6089     { Bad_Opcode },
6090     { Bad_Opcode },
6091     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6092   },
6093
6094   /* PREFIX_VEX_0F389E */
6095   {
6096     { Bad_Opcode },
6097     { Bad_Opcode },
6098     { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 },
6099   },
6100
6101   /* PREFIX_VEX_0F389F */
6102   {
6103     { Bad_Opcode },
6104     { Bad_Opcode },
6105     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6106   },
6107
6108   /* PREFIX_VEX_0F38A6 */
6109   {
6110     { Bad_Opcode },
6111     { Bad_Opcode },
6112     { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 },
6113     { Bad_Opcode },
6114   },
6115
6116   /* PREFIX_VEX_0F38A7 */
6117   {
6118     { Bad_Opcode },
6119     { Bad_Opcode },
6120     { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 },
6121   },
6122
6123   /* PREFIX_VEX_0F38A8 */
6124   {
6125     { Bad_Opcode },
6126     { Bad_Opcode },
6127     { "vfmadd213p%XW", { XM, Vex, EXx }, 0 },
6128   },
6129
6130   /* PREFIX_VEX_0F38A9 */
6131   {
6132     { Bad_Opcode },
6133     { Bad_Opcode },
6134     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6135   },
6136
6137   /* PREFIX_VEX_0F38AA */
6138   {
6139     { Bad_Opcode },
6140     { Bad_Opcode },
6141     { "vfmsub213p%XW", { XM, Vex, EXx }, 0 },
6142   },
6143
6144   /* PREFIX_VEX_0F38AB */
6145   {
6146     { Bad_Opcode },
6147     { Bad_Opcode },
6148     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6149   },
6150
6151   /* PREFIX_VEX_0F38AC */
6152   {
6153     { Bad_Opcode },
6154     { Bad_Opcode },
6155     { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 },
6156   },
6157
6158   /* PREFIX_VEX_0F38AD */
6159   {
6160     { Bad_Opcode },
6161     { Bad_Opcode },
6162     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6163   },
6164
6165   /* PREFIX_VEX_0F38AE */
6166   {
6167     { Bad_Opcode },
6168     { Bad_Opcode },
6169     { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 },
6170   },
6171
6172   /* PREFIX_VEX_0F38AF */
6173   {
6174     { Bad_Opcode },
6175     { Bad_Opcode },
6176     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6177   },
6178
6179   /* PREFIX_VEX_0F38B6 */
6180   {
6181     { Bad_Opcode },
6182     { Bad_Opcode },
6183     { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 },
6184   },
6185
6186   /* PREFIX_VEX_0F38B7 */
6187   {
6188     { Bad_Opcode },
6189     { Bad_Opcode },
6190     { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 },
6191   },
6192
6193   /* PREFIX_VEX_0F38B8 */
6194   {
6195     { Bad_Opcode },
6196     { Bad_Opcode },
6197     { "vfmadd231p%XW", { XM, Vex, EXx }, 0 },
6198   },
6199
6200   /* PREFIX_VEX_0F38B9 */
6201   {
6202     { Bad_Opcode },
6203     { Bad_Opcode },
6204     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6205   },
6206
6207   /* PREFIX_VEX_0F38BA */
6208   {
6209     { Bad_Opcode },
6210     { Bad_Opcode },
6211     { "vfmsub231p%XW", { XM, Vex, EXx }, 0 },
6212   },
6213
6214   /* PREFIX_VEX_0F38BB */
6215   {
6216     { Bad_Opcode },
6217     { Bad_Opcode },
6218     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6219   },
6220
6221   /* PREFIX_VEX_0F38BC */
6222   {
6223     { Bad_Opcode },
6224     { Bad_Opcode },
6225     { "vfnmadd231p%XW", { XM, Vex, EXx }, 0 },
6226   },
6227
6228   /* PREFIX_VEX_0F38BD */
6229   {
6230     { Bad_Opcode },
6231     { Bad_Opcode },
6232     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6233   },
6234
6235   /* PREFIX_VEX_0F38BE */
6236   {
6237     { Bad_Opcode },
6238     { Bad_Opcode },
6239     { "vfnmsub231p%XW", { XM, Vex, EXx }, 0 },
6240   },
6241
6242   /* PREFIX_VEX_0F38BF */
6243   {
6244     { Bad_Opcode },
6245     { Bad_Opcode },
6246     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6247   },
6248
6249   /* PREFIX_VEX_0F38DB */
6250   {
6251     { Bad_Opcode },
6252     { Bad_Opcode },
6253     { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6254   },
6255
6256   /* PREFIX_VEX_0F38DC */
6257   {
6258     { Bad_Opcode },
6259     { Bad_Opcode },
6260     { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2) },
6261   },
6262
6263   /* PREFIX_VEX_0F38DD */
6264   {
6265     { Bad_Opcode },
6266     { Bad_Opcode },
6267     { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2) },
6268   },
6269
6270   /* PREFIX_VEX_0F38DE */
6271   {
6272     { Bad_Opcode },
6273     { Bad_Opcode },
6274     { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2) },
6275   },
6276
6277   /* PREFIX_VEX_0F38DF */
6278   {
6279     { Bad_Opcode },
6280     { Bad_Opcode },
6281     { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2) },
6282   },
6283
6284   /* PREFIX_VEX_0F38F2 */
6285   {
6286     { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6287   },
6288
6289   /* PREFIX_VEX_0F38F3_REG_1 */
6290   {
6291     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6292   },
6293
6294   /* PREFIX_VEX_0F38F3_REG_2 */
6295   {
6296     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6297   },
6298
6299   /* PREFIX_VEX_0F38F3_REG_3 */
6300   {
6301     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6302   },
6303
6304   /* PREFIX_VEX_0F38F5 */
6305   {
6306     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6307     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6308     { Bad_Opcode },
6309     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6310   },
6311
6312   /* PREFIX_VEX_0F38F6 */
6313   {
6314     { Bad_Opcode },
6315     { Bad_Opcode },
6316     { Bad_Opcode },
6317     { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6318   },
6319
6320   /* PREFIX_VEX_0F38F7 */
6321   {
6322     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6323     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6324     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6325     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6326   },
6327
6328   /* PREFIX_VEX_0F3A00 */
6329   {
6330     { Bad_Opcode },
6331     { Bad_Opcode },
6332     { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6333   },
6334
6335   /* PREFIX_VEX_0F3A01 */
6336   {
6337     { Bad_Opcode },
6338     { Bad_Opcode },
6339     { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6340   },
6341
6342   /* PREFIX_VEX_0F3A02 */
6343   {
6344     { Bad_Opcode },
6345     { Bad_Opcode },
6346     { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6347   },
6348
6349   /* PREFIX_VEX_0F3A04 */
6350   {
6351     { Bad_Opcode },
6352     { Bad_Opcode },
6353     { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6354   },
6355
6356   /* PREFIX_VEX_0F3A05 */
6357   {
6358     { Bad_Opcode },
6359     { Bad_Opcode },
6360     { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6361   },
6362
6363   /* PREFIX_VEX_0F3A06 */
6364   {
6365     { Bad_Opcode },
6366     { Bad_Opcode },
6367     { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6368   },
6369
6370   /* PREFIX_VEX_0F3A08 */
6371   {
6372     { Bad_Opcode },
6373     { Bad_Opcode },
6374     { VEX_W_TABLE (VEX_W_0F3A08_P_2) },
6375   },
6376
6377   /* PREFIX_VEX_0F3A09 */
6378   {
6379     { Bad_Opcode },
6380     { Bad_Opcode },
6381     { VEX_W_TABLE (VEX_W_0F3A09_P_2) },
6382   },
6383
6384   /* PREFIX_VEX_0F3A0A */
6385   {
6386     { Bad_Opcode },
6387     { Bad_Opcode },
6388     { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) },
6389   },
6390
6391   /* PREFIX_VEX_0F3A0B */
6392   {
6393     { Bad_Opcode },
6394     { Bad_Opcode },
6395     { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) },
6396   },
6397
6398   /* PREFIX_VEX_0F3A0C */
6399   {
6400     { Bad_Opcode },
6401     { Bad_Opcode },
6402     { VEX_W_TABLE (VEX_W_0F3A0C_P_2) },
6403   },
6404
6405   /* PREFIX_VEX_0F3A0D */
6406   {
6407     { Bad_Opcode },
6408     { Bad_Opcode },
6409     { VEX_W_TABLE (VEX_W_0F3A0D_P_2) },
6410   },
6411
6412   /* PREFIX_VEX_0F3A0E */
6413   {
6414     { Bad_Opcode },
6415     { Bad_Opcode },
6416     { VEX_W_TABLE (VEX_W_0F3A0E_P_2) },
6417   },
6418
6419   /* PREFIX_VEX_0F3A0F */
6420   {
6421     { Bad_Opcode },
6422     { Bad_Opcode },
6423     { VEX_W_TABLE (VEX_W_0F3A0F_P_2) },
6424   },
6425
6426   /* PREFIX_VEX_0F3A14 */
6427   {
6428     { Bad_Opcode },
6429     { Bad_Opcode },
6430     { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6431   },
6432
6433   /* PREFIX_VEX_0F3A15 */
6434   {
6435     { Bad_Opcode },
6436     { Bad_Opcode },
6437     { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6438   },
6439
6440   /* PREFIX_VEX_0F3A16 */
6441   {
6442     { Bad_Opcode },
6443     { Bad_Opcode },
6444     { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6445   },
6446
6447   /* PREFIX_VEX_0F3A17 */
6448   {
6449     { Bad_Opcode },
6450     { Bad_Opcode },
6451     { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6452   },
6453
6454   /* PREFIX_VEX_0F3A18 */
6455   {
6456     { Bad_Opcode },
6457     { Bad_Opcode },
6458     { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6459   },
6460
6461   /* PREFIX_VEX_0F3A19 */
6462   {
6463     { Bad_Opcode },
6464     { Bad_Opcode },
6465     { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6466   },
6467
6468   /* PREFIX_VEX_0F3A1D */
6469   {
6470     { Bad_Opcode },
6471     { Bad_Opcode },
6472     { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 },
6473   },
6474
6475   /* PREFIX_VEX_0F3A20 */
6476   {
6477     { Bad_Opcode },
6478     { Bad_Opcode },
6479     { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6480   },
6481
6482   /* PREFIX_VEX_0F3A21 */
6483   {
6484     { Bad_Opcode },
6485     { Bad_Opcode },
6486     { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6487   },
6488
6489   /* PREFIX_VEX_0F3A22 */
6490   {
6491     { Bad_Opcode },
6492     { Bad_Opcode },
6493     { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6494   },
6495
6496   /* PREFIX_VEX_0F3A30 */
6497   {
6498     { Bad_Opcode },
6499     { Bad_Opcode },
6500     { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6501   },
6502
6503   /* PREFIX_VEX_0F3A31 */
6504   {
6505     { Bad_Opcode },
6506     { Bad_Opcode },
6507     { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6508   },
6509
6510   /* PREFIX_VEX_0F3A32 */
6511   {
6512     { Bad_Opcode },
6513     { Bad_Opcode },
6514     { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6515   },
6516
6517   /* PREFIX_VEX_0F3A33 */
6518   {
6519     { Bad_Opcode },
6520     { Bad_Opcode },
6521     { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6522   },
6523
6524   /* PREFIX_VEX_0F3A38 */
6525   {
6526     { Bad_Opcode },
6527     { Bad_Opcode },
6528     { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6529   },
6530
6531   /* PREFIX_VEX_0F3A39 */
6532   {
6533     { Bad_Opcode },
6534     { Bad_Opcode },
6535     { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6536   },
6537
6538   /* PREFIX_VEX_0F3A40 */
6539   {
6540     { Bad_Opcode },
6541     { Bad_Opcode },
6542     { VEX_W_TABLE (VEX_W_0F3A40_P_2) },
6543   },
6544
6545   /* PREFIX_VEX_0F3A41 */
6546   {
6547     { Bad_Opcode },
6548     { Bad_Opcode },
6549     { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6550   },
6551
6552   /* PREFIX_VEX_0F3A42 */
6553   {
6554     { Bad_Opcode },
6555     { Bad_Opcode },
6556     { VEX_W_TABLE (VEX_W_0F3A42_P_2) },
6557   },
6558
6559   /* PREFIX_VEX_0F3A44 */
6560   {
6561     { Bad_Opcode },
6562     { Bad_Opcode },
6563     { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2) },
6564   },
6565
6566   /* PREFIX_VEX_0F3A46 */
6567   {
6568     { Bad_Opcode },
6569     { Bad_Opcode },
6570     { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6571   },
6572
6573   /* PREFIX_VEX_0F3A48 */
6574   {
6575     { Bad_Opcode },
6576     { Bad_Opcode },
6577     { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6578   },
6579
6580   /* PREFIX_VEX_0F3A49 */
6581   {
6582     { Bad_Opcode },
6583     { Bad_Opcode },
6584     { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6585   },
6586
6587   /* PREFIX_VEX_0F3A4A */
6588   {
6589     { Bad_Opcode },
6590     { Bad_Opcode },
6591     { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6592   },
6593
6594   /* PREFIX_VEX_0F3A4B */
6595   {
6596     { Bad_Opcode },
6597     { Bad_Opcode },
6598     { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6599   },
6600
6601   /* PREFIX_VEX_0F3A4C */
6602   {
6603     { Bad_Opcode },
6604     { Bad_Opcode },
6605     { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6606   },
6607
6608   /* PREFIX_VEX_0F3A5C */
6609   {
6610     { Bad_Opcode },
6611     { Bad_Opcode },
6612     { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6613   },
6614
6615   /* PREFIX_VEX_0F3A5D */
6616   {
6617     { Bad_Opcode },
6618     { Bad_Opcode },
6619     { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6620   },
6621
6622   /* PREFIX_VEX_0F3A5E */
6623   {
6624     { Bad_Opcode },
6625     { Bad_Opcode },
6626     { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6627   },
6628
6629   /* PREFIX_VEX_0F3A5F */
6630   {
6631     { Bad_Opcode },
6632     { Bad_Opcode },
6633     { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6634   },
6635
6636   /* PREFIX_VEX_0F3A60 */
6637   {
6638     { Bad_Opcode },
6639     { Bad_Opcode },
6640     { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6641     { Bad_Opcode },
6642   },
6643
6644   /* PREFIX_VEX_0F3A61 */
6645   {
6646     { Bad_Opcode },
6647     { Bad_Opcode },
6648     { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6649   },
6650
6651   /* PREFIX_VEX_0F3A62 */
6652   {
6653     { Bad_Opcode },
6654     { Bad_Opcode },
6655     { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6656   },
6657
6658   /* PREFIX_VEX_0F3A63 */
6659   {
6660     { Bad_Opcode },
6661     { Bad_Opcode },
6662     { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6663   },
6664
6665   /* PREFIX_VEX_0F3A68 */
6666   {
6667     { Bad_Opcode },
6668     { Bad_Opcode },
6669     { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6670   },
6671
6672   /* PREFIX_VEX_0F3A69 */
6673   {
6674     { Bad_Opcode },
6675     { Bad_Opcode },
6676     { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6677   },
6678
6679   /* PREFIX_VEX_0F3A6A */
6680   {
6681     { Bad_Opcode },
6682     { Bad_Opcode },
6683     { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6684   },
6685
6686   /* PREFIX_VEX_0F3A6B */
6687   {
6688     { Bad_Opcode },
6689     { Bad_Opcode },
6690     { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6691   },
6692
6693   /* PREFIX_VEX_0F3A6C */
6694   {
6695     { Bad_Opcode },
6696     { Bad_Opcode },
6697     { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6698   },
6699
6700   /* PREFIX_VEX_0F3A6D */
6701   {
6702     { Bad_Opcode },
6703     { Bad_Opcode },
6704     { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6705   },
6706
6707   /* PREFIX_VEX_0F3A6E */
6708   {
6709     { Bad_Opcode },
6710     { Bad_Opcode },
6711     { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6712   },
6713
6714   /* PREFIX_VEX_0F3A6F */
6715   {
6716     { Bad_Opcode },
6717     { Bad_Opcode },
6718     { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6719   },
6720
6721   /* PREFIX_VEX_0F3A78 */
6722   {
6723     { Bad_Opcode },
6724     { Bad_Opcode },
6725     { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6726   },
6727
6728   /* PREFIX_VEX_0F3A79 */
6729   {
6730     { Bad_Opcode },
6731     { Bad_Opcode },
6732     { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6733   },
6734
6735   /* PREFIX_VEX_0F3A7A */
6736   {
6737     { Bad_Opcode },
6738     { Bad_Opcode },
6739     { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6740   },
6741
6742   /* PREFIX_VEX_0F3A7B */
6743   {
6744     { Bad_Opcode },
6745     { Bad_Opcode },
6746     { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6747   },
6748
6749   /* PREFIX_VEX_0F3A7C */
6750   {
6751     { Bad_Opcode },
6752     { Bad_Opcode },
6753     { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6754     { Bad_Opcode },
6755   },
6756
6757   /* PREFIX_VEX_0F3A7D */
6758   {
6759     { Bad_Opcode },
6760     { Bad_Opcode },
6761     { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6762   },
6763
6764   /* PREFIX_VEX_0F3A7E */
6765   {
6766     { Bad_Opcode },
6767     { Bad_Opcode },
6768     { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6769   },
6770
6771   /* PREFIX_VEX_0F3A7F */
6772   {
6773     { Bad_Opcode },
6774     { Bad_Opcode },
6775     { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6776   },
6777
6778   /* PREFIX_VEX_0F3ADF */
6779   {
6780     { Bad_Opcode },
6781     { Bad_Opcode },
6782     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6783   },
6784
6785   /* PREFIX_VEX_0F3AF0 */
6786   {
6787     { Bad_Opcode },
6788     { Bad_Opcode },
6789     { Bad_Opcode },
6790     { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6791   },
6792
6793 #define NEED_PREFIX_TABLE
6794 #include "i386-dis-evex.h"
6795 #undef NEED_PREFIX_TABLE
6796 };
6797
6798 static const struct dis386 x86_64_table[][2] = {
6799   /* X86_64_06 */
6800   {
6801     { "pushP", { es }, 0 },
6802   },
6803
6804   /* X86_64_07 */
6805   {
6806     { "popP", { es }, 0 },
6807   },
6808
6809   /* X86_64_0D */
6810   {
6811     { "pushP", { cs }, 0 },
6812   },
6813
6814   /* X86_64_16 */
6815   {
6816     { "pushP", { ss }, 0 },
6817   },
6818
6819   /* X86_64_17 */
6820   {
6821     { "popP", { ss }, 0 },
6822   },
6823
6824   /* X86_64_1E */
6825   {
6826     { "pushP", { ds }, 0 },
6827   },
6828
6829   /* X86_64_1F */
6830   {
6831     { "popP", { ds }, 0 },
6832   },
6833
6834   /* X86_64_27 */
6835   {
6836     { "daa", { XX }, 0 },
6837   },
6838
6839   /* X86_64_2F */
6840   {
6841     { "das", { XX }, 0 },
6842   },
6843
6844   /* X86_64_37 */
6845   {
6846     { "aaa", { XX }, 0 },
6847   },
6848
6849   /* X86_64_3F */
6850   {
6851     { "aas", { XX }, 0 },
6852   },
6853
6854   /* X86_64_60 */
6855   {
6856     { "pushaP", { XX }, 0 },
6857   },
6858
6859   /* X86_64_61 */
6860   {
6861     { "popaP", { XX }, 0 },
6862   },
6863
6864   /* X86_64_62 */
6865   {
6866     { MOD_TABLE (MOD_62_32BIT) },
6867     { EVEX_TABLE (EVEX_0F) },
6868   },
6869
6870   /* X86_64_63 */
6871   {
6872     { "arpl", { Ew, Gw }, 0 },
6873     { "movs{lq|xd}", { Gv, Ed }, 0 },
6874   },
6875
6876   /* X86_64_6D */
6877   {
6878     { "ins{R|}", { Yzr, indirDX }, 0 },
6879     { "ins{G|}", { Yzr, indirDX }, 0 },
6880   },
6881
6882   /* X86_64_6F */
6883   {
6884     { "outs{R|}", { indirDXr, Xz }, 0 },
6885     { "outs{G|}", { indirDXr, Xz }, 0 },
6886   },
6887
6888   /* X86_64_82 */
6889   {
6890     /* Opcode 0x82 is an alias of of opcode 0x80 in 32-bit mode.  */
6891     { REG_TABLE (REG_80) },
6892   },
6893
6894   /* X86_64_9A */
6895   {
6896     { "Jcall{T|}", { Ap }, 0 },
6897   },
6898
6899   /* X86_64_C4 */
6900   {
6901     { MOD_TABLE (MOD_C4_32BIT) },
6902     { VEX_C4_TABLE (VEX_0F) },
6903   },
6904
6905   /* X86_64_C5 */
6906   {
6907     { MOD_TABLE (MOD_C5_32BIT) },
6908     { VEX_C5_TABLE (VEX_0F) },
6909   },
6910
6911   /* X86_64_CE */
6912   {
6913     { "into", { XX }, 0 },
6914   },
6915
6916   /* X86_64_D4 */
6917   {
6918     { "aam", { Ib }, 0 },
6919   },
6920
6921   /* X86_64_D5 */
6922   {
6923     { "aad", { Ib }, 0 },
6924   },
6925
6926   /* X86_64_E8 */
6927   {
6928     { "callP",          { Jv, BND }, 0 },
6929     { "call@",          { Jv, BND }, 0 }
6930   },
6931
6932   /* X86_64_E9 */
6933   {
6934     { "jmpP",           { Jv, BND }, 0 },
6935     { "jmp@",           { Jv, BND }, 0 }
6936   },
6937
6938   /* X86_64_EA */
6939   {
6940     { "Jjmp{T|}", { Ap }, 0 },
6941   },
6942
6943   /* X86_64_0F01_REG_0 */
6944   {
6945     { "sgdt{Q|IQ}", { M }, 0 },
6946     { "sgdt", { M }, 0 },
6947   },
6948
6949   /* X86_64_0F01_REG_1 */
6950   {
6951     { "sidt{Q|IQ}", { M }, 0 },
6952     { "sidt", { M }, 0 },
6953   },
6954
6955   /* X86_64_0F01_REG_2 */
6956   {
6957     { "lgdt{Q|Q}", { M }, 0 },
6958     { "lgdt", { M }, 0 },
6959   },
6960
6961   /* X86_64_0F01_REG_3 */
6962   {
6963     { "lidt{Q|Q}", { M }, 0 },
6964     { "lidt", { M }, 0 },
6965   },
6966 };
6967
6968 static const struct dis386 three_byte_table[][256] = {
6969
6970   /* THREE_BYTE_0F38 */
6971   {
6972     /* 00 */
6973     { "pshufb",         { MX, EM }, PREFIX_OPCODE },
6974     { "phaddw",         { MX, EM }, PREFIX_OPCODE },
6975     { "phaddd",         { MX, EM }, PREFIX_OPCODE },
6976     { "phaddsw",        { MX, EM }, PREFIX_OPCODE },
6977     { "pmaddubsw",      { MX, EM }, PREFIX_OPCODE },
6978     { "phsubw",         { MX, EM }, PREFIX_OPCODE },
6979     { "phsubd",         { MX, EM }, PREFIX_OPCODE },
6980     { "phsubsw",        { MX, EM }, PREFIX_OPCODE },
6981     /* 08 */
6982     { "psignb",         { MX, EM }, PREFIX_OPCODE },
6983     { "psignw",         { MX, EM }, PREFIX_OPCODE },
6984     { "psignd",         { MX, EM }, PREFIX_OPCODE },
6985     { "pmulhrsw",       { MX, EM }, PREFIX_OPCODE },
6986     { Bad_Opcode },
6987     { Bad_Opcode },
6988     { Bad_Opcode },
6989     { Bad_Opcode },
6990     /* 10 */
6991     { PREFIX_TABLE (PREFIX_0F3810) },
6992     { Bad_Opcode },
6993     { Bad_Opcode },
6994     { Bad_Opcode },
6995     { PREFIX_TABLE (PREFIX_0F3814) },
6996     { PREFIX_TABLE (PREFIX_0F3815) },
6997     { Bad_Opcode },
6998     { PREFIX_TABLE (PREFIX_0F3817) },
6999     /* 18 */
7000     { Bad_Opcode },
7001     { Bad_Opcode },
7002     { Bad_Opcode },
7003     { Bad_Opcode },
7004     { "pabsb",          { MX, EM }, PREFIX_OPCODE },
7005     { "pabsw",          { MX, EM }, PREFIX_OPCODE },
7006     { "pabsd",          { MX, EM }, PREFIX_OPCODE },
7007     { Bad_Opcode },
7008     /* 20 */
7009     { PREFIX_TABLE (PREFIX_0F3820) },
7010     { PREFIX_TABLE (PREFIX_0F3821) },
7011     { PREFIX_TABLE (PREFIX_0F3822) },
7012     { PREFIX_TABLE (PREFIX_0F3823) },
7013     { PREFIX_TABLE (PREFIX_0F3824) },
7014     { PREFIX_TABLE (PREFIX_0F3825) },
7015     { Bad_Opcode },
7016     { Bad_Opcode },
7017     /* 28 */
7018     { PREFIX_TABLE (PREFIX_0F3828) },
7019     { PREFIX_TABLE (PREFIX_0F3829) },
7020     { PREFIX_TABLE (PREFIX_0F382A) },
7021     { PREFIX_TABLE (PREFIX_0F382B) },
7022     { Bad_Opcode },
7023     { Bad_Opcode },
7024     { Bad_Opcode },
7025     { Bad_Opcode },
7026     /* 30 */
7027     { PREFIX_TABLE (PREFIX_0F3830) },
7028     { PREFIX_TABLE (PREFIX_0F3831) },
7029     { PREFIX_TABLE (PREFIX_0F3832) },
7030     { PREFIX_TABLE (PREFIX_0F3833) },
7031     { PREFIX_TABLE (PREFIX_0F3834) },
7032     { PREFIX_TABLE (PREFIX_0F3835) },
7033     { Bad_Opcode },
7034     { PREFIX_TABLE (PREFIX_0F3837) },
7035     /* 38 */
7036     { PREFIX_TABLE (PREFIX_0F3838) },
7037     { PREFIX_TABLE (PREFIX_0F3839) },
7038     { PREFIX_TABLE (PREFIX_0F383A) },
7039     { PREFIX_TABLE (PREFIX_0F383B) },
7040     { PREFIX_TABLE (PREFIX_0F383C) },
7041     { PREFIX_TABLE (PREFIX_0F383D) },
7042     { PREFIX_TABLE (PREFIX_0F383E) },
7043     { PREFIX_TABLE (PREFIX_0F383F) },
7044     /* 40 */
7045     { PREFIX_TABLE (PREFIX_0F3840) },
7046     { PREFIX_TABLE (PREFIX_0F3841) },
7047     { Bad_Opcode },
7048     { Bad_Opcode },
7049     { Bad_Opcode },
7050     { Bad_Opcode },
7051     { Bad_Opcode },
7052     { Bad_Opcode },
7053     /* 48 */
7054     { Bad_Opcode },
7055     { Bad_Opcode },
7056     { Bad_Opcode },
7057     { Bad_Opcode },
7058     { Bad_Opcode },
7059     { Bad_Opcode },
7060     { Bad_Opcode },
7061     { Bad_Opcode },
7062     /* 50 */
7063     { Bad_Opcode },
7064     { Bad_Opcode },
7065     { Bad_Opcode },
7066     { Bad_Opcode },
7067     { Bad_Opcode },
7068     { Bad_Opcode },
7069     { Bad_Opcode },
7070     { Bad_Opcode },
7071     /* 58 */
7072     { Bad_Opcode },
7073     { Bad_Opcode },
7074     { Bad_Opcode },
7075     { Bad_Opcode },
7076     { Bad_Opcode },
7077     { Bad_Opcode },
7078     { Bad_Opcode },
7079     { Bad_Opcode },
7080     /* 60 */
7081     { Bad_Opcode },
7082     { Bad_Opcode },
7083     { Bad_Opcode },
7084     { Bad_Opcode },
7085     { Bad_Opcode },
7086     { Bad_Opcode },
7087     { Bad_Opcode },
7088     { Bad_Opcode },
7089     /* 68 */
7090     { Bad_Opcode },
7091     { Bad_Opcode },
7092     { Bad_Opcode },
7093     { Bad_Opcode },
7094     { Bad_Opcode },
7095     { Bad_Opcode },
7096     { Bad_Opcode },
7097     { Bad_Opcode },
7098     /* 70 */
7099     { Bad_Opcode },
7100     { Bad_Opcode },
7101     { Bad_Opcode },
7102     { Bad_Opcode },
7103     { Bad_Opcode },
7104     { Bad_Opcode },
7105     { Bad_Opcode },
7106     { Bad_Opcode },
7107     /* 78 */
7108     { Bad_Opcode },
7109     { Bad_Opcode },
7110     { Bad_Opcode },
7111     { Bad_Opcode },
7112     { Bad_Opcode },
7113     { Bad_Opcode },
7114     { Bad_Opcode },
7115     { Bad_Opcode },
7116     /* 80 */
7117     { PREFIX_TABLE (PREFIX_0F3880) },
7118     { PREFIX_TABLE (PREFIX_0F3881) },
7119     { PREFIX_TABLE (PREFIX_0F3882) },
7120     { Bad_Opcode },
7121     { Bad_Opcode },
7122     { Bad_Opcode },
7123     { Bad_Opcode },
7124     { Bad_Opcode },
7125     /* 88 */
7126     { Bad_Opcode },
7127     { Bad_Opcode },
7128     { Bad_Opcode },
7129     { Bad_Opcode },
7130     { Bad_Opcode },
7131     { Bad_Opcode },
7132     { Bad_Opcode },
7133     { Bad_Opcode },
7134     /* 90 */
7135     { Bad_Opcode },
7136     { Bad_Opcode },
7137     { Bad_Opcode },
7138     { Bad_Opcode },
7139     { Bad_Opcode },
7140     { Bad_Opcode },
7141     { Bad_Opcode },
7142     { Bad_Opcode },
7143     /* 98 */
7144     { Bad_Opcode },
7145     { Bad_Opcode },
7146     { Bad_Opcode },
7147     { Bad_Opcode },
7148     { Bad_Opcode },
7149     { Bad_Opcode },
7150     { Bad_Opcode },
7151     { Bad_Opcode },
7152     /* a0 */
7153     { Bad_Opcode },
7154     { Bad_Opcode },
7155     { Bad_Opcode },
7156     { Bad_Opcode },
7157     { Bad_Opcode },
7158     { Bad_Opcode },
7159     { Bad_Opcode },
7160     { Bad_Opcode },
7161     /* a8 */
7162     { Bad_Opcode },
7163     { Bad_Opcode },
7164     { Bad_Opcode },
7165     { Bad_Opcode },
7166     { Bad_Opcode },
7167     { Bad_Opcode },
7168     { Bad_Opcode },
7169     { Bad_Opcode },
7170     /* b0 */
7171     { Bad_Opcode },
7172     { Bad_Opcode },
7173     { Bad_Opcode },
7174     { Bad_Opcode },
7175     { Bad_Opcode },
7176     { Bad_Opcode },
7177     { Bad_Opcode },
7178     { Bad_Opcode },
7179     /* b8 */
7180     { Bad_Opcode },
7181     { Bad_Opcode },
7182     { Bad_Opcode },
7183     { Bad_Opcode },
7184     { Bad_Opcode },
7185     { Bad_Opcode },
7186     { Bad_Opcode },
7187     { Bad_Opcode },
7188     /* c0 */
7189     { Bad_Opcode },
7190     { Bad_Opcode },
7191     { Bad_Opcode },
7192     { Bad_Opcode },
7193     { Bad_Opcode },
7194     { Bad_Opcode },
7195     { Bad_Opcode },
7196     { Bad_Opcode },
7197     /* c8 */
7198     { PREFIX_TABLE (PREFIX_0F38C8) },
7199     { PREFIX_TABLE (PREFIX_0F38C9) },
7200     { PREFIX_TABLE (PREFIX_0F38CA) },
7201     { PREFIX_TABLE (PREFIX_0F38CB) },
7202     { PREFIX_TABLE (PREFIX_0F38CC) },
7203     { PREFIX_TABLE (PREFIX_0F38CD) },
7204     { Bad_Opcode },
7205     { Bad_Opcode },
7206     /* d0 */
7207     { Bad_Opcode },
7208     { Bad_Opcode },
7209     { Bad_Opcode },
7210     { Bad_Opcode },
7211     { Bad_Opcode },
7212     { Bad_Opcode },
7213     { Bad_Opcode },
7214     { Bad_Opcode },
7215     /* d8 */
7216     { Bad_Opcode },
7217     { Bad_Opcode },
7218     { Bad_Opcode },
7219     { PREFIX_TABLE (PREFIX_0F38DB) },
7220     { PREFIX_TABLE (PREFIX_0F38DC) },
7221     { PREFIX_TABLE (PREFIX_0F38DD) },
7222     { PREFIX_TABLE (PREFIX_0F38DE) },
7223     { PREFIX_TABLE (PREFIX_0F38DF) },
7224     /* e0 */
7225     { Bad_Opcode },
7226     { Bad_Opcode },
7227     { Bad_Opcode },
7228     { Bad_Opcode },
7229     { Bad_Opcode },
7230     { Bad_Opcode },
7231     { Bad_Opcode },
7232     { Bad_Opcode },
7233     /* e8 */
7234     { Bad_Opcode },
7235     { Bad_Opcode },
7236     { Bad_Opcode },
7237     { Bad_Opcode },
7238     { Bad_Opcode },
7239     { Bad_Opcode },
7240     { Bad_Opcode },
7241     { Bad_Opcode },
7242     /* f0 */
7243     { PREFIX_TABLE (PREFIX_0F38F0) },
7244     { PREFIX_TABLE (PREFIX_0F38F1) },
7245     { Bad_Opcode },
7246     { Bad_Opcode },
7247     { Bad_Opcode },
7248     { Bad_Opcode },
7249     { PREFIX_TABLE (PREFIX_0F38F6) },
7250     { Bad_Opcode },
7251     /* f8 */
7252     { Bad_Opcode },
7253     { Bad_Opcode },
7254     { Bad_Opcode },
7255     { Bad_Opcode },
7256     { Bad_Opcode },
7257     { Bad_Opcode },
7258     { Bad_Opcode },
7259     { Bad_Opcode },
7260   },
7261   /* THREE_BYTE_0F3A */
7262   {
7263     /* 00 */
7264     { Bad_Opcode },
7265     { Bad_Opcode },
7266     { Bad_Opcode },
7267     { Bad_Opcode },
7268     { Bad_Opcode },
7269     { Bad_Opcode },
7270     { Bad_Opcode },
7271     { Bad_Opcode },
7272     /* 08 */
7273     { PREFIX_TABLE (PREFIX_0F3A08) },
7274     { PREFIX_TABLE (PREFIX_0F3A09) },
7275     { PREFIX_TABLE (PREFIX_0F3A0A) },
7276     { PREFIX_TABLE (PREFIX_0F3A0B) },
7277     { PREFIX_TABLE (PREFIX_0F3A0C) },
7278     { PREFIX_TABLE (PREFIX_0F3A0D) },
7279     { PREFIX_TABLE (PREFIX_0F3A0E) },
7280     { "palignr",        { MX, EM, Ib }, PREFIX_OPCODE },
7281     /* 10 */
7282     { Bad_Opcode },
7283     { Bad_Opcode },
7284     { Bad_Opcode },
7285     { Bad_Opcode },
7286     { PREFIX_TABLE (PREFIX_0F3A14) },
7287     { PREFIX_TABLE (PREFIX_0F3A15) },
7288     { PREFIX_TABLE (PREFIX_0F3A16) },
7289     { PREFIX_TABLE (PREFIX_0F3A17) },
7290     /* 18 */
7291     { Bad_Opcode },
7292     { Bad_Opcode },
7293     { Bad_Opcode },
7294     { Bad_Opcode },
7295     { Bad_Opcode },
7296     { Bad_Opcode },
7297     { Bad_Opcode },
7298     { Bad_Opcode },
7299     /* 20 */
7300     { PREFIX_TABLE (PREFIX_0F3A20) },
7301     { PREFIX_TABLE (PREFIX_0F3A21) },
7302     { PREFIX_TABLE (PREFIX_0F3A22) },
7303     { Bad_Opcode },
7304     { Bad_Opcode },
7305     { Bad_Opcode },
7306     { Bad_Opcode },
7307     { Bad_Opcode },
7308     /* 28 */
7309     { Bad_Opcode },
7310     { Bad_Opcode },
7311     { Bad_Opcode },
7312     { Bad_Opcode },
7313     { Bad_Opcode },
7314     { Bad_Opcode },
7315     { Bad_Opcode },
7316     { Bad_Opcode },
7317     /* 30 */
7318     { Bad_Opcode },
7319     { Bad_Opcode },
7320     { Bad_Opcode },
7321     { Bad_Opcode },
7322     { Bad_Opcode },
7323     { Bad_Opcode },
7324     { Bad_Opcode },
7325     { Bad_Opcode },
7326     /* 38 */
7327     { Bad_Opcode },
7328     { Bad_Opcode },
7329     { Bad_Opcode },
7330     { Bad_Opcode },
7331     { Bad_Opcode },
7332     { Bad_Opcode },
7333     { Bad_Opcode },
7334     { Bad_Opcode },
7335     /* 40 */
7336     { PREFIX_TABLE (PREFIX_0F3A40) },
7337     { PREFIX_TABLE (PREFIX_0F3A41) },
7338     { PREFIX_TABLE (PREFIX_0F3A42) },
7339     { Bad_Opcode },
7340     { PREFIX_TABLE (PREFIX_0F3A44) },
7341     { Bad_Opcode },
7342     { Bad_Opcode },
7343     { Bad_Opcode },
7344     /* 48 */
7345     { Bad_Opcode },
7346     { Bad_Opcode },
7347     { Bad_Opcode },
7348     { Bad_Opcode },
7349     { Bad_Opcode },
7350     { Bad_Opcode },
7351     { Bad_Opcode },
7352     { Bad_Opcode },
7353     /* 50 */
7354     { Bad_Opcode },
7355     { Bad_Opcode },
7356     { Bad_Opcode },
7357     { Bad_Opcode },
7358     { Bad_Opcode },
7359     { Bad_Opcode },
7360     { Bad_Opcode },
7361     { Bad_Opcode },
7362     /* 58 */
7363     { Bad_Opcode },
7364     { Bad_Opcode },
7365     { Bad_Opcode },
7366     { Bad_Opcode },
7367     { Bad_Opcode },
7368     { Bad_Opcode },
7369     { Bad_Opcode },
7370     { Bad_Opcode },
7371     /* 60 */
7372     { PREFIX_TABLE (PREFIX_0F3A60) },
7373     { PREFIX_TABLE (PREFIX_0F3A61) },
7374     { PREFIX_TABLE (PREFIX_0F3A62) },
7375     { PREFIX_TABLE (PREFIX_0F3A63) },
7376     { Bad_Opcode },
7377     { Bad_Opcode },
7378     { Bad_Opcode },
7379     { Bad_Opcode },
7380     /* 68 */
7381     { Bad_Opcode },
7382     { Bad_Opcode },
7383     { Bad_Opcode },
7384     { Bad_Opcode },
7385     { Bad_Opcode },
7386     { Bad_Opcode },
7387     { Bad_Opcode },
7388     { Bad_Opcode },
7389     /* 70 */
7390     { Bad_Opcode },
7391     { Bad_Opcode },
7392     { Bad_Opcode },
7393     { Bad_Opcode },
7394     { Bad_Opcode },
7395     { Bad_Opcode },
7396     { Bad_Opcode },
7397     { Bad_Opcode },
7398     /* 78 */
7399     { Bad_Opcode },
7400     { Bad_Opcode },
7401     { Bad_Opcode },
7402     { Bad_Opcode },
7403     { Bad_Opcode },
7404     { Bad_Opcode },
7405     { Bad_Opcode },
7406     { Bad_Opcode },
7407     /* 80 */
7408     { Bad_Opcode },
7409     { Bad_Opcode },
7410     { Bad_Opcode },
7411     { Bad_Opcode },
7412     { Bad_Opcode },
7413     { Bad_Opcode },
7414     { Bad_Opcode },
7415     { Bad_Opcode },
7416     /* 88 */
7417     { Bad_Opcode },
7418     { Bad_Opcode },
7419     { Bad_Opcode },
7420     { Bad_Opcode },
7421     { Bad_Opcode },
7422     { Bad_Opcode },
7423     { Bad_Opcode },
7424     { Bad_Opcode },
7425     /* 90 */
7426     { Bad_Opcode },
7427     { Bad_Opcode },
7428     { Bad_Opcode },
7429     { Bad_Opcode },
7430     { Bad_Opcode },
7431     { Bad_Opcode },
7432     { Bad_Opcode },
7433     { Bad_Opcode },
7434     /* 98 */
7435     { Bad_Opcode },
7436     { Bad_Opcode },
7437     { Bad_Opcode },
7438     { Bad_Opcode },
7439     { Bad_Opcode },
7440     { Bad_Opcode },
7441     { Bad_Opcode },
7442     { Bad_Opcode },
7443     /* a0 */
7444     { Bad_Opcode },
7445     { Bad_Opcode },
7446     { Bad_Opcode },
7447     { Bad_Opcode },
7448     { Bad_Opcode },
7449     { Bad_Opcode },
7450     { Bad_Opcode },
7451     { Bad_Opcode },
7452     /* a8 */
7453     { Bad_Opcode },
7454     { Bad_Opcode },
7455     { Bad_Opcode },
7456     { Bad_Opcode },
7457     { Bad_Opcode },
7458     { Bad_Opcode },
7459     { Bad_Opcode },
7460     { Bad_Opcode },
7461     /* b0 */
7462     { Bad_Opcode },
7463     { Bad_Opcode },
7464     { Bad_Opcode },
7465     { Bad_Opcode },
7466     { Bad_Opcode },
7467     { Bad_Opcode },
7468     { Bad_Opcode },
7469     { Bad_Opcode },
7470     /* b8 */
7471     { Bad_Opcode },
7472     { Bad_Opcode },
7473     { Bad_Opcode },
7474     { Bad_Opcode },
7475     { Bad_Opcode },
7476     { Bad_Opcode },
7477     { Bad_Opcode },
7478     { Bad_Opcode },
7479     /* c0 */
7480     { Bad_Opcode },
7481     { Bad_Opcode },
7482     { Bad_Opcode },
7483     { Bad_Opcode },
7484     { Bad_Opcode },
7485     { Bad_Opcode },
7486     { Bad_Opcode },
7487     { Bad_Opcode },
7488     /* c8 */
7489     { Bad_Opcode },
7490     { Bad_Opcode },
7491     { Bad_Opcode },
7492     { Bad_Opcode },
7493     { PREFIX_TABLE (PREFIX_0F3ACC) },
7494     { Bad_Opcode },
7495     { Bad_Opcode },
7496     { Bad_Opcode },
7497     /* d0 */
7498     { Bad_Opcode },
7499     { Bad_Opcode },
7500     { Bad_Opcode },
7501     { Bad_Opcode },
7502     { Bad_Opcode },
7503     { Bad_Opcode },
7504     { Bad_Opcode },
7505     { Bad_Opcode },
7506     /* d8 */
7507     { Bad_Opcode },
7508     { Bad_Opcode },
7509     { Bad_Opcode },
7510     { Bad_Opcode },
7511     { Bad_Opcode },
7512     { Bad_Opcode },
7513     { Bad_Opcode },
7514     { PREFIX_TABLE (PREFIX_0F3ADF) },
7515     /* e0 */
7516     { Bad_Opcode },
7517     { Bad_Opcode },
7518     { Bad_Opcode },
7519     { Bad_Opcode },
7520     { Bad_Opcode },
7521     { Bad_Opcode },
7522     { Bad_Opcode },
7523     { Bad_Opcode },
7524     /* e8 */
7525     { Bad_Opcode },
7526     { Bad_Opcode },
7527     { Bad_Opcode },
7528     { Bad_Opcode },
7529     { Bad_Opcode },
7530     { Bad_Opcode },
7531     { Bad_Opcode },
7532     { Bad_Opcode },
7533     /* f0 */
7534     { Bad_Opcode },
7535     { Bad_Opcode },
7536     { Bad_Opcode },
7537     { Bad_Opcode },
7538     { Bad_Opcode },
7539     { Bad_Opcode },
7540     { Bad_Opcode },
7541     { Bad_Opcode },
7542     /* f8 */
7543     { Bad_Opcode },
7544     { Bad_Opcode },
7545     { Bad_Opcode },
7546     { Bad_Opcode },
7547     { Bad_Opcode },
7548     { Bad_Opcode },
7549     { Bad_Opcode },
7550     { Bad_Opcode },
7551   },
7552 };
7553
7554 static const struct dis386 xop_table[][256] = {
7555   /* XOP_08 */
7556   {
7557     /* 00 */
7558     { Bad_Opcode },
7559     { Bad_Opcode },
7560     { Bad_Opcode },
7561     { Bad_Opcode },
7562     { Bad_Opcode },
7563     { Bad_Opcode },
7564     { Bad_Opcode },
7565     { Bad_Opcode },
7566     /* 08 */
7567     { Bad_Opcode },
7568     { Bad_Opcode },
7569     { Bad_Opcode },
7570     { Bad_Opcode },
7571     { Bad_Opcode },
7572     { Bad_Opcode },
7573     { Bad_Opcode },
7574     { Bad_Opcode },
7575     /* 10 */
7576     { Bad_Opcode },
7577     { Bad_Opcode },
7578     { Bad_Opcode },
7579     { Bad_Opcode },
7580     { Bad_Opcode },
7581     { Bad_Opcode },
7582     { Bad_Opcode },
7583     { Bad_Opcode },
7584     /* 18 */
7585     { Bad_Opcode },
7586     { Bad_Opcode },
7587     { Bad_Opcode },
7588     { Bad_Opcode },
7589     { Bad_Opcode },
7590     { Bad_Opcode },
7591     { Bad_Opcode },
7592     { Bad_Opcode },
7593     /* 20 */
7594     { Bad_Opcode },
7595     { Bad_Opcode },
7596     { Bad_Opcode },
7597     { Bad_Opcode },
7598     { Bad_Opcode },
7599     { Bad_Opcode },
7600     { Bad_Opcode },
7601     { Bad_Opcode },
7602     /* 28 */
7603     { Bad_Opcode },
7604     { Bad_Opcode },
7605     { Bad_Opcode },
7606     { Bad_Opcode },
7607     { Bad_Opcode },
7608     { Bad_Opcode },
7609     { Bad_Opcode },
7610     { Bad_Opcode },
7611     /* 30 */
7612     { Bad_Opcode },
7613     { Bad_Opcode },
7614     { Bad_Opcode },
7615     { Bad_Opcode },
7616     { Bad_Opcode },
7617     { Bad_Opcode },
7618     { Bad_Opcode },
7619     { Bad_Opcode },
7620     /* 38 */
7621     { Bad_Opcode },
7622     { Bad_Opcode },
7623     { Bad_Opcode },
7624     { Bad_Opcode },
7625     { Bad_Opcode },
7626     { Bad_Opcode },
7627     { Bad_Opcode },
7628     { Bad_Opcode },
7629     /* 40 */
7630     { Bad_Opcode },
7631     { Bad_Opcode },
7632     { Bad_Opcode },
7633     { Bad_Opcode },
7634     { Bad_Opcode },
7635     { Bad_Opcode },
7636     { Bad_Opcode },
7637     { Bad_Opcode },
7638     /* 48 */
7639     { Bad_Opcode },
7640     { Bad_Opcode },
7641     { Bad_Opcode },
7642     { Bad_Opcode },
7643     { Bad_Opcode },
7644     { Bad_Opcode },
7645     { Bad_Opcode },
7646     { Bad_Opcode },
7647     /* 50 */
7648     { Bad_Opcode },
7649     { Bad_Opcode },
7650     { Bad_Opcode },
7651     { Bad_Opcode },
7652     { Bad_Opcode },
7653     { Bad_Opcode },
7654     { Bad_Opcode },
7655     { Bad_Opcode },
7656     /* 58 */
7657     { Bad_Opcode },
7658     { Bad_Opcode },
7659     { Bad_Opcode },
7660     { Bad_Opcode },
7661     { Bad_Opcode },
7662     { Bad_Opcode },
7663     { Bad_Opcode },
7664     { Bad_Opcode },
7665     /* 60 */
7666     { Bad_Opcode },
7667     { Bad_Opcode },
7668     { Bad_Opcode },
7669     { Bad_Opcode },
7670     { Bad_Opcode },
7671     { Bad_Opcode },
7672     { Bad_Opcode },
7673     { Bad_Opcode },
7674     /* 68 */
7675     { Bad_Opcode },
7676     { Bad_Opcode },
7677     { Bad_Opcode },
7678     { Bad_Opcode },
7679     { Bad_Opcode },
7680     { Bad_Opcode },
7681     { Bad_Opcode },
7682     { Bad_Opcode },
7683     /* 70 */
7684     { Bad_Opcode },
7685     { Bad_Opcode },
7686     { Bad_Opcode },
7687     { Bad_Opcode },
7688     { Bad_Opcode },
7689     { Bad_Opcode },
7690     { Bad_Opcode },
7691     { Bad_Opcode },
7692     /* 78 */
7693     { Bad_Opcode },
7694     { Bad_Opcode },
7695     { Bad_Opcode },
7696     { Bad_Opcode },
7697     { Bad_Opcode },
7698     { Bad_Opcode },
7699     { Bad_Opcode },
7700     { Bad_Opcode },
7701     /* 80 */
7702     { Bad_Opcode },
7703     { Bad_Opcode },
7704     { Bad_Opcode },
7705     { Bad_Opcode },
7706     { Bad_Opcode },
7707     { "vpmacssww",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7708     { "vpmacsswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7709     { "vpmacssdql",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7710     /* 88 */
7711     { Bad_Opcode },
7712     { Bad_Opcode },
7713     { Bad_Opcode },
7714     { Bad_Opcode },
7715     { Bad_Opcode },
7716     { Bad_Opcode },
7717     { "vpmacssdd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7718     { "vpmacssdqh",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7719     /* 90 */
7720     { Bad_Opcode },
7721     { Bad_Opcode },
7722     { Bad_Opcode },
7723     { Bad_Opcode },
7724     { Bad_Opcode },
7725     { "vpmacsww",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7726     { "vpmacswd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7727     { "vpmacsdql",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7728     /* 98 */
7729     { Bad_Opcode },
7730     { Bad_Opcode },
7731     { Bad_Opcode },
7732     { Bad_Opcode },
7733     { Bad_Opcode },
7734     { Bad_Opcode },
7735     { "vpmacsdd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7736     { "vpmacsdqh",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7737     /* a0 */
7738     { Bad_Opcode },
7739     { Bad_Opcode },
7740     { "vpcmov",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7741     { "vpperm",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7742     { Bad_Opcode },
7743     { Bad_Opcode },
7744     { "vpmadcsswd",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7745     { Bad_Opcode },
7746     /* a8 */
7747     { Bad_Opcode },
7748     { Bad_Opcode },
7749     { Bad_Opcode },
7750     { Bad_Opcode },
7751     { Bad_Opcode },
7752     { Bad_Opcode },
7753     { Bad_Opcode },
7754     { Bad_Opcode },
7755     /* b0 */
7756     { Bad_Opcode },
7757     { Bad_Opcode },
7758     { Bad_Opcode },
7759     { Bad_Opcode },
7760     { Bad_Opcode },
7761     { Bad_Opcode },
7762     { "vpmadcswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7763     { Bad_Opcode },
7764     /* b8 */
7765     { Bad_Opcode },
7766     { Bad_Opcode },
7767     { Bad_Opcode },
7768     { Bad_Opcode },
7769     { Bad_Opcode },
7770     { Bad_Opcode },
7771     { Bad_Opcode },
7772     { Bad_Opcode },
7773     /* c0 */
7774     { "vprotb",         { XM, Vex_2src_1, Ib }, 0 },
7775     { "vprotw",         { XM, Vex_2src_1, Ib }, 0 },
7776     { "vprotd",         { XM, Vex_2src_1, Ib }, 0 },
7777     { "vprotq",         { XM, Vex_2src_1, Ib }, 0 },
7778     { Bad_Opcode },
7779     { Bad_Opcode },
7780     { Bad_Opcode },
7781     { Bad_Opcode },
7782     /* c8 */
7783     { Bad_Opcode },
7784     { Bad_Opcode },
7785     { Bad_Opcode },
7786     { Bad_Opcode },
7787     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
7788     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
7789     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
7790     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
7791     /* d0 */
7792     { Bad_Opcode },
7793     { Bad_Opcode },
7794     { Bad_Opcode },
7795     { Bad_Opcode },
7796     { Bad_Opcode },
7797     { Bad_Opcode },
7798     { Bad_Opcode },
7799     { Bad_Opcode },
7800     /* d8 */
7801     { Bad_Opcode },
7802     { Bad_Opcode },
7803     { Bad_Opcode },
7804     { Bad_Opcode },
7805     { Bad_Opcode },
7806     { Bad_Opcode },
7807     { Bad_Opcode },
7808     { Bad_Opcode },
7809     /* e0 */
7810     { Bad_Opcode },
7811     { Bad_Opcode },
7812     { Bad_Opcode },
7813     { Bad_Opcode },
7814     { Bad_Opcode },
7815     { Bad_Opcode },
7816     { Bad_Opcode },
7817     { Bad_Opcode },
7818     /* e8 */
7819     { Bad_Opcode },
7820     { Bad_Opcode },
7821     { Bad_Opcode },
7822     { Bad_Opcode },
7823     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
7824     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
7825     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
7826     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
7827     /* f0 */
7828     { Bad_Opcode },
7829     { Bad_Opcode },
7830     { Bad_Opcode },
7831     { Bad_Opcode },
7832     { Bad_Opcode },
7833     { Bad_Opcode },
7834     { Bad_Opcode },
7835     { Bad_Opcode },
7836     /* f8 */
7837     { Bad_Opcode },
7838     { Bad_Opcode },
7839     { Bad_Opcode },
7840     { Bad_Opcode },
7841     { Bad_Opcode },
7842     { Bad_Opcode },
7843     { Bad_Opcode },
7844     { Bad_Opcode },
7845   },
7846   /* XOP_09 */
7847   {
7848     /* 00 */
7849     { Bad_Opcode },
7850     { REG_TABLE (REG_XOP_TBM_01) },
7851     { REG_TABLE (REG_XOP_TBM_02) },
7852     { Bad_Opcode },
7853     { Bad_Opcode },
7854     { Bad_Opcode },
7855     { Bad_Opcode },
7856     { Bad_Opcode },
7857     /* 08 */
7858     { Bad_Opcode },
7859     { Bad_Opcode },
7860     { Bad_Opcode },
7861     { Bad_Opcode },
7862     { Bad_Opcode },
7863     { Bad_Opcode },
7864     { Bad_Opcode },
7865     { Bad_Opcode },
7866     /* 10 */
7867     { Bad_Opcode },
7868     { Bad_Opcode },
7869     { REG_TABLE (REG_XOP_LWPCB) },
7870     { Bad_Opcode },
7871     { Bad_Opcode },
7872     { Bad_Opcode },
7873     { Bad_Opcode },
7874     { Bad_Opcode },
7875     /* 18 */
7876     { Bad_Opcode },
7877     { Bad_Opcode },
7878     { Bad_Opcode },
7879     { Bad_Opcode },
7880     { Bad_Opcode },
7881     { Bad_Opcode },
7882     { Bad_Opcode },
7883     { Bad_Opcode },
7884     /* 20 */
7885     { Bad_Opcode },
7886     { Bad_Opcode },
7887     { Bad_Opcode },
7888     { Bad_Opcode },
7889     { Bad_Opcode },
7890     { Bad_Opcode },
7891     { Bad_Opcode },
7892     { Bad_Opcode },
7893     /* 28 */
7894     { Bad_Opcode },
7895     { Bad_Opcode },
7896     { Bad_Opcode },
7897     { Bad_Opcode },
7898     { Bad_Opcode },
7899     { Bad_Opcode },
7900     { Bad_Opcode },
7901     { Bad_Opcode },
7902     /* 30 */
7903     { Bad_Opcode },
7904     { Bad_Opcode },
7905     { Bad_Opcode },
7906     { Bad_Opcode },
7907     { Bad_Opcode },
7908     { Bad_Opcode },
7909     { Bad_Opcode },
7910     { Bad_Opcode },
7911     /* 38 */
7912     { Bad_Opcode },
7913     { Bad_Opcode },
7914     { Bad_Opcode },
7915     { Bad_Opcode },
7916     { Bad_Opcode },
7917     { Bad_Opcode },
7918     { Bad_Opcode },
7919     { Bad_Opcode },
7920     /* 40 */
7921     { Bad_Opcode },
7922     { Bad_Opcode },
7923     { Bad_Opcode },
7924     { Bad_Opcode },
7925     { Bad_Opcode },
7926     { Bad_Opcode },
7927     { Bad_Opcode },
7928     { Bad_Opcode },
7929     /* 48 */
7930     { Bad_Opcode },
7931     { Bad_Opcode },
7932     { Bad_Opcode },
7933     { Bad_Opcode },
7934     { Bad_Opcode },
7935     { Bad_Opcode },
7936     { Bad_Opcode },
7937     { Bad_Opcode },
7938     /* 50 */
7939     { Bad_Opcode },
7940     { Bad_Opcode },
7941     { Bad_Opcode },
7942     { Bad_Opcode },
7943     { Bad_Opcode },
7944     { Bad_Opcode },
7945     { Bad_Opcode },
7946     { Bad_Opcode },
7947     /* 58 */
7948     { Bad_Opcode },
7949     { Bad_Opcode },
7950     { Bad_Opcode },
7951     { Bad_Opcode },
7952     { Bad_Opcode },
7953     { Bad_Opcode },
7954     { Bad_Opcode },
7955     { Bad_Opcode },
7956     /* 60 */
7957     { Bad_Opcode },
7958     { Bad_Opcode },
7959     { Bad_Opcode },
7960     { Bad_Opcode },
7961     { Bad_Opcode },
7962     { Bad_Opcode },
7963     { Bad_Opcode },
7964     { Bad_Opcode },
7965     /* 68 */
7966     { Bad_Opcode },
7967     { Bad_Opcode },
7968     { Bad_Opcode },
7969     { Bad_Opcode },
7970     { Bad_Opcode },
7971     { Bad_Opcode },
7972     { Bad_Opcode },
7973     { Bad_Opcode },
7974     /* 70 */
7975     { Bad_Opcode },
7976     { Bad_Opcode },
7977     { Bad_Opcode },
7978     { Bad_Opcode },
7979     { Bad_Opcode },
7980     { Bad_Opcode },
7981     { Bad_Opcode },
7982     { Bad_Opcode },
7983     /* 78 */
7984     { Bad_Opcode },
7985     { Bad_Opcode },
7986     { Bad_Opcode },
7987     { Bad_Opcode },
7988     { Bad_Opcode },
7989     { Bad_Opcode },
7990     { Bad_Opcode },
7991     { Bad_Opcode },
7992     /* 80 */
7993     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
7994     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
7995     { "vfrczss",        { XM, EXd }, 0 },
7996     { "vfrczsd",        { XM, EXq }, 0 },
7997     { Bad_Opcode },
7998     { Bad_Opcode },
7999     { Bad_Opcode },
8000     { Bad_Opcode },
8001     /* 88 */
8002     { Bad_Opcode },
8003     { Bad_Opcode },
8004     { Bad_Opcode },
8005     { Bad_Opcode },
8006     { Bad_Opcode },
8007     { Bad_Opcode },
8008     { Bad_Opcode },
8009     { Bad_Opcode },
8010     /* 90 */
8011     { "vprotb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8012     { "vprotw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8013     { "vprotd",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8014     { "vprotq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8015     { "vpshlb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8016     { "vpshlw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8017     { "vpshld",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8018     { "vpshlq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8019     /* 98 */
8020     { "vpshab",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8021     { "vpshaw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8022     { "vpshad",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8023     { "vpshaq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8024     { Bad_Opcode },
8025     { Bad_Opcode },
8026     { Bad_Opcode },
8027     { Bad_Opcode },
8028     /* a0 */
8029     { Bad_Opcode },
8030     { Bad_Opcode },
8031     { Bad_Opcode },
8032     { Bad_Opcode },
8033     { Bad_Opcode },
8034     { Bad_Opcode },
8035     { Bad_Opcode },
8036     { Bad_Opcode },
8037     /* a8 */
8038     { Bad_Opcode },
8039     { Bad_Opcode },
8040     { Bad_Opcode },
8041     { Bad_Opcode },
8042     { Bad_Opcode },
8043     { Bad_Opcode },
8044     { Bad_Opcode },
8045     { Bad_Opcode },
8046     /* b0 */
8047     { Bad_Opcode },
8048     { Bad_Opcode },
8049     { Bad_Opcode },
8050     { Bad_Opcode },
8051     { Bad_Opcode },
8052     { Bad_Opcode },
8053     { Bad_Opcode },
8054     { Bad_Opcode },
8055     /* b8 */
8056     { Bad_Opcode },
8057     { Bad_Opcode },
8058     { Bad_Opcode },
8059     { Bad_Opcode },
8060     { Bad_Opcode },
8061     { Bad_Opcode },
8062     { Bad_Opcode },
8063     { Bad_Opcode },
8064     /* c0 */
8065     { Bad_Opcode },
8066     { "vphaddbw",       { XM, EXxmm }, 0 },
8067     { "vphaddbd",       { XM, EXxmm }, 0 },
8068     { "vphaddbq",       { XM, EXxmm }, 0 },
8069     { Bad_Opcode },
8070     { Bad_Opcode },
8071     { "vphaddwd",       { XM, EXxmm }, 0 },
8072     { "vphaddwq",       { XM, EXxmm }, 0 },
8073     /* c8 */
8074     { Bad_Opcode },
8075     { Bad_Opcode },
8076     { Bad_Opcode },
8077     { "vphadddq",       { XM, EXxmm }, 0 },
8078     { Bad_Opcode },
8079     { Bad_Opcode },
8080     { Bad_Opcode },
8081     { Bad_Opcode },
8082     /* d0 */
8083     { Bad_Opcode },
8084     { "vphaddubw",      { XM, EXxmm }, 0 },
8085     { "vphaddubd",      { XM, EXxmm }, 0 },
8086     { "vphaddubq",      { XM, EXxmm }, 0 },
8087     { Bad_Opcode },
8088     { Bad_Opcode },
8089     { "vphadduwd",      { XM, EXxmm }, 0 },
8090     { "vphadduwq",      { XM, EXxmm }, 0 },
8091     /* d8 */
8092     { Bad_Opcode },
8093     { Bad_Opcode },
8094     { Bad_Opcode },
8095     { "vphaddudq",      { XM, EXxmm }, 0 },
8096     { Bad_Opcode },
8097     { Bad_Opcode },
8098     { Bad_Opcode },
8099     { Bad_Opcode },
8100     /* e0 */
8101     { Bad_Opcode },
8102     { "vphsubbw",       { XM, EXxmm }, 0 },
8103     { "vphsubwd",       { XM, EXxmm }, 0 },
8104     { "vphsubdq",       { XM, EXxmm }, 0 },
8105     { Bad_Opcode },
8106     { Bad_Opcode },
8107     { Bad_Opcode },
8108     { Bad_Opcode },
8109     /* e8 */
8110     { Bad_Opcode },
8111     { Bad_Opcode },
8112     { Bad_Opcode },
8113     { Bad_Opcode },
8114     { Bad_Opcode },
8115     { Bad_Opcode },
8116     { Bad_Opcode },
8117     { Bad_Opcode },
8118     /* f0 */
8119     { Bad_Opcode },
8120     { Bad_Opcode },
8121     { Bad_Opcode },
8122     { Bad_Opcode },
8123     { Bad_Opcode },
8124     { Bad_Opcode },
8125     { Bad_Opcode },
8126     { Bad_Opcode },
8127     /* f8 */
8128     { Bad_Opcode },
8129     { Bad_Opcode },
8130     { Bad_Opcode },
8131     { Bad_Opcode },
8132     { Bad_Opcode },
8133     { Bad_Opcode },
8134     { Bad_Opcode },
8135     { Bad_Opcode },
8136   },
8137   /* XOP_0A */
8138   {
8139     /* 00 */
8140     { Bad_Opcode },
8141     { Bad_Opcode },
8142     { Bad_Opcode },
8143     { Bad_Opcode },
8144     { Bad_Opcode },
8145     { Bad_Opcode },
8146     { Bad_Opcode },
8147     { Bad_Opcode },
8148     /* 08 */
8149     { Bad_Opcode },
8150     { Bad_Opcode },
8151     { Bad_Opcode },
8152     { Bad_Opcode },
8153     { Bad_Opcode },
8154     { Bad_Opcode },
8155     { Bad_Opcode },
8156     { Bad_Opcode },
8157     /* 10 */
8158     { "bextr",  { Gv, Ev, Iq }, 0 },
8159     { Bad_Opcode },
8160     { REG_TABLE (REG_XOP_LWP) },
8161     { Bad_Opcode },
8162     { Bad_Opcode },
8163     { Bad_Opcode },
8164     { Bad_Opcode },
8165     { Bad_Opcode },
8166     /* 18 */
8167     { Bad_Opcode },
8168     { Bad_Opcode },
8169     { Bad_Opcode },
8170     { Bad_Opcode },
8171     { Bad_Opcode },
8172     { Bad_Opcode },
8173     { Bad_Opcode },
8174     { Bad_Opcode },
8175     /* 20 */
8176     { Bad_Opcode },
8177     { Bad_Opcode },
8178     { Bad_Opcode },
8179     { Bad_Opcode },
8180     { Bad_Opcode },
8181     { Bad_Opcode },
8182     { Bad_Opcode },
8183     { Bad_Opcode },
8184     /* 28 */
8185     { Bad_Opcode },
8186     { Bad_Opcode },
8187     { Bad_Opcode },
8188     { Bad_Opcode },
8189     { Bad_Opcode },
8190     { Bad_Opcode },
8191     { Bad_Opcode },
8192     { Bad_Opcode },
8193     /* 30 */
8194     { Bad_Opcode },
8195     { Bad_Opcode },
8196     { Bad_Opcode },
8197     { Bad_Opcode },
8198     { Bad_Opcode },
8199     { Bad_Opcode },
8200     { Bad_Opcode },
8201     { Bad_Opcode },
8202     /* 38 */
8203     { Bad_Opcode },
8204     { Bad_Opcode },
8205     { Bad_Opcode },
8206     { Bad_Opcode },
8207     { Bad_Opcode },
8208     { Bad_Opcode },
8209     { Bad_Opcode },
8210     { Bad_Opcode },
8211     /* 40 */
8212     { Bad_Opcode },
8213     { Bad_Opcode },
8214     { Bad_Opcode },
8215     { Bad_Opcode },
8216     { Bad_Opcode },
8217     { Bad_Opcode },
8218     { Bad_Opcode },
8219     { Bad_Opcode },
8220     /* 48 */
8221     { Bad_Opcode },
8222     { Bad_Opcode },
8223     { Bad_Opcode },
8224     { Bad_Opcode },
8225     { Bad_Opcode },
8226     { Bad_Opcode },
8227     { Bad_Opcode },
8228     { Bad_Opcode },
8229     /* 50 */
8230     { Bad_Opcode },
8231     { Bad_Opcode },
8232     { Bad_Opcode },
8233     { Bad_Opcode },
8234     { Bad_Opcode },
8235     { Bad_Opcode },
8236     { Bad_Opcode },
8237     { Bad_Opcode },
8238     /* 58 */
8239     { Bad_Opcode },
8240     { Bad_Opcode },
8241     { Bad_Opcode },
8242     { Bad_Opcode },
8243     { Bad_Opcode },
8244     { Bad_Opcode },
8245     { Bad_Opcode },
8246     { Bad_Opcode },
8247     /* 60 */
8248     { Bad_Opcode },
8249     { Bad_Opcode },
8250     { Bad_Opcode },
8251     { Bad_Opcode },
8252     { Bad_Opcode },
8253     { Bad_Opcode },
8254     { Bad_Opcode },
8255     { Bad_Opcode },
8256     /* 68 */
8257     { Bad_Opcode },
8258     { Bad_Opcode },
8259     { Bad_Opcode },
8260     { Bad_Opcode },
8261     { Bad_Opcode },
8262     { Bad_Opcode },
8263     { Bad_Opcode },
8264     { Bad_Opcode },
8265     /* 70 */
8266     { Bad_Opcode },
8267     { Bad_Opcode },
8268     { Bad_Opcode },
8269     { Bad_Opcode },
8270     { Bad_Opcode },
8271     { Bad_Opcode },
8272     { Bad_Opcode },
8273     { Bad_Opcode },
8274     /* 78 */
8275     { Bad_Opcode },
8276     { Bad_Opcode },
8277     { Bad_Opcode },
8278     { Bad_Opcode },
8279     { Bad_Opcode },
8280     { Bad_Opcode },
8281     { Bad_Opcode },
8282     { Bad_Opcode },
8283     /* 80 */
8284     { Bad_Opcode },
8285     { Bad_Opcode },
8286     { Bad_Opcode },
8287     { Bad_Opcode },
8288     { Bad_Opcode },
8289     { Bad_Opcode },
8290     { Bad_Opcode },
8291     { Bad_Opcode },
8292     /* 88 */
8293     { Bad_Opcode },
8294     { Bad_Opcode },
8295     { Bad_Opcode },
8296     { Bad_Opcode },
8297     { Bad_Opcode },
8298     { Bad_Opcode },
8299     { Bad_Opcode },
8300     { Bad_Opcode },
8301     /* 90 */
8302     { Bad_Opcode },
8303     { Bad_Opcode },
8304     { Bad_Opcode },
8305     { Bad_Opcode },
8306     { Bad_Opcode },
8307     { Bad_Opcode },
8308     { Bad_Opcode },
8309     { Bad_Opcode },
8310     /* 98 */
8311     { Bad_Opcode },
8312     { Bad_Opcode },
8313     { Bad_Opcode },
8314     { Bad_Opcode },
8315     { Bad_Opcode },
8316     { Bad_Opcode },
8317     { Bad_Opcode },
8318     { Bad_Opcode },
8319     /* a0 */
8320     { Bad_Opcode },
8321     { Bad_Opcode },
8322     { Bad_Opcode },
8323     { Bad_Opcode },
8324     { Bad_Opcode },
8325     { Bad_Opcode },
8326     { Bad_Opcode },
8327     { Bad_Opcode },
8328     /* a8 */
8329     { Bad_Opcode },
8330     { Bad_Opcode },
8331     { Bad_Opcode },
8332     { Bad_Opcode },
8333     { Bad_Opcode },
8334     { Bad_Opcode },
8335     { Bad_Opcode },
8336     { Bad_Opcode },
8337     /* b0 */
8338     { Bad_Opcode },
8339     { Bad_Opcode },
8340     { Bad_Opcode },
8341     { Bad_Opcode },
8342     { Bad_Opcode },
8343     { Bad_Opcode },
8344     { Bad_Opcode },
8345     { Bad_Opcode },
8346     /* b8 */
8347     { Bad_Opcode },
8348     { Bad_Opcode },
8349     { Bad_Opcode },
8350     { Bad_Opcode },
8351     { Bad_Opcode },
8352     { Bad_Opcode },
8353     { Bad_Opcode },
8354     { Bad_Opcode },
8355     /* c0 */
8356     { Bad_Opcode },
8357     { Bad_Opcode },
8358     { Bad_Opcode },
8359     { Bad_Opcode },
8360     { Bad_Opcode },
8361     { Bad_Opcode },
8362     { Bad_Opcode },
8363     { Bad_Opcode },
8364     /* c8 */
8365     { Bad_Opcode },
8366     { Bad_Opcode },
8367     { Bad_Opcode },
8368     { Bad_Opcode },
8369     { Bad_Opcode },
8370     { Bad_Opcode },
8371     { Bad_Opcode },
8372     { Bad_Opcode },
8373     /* d0 */
8374     { Bad_Opcode },
8375     { Bad_Opcode },
8376     { Bad_Opcode },
8377     { Bad_Opcode },
8378     { Bad_Opcode },
8379     { Bad_Opcode },
8380     { Bad_Opcode },
8381     { Bad_Opcode },
8382     /* d8 */
8383     { Bad_Opcode },
8384     { Bad_Opcode },
8385     { Bad_Opcode },
8386     { Bad_Opcode },
8387     { Bad_Opcode },
8388     { Bad_Opcode },
8389     { Bad_Opcode },
8390     { Bad_Opcode },
8391     /* e0 */
8392     { Bad_Opcode },
8393     { Bad_Opcode },
8394     { Bad_Opcode },
8395     { Bad_Opcode },
8396     { Bad_Opcode },
8397     { Bad_Opcode },
8398     { Bad_Opcode },
8399     { Bad_Opcode },
8400     /* e8 */
8401     { Bad_Opcode },
8402     { Bad_Opcode },
8403     { Bad_Opcode },
8404     { Bad_Opcode },
8405     { Bad_Opcode },
8406     { Bad_Opcode },
8407     { Bad_Opcode },
8408     { Bad_Opcode },
8409     /* f0 */
8410     { Bad_Opcode },
8411     { Bad_Opcode },
8412     { Bad_Opcode },
8413     { Bad_Opcode },
8414     { Bad_Opcode },
8415     { Bad_Opcode },
8416     { Bad_Opcode },
8417     { Bad_Opcode },
8418     /* f8 */
8419     { Bad_Opcode },
8420     { Bad_Opcode },
8421     { Bad_Opcode },
8422     { Bad_Opcode },
8423     { Bad_Opcode },
8424     { Bad_Opcode },
8425     { Bad_Opcode },
8426     { Bad_Opcode },
8427   },
8428 };
8429
8430 static const struct dis386 vex_table[][256] = {
8431   /* VEX_0F */
8432   {
8433     /* 00 */
8434     { Bad_Opcode },
8435     { Bad_Opcode },
8436     { Bad_Opcode },
8437     { Bad_Opcode },
8438     { Bad_Opcode },
8439     { Bad_Opcode },
8440     { Bad_Opcode },
8441     { Bad_Opcode },
8442     /* 08 */
8443     { Bad_Opcode },
8444     { Bad_Opcode },
8445     { Bad_Opcode },
8446     { Bad_Opcode },
8447     { Bad_Opcode },
8448     { Bad_Opcode },
8449     { Bad_Opcode },
8450     { Bad_Opcode },
8451     /* 10 */
8452     { PREFIX_TABLE (PREFIX_VEX_0F10) },
8453     { PREFIX_TABLE (PREFIX_VEX_0F11) },
8454     { PREFIX_TABLE (PREFIX_VEX_0F12) },
8455     { MOD_TABLE (MOD_VEX_0F13) },
8456     { VEX_W_TABLE (VEX_W_0F14) },
8457     { VEX_W_TABLE (VEX_W_0F15) },
8458     { PREFIX_TABLE (PREFIX_VEX_0F16) },
8459     { MOD_TABLE (MOD_VEX_0F17) },
8460     /* 18 */
8461     { Bad_Opcode },
8462     { Bad_Opcode },
8463     { Bad_Opcode },
8464     { Bad_Opcode },
8465     { Bad_Opcode },
8466     { Bad_Opcode },
8467     { Bad_Opcode },
8468     { Bad_Opcode },
8469     /* 20 */
8470     { Bad_Opcode },
8471     { Bad_Opcode },
8472     { Bad_Opcode },
8473     { Bad_Opcode },
8474     { Bad_Opcode },
8475     { Bad_Opcode },
8476     { Bad_Opcode },
8477     { Bad_Opcode },
8478     /* 28 */
8479     { VEX_W_TABLE (VEX_W_0F28) },
8480     { VEX_W_TABLE (VEX_W_0F29) },
8481     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8482     { MOD_TABLE (MOD_VEX_0F2B) },
8483     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8484     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8485     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8486     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8487     /* 30 */
8488     { Bad_Opcode },
8489     { Bad_Opcode },
8490     { Bad_Opcode },
8491     { Bad_Opcode },
8492     { Bad_Opcode },
8493     { Bad_Opcode },
8494     { Bad_Opcode },
8495     { Bad_Opcode },
8496     /* 38 */
8497     { Bad_Opcode },
8498     { Bad_Opcode },
8499     { Bad_Opcode },
8500     { Bad_Opcode },
8501     { Bad_Opcode },
8502     { Bad_Opcode },
8503     { Bad_Opcode },
8504     { Bad_Opcode },
8505     /* 40 */
8506     { Bad_Opcode },
8507     { PREFIX_TABLE (PREFIX_VEX_0F41) },
8508     { PREFIX_TABLE (PREFIX_VEX_0F42) },
8509     { Bad_Opcode },
8510     { PREFIX_TABLE (PREFIX_VEX_0F44) },
8511     { PREFIX_TABLE (PREFIX_VEX_0F45) },
8512     { PREFIX_TABLE (PREFIX_VEX_0F46) },
8513     { PREFIX_TABLE (PREFIX_VEX_0F47) },
8514     /* 48 */
8515     { Bad_Opcode },
8516     { Bad_Opcode },
8517     { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8518     { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8519     { Bad_Opcode },
8520     { Bad_Opcode },
8521     { Bad_Opcode },
8522     { Bad_Opcode },
8523     /* 50 */
8524     { MOD_TABLE (MOD_VEX_0F50) },
8525     { PREFIX_TABLE (PREFIX_VEX_0F51) },
8526     { PREFIX_TABLE (PREFIX_VEX_0F52) },
8527     { PREFIX_TABLE (PREFIX_VEX_0F53) },
8528     { "vandpX",         { XM, Vex, EXx }, 0 },
8529     { "vandnpX",        { XM, Vex, EXx }, 0 },
8530     { "vorpX",          { XM, Vex, EXx }, 0 },
8531     { "vxorpX",         { XM, Vex, EXx }, 0 },
8532     /* 58 */
8533     { PREFIX_TABLE (PREFIX_VEX_0F58) },
8534     { PREFIX_TABLE (PREFIX_VEX_0F59) },
8535     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8536     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8537     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8538     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8539     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8540     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8541     /* 60 */
8542     { PREFIX_TABLE (PREFIX_VEX_0F60) },
8543     { PREFIX_TABLE (PREFIX_VEX_0F61) },
8544     { PREFIX_TABLE (PREFIX_VEX_0F62) },
8545     { PREFIX_TABLE (PREFIX_VEX_0F63) },
8546     { PREFIX_TABLE (PREFIX_VEX_0F64) },
8547     { PREFIX_TABLE (PREFIX_VEX_0F65) },
8548     { PREFIX_TABLE (PREFIX_VEX_0F66) },
8549     { PREFIX_TABLE (PREFIX_VEX_0F67) },
8550     /* 68 */
8551     { PREFIX_TABLE (PREFIX_VEX_0F68) },
8552     { PREFIX_TABLE (PREFIX_VEX_0F69) },
8553     { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8554     { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8555     { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8556     { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8557     { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8558     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8559     /* 70 */
8560     { PREFIX_TABLE (PREFIX_VEX_0F70) },
8561     { REG_TABLE (REG_VEX_0F71) },
8562     { REG_TABLE (REG_VEX_0F72) },
8563     { REG_TABLE (REG_VEX_0F73) },
8564     { PREFIX_TABLE (PREFIX_VEX_0F74) },
8565     { PREFIX_TABLE (PREFIX_VEX_0F75) },
8566     { PREFIX_TABLE (PREFIX_VEX_0F76) },
8567     { PREFIX_TABLE (PREFIX_VEX_0F77) },
8568     /* 78 */
8569     { Bad_Opcode },
8570     { Bad_Opcode },
8571     { Bad_Opcode },
8572     { Bad_Opcode },
8573     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8574     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8575     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8576     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8577     /* 80 */
8578     { Bad_Opcode },
8579     { Bad_Opcode },
8580     { Bad_Opcode },
8581     { Bad_Opcode },
8582     { Bad_Opcode },
8583     { Bad_Opcode },
8584     { Bad_Opcode },
8585     { Bad_Opcode },
8586     /* 88 */
8587     { Bad_Opcode },
8588     { Bad_Opcode },
8589     { Bad_Opcode },
8590     { Bad_Opcode },
8591     { Bad_Opcode },
8592     { Bad_Opcode },
8593     { Bad_Opcode },
8594     { Bad_Opcode },
8595     /* 90 */
8596     { PREFIX_TABLE (PREFIX_VEX_0F90) },
8597     { PREFIX_TABLE (PREFIX_VEX_0F91) },
8598     { PREFIX_TABLE (PREFIX_VEX_0F92) },
8599     { PREFIX_TABLE (PREFIX_VEX_0F93) },
8600     { Bad_Opcode },
8601     { Bad_Opcode },
8602     { Bad_Opcode },
8603     { Bad_Opcode },
8604     /* 98 */
8605     { PREFIX_TABLE (PREFIX_VEX_0F98) },
8606     { PREFIX_TABLE (PREFIX_VEX_0F99) },
8607     { Bad_Opcode },
8608     { Bad_Opcode },
8609     { Bad_Opcode },
8610     { Bad_Opcode },
8611     { Bad_Opcode },
8612     { Bad_Opcode },
8613     /* a0 */
8614     { Bad_Opcode },
8615     { Bad_Opcode },
8616     { Bad_Opcode },
8617     { Bad_Opcode },
8618     { Bad_Opcode },
8619     { Bad_Opcode },
8620     { Bad_Opcode },
8621     { Bad_Opcode },
8622     /* a8 */
8623     { Bad_Opcode },
8624     { Bad_Opcode },
8625     { Bad_Opcode },
8626     { Bad_Opcode },
8627     { Bad_Opcode },
8628     { Bad_Opcode },
8629     { REG_TABLE (REG_VEX_0FAE) },
8630     { Bad_Opcode },
8631     /* b0 */
8632     { Bad_Opcode },
8633     { Bad_Opcode },
8634     { Bad_Opcode },
8635     { Bad_Opcode },
8636     { Bad_Opcode },
8637     { Bad_Opcode },
8638     { Bad_Opcode },
8639     { Bad_Opcode },
8640     /* b8 */
8641     { Bad_Opcode },
8642     { Bad_Opcode },
8643     { Bad_Opcode },
8644     { Bad_Opcode },
8645     { Bad_Opcode },
8646     { Bad_Opcode },
8647     { Bad_Opcode },
8648     { Bad_Opcode },
8649     /* c0 */
8650     { Bad_Opcode },
8651     { Bad_Opcode },
8652     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8653     { Bad_Opcode },
8654     { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8655     { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8656     { "vshufpX",        { XM, Vex, EXx, Ib }, 0 },
8657     { Bad_Opcode },
8658     /* c8 */
8659     { Bad_Opcode },
8660     { Bad_Opcode },
8661     { Bad_Opcode },
8662     { Bad_Opcode },
8663     { Bad_Opcode },
8664     { Bad_Opcode },
8665     { Bad_Opcode },
8666     { Bad_Opcode },
8667     /* d0 */
8668     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8669     { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8670     { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8671     { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8672     { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8673     { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8674     { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8675     { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8676     /* d8 */
8677     { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8678     { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8679     { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8680     { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8681     { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8682     { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8683     { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8684     { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8685     /* e0 */
8686     { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8687     { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8688     { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8689     { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8690     { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8691     { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8692     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8693     { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8694     /* e8 */
8695     { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8696     { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8697     { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8698     { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8699     { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8700     { PREFIX_TABLE (PREFIX_VEX_0FED) },
8701     { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8702     { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8703     /* f0 */
8704     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8705     { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8706     { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8707     { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8708     { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8709     { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8710     { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8711     { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8712     /* f8 */
8713     { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8714     { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8715     { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8716     { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8717     { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8718     { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8719     { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8720     { Bad_Opcode },
8721   },
8722   /* VEX_0F38 */
8723   {
8724     /* 00 */
8725     { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8726     { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8727     { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8728     { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8729     { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8730     { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8731     { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8732     { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8733     /* 08 */
8734     { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8735     { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8736     { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8737     { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8738     { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8739     { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8740     { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8741     { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8742     /* 10 */
8743     { Bad_Opcode },
8744     { Bad_Opcode },
8745     { Bad_Opcode },
8746     { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8747     { Bad_Opcode },
8748     { Bad_Opcode },
8749     { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8750     { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8751     /* 18 */
8752     { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8753     { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8754     { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8755     { Bad_Opcode },
8756     { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8757     { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8758     { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8759     { Bad_Opcode },
8760     /* 20 */
8761     { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8762     { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8763     { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8764     { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8765     { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8766     { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8767     { Bad_Opcode },
8768     { Bad_Opcode },
8769     /* 28 */
8770     { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8771     { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8772     { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8773     { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8774     { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8775     { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8776     { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8777     { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8778     /* 30 */
8779     { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8780     { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8781     { PREFIX_TABLE (PREFIX_VEX_0F3832) },
8782     { PREFIX_TABLE (PREFIX_VEX_0F3833) },
8783     { PREFIX_TABLE (PREFIX_VEX_0F3834) },
8784     { PREFIX_TABLE (PREFIX_VEX_0F3835) },
8785     { PREFIX_TABLE (PREFIX_VEX_0F3836) },
8786     { PREFIX_TABLE (PREFIX_VEX_0F3837) },
8787     /* 38 */
8788     { PREFIX_TABLE (PREFIX_VEX_0F3838) },
8789     { PREFIX_TABLE (PREFIX_VEX_0F3839) },
8790     { PREFIX_TABLE (PREFIX_VEX_0F383A) },
8791     { PREFIX_TABLE (PREFIX_VEX_0F383B) },
8792     { PREFIX_TABLE (PREFIX_VEX_0F383C) },
8793     { PREFIX_TABLE (PREFIX_VEX_0F383D) },
8794     { PREFIX_TABLE (PREFIX_VEX_0F383E) },
8795     { PREFIX_TABLE (PREFIX_VEX_0F383F) },
8796     /* 40 */
8797     { PREFIX_TABLE (PREFIX_VEX_0F3840) },
8798     { PREFIX_TABLE (PREFIX_VEX_0F3841) },
8799     { Bad_Opcode },
8800     { Bad_Opcode },
8801     { Bad_Opcode },
8802     { PREFIX_TABLE (PREFIX_VEX_0F3845) },
8803     { PREFIX_TABLE (PREFIX_VEX_0F3846) },
8804     { PREFIX_TABLE (PREFIX_VEX_0F3847) },
8805     /* 48 */
8806     { Bad_Opcode },
8807     { Bad_Opcode },
8808     { Bad_Opcode },
8809     { Bad_Opcode },
8810     { Bad_Opcode },
8811     { Bad_Opcode },
8812     { Bad_Opcode },
8813     { Bad_Opcode },
8814     /* 50 */
8815     { Bad_Opcode },
8816     { Bad_Opcode },
8817     { Bad_Opcode },
8818     { Bad_Opcode },
8819     { Bad_Opcode },
8820     { Bad_Opcode },
8821     { Bad_Opcode },
8822     { Bad_Opcode },
8823     /* 58 */
8824     { PREFIX_TABLE (PREFIX_VEX_0F3858) },
8825     { PREFIX_TABLE (PREFIX_VEX_0F3859) },
8826     { PREFIX_TABLE (PREFIX_VEX_0F385A) },
8827     { Bad_Opcode },
8828     { Bad_Opcode },
8829     { Bad_Opcode },
8830     { Bad_Opcode },
8831     { Bad_Opcode },
8832     /* 60 */
8833     { Bad_Opcode },
8834     { Bad_Opcode },
8835     { Bad_Opcode },
8836     { Bad_Opcode },
8837     { Bad_Opcode },
8838     { Bad_Opcode },
8839     { Bad_Opcode },
8840     { Bad_Opcode },
8841     /* 68 */
8842     { Bad_Opcode },
8843     { Bad_Opcode },
8844     { Bad_Opcode },
8845     { Bad_Opcode },
8846     { Bad_Opcode },
8847     { Bad_Opcode },
8848     { Bad_Opcode },
8849     { Bad_Opcode },
8850     /* 70 */
8851     { Bad_Opcode },
8852     { Bad_Opcode },
8853     { Bad_Opcode },
8854     { Bad_Opcode },
8855     { Bad_Opcode },
8856     { Bad_Opcode },
8857     { Bad_Opcode },
8858     { Bad_Opcode },
8859     /* 78 */
8860     { PREFIX_TABLE (PREFIX_VEX_0F3878) },
8861     { PREFIX_TABLE (PREFIX_VEX_0F3879) },
8862     { Bad_Opcode },
8863     { Bad_Opcode },
8864     { Bad_Opcode },
8865     { Bad_Opcode },
8866     { Bad_Opcode },
8867     { Bad_Opcode },
8868     /* 80 */
8869     { Bad_Opcode },
8870     { Bad_Opcode },
8871     { Bad_Opcode },
8872     { Bad_Opcode },
8873     { Bad_Opcode },
8874     { Bad_Opcode },
8875     { Bad_Opcode },
8876     { Bad_Opcode },
8877     /* 88 */
8878     { Bad_Opcode },
8879     { Bad_Opcode },
8880     { Bad_Opcode },
8881     { Bad_Opcode },
8882     { PREFIX_TABLE (PREFIX_VEX_0F388C) },
8883     { Bad_Opcode },
8884     { PREFIX_TABLE (PREFIX_VEX_0F388E) },
8885     { Bad_Opcode },
8886     /* 90 */
8887     { PREFIX_TABLE (PREFIX_VEX_0F3890) },
8888     { PREFIX_TABLE (PREFIX_VEX_0F3891) },
8889     { PREFIX_TABLE (PREFIX_VEX_0F3892) },
8890     { PREFIX_TABLE (PREFIX_VEX_0F3893) },
8891     { Bad_Opcode },
8892     { Bad_Opcode },
8893     { PREFIX_TABLE (PREFIX_VEX_0F3896) },
8894     { PREFIX_TABLE (PREFIX_VEX_0F3897) },
8895     /* 98 */
8896     { PREFIX_TABLE (PREFIX_VEX_0F3898) },
8897     { PREFIX_TABLE (PREFIX_VEX_0F3899) },
8898     { PREFIX_TABLE (PREFIX_VEX_0F389A) },
8899     { PREFIX_TABLE (PREFIX_VEX_0F389B) },
8900     { PREFIX_TABLE (PREFIX_VEX_0F389C) },
8901     { PREFIX_TABLE (PREFIX_VEX_0F389D) },
8902     { PREFIX_TABLE (PREFIX_VEX_0F389E) },
8903     { PREFIX_TABLE (PREFIX_VEX_0F389F) },
8904     /* a0 */
8905     { Bad_Opcode },
8906     { Bad_Opcode },
8907     { Bad_Opcode },
8908     { Bad_Opcode },
8909     { Bad_Opcode },
8910     { Bad_Opcode },
8911     { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
8912     { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
8913     /* a8 */
8914     { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
8915     { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
8916     { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
8917     { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
8918     { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
8919     { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
8920     { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
8921     { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
8922     /* b0 */
8923     { Bad_Opcode },
8924     { Bad_Opcode },
8925     { Bad_Opcode },
8926     { Bad_Opcode },
8927     { Bad_Opcode },
8928     { Bad_Opcode },
8929     { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
8930     { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
8931     /* b8 */
8932     { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
8933     { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
8934     { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
8935     { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
8936     { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
8937     { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
8938     { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
8939     { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
8940     /* c0 */
8941     { Bad_Opcode },
8942     { Bad_Opcode },
8943     { Bad_Opcode },
8944     { Bad_Opcode },
8945     { Bad_Opcode },
8946     { Bad_Opcode },
8947     { Bad_Opcode },
8948     { Bad_Opcode },
8949     /* c8 */
8950     { Bad_Opcode },
8951     { Bad_Opcode },
8952     { Bad_Opcode },
8953     { Bad_Opcode },
8954     { Bad_Opcode },
8955     { Bad_Opcode },
8956     { Bad_Opcode },
8957     { Bad_Opcode },
8958     /* d0 */
8959     { Bad_Opcode },
8960     { Bad_Opcode },
8961     { Bad_Opcode },
8962     { Bad_Opcode },
8963     { Bad_Opcode },
8964     { Bad_Opcode },
8965     { Bad_Opcode },
8966     { Bad_Opcode },
8967     /* d8 */
8968     { Bad_Opcode },
8969     { Bad_Opcode },
8970     { Bad_Opcode },
8971     { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
8972     { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
8973     { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
8974     { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
8975     { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
8976     /* e0 */
8977     { Bad_Opcode },
8978     { Bad_Opcode },
8979     { Bad_Opcode },
8980     { Bad_Opcode },
8981     { Bad_Opcode },
8982     { Bad_Opcode },
8983     { Bad_Opcode },
8984     { Bad_Opcode },
8985     /* e8 */
8986     { Bad_Opcode },
8987     { Bad_Opcode },
8988     { Bad_Opcode },
8989     { Bad_Opcode },
8990     { Bad_Opcode },
8991     { Bad_Opcode },
8992     { Bad_Opcode },
8993     { Bad_Opcode },
8994     /* f0 */
8995     { Bad_Opcode },
8996     { Bad_Opcode },
8997     { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
8998     { REG_TABLE (REG_VEX_0F38F3) },
8999     { Bad_Opcode },
9000     { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
9001     { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
9002     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
9003     /* f8 */
9004     { Bad_Opcode },
9005     { Bad_Opcode },
9006     { Bad_Opcode },
9007     { Bad_Opcode },
9008     { Bad_Opcode },
9009     { Bad_Opcode },
9010     { Bad_Opcode },
9011     { Bad_Opcode },
9012   },
9013   /* VEX_0F3A */
9014   {
9015     /* 00 */
9016     { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
9017     { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
9018     { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
9019     { Bad_Opcode },
9020     { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
9021     { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
9022     { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
9023     { Bad_Opcode },
9024     /* 08 */
9025     { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
9026     { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
9027     { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
9028     { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
9029     { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
9030     { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
9031     { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
9032     { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
9033     /* 10 */
9034     { Bad_Opcode },
9035     { Bad_Opcode },
9036     { Bad_Opcode },
9037     { Bad_Opcode },
9038     { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
9039     { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
9040     { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
9041     { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
9042     /* 18 */
9043     { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
9044     { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
9045     { Bad_Opcode },
9046     { Bad_Opcode },
9047     { Bad_Opcode },
9048     { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
9049     { Bad_Opcode },
9050     { Bad_Opcode },
9051     /* 20 */
9052     { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
9053     { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
9054     { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
9055     { Bad_Opcode },
9056     { Bad_Opcode },
9057     { Bad_Opcode },
9058     { Bad_Opcode },
9059     { Bad_Opcode },
9060     /* 28 */
9061     { Bad_Opcode },
9062     { Bad_Opcode },
9063     { Bad_Opcode },
9064     { Bad_Opcode },
9065     { Bad_Opcode },
9066     { Bad_Opcode },
9067     { Bad_Opcode },
9068     { Bad_Opcode },
9069     /* 30 */
9070     { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
9071     { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
9072     { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
9073     { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
9074     { Bad_Opcode },
9075     { Bad_Opcode },
9076     { Bad_Opcode },
9077     { Bad_Opcode },
9078     /* 38 */
9079     { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
9080     { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
9081     { Bad_Opcode },
9082     { Bad_Opcode },
9083     { Bad_Opcode },
9084     { Bad_Opcode },
9085     { Bad_Opcode },
9086     { Bad_Opcode },
9087     /* 40 */
9088     { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
9089     { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
9090     { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
9091     { Bad_Opcode },
9092     { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
9093     { Bad_Opcode },
9094     { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
9095     { Bad_Opcode },
9096     /* 48 */
9097     { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
9098     { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
9099     { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
9100     { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
9101     { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
9102     { Bad_Opcode },
9103     { Bad_Opcode },
9104     { Bad_Opcode },
9105     /* 50 */
9106     { Bad_Opcode },
9107     { Bad_Opcode },
9108     { Bad_Opcode },
9109     { Bad_Opcode },
9110     { Bad_Opcode },
9111     { Bad_Opcode },
9112     { Bad_Opcode },
9113     { Bad_Opcode },
9114     /* 58 */
9115     { Bad_Opcode },
9116     { Bad_Opcode },
9117     { Bad_Opcode },
9118     { Bad_Opcode },
9119     { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9120     { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9121     { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9122     { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9123     /* 60 */
9124     { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9125     { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9126     { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9127     { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9128     { Bad_Opcode },
9129     { Bad_Opcode },
9130     { Bad_Opcode },
9131     { Bad_Opcode },
9132     /* 68 */
9133     { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9134     { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9135     { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9136     { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9137     { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9138     { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9139     { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9140     { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9141     /* 70 */
9142     { Bad_Opcode },
9143     { Bad_Opcode },
9144     { Bad_Opcode },
9145     { Bad_Opcode },
9146     { Bad_Opcode },
9147     { Bad_Opcode },
9148     { Bad_Opcode },
9149     { Bad_Opcode },
9150     /* 78 */
9151     { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9152     { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9153     { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9154     { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9155     { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9156     { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9157     { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9158     { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9159     /* 80 */
9160     { Bad_Opcode },
9161     { Bad_Opcode },
9162     { Bad_Opcode },
9163     { Bad_Opcode },
9164     { Bad_Opcode },
9165     { Bad_Opcode },
9166     { Bad_Opcode },
9167     { Bad_Opcode },
9168     /* 88 */
9169     { Bad_Opcode },
9170     { Bad_Opcode },
9171     { Bad_Opcode },
9172     { Bad_Opcode },
9173     { Bad_Opcode },
9174     { Bad_Opcode },
9175     { Bad_Opcode },
9176     { Bad_Opcode },
9177     /* 90 */
9178     { Bad_Opcode },
9179     { Bad_Opcode },
9180     { Bad_Opcode },
9181     { Bad_Opcode },
9182     { Bad_Opcode },
9183     { Bad_Opcode },
9184     { Bad_Opcode },
9185     { Bad_Opcode },
9186     /* 98 */
9187     { Bad_Opcode },
9188     { Bad_Opcode },
9189     { Bad_Opcode },
9190     { Bad_Opcode },
9191     { Bad_Opcode },
9192     { Bad_Opcode },
9193     { Bad_Opcode },
9194     { Bad_Opcode },
9195     /* a0 */
9196     { Bad_Opcode },
9197     { Bad_Opcode },
9198     { Bad_Opcode },
9199     { Bad_Opcode },
9200     { Bad_Opcode },
9201     { Bad_Opcode },
9202     { Bad_Opcode },
9203     { Bad_Opcode },
9204     /* a8 */
9205     { Bad_Opcode },
9206     { Bad_Opcode },
9207     { Bad_Opcode },
9208     { Bad_Opcode },
9209     { Bad_Opcode },
9210     { Bad_Opcode },
9211     { Bad_Opcode },
9212     { Bad_Opcode },
9213     /* b0 */
9214     { Bad_Opcode },
9215     { Bad_Opcode },
9216     { Bad_Opcode },
9217     { Bad_Opcode },
9218     { Bad_Opcode },
9219     { Bad_Opcode },
9220     { Bad_Opcode },
9221     { Bad_Opcode },
9222     /* b8 */
9223     { Bad_Opcode },
9224     { Bad_Opcode },
9225     { Bad_Opcode },
9226     { Bad_Opcode },
9227     { Bad_Opcode },
9228     { Bad_Opcode },
9229     { Bad_Opcode },
9230     { Bad_Opcode },
9231     /* c0 */
9232     { Bad_Opcode },
9233     { Bad_Opcode },
9234     { Bad_Opcode },
9235     { Bad_Opcode },
9236     { Bad_Opcode },
9237     { Bad_Opcode },
9238     { Bad_Opcode },
9239     { Bad_Opcode },
9240     /* c8 */
9241     { Bad_Opcode },
9242     { Bad_Opcode },
9243     { Bad_Opcode },
9244     { Bad_Opcode },
9245     { Bad_Opcode },
9246     { Bad_Opcode },
9247     { Bad_Opcode },
9248     { Bad_Opcode },
9249     /* d0 */
9250     { Bad_Opcode },
9251     { Bad_Opcode },
9252     { Bad_Opcode },
9253     { Bad_Opcode },
9254     { Bad_Opcode },
9255     { Bad_Opcode },
9256     { Bad_Opcode },
9257     { Bad_Opcode },
9258     /* d8 */
9259     { Bad_Opcode },
9260     { Bad_Opcode },
9261     { Bad_Opcode },
9262     { Bad_Opcode },
9263     { Bad_Opcode },
9264     { Bad_Opcode },
9265     { Bad_Opcode },
9266     { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9267     /* e0 */
9268     { Bad_Opcode },
9269     { Bad_Opcode },
9270     { Bad_Opcode },
9271     { Bad_Opcode },
9272     { Bad_Opcode },
9273     { Bad_Opcode },
9274     { Bad_Opcode },
9275     { Bad_Opcode },
9276     /* e8 */
9277     { Bad_Opcode },
9278     { Bad_Opcode },
9279     { Bad_Opcode },
9280     { Bad_Opcode },
9281     { Bad_Opcode },
9282     { Bad_Opcode },
9283     { Bad_Opcode },
9284     { Bad_Opcode },
9285     /* f0 */
9286     { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9287     { Bad_Opcode },
9288     { Bad_Opcode },
9289     { Bad_Opcode },
9290     { Bad_Opcode },
9291     { Bad_Opcode },
9292     { Bad_Opcode },
9293     { Bad_Opcode },
9294     /* f8 */
9295     { Bad_Opcode },
9296     { Bad_Opcode },
9297     { Bad_Opcode },
9298     { Bad_Opcode },
9299     { Bad_Opcode },
9300     { Bad_Opcode },
9301     { Bad_Opcode },
9302     { Bad_Opcode },
9303   },
9304 };
9305
9306 #define NEED_OPCODE_TABLE
9307 #include "i386-dis-evex.h"
9308 #undef NEED_OPCODE_TABLE
9309 static const struct dis386 vex_len_table[][2] = {
9310   /* VEX_LEN_0F10_P_1 */
9311   {
9312     { VEX_W_TABLE (VEX_W_0F10_P_1) },
9313     { VEX_W_TABLE (VEX_W_0F10_P_1) },
9314   },
9315
9316   /* VEX_LEN_0F10_P_3 */
9317   {
9318     { VEX_W_TABLE (VEX_W_0F10_P_3) },
9319     { VEX_W_TABLE (VEX_W_0F10_P_3) },
9320   },
9321
9322   /* VEX_LEN_0F11_P_1 */
9323   {
9324     { VEX_W_TABLE (VEX_W_0F11_P_1) },
9325     { VEX_W_TABLE (VEX_W_0F11_P_1) },
9326   },
9327
9328   /* VEX_LEN_0F11_P_3 */
9329   {
9330     { VEX_W_TABLE (VEX_W_0F11_P_3) },
9331     { VEX_W_TABLE (VEX_W_0F11_P_3) },
9332   },
9333
9334   /* VEX_LEN_0F12_P_0_M_0 */
9335   {
9336     { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) },
9337   },
9338
9339   /* VEX_LEN_0F12_P_0_M_1 */
9340   {
9341     { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) },
9342   },
9343
9344   /* VEX_LEN_0F12_P_2 */
9345   {
9346     { VEX_W_TABLE (VEX_W_0F12_P_2) },
9347   },
9348
9349   /* VEX_LEN_0F13_M_0 */
9350   {
9351     { VEX_W_TABLE (VEX_W_0F13_M_0) },
9352   },
9353
9354   /* VEX_LEN_0F16_P_0_M_0 */
9355   {
9356     { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) },
9357   },
9358
9359   /* VEX_LEN_0F16_P_0_M_1 */
9360   {
9361     { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) },
9362   },
9363
9364   /* VEX_LEN_0F16_P_2 */
9365   {
9366     { VEX_W_TABLE (VEX_W_0F16_P_2) },
9367   },
9368
9369   /* VEX_LEN_0F17_M_0 */
9370   {
9371     { VEX_W_TABLE (VEX_W_0F17_M_0) },
9372   },
9373
9374   /* VEX_LEN_0F2A_P_1 */
9375   {
9376     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9377     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9378   },
9379
9380   /* VEX_LEN_0F2A_P_3 */
9381   {
9382     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9383     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9384   },
9385
9386   /* VEX_LEN_0F2C_P_1 */
9387   {
9388     { "vcvttss2siY",    { Gv, EXdScalar }, 0 },
9389     { "vcvttss2siY",    { Gv, EXdScalar }, 0 },
9390   },
9391
9392   /* VEX_LEN_0F2C_P_3 */
9393   {
9394     { "vcvttsd2siY",    { Gv, EXqScalar }, 0 },
9395     { "vcvttsd2siY",    { Gv, EXqScalar }, 0 },
9396   },
9397
9398   /* VEX_LEN_0F2D_P_1 */
9399   {
9400     { "vcvtss2siY",     { Gv, EXdScalar }, 0 },
9401     { "vcvtss2siY",     { Gv, EXdScalar }, 0 },
9402   },
9403
9404   /* VEX_LEN_0F2D_P_3 */
9405   {
9406     { "vcvtsd2siY",     { Gv, EXqScalar }, 0 },
9407     { "vcvtsd2siY",     { Gv, EXqScalar }, 0 },
9408   },
9409
9410   /* VEX_LEN_0F2E_P_0 */
9411   {
9412     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9413     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9414   },
9415
9416   /* VEX_LEN_0F2E_P_2 */
9417   {
9418     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9419     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9420   },
9421
9422   /* VEX_LEN_0F2F_P_0 */
9423   {
9424     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9425     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9426   },
9427
9428   /* VEX_LEN_0F2F_P_2 */
9429   {
9430     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9431     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9432   },
9433
9434   /* VEX_LEN_0F41_P_0 */
9435   {
9436     { Bad_Opcode },
9437     { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9438   },
9439   /* VEX_LEN_0F41_P_2 */
9440   {
9441     { Bad_Opcode },
9442     { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9443   },
9444   /* VEX_LEN_0F42_P_0 */
9445   {
9446     { Bad_Opcode },
9447     { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9448   },
9449   /* VEX_LEN_0F42_P_2 */
9450   {
9451     { Bad_Opcode },
9452     { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9453   },
9454   /* VEX_LEN_0F44_P_0 */
9455   {
9456     { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9457   },
9458   /* VEX_LEN_0F44_P_2 */
9459   {
9460     { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9461   },
9462   /* VEX_LEN_0F45_P_0 */
9463   {
9464     { Bad_Opcode },
9465     { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9466   },
9467   /* VEX_LEN_0F45_P_2 */
9468   {
9469     { Bad_Opcode },
9470     { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9471   },
9472   /* VEX_LEN_0F46_P_0 */
9473   {
9474     { Bad_Opcode },
9475     { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9476   },
9477   /* VEX_LEN_0F46_P_2 */
9478   {
9479     { Bad_Opcode },
9480     { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9481   },
9482   /* VEX_LEN_0F47_P_0 */
9483   {
9484     { Bad_Opcode },
9485     { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9486   },
9487   /* VEX_LEN_0F47_P_2 */
9488   {
9489     { Bad_Opcode },
9490     { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9491   },
9492   /* VEX_LEN_0F4A_P_0 */
9493   {
9494     { Bad_Opcode },
9495     { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9496   },
9497   /* VEX_LEN_0F4A_P_2 */
9498   {
9499     { Bad_Opcode },
9500     { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9501   },
9502   /* VEX_LEN_0F4B_P_0 */
9503   {
9504     { Bad_Opcode },
9505     { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9506   },
9507   /* VEX_LEN_0F4B_P_2 */
9508   {
9509     { Bad_Opcode },
9510     { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9511   },
9512
9513   /* VEX_LEN_0F51_P_1 */
9514   {
9515     { VEX_W_TABLE (VEX_W_0F51_P_1) },
9516     { VEX_W_TABLE (VEX_W_0F51_P_1) },
9517   },
9518
9519   /* VEX_LEN_0F51_P_3 */
9520   {
9521     { VEX_W_TABLE (VEX_W_0F51_P_3) },
9522     { VEX_W_TABLE (VEX_W_0F51_P_3) },
9523   },
9524
9525   /* VEX_LEN_0F52_P_1 */
9526   {
9527     { VEX_W_TABLE (VEX_W_0F52_P_1) },
9528     { VEX_W_TABLE (VEX_W_0F52_P_1) },
9529   },
9530
9531   /* VEX_LEN_0F53_P_1 */
9532   {
9533     { VEX_W_TABLE (VEX_W_0F53_P_1) },
9534     { VEX_W_TABLE (VEX_W_0F53_P_1) },
9535   },
9536
9537   /* VEX_LEN_0F58_P_1 */
9538   {
9539     { VEX_W_TABLE (VEX_W_0F58_P_1) },
9540     { VEX_W_TABLE (VEX_W_0F58_P_1) },
9541   },
9542
9543   /* VEX_LEN_0F58_P_3 */
9544   {
9545     { VEX_W_TABLE (VEX_W_0F58_P_3) },
9546     { VEX_W_TABLE (VEX_W_0F58_P_3) },
9547   },
9548
9549   /* VEX_LEN_0F59_P_1 */
9550   {
9551     { VEX_W_TABLE (VEX_W_0F59_P_1) },
9552     { VEX_W_TABLE (VEX_W_0F59_P_1) },
9553   },
9554
9555   /* VEX_LEN_0F59_P_3 */
9556   {
9557     { VEX_W_TABLE (VEX_W_0F59_P_3) },
9558     { VEX_W_TABLE (VEX_W_0F59_P_3) },
9559   },
9560
9561   /* VEX_LEN_0F5A_P_1 */
9562   {
9563     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9564     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9565   },
9566
9567   /* VEX_LEN_0F5A_P_3 */
9568   {
9569     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9570     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9571   },
9572
9573   /* VEX_LEN_0F5C_P_1 */
9574   {
9575     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9576     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9577   },
9578
9579   /* VEX_LEN_0F5C_P_3 */
9580   {
9581     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9582     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9583   },
9584
9585   /* VEX_LEN_0F5D_P_1 */
9586   {
9587     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9588     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9589   },
9590
9591   /* VEX_LEN_0F5D_P_3 */
9592   {
9593     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9594     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9595   },
9596
9597   /* VEX_LEN_0F5E_P_1 */
9598   {
9599     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9600     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9601   },
9602
9603   /* VEX_LEN_0F5E_P_3 */
9604   {
9605     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9606     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9607   },
9608
9609   /* VEX_LEN_0F5F_P_1 */
9610   {
9611     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9612     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9613   },
9614
9615   /* VEX_LEN_0F5F_P_3 */
9616   {
9617     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9618     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9619   },
9620
9621   /* VEX_LEN_0F6E_P_2 */
9622   {
9623     { "vmovK",          { XMScalar, Edq }, 0 },
9624     { "vmovK",          { XMScalar, Edq }, 0 },
9625   },
9626
9627   /* VEX_LEN_0F7E_P_1 */
9628   {
9629     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9630     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9631   },
9632
9633   /* VEX_LEN_0F7E_P_2 */
9634   {
9635     { "vmovK",          { Edq, XMScalar }, 0 },
9636     { "vmovK",          { Edq, XMScalar }, 0 },
9637   },
9638
9639   /* VEX_LEN_0F90_P_0 */
9640   {
9641     { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9642   },
9643
9644   /* VEX_LEN_0F90_P_2 */
9645   {
9646     { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9647   },
9648
9649   /* VEX_LEN_0F91_P_0 */
9650   {
9651     { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9652   },
9653
9654   /* VEX_LEN_0F91_P_2 */
9655   {
9656     { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
9657   },
9658
9659   /* VEX_LEN_0F92_P_0 */
9660   {
9661     { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9662   },
9663
9664   /* VEX_LEN_0F92_P_2 */
9665   {
9666     { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
9667   },
9668
9669   /* VEX_LEN_0F92_P_3 */
9670   {
9671     { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0) },
9672   },
9673
9674   /* VEX_LEN_0F93_P_0 */
9675   {
9676     { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9677   },
9678
9679   /* VEX_LEN_0F93_P_2 */
9680   {
9681     { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
9682   },
9683
9684   /* VEX_LEN_0F93_P_3 */
9685   {
9686     { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0) },
9687   },
9688
9689   /* VEX_LEN_0F98_P_0 */
9690   {
9691     { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9692   },
9693
9694   /* VEX_LEN_0F98_P_2 */
9695   {
9696     { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
9697   },
9698
9699   /* VEX_LEN_0F99_P_0 */
9700   {
9701     { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
9702   },
9703
9704   /* VEX_LEN_0F99_P_2 */
9705   {
9706     { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
9707   },
9708
9709   /* VEX_LEN_0FAE_R_2_M_0 */
9710   {
9711     { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) },
9712   },
9713
9714   /* VEX_LEN_0FAE_R_3_M_0 */
9715   {
9716     { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) },
9717   },
9718
9719   /* VEX_LEN_0FC2_P_1 */
9720   {
9721     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9722     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9723   },
9724
9725   /* VEX_LEN_0FC2_P_3 */
9726   {
9727     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9728     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9729   },
9730
9731   /* VEX_LEN_0FC4_P_2 */
9732   {
9733     { VEX_W_TABLE (VEX_W_0FC4_P_2) },
9734   },
9735
9736   /* VEX_LEN_0FC5_P_2 */
9737   {
9738     { VEX_W_TABLE (VEX_W_0FC5_P_2) },
9739   },
9740
9741   /* VEX_LEN_0FD6_P_2 */
9742   {
9743     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9744     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9745   },
9746
9747   /* VEX_LEN_0FF7_P_2 */
9748   {
9749     { VEX_W_TABLE (VEX_W_0FF7_P_2) },
9750   },
9751
9752   /* VEX_LEN_0F3816_P_2 */
9753   {
9754     { Bad_Opcode },
9755     { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9756   },
9757
9758   /* VEX_LEN_0F3819_P_2 */
9759   {
9760     { Bad_Opcode },
9761     { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9762   },
9763
9764   /* VEX_LEN_0F381A_P_2_M_0 */
9765   {
9766     { Bad_Opcode },
9767     { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9768   },
9769
9770   /* VEX_LEN_0F3836_P_2 */
9771   {
9772     { Bad_Opcode },
9773     { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9774   },
9775
9776   /* VEX_LEN_0F3841_P_2 */
9777   {
9778     { VEX_W_TABLE (VEX_W_0F3841_P_2) },
9779   },
9780
9781   /* VEX_LEN_0F385A_P_2_M_0 */
9782   {
9783     { Bad_Opcode },
9784     { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
9785   },
9786
9787   /* VEX_LEN_0F38DB_P_2 */
9788   {
9789     { VEX_W_TABLE (VEX_W_0F38DB_P_2) },
9790   },
9791
9792   /* VEX_LEN_0F38DC_P_2 */
9793   {
9794     { VEX_W_TABLE (VEX_W_0F38DC_P_2) },
9795   },
9796
9797   /* VEX_LEN_0F38DD_P_2 */
9798   {
9799     { VEX_W_TABLE (VEX_W_0F38DD_P_2) },
9800   },
9801
9802   /* VEX_LEN_0F38DE_P_2 */
9803   {
9804     { VEX_W_TABLE (VEX_W_0F38DE_P_2) },
9805   },
9806
9807   /* VEX_LEN_0F38DF_P_2 */
9808   {
9809     { VEX_W_TABLE (VEX_W_0F38DF_P_2) },
9810   },
9811
9812   /* VEX_LEN_0F38F2_P_0 */
9813   {
9814     { "andnS",          { Gdq, VexGdq, Edq }, 0 },
9815   },
9816
9817   /* VEX_LEN_0F38F3_R_1_P_0 */
9818   {
9819     { "blsrS",          { VexGdq, Edq }, 0 },
9820   },
9821
9822   /* VEX_LEN_0F38F3_R_2_P_0 */
9823   {
9824     { "blsmskS",        { VexGdq, Edq }, 0 },
9825   },
9826
9827   /* VEX_LEN_0F38F3_R_3_P_0 */
9828   {
9829     { "blsiS",          { VexGdq, Edq }, 0 },
9830   },
9831
9832   /* VEX_LEN_0F38F5_P_0 */
9833   {
9834     { "bzhiS",          { Gdq, Edq, VexGdq }, 0 },
9835   },
9836
9837   /* VEX_LEN_0F38F5_P_1 */
9838   {
9839     { "pextS",          { Gdq, VexGdq, Edq }, 0 },
9840   },
9841
9842   /* VEX_LEN_0F38F5_P_3 */
9843   {
9844     { "pdepS",          { Gdq, VexGdq, Edq }, 0 },
9845   },
9846
9847   /* VEX_LEN_0F38F6_P_3 */
9848   {
9849     { "mulxS",          { Gdq, VexGdq, Edq }, 0 },
9850   },
9851
9852   /* VEX_LEN_0F38F7_P_0 */
9853   {
9854     { "bextrS",         { Gdq, Edq, VexGdq }, 0 },
9855   },
9856
9857   /* VEX_LEN_0F38F7_P_1 */
9858   {
9859     { "sarxS",          { Gdq, Edq, VexGdq }, 0 },
9860   },
9861
9862   /* VEX_LEN_0F38F7_P_2 */
9863   {
9864     { "shlxS",          { Gdq, Edq, VexGdq }, 0 },
9865   },
9866
9867   /* VEX_LEN_0F38F7_P_3 */
9868   {
9869     { "shrxS",          { Gdq, Edq, VexGdq }, 0 },
9870   },
9871
9872   /* VEX_LEN_0F3A00_P_2 */
9873   {
9874     { Bad_Opcode },
9875     { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
9876   },
9877
9878   /* VEX_LEN_0F3A01_P_2 */
9879   {
9880     { Bad_Opcode },
9881     { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
9882   },
9883
9884   /* VEX_LEN_0F3A06_P_2 */
9885   {
9886     { Bad_Opcode },
9887     { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
9888   },
9889
9890   /* VEX_LEN_0F3A0A_P_2 */
9891   {
9892     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
9893     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
9894   },
9895
9896   /* VEX_LEN_0F3A0B_P_2 */
9897   {
9898     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
9899     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
9900   },
9901
9902   /* VEX_LEN_0F3A14_P_2 */
9903   {
9904     { VEX_W_TABLE (VEX_W_0F3A14_P_2) },
9905   },
9906
9907   /* VEX_LEN_0F3A15_P_2 */
9908   {
9909     { VEX_W_TABLE (VEX_W_0F3A15_P_2) },
9910   },
9911
9912   /* VEX_LEN_0F3A16_P_2  */
9913   {
9914     { "vpextrK",        { Edq, XM, Ib }, 0 },
9915   },
9916
9917   /* VEX_LEN_0F3A17_P_2 */
9918   {
9919     { "vextractps",     { Edqd, XM, Ib }, 0 },
9920   },
9921
9922   /* VEX_LEN_0F3A18_P_2 */
9923   {
9924     { Bad_Opcode },
9925     { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
9926   },
9927
9928   /* VEX_LEN_0F3A19_P_2 */
9929   {
9930     { Bad_Opcode },
9931     { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
9932   },
9933
9934   /* VEX_LEN_0F3A20_P_2 */
9935   {
9936     { VEX_W_TABLE (VEX_W_0F3A20_P_2) },
9937   },
9938
9939   /* VEX_LEN_0F3A21_P_2 */
9940   {
9941     { VEX_W_TABLE (VEX_W_0F3A21_P_2) },
9942   },
9943
9944   /* VEX_LEN_0F3A22_P_2 */
9945   {
9946     { "vpinsrK",        { XM, Vex128, Edq, Ib }, 0 },
9947   },
9948
9949   /* VEX_LEN_0F3A30_P_2 */
9950   {
9951     { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
9952   },
9953
9954   /* VEX_LEN_0F3A31_P_2 */
9955   {
9956     { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
9957   },
9958
9959   /* VEX_LEN_0F3A32_P_2 */
9960   {
9961     { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
9962   },
9963
9964   /* VEX_LEN_0F3A33_P_2 */
9965   {
9966     { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
9967   },
9968
9969   /* VEX_LEN_0F3A38_P_2 */
9970   {
9971     { Bad_Opcode },
9972     { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
9973   },
9974
9975   /* VEX_LEN_0F3A39_P_2 */
9976   {
9977     { Bad_Opcode },
9978     { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
9979   },
9980
9981   /* VEX_LEN_0F3A41_P_2 */
9982   {
9983     { VEX_W_TABLE (VEX_W_0F3A41_P_2) },
9984   },
9985
9986   /* VEX_LEN_0F3A44_P_2 */
9987   {
9988     { VEX_W_TABLE (VEX_W_0F3A44_P_2) },
9989   },
9990
9991   /* VEX_LEN_0F3A46_P_2 */
9992   {
9993     { Bad_Opcode },
9994     { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
9995   },
9996
9997   /* VEX_LEN_0F3A60_P_2 */
9998   {
9999     { VEX_W_TABLE (VEX_W_0F3A60_P_2) },
10000   },
10001
10002   /* VEX_LEN_0F3A61_P_2 */
10003   {
10004     { VEX_W_TABLE (VEX_W_0F3A61_P_2) },
10005   },
10006
10007   /* VEX_LEN_0F3A62_P_2 */
10008   {
10009     { VEX_W_TABLE (VEX_W_0F3A62_P_2) },
10010   },
10011
10012   /* VEX_LEN_0F3A63_P_2 */
10013   {
10014     { VEX_W_TABLE (VEX_W_0F3A63_P_2) },
10015   },
10016
10017   /* VEX_LEN_0F3A6A_P_2 */
10018   {
10019     { "vfmaddss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10020   },
10021
10022   /* VEX_LEN_0F3A6B_P_2 */
10023   {
10024     { "vfmaddsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10025   },
10026
10027   /* VEX_LEN_0F3A6E_P_2 */
10028   {
10029     { "vfmsubss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10030   },
10031
10032   /* VEX_LEN_0F3A6F_P_2 */
10033   {
10034     { "vfmsubsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10035   },
10036
10037   /* VEX_LEN_0F3A7A_P_2 */
10038   {
10039     { "vfnmaddss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10040   },
10041
10042   /* VEX_LEN_0F3A7B_P_2 */
10043   {
10044     { "vfnmaddsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10045   },
10046
10047   /* VEX_LEN_0F3A7E_P_2 */
10048   {
10049     { "vfnmsubss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10050   },
10051
10052   /* VEX_LEN_0F3A7F_P_2 */
10053   {
10054     { "vfnmsubsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10055   },
10056
10057   /* VEX_LEN_0F3ADF_P_2 */
10058   {
10059     { VEX_W_TABLE (VEX_W_0F3ADF_P_2) },
10060   },
10061
10062   /* VEX_LEN_0F3AF0_P_3 */
10063   {
10064     { "rorxS",          { Gdq, Edq, Ib }, 0 },
10065   },
10066
10067   /* VEX_LEN_0FXOP_08_CC */
10068   {
10069      { "vpcomb",        { XM, Vex128, EXx, Ib }, 0 },
10070   },
10071
10072   /* VEX_LEN_0FXOP_08_CD */
10073   {
10074      { "vpcomw",        { XM, Vex128, EXx, Ib }, 0 },
10075   },
10076
10077   /* VEX_LEN_0FXOP_08_CE */
10078   {
10079      { "vpcomd",        { XM, Vex128, EXx, Ib }, 0 },
10080   },
10081
10082   /* VEX_LEN_0FXOP_08_CF */
10083   {
10084      { "vpcomq",        { XM, Vex128, EXx, Ib }, 0 },
10085   },
10086
10087   /* VEX_LEN_0FXOP_08_EC */
10088   {
10089      { "vpcomub",       { XM, Vex128, EXx, Ib }, 0 },
10090   },
10091
10092   /* VEX_LEN_0FXOP_08_ED */
10093   {
10094      { "vpcomuw",       { XM, Vex128, EXx, Ib }, 0 },
10095   },
10096
10097   /* VEX_LEN_0FXOP_08_EE */
10098   {
10099      { "vpcomud",       { XM, Vex128, EXx, Ib }, 0 },
10100   },
10101
10102   /* VEX_LEN_0FXOP_08_EF */
10103   {
10104      { "vpcomuq",       { XM, Vex128, EXx, Ib }, 0 },
10105   },
10106
10107   /* VEX_LEN_0FXOP_09_80 */
10108   {
10109     { "vfrczps",        { XM, EXxmm }, 0 },
10110     { "vfrczps",        { XM, EXymmq }, 0 },
10111   },
10112
10113   /* VEX_LEN_0FXOP_09_81 */
10114   {
10115     { "vfrczpd",        { XM, EXxmm }, 0 },
10116     { "vfrczpd",        { XM, EXymmq }, 0 },
10117   },
10118 };
10119
10120 static const struct dis386 vex_w_table[][2] = {
10121   {
10122     /* VEX_W_0F10_P_0 */
10123     { "vmovups",        { XM, EXx }, 0 },
10124   },
10125   {
10126     /* VEX_W_0F10_P_1 */
10127     { "vmovss",         { XMVexScalar, VexScalar, EXdScalar }, 0 },
10128   },
10129   {
10130     /* VEX_W_0F10_P_2 */
10131     { "vmovupd",        { XM, EXx }, 0 },
10132   },
10133   {
10134     /* VEX_W_0F10_P_3 */
10135     { "vmovsd",         { XMVexScalar, VexScalar, EXqScalar }, 0 },
10136   },
10137   {
10138     /* VEX_W_0F11_P_0 */
10139     { "vmovups",        { EXxS, XM }, 0 },
10140   },
10141   {
10142     /* VEX_W_0F11_P_1 */
10143     { "vmovss",         { EXdVexScalarS, VexScalar, XMScalar }, 0 },
10144   },
10145   {
10146     /* VEX_W_0F11_P_2 */
10147     { "vmovupd",        { EXxS, XM }, 0 },
10148   },
10149   {
10150     /* VEX_W_0F11_P_3 */
10151     { "vmovsd",         { EXqVexScalarS, VexScalar, XMScalar }, 0 },
10152   },
10153   {
10154     /* VEX_W_0F12_P_0_M_0 */
10155     { "vmovlps",        { XM, Vex128, EXq }, 0 },
10156   },
10157   {
10158     /* VEX_W_0F12_P_0_M_1 */
10159     { "vmovhlps",       { XM, Vex128, EXq }, 0 },
10160   },
10161   {
10162     /* VEX_W_0F12_P_1 */
10163     { "vmovsldup",      { XM, EXx }, 0 },
10164   },
10165   {
10166     /* VEX_W_0F12_P_2 */
10167     { "vmovlpd",        { XM, Vex128, EXq }, 0 },
10168   },
10169   {
10170     /* VEX_W_0F12_P_3 */
10171     { "vmovddup",       { XM, EXymmq }, 0 },
10172   },
10173   {
10174     /* VEX_W_0F13_M_0 */
10175     { "vmovlpX",        { EXq, XM }, 0 },
10176   },
10177   {
10178     /* VEX_W_0F14 */
10179     { "vunpcklpX",      { XM, Vex, EXx }, 0 },
10180   },
10181   {
10182     /* VEX_W_0F15 */
10183     { "vunpckhpX",      { XM, Vex, EXx }, 0 },
10184   },
10185   {
10186     /* VEX_W_0F16_P_0_M_0 */
10187     { "vmovhps",        { XM, Vex128, EXq }, 0 },
10188   },
10189   {
10190     /* VEX_W_0F16_P_0_M_1 */
10191     { "vmovlhps",       { XM, Vex128, EXq }, 0 },
10192   },
10193   {
10194     /* VEX_W_0F16_P_1 */
10195     { "vmovshdup",      { XM, EXx }, 0 },
10196   },
10197   {
10198     /* VEX_W_0F16_P_2 */
10199     { "vmovhpd",        { XM, Vex128, EXq }, 0 },
10200   },
10201   {
10202     /* VEX_W_0F17_M_0 */
10203     { "vmovhpX",        { EXq, XM }, 0 },
10204   },
10205   {
10206     /* VEX_W_0F28 */
10207     { "vmovapX",        { XM, EXx }, 0 },
10208   },
10209   {
10210     /* VEX_W_0F29 */
10211     { "vmovapX",        { EXxS, XM }, 0 },
10212   },
10213   {
10214     /* VEX_W_0F2B_M_0 */
10215     { "vmovntpX",       { Mx, XM }, 0 },
10216   },
10217   {
10218     /* VEX_W_0F2E_P_0 */
10219     { "vucomiss",       { XMScalar, EXdScalar }, 0 },
10220   },
10221   {
10222     /* VEX_W_0F2E_P_2 */
10223     { "vucomisd",       { XMScalar, EXqScalar }, 0 },
10224   },
10225   {
10226     /* VEX_W_0F2F_P_0 */
10227     { "vcomiss",        { XMScalar, EXdScalar }, 0 },
10228   },
10229   {
10230     /* VEX_W_0F2F_P_2 */
10231     { "vcomisd",        { XMScalar, EXqScalar }, 0 },
10232   },
10233   {
10234     /* VEX_W_0F41_P_0_LEN_1 */
10235     { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
10236     { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) },
10237   },
10238   {
10239     /* VEX_W_0F41_P_2_LEN_1 */
10240     { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) },
10241     { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) }
10242   },
10243   {
10244     /* VEX_W_0F42_P_0_LEN_1 */
10245     { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) },
10246     { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) },
10247   },
10248   {
10249     /* VEX_W_0F42_P_2_LEN_1 */
10250     { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) },
10251     { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) },
10252   },
10253   {
10254     /* VEX_W_0F44_P_0_LEN_0 */
10255     { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) },
10256     { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) },
10257   },
10258   {
10259     /* VEX_W_0F44_P_2_LEN_0 */
10260     { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) },
10261     { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) },
10262   },
10263   {
10264     /* VEX_W_0F45_P_0_LEN_1 */
10265     { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) },
10266     { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) },
10267   },
10268   {
10269     /* VEX_W_0F45_P_2_LEN_1 */
10270     { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) },
10271     { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) },
10272   },
10273   {
10274     /* VEX_W_0F46_P_0_LEN_1 */
10275     { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) },
10276     { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) },
10277   },
10278   {
10279     /* VEX_W_0F46_P_2_LEN_1 */
10280     { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) },
10281     { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) },
10282   },
10283   {
10284     /* VEX_W_0F47_P_0_LEN_1 */
10285     { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) },
10286     { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) },
10287   },
10288   {
10289     /* VEX_W_0F47_P_2_LEN_1 */
10290     { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) },
10291     { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) },
10292   },
10293   {
10294     /* VEX_W_0F4A_P_0_LEN_1 */
10295     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) },
10296     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) },
10297   },
10298   {
10299     /* VEX_W_0F4A_P_2_LEN_1 */
10300     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) },
10301     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) },
10302   },
10303   {
10304     /* VEX_W_0F4B_P_0_LEN_1 */
10305     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) },
10306     { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) },
10307   },
10308   {
10309     /* VEX_W_0F4B_P_2_LEN_1 */
10310     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
10311   },
10312   {
10313     /* VEX_W_0F50_M_0 */
10314     { "vmovmskpX",      { Gdq, XS }, 0 },
10315   },
10316   {
10317     /* VEX_W_0F51_P_0 */
10318     { "vsqrtps",        { XM, EXx }, 0 },
10319   },
10320   {
10321     /* VEX_W_0F51_P_1 */
10322     { "vsqrtss",        { XMScalar, VexScalar, EXdScalar }, 0 },
10323   },
10324   {
10325     /* VEX_W_0F51_P_2  */
10326     { "vsqrtpd",        { XM, EXx }, 0 },
10327   },
10328   {
10329     /* VEX_W_0F51_P_3 */
10330     { "vsqrtsd",        { XMScalar, VexScalar, EXqScalar }, 0 },
10331   },
10332   {
10333     /* VEX_W_0F52_P_0 */
10334     { "vrsqrtps",       { XM, EXx }, 0 },
10335   },
10336   {
10337     /* VEX_W_0F52_P_1 */
10338     { "vrsqrtss",       { XMScalar, VexScalar, EXdScalar }, 0 },
10339   },
10340   {
10341     /* VEX_W_0F53_P_0  */
10342     { "vrcpps",         { XM, EXx }, 0 },
10343   },
10344   {
10345     /* VEX_W_0F53_P_1  */
10346     { "vrcpss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10347   },
10348   {
10349     /* VEX_W_0F58_P_0  */
10350     { "vaddps",         { XM, Vex, EXx }, 0 },
10351   },
10352   {
10353     /* VEX_W_0F58_P_1  */
10354     { "vaddss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10355   },
10356   {
10357     /* VEX_W_0F58_P_2  */
10358     { "vaddpd",         { XM, Vex, EXx }, 0 },
10359   },
10360   {
10361     /* VEX_W_0F58_P_3  */
10362     { "vaddsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10363   },
10364   {
10365     /* VEX_W_0F59_P_0  */
10366     { "vmulps",         { XM, Vex, EXx }, 0 },
10367   },
10368   {
10369     /* VEX_W_0F59_P_1  */
10370     { "vmulss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10371   },
10372   {
10373     /* VEX_W_0F59_P_2  */
10374     { "vmulpd",         { XM, Vex, EXx }, 0 },
10375   },
10376   {
10377     /* VEX_W_0F59_P_3  */
10378     { "vmulsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10379   },
10380   {
10381     /* VEX_W_0F5A_P_0  */
10382     { "vcvtps2pd",      { XM, EXxmmq }, 0 },
10383   },
10384   {
10385     /* VEX_W_0F5A_P_1  */
10386     { "vcvtss2sd",      { XMScalar, VexScalar, EXdScalar }, 0 },
10387   },
10388   {
10389     /* VEX_W_0F5A_P_3  */
10390     { "vcvtsd2ss",      { XMScalar, VexScalar, EXqScalar }, 0 },
10391   },
10392   {
10393     /* VEX_W_0F5B_P_0  */
10394     { "vcvtdq2ps",      { XM, EXx }, 0 },
10395   },
10396   {
10397     /* VEX_W_0F5B_P_1  */
10398     { "vcvttps2dq",     { XM, EXx }, 0 },
10399   },
10400   {
10401     /* VEX_W_0F5B_P_2  */
10402     { "vcvtps2dq",      { XM, EXx }, 0 },
10403   },
10404   {
10405     /* VEX_W_0F5C_P_0  */
10406     { "vsubps",         { XM, Vex, EXx }, 0 },
10407   },
10408   {
10409     /* VEX_W_0F5C_P_1  */
10410     { "vsubss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10411   },
10412   {
10413     /* VEX_W_0F5C_P_2  */
10414     { "vsubpd",         { XM, Vex, EXx }, 0 },
10415   },
10416   {
10417     /* VEX_W_0F5C_P_3  */
10418     { "vsubsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10419   },
10420   {
10421     /* VEX_W_0F5D_P_0  */
10422     { "vminps",         { XM, Vex, EXx }, 0 },
10423   },
10424   {
10425     /* VEX_W_0F5D_P_1  */
10426     { "vminss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10427   },
10428   {
10429     /* VEX_W_0F5D_P_2  */
10430     { "vminpd",         { XM, Vex, EXx }, 0 },
10431   },
10432   {
10433     /* VEX_W_0F5D_P_3  */
10434     { "vminsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10435   },
10436   {
10437     /* VEX_W_0F5E_P_0  */
10438     { "vdivps",         { XM, Vex, EXx }, 0 },
10439   },
10440   {
10441     /* VEX_W_0F5E_P_1  */
10442     { "vdivss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10443   },
10444   {
10445     /* VEX_W_0F5E_P_2  */
10446     { "vdivpd",         { XM, Vex, EXx }, 0 },
10447   },
10448   {
10449     /* VEX_W_0F5E_P_3  */
10450     { "vdivsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10451   },
10452   {
10453     /* VEX_W_0F5F_P_0  */
10454     { "vmaxps",         { XM, Vex, EXx }, 0 },
10455   },
10456   {
10457     /* VEX_W_0F5F_P_1  */
10458     { "vmaxss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10459   },
10460   {
10461     /* VEX_W_0F5F_P_2  */
10462     { "vmaxpd",         { XM, Vex, EXx }, 0 },
10463   },
10464   {
10465     /* VEX_W_0F5F_P_3  */
10466     { "vmaxsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10467   },
10468   {
10469     /* VEX_W_0F60_P_2  */
10470     { "vpunpcklbw",     { XM, Vex, EXx }, 0 },
10471   },
10472   {
10473     /* VEX_W_0F61_P_2  */
10474     { "vpunpcklwd",     { XM, Vex, EXx }, 0 },
10475   },
10476   {
10477     /* VEX_W_0F62_P_2  */
10478     { "vpunpckldq",     { XM, Vex, EXx }, 0 },
10479   },
10480   {
10481     /* VEX_W_0F63_P_2  */
10482     { "vpacksswb",      { XM, Vex, EXx }, 0 },
10483   },
10484   {
10485     /* VEX_W_0F64_P_2  */
10486     { "vpcmpgtb",       { XM, Vex, EXx }, 0 },
10487   },
10488   {
10489     /* VEX_W_0F65_P_2  */
10490     { "vpcmpgtw",       { XM, Vex, EXx }, 0 },
10491   },
10492   {
10493     /* VEX_W_0F66_P_2  */
10494     { "vpcmpgtd",       { XM, Vex, EXx }, 0 },
10495   },
10496   {
10497     /* VEX_W_0F67_P_2  */
10498     { "vpackuswb",      { XM, Vex, EXx }, 0 },
10499   },
10500   {
10501     /* VEX_W_0F68_P_2  */
10502     { "vpunpckhbw",     { XM, Vex, EXx }, 0 },
10503   },
10504   {
10505     /* VEX_W_0F69_P_2  */
10506     { "vpunpckhwd",     { XM, Vex, EXx }, 0 },
10507   },
10508   {
10509     /* VEX_W_0F6A_P_2  */
10510     { "vpunpckhdq",     { XM, Vex, EXx }, 0 },
10511   },
10512   {
10513     /* VEX_W_0F6B_P_2  */
10514     { "vpackssdw",      { XM, Vex, EXx }, 0 },
10515   },
10516   {
10517     /* VEX_W_0F6C_P_2  */
10518     { "vpunpcklqdq",    { XM, Vex, EXx }, 0 },
10519   },
10520   {
10521     /* VEX_W_0F6D_P_2  */
10522     { "vpunpckhqdq",    { XM, Vex, EXx }, 0 },
10523   },
10524   {
10525     /* VEX_W_0F6F_P_1  */
10526     { "vmovdqu",        { XM, EXx }, 0 },
10527   },
10528   {
10529     /* VEX_W_0F6F_P_2  */
10530     { "vmovdqa",        { XM, EXx }, 0 },
10531   },
10532   {
10533     /* VEX_W_0F70_P_1 */
10534     { "vpshufhw",       { XM, EXx, Ib }, 0 },
10535   },
10536   {
10537     /* VEX_W_0F70_P_2 */
10538     { "vpshufd",        { XM, EXx, Ib }, 0 },
10539   },
10540   {
10541     /* VEX_W_0F70_P_3 */
10542     { "vpshuflw",       { XM, EXx, Ib }, 0 },
10543   },
10544   {
10545     /* VEX_W_0F71_R_2_P_2  */
10546     { "vpsrlw",         { Vex, XS, Ib }, 0 },
10547   },
10548   {
10549     /* VEX_W_0F71_R_4_P_2  */
10550     { "vpsraw",         { Vex, XS, Ib }, 0 },
10551   },
10552   {
10553     /* VEX_W_0F71_R_6_P_2  */
10554     { "vpsllw",         { Vex, XS, Ib }, 0 },
10555   },
10556   {
10557     /* VEX_W_0F72_R_2_P_2  */
10558     { "vpsrld",         { Vex, XS, Ib }, 0 },
10559   },
10560   {
10561     /* VEX_W_0F72_R_4_P_2  */
10562     { "vpsrad",         { Vex, XS, Ib }, 0 },
10563   },
10564   {
10565     /* VEX_W_0F72_R_6_P_2  */
10566     { "vpslld",         { Vex, XS, Ib }, 0 },
10567   },
10568   {
10569     /* VEX_W_0F73_R_2_P_2  */
10570     { "vpsrlq",         { Vex, XS, Ib }, 0 },
10571   },
10572   {
10573     /* VEX_W_0F73_R_3_P_2  */
10574     { "vpsrldq",        { Vex, XS, Ib }, 0 },
10575   },
10576   {
10577     /* VEX_W_0F73_R_6_P_2  */
10578     { "vpsllq",         { Vex, XS, Ib }, 0 },
10579   },
10580   {
10581     /* VEX_W_0F73_R_7_P_2  */
10582     { "vpslldq",        { Vex, XS, Ib }, 0 },
10583   },
10584   {
10585     /* VEX_W_0F74_P_2 */
10586     { "vpcmpeqb",       { XM, Vex, EXx }, 0 },
10587   },
10588   {
10589     /* VEX_W_0F75_P_2 */
10590     { "vpcmpeqw",       { XM, Vex, EXx }, 0 },
10591   },
10592   {
10593     /* VEX_W_0F76_P_2 */
10594     { "vpcmpeqd",       { XM, Vex, EXx }, 0 },
10595   },
10596   {
10597     /* VEX_W_0F77_P_0 */
10598     { "",               { VZERO }, 0 },
10599   },
10600   {
10601     /* VEX_W_0F7C_P_2 */
10602     { "vhaddpd",        { XM, Vex, EXx }, 0 },
10603   },
10604   {
10605     /* VEX_W_0F7C_P_3 */
10606     { "vhaddps",        { XM, Vex, EXx }, 0 },
10607   },
10608   {
10609     /* VEX_W_0F7D_P_2 */
10610     { "vhsubpd",        { XM, Vex, EXx }, 0 },
10611   },
10612   {
10613     /* VEX_W_0F7D_P_3 */
10614     { "vhsubps",        { XM, Vex, EXx }, 0 },
10615   },
10616   {
10617     /* VEX_W_0F7E_P_1 */
10618     { "vmovq",          { XMScalar, EXqScalar }, 0 },
10619   },
10620   {
10621     /* VEX_W_0F7F_P_1 */
10622     { "vmovdqu",        { EXxS, XM }, 0 },
10623   },
10624   {
10625     /* VEX_W_0F7F_P_2 */
10626     { "vmovdqa",        { EXxS, XM }, 0 },
10627   },
10628   {
10629     /* VEX_W_0F90_P_0_LEN_0 */
10630     { "kmovw",          { MaskG, MaskE }, 0 },
10631     { "kmovq",          { MaskG, MaskE }, 0 },
10632   },
10633   {
10634     /* VEX_W_0F90_P_2_LEN_0 */
10635     { "kmovb",          { MaskG, MaskBDE }, 0 },
10636     { "kmovd",          { MaskG, MaskBDE }, 0 },
10637   },
10638   {
10639     /* VEX_W_0F91_P_0_LEN_0 */
10640     { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
10641     { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
10642   },
10643   {
10644     /* VEX_W_0F91_P_2_LEN_0 */
10645     { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
10646     { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
10647   },
10648   {
10649     /* VEX_W_0F92_P_0_LEN_0 */
10650     { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
10651   },
10652   {
10653     /* VEX_W_0F92_P_2_LEN_0 */
10654     { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
10655   },
10656   {
10657     /* VEX_W_0F92_P_3_LEN_0 */
10658     { MOD_TABLE (MOD_VEX_W_0_0F92_P_3_LEN_0) },
10659     { MOD_TABLE (MOD_VEX_W_1_0F92_P_3_LEN_0) },
10660   },
10661   {
10662     /* VEX_W_0F93_P_0_LEN_0 */
10663     { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
10664   },
10665   {
10666     /* VEX_W_0F93_P_2_LEN_0 */
10667     { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
10668   },
10669   {
10670     /* VEX_W_0F93_P_3_LEN_0 */
10671     { MOD_TABLE (MOD_VEX_W_0_0F93_P_3_LEN_0) },
10672     { MOD_TABLE (MOD_VEX_W_1_0F93_P_3_LEN_0) },
10673   },
10674   {
10675     /* VEX_W_0F98_P_0_LEN_0 */
10676     { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
10677     { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
10678   },
10679   {
10680     /* VEX_W_0F98_P_2_LEN_0 */
10681     { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
10682     { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
10683   },
10684   {
10685     /* VEX_W_0F99_P_0_LEN_0 */
10686     { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
10687     { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
10688   },
10689   {
10690     /* VEX_W_0F99_P_2_LEN_0 */
10691     { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
10692     { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
10693   },
10694   {
10695     /* VEX_W_0FAE_R_2_M_0 */
10696     { "vldmxcsr",       { Md }, 0 },
10697   },
10698   {
10699     /* VEX_W_0FAE_R_3_M_0 */
10700     { "vstmxcsr",       { Md }, 0 },
10701   },
10702   {
10703     /* VEX_W_0FC2_P_0 */
10704     { "vcmpps",         { XM, Vex, EXx, VCMP }, 0 },
10705   },
10706   {
10707     /* VEX_W_0FC2_P_1 */
10708     { "vcmpss",         { XMScalar, VexScalar, EXdScalar, VCMP }, 0 },
10709   },
10710   {
10711     /* VEX_W_0FC2_P_2 */
10712     { "vcmppd",         { XM, Vex, EXx, VCMP }, 0 },
10713   },
10714   {
10715     /* VEX_W_0FC2_P_3 */
10716     { "vcmpsd",         { XMScalar, VexScalar, EXqScalar, VCMP }, 0 },
10717   },
10718   {
10719     /* VEX_W_0FC4_P_2 */
10720     { "vpinsrw",        { XM, Vex128, Edqw, Ib }, 0 },
10721   },
10722   {
10723     /* VEX_W_0FC5_P_2 */
10724     { "vpextrw",        { Gdq, XS, Ib }, 0 },
10725   },
10726   {
10727     /* VEX_W_0FD0_P_2 */
10728     { "vaddsubpd",      { XM, Vex, EXx }, 0 },
10729   },
10730   {
10731     /* VEX_W_0FD0_P_3 */
10732     { "vaddsubps",      { XM, Vex, EXx }, 0 },
10733   },
10734   {
10735     /* VEX_W_0FD1_P_2 */
10736     { "vpsrlw",         { XM, Vex, EXxmm }, 0 },
10737   },
10738   {
10739     /* VEX_W_0FD2_P_2 */
10740     { "vpsrld",         { XM, Vex, EXxmm }, 0 },
10741   },
10742   {
10743     /* VEX_W_0FD3_P_2 */
10744     { "vpsrlq",         { XM, Vex, EXxmm }, 0 },
10745   },
10746   {
10747     /* VEX_W_0FD4_P_2 */
10748     { "vpaddq",         { XM, Vex, EXx }, 0 },
10749   },
10750   {
10751     /* VEX_W_0FD5_P_2 */
10752     { "vpmullw",        { XM, Vex, EXx }, 0 },
10753   },
10754   {
10755     /* VEX_W_0FD6_P_2 */
10756     { "vmovq",          { EXqScalarS, XMScalar }, 0 },
10757   },
10758   {
10759     /* VEX_W_0FD7_P_2_M_1 */
10760     { "vpmovmskb",      { Gdq, XS }, 0 },
10761   },
10762   {
10763     /* VEX_W_0FD8_P_2 */
10764     { "vpsubusb",       { XM, Vex, EXx }, 0 },
10765   },
10766   {
10767     /* VEX_W_0FD9_P_2 */
10768     { "vpsubusw",       { XM, Vex, EXx }, 0 },
10769   },
10770   {
10771     /* VEX_W_0FDA_P_2 */
10772     { "vpminub",        { XM, Vex, EXx }, 0 },
10773   },
10774   {
10775     /* VEX_W_0FDB_P_2 */
10776     { "vpand",          { XM, Vex, EXx }, 0 },
10777   },
10778   {
10779     /* VEX_W_0FDC_P_2 */
10780     { "vpaddusb",       { XM, Vex, EXx }, 0 },
10781   },
10782   {
10783     /* VEX_W_0FDD_P_2 */
10784     { "vpaddusw",       { XM, Vex, EXx }, 0 },
10785   },
10786   {
10787     /* VEX_W_0FDE_P_2 */
10788     { "vpmaxub",        { XM, Vex, EXx }, 0 },
10789   },
10790   {
10791     /* VEX_W_0FDF_P_2 */
10792     { "vpandn",         { XM, Vex, EXx }, 0 },
10793   },
10794   {
10795     /* VEX_W_0FE0_P_2  */
10796     { "vpavgb",         { XM, Vex, EXx }, 0 },
10797   },
10798   {
10799     /* VEX_W_0FE1_P_2  */
10800     { "vpsraw",         { XM, Vex, EXxmm }, 0 },
10801   },
10802   {
10803     /* VEX_W_0FE2_P_2  */
10804     { "vpsrad",         { XM, Vex, EXxmm }, 0 },
10805   },
10806   {
10807     /* VEX_W_0FE3_P_2  */
10808     { "vpavgw",         { XM, Vex, EXx }, 0 },
10809   },
10810   {
10811     /* VEX_W_0FE4_P_2  */
10812     { "vpmulhuw",       { XM, Vex, EXx }, 0 },
10813   },
10814   {
10815     /* VEX_W_0FE5_P_2  */
10816     { "vpmulhw",        { XM, Vex, EXx }, 0 },
10817   },
10818   {
10819     /* VEX_W_0FE6_P_1  */
10820     { "vcvtdq2pd",      { XM, EXxmmq }, 0 },
10821   },
10822   {
10823     /* VEX_W_0FE6_P_2  */
10824     { "vcvttpd2dq%XY",  { XMM, EXx }, 0 },
10825   },
10826   {
10827     /* VEX_W_0FE6_P_3  */
10828     { "vcvtpd2dq%XY",   { XMM, EXx }, 0 },
10829   },
10830   {
10831     /* VEX_W_0FE7_P_2_M_0 */
10832     { "vmovntdq",       { Mx, XM }, 0 },
10833   },
10834   {
10835     /* VEX_W_0FE8_P_2  */
10836     { "vpsubsb",        { XM, Vex, EXx }, 0 },
10837   },
10838   {
10839     /* VEX_W_0FE9_P_2  */
10840     { "vpsubsw",        { XM, Vex, EXx }, 0 },
10841   },
10842   {
10843     /* VEX_W_0FEA_P_2  */
10844     { "vpminsw",        { XM, Vex, EXx }, 0 },
10845   },
10846   {
10847     /* VEX_W_0FEB_P_2  */
10848     { "vpor",           { XM, Vex, EXx }, 0 },
10849   },
10850   {
10851     /* VEX_W_0FEC_P_2  */
10852     { "vpaddsb",        { XM, Vex, EXx }, 0 },
10853   },
10854   {
10855     /* VEX_W_0FED_P_2  */
10856     { "vpaddsw",        { XM, Vex, EXx }, 0 },
10857   },
10858   {
10859     /* VEX_W_0FEE_P_2  */
10860     { "vpmaxsw",        { XM, Vex, EXx }, 0 },
10861   },
10862   {
10863     /* VEX_W_0FEF_P_2  */
10864     { "vpxor",          { XM, Vex, EXx }, 0 },
10865   },
10866   {
10867     /* VEX_W_0FF0_P_3_M_0 */
10868     { "vlddqu",         { XM, M }, 0 },
10869   },
10870   {
10871     /* VEX_W_0FF1_P_2 */
10872     { "vpsllw",         { XM, Vex, EXxmm }, 0 },
10873   },
10874   {
10875     /* VEX_W_0FF2_P_2 */
10876     { "vpslld",         { XM, Vex, EXxmm }, 0 },
10877   },
10878   {
10879     /* VEX_W_0FF3_P_2 */
10880     { "vpsllq",         { XM, Vex, EXxmm }, 0 },
10881   },
10882   {
10883     /* VEX_W_0FF4_P_2 */
10884     { "vpmuludq",       { XM, Vex, EXx }, 0 },
10885   },
10886   {
10887     /* VEX_W_0FF5_P_2 */
10888     { "vpmaddwd",       { XM, Vex, EXx }, 0 },
10889   },
10890   {
10891     /* VEX_W_0FF6_P_2 */
10892     { "vpsadbw",        { XM, Vex, EXx }, 0 },
10893   },
10894   {
10895     /* VEX_W_0FF7_P_2 */
10896     { "vmaskmovdqu",    { XM, XS }, 0 },
10897   },
10898   {
10899     /* VEX_W_0FF8_P_2 */
10900     { "vpsubb",         { XM, Vex, EXx }, 0 },
10901   },
10902   {
10903     /* VEX_W_0FF9_P_2 */
10904     { "vpsubw",         { XM, Vex, EXx }, 0 },
10905   },
10906   {
10907     /* VEX_W_0FFA_P_2 */
10908     { "vpsubd",         { XM, Vex, EXx }, 0 },
10909   },
10910   {
10911     /* VEX_W_0FFB_P_2 */
10912     { "vpsubq",         { XM, Vex, EXx }, 0 },
10913   },
10914   {
10915     /* VEX_W_0FFC_P_2 */
10916     { "vpaddb",         { XM, Vex, EXx }, 0 },
10917   },
10918   {
10919     /* VEX_W_0FFD_P_2 */
10920     { "vpaddw",         { XM, Vex, EXx }, 0 },
10921   },
10922   {
10923     /* VEX_W_0FFE_P_2 */
10924     { "vpaddd",         { XM, Vex, EXx }, 0 },
10925   },
10926   {
10927     /* VEX_W_0F3800_P_2  */
10928     { "vpshufb",        { XM, Vex, EXx }, 0 },
10929   },
10930   {
10931     /* VEX_W_0F3801_P_2  */
10932     { "vphaddw",        { XM, Vex, EXx }, 0 },
10933   },
10934   {
10935     /* VEX_W_0F3802_P_2  */
10936     { "vphaddd",        { XM, Vex, EXx }, 0 },
10937   },
10938   {
10939     /* VEX_W_0F3803_P_2  */
10940     { "vphaddsw",       { XM, Vex, EXx }, 0 },
10941   },
10942   {
10943     /* VEX_W_0F3804_P_2  */
10944     { "vpmaddubsw",     { XM, Vex, EXx }, 0 },
10945   },
10946   {
10947     /* VEX_W_0F3805_P_2  */
10948     { "vphsubw",        { XM, Vex, EXx }, 0 },
10949   },
10950   {
10951     /* VEX_W_0F3806_P_2  */
10952     { "vphsubd",        { XM, Vex, EXx }, 0 },
10953   },
10954   {
10955     /* VEX_W_0F3807_P_2  */
10956     { "vphsubsw",       { XM, Vex, EXx }, 0 },
10957   },
10958   {
10959     /* VEX_W_0F3808_P_2  */
10960     { "vpsignb",        { XM, Vex, EXx }, 0 },
10961   },
10962   {
10963     /* VEX_W_0F3809_P_2  */
10964     { "vpsignw",        { XM, Vex, EXx }, 0 },
10965   },
10966   {
10967     /* VEX_W_0F380A_P_2  */
10968     { "vpsignd",        { XM, Vex, EXx }, 0 },
10969   },
10970   {
10971     /* VEX_W_0F380B_P_2  */
10972     { "vpmulhrsw",      { XM, Vex, EXx }, 0 },
10973   },
10974   {
10975     /* VEX_W_0F380C_P_2  */
10976     { "vpermilps",      { XM, Vex, EXx }, 0 },
10977   },
10978   {
10979     /* VEX_W_0F380D_P_2  */
10980     { "vpermilpd",      { XM, Vex, EXx }, 0 },
10981   },
10982   {
10983     /* VEX_W_0F380E_P_2  */
10984     { "vtestps",        { XM, EXx }, 0 },
10985   },
10986   {
10987     /* VEX_W_0F380F_P_2  */
10988     { "vtestpd",        { XM, EXx }, 0 },
10989   },
10990   {
10991     /* VEX_W_0F3816_P_2  */
10992     { "vpermps",        { XM, Vex, EXx }, 0 },
10993   },
10994   {
10995     /* VEX_W_0F3817_P_2 */
10996     { "vptest",         { XM, EXx }, 0 },
10997   },
10998   {
10999     /* VEX_W_0F3818_P_2 */
11000     { "vbroadcastss",   { XM, EXxmm_md }, 0 },
11001   },
11002   {
11003     /* VEX_W_0F3819_P_2 */
11004     { "vbroadcastsd",   { XM, EXxmm_mq }, 0 },
11005   },
11006   {
11007     /* VEX_W_0F381A_P_2_M_0 */
11008     { "vbroadcastf128", { XM, Mxmm }, 0 },
11009   },
11010   {
11011     /* VEX_W_0F381C_P_2 */
11012     { "vpabsb",         { XM, EXx }, 0 },
11013   },
11014   {
11015     /* VEX_W_0F381D_P_2 */
11016     { "vpabsw",         { XM, EXx }, 0 },
11017   },
11018   {
11019     /* VEX_W_0F381E_P_2 */
11020     { "vpabsd",         { XM, EXx }, 0 },
11021   },
11022   {
11023     /* VEX_W_0F3820_P_2 */
11024     { "vpmovsxbw",      { XM, EXxmmq }, 0 },
11025   },
11026   {
11027     /* VEX_W_0F3821_P_2 */
11028     { "vpmovsxbd",      { XM, EXxmmqd }, 0 },
11029   },
11030   {
11031     /* VEX_W_0F3822_P_2 */
11032     { "vpmovsxbq",      { XM, EXxmmdw }, 0 },
11033   },
11034   {
11035     /* VEX_W_0F3823_P_2 */
11036     { "vpmovsxwd",      { XM, EXxmmq }, 0 },
11037   },
11038   {
11039     /* VEX_W_0F3824_P_2 */
11040     { "vpmovsxwq",      { XM, EXxmmqd }, 0 },
11041   },
11042   {
11043     /* VEX_W_0F3825_P_2 */
11044     { "vpmovsxdq",      { XM, EXxmmq }, 0 },
11045   },
11046   {
11047     /* VEX_W_0F3828_P_2 */
11048     { "vpmuldq",        { XM, Vex, EXx }, 0 },
11049   },
11050   {
11051     /* VEX_W_0F3829_P_2 */
11052     { "vpcmpeqq",       { XM, Vex, EXx }, 0 },
11053   },
11054   {
11055     /* VEX_W_0F382A_P_2_M_0 */
11056     { "vmovntdqa",      { XM, Mx }, 0 },
11057   },
11058   {
11059     /* VEX_W_0F382B_P_2 */
11060     { "vpackusdw",      { XM, Vex, EXx }, 0 },
11061   },
11062   {
11063     /* VEX_W_0F382C_P_2_M_0 */
11064     { "vmaskmovps",     { XM, Vex, Mx }, 0 },
11065   },
11066   {
11067     /* VEX_W_0F382D_P_2_M_0 */
11068     { "vmaskmovpd",     { XM, Vex, Mx }, 0 },
11069   },
11070   {
11071     /* VEX_W_0F382E_P_2_M_0 */
11072     { "vmaskmovps",     { Mx, Vex, XM }, 0 },
11073   },
11074   {
11075     /* VEX_W_0F382F_P_2_M_0 */
11076     { "vmaskmovpd",     { Mx, Vex, XM }, 0 },
11077   },
11078   {
11079     /* VEX_W_0F3830_P_2 */
11080     { "vpmovzxbw",      { XM, EXxmmq }, 0 },
11081   },
11082   {
11083     /* VEX_W_0F3831_P_2 */
11084     { "vpmovzxbd",      { XM, EXxmmqd }, 0 },
11085   },
11086   {
11087     /* VEX_W_0F3832_P_2 */
11088     { "vpmovzxbq",      { XM, EXxmmdw }, 0 },
11089   },
11090   {
11091     /* VEX_W_0F3833_P_2 */
11092     { "vpmovzxwd",      { XM, EXxmmq }, 0 },
11093   },
11094   {
11095     /* VEX_W_0F3834_P_2 */
11096     { "vpmovzxwq",      { XM, EXxmmqd }, 0 },
11097   },
11098   {
11099     /* VEX_W_0F3835_P_2 */
11100     { "vpmovzxdq",      { XM, EXxmmq }, 0 },
11101   },
11102   {
11103     /* VEX_W_0F3836_P_2  */
11104     { "vpermd",         { XM, Vex, EXx }, 0 },
11105   },
11106   {
11107     /* VEX_W_0F3837_P_2 */
11108     { "vpcmpgtq",       { XM, Vex, EXx }, 0 },
11109   },
11110   {
11111     /* VEX_W_0F3838_P_2 */
11112     { "vpminsb",        { XM, Vex, EXx }, 0 },
11113   },
11114   {
11115     /* VEX_W_0F3839_P_2 */
11116     { "vpminsd",        { XM, Vex, EXx }, 0 },
11117   },
11118   {
11119     /* VEX_W_0F383A_P_2 */
11120     { "vpminuw",        { XM, Vex, EXx }, 0 },
11121   },
11122   {
11123     /* VEX_W_0F383B_P_2 */
11124     { "vpminud",        { XM, Vex, EXx }, 0 },
11125   },
11126   {
11127     /* VEX_W_0F383C_P_2 */
11128     { "vpmaxsb",        { XM, Vex, EXx }, 0 },
11129   },
11130   {
11131     /* VEX_W_0F383D_P_2 */
11132     { "vpmaxsd",        { XM, Vex, EXx }, 0 },
11133   },
11134   {
11135     /* VEX_W_0F383E_P_2 */
11136     { "vpmaxuw",        { XM, Vex, EXx }, 0 },
11137   },
11138   {
11139     /* VEX_W_0F383F_P_2 */
11140     { "vpmaxud",        { XM, Vex, EXx }, 0 },
11141   },
11142   {
11143     /* VEX_W_0F3840_P_2 */
11144     { "vpmulld",        { XM, Vex, EXx }, 0 },
11145   },
11146   {
11147     /* VEX_W_0F3841_P_2 */
11148     { "vphminposuw",    { XM, EXx }, 0 },
11149   },
11150   {
11151     /* VEX_W_0F3846_P_2 */
11152     { "vpsravd",        { XM, Vex, EXx }, 0 },
11153   },
11154   {
11155     /* VEX_W_0F3858_P_2 */
11156     { "vpbroadcastd", { XM, EXxmm_md }, 0 },
11157   },
11158   {
11159     /* VEX_W_0F3859_P_2 */
11160     { "vpbroadcastq",   { XM, EXxmm_mq }, 0 },
11161   },
11162   {
11163     /* VEX_W_0F385A_P_2_M_0 */
11164     { "vbroadcasti128", { XM, Mxmm }, 0 },
11165   },
11166   {
11167     /* VEX_W_0F3878_P_2 */
11168     { "vpbroadcastb",   { XM, EXxmm_mb }, 0 },
11169   },
11170   {
11171     /* VEX_W_0F3879_P_2 */
11172     { "vpbroadcastw",   { XM, EXxmm_mw }, 0 },
11173   },
11174   {
11175     /* VEX_W_0F38DB_P_2 */
11176     { "vaesimc",        { XM, EXx }, 0 },
11177   },
11178   {
11179     /* VEX_W_0F38DC_P_2 */
11180     { "vaesenc",        { XM, Vex128, EXx }, 0 },
11181   },
11182   {
11183     /* VEX_W_0F38DD_P_2 */
11184     { "vaesenclast",    { XM, Vex128, EXx }, 0 },
11185   },
11186   {
11187     /* VEX_W_0F38DE_P_2 */
11188     { "vaesdec",        { XM, Vex128, EXx }, 0 },
11189   },
11190   {
11191     /* VEX_W_0F38DF_P_2 */
11192     { "vaesdeclast",    { XM, Vex128, EXx }, 0 },
11193   },
11194   {
11195     /* VEX_W_0F3A00_P_2 */
11196     { Bad_Opcode },
11197     { "vpermq",         { XM, EXx, Ib }, 0 },
11198   },
11199   {
11200     /* VEX_W_0F3A01_P_2 */
11201     { Bad_Opcode },
11202     { "vpermpd",        { XM, EXx, Ib }, 0 },
11203   },
11204   {
11205     /* VEX_W_0F3A02_P_2 */
11206     { "vpblendd",       { XM, Vex, EXx, Ib }, 0 },
11207   },
11208   {
11209     /* VEX_W_0F3A04_P_2 */
11210     { "vpermilps",      { XM, EXx, Ib }, 0 },
11211   },
11212   {
11213     /* VEX_W_0F3A05_P_2 */
11214     { "vpermilpd",      { XM, EXx, Ib }, 0 },
11215   },
11216   {
11217     /* VEX_W_0F3A06_P_2 */
11218     { "vperm2f128",     { XM, Vex256, EXx, Ib }, 0 },
11219   },
11220   {
11221     /* VEX_W_0F3A08_P_2 */
11222     { "vroundps",       { XM, EXx, Ib }, 0 },
11223   },
11224   {
11225     /* VEX_W_0F3A09_P_2 */
11226     { "vroundpd",       { XM, EXx, Ib }, 0 },
11227   },
11228   {
11229     /* VEX_W_0F3A0A_P_2 */
11230     { "vroundss",       { XMScalar, VexScalar, EXdScalar, Ib }, 0 },
11231   },
11232   {
11233     /* VEX_W_0F3A0B_P_2 */
11234     { "vroundsd",       { XMScalar, VexScalar, EXqScalar, Ib }, 0 },
11235   },
11236   {
11237     /* VEX_W_0F3A0C_P_2 */
11238     { "vblendps",       { XM, Vex, EXx, Ib }, 0 },
11239   },
11240   {
11241     /* VEX_W_0F3A0D_P_2 */
11242     { "vblendpd",       { XM, Vex, EXx, Ib }, 0 },
11243   },
11244   {
11245     /* VEX_W_0F3A0E_P_2 */
11246     { "vpblendw",       { XM, Vex, EXx, Ib }, 0 },
11247   },
11248   {
11249     /* VEX_W_0F3A0F_P_2 */
11250     { "vpalignr",       { XM, Vex, EXx, Ib }, 0 },
11251   },
11252   {
11253     /* VEX_W_0F3A14_P_2 */
11254     { "vpextrb",        { Edqb, XM, Ib }, 0 },
11255   },
11256   {
11257     /* VEX_W_0F3A15_P_2 */
11258     { "vpextrw",        { Edqw, XM, Ib }, 0 },
11259   },
11260   {
11261     /* VEX_W_0F3A18_P_2 */
11262     { "vinsertf128",    { XM, Vex256, EXxmm, Ib }, 0 },
11263   },
11264   {
11265     /* VEX_W_0F3A19_P_2 */
11266     { "vextractf128",   { EXxmm, XM, Ib }, 0 },
11267   },
11268   {
11269     /* VEX_W_0F3A20_P_2 */
11270     { "vpinsrb",        { XM, Vex128, Edqb, Ib }, 0 },
11271   },
11272   {
11273     /* VEX_W_0F3A21_P_2 */
11274     { "vinsertps",      { XM, Vex128, EXd, Ib }, 0 },
11275   },
11276   {
11277     /* VEX_W_0F3A30_P_2_LEN_0 */
11278     { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) },
11279     { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) },
11280   },
11281   {
11282     /* VEX_W_0F3A31_P_2_LEN_0 */
11283     { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) },
11284     { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) },
11285   },
11286   {
11287     /* VEX_W_0F3A32_P_2_LEN_0 */
11288     { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) },
11289     { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) },
11290   },
11291   {
11292     /* VEX_W_0F3A33_P_2_LEN_0 */
11293     { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) },
11294     { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) },
11295   },
11296   {
11297     /* VEX_W_0F3A38_P_2 */
11298     { "vinserti128",    { XM, Vex256, EXxmm, Ib }, 0 },
11299   },
11300   {
11301     /* VEX_W_0F3A39_P_2 */
11302     { "vextracti128",   { EXxmm, XM, Ib }, 0 },
11303   },
11304   {
11305     /* VEX_W_0F3A40_P_2 */
11306     { "vdpps",          { XM, Vex, EXx, Ib }, 0 },
11307   },
11308   {
11309     /* VEX_W_0F3A41_P_2 */
11310     { "vdppd",          { XM, Vex128, EXx, Ib }, 0 },
11311   },
11312   {
11313     /* VEX_W_0F3A42_P_2 */
11314     { "vmpsadbw",       { XM, Vex, EXx, Ib }, 0 },
11315   },
11316   {
11317     /* VEX_W_0F3A44_P_2 */
11318     { "vpclmulqdq",     { XM, Vex128, EXx, PCLMUL }, 0 },
11319   },
11320   {
11321     /* VEX_W_0F3A46_P_2 */
11322     { "vperm2i128",     { XM, Vex256, EXx, Ib }, 0 },
11323   },
11324   {
11325     /* VEX_W_0F3A48_P_2 */
11326     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11327     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11328   },
11329   {
11330     /* VEX_W_0F3A49_P_2 */
11331     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11332     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11333   },
11334   {
11335     /* VEX_W_0F3A4A_P_2 */
11336     { "vblendvps",      { XM, Vex, EXx, XMVexI4 }, 0 },
11337   },
11338   {
11339     /* VEX_W_0F3A4B_P_2 */
11340     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 }, 0 },
11341   },
11342   {
11343     /* VEX_W_0F3A4C_P_2 */
11344     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 }, 0 },
11345   },
11346   {
11347     /* VEX_W_0F3A60_P_2 */
11348     { "vpcmpestrm",     { XM, EXx, Ib }, 0 },
11349   },
11350   {
11351     /* VEX_W_0F3A61_P_2 */
11352     { "vpcmpestri",     { XM, EXx, Ib }, 0 },
11353   },
11354   {
11355     /* VEX_W_0F3A62_P_2 */
11356     { "vpcmpistrm",     { XM, EXx, Ib }, 0 },
11357   },
11358   {
11359     /* VEX_W_0F3A63_P_2 */
11360     { "vpcmpistri",     { XM, EXx, Ib }, 0 },
11361   },
11362   {
11363     /* VEX_W_0F3ADF_P_2 */
11364     { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
11365   },
11366 #define NEED_VEX_W_TABLE
11367 #include "i386-dis-evex.h"
11368 #undef NEED_VEX_W_TABLE
11369 };
11370
11371 static const struct dis386 mod_table[][2] = {
11372   {
11373     /* MOD_8D */
11374     { "leaS",           { Gv, M }, 0 },
11375   },
11376   {
11377     /* MOD_C6_REG_7 */
11378     { Bad_Opcode },
11379     { RM_TABLE (RM_C6_REG_7) },
11380   },
11381   {
11382     /* MOD_C7_REG_7 */
11383     { Bad_Opcode },
11384     { RM_TABLE (RM_C7_REG_7) },
11385   },
11386   {
11387     /* MOD_FF_REG_3 */
11388     { "Jcall^", { indirEp }, 0 },
11389   },
11390   {
11391     /* MOD_FF_REG_5 */
11392     { "Jjmp^", { indirEp }, 0 },
11393   },
11394   {
11395     /* MOD_0F01_REG_0 */
11396     { X86_64_TABLE (X86_64_0F01_REG_0) },
11397     { RM_TABLE (RM_0F01_REG_0) },
11398   },
11399   {
11400     /* MOD_0F01_REG_1 */
11401     { X86_64_TABLE (X86_64_0F01_REG_1) },
11402     { RM_TABLE (RM_0F01_REG_1) },
11403   },
11404   {
11405     /* MOD_0F01_REG_2 */
11406     { X86_64_TABLE (X86_64_0F01_REG_2) },
11407     { RM_TABLE (RM_0F01_REG_2) },
11408   },
11409   {
11410     /* MOD_0F01_REG_3 */
11411     { X86_64_TABLE (X86_64_0F01_REG_3) },
11412     { RM_TABLE (RM_0F01_REG_3) },
11413   },
11414   {
11415     /* MOD_0F01_REG_5 */
11416     { Bad_Opcode },
11417     { RM_TABLE (RM_0F01_REG_5) },
11418   },
11419   {
11420     /* MOD_0F01_REG_7 */
11421     { "invlpg",         { Mb }, 0 },
11422     { RM_TABLE (RM_0F01_REG_7) },
11423   },
11424   {
11425     /* MOD_0F12_PREFIX_0 */
11426     { "movlps",         { XM, EXq }, PREFIX_OPCODE },
11427     { "movhlps",        { XM, EXq }, PREFIX_OPCODE },
11428   },
11429   {
11430     /* MOD_0F13 */
11431     { "movlpX",         { EXq, XM }, PREFIX_OPCODE },
11432   },
11433   {
11434     /* MOD_0F16_PREFIX_0 */
11435     { "movhps",         { XM, EXq }, 0 },
11436     { "movlhps",        { XM, EXq }, 0 },
11437   },
11438   {
11439     /* MOD_0F17 */
11440     { "movhpX",         { EXq, XM }, PREFIX_OPCODE },
11441   },
11442   {
11443     /* MOD_0F18_REG_0 */
11444     { "prefetchnta",    { Mb }, 0 },
11445   },
11446   {
11447     /* MOD_0F18_REG_1 */
11448     { "prefetcht0",     { Mb }, 0 },
11449   },
11450   {
11451     /* MOD_0F18_REG_2 */
11452     { "prefetcht1",     { Mb }, 0 },
11453   },
11454   {
11455     /* MOD_0F18_REG_3 */
11456     { "prefetcht2",     { Mb }, 0 },
11457   },
11458   {
11459     /* MOD_0F18_REG_4 */
11460     { "nop/reserved",   { Mb }, 0 },
11461   },
11462   {
11463     /* MOD_0F18_REG_5 */
11464     { "nop/reserved",   { Mb }, 0 },
11465   },
11466   {
11467     /* MOD_0F18_REG_6 */
11468     { "nop/reserved",   { Mb }, 0 },
11469   },
11470   {
11471     /* MOD_0F18_REG_7 */
11472     { "nop/reserved",   { Mb }, 0 },
11473   },
11474   {
11475     /* MOD_0F1A_PREFIX_0 */
11476     { "bndldx",         { Gbnd, Ev_bnd }, 0 },
11477     { "nopQ",           { Ev }, 0 },
11478   },
11479   {
11480     /* MOD_0F1B_PREFIX_0 */
11481     { "bndstx",         { Ev_bnd, Gbnd }, 0 },
11482     { "nopQ",           { Ev }, 0 },
11483   },
11484   {
11485     /* MOD_0F1B_PREFIX_1 */
11486     { "bndmk",          { Gbnd, Ev_bnd }, 0 },
11487     { "nopQ",           { Ev }, 0 },
11488   },
11489   {
11490     /* MOD_0F24 */
11491     { Bad_Opcode },
11492     { "movL",           { Rd, Td }, 0 },
11493   },
11494   {
11495     /* MOD_0F26 */
11496     { Bad_Opcode },
11497     { "movL",           { Td, Rd }, 0 },
11498   },
11499   {
11500     /* MOD_0F2B_PREFIX_0 */
11501     {"movntps",         { Mx, XM }, PREFIX_OPCODE },
11502   },
11503   {
11504     /* MOD_0F2B_PREFIX_1 */
11505     {"movntss",         { Md, XM }, PREFIX_OPCODE },
11506   },
11507   {
11508     /* MOD_0F2B_PREFIX_2 */
11509     {"movntpd",         { Mx, XM }, PREFIX_OPCODE },
11510   },
11511   {
11512     /* MOD_0F2B_PREFIX_3 */
11513     {"movntsd",         { Mq, XM }, PREFIX_OPCODE },
11514   },
11515   {
11516     /* MOD_0F51 */
11517     { Bad_Opcode },
11518     { "movmskpX",       { Gdq, XS }, PREFIX_OPCODE },
11519   },
11520   {
11521     /* MOD_0F71_REG_2 */
11522     { Bad_Opcode },
11523     { "psrlw",          { MS, Ib }, 0 },
11524   },
11525   {
11526     /* MOD_0F71_REG_4 */
11527     { Bad_Opcode },
11528     { "psraw",          { MS, Ib }, 0 },
11529   },
11530   {
11531     /* MOD_0F71_REG_6 */
11532     { Bad_Opcode },
11533     { "psllw",          { MS, Ib }, 0 },
11534   },
11535   {
11536     /* MOD_0F72_REG_2 */
11537     { Bad_Opcode },
11538     { "psrld",          { MS, Ib }, 0 },
11539   },
11540   {
11541     /* MOD_0F72_REG_4 */
11542     { Bad_Opcode },
11543     { "psrad",          { MS, Ib }, 0 },
11544   },
11545   {
11546     /* MOD_0F72_REG_6 */
11547     { Bad_Opcode },
11548     { "pslld",          { MS, Ib }, 0 },
11549   },
11550   {
11551     /* MOD_0F73_REG_2 */
11552     { Bad_Opcode },
11553     { "psrlq",          { MS, Ib }, 0 },
11554   },
11555   {
11556     /* MOD_0F73_REG_3 */
11557     { Bad_Opcode },
11558     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
11559   },
11560   {
11561     /* MOD_0F73_REG_6 */
11562     { Bad_Opcode },
11563     { "psllq",          { MS, Ib }, 0 },
11564   },
11565   {
11566     /* MOD_0F73_REG_7 */
11567     { Bad_Opcode },
11568     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
11569   },
11570   {
11571     /* MOD_0FAE_REG_0 */
11572     { "fxsave",         { FXSAVE }, 0 },
11573     { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
11574   },
11575   {
11576     /* MOD_0FAE_REG_1 */
11577     { "fxrstor",        { FXSAVE }, 0 },
11578     { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
11579   },
11580   {
11581     /* MOD_0FAE_REG_2 */
11582     { "ldmxcsr",        { Md }, 0 },
11583     { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
11584   },
11585   {
11586     /* MOD_0FAE_REG_3 */
11587     { "stmxcsr",        { Md }, 0 },
11588     { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
11589   },
11590   {
11591     /* MOD_0FAE_REG_4 */
11592     { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_4) },
11593     { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_4) },
11594   },
11595   {
11596     /* MOD_0FAE_REG_5 */
11597     { "xrstor",         { FXSAVE }, 0 },
11598     { RM_TABLE (RM_0FAE_REG_5) },
11599   },
11600   {
11601     /* MOD_0FAE_REG_6 */
11602     { PREFIX_TABLE (PREFIX_0FAE_REG_6) },
11603     { RM_TABLE (RM_0FAE_REG_6) },
11604   },
11605   {
11606     /* MOD_0FAE_REG_7 */
11607     { PREFIX_TABLE (PREFIX_0FAE_REG_7) },
11608     { RM_TABLE (RM_0FAE_REG_7) },
11609   },
11610   {
11611     /* MOD_0FB2 */
11612     { "lssS",           { Gv, Mp }, 0 },
11613   },
11614   {
11615     /* MOD_0FB4 */
11616     { "lfsS",           { Gv, Mp }, 0 },
11617   },
11618   {
11619     /* MOD_0FB5 */
11620     { "lgsS",           { Gv, Mp }, 0 },
11621   },
11622   {
11623     /* MOD_0FC3 */
11624     { PREFIX_TABLE (PREFIX_MOD_0_0FC3) },
11625   },
11626   {
11627     /* MOD_0FC7_REG_3 */
11628     { "xrstors",        { FXSAVE }, 0 },
11629   },
11630   {
11631     /* MOD_0FC7_REG_4 */
11632     { "xsavec",         { FXSAVE }, 0 },
11633   },
11634   {
11635     /* MOD_0FC7_REG_5 */
11636     { "xsaves",         { FXSAVE }, 0 },
11637   },
11638   {
11639     /* MOD_0FC7_REG_6 */
11640     { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6) },
11641     { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6) }
11642   },
11643   {
11644     /* MOD_0FC7_REG_7 */
11645     { "vmptrst",        { Mq }, 0 },
11646     { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7) }
11647   },
11648   {
11649     /* MOD_0FD7 */
11650     { Bad_Opcode },
11651     { "pmovmskb",       { Gdq, MS }, 0 },
11652   },
11653   {
11654     /* MOD_0FE7_PREFIX_2 */
11655     { "movntdq",        { Mx, XM }, 0 },
11656   },
11657   {
11658     /* MOD_0FF0_PREFIX_3 */
11659     { "lddqu",          { XM, M }, 0 },
11660   },
11661   {
11662     /* MOD_0F382A_PREFIX_2 */
11663     { "movntdqa",       { XM, Mx }, 0 },
11664   },
11665   {
11666     /* MOD_62_32BIT */
11667     { "bound{S|}",      { Gv, Ma }, 0 },
11668     { EVEX_TABLE (EVEX_0F) },
11669   },
11670   {
11671     /* MOD_C4_32BIT */
11672     { "lesS",           { Gv, Mp }, 0 },
11673     { VEX_C4_TABLE (VEX_0F) },
11674   },
11675   {
11676     /* MOD_C5_32BIT */
11677     { "ldsS",           { Gv, Mp }, 0 },
11678     { VEX_C5_TABLE (VEX_0F) },
11679   },
11680   {
11681     /* MOD_VEX_0F12_PREFIX_0 */
11682     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
11683     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
11684   },
11685   {
11686     /* MOD_VEX_0F13 */
11687     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
11688   },
11689   {
11690     /* MOD_VEX_0F16_PREFIX_0 */
11691     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
11692     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
11693   },
11694   {
11695     /* MOD_VEX_0F17 */
11696     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
11697   },
11698   {
11699     /* MOD_VEX_0F2B */
11700     { VEX_W_TABLE (VEX_W_0F2B_M_0) },
11701   },
11702   {
11703     /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
11704     { Bad_Opcode },
11705     { "kandw",          { MaskG, MaskVex, MaskR }, 0 },
11706   },
11707   {
11708     /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
11709     { Bad_Opcode },
11710     { "kandq",          { MaskG, MaskVex, MaskR }, 0 },
11711   },
11712   {
11713     /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
11714     { Bad_Opcode },
11715     { "kandb",          { MaskG, MaskVex, MaskR }, 0 },
11716   },
11717   {
11718     /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
11719     { Bad_Opcode },
11720     { "kandd",          { MaskG, MaskVex, MaskR }, 0 },
11721   },
11722   {
11723     /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
11724     { Bad_Opcode },
11725     { "kandnw",         { MaskG, MaskVex, MaskR }, 0 },
11726   },
11727   {
11728     /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
11729     { Bad_Opcode },
11730     { "kandnq",         { MaskG, MaskVex, MaskR }, 0 },
11731   },
11732   {
11733     /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
11734     { Bad_Opcode },
11735     { "kandnb",         { MaskG, MaskVex, MaskR }, 0 },
11736   },
11737   {
11738     /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
11739     { Bad_Opcode },
11740     { "kandnd",         { MaskG, MaskVex, MaskR }, 0 },
11741   },
11742   {
11743     /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
11744     { Bad_Opcode },
11745     { "knotw",          { MaskG, MaskR }, 0 },
11746   },
11747   {
11748     /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
11749     { Bad_Opcode },
11750     { "knotq",          { MaskG, MaskR }, 0 },
11751   },
11752   {
11753     /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
11754     { Bad_Opcode },
11755     { "knotb",          { MaskG, MaskR }, 0 },
11756   },
11757   {
11758     /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
11759     { Bad_Opcode },
11760     { "knotd",          { MaskG, MaskR }, 0 },
11761   },
11762   {
11763     /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
11764     { Bad_Opcode },
11765     { "korw",       { MaskG, MaskVex, MaskR }, 0 },
11766   },
11767   {
11768     /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
11769     { Bad_Opcode },
11770     { "korq",       { MaskG, MaskVex, MaskR }, 0 },
11771   },
11772   {
11773     /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
11774     { Bad_Opcode },
11775     { "korb",       { MaskG, MaskVex, MaskR }, 0 },
11776   },
11777   {
11778     /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
11779     { Bad_Opcode },
11780     { "kord",       { MaskG, MaskVex, MaskR }, 0 },
11781   },
11782  {
11783     /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
11784     { Bad_Opcode },
11785     { "kxnorw",     { MaskG, MaskVex, MaskR }, 0 },
11786   },
11787   {
11788     /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
11789     { Bad_Opcode },
11790     { "kxnorq",     { MaskG, MaskVex, MaskR }, 0 },
11791   },
11792   {
11793     /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
11794     { Bad_Opcode },
11795     { "kxnorb",     { MaskG, MaskVex, MaskR }, 0 },
11796   },
11797   {
11798     /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
11799     { Bad_Opcode },
11800     { "kxnord",     { MaskG, MaskVex, MaskR }, 0 },
11801   },
11802   {
11803     /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
11804     { Bad_Opcode },
11805     { "kxorw",      { MaskG, MaskVex, MaskR }, 0 },
11806   },
11807   {
11808     /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
11809     { Bad_Opcode },
11810     { "kxorq",      { MaskG, MaskVex, MaskR }, 0 },
11811   },
11812   {
11813     /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
11814     { Bad_Opcode },
11815     { "kxorb",      { MaskG, MaskVex, MaskR }, 0 },
11816   },
11817   {
11818     /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
11819     { Bad_Opcode },
11820     { "kxord",      { MaskG, MaskVex, MaskR }, 0 },
11821   },
11822   {
11823     /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
11824     { Bad_Opcode },
11825     { "kaddw",          { MaskG, MaskVex, MaskR }, 0 },
11826   },
11827   {
11828     /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
11829     { Bad_Opcode },
11830     { "kaddq",          { MaskG, MaskVex, MaskR }, 0 },
11831   },
11832   {
11833     /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
11834     { Bad_Opcode },
11835     { "kaddb",          { MaskG, MaskVex, MaskR }, 0 },
11836   },
11837   {
11838     /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
11839     { Bad_Opcode },
11840     { "kaddd",          { MaskG, MaskVex, MaskR }, 0 },
11841   },
11842   {
11843     /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
11844     { Bad_Opcode },
11845     { "kunpckwd",   { MaskG, MaskVex, MaskR }, 0 },
11846   },
11847   {
11848     /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
11849     { Bad_Opcode },
11850     { "kunpckdq",   { MaskG, MaskVex, MaskR }, 0 },
11851   },
11852   {
11853     /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
11854     { Bad_Opcode },
11855     { "kunpckbw",   { MaskG, MaskVex, MaskR }, 0 },
11856   },
11857   {
11858     /* MOD_VEX_0F50 */
11859     { Bad_Opcode },
11860     { VEX_W_TABLE (VEX_W_0F50_M_0) },
11861   },
11862   {
11863     /* MOD_VEX_0F71_REG_2 */
11864     { Bad_Opcode },
11865     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
11866   },
11867   {
11868     /* MOD_VEX_0F71_REG_4 */
11869     { Bad_Opcode },
11870     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
11871   },
11872   {
11873     /* MOD_VEX_0F71_REG_6 */
11874     { Bad_Opcode },
11875     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
11876   },
11877   {
11878     /* MOD_VEX_0F72_REG_2 */
11879     { Bad_Opcode },
11880     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
11881   },
11882   {
11883     /* MOD_VEX_0F72_REG_4 */
11884     { Bad_Opcode },
11885     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
11886   },
11887   {
11888     /* MOD_VEX_0F72_REG_6 */
11889     { Bad_Opcode },
11890     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
11891   },
11892   {
11893     /* MOD_VEX_0F73_REG_2 */
11894     { Bad_Opcode },
11895     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
11896   },
11897   {
11898     /* MOD_VEX_0F73_REG_3 */
11899     { Bad_Opcode },
11900     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
11901   },
11902   {
11903     /* MOD_VEX_0F73_REG_6 */
11904     { Bad_Opcode },
11905     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
11906   },
11907   {
11908     /* MOD_VEX_0F73_REG_7 */
11909     { Bad_Opcode },
11910     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
11911   },
11912   {
11913     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
11914     { "kmovw",          { Ew, MaskG }, 0 },
11915     { Bad_Opcode },
11916   },
11917   {
11918     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
11919     { "kmovq",          { Eq, MaskG }, 0 },
11920     { Bad_Opcode },
11921   },
11922   {
11923     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
11924     { "kmovb",          { Eb, MaskG }, 0 },
11925     { Bad_Opcode },
11926   },
11927   {
11928     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
11929     { "kmovd",          { Ed, MaskG }, 0 },
11930     { Bad_Opcode },
11931   },
11932   {
11933     /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
11934     { Bad_Opcode },
11935     { "kmovw",          { MaskG, Rdq }, 0 },
11936   },
11937   {
11938     /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
11939     { Bad_Opcode },
11940     { "kmovb",          { MaskG, Rdq }, 0 },
11941   },
11942   {
11943     /* MOD_VEX_W_0_0F92_P_3_LEN_0 */
11944     { Bad_Opcode },
11945     { "kmovd",          { MaskG, Rdq }, 0 },
11946   },
11947   {
11948     /* MOD_VEX_W_1_0F92_P_3_LEN_0 */
11949     { Bad_Opcode },
11950     { "kmovq",          { MaskG, Rdq }, 0 },
11951   },
11952   {
11953     /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
11954     { Bad_Opcode },
11955     { "kmovw",          { Gdq, MaskR }, 0 },
11956   },
11957   {
11958     /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
11959     { Bad_Opcode },
11960     { "kmovb",          { Gdq, MaskR }, 0 },
11961   },
11962   {
11963     /* MOD_VEX_W_0_0F93_P_3_LEN_0 */
11964     { Bad_Opcode },
11965     { "kmovd",          { Gdq, MaskR }, 0 },
11966   },
11967   {
11968     /* MOD_VEX_W_1_0F93_P_3_LEN_0 */
11969     { Bad_Opcode },
11970     { "kmovq",          { Gdq, MaskR }, 0 },
11971   },
11972   {
11973     /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
11974     { Bad_Opcode },
11975     { "kortestw", { MaskG, MaskR }, 0 },
11976   },
11977   {
11978     /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
11979     { Bad_Opcode },
11980     { "kortestq", { MaskG, MaskR }, 0 },
11981   },
11982   {
11983     /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
11984     { Bad_Opcode },
11985     { "kortestb", { MaskG, MaskR }, 0 },
11986   },
11987   {
11988     /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
11989     { Bad_Opcode },
11990     { "kortestd", { MaskG, MaskR }, 0 },
11991   },
11992   {
11993     /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
11994     { Bad_Opcode },
11995     { "ktestw", { MaskG, MaskR }, 0 },
11996   },
11997   {
11998     /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
11999     { Bad_Opcode },
12000     { "ktestq", { MaskG, MaskR }, 0 },
12001   },
12002   {
12003     /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
12004     { Bad_Opcode },
12005     { "ktestb", { MaskG, MaskR }, 0 },
12006   },
12007   {
12008     /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
12009     { Bad_Opcode },
12010     { "ktestd", { MaskG, MaskR }, 0 },
12011   },
12012   {
12013     /* MOD_VEX_0FAE_REG_2 */
12014     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
12015   },
12016   {
12017     /* MOD_VEX_0FAE_REG_3 */
12018     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
12019   },
12020   {
12021     /* MOD_VEX_0FD7_PREFIX_2 */
12022     { Bad_Opcode },
12023     { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) },
12024   },
12025   {
12026     /* MOD_VEX_0FE7_PREFIX_2 */
12027     { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) },
12028   },
12029   {
12030     /* MOD_VEX_0FF0_PREFIX_3 */
12031     { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) },
12032   },
12033   {
12034     /* MOD_VEX_0F381A_PREFIX_2 */
12035     { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
12036   },
12037   {
12038     /* MOD_VEX_0F382A_PREFIX_2 */
12039     { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) },
12040   },
12041   {
12042     /* MOD_VEX_0F382C_PREFIX_2 */
12043     { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
12044   },
12045   {
12046     /* MOD_VEX_0F382D_PREFIX_2 */
12047     { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
12048   },
12049   {
12050     /* MOD_VEX_0F382E_PREFIX_2 */
12051     { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
12052   },
12053   {
12054     /* MOD_VEX_0F382F_PREFIX_2 */
12055     { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
12056   },
12057   {
12058     /* MOD_VEX_0F385A_PREFIX_2 */
12059     { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
12060   },
12061   {
12062     /* MOD_VEX_0F388C_PREFIX_2 */
12063     { "vpmaskmov%LW",   { XM, Vex, Mx }, 0 },
12064   },
12065   {
12066     /* MOD_VEX_0F388E_PREFIX_2 */
12067     { "vpmaskmov%LW",   { Mx, Vex, XM }, 0 },
12068   },
12069   {
12070     /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
12071     { Bad_Opcode },
12072     { "kshiftrb",       { MaskG, MaskR, Ib }, 0 },
12073   },
12074   {
12075     /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
12076     { Bad_Opcode },
12077     { "kshiftrw",       { MaskG, MaskR, Ib }, 0 },
12078   },
12079   {
12080     /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
12081     { Bad_Opcode },
12082     { "kshiftrd",       { MaskG, MaskR, Ib }, 0 },
12083   },
12084   {
12085     /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
12086     { Bad_Opcode },
12087     { "kshiftrq",       { MaskG, MaskR, Ib }, 0 },
12088   },
12089   {
12090     /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
12091     { Bad_Opcode },
12092     { "kshiftlb",       { MaskG, MaskR, Ib }, 0 },
12093   },
12094   {
12095     /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
12096     { Bad_Opcode },
12097     { "kshiftlw",       { MaskG, MaskR, Ib }, 0 },
12098   },
12099   {
12100     /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
12101     { Bad_Opcode },
12102     { "kshiftld",       { MaskG, MaskR, Ib }, 0 },
12103   },
12104   {
12105     /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
12106     { Bad_Opcode },
12107     { "kshiftlq",       { MaskG, MaskR, Ib }, 0 },
12108   },
12109 #define NEED_MOD_TABLE
12110 #include "i386-dis-evex.h"
12111 #undef NEED_MOD_TABLE
12112 };
12113
12114 static const struct dis386 rm_table[][8] = {
12115   {
12116     /* RM_C6_REG_7 */
12117     { "xabort",         { Skip_MODRM, Ib }, 0 },
12118   },
12119   {
12120     /* RM_C7_REG_7 */
12121     { "xbeginT",        { Skip_MODRM, Jv }, 0 },
12122   },
12123   {
12124     /* RM_0F01_REG_0 */
12125     { Bad_Opcode },
12126     { "vmcall",         { Skip_MODRM }, 0 },
12127     { "vmlaunch",       { Skip_MODRM }, 0 },
12128     { "vmresume",       { Skip_MODRM }, 0 },
12129     { "vmxoff",         { Skip_MODRM }, 0 },
12130   },
12131   {
12132     /* RM_0F01_REG_1 */
12133     { "monitor",        { { OP_Monitor, 0 } }, 0 },
12134     { "mwait",          { { OP_Mwait, 0 } }, 0 },
12135     { "clac",           { Skip_MODRM }, 0 },
12136     { "stac",           { Skip_MODRM }, 0 },
12137     { Bad_Opcode },
12138     { Bad_Opcode },
12139     { Bad_Opcode },
12140     { "encls",          { Skip_MODRM }, 0 },
12141   },
12142   {
12143     /* RM_0F01_REG_2 */
12144     { "xgetbv",         { Skip_MODRM }, 0 },
12145     { "xsetbv",         { Skip_MODRM }, 0 },
12146     { Bad_Opcode },
12147     { Bad_Opcode },
12148     { "vmfunc",         { Skip_MODRM }, 0 },
12149     { "xend",           { Skip_MODRM }, 0 },
12150     { "xtest",          { Skip_MODRM }, 0 },
12151     { "enclu",          { Skip_MODRM }, 0 },
12152   },
12153   {
12154     /* RM_0F01_REG_3 */
12155     { "vmrun",          { Skip_MODRM }, 0 },
12156     { "vmmcall",        { Skip_MODRM }, 0 },
12157     { "vmload",         { Skip_MODRM }, 0 },
12158     { "vmsave",         { Skip_MODRM }, 0 },
12159     { "stgi",           { Skip_MODRM }, 0 },
12160     { "clgi",           { Skip_MODRM }, 0 },
12161     { "skinit",         { Skip_MODRM }, 0 },
12162     { "invlpga",        { Skip_MODRM }, 0 },
12163   },
12164   {
12165     /* RM_0F01_REG_5 */
12166     { Bad_Opcode },
12167     { Bad_Opcode },
12168     { Bad_Opcode },
12169     { Bad_Opcode },
12170     { Bad_Opcode },
12171     { Bad_Opcode },
12172     { "rdpkru",         { Skip_MODRM }, 0 },
12173     { "wrpkru",         { Skip_MODRM }, 0 },
12174   },
12175   {
12176     /* RM_0F01_REG_7 */
12177     { "swapgs",         { Skip_MODRM }, 0  },
12178     { "rdtscp",         { Skip_MODRM }, 0  },
12179     { "monitorx",       { { OP_Monitor, 0 } }, 0  },
12180     { "mwaitx",         { { OP_Mwaitx,  0 } }, 0  },
12181     { "clzero",         { Skip_MODRM }, 0  },
12182   },
12183   {
12184     /* RM_0FAE_REG_5 */
12185     { "lfence",         { Skip_MODRM }, 0 },
12186   },
12187   {
12188     /* RM_0FAE_REG_6 */
12189     { "mfence",         { Skip_MODRM }, 0 },
12190   },
12191   {
12192     /* RM_0FAE_REG_7 */
12193     { "sfence",         { Skip_MODRM }, 0 },
12194
12195   },
12196 };
12197
12198 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
12199
12200 /* We use the high bit to indicate different name for the same
12201    prefix.  */
12202 #define REP_PREFIX      (0xf3 | 0x100)
12203 #define XACQUIRE_PREFIX (0xf2 | 0x200)
12204 #define XRELEASE_PREFIX (0xf3 | 0x400)
12205 #define BND_PREFIX      (0xf2 | 0x400)
12206
12207 static int
12208 ckprefix (void)
12209 {
12210   int newrex, i, length;
12211   rex = 0;
12212   rex_ignored = 0;
12213   prefixes = 0;
12214   used_prefixes = 0;
12215   rex_used = 0;
12216   last_lock_prefix = -1;
12217   last_repz_prefix = -1;
12218   last_repnz_prefix = -1;
12219   last_data_prefix = -1;
12220   last_addr_prefix = -1;
12221   last_rex_prefix = -1;
12222   last_seg_prefix = -1;
12223   fwait_prefix = -1;
12224   active_seg_prefix = 0;
12225   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12226     all_prefixes[i] = 0;
12227   i = 0;
12228   length = 0;
12229   /* The maximum instruction length is 15bytes.  */
12230   while (length < MAX_CODE_LENGTH - 1)
12231     {
12232       FETCH_DATA (the_info, codep + 1);
12233       newrex = 0;
12234       switch (*codep)
12235         {
12236         /* REX prefixes family.  */
12237         case 0x40:
12238         case 0x41:
12239         case 0x42:
12240         case 0x43:
12241         case 0x44:
12242         case 0x45:
12243         case 0x46:
12244         case 0x47:
12245         case 0x48:
12246         case 0x49:
12247         case 0x4a:
12248         case 0x4b:
12249         case 0x4c:
12250         case 0x4d:
12251         case 0x4e:
12252         case 0x4f:
12253           if (address_mode == mode_64bit)
12254             newrex = *codep;
12255           else
12256             return 1;
12257           last_rex_prefix = i;
12258           break;
12259         case 0xf3:
12260           prefixes |= PREFIX_REPZ;
12261           last_repz_prefix = i;
12262           break;
12263         case 0xf2:
12264           prefixes |= PREFIX_REPNZ;
12265           last_repnz_prefix = i;
12266           break;
12267         case 0xf0:
12268           prefixes |= PREFIX_LOCK;
12269           last_lock_prefix = i;
12270           break;
12271         case 0x2e:
12272           prefixes |= PREFIX_CS;
12273           last_seg_prefix = i;
12274           active_seg_prefix = PREFIX_CS;
12275           break;
12276         case 0x36:
12277           prefixes |= PREFIX_SS;
12278           last_seg_prefix = i;
12279           active_seg_prefix = PREFIX_SS;
12280           break;
12281         case 0x3e:
12282           prefixes |= PREFIX_DS;
12283           last_seg_prefix = i;
12284           active_seg_prefix = PREFIX_DS;
12285           break;
12286         case 0x26:
12287           prefixes |= PREFIX_ES;
12288           last_seg_prefix = i;
12289           active_seg_prefix = PREFIX_ES;
12290           break;
12291         case 0x64:
12292           prefixes |= PREFIX_FS;
12293           last_seg_prefix = i;
12294           active_seg_prefix = PREFIX_FS;
12295           break;
12296         case 0x65:
12297           prefixes |= PREFIX_GS;
12298           last_seg_prefix = i;
12299           active_seg_prefix = PREFIX_GS;
12300           break;
12301         case 0x66:
12302           prefixes |= PREFIX_DATA;
12303           last_data_prefix = i;
12304           break;
12305         case 0x67:
12306           prefixes |= PREFIX_ADDR;
12307           last_addr_prefix = i;
12308           break;
12309         case FWAIT_OPCODE:
12310           /* fwait is really an instruction.  If there are prefixes
12311              before the fwait, they belong to the fwait, *not* to the
12312              following instruction.  */
12313           fwait_prefix = i;
12314           if (prefixes || rex)
12315             {
12316               prefixes |= PREFIX_FWAIT;
12317               codep++;
12318               /* This ensures that the previous REX prefixes are noticed
12319                  as unused prefixes, as in the return case below.  */
12320               rex_used = rex;
12321               return 1;
12322             }
12323           prefixes = PREFIX_FWAIT;
12324           break;
12325         default:
12326           return 1;
12327         }
12328       /* Rex is ignored when followed by another prefix.  */
12329       if (rex)
12330         {
12331           rex_used = rex;
12332           return 1;
12333         }
12334       if (*codep != FWAIT_OPCODE)
12335         all_prefixes[i++] = *codep;
12336       rex = newrex;
12337       codep++;
12338       length++;
12339     }
12340   return 0;
12341 }
12342
12343 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
12344    prefix byte.  */
12345
12346 static const char *
12347 prefix_name (int pref, int sizeflag)
12348 {
12349   static const char *rexes [16] =
12350     {
12351       "rex",            /* 0x40 */
12352       "rex.B",          /* 0x41 */
12353       "rex.X",          /* 0x42 */
12354       "rex.XB",         /* 0x43 */
12355       "rex.R",          /* 0x44 */
12356       "rex.RB",         /* 0x45 */
12357       "rex.RX",         /* 0x46 */
12358       "rex.RXB",        /* 0x47 */
12359       "rex.W",          /* 0x48 */
12360       "rex.WB",         /* 0x49 */
12361       "rex.WX",         /* 0x4a */
12362       "rex.WXB",        /* 0x4b */
12363       "rex.WR",         /* 0x4c */
12364       "rex.WRB",        /* 0x4d */
12365       "rex.WRX",        /* 0x4e */
12366       "rex.WRXB",       /* 0x4f */
12367     };
12368
12369   switch (pref)
12370     {
12371     /* REX prefixes family.  */
12372     case 0x40:
12373     case 0x41:
12374     case 0x42:
12375     case 0x43:
12376     case 0x44:
12377     case 0x45:
12378     case 0x46:
12379     case 0x47:
12380     case 0x48:
12381     case 0x49:
12382     case 0x4a:
12383     case 0x4b:
12384     case 0x4c:
12385     case 0x4d:
12386     case 0x4e:
12387     case 0x4f:
12388       return rexes [pref - 0x40];
12389     case 0xf3:
12390       return "repz";
12391     case 0xf2:
12392       return "repnz";
12393     case 0xf0:
12394       return "lock";
12395     case 0x2e:
12396       return "cs";
12397     case 0x36:
12398       return "ss";
12399     case 0x3e:
12400       return "ds";
12401     case 0x26:
12402       return "es";
12403     case 0x64:
12404       return "fs";
12405     case 0x65:
12406       return "gs";
12407     case 0x66:
12408       return (sizeflag & DFLAG) ? "data16" : "data32";
12409     case 0x67:
12410       if (address_mode == mode_64bit)
12411         return (sizeflag & AFLAG) ? "addr32" : "addr64";
12412       else
12413         return (sizeflag & AFLAG) ? "addr16" : "addr32";
12414     case FWAIT_OPCODE:
12415       return "fwait";
12416     case REP_PREFIX:
12417       return "rep";
12418     case XACQUIRE_PREFIX:
12419       return "xacquire";
12420     case XRELEASE_PREFIX:
12421       return "xrelease";
12422     case BND_PREFIX:
12423       return "bnd";
12424     default:
12425       return NULL;
12426     }
12427 }
12428
12429 static char op_out[MAX_OPERANDS][100];
12430 static int op_ad, op_index[MAX_OPERANDS];
12431 static int two_source_ops;
12432 static bfd_vma op_address[MAX_OPERANDS];
12433 static bfd_vma op_riprel[MAX_OPERANDS];
12434 static bfd_vma start_pc;
12435
12436 /*
12437  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
12438  *   (see topic "Redundant prefixes" in the "Differences from 8086"
12439  *   section of the "Virtual 8086 Mode" chapter.)
12440  * 'pc' should be the address of this instruction, it will
12441  *   be used to print the target address if this is a relative jump or call
12442  * The function returns the length of this instruction in bytes.
12443  */
12444
12445 static char intel_syntax;
12446 static char intel_mnemonic = !SYSV386_COMPAT;
12447 static char open_char;
12448 static char close_char;
12449 static char separator_char;
12450 static char scale_char;
12451
12452 enum x86_64_isa
12453 {
12454   amd64 = 0,
12455   intel64
12456 };
12457
12458 static enum x86_64_isa isa64;
12459
12460 /* Here for backwards compatibility.  When gdb stops using
12461    print_insn_i386_att and print_insn_i386_intel these functions can
12462    disappear, and print_insn_i386 be merged into print_insn.  */
12463 int
12464 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
12465 {
12466   intel_syntax = 0;
12467
12468   return print_insn (pc, info);
12469 }
12470
12471 int
12472 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
12473 {
12474   intel_syntax = 1;
12475
12476   return print_insn (pc, info);
12477 }
12478
12479 int
12480 print_insn_i386 (bfd_vma pc, disassemble_info *info)
12481 {
12482   intel_syntax = -1;
12483
12484   return print_insn (pc, info);
12485 }
12486
12487 void
12488 print_i386_disassembler_options (FILE *stream)
12489 {
12490   fprintf (stream, _("\n\
12491 The following i386/x86-64 specific disassembler options are supported for use\n\
12492 with the -M switch (multiple options should be separated by commas):\n"));
12493
12494   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
12495   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
12496   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
12497   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
12498   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
12499   fprintf (stream, _("  att-mnemonic\n"
12500                      "              Display instruction in AT&T mnemonic\n"));
12501   fprintf (stream, _("  intel-mnemonic\n"
12502                      "              Display instruction in Intel mnemonic\n"));
12503   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
12504   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
12505   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
12506   fprintf (stream, _("  data32      Assume 32bit data size\n"));
12507   fprintf (stream, _("  data16      Assume 16bit data size\n"));
12508   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
12509   fprintf (stream, _("  amd64       Display instruction in AMD64 ISA\n"));
12510   fprintf (stream, _("  intel64     Display instruction in Intel64 ISA\n"));
12511 }
12512
12513 /* Bad opcode.  */
12514 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
12515
12516 /* Get a pointer to struct dis386 with a valid name.  */
12517
12518 static const struct dis386 *
12519 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
12520 {
12521   int vindex, vex_table_index;
12522
12523   if (dp->name != NULL)
12524     return dp;
12525
12526   switch (dp->op[0].bytemode)
12527     {
12528     case USE_REG_TABLE:
12529       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
12530       break;
12531
12532     case USE_MOD_TABLE:
12533       vindex = modrm.mod == 0x3 ? 1 : 0;
12534       dp = &mod_table[dp->op[1].bytemode][vindex];
12535       break;
12536
12537     case USE_RM_TABLE:
12538       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
12539       break;
12540
12541     case USE_PREFIX_TABLE:
12542       if (need_vex)
12543         {
12544           /* The prefix in VEX is implicit.  */
12545           switch (vex.prefix)
12546             {
12547             case 0:
12548               vindex = 0;
12549               break;
12550             case REPE_PREFIX_OPCODE:
12551               vindex = 1;
12552               break;
12553             case DATA_PREFIX_OPCODE:
12554               vindex = 2;
12555               break;
12556             case REPNE_PREFIX_OPCODE:
12557               vindex = 3;
12558               break;
12559             default:
12560               abort ();
12561               break;
12562             }
12563         }
12564       else
12565         {
12566           int last_prefix = -1;
12567           int prefix = 0;
12568           vindex = 0;
12569           /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
12570              When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
12571              last one wins.  */
12572           if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
12573             {
12574               if (last_repz_prefix > last_repnz_prefix)
12575                 {
12576                   vindex = 1;
12577                   prefix = PREFIX_REPZ;
12578                   last_prefix = last_repz_prefix;
12579                 }
12580               else
12581                 {
12582                   vindex = 3;
12583                   prefix = PREFIX_REPNZ;
12584                   last_prefix = last_repnz_prefix;
12585                 }
12586
12587               /* Check if prefix should be ignored.  */
12588               if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
12589                      & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
12590                    & prefix) != 0)
12591                 vindex = 0;
12592             }
12593
12594           if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
12595             {
12596               vindex = 2;
12597               prefix = PREFIX_DATA;
12598               last_prefix = last_data_prefix;
12599             }
12600
12601           if (vindex != 0)
12602             {
12603               used_prefixes |= prefix;
12604               all_prefixes[last_prefix] = 0;
12605             }
12606         }
12607       dp = &prefix_table[dp->op[1].bytemode][vindex];
12608       break;
12609
12610     case USE_X86_64_TABLE:
12611       vindex = address_mode == mode_64bit ? 1 : 0;
12612       dp = &x86_64_table[dp->op[1].bytemode][vindex];
12613       break;
12614
12615     case USE_3BYTE_TABLE:
12616       FETCH_DATA (info, codep + 2);
12617       vindex = *codep++;
12618       dp = &three_byte_table[dp->op[1].bytemode][vindex];
12619       end_codep = codep;
12620       modrm.mod = (*codep >> 6) & 3;
12621       modrm.reg = (*codep >> 3) & 7;
12622       modrm.rm = *codep & 7;
12623       break;
12624
12625     case USE_VEX_LEN_TABLE:
12626       if (!need_vex)
12627         abort ();
12628
12629       switch (vex.length)
12630         {
12631         case 128:
12632           vindex = 0;
12633           break;
12634         case 256:
12635           vindex = 1;
12636           break;
12637         default:
12638           abort ();
12639           break;
12640         }
12641
12642       dp = &vex_len_table[dp->op[1].bytemode][vindex];
12643       break;
12644
12645     case USE_XOP_8F_TABLE:
12646       FETCH_DATA (info, codep + 3);
12647       /* All bits in the REX prefix are ignored.  */
12648       rex_ignored = rex;
12649       rex = ~(*codep >> 5) & 0x7;
12650
12651       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
12652       switch ((*codep & 0x1f))
12653         {
12654         default:
12655           dp = &bad_opcode;
12656           return dp;
12657         case 0x8:
12658           vex_table_index = XOP_08;
12659           break;
12660         case 0x9:
12661           vex_table_index = XOP_09;
12662           break;
12663         case 0xa:
12664           vex_table_index = XOP_0A;
12665           break;
12666         }
12667       codep++;
12668       vex.w = *codep & 0x80;
12669       if (vex.w && address_mode == mode_64bit)
12670         rex |= REX_W;
12671
12672       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12673       if (address_mode != mode_64bit
12674           && vex.register_specifier > 0x7)
12675         {
12676           dp = &bad_opcode;
12677           return dp;
12678         }
12679
12680       vex.length = (*codep & 0x4) ? 256 : 128;
12681       switch ((*codep & 0x3))
12682         {
12683         case 0:
12684           vex.prefix = 0;
12685           break;
12686         case 1:
12687           vex.prefix = DATA_PREFIX_OPCODE;
12688           break;
12689         case 2:
12690           vex.prefix = REPE_PREFIX_OPCODE;
12691           break;
12692         case 3:
12693           vex.prefix = REPNE_PREFIX_OPCODE;
12694           break;
12695         }
12696       need_vex = 1;
12697       need_vex_reg = 1;
12698       codep++;
12699       vindex = *codep++;
12700       dp = &xop_table[vex_table_index][vindex];
12701
12702       end_codep = codep;
12703       FETCH_DATA (info, codep + 1);
12704       modrm.mod = (*codep >> 6) & 3;
12705       modrm.reg = (*codep >> 3) & 7;
12706       modrm.rm = *codep & 7;
12707       break;
12708
12709     case USE_VEX_C4_TABLE:
12710       /* VEX prefix.  */
12711       FETCH_DATA (info, codep + 3);
12712       /* All bits in the REX prefix are ignored.  */
12713       rex_ignored = rex;
12714       rex = ~(*codep >> 5) & 0x7;
12715       switch ((*codep & 0x1f))
12716         {
12717         default:
12718           dp = &bad_opcode;
12719           return dp;
12720         case 0x1:
12721           vex_table_index = VEX_0F;
12722           break;
12723         case 0x2:
12724           vex_table_index = VEX_0F38;
12725           break;
12726         case 0x3:
12727           vex_table_index = VEX_0F3A;
12728           break;
12729         }
12730       codep++;
12731       vex.w = *codep & 0x80;
12732       if (address_mode == mode_64bit)
12733         {
12734           if (vex.w)
12735             rex |= REX_W;
12736           vex.register_specifier = (~(*codep >> 3)) & 0xf;
12737         }
12738       else
12739         {
12740           /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
12741              is ignored, other REX bits are 0 and the highest bit in
12742              VEX.vvvv is also ignored.  */
12743           rex = 0;
12744           vex.register_specifier = (~(*codep >> 3)) & 0x7;
12745         }
12746       vex.length = (*codep & 0x4) ? 256 : 128;
12747       switch ((*codep & 0x3))
12748         {
12749         case 0:
12750           vex.prefix = 0;
12751           break;
12752         case 1:
12753           vex.prefix = DATA_PREFIX_OPCODE;
12754           break;
12755         case 2:
12756           vex.prefix = REPE_PREFIX_OPCODE;
12757           break;
12758         case 3:
12759           vex.prefix = REPNE_PREFIX_OPCODE;
12760           break;
12761         }
12762       need_vex = 1;
12763       need_vex_reg = 1;
12764       codep++;
12765       vindex = *codep++;
12766       dp = &vex_table[vex_table_index][vindex];
12767       end_codep = codep;
12768       /* There is no MODRM byte for VEX [82|77].  */
12769       if (vindex != 0x77 && vindex != 0x82)
12770         {
12771           FETCH_DATA (info, codep + 1);
12772           modrm.mod = (*codep >> 6) & 3;
12773           modrm.reg = (*codep >> 3) & 7;
12774           modrm.rm = *codep & 7;
12775         }
12776       break;
12777
12778     case USE_VEX_C5_TABLE:
12779       /* VEX prefix.  */
12780       FETCH_DATA (info, codep + 2);
12781       /* All bits in the REX prefix are ignored.  */
12782       rex_ignored = rex;
12783       rex = (*codep & 0x80) ? 0 : REX_R;
12784
12785       /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
12786          VEX.vvvv is 1.  */
12787       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12788       vex.w = 0;
12789       vex.length = (*codep & 0x4) ? 256 : 128;
12790       switch ((*codep & 0x3))
12791         {
12792         case 0:
12793           vex.prefix = 0;
12794           break;
12795         case 1:
12796           vex.prefix = DATA_PREFIX_OPCODE;
12797           break;
12798         case 2:
12799           vex.prefix = REPE_PREFIX_OPCODE;
12800           break;
12801         case 3:
12802           vex.prefix = REPNE_PREFIX_OPCODE;
12803           break;
12804         }
12805       need_vex = 1;
12806       need_vex_reg = 1;
12807       codep++;
12808       vindex = *codep++;
12809       dp = &vex_table[dp->op[1].bytemode][vindex];
12810       end_codep = codep;
12811       /* There is no MODRM byte for VEX [82|77].  */
12812       if (vindex != 0x77 && vindex != 0x82)
12813         {
12814           FETCH_DATA (info, codep + 1);
12815           modrm.mod = (*codep >> 6) & 3;
12816           modrm.reg = (*codep >> 3) & 7;
12817           modrm.rm = *codep & 7;
12818         }
12819       break;
12820
12821     case USE_VEX_W_TABLE:
12822       if (!need_vex)
12823         abort ();
12824
12825       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
12826       break;
12827
12828     case USE_EVEX_TABLE:
12829       two_source_ops = 0;
12830       /* EVEX prefix.  */
12831       vex.evex = 1;
12832       FETCH_DATA (info, codep + 4);
12833       /* All bits in the REX prefix are ignored.  */
12834       rex_ignored = rex;
12835       /* The first byte after 0x62.  */
12836       rex = ~(*codep >> 5) & 0x7;
12837       vex.r = *codep & 0x10;
12838       switch ((*codep & 0xf))
12839         {
12840         default:
12841           return &bad_opcode;
12842         case 0x1:
12843           vex_table_index = EVEX_0F;
12844           break;
12845         case 0x2:
12846           vex_table_index = EVEX_0F38;
12847           break;
12848         case 0x3:
12849           vex_table_index = EVEX_0F3A;
12850           break;
12851         }
12852
12853       /* The second byte after 0x62.  */
12854       codep++;
12855       vex.w = *codep & 0x80;
12856       if (vex.w && address_mode == mode_64bit)
12857         rex |= REX_W;
12858
12859       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12860       if (address_mode != mode_64bit)
12861         {
12862           /* In 16/32-bit mode silently ignore following bits.  */
12863           rex &= ~REX_B;
12864           vex.r = 1;
12865           vex.v = 1;
12866           vex.register_specifier &= 0x7;
12867         }
12868
12869       /* The U bit.  */
12870       if (!(*codep & 0x4))
12871         return &bad_opcode;
12872
12873       switch ((*codep & 0x3))
12874         {
12875         case 0:
12876           vex.prefix = 0;
12877           break;
12878         case 1:
12879           vex.prefix = DATA_PREFIX_OPCODE;
12880           break;
12881         case 2:
12882           vex.prefix = REPE_PREFIX_OPCODE;
12883           break;
12884         case 3:
12885           vex.prefix = REPNE_PREFIX_OPCODE;
12886           break;
12887         }
12888
12889       /* The third byte after 0x62.  */
12890       codep++;
12891
12892       /* Remember the static rounding bits.  */
12893       vex.ll = (*codep >> 5) & 3;
12894       vex.b = (*codep & 0x10) != 0;
12895
12896       vex.v = *codep & 0x8;
12897       vex.mask_register_specifier = *codep & 0x7;
12898       vex.zeroing = *codep & 0x80;
12899
12900       need_vex = 1;
12901       need_vex_reg = 1;
12902       codep++;
12903       vindex = *codep++;
12904       dp = &evex_table[vex_table_index][vindex];
12905       end_codep = codep;
12906       FETCH_DATA (info, codep + 1);
12907       modrm.mod = (*codep >> 6) & 3;
12908       modrm.reg = (*codep >> 3) & 7;
12909       modrm.rm = *codep & 7;
12910
12911       /* Set vector length.  */
12912       if (modrm.mod == 3 && vex.b)
12913         vex.length = 512;
12914       else
12915         {
12916           switch (vex.ll)
12917             {
12918             case 0x0:
12919               vex.length = 128;
12920               break;
12921             case 0x1:
12922               vex.length = 256;
12923               break;
12924             case 0x2:
12925               vex.length = 512;
12926               break;
12927             default:
12928               return &bad_opcode;
12929             }
12930         }
12931       break;
12932
12933     case 0:
12934       dp = &bad_opcode;
12935       break;
12936
12937     default:
12938       abort ();
12939     }
12940
12941   if (dp->name != NULL)
12942     return dp;
12943   else
12944     return get_valid_dis386 (dp, info);
12945 }
12946
12947 static void
12948 get_sib (disassemble_info *info, int sizeflag)
12949 {
12950   /* If modrm.mod == 3, operand must be register.  */
12951   if (need_modrm
12952       && ((sizeflag & AFLAG) || address_mode == mode_64bit)
12953       && modrm.mod != 3
12954       && modrm.rm == 4)
12955     {
12956       FETCH_DATA (info, codep + 2);
12957       sib.index = (codep [1] >> 3) & 7;
12958       sib.scale = (codep [1] >> 6) & 3;
12959       sib.base = codep [1] & 7;
12960     }
12961 }
12962
12963 static int
12964 print_insn (bfd_vma pc, disassemble_info *info)
12965 {
12966   const struct dis386 *dp;
12967   int i;
12968   char *op_txt[MAX_OPERANDS];
12969   int needcomma;
12970   int sizeflag, orig_sizeflag;
12971   const char *p;
12972   struct dis_private priv;
12973   int prefix_length;
12974
12975   priv.orig_sizeflag = AFLAG | DFLAG;
12976   if ((info->mach & bfd_mach_i386_i386) != 0)
12977     address_mode = mode_32bit;
12978   else if (info->mach == bfd_mach_i386_i8086)
12979     {
12980       address_mode = mode_16bit;
12981       priv.orig_sizeflag = 0;
12982     }
12983   else
12984     address_mode = mode_64bit;
12985
12986   if (intel_syntax == (char) -1)
12987     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
12988
12989   for (p = info->disassembler_options; p != NULL; )
12990     {
12991       if (CONST_STRNEQ (p, "amd64"))
12992         isa64 = amd64;
12993       else if (CONST_STRNEQ (p, "intel64"))
12994         isa64 = intel64;
12995       else if (CONST_STRNEQ (p, "x86-64"))
12996         {
12997           address_mode = mode_64bit;
12998           priv.orig_sizeflag = AFLAG | DFLAG;
12999         }
13000       else if (CONST_STRNEQ (p, "i386"))
13001         {
13002           address_mode = mode_32bit;
13003           priv.orig_sizeflag = AFLAG | DFLAG;
13004         }
13005       else if (CONST_STRNEQ (p, "i8086"))
13006         {
13007           address_mode = mode_16bit;
13008           priv.orig_sizeflag = 0;
13009         }
13010       else if (CONST_STRNEQ (p, "intel"))
13011         {
13012           intel_syntax = 1;
13013           if (CONST_STRNEQ (p + 5, "-mnemonic"))
13014             intel_mnemonic = 1;
13015         }
13016       else if (CONST_STRNEQ (p, "att"))
13017         {
13018           intel_syntax = 0;
13019           if (CONST_STRNEQ (p + 3, "-mnemonic"))
13020             intel_mnemonic = 0;
13021         }
13022       else if (CONST_STRNEQ (p, "addr"))
13023         {
13024           if (address_mode == mode_64bit)
13025             {
13026               if (p[4] == '3' && p[5] == '2')
13027                 priv.orig_sizeflag &= ~AFLAG;
13028               else if (p[4] == '6' && p[5] == '4')
13029                 priv.orig_sizeflag |= AFLAG;
13030             }
13031           else
13032             {
13033               if (p[4] == '1' && p[5] == '6')
13034                 priv.orig_sizeflag &= ~AFLAG;
13035               else if (p[4] == '3' && p[5] == '2')
13036                 priv.orig_sizeflag |= AFLAG;
13037             }
13038         }
13039       else if (CONST_STRNEQ (p, "data"))
13040         {
13041           if (p[4] == '1' && p[5] == '6')
13042             priv.orig_sizeflag &= ~DFLAG;
13043           else if (p[4] == '3' && p[5] == '2')
13044             priv.orig_sizeflag |= DFLAG;
13045         }
13046       else if (CONST_STRNEQ (p, "suffix"))
13047         priv.orig_sizeflag |= SUFFIX_ALWAYS;
13048
13049       p = strchr (p, ',');
13050       if (p != NULL)
13051         p++;
13052     }
13053
13054   if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
13055     {
13056       (*info->fprintf_func) (info->stream,
13057                              _("64-bit address is disabled"));
13058       return -1;
13059     }
13060
13061   if (intel_syntax)
13062     {
13063       names64 = intel_names64;
13064       names32 = intel_names32;
13065       names16 = intel_names16;
13066       names8 = intel_names8;
13067       names8rex = intel_names8rex;
13068       names_seg = intel_names_seg;
13069       names_mm = intel_names_mm;
13070       names_bnd = intel_names_bnd;
13071       names_xmm = intel_names_xmm;
13072       names_ymm = intel_names_ymm;
13073       names_zmm = intel_names_zmm;
13074       index64 = intel_index64;
13075       index32 = intel_index32;
13076       names_mask = intel_names_mask;
13077       index16 = intel_index16;
13078       open_char = '[';
13079       close_char = ']';
13080       separator_char = '+';
13081       scale_char = '*';
13082     }
13083   else
13084     {
13085       names64 = att_names64;
13086       names32 = att_names32;
13087       names16 = att_names16;
13088       names8 = att_names8;
13089       names8rex = att_names8rex;
13090       names_seg = att_names_seg;
13091       names_mm = att_names_mm;
13092       names_bnd = att_names_bnd;
13093       names_xmm = att_names_xmm;
13094       names_ymm = att_names_ymm;
13095       names_zmm = att_names_zmm;
13096       index64 = att_index64;
13097       index32 = att_index32;
13098       names_mask = att_names_mask;
13099       index16 = att_index16;
13100       open_char = '(';
13101       close_char =  ')';
13102       separator_char = ',';
13103       scale_char = ',';
13104     }
13105
13106   /* The output looks better if we put 7 bytes on a line, since that
13107      puts most long word instructions on a single line.  Use 8 bytes
13108      for Intel L1OM.  */
13109   if ((info->mach & bfd_mach_l1om) != 0)
13110     info->bytes_per_line = 8;
13111   else
13112     info->bytes_per_line = 7;
13113
13114   info->private_data = &priv;
13115   priv.max_fetched = priv.the_buffer;
13116   priv.insn_start = pc;
13117
13118   obuf[0] = 0;
13119   for (i = 0; i < MAX_OPERANDS; ++i)
13120     {
13121       op_out[i][0] = 0;
13122       op_index[i] = -1;
13123     }
13124
13125   the_info = info;
13126   start_pc = pc;
13127   start_codep = priv.the_buffer;
13128   codep = priv.the_buffer;
13129
13130   if (OPCODES_SIGSETJMP (priv.bailout) != 0)
13131     {
13132       const char *name;
13133
13134       /* Getting here means we tried for data but didn't get it.  That
13135          means we have an incomplete instruction of some sort.  Just
13136          print the first byte as a prefix or a .byte pseudo-op.  */
13137       if (codep > priv.the_buffer)
13138         {
13139           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
13140           if (name != NULL)
13141             (*info->fprintf_func) (info->stream, "%s", name);
13142           else
13143             {
13144               /* Just print the first byte as a .byte instruction.  */
13145               (*info->fprintf_func) (info->stream, ".byte 0x%x",
13146                                      (unsigned int) priv.the_buffer[0]);
13147             }
13148
13149           return 1;
13150         }
13151
13152       return -1;
13153     }
13154
13155   obufp = obuf;
13156   sizeflag = priv.orig_sizeflag;
13157
13158   if (!ckprefix () || rex_used)
13159     {
13160       /* Too many prefixes or unused REX prefixes.  */
13161       for (i = 0;
13162            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
13163            i++)
13164         (*info->fprintf_func) (info->stream, "%s%s",
13165                                i == 0 ? "" : " ",
13166                                prefix_name (all_prefixes[i], sizeflag));
13167       return i;
13168     }
13169
13170   insn_codep = codep;
13171
13172   FETCH_DATA (info, codep + 1);
13173   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
13174
13175   if (((prefixes & PREFIX_FWAIT)
13176        && ((*codep < 0xd8) || (*codep > 0xdf))))
13177     {
13178       /* Handle prefixes before fwait.  */
13179       for (i = 0; i < fwait_prefix && all_prefixes[i];
13180            i++)
13181         (*info->fprintf_func) (info->stream, "%s ",
13182                                prefix_name (all_prefixes[i], sizeflag));
13183       (*info->fprintf_func) (info->stream, "fwait");
13184       return i + 1;
13185     }
13186
13187   if (*codep == 0x0f)
13188     {
13189       unsigned char threebyte;
13190
13191       codep++;
13192       FETCH_DATA (info, codep + 1);
13193       threebyte = *codep;
13194       dp = &dis386_twobyte[threebyte];
13195       need_modrm = twobyte_has_modrm[*codep];
13196       codep++;
13197     }
13198   else
13199     {
13200       dp = &dis386[*codep];
13201       need_modrm = onebyte_has_modrm[*codep];
13202       codep++;
13203     }
13204
13205   /* Save sizeflag for printing the extra prefixes later before updating
13206      it for mnemonic and operand processing.  The prefix names depend
13207      only on the address mode.  */
13208   orig_sizeflag = sizeflag;
13209   if (prefixes & PREFIX_ADDR)
13210     sizeflag ^= AFLAG;
13211   if ((prefixes & PREFIX_DATA))
13212     sizeflag ^= DFLAG;
13213
13214   end_codep = codep;
13215   if (need_modrm)
13216     {
13217       FETCH_DATA (info, codep + 1);
13218       modrm.mod = (*codep >> 6) & 3;
13219       modrm.reg = (*codep >> 3) & 7;
13220       modrm.rm = *codep & 7;
13221     }
13222
13223   need_vex = 0;
13224   need_vex_reg = 0;
13225   vex_w_done = 0;
13226   vex.evex = 0;
13227
13228   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
13229     {
13230       get_sib (info, sizeflag);
13231       dofloat (sizeflag);
13232     }
13233   else
13234     {
13235       dp = get_valid_dis386 (dp, info);
13236       if (dp != NULL && putop (dp->name, sizeflag) == 0)
13237         {
13238           get_sib (info, sizeflag);
13239           for (i = 0; i < MAX_OPERANDS; ++i)
13240             {
13241               obufp = op_out[i];
13242               op_ad = MAX_OPERANDS - 1 - i;
13243               if (dp->op[i].rtn)
13244                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
13245               /* For EVEX instruction after the last operand masking
13246                  should be printed.  */
13247               if (i == 0 && vex.evex)
13248                 {
13249                   /* Don't print {%k0}.  */
13250                   if (vex.mask_register_specifier)
13251                     {
13252                       oappend ("{");
13253                       oappend (names_mask[vex.mask_register_specifier]);
13254                       oappend ("}");
13255                     }
13256                   if (vex.zeroing)
13257                     oappend ("{z}");
13258                 }
13259             }
13260         }
13261     }
13262
13263   /* Check if the REX prefix is used.  */
13264   if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)
13265     all_prefixes[last_rex_prefix] = 0;
13266
13267   /* Check if the SEG prefix is used.  */
13268   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
13269                    | PREFIX_FS | PREFIX_GS)) != 0
13270       && (used_prefixes & active_seg_prefix) != 0)
13271     all_prefixes[last_seg_prefix] = 0;
13272
13273   /* Check if the ADDR prefix is used.  */
13274   if ((prefixes & PREFIX_ADDR) != 0
13275       && (used_prefixes & PREFIX_ADDR) != 0)
13276     all_prefixes[last_addr_prefix] = 0;
13277
13278   /* Check if the DATA prefix is used.  */
13279   if ((prefixes & PREFIX_DATA) != 0
13280       && (used_prefixes & PREFIX_DATA) != 0)
13281     all_prefixes[last_data_prefix] = 0;
13282
13283   /* Print the extra prefixes.  */
13284   prefix_length = 0;
13285   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
13286     if (all_prefixes[i])
13287       {
13288         const char *name;
13289         name = prefix_name (all_prefixes[i], orig_sizeflag);
13290         if (name == NULL)
13291           abort ();
13292         prefix_length += strlen (name) + 1;
13293         (*info->fprintf_func) (info->stream, "%s ", name);
13294       }
13295
13296   /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
13297      unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
13298      used by putop and MMX/SSE operand and may be overriden by the
13299      PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
13300      separately.  */
13301   if (dp->prefix_requirement == PREFIX_OPCODE
13302       && dp != &bad_opcode
13303       && (((prefixes
13304             & (PREFIX_REPZ | PREFIX_REPNZ)) != 0
13305            && (used_prefixes
13306                & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
13307           || ((((prefixes
13308                  & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
13309                 == PREFIX_DATA)
13310                && (used_prefixes & PREFIX_DATA) == 0))))
13311     {
13312       (*info->fprintf_func) (info->stream, "(bad)");
13313       return end_codep - priv.the_buffer;
13314     }
13315
13316   /* Check maximum code length.  */
13317   if ((codep - start_codep) > MAX_CODE_LENGTH)
13318     {
13319       (*info->fprintf_func) (info->stream, "(bad)");
13320       return MAX_CODE_LENGTH;
13321     }
13322
13323   obufp = mnemonicendp;
13324   for (i = strlen (obuf) + prefix_length; i < 6; i++)
13325     oappend (" ");
13326   oappend (" ");
13327   (*info->fprintf_func) (info->stream, "%s", obuf);
13328
13329   /* The enter and bound instructions are printed with operands in the same
13330      order as the intel book; everything else is printed in reverse order.  */
13331   if (intel_syntax || two_source_ops)
13332     {
13333       bfd_vma riprel;
13334
13335       for (i = 0; i < MAX_OPERANDS; ++i)
13336         op_txt[i] = op_out[i];
13337
13338       if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
13339           && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
13340         {
13341           op_txt[2] = op_out[3];
13342           op_txt[3] = op_out[2];
13343         }
13344
13345       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
13346         {
13347           op_ad = op_index[i];
13348           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
13349           op_index[MAX_OPERANDS - 1 - i] = op_ad;
13350           riprel = op_riprel[i];
13351           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
13352           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
13353         }
13354     }
13355   else
13356     {
13357       for (i = 0; i < MAX_OPERANDS; ++i)
13358         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
13359     }
13360
13361   needcomma = 0;
13362   for (i = 0; i < MAX_OPERANDS; ++i)
13363     if (*op_txt[i])
13364       {
13365         if (needcomma)
13366           (*info->fprintf_func) (info->stream, ",");
13367         if (op_index[i] != -1 && !op_riprel[i])
13368           (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
13369         else
13370           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
13371         needcomma = 1;
13372       }
13373
13374   for (i = 0; i < MAX_OPERANDS; i++)
13375     if (op_index[i] != -1 && op_riprel[i])
13376       {
13377         (*info->fprintf_func) (info->stream, "        # ");
13378         (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
13379                                                 + op_address[op_index[i]]), info);
13380         break;
13381       }
13382   return codep - priv.the_buffer;
13383 }
13384
13385 static const char *float_mem[] = {
13386   /* d8 */
13387   "fadd{s|}",
13388   "fmul{s|}",
13389   "fcom{s|}",
13390   "fcomp{s|}",
13391   "fsub{s|}",
13392   "fsubr{s|}",
13393   "fdiv{s|}",
13394   "fdivr{s|}",
13395   /* d9 */
13396   "fld{s|}",
13397   "(bad)",
13398   "fst{s|}",
13399   "fstp{s|}",
13400   "fldenvIC",
13401   "fldcw",
13402   "fNstenvIC",
13403   "fNstcw",
13404   /* da */
13405   "fiadd{l|}",
13406   "fimul{l|}",
13407   "ficom{l|}",
13408   "ficomp{l|}",
13409   "fisub{l|}",
13410   "fisubr{l|}",
13411   "fidiv{l|}",
13412   "fidivr{l|}",
13413   /* db */
13414   "fild{l|}",
13415   "fisttp{l|}",
13416   "fist{l|}",
13417   "fistp{l|}",
13418   "(bad)",
13419   "fld{t||t|}",
13420   "(bad)",
13421   "fstp{t||t|}",
13422   /* dc */
13423   "fadd{l|}",
13424   "fmul{l|}",
13425   "fcom{l|}",
13426   "fcomp{l|}",
13427   "fsub{l|}",
13428   "fsubr{l|}",
13429   "fdiv{l|}",
13430   "fdivr{l|}",
13431   /* dd */
13432   "fld{l|}",
13433   "fisttp{ll|}",
13434   "fst{l||}",
13435   "fstp{l|}",
13436   "frstorIC",
13437   "(bad)",
13438   "fNsaveIC",
13439   "fNstsw",
13440   /* de */
13441   "fiadd",
13442   "fimul",
13443   "ficom",
13444   "ficomp",
13445   "fisub",
13446   "fisubr",
13447   "fidiv",
13448   "fidivr",
13449   /* df */
13450   "fild",
13451   "fisttp",
13452   "fist",
13453   "fistp",
13454   "fbld",
13455   "fild{ll|}",
13456   "fbstp",
13457   "fistp{ll|}",
13458 };
13459
13460 static const unsigned char float_mem_mode[] = {
13461   /* d8 */
13462   d_mode,
13463   d_mode,
13464   d_mode,
13465   d_mode,
13466   d_mode,
13467   d_mode,
13468   d_mode,
13469   d_mode,
13470   /* d9 */
13471   d_mode,
13472   0,
13473   d_mode,
13474   d_mode,
13475   0,
13476   w_mode,
13477   0,
13478   w_mode,
13479   /* da */
13480   d_mode,
13481   d_mode,
13482   d_mode,
13483   d_mode,
13484   d_mode,
13485   d_mode,
13486   d_mode,
13487   d_mode,
13488   /* db */
13489   d_mode,
13490   d_mode,
13491   d_mode,
13492   d_mode,
13493   0,
13494   t_mode,
13495   0,
13496   t_mode,
13497   /* dc */
13498   q_mode,
13499   q_mode,
13500   q_mode,
13501   q_mode,
13502   q_mode,
13503   q_mode,
13504   q_mode,
13505   q_mode,
13506   /* dd */
13507   q_mode,
13508   q_mode,
13509   q_mode,
13510   q_mode,
13511   0,
13512   0,
13513   0,
13514   w_mode,
13515   /* de */
13516   w_mode,
13517   w_mode,
13518   w_mode,
13519   w_mode,
13520   w_mode,
13521   w_mode,
13522   w_mode,
13523   w_mode,
13524   /* df */
13525   w_mode,
13526   w_mode,
13527   w_mode,
13528   w_mode,
13529   t_mode,
13530   q_mode,
13531   t_mode,
13532   q_mode
13533 };
13534
13535 #define ST { OP_ST, 0 }
13536 #define STi { OP_STi, 0 }
13537
13538 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
13539 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
13540 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
13541 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
13542 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
13543 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
13544 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
13545 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
13546 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
13547
13548 static const struct dis386 float_reg[][8] = {
13549   /* d8 */
13550   {
13551     { "fadd",   { ST, STi }, 0 },
13552     { "fmul",   { ST, STi }, 0 },
13553     { "fcom",   { STi }, 0 },
13554     { "fcomp",  { STi }, 0 },
13555     { "fsub",   { ST, STi }, 0 },
13556     { "fsubr",  { ST, STi }, 0 },
13557     { "fdiv",   { ST, STi }, 0 },
13558     { "fdivr",  { ST, STi }, 0 },
13559   },
13560   /* d9 */
13561   {
13562     { "fld",    { STi }, 0 },
13563     { "fxch",   { STi }, 0 },
13564     { FGRPd9_2 },
13565     { Bad_Opcode },
13566     { FGRPd9_4 },
13567     { FGRPd9_5 },
13568     { FGRPd9_6 },
13569     { FGRPd9_7 },
13570   },
13571   /* da */
13572   {
13573     { "fcmovb", { ST, STi }, 0 },
13574     { "fcmove", { ST, STi }, 0 },
13575     { "fcmovbe",{ ST, STi }, 0 },
13576     { "fcmovu", { ST, STi }, 0 },
13577     { Bad_Opcode },
13578     { FGRPda_5 },
13579     { Bad_Opcode },
13580     { Bad_Opcode },
13581   },
13582   /* db */
13583   {
13584     { "fcmovnb",{ ST, STi }, 0 },
13585     { "fcmovne",{ ST, STi }, 0 },
13586     { "fcmovnbe",{ ST, STi }, 0 },
13587     { "fcmovnu",{ ST, STi }, 0 },
13588     { FGRPdb_4 },
13589     { "fucomi", { ST, STi }, 0 },
13590     { "fcomi",  { ST, STi }, 0 },
13591     { Bad_Opcode },
13592   },
13593   /* dc */
13594   {
13595     { "fadd",   { STi, ST }, 0 },
13596     { "fmul",   { STi, ST }, 0 },
13597     { Bad_Opcode },
13598     { Bad_Opcode },
13599     { "fsub!M", { STi, ST }, 0 },
13600     { "fsubM",  { STi, ST }, 0 },
13601     { "fdiv!M", { STi, ST }, 0 },
13602     { "fdivM",  { STi, ST }, 0 },
13603   },
13604   /* dd */
13605   {
13606     { "ffree",  { STi }, 0 },
13607     { Bad_Opcode },
13608     { "fst",    { STi }, 0 },
13609     { "fstp",   { STi }, 0 },
13610     { "fucom",  { STi }, 0 },
13611     { "fucomp", { STi }, 0 },
13612     { Bad_Opcode },
13613     { Bad_Opcode },
13614   },
13615   /* de */
13616   {
13617     { "faddp",  { STi, ST }, 0 },
13618     { "fmulp",  { STi, ST }, 0 },
13619     { Bad_Opcode },
13620     { FGRPde_3 },
13621     { "fsub!Mp", { STi, ST }, 0 },
13622     { "fsubMp", { STi, ST }, 0 },
13623     { "fdiv!Mp", { STi, ST }, 0 },
13624     { "fdivMp", { STi, ST }, 0 },
13625   },
13626   /* df */
13627   {
13628     { "ffreep", { STi }, 0 },
13629     { Bad_Opcode },
13630     { Bad_Opcode },
13631     { Bad_Opcode },
13632     { FGRPdf_4 },
13633     { "fucomip", { ST, STi }, 0 },
13634     { "fcomip", { ST, STi }, 0 },
13635     { Bad_Opcode },
13636   },
13637 };
13638
13639 static char *fgrps[][8] = {
13640   /* Bad opcode 0 */
13641   {
13642     "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13643   },
13644
13645   /* d9_2  1 */
13646   {
13647     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13648   },
13649
13650   /* d9_4  2 */
13651   {
13652     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
13653   },
13654
13655   /* d9_5  3 */
13656   {
13657     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
13658   },
13659
13660   /* d9_6  4 */
13661   {
13662     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
13663   },
13664
13665   /* d9_7  5 */
13666   {
13667     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
13668   },
13669
13670   /* da_5  6 */
13671   {
13672     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13673   },
13674
13675   /* db_4  7 */
13676   {
13677     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
13678     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
13679   },
13680
13681   /* de_3  8 */
13682   {
13683     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13684   },
13685
13686   /* df_4  9 */
13687   {
13688     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13689   },
13690 };
13691
13692 static void
13693 swap_operand (void)
13694 {
13695   mnemonicendp[0] = '.';
13696   mnemonicendp[1] = 's';
13697   mnemonicendp += 2;
13698 }
13699
13700 static void
13701 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
13702                int sizeflag ATTRIBUTE_UNUSED)
13703 {
13704   /* Skip mod/rm byte.  */
13705   MODRM_CHECK;
13706   codep++;
13707 }
13708
13709 static void
13710 dofloat (int sizeflag)
13711 {
13712   const struct dis386 *dp;
13713   unsigned char floatop;
13714
13715   floatop = codep[-1];
13716
13717   if (modrm.mod != 3)
13718     {
13719       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
13720
13721       putop (float_mem[fp_indx], sizeflag);
13722       obufp = op_out[0];
13723       op_ad = 2;
13724       OP_E (float_mem_mode[fp_indx], sizeflag);
13725       return;
13726     }
13727   /* Skip mod/rm byte.  */
13728   MODRM_CHECK;
13729   codep++;
13730
13731   dp = &float_reg[floatop - 0xd8][modrm.reg];
13732   if (dp->name == NULL)
13733     {
13734       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
13735
13736       /* Instruction fnstsw is only one with strange arg.  */
13737       if (floatop == 0xdf && codep[-1] == 0xe0)
13738         strcpy (op_out[0], names16[0]);
13739     }
13740   else
13741     {
13742       putop (dp->name, sizeflag);
13743
13744       obufp = op_out[0];
13745       op_ad = 2;
13746       if (dp->op[0].rtn)
13747         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
13748
13749       obufp = op_out[1];
13750       op_ad = 1;
13751       if (dp->op[1].rtn)
13752         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
13753     }
13754 }
13755
13756 /* Like oappend (below), but S is a string starting with '%'.
13757    In Intel syntax, the '%' is elided.  */
13758 static void
13759 oappend_maybe_intel (const char *s)
13760 {
13761   oappend (s + intel_syntax);
13762 }
13763
13764 static void
13765 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13766 {
13767   oappend_maybe_intel ("%st");
13768 }
13769
13770 static void
13771 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13772 {
13773   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
13774   oappend_maybe_intel (scratchbuf);
13775 }
13776
13777 /* Capital letters in template are macros.  */
13778 static int
13779 putop (const char *in_template, int sizeflag)
13780 {
13781   const char *p;
13782   int alt = 0;
13783   int cond = 1;
13784   unsigned int l = 0, len = 1;
13785   char last[4];
13786
13787 #define SAVE_LAST(c)                    \
13788   if (l < len && l < sizeof (last))     \
13789     last[l++] = c;                      \
13790   else                                  \
13791     abort ();
13792
13793   for (p = in_template; *p; p++)
13794     {
13795       switch (*p)
13796         {
13797         default:
13798           *obufp++ = *p;
13799           break;
13800         case '%':
13801           len++;
13802           break;
13803         case '!':
13804           cond = 0;
13805           break;
13806         case '{':
13807           if (intel_syntax)
13808             {
13809               while (*++p != '|')
13810                 if (*p == '}' || *p == '\0')
13811                   abort ();
13812             }
13813           /* Fall through.  */
13814         case 'I':
13815           alt = 1;
13816           continue;
13817         case '|':
13818           while (*++p != '}')
13819             {
13820               if (*p == '\0')
13821                 abort ();
13822             }
13823           break;
13824         case '}':
13825           break;
13826         case 'A':
13827           if (intel_syntax)
13828             break;
13829           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13830             *obufp++ = 'b';
13831           break;
13832         case 'B':
13833           if (l == 0 && len == 1)
13834             {
13835 case_B:
13836               if (intel_syntax)
13837                 break;
13838               if (sizeflag & SUFFIX_ALWAYS)
13839                 *obufp++ = 'b';
13840             }
13841           else
13842             {
13843               if (l != 1
13844                   || len != 2
13845                   || last[0] != 'L')
13846                 {
13847                   SAVE_LAST (*p);
13848                   break;
13849                 }
13850
13851               if (address_mode == mode_64bit
13852                   && !(prefixes & PREFIX_ADDR))
13853                 {
13854                   *obufp++ = 'a';
13855                   *obufp++ = 'b';
13856                   *obufp++ = 's';
13857                 }
13858
13859               goto case_B;
13860             }
13861           break;
13862         case 'C':
13863           if (intel_syntax && !alt)
13864             break;
13865           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
13866             {
13867               if (sizeflag & DFLAG)
13868                 *obufp++ = intel_syntax ? 'd' : 'l';
13869               else
13870                 *obufp++ = intel_syntax ? 'w' : 's';
13871               used_prefixes |= (prefixes & PREFIX_DATA);
13872             }
13873           break;
13874         case 'D':
13875           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
13876             break;
13877           USED_REX (REX_W);
13878           if (modrm.mod == 3)
13879             {
13880               if (rex & REX_W)
13881                 *obufp++ = 'q';
13882               else
13883                 {
13884                   if (sizeflag & DFLAG)
13885                     *obufp++ = intel_syntax ? 'd' : 'l';
13886                   else
13887                     *obufp++ = 'w';
13888                   used_prefixes |= (prefixes & PREFIX_DATA);
13889                 }
13890             }
13891           else
13892             *obufp++ = 'w';
13893           break;
13894         case 'E':               /* For jcxz/jecxz */
13895           if (address_mode == mode_64bit)
13896             {
13897               if (sizeflag & AFLAG)
13898                 *obufp++ = 'r';
13899               else
13900                 *obufp++ = 'e';
13901             }
13902           else
13903             if (sizeflag & AFLAG)
13904               *obufp++ = 'e';
13905           used_prefixes |= (prefixes & PREFIX_ADDR);
13906           break;
13907         case 'F':
13908           if (intel_syntax)
13909             break;
13910           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
13911             {
13912               if (sizeflag & AFLAG)
13913                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
13914               else
13915                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
13916               used_prefixes |= (prefixes & PREFIX_ADDR);
13917             }
13918           break;
13919         case 'G':
13920           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
13921             break;
13922           if ((rex & REX_W) || (sizeflag & DFLAG))
13923             *obufp++ = 'l';
13924           else
13925             *obufp++ = 'w';
13926           if (!(rex & REX_W))
13927             used_prefixes |= (prefixes & PREFIX_DATA);
13928           break;
13929         case 'H':
13930           if (intel_syntax)
13931             break;
13932           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
13933               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
13934             {
13935               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
13936               *obufp++ = ',';
13937               *obufp++ = 'p';
13938               if (prefixes & PREFIX_DS)
13939                 *obufp++ = 't';
13940               else
13941                 *obufp++ = 'n';
13942             }
13943           break;
13944         case 'J':
13945           if (intel_syntax)
13946             break;
13947           *obufp++ = 'l';
13948           break;
13949         case 'K':
13950           USED_REX (REX_W);
13951           if (rex & REX_W)
13952             *obufp++ = 'q';
13953           else
13954             *obufp++ = 'd';
13955           break;
13956         case 'Z':
13957           if (l != 0 || len != 1)
13958             {
13959               if (l != 1 || len != 2 || last[0] != 'X')
13960                 {
13961                   SAVE_LAST (*p);
13962                   break;
13963                 }
13964               if (!need_vex || !vex.evex)
13965                 abort ();
13966               if (intel_syntax
13967                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
13968                 break;
13969               switch (vex.length)
13970                 {
13971                 case 128:
13972                   *obufp++ = 'x';
13973                   break;
13974                 case 256:
13975                   *obufp++ = 'y';
13976                   break;
13977                 case 512:
13978                   *obufp++ = 'z';
13979                   break;
13980                 default:
13981                   abort ();
13982                 }
13983               break;
13984             }
13985           if (intel_syntax)
13986             break;
13987           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
13988             {
13989               *obufp++ = 'q';
13990               break;
13991             }
13992           /* Fall through.  */
13993           goto case_L;
13994         case 'L':
13995           if (l != 0 || len != 1)
13996             {
13997               SAVE_LAST (*p);
13998               break;
13999             }
14000 case_L:
14001           if (intel_syntax)
14002             break;
14003           if (sizeflag & SUFFIX_ALWAYS)
14004             *obufp++ = 'l';
14005           break;
14006         case 'M':
14007           if (intel_mnemonic != cond)
14008             *obufp++ = 'r';
14009           break;
14010         case 'N':
14011           if ((prefixes & PREFIX_FWAIT) == 0)
14012             *obufp++ = 'n';
14013           else
14014             used_prefixes |= PREFIX_FWAIT;
14015           break;
14016         case 'O':
14017           USED_REX (REX_W);
14018           if (rex & REX_W)
14019             *obufp++ = 'o';
14020           else if (intel_syntax && (sizeflag & DFLAG))
14021             *obufp++ = 'q';
14022           else
14023             *obufp++ = 'd';
14024           if (!(rex & REX_W))
14025             used_prefixes |= (prefixes & PREFIX_DATA);
14026           break;
14027         case '&':
14028           if (!intel_syntax
14029               && address_mode == mode_64bit
14030               && isa64 == intel64)
14031             {
14032               *obufp++ = 'q';
14033               break;
14034             }
14035           /* Fall through.  */
14036         case 'T':
14037           if (!intel_syntax
14038               && address_mode == mode_64bit
14039               && ((sizeflag & DFLAG) || (rex & REX_W)))
14040             {
14041               *obufp++ = 'q';
14042               break;
14043             }
14044           /* Fall through.  */
14045           goto case_P;
14046         case 'P':
14047           if (l == 0 && len == 1)
14048             {
14049 case_P:
14050               if (intel_syntax)
14051                 {
14052                   if ((rex & REX_W) == 0
14053                       && (prefixes & PREFIX_DATA))
14054                     {
14055                       if ((sizeflag & DFLAG) == 0)
14056                         *obufp++ = 'w';
14057                       used_prefixes |= (prefixes & PREFIX_DATA);
14058                     }
14059                   break;
14060                 }
14061               if ((prefixes & PREFIX_DATA)
14062                   || (rex & REX_W)
14063                   || (sizeflag & SUFFIX_ALWAYS))
14064                 {
14065                   USED_REX (REX_W);
14066                   if (rex & REX_W)
14067                     *obufp++ = 'q';
14068                   else
14069                     {
14070                       if (sizeflag & DFLAG)
14071                         *obufp++ = 'l';
14072                       else
14073                         *obufp++ = 'w';
14074                       used_prefixes |= (prefixes & PREFIX_DATA);
14075                     }
14076                 }
14077             }
14078           else
14079             {
14080               if (l != 1 || len != 2 || last[0] != 'L')
14081                 {
14082                   SAVE_LAST (*p);
14083                   break;
14084                 }
14085
14086               if ((prefixes & PREFIX_DATA)
14087                   || (rex & REX_W)
14088                   || (sizeflag & SUFFIX_ALWAYS))
14089                 {
14090                   USED_REX (REX_W);
14091                   if (rex & REX_W)
14092                     *obufp++ = 'q';
14093                   else
14094                     {
14095                       if (sizeflag & DFLAG)
14096                         *obufp++ = intel_syntax ? 'd' : 'l';
14097                       else
14098                         *obufp++ = 'w';
14099                       used_prefixes |= (prefixes & PREFIX_DATA);
14100                     }
14101                 }
14102             }
14103           break;
14104         case 'U':
14105           if (intel_syntax)
14106             break;
14107           if (address_mode == mode_64bit
14108               && ((sizeflag & DFLAG) || (rex & REX_W)))
14109             {
14110               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
14111                 *obufp++ = 'q';
14112               break;
14113             }
14114           /* Fall through.  */
14115           goto case_Q;
14116         case 'Q':
14117           if (l == 0 && len == 1)
14118             {
14119 case_Q:
14120               if (intel_syntax && !alt)
14121                 break;
14122               USED_REX (REX_W);
14123               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
14124                 {
14125                   if (rex & REX_W)
14126                     *obufp++ = 'q';
14127                   else
14128                     {
14129                       if (sizeflag & DFLAG)
14130                         *obufp++ = intel_syntax ? 'd' : 'l';
14131                       else
14132                         *obufp++ = 'w';
14133                       used_prefixes |= (prefixes & PREFIX_DATA);
14134                     }
14135                 }
14136             }
14137           else
14138             {
14139               if (l != 1 || len != 2 || last[0] != 'L')
14140                 {
14141                   SAVE_LAST (*p);
14142                   break;
14143                 }
14144               if (intel_syntax
14145                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
14146                 break;
14147               if ((rex & REX_W))
14148                 {
14149                   USED_REX (REX_W);
14150                   *obufp++ = 'q';
14151                 }
14152               else
14153                 *obufp++ = 'l';
14154             }
14155           break;
14156         case 'R':
14157           USED_REX (REX_W);
14158           if (rex & REX_W)
14159             *obufp++ = 'q';
14160           else if (sizeflag & DFLAG)
14161             {
14162               if (intel_syntax)
14163                   *obufp++ = 'd';
14164               else
14165                   *obufp++ = 'l';
14166             }
14167           else
14168             *obufp++ = 'w';
14169           if (intel_syntax && !p[1]
14170               && ((rex & REX_W) || (sizeflag & DFLAG)))
14171             *obufp++ = 'e';
14172           if (!(rex & REX_W))
14173             used_prefixes |= (prefixes & PREFIX_DATA);
14174           break;
14175         case 'V':
14176           if (l == 0 && len == 1)
14177             {
14178               if (intel_syntax)
14179                 break;
14180               if (address_mode == mode_64bit
14181                   && ((sizeflag & DFLAG) || (rex & REX_W)))
14182                 {
14183                   if (sizeflag & SUFFIX_ALWAYS)
14184                     *obufp++ = 'q';
14185                   break;
14186                 }
14187             }
14188           else
14189             {
14190               if (l != 1
14191                   || len != 2
14192                   || last[0] != 'L')
14193                 {
14194                   SAVE_LAST (*p);
14195                   break;
14196                 }
14197
14198               if (rex & REX_W)
14199                 {
14200                   *obufp++ = 'a';
14201                   *obufp++ = 'b';
14202                   *obufp++ = 's';
14203                 }
14204             }
14205           /* Fall through.  */
14206           goto case_S;
14207         case 'S':
14208           if (l == 0 && len == 1)
14209             {
14210 case_S:
14211               if (intel_syntax)
14212                 break;
14213               if (sizeflag & SUFFIX_ALWAYS)
14214                 {
14215                   if (rex & REX_W)
14216                     *obufp++ = 'q';
14217                   else
14218                     {
14219                       if (sizeflag & DFLAG)
14220                         *obufp++ = 'l';
14221                       else
14222                         *obufp++ = 'w';
14223                       used_prefixes |= (prefixes & PREFIX_DATA);
14224                     }
14225                 }
14226             }
14227           else
14228             {
14229               if (l != 1
14230                   || len != 2
14231                   || last[0] != 'L')
14232                 {
14233                   SAVE_LAST (*p);
14234                   break;
14235                 }
14236
14237               if (address_mode == mode_64bit
14238                   && !(prefixes & PREFIX_ADDR))
14239                 {
14240                   *obufp++ = 'a';
14241                   *obufp++ = 'b';
14242                   *obufp++ = 's';
14243                 }
14244
14245               goto case_S;
14246             }
14247           break;
14248         case 'X':
14249           if (l != 0 || len != 1)
14250             {
14251               SAVE_LAST (*p);
14252               break;
14253             }
14254           if (need_vex && vex.prefix)
14255             {
14256               if (vex.prefix == DATA_PREFIX_OPCODE)
14257                 *obufp++ = 'd';
14258               else
14259                 *obufp++ = 's';
14260             }
14261           else
14262             {
14263               if (prefixes & PREFIX_DATA)
14264                 *obufp++ = 'd';
14265               else
14266                 *obufp++ = 's';
14267               used_prefixes |= (prefixes & PREFIX_DATA);
14268             }
14269           break;
14270         case 'Y':
14271           if (l == 0 && len == 1)
14272             {
14273               if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
14274                 break;
14275               if (rex & REX_W)
14276                 {
14277                   USED_REX (REX_W);
14278                   *obufp++ = 'q';
14279                 }
14280               break;
14281             }
14282           else
14283             {
14284               if (l != 1 || len != 2 || last[0] != 'X')
14285                 {
14286                   SAVE_LAST (*p);
14287                   break;
14288                 }
14289               if (!need_vex)
14290                 abort ();
14291               if (intel_syntax
14292                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
14293                 break;
14294               switch (vex.length)
14295                 {
14296                 case 128:
14297                   *obufp++ = 'x';
14298                   break;
14299                 case 256:
14300                   *obufp++ = 'y';
14301                   break;
14302                 case 512:
14303                   if (!vex.evex)
14304                 default:
14305                     abort ();
14306                 }
14307             }
14308           break;
14309         case 'W':
14310           if (l == 0 && len == 1)
14311             {
14312               /* operand size flag for cwtl, cbtw */
14313               USED_REX (REX_W);
14314               if (rex & REX_W)
14315                 {
14316                   if (intel_syntax)
14317                     *obufp++ = 'd';
14318                   else
14319                     *obufp++ = 'l';
14320                 }
14321               else if (sizeflag & DFLAG)
14322                 *obufp++ = 'w';
14323               else
14324                 *obufp++ = 'b';
14325               if (!(rex & REX_W))
14326                 used_prefixes |= (prefixes & PREFIX_DATA);
14327             }
14328           else
14329             {
14330               if (l != 1
14331                   || len != 2
14332                   || (last[0] != 'X'
14333                       && last[0] != 'L'))
14334                 {
14335                   SAVE_LAST (*p);
14336                   break;
14337                 }
14338               if (!need_vex)
14339                 abort ();
14340               if (last[0] == 'X')
14341                 *obufp++ = vex.w ? 'd': 's';
14342               else
14343                 *obufp++ = vex.w ? 'q': 'd';
14344             }
14345           break;
14346         case '^':
14347           if (intel_syntax)
14348             break;
14349           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
14350             {
14351               if (sizeflag & DFLAG)
14352                 *obufp++ = 'l';
14353               else
14354                 *obufp++ = 'w';
14355               used_prefixes |= (prefixes & PREFIX_DATA);
14356             }
14357           break;
14358         case '@':
14359           if (intel_syntax)
14360             break;
14361           if (address_mode == mode_64bit
14362               && (isa64 == intel64
14363                   || ((sizeflag & DFLAG) || (rex & REX_W))))
14364               *obufp++ = 'q';
14365           else if ((prefixes & PREFIX_DATA))
14366             {
14367               if (!(sizeflag & DFLAG))
14368                 *obufp++ = 'w';
14369               used_prefixes |= (prefixes & PREFIX_DATA);
14370             }
14371           break;
14372         }
14373       alt = 0;
14374     }
14375   *obufp = 0;
14376   mnemonicendp = obufp;
14377   return 0;
14378 }
14379
14380 static void
14381 oappend (const char *s)
14382 {
14383   obufp = stpcpy (obufp, s);
14384 }
14385
14386 static void
14387 append_seg (void)
14388 {
14389   /* Only print the active segment register.  */
14390   if (!active_seg_prefix)
14391     return;
14392
14393   used_prefixes |= active_seg_prefix;
14394   switch (active_seg_prefix)
14395     {
14396     case PREFIX_CS:
14397       oappend_maybe_intel ("%cs:");
14398       break;
14399     case PREFIX_DS:
14400       oappend_maybe_intel ("%ds:");
14401       break;
14402     case PREFIX_SS:
14403       oappend_maybe_intel ("%ss:");
14404       break;
14405     case PREFIX_ES:
14406       oappend_maybe_intel ("%es:");
14407       break;
14408     case PREFIX_FS:
14409       oappend_maybe_intel ("%fs:");
14410       break;
14411     case PREFIX_GS:
14412       oappend_maybe_intel ("%gs:");
14413       break;
14414     default:
14415       break;
14416     }
14417 }
14418
14419 static void
14420 OP_indirE (int bytemode, int sizeflag)
14421 {
14422   if (!intel_syntax)
14423     oappend ("*");
14424   OP_E (bytemode, sizeflag);
14425 }
14426
14427 static void
14428 print_operand_value (char *buf, int hex, bfd_vma disp)
14429 {
14430   if (address_mode == mode_64bit)
14431     {
14432       if (hex)
14433         {
14434           char tmp[30];
14435           int i;
14436           buf[0] = '0';
14437           buf[1] = 'x';
14438           sprintf_vma (tmp, disp);
14439           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
14440           strcpy (buf + 2, tmp + i);
14441         }
14442       else
14443         {
14444           bfd_signed_vma v = disp;
14445           char tmp[30];
14446           int i;
14447           if (v < 0)
14448             {
14449               *(buf++) = '-';
14450               v = -disp;
14451               /* Check for possible overflow on 0x8000000000000000.  */
14452               if (v < 0)
14453                 {
14454                   strcpy (buf, "9223372036854775808");
14455                   return;
14456                 }
14457             }
14458           if (!v)
14459             {
14460               strcpy (buf, "0");
14461               return;
14462             }
14463
14464           i = 0;
14465           tmp[29] = 0;
14466           while (v)
14467             {
14468               tmp[28 - i] = (v % 10) + '0';
14469               v /= 10;
14470               i++;
14471             }
14472           strcpy (buf, tmp + 29 - i);
14473         }
14474     }
14475   else
14476     {
14477       if (hex)
14478         sprintf (buf, "0x%x", (unsigned int) disp);
14479       else
14480         sprintf (buf, "%d", (int) disp);
14481     }
14482 }
14483
14484 /* Put DISP in BUF as signed hex number.  */
14485
14486 static void
14487 print_displacement (char *buf, bfd_vma disp)
14488 {
14489   bfd_signed_vma val = disp;
14490   char tmp[30];
14491   int i, j = 0;
14492
14493   if (val < 0)
14494     {
14495       buf[j++] = '-';
14496       val = -disp;
14497
14498       /* Check for possible overflow.  */
14499       if (val < 0)
14500         {
14501           switch (address_mode)
14502             {
14503             case mode_64bit:
14504               strcpy (buf + j, "0x8000000000000000");
14505               break;
14506             case mode_32bit:
14507               strcpy (buf + j, "0x80000000");
14508               break;
14509             case mode_16bit:
14510               strcpy (buf + j, "0x8000");
14511               break;
14512             }
14513           return;
14514         }
14515     }
14516
14517   buf[j++] = '0';
14518   buf[j++] = 'x';
14519
14520   sprintf_vma (tmp, (bfd_vma) val);
14521   for (i = 0; tmp[i] == '0'; i++)
14522     continue;
14523   if (tmp[i] == '\0')
14524     i--;
14525   strcpy (buf + j, tmp + i);
14526 }
14527
14528 static void
14529 intel_operand_size (int bytemode, int sizeflag)
14530 {
14531   if (vex.evex
14532       && vex.b
14533       && (bytemode == x_mode
14534           || bytemode == evex_half_bcst_xmmq_mode))
14535     {
14536       if (vex.w)
14537         oappend ("QWORD PTR ");
14538       else
14539         oappend ("DWORD PTR ");
14540       return;
14541     }
14542   switch (bytemode)
14543     {
14544     case b_mode:
14545     case b_swap_mode:
14546     case dqb_mode:
14547     case db_mode:
14548       oappend ("BYTE PTR ");
14549       break;
14550     case w_mode:
14551     case dw_mode:
14552     case dqw_mode:
14553       oappend ("WORD PTR ");
14554       break;
14555     case indir_v_mode:
14556       if (address_mode == mode_64bit && isa64 == intel64)
14557         {
14558           oappend ("QWORD PTR ");
14559           break;
14560         }
14561       /* Fall through.  */
14562     case stack_v_mode:
14563       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14564         {
14565           oappend ("QWORD PTR ");
14566           break;
14567         }
14568       /* Fall through.  */
14569     case v_mode:
14570     case v_swap_mode:
14571     case dq_mode:
14572       USED_REX (REX_W);
14573       if (rex & REX_W)
14574         oappend ("QWORD PTR ");
14575       else
14576         {
14577           if ((sizeflag & DFLAG) || bytemode == dq_mode)
14578             oappend ("DWORD PTR ");
14579           else
14580             oappend ("WORD PTR ");
14581           used_prefixes |= (prefixes & PREFIX_DATA);
14582         }
14583       break;
14584     case z_mode:
14585       if ((rex & REX_W) || (sizeflag & DFLAG))
14586         *obufp++ = 'D';
14587       oappend ("WORD PTR ");
14588       if (!(rex & REX_W))
14589         used_prefixes |= (prefixes & PREFIX_DATA);
14590       break;
14591     case a_mode:
14592       if (sizeflag & DFLAG)
14593         oappend ("QWORD PTR ");
14594       else
14595         oappend ("DWORD PTR ");
14596       used_prefixes |= (prefixes & PREFIX_DATA);
14597       break;
14598     case d_mode:
14599     case d_scalar_mode:
14600     case d_scalar_swap_mode:
14601     case d_swap_mode:
14602     case dqd_mode:
14603       oappend ("DWORD PTR ");
14604       break;
14605     case q_mode:
14606     case q_scalar_mode:
14607     case q_scalar_swap_mode:
14608     case q_swap_mode:
14609       oappend ("QWORD PTR ");
14610       break;
14611     case m_mode:
14612       if (address_mode == mode_64bit)
14613         oappend ("QWORD PTR ");
14614       else
14615         oappend ("DWORD PTR ");
14616       break;
14617     case f_mode:
14618       if (sizeflag & DFLAG)
14619         oappend ("FWORD PTR ");
14620       else
14621         oappend ("DWORD PTR ");
14622       used_prefixes |= (prefixes & PREFIX_DATA);
14623       break;
14624     case t_mode:
14625       oappend ("TBYTE PTR ");
14626       break;
14627     case x_mode:
14628     case x_swap_mode:
14629     case evex_x_gscat_mode:
14630     case evex_x_nobcst_mode:
14631       if (need_vex)
14632         {
14633           switch (vex.length)
14634             {
14635             case 128:
14636               oappend ("XMMWORD PTR ");
14637               break;
14638             case 256:
14639               oappend ("YMMWORD PTR ");
14640               break;
14641             case 512:
14642               oappend ("ZMMWORD PTR ");
14643               break;
14644             default:
14645               abort ();
14646             }
14647         }
14648       else
14649         oappend ("XMMWORD PTR ");
14650       break;
14651     case xmm_mode:
14652       oappend ("XMMWORD PTR ");
14653       break;
14654     case ymm_mode:
14655       oappend ("YMMWORD PTR ");
14656       break;
14657     case xmmq_mode:
14658     case evex_half_bcst_xmmq_mode:
14659       if (!need_vex)
14660         abort ();
14661
14662       switch (vex.length)
14663         {
14664         case 128:
14665           oappend ("QWORD PTR ");
14666           break;
14667         case 256:
14668           oappend ("XMMWORD PTR ");
14669           break;
14670         case 512:
14671           oappend ("YMMWORD PTR ");
14672           break;
14673         default:
14674           abort ();
14675         }
14676       break;
14677     case xmm_mb_mode:
14678       if (!need_vex)
14679         abort ();
14680
14681       switch (vex.length)
14682         {
14683         case 128:
14684         case 256:
14685         case 512:
14686           oappend ("BYTE PTR ");
14687           break;
14688         default:
14689           abort ();
14690         }
14691       break;
14692     case xmm_mw_mode:
14693       if (!need_vex)
14694         abort ();
14695
14696       switch (vex.length)
14697         {
14698         case 128:
14699         case 256:
14700         case 512:
14701           oappend ("WORD PTR ");
14702           break;
14703         default:
14704           abort ();
14705         }
14706       break;
14707     case xmm_md_mode:
14708       if (!need_vex)
14709         abort ();
14710
14711       switch (vex.length)
14712         {
14713         case 128:
14714         case 256:
14715         case 512:
14716           oappend ("DWORD PTR ");
14717           break;
14718         default:
14719           abort ();
14720         }
14721       break;
14722     case xmm_mq_mode:
14723       if (!need_vex)
14724         abort ();
14725
14726       switch (vex.length)
14727         {
14728         case 128:
14729         case 256:
14730         case 512:
14731           oappend ("QWORD PTR ");
14732           break;
14733         default:
14734           abort ();
14735         }
14736       break;
14737     case xmmdw_mode:
14738       if (!need_vex)
14739         abort ();
14740
14741       switch (vex.length)
14742         {
14743         case 128:
14744           oappend ("WORD PTR ");
14745           break;
14746         case 256:
14747           oappend ("DWORD PTR ");
14748           break;
14749         case 512:
14750           oappend ("QWORD PTR ");
14751           break;
14752         default:
14753           abort ();
14754         }
14755       break;
14756     case xmmqd_mode:
14757       if (!need_vex)
14758         abort ();
14759
14760       switch (vex.length)
14761         {
14762         case 128:
14763           oappend ("DWORD PTR ");
14764           break;
14765         case 256:
14766           oappend ("QWORD PTR ");
14767           break;
14768         case 512:
14769           oappend ("XMMWORD PTR ");
14770           break;
14771         default:
14772           abort ();
14773         }
14774       break;
14775     case ymmq_mode:
14776       if (!need_vex)
14777         abort ();
14778
14779       switch (vex.length)
14780         {
14781         case 128:
14782           oappend ("QWORD PTR ");
14783           break;
14784         case 256:
14785           oappend ("YMMWORD PTR ");
14786           break;
14787         case 512:
14788           oappend ("ZMMWORD PTR ");
14789           break;
14790         default:
14791           abort ();
14792         }
14793       break;
14794     case ymmxmm_mode:
14795       if (!need_vex)
14796         abort ();
14797
14798       switch (vex.length)
14799         {
14800         case 128:
14801         case 256:
14802           oappend ("XMMWORD PTR ");
14803           break;
14804         default:
14805           abort ();
14806         }
14807       break;
14808     case o_mode:
14809       oappend ("OWORD PTR ");
14810       break;
14811     case xmm_mdq_mode:
14812     case vex_w_dq_mode:
14813     case vex_scalar_w_dq_mode:
14814       if (!need_vex)
14815         abort ();
14816
14817       if (vex.w)
14818         oappend ("QWORD PTR ");
14819       else
14820         oappend ("DWORD PTR ");
14821       break;
14822     case vex_vsib_d_w_dq_mode:
14823     case vex_vsib_q_w_dq_mode:
14824       if (!need_vex)
14825         abort ();
14826
14827       if (!vex.evex)
14828         {
14829           if (vex.w)
14830             oappend ("QWORD PTR ");
14831           else
14832             oappend ("DWORD PTR ");
14833         }
14834       else
14835         {
14836           switch (vex.length)
14837             {
14838             case 128:
14839               oappend ("XMMWORD PTR ");
14840               break;
14841             case 256:
14842               oappend ("YMMWORD PTR ");
14843               break;
14844             case 512:
14845               oappend ("ZMMWORD PTR ");
14846               break;
14847             default:
14848               abort ();
14849             }
14850         }
14851       break;
14852     case vex_vsib_q_w_d_mode:
14853     case vex_vsib_d_w_d_mode:
14854       if (!need_vex || !vex.evex)
14855         abort ();
14856
14857       switch (vex.length)
14858         {
14859         case 128:
14860           oappend ("QWORD PTR ");
14861           break;
14862         case 256:
14863           oappend ("XMMWORD PTR ");
14864           break;
14865         case 512:
14866           oappend ("YMMWORD PTR ");
14867           break;
14868         default:
14869           abort ();
14870         }
14871
14872       break;
14873     case mask_bd_mode:
14874       if (!need_vex || vex.length != 128)
14875         abort ();
14876       if (vex.w)
14877         oappend ("DWORD PTR ");
14878       else
14879         oappend ("BYTE PTR ");
14880       break;
14881     case mask_mode:
14882       if (!need_vex)
14883         abort ();
14884       if (vex.w)
14885         oappend ("QWORD PTR ");
14886       else
14887         oappend ("WORD PTR ");
14888       break;
14889     case v_bnd_mode:
14890     default:
14891       break;
14892     }
14893 }
14894
14895 static void
14896 OP_E_register (int bytemode, int sizeflag)
14897 {
14898   int reg = modrm.rm;
14899   const char **names;
14900
14901   USED_REX (REX_B);
14902   if ((rex & REX_B))
14903     reg += 8;
14904
14905   if ((sizeflag & SUFFIX_ALWAYS)
14906       && (bytemode == b_swap_mode
14907           || bytemode == v_swap_mode))
14908     swap_operand ();
14909
14910   switch (bytemode)
14911     {
14912     case b_mode:
14913     case b_swap_mode:
14914       USED_REX (0);
14915       if (rex)
14916         names = names8rex;
14917       else
14918         names = names8;
14919       break;
14920     case w_mode:
14921       names = names16;
14922       break;
14923     case d_mode:
14924     case dw_mode:
14925     case db_mode:
14926       names = names32;
14927       break;
14928     case q_mode:
14929       names = names64;
14930       break;
14931     case m_mode:
14932     case v_bnd_mode:
14933       names = address_mode == mode_64bit ? names64 : names32;
14934       break;
14935     case bnd_mode:
14936       names = names_bnd;
14937       break;
14938     case indir_v_mode:
14939       if (address_mode == mode_64bit && isa64 == intel64)
14940         {
14941           names = names64;
14942           break;
14943         }
14944       /* Fall through.  */
14945     case stack_v_mode:
14946       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14947         {
14948           names = names64;
14949           break;
14950         }
14951       bytemode = v_mode;
14952       /* Fall through.  */
14953     case v_mode:
14954     case v_swap_mode:
14955     case dq_mode:
14956     case dqb_mode:
14957     case dqd_mode:
14958     case dqw_mode:
14959       USED_REX (REX_W);
14960       if (rex & REX_W)
14961         names = names64;
14962       else
14963         {
14964           if ((sizeflag & DFLAG)
14965               || (bytemode != v_mode
14966                   && bytemode != v_swap_mode))
14967             names = names32;
14968           else
14969             names = names16;
14970           used_prefixes |= (prefixes & PREFIX_DATA);
14971         }
14972       break;
14973     case mask_bd_mode:
14974     case mask_mode:
14975       if (reg > 0x7)
14976         {
14977           oappend ("(bad)");
14978           return;
14979         }
14980       names = names_mask;
14981       break;
14982     case 0:
14983       return;
14984     default:
14985       oappend (INTERNAL_DISASSEMBLER_ERROR);
14986       return;
14987     }
14988   oappend (names[reg]);
14989 }
14990
14991 static void
14992 OP_E_memory (int bytemode, int sizeflag)
14993 {
14994   bfd_vma disp = 0;
14995   int add = (rex & REX_B) ? 8 : 0;
14996   int riprel = 0;
14997   int shift;
14998
14999   if (vex.evex)
15000     {
15001       /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0.  */
15002       if (vex.b
15003           && bytemode != x_mode
15004           && bytemode != xmmq_mode
15005           && bytemode != evex_half_bcst_xmmq_mode)
15006         {
15007           BadOp ();
15008           return;
15009         }
15010       switch (bytemode)
15011         {
15012         case dqw_mode:
15013         case dw_mode:
15014           shift = 1;
15015           break;
15016         case dqb_mode:
15017         case db_mode:
15018           shift = 0;
15019           break;
15020         case vex_vsib_d_w_dq_mode:
15021         case vex_vsib_d_w_d_mode:
15022         case vex_vsib_q_w_dq_mode:
15023         case vex_vsib_q_w_d_mode:
15024         case evex_x_gscat_mode:
15025         case xmm_mdq_mode:
15026           shift = vex.w ? 3 : 2;
15027           break;
15028         case x_mode:
15029         case evex_half_bcst_xmmq_mode:
15030         case xmmq_mode:
15031           if (vex.b)
15032             {
15033               shift = vex.w ? 3 : 2;
15034               break;
15035             }
15036           /* Fall through.  */
15037         case xmmqd_mode:
15038         case xmmdw_mode:
15039         case ymmq_mode:
15040         case evex_x_nobcst_mode:
15041         case x_swap_mode:
15042           switch (vex.length)
15043             {
15044             case 128:
15045               shift = 4;
15046               break;
15047             case 256:
15048               shift = 5;
15049               break;
15050             case 512:
15051               shift = 6;
15052               break;
15053             default:
15054               abort ();
15055             }
15056           break;
15057         case ymm_mode:
15058           shift = 5;
15059           break;
15060         case xmm_mode:
15061           shift = 4;
15062           break;
15063         case xmm_mq_mode:
15064         case q_mode:
15065         case q_scalar_mode:
15066         case q_swap_mode:
15067         case q_scalar_swap_mode:
15068           shift = 3;
15069           break;
15070         case dqd_mode:
15071         case xmm_md_mode:
15072         case d_mode:
15073         case d_scalar_mode:
15074         case d_swap_mode:
15075         case d_scalar_swap_mode:
15076           shift = 2;
15077           break;
15078         case xmm_mw_mode:
15079           shift = 1;
15080           break;
15081         case xmm_mb_mode:
15082           shift = 0;
15083           break;
15084         default:
15085           abort ();
15086         }
15087       /* Make necessary corrections to shift for modes that need it.
15088          For these modes we currently have shift 4, 5 or 6 depending on
15089          vex.length (it corresponds to xmmword, ymmword or zmmword
15090          operand).  We might want to make it 3, 4 or 5 (e.g. for
15091          xmmq_mode).  In case of broadcast enabled the corrections
15092          aren't needed, as element size is always 32 or 64 bits.  */
15093       if (!vex.b
15094           && (bytemode == xmmq_mode
15095               || bytemode == evex_half_bcst_xmmq_mode))
15096         shift -= 1;
15097       else if (bytemode == xmmqd_mode)
15098         shift -= 2;
15099       else if (bytemode == xmmdw_mode)
15100         shift -= 3;
15101       else if (bytemode == ymmq_mode && vex.length == 128)
15102         shift -= 1;
15103     }
15104   else
15105     shift = 0;
15106
15107   USED_REX (REX_B);
15108   if (intel_syntax)
15109     intel_operand_size (bytemode, sizeflag);
15110   append_seg ();
15111
15112   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
15113     {
15114       /* 32/64 bit address mode */
15115       int havedisp;
15116       int havesib;
15117       int havebase;
15118       int haveindex;
15119       int needindex;
15120       int base, rbase;
15121       int vindex = 0;
15122       int scale = 0;
15123       int addr32flag = !((sizeflag & AFLAG)
15124                          || bytemode == v_bnd_mode
15125                          || bytemode == bnd_mode);
15126       const char **indexes64 = names64;
15127       const char **indexes32 = names32;
15128
15129       havesib = 0;
15130       havebase = 1;
15131       haveindex = 0;
15132       base = modrm.rm;
15133
15134       if (base == 4)
15135         {
15136           havesib = 1;
15137           vindex = sib.index;
15138           USED_REX (REX_X);
15139           if (rex & REX_X)
15140             vindex += 8;
15141           switch (bytemode)
15142             {
15143             case vex_vsib_d_w_dq_mode:
15144             case vex_vsib_d_w_d_mode:
15145             case vex_vsib_q_w_dq_mode:
15146             case vex_vsib_q_w_d_mode:
15147               if (!need_vex)
15148                 abort ();
15149               if (vex.evex)
15150                 {
15151                   if (!vex.v)
15152                     vindex += 16;
15153                 }
15154
15155               haveindex = 1;
15156               switch (vex.length)
15157                 {
15158                 case 128:
15159                   indexes64 = indexes32 = names_xmm;
15160                   break;
15161                 case 256:
15162                   if (!vex.w
15163                       || bytemode == vex_vsib_q_w_dq_mode
15164                       || bytemode == vex_vsib_q_w_d_mode)
15165                     indexes64 = indexes32 = names_ymm;
15166                   else
15167                     indexes64 = indexes32 = names_xmm;
15168                   break;
15169                 case 512:
15170                   if (!vex.w
15171                       || bytemode == vex_vsib_q_w_dq_mode
15172                       || bytemode == vex_vsib_q_w_d_mode)
15173                     indexes64 = indexes32 = names_zmm;
15174                   else
15175                     indexes64 = indexes32 = names_ymm;
15176                   break;
15177                 default:
15178                   abort ();
15179                 }
15180               break;
15181             default:
15182               haveindex = vindex != 4;
15183               break;
15184             }
15185           scale = sib.scale;
15186           base = sib.base;
15187           codep++;
15188         }
15189       rbase = base + add;
15190
15191       switch (modrm.mod)
15192         {
15193         case 0:
15194           if (base == 5)
15195             {
15196               havebase = 0;
15197               if (address_mode == mode_64bit && !havesib)
15198                 riprel = 1;
15199               disp = get32s ();
15200             }
15201           break;
15202         case 1:
15203           FETCH_DATA (the_info, codep + 1);
15204           disp = *codep++;
15205           if ((disp & 0x80) != 0)
15206             disp -= 0x100;
15207           if (vex.evex && shift > 0)
15208             disp <<= shift;
15209           break;
15210         case 2:
15211           disp = get32s ();
15212           break;
15213         }
15214
15215       /* In 32bit mode, we need index register to tell [offset] from
15216          [eiz*1 + offset].  */
15217       needindex = (havesib
15218                    && !havebase
15219                    && !haveindex
15220                    && address_mode == mode_32bit);
15221       havedisp = (havebase
15222                   || needindex
15223                   || (havesib && (haveindex || scale != 0)));
15224
15225       if (!intel_syntax)
15226         if (modrm.mod != 0 || base == 5)
15227           {
15228             if (havedisp || riprel)
15229               print_displacement (scratchbuf, disp);
15230             else
15231               print_operand_value (scratchbuf, 1, disp);
15232             oappend (scratchbuf);
15233             if (riprel)
15234               {
15235                 set_op (disp, 1);
15236                 oappend (!addr32flag ? "(%rip)" : "(%eip)");
15237               }
15238           }
15239
15240       if ((havebase || haveindex || riprel)
15241           && (bytemode != v_bnd_mode)
15242           && (bytemode != bnd_mode))
15243         used_prefixes |= PREFIX_ADDR;
15244
15245       if (havedisp || (intel_syntax && riprel))
15246         {
15247           *obufp++ = open_char;
15248           if (intel_syntax && riprel)
15249             {
15250               set_op (disp, 1);
15251               oappend (!addr32flag ? "rip" : "eip");
15252             }
15253           *obufp = '\0';
15254           if (havebase)
15255             oappend (address_mode == mode_64bit && !addr32flag
15256                      ? names64[rbase] : names32[rbase]);
15257           if (havesib)
15258             {
15259               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
15260                  print index to tell base + index from base.  */
15261               if (scale != 0
15262                   || needindex
15263                   || haveindex
15264                   || (havebase && base != ESP_REG_NUM))
15265                 {
15266                   if (!intel_syntax || havebase)
15267                     {
15268                       *obufp++ = separator_char;
15269                       *obufp = '\0';
15270                     }
15271                   if (haveindex)
15272                     oappend (address_mode == mode_64bit && !addr32flag
15273                              ? indexes64[vindex] : indexes32[vindex]);
15274                   else
15275                     oappend (address_mode == mode_64bit && !addr32flag
15276                              ? index64 : index32);
15277
15278                   *obufp++ = scale_char;
15279                   *obufp = '\0';
15280                   sprintf (scratchbuf, "%d", 1 << scale);
15281                   oappend (scratchbuf);
15282                 }
15283             }
15284           if (intel_syntax
15285               && (disp || modrm.mod != 0 || base == 5))
15286             {
15287               if (!havedisp || (bfd_signed_vma) disp >= 0)
15288                 {
15289                   *obufp++ = '+';
15290                   *obufp = '\0';
15291                 }
15292               else if (modrm.mod != 1 && disp != -disp)
15293                 {
15294                   *obufp++ = '-';
15295                   *obufp = '\0';
15296                   disp = - (bfd_signed_vma) disp;
15297                 }
15298
15299               if (havedisp)
15300                 print_displacement (scratchbuf, disp);
15301               else
15302                 print_operand_value (scratchbuf, 1, disp);
15303               oappend (scratchbuf);
15304             }
15305
15306           *obufp++ = close_char;
15307           *obufp = '\0';
15308         }
15309       else if (intel_syntax)
15310         {
15311           if (modrm.mod != 0 || base == 5)
15312             {
15313               if (!active_seg_prefix)
15314                 {
15315                   oappend (names_seg[ds_reg - es_reg]);
15316                   oappend (":");
15317                 }
15318               print_operand_value (scratchbuf, 1, disp);
15319               oappend (scratchbuf);
15320             }
15321         }
15322     }
15323   else
15324     {
15325       /* 16 bit address mode */
15326       used_prefixes |= prefixes & PREFIX_ADDR;
15327       switch (modrm.mod)
15328         {
15329         case 0:
15330           if (modrm.rm == 6)
15331             {
15332               disp = get16 ();
15333               if ((disp & 0x8000) != 0)
15334                 disp -= 0x10000;
15335             }
15336           break;
15337         case 1:
15338           FETCH_DATA (the_info, codep + 1);
15339           disp = *codep++;
15340           if ((disp & 0x80) != 0)
15341             disp -= 0x100;
15342           break;
15343         case 2:
15344           disp = get16 ();
15345           if ((disp & 0x8000) != 0)
15346             disp -= 0x10000;
15347           break;
15348         }
15349
15350       if (!intel_syntax)
15351         if (modrm.mod != 0 || modrm.rm == 6)
15352           {
15353             print_displacement (scratchbuf, disp);
15354             oappend (scratchbuf);
15355           }
15356
15357       if (modrm.mod != 0 || modrm.rm != 6)
15358         {
15359           *obufp++ = open_char;
15360           *obufp = '\0';
15361           oappend (index16[modrm.rm]);
15362           if (intel_syntax
15363               && (disp || modrm.mod != 0 || modrm.rm == 6))
15364             {
15365               if ((bfd_signed_vma) disp >= 0)
15366                 {
15367                   *obufp++ = '+';
15368                   *obufp = '\0';
15369                 }
15370               else if (modrm.mod != 1)
15371                 {
15372                   *obufp++ = '-';
15373                   *obufp = '\0';
15374                   disp = - (bfd_signed_vma) disp;
15375                 }
15376
15377               print_displacement (scratchbuf, disp);
15378               oappend (scratchbuf);
15379             }
15380
15381           *obufp++ = close_char;
15382           *obufp = '\0';
15383         }
15384       else if (intel_syntax)
15385         {
15386           if (!active_seg_prefix)
15387             {
15388               oappend (names_seg[ds_reg - es_reg]);
15389               oappend (":");
15390             }
15391           print_operand_value (scratchbuf, 1, disp & 0xffff);
15392           oappend (scratchbuf);
15393         }
15394     }
15395   if (vex.evex && vex.b
15396       && (bytemode == x_mode
15397           || bytemode == xmmq_mode
15398           || bytemode == evex_half_bcst_xmmq_mode))
15399     {
15400       if (vex.w
15401           || bytemode == xmmq_mode
15402           || bytemode == evex_half_bcst_xmmq_mode)
15403         {
15404           switch (vex.length)
15405             {
15406             case 128:
15407               oappend ("{1to2}");
15408               break;
15409             case 256:
15410               oappend ("{1to4}");
15411               break;
15412             case 512:
15413               oappend ("{1to8}");
15414               break;
15415             default:
15416               abort ();
15417             }
15418         }
15419       else
15420         {
15421           switch (vex.length)
15422             {
15423             case 128:
15424               oappend ("{1to4}");
15425               break;
15426             case 256:
15427               oappend ("{1to8}");
15428               break;
15429             case 512:
15430               oappend ("{1to16}");
15431               break;
15432             default:
15433               abort ();
15434             }
15435         }
15436     }
15437 }
15438
15439 static void
15440 OP_E (int bytemode, int sizeflag)
15441 {
15442   /* Skip mod/rm byte.  */
15443   MODRM_CHECK;
15444   codep++;
15445
15446   if (modrm.mod == 3)
15447     OP_E_register (bytemode, sizeflag);
15448   else
15449     OP_E_memory (bytemode, sizeflag);
15450 }
15451
15452 static void
15453 OP_G (int bytemode, int sizeflag)
15454 {
15455   int add = 0;
15456   USED_REX (REX_R);
15457   if (rex & REX_R)
15458     add += 8;
15459   switch (bytemode)
15460     {
15461     case b_mode:
15462       USED_REX (0);
15463       if (rex)
15464         oappend (names8rex[modrm.reg + add]);
15465       else
15466         oappend (names8[modrm.reg + add]);
15467       break;
15468     case w_mode:
15469       oappend (names16[modrm.reg + add]);
15470       break;
15471     case d_mode:
15472     case db_mode:
15473     case dw_mode:
15474       oappend (names32[modrm.reg + add]);
15475       break;
15476     case q_mode:
15477       oappend (names64[modrm.reg + add]);
15478       break;
15479     case bnd_mode:
15480       oappend (names_bnd[modrm.reg]);
15481       break;
15482     case v_mode:
15483     case dq_mode:
15484     case dqb_mode:
15485     case dqd_mode:
15486     case dqw_mode:
15487       USED_REX (REX_W);
15488       if (rex & REX_W)
15489         oappend (names64[modrm.reg + add]);
15490       else
15491         {
15492           if ((sizeflag & DFLAG) || bytemode != v_mode)
15493             oappend (names32[modrm.reg + add]);
15494           else
15495             oappend (names16[modrm.reg + add]);
15496           used_prefixes |= (prefixes & PREFIX_DATA);
15497         }
15498       break;
15499     case m_mode:
15500       if (address_mode == mode_64bit)
15501         oappend (names64[modrm.reg + add]);
15502       else
15503         oappend (names32[modrm.reg + add]);
15504       break;
15505     case mask_bd_mode:
15506     case mask_mode:
15507       if ((modrm.reg + add) > 0x7)
15508         {
15509           oappend ("(bad)");
15510           return;
15511         }
15512       oappend (names_mask[modrm.reg + add]);
15513       break;
15514     default:
15515       oappend (INTERNAL_DISASSEMBLER_ERROR);
15516       break;
15517     }
15518 }
15519
15520 static bfd_vma
15521 get64 (void)
15522 {
15523   bfd_vma x;
15524 #ifdef BFD64
15525   unsigned int a;
15526   unsigned int b;
15527
15528   FETCH_DATA (the_info, codep + 8);
15529   a = *codep++ & 0xff;
15530   a |= (*codep++ & 0xff) << 8;
15531   a |= (*codep++ & 0xff) << 16;
15532   a |= (*codep++ & 0xffu) << 24;
15533   b = *codep++ & 0xff;
15534   b |= (*codep++ & 0xff) << 8;
15535   b |= (*codep++ & 0xff) << 16;
15536   b |= (*codep++ & 0xffu) << 24;
15537   x = a + ((bfd_vma) b << 32);
15538 #else
15539   abort ();
15540   x = 0;
15541 #endif
15542   return x;
15543 }
15544
15545 static bfd_signed_vma
15546 get32 (void)
15547 {
15548   bfd_signed_vma x = 0;
15549
15550   FETCH_DATA (the_info, codep + 4);
15551   x = *codep++ & (bfd_signed_vma) 0xff;
15552   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15553   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15554   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15555   return x;
15556 }
15557
15558 static bfd_signed_vma
15559 get32s (void)
15560 {
15561   bfd_signed_vma x = 0;
15562
15563   FETCH_DATA (the_info, codep + 4);
15564   x = *codep++ & (bfd_signed_vma) 0xff;
15565   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15566   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15567   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15568
15569   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
15570
15571   return x;
15572 }
15573
15574 static int
15575 get16 (void)
15576 {
15577   int x = 0;
15578
15579   FETCH_DATA (the_info, codep + 2);
15580   x = *codep++ & 0xff;
15581   x |= (*codep++ & 0xff) << 8;
15582   return x;
15583 }
15584
15585 static void
15586 set_op (bfd_vma op, int riprel)
15587 {
15588   op_index[op_ad] = op_ad;
15589   if (address_mode == mode_64bit)
15590     {
15591       op_address[op_ad] = op;
15592       op_riprel[op_ad] = riprel;
15593     }
15594   else
15595     {
15596       /* Mask to get a 32-bit address.  */
15597       op_address[op_ad] = op & 0xffffffff;
15598       op_riprel[op_ad] = riprel & 0xffffffff;
15599     }
15600 }
15601
15602 static void
15603 OP_REG (int code, int sizeflag)
15604 {
15605   const char *s;
15606   int add;
15607
15608   switch (code)
15609     {
15610     case es_reg: case ss_reg: case cs_reg:
15611     case ds_reg: case fs_reg: case gs_reg:
15612       oappend (names_seg[code - es_reg]);
15613       return;
15614     }
15615
15616   USED_REX (REX_B);
15617   if (rex & REX_B)
15618     add = 8;
15619   else
15620     add = 0;
15621
15622   switch (code)
15623     {
15624     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15625     case sp_reg: case bp_reg: case si_reg: case di_reg:
15626       s = names16[code - ax_reg + add];
15627       break;
15628     case al_reg: case ah_reg: case cl_reg: case ch_reg:
15629     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15630       USED_REX (0);
15631       if (rex)
15632         s = names8rex[code - al_reg + add];
15633       else
15634         s = names8[code - al_reg];
15635       break;
15636     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
15637     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
15638       if (address_mode == mode_64bit
15639           && ((sizeflag & DFLAG) || (rex & REX_W)))
15640         {
15641           s = names64[code - rAX_reg + add];
15642           break;
15643         }
15644       code += eAX_reg - rAX_reg;
15645       /* Fall through.  */
15646     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15647     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15648       USED_REX (REX_W);
15649       if (rex & REX_W)
15650         s = names64[code - eAX_reg + add];
15651       else
15652         {
15653           if (sizeflag & DFLAG)
15654             s = names32[code - eAX_reg + add];
15655           else
15656             s = names16[code - eAX_reg + add];
15657           used_prefixes |= (prefixes & PREFIX_DATA);
15658         }
15659       break;
15660     default:
15661       s = INTERNAL_DISASSEMBLER_ERROR;
15662       break;
15663     }
15664   oappend (s);
15665 }
15666
15667 static void
15668 OP_IMREG (int code, int sizeflag)
15669 {
15670   const char *s;
15671
15672   switch (code)
15673     {
15674     case indir_dx_reg:
15675       if (intel_syntax)
15676         s = "dx";
15677       else
15678         s = "(%dx)";
15679       break;
15680     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15681     case sp_reg: case bp_reg: case si_reg: case di_reg:
15682       s = names16[code - ax_reg];
15683       break;
15684     case es_reg: case ss_reg: case cs_reg:
15685     case ds_reg: case fs_reg: case gs_reg:
15686       s = names_seg[code - es_reg];
15687       break;
15688     case al_reg: case ah_reg: case cl_reg: case ch_reg:
15689     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15690       USED_REX (0);
15691       if (rex)
15692         s = names8rex[code - al_reg];
15693       else
15694         s = names8[code - al_reg];
15695       break;
15696     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15697     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15698       USED_REX (REX_W);
15699       if (rex & REX_W)
15700         s = names64[code - eAX_reg];
15701       else
15702         {
15703           if (sizeflag & DFLAG)
15704             s = names32[code - eAX_reg];
15705           else
15706             s = names16[code - eAX_reg];
15707           used_prefixes |= (prefixes & PREFIX_DATA);
15708         }
15709       break;
15710     case z_mode_ax_reg:
15711       if ((rex & REX_W) || (sizeflag & DFLAG))
15712         s = *names32;
15713       else
15714         s = *names16;
15715       if (!(rex & REX_W))
15716         used_prefixes |= (prefixes & PREFIX_DATA);
15717       break;
15718     default:
15719       s = INTERNAL_DISASSEMBLER_ERROR;
15720       break;
15721     }
15722   oappend (s);
15723 }
15724
15725 static void
15726 OP_I (int bytemode, int sizeflag)
15727 {
15728   bfd_signed_vma op;
15729   bfd_signed_vma mask = -1;
15730
15731   switch (bytemode)
15732     {
15733     case b_mode:
15734       FETCH_DATA (the_info, codep + 1);
15735       op = *codep++;
15736       mask = 0xff;
15737       break;
15738     case q_mode:
15739       if (address_mode == mode_64bit)
15740         {
15741           op = get32s ();
15742           break;
15743         }
15744       /* Fall through.  */
15745     case v_mode:
15746       USED_REX (REX_W);
15747       if (rex & REX_W)
15748         op = get32s ();
15749       else
15750         {
15751           if (sizeflag & DFLAG)
15752             {
15753               op = get32 ();
15754               mask = 0xffffffff;
15755             }
15756           else
15757             {
15758               op = get16 ();
15759               mask = 0xfffff;
15760             }
15761           used_prefixes |= (prefixes & PREFIX_DATA);
15762         }
15763       break;
15764     case w_mode:
15765       mask = 0xfffff;
15766       op = get16 ();
15767       break;
15768     case const_1_mode:
15769       if (intel_syntax)
15770         oappend ("1");
15771       return;
15772     default:
15773       oappend (INTERNAL_DISASSEMBLER_ERROR);
15774       return;
15775     }
15776
15777   op &= mask;
15778   scratchbuf[0] = '$';
15779   print_operand_value (scratchbuf + 1, 1, op);
15780   oappend_maybe_intel (scratchbuf);
15781   scratchbuf[0] = '\0';
15782 }
15783
15784 static void
15785 OP_I64 (int bytemode, int sizeflag)
15786 {
15787   bfd_signed_vma op;
15788   bfd_signed_vma mask = -1;
15789
15790   if (address_mode != mode_64bit)
15791     {
15792       OP_I (bytemode, sizeflag);
15793       return;
15794     }
15795
15796   switch (bytemode)
15797     {
15798     case b_mode:
15799       FETCH_DATA (the_info, codep + 1);
15800       op = *codep++;
15801       mask = 0xff;
15802       break;
15803     case v_mode:
15804       USED_REX (REX_W);
15805       if (rex & REX_W)
15806         op = get64 ();
15807       else
15808         {
15809           if (sizeflag & DFLAG)
15810             {
15811               op = get32 ();
15812               mask = 0xffffffff;
15813             }
15814           else
15815             {
15816               op = get16 ();
15817               mask = 0xfffff;
15818             }
15819           used_prefixes |= (prefixes & PREFIX_DATA);
15820         }
15821       break;
15822     case w_mode:
15823       mask = 0xfffff;
15824       op = get16 ();
15825       break;
15826     default:
15827       oappend (INTERNAL_DISASSEMBLER_ERROR);
15828       return;
15829     }
15830
15831   op &= mask;
15832   scratchbuf[0] = '$';
15833   print_operand_value (scratchbuf + 1, 1, op);
15834   oappend_maybe_intel (scratchbuf);
15835   scratchbuf[0] = '\0';
15836 }
15837
15838 static void
15839 OP_sI (int bytemode, int sizeflag)
15840 {
15841   bfd_signed_vma op;
15842
15843   switch (bytemode)
15844     {
15845     case b_mode:
15846     case b_T_mode:
15847       FETCH_DATA (the_info, codep + 1);
15848       op = *codep++;
15849       if ((op & 0x80) != 0)
15850         op -= 0x100;
15851       if (bytemode == b_T_mode)
15852         {
15853           if (address_mode != mode_64bit
15854               || !((sizeflag & DFLAG) || (rex & REX_W)))
15855             {
15856               /* The operand-size prefix is overridden by a REX prefix.  */
15857               if ((sizeflag & DFLAG) || (rex & REX_W))
15858                 op &= 0xffffffff;
15859               else
15860                 op &= 0xffff;
15861           }
15862         }
15863       else
15864         {
15865           if (!(rex & REX_W))
15866             {
15867               if (sizeflag & DFLAG)
15868                 op &= 0xffffffff;
15869               else
15870                 op &= 0xffff;
15871             }
15872         }
15873       break;
15874     case v_mode:
15875       /* The operand-size prefix is overridden by a REX prefix.  */
15876       if ((sizeflag & DFLAG) || (rex & REX_W))
15877         op = get32s ();
15878       else
15879         op = get16 ();
15880       break;
15881     default:
15882       oappend (INTERNAL_DISASSEMBLER_ERROR);
15883       return;
15884     }
15885
15886   scratchbuf[0] = '$';
15887   print_operand_value (scratchbuf + 1, 1, op);
15888   oappend_maybe_intel (scratchbuf);
15889 }
15890
15891 static void
15892 OP_J (int bytemode, int sizeflag)
15893 {
15894   bfd_vma disp;
15895   bfd_vma mask = -1;
15896   bfd_vma segment = 0;
15897
15898   switch (bytemode)
15899     {
15900     case b_mode:
15901       FETCH_DATA (the_info, codep + 1);
15902       disp = *codep++;
15903       if ((disp & 0x80) != 0)
15904         disp -= 0x100;
15905       break;
15906     case v_mode:
15907       if (isa64 == amd64)
15908         USED_REX (REX_W);
15909       if ((sizeflag & DFLAG)
15910           || (address_mode == mode_64bit
15911               && (isa64 != amd64 || (rex & REX_W))))
15912         disp = get32s ();
15913       else
15914         {
15915           disp = get16 ();
15916           if ((disp & 0x8000) != 0)
15917             disp -= 0x10000;
15918           /* In 16bit mode, address is wrapped around at 64k within
15919              the same segment.  Otherwise, a data16 prefix on a jump
15920              instruction means that the pc is masked to 16 bits after
15921              the displacement is added!  */
15922           mask = 0xffff;
15923           if ((prefixes & PREFIX_DATA) == 0)
15924             segment = ((start_pc + (codep - start_codep))
15925                        & ~((bfd_vma) 0xffff));
15926         }
15927       if (address_mode != mode_64bit
15928           || (isa64 == amd64 && !(rex & REX_W)))
15929         used_prefixes |= (prefixes & PREFIX_DATA);
15930       break;
15931     default:
15932       oappend (INTERNAL_DISASSEMBLER_ERROR);
15933       return;
15934     }
15935   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
15936   set_op (disp, 0);
15937   print_operand_value (scratchbuf, 1, disp);
15938   oappend (scratchbuf);
15939 }
15940
15941 static void
15942 OP_SEG (int bytemode, int sizeflag)
15943 {
15944   if (bytemode == w_mode)
15945     oappend (names_seg[modrm.reg]);
15946   else
15947     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
15948 }
15949
15950 static void
15951 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
15952 {
15953   int seg, offset;
15954
15955   if (sizeflag & DFLAG)
15956     {
15957       offset = get32 ();
15958       seg = get16 ();
15959     }
15960   else
15961     {
15962       offset = get16 ();
15963       seg = get16 ();
15964     }
15965   used_prefixes |= (prefixes & PREFIX_DATA);
15966   if (intel_syntax)
15967     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
15968   else
15969     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
15970   oappend (scratchbuf);
15971 }
15972
15973 static void
15974 OP_OFF (int bytemode, int sizeflag)
15975 {
15976   bfd_vma off;
15977
15978   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
15979     intel_operand_size (bytemode, sizeflag);
15980   append_seg ();
15981
15982   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
15983     off = get32 ();
15984   else
15985     off = get16 ();
15986
15987   if (intel_syntax)
15988     {
15989       if (!active_seg_prefix)
15990         {
15991           oappend (names_seg[ds_reg - es_reg]);
15992           oappend (":");
15993         }
15994     }
15995   print_operand_value (scratchbuf, 1, off);
15996   oappend (scratchbuf);
15997 }
15998
15999 static void
16000 OP_OFF64 (int bytemode, int sizeflag)
16001 {
16002   bfd_vma off;
16003
16004   if (address_mode != mode_64bit
16005       || (prefixes & PREFIX_ADDR))
16006     {
16007       OP_OFF (bytemode, sizeflag);
16008       return;
16009     }
16010
16011   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
16012     intel_operand_size (bytemode, sizeflag);
16013   append_seg ();
16014
16015   off = get64 ();
16016
16017   if (intel_syntax)
16018     {
16019       if (!active_seg_prefix)
16020         {
16021           oappend (names_seg[ds_reg - es_reg]);
16022           oappend (":");
16023         }
16024     }
16025   print_operand_value (scratchbuf, 1, off);
16026   oappend (scratchbuf);
16027 }
16028
16029 static void
16030 ptr_reg (int code, int sizeflag)
16031 {
16032   const char *s;
16033
16034   *obufp++ = open_char;
16035   used_prefixes |= (prefixes & PREFIX_ADDR);
16036   if (address_mode == mode_64bit)
16037     {
16038       if (!(sizeflag & AFLAG))
16039         s = names32[code - eAX_reg];
16040       else
16041         s = names64[code - eAX_reg];
16042     }
16043   else if (sizeflag & AFLAG)
16044     s = names32[code - eAX_reg];
16045   else
16046     s = names16[code - eAX_reg];
16047   oappend (s);
16048   *obufp++ = close_char;
16049   *obufp = 0;
16050 }
16051
16052 static void
16053 OP_ESreg (int code, int sizeflag)
16054 {
16055   if (intel_syntax)
16056     {
16057       switch (codep[-1])
16058         {
16059         case 0x6d:      /* insw/insl */
16060           intel_operand_size (z_mode, sizeflag);
16061           break;
16062         case 0xa5:      /* movsw/movsl/movsq */
16063         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
16064         case 0xab:      /* stosw/stosl */
16065         case 0xaf:      /* scasw/scasl */
16066           intel_operand_size (v_mode, sizeflag);
16067           break;
16068         default:
16069           intel_operand_size (b_mode, sizeflag);
16070         }
16071     }
16072   oappend_maybe_intel ("%es:");
16073   ptr_reg (code, sizeflag);
16074 }
16075
16076 static void
16077 OP_DSreg (int code, int sizeflag)
16078 {
16079   if (intel_syntax)
16080     {
16081       switch (codep[-1])
16082         {
16083         case 0x6f:      /* outsw/outsl */
16084           intel_operand_size (z_mode, sizeflag);
16085           break;
16086         case 0xa5:      /* movsw/movsl/movsq */
16087         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
16088         case 0xad:      /* lodsw/lodsl/lodsq */
16089           intel_operand_size (v_mode, sizeflag);
16090           break;
16091         default:
16092           intel_operand_size (b_mode, sizeflag);
16093         }
16094     }
16095   /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
16096      default segment register DS is printed.  */
16097   if (!active_seg_prefix)
16098     active_seg_prefix = PREFIX_DS;
16099   append_seg ();
16100   ptr_reg (code, sizeflag);
16101 }
16102
16103 static void
16104 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16105 {
16106   int add;
16107   if (rex & REX_R)
16108     {
16109       USED_REX (REX_R);
16110       add = 8;
16111     }
16112   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
16113     {
16114       all_prefixes[last_lock_prefix] = 0;
16115       used_prefixes |= PREFIX_LOCK;
16116       add = 8;
16117     }
16118   else
16119     add = 0;
16120   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
16121   oappend_maybe_intel (scratchbuf);
16122 }
16123
16124 static void
16125 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16126 {
16127   int add;
16128   USED_REX (REX_R);
16129   if (rex & REX_R)
16130     add = 8;
16131   else
16132     add = 0;
16133   if (intel_syntax)
16134     sprintf (scratchbuf, "db%d", modrm.reg + add);
16135   else
16136     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
16137   oappend (scratchbuf);
16138 }
16139
16140 static void
16141 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16142 {
16143   sprintf (scratchbuf, "%%tr%d", modrm.reg);
16144   oappend_maybe_intel (scratchbuf);
16145 }
16146
16147 static void
16148 OP_R (int bytemode, int sizeflag)
16149 {
16150   /* Skip mod/rm byte.  */
16151   MODRM_CHECK;
16152   codep++;
16153   OP_E_register (bytemode, sizeflag);
16154 }
16155
16156 static void
16157 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16158 {
16159   int reg = modrm.reg;
16160   const char **names;
16161
16162   used_prefixes |= (prefixes & PREFIX_DATA);
16163   if (prefixes & PREFIX_DATA)
16164     {
16165       names = names_xmm;
16166       USED_REX (REX_R);
16167       if (rex & REX_R)
16168         reg += 8;
16169     }
16170   else
16171     names = names_mm;
16172   oappend (names[reg]);
16173 }
16174
16175 static void
16176 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16177 {
16178   int reg = modrm.reg;
16179   const char **names;
16180
16181   USED_REX (REX_R);
16182   if (rex & REX_R)
16183     reg += 8;
16184   if (vex.evex)
16185     {
16186       if (!vex.r)
16187         reg += 16;
16188     }
16189
16190   if (need_vex
16191       && bytemode != xmm_mode
16192       && bytemode != xmmq_mode
16193       && bytemode != evex_half_bcst_xmmq_mode
16194       && bytemode != ymm_mode
16195       && bytemode != scalar_mode)
16196     {
16197       switch (vex.length)
16198         {
16199         case 128:
16200           names = names_xmm;
16201           break;
16202         case 256:
16203           if (vex.w
16204               || (bytemode != vex_vsib_q_w_dq_mode
16205                   && bytemode != vex_vsib_q_w_d_mode))
16206             names = names_ymm;
16207           else
16208             names = names_xmm;
16209           break;
16210         case 512:
16211           names = names_zmm;
16212           break;
16213         default:
16214           abort ();
16215         }
16216     }
16217   else if (bytemode == xmmq_mode
16218            || bytemode == evex_half_bcst_xmmq_mode)
16219     {
16220       switch (vex.length)
16221         {
16222         case 128:
16223         case 256:
16224           names = names_xmm;
16225           break;
16226         case 512:
16227           names = names_ymm;
16228           break;
16229         default:
16230           abort ();
16231         }
16232     }
16233   else if (bytemode == ymm_mode)
16234     names = names_ymm;
16235   else
16236     names = names_xmm;
16237   oappend (names[reg]);
16238 }
16239
16240 static void
16241 OP_EM (int bytemode, int sizeflag)
16242 {
16243   int reg;
16244   const char **names;
16245
16246   if (modrm.mod != 3)
16247     {
16248       if (intel_syntax
16249           && (bytemode == v_mode || bytemode == v_swap_mode))
16250         {
16251           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16252           used_prefixes |= (prefixes & PREFIX_DATA);
16253         }
16254       OP_E (bytemode, sizeflag);
16255       return;
16256     }
16257
16258   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
16259     swap_operand ();
16260
16261   /* Skip mod/rm byte.  */
16262   MODRM_CHECK;
16263   codep++;
16264   used_prefixes |= (prefixes & PREFIX_DATA);
16265   reg = modrm.rm;
16266   if (prefixes & PREFIX_DATA)
16267     {
16268       names = names_xmm;
16269       USED_REX (REX_B);
16270       if (rex & REX_B)
16271         reg += 8;
16272     }
16273   else
16274     names = names_mm;
16275   oappend (names[reg]);
16276 }
16277
16278 /* cvt* are the only instructions in sse2 which have
16279    both SSE and MMX operands and also have 0x66 prefix
16280    in their opcode. 0x66 was originally used to differentiate
16281    between SSE and MMX instruction(operands). So we have to handle the
16282    cvt* separately using OP_EMC and OP_MXC */
16283 static void
16284 OP_EMC (int bytemode, int sizeflag)
16285 {
16286   if (modrm.mod != 3)
16287     {
16288       if (intel_syntax && bytemode == v_mode)
16289         {
16290           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16291           used_prefixes |= (prefixes & PREFIX_DATA);
16292         }
16293       OP_E (bytemode, sizeflag);
16294       return;
16295     }
16296
16297   /* Skip mod/rm byte.  */
16298   MODRM_CHECK;
16299   codep++;
16300   used_prefixes |= (prefixes & PREFIX_DATA);
16301   oappend (names_mm[modrm.rm]);
16302 }
16303
16304 static void
16305 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16306 {
16307   used_prefixes |= (prefixes & PREFIX_DATA);
16308   oappend (names_mm[modrm.reg]);
16309 }
16310
16311 static void
16312 OP_EX (int bytemode, int sizeflag)
16313 {
16314   int reg;
16315   const char **names;
16316
16317   /* Skip mod/rm byte.  */
16318   MODRM_CHECK;
16319   codep++;
16320
16321   if (modrm.mod != 3)
16322     {
16323       OP_E_memory (bytemode, sizeflag);
16324       return;
16325     }
16326
16327   reg = modrm.rm;
16328   USED_REX (REX_B);
16329   if (rex & REX_B)
16330     reg += 8;
16331   if (vex.evex)
16332     {
16333       USED_REX (REX_X);
16334       if ((rex & REX_X))
16335         reg += 16;
16336     }
16337
16338   if ((sizeflag & SUFFIX_ALWAYS)
16339       && (bytemode == x_swap_mode
16340           || bytemode == d_swap_mode
16341           || bytemode == d_scalar_swap_mode
16342           || bytemode == q_swap_mode
16343           || bytemode == q_scalar_swap_mode))
16344     swap_operand ();
16345
16346   if (need_vex
16347       && bytemode != xmm_mode
16348       && bytemode != xmmdw_mode
16349       && bytemode != xmmqd_mode
16350       && bytemode != xmm_mb_mode
16351       && bytemode != xmm_mw_mode
16352       && bytemode != xmm_md_mode
16353       && bytemode != xmm_mq_mode
16354       && bytemode != xmm_mdq_mode
16355       && bytemode != xmmq_mode
16356       && bytemode != evex_half_bcst_xmmq_mode
16357       && bytemode != ymm_mode
16358       && bytemode != d_scalar_mode
16359       && bytemode != d_scalar_swap_mode
16360       && bytemode != q_scalar_mode
16361       && bytemode != q_scalar_swap_mode
16362       && bytemode != vex_scalar_w_dq_mode)
16363     {
16364       switch (vex.length)
16365         {
16366         case 128:
16367           names = names_xmm;
16368           break;
16369         case 256:
16370           names = names_ymm;
16371           break;
16372         case 512:
16373           names = names_zmm;
16374           break;
16375         default:
16376           abort ();
16377         }
16378     }
16379   else if (bytemode == xmmq_mode
16380            || bytemode == evex_half_bcst_xmmq_mode)
16381     {
16382       switch (vex.length)
16383         {
16384         case 128:
16385         case 256:
16386           names = names_xmm;
16387           break;
16388         case 512:
16389           names = names_ymm;
16390           break;
16391         default:
16392           abort ();
16393         }
16394     }
16395   else if (bytemode == ymm_mode)
16396     names = names_ymm;
16397   else
16398     names = names_xmm;
16399   oappend (names[reg]);
16400 }
16401
16402 static void
16403 OP_MS (int bytemode, int sizeflag)
16404 {
16405   if (modrm.mod == 3)
16406     OP_EM (bytemode, sizeflag);
16407   else
16408     BadOp ();
16409 }
16410
16411 static void
16412 OP_XS (int bytemode, int sizeflag)
16413 {
16414   if (modrm.mod == 3)
16415     OP_EX (bytemode, sizeflag);
16416   else
16417     BadOp ();
16418 }
16419
16420 static void
16421 OP_M (int bytemode, int sizeflag)
16422 {
16423   if (modrm.mod == 3)
16424     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
16425     BadOp ();
16426   else
16427     OP_E (bytemode, sizeflag);
16428 }
16429
16430 static void
16431 OP_0f07 (int bytemode, int sizeflag)
16432 {
16433   if (modrm.mod != 3 || modrm.rm != 0)
16434     BadOp ();
16435   else
16436     OP_E (bytemode, sizeflag);
16437 }
16438
16439 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
16440    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
16441
16442 static void
16443 NOP_Fixup1 (int bytemode, int sizeflag)
16444 {
16445   if ((prefixes & PREFIX_DATA) != 0
16446       || (rex != 0
16447           && rex != 0x48
16448           && address_mode == mode_64bit))
16449     OP_REG (bytemode, sizeflag);
16450   else
16451     strcpy (obuf, "nop");
16452 }
16453
16454 static void
16455 NOP_Fixup2 (int bytemode, int sizeflag)
16456 {
16457   if ((prefixes & PREFIX_DATA) != 0
16458       || (rex != 0
16459           && rex != 0x48
16460           && address_mode == mode_64bit))
16461     OP_IMREG (bytemode, sizeflag);
16462 }
16463
16464 static const char *const Suffix3DNow[] = {
16465 /* 00 */        NULL,           NULL,           NULL,           NULL,
16466 /* 04 */        NULL,           NULL,           NULL,           NULL,
16467 /* 08 */        NULL,           NULL,           NULL,           NULL,
16468 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
16469 /* 10 */        NULL,           NULL,           NULL,           NULL,
16470 /* 14 */        NULL,           NULL,           NULL,           NULL,
16471 /* 18 */        NULL,           NULL,           NULL,           NULL,
16472 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
16473 /* 20 */        NULL,           NULL,           NULL,           NULL,
16474 /* 24 */        NULL,           NULL,           NULL,           NULL,
16475 /* 28 */        NULL,           NULL,           NULL,           NULL,
16476 /* 2C */        NULL,           NULL,           NULL,           NULL,
16477 /* 30 */        NULL,           NULL,           NULL,           NULL,
16478 /* 34 */        NULL,           NULL,           NULL,           NULL,
16479 /* 38 */        NULL,           NULL,           NULL,           NULL,
16480 /* 3C */        NULL,           NULL,           NULL,           NULL,
16481 /* 40 */        NULL,           NULL,           NULL,           NULL,
16482 /* 44 */        NULL,           NULL,           NULL,           NULL,
16483 /* 48 */        NULL,           NULL,           NULL,           NULL,
16484 /* 4C */        NULL,           NULL,           NULL,           NULL,
16485 /* 50 */        NULL,           NULL,           NULL,           NULL,
16486 /* 54 */        NULL,           NULL,           NULL,           NULL,
16487 /* 58 */        NULL,           NULL,           NULL,           NULL,
16488 /* 5C */        NULL,           NULL,           NULL,           NULL,
16489 /* 60 */        NULL,           NULL,           NULL,           NULL,
16490 /* 64 */        NULL,           NULL,           NULL,           NULL,
16491 /* 68 */        NULL,           NULL,           NULL,           NULL,
16492 /* 6C */        NULL,           NULL,           NULL,           NULL,
16493 /* 70 */        NULL,           NULL,           NULL,           NULL,
16494 /* 74 */        NULL,           NULL,           NULL,           NULL,
16495 /* 78 */        NULL,           NULL,           NULL,           NULL,
16496 /* 7C */        NULL,           NULL,           NULL,           NULL,
16497 /* 80 */        NULL,           NULL,           NULL,           NULL,
16498 /* 84 */        NULL,           NULL,           NULL,           NULL,
16499 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
16500 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
16501 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
16502 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
16503 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
16504 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
16505 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
16506 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
16507 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
16508 /* AC */        NULL,           NULL,           "pfacc",        NULL,
16509 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
16510 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
16511 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
16512 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
16513 /* C0 */        NULL,           NULL,           NULL,           NULL,
16514 /* C4 */        NULL,           NULL,           NULL,           NULL,
16515 /* C8 */        NULL,           NULL,           NULL,           NULL,
16516 /* CC */        NULL,           NULL,           NULL,           NULL,
16517 /* D0 */        NULL,           NULL,           NULL,           NULL,
16518 /* D4 */        NULL,           NULL,           NULL,           NULL,
16519 /* D8 */        NULL,           NULL,           NULL,           NULL,
16520 /* DC */        NULL,           NULL,           NULL,           NULL,
16521 /* E0 */        NULL,           NULL,           NULL,           NULL,
16522 /* E4 */        NULL,           NULL,           NULL,           NULL,
16523 /* E8 */        NULL,           NULL,           NULL,           NULL,
16524 /* EC */        NULL,           NULL,           NULL,           NULL,
16525 /* F0 */        NULL,           NULL,           NULL,           NULL,
16526 /* F4 */        NULL,           NULL,           NULL,           NULL,
16527 /* F8 */        NULL,           NULL,           NULL,           NULL,
16528 /* FC */        NULL,           NULL,           NULL,           NULL,
16529 };
16530
16531 static void
16532 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16533 {
16534   const char *mnemonic;
16535
16536   FETCH_DATA (the_info, codep + 1);
16537   /* AMD 3DNow! instructions are specified by an opcode suffix in the
16538      place where an 8-bit immediate would normally go.  ie. the last
16539      byte of the instruction.  */
16540   obufp = mnemonicendp;
16541   mnemonic = Suffix3DNow[*codep++ & 0xff];
16542   if (mnemonic)
16543     oappend (mnemonic);
16544   else
16545     {
16546       /* Since a variable sized modrm/sib chunk is between the start
16547          of the opcode (0x0f0f) and the opcode suffix, we need to do
16548          all the modrm processing first, and don't know until now that
16549          we have a bad opcode.  This necessitates some cleaning up.  */
16550       op_out[0][0] = '\0';
16551       op_out[1][0] = '\0';
16552       BadOp ();
16553     }
16554   mnemonicendp = obufp;
16555 }
16556
16557 static struct op simd_cmp_op[] =
16558 {
16559   { STRING_COMMA_LEN ("eq") },
16560   { STRING_COMMA_LEN ("lt") },
16561   { STRING_COMMA_LEN ("le") },
16562   { STRING_COMMA_LEN ("unord") },
16563   { STRING_COMMA_LEN ("neq") },
16564   { STRING_COMMA_LEN ("nlt") },
16565   { STRING_COMMA_LEN ("nle") },
16566   { STRING_COMMA_LEN ("ord") }
16567 };
16568
16569 static void
16570 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16571 {
16572   unsigned int cmp_type;
16573
16574   FETCH_DATA (the_info, codep + 1);
16575   cmp_type = *codep++ & 0xff;
16576   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
16577     {
16578       char suffix [3];
16579       char *p = mnemonicendp - 2;
16580       suffix[0] = p[0];
16581       suffix[1] = p[1];
16582       suffix[2] = '\0';
16583       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16584       mnemonicendp += simd_cmp_op[cmp_type].len;
16585     }
16586   else
16587     {
16588       /* We have a reserved extension byte.  Output it directly.  */
16589       scratchbuf[0] = '$';
16590       print_operand_value (scratchbuf + 1, 1, cmp_type);
16591       oappend_maybe_intel (scratchbuf);
16592       scratchbuf[0] = '\0';
16593     }
16594 }
16595
16596 static void
16597 OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED,
16598           int sizeflag ATTRIBUTE_UNUSED)
16599 {
16600   /* mwaitx %eax,%ecx,%ebx */
16601   if (!intel_syntax)
16602     {
16603       const char **names = (address_mode == mode_64bit
16604                             ? names64 : names32);
16605       strcpy (op_out[0], names[0]);
16606       strcpy (op_out[1], names[1]);
16607       strcpy (op_out[2], names[3]);
16608       two_source_ops = 1;
16609     }
16610   /* Skip mod/rm byte.  */
16611   MODRM_CHECK;
16612   codep++;
16613 }
16614
16615 static void
16616 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
16617           int sizeflag ATTRIBUTE_UNUSED)
16618 {
16619   /* mwait %eax,%ecx  */
16620   if (!intel_syntax)
16621     {
16622       const char **names = (address_mode == mode_64bit
16623                             ? names64 : names32);
16624       strcpy (op_out[0], names[0]);
16625       strcpy (op_out[1], names[1]);
16626       two_source_ops = 1;
16627     }
16628   /* Skip mod/rm byte.  */
16629   MODRM_CHECK;
16630   codep++;
16631 }
16632
16633 static void
16634 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
16635             int sizeflag ATTRIBUTE_UNUSED)
16636 {
16637   /* monitor %eax,%ecx,%edx"  */
16638   if (!intel_syntax)
16639     {
16640       const char **op1_names;
16641       const char **names = (address_mode == mode_64bit
16642                             ? names64 : names32);
16643
16644       if (!(prefixes & PREFIX_ADDR))
16645         op1_names = (address_mode == mode_16bit
16646                      ? names16 : names);
16647       else
16648         {
16649           /* Remove "addr16/addr32".  */
16650           all_prefixes[last_addr_prefix] = 0;
16651           op1_names = (address_mode != mode_32bit
16652                        ? names32 : names16);
16653           used_prefixes |= PREFIX_ADDR;
16654         }
16655       strcpy (op_out[0], op1_names[0]);
16656       strcpy (op_out[1], names[1]);
16657       strcpy (op_out[2], names[2]);
16658       two_source_ops = 1;
16659     }
16660   /* Skip mod/rm byte.  */
16661   MODRM_CHECK;
16662   codep++;
16663 }
16664
16665 static void
16666 BadOp (void)
16667 {
16668   /* Throw away prefixes and 1st. opcode byte.  */
16669   codep = insn_codep + 1;
16670   oappend ("(bad)");
16671 }
16672
16673 static void
16674 REP_Fixup (int bytemode, int sizeflag)
16675 {
16676   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
16677      lods and stos.  */
16678   if (prefixes & PREFIX_REPZ)
16679     all_prefixes[last_repz_prefix] = REP_PREFIX;
16680
16681   switch (bytemode)
16682     {
16683     case al_reg:
16684     case eAX_reg:
16685     case indir_dx_reg:
16686       OP_IMREG (bytemode, sizeflag);
16687       break;
16688     case eDI_reg:
16689       OP_ESreg (bytemode, sizeflag);
16690       break;
16691     case eSI_reg:
16692       OP_DSreg (bytemode, sizeflag);
16693       break;
16694     default:
16695       abort ();
16696       break;
16697     }
16698 }
16699
16700 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
16701    "bnd".  */
16702
16703 static void
16704 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16705 {
16706   if (prefixes & PREFIX_REPNZ)
16707     all_prefixes[last_repnz_prefix] = BND_PREFIX;
16708 }
16709
16710 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
16711    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
16712  */
16713
16714 static void
16715 HLE_Fixup1 (int bytemode, int sizeflag)
16716 {
16717   if (modrm.mod != 3
16718       && (prefixes & PREFIX_LOCK) != 0)
16719     {
16720       if (prefixes & PREFIX_REPZ)
16721         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16722       if (prefixes & PREFIX_REPNZ)
16723         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16724     }
16725
16726   OP_E (bytemode, sizeflag);
16727 }
16728
16729 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
16730    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
16731  */
16732
16733 static void
16734 HLE_Fixup2 (int bytemode, int sizeflag)
16735 {
16736   if (modrm.mod != 3)
16737     {
16738       if (prefixes & PREFIX_REPZ)
16739         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16740       if (prefixes & PREFIX_REPNZ)
16741         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16742     }
16743
16744   OP_E (bytemode, sizeflag);
16745 }
16746
16747 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
16748    "xrelease" for memory operand.  No check for LOCK prefix.   */
16749
16750 static void
16751 HLE_Fixup3 (int bytemode, int sizeflag)
16752 {
16753   if (modrm.mod != 3
16754       && last_repz_prefix > last_repnz_prefix
16755       && (prefixes & PREFIX_REPZ) != 0)
16756     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16757
16758   OP_E (bytemode, sizeflag);
16759 }
16760
16761 static void
16762 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
16763 {
16764   USED_REX (REX_W);
16765   if (rex & REX_W)
16766     {
16767       /* Change cmpxchg8b to cmpxchg16b.  */
16768       char *p = mnemonicendp - 2;
16769       mnemonicendp = stpcpy (p, "16b");
16770       bytemode = o_mode;
16771     }
16772   else if ((prefixes & PREFIX_LOCK) != 0)
16773     {
16774       if (prefixes & PREFIX_REPZ)
16775         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16776       if (prefixes & PREFIX_REPNZ)
16777         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16778     }
16779
16780   OP_M (bytemode, sizeflag);
16781 }
16782
16783 static void
16784 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
16785 {
16786   const char **names;
16787
16788   if (need_vex)
16789     {
16790       switch (vex.length)
16791         {
16792         case 128:
16793           names = names_xmm;
16794           break;
16795         case 256:
16796           names = names_ymm;
16797           break;
16798         default:
16799           abort ();
16800         }
16801     }
16802   else
16803     names = names_xmm;
16804   oappend (names[reg]);
16805 }
16806
16807 static void
16808 CRC32_Fixup (int bytemode, int sizeflag)
16809 {
16810   /* Add proper suffix to "crc32".  */
16811   char *p = mnemonicendp;
16812
16813   switch (bytemode)
16814     {
16815     case b_mode:
16816       if (intel_syntax)
16817         goto skip;
16818
16819       *p++ = 'b';
16820       break;
16821     case v_mode:
16822       if (intel_syntax)
16823         goto skip;
16824
16825       USED_REX (REX_W);
16826       if (rex & REX_W)
16827         *p++ = 'q';
16828       else
16829         {
16830           if (sizeflag & DFLAG)
16831             *p++ = 'l';
16832           else
16833             *p++ = 'w';
16834           used_prefixes |= (prefixes & PREFIX_DATA);
16835         }
16836       break;
16837     default:
16838       oappend (INTERNAL_DISASSEMBLER_ERROR);
16839       break;
16840     }
16841   mnemonicendp = p;
16842   *p = '\0';
16843
16844 skip:
16845   if (modrm.mod == 3)
16846     {
16847       int add;
16848
16849       /* Skip mod/rm byte.  */
16850       MODRM_CHECK;
16851       codep++;
16852
16853       USED_REX (REX_B);
16854       add = (rex & REX_B) ? 8 : 0;
16855       if (bytemode == b_mode)
16856         {
16857           USED_REX (0);
16858           if (rex)
16859             oappend (names8rex[modrm.rm + add]);
16860           else
16861             oappend (names8[modrm.rm + add]);
16862         }
16863       else
16864         {
16865           USED_REX (REX_W);
16866           if (rex & REX_W)
16867             oappend (names64[modrm.rm + add]);
16868           else if ((prefixes & PREFIX_DATA))
16869             oappend (names16[modrm.rm + add]);
16870           else
16871             oappend (names32[modrm.rm + add]);
16872         }
16873     }
16874   else
16875     OP_E (bytemode, sizeflag);
16876 }
16877
16878 static void
16879 FXSAVE_Fixup (int bytemode, int sizeflag)
16880 {
16881   /* Add proper suffix to "fxsave" and "fxrstor".  */
16882   USED_REX (REX_W);
16883   if (rex & REX_W)
16884     {
16885       char *p = mnemonicendp;
16886       *p++ = '6';
16887       *p++ = '4';
16888       *p = '\0';
16889       mnemonicendp = p;
16890     }
16891   OP_M (bytemode, sizeflag);
16892 }
16893
16894 /* Display the destination register operand for instructions with
16895    VEX. */
16896
16897 static void
16898 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16899 {
16900   int reg;
16901   const char **names;
16902
16903   if (!need_vex)
16904     abort ();
16905
16906   if (!need_vex_reg)
16907     return;
16908
16909   reg = vex.register_specifier;
16910   if (vex.evex)
16911     {
16912       if (!vex.v)
16913         reg += 16;
16914     }
16915
16916   if (bytemode == vex_scalar_mode)
16917     {
16918       oappend (names_xmm[reg]);
16919       return;
16920     }
16921
16922   switch (vex.length)
16923     {
16924     case 128:
16925       switch (bytemode)
16926         {
16927         case vex_mode:
16928         case vex128_mode:
16929         case vex_vsib_q_w_dq_mode:
16930         case vex_vsib_q_w_d_mode:
16931           names = names_xmm;
16932           break;
16933         case dq_mode:
16934           if (vex.w)
16935             names = names64;
16936           else
16937             names = names32;
16938           break;
16939         case mask_bd_mode:
16940         case mask_mode:
16941           if (reg > 0x7)
16942             {
16943               oappend ("(bad)");
16944               return;
16945             }
16946           names = names_mask;
16947           break;
16948         default:
16949           abort ();
16950           return;
16951         }
16952       break;
16953     case 256:
16954       switch (bytemode)
16955         {
16956         case vex_mode:
16957         case vex256_mode:
16958           names = names_ymm;
16959           break;
16960         case vex_vsib_q_w_dq_mode:
16961         case vex_vsib_q_w_d_mode:
16962           names = vex.w ? names_ymm : names_xmm;
16963           break;
16964         case mask_bd_mode:
16965         case mask_mode:
16966           if (reg > 0x7)
16967             {
16968               oappend ("(bad)");
16969               return;
16970             }
16971           names = names_mask;
16972           break;
16973         default:
16974           abort ();
16975           return;
16976         }
16977       break;
16978     case 512:
16979       names = names_zmm;
16980       break;
16981     default:
16982       abort ();
16983       break;
16984     }
16985   oappend (names[reg]);
16986 }
16987
16988 /* Get the VEX immediate byte without moving codep.  */
16989
16990 static unsigned char
16991 get_vex_imm8 (int sizeflag, int opnum)
16992 {
16993   int bytes_before_imm = 0;
16994
16995   if (modrm.mod != 3)
16996     {
16997       /* There are SIB/displacement bytes.  */
16998       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
16999         {
17000           /* 32/64 bit address mode */
17001           int base = modrm.rm;
17002
17003           /* Check SIB byte.  */
17004           if (base == 4)
17005             {
17006               FETCH_DATA (the_info, codep + 1);
17007               base = *codep & 7;
17008               /* When decoding the third source, don't increase
17009                  bytes_before_imm as this has already been incremented
17010                  by one in OP_E_memory while decoding the second
17011                  source operand.  */
17012               if (opnum == 0)
17013                 bytes_before_imm++;
17014             }
17015
17016           /* Don't increase bytes_before_imm when decoding the third source,
17017              it has already been incremented by OP_E_memory while decoding
17018              the second source operand.  */
17019           if (opnum == 0)
17020             {
17021               switch (modrm.mod)
17022                 {
17023                   case 0:
17024                     /* When modrm.rm == 5 or modrm.rm == 4 and base in
17025                        SIB == 5, there is a 4 byte displacement.  */
17026                     if (base != 5)
17027                       /* No displacement. */
17028                       break;
17029                     /* Fall through.  */
17030                   case 2:
17031                     /* 4 byte displacement.  */
17032                     bytes_before_imm += 4;
17033                     break;
17034                   case 1:
17035                     /* 1 byte displacement.  */
17036                     bytes_before_imm++;
17037                     break;
17038                 }
17039             }
17040         }
17041       else
17042         {
17043           /* 16 bit address mode */
17044           /* Don't increase bytes_before_imm when decoding the third source,
17045              it has already been incremented by OP_E_memory while decoding
17046              the second source operand.  */
17047           if (opnum == 0)
17048             {
17049               switch (modrm.mod)
17050                 {
17051                 case 0:
17052                   /* When modrm.rm == 6, there is a 2 byte displacement.  */
17053                   if (modrm.rm != 6)
17054                     /* No displacement. */
17055                     break;
17056                   /* Fall through.  */
17057                 case 2:
17058                   /* 2 byte displacement.  */
17059                   bytes_before_imm += 2;
17060                   break;
17061                 case 1:
17062                   /* 1 byte displacement: when decoding the third source,
17063                      don't increase bytes_before_imm as this has already
17064                      been incremented by one in OP_E_memory while decoding
17065                      the second source operand.  */
17066                   if (opnum == 0)
17067                     bytes_before_imm++;
17068
17069                   break;
17070                 }
17071             }
17072         }
17073     }
17074
17075   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
17076   return codep [bytes_before_imm];
17077 }
17078
17079 static void
17080 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
17081 {
17082   const char **names;
17083
17084   if (reg == -1 && modrm.mod != 3)
17085     {
17086       OP_E_memory (bytemode, sizeflag);
17087       return;
17088     }
17089   else
17090     {
17091       if (reg == -1)
17092         {
17093           reg = modrm.rm;
17094           USED_REX (REX_B);
17095           if (rex & REX_B)
17096             reg += 8;
17097         }
17098       else if (reg > 7 && address_mode != mode_64bit)
17099         BadOp ();
17100     }
17101
17102   switch (vex.length)
17103     {
17104     case 128:
17105       names = names_xmm;
17106       break;
17107     case 256:
17108       names = names_ymm;
17109       break;
17110     default:
17111       abort ();
17112     }
17113   oappend (names[reg]);
17114 }
17115
17116 static void
17117 OP_EX_VexImmW (int bytemode, int sizeflag)
17118 {
17119   int reg = -1;
17120   static unsigned char vex_imm8;
17121
17122   if (vex_w_done == 0)
17123     {
17124       vex_w_done = 1;
17125
17126       /* Skip mod/rm byte.  */
17127       MODRM_CHECK;
17128       codep++;
17129
17130       vex_imm8 = get_vex_imm8 (sizeflag, 0);
17131
17132       if (vex.w)
17133           reg = vex_imm8 >> 4;
17134
17135       OP_EX_VexReg (bytemode, sizeflag, reg);
17136     }
17137   else if (vex_w_done == 1)
17138     {
17139       vex_w_done = 2;
17140
17141       if (!vex.w)
17142           reg = vex_imm8 >> 4;
17143
17144       OP_EX_VexReg (bytemode, sizeflag, reg);
17145     }
17146   else
17147     {
17148       /* Output the imm8 directly.  */
17149       scratchbuf[0] = '$';
17150       print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
17151       oappend_maybe_intel (scratchbuf);
17152       scratchbuf[0] = '\0';
17153       codep++;
17154     }
17155 }
17156
17157 static void
17158 OP_Vex_2src (int bytemode, int sizeflag)
17159 {
17160   if (modrm.mod == 3)
17161     {
17162       int reg = modrm.rm;
17163       USED_REX (REX_B);
17164       if (rex & REX_B)
17165         reg += 8;
17166       oappend (names_xmm[reg]);
17167     }
17168   else
17169     {
17170       if (intel_syntax
17171           && (bytemode == v_mode || bytemode == v_swap_mode))
17172         {
17173           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
17174           used_prefixes |= (prefixes & PREFIX_DATA);
17175         }
17176       OP_E (bytemode, sizeflag);
17177     }
17178 }
17179
17180 static void
17181 OP_Vex_2src_1 (int bytemode, int sizeflag)
17182 {
17183   if (modrm.mod == 3)
17184     {
17185       /* Skip mod/rm byte.   */
17186       MODRM_CHECK;
17187       codep++;
17188     }
17189
17190   if (vex.w)
17191     oappend (names_xmm[vex.register_specifier]);
17192   else
17193     OP_Vex_2src (bytemode, sizeflag);
17194 }
17195
17196 static void
17197 OP_Vex_2src_2 (int bytemode, int sizeflag)
17198 {
17199   if (vex.w)
17200     OP_Vex_2src (bytemode, sizeflag);
17201   else
17202     oappend (names_xmm[vex.register_specifier]);
17203 }
17204
17205 static void
17206 OP_EX_VexW (int bytemode, int sizeflag)
17207 {
17208   int reg = -1;
17209
17210   if (!vex_w_done)
17211     {
17212       vex_w_done = 1;
17213
17214       /* Skip mod/rm byte.  */
17215       MODRM_CHECK;
17216       codep++;
17217
17218       if (vex.w)
17219         reg = get_vex_imm8 (sizeflag, 0) >> 4;
17220     }
17221   else
17222     {
17223       if (!vex.w)
17224         reg = get_vex_imm8 (sizeflag, 1) >> 4;
17225     }
17226
17227   OP_EX_VexReg (bytemode, sizeflag, reg);
17228 }
17229
17230 static void
17231 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,
17232              int sizeflag ATTRIBUTE_UNUSED)
17233 {
17234   /* Skip the immediate byte and check for invalid bits.  */
17235   FETCH_DATA (the_info, codep + 1);
17236   if (*codep++ & 0xf)
17237     BadOp ();
17238 }
17239
17240 static void
17241 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17242 {
17243   int reg;
17244   const char **names;
17245
17246   FETCH_DATA (the_info, codep + 1);
17247   reg = *codep++;
17248
17249   if (bytemode != x_mode)
17250     abort ();
17251
17252   if (reg & 0xf)
17253       BadOp ();
17254
17255   reg >>= 4;
17256   if (reg > 7 && address_mode != mode_64bit)
17257     BadOp ();
17258
17259   switch (vex.length)
17260     {
17261     case 128:
17262       names = names_xmm;
17263       break;
17264     case 256:
17265       names = names_ymm;
17266       break;
17267     default:
17268       abort ();
17269     }
17270   oappend (names[reg]);
17271 }
17272
17273 static void
17274 OP_XMM_VexW (int bytemode, int sizeflag)
17275 {
17276   /* Turn off the REX.W bit since it is used for swapping operands
17277      now.  */
17278   rex &= ~REX_W;
17279   OP_XMM (bytemode, sizeflag);
17280 }
17281
17282 static void
17283 OP_EX_Vex (int bytemode, int sizeflag)
17284 {
17285   if (modrm.mod != 3)
17286     {
17287       if (vex.register_specifier != 0)
17288         BadOp ();
17289       need_vex_reg = 0;
17290     }
17291   OP_EX (bytemode, sizeflag);
17292 }
17293
17294 static void
17295 OP_XMM_Vex (int bytemode, int sizeflag)
17296 {
17297   if (modrm.mod != 3)
17298     {
17299       if (vex.register_specifier != 0)
17300         BadOp ();
17301       need_vex_reg = 0;
17302     }
17303   OP_XMM (bytemode, sizeflag);
17304 }
17305
17306 static void
17307 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17308 {
17309   switch (vex.length)
17310     {
17311     case 128:
17312       mnemonicendp = stpcpy (obuf, "vzeroupper");
17313       break;
17314     case 256:
17315       mnemonicendp = stpcpy (obuf, "vzeroall");
17316       break;
17317     default:
17318       abort ();
17319     }
17320 }
17321
17322 static struct op vex_cmp_op[] =
17323 {
17324   { STRING_COMMA_LEN ("eq") },
17325   { STRING_COMMA_LEN ("lt") },
17326   { STRING_COMMA_LEN ("le") },
17327   { STRING_COMMA_LEN ("unord") },
17328   { STRING_COMMA_LEN ("neq") },
17329   { STRING_COMMA_LEN ("nlt") },
17330   { STRING_COMMA_LEN ("nle") },
17331   { STRING_COMMA_LEN ("ord") },
17332   { STRING_COMMA_LEN ("eq_uq") },
17333   { STRING_COMMA_LEN ("nge") },
17334   { STRING_COMMA_LEN ("ngt") },
17335   { STRING_COMMA_LEN ("false") },
17336   { STRING_COMMA_LEN ("neq_oq") },
17337   { STRING_COMMA_LEN ("ge") },
17338   { STRING_COMMA_LEN ("gt") },
17339   { STRING_COMMA_LEN ("true") },
17340   { STRING_COMMA_LEN ("eq_os") },
17341   { STRING_COMMA_LEN ("lt_oq") },
17342   { STRING_COMMA_LEN ("le_oq") },
17343   { STRING_COMMA_LEN ("unord_s") },
17344   { STRING_COMMA_LEN ("neq_us") },
17345   { STRING_COMMA_LEN ("nlt_uq") },
17346   { STRING_COMMA_LEN ("nle_uq") },
17347   { STRING_COMMA_LEN ("ord_s") },
17348   { STRING_COMMA_LEN ("eq_us") },
17349   { STRING_COMMA_LEN ("nge_uq") },
17350   { STRING_COMMA_LEN ("ngt_uq") },
17351   { STRING_COMMA_LEN ("false_os") },
17352   { STRING_COMMA_LEN ("neq_os") },
17353   { STRING_COMMA_LEN ("ge_oq") },
17354   { STRING_COMMA_LEN ("gt_oq") },
17355   { STRING_COMMA_LEN ("true_us") },
17356 };
17357
17358 static void
17359 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17360 {
17361   unsigned int cmp_type;
17362
17363   FETCH_DATA (the_info, codep + 1);
17364   cmp_type = *codep++ & 0xff;
17365   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
17366     {
17367       char suffix [3];
17368       char *p = mnemonicendp - 2;
17369       suffix[0] = p[0];
17370       suffix[1] = p[1];
17371       suffix[2] = '\0';
17372       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
17373       mnemonicendp += vex_cmp_op[cmp_type].len;
17374     }
17375   else
17376     {
17377       /* We have a reserved extension byte.  Output it directly.  */
17378       scratchbuf[0] = '$';
17379       print_operand_value (scratchbuf + 1, 1, cmp_type);
17380       oappend_maybe_intel (scratchbuf);
17381       scratchbuf[0] = '\0';
17382     }
17383 }
17384
17385 static void
17386 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
17387              int sizeflag ATTRIBUTE_UNUSED)
17388 {
17389   unsigned int cmp_type;
17390
17391   if (!vex.evex)
17392     abort ();
17393
17394   FETCH_DATA (the_info, codep + 1);
17395   cmp_type = *codep++ & 0xff;
17396   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
17397      If it's the case, print suffix, otherwise - print the immediate.  */
17398   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
17399       && cmp_type != 3
17400       && cmp_type != 7)
17401     {
17402       char suffix [3];
17403       char *p = mnemonicendp - 2;
17404
17405       /* vpcmp* can have both one- and two-lettered suffix.  */
17406       if (p[0] == 'p')
17407         {
17408           p++;
17409           suffix[0] = p[0];
17410           suffix[1] = '\0';
17411         }
17412       else
17413         {
17414           suffix[0] = p[0];
17415           suffix[1] = p[1];
17416           suffix[2] = '\0';
17417         }
17418
17419       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
17420       mnemonicendp += simd_cmp_op[cmp_type].len;
17421     }
17422   else
17423     {
17424       /* We have a reserved extension byte.  Output it directly.  */
17425       scratchbuf[0] = '$';
17426       print_operand_value (scratchbuf + 1, 1, cmp_type);
17427       oappend_maybe_intel (scratchbuf);
17428       scratchbuf[0] = '\0';
17429     }
17430 }
17431
17432 static const struct op pclmul_op[] =
17433 {
17434   { STRING_COMMA_LEN ("lql") },
17435   { STRING_COMMA_LEN ("hql") },
17436   { STRING_COMMA_LEN ("lqh") },
17437   { STRING_COMMA_LEN ("hqh") }
17438 };
17439
17440 static void
17441 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
17442               int sizeflag ATTRIBUTE_UNUSED)
17443 {
17444   unsigned int pclmul_type;
17445
17446   FETCH_DATA (the_info, codep + 1);
17447   pclmul_type = *codep++ & 0xff;
17448   switch (pclmul_type)
17449     {
17450     case 0x10:
17451       pclmul_type = 2;
17452       break;
17453     case 0x11:
17454       pclmul_type = 3;
17455       break;
17456     default:
17457       break;
17458     }
17459   if (pclmul_type < ARRAY_SIZE (pclmul_op))
17460     {
17461       char suffix [4];
17462       char *p = mnemonicendp - 3;
17463       suffix[0] = p[0];
17464       suffix[1] = p[1];
17465       suffix[2] = p[2];
17466       suffix[3] = '\0';
17467       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
17468       mnemonicendp += pclmul_op[pclmul_type].len;
17469     }
17470   else
17471     {
17472       /* We have a reserved extension byte.  Output it directly.  */
17473       scratchbuf[0] = '$';
17474       print_operand_value (scratchbuf + 1, 1, pclmul_type);
17475       oappend_maybe_intel (scratchbuf);
17476       scratchbuf[0] = '\0';
17477     }
17478 }
17479
17480 static void
17481 MOVBE_Fixup (int bytemode, int sizeflag)
17482 {
17483   /* Add proper suffix to "movbe".  */
17484   char *p = mnemonicendp;
17485
17486   switch (bytemode)
17487     {
17488     case v_mode:
17489       if (intel_syntax)
17490         goto skip;
17491
17492       USED_REX (REX_W);
17493       if (sizeflag & SUFFIX_ALWAYS)
17494         {
17495           if (rex & REX_W)
17496             *p++ = 'q';
17497           else
17498             {
17499               if (sizeflag & DFLAG)
17500                 *p++ = 'l';
17501               else
17502                 *p++ = 'w';
17503               used_prefixes |= (prefixes & PREFIX_DATA);
17504             }
17505         }
17506       break;
17507     default:
17508       oappend (INTERNAL_DISASSEMBLER_ERROR);
17509       break;
17510     }
17511   mnemonicendp = p;
17512   *p = '\0';
17513
17514 skip:
17515   OP_M (bytemode, sizeflag);
17516 }
17517
17518 static void
17519 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17520 {
17521   int reg;
17522   const char **names;
17523
17524   /* Skip mod/rm byte.  */
17525   MODRM_CHECK;
17526   codep++;
17527
17528   if (vex.w)
17529     names = names64;
17530   else
17531     names = names32;
17532
17533   reg = modrm.rm;
17534   USED_REX (REX_B);
17535   if (rex & REX_B)
17536     reg += 8;
17537
17538   oappend (names[reg]);
17539 }
17540
17541 static void
17542 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17543 {
17544   const char **names;
17545
17546   if (vex.w)
17547     names = names64;
17548   else
17549     names = names32;
17550
17551   oappend (names[vex.register_specifier]);
17552 }
17553
17554 static void
17555 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17556 {
17557   if (!vex.evex
17558       || (bytemode != mask_mode && bytemode != mask_bd_mode))
17559     abort ();
17560
17561   USED_REX (REX_R);
17562   if ((rex & REX_R) != 0 || !vex.r)
17563     {
17564       BadOp ();
17565       return;
17566     }
17567
17568   oappend (names_mask [modrm.reg]);
17569 }
17570
17571 static void
17572 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17573 {
17574   if (!vex.evex
17575       || (bytemode != evex_rounding_mode
17576           && bytemode != evex_sae_mode))
17577     abort ();
17578   if (modrm.mod == 3 && vex.b)
17579     switch (bytemode)
17580       {
17581       case evex_rounding_mode:
17582         oappend (names_rounding[vex.ll]);
17583         break;
17584       case evex_sae_mode:
17585         oappend ("{sae}");
17586         break;
17587       default:
17588         break;
17589       }
17590 }