opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2017 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "dis-asm.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40
  41 #include <setjmp.h>
  42
  43 static int print_insn (bfd_vma, disassemble_info *);
  44 static void dofloat (int);
  45 static void OP_ST (int, int);
  46 static void OP_STi (int, int);
  47 static int putop (const char *, int);
  48 static void oappend (const char *);
  49 static void append_seg (void);
  50 static void OP_indirE (int, int);
  51 static void print_operand_value (char *, int, bfd_vma);
  52 static void OP_E_register (int, int);
  53 static void OP_E_memory (int, int);
  54 static void print_displacement (char *, bfd_vma);
  55 static void OP_E (int, int);
  56 static void OP_G (int, int);
  57 static bfd_vma get64 (void);
  58 static bfd_signed_vma get32 (void);
  59 static bfd_signed_vma get32s (void);
  60 static int get16 (void);
  61 static void set_op (bfd_vma, int);
  62 static void OP_Skip_MODRM (int, int);
  63 static void OP_REG (int, int);
  64 static void OP_IMREG (int, int);
  65 static void OP_I (int, int);
  66 static void OP_I64 (int, int);
  67 static void OP_sI (int, int);
  68 static void OP_J (int, int);
  69 static void OP_SEG (int, int);
  70 static void OP_DIR (int, int);
  71 static void OP_OFF (int, int);
  72 static void OP_OFF64 (int, int);
  73 static void ptr_reg (int, int);
  74 static void OP_ESreg (int, int);
  75 static void OP_DSreg (int, int);
  76 static void OP_C (int, int);
  77 static void OP_D (int, int);
  78 static void OP_T (int, int);
  79 static void OP_R (int, int);
  80 static void OP_MMX (int, int);
  81 static void OP_XMM (int, int);
  82 static void OP_EM (int, int);
  83 static void OP_EX (int, int);
  84 static void OP_EMC (int,int);
  85 static void OP_MXC (int,int);
  86 static void OP_MS (int, int);
  87 static void OP_XS (int, int);
  88 static void OP_M (int, int);
  89 static void OP_VEX (int, int);
  90 static void OP_EX_Vex (int, int);
  91 static void OP_EX_VexW (int, int);
  92 static void OP_EX_VexImmW (int, int);
  93 static void OP_XMM_Vex (int, int);
  94 static void OP_XMM_VexW (int, int);
  95 static void OP_Rounding (int, int);
  96 static void OP_REG_VexI4 (int, int);
  97 static void PCLMUL_Fixup (int, int);
  98 static void VEXI4_Fixup (int, int);
  99 static void VZERO_Fixup (int, int);
 100 static void VCMP_Fixup (int, int);
 101 static void VPCMP_Fixup (int, int);
 102 static void OP_0f07 (int, int);
 103 static void OP_Monitor (int, int);
 104 static void OP_Mwait (int, int);
 105 static void OP_Mwaitx (int, int);
 106 static void NOP_Fixup1 (int, int);
 107 static void NOP_Fixup2 (int, int);
 108 static void OP_3DNowSuffix (int, int);
 109 static void CMP_Fixup (int, int);
 110 static void BadOp (void);
 111 static void REP_Fixup (int, int);
 112 static void BND_Fixup (int, int);
 113 static void HLE_Fixup1 (int, int);
 114 static void HLE_Fixup2 (int, int);
 115 static void HLE_Fixup3 (int, int);
 116 static void CMPXCHG8B_Fixup (int, int);
 117 static void XMM_Fixup (int, int);
 118 static void CRC32_Fixup (int, int);
 119 static void FXSAVE_Fixup (int, int);
 120 static void PCMPESTR_Fixup (int, int);
 121 static void OP_LWPCB_E (int, int);
 122 static void OP_LWP_E (int, int);
 123 static void OP_Vex_2src_1 (int, int);
 124 static void OP_Vex_2src_2 (int, int);
 125
 126 static void MOVBE_Fixup (int, int);
 127
 128 static void OP_Mask (int, int);
 129
 130 struct dis_private {
 131   /* Points to first byte not fetched.  */
 132   bfd_byte *max_fetched;
 133   bfd_byte the_buffer[MAX_MNEM_SIZE];
 134   bfd_vma insn_start;
 135   int orig_sizeflag;
 136   OPCODES_SIGJMP_BUF bailout;
 137 };
 138
 139 enum address_mode
 140 {
 141   mode_16bit,
 142   mode_32bit,
 143   mode_64bit
 144 };
 145
 146 enum address_mode address_mode;
 147
 148 /* Flags for the prefixes for the current instruction.  See below.  */
 149 static int prefixes;
 150
 151 /* REX prefix the current instruction.  See below.  */
 152 static int rex;
 153 /* Bits of REX we've already used.  */
 154 static int rex_used;
 155 /* REX bits in original REX prefix ignored.  */
 156 static int rex_ignored;
 157 /* Mark parts used in the REX prefix.  When we are testing for
 158    empty prefix (for 8bit register REX extension), just mask it
 159    out.  Otherwise test for REX bit is excuse for existence of REX
 160    only in case value is nonzero.  */
 161 #define USED_REX(value)                                 \
 162   {                                                     \
 163     if (value)                                          \
 164       {                                                 \
 165         if ((rex & value))                              \
 166           rex_used |= (value) | REX_OPCODE;             \
 167       }                                                 \
 168     else                                                \
 169       rex_used |= REX_OPCODE;                           \
 170   }
 171
 172 /* Flags for prefixes which we somehow handled when printing the
 173    current instruction.  */
 174 static int used_prefixes;
 175
 176 /* Flags stored in PREFIXES.  */
 177 #define PREFIX_REPZ 1
 178 #define PREFIX_REPNZ 2
 179 #define PREFIX_LOCK 4
 180 #define PREFIX_CS 8
 181 #define PREFIX_SS 0x10
 182 #define PREFIX_DS 0x20
 183 #define PREFIX_ES 0x40
 184 #define PREFIX_FS 0x80
 185 #define PREFIX_GS 0x100
 186 #define PREFIX_DATA 0x200
 187 #define PREFIX_ADDR 0x400
 188 #define PREFIX_FWAIT 0x800
 189
 190 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 191    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 192    on error.  */
 193 #define FETCH_DATA(info, addr) \
 194   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 195    ? 1 : fetch_data ((info), (addr)))
 196
 197 static int
 198 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 199 {
 200   int status;
 201   struct dis_private *priv = (struct dis_private *) info->private_data;
 202   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 203
 204   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 205     status = (*info->read_memory_func) (start,
 206                                         priv->max_fetched,
 207                                         addr - priv->max_fetched,
 208                                         info);
 209   else
 210     status = -1;
 211   if (status != 0)
 212     {
 213       /* If we did manage to read at least one byte, then
 214          print_insn_i386 will do something sensible.  Otherwise, print
 215          an error.  We do that here because this is where we know
 216          STATUS.  */
 217       if (priv->max_fetched == priv->the_buffer)
 218         (*info->memory_error_func) (status, start, info);
 219       OPCODES_SIGLONGJMP (priv->bailout, 1);
 220     }
 221   else
 222     priv->max_fetched = addr;
 223   return 1;
 224 }
 225
 226 /* Possible values for prefix requirement.  */
 227 #define PREFIX_IGNORED_SHIFT    16
 228 #define PREFIX_IGNORED_REPZ     (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
 229 #define PREFIX_IGNORED_REPNZ    (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
 230 #define PREFIX_IGNORED_DATA     (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
 231 #define PREFIX_IGNORED_ADDR     (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
 232 #define PREFIX_IGNORED_LOCK     (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
 233
 234 /* Opcode prefixes.  */
 235 #define PREFIX_OPCODE           (PREFIX_REPZ \
 236                                  | PREFIX_REPNZ \
 237                                  | PREFIX_DATA)
 238
 239 /* Prefixes ignored.  */
 240 #define PREFIX_IGNORED          (PREFIX_IGNORED_REPZ \
 241                                  | PREFIX_IGNORED_REPNZ \
 242                                  | PREFIX_IGNORED_DATA)
 243
 244 #define XX { NULL, 0 }
 245 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
 246
 247 #define Eb { OP_E, b_mode }
 248 #define Ebnd { OP_E, bnd_mode }
 249 #define EbS { OP_E, b_swap_mode }
 250 #define Ev { OP_E, v_mode }
 251 #define Ev_bnd { OP_E, v_bnd_mode }
 252 #define EvS { OP_E, v_swap_mode }
 253 #define Ed { OP_E, d_mode }
 254 #define Edq { OP_E, dq_mode }
 255 #define Edqw { OP_E, dqw_mode }
 256 #define Edqb { OP_E, dqb_mode }
 257 #define Edb { OP_E, db_mode }
 258 #define Edw { OP_E, dw_mode }
 259 #define Edqd { OP_E, dqd_mode }
 260 #define Eq { OP_E, q_mode }
 261 #define indirEv { OP_indirE, indir_v_mode }
 262 #define indirEp { OP_indirE, f_mode }
 263 #define stackEv { OP_E, stack_v_mode }
 264 #define Em { OP_E, m_mode }
 265 #define Ew { OP_E, w_mode }
 266 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 267 #define Ma { OP_M, a_mode }
 268 #define Mb { OP_M, b_mode }
 269 #define Md { OP_M, d_mode }
 270 #define Mo { OP_M, o_mode }
 271 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 272 #define Mq { OP_M, q_mode }
 273 #define Mx { OP_M, x_mode }
 274 #define Mxmm { OP_M, xmm_mode }
 275 #define Gb { OP_G, b_mode }
 276 #define Gbnd { OP_G, bnd_mode }
 277 #define Gv { OP_G, v_mode }
 278 #define Gd { OP_G, d_mode }
 279 #define Gdq { OP_G, dq_mode }
 280 #define Gm { OP_G, m_mode }
 281 #define Gw { OP_G, w_mode }
 282 #define Rd { OP_R, d_mode }
 283 #define Rdq { OP_R, dq_mode }
 284 #define Rm { OP_R, m_mode }
 285 #define Ib { OP_I, b_mode }
 286 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 287 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 288 #define Iv { OP_I, v_mode }
 289 #define sIv { OP_sI, v_mode }
 290 #define Iq { OP_I, q_mode }
 291 #define Iv64 { OP_I64, v_mode }
 292 #define Iw { OP_I, w_mode }
 293 #define I1 { OP_I, const_1_mode }
 294 #define Jb { OP_J, b_mode }
 295 #define Jv { OP_J, v_mode }
 296 #define Cm { OP_C, m_mode }
 297 #define Dm { OP_D, m_mode }
 298 #define Td { OP_T, d_mode }
 299 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 300
 301 #define RMeAX { OP_REG, eAX_reg }
 302 #define RMeBX { OP_REG, eBX_reg }
 303 #define RMeCX { OP_REG, eCX_reg }
 304 #define RMeDX { OP_REG, eDX_reg }
 305 #define RMeSP { OP_REG, eSP_reg }
 306 #define RMeBP { OP_REG, eBP_reg }
 307 #define RMeSI { OP_REG, eSI_reg }
 308 #define RMeDI { OP_REG, eDI_reg }
 309 #define RMrAX { OP_REG, rAX_reg }
 310 #define RMrBX { OP_REG, rBX_reg }
 311 #define RMrCX { OP_REG, rCX_reg }
 312 #define RMrDX { OP_REG, rDX_reg }
 313 #define RMrSP { OP_REG, rSP_reg }
 314 #define RMrBP { OP_REG, rBP_reg }
 315 #define RMrSI { OP_REG, rSI_reg }
 316 #define RMrDI { OP_REG, rDI_reg }
 317 #define RMAL { OP_REG, al_reg }
 318 #define RMCL { OP_REG, cl_reg }
 319 #define RMDL { OP_REG, dl_reg }
 320 #define RMBL { OP_REG, bl_reg }
 321 #define RMAH { OP_REG, ah_reg }
 322 #define RMCH { OP_REG, ch_reg }
 323 #define RMDH { OP_REG, dh_reg }
 324 #define RMBH { OP_REG, bh_reg }
 325 #define RMAX { OP_REG, ax_reg }
 326 #define RMDX { OP_REG, dx_reg }
 327
 328 #define eAX { OP_IMREG, eAX_reg }
 329 #define eBX { OP_IMREG, eBX_reg }
 330 #define eCX { OP_IMREG, eCX_reg }
 331 #define eDX { OP_IMREG, eDX_reg }
 332 #define eSP { OP_IMREG, eSP_reg }
 333 #define eBP { OP_IMREG, eBP_reg }
 334 #define eSI { OP_IMREG, eSI_reg }
 335 #define eDI { OP_IMREG, eDI_reg }
 336 #define AL { OP_IMREG, al_reg }
 337 #define CL { OP_IMREG, cl_reg }
 338 #define DL { OP_IMREG, dl_reg }
 339 #define BL { OP_IMREG, bl_reg }
 340 #define AH { OP_IMREG, ah_reg }
 341 #define CH { OP_IMREG, ch_reg }
 342 #define DH { OP_IMREG, dh_reg }
 343 #define BH { OP_IMREG, bh_reg }
 344 #define AX { OP_IMREG, ax_reg }
 345 #define DX { OP_IMREG, dx_reg }
 346 #define zAX { OP_IMREG, z_mode_ax_reg }
 347 #define indirDX { OP_IMREG, indir_dx_reg }
 348
 349 #define Sw { OP_SEG, w_mode }
 350 #define Sv { OP_SEG, v_mode }
 351 #define Ap { OP_DIR, 0 }
 352 #define Ob { OP_OFF64, b_mode }
 353 #define Ov { OP_OFF64, v_mode }
 354 #define Xb { OP_DSreg, eSI_reg }
 355 #define Xv { OP_DSreg, eSI_reg }
 356 #define Xz { OP_DSreg, eSI_reg }
 357 #define Yb { OP_ESreg, eDI_reg }
 358 #define Yv { OP_ESreg, eDI_reg }
 359 #define DSBX { OP_DSreg, eBX_reg }
 360
 361 #define es { OP_REG, es_reg }
 362 #define ss { OP_REG, ss_reg }
 363 #define cs { OP_REG, cs_reg }
 364 #define ds { OP_REG, ds_reg }
 365 #define fs { OP_REG, fs_reg }
 366 #define gs { OP_REG, gs_reg }
 367
 368 #define MX { OP_MMX, 0 }
 369 #define XM { OP_XMM, 0 }
 370 #define XMScalar { OP_XMM, scalar_mode }
 371 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 372 #define XMM { OP_XMM, xmm_mode }
 373 #define XMxmmq { OP_XMM, xmmq_mode }
 374 #define EM { OP_EM, v_mode }
 375 #define EMS { OP_EM, v_swap_mode }
 376 #define EMd { OP_EM, d_mode }
 377 #define EMx { OP_EM, x_mode }
 378 #define EXw { OP_EX, w_mode }
 379 #define EXd { OP_EX, d_mode }
 380 #define EXdScalar { OP_EX, d_scalar_mode }
 381 #define EXdS { OP_EX, d_swap_mode }
 382 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
 383 #define EXq { OP_EX, q_mode }
 384 #define EXqScalar { OP_EX, q_scalar_mode }
 385 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
 386 #define EXqS { OP_EX, q_swap_mode }
 387 #define EXx { OP_EX, x_mode }
 388 #define EXxS { OP_EX, x_swap_mode }
 389 #define EXxmm { OP_EX, xmm_mode }
 390 #define EXymm { OP_EX, ymm_mode }
 391 #define EXxmmq { OP_EX, xmmq_mode }
 392 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 393 #define EXxmm_mb { OP_EX, xmm_mb_mode }
 394 #define EXxmm_mw { OP_EX, xmm_mw_mode }
 395 #define EXxmm_md { OP_EX, xmm_md_mode }
 396 #define EXxmm_mq { OP_EX, xmm_mq_mode }
 397 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
 398 #define EXxmmdw { OP_EX, xmmdw_mode }
 399 #define EXxmmqd { OP_EX, xmmqd_mode }
 400 #define EXymmq { OP_EX, ymmq_mode }
 401 #define EXVexWdq { OP_EX, vex_w_dq_mode }
 402 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 403 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 404 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 405 #define MS { OP_MS, v_mode }
 406 #define XS { OP_XS, v_mode }
 407 #define EMCq { OP_EMC, q_mode }
 408 #define MXC { OP_MXC, 0 }
 409 #define OPSUF { OP_3DNowSuffix, 0 }
 410 #define CMP { CMP_Fixup, 0 }
 411 #define XMM0 { XMM_Fixup, 0 }
 412 #define FXSAVE { FXSAVE_Fixup, 0 }
 413 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
 414 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
 415
 416 #define Vex { OP_VEX, vex_mode }
 417 #define VexScalar { OP_VEX, vex_scalar_mode }
 418 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 419 #define Vex128 { OP_VEX, vex128_mode }
 420 #define Vex256 { OP_VEX, vex256_mode }
 421 #define VexGdq { OP_VEX, dq_mode }
 422 #define VexI4 { VEXI4_Fixup, 0}
 423 #define EXdVex { OP_EX_Vex, d_mode }
 424 #define EXdVexS { OP_EX_Vex, d_swap_mode }
 425 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
 426 #define EXqVex { OP_EX_Vex, q_mode }
 427 #define EXqVexS { OP_EX_Vex, q_swap_mode }
 428 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
 429 #define EXVexW { OP_EX_VexW, x_mode }
 430 #define EXdVexW { OP_EX_VexW, d_mode }
 431 #define EXqVexW { OP_EX_VexW, q_mode }
 432 #define EXVexImmW { OP_EX_VexImmW, x_mode }
 433 #define XMVex { OP_XMM_Vex, 0 }
 434 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
 435 #define XMVexW { OP_XMM_VexW, 0 }
 436 #define XMVexI4 { OP_REG_VexI4, x_mode }
 437 #define PCLMUL { PCLMUL_Fixup, 0 }
 438 #define VZERO { VZERO_Fixup, 0 }
 439 #define VCMP { VCMP_Fixup, 0 }
 440 #define VPCMP { VPCMP_Fixup, 0 }
 441
 442 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 443 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 444
 445 #define XMask { OP_Mask, mask_mode }
 446 #define MaskG { OP_G, mask_mode }
 447 #define MaskE { OP_E, mask_mode }
 448 #define MaskBDE { OP_E, mask_bd_mode }
 449 #define MaskR { OP_R, mask_mode }
 450 #define MaskVex { OP_VEX, mask_mode }
 451
 452 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 453 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
 454 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 455 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
 456
 457 /* Used handle "rep" prefix for string instructions.  */
 458 #define Xbr { REP_Fixup, eSI_reg }
 459 #define Xvr { REP_Fixup, eSI_reg }
 460 #define Ybr { REP_Fixup, eDI_reg }
 461 #define Yvr { REP_Fixup, eDI_reg }
 462 #define Yzr { REP_Fixup, eDI_reg }
 463 #define indirDXr { REP_Fixup, indir_dx_reg }
 464 #define ALr { REP_Fixup, al_reg }
 465 #define eAXr { REP_Fixup, eAX_reg }
 466
 467 /* Used handle HLE prefix for lockable instructions.  */
 468 #define Ebh1 { HLE_Fixup1, b_mode }
 469 #define Evh1 { HLE_Fixup1, v_mode }
 470 #define Ebh2 { HLE_Fixup2, b_mode }
 471 #define Evh2 { HLE_Fixup2, v_mode }
 472 #define Ebh3 { HLE_Fixup3, b_mode }
 473 #define Evh3 { HLE_Fixup3, v_mode }
 474
 475 #define BND { BND_Fixup, 0 }
 476
 477 #define cond_jump_flag { NULL, cond_jump_mode }
 478 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 479
 480 /* bits in sizeflag */
 481 #define SUFFIX_ALWAYS 4
 482 #define AFLAG 2
 483 #define DFLAG 1
 484
 485 enum
 486 {
 487   /* byte operand */
 488   b_mode = 1,
 489   /* byte operand with operand swapped */
 490   b_swap_mode,
 491   /* byte operand, sign extend like 'T' suffix */
 492   b_T_mode,
 493   /* operand size depends on prefixes */
 494   v_mode,
 495   /* operand size depends on prefixes with operand swapped */
 496   v_swap_mode,
 497   /* word operand */
 498   w_mode,
 499   /* double word operand  */
 500   d_mode,
 501   /* double word operand with operand swapped */
 502   d_swap_mode,
 503   /* quad word operand */
 504   q_mode,
 505   /* quad word operand with operand swapped */
 506   q_swap_mode,
 507   /* ten-byte operand */
 508   t_mode,
 509   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 510      broadcast enabled.  */
 511   x_mode,
 512   /* Similar to x_mode, but with different EVEX mem shifts.  */
 513   evex_x_gscat_mode,
 514   /* Similar to x_mode, but with disabled broadcast.  */
 515   evex_x_nobcst_mode,
 516   /* Similar to x_mode, but with operands swapped and disabled broadcast
 517      in EVEX.  */
 518   x_swap_mode,
 519   /* 16-byte XMM operand */
 520   xmm_mode,
 521   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 522      memory operand (depending on vector length).  Broadcast isn't
 523      allowed.  */
 524   xmmq_mode,
 525   /* Same as xmmq_mode, but broadcast is allowed.  */
 526   evex_half_bcst_xmmq_mode,
 527   /* XMM register or byte memory operand */
 528   xmm_mb_mode,
 529   /* XMM register or word memory operand */
 530   xmm_mw_mode,
 531   /* XMM register or double word memory operand */
 532   xmm_md_mode,
 533   /* XMM register or quad word memory operand */
 534   xmm_mq_mode,
 535   /* XMM register or double/quad word memory operand, depending on
 536      VEX.W.  */
 537   xmm_mdq_mode,
 538   /* 16-byte XMM, word, double word or quad word operand.  */
 539   xmmdw_mode,
 540   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 541   xmmqd_mode,
 542   /* 32-byte YMM operand */
 543   ymm_mode,
 544   /* quad word, ymmword or zmmword memory operand.  */
 545   ymmq_mode,
 546   /* 32-byte YMM or 16-byte word operand */
 547   ymmxmm_mode,
 548   /* d_mode in 32bit, q_mode in 64bit mode.  */
 549   m_mode,
 550   /* pair of v_mode operands */
 551   a_mode,
 552   cond_jump_mode,
 553   loop_jcxz_mode,
 554   v_bnd_mode,
 555   /* operand size depends on REX prefixes.  */
 556   dq_mode,
 557   /* registers like dq_mode, memory like w_mode.  */
 558   dqw_mode,
 559   bnd_mode,
 560   /* 4- or 6-byte pointer operand */
 561   f_mode,
 562   const_1_mode,
 563   /* v_mode for indirect branch opcodes.  */
 564   indir_v_mode,
 565   /* v_mode for stack-related opcodes.  */
 566   stack_v_mode,
 567   /* non-quad operand size depends on prefixes */
 568   z_mode,
 569   /* 16-byte operand */
 570   o_mode,
 571   /* registers like dq_mode, memory like b_mode.  */
 572   dqb_mode,
 573   /* registers like d_mode, memory like b_mode.  */
 574   db_mode,
 575   /* registers like d_mode, memory like w_mode.  */
 576   dw_mode,
 577   /* registers like dq_mode, memory like d_mode.  */
 578   dqd_mode,
 579   /* normal vex mode */
 580   vex_mode,
 581   /* 128bit vex mode */
 582   vex128_mode,
 583   /* 256bit vex mode */
 584   vex256_mode,
 585   /* operand size depends on the VEX.W bit.  */
 586   vex_w_dq_mode,
 587
 588   /* Similar to vex_w_dq_mode, with VSIB dword indices.  */
 589   vex_vsib_d_w_dq_mode,
 590   /* Similar to vex_vsib_d_w_dq_mode, with smaller memory.  */
 591   vex_vsib_d_w_d_mode,
 592   /* Similar to vex_w_dq_mode, with VSIB qword indices.  */
 593   vex_vsib_q_w_dq_mode,
 594   /* Similar to vex_vsib_q_w_dq_mode, with smaller memory.  */
 595   vex_vsib_q_w_d_mode,
 596
 597   /* scalar, ignore vector length.  */
 598   scalar_mode,
 599   /* like d_mode, ignore vector length.  */
 600   d_scalar_mode,
 601   /* like d_swap_mode, ignore vector length.  */
 602   d_scalar_swap_mode,
 603   /* like q_mode, ignore vector length.  */
 604   q_scalar_mode,
 605   /* like q_swap_mode, ignore vector length.  */
 606   q_scalar_swap_mode,
 607   /* like vex_mode, ignore vector length.  */
 608   vex_scalar_mode,
 609   /* like vex_w_dq_mode, ignore vector length.  */
 610   vex_scalar_w_dq_mode,
 611
 612   /* Static rounding.  */
 613   evex_rounding_mode,
 614   /* Supress all exceptions.  */
 615   evex_sae_mode,
 616
 617   /* Mask register operand.  */
 618   mask_mode,
 619   /* Mask register operand.  */
 620   mask_bd_mode,
 621
 622   es_reg,
 623   cs_reg,
 624   ss_reg,
 625   ds_reg,
 626   fs_reg,
 627   gs_reg,
 628
 629   eAX_reg,
 630   eCX_reg,
 631   eDX_reg,
 632   eBX_reg,
 633   eSP_reg,
 634   eBP_reg,
 635   eSI_reg,
 636   eDI_reg,
 637
 638   al_reg,
 639   cl_reg,
 640   dl_reg,
 641   bl_reg,
 642   ah_reg,
 643   ch_reg,
 644   dh_reg,
 645   bh_reg,
 646
 647   ax_reg,
 648   cx_reg,
 649   dx_reg,
 650   bx_reg,
 651   sp_reg,
 652   bp_reg,
 653   si_reg,
 654   di_reg,
 655
 656   rAX_reg,
 657   rCX_reg,
 658   rDX_reg,
 659   rBX_reg,
 660   rSP_reg,
 661   rBP_reg,
 662   rSI_reg,
 663   rDI_reg,
 664
 665   z_mode_ax_reg,
 666   indir_dx_reg
 667 };
 668
 669 enum
 670 {
 671   FLOATCODE = 1,
 672   USE_REG_TABLE,
 673   USE_MOD_TABLE,
 674   USE_RM_TABLE,
 675   USE_PREFIX_TABLE,
 676   USE_X86_64_TABLE,
 677   USE_3BYTE_TABLE,
 678   USE_XOP_8F_TABLE,
 679   USE_VEX_C4_TABLE,
 680   USE_VEX_C5_TABLE,
 681   USE_VEX_LEN_TABLE,
 682   USE_VEX_W_TABLE,
 683   USE_EVEX_TABLE
 684 };
 685
 686 #define FLOAT                   NULL, { { NULL, FLOATCODE } }, 0
 687
 688 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }, 0
 689 #define DIS386_PREFIX(T, I, P)          NULL, { { NULL, (T)}, { NULL,  (I) } }, P
 690 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 691 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 692 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 693 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 694 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 695 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 696 #define THREE_BYTE_TABLE_PREFIX(I, P)   DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
 697 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 698 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 699 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 700 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 701 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 702 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 703
 704 enum
 705 {
 706   REG_80 = 0,
 707   REG_81,
 708   REG_83,
 709   REG_8F,
 710   REG_C0,
 711   REG_C1,
 712   REG_C6,
 713   REG_C7,
 714   REG_D0,
 715   REG_D1,
 716   REG_D2,
 717   REG_D3,
 718   REG_F6,
 719   REG_F7,
 720   REG_FE,
 721   REG_FF,
 722   REG_0F00,
 723   REG_0F01,
 724   REG_0F0D,
 725   REG_0F18,
 726   REG_0F71,
 727   REG_0F72,
 728   REG_0F73,
 729   REG_0FA6,
 730   REG_0FA7,
 731   REG_0FAE,
 732   REG_0FBA,
 733   REG_0FC7,
 734   REG_VEX_0F71,
 735   REG_VEX_0F72,
 736   REG_VEX_0F73,
 737   REG_VEX_0FAE,
 738   REG_VEX_0F38F3,
 739   REG_XOP_LWPCB,
 740   REG_XOP_LWP,
 741   REG_XOP_TBM_01,
 742   REG_XOP_TBM_02,
 743
 744   REG_EVEX_0F71,
 745   REG_EVEX_0F72,
 746   REG_EVEX_0F73,
 747   REG_EVEX_0F38C6,
 748   REG_EVEX_0F38C7
 749 };
 750
 751 enum
 752 {
 753   MOD_8D = 0,
 754   MOD_C6_REG_7,
 755   MOD_C7_REG_7,
 756   MOD_FF_REG_3,
 757   MOD_FF_REG_5,
 758   MOD_0F01_REG_0,
 759   MOD_0F01_REG_1,
 760   MOD_0F01_REG_2,
 761   MOD_0F01_REG_3,
 762   MOD_0F01_REG_5,
 763   MOD_0F01_REG_7,
 764   MOD_0F12_PREFIX_0,
 765   MOD_0F13,
 766   MOD_0F16_PREFIX_0,
 767   MOD_0F17,
 768   MOD_0F18_REG_0,
 769   MOD_0F18_REG_1,
 770   MOD_0F18_REG_2,
 771   MOD_0F18_REG_3,
 772   MOD_0F18_REG_4,
 773   MOD_0F18_REG_5,
 774   MOD_0F18_REG_6,
 775   MOD_0F18_REG_7,
 776   MOD_0F1A_PREFIX_0,
 777   MOD_0F1B_PREFIX_0,
 778   MOD_0F1B_PREFIX_1,
 779   MOD_0F24,
 780   MOD_0F26,
 781   MOD_0F2B_PREFIX_0,
 782   MOD_0F2B_PREFIX_1,
 783   MOD_0F2B_PREFIX_2,
 784   MOD_0F2B_PREFIX_3,
 785   MOD_0F51,
 786   MOD_0F71_REG_2,
 787   MOD_0F71_REG_4,
 788   MOD_0F71_REG_6,
 789   MOD_0F72_REG_2,
 790   MOD_0F72_REG_4,
 791   MOD_0F72_REG_6,
 792   MOD_0F73_REG_2,
 793   MOD_0F73_REG_3,
 794   MOD_0F73_REG_6,
 795   MOD_0F73_REG_7,
 796   MOD_0FAE_REG_0,
 797   MOD_0FAE_REG_1,
 798   MOD_0FAE_REG_2,
 799   MOD_0FAE_REG_3,
 800   MOD_0FAE_REG_4,
 801   MOD_0FAE_REG_5,
 802   MOD_0FAE_REG_6,
 803   MOD_0FAE_REG_7,
 804   MOD_0FB2,
 805   MOD_0FB4,
 806   MOD_0FB5,
 807   MOD_0FC3,
 808   MOD_0FC7_REG_3,
 809   MOD_0FC7_REG_4,
 810   MOD_0FC7_REG_5,
 811   MOD_0FC7_REG_6,
 812   MOD_0FC7_REG_7,
 813   MOD_0FD7,
 814   MOD_0FE7_PREFIX_2,
 815   MOD_0FF0_PREFIX_3,
 816   MOD_0F382A_PREFIX_2,
 817   MOD_62_32BIT,
 818   MOD_C4_32BIT,
 819   MOD_C5_32BIT,
 820   MOD_VEX_0F12_PREFIX_0,
 821   MOD_VEX_0F13,
 822   MOD_VEX_0F16_PREFIX_0,
 823   MOD_VEX_0F17,
 824   MOD_VEX_0F2B,
 825   MOD_VEX_W_0_0F41_P_0_LEN_1,
 826   MOD_VEX_W_1_0F41_P_0_LEN_1,
 827   MOD_VEX_W_0_0F41_P_2_LEN_1,
 828   MOD_VEX_W_1_0F41_P_2_LEN_1,
 829   MOD_VEX_W_0_0F42_P_0_LEN_1,
 830   MOD_VEX_W_1_0F42_P_0_LEN_1,
 831   MOD_VEX_W_0_0F42_P_2_LEN_1,
 832   MOD_VEX_W_1_0F42_P_2_LEN_1,
 833   MOD_VEX_W_0_0F44_P_0_LEN_1,
 834   MOD_VEX_W_1_0F44_P_0_LEN_1,
 835   MOD_VEX_W_0_0F44_P_2_LEN_1,
 836   MOD_VEX_W_1_0F44_P_2_LEN_1,
 837   MOD_VEX_W_0_0F45_P_0_LEN_1,
 838   MOD_VEX_W_1_0F45_P_0_LEN_1,
 839   MOD_VEX_W_0_0F45_P_2_LEN_1,
 840   MOD_VEX_W_1_0F45_P_2_LEN_1,
 841   MOD_VEX_W_0_0F46_P_0_LEN_1,
 842   MOD_VEX_W_1_0F46_P_0_LEN_1,
 843   MOD_VEX_W_0_0F46_P_2_LEN_1,
 844   MOD_VEX_W_1_0F46_P_2_LEN_1,
 845   MOD_VEX_W_0_0F47_P_0_LEN_1,
 846   MOD_VEX_W_1_0F47_P_0_LEN_1,
 847   MOD_VEX_W_0_0F47_P_2_LEN_1,
 848   MOD_VEX_W_1_0F47_P_2_LEN_1,
 849   MOD_VEX_W_0_0F4A_P_0_LEN_1,
 850   MOD_VEX_W_1_0F4A_P_0_LEN_1,
 851   MOD_VEX_W_0_0F4A_P_2_LEN_1,
 852   MOD_VEX_W_1_0F4A_P_2_LEN_1,
 853   MOD_VEX_W_0_0F4B_P_0_LEN_1,
 854   MOD_VEX_W_1_0F4B_P_0_LEN_1,
 855   MOD_VEX_W_0_0F4B_P_2_LEN_1,
 856   MOD_VEX_0F50,
 857   MOD_VEX_0F71_REG_2,
 858   MOD_VEX_0F71_REG_4,
 859   MOD_VEX_0F71_REG_6,
 860   MOD_VEX_0F72_REG_2,
 861   MOD_VEX_0F72_REG_4,
 862   MOD_VEX_0F72_REG_6,
 863   MOD_VEX_0F73_REG_2,
 864   MOD_VEX_0F73_REG_3,
 865   MOD_VEX_0F73_REG_6,
 866   MOD_VEX_0F73_REG_7,
 867   MOD_VEX_W_0_0F91_P_0_LEN_0,
 868   MOD_VEX_W_1_0F91_P_0_LEN_0,
 869   MOD_VEX_W_0_0F91_P_2_LEN_0,
 870   MOD_VEX_W_1_0F91_P_2_LEN_0,
 871   MOD_VEX_W_0_0F92_P_0_LEN_0,
 872   MOD_VEX_W_0_0F92_P_2_LEN_0,
 873   MOD_VEX_W_0_0F92_P_3_LEN_0,
 874   MOD_VEX_W_1_0F92_P_3_LEN_0,
 875   MOD_VEX_W_0_0F93_P_0_LEN_0,
 876   MOD_VEX_W_0_0F93_P_2_LEN_0,
 877   MOD_VEX_W_0_0F93_P_3_LEN_0,
 878   MOD_VEX_W_1_0F93_P_3_LEN_0,
 879   MOD_VEX_W_0_0F98_P_0_LEN_0,
 880   MOD_VEX_W_1_0F98_P_0_LEN_0,
 881   MOD_VEX_W_0_0F98_P_2_LEN_0,
 882   MOD_VEX_W_1_0F98_P_2_LEN_0,
 883   MOD_VEX_W_0_0F99_P_0_LEN_0,
 884   MOD_VEX_W_1_0F99_P_0_LEN_0,
 885   MOD_VEX_W_0_0F99_P_2_LEN_0,
 886   MOD_VEX_W_1_0F99_P_2_LEN_0,
 887   MOD_VEX_0FAE_REG_2,
 888   MOD_VEX_0FAE_REG_3,
 889   MOD_VEX_0FD7_PREFIX_2,
 890   MOD_VEX_0FE7_PREFIX_2,
 891   MOD_VEX_0FF0_PREFIX_3,
 892   MOD_VEX_0F381A_PREFIX_2,
 893   MOD_VEX_0F382A_PREFIX_2,
 894   MOD_VEX_0F382C_PREFIX_2,
 895   MOD_VEX_0F382D_PREFIX_2,
 896   MOD_VEX_0F382E_PREFIX_2,
 897   MOD_VEX_0F382F_PREFIX_2,
 898   MOD_VEX_0F385A_PREFIX_2,
 899   MOD_VEX_0F388C_PREFIX_2,
 900   MOD_VEX_0F388E_PREFIX_2,
 901   MOD_VEX_W_0_0F3A30_P_2_LEN_0,
 902   MOD_VEX_W_1_0F3A30_P_2_LEN_0,
 903   MOD_VEX_W_0_0F3A31_P_2_LEN_0,
 904   MOD_VEX_W_1_0F3A31_P_2_LEN_0,
 905   MOD_VEX_W_0_0F3A32_P_2_LEN_0,
 906   MOD_VEX_W_1_0F3A32_P_2_LEN_0,
 907   MOD_VEX_W_0_0F3A33_P_2_LEN_0,
 908   MOD_VEX_W_1_0F3A33_P_2_LEN_0,
 909
 910   MOD_EVEX_0F10_PREFIX_1,
 911   MOD_EVEX_0F10_PREFIX_3,
 912   MOD_EVEX_0F11_PREFIX_1,
 913   MOD_EVEX_0F11_PREFIX_3,
 914   MOD_EVEX_0F12_PREFIX_0,
 915   MOD_EVEX_0F16_PREFIX_0,
 916   MOD_EVEX_0F38C6_REG_1,
 917   MOD_EVEX_0F38C6_REG_2,
 918   MOD_EVEX_0F38C6_REG_5,
 919   MOD_EVEX_0F38C6_REG_6,
 920   MOD_EVEX_0F38C7_REG_1,
 921   MOD_EVEX_0F38C7_REG_2,
 922   MOD_EVEX_0F38C7_REG_5,
 923   MOD_EVEX_0F38C7_REG_6
 924 };
 925
 926 enum
 927 {
 928   RM_C6_REG_7 = 0,
 929   RM_C7_REG_7,
 930   RM_0F01_REG_0,
 931   RM_0F01_REG_1,
 932   RM_0F01_REG_2,
 933   RM_0F01_REG_3,
 934   RM_0F01_REG_5,
 935   RM_0F01_REG_7,
 936   RM_0FAE_REG_5,
 937   RM_0FAE_REG_6,
 938   RM_0FAE_REG_7
 939 };
 940
 941 enum
 942 {
 943   PREFIX_90 = 0,
 944   PREFIX_0F10,
 945   PREFIX_0F11,
 946   PREFIX_0F12,
 947   PREFIX_0F16,
 948   PREFIX_0F1A,
 949   PREFIX_0F1B,
 950   PREFIX_0F2A,
 951   PREFIX_0F2B,
 952   PREFIX_0F2C,
 953   PREFIX_0F2D,
 954   PREFIX_0F2E,
 955   PREFIX_0F2F,
 956   PREFIX_0F51,
 957   PREFIX_0F52,
 958   PREFIX_0F53,
 959   PREFIX_0F58,
 960   PREFIX_0F59,
 961   PREFIX_0F5A,
 962   PREFIX_0F5B,
 963   PREFIX_0F5C,
 964   PREFIX_0F5D,
 965   PREFIX_0F5E,
 966   PREFIX_0F5F,
 967   PREFIX_0F60,
 968   PREFIX_0F61,
 969   PREFIX_0F62,
 970   PREFIX_0F6C,
 971   PREFIX_0F6D,
 972   PREFIX_0F6F,
 973   PREFIX_0F70,
 974   PREFIX_0F73_REG_3,
 975   PREFIX_0F73_REG_7,
 976   PREFIX_0F78,
 977   PREFIX_0F79,
 978   PREFIX_0F7C,
 979   PREFIX_0F7D,
 980   PREFIX_0F7E,
 981   PREFIX_0F7F,
 982   PREFIX_0FAE_REG_0,
 983   PREFIX_0FAE_REG_1,
 984   PREFIX_0FAE_REG_2,
 985   PREFIX_0FAE_REG_3,
 986   PREFIX_MOD_0_0FAE_REG_4,
 987   PREFIX_MOD_3_0FAE_REG_4,
 988   PREFIX_0FAE_REG_6,
 989   PREFIX_0FAE_REG_7,
 990   PREFIX_0FB8,
 991   PREFIX_0FBC,
 992   PREFIX_0FBD,
 993   PREFIX_0FC2,
 994   PREFIX_MOD_0_0FC3,
 995   PREFIX_MOD_0_0FC7_REG_6,
 996   PREFIX_MOD_3_0FC7_REG_6,
 997   PREFIX_MOD_3_0FC7_REG_7,
 998   PREFIX_0FD0,
 999   PREFIX_0FD6,
1000   PREFIX_0FE6,
1001   PREFIX_0FE7,
1002   PREFIX_0FF0,
1003   PREFIX_0FF7,
1004   PREFIX_0F3810,
1005   PREFIX_0F3814,
1006   PREFIX_0F3815,
1007   PREFIX_0F3817,
1008   PREFIX_0F3820,
1009   PREFIX_0F3821,
1010   PREFIX_0F3822,
1011   PREFIX_0F3823,
1012   PREFIX_0F3824,
1013   PREFIX_0F3825,
1014   PREFIX_0F3828,
1015   PREFIX_0F3829,
1016   PREFIX_0F382A,
1017   PREFIX_0F382B,
1018   PREFIX_0F3830,
1019   PREFIX_0F3831,
1020   PREFIX_0F3832,
1021   PREFIX_0F3833,
1022   PREFIX_0F3834,
1023   PREFIX_0F3835,
1024   PREFIX_0F3837,
1025   PREFIX_0F3838,
1026   PREFIX_0F3839,
1027   PREFIX_0F383A,
1028   PREFIX_0F383B,
1029   PREFIX_0F383C,
1030   PREFIX_0F383D,
1031   PREFIX_0F383E,
1032   PREFIX_0F383F,
1033   PREFIX_0F3840,
1034   PREFIX_0F3841,
1035   PREFIX_0F3880,
1036   PREFIX_0F3881,
1037   PREFIX_0F3882,
1038   PREFIX_0F38C8,
1039   PREFIX_0F38C9,
1040   PREFIX_0F38CA,
1041   PREFIX_0F38CB,
1042   PREFIX_0F38CC,
1043   PREFIX_0F38CD,
1044   PREFIX_0F38DB,
1045   PREFIX_0F38DC,
1046   PREFIX_0F38DD,
1047   PREFIX_0F38DE,
1048   PREFIX_0F38DF,
1049   PREFIX_0F38F0,
1050   PREFIX_0F38F1,
1051   PREFIX_0F38F6,
1052   PREFIX_0F3A08,
1053   PREFIX_0F3A09,
1054   PREFIX_0F3A0A,
1055   PREFIX_0F3A0B,
1056   PREFIX_0F3A0C,
1057   PREFIX_0F3A0D,
1058   PREFIX_0F3A0E,
1059   PREFIX_0F3A14,
1060   PREFIX_0F3A15,
1061   PREFIX_0F3A16,
1062   PREFIX_0F3A17,
1063   PREFIX_0F3A20,
1064   PREFIX_0F3A21,
1065   PREFIX_0F3A22,
1066   PREFIX_0F3A40,
1067   PREFIX_0F3A41,
1068   PREFIX_0F3A42,
1069   PREFIX_0F3A44,
1070   PREFIX_0F3A60,
1071   PREFIX_0F3A61,
1072   PREFIX_0F3A62,
1073   PREFIX_0F3A63,
1074   PREFIX_0F3ACC,
1075   PREFIX_0F3ADF,
1076   PREFIX_VEX_0F10,
1077   PREFIX_VEX_0F11,
1078   PREFIX_VEX_0F12,
1079   PREFIX_VEX_0F16,
1080   PREFIX_VEX_0F2A,
1081   PREFIX_VEX_0F2C,
1082   PREFIX_VEX_0F2D,
1083   PREFIX_VEX_0F2E,
1084   PREFIX_VEX_0F2F,
1085   PREFIX_VEX_0F41,
1086   PREFIX_VEX_0F42,
1087   PREFIX_VEX_0F44,
1088   PREFIX_VEX_0F45,
1089   PREFIX_VEX_0F46,
1090   PREFIX_VEX_0F47,
1091   PREFIX_VEX_0F4A,
1092   PREFIX_VEX_0F4B,
1093   PREFIX_VEX_0F51,
1094   PREFIX_VEX_0F52,
1095   PREFIX_VEX_0F53,
1096   PREFIX_VEX_0F58,
1097   PREFIX_VEX_0F59,
1098   PREFIX_VEX_0F5A,
1099   PREFIX_VEX_0F5B,
1100   PREFIX_VEX_0F5C,
1101   PREFIX_VEX_0F5D,
1102   PREFIX_VEX_0F5E,
1103   PREFIX_VEX_0F5F,
1104   PREFIX_VEX_0F60,
1105   PREFIX_VEX_0F61,
1106   PREFIX_VEX_0F62,
1107   PREFIX_VEX_0F63,
1108   PREFIX_VEX_0F64,
1109   PREFIX_VEX_0F65,
1110   PREFIX_VEX_0F66,
1111   PREFIX_VEX_0F67,
1112   PREFIX_VEX_0F68,
1113   PREFIX_VEX_0F69,
1114   PREFIX_VEX_0F6A,
1115   PREFIX_VEX_0F6B,
1116   PREFIX_VEX_0F6C,
1117   PREFIX_VEX_0F6D,
1118   PREFIX_VEX_0F6E,
1119   PREFIX_VEX_0F6F,
1120   PREFIX_VEX_0F70,
1121   PREFIX_VEX_0F71_REG_2,
1122   PREFIX_VEX_0F71_REG_4,
1123   PREFIX_VEX_0F71_REG_6,
1124   PREFIX_VEX_0F72_REG_2,
1125   PREFIX_VEX_0F72_REG_4,
1126   PREFIX_VEX_0F72_REG_6,
1127   PREFIX_VEX_0F73_REG_2,
1128   PREFIX_VEX_0F73_REG_3,
1129   PREFIX_VEX_0F73_REG_6,
1130   PREFIX_VEX_0F73_REG_7,
1131   PREFIX_VEX_0F74,
1132   PREFIX_VEX_0F75,
1133   PREFIX_VEX_0F76,
1134   PREFIX_VEX_0F77,
1135   PREFIX_VEX_0F7C,
1136   PREFIX_VEX_0F7D,
1137   PREFIX_VEX_0F7E,
1138   PREFIX_VEX_0F7F,
1139   PREFIX_VEX_0F90,
1140   PREFIX_VEX_0F91,
1141   PREFIX_VEX_0F92,
1142   PREFIX_VEX_0F93,
1143   PREFIX_VEX_0F98,
1144   PREFIX_VEX_0F99,
1145   PREFIX_VEX_0FC2,
1146   PREFIX_VEX_0FC4,
1147   PREFIX_VEX_0FC5,
1148   PREFIX_VEX_0FD0,
1149   PREFIX_VEX_0FD1,
1150   PREFIX_VEX_0FD2,
1151   PREFIX_VEX_0FD3,
1152   PREFIX_VEX_0FD4,
1153   PREFIX_VEX_0FD5,
1154   PREFIX_VEX_0FD6,
1155   PREFIX_VEX_0FD7,
1156   PREFIX_VEX_0FD8,
1157   PREFIX_VEX_0FD9,
1158   PREFIX_VEX_0FDA,
1159   PREFIX_VEX_0FDB,
1160   PREFIX_VEX_0FDC,
1161   PREFIX_VEX_0FDD,
1162   PREFIX_VEX_0FDE,
1163   PREFIX_VEX_0FDF,
1164   PREFIX_VEX_0FE0,
1165   PREFIX_VEX_0FE1,
1166   PREFIX_VEX_0FE2,
1167   PREFIX_VEX_0FE3,
1168   PREFIX_VEX_0FE4,
1169   PREFIX_VEX_0FE5,
1170   PREFIX_VEX_0FE6,
1171   PREFIX_VEX_0FE7,
1172   PREFIX_VEX_0FE8,
1173   PREFIX_VEX_0FE9,
1174   PREFIX_VEX_0FEA,
1175   PREFIX_VEX_0FEB,
1176   PREFIX_VEX_0FEC,
1177   PREFIX_VEX_0FED,
1178   PREFIX_VEX_0FEE,
1179   PREFIX_VEX_0FEF,
1180   PREFIX_VEX_0FF0,
1181   PREFIX_VEX_0FF1,
1182   PREFIX_VEX_0FF2,
1183   PREFIX_VEX_0FF3,
1184   PREFIX_VEX_0FF4,
1185   PREFIX_VEX_0FF5,
1186   PREFIX_VEX_0FF6,
1187   PREFIX_VEX_0FF7,
1188   PREFIX_VEX_0FF8,
1189   PREFIX_VEX_0FF9,
1190   PREFIX_VEX_0FFA,
1191   PREFIX_VEX_0FFB,
1192   PREFIX_VEX_0FFC,
1193   PREFIX_VEX_0FFD,
1194   PREFIX_VEX_0FFE,
1195   PREFIX_VEX_0F3800,
1196   PREFIX_VEX_0F3801,
1197   PREFIX_VEX_0F3802,
1198   PREFIX_VEX_0F3803,
1199   PREFIX_VEX_0F3804,
1200   PREFIX_VEX_0F3805,
1201   PREFIX_VEX_0F3806,
1202   PREFIX_VEX_0F3807,
1203   PREFIX_VEX_0F3808,
1204   PREFIX_VEX_0F3809,
1205   PREFIX_VEX_0F380A,
1206   PREFIX_VEX_0F380B,
1207   PREFIX_VEX_0F380C,
1208   PREFIX_VEX_0F380D,
1209   PREFIX_VEX_0F380E,
1210   PREFIX_VEX_0F380F,
1211   PREFIX_VEX_0F3813,
1212   PREFIX_VEX_0F3816,
1213   PREFIX_VEX_0F3817,
1214   PREFIX_VEX_0F3818,
1215   PREFIX_VEX_0F3819,
1216   PREFIX_VEX_0F381A,
1217   PREFIX_VEX_0F381C,
1218   PREFIX_VEX_0F381D,
1219   PREFIX_VEX_0F381E,
1220   PREFIX_VEX_0F3820,
1221   PREFIX_VEX_0F3821,
1222   PREFIX_VEX_0F3822,
1223   PREFIX_VEX_0F3823,
1224   PREFIX_VEX_0F3824,
1225   PREFIX_VEX_0F3825,
1226   PREFIX_VEX_0F3828,
1227   PREFIX_VEX_0F3829,
1228   PREFIX_VEX_0F382A,
1229   PREFIX_VEX_0F382B,
1230   PREFIX_VEX_0F382C,
1231   PREFIX_VEX_0F382D,
1232   PREFIX_VEX_0F382E,
1233   PREFIX_VEX_0F382F,
1234   PREFIX_VEX_0F3830,
1235   PREFIX_VEX_0F3831,
1236   PREFIX_VEX_0F3832,
1237   PREFIX_VEX_0F3833,
1238   PREFIX_VEX_0F3834,
1239   PREFIX_VEX_0F3835,
1240   PREFIX_VEX_0F3836,
1241   PREFIX_VEX_0F3837,
1242   PREFIX_VEX_0F3838,
1243   PREFIX_VEX_0F3839,
1244   PREFIX_VEX_0F383A,
1245   PREFIX_VEX_0F383B,
1246   PREFIX_VEX_0F383C,
1247   PREFIX_VEX_0F383D,
1248   PREFIX_VEX_0F383E,
1249   PREFIX_VEX_0F383F,
1250   PREFIX_VEX_0F3840,
1251   PREFIX_VEX_0F3841,
1252   PREFIX_VEX_0F3845,
1253   PREFIX_VEX_0F3846,
1254   PREFIX_VEX_0F3847,
1255   PREFIX_VEX_0F3858,
1256   PREFIX_VEX_0F3859,
1257   PREFIX_VEX_0F385A,
1258   PREFIX_VEX_0F3878,
1259   PREFIX_VEX_0F3879,
1260   PREFIX_VEX_0F388C,
1261   PREFIX_VEX_0F388E,
1262   PREFIX_VEX_0F3890,
1263   PREFIX_VEX_0F3891,
1264   PREFIX_VEX_0F3892,
1265   PREFIX_VEX_0F3893,
1266   PREFIX_VEX_0F3896,
1267   PREFIX_VEX_0F3897,
1268   PREFIX_VEX_0F3898,
1269   PREFIX_VEX_0F3899,
1270   PREFIX_VEX_0F389A,
1271   PREFIX_VEX_0F389B,
1272   PREFIX_VEX_0F389C,
1273   PREFIX_VEX_0F389D,
1274   PREFIX_VEX_0F389E,
1275   PREFIX_VEX_0F389F,
1276   PREFIX_VEX_0F38A6,
1277   PREFIX_VEX_0F38A7,
1278   PREFIX_VEX_0F38A8,
1279   PREFIX_VEX_0F38A9,
1280   PREFIX_VEX_0F38AA,
1281   PREFIX_VEX_0F38AB,
1282   PREFIX_VEX_0F38AC,
1283   PREFIX_VEX_0F38AD,
1284   PREFIX_VEX_0F38AE,
1285   PREFIX_VEX_0F38AF,
1286   PREFIX_VEX_0F38B6,
1287   PREFIX_VEX_0F38B7,
1288   PREFIX_VEX_0F38B8,
1289   PREFIX_VEX_0F38B9,
1290   PREFIX_VEX_0F38BA,
1291   PREFIX_VEX_0F38BB,
1292   PREFIX_VEX_0F38BC,
1293   PREFIX_VEX_0F38BD,
1294   PREFIX_VEX_0F38BE,
1295   PREFIX_VEX_0F38BF,
1296   PREFIX_VEX_0F38DB,
1297   PREFIX_VEX_0F38DC,
1298   PREFIX_VEX_0F38DD,
1299   PREFIX_VEX_0F38DE,
1300   PREFIX_VEX_0F38DF,
1301   PREFIX_VEX_0F38F2,
1302   PREFIX_VEX_0F38F3_REG_1,
1303   PREFIX_VEX_0F38F3_REG_2,
1304   PREFIX_VEX_0F38F3_REG_3,
1305   PREFIX_VEX_0F38F5,
1306   PREFIX_VEX_0F38F6,
1307   PREFIX_VEX_0F38F7,
1308   PREFIX_VEX_0F3A00,
1309   PREFIX_VEX_0F3A01,
1310   PREFIX_VEX_0F3A02,
1311   PREFIX_VEX_0F3A04,
1312   PREFIX_VEX_0F3A05,
1313   PREFIX_VEX_0F3A06,
1314   PREFIX_VEX_0F3A08,
1315   PREFIX_VEX_0F3A09,
1316   PREFIX_VEX_0F3A0A,
1317   PREFIX_VEX_0F3A0B,
1318   PREFIX_VEX_0F3A0C,
1319   PREFIX_VEX_0F3A0D,
1320   PREFIX_VEX_0F3A0E,
1321   PREFIX_VEX_0F3A0F,
1322   PREFIX_VEX_0F3A14,
1323   PREFIX_VEX_0F3A15,
1324   PREFIX_VEX_0F3A16,
1325   PREFIX_VEX_0F3A17,
1326   PREFIX_VEX_0F3A18,
1327   PREFIX_VEX_0F3A19,
1328   PREFIX_VEX_0F3A1D,
1329   PREFIX_VEX_0F3A20,
1330   PREFIX_VEX_0F3A21,
1331   PREFIX_VEX_0F3A22,
1332   PREFIX_VEX_0F3A30,
1333   PREFIX_VEX_0F3A31,
1334   PREFIX_VEX_0F3A32,
1335   PREFIX_VEX_0F3A33,
1336   PREFIX_VEX_0F3A38,
1337   PREFIX_VEX_0F3A39,
1338   PREFIX_VEX_0F3A40,
1339   PREFIX_VEX_0F3A41,
1340   PREFIX_VEX_0F3A42,
1341   PREFIX_VEX_0F3A44,
1342   PREFIX_VEX_0F3A46,
1343   PREFIX_VEX_0F3A48,
1344   PREFIX_VEX_0F3A49,
1345   PREFIX_VEX_0F3A4A,
1346   PREFIX_VEX_0F3A4B,
1347   PREFIX_VEX_0F3A4C,
1348   PREFIX_VEX_0F3A5C,
1349   PREFIX_VEX_0F3A5D,
1350   PREFIX_VEX_0F3A5E,
1351   PREFIX_VEX_0F3A5F,
1352   PREFIX_VEX_0F3A60,
1353   PREFIX_VEX_0F3A61,
1354   PREFIX_VEX_0F3A62,
1355   PREFIX_VEX_0F3A63,
1356   PREFIX_VEX_0F3A68,
1357   PREFIX_VEX_0F3A69,
1358   PREFIX_VEX_0F3A6A,
1359   PREFIX_VEX_0F3A6B,
1360   PREFIX_VEX_0F3A6C,
1361   PREFIX_VEX_0F3A6D,
1362   PREFIX_VEX_0F3A6E,
1363   PREFIX_VEX_0F3A6F,
1364   PREFIX_VEX_0F3A78,
1365   PREFIX_VEX_0F3A79,
1366   PREFIX_VEX_0F3A7A,
1367   PREFIX_VEX_0F3A7B,
1368   PREFIX_VEX_0F3A7C,
1369   PREFIX_VEX_0F3A7D,
1370   PREFIX_VEX_0F3A7E,
1371   PREFIX_VEX_0F3A7F,
1372   PREFIX_VEX_0F3ADF,
1373   PREFIX_VEX_0F3AF0,
1374
1375   PREFIX_EVEX_0F10,
1376   PREFIX_EVEX_0F11,
1377   PREFIX_EVEX_0F12,
1378   PREFIX_EVEX_0F13,
1379   PREFIX_EVEX_0F14,
1380   PREFIX_EVEX_0F15,
1381   PREFIX_EVEX_0F16,
1382   PREFIX_EVEX_0F17,
1383   PREFIX_EVEX_0F28,
1384   PREFIX_EVEX_0F29,
1385   PREFIX_EVEX_0F2A,
1386   PREFIX_EVEX_0F2B,
1387   PREFIX_EVEX_0F2C,
1388   PREFIX_EVEX_0F2D,
1389   PREFIX_EVEX_0F2E,
1390   PREFIX_EVEX_0F2F,
1391   PREFIX_EVEX_0F51,
1392   PREFIX_EVEX_0F54,
1393   PREFIX_EVEX_0F55,
1394   PREFIX_EVEX_0F56,
1395   PREFIX_EVEX_0F57,
1396   PREFIX_EVEX_0F58,
1397   PREFIX_EVEX_0F59,
1398   PREFIX_EVEX_0F5A,
1399   PREFIX_EVEX_0F5B,
1400   PREFIX_EVEX_0F5C,
1401   PREFIX_EVEX_0F5D,
1402   PREFIX_EVEX_0F5E,
1403   PREFIX_EVEX_0F5F,
1404   PREFIX_EVEX_0F60,
1405   PREFIX_EVEX_0F61,
1406   PREFIX_EVEX_0F62,
1407   PREFIX_EVEX_0F63,
1408   PREFIX_EVEX_0F64,
1409   PREFIX_EVEX_0F65,
1410   PREFIX_EVEX_0F66,
1411   PREFIX_EVEX_0F67,
1412   PREFIX_EVEX_0F68,
1413   PREFIX_EVEX_0F69,
1414   PREFIX_EVEX_0F6A,
1415   PREFIX_EVEX_0F6B,
1416   PREFIX_EVEX_0F6C,
1417   PREFIX_EVEX_0F6D,
1418   PREFIX_EVEX_0F6E,
1419   PREFIX_EVEX_0F6F,
1420   PREFIX_EVEX_0F70,
1421   PREFIX_EVEX_0F71_REG_2,
1422   PREFIX_EVEX_0F71_REG_4,
1423   PREFIX_EVEX_0F71_REG_6,
1424   PREFIX_EVEX_0F72_REG_0,
1425   PREFIX_EVEX_0F72_REG_1,
1426   PREFIX_EVEX_0F72_REG_2,
1427   PREFIX_EVEX_0F72_REG_4,
1428   PREFIX_EVEX_0F72_REG_6,
1429   PREFIX_EVEX_0F73_REG_2,
1430   PREFIX_EVEX_0F73_REG_3,
1431   PREFIX_EVEX_0F73_REG_6,
1432   PREFIX_EVEX_0F73_REG_7,
1433   PREFIX_EVEX_0F74,
1434   PREFIX_EVEX_0F75,
1435   PREFIX_EVEX_0F76,
1436   PREFIX_EVEX_0F78,
1437   PREFIX_EVEX_0F79,
1438   PREFIX_EVEX_0F7A,
1439   PREFIX_EVEX_0F7B,
1440   PREFIX_EVEX_0F7E,
1441   PREFIX_EVEX_0F7F,
1442   PREFIX_EVEX_0FC2,
1443   PREFIX_EVEX_0FC4,
1444   PREFIX_EVEX_0FC5,
1445   PREFIX_EVEX_0FC6,
1446   PREFIX_EVEX_0FD1,
1447   PREFIX_EVEX_0FD2,
1448   PREFIX_EVEX_0FD3,
1449   PREFIX_EVEX_0FD4,
1450   PREFIX_EVEX_0FD5,
1451   PREFIX_EVEX_0FD6,
1452   PREFIX_EVEX_0FD8,
1453   PREFIX_EVEX_0FD9,
1454   PREFIX_EVEX_0FDA,
1455   PREFIX_EVEX_0FDB,
1456   PREFIX_EVEX_0FDC,
1457   PREFIX_EVEX_0FDD,
1458   PREFIX_EVEX_0FDE,
1459   PREFIX_EVEX_0FDF,
1460   PREFIX_EVEX_0FE0,
1461   PREFIX_EVEX_0FE1,
1462   PREFIX_EVEX_0FE2,
1463   PREFIX_EVEX_0FE3,
1464   PREFIX_EVEX_0FE4,
1465   PREFIX_EVEX_0FE5,
1466   PREFIX_EVEX_0FE6,
1467   PREFIX_EVEX_0FE7,
1468   PREFIX_EVEX_0FE8,
1469   PREFIX_EVEX_0FE9,
1470   PREFIX_EVEX_0FEA,
1471   PREFIX_EVEX_0FEB,
1472   PREFIX_EVEX_0FEC,
1473   PREFIX_EVEX_0FED,
1474   PREFIX_EVEX_0FEE,
1475   PREFIX_EVEX_0FEF,
1476   PREFIX_EVEX_0FF1,
1477   PREFIX_EVEX_0FF2,
1478   PREFIX_EVEX_0FF3,
1479   PREFIX_EVEX_0FF4,
1480   PREFIX_EVEX_0FF5,
1481   PREFIX_EVEX_0FF6,
1482   PREFIX_EVEX_0FF8,
1483   PREFIX_EVEX_0FF9,
1484   PREFIX_EVEX_0FFA,
1485   PREFIX_EVEX_0FFB,
1486   PREFIX_EVEX_0FFC,
1487   PREFIX_EVEX_0FFD,
1488   PREFIX_EVEX_0FFE,
1489   PREFIX_EVEX_0F3800,
1490   PREFIX_EVEX_0F3804,
1491   PREFIX_EVEX_0F380B,
1492   PREFIX_EVEX_0F380C,
1493   PREFIX_EVEX_0F380D,
1494   PREFIX_EVEX_0F3810,
1495   PREFIX_EVEX_0F3811,
1496   PREFIX_EVEX_0F3812,
1497   PREFIX_EVEX_0F3813,
1498   PREFIX_EVEX_0F3814,
1499   PREFIX_EVEX_0F3815,
1500   PREFIX_EVEX_0F3816,
1501   PREFIX_EVEX_0F3818,
1502   PREFIX_EVEX_0F3819,
1503   PREFIX_EVEX_0F381A,
1504   PREFIX_EVEX_0F381B,
1505   PREFIX_EVEX_0F381C,
1506   PREFIX_EVEX_0F381D,
1507   PREFIX_EVEX_0F381E,
1508   PREFIX_EVEX_0F381F,
1509   PREFIX_EVEX_0F3820,
1510   PREFIX_EVEX_0F3821,
1511   PREFIX_EVEX_0F3822,
1512   PREFIX_EVEX_0F3823,
1513   PREFIX_EVEX_0F3824,
1514   PREFIX_EVEX_0F3825,
1515   PREFIX_EVEX_0F3826,
1516   PREFIX_EVEX_0F3827,
1517   PREFIX_EVEX_0F3828,
1518   PREFIX_EVEX_0F3829,
1519   PREFIX_EVEX_0F382A,
1520   PREFIX_EVEX_0F382B,
1521   PREFIX_EVEX_0F382C,
1522   PREFIX_EVEX_0F382D,
1523   PREFIX_EVEX_0F3830,
1524   PREFIX_EVEX_0F3831,
1525   PREFIX_EVEX_0F3832,
1526   PREFIX_EVEX_0F3833,
1527   PREFIX_EVEX_0F3834,
1528   PREFIX_EVEX_0F3835,
1529   PREFIX_EVEX_0F3836,
1530   PREFIX_EVEX_0F3837,
1531   PREFIX_EVEX_0F3838,
1532   PREFIX_EVEX_0F3839,
1533   PREFIX_EVEX_0F383A,
1534   PREFIX_EVEX_0F383B,
1535   PREFIX_EVEX_0F383C,
1536   PREFIX_EVEX_0F383D,
1537   PREFIX_EVEX_0F383E,
1538   PREFIX_EVEX_0F383F,
1539   PREFIX_EVEX_0F3840,
1540   PREFIX_EVEX_0F3842,
1541   PREFIX_EVEX_0F3843,
1542   PREFIX_EVEX_0F3844,
1543   PREFIX_EVEX_0F3845,
1544   PREFIX_EVEX_0F3846,
1545   PREFIX_EVEX_0F3847,
1546   PREFIX_EVEX_0F384C,
1547   PREFIX_EVEX_0F384D,
1548   PREFIX_EVEX_0F384E,
1549   PREFIX_EVEX_0F384F,
1550   PREFIX_EVEX_0F3852,
1551   PREFIX_EVEX_0F3853,
1552   PREFIX_EVEX_0F3855,
1553   PREFIX_EVEX_0F3858,
1554   PREFIX_EVEX_0F3859,
1555   PREFIX_EVEX_0F385A,
1556   PREFIX_EVEX_0F385B,
1557   PREFIX_EVEX_0F3864,
1558   PREFIX_EVEX_0F3865,
1559   PREFIX_EVEX_0F3866,
1560   PREFIX_EVEX_0F3875,
1561   PREFIX_EVEX_0F3876,
1562   PREFIX_EVEX_0F3877,
1563   PREFIX_EVEX_0F3878,
1564   PREFIX_EVEX_0F3879,
1565   PREFIX_EVEX_0F387A,
1566   PREFIX_EVEX_0F387B,
1567   PREFIX_EVEX_0F387C,
1568   PREFIX_EVEX_0F387D,
1569   PREFIX_EVEX_0F387E,
1570   PREFIX_EVEX_0F387F,
1571   PREFIX_EVEX_0F3883,
1572   PREFIX_EVEX_0F3888,
1573   PREFIX_EVEX_0F3889,
1574   PREFIX_EVEX_0F388A,
1575   PREFIX_EVEX_0F388B,
1576   PREFIX_EVEX_0F388D,
1577   PREFIX_EVEX_0F3890,
1578   PREFIX_EVEX_0F3891,
1579   PREFIX_EVEX_0F3892,
1580   PREFIX_EVEX_0F3893,
1581   PREFIX_EVEX_0F3896,
1582   PREFIX_EVEX_0F3897,
1583   PREFIX_EVEX_0F3898,
1584   PREFIX_EVEX_0F3899,
1585   PREFIX_EVEX_0F389A,
1586   PREFIX_EVEX_0F389B,
1587   PREFIX_EVEX_0F389C,
1588   PREFIX_EVEX_0F389D,
1589   PREFIX_EVEX_0F389E,
1590   PREFIX_EVEX_0F389F,
1591   PREFIX_EVEX_0F38A0,
1592   PREFIX_EVEX_0F38A1,
1593   PREFIX_EVEX_0F38A2,
1594   PREFIX_EVEX_0F38A3,
1595   PREFIX_EVEX_0F38A6,
1596   PREFIX_EVEX_0F38A7,
1597   PREFIX_EVEX_0F38A8,
1598   PREFIX_EVEX_0F38A9,
1599   PREFIX_EVEX_0F38AA,
1600   PREFIX_EVEX_0F38AB,
1601   PREFIX_EVEX_0F38AC,
1602   PREFIX_EVEX_0F38AD,
1603   PREFIX_EVEX_0F38AE,
1604   PREFIX_EVEX_0F38AF,
1605   PREFIX_EVEX_0F38B4,
1606   PREFIX_EVEX_0F38B5,
1607   PREFIX_EVEX_0F38B6,
1608   PREFIX_EVEX_0F38B7,
1609   PREFIX_EVEX_0F38B8,
1610   PREFIX_EVEX_0F38B9,
1611   PREFIX_EVEX_0F38BA,
1612   PREFIX_EVEX_0F38BB,
1613   PREFIX_EVEX_0F38BC,
1614   PREFIX_EVEX_0F38BD,
1615   PREFIX_EVEX_0F38BE,
1616   PREFIX_EVEX_0F38BF,
1617   PREFIX_EVEX_0F38C4,
1618   PREFIX_EVEX_0F38C6_REG_1,
1619   PREFIX_EVEX_0F38C6_REG_2,
1620   PREFIX_EVEX_0F38C6_REG_5,
1621   PREFIX_EVEX_0F38C6_REG_6,
1622   PREFIX_EVEX_0F38C7_REG_1,
1623   PREFIX_EVEX_0F38C7_REG_2,
1624   PREFIX_EVEX_0F38C7_REG_5,
1625   PREFIX_EVEX_0F38C7_REG_6,
1626   PREFIX_EVEX_0F38C8,
1627   PREFIX_EVEX_0F38CA,
1628   PREFIX_EVEX_0F38CB,
1629   PREFIX_EVEX_0F38CC,
1630   PREFIX_EVEX_0F38CD,
1631
1632   PREFIX_EVEX_0F3A00,
1633   PREFIX_EVEX_0F3A01,
1634   PREFIX_EVEX_0F3A03,
1635   PREFIX_EVEX_0F3A04,
1636   PREFIX_EVEX_0F3A05,
1637   PREFIX_EVEX_0F3A08,
1638   PREFIX_EVEX_0F3A09,
1639   PREFIX_EVEX_0F3A0A,
1640   PREFIX_EVEX_0F3A0B,
1641   PREFIX_EVEX_0F3A0F,
1642   PREFIX_EVEX_0F3A14,
1643   PREFIX_EVEX_0F3A15,
1644   PREFIX_EVEX_0F3A16,
1645   PREFIX_EVEX_0F3A17,
1646   PREFIX_EVEX_0F3A18,
1647   PREFIX_EVEX_0F3A19,
1648   PREFIX_EVEX_0F3A1A,
1649   PREFIX_EVEX_0F3A1B,
1650   PREFIX_EVEX_0F3A1D,
1651   PREFIX_EVEX_0F3A1E,
1652   PREFIX_EVEX_0F3A1F,
1653   PREFIX_EVEX_0F3A20,
1654   PREFIX_EVEX_0F3A21,
1655   PREFIX_EVEX_0F3A22,
1656   PREFIX_EVEX_0F3A23,
1657   PREFIX_EVEX_0F3A25,
1658   PREFIX_EVEX_0F3A26,
1659   PREFIX_EVEX_0F3A27,
1660   PREFIX_EVEX_0F3A38,
1661   PREFIX_EVEX_0F3A39,
1662   PREFIX_EVEX_0F3A3A,
1663   PREFIX_EVEX_0F3A3B,
1664   PREFIX_EVEX_0F3A3E,
1665   PREFIX_EVEX_0F3A3F,
1666   PREFIX_EVEX_0F3A42,
1667   PREFIX_EVEX_0F3A43,
1668   PREFIX_EVEX_0F3A50,
1669   PREFIX_EVEX_0F3A51,
1670   PREFIX_EVEX_0F3A54,
1671   PREFIX_EVEX_0F3A55,
1672   PREFIX_EVEX_0F3A56,
1673   PREFIX_EVEX_0F3A57,
1674   PREFIX_EVEX_0F3A66,
1675   PREFIX_EVEX_0F3A67
1676 };
1677
1678 enum
1679 {
1680   X86_64_06 = 0,
1681   X86_64_07,
1682   X86_64_0D,
1683   X86_64_16,
1684   X86_64_17,
1685   X86_64_1E,
1686   X86_64_1F,
1687   X86_64_27,
1688   X86_64_2F,
1689   X86_64_37,
1690   X86_64_3F,
1691   X86_64_60,
1692   X86_64_61,
1693   X86_64_62,
1694   X86_64_63,
1695   X86_64_6D,
1696   X86_64_6F,
1697   X86_64_82,
1698   X86_64_9A,
1699   X86_64_C4,
1700   X86_64_C5,
1701   X86_64_CE,
1702   X86_64_D4,
1703   X86_64_D5,
1704   X86_64_E8,
1705   X86_64_E9,
1706   X86_64_EA,
1707   X86_64_0F01_REG_0,
1708   X86_64_0F01_REG_1,
1709   X86_64_0F01_REG_2,
1710   X86_64_0F01_REG_3
1711 };
1712
1713 enum
1714 {
1715   THREE_BYTE_0F38 = 0,
1716   THREE_BYTE_0F3A
1717 };
1718
1719 enum
1720 {
1721   XOP_08 = 0,
1722   XOP_09,
1723   XOP_0A
1724 };
1725
1726 enum
1727 {
1728   VEX_0F = 0,
1729   VEX_0F38,
1730   VEX_0F3A
1731 };
1732
1733 enum
1734 {
1735   EVEX_0F = 0,
1736   EVEX_0F38,
1737   EVEX_0F3A
1738 };
1739
1740 enum
1741 {
1742   VEX_LEN_0F10_P_1 = 0,
1743   VEX_LEN_0F10_P_3,
1744   VEX_LEN_0F11_P_1,
1745   VEX_LEN_0F11_P_3,
1746   VEX_LEN_0F12_P_0_M_0,
1747   VEX_LEN_0F12_P_0_M_1,
1748   VEX_LEN_0F12_P_2,
1749   VEX_LEN_0F13_M_0,
1750   VEX_LEN_0F16_P_0_M_0,
1751   VEX_LEN_0F16_P_0_M_1,
1752   VEX_LEN_0F16_P_2,
1753   VEX_LEN_0F17_M_0,
1754   VEX_LEN_0F2A_P_1,
1755   VEX_LEN_0F2A_P_3,
1756   VEX_LEN_0F2C_P_1,
1757   VEX_LEN_0F2C_P_3,
1758   VEX_LEN_0F2D_P_1,
1759   VEX_LEN_0F2D_P_3,
1760   VEX_LEN_0F2E_P_0,
1761   VEX_LEN_0F2E_P_2,
1762   VEX_LEN_0F2F_P_0,
1763   VEX_LEN_0F2F_P_2,
1764   VEX_LEN_0F41_P_0,
1765   VEX_LEN_0F41_P_2,
1766   VEX_LEN_0F42_P_0,
1767   VEX_LEN_0F42_P_2,
1768   VEX_LEN_0F44_P_0,
1769   VEX_LEN_0F44_P_2,
1770   VEX_LEN_0F45_P_0,
1771   VEX_LEN_0F45_P_2,
1772   VEX_LEN_0F46_P_0,
1773   VEX_LEN_0F46_P_2,
1774   VEX_LEN_0F47_P_0,
1775   VEX_LEN_0F47_P_2,
1776   VEX_LEN_0F4A_P_0,
1777   VEX_LEN_0F4A_P_2,
1778   VEX_LEN_0F4B_P_0,
1779   VEX_LEN_0F4B_P_2,
1780   VEX_LEN_0F51_P_1,
1781   VEX_LEN_0F51_P_3,
1782   VEX_LEN_0F52_P_1,
1783   VEX_LEN_0F53_P_1,
1784   VEX_LEN_0F58_P_1,
1785   VEX_LEN_0F58_P_3,
1786   VEX_LEN_0F59_P_1,
1787   VEX_LEN_0F59_P_3,
1788   VEX_LEN_0F5A_P_1,
1789   VEX_LEN_0F5A_P_3,
1790   VEX_LEN_0F5C_P_1,
1791   VEX_LEN_0F5C_P_3,
1792   VEX_LEN_0F5D_P_1,
1793   VEX_LEN_0F5D_P_3,
1794   VEX_LEN_0F5E_P_1,
1795   VEX_LEN_0F5E_P_3,
1796   VEX_LEN_0F5F_P_1,
1797   VEX_LEN_0F5F_P_3,
1798   VEX_LEN_0F6E_P_2,
1799   VEX_LEN_0F7E_P_1,
1800   VEX_LEN_0F7E_P_2,
1801   VEX_LEN_0F90_P_0,
1802   VEX_LEN_0F90_P_2,
1803   VEX_LEN_0F91_P_0,
1804   VEX_LEN_0F91_P_2,
1805   VEX_LEN_0F92_P_0,
1806   VEX_LEN_0F92_P_2,
1807   VEX_LEN_0F92_P_3,
1808   VEX_LEN_0F93_P_0,
1809   VEX_LEN_0F93_P_2,
1810   VEX_LEN_0F93_P_3,
1811   VEX_LEN_0F98_P_0,
1812   VEX_LEN_0F98_P_2,
1813   VEX_LEN_0F99_P_0,
1814   VEX_LEN_0F99_P_2,
1815   VEX_LEN_0FAE_R_2_M_0,
1816   VEX_LEN_0FAE_R_3_M_0,
1817   VEX_LEN_0FC2_P_1,
1818   VEX_LEN_0FC2_P_3,
1819   VEX_LEN_0FC4_P_2,
1820   VEX_LEN_0FC5_P_2,
1821   VEX_LEN_0FD6_P_2,
1822   VEX_LEN_0FF7_P_2,
1823   VEX_LEN_0F3816_P_2,
1824   VEX_LEN_0F3819_P_2,
1825   VEX_LEN_0F381A_P_2_M_0,
1826   VEX_LEN_0F3836_P_2,
1827   VEX_LEN_0F3841_P_2,
1828   VEX_LEN_0F385A_P_2_M_0,
1829   VEX_LEN_0F38DB_P_2,
1830   VEX_LEN_0F38DC_P_2,
1831   VEX_LEN_0F38DD_P_2,
1832   VEX_LEN_0F38DE_P_2,
1833   VEX_LEN_0F38DF_P_2,
1834   VEX_LEN_0F38F2_P_0,
1835   VEX_LEN_0F38F3_R_1_P_0,
1836   VEX_LEN_0F38F3_R_2_P_0,
1837   VEX_LEN_0F38F3_R_3_P_0,
1838   VEX_LEN_0F38F5_P_0,
1839   VEX_LEN_0F38F5_P_1,
1840   VEX_LEN_0F38F5_P_3,
1841   VEX_LEN_0F38F6_P_3,
1842   VEX_LEN_0F38F7_P_0,
1843   VEX_LEN_0F38F7_P_1,
1844   VEX_LEN_0F38F7_P_2,
1845   VEX_LEN_0F38F7_P_3,
1846   VEX_LEN_0F3A00_P_2,
1847   VEX_LEN_0F3A01_P_2,
1848   VEX_LEN_0F3A06_P_2,
1849   VEX_LEN_0F3A0A_P_2,
1850   VEX_LEN_0F3A0B_P_2,
1851   VEX_LEN_0F3A14_P_2,
1852   VEX_LEN_0F3A15_P_2,
1853   VEX_LEN_0F3A16_P_2,
1854   VEX_LEN_0F3A17_P_2,
1855   VEX_LEN_0F3A18_P_2,
1856   VEX_LEN_0F3A19_P_2,
1857   VEX_LEN_0F3A20_P_2,
1858   VEX_LEN_0F3A21_P_2,
1859   VEX_LEN_0F3A22_P_2,
1860   VEX_LEN_0F3A30_P_2,
1861   VEX_LEN_0F3A31_P_2,
1862   VEX_LEN_0F3A32_P_2,
1863   VEX_LEN_0F3A33_P_2,
1864   VEX_LEN_0F3A38_P_2,
1865   VEX_LEN_0F3A39_P_2,
1866   VEX_LEN_0F3A41_P_2,
1867   VEX_LEN_0F3A44_P_2,
1868   VEX_LEN_0F3A46_P_2,
1869   VEX_LEN_0F3A60_P_2,
1870   VEX_LEN_0F3A61_P_2,
1871   VEX_LEN_0F3A62_P_2,
1872   VEX_LEN_0F3A63_P_2,
1873   VEX_LEN_0F3A6A_P_2,
1874   VEX_LEN_0F3A6B_P_2,
1875   VEX_LEN_0F3A6E_P_2,
1876   VEX_LEN_0F3A6F_P_2,
1877   VEX_LEN_0F3A7A_P_2,
1878   VEX_LEN_0F3A7B_P_2,
1879   VEX_LEN_0F3A7E_P_2,
1880   VEX_LEN_0F3A7F_P_2,
1881   VEX_LEN_0F3ADF_P_2,
1882   VEX_LEN_0F3AF0_P_3,
1883   VEX_LEN_0FXOP_08_CC,
1884   VEX_LEN_0FXOP_08_CD,
1885   VEX_LEN_0FXOP_08_CE,
1886   VEX_LEN_0FXOP_08_CF,
1887   VEX_LEN_0FXOP_08_EC,
1888   VEX_LEN_0FXOP_08_ED,
1889   VEX_LEN_0FXOP_08_EE,
1890   VEX_LEN_0FXOP_08_EF,
1891   VEX_LEN_0FXOP_09_80,
1892   VEX_LEN_0FXOP_09_81
1893 };
1894
1895 enum
1896 {
1897   VEX_W_0F10_P_0 = 0,
1898   VEX_W_0F10_P_1,
1899   VEX_W_0F10_P_2,
1900   VEX_W_0F10_P_3,
1901   VEX_W_0F11_P_0,
1902   VEX_W_0F11_P_1,
1903   VEX_W_0F11_P_2,
1904   VEX_W_0F11_P_3,
1905   VEX_W_0F12_P_0_M_0,
1906   VEX_W_0F12_P_0_M_1,
1907   VEX_W_0F12_P_1,
1908   VEX_W_0F12_P_2,
1909   VEX_W_0F12_P_3,
1910   VEX_W_0F13_M_0,
1911   VEX_W_0F14,
1912   VEX_W_0F15,
1913   VEX_W_0F16_P_0_M_0,
1914   VEX_W_0F16_P_0_M_1,
1915   VEX_W_0F16_P_1,
1916   VEX_W_0F16_P_2,
1917   VEX_W_0F17_M_0,
1918   VEX_W_0F28,
1919   VEX_W_0F29,
1920   VEX_W_0F2B_M_0,
1921   VEX_W_0F2E_P_0,
1922   VEX_W_0F2E_P_2,
1923   VEX_W_0F2F_P_0,
1924   VEX_W_0F2F_P_2,
1925   VEX_W_0F41_P_0_LEN_1,
1926   VEX_W_0F41_P_2_LEN_1,
1927   VEX_W_0F42_P_0_LEN_1,
1928   VEX_W_0F42_P_2_LEN_1,
1929   VEX_W_0F44_P_0_LEN_0,
1930   VEX_W_0F44_P_2_LEN_0,
1931   VEX_W_0F45_P_0_LEN_1,
1932   VEX_W_0F45_P_2_LEN_1,
1933   VEX_W_0F46_P_0_LEN_1,
1934   VEX_W_0F46_P_2_LEN_1,
1935   VEX_W_0F47_P_0_LEN_1,
1936   VEX_W_0F47_P_2_LEN_1,
1937   VEX_W_0F4A_P_0_LEN_1,
1938   VEX_W_0F4A_P_2_LEN_1,
1939   VEX_W_0F4B_P_0_LEN_1,
1940   VEX_W_0F4B_P_2_LEN_1,
1941   VEX_W_0F50_M_0,
1942   VEX_W_0F51_P_0,
1943   VEX_W_0F51_P_1,
1944   VEX_W_0F51_P_2,
1945   VEX_W_0F51_P_3,
1946   VEX_W_0F52_P_0,
1947   VEX_W_0F52_P_1,
1948   VEX_W_0F53_P_0,
1949   VEX_W_0F53_P_1,
1950   VEX_W_0F58_P_0,
1951   VEX_W_0F58_P_1,
1952   VEX_W_0F58_P_2,
1953   VEX_W_0F58_P_3,
1954   VEX_W_0F59_P_0,
1955   VEX_W_0F59_P_1,
1956   VEX_W_0F59_P_2,
1957   VEX_W_0F59_P_3,
1958   VEX_W_0F5A_P_0,
1959   VEX_W_0F5A_P_1,
1960   VEX_W_0F5A_P_3,
1961   VEX_W_0F5B_P_0,
1962   VEX_W_0F5B_P_1,
1963   VEX_W_0F5B_P_2,
1964   VEX_W_0F5C_P_0,
1965   VEX_W_0F5C_P_1,
1966   VEX_W_0F5C_P_2,
1967   VEX_W_0F5C_P_3,
1968   VEX_W_0F5D_P_0,
1969   VEX_W_0F5D_P_1,
1970   VEX_W_0F5D_P_2,
1971   VEX_W_0F5D_P_3,
1972   VEX_W_0F5E_P_0,
1973   VEX_W_0F5E_P_1,
1974   VEX_W_0F5E_P_2,
1975   VEX_W_0F5E_P_3,
1976   VEX_W_0F5F_P_0,
1977   VEX_W_0F5F_P_1,
1978   VEX_W_0F5F_P_2,
1979   VEX_W_0F5F_P_3,
1980   VEX_W_0F60_P_2,
1981   VEX_W_0F61_P_2,
1982   VEX_W_0F62_P_2,
1983   VEX_W_0F63_P_2,
1984   VEX_W_0F64_P_2,
1985   VEX_W_0F65_P_2,
1986   VEX_W_0F66_P_2,
1987   VEX_W_0F67_P_2,
1988   VEX_W_0F68_P_2,
1989   VEX_W_0F69_P_2,
1990   VEX_W_0F6A_P_2,
1991   VEX_W_0F6B_P_2,
1992   VEX_W_0F6C_P_2,
1993   VEX_W_0F6D_P_2,
1994   VEX_W_0F6F_P_1,
1995   VEX_W_0F6F_P_2,
1996   VEX_W_0F70_P_1,
1997   VEX_W_0F70_P_2,
1998   VEX_W_0F70_P_3,
1999   VEX_W_0F71_R_2_P_2,
2000   VEX_W_0F71_R_4_P_2,
2001   VEX_W_0F71_R_6_P_2,
2002   VEX_W_0F72_R_2_P_2,
2003   VEX_W_0F72_R_4_P_2,
2004   VEX_W_0F72_R_6_P_2,
2005   VEX_W_0F73_R_2_P_2,
2006   VEX_W_0F73_R_3_P_2,
2007   VEX_W_0F73_R_6_P_2,
2008   VEX_W_0F73_R_7_P_2,
2009   VEX_W_0F74_P_2,
2010   VEX_W_0F75_P_2,
2011   VEX_W_0F76_P_2,
2012   VEX_W_0F77_P_0,
2013   VEX_W_0F7C_P_2,
2014   VEX_W_0F7C_P_3,
2015   VEX_W_0F7D_P_2,
2016   VEX_W_0F7D_P_3,
2017   VEX_W_0F7E_P_1,
2018   VEX_W_0F7F_P_1,
2019   VEX_W_0F7F_P_2,
2020   VEX_W_0F90_P_0_LEN_0,
2021   VEX_W_0F90_P_2_LEN_0,
2022   VEX_W_0F91_P_0_LEN_0,
2023   VEX_W_0F91_P_2_LEN_0,
2024   VEX_W_0F92_P_0_LEN_0,
2025   VEX_W_0F92_P_2_LEN_0,
2026   VEX_W_0F92_P_3_LEN_0,
2027   VEX_W_0F93_P_0_LEN_0,
2028   VEX_W_0F93_P_2_LEN_0,
2029   VEX_W_0F93_P_3_LEN_0,
2030   VEX_W_0F98_P_0_LEN_0,
2031   VEX_W_0F98_P_2_LEN_0,
2032   VEX_W_0F99_P_0_LEN_0,
2033   VEX_W_0F99_P_2_LEN_0,
2034   VEX_W_0FAE_R_2_M_0,
2035   VEX_W_0FAE_R_3_M_0,
2036   VEX_W_0FC2_P_0,
2037   VEX_W_0FC2_P_1,
2038   VEX_W_0FC2_P_2,
2039   VEX_W_0FC2_P_3,
2040   VEX_W_0FC4_P_2,
2041   VEX_W_0FC5_P_2,
2042   VEX_W_0FD0_P_2,
2043   VEX_W_0FD0_P_3,
2044   VEX_W_0FD1_P_2,
2045   VEX_W_0FD2_P_2,
2046   VEX_W_0FD3_P_2,
2047   VEX_W_0FD4_P_2,
2048   VEX_W_0FD5_P_2,
2049   VEX_W_0FD6_P_2,
2050   VEX_W_0FD7_P_2_M_1,
2051   VEX_W_0FD8_P_2,
2052   VEX_W_0FD9_P_2,
2053   VEX_W_0FDA_P_2,
2054   VEX_W_0FDB_P_2,
2055   VEX_W_0FDC_P_2,
2056   VEX_W_0FDD_P_2,
2057   VEX_W_0FDE_P_2,
2058   VEX_W_0FDF_P_2,
2059   VEX_W_0FE0_P_2,
2060   VEX_W_0FE1_P_2,
2061   VEX_W_0FE2_P_2,
2062   VEX_W_0FE3_P_2,
2063   VEX_W_0FE4_P_2,
2064   VEX_W_0FE5_P_2,
2065   VEX_W_0FE6_P_1,
2066   VEX_W_0FE6_P_2,
2067   VEX_W_0FE6_P_3,
2068   VEX_W_0FE7_P_2_M_0,
2069   VEX_W_0FE8_P_2,
2070   VEX_W_0FE9_P_2,
2071   VEX_W_0FEA_P_2,
2072   VEX_W_0FEB_P_2,
2073   VEX_W_0FEC_P_2,
2074   VEX_W_0FED_P_2,
2075   VEX_W_0FEE_P_2,
2076   VEX_W_0FEF_P_2,
2077   VEX_W_0FF0_P_3_M_0,
2078   VEX_W_0FF1_P_2,
2079   VEX_W_0FF2_P_2,
2080   VEX_W_0FF3_P_2,
2081   VEX_W_0FF4_P_2,
2082   VEX_W_0FF5_P_2,
2083   VEX_W_0FF6_P_2,
2084   VEX_W_0FF7_P_2,
2085   VEX_W_0FF8_P_2,
2086   VEX_W_0FF9_P_2,
2087   VEX_W_0FFA_P_2,
2088   VEX_W_0FFB_P_2,
2089   VEX_W_0FFC_P_2,
2090   VEX_W_0FFD_P_2,
2091   VEX_W_0FFE_P_2,
2092   VEX_W_0F3800_P_2,
2093   VEX_W_0F3801_P_2,
2094   VEX_W_0F3802_P_2,
2095   VEX_W_0F3803_P_2,
2096   VEX_W_0F3804_P_2,
2097   VEX_W_0F3805_P_2,
2098   VEX_W_0F3806_P_2,
2099   VEX_W_0F3807_P_2,
2100   VEX_W_0F3808_P_2,
2101   VEX_W_0F3809_P_2,
2102   VEX_W_0F380A_P_2,
2103   VEX_W_0F380B_P_2,
2104   VEX_W_0F380C_P_2,
2105   VEX_W_0F380D_P_2,
2106   VEX_W_0F380E_P_2,
2107   VEX_W_0F380F_P_2,
2108   VEX_W_0F3816_P_2,
2109   VEX_W_0F3817_P_2,
2110   VEX_W_0F3818_P_2,
2111   VEX_W_0F3819_P_2,
2112   VEX_W_0F381A_P_2_M_0,
2113   VEX_W_0F381C_P_2,
2114   VEX_W_0F381D_P_2,
2115   VEX_W_0F381E_P_2,
2116   VEX_W_0F3820_P_2,
2117   VEX_W_0F3821_P_2,
2118   VEX_W_0F3822_P_2,
2119   VEX_W_0F3823_P_2,
2120   VEX_W_0F3824_P_2,
2121   VEX_W_0F3825_P_2,
2122   VEX_W_0F3828_P_2,
2123   VEX_W_0F3829_P_2,
2124   VEX_W_0F382A_P_2_M_0,
2125   VEX_W_0F382B_P_2,
2126   VEX_W_0F382C_P_2_M_0,
2127   VEX_W_0F382D_P_2_M_0,
2128   VEX_W_0F382E_P_2_M_0,
2129   VEX_W_0F382F_P_2_M_0,
2130   VEX_W_0F3830_P_2,
2131   VEX_W_0F3831_P_2,
2132   VEX_W_0F3832_P_2,
2133   VEX_W_0F3833_P_2,
2134   VEX_W_0F3834_P_2,
2135   VEX_W_0F3835_P_2,
2136   VEX_W_0F3836_P_2,
2137   VEX_W_0F3837_P_2,
2138   VEX_W_0F3838_P_2,
2139   VEX_W_0F3839_P_2,
2140   VEX_W_0F383A_P_2,
2141   VEX_W_0F383B_P_2,
2142   VEX_W_0F383C_P_2,
2143   VEX_W_0F383D_P_2,
2144   VEX_W_0F383E_P_2,
2145   VEX_W_0F383F_P_2,
2146   VEX_W_0F3840_P_2,
2147   VEX_W_0F3841_P_2,
2148   VEX_W_0F3846_P_2,
2149   VEX_W_0F3858_P_2,
2150   VEX_W_0F3859_P_2,
2151   VEX_W_0F385A_P_2_M_0,
2152   VEX_W_0F3878_P_2,
2153   VEX_W_0F3879_P_2,
2154   VEX_W_0F38DB_P_2,
2155   VEX_W_0F38DC_P_2,
2156   VEX_W_0F38DD_P_2,
2157   VEX_W_0F38DE_P_2,
2158   VEX_W_0F38DF_P_2,
2159   VEX_W_0F3A00_P_2,
2160   VEX_W_0F3A01_P_2,
2161   VEX_W_0F3A02_P_2,
2162   VEX_W_0F3A04_P_2,
2163   VEX_W_0F3A05_P_2,
2164   VEX_W_0F3A06_P_2,
2165   VEX_W_0F3A08_P_2,
2166   VEX_W_0F3A09_P_2,
2167   VEX_W_0F3A0A_P_2,
2168   VEX_W_0F3A0B_P_2,
2169   VEX_W_0F3A0C_P_2,
2170   VEX_W_0F3A0D_P_2,
2171   VEX_W_0F3A0E_P_2,
2172   VEX_W_0F3A0F_P_2,
2173   VEX_W_0F3A14_P_2,
2174   VEX_W_0F3A15_P_2,
2175   VEX_W_0F3A18_P_2,
2176   VEX_W_0F3A19_P_2,
2177   VEX_W_0F3A20_P_2,
2178   VEX_W_0F3A21_P_2,
2179   VEX_W_0F3A30_P_2_LEN_0,
2180   VEX_W_0F3A31_P_2_LEN_0,
2181   VEX_W_0F3A32_P_2_LEN_0,
2182   VEX_W_0F3A33_P_2_LEN_0,
2183   VEX_W_0F3A38_P_2,
2184   VEX_W_0F3A39_P_2,
2185   VEX_W_0F3A40_P_2,
2186   VEX_W_0F3A41_P_2,
2187   VEX_W_0F3A42_P_2,
2188   VEX_W_0F3A44_P_2,
2189   VEX_W_0F3A46_P_2,
2190   VEX_W_0F3A48_P_2,
2191   VEX_W_0F3A49_P_2,
2192   VEX_W_0F3A4A_P_2,
2193   VEX_W_0F3A4B_P_2,
2194   VEX_W_0F3A4C_P_2,
2195   VEX_W_0F3A62_P_2,
2196   VEX_W_0F3A63_P_2,
2197   VEX_W_0F3ADF_P_2,
2198
2199   EVEX_W_0F10_P_0,
2200   EVEX_W_0F10_P_1_M_0,
2201   EVEX_W_0F10_P_1_M_1,
2202   EVEX_W_0F10_P_2,
2203   EVEX_W_0F10_P_3_M_0,
2204   EVEX_W_0F10_P_3_M_1,
2205   EVEX_W_0F11_P_0,
2206   EVEX_W_0F11_P_1_M_0,
2207   EVEX_W_0F11_P_1_M_1,
2208   EVEX_W_0F11_P_2,
2209   EVEX_W_0F11_P_3_M_0,
2210   EVEX_W_0F11_P_3_M_1,
2211   EVEX_W_0F12_P_0_M_0,
2212   EVEX_W_0F12_P_0_M_1,
2213   EVEX_W_0F12_P_1,
2214   EVEX_W_0F12_P_2,
2215   EVEX_W_0F12_P_3,
2216   EVEX_W_0F13_P_0,
2217   EVEX_W_0F13_P_2,
2218   EVEX_W_0F14_P_0,
2219   EVEX_W_0F14_P_2,
2220   EVEX_W_0F15_P_0,
2221   EVEX_W_0F15_P_2,
2222   EVEX_W_0F16_P_0_M_0,
2223   EVEX_W_0F16_P_0_M_1,
2224   EVEX_W_0F16_P_1,
2225   EVEX_W_0F16_P_2,
2226   EVEX_W_0F17_P_0,
2227   EVEX_W_0F17_P_2,
2228   EVEX_W_0F28_P_0,
2229   EVEX_W_0F28_P_2,
2230   EVEX_W_0F29_P_0,
2231   EVEX_W_0F29_P_2,
2232   EVEX_W_0F2A_P_1,
2233   EVEX_W_0F2A_P_3,
2234   EVEX_W_0F2B_P_0,
2235   EVEX_W_0F2B_P_2,
2236   EVEX_W_0F2E_P_0,
2237   EVEX_W_0F2E_P_2,
2238   EVEX_W_0F2F_P_0,
2239   EVEX_W_0F2F_P_2,
2240   EVEX_W_0F51_P_0,
2241   EVEX_W_0F51_P_1,
2242   EVEX_W_0F51_P_2,
2243   EVEX_W_0F51_P_3,
2244   EVEX_W_0F54_P_0,
2245   EVEX_W_0F54_P_2,
2246   EVEX_W_0F55_P_0,
2247   EVEX_W_0F55_P_2,
2248   EVEX_W_0F56_P_0,
2249   EVEX_W_0F56_P_2,
2250   EVEX_W_0F57_P_0,
2251   EVEX_W_0F57_P_2,
2252   EVEX_W_0F58_P_0,
2253   EVEX_W_0F58_P_1,
2254   EVEX_W_0F58_P_2,
2255   EVEX_W_0F58_P_3,
2256   EVEX_W_0F59_P_0,
2257   EVEX_W_0F59_P_1,
2258   EVEX_W_0F59_P_2,
2259   EVEX_W_0F59_P_3,
2260   EVEX_W_0F5A_P_0,
2261   EVEX_W_0F5A_P_1,
2262   EVEX_W_0F5A_P_2,
2263   EVEX_W_0F5A_P_3,
2264   EVEX_W_0F5B_P_0,
2265   EVEX_W_0F5B_P_1,
2266   EVEX_W_0F5B_P_2,
2267   EVEX_W_0F5C_P_0,
2268   EVEX_W_0F5C_P_1,
2269   EVEX_W_0F5C_P_2,
2270   EVEX_W_0F5C_P_3,
2271   EVEX_W_0F5D_P_0,
2272   EVEX_W_0F5D_P_1,
2273   EVEX_W_0F5D_P_2,
2274   EVEX_W_0F5D_P_3,
2275   EVEX_W_0F5E_P_0,
2276   EVEX_W_0F5E_P_1,
2277   EVEX_W_0F5E_P_2,
2278   EVEX_W_0F5E_P_3,
2279   EVEX_W_0F5F_P_0,
2280   EVEX_W_0F5F_P_1,
2281   EVEX_W_0F5F_P_2,
2282   EVEX_W_0F5F_P_3,
2283   EVEX_W_0F62_P_2,
2284   EVEX_W_0F66_P_2,
2285   EVEX_W_0F6A_P_2,
2286   EVEX_W_0F6B_P_2,
2287   EVEX_W_0F6C_P_2,
2288   EVEX_W_0F6D_P_2,
2289   EVEX_W_0F6E_P_2,
2290   EVEX_W_0F6F_P_1,
2291   EVEX_W_0F6F_P_2,
2292   EVEX_W_0F6F_P_3,
2293   EVEX_W_0F70_P_2,
2294   EVEX_W_0F72_R_2_P_2,
2295   EVEX_W_0F72_R_6_P_2,
2296   EVEX_W_0F73_R_2_P_2,
2297   EVEX_W_0F73_R_6_P_2,
2298   EVEX_W_0F76_P_2,
2299   EVEX_W_0F78_P_0,
2300   EVEX_W_0F78_P_2,
2301   EVEX_W_0F79_P_0,
2302   EVEX_W_0F79_P_2,
2303   EVEX_W_0F7A_P_1,
2304   EVEX_W_0F7A_P_2,
2305   EVEX_W_0F7A_P_3,
2306   EVEX_W_0F7B_P_1,
2307   EVEX_W_0F7B_P_2,
2308   EVEX_W_0F7B_P_3,
2309   EVEX_W_0F7E_P_1,
2310   EVEX_W_0F7E_P_2,
2311   EVEX_W_0F7F_P_1,
2312   EVEX_W_0F7F_P_2,
2313   EVEX_W_0F7F_P_3,
2314   EVEX_W_0FC2_P_0,
2315   EVEX_W_0FC2_P_1,
2316   EVEX_W_0FC2_P_2,
2317   EVEX_W_0FC2_P_3,
2318   EVEX_W_0FC6_P_0,
2319   EVEX_W_0FC6_P_2,
2320   EVEX_W_0FD2_P_2,
2321   EVEX_W_0FD3_P_2,
2322   EVEX_W_0FD4_P_2,
2323   EVEX_W_0FD6_P_2,
2324   EVEX_W_0FE6_P_1,
2325   EVEX_W_0FE6_P_2,
2326   EVEX_W_0FE6_P_3,
2327   EVEX_W_0FE7_P_2,
2328   EVEX_W_0FF2_P_2,
2329   EVEX_W_0FF3_P_2,
2330   EVEX_W_0FF4_P_2,
2331   EVEX_W_0FFA_P_2,
2332   EVEX_W_0FFB_P_2,
2333   EVEX_W_0FFE_P_2,
2334   EVEX_W_0F380C_P_2,
2335   EVEX_W_0F380D_P_2,
2336   EVEX_W_0F3810_P_1,
2337   EVEX_W_0F3810_P_2,
2338   EVEX_W_0F3811_P_1,
2339   EVEX_W_0F3811_P_2,
2340   EVEX_W_0F3812_P_1,
2341   EVEX_W_0F3812_P_2,
2342   EVEX_W_0F3813_P_1,
2343   EVEX_W_0F3813_P_2,
2344   EVEX_W_0F3814_P_1,
2345   EVEX_W_0F3815_P_1,
2346   EVEX_W_0F3818_P_2,
2347   EVEX_W_0F3819_P_2,
2348   EVEX_W_0F381A_P_2,
2349   EVEX_W_0F381B_P_2,
2350   EVEX_W_0F381E_P_2,
2351   EVEX_W_0F381F_P_2,
2352   EVEX_W_0F3820_P_1,
2353   EVEX_W_0F3821_P_1,
2354   EVEX_W_0F3822_P_1,
2355   EVEX_W_0F3823_P_1,
2356   EVEX_W_0F3824_P_1,
2357   EVEX_W_0F3825_P_1,
2358   EVEX_W_0F3825_P_2,
2359   EVEX_W_0F3826_P_1,
2360   EVEX_W_0F3826_P_2,
2361   EVEX_W_0F3828_P_1,
2362   EVEX_W_0F3828_P_2,
2363   EVEX_W_0F3829_P_1,
2364   EVEX_W_0F3829_P_2,
2365   EVEX_W_0F382A_P_1,
2366   EVEX_W_0F382A_P_2,
2367   EVEX_W_0F382B_P_2,
2368   EVEX_W_0F3830_P_1,
2369   EVEX_W_0F3831_P_1,
2370   EVEX_W_0F3832_P_1,
2371   EVEX_W_0F3833_P_1,
2372   EVEX_W_0F3834_P_1,
2373   EVEX_W_0F3835_P_1,
2374   EVEX_W_0F3835_P_2,
2375   EVEX_W_0F3837_P_2,
2376   EVEX_W_0F3838_P_1,
2377   EVEX_W_0F3839_P_1,
2378   EVEX_W_0F383A_P_1,
2379   EVEX_W_0F3840_P_2,
2380   EVEX_W_0F3855_P_2,
2381   EVEX_W_0F3858_P_2,
2382   EVEX_W_0F3859_P_2,
2383   EVEX_W_0F385A_P_2,
2384   EVEX_W_0F385B_P_2,
2385   EVEX_W_0F3866_P_2,
2386   EVEX_W_0F3875_P_2,
2387   EVEX_W_0F3878_P_2,
2388   EVEX_W_0F3879_P_2,
2389   EVEX_W_0F387A_P_2,
2390   EVEX_W_0F387B_P_2,
2391   EVEX_W_0F387D_P_2,
2392   EVEX_W_0F3883_P_2,
2393   EVEX_W_0F388D_P_2,
2394   EVEX_W_0F3891_P_2,
2395   EVEX_W_0F3893_P_2,
2396   EVEX_W_0F38A1_P_2,
2397   EVEX_W_0F38A3_P_2,
2398   EVEX_W_0F38C7_R_1_P_2,
2399   EVEX_W_0F38C7_R_2_P_2,
2400   EVEX_W_0F38C7_R_5_P_2,
2401   EVEX_W_0F38C7_R_6_P_2,
2402
2403   EVEX_W_0F3A00_P_2,
2404   EVEX_W_0F3A01_P_2,
2405   EVEX_W_0F3A04_P_2,
2406   EVEX_W_0F3A05_P_2,
2407   EVEX_W_0F3A08_P_2,
2408   EVEX_W_0F3A09_P_2,
2409   EVEX_W_0F3A0A_P_2,
2410   EVEX_W_0F3A0B_P_2,
2411   EVEX_W_0F3A16_P_2,
2412   EVEX_W_0F3A18_P_2,
2413   EVEX_W_0F3A19_P_2,
2414   EVEX_W_0F3A1A_P_2,
2415   EVEX_W_0F3A1B_P_2,
2416   EVEX_W_0F3A1D_P_2,
2417   EVEX_W_0F3A21_P_2,
2418   EVEX_W_0F3A22_P_2,
2419   EVEX_W_0F3A23_P_2,
2420   EVEX_W_0F3A38_P_2,
2421   EVEX_W_0F3A39_P_2,
2422   EVEX_W_0F3A3A_P_2,
2423   EVEX_W_0F3A3B_P_2,
2424   EVEX_W_0F3A3E_P_2,
2425   EVEX_W_0F3A3F_P_2,
2426   EVEX_W_0F3A42_P_2,
2427   EVEX_W_0F3A43_P_2,
2428   EVEX_W_0F3A50_P_2,
2429   EVEX_W_0F3A51_P_2,
2430   EVEX_W_0F3A56_P_2,
2431   EVEX_W_0F3A57_P_2,
2432   EVEX_W_0F3A66_P_2,
2433   EVEX_W_0F3A67_P_2
2434 };
2435
2436 typedef void (*op_rtn) (int bytemode, int sizeflag);
2437
2438 struct dis386 {
2439   const char *name;
2440   struct
2441     {
2442       op_rtn rtn;
2443       int bytemode;
2444     } op[MAX_OPERANDS];
2445   unsigned int prefix_requirement;
2446 };
2447
2448 /* Upper case letters in the instruction names here are macros.
2449    'A' => print 'b' if no register operands or suffix_always is true
2450    'B' => print 'b' if suffix_always is true
2451    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2452           size prefix
2453    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2454           suffix_always is true
2455    'E' => print 'e' if 32-bit form of jcxz
2456    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2457    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2458    'H' => print ",pt" or ",pn" branch hint
2459    'I' => honor following macro letter even in Intel mode (implemented only
2460           for some of the macro letters)
2461    'J' => print 'l'
2462    'K' => print 'd' or 'q' if rex prefix is present.
2463    'L' => print 'l' if suffix_always is true
2464    'M' => print 'r' if intel_mnemonic is false.
2465    'N' => print 'n' if instruction has no wait "prefix"
2466    'O' => print 'd' or 'o' (or 'q' in Intel mode)
2467    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2468           or suffix_always is true.  print 'q' if rex prefix is present.
2469    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2470           is true
2471    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2472    'S' => print 'w', 'l' or 'q' if suffix_always is true
2473    'T' => print 'q' in 64bit mode if instruction has no operand size
2474           prefix and behave as 'P' otherwise
2475    'U' => print 'q' in 64bit mode if instruction has no operand size
2476           prefix and behave as 'Q' otherwise
2477    'V' => print 'q' in 64bit mode if instruction has no operand size
2478           prefix and behave as 'S' otherwise
2479    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2480    'X' => print 's', 'd' depending on data16 prefix (for XMM)
2481    'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
2482           suffix_always is true.
2483    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2484    '!' => change condition from true to false or from false to true.
2485    '%' => add 1 upper case letter to the macro.
2486    '^' => print 'w' or 'l' depending on operand size prefix or
2487           suffix_always is true (lcall/ljmp).
2488    '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2489           on operand size prefix.
2490    '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2491           has no operand size prefix for AMD64 ISA, behave as 'P'
2492           otherwise
2493
2494    2 upper case letter macros:
2495    "XY" => print 'x' or 'y' if suffix_always is true or no register
2496            operands and no broadcast.
2497    "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2498            register operands and no broadcast.
2499    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2500    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2501            or suffix_always is true
2502    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2503    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2504    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2505    "LW" => print 'd', 'q' depending on the VEX.W bit
2506    "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2507            an operand size prefix, or suffix_always is true.  print
2508            'q' if rex prefix is present.
2509
2510    Many of the above letters print nothing in Intel mode.  See "putop"
2511    for the details.
2512
2513    Braces '{' and '}', and vertical bars '|', indicate alternative
2514    mnemonic strings for AT&T and Intel.  */
2515
2516 static const struct dis386 dis386[] = {
2517   /* 00 */
2518   { "addB",             { Ebh1, Gb }, 0 },
2519   { "addS",             { Evh1, Gv }, 0 },
2520   { "addB",             { Gb, EbS }, 0 },
2521   { "addS",             { Gv, EvS }, 0 },
2522   { "addB",             { AL, Ib }, 0 },
2523   { "addS",             { eAX, Iv }, 0 },
2524   { X86_64_TABLE (X86_64_06) },
2525   { X86_64_TABLE (X86_64_07) },
2526   /* 08 */
2527   { "orB",              { Ebh1, Gb }, 0 },
2528   { "orS",              { Evh1, Gv }, 0 },
2529   { "orB",              { Gb, EbS }, 0 },
2530   { "orS",              { Gv, EvS }, 0 },
2531   { "orB",              { AL, Ib }, 0 },
2532   { "orS",              { eAX, Iv }, 0 },
2533   { X86_64_TABLE (X86_64_0D) },
2534   { Bad_Opcode },       /* 0x0f extended opcode escape */
2535   /* 10 */
2536   { "adcB",             { Ebh1, Gb }, 0 },
2537   { "adcS",             { Evh1, Gv }, 0 },
2538   { "adcB",             { Gb, EbS }, 0 },
2539   { "adcS",             { Gv, EvS }, 0 },
2540   { "adcB",             { AL, Ib }, 0 },
2541   { "adcS",             { eAX, Iv }, 0 },
2542   { X86_64_TABLE (X86_64_16) },
2543   { X86_64_TABLE (X86_64_17) },
2544   /* 18 */
2545   { "sbbB",             { Ebh1, Gb }, 0 },
2546   { "sbbS",             { Evh1, Gv }, 0 },
2547   { "sbbB",             { Gb, EbS }, 0 },
2548   { "sbbS",             { Gv, EvS }, 0 },
2549   { "sbbB",             { AL, Ib }, 0 },
2550   { "sbbS",             { eAX, Iv }, 0 },
2551   { X86_64_TABLE (X86_64_1E) },
2552   { X86_64_TABLE (X86_64_1F) },
2553   /* 20 */
2554   { "andB",             { Ebh1, Gb }, 0 },
2555   { "andS",             { Evh1, Gv }, 0 },
2556   { "andB",             { Gb, EbS }, 0 },
2557   { "andS",             { Gv, EvS }, 0 },
2558   { "andB",             { AL, Ib }, 0 },
2559   { "andS",             { eAX, Iv }, 0 },
2560   { Bad_Opcode },       /* SEG ES prefix */
2561   { X86_64_TABLE (X86_64_27) },
2562   /* 28 */
2563   { "subB",             { Ebh1, Gb }, 0 },
2564   { "subS",             { Evh1, Gv }, 0 },
2565   { "subB",             { Gb, EbS }, 0 },
2566   { "subS",             { Gv, EvS }, 0 },
2567   { "subB",             { AL, Ib }, 0 },
2568   { "subS",             { eAX, Iv }, 0 },
2569   { Bad_Opcode },       /* SEG CS prefix */
2570   { X86_64_TABLE (X86_64_2F) },
2571   /* 30 */
2572   { "xorB",             { Ebh1, Gb }, 0 },
2573   { "xorS",             { Evh1, Gv }, 0 },
2574   { "xorB",             { Gb, EbS }, 0 },
2575   { "xorS",             { Gv, EvS }, 0 },
2576   { "xorB",             { AL, Ib }, 0 },
2577   { "xorS",             { eAX, Iv }, 0 },
2578   { Bad_Opcode },       /* SEG SS prefix */
2579   { X86_64_TABLE (X86_64_37) },
2580   /* 38 */
2581   { "cmpB",             { Eb, Gb }, 0 },
2582   { "cmpS",             { Ev, Gv }, 0 },
2583   { "cmpB",             { Gb, EbS }, 0 },
2584   { "cmpS",             { Gv, EvS }, 0 },
2585   { "cmpB",             { AL, Ib }, 0 },
2586   { "cmpS",             { eAX, Iv }, 0 },
2587   { Bad_Opcode },       /* SEG DS prefix */
2588   { X86_64_TABLE (X86_64_3F) },
2589   /* 40 */
2590   { "inc{S|}",          { RMeAX }, 0 },
2591   { "inc{S|}",          { RMeCX }, 0 },
2592   { "inc{S|}",          { RMeDX }, 0 },
2593   { "inc{S|}",          { RMeBX }, 0 },
2594   { "inc{S|}",          { RMeSP }, 0 },
2595   { "inc{S|}",          { RMeBP }, 0 },
2596   { "inc{S|}",          { RMeSI }, 0 },
2597   { "inc{S|}",          { RMeDI }, 0 },
2598   /* 48 */
2599   { "dec{S|}",          { RMeAX }, 0 },
2600   { "dec{S|}",          { RMeCX }, 0 },
2601   { "dec{S|}",          { RMeDX }, 0 },
2602   { "dec{S|}",          { RMeBX }, 0 },
2603   { "dec{S|}",          { RMeSP }, 0 },
2604   { "dec{S|}",          { RMeBP }, 0 },
2605   { "dec{S|}",          { RMeSI }, 0 },
2606   { "dec{S|}",          { RMeDI }, 0 },
2607   /* 50 */
2608   { "pushV",            { RMrAX }, 0 },
2609   { "pushV",            { RMrCX }, 0 },
2610   { "pushV",            { RMrDX }, 0 },
2611   { "pushV",            { RMrBX }, 0 },
2612   { "pushV",            { RMrSP }, 0 },
2613   { "pushV",            { RMrBP }, 0 },
2614   { "pushV",            { RMrSI }, 0 },
2615   { "pushV",            { RMrDI }, 0 },
2616   /* 58 */
2617   { "popV",             { RMrAX }, 0 },
2618   { "popV",             { RMrCX }, 0 },
2619   { "popV",             { RMrDX }, 0 },
2620   { "popV",             { RMrBX }, 0 },
2621   { "popV",             { RMrSP }, 0 },
2622   { "popV",             { RMrBP }, 0 },
2623   { "popV",             { RMrSI }, 0 },
2624   { "popV",             { RMrDI }, 0 },
2625   /* 60 */
2626   { X86_64_TABLE (X86_64_60) },
2627   { X86_64_TABLE (X86_64_61) },
2628   { X86_64_TABLE (X86_64_62) },
2629   { X86_64_TABLE (X86_64_63) },
2630   { Bad_Opcode },       /* seg fs */
2631   { Bad_Opcode },       /* seg gs */
2632   { Bad_Opcode },       /* op size prefix */
2633   { Bad_Opcode },       /* adr size prefix */
2634   /* 68 */
2635   { "pushT",            { sIv }, 0 },
2636   { "imulS",            { Gv, Ev, Iv }, 0 },
2637   { "pushT",            { sIbT }, 0 },
2638   { "imulS",            { Gv, Ev, sIb }, 0 },
2639   { "ins{b|}",          { Ybr, indirDX }, 0 },
2640   { X86_64_TABLE (X86_64_6D) },
2641   { "outs{b|}",         { indirDXr, Xb }, 0 },
2642   { X86_64_TABLE (X86_64_6F) },
2643   /* 70 */
2644   { "joH",              { Jb, BND, cond_jump_flag }, 0 },
2645   { "jnoH",             { Jb, BND, cond_jump_flag }, 0 },
2646   { "jbH",              { Jb, BND, cond_jump_flag }, 0 },
2647   { "jaeH",             { Jb, BND, cond_jump_flag }, 0 },
2648   { "jeH",              { Jb, BND, cond_jump_flag }, 0 },
2649   { "jneH",             { Jb, BND, cond_jump_flag }, 0 },
2650   { "jbeH",             { Jb, BND, cond_jump_flag }, 0 },
2651   { "jaH",              { Jb, BND, cond_jump_flag }, 0 },
2652   /* 78 */
2653   { "jsH",              { Jb, BND, cond_jump_flag }, 0 },
2654   { "jnsH",             { Jb, BND, cond_jump_flag }, 0 },
2655   { "jpH",              { Jb, BND, cond_jump_flag }, 0 },
2656   { "jnpH",             { Jb, BND, cond_jump_flag }, 0 },
2657   { "jlH",              { Jb, BND, cond_jump_flag }, 0 },
2658   { "jgeH",             { Jb, BND, cond_jump_flag }, 0 },
2659   { "jleH",             { Jb, BND, cond_jump_flag }, 0 },
2660   { "jgH",              { Jb, BND, cond_jump_flag }, 0 },
2661   /* 80 */
2662   { REG_TABLE (REG_80) },
2663   { REG_TABLE (REG_81) },
2664   { X86_64_TABLE (X86_64_82) },
2665   { REG_TABLE (REG_83) },
2666   { "testB",            { Eb, Gb }, 0 },
2667   { "testS",            { Ev, Gv }, 0 },
2668   { "xchgB",            { Ebh2, Gb }, 0 },
2669   { "xchgS",            { Evh2, Gv }, 0 },
2670   /* 88 */
2671   { "movB",             { Ebh3, Gb }, 0 },
2672   { "movS",             { Evh3, Gv }, 0 },
2673   { "movB",             { Gb, EbS }, 0 },
2674   { "movS",             { Gv, EvS }, 0 },
2675   { "movD",             { Sv, Sw }, 0 },
2676   { MOD_TABLE (MOD_8D) },
2677   { "movD",             { Sw, Sv }, 0 },
2678   { REG_TABLE (REG_8F) },
2679   /* 90 */
2680   { PREFIX_TABLE (PREFIX_90) },
2681   { "xchgS",            { RMeCX, eAX }, 0 },
2682   { "xchgS",            { RMeDX, eAX }, 0 },
2683   { "xchgS",            { RMeBX, eAX }, 0 },
2684   { "xchgS",            { RMeSP, eAX }, 0 },
2685   { "xchgS",            { RMeBP, eAX }, 0 },
2686   { "xchgS",            { RMeSI, eAX }, 0 },
2687   { "xchgS",            { RMeDI, eAX }, 0 },
2688   /* 98 */
2689   { "cW{t|}R",          { XX }, 0 },
2690   { "cR{t|}O",          { XX }, 0 },
2691   { X86_64_TABLE (X86_64_9A) },
2692   { Bad_Opcode },       /* fwait */
2693   { "pushfT",           { XX }, 0 },
2694   { "popfT",            { XX }, 0 },
2695   { "sahf",             { XX }, 0 },
2696   { "lahf",             { XX }, 0 },
2697   /* a0 */
2698   { "mov%LB",           { AL, Ob }, 0 },
2699   { "mov%LS",           { eAX, Ov }, 0 },
2700   { "mov%LB",           { Ob, AL }, 0 },
2701   { "mov%LS",           { Ov, eAX }, 0 },
2702   { "movs{b|}",         { Ybr, Xb }, 0 },
2703   { "movs{R|}",         { Yvr, Xv }, 0 },
2704   { "cmps{b|}",         { Xb, Yb }, 0 },
2705   { "cmps{R|}",         { Xv, Yv }, 0 },
2706   /* a8 */
2707   { "testB",            { AL, Ib }, 0 },
2708   { "testS",            { eAX, Iv }, 0 },
2709   { "stosB",            { Ybr, AL }, 0 },
2710   { "stosS",            { Yvr, eAX }, 0 },
2711   { "lodsB",            { ALr, Xb }, 0 },
2712   { "lodsS",            { eAXr, Xv }, 0 },
2713   { "scasB",            { AL, Yb }, 0 },
2714   { "scasS",            { eAX, Yv }, 0 },
2715   /* b0 */
2716   { "movB",             { RMAL, Ib }, 0 },
2717   { "movB",             { RMCL, Ib }, 0 },
2718   { "movB",             { RMDL, Ib }, 0 },
2719   { "movB",             { RMBL, Ib }, 0 },
2720   { "movB",             { RMAH, Ib }, 0 },
2721   { "movB",             { RMCH, Ib }, 0 },
2722   { "movB",             { RMDH, Ib }, 0 },
2723   { "movB",             { RMBH, Ib }, 0 },
2724   /* b8 */
2725   { "mov%LV",           { RMeAX, Iv64 }, 0 },
2726   { "mov%LV",           { RMeCX, Iv64 }, 0 },
2727   { "mov%LV",           { RMeDX, Iv64 }, 0 },
2728   { "mov%LV",           { RMeBX, Iv64 }, 0 },
2729   { "mov%LV",           { RMeSP, Iv64 }, 0 },
2730   { "mov%LV",           { RMeBP, Iv64 }, 0 },
2731   { "mov%LV",           { RMeSI, Iv64 }, 0 },
2732   { "mov%LV",           { RMeDI, Iv64 }, 0 },
2733   /* c0 */
2734   { REG_TABLE (REG_C0) },
2735   { REG_TABLE (REG_C1) },
2736   { "retT",             { Iw, BND }, 0 },
2737   { "retT",             { BND }, 0 },
2738   { X86_64_TABLE (X86_64_C4) },
2739   { X86_64_TABLE (X86_64_C5) },
2740   { REG_TABLE (REG_C6) },
2741   { REG_TABLE (REG_C7) },
2742   /* c8 */
2743   { "enterT",           { Iw, Ib }, 0 },
2744   { "leaveT",           { XX }, 0 },
2745   { "Jret{|f}P",        { Iw }, 0 },
2746   { "Jret{|f}P",        { XX }, 0 },
2747   { "int3",             { XX }, 0 },
2748   { "int",              { Ib }, 0 },
2749   { X86_64_TABLE (X86_64_CE) },
2750   { "iret%LP",          { XX }, 0 },
2751   /* d0 */
2752   { REG_TABLE (REG_D0) },
2753   { REG_TABLE (REG_D1) },
2754   { REG_TABLE (REG_D2) },
2755   { REG_TABLE (REG_D3) },
2756   { X86_64_TABLE (X86_64_D4) },
2757   { X86_64_TABLE (X86_64_D5) },
2758   { Bad_Opcode },
2759   { "xlat",             { DSBX }, 0 },
2760   /* d8 */
2761   { FLOAT },
2762   { FLOAT },
2763   { FLOAT },
2764   { FLOAT },
2765   { FLOAT },
2766   { FLOAT },
2767   { FLOAT },
2768   { FLOAT },
2769   /* e0 */
2770   { "loopneFH",         { Jb, XX, loop_jcxz_flag }, 0 },
2771   { "loopeFH",          { Jb, XX, loop_jcxz_flag }, 0 },
2772   { "loopFH",           { Jb, XX, loop_jcxz_flag }, 0 },
2773   { "jEcxzH",           { Jb, XX, loop_jcxz_flag }, 0 },
2774   { "inB",              { AL, Ib }, 0 },
2775   { "inG",              { zAX, Ib }, 0 },
2776   { "outB",             { Ib, AL }, 0 },
2777   { "outG",             { Ib, zAX }, 0 },
2778   /* e8 */
2779   { X86_64_TABLE (X86_64_E8) },
2780   { X86_64_TABLE (X86_64_E9) },
2781   { X86_64_TABLE (X86_64_EA) },
2782   { "jmp",              { Jb, BND }, 0 },
2783   { "inB",              { AL, indirDX }, 0 },
2784   { "inG",              { zAX, indirDX }, 0 },
2785   { "outB",             { indirDX, AL }, 0 },
2786   { "outG",             { indirDX, zAX }, 0 },
2787   /* f0 */
2788   { Bad_Opcode },       /* lock prefix */
2789   { "icebp",            { XX }, 0 },
2790   { Bad_Opcode },       /* repne */
2791   { Bad_Opcode },       /* repz */
2792   { "hlt",              { XX }, 0 },
2793   { "cmc",              { XX }, 0 },
2794   { REG_TABLE (REG_F6) },
2795   { REG_TABLE (REG_F7) },
2796   /* f8 */
2797   { "clc",              { XX }, 0 },
2798   { "stc",              { XX }, 0 },
2799   { "cli",              { XX }, 0 },
2800   { "sti",              { XX }, 0 },
2801   { "cld",              { XX }, 0 },
2802   { "std",              { XX }, 0 },
2803   { REG_TABLE (REG_FE) },
2804   { REG_TABLE (REG_FF) },
2805 };
2806
2807 static const struct dis386 dis386_twobyte[] = {
2808   /* 00 */
2809   { REG_TABLE (REG_0F00 ) },
2810   { REG_TABLE (REG_0F01 ) },
2811   { "larS",             { Gv, Ew }, 0 },
2812   { "lslS",             { Gv, Ew }, 0 },
2813   { Bad_Opcode },
2814   { "syscall",          { XX }, 0 },
2815   { "clts",             { XX }, 0 },
2816   { "sysret%LP",                { XX }, 0 },
2817   /* 08 */
2818   { "invd",             { XX }, 0 },
2819   { "wbinvd",           { XX }, 0 },
2820   { Bad_Opcode },
2821   { "ud2",              { XX }, 0 },
2822   { Bad_Opcode },
2823   { REG_TABLE (REG_0F0D) },
2824   { "femms",            { XX }, 0 },
2825   { "",                 { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix.  */
2826   /* 10 */
2827   { PREFIX_TABLE (PREFIX_0F10) },
2828   { PREFIX_TABLE (PREFIX_0F11) },
2829   { PREFIX_TABLE (PREFIX_0F12) },
2830   { MOD_TABLE (MOD_0F13) },
2831   { "unpcklpX",         { XM, EXx }, PREFIX_OPCODE },
2832   { "unpckhpX",         { XM, EXx }, PREFIX_OPCODE },
2833   { PREFIX_TABLE (PREFIX_0F16) },
2834   { MOD_TABLE (MOD_0F17) },
2835   /* 18 */
2836   { REG_TABLE (REG_0F18) },
2837   { "nopQ",             { Ev }, 0 },
2838   { PREFIX_TABLE (PREFIX_0F1A) },
2839   { PREFIX_TABLE (PREFIX_0F1B) },
2840   { "nopQ",             { Ev }, 0 },
2841   { "nopQ",             { Ev }, 0 },
2842   { "nopQ",             { Ev }, 0 },
2843   { "nopQ",             { Ev }, 0 },
2844   /* 20 */
2845   { "movZ",             { Rm, Cm }, 0 },
2846   { "movZ",             { Rm, Dm }, 0 },
2847   { "movZ",             { Cm, Rm }, 0 },
2848   { "movZ",             { Dm, Rm }, 0 },
2849   { MOD_TABLE (MOD_0F24) },
2850   { Bad_Opcode },
2851   { MOD_TABLE (MOD_0F26) },
2852   { Bad_Opcode },
2853   /* 28 */
2854   { "movapX",           { XM, EXx }, PREFIX_OPCODE },
2855   { "movapX",           { EXxS, XM }, PREFIX_OPCODE },
2856   { PREFIX_TABLE (PREFIX_0F2A) },
2857   { PREFIX_TABLE (PREFIX_0F2B) },
2858   { PREFIX_TABLE (PREFIX_0F2C) },
2859   { PREFIX_TABLE (PREFIX_0F2D) },
2860   { PREFIX_TABLE (PREFIX_0F2E) },
2861   { PREFIX_TABLE (PREFIX_0F2F) },
2862   /* 30 */
2863   { "wrmsr",            { XX }, 0 },
2864   { "rdtsc",            { XX }, 0 },
2865   { "rdmsr",            { XX }, 0 },
2866   { "rdpmc",            { XX }, 0 },
2867   { "sysenter",         { XX }, 0 },
2868   { "sysexit",          { XX }, 0 },
2869   { Bad_Opcode },
2870   { "getsec",           { XX }, 0 },
2871   /* 38 */
2872   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2873   { Bad_Opcode },
2874   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2875   { Bad_Opcode },
2876   { Bad_Opcode },
2877   { Bad_Opcode },
2878   { Bad_Opcode },
2879   { Bad_Opcode },
2880   /* 40 */
2881   { "cmovoS",           { Gv, Ev }, 0 },
2882   { "cmovnoS",          { Gv, Ev }, 0 },
2883   { "cmovbS",           { Gv, Ev }, 0 },
2884   { "cmovaeS",          { Gv, Ev }, 0 },
2885   { "cmoveS",           { Gv, Ev }, 0 },
2886   { "cmovneS",          { Gv, Ev }, 0 },
2887   { "cmovbeS",          { Gv, Ev }, 0 },
2888   { "cmovaS",           { Gv, Ev }, 0 },
2889   /* 48 */
2890   { "cmovsS",           { Gv, Ev }, 0 },
2891   { "cmovnsS",          { Gv, Ev }, 0 },
2892   { "cmovpS",           { Gv, Ev }, 0 },
2893   { "cmovnpS",          { Gv, Ev }, 0 },
2894   { "cmovlS",           { Gv, Ev }, 0 },
2895   { "cmovgeS",          { Gv, Ev }, 0 },
2896   { "cmovleS",          { Gv, Ev }, 0 },
2897   { "cmovgS",           { Gv, Ev }, 0 },
2898   /* 50 */
2899   { MOD_TABLE (MOD_0F51) },
2900   { PREFIX_TABLE (PREFIX_0F51) },
2901   { PREFIX_TABLE (PREFIX_0F52) },
2902   { PREFIX_TABLE (PREFIX_0F53) },
2903   { "andpX",            { XM, EXx }, PREFIX_OPCODE },
2904   { "andnpX",           { XM, EXx }, PREFIX_OPCODE },
2905   { "orpX",             { XM, EXx }, PREFIX_OPCODE },
2906   { "xorpX",            { XM, EXx }, PREFIX_OPCODE },
2907   /* 58 */
2908   { PREFIX_TABLE (PREFIX_0F58) },
2909   { PREFIX_TABLE (PREFIX_0F59) },
2910   { PREFIX_TABLE (PREFIX_0F5A) },
2911   { PREFIX_TABLE (PREFIX_0F5B) },
2912   { PREFIX_TABLE (PREFIX_0F5C) },
2913   { PREFIX_TABLE (PREFIX_0F5D) },
2914   { PREFIX_TABLE (PREFIX_0F5E) },
2915   { PREFIX_TABLE (PREFIX_0F5F) },
2916   /* 60 */
2917   { PREFIX_TABLE (PREFIX_0F60) },
2918   { PREFIX_TABLE (PREFIX_0F61) },
2919   { PREFIX_TABLE (PREFIX_0F62) },
2920   { "packsswb",         { MX, EM }, PREFIX_OPCODE },
2921   { "pcmpgtb",          { MX, EM }, PREFIX_OPCODE },
2922   { "pcmpgtw",          { MX, EM }, PREFIX_OPCODE },
2923   { "pcmpgtd",          { MX, EM }, PREFIX_OPCODE },
2924   { "packuswb",         { MX, EM }, PREFIX_OPCODE },
2925   /* 68 */
2926   { "punpckhbw",        { MX, EM }, PREFIX_OPCODE },
2927   { "punpckhwd",        { MX, EM }, PREFIX_OPCODE },
2928   { "punpckhdq",        { MX, EM }, PREFIX_OPCODE },
2929   { "packssdw",         { MX, EM }, PREFIX_OPCODE },
2930   { PREFIX_TABLE (PREFIX_0F6C) },
2931   { PREFIX_TABLE (PREFIX_0F6D) },
2932   { "movK",             { MX, Edq }, PREFIX_OPCODE },
2933   { PREFIX_TABLE (PREFIX_0F6F) },
2934   /* 70 */
2935   { PREFIX_TABLE (PREFIX_0F70) },
2936   { REG_TABLE (REG_0F71) },
2937   { REG_TABLE (REG_0F72) },
2938   { REG_TABLE (REG_0F73) },
2939   { "pcmpeqb",          { MX, EM }, PREFIX_OPCODE },
2940   { "pcmpeqw",          { MX, EM }, PREFIX_OPCODE },
2941   { "pcmpeqd",          { MX, EM }, PREFIX_OPCODE },
2942   { "emms",             { XX }, PREFIX_OPCODE },
2943   /* 78 */
2944   { PREFIX_TABLE (PREFIX_0F78) },
2945   { PREFIX_TABLE (PREFIX_0F79) },
2946   { Bad_Opcode },
2947   { Bad_Opcode },
2948   { PREFIX_TABLE (PREFIX_0F7C) },
2949   { PREFIX_TABLE (PREFIX_0F7D) },
2950   { PREFIX_TABLE (PREFIX_0F7E) },
2951   { PREFIX_TABLE (PREFIX_0F7F) },
2952   /* 80 */
2953   { "joH",              { Jv, BND, cond_jump_flag }, 0 },
2954   { "jnoH",             { Jv, BND, cond_jump_flag }, 0 },
2955   { "jbH",              { Jv, BND, cond_jump_flag }, 0 },
2956   { "jaeH",             { Jv, BND, cond_jump_flag }, 0 },
2957   { "jeH",              { Jv, BND, cond_jump_flag }, 0 },
2958   { "jneH",             { Jv, BND, cond_jump_flag }, 0 },
2959   { "jbeH",             { Jv, BND, cond_jump_flag }, 0 },
2960   { "jaH",              { Jv, BND, cond_jump_flag }, 0 },
2961   /* 88 */
2962   { "jsH",              { Jv, BND, cond_jump_flag }, 0 },
2963   { "jnsH",             { Jv, BND, cond_jump_flag }, 0 },
2964   { "jpH",              { Jv, BND, cond_jump_flag }, 0 },
2965   { "jnpH",             { Jv, BND, cond_jump_flag }, 0 },
2966   { "jlH",              { Jv, BND, cond_jump_flag }, 0 },
2967   { "jgeH",             { Jv, BND, cond_jump_flag }, 0 },
2968   { "jleH",             { Jv, BND, cond_jump_flag }, 0 },
2969   { "jgH",              { Jv, BND, cond_jump_flag }, 0 },
2970   /* 90 */
2971   { "seto",             { Eb }, 0 },
2972   { "setno",            { Eb }, 0 },
2973   { "setb",             { Eb }, 0 },
2974   { "setae",            { Eb }, 0 },
2975   { "sete",             { Eb }, 0 },
2976   { "setne",            { Eb }, 0 },
2977   { "setbe",            { Eb }, 0 },
2978   { "seta",             { Eb }, 0 },
2979   /* 98 */
2980   { "sets",             { Eb }, 0 },
2981   { "setns",            { Eb }, 0 },
2982   { "setp",             { Eb }, 0 },
2983   { "setnp",            { Eb }, 0 },
2984   { "setl",             { Eb }, 0 },
2985   { "setge",            { Eb }, 0 },
2986   { "setle",            { Eb }, 0 },
2987   { "setg",             { Eb }, 0 },
2988   /* a0 */
2989   { "pushT",            { fs }, 0 },
2990   { "popT",             { fs }, 0 },
2991   { "cpuid",            { XX }, 0 },
2992   { "btS",              { Ev, Gv }, 0 },
2993   { "shldS",            { Ev, Gv, Ib }, 0 },
2994   { "shldS",            { Ev, Gv, CL }, 0 },
2995   { REG_TABLE (REG_0FA6) },
2996   { REG_TABLE (REG_0FA7) },
2997   /* a8 */
2998   { "pushT",            { gs }, 0 },
2999   { "popT",             { gs }, 0 },
3000   { "rsm",              { XX }, 0 },
3001   { "btsS",             { Evh1, Gv }, 0 },
3002   { "shrdS",            { Ev, Gv, Ib }, 0 },
3003   { "shrdS",            { Ev, Gv, CL }, 0 },
3004   { REG_TABLE (REG_0FAE) },
3005   { "imulS",            { Gv, Ev }, 0 },
3006   /* b0 */
3007   { "cmpxchgB",         { Ebh1, Gb }, 0 },
3008   { "cmpxchgS",         { Evh1, Gv }, 0 },
3009   { MOD_TABLE (MOD_0FB2) },
3010   { "btrS",             { Evh1, Gv }, 0 },
3011   { MOD_TABLE (MOD_0FB4) },
3012   { MOD_TABLE (MOD_0FB5) },
3013   { "movz{bR|x}",       { Gv, Eb }, 0 },
3014   { "movz{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
3015   /* b8 */
3016   { PREFIX_TABLE (PREFIX_0FB8) },
3017   { "ud1",              { XX }, 0 },
3018   { REG_TABLE (REG_0FBA) },
3019   { "btcS",             { Evh1, Gv }, 0 },
3020   { PREFIX_TABLE (PREFIX_0FBC) },
3021   { PREFIX_TABLE (PREFIX_0FBD) },
3022   { "movs{bR|x}",       { Gv, Eb }, 0 },
3023   { "movs{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
3024   /* c0 */
3025   { "xaddB",            { Ebh1, Gb }, 0 },
3026   { "xaddS",            { Evh1, Gv }, 0 },
3027   { PREFIX_TABLE (PREFIX_0FC2) },
3028   { MOD_TABLE (MOD_0FC3) },
3029   { "pinsrw",           { MX, Edqw, Ib }, PREFIX_OPCODE },
3030   { "pextrw",           { Gdq, MS, Ib }, PREFIX_OPCODE },
3031   { "shufpX",           { XM, EXx, Ib }, PREFIX_OPCODE },
3032   { REG_TABLE (REG_0FC7) },
3033   /* c8 */
3034   { "bswap",            { RMeAX }, 0 },
3035   { "bswap",            { RMeCX }, 0 },
3036   { "bswap",            { RMeDX }, 0 },
3037   { "bswap",            { RMeBX }, 0 },
3038   { "bswap",            { RMeSP }, 0 },
3039   { "bswap",            { RMeBP }, 0 },
3040   { "bswap",            { RMeSI }, 0 },
3041   { "bswap",            { RMeDI }, 0 },
3042   /* d0 */
3043   { PREFIX_TABLE (PREFIX_0FD0) },
3044   { "psrlw",            { MX, EM }, PREFIX_OPCODE },
3045   { "psrld",            { MX, EM }, PREFIX_OPCODE },
3046   { "psrlq",            { MX, EM }, PREFIX_OPCODE },
3047   { "paddq",            { MX, EM }, PREFIX_OPCODE },
3048   { "pmullw",           { MX, EM }, PREFIX_OPCODE },
3049   { PREFIX_TABLE (PREFIX_0FD6) },
3050   { MOD_TABLE (MOD_0FD7) },
3051   /* d8 */
3052   { "psubusb",          { MX, EM }, PREFIX_OPCODE },
3053   { "psubusw",          { MX, EM }, PREFIX_OPCODE },
3054   { "pminub",           { MX, EM }, PREFIX_OPCODE },
3055   { "pand",             { MX, EM }, PREFIX_OPCODE },
3056   { "paddusb",          { MX, EM }, PREFIX_OPCODE },
3057   { "paddusw",          { MX, EM }, PREFIX_OPCODE },
3058   { "pmaxub",           { MX, EM }, PREFIX_OPCODE },
3059   { "pandn",            { MX, EM }, PREFIX_OPCODE },
3060   /* e0 */
3061   { "pavgb",            { MX, EM }, PREFIX_OPCODE },
3062   { "psraw",            { MX, EM }, PREFIX_OPCODE },
3063   { "psrad",            { MX, EM }, PREFIX_OPCODE },
3064   { "pavgw",            { MX, EM }, PREFIX_OPCODE },
3065   { "pmulhuw",          { MX, EM }, PREFIX_OPCODE },
3066   { "pmulhw",           { MX, EM }, PREFIX_OPCODE },
3067   { PREFIX_TABLE (PREFIX_0FE6) },
3068   { PREFIX_TABLE (PREFIX_0FE7) },
3069   /* e8 */
3070   { "psubsb",           { MX, EM }, PREFIX_OPCODE },
3071   { "psubsw",           { MX, EM }, PREFIX_OPCODE },
3072   { "pminsw",           { MX, EM }, PREFIX_OPCODE },
3073   { "por",              { MX, EM }, PREFIX_OPCODE },
3074   { "paddsb",           { MX, EM }, PREFIX_OPCODE },
3075   { "paddsw",           { MX, EM }, PREFIX_OPCODE },
3076   { "pmaxsw",           { MX, EM }, PREFIX_OPCODE },
3077   { "pxor",             { MX, EM }, PREFIX_OPCODE },
3078   /* f0 */
3079   { PREFIX_TABLE (PREFIX_0FF0) },
3080   { "psllw",            { MX, EM }, PREFIX_OPCODE },
3081   { "pslld",            { MX, EM }, PREFIX_OPCODE },
3082   { "psllq",            { MX, EM }, PREFIX_OPCODE },
3083   { "pmuludq",          { MX, EM }, PREFIX_OPCODE },
3084   { "pmaddwd",          { MX, EM }, PREFIX_OPCODE },
3085   { "psadbw",           { MX, EM }, PREFIX_OPCODE },
3086   { PREFIX_TABLE (PREFIX_0FF7) },
3087   /* f8 */
3088   { "psubb",            { MX, EM }, PREFIX_OPCODE },
3089   { "psubw",            { MX, EM }, PREFIX_OPCODE },
3090   { "psubd",            { MX, EM }, PREFIX_OPCODE },
3091   { "psubq",            { MX, EM }, PREFIX_OPCODE },
3092   { "paddb",            { MX, EM }, PREFIX_OPCODE },
3093   { "paddw",            { MX, EM }, PREFIX_OPCODE },
3094   { "paddd",            { MX, EM }, PREFIX_OPCODE },
3095   { Bad_Opcode },
3096 };
3097
3098 static const unsigned char onebyte_has_modrm[256] = {
3099   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3100   /*       -------------------------------        */
3101   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
3102   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
3103   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
3104   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
3105   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
3106   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
3107   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
3108   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
3109   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
3110   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
3111   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
3112   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
3113   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
3114   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
3115   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
3116   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
3117   /*       -------------------------------        */
3118   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3119 };
3120
3121 static const unsigned char twobyte_has_modrm[256] = {
3122   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3123   /*       -------------------------------        */
3124   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
3125   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
3126   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
3127   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
3128   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
3129   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
3130   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
3131   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
3132   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
3133   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
3134   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
3135   /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
3136   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
3137   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
3138   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
3139   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0  /* ff */
3140   /*       -------------------------------        */
3141   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3142 };
3143
3144 static char obuf[100];
3145 static char *obufp;
3146 static char *mnemonicendp;
3147 static char scratchbuf[100];
3148 static unsigned char *start_codep;
3149 static unsigned char *insn_codep;
3150 static unsigned char *codep;
3151 static unsigned char *end_codep;
3152 static int last_lock_prefix;
3153 static int last_repz_prefix;
3154 static int last_repnz_prefix;
3155 static int last_data_prefix;
3156 static int last_addr_prefix;
3157 static int last_rex_prefix;
3158 static int last_seg_prefix;
3159 static int fwait_prefix;
3160 /* The active segment register prefix.  */
3161 static int active_seg_prefix;
3162 #define MAX_CODE_LENGTH 15
3163 /* We can up to 14 prefixes since the maximum instruction length is
3164    15bytes.  */
3165 static int all_prefixes[MAX_CODE_LENGTH - 1];
3166 static disassemble_info *the_info;
3167 static struct
3168   {
3169     int mod;
3170     int reg;
3171     int rm;
3172   }
3173 modrm;
3174 static unsigned char need_modrm;
3175 static struct
3176   {
3177     int scale;
3178     int index;
3179     int base;
3180   }
3181 sib;
3182 static struct
3183   {
3184     int register_specifier;
3185     int length;
3186     int prefix;
3187     int w;
3188     int evex;
3189     int r;
3190     int v;
3191     int mask_register_specifier;
3192     int zeroing;
3193     int ll;
3194     int b;
3195   }
3196 vex;
3197 static unsigned char need_vex;
3198 static unsigned char need_vex_reg;
3199 static unsigned char vex_w_done;
3200
3201 struct op
3202   {
3203     const char *name;
3204     unsigned int len;
3205   };
3206
3207 /* If we are accessing mod/rm/reg without need_modrm set, then the
3208    values are stale.  Hitting this abort likely indicates that you
3209    need to update onebyte_has_modrm or twobyte_has_modrm.  */
3210 #define MODRM_CHECK  if (!need_modrm) abort ()
3211
3212 static const char **names64;
3213 static const char **names32;
3214 static const char **names16;
3215 static const char **names8;
3216 static const char **names8rex;
3217 static const char **names_seg;
3218 static const char *index64;
3219 static const char *index32;
3220 static const char **index16;
3221 static const char **names_bnd;
3222
3223 static const char *intel_names64[] = {
3224   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3225   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3226 };
3227 static const char *intel_names32[] = {
3228   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3229   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3230 };
3231 static const char *intel_names16[] = {
3232   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3233   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3234 };
3235 static const char *intel_names8[] = {
3236   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3237 };
3238 static const char *intel_names8rex[] = {
3239   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3240   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3241 };
3242 static const char *intel_names_seg[] = {
3243   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3244 };
3245 static const char *intel_index64 = "riz";
3246 static const char *intel_index32 = "eiz";
3247 static const char *intel_index16[] = {
3248   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3249 };
3250
3251 static const char *att_names64[] = {
3252   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3253   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3254 };
3255 static const char *att_names32[] = {
3256   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3257   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3258 };
3259 static const char *att_names16[] = {
3260   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3261   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3262 };
3263 static const char *att_names8[] = {
3264   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3265 };
3266 static const char *att_names8rex[] = {
3267   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3268   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3269 };
3270 static const char *att_names_seg[] = {
3271   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3272 };
3273 static const char *att_index64 = "%riz";
3274 static const char *att_index32 = "%eiz";
3275 static const char *att_index16[] = {
3276   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3277 };
3278
3279 static const char **names_mm;
3280 static const char *intel_names_mm[] = {
3281   "mm0", "mm1", "mm2", "mm3",
3282   "mm4", "mm5", "mm6", "mm7"
3283 };
3284 static const char *att_names_mm[] = {
3285   "%mm0", "%mm1", "%mm2", "%mm3",
3286   "%mm4", "%mm5", "%mm6", "%mm7"
3287 };
3288
3289 static const char *intel_names_bnd[] = {
3290   "bnd0", "bnd1", "bnd2", "bnd3"
3291 };
3292
3293 static const char *att_names_bnd[] = {
3294   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3295 };
3296
3297 static const char **names_xmm;
3298 static const char *intel_names_xmm[] = {
3299   "xmm0", "xmm1", "xmm2", "xmm3",
3300   "xmm4", "xmm5", "xmm6", "xmm7",
3301   "xmm8", "xmm9", "xmm10", "xmm11",
3302   "xmm12", "xmm13", "xmm14", "xmm15",
3303   "xmm16", "xmm17", "xmm18", "xmm19",
3304   "xmm20", "xmm21", "xmm22", "xmm23",
3305   "xmm24", "xmm25", "xmm26", "xmm27",
3306   "xmm28", "xmm29", "xmm30", "xmm31"
3307 };
3308 static const char *att_names_xmm[] = {
3309   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3310   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3311   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3312   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3313   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3314   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3315   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3316   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3317 };
3318
3319 static const char **names_ymm;
3320 static const char *intel_names_ymm[] = {
3321   "ymm0", "ymm1", "ymm2", "ymm3",
3322   "ymm4", "ymm5", "ymm6", "ymm7",
3323   "ymm8", "ymm9", "ymm10", "ymm11",
3324   "ymm12", "ymm13", "ymm14", "ymm15",
3325   "ymm16", "ymm17", "ymm18", "ymm19",
3326   "ymm20", "ymm21", "ymm22", "ymm23",
3327   "ymm24", "ymm25", "ymm26", "ymm27",
3328   "ymm28", "ymm29", "ymm30", "ymm31"
3329 };
3330 static const char *att_names_ymm[] = {
3331   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3332   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3333   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3334   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3335   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3336   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3337   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3338   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3339 };
3340
3341 static const char **names_zmm;
3342 static const char *intel_names_zmm[] = {
3343   "zmm0", "zmm1", "zmm2", "zmm3",
3344   "zmm4", "zmm5", "zmm6", "zmm7",
3345   "zmm8", "zmm9", "zmm10", "zmm11",
3346   "zmm12", "zmm13", "zmm14", "zmm15",
3347   "zmm16", "zmm17", "zmm18", "zmm19",
3348   "zmm20", "zmm21", "zmm22", "zmm23",
3349   "zmm24", "zmm25", "zmm26", "zmm27",
3350   "zmm28", "zmm29", "zmm30", "zmm31"
3351 };
3352 static const char *att_names_zmm[] = {
3353   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3354   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3355   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3356   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3357   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3358   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3359   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3360   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3361 };
3362
3363 static const char **names_mask;
3364 static const char *intel_names_mask[] = {
3365   "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3366 };
3367 static const char *att_names_mask[] = {
3368   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3369 };
3370
3371 static const char *names_rounding[] =
3372 {
3373   "{rn-sae}",
3374   "{rd-sae}",
3375   "{ru-sae}",
3376   "{rz-sae}"
3377 };
3378
3379 static const struct dis386 reg_table[][8] = {
3380   /* REG_80 */
3381   {
3382     { "addA",   { Ebh1, Ib }, 0 },
3383     { "orA",    { Ebh1, Ib }, 0 },
3384     { "adcA",   { Ebh1, Ib }, 0 },
3385     { "sbbA",   { Ebh1, Ib }, 0 },
3386     { "andA",   { Ebh1, Ib }, 0 },
3387     { "subA",   { Ebh1, Ib }, 0 },
3388     { "xorA",   { Ebh1, Ib }, 0 },
3389     { "cmpA",   { Eb, Ib }, 0 },
3390   },
3391   /* REG_81 */
3392   {
3393     { "addQ",   { Evh1, Iv }, 0 },
3394     { "orQ",    { Evh1, Iv }, 0 },
3395     { "adcQ",   { Evh1, Iv }, 0 },
3396     { "sbbQ",   { Evh1, Iv }, 0 },
3397     { "andQ",   { Evh1, Iv }, 0 },
3398     { "subQ",   { Evh1, Iv }, 0 },
3399     { "xorQ",   { Evh1, Iv }, 0 },
3400     { "cmpQ",   { Ev, Iv }, 0 },
3401   },
3402   /* REG_83 */
3403   {
3404     { "addQ",   { Evh1, sIb }, 0 },
3405     { "orQ",    { Evh1, sIb }, 0 },
3406     { "adcQ",   { Evh1, sIb }, 0 },
3407     { "sbbQ",   { Evh1, sIb }, 0 },
3408     { "andQ",   { Evh1, sIb }, 0 },
3409     { "subQ",   { Evh1, sIb }, 0 },
3410     { "xorQ",   { Evh1, sIb }, 0 },
3411     { "cmpQ",   { Ev, sIb }, 0 },
3412   },
3413   /* REG_8F */
3414   {
3415     { "popU",   { stackEv }, 0 },
3416     { XOP_8F_TABLE (XOP_09) },
3417     { Bad_Opcode },
3418     { Bad_Opcode },
3419     { Bad_Opcode },
3420     { XOP_8F_TABLE (XOP_09) },
3421   },
3422   /* REG_C0 */
3423   {
3424     { "rolA",   { Eb, Ib }, 0 },
3425     { "rorA",   { Eb, Ib }, 0 },
3426     { "rclA",   { Eb, Ib }, 0 },
3427     { "rcrA",   { Eb, Ib }, 0 },
3428     { "shlA",   { Eb, Ib }, 0 },
3429     { "shrA",   { Eb, Ib }, 0 },
3430     { Bad_Opcode },
3431     { "sarA",   { Eb, Ib }, 0 },
3432   },
3433   /* REG_C1 */
3434   {
3435     { "rolQ",   { Ev, Ib }, 0 },
3436     { "rorQ",   { Ev, Ib }, 0 },
3437     { "rclQ",   { Ev, Ib }, 0 },
3438     { "rcrQ",   { Ev, Ib }, 0 },
3439     { "shlQ",   { Ev, Ib }, 0 },
3440     { "shrQ",   { Ev, Ib }, 0 },
3441     { Bad_Opcode },
3442     { "sarQ",   { Ev, Ib }, 0 },
3443   },
3444   /* REG_C6 */
3445   {
3446     { "movA",   { Ebh3, Ib }, 0 },
3447     { Bad_Opcode },
3448     { Bad_Opcode },
3449     { Bad_Opcode },
3450     { Bad_Opcode },
3451     { Bad_Opcode },
3452     { Bad_Opcode },
3453     { MOD_TABLE (MOD_C6_REG_7) },
3454   },
3455   /* REG_C7 */
3456   {
3457     { "movQ",   { Evh3, Iv }, 0 },
3458     { Bad_Opcode },
3459     { Bad_Opcode },
3460     { Bad_Opcode },
3461     { Bad_Opcode },
3462     { Bad_Opcode },
3463     { Bad_Opcode },
3464     { MOD_TABLE (MOD_C7_REG_7) },
3465   },
3466   /* REG_D0 */
3467   {
3468     { "rolA",   { Eb, I1 }, 0 },
3469     { "rorA",   { Eb, I1 }, 0 },
3470     { "rclA",   { Eb, I1 }, 0 },
3471     { "rcrA",   { Eb, I1 }, 0 },
3472     { "shlA",   { Eb, I1 }, 0 },
3473     { "shrA",   { Eb, I1 }, 0 },
3474     { Bad_Opcode },
3475     { "sarA",   { Eb, I1 }, 0 },
3476   },
3477   /* REG_D1 */
3478   {
3479     { "rolQ",   { Ev, I1 }, 0 },
3480     { "rorQ",   { Ev, I1 }, 0 },
3481     { "rclQ",   { Ev, I1 }, 0 },
3482     { "rcrQ",   { Ev, I1 }, 0 },
3483     { "shlQ",   { Ev, I1 }, 0 },
3484     { "shrQ",   { Ev, I1 }, 0 },
3485     { Bad_Opcode },
3486     { "sarQ",   { Ev, I1 }, 0 },
3487   },
3488   /* REG_D2 */
3489   {
3490     { "rolA",   { Eb, CL }, 0 },
3491     { "rorA",   { Eb, CL }, 0 },
3492     { "rclA",   { Eb, CL }, 0 },
3493     { "rcrA",   { Eb, CL }, 0 },
3494     { "shlA",   { Eb, CL }, 0 },
3495     { "shrA",   { Eb, CL }, 0 },
3496     { Bad_Opcode },
3497     { "sarA",   { Eb, CL }, 0 },
3498   },
3499   /* REG_D3 */
3500   {
3501     { "rolQ",   { Ev, CL }, 0 },
3502     { "rorQ",   { Ev, CL }, 0 },
3503     { "rclQ",   { Ev, CL }, 0 },
3504     { "rcrQ",   { Ev, CL }, 0 },
3505     { "shlQ",   { Ev, CL }, 0 },
3506     { "shrQ",   { Ev, CL }, 0 },
3507     { Bad_Opcode },
3508     { "sarQ",   { Ev, CL }, 0 },
3509   },
3510   /* REG_F6 */
3511   {
3512     { "testA",  { Eb, Ib }, 0 },
3513     { "testA",  { Eb, Ib }, 0 },
3514     { "notA",   { Ebh1 }, 0 },
3515     { "negA",   { Ebh1 }, 0 },
3516     { "mulA",   { Eb }, 0 },    /* Don't print the implicit %al register,  */
3517     { "imulA",  { Eb }, 0 },    /* to distinguish these opcodes from other */
3518     { "divA",   { Eb }, 0 },    /* mul/imul opcodes.  Do the same for div  */
3519     { "idivA",  { Eb }, 0 },    /* and idiv for consistency.               */
3520   },
3521   /* REG_F7 */
3522   {
3523     { "testQ",  { Ev, Iv }, 0 },
3524     { "testQ",  { Ev, Iv }, 0 },
3525     { "notQ",   { Evh1 }, 0 },
3526     { "negQ",   { Evh1 }, 0 },
3527     { "mulQ",   { Ev }, 0 },    /* Don't print the implicit register.  */
3528     { "imulQ",  { Ev }, 0 },
3529     { "divQ",   { Ev }, 0 },
3530     { "idivQ",  { Ev }, 0 },
3531   },
3532   /* REG_FE */
3533   {
3534     { "incA",   { Ebh1 }, 0 },
3535     { "decA",   { Ebh1 }, 0 },
3536   },
3537   /* REG_FF */
3538   {
3539     { "incQ",   { Evh1 }, 0 },
3540     { "decQ",   { Evh1 }, 0 },
3541     { "call{&|}", { indirEv, BND }, 0 },
3542     { MOD_TABLE (MOD_FF_REG_3) },
3543     { "jmp{&|}", { indirEv, BND }, 0 },
3544     { MOD_TABLE (MOD_FF_REG_5) },
3545     { "pushU",  { stackEv }, 0 },
3546     { Bad_Opcode },
3547   },
3548   /* REG_0F00 */
3549   {
3550     { "sldtD",  { Sv }, 0 },
3551     { "strD",   { Sv }, 0 },
3552     { "lldt",   { Ew }, 0 },
3553     { "ltr",    { Ew }, 0 },
3554     { "verr",   { Ew }, 0 },
3555     { "verw",   { Ew }, 0 },
3556     { Bad_Opcode },
3557     { Bad_Opcode },
3558   },
3559   /* REG_0F01 */
3560   {
3561     { MOD_TABLE (MOD_0F01_REG_0) },
3562     { MOD_TABLE (MOD_0F01_REG_1) },
3563     { MOD_TABLE (MOD_0F01_REG_2) },
3564     { MOD_TABLE (MOD_0F01_REG_3) },
3565     { "smswD",  { Sv }, 0 },
3566     { MOD_TABLE (MOD_0F01_REG_5) },
3567     { "lmsw",   { Ew }, 0 },
3568     { MOD_TABLE (MOD_0F01_REG_7) },
3569   },
3570   /* REG_0F0D */
3571   {
3572     { "prefetch",       { Mb }, 0 },
3573     { "prefetchw",      { Mb }, 0 },
3574     { "prefetchwt1",    { Mb }, 0 },
3575     { "prefetch",       { Mb }, 0 },
3576     { "prefetch",       { Mb }, 0 },
3577     { "prefetch",       { Mb }, 0 },
3578     { "prefetch",       { Mb }, 0 },
3579     { "prefetch",       { Mb }, 0 },
3580   },
3581   /* REG_0F18 */
3582   {
3583     { MOD_TABLE (MOD_0F18_REG_0) },
3584     { MOD_TABLE (MOD_0F18_REG_1) },
3585     { MOD_TABLE (MOD_0F18_REG_2) },
3586     { MOD_TABLE (MOD_0F18_REG_3) },
3587     { MOD_TABLE (MOD_0F18_REG_4) },
3588     { MOD_TABLE (MOD_0F18_REG_5) },
3589     { MOD_TABLE (MOD_0F18_REG_6) },
3590     { MOD_TABLE (MOD_0F18_REG_7) },
3591   },
3592   /* REG_0F71 */
3593   {
3594     { Bad_Opcode },
3595     { Bad_Opcode },
3596     { MOD_TABLE (MOD_0F71_REG_2) },
3597     { Bad_Opcode },
3598     { MOD_TABLE (MOD_0F71_REG_4) },
3599     { Bad_Opcode },
3600     { MOD_TABLE (MOD_0F71_REG_6) },
3601   },
3602   /* REG_0F72 */
3603   {
3604     { Bad_Opcode },
3605     { Bad_Opcode },
3606     { MOD_TABLE (MOD_0F72_REG_2) },
3607     { Bad_Opcode },
3608     { MOD_TABLE (MOD_0F72_REG_4) },
3609     { Bad_Opcode },
3610     { MOD_TABLE (MOD_0F72_REG_6) },
3611   },
3612   /* REG_0F73 */
3613   {
3614     { Bad_Opcode },
3615     { Bad_Opcode },
3616     { MOD_TABLE (MOD_0F73_REG_2) },
3617     { MOD_TABLE (MOD_0F73_REG_3) },
3618     { Bad_Opcode },
3619     { Bad_Opcode },
3620     { MOD_TABLE (MOD_0F73_REG_6) },
3621     { MOD_TABLE (MOD_0F73_REG_7) },
3622   },
3623   /* REG_0FA6 */
3624   {
3625     { "montmul",        { { OP_0f07, 0 } }, 0 },
3626     { "xsha1",          { { OP_0f07, 0 } }, 0 },
3627     { "xsha256",        { { OP_0f07, 0 } }, 0 },
3628   },
3629   /* REG_0FA7 */
3630   {
3631     { "xstore-rng",     { { OP_0f07, 0 } }, 0 },
3632     { "xcrypt-ecb",     { { OP_0f07, 0 } }, 0 },
3633     { "xcrypt-cbc",     { { OP_0f07, 0 } }, 0 },
3634     { "xcrypt-ctr",     { { OP_0f07, 0 } }, 0 },
3635     { "xcrypt-cfb",     { { OP_0f07, 0 } }, 0 },
3636     { "xcrypt-ofb",     { { OP_0f07, 0 } }, 0 },
3637   },
3638   /* REG_0FAE */
3639   {
3640     { MOD_TABLE (MOD_0FAE_REG_0) },
3641     { MOD_TABLE (MOD_0FAE_REG_1) },
3642     { MOD_TABLE (MOD_0FAE_REG_2) },
3643     { MOD_TABLE (MOD_0FAE_REG_3) },
3644     { MOD_TABLE (MOD_0FAE_REG_4) },
3645     { MOD_TABLE (MOD_0FAE_REG_5) },
3646     { MOD_TABLE (MOD_0FAE_REG_6) },
3647     { MOD_TABLE (MOD_0FAE_REG_7) },
3648   },
3649   /* REG_0FBA */
3650   {
3651     { Bad_Opcode },
3652     { Bad_Opcode },
3653     { Bad_Opcode },
3654     { Bad_Opcode },
3655     { "btQ",    { Ev, Ib }, 0 },
3656     { "btsQ",   { Evh1, Ib }, 0 },
3657     { "btrQ",   { Evh1, Ib }, 0 },
3658     { "btcQ",   { Evh1, Ib }, 0 },
3659   },
3660   /* REG_0FC7 */
3661   {
3662     { Bad_Opcode },
3663     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
3664     { Bad_Opcode },
3665     { MOD_TABLE (MOD_0FC7_REG_3) },
3666     { MOD_TABLE (MOD_0FC7_REG_4) },
3667     { MOD_TABLE (MOD_0FC7_REG_5) },
3668     { MOD_TABLE (MOD_0FC7_REG_6) },
3669     { MOD_TABLE (MOD_0FC7_REG_7) },
3670   },
3671   /* REG_VEX_0F71 */
3672   {
3673     { Bad_Opcode },
3674     { Bad_Opcode },
3675     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3676     { Bad_Opcode },
3677     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3678     { Bad_Opcode },
3679     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3680   },
3681   /* REG_VEX_0F72 */
3682   {
3683     { Bad_Opcode },
3684     { Bad_Opcode },
3685     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3686     { Bad_Opcode },
3687     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3688     { Bad_Opcode },
3689     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3690   },
3691   /* REG_VEX_0F73 */
3692   {
3693     { Bad_Opcode },
3694     { Bad_Opcode },
3695     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3696     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3697     { Bad_Opcode },
3698     { Bad_Opcode },
3699     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3700     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3701   },
3702   /* REG_VEX_0FAE */
3703   {
3704     { Bad_Opcode },
3705     { Bad_Opcode },
3706     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3707     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3708   },
3709   /* REG_VEX_0F38F3 */
3710   {
3711     { Bad_Opcode },
3712     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3713     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3714     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3715   },
3716   /* REG_XOP_LWPCB */
3717   {
3718     { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3719     { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3720   },
3721   /* REG_XOP_LWP */
3722   {
3723     { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3724     { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3725   },
3726   /* REG_XOP_TBM_01 */
3727   {
3728     { Bad_Opcode },
3729     { "blcfill",        { { OP_LWP_E, 0 }, Ev }, 0 },
3730     { "blsfill",        { { OP_LWP_E, 0 }, Ev }, 0 },
3731     { "blcs",   { { OP_LWP_E, 0 }, Ev }, 0 },
3732     { "tzmsk",  { { OP_LWP_E, 0 }, Ev }, 0 },
3733     { "blcic",  { { OP_LWP_E, 0 }, Ev }, 0 },
3734     { "blsic",  { { OP_LWP_E, 0 }, Ev }, 0 },
3735     { "t1mskc", { { OP_LWP_E, 0 }, Ev }, 0 },
3736   },
3737   /* REG_XOP_TBM_02 */
3738   {
3739     { Bad_Opcode },
3740     { "blcmsk", { { OP_LWP_E, 0 }, Ev }, 0 },
3741     { Bad_Opcode },
3742     { Bad_Opcode },
3743     { Bad_Opcode },
3744     { Bad_Opcode },
3745     { "blci",   { { OP_LWP_E, 0 }, Ev }, 0 },
3746   },
3747 #define NEED_REG_TABLE
3748 #include "i386-dis-evex.h"
3749 #undef NEED_REG_TABLE
3750 };
3751
3752 static const struct dis386 prefix_table[][4] = {
3753   /* PREFIX_90 */
3754   {
3755     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3756     { "pause", { XX }, 0 },
3757     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3758     { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3759   },
3760
3761   /* PREFIX_0F10 */
3762   {
3763     { "movups", { XM, EXx }, PREFIX_OPCODE },
3764     { "movss",  { XM, EXd }, PREFIX_OPCODE },
3765     { "movupd", { XM, EXx }, PREFIX_OPCODE },
3766     { "movsd",  { XM, EXq }, PREFIX_OPCODE },
3767   },
3768
3769   /* PREFIX_0F11 */
3770   {
3771     { "movups", { EXxS, XM }, PREFIX_OPCODE },
3772     { "movss",  { EXdS, XM }, PREFIX_OPCODE },
3773     { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3774     { "movsd",  { EXqS, XM }, PREFIX_OPCODE },
3775   },
3776
3777   /* PREFIX_0F12 */
3778   {
3779     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3780     { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3781     { "movlpd", { XM, EXq }, PREFIX_OPCODE },
3782     { "movddup", { XM, EXq }, PREFIX_OPCODE },
3783   },
3784
3785   /* PREFIX_0F16 */
3786   {
3787     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3788     { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3789     { "movhpd", { XM, EXq }, PREFIX_OPCODE },
3790   },
3791
3792   /* PREFIX_0F1A */
3793   {
3794     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3795     { "bndcl",  { Gbnd, Ev_bnd }, 0 },
3796     { "bndmov", { Gbnd, Ebnd }, 0 },
3797     { "bndcu",  { Gbnd, Ev_bnd }, 0 },
3798   },
3799
3800   /* PREFIX_0F1B */
3801   {
3802     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3803     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3804     { "bndmov", { Ebnd, Gbnd }, 0 },
3805     { "bndcn",  { Gbnd, Ev_bnd }, 0 },
3806   },
3807
3808   /* PREFIX_0F2A */
3809   {
3810     { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3811     { "cvtsi2ss%LQ", { XM, Ev }, PREFIX_OPCODE },
3812     { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3813     { "cvtsi2sd%LQ", { XM, Ev }, 0 },
3814   },
3815
3816   /* PREFIX_0F2B */
3817   {
3818     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3819     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3820     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3821     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3822   },
3823
3824   /* PREFIX_0F2C */
3825   {
3826     { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3827     { "cvttss2siY", { Gv, EXd }, PREFIX_OPCODE },
3828     { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3829     { "cvttsd2siY", { Gv, EXq }, PREFIX_OPCODE },
3830   },
3831
3832   /* PREFIX_0F2D */
3833   {
3834     { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3835     { "cvtss2siY", { Gv, EXd }, PREFIX_OPCODE },
3836     { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3837     { "cvtsd2siY", { Gv, EXq }, PREFIX_OPCODE },
3838   },
3839
3840   /* PREFIX_0F2E */
3841   {
3842     { "ucomiss",{ XM, EXd }, 0 },
3843     { Bad_Opcode },
3844     { "ucomisd",{ XM, EXq }, 0 },
3845   },
3846
3847   /* PREFIX_0F2F */
3848   {
3849     { "comiss", { XM, EXd }, 0 },
3850     { Bad_Opcode },
3851     { "comisd", { XM, EXq }, 0 },
3852   },
3853
3854   /* PREFIX_0F51 */
3855   {
3856     { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3857     { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3858     { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3859     { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3860   },
3861
3862   /* PREFIX_0F52 */
3863   {
3864     { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3865     { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3866   },
3867
3868   /* PREFIX_0F53 */
3869   {
3870     { "rcpps",  { XM, EXx }, PREFIX_OPCODE },
3871     { "rcpss",  { XM, EXd }, PREFIX_OPCODE },
3872   },
3873
3874   /* PREFIX_0F58 */
3875   {
3876     { "addps", { XM, EXx }, PREFIX_OPCODE },
3877     { "addss", { XM, EXd }, PREFIX_OPCODE },
3878     { "addpd", { XM, EXx }, PREFIX_OPCODE },
3879     { "addsd", { XM, EXq }, PREFIX_OPCODE },
3880   },
3881
3882   /* PREFIX_0F59 */
3883   {
3884     { "mulps",  { XM, EXx }, PREFIX_OPCODE },
3885     { "mulss",  { XM, EXd }, PREFIX_OPCODE },
3886     { "mulpd",  { XM, EXx }, PREFIX_OPCODE },
3887     { "mulsd",  { XM, EXq }, PREFIX_OPCODE },
3888   },
3889
3890   /* PREFIX_0F5A */
3891   {
3892     { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3893     { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3894     { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3895     { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3896   },
3897
3898   /* PREFIX_0F5B */
3899   {
3900     { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3901     { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3902     { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3903   },
3904
3905   /* PREFIX_0F5C */
3906   {
3907     { "subps",  { XM, EXx }, PREFIX_OPCODE },
3908     { "subss",  { XM, EXd }, PREFIX_OPCODE },
3909     { "subpd",  { XM, EXx }, PREFIX_OPCODE },
3910     { "subsd",  { XM, EXq }, PREFIX_OPCODE },
3911   },
3912
3913   /* PREFIX_0F5D */
3914   {
3915     { "minps",  { XM, EXx }, PREFIX_OPCODE },
3916     { "minss",  { XM, EXd }, PREFIX_OPCODE },
3917     { "minpd",  { XM, EXx }, PREFIX_OPCODE },
3918     { "minsd",  { XM, EXq }, PREFIX_OPCODE },
3919   },
3920
3921   /* PREFIX_0F5E */
3922   {
3923     { "divps",  { XM, EXx }, PREFIX_OPCODE },
3924     { "divss",  { XM, EXd }, PREFIX_OPCODE },
3925     { "divpd",  { XM, EXx }, PREFIX_OPCODE },
3926     { "divsd",  { XM, EXq }, PREFIX_OPCODE },
3927   },
3928
3929   /* PREFIX_0F5F */
3930   {
3931     { "maxps",  { XM, EXx }, PREFIX_OPCODE },
3932     { "maxss",  { XM, EXd }, PREFIX_OPCODE },
3933     { "maxpd",  { XM, EXx }, PREFIX_OPCODE },
3934     { "maxsd",  { XM, EXq }, PREFIX_OPCODE },
3935   },
3936
3937   /* PREFIX_0F60 */
3938   {
3939     { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3940     { Bad_Opcode },
3941     { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3942   },
3943
3944   /* PREFIX_0F61 */
3945   {
3946     { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3947     { Bad_Opcode },
3948     { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3949   },
3950
3951   /* PREFIX_0F62 */
3952   {
3953     { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3954     { Bad_Opcode },
3955     { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3956   },
3957
3958   /* PREFIX_0F6C */
3959   {
3960     { Bad_Opcode },
3961     { Bad_Opcode },
3962     { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE },
3963   },
3964
3965   /* PREFIX_0F6D */
3966   {
3967     { Bad_Opcode },
3968     { Bad_Opcode },
3969     { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE },
3970   },
3971
3972   /* PREFIX_0F6F */
3973   {
3974     { "movq",   { MX, EM }, PREFIX_OPCODE },
3975     { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3976     { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3977   },
3978
3979   /* PREFIX_0F70 */
3980   {
3981     { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3982     { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3983     { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3984     { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3985   },
3986
3987   /* PREFIX_0F73_REG_3 */
3988   {
3989     { Bad_Opcode },
3990     { Bad_Opcode },
3991     { "psrldq", { XS, Ib }, 0 },
3992   },
3993
3994   /* PREFIX_0F73_REG_7 */
3995   {
3996     { Bad_Opcode },
3997     { Bad_Opcode },
3998     { "pslldq", { XS, Ib }, 0 },
3999   },
4000
4001   /* PREFIX_0F78 */
4002   {
4003     {"vmread",  { Em, Gm }, 0 },
4004     { Bad_Opcode },
4005     {"extrq",   { XS, Ib, Ib }, 0 },
4006     {"insertq", { XM, XS, Ib, Ib }, 0 },
4007   },
4008
4009   /* PREFIX_0F79 */
4010   {
4011     {"vmwrite", { Gm, Em }, 0 },
4012     { Bad_Opcode },
4013     {"extrq",   { XM, XS }, 0 },
4014     {"insertq", { XM, XS }, 0 },
4015   },
4016
4017   /* PREFIX_0F7C */
4018   {
4019     { Bad_Opcode },
4020     { Bad_Opcode },
4021     { "haddpd", { XM, EXx }, PREFIX_OPCODE },
4022     { "haddps", { XM, EXx }, PREFIX_OPCODE },
4023   },
4024
4025   /* PREFIX_0F7D */
4026   {
4027     { Bad_Opcode },
4028     { Bad_Opcode },
4029     { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
4030     { "hsubps", { XM, EXx }, PREFIX_OPCODE },
4031   },
4032
4033   /* PREFIX_0F7E */
4034   {
4035     { "movK",   { Edq, MX }, PREFIX_OPCODE },
4036     { "movq",   { XM, EXq }, PREFIX_OPCODE },
4037     { "movK",   { Edq, XM }, PREFIX_OPCODE },
4038   },
4039
4040   /* PREFIX_0F7F */
4041   {
4042     { "movq",   { EMS, MX }, PREFIX_OPCODE },
4043     { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
4044     { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
4045   },
4046
4047   /* PREFIX_0FAE_REG_0 */
4048   {
4049     { Bad_Opcode },
4050     { "rdfsbase", { Ev }, 0 },
4051   },
4052
4053   /* PREFIX_0FAE_REG_1 */
4054   {
4055     { Bad_Opcode },
4056     { "rdgsbase", { Ev }, 0 },
4057   },
4058
4059   /* PREFIX_0FAE_REG_2 */
4060   {
4061     { Bad_Opcode },
4062     { "wrfsbase", { Ev }, 0 },
4063   },
4064
4065   /* PREFIX_0FAE_REG_3 */
4066   {
4067     { Bad_Opcode },
4068     { "wrgsbase", { Ev }, 0 },
4069   },
4070
4071   /* PREFIX_MOD_0_0FAE_REG_4 */
4072   {
4073     { "xsave",  { FXSAVE }, 0 },
4074     { "ptwrite%LQ", { Edq }, 0 },
4075   },
4076
4077   /* PREFIX_MOD_3_0FAE_REG_4 */
4078   {
4079     { Bad_Opcode },
4080     { "ptwrite%LQ", { Edq }, 0 },
4081   },
4082
4083   /* PREFIX_0FAE_REG_6 */
4084   {
4085     { "xsaveopt",      { FXSAVE }, 0 },
4086     { Bad_Opcode },
4087     { "clwb",   { Mb }, 0 },
4088   },
4089
4090   /* PREFIX_0FAE_REG_7 */
4091   {
4092     { "clflush",        { Mb }, 0 },
4093     { Bad_Opcode },
4094     { "clflushopt",     { Mb }, 0 },
4095   },
4096
4097   /* PREFIX_0FB8 */
4098   {
4099     { Bad_Opcode },
4100     { "popcntS", { Gv, Ev }, 0 },
4101   },
4102
4103   /* PREFIX_0FBC */
4104   {
4105     { "bsfS",   { Gv, Ev }, 0 },
4106     { "tzcntS", { Gv, Ev }, 0 },
4107     { "bsfS",   { Gv, Ev }, 0 },
4108   },
4109
4110   /* PREFIX_0FBD */
4111   {
4112     { "bsrS",   { Gv, Ev }, 0 },
4113     { "lzcntS", { Gv, Ev }, 0 },
4114     { "bsrS",   { Gv, Ev }, 0 },
4115   },
4116
4117   /* PREFIX_0FC2 */
4118   {
4119     { "cmpps",  { XM, EXx, CMP }, PREFIX_OPCODE },
4120     { "cmpss",  { XM, EXd, CMP }, PREFIX_OPCODE },
4121     { "cmppd",  { XM, EXx, CMP }, PREFIX_OPCODE },
4122     { "cmpsd",  { XM, EXq, CMP }, PREFIX_OPCODE },
4123   },
4124
4125   /* PREFIX_MOD_0_0FC3 */
4126   {
4127     { "movntiS", { Ev, Gv }, PREFIX_OPCODE },
4128   },
4129
4130   /* PREFIX_MOD_0_0FC7_REG_6 */
4131   {
4132     { "vmptrld",{ Mq }, 0 },
4133     { "vmxon",  { Mq }, 0 },
4134     { "vmclear",{ Mq }, 0 },
4135   },
4136
4137   /* PREFIX_MOD_3_0FC7_REG_6 */
4138   {
4139     { "rdrand", { Ev }, 0 },
4140     { Bad_Opcode },
4141     { "rdrand", { Ev }, 0 }
4142   },
4143
4144   /* PREFIX_MOD_3_0FC7_REG_7 */
4145   {
4146     { "rdseed", { Ev }, 0 },
4147     { "rdpid",  { Em }, 0 },
4148     { "rdseed", { Ev }, 0 },
4149   },
4150
4151   /* PREFIX_0FD0 */
4152   {
4153     { Bad_Opcode },
4154     { Bad_Opcode },
4155     { "addsubpd", { XM, EXx }, 0 },
4156     { "addsubps", { XM, EXx }, 0 },
4157   },
4158
4159   /* PREFIX_0FD6 */
4160   {
4161     { Bad_Opcode },
4162     { "movq2dq",{ XM, MS }, 0 },
4163     { "movq",   { EXqS, XM }, 0 },
4164     { "movdq2q",{ MX, XS }, 0 },
4165   },
4166
4167   /* PREFIX_0FE6 */
4168   {
4169     { Bad_Opcode },
4170     { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
4171     { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
4172     { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
4173   },
4174
4175   /* PREFIX_0FE7 */
4176   {
4177     { "movntq", { Mq, MX }, PREFIX_OPCODE },
4178     { Bad_Opcode },
4179     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
4180   },
4181
4182   /* PREFIX_0FF0 */
4183   {
4184     { Bad_Opcode },
4185     { Bad_Opcode },
4186     { Bad_Opcode },
4187     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4188   },
4189
4190   /* PREFIX_0FF7 */
4191   {
4192     { "maskmovq", { MX, MS }, PREFIX_OPCODE },
4193     { Bad_Opcode },
4194     { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
4195   },
4196
4197   /* PREFIX_0F3810 */
4198   {
4199     { Bad_Opcode },
4200     { Bad_Opcode },
4201     { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4202   },
4203
4204   /* PREFIX_0F3814 */
4205   {
4206     { Bad_Opcode },
4207     { Bad_Opcode },
4208     { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4209   },
4210
4211   /* PREFIX_0F3815 */
4212   {
4213     { Bad_Opcode },
4214     { Bad_Opcode },
4215     { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4216   },
4217
4218   /* PREFIX_0F3817 */
4219   {
4220     { Bad_Opcode },
4221     { Bad_Opcode },
4222     { "ptest",  { XM, EXx }, PREFIX_OPCODE },
4223   },
4224
4225   /* PREFIX_0F3820 */
4226   {
4227     { Bad_Opcode },
4228     { Bad_Opcode },
4229     { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE },
4230   },
4231
4232   /* PREFIX_0F3821 */
4233   {
4234     { Bad_Opcode },
4235     { Bad_Opcode },
4236     { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE },
4237   },
4238
4239   /* PREFIX_0F3822 */
4240   {
4241     { Bad_Opcode },
4242     { Bad_Opcode },
4243     { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE },
4244   },
4245
4246   /* PREFIX_0F3823 */
4247   {
4248     { Bad_Opcode },
4249     { Bad_Opcode },
4250     { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE },
4251   },
4252
4253   /* PREFIX_0F3824 */
4254   {
4255     { Bad_Opcode },
4256     { Bad_Opcode },
4257     { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE },
4258   },
4259
4260   /* PREFIX_0F3825 */
4261   {
4262     { Bad_Opcode },
4263     { Bad_Opcode },
4264     { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE },
4265   },
4266
4267   /* PREFIX_0F3828 */
4268   {
4269     { Bad_Opcode },
4270     { Bad_Opcode },
4271     { "pmuldq", { XM, EXx }, PREFIX_OPCODE },
4272   },
4273
4274   /* PREFIX_0F3829 */
4275   {
4276     { Bad_Opcode },
4277     { Bad_Opcode },
4278     { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE },
4279   },
4280
4281   /* PREFIX_0F382A */
4282   {
4283     { Bad_Opcode },
4284     { Bad_Opcode },
4285     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4286   },
4287
4288   /* PREFIX_0F382B */
4289   {
4290     { Bad_Opcode },
4291     { Bad_Opcode },
4292     { "packusdw", { XM, EXx }, PREFIX_OPCODE },
4293   },
4294
4295   /* PREFIX_0F3830 */
4296   {
4297     { Bad_Opcode },
4298     { Bad_Opcode },
4299     { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE },
4300   },
4301
4302   /* PREFIX_0F3831 */
4303   {
4304     { Bad_Opcode },
4305     { Bad_Opcode },
4306     { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE },
4307   },
4308
4309   /* PREFIX_0F3832 */
4310   {
4311     { Bad_Opcode },
4312     { Bad_Opcode },
4313     { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE },
4314   },
4315
4316   /* PREFIX_0F3833 */
4317   {
4318     { Bad_Opcode },
4319     { Bad_Opcode },
4320     { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE },
4321   },
4322
4323   /* PREFIX_0F3834 */
4324   {
4325     { Bad_Opcode },
4326     { Bad_Opcode },
4327     { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE },
4328   },
4329
4330   /* PREFIX_0F3835 */
4331   {
4332     { Bad_Opcode },
4333     { Bad_Opcode },
4334     { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE },
4335   },
4336
4337   /* PREFIX_0F3837 */
4338   {
4339     { Bad_Opcode },
4340     { Bad_Opcode },
4341     { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE },
4342   },
4343
4344   /* PREFIX_0F3838 */
4345   {
4346     { Bad_Opcode },
4347     { Bad_Opcode },
4348     { "pminsb", { XM, EXx }, PREFIX_OPCODE },
4349   },
4350
4351   /* PREFIX_0F3839 */
4352   {
4353     { Bad_Opcode },
4354     { Bad_Opcode },
4355     { "pminsd", { XM, EXx }, PREFIX_OPCODE },
4356   },
4357
4358   /* PREFIX_0F383A */
4359   {
4360     { Bad_Opcode },
4361     { Bad_Opcode },
4362     { "pminuw", { XM, EXx }, PREFIX_OPCODE },
4363   },
4364
4365   /* PREFIX_0F383B */
4366   {
4367     { Bad_Opcode },
4368     { Bad_Opcode },
4369     { "pminud", { XM, EXx }, PREFIX_OPCODE },
4370   },
4371
4372   /* PREFIX_0F383C */
4373   {
4374     { Bad_Opcode },
4375     { Bad_Opcode },
4376     { "pmaxsb", { XM, EXx }, PREFIX_OPCODE },
4377   },
4378
4379   /* PREFIX_0F383D */
4380   {
4381     { Bad_Opcode },
4382     { Bad_Opcode },
4383     { "pmaxsd", { XM, EXx }, PREFIX_OPCODE },
4384   },
4385
4386   /* PREFIX_0F383E */
4387   {
4388     { Bad_Opcode },
4389     { Bad_Opcode },
4390     { "pmaxuw", { XM, EXx }, PREFIX_OPCODE },
4391   },
4392
4393   /* PREFIX_0F383F */
4394   {
4395     { Bad_Opcode },
4396     { Bad_Opcode },
4397     { "pmaxud", { XM, EXx }, PREFIX_OPCODE },
4398   },
4399
4400   /* PREFIX_0F3840 */
4401   {
4402     { Bad_Opcode },
4403     { Bad_Opcode },
4404     { "pmulld", { XM, EXx }, PREFIX_OPCODE },
4405   },
4406
4407   /* PREFIX_0F3841 */
4408   {
4409     { Bad_Opcode },
4410     { Bad_Opcode },
4411     { "phminposuw", { XM, EXx }, PREFIX_OPCODE },
4412   },
4413
4414   /* PREFIX_0F3880 */
4415   {
4416     { Bad_Opcode },
4417     { Bad_Opcode },
4418     { "invept", { Gm, Mo }, PREFIX_OPCODE },
4419   },
4420
4421   /* PREFIX_0F3881 */
4422   {
4423     { Bad_Opcode },
4424     { Bad_Opcode },
4425     { "invvpid", { Gm, Mo }, PREFIX_OPCODE },
4426   },
4427
4428   /* PREFIX_0F3882 */
4429   {
4430     { Bad_Opcode },
4431     { Bad_Opcode },
4432     { "invpcid", { Gm, M }, PREFIX_OPCODE },
4433   },
4434
4435   /* PREFIX_0F38C8 */
4436   {
4437     { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4438   },
4439
4440   /* PREFIX_0F38C9 */
4441   {
4442     { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4443   },
4444
4445   /* PREFIX_0F38CA */
4446   {
4447     { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4448   },
4449
4450   /* PREFIX_0F38CB */
4451   {
4452     { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4453   },
4454
4455   /* PREFIX_0F38CC */
4456   {
4457     { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4458   },
4459
4460   /* PREFIX_0F38CD */
4461   {
4462     { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4463   },
4464
4465   /* PREFIX_0F38DB */
4466   {
4467     { Bad_Opcode },
4468     { Bad_Opcode },
4469     { "aesimc", { XM, EXx }, PREFIX_OPCODE },
4470   },
4471
4472   /* PREFIX_0F38DC */
4473   {
4474     { Bad_Opcode },
4475     { Bad_Opcode },
4476     { "aesenc", { XM, EXx }, PREFIX_OPCODE },
4477   },
4478
4479   /* PREFIX_0F38DD */
4480   {
4481     { Bad_Opcode },
4482     { Bad_Opcode },
4483     { "aesenclast", { XM, EXx }, PREFIX_OPCODE },
4484   },
4485
4486   /* PREFIX_0F38DE */
4487   {
4488     { Bad_Opcode },
4489     { Bad_Opcode },
4490     { "aesdec", { XM, EXx }, PREFIX_OPCODE },
4491   },
4492
4493   /* PREFIX_0F38DF */
4494   {
4495     { Bad_Opcode },
4496     { Bad_Opcode },
4497     { "aesdeclast", { XM, EXx }, PREFIX_OPCODE },
4498   },
4499
4500   /* PREFIX_0F38F0 */
4501   {
4502     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4503     { Bad_Opcode },
4504     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4505     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE },
4506   },
4507
4508   /* PREFIX_0F38F1 */
4509   {
4510     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4511     { Bad_Opcode },
4512     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4513     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE },
4514   },
4515
4516   /* PREFIX_0F38F6 */
4517   {
4518     { Bad_Opcode },
4519     { "adoxS",  { Gdq, Edq}, PREFIX_OPCODE },
4520     { "adcxS",  { Gdq, Edq}, PREFIX_OPCODE },
4521     { Bad_Opcode },
4522   },
4523
4524   /* PREFIX_0F3A08 */
4525   {
4526     { Bad_Opcode },
4527     { Bad_Opcode },
4528     { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE },
4529   },
4530
4531   /* PREFIX_0F3A09 */
4532   {
4533     { Bad_Opcode },
4534     { Bad_Opcode },
4535     { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4536   },
4537
4538   /* PREFIX_0F3A0A */
4539   {
4540     { Bad_Opcode },
4541     { Bad_Opcode },
4542     { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE },
4543   },
4544
4545   /* PREFIX_0F3A0B */
4546   {
4547     { Bad_Opcode },
4548     { Bad_Opcode },
4549     { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE },
4550   },
4551
4552   /* PREFIX_0F3A0C */
4553   {
4554     { Bad_Opcode },
4555     { Bad_Opcode },
4556     { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE },
4557   },
4558
4559   /* PREFIX_0F3A0D */
4560   {
4561     { Bad_Opcode },
4562     { Bad_Opcode },
4563     { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4564   },
4565
4566   /* PREFIX_0F3A0E */
4567   {
4568     { Bad_Opcode },
4569     { Bad_Opcode },
4570     { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE },
4571   },
4572
4573   /* PREFIX_0F3A14 */
4574   {
4575     { Bad_Opcode },
4576     { Bad_Opcode },
4577     { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE },
4578   },
4579
4580   /* PREFIX_0F3A15 */
4581   {
4582     { Bad_Opcode },
4583     { Bad_Opcode },
4584     { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE },
4585   },
4586
4587   /* PREFIX_0F3A16 */
4588   {
4589     { Bad_Opcode },
4590     { Bad_Opcode },
4591     { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE },
4592   },
4593
4594   /* PREFIX_0F3A17 */
4595   {
4596     { Bad_Opcode },
4597     { Bad_Opcode },
4598     { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE },
4599   },
4600
4601   /* PREFIX_0F3A20 */
4602   {
4603     { Bad_Opcode },
4604     { Bad_Opcode },
4605     { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE },
4606   },
4607
4608   /* PREFIX_0F3A21 */
4609   {
4610     { Bad_Opcode },
4611     { Bad_Opcode },
4612     { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE },
4613   },
4614
4615   /* PREFIX_0F3A22 */
4616   {
4617     { Bad_Opcode },
4618     { Bad_Opcode },
4619     { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE },
4620   },
4621
4622   /* PREFIX_0F3A40 */
4623   {
4624     { Bad_Opcode },
4625     { Bad_Opcode },
4626     { "dpps",   { XM, EXx, Ib }, PREFIX_OPCODE },
4627   },
4628
4629   /* PREFIX_0F3A41 */
4630   {
4631     { Bad_Opcode },
4632     { Bad_Opcode },
4633     { "dppd",   { XM, EXx, Ib }, PREFIX_OPCODE },
4634   },
4635
4636   /* PREFIX_0F3A42 */
4637   {
4638     { Bad_Opcode },
4639     { Bad_Opcode },
4640     { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE },
4641   },
4642
4643   /* PREFIX_0F3A44 */
4644   {
4645     { Bad_Opcode },
4646     { Bad_Opcode },
4647     { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE },
4648   },
4649
4650   /* PREFIX_0F3A60 */
4651   {
4652     { Bad_Opcode },
4653     { Bad_Opcode },
4654     { "pcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4655   },
4656
4657   /* PREFIX_0F3A61 */
4658   {
4659     { Bad_Opcode },
4660     { Bad_Opcode },
4661     { "pcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4662   },
4663
4664   /* PREFIX_0F3A62 */
4665   {
4666     { Bad_Opcode },
4667     { Bad_Opcode },
4668     { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4669   },
4670
4671   /* PREFIX_0F3A63 */
4672   {
4673     { Bad_Opcode },
4674     { Bad_Opcode },
4675     { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE },
4676   },
4677
4678   /* PREFIX_0F3ACC */
4679   {
4680     { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4681   },
4682
4683   /* PREFIX_0F3ADF */
4684   {
4685     { Bad_Opcode },
4686     { Bad_Opcode },
4687     { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE },
4688   },
4689
4690   /* PREFIX_VEX_0F10 */
4691   {
4692     { VEX_W_TABLE (VEX_W_0F10_P_0) },
4693     { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) },
4694     { VEX_W_TABLE (VEX_W_0F10_P_2) },
4695     { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) },
4696   },
4697
4698   /* PREFIX_VEX_0F11 */
4699   {
4700     { VEX_W_TABLE (VEX_W_0F11_P_0) },
4701     { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) },
4702     { VEX_W_TABLE (VEX_W_0F11_P_2) },
4703     { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) },
4704   },
4705
4706   /* PREFIX_VEX_0F12 */
4707   {
4708     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4709     { VEX_W_TABLE (VEX_W_0F12_P_1) },
4710     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
4711     { VEX_W_TABLE (VEX_W_0F12_P_3) },
4712   },
4713
4714   /* PREFIX_VEX_0F16 */
4715   {
4716     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4717     { VEX_W_TABLE (VEX_W_0F16_P_1) },
4718     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
4719   },
4720
4721   /* PREFIX_VEX_0F2A */
4722   {
4723     { Bad_Opcode },
4724     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) },
4725     { Bad_Opcode },
4726     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) },
4727   },
4728
4729   /* PREFIX_VEX_0F2C */
4730   {
4731     { Bad_Opcode },
4732     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) },
4733     { Bad_Opcode },
4734     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) },
4735   },
4736
4737   /* PREFIX_VEX_0F2D */
4738   {
4739     { Bad_Opcode },
4740     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) },
4741     { Bad_Opcode },
4742     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) },
4743   },
4744
4745   /* PREFIX_VEX_0F2E */
4746   {
4747     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) },
4748     { Bad_Opcode },
4749     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) },
4750   },
4751
4752   /* PREFIX_VEX_0F2F */
4753   {
4754     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) },
4755     { Bad_Opcode },
4756     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) },
4757   },
4758
4759   /* PREFIX_VEX_0F41 */
4760   {
4761     { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4762     { Bad_Opcode },
4763     { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4764   },
4765
4766   /* PREFIX_VEX_0F42 */
4767   {
4768     { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4769     { Bad_Opcode },
4770     { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4771   },
4772
4773   /* PREFIX_VEX_0F44 */
4774   {
4775     { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4776     { Bad_Opcode },
4777     { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4778   },
4779
4780   /* PREFIX_VEX_0F45 */
4781   {
4782     { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4783     { Bad_Opcode },
4784     { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4785   },
4786
4787   /* PREFIX_VEX_0F46 */
4788   {
4789     { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4790     { Bad_Opcode },
4791     { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4792   },
4793
4794   /* PREFIX_VEX_0F47 */
4795   {
4796     { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4797     { Bad_Opcode },
4798     { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
4799   },
4800
4801   /* PREFIX_VEX_0F4A */
4802   {
4803     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
4804     { Bad_Opcode },
4805     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
4806   },
4807
4808   /* PREFIX_VEX_0F4B */
4809   {
4810     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
4811     { Bad_Opcode },
4812     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4813   },
4814
4815   /* PREFIX_VEX_0F51 */
4816   {
4817     { VEX_W_TABLE (VEX_W_0F51_P_0) },
4818     { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) },
4819     { VEX_W_TABLE (VEX_W_0F51_P_2) },
4820     { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) },
4821   },
4822
4823   /* PREFIX_VEX_0F52 */
4824   {
4825     { VEX_W_TABLE (VEX_W_0F52_P_0) },
4826     { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) },
4827   },
4828
4829   /* PREFIX_VEX_0F53 */
4830   {
4831     { VEX_W_TABLE (VEX_W_0F53_P_0) },
4832     { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) },
4833   },
4834
4835   /* PREFIX_VEX_0F58 */
4836   {
4837     { VEX_W_TABLE (VEX_W_0F58_P_0) },
4838     { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) },
4839     { VEX_W_TABLE (VEX_W_0F58_P_2) },
4840     { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) },
4841   },
4842
4843   /* PREFIX_VEX_0F59 */
4844   {
4845     { VEX_W_TABLE (VEX_W_0F59_P_0) },
4846     { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) },
4847     { VEX_W_TABLE (VEX_W_0F59_P_2) },
4848     { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) },
4849   },
4850
4851   /* PREFIX_VEX_0F5A */
4852   {
4853     { VEX_W_TABLE (VEX_W_0F5A_P_0) },
4854     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) },
4855     { "vcvtpd2ps%XY", { XMM, EXx }, 0 },
4856     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) },
4857   },
4858
4859   /* PREFIX_VEX_0F5B */
4860   {
4861     { VEX_W_TABLE (VEX_W_0F5B_P_0) },
4862     { VEX_W_TABLE (VEX_W_0F5B_P_1) },
4863     { VEX_W_TABLE (VEX_W_0F5B_P_2) },
4864   },
4865
4866   /* PREFIX_VEX_0F5C */
4867   {
4868     { VEX_W_TABLE (VEX_W_0F5C_P_0) },
4869     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) },
4870     { VEX_W_TABLE (VEX_W_0F5C_P_2) },
4871     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) },
4872   },
4873
4874   /* PREFIX_VEX_0F5D */
4875   {
4876     { VEX_W_TABLE (VEX_W_0F5D_P_0) },
4877     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) },
4878     { VEX_W_TABLE (VEX_W_0F5D_P_2) },
4879     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) },
4880   },
4881
4882   /* PREFIX_VEX_0F5E */
4883   {
4884     { VEX_W_TABLE (VEX_W_0F5E_P_0) },
4885     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) },
4886     { VEX_W_TABLE (VEX_W_0F5E_P_2) },
4887     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) },
4888   },
4889
4890   /* PREFIX_VEX_0F5F */
4891   {
4892     { VEX_W_TABLE (VEX_W_0F5F_P_0) },
4893     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) },
4894     { VEX_W_TABLE (VEX_W_0F5F_P_2) },
4895     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) },
4896   },
4897
4898   /* PREFIX_VEX_0F60 */
4899   {
4900     { Bad_Opcode },
4901     { Bad_Opcode },
4902     { VEX_W_TABLE (VEX_W_0F60_P_2) },
4903   },
4904
4905   /* PREFIX_VEX_0F61 */
4906   {
4907     { Bad_Opcode },
4908     { Bad_Opcode },
4909     { VEX_W_TABLE (VEX_W_0F61_P_2) },
4910   },
4911
4912   /* PREFIX_VEX_0F62 */
4913   {
4914     { Bad_Opcode },
4915     { Bad_Opcode },
4916     { VEX_W_TABLE (VEX_W_0F62_P_2) },
4917   },
4918
4919   /* PREFIX_VEX_0F63 */
4920   {
4921     { Bad_Opcode },
4922     { Bad_Opcode },
4923     { VEX_W_TABLE (VEX_W_0F63_P_2) },
4924   },
4925
4926   /* PREFIX_VEX_0F64 */
4927   {
4928     { Bad_Opcode },
4929     { Bad_Opcode },
4930     { VEX_W_TABLE (VEX_W_0F64_P_2) },
4931   },
4932
4933   /* PREFIX_VEX_0F65 */
4934   {
4935     { Bad_Opcode },
4936     { Bad_Opcode },
4937     { VEX_W_TABLE (VEX_W_0F65_P_2) },
4938   },
4939
4940   /* PREFIX_VEX_0F66 */
4941   {
4942     { Bad_Opcode },
4943     { Bad_Opcode },
4944     { VEX_W_TABLE (VEX_W_0F66_P_2) },
4945   },
4946
4947   /* PREFIX_VEX_0F67 */
4948   {
4949     { Bad_Opcode },
4950     { Bad_Opcode },
4951     { VEX_W_TABLE (VEX_W_0F67_P_2) },
4952   },
4953
4954   /* PREFIX_VEX_0F68 */
4955   {
4956     { Bad_Opcode },
4957     { Bad_Opcode },
4958     { VEX_W_TABLE (VEX_W_0F68_P_2) },
4959   },
4960
4961   /* PREFIX_VEX_0F69 */
4962   {
4963     { Bad_Opcode },
4964     { Bad_Opcode },
4965     { VEX_W_TABLE (VEX_W_0F69_P_2) },
4966   },
4967
4968   /* PREFIX_VEX_0F6A */
4969   {
4970     { Bad_Opcode },
4971     { Bad_Opcode },
4972     { VEX_W_TABLE (VEX_W_0F6A_P_2) },
4973   },
4974
4975   /* PREFIX_VEX_0F6B */
4976   {
4977     { Bad_Opcode },
4978     { Bad_Opcode },
4979     { VEX_W_TABLE (VEX_W_0F6B_P_2) },
4980   },
4981
4982   /* PREFIX_VEX_0F6C */
4983   {
4984     { Bad_Opcode },
4985     { Bad_Opcode },
4986     { VEX_W_TABLE (VEX_W_0F6C_P_2) },
4987   },
4988
4989   /* PREFIX_VEX_0F6D */
4990   {
4991     { Bad_Opcode },
4992     { Bad_Opcode },
4993     { VEX_W_TABLE (VEX_W_0F6D_P_2) },
4994   },
4995
4996   /* PREFIX_VEX_0F6E */
4997   {
4998     { Bad_Opcode },
4999     { Bad_Opcode },
5000     { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
5001   },
5002
5003   /* PREFIX_VEX_0F6F */
5004   {
5005     { Bad_Opcode },
5006     { VEX_W_TABLE (VEX_W_0F6F_P_1) },
5007     { VEX_W_TABLE (VEX_W_0F6F_P_2) },
5008   },
5009
5010   /* PREFIX_VEX_0F70 */
5011   {
5012     { Bad_Opcode },
5013     { VEX_W_TABLE (VEX_W_0F70_P_1) },
5014     { VEX_W_TABLE (VEX_W_0F70_P_2) },
5015     { VEX_W_TABLE (VEX_W_0F70_P_3) },
5016   },
5017
5018   /* PREFIX_VEX_0F71_REG_2 */
5019   {
5020     { Bad_Opcode },
5021     { Bad_Opcode },
5022     { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) },
5023   },
5024
5025   /* PREFIX_VEX_0F71_REG_4 */
5026   {
5027     { Bad_Opcode },
5028     { Bad_Opcode },
5029     { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) },
5030   },
5031
5032   /* PREFIX_VEX_0F71_REG_6 */
5033   {
5034     { Bad_Opcode },
5035     { Bad_Opcode },
5036     { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) },
5037   },
5038
5039   /* PREFIX_VEX_0F72_REG_2 */
5040   {
5041     { Bad_Opcode },
5042     { Bad_Opcode },
5043     { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) },
5044   },
5045
5046   /* PREFIX_VEX_0F72_REG_4 */
5047   {
5048     { Bad_Opcode },
5049     { Bad_Opcode },
5050     { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) },
5051   },
5052
5053   /* PREFIX_VEX_0F72_REG_6 */
5054   {
5055     { Bad_Opcode },
5056     { Bad_Opcode },
5057     { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) },
5058   },
5059
5060   /* PREFIX_VEX_0F73_REG_2 */
5061   {
5062     { Bad_Opcode },
5063     { Bad_Opcode },
5064     { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) },
5065   },
5066
5067   /* PREFIX_VEX_0F73_REG_3 */
5068   {
5069     { Bad_Opcode },
5070     { Bad_Opcode },
5071     { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) },
5072   },
5073
5074   /* PREFIX_VEX_0F73_REG_6 */
5075   {
5076     { Bad_Opcode },
5077     { Bad_Opcode },
5078     { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) },
5079   },
5080
5081   /* PREFIX_VEX_0F73_REG_7 */
5082   {
5083     { Bad_Opcode },
5084     { Bad_Opcode },
5085     { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) },
5086   },
5087
5088   /* PREFIX_VEX_0F74 */
5089   {
5090     { Bad_Opcode },
5091     { Bad_Opcode },
5092     { VEX_W_TABLE (VEX_W_0F74_P_2) },
5093   },
5094
5095   /* PREFIX_VEX_0F75 */
5096   {
5097     { Bad_Opcode },
5098     { Bad_Opcode },
5099     { VEX_W_TABLE (VEX_W_0F75_P_2) },
5100   },
5101
5102   /* PREFIX_VEX_0F76 */
5103   {
5104     { Bad_Opcode },
5105     { Bad_Opcode },
5106     { VEX_W_TABLE (VEX_W_0F76_P_2) },
5107   },
5108
5109   /* PREFIX_VEX_0F77 */
5110   {
5111     { VEX_W_TABLE (VEX_W_0F77_P_0) },
5112   },
5113
5114   /* PREFIX_VEX_0F7C */
5115   {
5116     { Bad_Opcode },
5117     { Bad_Opcode },
5118     { VEX_W_TABLE (VEX_W_0F7C_P_2) },
5119     { VEX_W_TABLE (VEX_W_0F7C_P_3) },
5120   },
5121
5122   /* PREFIX_VEX_0F7D */
5123   {
5124     { Bad_Opcode },
5125     { Bad_Opcode },
5126     { VEX_W_TABLE (VEX_W_0F7D_P_2) },
5127     { VEX_W_TABLE (VEX_W_0F7D_P_3) },
5128   },
5129
5130   /* PREFIX_VEX_0F7E */
5131   {
5132     { Bad_Opcode },
5133     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
5134     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
5135   },
5136
5137   /* PREFIX_VEX_0F7F */
5138   {
5139     { Bad_Opcode },
5140     { VEX_W_TABLE (VEX_W_0F7F_P_1) },
5141     { VEX_W_TABLE (VEX_W_0F7F_P_2) },
5142   },
5143
5144   /* PREFIX_VEX_0F90 */
5145   {
5146     { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
5147     { Bad_Opcode },
5148     { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
5149   },
5150
5151   /* PREFIX_VEX_0F91 */
5152   {
5153     { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
5154     { Bad_Opcode },
5155     { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
5156   },
5157
5158   /* PREFIX_VEX_0F92 */
5159   {
5160     { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
5161     { Bad_Opcode },
5162     { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
5163     { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
5164   },
5165
5166   /* PREFIX_VEX_0F93 */
5167   {
5168     { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
5169     { Bad_Opcode },
5170     { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
5171     { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
5172   },
5173
5174   /* PREFIX_VEX_0F98 */
5175   {
5176     { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
5177     { Bad_Opcode },
5178     { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
5179   },
5180
5181   /* PREFIX_VEX_0F99 */
5182   {
5183     { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5184     { Bad_Opcode },
5185     { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5186   },
5187
5188   /* PREFIX_VEX_0FC2 */
5189   {
5190     { VEX_W_TABLE (VEX_W_0FC2_P_0) },
5191     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) },
5192     { VEX_W_TABLE (VEX_W_0FC2_P_2) },
5193     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) },
5194   },
5195
5196   /* PREFIX_VEX_0FC4 */
5197   {
5198     { Bad_Opcode },
5199     { Bad_Opcode },
5200     { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5201   },
5202
5203   /* PREFIX_VEX_0FC5 */
5204   {
5205     { Bad_Opcode },
5206     { Bad_Opcode },
5207     { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5208   },
5209
5210   /* PREFIX_VEX_0FD0 */
5211   {
5212     { Bad_Opcode },
5213     { Bad_Opcode },
5214     { VEX_W_TABLE (VEX_W_0FD0_P_2) },
5215     { VEX_W_TABLE (VEX_W_0FD0_P_3) },
5216   },
5217
5218   /* PREFIX_VEX_0FD1 */
5219   {
5220     { Bad_Opcode },
5221     { Bad_Opcode },
5222     { VEX_W_TABLE (VEX_W_0FD1_P_2) },
5223   },
5224
5225   /* PREFIX_VEX_0FD2 */
5226   {
5227     { Bad_Opcode },
5228     { Bad_Opcode },
5229     { VEX_W_TABLE (VEX_W_0FD2_P_2) },
5230   },
5231
5232   /* PREFIX_VEX_0FD3 */
5233   {
5234     { Bad_Opcode },
5235     { Bad_Opcode },
5236     { VEX_W_TABLE (VEX_W_0FD3_P_2) },
5237   },
5238
5239   /* PREFIX_VEX_0FD4 */
5240   {
5241     { Bad_Opcode },
5242     { Bad_Opcode },
5243     { VEX_W_TABLE (VEX_W_0FD4_P_2) },
5244   },
5245
5246   /* PREFIX_VEX_0FD5 */
5247   {
5248     { Bad_Opcode },
5249     { Bad_Opcode },
5250     { VEX_W_TABLE (VEX_W_0FD5_P_2) },
5251   },
5252
5253   /* PREFIX_VEX_0FD6 */
5254   {
5255     { Bad_Opcode },
5256     { Bad_Opcode },
5257     { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5258   },
5259
5260   /* PREFIX_VEX_0FD7 */
5261   {
5262     { Bad_Opcode },
5263     { Bad_Opcode },
5264     { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5265   },
5266
5267   /* PREFIX_VEX_0FD8 */
5268   {
5269     { Bad_Opcode },
5270     { Bad_Opcode },
5271     { VEX_W_TABLE (VEX_W_0FD8_P_2) },
5272   },
5273
5274   /* PREFIX_VEX_0FD9 */
5275   {
5276     { Bad_Opcode },
5277     { Bad_Opcode },
5278     { VEX_W_TABLE (VEX_W_0FD9_P_2) },
5279   },
5280
5281   /* PREFIX_VEX_0FDA */
5282   {
5283     { Bad_Opcode },
5284     { Bad_Opcode },
5285     { VEX_W_TABLE (VEX_W_0FDA_P_2) },
5286   },
5287
5288   /* PREFIX_VEX_0FDB */
5289   {
5290     { Bad_Opcode },
5291     { Bad_Opcode },
5292     { VEX_W_TABLE (VEX_W_0FDB_P_2) },
5293   },
5294
5295   /* PREFIX_VEX_0FDC */
5296   {
5297     { Bad_Opcode },
5298     { Bad_Opcode },
5299     { VEX_W_TABLE (VEX_W_0FDC_P_2) },
5300   },
5301
5302   /* PREFIX_VEX_0FDD */
5303   {
5304     { Bad_Opcode },
5305     { Bad_Opcode },
5306     { VEX_W_TABLE (VEX_W_0FDD_P_2) },
5307   },
5308
5309   /* PREFIX_VEX_0FDE */
5310   {
5311     { Bad_Opcode },
5312     { Bad_Opcode },
5313     { VEX_W_TABLE (VEX_W_0FDE_P_2) },
5314   },
5315
5316   /* PREFIX_VEX_0FDF */
5317   {
5318     { Bad_Opcode },
5319     { Bad_Opcode },
5320     { VEX_W_TABLE (VEX_W_0FDF_P_2) },
5321   },
5322
5323   /* PREFIX_VEX_0FE0 */
5324   {
5325     { Bad_Opcode },
5326     { Bad_Opcode },
5327     { VEX_W_TABLE (VEX_W_0FE0_P_2) },
5328   },
5329
5330   /* PREFIX_VEX_0FE1 */
5331   {
5332     { Bad_Opcode },
5333     { Bad_Opcode },
5334     { VEX_W_TABLE (VEX_W_0FE1_P_2) },
5335   },
5336
5337   /* PREFIX_VEX_0FE2 */
5338   {
5339     { Bad_Opcode },
5340     { Bad_Opcode },
5341     { VEX_W_TABLE (VEX_W_0FE2_P_2) },
5342   },
5343
5344   /* PREFIX_VEX_0FE3 */
5345   {
5346     { Bad_Opcode },
5347     { Bad_Opcode },
5348     { VEX_W_TABLE (VEX_W_0FE3_P_2) },
5349   },
5350
5351   /* PREFIX_VEX_0FE4 */
5352   {
5353     { Bad_Opcode },
5354     { Bad_Opcode },
5355     { VEX_W_TABLE (VEX_W_0FE4_P_2) },
5356   },
5357
5358   /* PREFIX_VEX_0FE5 */
5359   {
5360     { Bad_Opcode },
5361     { Bad_Opcode },
5362     { VEX_W_TABLE (VEX_W_0FE5_P_2) },
5363   },
5364
5365   /* PREFIX_VEX_0FE6 */
5366   {
5367     { Bad_Opcode },
5368     { VEX_W_TABLE (VEX_W_0FE6_P_1) },
5369     { VEX_W_TABLE (VEX_W_0FE6_P_2) },
5370     { VEX_W_TABLE (VEX_W_0FE6_P_3) },
5371   },
5372
5373   /* PREFIX_VEX_0FE7 */
5374   {
5375     { Bad_Opcode },
5376     { Bad_Opcode },
5377     { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5378   },
5379
5380   /* PREFIX_VEX_0FE8 */
5381   {
5382     { Bad_Opcode },
5383     { Bad_Opcode },
5384     { VEX_W_TABLE (VEX_W_0FE8_P_2) },
5385   },
5386
5387   /* PREFIX_VEX_0FE9 */
5388   {
5389     { Bad_Opcode },
5390     { Bad_Opcode },
5391     { VEX_W_TABLE (VEX_W_0FE9_P_2) },
5392   },
5393
5394   /* PREFIX_VEX_0FEA */
5395   {
5396     { Bad_Opcode },
5397     { Bad_Opcode },
5398     { VEX_W_TABLE (VEX_W_0FEA_P_2) },
5399   },
5400
5401   /* PREFIX_VEX_0FEB */
5402   {
5403     { Bad_Opcode },
5404     { Bad_Opcode },
5405     { VEX_W_TABLE (VEX_W_0FEB_P_2) },
5406   },
5407
5408   /* PREFIX_VEX_0FEC */
5409   {
5410     { Bad_Opcode },
5411     { Bad_Opcode },
5412     { VEX_W_TABLE (VEX_W_0FEC_P_2) },
5413   },
5414
5415   /* PREFIX_VEX_0FED */
5416   {
5417     { Bad_Opcode },
5418     { Bad_Opcode },
5419     { VEX_W_TABLE (VEX_W_0FED_P_2) },
5420   },
5421
5422   /* PREFIX_VEX_0FEE */
5423   {
5424     { Bad_Opcode },
5425     { Bad_Opcode },
5426     { VEX_W_TABLE (VEX_W_0FEE_P_2) },
5427   },
5428
5429   /* PREFIX_VEX_0FEF */
5430   {
5431     { Bad_Opcode },
5432     { Bad_Opcode },
5433     { VEX_W_TABLE (VEX_W_0FEF_P_2) },
5434   },
5435
5436   /* PREFIX_VEX_0FF0 */
5437   {
5438     { Bad_Opcode },
5439     { Bad_Opcode },
5440     { Bad_Opcode },
5441     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5442   },
5443
5444   /* PREFIX_VEX_0FF1 */
5445   {
5446     { Bad_Opcode },
5447     { Bad_Opcode },
5448     { VEX_W_TABLE (VEX_W_0FF1_P_2) },
5449   },
5450
5451   /* PREFIX_VEX_0FF2 */
5452   {
5453     { Bad_Opcode },
5454     { Bad_Opcode },
5455     { VEX_W_TABLE (VEX_W_0FF2_P_2) },
5456   },
5457
5458   /* PREFIX_VEX_0FF3 */
5459   {
5460     { Bad_Opcode },
5461     { Bad_Opcode },
5462     { VEX_W_TABLE (VEX_W_0FF3_P_2) },
5463   },
5464
5465   /* PREFIX_VEX_0FF4 */
5466   {
5467     { Bad_Opcode },
5468     { Bad_Opcode },
5469     { VEX_W_TABLE (VEX_W_0FF4_P_2) },
5470   },
5471
5472   /* PREFIX_VEX_0FF5 */
5473   {
5474     { Bad_Opcode },
5475     { Bad_Opcode },
5476     { VEX_W_TABLE (VEX_W_0FF5_P_2) },
5477   },
5478
5479   /* PREFIX_VEX_0FF6 */
5480   {
5481     { Bad_Opcode },
5482     { Bad_Opcode },
5483     { VEX_W_TABLE (VEX_W_0FF6_P_2) },
5484   },
5485
5486   /* PREFIX_VEX_0FF7 */
5487   {
5488     { Bad_Opcode },
5489     { Bad_Opcode },
5490     { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5491   },
5492
5493   /* PREFIX_VEX_0FF8 */
5494   {
5495     { Bad_Opcode },
5496     { Bad_Opcode },
5497     { VEX_W_TABLE (VEX_W_0FF8_P_2) },
5498   },
5499
5500   /* PREFIX_VEX_0FF9 */
5501   {
5502     { Bad_Opcode },
5503     { Bad_Opcode },
5504     { VEX_W_TABLE (VEX_W_0FF9_P_2) },
5505   },
5506
5507   /* PREFIX_VEX_0FFA */
5508   {
5509     { Bad_Opcode },
5510     { Bad_Opcode },
5511     { VEX_W_TABLE (VEX_W_0FFA_P_2) },
5512   },
5513
5514   /* PREFIX_VEX_0FFB */
5515   {
5516     { Bad_Opcode },
5517     { Bad_Opcode },
5518     { VEX_W_TABLE (VEX_W_0FFB_P_2) },
5519   },
5520
5521   /* PREFIX_VEX_0FFC */
5522   {
5523     { Bad_Opcode },
5524     { Bad_Opcode },
5525     { VEX_W_TABLE (VEX_W_0FFC_P_2) },
5526   },
5527
5528   /* PREFIX_VEX_0FFD */
5529   {
5530     { Bad_Opcode },
5531     { Bad_Opcode },
5532     { VEX_W_TABLE (VEX_W_0FFD_P_2) },
5533   },
5534
5535   /* PREFIX_VEX_0FFE */
5536   {
5537     { Bad_Opcode },
5538     { Bad_Opcode },
5539     { VEX_W_TABLE (VEX_W_0FFE_P_2) },
5540   },
5541
5542   /* PREFIX_VEX_0F3800 */
5543   {
5544     { Bad_Opcode },
5545     { Bad_Opcode },
5546     { VEX_W_TABLE (VEX_W_0F3800_P_2) },
5547   },
5548
5549   /* PREFIX_VEX_0F3801 */
5550   {
5551     { Bad_Opcode },
5552     { Bad_Opcode },
5553     { VEX_W_TABLE (VEX_W_0F3801_P_2) },
5554   },
5555
5556   /* PREFIX_VEX_0F3802 */
5557   {
5558     { Bad_Opcode },
5559     { Bad_Opcode },
5560     { VEX_W_TABLE (VEX_W_0F3802_P_2) },
5561   },
5562
5563   /* PREFIX_VEX_0F3803 */
5564   {
5565     { Bad_Opcode },
5566     { Bad_Opcode },
5567     { VEX_W_TABLE (VEX_W_0F3803_P_2) },
5568   },
5569
5570   /* PREFIX_VEX_0F3804 */
5571   {
5572     { Bad_Opcode },
5573     { Bad_Opcode },
5574     { VEX_W_TABLE (VEX_W_0F3804_P_2) },
5575   },
5576
5577   /* PREFIX_VEX_0F3805 */
5578   {
5579     { Bad_Opcode },
5580     { Bad_Opcode },
5581     { VEX_W_TABLE (VEX_W_0F3805_P_2) },
5582   },
5583
5584   /* PREFIX_VEX_0F3806 */
5585   {
5586     { Bad_Opcode },
5587     { Bad_Opcode },
5588     { VEX_W_TABLE (VEX_W_0F3806_P_2) },
5589   },
5590
5591   /* PREFIX_VEX_0F3807 */
5592   {
5593     { Bad_Opcode },
5594     { Bad_Opcode },
5595     { VEX_W_TABLE (VEX_W_0F3807_P_2) },
5596   },
5597
5598   /* PREFIX_VEX_0F3808 */
5599   {
5600     { Bad_Opcode },
5601     { Bad_Opcode },
5602     { VEX_W_TABLE (VEX_W_0F3808_P_2) },
5603   },
5604
5605   /* PREFIX_VEX_0F3809 */
5606   {
5607     { Bad_Opcode },
5608     { Bad_Opcode },
5609     { VEX_W_TABLE (VEX_W_0F3809_P_2) },
5610   },
5611
5612   /* PREFIX_VEX_0F380A */
5613   {
5614     { Bad_Opcode },
5615     { Bad_Opcode },
5616     { VEX_W_TABLE (VEX_W_0F380A_P_2) },
5617   },
5618
5619   /* PREFIX_VEX_0F380B */
5620   {
5621     { Bad_Opcode },
5622     { Bad_Opcode },
5623     { VEX_W_TABLE (VEX_W_0F380B_P_2) },
5624   },
5625
5626   /* PREFIX_VEX_0F380C */
5627   {
5628     { Bad_Opcode },
5629     { Bad_Opcode },
5630     { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5631   },
5632
5633   /* PREFIX_VEX_0F380D */
5634   {
5635     { Bad_Opcode },
5636     { Bad_Opcode },
5637     { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5638   },
5639
5640   /* PREFIX_VEX_0F380E */
5641   {
5642     { Bad_Opcode },
5643     { Bad_Opcode },
5644     { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5645   },
5646
5647   /* PREFIX_VEX_0F380F */
5648   {
5649     { Bad_Opcode },
5650     { Bad_Opcode },
5651     { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5652   },
5653
5654   /* PREFIX_VEX_0F3813 */
5655   {
5656     { Bad_Opcode },
5657     { Bad_Opcode },
5658     { "vcvtph2ps", { XM, EXxmmq }, 0 },
5659   },
5660
5661   /* PREFIX_VEX_0F3816 */
5662   {
5663     { Bad_Opcode },
5664     { Bad_Opcode },
5665     { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5666   },
5667
5668   /* PREFIX_VEX_0F3817 */
5669   {
5670     { Bad_Opcode },
5671     { Bad_Opcode },
5672     { VEX_W_TABLE (VEX_W_0F3817_P_2) },
5673   },
5674
5675   /* PREFIX_VEX_0F3818 */
5676   {
5677     { Bad_Opcode },
5678     { Bad_Opcode },
5679     { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5680   },
5681
5682   /* PREFIX_VEX_0F3819 */
5683   {
5684     { Bad_Opcode },
5685     { Bad_Opcode },
5686     { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5687   },
5688
5689   /* PREFIX_VEX_0F381A */
5690   {
5691     { Bad_Opcode },
5692     { Bad_Opcode },
5693     { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5694   },
5695
5696   /* PREFIX_VEX_0F381C */
5697   {
5698     { Bad_Opcode },
5699     { Bad_Opcode },
5700     { VEX_W_TABLE (VEX_W_0F381C_P_2) },
5701   },
5702
5703   /* PREFIX_VEX_0F381D */
5704   {
5705     { Bad_Opcode },
5706     { Bad_Opcode },
5707     { VEX_W_TABLE (VEX_W_0F381D_P_2) },
5708   },
5709
5710   /* PREFIX_VEX_0F381E */
5711   {
5712     { Bad_Opcode },
5713     { Bad_Opcode },
5714     { VEX_W_TABLE (VEX_W_0F381E_P_2) },
5715   },
5716
5717   /* PREFIX_VEX_0F3820 */
5718   {
5719     { Bad_Opcode },
5720     { Bad_Opcode },
5721     { VEX_W_TABLE (VEX_W_0F3820_P_2) },
5722   },
5723
5724   /* PREFIX_VEX_0F3821 */
5725   {
5726     { Bad_Opcode },
5727     { Bad_Opcode },
5728     { VEX_W_TABLE (VEX_W_0F3821_P_2) },
5729   },
5730
5731   /* PREFIX_VEX_0F3822 */
5732   {
5733     { Bad_Opcode },
5734     { Bad_Opcode },
5735     { VEX_W_TABLE (VEX_W_0F3822_P_2) },
5736   },
5737
5738   /* PREFIX_VEX_0F3823 */
5739   {
5740     { Bad_Opcode },
5741     { Bad_Opcode },
5742     { VEX_W_TABLE (VEX_W_0F3823_P_2) },
5743   },
5744
5745   /* PREFIX_VEX_0F3824 */
5746   {
5747     { Bad_Opcode },
5748     { Bad_Opcode },
5749     { VEX_W_TABLE (VEX_W_0F3824_P_2) },
5750   },
5751
5752   /* PREFIX_VEX_0F3825 */
5753   {
5754     { Bad_Opcode },
5755     { Bad_Opcode },
5756     { VEX_W_TABLE (VEX_W_0F3825_P_2) },
5757   },
5758
5759   /* PREFIX_VEX_0F3828 */
5760   {
5761     { Bad_Opcode },
5762     { Bad_Opcode },
5763     { VEX_W_TABLE (VEX_W_0F3828_P_2) },
5764   },
5765
5766   /* PREFIX_VEX_0F3829 */
5767   {
5768     { Bad_Opcode },
5769     { Bad_Opcode },
5770     { VEX_W_TABLE (VEX_W_0F3829_P_2) },
5771   },
5772
5773   /* PREFIX_VEX_0F382A */
5774   {
5775     { Bad_Opcode },
5776     { Bad_Opcode },
5777     { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5778   },
5779
5780   /* PREFIX_VEX_0F382B */
5781   {
5782     { Bad_Opcode },
5783     { Bad_Opcode },
5784     { VEX_W_TABLE (VEX_W_0F382B_P_2) },
5785   },
5786
5787   /* PREFIX_VEX_0F382C */
5788   {
5789     { Bad_Opcode },
5790     { Bad_Opcode },
5791      { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5792   },
5793
5794   /* PREFIX_VEX_0F382D */
5795   {
5796     { Bad_Opcode },
5797     { Bad_Opcode },
5798      { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5799   },
5800
5801   /* PREFIX_VEX_0F382E */
5802   {
5803     { Bad_Opcode },
5804     { Bad_Opcode },
5805      { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5806   },
5807
5808   /* PREFIX_VEX_0F382F */
5809   {
5810     { Bad_Opcode },
5811     { Bad_Opcode },
5812      { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5813   },
5814
5815   /* PREFIX_VEX_0F3830 */
5816   {
5817     { Bad_Opcode },
5818     { Bad_Opcode },
5819     { VEX_W_TABLE (VEX_W_0F3830_P_2) },
5820   },
5821
5822   /* PREFIX_VEX_0F3831 */
5823   {
5824     { Bad_Opcode },
5825     { Bad_Opcode },
5826     { VEX_W_TABLE (VEX_W_0F3831_P_2) },
5827   },
5828
5829   /* PREFIX_VEX_0F3832 */
5830   {
5831     { Bad_Opcode },
5832     { Bad_Opcode },
5833     { VEX_W_TABLE (VEX_W_0F3832_P_2) },
5834   },
5835
5836   /* PREFIX_VEX_0F3833 */
5837   {
5838     { Bad_Opcode },
5839     { Bad_Opcode },
5840     { VEX_W_TABLE (VEX_W_0F3833_P_2) },
5841   },
5842
5843   /* PREFIX_VEX_0F3834 */
5844   {
5845     { Bad_Opcode },
5846     { Bad_Opcode },
5847     { VEX_W_TABLE (VEX_W_0F3834_P_2) },
5848   },
5849
5850   /* PREFIX_VEX_0F3835 */
5851   {
5852     { Bad_Opcode },
5853     { Bad_Opcode },
5854     { VEX_W_TABLE (VEX_W_0F3835_P_2) },
5855   },
5856
5857   /* PREFIX_VEX_0F3836 */
5858   {
5859     { Bad_Opcode },
5860     { Bad_Opcode },
5861     { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5862   },
5863
5864   /* PREFIX_VEX_0F3837 */
5865   {
5866     { Bad_Opcode },
5867     { Bad_Opcode },
5868     { VEX_W_TABLE (VEX_W_0F3837_P_2) },
5869   },
5870
5871   /* PREFIX_VEX_0F3838 */
5872   {
5873     { Bad_Opcode },
5874     { Bad_Opcode },
5875     { VEX_W_TABLE (VEX_W_0F3838_P_2) },
5876   },
5877
5878   /* PREFIX_VEX_0F3839 */
5879   {
5880     { Bad_Opcode },
5881     { Bad_Opcode },
5882     { VEX_W_TABLE (VEX_W_0F3839_P_2) },
5883   },
5884
5885   /* PREFIX_VEX_0F383A */
5886   {
5887     { Bad_Opcode },
5888     { Bad_Opcode },
5889     { VEX_W_TABLE (VEX_W_0F383A_P_2) },
5890   },
5891
5892   /* PREFIX_VEX_0F383B */
5893   {
5894     { Bad_Opcode },
5895     { Bad_Opcode },
5896     { VEX_W_TABLE (VEX_W_0F383B_P_2) },
5897   },
5898
5899   /* PREFIX_VEX_0F383C */
5900   {
5901     { Bad_Opcode },
5902     { Bad_Opcode },
5903     { VEX_W_TABLE (VEX_W_0F383C_P_2) },
5904   },
5905
5906   /* PREFIX_VEX_0F383D */
5907   {
5908     { Bad_Opcode },
5909     { Bad_Opcode },
5910     { VEX_W_TABLE (VEX_W_0F383D_P_2) },
5911   },
5912
5913   /* PREFIX_VEX_0F383E */
5914   {
5915     { Bad_Opcode },
5916     { Bad_Opcode },
5917     { VEX_W_TABLE (VEX_W_0F383E_P_2) },
5918   },
5919
5920   /* PREFIX_VEX_0F383F */
5921   {
5922     { Bad_Opcode },
5923     { Bad_Opcode },
5924     { VEX_W_TABLE (VEX_W_0F383F_P_2) },
5925   },
5926
5927   /* PREFIX_VEX_0F3840 */
5928   {
5929     { Bad_Opcode },
5930     { Bad_Opcode },
5931     { VEX_W_TABLE (VEX_W_0F3840_P_2) },
5932   },
5933
5934   /* PREFIX_VEX_0F3841 */
5935   {
5936     { Bad_Opcode },
5937     { Bad_Opcode },
5938     { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
5939   },
5940
5941   /* PREFIX_VEX_0F3845 */
5942   {
5943     { Bad_Opcode },
5944     { Bad_Opcode },
5945     { "vpsrlv%LW", { XM, Vex, EXx }, 0 },
5946   },
5947
5948   /* PREFIX_VEX_0F3846 */
5949   {
5950     { Bad_Opcode },
5951     { Bad_Opcode },
5952     { VEX_W_TABLE (VEX_W_0F3846_P_2) },
5953   },
5954
5955   /* PREFIX_VEX_0F3847 */
5956   {
5957     { Bad_Opcode },
5958     { Bad_Opcode },
5959     { "vpsllv%LW", { XM, Vex, EXx }, 0 },
5960   },
5961
5962   /* PREFIX_VEX_0F3858 */
5963   {
5964     { Bad_Opcode },
5965     { Bad_Opcode },
5966     { VEX_W_TABLE (VEX_W_0F3858_P_2) },
5967   },
5968
5969   /* PREFIX_VEX_0F3859 */
5970   {
5971     { Bad_Opcode },
5972     { Bad_Opcode },
5973     { VEX_W_TABLE (VEX_W_0F3859_P_2) },
5974   },
5975
5976   /* PREFIX_VEX_0F385A */
5977   {
5978     { Bad_Opcode },
5979     { Bad_Opcode },
5980     { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
5981   },
5982
5983   /* PREFIX_VEX_0F3878 */
5984   {
5985     { Bad_Opcode },
5986     { Bad_Opcode },
5987     { VEX_W_TABLE (VEX_W_0F3878_P_2) },
5988   },
5989
5990   /* PREFIX_VEX_0F3879 */
5991   {
5992     { Bad_Opcode },
5993     { Bad_Opcode },
5994     { VEX_W_TABLE (VEX_W_0F3879_P_2) },
5995   },
5996
5997   /* PREFIX_VEX_0F388C */
5998   {
5999     { Bad_Opcode },
6000     { Bad_Opcode },
6001     { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
6002   },
6003
6004   /* PREFIX_VEX_0F388E */
6005   {
6006     { Bad_Opcode },
6007     { Bad_Opcode },
6008     { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
6009   },
6010
6011   /* PREFIX_VEX_0F3890 */
6012   {
6013     { Bad_Opcode },
6014     { Bad_Opcode },
6015     { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 },
6016   },
6017
6018   /* PREFIX_VEX_0F3891 */
6019   {
6020     { Bad_Opcode },
6021     { Bad_Opcode },
6022     { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6023   },
6024
6025   /* PREFIX_VEX_0F3892 */
6026   {
6027     { Bad_Opcode },
6028     { Bad_Opcode },
6029     { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 },
6030   },
6031
6032   /* PREFIX_VEX_0F3893 */
6033   {
6034     { Bad_Opcode },
6035     { Bad_Opcode },
6036     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6037   },
6038
6039   /* PREFIX_VEX_0F3896 */
6040   {
6041     { Bad_Opcode },
6042     { Bad_Opcode },
6043     { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 },
6044   },
6045
6046   /* PREFIX_VEX_0F3897 */
6047   {
6048     { Bad_Opcode },
6049     { Bad_Opcode },
6050     { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 },
6051   },
6052
6053   /* PREFIX_VEX_0F3898 */
6054   {
6055     { Bad_Opcode },
6056     { Bad_Opcode },
6057     { "vfmadd132p%XW", { XM, Vex, EXx }, 0 },
6058   },
6059
6060   /* PREFIX_VEX_0F3899 */
6061   {
6062     { Bad_Opcode },
6063     { Bad_Opcode },
6064     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6065   },
6066
6067   /* PREFIX_VEX_0F389A */
6068   {
6069     { Bad_Opcode },
6070     { Bad_Opcode },
6071     { "vfmsub132p%XW", { XM, Vex, EXx }, 0 },
6072   },
6073
6074   /* PREFIX_VEX_0F389B */
6075   {
6076     { Bad_Opcode },
6077     { Bad_Opcode },
6078     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6079   },
6080
6081   /* PREFIX_VEX_0F389C */
6082   {
6083     { Bad_Opcode },
6084     { Bad_Opcode },
6085     { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 },
6086   },
6087
6088   /* PREFIX_VEX_0F389D */
6089   {
6090     { Bad_Opcode },
6091     { Bad_Opcode },
6092     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6093   },
6094
6095   /* PREFIX_VEX_0F389E */
6096   {
6097     { Bad_Opcode },
6098     { Bad_Opcode },
6099     { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 },
6100   },
6101
6102   /* PREFIX_VEX_0F389F */
6103   {
6104     { Bad_Opcode },
6105     { Bad_Opcode },
6106     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6107   },
6108
6109   /* PREFIX_VEX_0F38A6 */
6110   {
6111     { Bad_Opcode },
6112     { Bad_Opcode },
6113     { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 },
6114     { Bad_Opcode },
6115   },
6116
6117   /* PREFIX_VEX_0F38A7 */
6118   {
6119     { Bad_Opcode },
6120     { Bad_Opcode },
6121     { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 },
6122   },
6123
6124   /* PREFIX_VEX_0F38A8 */
6125   {
6126     { Bad_Opcode },
6127     { Bad_Opcode },
6128     { "vfmadd213p%XW", { XM, Vex, EXx }, 0 },
6129   },
6130
6131   /* PREFIX_VEX_0F38A9 */
6132   {
6133     { Bad_Opcode },
6134     { Bad_Opcode },
6135     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6136   },
6137
6138   /* PREFIX_VEX_0F38AA */
6139   {
6140     { Bad_Opcode },
6141     { Bad_Opcode },
6142     { "vfmsub213p%XW", { XM, Vex, EXx }, 0 },
6143   },
6144
6145   /* PREFIX_VEX_0F38AB */
6146   {
6147     { Bad_Opcode },
6148     { Bad_Opcode },
6149     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6150   },
6151
6152   /* PREFIX_VEX_0F38AC */
6153   {
6154     { Bad_Opcode },
6155     { Bad_Opcode },
6156     { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 },
6157   },
6158
6159   /* PREFIX_VEX_0F38AD */
6160   {
6161     { Bad_Opcode },
6162     { Bad_Opcode },
6163     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6164   },
6165
6166   /* PREFIX_VEX_0F38AE */
6167   {
6168     { Bad_Opcode },
6169     { Bad_Opcode },
6170     { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 },
6171   },
6172
6173   /* PREFIX_VEX_0F38AF */
6174   {
6175     { Bad_Opcode },
6176     { Bad_Opcode },
6177     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6178   },
6179
6180   /* PREFIX_VEX_0F38B6 */
6181   {
6182     { Bad_Opcode },
6183     { Bad_Opcode },
6184     { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 },
6185   },
6186
6187   /* PREFIX_VEX_0F38B7 */
6188   {
6189     { Bad_Opcode },
6190     { Bad_Opcode },
6191     { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 },
6192   },
6193
6194   /* PREFIX_VEX_0F38B8 */
6195   {
6196     { Bad_Opcode },
6197     { Bad_Opcode },
6198     { "vfmadd231p%XW", { XM, Vex, EXx }, 0 },
6199   },
6200
6201   /* PREFIX_VEX_0F38B9 */
6202   {
6203     { Bad_Opcode },
6204     { Bad_Opcode },
6205     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6206   },
6207
6208   /* PREFIX_VEX_0F38BA */
6209   {
6210     { Bad_Opcode },
6211     { Bad_Opcode },
6212     { "vfmsub231p%XW", { XM, Vex, EXx }, 0 },
6213   },
6214
6215   /* PREFIX_VEX_0F38BB */
6216   {
6217     { Bad_Opcode },
6218     { Bad_Opcode },
6219     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6220   },
6221
6222   /* PREFIX_VEX_0F38BC */
6223   {
6224     { Bad_Opcode },
6225     { Bad_Opcode },
6226     { "vfnmadd231p%XW", { XM, Vex, EXx }, 0 },
6227   },
6228
6229   /* PREFIX_VEX_0F38BD */
6230   {
6231     { Bad_Opcode },
6232     { Bad_Opcode },
6233     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6234   },
6235
6236   /* PREFIX_VEX_0F38BE */
6237   {
6238     { Bad_Opcode },
6239     { Bad_Opcode },
6240     { "vfnmsub231p%XW", { XM, Vex, EXx }, 0 },
6241   },
6242
6243   /* PREFIX_VEX_0F38BF */
6244   {
6245     { Bad_Opcode },
6246     { Bad_Opcode },
6247     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6248   },
6249
6250   /* PREFIX_VEX_0F38DB */
6251   {
6252     { Bad_Opcode },
6253     { Bad_Opcode },
6254     { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6255   },
6256
6257   /* PREFIX_VEX_0F38DC */
6258   {
6259     { Bad_Opcode },
6260     { Bad_Opcode },
6261     { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2) },
6262   },
6263
6264   /* PREFIX_VEX_0F38DD */
6265   {
6266     { Bad_Opcode },
6267     { Bad_Opcode },
6268     { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2) },
6269   },
6270
6271   /* PREFIX_VEX_0F38DE */
6272   {
6273     { Bad_Opcode },
6274     { Bad_Opcode },
6275     { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2) },
6276   },
6277
6278   /* PREFIX_VEX_0F38DF */
6279   {
6280     { Bad_Opcode },
6281     { Bad_Opcode },
6282     { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2) },
6283   },
6284
6285   /* PREFIX_VEX_0F38F2 */
6286   {
6287     { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6288   },
6289
6290   /* PREFIX_VEX_0F38F3_REG_1 */
6291   {
6292     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6293   },
6294
6295   /* PREFIX_VEX_0F38F3_REG_2 */
6296   {
6297     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6298   },
6299
6300   /* PREFIX_VEX_0F38F3_REG_3 */
6301   {
6302     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6303   },
6304
6305   /* PREFIX_VEX_0F38F5 */
6306   {
6307     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6308     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6309     { Bad_Opcode },
6310     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6311   },
6312
6313   /* PREFIX_VEX_0F38F6 */
6314   {
6315     { Bad_Opcode },
6316     { Bad_Opcode },
6317     { Bad_Opcode },
6318     { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6319   },
6320
6321   /* PREFIX_VEX_0F38F7 */
6322   {
6323     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6324     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6325     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6326     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6327   },
6328
6329   /* PREFIX_VEX_0F3A00 */
6330   {
6331     { Bad_Opcode },
6332     { Bad_Opcode },
6333     { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6334   },
6335
6336   /* PREFIX_VEX_0F3A01 */
6337   {
6338     { Bad_Opcode },
6339     { Bad_Opcode },
6340     { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6341   },
6342
6343   /* PREFIX_VEX_0F3A02 */
6344   {
6345     { Bad_Opcode },
6346     { Bad_Opcode },
6347     { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6348   },
6349
6350   /* PREFIX_VEX_0F3A04 */
6351   {
6352     { Bad_Opcode },
6353     { Bad_Opcode },
6354     { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6355   },
6356
6357   /* PREFIX_VEX_0F3A05 */
6358   {
6359     { Bad_Opcode },
6360     { Bad_Opcode },
6361     { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6362   },
6363
6364   /* PREFIX_VEX_0F3A06 */
6365   {
6366     { Bad_Opcode },
6367     { Bad_Opcode },
6368     { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6369   },
6370
6371   /* PREFIX_VEX_0F3A08 */
6372   {
6373     { Bad_Opcode },
6374     { Bad_Opcode },
6375     { VEX_W_TABLE (VEX_W_0F3A08_P_2) },
6376   },
6377
6378   /* PREFIX_VEX_0F3A09 */
6379   {
6380     { Bad_Opcode },
6381     { Bad_Opcode },
6382     { VEX_W_TABLE (VEX_W_0F3A09_P_2) },
6383   },
6384
6385   /* PREFIX_VEX_0F3A0A */
6386   {
6387     { Bad_Opcode },
6388     { Bad_Opcode },
6389     { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) },
6390   },
6391
6392   /* PREFIX_VEX_0F3A0B */
6393   {
6394     { Bad_Opcode },
6395     { Bad_Opcode },
6396     { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) },
6397   },
6398
6399   /* PREFIX_VEX_0F3A0C */
6400   {
6401     { Bad_Opcode },
6402     { Bad_Opcode },
6403     { VEX_W_TABLE (VEX_W_0F3A0C_P_2) },
6404   },
6405
6406   /* PREFIX_VEX_0F3A0D */
6407   {
6408     { Bad_Opcode },
6409     { Bad_Opcode },
6410     { VEX_W_TABLE (VEX_W_0F3A0D_P_2) },
6411   },
6412
6413   /* PREFIX_VEX_0F3A0E */
6414   {
6415     { Bad_Opcode },
6416     { Bad_Opcode },
6417     { VEX_W_TABLE (VEX_W_0F3A0E_P_2) },
6418   },
6419
6420   /* PREFIX_VEX_0F3A0F */
6421   {
6422     { Bad_Opcode },
6423     { Bad_Opcode },
6424     { VEX_W_TABLE (VEX_W_0F3A0F_P_2) },
6425   },
6426
6427   /* PREFIX_VEX_0F3A14 */
6428   {
6429     { Bad_Opcode },
6430     { Bad_Opcode },
6431     { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6432   },
6433
6434   /* PREFIX_VEX_0F3A15 */
6435   {
6436     { Bad_Opcode },
6437     { Bad_Opcode },
6438     { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6439   },
6440
6441   /* PREFIX_VEX_0F3A16 */
6442   {
6443     { Bad_Opcode },
6444     { Bad_Opcode },
6445     { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6446   },
6447
6448   /* PREFIX_VEX_0F3A17 */
6449   {
6450     { Bad_Opcode },
6451     { Bad_Opcode },
6452     { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6453   },
6454
6455   /* PREFIX_VEX_0F3A18 */
6456   {
6457     { Bad_Opcode },
6458     { Bad_Opcode },
6459     { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6460   },
6461
6462   /* PREFIX_VEX_0F3A19 */
6463   {
6464     { Bad_Opcode },
6465     { Bad_Opcode },
6466     { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6467   },
6468
6469   /* PREFIX_VEX_0F3A1D */
6470   {
6471     { Bad_Opcode },
6472     { Bad_Opcode },
6473     { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 },
6474   },
6475
6476   /* PREFIX_VEX_0F3A20 */
6477   {
6478     { Bad_Opcode },
6479     { Bad_Opcode },
6480     { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6481   },
6482
6483   /* PREFIX_VEX_0F3A21 */
6484   {
6485     { Bad_Opcode },
6486     { Bad_Opcode },
6487     { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6488   },
6489
6490   /* PREFIX_VEX_0F3A22 */
6491   {
6492     { Bad_Opcode },
6493     { Bad_Opcode },
6494     { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6495   },
6496
6497   /* PREFIX_VEX_0F3A30 */
6498   {
6499     { Bad_Opcode },
6500     { Bad_Opcode },
6501     { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6502   },
6503
6504   /* PREFIX_VEX_0F3A31 */
6505   {
6506     { Bad_Opcode },
6507     { Bad_Opcode },
6508     { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6509   },
6510
6511   /* PREFIX_VEX_0F3A32 */
6512   {
6513     { Bad_Opcode },
6514     { Bad_Opcode },
6515     { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6516   },
6517
6518   /* PREFIX_VEX_0F3A33 */
6519   {
6520     { Bad_Opcode },
6521     { Bad_Opcode },
6522     { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6523   },
6524
6525   /* PREFIX_VEX_0F3A38 */
6526   {
6527     { Bad_Opcode },
6528     { Bad_Opcode },
6529     { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6530   },
6531
6532   /* PREFIX_VEX_0F3A39 */
6533   {
6534     { Bad_Opcode },
6535     { Bad_Opcode },
6536     { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6537   },
6538
6539   /* PREFIX_VEX_0F3A40 */
6540   {
6541     { Bad_Opcode },
6542     { Bad_Opcode },
6543     { VEX_W_TABLE (VEX_W_0F3A40_P_2) },
6544   },
6545
6546   /* PREFIX_VEX_0F3A41 */
6547   {
6548     { Bad_Opcode },
6549     { Bad_Opcode },
6550     { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6551   },
6552
6553   /* PREFIX_VEX_0F3A42 */
6554   {
6555     { Bad_Opcode },
6556     { Bad_Opcode },
6557     { VEX_W_TABLE (VEX_W_0F3A42_P_2) },
6558   },
6559
6560   /* PREFIX_VEX_0F3A44 */
6561   {
6562     { Bad_Opcode },
6563     { Bad_Opcode },
6564     { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2) },
6565   },
6566
6567   /* PREFIX_VEX_0F3A46 */
6568   {
6569     { Bad_Opcode },
6570     { Bad_Opcode },
6571     { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6572   },
6573
6574   /* PREFIX_VEX_0F3A48 */
6575   {
6576     { Bad_Opcode },
6577     { Bad_Opcode },
6578     { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6579   },
6580
6581   /* PREFIX_VEX_0F3A49 */
6582   {
6583     { Bad_Opcode },
6584     { Bad_Opcode },
6585     { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6586   },
6587
6588   /* PREFIX_VEX_0F3A4A */
6589   {
6590     { Bad_Opcode },
6591     { Bad_Opcode },
6592     { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6593   },
6594
6595   /* PREFIX_VEX_0F3A4B */
6596   {
6597     { Bad_Opcode },
6598     { Bad_Opcode },
6599     { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6600   },
6601
6602   /* PREFIX_VEX_0F3A4C */
6603   {
6604     { Bad_Opcode },
6605     { Bad_Opcode },
6606     { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6607   },
6608
6609   /* PREFIX_VEX_0F3A5C */
6610   {
6611     { Bad_Opcode },
6612     { Bad_Opcode },
6613     { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6614   },
6615
6616   /* PREFIX_VEX_0F3A5D */
6617   {
6618     { Bad_Opcode },
6619     { Bad_Opcode },
6620     { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6621   },
6622
6623   /* PREFIX_VEX_0F3A5E */
6624   {
6625     { Bad_Opcode },
6626     { Bad_Opcode },
6627     { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6628   },
6629
6630   /* PREFIX_VEX_0F3A5F */
6631   {
6632     { Bad_Opcode },
6633     { Bad_Opcode },
6634     { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6635   },
6636
6637   /* PREFIX_VEX_0F3A60 */
6638   {
6639     { Bad_Opcode },
6640     { Bad_Opcode },
6641     { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6642     { Bad_Opcode },
6643   },
6644
6645   /* PREFIX_VEX_0F3A61 */
6646   {
6647     { Bad_Opcode },
6648     { Bad_Opcode },
6649     { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6650   },
6651
6652   /* PREFIX_VEX_0F3A62 */
6653   {
6654     { Bad_Opcode },
6655     { Bad_Opcode },
6656     { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6657   },
6658
6659   /* PREFIX_VEX_0F3A63 */
6660   {
6661     { Bad_Opcode },
6662     { Bad_Opcode },
6663     { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6664   },
6665
6666   /* PREFIX_VEX_0F3A68 */
6667   {
6668     { Bad_Opcode },
6669     { Bad_Opcode },
6670     { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6671   },
6672
6673   /* PREFIX_VEX_0F3A69 */
6674   {
6675     { Bad_Opcode },
6676     { Bad_Opcode },
6677     { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6678   },
6679
6680   /* PREFIX_VEX_0F3A6A */
6681   {
6682     { Bad_Opcode },
6683     { Bad_Opcode },
6684     { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6685   },
6686
6687   /* PREFIX_VEX_0F3A6B */
6688   {
6689     { Bad_Opcode },
6690     { Bad_Opcode },
6691     { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6692   },
6693
6694   /* PREFIX_VEX_0F3A6C */
6695   {
6696     { Bad_Opcode },
6697     { Bad_Opcode },
6698     { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6699   },
6700
6701   /* PREFIX_VEX_0F3A6D */
6702   {
6703     { Bad_Opcode },
6704     { Bad_Opcode },
6705     { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6706   },
6707
6708   /* PREFIX_VEX_0F3A6E */
6709   {
6710     { Bad_Opcode },
6711     { Bad_Opcode },
6712     { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6713   },
6714
6715   /* PREFIX_VEX_0F3A6F */
6716   {
6717     { Bad_Opcode },
6718     { Bad_Opcode },
6719     { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6720   },
6721
6722   /* PREFIX_VEX_0F3A78 */
6723   {
6724     { Bad_Opcode },
6725     { Bad_Opcode },
6726     { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6727   },
6728
6729   /* PREFIX_VEX_0F3A79 */
6730   {
6731     { Bad_Opcode },
6732     { Bad_Opcode },
6733     { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6734   },
6735
6736   /* PREFIX_VEX_0F3A7A */
6737   {
6738     { Bad_Opcode },
6739     { Bad_Opcode },
6740     { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6741   },
6742
6743   /* PREFIX_VEX_0F3A7B */
6744   {
6745     { Bad_Opcode },
6746     { Bad_Opcode },
6747     { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6748   },
6749
6750   /* PREFIX_VEX_0F3A7C */
6751   {
6752     { Bad_Opcode },
6753     { Bad_Opcode },
6754     { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6755     { Bad_Opcode },
6756   },
6757
6758   /* PREFIX_VEX_0F3A7D */
6759   {
6760     { Bad_Opcode },
6761     { Bad_Opcode },
6762     { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6763   },
6764
6765   /* PREFIX_VEX_0F3A7E */
6766   {
6767     { Bad_Opcode },
6768     { Bad_Opcode },
6769     { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6770   },
6771
6772   /* PREFIX_VEX_0F3A7F */
6773   {
6774     { Bad_Opcode },
6775     { Bad_Opcode },
6776     { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6777   },
6778
6779   /* PREFIX_VEX_0F3ADF */
6780   {
6781     { Bad_Opcode },
6782     { Bad_Opcode },
6783     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6784   },
6785
6786   /* PREFIX_VEX_0F3AF0 */
6787   {
6788     { Bad_Opcode },
6789     { Bad_Opcode },
6790     { Bad_Opcode },
6791     { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6792   },
6793
6794 #define NEED_PREFIX_TABLE
6795 #include "i386-dis-evex.h"
6796 #undef NEED_PREFIX_TABLE
6797 };
6798
6799 static const struct dis386 x86_64_table[][2] = {
6800   /* X86_64_06 */
6801   {
6802     { "pushP", { es }, 0 },
6803   },
6804
6805   /* X86_64_07 */
6806   {
6807     { "popP", { es }, 0 },
6808   },
6809
6810   /* X86_64_0D */
6811   {
6812     { "pushP", { cs }, 0 },
6813   },
6814
6815   /* X86_64_16 */
6816   {
6817     { "pushP", { ss }, 0 },
6818   },
6819
6820   /* X86_64_17 */
6821   {
6822     { "popP", { ss }, 0 },
6823   },
6824
6825   /* X86_64_1E */
6826   {
6827     { "pushP", { ds }, 0 },
6828   },
6829
6830   /* X86_64_1F */
6831   {
6832     { "popP", { ds }, 0 },
6833   },
6834
6835   /* X86_64_27 */
6836   {
6837     { "daa", { XX }, 0 },
6838   },
6839
6840   /* X86_64_2F */
6841   {
6842     { "das", { XX }, 0 },
6843   },
6844
6845   /* X86_64_37 */
6846   {
6847     { "aaa", { XX }, 0 },
6848   },
6849
6850   /* X86_64_3F */
6851   {
6852     { "aas", { XX }, 0 },
6853   },
6854
6855   /* X86_64_60 */
6856   {
6857     { "pushaP", { XX }, 0 },
6858   },
6859
6860   /* X86_64_61 */
6861   {
6862     { "popaP", { XX }, 0 },
6863   },
6864
6865   /* X86_64_62 */
6866   {
6867     { MOD_TABLE (MOD_62_32BIT) },
6868     { EVEX_TABLE (EVEX_0F) },
6869   },
6870
6871   /* X86_64_63 */
6872   {
6873     { "arpl", { Ew, Gw }, 0 },
6874     { "movs{lq|xd}", { Gv, Ed }, 0 },
6875   },
6876
6877   /* X86_64_6D */
6878   {
6879     { "ins{R|}", { Yzr, indirDX }, 0 },
6880     { "ins{G|}", { Yzr, indirDX }, 0 },
6881   },
6882
6883   /* X86_64_6F */
6884   {
6885     { "outs{R|}", { indirDXr, Xz }, 0 },
6886     { "outs{G|}", { indirDXr, Xz }, 0 },
6887   },
6888
6889   /* X86_64_82 */
6890   {
6891     /* Opcode 0x82 is an alias of of opcode 0x80 in 32-bit mode.  */
6892     { REG_TABLE (REG_80) },
6893   },
6894
6895   /* X86_64_9A */
6896   {
6897     { "Jcall{T|}", { Ap }, 0 },
6898   },
6899
6900   /* X86_64_C4 */
6901   {
6902     { MOD_TABLE (MOD_C4_32BIT) },
6903     { VEX_C4_TABLE (VEX_0F) },
6904   },
6905
6906   /* X86_64_C5 */
6907   {
6908     { MOD_TABLE (MOD_C5_32BIT) },
6909     { VEX_C5_TABLE (VEX_0F) },
6910   },
6911
6912   /* X86_64_CE */
6913   {
6914     { "into", { XX }, 0 },
6915   },
6916
6917   /* X86_64_D4 */
6918   {
6919     { "aam", { Ib }, 0 },
6920   },
6921
6922   /* X86_64_D5 */
6923   {
6924     { "aad", { Ib }, 0 },
6925   },
6926
6927   /* X86_64_E8 */
6928   {
6929     { "callP",          { Jv, BND }, 0 },
6930     { "call@",          { Jv, BND }, 0 }
6931   },
6932
6933   /* X86_64_E9 */
6934   {
6935     { "jmpP",           { Jv, BND }, 0 },
6936     { "jmp@",           { Jv, BND }, 0 }
6937   },
6938
6939   /* X86_64_EA */
6940   {
6941     { "Jjmp{T|}", { Ap }, 0 },
6942   },
6943
6944   /* X86_64_0F01_REG_0 */
6945   {
6946     { "sgdt{Q|IQ}", { M }, 0 },
6947     { "sgdt", { M }, 0 },
6948   },
6949
6950   /* X86_64_0F01_REG_1 */
6951   {
6952     { "sidt{Q|IQ}", { M }, 0 },
6953     { "sidt", { M }, 0 },
6954   },
6955
6956   /* X86_64_0F01_REG_2 */
6957   {
6958     { "lgdt{Q|Q}", { M }, 0 },
6959     { "lgdt", { M }, 0 },
6960   },
6961
6962   /* X86_64_0F01_REG_3 */
6963   {
6964     { "lidt{Q|Q}", { M }, 0 },
6965     { "lidt", { M }, 0 },
6966   },
6967 };
6968
6969 static const struct dis386 three_byte_table[][256] = {
6970
6971   /* THREE_BYTE_0F38 */
6972   {
6973     /* 00 */
6974     { "pshufb",         { MX, EM }, PREFIX_OPCODE },
6975     { "phaddw",         { MX, EM }, PREFIX_OPCODE },
6976     { "phaddd",         { MX, EM }, PREFIX_OPCODE },
6977     { "phaddsw",        { MX, EM }, PREFIX_OPCODE },
6978     { "pmaddubsw",      { MX, EM }, PREFIX_OPCODE },
6979     { "phsubw",         { MX, EM }, PREFIX_OPCODE },
6980     { "phsubd",         { MX, EM }, PREFIX_OPCODE },
6981     { "phsubsw",        { MX, EM }, PREFIX_OPCODE },
6982     /* 08 */
6983     { "psignb",         { MX, EM }, PREFIX_OPCODE },
6984     { "psignw",         { MX, EM }, PREFIX_OPCODE },
6985     { "psignd",         { MX, EM }, PREFIX_OPCODE },
6986     { "pmulhrsw",       { MX, EM }, PREFIX_OPCODE },
6987     { Bad_Opcode },
6988     { Bad_Opcode },
6989     { Bad_Opcode },
6990     { Bad_Opcode },
6991     /* 10 */
6992     { PREFIX_TABLE (PREFIX_0F3810) },
6993     { Bad_Opcode },
6994     { Bad_Opcode },
6995     { Bad_Opcode },
6996     { PREFIX_TABLE (PREFIX_0F3814) },
6997     { PREFIX_TABLE (PREFIX_0F3815) },
6998     { Bad_Opcode },
6999     { PREFIX_TABLE (PREFIX_0F3817) },
7000     /* 18 */
7001     { Bad_Opcode },
7002     { Bad_Opcode },
7003     { Bad_Opcode },
7004     { Bad_Opcode },
7005     { "pabsb",          { MX, EM }, PREFIX_OPCODE },
7006     { "pabsw",          { MX, EM }, PREFIX_OPCODE },
7007     { "pabsd",          { MX, EM }, PREFIX_OPCODE },
7008     { Bad_Opcode },
7009     /* 20 */
7010     { PREFIX_TABLE (PREFIX_0F3820) },
7011     { PREFIX_TABLE (PREFIX_0F3821) },
7012     { PREFIX_TABLE (PREFIX_0F3822) },
7013     { PREFIX_TABLE (PREFIX_0F3823) },
7014     { PREFIX_TABLE (PREFIX_0F3824) },
7015     { PREFIX_TABLE (PREFIX_0F3825) },
7016     { Bad_Opcode },
7017     { Bad_Opcode },
7018     /* 28 */
7019     { PREFIX_TABLE (PREFIX_0F3828) },
7020     { PREFIX_TABLE (PREFIX_0F3829) },
7021     { PREFIX_TABLE (PREFIX_0F382A) },
7022     { PREFIX_TABLE (PREFIX_0F382B) },
7023     { Bad_Opcode },
7024     { Bad_Opcode },
7025     { Bad_Opcode },
7026     { Bad_Opcode },
7027     /* 30 */
7028     { PREFIX_TABLE (PREFIX_0F3830) },
7029     { PREFIX_TABLE (PREFIX_0F3831) },
7030     { PREFIX_TABLE (PREFIX_0F3832) },
7031     { PREFIX_TABLE (PREFIX_0F3833) },
7032     { PREFIX_TABLE (PREFIX_0F3834) },
7033     { PREFIX_TABLE (PREFIX_0F3835) },
7034     { Bad_Opcode },
7035     { PREFIX_TABLE (PREFIX_0F3837) },
7036     /* 38 */
7037     { PREFIX_TABLE (PREFIX_0F3838) },
7038     { PREFIX_TABLE (PREFIX_0F3839) },
7039     { PREFIX_TABLE (PREFIX_0F383A) },
7040     { PREFIX_TABLE (PREFIX_0F383B) },
7041     { PREFIX_TABLE (PREFIX_0F383C) },
7042     { PREFIX_TABLE (PREFIX_0F383D) },
7043     { PREFIX_TABLE (PREFIX_0F383E) },
7044     { PREFIX_TABLE (PREFIX_0F383F) },
7045     /* 40 */
7046     { PREFIX_TABLE (PREFIX_0F3840) },
7047     { PREFIX_TABLE (PREFIX_0F3841) },
7048     { Bad_Opcode },
7049     { Bad_Opcode },
7050     { Bad_Opcode },
7051     { Bad_Opcode },
7052     { Bad_Opcode },
7053     { Bad_Opcode },
7054     /* 48 */
7055     { Bad_Opcode },
7056     { Bad_Opcode },
7057     { Bad_Opcode },
7058     { Bad_Opcode },
7059     { Bad_Opcode },
7060     { Bad_Opcode },
7061     { Bad_Opcode },
7062     { Bad_Opcode },
7063     /* 50 */
7064     { Bad_Opcode },
7065     { Bad_Opcode },
7066     { Bad_Opcode },
7067     { Bad_Opcode },
7068     { Bad_Opcode },
7069     { Bad_Opcode },
7070     { Bad_Opcode },
7071     { Bad_Opcode },
7072     /* 58 */
7073     { Bad_Opcode },
7074     { Bad_Opcode },
7075     { Bad_Opcode },
7076     { Bad_Opcode },
7077     { Bad_Opcode },
7078     { Bad_Opcode },
7079     { Bad_Opcode },
7080     { Bad_Opcode },
7081     /* 60 */
7082     { Bad_Opcode },
7083     { Bad_Opcode },
7084     { Bad_Opcode },
7085     { Bad_Opcode },
7086     { Bad_Opcode },
7087     { Bad_Opcode },
7088     { Bad_Opcode },
7089     { Bad_Opcode },
7090     /* 68 */
7091     { Bad_Opcode },
7092     { Bad_Opcode },
7093     { Bad_Opcode },
7094     { Bad_Opcode },
7095     { Bad_Opcode },
7096     { Bad_Opcode },
7097     { Bad_Opcode },
7098     { Bad_Opcode },
7099     /* 70 */
7100     { Bad_Opcode },
7101     { Bad_Opcode },
7102     { Bad_Opcode },
7103     { Bad_Opcode },
7104     { Bad_Opcode },
7105     { Bad_Opcode },
7106     { Bad_Opcode },
7107     { Bad_Opcode },
7108     /* 78 */
7109     { Bad_Opcode },
7110     { Bad_Opcode },
7111     { Bad_Opcode },
7112     { Bad_Opcode },
7113     { Bad_Opcode },
7114     { Bad_Opcode },
7115     { Bad_Opcode },
7116     { Bad_Opcode },
7117     /* 80 */
7118     { PREFIX_TABLE (PREFIX_0F3880) },
7119     { PREFIX_TABLE (PREFIX_0F3881) },
7120     { PREFIX_TABLE (PREFIX_0F3882) },
7121     { Bad_Opcode },
7122     { Bad_Opcode },
7123     { Bad_Opcode },
7124     { Bad_Opcode },
7125     { Bad_Opcode },
7126     /* 88 */
7127     { Bad_Opcode },
7128     { Bad_Opcode },
7129     { Bad_Opcode },
7130     { Bad_Opcode },
7131     { Bad_Opcode },
7132     { Bad_Opcode },
7133     { Bad_Opcode },
7134     { Bad_Opcode },
7135     /* 90 */
7136     { Bad_Opcode },
7137     { Bad_Opcode },
7138     { Bad_Opcode },
7139     { Bad_Opcode },
7140     { Bad_Opcode },
7141     { Bad_Opcode },
7142     { Bad_Opcode },
7143     { Bad_Opcode },
7144     /* 98 */
7145     { Bad_Opcode },
7146     { Bad_Opcode },
7147     { Bad_Opcode },
7148     { Bad_Opcode },
7149     { Bad_Opcode },
7150     { Bad_Opcode },
7151     { Bad_Opcode },
7152     { Bad_Opcode },
7153     /* a0 */
7154     { Bad_Opcode },
7155     { Bad_Opcode },
7156     { Bad_Opcode },
7157     { Bad_Opcode },
7158     { Bad_Opcode },
7159     { Bad_Opcode },
7160     { Bad_Opcode },
7161     { Bad_Opcode },
7162     /* a8 */
7163     { Bad_Opcode },
7164     { Bad_Opcode },
7165     { Bad_Opcode },
7166     { Bad_Opcode },
7167     { Bad_Opcode },
7168     { Bad_Opcode },
7169     { Bad_Opcode },
7170     { Bad_Opcode },
7171     /* b0 */
7172     { Bad_Opcode },
7173     { Bad_Opcode },
7174     { Bad_Opcode },
7175     { Bad_Opcode },
7176     { Bad_Opcode },
7177     { Bad_Opcode },
7178     { Bad_Opcode },
7179     { Bad_Opcode },
7180     /* b8 */
7181     { Bad_Opcode },
7182     { Bad_Opcode },
7183     { Bad_Opcode },
7184     { Bad_Opcode },
7185     { Bad_Opcode },
7186     { Bad_Opcode },
7187     { Bad_Opcode },
7188     { Bad_Opcode },
7189     /* c0 */
7190     { Bad_Opcode },
7191     { Bad_Opcode },
7192     { Bad_Opcode },
7193     { Bad_Opcode },
7194     { Bad_Opcode },
7195     { Bad_Opcode },
7196     { Bad_Opcode },
7197     { Bad_Opcode },
7198     /* c8 */
7199     { PREFIX_TABLE (PREFIX_0F38C8) },
7200     { PREFIX_TABLE (PREFIX_0F38C9) },
7201     { PREFIX_TABLE (PREFIX_0F38CA) },
7202     { PREFIX_TABLE (PREFIX_0F38CB) },
7203     { PREFIX_TABLE (PREFIX_0F38CC) },
7204     { PREFIX_TABLE (PREFIX_0F38CD) },
7205     { Bad_Opcode },
7206     { Bad_Opcode },
7207     /* d0 */
7208     { Bad_Opcode },
7209     { Bad_Opcode },
7210     { Bad_Opcode },
7211     { Bad_Opcode },
7212     { Bad_Opcode },
7213     { Bad_Opcode },
7214     { Bad_Opcode },
7215     { Bad_Opcode },
7216     /* d8 */
7217     { Bad_Opcode },
7218     { Bad_Opcode },
7219     { Bad_Opcode },
7220     { PREFIX_TABLE (PREFIX_0F38DB) },
7221     { PREFIX_TABLE (PREFIX_0F38DC) },
7222     { PREFIX_TABLE (PREFIX_0F38DD) },
7223     { PREFIX_TABLE (PREFIX_0F38DE) },
7224     { PREFIX_TABLE (PREFIX_0F38DF) },
7225     /* e0 */
7226     { Bad_Opcode },
7227     { Bad_Opcode },
7228     { Bad_Opcode },
7229     { Bad_Opcode },
7230     { Bad_Opcode },
7231     { Bad_Opcode },
7232     { Bad_Opcode },
7233     { Bad_Opcode },
7234     /* e8 */
7235     { Bad_Opcode },
7236     { Bad_Opcode },
7237     { Bad_Opcode },
7238     { Bad_Opcode },
7239     { Bad_Opcode },
7240     { Bad_Opcode },
7241     { Bad_Opcode },
7242     { Bad_Opcode },
7243     /* f0 */
7244     { PREFIX_TABLE (PREFIX_0F38F0) },
7245     { PREFIX_TABLE (PREFIX_0F38F1) },
7246     { Bad_Opcode },
7247     { Bad_Opcode },
7248     { Bad_Opcode },
7249     { Bad_Opcode },
7250     { PREFIX_TABLE (PREFIX_0F38F6) },
7251     { Bad_Opcode },
7252     /* f8 */
7253     { Bad_Opcode },
7254     { Bad_Opcode },
7255     { Bad_Opcode },
7256     { Bad_Opcode },
7257     { Bad_Opcode },
7258     { Bad_Opcode },
7259     { Bad_Opcode },
7260     { Bad_Opcode },
7261   },
7262   /* THREE_BYTE_0F3A */
7263   {
7264     /* 00 */
7265     { Bad_Opcode },
7266     { Bad_Opcode },
7267     { Bad_Opcode },
7268     { Bad_Opcode },
7269     { Bad_Opcode },
7270     { Bad_Opcode },
7271     { Bad_Opcode },
7272     { Bad_Opcode },
7273     /* 08 */
7274     { PREFIX_TABLE (PREFIX_0F3A08) },
7275     { PREFIX_TABLE (PREFIX_0F3A09) },
7276     { PREFIX_TABLE (PREFIX_0F3A0A) },
7277     { PREFIX_TABLE (PREFIX_0F3A0B) },
7278     { PREFIX_TABLE (PREFIX_0F3A0C) },
7279     { PREFIX_TABLE (PREFIX_0F3A0D) },
7280     { PREFIX_TABLE (PREFIX_0F3A0E) },
7281     { "palignr",        { MX, EM, Ib }, PREFIX_OPCODE },
7282     /* 10 */
7283     { Bad_Opcode },
7284     { Bad_Opcode },
7285     { Bad_Opcode },
7286     { Bad_Opcode },
7287     { PREFIX_TABLE (PREFIX_0F3A14) },
7288     { PREFIX_TABLE (PREFIX_0F3A15) },
7289     { PREFIX_TABLE (PREFIX_0F3A16) },
7290     { PREFIX_TABLE (PREFIX_0F3A17) },
7291     /* 18 */
7292     { Bad_Opcode },
7293     { Bad_Opcode },
7294     { Bad_Opcode },
7295     { Bad_Opcode },
7296     { Bad_Opcode },
7297     { Bad_Opcode },
7298     { Bad_Opcode },
7299     { Bad_Opcode },
7300     /* 20 */
7301     { PREFIX_TABLE (PREFIX_0F3A20) },
7302     { PREFIX_TABLE (PREFIX_0F3A21) },
7303     { PREFIX_TABLE (PREFIX_0F3A22) },
7304     { Bad_Opcode },
7305     { Bad_Opcode },
7306     { Bad_Opcode },
7307     { Bad_Opcode },
7308     { Bad_Opcode },
7309     /* 28 */
7310     { Bad_Opcode },
7311     { Bad_Opcode },
7312     { Bad_Opcode },
7313     { Bad_Opcode },
7314     { Bad_Opcode },
7315     { Bad_Opcode },
7316     { Bad_Opcode },
7317     { Bad_Opcode },
7318     /* 30 */
7319     { Bad_Opcode },
7320     { Bad_Opcode },
7321     { Bad_Opcode },
7322     { Bad_Opcode },
7323     { Bad_Opcode },
7324     { Bad_Opcode },
7325     { Bad_Opcode },
7326     { Bad_Opcode },
7327     /* 38 */
7328     { Bad_Opcode },
7329     { Bad_Opcode },
7330     { Bad_Opcode },
7331     { Bad_Opcode },
7332     { Bad_Opcode },
7333     { Bad_Opcode },
7334     { Bad_Opcode },
7335     { Bad_Opcode },
7336     /* 40 */
7337     { PREFIX_TABLE (PREFIX_0F3A40) },
7338     { PREFIX_TABLE (PREFIX_0F3A41) },
7339     { PREFIX_TABLE (PREFIX_0F3A42) },
7340     { Bad_Opcode },
7341     { PREFIX_TABLE (PREFIX_0F3A44) },
7342     { Bad_Opcode },
7343     { Bad_Opcode },
7344     { Bad_Opcode },
7345     /* 48 */
7346     { Bad_Opcode },
7347     { Bad_Opcode },
7348     { Bad_Opcode },
7349     { Bad_Opcode },
7350     { Bad_Opcode },
7351     { Bad_Opcode },
7352     { Bad_Opcode },
7353     { Bad_Opcode },
7354     /* 50 */
7355     { Bad_Opcode },
7356     { Bad_Opcode },
7357     { Bad_Opcode },
7358     { Bad_Opcode },
7359     { Bad_Opcode },
7360     { Bad_Opcode },
7361     { Bad_Opcode },
7362     { Bad_Opcode },
7363     /* 58 */
7364     { Bad_Opcode },
7365     { Bad_Opcode },
7366     { Bad_Opcode },
7367     { Bad_Opcode },
7368     { Bad_Opcode },
7369     { Bad_Opcode },
7370     { Bad_Opcode },
7371     { Bad_Opcode },
7372     /* 60 */
7373     { PREFIX_TABLE (PREFIX_0F3A60) },
7374     { PREFIX_TABLE (PREFIX_0F3A61) },
7375     { PREFIX_TABLE (PREFIX_0F3A62) },
7376     { PREFIX_TABLE (PREFIX_0F3A63) },
7377     { Bad_Opcode },
7378     { Bad_Opcode },
7379     { Bad_Opcode },
7380     { Bad_Opcode },
7381     /* 68 */
7382     { Bad_Opcode },
7383     { Bad_Opcode },
7384     { Bad_Opcode },
7385     { Bad_Opcode },
7386     { Bad_Opcode },
7387     { Bad_Opcode },
7388     { Bad_Opcode },
7389     { Bad_Opcode },
7390     /* 70 */
7391     { Bad_Opcode },
7392     { Bad_Opcode },
7393     { Bad_Opcode },
7394     { Bad_Opcode },
7395     { Bad_Opcode },
7396     { Bad_Opcode },
7397     { Bad_Opcode },
7398     { Bad_Opcode },
7399     /* 78 */
7400     { Bad_Opcode },
7401     { Bad_Opcode },
7402     { Bad_Opcode },
7403     { Bad_Opcode },
7404     { Bad_Opcode },
7405     { Bad_Opcode },
7406     { Bad_Opcode },
7407     { Bad_Opcode },
7408     /* 80 */
7409     { Bad_Opcode },
7410     { Bad_Opcode },
7411     { Bad_Opcode },
7412     { Bad_Opcode },
7413     { Bad_Opcode },
7414     { Bad_Opcode },
7415     { Bad_Opcode },
7416     { Bad_Opcode },
7417     /* 88 */
7418     { Bad_Opcode },
7419     { Bad_Opcode },
7420     { Bad_Opcode },
7421     { Bad_Opcode },
7422     { Bad_Opcode },
7423     { Bad_Opcode },
7424     { Bad_Opcode },
7425     { Bad_Opcode },
7426     /* 90 */
7427     { Bad_Opcode },
7428     { Bad_Opcode },
7429     { Bad_Opcode },
7430     { Bad_Opcode },
7431     { Bad_Opcode },
7432     { Bad_Opcode },
7433     { Bad_Opcode },
7434     { Bad_Opcode },
7435     /* 98 */
7436     { Bad_Opcode },
7437     { Bad_Opcode },
7438     { Bad_Opcode },
7439     { Bad_Opcode },
7440     { Bad_Opcode },
7441     { Bad_Opcode },
7442     { Bad_Opcode },
7443     { Bad_Opcode },
7444     /* a0 */
7445     { Bad_Opcode },
7446     { Bad_Opcode },
7447     { Bad_Opcode },
7448     { Bad_Opcode },
7449     { Bad_Opcode },
7450     { Bad_Opcode },
7451     { Bad_Opcode },
7452     { Bad_Opcode },
7453     /* a8 */
7454     { Bad_Opcode },
7455     { Bad_Opcode },
7456     { Bad_Opcode },
7457     { Bad_Opcode },
7458     { Bad_Opcode },
7459     { Bad_Opcode },
7460     { Bad_Opcode },
7461     { Bad_Opcode },
7462     /* b0 */
7463     { Bad_Opcode },
7464     { Bad_Opcode },
7465     { Bad_Opcode },
7466     { Bad_Opcode },
7467     { Bad_Opcode },
7468     { Bad_Opcode },
7469     { Bad_Opcode },
7470     { Bad_Opcode },
7471     /* b8 */
7472     { Bad_Opcode },
7473     { Bad_Opcode },
7474     { Bad_Opcode },
7475     { Bad_Opcode },
7476     { Bad_Opcode },
7477     { Bad_Opcode },
7478     { Bad_Opcode },
7479     { Bad_Opcode },
7480     /* c0 */
7481     { Bad_Opcode },
7482     { Bad_Opcode },
7483     { Bad_Opcode },
7484     { Bad_Opcode },
7485     { Bad_Opcode },
7486     { Bad_Opcode },
7487     { Bad_Opcode },
7488     { Bad_Opcode },
7489     /* c8 */
7490     { Bad_Opcode },
7491     { Bad_Opcode },
7492     { Bad_Opcode },
7493     { Bad_Opcode },
7494     { PREFIX_TABLE (PREFIX_0F3ACC) },
7495     { Bad_Opcode },
7496     { Bad_Opcode },
7497     { Bad_Opcode },
7498     /* d0 */
7499     { Bad_Opcode },
7500     { Bad_Opcode },
7501     { Bad_Opcode },
7502     { Bad_Opcode },
7503     { Bad_Opcode },
7504     { Bad_Opcode },
7505     { Bad_Opcode },
7506     { Bad_Opcode },
7507     /* d8 */
7508     { Bad_Opcode },
7509     { Bad_Opcode },
7510     { Bad_Opcode },
7511     { Bad_Opcode },
7512     { Bad_Opcode },
7513     { Bad_Opcode },
7514     { Bad_Opcode },
7515     { PREFIX_TABLE (PREFIX_0F3ADF) },
7516     /* e0 */
7517     { Bad_Opcode },
7518     { Bad_Opcode },
7519     { Bad_Opcode },
7520     { Bad_Opcode },
7521     { Bad_Opcode },
7522     { Bad_Opcode },
7523     { Bad_Opcode },
7524     { Bad_Opcode },
7525     /* e8 */
7526     { Bad_Opcode },
7527     { Bad_Opcode },
7528     { Bad_Opcode },
7529     { Bad_Opcode },
7530     { Bad_Opcode },
7531     { Bad_Opcode },
7532     { Bad_Opcode },
7533     { Bad_Opcode },
7534     /* f0 */
7535     { Bad_Opcode },
7536     { Bad_Opcode },
7537     { Bad_Opcode },
7538     { Bad_Opcode },
7539     { Bad_Opcode },
7540     { Bad_Opcode },
7541     { Bad_Opcode },
7542     { Bad_Opcode },
7543     /* f8 */
7544     { Bad_Opcode },
7545     { Bad_Opcode },
7546     { Bad_Opcode },
7547     { Bad_Opcode },
7548     { Bad_Opcode },
7549     { Bad_Opcode },
7550     { Bad_Opcode },
7551     { Bad_Opcode },
7552   },
7553 };
7554
7555 static const struct dis386 xop_table[][256] = {
7556   /* XOP_08 */
7557   {
7558     /* 00 */
7559     { Bad_Opcode },
7560     { Bad_Opcode },
7561     { Bad_Opcode },
7562     { Bad_Opcode },
7563     { Bad_Opcode },
7564     { Bad_Opcode },
7565     { Bad_Opcode },
7566     { Bad_Opcode },
7567     /* 08 */
7568     { Bad_Opcode },
7569     { Bad_Opcode },
7570     { Bad_Opcode },
7571     { Bad_Opcode },
7572     { Bad_Opcode },
7573     { Bad_Opcode },
7574     { Bad_Opcode },
7575     { Bad_Opcode },
7576     /* 10 */
7577     { Bad_Opcode },
7578     { Bad_Opcode },
7579     { Bad_Opcode },
7580     { Bad_Opcode },
7581     { Bad_Opcode },
7582     { Bad_Opcode },
7583     { Bad_Opcode },
7584     { Bad_Opcode },
7585     /* 18 */
7586     { Bad_Opcode },
7587     { Bad_Opcode },
7588     { Bad_Opcode },
7589     { Bad_Opcode },
7590     { Bad_Opcode },
7591     { Bad_Opcode },
7592     { Bad_Opcode },
7593     { Bad_Opcode },
7594     /* 20 */
7595     { Bad_Opcode },
7596     { Bad_Opcode },
7597     { Bad_Opcode },
7598     { Bad_Opcode },
7599     { Bad_Opcode },
7600     { Bad_Opcode },
7601     { Bad_Opcode },
7602     { Bad_Opcode },
7603     /* 28 */
7604     { Bad_Opcode },
7605     { Bad_Opcode },
7606     { Bad_Opcode },
7607     { Bad_Opcode },
7608     { Bad_Opcode },
7609     { Bad_Opcode },
7610     { Bad_Opcode },
7611     { Bad_Opcode },
7612     /* 30 */
7613     { Bad_Opcode },
7614     { Bad_Opcode },
7615     { Bad_Opcode },
7616     { Bad_Opcode },
7617     { Bad_Opcode },
7618     { Bad_Opcode },
7619     { Bad_Opcode },
7620     { Bad_Opcode },
7621     /* 38 */
7622     { Bad_Opcode },
7623     { Bad_Opcode },
7624     { Bad_Opcode },
7625     { Bad_Opcode },
7626     { Bad_Opcode },
7627     { Bad_Opcode },
7628     { Bad_Opcode },
7629     { Bad_Opcode },
7630     /* 40 */
7631     { Bad_Opcode },
7632     { Bad_Opcode },
7633     { Bad_Opcode },
7634     { Bad_Opcode },
7635     { Bad_Opcode },
7636     { Bad_Opcode },
7637     { Bad_Opcode },
7638     { Bad_Opcode },
7639     /* 48 */
7640     { Bad_Opcode },
7641     { Bad_Opcode },
7642     { Bad_Opcode },
7643     { Bad_Opcode },
7644     { Bad_Opcode },
7645     { Bad_Opcode },
7646     { Bad_Opcode },
7647     { Bad_Opcode },
7648     /* 50 */
7649     { Bad_Opcode },
7650     { Bad_Opcode },
7651     { Bad_Opcode },
7652     { Bad_Opcode },
7653     { Bad_Opcode },
7654     { Bad_Opcode },
7655     { Bad_Opcode },
7656     { Bad_Opcode },
7657     /* 58 */
7658     { Bad_Opcode },
7659     { Bad_Opcode },
7660     { Bad_Opcode },
7661     { Bad_Opcode },
7662     { Bad_Opcode },
7663     { Bad_Opcode },
7664     { Bad_Opcode },
7665     { Bad_Opcode },
7666     /* 60 */
7667     { Bad_Opcode },
7668     { Bad_Opcode },
7669     { Bad_Opcode },
7670     { Bad_Opcode },
7671     { Bad_Opcode },
7672     { Bad_Opcode },
7673     { Bad_Opcode },
7674     { Bad_Opcode },
7675     /* 68 */
7676     { Bad_Opcode },
7677     { Bad_Opcode },
7678     { Bad_Opcode },
7679     { Bad_Opcode },
7680     { Bad_Opcode },
7681     { Bad_Opcode },
7682     { Bad_Opcode },
7683     { Bad_Opcode },
7684     /* 70 */
7685     { Bad_Opcode },
7686     { Bad_Opcode },
7687     { Bad_Opcode },
7688     { Bad_Opcode },
7689     { Bad_Opcode },
7690     { Bad_Opcode },
7691     { Bad_Opcode },
7692     { Bad_Opcode },
7693     /* 78 */
7694     { Bad_Opcode },
7695     { Bad_Opcode },
7696     { Bad_Opcode },
7697     { Bad_Opcode },
7698     { Bad_Opcode },
7699     { Bad_Opcode },
7700     { Bad_Opcode },
7701     { Bad_Opcode },
7702     /* 80 */
7703     { Bad_Opcode },
7704     { Bad_Opcode },
7705     { Bad_Opcode },
7706     { Bad_Opcode },
7707     { Bad_Opcode },
7708     { "vpmacssww",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7709     { "vpmacsswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7710     { "vpmacssdql",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7711     /* 88 */
7712     { Bad_Opcode },
7713     { Bad_Opcode },
7714     { Bad_Opcode },
7715     { Bad_Opcode },
7716     { Bad_Opcode },
7717     { Bad_Opcode },
7718     { "vpmacssdd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7719     { "vpmacssdqh",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7720     /* 90 */
7721     { Bad_Opcode },
7722     { Bad_Opcode },
7723     { Bad_Opcode },
7724     { Bad_Opcode },
7725     { Bad_Opcode },
7726     { "vpmacsww",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7727     { "vpmacswd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7728     { "vpmacsdql",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7729     /* 98 */
7730     { Bad_Opcode },
7731     { Bad_Opcode },
7732     { Bad_Opcode },
7733     { Bad_Opcode },
7734     { Bad_Opcode },
7735     { Bad_Opcode },
7736     { "vpmacsdd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7737     { "vpmacsdqh",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7738     /* a0 */
7739     { Bad_Opcode },
7740     { Bad_Opcode },
7741     { "vpcmov",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7742     { "vpperm",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7743     { Bad_Opcode },
7744     { Bad_Opcode },
7745     { "vpmadcsswd",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7746     { Bad_Opcode },
7747     /* a8 */
7748     { Bad_Opcode },
7749     { Bad_Opcode },
7750     { Bad_Opcode },
7751     { Bad_Opcode },
7752     { Bad_Opcode },
7753     { Bad_Opcode },
7754     { Bad_Opcode },
7755     { Bad_Opcode },
7756     /* b0 */
7757     { Bad_Opcode },
7758     { Bad_Opcode },
7759     { Bad_Opcode },
7760     { Bad_Opcode },
7761     { Bad_Opcode },
7762     { Bad_Opcode },
7763     { "vpmadcswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7764     { Bad_Opcode },
7765     /* b8 */
7766     { Bad_Opcode },
7767     { Bad_Opcode },
7768     { Bad_Opcode },
7769     { Bad_Opcode },
7770     { Bad_Opcode },
7771     { Bad_Opcode },
7772     { Bad_Opcode },
7773     { Bad_Opcode },
7774     /* c0 */
7775     { "vprotb",         { XM, Vex_2src_1, Ib }, 0 },
7776     { "vprotw",         { XM, Vex_2src_1, Ib }, 0 },
7777     { "vprotd",         { XM, Vex_2src_1, Ib }, 0 },
7778     { "vprotq",         { XM, Vex_2src_1, Ib }, 0 },
7779     { Bad_Opcode },
7780     { Bad_Opcode },
7781     { Bad_Opcode },
7782     { Bad_Opcode },
7783     /* c8 */
7784     { Bad_Opcode },
7785     { Bad_Opcode },
7786     { Bad_Opcode },
7787     { Bad_Opcode },
7788     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
7789     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
7790     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
7791     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
7792     /* d0 */
7793     { Bad_Opcode },
7794     { Bad_Opcode },
7795     { Bad_Opcode },
7796     { Bad_Opcode },
7797     { Bad_Opcode },
7798     { Bad_Opcode },
7799     { Bad_Opcode },
7800     { Bad_Opcode },
7801     /* d8 */
7802     { Bad_Opcode },
7803     { Bad_Opcode },
7804     { Bad_Opcode },
7805     { Bad_Opcode },
7806     { Bad_Opcode },
7807     { Bad_Opcode },
7808     { Bad_Opcode },
7809     { Bad_Opcode },
7810     /* e0 */
7811     { Bad_Opcode },
7812     { Bad_Opcode },
7813     { Bad_Opcode },
7814     { Bad_Opcode },
7815     { Bad_Opcode },
7816     { Bad_Opcode },
7817     { Bad_Opcode },
7818     { Bad_Opcode },
7819     /* e8 */
7820     { Bad_Opcode },
7821     { Bad_Opcode },
7822     { Bad_Opcode },
7823     { Bad_Opcode },
7824     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
7825     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
7826     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
7827     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
7828     /* f0 */
7829     { Bad_Opcode },
7830     { Bad_Opcode },
7831     { Bad_Opcode },
7832     { Bad_Opcode },
7833     { Bad_Opcode },
7834     { Bad_Opcode },
7835     { Bad_Opcode },
7836     { Bad_Opcode },
7837     /* f8 */
7838     { Bad_Opcode },
7839     { Bad_Opcode },
7840     { Bad_Opcode },
7841     { Bad_Opcode },
7842     { Bad_Opcode },
7843     { Bad_Opcode },
7844     { Bad_Opcode },
7845     { Bad_Opcode },
7846   },
7847   /* XOP_09 */
7848   {
7849     /* 00 */
7850     { Bad_Opcode },
7851     { REG_TABLE (REG_XOP_TBM_01) },
7852     { REG_TABLE (REG_XOP_TBM_02) },
7853     { Bad_Opcode },
7854     { Bad_Opcode },
7855     { Bad_Opcode },
7856     { Bad_Opcode },
7857     { Bad_Opcode },
7858     /* 08 */
7859     { Bad_Opcode },
7860     { Bad_Opcode },
7861     { Bad_Opcode },
7862     { Bad_Opcode },
7863     { Bad_Opcode },
7864     { Bad_Opcode },
7865     { Bad_Opcode },
7866     { Bad_Opcode },
7867     /* 10 */
7868     { Bad_Opcode },
7869     { Bad_Opcode },
7870     { REG_TABLE (REG_XOP_LWPCB) },
7871     { Bad_Opcode },
7872     { Bad_Opcode },
7873     { Bad_Opcode },
7874     { Bad_Opcode },
7875     { Bad_Opcode },
7876     /* 18 */
7877     { Bad_Opcode },
7878     { Bad_Opcode },
7879     { Bad_Opcode },
7880     { Bad_Opcode },
7881     { Bad_Opcode },
7882     { Bad_Opcode },
7883     { Bad_Opcode },
7884     { Bad_Opcode },
7885     /* 20 */
7886     { Bad_Opcode },
7887     { Bad_Opcode },
7888     { Bad_Opcode },
7889     { Bad_Opcode },
7890     { Bad_Opcode },
7891     { Bad_Opcode },
7892     { Bad_Opcode },
7893     { Bad_Opcode },
7894     /* 28 */
7895     { Bad_Opcode },
7896     { Bad_Opcode },
7897     { Bad_Opcode },
7898     { Bad_Opcode },
7899     { Bad_Opcode },
7900     { Bad_Opcode },
7901     { Bad_Opcode },
7902     { Bad_Opcode },
7903     /* 30 */
7904     { Bad_Opcode },
7905     { Bad_Opcode },
7906     { Bad_Opcode },
7907     { Bad_Opcode },
7908     { Bad_Opcode },
7909     { Bad_Opcode },
7910     { Bad_Opcode },
7911     { Bad_Opcode },
7912     /* 38 */
7913     { Bad_Opcode },
7914     { Bad_Opcode },
7915     { Bad_Opcode },
7916     { Bad_Opcode },
7917     { Bad_Opcode },
7918     { Bad_Opcode },
7919     { Bad_Opcode },
7920     { Bad_Opcode },
7921     /* 40 */
7922     { Bad_Opcode },
7923     { Bad_Opcode },
7924     { Bad_Opcode },
7925     { Bad_Opcode },
7926     { Bad_Opcode },
7927     { Bad_Opcode },
7928     { Bad_Opcode },
7929     { Bad_Opcode },
7930     /* 48 */
7931     { Bad_Opcode },
7932     { Bad_Opcode },
7933     { Bad_Opcode },
7934     { Bad_Opcode },
7935     { Bad_Opcode },
7936     { Bad_Opcode },
7937     { Bad_Opcode },
7938     { Bad_Opcode },
7939     /* 50 */
7940     { Bad_Opcode },
7941     { Bad_Opcode },
7942     { Bad_Opcode },
7943     { Bad_Opcode },
7944     { Bad_Opcode },
7945     { Bad_Opcode },
7946     { Bad_Opcode },
7947     { Bad_Opcode },
7948     /* 58 */
7949     { Bad_Opcode },
7950     { Bad_Opcode },
7951     { Bad_Opcode },
7952     { Bad_Opcode },
7953     { Bad_Opcode },
7954     { Bad_Opcode },
7955     { Bad_Opcode },
7956     { Bad_Opcode },
7957     /* 60 */
7958     { Bad_Opcode },
7959     { Bad_Opcode },
7960     { Bad_Opcode },
7961     { Bad_Opcode },
7962     { Bad_Opcode },
7963     { Bad_Opcode },
7964     { Bad_Opcode },
7965     { Bad_Opcode },
7966     /* 68 */
7967     { Bad_Opcode },
7968     { Bad_Opcode },
7969     { Bad_Opcode },
7970     { Bad_Opcode },
7971     { Bad_Opcode },
7972     { Bad_Opcode },
7973     { Bad_Opcode },
7974     { Bad_Opcode },
7975     /* 70 */
7976     { Bad_Opcode },
7977     { Bad_Opcode },
7978     { Bad_Opcode },
7979     { Bad_Opcode },
7980     { Bad_Opcode },
7981     { Bad_Opcode },
7982     { Bad_Opcode },
7983     { Bad_Opcode },
7984     /* 78 */
7985     { Bad_Opcode },
7986     { Bad_Opcode },
7987     { Bad_Opcode },
7988     { Bad_Opcode },
7989     { Bad_Opcode },
7990     { Bad_Opcode },
7991     { Bad_Opcode },
7992     { Bad_Opcode },
7993     /* 80 */
7994     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
7995     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
7996     { "vfrczss",        { XM, EXd }, 0 },
7997     { "vfrczsd",        { XM, EXq }, 0 },
7998     { Bad_Opcode },
7999     { Bad_Opcode },
8000     { Bad_Opcode },
8001     { Bad_Opcode },
8002     /* 88 */
8003     { Bad_Opcode },
8004     { Bad_Opcode },
8005     { Bad_Opcode },
8006     { Bad_Opcode },
8007     { Bad_Opcode },
8008     { Bad_Opcode },
8009     { Bad_Opcode },
8010     { Bad_Opcode },
8011     /* 90 */
8012     { "vprotb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8013     { "vprotw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8014     { "vprotd",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8015     { "vprotq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8016     { "vpshlb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8017     { "vpshlw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8018     { "vpshld",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8019     { "vpshlq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8020     /* 98 */
8021     { "vpshab",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8022     { "vpshaw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8023     { "vpshad",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8024     { "vpshaq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8025     { Bad_Opcode },
8026     { Bad_Opcode },
8027     { Bad_Opcode },
8028     { Bad_Opcode },
8029     /* a0 */
8030     { Bad_Opcode },
8031     { Bad_Opcode },
8032     { Bad_Opcode },
8033     { Bad_Opcode },
8034     { Bad_Opcode },
8035     { Bad_Opcode },
8036     { Bad_Opcode },
8037     { Bad_Opcode },
8038     /* a8 */
8039     { Bad_Opcode },
8040     { Bad_Opcode },
8041     { Bad_Opcode },
8042     { Bad_Opcode },
8043     { Bad_Opcode },
8044     { Bad_Opcode },
8045     { Bad_Opcode },
8046     { Bad_Opcode },
8047     /* b0 */
8048     { Bad_Opcode },
8049     { Bad_Opcode },
8050     { Bad_Opcode },
8051     { Bad_Opcode },
8052     { Bad_Opcode },
8053     { Bad_Opcode },
8054     { Bad_Opcode },
8055     { Bad_Opcode },
8056     /* b8 */
8057     { Bad_Opcode },
8058     { Bad_Opcode },
8059     { Bad_Opcode },
8060     { Bad_Opcode },
8061     { Bad_Opcode },
8062     { Bad_Opcode },
8063     { Bad_Opcode },
8064     { Bad_Opcode },
8065     /* c0 */
8066     { Bad_Opcode },
8067     { "vphaddbw",       { XM, EXxmm }, 0 },
8068     { "vphaddbd",       { XM, EXxmm }, 0 },
8069     { "vphaddbq",       { XM, EXxmm }, 0 },
8070     { Bad_Opcode },
8071     { Bad_Opcode },
8072     { "vphaddwd",       { XM, EXxmm }, 0 },
8073     { "vphaddwq",       { XM, EXxmm }, 0 },
8074     /* c8 */
8075     { Bad_Opcode },
8076     { Bad_Opcode },
8077     { Bad_Opcode },
8078     { "vphadddq",       { XM, EXxmm }, 0 },
8079     { Bad_Opcode },
8080     { Bad_Opcode },
8081     { Bad_Opcode },
8082     { Bad_Opcode },
8083     /* d0 */
8084     { Bad_Opcode },
8085     { "vphaddubw",      { XM, EXxmm }, 0 },
8086     { "vphaddubd",      { XM, EXxmm }, 0 },
8087     { "vphaddubq",      { XM, EXxmm }, 0 },
8088     { Bad_Opcode },
8089     { Bad_Opcode },
8090     { "vphadduwd",      { XM, EXxmm }, 0 },
8091     { "vphadduwq",      { XM, EXxmm }, 0 },
8092     /* d8 */
8093     { Bad_Opcode },
8094     { Bad_Opcode },
8095     { Bad_Opcode },
8096     { "vphaddudq",      { XM, EXxmm }, 0 },
8097     { Bad_Opcode },
8098     { Bad_Opcode },
8099     { Bad_Opcode },
8100     { Bad_Opcode },
8101     /* e0 */
8102     { Bad_Opcode },
8103     { "vphsubbw",       { XM, EXxmm }, 0 },
8104     { "vphsubwd",       { XM, EXxmm }, 0 },
8105     { "vphsubdq",       { XM, EXxmm }, 0 },
8106     { Bad_Opcode },
8107     { Bad_Opcode },
8108     { Bad_Opcode },
8109     { Bad_Opcode },
8110     /* e8 */
8111     { Bad_Opcode },
8112     { Bad_Opcode },
8113     { Bad_Opcode },
8114     { Bad_Opcode },
8115     { Bad_Opcode },
8116     { Bad_Opcode },
8117     { Bad_Opcode },
8118     { Bad_Opcode },
8119     /* f0 */
8120     { Bad_Opcode },
8121     { Bad_Opcode },
8122     { Bad_Opcode },
8123     { Bad_Opcode },
8124     { Bad_Opcode },
8125     { Bad_Opcode },
8126     { Bad_Opcode },
8127     { Bad_Opcode },
8128     /* f8 */
8129     { Bad_Opcode },
8130     { Bad_Opcode },
8131     { Bad_Opcode },
8132     { Bad_Opcode },
8133     { Bad_Opcode },
8134     { Bad_Opcode },
8135     { Bad_Opcode },
8136     { Bad_Opcode },
8137   },
8138   /* XOP_0A */
8139   {
8140     /* 00 */
8141     { Bad_Opcode },
8142     { Bad_Opcode },
8143     { Bad_Opcode },
8144     { Bad_Opcode },
8145     { Bad_Opcode },
8146     { Bad_Opcode },
8147     { Bad_Opcode },
8148     { Bad_Opcode },
8149     /* 08 */
8150     { Bad_Opcode },
8151     { Bad_Opcode },
8152     { Bad_Opcode },
8153     { Bad_Opcode },
8154     { Bad_Opcode },
8155     { Bad_Opcode },
8156     { Bad_Opcode },
8157     { Bad_Opcode },
8158     /* 10 */
8159     { "bextr",  { Gv, Ev, Iq }, 0 },
8160     { Bad_Opcode },
8161     { REG_TABLE (REG_XOP_LWP) },
8162     { Bad_Opcode },
8163     { Bad_Opcode },
8164     { Bad_Opcode },
8165     { Bad_Opcode },
8166     { Bad_Opcode },
8167     /* 18 */
8168     { Bad_Opcode },
8169     { Bad_Opcode },
8170     { Bad_Opcode },
8171     { Bad_Opcode },
8172     { Bad_Opcode },
8173     { Bad_Opcode },
8174     { Bad_Opcode },
8175     { Bad_Opcode },
8176     /* 20 */
8177     { Bad_Opcode },
8178     { Bad_Opcode },
8179     { Bad_Opcode },
8180     { Bad_Opcode },
8181     { Bad_Opcode },
8182     { Bad_Opcode },
8183     { Bad_Opcode },
8184     { Bad_Opcode },
8185     /* 28 */
8186     { Bad_Opcode },
8187     { Bad_Opcode },
8188     { Bad_Opcode },
8189     { Bad_Opcode },
8190     { Bad_Opcode },
8191     { Bad_Opcode },
8192     { Bad_Opcode },
8193     { Bad_Opcode },
8194     /* 30 */
8195     { Bad_Opcode },
8196     { Bad_Opcode },
8197     { Bad_Opcode },
8198     { Bad_Opcode },
8199     { Bad_Opcode },
8200     { Bad_Opcode },
8201     { Bad_Opcode },
8202     { Bad_Opcode },
8203     /* 38 */
8204     { Bad_Opcode },
8205     { Bad_Opcode },
8206     { Bad_Opcode },
8207     { Bad_Opcode },
8208     { Bad_Opcode },
8209     { Bad_Opcode },
8210     { Bad_Opcode },
8211     { Bad_Opcode },
8212     /* 40 */
8213     { Bad_Opcode },
8214     { Bad_Opcode },
8215     { Bad_Opcode },
8216     { Bad_Opcode },
8217     { Bad_Opcode },
8218     { Bad_Opcode },
8219     { Bad_Opcode },
8220     { Bad_Opcode },
8221     /* 48 */
8222     { Bad_Opcode },
8223     { Bad_Opcode },
8224     { Bad_Opcode },
8225     { Bad_Opcode },
8226     { Bad_Opcode },
8227     { Bad_Opcode },
8228     { Bad_Opcode },
8229     { Bad_Opcode },
8230     /* 50 */
8231     { Bad_Opcode },
8232     { Bad_Opcode },
8233     { Bad_Opcode },
8234     { Bad_Opcode },
8235     { Bad_Opcode },
8236     { Bad_Opcode },
8237     { Bad_Opcode },
8238     { Bad_Opcode },
8239     /* 58 */
8240     { Bad_Opcode },
8241     { Bad_Opcode },
8242     { Bad_Opcode },
8243     { Bad_Opcode },
8244     { Bad_Opcode },
8245     { Bad_Opcode },
8246     { Bad_Opcode },
8247     { Bad_Opcode },
8248     /* 60 */
8249     { Bad_Opcode },
8250     { Bad_Opcode },
8251     { Bad_Opcode },
8252     { Bad_Opcode },
8253     { Bad_Opcode },
8254     { Bad_Opcode },
8255     { Bad_Opcode },
8256     { Bad_Opcode },
8257     /* 68 */
8258     { Bad_Opcode },
8259     { Bad_Opcode },
8260     { Bad_Opcode },
8261     { Bad_Opcode },
8262     { Bad_Opcode },
8263     { Bad_Opcode },
8264     { Bad_Opcode },
8265     { Bad_Opcode },
8266     /* 70 */
8267     { Bad_Opcode },
8268     { Bad_Opcode },
8269     { Bad_Opcode },
8270     { Bad_Opcode },
8271     { Bad_Opcode },
8272     { Bad_Opcode },
8273     { Bad_Opcode },
8274     { Bad_Opcode },
8275     /* 78 */
8276     { Bad_Opcode },
8277     { Bad_Opcode },
8278     { Bad_Opcode },
8279     { Bad_Opcode },
8280     { Bad_Opcode },
8281     { Bad_Opcode },
8282     { Bad_Opcode },
8283     { Bad_Opcode },
8284     /* 80 */
8285     { Bad_Opcode },
8286     { Bad_Opcode },
8287     { Bad_Opcode },
8288     { Bad_Opcode },
8289     { Bad_Opcode },
8290     { Bad_Opcode },
8291     { Bad_Opcode },
8292     { Bad_Opcode },
8293     /* 88 */
8294     { Bad_Opcode },
8295     { Bad_Opcode },
8296     { Bad_Opcode },
8297     { Bad_Opcode },
8298     { Bad_Opcode },
8299     { Bad_Opcode },
8300     { Bad_Opcode },
8301     { Bad_Opcode },
8302     /* 90 */
8303     { Bad_Opcode },
8304     { Bad_Opcode },
8305     { Bad_Opcode },
8306     { Bad_Opcode },
8307     { Bad_Opcode },
8308     { Bad_Opcode },
8309     { Bad_Opcode },
8310     { Bad_Opcode },
8311     /* 98 */
8312     { Bad_Opcode },
8313     { Bad_Opcode },
8314     { Bad_Opcode },
8315     { Bad_Opcode },
8316     { Bad_Opcode },
8317     { Bad_Opcode },
8318     { Bad_Opcode },
8319     { Bad_Opcode },
8320     /* a0 */
8321     { Bad_Opcode },
8322     { Bad_Opcode },
8323     { Bad_Opcode },
8324     { Bad_Opcode },
8325     { Bad_Opcode },
8326     { Bad_Opcode },
8327     { Bad_Opcode },
8328     { Bad_Opcode },
8329     /* a8 */
8330     { Bad_Opcode },
8331     { Bad_Opcode },
8332     { Bad_Opcode },
8333     { Bad_Opcode },
8334     { Bad_Opcode },
8335     { Bad_Opcode },
8336     { Bad_Opcode },
8337     { Bad_Opcode },
8338     /* b0 */
8339     { Bad_Opcode },
8340     { Bad_Opcode },
8341     { Bad_Opcode },
8342     { Bad_Opcode },
8343     { Bad_Opcode },
8344     { Bad_Opcode },
8345     { Bad_Opcode },
8346     { Bad_Opcode },
8347     /* b8 */
8348     { Bad_Opcode },
8349     { Bad_Opcode },
8350     { Bad_Opcode },
8351     { Bad_Opcode },
8352     { Bad_Opcode },
8353     { Bad_Opcode },
8354     { Bad_Opcode },
8355     { Bad_Opcode },
8356     /* c0 */
8357     { Bad_Opcode },
8358     { Bad_Opcode },
8359     { Bad_Opcode },
8360     { Bad_Opcode },
8361     { Bad_Opcode },
8362     { Bad_Opcode },
8363     { Bad_Opcode },
8364     { Bad_Opcode },
8365     /* c8 */
8366     { Bad_Opcode },
8367     { Bad_Opcode },
8368     { Bad_Opcode },
8369     { Bad_Opcode },
8370     { Bad_Opcode },
8371     { Bad_Opcode },
8372     { Bad_Opcode },
8373     { Bad_Opcode },
8374     /* d0 */
8375     { Bad_Opcode },
8376     { Bad_Opcode },
8377     { Bad_Opcode },
8378     { Bad_Opcode },
8379     { Bad_Opcode },
8380     { Bad_Opcode },
8381     { Bad_Opcode },
8382     { Bad_Opcode },
8383     /* d8 */
8384     { Bad_Opcode },
8385     { Bad_Opcode },
8386     { Bad_Opcode },
8387     { Bad_Opcode },
8388     { Bad_Opcode },
8389     { Bad_Opcode },
8390     { Bad_Opcode },
8391     { Bad_Opcode },
8392     /* e0 */
8393     { Bad_Opcode },
8394     { Bad_Opcode },
8395     { Bad_Opcode },
8396     { Bad_Opcode },
8397     { Bad_Opcode },
8398     { Bad_Opcode },
8399     { Bad_Opcode },
8400     { Bad_Opcode },
8401     /* e8 */
8402     { Bad_Opcode },
8403     { Bad_Opcode },
8404     { Bad_Opcode },
8405     { Bad_Opcode },
8406     { Bad_Opcode },
8407     { Bad_Opcode },
8408     { Bad_Opcode },
8409     { Bad_Opcode },
8410     /* f0 */
8411     { Bad_Opcode },
8412     { Bad_Opcode },
8413     { Bad_Opcode },
8414     { Bad_Opcode },
8415     { Bad_Opcode },
8416     { Bad_Opcode },
8417     { Bad_Opcode },
8418     { Bad_Opcode },
8419     /* f8 */
8420     { Bad_Opcode },
8421     { Bad_Opcode },
8422     { Bad_Opcode },
8423     { Bad_Opcode },
8424     { Bad_Opcode },
8425     { Bad_Opcode },
8426     { Bad_Opcode },
8427     { Bad_Opcode },
8428   },
8429 };
8430
8431 static const struct dis386 vex_table[][256] = {
8432   /* VEX_0F */
8433   {
8434     /* 00 */
8435     { Bad_Opcode },
8436     { Bad_Opcode },
8437     { Bad_Opcode },
8438     { Bad_Opcode },
8439     { Bad_Opcode },
8440     { Bad_Opcode },
8441     { Bad_Opcode },
8442     { Bad_Opcode },
8443     /* 08 */
8444     { Bad_Opcode },
8445     { Bad_Opcode },
8446     { Bad_Opcode },
8447     { Bad_Opcode },
8448     { Bad_Opcode },
8449     { Bad_Opcode },
8450     { Bad_Opcode },
8451     { Bad_Opcode },
8452     /* 10 */
8453     { PREFIX_TABLE (PREFIX_VEX_0F10) },
8454     { PREFIX_TABLE (PREFIX_VEX_0F11) },
8455     { PREFIX_TABLE (PREFIX_VEX_0F12) },
8456     { MOD_TABLE (MOD_VEX_0F13) },
8457     { VEX_W_TABLE (VEX_W_0F14) },
8458     { VEX_W_TABLE (VEX_W_0F15) },
8459     { PREFIX_TABLE (PREFIX_VEX_0F16) },
8460     { MOD_TABLE (MOD_VEX_0F17) },
8461     /* 18 */
8462     { Bad_Opcode },
8463     { Bad_Opcode },
8464     { Bad_Opcode },
8465     { Bad_Opcode },
8466     { Bad_Opcode },
8467     { Bad_Opcode },
8468     { Bad_Opcode },
8469     { Bad_Opcode },
8470     /* 20 */
8471     { Bad_Opcode },
8472     { Bad_Opcode },
8473     { Bad_Opcode },
8474     { Bad_Opcode },
8475     { Bad_Opcode },
8476     { Bad_Opcode },
8477     { Bad_Opcode },
8478     { Bad_Opcode },
8479     /* 28 */
8480     { VEX_W_TABLE (VEX_W_0F28) },
8481     { VEX_W_TABLE (VEX_W_0F29) },
8482     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8483     { MOD_TABLE (MOD_VEX_0F2B) },
8484     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8485     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8486     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8487     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8488     /* 30 */
8489     { Bad_Opcode },
8490     { Bad_Opcode },
8491     { Bad_Opcode },
8492     { Bad_Opcode },
8493     { Bad_Opcode },
8494     { Bad_Opcode },
8495     { Bad_Opcode },
8496     { Bad_Opcode },
8497     /* 38 */
8498     { Bad_Opcode },
8499     { Bad_Opcode },
8500     { Bad_Opcode },
8501     { Bad_Opcode },
8502     { Bad_Opcode },
8503     { Bad_Opcode },
8504     { Bad_Opcode },
8505     { Bad_Opcode },
8506     /* 40 */
8507     { Bad_Opcode },
8508     { PREFIX_TABLE (PREFIX_VEX_0F41) },
8509     { PREFIX_TABLE (PREFIX_VEX_0F42) },
8510     { Bad_Opcode },
8511     { PREFIX_TABLE (PREFIX_VEX_0F44) },
8512     { PREFIX_TABLE (PREFIX_VEX_0F45) },
8513     { PREFIX_TABLE (PREFIX_VEX_0F46) },
8514     { PREFIX_TABLE (PREFIX_VEX_0F47) },
8515     /* 48 */
8516     { Bad_Opcode },
8517     { Bad_Opcode },
8518     { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8519     { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8520     { Bad_Opcode },
8521     { Bad_Opcode },
8522     { Bad_Opcode },
8523     { Bad_Opcode },
8524     /* 50 */
8525     { MOD_TABLE (MOD_VEX_0F50) },
8526     { PREFIX_TABLE (PREFIX_VEX_0F51) },
8527     { PREFIX_TABLE (PREFIX_VEX_0F52) },
8528     { PREFIX_TABLE (PREFIX_VEX_0F53) },
8529     { "vandpX",         { XM, Vex, EXx }, 0 },
8530     { "vandnpX",        { XM, Vex, EXx }, 0 },
8531     { "vorpX",          { XM, Vex, EXx }, 0 },
8532     { "vxorpX",         { XM, Vex, EXx }, 0 },
8533     /* 58 */
8534     { PREFIX_TABLE (PREFIX_VEX_0F58) },
8535     { PREFIX_TABLE (PREFIX_VEX_0F59) },
8536     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8537     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8538     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8539     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8540     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8541     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8542     /* 60 */
8543     { PREFIX_TABLE (PREFIX_VEX_0F60) },
8544     { PREFIX_TABLE (PREFIX_VEX_0F61) },
8545     { PREFIX_TABLE (PREFIX_VEX_0F62) },
8546     { PREFIX_TABLE (PREFIX_VEX_0F63) },
8547     { PREFIX_TABLE (PREFIX_VEX_0F64) },
8548     { PREFIX_TABLE (PREFIX_VEX_0F65) },
8549     { PREFIX_TABLE (PREFIX_VEX_0F66) },
8550     { PREFIX_TABLE (PREFIX_VEX_0F67) },
8551     /* 68 */
8552     { PREFIX_TABLE (PREFIX_VEX_0F68) },
8553     { PREFIX_TABLE (PREFIX_VEX_0F69) },
8554     { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8555     { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8556     { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8557     { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8558     { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8559     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8560     /* 70 */
8561     { PREFIX_TABLE (PREFIX_VEX_0F70) },
8562     { REG_TABLE (REG_VEX_0F71) },
8563     { REG_TABLE (REG_VEX_0F72) },
8564     { REG_TABLE (REG_VEX_0F73) },
8565     { PREFIX_TABLE (PREFIX_VEX_0F74) },
8566     { PREFIX_TABLE (PREFIX_VEX_0F75) },
8567     { PREFIX_TABLE (PREFIX_VEX_0F76) },
8568     { PREFIX_TABLE (PREFIX_VEX_0F77) },
8569     /* 78 */
8570     { Bad_Opcode },
8571     { Bad_Opcode },
8572     { Bad_Opcode },
8573     { Bad_Opcode },
8574     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8575     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8576     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8577     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8578     /* 80 */
8579     { Bad_Opcode },
8580     { Bad_Opcode },
8581     { Bad_Opcode },
8582     { Bad_Opcode },
8583     { Bad_Opcode },
8584     { Bad_Opcode },
8585     { Bad_Opcode },
8586     { Bad_Opcode },
8587     /* 88 */
8588     { Bad_Opcode },
8589     { Bad_Opcode },
8590     { Bad_Opcode },
8591     { Bad_Opcode },
8592     { Bad_Opcode },
8593     { Bad_Opcode },
8594     { Bad_Opcode },
8595     { Bad_Opcode },
8596     /* 90 */
8597     { PREFIX_TABLE (PREFIX_VEX_0F90) },
8598     { PREFIX_TABLE (PREFIX_VEX_0F91) },
8599     { PREFIX_TABLE (PREFIX_VEX_0F92) },
8600     { PREFIX_TABLE (PREFIX_VEX_0F93) },
8601     { Bad_Opcode },
8602     { Bad_Opcode },
8603     { Bad_Opcode },
8604     { Bad_Opcode },
8605     /* 98 */
8606     { PREFIX_TABLE (PREFIX_VEX_0F98) },
8607     { PREFIX_TABLE (PREFIX_VEX_0F99) },
8608     { Bad_Opcode },
8609     { Bad_Opcode },
8610     { Bad_Opcode },
8611     { Bad_Opcode },
8612     { Bad_Opcode },
8613     { Bad_Opcode },
8614     /* a0 */
8615     { Bad_Opcode },
8616     { Bad_Opcode },
8617     { Bad_Opcode },
8618     { Bad_Opcode },
8619     { Bad_Opcode },
8620     { Bad_Opcode },
8621     { Bad_Opcode },
8622     { Bad_Opcode },
8623     /* a8 */
8624     { Bad_Opcode },
8625     { Bad_Opcode },
8626     { Bad_Opcode },
8627     { Bad_Opcode },
8628     { Bad_Opcode },
8629     { Bad_Opcode },
8630     { REG_TABLE (REG_VEX_0FAE) },
8631     { Bad_Opcode },
8632     /* b0 */
8633     { Bad_Opcode },
8634     { Bad_Opcode },
8635     { Bad_Opcode },
8636     { Bad_Opcode },
8637     { Bad_Opcode },
8638     { Bad_Opcode },
8639     { Bad_Opcode },
8640     { Bad_Opcode },
8641     /* b8 */
8642     { Bad_Opcode },
8643     { Bad_Opcode },
8644     { Bad_Opcode },
8645     { Bad_Opcode },
8646     { Bad_Opcode },
8647     { Bad_Opcode },
8648     { Bad_Opcode },
8649     { Bad_Opcode },
8650     /* c0 */
8651     { Bad_Opcode },
8652     { Bad_Opcode },
8653     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8654     { Bad_Opcode },
8655     { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8656     { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8657     { "vshufpX",        { XM, Vex, EXx, Ib }, 0 },
8658     { Bad_Opcode },
8659     /* c8 */
8660     { Bad_Opcode },
8661     { Bad_Opcode },
8662     { Bad_Opcode },
8663     { Bad_Opcode },
8664     { Bad_Opcode },
8665     { Bad_Opcode },
8666     { Bad_Opcode },
8667     { Bad_Opcode },
8668     /* d0 */
8669     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8670     { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8671     { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8672     { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8673     { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8674     { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8675     { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8676     { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8677     /* d8 */
8678     { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8679     { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8680     { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8681     { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8682     { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8683     { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8684     { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8685     { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8686     /* e0 */
8687     { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8688     { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8689     { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8690     { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8691     { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8692     { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8693     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8694     { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8695     /* e8 */
8696     { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8697     { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8698     { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8699     { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8700     { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8701     { PREFIX_TABLE (PREFIX_VEX_0FED) },
8702     { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8703     { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8704     /* f0 */
8705     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8706     { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8707     { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8708     { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8709     { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8710     { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8711     { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8712     { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8713     /* f8 */
8714     { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8715     { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8716     { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8717     { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8718     { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8719     { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8720     { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8721     { Bad_Opcode },
8722   },
8723   /* VEX_0F38 */
8724   {
8725     /* 00 */
8726     { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8727     { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8728     { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8729     { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8730     { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8731     { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8732     { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8733     { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8734     /* 08 */
8735     { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8736     { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8737     { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8738     { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8739     { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8740     { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8741     { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8742     { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8743     /* 10 */
8744     { Bad_Opcode },
8745     { Bad_Opcode },
8746     { Bad_Opcode },
8747     { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8748     { Bad_Opcode },
8749     { Bad_Opcode },
8750     { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8751     { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8752     /* 18 */
8753     { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8754     { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8755     { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8756     { Bad_Opcode },
8757     { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8758     { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8759     { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8760     { Bad_Opcode },
8761     /* 20 */
8762     { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8763     { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8764     { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8765     { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8766     { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8767     { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8768     { Bad_Opcode },
8769     { Bad_Opcode },
8770     /* 28 */
8771     { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8772     { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8773     { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8774     { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8775     { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8776     { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8777     { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8778     { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8779     /* 30 */
8780     { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8781     { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8782     { PREFIX_TABLE (PREFIX_VEX_0F3832) },
8783     { PREFIX_TABLE (PREFIX_VEX_0F3833) },
8784     { PREFIX_TABLE (PREFIX_VEX_0F3834) },
8785     { PREFIX_TABLE (PREFIX_VEX_0F3835) },
8786     { PREFIX_TABLE (PREFIX_VEX_0F3836) },
8787     { PREFIX_TABLE (PREFIX_VEX_0F3837) },
8788     /* 38 */
8789     { PREFIX_TABLE (PREFIX_VEX_0F3838) },
8790     { PREFIX_TABLE (PREFIX_VEX_0F3839) },
8791     { PREFIX_TABLE (PREFIX_VEX_0F383A) },
8792     { PREFIX_TABLE (PREFIX_VEX_0F383B) },
8793     { PREFIX_TABLE (PREFIX_VEX_0F383C) },
8794     { PREFIX_TABLE (PREFIX_VEX_0F383D) },
8795     { PREFIX_TABLE (PREFIX_VEX_0F383E) },
8796     { PREFIX_TABLE (PREFIX_VEX_0F383F) },
8797     /* 40 */
8798     { PREFIX_TABLE (PREFIX_VEX_0F3840) },
8799     { PREFIX_TABLE (PREFIX_VEX_0F3841) },
8800     { Bad_Opcode },
8801     { Bad_Opcode },
8802     { Bad_Opcode },
8803     { PREFIX_TABLE (PREFIX_VEX_0F3845) },
8804     { PREFIX_TABLE (PREFIX_VEX_0F3846) },
8805     { PREFIX_TABLE (PREFIX_VEX_0F3847) },
8806     /* 48 */
8807     { Bad_Opcode },
8808     { Bad_Opcode },
8809     { Bad_Opcode },
8810     { Bad_Opcode },
8811     { Bad_Opcode },
8812     { Bad_Opcode },
8813     { Bad_Opcode },
8814     { Bad_Opcode },
8815     /* 50 */
8816     { Bad_Opcode },
8817     { Bad_Opcode },
8818     { Bad_Opcode },
8819     { Bad_Opcode },
8820     { Bad_Opcode },
8821     { Bad_Opcode },
8822     { Bad_Opcode },
8823     { Bad_Opcode },
8824     /* 58 */
8825     { PREFIX_TABLE (PREFIX_VEX_0F3858) },
8826     { PREFIX_TABLE (PREFIX_VEX_0F3859) },
8827     { PREFIX_TABLE (PREFIX_VEX_0F385A) },
8828     { Bad_Opcode },
8829     { Bad_Opcode },
8830     { Bad_Opcode },
8831     { Bad_Opcode },
8832     { Bad_Opcode },
8833     /* 60 */
8834     { Bad_Opcode },
8835     { Bad_Opcode },
8836     { Bad_Opcode },
8837     { Bad_Opcode },
8838     { Bad_Opcode },
8839     { Bad_Opcode },
8840     { Bad_Opcode },
8841     { Bad_Opcode },
8842     /* 68 */
8843     { Bad_Opcode },
8844     { Bad_Opcode },
8845     { Bad_Opcode },
8846     { Bad_Opcode },
8847     { Bad_Opcode },
8848     { Bad_Opcode },
8849     { Bad_Opcode },
8850     { Bad_Opcode },
8851     /* 70 */
8852     { Bad_Opcode },
8853     { Bad_Opcode },
8854     { Bad_Opcode },
8855     { Bad_Opcode },
8856     { Bad_Opcode },
8857     { Bad_Opcode },
8858     { Bad_Opcode },
8859     { Bad_Opcode },
8860     /* 78 */
8861     { PREFIX_TABLE (PREFIX_VEX_0F3878) },
8862     { PREFIX_TABLE (PREFIX_VEX_0F3879) },
8863     { Bad_Opcode },
8864     { Bad_Opcode },
8865     { Bad_Opcode },
8866     { Bad_Opcode },
8867     { Bad_Opcode },
8868     { Bad_Opcode },
8869     /* 80 */
8870     { Bad_Opcode },
8871     { Bad_Opcode },
8872     { Bad_Opcode },
8873     { Bad_Opcode },
8874     { Bad_Opcode },
8875     { Bad_Opcode },
8876     { Bad_Opcode },
8877     { Bad_Opcode },
8878     /* 88 */
8879     { Bad_Opcode },
8880     { Bad_Opcode },
8881     { Bad_Opcode },
8882     { Bad_Opcode },
8883     { PREFIX_TABLE (PREFIX_VEX_0F388C) },
8884     { Bad_Opcode },
8885     { PREFIX_TABLE (PREFIX_VEX_0F388E) },
8886     { Bad_Opcode },
8887     /* 90 */
8888     { PREFIX_TABLE (PREFIX_VEX_0F3890) },
8889     { PREFIX_TABLE (PREFIX_VEX_0F3891) },
8890     { PREFIX_TABLE (PREFIX_VEX_0F3892) },
8891     { PREFIX_TABLE (PREFIX_VEX_0F3893) },
8892     { Bad_Opcode },
8893     { Bad_Opcode },
8894     { PREFIX_TABLE (PREFIX_VEX_0F3896) },
8895     { PREFIX_TABLE (PREFIX_VEX_0F3897) },
8896     /* 98 */
8897     { PREFIX_TABLE (PREFIX_VEX_0F3898) },
8898     { PREFIX_TABLE (PREFIX_VEX_0F3899) },
8899     { PREFIX_TABLE (PREFIX_VEX_0F389A) },
8900     { PREFIX_TABLE (PREFIX_VEX_0F389B) },
8901     { PREFIX_TABLE (PREFIX_VEX_0F389C) },
8902     { PREFIX_TABLE (PREFIX_VEX_0F389D) },
8903     { PREFIX_TABLE (PREFIX_VEX_0F389E) },
8904     { PREFIX_TABLE (PREFIX_VEX_0F389F) },
8905     /* a0 */
8906     { Bad_Opcode },
8907     { Bad_Opcode },
8908     { Bad_Opcode },
8909     { Bad_Opcode },
8910     { Bad_Opcode },
8911     { Bad_Opcode },
8912     { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
8913     { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
8914     /* a8 */
8915     { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
8916     { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
8917     { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
8918     { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
8919     { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
8920     { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
8921     { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
8922     { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
8923     /* b0 */
8924     { Bad_Opcode },
8925     { Bad_Opcode },
8926     { Bad_Opcode },
8927     { Bad_Opcode },
8928     { Bad_Opcode },
8929     { Bad_Opcode },
8930     { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
8931     { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
8932     /* b8 */
8933     { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
8934     { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
8935     { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
8936     { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
8937     { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
8938     { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
8939     { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
8940     { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
8941     /* c0 */
8942     { Bad_Opcode },
8943     { Bad_Opcode },
8944     { Bad_Opcode },
8945     { Bad_Opcode },
8946     { Bad_Opcode },
8947     { Bad_Opcode },
8948     { Bad_Opcode },
8949     { Bad_Opcode },
8950     /* c8 */
8951     { Bad_Opcode },
8952     { Bad_Opcode },
8953     { Bad_Opcode },
8954     { Bad_Opcode },
8955     { Bad_Opcode },
8956     { Bad_Opcode },
8957     { Bad_Opcode },
8958     { Bad_Opcode },
8959     /* d0 */
8960     { Bad_Opcode },
8961     { Bad_Opcode },
8962     { Bad_Opcode },
8963     { Bad_Opcode },
8964     { Bad_Opcode },
8965     { Bad_Opcode },
8966     { Bad_Opcode },
8967     { Bad_Opcode },
8968     /* d8 */
8969     { Bad_Opcode },
8970     { Bad_Opcode },
8971     { Bad_Opcode },
8972     { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
8973     { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
8974     { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
8975     { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
8976     { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
8977     /* e0 */
8978     { Bad_Opcode },
8979     { Bad_Opcode },
8980     { Bad_Opcode },
8981     { Bad_Opcode },
8982     { Bad_Opcode },
8983     { Bad_Opcode },
8984     { Bad_Opcode },
8985     { Bad_Opcode },
8986     /* e8 */
8987     { Bad_Opcode },
8988     { Bad_Opcode },
8989     { Bad_Opcode },
8990     { Bad_Opcode },
8991     { Bad_Opcode },
8992     { Bad_Opcode },
8993     { Bad_Opcode },
8994     { Bad_Opcode },
8995     /* f0 */
8996     { Bad_Opcode },
8997     { Bad_Opcode },
8998     { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
8999     { REG_TABLE (REG_VEX_0F38F3) },
9000     { Bad_Opcode },
9001     { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
9002     { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
9003     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
9004     /* f8 */
9005     { Bad_Opcode },
9006     { Bad_Opcode },
9007     { Bad_Opcode },
9008     { Bad_Opcode },
9009     { Bad_Opcode },
9010     { Bad_Opcode },
9011     { Bad_Opcode },
9012     { Bad_Opcode },
9013   },
9014   /* VEX_0F3A */
9015   {
9016     /* 00 */
9017     { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
9018     { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
9019     { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
9020     { Bad_Opcode },
9021     { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
9022     { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
9023     { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
9024     { Bad_Opcode },
9025     /* 08 */
9026     { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
9027     { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
9028     { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
9029     { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
9030     { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
9031     { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
9032     { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
9033     { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
9034     /* 10 */
9035     { Bad_Opcode },
9036     { Bad_Opcode },
9037     { Bad_Opcode },
9038     { Bad_Opcode },
9039     { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
9040     { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
9041     { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
9042     { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
9043     /* 18 */
9044     { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
9045     { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
9046     { Bad_Opcode },
9047     { Bad_Opcode },
9048     { Bad_Opcode },
9049     { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
9050     { Bad_Opcode },
9051     { Bad_Opcode },
9052     /* 20 */
9053     { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
9054     { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
9055     { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
9056     { Bad_Opcode },
9057     { Bad_Opcode },
9058     { Bad_Opcode },
9059     { Bad_Opcode },
9060     { Bad_Opcode },
9061     /* 28 */
9062     { Bad_Opcode },
9063     { Bad_Opcode },
9064     { Bad_Opcode },
9065     { Bad_Opcode },
9066     { Bad_Opcode },
9067     { Bad_Opcode },
9068     { Bad_Opcode },
9069     { Bad_Opcode },
9070     /* 30 */
9071     { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
9072     { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
9073     { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
9074     { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
9075     { Bad_Opcode },
9076     { Bad_Opcode },
9077     { Bad_Opcode },
9078     { Bad_Opcode },
9079     /* 38 */
9080     { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
9081     { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
9082     { Bad_Opcode },
9083     { Bad_Opcode },
9084     { Bad_Opcode },
9085     { Bad_Opcode },
9086     { Bad_Opcode },
9087     { Bad_Opcode },
9088     /* 40 */
9089     { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
9090     { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
9091     { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
9092     { Bad_Opcode },
9093     { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
9094     { Bad_Opcode },
9095     { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
9096     { Bad_Opcode },
9097     /* 48 */
9098     { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
9099     { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
9100     { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
9101     { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
9102     { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
9103     { Bad_Opcode },
9104     { Bad_Opcode },
9105     { Bad_Opcode },
9106     /* 50 */
9107     { Bad_Opcode },
9108     { Bad_Opcode },
9109     { Bad_Opcode },
9110     { Bad_Opcode },
9111     { Bad_Opcode },
9112     { Bad_Opcode },
9113     { Bad_Opcode },
9114     { Bad_Opcode },
9115     /* 58 */
9116     { Bad_Opcode },
9117     { Bad_Opcode },
9118     { Bad_Opcode },
9119     { Bad_Opcode },
9120     { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9121     { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9122     { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9123     { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9124     /* 60 */
9125     { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9126     { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9127     { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9128     { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9129     { Bad_Opcode },
9130     { Bad_Opcode },
9131     { Bad_Opcode },
9132     { Bad_Opcode },
9133     /* 68 */
9134     { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9135     { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9136     { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9137     { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9138     { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9139     { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9140     { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9141     { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9142     /* 70 */
9143     { Bad_Opcode },
9144     { Bad_Opcode },
9145     { Bad_Opcode },
9146     { Bad_Opcode },
9147     { Bad_Opcode },
9148     { Bad_Opcode },
9149     { Bad_Opcode },
9150     { Bad_Opcode },
9151     /* 78 */
9152     { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9153     { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9154     { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9155     { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9156     { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9157     { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9158     { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9159     { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9160     /* 80 */
9161     { Bad_Opcode },
9162     { Bad_Opcode },
9163     { Bad_Opcode },
9164     { Bad_Opcode },
9165     { Bad_Opcode },
9166     { Bad_Opcode },
9167     { Bad_Opcode },
9168     { Bad_Opcode },
9169     /* 88 */
9170     { Bad_Opcode },
9171     { Bad_Opcode },
9172     { Bad_Opcode },
9173     { Bad_Opcode },
9174     { Bad_Opcode },
9175     { Bad_Opcode },
9176     { Bad_Opcode },
9177     { Bad_Opcode },
9178     /* 90 */
9179     { Bad_Opcode },
9180     { Bad_Opcode },
9181     { Bad_Opcode },
9182     { Bad_Opcode },
9183     { Bad_Opcode },
9184     { Bad_Opcode },
9185     { Bad_Opcode },
9186     { Bad_Opcode },
9187     /* 98 */
9188     { Bad_Opcode },
9189     { Bad_Opcode },
9190     { Bad_Opcode },
9191     { Bad_Opcode },
9192     { Bad_Opcode },
9193     { Bad_Opcode },
9194     { Bad_Opcode },
9195     { Bad_Opcode },
9196     /* a0 */
9197     { Bad_Opcode },
9198     { Bad_Opcode },
9199     { Bad_Opcode },
9200     { Bad_Opcode },
9201     { Bad_Opcode },
9202     { Bad_Opcode },
9203     { Bad_Opcode },
9204     { Bad_Opcode },
9205     /* a8 */
9206     { Bad_Opcode },
9207     { Bad_Opcode },
9208     { Bad_Opcode },
9209     { Bad_Opcode },
9210     { Bad_Opcode },
9211     { Bad_Opcode },
9212     { Bad_Opcode },
9213     { Bad_Opcode },
9214     /* b0 */
9215     { Bad_Opcode },
9216     { Bad_Opcode },
9217     { Bad_Opcode },
9218     { Bad_Opcode },
9219     { Bad_Opcode },
9220     { Bad_Opcode },
9221     { Bad_Opcode },
9222     { Bad_Opcode },
9223     /* b8 */
9224     { Bad_Opcode },
9225     { Bad_Opcode },
9226     { Bad_Opcode },
9227     { Bad_Opcode },
9228     { Bad_Opcode },
9229     { Bad_Opcode },
9230     { Bad_Opcode },
9231     { Bad_Opcode },
9232     /* c0 */
9233     { Bad_Opcode },
9234     { Bad_Opcode },
9235     { Bad_Opcode },
9236     { Bad_Opcode },
9237     { Bad_Opcode },
9238     { Bad_Opcode },
9239     { Bad_Opcode },
9240     { Bad_Opcode },
9241     /* c8 */
9242     { Bad_Opcode },
9243     { Bad_Opcode },
9244     { Bad_Opcode },
9245     { Bad_Opcode },
9246     { Bad_Opcode },
9247     { Bad_Opcode },
9248     { Bad_Opcode },
9249     { Bad_Opcode },
9250     /* d0 */
9251     { Bad_Opcode },
9252     { Bad_Opcode },
9253     { Bad_Opcode },
9254     { Bad_Opcode },
9255     { Bad_Opcode },
9256     { Bad_Opcode },
9257     { Bad_Opcode },
9258     { Bad_Opcode },
9259     /* d8 */
9260     { Bad_Opcode },
9261     { Bad_Opcode },
9262     { Bad_Opcode },
9263     { Bad_Opcode },
9264     { Bad_Opcode },
9265     { Bad_Opcode },
9266     { Bad_Opcode },
9267     { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9268     /* e0 */
9269     { Bad_Opcode },
9270     { Bad_Opcode },
9271     { Bad_Opcode },
9272     { Bad_Opcode },
9273     { Bad_Opcode },
9274     { Bad_Opcode },
9275     { Bad_Opcode },
9276     { Bad_Opcode },
9277     /* e8 */
9278     { Bad_Opcode },
9279     { Bad_Opcode },
9280     { Bad_Opcode },
9281     { Bad_Opcode },
9282     { Bad_Opcode },
9283     { Bad_Opcode },
9284     { Bad_Opcode },
9285     { Bad_Opcode },
9286     /* f0 */
9287     { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9288     { Bad_Opcode },
9289     { Bad_Opcode },
9290     { Bad_Opcode },
9291     { Bad_Opcode },
9292     { Bad_Opcode },
9293     { Bad_Opcode },
9294     { Bad_Opcode },
9295     /* f8 */
9296     { Bad_Opcode },
9297     { Bad_Opcode },
9298     { Bad_Opcode },
9299     { Bad_Opcode },
9300     { Bad_Opcode },
9301     { Bad_Opcode },
9302     { Bad_Opcode },
9303     { Bad_Opcode },
9304   },
9305 };
9306
9307 #define NEED_OPCODE_TABLE
9308 #include "i386-dis-evex.h"
9309 #undef NEED_OPCODE_TABLE
9310 static const struct dis386 vex_len_table[][2] = {
9311   /* VEX_LEN_0F10_P_1 */
9312   {
9313     { VEX_W_TABLE (VEX_W_0F10_P_1) },
9314     { VEX_W_TABLE (VEX_W_0F10_P_1) },
9315   },
9316
9317   /* VEX_LEN_0F10_P_3 */
9318   {
9319     { VEX_W_TABLE (VEX_W_0F10_P_3) },
9320     { VEX_W_TABLE (VEX_W_0F10_P_3) },
9321   },
9322
9323   /* VEX_LEN_0F11_P_1 */
9324   {
9325     { VEX_W_TABLE (VEX_W_0F11_P_1) },
9326     { VEX_W_TABLE (VEX_W_0F11_P_1) },
9327   },
9328
9329   /* VEX_LEN_0F11_P_3 */
9330   {
9331     { VEX_W_TABLE (VEX_W_0F11_P_3) },
9332     { VEX_W_TABLE (VEX_W_0F11_P_3) },
9333   },
9334
9335   /* VEX_LEN_0F12_P_0_M_0 */
9336   {
9337     { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) },
9338   },
9339
9340   /* VEX_LEN_0F12_P_0_M_1 */
9341   {
9342     { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) },
9343   },
9344
9345   /* VEX_LEN_0F12_P_2 */
9346   {
9347     { VEX_W_TABLE (VEX_W_0F12_P_2) },
9348   },
9349
9350   /* VEX_LEN_0F13_M_0 */
9351   {
9352     { VEX_W_TABLE (VEX_W_0F13_M_0) },
9353   },
9354
9355   /* VEX_LEN_0F16_P_0_M_0 */
9356   {
9357     { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) },
9358   },
9359
9360   /* VEX_LEN_0F16_P_0_M_1 */
9361   {
9362     { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) },
9363   },
9364
9365   /* VEX_LEN_0F16_P_2 */
9366   {
9367     { VEX_W_TABLE (VEX_W_0F16_P_2) },
9368   },
9369
9370   /* VEX_LEN_0F17_M_0 */
9371   {
9372     { VEX_W_TABLE (VEX_W_0F17_M_0) },
9373   },
9374
9375   /* VEX_LEN_0F2A_P_1 */
9376   {
9377     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9378     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9379   },
9380
9381   /* VEX_LEN_0F2A_P_3 */
9382   {
9383     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9384     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9385   },
9386
9387   /* VEX_LEN_0F2C_P_1 */
9388   {
9389     { "vcvttss2siY",    { Gv, EXdScalar }, 0 },
9390     { "vcvttss2siY",    { Gv, EXdScalar }, 0 },
9391   },
9392
9393   /* VEX_LEN_0F2C_P_3 */
9394   {
9395     { "vcvttsd2siY",    { Gv, EXqScalar }, 0 },
9396     { "vcvttsd2siY",    { Gv, EXqScalar }, 0 },
9397   },
9398
9399   /* VEX_LEN_0F2D_P_1 */
9400   {
9401     { "vcvtss2siY",     { Gv, EXdScalar }, 0 },
9402     { "vcvtss2siY",     { Gv, EXdScalar }, 0 },
9403   },
9404
9405   /* VEX_LEN_0F2D_P_3 */
9406   {
9407     { "vcvtsd2siY",     { Gv, EXqScalar }, 0 },
9408     { "vcvtsd2siY",     { Gv, EXqScalar }, 0 },
9409   },
9410
9411   /* VEX_LEN_0F2E_P_0 */
9412   {
9413     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9414     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9415   },
9416
9417   /* VEX_LEN_0F2E_P_2 */
9418   {
9419     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9420     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9421   },
9422
9423   /* VEX_LEN_0F2F_P_0 */
9424   {
9425     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9426     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9427   },
9428
9429   /* VEX_LEN_0F2F_P_2 */
9430   {
9431     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9432     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9433   },
9434
9435   /* VEX_LEN_0F41_P_0 */
9436   {
9437     { Bad_Opcode },
9438     { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9439   },
9440   /* VEX_LEN_0F41_P_2 */
9441   {
9442     { Bad_Opcode },
9443     { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9444   },
9445   /* VEX_LEN_0F42_P_0 */
9446   {
9447     { Bad_Opcode },
9448     { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9449   },
9450   /* VEX_LEN_0F42_P_2 */
9451   {
9452     { Bad_Opcode },
9453     { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9454   },
9455   /* VEX_LEN_0F44_P_0 */
9456   {
9457     { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9458   },
9459   /* VEX_LEN_0F44_P_2 */
9460   {
9461     { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9462   },
9463   /* VEX_LEN_0F45_P_0 */
9464   {
9465     { Bad_Opcode },
9466     { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9467   },
9468   /* VEX_LEN_0F45_P_2 */
9469   {
9470     { Bad_Opcode },
9471     { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9472   },
9473   /* VEX_LEN_0F46_P_0 */
9474   {
9475     { Bad_Opcode },
9476     { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9477   },
9478   /* VEX_LEN_0F46_P_2 */
9479   {
9480     { Bad_Opcode },
9481     { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9482   },
9483   /* VEX_LEN_0F47_P_0 */
9484   {
9485     { Bad_Opcode },
9486     { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9487   },
9488   /* VEX_LEN_0F47_P_2 */
9489   {
9490     { Bad_Opcode },
9491     { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9492   },
9493   /* VEX_LEN_0F4A_P_0 */
9494   {
9495     { Bad_Opcode },
9496     { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9497   },
9498   /* VEX_LEN_0F4A_P_2 */
9499   {
9500     { Bad_Opcode },
9501     { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9502   },
9503   /* VEX_LEN_0F4B_P_0 */
9504   {
9505     { Bad_Opcode },
9506     { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9507   },
9508   /* VEX_LEN_0F4B_P_2 */
9509   {
9510     { Bad_Opcode },
9511     { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9512   },
9513
9514   /* VEX_LEN_0F51_P_1 */
9515   {
9516     { VEX_W_TABLE (VEX_W_0F51_P_1) },
9517     { VEX_W_TABLE (VEX_W_0F51_P_1) },
9518   },
9519
9520   /* VEX_LEN_0F51_P_3 */
9521   {
9522     { VEX_W_TABLE (VEX_W_0F51_P_3) },
9523     { VEX_W_TABLE (VEX_W_0F51_P_3) },
9524   },
9525
9526   /* VEX_LEN_0F52_P_1 */
9527   {
9528     { VEX_W_TABLE (VEX_W_0F52_P_1) },
9529     { VEX_W_TABLE (VEX_W_0F52_P_1) },
9530   },
9531
9532   /* VEX_LEN_0F53_P_1 */
9533   {
9534     { VEX_W_TABLE (VEX_W_0F53_P_1) },
9535     { VEX_W_TABLE (VEX_W_0F53_P_1) },
9536   },
9537
9538   /* VEX_LEN_0F58_P_1 */
9539   {
9540     { VEX_W_TABLE (VEX_W_0F58_P_1) },
9541     { VEX_W_TABLE (VEX_W_0F58_P_1) },
9542   },
9543
9544   /* VEX_LEN_0F58_P_3 */
9545   {
9546     { VEX_W_TABLE (VEX_W_0F58_P_3) },
9547     { VEX_W_TABLE (VEX_W_0F58_P_3) },
9548   },
9549
9550   /* VEX_LEN_0F59_P_1 */
9551   {
9552     { VEX_W_TABLE (VEX_W_0F59_P_1) },
9553     { VEX_W_TABLE (VEX_W_0F59_P_1) },
9554   },
9555
9556   /* VEX_LEN_0F59_P_3 */
9557   {
9558     { VEX_W_TABLE (VEX_W_0F59_P_3) },
9559     { VEX_W_TABLE (VEX_W_0F59_P_3) },
9560   },
9561
9562   /* VEX_LEN_0F5A_P_1 */
9563   {
9564     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9565     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9566   },
9567
9568   /* VEX_LEN_0F5A_P_3 */
9569   {
9570     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9571     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9572   },
9573
9574   /* VEX_LEN_0F5C_P_1 */
9575   {
9576     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9577     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9578   },
9579
9580   /* VEX_LEN_0F5C_P_3 */
9581   {
9582     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9583     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9584   },
9585
9586   /* VEX_LEN_0F5D_P_1 */
9587   {
9588     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9589     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9590   },
9591
9592   /* VEX_LEN_0F5D_P_3 */
9593   {
9594     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9595     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9596   },
9597
9598   /* VEX_LEN_0F5E_P_1 */
9599   {
9600     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9601     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9602   },
9603
9604   /* VEX_LEN_0F5E_P_3 */
9605   {
9606     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9607     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9608   },
9609
9610   /* VEX_LEN_0F5F_P_1 */
9611   {
9612     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9613     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9614   },
9615
9616   /* VEX_LEN_0F5F_P_3 */
9617   {
9618     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9619     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9620   },
9621
9622   /* VEX_LEN_0F6E_P_2 */
9623   {
9624     { "vmovK",          { XMScalar, Edq }, 0 },
9625     { "vmovK",          { XMScalar, Edq }, 0 },
9626   },
9627
9628   /* VEX_LEN_0F7E_P_1 */
9629   {
9630     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9631     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9632   },
9633
9634   /* VEX_LEN_0F7E_P_2 */
9635   {
9636     { "vmovK",          { Edq, XMScalar }, 0 },
9637     { "vmovK",          { Edq, XMScalar }, 0 },
9638   },
9639
9640   /* VEX_LEN_0F90_P_0 */
9641   {
9642     { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9643   },
9644
9645   /* VEX_LEN_0F90_P_2 */
9646   {
9647     { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9648   },
9649
9650   /* VEX_LEN_0F91_P_0 */
9651   {
9652     { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9653   },
9654
9655   /* VEX_LEN_0F91_P_2 */
9656   {
9657     { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
9658   },
9659
9660   /* VEX_LEN_0F92_P_0 */
9661   {
9662     { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9663   },
9664
9665   /* VEX_LEN_0F92_P_2 */
9666   {
9667     { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
9668   },
9669
9670   /* VEX_LEN_0F92_P_3 */
9671   {
9672     { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0) },
9673   },
9674
9675   /* VEX_LEN_0F93_P_0 */
9676   {
9677     { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9678   },
9679
9680   /* VEX_LEN_0F93_P_2 */
9681   {
9682     { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
9683   },
9684
9685   /* VEX_LEN_0F93_P_3 */
9686   {
9687     { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0) },
9688   },
9689
9690   /* VEX_LEN_0F98_P_0 */
9691   {
9692     { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9693   },
9694
9695   /* VEX_LEN_0F98_P_2 */
9696   {
9697     { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
9698   },
9699
9700   /* VEX_LEN_0F99_P_0 */
9701   {
9702     { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
9703   },
9704
9705   /* VEX_LEN_0F99_P_2 */
9706   {
9707     { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
9708   },
9709
9710   /* VEX_LEN_0FAE_R_2_M_0 */
9711   {
9712     { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) },
9713   },
9714
9715   /* VEX_LEN_0FAE_R_3_M_0 */
9716   {
9717     { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) },
9718   },
9719
9720   /* VEX_LEN_0FC2_P_1 */
9721   {
9722     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9723     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9724   },
9725
9726   /* VEX_LEN_0FC2_P_3 */
9727   {
9728     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9729     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9730   },
9731
9732   /* VEX_LEN_0FC4_P_2 */
9733   {
9734     { VEX_W_TABLE (VEX_W_0FC4_P_2) },
9735   },
9736
9737   /* VEX_LEN_0FC5_P_2 */
9738   {
9739     { VEX_W_TABLE (VEX_W_0FC5_P_2) },
9740   },
9741
9742   /* VEX_LEN_0FD6_P_2 */
9743   {
9744     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9745     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9746   },
9747
9748   /* VEX_LEN_0FF7_P_2 */
9749   {
9750     { VEX_W_TABLE (VEX_W_0FF7_P_2) },
9751   },
9752
9753   /* VEX_LEN_0F3816_P_2 */
9754   {
9755     { Bad_Opcode },
9756     { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9757   },
9758
9759   /* VEX_LEN_0F3819_P_2 */
9760   {
9761     { Bad_Opcode },
9762     { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9763   },
9764
9765   /* VEX_LEN_0F381A_P_2_M_0 */
9766   {
9767     { Bad_Opcode },
9768     { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9769   },
9770
9771   /* VEX_LEN_0F3836_P_2 */
9772   {
9773     { Bad_Opcode },
9774     { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9775   },
9776
9777   /* VEX_LEN_0F3841_P_2 */
9778   {
9779     { VEX_W_TABLE (VEX_W_0F3841_P_2) },
9780   },
9781
9782   /* VEX_LEN_0F385A_P_2_M_0 */
9783   {
9784     { Bad_Opcode },
9785     { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
9786   },
9787
9788   /* VEX_LEN_0F38DB_P_2 */
9789   {
9790     { VEX_W_TABLE (VEX_W_0F38DB_P_2) },
9791   },
9792
9793   /* VEX_LEN_0F38DC_P_2 */
9794   {
9795     { VEX_W_TABLE (VEX_W_0F38DC_P_2) },
9796   },
9797
9798   /* VEX_LEN_0F38DD_P_2 */
9799   {
9800     { VEX_W_TABLE (VEX_W_0F38DD_P_2) },
9801   },
9802
9803   /* VEX_LEN_0F38DE_P_2 */
9804   {
9805     { VEX_W_TABLE (VEX_W_0F38DE_P_2) },
9806   },
9807
9808   /* VEX_LEN_0F38DF_P_2 */
9809   {
9810     { VEX_W_TABLE (VEX_W_0F38DF_P_2) },
9811   },
9812
9813   /* VEX_LEN_0F38F2_P_0 */
9814   {
9815     { "andnS",          { Gdq, VexGdq, Edq }, 0 },
9816   },
9817
9818   /* VEX_LEN_0F38F3_R_1_P_0 */
9819   {
9820     { "blsrS",          { VexGdq, Edq }, 0 },
9821   },
9822
9823   /* VEX_LEN_0F38F3_R_2_P_0 */
9824   {
9825     { "blsmskS",        { VexGdq, Edq }, 0 },
9826   },
9827
9828   /* VEX_LEN_0F38F3_R_3_P_0 */
9829   {
9830     { "blsiS",          { VexGdq, Edq }, 0 },
9831   },
9832
9833   /* VEX_LEN_0F38F5_P_0 */
9834   {
9835     { "bzhiS",          { Gdq, Edq, VexGdq }, 0 },
9836   },
9837
9838   /* VEX_LEN_0F38F5_P_1 */
9839   {
9840     { "pextS",          { Gdq, VexGdq, Edq }, 0 },
9841   },
9842
9843   /* VEX_LEN_0F38F5_P_3 */
9844   {
9845     { "pdepS",          { Gdq, VexGdq, Edq }, 0 },
9846   },
9847
9848   /* VEX_LEN_0F38F6_P_3 */
9849   {
9850     { "mulxS",          { Gdq, VexGdq, Edq }, 0 },
9851   },
9852
9853   /* VEX_LEN_0F38F7_P_0 */
9854   {
9855     { "bextrS",         { Gdq, Edq, VexGdq }, 0 },
9856   },
9857
9858   /* VEX_LEN_0F38F7_P_1 */
9859   {
9860     { "sarxS",          { Gdq, Edq, VexGdq }, 0 },
9861   },
9862
9863   /* VEX_LEN_0F38F7_P_2 */
9864   {
9865     { "shlxS",          { Gdq, Edq, VexGdq }, 0 },
9866   },
9867
9868   /* VEX_LEN_0F38F7_P_3 */
9869   {
9870     { "shrxS",          { Gdq, Edq, VexGdq }, 0 },
9871   },
9872
9873   /* VEX_LEN_0F3A00_P_2 */
9874   {
9875     { Bad_Opcode },
9876     { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
9877   },
9878
9879   /* VEX_LEN_0F3A01_P_2 */
9880   {
9881     { Bad_Opcode },
9882     { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
9883   },
9884
9885   /* VEX_LEN_0F3A06_P_2 */
9886   {
9887     { Bad_Opcode },
9888     { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
9889   },
9890
9891   /* VEX_LEN_0F3A0A_P_2 */
9892   {
9893     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
9894     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
9895   },
9896
9897   /* VEX_LEN_0F3A0B_P_2 */
9898   {
9899     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
9900     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
9901   },
9902
9903   /* VEX_LEN_0F3A14_P_2 */
9904   {
9905     { VEX_W_TABLE (VEX_W_0F3A14_P_2) },
9906   },
9907
9908   /* VEX_LEN_0F3A15_P_2 */
9909   {
9910     { VEX_W_TABLE (VEX_W_0F3A15_P_2) },
9911   },
9912
9913   /* VEX_LEN_0F3A16_P_2  */
9914   {
9915     { "vpextrK",        { Edq, XM, Ib }, 0 },
9916   },
9917
9918   /* VEX_LEN_0F3A17_P_2 */
9919   {
9920     { "vextractps",     { Edqd, XM, Ib }, 0 },
9921   },
9922
9923   /* VEX_LEN_0F3A18_P_2 */
9924   {
9925     { Bad_Opcode },
9926     { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
9927   },
9928
9929   /* VEX_LEN_0F3A19_P_2 */
9930   {
9931     { Bad_Opcode },
9932     { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
9933   },
9934
9935   /* VEX_LEN_0F3A20_P_2 */
9936   {
9937     { VEX_W_TABLE (VEX_W_0F3A20_P_2) },
9938   },
9939
9940   /* VEX_LEN_0F3A21_P_2 */
9941   {
9942     { VEX_W_TABLE (VEX_W_0F3A21_P_2) },
9943   },
9944
9945   /* VEX_LEN_0F3A22_P_2 */
9946   {
9947     { "vpinsrK",        { XM, Vex128, Edq, Ib }, 0 },
9948   },
9949
9950   /* VEX_LEN_0F3A30_P_2 */
9951   {
9952     { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
9953   },
9954
9955   /* VEX_LEN_0F3A31_P_2 */
9956   {
9957     { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
9958   },
9959
9960   /* VEX_LEN_0F3A32_P_2 */
9961   {
9962     { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
9963   },
9964
9965   /* VEX_LEN_0F3A33_P_2 */
9966   {
9967     { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
9968   },
9969
9970   /* VEX_LEN_0F3A38_P_2 */
9971   {
9972     { Bad_Opcode },
9973     { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
9974   },
9975
9976   /* VEX_LEN_0F3A39_P_2 */
9977   {
9978     { Bad_Opcode },
9979     { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
9980   },
9981
9982   /* VEX_LEN_0F3A41_P_2 */
9983   {
9984     { VEX_W_TABLE (VEX_W_0F3A41_P_2) },
9985   },
9986
9987   /* VEX_LEN_0F3A44_P_2 */
9988   {
9989     { VEX_W_TABLE (VEX_W_0F3A44_P_2) },
9990   },
9991
9992   /* VEX_LEN_0F3A46_P_2 */
9993   {
9994     { Bad_Opcode },
9995     { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
9996   },
9997
9998   /* VEX_LEN_0F3A60_P_2 */
9999   {
10000     { "vpcmpestrm",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
10001   },
10002
10003   /* VEX_LEN_0F3A61_P_2 */
10004   {
10005     { "vpcmpestri",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
10006   },
10007
10008   /* VEX_LEN_0F3A62_P_2 */
10009   {
10010     { VEX_W_TABLE (VEX_W_0F3A62_P_2) },
10011   },
10012
10013   /* VEX_LEN_0F3A63_P_2 */
10014   {
10015     { VEX_W_TABLE (VEX_W_0F3A63_P_2) },
10016   },
10017
10018   /* VEX_LEN_0F3A6A_P_2 */
10019   {
10020     { "vfmaddss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10021   },
10022
10023   /* VEX_LEN_0F3A6B_P_2 */
10024   {
10025     { "vfmaddsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10026   },
10027
10028   /* VEX_LEN_0F3A6E_P_2 */
10029   {
10030     { "vfmsubss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10031   },
10032
10033   /* VEX_LEN_0F3A6F_P_2 */
10034   {
10035     { "vfmsubsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10036   },
10037
10038   /* VEX_LEN_0F3A7A_P_2 */
10039   {
10040     { "vfnmaddss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10041   },
10042
10043   /* VEX_LEN_0F3A7B_P_2 */
10044   {
10045     { "vfnmaddsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10046   },
10047
10048   /* VEX_LEN_0F3A7E_P_2 */
10049   {
10050     { "vfnmsubss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10051   },
10052
10053   /* VEX_LEN_0F3A7F_P_2 */
10054   {
10055     { "vfnmsubsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10056   },
10057
10058   /* VEX_LEN_0F3ADF_P_2 */
10059   {
10060     { VEX_W_TABLE (VEX_W_0F3ADF_P_2) },
10061   },
10062
10063   /* VEX_LEN_0F3AF0_P_3 */
10064   {
10065     { "rorxS",          { Gdq, Edq, Ib }, 0 },
10066   },
10067
10068   /* VEX_LEN_0FXOP_08_CC */
10069   {
10070      { "vpcomb",        { XM, Vex128, EXx, Ib }, 0 },
10071   },
10072
10073   /* VEX_LEN_0FXOP_08_CD */
10074   {
10075      { "vpcomw",        { XM, Vex128, EXx, Ib }, 0 },
10076   },
10077
10078   /* VEX_LEN_0FXOP_08_CE */
10079   {
10080      { "vpcomd",        { XM, Vex128, EXx, Ib }, 0 },
10081   },
10082
10083   /* VEX_LEN_0FXOP_08_CF */
10084   {
10085      { "vpcomq",        { XM, Vex128, EXx, Ib }, 0 },
10086   },
10087
10088   /* VEX_LEN_0FXOP_08_EC */
10089   {
10090      { "vpcomub",       { XM, Vex128, EXx, Ib }, 0 },
10091   },
10092
10093   /* VEX_LEN_0FXOP_08_ED */
10094   {
10095      { "vpcomuw",       { XM, Vex128, EXx, Ib }, 0 },
10096   },
10097
10098   /* VEX_LEN_0FXOP_08_EE */
10099   {
10100      { "vpcomud",       { XM, Vex128, EXx, Ib }, 0 },
10101   },
10102
10103   /* VEX_LEN_0FXOP_08_EF */
10104   {
10105      { "vpcomuq",       { XM, Vex128, EXx, Ib }, 0 },
10106   },
10107
10108   /* VEX_LEN_0FXOP_09_80 */
10109   {
10110     { "vfrczps",        { XM, EXxmm }, 0 },
10111     { "vfrczps",        { XM, EXymmq }, 0 },
10112   },
10113
10114   /* VEX_LEN_0FXOP_09_81 */
10115   {
10116     { "vfrczpd",        { XM, EXxmm }, 0 },
10117     { "vfrczpd",        { XM, EXymmq }, 0 },
10118   },
10119 };
10120
10121 static const struct dis386 vex_w_table[][2] = {
10122   {
10123     /* VEX_W_0F10_P_0 */
10124     { "vmovups",        { XM, EXx }, 0 },
10125   },
10126   {
10127     /* VEX_W_0F10_P_1 */
10128     { "vmovss",         { XMVexScalar, VexScalar, EXdScalar }, 0 },
10129   },
10130   {
10131     /* VEX_W_0F10_P_2 */
10132     { "vmovupd",        { XM, EXx }, 0 },
10133   },
10134   {
10135     /* VEX_W_0F10_P_3 */
10136     { "vmovsd",         { XMVexScalar, VexScalar, EXqScalar }, 0 },
10137   },
10138   {
10139     /* VEX_W_0F11_P_0 */
10140     { "vmovups",        { EXxS, XM }, 0 },
10141   },
10142   {
10143     /* VEX_W_0F11_P_1 */
10144     { "vmovss",         { EXdVexScalarS, VexScalar, XMScalar }, 0 },
10145   },
10146   {
10147     /* VEX_W_0F11_P_2 */
10148     { "vmovupd",        { EXxS, XM }, 0 },
10149   },
10150   {
10151     /* VEX_W_0F11_P_3 */
10152     { "vmovsd",         { EXqVexScalarS, VexScalar, XMScalar }, 0 },
10153   },
10154   {
10155     /* VEX_W_0F12_P_0_M_0 */
10156     { "vmovlps",        { XM, Vex128, EXq }, 0 },
10157   },
10158   {
10159     /* VEX_W_0F12_P_0_M_1 */
10160     { "vmovhlps",       { XM, Vex128, EXq }, 0 },
10161   },
10162   {
10163     /* VEX_W_0F12_P_1 */
10164     { "vmovsldup",      { XM, EXx }, 0 },
10165   },
10166   {
10167     /* VEX_W_0F12_P_2 */
10168     { "vmovlpd",        { XM, Vex128, EXq }, 0 },
10169   },
10170   {
10171     /* VEX_W_0F12_P_3 */
10172     { "vmovddup",       { XM, EXymmq }, 0 },
10173   },
10174   {
10175     /* VEX_W_0F13_M_0 */
10176     { "vmovlpX",        { EXq, XM }, 0 },
10177   },
10178   {
10179     /* VEX_W_0F14 */
10180     { "vunpcklpX",      { XM, Vex, EXx }, 0 },
10181   },
10182   {
10183     /* VEX_W_0F15 */
10184     { "vunpckhpX",      { XM, Vex, EXx }, 0 },
10185   },
10186   {
10187     /* VEX_W_0F16_P_0_M_0 */
10188     { "vmovhps",        { XM, Vex128, EXq }, 0 },
10189   },
10190   {
10191     /* VEX_W_0F16_P_0_M_1 */
10192     { "vmovlhps",       { XM, Vex128, EXq }, 0 },
10193   },
10194   {
10195     /* VEX_W_0F16_P_1 */
10196     { "vmovshdup",      { XM, EXx }, 0 },
10197   },
10198   {
10199     /* VEX_W_0F16_P_2 */
10200     { "vmovhpd",        { XM, Vex128, EXq }, 0 },
10201   },
10202   {
10203     /* VEX_W_0F17_M_0 */
10204     { "vmovhpX",        { EXq, XM }, 0 },
10205   },
10206   {
10207     /* VEX_W_0F28 */
10208     { "vmovapX",        { XM, EXx }, 0 },
10209   },
10210   {
10211     /* VEX_W_0F29 */
10212     { "vmovapX",        { EXxS, XM }, 0 },
10213   },
10214   {
10215     /* VEX_W_0F2B_M_0 */
10216     { "vmovntpX",       { Mx, XM }, 0 },
10217   },
10218   {
10219     /* VEX_W_0F2E_P_0 */
10220     { "vucomiss",       { XMScalar, EXdScalar }, 0 },
10221   },
10222   {
10223     /* VEX_W_0F2E_P_2 */
10224     { "vucomisd",       { XMScalar, EXqScalar }, 0 },
10225   },
10226   {
10227     /* VEX_W_0F2F_P_0 */
10228     { "vcomiss",        { XMScalar, EXdScalar }, 0 },
10229   },
10230   {
10231     /* VEX_W_0F2F_P_2 */
10232     { "vcomisd",        { XMScalar, EXqScalar }, 0 },
10233   },
10234   {
10235     /* VEX_W_0F41_P_0_LEN_1 */
10236     { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
10237     { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) },
10238   },
10239   {
10240     /* VEX_W_0F41_P_2_LEN_1 */
10241     { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) },
10242     { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) }
10243   },
10244   {
10245     /* VEX_W_0F42_P_0_LEN_1 */
10246     { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) },
10247     { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) },
10248   },
10249   {
10250     /* VEX_W_0F42_P_2_LEN_1 */
10251     { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) },
10252     { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) },
10253   },
10254   {
10255     /* VEX_W_0F44_P_0_LEN_0 */
10256     { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) },
10257     { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) },
10258   },
10259   {
10260     /* VEX_W_0F44_P_2_LEN_0 */
10261     { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) },
10262     { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) },
10263   },
10264   {
10265     /* VEX_W_0F45_P_0_LEN_1 */
10266     { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) },
10267     { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) },
10268   },
10269   {
10270     /* VEX_W_0F45_P_2_LEN_1 */
10271     { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) },
10272     { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) },
10273   },
10274   {
10275     /* VEX_W_0F46_P_0_LEN_1 */
10276     { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) },
10277     { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) },
10278   },
10279   {
10280     /* VEX_W_0F46_P_2_LEN_1 */
10281     { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) },
10282     { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) },
10283   },
10284   {
10285     /* VEX_W_0F47_P_0_LEN_1 */
10286     { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) },
10287     { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) },
10288   },
10289   {
10290     /* VEX_W_0F47_P_2_LEN_1 */
10291     { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) },
10292     { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) },
10293   },
10294   {
10295     /* VEX_W_0F4A_P_0_LEN_1 */
10296     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) },
10297     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) },
10298   },
10299   {
10300     /* VEX_W_0F4A_P_2_LEN_1 */
10301     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) },
10302     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) },
10303   },
10304   {
10305     /* VEX_W_0F4B_P_0_LEN_1 */
10306     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) },
10307     { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) },
10308   },
10309   {
10310     /* VEX_W_0F4B_P_2_LEN_1 */
10311     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
10312   },
10313   {
10314     /* VEX_W_0F50_M_0 */
10315     { "vmovmskpX",      { Gdq, XS }, 0 },
10316   },
10317   {
10318     /* VEX_W_0F51_P_0 */
10319     { "vsqrtps",        { XM, EXx }, 0 },
10320   },
10321   {
10322     /* VEX_W_0F51_P_1 */
10323     { "vsqrtss",        { XMScalar, VexScalar, EXdScalar }, 0 },
10324   },
10325   {
10326     /* VEX_W_0F51_P_2  */
10327     { "vsqrtpd",        { XM, EXx }, 0 },
10328   },
10329   {
10330     /* VEX_W_0F51_P_3 */
10331     { "vsqrtsd",        { XMScalar, VexScalar, EXqScalar }, 0 },
10332   },
10333   {
10334     /* VEX_W_0F52_P_0 */
10335     { "vrsqrtps",       { XM, EXx }, 0 },
10336   },
10337   {
10338     /* VEX_W_0F52_P_1 */
10339     { "vrsqrtss",       { XMScalar, VexScalar, EXdScalar }, 0 },
10340   },
10341   {
10342     /* VEX_W_0F53_P_0  */
10343     { "vrcpps",         { XM, EXx }, 0 },
10344   },
10345   {
10346     /* VEX_W_0F53_P_1  */
10347     { "vrcpss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10348   },
10349   {
10350     /* VEX_W_0F58_P_0  */
10351     { "vaddps",         { XM, Vex, EXx }, 0 },
10352   },
10353   {
10354     /* VEX_W_0F58_P_1  */
10355     { "vaddss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10356   },
10357   {
10358     /* VEX_W_0F58_P_2  */
10359     { "vaddpd",         { XM, Vex, EXx }, 0 },
10360   },
10361   {
10362     /* VEX_W_0F58_P_3  */
10363     { "vaddsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10364   },
10365   {
10366     /* VEX_W_0F59_P_0  */
10367     { "vmulps",         { XM, Vex, EXx }, 0 },
10368   },
10369   {
10370     /* VEX_W_0F59_P_1  */
10371     { "vmulss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10372   },
10373   {
10374     /* VEX_W_0F59_P_2  */
10375     { "vmulpd",         { XM, Vex, EXx }, 0 },
10376   },
10377   {
10378     /* VEX_W_0F59_P_3  */
10379     { "vmulsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10380   },
10381   {
10382     /* VEX_W_0F5A_P_0  */
10383     { "vcvtps2pd",      { XM, EXxmmq }, 0 },
10384   },
10385   {
10386     /* VEX_W_0F5A_P_1  */
10387     { "vcvtss2sd",      { XMScalar, VexScalar, EXdScalar }, 0 },
10388   },
10389   {
10390     /* VEX_W_0F5A_P_3  */
10391     { "vcvtsd2ss",      { XMScalar, VexScalar, EXqScalar }, 0 },
10392   },
10393   {
10394     /* VEX_W_0F5B_P_0  */
10395     { "vcvtdq2ps",      { XM, EXx }, 0 },
10396   },
10397   {
10398     /* VEX_W_0F5B_P_1  */
10399     { "vcvttps2dq",     { XM, EXx }, 0 },
10400   },
10401   {
10402     /* VEX_W_0F5B_P_2  */
10403     { "vcvtps2dq",      { XM, EXx }, 0 },
10404   },
10405   {
10406     /* VEX_W_0F5C_P_0  */
10407     { "vsubps",         { XM, Vex, EXx }, 0 },
10408   },
10409   {
10410     /* VEX_W_0F5C_P_1  */
10411     { "vsubss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10412   },
10413   {
10414     /* VEX_W_0F5C_P_2  */
10415     { "vsubpd",         { XM, Vex, EXx }, 0 },
10416   },
10417   {
10418     /* VEX_W_0F5C_P_3  */
10419     { "vsubsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10420   },
10421   {
10422     /* VEX_W_0F5D_P_0  */
10423     { "vminps",         { XM, Vex, EXx }, 0 },
10424   },
10425   {
10426     /* VEX_W_0F5D_P_1  */
10427     { "vminss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10428   },
10429   {
10430     /* VEX_W_0F5D_P_2  */
10431     { "vminpd",         { XM, Vex, EXx }, 0 },
10432   },
10433   {
10434     /* VEX_W_0F5D_P_3  */
10435     { "vminsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10436   },
10437   {
10438     /* VEX_W_0F5E_P_0  */
10439     { "vdivps",         { XM, Vex, EXx }, 0 },
10440   },
10441   {
10442     /* VEX_W_0F5E_P_1  */
10443     { "vdivss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10444   },
10445   {
10446     /* VEX_W_0F5E_P_2  */
10447     { "vdivpd",         { XM, Vex, EXx }, 0 },
10448   },
10449   {
10450     /* VEX_W_0F5E_P_3  */
10451     { "vdivsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10452   },
10453   {
10454     /* VEX_W_0F5F_P_0  */
10455     { "vmaxps",         { XM, Vex, EXx }, 0 },
10456   },
10457   {
10458     /* VEX_W_0F5F_P_1  */
10459     { "vmaxss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10460   },
10461   {
10462     /* VEX_W_0F5F_P_2  */
10463     { "vmaxpd",         { XM, Vex, EXx }, 0 },
10464   },
10465   {
10466     /* VEX_W_0F5F_P_3  */
10467     { "vmaxsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10468   },
10469   {
10470     /* VEX_W_0F60_P_2  */
10471     { "vpunpcklbw",     { XM, Vex, EXx }, 0 },
10472   },
10473   {
10474     /* VEX_W_0F61_P_2  */
10475     { "vpunpcklwd",     { XM, Vex, EXx }, 0 },
10476   },
10477   {
10478     /* VEX_W_0F62_P_2  */
10479     { "vpunpckldq",     { XM, Vex, EXx }, 0 },
10480   },
10481   {
10482     /* VEX_W_0F63_P_2  */
10483     { "vpacksswb",      { XM, Vex, EXx }, 0 },
10484   },
10485   {
10486     /* VEX_W_0F64_P_2  */
10487     { "vpcmpgtb",       { XM, Vex, EXx }, 0 },
10488   },
10489   {
10490     /* VEX_W_0F65_P_2  */
10491     { "vpcmpgtw",       { XM, Vex, EXx }, 0 },
10492   },
10493   {
10494     /* VEX_W_0F66_P_2  */
10495     { "vpcmpgtd",       { XM, Vex, EXx }, 0 },
10496   },
10497   {
10498     /* VEX_W_0F67_P_2  */
10499     { "vpackuswb",      { XM, Vex, EXx }, 0 },
10500   },
10501   {
10502     /* VEX_W_0F68_P_2  */
10503     { "vpunpckhbw",     { XM, Vex, EXx }, 0 },
10504   },
10505   {
10506     /* VEX_W_0F69_P_2  */
10507     { "vpunpckhwd",     { XM, Vex, EXx }, 0 },
10508   },
10509   {
10510     /* VEX_W_0F6A_P_2  */
10511     { "vpunpckhdq",     { XM, Vex, EXx }, 0 },
10512   },
10513   {
10514     /* VEX_W_0F6B_P_2  */
10515     { "vpackssdw",      { XM, Vex, EXx }, 0 },
10516   },
10517   {
10518     /* VEX_W_0F6C_P_2  */
10519     { "vpunpcklqdq",    { XM, Vex, EXx }, 0 },
10520   },
10521   {
10522     /* VEX_W_0F6D_P_2  */
10523     { "vpunpckhqdq",    { XM, Vex, EXx }, 0 },
10524   },
10525   {
10526     /* VEX_W_0F6F_P_1  */
10527     { "vmovdqu",        { XM, EXx }, 0 },
10528   },
10529   {
10530     /* VEX_W_0F6F_P_2  */
10531     { "vmovdqa",        { XM, EXx }, 0 },
10532   },
10533   {
10534     /* VEX_W_0F70_P_1 */
10535     { "vpshufhw",       { XM, EXx, Ib }, 0 },
10536   },
10537   {
10538     /* VEX_W_0F70_P_2 */
10539     { "vpshufd",        { XM, EXx, Ib }, 0 },
10540   },
10541   {
10542     /* VEX_W_0F70_P_3 */
10543     { "vpshuflw",       { XM, EXx, Ib }, 0 },
10544   },
10545   {
10546     /* VEX_W_0F71_R_2_P_2  */
10547     { "vpsrlw",         { Vex, XS, Ib }, 0 },
10548   },
10549   {
10550     /* VEX_W_0F71_R_4_P_2  */
10551     { "vpsraw",         { Vex, XS, Ib }, 0 },
10552   },
10553   {
10554     /* VEX_W_0F71_R_6_P_2  */
10555     { "vpsllw",         { Vex, XS, Ib }, 0 },
10556   },
10557   {
10558     /* VEX_W_0F72_R_2_P_2  */
10559     { "vpsrld",         { Vex, XS, Ib }, 0 },
10560   },
10561   {
10562     /* VEX_W_0F72_R_4_P_2  */
10563     { "vpsrad",         { Vex, XS, Ib }, 0 },
10564   },
10565   {
10566     /* VEX_W_0F72_R_6_P_2  */
10567     { "vpslld",         { Vex, XS, Ib }, 0 },
10568   },
10569   {
10570     /* VEX_W_0F73_R_2_P_2  */
10571     { "vpsrlq",         { Vex, XS, Ib }, 0 },
10572   },
10573   {
10574     /* VEX_W_0F73_R_3_P_2  */
10575     { "vpsrldq",        { Vex, XS, Ib }, 0 },
10576   },
10577   {
10578     /* VEX_W_0F73_R_6_P_2  */
10579     { "vpsllq",         { Vex, XS, Ib }, 0 },
10580   },
10581   {
10582     /* VEX_W_0F73_R_7_P_2  */
10583     { "vpslldq",        { Vex, XS, Ib }, 0 },
10584   },
10585   {
10586     /* VEX_W_0F74_P_2 */
10587     { "vpcmpeqb",       { XM, Vex, EXx }, 0 },
10588   },
10589   {
10590     /* VEX_W_0F75_P_2 */
10591     { "vpcmpeqw",       { XM, Vex, EXx }, 0 },
10592   },
10593   {
10594     /* VEX_W_0F76_P_2 */
10595     { "vpcmpeqd",       { XM, Vex, EXx }, 0 },
10596   },
10597   {
10598     /* VEX_W_0F77_P_0 */
10599     { "",               { VZERO }, 0 },
10600   },
10601   {
10602     /* VEX_W_0F7C_P_2 */
10603     { "vhaddpd",        { XM, Vex, EXx }, 0 },
10604   },
10605   {
10606     /* VEX_W_0F7C_P_3 */
10607     { "vhaddps",        { XM, Vex, EXx }, 0 },
10608   },
10609   {
10610     /* VEX_W_0F7D_P_2 */
10611     { "vhsubpd",        { XM, Vex, EXx }, 0 },
10612   },
10613   {
10614     /* VEX_W_0F7D_P_3 */
10615     { "vhsubps",        { XM, Vex, EXx }, 0 },
10616   },
10617   {
10618     /* VEX_W_0F7E_P_1 */
10619     { "vmovq",          { XMScalar, EXqScalar }, 0 },
10620   },
10621   {
10622     /* VEX_W_0F7F_P_1 */
10623     { "vmovdqu",        { EXxS, XM }, 0 },
10624   },
10625   {
10626     /* VEX_W_0F7F_P_2 */
10627     { "vmovdqa",        { EXxS, XM }, 0 },
10628   },
10629   {
10630     /* VEX_W_0F90_P_0_LEN_0 */
10631     { "kmovw",          { MaskG, MaskE }, 0 },
10632     { "kmovq",          { MaskG, MaskE }, 0 },
10633   },
10634   {
10635     /* VEX_W_0F90_P_2_LEN_0 */
10636     { "kmovb",          { MaskG, MaskBDE }, 0 },
10637     { "kmovd",          { MaskG, MaskBDE }, 0 },
10638   },
10639   {
10640     /* VEX_W_0F91_P_0_LEN_0 */
10641     { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
10642     { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
10643   },
10644   {
10645     /* VEX_W_0F91_P_2_LEN_0 */
10646     { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
10647     { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
10648   },
10649   {
10650     /* VEX_W_0F92_P_0_LEN_0 */
10651     { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
10652   },
10653   {
10654     /* VEX_W_0F92_P_2_LEN_0 */
10655     { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
10656   },
10657   {
10658     /* VEX_W_0F92_P_3_LEN_0 */
10659     { MOD_TABLE (MOD_VEX_W_0_0F92_P_3_LEN_0) },
10660     { MOD_TABLE (MOD_VEX_W_1_0F92_P_3_LEN_0) },
10661   },
10662   {
10663     /* VEX_W_0F93_P_0_LEN_0 */
10664     { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
10665   },
10666   {
10667     /* VEX_W_0F93_P_2_LEN_0 */
10668     { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
10669   },
10670   {
10671     /* VEX_W_0F93_P_3_LEN_0 */
10672     { MOD_TABLE (MOD_VEX_W_0_0F93_P_3_LEN_0) },
10673     { MOD_TABLE (MOD_VEX_W_1_0F93_P_3_LEN_0) },
10674   },
10675   {
10676     /* VEX_W_0F98_P_0_LEN_0 */
10677     { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
10678     { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
10679   },
10680   {
10681     /* VEX_W_0F98_P_2_LEN_0 */
10682     { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
10683     { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
10684   },
10685   {
10686     /* VEX_W_0F99_P_0_LEN_0 */
10687     { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
10688     { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
10689   },
10690   {
10691     /* VEX_W_0F99_P_2_LEN_0 */
10692     { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
10693     { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
10694   },
10695   {
10696     /* VEX_W_0FAE_R_2_M_0 */
10697     { "vldmxcsr",       { Md }, 0 },
10698   },
10699   {
10700     /* VEX_W_0FAE_R_3_M_0 */
10701     { "vstmxcsr",       { Md }, 0 },
10702   },
10703   {
10704     /* VEX_W_0FC2_P_0 */
10705     { "vcmpps",         { XM, Vex, EXx, VCMP }, 0 },
10706   },
10707   {
10708     /* VEX_W_0FC2_P_1 */
10709     { "vcmpss",         { XMScalar, VexScalar, EXdScalar, VCMP }, 0 },
10710   },
10711   {
10712     /* VEX_W_0FC2_P_2 */
10713     { "vcmppd",         { XM, Vex, EXx, VCMP }, 0 },
10714   },
10715   {
10716     /* VEX_W_0FC2_P_3 */
10717     { "vcmpsd",         { XMScalar, VexScalar, EXqScalar, VCMP }, 0 },
10718   },
10719   {
10720     /* VEX_W_0FC4_P_2 */
10721     { "vpinsrw",        { XM, Vex128, Edqw, Ib }, 0 },
10722   },
10723   {
10724     /* VEX_W_0FC5_P_2 */
10725     { "vpextrw",        { Gdq, XS, Ib }, 0 },
10726   },
10727   {
10728     /* VEX_W_0FD0_P_2 */
10729     { "vaddsubpd",      { XM, Vex, EXx }, 0 },
10730   },
10731   {
10732     /* VEX_W_0FD0_P_3 */
10733     { "vaddsubps",      { XM, Vex, EXx }, 0 },
10734   },
10735   {
10736     /* VEX_W_0FD1_P_2 */
10737     { "vpsrlw",         { XM, Vex, EXxmm }, 0 },
10738   },
10739   {
10740     /* VEX_W_0FD2_P_2 */
10741     { "vpsrld",         { XM, Vex, EXxmm }, 0 },
10742   },
10743   {
10744     /* VEX_W_0FD3_P_2 */
10745     { "vpsrlq",         { XM, Vex, EXxmm }, 0 },
10746   },
10747   {
10748     /* VEX_W_0FD4_P_2 */
10749     { "vpaddq",         { XM, Vex, EXx }, 0 },
10750   },
10751   {
10752     /* VEX_W_0FD5_P_2 */
10753     { "vpmullw",        { XM, Vex, EXx }, 0 },
10754   },
10755   {
10756     /* VEX_W_0FD6_P_2 */
10757     { "vmovq",          { EXqScalarS, XMScalar }, 0 },
10758   },
10759   {
10760     /* VEX_W_0FD7_P_2_M_1 */
10761     { "vpmovmskb",      { Gdq, XS }, 0 },
10762   },
10763   {
10764     /* VEX_W_0FD8_P_2 */
10765     { "vpsubusb",       { XM, Vex, EXx }, 0 },
10766   },
10767   {
10768     /* VEX_W_0FD9_P_2 */
10769     { "vpsubusw",       { XM, Vex, EXx }, 0 },
10770   },
10771   {
10772     /* VEX_W_0FDA_P_2 */
10773     { "vpminub",        { XM, Vex, EXx }, 0 },
10774   },
10775   {
10776     /* VEX_W_0FDB_P_2 */
10777     { "vpand",          { XM, Vex, EXx }, 0 },
10778   },
10779   {
10780     /* VEX_W_0FDC_P_2 */
10781     { "vpaddusb",       { XM, Vex, EXx }, 0 },
10782   },
10783   {
10784     /* VEX_W_0FDD_P_2 */
10785     { "vpaddusw",       { XM, Vex, EXx }, 0 },
10786   },
10787   {
10788     /* VEX_W_0FDE_P_2 */
10789     { "vpmaxub",        { XM, Vex, EXx }, 0 },
10790   },
10791   {
10792     /* VEX_W_0FDF_P_2 */
10793     { "vpandn",         { XM, Vex, EXx }, 0 },
10794   },
10795   {
10796     /* VEX_W_0FE0_P_2  */
10797     { "vpavgb",         { XM, Vex, EXx }, 0 },
10798   },
10799   {
10800     /* VEX_W_0FE1_P_2  */
10801     { "vpsraw",         { XM, Vex, EXxmm }, 0 },
10802   },
10803   {
10804     /* VEX_W_0FE2_P_2  */
10805     { "vpsrad",         { XM, Vex, EXxmm }, 0 },
10806   },
10807   {
10808     /* VEX_W_0FE3_P_2  */
10809     { "vpavgw",         { XM, Vex, EXx }, 0 },
10810   },
10811   {
10812     /* VEX_W_0FE4_P_2  */
10813     { "vpmulhuw",       { XM, Vex, EXx }, 0 },
10814   },
10815   {
10816     /* VEX_W_0FE5_P_2  */
10817     { "vpmulhw",        { XM, Vex, EXx }, 0 },
10818   },
10819   {
10820     /* VEX_W_0FE6_P_1  */
10821     { "vcvtdq2pd",      { XM, EXxmmq }, 0 },
10822   },
10823   {
10824     /* VEX_W_0FE6_P_2  */
10825     { "vcvttpd2dq%XY",  { XMM, EXx }, 0 },
10826   },
10827   {
10828     /* VEX_W_0FE6_P_3  */
10829     { "vcvtpd2dq%XY",   { XMM, EXx }, 0 },
10830   },
10831   {
10832     /* VEX_W_0FE7_P_2_M_0 */
10833     { "vmovntdq",       { Mx, XM }, 0 },
10834   },
10835   {
10836     /* VEX_W_0FE8_P_2  */
10837     { "vpsubsb",        { XM, Vex, EXx }, 0 },
10838   },
10839   {
10840     /* VEX_W_0FE9_P_2  */
10841     { "vpsubsw",        { XM, Vex, EXx }, 0 },
10842   },
10843   {
10844     /* VEX_W_0FEA_P_2  */
10845     { "vpminsw",        { XM, Vex, EXx }, 0 },
10846   },
10847   {
10848     /* VEX_W_0FEB_P_2  */
10849     { "vpor",           { XM, Vex, EXx }, 0 },
10850   },
10851   {
10852     /* VEX_W_0FEC_P_2  */
10853     { "vpaddsb",        { XM, Vex, EXx }, 0 },
10854   },
10855   {
10856     /* VEX_W_0FED_P_2  */
10857     { "vpaddsw",        { XM, Vex, EXx }, 0 },
10858   },
10859   {
10860     /* VEX_W_0FEE_P_2  */
10861     { "vpmaxsw",        { XM, Vex, EXx }, 0 },
10862   },
10863   {
10864     /* VEX_W_0FEF_P_2  */
10865     { "vpxor",          { XM, Vex, EXx }, 0 },
10866   },
10867   {
10868     /* VEX_W_0FF0_P_3_M_0 */
10869     { "vlddqu",         { XM, M }, 0 },
10870   },
10871   {
10872     /* VEX_W_0FF1_P_2 */
10873     { "vpsllw",         { XM, Vex, EXxmm }, 0 },
10874   },
10875   {
10876     /* VEX_W_0FF2_P_2 */
10877     { "vpslld",         { XM, Vex, EXxmm }, 0 },
10878   },
10879   {
10880     /* VEX_W_0FF3_P_2 */
10881     { "vpsllq",         { XM, Vex, EXxmm }, 0 },
10882   },
10883   {
10884     /* VEX_W_0FF4_P_2 */
10885     { "vpmuludq",       { XM, Vex, EXx }, 0 },
10886   },
10887   {
10888     /* VEX_W_0FF5_P_2 */
10889     { "vpmaddwd",       { XM, Vex, EXx }, 0 },
10890   },
10891   {
10892     /* VEX_W_0FF6_P_2 */
10893     { "vpsadbw",        { XM, Vex, EXx }, 0 },
10894   },
10895   {
10896     /* VEX_W_0FF7_P_2 */
10897     { "vmaskmovdqu",    { XM, XS }, 0 },
10898   },
10899   {
10900     /* VEX_W_0FF8_P_2 */
10901     { "vpsubb",         { XM, Vex, EXx }, 0 },
10902   },
10903   {
10904     /* VEX_W_0FF9_P_2 */
10905     { "vpsubw",         { XM, Vex, EXx }, 0 },
10906   },
10907   {
10908     /* VEX_W_0FFA_P_2 */
10909     { "vpsubd",         { XM, Vex, EXx }, 0 },
10910   },
10911   {
10912     /* VEX_W_0FFB_P_2 */
10913     { "vpsubq",         { XM, Vex, EXx }, 0 },
10914   },
10915   {
10916     /* VEX_W_0FFC_P_2 */
10917     { "vpaddb",         { XM, Vex, EXx }, 0 },
10918   },
10919   {
10920     /* VEX_W_0FFD_P_2 */
10921     { "vpaddw",         { XM, Vex, EXx }, 0 },
10922   },
10923   {
10924     /* VEX_W_0FFE_P_2 */
10925     { "vpaddd",         { XM, Vex, EXx }, 0 },
10926   },
10927   {
10928     /* VEX_W_0F3800_P_2  */
10929     { "vpshufb",        { XM, Vex, EXx }, 0 },
10930   },
10931   {
10932     /* VEX_W_0F3801_P_2  */
10933     { "vphaddw",        { XM, Vex, EXx }, 0 },
10934   },
10935   {
10936     /* VEX_W_0F3802_P_2  */
10937     { "vphaddd",        { XM, Vex, EXx }, 0 },
10938   },
10939   {
10940     /* VEX_W_0F3803_P_2  */
10941     { "vphaddsw",       { XM, Vex, EXx }, 0 },
10942   },
10943   {
10944     /* VEX_W_0F3804_P_2  */
10945     { "vpmaddubsw",     { XM, Vex, EXx }, 0 },
10946   },
10947   {
10948     /* VEX_W_0F3805_P_2  */
10949     { "vphsubw",        { XM, Vex, EXx }, 0 },
10950   },
10951   {
10952     /* VEX_W_0F3806_P_2  */
10953     { "vphsubd",        { XM, Vex, EXx }, 0 },
10954   },
10955   {
10956     /* VEX_W_0F3807_P_2  */
10957     { "vphsubsw",       { XM, Vex, EXx }, 0 },
10958   },
10959   {
10960     /* VEX_W_0F3808_P_2  */
10961     { "vpsignb",        { XM, Vex, EXx }, 0 },
10962   },
10963   {
10964     /* VEX_W_0F3809_P_2  */
10965     { "vpsignw",        { XM, Vex, EXx }, 0 },
10966   },
10967   {
10968     /* VEX_W_0F380A_P_2  */
10969     { "vpsignd",        { XM, Vex, EXx }, 0 },
10970   },
10971   {
10972     /* VEX_W_0F380B_P_2  */
10973     { "vpmulhrsw",      { XM, Vex, EXx }, 0 },
10974   },
10975   {
10976     /* VEX_W_0F380C_P_2  */
10977     { "vpermilps",      { XM, Vex, EXx }, 0 },
10978   },
10979   {
10980     /* VEX_W_0F380D_P_2  */
10981     { "vpermilpd",      { XM, Vex, EXx }, 0 },
10982   },
10983   {
10984     /* VEX_W_0F380E_P_2  */
10985     { "vtestps",        { XM, EXx }, 0 },
10986   },
10987   {
10988     /* VEX_W_0F380F_P_2  */
10989     { "vtestpd",        { XM, EXx }, 0 },
10990   },
10991   {
10992     /* VEX_W_0F3816_P_2  */
10993     { "vpermps",        { XM, Vex, EXx }, 0 },
10994   },
10995   {
10996     /* VEX_W_0F3817_P_2 */
10997     { "vptest",         { XM, EXx }, 0 },
10998   },
10999   {
11000     /* VEX_W_0F3818_P_2 */
11001     { "vbroadcastss",   { XM, EXxmm_md }, 0 },
11002   },
11003   {
11004     /* VEX_W_0F3819_P_2 */
11005     { "vbroadcastsd",   { XM, EXxmm_mq }, 0 },
11006   },
11007   {
11008     /* VEX_W_0F381A_P_2_M_0 */
11009     { "vbroadcastf128", { XM, Mxmm }, 0 },
11010   },
11011   {
11012     /* VEX_W_0F381C_P_2 */
11013     { "vpabsb",         { XM, EXx }, 0 },
11014   },
11015   {
11016     /* VEX_W_0F381D_P_2 */
11017     { "vpabsw",         { XM, EXx }, 0 },
11018   },
11019   {
11020     /* VEX_W_0F381E_P_2 */
11021     { "vpabsd",         { XM, EXx }, 0 },
11022   },
11023   {
11024     /* VEX_W_0F3820_P_2 */
11025     { "vpmovsxbw",      { XM, EXxmmq }, 0 },
11026   },
11027   {
11028     /* VEX_W_0F3821_P_2 */
11029     { "vpmovsxbd",      { XM, EXxmmqd }, 0 },
11030   },
11031   {
11032     /* VEX_W_0F3822_P_2 */
11033     { "vpmovsxbq",      { XM, EXxmmdw }, 0 },
11034   },
11035   {
11036     /* VEX_W_0F3823_P_2 */
11037     { "vpmovsxwd",      { XM, EXxmmq }, 0 },
11038   },
11039   {
11040     /* VEX_W_0F3824_P_2 */
11041     { "vpmovsxwq",      { XM, EXxmmqd }, 0 },
11042   },
11043   {
11044     /* VEX_W_0F3825_P_2 */
11045     { "vpmovsxdq",      { XM, EXxmmq }, 0 },
11046   },
11047   {
11048     /* VEX_W_0F3828_P_2 */
11049     { "vpmuldq",        { XM, Vex, EXx }, 0 },
11050   },
11051   {
11052     /* VEX_W_0F3829_P_2 */
11053     { "vpcmpeqq",       { XM, Vex, EXx }, 0 },
11054   },
11055   {
11056     /* VEX_W_0F382A_P_2_M_0 */
11057     { "vmovntdqa",      { XM, Mx }, 0 },
11058   },
11059   {
11060     /* VEX_W_0F382B_P_2 */
11061     { "vpackusdw",      { XM, Vex, EXx }, 0 },
11062   },
11063   {
11064     /* VEX_W_0F382C_P_2_M_0 */
11065     { "vmaskmovps",     { XM, Vex, Mx }, 0 },
11066   },
11067   {
11068     /* VEX_W_0F382D_P_2_M_0 */
11069     { "vmaskmovpd",     { XM, Vex, Mx }, 0 },
11070   },
11071   {
11072     /* VEX_W_0F382E_P_2_M_0 */
11073     { "vmaskmovps",     { Mx, Vex, XM }, 0 },
11074   },
11075   {
11076     /* VEX_W_0F382F_P_2_M_0 */
11077     { "vmaskmovpd",     { Mx, Vex, XM }, 0 },
11078   },
11079   {
11080     /* VEX_W_0F3830_P_2 */
11081     { "vpmovzxbw",      { XM, EXxmmq }, 0 },
11082   },
11083   {
11084     /* VEX_W_0F3831_P_2 */
11085     { "vpmovzxbd",      { XM, EXxmmqd }, 0 },
11086   },
11087   {
11088     /* VEX_W_0F3832_P_2 */
11089     { "vpmovzxbq",      { XM, EXxmmdw }, 0 },
11090   },
11091   {
11092     /* VEX_W_0F3833_P_2 */
11093     { "vpmovzxwd",      { XM, EXxmmq }, 0 },
11094   },
11095   {
11096     /* VEX_W_0F3834_P_2 */
11097     { "vpmovzxwq",      { XM, EXxmmqd }, 0 },
11098   },
11099   {
11100     /* VEX_W_0F3835_P_2 */
11101     { "vpmovzxdq",      { XM, EXxmmq }, 0 },
11102   },
11103   {
11104     /* VEX_W_0F3836_P_2  */
11105     { "vpermd",         { XM, Vex, EXx }, 0 },
11106   },
11107   {
11108     /* VEX_W_0F3837_P_2 */
11109     { "vpcmpgtq",       { XM, Vex, EXx }, 0 },
11110   },
11111   {
11112     /* VEX_W_0F3838_P_2 */
11113     { "vpminsb",        { XM, Vex, EXx }, 0 },
11114   },
11115   {
11116     /* VEX_W_0F3839_P_2 */
11117     { "vpminsd",        { XM, Vex, EXx }, 0 },
11118   },
11119   {
11120     /* VEX_W_0F383A_P_2 */
11121     { "vpminuw",        { XM, Vex, EXx }, 0 },
11122   },
11123   {
11124     /* VEX_W_0F383B_P_2 */
11125     { "vpminud",        { XM, Vex, EXx }, 0 },
11126   },
11127   {
11128     /* VEX_W_0F383C_P_2 */
11129     { "vpmaxsb",        { XM, Vex, EXx }, 0 },
11130   },
11131   {
11132     /* VEX_W_0F383D_P_2 */
11133     { "vpmaxsd",        { XM, Vex, EXx }, 0 },
11134   },
11135   {
11136     /* VEX_W_0F383E_P_2 */
11137     { "vpmaxuw",        { XM, Vex, EXx }, 0 },
11138   },
11139   {
11140     /* VEX_W_0F383F_P_2 */
11141     { "vpmaxud",        { XM, Vex, EXx }, 0 },
11142   },
11143   {
11144     /* VEX_W_0F3840_P_2 */
11145     { "vpmulld",        { XM, Vex, EXx }, 0 },
11146   },
11147   {
11148     /* VEX_W_0F3841_P_2 */
11149     { "vphminposuw",    { XM, EXx }, 0 },
11150   },
11151   {
11152     /* VEX_W_0F3846_P_2 */
11153     { "vpsravd",        { XM, Vex, EXx }, 0 },
11154   },
11155   {
11156     /* VEX_W_0F3858_P_2 */
11157     { "vpbroadcastd", { XM, EXxmm_md }, 0 },
11158   },
11159   {
11160     /* VEX_W_0F3859_P_2 */
11161     { "vpbroadcastq",   { XM, EXxmm_mq }, 0 },
11162   },
11163   {
11164     /* VEX_W_0F385A_P_2_M_0 */
11165     { "vbroadcasti128", { XM, Mxmm }, 0 },
11166   },
11167   {
11168     /* VEX_W_0F3878_P_2 */
11169     { "vpbroadcastb",   { XM, EXxmm_mb }, 0 },
11170   },
11171   {
11172     /* VEX_W_0F3879_P_2 */
11173     { "vpbroadcastw",   { XM, EXxmm_mw }, 0 },
11174   },
11175   {
11176     /* VEX_W_0F38DB_P_2 */
11177     { "vaesimc",        { XM, EXx }, 0 },
11178   },
11179   {
11180     /* VEX_W_0F38DC_P_2 */
11181     { "vaesenc",        { XM, Vex128, EXx }, 0 },
11182   },
11183   {
11184     /* VEX_W_0F38DD_P_2 */
11185     { "vaesenclast",    { XM, Vex128, EXx }, 0 },
11186   },
11187   {
11188     /* VEX_W_0F38DE_P_2 */
11189     { "vaesdec",        { XM, Vex128, EXx }, 0 },
11190   },
11191   {
11192     /* VEX_W_0F38DF_P_2 */
11193     { "vaesdeclast",    { XM, Vex128, EXx }, 0 },
11194   },
11195   {
11196     /* VEX_W_0F3A00_P_2 */
11197     { Bad_Opcode },
11198     { "vpermq",         { XM, EXx, Ib }, 0 },
11199   },
11200   {
11201     /* VEX_W_0F3A01_P_2 */
11202     { Bad_Opcode },
11203     { "vpermpd",        { XM, EXx, Ib }, 0 },
11204   },
11205   {
11206     /* VEX_W_0F3A02_P_2 */
11207     { "vpblendd",       { XM, Vex, EXx, Ib }, 0 },
11208   },
11209   {
11210     /* VEX_W_0F3A04_P_2 */
11211     { "vpermilps",      { XM, EXx, Ib }, 0 },
11212   },
11213   {
11214     /* VEX_W_0F3A05_P_2 */
11215     { "vpermilpd",      { XM, EXx, Ib }, 0 },
11216   },
11217   {
11218     /* VEX_W_0F3A06_P_2 */
11219     { "vperm2f128",     { XM, Vex256, EXx, Ib }, 0 },
11220   },
11221   {
11222     /* VEX_W_0F3A08_P_2 */
11223     { "vroundps",       { XM, EXx, Ib }, 0 },
11224   },
11225   {
11226     /* VEX_W_0F3A09_P_2 */
11227     { "vroundpd",       { XM, EXx, Ib }, 0 },
11228   },
11229   {
11230     /* VEX_W_0F3A0A_P_2 */
11231     { "vroundss",       { XMScalar, VexScalar, EXdScalar, Ib }, 0 },
11232   },
11233   {
11234     /* VEX_W_0F3A0B_P_2 */
11235     { "vroundsd",       { XMScalar, VexScalar, EXqScalar, Ib }, 0 },
11236   },
11237   {
11238     /* VEX_W_0F3A0C_P_2 */
11239     { "vblendps",       { XM, Vex, EXx, Ib }, 0 },
11240   },
11241   {
11242     /* VEX_W_0F3A0D_P_2 */
11243     { "vblendpd",       { XM, Vex, EXx, Ib }, 0 },
11244   },
11245   {
11246     /* VEX_W_0F3A0E_P_2 */
11247     { "vpblendw",       { XM, Vex, EXx, Ib }, 0 },
11248   },
11249   {
11250     /* VEX_W_0F3A0F_P_2 */
11251     { "vpalignr",       { XM, Vex, EXx, Ib }, 0 },
11252   },
11253   {
11254     /* VEX_W_0F3A14_P_2 */
11255     { "vpextrb",        { Edqb, XM, Ib }, 0 },
11256   },
11257   {
11258     /* VEX_W_0F3A15_P_2 */
11259     { "vpextrw",        { Edqw, XM, Ib }, 0 },
11260   },
11261   {
11262     /* VEX_W_0F3A18_P_2 */
11263     { "vinsertf128",    { XM, Vex256, EXxmm, Ib }, 0 },
11264   },
11265   {
11266     /* VEX_W_0F3A19_P_2 */
11267     { "vextractf128",   { EXxmm, XM, Ib }, 0 },
11268   },
11269   {
11270     /* VEX_W_0F3A20_P_2 */
11271     { "vpinsrb",        { XM, Vex128, Edqb, Ib }, 0 },
11272   },
11273   {
11274     /* VEX_W_0F3A21_P_2 */
11275     { "vinsertps",      { XM, Vex128, EXd, Ib }, 0 },
11276   },
11277   {
11278     /* VEX_W_0F3A30_P_2_LEN_0 */
11279     { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) },
11280     { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) },
11281   },
11282   {
11283     /* VEX_W_0F3A31_P_2_LEN_0 */
11284     { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) },
11285     { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) },
11286   },
11287   {
11288     /* VEX_W_0F3A32_P_2_LEN_0 */
11289     { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) },
11290     { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) },
11291   },
11292   {
11293     /* VEX_W_0F3A33_P_2_LEN_0 */
11294     { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) },
11295     { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) },
11296   },
11297   {
11298     /* VEX_W_0F3A38_P_2 */
11299     { "vinserti128",    { XM, Vex256, EXxmm, Ib }, 0 },
11300   },
11301   {
11302     /* VEX_W_0F3A39_P_2 */
11303     { "vextracti128",   { EXxmm, XM, Ib }, 0 },
11304   },
11305   {
11306     /* VEX_W_0F3A40_P_2 */
11307     { "vdpps",          { XM, Vex, EXx, Ib }, 0 },
11308   },
11309   {
11310     /* VEX_W_0F3A41_P_2 */
11311     { "vdppd",          { XM, Vex128, EXx, Ib }, 0 },
11312   },
11313   {
11314     /* VEX_W_0F3A42_P_2 */
11315     { "vmpsadbw",       { XM, Vex, EXx, Ib }, 0 },
11316   },
11317   {
11318     /* VEX_W_0F3A44_P_2 */
11319     { "vpclmulqdq",     { XM, Vex128, EXx, PCLMUL }, 0 },
11320   },
11321   {
11322     /* VEX_W_0F3A46_P_2 */
11323     { "vperm2i128",     { XM, Vex256, EXx, Ib }, 0 },
11324   },
11325   {
11326     /* VEX_W_0F3A48_P_2 */
11327     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11328     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11329   },
11330   {
11331     /* VEX_W_0F3A49_P_2 */
11332     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11333     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11334   },
11335   {
11336     /* VEX_W_0F3A4A_P_2 */
11337     { "vblendvps",      { XM, Vex, EXx, XMVexI4 }, 0 },
11338   },
11339   {
11340     /* VEX_W_0F3A4B_P_2 */
11341     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 }, 0 },
11342   },
11343   {
11344     /* VEX_W_0F3A4C_P_2 */
11345     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 }, 0 },
11346   },
11347   {
11348     /* VEX_W_0F3A62_P_2 */
11349     { "vpcmpistrm",     { XM, EXx, Ib }, 0 },
11350   },
11351   {
11352     /* VEX_W_0F3A63_P_2 */
11353     { "vpcmpistri",     { XM, EXx, Ib }, 0 },
11354   },
11355   {
11356     /* VEX_W_0F3ADF_P_2 */
11357     { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
11358   },
11359 #define NEED_VEX_W_TABLE
11360 #include "i386-dis-evex.h"
11361 #undef NEED_VEX_W_TABLE
11362 };
11363
11364 static const struct dis386 mod_table[][2] = {
11365   {
11366     /* MOD_8D */
11367     { "leaS",           { Gv, M }, 0 },
11368   },
11369   {
11370     /* MOD_C6_REG_7 */
11371     { Bad_Opcode },
11372     { RM_TABLE (RM_C6_REG_7) },
11373   },
11374   {
11375     /* MOD_C7_REG_7 */
11376     { Bad_Opcode },
11377     { RM_TABLE (RM_C7_REG_7) },
11378   },
11379   {
11380     /* MOD_FF_REG_3 */
11381     { "Jcall^", { indirEp }, 0 },
11382   },
11383   {
11384     /* MOD_FF_REG_5 */
11385     { "Jjmp^", { indirEp }, 0 },
11386   },
11387   {
11388     /* MOD_0F01_REG_0 */
11389     { X86_64_TABLE (X86_64_0F01_REG_0) },
11390     { RM_TABLE (RM_0F01_REG_0) },
11391   },
11392   {
11393     /* MOD_0F01_REG_1 */
11394     { X86_64_TABLE (X86_64_0F01_REG_1) },
11395     { RM_TABLE (RM_0F01_REG_1) },
11396   },
11397   {
11398     /* MOD_0F01_REG_2 */
11399     { X86_64_TABLE (X86_64_0F01_REG_2) },
11400     { RM_TABLE (RM_0F01_REG_2) },
11401   },
11402   {
11403     /* MOD_0F01_REG_3 */
11404     { X86_64_TABLE (X86_64_0F01_REG_3) },
11405     { RM_TABLE (RM_0F01_REG_3) },
11406   },
11407   {
11408     /* MOD_0F01_REG_5 */
11409     { Bad_Opcode },
11410     { RM_TABLE (RM_0F01_REG_5) },
11411   },
11412   {
11413     /* MOD_0F01_REG_7 */
11414     { "invlpg",         { Mb }, 0 },
11415     { RM_TABLE (RM_0F01_REG_7) },
11416   },
11417   {
11418     /* MOD_0F12_PREFIX_0 */
11419     { "movlps",         { XM, EXq }, PREFIX_OPCODE },
11420     { "movhlps",        { XM, EXq }, PREFIX_OPCODE },
11421   },
11422   {
11423     /* MOD_0F13 */
11424     { "movlpX",         { EXq, XM }, PREFIX_OPCODE },
11425   },
11426   {
11427     /* MOD_0F16_PREFIX_0 */
11428     { "movhps",         { XM, EXq }, 0 },
11429     { "movlhps",        { XM, EXq }, 0 },
11430   },
11431   {
11432     /* MOD_0F17 */
11433     { "movhpX",         { EXq, XM }, PREFIX_OPCODE },
11434   },
11435   {
11436     /* MOD_0F18_REG_0 */
11437     { "prefetchnta",    { Mb }, 0 },
11438   },
11439   {
11440     /* MOD_0F18_REG_1 */
11441     { "prefetcht0",     { Mb }, 0 },
11442   },
11443   {
11444     /* MOD_0F18_REG_2 */
11445     { "prefetcht1",     { Mb }, 0 },
11446   },
11447   {
11448     /* MOD_0F18_REG_3 */
11449     { "prefetcht2",     { Mb }, 0 },
11450   },
11451   {
11452     /* MOD_0F18_REG_4 */
11453     { "nop/reserved",   { Mb }, 0 },
11454   },
11455   {
11456     /* MOD_0F18_REG_5 */
11457     { "nop/reserved",   { Mb }, 0 },
11458   },
11459   {
11460     /* MOD_0F18_REG_6 */
11461     { "nop/reserved",   { Mb }, 0 },
11462   },
11463   {
11464     /* MOD_0F18_REG_7 */
11465     { "nop/reserved",   { Mb }, 0 },
11466   },
11467   {
11468     /* MOD_0F1A_PREFIX_0 */
11469     { "bndldx",         { Gbnd, Ev_bnd }, 0 },
11470     { "nopQ",           { Ev }, 0 },
11471   },
11472   {
11473     /* MOD_0F1B_PREFIX_0 */
11474     { "bndstx",         { Ev_bnd, Gbnd }, 0 },
11475     { "nopQ",           { Ev }, 0 },
11476   },
11477   {
11478     /* MOD_0F1B_PREFIX_1 */
11479     { "bndmk",          { Gbnd, Ev_bnd }, 0 },
11480     { "nopQ",           { Ev }, 0 },
11481   },
11482   {
11483     /* MOD_0F24 */
11484     { Bad_Opcode },
11485     { "movL",           { Rd, Td }, 0 },
11486   },
11487   {
11488     /* MOD_0F26 */
11489     { Bad_Opcode },
11490     { "movL",           { Td, Rd }, 0 },
11491   },
11492   {
11493     /* MOD_0F2B_PREFIX_0 */
11494     {"movntps",         { Mx, XM }, PREFIX_OPCODE },
11495   },
11496   {
11497     /* MOD_0F2B_PREFIX_1 */
11498     {"movntss",         { Md, XM }, PREFIX_OPCODE },
11499   },
11500   {
11501     /* MOD_0F2B_PREFIX_2 */
11502     {"movntpd",         { Mx, XM }, PREFIX_OPCODE },
11503   },
11504   {
11505     /* MOD_0F2B_PREFIX_3 */
11506     {"movntsd",         { Mq, XM }, PREFIX_OPCODE },
11507   },
11508   {
11509     /* MOD_0F51 */
11510     { Bad_Opcode },
11511     { "movmskpX",       { Gdq, XS }, PREFIX_OPCODE },
11512   },
11513   {
11514     /* MOD_0F71_REG_2 */
11515     { Bad_Opcode },
11516     { "psrlw",          { MS, Ib }, 0 },
11517   },
11518   {
11519     /* MOD_0F71_REG_4 */
11520     { Bad_Opcode },
11521     { "psraw",          { MS, Ib }, 0 },
11522   },
11523   {
11524     /* MOD_0F71_REG_6 */
11525     { Bad_Opcode },
11526     { "psllw",          { MS, Ib }, 0 },
11527   },
11528   {
11529     /* MOD_0F72_REG_2 */
11530     { Bad_Opcode },
11531     { "psrld",          { MS, Ib }, 0 },
11532   },
11533   {
11534     /* MOD_0F72_REG_4 */
11535     { Bad_Opcode },
11536     { "psrad",          { MS, Ib }, 0 },
11537   },
11538   {
11539     /* MOD_0F72_REG_6 */
11540     { Bad_Opcode },
11541     { "pslld",          { MS, Ib }, 0 },
11542   },
11543   {
11544     /* MOD_0F73_REG_2 */
11545     { Bad_Opcode },
11546     { "psrlq",          { MS, Ib }, 0 },
11547   },
11548   {
11549     /* MOD_0F73_REG_3 */
11550     { Bad_Opcode },
11551     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
11552   },
11553   {
11554     /* MOD_0F73_REG_6 */
11555     { Bad_Opcode },
11556     { "psllq",          { MS, Ib }, 0 },
11557   },
11558   {
11559     /* MOD_0F73_REG_7 */
11560     { Bad_Opcode },
11561     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
11562   },
11563   {
11564     /* MOD_0FAE_REG_0 */
11565     { "fxsave",         { FXSAVE }, 0 },
11566     { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
11567   },
11568   {
11569     /* MOD_0FAE_REG_1 */
11570     { "fxrstor",        { FXSAVE }, 0 },
11571     { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
11572   },
11573   {
11574     /* MOD_0FAE_REG_2 */
11575     { "ldmxcsr",        { Md }, 0 },
11576     { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
11577   },
11578   {
11579     /* MOD_0FAE_REG_3 */
11580     { "stmxcsr",        { Md }, 0 },
11581     { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
11582   },
11583   {
11584     /* MOD_0FAE_REG_4 */
11585     { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_4) },
11586     { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_4) },
11587   },
11588   {
11589     /* MOD_0FAE_REG_5 */
11590     { "xrstor",         { FXSAVE }, 0 },
11591     { RM_TABLE (RM_0FAE_REG_5) },
11592   },
11593   {
11594     /* MOD_0FAE_REG_6 */
11595     { PREFIX_TABLE (PREFIX_0FAE_REG_6) },
11596     { RM_TABLE (RM_0FAE_REG_6) },
11597   },
11598   {
11599     /* MOD_0FAE_REG_7 */
11600     { PREFIX_TABLE (PREFIX_0FAE_REG_7) },
11601     { RM_TABLE (RM_0FAE_REG_7) },
11602   },
11603   {
11604     /* MOD_0FB2 */
11605     { "lssS",           { Gv, Mp }, 0 },
11606   },
11607   {
11608     /* MOD_0FB4 */
11609     { "lfsS",           { Gv, Mp }, 0 },
11610   },
11611   {
11612     /* MOD_0FB5 */
11613     { "lgsS",           { Gv, Mp }, 0 },
11614   },
11615   {
11616     /* MOD_0FC3 */
11617     { PREFIX_TABLE (PREFIX_MOD_0_0FC3) },
11618   },
11619   {
11620     /* MOD_0FC7_REG_3 */
11621     { "xrstors",        { FXSAVE }, 0 },
11622   },
11623   {
11624     /* MOD_0FC7_REG_4 */
11625     { "xsavec",         { FXSAVE }, 0 },
11626   },
11627   {
11628     /* MOD_0FC7_REG_5 */
11629     { "xsaves",         { FXSAVE }, 0 },
11630   },
11631   {
11632     /* MOD_0FC7_REG_6 */
11633     { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6) },
11634     { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6) }
11635   },
11636   {
11637     /* MOD_0FC7_REG_7 */
11638     { "vmptrst",        { Mq }, 0 },
11639     { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7) }
11640   },
11641   {
11642     /* MOD_0FD7 */
11643     { Bad_Opcode },
11644     { "pmovmskb",       { Gdq, MS }, 0 },
11645   },
11646   {
11647     /* MOD_0FE7_PREFIX_2 */
11648     { "movntdq",        { Mx, XM }, 0 },
11649   },
11650   {
11651     /* MOD_0FF0_PREFIX_3 */
11652     { "lddqu",          { XM, M }, 0 },
11653   },
11654   {
11655     /* MOD_0F382A_PREFIX_2 */
11656     { "movntdqa",       { XM, Mx }, 0 },
11657   },
11658   {
11659     /* MOD_62_32BIT */
11660     { "bound{S|}",      { Gv, Ma }, 0 },
11661     { EVEX_TABLE (EVEX_0F) },
11662   },
11663   {
11664     /* MOD_C4_32BIT */
11665     { "lesS",           { Gv, Mp }, 0 },
11666     { VEX_C4_TABLE (VEX_0F) },
11667   },
11668   {
11669     /* MOD_C5_32BIT */
11670     { "ldsS",           { Gv, Mp }, 0 },
11671     { VEX_C5_TABLE (VEX_0F) },
11672   },
11673   {
11674     /* MOD_VEX_0F12_PREFIX_0 */
11675     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
11676     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
11677   },
11678   {
11679     /* MOD_VEX_0F13 */
11680     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
11681   },
11682   {
11683     /* MOD_VEX_0F16_PREFIX_0 */
11684     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
11685     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
11686   },
11687   {
11688     /* MOD_VEX_0F17 */
11689     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
11690   },
11691   {
11692     /* MOD_VEX_0F2B */
11693     { VEX_W_TABLE (VEX_W_0F2B_M_0) },
11694   },
11695   {
11696     /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
11697     { Bad_Opcode },
11698     { "kandw",          { MaskG, MaskVex, MaskR }, 0 },
11699   },
11700   {
11701     /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
11702     { Bad_Opcode },
11703     { "kandq",          { MaskG, MaskVex, MaskR }, 0 },
11704   },
11705   {
11706     /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
11707     { Bad_Opcode },
11708     { "kandb",          { MaskG, MaskVex, MaskR }, 0 },
11709   },
11710   {
11711     /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
11712     { Bad_Opcode },
11713     { "kandd",          { MaskG, MaskVex, MaskR }, 0 },
11714   },
11715   {
11716     /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
11717     { Bad_Opcode },
11718     { "kandnw",         { MaskG, MaskVex, MaskR }, 0 },
11719   },
11720   {
11721     /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
11722     { Bad_Opcode },
11723     { "kandnq",         { MaskG, MaskVex, MaskR }, 0 },
11724   },
11725   {
11726     /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
11727     { Bad_Opcode },
11728     { "kandnb",         { MaskG, MaskVex, MaskR }, 0 },
11729   },
11730   {
11731     /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
11732     { Bad_Opcode },
11733     { "kandnd",         { MaskG, MaskVex, MaskR }, 0 },
11734   },
11735   {
11736     /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
11737     { Bad_Opcode },
11738     { "knotw",          { MaskG, MaskR }, 0 },
11739   },
11740   {
11741     /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
11742     { Bad_Opcode },
11743     { "knotq",          { MaskG, MaskR }, 0 },
11744   },
11745   {
11746     /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
11747     { Bad_Opcode },
11748     { "knotb",          { MaskG, MaskR }, 0 },
11749   },
11750   {
11751     /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
11752     { Bad_Opcode },
11753     { "knotd",          { MaskG, MaskR }, 0 },
11754   },
11755   {
11756     /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
11757     { Bad_Opcode },
11758     { "korw",       { MaskG, MaskVex, MaskR }, 0 },
11759   },
11760   {
11761     /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
11762     { Bad_Opcode },
11763     { "korq",       { MaskG, MaskVex, MaskR }, 0 },
11764   },
11765   {
11766     /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
11767     { Bad_Opcode },
11768     { "korb",       { MaskG, MaskVex, MaskR }, 0 },
11769   },
11770   {
11771     /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
11772     { Bad_Opcode },
11773     { "kord",       { MaskG, MaskVex, MaskR }, 0 },
11774   },
11775  {
11776     /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
11777     { Bad_Opcode },
11778     { "kxnorw",     { MaskG, MaskVex, MaskR }, 0 },
11779   },
11780   {
11781     /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
11782     { Bad_Opcode },
11783     { "kxnorq",     { MaskG, MaskVex, MaskR }, 0 },
11784   },
11785   {
11786     /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
11787     { Bad_Opcode },
11788     { "kxnorb",     { MaskG, MaskVex, MaskR }, 0 },
11789   },
11790   {
11791     /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
11792     { Bad_Opcode },
11793     { "kxnord",     { MaskG, MaskVex, MaskR }, 0 },
11794   },
11795   {
11796     /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
11797     { Bad_Opcode },
11798     { "kxorw",      { MaskG, MaskVex, MaskR }, 0 },
11799   },
11800   {
11801     /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
11802     { Bad_Opcode },
11803     { "kxorq",      { MaskG, MaskVex, MaskR }, 0 },
11804   },
11805   {
11806     /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
11807     { Bad_Opcode },
11808     { "kxorb",      { MaskG, MaskVex, MaskR }, 0 },
11809   },
11810   {
11811     /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
11812     { Bad_Opcode },
11813     { "kxord",      { MaskG, MaskVex, MaskR }, 0 },
11814   },
11815   {
11816     /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
11817     { Bad_Opcode },
11818     { "kaddw",          { MaskG, MaskVex, MaskR }, 0 },
11819   },
11820   {
11821     /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
11822     { Bad_Opcode },
11823     { "kaddq",          { MaskG, MaskVex, MaskR }, 0 },
11824   },
11825   {
11826     /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
11827     { Bad_Opcode },
11828     { "kaddb",          { MaskG, MaskVex, MaskR }, 0 },
11829   },
11830   {
11831     /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
11832     { Bad_Opcode },
11833     { "kaddd",          { MaskG, MaskVex, MaskR }, 0 },
11834   },
11835   {
11836     /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
11837     { Bad_Opcode },
11838     { "kunpckwd",   { MaskG, MaskVex, MaskR }, 0 },
11839   },
11840   {
11841     /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
11842     { Bad_Opcode },
11843     { "kunpckdq",   { MaskG, MaskVex, MaskR }, 0 },
11844   },
11845   {
11846     /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
11847     { Bad_Opcode },
11848     { "kunpckbw",   { MaskG, MaskVex, MaskR }, 0 },
11849   },
11850   {
11851     /* MOD_VEX_0F50 */
11852     { Bad_Opcode },
11853     { VEX_W_TABLE (VEX_W_0F50_M_0) },
11854   },
11855   {
11856     /* MOD_VEX_0F71_REG_2 */
11857     { Bad_Opcode },
11858     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
11859   },
11860   {
11861     /* MOD_VEX_0F71_REG_4 */
11862     { Bad_Opcode },
11863     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
11864   },
11865   {
11866     /* MOD_VEX_0F71_REG_6 */
11867     { Bad_Opcode },
11868     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
11869   },
11870   {
11871     /* MOD_VEX_0F72_REG_2 */
11872     { Bad_Opcode },
11873     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
11874   },
11875   {
11876     /* MOD_VEX_0F72_REG_4 */
11877     { Bad_Opcode },
11878     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
11879   },
11880   {
11881     /* MOD_VEX_0F72_REG_6 */
11882     { Bad_Opcode },
11883     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
11884   },
11885   {
11886     /* MOD_VEX_0F73_REG_2 */
11887     { Bad_Opcode },
11888     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
11889   },
11890   {
11891     /* MOD_VEX_0F73_REG_3 */
11892     { Bad_Opcode },
11893     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
11894   },
11895   {
11896     /* MOD_VEX_0F73_REG_6 */
11897     { Bad_Opcode },
11898     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
11899   },
11900   {
11901     /* MOD_VEX_0F73_REG_7 */
11902     { Bad_Opcode },
11903     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
11904   },
11905   {
11906     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
11907     { "kmovw",          { Ew, MaskG }, 0 },
11908     { Bad_Opcode },
11909   },
11910   {
11911     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
11912     { "kmovq",          { Eq, MaskG }, 0 },
11913     { Bad_Opcode },
11914   },
11915   {
11916     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
11917     { "kmovb",          { Eb, MaskG }, 0 },
11918     { Bad_Opcode },
11919   },
11920   {
11921     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
11922     { "kmovd",          { Ed, MaskG }, 0 },
11923     { Bad_Opcode },
11924   },
11925   {
11926     /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
11927     { Bad_Opcode },
11928     { "kmovw",          { MaskG, Rdq }, 0 },
11929   },
11930   {
11931     /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
11932     { Bad_Opcode },
11933     { "kmovb",          { MaskG, Rdq }, 0 },
11934   },
11935   {
11936     /* MOD_VEX_W_0_0F92_P_3_LEN_0 */
11937     { Bad_Opcode },
11938     { "kmovd",          { MaskG, Rdq }, 0 },
11939   },
11940   {
11941     /* MOD_VEX_W_1_0F92_P_3_LEN_0 */
11942     { Bad_Opcode },
11943     { "kmovq",          { MaskG, Rdq }, 0 },
11944   },
11945   {
11946     /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
11947     { Bad_Opcode },
11948     { "kmovw",          { Gdq, MaskR }, 0 },
11949   },
11950   {
11951     /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
11952     { Bad_Opcode },
11953     { "kmovb",          { Gdq, MaskR }, 0 },
11954   },
11955   {
11956     /* MOD_VEX_W_0_0F93_P_3_LEN_0 */
11957     { Bad_Opcode },
11958     { "kmovd",          { Gdq, MaskR }, 0 },
11959   },
11960   {
11961     /* MOD_VEX_W_1_0F93_P_3_LEN_0 */
11962     { Bad_Opcode },
11963     { "kmovq",          { Gdq, MaskR }, 0 },
11964   },
11965   {
11966     /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
11967     { Bad_Opcode },
11968     { "kortestw", { MaskG, MaskR }, 0 },
11969   },
11970   {
11971     /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
11972     { Bad_Opcode },
11973     { "kortestq", { MaskG, MaskR }, 0 },
11974   },
11975   {
11976     /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
11977     { Bad_Opcode },
11978     { "kortestb", { MaskG, MaskR }, 0 },
11979   },
11980   {
11981     /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
11982     { Bad_Opcode },
11983     { "kortestd", { MaskG, MaskR }, 0 },
11984   },
11985   {
11986     /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
11987     { Bad_Opcode },
11988     { "ktestw", { MaskG, MaskR }, 0 },
11989   },
11990   {
11991     /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
11992     { Bad_Opcode },
11993     { "ktestq", { MaskG, MaskR }, 0 },
11994   },
11995   {
11996     /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
11997     { Bad_Opcode },
11998     { "ktestb", { MaskG, MaskR }, 0 },
11999   },
12000   {
12001     /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
12002     { Bad_Opcode },
12003     { "ktestd", { MaskG, MaskR }, 0 },
12004   },
12005   {
12006     /* MOD_VEX_0FAE_REG_2 */
12007     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
12008   },
12009   {
12010     /* MOD_VEX_0FAE_REG_3 */
12011     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
12012   },
12013   {
12014     /* MOD_VEX_0FD7_PREFIX_2 */
12015     { Bad_Opcode },
12016     { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) },
12017   },
12018   {
12019     /* MOD_VEX_0FE7_PREFIX_2 */
12020     { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) },
12021   },
12022   {
12023     /* MOD_VEX_0FF0_PREFIX_3 */
12024     { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) },
12025   },
12026   {
12027     /* MOD_VEX_0F381A_PREFIX_2 */
12028     { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
12029   },
12030   {
12031     /* MOD_VEX_0F382A_PREFIX_2 */
12032     { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) },
12033   },
12034   {
12035     /* MOD_VEX_0F382C_PREFIX_2 */
12036     { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
12037   },
12038   {
12039     /* MOD_VEX_0F382D_PREFIX_2 */
12040     { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
12041   },
12042   {
12043     /* MOD_VEX_0F382E_PREFIX_2 */
12044     { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
12045   },
12046   {
12047     /* MOD_VEX_0F382F_PREFIX_2 */
12048     { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
12049   },
12050   {
12051     /* MOD_VEX_0F385A_PREFIX_2 */
12052     { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
12053   },
12054   {
12055     /* MOD_VEX_0F388C_PREFIX_2 */
12056     { "vpmaskmov%LW",   { XM, Vex, Mx }, 0 },
12057   },
12058   {
12059     /* MOD_VEX_0F388E_PREFIX_2 */
12060     { "vpmaskmov%LW",   { Mx, Vex, XM }, 0 },
12061   },
12062   {
12063     /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
12064     { Bad_Opcode },
12065     { "kshiftrb",       { MaskG, MaskR, Ib }, 0 },
12066   },
12067   {
12068     /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
12069     { Bad_Opcode },
12070     { "kshiftrw",       { MaskG, MaskR, Ib }, 0 },
12071   },
12072   {
12073     /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
12074     { Bad_Opcode },
12075     { "kshiftrd",       { MaskG, MaskR, Ib }, 0 },
12076   },
12077   {
12078     /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
12079     { Bad_Opcode },
12080     { "kshiftrq",       { MaskG, MaskR, Ib }, 0 },
12081   },
12082   {
12083     /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
12084     { Bad_Opcode },
12085     { "kshiftlb",       { MaskG, MaskR, Ib }, 0 },
12086   },
12087   {
12088     /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
12089     { Bad_Opcode },
12090     { "kshiftlw",       { MaskG, MaskR, Ib }, 0 },
12091   },
12092   {
12093     /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
12094     { Bad_Opcode },
12095     { "kshiftld",       { MaskG, MaskR, Ib }, 0 },
12096   },
12097   {
12098     /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
12099     { Bad_Opcode },
12100     { "kshiftlq",       { MaskG, MaskR, Ib }, 0 },
12101   },
12102 #define NEED_MOD_TABLE
12103 #include "i386-dis-evex.h"
12104 #undef NEED_MOD_TABLE
12105 };
12106
12107 static const struct dis386 rm_table[][8] = {
12108   {
12109     /* RM_C6_REG_7 */
12110     { "xabort",         { Skip_MODRM, Ib }, 0 },
12111   },
12112   {
12113     /* RM_C7_REG_7 */
12114     { "xbeginT",        { Skip_MODRM, Jv }, 0 },
12115   },
12116   {
12117     /* RM_0F01_REG_0 */
12118     { Bad_Opcode },
12119     { "vmcall",         { Skip_MODRM }, 0 },
12120     { "vmlaunch",       { Skip_MODRM }, 0 },
12121     { "vmresume",       { Skip_MODRM }, 0 },
12122     { "vmxoff",         { Skip_MODRM }, 0 },
12123   },
12124   {
12125     /* RM_0F01_REG_1 */
12126     { "monitor",        { { OP_Monitor, 0 } }, 0 },
12127     { "mwait",          { { OP_Mwait, 0 } }, 0 },
12128     { "clac",           { Skip_MODRM }, 0 },
12129     { "stac",           { Skip_MODRM }, 0 },
12130     { Bad_Opcode },
12131     { Bad_Opcode },
12132     { Bad_Opcode },
12133     { "encls",          { Skip_MODRM }, 0 },
12134   },
12135   {
12136     /* RM_0F01_REG_2 */
12137     { "xgetbv",         { Skip_MODRM }, 0 },
12138     { "xsetbv",         { Skip_MODRM }, 0 },
12139     { Bad_Opcode },
12140     { Bad_Opcode },
12141     { "vmfunc",         { Skip_MODRM }, 0 },
12142     { "xend",           { Skip_MODRM }, 0 },
12143     { "xtest",          { Skip_MODRM }, 0 },
12144     { "enclu",          { Skip_MODRM }, 0 },
12145   },
12146   {
12147     /* RM_0F01_REG_3 */
12148     { "vmrun",          { Skip_MODRM }, 0 },
12149     { "vmmcall",        { Skip_MODRM }, 0 },
12150     { "vmload",         { Skip_MODRM }, 0 },
12151     { "vmsave",         { Skip_MODRM }, 0 },
12152     { "stgi",           { Skip_MODRM }, 0 },
12153     { "clgi",           { Skip_MODRM }, 0 },
12154     { "skinit",         { Skip_MODRM }, 0 },
12155     { "invlpga",        { Skip_MODRM }, 0 },
12156   },
12157   {
12158     /* RM_0F01_REG_5 */
12159     { Bad_Opcode },
12160     { Bad_Opcode },
12161     { Bad_Opcode },
12162     { Bad_Opcode },
12163     { Bad_Opcode },
12164     { Bad_Opcode },
12165     { "rdpkru",         { Skip_MODRM }, 0 },
12166     { "wrpkru",         { Skip_MODRM }, 0 },
12167   },
12168   {
12169     /* RM_0F01_REG_7 */
12170     { "swapgs",         { Skip_MODRM }, 0  },
12171     { "rdtscp",         { Skip_MODRM }, 0  },
12172     { "monitorx",       { { OP_Monitor, 0 } }, 0  },
12173     { "mwaitx",         { { OP_Mwaitx,  0 } }, 0  },
12174     { "clzero",         { Skip_MODRM }, 0  },
12175   },
12176   {
12177     /* RM_0FAE_REG_5 */
12178     { "lfence",         { Skip_MODRM }, 0 },
12179   },
12180   {
12181     /* RM_0FAE_REG_6 */
12182     { "mfence",         { Skip_MODRM }, 0 },
12183   },
12184   {
12185     /* RM_0FAE_REG_7 */
12186     { "sfence",         { Skip_MODRM }, 0 },
12187
12188   },
12189 };
12190
12191 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
12192
12193 /* We use the high bit to indicate different name for the same
12194    prefix.  */
12195 #define REP_PREFIX      (0xf3 | 0x100)
12196 #define XACQUIRE_PREFIX (0xf2 | 0x200)
12197 #define XRELEASE_PREFIX (0xf3 | 0x400)
12198 #define BND_PREFIX      (0xf2 | 0x400)
12199
12200 static int
12201 ckprefix (void)
12202 {
12203   int newrex, i, length;
12204   rex = 0;
12205   rex_ignored = 0;
12206   prefixes = 0;
12207   used_prefixes = 0;
12208   rex_used = 0;
12209   last_lock_prefix = -1;
12210   last_repz_prefix = -1;
12211   last_repnz_prefix = -1;
12212   last_data_prefix = -1;
12213   last_addr_prefix = -1;
12214   last_rex_prefix = -1;
12215   last_seg_prefix = -1;
12216   fwait_prefix = -1;
12217   active_seg_prefix = 0;
12218   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12219     all_prefixes[i] = 0;
12220   i = 0;
12221   length = 0;
12222   /* The maximum instruction length is 15bytes.  */
12223   while (length < MAX_CODE_LENGTH - 1)
12224     {
12225       FETCH_DATA (the_info, codep + 1);
12226       newrex = 0;
12227       switch (*codep)
12228         {
12229         /* REX prefixes family.  */
12230         case 0x40:
12231         case 0x41:
12232         case 0x42:
12233         case 0x43:
12234         case 0x44:
12235         case 0x45:
12236         case 0x46:
12237         case 0x47:
12238         case 0x48:
12239         case 0x49:
12240         case 0x4a:
12241         case 0x4b:
12242         case 0x4c:
12243         case 0x4d:
12244         case 0x4e:
12245         case 0x4f:
12246           if (address_mode == mode_64bit)
12247             newrex = *codep;
12248           else
12249             return 1;
12250           last_rex_prefix = i;
12251           break;
12252         case 0xf3:
12253           prefixes |= PREFIX_REPZ;
12254           last_repz_prefix = i;
12255           break;
12256         case 0xf2:
12257           prefixes |= PREFIX_REPNZ;
12258           last_repnz_prefix = i;
12259           break;
12260         case 0xf0:
12261           prefixes |= PREFIX_LOCK;
12262           last_lock_prefix = i;
12263           break;
12264         case 0x2e:
12265           prefixes |= PREFIX_CS;
12266           last_seg_prefix = i;
12267           active_seg_prefix = PREFIX_CS;
12268           break;
12269         case 0x36:
12270           prefixes |= PREFIX_SS;
12271           last_seg_prefix = i;
12272           active_seg_prefix = PREFIX_SS;
12273           break;
12274         case 0x3e:
12275           prefixes |= PREFIX_DS;
12276           last_seg_prefix = i;
12277           active_seg_prefix = PREFIX_DS;
12278           break;
12279         case 0x26:
12280           prefixes |= PREFIX_ES;
12281           last_seg_prefix = i;
12282           active_seg_prefix = PREFIX_ES;
12283           break;
12284         case 0x64:
12285           prefixes |= PREFIX_FS;
12286           last_seg_prefix = i;
12287           active_seg_prefix = PREFIX_FS;
12288           break;
12289         case 0x65:
12290           prefixes |= PREFIX_GS;
12291           last_seg_prefix = i;
12292           active_seg_prefix = PREFIX_GS;
12293           break;
12294         case 0x66:
12295           prefixes |= PREFIX_DATA;
12296           last_data_prefix = i;
12297           break;
12298         case 0x67:
12299           prefixes |= PREFIX_ADDR;
12300           last_addr_prefix = i;
12301           break;
12302         case FWAIT_OPCODE:
12303           /* fwait is really an instruction.  If there are prefixes
12304              before the fwait, they belong to the fwait, *not* to the
12305              following instruction.  */
12306           fwait_prefix = i;
12307           if (prefixes || rex)
12308             {
12309               prefixes |= PREFIX_FWAIT;
12310               codep++;
12311               /* This ensures that the previous REX prefixes are noticed
12312                  as unused prefixes, as in the return case below.  */
12313               rex_used = rex;
12314               return 1;
12315             }
12316           prefixes = PREFIX_FWAIT;
12317           break;
12318         default:
12319           return 1;
12320         }
12321       /* Rex is ignored when followed by another prefix.  */
12322       if (rex)
12323         {
12324           rex_used = rex;
12325           return 1;
12326         }
12327       if (*codep != FWAIT_OPCODE)
12328         all_prefixes[i++] = *codep;
12329       rex = newrex;
12330       codep++;
12331       length++;
12332     }
12333   return 0;
12334 }
12335
12336 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
12337    prefix byte.  */
12338
12339 static const char *
12340 prefix_name (int pref, int sizeflag)
12341 {
12342   static const char *rexes [16] =
12343     {
12344       "rex",            /* 0x40 */
12345       "rex.B",          /* 0x41 */
12346       "rex.X",          /* 0x42 */
12347       "rex.XB",         /* 0x43 */
12348       "rex.R",          /* 0x44 */
12349       "rex.RB",         /* 0x45 */
12350       "rex.RX",         /* 0x46 */
12351       "rex.RXB",        /* 0x47 */
12352       "rex.W",          /* 0x48 */
12353       "rex.WB",         /* 0x49 */
12354       "rex.WX",         /* 0x4a */
12355       "rex.WXB",        /* 0x4b */
12356       "rex.WR",         /* 0x4c */
12357       "rex.WRB",        /* 0x4d */
12358       "rex.WRX",        /* 0x4e */
12359       "rex.WRXB",       /* 0x4f */
12360     };
12361
12362   switch (pref)
12363     {
12364     /* REX prefixes family.  */
12365     case 0x40:
12366     case 0x41:
12367     case 0x42:
12368     case 0x43:
12369     case 0x44:
12370     case 0x45:
12371     case 0x46:
12372     case 0x47:
12373     case 0x48:
12374     case 0x49:
12375     case 0x4a:
12376     case 0x4b:
12377     case 0x4c:
12378     case 0x4d:
12379     case 0x4e:
12380     case 0x4f:
12381       return rexes [pref - 0x40];
12382     case 0xf3:
12383       return "repz";
12384     case 0xf2:
12385       return "repnz";
12386     case 0xf0:
12387       return "lock";
12388     case 0x2e:
12389       return "cs";
12390     case 0x36:
12391       return "ss";
12392     case 0x3e:
12393       return "ds";
12394     case 0x26:
12395       return "es";
12396     case 0x64:
12397       return "fs";
12398     case 0x65:
12399       return "gs";
12400     case 0x66:
12401       return (sizeflag & DFLAG) ? "data16" : "data32";
12402     case 0x67:
12403       if (address_mode == mode_64bit)
12404         return (sizeflag & AFLAG) ? "addr32" : "addr64";
12405       else
12406         return (sizeflag & AFLAG) ? "addr16" : "addr32";
12407     case FWAIT_OPCODE:
12408       return "fwait";
12409     case REP_PREFIX:
12410       return "rep";
12411     case XACQUIRE_PREFIX:
12412       return "xacquire";
12413     case XRELEASE_PREFIX:
12414       return "xrelease";
12415     case BND_PREFIX:
12416       return "bnd";
12417     default:
12418       return NULL;
12419     }
12420 }
12421
12422 static char op_out[MAX_OPERANDS][100];
12423 static int op_ad, op_index[MAX_OPERANDS];
12424 static int two_source_ops;
12425 static bfd_vma op_address[MAX_OPERANDS];
12426 static bfd_vma op_riprel[MAX_OPERANDS];
12427 static bfd_vma start_pc;
12428
12429 /*
12430  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
12431  *   (see topic "Redundant prefixes" in the "Differences from 8086"
12432  *   section of the "Virtual 8086 Mode" chapter.)
12433  * 'pc' should be the address of this instruction, it will
12434  *   be used to print the target address if this is a relative jump or call
12435  * The function returns the length of this instruction in bytes.
12436  */
12437
12438 static char intel_syntax;
12439 static char intel_mnemonic = !SYSV386_COMPAT;
12440 static char open_char;
12441 static char close_char;
12442 static char separator_char;
12443 static char scale_char;
12444
12445 enum x86_64_isa
12446 {
12447   amd64 = 0,
12448   intel64
12449 };
12450
12451 static enum x86_64_isa isa64;
12452
12453 /* Here for backwards compatibility.  When gdb stops using
12454    print_insn_i386_att and print_insn_i386_intel these functions can
12455    disappear, and print_insn_i386 be merged into print_insn.  */
12456 int
12457 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
12458 {
12459   intel_syntax = 0;
12460
12461   return print_insn (pc, info);
12462 }
12463
12464 int
12465 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
12466 {
12467   intel_syntax = 1;
12468
12469   return print_insn (pc, info);
12470 }
12471
12472 int
12473 print_insn_i386 (bfd_vma pc, disassemble_info *info)
12474 {
12475   intel_syntax = -1;
12476
12477   return print_insn (pc, info);
12478 }
12479
12480 void
12481 print_i386_disassembler_options (FILE *stream)
12482 {
12483   fprintf (stream, _("\n\
12484 The following i386/x86-64 specific disassembler options are supported for use\n\
12485 with the -M switch (multiple options should be separated by commas):\n"));
12486
12487   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
12488   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
12489   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
12490   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
12491   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
12492   fprintf (stream, _("  att-mnemonic\n"
12493                      "              Display instruction in AT&T mnemonic\n"));
12494   fprintf (stream, _("  intel-mnemonic\n"
12495                      "              Display instruction in Intel mnemonic\n"));
12496   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
12497   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
12498   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
12499   fprintf (stream, _("  data32      Assume 32bit data size\n"));
12500   fprintf (stream, _("  data16      Assume 16bit data size\n"));
12501   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
12502   fprintf (stream, _("  amd64       Display instruction in AMD64 ISA\n"));
12503   fprintf (stream, _("  intel64     Display instruction in Intel64 ISA\n"));
12504 }
12505
12506 /* Bad opcode.  */
12507 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
12508
12509 /* Get a pointer to struct dis386 with a valid name.  */
12510
12511 static const struct dis386 *
12512 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
12513 {
12514   int vindex, vex_table_index;
12515
12516   if (dp->name != NULL)
12517     return dp;
12518
12519   switch (dp->op[0].bytemode)
12520     {
12521     case USE_REG_TABLE:
12522       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
12523       break;
12524
12525     case USE_MOD_TABLE:
12526       vindex = modrm.mod == 0x3 ? 1 : 0;
12527       dp = &mod_table[dp->op[1].bytemode][vindex];
12528       break;
12529
12530     case USE_RM_TABLE:
12531       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
12532       break;
12533
12534     case USE_PREFIX_TABLE:
12535       if (need_vex)
12536         {
12537           /* The prefix in VEX is implicit.  */
12538           switch (vex.prefix)
12539             {
12540             case 0:
12541               vindex = 0;
12542               break;
12543             case REPE_PREFIX_OPCODE:
12544               vindex = 1;
12545               break;
12546             case DATA_PREFIX_OPCODE:
12547               vindex = 2;
12548               break;
12549             case REPNE_PREFIX_OPCODE:
12550               vindex = 3;
12551               break;
12552             default:
12553               abort ();
12554               break;
12555             }
12556         }
12557       else
12558         {
12559           int last_prefix = -1;
12560           int prefix = 0;
12561           vindex = 0;
12562           /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
12563              When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
12564              last one wins.  */
12565           if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
12566             {
12567               if (last_repz_prefix > last_repnz_prefix)
12568                 {
12569                   vindex = 1;
12570                   prefix = PREFIX_REPZ;
12571                   last_prefix = last_repz_prefix;
12572                 }
12573               else
12574                 {
12575                   vindex = 3;
12576                   prefix = PREFIX_REPNZ;
12577                   last_prefix = last_repnz_prefix;
12578                 }
12579
12580               /* Check if prefix should be ignored.  */
12581               if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
12582                      & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
12583                    & prefix) != 0)
12584                 vindex = 0;
12585             }
12586
12587           if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
12588             {
12589               vindex = 2;
12590               prefix = PREFIX_DATA;
12591               last_prefix = last_data_prefix;
12592             }
12593
12594           if (vindex != 0)
12595             {
12596               used_prefixes |= prefix;
12597               all_prefixes[last_prefix] = 0;
12598             }
12599         }
12600       dp = &prefix_table[dp->op[1].bytemode][vindex];
12601       break;
12602
12603     case USE_X86_64_TABLE:
12604       vindex = address_mode == mode_64bit ? 1 : 0;
12605       dp = &x86_64_table[dp->op[1].bytemode][vindex];
12606       break;
12607
12608     case USE_3BYTE_TABLE:
12609       FETCH_DATA (info, codep + 2);
12610       vindex = *codep++;
12611       dp = &three_byte_table[dp->op[1].bytemode][vindex];
12612       end_codep = codep;
12613       modrm.mod = (*codep >> 6) & 3;
12614       modrm.reg = (*codep >> 3) & 7;
12615       modrm.rm = *codep & 7;
12616       break;
12617
12618     case USE_VEX_LEN_TABLE:
12619       if (!need_vex)
12620         abort ();
12621
12622       switch (vex.length)
12623         {
12624         case 128:
12625           vindex = 0;
12626           break;
12627         case 256:
12628           vindex = 1;
12629           break;
12630         default:
12631           abort ();
12632           break;
12633         }
12634
12635       dp = &vex_len_table[dp->op[1].bytemode][vindex];
12636       break;
12637
12638     case USE_XOP_8F_TABLE:
12639       FETCH_DATA (info, codep + 3);
12640       /* All bits in the REX prefix are ignored.  */
12641       rex_ignored = rex;
12642       rex = ~(*codep >> 5) & 0x7;
12643
12644       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
12645       switch ((*codep & 0x1f))
12646         {
12647         default:
12648           dp = &bad_opcode;
12649           return dp;
12650         case 0x8:
12651           vex_table_index = XOP_08;
12652           break;
12653         case 0x9:
12654           vex_table_index = XOP_09;
12655           break;
12656         case 0xa:
12657           vex_table_index = XOP_0A;
12658           break;
12659         }
12660       codep++;
12661       vex.w = *codep & 0x80;
12662       if (vex.w && address_mode == mode_64bit)
12663         rex |= REX_W;
12664
12665       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12666       if (address_mode != mode_64bit)
12667         {
12668           /* In 16/32-bit mode REX_B is silently ignored.  */
12669           rex &= ~REX_B;
12670           if (vex.register_specifier > 0x7)
12671             {
12672               dp = &bad_opcode;
12673               return dp;
12674             }
12675         }
12676
12677       vex.length = (*codep & 0x4) ? 256 : 128;
12678       switch ((*codep & 0x3))
12679         {
12680         case 0:
12681           vex.prefix = 0;
12682           break;
12683         case 1:
12684           vex.prefix = DATA_PREFIX_OPCODE;
12685           break;
12686         case 2:
12687           vex.prefix = REPE_PREFIX_OPCODE;
12688           break;
12689         case 3:
12690           vex.prefix = REPNE_PREFIX_OPCODE;
12691           break;
12692         }
12693       need_vex = 1;
12694       need_vex_reg = 1;
12695       codep++;
12696       vindex = *codep++;
12697       dp = &xop_table[vex_table_index][vindex];
12698
12699       end_codep = codep;
12700       FETCH_DATA (info, codep + 1);
12701       modrm.mod = (*codep >> 6) & 3;
12702       modrm.reg = (*codep >> 3) & 7;
12703       modrm.rm = *codep & 7;
12704       break;
12705
12706     case USE_VEX_C4_TABLE:
12707       /* VEX prefix.  */
12708       FETCH_DATA (info, codep + 3);
12709       /* All bits in the REX prefix are ignored.  */
12710       rex_ignored = rex;
12711       rex = ~(*codep >> 5) & 0x7;
12712       switch ((*codep & 0x1f))
12713         {
12714         default:
12715           dp = &bad_opcode;
12716           return dp;
12717         case 0x1:
12718           vex_table_index = VEX_0F;
12719           break;
12720         case 0x2:
12721           vex_table_index = VEX_0F38;
12722           break;
12723         case 0x3:
12724           vex_table_index = VEX_0F3A;
12725           break;
12726         }
12727       codep++;
12728       vex.w = *codep & 0x80;
12729       if (address_mode == mode_64bit)
12730         {
12731           if (vex.w)
12732             rex |= REX_W;
12733           vex.register_specifier = (~(*codep >> 3)) & 0xf;
12734         }
12735       else
12736         {
12737           /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
12738              is ignored, other REX bits are 0 and the highest bit in
12739              VEX.vvvv is also ignored.  */
12740           rex = 0;
12741           vex.register_specifier = (~(*codep >> 3)) & 0x7;
12742         }
12743       vex.length = (*codep & 0x4) ? 256 : 128;
12744       switch ((*codep & 0x3))
12745         {
12746         case 0:
12747           vex.prefix = 0;
12748           break;
12749         case 1:
12750           vex.prefix = DATA_PREFIX_OPCODE;
12751           break;
12752         case 2:
12753           vex.prefix = REPE_PREFIX_OPCODE;
12754           break;
12755         case 3:
12756           vex.prefix = REPNE_PREFIX_OPCODE;
12757           break;
12758         }
12759       need_vex = 1;
12760       need_vex_reg = 1;
12761       codep++;
12762       vindex = *codep++;
12763       dp = &vex_table[vex_table_index][vindex];
12764       end_codep = codep;
12765       /* There is no MODRM byte for VEX0F 77.  */
12766       if (vex_table_index != VEX_0F || vindex != 0x77)
12767         {
12768           FETCH_DATA (info, codep + 1);
12769           modrm.mod = (*codep >> 6) & 3;
12770           modrm.reg = (*codep >> 3) & 7;
12771           modrm.rm = *codep & 7;
12772         }
12773       break;
12774
12775     case USE_VEX_C5_TABLE:
12776       /* VEX prefix.  */
12777       FETCH_DATA (info, codep + 2);
12778       /* All bits in the REX prefix are ignored.  */
12779       rex_ignored = rex;
12780       rex = (*codep & 0x80) ? 0 : REX_R;
12781
12782       /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
12783          VEX.vvvv is 1.  */
12784       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12785       vex.w = 0;
12786       vex.length = (*codep & 0x4) ? 256 : 128;
12787       switch ((*codep & 0x3))
12788         {
12789         case 0:
12790           vex.prefix = 0;
12791           break;
12792         case 1:
12793           vex.prefix = DATA_PREFIX_OPCODE;
12794           break;
12795         case 2:
12796           vex.prefix = REPE_PREFIX_OPCODE;
12797           break;
12798         case 3:
12799           vex.prefix = REPNE_PREFIX_OPCODE;
12800           break;
12801         }
12802       need_vex = 1;
12803       need_vex_reg = 1;
12804       codep++;
12805       vindex = *codep++;
12806       dp = &vex_table[dp->op[1].bytemode][vindex];
12807       end_codep = codep;
12808       /* There is no MODRM byte for VEX 77.  */
12809       if (vindex != 0x77)
12810         {
12811           FETCH_DATA (info, codep + 1);
12812           modrm.mod = (*codep >> 6) & 3;
12813           modrm.reg = (*codep >> 3) & 7;
12814           modrm.rm = *codep & 7;
12815         }
12816       break;
12817
12818     case USE_VEX_W_TABLE:
12819       if (!need_vex)
12820         abort ();
12821
12822       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
12823       break;
12824
12825     case USE_EVEX_TABLE:
12826       two_source_ops = 0;
12827       /* EVEX prefix.  */
12828       vex.evex = 1;
12829       FETCH_DATA (info, codep + 4);
12830       /* All bits in the REX prefix are ignored.  */
12831       rex_ignored = rex;
12832       /* The first byte after 0x62.  */
12833       rex = ~(*codep >> 5) & 0x7;
12834       vex.r = *codep & 0x10;
12835       switch ((*codep & 0xf))
12836         {
12837         default:
12838           return &bad_opcode;
12839         case 0x1:
12840           vex_table_index = EVEX_0F;
12841           break;
12842         case 0x2:
12843           vex_table_index = EVEX_0F38;
12844           break;
12845         case 0x3:
12846           vex_table_index = EVEX_0F3A;
12847           break;
12848         }
12849
12850       /* The second byte after 0x62.  */
12851       codep++;
12852       vex.w = *codep & 0x80;
12853       if (vex.w && address_mode == mode_64bit)
12854         rex |= REX_W;
12855
12856       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12857       if (address_mode != mode_64bit)
12858         {
12859           /* In 16/32-bit mode silently ignore following bits.  */
12860           rex &= ~REX_B;
12861           vex.r = 1;
12862           vex.v = 1;
12863           vex.register_specifier &= 0x7;
12864         }
12865
12866       /* The U bit.  */
12867       if (!(*codep & 0x4))
12868         return &bad_opcode;
12869
12870       switch ((*codep & 0x3))
12871         {
12872         case 0:
12873           vex.prefix = 0;
12874           break;
12875         case 1:
12876           vex.prefix = DATA_PREFIX_OPCODE;
12877           break;
12878         case 2:
12879           vex.prefix = REPE_PREFIX_OPCODE;
12880           break;
12881         case 3:
12882           vex.prefix = REPNE_PREFIX_OPCODE;
12883           break;
12884         }
12885
12886       /* The third byte after 0x62.  */
12887       codep++;
12888
12889       /* Remember the static rounding bits.  */
12890       vex.ll = (*codep >> 5) & 3;
12891       vex.b = (*codep & 0x10) != 0;
12892
12893       vex.v = *codep & 0x8;
12894       vex.mask_register_specifier = *codep & 0x7;
12895       vex.zeroing = *codep & 0x80;
12896
12897       need_vex = 1;
12898       need_vex_reg = 1;
12899       codep++;
12900       vindex = *codep++;
12901       dp = &evex_table[vex_table_index][vindex];
12902       end_codep = codep;
12903       FETCH_DATA (info, codep + 1);
12904       modrm.mod = (*codep >> 6) & 3;
12905       modrm.reg = (*codep >> 3) & 7;
12906       modrm.rm = *codep & 7;
12907
12908       /* Set vector length.  */
12909       if (modrm.mod == 3 && vex.b)
12910         vex.length = 512;
12911       else
12912         {
12913           switch (vex.ll)
12914             {
12915             case 0x0:
12916               vex.length = 128;
12917               break;
12918             case 0x1:
12919               vex.length = 256;
12920               break;
12921             case 0x2:
12922               vex.length = 512;
12923               break;
12924             default:
12925               return &bad_opcode;
12926             }
12927         }
12928       break;
12929
12930     case 0:
12931       dp = &bad_opcode;
12932       break;
12933
12934     default:
12935       abort ();
12936     }
12937
12938   if (dp->name != NULL)
12939     return dp;
12940   else
12941     return get_valid_dis386 (dp, info);
12942 }
12943
12944 static void
12945 get_sib (disassemble_info *info, int sizeflag)
12946 {
12947   /* If modrm.mod == 3, operand must be register.  */
12948   if (need_modrm
12949       && ((sizeflag & AFLAG) || address_mode == mode_64bit)
12950       && modrm.mod != 3
12951       && modrm.rm == 4)
12952     {
12953       FETCH_DATA (info, codep + 2);
12954       sib.index = (codep [1] >> 3) & 7;
12955       sib.scale = (codep [1] >> 6) & 3;
12956       sib.base = codep [1] & 7;
12957     }
12958 }
12959
12960 static int
12961 print_insn (bfd_vma pc, disassemble_info *info)
12962 {
12963   const struct dis386 *dp;
12964   int i;
12965   char *op_txt[MAX_OPERANDS];
12966   int needcomma;
12967   int sizeflag, orig_sizeflag;
12968   const char *p;
12969   struct dis_private priv;
12970   int prefix_length;
12971
12972   priv.orig_sizeflag = AFLAG | DFLAG;
12973   if ((info->mach & bfd_mach_i386_i386) != 0)
12974     address_mode = mode_32bit;
12975   else if (info->mach == bfd_mach_i386_i8086)
12976     {
12977       address_mode = mode_16bit;
12978       priv.orig_sizeflag = 0;
12979     }
12980   else
12981     address_mode = mode_64bit;
12982
12983   if (intel_syntax == (char) -1)
12984     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
12985
12986   for (p = info->disassembler_options; p != NULL; )
12987     {
12988       if (CONST_STRNEQ (p, "amd64"))
12989         isa64 = amd64;
12990       else if (CONST_STRNEQ (p, "intel64"))
12991         isa64 = intel64;
12992       else if (CONST_STRNEQ (p, "x86-64"))
12993         {
12994           address_mode = mode_64bit;
12995           priv.orig_sizeflag = AFLAG | DFLAG;
12996         }
12997       else if (CONST_STRNEQ (p, "i386"))
12998         {
12999           address_mode = mode_32bit;
13000           priv.orig_sizeflag = AFLAG | DFLAG;
13001         }
13002       else if (CONST_STRNEQ (p, "i8086"))
13003         {
13004           address_mode = mode_16bit;
13005           priv.orig_sizeflag = 0;
13006         }
13007       else if (CONST_STRNEQ (p, "intel"))
13008         {
13009           intel_syntax = 1;
13010           if (CONST_STRNEQ (p + 5, "-mnemonic"))
13011             intel_mnemonic = 1;
13012         }
13013       else if (CONST_STRNEQ (p, "att"))
13014         {
13015           intel_syntax = 0;
13016           if (CONST_STRNEQ (p + 3, "-mnemonic"))
13017             intel_mnemonic = 0;
13018         }
13019       else if (CONST_STRNEQ (p, "addr"))
13020         {
13021           if (address_mode == mode_64bit)
13022             {
13023               if (p[4] == '3' && p[5] == '2')
13024                 priv.orig_sizeflag &= ~AFLAG;
13025               else if (p[4] == '6' && p[5] == '4')
13026                 priv.orig_sizeflag |= AFLAG;
13027             }
13028           else
13029             {
13030               if (p[4] == '1' && p[5] == '6')
13031                 priv.orig_sizeflag &= ~AFLAG;
13032               else if (p[4] == '3' && p[5] == '2')
13033                 priv.orig_sizeflag |= AFLAG;
13034             }
13035         }
13036       else if (CONST_STRNEQ (p, "data"))
13037         {
13038           if (p[4] == '1' && p[5] == '6')
13039             priv.orig_sizeflag &= ~DFLAG;
13040           else if (p[4] == '3' && p[5] == '2')
13041             priv.orig_sizeflag |= DFLAG;
13042         }
13043       else if (CONST_STRNEQ (p, "suffix"))
13044         priv.orig_sizeflag |= SUFFIX_ALWAYS;
13045
13046       p = strchr (p, ',');
13047       if (p != NULL)
13048         p++;
13049     }
13050
13051   if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
13052     {
13053       (*info->fprintf_func) (info->stream,
13054                              _("64-bit address is disabled"));
13055       return -1;
13056     }
13057
13058   if (intel_syntax)
13059     {
13060       names64 = intel_names64;
13061       names32 = intel_names32;
13062       names16 = intel_names16;
13063       names8 = intel_names8;
13064       names8rex = intel_names8rex;
13065       names_seg = intel_names_seg;
13066       names_mm = intel_names_mm;
13067       names_bnd = intel_names_bnd;
13068       names_xmm = intel_names_xmm;
13069       names_ymm = intel_names_ymm;
13070       names_zmm = intel_names_zmm;
13071       index64 = intel_index64;
13072       index32 = intel_index32;
13073       names_mask = intel_names_mask;
13074       index16 = intel_index16;
13075       open_char = '[';
13076       close_char = ']';
13077       separator_char = '+';
13078       scale_char = '*';
13079     }
13080   else
13081     {
13082       names64 = att_names64;
13083       names32 = att_names32;
13084       names16 = att_names16;
13085       names8 = att_names8;
13086       names8rex = att_names8rex;
13087       names_seg = att_names_seg;
13088       names_mm = att_names_mm;
13089       names_bnd = att_names_bnd;
13090       names_xmm = att_names_xmm;
13091       names_ymm = att_names_ymm;
13092       names_zmm = att_names_zmm;
13093       index64 = att_index64;
13094       index32 = att_index32;
13095       names_mask = att_names_mask;
13096       index16 = att_index16;
13097       open_char = '(';
13098       close_char =  ')';
13099       separator_char = ',';
13100       scale_char = ',';
13101     }
13102
13103   /* The output looks better if we put 7 bytes on a line, since that
13104      puts most long word instructions on a single line.  Use 8 bytes
13105      for Intel L1OM.  */
13106   if ((info->mach & bfd_mach_l1om) != 0)
13107     info->bytes_per_line = 8;
13108   else
13109     info->bytes_per_line = 7;
13110
13111   info->private_data = &priv;
13112   priv.max_fetched = priv.the_buffer;
13113   priv.insn_start = pc;
13114
13115   obuf[0] = 0;
13116   for (i = 0; i < MAX_OPERANDS; ++i)
13117     {
13118       op_out[i][0] = 0;
13119       op_index[i] = -1;
13120     }
13121
13122   the_info = info;
13123   start_pc = pc;
13124   start_codep = priv.the_buffer;
13125   codep = priv.the_buffer;
13126
13127   if (OPCODES_SIGSETJMP (priv.bailout) != 0)
13128     {
13129       const char *name;
13130
13131       /* Getting here means we tried for data but didn't get it.  That
13132          means we have an incomplete instruction of some sort.  Just
13133          print the first byte as a prefix or a .byte pseudo-op.  */
13134       if (codep > priv.the_buffer)
13135         {
13136           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
13137           if (name != NULL)
13138             (*info->fprintf_func) (info->stream, "%s", name);
13139           else
13140             {
13141               /* Just print the first byte as a .byte instruction.  */
13142               (*info->fprintf_func) (info->stream, ".byte 0x%x",
13143                                      (unsigned int) priv.the_buffer[0]);
13144             }
13145
13146           return 1;
13147         }
13148
13149       return -1;
13150     }
13151
13152   obufp = obuf;
13153   sizeflag = priv.orig_sizeflag;
13154
13155   if (!ckprefix () || rex_used)
13156     {
13157       /* Too many prefixes or unused REX prefixes.  */
13158       for (i = 0;
13159            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
13160            i++)
13161         (*info->fprintf_func) (info->stream, "%s%s",
13162                                i == 0 ? "" : " ",
13163                                prefix_name (all_prefixes[i], sizeflag));
13164       return i;
13165     }
13166
13167   insn_codep = codep;
13168
13169   FETCH_DATA (info, codep + 1);
13170   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
13171
13172   if (((prefixes & PREFIX_FWAIT)
13173        && ((*codep < 0xd8) || (*codep > 0xdf))))
13174     {
13175       /* Handle prefixes before fwait.  */
13176       for (i = 0; i < fwait_prefix && all_prefixes[i];
13177            i++)
13178         (*info->fprintf_func) (info->stream, "%s ",
13179                                prefix_name (all_prefixes[i], sizeflag));
13180       (*info->fprintf_func) (info->stream, "fwait");
13181       return i + 1;
13182     }
13183
13184   if (*codep == 0x0f)
13185     {
13186       unsigned char threebyte;
13187
13188       codep++;
13189       FETCH_DATA (info, codep + 1);
13190       threebyte = *codep;
13191       dp = &dis386_twobyte[threebyte];
13192       need_modrm = twobyte_has_modrm[*codep];
13193       codep++;
13194     }
13195   else
13196     {
13197       dp = &dis386[*codep];
13198       need_modrm = onebyte_has_modrm[*codep];
13199       codep++;
13200     }
13201
13202   /* Save sizeflag for printing the extra prefixes later before updating
13203      it for mnemonic and operand processing.  The prefix names depend
13204      only on the address mode.  */
13205   orig_sizeflag = sizeflag;
13206   if (prefixes & PREFIX_ADDR)
13207     sizeflag ^= AFLAG;
13208   if ((prefixes & PREFIX_DATA))
13209     sizeflag ^= DFLAG;
13210
13211   end_codep = codep;
13212   if (need_modrm)
13213     {
13214       FETCH_DATA (info, codep + 1);
13215       modrm.mod = (*codep >> 6) & 3;
13216       modrm.reg = (*codep >> 3) & 7;
13217       modrm.rm = *codep & 7;
13218     }
13219
13220   need_vex = 0;
13221   need_vex_reg = 0;
13222   vex_w_done = 0;
13223   vex.evex = 0;
13224
13225   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
13226     {
13227       get_sib (info, sizeflag);
13228       dofloat (sizeflag);
13229     }
13230   else
13231     {
13232       dp = get_valid_dis386 (dp, info);
13233       if (dp != NULL && putop (dp->name, sizeflag) == 0)
13234         {
13235           get_sib (info, sizeflag);
13236           for (i = 0; i < MAX_OPERANDS; ++i)
13237             {
13238               obufp = op_out[i];
13239               op_ad = MAX_OPERANDS - 1 - i;
13240               if (dp->op[i].rtn)
13241                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
13242               /* For EVEX instruction after the last operand masking
13243                  should be printed.  */
13244               if (i == 0 && vex.evex)
13245                 {
13246                   /* Don't print {%k0}.  */
13247                   if (vex.mask_register_specifier)
13248                     {
13249                       oappend ("{");
13250                       oappend (names_mask[vex.mask_register_specifier]);
13251                       oappend ("}");
13252                     }
13253                   if (vex.zeroing)
13254                     oappend ("{z}");
13255                 }
13256             }
13257         }
13258     }
13259
13260   /* Check if the REX prefix is used.  */
13261   if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)
13262     all_prefixes[last_rex_prefix] = 0;
13263
13264   /* Check if the SEG prefix is used.  */
13265   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
13266                    | PREFIX_FS | PREFIX_GS)) != 0
13267       && (used_prefixes & active_seg_prefix) != 0)
13268     all_prefixes[last_seg_prefix] = 0;
13269
13270   /* Check if the ADDR prefix is used.  */
13271   if ((prefixes & PREFIX_ADDR) != 0
13272       && (used_prefixes & PREFIX_ADDR) != 0)
13273     all_prefixes[last_addr_prefix] = 0;
13274
13275   /* Check if the DATA prefix is used.  */
13276   if ((prefixes & PREFIX_DATA) != 0
13277       && (used_prefixes & PREFIX_DATA) != 0)
13278     all_prefixes[last_data_prefix] = 0;
13279
13280   /* Print the extra prefixes.  */
13281   prefix_length = 0;
13282   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
13283     if (all_prefixes[i])
13284       {
13285         const char *name;
13286         name = prefix_name (all_prefixes[i], orig_sizeflag);
13287         if (name == NULL)
13288           abort ();
13289         prefix_length += strlen (name) + 1;
13290         (*info->fprintf_func) (info->stream, "%s ", name);
13291       }
13292
13293   /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
13294      unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
13295      used by putop and MMX/SSE operand and may be overriden by the
13296      PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
13297      separately.  */
13298   if (dp->prefix_requirement == PREFIX_OPCODE
13299       && dp != &bad_opcode
13300       && (((prefixes
13301             & (PREFIX_REPZ | PREFIX_REPNZ)) != 0
13302            && (used_prefixes
13303                & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
13304           || ((((prefixes
13305                  & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
13306                 == PREFIX_DATA)
13307                && (used_prefixes & PREFIX_DATA) == 0))))
13308     {
13309       (*info->fprintf_func) (info->stream, "(bad)");
13310       return end_codep - priv.the_buffer;
13311     }
13312
13313   /* Check maximum code length.  */
13314   if ((codep - start_codep) > MAX_CODE_LENGTH)
13315     {
13316       (*info->fprintf_func) (info->stream, "(bad)");
13317       return MAX_CODE_LENGTH;
13318     }
13319
13320   obufp = mnemonicendp;
13321   for (i = strlen (obuf) + prefix_length; i < 6; i++)
13322     oappend (" ");
13323   oappend (" ");
13324   (*info->fprintf_func) (info->stream, "%s", obuf);
13325
13326   /* The enter and bound instructions are printed with operands in the same
13327      order as the intel book; everything else is printed in reverse order.  */
13328   if (intel_syntax || two_source_ops)
13329     {
13330       bfd_vma riprel;
13331
13332       for (i = 0; i < MAX_OPERANDS; ++i)
13333         op_txt[i] = op_out[i];
13334
13335       if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
13336           && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
13337         {
13338           op_txt[2] = op_out[3];
13339           op_txt[3] = op_out[2];
13340         }
13341
13342       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
13343         {
13344           op_ad = op_index[i];
13345           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
13346           op_index[MAX_OPERANDS - 1 - i] = op_ad;
13347           riprel = op_riprel[i];
13348           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
13349           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
13350         }
13351     }
13352   else
13353     {
13354       for (i = 0; i < MAX_OPERANDS; ++i)
13355         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
13356     }
13357
13358   needcomma = 0;
13359   for (i = 0; i < MAX_OPERANDS; ++i)
13360     if (*op_txt[i])
13361       {
13362         if (needcomma)
13363           (*info->fprintf_func) (info->stream, ",");
13364         if (op_index[i] != -1 && !op_riprel[i])
13365           (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
13366         else
13367           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
13368         needcomma = 1;
13369       }
13370
13371   for (i = 0; i < MAX_OPERANDS; i++)
13372     if (op_index[i] != -1 && op_riprel[i])
13373       {
13374         (*info->fprintf_func) (info->stream, "        # ");
13375         (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
13376                                                 + op_address[op_index[i]]), info);
13377         break;
13378       }
13379   return codep - priv.the_buffer;
13380 }
13381
13382 static const char *float_mem[] = {
13383   /* d8 */
13384   "fadd{s|}",
13385   "fmul{s|}",
13386   "fcom{s|}",
13387   "fcomp{s|}",
13388   "fsub{s|}",
13389   "fsubr{s|}",
13390   "fdiv{s|}",
13391   "fdivr{s|}",
13392   /* d9 */
13393   "fld{s|}",
13394   "(bad)",
13395   "fst{s|}",
13396   "fstp{s|}",
13397   "fldenvIC",
13398   "fldcw",
13399   "fNstenvIC",
13400   "fNstcw",
13401   /* da */
13402   "fiadd{l|}",
13403   "fimul{l|}",
13404   "ficom{l|}",
13405   "ficomp{l|}",
13406   "fisub{l|}",
13407   "fisubr{l|}",
13408   "fidiv{l|}",
13409   "fidivr{l|}",
13410   /* db */
13411   "fild{l|}",
13412   "fisttp{l|}",
13413   "fist{l|}",
13414   "fistp{l|}",
13415   "(bad)",
13416   "fld{t||t|}",
13417   "(bad)",
13418   "fstp{t||t|}",
13419   /* dc */
13420   "fadd{l|}",
13421   "fmul{l|}",
13422   "fcom{l|}",
13423   "fcomp{l|}",
13424   "fsub{l|}",
13425   "fsubr{l|}",
13426   "fdiv{l|}",
13427   "fdivr{l|}",
13428   /* dd */
13429   "fld{l|}",
13430   "fisttp{ll|}",
13431   "fst{l||}",
13432   "fstp{l|}",
13433   "frstorIC",
13434   "(bad)",
13435   "fNsaveIC",
13436   "fNstsw",
13437   /* de */
13438   "fiadd",
13439   "fimul",
13440   "ficom",
13441   "ficomp",
13442   "fisub",
13443   "fisubr",
13444   "fidiv",
13445   "fidivr",
13446   /* df */
13447   "fild",
13448   "fisttp",
13449   "fist",
13450   "fistp",
13451   "fbld",
13452   "fild{ll|}",
13453   "fbstp",
13454   "fistp{ll|}",
13455 };
13456
13457 static const unsigned char float_mem_mode[] = {
13458   /* d8 */
13459   d_mode,
13460   d_mode,
13461   d_mode,
13462   d_mode,
13463   d_mode,
13464   d_mode,
13465   d_mode,
13466   d_mode,
13467   /* d9 */
13468   d_mode,
13469   0,
13470   d_mode,
13471   d_mode,
13472   0,
13473   w_mode,
13474   0,
13475   w_mode,
13476   /* da */
13477   d_mode,
13478   d_mode,
13479   d_mode,
13480   d_mode,
13481   d_mode,
13482   d_mode,
13483   d_mode,
13484   d_mode,
13485   /* db */
13486   d_mode,
13487   d_mode,
13488   d_mode,
13489   d_mode,
13490   0,
13491   t_mode,
13492   0,
13493   t_mode,
13494   /* dc */
13495   q_mode,
13496   q_mode,
13497   q_mode,
13498   q_mode,
13499   q_mode,
13500   q_mode,
13501   q_mode,
13502   q_mode,
13503   /* dd */
13504   q_mode,
13505   q_mode,
13506   q_mode,
13507   q_mode,
13508   0,
13509   0,
13510   0,
13511   w_mode,
13512   /* de */
13513   w_mode,
13514   w_mode,
13515   w_mode,
13516   w_mode,
13517   w_mode,
13518   w_mode,
13519   w_mode,
13520   w_mode,
13521   /* df */
13522   w_mode,
13523   w_mode,
13524   w_mode,
13525   w_mode,
13526   t_mode,
13527   q_mode,
13528   t_mode,
13529   q_mode
13530 };
13531
13532 #define ST { OP_ST, 0 }
13533 #define STi { OP_STi, 0 }
13534
13535 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
13536 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
13537 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
13538 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
13539 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
13540 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
13541 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
13542 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
13543 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
13544
13545 static const struct dis386 float_reg[][8] = {
13546   /* d8 */
13547   {
13548     { "fadd",   { ST, STi }, 0 },
13549     { "fmul",   { ST, STi }, 0 },
13550     { "fcom",   { STi }, 0 },
13551     { "fcomp",  { STi }, 0 },
13552     { "fsub",   { ST, STi }, 0 },
13553     { "fsubr",  { ST, STi }, 0 },
13554     { "fdiv",   { ST, STi }, 0 },
13555     { "fdivr",  { ST, STi }, 0 },
13556   },
13557   /* d9 */
13558   {
13559     { "fld",    { STi }, 0 },
13560     { "fxch",   { STi }, 0 },
13561     { FGRPd9_2 },
13562     { Bad_Opcode },
13563     { FGRPd9_4 },
13564     { FGRPd9_5 },
13565     { FGRPd9_6 },
13566     { FGRPd9_7 },
13567   },
13568   /* da */
13569   {
13570     { "fcmovb", { ST, STi }, 0 },
13571     { "fcmove", { ST, STi }, 0 },
13572     { "fcmovbe",{ ST, STi }, 0 },
13573     { "fcmovu", { ST, STi }, 0 },
13574     { Bad_Opcode },
13575     { FGRPda_5 },
13576     { Bad_Opcode },
13577     { Bad_Opcode },
13578   },
13579   /* db */
13580   {
13581     { "fcmovnb",{ ST, STi }, 0 },
13582     { "fcmovne",{ ST, STi }, 0 },
13583     { "fcmovnbe",{ ST, STi }, 0 },
13584     { "fcmovnu",{ ST, STi }, 0 },
13585     { FGRPdb_4 },
13586     { "fucomi", { ST, STi }, 0 },
13587     { "fcomi",  { ST, STi }, 0 },
13588     { Bad_Opcode },
13589   },
13590   /* dc */
13591   {
13592     { "fadd",   { STi, ST }, 0 },
13593     { "fmul",   { STi, ST }, 0 },
13594     { Bad_Opcode },
13595     { Bad_Opcode },
13596     { "fsub!M", { STi, ST }, 0 },
13597     { "fsubM",  { STi, ST }, 0 },
13598     { "fdiv!M", { STi, ST }, 0 },
13599     { "fdivM",  { STi, ST }, 0 },
13600   },
13601   /* dd */
13602   {
13603     { "ffree",  { STi }, 0 },
13604     { Bad_Opcode },
13605     { "fst",    { STi }, 0 },
13606     { "fstp",   { STi }, 0 },
13607     { "fucom",  { STi }, 0 },
13608     { "fucomp", { STi }, 0 },
13609     { Bad_Opcode },
13610     { Bad_Opcode },
13611   },
13612   /* de */
13613   {
13614     { "faddp",  { STi, ST }, 0 },
13615     { "fmulp",  { STi, ST }, 0 },
13616     { Bad_Opcode },
13617     { FGRPde_3 },
13618     { "fsub!Mp", { STi, ST }, 0 },
13619     { "fsubMp", { STi, ST }, 0 },
13620     { "fdiv!Mp", { STi, ST }, 0 },
13621     { "fdivMp", { STi, ST }, 0 },
13622   },
13623   /* df */
13624   {
13625     { "ffreep", { STi }, 0 },
13626     { Bad_Opcode },
13627     { Bad_Opcode },
13628     { Bad_Opcode },
13629     { FGRPdf_4 },
13630     { "fucomip", { ST, STi }, 0 },
13631     { "fcomip", { ST, STi }, 0 },
13632     { Bad_Opcode },
13633   },
13634 };
13635
13636 static char *fgrps[][8] = {
13637   /* Bad opcode 0 */
13638   {
13639     "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13640   },
13641
13642   /* d9_2  1 */
13643   {
13644     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13645   },
13646
13647   /* d9_4  2 */
13648   {
13649     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
13650   },
13651
13652   /* d9_5  3 */
13653   {
13654     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
13655   },
13656
13657   /* d9_6  4 */
13658   {
13659     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
13660   },
13661
13662   /* d9_7  5 */
13663   {
13664     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
13665   },
13666
13667   /* da_5  6 */
13668   {
13669     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13670   },
13671
13672   /* db_4  7 */
13673   {
13674     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
13675     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
13676   },
13677
13678   /* de_3  8 */
13679   {
13680     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13681   },
13682
13683   /* df_4  9 */
13684   {
13685     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13686   },
13687 };
13688
13689 static void
13690 swap_operand (void)
13691 {
13692   mnemonicendp[0] = '.';
13693   mnemonicendp[1] = 's';
13694   mnemonicendp += 2;
13695 }
13696
13697 static void
13698 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
13699                int sizeflag ATTRIBUTE_UNUSED)
13700 {
13701   /* Skip mod/rm byte.  */
13702   MODRM_CHECK;
13703   codep++;
13704 }
13705
13706 static void
13707 dofloat (int sizeflag)
13708 {
13709   const struct dis386 *dp;
13710   unsigned char floatop;
13711
13712   floatop = codep[-1];
13713
13714   if (modrm.mod != 3)
13715     {
13716       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
13717
13718       putop (float_mem[fp_indx], sizeflag);
13719       obufp = op_out[0];
13720       op_ad = 2;
13721       OP_E (float_mem_mode[fp_indx], sizeflag);
13722       return;
13723     }
13724   /* Skip mod/rm byte.  */
13725   MODRM_CHECK;
13726   codep++;
13727
13728   dp = &float_reg[floatop - 0xd8][modrm.reg];
13729   if (dp->name == NULL)
13730     {
13731       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
13732
13733       /* Instruction fnstsw is only one with strange arg.  */
13734       if (floatop == 0xdf && codep[-1] == 0xe0)
13735         strcpy (op_out[0], names16[0]);
13736     }
13737   else
13738     {
13739       putop (dp->name, sizeflag);
13740
13741       obufp = op_out[0];
13742       op_ad = 2;
13743       if (dp->op[0].rtn)
13744         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
13745
13746       obufp = op_out[1];
13747       op_ad = 1;
13748       if (dp->op[1].rtn)
13749         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
13750     }
13751 }
13752
13753 /* Like oappend (below), but S is a string starting with '%'.
13754    In Intel syntax, the '%' is elided.  */
13755 static void
13756 oappend_maybe_intel (const char *s)
13757 {
13758   oappend (s + intel_syntax);
13759 }
13760
13761 static void
13762 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13763 {
13764   oappend_maybe_intel ("%st");
13765 }
13766
13767 static void
13768 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13769 {
13770   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
13771   oappend_maybe_intel (scratchbuf);
13772 }
13773
13774 /* Capital letters in template are macros.  */
13775 static int
13776 putop (const char *in_template, int sizeflag)
13777 {
13778   const char *p;
13779   int alt = 0;
13780   int cond = 1;
13781   unsigned int l = 0, len = 1;
13782   char last[4];
13783
13784 #define SAVE_LAST(c)                    \
13785   if (l < len && l < sizeof (last))     \
13786     last[l++] = c;                      \
13787   else                                  \
13788     abort ();
13789
13790   for (p = in_template; *p; p++)
13791     {
13792       switch (*p)
13793         {
13794         default:
13795           *obufp++ = *p;
13796           break;
13797         case '%':
13798           len++;
13799           break;
13800         case '!':
13801           cond = 0;
13802           break;
13803         case '{':
13804           if (intel_syntax)
13805             {
13806               while (*++p != '|')
13807                 if (*p == '}' || *p == '\0')
13808                   abort ();
13809             }
13810           /* Fall through.  */
13811         case 'I':
13812           alt = 1;
13813           continue;
13814         case '|':
13815           while (*++p != '}')
13816             {
13817               if (*p == '\0')
13818                 abort ();
13819             }
13820           break;
13821         case '}':
13822           break;
13823         case 'A':
13824           if (intel_syntax)
13825             break;
13826           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13827             *obufp++ = 'b';
13828           break;
13829         case 'B':
13830           if (l == 0 && len == 1)
13831             {
13832 case_B:
13833               if (intel_syntax)
13834                 break;
13835               if (sizeflag & SUFFIX_ALWAYS)
13836                 *obufp++ = 'b';
13837             }
13838           else
13839             {
13840               if (l != 1
13841                   || len != 2
13842                   || last[0] != 'L')
13843                 {
13844                   SAVE_LAST (*p);
13845                   break;
13846                 }
13847
13848               if (address_mode == mode_64bit
13849                   && !(prefixes & PREFIX_ADDR))
13850                 {
13851                   *obufp++ = 'a';
13852                   *obufp++ = 'b';
13853                   *obufp++ = 's';
13854                 }
13855
13856               goto case_B;
13857             }
13858           break;
13859         case 'C':
13860           if (intel_syntax && !alt)
13861             break;
13862           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
13863             {
13864               if (sizeflag & DFLAG)
13865                 *obufp++ = intel_syntax ? 'd' : 'l';
13866               else
13867                 *obufp++ = intel_syntax ? 'w' : 's';
13868               used_prefixes |= (prefixes & PREFIX_DATA);
13869             }
13870           break;
13871         case 'D':
13872           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
13873             break;
13874           USED_REX (REX_W);
13875           if (modrm.mod == 3)
13876             {
13877               if (rex & REX_W)
13878                 *obufp++ = 'q';
13879               else
13880                 {
13881                   if (sizeflag & DFLAG)
13882                     *obufp++ = intel_syntax ? 'd' : 'l';
13883                   else
13884                     *obufp++ = 'w';
13885                   used_prefixes |= (prefixes & PREFIX_DATA);
13886                 }
13887             }
13888           else
13889             *obufp++ = 'w';
13890           break;
13891         case 'E':               /* For jcxz/jecxz */
13892           if (address_mode == mode_64bit)
13893             {
13894               if (sizeflag & AFLAG)
13895                 *obufp++ = 'r';
13896               else
13897                 *obufp++ = 'e';
13898             }
13899           else
13900             if (sizeflag & AFLAG)
13901               *obufp++ = 'e';
13902           used_prefixes |= (prefixes & PREFIX_ADDR);
13903           break;
13904         case 'F':
13905           if (intel_syntax)
13906             break;
13907           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
13908             {
13909               if (sizeflag & AFLAG)
13910                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
13911               else
13912                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
13913               used_prefixes |= (prefixes & PREFIX_ADDR);
13914             }
13915           break;
13916         case 'G':
13917           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
13918             break;
13919           if ((rex & REX_W) || (sizeflag & DFLAG))
13920             *obufp++ = 'l';
13921           else
13922             *obufp++ = 'w';
13923           if (!(rex & REX_W))
13924             used_prefixes |= (prefixes & PREFIX_DATA);
13925           break;
13926         case 'H':
13927           if (intel_syntax)
13928             break;
13929           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
13930               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
13931             {
13932               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
13933               *obufp++ = ',';
13934               *obufp++ = 'p';
13935               if (prefixes & PREFIX_DS)
13936                 *obufp++ = 't';
13937               else
13938                 *obufp++ = 'n';
13939             }
13940           break;
13941         case 'J':
13942           if (intel_syntax)
13943             break;
13944           *obufp++ = 'l';
13945           break;
13946         case 'K':
13947           USED_REX (REX_W);
13948           if (rex & REX_W)
13949             *obufp++ = 'q';
13950           else
13951             *obufp++ = 'd';
13952           break;
13953         case 'Z':
13954           if (l != 0 || len != 1)
13955             {
13956               if (l != 1 || len != 2 || last[0] != 'X')
13957                 {
13958                   SAVE_LAST (*p);
13959                   break;
13960                 }
13961               if (!need_vex || !vex.evex)
13962                 abort ();
13963               if (intel_syntax
13964                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
13965                 break;
13966               switch (vex.length)
13967                 {
13968                 case 128:
13969                   *obufp++ = 'x';
13970                   break;
13971                 case 256:
13972                   *obufp++ = 'y';
13973                   break;
13974                 case 512:
13975                   *obufp++ = 'z';
13976                   break;
13977                 default:
13978                   abort ();
13979                 }
13980               break;
13981             }
13982           if (intel_syntax)
13983             break;
13984           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
13985             {
13986               *obufp++ = 'q';
13987               break;
13988             }
13989           /* Fall through.  */
13990           goto case_L;
13991         case 'L':
13992           if (l != 0 || len != 1)
13993             {
13994               SAVE_LAST (*p);
13995               break;
13996             }
13997 case_L:
13998           if (intel_syntax)
13999             break;
14000           if (sizeflag & SUFFIX_ALWAYS)
14001             *obufp++ = 'l';
14002           break;
14003         case 'M':
14004           if (intel_mnemonic != cond)
14005             *obufp++ = 'r';
14006           break;
14007         case 'N':
14008           if ((prefixes & PREFIX_FWAIT) == 0)
14009             *obufp++ = 'n';
14010           else
14011             used_prefixes |= PREFIX_FWAIT;
14012           break;
14013         case 'O':
14014           USED_REX (REX_W);
14015           if (rex & REX_W)
14016             *obufp++ = 'o';
14017           else if (intel_syntax && (sizeflag & DFLAG))
14018             *obufp++ = 'q';
14019           else
14020             *obufp++ = 'd';
14021           if (!(rex & REX_W))
14022             used_prefixes |= (prefixes & PREFIX_DATA);
14023           break;
14024         case '&':
14025           if (!intel_syntax
14026               && address_mode == mode_64bit
14027               && isa64 == intel64)
14028             {
14029               *obufp++ = 'q';
14030               break;
14031             }
14032           /* Fall through.  */
14033         case 'T':
14034           if (!intel_syntax
14035               && address_mode == mode_64bit
14036               && ((sizeflag & DFLAG) || (rex & REX_W)))
14037             {
14038               *obufp++ = 'q';
14039               break;
14040             }
14041           /* Fall through.  */
14042           goto case_P;
14043         case 'P':
14044           if (l == 0 && len == 1)
14045             {
14046 case_P:
14047               if (intel_syntax)
14048                 {
14049                   if ((rex & REX_W) == 0
14050                       && (prefixes & PREFIX_DATA))
14051                     {
14052                       if ((sizeflag & DFLAG) == 0)
14053                         *obufp++ = 'w';
14054                       used_prefixes |= (prefixes & PREFIX_DATA);
14055                     }
14056                   break;
14057                 }
14058               if ((prefixes & PREFIX_DATA)
14059                   || (rex & REX_W)
14060                   || (sizeflag & SUFFIX_ALWAYS))
14061                 {
14062                   USED_REX (REX_W);
14063                   if (rex & REX_W)
14064                     *obufp++ = 'q';
14065                   else
14066                     {
14067                       if (sizeflag & DFLAG)
14068                         *obufp++ = 'l';
14069                       else
14070                         *obufp++ = 'w';
14071                       used_prefixes |= (prefixes & PREFIX_DATA);
14072                     }
14073                 }
14074             }
14075           else
14076             {
14077               if (l != 1 || len != 2 || last[0] != 'L')
14078                 {
14079                   SAVE_LAST (*p);
14080                   break;
14081                 }
14082
14083               if ((prefixes & PREFIX_DATA)
14084                   || (rex & REX_W)
14085                   || (sizeflag & SUFFIX_ALWAYS))
14086                 {
14087                   USED_REX (REX_W);
14088                   if (rex & REX_W)
14089                     *obufp++ = 'q';
14090                   else
14091                     {
14092                       if (sizeflag & DFLAG)
14093                         *obufp++ = intel_syntax ? 'd' : 'l';
14094                       else
14095                         *obufp++ = 'w';
14096                       used_prefixes |= (prefixes & PREFIX_DATA);
14097                     }
14098                 }
14099             }
14100           break;
14101         case 'U':
14102           if (intel_syntax)
14103             break;
14104           if (address_mode == mode_64bit
14105               && ((sizeflag & DFLAG) || (rex & REX_W)))
14106             {
14107               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
14108                 *obufp++ = 'q';
14109               break;
14110             }
14111           /* Fall through.  */
14112           goto case_Q;
14113         case 'Q':
14114           if (l == 0 && len == 1)
14115             {
14116 case_Q:
14117               if (intel_syntax && !alt)
14118                 break;
14119               USED_REX (REX_W);
14120               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
14121                 {
14122                   if (rex & REX_W)
14123                     *obufp++ = 'q';
14124                   else
14125                     {
14126                       if (sizeflag & DFLAG)
14127                         *obufp++ = intel_syntax ? 'd' : 'l';
14128                       else
14129                         *obufp++ = 'w';
14130                       used_prefixes |= (prefixes & PREFIX_DATA);
14131                     }
14132                 }
14133             }
14134           else
14135             {
14136               if (l != 1 || len != 2 || last[0] != 'L')
14137                 {
14138                   SAVE_LAST (*p);
14139                   break;
14140                 }
14141               if (intel_syntax
14142                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
14143                 break;
14144               if ((rex & REX_W))
14145                 {
14146                   USED_REX (REX_W);
14147                   *obufp++ = 'q';
14148                 }
14149               else
14150                 *obufp++ = 'l';
14151             }
14152           break;
14153         case 'R':
14154           USED_REX (REX_W);
14155           if (rex & REX_W)
14156             *obufp++ = 'q';
14157           else if (sizeflag & DFLAG)
14158             {
14159               if (intel_syntax)
14160                   *obufp++ = 'd';
14161               else
14162                   *obufp++ = 'l';
14163             }
14164           else
14165             *obufp++ = 'w';
14166           if (intel_syntax && !p[1]
14167               && ((rex & REX_W) || (sizeflag & DFLAG)))
14168             *obufp++ = 'e';
14169           if (!(rex & REX_W))
14170             used_prefixes |= (prefixes & PREFIX_DATA);
14171           break;
14172         case 'V':
14173           if (l == 0 && len == 1)
14174             {
14175               if (intel_syntax)
14176                 break;
14177               if (address_mode == mode_64bit
14178                   && ((sizeflag & DFLAG) || (rex & REX_W)))
14179                 {
14180                   if (sizeflag & SUFFIX_ALWAYS)
14181                     *obufp++ = 'q';
14182                   break;
14183                 }
14184             }
14185           else
14186             {
14187               if (l != 1
14188                   || len != 2
14189                   || last[0] != 'L')
14190                 {
14191                   SAVE_LAST (*p);
14192                   break;
14193                 }
14194
14195               if (rex & REX_W)
14196                 {
14197                   *obufp++ = 'a';
14198                   *obufp++ = 'b';
14199                   *obufp++ = 's';
14200                 }
14201             }
14202           /* Fall through.  */
14203           goto case_S;
14204         case 'S':
14205           if (l == 0 && len == 1)
14206             {
14207 case_S:
14208               if (intel_syntax)
14209                 break;
14210               if (sizeflag & SUFFIX_ALWAYS)
14211                 {
14212                   if (rex & REX_W)
14213                     *obufp++ = 'q';
14214                   else
14215                     {
14216                       if (sizeflag & DFLAG)
14217                         *obufp++ = 'l';
14218                       else
14219                         *obufp++ = 'w';
14220                       used_prefixes |= (prefixes & PREFIX_DATA);
14221                     }
14222                 }
14223             }
14224           else
14225             {
14226               if (l != 1
14227                   || len != 2
14228                   || last[0] != 'L')
14229                 {
14230                   SAVE_LAST (*p);
14231                   break;
14232                 }
14233
14234               if (address_mode == mode_64bit
14235                   && !(prefixes & PREFIX_ADDR))
14236                 {
14237                   *obufp++ = 'a';
14238                   *obufp++ = 'b';
14239                   *obufp++ = 's';
14240                 }
14241
14242               goto case_S;
14243             }
14244           break;
14245         case 'X':
14246           if (l != 0 || len != 1)
14247             {
14248               SAVE_LAST (*p);
14249               break;
14250             }
14251           if (need_vex && vex.prefix)
14252             {
14253               if (vex.prefix == DATA_PREFIX_OPCODE)
14254                 *obufp++ = 'd';
14255               else
14256                 *obufp++ = 's';
14257             }
14258           else
14259             {
14260               if (prefixes & PREFIX_DATA)
14261                 *obufp++ = 'd';
14262               else
14263                 *obufp++ = 's';
14264               used_prefixes |= (prefixes & PREFIX_DATA);
14265             }
14266           break;
14267         case 'Y':
14268           if (l == 0 && len == 1)
14269             {
14270               if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
14271                 break;
14272               if (rex & REX_W)
14273                 {
14274                   USED_REX (REX_W);
14275                   *obufp++ = 'q';
14276                 }
14277               break;
14278             }
14279           else
14280             {
14281               if (l != 1 || len != 2 || last[0] != 'X')
14282                 {
14283                   SAVE_LAST (*p);
14284                   break;
14285                 }
14286               if (!need_vex)
14287                 abort ();
14288               if (intel_syntax
14289                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
14290                 break;
14291               switch (vex.length)
14292                 {
14293                 case 128:
14294                   *obufp++ = 'x';
14295                   break;
14296                 case 256:
14297                   *obufp++ = 'y';
14298                   break;
14299                 case 512:
14300                   if (!vex.evex)
14301                 default:
14302                     abort ();
14303                 }
14304             }
14305           break;
14306         case 'W':
14307           if (l == 0 && len == 1)
14308             {
14309               /* operand size flag for cwtl, cbtw */
14310               USED_REX (REX_W);
14311               if (rex & REX_W)
14312                 {
14313                   if (intel_syntax)
14314                     *obufp++ = 'd';
14315                   else
14316                     *obufp++ = 'l';
14317                 }
14318               else if (sizeflag & DFLAG)
14319                 *obufp++ = 'w';
14320               else
14321                 *obufp++ = 'b';
14322               if (!(rex & REX_W))
14323                 used_prefixes |= (prefixes & PREFIX_DATA);
14324             }
14325           else
14326             {
14327               if (l != 1
14328                   || len != 2
14329                   || (last[0] != 'X'
14330                       && last[0] != 'L'))
14331                 {
14332                   SAVE_LAST (*p);
14333                   break;
14334                 }
14335               if (!need_vex)
14336                 abort ();
14337               if (last[0] == 'X')
14338                 *obufp++ = vex.w ? 'd': 's';
14339               else
14340                 *obufp++ = vex.w ? 'q': 'd';
14341             }
14342           break;
14343         case '^':
14344           if (intel_syntax)
14345             break;
14346           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
14347             {
14348               if (sizeflag & DFLAG)
14349                 *obufp++ = 'l';
14350               else
14351                 *obufp++ = 'w';
14352               used_prefixes |= (prefixes & PREFIX_DATA);
14353             }
14354           break;
14355         case '@':
14356           if (intel_syntax)
14357             break;
14358           if (address_mode == mode_64bit
14359               && (isa64 == intel64
14360                   || ((sizeflag & DFLAG) || (rex & REX_W))))
14361               *obufp++ = 'q';
14362           else if ((prefixes & PREFIX_DATA))
14363             {
14364               if (!(sizeflag & DFLAG))
14365                 *obufp++ = 'w';
14366               used_prefixes |= (prefixes & PREFIX_DATA);
14367             }
14368           break;
14369         }
14370       alt = 0;
14371     }
14372   *obufp = 0;
14373   mnemonicendp = obufp;
14374   return 0;
14375 }
14376
14377 static void
14378 oappend (const char *s)
14379 {
14380   obufp = stpcpy (obufp, s);
14381 }
14382
14383 static void
14384 append_seg (void)
14385 {
14386   /* Only print the active segment register.  */
14387   if (!active_seg_prefix)
14388     return;
14389
14390   used_prefixes |= active_seg_prefix;
14391   switch (active_seg_prefix)
14392     {
14393     case PREFIX_CS:
14394       oappend_maybe_intel ("%cs:");
14395       break;
14396     case PREFIX_DS:
14397       oappend_maybe_intel ("%ds:");
14398       break;
14399     case PREFIX_SS:
14400       oappend_maybe_intel ("%ss:");
14401       break;
14402     case PREFIX_ES:
14403       oappend_maybe_intel ("%es:");
14404       break;
14405     case PREFIX_FS:
14406       oappend_maybe_intel ("%fs:");
14407       break;
14408     case PREFIX_GS:
14409       oappend_maybe_intel ("%gs:");
14410       break;
14411     default:
14412       break;
14413     }
14414 }
14415
14416 static void
14417 OP_indirE (int bytemode, int sizeflag)
14418 {
14419   if (!intel_syntax)
14420     oappend ("*");
14421   OP_E (bytemode, sizeflag);
14422 }
14423
14424 static void
14425 print_operand_value (char *buf, int hex, bfd_vma disp)
14426 {
14427   if (address_mode == mode_64bit)
14428     {
14429       if (hex)
14430         {
14431           char tmp[30];
14432           int i;
14433           buf[0] = '0';
14434           buf[1] = 'x';
14435           sprintf_vma (tmp, disp);
14436           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
14437           strcpy (buf + 2, tmp + i);
14438         }
14439       else
14440         {
14441           bfd_signed_vma v = disp;
14442           char tmp[30];
14443           int i;
14444           if (v < 0)
14445             {
14446               *(buf++) = '-';
14447               v = -disp;
14448               /* Check for possible overflow on 0x8000000000000000.  */
14449               if (v < 0)
14450                 {
14451                   strcpy (buf, "9223372036854775808");
14452                   return;
14453                 }
14454             }
14455           if (!v)
14456             {
14457               strcpy (buf, "0");
14458               return;
14459             }
14460
14461           i = 0;
14462           tmp[29] = 0;
14463           while (v)
14464             {
14465               tmp[28 - i] = (v % 10) + '0';
14466               v /= 10;
14467               i++;
14468             }
14469           strcpy (buf, tmp + 29 - i);
14470         }
14471     }
14472   else
14473     {
14474       if (hex)
14475         sprintf (buf, "0x%x", (unsigned int) disp);
14476       else
14477         sprintf (buf, "%d", (int) disp);
14478     }
14479 }
14480
14481 /* Put DISP in BUF as signed hex number.  */
14482
14483 static void
14484 print_displacement (char *buf, bfd_vma disp)
14485 {
14486   bfd_signed_vma val = disp;
14487   char tmp[30];
14488   int i, j = 0;
14489
14490   if (val < 0)
14491     {
14492       buf[j++] = '-';
14493       val = -disp;
14494
14495       /* Check for possible overflow.  */
14496       if (val < 0)
14497         {
14498           switch (address_mode)
14499             {
14500             case mode_64bit:
14501               strcpy (buf + j, "0x8000000000000000");
14502               break;
14503             case mode_32bit:
14504               strcpy (buf + j, "0x80000000");
14505               break;
14506             case mode_16bit:
14507               strcpy (buf + j, "0x8000");
14508               break;
14509             }
14510           return;
14511         }
14512     }
14513
14514   buf[j++] = '0';
14515   buf[j++] = 'x';
14516
14517   sprintf_vma (tmp, (bfd_vma) val);
14518   for (i = 0; tmp[i] == '0'; i++)
14519     continue;
14520   if (tmp[i] == '\0')
14521     i--;
14522   strcpy (buf + j, tmp + i);
14523 }
14524
14525 static void
14526 intel_operand_size (int bytemode, int sizeflag)
14527 {
14528   if (vex.evex
14529       && vex.b
14530       && (bytemode == x_mode
14531           || bytemode == evex_half_bcst_xmmq_mode))
14532     {
14533       if (vex.w)
14534         oappend ("QWORD PTR ");
14535       else
14536         oappend ("DWORD PTR ");
14537       return;
14538     }
14539   switch (bytemode)
14540     {
14541     case b_mode:
14542     case b_swap_mode:
14543     case dqb_mode:
14544     case db_mode:
14545       oappend ("BYTE PTR ");
14546       break;
14547     case w_mode:
14548     case dw_mode:
14549     case dqw_mode:
14550       oappend ("WORD PTR ");
14551       break;
14552     case indir_v_mode:
14553       if (address_mode == mode_64bit && isa64 == intel64)
14554         {
14555           oappend ("QWORD PTR ");
14556           break;
14557         }
14558       /* Fall through.  */
14559     case stack_v_mode:
14560       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14561         {
14562           oappend ("QWORD PTR ");
14563           break;
14564         }
14565       /* Fall through.  */
14566     case v_mode:
14567     case v_swap_mode:
14568     case dq_mode:
14569       USED_REX (REX_W);
14570       if (rex & REX_W)
14571         oappend ("QWORD PTR ");
14572       else
14573         {
14574           if ((sizeflag & DFLAG) || bytemode == dq_mode)
14575             oappend ("DWORD PTR ");
14576           else
14577             oappend ("WORD PTR ");
14578           used_prefixes |= (prefixes & PREFIX_DATA);
14579         }
14580       break;
14581     case z_mode:
14582       if ((rex & REX_W) || (sizeflag & DFLAG))
14583         *obufp++ = 'D';
14584       oappend ("WORD PTR ");
14585       if (!(rex & REX_W))
14586         used_prefixes |= (prefixes & PREFIX_DATA);
14587       break;
14588     case a_mode:
14589       if (sizeflag & DFLAG)
14590         oappend ("QWORD PTR ");
14591       else
14592         oappend ("DWORD PTR ");
14593       used_prefixes |= (prefixes & PREFIX_DATA);
14594       break;
14595     case d_mode:
14596     case d_scalar_mode:
14597     case d_scalar_swap_mode:
14598     case d_swap_mode:
14599     case dqd_mode:
14600       oappend ("DWORD PTR ");
14601       break;
14602     case q_mode:
14603     case q_scalar_mode:
14604     case q_scalar_swap_mode:
14605     case q_swap_mode:
14606       oappend ("QWORD PTR ");
14607       break;
14608     case m_mode:
14609       if (address_mode == mode_64bit)
14610         oappend ("QWORD PTR ");
14611       else
14612         oappend ("DWORD PTR ");
14613       break;
14614     case f_mode:
14615       if (sizeflag & DFLAG)
14616         oappend ("FWORD PTR ");
14617       else
14618         oappend ("DWORD PTR ");
14619       used_prefixes |= (prefixes & PREFIX_DATA);
14620       break;
14621     case t_mode:
14622       oappend ("TBYTE PTR ");
14623       break;
14624     case x_mode:
14625     case x_swap_mode:
14626     case evex_x_gscat_mode:
14627     case evex_x_nobcst_mode:
14628       if (need_vex)
14629         {
14630           switch (vex.length)
14631             {
14632             case 128:
14633               oappend ("XMMWORD PTR ");
14634               break;
14635             case 256:
14636               oappend ("YMMWORD PTR ");
14637               break;
14638             case 512:
14639               oappend ("ZMMWORD PTR ");
14640               break;
14641             default:
14642               abort ();
14643             }
14644         }
14645       else
14646         oappend ("XMMWORD PTR ");
14647       break;
14648     case xmm_mode:
14649       oappend ("XMMWORD PTR ");
14650       break;
14651     case ymm_mode:
14652       oappend ("YMMWORD PTR ");
14653       break;
14654     case xmmq_mode:
14655     case evex_half_bcst_xmmq_mode:
14656       if (!need_vex)
14657         abort ();
14658
14659       switch (vex.length)
14660         {
14661         case 128:
14662           oappend ("QWORD PTR ");
14663           break;
14664         case 256:
14665           oappend ("XMMWORD PTR ");
14666           break;
14667         case 512:
14668           oappend ("YMMWORD PTR ");
14669           break;
14670         default:
14671           abort ();
14672         }
14673       break;
14674     case xmm_mb_mode:
14675       if (!need_vex)
14676         abort ();
14677
14678       switch (vex.length)
14679         {
14680         case 128:
14681         case 256:
14682         case 512:
14683           oappend ("BYTE PTR ");
14684           break;
14685         default:
14686           abort ();
14687         }
14688       break;
14689     case xmm_mw_mode:
14690       if (!need_vex)
14691         abort ();
14692
14693       switch (vex.length)
14694         {
14695         case 128:
14696         case 256:
14697         case 512:
14698           oappend ("WORD PTR ");
14699           break;
14700         default:
14701           abort ();
14702         }
14703       break;
14704     case xmm_md_mode:
14705       if (!need_vex)
14706         abort ();
14707
14708       switch (vex.length)
14709         {
14710         case 128:
14711         case 256:
14712         case 512:
14713           oappend ("DWORD PTR ");
14714           break;
14715         default:
14716           abort ();
14717         }
14718       break;
14719     case xmm_mq_mode:
14720       if (!need_vex)
14721         abort ();
14722
14723       switch (vex.length)
14724         {
14725         case 128:
14726         case 256:
14727         case 512:
14728           oappend ("QWORD PTR ");
14729           break;
14730         default:
14731           abort ();
14732         }
14733       break;
14734     case xmmdw_mode:
14735       if (!need_vex)
14736         abort ();
14737
14738       switch (vex.length)
14739         {
14740         case 128:
14741           oappend ("WORD PTR ");
14742           break;
14743         case 256:
14744           oappend ("DWORD PTR ");
14745           break;
14746         case 512:
14747           oappend ("QWORD PTR ");
14748           break;
14749         default:
14750           abort ();
14751         }
14752       break;
14753     case xmmqd_mode:
14754       if (!need_vex)
14755         abort ();
14756
14757       switch (vex.length)
14758         {
14759         case 128:
14760           oappend ("DWORD PTR ");
14761           break;
14762         case 256:
14763           oappend ("QWORD PTR ");
14764           break;
14765         case 512:
14766           oappend ("XMMWORD PTR ");
14767           break;
14768         default:
14769           abort ();
14770         }
14771       break;
14772     case ymmq_mode:
14773       if (!need_vex)
14774         abort ();
14775
14776       switch (vex.length)
14777         {
14778         case 128:
14779           oappend ("QWORD PTR ");
14780           break;
14781         case 256:
14782           oappend ("YMMWORD PTR ");
14783           break;
14784         case 512:
14785           oappend ("ZMMWORD PTR ");
14786           break;
14787         default:
14788           abort ();
14789         }
14790       break;
14791     case ymmxmm_mode:
14792       if (!need_vex)
14793         abort ();
14794
14795       switch (vex.length)
14796         {
14797         case 128:
14798         case 256:
14799           oappend ("XMMWORD PTR ");
14800           break;
14801         default:
14802           abort ();
14803         }
14804       break;
14805     case o_mode:
14806       oappend ("OWORD PTR ");
14807       break;
14808     case xmm_mdq_mode:
14809     case vex_w_dq_mode:
14810     case vex_scalar_w_dq_mode:
14811       if (!need_vex)
14812         abort ();
14813
14814       if (vex.w)
14815         oappend ("QWORD PTR ");
14816       else
14817         oappend ("DWORD PTR ");
14818       break;
14819     case vex_vsib_d_w_dq_mode:
14820     case vex_vsib_q_w_dq_mode:
14821       if (!need_vex)
14822         abort ();
14823
14824       if (!vex.evex)
14825         {
14826           if (vex.w)
14827             oappend ("QWORD PTR ");
14828           else
14829             oappend ("DWORD PTR ");
14830         }
14831       else
14832         {
14833           switch (vex.length)
14834             {
14835             case 128:
14836               oappend ("XMMWORD PTR ");
14837               break;
14838             case 256:
14839               oappend ("YMMWORD PTR ");
14840               break;
14841             case 512:
14842               oappend ("ZMMWORD PTR ");
14843               break;
14844             default:
14845               abort ();
14846             }
14847         }
14848       break;
14849     case vex_vsib_q_w_d_mode:
14850     case vex_vsib_d_w_d_mode:
14851       if (!need_vex || !vex.evex)
14852         abort ();
14853
14854       switch (vex.length)
14855         {
14856         case 128:
14857           oappend ("QWORD PTR ");
14858           break;
14859         case 256:
14860           oappend ("XMMWORD PTR ");
14861           break;
14862         case 512:
14863           oappend ("YMMWORD PTR ");
14864           break;
14865         default:
14866           abort ();
14867         }
14868
14869       break;
14870     case mask_bd_mode:
14871       if (!need_vex || vex.length != 128)
14872         abort ();
14873       if (vex.w)
14874         oappend ("DWORD PTR ");
14875       else
14876         oappend ("BYTE PTR ");
14877       break;
14878     case mask_mode:
14879       if (!need_vex)
14880         abort ();
14881       if (vex.w)
14882         oappend ("QWORD PTR ");
14883       else
14884         oappend ("WORD PTR ");
14885       break;
14886     case v_bnd_mode:
14887     default:
14888       break;
14889     }
14890 }
14891
14892 static void
14893 OP_E_register (int bytemode, int sizeflag)
14894 {
14895   int reg = modrm.rm;
14896   const char **names;
14897
14898   USED_REX (REX_B);
14899   if ((rex & REX_B))
14900     reg += 8;
14901
14902   if ((sizeflag & SUFFIX_ALWAYS)
14903       && (bytemode == b_swap_mode
14904           || bytemode == v_swap_mode))
14905     swap_operand ();
14906
14907   switch (bytemode)
14908     {
14909     case b_mode:
14910     case b_swap_mode:
14911       USED_REX (0);
14912       if (rex)
14913         names = names8rex;
14914       else
14915         names = names8;
14916       break;
14917     case w_mode:
14918       names = names16;
14919       break;
14920     case d_mode:
14921     case dw_mode:
14922     case db_mode:
14923       names = names32;
14924       break;
14925     case q_mode:
14926       names = names64;
14927       break;
14928     case m_mode:
14929     case v_bnd_mode:
14930       names = address_mode == mode_64bit ? names64 : names32;
14931       break;
14932     case bnd_mode:
14933       names = names_bnd;
14934       break;
14935     case indir_v_mode:
14936       if (address_mode == mode_64bit && isa64 == intel64)
14937         {
14938           names = names64;
14939           break;
14940         }
14941       /* Fall through.  */
14942     case stack_v_mode:
14943       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14944         {
14945           names = names64;
14946           break;
14947         }
14948       bytemode = v_mode;
14949       /* Fall through.  */
14950     case v_mode:
14951     case v_swap_mode:
14952     case dq_mode:
14953     case dqb_mode:
14954     case dqd_mode:
14955     case dqw_mode:
14956       USED_REX (REX_W);
14957       if (rex & REX_W)
14958         names = names64;
14959       else
14960         {
14961           if ((sizeflag & DFLAG)
14962               || (bytemode != v_mode
14963                   && bytemode != v_swap_mode))
14964             names = names32;
14965           else
14966             names = names16;
14967           used_prefixes |= (prefixes & PREFIX_DATA);
14968         }
14969       break;
14970     case mask_bd_mode:
14971     case mask_mode:
14972       if (reg > 0x7)
14973         {
14974           oappend ("(bad)");
14975           return;
14976         }
14977       names = names_mask;
14978       break;
14979     case 0:
14980       return;
14981     default:
14982       oappend (INTERNAL_DISASSEMBLER_ERROR);
14983       return;
14984     }
14985   oappend (names[reg]);
14986 }
14987
14988 static void
14989 OP_E_memory (int bytemode, int sizeflag)
14990 {
14991   bfd_vma disp = 0;
14992   int add = (rex & REX_B) ? 8 : 0;
14993   int riprel = 0;
14994   int shift;
14995
14996   if (vex.evex)
14997     {
14998       /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0.  */
14999       if (vex.b
15000           && bytemode != x_mode
15001           && bytemode != xmmq_mode
15002           && bytemode != evex_half_bcst_xmmq_mode)
15003         {
15004           BadOp ();
15005           return;
15006         }
15007       switch (bytemode)
15008         {
15009         case dqw_mode:
15010         case dw_mode:
15011           shift = 1;
15012           break;
15013         case dqb_mode:
15014         case db_mode:
15015           shift = 0;
15016           break;
15017         case vex_vsib_d_w_dq_mode:
15018         case vex_vsib_d_w_d_mode:
15019         case vex_vsib_q_w_dq_mode:
15020         case vex_vsib_q_w_d_mode:
15021         case evex_x_gscat_mode:
15022         case xmm_mdq_mode:
15023           shift = vex.w ? 3 : 2;
15024           break;
15025         case x_mode:
15026         case evex_half_bcst_xmmq_mode:
15027         case xmmq_mode:
15028           if (vex.b)
15029             {
15030               shift = vex.w ? 3 : 2;
15031               break;
15032             }
15033           /* Fall through.  */
15034         case xmmqd_mode:
15035         case xmmdw_mode:
15036         case ymmq_mode:
15037         case evex_x_nobcst_mode:
15038         case x_swap_mode:
15039           switch (vex.length)
15040             {
15041             case 128:
15042               shift = 4;
15043               break;
15044             case 256:
15045               shift = 5;
15046               break;
15047             case 512:
15048               shift = 6;
15049               break;
15050             default:
15051               abort ();
15052             }
15053           break;
15054         case ymm_mode:
15055           shift = 5;
15056           break;
15057         case xmm_mode:
15058           shift = 4;
15059           break;
15060         case xmm_mq_mode:
15061         case q_mode:
15062         case q_scalar_mode:
15063         case q_swap_mode:
15064         case q_scalar_swap_mode:
15065           shift = 3;
15066           break;
15067         case dqd_mode:
15068         case xmm_md_mode:
15069         case d_mode:
15070         case d_scalar_mode:
15071         case d_swap_mode:
15072         case d_scalar_swap_mode:
15073           shift = 2;
15074           break;
15075         case xmm_mw_mode:
15076           shift = 1;
15077           break;
15078         case xmm_mb_mode:
15079           shift = 0;
15080           break;
15081         default:
15082           abort ();
15083         }
15084       /* Make necessary corrections to shift for modes that need it.
15085          For these modes we currently have shift 4, 5 or 6 depending on
15086          vex.length (it corresponds to xmmword, ymmword or zmmword
15087          operand).  We might want to make it 3, 4 or 5 (e.g. for
15088          xmmq_mode).  In case of broadcast enabled the corrections
15089          aren't needed, as element size is always 32 or 64 bits.  */
15090       if (!vex.b
15091           && (bytemode == xmmq_mode
15092               || bytemode == evex_half_bcst_xmmq_mode))
15093         shift -= 1;
15094       else if (bytemode == xmmqd_mode)
15095         shift -= 2;
15096       else if (bytemode == xmmdw_mode)
15097         shift -= 3;
15098       else if (bytemode == ymmq_mode && vex.length == 128)
15099         shift -= 1;
15100     }
15101   else
15102     shift = 0;
15103
15104   USED_REX (REX_B);
15105   if (intel_syntax)
15106     intel_operand_size (bytemode, sizeflag);
15107   append_seg ();
15108
15109   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
15110     {
15111       /* 32/64 bit address mode */
15112       int havedisp;
15113       int havesib;
15114       int havebase;
15115       int haveindex;
15116       int needindex;
15117       int base, rbase;
15118       int vindex = 0;
15119       int scale = 0;
15120       int addr32flag = !((sizeflag & AFLAG)
15121                          || bytemode == v_bnd_mode
15122                          || bytemode == bnd_mode);
15123       const char **indexes64 = names64;
15124       const char **indexes32 = names32;
15125
15126       havesib = 0;
15127       havebase = 1;
15128       haveindex = 0;
15129       base = modrm.rm;
15130
15131       if (base == 4)
15132         {
15133           havesib = 1;
15134           vindex = sib.index;
15135           USED_REX (REX_X);
15136           if (rex & REX_X)
15137             vindex += 8;
15138           switch (bytemode)
15139             {
15140             case vex_vsib_d_w_dq_mode:
15141             case vex_vsib_d_w_d_mode:
15142             case vex_vsib_q_w_dq_mode:
15143             case vex_vsib_q_w_d_mode:
15144               if (!need_vex)
15145                 abort ();
15146               if (vex.evex)
15147                 {
15148                   if (!vex.v)
15149                     vindex += 16;
15150                 }
15151
15152               haveindex = 1;
15153               switch (vex.length)
15154                 {
15155                 case 128:
15156                   indexes64 = indexes32 = names_xmm;
15157                   break;
15158                 case 256:
15159                   if (!vex.w
15160                       || bytemode == vex_vsib_q_w_dq_mode
15161                       || bytemode == vex_vsib_q_w_d_mode)
15162                     indexes64 = indexes32 = names_ymm;
15163                   else
15164                     indexes64 = indexes32 = names_xmm;
15165                   break;
15166                 case 512:
15167                   if (!vex.w
15168                       || bytemode == vex_vsib_q_w_dq_mode
15169                       || bytemode == vex_vsib_q_w_d_mode)
15170                     indexes64 = indexes32 = names_zmm;
15171                   else
15172                     indexes64 = indexes32 = names_ymm;
15173                   break;
15174                 default:
15175                   abort ();
15176                 }
15177               break;
15178             default:
15179               haveindex = vindex != 4;
15180               break;
15181             }
15182           scale = sib.scale;
15183           base = sib.base;
15184           codep++;
15185         }
15186       rbase = base + add;
15187
15188       switch (modrm.mod)
15189         {
15190         case 0:
15191           if (base == 5)
15192             {
15193               havebase = 0;
15194               if (address_mode == mode_64bit && !havesib)
15195                 riprel = 1;
15196               disp = get32s ();
15197             }
15198           break;
15199         case 1:
15200           FETCH_DATA (the_info, codep + 1);
15201           disp = *codep++;
15202           if ((disp & 0x80) != 0)
15203             disp -= 0x100;
15204           if (vex.evex && shift > 0)
15205             disp <<= shift;
15206           break;
15207         case 2:
15208           disp = get32s ();
15209           break;
15210         }
15211
15212       /* In 32bit mode, we need index register to tell [offset] from
15213          [eiz*1 + offset].  */
15214       needindex = (havesib
15215                    && !havebase
15216                    && !haveindex
15217                    && address_mode == mode_32bit);
15218       havedisp = (havebase
15219                   || needindex
15220                   || (havesib && (haveindex || scale != 0)));
15221
15222       if (!intel_syntax)
15223         if (modrm.mod != 0 || base == 5)
15224           {
15225             if (havedisp || riprel)
15226               print_displacement (scratchbuf, disp);
15227             else
15228               print_operand_value (scratchbuf, 1, disp);
15229             oappend (scratchbuf);
15230             if (riprel)
15231               {
15232                 set_op (disp, 1);
15233                 oappend (!addr32flag ? "(%rip)" : "(%eip)");
15234               }
15235           }
15236
15237       if ((havebase || haveindex || riprel)
15238           && (bytemode != v_bnd_mode)
15239           && (bytemode != bnd_mode))
15240         used_prefixes |= PREFIX_ADDR;
15241
15242       if (havedisp || (intel_syntax && riprel))
15243         {
15244           *obufp++ = open_char;
15245           if (intel_syntax && riprel)
15246             {
15247               set_op (disp, 1);
15248               oappend (!addr32flag ? "rip" : "eip");
15249             }
15250           *obufp = '\0';
15251           if (havebase)
15252             oappend (address_mode == mode_64bit && !addr32flag
15253                      ? names64[rbase] : names32[rbase]);
15254           if (havesib)
15255             {
15256               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
15257                  print index to tell base + index from base.  */
15258               if (scale != 0
15259                   || needindex
15260                   || haveindex
15261                   || (havebase && base != ESP_REG_NUM))
15262                 {
15263                   if (!intel_syntax || havebase)
15264                     {
15265                       *obufp++ = separator_char;
15266                       *obufp = '\0';
15267                     }
15268                   if (haveindex)
15269                     oappend (address_mode == mode_64bit && !addr32flag
15270                              ? indexes64[vindex] : indexes32[vindex]);
15271                   else
15272                     oappend (address_mode == mode_64bit && !addr32flag
15273                              ? index64 : index32);
15274
15275                   *obufp++ = scale_char;
15276                   *obufp = '\0';
15277                   sprintf (scratchbuf, "%d", 1 << scale);
15278                   oappend (scratchbuf);
15279                 }
15280             }
15281           if (intel_syntax
15282               && (disp || modrm.mod != 0 || base == 5))
15283             {
15284               if (!havedisp || (bfd_signed_vma) disp >= 0)
15285                 {
15286                   *obufp++ = '+';
15287                   *obufp = '\0';
15288                 }
15289               else if (modrm.mod != 1 && disp != -disp)
15290                 {
15291                   *obufp++ = '-';
15292                   *obufp = '\0';
15293                   disp = - (bfd_signed_vma) disp;
15294                 }
15295
15296               if (havedisp)
15297                 print_displacement (scratchbuf, disp);
15298               else
15299                 print_operand_value (scratchbuf, 1, disp);
15300               oappend (scratchbuf);
15301             }
15302
15303           *obufp++ = close_char;
15304           *obufp = '\0';
15305         }
15306       else if (intel_syntax)
15307         {
15308           if (modrm.mod != 0 || base == 5)
15309             {
15310               if (!active_seg_prefix)
15311                 {
15312                   oappend (names_seg[ds_reg - es_reg]);
15313                   oappend (":");
15314                 }
15315               print_operand_value (scratchbuf, 1, disp);
15316               oappend (scratchbuf);
15317             }
15318         }
15319     }
15320   else
15321     {
15322       /* 16 bit address mode */
15323       used_prefixes |= prefixes & PREFIX_ADDR;
15324       switch (modrm.mod)
15325         {
15326         case 0:
15327           if (modrm.rm == 6)
15328             {
15329               disp = get16 ();
15330               if ((disp & 0x8000) != 0)
15331                 disp -= 0x10000;
15332             }
15333           break;
15334         case 1:
15335           FETCH_DATA (the_info, codep + 1);
15336           disp = *codep++;
15337           if ((disp & 0x80) != 0)
15338             disp -= 0x100;
15339           break;
15340         case 2:
15341           disp = get16 ();
15342           if ((disp & 0x8000) != 0)
15343             disp -= 0x10000;
15344           break;
15345         }
15346
15347       if (!intel_syntax)
15348         if (modrm.mod != 0 || modrm.rm == 6)
15349           {
15350             print_displacement (scratchbuf, disp);
15351             oappend (scratchbuf);
15352           }
15353
15354       if (modrm.mod != 0 || modrm.rm != 6)
15355         {
15356           *obufp++ = open_char;
15357           *obufp = '\0';
15358           oappend (index16[modrm.rm]);
15359           if (intel_syntax
15360               && (disp || modrm.mod != 0 || modrm.rm == 6))
15361             {
15362               if ((bfd_signed_vma) disp >= 0)
15363                 {
15364                   *obufp++ = '+';
15365                   *obufp = '\0';
15366                 }
15367               else if (modrm.mod != 1)
15368                 {
15369                   *obufp++ = '-';
15370                   *obufp = '\0';
15371                   disp = - (bfd_signed_vma) disp;
15372                 }
15373
15374               print_displacement (scratchbuf, disp);
15375               oappend (scratchbuf);
15376             }
15377
15378           *obufp++ = close_char;
15379           *obufp = '\0';
15380         }
15381       else if (intel_syntax)
15382         {
15383           if (!active_seg_prefix)
15384             {
15385               oappend (names_seg[ds_reg - es_reg]);
15386               oappend (":");
15387             }
15388           print_operand_value (scratchbuf, 1, disp & 0xffff);
15389           oappend (scratchbuf);
15390         }
15391     }
15392   if (vex.evex && vex.b
15393       && (bytemode == x_mode
15394           || bytemode == xmmq_mode
15395           || bytemode == evex_half_bcst_xmmq_mode))
15396     {
15397       if (vex.w
15398           || bytemode == xmmq_mode
15399           || bytemode == evex_half_bcst_xmmq_mode)
15400         {
15401           switch (vex.length)
15402             {
15403             case 128:
15404               oappend ("{1to2}");
15405               break;
15406             case 256:
15407               oappend ("{1to4}");
15408               break;
15409             case 512:
15410               oappend ("{1to8}");
15411               break;
15412             default:
15413               abort ();
15414             }
15415         }
15416       else
15417         {
15418           switch (vex.length)
15419             {
15420             case 128:
15421               oappend ("{1to4}");
15422               break;
15423             case 256:
15424               oappend ("{1to8}");
15425               break;
15426             case 512:
15427               oappend ("{1to16}");
15428               break;
15429             default:
15430               abort ();
15431             }
15432         }
15433     }
15434 }
15435
15436 static void
15437 OP_E (int bytemode, int sizeflag)
15438 {
15439   /* Skip mod/rm byte.  */
15440   MODRM_CHECK;
15441   codep++;
15442
15443   if (modrm.mod == 3)
15444     OP_E_register (bytemode, sizeflag);
15445   else
15446     OP_E_memory (bytemode, sizeflag);
15447 }
15448
15449 static void
15450 OP_G (int bytemode, int sizeflag)
15451 {
15452   int add = 0;
15453   USED_REX (REX_R);
15454   if (rex & REX_R)
15455     add += 8;
15456   switch (bytemode)
15457     {
15458     case b_mode:
15459       USED_REX (0);
15460       if (rex)
15461         oappend (names8rex[modrm.reg + add]);
15462       else
15463         oappend (names8[modrm.reg + add]);
15464       break;
15465     case w_mode:
15466       oappend (names16[modrm.reg + add]);
15467       break;
15468     case d_mode:
15469     case db_mode:
15470     case dw_mode:
15471       oappend (names32[modrm.reg + add]);
15472       break;
15473     case q_mode:
15474       oappend (names64[modrm.reg + add]);
15475       break;
15476     case bnd_mode:
15477       oappend (names_bnd[modrm.reg]);
15478       break;
15479     case v_mode:
15480     case dq_mode:
15481     case dqb_mode:
15482     case dqd_mode:
15483     case dqw_mode:
15484       USED_REX (REX_W);
15485       if (rex & REX_W)
15486         oappend (names64[modrm.reg + add]);
15487       else
15488         {
15489           if ((sizeflag & DFLAG) || bytemode != v_mode)
15490             oappend (names32[modrm.reg + add]);
15491           else
15492             oappend (names16[modrm.reg + add]);
15493           used_prefixes |= (prefixes & PREFIX_DATA);
15494         }
15495       break;
15496     case m_mode:
15497       if (address_mode == mode_64bit)
15498         oappend (names64[modrm.reg + add]);
15499       else
15500         oappend (names32[modrm.reg + add]);
15501       break;
15502     case mask_bd_mode:
15503     case mask_mode:
15504       if ((modrm.reg + add) > 0x7)
15505         {
15506           oappend ("(bad)");
15507           return;
15508         }
15509       oappend (names_mask[modrm.reg + add]);
15510       break;
15511     default:
15512       oappend (INTERNAL_DISASSEMBLER_ERROR);
15513       break;
15514     }
15515 }
15516
15517 static bfd_vma
15518 get64 (void)
15519 {
15520   bfd_vma x;
15521 #ifdef BFD64
15522   unsigned int a;
15523   unsigned int b;
15524
15525   FETCH_DATA (the_info, codep + 8);
15526   a = *codep++ & 0xff;
15527   a |= (*codep++ & 0xff) << 8;
15528   a |= (*codep++ & 0xff) << 16;
15529   a |= (*codep++ & 0xffu) << 24;
15530   b = *codep++ & 0xff;
15531   b |= (*codep++ & 0xff) << 8;
15532   b |= (*codep++ & 0xff) << 16;
15533   b |= (*codep++ & 0xffu) << 24;
15534   x = a + ((bfd_vma) b << 32);
15535 #else
15536   abort ();
15537   x = 0;
15538 #endif
15539   return x;
15540 }
15541
15542 static bfd_signed_vma
15543 get32 (void)
15544 {
15545   bfd_signed_vma x = 0;
15546
15547   FETCH_DATA (the_info, codep + 4);
15548   x = *codep++ & (bfd_signed_vma) 0xff;
15549   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15550   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15551   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15552   return x;
15553 }
15554
15555 static bfd_signed_vma
15556 get32s (void)
15557 {
15558   bfd_signed_vma x = 0;
15559
15560   FETCH_DATA (the_info, codep + 4);
15561   x = *codep++ & (bfd_signed_vma) 0xff;
15562   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15563   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15564   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15565
15566   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
15567
15568   return x;
15569 }
15570
15571 static int
15572 get16 (void)
15573 {
15574   int x = 0;
15575
15576   FETCH_DATA (the_info, codep + 2);
15577   x = *codep++ & 0xff;
15578   x |= (*codep++ & 0xff) << 8;
15579   return x;
15580 }
15581
15582 static void
15583 set_op (bfd_vma op, int riprel)
15584 {
15585   op_index[op_ad] = op_ad;
15586   if (address_mode == mode_64bit)
15587     {
15588       op_address[op_ad] = op;
15589       op_riprel[op_ad] = riprel;
15590     }
15591   else
15592     {
15593       /* Mask to get a 32-bit address.  */
15594       op_address[op_ad] = op & 0xffffffff;
15595       op_riprel[op_ad] = riprel & 0xffffffff;
15596     }
15597 }
15598
15599 static void
15600 OP_REG (int code, int sizeflag)
15601 {
15602   const char *s;
15603   int add;
15604
15605   switch (code)
15606     {
15607     case es_reg: case ss_reg: case cs_reg:
15608     case ds_reg: case fs_reg: case gs_reg:
15609       oappend (names_seg[code - es_reg]);
15610       return;
15611     }
15612
15613   USED_REX (REX_B);
15614   if (rex & REX_B)
15615     add = 8;
15616   else
15617     add = 0;
15618
15619   switch (code)
15620     {
15621     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15622     case sp_reg: case bp_reg: case si_reg: case di_reg:
15623       s = names16[code - ax_reg + add];
15624       break;
15625     case al_reg: case ah_reg: case cl_reg: case ch_reg:
15626     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15627       USED_REX (0);
15628       if (rex)
15629         s = names8rex[code - al_reg + add];
15630       else
15631         s = names8[code - al_reg];
15632       break;
15633     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
15634     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
15635       if (address_mode == mode_64bit
15636           && ((sizeflag & DFLAG) || (rex & REX_W)))
15637         {
15638           s = names64[code - rAX_reg + add];
15639           break;
15640         }
15641       code += eAX_reg - rAX_reg;
15642       /* Fall through.  */
15643     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15644     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15645       USED_REX (REX_W);
15646       if (rex & REX_W)
15647         s = names64[code - eAX_reg + add];
15648       else
15649         {
15650           if (sizeflag & DFLAG)
15651             s = names32[code - eAX_reg + add];
15652           else
15653             s = names16[code - eAX_reg + add];
15654           used_prefixes |= (prefixes & PREFIX_DATA);
15655         }
15656       break;
15657     default:
15658       s = INTERNAL_DISASSEMBLER_ERROR;
15659       break;
15660     }
15661   oappend (s);
15662 }
15663
15664 static void
15665 OP_IMREG (int code, int sizeflag)
15666 {
15667   const char *s;
15668
15669   switch (code)
15670     {
15671     case indir_dx_reg:
15672       if (intel_syntax)
15673         s = "dx";
15674       else
15675         s = "(%dx)";
15676       break;
15677     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15678     case sp_reg: case bp_reg: case si_reg: case di_reg:
15679       s = names16[code - ax_reg];
15680       break;
15681     case es_reg: case ss_reg: case cs_reg:
15682     case ds_reg: case fs_reg: case gs_reg:
15683       s = names_seg[code - es_reg];
15684       break;
15685     case al_reg: case ah_reg: case cl_reg: case ch_reg:
15686     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15687       USED_REX (0);
15688       if (rex)
15689         s = names8rex[code - al_reg];
15690       else
15691         s = names8[code - al_reg];
15692       break;
15693     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15694     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15695       USED_REX (REX_W);
15696       if (rex & REX_W)
15697         s = names64[code - eAX_reg];
15698       else
15699         {
15700           if (sizeflag & DFLAG)
15701             s = names32[code - eAX_reg];
15702           else
15703             s = names16[code - eAX_reg];
15704           used_prefixes |= (prefixes & PREFIX_DATA);
15705         }
15706       break;
15707     case z_mode_ax_reg:
15708       if ((rex & REX_W) || (sizeflag & DFLAG))
15709         s = *names32;
15710       else
15711         s = *names16;
15712       if (!(rex & REX_W))
15713         used_prefixes |= (prefixes & PREFIX_DATA);
15714       break;
15715     default:
15716       s = INTERNAL_DISASSEMBLER_ERROR;
15717       break;
15718     }
15719   oappend (s);
15720 }
15721
15722 static void
15723 OP_I (int bytemode, int sizeflag)
15724 {
15725   bfd_signed_vma op;
15726   bfd_signed_vma mask = -1;
15727
15728   switch (bytemode)
15729     {
15730     case b_mode:
15731       FETCH_DATA (the_info, codep + 1);
15732       op = *codep++;
15733       mask = 0xff;
15734       break;
15735     case q_mode:
15736       if (address_mode == mode_64bit)
15737         {
15738           op = get32s ();
15739           break;
15740         }
15741       /* Fall through.  */
15742     case v_mode:
15743       USED_REX (REX_W);
15744       if (rex & REX_W)
15745         op = get32s ();
15746       else
15747         {
15748           if (sizeflag & DFLAG)
15749             {
15750               op = get32 ();
15751               mask = 0xffffffff;
15752             }
15753           else
15754             {
15755               op = get16 ();
15756               mask = 0xfffff;
15757             }
15758           used_prefixes |= (prefixes & PREFIX_DATA);
15759         }
15760       break;
15761     case w_mode:
15762       mask = 0xfffff;
15763       op = get16 ();
15764       break;
15765     case const_1_mode:
15766       if (intel_syntax)
15767         oappend ("1");
15768       return;
15769     default:
15770       oappend (INTERNAL_DISASSEMBLER_ERROR);
15771       return;
15772     }
15773
15774   op &= mask;
15775   scratchbuf[0] = '$';
15776   print_operand_value (scratchbuf + 1, 1, op);
15777   oappend_maybe_intel (scratchbuf);
15778   scratchbuf[0] = '\0';
15779 }
15780
15781 static void
15782 OP_I64 (int bytemode, int sizeflag)
15783 {
15784   bfd_signed_vma op;
15785   bfd_signed_vma mask = -1;
15786
15787   if (address_mode != mode_64bit)
15788     {
15789       OP_I (bytemode, sizeflag);
15790       return;
15791     }
15792
15793   switch (bytemode)
15794     {
15795     case b_mode:
15796       FETCH_DATA (the_info, codep + 1);
15797       op = *codep++;
15798       mask = 0xff;
15799       break;
15800     case v_mode:
15801       USED_REX (REX_W);
15802       if (rex & REX_W)
15803         op = get64 ();
15804       else
15805         {
15806           if (sizeflag & DFLAG)
15807             {
15808               op = get32 ();
15809               mask = 0xffffffff;
15810             }
15811           else
15812             {
15813               op = get16 ();
15814               mask = 0xfffff;
15815             }
15816           used_prefixes |= (prefixes & PREFIX_DATA);
15817         }
15818       break;
15819     case w_mode:
15820       mask = 0xfffff;
15821       op = get16 ();
15822       break;
15823     default:
15824       oappend (INTERNAL_DISASSEMBLER_ERROR);
15825       return;
15826     }
15827
15828   op &= mask;
15829   scratchbuf[0] = '$';
15830   print_operand_value (scratchbuf + 1, 1, op);
15831   oappend_maybe_intel (scratchbuf);
15832   scratchbuf[0] = '\0';
15833 }
15834
15835 static void
15836 OP_sI (int bytemode, int sizeflag)
15837 {
15838   bfd_signed_vma op;
15839
15840   switch (bytemode)
15841     {
15842     case b_mode:
15843     case b_T_mode:
15844       FETCH_DATA (the_info, codep + 1);
15845       op = *codep++;
15846       if ((op & 0x80) != 0)
15847         op -= 0x100;
15848       if (bytemode == b_T_mode)
15849         {
15850           if (address_mode != mode_64bit
15851               || !((sizeflag & DFLAG) || (rex & REX_W)))
15852             {
15853               /* The operand-size prefix is overridden by a REX prefix.  */
15854               if ((sizeflag & DFLAG) || (rex & REX_W))
15855                 op &= 0xffffffff;
15856               else
15857                 op &= 0xffff;
15858           }
15859         }
15860       else
15861         {
15862           if (!(rex & REX_W))
15863             {
15864               if (sizeflag & DFLAG)
15865                 op &= 0xffffffff;
15866               else
15867                 op &= 0xffff;
15868             }
15869         }
15870       break;
15871     case v_mode:
15872       /* The operand-size prefix is overridden by a REX prefix.  */
15873       if ((sizeflag & DFLAG) || (rex & REX_W))
15874         op = get32s ();
15875       else
15876         op = get16 ();
15877       break;
15878     default:
15879       oappend (INTERNAL_DISASSEMBLER_ERROR);
15880       return;
15881     }
15882
15883   scratchbuf[0] = '$';
15884   print_operand_value (scratchbuf + 1, 1, op);
15885   oappend_maybe_intel (scratchbuf);
15886 }
15887
15888 static void
15889 OP_J (int bytemode, int sizeflag)
15890 {
15891   bfd_vma disp;
15892   bfd_vma mask = -1;
15893   bfd_vma segment = 0;
15894
15895   switch (bytemode)
15896     {
15897     case b_mode:
15898       FETCH_DATA (the_info, codep + 1);
15899       disp = *codep++;
15900       if ((disp & 0x80) != 0)
15901         disp -= 0x100;
15902       break;
15903     case v_mode:
15904       if (isa64 == amd64)
15905         USED_REX (REX_W);
15906       if ((sizeflag & DFLAG)
15907           || (address_mode == mode_64bit
15908               && (isa64 != amd64 || (rex & REX_W))))
15909         disp = get32s ();
15910       else
15911         {
15912           disp = get16 ();
15913           if ((disp & 0x8000) != 0)
15914             disp -= 0x10000;
15915           /* In 16bit mode, address is wrapped around at 64k within
15916              the same segment.  Otherwise, a data16 prefix on a jump
15917              instruction means that the pc is masked to 16 bits after
15918              the displacement is added!  */
15919           mask = 0xffff;
15920           if ((prefixes & PREFIX_DATA) == 0)
15921             segment = ((start_pc + (codep - start_codep))
15922                        & ~((bfd_vma) 0xffff));
15923         }
15924       if (address_mode != mode_64bit
15925           || (isa64 == amd64 && !(rex & REX_W)))
15926         used_prefixes |= (prefixes & PREFIX_DATA);
15927       break;
15928     default:
15929       oappend (INTERNAL_DISASSEMBLER_ERROR);
15930       return;
15931     }
15932   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
15933   set_op (disp, 0);
15934   print_operand_value (scratchbuf, 1, disp);
15935   oappend (scratchbuf);
15936 }
15937
15938 static void
15939 OP_SEG (int bytemode, int sizeflag)
15940 {
15941   if (bytemode == w_mode)
15942     oappend (names_seg[modrm.reg]);
15943   else
15944     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
15945 }
15946
15947 static void
15948 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
15949 {
15950   int seg, offset;
15951
15952   if (sizeflag & DFLAG)
15953     {
15954       offset = get32 ();
15955       seg = get16 ();
15956     }
15957   else
15958     {
15959       offset = get16 ();
15960       seg = get16 ();
15961     }
15962   used_prefixes |= (prefixes & PREFIX_DATA);
15963   if (intel_syntax)
15964     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
15965   else
15966     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
15967   oappend (scratchbuf);
15968 }
15969
15970 static void
15971 OP_OFF (int bytemode, int sizeflag)
15972 {
15973   bfd_vma off;
15974
15975   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
15976     intel_operand_size (bytemode, sizeflag);
15977   append_seg ();
15978
15979   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
15980     off = get32 ();
15981   else
15982     off = get16 ();
15983
15984   if (intel_syntax)
15985     {
15986       if (!active_seg_prefix)
15987         {
15988           oappend (names_seg[ds_reg - es_reg]);
15989           oappend (":");
15990         }
15991     }
15992   print_operand_value (scratchbuf, 1, off);
15993   oappend (scratchbuf);
15994 }
15995
15996 static void
15997 OP_OFF64 (int bytemode, int sizeflag)
15998 {
15999   bfd_vma off;
16000
16001   if (address_mode != mode_64bit
16002       || (prefixes & PREFIX_ADDR))
16003     {
16004       OP_OFF (bytemode, sizeflag);
16005       return;
16006     }
16007
16008   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
16009     intel_operand_size (bytemode, sizeflag);
16010   append_seg ();
16011
16012   off = get64 ();
16013
16014   if (intel_syntax)
16015     {
16016       if (!active_seg_prefix)
16017         {
16018           oappend (names_seg[ds_reg - es_reg]);
16019           oappend (":");
16020         }
16021     }
16022   print_operand_value (scratchbuf, 1, off);
16023   oappend (scratchbuf);
16024 }
16025
16026 static void
16027 ptr_reg (int code, int sizeflag)
16028 {
16029   const char *s;
16030
16031   *obufp++ = open_char;
16032   used_prefixes |= (prefixes & PREFIX_ADDR);
16033   if (address_mode == mode_64bit)
16034     {
16035       if (!(sizeflag & AFLAG))
16036         s = names32[code - eAX_reg];
16037       else
16038         s = names64[code - eAX_reg];
16039     }
16040   else if (sizeflag & AFLAG)
16041     s = names32[code - eAX_reg];
16042   else
16043     s = names16[code - eAX_reg];
16044   oappend (s);
16045   *obufp++ = close_char;
16046   *obufp = 0;
16047 }
16048
16049 static void
16050 OP_ESreg (int code, int sizeflag)
16051 {
16052   if (intel_syntax)
16053     {
16054       switch (codep[-1])
16055         {
16056         case 0x6d:      /* insw/insl */
16057           intel_operand_size (z_mode, sizeflag);
16058           break;
16059         case 0xa5:      /* movsw/movsl/movsq */
16060         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
16061         case 0xab:      /* stosw/stosl */
16062         case 0xaf:      /* scasw/scasl */
16063           intel_operand_size (v_mode, sizeflag);
16064           break;
16065         default:
16066           intel_operand_size (b_mode, sizeflag);
16067         }
16068     }
16069   oappend_maybe_intel ("%es:");
16070   ptr_reg (code, sizeflag);
16071 }
16072
16073 static void
16074 OP_DSreg (int code, int sizeflag)
16075 {
16076   if (intel_syntax)
16077     {
16078       switch (codep[-1])
16079         {
16080         case 0x6f:      /* outsw/outsl */
16081           intel_operand_size (z_mode, sizeflag);
16082           break;
16083         case 0xa5:      /* movsw/movsl/movsq */
16084         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
16085         case 0xad:      /* lodsw/lodsl/lodsq */
16086           intel_operand_size (v_mode, sizeflag);
16087           break;
16088         default:
16089           intel_operand_size (b_mode, sizeflag);
16090         }
16091     }
16092   /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
16093      default segment register DS is printed.  */
16094   if (!active_seg_prefix)
16095     active_seg_prefix = PREFIX_DS;
16096   append_seg ();
16097   ptr_reg (code, sizeflag);
16098 }
16099
16100 static void
16101 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16102 {
16103   int add;
16104   if (rex & REX_R)
16105     {
16106       USED_REX (REX_R);
16107       add = 8;
16108     }
16109   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
16110     {
16111       all_prefixes[last_lock_prefix] = 0;
16112       used_prefixes |= PREFIX_LOCK;
16113       add = 8;
16114     }
16115   else
16116     add = 0;
16117   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
16118   oappend_maybe_intel (scratchbuf);
16119 }
16120
16121 static void
16122 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16123 {
16124   int add;
16125   USED_REX (REX_R);
16126   if (rex & REX_R)
16127     add = 8;
16128   else
16129     add = 0;
16130   if (intel_syntax)
16131     sprintf (scratchbuf, "db%d", modrm.reg + add);
16132   else
16133     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
16134   oappend (scratchbuf);
16135 }
16136
16137 static void
16138 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16139 {
16140   sprintf (scratchbuf, "%%tr%d", modrm.reg);
16141   oappend_maybe_intel (scratchbuf);
16142 }
16143
16144 static void
16145 OP_R (int bytemode, int sizeflag)
16146 {
16147   /* Skip mod/rm byte.  */
16148   MODRM_CHECK;
16149   codep++;
16150   OP_E_register (bytemode, sizeflag);
16151 }
16152
16153 static void
16154 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16155 {
16156   int reg = modrm.reg;
16157   const char **names;
16158
16159   used_prefixes |= (prefixes & PREFIX_DATA);
16160   if (prefixes & PREFIX_DATA)
16161     {
16162       names = names_xmm;
16163       USED_REX (REX_R);
16164       if (rex & REX_R)
16165         reg += 8;
16166     }
16167   else
16168     names = names_mm;
16169   oappend (names[reg]);
16170 }
16171
16172 static void
16173 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16174 {
16175   int reg = modrm.reg;
16176   const char **names;
16177
16178   USED_REX (REX_R);
16179   if (rex & REX_R)
16180     reg += 8;
16181   if (vex.evex)
16182     {
16183       if (!vex.r)
16184         reg += 16;
16185     }
16186
16187   if (need_vex
16188       && bytemode != xmm_mode
16189       && bytemode != xmmq_mode
16190       && bytemode != evex_half_bcst_xmmq_mode
16191       && bytemode != ymm_mode
16192       && bytemode != scalar_mode)
16193     {
16194       switch (vex.length)
16195         {
16196         case 128:
16197           names = names_xmm;
16198           break;
16199         case 256:
16200           if (vex.w
16201               || (bytemode != vex_vsib_q_w_dq_mode
16202                   && bytemode != vex_vsib_q_w_d_mode))
16203             names = names_ymm;
16204           else
16205             names = names_xmm;
16206           break;
16207         case 512:
16208           names = names_zmm;
16209           break;
16210         default:
16211           abort ();
16212         }
16213     }
16214   else if (bytemode == xmmq_mode
16215            || bytemode == evex_half_bcst_xmmq_mode)
16216     {
16217       switch (vex.length)
16218         {
16219         case 128:
16220         case 256:
16221           names = names_xmm;
16222           break;
16223         case 512:
16224           names = names_ymm;
16225           break;
16226         default:
16227           abort ();
16228         }
16229     }
16230   else if (bytemode == ymm_mode)
16231     names = names_ymm;
16232   else
16233     names = names_xmm;
16234   oappend (names[reg]);
16235 }
16236
16237 static void
16238 OP_EM (int bytemode, int sizeflag)
16239 {
16240   int reg;
16241   const char **names;
16242
16243   if (modrm.mod != 3)
16244     {
16245       if (intel_syntax
16246           && (bytemode == v_mode || bytemode == v_swap_mode))
16247         {
16248           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16249           used_prefixes |= (prefixes & PREFIX_DATA);
16250         }
16251       OP_E (bytemode, sizeflag);
16252       return;
16253     }
16254
16255   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
16256     swap_operand ();
16257
16258   /* Skip mod/rm byte.  */
16259   MODRM_CHECK;
16260   codep++;
16261   used_prefixes |= (prefixes & PREFIX_DATA);
16262   reg = modrm.rm;
16263   if (prefixes & PREFIX_DATA)
16264     {
16265       names = names_xmm;
16266       USED_REX (REX_B);
16267       if (rex & REX_B)
16268         reg += 8;
16269     }
16270   else
16271     names = names_mm;
16272   oappend (names[reg]);
16273 }
16274
16275 /* cvt* are the only instructions in sse2 which have
16276    both SSE and MMX operands and also have 0x66 prefix
16277    in their opcode. 0x66 was originally used to differentiate
16278    between SSE and MMX instruction(operands). So we have to handle the
16279    cvt* separately using OP_EMC and OP_MXC */
16280 static void
16281 OP_EMC (int bytemode, int sizeflag)
16282 {
16283   if (modrm.mod != 3)
16284     {
16285       if (intel_syntax && bytemode == v_mode)
16286         {
16287           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16288           used_prefixes |= (prefixes & PREFIX_DATA);
16289         }
16290       OP_E (bytemode, sizeflag);
16291       return;
16292     }
16293
16294   /* Skip mod/rm byte.  */
16295   MODRM_CHECK;
16296   codep++;
16297   used_prefixes |= (prefixes & PREFIX_DATA);
16298   oappend (names_mm[modrm.rm]);
16299 }
16300
16301 static void
16302 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16303 {
16304   used_prefixes |= (prefixes & PREFIX_DATA);
16305   oappend (names_mm[modrm.reg]);
16306 }
16307
16308 static void
16309 OP_EX (int bytemode, int sizeflag)
16310 {
16311   int reg;
16312   const char **names;
16313
16314   /* Skip mod/rm byte.  */
16315   MODRM_CHECK;
16316   codep++;
16317
16318   if (modrm.mod != 3)
16319     {
16320       OP_E_memory (bytemode, sizeflag);
16321       return;
16322     }
16323
16324   reg = modrm.rm;
16325   USED_REX (REX_B);
16326   if (rex & REX_B)
16327     reg += 8;
16328   if (vex.evex)
16329     {
16330       USED_REX (REX_X);
16331       if ((rex & REX_X))
16332         reg += 16;
16333     }
16334
16335   if ((sizeflag & SUFFIX_ALWAYS)
16336       && (bytemode == x_swap_mode
16337           || bytemode == d_swap_mode
16338           || bytemode == d_scalar_swap_mode
16339           || bytemode == q_swap_mode
16340           || bytemode == q_scalar_swap_mode))
16341     swap_operand ();
16342
16343   if (need_vex
16344       && bytemode != xmm_mode
16345       && bytemode != xmmdw_mode
16346       && bytemode != xmmqd_mode
16347       && bytemode != xmm_mb_mode
16348       && bytemode != xmm_mw_mode
16349       && bytemode != xmm_md_mode
16350       && bytemode != xmm_mq_mode
16351       && bytemode != xmm_mdq_mode
16352       && bytemode != xmmq_mode
16353       && bytemode != evex_half_bcst_xmmq_mode
16354       && bytemode != ymm_mode
16355       && bytemode != d_scalar_mode
16356       && bytemode != d_scalar_swap_mode
16357       && bytemode != q_scalar_mode
16358       && bytemode != q_scalar_swap_mode
16359       && bytemode != vex_scalar_w_dq_mode)
16360     {
16361       switch (vex.length)
16362         {
16363         case 128:
16364           names = names_xmm;
16365           break;
16366         case 256:
16367           names = names_ymm;
16368           break;
16369         case 512:
16370           names = names_zmm;
16371           break;
16372         default:
16373           abort ();
16374         }
16375     }
16376   else if (bytemode == xmmq_mode
16377            || bytemode == evex_half_bcst_xmmq_mode)
16378     {
16379       switch (vex.length)
16380         {
16381         case 128:
16382         case 256:
16383           names = names_xmm;
16384           break;
16385         case 512:
16386           names = names_ymm;
16387           break;
16388         default:
16389           abort ();
16390         }
16391     }
16392   else if (bytemode == ymm_mode)
16393     names = names_ymm;
16394   else
16395     names = names_xmm;
16396   oappend (names[reg]);
16397 }
16398
16399 static void
16400 OP_MS (int bytemode, int sizeflag)
16401 {
16402   if (modrm.mod == 3)
16403     OP_EM (bytemode, sizeflag);
16404   else
16405     BadOp ();
16406 }
16407
16408 static void
16409 OP_XS (int bytemode, int sizeflag)
16410 {
16411   if (modrm.mod == 3)
16412     OP_EX (bytemode, sizeflag);
16413   else
16414     BadOp ();
16415 }
16416
16417 static void
16418 OP_M (int bytemode, int sizeflag)
16419 {
16420   if (modrm.mod == 3)
16421     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
16422     BadOp ();
16423   else
16424     OP_E (bytemode, sizeflag);
16425 }
16426
16427 static void
16428 OP_0f07 (int bytemode, int sizeflag)
16429 {
16430   if (modrm.mod != 3 || modrm.rm != 0)
16431     BadOp ();
16432   else
16433     OP_E (bytemode, sizeflag);
16434 }
16435
16436 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
16437    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
16438
16439 static void
16440 NOP_Fixup1 (int bytemode, int sizeflag)
16441 {
16442   if ((prefixes & PREFIX_DATA) != 0
16443       || (rex != 0
16444           && rex != 0x48
16445           && address_mode == mode_64bit))
16446     OP_REG (bytemode, sizeflag);
16447   else
16448     strcpy (obuf, "nop");
16449 }
16450
16451 static void
16452 NOP_Fixup2 (int bytemode, int sizeflag)
16453 {
16454   if ((prefixes & PREFIX_DATA) != 0
16455       || (rex != 0
16456           && rex != 0x48
16457           && address_mode == mode_64bit))
16458     OP_IMREG (bytemode, sizeflag);
16459 }
16460
16461 static const char *const Suffix3DNow[] = {
16462 /* 00 */        NULL,           NULL,           NULL,           NULL,
16463 /* 04 */        NULL,           NULL,           NULL,           NULL,
16464 /* 08 */        NULL,           NULL,           NULL,           NULL,
16465 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
16466 /* 10 */        NULL,           NULL,           NULL,           NULL,
16467 /* 14 */        NULL,           NULL,           NULL,           NULL,
16468 /* 18 */        NULL,           NULL,           NULL,           NULL,
16469 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
16470 /* 20 */        NULL,           NULL,           NULL,           NULL,
16471 /* 24 */        NULL,           NULL,           NULL,           NULL,
16472 /* 28 */        NULL,           NULL,           NULL,           NULL,
16473 /* 2C */        NULL,           NULL,           NULL,           NULL,
16474 /* 30 */        NULL,           NULL,           NULL,           NULL,
16475 /* 34 */        NULL,           NULL,           NULL,           NULL,
16476 /* 38 */        NULL,           NULL,           NULL,           NULL,
16477 /* 3C */        NULL,           NULL,           NULL,           NULL,
16478 /* 40 */        NULL,           NULL,           NULL,           NULL,
16479 /* 44 */        NULL,           NULL,           NULL,           NULL,
16480 /* 48 */        NULL,           NULL,           NULL,           NULL,
16481 /* 4C */        NULL,           NULL,           NULL,           NULL,
16482 /* 50 */        NULL,           NULL,           NULL,           NULL,
16483 /* 54 */        NULL,           NULL,           NULL,           NULL,
16484 /* 58 */        NULL,           NULL,           NULL,           NULL,
16485 /* 5C */        NULL,           NULL,           NULL,           NULL,
16486 /* 60 */        NULL,           NULL,           NULL,           NULL,
16487 /* 64 */        NULL,           NULL,           NULL,           NULL,
16488 /* 68 */        NULL,           NULL,           NULL,           NULL,
16489 /* 6C */        NULL,           NULL,           NULL,           NULL,
16490 /* 70 */        NULL,           NULL,           NULL,           NULL,
16491 /* 74 */        NULL,           NULL,           NULL,           NULL,
16492 /* 78 */        NULL,           NULL,           NULL,           NULL,
16493 /* 7C */        NULL,           NULL,           NULL,           NULL,
16494 /* 80 */        NULL,           NULL,           NULL,           NULL,
16495 /* 84 */        NULL,           NULL,           NULL,           NULL,
16496 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
16497 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
16498 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
16499 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
16500 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
16501 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
16502 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
16503 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
16504 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
16505 /* AC */        NULL,           NULL,           "pfacc",        NULL,
16506 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
16507 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
16508 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
16509 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
16510 /* C0 */        NULL,           NULL,           NULL,           NULL,
16511 /* C4 */        NULL,           NULL,           NULL,           NULL,
16512 /* C8 */        NULL,           NULL,           NULL,           NULL,
16513 /* CC */        NULL,           NULL,           NULL,           NULL,
16514 /* D0 */        NULL,           NULL,           NULL,           NULL,
16515 /* D4 */        NULL,           NULL,           NULL,           NULL,
16516 /* D8 */        NULL,           NULL,           NULL,           NULL,
16517 /* DC */        NULL,           NULL,           NULL,           NULL,
16518 /* E0 */        NULL,           NULL,           NULL,           NULL,
16519 /* E4 */        NULL,           NULL,           NULL,           NULL,
16520 /* E8 */        NULL,           NULL,           NULL,           NULL,
16521 /* EC */        NULL,           NULL,           NULL,           NULL,
16522 /* F0 */        NULL,           NULL,           NULL,           NULL,
16523 /* F4 */        NULL,           NULL,           NULL,           NULL,
16524 /* F8 */        NULL,           NULL,           NULL,           NULL,
16525 /* FC */        NULL,           NULL,           NULL,           NULL,
16526 };
16527
16528 static void
16529 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16530 {
16531   const char *mnemonic;
16532
16533   FETCH_DATA (the_info, codep + 1);
16534   /* AMD 3DNow! instructions are specified by an opcode suffix in the
16535      place where an 8-bit immediate would normally go.  ie. the last
16536      byte of the instruction.  */
16537   obufp = mnemonicendp;
16538   mnemonic = Suffix3DNow[*codep++ & 0xff];
16539   if (mnemonic)
16540     oappend (mnemonic);
16541   else
16542     {
16543       /* Since a variable sized modrm/sib chunk is between the start
16544          of the opcode (0x0f0f) and the opcode suffix, we need to do
16545          all the modrm processing first, and don't know until now that
16546          we have a bad opcode.  This necessitates some cleaning up.  */
16547       op_out[0][0] = '\0';
16548       op_out[1][0] = '\0';
16549       BadOp ();
16550     }
16551   mnemonicendp = obufp;
16552 }
16553
16554 static struct op simd_cmp_op[] =
16555 {
16556   { STRING_COMMA_LEN ("eq") },
16557   { STRING_COMMA_LEN ("lt") },
16558   { STRING_COMMA_LEN ("le") },
16559   { STRING_COMMA_LEN ("unord") },
16560   { STRING_COMMA_LEN ("neq") },
16561   { STRING_COMMA_LEN ("nlt") },
16562   { STRING_COMMA_LEN ("nle") },
16563   { STRING_COMMA_LEN ("ord") }
16564 };
16565
16566 static void
16567 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16568 {
16569   unsigned int cmp_type;
16570
16571   FETCH_DATA (the_info, codep + 1);
16572   cmp_type = *codep++ & 0xff;
16573   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
16574     {
16575       char suffix [3];
16576       char *p = mnemonicendp - 2;
16577       suffix[0] = p[0];
16578       suffix[1] = p[1];
16579       suffix[2] = '\0';
16580       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16581       mnemonicendp += simd_cmp_op[cmp_type].len;
16582     }
16583   else
16584     {
16585       /* We have a reserved extension byte.  Output it directly.  */
16586       scratchbuf[0] = '$';
16587       print_operand_value (scratchbuf + 1, 1, cmp_type);
16588       oappend_maybe_intel (scratchbuf);
16589       scratchbuf[0] = '\0';
16590     }
16591 }
16592
16593 static void
16594 OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED,
16595           int sizeflag ATTRIBUTE_UNUSED)
16596 {
16597   /* mwaitx %eax,%ecx,%ebx */
16598   if (!intel_syntax)
16599     {
16600       const char **names = (address_mode == mode_64bit
16601                             ? names64 : names32);
16602       strcpy (op_out[0], names[0]);
16603       strcpy (op_out[1], names[1]);
16604       strcpy (op_out[2], names[3]);
16605       two_source_ops = 1;
16606     }
16607   /* Skip mod/rm byte.  */
16608   MODRM_CHECK;
16609   codep++;
16610 }
16611
16612 static void
16613 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
16614           int sizeflag ATTRIBUTE_UNUSED)
16615 {
16616   /* mwait %eax,%ecx  */
16617   if (!intel_syntax)
16618     {
16619       const char **names = (address_mode == mode_64bit
16620                             ? names64 : names32);
16621       strcpy (op_out[0], names[0]);
16622       strcpy (op_out[1], names[1]);
16623       two_source_ops = 1;
16624     }
16625   /* Skip mod/rm byte.  */
16626   MODRM_CHECK;
16627   codep++;
16628 }
16629
16630 static void
16631 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
16632             int sizeflag ATTRIBUTE_UNUSED)
16633 {
16634   /* monitor %eax,%ecx,%edx"  */
16635   if (!intel_syntax)
16636     {
16637       const char **op1_names;
16638       const char **names = (address_mode == mode_64bit
16639                             ? names64 : names32);
16640
16641       if (!(prefixes & PREFIX_ADDR))
16642         op1_names = (address_mode == mode_16bit
16643                      ? names16 : names);
16644       else
16645         {
16646           /* Remove "addr16/addr32".  */
16647           all_prefixes[last_addr_prefix] = 0;
16648           op1_names = (address_mode != mode_32bit
16649                        ? names32 : names16);
16650           used_prefixes |= PREFIX_ADDR;
16651         }
16652       strcpy (op_out[0], op1_names[0]);
16653       strcpy (op_out[1], names[1]);
16654       strcpy (op_out[2], names[2]);
16655       two_source_ops = 1;
16656     }
16657   /* Skip mod/rm byte.  */
16658   MODRM_CHECK;
16659   codep++;
16660 }
16661
16662 static void
16663 BadOp (void)
16664 {
16665   /* Throw away prefixes and 1st. opcode byte.  */
16666   codep = insn_codep + 1;
16667   oappend ("(bad)");
16668 }
16669
16670 static void
16671 REP_Fixup (int bytemode, int sizeflag)
16672 {
16673   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
16674      lods and stos.  */
16675   if (prefixes & PREFIX_REPZ)
16676     all_prefixes[last_repz_prefix] = REP_PREFIX;
16677
16678   switch (bytemode)
16679     {
16680     case al_reg:
16681     case eAX_reg:
16682     case indir_dx_reg:
16683       OP_IMREG (bytemode, sizeflag);
16684       break;
16685     case eDI_reg:
16686       OP_ESreg (bytemode, sizeflag);
16687       break;
16688     case eSI_reg:
16689       OP_DSreg (bytemode, sizeflag);
16690       break;
16691     default:
16692       abort ();
16693       break;
16694     }
16695 }
16696
16697 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
16698    "bnd".  */
16699
16700 static void
16701 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16702 {
16703   if (prefixes & PREFIX_REPNZ)
16704     all_prefixes[last_repnz_prefix] = BND_PREFIX;
16705 }
16706
16707 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
16708    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
16709  */
16710
16711 static void
16712 HLE_Fixup1 (int bytemode, int sizeflag)
16713 {
16714   if (modrm.mod != 3
16715       && (prefixes & PREFIX_LOCK) != 0)
16716     {
16717       if (prefixes & PREFIX_REPZ)
16718         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16719       if (prefixes & PREFIX_REPNZ)
16720         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16721     }
16722
16723   OP_E (bytemode, sizeflag);
16724 }
16725
16726 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
16727    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
16728  */
16729
16730 static void
16731 HLE_Fixup2 (int bytemode, int sizeflag)
16732 {
16733   if (modrm.mod != 3)
16734     {
16735       if (prefixes & PREFIX_REPZ)
16736         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16737       if (prefixes & PREFIX_REPNZ)
16738         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16739     }
16740
16741   OP_E (bytemode, sizeflag);
16742 }
16743
16744 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
16745    "xrelease" for memory operand.  No check for LOCK prefix.   */
16746
16747 static void
16748 HLE_Fixup3 (int bytemode, int sizeflag)
16749 {
16750   if (modrm.mod != 3
16751       && last_repz_prefix > last_repnz_prefix
16752       && (prefixes & PREFIX_REPZ) != 0)
16753     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16754
16755   OP_E (bytemode, sizeflag);
16756 }
16757
16758 static void
16759 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
16760 {
16761   USED_REX (REX_W);
16762   if (rex & REX_W)
16763     {
16764       /* Change cmpxchg8b to cmpxchg16b.  */
16765       char *p = mnemonicendp - 2;
16766       mnemonicendp = stpcpy (p, "16b");
16767       bytemode = o_mode;
16768     }
16769   else if ((prefixes & PREFIX_LOCK) != 0)
16770     {
16771       if (prefixes & PREFIX_REPZ)
16772         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16773       if (prefixes & PREFIX_REPNZ)
16774         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16775     }
16776
16777   OP_M (bytemode, sizeflag);
16778 }
16779
16780 static void
16781 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
16782 {
16783   const char **names;
16784
16785   if (need_vex)
16786     {
16787       switch (vex.length)
16788         {
16789         case 128:
16790           names = names_xmm;
16791           break;
16792         case 256:
16793           names = names_ymm;
16794           break;
16795         default:
16796           abort ();
16797         }
16798     }
16799   else
16800     names = names_xmm;
16801   oappend (names[reg]);
16802 }
16803
16804 static void
16805 CRC32_Fixup (int bytemode, int sizeflag)
16806 {
16807   /* Add proper suffix to "crc32".  */
16808   char *p = mnemonicendp;
16809
16810   switch (bytemode)
16811     {
16812     case b_mode:
16813       if (intel_syntax)
16814         goto skip;
16815
16816       *p++ = 'b';
16817       break;
16818     case v_mode:
16819       if (intel_syntax)
16820         goto skip;
16821
16822       USED_REX (REX_W);
16823       if (rex & REX_W)
16824         *p++ = 'q';
16825       else
16826         {
16827           if (sizeflag & DFLAG)
16828             *p++ = 'l';
16829           else
16830             *p++ = 'w';
16831           used_prefixes |= (prefixes & PREFIX_DATA);
16832         }
16833       break;
16834     default:
16835       oappend (INTERNAL_DISASSEMBLER_ERROR);
16836       break;
16837     }
16838   mnemonicendp = p;
16839   *p = '\0';
16840
16841 skip:
16842   if (modrm.mod == 3)
16843     {
16844       int add;
16845
16846       /* Skip mod/rm byte.  */
16847       MODRM_CHECK;
16848       codep++;
16849
16850       USED_REX (REX_B);
16851       add = (rex & REX_B) ? 8 : 0;
16852       if (bytemode == b_mode)
16853         {
16854           USED_REX (0);
16855           if (rex)
16856             oappend (names8rex[modrm.rm + add]);
16857           else
16858             oappend (names8[modrm.rm + add]);
16859         }
16860       else
16861         {
16862           USED_REX (REX_W);
16863           if (rex & REX_W)
16864             oappend (names64[modrm.rm + add]);
16865           else if ((prefixes & PREFIX_DATA))
16866             oappend (names16[modrm.rm + add]);
16867           else
16868             oappend (names32[modrm.rm + add]);
16869         }
16870     }
16871   else
16872     OP_E (bytemode, sizeflag);
16873 }
16874
16875 static void
16876 FXSAVE_Fixup (int bytemode, int sizeflag)
16877 {
16878   /* Add proper suffix to "fxsave" and "fxrstor".  */
16879   USED_REX (REX_W);
16880   if (rex & REX_W)
16881     {
16882       char *p = mnemonicendp;
16883       *p++ = '6';
16884       *p++ = '4';
16885       *p = '\0';
16886       mnemonicendp = p;
16887     }
16888   OP_M (bytemode, sizeflag);
16889 }
16890
16891 static void
16892 PCMPESTR_Fixup (int bytemode, int sizeflag)
16893 {
16894   /* Add proper suffix to "{,v}pcmpestr{i,m}".  */
16895   if (!intel_syntax)
16896     {
16897       char *p = mnemonicendp;
16898
16899       USED_REX (REX_W);
16900       if (rex & REX_W)
16901         *p++ = 'q';
16902       else if (sizeflag & SUFFIX_ALWAYS)
16903         *p++ = 'l';
16904
16905       *p = '\0';
16906       mnemonicendp = p;
16907     }
16908
16909   OP_EX (bytemode, sizeflag);
16910 }
16911
16912 /* Display the destination register operand for instructions with
16913    VEX. */
16914
16915 static void
16916 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16917 {
16918   int reg;
16919   const char **names;
16920
16921   if (!need_vex)
16922     abort ();
16923
16924   if (!need_vex_reg)
16925     return;
16926
16927   reg = vex.register_specifier;
16928   if (vex.evex)
16929     {
16930       if (!vex.v)
16931         reg += 16;
16932     }
16933
16934   if (bytemode == vex_scalar_mode)
16935     {
16936       oappend (names_xmm[reg]);
16937       return;
16938     }
16939
16940   switch (vex.length)
16941     {
16942     case 128:
16943       switch (bytemode)
16944         {
16945         case vex_mode:
16946         case vex128_mode:
16947         case vex_vsib_q_w_dq_mode:
16948         case vex_vsib_q_w_d_mode:
16949           names = names_xmm;
16950           break;
16951         case dq_mode:
16952           if (vex.w)
16953             names = names64;
16954           else
16955             names = names32;
16956           break;
16957         case mask_bd_mode:
16958         case mask_mode:
16959           if (reg > 0x7)
16960             {
16961               oappend ("(bad)");
16962               return;
16963             }
16964           names = names_mask;
16965           break;
16966         default:
16967           abort ();
16968           return;
16969         }
16970       break;
16971     case 256:
16972       switch (bytemode)
16973         {
16974         case vex_mode:
16975         case vex256_mode:
16976           names = names_ymm;
16977           break;
16978         case vex_vsib_q_w_dq_mode:
16979         case vex_vsib_q_w_d_mode:
16980           names = vex.w ? names_ymm : names_xmm;
16981           break;
16982         case mask_bd_mode:
16983         case mask_mode:
16984           if (reg > 0x7)
16985             {
16986               oappend ("(bad)");
16987               return;
16988             }
16989           names = names_mask;
16990           break;
16991         default:
16992           /* See PR binutils/20893 for a reproducer.  */
16993           oappend ("(bad)");
16994           return;
16995         }
16996       break;
16997     case 512:
16998       names = names_zmm;
16999       break;
17000     default:
17001       abort ();
17002       break;
17003     }
17004   oappend (names[reg]);
17005 }
17006
17007 /* Get the VEX immediate byte without moving codep.  */
17008
17009 static unsigned char
17010 get_vex_imm8 (int sizeflag, int opnum)
17011 {
17012   int bytes_before_imm = 0;
17013
17014   if (modrm.mod != 3)
17015     {
17016       /* There are SIB/displacement bytes.  */
17017       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
17018         {
17019           /* 32/64 bit address mode */
17020           int base = modrm.rm;
17021
17022           /* Check SIB byte.  */
17023           if (base == 4)
17024             {
17025               FETCH_DATA (the_info, codep + 1);
17026               base = *codep & 7;
17027               /* When decoding the third source, don't increase
17028                  bytes_before_imm as this has already been incremented
17029                  by one in OP_E_memory while decoding the second
17030                  source operand.  */
17031               if (opnum == 0)
17032                 bytes_before_imm++;
17033             }
17034
17035           /* Don't increase bytes_before_imm when decoding the third source,
17036              it has already been incremented by OP_E_memory while decoding
17037              the second source operand.  */
17038           if (opnum == 0)
17039             {
17040               switch (modrm.mod)
17041                 {
17042                   case 0:
17043                     /* When modrm.rm == 5 or modrm.rm == 4 and base in
17044                        SIB == 5, there is a 4 byte displacement.  */
17045                     if (base != 5)
17046                       /* No displacement. */
17047                       break;
17048                     /* Fall through.  */
17049                   case 2:
17050                     /* 4 byte displacement.  */
17051                     bytes_before_imm += 4;
17052                     break;
17053                   case 1:
17054                     /* 1 byte displacement.  */
17055                     bytes_before_imm++;
17056                     break;
17057                 }
17058             }
17059         }
17060       else
17061         {
17062           /* 16 bit address mode */
17063           /* Don't increase bytes_before_imm when decoding the third source,
17064              it has already been incremented by OP_E_memory while decoding
17065              the second source operand.  */
17066           if (opnum == 0)
17067             {
17068               switch (modrm.mod)
17069                 {
17070                 case 0:
17071                   /* When modrm.rm == 6, there is a 2 byte displacement.  */
17072                   if (modrm.rm != 6)
17073                     /* No displacement. */
17074                     break;
17075                   /* Fall through.  */
17076                 case 2:
17077                   /* 2 byte displacement.  */
17078                   bytes_before_imm += 2;
17079                   break;
17080                 case 1:
17081                   /* 1 byte displacement: when decoding the third source,
17082                      don't increase bytes_before_imm as this has already
17083                      been incremented by one in OP_E_memory while decoding
17084                      the second source operand.  */
17085                   if (opnum == 0)
17086                     bytes_before_imm++;
17087
17088                   break;
17089                 }
17090             }
17091         }
17092     }
17093
17094   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
17095   return codep [bytes_before_imm];
17096 }
17097
17098 static void
17099 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
17100 {
17101   const char **names;
17102
17103   if (reg == -1 && modrm.mod != 3)
17104     {
17105       OP_E_memory (bytemode, sizeflag);
17106       return;
17107     }
17108   else
17109     {
17110       if (reg == -1)
17111         {
17112           reg = modrm.rm;
17113           USED_REX (REX_B);
17114           if (rex & REX_B)
17115             reg += 8;
17116         }
17117       else if (reg > 7 && address_mode != mode_64bit)
17118         BadOp ();
17119     }
17120
17121   switch (vex.length)
17122     {
17123     case 128:
17124       names = names_xmm;
17125       break;
17126     case 256:
17127       names = names_ymm;
17128       break;
17129     default:
17130       abort ();
17131     }
17132   oappend (names[reg]);
17133 }
17134
17135 static void
17136 OP_EX_VexImmW (int bytemode, int sizeflag)
17137 {
17138   int reg = -1;
17139   static unsigned char vex_imm8;
17140
17141   if (vex_w_done == 0)
17142     {
17143       vex_w_done = 1;
17144
17145       /* Skip mod/rm byte.  */
17146       MODRM_CHECK;
17147       codep++;
17148
17149       vex_imm8 = get_vex_imm8 (sizeflag, 0);
17150
17151       if (vex.w)
17152           reg = vex_imm8 >> 4;
17153
17154       OP_EX_VexReg (bytemode, sizeflag, reg);
17155     }
17156   else if (vex_w_done == 1)
17157     {
17158       vex_w_done = 2;
17159
17160       if (!vex.w)
17161           reg = vex_imm8 >> 4;
17162
17163       OP_EX_VexReg (bytemode, sizeflag, reg);
17164     }
17165   else
17166     {
17167       /* Output the imm8 directly.  */
17168       scratchbuf[0] = '$';
17169       print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
17170       oappend_maybe_intel (scratchbuf);
17171       scratchbuf[0] = '\0';
17172       codep++;
17173     }
17174 }
17175
17176 static void
17177 OP_Vex_2src (int bytemode, int sizeflag)
17178 {
17179   if (modrm.mod == 3)
17180     {
17181       int reg = modrm.rm;
17182       USED_REX (REX_B);
17183       if (rex & REX_B)
17184         reg += 8;
17185       oappend (names_xmm[reg]);
17186     }
17187   else
17188     {
17189       if (intel_syntax
17190           && (bytemode == v_mode || bytemode == v_swap_mode))
17191         {
17192           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
17193           used_prefixes |= (prefixes & PREFIX_DATA);
17194         }
17195       OP_E (bytemode, sizeflag);
17196     }
17197 }
17198
17199 static void
17200 OP_Vex_2src_1 (int bytemode, int sizeflag)
17201 {
17202   if (modrm.mod == 3)
17203     {
17204       /* Skip mod/rm byte.   */
17205       MODRM_CHECK;
17206       codep++;
17207     }
17208
17209   if (vex.w)
17210     oappend (names_xmm[vex.register_specifier]);
17211   else
17212     OP_Vex_2src (bytemode, sizeflag);
17213 }
17214
17215 static void
17216 OP_Vex_2src_2 (int bytemode, int sizeflag)
17217 {
17218   if (vex.w)
17219     OP_Vex_2src (bytemode, sizeflag);
17220   else
17221     oappend (names_xmm[vex.register_specifier]);
17222 }
17223
17224 static void
17225 OP_EX_VexW (int bytemode, int sizeflag)
17226 {
17227   int reg = -1;
17228
17229   if (!vex_w_done)
17230     {
17231       vex_w_done = 1;
17232
17233       /* Skip mod/rm byte.  */
17234       MODRM_CHECK;
17235       codep++;
17236
17237       if (vex.w)
17238         reg = get_vex_imm8 (sizeflag, 0) >> 4;
17239     }
17240   else
17241     {
17242       if (!vex.w)
17243         reg = get_vex_imm8 (sizeflag, 1) >> 4;
17244     }
17245
17246   OP_EX_VexReg (bytemode, sizeflag, reg);
17247 }
17248
17249 static void
17250 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,
17251              int sizeflag ATTRIBUTE_UNUSED)
17252 {
17253   /* Skip the immediate byte and check for invalid bits.  */
17254   FETCH_DATA (the_info, codep + 1);
17255   if (*codep++ & 0xf)
17256     BadOp ();
17257 }
17258
17259 static void
17260 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17261 {
17262   int reg;
17263   const char **names;
17264
17265   FETCH_DATA (the_info, codep + 1);
17266   reg = *codep++;
17267
17268   if (bytemode != x_mode)
17269     abort ();
17270
17271   if (reg & 0xf)
17272       BadOp ();
17273
17274   reg >>= 4;
17275   if (reg > 7 && address_mode != mode_64bit)
17276     BadOp ();
17277
17278   switch (vex.length)
17279     {
17280     case 128:
17281       names = names_xmm;
17282       break;
17283     case 256:
17284       names = names_ymm;
17285       break;
17286     default:
17287       abort ();
17288     }
17289   oappend (names[reg]);
17290 }
17291
17292 static void
17293 OP_XMM_VexW (int bytemode, int sizeflag)
17294 {
17295   /* Turn off the REX.W bit since it is used for swapping operands
17296      now.  */
17297   rex &= ~REX_W;
17298   OP_XMM (bytemode, sizeflag);
17299 }
17300
17301 static void
17302 OP_EX_Vex (int bytemode, int sizeflag)
17303 {
17304   if (modrm.mod != 3)
17305     {
17306       if (vex.register_specifier != 0)
17307         BadOp ();
17308       need_vex_reg = 0;
17309     }
17310   OP_EX (bytemode, sizeflag);
17311 }
17312
17313 static void
17314 OP_XMM_Vex (int bytemode, int sizeflag)
17315 {
17316   if (modrm.mod != 3)
17317     {
17318       if (vex.register_specifier != 0)
17319         BadOp ();
17320       need_vex_reg = 0;
17321     }
17322   OP_XMM (bytemode, sizeflag);
17323 }
17324
17325 static void
17326 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17327 {
17328   switch (vex.length)
17329     {
17330     case 128:
17331       mnemonicendp = stpcpy (obuf, "vzeroupper");
17332       break;
17333     case 256:
17334       mnemonicendp = stpcpy (obuf, "vzeroall");
17335       break;
17336     default:
17337       abort ();
17338     }
17339 }
17340
17341 static struct op vex_cmp_op[] =
17342 {
17343   { STRING_COMMA_LEN ("eq") },
17344   { STRING_COMMA_LEN ("lt") },
17345   { STRING_COMMA_LEN ("le") },
17346   { STRING_COMMA_LEN ("unord") },
17347   { STRING_COMMA_LEN ("neq") },
17348   { STRING_COMMA_LEN ("nlt") },
17349   { STRING_COMMA_LEN ("nle") },
17350   { STRING_COMMA_LEN ("ord") },
17351   { STRING_COMMA_LEN ("eq_uq") },
17352   { STRING_COMMA_LEN ("nge") },
17353   { STRING_COMMA_LEN ("ngt") },
17354   { STRING_COMMA_LEN ("false") },
17355   { STRING_COMMA_LEN ("neq_oq") },
17356   { STRING_COMMA_LEN ("ge") },
17357   { STRING_COMMA_LEN ("gt") },
17358   { STRING_COMMA_LEN ("true") },
17359   { STRING_COMMA_LEN ("eq_os") },
17360   { STRING_COMMA_LEN ("lt_oq") },
17361   { STRING_COMMA_LEN ("le_oq") },
17362   { STRING_COMMA_LEN ("unord_s") },
17363   { STRING_COMMA_LEN ("neq_us") },
17364   { STRING_COMMA_LEN ("nlt_uq") },
17365   { STRING_COMMA_LEN ("nle_uq") },
17366   { STRING_COMMA_LEN ("ord_s") },
17367   { STRING_COMMA_LEN ("eq_us") },
17368   { STRING_COMMA_LEN ("nge_uq") },
17369   { STRING_COMMA_LEN ("ngt_uq") },
17370   { STRING_COMMA_LEN ("false_os") },
17371   { STRING_COMMA_LEN ("neq_os") },
17372   { STRING_COMMA_LEN ("ge_oq") },
17373   { STRING_COMMA_LEN ("gt_oq") },
17374   { STRING_COMMA_LEN ("true_us") },
17375 };
17376
17377 static void
17378 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17379 {
17380   unsigned int cmp_type;
17381
17382   FETCH_DATA (the_info, codep + 1);
17383   cmp_type = *codep++ & 0xff;
17384   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
17385     {
17386       char suffix [3];
17387       char *p = mnemonicendp - 2;
17388       suffix[0] = p[0];
17389       suffix[1] = p[1];
17390       suffix[2] = '\0';
17391       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
17392       mnemonicendp += vex_cmp_op[cmp_type].len;
17393     }
17394   else
17395     {
17396       /* We have a reserved extension byte.  Output it directly.  */
17397       scratchbuf[0] = '$';
17398       print_operand_value (scratchbuf + 1, 1, cmp_type);
17399       oappend_maybe_intel (scratchbuf);
17400       scratchbuf[0] = '\0';
17401     }
17402 }
17403
17404 static void
17405 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
17406              int sizeflag ATTRIBUTE_UNUSED)
17407 {
17408   unsigned int cmp_type;
17409
17410   if (!vex.evex)
17411     abort ();
17412
17413   FETCH_DATA (the_info, codep + 1);
17414   cmp_type = *codep++ & 0xff;
17415   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
17416      If it's the case, print suffix, otherwise - print the immediate.  */
17417   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
17418       && cmp_type != 3
17419       && cmp_type != 7)
17420     {
17421       char suffix [3];
17422       char *p = mnemonicendp - 2;
17423
17424       /* vpcmp* can have both one- and two-lettered suffix.  */
17425       if (p[0] == 'p')
17426         {
17427           p++;
17428           suffix[0] = p[0];
17429           suffix[1] = '\0';
17430         }
17431       else
17432         {
17433           suffix[0] = p[0];
17434           suffix[1] = p[1];
17435           suffix[2] = '\0';
17436         }
17437
17438       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
17439       mnemonicendp += simd_cmp_op[cmp_type].len;
17440     }
17441   else
17442     {
17443       /* We have a reserved extension byte.  Output it directly.  */
17444       scratchbuf[0] = '$';
17445       print_operand_value (scratchbuf + 1, 1, cmp_type);
17446       oappend_maybe_intel (scratchbuf);
17447       scratchbuf[0] = '\0';
17448     }
17449 }
17450
17451 static const struct op pclmul_op[] =
17452 {
17453   { STRING_COMMA_LEN ("lql") },
17454   { STRING_COMMA_LEN ("hql") },
17455   { STRING_COMMA_LEN ("lqh") },
17456   { STRING_COMMA_LEN ("hqh") }
17457 };
17458
17459 static void
17460 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
17461               int sizeflag ATTRIBUTE_UNUSED)
17462 {
17463   unsigned int pclmul_type;
17464
17465   FETCH_DATA (the_info, codep + 1);
17466   pclmul_type = *codep++ & 0xff;
17467   switch (pclmul_type)
17468     {
17469     case 0x10:
17470       pclmul_type = 2;
17471       break;
17472     case 0x11:
17473       pclmul_type = 3;
17474       break;
17475     default:
17476       break;
17477     }
17478   if (pclmul_type < ARRAY_SIZE (pclmul_op))
17479     {
17480       char suffix [4];
17481       char *p = mnemonicendp - 3;
17482       suffix[0] = p[0];
17483       suffix[1] = p[1];
17484       suffix[2] = p[2];
17485       suffix[3] = '\0';
17486       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
17487       mnemonicendp += pclmul_op[pclmul_type].len;
17488     }
17489   else
17490     {
17491       /* We have a reserved extension byte.  Output it directly.  */
17492       scratchbuf[0] = '$';
17493       print_operand_value (scratchbuf + 1, 1, pclmul_type);
17494       oappend_maybe_intel (scratchbuf);
17495       scratchbuf[0] = '\0';
17496     }
17497 }
17498
17499 static void
17500 MOVBE_Fixup (int bytemode, int sizeflag)
17501 {
17502   /* Add proper suffix to "movbe".  */
17503   char *p = mnemonicendp;
17504
17505   switch (bytemode)
17506     {
17507     case v_mode:
17508       if (intel_syntax)
17509         goto skip;
17510
17511       USED_REX (REX_W);
17512       if (sizeflag & SUFFIX_ALWAYS)
17513         {
17514           if (rex & REX_W)
17515             *p++ = 'q';
17516           else
17517             {
17518               if (sizeflag & DFLAG)
17519                 *p++ = 'l';
17520               else
17521                 *p++ = 'w';
17522               used_prefixes |= (prefixes & PREFIX_DATA);
17523             }
17524         }
17525       break;
17526     default:
17527       oappend (INTERNAL_DISASSEMBLER_ERROR);
17528       break;
17529     }
17530   mnemonicendp = p;
17531   *p = '\0';
17532
17533 skip:
17534   OP_M (bytemode, sizeflag);
17535 }
17536
17537 static void
17538 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17539 {
17540   int reg;
17541   const char **names;
17542
17543   /* Skip mod/rm byte.  */
17544   MODRM_CHECK;
17545   codep++;
17546
17547   if (vex.w)
17548     names = names64;
17549   else
17550     names = names32;
17551
17552   reg = modrm.rm;
17553   USED_REX (REX_B);
17554   if (rex & REX_B)
17555     reg += 8;
17556
17557   oappend (names[reg]);
17558 }
17559
17560 static void
17561 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17562 {
17563   const char **names;
17564
17565   if (vex.w)
17566     names = names64;
17567   else
17568     names = names32;
17569
17570   oappend (names[vex.register_specifier]);
17571 }
17572
17573 static void
17574 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17575 {
17576   if (!vex.evex
17577       || (bytemode != mask_mode && bytemode != mask_bd_mode))
17578     abort ();
17579
17580   USED_REX (REX_R);
17581   if ((rex & REX_R) != 0 || !vex.r)
17582     {
17583       BadOp ();
17584       return;
17585     }
17586
17587   oappend (names_mask [modrm.reg]);
17588 }
17589
17590 static void
17591 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17592 {
17593   if (!vex.evex
17594       || (bytemode != evex_rounding_mode
17595           && bytemode != evex_sae_mode))
17596     abort ();
17597   if (modrm.mod == 3 && vex.b)
17598     switch (bytemode)
17599       {
17600       case evex_rounding_mode:
17601         oappend (names_rounding[vex.ll]);
17602         break;
17603       case evex_sae_mode:
17604         oappend ("{sae}");
17605         break;
17606       default:
17607         break;
17608       }
17609 }