opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2014 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "dis-asm.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40
  41 #include <setjmp.h>
  42
  43 static int print_insn (bfd_vma, disassemble_info *);
  44 static void dofloat (int);
  45 static void OP_ST (int, int);
  46 static void OP_STi (int, int);
  47 static int putop (const char *, int);
  48 static void oappend (const char *);
  49 static void append_seg (void);
  50 static void OP_indirE (int, int);
  51 static void print_operand_value (char *, int, bfd_vma);
  52 static void OP_E_register (int, int);
  53 static void OP_E_memory (int, int);
  54 static void print_displacement (char *, bfd_vma);
  55 static void OP_E (int, int);
  56 static void OP_G (int, int);
  57 static bfd_vma get64 (void);
  58 static bfd_signed_vma get32 (void);
  59 static bfd_signed_vma get32s (void);
  60 static int get16 (void);
  61 static void set_op (bfd_vma, int);
  62 static void OP_Skip_MODRM (int, int);
  63 static void OP_REG (int, int);
  64 static void OP_IMREG (int, int);
  65 static void OP_I (int, int);
  66 static void OP_I64 (int, int);
  67 static void OP_sI (int, int);
  68 static void OP_J (int, int);
  69 static void OP_SEG (int, int);
  70 static void OP_DIR (int, int);
  71 static void OP_OFF (int, int);
  72 static void OP_OFF64 (int, int);
  73 static void ptr_reg (int, int);
  74 static void OP_ESreg (int, int);
  75 static void OP_DSreg (int, int);
  76 static void OP_C (int, int);
  77 static void OP_D (int, int);
  78 static void OP_T (int, int);
  79 static void OP_R (int, int);
  80 static void OP_MMX (int, int);
  81 static void OP_XMM (int, int);
  82 static void OP_EM (int, int);
  83 static void OP_EX (int, int);
  84 static void OP_EMC (int,int);
  85 static void OP_MXC (int,int);
  86 static void OP_MS (int, int);
  87 static void OP_XS (int, int);
  88 static void OP_M (int, int);
  89 static void OP_VEX (int, int);
  90 static void OP_EX_Vex (int, int);
  91 static void OP_EX_VexW (int, int);
  92 static void OP_EX_VexImmW (int, int);
  93 static void OP_XMM_Vex (int, int);
  94 static void OP_XMM_VexW (int, int);
  95 static void OP_Rounding (int, int);
  96 static void OP_REG_VexI4 (int, int);
  97 static void PCLMUL_Fixup (int, int);
  98 static void VEXI4_Fixup (int, int);
  99 static void VZERO_Fixup (int, int);
 100 static void VCMP_Fixup (int, int);
 101 static void VPCMP_Fixup (int, int);
 102 static void OP_0f07 (int, int);
 103 static void OP_Monitor (int, int);
 104 static void OP_Mwait (int, int);
 105 static void NOP_Fixup1 (int, int);
 106 static void NOP_Fixup2 (int, int);
 107 static void OP_3DNowSuffix (int, int);
 108 static void CMP_Fixup (int, int);
 109 static void BadOp (void);
 110 static void REP_Fixup (int, int);
 111 static void BND_Fixup (int, int);
 112 static void HLE_Fixup1 (int, int);
 113 static void HLE_Fixup2 (int, int);
 114 static void HLE_Fixup3 (int, int);
 115 static void CMPXCHG8B_Fixup (int, int);
 116 static void XMM_Fixup (int, int);
 117 static void CRC32_Fixup (int, int);
 118 static void FXSAVE_Fixup (int, int);
 119 static void OP_LWPCB_E (int, int);
 120 static void OP_LWP_E (int, int);
 121 static void OP_Vex_2src_1 (int, int);
 122 static void OP_Vex_2src_2 (int, int);
 123
 124 static void MOVBE_Fixup (int, int);
 125
 126 static void OP_Mask (int, int);
 127
 128 struct dis_private {
 129   /* Points to first byte not fetched.  */
 130   bfd_byte *max_fetched;
 131   bfd_byte the_buffer[MAX_MNEM_SIZE];
 132   bfd_vma insn_start;
 133   int orig_sizeflag;
 134   jmp_buf bailout;
 135 };
 136
 137 enum address_mode
 138 {
 139   mode_16bit,
 140   mode_32bit,
 141   mode_64bit
 142 };
 143
 144 enum address_mode address_mode;
 145
 146 /* Flags for the prefixes for the current instruction.  See below.  */
 147 static int prefixes;
 148
 149 /* REX prefix the current instruction.  See below.  */
 150 static int rex;
 151 /* Bits of REX we've already used.  */
 152 static int rex_used;
 153 /* REX bits in original REX prefix ignored.  */
 154 static int rex_ignored;
 155 /* Mark parts used in the REX prefix.  When we are testing for
 156    empty prefix (for 8bit register REX extension), just mask it
 157    out.  Otherwise test for REX bit is excuse for existence of REX
 158    only in case value is nonzero.  */
 159 #define USED_REX(value)                                 \
 160   {                                                     \
 161     if (value)                                          \
 162       {                                                 \
 163         if ((rex & value))                              \
 164           rex_used |= (value) | REX_OPCODE;             \
 165       }                                                 \
 166     else                                                \
 167       rex_used |= REX_OPCODE;                           \
 168   }
 169
 170 /* Flags for prefixes which we somehow handled when printing the
 171    current instruction.  */
 172 static int used_prefixes;
 173
 174 /* Flags stored in PREFIXES.  */
 175 #define PREFIX_REPZ 1
 176 #define PREFIX_REPNZ 2
 177 #define PREFIX_LOCK 4
 178 #define PREFIX_CS 8
 179 #define PREFIX_SS 0x10
 180 #define PREFIX_DS 0x20
 181 #define PREFIX_ES 0x40
 182 #define PREFIX_FS 0x80
 183 #define PREFIX_GS 0x100
 184 #define PREFIX_DATA 0x200
 185 #define PREFIX_ADDR 0x400
 186 #define PREFIX_FWAIT 0x800
 187
 188 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 189    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 190    on error.  */
 191 #define FETCH_DATA(info, addr) \
 192   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 193    ? 1 : fetch_data ((info), (addr)))
 194
 195 static int
 196 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 197 {
 198   int status;
 199   struct dis_private *priv = (struct dis_private *) info->private_data;
 200   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 201
 202   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 203     status = (*info->read_memory_func) (start,
 204                                         priv->max_fetched,
 205                                         addr - priv->max_fetched,
 206                                         info);
 207   else
 208     status = -1;
 209   if (status != 0)
 210     {
 211       /* If we did manage to read at least one byte, then
 212          print_insn_i386 will do something sensible.  Otherwise, print
 213          an error.  We do that here because this is where we know
 214          STATUS.  */
 215       if (priv->max_fetched == priv->the_buffer)
 216         (*info->memory_error_func) (status, start, info);
 217       longjmp (priv->bailout, 1);
 218     }
 219   else
 220     priv->max_fetched = addr;
 221   return 1;
 222 }
 223
 224 #define XX { NULL, 0 }
 225 #define Bad_Opcode NULL, { { NULL, 0 } }
 226
 227 #define Eb { OP_E, b_mode }
 228 #define Ebnd { OP_E, bnd_mode }
 229 #define EbS { OP_E, b_swap_mode }
 230 #define Ev { OP_E, v_mode }
 231 #define Ev_bnd { OP_E, v_bnd_mode }
 232 #define EvS { OP_E, v_swap_mode }
 233 #define Ed { OP_E, d_mode }
 234 #define Edq { OP_E, dq_mode }
 235 #define Edqw { OP_E, dqw_mode }
 236 #define Edqb { OP_E, dqb_mode }
 237 #define Edqd { OP_E, dqd_mode }
 238 #define Eq { OP_E, q_mode }
 239 #define indirEv { OP_indirE, stack_v_mode }
 240 #define indirEp { OP_indirE, f_mode }
 241 #define stackEv { OP_E, stack_v_mode }
 242 #define Em { OP_E, m_mode }
 243 #define Ew { OP_E, w_mode }
 244 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 245 #define Ma { OP_M, a_mode }
 246 #define Mb { OP_M, b_mode }
 247 #define Md { OP_M, d_mode }
 248 #define Mo { OP_M, o_mode }
 249 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 250 #define Mq { OP_M, q_mode }
 251 #define Mx { OP_M, x_mode }
 252 #define Mxmm { OP_M, xmm_mode }
 253 #define Gb { OP_G, b_mode }
 254 #define Gbnd { OP_G, bnd_mode }
 255 #define Gv { OP_G, v_mode }
 256 #define Gd { OP_G, d_mode }
 257 #define Gdq { OP_G, dq_mode }
 258 #define Gm { OP_G, m_mode }
 259 #define Gw { OP_G, w_mode }
 260 #define Rd { OP_R, d_mode }
 261 #define Rdq { OP_R, dq_mode }
 262 #define Rm { OP_R, m_mode }
 263 #define Ib { OP_I, b_mode }
 264 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 265 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 266 #define Iv { OP_I, v_mode }
 267 #define sIv { OP_sI, v_mode }
 268 #define Iq { OP_I, q_mode }
 269 #define Iv64 { OP_I64, v_mode }
 270 #define Iw { OP_I, w_mode }
 271 #define I1 { OP_I, const_1_mode }
 272 #define Jb { OP_J, b_mode }
 273 #define Jv { OP_J, v_mode }
 274 #define Cm { OP_C, m_mode }
 275 #define Dm { OP_D, m_mode }
 276 #define Td { OP_T, d_mode }
 277 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 278
 279 #define RMeAX { OP_REG, eAX_reg }
 280 #define RMeBX { OP_REG, eBX_reg }
 281 #define RMeCX { OP_REG, eCX_reg }
 282 #define RMeDX { OP_REG, eDX_reg }
 283 #define RMeSP { OP_REG, eSP_reg }
 284 #define RMeBP { OP_REG, eBP_reg }
 285 #define RMeSI { OP_REG, eSI_reg }
 286 #define RMeDI { OP_REG, eDI_reg }
 287 #define RMrAX { OP_REG, rAX_reg }
 288 #define RMrBX { OP_REG, rBX_reg }
 289 #define RMrCX { OP_REG, rCX_reg }
 290 #define RMrDX { OP_REG, rDX_reg }
 291 #define RMrSP { OP_REG, rSP_reg }
 292 #define RMrBP { OP_REG, rBP_reg }
 293 #define RMrSI { OP_REG, rSI_reg }
 294 #define RMrDI { OP_REG, rDI_reg }
 295 #define RMAL { OP_REG, al_reg }
 296 #define RMCL { OP_REG, cl_reg }
 297 #define RMDL { OP_REG, dl_reg }
 298 #define RMBL { OP_REG, bl_reg }
 299 #define RMAH { OP_REG, ah_reg }
 300 #define RMCH { OP_REG, ch_reg }
 301 #define RMDH { OP_REG, dh_reg }
 302 #define RMBH { OP_REG, bh_reg }
 303 #define RMAX { OP_REG, ax_reg }
 304 #define RMDX { OP_REG, dx_reg }
 305
 306 #define eAX { OP_IMREG, eAX_reg }
 307 #define eBX { OP_IMREG, eBX_reg }
 308 #define eCX { OP_IMREG, eCX_reg }
 309 #define eDX { OP_IMREG, eDX_reg }
 310 #define eSP { OP_IMREG, eSP_reg }
 311 #define eBP { OP_IMREG, eBP_reg }
 312 #define eSI { OP_IMREG, eSI_reg }
 313 #define eDI { OP_IMREG, eDI_reg }
 314 #define AL { OP_IMREG, al_reg }
 315 #define CL { OP_IMREG, cl_reg }
 316 #define DL { OP_IMREG, dl_reg }
 317 #define BL { OP_IMREG, bl_reg }
 318 #define AH { OP_IMREG, ah_reg }
 319 #define CH { OP_IMREG, ch_reg }
 320 #define DH { OP_IMREG, dh_reg }
 321 #define BH { OP_IMREG, bh_reg }
 322 #define AX { OP_IMREG, ax_reg }
 323 #define DX { OP_IMREG, dx_reg }
 324 #define zAX { OP_IMREG, z_mode_ax_reg }
 325 #define indirDX { OP_IMREG, indir_dx_reg }
 326
 327 #define Sw { OP_SEG, w_mode }
 328 #define Sv { OP_SEG, v_mode }
 329 #define Ap { OP_DIR, 0 }
 330 #define Ob { OP_OFF64, b_mode }
 331 #define Ov { OP_OFF64, v_mode }
 332 #define Xb { OP_DSreg, eSI_reg }
 333 #define Xv { OP_DSreg, eSI_reg }
 334 #define Xz { OP_DSreg, eSI_reg }
 335 #define Yb { OP_ESreg, eDI_reg }
 336 #define Yv { OP_ESreg, eDI_reg }
 337 #define DSBX { OP_DSreg, eBX_reg }
 338
 339 #define es { OP_REG, es_reg }
 340 #define ss { OP_REG, ss_reg }
 341 #define cs { OP_REG, cs_reg }
 342 #define ds { OP_REG, ds_reg }
 343 #define fs { OP_REG, fs_reg }
 344 #define gs { OP_REG, gs_reg }
 345
 346 #define MX { OP_MMX, 0 }
 347 #define XM { OP_XMM, 0 }
 348 #define XMScalar { OP_XMM, scalar_mode }
 349 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 350 #define XMM { OP_XMM, xmm_mode }
 351 #define XMxmmq { OP_XMM, xmmq_mode }
 352 #define EM { OP_EM, v_mode }
 353 #define EMS { OP_EM, v_swap_mode }
 354 #define EMd { OP_EM, d_mode }
 355 #define EMx { OP_EM, x_mode }
 356 #define EXw { OP_EX, w_mode }
 357 #define EXd { OP_EX, d_mode }
 358 #define EXdScalar { OP_EX, d_scalar_mode }
 359 #define EXdS { OP_EX, d_swap_mode }
 360 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
 361 #define EXq { OP_EX, q_mode }
 362 #define EXqScalar { OP_EX, q_scalar_mode }
 363 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
 364 #define EXqS { OP_EX, q_swap_mode }
 365 #define EXx { OP_EX, x_mode }
 366 #define EXxS { OP_EX, x_swap_mode }
 367 #define EXxmm { OP_EX, xmm_mode }
 368 #define EXymm { OP_EX, ymm_mode }
 369 #define EXxmmq { OP_EX, xmmq_mode }
 370 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 371 #define EXxmm_mb { OP_EX, xmm_mb_mode }
 372 #define EXxmm_mw { OP_EX, xmm_mw_mode }
 373 #define EXxmm_md { OP_EX, xmm_md_mode }
 374 #define EXxmm_mq { OP_EX, xmm_mq_mode }
 375 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
 376 #define EXxmmdw { OP_EX, xmmdw_mode }
 377 #define EXxmmqd { OP_EX, xmmqd_mode }
 378 #define EXymmq { OP_EX, ymmq_mode }
 379 #define EXVexWdq { OP_EX, vex_w_dq_mode }
 380 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 381 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 382 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 383 #define MS { OP_MS, v_mode }
 384 #define XS { OP_XS, v_mode }
 385 #define EMCq { OP_EMC, q_mode }
 386 #define MXC { OP_MXC, 0 }
 387 #define OPSUF { OP_3DNowSuffix, 0 }
 388 #define CMP { CMP_Fixup, 0 }
 389 #define XMM0 { XMM_Fixup, 0 }
 390 #define FXSAVE { FXSAVE_Fixup, 0 }
 391 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
 392 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
 393
 394 #define Vex { OP_VEX, vex_mode }
 395 #define VexScalar { OP_VEX, vex_scalar_mode }
 396 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 397 #define Vex128 { OP_VEX, vex128_mode }
 398 #define Vex256 { OP_VEX, vex256_mode }
 399 #define VexGdq { OP_VEX, dq_mode }
 400 #define VexI4 { VEXI4_Fixup, 0}
 401 #define EXdVex { OP_EX_Vex, d_mode }
 402 #define EXdVexS { OP_EX_Vex, d_swap_mode }
 403 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
 404 #define EXqVex { OP_EX_Vex, q_mode }
 405 #define EXqVexS { OP_EX_Vex, q_swap_mode }
 406 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
 407 #define EXVexW { OP_EX_VexW, x_mode }
 408 #define EXdVexW { OP_EX_VexW, d_mode }
 409 #define EXqVexW { OP_EX_VexW, q_mode }
 410 #define EXVexImmW { OP_EX_VexImmW, x_mode }
 411 #define XMVex { OP_XMM_Vex, 0 }
 412 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
 413 #define XMVexW { OP_XMM_VexW, 0 }
 414 #define XMVexI4 { OP_REG_VexI4, x_mode }
 415 #define PCLMUL { PCLMUL_Fixup, 0 }
 416 #define VZERO { VZERO_Fixup, 0 }
 417 #define VCMP { VCMP_Fixup, 0 }
 418 #define VPCMP { VPCMP_Fixup, 0 }
 419
 420 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 421 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 422
 423 #define XMask { OP_Mask, mask_mode }
 424 #define MaskG { OP_G, mask_mode }
 425 #define MaskE { OP_E, mask_mode }
 426 #define MaskR { OP_R, mask_mode }
 427 #define MaskVex { OP_VEX, mask_mode }
 428
 429 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 430 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 431
 432 /* Used handle "rep" prefix for string instructions.  */
 433 #define Xbr { REP_Fixup, eSI_reg }
 434 #define Xvr { REP_Fixup, eSI_reg }
 435 #define Ybr { REP_Fixup, eDI_reg }
 436 #define Yvr { REP_Fixup, eDI_reg }
 437 #define Yzr { REP_Fixup, eDI_reg }
 438 #define indirDXr { REP_Fixup, indir_dx_reg }
 439 #define ALr { REP_Fixup, al_reg }
 440 #define eAXr { REP_Fixup, eAX_reg }
 441
 442 /* Used handle HLE prefix for lockable instructions.  */
 443 #define Ebh1 { HLE_Fixup1, b_mode }
 444 #define Evh1 { HLE_Fixup1, v_mode }
 445 #define Ebh2 { HLE_Fixup2, b_mode }
 446 #define Evh2 { HLE_Fixup2, v_mode }
 447 #define Ebh3 { HLE_Fixup3, b_mode }
 448 #define Evh3 { HLE_Fixup3, v_mode }
 449
 450 #define BND { BND_Fixup, 0 }
 451
 452 #define cond_jump_flag { NULL, cond_jump_mode }
 453 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 454
 455 /* bits in sizeflag */
 456 #define SUFFIX_ALWAYS 4
 457 #define AFLAG 2
 458 #define DFLAG 1
 459
 460 enum
 461 {
 462   /* byte operand */
 463   b_mode = 1,
 464   /* byte operand with operand swapped */
 465   b_swap_mode,
 466   /* byte operand, sign extend like 'T' suffix */
 467   b_T_mode,
 468   /* operand size depends on prefixes */
 469   v_mode,
 470   /* operand size depends on prefixes with operand swapped */
 471   v_swap_mode,
 472   /* word operand */
 473   w_mode,
 474   /* double word operand  */
 475   d_mode,
 476   /* double word operand with operand swapped */
 477   d_swap_mode,
 478   /* quad word operand */
 479   q_mode,
 480   /* quad word operand with operand swapped */
 481   q_swap_mode,
 482   /* ten-byte operand */
 483   t_mode,
 484   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 485      broadcast enabled.  */
 486   x_mode,
 487   /* Similar to x_mode, but with different EVEX mem shifts.  */
 488   evex_x_gscat_mode,
 489   /* Similar to x_mode, but with disabled broadcast.  */
 490   evex_x_nobcst_mode,
 491   /* Similar to x_mode, but with operands swapped and disabled broadcast
 492      in EVEX.  */
 493   x_swap_mode,
 494   /* 16-byte XMM operand */
 495   xmm_mode,
 496   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 497      memory operand (depending on vector length).  Broadcast isn't
 498      allowed.  */
 499   xmmq_mode,
 500   /* Same as xmmq_mode, but broadcast is allowed.  */
 501   evex_half_bcst_xmmq_mode,
 502   /* XMM register or byte memory operand */
 503   xmm_mb_mode,
 504   /* XMM register or word memory operand */
 505   xmm_mw_mode,
 506   /* XMM register or double word memory operand */
 507   xmm_md_mode,
 508   /* XMM register or quad word memory operand */
 509   xmm_mq_mode,
 510   /* XMM register or double/quad word memory operand, depending on
 511      VEX.W.  */
 512   xmm_mdq_mode,
 513   /* 16-byte XMM, word, double word or quad word operand.  */
 514   xmmdw_mode,
 515   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 516   xmmqd_mode,
 517   /* 32-byte YMM operand */
 518   ymm_mode,
 519   /* quad word, ymmword or zmmword memory operand.  */
 520   ymmq_mode,
 521   /* 32-byte YMM or 16-byte word operand */
 522   ymmxmm_mode,
 523   /* d_mode in 32bit, q_mode in 64bit mode.  */
 524   m_mode,
 525   /* pair of v_mode operands */
 526   a_mode,
 527   cond_jump_mode,
 528   loop_jcxz_mode,
 529   v_bnd_mode,
 530   /* operand size depends on REX prefixes.  */
 531   dq_mode,
 532   /* registers like dq_mode, memory like w_mode.  */
 533   dqw_mode,
 534   bnd_mode,
 535   /* 4- or 6-byte pointer operand */
 536   f_mode,
 537   const_1_mode,
 538   /* v_mode for stack-related opcodes.  */
 539   stack_v_mode,
 540   /* non-quad operand size depends on prefixes */
 541   z_mode,
 542   /* 16-byte operand */
 543   o_mode,
 544   /* registers like dq_mode, memory like b_mode.  */
 545   dqb_mode,
 546   /* registers like dq_mode, memory like d_mode.  */
 547   dqd_mode,
 548   /* normal vex mode */
 549   vex_mode,
 550   /* 128bit vex mode */
 551   vex128_mode,
 552   /* 256bit vex mode */
 553   vex256_mode,
 554   /* operand size depends on the VEX.W bit.  */
 555   vex_w_dq_mode,
 556
 557   /* Similar to vex_w_dq_mode, with VSIB dword indices.  */
 558   vex_vsib_d_w_dq_mode,
 559   /* Similar to vex_w_dq_mode, with VSIB qword indices.  */
 560   vex_vsib_q_w_dq_mode,
 561
 562   /* scalar, ignore vector length.  */
 563   scalar_mode,
 564   /* like d_mode, ignore vector length.  */
 565   d_scalar_mode,
 566   /* like d_swap_mode, ignore vector length.  */
 567   d_scalar_swap_mode,
 568   /* like q_mode, ignore vector length.  */
 569   q_scalar_mode,
 570   /* like q_swap_mode, ignore vector length.  */
 571   q_scalar_swap_mode,
 572   /* like vex_mode, ignore vector length.  */
 573   vex_scalar_mode,
 574   /* like vex_w_dq_mode, ignore vector length.  */
 575   vex_scalar_w_dq_mode,
 576
 577   /* Static rounding.  */
 578   evex_rounding_mode,
 579   /* Supress all exceptions.  */
 580   evex_sae_mode,
 581
 582   /* Mask register operand.  */
 583   mask_mode,
 584
 585   es_reg,
 586   cs_reg,
 587   ss_reg,
 588   ds_reg,
 589   fs_reg,
 590   gs_reg,
 591
 592   eAX_reg,
 593   eCX_reg,
 594   eDX_reg,
 595   eBX_reg,
 596   eSP_reg,
 597   eBP_reg,
 598   eSI_reg,
 599   eDI_reg,
 600
 601   al_reg,
 602   cl_reg,
 603   dl_reg,
 604   bl_reg,
 605   ah_reg,
 606   ch_reg,
 607   dh_reg,
 608   bh_reg,
 609
 610   ax_reg,
 611   cx_reg,
 612   dx_reg,
 613   bx_reg,
 614   sp_reg,
 615   bp_reg,
 616   si_reg,
 617   di_reg,
 618
 619   rAX_reg,
 620   rCX_reg,
 621   rDX_reg,
 622   rBX_reg,
 623   rSP_reg,
 624   rBP_reg,
 625   rSI_reg,
 626   rDI_reg,
 627
 628   z_mode_ax_reg,
 629   indir_dx_reg
 630 };
 631
 632 enum
 633 {
 634   FLOATCODE = 1,
 635   USE_REG_TABLE,
 636   USE_MOD_TABLE,
 637   USE_RM_TABLE,
 638   USE_PREFIX_TABLE,
 639   USE_X86_64_TABLE,
 640   USE_3BYTE_TABLE,
 641   USE_XOP_8F_TABLE,
 642   USE_VEX_C4_TABLE,
 643   USE_VEX_C5_TABLE,
 644   USE_VEX_LEN_TABLE,
 645   USE_VEX_W_TABLE,
 646   USE_EVEX_TABLE
 647 };
 648
 649 #define FLOAT                   NULL, { { NULL, FLOATCODE } }
 650
 651 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }
 652 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 653 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 654 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 655 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 656 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 657 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 658 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 659 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 660 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 661 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 662 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 663 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 664
 665 enum
 666 {
 667   REG_80 = 0,
 668   REG_81,
 669   REG_82,
 670   REG_8F,
 671   REG_C0,
 672   REG_C1,
 673   REG_C6,
 674   REG_C7,
 675   REG_D0,
 676   REG_D1,
 677   REG_D2,
 678   REG_D3,
 679   REG_F6,
 680   REG_F7,
 681   REG_FE,
 682   REG_FF,
 683   REG_0F00,
 684   REG_0F01,
 685   REG_0F0D,
 686   REG_0F18,
 687   REG_0F71,
 688   REG_0F72,
 689   REG_0F73,
 690   REG_0FA6,
 691   REG_0FA7,
 692   REG_0FAE,
 693   REG_0FBA,
 694   REG_0FC7,
 695   REG_VEX_0F71,
 696   REG_VEX_0F72,
 697   REG_VEX_0F73,
 698   REG_VEX_0FAE,
 699   REG_VEX_0F38F3,
 700   REG_XOP_LWPCB,
 701   REG_XOP_LWP,
 702   REG_XOP_TBM_01,
 703   REG_XOP_TBM_02,
 704
 705   REG_EVEX_0F72,
 706   REG_EVEX_0F73,
 707   REG_EVEX_0F38C6,
 708   REG_EVEX_0F38C7
 709 };
 710
 711 enum
 712 {
 713   MOD_8D = 0,
 714   MOD_C6_REG_7,
 715   MOD_C7_REG_7,
 716   MOD_FF_REG_3,
 717   MOD_FF_REG_5,
 718   MOD_0F01_REG_0,
 719   MOD_0F01_REG_1,
 720   MOD_0F01_REG_2,
 721   MOD_0F01_REG_3,
 722   MOD_0F01_REG_7,
 723   MOD_0F12_PREFIX_0,
 724   MOD_0F13,
 725   MOD_0F16_PREFIX_0,
 726   MOD_0F17,
 727   MOD_0F18_REG_0,
 728   MOD_0F18_REG_1,
 729   MOD_0F18_REG_2,
 730   MOD_0F18_REG_3,
 731   MOD_0F18_REG_4,
 732   MOD_0F18_REG_5,
 733   MOD_0F18_REG_6,
 734   MOD_0F18_REG_7,
 735   MOD_0F1A_PREFIX_0,
 736   MOD_0F1B_PREFIX_0,
 737   MOD_0F1B_PREFIX_1,
 738   MOD_0F20,
 739   MOD_0F21,
 740   MOD_0F22,
 741   MOD_0F23,
 742   MOD_0F24,
 743   MOD_0F26,
 744   MOD_0F2B_PREFIX_0,
 745   MOD_0F2B_PREFIX_1,
 746   MOD_0F2B_PREFIX_2,
 747   MOD_0F2B_PREFIX_3,
 748   MOD_0F51,
 749   MOD_0F71_REG_2,
 750   MOD_0F71_REG_4,
 751   MOD_0F71_REG_6,
 752   MOD_0F72_REG_2,
 753   MOD_0F72_REG_4,
 754   MOD_0F72_REG_6,
 755   MOD_0F73_REG_2,
 756   MOD_0F73_REG_3,
 757   MOD_0F73_REG_6,
 758   MOD_0F73_REG_7,
 759   MOD_0FAE_REG_0,
 760   MOD_0FAE_REG_1,
 761   MOD_0FAE_REG_2,
 762   MOD_0FAE_REG_3,
 763   MOD_0FAE_REG_4,
 764   MOD_0FAE_REG_5,
 765   MOD_0FAE_REG_6,
 766   MOD_0FAE_REG_7,
 767   MOD_0FB2,
 768   MOD_0FB4,
 769   MOD_0FB5,
 770   MOD_0FC7_REG_3,
 771   MOD_0FC7_REG_4,
 772   MOD_0FC7_REG_5,
 773   MOD_0FC7_REG_6,
 774   MOD_0FC7_REG_7,
 775   MOD_0FD7,
 776   MOD_0FE7_PREFIX_2,
 777   MOD_0FF0_PREFIX_3,
 778   MOD_0F382A_PREFIX_2,
 779   MOD_62_32BIT,
 780   MOD_C4_32BIT,
 781   MOD_C5_32BIT,
 782   MOD_VEX_0F12_PREFIX_0,
 783   MOD_VEX_0F13,
 784   MOD_VEX_0F16_PREFIX_0,
 785   MOD_VEX_0F17,
 786   MOD_VEX_0F2B,
 787   MOD_VEX_0F50,
 788   MOD_VEX_0F71_REG_2,
 789   MOD_VEX_0F71_REG_4,
 790   MOD_VEX_0F71_REG_6,
 791   MOD_VEX_0F72_REG_2,
 792   MOD_VEX_0F72_REG_4,
 793   MOD_VEX_0F72_REG_6,
 794   MOD_VEX_0F73_REG_2,
 795   MOD_VEX_0F73_REG_3,
 796   MOD_VEX_0F73_REG_6,
 797   MOD_VEX_0F73_REG_7,
 798   MOD_VEX_0FAE_REG_2,
 799   MOD_VEX_0FAE_REG_3,
 800   MOD_VEX_0FD7_PREFIX_2,
 801   MOD_VEX_0FE7_PREFIX_2,
 802   MOD_VEX_0FF0_PREFIX_3,
 803   MOD_VEX_0F381A_PREFIX_2,
 804   MOD_VEX_0F382A_PREFIX_2,
 805   MOD_VEX_0F382C_PREFIX_2,
 806   MOD_VEX_0F382D_PREFIX_2,
 807   MOD_VEX_0F382E_PREFIX_2,
 808   MOD_VEX_0F382F_PREFIX_2,
 809   MOD_VEX_0F385A_PREFIX_2,
 810   MOD_VEX_0F388C_PREFIX_2,
 811   MOD_VEX_0F388E_PREFIX_2,
 812
 813   MOD_EVEX_0F10_PREFIX_1,
 814   MOD_EVEX_0F10_PREFIX_3,
 815   MOD_EVEX_0F11_PREFIX_1,
 816   MOD_EVEX_0F11_PREFIX_3,
 817   MOD_EVEX_0F12_PREFIX_0,
 818   MOD_EVEX_0F16_PREFIX_0,
 819   MOD_EVEX_0F38C6_REG_1,
 820   MOD_EVEX_0F38C6_REG_2,
 821   MOD_EVEX_0F38C6_REG_5,
 822   MOD_EVEX_0F38C6_REG_6,
 823   MOD_EVEX_0F38C7_REG_1,
 824   MOD_EVEX_0F38C7_REG_2,
 825   MOD_EVEX_0F38C7_REG_5,
 826   MOD_EVEX_0F38C7_REG_6
 827 };
 828
 829 enum
 830 {
 831   RM_C6_REG_7 = 0,
 832   RM_C7_REG_7,
 833   RM_0F01_REG_0,
 834   RM_0F01_REG_1,
 835   RM_0F01_REG_2,
 836   RM_0F01_REG_3,
 837   RM_0F01_REG_7,
 838   RM_0FAE_REG_5,
 839   RM_0FAE_REG_6,
 840   RM_0FAE_REG_7
 841 };
 842
 843 enum
 844 {
 845   PREFIX_90 = 0,
 846   PREFIX_0F10,
 847   PREFIX_0F11,
 848   PREFIX_0F12,
 849   PREFIX_0F16,
 850   PREFIX_0F1A,
 851   PREFIX_0F1B,
 852   PREFIX_0F2A,
 853   PREFIX_0F2B,
 854   PREFIX_0F2C,
 855   PREFIX_0F2D,
 856   PREFIX_0F2E,
 857   PREFIX_0F2F,
 858   PREFIX_0F51,
 859   PREFIX_0F52,
 860   PREFIX_0F53,
 861   PREFIX_0F58,
 862   PREFIX_0F59,
 863   PREFIX_0F5A,
 864   PREFIX_0F5B,
 865   PREFIX_0F5C,
 866   PREFIX_0F5D,
 867   PREFIX_0F5E,
 868   PREFIX_0F5F,
 869   PREFIX_0F60,
 870   PREFIX_0F61,
 871   PREFIX_0F62,
 872   PREFIX_0F6C,
 873   PREFIX_0F6D,
 874   PREFIX_0F6F,
 875   PREFIX_0F70,
 876   PREFIX_0F73_REG_3,
 877   PREFIX_0F73_REG_7,
 878   PREFIX_0F78,
 879   PREFIX_0F79,
 880   PREFIX_0F7C,
 881   PREFIX_0F7D,
 882   PREFIX_0F7E,
 883   PREFIX_0F7F,
 884   PREFIX_0FAE_REG_0,
 885   PREFIX_0FAE_REG_1,
 886   PREFIX_0FAE_REG_2,
 887   PREFIX_0FAE_REG_3,
 888   PREFIX_0FAE_REG_7,
 889   PREFIX_0FB8,
 890   PREFIX_0FBC,
 891   PREFIX_0FBD,
 892   PREFIX_0FC2,
 893   PREFIX_0FC3,
 894   PREFIX_0FC7_REG_6,
 895   PREFIX_0FD0,
 896   PREFIX_0FD6,
 897   PREFIX_0FE6,
 898   PREFIX_0FE7,
 899   PREFIX_0FF0,
 900   PREFIX_0FF7,
 901   PREFIX_0F3810,
 902   PREFIX_0F3814,
 903   PREFIX_0F3815,
 904   PREFIX_0F3817,
 905   PREFIX_0F3820,
 906   PREFIX_0F3821,
 907   PREFIX_0F3822,
 908   PREFIX_0F3823,
 909   PREFIX_0F3824,
 910   PREFIX_0F3825,
 911   PREFIX_0F3828,
 912   PREFIX_0F3829,
 913   PREFIX_0F382A,
 914   PREFIX_0F382B,
 915   PREFIX_0F3830,
 916   PREFIX_0F3831,
 917   PREFIX_0F3832,
 918   PREFIX_0F3833,
 919   PREFIX_0F3834,
 920   PREFIX_0F3835,
 921   PREFIX_0F3837,
 922   PREFIX_0F3838,
 923   PREFIX_0F3839,
 924   PREFIX_0F383A,
 925   PREFIX_0F383B,
 926   PREFIX_0F383C,
 927   PREFIX_0F383D,
 928   PREFIX_0F383E,
 929   PREFIX_0F383F,
 930   PREFIX_0F3840,
 931   PREFIX_0F3841,
 932   PREFIX_0F3880,
 933   PREFIX_0F3881,
 934   PREFIX_0F3882,
 935   PREFIX_0F38C8,
 936   PREFIX_0F38C9,
 937   PREFIX_0F38CA,
 938   PREFIX_0F38CB,
 939   PREFIX_0F38CC,
 940   PREFIX_0F38CD,
 941   PREFIX_0F38DB,
 942   PREFIX_0F38DC,
 943   PREFIX_0F38DD,
 944   PREFIX_0F38DE,
 945   PREFIX_0F38DF,
 946   PREFIX_0F38F0,
 947   PREFIX_0F38F1,
 948   PREFIX_0F38F6,
 949   PREFIX_0F3A08,
 950   PREFIX_0F3A09,
 951   PREFIX_0F3A0A,
 952   PREFIX_0F3A0B,
 953   PREFIX_0F3A0C,
 954   PREFIX_0F3A0D,
 955   PREFIX_0F3A0E,
 956   PREFIX_0F3A14,
 957   PREFIX_0F3A15,
 958   PREFIX_0F3A16,
 959   PREFIX_0F3A17,
 960   PREFIX_0F3A20,
 961   PREFIX_0F3A21,
 962   PREFIX_0F3A22,
 963   PREFIX_0F3A40,
 964   PREFIX_0F3A41,
 965   PREFIX_0F3A42,
 966   PREFIX_0F3A44,
 967   PREFIX_0F3A60,
 968   PREFIX_0F3A61,
 969   PREFIX_0F3A62,
 970   PREFIX_0F3A63,
 971   PREFIX_0F3ACC,
 972   PREFIX_0F3ADF,
 973   PREFIX_VEX_0F10,
 974   PREFIX_VEX_0F11,
 975   PREFIX_VEX_0F12,
 976   PREFIX_VEX_0F16,
 977   PREFIX_VEX_0F2A,
 978   PREFIX_VEX_0F2C,
 979   PREFIX_VEX_0F2D,
 980   PREFIX_VEX_0F2E,
 981   PREFIX_VEX_0F2F,
 982   PREFIX_VEX_0F41,
 983   PREFIX_VEX_0F42,
 984   PREFIX_VEX_0F44,
 985   PREFIX_VEX_0F45,
 986   PREFIX_VEX_0F46,
 987   PREFIX_VEX_0F47,
 988   PREFIX_VEX_0F4B,
 989   PREFIX_VEX_0F51,
 990   PREFIX_VEX_0F52,
 991   PREFIX_VEX_0F53,
 992   PREFIX_VEX_0F58,
 993   PREFIX_VEX_0F59,
 994   PREFIX_VEX_0F5A,
 995   PREFIX_VEX_0F5B,
 996   PREFIX_VEX_0F5C,
 997   PREFIX_VEX_0F5D,
 998   PREFIX_VEX_0F5E,
 999   PREFIX_VEX_0F5F,
1000   PREFIX_VEX_0F60,
1001   PREFIX_VEX_0F61,
1002   PREFIX_VEX_0F62,
1003   PREFIX_VEX_0F63,
1004   PREFIX_VEX_0F64,
1005   PREFIX_VEX_0F65,
1006   PREFIX_VEX_0F66,
1007   PREFIX_VEX_0F67,
1008   PREFIX_VEX_0F68,
1009   PREFIX_VEX_0F69,
1010   PREFIX_VEX_0F6A,
1011   PREFIX_VEX_0F6B,
1012   PREFIX_VEX_0F6C,
1013   PREFIX_VEX_0F6D,
1014   PREFIX_VEX_0F6E,
1015   PREFIX_VEX_0F6F,
1016   PREFIX_VEX_0F70,
1017   PREFIX_VEX_0F71_REG_2,
1018   PREFIX_VEX_0F71_REG_4,
1019   PREFIX_VEX_0F71_REG_6,
1020   PREFIX_VEX_0F72_REG_2,
1021   PREFIX_VEX_0F72_REG_4,
1022   PREFIX_VEX_0F72_REG_6,
1023   PREFIX_VEX_0F73_REG_2,
1024   PREFIX_VEX_0F73_REG_3,
1025   PREFIX_VEX_0F73_REG_6,
1026   PREFIX_VEX_0F73_REG_7,
1027   PREFIX_VEX_0F74,
1028   PREFIX_VEX_0F75,
1029   PREFIX_VEX_0F76,
1030   PREFIX_VEX_0F77,
1031   PREFIX_VEX_0F7C,
1032   PREFIX_VEX_0F7D,
1033   PREFIX_VEX_0F7E,
1034   PREFIX_VEX_0F7F,
1035   PREFIX_VEX_0F90,
1036   PREFIX_VEX_0F91,
1037   PREFIX_VEX_0F92,
1038   PREFIX_VEX_0F93,
1039   PREFIX_VEX_0F98,
1040   PREFIX_VEX_0FC2,
1041   PREFIX_VEX_0FC4,
1042   PREFIX_VEX_0FC5,
1043   PREFIX_VEX_0FD0,
1044   PREFIX_VEX_0FD1,
1045   PREFIX_VEX_0FD2,
1046   PREFIX_VEX_0FD3,
1047   PREFIX_VEX_0FD4,
1048   PREFIX_VEX_0FD5,
1049   PREFIX_VEX_0FD6,
1050   PREFIX_VEX_0FD7,
1051   PREFIX_VEX_0FD8,
1052   PREFIX_VEX_0FD9,
1053   PREFIX_VEX_0FDA,
1054   PREFIX_VEX_0FDB,
1055   PREFIX_VEX_0FDC,
1056   PREFIX_VEX_0FDD,
1057   PREFIX_VEX_0FDE,
1058   PREFIX_VEX_0FDF,
1059   PREFIX_VEX_0FE0,
1060   PREFIX_VEX_0FE1,
1061   PREFIX_VEX_0FE2,
1062   PREFIX_VEX_0FE3,
1063   PREFIX_VEX_0FE4,
1064   PREFIX_VEX_0FE5,
1065   PREFIX_VEX_0FE6,
1066   PREFIX_VEX_0FE7,
1067   PREFIX_VEX_0FE8,
1068   PREFIX_VEX_0FE9,
1069   PREFIX_VEX_0FEA,
1070   PREFIX_VEX_0FEB,
1071   PREFIX_VEX_0FEC,
1072   PREFIX_VEX_0FED,
1073   PREFIX_VEX_0FEE,
1074   PREFIX_VEX_0FEF,
1075   PREFIX_VEX_0FF0,
1076   PREFIX_VEX_0FF1,
1077   PREFIX_VEX_0FF2,
1078   PREFIX_VEX_0FF3,
1079   PREFIX_VEX_0FF4,
1080   PREFIX_VEX_0FF5,
1081   PREFIX_VEX_0FF6,
1082   PREFIX_VEX_0FF7,
1083   PREFIX_VEX_0FF8,
1084   PREFIX_VEX_0FF9,
1085   PREFIX_VEX_0FFA,
1086   PREFIX_VEX_0FFB,
1087   PREFIX_VEX_0FFC,
1088   PREFIX_VEX_0FFD,
1089   PREFIX_VEX_0FFE,
1090   PREFIX_VEX_0F3800,
1091   PREFIX_VEX_0F3801,
1092   PREFIX_VEX_0F3802,
1093   PREFIX_VEX_0F3803,
1094   PREFIX_VEX_0F3804,
1095   PREFIX_VEX_0F3805,
1096   PREFIX_VEX_0F3806,
1097   PREFIX_VEX_0F3807,
1098   PREFIX_VEX_0F3808,
1099   PREFIX_VEX_0F3809,
1100   PREFIX_VEX_0F380A,
1101   PREFIX_VEX_0F380B,
1102   PREFIX_VEX_0F380C,
1103   PREFIX_VEX_0F380D,
1104   PREFIX_VEX_0F380E,
1105   PREFIX_VEX_0F380F,
1106   PREFIX_VEX_0F3813,
1107   PREFIX_VEX_0F3816,
1108   PREFIX_VEX_0F3817,
1109   PREFIX_VEX_0F3818,
1110   PREFIX_VEX_0F3819,
1111   PREFIX_VEX_0F381A,
1112   PREFIX_VEX_0F381C,
1113   PREFIX_VEX_0F381D,
1114   PREFIX_VEX_0F381E,
1115   PREFIX_VEX_0F3820,
1116   PREFIX_VEX_0F3821,
1117   PREFIX_VEX_0F3822,
1118   PREFIX_VEX_0F3823,
1119   PREFIX_VEX_0F3824,
1120   PREFIX_VEX_0F3825,
1121   PREFIX_VEX_0F3828,
1122   PREFIX_VEX_0F3829,
1123   PREFIX_VEX_0F382A,
1124   PREFIX_VEX_0F382B,
1125   PREFIX_VEX_0F382C,
1126   PREFIX_VEX_0F382D,
1127   PREFIX_VEX_0F382E,
1128   PREFIX_VEX_0F382F,
1129   PREFIX_VEX_0F3830,
1130   PREFIX_VEX_0F3831,
1131   PREFIX_VEX_0F3832,
1132   PREFIX_VEX_0F3833,
1133   PREFIX_VEX_0F3834,
1134   PREFIX_VEX_0F3835,
1135   PREFIX_VEX_0F3836,
1136   PREFIX_VEX_0F3837,
1137   PREFIX_VEX_0F3838,
1138   PREFIX_VEX_0F3839,
1139   PREFIX_VEX_0F383A,
1140   PREFIX_VEX_0F383B,
1141   PREFIX_VEX_0F383C,
1142   PREFIX_VEX_0F383D,
1143   PREFIX_VEX_0F383E,
1144   PREFIX_VEX_0F383F,
1145   PREFIX_VEX_0F3840,
1146   PREFIX_VEX_0F3841,
1147   PREFIX_VEX_0F3845,
1148   PREFIX_VEX_0F3846,
1149   PREFIX_VEX_0F3847,
1150   PREFIX_VEX_0F3858,
1151   PREFIX_VEX_0F3859,
1152   PREFIX_VEX_0F385A,
1153   PREFIX_VEX_0F3878,
1154   PREFIX_VEX_0F3879,
1155   PREFIX_VEX_0F388C,
1156   PREFIX_VEX_0F388E,
1157   PREFIX_VEX_0F3890,
1158   PREFIX_VEX_0F3891,
1159   PREFIX_VEX_0F3892,
1160   PREFIX_VEX_0F3893,
1161   PREFIX_VEX_0F3896,
1162   PREFIX_VEX_0F3897,
1163   PREFIX_VEX_0F3898,
1164   PREFIX_VEX_0F3899,
1165   PREFIX_VEX_0F389A,
1166   PREFIX_VEX_0F389B,
1167   PREFIX_VEX_0F389C,
1168   PREFIX_VEX_0F389D,
1169   PREFIX_VEX_0F389E,
1170   PREFIX_VEX_0F389F,
1171   PREFIX_VEX_0F38A6,
1172   PREFIX_VEX_0F38A7,
1173   PREFIX_VEX_0F38A8,
1174   PREFIX_VEX_0F38A9,
1175   PREFIX_VEX_0F38AA,
1176   PREFIX_VEX_0F38AB,
1177   PREFIX_VEX_0F38AC,
1178   PREFIX_VEX_0F38AD,
1179   PREFIX_VEX_0F38AE,
1180   PREFIX_VEX_0F38AF,
1181   PREFIX_VEX_0F38B6,
1182   PREFIX_VEX_0F38B7,
1183   PREFIX_VEX_0F38B8,
1184   PREFIX_VEX_0F38B9,
1185   PREFIX_VEX_0F38BA,
1186   PREFIX_VEX_0F38BB,
1187   PREFIX_VEX_0F38BC,
1188   PREFIX_VEX_0F38BD,
1189   PREFIX_VEX_0F38BE,
1190   PREFIX_VEX_0F38BF,
1191   PREFIX_VEX_0F38DB,
1192   PREFIX_VEX_0F38DC,
1193   PREFIX_VEX_0F38DD,
1194   PREFIX_VEX_0F38DE,
1195   PREFIX_VEX_0F38DF,
1196   PREFIX_VEX_0F38F2,
1197   PREFIX_VEX_0F38F3_REG_1,
1198   PREFIX_VEX_0F38F3_REG_2,
1199   PREFIX_VEX_0F38F3_REG_3,
1200   PREFIX_VEX_0F38F5,
1201   PREFIX_VEX_0F38F6,
1202   PREFIX_VEX_0F38F7,
1203   PREFIX_VEX_0F3A00,
1204   PREFIX_VEX_0F3A01,
1205   PREFIX_VEX_0F3A02,
1206   PREFIX_VEX_0F3A04,
1207   PREFIX_VEX_0F3A05,
1208   PREFIX_VEX_0F3A06,
1209   PREFIX_VEX_0F3A08,
1210   PREFIX_VEX_0F3A09,
1211   PREFIX_VEX_0F3A0A,
1212   PREFIX_VEX_0F3A0B,
1213   PREFIX_VEX_0F3A0C,
1214   PREFIX_VEX_0F3A0D,
1215   PREFIX_VEX_0F3A0E,
1216   PREFIX_VEX_0F3A0F,
1217   PREFIX_VEX_0F3A14,
1218   PREFIX_VEX_0F3A15,
1219   PREFIX_VEX_0F3A16,
1220   PREFIX_VEX_0F3A17,
1221   PREFIX_VEX_0F3A18,
1222   PREFIX_VEX_0F3A19,
1223   PREFIX_VEX_0F3A1D,
1224   PREFIX_VEX_0F3A20,
1225   PREFIX_VEX_0F3A21,
1226   PREFIX_VEX_0F3A22,
1227   PREFIX_VEX_0F3A30,
1228   PREFIX_VEX_0F3A32,
1229   PREFIX_VEX_0F3A38,
1230   PREFIX_VEX_0F3A39,
1231   PREFIX_VEX_0F3A40,
1232   PREFIX_VEX_0F3A41,
1233   PREFIX_VEX_0F3A42,
1234   PREFIX_VEX_0F3A44,
1235   PREFIX_VEX_0F3A46,
1236   PREFIX_VEX_0F3A48,
1237   PREFIX_VEX_0F3A49,
1238   PREFIX_VEX_0F3A4A,
1239   PREFIX_VEX_0F3A4B,
1240   PREFIX_VEX_0F3A4C,
1241   PREFIX_VEX_0F3A5C,
1242   PREFIX_VEX_0F3A5D,
1243   PREFIX_VEX_0F3A5E,
1244   PREFIX_VEX_0F3A5F,
1245   PREFIX_VEX_0F3A60,
1246   PREFIX_VEX_0F3A61,
1247   PREFIX_VEX_0F3A62,
1248   PREFIX_VEX_0F3A63,
1249   PREFIX_VEX_0F3A68,
1250   PREFIX_VEX_0F3A69,
1251   PREFIX_VEX_0F3A6A,
1252   PREFIX_VEX_0F3A6B,
1253   PREFIX_VEX_0F3A6C,
1254   PREFIX_VEX_0F3A6D,
1255   PREFIX_VEX_0F3A6E,
1256   PREFIX_VEX_0F3A6F,
1257   PREFIX_VEX_0F3A78,
1258   PREFIX_VEX_0F3A79,
1259   PREFIX_VEX_0F3A7A,
1260   PREFIX_VEX_0F3A7B,
1261   PREFIX_VEX_0F3A7C,
1262   PREFIX_VEX_0F3A7D,
1263   PREFIX_VEX_0F3A7E,
1264   PREFIX_VEX_0F3A7F,
1265   PREFIX_VEX_0F3ADF,
1266   PREFIX_VEX_0F3AF0,
1267
1268   PREFIX_EVEX_0F10,
1269   PREFIX_EVEX_0F11,
1270   PREFIX_EVEX_0F12,
1271   PREFIX_EVEX_0F13,
1272   PREFIX_EVEX_0F14,
1273   PREFIX_EVEX_0F15,
1274   PREFIX_EVEX_0F16,
1275   PREFIX_EVEX_0F17,
1276   PREFIX_EVEX_0F28,
1277   PREFIX_EVEX_0F29,
1278   PREFIX_EVEX_0F2A,
1279   PREFIX_EVEX_0F2B,
1280   PREFIX_EVEX_0F2C,
1281   PREFIX_EVEX_0F2D,
1282   PREFIX_EVEX_0F2E,
1283   PREFIX_EVEX_0F2F,
1284   PREFIX_EVEX_0F51,
1285   PREFIX_EVEX_0F58,
1286   PREFIX_EVEX_0F59,
1287   PREFIX_EVEX_0F5A,
1288   PREFIX_EVEX_0F5B,
1289   PREFIX_EVEX_0F5C,
1290   PREFIX_EVEX_0F5D,
1291   PREFIX_EVEX_0F5E,
1292   PREFIX_EVEX_0F5F,
1293   PREFIX_EVEX_0F62,
1294   PREFIX_EVEX_0F66,
1295   PREFIX_EVEX_0F6A,
1296   PREFIX_EVEX_0F6C,
1297   PREFIX_EVEX_0F6D,
1298   PREFIX_EVEX_0F6E,
1299   PREFIX_EVEX_0F6F,
1300   PREFIX_EVEX_0F70,
1301   PREFIX_EVEX_0F72_REG_0,
1302   PREFIX_EVEX_0F72_REG_1,
1303   PREFIX_EVEX_0F72_REG_2,
1304   PREFIX_EVEX_0F72_REG_4,
1305   PREFIX_EVEX_0F72_REG_6,
1306   PREFIX_EVEX_0F73_REG_2,
1307   PREFIX_EVEX_0F73_REG_6,
1308   PREFIX_EVEX_0F76,
1309   PREFIX_EVEX_0F78,
1310   PREFIX_EVEX_0F79,
1311   PREFIX_EVEX_0F7A,
1312   PREFIX_EVEX_0F7B,
1313   PREFIX_EVEX_0F7E,
1314   PREFIX_EVEX_0F7F,
1315   PREFIX_EVEX_0FC2,
1316   PREFIX_EVEX_0FC6,
1317   PREFIX_EVEX_0FD2,
1318   PREFIX_EVEX_0FD3,
1319   PREFIX_EVEX_0FD4,
1320   PREFIX_EVEX_0FD6,
1321   PREFIX_EVEX_0FDB,
1322   PREFIX_EVEX_0FDF,
1323   PREFIX_EVEX_0FE2,
1324   PREFIX_EVEX_0FE6,
1325   PREFIX_EVEX_0FE7,
1326   PREFIX_EVEX_0FEB,
1327   PREFIX_EVEX_0FEF,
1328   PREFIX_EVEX_0FF2,
1329   PREFIX_EVEX_0FF3,
1330   PREFIX_EVEX_0FF4,
1331   PREFIX_EVEX_0FFA,
1332   PREFIX_EVEX_0FFB,
1333   PREFIX_EVEX_0FFE,
1334   PREFIX_EVEX_0F380C,
1335   PREFIX_EVEX_0F380D,
1336   PREFIX_EVEX_0F3811,
1337   PREFIX_EVEX_0F3812,
1338   PREFIX_EVEX_0F3813,
1339   PREFIX_EVEX_0F3814,
1340   PREFIX_EVEX_0F3815,
1341   PREFIX_EVEX_0F3816,
1342   PREFIX_EVEX_0F3818,
1343   PREFIX_EVEX_0F3819,
1344   PREFIX_EVEX_0F381A,
1345   PREFIX_EVEX_0F381B,
1346   PREFIX_EVEX_0F381E,
1347   PREFIX_EVEX_0F381F,
1348   PREFIX_EVEX_0F3821,
1349   PREFIX_EVEX_0F3822,
1350   PREFIX_EVEX_0F3823,
1351   PREFIX_EVEX_0F3824,
1352   PREFIX_EVEX_0F3825,
1353   PREFIX_EVEX_0F3827,
1354   PREFIX_EVEX_0F3828,
1355   PREFIX_EVEX_0F3829,
1356   PREFIX_EVEX_0F382A,
1357   PREFIX_EVEX_0F382C,
1358   PREFIX_EVEX_0F382D,
1359   PREFIX_EVEX_0F3831,
1360   PREFIX_EVEX_0F3832,
1361   PREFIX_EVEX_0F3833,
1362   PREFIX_EVEX_0F3834,
1363   PREFIX_EVEX_0F3835,
1364   PREFIX_EVEX_0F3836,
1365   PREFIX_EVEX_0F3837,
1366   PREFIX_EVEX_0F3839,
1367   PREFIX_EVEX_0F383A,
1368   PREFIX_EVEX_0F383B,
1369   PREFIX_EVEX_0F383D,
1370   PREFIX_EVEX_0F383F,
1371   PREFIX_EVEX_0F3840,
1372   PREFIX_EVEX_0F3842,
1373   PREFIX_EVEX_0F3843,
1374   PREFIX_EVEX_0F3844,
1375   PREFIX_EVEX_0F3845,
1376   PREFIX_EVEX_0F3846,
1377   PREFIX_EVEX_0F3847,
1378   PREFIX_EVEX_0F384C,
1379   PREFIX_EVEX_0F384D,
1380   PREFIX_EVEX_0F384E,
1381   PREFIX_EVEX_0F384F,
1382   PREFIX_EVEX_0F3858,
1383   PREFIX_EVEX_0F3859,
1384   PREFIX_EVEX_0F385A,
1385   PREFIX_EVEX_0F385B,
1386   PREFIX_EVEX_0F3864,
1387   PREFIX_EVEX_0F3865,
1388   PREFIX_EVEX_0F3876,
1389   PREFIX_EVEX_0F3877,
1390   PREFIX_EVEX_0F387C,
1391   PREFIX_EVEX_0F387E,
1392   PREFIX_EVEX_0F387F,
1393   PREFIX_EVEX_0F3888,
1394   PREFIX_EVEX_0F3889,
1395   PREFIX_EVEX_0F388A,
1396   PREFIX_EVEX_0F388B,
1397   PREFIX_EVEX_0F3890,
1398   PREFIX_EVEX_0F3891,
1399   PREFIX_EVEX_0F3892,
1400   PREFIX_EVEX_0F3893,
1401   PREFIX_EVEX_0F3896,
1402   PREFIX_EVEX_0F3897,
1403   PREFIX_EVEX_0F3898,
1404   PREFIX_EVEX_0F3899,
1405   PREFIX_EVEX_0F389A,
1406   PREFIX_EVEX_0F389B,
1407   PREFIX_EVEX_0F389C,
1408   PREFIX_EVEX_0F389D,
1409   PREFIX_EVEX_0F389E,
1410   PREFIX_EVEX_0F389F,
1411   PREFIX_EVEX_0F38A0,
1412   PREFIX_EVEX_0F38A1,
1413   PREFIX_EVEX_0F38A2,
1414   PREFIX_EVEX_0F38A3,
1415   PREFIX_EVEX_0F38A6,
1416   PREFIX_EVEX_0F38A7,
1417   PREFIX_EVEX_0F38A8,
1418   PREFIX_EVEX_0F38A9,
1419   PREFIX_EVEX_0F38AA,
1420   PREFIX_EVEX_0F38AB,
1421   PREFIX_EVEX_0F38AC,
1422   PREFIX_EVEX_0F38AD,
1423   PREFIX_EVEX_0F38AE,
1424   PREFIX_EVEX_0F38AF,
1425   PREFIX_EVEX_0F38B6,
1426   PREFIX_EVEX_0F38B7,
1427   PREFIX_EVEX_0F38B8,
1428   PREFIX_EVEX_0F38B9,
1429   PREFIX_EVEX_0F38BA,
1430   PREFIX_EVEX_0F38BB,
1431   PREFIX_EVEX_0F38BC,
1432   PREFIX_EVEX_0F38BD,
1433   PREFIX_EVEX_0F38BE,
1434   PREFIX_EVEX_0F38BF,
1435   PREFIX_EVEX_0F38C4,
1436   PREFIX_EVEX_0F38C6_REG_1,
1437   PREFIX_EVEX_0F38C6_REG_2,
1438   PREFIX_EVEX_0F38C6_REG_5,
1439   PREFIX_EVEX_0F38C6_REG_6,
1440   PREFIX_EVEX_0F38C7_REG_1,
1441   PREFIX_EVEX_0F38C7_REG_2,
1442   PREFIX_EVEX_0F38C7_REG_5,
1443   PREFIX_EVEX_0F38C7_REG_6,
1444   PREFIX_EVEX_0F38C8,
1445   PREFIX_EVEX_0F38CA,
1446   PREFIX_EVEX_0F38CB,
1447   PREFIX_EVEX_0F38CC,
1448   PREFIX_EVEX_0F38CD,
1449
1450   PREFIX_EVEX_0F3A00,
1451   PREFIX_EVEX_0F3A01,
1452   PREFIX_EVEX_0F3A03,
1453   PREFIX_EVEX_0F3A04,
1454   PREFIX_EVEX_0F3A05,
1455   PREFIX_EVEX_0F3A08,
1456   PREFIX_EVEX_0F3A09,
1457   PREFIX_EVEX_0F3A0A,
1458   PREFIX_EVEX_0F3A0B,
1459   PREFIX_EVEX_0F3A17,
1460   PREFIX_EVEX_0F3A18,
1461   PREFIX_EVEX_0F3A19,
1462   PREFIX_EVEX_0F3A1A,
1463   PREFIX_EVEX_0F3A1B,
1464   PREFIX_EVEX_0F3A1D,
1465   PREFIX_EVEX_0F3A1E,
1466   PREFIX_EVEX_0F3A1F,
1467   PREFIX_EVEX_0F3A21,
1468   PREFIX_EVEX_0F3A23,
1469   PREFIX_EVEX_0F3A25,
1470   PREFIX_EVEX_0F3A26,
1471   PREFIX_EVEX_0F3A27,
1472   PREFIX_EVEX_0F3A38,
1473   PREFIX_EVEX_0F3A39,
1474   PREFIX_EVEX_0F3A3A,
1475   PREFIX_EVEX_0F3A3B,
1476   PREFIX_EVEX_0F3A43,
1477   PREFIX_EVEX_0F3A54,
1478   PREFIX_EVEX_0F3A55,
1479 };
1480
1481 enum
1482 {
1483   X86_64_06 = 0,
1484   X86_64_07,
1485   X86_64_0D,
1486   X86_64_16,
1487   X86_64_17,
1488   X86_64_1E,
1489   X86_64_1F,
1490   X86_64_27,
1491   X86_64_2F,
1492   X86_64_37,
1493   X86_64_3F,
1494   X86_64_60,
1495   X86_64_61,
1496   X86_64_62,
1497   X86_64_63,
1498   X86_64_6D,
1499   X86_64_6F,
1500   X86_64_9A,
1501   X86_64_C4,
1502   X86_64_C5,
1503   X86_64_CE,
1504   X86_64_D4,
1505   X86_64_D5,
1506   X86_64_EA,
1507   X86_64_0F01_REG_0,
1508   X86_64_0F01_REG_1,
1509   X86_64_0F01_REG_2,
1510   X86_64_0F01_REG_3
1511 };
1512
1513 enum
1514 {
1515   THREE_BYTE_0F38 = 0,
1516   THREE_BYTE_0F3A,
1517   THREE_BYTE_0F7A
1518 };
1519
1520 enum
1521 {
1522   XOP_08 = 0,
1523   XOP_09,
1524   XOP_0A
1525 };
1526
1527 enum
1528 {
1529   VEX_0F = 0,
1530   VEX_0F38,
1531   VEX_0F3A
1532 };
1533
1534 enum
1535 {
1536   EVEX_0F = 0,
1537   EVEX_0F38,
1538   EVEX_0F3A
1539 };
1540
1541 enum
1542 {
1543   VEX_LEN_0F10_P_1 = 0,
1544   VEX_LEN_0F10_P_3,
1545   VEX_LEN_0F11_P_1,
1546   VEX_LEN_0F11_P_3,
1547   VEX_LEN_0F12_P_0_M_0,
1548   VEX_LEN_0F12_P_0_M_1,
1549   VEX_LEN_0F12_P_2,
1550   VEX_LEN_0F13_M_0,
1551   VEX_LEN_0F16_P_0_M_0,
1552   VEX_LEN_0F16_P_0_M_1,
1553   VEX_LEN_0F16_P_2,
1554   VEX_LEN_0F17_M_0,
1555   VEX_LEN_0F2A_P_1,
1556   VEX_LEN_0F2A_P_3,
1557   VEX_LEN_0F2C_P_1,
1558   VEX_LEN_0F2C_P_3,
1559   VEX_LEN_0F2D_P_1,
1560   VEX_LEN_0F2D_P_3,
1561   VEX_LEN_0F2E_P_0,
1562   VEX_LEN_0F2E_P_2,
1563   VEX_LEN_0F2F_P_0,
1564   VEX_LEN_0F2F_P_2,
1565   VEX_LEN_0F41_P_0,
1566   VEX_LEN_0F42_P_0,
1567   VEX_LEN_0F44_P_0,
1568   VEX_LEN_0F45_P_0,
1569   VEX_LEN_0F46_P_0,
1570   VEX_LEN_0F47_P_0,
1571   VEX_LEN_0F4B_P_2,
1572   VEX_LEN_0F51_P_1,
1573   VEX_LEN_0F51_P_3,
1574   VEX_LEN_0F52_P_1,
1575   VEX_LEN_0F53_P_1,
1576   VEX_LEN_0F58_P_1,
1577   VEX_LEN_0F58_P_3,
1578   VEX_LEN_0F59_P_1,
1579   VEX_LEN_0F59_P_3,
1580   VEX_LEN_0F5A_P_1,
1581   VEX_LEN_0F5A_P_3,
1582   VEX_LEN_0F5C_P_1,
1583   VEX_LEN_0F5C_P_3,
1584   VEX_LEN_0F5D_P_1,
1585   VEX_LEN_0F5D_P_3,
1586   VEX_LEN_0F5E_P_1,
1587   VEX_LEN_0F5E_P_3,
1588   VEX_LEN_0F5F_P_1,
1589   VEX_LEN_0F5F_P_3,
1590   VEX_LEN_0F6E_P_2,
1591   VEX_LEN_0F7E_P_1,
1592   VEX_LEN_0F7E_P_2,
1593   VEX_LEN_0F90_P_0,
1594   VEX_LEN_0F91_P_0,
1595   VEX_LEN_0F92_P_0,
1596   VEX_LEN_0F93_P_0,
1597   VEX_LEN_0F98_P_0,
1598   VEX_LEN_0FAE_R_2_M_0,
1599   VEX_LEN_0FAE_R_3_M_0,
1600   VEX_LEN_0FC2_P_1,
1601   VEX_LEN_0FC2_P_3,
1602   VEX_LEN_0FC4_P_2,
1603   VEX_LEN_0FC5_P_2,
1604   VEX_LEN_0FD6_P_2,
1605   VEX_LEN_0FF7_P_2,
1606   VEX_LEN_0F3816_P_2,
1607   VEX_LEN_0F3819_P_2,
1608   VEX_LEN_0F381A_P_2_M_0,
1609   VEX_LEN_0F3836_P_2,
1610   VEX_LEN_0F3841_P_2,
1611   VEX_LEN_0F385A_P_2_M_0,
1612   VEX_LEN_0F38DB_P_2,
1613   VEX_LEN_0F38DC_P_2,
1614   VEX_LEN_0F38DD_P_2,
1615   VEX_LEN_0F38DE_P_2,
1616   VEX_LEN_0F38DF_P_2,
1617   VEX_LEN_0F38F2_P_0,
1618   VEX_LEN_0F38F3_R_1_P_0,
1619   VEX_LEN_0F38F3_R_2_P_0,
1620   VEX_LEN_0F38F3_R_3_P_0,
1621   VEX_LEN_0F38F5_P_0,
1622   VEX_LEN_0F38F5_P_1,
1623   VEX_LEN_0F38F5_P_3,
1624   VEX_LEN_0F38F6_P_3,
1625   VEX_LEN_0F38F7_P_0,
1626   VEX_LEN_0F38F7_P_1,
1627   VEX_LEN_0F38F7_P_2,
1628   VEX_LEN_0F38F7_P_3,
1629   VEX_LEN_0F3A00_P_2,
1630   VEX_LEN_0F3A01_P_2,
1631   VEX_LEN_0F3A06_P_2,
1632   VEX_LEN_0F3A0A_P_2,
1633   VEX_LEN_0F3A0B_P_2,
1634   VEX_LEN_0F3A14_P_2,
1635   VEX_LEN_0F3A15_P_2,
1636   VEX_LEN_0F3A16_P_2,
1637   VEX_LEN_0F3A17_P_2,
1638   VEX_LEN_0F3A18_P_2,
1639   VEX_LEN_0F3A19_P_2,
1640   VEX_LEN_0F3A20_P_2,
1641   VEX_LEN_0F3A21_P_2,
1642   VEX_LEN_0F3A22_P_2,
1643   VEX_LEN_0F3A30_P_2,
1644   VEX_LEN_0F3A32_P_2,
1645   VEX_LEN_0F3A38_P_2,
1646   VEX_LEN_0F3A39_P_2,
1647   VEX_LEN_0F3A41_P_2,
1648   VEX_LEN_0F3A44_P_2,
1649   VEX_LEN_0F3A46_P_2,
1650   VEX_LEN_0F3A60_P_2,
1651   VEX_LEN_0F3A61_P_2,
1652   VEX_LEN_0F3A62_P_2,
1653   VEX_LEN_0F3A63_P_2,
1654   VEX_LEN_0F3A6A_P_2,
1655   VEX_LEN_0F3A6B_P_2,
1656   VEX_LEN_0F3A6E_P_2,
1657   VEX_LEN_0F3A6F_P_2,
1658   VEX_LEN_0F3A7A_P_2,
1659   VEX_LEN_0F3A7B_P_2,
1660   VEX_LEN_0F3A7E_P_2,
1661   VEX_LEN_0F3A7F_P_2,
1662   VEX_LEN_0F3ADF_P_2,
1663   VEX_LEN_0F3AF0_P_3,
1664   VEX_LEN_0FXOP_08_CC,
1665   VEX_LEN_0FXOP_08_CD,
1666   VEX_LEN_0FXOP_08_CE,
1667   VEX_LEN_0FXOP_08_CF,
1668   VEX_LEN_0FXOP_08_EC,
1669   VEX_LEN_0FXOP_08_ED,
1670   VEX_LEN_0FXOP_08_EE,
1671   VEX_LEN_0FXOP_08_EF,
1672   VEX_LEN_0FXOP_09_80,
1673   VEX_LEN_0FXOP_09_81
1674 };
1675
1676 enum
1677 {
1678   VEX_W_0F10_P_0 = 0,
1679   VEX_W_0F10_P_1,
1680   VEX_W_0F10_P_2,
1681   VEX_W_0F10_P_3,
1682   VEX_W_0F11_P_0,
1683   VEX_W_0F11_P_1,
1684   VEX_W_0F11_P_2,
1685   VEX_W_0F11_P_3,
1686   VEX_W_0F12_P_0_M_0,
1687   VEX_W_0F12_P_0_M_1,
1688   VEX_W_0F12_P_1,
1689   VEX_W_0F12_P_2,
1690   VEX_W_0F12_P_3,
1691   VEX_W_0F13_M_0,
1692   VEX_W_0F14,
1693   VEX_W_0F15,
1694   VEX_W_0F16_P_0_M_0,
1695   VEX_W_0F16_P_0_M_1,
1696   VEX_W_0F16_P_1,
1697   VEX_W_0F16_P_2,
1698   VEX_W_0F17_M_0,
1699   VEX_W_0F28,
1700   VEX_W_0F29,
1701   VEX_W_0F2B_M_0,
1702   VEX_W_0F2E_P_0,
1703   VEX_W_0F2E_P_2,
1704   VEX_W_0F2F_P_0,
1705   VEX_W_0F2F_P_2,
1706   VEX_W_0F41_P_0_LEN_1,
1707   VEX_W_0F42_P_0_LEN_1,
1708   VEX_W_0F44_P_0_LEN_0,
1709   VEX_W_0F45_P_0_LEN_1,
1710   VEX_W_0F46_P_0_LEN_1,
1711   VEX_W_0F47_P_0_LEN_1,
1712   VEX_W_0F4B_P_2_LEN_1,
1713   VEX_W_0F50_M_0,
1714   VEX_W_0F51_P_0,
1715   VEX_W_0F51_P_1,
1716   VEX_W_0F51_P_2,
1717   VEX_W_0F51_P_3,
1718   VEX_W_0F52_P_0,
1719   VEX_W_0F52_P_1,
1720   VEX_W_0F53_P_0,
1721   VEX_W_0F53_P_1,
1722   VEX_W_0F58_P_0,
1723   VEX_W_0F58_P_1,
1724   VEX_W_0F58_P_2,
1725   VEX_W_0F58_P_3,
1726   VEX_W_0F59_P_0,
1727   VEX_W_0F59_P_1,
1728   VEX_W_0F59_P_2,
1729   VEX_W_0F59_P_3,
1730   VEX_W_0F5A_P_0,
1731   VEX_W_0F5A_P_1,
1732   VEX_W_0F5A_P_3,
1733   VEX_W_0F5B_P_0,
1734   VEX_W_0F5B_P_1,
1735   VEX_W_0F5B_P_2,
1736   VEX_W_0F5C_P_0,
1737   VEX_W_0F5C_P_1,
1738   VEX_W_0F5C_P_2,
1739   VEX_W_0F5C_P_3,
1740   VEX_W_0F5D_P_0,
1741   VEX_W_0F5D_P_1,
1742   VEX_W_0F5D_P_2,
1743   VEX_W_0F5D_P_3,
1744   VEX_W_0F5E_P_0,
1745   VEX_W_0F5E_P_1,
1746   VEX_W_0F5E_P_2,
1747   VEX_W_0F5E_P_3,
1748   VEX_W_0F5F_P_0,
1749   VEX_W_0F5F_P_1,
1750   VEX_W_0F5F_P_2,
1751   VEX_W_0F5F_P_3,
1752   VEX_W_0F60_P_2,
1753   VEX_W_0F61_P_2,
1754   VEX_W_0F62_P_2,
1755   VEX_W_0F63_P_2,
1756   VEX_W_0F64_P_2,
1757   VEX_W_0F65_P_2,
1758   VEX_W_0F66_P_2,
1759   VEX_W_0F67_P_2,
1760   VEX_W_0F68_P_2,
1761   VEX_W_0F69_P_2,
1762   VEX_W_0F6A_P_2,
1763   VEX_W_0F6B_P_2,
1764   VEX_W_0F6C_P_2,
1765   VEX_W_0F6D_P_2,
1766   VEX_W_0F6F_P_1,
1767   VEX_W_0F6F_P_2,
1768   VEX_W_0F70_P_1,
1769   VEX_W_0F70_P_2,
1770   VEX_W_0F70_P_3,
1771   VEX_W_0F71_R_2_P_2,
1772   VEX_W_0F71_R_4_P_2,
1773   VEX_W_0F71_R_6_P_2,
1774   VEX_W_0F72_R_2_P_2,
1775   VEX_W_0F72_R_4_P_2,
1776   VEX_W_0F72_R_6_P_2,
1777   VEX_W_0F73_R_2_P_2,
1778   VEX_W_0F73_R_3_P_2,
1779   VEX_W_0F73_R_6_P_2,
1780   VEX_W_0F73_R_7_P_2,
1781   VEX_W_0F74_P_2,
1782   VEX_W_0F75_P_2,
1783   VEX_W_0F76_P_2,
1784   VEX_W_0F77_P_0,
1785   VEX_W_0F7C_P_2,
1786   VEX_W_0F7C_P_3,
1787   VEX_W_0F7D_P_2,
1788   VEX_W_0F7D_P_3,
1789   VEX_W_0F7E_P_1,
1790   VEX_W_0F7F_P_1,
1791   VEX_W_0F7F_P_2,
1792   VEX_W_0F90_P_0_LEN_0,
1793   VEX_W_0F91_P_0_LEN_0,
1794   VEX_W_0F92_P_0_LEN_0,
1795   VEX_W_0F93_P_0_LEN_0,
1796   VEX_W_0F98_P_0_LEN_0,
1797   VEX_W_0FAE_R_2_M_0,
1798   VEX_W_0FAE_R_3_M_0,
1799   VEX_W_0FC2_P_0,
1800   VEX_W_0FC2_P_1,
1801   VEX_W_0FC2_P_2,
1802   VEX_W_0FC2_P_3,
1803   VEX_W_0FC4_P_2,
1804   VEX_W_0FC5_P_2,
1805   VEX_W_0FD0_P_2,
1806   VEX_W_0FD0_P_3,
1807   VEX_W_0FD1_P_2,
1808   VEX_W_0FD2_P_2,
1809   VEX_W_0FD3_P_2,
1810   VEX_W_0FD4_P_2,
1811   VEX_W_0FD5_P_2,
1812   VEX_W_0FD6_P_2,
1813   VEX_W_0FD7_P_2_M_1,
1814   VEX_W_0FD8_P_2,
1815   VEX_W_0FD9_P_2,
1816   VEX_W_0FDA_P_2,
1817   VEX_W_0FDB_P_2,
1818   VEX_W_0FDC_P_2,
1819   VEX_W_0FDD_P_2,
1820   VEX_W_0FDE_P_2,
1821   VEX_W_0FDF_P_2,
1822   VEX_W_0FE0_P_2,
1823   VEX_W_0FE1_P_2,
1824   VEX_W_0FE2_P_2,
1825   VEX_W_0FE3_P_2,
1826   VEX_W_0FE4_P_2,
1827   VEX_W_0FE5_P_2,
1828   VEX_W_0FE6_P_1,
1829   VEX_W_0FE6_P_2,
1830   VEX_W_0FE6_P_3,
1831   VEX_W_0FE7_P_2_M_0,
1832   VEX_W_0FE8_P_2,
1833   VEX_W_0FE9_P_2,
1834   VEX_W_0FEA_P_2,
1835   VEX_W_0FEB_P_2,
1836   VEX_W_0FEC_P_2,
1837   VEX_W_0FED_P_2,
1838   VEX_W_0FEE_P_2,
1839   VEX_W_0FEF_P_2,
1840   VEX_W_0FF0_P_3_M_0,
1841   VEX_W_0FF1_P_2,
1842   VEX_W_0FF2_P_2,
1843   VEX_W_0FF3_P_2,
1844   VEX_W_0FF4_P_2,
1845   VEX_W_0FF5_P_2,
1846   VEX_W_0FF6_P_2,
1847   VEX_W_0FF7_P_2,
1848   VEX_W_0FF8_P_2,
1849   VEX_W_0FF9_P_2,
1850   VEX_W_0FFA_P_2,
1851   VEX_W_0FFB_P_2,
1852   VEX_W_0FFC_P_2,
1853   VEX_W_0FFD_P_2,
1854   VEX_W_0FFE_P_2,
1855   VEX_W_0F3800_P_2,
1856   VEX_W_0F3801_P_2,
1857   VEX_W_0F3802_P_2,
1858   VEX_W_0F3803_P_2,
1859   VEX_W_0F3804_P_2,
1860   VEX_W_0F3805_P_2,
1861   VEX_W_0F3806_P_2,
1862   VEX_W_0F3807_P_2,
1863   VEX_W_0F3808_P_2,
1864   VEX_W_0F3809_P_2,
1865   VEX_W_0F380A_P_2,
1866   VEX_W_0F380B_P_2,
1867   VEX_W_0F380C_P_2,
1868   VEX_W_0F380D_P_2,
1869   VEX_W_0F380E_P_2,
1870   VEX_W_0F380F_P_2,
1871   VEX_W_0F3816_P_2,
1872   VEX_W_0F3817_P_2,
1873   VEX_W_0F3818_P_2,
1874   VEX_W_0F3819_P_2,
1875   VEX_W_0F381A_P_2_M_0,
1876   VEX_W_0F381C_P_2,
1877   VEX_W_0F381D_P_2,
1878   VEX_W_0F381E_P_2,
1879   VEX_W_0F3820_P_2,
1880   VEX_W_0F3821_P_2,
1881   VEX_W_0F3822_P_2,
1882   VEX_W_0F3823_P_2,
1883   VEX_W_0F3824_P_2,
1884   VEX_W_0F3825_P_2,
1885   VEX_W_0F3828_P_2,
1886   VEX_W_0F3829_P_2,
1887   VEX_W_0F382A_P_2_M_0,
1888   VEX_W_0F382B_P_2,
1889   VEX_W_0F382C_P_2_M_0,
1890   VEX_W_0F382D_P_2_M_0,
1891   VEX_W_0F382E_P_2_M_0,
1892   VEX_W_0F382F_P_2_M_0,
1893   VEX_W_0F3830_P_2,
1894   VEX_W_0F3831_P_2,
1895   VEX_W_0F3832_P_2,
1896   VEX_W_0F3833_P_2,
1897   VEX_W_0F3834_P_2,
1898   VEX_W_0F3835_P_2,
1899   VEX_W_0F3836_P_2,
1900   VEX_W_0F3837_P_2,
1901   VEX_W_0F3838_P_2,
1902   VEX_W_0F3839_P_2,
1903   VEX_W_0F383A_P_2,
1904   VEX_W_0F383B_P_2,
1905   VEX_W_0F383C_P_2,
1906   VEX_W_0F383D_P_2,
1907   VEX_W_0F383E_P_2,
1908   VEX_W_0F383F_P_2,
1909   VEX_W_0F3840_P_2,
1910   VEX_W_0F3841_P_2,
1911   VEX_W_0F3846_P_2,
1912   VEX_W_0F3858_P_2,
1913   VEX_W_0F3859_P_2,
1914   VEX_W_0F385A_P_2_M_0,
1915   VEX_W_0F3878_P_2,
1916   VEX_W_0F3879_P_2,
1917   VEX_W_0F38DB_P_2,
1918   VEX_W_0F38DC_P_2,
1919   VEX_W_0F38DD_P_2,
1920   VEX_W_0F38DE_P_2,
1921   VEX_W_0F38DF_P_2,
1922   VEX_W_0F3A00_P_2,
1923   VEX_W_0F3A01_P_2,
1924   VEX_W_0F3A02_P_2,
1925   VEX_W_0F3A04_P_2,
1926   VEX_W_0F3A05_P_2,
1927   VEX_W_0F3A06_P_2,
1928   VEX_W_0F3A08_P_2,
1929   VEX_W_0F3A09_P_2,
1930   VEX_W_0F3A0A_P_2,
1931   VEX_W_0F3A0B_P_2,
1932   VEX_W_0F3A0C_P_2,
1933   VEX_W_0F3A0D_P_2,
1934   VEX_W_0F3A0E_P_2,
1935   VEX_W_0F3A0F_P_2,
1936   VEX_W_0F3A14_P_2,
1937   VEX_W_0F3A15_P_2,
1938   VEX_W_0F3A18_P_2,
1939   VEX_W_0F3A19_P_2,
1940   VEX_W_0F3A20_P_2,
1941   VEX_W_0F3A21_P_2,
1942   VEX_W_0F3A30_P_2_LEN_0,
1943   VEX_W_0F3A32_P_2_LEN_0,
1944   VEX_W_0F3A38_P_2,
1945   VEX_W_0F3A39_P_2,
1946   VEX_W_0F3A40_P_2,
1947   VEX_W_0F3A41_P_2,
1948   VEX_W_0F3A42_P_2,
1949   VEX_W_0F3A44_P_2,
1950   VEX_W_0F3A46_P_2,
1951   VEX_W_0F3A48_P_2,
1952   VEX_W_0F3A49_P_2,
1953   VEX_W_0F3A4A_P_2,
1954   VEX_W_0F3A4B_P_2,
1955   VEX_W_0F3A4C_P_2,
1956   VEX_W_0F3A60_P_2,
1957   VEX_W_0F3A61_P_2,
1958   VEX_W_0F3A62_P_2,
1959   VEX_W_0F3A63_P_2,
1960   VEX_W_0F3ADF_P_2,
1961
1962   EVEX_W_0F10_P_0,
1963   EVEX_W_0F10_P_1_M_0,
1964   EVEX_W_0F10_P_1_M_1,
1965   EVEX_W_0F10_P_2,
1966   EVEX_W_0F10_P_3_M_0,
1967   EVEX_W_0F10_P_3_M_1,
1968   EVEX_W_0F11_P_0,
1969   EVEX_W_0F11_P_1_M_0,
1970   EVEX_W_0F11_P_1_M_1,
1971   EVEX_W_0F11_P_2,
1972   EVEX_W_0F11_P_3_M_0,
1973   EVEX_W_0F11_P_3_M_1,
1974   EVEX_W_0F12_P_0_M_0,
1975   EVEX_W_0F12_P_0_M_1,
1976   EVEX_W_0F12_P_1,
1977   EVEX_W_0F12_P_2,
1978   EVEX_W_0F12_P_3,
1979   EVEX_W_0F13_P_0,
1980   EVEX_W_0F13_P_2,
1981   EVEX_W_0F14_P_0,
1982   EVEX_W_0F14_P_2,
1983   EVEX_W_0F15_P_0,
1984   EVEX_W_0F15_P_2,
1985   EVEX_W_0F16_P_0_M_0,
1986   EVEX_W_0F16_P_0_M_1,
1987   EVEX_W_0F16_P_1,
1988   EVEX_W_0F16_P_2,
1989   EVEX_W_0F17_P_0,
1990   EVEX_W_0F17_P_2,
1991   EVEX_W_0F28_P_0,
1992   EVEX_W_0F28_P_2,
1993   EVEX_W_0F29_P_0,
1994   EVEX_W_0F29_P_2,
1995   EVEX_W_0F2A_P_1,
1996   EVEX_W_0F2A_P_3,
1997   EVEX_W_0F2B_P_0,
1998   EVEX_W_0F2B_P_2,
1999   EVEX_W_0F2E_P_0,
2000   EVEX_W_0F2E_P_2,
2001   EVEX_W_0F2F_P_0,
2002   EVEX_W_0F2F_P_2,
2003   EVEX_W_0F51_P_0,
2004   EVEX_W_0F51_P_1,
2005   EVEX_W_0F51_P_2,
2006   EVEX_W_0F51_P_3,
2007   EVEX_W_0F58_P_0,
2008   EVEX_W_0F58_P_1,
2009   EVEX_W_0F58_P_2,
2010   EVEX_W_0F58_P_3,
2011   EVEX_W_0F59_P_0,
2012   EVEX_W_0F59_P_1,
2013   EVEX_W_0F59_P_2,
2014   EVEX_W_0F59_P_3,
2015   EVEX_W_0F5A_P_0,
2016   EVEX_W_0F5A_P_1,
2017   EVEX_W_0F5A_P_2,
2018   EVEX_W_0F5A_P_3,
2019   EVEX_W_0F5B_P_0,
2020   EVEX_W_0F5B_P_1,
2021   EVEX_W_0F5B_P_2,
2022   EVEX_W_0F5C_P_0,
2023   EVEX_W_0F5C_P_1,
2024   EVEX_W_0F5C_P_2,
2025   EVEX_W_0F5C_P_3,
2026   EVEX_W_0F5D_P_0,
2027   EVEX_W_0F5D_P_1,
2028   EVEX_W_0F5D_P_2,
2029   EVEX_W_0F5D_P_3,
2030   EVEX_W_0F5E_P_0,
2031   EVEX_W_0F5E_P_1,
2032   EVEX_W_0F5E_P_2,
2033   EVEX_W_0F5E_P_3,
2034   EVEX_W_0F5F_P_0,
2035   EVEX_W_0F5F_P_1,
2036   EVEX_W_0F5F_P_2,
2037   EVEX_W_0F5F_P_3,
2038   EVEX_W_0F62_P_2,
2039   EVEX_W_0F66_P_2,
2040   EVEX_W_0F6A_P_2,
2041   EVEX_W_0F6C_P_2,
2042   EVEX_W_0F6D_P_2,
2043   EVEX_W_0F6E_P_2,
2044   EVEX_W_0F6F_P_1,
2045   EVEX_W_0F6F_P_2,
2046   EVEX_W_0F70_P_2,
2047   EVEX_W_0F72_R_2_P_2,
2048   EVEX_W_0F72_R_6_P_2,
2049   EVEX_W_0F73_R_2_P_2,
2050   EVEX_W_0F73_R_6_P_2,
2051   EVEX_W_0F76_P_2,
2052   EVEX_W_0F78_P_0,
2053   EVEX_W_0F79_P_0,
2054   EVEX_W_0F7A_P_1,
2055   EVEX_W_0F7A_P_3,
2056   EVEX_W_0F7B_P_1,
2057   EVEX_W_0F7B_P_3,
2058   EVEX_W_0F7E_P_1,
2059   EVEX_W_0F7E_P_2,
2060   EVEX_W_0F7F_P_1,
2061   EVEX_W_0F7F_P_2,
2062   EVEX_W_0FC2_P_0,
2063   EVEX_W_0FC2_P_1,
2064   EVEX_W_0FC2_P_2,
2065   EVEX_W_0FC2_P_3,
2066   EVEX_W_0FC6_P_0,
2067   EVEX_W_0FC6_P_2,
2068   EVEX_W_0FD2_P_2,
2069   EVEX_W_0FD3_P_2,
2070   EVEX_W_0FD4_P_2,
2071   EVEX_W_0FD6_P_2,
2072   EVEX_W_0FE6_P_1,
2073   EVEX_W_0FE6_P_2,
2074   EVEX_W_0FE6_P_3,
2075   EVEX_W_0FE7_P_2,
2076   EVEX_W_0FF2_P_2,
2077   EVEX_W_0FF3_P_2,
2078   EVEX_W_0FF4_P_2,
2079   EVEX_W_0FFA_P_2,
2080   EVEX_W_0FFB_P_2,
2081   EVEX_W_0FFE_P_2,
2082   EVEX_W_0F380C_P_2,
2083   EVEX_W_0F380D_P_2,
2084   EVEX_W_0F3811_P_1,
2085   EVEX_W_0F3812_P_1,
2086   EVEX_W_0F3813_P_1,
2087   EVEX_W_0F3813_P_2,
2088   EVEX_W_0F3814_P_1,
2089   EVEX_W_0F3815_P_1,
2090   EVEX_W_0F3818_P_2,
2091   EVEX_W_0F3819_P_2,
2092   EVEX_W_0F381A_P_2,
2093   EVEX_W_0F381B_P_2,
2094   EVEX_W_0F381E_P_2,
2095   EVEX_W_0F381F_P_2,
2096   EVEX_W_0F3821_P_1,
2097   EVEX_W_0F3822_P_1,
2098   EVEX_W_0F3823_P_1,
2099   EVEX_W_0F3824_P_1,
2100   EVEX_W_0F3825_P_1,
2101   EVEX_W_0F3825_P_2,
2102   EVEX_W_0F3828_P_2,
2103   EVEX_W_0F3829_P_2,
2104   EVEX_W_0F382A_P_1,
2105   EVEX_W_0F382A_P_2,
2106   EVEX_W_0F3831_P_1,
2107   EVEX_W_0F3832_P_1,
2108   EVEX_W_0F3833_P_1,
2109   EVEX_W_0F3834_P_1,
2110   EVEX_W_0F3835_P_1,
2111   EVEX_W_0F3835_P_2,
2112   EVEX_W_0F3837_P_2,
2113   EVEX_W_0F383A_P_1,
2114   EVEX_W_0F3840_P_2,
2115   EVEX_W_0F3858_P_2,
2116   EVEX_W_0F3859_P_2,
2117   EVEX_W_0F385A_P_2,
2118   EVEX_W_0F385B_P_2,
2119   EVEX_W_0F3891_P_2,
2120   EVEX_W_0F3893_P_2,
2121   EVEX_W_0F38A1_P_2,
2122   EVEX_W_0F38A3_P_2,
2123   EVEX_W_0F38C7_R_1_P_2,
2124   EVEX_W_0F38C7_R_2_P_2,
2125   EVEX_W_0F38C7_R_5_P_2,
2126   EVEX_W_0F38C7_R_6_P_2,
2127
2128   EVEX_W_0F3A00_P_2,
2129   EVEX_W_0F3A01_P_2,
2130   EVEX_W_0F3A04_P_2,
2131   EVEX_W_0F3A05_P_2,
2132   EVEX_W_0F3A08_P_2,
2133   EVEX_W_0F3A09_P_2,
2134   EVEX_W_0F3A0A_P_2,
2135   EVEX_W_0F3A0B_P_2,
2136   EVEX_W_0F3A18_P_2,
2137   EVEX_W_0F3A19_P_2,
2138   EVEX_W_0F3A1A_P_2,
2139   EVEX_W_0F3A1B_P_2,
2140   EVEX_W_0F3A1D_P_2,
2141   EVEX_W_0F3A21_P_2,
2142   EVEX_W_0F3A23_P_2,
2143   EVEX_W_0F3A38_P_2,
2144   EVEX_W_0F3A39_P_2,
2145   EVEX_W_0F3A3A_P_2,
2146   EVEX_W_0F3A3B_P_2,
2147   EVEX_W_0F3A43_P_2,
2148 };
2149
2150 typedef void (*op_rtn) (int bytemode, int sizeflag);
2151
2152 struct dis386 {
2153   const char *name;
2154   struct
2155     {
2156       op_rtn rtn;
2157       int bytemode;
2158     } op[MAX_OPERANDS];
2159 };
2160
2161 /* Upper case letters in the instruction names here are macros.
2162    'A' => print 'b' if no register operands or suffix_always is true
2163    'B' => print 'b' if suffix_always is true
2164    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2165           size prefix
2166    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2167           suffix_always is true
2168    'E' => print 'e' if 32-bit form of jcxz
2169    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2170    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2171    'H' => print ",pt" or ",pn" branch hint
2172    'I' => honor following macro letter even in Intel mode (implemented only
2173           for some of the macro letters)
2174    'J' => print 'l'
2175    'K' => print 'd' or 'q' if rex prefix is present.
2176    'L' => print 'l' if suffix_always is true
2177    'M' => print 'r' if intel_mnemonic is false.
2178    'N' => print 'n' if instruction has no wait "prefix"
2179    'O' => print 'd' or 'o' (or 'q' in Intel mode)
2180    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2181           or suffix_always is true.  print 'q' if rex prefix is present.
2182    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2183           is true
2184    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2185    'S' => print 'w', 'l' or 'q' if suffix_always is true
2186    'T' => print 'q' in 64bit mode and behave as 'P' otherwise
2187    'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
2188    'V' => print 'q' in 64bit mode and behave as 'S' otherwise
2189    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2190    'X' => print 's', 'd' depending on data16 prefix (for XMM)
2191    'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
2192           suffix_always is true.
2193    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2194    '!' => change condition from true to false or from false to true.
2195    '%' => add 1 upper case letter to the macro.
2196
2197    2 upper case letter macros:
2198    "XY" => print 'x' or 'y' if no register operands or suffix_always
2199            is true.
2200    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2201    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2202            or suffix_always is true
2203    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2204    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2205    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2206    "LW" => print 'd', 'q' depending on the VEX.W bit
2207
2208    Many of the above letters print nothing in Intel mode.  See "putop"
2209    for the details.
2210
2211    Braces '{' and '}', and vertical bars '|', indicate alternative
2212    mnemonic strings for AT&T and Intel.  */
2213
2214 static const struct dis386 dis386[] = {
2215   /* 00 */
2216   { "addB",             { Ebh1, Gb } },
2217   { "addS",             { Evh1, Gv } },
2218   { "addB",             { Gb, EbS } },
2219   { "addS",             { Gv, EvS } },
2220   { "addB",             { AL, Ib } },
2221   { "addS",             { eAX, Iv } },
2222   { X86_64_TABLE (X86_64_06) },
2223   { X86_64_TABLE (X86_64_07) },
2224   /* 08 */
2225   { "orB",              { Ebh1, Gb } },
2226   { "orS",              { Evh1, Gv } },
2227   { "orB",              { Gb, EbS } },
2228   { "orS",              { Gv, EvS } },
2229   { "orB",              { AL, Ib } },
2230   { "orS",              { eAX, Iv } },
2231   { X86_64_TABLE (X86_64_0D) },
2232   { Bad_Opcode },       /* 0x0f extended opcode escape */
2233   /* 10 */
2234   { "adcB",             { Ebh1, Gb } },
2235   { "adcS",             { Evh1, Gv } },
2236   { "adcB",             { Gb, EbS } },
2237   { "adcS",             { Gv, EvS } },
2238   { "adcB",             { AL, Ib } },
2239   { "adcS",             { eAX, Iv } },
2240   { X86_64_TABLE (X86_64_16) },
2241   { X86_64_TABLE (X86_64_17) },
2242   /* 18 */
2243   { "sbbB",             { Ebh1, Gb } },
2244   { "sbbS",             { Evh1, Gv } },
2245   { "sbbB",             { Gb, EbS } },
2246   { "sbbS",             { Gv, EvS } },
2247   { "sbbB",             { AL, Ib } },
2248   { "sbbS",             { eAX, Iv } },
2249   { X86_64_TABLE (X86_64_1E) },
2250   { X86_64_TABLE (X86_64_1F) },
2251   /* 20 */
2252   { "andB",             { Ebh1, Gb } },
2253   { "andS",             { Evh1, Gv } },
2254   { "andB",             { Gb, EbS } },
2255   { "andS",             { Gv, EvS } },
2256   { "andB",             { AL, Ib } },
2257   { "andS",             { eAX, Iv } },
2258   { Bad_Opcode },       /* SEG ES prefix */
2259   { X86_64_TABLE (X86_64_27) },
2260   /* 28 */
2261   { "subB",             { Ebh1, Gb } },
2262   { "subS",             { Evh1, Gv } },
2263   { "subB",             { Gb, EbS } },
2264   { "subS",             { Gv, EvS } },
2265   { "subB",             { AL, Ib } },
2266   { "subS",             { eAX, Iv } },
2267   { Bad_Opcode },       /* SEG CS prefix */
2268   { X86_64_TABLE (X86_64_2F) },
2269   /* 30 */
2270   { "xorB",             { Ebh1, Gb } },
2271   { "xorS",             { Evh1, Gv } },
2272   { "xorB",             { Gb, EbS } },
2273   { "xorS",             { Gv, EvS } },
2274   { "xorB",             { AL, Ib } },
2275   { "xorS",             { eAX, Iv } },
2276   { Bad_Opcode },       /* SEG SS prefix */
2277   { X86_64_TABLE (X86_64_37) },
2278   /* 38 */
2279   { "cmpB",             { Eb, Gb } },
2280   { "cmpS",             { Ev, Gv } },
2281   { "cmpB",             { Gb, EbS } },
2282   { "cmpS",             { Gv, EvS } },
2283   { "cmpB",             { AL, Ib } },
2284   { "cmpS",             { eAX, Iv } },
2285   { Bad_Opcode },       /* SEG DS prefix */
2286   { X86_64_TABLE (X86_64_3F) },
2287   /* 40 */
2288   { "inc{S|}",          { RMeAX } },
2289   { "inc{S|}",          { RMeCX } },
2290   { "inc{S|}",          { RMeDX } },
2291   { "inc{S|}",          { RMeBX } },
2292   { "inc{S|}",          { RMeSP } },
2293   { "inc{S|}",          { RMeBP } },
2294   { "inc{S|}",          { RMeSI } },
2295   { "inc{S|}",          { RMeDI } },
2296   /* 48 */
2297   { "dec{S|}",          { RMeAX } },
2298   { "dec{S|}",          { RMeCX } },
2299   { "dec{S|}",          { RMeDX } },
2300   { "dec{S|}",          { RMeBX } },
2301   { "dec{S|}",          { RMeSP } },
2302   { "dec{S|}",          { RMeBP } },
2303   { "dec{S|}",          { RMeSI } },
2304   { "dec{S|}",          { RMeDI } },
2305   /* 50 */
2306   { "pushV",            { RMrAX } },
2307   { "pushV",            { RMrCX } },
2308   { "pushV",            { RMrDX } },
2309   { "pushV",            { RMrBX } },
2310   { "pushV",            { RMrSP } },
2311   { "pushV",            { RMrBP } },
2312   { "pushV",            { RMrSI } },
2313   { "pushV",            { RMrDI } },
2314   /* 58 */
2315   { "popV",             { RMrAX } },
2316   { "popV",             { RMrCX } },
2317   { "popV",             { RMrDX } },
2318   { "popV",             { RMrBX } },
2319   { "popV",             { RMrSP } },
2320   { "popV",             { RMrBP } },
2321   { "popV",             { RMrSI } },
2322   { "popV",             { RMrDI } },
2323   /* 60 */
2324   { X86_64_TABLE (X86_64_60) },
2325   { X86_64_TABLE (X86_64_61) },
2326   { X86_64_TABLE (X86_64_62) },
2327   { X86_64_TABLE (X86_64_63) },
2328   { Bad_Opcode },       /* seg fs */
2329   { Bad_Opcode },       /* seg gs */
2330   { Bad_Opcode },       /* op size prefix */
2331   { Bad_Opcode },       /* adr size prefix */
2332   /* 68 */
2333   { "pushT",            { sIv } },
2334   { "imulS",            { Gv, Ev, Iv } },
2335   { "pushT",            { sIbT } },
2336   { "imulS",            { Gv, Ev, sIb } },
2337   { "ins{b|}",          { Ybr, indirDX } },
2338   { X86_64_TABLE (X86_64_6D) },
2339   { "outs{b|}",         { indirDXr, Xb } },
2340   { X86_64_TABLE (X86_64_6F) },
2341   /* 70 */
2342   { "joH",              { Jb, BND, cond_jump_flag } },
2343   { "jnoH",             { Jb, BND, cond_jump_flag } },
2344   { "jbH",              { Jb, BND, cond_jump_flag } },
2345   { "jaeH",             { Jb, BND, cond_jump_flag } },
2346   { "jeH",              { Jb, BND, cond_jump_flag } },
2347   { "jneH",             { Jb, BND, cond_jump_flag } },
2348   { "jbeH",             { Jb, BND, cond_jump_flag } },
2349   { "jaH",              { Jb, BND, cond_jump_flag } },
2350   /* 78 */
2351   { "jsH",              { Jb, BND, cond_jump_flag } },
2352   { "jnsH",             { Jb, BND, cond_jump_flag } },
2353   { "jpH",              { Jb, BND, cond_jump_flag } },
2354   { "jnpH",             { Jb, BND, cond_jump_flag } },
2355   { "jlH",              { Jb, BND, cond_jump_flag } },
2356   { "jgeH",             { Jb, BND, cond_jump_flag } },
2357   { "jleH",             { Jb, BND, cond_jump_flag } },
2358   { "jgH",              { Jb, BND, cond_jump_flag } },
2359   /* 80 */
2360   { REG_TABLE (REG_80) },
2361   { REG_TABLE (REG_81) },
2362   { Bad_Opcode },
2363   { REG_TABLE (REG_82) },
2364   { "testB",            { Eb, Gb } },
2365   { "testS",            { Ev, Gv } },
2366   { "xchgB",            { Ebh2, Gb } },
2367   { "xchgS",            { Evh2, Gv } },
2368   /* 88 */
2369   { "movB",             { Ebh3, Gb } },
2370   { "movS",             { Evh3, Gv } },
2371   { "movB",             { Gb, EbS } },
2372   { "movS",             { Gv, EvS } },
2373   { "movD",             { Sv, Sw } },
2374   { MOD_TABLE (MOD_8D) },
2375   { "movD",             { Sw, Sv } },
2376   { REG_TABLE (REG_8F) },
2377   /* 90 */
2378   { PREFIX_TABLE (PREFIX_90) },
2379   { "xchgS",            { RMeCX, eAX } },
2380   { "xchgS",            { RMeDX, eAX } },
2381   { "xchgS",            { RMeBX, eAX } },
2382   { "xchgS",            { RMeSP, eAX } },
2383   { "xchgS",            { RMeBP, eAX } },
2384   { "xchgS",            { RMeSI, eAX } },
2385   { "xchgS",            { RMeDI, eAX } },
2386   /* 98 */
2387   { "cW{t|}R",          { XX } },
2388   { "cR{t|}O",          { XX } },
2389   { X86_64_TABLE (X86_64_9A) },
2390   { Bad_Opcode },       /* fwait */
2391   { "pushfT",           { XX } },
2392   { "popfT",            { XX } },
2393   { "sahf",             { XX } },
2394   { "lahf",             { XX } },
2395   /* a0 */
2396   { "mov%LB",           { AL, Ob } },
2397   { "mov%LS",           { eAX, Ov } },
2398   { "mov%LB",           { Ob, AL } },
2399   { "mov%LS",           { Ov, eAX } },
2400   { "movs{b|}",         { Ybr, Xb } },
2401   { "movs{R|}",         { Yvr, Xv } },
2402   { "cmps{b|}",         { Xb, Yb } },
2403   { "cmps{R|}",         { Xv, Yv } },
2404   /* a8 */
2405   { "testB",            { AL, Ib } },
2406   { "testS",            { eAX, Iv } },
2407   { "stosB",            { Ybr, AL } },
2408   { "stosS",            { Yvr, eAX } },
2409   { "lodsB",            { ALr, Xb } },
2410   { "lodsS",            { eAXr, Xv } },
2411   { "scasB",            { AL, Yb } },
2412   { "scasS",            { eAX, Yv } },
2413   /* b0 */
2414   { "movB",             { RMAL, Ib } },
2415   { "movB",             { RMCL, Ib } },
2416   { "movB",             { RMDL, Ib } },
2417   { "movB",             { RMBL, Ib } },
2418   { "movB",             { RMAH, Ib } },
2419   { "movB",             { RMCH, Ib } },
2420   { "movB",             { RMDH, Ib } },
2421   { "movB",             { RMBH, Ib } },
2422   /* b8 */
2423   { "mov%LV",           { RMeAX, Iv64 } },
2424   { "mov%LV",           { RMeCX, Iv64 } },
2425   { "mov%LV",           { RMeDX, Iv64 } },
2426   { "mov%LV",           { RMeBX, Iv64 } },
2427   { "mov%LV",           { RMeSP, Iv64 } },
2428   { "mov%LV",           { RMeBP, Iv64 } },
2429   { "mov%LV",           { RMeSI, Iv64 } },
2430   { "mov%LV",           { RMeDI, Iv64 } },
2431   /* c0 */
2432   { REG_TABLE (REG_C0) },
2433   { REG_TABLE (REG_C1) },
2434   { "retT",             { Iw, BND } },
2435   { "retT",             { BND } },
2436   { X86_64_TABLE (X86_64_C4) },
2437   { X86_64_TABLE (X86_64_C5) },
2438   { REG_TABLE (REG_C6) },
2439   { REG_TABLE (REG_C7) },
2440   /* c8 */
2441   { "enterT",           { Iw, Ib } },
2442   { "leaveT",           { XX } },
2443   { "Jret{|f}P",        { Iw } },
2444   { "Jret{|f}P",        { XX } },
2445   { "int3",             { XX } },
2446   { "int",              { Ib } },
2447   { X86_64_TABLE (X86_64_CE) },
2448   { "iretP",            { XX } },
2449   /* d0 */
2450   { REG_TABLE (REG_D0) },
2451   { REG_TABLE (REG_D1) },
2452   { REG_TABLE (REG_D2) },
2453   { REG_TABLE (REG_D3) },
2454   { X86_64_TABLE (X86_64_D4) },
2455   { X86_64_TABLE (X86_64_D5) },
2456   { Bad_Opcode },
2457   { "xlat",             { DSBX } },
2458   /* d8 */
2459   { FLOAT },
2460   { FLOAT },
2461   { FLOAT },
2462   { FLOAT },
2463   { FLOAT },
2464   { FLOAT },
2465   { FLOAT },
2466   { FLOAT },
2467   /* e0 */
2468   { "loopneFH",         { Jb, XX, loop_jcxz_flag } },
2469   { "loopeFH",          { Jb, XX, loop_jcxz_flag } },
2470   { "loopFH",           { Jb, XX, loop_jcxz_flag } },
2471   { "jEcxzH",           { Jb, XX, loop_jcxz_flag } },
2472   { "inB",              { AL, Ib } },
2473   { "inG",              { zAX, Ib } },
2474   { "outB",             { Ib, AL } },
2475   { "outG",             { Ib, zAX } },
2476   /* e8 */
2477   { "callT",            { Jv, BND } },
2478   { "jmpT",             { Jv, BND } },
2479   { X86_64_TABLE (X86_64_EA) },
2480   { "jmp",              { Jb, BND } },
2481   { "inB",              { AL, indirDX } },
2482   { "inG",              { zAX, indirDX } },
2483   { "outB",             { indirDX, AL } },
2484   { "outG",             { indirDX, zAX } },
2485   /* f0 */
2486   { Bad_Opcode },       /* lock prefix */
2487   { "icebp",            { XX } },
2488   { Bad_Opcode },       /* repne */
2489   { Bad_Opcode },       /* repz */
2490   { "hlt",              { XX } },
2491   { "cmc",              { XX } },
2492   { REG_TABLE (REG_F6) },
2493   { REG_TABLE (REG_F7) },
2494   /* f8 */
2495   { "clc",              { XX } },
2496   { "stc",              { XX } },
2497   { "cli",              { XX } },
2498   { "sti",              { XX } },
2499   { "cld",              { XX } },
2500   { "std",              { XX } },
2501   { REG_TABLE (REG_FE) },
2502   { REG_TABLE (REG_FF) },
2503 };
2504
2505 static const struct dis386 dis386_twobyte[] = {
2506   /* 00 */
2507   { REG_TABLE (REG_0F00 ) },
2508   { REG_TABLE (REG_0F01 ) },
2509   { "larS",             { Gv, Ew } },
2510   { "lslS",             { Gv, Ew } },
2511   { Bad_Opcode },
2512   { "syscall",          { XX } },
2513   { "clts",             { XX } },
2514   { "sysretP",          { XX } },
2515   /* 08 */
2516   { "invd",             { XX } },
2517   { "wbinvd",           { XX } },
2518   { Bad_Opcode },
2519   { "ud2",              { XX } },
2520   { Bad_Opcode },
2521   { REG_TABLE (REG_0F0D) },
2522   { "femms",            { XX } },
2523   { "",                 { MX, EM, OPSUF } }, /* See OP_3DNowSuffix.  */
2524   /* 10 */
2525   { PREFIX_TABLE (PREFIX_0F10) },
2526   { PREFIX_TABLE (PREFIX_0F11) },
2527   { PREFIX_TABLE (PREFIX_0F12) },
2528   { MOD_TABLE (MOD_0F13) },
2529   { "unpcklpX",         { XM, EXx } },
2530   { "unpckhpX",         { XM, EXx } },
2531   { PREFIX_TABLE (PREFIX_0F16) },
2532   { MOD_TABLE (MOD_0F17) },
2533   /* 18 */
2534   { REG_TABLE (REG_0F18) },
2535   { "nopQ",             { Ev } },
2536   { PREFIX_TABLE (PREFIX_0F1A) },
2537   { PREFIX_TABLE (PREFIX_0F1B) },
2538   { "nopQ",             { Ev } },
2539   { "nopQ",             { Ev } },
2540   { "nopQ",             { Ev } },
2541   { "nopQ",             { Ev } },
2542   /* 20 */
2543   { MOD_TABLE (MOD_0F20) },
2544   { MOD_TABLE (MOD_0F21) },
2545   { MOD_TABLE (MOD_0F22) },
2546   { MOD_TABLE (MOD_0F23) },
2547   { MOD_TABLE (MOD_0F24) },
2548   { Bad_Opcode },
2549   { MOD_TABLE (MOD_0F26) },
2550   { Bad_Opcode },
2551   /* 28 */
2552   { "movapX",           { XM, EXx } },
2553   { "movapX",           { EXxS, XM } },
2554   { PREFIX_TABLE (PREFIX_0F2A) },
2555   { PREFIX_TABLE (PREFIX_0F2B) },
2556   { PREFIX_TABLE (PREFIX_0F2C) },
2557   { PREFIX_TABLE (PREFIX_0F2D) },
2558   { PREFIX_TABLE (PREFIX_0F2E) },
2559   { PREFIX_TABLE (PREFIX_0F2F) },
2560   /* 30 */
2561   { "wrmsr",            { XX } },
2562   { "rdtsc",            { XX } },
2563   { "rdmsr",            { XX } },
2564   { "rdpmc",            { XX } },
2565   { "sysenter",         { XX } },
2566   { "sysexit",          { XX } },
2567   { Bad_Opcode },
2568   { "getsec",           { XX } },
2569   /* 38 */
2570   { THREE_BYTE_TABLE (THREE_BYTE_0F38) },
2571   { Bad_Opcode },
2572   { THREE_BYTE_TABLE (THREE_BYTE_0F3A) },
2573   { Bad_Opcode },
2574   { Bad_Opcode },
2575   { Bad_Opcode },
2576   { Bad_Opcode },
2577   { Bad_Opcode },
2578   /* 40 */
2579   { "cmovoS",           { Gv, Ev } },
2580   { "cmovnoS",          { Gv, Ev } },
2581   { "cmovbS",           { Gv, Ev } },
2582   { "cmovaeS",          { Gv, Ev } },
2583   { "cmoveS",           { Gv, Ev } },
2584   { "cmovneS",          { Gv, Ev } },
2585   { "cmovbeS",          { Gv, Ev } },
2586   { "cmovaS",           { Gv, Ev } },
2587   /* 48 */
2588   { "cmovsS",           { Gv, Ev } },
2589   { "cmovnsS",          { Gv, Ev } },
2590   { "cmovpS",           { Gv, Ev } },
2591   { "cmovnpS",          { Gv, Ev } },
2592   { "cmovlS",           { Gv, Ev } },
2593   { "cmovgeS",          { Gv, Ev } },
2594   { "cmovleS",          { Gv, Ev } },
2595   { "cmovgS",           { Gv, Ev } },
2596   /* 50 */
2597   { MOD_TABLE (MOD_0F51) },
2598   { PREFIX_TABLE (PREFIX_0F51) },
2599   { PREFIX_TABLE (PREFIX_0F52) },
2600   { PREFIX_TABLE (PREFIX_0F53) },
2601   { "andpX",            { XM, EXx } },
2602   { "andnpX",           { XM, EXx } },
2603   { "orpX",             { XM, EXx } },
2604   { "xorpX",            { XM, EXx } },
2605   /* 58 */
2606   { PREFIX_TABLE (PREFIX_0F58) },
2607   { PREFIX_TABLE (PREFIX_0F59) },
2608   { PREFIX_TABLE (PREFIX_0F5A) },
2609   { PREFIX_TABLE (PREFIX_0F5B) },
2610   { PREFIX_TABLE (PREFIX_0F5C) },
2611   { PREFIX_TABLE (PREFIX_0F5D) },
2612   { PREFIX_TABLE (PREFIX_0F5E) },
2613   { PREFIX_TABLE (PREFIX_0F5F) },
2614   /* 60 */
2615   { PREFIX_TABLE (PREFIX_0F60) },
2616   { PREFIX_TABLE (PREFIX_0F61) },
2617   { PREFIX_TABLE (PREFIX_0F62) },
2618   { "packsswb",         { MX, EM } },
2619   { "pcmpgtb",          { MX, EM } },
2620   { "pcmpgtw",          { MX, EM } },
2621   { "pcmpgtd",          { MX, EM } },
2622   { "packuswb",         { MX, EM } },
2623   /* 68 */
2624   { "punpckhbw",        { MX, EM } },
2625   { "punpckhwd",        { MX, EM } },
2626   { "punpckhdq",        { MX, EM } },
2627   { "packssdw",         { MX, EM } },
2628   { PREFIX_TABLE (PREFIX_0F6C) },
2629   { PREFIX_TABLE (PREFIX_0F6D) },
2630   { "movK",             { MX, Edq } },
2631   { PREFIX_TABLE (PREFIX_0F6F) },
2632   /* 70 */
2633   { PREFIX_TABLE (PREFIX_0F70) },
2634   { REG_TABLE (REG_0F71) },
2635   { REG_TABLE (REG_0F72) },
2636   { REG_TABLE (REG_0F73) },
2637   { "pcmpeqb",          { MX, EM } },
2638   { "pcmpeqw",          { MX, EM } },
2639   { "pcmpeqd",          { MX, EM } },
2640   { "emms",             { XX } },
2641   /* 78 */
2642   { PREFIX_TABLE (PREFIX_0F78) },
2643   { PREFIX_TABLE (PREFIX_0F79) },
2644   { THREE_BYTE_TABLE (THREE_BYTE_0F7A) },
2645   { Bad_Opcode },
2646   { PREFIX_TABLE (PREFIX_0F7C) },
2647   { PREFIX_TABLE (PREFIX_0F7D) },
2648   { PREFIX_TABLE (PREFIX_0F7E) },
2649   { PREFIX_TABLE (PREFIX_0F7F) },
2650   /* 80 */
2651   { "joH",              { Jv, BND, cond_jump_flag } },
2652   { "jnoH",             { Jv, BND, cond_jump_flag } },
2653   { "jbH",              { Jv, BND, cond_jump_flag } },
2654   { "jaeH",             { Jv, BND, cond_jump_flag } },
2655   { "jeH",              { Jv, BND, cond_jump_flag } },
2656   { "jneH",             { Jv, BND, cond_jump_flag } },
2657   { "jbeH",             { Jv, BND, cond_jump_flag } },
2658   { "jaH",              { Jv, BND, cond_jump_flag } },
2659   /* 88 */
2660   { "jsH",              { Jv, BND, cond_jump_flag } },
2661   { "jnsH",             { Jv, BND, cond_jump_flag } },
2662   { "jpH",              { Jv, BND, cond_jump_flag } },
2663   { "jnpH",             { Jv, BND, cond_jump_flag } },
2664   { "jlH",              { Jv, BND, cond_jump_flag } },
2665   { "jgeH",             { Jv, BND, cond_jump_flag } },
2666   { "jleH",             { Jv, BND, cond_jump_flag } },
2667   { "jgH",              { Jv, BND, cond_jump_flag } },
2668   /* 90 */
2669   { "seto",             { Eb } },
2670   { "setno",            { Eb } },
2671   { "setb",             { Eb } },
2672   { "setae",            { Eb } },
2673   { "sete",             { Eb } },
2674   { "setne",            { Eb } },
2675   { "setbe",            { Eb } },
2676   { "seta",             { Eb } },
2677   /* 98 */
2678   { "sets",             { Eb } },
2679   { "setns",            { Eb } },
2680   { "setp",             { Eb } },
2681   { "setnp",            { Eb } },
2682   { "setl",             { Eb } },
2683   { "setge",            { Eb } },
2684   { "setle",            { Eb } },
2685   { "setg",             { Eb } },
2686   /* a0 */
2687   { "pushT",            { fs } },
2688   { "popT",             { fs } },
2689   { "cpuid",            { XX } },
2690   { "btS",              { Ev, Gv } },
2691   { "shldS",            { Ev, Gv, Ib } },
2692   { "shldS",            { Ev, Gv, CL } },
2693   { REG_TABLE (REG_0FA6) },
2694   { REG_TABLE (REG_0FA7) },
2695   /* a8 */
2696   { "pushT",            { gs } },
2697   { "popT",             { gs } },
2698   { "rsm",              { XX } },
2699   { "btsS",             { Evh1, Gv } },
2700   { "shrdS",            { Ev, Gv, Ib } },
2701   { "shrdS",            { Ev, Gv, CL } },
2702   { REG_TABLE (REG_0FAE) },
2703   { "imulS",            { Gv, Ev } },
2704   /* b0 */
2705   { "cmpxchgB",         { Ebh1, Gb } },
2706   { "cmpxchgS",         { Evh1, Gv } },
2707   { MOD_TABLE (MOD_0FB2) },
2708   { "btrS",             { Evh1, Gv } },
2709   { MOD_TABLE (MOD_0FB4) },
2710   { MOD_TABLE (MOD_0FB5) },
2711   { "movz{bR|x}",       { Gv, Eb } },
2712   { "movz{wR|x}",       { Gv, Ew } }, /* yes, there really is movzww ! */
2713   /* b8 */
2714   { PREFIX_TABLE (PREFIX_0FB8) },
2715   { "ud1",              { XX } },
2716   { REG_TABLE (REG_0FBA) },
2717   { "btcS",             { Evh1, Gv } },
2718   { PREFIX_TABLE (PREFIX_0FBC) },
2719   { PREFIX_TABLE (PREFIX_0FBD) },
2720   { "movs{bR|x}",       { Gv, Eb } },
2721   { "movs{wR|x}",       { Gv, Ew } }, /* yes, there really is movsww ! */
2722   /* c0 */
2723   { "xaddB",            { Ebh1, Gb } },
2724   { "xaddS",            { Evh1, Gv } },
2725   { PREFIX_TABLE (PREFIX_0FC2) },
2726   { PREFIX_TABLE (PREFIX_0FC3) },
2727   { "pinsrw",           { MX, Edqw, Ib } },
2728   { "pextrw",           { Gdq, MS, Ib } },
2729   { "shufpX",           { XM, EXx, Ib } },
2730   { REG_TABLE (REG_0FC7) },
2731   /* c8 */
2732   { "bswap",            { RMeAX } },
2733   { "bswap",            { RMeCX } },
2734   { "bswap",            { RMeDX } },
2735   { "bswap",            { RMeBX } },
2736   { "bswap",            { RMeSP } },
2737   { "bswap",            { RMeBP } },
2738   { "bswap",            { RMeSI } },
2739   { "bswap",            { RMeDI } },
2740   /* d0 */
2741   { PREFIX_TABLE (PREFIX_0FD0) },
2742   { "psrlw",            { MX, EM } },
2743   { "psrld",            { MX, EM } },
2744   { "psrlq",            { MX, EM } },
2745   { "paddq",            { MX, EM } },
2746   { "pmullw",           { MX, EM } },
2747   { PREFIX_TABLE (PREFIX_0FD6) },
2748   { MOD_TABLE (MOD_0FD7) },
2749   /* d8 */
2750   { "psubusb",          { MX, EM } },
2751   { "psubusw",          { MX, EM } },
2752   { "pminub",           { MX, EM } },
2753   { "pand",             { MX, EM } },
2754   { "paddusb",          { MX, EM } },
2755   { "paddusw",          { MX, EM } },
2756   { "pmaxub",           { MX, EM } },
2757   { "pandn",            { MX, EM } },
2758   /* e0 */
2759   { "pavgb",            { MX, EM } },
2760   { "psraw",            { MX, EM } },
2761   { "psrad",            { MX, EM } },
2762   { "pavgw",            { MX, EM } },
2763   { "pmulhuw",          { MX, EM } },
2764   { "pmulhw",           { MX, EM } },
2765   { PREFIX_TABLE (PREFIX_0FE6) },
2766   { PREFIX_TABLE (PREFIX_0FE7) },
2767   /* e8 */
2768   { "psubsb",           { MX, EM } },
2769   { "psubsw",           { MX, EM } },
2770   { "pminsw",           { MX, EM } },
2771   { "por",              { MX, EM } },
2772   { "paddsb",           { MX, EM } },
2773   { "paddsw",           { MX, EM } },
2774   { "pmaxsw",           { MX, EM } },
2775   { "pxor",             { MX, EM } },
2776   /* f0 */
2777   { PREFIX_TABLE (PREFIX_0FF0) },
2778   { "psllw",            { MX, EM } },
2779   { "pslld",            { MX, EM } },
2780   { "psllq",            { MX, EM } },
2781   { "pmuludq",          { MX, EM } },
2782   { "pmaddwd",          { MX, EM } },
2783   { "psadbw",           { MX, EM } },
2784   { PREFIX_TABLE (PREFIX_0FF7) },
2785   /* f8 */
2786   { "psubb",            { MX, EM } },
2787   { "psubw",            { MX, EM } },
2788   { "psubd",            { MX, EM } },
2789   { "psubq",            { MX, EM } },
2790   { "paddb",            { MX, EM } },
2791   { "paddw",            { MX, EM } },
2792   { "paddd",            { MX, EM } },
2793   { Bad_Opcode },
2794 };
2795
2796 static const unsigned char onebyte_has_modrm[256] = {
2797   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2798   /*       -------------------------------        */
2799   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2800   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2801   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2802   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2803   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2804   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2805   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2806   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2807   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2808   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2809   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2810   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2811   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2812   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2813   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2814   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
2815   /*       -------------------------------        */
2816   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2817 };
2818
2819 static const unsigned char twobyte_has_modrm[256] = {
2820   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2821   /*       -------------------------------        */
2822   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2823   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2824   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2825   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2826   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2827   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2828   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2829   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2830   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2831   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2832   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2833   /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
2834   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2835   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2836   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2837   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0  /* ff */
2838   /*       -------------------------------        */
2839   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2840 };
2841
2842 static char obuf[100];
2843 static char *obufp;
2844 static char *mnemonicendp;
2845 static char scratchbuf[100];
2846 static unsigned char *start_codep;
2847 static unsigned char *insn_codep;
2848 static unsigned char *codep;
2849 static int last_lock_prefix;
2850 static int last_repz_prefix;
2851 static int last_repnz_prefix;
2852 static int last_data_prefix;
2853 static int last_addr_prefix;
2854 static int last_rex_prefix;
2855 static int last_seg_prefix;
2856 #define MAX_CODE_LENGTH 15
2857 /* We can up to 14 prefixes since the maximum instruction length is
2858    15bytes.  */
2859 static int all_prefixes[MAX_CODE_LENGTH - 1];
2860 static disassemble_info *the_info;
2861 static struct
2862   {
2863     int mod;
2864     int reg;
2865     int rm;
2866   }
2867 modrm;
2868 static unsigned char need_modrm;
2869 static struct
2870   {
2871     int scale;
2872     int index;
2873     int base;
2874   }
2875 sib;
2876 static struct
2877   {
2878     int register_specifier;
2879     int length;
2880     int prefix;
2881     int w;
2882     int evex;
2883     int r;
2884     int v;
2885     int mask_register_specifier;
2886     int zeroing;
2887     int ll;
2888     int b;
2889   }
2890 vex;
2891 static unsigned char need_vex;
2892 static unsigned char need_vex_reg;
2893 static unsigned char vex_w_done;
2894
2895 struct op
2896   {
2897     const char *name;
2898     unsigned int len;
2899   };
2900
2901 /* If we are accessing mod/rm/reg without need_modrm set, then the
2902    values are stale.  Hitting this abort likely indicates that you
2903    need to update onebyte_has_modrm or twobyte_has_modrm.  */
2904 #define MODRM_CHECK  if (!need_modrm) abort ()
2905
2906 static const char **names64;
2907 static const char **names32;
2908 static const char **names16;
2909 static const char **names8;
2910 static const char **names8rex;
2911 static const char **names_seg;
2912 static const char *index64;
2913 static const char *index32;
2914 static const char **index16;
2915 static const char **names_bnd;
2916
2917 static const char *intel_names64[] = {
2918   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2919   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2920 };
2921 static const char *intel_names32[] = {
2922   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
2923   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
2924 };
2925 static const char *intel_names16[] = {
2926   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
2927   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
2928 };
2929 static const char *intel_names8[] = {
2930   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2931 };
2932 static const char *intel_names8rex[] = {
2933   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2934   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2935 };
2936 static const char *intel_names_seg[] = {
2937   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2938 };
2939 static const char *intel_index64 = "riz";
2940 static const char *intel_index32 = "eiz";
2941 static const char *intel_index16[] = {
2942   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2943 };
2944
2945 static const char *att_names64[] = {
2946   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2947   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2948 };
2949 static const char *att_names32[] = {
2950   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2951   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2952 };
2953 static const char *att_names16[] = {
2954   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2955   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2956 };
2957 static const char *att_names8[] = {
2958   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2959 };
2960 static const char *att_names8rex[] = {
2961   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2962   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2963 };
2964 static const char *att_names_seg[] = {
2965   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2966 };
2967 static const char *att_index64 = "%riz";
2968 static const char *att_index32 = "%eiz";
2969 static const char *att_index16[] = {
2970   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2971 };
2972
2973 static const char **names_mm;
2974 static const char *intel_names_mm[] = {
2975   "mm0", "mm1", "mm2", "mm3",
2976   "mm4", "mm5", "mm6", "mm7"
2977 };
2978 static const char *att_names_mm[] = {
2979   "%mm0", "%mm1", "%mm2", "%mm3",
2980   "%mm4", "%mm5", "%mm6", "%mm7"
2981 };
2982
2983 static const char *intel_names_bnd[] = {
2984   "bnd0", "bnd1", "bnd2", "bnd3"
2985 };
2986
2987 static const char *att_names_bnd[] = {
2988   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
2989 };
2990
2991 static const char **names_xmm;
2992 static const char *intel_names_xmm[] = {
2993   "xmm0", "xmm1", "xmm2", "xmm3",
2994   "xmm4", "xmm5", "xmm6", "xmm7",
2995   "xmm8", "xmm9", "xmm10", "xmm11",
2996   "xmm12", "xmm13", "xmm14", "xmm15",
2997   "xmm16", "xmm17", "xmm18", "xmm19",
2998   "xmm20", "xmm21", "xmm22", "xmm23",
2999   "xmm24", "xmm25", "xmm26", "xmm27",
3000   "xmm28", "xmm29", "xmm30", "xmm31"
3001 };
3002 static const char *att_names_xmm[] = {
3003   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3004   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3005   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3006   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3007   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3008   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3009   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3010   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3011 };
3012
3013 static const char **names_ymm;
3014 static const char *intel_names_ymm[] = {
3015   "ymm0", "ymm1", "ymm2", "ymm3",
3016   "ymm4", "ymm5", "ymm6", "ymm7",
3017   "ymm8", "ymm9", "ymm10", "ymm11",
3018   "ymm12", "ymm13", "ymm14", "ymm15",
3019   "ymm16", "ymm17", "ymm18", "ymm19",
3020   "ymm20", "ymm21", "ymm22", "ymm23",
3021   "ymm24", "ymm25", "ymm26", "ymm27",
3022   "ymm28", "ymm29", "ymm30", "ymm31"
3023 };
3024 static const char *att_names_ymm[] = {
3025   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3026   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3027   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3028   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3029   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3030   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3031   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3032   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3033 };
3034
3035 static const char **names_zmm;
3036 static const char *intel_names_zmm[] = {
3037   "zmm0", "zmm1", "zmm2", "zmm3",
3038   "zmm4", "zmm5", "zmm6", "zmm7",
3039   "zmm8", "zmm9", "zmm10", "zmm11",
3040   "zmm12", "zmm13", "zmm14", "zmm15",
3041   "zmm16", "zmm17", "zmm18", "zmm19",
3042   "zmm20", "zmm21", "zmm22", "zmm23",
3043   "zmm24", "zmm25", "zmm26", "zmm27",
3044   "zmm28", "zmm29", "zmm30", "zmm31"
3045 };
3046 static const char *att_names_zmm[] = {
3047   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3048   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3049   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3050   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3051   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3052   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3053   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3054   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3055 };
3056
3057 static const char **names_mask;
3058 static const char *intel_names_mask[] = {
3059   "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3060 };
3061 static const char *att_names_mask[] = {
3062   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3063 };
3064
3065 static const char *names_rounding[] =
3066 {
3067   "{rn-sae}",
3068   "{rd-sae}",
3069   "{ru-sae}",
3070   "{rz-sae}"
3071 };
3072
3073 static const struct dis386 reg_table[][8] = {
3074   /* REG_80 */
3075   {
3076     { "addA",   { Ebh1, Ib } },
3077     { "orA",    { Ebh1, Ib } },
3078     { "adcA",   { Ebh1, Ib } },
3079     { "sbbA",   { Ebh1, Ib } },
3080     { "andA",   { Ebh1, Ib } },
3081     { "subA",   { Ebh1, Ib } },
3082     { "xorA",   { Ebh1, Ib } },
3083     { "cmpA",   { Eb, Ib } },
3084   },
3085   /* REG_81 */
3086   {
3087     { "addQ",   { Evh1, Iv } },
3088     { "orQ",    { Evh1, Iv } },
3089     { "adcQ",   { Evh1, Iv } },
3090     { "sbbQ",   { Evh1, Iv } },
3091     { "andQ",   { Evh1, Iv } },
3092     { "subQ",   { Evh1, Iv } },
3093     { "xorQ",   { Evh1, Iv } },
3094     { "cmpQ",   { Ev, Iv } },
3095   },
3096   /* REG_82 */
3097   {
3098     { "addQ",   { Evh1, sIb } },
3099     { "orQ",    { Evh1, sIb } },
3100     { "adcQ",   { Evh1, sIb } },
3101     { "sbbQ",   { Evh1, sIb } },
3102     { "andQ",   { Evh1, sIb } },
3103     { "subQ",   { Evh1, sIb } },
3104     { "xorQ",   { Evh1, sIb } },
3105     { "cmpQ",   { Ev, sIb } },
3106   },
3107   /* REG_8F */
3108   {
3109     { "popU",   { stackEv } },
3110     { XOP_8F_TABLE (XOP_09) },
3111     { Bad_Opcode },
3112     { Bad_Opcode },
3113     { Bad_Opcode },
3114     { XOP_8F_TABLE (XOP_09) },
3115   },
3116   /* REG_C0 */
3117   {
3118     { "rolA",   { Eb, Ib } },
3119     { "rorA",   { Eb, Ib } },
3120     { "rclA",   { Eb, Ib } },
3121     { "rcrA",   { Eb, Ib } },
3122     { "shlA",   { Eb, Ib } },
3123     { "shrA",   { Eb, Ib } },
3124     { Bad_Opcode },
3125     { "sarA",   { Eb, Ib } },
3126   },
3127   /* REG_C1 */
3128   {
3129     { "rolQ",   { Ev, Ib } },
3130     { "rorQ",   { Ev, Ib } },
3131     { "rclQ",   { Ev, Ib } },
3132     { "rcrQ",   { Ev, Ib } },
3133     { "shlQ",   { Ev, Ib } },
3134     { "shrQ",   { Ev, Ib } },
3135     { Bad_Opcode },
3136     { "sarQ",   { Ev, Ib } },
3137   },
3138   /* REG_C6 */
3139   {
3140     { "movA",   { Ebh3, Ib } },
3141     { Bad_Opcode },
3142     { Bad_Opcode },
3143     { Bad_Opcode },
3144     { Bad_Opcode },
3145     { Bad_Opcode },
3146     { Bad_Opcode },
3147     { MOD_TABLE (MOD_C6_REG_7) },
3148   },
3149   /* REG_C7 */
3150   {
3151     { "movQ",   { Evh3, Iv } },
3152     { Bad_Opcode },
3153     { Bad_Opcode },
3154     { Bad_Opcode },
3155     { Bad_Opcode },
3156     { Bad_Opcode },
3157     { Bad_Opcode },
3158     { MOD_TABLE (MOD_C7_REG_7) },
3159   },
3160   /* REG_D0 */
3161   {
3162     { "rolA",   { Eb, I1 } },
3163     { "rorA",   { Eb, I1 } },
3164     { "rclA",   { Eb, I1 } },
3165     { "rcrA",   { Eb, I1 } },
3166     { "shlA",   { Eb, I1 } },
3167     { "shrA",   { Eb, I1 } },
3168     { Bad_Opcode },
3169     { "sarA",   { Eb, I1 } },
3170   },
3171   /* REG_D1 */
3172   {
3173     { "rolQ",   { Ev, I1 } },
3174     { "rorQ",   { Ev, I1 } },
3175     { "rclQ",   { Ev, I1 } },
3176     { "rcrQ",   { Ev, I1 } },
3177     { "shlQ",   { Ev, I1 } },
3178     { "shrQ",   { Ev, I1 } },
3179     { Bad_Opcode },
3180     { "sarQ",   { Ev, I1 } },
3181   },
3182   /* REG_D2 */
3183   {
3184     { "rolA",   { Eb, CL } },
3185     { "rorA",   { Eb, CL } },
3186     { "rclA",   { Eb, CL } },
3187     { "rcrA",   { Eb, CL } },
3188     { "shlA",   { Eb, CL } },
3189     { "shrA",   { Eb, CL } },
3190     { Bad_Opcode },
3191     { "sarA",   { Eb, CL } },
3192   },
3193   /* REG_D3 */
3194   {
3195     { "rolQ",   { Ev, CL } },
3196     { "rorQ",   { Ev, CL } },
3197     { "rclQ",   { Ev, CL } },
3198     { "rcrQ",   { Ev, CL } },
3199     { "shlQ",   { Ev, CL } },
3200     { "shrQ",   { Ev, CL } },
3201     { Bad_Opcode },
3202     { "sarQ",   { Ev, CL } },
3203   },
3204   /* REG_F6 */
3205   {
3206     { "testA",  { Eb, Ib } },
3207     { Bad_Opcode },
3208     { "notA",   { Ebh1 } },
3209     { "negA",   { Ebh1 } },
3210     { "mulA",   { Eb } },       /* Don't print the implicit %al register,  */
3211     { "imulA",  { Eb } },       /* to distinguish these opcodes from other */
3212     { "divA",   { Eb } },       /* mul/imul opcodes.  Do the same for div  */
3213     { "idivA",  { Eb } },       /* and idiv for consistency.               */
3214   },
3215   /* REG_F7 */
3216   {
3217     { "testQ",  { Ev, Iv } },
3218     { Bad_Opcode },
3219     { "notQ",   { Evh1 } },
3220     { "negQ",   { Evh1 } },
3221     { "mulQ",   { Ev } },       /* Don't print the implicit register.  */
3222     { "imulQ",  { Ev } },
3223     { "divQ",   { Ev } },
3224     { "idivQ",  { Ev } },
3225   },
3226   /* REG_FE */
3227   {
3228     { "incA",   { Ebh1 } },
3229     { "decA",   { Ebh1 } },
3230   },
3231   /* REG_FF */
3232   {
3233     { "incQ",   { Evh1 } },
3234     { "decQ",   { Evh1 } },
3235     { "call{T|}", { indirEv, BND } },
3236     { MOD_TABLE (MOD_FF_REG_3) },
3237     { "jmp{T|}", { indirEv, BND } },
3238     { MOD_TABLE (MOD_FF_REG_5) },
3239     { "pushU",  { stackEv } },
3240     { Bad_Opcode },
3241   },
3242   /* REG_0F00 */
3243   {
3244     { "sldtD",  { Sv } },
3245     { "strD",   { Sv } },
3246     { "lldt",   { Ew } },
3247     { "ltr",    { Ew } },
3248     { "verr",   { Ew } },
3249     { "verw",   { Ew } },
3250     { Bad_Opcode },
3251     { Bad_Opcode },
3252   },
3253   /* REG_0F01 */
3254   {
3255     { MOD_TABLE (MOD_0F01_REG_0) },
3256     { MOD_TABLE (MOD_0F01_REG_1) },
3257     { MOD_TABLE (MOD_0F01_REG_2) },
3258     { MOD_TABLE (MOD_0F01_REG_3) },
3259     { "smswD",  { Sv } },
3260     { Bad_Opcode },
3261     { "lmsw",   { Ew } },
3262     { MOD_TABLE (MOD_0F01_REG_7) },
3263   },
3264   /* REG_0F0D */
3265   {
3266     { "prefetch",       { Mb } },
3267     { "prefetchw",      { Mb } },
3268     { "prefetchwt1",    { Mb } },
3269     { "prefetch",       { Mb } },
3270     { "prefetch",       { Mb } },
3271     { "prefetch",       { Mb } },
3272     { "prefetch",       { Mb } },
3273     { "prefetch",       { Mb } },
3274   },
3275   /* REG_0F18 */
3276   {
3277     { MOD_TABLE (MOD_0F18_REG_0) },
3278     { MOD_TABLE (MOD_0F18_REG_1) },
3279     { MOD_TABLE (MOD_0F18_REG_2) },
3280     { MOD_TABLE (MOD_0F18_REG_3) },
3281     { MOD_TABLE (MOD_0F18_REG_4) },
3282     { MOD_TABLE (MOD_0F18_REG_5) },
3283     { MOD_TABLE (MOD_0F18_REG_6) },
3284     { MOD_TABLE (MOD_0F18_REG_7) },
3285   },
3286   /* REG_0F71 */
3287   {
3288     { Bad_Opcode },
3289     { Bad_Opcode },
3290     { MOD_TABLE (MOD_0F71_REG_2) },
3291     { Bad_Opcode },
3292     { MOD_TABLE (MOD_0F71_REG_4) },
3293     { Bad_Opcode },
3294     { MOD_TABLE (MOD_0F71_REG_6) },
3295   },
3296   /* REG_0F72 */
3297   {
3298     { Bad_Opcode },
3299     { Bad_Opcode },
3300     { MOD_TABLE (MOD_0F72_REG_2) },
3301     { Bad_Opcode },
3302     { MOD_TABLE (MOD_0F72_REG_4) },
3303     { Bad_Opcode },
3304     { MOD_TABLE (MOD_0F72_REG_6) },
3305   },
3306   /* REG_0F73 */
3307   {
3308     { Bad_Opcode },
3309     { Bad_Opcode },
3310     { MOD_TABLE (MOD_0F73_REG_2) },
3311     { MOD_TABLE (MOD_0F73_REG_3) },
3312     { Bad_Opcode },
3313     { Bad_Opcode },
3314     { MOD_TABLE (MOD_0F73_REG_6) },
3315     { MOD_TABLE (MOD_0F73_REG_7) },
3316   },
3317   /* REG_0FA6 */
3318   {
3319     { "montmul",        { { OP_0f07, 0 } } },
3320     { "xsha1",          { { OP_0f07, 0 } } },
3321     { "xsha256",        { { OP_0f07, 0 } } },
3322   },
3323   /* REG_0FA7 */
3324   {
3325     { "xstore-rng",     { { OP_0f07, 0 } } },
3326     { "xcrypt-ecb",     { { OP_0f07, 0 } } },
3327     { "xcrypt-cbc",     { { OP_0f07, 0 } } },
3328     { "xcrypt-ctr",     { { OP_0f07, 0 } } },
3329     { "xcrypt-cfb",     { { OP_0f07, 0 } } },
3330     { "xcrypt-ofb",     { { OP_0f07, 0 } } },
3331   },
3332   /* REG_0FAE */
3333   {
3334     { MOD_TABLE (MOD_0FAE_REG_0) },
3335     { MOD_TABLE (MOD_0FAE_REG_1) },
3336     { MOD_TABLE (MOD_0FAE_REG_2) },
3337     { MOD_TABLE (MOD_0FAE_REG_3) },
3338     { MOD_TABLE (MOD_0FAE_REG_4) },
3339     { MOD_TABLE (MOD_0FAE_REG_5) },
3340     { MOD_TABLE (MOD_0FAE_REG_6) },
3341     { MOD_TABLE (MOD_0FAE_REG_7) },
3342   },
3343   /* REG_0FBA */
3344   {
3345     { Bad_Opcode },
3346     { Bad_Opcode },
3347     { Bad_Opcode },
3348     { Bad_Opcode },
3349     { "btQ",    { Ev, Ib } },
3350     { "btsQ",   { Evh1, Ib } },
3351     { "btrQ",   { Evh1, Ib } },
3352     { "btcQ",   { Evh1, Ib } },
3353   },
3354   /* REG_0FC7 */
3355   {
3356     { Bad_Opcode },
3357     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } },
3358     { Bad_Opcode },
3359     { MOD_TABLE (MOD_0FC7_REG_3) },
3360     { MOD_TABLE (MOD_0FC7_REG_4) },
3361     { MOD_TABLE (MOD_0FC7_REG_5) },
3362     { MOD_TABLE (MOD_0FC7_REG_6) },
3363     { MOD_TABLE (MOD_0FC7_REG_7) },
3364   },
3365   /* REG_VEX_0F71 */
3366   {
3367     { Bad_Opcode },
3368     { Bad_Opcode },
3369     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3370     { Bad_Opcode },
3371     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3372     { Bad_Opcode },
3373     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3374   },
3375   /* REG_VEX_0F72 */
3376   {
3377     { Bad_Opcode },
3378     { Bad_Opcode },
3379     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3380     { Bad_Opcode },
3381     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3382     { Bad_Opcode },
3383     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3384   },
3385   /* REG_VEX_0F73 */
3386   {
3387     { Bad_Opcode },
3388     { Bad_Opcode },
3389     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3390     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3391     { Bad_Opcode },
3392     { Bad_Opcode },
3393     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3394     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3395   },
3396   /* REG_VEX_0FAE */
3397   {
3398     { Bad_Opcode },
3399     { Bad_Opcode },
3400     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3401     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3402   },
3403   /* REG_VEX_0F38F3 */
3404   {
3405     { Bad_Opcode },
3406     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3407     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3408     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3409   },
3410   /* REG_XOP_LWPCB */
3411   {
3412     { "llwpcb", { { OP_LWPCB_E, 0 } } },
3413     { "slwpcb", { { OP_LWPCB_E, 0 } } },
3414   },
3415   /* REG_XOP_LWP */
3416   {
3417     { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq } },
3418     { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq } },
3419   },
3420   /* REG_XOP_TBM_01 */
3421   {
3422     { Bad_Opcode },
3423     { "blcfill",        { { OP_LWP_E, 0 }, Ev } },
3424     { "blsfill",        { { OP_LWP_E, 0 }, Ev } },
3425     { "blcs",   { { OP_LWP_E, 0 }, Ev } },
3426     { "tzmsk",  { { OP_LWP_E, 0 }, Ev } },
3427     { "blcic",  { { OP_LWP_E, 0 }, Ev } },
3428     { "blsic",  { { OP_LWP_E, 0 }, Ev } },
3429     { "t1mskc", { { OP_LWP_E, 0 }, Ev } },
3430   },
3431   /* REG_XOP_TBM_02 */
3432   {
3433     { Bad_Opcode },
3434     { "blcmsk", { { OP_LWP_E, 0 }, Ev } },
3435     { Bad_Opcode },
3436     { Bad_Opcode },
3437     { Bad_Opcode },
3438     { Bad_Opcode },
3439     { "blci",   { { OP_LWP_E, 0 }, Ev } },
3440   },
3441 #define NEED_REG_TABLE
3442 #include "i386-dis-evex.h"
3443 #undef NEED_REG_TABLE
3444 };
3445
3446 static const struct dis386 prefix_table[][4] = {
3447   /* PREFIX_90 */
3448   {
3449     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
3450     { "pause", { XX } },
3451     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
3452   },
3453
3454   /* PREFIX_0F10 */
3455   {
3456     { "movups", { XM, EXx } },
3457     { "movss",  { XM, EXd } },
3458     { "movupd", { XM, EXx } },
3459     { "movsd",  { XM, EXq } },
3460   },
3461
3462   /* PREFIX_0F11 */
3463   {
3464     { "movups", { EXxS, XM } },
3465     { "movss",  { EXdS, XM } },
3466     { "movupd", { EXxS, XM } },
3467     { "movsd",  { EXqS, XM } },
3468   },
3469
3470   /* PREFIX_0F12 */
3471   {
3472     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3473     { "movsldup", { XM, EXx } },
3474     { "movlpd", { XM, EXq } },
3475     { "movddup", { XM, EXq } },
3476   },
3477
3478   /* PREFIX_0F16 */
3479   {
3480     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3481     { "movshdup", { XM, EXx } },
3482     { "movhpd", { XM, EXq } },
3483   },
3484
3485   /* PREFIX_0F1A */
3486   {
3487     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3488     { "bndcl",  { Gbnd, Ev_bnd } },
3489     { "bndmov", { Gbnd, Ebnd } },
3490     { "bndcu",  { Gbnd, Ev_bnd } },
3491   },
3492
3493   /* PREFIX_0F1B */
3494   {
3495     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3496     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3497     { "bndmov", { Ebnd, Gbnd } },
3498     { "bndcn",  { Gbnd, Ev_bnd } },
3499   },
3500
3501   /* PREFIX_0F2A */
3502   {
3503     { "cvtpi2ps", { XM, EMCq } },
3504     { "cvtsi2ss%LQ", { XM, Ev } },
3505     { "cvtpi2pd", { XM, EMCq } },
3506     { "cvtsi2sd%LQ", { XM, Ev } },
3507   },
3508
3509   /* PREFIX_0F2B */
3510   {
3511     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3512     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3513     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3514     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3515   },
3516
3517   /* PREFIX_0F2C */
3518   {
3519     { "cvttps2pi", { MXC, EXq } },
3520     { "cvttss2siY", { Gv, EXd } },
3521     { "cvttpd2pi", { MXC, EXx } },
3522     { "cvttsd2siY", { Gv, EXq } },
3523   },
3524
3525   /* PREFIX_0F2D */
3526   {
3527     { "cvtps2pi", { MXC, EXq } },
3528     { "cvtss2siY", { Gv, EXd } },
3529     { "cvtpd2pi", { MXC, EXx } },
3530     { "cvtsd2siY", { Gv, EXq } },
3531   },
3532
3533   /* PREFIX_0F2E */
3534   {
3535     { "ucomiss",{ XM, EXd } },
3536     { Bad_Opcode },
3537     { "ucomisd",{ XM, EXq } },
3538   },
3539
3540   /* PREFIX_0F2F */
3541   {
3542     { "comiss", { XM, EXd } },
3543     { Bad_Opcode },
3544     { "comisd", { XM, EXq } },
3545   },
3546
3547   /* PREFIX_0F51 */
3548   {
3549     { "sqrtps", { XM, EXx } },
3550     { "sqrtss", { XM, EXd } },
3551     { "sqrtpd", { XM, EXx } },
3552     { "sqrtsd", { XM, EXq } },
3553   },
3554
3555   /* PREFIX_0F52 */
3556   {
3557     { "rsqrtps",{ XM, EXx } },
3558     { "rsqrtss",{ XM, EXd } },
3559   },
3560
3561   /* PREFIX_0F53 */
3562   {
3563     { "rcpps",  { XM, EXx } },
3564     { "rcpss",  { XM, EXd } },
3565   },
3566
3567   /* PREFIX_0F58 */
3568   {
3569     { "addps", { XM, EXx } },
3570     { "addss", { XM, EXd } },
3571     { "addpd", { XM, EXx } },
3572     { "addsd", { XM, EXq } },
3573   },
3574
3575   /* PREFIX_0F59 */
3576   {
3577     { "mulps",  { XM, EXx } },
3578     { "mulss",  { XM, EXd } },
3579     { "mulpd",  { XM, EXx } },
3580     { "mulsd",  { XM, EXq } },
3581   },
3582
3583   /* PREFIX_0F5A */
3584   {
3585     { "cvtps2pd", { XM, EXq } },
3586     { "cvtss2sd", { XM, EXd } },
3587     { "cvtpd2ps", { XM, EXx } },
3588     { "cvtsd2ss", { XM, EXq } },
3589   },
3590
3591   /* PREFIX_0F5B */
3592   {
3593     { "cvtdq2ps", { XM, EXx } },
3594     { "cvttps2dq", { XM, EXx } },
3595     { "cvtps2dq", { XM, EXx } },
3596   },
3597
3598   /* PREFIX_0F5C */
3599   {
3600     { "subps",  { XM, EXx } },
3601     { "subss",  { XM, EXd } },
3602     { "subpd",  { XM, EXx } },
3603     { "subsd",  { XM, EXq } },
3604   },
3605
3606   /* PREFIX_0F5D */
3607   {
3608     { "minps",  { XM, EXx } },
3609     { "minss",  { XM, EXd } },
3610     { "minpd",  { XM, EXx } },
3611     { "minsd",  { XM, EXq } },
3612   },
3613
3614   /* PREFIX_0F5E */
3615   {
3616     { "divps",  { XM, EXx } },
3617     { "divss",  { XM, EXd } },
3618     { "divpd",  { XM, EXx } },
3619     { "divsd",  { XM, EXq } },
3620   },
3621
3622   /* PREFIX_0F5F */
3623   {
3624     { "maxps",  { XM, EXx } },
3625     { "maxss",  { XM, EXd } },
3626     { "maxpd",  { XM, EXx } },
3627     { "maxsd",  { XM, EXq } },
3628   },
3629
3630   /* PREFIX_0F60 */
3631   {
3632     { "punpcklbw",{ MX, EMd } },
3633     { Bad_Opcode },
3634     { "punpcklbw",{ MX, EMx } },
3635   },
3636
3637   /* PREFIX_0F61 */
3638   {
3639     { "punpcklwd",{ MX, EMd } },
3640     { Bad_Opcode },
3641     { "punpcklwd",{ MX, EMx } },
3642   },
3643
3644   /* PREFIX_0F62 */
3645   {
3646     { "punpckldq",{ MX, EMd } },
3647     { Bad_Opcode },
3648     { "punpckldq",{ MX, EMx } },
3649   },
3650
3651   /* PREFIX_0F6C */
3652   {
3653     { Bad_Opcode },
3654     { Bad_Opcode },
3655     { "punpcklqdq", { XM, EXx } },
3656   },
3657
3658   /* PREFIX_0F6D */
3659   {
3660     { Bad_Opcode },
3661     { Bad_Opcode },
3662     { "punpckhqdq", { XM, EXx } },
3663   },
3664
3665   /* PREFIX_0F6F */
3666   {
3667     { "movq",   { MX, EM } },
3668     { "movdqu", { XM, EXx } },
3669     { "movdqa", { XM, EXx } },
3670   },
3671
3672   /* PREFIX_0F70 */
3673   {
3674     { "pshufw", { MX, EM, Ib } },
3675     { "pshufhw",{ XM, EXx, Ib } },
3676     { "pshufd", { XM, EXx, Ib } },
3677     { "pshuflw",{ XM, EXx, Ib } },
3678   },
3679
3680   /* PREFIX_0F73_REG_3 */
3681   {
3682     { Bad_Opcode },
3683     { Bad_Opcode },
3684     { "psrldq", { XS, Ib } },
3685   },
3686
3687   /* PREFIX_0F73_REG_7 */
3688   {
3689     { Bad_Opcode },
3690     { Bad_Opcode },
3691     { "pslldq", { XS, Ib } },
3692   },
3693
3694   /* PREFIX_0F78 */
3695   {
3696     {"vmread",  { Em, Gm } },
3697     { Bad_Opcode },
3698     {"extrq",   { XS, Ib, Ib } },
3699     {"insertq", { XM, XS, Ib, Ib } },
3700   },
3701
3702   /* PREFIX_0F79 */
3703   {
3704     {"vmwrite", { Gm, Em } },
3705     { Bad_Opcode },
3706     {"extrq",   { XM, XS } },
3707     {"insertq", { XM, XS } },
3708   },
3709
3710   /* PREFIX_0F7C */
3711   {
3712     { Bad_Opcode },
3713     { Bad_Opcode },
3714     { "haddpd", { XM, EXx } },
3715     { "haddps", { XM, EXx } },
3716   },
3717
3718   /* PREFIX_0F7D */
3719   {
3720     { Bad_Opcode },
3721     { Bad_Opcode },
3722     { "hsubpd", { XM, EXx } },
3723     { "hsubps", { XM, EXx } },
3724   },
3725
3726   /* PREFIX_0F7E */
3727   {
3728     { "movK",   { Edq, MX } },
3729     { "movq",   { XM, EXq } },
3730     { "movK",   { Edq, XM } },
3731   },
3732
3733   /* PREFIX_0F7F */
3734   {
3735     { "movq",   { EMS, MX } },
3736     { "movdqu", { EXxS, XM } },
3737     { "movdqa", { EXxS, XM } },
3738   },
3739
3740   /* PREFIX_0FAE_REG_0 */
3741   {
3742     { Bad_Opcode },
3743     { "rdfsbase", { Ev } },
3744   },
3745
3746   /* PREFIX_0FAE_REG_1 */
3747   {
3748     { Bad_Opcode },
3749     { "rdgsbase", { Ev } },
3750   },
3751
3752   /* PREFIX_0FAE_REG_2 */
3753   {
3754     { Bad_Opcode },
3755     { "wrfsbase", { Ev } },
3756   },
3757
3758   /* PREFIX_0FAE_REG_3 */
3759   {
3760     { Bad_Opcode },
3761     { "wrgsbase", { Ev } },
3762   },
3763
3764   /* PREFIX_0FAE_REG_7 */
3765   {
3766     { "clflush",        { Mb } },
3767     { Bad_Opcode },
3768     { "clflushopt",     { Mb } },
3769   },
3770
3771   /* PREFIX_0FB8 */
3772   {
3773     { Bad_Opcode },
3774     { "popcntS", { Gv, Ev } },
3775   },
3776
3777   /* PREFIX_0FBC */
3778   {
3779     { "bsfS",   { Gv, Ev } },
3780     { "tzcntS", { Gv, Ev } },
3781     { "bsfS",   { Gv, Ev } },
3782   },
3783
3784   /* PREFIX_0FBD */
3785   {
3786     { "bsrS",   { Gv, Ev } },
3787     { "lzcntS", { Gv, Ev } },
3788     { "bsrS",   { Gv, Ev } },
3789   },
3790
3791   /* PREFIX_0FC2 */
3792   {
3793     { "cmpps",  { XM, EXx, CMP } },
3794     { "cmpss",  { XM, EXd, CMP } },
3795     { "cmppd",  { XM, EXx, CMP } },
3796     { "cmpsd",  { XM, EXq, CMP } },
3797   },
3798
3799   /* PREFIX_0FC3 */
3800   {
3801     { "movntiS", { Ma, Gv } },
3802   },
3803
3804   /* PREFIX_0FC7_REG_6 */
3805   {
3806     { "vmptrld",{ Mq } },
3807     { "vmxon",  { Mq } },
3808     { "vmclear",{ Mq } },
3809   },
3810
3811   /* PREFIX_0FD0 */
3812   {
3813     { Bad_Opcode },
3814     { Bad_Opcode },
3815     { "addsubpd", { XM, EXx } },
3816     { "addsubps", { XM, EXx } },
3817   },
3818
3819   /* PREFIX_0FD6 */
3820   {
3821     { Bad_Opcode },
3822     { "movq2dq",{ XM, MS } },
3823     { "movq",   { EXqS, XM } },
3824     { "movdq2q",{ MX, XS } },
3825   },
3826
3827   /* PREFIX_0FE6 */
3828   {
3829     { Bad_Opcode },
3830     { "cvtdq2pd", { XM, EXq } },
3831     { "cvttpd2dq", { XM, EXx } },
3832     { "cvtpd2dq", { XM, EXx } },
3833   },
3834
3835   /* PREFIX_0FE7 */
3836   {
3837     { "movntq", { Mq, MX } },
3838     { Bad_Opcode },
3839     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
3840   },
3841
3842   /* PREFIX_0FF0 */
3843   {
3844     { Bad_Opcode },
3845     { Bad_Opcode },
3846     { Bad_Opcode },
3847     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
3848   },
3849
3850   /* PREFIX_0FF7 */
3851   {
3852     { "maskmovq", { MX, MS } },
3853     { Bad_Opcode },
3854     { "maskmovdqu", { XM, XS } },
3855   },
3856
3857   /* PREFIX_0F3810 */
3858   {
3859     { Bad_Opcode },
3860     { Bad_Opcode },
3861     { "pblendvb", { XM, EXx, XMM0 } },
3862   },
3863
3864   /* PREFIX_0F3814 */
3865   {
3866     { Bad_Opcode },
3867     { Bad_Opcode },
3868     { "blendvps", { XM, EXx, XMM0 } },
3869   },
3870
3871   /* PREFIX_0F3815 */
3872   {
3873     { Bad_Opcode },
3874     { Bad_Opcode },
3875     { "blendvpd", { XM, EXx, XMM0 } },
3876   },
3877
3878   /* PREFIX_0F3817 */
3879   {
3880     { Bad_Opcode },
3881     { Bad_Opcode },
3882     { "ptest",  { XM, EXx } },
3883   },
3884
3885   /* PREFIX_0F3820 */
3886   {
3887     { Bad_Opcode },
3888     { Bad_Opcode },
3889     { "pmovsxbw", { XM, EXq } },
3890   },
3891
3892   /* PREFIX_0F3821 */
3893   {
3894     { Bad_Opcode },
3895     { Bad_Opcode },
3896     { "pmovsxbd", { XM, EXd } },
3897   },
3898
3899   /* PREFIX_0F3822 */
3900   {
3901     { Bad_Opcode },
3902     { Bad_Opcode },
3903     { "pmovsxbq", { XM, EXw } },
3904   },
3905
3906   /* PREFIX_0F3823 */
3907   {
3908     { Bad_Opcode },
3909     { Bad_Opcode },
3910     { "pmovsxwd", { XM, EXq } },
3911   },
3912
3913   /* PREFIX_0F3824 */
3914   {
3915     { Bad_Opcode },
3916     { Bad_Opcode },
3917     { "pmovsxwq", { XM, EXd } },
3918   },
3919
3920   /* PREFIX_0F3825 */
3921   {
3922     { Bad_Opcode },
3923     { Bad_Opcode },
3924     { "pmovsxdq", { XM, EXq } },
3925   },
3926
3927   /* PREFIX_0F3828 */
3928   {
3929     { Bad_Opcode },
3930     { Bad_Opcode },
3931     { "pmuldq", { XM, EXx } },
3932   },
3933
3934   /* PREFIX_0F3829 */
3935   {
3936     { Bad_Opcode },
3937     { Bad_Opcode },
3938     { "pcmpeqq", { XM, EXx } },
3939   },
3940
3941   /* PREFIX_0F382A */
3942   {
3943     { Bad_Opcode },
3944     { Bad_Opcode },
3945     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
3946   },
3947
3948   /* PREFIX_0F382B */
3949   {
3950     { Bad_Opcode },
3951     { Bad_Opcode },
3952     { "packusdw", { XM, EXx } },
3953   },
3954
3955   /* PREFIX_0F3830 */
3956   {
3957     { Bad_Opcode },
3958     { Bad_Opcode },
3959     { "pmovzxbw", { XM, EXq } },
3960   },
3961
3962   /* PREFIX_0F3831 */
3963   {
3964     { Bad_Opcode },
3965     { Bad_Opcode },
3966     { "pmovzxbd", { XM, EXd } },
3967   },
3968
3969   /* PREFIX_0F3832 */
3970   {
3971     { Bad_Opcode },
3972     { Bad_Opcode },
3973     { "pmovzxbq", { XM, EXw } },
3974   },
3975
3976   /* PREFIX_0F3833 */
3977   {
3978     { Bad_Opcode },
3979     { Bad_Opcode },
3980     { "pmovzxwd", { XM, EXq } },
3981   },
3982
3983   /* PREFIX_0F3834 */
3984   {
3985     { Bad_Opcode },
3986     { Bad_Opcode },
3987     { "pmovzxwq", { XM, EXd } },
3988   },
3989
3990   /* PREFIX_0F3835 */
3991   {
3992     { Bad_Opcode },
3993     { Bad_Opcode },
3994     { "pmovzxdq", { XM, EXq } },
3995   },
3996
3997   /* PREFIX_0F3837 */
3998   {
3999     { Bad_Opcode },
4000     { Bad_Opcode },
4001     { "pcmpgtq", { XM, EXx } },
4002   },
4003
4004   /* PREFIX_0F3838 */
4005   {
4006     { Bad_Opcode },
4007     { Bad_Opcode },
4008     { "pminsb", { XM, EXx } },
4009   },
4010
4011   /* PREFIX_0F3839 */
4012   {
4013     { Bad_Opcode },
4014     { Bad_Opcode },
4015     { "pminsd", { XM, EXx } },
4016   },
4017
4018   /* PREFIX_0F383A */
4019   {
4020     { Bad_Opcode },
4021     { Bad_Opcode },
4022     { "pminuw", { XM, EXx } },
4023   },
4024
4025   /* PREFIX_0F383B */
4026   {
4027     { Bad_Opcode },
4028     { Bad_Opcode },
4029     { "pminud", { XM, EXx } },
4030   },
4031
4032   /* PREFIX_0F383C */
4033   {
4034     { Bad_Opcode },
4035     { Bad_Opcode },
4036     { "pmaxsb", { XM, EXx } },
4037   },
4038
4039   /* PREFIX_0F383D */
4040   {
4041     { Bad_Opcode },
4042     { Bad_Opcode },
4043     { "pmaxsd", { XM, EXx } },
4044   },
4045
4046   /* PREFIX_0F383E */
4047   {
4048     { Bad_Opcode },
4049     { Bad_Opcode },
4050     { "pmaxuw", { XM, EXx } },
4051   },
4052
4053   /* PREFIX_0F383F */
4054   {
4055     { Bad_Opcode },
4056     { Bad_Opcode },
4057     { "pmaxud", { XM, EXx } },
4058   },
4059
4060   /* PREFIX_0F3840 */
4061   {
4062     { Bad_Opcode },
4063     { Bad_Opcode },
4064     { "pmulld", { XM, EXx } },
4065   },
4066
4067   /* PREFIX_0F3841 */
4068   {
4069     { Bad_Opcode },
4070     { Bad_Opcode },
4071     { "phminposuw", { XM, EXx } },
4072   },
4073
4074   /* PREFIX_0F3880 */
4075   {
4076     { Bad_Opcode },
4077     { Bad_Opcode },
4078     { "invept", { Gm, Mo } },
4079   },
4080
4081   /* PREFIX_0F3881 */
4082   {
4083     { Bad_Opcode },
4084     { Bad_Opcode },
4085     { "invvpid", { Gm, Mo } },
4086   },
4087
4088   /* PREFIX_0F3882 */
4089   {
4090     { Bad_Opcode },
4091     { Bad_Opcode },
4092     { "invpcid", { Gm, M } },
4093   },
4094
4095   /* PREFIX_0F38C8 */
4096   {
4097     { "sha1nexte", { XM, EXxmm } },
4098   },
4099
4100   /* PREFIX_0F38C9 */
4101   {
4102     { "sha1msg1", { XM, EXxmm } },
4103   },
4104
4105   /* PREFIX_0F38CA */
4106   {
4107     { "sha1msg2", { XM, EXxmm } },
4108   },
4109
4110   /* PREFIX_0F38CB */
4111   {
4112     { "sha256rnds2", { XM, EXxmm, XMM0 } },
4113   },
4114
4115   /* PREFIX_0F38CC */
4116   {
4117     { "sha256msg1", { XM, EXxmm } },
4118   },
4119
4120   /* PREFIX_0F38CD */
4121   {
4122     { "sha256msg2", { XM, EXxmm } },
4123   },
4124
4125   /* PREFIX_0F38DB */
4126   {
4127     { Bad_Opcode },
4128     { Bad_Opcode },
4129     { "aesimc", { XM, EXx } },
4130   },
4131
4132   /* PREFIX_0F38DC */
4133   {
4134     { Bad_Opcode },
4135     { Bad_Opcode },
4136     { "aesenc", { XM, EXx } },
4137   },
4138
4139   /* PREFIX_0F38DD */
4140   {
4141     { Bad_Opcode },
4142     { Bad_Opcode },
4143     { "aesenclast", { XM, EXx } },
4144   },
4145
4146   /* PREFIX_0F38DE */
4147   {
4148     { Bad_Opcode },
4149     { Bad_Opcode },
4150     { "aesdec", { XM, EXx } },
4151   },
4152
4153   /* PREFIX_0F38DF */
4154   {
4155     { Bad_Opcode },
4156     { Bad_Opcode },
4157     { "aesdeclast", { XM, EXx } },
4158   },
4159
4160   /* PREFIX_0F38F0 */
4161   {
4162     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
4163     { Bad_Opcode },
4164     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
4165     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } } },
4166   },
4167
4168   /* PREFIX_0F38F1 */
4169   {
4170     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
4171     { Bad_Opcode },
4172     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
4173     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } } },
4174   },
4175
4176   /* PREFIX_0F38F6 */
4177   {
4178     { Bad_Opcode },
4179     { "adoxS",  { Gdq, Edq} },
4180     { "adcxS",  { Gdq, Edq} },
4181     { Bad_Opcode },
4182   },
4183
4184   /* PREFIX_0F3A08 */
4185   {
4186     { Bad_Opcode },
4187     { Bad_Opcode },
4188     { "roundps", { XM, EXx, Ib } },
4189   },
4190
4191   /* PREFIX_0F3A09 */
4192   {
4193     { Bad_Opcode },
4194     { Bad_Opcode },
4195     { "roundpd", { XM, EXx, Ib } },
4196   },
4197
4198   /* PREFIX_0F3A0A */
4199   {
4200     { Bad_Opcode },
4201     { Bad_Opcode },
4202     { "roundss", { XM, EXd, Ib } },
4203   },
4204
4205   /* PREFIX_0F3A0B */
4206   {
4207     { Bad_Opcode },
4208     { Bad_Opcode },
4209     { "roundsd", { XM, EXq, Ib } },
4210   },
4211
4212   /* PREFIX_0F3A0C */
4213   {
4214     { Bad_Opcode },
4215     { Bad_Opcode },
4216     { "blendps", { XM, EXx, Ib } },
4217   },
4218
4219   /* PREFIX_0F3A0D */
4220   {
4221     { Bad_Opcode },
4222     { Bad_Opcode },
4223     { "blendpd", { XM, EXx, Ib } },
4224   },
4225
4226   /* PREFIX_0F3A0E */
4227   {
4228     { Bad_Opcode },
4229     { Bad_Opcode },
4230     { "pblendw", { XM, EXx, Ib } },
4231   },
4232
4233   /* PREFIX_0F3A14 */
4234   {
4235     { Bad_Opcode },
4236     { Bad_Opcode },
4237     { "pextrb", { Edqb, XM, Ib } },
4238   },
4239
4240   /* PREFIX_0F3A15 */
4241   {
4242     { Bad_Opcode },
4243     { Bad_Opcode },
4244     { "pextrw", { Edqw, XM, Ib } },
4245   },
4246
4247   /* PREFIX_0F3A16 */
4248   {
4249     { Bad_Opcode },
4250     { Bad_Opcode },
4251     { "pextrK", { Edq, XM, Ib } },
4252   },
4253
4254   /* PREFIX_0F3A17 */
4255   {
4256     { Bad_Opcode },
4257     { Bad_Opcode },
4258     { "extractps", { Edqd, XM, Ib } },
4259   },
4260
4261   /* PREFIX_0F3A20 */
4262   {
4263     { Bad_Opcode },
4264     { Bad_Opcode },
4265     { "pinsrb", { XM, Edqb, Ib } },
4266   },
4267
4268   /* PREFIX_0F3A21 */
4269   {
4270     { Bad_Opcode },
4271     { Bad_Opcode },
4272     { "insertps", { XM, EXd, Ib } },
4273   },
4274
4275   /* PREFIX_0F3A22 */
4276   {
4277     { Bad_Opcode },
4278     { Bad_Opcode },
4279     { "pinsrK", { XM, Edq, Ib } },
4280   },
4281
4282   /* PREFIX_0F3A40 */
4283   {
4284     { Bad_Opcode },
4285     { Bad_Opcode },
4286     { "dpps",   { XM, EXx, Ib } },
4287   },
4288
4289   /* PREFIX_0F3A41 */
4290   {
4291     { Bad_Opcode },
4292     { Bad_Opcode },
4293     { "dppd",   { XM, EXx, Ib } },
4294   },
4295
4296   /* PREFIX_0F3A42 */
4297   {
4298     { Bad_Opcode },
4299     { Bad_Opcode },
4300     { "mpsadbw", { XM, EXx, Ib } },
4301   },
4302
4303   /* PREFIX_0F3A44 */
4304   {
4305     { Bad_Opcode },
4306     { Bad_Opcode },
4307     { "pclmulqdq", { XM, EXx, PCLMUL } },
4308   },
4309
4310   /* PREFIX_0F3A60 */
4311   {
4312     { Bad_Opcode },
4313     { Bad_Opcode },
4314     { "pcmpestrm", { XM, EXx, Ib } },
4315   },
4316
4317   /* PREFIX_0F3A61 */
4318   {
4319     { Bad_Opcode },
4320     { Bad_Opcode },
4321     { "pcmpestri", { XM, EXx, Ib } },
4322   },
4323
4324   /* PREFIX_0F3A62 */
4325   {
4326     { Bad_Opcode },
4327     { Bad_Opcode },
4328     { "pcmpistrm", { XM, EXx, Ib } },
4329   },
4330
4331   /* PREFIX_0F3A63 */
4332   {
4333     { Bad_Opcode },
4334     { Bad_Opcode },
4335     { "pcmpistri", { XM, EXx, Ib } },
4336   },
4337
4338   /* PREFIX_0F3ACC */
4339   {
4340     { "sha1rnds4", { XM, EXxmm, Ib } },
4341   },
4342
4343   /* PREFIX_0F3ADF */
4344   {
4345     { Bad_Opcode },
4346     { Bad_Opcode },
4347     { "aeskeygenassist", { XM, EXx, Ib } },
4348   },
4349
4350   /* PREFIX_VEX_0F10 */
4351   {
4352     { VEX_W_TABLE (VEX_W_0F10_P_0) },
4353     { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) },
4354     { VEX_W_TABLE (VEX_W_0F10_P_2) },
4355     { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) },
4356   },
4357
4358   /* PREFIX_VEX_0F11 */
4359   {
4360     { VEX_W_TABLE (VEX_W_0F11_P_0) },
4361     { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) },
4362     { VEX_W_TABLE (VEX_W_0F11_P_2) },
4363     { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) },
4364   },
4365
4366   /* PREFIX_VEX_0F12 */
4367   {
4368     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4369     { VEX_W_TABLE (VEX_W_0F12_P_1) },
4370     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
4371     { VEX_W_TABLE (VEX_W_0F12_P_3) },
4372   },
4373
4374   /* PREFIX_VEX_0F16 */
4375   {
4376     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4377     { VEX_W_TABLE (VEX_W_0F16_P_1) },
4378     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
4379   },
4380
4381   /* PREFIX_VEX_0F2A */
4382   {
4383     { Bad_Opcode },
4384     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) },
4385     { Bad_Opcode },
4386     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) },
4387   },
4388
4389   /* PREFIX_VEX_0F2C */
4390   {
4391     { Bad_Opcode },
4392     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) },
4393     { Bad_Opcode },
4394     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) },
4395   },
4396
4397   /* PREFIX_VEX_0F2D */
4398   {
4399     { Bad_Opcode },
4400     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) },
4401     { Bad_Opcode },
4402     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) },
4403   },
4404
4405   /* PREFIX_VEX_0F2E */
4406   {
4407     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) },
4408     { Bad_Opcode },
4409     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) },
4410   },
4411
4412   /* PREFIX_VEX_0F2F */
4413   {
4414     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) },
4415     { Bad_Opcode },
4416     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) },
4417   },
4418
4419   /* PREFIX_VEX_0F41 */
4420   {
4421     { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4422   },
4423
4424   /* PREFIX_VEX_0F42 */
4425   {
4426     { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4427   },
4428
4429   /* PREFIX_VEX_0F44 */
4430   {
4431     { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4432   },
4433
4434   /* PREFIX_VEX_0F45 */
4435   {
4436     { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4437   },
4438
4439   /* PREFIX_VEX_0F46 */
4440   {
4441     { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4442   },
4443
4444   /* PREFIX_VEX_0F47 */
4445   {
4446     { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4447   },
4448
4449   /* PREFIX_VEX_0F4B */
4450   {
4451     { Bad_Opcode },
4452     { Bad_Opcode },
4453     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4454   },
4455
4456   /* PREFIX_VEX_0F51 */
4457   {
4458     { VEX_W_TABLE (VEX_W_0F51_P_0) },
4459     { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) },
4460     { VEX_W_TABLE (VEX_W_0F51_P_2) },
4461     { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) },
4462   },
4463
4464   /* PREFIX_VEX_0F52 */
4465   {
4466     { VEX_W_TABLE (VEX_W_0F52_P_0) },
4467     { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) },
4468   },
4469
4470   /* PREFIX_VEX_0F53 */
4471   {
4472     { VEX_W_TABLE (VEX_W_0F53_P_0) },
4473     { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) },
4474   },
4475
4476   /* PREFIX_VEX_0F58 */
4477   {
4478     { VEX_W_TABLE (VEX_W_0F58_P_0) },
4479     { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) },
4480     { VEX_W_TABLE (VEX_W_0F58_P_2) },
4481     { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) },
4482   },
4483
4484   /* PREFIX_VEX_0F59 */
4485   {
4486     { VEX_W_TABLE (VEX_W_0F59_P_0) },
4487     { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) },
4488     { VEX_W_TABLE (VEX_W_0F59_P_2) },
4489     { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) },
4490   },
4491
4492   /* PREFIX_VEX_0F5A */
4493   {
4494     { VEX_W_TABLE (VEX_W_0F5A_P_0) },
4495     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) },
4496     { "vcvtpd2ps%XY", { XMM, EXx } },
4497     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) },
4498   },
4499
4500   /* PREFIX_VEX_0F5B */
4501   {
4502     { VEX_W_TABLE (VEX_W_0F5B_P_0) },
4503     { VEX_W_TABLE (VEX_W_0F5B_P_1) },
4504     { VEX_W_TABLE (VEX_W_0F5B_P_2) },
4505   },
4506
4507   /* PREFIX_VEX_0F5C */
4508   {
4509     { VEX_W_TABLE (VEX_W_0F5C_P_0) },
4510     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) },
4511     { VEX_W_TABLE (VEX_W_0F5C_P_2) },
4512     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) },
4513   },
4514
4515   /* PREFIX_VEX_0F5D */
4516   {
4517     { VEX_W_TABLE (VEX_W_0F5D_P_0) },
4518     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) },
4519     { VEX_W_TABLE (VEX_W_0F5D_P_2) },
4520     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) },
4521   },
4522
4523   /* PREFIX_VEX_0F5E */
4524   {
4525     { VEX_W_TABLE (VEX_W_0F5E_P_0) },
4526     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) },
4527     { VEX_W_TABLE (VEX_W_0F5E_P_2) },
4528     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) },
4529   },
4530
4531   /* PREFIX_VEX_0F5F */
4532   {
4533     { VEX_W_TABLE (VEX_W_0F5F_P_0) },
4534     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) },
4535     { VEX_W_TABLE (VEX_W_0F5F_P_2) },
4536     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) },
4537   },
4538
4539   /* PREFIX_VEX_0F60 */
4540   {
4541     { Bad_Opcode },
4542     { Bad_Opcode },
4543     { VEX_W_TABLE (VEX_W_0F60_P_2) },
4544   },
4545
4546   /* PREFIX_VEX_0F61 */
4547   {
4548     { Bad_Opcode },
4549     { Bad_Opcode },
4550     { VEX_W_TABLE (VEX_W_0F61_P_2) },
4551   },
4552
4553   /* PREFIX_VEX_0F62 */
4554   {
4555     { Bad_Opcode },
4556     { Bad_Opcode },
4557     { VEX_W_TABLE (VEX_W_0F62_P_2) },
4558   },
4559
4560   /* PREFIX_VEX_0F63 */
4561   {
4562     { Bad_Opcode },
4563     { Bad_Opcode },
4564     { VEX_W_TABLE (VEX_W_0F63_P_2) },
4565   },
4566
4567   /* PREFIX_VEX_0F64 */
4568   {
4569     { Bad_Opcode },
4570     { Bad_Opcode },
4571     { VEX_W_TABLE (VEX_W_0F64_P_2) },
4572   },
4573
4574   /* PREFIX_VEX_0F65 */
4575   {
4576     { Bad_Opcode },
4577     { Bad_Opcode },
4578     { VEX_W_TABLE (VEX_W_0F65_P_2) },
4579   },
4580
4581   /* PREFIX_VEX_0F66 */
4582   {
4583     { Bad_Opcode },
4584     { Bad_Opcode },
4585     { VEX_W_TABLE (VEX_W_0F66_P_2) },
4586   },
4587
4588   /* PREFIX_VEX_0F67 */
4589   {
4590     { Bad_Opcode },
4591     { Bad_Opcode },
4592     { VEX_W_TABLE (VEX_W_0F67_P_2) },
4593   },
4594
4595   /* PREFIX_VEX_0F68 */
4596   {
4597     { Bad_Opcode },
4598     { Bad_Opcode },
4599     { VEX_W_TABLE (VEX_W_0F68_P_2) },
4600   },
4601
4602   /* PREFIX_VEX_0F69 */
4603   {
4604     { Bad_Opcode },
4605     { Bad_Opcode },
4606     { VEX_W_TABLE (VEX_W_0F69_P_2) },
4607   },
4608
4609   /* PREFIX_VEX_0F6A */
4610   {
4611     { Bad_Opcode },
4612     { Bad_Opcode },
4613     { VEX_W_TABLE (VEX_W_0F6A_P_2) },
4614   },
4615
4616   /* PREFIX_VEX_0F6B */
4617   {
4618     { Bad_Opcode },
4619     { Bad_Opcode },
4620     { VEX_W_TABLE (VEX_W_0F6B_P_2) },
4621   },
4622
4623   /* PREFIX_VEX_0F6C */
4624   {
4625     { Bad_Opcode },
4626     { Bad_Opcode },
4627     { VEX_W_TABLE (VEX_W_0F6C_P_2) },
4628   },
4629
4630   /* PREFIX_VEX_0F6D */
4631   {
4632     { Bad_Opcode },
4633     { Bad_Opcode },
4634     { VEX_W_TABLE (VEX_W_0F6D_P_2) },
4635   },
4636
4637   /* PREFIX_VEX_0F6E */
4638   {
4639     { Bad_Opcode },
4640     { Bad_Opcode },
4641     { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
4642   },
4643
4644   /* PREFIX_VEX_0F6F */
4645   {
4646     { Bad_Opcode },
4647     { VEX_W_TABLE (VEX_W_0F6F_P_1) },
4648     { VEX_W_TABLE (VEX_W_0F6F_P_2) },
4649   },
4650
4651   /* PREFIX_VEX_0F70 */
4652   {
4653     { Bad_Opcode },
4654     { VEX_W_TABLE (VEX_W_0F70_P_1) },
4655     { VEX_W_TABLE (VEX_W_0F70_P_2) },
4656     { VEX_W_TABLE (VEX_W_0F70_P_3) },
4657   },
4658
4659   /* PREFIX_VEX_0F71_REG_2 */
4660   {
4661     { Bad_Opcode },
4662     { Bad_Opcode },
4663     { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) },
4664   },
4665
4666   /* PREFIX_VEX_0F71_REG_4 */
4667   {
4668     { Bad_Opcode },
4669     { Bad_Opcode },
4670     { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) },
4671   },
4672
4673   /* PREFIX_VEX_0F71_REG_6 */
4674   {
4675     { Bad_Opcode },
4676     { Bad_Opcode },
4677     { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) },
4678   },
4679
4680   /* PREFIX_VEX_0F72_REG_2 */
4681   {
4682     { Bad_Opcode },
4683     { Bad_Opcode },
4684     { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) },
4685   },
4686
4687   /* PREFIX_VEX_0F72_REG_4 */
4688   {
4689     { Bad_Opcode },
4690     { Bad_Opcode },
4691     { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) },
4692   },
4693
4694   /* PREFIX_VEX_0F72_REG_6 */
4695   {
4696     { Bad_Opcode },
4697     { Bad_Opcode },
4698     { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) },
4699   },
4700
4701   /* PREFIX_VEX_0F73_REG_2 */
4702   {
4703     { Bad_Opcode },
4704     { Bad_Opcode },
4705     { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) },
4706   },
4707
4708   /* PREFIX_VEX_0F73_REG_3 */
4709   {
4710     { Bad_Opcode },
4711     { Bad_Opcode },
4712     { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) },
4713   },
4714
4715   /* PREFIX_VEX_0F73_REG_6 */
4716   {
4717     { Bad_Opcode },
4718     { Bad_Opcode },
4719     { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) },
4720   },
4721
4722   /* PREFIX_VEX_0F73_REG_7 */
4723   {
4724     { Bad_Opcode },
4725     { Bad_Opcode },
4726     { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) },
4727   },
4728
4729   /* PREFIX_VEX_0F74 */
4730   {
4731     { Bad_Opcode },
4732     { Bad_Opcode },
4733     { VEX_W_TABLE (VEX_W_0F74_P_2) },
4734   },
4735
4736   /* PREFIX_VEX_0F75 */
4737   {
4738     { Bad_Opcode },
4739     { Bad_Opcode },
4740     { VEX_W_TABLE (VEX_W_0F75_P_2) },
4741   },
4742
4743   /* PREFIX_VEX_0F76 */
4744   {
4745     { Bad_Opcode },
4746     { Bad_Opcode },
4747     { VEX_W_TABLE (VEX_W_0F76_P_2) },
4748   },
4749
4750   /* PREFIX_VEX_0F77 */
4751   {
4752     { VEX_W_TABLE (VEX_W_0F77_P_0) },
4753   },
4754
4755   /* PREFIX_VEX_0F7C */
4756   {
4757     { Bad_Opcode },
4758     { Bad_Opcode },
4759     { VEX_W_TABLE (VEX_W_0F7C_P_2) },
4760     { VEX_W_TABLE (VEX_W_0F7C_P_3) },
4761   },
4762
4763   /* PREFIX_VEX_0F7D */
4764   {
4765     { Bad_Opcode },
4766     { Bad_Opcode },
4767     { VEX_W_TABLE (VEX_W_0F7D_P_2) },
4768     { VEX_W_TABLE (VEX_W_0F7D_P_3) },
4769   },
4770
4771   /* PREFIX_VEX_0F7E */
4772   {
4773     { Bad_Opcode },
4774     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
4775     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
4776   },
4777
4778   /* PREFIX_VEX_0F7F */
4779   {
4780     { Bad_Opcode },
4781     { VEX_W_TABLE (VEX_W_0F7F_P_1) },
4782     { VEX_W_TABLE (VEX_W_0F7F_P_2) },
4783   },
4784
4785   /* PREFIX_VEX_0F90 */
4786   {
4787     { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
4788   },
4789
4790   /* PREFIX_VEX_0F91 */
4791   {
4792     { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
4793   },
4794
4795   /* PREFIX_VEX_0F92 */
4796   {
4797     { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
4798   },
4799
4800   /* PREFIX_VEX_0F93 */
4801   {
4802     { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
4803   },
4804
4805   /* PREFIX_VEX_0F98 */
4806   {
4807     { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
4808   },
4809
4810   /* PREFIX_VEX_0FC2 */
4811   {
4812     { VEX_W_TABLE (VEX_W_0FC2_P_0) },
4813     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) },
4814     { VEX_W_TABLE (VEX_W_0FC2_P_2) },
4815     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) },
4816   },
4817
4818   /* PREFIX_VEX_0FC4 */
4819   {
4820     { Bad_Opcode },
4821     { Bad_Opcode },
4822     { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
4823   },
4824
4825   /* PREFIX_VEX_0FC5 */
4826   {
4827     { Bad_Opcode },
4828     { Bad_Opcode },
4829     { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
4830   },
4831
4832   /* PREFIX_VEX_0FD0 */
4833   {
4834     { Bad_Opcode },
4835     { Bad_Opcode },
4836     { VEX_W_TABLE (VEX_W_0FD0_P_2) },
4837     { VEX_W_TABLE (VEX_W_0FD0_P_3) },
4838   },
4839
4840   /* PREFIX_VEX_0FD1 */
4841   {
4842     { Bad_Opcode },
4843     { Bad_Opcode },
4844     { VEX_W_TABLE (VEX_W_0FD1_P_2) },
4845   },
4846
4847   /* PREFIX_VEX_0FD2 */
4848   {
4849     { Bad_Opcode },
4850     { Bad_Opcode },
4851     { VEX_W_TABLE (VEX_W_0FD2_P_2) },
4852   },
4853
4854   /* PREFIX_VEX_0FD3 */
4855   {
4856     { Bad_Opcode },
4857     { Bad_Opcode },
4858     { VEX_W_TABLE (VEX_W_0FD3_P_2) },
4859   },
4860
4861   /* PREFIX_VEX_0FD4 */
4862   {
4863     { Bad_Opcode },
4864     { Bad_Opcode },
4865     { VEX_W_TABLE (VEX_W_0FD4_P_2) },
4866   },
4867
4868   /* PREFIX_VEX_0FD5 */
4869   {
4870     { Bad_Opcode },
4871     { Bad_Opcode },
4872     { VEX_W_TABLE (VEX_W_0FD5_P_2) },
4873   },
4874
4875   /* PREFIX_VEX_0FD6 */
4876   {
4877     { Bad_Opcode },
4878     { Bad_Opcode },
4879     { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
4880   },
4881
4882   /* PREFIX_VEX_0FD7 */
4883   {
4884     { Bad_Opcode },
4885     { Bad_Opcode },
4886     { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
4887   },
4888
4889   /* PREFIX_VEX_0FD8 */
4890   {
4891     { Bad_Opcode },
4892     { Bad_Opcode },
4893     { VEX_W_TABLE (VEX_W_0FD8_P_2) },
4894   },
4895
4896   /* PREFIX_VEX_0FD9 */
4897   {
4898     { Bad_Opcode },
4899     { Bad_Opcode },
4900     { VEX_W_TABLE (VEX_W_0FD9_P_2) },
4901   },
4902
4903   /* PREFIX_VEX_0FDA */
4904   {
4905     { Bad_Opcode },
4906     { Bad_Opcode },
4907     { VEX_W_TABLE (VEX_W_0FDA_P_2) },
4908   },
4909
4910   /* PREFIX_VEX_0FDB */
4911   {
4912     { Bad_Opcode },
4913     { Bad_Opcode },
4914     { VEX_W_TABLE (VEX_W_0FDB_P_2) },
4915   },
4916
4917   /* PREFIX_VEX_0FDC */
4918   {
4919     { Bad_Opcode },
4920     { Bad_Opcode },
4921     { VEX_W_TABLE (VEX_W_0FDC_P_2) },
4922   },
4923
4924   /* PREFIX_VEX_0FDD */
4925   {
4926     { Bad_Opcode },
4927     { Bad_Opcode },
4928     { VEX_W_TABLE (VEX_W_0FDD_P_2) },
4929   },
4930
4931   /* PREFIX_VEX_0FDE */
4932   {
4933     { Bad_Opcode },
4934     { Bad_Opcode },
4935     { VEX_W_TABLE (VEX_W_0FDE_P_2) },
4936   },
4937
4938   /* PREFIX_VEX_0FDF */
4939   {
4940     { Bad_Opcode },
4941     { Bad_Opcode },
4942     { VEX_W_TABLE (VEX_W_0FDF_P_2) },
4943   },
4944
4945   /* PREFIX_VEX_0FE0 */
4946   {
4947     { Bad_Opcode },
4948     { Bad_Opcode },
4949     { VEX_W_TABLE (VEX_W_0FE0_P_2) },
4950   },
4951
4952   /* PREFIX_VEX_0FE1 */
4953   {
4954     { Bad_Opcode },
4955     { Bad_Opcode },
4956     { VEX_W_TABLE (VEX_W_0FE1_P_2) },
4957   },
4958
4959   /* PREFIX_VEX_0FE2 */
4960   {
4961     { Bad_Opcode },
4962     { Bad_Opcode },
4963     { VEX_W_TABLE (VEX_W_0FE2_P_2) },
4964   },
4965
4966   /* PREFIX_VEX_0FE3 */
4967   {
4968     { Bad_Opcode },
4969     { Bad_Opcode },
4970     { VEX_W_TABLE (VEX_W_0FE3_P_2) },
4971   },
4972
4973   /* PREFIX_VEX_0FE4 */
4974   {
4975     { Bad_Opcode },
4976     { Bad_Opcode },
4977     { VEX_W_TABLE (VEX_W_0FE4_P_2) },
4978   },
4979
4980   /* PREFIX_VEX_0FE5 */
4981   {
4982     { Bad_Opcode },
4983     { Bad_Opcode },
4984     { VEX_W_TABLE (VEX_W_0FE5_P_2) },
4985   },
4986
4987   /* PREFIX_VEX_0FE6 */
4988   {
4989     { Bad_Opcode },
4990     { VEX_W_TABLE (VEX_W_0FE6_P_1) },
4991     { VEX_W_TABLE (VEX_W_0FE6_P_2) },
4992     { VEX_W_TABLE (VEX_W_0FE6_P_3) },
4993   },
4994
4995   /* PREFIX_VEX_0FE7 */
4996   {
4997     { Bad_Opcode },
4998     { Bad_Opcode },
4999     { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5000   },
5001
5002   /* PREFIX_VEX_0FE8 */
5003   {
5004     { Bad_Opcode },
5005     { Bad_Opcode },
5006     { VEX_W_TABLE (VEX_W_0FE8_P_2) },
5007   },
5008
5009   /* PREFIX_VEX_0FE9 */
5010   {
5011     { Bad_Opcode },
5012     { Bad_Opcode },
5013     { VEX_W_TABLE (VEX_W_0FE9_P_2) },
5014   },
5015
5016   /* PREFIX_VEX_0FEA */
5017   {
5018     { Bad_Opcode },
5019     { Bad_Opcode },
5020     { VEX_W_TABLE (VEX_W_0FEA_P_2) },
5021   },
5022
5023   /* PREFIX_VEX_0FEB */
5024   {
5025     { Bad_Opcode },
5026     { Bad_Opcode },
5027     { VEX_W_TABLE (VEX_W_0FEB_P_2) },
5028   },
5029
5030   /* PREFIX_VEX_0FEC */
5031   {
5032     { Bad_Opcode },
5033     { Bad_Opcode },
5034     { VEX_W_TABLE (VEX_W_0FEC_P_2) },
5035   },
5036
5037   /* PREFIX_VEX_0FED */
5038   {
5039     { Bad_Opcode },
5040     { Bad_Opcode },
5041     { VEX_W_TABLE (VEX_W_0FED_P_2) },
5042   },
5043
5044   /* PREFIX_VEX_0FEE */
5045   {
5046     { Bad_Opcode },
5047     { Bad_Opcode },
5048     { VEX_W_TABLE (VEX_W_0FEE_P_2) },
5049   },
5050
5051   /* PREFIX_VEX_0FEF */
5052   {
5053     { Bad_Opcode },
5054     { Bad_Opcode },
5055     { VEX_W_TABLE (VEX_W_0FEF_P_2) },
5056   },
5057
5058   /* PREFIX_VEX_0FF0 */
5059   {
5060     { Bad_Opcode },
5061     { Bad_Opcode },
5062     { Bad_Opcode },
5063     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5064   },
5065
5066   /* PREFIX_VEX_0FF1 */
5067   {
5068     { Bad_Opcode },
5069     { Bad_Opcode },
5070     { VEX_W_TABLE (VEX_W_0FF1_P_2) },
5071   },
5072
5073   /* PREFIX_VEX_0FF2 */
5074   {
5075     { Bad_Opcode },
5076     { Bad_Opcode },
5077     { VEX_W_TABLE (VEX_W_0FF2_P_2) },
5078   },
5079
5080   /* PREFIX_VEX_0FF3 */
5081   {
5082     { Bad_Opcode },
5083     { Bad_Opcode },
5084     { VEX_W_TABLE (VEX_W_0FF3_P_2) },
5085   },
5086
5087   /* PREFIX_VEX_0FF4 */
5088   {
5089     { Bad_Opcode },
5090     { Bad_Opcode },
5091     { VEX_W_TABLE (VEX_W_0FF4_P_2) },
5092   },
5093
5094   /* PREFIX_VEX_0FF5 */
5095   {
5096     { Bad_Opcode },
5097     { Bad_Opcode },
5098     { VEX_W_TABLE (VEX_W_0FF5_P_2) },
5099   },
5100
5101   /* PREFIX_VEX_0FF6 */
5102   {
5103     { Bad_Opcode },
5104     { Bad_Opcode },
5105     { VEX_W_TABLE (VEX_W_0FF6_P_2) },
5106   },
5107
5108   /* PREFIX_VEX_0FF7 */
5109   {
5110     { Bad_Opcode },
5111     { Bad_Opcode },
5112     { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5113   },
5114
5115   /* PREFIX_VEX_0FF8 */
5116   {
5117     { Bad_Opcode },
5118     { Bad_Opcode },
5119     { VEX_W_TABLE (VEX_W_0FF8_P_2) },
5120   },
5121
5122   /* PREFIX_VEX_0FF9 */
5123   {
5124     { Bad_Opcode },
5125     { Bad_Opcode },
5126     { VEX_W_TABLE (VEX_W_0FF9_P_2) },
5127   },
5128
5129   /* PREFIX_VEX_0FFA */
5130   {
5131     { Bad_Opcode },
5132     { Bad_Opcode },
5133     { VEX_W_TABLE (VEX_W_0FFA_P_2) },
5134   },
5135
5136   /* PREFIX_VEX_0FFB */
5137   {
5138     { Bad_Opcode },
5139     { Bad_Opcode },
5140     { VEX_W_TABLE (VEX_W_0FFB_P_2) },
5141   },
5142
5143   /* PREFIX_VEX_0FFC */
5144   {
5145     { Bad_Opcode },
5146     { Bad_Opcode },
5147     { VEX_W_TABLE (VEX_W_0FFC_P_2) },
5148   },
5149
5150   /* PREFIX_VEX_0FFD */
5151   {
5152     { Bad_Opcode },
5153     { Bad_Opcode },
5154     { VEX_W_TABLE (VEX_W_0FFD_P_2) },
5155   },
5156
5157   /* PREFIX_VEX_0FFE */
5158   {
5159     { Bad_Opcode },
5160     { Bad_Opcode },
5161     { VEX_W_TABLE (VEX_W_0FFE_P_2) },
5162   },
5163
5164   /* PREFIX_VEX_0F3800 */
5165   {
5166     { Bad_Opcode },
5167     { Bad_Opcode },
5168     { VEX_W_TABLE (VEX_W_0F3800_P_2) },
5169   },
5170
5171   /* PREFIX_VEX_0F3801 */
5172   {
5173     { Bad_Opcode },
5174     { Bad_Opcode },
5175     { VEX_W_TABLE (VEX_W_0F3801_P_2) },
5176   },
5177
5178   /* PREFIX_VEX_0F3802 */
5179   {
5180     { Bad_Opcode },
5181     { Bad_Opcode },
5182     { VEX_W_TABLE (VEX_W_0F3802_P_2) },
5183   },
5184
5185   /* PREFIX_VEX_0F3803 */
5186   {
5187     { Bad_Opcode },
5188     { Bad_Opcode },
5189     { VEX_W_TABLE (VEX_W_0F3803_P_2) },
5190   },
5191
5192   /* PREFIX_VEX_0F3804 */
5193   {
5194     { Bad_Opcode },
5195     { Bad_Opcode },
5196     { VEX_W_TABLE (VEX_W_0F3804_P_2) },
5197   },
5198
5199   /* PREFIX_VEX_0F3805 */
5200   {
5201     { Bad_Opcode },
5202     { Bad_Opcode },
5203     { VEX_W_TABLE (VEX_W_0F3805_P_2) },
5204   },
5205
5206   /* PREFIX_VEX_0F3806 */
5207   {
5208     { Bad_Opcode },
5209     { Bad_Opcode },
5210     { VEX_W_TABLE (VEX_W_0F3806_P_2) },
5211   },
5212
5213   /* PREFIX_VEX_0F3807 */
5214   {
5215     { Bad_Opcode },
5216     { Bad_Opcode },
5217     { VEX_W_TABLE (VEX_W_0F3807_P_2) },
5218   },
5219
5220   /* PREFIX_VEX_0F3808 */
5221   {
5222     { Bad_Opcode },
5223     { Bad_Opcode },
5224     { VEX_W_TABLE (VEX_W_0F3808_P_2) },
5225   },
5226
5227   /* PREFIX_VEX_0F3809 */
5228   {
5229     { Bad_Opcode },
5230     { Bad_Opcode },
5231     { VEX_W_TABLE (VEX_W_0F3809_P_2) },
5232   },
5233
5234   /* PREFIX_VEX_0F380A */
5235   {
5236     { Bad_Opcode },
5237     { Bad_Opcode },
5238     { VEX_W_TABLE (VEX_W_0F380A_P_2) },
5239   },
5240
5241   /* PREFIX_VEX_0F380B */
5242   {
5243     { Bad_Opcode },
5244     { Bad_Opcode },
5245     { VEX_W_TABLE (VEX_W_0F380B_P_2) },
5246   },
5247
5248   /* PREFIX_VEX_0F380C */
5249   {
5250     { Bad_Opcode },
5251     { Bad_Opcode },
5252     { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5253   },
5254
5255   /* PREFIX_VEX_0F380D */
5256   {
5257     { Bad_Opcode },
5258     { Bad_Opcode },
5259     { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5260   },
5261
5262   /* PREFIX_VEX_0F380E */
5263   {
5264     { Bad_Opcode },
5265     { Bad_Opcode },
5266     { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5267   },
5268
5269   /* PREFIX_VEX_0F380F */
5270   {
5271     { Bad_Opcode },
5272     { Bad_Opcode },
5273     { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5274   },
5275
5276   /* PREFIX_VEX_0F3813 */
5277   {
5278     { Bad_Opcode },
5279     { Bad_Opcode },
5280     { "vcvtph2ps", { XM, EXxmmq } },
5281   },
5282
5283   /* PREFIX_VEX_0F3816 */
5284   {
5285     { Bad_Opcode },
5286     { Bad_Opcode },
5287     { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5288   },
5289
5290   /* PREFIX_VEX_0F3817 */
5291   {
5292     { Bad_Opcode },
5293     { Bad_Opcode },
5294     { VEX_W_TABLE (VEX_W_0F3817_P_2) },
5295   },
5296
5297   /* PREFIX_VEX_0F3818 */
5298   {
5299     { Bad_Opcode },
5300     { Bad_Opcode },
5301     { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5302   },
5303
5304   /* PREFIX_VEX_0F3819 */
5305   {
5306     { Bad_Opcode },
5307     { Bad_Opcode },
5308     { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5309   },
5310
5311   /* PREFIX_VEX_0F381A */
5312   {
5313     { Bad_Opcode },
5314     { Bad_Opcode },
5315     { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5316   },
5317
5318   /* PREFIX_VEX_0F381C */
5319   {
5320     { Bad_Opcode },
5321     { Bad_Opcode },
5322     { VEX_W_TABLE (VEX_W_0F381C_P_2) },
5323   },
5324
5325   /* PREFIX_VEX_0F381D */
5326   {
5327     { Bad_Opcode },
5328     { Bad_Opcode },
5329     { VEX_W_TABLE (VEX_W_0F381D_P_2) },
5330   },
5331
5332   /* PREFIX_VEX_0F381E */
5333   {
5334     { Bad_Opcode },
5335     { Bad_Opcode },
5336     { VEX_W_TABLE (VEX_W_0F381E_P_2) },
5337   },
5338
5339   /* PREFIX_VEX_0F3820 */
5340   {
5341     { Bad_Opcode },
5342     { Bad_Opcode },
5343     { VEX_W_TABLE (VEX_W_0F3820_P_2) },
5344   },
5345
5346   /* PREFIX_VEX_0F3821 */
5347   {
5348     { Bad_Opcode },
5349     { Bad_Opcode },
5350     { VEX_W_TABLE (VEX_W_0F3821_P_2) },
5351   },
5352
5353   /* PREFIX_VEX_0F3822 */
5354   {
5355     { Bad_Opcode },
5356     { Bad_Opcode },
5357     { VEX_W_TABLE (VEX_W_0F3822_P_2) },
5358   },
5359
5360   /* PREFIX_VEX_0F3823 */
5361   {
5362     { Bad_Opcode },
5363     { Bad_Opcode },
5364     { VEX_W_TABLE (VEX_W_0F3823_P_2) },
5365   },
5366
5367   /* PREFIX_VEX_0F3824 */
5368   {
5369     { Bad_Opcode },
5370     { Bad_Opcode },
5371     { VEX_W_TABLE (VEX_W_0F3824_P_2) },
5372   },
5373
5374   /* PREFIX_VEX_0F3825 */
5375   {
5376     { Bad_Opcode },
5377     { Bad_Opcode },
5378     { VEX_W_TABLE (VEX_W_0F3825_P_2) },
5379   },
5380
5381   /* PREFIX_VEX_0F3828 */
5382   {
5383     { Bad_Opcode },
5384     { Bad_Opcode },
5385     { VEX_W_TABLE (VEX_W_0F3828_P_2) },
5386   },
5387
5388   /* PREFIX_VEX_0F3829 */
5389   {
5390     { Bad_Opcode },
5391     { Bad_Opcode },
5392     { VEX_W_TABLE (VEX_W_0F3829_P_2) },
5393   },
5394
5395   /* PREFIX_VEX_0F382A */
5396   {
5397     { Bad_Opcode },
5398     { Bad_Opcode },
5399     { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5400   },
5401
5402   /* PREFIX_VEX_0F382B */
5403   {
5404     { Bad_Opcode },
5405     { Bad_Opcode },
5406     { VEX_W_TABLE (VEX_W_0F382B_P_2) },
5407   },
5408
5409   /* PREFIX_VEX_0F382C */
5410   {
5411     { Bad_Opcode },
5412     { Bad_Opcode },
5413      { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5414   },
5415
5416   /* PREFIX_VEX_0F382D */
5417   {
5418     { Bad_Opcode },
5419     { Bad_Opcode },
5420      { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5421   },
5422
5423   /* PREFIX_VEX_0F382E */
5424   {
5425     { Bad_Opcode },
5426     { Bad_Opcode },
5427      { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5428   },
5429
5430   /* PREFIX_VEX_0F382F */
5431   {
5432     { Bad_Opcode },
5433     { Bad_Opcode },
5434      { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5435   },
5436
5437   /* PREFIX_VEX_0F3830 */
5438   {
5439     { Bad_Opcode },
5440     { Bad_Opcode },
5441     { VEX_W_TABLE (VEX_W_0F3830_P_2) },
5442   },
5443
5444   /* PREFIX_VEX_0F3831 */
5445   {
5446     { Bad_Opcode },
5447     { Bad_Opcode },
5448     { VEX_W_TABLE (VEX_W_0F3831_P_2) },
5449   },
5450
5451   /* PREFIX_VEX_0F3832 */
5452   {
5453     { Bad_Opcode },
5454     { Bad_Opcode },
5455     { VEX_W_TABLE (VEX_W_0F3832_P_2) },
5456   },
5457
5458   /* PREFIX_VEX_0F3833 */
5459   {
5460     { Bad_Opcode },
5461     { Bad_Opcode },
5462     { VEX_W_TABLE (VEX_W_0F3833_P_2) },
5463   },
5464
5465   /* PREFIX_VEX_0F3834 */
5466   {
5467     { Bad_Opcode },
5468     { Bad_Opcode },
5469     { VEX_W_TABLE (VEX_W_0F3834_P_2) },
5470   },
5471
5472   /* PREFIX_VEX_0F3835 */
5473   {
5474     { Bad_Opcode },
5475     { Bad_Opcode },
5476     { VEX_W_TABLE (VEX_W_0F3835_P_2) },
5477   },
5478
5479   /* PREFIX_VEX_0F3836 */
5480   {
5481     { Bad_Opcode },
5482     { Bad_Opcode },
5483     { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5484   },
5485
5486   /* PREFIX_VEX_0F3837 */
5487   {
5488     { Bad_Opcode },
5489     { Bad_Opcode },
5490     { VEX_W_TABLE (VEX_W_0F3837_P_2) },
5491   },
5492
5493   /* PREFIX_VEX_0F3838 */
5494   {
5495     { Bad_Opcode },
5496     { Bad_Opcode },
5497     { VEX_W_TABLE (VEX_W_0F3838_P_2) },
5498   },
5499
5500   /* PREFIX_VEX_0F3839 */
5501   {
5502     { Bad_Opcode },
5503     { Bad_Opcode },
5504     { VEX_W_TABLE (VEX_W_0F3839_P_2) },
5505   },
5506
5507   /* PREFIX_VEX_0F383A */
5508   {
5509     { Bad_Opcode },
5510     { Bad_Opcode },
5511     { VEX_W_TABLE (VEX_W_0F383A_P_2) },
5512   },
5513
5514   /* PREFIX_VEX_0F383B */
5515   {
5516     { Bad_Opcode },
5517     { Bad_Opcode },
5518     { VEX_W_TABLE (VEX_W_0F383B_P_2) },
5519   },
5520
5521   /* PREFIX_VEX_0F383C */
5522   {
5523     { Bad_Opcode },
5524     { Bad_Opcode },
5525     { VEX_W_TABLE (VEX_W_0F383C_P_2) },
5526   },
5527
5528   /* PREFIX_VEX_0F383D */
5529   {
5530     { Bad_Opcode },
5531     { Bad_Opcode },
5532     { VEX_W_TABLE (VEX_W_0F383D_P_2) },
5533   },
5534
5535   /* PREFIX_VEX_0F383E */
5536   {
5537     { Bad_Opcode },
5538     { Bad_Opcode },
5539     { VEX_W_TABLE (VEX_W_0F383E_P_2) },
5540   },
5541
5542   /* PREFIX_VEX_0F383F */
5543   {
5544     { Bad_Opcode },
5545     { Bad_Opcode },
5546     { VEX_W_TABLE (VEX_W_0F383F_P_2) },
5547   },
5548
5549   /* PREFIX_VEX_0F3840 */
5550   {
5551     { Bad_Opcode },
5552     { Bad_Opcode },
5553     { VEX_W_TABLE (VEX_W_0F3840_P_2) },
5554   },
5555
5556   /* PREFIX_VEX_0F3841 */
5557   {
5558     { Bad_Opcode },
5559     { Bad_Opcode },
5560     { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
5561   },
5562
5563   /* PREFIX_VEX_0F3845 */
5564   {
5565     { Bad_Opcode },
5566     { Bad_Opcode },
5567     { "vpsrlv%LW", { XM, Vex, EXx } },
5568   },
5569
5570   /* PREFIX_VEX_0F3846 */
5571   {
5572     { Bad_Opcode },
5573     { Bad_Opcode },
5574     { VEX_W_TABLE (VEX_W_0F3846_P_2) },
5575   },
5576
5577   /* PREFIX_VEX_0F3847 */
5578   {
5579     { Bad_Opcode },
5580     { Bad_Opcode },
5581     { "vpsllv%LW", { XM, Vex, EXx } },
5582   },
5583
5584   /* PREFIX_VEX_0F3858 */
5585   {
5586     { Bad_Opcode },
5587     { Bad_Opcode },
5588     { VEX_W_TABLE (VEX_W_0F3858_P_2) },
5589   },
5590
5591   /* PREFIX_VEX_0F3859 */
5592   {
5593     { Bad_Opcode },
5594     { Bad_Opcode },
5595     { VEX_W_TABLE (VEX_W_0F3859_P_2) },
5596   },
5597
5598   /* PREFIX_VEX_0F385A */
5599   {
5600     { Bad_Opcode },
5601     { Bad_Opcode },
5602     { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
5603   },
5604
5605   /* PREFIX_VEX_0F3878 */
5606   {
5607     { Bad_Opcode },
5608     { Bad_Opcode },
5609     { VEX_W_TABLE (VEX_W_0F3878_P_2) },
5610   },
5611
5612   /* PREFIX_VEX_0F3879 */
5613   {
5614     { Bad_Opcode },
5615     { Bad_Opcode },
5616     { VEX_W_TABLE (VEX_W_0F3879_P_2) },
5617   },
5618
5619   /* PREFIX_VEX_0F388C */
5620   {
5621     { Bad_Opcode },
5622     { Bad_Opcode },
5623     { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
5624   },
5625
5626   /* PREFIX_VEX_0F388E */
5627   {
5628     { Bad_Opcode },
5629     { Bad_Opcode },
5630     { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
5631   },
5632
5633   /* PREFIX_VEX_0F3890 */
5634   {
5635     { Bad_Opcode },
5636     { Bad_Opcode },
5637     { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex } },
5638   },
5639
5640   /* PREFIX_VEX_0F3891 */
5641   {
5642     { Bad_Opcode },
5643     { Bad_Opcode },
5644     { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ } },
5645   },
5646
5647   /* PREFIX_VEX_0F3892 */
5648   {
5649     { Bad_Opcode },
5650     { Bad_Opcode },
5651     { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex } },
5652   },
5653
5654   /* PREFIX_VEX_0F3893 */
5655   {
5656     { Bad_Opcode },
5657     { Bad_Opcode },
5658     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ } },
5659   },
5660
5661   /* PREFIX_VEX_0F3896 */
5662   {
5663     { Bad_Opcode },
5664     { Bad_Opcode },
5665     { "vfmaddsub132p%XW", { XM, Vex, EXx } },
5666   },
5667
5668   /* PREFIX_VEX_0F3897 */
5669   {
5670     { Bad_Opcode },
5671     { Bad_Opcode },
5672     { "vfmsubadd132p%XW", { XM, Vex, EXx } },
5673   },
5674
5675   /* PREFIX_VEX_0F3898 */
5676   {
5677     { Bad_Opcode },
5678     { Bad_Opcode },
5679     { "vfmadd132p%XW", { XM, Vex, EXx } },
5680   },
5681
5682   /* PREFIX_VEX_0F3899 */
5683   {
5684     { Bad_Opcode },
5685     { Bad_Opcode },
5686     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5687   },
5688
5689   /* PREFIX_VEX_0F389A */
5690   {
5691     { Bad_Opcode },
5692     { Bad_Opcode },
5693     { "vfmsub132p%XW", { XM, Vex, EXx } },
5694   },
5695
5696   /* PREFIX_VEX_0F389B */
5697   {
5698     { Bad_Opcode },
5699     { Bad_Opcode },
5700     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5701   },
5702
5703   /* PREFIX_VEX_0F389C */
5704   {
5705     { Bad_Opcode },
5706     { Bad_Opcode },
5707     { "vfnmadd132p%XW", { XM, Vex, EXx } },
5708   },
5709
5710   /* PREFIX_VEX_0F389D */
5711   {
5712     { Bad_Opcode },
5713     { Bad_Opcode },
5714     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5715   },
5716
5717   /* PREFIX_VEX_0F389E */
5718   {
5719     { Bad_Opcode },
5720     { Bad_Opcode },
5721     { "vfnmsub132p%XW", { XM, Vex, EXx } },
5722   },
5723
5724   /* PREFIX_VEX_0F389F */
5725   {
5726     { Bad_Opcode },
5727     { Bad_Opcode },
5728     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5729   },
5730
5731   /* PREFIX_VEX_0F38A6 */
5732   {
5733     { Bad_Opcode },
5734     { Bad_Opcode },
5735     { "vfmaddsub213p%XW", { XM, Vex, EXx } },
5736     { Bad_Opcode },
5737   },
5738
5739   /* PREFIX_VEX_0F38A7 */
5740   {
5741     { Bad_Opcode },
5742     { Bad_Opcode },
5743     { "vfmsubadd213p%XW", { XM, Vex, EXx } },
5744   },
5745
5746   /* PREFIX_VEX_0F38A8 */
5747   {
5748     { Bad_Opcode },
5749     { Bad_Opcode },
5750     { "vfmadd213p%XW", { XM, Vex, EXx } },
5751   },
5752
5753   /* PREFIX_VEX_0F38A9 */
5754   {
5755     { Bad_Opcode },
5756     { Bad_Opcode },
5757     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5758   },
5759
5760   /* PREFIX_VEX_0F38AA */
5761   {
5762     { Bad_Opcode },
5763     { Bad_Opcode },
5764     { "vfmsub213p%XW", { XM, Vex, EXx } },
5765   },
5766
5767   /* PREFIX_VEX_0F38AB */
5768   {
5769     { Bad_Opcode },
5770     { Bad_Opcode },
5771     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5772   },
5773
5774   /* PREFIX_VEX_0F38AC */
5775   {
5776     { Bad_Opcode },
5777     { Bad_Opcode },
5778     { "vfnmadd213p%XW", { XM, Vex, EXx } },
5779   },
5780
5781   /* PREFIX_VEX_0F38AD */
5782   {
5783     { Bad_Opcode },
5784     { Bad_Opcode },
5785     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5786   },
5787
5788   /* PREFIX_VEX_0F38AE */
5789   {
5790     { Bad_Opcode },
5791     { Bad_Opcode },
5792     { "vfnmsub213p%XW", { XM, Vex, EXx } },
5793   },
5794
5795   /* PREFIX_VEX_0F38AF */
5796   {
5797     { Bad_Opcode },
5798     { Bad_Opcode },
5799     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5800   },
5801
5802   /* PREFIX_VEX_0F38B6 */
5803   {
5804     { Bad_Opcode },
5805     { Bad_Opcode },
5806     { "vfmaddsub231p%XW", { XM, Vex, EXx } },
5807   },
5808
5809   /* PREFIX_VEX_0F38B7 */
5810   {
5811     { Bad_Opcode },
5812     { Bad_Opcode },
5813     { "vfmsubadd231p%XW", { XM, Vex, EXx } },
5814   },
5815
5816   /* PREFIX_VEX_0F38B8 */
5817   {
5818     { Bad_Opcode },
5819     { Bad_Opcode },
5820     { "vfmadd231p%XW", { XM, Vex, EXx } },
5821   },
5822
5823   /* PREFIX_VEX_0F38B9 */
5824   {
5825     { Bad_Opcode },
5826     { Bad_Opcode },
5827     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5828   },
5829
5830   /* PREFIX_VEX_0F38BA */
5831   {
5832     { Bad_Opcode },
5833     { Bad_Opcode },
5834     { "vfmsub231p%XW", { XM, Vex, EXx } },
5835   },
5836
5837   /* PREFIX_VEX_0F38BB */
5838   {
5839     { Bad_Opcode },
5840     { Bad_Opcode },
5841     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5842   },
5843
5844   /* PREFIX_VEX_0F38BC */
5845   {
5846     { Bad_Opcode },
5847     { Bad_Opcode },
5848     { "vfnmadd231p%XW", { XM, Vex, EXx } },
5849   },
5850
5851   /* PREFIX_VEX_0F38BD */
5852   {
5853     { Bad_Opcode },
5854     { Bad_Opcode },
5855     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5856   },
5857
5858   /* PREFIX_VEX_0F38BE */
5859   {
5860     { Bad_Opcode },
5861     { Bad_Opcode },
5862     { "vfnmsub231p%XW", { XM, Vex, EXx } },
5863   },
5864
5865   /* PREFIX_VEX_0F38BF */
5866   {
5867     { Bad_Opcode },
5868     { Bad_Opcode },
5869     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5870   },
5871
5872   /* PREFIX_VEX_0F38DB */
5873   {
5874     { Bad_Opcode },
5875     { Bad_Opcode },
5876     { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
5877   },
5878
5879   /* PREFIX_VEX_0F38DC */
5880   {
5881     { Bad_Opcode },
5882     { Bad_Opcode },
5883     { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2) },
5884   },
5885
5886   /* PREFIX_VEX_0F38DD */
5887   {
5888     { Bad_Opcode },
5889     { Bad_Opcode },
5890     { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2) },
5891   },
5892
5893   /* PREFIX_VEX_0F38DE */
5894   {
5895     { Bad_Opcode },
5896     { Bad_Opcode },
5897     { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2) },
5898   },
5899
5900   /* PREFIX_VEX_0F38DF */
5901   {
5902     { Bad_Opcode },
5903     { Bad_Opcode },
5904     { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2) },
5905   },
5906
5907   /* PREFIX_VEX_0F38F2 */
5908   {
5909     { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
5910   },
5911
5912   /* PREFIX_VEX_0F38F3_REG_1 */
5913   {
5914     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
5915   },
5916
5917   /* PREFIX_VEX_0F38F3_REG_2 */
5918   {
5919     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
5920   },
5921
5922   /* PREFIX_VEX_0F38F3_REG_3 */
5923   {
5924     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
5925   },
5926
5927   /* PREFIX_VEX_0F38F5 */
5928   {
5929     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
5930     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
5931     { Bad_Opcode },
5932     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
5933   },
5934
5935   /* PREFIX_VEX_0F38F6 */
5936   {
5937     { Bad_Opcode },
5938     { Bad_Opcode },
5939     { Bad_Opcode },
5940     { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
5941   },
5942
5943   /* PREFIX_VEX_0F38F7 */
5944   {
5945     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
5946     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
5947     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
5948     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
5949   },
5950
5951   /* PREFIX_VEX_0F3A00 */
5952   {
5953     { Bad_Opcode },
5954     { Bad_Opcode },
5955     { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
5956   },
5957
5958   /* PREFIX_VEX_0F3A01 */
5959   {
5960     { Bad_Opcode },
5961     { Bad_Opcode },
5962     { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
5963   },
5964
5965   /* PREFIX_VEX_0F3A02 */
5966   {
5967     { Bad_Opcode },
5968     { Bad_Opcode },
5969     { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
5970   },
5971
5972   /* PREFIX_VEX_0F3A04 */
5973   {
5974     { Bad_Opcode },
5975     { Bad_Opcode },
5976     { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
5977   },
5978
5979   /* PREFIX_VEX_0F3A05 */
5980   {
5981     { Bad_Opcode },
5982     { Bad_Opcode },
5983     { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
5984   },
5985
5986   /* PREFIX_VEX_0F3A06 */
5987   {
5988     { Bad_Opcode },
5989     { Bad_Opcode },
5990     { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
5991   },
5992
5993   /* PREFIX_VEX_0F3A08 */
5994   {
5995     { Bad_Opcode },
5996     { Bad_Opcode },
5997     { VEX_W_TABLE (VEX_W_0F3A08_P_2) },
5998   },
5999
6000   /* PREFIX_VEX_0F3A09 */
6001   {
6002     { Bad_Opcode },
6003     { Bad_Opcode },
6004     { VEX_W_TABLE (VEX_W_0F3A09_P_2) },
6005   },
6006
6007   /* PREFIX_VEX_0F3A0A */
6008   {
6009     { Bad_Opcode },
6010     { Bad_Opcode },
6011     { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) },
6012   },
6013
6014   /* PREFIX_VEX_0F3A0B */
6015   {
6016     { Bad_Opcode },
6017     { Bad_Opcode },
6018     { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) },
6019   },
6020
6021   /* PREFIX_VEX_0F3A0C */
6022   {
6023     { Bad_Opcode },
6024     { Bad_Opcode },
6025     { VEX_W_TABLE (VEX_W_0F3A0C_P_2) },
6026   },
6027
6028   /* PREFIX_VEX_0F3A0D */
6029   {
6030     { Bad_Opcode },
6031     { Bad_Opcode },
6032     { VEX_W_TABLE (VEX_W_0F3A0D_P_2) },
6033   },
6034
6035   /* PREFIX_VEX_0F3A0E */
6036   {
6037     { Bad_Opcode },
6038     { Bad_Opcode },
6039     { VEX_W_TABLE (VEX_W_0F3A0E_P_2) },
6040   },
6041
6042   /* PREFIX_VEX_0F3A0F */
6043   {
6044     { Bad_Opcode },
6045     { Bad_Opcode },
6046     { VEX_W_TABLE (VEX_W_0F3A0F_P_2) },
6047   },
6048
6049   /* PREFIX_VEX_0F3A14 */
6050   {
6051     { Bad_Opcode },
6052     { Bad_Opcode },
6053     { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6054   },
6055
6056   /* PREFIX_VEX_0F3A15 */
6057   {
6058     { Bad_Opcode },
6059     { Bad_Opcode },
6060     { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6061   },
6062
6063   /* PREFIX_VEX_0F3A16 */
6064   {
6065     { Bad_Opcode },
6066     { Bad_Opcode },
6067     { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6068   },
6069
6070   /* PREFIX_VEX_0F3A17 */
6071   {
6072     { Bad_Opcode },
6073     { Bad_Opcode },
6074     { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6075   },
6076
6077   /* PREFIX_VEX_0F3A18 */
6078   {
6079     { Bad_Opcode },
6080     { Bad_Opcode },
6081     { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6082   },
6083
6084   /* PREFIX_VEX_0F3A19 */
6085   {
6086     { Bad_Opcode },
6087     { Bad_Opcode },
6088     { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6089   },
6090
6091   /* PREFIX_VEX_0F3A1D */
6092   {
6093     { Bad_Opcode },
6094     { Bad_Opcode },
6095     { "vcvtps2ph", { EXxmmq, XM, Ib } },
6096   },
6097
6098   /* PREFIX_VEX_0F3A20 */
6099   {
6100     { Bad_Opcode },
6101     { Bad_Opcode },
6102     { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6103   },
6104
6105   /* PREFIX_VEX_0F3A21 */
6106   {
6107     { Bad_Opcode },
6108     { Bad_Opcode },
6109     { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6110   },
6111
6112   /* PREFIX_VEX_0F3A22 */
6113   {
6114     { Bad_Opcode },
6115     { Bad_Opcode },
6116     { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6117   },
6118
6119   /* PREFIX_VEX_0F3A30 */
6120   {
6121     { Bad_Opcode },
6122     { Bad_Opcode },
6123     { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6124   },
6125
6126   /* PREFIX_VEX_0F3A32 */
6127   {
6128     { Bad_Opcode },
6129     { Bad_Opcode },
6130     { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6131   },
6132
6133   /* PREFIX_VEX_0F3A38 */
6134   {
6135     { Bad_Opcode },
6136     { Bad_Opcode },
6137     { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6138   },
6139
6140   /* PREFIX_VEX_0F3A39 */
6141   {
6142     { Bad_Opcode },
6143     { Bad_Opcode },
6144     { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6145   },
6146
6147   /* PREFIX_VEX_0F3A40 */
6148   {
6149     { Bad_Opcode },
6150     { Bad_Opcode },
6151     { VEX_W_TABLE (VEX_W_0F3A40_P_2) },
6152   },
6153
6154   /* PREFIX_VEX_0F3A41 */
6155   {
6156     { Bad_Opcode },
6157     { Bad_Opcode },
6158     { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6159   },
6160
6161   /* PREFIX_VEX_0F3A42 */
6162   {
6163     { Bad_Opcode },
6164     { Bad_Opcode },
6165     { VEX_W_TABLE (VEX_W_0F3A42_P_2) },
6166   },
6167
6168   /* PREFIX_VEX_0F3A44 */
6169   {
6170     { Bad_Opcode },
6171     { Bad_Opcode },
6172     { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2) },
6173   },
6174
6175   /* PREFIX_VEX_0F3A46 */
6176   {
6177     { Bad_Opcode },
6178     { Bad_Opcode },
6179     { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6180   },
6181
6182   /* PREFIX_VEX_0F3A48 */
6183   {
6184     { Bad_Opcode },
6185     { Bad_Opcode },
6186     { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6187   },
6188
6189   /* PREFIX_VEX_0F3A49 */
6190   {
6191     { Bad_Opcode },
6192     { Bad_Opcode },
6193     { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6194   },
6195
6196   /* PREFIX_VEX_0F3A4A */
6197   {
6198     { Bad_Opcode },
6199     { Bad_Opcode },
6200     { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6201   },
6202
6203   /* PREFIX_VEX_0F3A4B */
6204   {
6205     { Bad_Opcode },
6206     { Bad_Opcode },
6207     { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6208   },
6209
6210   /* PREFIX_VEX_0F3A4C */
6211   {
6212     { Bad_Opcode },
6213     { Bad_Opcode },
6214     { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6215   },
6216
6217   /* PREFIX_VEX_0F3A5C */
6218   {
6219     { Bad_Opcode },
6220     { Bad_Opcode },
6221     { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6222   },
6223
6224   /* PREFIX_VEX_0F3A5D */
6225   {
6226     { Bad_Opcode },
6227     { Bad_Opcode },
6228     { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6229   },
6230
6231   /* PREFIX_VEX_0F3A5E */
6232   {
6233     { Bad_Opcode },
6234     { Bad_Opcode },
6235     { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6236   },
6237
6238   /* PREFIX_VEX_0F3A5F */
6239   {
6240     { Bad_Opcode },
6241     { Bad_Opcode },
6242     { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6243   },
6244
6245   /* PREFIX_VEX_0F3A60 */
6246   {
6247     { Bad_Opcode },
6248     { Bad_Opcode },
6249     { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6250     { Bad_Opcode },
6251   },
6252
6253   /* PREFIX_VEX_0F3A61 */
6254   {
6255     { Bad_Opcode },
6256     { Bad_Opcode },
6257     { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6258   },
6259
6260   /* PREFIX_VEX_0F3A62 */
6261   {
6262     { Bad_Opcode },
6263     { Bad_Opcode },
6264     { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6265   },
6266
6267   /* PREFIX_VEX_0F3A63 */
6268   {
6269     { Bad_Opcode },
6270     { Bad_Opcode },
6271     { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6272   },
6273
6274   /* PREFIX_VEX_0F3A68 */
6275   {
6276     { Bad_Opcode },
6277     { Bad_Opcode },
6278     { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6279   },
6280
6281   /* PREFIX_VEX_0F3A69 */
6282   {
6283     { Bad_Opcode },
6284     { Bad_Opcode },
6285     { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6286   },
6287
6288   /* PREFIX_VEX_0F3A6A */
6289   {
6290     { Bad_Opcode },
6291     { Bad_Opcode },
6292     { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6293   },
6294
6295   /* PREFIX_VEX_0F3A6B */
6296   {
6297     { Bad_Opcode },
6298     { Bad_Opcode },
6299     { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6300   },
6301
6302   /* PREFIX_VEX_0F3A6C */
6303   {
6304     { Bad_Opcode },
6305     { Bad_Opcode },
6306     { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6307   },
6308
6309   /* PREFIX_VEX_0F3A6D */
6310   {
6311     { Bad_Opcode },
6312     { Bad_Opcode },
6313     { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6314   },
6315
6316   /* PREFIX_VEX_0F3A6E */
6317   {
6318     { Bad_Opcode },
6319     { Bad_Opcode },
6320     { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6321   },
6322
6323   /* PREFIX_VEX_0F3A6F */
6324   {
6325     { Bad_Opcode },
6326     { Bad_Opcode },
6327     { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6328   },
6329
6330   /* PREFIX_VEX_0F3A78 */
6331   {
6332     { Bad_Opcode },
6333     { Bad_Opcode },
6334     { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6335   },
6336
6337   /* PREFIX_VEX_0F3A79 */
6338   {
6339     { Bad_Opcode },
6340     { Bad_Opcode },
6341     { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6342   },
6343
6344   /* PREFIX_VEX_0F3A7A */
6345   {
6346     { Bad_Opcode },
6347     { Bad_Opcode },
6348     { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6349   },
6350
6351   /* PREFIX_VEX_0F3A7B */
6352   {
6353     { Bad_Opcode },
6354     { Bad_Opcode },
6355     { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6356   },
6357
6358   /* PREFIX_VEX_0F3A7C */
6359   {
6360     { Bad_Opcode },
6361     { Bad_Opcode },
6362     { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6363     { Bad_Opcode },
6364   },
6365
6366   /* PREFIX_VEX_0F3A7D */
6367   {
6368     { Bad_Opcode },
6369     { Bad_Opcode },
6370     { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6371   },
6372
6373   /* PREFIX_VEX_0F3A7E */
6374   {
6375     { Bad_Opcode },
6376     { Bad_Opcode },
6377     { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6378   },
6379
6380   /* PREFIX_VEX_0F3A7F */
6381   {
6382     { Bad_Opcode },
6383     { Bad_Opcode },
6384     { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6385   },
6386
6387   /* PREFIX_VEX_0F3ADF */
6388   {
6389     { Bad_Opcode },
6390     { Bad_Opcode },
6391     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6392   },
6393
6394   /* PREFIX_VEX_0F3AF0 */
6395   {
6396     { Bad_Opcode },
6397     { Bad_Opcode },
6398     { Bad_Opcode },
6399     { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6400   },
6401
6402 #define NEED_PREFIX_TABLE
6403 #include "i386-dis-evex.h"
6404 #undef NEED_PREFIX_TABLE
6405 };
6406
6407 static const struct dis386 x86_64_table[][2] = {
6408   /* X86_64_06 */
6409   {
6410     { "pushP", { es } },
6411   },
6412
6413   /* X86_64_07 */
6414   {
6415     { "popP", { es } },
6416   },
6417
6418   /* X86_64_0D */
6419   {
6420     { "pushP", { cs } },
6421   },
6422
6423   /* X86_64_16 */
6424   {
6425     { "pushP", { ss } },
6426   },
6427
6428   /* X86_64_17 */
6429   {
6430     { "popP", { ss } },
6431   },
6432
6433   /* X86_64_1E */
6434   {
6435     { "pushP", { ds } },
6436   },
6437
6438   /* X86_64_1F */
6439   {
6440     { "popP", { ds } },
6441   },
6442
6443   /* X86_64_27 */
6444   {
6445     { "daa", { XX } },
6446   },
6447
6448   /* X86_64_2F */
6449   {
6450     { "das", { XX } },
6451   },
6452
6453   /* X86_64_37 */
6454   {
6455     { "aaa", { XX } },
6456   },
6457
6458   /* X86_64_3F */
6459   {
6460     { "aas", { XX } },
6461   },
6462
6463   /* X86_64_60 */
6464   {
6465     { "pushaP", { XX } },
6466   },
6467
6468   /* X86_64_61 */
6469   {
6470     { "popaP", { XX } },
6471   },
6472
6473   /* X86_64_62 */
6474   {
6475     { MOD_TABLE (MOD_62_32BIT) },
6476     { EVEX_TABLE (EVEX_0F) },
6477   },
6478
6479   /* X86_64_63 */
6480   {
6481     { "arpl", { Ew, Gw } },
6482     { "movs{lq|xd}", { Gv, Ed } },
6483   },
6484
6485   /* X86_64_6D */
6486   {
6487     { "ins{R|}", { Yzr, indirDX } },
6488     { "ins{G|}", { Yzr, indirDX } },
6489   },
6490
6491   /* X86_64_6F */
6492   {
6493     { "outs{R|}", { indirDXr, Xz } },
6494     { "outs{G|}", { indirDXr, Xz } },
6495   },
6496
6497   /* X86_64_9A */
6498   {
6499     { "Jcall{T|}", { Ap } },
6500   },
6501
6502   /* X86_64_C4 */
6503   {
6504     { MOD_TABLE (MOD_C4_32BIT) },
6505     { VEX_C4_TABLE (VEX_0F) },
6506   },
6507
6508   /* X86_64_C5 */
6509   {
6510     { MOD_TABLE (MOD_C5_32BIT) },
6511     { VEX_C5_TABLE (VEX_0F) },
6512   },
6513
6514   /* X86_64_CE */
6515   {
6516     { "into", { XX } },
6517   },
6518
6519   /* X86_64_D4 */
6520   {
6521     { "aam", { Ib } },
6522   },
6523
6524   /* X86_64_D5 */
6525   {
6526     { "aad", { Ib } },
6527   },
6528
6529   /* X86_64_EA */
6530   {
6531     { "Jjmp{T|}", { Ap } },
6532   },
6533
6534   /* X86_64_0F01_REG_0 */
6535   {
6536     { "sgdt{Q|IQ}", { M } },
6537     { "sgdt", { M } },
6538   },
6539
6540   /* X86_64_0F01_REG_1 */
6541   {
6542     { "sidt{Q|IQ}", { M } },
6543     { "sidt", { M } },
6544   },
6545
6546   /* X86_64_0F01_REG_2 */
6547   {
6548     { "lgdt{Q|Q}", { M } },
6549     { "lgdt", { M } },
6550   },
6551
6552   /* X86_64_0F01_REG_3 */
6553   {
6554     { "lidt{Q|Q}", { M } },
6555     { "lidt", { M } },
6556   },
6557 };
6558
6559 static const struct dis386 three_byte_table[][256] = {
6560
6561   /* THREE_BYTE_0F38 */
6562   {
6563     /* 00 */
6564     { "pshufb",         { MX, EM } },
6565     { "phaddw",         { MX, EM } },
6566     { "phaddd",         { MX, EM } },
6567     { "phaddsw",        { MX, EM } },
6568     { "pmaddubsw",      { MX, EM } },
6569     { "phsubw",         { MX, EM } },
6570     { "phsubd",         { MX, EM } },
6571     { "phsubsw",        { MX, EM } },
6572     /* 08 */
6573     { "psignb",         { MX, EM } },
6574     { "psignw",         { MX, EM } },
6575     { "psignd",         { MX, EM } },
6576     { "pmulhrsw",       { MX, EM } },
6577     { Bad_Opcode },
6578     { Bad_Opcode },
6579     { Bad_Opcode },
6580     { Bad_Opcode },
6581     /* 10 */
6582     { PREFIX_TABLE (PREFIX_0F3810) },
6583     { Bad_Opcode },
6584     { Bad_Opcode },
6585     { Bad_Opcode },
6586     { PREFIX_TABLE (PREFIX_0F3814) },
6587     { PREFIX_TABLE (PREFIX_0F3815) },
6588     { Bad_Opcode },
6589     { PREFIX_TABLE (PREFIX_0F3817) },
6590     /* 18 */
6591     { Bad_Opcode },
6592     { Bad_Opcode },
6593     { Bad_Opcode },
6594     { Bad_Opcode },
6595     { "pabsb",          { MX, EM } },
6596     { "pabsw",          { MX, EM } },
6597     { "pabsd",          { MX, EM } },
6598     { Bad_Opcode },
6599     /* 20 */
6600     { PREFIX_TABLE (PREFIX_0F3820) },
6601     { PREFIX_TABLE (PREFIX_0F3821) },
6602     { PREFIX_TABLE (PREFIX_0F3822) },
6603     { PREFIX_TABLE (PREFIX_0F3823) },
6604     { PREFIX_TABLE (PREFIX_0F3824) },
6605     { PREFIX_TABLE (PREFIX_0F3825) },
6606     { Bad_Opcode },
6607     { Bad_Opcode },
6608     /* 28 */
6609     { PREFIX_TABLE (PREFIX_0F3828) },
6610     { PREFIX_TABLE (PREFIX_0F3829) },
6611     { PREFIX_TABLE (PREFIX_0F382A) },
6612     { PREFIX_TABLE (PREFIX_0F382B) },
6613     { Bad_Opcode },
6614     { Bad_Opcode },
6615     { Bad_Opcode },
6616     { Bad_Opcode },
6617     /* 30 */
6618     { PREFIX_TABLE (PREFIX_0F3830) },
6619     { PREFIX_TABLE (PREFIX_0F3831) },
6620     { PREFIX_TABLE (PREFIX_0F3832) },
6621     { PREFIX_TABLE (PREFIX_0F3833) },
6622     { PREFIX_TABLE (PREFIX_0F3834) },
6623     { PREFIX_TABLE (PREFIX_0F3835) },
6624     { Bad_Opcode },
6625     { PREFIX_TABLE (PREFIX_0F3837) },
6626     /* 38 */
6627     { PREFIX_TABLE (PREFIX_0F3838) },
6628     { PREFIX_TABLE (PREFIX_0F3839) },
6629     { PREFIX_TABLE (PREFIX_0F383A) },
6630     { PREFIX_TABLE (PREFIX_0F383B) },
6631     { PREFIX_TABLE (PREFIX_0F383C) },
6632     { PREFIX_TABLE (PREFIX_0F383D) },
6633     { PREFIX_TABLE (PREFIX_0F383E) },
6634     { PREFIX_TABLE (PREFIX_0F383F) },
6635     /* 40 */
6636     { PREFIX_TABLE (PREFIX_0F3840) },
6637     { PREFIX_TABLE (PREFIX_0F3841) },
6638     { Bad_Opcode },
6639     { Bad_Opcode },
6640     { Bad_Opcode },
6641     { Bad_Opcode },
6642     { Bad_Opcode },
6643     { Bad_Opcode },
6644     /* 48 */
6645     { Bad_Opcode },
6646     { Bad_Opcode },
6647     { Bad_Opcode },
6648     { Bad_Opcode },
6649     { Bad_Opcode },
6650     { Bad_Opcode },
6651     { Bad_Opcode },
6652     { Bad_Opcode },
6653     /* 50 */
6654     { Bad_Opcode },
6655     { Bad_Opcode },
6656     { Bad_Opcode },
6657     { Bad_Opcode },
6658     { Bad_Opcode },
6659     { Bad_Opcode },
6660     { Bad_Opcode },
6661     { Bad_Opcode },
6662     /* 58 */
6663     { Bad_Opcode },
6664     { Bad_Opcode },
6665     { Bad_Opcode },
6666     { Bad_Opcode },
6667     { Bad_Opcode },
6668     { Bad_Opcode },
6669     { Bad_Opcode },
6670     { Bad_Opcode },
6671     /* 60 */
6672     { Bad_Opcode },
6673     { Bad_Opcode },
6674     { Bad_Opcode },
6675     { Bad_Opcode },
6676     { Bad_Opcode },
6677     { Bad_Opcode },
6678     { Bad_Opcode },
6679     { Bad_Opcode },
6680     /* 68 */
6681     { Bad_Opcode },
6682     { Bad_Opcode },
6683     { Bad_Opcode },
6684     { Bad_Opcode },
6685     { Bad_Opcode },
6686     { Bad_Opcode },
6687     { Bad_Opcode },
6688     { Bad_Opcode },
6689     /* 70 */
6690     { Bad_Opcode },
6691     { Bad_Opcode },
6692     { Bad_Opcode },
6693     { Bad_Opcode },
6694     { Bad_Opcode },
6695     { Bad_Opcode },
6696     { Bad_Opcode },
6697     { Bad_Opcode },
6698     /* 78 */
6699     { Bad_Opcode },
6700     { Bad_Opcode },
6701     { Bad_Opcode },
6702     { Bad_Opcode },
6703     { Bad_Opcode },
6704     { Bad_Opcode },
6705     { Bad_Opcode },
6706     { Bad_Opcode },
6707     /* 80 */
6708     { PREFIX_TABLE (PREFIX_0F3880) },
6709     { PREFIX_TABLE (PREFIX_0F3881) },
6710     { PREFIX_TABLE (PREFIX_0F3882) },
6711     { Bad_Opcode },
6712     { Bad_Opcode },
6713     { Bad_Opcode },
6714     { Bad_Opcode },
6715     { Bad_Opcode },
6716     /* 88 */
6717     { Bad_Opcode },
6718     { Bad_Opcode },
6719     { Bad_Opcode },
6720     { Bad_Opcode },
6721     { Bad_Opcode },
6722     { Bad_Opcode },
6723     { Bad_Opcode },
6724     { Bad_Opcode },
6725     /* 90 */
6726     { Bad_Opcode },
6727     { Bad_Opcode },
6728     { Bad_Opcode },
6729     { Bad_Opcode },
6730     { Bad_Opcode },
6731     { Bad_Opcode },
6732     { Bad_Opcode },
6733     { Bad_Opcode },
6734     /* 98 */
6735     { Bad_Opcode },
6736     { Bad_Opcode },
6737     { Bad_Opcode },
6738     { Bad_Opcode },
6739     { Bad_Opcode },
6740     { Bad_Opcode },
6741     { Bad_Opcode },
6742     { Bad_Opcode },
6743     /* a0 */
6744     { Bad_Opcode },
6745     { Bad_Opcode },
6746     { Bad_Opcode },
6747     { Bad_Opcode },
6748     { Bad_Opcode },
6749     { Bad_Opcode },
6750     { Bad_Opcode },
6751     { Bad_Opcode },
6752     /* a8 */
6753     { Bad_Opcode },
6754     { Bad_Opcode },
6755     { Bad_Opcode },
6756     { Bad_Opcode },
6757     { Bad_Opcode },
6758     { Bad_Opcode },
6759     { Bad_Opcode },
6760     { Bad_Opcode },
6761     /* b0 */
6762     { Bad_Opcode },
6763     { Bad_Opcode },
6764     { Bad_Opcode },
6765     { Bad_Opcode },
6766     { Bad_Opcode },
6767     { Bad_Opcode },
6768     { Bad_Opcode },
6769     { Bad_Opcode },
6770     /* b8 */
6771     { Bad_Opcode },
6772     { Bad_Opcode },
6773     { Bad_Opcode },
6774     { Bad_Opcode },
6775     { Bad_Opcode },
6776     { Bad_Opcode },
6777     { Bad_Opcode },
6778     { Bad_Opcode },
6779     /* c0 */
6780     { Bad_Opcode },
6781     { Bad_Opcode },
6782     { Bad_Opcode },
6783     { Bad_Opcode },
6784     { Bad_Opcode },
6785     { Bad_Opcode },
6786     { Bad_Opcode },
6787     { Bad_Opcode },
6788     /* c8 */
6789     { PREFIX_TABLE (PREFIX_0F38C8) },
6790     { PREFIX_TABLE (PREFIX_0F38C9) },
6791     { PREFIX_TABLE (PREFIX_0F38CA) },
6792     { PREFIX_TABLE (PREFIX_0F38CB) },
6793     { PREFIX_TABLE (PREFIX_0F38CC) },
6794     { PREFIX_TABLE (PREFIX_0F38CD) },
6795     { Bad_Opcode },
6796     { Bad_Opcode },
6797     /* d0 */
6798     { Bad_Opcode },
6799     { Bad_Opcode },
6800     { Bad_Opcode },
6801     { Bad_Opcode },
6802     { Bad_Opcode },
6803     { Bad_Opcode },
6804     { Bad_Opcode },
6805     { Bad_Opcode },
6806     /* d8 */
6807     { Bad_Opcode },
6808     { Bad_Opcode },
6809     { Bad_Opcode },
6810     { PREFIX_TABLE (PREFIX_0F38DB) },
6811     { PREFIX_TABLE (PREFIX_0F38DC) },
6812     { PREFIX_TABLE (PREFIX_0F38DD) },
6813     { PREFIX_TABLE (PREFIX_0F38DE) },
6814     { PREFIX_TABLE (PREFIX_0F38DF) },
6815     /* e0 */
6816     { Bad_Opcode },
6817     { Bad_Opcode },
6818     { Bad_Opcode },
6819     { Bad_Opcode },
6820     { Bad_Opcode },
6821     { Bad_Opcode },
6822     { Bad_Opcode },
6823     { Bad_Opcode },
6824     /* e8 */
6825     { Bad_Opcode },
6826     { Bad_Opcode },
6827     { Bad_Opcode },
6828     { Bad_Opcode },
6829     { Bad_Opcode },
6830     { Bad_Opcode },
6831     { Bad_Opcode },
6832     { Bad_Opcode },
6833     /* f0 */
6834     { PREFIX_TABLE (PREFIX_0F38F0) },
6835     { PREFIX_TABLE (PREFIX_0F38F1) },
6836     { Bad_Opcode },
6837     { Bad_Opcode },
6838     { Bad_Opcode },
6839     { Bad_Opcode },
6840     { PREFIX_TABLE (PREFIX_0F38F6) },
6841     { Bad_Opcode },
6842     /* f8 */
6843     { Bad_Opcode },
6844     { Bad_Opcode },
6845     { Bad_Opcode },
6846     { Bad_Opcode },
6847     { Bad_Opcode },
6848     { Bad_Opcode },
6849     { Bad_Opcode },
6850     { Bad_Opcode },
6851   },
6852   /* THREE_BYTE_0F3A */
6853   {
6854     /* 00 */
6855     { Bad_Opcode },
6856     { Bad_Opcode },
6857     { Bad_Opcode },
6858     { Bad_Opcode },
6859     { Bad_Opcode },
6860     { Bad_Opcode },
6861     { Bad_Opcode },
6862     { Bad_Opcode },
6863     /* 08 */
6864     { PREFIX_TABLE (PREFIX_0F3A08) },
6865     { PREFIX_TABLE (PREFIX_0F3A09) },
6866     { PREFIX_TABLE (PREFIX_0F3A0A) },
6867     { PREFIX_TABLE (PREFIX_0F3A0B) },
6868     { PREFIX_TABLE (PREFIX_0F3A0C) },
6869     { PREFIX_TABLE (PREFIX_0F3A0D) },
6870     { PREFIX_TABLE (PREFIX_0F3A0E) },
6871     { "palignr",        { MX, EM, Ib } },
6872     /* 10 */
6873     { Bad_Opcode },
6874     { Bad_Opcode },
6875     { Bad_Opcode },
6876     { Bad_Opcode },
6877     { PREFIX_TABLE (PREFIX_0F3A14) },
6878     { PREFIX_TABLE (PREFIX_0F3A15) },
6879     { PREFIX_TABLE (PREFIX_0F3A16) },
6880     { PREFIX_TABLE (PREFIX_0F3A17) },
6881     /* 18 */
6882     { Bad_Opcode },
6883     { Bad_Opcode },
6884     { Bad_Opcode },
6885     { Bad_Opcode },
6886     { Bad_Opcode },
6887     { Bad_Opcode },
6888     { Bad_Opcode },
6889     { Bad_Opcode },
6890     /* 20 */
6891     { PREFIX_TABLE (PREFIX_0F3A20) },
6892     { PREFIX_TABLE (PREFIX_0F3A21) },
6893     { PREFIX_TABLE (PREFIX_0F3A22) },
6894     { Bad_Opcode },
6895     { Bad_Opcode },
6896     { Bad_Opcode },
6897     { Bad_Opcode },
6898     { Bad_Opcode },
6899     /* 28 */
6900     { Bad_Opcode },
6901     { Bad_Opcode },
6902     { Bad_Opcode },
6903     { Bad_Opcode },
6904     { Bad_Opcode },
6905     { Bad_Opcode },
6906     { Bad_Opcode },
6907     { Bad_Opcode },
6908     /* 30 */
6909     { Bad_Opcode },
6910     { Bad_Opcode },
6911     { Bad_Opcode },
6912     { Bad_Opcode },
6913     { Bad_Opcode },
6914     { Bad_Opcode },
6915     { Bad_Opcode },
6916     { Bad_Opcode },
6917     /* 38 */
6918     { Bad_Opcode },
6919     { Bad_Opcode },
6920     { Bad_Opcode },
6921     { Bad_Opcode },
6922     { Bad_Opcode },
6923     { Bad_Opcode },
6924     { Bad_Opcode },
6925     { Bad_Opcode },
6926     /* 40 */
6927     { PREFIX_TABLE (PREFIX_0F3A40) },
6928     { PREFIX_TABLE (PREFIX_0F3A41) },
6929     { PREFIX_TABLE (PREFIX_0F3A42) },
6930     { Bad_Opcode },
6931     { PREFIX_TABLE (PREFIX_0F3A44) },
6932     { Bad_Opcode },
6933     { Bad_Opcode },
6934     { Bad_Opcode },
6935     /* 48 */
6936     { Bad_Opcode },
6937     { Bad_Opcode },
6938     { Bad_Opcode },
6939     { Bad_Opcode },
6940     { Bad_Opcode },
6941     { Bad_Opcode },
6942     { Bad_Opcode },
6943     { Bad_Opcode },
6944     /* 50 */
6945     { Bad_Opcode },
6946     { Bad_Opcode },
6947     { Bad_Opcode },
6948     { Bad_Opcode },
6949     { Bad_Opcode },
6950     { Bad_Opcode },
6951     { Bad_Opcode },
6952     { Bad_Opcode },
6953     /* 58 */
6954     { Bad_Opcode },
6955     { Bad_Opcode },
6956     { Bad_Opcode },
6957     { Bad_Opcode },
6958     { Bad_Opcode },
6959     { Bad_Opcode },
6960     { Bad_Opcode },
6961     { Bad_Opcode },
6962     /* 60 */
6963     { PREFIX_TABLE (PREFIX_0F3A60) },
6964     { PREFIX_TABLE (PREFIX_0F3A61) },
6965     { PREFIX_TABLE (PREFIX_0F3A62) },
6966     { PREFIX_TABLE (PREFIX_0F3A63) },
6967     { Bad_Opcode },
6968     { Bad_Opcode },
6969     { Bad_Opcode },
6970     { Bad_Opcode },
6971     /* 68 */
6972     { Bad_Opcode },
6973     { Bad_Opcode },
6974     { Bad_Opcode },
6975     { Bad_Opcode },
6976     { Bad_Opcode },
6977     { Bad_Opcode },
6978     { Bad_Opcode },
6979     { Bad_Opcode },
6980     /* 70 */
6981     { Bad_Opcode },
6982     { Bad_Opcode },
6983     { Bad_Opcode },
6984     { Bad_Opcode },
6985     { Bad_Opcode },
6986     { Bad_Opcode },
6987     { Bad_Opcode },
6988     { Bad_Opcode },
6989     /* 78 */
6990     { Bad_Opcode },
6991     { Bad_Opcode },
6992     { Bad_Opcode },
6993     { Bad_Opcode },
6994     { Bad_Opcode },
6995     { Bad_Opcode },
6996     { Bad_Opcode },
6997     { Bad_Opcode },
6998     /* 80 */
6999     { Bad_Opcode },
7000     { Bad_Opcode },
7001     { Bad_Opcode },
7002     { Bad_Opcode },
7003     { Bad_Opcode },
7004     { Bad_Opcode },
7005     { Bad_Opcode },
7006     { Bad_Opcode },
7007     /* 88 */
7008     { Bad_Opcode },
7009     { Bad_Opcode },
7010     { Bad_Opcode },
7011     { Bad_Opcode },
7012     { Bad_Opcode },
7013     { Bad_Opcode },
7014     { Bad_Opcode },
7015     { Bad_Opcode },
7016     /* 90 */
7017     { Bad_Opcode },
7018     { Bad_Opcode },
7019     { Bad_Opcode },
7020     { Bad_Opcode },
7021     { Bad_Opcode },
7022     { Bad_Opcode },
7023     { Bad_Opcode },
7024     { Bad_Opcode },
7025     /* 98 */
7026     { Bad_Opcode },
7027     { Bad_Opcode },
7028     { Bad_Opcode },
7029     { Bad_Opcode },
7030     { Bad_Opcode },
7031     { Bad_Opcode },
7032     { Bad_Opcode },
7033     { Bad_Opcode },
7034     /* a0 */
7035     { Bad_Opcode },
7036     { Bad_Opcode },
7037     { Bad_Opcode },
7038     { Bad_Opcode },
7039     { Bad_Opcode },
7040     { Bad_Opcode },
7041     { Bad_Opcode },
7042     { Bad_Opcode },
7043     /* a8 */
7044     { Bad_Opcode },
7045     { Bad_Opcode },
7046     { Bad_Opcode },
7047     { Bad_Opcode },
7048     { Bad_Opcode },
7049     { Bad_Opcode },
7050     { Bad_Opcode },
7051     { Bad_Opcode },
7052     /* b0 */
7053     { Bad_Opcode },
7054     { Bad_Opcode },
7055     { Bad_Opcode },
7056     { Bad_Opcode },
7057     { Bad_Opcode },
7058     { Bad_Opcode },
7059     { Bad_Opcode },
7060     { Bad_Opcode },
7061     /* b8 */
7062     { Bad_Opcode },
7063     { Bad_Opcode },
7064     { Bad_Opcode },
7065     { Bad_Opcode },
7066     { Bad_Opcode },
7067     { Bad_Opcode },
7068     { Bad_Opcode },
7069     { Bad_Opcode },
7070     /* c0 */
7071     { Bad_Opcode },
7072     { Bad_Opcode },
7073     { Bad_Opcode },
7074     { Bad_Opcode },
7075     { Bad_Opcode },
7076     { Bad_Opcode },
7077     { Bad_Opcode },
7078     { Bad_Opcode },
7079     /* c8 */
7080     { Bad_Opcode },
7081     { Bad_Opcode },
7082     { Bad_Opcode },
7083     { Bad_Opcode },
7084     { PREFIX_TABLE (PREFIX_0F3ACC) },
7085     { Bad_Opcode },
7086     { Bad_Opcode },
7087     { Bad_Opcode },
7088     /* d0 */
7089     { Bad_Opcode },
7090     { Bad_Opcode },
7091     { Bad_Opcode },
7092     { Bad_Opcode },
7093     { Bad_Opcode },
7094     { Bad_Opcode },
7095     { Bad_Opcode },
7096     { Bad_Opcode },
7097     /* d8 */
7098     { Bad_Opcode },
7099     { Bad_Opcode },
7100     { Bad_Opcode },
7101     { Bad_Opcode },
7102     { Bad_Opcode },
7103     { Bad_Opcode },
7104     { Bad_Opcode },
7105     { PREFIX_TABLE (PREFIX_0F3ADF) },
7106     /* e0 */
7107     { Bad_Opcode },
7108     { Bad_Opcode },
7109     { Bad_Opcode },
7110     { Bad_Opcode },
7111     { Bad_Opcode },
7112     { Bad_Opcode },
7113     { Bad_Opcode },
7114     { Bad_Opcode },
7115     /* e8 */
7116     { Bad_Opcode },
7117     { Bad_Opcode },
7118     { Bad_Opcode },
7119     { Bad_Opcode },
7120     { Bad_Opcode },
7121     { Bad_Opcode },
7122     { Bad_Opcode },
7123     { Bad_Opcode },
7124     /* f0 */
7125     { Bad_Opcode },
7126     { Bad_Opcode },
7127     { Bad_Opcode },
7128     { Bad_Opcode },
7129     { Bad_Opcode },
7130     { Bad_Opcode },
7131     { Bad_Opcode },
7132     { Bad_Opcode },
7133     /* f8 */
7134     { Bad_Opcode },
7135     { Bad_Opcode },
7136     { Bad_Opcode },
7137     { Bad_Opcode },
7138     { Bad_Opcode },
7139     { Bad_Opcode },
7140     { Bad_Opcode },
7141     { Bad_Opcode },
7142   },
7143
7144   /* THREE_BYTE_0F7A */
7145   {
7146     /* 00 */
7147     { Bad_Opcode },
7148     { Bad_Opcode },
7149     { Bad_Opcode },
7150     { Bad_Opcode },
7151     { Bad_Opcode },
7152     { Bad_Opcode },
7153     { Bad_Opcode },
7154     { Bad_Opcode },
7155     /* 08 */
7156     { Bad_Opcode },
7157     { Bad_Opcode },
7158     { Bad_Opcode },
7159     { Bad_Opcode },
7160     { Bad_Opcode },
7161     { Bad_Opcode },
7162     { Bad_Opcode },
7163     { Bad_Opcode },
7164     /* 10 */
7165     { Bad_Opcode },
7166     { Bad_Opcode },
7167     { Bad_Opcode },
7168     { Bad_Opcode },
7169     { Bad_Opcode },
7170     { Bad_Opcode },
7171     { Bad_Opcode },
7172     { Bad_Opcode },
7173     /* 18 */
7174     { Bad_Opcode },
7175     { Bad_Opcode },
7176     { Bad_Opcode },
7177     { Bad_Opcode },
7178     { Bad_Opcode },
7179     { Bad_Opcode },
7180     { Bad_Opcode },
7181     { Bad_Opcode },
7182     /* 20 */
7183     { "ptest",          { XX } },
7184     { Bad_Opcode },
7185     { Bad_Opcode },
7186     { Bad_Opcode },
7187     { Bad_Opcode },
7188     { Bad_Opcode },
7189     { Bad_Opcode },
7190     { Bad_Opcode },
7191     /* 28 */
7192     { Bad_Opcode },
7193     { Bad_Opcode },
7194     { Bad_Opcode },
7195     { Bad_Opcode },
7196     { Bad_Opcode },
7197     { Bad_Opcode },
7198     { Bad_Opcode },
7199     { Bad_Opcode },
7200     /* 30 */
7201     { Bad_Opcode },
7202     { Bad_Opcode },
7203     { Bad_Opcode },
7204     { Bad_Opcode },
7205     { Bad_Opcode },
7206     { Bad_Opcode },
7207     { Bad_Opcode },
7208     { Bad_Opcode },
7209     /* 38 */
7210     { Bad_Opcode },
7211     { Bad_Opcode },
7212     { Bad_Opcode },
7213     { Bad_Opcode },
7214     { Bad_Opcode },
7215     { Bad_Opcode },
7216     { Bad_Opcode },
7217     { Bad_Opcode },
7218     /* 40 */
7219     { Bad_Opcode },
7220     { "phaddbw",        { XM, EXq } },
7221     { "phaddbd",        { XM, EXq } },
7222     { "phaddbq",        { XM, EXq } },
7223     { Bad_Opcode },
7224     { Bad_Opcode },
7225     { "phaddwd",        { XM, EXq } },
7226     { "phaddwq",        { XM, EXq } },
7227     /* 48 */
7228     { Bad_Opcode },
7229     { Bad_Opcode },
7230     { Bad_Opcode },
7231     { "phadddq",        { XM, EXq } },
7232     { Bad_Opcode },
7233     { Bad_Opcode },
7234     { Bad_Opcode },
7235     { Bad_Opcode },
7236     /* 50 */
7237     { Bad_Opcode },
7238     { "phaddubw",       { XM, EXq } },
7239     { "phaddubd",       { XM, EXq } },
7240     { "phaddubq",       { XM, EXq } },
7241     { Bad_Opcode },
7242     { Bad_Opcode },
7243     { "phadduwd",       { XM, EXq } },
7244     { "phadduwq",       { XM, EXq } },
7245     /* 58 */
7246     { Bad_Opcode },
7247     { Bad_Opcode },
7248     { Bad_Opcode },
7249     { "phaddudq",       { XM, EXq } },
7250     { Bad_Opcode },
7251     { Bad_Opcode },
7252     { Bad_Opcode },
7253     { Bad_Opcode },
7254     /* 60 */
7255     { Bad_Opcode },
7256     { "phsubbw",        { XM, EXq } },
7257     { "phsubbd",        { XM, EXq } },
7258     { "phsubbq",        { XM, EXq } },
7259     { Bad_Opcode },
7260     { Bad_Opcode },
7261     { Bad_Opcode },
7262     { Bad_Opcode },
7263     /* 68 */
7264     { Bad_Opcode },
7265     { Bad_Opcode },
7266     { Bad_Opcode },
7267     { Bad_Opcode },
7268     { Bad_Opcode },
7269     { Bad_Opcode },
7270     { Bad_Opcode },
7271     { Bad_Opcode },
7272     /* 70 */
7273     { Bad_Opcode },
7274     { Bad_Opcode },
7275     { Bad_Opcode },
7276     { Bad_Opcode },
7277     { Bad_Opcode },
7278     { Bad_Opcode },
7279     { Bad_Opcode },
7280     { Bad_Opcode },
7281     /* 78 */
7282     { Bad_Opcode },
7283     { Bad_Opcode },
7284     { Bad_Opcode },
7285     { Bad_Opcode },
7286     { Bad_Opcode },
7287     { Bad_Opcode },
7288     { Bad_Opcode },
7289     { Bad_Opcode },
7290     /* 80 */
7291     { Bad_Opcode },
7292     { Bad_Opcode },
7293     { Bad_Opcode },
7294     { Bad_Opcode },
7295     { Bad_Opcode },
7296     { Bad_Opcode },
7297     { Bad_Opcode },
7298     { Bad_Opcode },
7299     /* 88 */
7300     { Bad_Opcode },
7301     { Bad_Opcode },
7302     { Bad_Opcode },
7303     { Bad_Opcode },
7304     { Bad_Opcode },
7305     { Bad_Opcode },
7306     { Bad_Opcode },
7307     { Bad_Opcode },
7308     /* 90 */
7309     { Bad_Opcode },
7310     { Bad_Opcode },
7311     { Bad_Opcode },
7312     { Bad_Opcode },
7313     { Bad_Opcode },
7314     { Bad_Opcode },
7315     { Bad_Opcode },
7316     { Bad_Opcode },
7317     /* 98 */
7318     { Bad_Opcode },
7319     { Bad_Opcode },
7320     { Bad_Opcode },
7321     { Bad_Opcode },
7322     { Bad_Opcode },
7323     { Bad_Opcode },
7324     { Bad_Opcode },
7325     { Bad_Opcode },
7326     /* a0 */
7327     { Bad_Opcode },
7328     { Bad_Opcode },
7329     { Bad_Opcode },
7330     { Bad_Opcode },
7331     { Bad_Opcode },
7332     { Bad_Opcode },
7333     { Bad_Opcode },
7334     { Bad_Opcode },
7335     /* a8 */
7336     { Bad_Opcode },
7337     { Bad_Opcode },
7338     { Bad_Opcode },
7339     { Bad_Opcode },
7340     { Bad_Opcode },
7341     { Bad_Opcode },
7342     { Bad_Opcode },
7343     { Bad_Opcode },
7344     /* b0 */
7345     { Bad_Opcode },
7346     { Bad_Opcode },
7347     { Bad_Opcode },
7348     { Bad_Opcode },
7349     { Bad_Opcode },
7350     { Bad_Opcode },
7351     { Bad_Opcode },
7352     { Bad_Opcode },
7353     /* b8 */
7354     { Bad_Opcode },
7355     { Bad_Opcode },
7356     { Bad_Opcode },
7357     { Bad_Opcode },
7358     { Bad_Opcode },
7359     { Bad_Opcode },
7360     { Bad_Opcode },
7361     { Bad_Opcode },
7362     /* c0 */
7363     { Bad_Opcode },
7364     { Bad_Opcode },
7365     { Bad_Opcode },
7366     { Bad_Opcode },
7367     { Bad_Opcode },
7368     { Bad_Opcode },
7369     { Bad_Opcode },
7370     { Bad_Opcode },
7371     /* c8 */
7372     { Bad_Opcode },
7373     { Bad_Opcode },
7374     { Bad_Opcode },
7375     { Bad_Opcode },
7376     { Bad_Opcode },
7377     { Bad_Opcode },
7378     { Bad_Opcode },
7379     { Bad_Opcode },
7380     /* d0 */
7381     { Bad_Opcode },
7382     { Bad_Opcode },
7383     { Bad_Opcode },
7384     { Bad_Opcode },
7385     { Bad_Opcode },
7386     { Bad_Opcode },
7387     { Bad_Opcode },
7388     { Bad_Opcode },
7389     /* d8 */
7390     { Bad_Opcode },
7391     { Bad_Opcode },
7392     { Bad_Opcode },
7393     { Bad_Opcode },
7394     { Bad_Opcode },
7395     { Bad_Opcode },
7396     { Bad_Opcode },
7397     { Bad_Opcode },
7398     /* e0 */
7399     { Bad_Opcode },
7400     { Bad_Opcode },
7401     { Bad_Opcode },
7402     { Bad_Opcode },
7403     { Bad_Opcode },
7404     { Bad_Opcode },
7405     { Bad_Opcode },
7406     { Bad_Opcode },
7407     /* e8 */
7408     { Bad_Opcode },
7409     { Bad_Opcode },
7410     { Bad_Opcode },
7411     { Bad_Opcode },
7412     { Bad_Opcode },
7413     { Bad_Opcode },
7414     { Bad_Opcode },
7415     { Bad_Opcode },
7416     /* f0 */
7417     { Bad_Opcode },
7418     { Bad_Opcode },
7419     { Bad_Opcode },
7420     { Bad_Opcode },
7421     { Bad_Opcode },
7422     { Bad_Opcode },
7423     { Bad_Opcode },
7424     { Bad_Opcode },
7425     /* f8 */
7426     { Bad_Opcode },
7427     { Bad_Opcode },
7428     { Bad_Opcode },
7429     { Bad_Opcode },
7430     { Bad_Opcode },
7431     { Bad_Opcode },
7432     { Bad_Opcode },
7433     { Bad_Opcode },
7434   },
7435 };
7436
7437 static const struct dis386 xop_table[][256] = {
7438   /* XOP_08 */
7439   {
7440     /* 00 */
7441     { Bad_Opcode },
7442     { Bad_Opcode },
7443     { Bad_Opcode },
7444     { Bad_Opcode },
7445     { Bad_Opcode },
7446     { Bad_Opcode },
7447     { Bad_Opcode },
7448     { Bad_Opcode },
7449     /* 08 */
7450     { Bad_Opcode },
7451     { Bad_Opcode },
7452     { Bad_Opcode },
7453     { Bad_Opcode },
7454     { Bad_Opcode },
7455     { Bad_Opcode },
7456     { Bad_Opcode },
7457     { Bad_Opcode },
7458     /* 10 */
7459     { Bad_Opcode },
7460     { Bad_Opcode },
7461     { Bad_Opcode },
7462     { Bad_Opcode },
7463     { Bad_Opcode },
7464     { Bad_Opcode },
7465     { Bad_Opcode },
7466     { Bad_Opcode },
7467     /* 18 */
7468     { Bad_Opcode },
7469     { Bad_Opcode },
7470     { Bad_Opcode },
7471     { Bad_Opcode },
7472     { Bad_Opcode },
7473     { Bad_Opcode },
7474     { Bad_Opcode },
7475     { Bad_Opcode },
7476     /* 20 */
7477     { Bad_Opcode },
7478     { Bad_Opcode },
7479     { Bad_Opcode },
7480     { Bad_Opcode },
7481     { Bad_Opcode },
7482     { Bad_Opcode },
7483     { Bad_Opcode },
7484     { Bad_Opcode },
7485     /* 28 */
7486     { Bad_Opcode },
7487     { Bad_Opcode },
7488     { Bad_Opcode },
7489     { Bad_Opcode },
7490     { Bad_Opcode },
7491     { Bad_Opcode },
7492     { Bad_Opcode },
7493     { Bad_Opcode },
7494     /* 30 */
7495     { Bad_Opcode },
7496     { Bad_Opcode },
7497     { Bad_Opcode },
7498     { Bad_Opcode },
7499     { Bad_Opcode },
7500     { Bad_Opcode },
7501     { Bad_Opcode },
7502     { Bad_Opcode },
7503     /* 38 */
7504     { Bad_Opcode },
7505     { Bad_Opcode },
7506     { Bad_Opcode },
7507     { Bad_Opcode },
7508     { Bad_Opcode },
7509     { Bad_Opcode },
7510     { Bad_Opcode },
7511     { Bad_Opcode },
7512     /* 40 */
7513     { Bad_Opcode },
7514     { Bad_Opcode },
7515     { Bad_Opcode },
7516     { Bad_Opcode },
7517     { Bad_Opcode },
7518     { Bad_Opcode },
7519     { Bad_Opcode },
7520     { Bad_Opcode },
7521     /* 48 */
7522     { Bad_Opcode },
7523     { Bad_Opcode },
7524     { Bad_Opcode },
7525     { Bad_Opcode },
7526     { Bad_Opcode },
7527     { Bad_Opcode },
7528     { Bad_Opcode },
7529     { Bad_Opcode },
7530     /* 50 */
7531     { Bad_Opcode },
7532     { Bad_Opcode },
7533     { Bad_Opcode },
7534     { Bad_Opcode },
7535     { Bad_Opcode },
7536     { Bad_Opcode },
7537     { Bad_Opcode },
7538     { Bad_Opcode },
7539     /* 58 */
7540     { Bad_Opcode },
7541     { Bad_Opcode },
7542     { Bad_Opcode },
7543     { Bad_Opcode },
7544     { Bad_Opcode },
7545     { Bad_Opcode },
7546     { Bad_Opcode },
7547     { Bad_Opcode },
7548     /* 60 */
7549     { Bad_Opcode },
7550     { Bad_Opcode },
7551     { Bad_Opcode },
7552     { Bad_Opcode },
7553     { Bad_Opcode },
7554     { Bad_Opcode },
7555     { Bad_Opcode },
7556     { Bad_Opcode },
7557     /* 68 */
7558     { Bad_Opcode },
7559     { Bad_Opcode },
7560     { Bad_Opcode },
7561     { Bad_Opcode },
7562     { Bad_Opcode },
7563     { Bad_Opcode },
7564     { Bad_Opcode },
7565     { Bad_Opcode },
7566     /* 70 */
7567     { Bad_Opcode },
7568     { Bad_Opcode },
7569     { Bad_Opcode },
7570     { Bad_Opcode },
7571     { Bad_Opcode },
7572     { Bad_Opcode },
7573     { Bad_Opcode },
7574     { Bad_Opcode },
7575     /* 78 */
7576     { Bad_Opcode },
7577     { Bad_Opcode },
7578     { Bad_Opcode },
7579     { Bad_Opcode },
7580     { Bad_Opcode },
7581     { Bad_Opcode },
7582     { Bad_Opcode },
7583     { Bad_Opcode },
7584     /* 80 */
7585     { Bad_Opcode },
7586     { Bad_Opcode },
7587     { Bad_Opcode },
7588     { Bad_Opcode },
7589     { Bad_Opcode },
7590     { "vpmacssww",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7591     { "vpmacsswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7592     { "vpmacssdql",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7593     /* 88 */
7594     { Bad_Opcode },
7595     { Bad_Opcode },
7596     { Bad_Opcode },
7597     { Bad_Opcode },
7598     { Bad_Opcode },
7599     { Bad_Opcode },
7600     { "vpmacssdd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7601     { "vpmacssdqh",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7602     /* 90 */
7603     { Bad_Opcode },
7604     { Bad_Opcode },
7605     { Bad_Opcode },
7606     { Bad_Opcode },
7607     { Bad_Opcode },
7608     { "vpmacsww",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7609     { "vpmacswd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7610     { "vpmacsdql",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7611     /* 98 */
7612     { Bad_Opcode },
7613     { Bad_Opcode },
7614     { Bad_Opcode },
7615     { Bad_Opcode },
7616     { Bad_Opcode },
7617     { Bad_Opcode },
7618     { "vpmacsdd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7619     { "vpmacsdqh",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7620     /* a0 */
7621     { Bad_Opcode },
7622     { Bad_Opcode },
7623     { "vpcmov",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7624     { "vpperm",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7625     { Bad_Opcode },
7626     { Bad_Opcode },
7627     { "vpmadcsswd",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7628     { Bad_Opcode },
7629     /* a8 */
7630     { Bad_Opcode },
7631     { Bad_Opcode },
7632     { Bad_Opcode },
7633     { Bad_Opcode },
7634     { Bad_Opcode },
7635     { Bad_Opcode },
7636     { Bad_Opcode },
7637     { Bad_Opcode },
7638     /* b0 */
7639     { Bad_Opcode },
7640     { Bad_Opcode },
7641     { Bad_Opcode },
7642     { Bad_Opcode },
7643     { Bad_Opcode },
7644     { Bad_Opcode },
7645     { "vpmadcswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7646     { Bad_Opcode },
7647     /* b8 */
7648     { Bad_Opcode },
7649     { Bad_Opcode },
7650     { Bad_Opcode },
7651     { Bad_Opcode },
7652     { Bad_Opcode },
7653     { Bad_Opcode },
7654     { Bad_Opcode },
7655     { Bad_Opcode },
7656     /* c0 */
7657     { "vprotb",         { XM, Vex_2src_1, Ib } },
7658     { "vprotw",         { XM, Vex_2src_1, Ib } },
7659     { "vprotd",         { XM, Vex_2src_1, Ib } },
7660     { "vprotq",         { XM, Vex_2src_1, Ib } },
7661     { Bad_Opcode },
7662     { Bad_Opcode },
7663     { Bad_Opcode },
7664     { Bad_Opcode },
7665     /* c8 */
7666     { Bad_Opcode },
7667     { Bad_Opcode },
7668     { Bad_Opcode },
7669     { Bad_Opcode },
7670     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
7671     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
7672     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
7673     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
7674     /* d0 */
7675     { Bad_Opcode },
7676     { Bad_Opcode },
7677     { Bad_Opcode },
7678     { Bad_Opcode },
7679     { Bad_Opcode },
7680     { Bad_Opcode },
7681     { Bad_Opcode },
7682     { Bad_Opcode },
7683     /* d8 */
7684     { Bad_Opcode },
7685     { Bad_Opcode },
7686     { Bad_Opcode },
7687     { Bad_Opcode },
7688     { Bad_Opcode },
7689     { Bad_Opcode },
7690     { Bad_Opcode },
7691     { Bad_Opcode },
7692     /* e0 */
7693     { Bad_Opcode },
7694     { Bad_Opcode },
7695     { Bad_Opcode },
7696     { Bad_Opcode },
7697     { Bad_Opcode },
7698     { Bad_Opcode },
7699     { Bad_Opcode },
7700     { Bad_Opcode },
7701     /* e8 */
7702     { Bad_Opcode },
7703     { Bad_Opcode },
7704     { Bad_Opcode },
7705     { Bad_Opcode },
7706     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
7707     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
7708     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
7709     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
7710     /* f0 */
7711     { Bad_Opcode },
7712     { Bad_Opcode },
7713     { Bad_Opcode },
7714     { Bad_Opcode },
7715     { Bad_Opcode },
7716     { Bad_Opcode },
7717     { Bad_Opcode },
7718     { Bad_Opcode },
7719     /* f8 */
7720     { Bad_Opcode },
7721     { Bad_Opcode },
7722     { Bad_Opcode },
7723     { Bad_Opcode },
7724     { Bad_Opcode },
7725     { Bad_Opcode },
7726     { Bad_Opcode },
7727     { Bad_Opcode },
7728   },
7729   /* XOP_09 */
7730   {
7731     /* 00 */
7732     { Bad_Opcode },
7733     { REG_TABLE (REG_XOP_TBM_01) },
7734     { REG_TABLE (REG_XOP_TBM_02) },
7735     { Bad_Opcode },
7736     { Bad_Opcode },
7737     { Bad_Opcode },
7738     { Bad_Opcode },
7739     { Bad_Opcode },
7740     /* 08 */
7741     { Bad_Opcode },
7742     { Bad_Opcode },
7743     { Bad_Opcode },
7744     { Bad_Opcode },
7745     { Bad_Opcode },
7746     { Bad_Opcode },
7747     { Bad_Opcode },
7748     { Bad_Opcode },
7749     /* 10 */
7750     { Bad_Opcode },
7751     { Bad_Opcode },
7752     { REG_TABLE (REG_XOP_LWPCB) },
7753     { Bad_Opcode },
7754     { Bad_Opcode },
7755     { Bad_Opcode },
7756     { Bad_Opcode },
7757     { Bad_Opcode },
7758     /* 18 */
7759     { Bad_Opcode },
7760     { Bad_Opcode },
7761     { Bad_Opcode },
7762     { Bad_Opcode },
7763     { Bad_Opcode },
7764     { Bad_Opcode },
7765     { Bad_Opcode },
7766     { Bad_Opcode },
7767     /* 20 */
7768     { Bad_Opcode },
7769     { Bad_Opcode },
7770     { Bad_Opcode },
7771     { Bad_Opcode },
7772     { Bad_Opcode },
7773     { Bad_Opcode },
7774     { Bad_Opcode },
7775     { Bad_Opcode },
7776     /* 28 */
7777     { Bad_Opcode },
7778     { Bad_Opcode },
7779     { Bad_Opcode },
7780     { Bad_Opcode },
7781     { Bad_Opcode },
7782     { Bad_Opcode },
7783     { Bad_Opcode },
7784     { Bad_Opcode },
7785     /* 30 */
7786     { Bad_Opcode },
7787     { Bad_Opcode },
7788     { Bad_Opcode },
7789     { Bad_Opcode },
7790     { Bad_Opcode },
7791     { Bad_Opcode },
7792     { Bad_Opcode },
7793     { Bad_Opcode },
7794     /* 38 */
7795     { Bad_Opcode },
7796     { Bad_Opcode },
7797     { Bad_Opcode },
7798     { Bad_Opcode },
7799     { Bad_Opcode },
7800     { Bad_Opcode },
7801     { Bad_Opcode },
7802     { Bad_Opcode },
7803     /* 40 */
7804     { Bad_Opcode },
7805     { Bad_Opcode },
7806     { Bad_Opcode },
7807     { Bad_Opcode },
7808     { Bad_Opcode },
7809     { Bad_Opcode },
7810     { Bad_Opcode },
7811     { Bad_Opcode },
7812     /* 48 */
7813     { Bad_Opcode },
7814     { Bad_Opcode },
7815     { Bad_Opcode },
7816     { Bad_Opcode },
7817     { Bad_Opcode },
7818     { Bad_Opcode },
7819     { Bad_Opcode },
7820     { Bad_Opcode },
7821     /* 50 */
7822     { Bad_Opcode },
7823     { Bad_Opcode },
7824     { Bad_Opcode },
7825     { Bad_Opcode },
7826     { Bad_Opcode },
7827     { Bad_Opcode },
7828     { Bad_Opcode },
7829     { Bad_Opcode },
7830     /* 58 */
7831     { Bad_Opcode },
7832     { Bad_Opcode },
7833     { Bad_Opcode },
7834     { Bad_Opcode },
7835     { Bad_Opcode },
7836     { Bad_Opcode },
7837     { Bad_Opcode },
7838     { Bad_Opcode },
7839     /* 60 */
7840     { Bad_Opcode },
7841     { Bad_Opcode },
7842     { Bad_Opcode },
7843     { Bad_Opcode },
7844     { Bad_Opcode },
7845     { Bad_Opcode },
7846     { Bad_Opcode },
7847     { Bad_Opcode },
7848     /* 68 */
7849     { Bad_Opcode },
7850     { Bad_Opcode },
7851     { Bad_Opcode },
7852     { Bad_Opcode },
7853     { Bad_Opcode },
7854     { Bad_Opcode },
7855     { Bad_Opcode },
7856     { Bad_Opcode },
7857     /* 70 */
7858     { Bad_Opcode },
7859     { Bad_Opcode },
7860     { Bad_Opcode },
7861     { Bad_Opcode },
7862     { Bad_Opcode },
7863     { Bad_Opcode },
7864     { Bad_Opcode },
7865     { Bad_Opcode },
7866     /* 78 */
7867     { Bad_Opcode },
7868     { Bad_Opcode },
7869     { Bad_Opcode },
7870     { Bad_Opcode },
7871     { Bad_Opcode },
7872     { Bad_Opcode },
7873     { Bad_Opcode },
7874     { Bad_Opcode },
7875     /* 80 */
7876     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
7877     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
7878     { "vfrczss",        { XM, EXd } },
7879     { "vfrczsd",        { XM, EXq } },
7880     { Bad_Opcode },
7881     { Bad_Opcode },
7882     { Bad_Opcode },
7883     { Bad_Opcode },
7884     /* 88 */
7885     { Bad_Opcode },
7886     { Bad_Opcode },
7887     { Bad_Opcode },
7888     { Bad_Opcode },
7889     { Bad_Opcode },
7890     { Bad_Opcode },
7891     { Bad_Opcode },
7892     { Bad_Opcode },
7893     /* 90 */
7894     { "vprotb",         { XM, Vex_2src_1, Vex_2src_2 } },
7895     { "vprotw",         { XM, Vex_2src_1, Vex_2src_2 } },
7896     { "vprotd",         { XM, Vex_2src_1, Vex_2src_2 } },
7897     { "vprotq",         { XM, Vex_2src_1, Vex_2src_2 } },
7898     { "vpshlb",         { XM, Vex_2src_1, Vex_2src_2 } },
7899     { "vpshlw",         { XM, Vex_2src_1, Vex_2src_2 } },
7900     { "vpshld",         { XM, Vex_2src_1, Vex_2src_2 } },
7901     { "vpshlq",         { XM, Vex_2src_1, Vex_2src_2 } },
7902     /* 98 */
7903     { "vpshab",         { XM, Vex_2src_1, Vex_2src_2 } },
7904     { "vpshaw",         { XM, Vex_2src_1, Vex_2src_2 } },
7905     { "vpshad",         { XM, Vex_2src_1, Vex_2src_2 } },
7906     { "vpshaq",         { XM, Vex_2src_1, Vex_2src_2 } },
7907     { Bad_Opcode },
7908     { Bad_Opcode },
7909     { Bad_Opcode },
7910     { Bad_Opcode },
7911     /* a0 */
7912     { Bad_Opcode },
7913     { Bad_Opcode },
7914     { Bad_Opcode },
7915     { Bad_Opcode },
7916     { Bad_Opcode },
7917     { Bad_Opcode },
7918     { Bad_Opcode },
7919     { Bad_Opcode },
7920     /* a8 */
7921     { Bad_Opcode },
7922     { Bad_Opcode },
7923     { Bad_Opcode },
7924     { Bad_Opcode },
7925     { Bad_Opcode },
7926     { Bad_Opcode },
7927     { Bad_Opcode },
7928     { Bad_Opcode },
7929     /* b0 */
7930     { Bad_Opcode },
7931     { Bad_Opcode },
7932     { Bad_Opcode },
7933     { Bad_Opcode },
7934     { Bad_Opcode },
7935     { Bad_Opcode },
7936     { Bad_Opcode },
7937     { Bad_Opcode },
7938     /* b8 */
7939     { Bad_Opcode },
7940     { Bad_Opcode },
7941     { Bad_Opcode },
7942     { Bad_Opcode },
7943     { Bad_Opcode },
7944     { Bad_Opcode },
7945     { Bad_Opcode },
7946     { Bad_Opcode },
7947     /* c0 */
7948     { Bad_Opcode },
7949     { "vphaddbw",       { XM, EXxmm } },
7950     { "vphaddbd",       { XM, EXxmm } },
7951     { "vphaddbq",       { XM, EXxmm } },
7952     { Bad_Opcode },
7953     { Bad_Opcode },
7954     { "vphaddwd",       { XM, EXxmm } },
7955     { "vphaddwq",       { XM, EXxmm } },
7956     /* c8 */
7957     { Bad_Opcode },
7958     { Bad_Opcode },
7959     { Bad_Opcode },
7960     { "vphadddq",       { XM, EXxmm } },
7961     { Bad_Opcode },
7962     { Bad_Opcode },
7963     { Bad_Opcode },
7964     { Bad_Opcode },
7965     /* d0 */
7966     { Bad_Opcode },
7967     { "vphaddubw",      { XM, EXxmm } },
7968     { "vphaddubd",      { XM, EXxmm } },
7969     { "vphaddubq",      { XM, EXxmm } },
7970     { Bad_Opcode },
7971     { Bad_Opcode },
7972     { "vphadduwd",      { XM, EXxmm } },
7973     { "vphadduwq",      { XM, EXxmm } },
7974     /* d8 */
7975     { Bad_Opcode },
7976     { Bad_Opcode },
7977     { Bad_Opcode },
7978     { "vphaddudq",      { XM, EXxmm } },
7979     { Bad_Opcode },
7980     { Bad_Opcode },
7981     { Bad_Opcode },
7982     { Bad_Opcode },
7983     /* e0 */
7984     { Bad_Opcode },
7985     { "vphsubbw",       { XM, EXxmm } },
7986     { "vphsubwd",       { XM, EXxmm } },
7987     { "vphsubdq",       { XM, EXxmm } },
7988     { Bad_Opcode },
7989     { Bad_Opcode },
7990     { Bad_Opcode },
7991     { Bad_Opcode },
7992     /* e8 */
7993     { Bad_Opcode },
7994     { Bad_Opcode },
7995     { Bad_Opcode },
7996     { Bad_Opcode },
7997     { Bad_Opcode },
7998     { Bad_Opcode },
7999     { Bad_Opcode },
8000     { Bad_Opcode },
8001     /* f0 */
8002     { Bad_Opcode },
8003     { Bad_Opcode },
8004     { Bad_Opcode },
8005     { Bad_Opcode },
8006     { Bad_Opcode },
8007     { Bad_Opcode },
8008     { Bad_Opcode },
8009     { Bad_Opcode },
8010     /* f8 */
8011     { Bad_Opcode },
8012     { Bad_Opcode },
8013     { Bad_Opcode },
8014     { Bad_Opcode },
8015     { Bad_Opcode },
8016     { Bad_Opcode },
8017     { Bad_Opcode },
8018     { Bad_Opcode },
8019   },
8020   /* XOP_0A */
8021   {
8022     /* 00 */
8023     { Bad_Opcode },
8024     { Bad_Opcode },
8025     { Bad_Opcode },
8026     { Bad_Opcode },
8027     { Bad_Opcode },
8028     { Bad_Opcode },
8029     { Bad_Opcode },
8030     { Bad_Opcode },
8031     /* 08 */
8032     { Bad_Opcode },
8033     { Bad_Opcode },
8034     { Bad_Opcode },
8035     { Bad_Opcode },
8036     { Bad_Opcode },
8037     { Bad_Opcode },
8038     { Bad_Opcode },
8039     { Bad_Opcode },
8040     /* 10 */
8041     { "bextr",  { Gv, Ev, Iq } },
8042     { Bad_Opcode },
8043     { REG_TABLE (REG_XOP_LWP) },
8044     { Bad_Opcode },
8045     { Bad_Opcode },
8046     { Bad_Opcode },
8047     { Bad_Opcode },
8048     { Bad_Opcode },
8049     /* 18 */
8050     { Bad_Opcode },
8051     { Bad_Opcode },
8052     { Bad_Opcode },
8053     { Bad_Opcode },
8054     { Bad_Opcode },
8055     { Bad_Opcode },
8056     { Bad_Opcode },
8057     { Bad_Opcode },
8058     /* 20 */
8059     { Bad_Opcode },
8060     { Bad_Opcode },
8061     { Bad_Opcode },
8062     { Bad_Opcode },
8063     { Bad_Opcode },
8064     { Bad_Opcode },
8065     { Bad_Opcode },
8066     { Bad_Opcode },
8067     /* 28 */
8068     { Bad_Opcode },
8069     { Bad_Opcode },
8070     { Bad_Opcode },
8071     { Bad_Opcode },
8072     { Bad_Opcode },
8073     { Bad_Opcode },
8074     { Bad_Opcode },
8075     { Bad_Opcode },
8076     /* 30 */
8077     { Bad_Opcode },
8078     { Bad_Opcode },
8079     { Bad_Opcode },
8080     { Bad_Opcode },
8081     { Bad_Opcode },
8082     { Bad_Opcode },
8083     { Bad_Opcode },
8084     { Bad_Opcode },
8085     /* 38 */
8086     { Bad_Opcode },
8087     { Bad_Opcode },
8088     { Bad_Opcode },
8089     { Bad_Opcode },
8090     { Bad_Opcode },
8091     { Bad_Opcode },
8092     { Bad_Opcode },
8093     { Bad_Opcode },
8094     /* 40 */
8095     { Bad_Opcode },
8096     { Bad_Opcode },
8097     { Bad_Opcode },
8098     { Bad_Opcode },
8099     { Bad_Opcode },
8100     { Bad_Opcode },
8101     { Bad_Opcode },
8102     { Bad_Opcode },
8103     /* 48 */
8104     { Bad_Opcode },
8105     { Bad_Opcode },
8106     { Bad_Opcode },
8107     { Bad_Opcode },
8108     { Bad_Opcode },
8109     { Bad_Opcode },
8110     { Bad_Opcode },
8111     { Bad_Opcode },
8112     /* 50 */
8113     { Bad_Opcode },
8114     { Bad_Opcode },
8115     { Bad_Opcode },
8116     { Bad_Opcode },
8117     { Bad_Opcode },
8118     { Bad_Opcode },
8119     { Bad_Opcode },
8120     { Bad_Opcode },
8121     /* 58 */
8122     { Bad_Opcode },
8123     { Bad_Opcode },
8124     { Bad_Opcode },
8125     { Bad_Opcode },
8126     { Bad_Opcode },
8127     { Bad_Opcode },
8128     { Bad_Opcode },
8129     { Bad_Opcode },
8130     /* 60 */
8131     { Bad_Opcode },
8132     { Bad_Opcode },
8133     { Bad_Opcode },
8134     { Bad_Opcode },
8135     { Bad_Opcode },
8136     { Bad_Opcode },
8137     { Bad_Opcode },
8138     { Bad_Opcode },
8139     /* 68 */
8140     { Bad_Opcode },
8141     { Bad_Opcode },
8142     { Bad_Opcode },
8143     { Bad_Opcode },
8144     { Bad_Opcode },
8145     { Bad_Opcode },
8146     { Bad_Opcode },
8147     { Bad_Opcode },
8148     /* 70 */
8149     { Bad_Opcode },
8150     { Bad_Opcode },
8151     { Bad_Opcode },
8152     { Bad_Opcode },
8153     { Bad_Opcode },
8154     { Bad_Opcode },
8155     { Bad_Opcode },
8156     { Bad_Opcode },
8157     /* 78 */
8158     { Bad_Opcode },
8159     { Bad_Opcode },
8160     { Bad_Opcode },
8161     { Bad_Opcode },
8162     { Bad_Opcode },
8163     { Bad_Opcode },
8164     { Bad_Opcode },
8165     { Bad_Opcode },
8166     /* 80 */
8167     { Bad_Opcode },
8168     { Bad_Opcode },
8169     { Bad_Opcode },
8170     { Bad_Opcode },
8171     { Bad_Opcode },
8172     { Bad_Opcode },
8173     { Bad_Opcode },
8174     { Bad_Opcode },
8175     /* 88 */
8176     { Bad_Opcode },
8177     { Bad_Opcode },
8178     { Bad_Opcode },
8179     { Bad_Opcode },
8180     { Bad_Opcode },
8181     { Bad_Opcode },
8182     { Bad_Opcode },
8183     { Bad_Opcode },
8184     /* 90 */
8185     { Bad_Opcode },
8186     { Bad_Opcode },
8187     { Bad_Opcode },
8188     { Bad_Opcode },
8189     { Bad_Opcode },
8190     { Bad_Opcode },
8191     { Bad_Opcode },
8192     { Bad_Opcode },
8193     /* 98 */
8194     { Bad_Opcode },
8195     { Bad_Opcode },
8196     { Bad_Opcode },
8197     { Bad_Opcode },
8198     { Bad_Opcode },
8199     { Bad_Opcode },
8200     { Bad_Opcode },
8201     { Bad_Opcode },
8202     /* a0 */
8203     { Bad_Opcode },
8204     { Bad_Opcode },
8205     { Bad_Opcode },
8206     { Bad_Opcode },
8207     { Bad_Opcode },
8208     { Bad_Opcode },
8209     { Bad_Opcode },
8210     { Bad_Opcode },
8211     /* a8 */
8212     { Bad_Opcode },
8213     { Bad_Opcode },
8214     { Bad_Opcode },
8215     { Bad_Opcode },
8216     { Bad_Opcode },
8217     { Bad_Opcode },
8218     { Bad_Opcode },
8219     { Bad_Opcode },
8220     /* b0 */
8221     { Bad_Opcode },
8222     { Bad_Opcode },
8223     { Bad_Opcode },
8224     { Bad_Opcode },
8225     { Bad_Opcode },
8226     { Bad_Opcode },
8227     { Bad_Opcode },
8228     { Bad_Opcode },
8229     /* b8 */
8230     { Bad_Opcode },
8231     { Bad_Opcode },
8232     { Bad_Opcode },
8233     { Bad_Opcode },
8234     { Bad_Opcode },
8235     { Bad_Opcode },
8236     { Bad_Opcode },
8237     { Bad_Opcode },
8238     /* c0 */
8239     { Bad_Opcode },
8240     { Bad_Opcode },
8241     { Bad_Opcode },
8242     { Bad_Opcode },
8243     { Bad_Opcode },
8244     { Bad_Opcode },
8245     { Bad_Opcode },
8246     { Bad_Opcode },
8247     /* c8 */
8248     { Bad_Opcode },
8249     { Bad_Opcode },
8250     { Bad_Opcode },
8251     { Bad_Opcode },
8252     { Bad_Opcode },
8253     { Bad_Opcode },
8254     { Bad_Opcode },
8255     { Bad_Opcode },
8256     /* d0 */
8257     { Bad_Opcode },
8258     { Bad_Opcode },
8259     { Bad_Opcode },
8260     { Bad_Opcode },
8261     { Bad_Opcode },
8262     { Bad_Opcode },
8263     { Bad_Opcode },
8264     { Bad_Opcode },
8265     /* d8 */
8266     { Bad_Opcode },
8267     { Bad_Opcode },
8268     { Bad_Opcode },
8269     { Bad_Opcode },
8270     { Bad_Opcode },
8271     { Bad_Opcode },
8272     { Bad_Opcode },
8273     { Bad_Opcode },
8274     /* e0 */
8275     { Bad_Opcode },
8276     { Bad_Opcode },
8277     { Bad_Opcode },
8278     { Bad_Opcode },
8279     { Bad_Opcode },
8280     { Bad_Opcode },
8281     { Bad_Opcode },
8282     { Bad_Opcode },
8283     /* e8 */
8284     { Bad_Opcode },
8285     { Bad_Opcode },
8286     { Bad_Opcode },
8287     { Bad_Opcode },
8288     { Bad_Opcode },
8289     { Bad_Opcode },
8290     { Bad_Opcode },
8291     { Bad_Opcode },
8292     /* f0 */
8293     { Bad_Opcode },
8294     { Bad_Opcode },
8295     { Bad_Opcode },
8296     { Bad_Opcode },
8297     { Bad_Opcode },
8298     { Bad_Opcode },
8299     { Bad_Opcode },
8300     { Bad_Opcode },
8301     /* f8 */
8302     { Bad_Opcode },
8303     { Bad_Opcode },
8304     { Bad_Opcode },
8305     { Bad_Opcode },
8306     { Bad_Opcode },
8307     { Bad_Opcode },
8308     { Bad_Opcode },
8309     { Bad_Opcode },
8310   },
8311 };
8312
8313 static const struct dis386 vex_table[][256] = {
8314   /* VEX_0F */
8315   {
8316     /* 00 */
8317     { Bad_Opcode },
8318     { Bad_Opcode },
8319     { Bad_Opcode },
8320     { Bad_Opcode },
8321     { Bad_Opcode },
8322     { Bad_Opcode },
8323     { Bad_Opcode },
8324     { Bad_Opcode },
8325     /* 08 */
8326     { Bad_Opcode },
8327     { Bad_Opcode },
8328     { Bad_Opcode },
8329     { Bad_Opcode },
8330     { Bad_Opcode },
8331     { Bad_Opcode },
8332     { Bad_Opcode },
8333     { Bad_Opcode },
8334     /* 10 */
8335     { PREFIX_TABLE (PREFIX_VEX_0F10) },
8336     { PREFIX_TABLE (PREFIX_VEX_0F11) },
8337     { PREFIX_TABLE (PREFIX_VEX_0F12) },
8338     { MOD_TABLE (MOD_VEX_0F13) },
8339     { VEX_W_TABLE (VEX_W_0F14) },
8340     { VEX_W_TABLE (VEX_W_0F15) },
8341     { PREFIX_TABLE (PREFIX_VEX_0F16) },
8342     { MOD_TABLE (MOD_VEX_0F17) },
8343     /* 18 */
8344     { Bad_Opcode },
8345     { Bad_Opcode },
8346     { Bad_Opcode },
8347     { Bad_Opcode },
8348     { Bad_Opcode },
8349     { Bad_Opcode },
8350     { Bad_Opcode },
8351     { Bad_Opcode },
8352     /* 20 */
8353     { Bad_Opcode },
8354     { Bad_Opcode },
8355     { Bad_Opcode },
8356     { Bad_Opcode },
8357     { Bad_Opcode },
8358     { Bad_Opcode },
8359     { Bad_Opcode },
8360     { Bad_Opcode },
8361     /* 28 */
8362     { VEX_W_TABLE (VEX_W_0F28) },
8363     { VEX_W_TABLE (VEX_W_0F29) },
8364     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8365     { MOD_TABLE (MOD_VEX_0F2B) },
8366     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8367     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8368     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8369     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8370     /* 30 */
8371     { Bad_Opcode },
8372     { Bad_Opcode },
8373     { Bad_Opcode },
8374     { Bad_Opcode },
8375     { Bad_Opcode },
8376     { Bad_Opcode },
8377     { Bad_Opcode },
8378     { Bad_Opcode },
8379     /* 38 */
8380     { Bad_Opcode },
8381     { Bad_Opcode },
8382     { Bad_Opcode },
8383     { Bad_Opcode },
8384     { Bad_Opcode },
8385     { Bad_Opcode },
8386     { Bad_Opcode },
8387     { Bad_Opcode },
8388     /* 40 */
8389     { Bad_Opcode },
8390     { PREFIX_TABLE (PREFIX_VEX_0F41) },
8391     { PREFIX_TABLE (PREFIX_VEX_0F42) },
8392     { Bad_Opcode },
8393     { PREFIX_TABLE (PREFIX_VEX_0F44) },
8394     { PREFIX_TABLE (PREFIX_VEX_0F45) },
8395     { PREFIX_TABLE (PREFIX_VEX_0F46) },
8396     { PREFIX_TABLE (PREFIX_VEX_0F47) },
8397     /* 48 */
8398     { Bad_Opcode },
8399     { Bad_Opcode },
8400     { Bad_Opcode },
8401     { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8402     { Bad_Opcode },
8403     { Bad_Opcode },
8404     { Bad_Opcode },
8405     { Bad_Opcode },
8406     /* 50 */
8407     { MOD_TABLE (MOD_VEX_0F50) },
8408     { PREFIX_TABLE (PREFIX_VEX_0F51) },
8409     { PREFIX_TABLE (PREFIX_VEX_0F52) },
8410     { PREFIX_TABLE (PREFIX_VEX_0F53) },
8411     { "vandpX",         { XM, Vex, EXx } },
8412     { "vandnpX",        { XM, Vex, EXx } },
8413     { "vorpX",          { XM, Vex, EXx } },
8414     { "vxorpX",         { XM, Vex, EXx } },
8415     /* 58 */
8416     { PREFIX_TABLE (PREFIX_VEX_0F58) },
8417     { PREFIX_TABLE (PREFIX_VEX_0F59) },
8418     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8419     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8420     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8421     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8422     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8423     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8424     /* 60 */
8425     { PREFIX_TABLE (PREFIX_VEX_0F60) },
8426     { PREFIX_TABLE (PREFIX_VEX_0F61) },
8427     { PREFIX_TABLE (PREFIX_VEX_0F62) },
8428     { PREFIX_TABLE (PREFIX_VEX_0F63) },
8429     { PREFIX_TABLE (PREFIX_VEX_0F64) },
8430     { PREFIX_TABLE (PREFIX_VEX_0F65) },
8431     { PREFIX_TABLE (PREFIX_VEX_0F66) },
8432     { PREFIX_TABLE (PREFIX_VEX_0F67) },
8433     /* 68 */
8434     { PREFIX_TABLE (PREFIX_VEX_0F68) },
8435     { PREFIX_TABLE (PREFIX_VEX_0F69) },
8436     { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8437     { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8438     { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8439     { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8440     { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8441     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8442     /* 70 */
8443     { PREFIX_TABLE (PREFIX_VEX_0F70) },
8444     { REG_TABLE (REG_VEX_0F71) },
8445     { REG_TABLE (REG_VEX_0F72) },
8446     { REG_TABLE (REG_VEX_0F73) },
8447     { PREFIX_TABLE (PREFIX_VEX_0F74) },
8448     { PREFIX_TABLE (PREFIX_VEX_0F75) },
8449     { PREFIX_TABLE (PREFIX_VEX_0F76) },
8450     { PREFIX_TABLE (PREFIX_VEX_0F77) },
8451     /* 78 */
8452     { Bad_Opcode },
8453     { Bad_Opcode },
8454     { Bad_Opcode },
8455     { Bad_Opcode },
8456     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8457     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8458     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8459     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8460     /* 80 */
8461     { Bad_Opcode },
8462     { Bad_Opcode },
8463     { Bad_Opcode },
8464     { Bad_Opcode },
8465     { Bad_Opcode },
8466     { Bad_Opcode },
8467     { Bad_Opcode },
8468     { Bad_Opcode },
8469     /* 88 */
8470     { Bad_Opcode },
8471     { Bad_Opcode },
8472     { Bad_Opcode },
8473     { Bad_Opcode },
8474     { Bad_Opcode },
8475     { Bad_Opcode },
8476     { Bad_Opcode },
8477     { Bad_Opcode },
8478     /* 90 */
8479     { PREFIX_TABLE (PREFIX_VEX_0F90) },
8480     { PREFIX_TABLE (PREFIX_VEX_0F91) },
8481     { PREFIX_TABLE (PREFIX_VEX_0F92) },
8482     { PREFIX_TABLE (PREFIX_VEX_0F93) },
8483     { Bad_Opcode },
8484     { Bad_Opcode },
8485     { Bad_Opcode },
8486     { Bad_Opcode },
8487     /* 98 */
8488     { PREFIX_TABLE (PREFIX_VEX_0F98) },
8489     { Bad_Opcode },
8490     { Bad_Opcode },
8491     { Bad_Opcode },
8492     { Bad_Opcode },
8493     { Bad_Opcode },
8494     { Bad_Opcode },
8495     { Bad_Opcode },
8496     /* a0 */
8497     { Bad_Opcode },
8498     { Bad_Opcode },
8499     { Bad_Opcode },
8500     { Bad_Opcode },
8501     { Bad_Opcode },
8502     { Bad_Opcode },
8503     { Bad_Opcode },
8504     { Bad_Opcode },
8505     /* a8 */
8506     { Bad_Opcode },
8507     { Bad_Opcode },
8508     { Bad_Opcode },
8509     { Bad_Opcode },
8510     { Bad_Opcode },
8511     { Bad_Opcode },
8512     { REG_TABLE (REG_VEX_0FAE) },
8513     { Bad_Opcode },
8514     /* b0 */
8515     { Bad_Opcode },
8516     { Bad_Opcode },
8517     { Bad_Opcode },
8518     { Bad_Opcode },
8519     { Bad_Opcode },
8520     { Bad_Opcode },
8521     { Bad_Opcode },
8522     { Bad_Opcode },
8523     /* b8 */
8524     { Bad_Opcode },
8525     { Bad_Opcode },
8526     { Bad_Opcode },
8527     { Bad_Opcode },
8528     { Bad_Opcode },
8529     { Bad_Opcode },
8530     { Bad_Opcode },
8531     { Bad_Opcode },
8532     /* c0 */
8533     { Bad_Opcode },
8534     { Bad_Opcode },
8535     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8536     { Bad_Opcode },
8537     { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8538     { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8539     { "vshufpX",        { XM, Vex, EXx, Ib } },
8540     { Bad_Opcode },
8541     /* c8 */
8542     { Bad_Opcode },
8543     { Bad_Opcode },
8544     { Bad_Opcode },
8545     { Bad_Opcode },
8546     { Bad_Opcode },
8547     { Bad_Opcode },
8548     { Bad_Opcode },
8549     { Bad_Opcode },
8550     /* d0 */
8551     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8552     { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8553     { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8554     { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8555     { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8556     { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8557     { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8558     { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8559     /* d8 */
8560     { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8561     { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8562     { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8563     { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8564     { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8565     { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8566     { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8567     { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8568     /* e0 */
8569     { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8570     { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8571     { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8572     { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8573     { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8574     { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8575     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8576     { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8577     /* e8 */
8578     { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8579     { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8580     { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8581     { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8582     { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8583     { PREFIX_TABLE (PREFIX_VEX_0FED) },
8584     { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8585     { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8586     /* f0 */
8587     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8588     { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8589     { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8590     { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8591     { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8592     { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8593     { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8594     { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8595     /* f8 */
8596     { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8597     { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8598     { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8599     { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8600     { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8601     { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8602     { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8603     { Bad_Opcode },
8604   },
8605   /* VEX_0F38 */
8606   {
8607     /* 00 */
8608     { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8609     { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8610     { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8611     { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8612     { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8613     { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8614     { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8615     { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8616     /* 08 */
8617     { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8618     { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8619     { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8620     { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8621     { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8622     { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8623     { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8624     { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8625     /* 10 */
8626     { Bad_Opcode },
8627     { Bad_Opcode },
8628     { Bad_Opcode },
8629     { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8630     { Bad_Opcode },
8631     { Bad_Opcode },
8632     { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8633     { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8634     /* 18 */
8635     { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8636     { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8637     { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8638     { Bad_Opcode },
8639     { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8640     { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8641     { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8642     { Bad_Opcode },
8643     /* 20 */
8644     { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8645     { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8646     { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8647     { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8648     { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8649     { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8650     { Bad_Opcode },
8651     { Bad_Opcode },
8652     /* 28 */
8653     { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8654     { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8655     { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8656     { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8657     { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8658     { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8659     { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8660     { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8661     /* 30 */
8662     { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8663     { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8664     { PREFIX_TABLE (PREFIX_VEX_0F3832) },
8665     { PREFIX_TABLE (PREFIX_VEX_0F3833) },
8666     { PREFIX_TABLE (PREFIX_VEX_0F3834) },
8667     { PREFIX_TABLE (PREFIX_VEX_0F3835) },
8668     { PREFIX_TABLE (PREFIX_VEX_0F3836) },
8669     { PREFIX_TABLE (PREFIX_VEX_0F3837) },
8670     /* 38 */
8671     { PREFIX_TABLE (PREFIX_VEX_0F3838) },
8672     { PREFIX_TABLE (PREFIX_VEX_0F3839) },
8673     { PREFIX_TABLE (PREFIX_VEX_0F383A) },
8674     { PREFIX_TABLE (PREFIX_VEX_0F383B) },
8675     { PREFIX_TABLE (PREFIX_VEX_0F383C) },
8676     { PREFIX_TABLE (PREFIX_VEX_0F383D) },
8677     { PREFIX_TABLE (PREFIX_VEX_0F383E) },
8678     { PREFIX_TABLE (PREFIX_VEX_0F383F) },
8679     /* 40 */
8680     { PREFIX_TABLE (PREFIX_VEX_0F3840) },
8681     { PREFIX_TABLE (PREFIX_VEX_0F3841) },
8682     { Bad_Opcode },
8683     { Bad_Opcode },
8684     { Bad_Opcode },
8685     { PREFIX_TABLE (PREFIX_VEX_0F3845) },
8686     { PREFIX_TABLE (PREFIX_VEX_0F3846) },
8687     { PREFIX_TABLE (PREFIX_VEX_0F3847) },
8688     /* 48 */
8689     { Bad_Opcode },
8690     { Bad_Opcode },
8691     { Bad_Opcode },
8692     { Bad_Opcode },
8693     { Bad_Opcode },
8694     { Bad_Opcode },
8695     { Bad_Opcode },
8696     { Bad_Opcode },
8697     /* 50 */
8698     { Bad_Opcode },
8699     { Bad_Opcode },
8700     { Bad_Opcode },
8701     { Bad_Opcode },
8702     { Bad_Opcode },
8703     { Bad_Opcode },
8704     { Bad_Opcode },
8705     { Bad_Opcode },
8706     /* 58 */
8707     { PREFIX_TABLE (PREFIX_VEX_0F3858) },
8708     { PREFIX_TABLE (PREFIX_VEX_0F3859) },
8709     { PREFIX_TABLE (PREFIX_VEX_0F385A) },
8710     { Bad_Opcode },
8711     { Bad_Opcode },
8712     { Bad_Opcode },
8713     { Bad_Opcode },
8714     { Bad_Opcode },
8715     /* 60 */
8716     { Bad_Opcode },
8717     { Bad_Opcode },
8718     { Bad_Opcode },
8719     { Bad_Opcode },
8720     { Bad_Opcode },
8721     { Bad_Opcode },
8722     { Bad_Opcode },
8723     { Bad_Opcode },
8724     /* 68 */
8725     { Bad_Opcode },
8726     { Bad_Opcode },
8727     { Bad_Opcode },
8728     { Bad_Opcode },
8729     { Bad_Opcode },
8730     { Bad_Opcode },
8731     { Bad_Opcode },
8732     { Bad_Opcode },
8733     /* 70 */
8734     { Bad_Opcode },
8735     { Bad_Opcode },
8736     { Bad_Opcode },
8737     { Bad_Opcode },
8738     { Bad_Opcode },
8739     { Bad_Opcode },
8740     { Bad_Opcode },
8741     { Bad_Opcode },
8742     /* 78 */
8743     { PREFIX_TABLE (PREFIX_VEX_0F3878) },
8744     { PREFIX_TABLE (PREFIX_VEX_0F3879) },
8745     { Bad_Opcode },
8746     { Bad_Opcode },
8747     { Bad_Opcode },
8748     { Bad_Opcode },
8749     { Bad_Opcode },
8750     { Bad_Opcode },
8751     /* 80 */
8752     { Bad_Opcode },
8753     { Bad_Opcode },
8754     { Bad_Opcode },
8755     { Bad_Opcode },
8756     { Bad_Opcode },
8757     { Bad_Opcode },
8758     { Bad_Opcode },
8759     { Bad_Opcode },
8760     /* 88 */
8761     { Bad_Opcode },
8762     { Bad_Opcode },
8763     { Bad_Opcode },
8764     { Bad_Opcode },
8765     { PREFIX_TABLE (PREFIX_VEX_0F388C) },
8766     { Bad_Opcode },
8767     { PREFIX_TABLE (PREFIX_VEX_0F388E) },
8768     { Bad_Opcode },
8769     /* 90 */
8770     { PREFIX_TABLE (PREFIX_VEX_0F3890) },
8771     { PREFIX_TABLE (PREFIX_VEX_0F3891) },
8772     { PREFIX_TABLE (PREFIX_VEX_0F3892) },
8773     { PREFIX_TABLE (PREFIX_VEX_0F3893) },
8774     { Bad_Opcode },
8775     { Bad_Opcode },
8776     { PREFIX_TABLE (PREFIX_VEX_0F3896) },
8777     { PREFIX_TABLE (PREFIX_VEX_0F3897) },
8778     /* 98 */
8779     { PREFIX_TABLE (PREFIX_VEX_0F3898) },
8780     { PREFIX_TABLE (PREFIX_VEX_0F3899) },
8781     { PREFIX_TABLE (PREFIX_VEX_0F389A) },
8782     { PREFIX_TABLE (PREFIX_VEX_0F389B) },
8783     { PREFIX_TABLE (PREFIX_VEX_0F389C) },
8784     { PREFIX_TABLE (PREFIX_VEX_0F389D) },
8785     { PREFIX_TABLE (PREFIX_VEX_0F389E) },
8786     { PREFIX_TABLE (PREFIX_VEX_0F389F) },
8787     /* a0 */
8788     { Bad_Opcode },
8789     { Bad_Opcode },
8790     { Bad_Opcode },
8791     { Bad_Opcode },
8792     { Bad_Opcode },
8793     { Bad_Opcode },
8794     { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
8795     { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
8796     /* a8 */
8797     { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
8798     { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
8799     { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
8800     { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
8801     { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
8802     { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
8803     { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
8804     { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
8805     /* b0 */
8806     { Bad_Opcode },
8807     { Bad_Opcode },
8808     { Bad_Opcode },
8809     { Bad_Opcode },
8810     { Bad_Opcode },
8811     { Bad_Opcode },
8812     { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
8813     { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
8814     /* b8 */
8815     { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
8816     { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
8817     { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
8818     { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
8819     { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
8820     { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
8821     { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
8822     { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
8823     /* c0 */
8824     { Bad_Opcode },
8825     { Bad_Opcode },
8826     { Bad_Opcode },
8827     { Bad_Opcode },
8828     { Bad_Opcode },
8829     { Bad_Opcode },
8830     { Bad_Opcode },
8831     { Bad_Opcode },
8832     /* c8 */
8833     { Bad_Opcode },
8834     { Bad_Opcode },
8835     { Bad_Opcode },
8836     { Bad_Opcode },
8837     { Bad_Opcode },
8838     { Bad_Opcode },
8839     { Bad_Opcode },
8840     { Bad_Opcode },
8841     /* d0 */
8842     { Bad_Opcode },
8843     { Bad_Opcode },
8844     { Bad_Opcode },
8845     { Bad_Opcode },
8846     { Bad_Opcode },
8847     { Bad_Opcode },
8848     { Bad_Opcode },
8849     { Bad_Opcode },
8850     /* d8 */
8851     { Bad_Opcode },
8852     { Bad_Opcode },
8853     { Bad_Opcode },
8854     { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
8855     { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
8856     { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
8857     { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
8858     { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
8859     /* e0 */
8860     { Bad_Opcode },
8861     { Bad_Opcode },
8862     { Bad_Opcode },
8863     { Bad_Opcode },
8864     { Bad_Opcode },
8865     { Bad_Opcode },
8866     { Bad_Opcode },
8867     { Bad_Opcode },
8868     /* e8 */
8869     { Bad_Opcode },
8870     { Bad_Opcode },
8871     { Bad_Opcode },
8872     { Bad_Opcode },
8873     { Bad_Opcode },
8874     { Bad_Opcode },
8875     { Bad_Opcode },
8876     { Bad_Opcode },
8877     /* f0 */
8878     { Bad_Opcode },
8879     { Bad_Opcode },
8880     { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
8881     { REG_TABLE (REG_VEX_0F38F3) },
8882     { Bad_Opcode },
8883     { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
8884     { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
8885     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
8886     /* f8 */
8887     { Bad_Opcode },
8888     { Bad_Opcode },
8889     { Bad_Opcode },
8890     { Bad_Opcode },
8891     { Bad_Opcode },
8892     { Bad_Opcode },
8893     { Bad_Opcode },
8894     { Bad_Opcode },
8895   },
8896   /* VEX_0F3A */
8897   {
8898     /* 00 */
8899     { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
8900     { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
8901     { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
8902     { Bad_Opcode },
8903     { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
8904     { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
8905     { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
8906     { Bad_Opcode },
8907     /* 08 */
8908     { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
8909     { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
8910     { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
8911     { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
8912     { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
8913     { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
8914     { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
8915     { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
8916     /* 10 */
8917     { Bad_Opcode },
8918     { Bad_Opcode },
8919     { Bad_Opcode },
8920     { Bad_Opcode },
8921     { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
8922     { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
8923     { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
8924     { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
8925     /* 18 */
8926     { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
8927     { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
8928     { Bad_Opcode },
8929     { Bad_Opcode },
8930     { Bad_Opcode },
8931     { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
8932     { Bad_Opcode },
8933     { Bad_Opcode },
8934     /* 20 */
8935     { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
8936     { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
8937     { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
8938     { Bad_Opcode },
8939     { Bad_Opcode },
8940     { Bad_Opcode },
8941     { Bad_Opcode },
8942     { Bad_Opcode },
8943     /* 28 */
8944     { Bad_Opcode },
8945     { Bad_Opcode },
8946     { Bad_Opcode },
8947     { Bad_Opcode },
8948     { Bad_Opcode },
8949     { Bad_Opcode },
8950     { Bad_Opcode },
8951     { Bad_Opcode },
8952     /* 30 */
8953     { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
8954     { Bad_Opcode },
8955     { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
8956     { Bad_Opcode },
8957     { Bad_Opcode },
8958     { Bad_Opcode },
8959     { Bad_Opcode },
8960     { Bad_Opcode },
8961     /* 38 */
8962     { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
8963     { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
8964     { Bad_Opcode },
8965     { Bad_Opcode },
8966     { Bad_Opcode },
8967     { Bad_Opcode },
8968     { Bad_Opcode },
8969     { Bad_Opcode },
8970     /* 40 */
8971     { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
8972     { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
8973     { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
8974     { Bad_Opcode },
8975     { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
8976     { Bad_Opcode },
8977     { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
8978     { Bad_Opcode },
8979     /* 48 */
8980     { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
8981     { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
8982     { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
8983     { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
8984     { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
8985     { Bad_Opcode },
8986     { Bad_Opcode },
8987     { Bad_Opcode },
8988     /* 50 */
8989     { Bad_Opcode },
8990     { Bad_Opcode },
8991     { Bad_Opcode },
8992     { Bad_Opcode },
8993     { Bad_Opcode },
8994     { Bad_Opcode },
8995     { Bad_Opcode },
8996     { Bad_Opcode },
8997     /* 58 */
8998     { Bad_Opcode },
8999     { Bad_Opcode },
9000     { Bad_Opcode },
9001     { Bad_Opcode },
9002     { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9003     { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9004     { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9005     { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9006     /* 60 */
9007     { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9008     { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9009     { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9010     { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9011     { Bad_Opcode },
9012     { Bad_Opcode },
9013     { Bad_Opcode },
9014     { Bad_Opcode },
9015     /* 68 */
9016     { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9017     { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9018     { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9019     { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9020     { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9021     { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9022     { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9023     { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9024     /* 70 */
9025     { Bad_Opcode },
9026     { Bad_Opcode },
9027     { Bad_Opcode },
9028     { Bad_Opcode },
9029     { Bad_Opcode },
9030     { Bad_Opcode },
9031     { Bad_Opcode },
9032     { Bad_Opcode },
9033     /* 78 */
9034     { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9035     { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9036     { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9037     { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9038     { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9039     { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9040     { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9041     { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9042     /* 80 */
9043     { Bad_Opcode },
9044     { Bad_Opcode },
9045     { Bad_Opcode },
9046     { Bad_Opcode },
9047     { Bad_Opcode },
9048     { Bad_Opcode },
9049     { Bad_Opcode },
9050     { Bad_Opcode },
9051     /* 88 */
9052     { Bad_Opcode },
9053     { Bad_Opcode },
9054     { Bad_Opcode },
9055     { Bad_Opcode },
9056     { Bad_Opcode },
9057     { Bad_Opcode },
9058     { Bad_Opcode },
9059     { Bad_Opcode },
9060     /* 90 */
9061     { Bad_Opcode },
9062     { Bad_Opcode },
9063     { Bad_Opcode },
9064     { Bad_Opcode },
9065     { Bad_Opcode },
9066     { Bad_Opcode },
9067     { Bad_Opcode },
9068     { Bad_Opcode },
9069     /* 98 */
9070     { Bad_Opcode },
9071     { Bad_Opcode },
9072     { Bad_Opcode },
9073     { Bad_Opcode },
9074     { Bad_Opcode },
9075     { Bad_Opcode },
9076     { Bad_Opcode },
9077     { Bad_Opcode },
9078     /* a0 */
9079     { Bad_Opcode },
9080     { Bad_Opcode },
9081     { Bad_Opcode },
9082     { Bad_Opcode },
9083     { Bad_Opcode },
9084     { Bad_Opcode },
9085     { Bad_Opcode },
9086     { Bad_Opcode },
9087     /* a8 */
9088     { Bad_Opcode },
9089     { Bad_Opcode },
9090     { Bad_Opcode },
9091     { Bad_Opcode },
9092     { Bad_Opcode },
9093     { Bad_Opcode },
9094     { Bad_Opcode },
9095     { Bad_Opcode },
9096     /* b0 */
9097     { Bad_Opcode },
9098     { Bad_Opcode },
9099     { Bad_Opcode },
9100     { Bad_Opcode },
9101     { Bad_Opcode },
9102     { Bad_Opcode },
9103     { Bad_Opcode },
9104     { Bad_Opcode },
9105     /* b8 */
9106     { Bad_Opcode },
9107     { Bad_Opcode },
9108     { Bad_Opcode },
9109     { Bad_Opcode },
9110     { Bad_Opcode },
9111     { Bad_Opcode },
9112     { Bad_Opcode },
9113     { Bad_Opcode },
9114     /* c0 */
9115     { Bad_Opcode },
9116     { Bad_Opcode },
9117     { Bad_Opcode },
9118     { Bad_Opcode },
9119     { Bad_Opcode },
9120     { Bad_Opcode },
9121     { Bad_Opcode },
9122     { Bad_Opcode },
9123     /* c8 */
9124     { Bad_Opcode },
9125     { Bad_Opcode },
9126     { Bad_Opcode },
9127     { Bad_Opcode },
9128     { Bad_Opcode },
9129     { Bad_Opcode },
9130     { Bad_Opcode },
9131     { Bad_Opcode },
9132     /* d0 */
9133     { Bad_Opcode },
9134     { Bad_Opcode },
9135     { Bad_Opcode },
9136     { Bad_Opcode },
9137     { Bad_Opcode },
9138     { Bad_Opcode },
9139     { Bad_Opcode },
9140     { Bad_Opcode },
9141     /* d8 */
9142     { Bad_Opcode },
9143     { Bad_Opcode },
9144     { Bad_Opcode },
9145     { Bad_Opcode },
9146     { Bad_Opcode },
9147     { Bad_Opcode },
9148     { Bad_Opcode },
9149     { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9150     /* e0 */
9151     { Bad_Opcode },
9152     { Bad_Opcode },
9153     { Bad_Opcode },
9154     { Bad_Opcode },
9155     { Bad_Opcode },
9156     { Bad_Opcode },
9157     { Bad_Opcode },
9158     { Bad_Opcode },
9159     /* e8 */
9160     { Bad_Opcode },
9161     { Bad_Opcode },
9162     { Bad_Opcode },
9163     { Bad_Opcode },
9164     { Bad_Opcode },
9165     { Bad_Opcode },
9166     { Bad_Opcode },
9167     { Bad_Opcode },
9168     /* f0 */
9169     { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9170     { Bad_Opcode },
9171     { Bad_Opcode },
9172     { Bad_Opcode },
9173     { Bad_Opcode },
9174     { Bad_Opcode },
9175     { Bad_Opcode },
9176     { Bad_Opcode },
9177     /* f8 */
9178     { Bad_Opcode },
9179     { Bad_Opcode },
9180     { Bad_Opcode },
9181     { Bad_Opcode },
9182     { Bad_Opcode },
9183     { Bad_Opcode },
9184     { Bad_Opcode },
9185     { Bad_Opcode },
9186   },
9187 };
9188
9189 #define NEED_OPCODE_TABLE
9190 #include "i386-dis-evex.h"
9191 #undef NEED_OPCODE_TABLE
9192 static const struct dis386 vex_len_table[][2] = {
9193   /* VEX_LEN_0F10_P_1 */
9194   {
9195     { VEX_W_TABLE (VEX_W_0F10_P_1) },
9196     { VEX_W_TABLE (VEX_W_0F10_P_1) },
9197   },
9198
9199   /* VEX_LEN_0F10_P_3 */
9200   {
9201     { VEX_W_TABLE (VEX_W_0F10_P_3) },
9202     { VEX_W_TABLE (VEX_W_0F10_P_3) },
9203   },
9204
9205   /* VEX_LEN_0F11_P_1 */
9206   {
9207     { VEX_W_TABLE (VEX_W_0F11_P_1) },
9208     { VEX_W_TABLE (VEX_W_0F11_P_1) },
9209   },
9210
9211   /* VEX_LEN_0F11_P_3 */
9212   {
9213     { VEX_W_TABLE (VEX_W_0F11_P_3) },
9214     { VEX_W_TABLE (VEX_W_0F11_P_3) },
9215   },
9216
9217   /* VEX_LEN_0F12_P_0_M_0 */
9218   {
9219     { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) },
9220   },
9221
9222   /* VEX_LEN_0F12_P_0_M_1 */
9223   {
9224     { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) },
9225   },
9226
9227   /* VEX_LEN_0F12_P_2 */
9228   {
9229     { VEX_W_TABLE (VEX_W_0F12_P_2) },
9230   },
9231
9232   /* VEX_LEN_0F13_M_0 */
9233   {
9234     { VEX_W_TABLE (VEX_W_0F13_M_0) },
9235   },
9236
9237   /* VEX_LEN_0F16_P_0_M_0 */
9238   {
9239     { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) },
9240   },
9241
9242   /* VEX_LEN_0F16_P_0_M_1 */
9243   {
9244     { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) },
9245   },
9246
9247   /* VEX_LEN_0F16_P_2 */
9248   {
9249     { VEX_W_TABLE (VEX_W_0F16_P_2) },
9250   },
9251
9252   /* VEX_LEN_0F17_M_0 */
9253   {
9254     { VEX_W_TABLE (VEX_W_0F17_M_0) },
9255   },
9256
9257   /* VEX_LEN_0F2A_P_1 */
9258   {
9259     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev } },
9260     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev } },
9261   },
9262
9263   /* VEX_LEN_0F2A_P_3 */
9264   {
9265     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev } },
9266     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev } },
9267   },
9268
9269   /* VEX_LEN_0F2C_P_1 */
9270   {
9271     { "vcvttss2siY",    { Gv, EXdScalar } },
9272     { "vcvttss2siY",    { Gv, EXdScalar } },
9273   },
9274
9275   /* VEX_LEN_0F2C_P_3 */
9276   {
9277     { "vcvttsd2siY",    { Gv, EXqScalar } },
9278     { "vcvttsd2siY",    { Gv, EXqScalar } },
9279   },
9280
9281   /* VEX_LEN_0F2D_P_1 */
9282   {
9283     { "vcvtss2siY",     { Gv, EXdScalar } },
9284     { "vcvtss2siY",     { Gv, EXdScalar } },
9285   },
9286
9287   /* VEX_LEN_0F2D_P_3 */
9288   {
9289     { "vcvtsd2siY",     { Gv, EXqScalar } },
9290     { "vcvtsd2siY",     { Gv, EXqScalar } },
9291   },
9292
9293   /* VEX_LEN_0F2E_P_0 */
9294   {
9295     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9296     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9297   },
9298
9299   /* VEX_LEN_0F2E_P_2 */
9300   {
9301     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9302     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9303   },
9304
9305   /* VEX_LEN_0F2F_P_0 */
9306   {
9307     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9308     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9309   },
9310
9311   /* VEX_LEN_0F2F_P_2 */
9312   {
9313     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9314     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9315   },
9316
9317   /* VEX_LEN_0F41_P_0 */
9318   {
9319     { Bad_Opcode },
9320     { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9321   },
9322   /* VEX_LEN_0F42_P_0 */
9323   {
9324     { Bad_Opcode },
9325     { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9326   },
9327   /* VEX_LEN_0F44_P_0 */
9328   {
9329     { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9330   },
9331   /* VEX_LEN_0F45_P_0 */
9332   {
9333     { Bad_Opcode },
9334     { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9335   },
9336   /* VEX_LEN_0F46_P_0 */
9337   {
9338     { Bad_Opcode },
9339     { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9340   },
9341   /* VEX_LEN_0F47_P_0 */
9342   {
9343     { Bad_Opcode },
9344     { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9345   },
9346   /* VEX_LEN_0F4B_P_2 */
9347   {
9348     { Bad_Opcode },
9349     { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9350   },
9351
9352   /* VEX_LEN_0F51_P_1 */
9353   {
9354     { VEX_W_TABLE (VEX_W_0F51_P_1) },
9355     { VEX_W_TABLE (VEX_W_0F51_P_1) },
9356   },
9357
9358   /* VEX_LEN_0F51_P_3 */
9359   {
9360     { VEX_W_TABLE (VEX_W_0F51_P_3) },
9361     { VEX_W_TABLE (VEX_W_0F51_P_3) },
9362   },
9363
9364   /* VEX_LEN_0F52_P_1 */
9365   {
9366     { VEX_W_TABLE (VEX_W_0F52_P_1) },
9367     { VEX_W_TABLE (VEX_W_0F52_P_1) },
9368   },
9369
9370   /* VEX_LEN_0F53_P_1 */
9371   {
9372     { VEX_W_TABLE (VEX_W_0F53_P_1) },
9373     { VEX_W_TABLE (VEX_W_0F53_P_1) },
9374   },
9375
9376   /* VEX_LEN_0F58_P_1 */
9377   {
9378     { VEX_W_TABLE (VEX_W_0F58_P_1) },
9379     { VEX_W_TABLE (VEX_W_0F58_P_1) },
9380   },
9381
9382   /* VEX_LEN_0F58_P_3 */
9383   {
9384     { VEX_W_TABLE (VEX_W_0F58_P_3) },
9385     { VEX_W_TABLE (VEX_W_0F58_P_3) },
9386   },
9387
9388   /* VEX_LEN_0F59_P_1 */
9389   {
9390     { VEX_W_TABLE (VEX_W_0F59_P_1) },
9391     { VEX_W_TABLE (VEX_W_0F59_P_1) },
9392   },
9393
9394   /* VEX_LEN_0F59_P_3 */
9395   {
9396     { VEX_W_TABLE (VEX_W_0F59_P_3) },
9397     { VEX_W_TABLE (VEX_W_0F59_P_3) },
9398   },
9399
9400   /* VEX_LEN_0F5A_P_1 */
9401   {
9402     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9403     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9404   },
9405
9406   /* VEX_LEN_0F5A_P_3 */
9407   {
9408     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9409     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9410   },
9411
9412   /* VEX_LEN_0F5C_P_1 */
9413   {
9414     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9415     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9416   },
9417
9418   /* VEX_LEN_0F5C_P_3 */
9419   {
9420     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9421     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9422   },
9423
9424   /* VEX_LEN_0F5D_P_1 */
9425   {
9426     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9427     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9428   },
9429
9430   /* VEX_LEN_0F5D_P_3 */
9431   {
9432     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9433     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9434   },
9435
9436   /* VEX_LEN_0F5E_P_1 */
9437   {
9438     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9439     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9440   },
9441
9442   /* VEX_LEN_0F5E_P_3 */
9443   {
9444     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9445     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9446   },
9447
9448   /* VEX_LEN_0F5F_P_1 */
9449   {
9450     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9451     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9452   },
9453
9454   /* VEX_LEN_0F5F_P_3 */
9455   {
9456     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9457     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9458   },
9459
9460   /* VEX_LEN_0F6E_P_2 */
9461   {
9462     { "vmovK",          { XMScalar, Edq } },
9463     { "vmovK",          { XMScalar, Edq } },
9464   },
9465
9466   /* VEX_LEN_0F7E_P_1 */
9467   {
9468     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9469     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9470   },
9471
9472   /* VEX_LEN_0F7E_P_2 */
9473   {
9474     { "vmovK",          { Edq, XMScalar } },
9475     { "vmovK",          { Edq, XMScalar } },
9476   },
9477
9478   /* VEX_LEN_0F90_P_0 */
9479   {
9480     { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9481   },
9482
9483   /* VEX_LEN_0F91_P_0 */
9484   {
9485     { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9486   },
9487
9488   /* VEX_LEN_0F92_P_0 */
9489   {
9490     { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9491   },
9492
9493   /* VEX_LEN_0F93_P_0 */
9494   {
9495     { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9496   },
9497
9498   /* VEX_LEN_0F98_P_0 */
9499   {
9500     { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9501   },
9502
9503   /* VEX_LEN_0FAE_R_2_M_0 */
9504   {
9505     { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) },
9506   },
9507
9508   /* VEX_LEN_0FAE_R_3_M_0 */
9509   {
9510     { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) },
9511   },
9512
9513   /* VEX_LEN_0FC2_P_1 */
9514   {
9515     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9516     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9517   },
9518
9519   /* VEX_LEN_0FC2_P_3 */
9520   {
9521     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9522     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9523   },
9524
9525   /* VEX_LEN_0FC4_P_2 */
9526   {
9527     { VEX_W_TABLE (VEX_W_0FC4_P_2) },
9528   },
9529
9530   /* VEX_LEN_0FC5_P_2 */
9531   {
9532     { VEX_W_TABLE (VEX_W_0FC5_P_2) },
9533   },
9534
9535   /* VEX_LEN_0FD6_P_2 */
9536   {
9537     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9538     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9539   },
9540
9541   /* VEX_LEN_0FF7_P_2 */
9542   {
9543     { VEX_W_TABLE (VEX_W_0FF7_P_2) },
9544   },
9545
9546   /* VEX_LEN_0F3816_P_2 */
9547   {
9548     { Bad_Opcode },
9549     { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9550   },
9551
9552   /* VEX_LEN_0F3819_P_2 */
9553   {
9554     { Bad_Opcode },
9555     { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9556   },
9557
9558   /* VEX_LEN_0F381A_P_2_M_0 */
9559   {
9560     { Bad_Opcode },
9561     { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9562   },
9563
9564   /* VEX_LEN_0F3836_P_2 */
9565   {
9566     { Bad_Opcode },
9567     { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9568   },
9569
9570   /* VEX_LEN_0F3841_P_2 */
9571   {
9572     { VEX_W_TABLE (VEX_W_0F3841_P_2) },
9573   },
9574
9575   /* VEX_LEN_0F385A_P_2_M_0 */
9576   {
9577     { Bad_Opcode },
9578     { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
9579   },
9580
9581   /* VEX_LEN_0F38DB_P_2 */
9582   {
9583     { VEX_W_TABLE (VEX_W_0F38DB_P_2) },
9584   },
9585
9586   /* VEX_LEN_0F38DC_P_2 */
9587   {
9588     { VEX_W_TABLE (VEX_W_0F38DC_P_2) },
9589   },
9590
9591   /* VEX_LEN_0F38DD_P_2 */
9592   {
9593     { VEX_W_TABLE (VEX_W_0F38DD_P_2) },
9594   },
9595
9596   /* VEX_LEN_0F38DE_P_2 */
9597   {
9598     { VEX_W_TABLE (VEX_W_0F38DE_P_2) },
9599   },
9600
9601   /* VEX_LEN_0F38DF_P_2 */
9602   {
9603     { VEX_W_TABLE (VEX_W_0F38DF_P_2) },
9604   },
9605
9606   /* VEX_LEN_0F38F2_P_0 */
9607   {
9608     { "andnS",          { Gdq, VexGdq, Edq } },
9609   },
9610
9611   /* VEX_LEN_0F38F3_R_1_P_0 */
9612   {
9613     { "blsrS",          { VexGdq, Edq } },
9614   },
9615
9616   /* VEX_LEN_0F38F3_R_2_P_0 */
9617   {
9618     { "blsmskS",        { VexGdq, Edq } },
9619   },
9620
9621   /* VEX_LEN_0F38F3_R_3_P_0 */
9622   {
9623     { "blsiS",          { VexGdq, Edq } },
9624   },
9625
9626   /* VEX_LEN_0F38F5_P_0 */
9627   {
9628     { "bzhiS",          { Gdq, Edq, VexGdq } },
9629   },
9630
9631   /* VEX_LEN_0F38F5_P_1 */
9632   {
9633     { "pextS",          { Gdq, VexGdq, Edq } },
9634   },
9635
9636   /* VEX_LEN_0F38F5_P_3 */
9637   {
9638     { "pdepS",          { Gdq, VexGdq, Edq } },
9639   },
9640
9641   /* VEX_LEN_0F38F6_P_3 */
9642   {
9643     { "mulxS",          { Gdq, VexGdq, Edq } },
9644   },
9645
9646   /* VEX_LEN_0F38F7_P_0 */
9647   {
9648     { "bextrS",         { Gdq, Edq, VexGdq } },
9649   },
9650
9651   /* VEX_LEN_0F38F7_P_1 */
9652   {
9653     { "sarxS",          { Gdq, Edq, VexGdq } },
9654   },
9655
9656   /* VEX_LEN_0F38F7_P_2 */
9657   {
9658     { "shlxS",          { Gdq, Edq, VexGdq } },
9659   },
9660
9661   /* VEX_LEN_0F38F7_P_3 */
9662   {
9663     { "shrxS",          { Gdq, Edq, VexGdq } },
9664   },
9665
9666   /* VEX_LEN_0F3A00_P_2 */
9667   {
9668     { Bad_Opcode },
9669     { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
9670   },
9671
9672   /* VEX_LEN_0F3A01_P_2 */
9673   {
9674     { Bad_Opcode },
9675     { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
9676   },
9677
9678   /* VEX_LEN_0F3A06_P_2 */
9679   {
9680     { Bad_Opcode },
9681     { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
9682   },
9683
9684   /* VEX_LEN_0F3A0A_P_2 */
9685   {
9686     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
9687     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
9688   },
9689
9690   /* VEX_LEN_0F3A0B_P_2 */
9691   {
9692     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
9693     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
9694   },
9695
9696   /* VEX_LEN_0F3A14_P_2 */
9697   {
9698     { VEX_W_TABLE (VEX_W_0F3A14_P_2) },
9699   },
9700
9701   /* VEX_LEN_0F3A15_P_2 */
9702   {
9703     { VEX_W_TABLE (VEX_W_0F3A15_P_2) },
9704   },
9705
9706   /* VEX_LEN_0F3A16_P_2  */
9707   {
9708     { "vpextrK",        { Edq, XM, Ib } },
9709   },
9710
9711   /* VEX_LEN_0F3A17_P_2 */
9712   {
9713     { "vextractps",     { Edqd, XM, Ib } },
9714   },
9715
9716   /* VEX_LEN_0F3A18_P_2 */
9717   {
9718     { Bad_Opcode },
9719     { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
9720   },
9721
9722   /* VEX_LEN_0F3A19_P_2 */
9723   {
9724     { Bad_Opcode },
9725     { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
9726   },
9727
9728   /* VEX_LEN_0F3A20_P_2 */
9729   {
9730     { VEX_W_TABLE (VEX_W_0F3A20_P_2) },
9731   },
9732
9733   /* VEX_LEN_0F3A21_P_2 */
9734   {
9735     { VEX_W_TABLE (VEX_W_0F3A21_P_2) },
9736   },
9737
9738   /* VEX_LEN_0F3A22_P_2 */
9739   {
9740     { "vpinsrK",        { XM, Vex128, Edq, Ib } },
9741   },
9742
9743   /* VEX_LEN_0F3A30_P_2 */
9744   {
9745     { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
9746   },
9747
9748   /* VEX_LEN_0F3A32_P_2 */
9749   {
9750     { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
9751   },
9752
9753   /* VEX_LEN_0F3A38_P_2 */
9754   {
9755     { Bad_Opcode },
9756     { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
9757   },
9758
9759   /* VEX_LEN_0F3A39_P_2 */
9760   {
9761     { Bad_Opcode },
9762     { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
9763   },
9764
9765   /* VEX_LEN_0F3A41_P_2 */
9766   {
9767     { VEX_W_TABLE (VEX_W_0F3A41_P_2) },
9768   },
9769
9770   /* VEX_LEN_0F3A44_P_2 */
9771   {
9772     { VEX_W_TABLE (VEX_W_0F3A44_P_2) },
9773   },
9774
9775   /* VEX_LEN_0F3A46_P_2 */
9776   {
9777     { Bad_Opcode },
9778     { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
9779   },
9780
9781   /* VEX_LEN_0F3A60_P_2 */
9782   {
9783     { VEX_W_TABLE (VEX_W_0F3A60_P_2) },
9784   },
9785
9786   /* VEX_LEN_0F3A61_P_2 */
9787   {
9788     { VEX_W_TABLE (VEX_W_0F3A61_P_2) },
9789   },
9790
9791   /* VEX_LEN_0F3A62_P_2 */
9792   {
9793     { VEX_W_TABLE (VEX_W_0F3A62_P_2) },
9794   },
9795
9796   /* VEX_LEN_0F3A63_P_2 */
9797   {
9798     { VEX_W_TABLE (VEX_W_0F3A63_P_2) },
9799   },
9800
9801   /* VEX_LEN_0F3A6A_P_2 */
9802   {
9803     { "vfmaddss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9804   },
9805
9806   /* VEX_LEN_0F3A6B_P_2 */
9807   {
9808     { "vfmaddsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9809   },
9810
9811   /* VEX_LEN_0F3A6E_P_2 */
9812   {
9813     { "vfmsubss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9814   },
9815
9816   /* VEX_LEN_0F3A6F_P_2 */
9817   {
9818     { "vfmsubsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9819   },
9820
9821   /* VEX_LEN_0F3A7A_P_2 */
9822   {
9823     { "vfnmaddss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9824   },
9825
9826   /* VEX_LEN_0F3A7B_P_2 */
9827   {
9828     { "vfnmaddsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9829   },
9830
9831   /* VEX_LEN_0F3A7E_P_2 */
9832   {
9833     { "vfnmsubss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9834   },
9835
9836   /* VEX_LEN_0F3A7F_P_2 */
9837   {
9838     { "vfnmsubsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9839   },
9840
9841   /* VEX_LEN_0F3ADF_P_2 */
9842   {
9843     { VEX_W_TABLE (VEX_W_0F3ADF_P_2) },
9844   },
9845
9846   /* VEX_LEN_0F3AF0_P_3 */
9847   {
9848     { "rorxS",          { Gdq, Edq, Ib } },
9849   },
9850
9851   /* VEX_LEN_0FXOP_08_CC */
9852   {
9853      { "vpcomb",        { XM, Vex128, EXx, Ib } },
9854   },
9855
9856   /* VEX_LEN_0FXOP_08_CD */
9857   {
9858      { "vpcomw",        { XM, Vex128, EXx, Ib } },
9859   },
9860
9861   /* VEX_LEN_0FXOP_08_CE */
9862   {
9863      { "vpcomd",        { XM, Vex128, EXx, Ib } },
9864   },
9865
9866   /* VEX_LEN_0FXOP_08_CF */
9867   {
9868      { "vpcomq",        { XM, Vex128, EXx, Ib } },
9869   },
9870
9871   /* VEX_LEN_0FXOP_08_EC */
9872   {
9873      { "vpcomub",       { XM, Vex128, EXx, Ib } },
9874   },
9875
9876   /* VEX_LEN_0FXOP_08_ED */
9877   {
9878      { "vpcomuw",       { XM, Vex128, EXx, Ib } },
9879   },
9880
9881   /* VEX_LEN_0FXOP_08_EE */
9882   {
9883      { "vpcomud",       { XM, Vex128, EXx, Ib } },
9884   },
9885
9886   /* VEX_LEN_0FXOP_08_EF */
9887   {
9888      { "vpcomuq",       { XM, Vex128, EXx, Ib } },
9889   },
9890
9891   /* VEX_LEN_0FXOP_09_80 */
9892   {
9893     { "vfrczps",        { XM, EXxmm } },
9894     { "vfrczps",        { XM, EXymmq } },
9895   },
9896
9897   /* VEX_LEN_0FXOP_09_81 */
9898   {
9899     { "vfrczpd",        { XM, EXxmm } },
9900     { "vfrczpd",        { XM, EXymmq } },
9901   },
9902 };
9903
9904 static const struct dis386 vex_w_table[][2] = {
9905   {
9906     /* VEX_W_0F10_P_0 */
9907     { "vmovups",        { XM, EXx } },
9908   },
9909   {
9910     /* VEX_W_0F10_P_1 */
9911     { "vmovss",         { XMVexScalar, VexScalar, EXdScalar } },
9912   },
9913   {
9914     /* VEX_W_0F10_P_2 */
9915     { "vmovupd",        { XM, EXx } },
9916   },
9917   {
9918     /* VEX_W_0F10_P_3 */
9919     { "vmovsd",         { XMVexScalar, VexScalar, EXqScalar } },
9920   },
9921   {
9922     /* VEX_W_0F11_P_0 */
9923     { "vmovups",        { EXxS, XM } },
9924   },
9925   {
9926     /* VEX_W_0F11_P_1 */
9927     { "vmovss",         { EXdVexScalarS, VexScalar, XMScalar } },
9928   },
9929   {
9930     /* VEX_W_0F11_P_2 */
9931     { "vmovupd",        { EXxS, XM } },
9932   },
9933   {
9934     /* VEX_W_0F11_P_3 */
9935     { "vmovsd",         { EXqVexScalarS, VexScalar, XMScalar } },
9936   },
9937   {
9938     /* VEX_W_0F12_P_0_M_0 */
9939     { "vmovlps",        { XM, Vex128, EXq } },
9940   },
9941   {
9942     /* VEX_W_0F12_P_0_M_1 */
9943     { "vmovhlps",       { XM, Vex128, EXq } },
9944   },
9945   {
9946     /* VEX_W_0F12_P_1 */
9947     { "vmovsldup",      { XM, EXx } },
9948   },
9949   {
9950     /* VEX_W_0F12_P_2 */
9951     { "vmovlpd",        { XM, Vex128, EXq } },
9952   },
9953   {
9954     /* VEX_W_0F12_P_3 */
9955     { "vmovddup",       { XM, EXymmq } },
9956   },
9957   {
9958     /* VEX_W_0F13_M_0 */
9959     { "vmovlpX",        { EXq, XM } },
9960   },
9961   {
9962     /* VEX_W_0F14 */
9963     { "vunpcklpX",      { XM, Vex, EXx } },
9964   },
9965   {
9966     /* VEX_W_0F15 */
9967     { "vunpckhpX",      { XM, Vex, EXx } },
9968   },
9969   {
9970     /* VEX_W_0F16_P_0_M_0 */
9971     { "vmovhps",        { XM, Vex128, EXq } },
9972   },
9973   {
9974     /* VEX_W_0F16_P_0_M_1 */
9975     { "vmovlhps",       { XM, Vex128, EXq } },
9976   },
9977   {
9978     /* VEX_W_0F16_P_1 */
9979     { "vmovshdup",      { XM, EXx } },
9980   },
9981   {
9982     /* VEX_W_0F16_P_2 */
9983     { "vmovhpd",        { XM, Vex128, EXq } },
9984   },
9985   {
9986     /* VEX_W_0F17_M_0 */
9987     { "vmovhpX",        { EXq, XM } },
9988   },
9989   {
9990     /* VEX_W_0F28 */
9991     { "vmovapX",        { XM, EXx } },
9992   },
9993   {
9994     /* VEX_W_0F29 */
9995     { "vmovapX",        { EXxS, XM } },
9996   },
9997   {
9998     /* VEX_W_0F2B_M_0 */
9999     { "vmovntpX",       { Mx, XM } },
10000   },
10001   {
10002     /* VEX_W_0F2E_P_0 */
10003     { "vucomiss",       { XMScalar, EXdScalar } },
10004   },
10005   {
10006     /* VEX_W_0F2E_P_2 */
10007     { "vucomisd",       { XMScalar, EXqScalar } },
10008   },
10009   {
10010     /* VEX_W_0F2F_P_0 */
10011     { "vcomiss",        { XMScalar, EXdScalar } },
10012   },
10013   {
10014     /* VEX_W_0F2F_P_2 */
10015     { "vcomisd",        { XMScalar, EXqScalar } },
10016   },
10017   {
10018     /* VEX_W_0F41_P_0_LEN_1 */
10019     { "kandw",          { MaskG, MaskVex, MaskR } },
10020   },
10021   {
10022     /* VEX_W_0F42_P_0_LEN_1 */
10023     { "kandnw",         { MaskG, MaskVex, MaskR } },
10024   },
10025   {
10026     /* VEX_W_0F44_P_0_LEN_0 */
10027     { "knotw",          { MaskG, MaskR } },
10028   },
10029   {
10030     /* VEX_W_0F45_P_0_LEN_1 */
10031     { "korw",           { MaskG, MaskVex, MaskR } },
10032   },
10033   {
10034     /* VEX_W_0F46_P_0_LEN_1 */
10035     { "kxnorw",         { MaskG, MaskVex, MaskR } },
10036   },
10037   {
10038     /* VEX_W_0F47_P_0_LEN_1 */
10039     { "kxorw",          { MaskG, MaskVex, MaskR } },
10040   },
10041   {
10042     /* VEX_W_0F4B_P_2_LEN_1 */
10043     { "kunpckbw",       { MaskG, MaskVex, MaskR } },
10044   },
10045   {
10046     /* VEX_W_0F50_M_0 */
10047     { "vmovmskpX",      { Gdq, XS } },
10048   },
10049   {
10050     /* VEX_W_0F51_P_0 */
10051     { "vsqrtps",        { XM, EXx } },
10052   },
10053   {
10054     /* VEX_W_0F51_P_1 */
10055     { "vsqrtss",        { XMScalar, VexScalar, EXdScalar } },
10056   },
10057   {
10058     /* VEX_W_0F51_P_2  */
10059     { "vsqrtpd",        { XM, EXx } },
10060   },
10061   {
10062     /* VEX_W_0F51_P_3 */
10063     { "vsqrtsd",        { XMScalar, VexScalar, EXqScalar } },
10064   },
10065   {
10066     /* VEX_W_0F52_P_0 */
10067     { "vrsqrtps",       { XM, EXx } },
10068   },
10069   {
10070     /* VEX_W_0F52_P_1 */
10071     { "vrsqrtss",       { XMScalar, VexScalar, EXdScalar } },
10072   },
10073   {
10074     /* VEX_W_0F53_P_0  */
10075     { "vrcpps",         { XM, EXx } },
10076   },
10077   {
10078     /* VEX_W_0F53_P_1  */
10079     { "vrcpss",         { XMScalar, VexScalar, EXdScalar } },
10080   },
10081   {
10082     /* VEX_W_0F58_P_0  */
10083     { "vaddps",         { XM, Vex, EXx } },
10084   },
10085   {
10086     /* VEX_W_0F58_P_1  */
10087     { "vaddss",         { XMScalar, VexScalar, EXdScalar } },
10088   },
10089   {
10090     /* VEX_W_0F58_P_2  */
10091     { "vaddpd",         { XM, Vex, EXx } },
10092   },
10093   {
10094     /* VEX_W_0F58_P_3  */
10095     { "vaddsd",         { XMScalar, VexScalar, EXqScalar } },
10096   },
10097   {
10098     /* VEX_W_0F59_P_0  */
10099     { "vmulps",         { XM, Vex, EXx } },
10100   },
10101   {
10102     /* VEX_W_0F59_P_1  */
10103     { "vmulss",         { XMScalar, VexScalar, EXdScalar } },
10104   },
10105   {
10106     /* VEX_W_0F59_P_2  */
10107     { "vmulpd",         { XM, Vex, EXx } },
10108   },
10109   {
10110     /* VEX_W_0F59_P_3  */
10111     { "vmulsd",         { XMScalar, VexScalar, EXqScalar } },
10112   },
10113   {
10114     /* VEX_W_0F5A_P_0  */
10115     { "vcvtps2pd",      { XM, EXxmmq } },
10116   },
10117   {
10118     /* VEX_W_0F5A_P_1  */
10119     { "vcvtss2sd",      { XMScalar, VexScalar, EXdScalar } },
10120   },
10121   {
10122     /* VEX_W_0F5A_P_3  */
10123     { "vcvtsd2ss",      { XMScalar, VexScalar, EXqScalar } },
10124   },
10125   {
10126     /* VEX_W_0F5B_P_0  */
10127     { "vcvtdq2ps",      { XM, EXx } },
10128   },
10129   {
10130     /* VEX_W_0F5B_P_1  */
10131     { "vcvttps2dq",     { XM, EXx } },
10132   },
10133   {
10134     /* VEX_W_0F5B_P_2  */
10135     { "vcvtps2dq",      { XM, EXx } },
10136   },
10137   {
10138     /* VEX_W_0F5C_P_0  */
10139     { "vsubps",         { XM, Vex, EXx } },
10140   },
10141   {
10142     /* VEX_W_0F5C_P_1  */
10143     { "vsubss",         { XMScalar, VexScalar, EXdScalar } },
10144   },
10145   {
10146     /* VEX_W_0F5C_P_2  */
10147     { "vsubpd",         { XM, Vex, EXx } },
10148   },
10149   {
10150     /* VEX_W_0F5C_P_3  */
10151     { "vsubsd",         { XMScalar, VexScalar, EXqScalar } },
10152   },
10153   {
10154     /* VEX_W_0F5D_P_0  */
10155     { "vminps",         { XM, Vex, EXx } },
10156   },
10157   {
10158     /* VEX_W_0F5D_P_1  */
10159     { "vminss",         { XMScalar, VexScalar, EXdScalar } },
10160   },
10161   {
10162     /* VEX_W_0F5D_P_2  */
10163     { "vminpd",         { XM, Vex, EXx } },
10164   },
10165   {
10166     /* VEX_W_0F5D_P_3  */
10167     { "vminsd",         { XMScalar, VexScalar, EXqScalar } },
10168   },
10169   {
10170     /* VEX_W_0F5E_P_0  */
10171     { "vdivps",         { XM, Vex, EXx } },
10172   },
10173   {
10174     /* VEX_W_0F5E_P_1  */
10175     { "vdivss",         { XMScalar, VexScalar, EXdScalar } },
10176   },
10177   {
10178     /* VEX_W_0F5E_P_2  */
10179     { "vdivpd",         { XM, Vex, EXx } },
10180   },
10181   {
10182     /* VEX_W_0F5E_P_3  */
10183     { "vdivsd",         { XMScalar, VexScalar, EXqScalar } },
10184   },
10185   {
10186     /* VEX_W_0F5F_P_0  */
10187     { "vmaxps",         { XM, Vex, EXx } },
10188   },
10189   {
10190     /* VEX_W_0F5F_P_1  */
10191     { "vmaxss",         { XMScalar, VexScalar, EXdScalar } },
10192   },
10193   {
10194     /* VEX_W_0F5F_P_2  */
10195     { "vmaxpd",         { XM, Vex, EXx } },
10196   },
10197   {
10198     /* VEX_W_0F5F_P_3  */
10199     { "vmaxsd",         { XMScalar, VexScalar, EXqScalar } },
10200   },
10201   {
10202     /* VEX_W_0F60_P_2  */
10203     { "vpunpcklbw",     { XM, Vex, EXx } },
10204   },
10205   {
10206     /* VEX_W_0F61_P_2  */
10207     { "vpunpcklwd",     { XM, Vex, EXx } },
10208   },
10209   {
10210     /* VEX_W_0F62_P_2  */
10211     { "vpunpckldq",     { XM, Vex, EXx } },
10212   },
10213   {
10214     /* VEX_W_0F63_P_2  */
10215     { "vpacksswb",      { XM, Vex, EXx } },
10216   },
10217   {
10218     /* VEX_W_0F64_P_2  */
10219     { "vpcmpgtb",       { XM, Vex, EXx } },
10220   },
10221   {
10222     /* VEX_W_0F65_P_2  */
10223     { "vpcmpgtw",       { XM, Vex, EXx } },
10224   },
10225   {
10226     /* VEX_W_0F66_P_2  */
10227     { "vpcmpgtd",       { XM, Vex, EXx } },
10228   },
10229   {
10230     /* VEX_W_0F67_P_2  */
10231     { "vpackuswb",      { XM, Vex, EXx } },
10232   },
10233   {
10234     /* VEX_W_0F68_P_2  */
10235     { "vpunpckhbw",     { XM, Vex, EXx } },
10236   },
10237   {
10238     /* VEX_W_0F69_P_2  */
10239     { "vpunpckhwd",     { XM, Vex, EXx } },
10240   },
10241   {
10242     /* VEX_W_0F6A_P_2  */
10243     { "vpunpckhdq",     { XM, Vex, EXx } },
10244   },
10245   {
10246     /* VEX_W_0F6B_P_2  */
10247     { "vpackssdw",      { XM, Vex, EXx } },
10248   },
10249   {
10250     /* VEX_W_0F6C_P_2  */
10251     { "vpunpcklqdq",    { XM, Vex, EXx } },
10252   },
10253   {
10254     /* VEX_W_0F6D_P_2  */
10255     { "vpunpckhqdq",    { XM, Vex, EXx } },
10256   },
10257   {
10258     /* VEX_W_0F6F_P_1  */
10259     { "vmovdqu",        { XM, EXx } },
10260   },
10261   {
10262     /* VEX_W_0F6F_P_2  */
10263     { "vmovdqa",        { XM, EXx } },
10264   },
10265   {
10266     /* VEX_W_0F70_P_1 */
10267     { "vpshufhw",       { XM, EXx, Ib } },
10268   },
10269   {
10270     /* VEX_W_0F70_P_2 */
10271     { "vpshufd",        { XM, EXx, Ib } },
10272   },
10273   {
10274     /* VEX_W_0F70_P_3 */
10275     { "vpshuflw",       { XM, EXx, Ib } },
10276   },
10277   {
10278     /* VEX_W_0F71_R_2_P_2  */
10279     { "vpsrlw",         { Vex, XS, Ib } },
10280   },
10281   {
10282     /* VEX_W_0F71_R_4_P_2  */
10283     { "vpsraw",         { Vex, XS, Ib } },
10284   },
10285   {
10286     /* VEX_W_0F71_R_6_P_2  */
10287     { "vpsllw",         { Vex, XS, Ib } },
10288   },
10289   {
10290     /* VEX_W_0F72_R_2_P_2  */
10291     { "vpsrld",         { Vex, XS, Ib } },
10292   },
10293   {
10294     /* VEX_W_0F72_R_4_P_2  */
10295     { "vpsrad",         { Vex, XS, Ib } },
10296   },
10297   {
10298     /* VEX_W_0F72_R_6_P_2  */
10299     { "vpslld",         { Vex, XS, Ib } },
10300   },
10301   {
10302     /* VEX_W_0F73_R_2_P_2  */
10303     { "vpsrlq",         { Vex, XS, Ib } },
10304   },
10305   {
10306     /* VEX_W_0F73_R_3_P_2  */
10307     { "vpsrldq",        { Vex, XS, Ib } },
10308   },
10309   {
10310     /* VEX_W_0F73_R_6_P_2  */
10311     { "vpsllq",         { Vex, XS, Ib } },
10312   },
10313   {
10314     /* VEX_W_0F73_R_7_P_2  */
10315     { "vpslldq",        { Vex, XS, Ib } },
10316   },
10317   {
10318     /* VEX_W_0F74_P_2 */
10319     { "vpcmpeqb",       { XM, Vex, EXx } },
10320   },
10321   {
10322     /* VEX_W_0F75_P_2 */
10323     { "vpcmpeqw",       { XM, Vex, EXx } },
10324   },
10325   {
10326     /* VEX_W_0F76_P_2 */
10327     { "vpcmpeqd",       { XM, Vex, EXx } },
10328   },
10329   {
10330     /* VEX_W_0F77_P_0 */
10331     { "",               { VZERO } },
10332   },
10333   {
10334     /* VEX_W_0F7C_P_2 */
10335     { "vhaddpd",        { XM, Vex, EXx } },
10336   },
10337   {
10338     /* VEX_W_0F7C_P_3 */
10339     { "vhaddps",        { XM, Vex, EXx } },
10340   },
10341   {
10342     /* VEX_W_0F7D_P_2 */
10343     { "vhsubpd",        { XM, Vex, EXx } },
10344   },
10345   {
10346     /* VEX_W_0F7D_P_3 */
10347     { "vhsubps",        { XM, Vex, EXx } },
10348   },
10349   {
10350     /* VEX_W_0F7E_P_1 */
10351     { "vmovq",          { XMScalar, EXqScalar } },
10352   },
10353   {
10354     /* VEX_W_0F7F_P_1 */
10355     { "vmovdqu",        { EXxS, XM } },
10356   },
10357   {
10358     /* VEX_W_0F7F_P_2 */
10359     { "vmovdqa",        { EXxS, XM } },
10360   },
10361   {
10362     /* VEX_W_0F90_P_0_LEN_0 */
10363     { "kmovw",          { MaskG, MaskE } },
10364   },
10365   {
10366     /* VEX_W_0F91_P_0_LEN_0 */
10367     { "kmovw",          { Ew, MaskG } },
10368   },
10369   {
10370     /* VEX_W_0F92_P_0_LEN_0 */
10371     { "kmovw",          { MaskG, Rdq } },
10372   },
10373   {
10374     /* VEX_W_0F93_P_0_LEN_0 */
10375     { "kmovw",          { Gdq, MaskR } },
10376   },
10377   {
10378     /* VEX_W_0F98_P_0_LEN_0 */
10379     { "kortestw",       { MaskG, MaskR } },
10380   },
10381   {
10382     /* VEX_W_0FAE_R_2_M_0 */
10383     { "vldmxcsr",       { Md } },
10384   },
10385   {
10386     /* VEX_W_0FAE_R_3_M_0 */
10387     { "vstmxcsr",       { Md } },
10388   },
10389   {
10390     /* VEX_W_0FC2_P_0 */
10391     { "vcmpps",         { XM, Vex, EXx, VCMP } },
10392   },
10393   {
10394     /* VEX_W_0FC2_P_1 */
10395     { "vcmpss",         { XMScalar, VexScalar, EXdScalar, VCMP } },
10396   },
10397   {
10398     /* VEX_W_0FC2_P_2 */
10399     { "vcmppd",         { XM, Vex, EXx, VCMP } },
10400   },
10401   {
10402     /* VEX_W_0FC2_P_3 */
10403     { "vcmpsd",         { XMScalar, VexScalar, EXqScalar, VCMP } },
10404   },
10405   {
10406     /* VEX_W_0FC4_P_2 */
10407     { "vpinsrw",        { XM, Vex128, Edqw, Ib } },
10408   },
10409   {
10410     /* VEX_W_0FC5_P_2 */
10411     { "vpextrw",        { Gdq, XS, Ib } },
10412   },
10413   {
10414     /* VEX_W_0FD0_P_2 */
10415     { "vaddsubpd",      { XM, Vex, EXx } },
10416   },
10417   {
10418     /* VEX_W_0FD0_P_3 */
10419     { "vaddsubps",      { XM, Vex, EXx } },
10420   },
10421   {
10422     /* VEX_W_0FD1_P_2 */
10423     { "vpsrlw",         { XM, Vex, EXxmm } },
10424   },
10425   {
10426     /* VEX_W_0FD2_P_2 */
10427     { "vpsrld",         { XM, Vex, EXxmm } },
10428   },
10429   {
10430     /* VEX_W_0FD3_P_2 */
10431     { "vpsrlq",         { XM, Vex, EXxmm } },
10432   },
10433   {
10434     /* VEX_W_0FD4_P_2 */
10435     { "vpaddq",         { XM, Vex, EXx } },
10436   },
10437   {
10438     /* VEX_W_0FD5_P_2 */
10439     { "vpmullw",        { XM, Vex, EXx } },
10440   },
10441   {
10442     /* VEX_W_0FD6_P_2 */
10443     { "vmovq",          { EXqScalarS, XMScalar } },
10444   },
10445   {
10446     /* VEX_W_0FD7_P_2_M_1 */
10447     { "vpmovmskb",      { Gdq, XS } },
10448   },
10449   {
10450     /* VEX_W_0FD8_P_2 */
10451     { "vpsubusb",       { XM, Vex, EXx } },
10452   },
10453   {
10454     /* VEX_W_0FD9_P_2 */
10455     { "vpsubusw",       { XM, Vex, EXx } },
10456   },
10457   {
10458     /* VEX_W_0FDA_P_2 */
10459     { "vpminub",        { XM, Vex, EXx } },
10460   },
10461   {
10462     /* VEX_W_0FDB_P_2 */
10463     { "vpand",          { XM, Vex, EXx } },
10464   },
10465   {
10466     /* VEX_W_0FDC_P_2 */
10467     { "vpaddusb",       { XM, Vex, EXx } },
10468   },
10469   {
10470     /* VEX_W_0FDD_P_2 */
10471     { "vpaddusw",       { XM, Vex, EXx } },
10472   },
10473   {
10474     /* VEX_W_0FDE_P_2 */
10475     { "vpmaxub",        { XM, Vex, EXx } },
10476   },
10477   {
10478     /* VEX_W_0FDF_P_2 */
10479     { "vpandn",         { XM, Vex, EXx } },
10480   },
10481   {
10482     /* VEX_W_0FE0_P_2  */
10483     { "vpavgb",         { XM, Vex, EXx } },
10484   },
10485   {
10486     /* VEX_W_0FE1_P_2  */
10487     { "vpsraw",         { XM, Vex, EXxmm } },
10488   },
10489   {
10490     /* VEX_W_0FE2_P_2  */
10491     { "vpsrad",         { XM, Vex, EXxmm } },
10492   },
10493   {
10494     /* VEX_W_0FE3_P_2  */
10495     { "vpavgw",         { XM, Vex, EXx } },
10496   },
10497   {
10498     /* VEX_W_0FE4_P_2  */
10499     { "vpmulhuw",       { XM, Vex, EXx } },
10500   },
10501   {
10502     /* VEX_W_0FE5_P_2  */
10503     { "vpmulhw",        { XM, Vex, EXx } },
10504   },
10505   {
10506     /* VEX_W_0FE6_P_1  */
10507     { "vcvtdq2pd",      { XM, EXxmmq } },
10508   },
10509   {
10510     /* VEX_W_0FE6_P_2  */
10511     { "vcvttpd2dq%XY",  { XMM, EXx } },
10512   },
10513   {
10514     /* VEX_W_0FE6_P_3  */
10515     { "vcvtpd2dq%XY",   { XMM, EXx } },
10516   },
10517   {
10518     /* VEX_W_0FE7_P_2_M_0 */
10519     { "vmovntdq",       { Mx, XM } },
10520   },
10521   {
10522     /* VEX_W_0FE8_P_2  */
10523     { "vpsubsb",        { XM, Vex, EXx } },
10524   },
10525   {
10526     /* VEX_W_0FE9_P_2  */
10527     { "vpsubsw",        { XM, Vex, EXx } },
10528   },
10529   {
10530     /* VEX_W_0FEA_P_2  */
10531     { "vpminsw",        { XM, Vex, EXx } },
10532   },
10533   {
10534     /* VEX_W_0FEB_P_2  */
10535     { "vpor",           { XM, Vex, EXx } },
10536   },
10537   {
10538     /* VEX_W_0FEC_P_2  */
10539     { "vpaddsb",        { XM, Vex, EXx } },
10540   },
10541   {
10542     /* VEX_W_0FED_P_2  */
10543     { "vpaddsw",        { XM, Vex, EXx } },
10544   },
10545   {
10546     /* VEX_W_0FEE_P_2  */
10547     { "vpmaxsw",        { XM, Vex, EXx } },
10548   },
10549   {
10550     /* VEX_W_0FEF_P_2  */
10551     { "vpxor",          { XM, Vex, EXx } },
10552   },
10553   {
10554     /* VEX_W_0FF0_P_3_M_0 */
10555     { "vlddqu",         { XM, M } },
10556   },
10557   {
10558     /* VEX_W_0FF1_P_2 */
10559     { "vpsllw",         { XM, Vex, EXxmm } },
10560   },
10561   {
10562     /* VEX_W_0FF2_P_2 */
10563     { "vpslld",         { XM, Vex, EXxmm } },
10564   },
10565   {
10566     /* VEX_W_0FF3_P_2 */
10567     { "vpsllq",         { XM, Vex, EXxmm } },
10568   },
10569   {
10570     /* VEX_W_0FF4_P_2 */
10571     { "vpmuludq",       { XM, Vex, EXx } },
10572   },
10573   {
10574     /* VEX_W_0FF5_P_2 */
10575     { "vpmaddwd",       { XM, Vex, EXx } },
10576   },
10577   {
10578     /* VEX_W_0FF6_P_2 */
10579     { "vpsadbw",        { XM, Vex, EXx } },
10580   },
10581   {
10582     /* VEX_W_0FF7_P_2 */
10583     { "vmaskmovdqu",    { XM, XS } },
10584   },
10585   {
10586     /* VEX_W_0FF8_P_2 */
10587     { "vpsubb",         { XM, Vex, EXx } },
10588   },
10589   {
10590     /* VEX_W_0FF9_P_2 */
10591     { "vpsubw",         { XM, Vex, EXx } },
10592   },
10593   {
10594     /* VEX_W_0FFA_P_2 */
10595     { "vpsubd",         { XM, Vex, EXx } },
10596   },
10597   {
10598     /* VEX_W_0FFB_P_2 */
10599     { "vpsubq",         { XM, Vex, EXx } },
10600   },
10601   {
10602     /* VEX_W_0FFC_P_2 */
10603     { "vpaddb",         { XM, Vex, EXx } },
10604   },
10605   {
10606     /* VEX_W_0FFD_P_2 */
10607     { "vpaddw",         { XM, Vex, EXx } },
10608   },
10609   {
10610     /* VEX_W_0FFE_P_2 */
10611     { "vpaddd",         { XM, Vex, EXx } },
10612   },
10613   {
10614     /* VEX_W_0F3800_P_2  */
10615     { "vpshufb",        { XM, Vex, EXx } },
10616   },
10617   {
10618     /* VEX_W_0F3801_P_2  */
10619     { "vphaddw",        { XM, Vex, EXx } },
10620   },
10621   {
10622     /* VEX_W_0F3802_P_2  */
10623     { "vphaddd",        { XM, Vex, EXx } },
10624   },
10625   {
10626     /* VEX_W_0F3803_P_2  */
10627     { "vphaddsw",       { XM, Vex, EXx } },
10628   },
10629   {
10630     /* VEX_W_0F3804_P_2  */
10631     { "vpmaddubsw",     { XM, Vex, EXx } },
10632   },
10633   {
10634     /* VEX_W_0F3805_P_2  */
10635     { "vphsubw",        { XM, Vex, EXx } },
10636   },
10637   {
10638     /* VEX_W_0F3806_P_2  */
10639     { "vphsubd",        { XM, Vex, EXx } },
10640   },
10641   {
10642     /* VEX_W_0F3807_P_2  */
10643     { "vphsubsw",       { XM, Vex, EXx } },
10644   },
10645   {
10646     /* VEX_W_0F3808_P_2  */
10647     { "vpsignb",        { XM, Vex, EXx } },
10648   },
10649   {
10650     /* VEX_W_0F3809_P_2  */
10651     { "vpsignw",        { XM, Vex, EXx } },
10652   },
10653   {
10654     /* VEX_W_0F380A_P_2  */
10655     { "vpsignd",        { XM, Vex, EXx } },
10656   },
10657   {
10658     /* VEX_W_0F380B_P_2  */
10659     { "vpmulhrsw",      { XM, Vex, EXx } },
10660   },
10661   {
10662     /* VEX_W_0F380C_P_2  */
10663     { "vpermilps",      { XM, Vex, EXx } },
10664   },
10665   {
10666     /* VEX_W_0F380D_P_2  */
10667     { "vpermilpd",      { XM, Vex, EXx } },
10668   },
10669   {
10670     /* VEX_W_0F380E_P_2  */
10671     { "vtestps",        { XM, EXx } },
10672   },
10673   {
10674     /* VEX_W_0F380F_P_2  */
10675     { "vtestpd",        { XM, EXx } },
10676   },
10677   {
10678     /* VEX_W_0F3816_P_2  */
10679     { "vpermps",        { XM, Vex, EXx } },
10680   },
10681   {
10682     /* VEX_W_0F3817_P_2 */
10683     { "vptest",         { XM, EXx } },
10684   },
10685   {
10686     /* VEX_W_0F3818_P_2 */
10687     { "vbroadcastss",   { XM, EXxmm_md } },
10688   },
10689   {
10690     /* VEX_W_0F3819_P_2 */
10691     { "vbroadcastsd",   { XM, EXxmm_mq } },
10692   },
10693   {
10694     /* VEX_W_0F381A_P_2_M_0 */
10695     { "vbroadcastf128", { XM, Mxmm } },
10696   },
10697   {
10698     /* VEX_W_0F381C_P_2 */
10699     { "vpabsb",         { XM, EXx } },
10700   },
10701   {
10702     /* VEX_W_0F381D_P_2 */
10703     { "vpabsw",         { XM, EXx } },
10704   },
10705   {
10706     /* VEX_W_0F381E_P_2 */
10707     { "vpabsd",         { XM, EXx } },
10708   },
10709   {
10710     /* VEX_W_0F3820_P_2 */
10711     { "vpmovsxbw",      { XM, EXxmmq } },
10712   },
10713   {
10714     /* VEX_W_0F3821_P_2 */
10715     { "vpmovsxbd",      { XM, EXxmmqd } },
10716   },
10717   {
10718     /* VEX_W_0F3822_P_2 */
10719     { "vpmovsxbq",      { XM, EXxmmdw } },
10720   },
10721   {
10722     /* VEX_W_0F3823_P_2 */
10723     { "vpmovsxwd",      { XM, EXxmmq } },
10724   },
10725   {
10726     /* VEX_W_0F3824_P_2 */
10727     { "vpmovsxwq",      { XM, EXxmmqd } },
10728   },
10729   {
10730     /* VEX_W_0F3825_P_2 */
10731     { "vpmovsxdq",      { XM, EXxmmq } },
10732   },
10733   {
10734     /* VEX_W_0F3828_P_2 */
10735     { "vpmuldq",        { XM, Vex, EXx } },
10736   },
10737   {
10738     /* VEX_W_0F3829_P_2 */
10739     { "vpcmpeqq",       { XM, Vex, EXx } },
10740   },
10741   {
10742     /* VEX_W_0F382A_P_2_M_0 */
10743     { "vmovntdqa",      { XM, Mx } },
10744   },
10745   {
10746     /* VEX_W_0F382B_P_2 */
10747     { "vpackusdw",      { XM, Vex, EXx } },
10748   },
10749   {
10750     /* VEX_W_0F382C_P_2_M_0 */
10751     { "vmaskmovps",     { XM, Vex, Mx } },
10752   },
10753   {
10754     /* VEX_W_0F382D_P_2_M_0 */
10755     { "vmaskmovpd",     { XM, Vex, Mx } },
10756   },
10757   {
10758     /* VEX_W_0F382E_P_2_M_0 */
10759     { "vmaskmovps",     { Mx, Vex, XM } },
10760   },
10761   {
10762     /* VEX_W_0F382F_P_2_M_0 */
10763     { "vmaskmovpd",     { Mx, Vex, XM } },
10764   },
10765   {
10766     /* VEX_W_0F3830_P_2 */
10767     { "vpmovzxbw",      { XM, EXxmmq } },
10768   },
10769   {
10770     /* VEX_W_0F3831_P_2 */
10771     { "vpmovzxbd",      { XM, EXxmmqd } },
10772   },
10773   {
10774     /* VEX_W_0F3832_P_2 */
10775     { "vpmovzxbq",      { XM, EXxmmdw } },
10776   },
10777   {
10778     /* VEX_W_0F3833_P_2 */
10779     { "vpmovzxwd",      { XM, EXxmmq } },
10780   },
10781   {
10782     /* VEX_W_0F3834_P_2 */
10783     { "vpmovzxwq",      { XM, EXxmmqd } },
10784   },
10785   {
10786     /* VEX_W_0F3835_P_2 */
10787     { "vpmovzxdq",      { XM, EXxmmq } },
10788   },
10789   {
10790     /* VEX_W_0F3836_P_2  */
10791     { "vpermd",         { XM, Vex, EXx } },
10792   },
10793   {
10794     /* VEX_W_0F3837_P_2 */
10795     { "vpcmpgtq",       { XM, Vex, EXx } },
10796   },
10797   {
10798     /* VEX_W_0F3838_P_2 */
10799     { "vpminsb",        { XM, Vex, EXx } },
10800   },
10801   {
10802     /* VEX_W_0F3839_P_2 */
10803     { "vpminsd",        { XM, Vex, EXx } },
10804   },
10805   {
10806     /* VEX_W_0F383A_P_2 */
10807     { "vpminuw",        { XM, Vex, EXx } },
10808   },
10809   {
10810     /* VEX_W_0F383B_P_2 */
10811     { "vpminud",        { XM, Vex, EXx } },
10812   },
10813   {
10814     /* VEX_W_0F383C_P_2 */
10815     { "vpmaxsb",        { XM, Vex, EXx } },
10816   },
10817   {
10818     /* VEX_W_0F383D_P_2 */
10819     { "vpmaxsd",        { XM, Vex, EXx } },
10820   },
10821   {
10822     /* VEX_W_0F383E_P_2 */
10823     { "vpmaxuw",        { XM, Vex, EXx } },
10824   },
10825   {
10826     /* VEX_W_0F383F_P_2 */
10827     { "vpmaxud",        { XM, Vex, EXx } },
10828   },
10829   {
10830     /* VEX_W_0F3840_P_2 */
10831     { "vpmulld",        { XM, Vex, EXx } },
10832   },
10833   {
10834     /* VEX_W_0F3841_P_2 */
10835     { "vphminposuw",    { XM, EXx } },
10836   },
10837   {
10838     /* VEX_W_0F3846_P_2 */
10839     { "vpsravd",        { XM, Vex, EXx } },
10840   },
10841   {
10842     /* VEX_W_0F3858_P_2 */
10843     { "vpbroadcastd", { XM, EXxmm_md } },
10844   },
10845   {
10846     /* VEX_W_0F3859_P_2 */
10847     { "vpbroadcastq",   { XM, EXxmm_mq } },
10848   },
10849   {
10850     /* VEX_W_0F385A_P_2_M_0 */
10851     { "vbroadcasti128", { XM, Mxmm } },
10852   },
10853   {
10854     /* VEX_W_0F3878_P_2 */
10855     { "vpbroadcastb",   { XM, EXxmm_mb } },
10856   },
10857   {
10858     /* VEX_W_0F3879_P_2 */
10859     { "vpbroadcastw",   { XM, EXxmm_mw } },
10860   },
10861   {
10862     /* VEX_W_0F38DB_P_2 */
10863     { "vaesimc",        { XM, EXx } },
10864   },
10865   {
10866     /* VEX_W_0F38DC_P_2 */
10867     { "vaesenc",        { XM, Vex128, EXx } },
10868   },
10869   {
10870     /* VEX_W_0F38DD_P_2 */
10871     { "vaesenclast",    { XM, Vex128, EXx } },
10872   },
10873   {
10874     /* VEX_W_0F38DE_P_2 */
10875     { "vaesdec",        { XM, Vex128, EXx } },
10876   },
10877   {
10878     /* VEX_W_0F38DF_P_2 */
10879     { "vaesdeclast",    { XM, Vex128, EXx } },
10880   },
10881   {
10882     /* VEX_W_0F3A00_P_2 */
10883     { Bad_Opcode },
10884     { "vpermq",         { XM, EXx, Ib } },
10885   },
10886   {
10887     /* VEX_W_0F3A01_P_2 */
10888     { Bad_Opcode },
10889     { "vpermpd",        { XM, EXx, Ib } },
10890   },
10891   {
10892     /* VEX_W_0F3A02_P_2 */
10893     { "vpblendd",       { XM, Vex, EXx, Ib } },
10894   },
10895   {
10896     /* VEX_W_0F3A04_P_2 */
10897     { "vpermilps",      { XM, EXx, Ib } },
10898   },
10899   {
10900     /* VEX_W_0F3A05_P_2 */
10901     { "vpermilpd",      { XM, EXx, Ib } },
10902   },
10903   {
10904     /* VEX_W_0F3A06_P_2 */
10905     { "vperm2f128",     { XM, Vex256, EXx, Ib } },
10906   },
10907   {
10908     /* VEX_W_0F3A08_P_2 */
10909     { "vroundps",       { XM, EXx, Ib } },
10910   },
10911   {
10912     /* VEX_W_0F3A09_P_2 */
10913     { "vroundpd",       { XM, EXx, Ib } },
10914   },
10915   {
10916     /* VEX_W_0F3A0A_P_2 */
10917     { "vroundss",       { XMScalar, VexScalar, EXdScalar, Ib } },
10918   },
10919   {
10920     /* VEX_W_0F3A0B_P_2 */
10921     { "vroundsd",       { XMScalar, VexScalar, EXqScalar, Ib } },
10922   },
10923   {
10924     /* VEX_W_0F3A0C_P_2 */
10925     { "vblendps",       { XM, Vex, EXx, Ib } },
10926   },
10927   {
10928     /* VEX_W_0F3A0D_P_2 */
10929     { "vblendpd",       { XM, Vex, EXx, Ib } },
10930   },
10931   {
10932     /* VEX_W_0F3A0E_P_2 */
10933     { "vpblendw",       { XM, Vex, EXx, Ib } },
10934   },
10935   {
10936     /* VEX_W_0F3A0F_P_2 */
10937     { "vpalignr",       { XM, Vex, EXx, Ib } },
10938   },
10939   {
10940     /* VEX_W_0F3A14_P_2 */
10941     { "vpextrb",        { Edqb, XM, Ib } },
10942   },
10943   {
10944     /* VEX_W_0F3A15_P_2 */
10945     { "vpextrw",        { Edqw, XM, Ib } },
10946   },
10947   {
10948     /* VEX_W_0F3A18_P_2 */
10949     { "vinsertf128",    { XM, Vex256, EXxmm, Ib } },
10950   },
10951   {
10952     /* VEX_W_0F3A19_P_2 */
10953     { "vextractf128",   { EXxmm, XM, Ib } },
10954   },
10955   {
10956     /* VEX_W_0F3A20_P_2 */
10957     { "vpinsrb",        { XM, Vex128, Edqb, Ib } },
10958   },
10959   {
10960     /* VEX_W_0F3A21_P_2 */
10961     { "vinsertps",      { XM, Vex128, EXd, Ib } },
10962   },
10963   {
10964     /* VEX_W_0F3A30_P_2 */
10965     { Bad_Opcode },
10966     { "kshiftrw",       { MaskG, MaskR, Ib } },
10967   },
10968   {
10969     /* VEX_W_0F3A32_P_2 */
10970     { Bad_Opcode },
10971     { "kshiftlw",       { MaskG, MaskR, Ib } },
10972   },
10973   {
10974     /* VEX_W_0F3A38_P_2 */
10975     { "vinserti128",    { XM, Vex256, EXxmm, Ib } },
10976   },
10977   {
10978     /* VEX_W_0F3A39_P_2 */
10979     { "vextracti128",   { EXxmm, XM, Ib } },
10980   },
10981   {
10982     /* VEX_W_0F3A40_P_2 */
10983     { "vdpps",          { XM, Vex, EXx, Ib } },
10984   },
10985   {
10986     /* VEX_W_0F3A41_P_2 */
10987     { "vdppd",          { XM, Vex128, EXx, Ib } },
10988   },
10989   {
10990     /* VEX_W_0F3A42_P_2 */
10991     { "vmpsadbw",       { XM, Vex, EXx, Ib } },
10992   },
10993   {
10994     /* VEX_W_0F3A44_P_2 */
10995     { "vpclmulqdq",     { XM, Vex128, EXx, PCLMUL } },
10996   },
10997   {
10998     /* VEX_W_0F3A46_P_2 */
10999     { "vperm2i128",     { XM, Vex256, EXx, Ib } },
11000   },
11001   {
11002     /* VEX_W_0F3A48_P_2 */
11003     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
11004     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
11005   },
11006   {
11007     /* VEX_W_0F3A49_P_2 */
11008     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
11009     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
11010   },
11011   {
11012     /* VEX_W_0F3A4A_P_2 */
11013     { "vblendvps",      { XM, Vex, EXx, XMVexI4 } },
11014   },
11015   {
11016     /* VEX_W_0F3A4B_P_2 */
11017     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 } },
11018   },
11019   {
11020     /* VEX_W_0F3A4C_P_2 */
11021     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 } },
11022   },
11023   {
11024     /* VEX_W_0F3A60_P_2 */
11025     { "vpcmpestrm",     { XM, EXx, Ib } },
11026   },
11027   {
11028     /* VEX_W_0F3A61_P_2 */
11029     { "vpcmpestri",     { XM, EXx, Ib } },
11030   },
11031   {
11032     /* VEX_W_0F3A62_P_2 */
11033     { "vpcmpistrm",     { XM, EXx, Ib } },
11034   },
11035   {
11036     /* VEX_W_0F3A63_P_2 */
11037     { "vpcmpistri",     { XM, EXx, Ib } },
11038   },
11039   {
11040     /* VEX_W_0F3ADF_P_2 */
11041     { "vaeskeygenassist", { XM, EXx, Ib } },
11042   },
11043 #define NEED_VEX_W_TABLE
11044 #include "i386-dis-evex.h"
11045 #undef NEED_VEX_W_TABLE
11046 };
11047
11048 static const struct dis386 mod_table[][2] = {
11049   {
11050     /* MOD_8D */
11051     { "leaS",           { Gv, M } },
11052   },
11053   {
11054     /* MOD_C6_REG_7 */
11055     { Bad_Opcode },
11056     { RM_TABLE (RM_C6_REG_7) },
11057   },
11058   {
11059     /* MOD_C7_REG_7 */
11060     { Bad_Opcode },
11061     { RM_TABLE (RM_C7_REG_7) },
11062   },
11063   {
11064     /* MOD_FF_REG_3 */
11065     { "Jcall{T|}", { indirEp } },
11066   },
11067   {
11068     /* MOD_FF_REG_5 */
11069     { "Jjmp{T|}", { indirEp } },
11070   },
11071   {
11072     /* MOD_0F01_REG_0 */
11073     { X86_64_TABLE (X86_64_0F01_REG_0) },
11074     { RM_TABLE (RM_0F01_REG_0) },
11075   },
11076   {
11077     /* MOD_0F01_REG_1 */
11078     { X86_64_TABLE (X86_64_0F01_REG_1) },
11079     { RM_TABLE (RM_0F01_REG_1) },
11080   },
11081   {
11082     /* MOD_0F01_REG_2 */
11083     { X86_64_TABLE (X86_64_0F01_REG_2) },
11084     { RM_TABLE (RM_0F01_REG_2) },
11085   },
11086   {
11087     /* MOD_0F01_REG_3 */
11088     { X86_64_TABLE (X86_64_0F01_REG_3) },
11089     { RM_TABLE (RM_0F01_REG_3) },
11090   },
11091   {
11092     /* MOD_0F01_REG_7 */
11093     { "invlpg",         { Mb } },
11094     { RM_TABLE (RM_0F01_REG_7) },
11095   },
11096   {
11097     /* MOD_0F12_PREFIX_0 */
11098     { "movlps",         { XM, EXq } },
11099     { "movhlps",        { XM, EXq } },
11100   },
11101   {
11102     /* MOD_0F13 */
11103     { "movlpX",         { EXq, XM } },
11104   },
11105   {
11106     /* MOD_0F16_PREFIX_0 */
11107     { "movhps",         { XM, EXq } },
11108     { "movlhps",        { XM, EXq } },
11109   },
11110   {
11111     /* MOD_0F17 */
11112     { "movhpX",         { EXq, XM } },
11113   },
11114   {
11115     /* MOD_0F18_REG_0 */
11116     { "prefetchnta",    { Mb } },
11117   },
11118   {
11119     /* MOD_0F18_REG_1 */
11120     { "prefetcht0",     { Mb } },
11121   },
11122   {
11123     /* MOD_0F18_REG_2 */
11124     { "prefetcht1",     { Mb } },
11125   },
11126   {
11127     /* MOD_0F18_REG_3 */
11128     { "prefetcht2",     { Mb } },
11129   },
11130   {
11131     /* MOD_0F18_REG_4 */
11132     { "nop/reserved",   { Mb } },
11133   },
11134   {
11135     /* MOD_0F18_REG_5 */
11136     { "nop/reserved",   { Mb } },
11137   },
11138   {
11139     /* MOD_0F18_REG_6 */
11140     { "nop/reserved",   { Mb } },
11141   },
11142   {
11143     /* MOD_0F18_REG_7 */
11144     { "nop/reserved",   { Mb } },
11145   },
11146   {
11147     /* MOD_0F1A_PREFIX_0 */
11148     { "bndldx",         { Gbnd, Ev_bnd } },
11149     { "nopQ",           { Ev } },
11150   },
11151   {
11152     /* MOD_0F1B_PREFIX_0 */
11153     { "bndstx",         { Ev_bnd, Gbnd } },
11154     { "nopQ",           { Ev } },
11155   },
11156   {
11157     /* MOD_0F1B_PREFIX_1 */
11158     { "bndmk",          { Gbnd, Ev_bnd } },
11159     { "nopQ",           { Ev } },
11160   },
11161   {
11162     /* MOD_0F20 */
11163     { Bad_Opcode },
11164     { "movZ",           { Rm, Cm } },
11165   },
11166   {
11167     /* MOD_0F21 */
11168     { Bad_Opcode },
11169     { "movZ",           { Rm, Dm } },
11170   },
11171   {
11172     /* MOD_0F22 */
11173     { Bad_Opcode },
11174     { "movZ",           { Cm, Rm } },
11175   },
11176   {
11177     /* MOD_0F23 */
11178     { Bad_Opcode },
11179     { "movZ",           { Dm, Rm } },
11180   },
11181   {
11182     /* MOD_0F24 */
11183     { Bad_Opcode },
11184     { "movL",           { Rd, Td } },
11185   },
11186   {
11187     /* MOD_0F26 */
11188     { Bad_Opcode },
11189     { "movL",           { Td, Rd } },
11190   },
11191   {
11192     /* MOD_0F2B_PREFIX_0 */
11193     {"movntps",         { Mx, XM } },
11194   },
11195   {
11196     /* MOD_0F2B_PREFIX_1 */
11197     {"movntss",         { Md, XM } },
11198   },
11199   {
11200     /* MOD_0F2B_PREFIX_2 */
11201     {"movntpd",         { Mx, XM } },
11202   },
11203   {
11204     /* MOD_0F2B_PREFIX_3 */
11205     {"movntsd",         { Mq, XM } },
11206   },
11207   {
11208     /* MOD_0F51 */
11209     { Bad_Opcode },
11210     { "movmskpX",       { Gdq, XS } },
11211   },
11212   {
11213     /* MOD_0F71_REG_2 */
11214     { Bad_Opcode },
11215     { "psrlw",          { MS, Ib } },
11216   },
11217   {
11218     /* MOD_0F71_REG_4 */
11219     { Bad_Opcode },
11220     { "psraw",          { MS, Ib } },
11221   },
11222   {
11223     /* MOD_0F71_REG_6 */
11224     { Bad_Opcode },
11225     { "psllw",          { MS, Ib } },
11226   },
11227   {
11228     /* MOD_0F72_REG_2 */
11229     { Bad_Opcode },
11230     { "psrld",          { MS, Ib } },
11231   },
11232   {
11233     /* MOD_0F72_REG_4 */
11234     { Bad_Opcode },
11235     { "psrad",          { MS, Ib } },
11236   },
11237   {
11238     /* MOD_0F72_REG_6 */
11239     { Bad_Opcode },
11240     { "pslld",          { MS, Ib } },
11241   },
11242   {
11243     /* MOD_0F73_REG_2 */
11244     { Bad_Opcode },
11245     { "psrlq",          { MS, Ib } },
11246   },
11247   {
11248     /* MOD_0F73_REG_3 */
11249     { Bad_Opcode },
11250     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
11251   },
11252   {
11253     /* MOD_0F73_REG_6 */
11254     { Bad_Opcode },
11255     { "psllq",          { MS, Ib } },
11256   },
11257   {
11258     /* MOD_0F73_REG_7 */
11259     { Bad_Opcode },
11260     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
11261   },
11262   {
11263     /* MOD_0FAE_REG_0 */
11264     { "fxsave",         { FXSAVE } },
11265     { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
11266   },
11267   {
11268     /* MOD_0FAE_REG_1 */
11269     { "fxrstor",        { FXSAVE } },
11270     { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
11271   },
11272   {
11273     /* MOD_0FAE_REG_2 */
11274     { "ldmxcsr",        { Md } },
11275     { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
11276   },
11277   {
11278     /* MOD_0FAE_REG_3 */
11279     { "stmxcsr",        { Md } },
11280     { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
11281   },
11282   {
11283     /* MOD_0FAE_REG_4 */
11284     { "xsave",          { FXSAVE } },
11285   },
11286   {
11287     /* MOD_0FAE_REG_5 */
11288     { "xrstor",         { FXSAVE } },
11289     { RM_TABLE (RM_0FAE_REG_5) },
11290   },
11291   {
11292     /* MOD_0FAE_REG_6 */
11293     { "xsaveopt",       { FXSAVE } },
11294     { RM_TABLE (RM_0FAE_REG_6) },
11295   },
11296   {
11297     /* MOD_0FAE_REG_7 */
11298     { PREFIX_TABLE (PREFIX_0FAE_REG_7) },
11299     { RM_TABLE (RM_0FAE_REG_7) },
11300   },
11301   {
11302     /* MOD_0FB2 */
11303     { "lssS",           { Gv, Mp } },
11304   },
11305   {
11306     /* MOD_0FB4 */
11307     { "lfsS",           { Gv, Mp } },
11308   },
11309   {
11310     /* MOD_0FB5 */
11311     { "lgsS",           { Gv, Mp } },
11312   },
11313   {
11314     /* MOD_0FC7_REG_3 */
11315     { "xrstors",                { FXSAVE } },
11316   },
11317   {
11318     /* MOD_0FC7_REG_4 */
11319     { "xsavec",         { FXSAVE } },
11320   },
11321   {
11322     /* MOD_0FC7_REG_5 */
11323     { "xsaves",         { FXSAVE } },
11324   },
11325   {
11326     /* MOD_0FC7_REG_6 */
11327     { PREFIX_TABLE (PREFIX_0FC7_REG_6) },
11328     { "rdrand",         { Ev } },
11329   },
11330   {
11331     /* MOD_0FC7_REG_7 */
11332     { "vmptrst",        { Mq } },
11333     { "rdseed",         { Ev } },
11334   },
11335   {
11336     /* MOD_0FD7 */
11337     { Bad_Opcode },
11338     { "pmovmskb",       { Gdq, MS } },
11339   },
11340   {
11341     /* MOD_0FE7_PREFIX_2 */
11342     { "movntdq",        { Mx, XM } },
11343   },
11344   {
11345     /* MOD_0FF0_PREFIX_3 */
11346     { "lddqu",          { XM, M } },
11347   },
11348   {
11349     /* MOD_0F382A_PREFIX_2 */
11350     { "movntdqa",       { XM, Mx } },
11351   },
11352   {
11353     /* MOD_62_32BIT */
11354     { "bound{S|}",      { Gv, Ma } },
11355     { EVEX_TABLE (EVEX_0F) },
11356   },
11357   {
11358     /* MOD_C4_32BIT */
11359     { "lesS",           { Gv, Mp } },
11360     { VEX_C4_TABLE (VEX_0F) },
11361   },
11362   {
11363     /* MOD_C5_32BIT */
11364     { "ldsS",           { Gv, Mp } },
11365     { VEX_C5_TABLE (VEX_0F) },
11366   },
11367   {
11368     /* MOD_VEX_0F12_PREFIX_0 */
11369     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
11370     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
11371   },
11372   {
11373     /* MOD_VEX_0F13 */
11374     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
11375   },
11376   {
11377     /* MOD_VEX_0F16_PREFIX_0 */
11378     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
11379     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
11380   },
11381   {
11382     /* MOD_VEX_0F17 */
11383     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
11384   },
11385   {
11386     /* MOD_VEX_0F2B */
11387     { VEX_W_TABLE (VEX_W_0F2B_M_0) },
11388   },
11389   {
11390     /* MOD_VEX_0F50 */
11391     { Bad_Opcode },
11392     { VEX_W_TABLE (VEX_W_0F50_M_0) },
11393   },
11394   {
11395     /* MOD_VEX_0F71_REG_2 */
11396     { Bad_Opcode },
11397     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
11398   },
11399   {
11400     /* MOD_VEX_0F71_REG_4 */
11401     { Bad_Opcode },
11402     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
11403   },
11404   {
11405     /* MOD_VEX_0F71_REG_6 */
11406     { Bad_Opcode },
11407     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
11408   },
11409   {
11410     /* MOD_VEX_0F72_REG_2 */
11411     { Bad_Opcode },
11412     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
11413   },
11414   {
11415     /* MOD_VEX_0F72_REG_4 */
11416     { Bad_Opcode },
11417     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
11418   },
11419   {
11420     /* MOD_VEX_0F72_REG_6 */
11421     { Bad_Opcode },
11422     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
11423   },
11424   {
11425     /* MOD_VEX_0F73_REG_2 */
11426     { Bad_Opcode },
11427     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
11428   },
11429   {
11430     /* MOD_VEX_0F73_REG_3 */
11431     { Bad_Opcode },
11432     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
11433   },
11434   {
11435     /* MOD_VEX_0F73_REG_6 */
11436     { Bad_Opcode },
11437     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
11438   },
11439   {
11440     /* MOD_VEX_0F73_REG_7 */
11441     { Bad_Opcode },
11442     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
11443   },
11444   {
11445     /* MOD_VEX_0FAE_REG_2 */
11446     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
11447   },
11448   {
11449     /* MOD_VEX_0FAE_REG_3 */
11450     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
11451   },
11452   {
11453     /* MOD_VEX_0FD7_PREFIX_2 */
11454     { Bad_Opcode },
11455     { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) },
11456   },
11457   {
11458     /* MOD_VEX_0FE7_PREFIX_2 */
11459     { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) },
11460   },
11461   {
11462     /* MOD_VEX_0FF0_PREFIX_3 */
11463     { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) },
11464   },
11465   {
11466     /* MOD_VEX_0F381A_PREFIX_2 */
11467     { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
11468   },
11469   {
11470     /* MOD_VEX_0F382A_PREFIX_2 */
11471     { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) },
11472   },
11473   {
11474     /* MOD_VEX_0F382C_PREFIX_2 */
11475     { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
11476   },
11477   {
11478     /* MOD_VEX_0F382D_PREFIX_2 */
11479     { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
11480   },
11481   {
11482     /* MOD_VEX_0F382E_PREFIX_2 */
11483     { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
11484   },
11485   {
11486     /* MOD_VEX_0F382F_PREFIX_2 */
11487     { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
11488   },
11489   {
11490     /* MOD_VEX_0F385A_PREFIX_2 */
11491     { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
11492   },
11493   {
11494     /* MOD_VEX_0F388C_PREFIX_2 */
11495     { "vpmaskmov%LW",   { XM, Vex, Mx } },
11496   },
11497   {
11498     /* MOD_VEX_0F388E_PREFIX_2 */
11499     { "vpmaskmov%LW",   { Mx, Vex, XM } },
11500   },
11501 #define NEED_MOD_TABLE
11502 #include "i386-dis-evex.h"
11503 #undef NEED_MOD_TABLE
11504 };
11505
11506 static const struct dis386 rm_table[][8] = {
11507   {
11508     /* RM_C6_REG_7 */
11509     { "xabort",         { Skip_MODRM, Ib } },
11510   },
11511   {
11512     /* RM_C7_REG_7 */
11513     { "xbeginT",        { Skip_MODRM, Jv } },
11514   },
11515   {
11516     /* RM_0F01_REG_0 */
11517     { Bad_Opcode },
11518     { "vmcall",         { Skip_MODRM } },
11519     { "vmlaunch",       { Skip_MODRM } },
11520     { "vmresume",       { Skip_MODRM } },
11521     { "vmxoff",         { Skip_MODRM } },
11522   },
11523   {
11524     /* RM_0F01_REG_1 */
11525     { "monitor",        { { OP_Monitor, 0 } } },
11526     { "mwait",          { { OP_Mwait, 0 } } },
11527     { "clac",           { Skip_MODRM } },
11528     { "stac",           { Skip_MODRM } },
11529   },
11530   {
11531     /* RM_0F01_REG_2 */
11532     { "xgetbv",         { Skip_MODRM } },
11533     { "xsetbv",         { Skip_MODRM } },
11534     { Bad_Opcode },
11535     { Bad_Opcode },
11536     { "vmfunc",         { Skip_MODRM } },
11537     { "xend",           { Skip_MODRM } },
11538     { "xtest",          { Skip_MODRM } },
11539     { Bad_Opcode },
11540   },
11541   {
11542     /* RM_0F01_REG_3 */
11543     { "vmrun",          { Skip_MODRM } },
11544     { "vmmcall",        { Skip_MODRM } },
11545     { "vmload",         { Skip_MODRM } },
11546     { "vmsave",         { Skip_MODRM } },
11547     { "stgi",           { Skip_MODRM } },
11548     { "clgi",           { Skip_MODRM } },
11549     { "skinit",         { Skip_MODRM } },
11550     { "invlpga",        { Skip_MODRM } },
11551   },
11552   {
11553     /* RM_0F01_REG_7 */
11554     { "swapgs",         { Skip_MODRM } },
11555     { "rdtscp",         { Skip_MODRM } },
11556   },
11557   {
11558     /* RM_0FAE_REG_5 */
11559     { "lfence",         { Skip_MODRM } },
11560   },
11561   {
11562     /* RM_0FAE_REG_6 */
11563     { "mfence",         { Skip_MODRM } },
11564   },
11565   {
11566     /* RM_0FAE_REG_7 */
11567     { "sfence",         { Skip_MODRM } },
11568   },
11569 };
11570
11571 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
11572
11573 /* We use the high bit to indicate different name for the same
11574    prefix.  */
11575 #define ADDR16_PREFIX   (0x67 | 0x100)
11576 #define ADDR32_PREFIX   (0x67 | 0x200)
11577 #define DATA16_PREFIX   (0x66 | 0x100)
11578 #define DATA32_PREFIX   (0x66 | 0x200)
11579 #define REP_PREFIX      (0xf3 | 0x100)
11580 #define XACQUIRE_PREFIX (0xf2 | 0x200)
11581 #define XRELEASE_PREFIX (0xf3 | 0x400)
11582 #define BND_PREFIX      (0xf2 | 0x400)
11583
11584 static int
11585 ckprefix (void)
11586 {
11587   int newrex, i, length;
11588   rex = 0;
11589   rex_ignored = 0;
11590   prefixes = 0;
11591   used_prefixes = 0;
11592   rex_used = 0;
11593   last_lock_prefix = -1;
11594   last_repz_prefix = -1;
11595   last_repnz_prefix = -1;
11596   last_data_prefix = -1;
11597   last_addr_prefix = -1;
11598   last_rex_prefix = -1;
11599   last_seg_prefix = -1;
11600   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
11601     all_prefixes[i] = 0;
11602   i = 0;
11603   length = 0;
11604   /* The maximum instruction length is 15bytes.  */
11605   while (length < MAX_CODE_LENGTH - 1)
11606     {
11607       FETCH_DATA (the_info, codep + 1);
11608       newrex = 0;
11609       switch (*codep)
11610         {
11611         /* REX prefixes family.  */
11612         case 0x40:
11613         case 0x41:
11614         case 0x42:
11615         case 0x43:
11616         case 0x44:
11617         case 0x45:
11618         case 0x46:
11619         case 0x47:
11620         case 0x48:
11621         case 0x49:
11622         case 0x4a:
11623         case 0x4b:
11624         case 0x4c:
11625         case 0x4d:
11626         case 0x4e:
11627         case 0x4f:
11628           if (address_mode == mode_64bit)
11629             newrex = *codep;
11630           else
11631             return 1;
11632           last_rex_prefix = i;
11633           break;
11634         case 0xf3:
11635           prefixes |= PREFIX_REPZ;
11636           last_repz_prefix = i;
11637           break;
11638         case 0xf2:
11639           prefixes |= PREFIX_REPNZ;
11640           last_repnz_prefix = i;
11641           break;
11642         case 0xf0:
11643           prefixes |= PREFIX_LOCK;
11644           last_lock_prefix = i;
11645           break;
11646         case 0x2e:
11647           prefixes |= PREFIX_CS;
11648           last_seg_prefix = i;
11649           break;
11650         case 0x36:
11651           prefixes |= PREFIX_SS;
11652           last_seg_prefix = i;
11653           break;
11654         case 0x3e:
11655           prefixes |= PREFIX_DS;
11656           last_seg_prefix = i;
11657           break;
11658         case 0x26:
11659           prefixes |= PREFIX_ES;
11660           last_seg_prefix = i;
11661           break;
11662         case 0x64:
11663           prefixes |= PREFIX_FS;
11664           last_seg_prefix = i;
11665           break;
11666         case 0x65:
11667           prefixes |= PREFIX_GS;
11668           last_seg_prefix = i;
11669           break;
11670         case 0x66:
11671           prefixes |= PREFIX_DATA;
11672           last_data_prefix = i;
11673           break;
11674         case 0x67:
11675           prefixes |= PREFIX_ADDR;
11676           last_addr_prefix = i;
11677           break;
11678         case FWAIT_OPCODE:
11679           /* fwait is really an instruction.  If there are prefixes
11680              before the fwait, they belong to the fwait, *not* to the
11681              following instruction.  */
11682           if (prefixes || rex)
11683             {
11684               prefixes |= PREFIX_FWAIT;
11685               codep++;
11686               /* This ensures that the previous REX prefixes are noticed
11687                  as unused prefixes, as in the return case below.  */
11688               rex_used = rex;
11689               return 1;
11690             }
11691           prefixes = PREFIX_FWAIT;
11692           break;
11693         default:
11694           return 1;
11695         }
11696       /* Rex is ignored when followed by another prefix.  */
11697       if (rex)
11698         {
11699           rex_used = rex;
11700           return 1;
11701         }
11702       if (*codep != FWAIT_OPCODE)
11703         all_prefixes[i++] = *codep;
11704       rex = newrex;
11705       codep++;
11706       length++;
11707     }
11708   return 0;
11709 }
11710
11711 static int
11712 seg_prefix (int pref)
11713 {
11714   switch (pref)
11715     {
11716     case 0x2e:
11717       return PREFIX_CS;
11718     case 0x36:
11719       return PREFIX_SS;
11720     case 0x3e:
11721       return PREFIX_DS;
11722     case 0x26:
11723       return PREFIX_ES;
11724     case 0x64:
11725       return PREFIX_FS;
11726     case 0x65:
11727       return PREFIX_GS;
11728     default:
11729       return 0;
11730     }
11731 }
11732
11733 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
11734    prefix byte.  */
11735
11736 static const char *
11737 prefix_name (int pref, int sizeflag)
11738 {
11739   static const char *rexes [16] =
11740     {
11741       "rex",            /* 0x40 */
11742       "rex.B",          /* 0x41 */
11743       "rex.X",          /* 0x42 */
11744       "rex.XB",         /* 0x43 */
11745       "rex.R",          /* 0x44 */
11746       "rex.RB",         /* 0x45 */
11747       "rex.RX",         /* 0x46 */
11748       "rex.RXB",        /* 0x47 */
11749       "rex.W",          /* 0x48 */
11750       "rex.WB",         /* 0x49 */
11751       "rex.WX",         /* 0x4a */
11752       "rex.WXB",        /* 0x4b */
11753       "rex.WR",         /* 0x4c */
11754       "rex.WRB",        /* 0x4d */
11755       "rex.WRX",        /* 0x4e */
11756       "rex.WRXB",       /* 0x4f */
11757     };
11758
11759   switch (pref)
11760     {
11761     /* REX prefixes family.  */
11762     case 0x40:
11763     case 0x41:
11764     case 0x42:
11765     case 0x43:
11766     case 0x44:
11767     case 0x45:
11768     case 0x46:
11769     case 0x47:
11770     case 0x48:
11771     case 0x49:
11772     case 0x4a:
11773     case 0x4b:
11774     case 0x4c:
11775     case 0x4d:
11776     case 0x4e:
11777     case 0x4f:
11778       return rexes [pref - 0x40];
11779     case 0xf3:
11780       return "repz";
11781     case 0xf2:
11782       return "repnz";
11783     case 0xf0:
11784       return "lock";
11785     case 0x2e:
11786       return "cs";
11787     case 0x36:
11788       return "ss";
11789     case 0x3e:
11790       return "ds";
11791     case 0x26:
11792       return "es";
11793     case 0x64:
11794       return "fs";
11795     case 0x65:
11796       return "gs";
11797     case 0x66:
11798       return (sizeflag & DFLAG) ? "data16" : "data32";
11799     case 0x67:
11800       if (address_mode == mode_64bit)
11801         return (sizeflag & AFLAG) ? "addr32" : "addr64";
11802       else
11803         return (sizeflag & AFLAG) ? "addr16" : "addr32";
11804     case FWAIT_OPCODE:
11805       return "fwait";
11806     case ADDR16_PREFIX:
11807       return "addr16";
11808     case ADDR32_PREFIX:
11809       return "addr32";
11810     case DATA16_PREFIX:
11811       return "data16";
11812     case DATA32_PREFIX:
11813       return "data32";
11814     case REP_PREFIX:
11815       return "rep";
11816     case XACQUIRE_PREFIX:
11817       return "xacquire";
11818     case XRELEASE_PREFIX:
11819       return "xrelease";
11820     case BND_PREFIX:
11821       return "bnd";
11822     default:
11823       return NULL;
11824     }
11825 }
11826
11827 static char op_out[MAX_OPERANDS][100];
11828 static int op_ad, op_index[MAX_OPERANDS];
11829 static int two_source_ops;
11830 static bfd_vma op_address[MAX_OPERANDS];
11831 static bfd_vma op_riprel[MAX_OPERANDS];
11832 static bfd_vma start_pc;
11833
11834 /*
11835  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
11836  *   (see topic "Redundant prefixes" in the "Differences from 8086"
11837  *   section of the "Virtual 8086 Mode" chapter.)
11838  * 'pc' should be the address of this instruction, it will
11839  *   be used to print the target address if this is a relative jump or call
11840  * The function returns the length of this instruction in bytes.
11841  */
11842
11843 static char intel_syntax;
11844 static char intel_mnemonic = !SYSV386_COMPAT;
11845 static char open_char;
11846 static char close_char;
11847 static char separator_char;
11848 static char scale_char;
11849
11850 /* Here for backwards compatibility.  When gdb stops using
11851    print_insn_i386_att and print_insn_i386_intel these functions can
11852    disappear, and print_insn_i386 be merged into print_insn.  */
11853 int
11854 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
11855 {
11856   intel_syntax = 0;
11857
11858   return print_insn (pc, info);
11859 }
11860
11861 int
11862 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
11863 {
11864   intel_syntax = 1;
11865
11866   return print_insn (pc, info);
11867 }
11868
11869 int
11870 print_insn_i386 (bfd_vma pc, disassemble_info *info)
11871 {
11872   intel_syntax = -1;
11873
11874   return print_insn (pc, info);
11875 }
11876
11877 void
11878 print_i386_disassembler_options (FILE *stream)
11879 {
11880   fprintf (stream, _("\n\
11881 The following i386/x86-64 specific disassembler options are supported for use\n\
11882 with the -M switch (multiple options should be separated by commas):\n"));
11883
11884   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
11885   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
11886   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
11887   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
11888   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
11889   fprintf (stream, _("  att-mnemonic\n"
11890                      "              Display instruction in AT&T mnemonic\n"));
11891   fprintf (stream, _("  intel-mnemonic\n"
11892                      "              Display instruction in Intel mnemonic\n"));
11893   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
11894   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
11895   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
11896   fprintf (stream, _("  data32      Assume 32bit data size\n"));
11897   fprintf (stream, _("  data16      Assume 16bit data size\n"));
11898   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
11899 }
11900
11901 /* Bad opcode.  */
11902 static const struct dis386 bad_opcode = { "(bad)", { XX } };
11903
11904 /* Get a pointer to struct dis386 with a valid name.  */
11905
11906 static const struct dis386 *
11907 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
11908 {
11909   int vindex, vex_table_index;
11910
11911   if (dp->name != NULL)
11912     return dp;
11913
11914   switch (dp->op[0].bytemode)
11915     {
11916     case USE_REG_TABLE:
11917       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
11918       break;
11919
11920     case USE_MOD_TABLE:
11921       vindex = modrm.mod == 0x3 ? 1 : 0;
11922       dp = &mod_table[dp->op[1].bytemode][vindex];
11923       break;
11924
11925     case USE_RM_TABLE:
11926       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
11927       break;
11928
11929     case USE_PREFIX_TABLE:
11930       if (need_vex)
11931         {
11932           /* The prefix in VEX is implicit.  */
11933           switch (vex.prefix)
11934             {
11935             case 0:
11936               vindex = 0;
11937               break;
11938             case REPE_PREFIX_OPCODE:
11939               vindex = 1;
11940               break;
11941             case DATA_PREFIX_OPCODE:
11942               vindex = 2;
11943               break;
11944             case REPNE_PREFIX_OPCODE:
11945               vindex = 3;
11946               break;
11947             default:
11948               abort ();
11949               break;
11950             }
11951         }
11952       else
11953         {
11954           vindex = 0;
11955           used_prefixes |= (prefixes & PREFIX_REPZ);
11956           if (prefixes & PREFIX_REPZ)
11957             {
11958               vindex = 1;
11959               all_prefixes[last_repz_prefix] = 0;
11960             }
11961           else
11962             {
11963               /* We should check PREFIX_REPNZ and PREFIX_REPZ before
11964                  PREFIX_DATA.  */
11965               used_prefixes |= (prefixes & PREFIX_REPNZ);
11966               if (prefixes & PREFIX_REPNZ)
11967                 {
11968                   vindex = 3;
11969                   all_prefixes[last_repnz_prefix] = 0;
11970                 }
11971               else
11972                 {
11973                   used_prefixes |= (prefixes & PREFIX_DATA);
11974                   if (prefixes & PREFIX_DATA)
11975                     {
11976                       vindex = 2;
11977                       all_prefixes[last_data_prefix] = 0;
11978                     }
11979                 }
11980             }
11981         }
11982       dp = &prefix_table[dp->op[1].bytemode][vindex];
11983       break;
11984
11985     case USE_X86_64_TABLE:
11986       vindex = address_mode == mode_64bit ? 1 : 0;
11987       dp = &x86_64_table[dp->op[1].bytemode][vindex];
11988       break;
11989
11990     case USE_3BYTE_TABLE:
11991       FETCH_DATA (info, codep + 2);
11992       vindex = *codep++;
11993       dp = &three_byte_table[dp->op[1].bytemode][vindex];
11994       modrm.mod = (*codep >> 6) & 3;
11995       modrm.reg = (*codep >> 3) & 7;
11996       modrm.rm = *codep & 7;
11997       break;
11998
11999     case USE_VEX_LEN_TABLE:
12000       if (!need_vex)
12001         abort ();
12002
12003       switch (vex.length)
12004         {
12005         case 128:
12006           vindex = 0;
12007           break;
12008         case 256:
12009           vindex = 1;
12010           break;
12011         default:
12012           abort ();
12013           break;
12014         }
12015
12016       dp = &vex_len_table[dp->op[1].bytemode][vindex];
12017       break;
12018
12019     case USE_XOP_8F_TABLE:
12020       FETCH_DATA (info, codep + 3);
12021       /* All bits in the REX prefix are ignored.  */
12022       rex_ignored = rex;
12023       rex = ~(*codep >> 5) & 0x7;
12024
12025       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
12026       switch ((*codep & 0x1f))
12027         {
12028         default:
12029           dp = &bad_opcode;
12030           return dp;
12031         case 0x8:
12032           vex_table_index = XOP_08;
12033           break;
12034         case 0x9:
12035           vex_table_index = XOP_09;
12036           break;
12037         case 0xa:
12038           vex_table_index = XOP_0A;
12039           break;
12040         }
12041       codep++;
12042       vex.w = *codep & 0x80;
12043       if (vex.w && address_mode == mode_64bit)
12044         rex |= REX_W;
12045
12046       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12047       if (address_mode != mode_64bit
12048           && vex.register_specifier > 0x7)
12049         {
12050           dp = &bad_opcode;
12051           return dp;
12052         }
12053
12054       vex.length = (*codep & 0x4) ? 256 : 128;
12055       switch ((*codep & 0x3))
12056         {
12057         case 0:
12058           vex.prefix = 0;
12059           break;
12060         case 1:
12061           vex.prefix = DATA_PREFIX_OPCODE;
12062           break;
12063         case 2:
12064           vex.prefix = REPE_PREFIX_OPCODE;
12065           break;
12066         case 3:
12067           vex.prefix = REPNE_PREFIX_OPCODE;
12068           break;
12069         }
12070       need_vex = 1;
12071       need_vex_reg = 1;
12072       codep++;
12073       vindex = *codep++;
12074       dp = &xop_table[vex_table_index][vindex];
12075
12076       FETCH_DATA (info, codep + 1);
12077       modrm.mod = (*codep >> 6) & 3;
12078       modrm.reg = (*codep >> 3) & 7;
12079       modrm.rm = *codep & 7;
12080       break;
12081
12082     case USE_VEX_C4_TABLE:
12083       /* VEX prefix.  */
12084       FETCH_DATA (info, codep + 3);
12085       /* All bits in the REX prefix are ignored.  */
12086       rex_ignored = rex;
12087       rex = ~(*codep >> 5) & 0x7;
12088       switch ((*codep & 0x1f))
12089         {
12090         default:
12091           dp = &bad_opcode;
12092           return dp;
12093         case 0x1:
12094           vex_table_index = VEX_0F;
12095           break;
12096         case 0x2:
12097           vex_table_index = VEX_0F38;
12098           break;
12099         case 0x3:
12100           vex_table_index = VEX_0F3A;
12101           break;
12102         }
12103       codep++;
12104       vex.w = *codep & 0x80;
12105       if (vex.w && address_mode == mode_64bit)
12106         rex |= REX_W;
12107
12108       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12109       if (address_mode != mode_64bit
12110           && vex.register_specifier > 0x7)
12111         {
12112           dp = &bad_opcode;
12113           return dp;
12114         }
12115
12116       vex.length = (*codep & 0x4) ? 256 : 128;
12117       switch ((*codep & 0x3))
12118         {
12119         case 0:
12120           vex.prefix = 0;
12121           break;
12122         case 1:
12123           vex.prefix = DATA_PREFIX_OPCODE;
12124           break;
12125         case 2:
12126           vex.prefix = REPE_PREFIX_OPCODE;
12127           break;
12128         case 3:
12129           vex.prefix = REPNE_PREFIX_OPCODE;
12130           break;
12131         }
12132       need_vex = 1;
12133       need_vex_reg = 1;
12134       codep++;
12135       vindex = *codep++;
12136       dp = &vex_table[vex_table_index][vindex];
12137       /* There is no MODRM byte for VEX [82|77].  */
12138       if (vindex != 0x77 && vindex != 0x82)
12139         {
12140           FETCH_DATA (info, codep + 1);
12141           modrm.mod = (*codep >> 6) & 3;
12142           modrm.reg = (*codep >> 3) & 7;
12143           modrm.rm = *codep & 7;
12144         }
12145       break;
12146
12147     case USE_VEX_C5_TABLE:
12148       /* VEX prefix.  */
12149       FETCH_DATA (info, codep + 2);
12150       /* All bits in the REX prefix are ignored.  */
12151       rex_ignored = rex;
12152       rex = (*codep & 0x80) ? 0 : REX_R;
12153
12154       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12155       if (address_mode != mode_64bit
12156           && vex.register_specifier > 0x7)
12157         {
12158           dp = &bad_opcode;
12159           return dp;
12160         }
12161
12162       vex.w = 0;
12163
12164       vex.length = (*codep & 0x4) ? 256 : 128;
12165       switch ((*codep & 0x3))
12166         {
12167         case 0:
12168           vex.prefix = 0;
12169           break;
12170         case 1:
12171           vex.prefix = DATA_PREFIX_OPCODE;
12172           break;
12173         case 2:
12174           vex.prefix = REPE_PREFIX_OPCODE;
12175           break;
12176         case 3:
12177           vex.prefix = REPNE_PREFIX_OPCODE;
12178           break;
12179         }
12180       need_vex = 1;
12181       need_vex_reg = 1;
12182       codep++;
12183       vindex = *codep++;
12184       dp = &vex_table[dp->op[1].bytemode][vindex];
12185       /* There is no MODRM byte for VEX [82|77].  */
12186       if (vindex != 0x77 && vindex != 0x82)
12187         {
12188           FETCH_DATA (info, codep + 1);
12189           modrm.mod = (*codep >> 6) & 3;
12190           modrm.reg = (*codep >> 3) & 7;
12191           modrm.rm = *codep & 7;
12192         }
12193       break;
12194
12195     case USE_VEX_W_TABLE:
12196       if (!need_vex)
12197         abort ();
12198
12199       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
12200       break;
12201
12202     case USE_EVEX_TABLE:
12203       two_source_ops = 0;
12204       /* EVEX prefix.  */
12205       vex.evex = 1;
12206       FETCH_DATA (info, codep + 4);
12207       /* All bits in the REX prefix are ignored.  */
12208       rex_ignored = rex;
12209       /* The first byte after 0x62.  */
12210       rex = ~(*codep >> 5) & 0x7;
12211       vex.r = *codep & 0x10;
12212       switch ((*codep & 0xf))
12213         {
12214         default:
12215           return &bad_opcode;
12216         case 0x1:
12217           vex_table_index = EVEX_0F;
12218           break;
12219         case 0x2:
12220           vex_table_index = EVEX_0F38;
12221           break;
12222         case 0x3:
12223           vex_table_index = EVEX_0F3A;
12224           break;
12225         }
12226
12227       /* The second byte after 0x62.  */
12228       codep++;
12229       vex.w = *codep & 0x80;
12230       if (vex.w && address_mode == mode_64bit)
12231         rex |= REX_W;
12232
12233       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12234       if (address_mode != mode_64bit)
12235         {
12236           /* In 16/32-bit mode silently ignore following bits.  */
12237           rex &= ~REX_B;
12238           vex.r = 1;
12239           vex.v = 1;
12240           vex.register_specifier &= 0x7;
12241         }
12242
12243       /* The U bit.  */
12244       if (!(*codep & 0x4))
12245         return &bad_opcode;
12246
12247       switch ((*codep & 0x3))
12248         {
12249         case 0:
12250           vex.prefix = 0;
12251           break;
12252         case 1:
12253           vex.prefix = DATA_PREFIX_OPCODE;
12254           break;
12255         case 2:
12256           vex.prefix = REPE_PREFIX_OPCODE;
12257           break;
12258         case 3:
12259           vex.prefix = REPNE_PREFIX_OPCODE;
12260           break;
12261         }
12262
12263       /* The third byte after 0x62.  */
12264       codep++;
12265
12266       /* Remember the static rounding bits.  */
12267       vex.ll = (*codep >> 5) & 3;
12268       vex.b = (*codep & 0x10) != 0;
12269
12270       vex.v = *codep & 0x8;
12271       vex.mask_register_specifier = *codep & 0x7;
12272       vex.zeroing = *codep & 0x80;
12273
12274       need_vex = 1;
12275       need_vex_reg = 1;
12276       codep++;
12277       vindex = *codep++;
12278       dp = &evex_table[vex_table_index][vindex];
12279       FETCH_DATA (info, codep + 1);
12280       modrm.mod = (*codep >> 6) & 3;
12281       modrm.reg = (*codep >> 3) & 7;
12282       modrm.rm = *codep & 7;
12283
12284       /* Set vector length.  */
12285       if (modrm.mod == 3 && vex.b)
12286         vex.length = 512;
12287       else
12288         {
12289           switch (vex.ll)
12290             {
12291             case 0x0:
12292               vex.length = 128;
12293               break;
12294             case 0x1:
12295               vex.length = 256;
12296               break;
12297             case 0x2:
12298               vex.length = 512;
12299               break;
12300             default:
12301               return &bad_opcode;
12302             }
12303         }
12304       break;
12305
12306     case 0:
12307       dp = &bad_opcode;
12308       break;
12309
12310     default:
12311       abort ();
12312     }
12313
12314   if (dp->name != NULL)
12315     return dp;
12316   else
12317     return get_valid_dis386 (dp, info);
12318 }
12319
12320 static void
12321 get_sib (disassemble_info *info, int sizeflag)
12322 {
12323   /* If modrm.mod == 3, operand must be register.  */
12324   if (need_modrm
12325       && ((sizeflag & AFLAG) || address_mode == mode_64bit)
12326       && modrm.mod != 3
12327       && modrm.rm == 4)
12328     {
12329       FETCH_DATA (info, codep + 2);
12330       sib.index = (codep [1] >> 3) & 7;
12331       sib.scale = (codep [1] >> 6) & 3;
12332       sib.base = codep [1] & 7;
12333     }
12334 }
12335
12336 static int
12337 print_insn (bfd_vma pc, disassemble_info *info)
12338 {
12339   const struct dis386 *dp;
12340   int i;
12341   char *op_txt[MAX_OPERANDS];
12342   int needcomma;
12343   int sizeflag;
12344   const char *p;
12345   struct dis_private priv;
12346   int prefix_length;
12347   int default_prefixes;
12348
12349   priv.orig_sizeflag = AFLAG | DFLAG;
12350   if ((info->mach & bfd_mach_i386_i386) != 0)
12351     address_mode = mode_32bit;
12352   else if (info->mach == bfd_mach_i386_i8086)
12353     {
12354       address_mode = mode_16bit;
12355       priv.orig_sizeflag = 0;
12356     }
12357   else
12358     address_mode = mode_64bit;
12359
12360   if (intel_syntax == (char) -1)
12361     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
12362
12363   for (p = info->disassembler_options; p != NULL; )
12364     {
12365       if (CONST_STRNEQ (p, "x86-64"))
12366         {
12367           address_mode = mode_64bit;
12368           priv.orig_sizeflag = AFLAG | DFLAG;
12369         }
12370       else if (CONST_STRNEQ (p, "i386"))
12371         {
12372           address_mode = mode_32bit;
12373           priv.orig_sizeflag = AFLAG | DFLAG;
12374         }
12375       else if (CONST_STRNEQ (p, "i8086"))
12376         {
12377           address_mode = mode_16bit;
12378           priv.orig_sizeflag = 0;
12379         }
12380       else if (CONST_STRNEQ (p, "intel"))
12381         {
12382           intel_syntax = 1;
12383           if (CONST_STRNEQ (p + 5, "-mnemonic"))
12384             intel_mnemonic = 1;
12385         }
12386       else if (CONST_STRNEQ (p, "att"))
12387         {
12388           intel_syntax = 0;
12389           if (CONST_STRNEQ (p + 3, "-mnemonic"))
12390             intel_mnemonic = 0;
12391         }
12392       else if (CONST_STRNEQ (p, "addr"))
12393         {
12394           if (address_mode == mode_64bit)
12395             {
12396               if (p[4] == '3' && p[5] == '2')
12397                 priv.orig_sizeflag &= ~AFLAG;
12398               else if (p[4] == '6' && p[5] == '4')
12399                 priv.orig_sizeflag |= AFLAG;
12400             }
12401           else
12402             {
12403               if (p[4] == '1' && p[5] == '6')
12404                 priv.orig_sizeflag &= ~AFLAG;
12405               else if (p[4] == '3' && p[5] == '2')
12406                 priv.orig_sizeflag |= AFLAG;
12407             }
12408         }
12409       else if (CONST_STRNEQ (p, "data"))
12410         {
12411           if (p[4] == '1' && p[5] == '6')
12412             priv.orig_sizeflag &= ~DFLAG;
12413           else if (p[4] == '3' && p[5] == '2')
12414             priv.orig_sizeflag |= DFLAG;
12415         }
12416       else if (CONST_STRNEQ (p, "suffix"))
12417         priv.orig_sizeflag |= SUFFIX_ALWAYS;
12418
12419       p = strchr (p, ',');
12420       if (p != NULL)
12421         p++;
12422     }
12423
12424   if (intel_syntax)
12425     {
12426       names64 = intel_names64;
12427       names32 = intel_names32;
12428       names16 = intel_names16;
12429       names8 = intel_names8;
12430       names8rex = intel_names8rex;
12431       names_seg = intel_names_seg;
12432       names_mm = intel_names_mm;
12433       names_bnd = intel_names_bnd;
12434       names_xmm = intel_names_xmm;
12435       names_ymm = intel_names_ymm;
12436       names_zmm = intel_names_zmm;
12437       index64 = intel_index64;
12438       index32 = intel_index32;
12439       names_mask = intel_names_mask;
12440       index16 = intel_index16;
12441       open_char = '[';
12442       close_char = ']';
12443       separator_char = '+';
12444       scale_char = '*';
12445     }
12446   else
12447     {
12448       names64 = att_names64;
12449       names32 = att_names32;
12450       names16 = att_names16;
12451       names8 = att_names8;
12452       names8rex = att_names8rex;
12453       names_seg = att_names_seg;
12454       names_mm = att_names_mm;
12455       names_bnd = att_names_bnd;
12456       names_xmm = att_names_xmm;
12457       names_ymm = att_names_ymm;
12458       names_zmm = att_names_zmm;
12459       index64 = att_index64;
12460       index32 = att_index32;
12461       names_mask = att_names_mask;
12462       index16 = att_index16;
12463       open_char = '(';
12464       close_char =  ')';
12465       separator_char = ',';
12466       scale_char = ',';
12467     }
12468
12469   /* The output looks better if we put 7 bytes on a line, since that
12470      puts most long word instructions on a single line.  Use 8 bytes
12471      for Intel L1OM.  */
12472   if ((info->mach & bfd_mach_l1om) != 0)
12473     info->bytes_per_line = 8;
12474   else
12475     info->bytes_per_line = 7;
12476
12477   info->private_data = &priv;
12478   priv.max_fetched = priv.the_buffer;
12479   priv.insn_start = pc;
12480
12481   obuf[0] = 0;
12482   for (i = 0; i < MAX_OPERANDS; ++i)
12483     {
12484       op_out[i][0] = 0;
12485       op_index[i] = -1;
12486     }
12487
12488   the_info = info;
12489   start_pc = pc;
12490   start_codep = priv.the_buffer;
12491   codep = priv.the_buffer;
12492
12493   if (setjmp (priv.bailout) != 0)
12494     {
12495       const char *name;
12496
12497       /* Getting here means we tried for data but didn't get it.  That
12498          means we have an incomplete instruction of some sort.  Just
12499          print the first byte as a prefix or a .byte pseudo-op.  */
12500       if (codep > priv.the_buffer)
12501         {
12502           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
12503           if (name != NULL)
12504             (*info->fprintf_func) (info->stream, "%s", name);
12505           else
12506             {
12507               /* Just print the first byte as a .byte instruction.  */
12508               (*info->fprintf_func) (info->stream, ".byte 0x%x",
12509                                      (unsigned int) priv.the_buffer[0]);
12510             }
12511
12512           return 1;
12513         }
12514
12515       return -1;
12516     }
12517
12518   obufp = obuf;
12519   sizeflag = priv.orig_sizeflag;
12520
12521   if (!ckprefix () || rex_used)
12522     {
12523       /* Too many prefixes or unused REX prefixes.  */
12524       for (i = 0;
12525            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
12526            i++)
12527         (*info->fprintf_func) (info->stream, "%s%s",
12528                                i == 0 ? "" : " ",
12529                                prefix_name (all_prefixes[i], sizeflag));
12530       return i;
12531     }
12532
12533   insn_codep = codep;
12534
12535   FETCH_DATA (info, codep + 1);
12536   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
12537
12538   if (((prefixes & PREFIX_FWAIT)
12539        && ((*codep < 0xd8) || (*codep > 0xdf))))
12540     {
12541       (*info->fprintf_func) (info->stream, "fwait");
12542       return 1;
12543     }
12544
12545   if (*codep == 0x0f)
12546     {
12547       unsigned char threebyte;
12548       FETCH_DATA (info, codep + 2);
12549       threebyte = *++codep;
12550       dp = &dis386_twobyte[threebyte];
12551       need_modrm = twobyte_has_modrm[*codep];
12552       codep++;
12553     }
12554   else
12555     {
12556       dp = &dis386[*codep];
12557       need_modrm = onebyte_has_modrm[*codep];
12558       codep++;
12559     }
12560
12561   if ((prefixes & PREFIX_REPZ))
12562     used_prefixes |= PREFIX_REPZ;
12563   if ((prefixes & PREFIX_REPNZ))
12564     used_prefixes |= PREFIX_REPNZ;
12565   if ((prefixes & PREFIX_LOCK))
12566     used_prefixes |= PREFIX_LOCK;
12567
12568   default_prefixes = 0;
12569   if (prefixes & PREFIX_ADDR)
12570     {
12571       sizeflag ^= AFLAG;
12572       if (dp->op[2].bytemode != loop_jcxz_mode || intel_syntax)
12573         {
12574           if ((sizeflag & AFLAG) || address_mode == mode_64bit)
12575             all_prefixes[last_addr_prefix] = ADDR32_PREFIX;
12576           else
12577             all_prefixes[last_addr_prefix] = ADDR16_PREFIX;
12578           default_prefixes |= PREFIX_ADDR;
12579         }
12580     }
12581
12582   if ((prefixes & PREFIX_DATA))
12583     {
12584       sizeflag ^= DFLAG;
12585       if (dp->op[2].bytemode == cond_jump_mode
12586           && dp->op[0].bytemode == v_mode
12587           && !intel_syntax)
12588         {
12589           if (sizeflag & DFLAG)
12590             all_prefixes[last_data_prefix] = DATA32_PREFIX;
12591           else
12592             all_prefixes[last_data_prefix] = DATA16_PREFIX;
12593           default_prefixes |= PREFIX_DATA;
12594         }
12595       else if (rex & REX_W)
12596         {
12597           /* REX_W will override PREFIX_DATA.  */
12598           default_prefixes |= PREFIX_DATA;
12599         }
12600     }
12601
12602   if (need_modrm)
12603     {
12604       FETCH_DATA (info, codep + 1);
12605       modrm.mod = (*codep >> 6) & 3;
12606       modrm.reg = (*codep >> 3) & 7;
12607       modrm.rm = *codep & 7;
12608     }
12609
12610   need_vex = 0;
12611   need_vex_reg = 0;
12612   vex_w_done = 0;
12613   vex.evex = 0;
12614
12615   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
12616     {
12617       get_sib (info, sizeflag);
12618       dofloat (sizeflag);
12619     }
12620   else
12621     {
12622       dp = get_valid_dis386 (dp, info);
12623       if (dp != NULL && putop (dp->name, sizeflag) == 0)
12624         {
12625           get_sib (info, sizeflag);
12626           for (i = 0; i < MAX_OPERANDS; ++i)
12627             {
12628               obufp = op_out[i];
12629               op_ad = MAX_OPERANDS - 1 - i;
12630               if (dp->op[i].rtn)
12631                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
12632               /* For EVEX instruction after the last operand masking
12633                  should be printed.  */
12634               if (i == 0 && vex.evex)
12635                 {
12636                   /* Don't print {%k0}.  */
12637                   if (vex.mask_register_specifier)
12638                     {
12639                       oappend ("{");
12640                       oappend (names_mask[vex.mask_register_specifier]);
12641                       oappend ("}");
12642                     }
12643                   if (vex.zeroing)
12644                     oappend ("{z}");
12645                 }
12646             }
12647         }
12648     }
12649
12650   /* See if any prefixes were not used.  If so, print the first one
12651      separately.  If we don't do this, we'll wind up printing an
12652      instruction stream which does not precisely correspond to the
12653      bytes we are disassembling.  */
12654   if ((prefixes & ~(used_prefixes | default_prefixes)) != 0)
12655     {
12656       for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12657         if (all_prefixes[i])
12658           {
12659             const char *name;
12660             name = prefix_name (all_prefixes[i], priv.orig_sizeflag);
12661             if (name == NULL)
12662               name = INTERNAL_DISASSEMBLER_ERROR;
12663             (*info->fprintf_func) (info->stream, "%s", name);
12664             return 1;
12665           }
12666     }
12667
12668   /* Check if the REX prefix is used.  */
12669   if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)
12670     all_prefixes[last_rex_prefix] = 0;
12671
12672   /* Check if the SEG prefix is used.  */
12673   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
12674                    | PREFIX_FS | PREFIX_GS)) != 0
12675       && (used_prefixes
12676           & seg_prefix (all_prefixes[last_seg_prefix])) != 0)
12677     all_prefixes[last_seg_prefix] = 0;
12678
12679   /* Check if the ADDR prefix is used.  */
12680   if ((prefixes & PREFIX_ADDR) != 0
12681       && (used_prefixes & PREFIX_ADDR) != 0)
12682     all_prefixes[last_addr_prefix] = 0;
12683
12684   /* Check if the DATA prefix is used.  */
12685   if ((prefixes & PREFIX_DATA) != 0
12686       && (used_prefixes & PREFIX_DATA) != 0)
12687     all_prefixes[last_data_prefix] = 0;
12688
12689   prefix_length = 0;
12690   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12691     if (all_prefixes[i])
12692       {
12693         const char *name;
12694         name = prefix_name (all_prefixes[i], sizeflag);
12695         if (name == NULL)
12696           abort ();
12697         prefix_length += strlen (name) + 1;
12698         (*info->fprintf_func) (info->stream, "%s ", name);
12699       }
12700
12701   /* Check maximum code length.  */
12702   if ((codep - start_codep) > MAX_CODE_LENGTH)
12703     {
12704       (*info->fprintf_func) (info->stream, "(bad)");
12705       return MAX_CODE_LENGTH;
12706     }
12707
12708   obufp = mnemonicendp;
12709   for (i = strlen (obuf) + prefix_length; i < 6; i++)
12710     oappend (" ");
12711   oappend (" ");
12712   (*info->fprintf_func) (info->stream, "%s", obuf);
12713
12714   /* The enter and bound instructions are printed with operands in the same
12715      order as the intel book; everything else is printed in reverse order.  */
12716   if (intel_syntax || two_source_ops)
12717     {
12718       bfd_vma riprel;
12719
12720       for (i = 0; i < MAX_OPERANDS; ++i)
12721         op_txt[i] = op_out[i];
12722
12723       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
12724         {
12725           op_ad = op_index[i];
12726           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
12727           op_index[MAX_OPERANDS - 1 - i] = op_ad;
12728           riprel = op_riprel[i];
12729           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
12730           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
12731         }
12732     }
12733   else
12734     {
12735       for (i = 0; i < MAX_OPERANDS; ++i)
12736         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
12737     }
12738
12739   needcomma = 0;
12740   for (i = 0; i < MAX_OPERANDS; ++i)
12741     if (*op_txt[i])
12742       {
12743         if (needcomma)
12744           (*info->fprintf_func) (info->stream, ",");
12745         if (op_index[i] != -1 && !op_riprel[i])
12746           (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
12747         else
12748           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
12749         needcomma = 1;
12750       }
12751
12752   for (i = 0; i < MAX_OPERANDS; i++)
12753     if (op_index[i] != -1 && op_riprel[i])
12754       {
12755         (*info->fprintf_func) (info->stream, "        # ");
12756         (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep
12757                                                 + op_address[op_index[i]]), info);
12758         break;
12759       }
12760   return codep - priv.the_buffer;
12761 }
12762
12763 static const char *float_mem[] = {
12764   /* d8 */
12765   "fadd{s|}",
12766   "fmul{s|}",
12767   "fcom{s|}",
12768   "fcomp{s|}",
12769   "fsub{s|}",
12770   "fsubr{s|}",
12771   "fdiv{s|}",
12772   "fdivr{s|}",
12773   /* d9 */
12774   "fld{s|}",
12775   "(bad)",
12776   "fst{s|}",
12777   "fstp{s|}",
12778   "fldenvIC",
12779   "fldcw",
12780   "fNstenvIC",
12781   "fNstcw",
12782   /* da */
12783   "fiadd{l|}",
12784   "fimul{l|}",
12785   "ficom{l|}",
12786   "ficomp{l|}",
12787   "fisub{l|}",
12788   "fisubr{l|}",
12789   "fidiv{l|}",
12790   "fidivr{l|}",
12791   /* db */
12792   "fild{l|}",
12793   "fisttp{l|}",
12794   "fist{l|}",
12795   "fistp{l|}",
12796   "(bad)",
12797   "fld{t||t|}",
12798   "(bad)",
12799   "fstp{t||t|}",
12800   /* dc */
12801   "fadd{l|}",
12802   "fmul{l|}",
12803   "fcom{l|}",
12804   "fcomp{l|}",
12805   "fsub{l|}",
12806   "fsubr{l|}",
12807   "fdiv{l|}",
12808   "fdivr{l|}",
12809   /* dd */
12810   "fld{l|}",
12811   "fisttp{ll|}",
12812   "fst{l||}",
12813   "fstp{l|}",
12814   "frstorIC",
12815   "(bad)",
12816   "fNsaveIC",
12817   "fNstsw",
12818   /* de */
12819   "fiadd",
12820   "fimul",
12821   "ficom",
12822   "ficomp",
12823   "fisub",
12824   "fisubr",
12825   "fidiv",
12826   "fidivr",
12827   /* df */
12828   "fild",
12829   "fisttp",
12830   "fist",
12831   "fistp",
12832   "fbld",
12833   "fild{ll|}",
12834   "fbstp",
12835   "fistp{ll|}",
12836 };
12837
12838 static const unsigned char float_mem_mode[] = {
12839   /* d8 */
12840   d_mode,
12841   d_mode,
12842   d_mode,
12843   d_mode,
12844   d_mode,
12845   d_mode,
12846   d_mode,
12847   d_mode,
12848   /* d9 */
12849   d_mode,
12850   0,
12851   d_mode,
12852   d_mode,
12853   0,
12854   w_mode,
12855   0,
12856   w_mode,
12857   /* da */
12858   d_mode,
12859   d_mode,
12860   d_mode,
12861   d_mode,
12862   d_mode,
12863   d_mode,
12864   d_mode,
12865   d_mode,
12866   /* db */
12867   d_mode,
12868   d_mode,
12869   d_mode,
12870   d_mode,
12871   0,
12872   t_mode,
12873   0,
12874   t_mode,
12875   /* dc */
12876   q_mode,
12877   q_mode,
12878   q_mode,
12879   q_mode,
12880   q_mode,
12881   q_mode,
12882   q_mode,
12883   q_mode,
12884   /* dd */
12885   q_mode,
12886   q_mode,
12887   q_mode,
12888   q_mode,
12889   0,
12890   0,
12891   0,
12892   w_mode,
12893   /* de */
12894   w_mode,
12895   w_mode,
12896   w_mode,
12897   w_mode,
12898   w_mode,
12899   w_mode,
12900   w_mode,
12901   w_mode,
12902   /* df */
12903   w_mode,
12904   w_mode,
12905   w_mode,
12906   w_mode,
12907   t_mode,
12908   q_mode,
12909   t_mode,
12910   q_mode
12911 };
12912
12913 #define ST { OP_ST, 0 }
12914 #define STi { OP_STi, 0 }
12915
12916 #define FGRPd9_2 NULL, { { NULL, 0 } }
12917 #define FGRPd9_4 NULL, { { NULL, 1 } }
12918 #define FGRPd9_5 NULL, { { NULL, 2 } }
12919 #define FGRPd9_6 NULL, { { NULL, 3 } }
12920 #define FGRPd9_7 NULL, { { NULL, 4 } }
12921 #define FGRPda_5 NULL, { { NULL, 5 } }
12922 #define FGRPdb_4 NULL, { { NULL, 6 } }
12923 #define FGRPde_3 NULL, { { NULL, 7 } }
12924 #define FGRPdf_4 NULL, { { NULL, 8 } }
12925
12926 static const struct dis386 float_reg[][8] = {
12927   /* d8 */
12928   {
12929     { "fadd",   { ST, STi } },
12930     { "fmul",   { ST, STi } },
12931     { "fcom",   { STi } },
12932     { "fcomp",  { STi } },
12933     { "fsub",   { ST, STi } },
12934     { "fsubr",  { ST, STi } },
12935     { "fdiv",   { ST, STi } },
12936     { "fdivr",  { ST, STi } },
12937   },
12938   /* d9 */
12939   {
12940     { "fld",    { STi } },
12941     { "fxch",   { STi } },
12942     { FGRPd9_2 },
12943     { Bad_Opcode },
12944     { FGRPd9_4 },
12945     { FGRPd9_5 },
12946     { FGRPd9_6 },
12947     { FGRPd9_7 },
12948   },
12949   /* da */
12950   {
12951     { "fcmovb", { ST, STi } },
12952     { "fcmove", { ST, STi } },
12953     { "fcmovbe",{ ST, STi } },
12954     { "fcmovu", { ST, STi } },
12955     { Bad_Opcode },
12956     { FGRPda_5 },
12957     { Bad_Opcode },
12958     { Bad_Opcode },
12959   },
12960   /* db */
12961   {
12962     { "fcmovnb",{ ST, STi } },
12963     { "fcmovne",{ ST, STi } },
12964     { "fcmovnbe",{ ST, STi } },
12965     { "fcmovnu",{ ST, STi } },
12966     { FGRPdb_4 },
12967     { "fucomi", { ST, STi } },
12968     { "fcomi",  { ST, STi } },
12969     { Bad_Opcode },
12970   },
12971   /* dc */
12972   {
12973     { "fadd",   { STi, ST } },
12974     { "fmul",   { STi, ST } },
12975     { Bad_Opcode },
12976     { Bad_Opcode },
12977     { "fsub!M", { STi, ST } },
12978     { "fsubM",  { STi, ST } },
12979     { "fdiv!M", { STi, ST } },
12980     { "fdivM",  { STi, ST } },
12981   },
12982   /* dd */
12983   {
12984     { "ffree",  { STi } },
12985     { Bad_Opcode },
12986     { "fst",    { STi } },
12987     { "fstp",   { STi } },
12988     { "fucom",  { STi } },
12989     { "fucomp", { STi } },
12990     { Bad_Opcode },
12991     { Bad_Opcode },
12992   },
12993   /* de */
12994   {
12995     { "faddp",  { STi, ST } },
12996     { "fmulp",  { STi, ST } },
12997     { Bad_Opcode },
12998     { FGRPde_3 },
12999     { "fsub!Mp", { STi, ST } },
13000     { "fsubMp", { STi, ST } },
13001     { "fdiv!Mp", { STi, ST } },
13002     { "fdivMp", { STi, ST } },
13003   },
13004   /* df */
13005   {
13006     { "ffreep", { STi } },
13007     { Bad_Opcode },
13008     { Bad_Opcode },
13009     { Bad_Opcode },
13010     { FGRPdf_4 },
13011     { "fucomip", { ST, STi } },
13012     { "fcomip", { ST, STi } },
13013     { Bad_Opcode },
13014   },
13015 };
13016
13017 static char *fgrps[][8] = {
13018   /* d9_2  0 */
13019   {
13020     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13021   },
13022
13023   /* d9_4  1 */
13024   {
13025     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
13026   },
13027
13028   /* d9_5  2 */
13029   {
13030     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
13031   },
13032
13033   /* d9_6  3 */
13034   {
13035     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
13036   },
13037
13038   /* d9_7  4 */
13039   {
13040     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
13041   },
13042
13043   /* da_5  5 */
13044   {
13045     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13046   },
13047
13048   /* db_4  6 */
13049   {
13050     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
13051     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
13052   },
13053
13054   /* de_3  7 */
13055   {
13056     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13057   },
13058
13059   /* df_4  8 */
13060   {
13061     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13062   },
13063 };
13064
13065 static void
13066 swap_operand (void)
13067 {
13068   mnemonicendp[0] = '.';
13069   mnemonicendp[1] = 's';
13070   mnemonicendp += 2;
13071 }
13072
13073 static void
13074 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
13075                int sizeflag ATTRIBUTE_UNUSED)
13076 {
13077   /* Skip mod/rm byte.  */
13078   MODRM_CHECK;
13079   codep++;
13080 }
13081
13082 static void
13083 dofloat (int sizeflag)
13084 {
13085   const struct dis386 *dp;
13086   unsigned char floatop;
13087
13088   floatop = codep[-1];
13089
13090   if (modrm.mod != 3)
13091     {
13092       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
13093
13094       putop (float_mem[fp_indx], sizeflag);
13095       obufp = op_out[0];
13096       op_ad = 2;
13097       OP_E (float_mem_mode[fp_indx], sizeflag);
13098       return;
13099     }
13100   /* Skip mod/rm byte.  */
13101   MODRM_CHECK;
13102   codep++;
13103
13104   dp = &float_reg[floatop - 0xd8][modrm.reg];
13105   if (dp->name == NULL)
13106     {
13107       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
13108
13109       /* Instruction fnstsw is only one with strange arg.  */
13110       if (floatop == 0xdf && codep[-1] == 0xe0)
13111         strcpy (op_out[0], names16[0]);
13112     }
13113   else
13114     {
13115       putop (dp->name, sizeflag);
13116
13117       obufp = op_out[0];
13118       op_ad = 2;
13119       if (dp->op[0].rtn)
13120         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
13121
13122       obufp = op_out[1];
13123       op_ad = 1;
13124       if (dp->op[1].rtn)
13125         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
13126     }
13127 }
13128
13129 /* Like oappend (below), but S is a string starting with '%'.
13130    In Intel syntax, the '%' is elided.  */
13131 static void
13132 oappend_maybe_intel (const char *s)
13133 {
13134   oappend (s + intel_syntax);
13135 }
13136
13137 static void
13138 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13139 {
13140   oappend_maybe_intel ("%st");
13141 }
13142
13143 static void
13144 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13145 {
13146   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
13147   oappend_maybe_intel (scratchbuf);
13148 }
13149
13150 /* Capital letters in template are macros.  */
13151 static int
13152 putop (const char *in_template, int sizeflag)
13153 {
13154   const char *p;
13155   int alt = 0;
13156   int cond = 1;
13157   unsigned int l = 0, len = 1;
13158   char last[4];
13159
13160 #define SAVE_LAST(c)                    \
13161   if (l < len && l < sizeof (last))     \
13162     last[l++] = c;                      \
13163   else                                  \
13164     abort ();
13165
13166   for (p = in_template; *p; p++)
13167     {
13168       switch (*p)
13169         {
13170         default:
13171           *obufp++ = *p;
13172           break;
13173         case '%':
13174           len++;
13175           break;
13176         case '!':
13177           cond = 0;
13178           break;
13179         case '{':
13180           alt = 0;
13181           if (intel_syntax)
13182             {
13183               while (*++p != '|')
13184                 if (*p == '}' || *p == '\0')
13185                   abort ();
13186             }
13187           /* Fall through.  */
13188         case 'I':
13189           alt = 1;
13190           continue;
13191         case '|':
13192           while (*++p != '}')
13193             {
13194               if (*p == '\0')
13195                 abort ();
13196             }
13197           break;
13198         case '}':
13199           break;
13200         case 'A':
13201           if (intel_syntax)
13202             break;
13203           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13204             *obufp++ = 'b';
13205           break;
13206         case 'B':
13207           if (l == 0 && len == 1)
13208             {
13209 case_B:
13210               if (intel_syntax)
13211                 break;
13212               if (sizeflag & SUFFIX_ALWAYS)
13213                 *obufp++ = 'b';
13214             }
13215           else
13216             {
13217               if (l != 1
13218                   || len != 2
13219                   || last[0] != 'L')
13220                 {
13221                   SAVE_LAST (*p);
13222                   break;
13223                 }
13224
13225               if (address_mode == mode_64bit
13226                   && !(prefixes & PREFIX_ADDR))
13227                 {
13228                   *obufp++ = 'a';
13229                   *obufp++ = 'b';
13230                   *obufp++ = 's';
13231                 }
13232
13233               goto case_B;
13234             }
13235           break;
13236         case 'C':
13237           if (intel_syntax && !alt)
13238             break;
13239           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
13240             {
13241               if (sizeflag & DFLAG)
13242                 *obufp++ = intel_syntax ? 'd' : 'l';
13243               else
13244                 *obufp++ = intel_syntax ? 'w' : 's';
13245               used_prefixes |= (prefixes & PREFIX_DATA);
13246             }
13247           break;
13248         case 'D':
13249           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
13250             break;
13251           USED_REX (REX_W);
13252           if (modrm.mod == 3)
13253             {
13254               if (rex & REX_W)
13255                 *obufp++ = 'q';
13256               else
13257                 {
13258                   if (sizeflag & DFLAG)
13259                     *obufp++ = intel_syntax ? 'd' : 'l';
13260                   else
13261                     *obufp++ = 'w';
13262                   used_prefixes |= (prefixes & PREFIX_DATA);
13263                 }
13264             }
13265           else
13266             *obufp++ = 'w';
13267           break;
13268         case 'E':               /* For jcxz/jecxz */
13269           if (address_mode == mode_64bit)
13270             {
13271               if (sizeflag & AFLAG)
13272                 *obufp++ = 'r';
13273               else
13274                 *obufp++ = 'e';
13275             }
13276           else
13277             if (sizeflag & AFLAG)
13278               *obufp++ = 'e';
13279           used_prefixes |= (prefixes & PREFIX_ADDR);
13280           break;
13281         case 'F':
13282           if (intel_syntax)
13283             break;
13284           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
13285             {
13286               if (sizeflag & AFLAG)
13287                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
13288               else
13289                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
13290               used_prefixes |= (prefixes & PREFIX_ADDR);
13291             }
13292           break;
13293         case 'G':
13294           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
13295             break;
13296           if ((rex & REX_W) || (sizeflag & DFLAG))
13297             *obufp++ = 'l';
13298           else
13299             *obufp++ = 'w';
13300           if (!(rex & REX_W))
13301             used_prefixes |= (prefixes & PREFIX_DATA);
13302           break;
13303         case 'H':
13304           if (intel_syntax)
13305             break;
13306           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
13307               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
13308             {
13309               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
13310               *obufp++ = ',';
13311               *obufp++ = 'p';
13312               if (prefixes & PREFIX_DS)
13313                 *obufp++ = 't';
13314               else
13315                 *obufp++ = 'n';
13316             }
13317           break;
13318         case 'J':
13319           if (intel_syntax)
13320             break;
13321           *obufp++ = 'l';
13322           break;
13323         case 'K':
13324           USED_REX (REX_W);
13325           if (rex & REX_W)
13326             *obufp++ = 'q';
13327           else
13328             *obufp++ = 'd';
13329           break;
13330         case 'Z':
13331           if (intel_syntax)
13332             break;
13333           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
13334             {
13335               *obufp++ = 'q';
13336               break;
13337             }
13338           /* Fall through.  */
13339           goto case_L;
13340         case 'L':
13341           if (l != 0 || len != 1)
13342             {
13343               SAVE_LAST (*p);
13344               break;
13345             }
13346 case_L:
13347           if (intel_syntax)
13348             break;
13349           if (sizeflag & SUFFIX_ALWAYS)
13350             *obufp++ = 'l';
13351           break;
13352         case 'M':
13353           if (intel_mnemonic != cond)
13354             *obufp++ = 'r';
13355           break;
13356         case 'N':
13357           if ((prefixes & PREFIX_FWAIT) == 0)
13358             *obufp++ = 'n';
13359           else
13360             used_prefixes |= PREFIX_FWAIT;
13361           break;
13362         case 'O':
13363           USED_REX (REX_W);
13364           if (rex & REX_W)
13365             *obufp++ = 'o';
13366           else if (intel_syntax && (sizeflag & DFLAG))
13367             *obufp++ = 'q';
13368           else
13369             *obufp++ = 'd';
13370           if (!(rex & REX_W))
13371             used_prefixes |= (prefixes & PREFIX_DATA);
13372           break;
13373         case 'T':
13374           if (!intel_syntax
13375               && address_mode == mode_64bit
13376               && ((sizeflag & DFLAG) || (rex & REX_W)))
13377             {
13378               *obufp++ = 'q';
13379               break;
13380             }
13381           /* Fall through.  */
13382         case 'P':
13383           if (intel_syntax)
13384             {
13385               if ((rex & REX_W) == 0
13386                   && (prefixes & PREFIX_DATA))
13387                 {
13388                   if ((sizeflag & DFLAG) == 0)
13389                     *obufp++ = 'w';
13390                    used_prefixes |= (prefixes & PREFIX_DATA);
13391                 }
13392               break;
13393             }
13394           if ((prefixes & PREFIX_DATA)
13395               || (rex & REX_W)
13396               || (sizeflag & SUFFIX_ALWAYS))
13397             {
13398               USED_REX (REX_W);
13399               if (rex & REX_W)
13400                 *obufp++ = 'q';
13401               else
13402                 {
13403                    if (sizeflag & DFLAG)
13404                       *obufp++ = 'l';
13405                    else
13406                      *obufp++ = 'w';
13407                    used_prefixes |= (prefixes & PREFIX_DATA);
13408                 }
13409             }
13410           break;
13411         case 'U':
13412           if (intel_syntax)
13413             break;
13414           if (address_mode == mode_64bit
13415               && ((sizeflag & DFLAG) || (rex & REX_W)))
13416             {
13417               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13418                 *obufp++ = 'q';
13419               break;
13420             }
13421           /* Fall through.  */
13422           goto case_Q;
13423         case 'Q':
13424           if (l == 0 && len == 1)
13425             {
13426 case_Q:
13427               if (intel_syntax && !alt)
13428                 break;
13429               USED_REX (REX_W);
13430               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13431                 {
13432                   if (rex & REX_W)
13433                     *obufp++ = 'q';
13434                   else
13435                     {
13436                       if (sizeflag & DFLAG)
13437                         *obufp++ = intel_syntax ? 'd' : 'l';
13438                       else
13439                         *obufp++ = 'w';
13440                       used_prefixes |= (prefixes & PREFIX_DATA);
13441                     }
13442                 }
13443             }
13444           else
13445             {
13446               if (l != 1 || len != 2 || last[0] != 'L')
13447                 {
13448                   SAVE_LAST (*p);
13449                   break;
13450                 }
13451               if (intel_syntax
13452                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
13453                 break;
13454               if ((rex & REX_W))
13455                 {
13456                   USED_REX (REX_W);
13457                   *obufp++ = 'q';
13458                 }
13459               else
13460                 *obufp++ = 'l';
13461             }
13462           break;
13463         case 'R':
13464           USED_REX (REX_W);
13465           if (rex & REX_W)
13466             *obufp++ = 'q';
13467           else if (sizeflag & DFLAG)
13468             {
13469               if (intel_syntax)
13470                   *obufp++ = 'd';
13471               else
13472                   *obufp++ = 'l';
13473             }
13474           else
13475             *obufp++ = 'w';
13476           if (intel_syntax && !p[1]
13477               && ((rex & REX_W) || (sizeflag & DFLAG)))
13478             *obufp++ = 'e';
13479           if (!(rex & REX_W))
13480             used_prefixes |= (prefixes & PREFIX_DATA);
13481           break;
13482         case 'V':
13483           if (l == 0 && len == 1)
13484             {
13485               if (intel_syntax)
13486                 break;
13487               if (address_mode == mode_64bit
13488                   && ((sizeflag & DFLAG) || (rex & REX_W)))
13489                 {
13490                   if (sizeflag & SUFFIX_ALWAYS)
13491                     *obufp++ = 'q';
13492                   break;
13493                 }
13494             }
13495           else
13496             {
13497               if (l != 1
13498                   || len != 2
13499                   || last[0] != 'L')
13500                 {
13501                   SAVE_LAST (*p);
13502                   break;
13503                 }
13504
13505               if (rex & REX_W)
13506                 {
13507                   *obufp++ = 'a';
13508                   *obufp++ = 'b';
13509                   *obufp++ = 's';
13510                 }
13511             }
13512           /* Fall through.  */
13513           goto case_S;
13514         case 'S':
13515           if (l == 0 && len == 1)
13516             {
13517 case_S:
13518               if (intel_syntax)
13519                 break;
13520               if (sizeflag & SUFFIX_ALWAYS)
13521                 {
13522                   if (rex & REX_W)
13523                     *obufp++ = 'q';
13524                   else
13525                     {
13526                       if (sizeflag & DFLAG)
13527                         *obufp++ = 'l';
13528                       else
13529                         *obufp++ = 'w';
13530                       used_prefixes |= (prefixes & PREFIX_DATA);
13531                     }
13532                 }
13533             }
13534           else
13535             {
13536               if (l != 1
13537                   || len != 2
13538                   || last[0] != 'L')
13539                 {
13540                   SAVE_LAST (*p);
13541                   break;
13542                 }
13543
13544               if (address_mode == mode_64bit
13545                   && !(prefixes & PREFIX_ADDR))
13546                 {
13547                   *obufp++ = 'a';
13548                   *obufp++ = 'b';
13549                   *obufp++ = 's';
13550                 }
13551
13552               goto case_S;
13553             }
13554           break;
13555         case 'X':
13556           if (l != 0 || len != 1)
13557             {
13558               SAVE_LAST (*p);
13559               break;
13560             }
13561           if (need_vex && vex.prefix)
13562             {
13563               if (vex.prefix == DATA_PREFIX_OPCODE)
13564                 *obufp++ = 'd';
13565               else
13566                 *obufp++ = 's';
13567             }
13568           else
13569             {
13570               if (prefixes & PREFIX_DATA)
13571                 *obufp++ = 'd';
13572               else
13573                 *obufp++ = 's';
13574               used_prefixes |= (prefixes & PREFIX_DATA);
13575             }
13576           break;
13577         case 'Y':
13578           if (l == 0 && len == 1)
13579             {
13580               if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
13581                 break;
13582               if (rex & REX_W)
13583                 {
13584                   USED_REX (REX_W);
13585                   *obufp++ = 'q';
13586                 }
13587               break;
13588             }
13589           else
13590             {
13591               if (l != 1 || len != 2 || last[0] != 'X')
13592                 {
13593                   SAVE_LAST (*p);
13594                   break;
13595                 }
13596               if (!need_vex)
13597                 abort ();
13598               if (intel_syntax
13599                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
13600                 break;
13601               switch (vex.length)
13602                 {
13603                 case 128:
13604                   *obufp++ = 'x';
13605                   break;
13606                 case 256:
13607                   *obufp++ = 'y';
13608                   break;
13609                 default:
13610                   abort ();
13611                 }
13612             }
13613           break;
13614         case 'W':
13615           if (l == 0 && len == 1)
13616             {
13617               /* operand size flag for cwtl, cbtw */
13618               USED_REX (REX_W);
13619               if (rex & REX_W)
13620                 {
13621                   if (intel_syntax)
13622                     *obufp++ = 'd';
13623                   else
13624                     *obufp++ = 'l';
13625                 }
13626               else if (sizeflag & DFLAG)
13627                 *obufp++ = 'w';
13628               else
13629                 *obufp++ = 'b';
13630               if (!(rex & REX_W))
13631                 used_prefixes |= (prefixes & PREFIX_DATA);
13632             }
13633           else
13634             {
13635               if (l != 1
13636                   || len != 2
13637                   || (last[0] != 'X'
13638                       && last[0] != 'L'))
13639                 {
13640                   SAVE_LAST (*p);
13641                   break;
13642                 }
13643               if (!need_vex)
13644                 abort ();
13645               if (last[0] == 'X')
13646                 *obufp++ = vex.w ? 'd': 's';
13647               else
13648                 *obufp++ = vex.w ? 'q': 'd';
13649             }
13650           break;
13651         }
13652       alt = 0;
13653     }
13654   *obufp = 0;
13655   mnemonicendp = obufp;
13656   return 0;
13657 }
13658
13659 static void
13660 oappend (const char *s)
13661 {
13662   obufp = stpcpy (obufp, s);
13663 }
13664
13665 static void
13666 append_seg (void)
13667 {
13668   if (prefixes & PREFIX_CS)
13669     {
13670       used_prefixes |= PREFIX_CS;
13671       oappend_maybe_intel ("%cs:");
13672     }
13673   if (prefixes & PREFIX_DS)
13674     {
13675       used_prefixes |= PREFIX_DS;
13676       oappend_maybe_intel ("%ds:");
13677     }
13678   if (prefixes & PREFIX_SS)
13679     {
13680       used_prefixes |= PREFIX_SS;
13681       oappend_maybe_intel ("%ss:");
13682     }
13683   if (prefixes & PREFIX_ES)
13684     {
13685       used_prefixes |= PREFIX_ES;
13686       oappend_maybe_intel ("%es:");
13687     }
13688   if (prefixes & PREFIX_FS)
13689     {
13690       used_prefixes |= PREFIX_FS;
13691       oappend_maybe_intel ("%fs:");
13692     }
13693   if (prefixes & PREFIX_GS)
13694     {
13695       used_prefixes |= PREFIX_GS;
13696       oappend_maybe_intel ("%gs:");
13697     }
13698 }
13699
13700 static void
13701 OP_indirE (int bytemode, int sizeflag)
13702 {
13703   if (!intel_syntax)
13704     oappend ("*");
13705   OP_E (bytemode, sizeflag);
13706 }
13707
13708 static void
13709 print_operand_value (char *buf, int hex, bfd_vma disp)
13710 {
13711   if (address_mode == mode_64bit)
13712     {
13713       if (hex)
13714         {
13715           char tmp[30];
13716           int i;
13717           buf[0] = '0';
13718           buf[1] = 'x';
13719           sprintf_vma (tmp, disp);
13720           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
13721           strcpy (buf + 2, tmp + i);
13722         }
13723       else
13724         {
13725           bfd_signed_vma v = disp;
13726           char tmp[30];
13727           int i;
13728           if (v < 0)
13729             {
13730               *(buf++) = '-';
13731               v = -disp;
13732               /* Check for possible overflow on 0x8000000000000000.  */
13733               if (v < 0)
13734                 {
13735                   strcpy (buf, "9223372036854775808");
13736                   return;
13737                 }
13738             }
13739           if (!v)
13740             {
13741               strcpy (buf, "0");
13742               return;
13743             }
13744
13745           i = 0;
13746           tmp[29] = 0;
13747           while (v)
13748             {
13749               tmp[28 - i] = (v % 10) + '0';
13750               v /= 10;
13751               i++;
13752             }
13753           strcpy (buf, tmp + 29 - i);
13754         }
13755     }
13756   else
13757     {
13758       if (hex)
13759         sprintf (buf, "0x%x", (unsigned int) disp);
13760       else
13761         sprintf (buf, "%d", (int) disp);
13762     }
13763 }
13764
13765 /* Put DISP in BUF as signed hex number.  */
13766
13767 static void
13768 print_displacement (char *buf, bfd_vma disp)
13769 {
13770   bfd_signed_vma val = disp;
13771   char tmp[30];
13772   int i, j = 0;
13773
13774   if (val < 0)
13775     {
13776       buf[j++] = '-';
13777       val = -disp;
13778
13779       /* Check for possible overflow.  */
13780       if (val < 0)
13781         {
13782           switch (address_mode)
13783             {
13784             case mode_64bit:
13785               strcpy (buf + j, "0x8000000000000000");
13786               break;
13787             case mode_32bit:
13788               strcpy (buf + j, "0x80000000");
13789               break;
13790             case mode_16bit:
13791               strcpy (buf + j, "0x8000");
13792               break;
13793             }
13794           return;
13795         }
13796     }
13797
13798   buf[j++] = '0';
13799   buf[j++] = 'x';
13800
13801   sprintf_vma (tmp, (bfd_vma) val);
13802   for (i = 0; tmp[i] == '0'; i++)
13803     continue;
13804   if (tmp[i] == '\0')
13805     i--;
13806   strcpy (buf + j, tmp + i);
13807 }
13808
13809 static void
13810 intel_operand_size (int bytemode, int sizeflag)
13811 {
13812   if (vex.evex
13813       && vex.b
13814       && (bytemode == x_mode
13815           || bytemode == evex_half_bcst_xmmq_mode))
13816     {
13817       if (vex.w)
13818         oappend ("QWORD PTR ");
13819       else
13820         oappend ("DWORD PTR ");
13821       return;
13822     }
13823   switch (bytemode)
13824     {
13825     case b_mode:
13826     case b_swap_mode:
13827     case dqb_mode:
13828       oappend ("BYTE PTR ");
13829       break;
13830     case w_mode:
13831     case dqw_mode:
13832       oappend ("WORD PTR ");
13833       break;
13834     case stack_v_mode:
13835       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
13836         {
13837           oappend ("QWORD PTR ");
13838           break;
13839         }
13840       /* FALLTHRU */
13841     case v_mode:
13842     case v_swap_mode:
13843     case dq_mode:
13844       USED_REX (REX_W);
13845       if (rex & REX_W)
13846         oappend ("QWORD PTR ");
13847       else
13848         {
13849           if ((sizeflag & DFLAG) || bytemode == dq_mode)
13850             oappend ("DWORD PTR ");
13851           else
13852             oappend ("WORD PTR ");
13853           used_prefixes |= (prefixes & PREFIX_DATA);
13854         }
13855       break;
13856     case z_mode:
13857       if ((rex & REX_W) || (sizeflag & DFLAG))
13858         *obufp++ = 'D';
13859       oappend ("WORD PTR ");
13860       if (!(rex & REX_W))
13861         used_prefixes |= (prefixes & PREFIX_DATA);
13862       break;
13863     case a_mode:
13864       if (sizeflag & DFLAG)
13865         oappend ("QWORD PTR ");
13866       else
13867         oappend ("DWORD PTR ");
13868       used_prefixes |= (prefixes & PREFIX_DATA);
13869       break;
13870     case d_mode:
13871     case d_scalar_mode:
13872     case d_scalar_swap_mode:
13873     case d_swap_mode:
13874     case dqd_mode:
13875       oappend ("DWORD PTR ");
13876       break;
13877     case q_mode:
13878     case q_scalar_mode:
13879     case q_scalar_swap_mode:
13880     case q_swap_mode:
13881       oappend ("QWORD PTR ");
13882       break;
13883     case m_mode:
13884       if (address_mode == mode_64bit)
13885         oappend ("QWORD PTR ");
13886       else
13887         oappend ("DWORD PTR ");
13888       break;
13889     case f_mode:
13890       if (sizeflag & DFLAG)
13891         oappend ("FWORD PTR ");
13892       else
13893         oappend ("DWORD PTR ");
13894       used_prefixes |= (prefixes & PREFIX_DATA);
13895       break;
13896     case t_mode:
13897       oappend ("TBYTE PTR ");
13898       break;
13899     case x_mode:
13900     case x_swap_mode:
13901     case evex_x_gscat_mode:
13902     case evex_x_nobcst_mode:
13903       if (need_vex)
13904         {
13905           switch (vex.length)
13906             {
13907             case 128:
13908               oappend ("XMMWORD PTR ");
13909               break;
13910             case 256:
13911               oappend ("YMMWORD PTR ");
13912               break;
13913             case 512:
13914               oappend ("ZMMWORD PTR ");
13915               break;
13916             default:
13917               abort ();
13918             }
13919         }
13920       else
13921         oappend ("XMMWORD PTR ");
13922       break;
13923     case xmm_mode:
13924       oappend ("XMMWORD PTR ");
13925       break;
13926     case ymm_mode:
13927       oappend ("YMMWORD PTR ");
13928       break;
13929     case xmmq_mode:
13930     case evex_half_bcst_xmmq_mode:
13931       if (!need_vex)
13932         abort ();
13933
13934       switch (vex.length)
13935         {
13936         case 128:
13937           oappend ("QWORD PTR ");
13938           break;
13939         case 256:
13940           oappend ("XMMWORD PTR ");
13941           break;
13942         case 512:
13943           oappend ("YMMWORD PTR ");
13944           break;
13945         default:
13946           abort ();
13947         }
13948       break;
13949     case xmm_mb_mode:
13950       if (!need_vex)
13951         abort ();
13952
13953       switch (vex.length)
13954         {
13955         case 128:
13956         case 256:
13957         case 512:
13958           oappend ("BYTE PTR ");
13959           break;
13960         default:
13961           abort ();
13962         }
13963       break;
13964     case xmm_mw_mode:
13965       if (!need_vex)
13966         abort ();
13967
13968       switch (vex.length)
13969         {
13970         case 128:
13971         case 256:
13972         case 512:
13973           oappend ("WORD PTR ");
13974           break;
13975         default:
13976           abort ();
13977         }
13978       break;
13979     case xmm_md_mode:
13980       if (!need_vex)
13981         abort ();
13982
13983       switch (vex.length)
13984         {
13985         case 128:
13986         case 256:
13987         case 512:
13988           oappend ("DWORD PTR ");
13989           break;
13990         default:
13991           abort ();
13992         }
13993       break;
13994     case xmm_mq_mode:
13995       if (!need_vex)
13996         abort ();
13997
13998       switch (vex.length)
13999         {
14000         case 128:
14001         case 256:
14002         case 512:
14003           oappend ("QWORD PTR ");
14004           break;
14005         default:
14006           abort ();
14007         }
14008       break;
14009     case xmmdw_mode:
14010       if (!need_vex)
14011         abort ();
14012
14013       switch (vex.length)
14014         {
14015         case 128:
14016           oappend ("WORD PTR ");
14017           break;
14018         case 256:
14019           oappend ("DWORD PTR ");
14020           break;
14021         case 512:
14022           oappend ("QWORD PTR ");
14023           break;
14024         default:
14025           abort ();
14026         }
14027       break;
14028     case xmmqd_mode:
14029       if (!need_vex)
14030         abort ();
14031
14032       switch (vex.length)
14033         {
14034         case 128:
14035           oappend ("DWORD PTR ");
14036           break;
14037         case 256:
14038           oappend ("QWORD PTR ");
14039           break;
14040         case 512:
14041           oappend ("XMMWORD PTR ");
14042           break;
14043         default:
14044           abort ();
14045         }
14046       break;
14047     case ymmq_mode:
14048       if (!need_vex)
14049         abort ();
14050
14051       switch (vex.length)
14052         {
14053         case 128:
14054           oappend ("QWORD PTR ");
14055           break;
14056         case 256:
14057           oappend ("YMMWORD PTR ");
14058           break;
14059         case 512:
14060           oappend ("ZMMWORD PTR ");
14061           break;
14062         default:
14063           abort ();
14064         }
14065       break;
14066     case ymmxmm_mode:
14067       if (!need_vex)
14068         abort ();
14069
14070       switch (vex.length)
14071         {
14072         case 128:
14073         case 256:
14074           oappend ("XMMWORD PTR ");
14075           break;
14076         default:
14077           abort ();
14078         }
14079       break;
14080     case o_mode:
14081       oappend ("OWORD PTR ");
14082       break;
14083     case xmm_mdq_mode:
14084     case vex_w_dq_mode:
14085     case vex_scalar_w_dq_mode:
14086       if (!need_vex)
14087         abort ();
14088
14089       if (vex.w)
14090         oappend ("QWORD PTR ");
14091       else
14092         oappend ("DWORD PTR ");
14093       break;
14094     case vex_vsib_d_w_dq_mode:
14095     case vex_vsib_q_w_dq_mode:
14096       if (!need_vex)
14097         abort ();
14098
14099       if (!vex.evex)
14100         {
14101           if (vex.w)
14102             oappend ("QWORD PTR ");
14103           else
14104             oappend ("DWORD PTR ");
14105         }
14106       else
14107         {
14108           if (vex.length != 512)
14109             abort ();
14110           oappend ("ZMMWORD PTR ");
14111         }
14112       break;
14113     case mask_mode:
14114       if (!need_vex)
14115         abort ();
14116       /* Currently the only instructions, which allows either mask or
14117          memory operand, are AVX512's KMOVW instructions.  They need
14118          Word-sized operand.  */
14119       if (vex.w || vex.length != 128)
14120         abort ();
14121       oappend ("WORD PTR ");
14122       break;
14123     case v_bnd_mode:
14124     default:
14125       break;
14126     }
14127 }
14128
14129 static void
14130 OP_E_register (int bytemode, int sizeflag)
14131 {
14132   int reg = modrm.rm;
14133   const char **names;
14134
14135   USED_REX (REX_B);
14136   if ((rex & REX_B))
14137     reg += 8;
14138
14139   if ((sizeflag & SUFFIX_ALWAYS)
14140       && (bytemode == b_swap_mode || bytemode == v_swap_mode))
14141     swap_operand ();
14142
14143   switch (bytemode)
14144     {
14145     case b_mode:
14146     case b_swap_mode:
14147       USED_REX (0);
14148       if (rex)
14149         names = names8rex;
14150       else
14151         names = names8;
14152       break;
14153     case w_mode:
14154       names = names16;
14155       break;
14156     case d_mode:
14157       names = names32;
14158       break;
14159     case q_mode:
14160       names = names64;
14161       break;
14162     case m_mode:
14163     case v_bnd_mode:
14164       names = address_mode == mode_64bit ? names64 : names32;
14165       break;
14166     case bnd_mode:
14167       names = names_bnd;
14168       break;
14169     case stack_v_mode:
14170       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14171         {
14172           names = names64;
14173           break;
14174         }
14175       bytemode = v_mode;
14176       /* FALLTHRU */
14177     case v_mode:
14178     case v_swap_mode:
14179     case dq_mode:
14180     case dqb_mode:
14181     case dqd_mode:
14182     case dqw_mode:
14183       USED_REX (REX_W);
14184       if (rex & REX_W)
14185         names = names64;
14186       else
14187         {
14188           if ((sizeflag & DFLAG)
14189               || (bytemode != v_mode
14190                   && bytemode != v_swap_mode))
14191             names = names32;
14192           else
14193             names = names16;
14194           used_prefixes |= (prefixes & PREFIX_DATA);
14195         }
14196       break;
14197     case mask_mode:
14198       names = names_mask;
14199       break;
14200     case 0:
14201       return;
14202     default:
14203       oappend (INTERNAL_DISASSEMBLER_ERROR);
14204       return;
14205     }
14206   oappend (names[reg]);
14207 }
14208
14209 static void
14210 OP_E_memory (int bytemode, int sizeflag)
14211 {
14212   bfd_vma disp = 0;
14213   int add = (rex & REX_B) ? 8 : 0;
14214   int riprel = 0;
14215   int shift;
14216
14217   if (vex.evex)
14218     {
14219       /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0.  */
14220       if (vex.b
14221           && bytemode != x_mode
14222           && bytemode != evex_half_bcst_xmmq_mode)
14223         {
14224           BadOp ();
14225           return;
14226         }
14227       switch (bytemode)
14228         {
14229         case vex_vsib_d_w_dq_mode:
14230         case vex_vsib_q_w_dq_mode:
14231         case evex_x_gscat_mode:
14232         case xmm_mdq_mode:
14233           shift = vex.w ? 3 : 2;
14234           break;
14235         case x_mode:
14236         case evex_half_bcst_xmmq_mode:
14237           if (vex.b)
14238             {
14239               shift = vex.w ? 3 : 2;
14240               break;
14241             }
14242           /* Fall through if vex.b == 0.  */
14243         case xmmqd_mode:
14244         case xmmdw_mode:
14245         case xmmq_mode:
14246         case ymmq_mode:
14247         case evex_x_nobcst_mode:
14248         case x_swap_mode:
14249           switch (vex.length)
14250             {
14251             case 128:
14252               shift = 4;
14253               break;
14254             case 256:
14255               shift = 5;
14256               break;
14257             case 512:
14258               shift = 6;
14259               break;
14260             default:
14261               abort ();
14262             }
14263           break;
14264         case ymm_mode:
14265           shift = 5;
14266           break;
14267         case xmm_mode:
14268           shift = 4;
14269           break;
14270         case xmm_mq_mode:
14271         case q_mode:
14272         case q_scalar_mode:
14273         case q_swap_mode:
14274         case q_scalar_swap_mode:
14275           shift = 3;
14276           break;
14277         case dqd_mode:
14278         case xmm_md_mode:
14279         case d_mode:
14280         case d_scalar_mode:
14281         case d_swap_mode:
14282         case d_scalar_swap_mode:
14283           shift = 2;
14284           break;
14285         case xmm_mw_mode:
14286           shift = 1;
14287           break;
14288         case xmm_mb_mode:
14289           shift = 0;
14290           break;
14291         default:
14292           abort ();
14293         }
14294       /* Make necessary corrections to shift for modes that need it.
14295          For these modes we currently have shift 4, 5 or 6 depending on
14296          vex.length (it corresponds to xmmword, ymmword or zmmword
14297          operand).  We might want to make it 3, 4 or 5 (e.g. for
14298          xmmq_mode).  In case of broadcast enabled the corrections
14299          aren't needed, as element size is always 32 or 64 bits.  */
14300       if (bytemode == xmmq_mode
14301           || (bytemode == evex_half_bcst_xmmq_mode
14302               && !vex.b))
14303         shift -= 1;
14304       else if (bytemode == xmmqd_mode)
14305         shift -= 2;
14306       else if (bytemode == xmmdw_mode)
14307         shift -= 3;
14308     }
14309   else
14310     shift = 0;
14311
14312   USED_REX (REX_B);
14313   if (intel_syntax)
14314     intel_operand_size (bytemode, sizeflag);
14315   append_seg ();
14316
14317   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14318     {
14319       /* 32/64 bit address mode */
14320       int havedisp;
14321       int havesib;
14322       int havebase;
14323       int haveindex;
14324       int needindex;
14325       int base, rbase;
14326       int vindex = 0;
14327       int scale = 0;
14328       int addr32flag = !((sizeflag & AFLAG)
14329                          || bytemode == v_bnd_mode
14330                          || bytemode == bnd_mode);
14331       const char **indexes64 = names64;
14332       const char **indexes32 = names32;
14333
14334       havesib = 0;
14335       havebase = 1;
14336       haveindex = 0;
14337       base = modrm.rm;
14338
14339       if (base == 4)
14340         {
14341           havesib = 1;
14342           vindex = sib.index;
14343           USED_REX (REX_X);
14344           if (rex & REX_X)
14345             vindex += 8;
14346           switch (bytemode)
14347             {
14348             case vex_vsib_d_w_dq_mode:
14349             case vex_vsib_q_w_dq_mode:
14350               if (!need_vex)
14351                 abort ();
14352               if (vex.evex)
14353                 {
14354                   if (!vex.v)
14355                     vindex += 16;
14356                 }
14357
14358               haveindex = 1;
14359               switch (vex.length)
14360                 {
14361                 case 128:
14362                   indexes64 = indexes32 = names_xmm;
14363                   break;
14364                 case 256:
14365                   if (!vex.w || bytemode == vex_vsib_q_w_dq_mode)
14366                     indexes64 = indexes32 = names_ymm;
14367                   else
14368                     indexes64 = indexes32 = names_xmm;
14369                   break;
14370                 case 512:
14371                   if (!vex.w || bytemode == vex_vsib_q_w_dq_mode)
14372                     indexes64 = indexes32 = names_zmm;
14373                   else
14374                     indexes64 = indexes32 = names_ymm;
14375                   break;
14376                 default:
14377                   abort ();
14378                 }
14379               break;
14380             default:
14381               haveindex = vindex != 4;
14382               break;
14383             }
14384           scale = sib.scale;
14385           base = sib.base;
14386           codep++;
14387         }
14388       rbase = base + add;
14389
14390       switch (modrm.mod)
14391         {
14392         case 0:
14393           if (base == 5)
14394             {
14395               havebase = 0;
14396               if (address_mode == mode_64bit && !havesib)
14397                 riprel = 1;
14398               disp = get32s ();
14399             }
14400           break;
14401         case 1:
14402           FETCH_DATA (the_info, codep + 1);
14403           disp = *codep++;
14404           if ((disp & 0x80) != 0)
14405             disp -= 0x100;
14406           if (vex.evex && shift > 0)
14407             disp <<= shift;
14408           break;
14409         case 2:
14410           disp = get32s ();
14411           break;
14412         }
14413
14414       /* In 32bit mode, we need index register to tell [offset] from
14415          [eiz*1 + offset].  */
14416       needindex = (havesib
14417                    && !havebase
14418                    && !haveindex
14419                    && address_mode == mode_32bit);
14420       havedisp = (havebase
14421                   || needindex
14422                   || (havesib && (haveindex || scale != 0)));
14423
14424       if (!intel_syntax)
14425         if (modrm.mod != 0 || base == 5)
14426           {
14427             if (havedisp || riprel)
14428               print_displacement (scratchbuf, disp);
14429             else
14430               print_operand_value (scratchbuf, 1, disp);
14431             oappend (scratchbuf);
14432             if (riprel)
14433               {
14434                 set_op (disp, 1);
14435                 oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)");
14436               }
14437           }
14438
14439       if ((havebase || haveindex || riprel)
14440           && (bytemode != v_bnd_mode)
14441           && (bytemode != bnd_mode))
14442         used_prefixes |= PREFIX_ADDR;
14443
14444       if (havedisp || (intel_syntax && riprel))
14445         {
14446           *obufp++ = open_char;
14447           if (intel_syntax && riprel)
14448             {
14449               set_op (disp, 1);
14450               oappend (sizeflag & AFLAG ? "rip" : "eip");
14451             }
14452           *obufp = '\0';
14453           if (havebase)
14454             oappend (address_mode == mode_64bit && !addr32flag
14455                      ? names64[rbase] : names32[rbase]);
14456           if (havesib)
14457             {
14458               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
14459                  print index to tell base + index from base.  */
14460               if (scale != 0
14461                   || needindex
14462                   || haveindex
14463                   || (havebase && base != ESP_REG_NUM))
14464                 {
14465                   if (!intel_syntax || havebase)
14466                     {
14467                       *obufp++ = separator_char;
14468                       *obufp = '\0';
14469                     }
14470                   if (haveindex)
14471                     oappend (address_mode == mode_64bit && !addr32flag
14472                              ? indexes64[vindex] : indexes32[vindex]);
14473                   else
14474                     oappend (address_mode == mode_64bit && !addr32flag
14475                              ? index64 : index32);
14476
14477                   *obufp++ = scale_char;
14478                   *obufp = '\0';
14479                   sprintf (scratchbuf, "%d", 1 << scale);
14480                   oappend (scratchbuf);
14481                 }
14482             }
14483           if (intel_syntax
14484               && (disp || modrm.mod != 0 || base == 5))
14485             {
14486               if (!havedisp || (bfd_signed_vma) disp >= 0)
14487                 {
14488                   *obufp++ = '+';
14489                   *obufp = '\0';
14490                 }
14491               else if (modrm.mod != 1 && disp != -disp)
14492                 {
14493                   *obufp++ = '-';
14494                   *obufp = '\0';
14495                   disp = - (bfd_signed_vma) disp;
14496                 }
14497
14498               if (havedisp)
14499                 print_displacement (scratchbuf, disp);
14500               else
14501                 print_operand_value (scratchbuf, 1, disp);
14502               oappend (scratchbuf);
14503             }
14504
14505           *obufp++ = close_char;
14506           *obufp = '\0';
14507         }
14508       else if (intel_syntax)
14509         {
14510           if (modrm.mod != 0 || base == 5)
14511             {
14512               if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
14513                               | PREFIX_ES | PREFIX_FS | PREFIX_GS))
14514                 ;
14515               else
14516                 {
14517                   oappend (names_seg[ds_reg - es_reg]);
14518                   oappend (":");
14519                 }
14520               print_operand_value (scratchbuf, 1, disp);
14521               oappend (scratchbuf);
14522             }
14523         }
14524     }
14525   else
14526     {
14527       /* 16 bit address mode */
14528       used_prefixes |= prefixes & PREFIX_ADDR;
14529       switch (modrm.mod)
14530         {
14531         case 0:
14532           if (modrm.rm == 6)
14533             {
14534               disp = get16 ();
14535               if ((disp & 0x8000) != 0)
14536                 disp -= 0x10000;
14537             }
14538           break;
14539         case 1:
14540           FETCH_DATA (the_info, codep + 1);
14541           disp = *codep++;
14542           if ((disp & 0x80) != 0)
14543             disp -= 0x100;
14544           break;
14545         case 2:
14546           disp = get16 ();
14547           if ((disp & 0x8000) != 0)
14548             disp -= 0x10000;
14549           break;
14550         }
14551
14552       if (!intel_syntax)
14553         if (modrm.mod != 0 || modrm.rm == 6)
14554           {
14555             print_displacement (scratchbuf, disp);
14556             oappend (scratchbuf);
14557           }
14558
14559       if (modrm.mod != 0 || modrm.rm != 6)
14560         {
14561           *obufp++ = open_char;
14562           *obufp = '\0';
14563           oappend (index16[modrm.rm]);
14564           if (intel_syntax
14565               && (disp || modrm.mod != 0 || modrm.rm == 6))
14566             {
14567               if ((bfd_signed_vma) disp >= 0)
14568                 {
14569                   *obufp++ = '+';
14570                   *obufp = '\0';
14571                 }
14572               else if (modrm.mod != 1)
14573                 {
14574                   *obufp++ = '-';
14575                   *obufp = '\0';
14576                   disp = - (bfd_signed_vma) disp;
14577                 }
14578
14579               print_displacement (scratchbuf, disp);
14580               oappend (scratchbuf);
14581             }
14582
14583           *obufp++ = close_char;
14584           *obufp = '\0';
14585         }
14586       else if (intel_syntax)
14587         {
14588           if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
14589                           | PREFIX_ES | PREFIX_FS | PREFIX_GS))
14590             ;
14591           else
14592             {
14593               oappend (names_seg[ds_reg - es_reg]);
14594               oappend (":");
14595             }
14596           print_operand_value (scratchbuf, 1, disp & 0xffff);
14597           oappend (scratchbuf);
14598         }
14599     }
14600   if (vex.evex && vex.b
14601       && (bytemode == x_mode
14602           || bytemode == evex_half_bcst_xmmq_mode))
14603     {
14604       if (vex.w || bytemode == evex_half_bcst_xmmq_mode)
14605         oappend ("{1to8}");
14606       else
14607         oappend ("{1to16}");
14608     }
14609 }
14610
14611 static void
14612 OP_E (int bytemode, int sizeflag)
14613 {
14614   /* Skip mod/rm byte.  */
14615   MODRM_CHECK;
14616   codep++;
14617
14618   if (modrm.mod == 3)
14619     OP_E_register (bytemode, sizeflag);
14620   else
14621     OP_E_memory (bytemode, sizeflag);
14622 }
14623
14624 static void
14625 OP_G (int bytemode, int sizeflag)
14626 {
14627   int add = 0;
14628   USED_REX (REX_R);
14629   if (rex & REX_R)
14630     add += 8;
14631   switch (bytemode)
14632     {
14633     case b_mode:
14634       USED_REX (0);
14635       if (rex)
14636         oappend (names8rex[modrm.reg + add]);
14637       else
14638         oappend (names8[modrm.reg + add]);
14639       break;
14640     case w_mode:
14641       oappend (names16[modrm.reg + add]);
14642       break;
14643     case d_mode:
14644       oappend (names32[modrm.reg + add]);
14645       break;
14646     case q_mode:
14647       oappend (names64[modrm.reg + add]);
14648       break;
14649     case bnd_mode:
14650       oappend (names_bnd[modrm.reg]);
14651       break;
14652     case v_mode:
14653     case dq_mode:
14654     case dqb_mode:
14655     case dqd_mode:
14656     case dqw_mode:
14657       USED_REX (REX_W);
14658       if (rex & REX_W)
14659         oappend (names64[modrm.reg + add]);
14660       else
14661         {
14662           if ((sizeflag & DFLAG) || bytemode != v_mode)
14663             oappend (names32[modrm.reg + add]);
14664           else
14665             oappend (names16[modrm.reg + add]);
14666           used_prefixes |= (prefixes & PREFIX_DATA);
14667         }
14668       break;
14669     case m_mode:
14670       if (address_mode == mode_64bit)
14671         oappend (names64[modrm.reg + add]);
14672       else
14673         oappend (names32[modrm.reg + add]);
14674       break;
14675     case mask_mode:
14676       oappend (names_mask[modrm.reg + add]);
14677       break;
14678     default:
14679       oappend (INTERNAL_DISASSEMBLER_ERROR);
14680       break;
14681     }
14682 }
14683
14684 static bfd_vma
14685 get64 (void)
14686 {
14687   bfd_vma x;
14688 #ifdef BFD64
14689   unsigned int a;
14690   unsigned int b;
14691
14692   FETCH_DATA (the_info, codep + 8);
14693   a = *codep++ & 0xff;
14694   a |= (*codep++ & 0xff) << 8;
14695   a |= (*codep++ & 0xff) << 16;
14696   a |= (*codep++ & 0xff) << 24;
14697   b = *codep++ & 0xff;
14698   b |= (*codep++ & 0xff) << 8;
14699   b |= (*codep++ & 0xff) << 16;
14700   b |= (*codep++ & 0xff) << 24;
14701   x = a + ((bfd_vma) b << 32);
14702 #else
14703   abort ();
14704   x = 0;
14705 #endif
14706   return x;
14707 }
14708
14709 static bfd_signed_vma
14710 get32 (void)
14711 {
14712   bfd_signed_vma x = 0;
14713
14714   FETCH_DATA (the_info, codep + 4);
14715   x = *codep++ & (bfd_signed_vma) 0xff;
14716   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14717   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14718   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14719   return x;
14720 }
14721
14722 static bfd_signed_vma
14723 get32s (void)
14724 {
14725   bfd_signed_vma x = 0;
14726
14727   FETCH_DATA (the_info, codep + 4);
14728   x = *codep++ & (bfd_signed_vma) 0xff;
14729   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14730   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14731   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14732
14733   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
14734
14735   return x;
14736 }
14737
14738 static int
14739 get16 (void)
14740 {
14741   int x = 0;
14742
14743   FETCH_DATA (the_info, codep + 2);
14744   x = *codep++ & 0xff;
14745   x |= (*codep++ & 0xff) << 8;
14746   return x;
14747 }
14748
14749 static void
14750 set_op (bfd_vma op, int riprel)
14751 {
14752   op_index[op_ad] = op_ad;
14753   if (address_mode == mode_64bit)
14754     {
14755       op_address[op_ad] = op;
14756       op_riprel[op_ad] = riprel;
14757     }
14758   else
14759     {
14760       /* Mask to get a 32-bit address.  */
14761       op_address[op_ad] = op & 0xffffffff;
14762       op_riprel[op_ad] = riprel & 0xffffffff;
14763     }
14764 }
14765
14766 static void
14767 OP_REG (int code, int sizeflag)
14768 {
14769   const char *s;
14770   int add;
14771
14772   switch (code)
14773     {
14774     case es_reg: case ss_reg: case cs_reg:
14775     case ds_reg: case fs_reg: case gs_reg:
14776       oappend (names_seg[code - es_reg]);
14777       return;
14778     }
14779
14780   USED_REX (REX_B);
14781   if (rex & REX_B)
14782     add = 8;
14783   else
14784     add = 0;
14785
14786   switch (code)
14787     {
14788     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14789     case sp_reg: case bp_reg: case si_reg: case di_reg:
14790       s = names16[code - ax_reg + add];
14791       break;
14792     case al_reg: case ah_reg: case cl_reg: case ch_reg:
14793     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14794       USED_REX (0);
14795       if (rex)
14796         s = names8rex[code - al_reg + add];
14797       else
14798         s = names8[code - al_reg];
14799       break;
14800     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
14801     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
14802       if (address_mode == mode_64bit
14803           && ((sizeflag & DFLAG) || (rex & REX_W)))
14804         {
14805           s = names64[code - rAX_reg + add];
14806           break;
14807         }
14808       code += eAX_reg - rAX_reg;
14809       /* Fall through.  */
14810     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14811     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14812       USED_REX (REX_W);
14813       if (rex & REX_W)
14814         s = names64[code - eAX_reg + add];
14815       else
14816         {
14817           if (sizeflag & DFLAG)
14818             s = names32[code - eAX_reg + add];
14819           else
14820             s = names16[code - eAX_reg + add];
14821           used_prefixes |= (prefixes & PREFIX_DATA);
14822         }
14823       break;
14824     default:
14825       s = INTERNAL_DISASSEMBLER_ERROR;
14826       break;
14827     }
14828   oappend (s);
14829 }
14830
14831 static void
14832 OP_IMREG (int code, int sizeflag)
14833 {
14834   const char *s;
14835
14836   switch (code)
14837     {
14838     case indir_dx_reg:
14839       if (intel_syntax)
14840         s = "dx";
14841       else
14842         s = "(%dx)";
14843       break;
14844     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14845     case sp_reg: case bp_reg: case si_reg: case di_reg:
14846       s = names16[code - ax_reg];
14847       break;
14848     case es_reg: case ss_reg: case cs_reg:
14849     case ds_reg: case fs_reg: case gs_reg:
14850       s = names_seg[code - es_reg];
14851       break;
14852     case al_reg: case ah_reg: case cl_reg: case ch_reg:
14853     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14854       USED_REX (0);
14855       if (rex)
14856         s = names8rex[code - al_reg];
14857       else
14858         s = names8[code - al_reg];
14859       break;
14860     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14861     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14862       USED_REX (REX_W);
14863       if (rex & REX_W)
14864         s = names64[code - eAX_reg];
14865       else
14866         {
14867           if (sizeflag & DFLAG)
14868             s = names32[code - eAX_reg];
14869           else
14870             s = names16[code - eAX_reg];
14871           used_prefixes |= (prefixes & PREFIX_DATA);
14872         }
14873       break;
14874     case z_mode_ax_reg:
14875       if ((rex & REX_W) || (sizeflag & DFLAG))
14876         s = *names32;
14877       else
14878         s = *names16;
14879       if (!(rex & REX_W))
14880         used_prefixes |= (prefixes & PREFIX_DATA);
14881       break;
14882     default:
14883       s = INTERNAL_DISASSEMBLER_ERROR;
14884       break;
14885     }
14886   oappend (s);
14887 }
14888
14889 static void
14890 OP_I (int bytemode, int sizeflag)
14891 {
14892   bfd_signed_vma op;
14893   bfd_signed_vma mask = -1;
14894
14895   switch (bytemode)
14896     {
14897     case b_mode:
14898       FETCH_DATA (the_info, codep + 1);
14899       op = *codep++;
14900       mask = 0xff;
14901       break;
14902     case q_mode:
14903       if (address_mode == mode_64bit)
14904         {
14905           op = get32s ();
14906           break;
14907         }
14908       /* Fall through.  */
14909     case v_mode:
14910       USED_REX (REX_W);
14911       if (rex & REX_W)
14912         op = get32s ();
14913       else
14914         {
14915           if (sizeflag & DFLAG)
14916             {
14917               op = get32 ();
14918               mask = 0xffffffff;
14919             }
14920           else
14921             {
14922               op = get16 ();
14923               mask = 0xfffff;
14924             }
14925           used_prefixes |= (prefixes & PREFIX_DATA);
14926         }
14927       break;
14928     case w_mode:
14929       mask = 0xfffff;
14930       op = get16 ();
14931       break;
14932     case const_1_mode:
14933       if (intel_syntax)
14934         oappend ("1");
14935       return;
14936     default:
14937       oappend (INTERNAL_DISASSEMBLER_ERROR);
14938       return;
14939     }
14940
14941   op &= mask;
14942   scratchbuf[0] = '$';
14943   print_operand_value (scratchbuf + 1, 1, op);
14944   oappend_maybe_intel (scratchbuf);
14945   scratchbuf[0] = '\0';
14946 }
14947
14948 static void
14949 OP_I64 (int bytemode, int sizeflag)
14950 {
14951   bfd_signed_vma op;
14952   bfd_signed_vma mask = -1;
14953
14954   if (address_mode != mode_64bit)
14955     {
14956       OP_I (bytemode, sizeflag);
14957       return;
14958     }
14959
14960   switch (bytemode)
14961     {
14962     case b_mode:
14963       FETCH_DATA (the_info, codep + 1);
14964       op = *codep++;
14965       mask = 0xff;
14966       break;
14967     case v_mode:
14968       USED_REX (REX_W);
14969       if (rex & REX_W)
14970         op = get64 ();
14971       else
14972         {
14973           if (sizeflag & DFLAG)
14974             {
14975               op = get32 ();
14976               mask = 0xffffffff;
14977             }
14978           else
14979             {
14980               op = get16 ();
14981               mask = 0xfffff;
14982             }
14983           used_prefixes |= (prefixes & PREFIX_DATA);
14984         }
14985       break;
14986     case w_mode:
14987       mask = 0xfffff;
14988       op = get16 ();
14989       break;
14990     default:
14991       oappend (INTERNAL_DISASSEMBLER_ERROR);
14992       return;
14993     }
14994
14995   op &= mask;
14996   scratchbuf[0] = '$';
14997   print_operand_value (scratchbuf + 1, 1, op);
14998   oappend_maybe_intel (scratchbuf);
14999   scratchbuf[0] = '\0';
15000 }
15001
15002 static void
15003 OP_sI (int bytemode, int sizeflag)
15004 {
15005   bfd_signed_vma op;
15006
15007   switch (bytemode)
15008     {
15009     case b_mode:
15010     case b_T_mode:
15011       FETCH_DATA (the_info, codep + 1);
15012       op = *codep++;
15013       if ((op & 0x80) != 0)
15014         op -= 0x100;
15015       if (bytemode == b_T_mode)
15016         {
15017           if (address_mode != mode_64bit
15018               || !((sizeflag & DFLAG) || (rex & REX_W)))
15019             {
15020               /* The operand-size prefix is overridden by a REX prefix.  */
15021               if ((sizeflag & DFLAG) || (rex & REX_W))
15022                 op &= 0xffffffff;
15023               else
15024                 op &= 0xffff;
15025           }
15026         }
15027       else
15028         {
15029           if (!(rex & REX_W))
15030             {
15031               if (sizeflag & DFLAG)
15032                 op &= 0xffffffff;
15033               else
15034                 op &= 0xffff;
15035             }
15036         }
15037       break;
15038     case v_mode:
15039       /* The operand-size prefix is overridden by a REX prefix.  */
15040       if ((sizeflag & DFLAG) || (rex & REX_W))
15041         op = get32s ();
15042       else
15043         op = get16 ();
15044       break;
15045     default:
15046       oappend (INTERNAL_DISASSEMBLER_ERROR);
15047       return;
15048     }
15049
15050   scratchbuf[0] = '$';
15051   print_operand_value (scratchbuf + 1, 1, op);
15052   oappend_maybe_intel (scratchbuf);
15053 }
15054
15055 static void
15056 OP_J (int bytemode, int sizeflag)
15057 {
15058   bfd_vma disp;
15059   bfd_vma mask = -1;
15060   bfd_vma segment = 0;
15061
15062   switch (bytemode)
15063     {
15064     case b_mode:
15065       FETCH_DATA (the_info, codep + 1);
15066       disp = *codep++;
15067       if ((disp & 0x80) != 0)
15068         disp -= 0x100;
15069       break;
15070     case v_mode:
15071       USED_REX (REX_W);
15072       if ((sizeflag & DFLAG) || (rex & REX_W))
15073         disp = get32s ();
15074       else
15075         {
15076           disp = get16 ();
15077           if ((disp & 0x8000) != 0)
15078             disp -= 0x10000;
15079           /* In 16bit mode, address is wrapped around at 64k within
15080              the same segment.  Otherwise, a data16 prefix on a jump
15081              instruction means that the pc is masked to 16 bits after
15082              the displacement is added!  */
15083           mask = 0xffff;
15084           if ((prefixes & PREFIX_DATA) == 0)
15085             segment = ((start_pc + codep - start_codep)
15086                        & ~((bfd_vma) 0xffff));
15087         }
15088       if (!(rex & REX_W))
15089         used_prefixes |= (prefixes & PREFIX_DATA);
15090       break;
15091     default:
15092       oappend (INTERNAL_DISASSEMBLER_ERROR);
15093       return;
15094     }
15095   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
15096   set_op (disp, 0);
15097   print_operand_value (scratchbuf, 1, disp);
15098   oappend (scratchbuf);
15099 }
15100
15101 static void
15102 OP_SEG (int bytemode, int sizeflag)
15103 {
15104   if (bytemode == w_mode)
15105     oappend (names_seg[modrm.reg]);
15106   else
15107     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
15108 }
15109
15110 static void
15111 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
15112 {
15113   int seg, offset;
15114
15115   if (sizeflag & DFLAG)
15116     {
15117       offset = get32 ();
15118       seg = get16 ();
15119     }
15120   else
15121     {
15122       offset = get16 ();
15123       seg = get16 ();
15124     }
15125   used_prefixes |= (prefixes & PREFIX_DATA);
15126   if (intel_syntax)
15127     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
15128   else
15129     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
15130   oappend (scratchbuf);
15131 }
15132
15133 static void
15134 OP_OFF (int bytemode, int sizeflag)
15135 {
15136   bfd_vma off;
15137
15138   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
15139     intel_operand_size (bytemode, sizeflag);
15140   append_seg ();
15141
15142   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
15143     off = get32 ();
15144   else
15145     off = get16 ();
15146
15147   if (intel_syntax)
15148     {
15149       if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
15150                         | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
15151         {
15152           oappend (names_seg[ds_reg - es_reg]);
15153           oappend (":");
15154         }
15155     }
15156   print_operand_value (scratchbuf, 1, off);
15157   oappend (scratchbuf);
15158 }
15159
15160 static void
15161 OP_OFF64 (int bytemode, int sizeflag)
15162 {
15163   bfd_vma off;
15164
15165   if (address_mode != mode_64bit
15166       || (prefixes & PREFIX_ADDR))
15167     {
15168       OP_OFF (bytemode, sizeflag);
15169       return;
15170     }
15171
15172   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
15173     intel_operand_size (bytemode, sizeflag);
15174   append_seg ();
15175
15176   off = get64 ();
15177
15178   if (intel_syntax)
15179     {
15180       if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
15181                         | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
15182         {
15183           oappend (names_seg[ds_reg - es_reg]);
15184           oappend (":");
15185         }
15186     }
15187   print_operand_value (scratchbuf, 1, off);
15188   oappend (scratchbuf);
15189 }
15190
15191 static void
15192 ptr_reg (int code, int sizeflag)
15193 {
15194   const char *s;
15195
15196   *obufp++ = open_char;
15197   used_prefixes |= (prefixes & PREFIX_ADDR);
15198   if (address_mode == mode_64bit)
15199     {
15200       if (!(sizeflag & AFLAG))
15201         s = names32[code - eAX_reg];
15202       else
15203         s = names64[code - eAX_reg];
15204     }
15205   else if (sizeflag & AFLAG)
15206     s = names32[code - eAX_reg];
15207   else
15208     s = names16[code - eAX_reg];
15209   oappend (s);
15210   *obufp++ = close_char;
15211   *obufp = 0;
15212 }
15213
15214 static void
15215 OP_ESreg (int code, int sizeflag)
15216 {
15217   if (intel_syntax)
15218     {
15219       switch (codep[-1])
15220         {
15221         case 0x6d:      /* insw/insl */
15222           intel_operand_size (z_mode, sizeflag);
15223           break;
15224         case 0xa5:      /* movsw/movsl/movsq */
15225         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15226         case 0xab:      /* stosw/stosl */
15227         case 0xaf:      /* scasw/scasl */
15228           intel_operand_size (v_mode, sizeflag);
15229           break;
15230         default:
15231           intel_operand_size (b_mode, sizeflag);
15232         }
15233     }
15234   oappend_maybe_intel ("%es:");
15235   ptr_reg (code, sizeflag);
15236 }
15237
15238 static void
15239 OP_DSreg (int code, int sizeflag)
15240 {
15241   if (intel_syntax)
15242     {
15243       switch (codep[-1])
15244         {
15245         case 0x6f:      /* outsw/outsl */
15246           intel_operand_size (z_mode, sizeflag);
15247           break;
15248         case 0xa5:      /* movsw/movsl/movsq */
15249         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15250         case 0xad:      /* lodsw/lodsl/lodsq */
15251           intel_operand_size (v_mode, sizeflag);
15252           break;
15253         default:
15254           intel_operand_size (b_mode, sizeflag);
15255         }
15256     }
15257   if ((prefixes
15258        & (PREFIX_CS
15259           | PREFIX_DS
15260           | PREFIX_SS
15261           | PREFIX_ES
15262           | PREFIX_FS
15263           | PREFIX_GS)) == 0)
15264     prefixes |= PREFIX_DS;
15265   append_seg ();
15266   ptr_reg (code, sizeflag);
15267 }
15268
15269 static void
15270 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15271 {
15272   int add;
15273   if (rex & REX_R)
15274     {
15275       USED_REX (REX_R);
15276       add = 8;
15277     }
15278   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
15279     {
15280       all_prefixes[last_lock_prefix] = 0;
15281       used_prefixes |= PREFIX_LOCK;
15282       add = 8;
15283     }
15284   else
15285     add = 0;
15286   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
15287   oappend_maybe_intel (scratchbuf);
15288 }
15289
15290 static void
15291 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15292 {
15293   int add;
15294   USED_REX (REX_R);
15295   if (rex & REX_R)
15296     add = 8;
15297   else
15298     add = 0;
15299   if (intel_syntax)
15300     sprintf (scratchbuf, "db%d", modrm.reg + add);
15301   else
15302     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
15303   oappend (scratchbuf);
15304 }
15305
15306 static void
15307 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15308 {
15309   sprintf (scratchbuf, "%%tr%d", modrm.reg);
15310   oappend_maybe_intel (scratchbuf);
15311 }
15312
15313 static void
15314 OP_R (int bytemode, int sizeflag)
15315 {
15316   if (modrm.mod == 3)
15317     OP_E (bytemode, sizeflag);
15318   else
15319     BadOp ();
15320 }
15321
15322 static void
15323 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15324 {
15325   int reg = modrm.reg;
15326   const char **names;
15327
15328   used_prefixes |= (prefixes & PREFIX_DATA);
15329   if (prefixes & PREFIX_DATA)
15330     {
15331       names = names_xmm;
15332       USED_REX (REX_R);
15333       if (rex & REX_R)
15334         reg += 8;
15335     }
15336   else
15337     names = names_mm;
15338   oappend (names[reg]);
15339 }
15340
15341 static void
15342 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15343 {
15344   int reg = modrm.reg;
15345   const char **names;
15346
15347   USED_REX (REX_R);
15348   if (rex & REX_R)
15349     reg += 8;
15350   if (vex.evex)
15351     {
15352       if (!vex.r)
15353         reg += 16;
15354     }
15355
15356   if (need_vex
15357       && bytemode != xmm_mode
15358       && bytemode != xmmq_mode
15359       && bytemode != evex_half_bcst_xmmq_mode
15360       && bytemode != ymm_mode
15361       && bytemode != scalar_mode)
15362     {
15363       switch (vex.length)
15364         {
15365         case 128:
15366           names = names_xmm;
15367           break;
15368         case 256:
15369           if (vex.w || bytemode != vex_vsib_q_w_dq_mode)
15370             names = names_ymm;
15371           else
15372             names = names_xmm;
15373           break;
15374         case 512:
15375           names = names_zmm;
15376           break;
15377         default:
15378           abort ();
15379         }
15380     }
15381   else if (bytemode == xmmq_mode
15382            || bytemode == evex_half_bcst_xmmq_mode)
15383     {
15384       switch (vex.length)
15385         {
15386         case 128:
15387         case 256:
15388           names = names_xmm;
15389           break;
15390         case 512:
15391           names = names_ymm;
15392           break;
15393         default:
15394           abort ();
15395         }
15396     }
15397   else if (bytemode == ymm_mode)
15398     names = names_ymm;
15399   else
15400     names = names_xmm;
15401   oappend (names[reg]);
15402 }
15403
15404 static void
15405 OP_EM (int bytemode, int sizeflag)
15406 {
15407   int reg;
15408   const char **names;
15409
15410   if (modrm.mod != 3)
15411     {
15412       if (intel_syntax
15413           && (bytemode == v_mode || bytemode == v_swap_mode))
15414         {
15415           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15416           used_prefixes |= (prefixes & PREFIX_DATA);
15417         }
15418       OP_E (bytemode, sizeflag);
15419       return;
15420     }
15421
15422   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
15423     swap_operand ();
15424
15425   /* Skip mod/rm byte.  */
15426   MODRM_CHECK;
15427   codep++;
15428   used_prefixes |= (prefixes & PREFIX_DATA);
15429   reg = modrm.rm;
15430   if (prefixes & PREFIX_DATA)
15431     {
15432       names = names_xmm;
15433       USED_REX (REX_B);
15434       if (rex & REX_B)
15435         reg += 8;
15436     }
15437   else
15438     names = names_mm;
15439   oappend (names[reg]);
15440 }
15441
15442 /* cvt* are the only instructions in sse2 which have
15443    both SSE and MMX operands and also have 0x66 prefix
15444    in their opcode. 0x66 was originally used to differentiate
15445    between SSE and MMX instruction(operands). So we have to handle the
15446    cvt* separately using OP_EMC and OP_MXC */
15447 static void
15448 OP_EMC (int bytemode, int sizeflag)
15449 {
15450   if (modrm.mod != 3)
15451     {
15452       if (intel_syntax && bytemode == v_mode)
15453         {
15454           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15455           used_prefixes |= (prefixes & PREFIX_DATA);
15456         }
15457       OP_E (bytemode, sizeflag);
15458       return;
15459     }
15460
15461   /* Skip mod/rm byte.  */
15462   MODRM_CHECK;
15463   codep++;
15464   used_prefixes |= (prefixes & PREFIX_DATA);
15465   oappend (names_mm[modrm.rm]);
15466 }
15467
15468 static void
15469 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15470 {
15471   used_prefixes |= (prefixes & PREFIX_DATA);
15472   oappend (names_mm[modrm.reg]);
15473 }
15474
15475 static void
15476 OP_EX (int bytemode, int sizeflag)
15477 {
15478   int reg;
15479   const char **names;
15480
15481   /* Skip mod/rm byte.  */
15482   MODRM_CHECK;
15483   codep++;
15484
15485   if (modrm.mod != 3)
15486     {
15487       OP_E_memory (bytemode, sizeflag);
15488       return;
15489     }
15490
15491   reg = modrm.rm;
15492   USED_REX (REX_B);
15493   if (rex & REX_B)
15494     reg += 8;
15495   if (vex.evex)
15496     {
15497       USED_REX (REX_X);
15498       if ((rex & REX_X))
15499         reg += 16;
15500     }
15501
15502   if ((sizeflag & SUFFIX_ALWAYS)
15503       && (bytemode == x_swap_mode
15504           || bytemode == d_swap_mode
15505           || bytemode == d_scalar_swap_mode
15506           || bytemode == q_swap_mode
15507           || bytemode == q_scalar_swap_mode))
15508     swap_operand ();
15509
15510   if (need_vex
15511       && bytemode != xmm_mode
15512       && bytemode != xmmdw_mode
15513       && bytemode != xmmqd_mode
15514       && bytemode != xmm_mb_mode
15515       && bytemode != xmm_mw_mode
15516       && bytemode != xmm_md_mode
15517       && bytemode != xmm_mq_mode
15518       && bytemode != xmm_mdq_mode
15519       && bytemode != xmmq_mode
15520       && bytemode != evex_half_bcst_xmmq_mode
15521       && bytemode != ymm_mode
15522       && bytemode != d_scalar_mode
15523       && bytemode != d_scalar_swap_mode
15524       && bytemode != q_scalar_mode
15525       && bytemode != q_scalar_swap_mode
15526       && bytemode != vex_scalar_w_dq_mode)
15527     {
15528       switch (vex.length)
15529         {
15530         case 128:
15531           names = names_xmm;
15532           break;
15533         case 256:
15534           names = names_ymm;
15535           break;
15536         case 512:
15537           names = names_zmm;
15538           break;
15539         default:
15540           abort ();
15541         }
15542     }
15543   else if (bytemode == xmmq_mode
15544            || bytemode == evex_half_bcst_xmmq_mode)
15545     {
15546       switch (vex.length)
15547         {
15548         case 128:
15549         case 256:
15550           names = names_xmm;
15551           break;
15552         case 512:
15553           names = names_ymm;
15554           break;
15555         default:
15556           abort ();
15557         }
15558     }
15559   else if (bytemode == ymm_mode)
15560     names = names_ymm;
15561   else
15562     names = names_xmm;
15563   oappend (names[reg]);
15564 }
15565
15566 static void
15567 OP_MS (int bytemode, int sizeflag)
15568 {
15569   if (modrm.mod == 3)
15570     OP_EM (bytemode, sizeflag);
15571   else
15572     BadOp ();
15573 }
15574
15575 static void
15576 OP_XS (int bytemode, int sizeflag)
15577 {
15578   if (modrm.mod == 3)
15579     OP_EX (bytemode, sizeflag);
15580   else
15581     BadOp ();
15582 }
15583
15584 static void
15585 OP_M (int bytemode, int sizeflag)
15586 {
15587   if (modrm.mod == 3)
15588     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
15589     BadOp ();
15590   else
15591     OP_E (bytemode, sizeflag);
15592 }
15593
15594 static void
15595 OP_0f07 (int bytemode, int sizeflag)
15596 {
15597   if (modrm.mod != 3 || modrm.rm != 0)
15598     BadOp ();
15599   else
15600     OP_E (bytemode, sizeflag);
15601 }
15602
15603 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
15604    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
15605
15606 static void
15607 NOP_Fixup1 (int bytemode, int sizeflag)
15608 {
15609   if ((prefixes & PREFIX_DATA) != 0
15610       || (rex != 0
15611           && rex != 0x48
15612           && address_mode == mode_64bit))
15613     OP_REG (bytemode, sizeflag);
15614   else
15615     strcpy (obuf, "nop");
15616 }
15617
15618 static void
15619 NOP_Fixup2 (int bytemode, int sizeflag)
15620 {
15621   if ((prefixes & PREFIX_DATA) != 0
15622       || (rex != 0
15623           && rex != 0x48
15624           && address_mode == mode_64bit))
15625     OP_IMREG (bytemode, sizeflag);
15626 }
15627
15628 static const char *const Suffix3DNow[] = {
15629 /* 00 */        NULL,           NULL,           NULL,           NULL,
15630 /* 04 */        NULL,           NULL,           NULL,           NULL,
15631 /* 08 */        NULL,           NULL,           NULL,           NULL,
15632 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
15633 /* 10 */        NULL,           NULL,           NULL,           NULL,
15634 /* 14 */        NULL,           NULL,           NULL,           NULL,
15635 /* 18 */        NULL,           NULL,           NULL,           NULL,
15636 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
15637 /* 20 */        NULL,           NULL,           NULL,           NULL,
15638 /* 24 */        NULL,           NULL,           NULL,           NULL,
15639 /* 28 */        NULL,           NULL,           NULL,           NULL,
15640 /* 2C */        NULL,           NULL,           NULL,           NULL,
15641 /* 30 */        NULL,           NULL,           NULL,           NULL,
15642 /* 34 */        NULL,           NULL,           NULL,           NULL,
15643 /* 38 */        NULL,           NULL,           NULL,           NULL,
15644 /* 3C */        NULL,           NULL,           NULL,           NULL,
15645 /* 40 */        NULL,           NULL,           NULL,           NULL,
15646 /* 44 */        NULL,           NULL,           NULL,           NULL,
15647 /* 48 */        NULL,           NULL,           NULL,           NULL,
15648 /* 4C */        NULL,           NULL,           NULL,           NULL,
15649 /* 50 */        NULL,           NULL,           NULL,           NULL,
15650 /* 54 */        NULL,           NULL,           NULL,           NULL,
15651 /* 58 */        NULL,           NULL,           NULL,           NULL,
15652 /* 5C */        NULL,           NULL,           NULL,           NULL,
15653 /* 60 */        NULL,           NULL,           NULL,           NULL,
15654 /* 64 */        NULL,           NULL,           NULL,           NULL,
15655 /* 68 */        NULL,           NULL,           NULL,           NULL,
15656 /* 6C */        NULL,           NULL,           NULL,           NULL,
15657 /* 70 */        NULL,           NULL,           NULL,           NULL,
15658 /* 74 */        NULL,           NULL,           NULL,           NULL,
15659 /* 78 */        NULL,           NULL,           NULL,           NULL,
15660 /* 7C */        NULL,           NULL,           NULL,           NULL,
15661 /* 80 */        NULL,           NULL,           NULL,           NULL,
15662 /* 84 */        NULL,           NULL,           NULL,           NULL,
15663 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
15664 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
15665 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
15666 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
15667 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
15668 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
15669 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
15670 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
15671 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
15672 /* AC */        NULL,           NULL,           "pfacc",        NULL,
15673 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
15674 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
15675 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
15676 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
15677 /* C0 */        NULL,           NULL,           NULL,           NULL,
15678 /* C4 */        NULL,           NULL,           NULL,           NULL,
15679 /* C8 */        NULL,           NULL,           NULL,           NULL,
15680 /* CC */        NULL,           NULL,           NULL,           NULL,
15681 /* D0 */        NULL,           NULL,           NULL,           NULL,
15682 /* D4 */        NULL,           NULL,           NULL,           NULL,
15683 /* D8 */        NULL,           NULL,           NULL,           NULL,
15684 /* DC */        NULL,           NULL,           NULL,           NULL,
15685 /* E0 */        NULL,           NULL,           NULL,           NULL,
15686 /* E4 */        NULL,           NULL,           NULL,           NULL,
15687 /* E8 */        NULL,           NULL,           NULL,           NULL,
15688 /* EC */        NULL,           NULL,           NULL,           NULL,
15689 /* F0 */        NULL,           NULL,           NULL,           NULL,
15690 /* F4 */        NULL,           NULL,           NULL,           NULL,
15691 /* F8 */        NULL,           NULL,           NULL,           NULL,
15692 /* FC */        NULL,           NULL,           NULL,           NULL,
15693 };
15694
15695 static void
15696 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15697 {
15698   const char *mnemonic;
15699
15700   FETCH_DATA (the_info, codep + 1);
15701   /* AMD 3DNow! instructions are specified by an opcode suffix in the
15702      place where an 8-bit immediate would normally go.  ie. the last
15703      byte of the instruction.  */
15704   obufp = mnemonicendp;
15705   mnemonic = Suffix3DNow[*codep++ & 0xff];
15706   if (mnemonic)
15707     oappend (mnemonic);
15708   else
15709     {
15710       /* Since a variable sized modrm/sib chunk is between the start
15711          of the opcode (0x0f0f) and the opcode suffix, we need to do
15712          all the modrm processing first, and don't know until now that
15713          we have a bad opcode.  This necessitates some cleaning up.  */
15714       op_out[0][0] = '\0';
15715       op_out[1][0] = '\0';
15716       BadOp ();
15717     }
15718   mnemonicendp = obufp;
15719 }
15720
15721 static struct op simd_cmp_op[] =
15722 {
15723   { STRING_COMMA_LEN ("eq") },
15724   { STRING_COMMA_LEN ("lt") },
15725   { STRING_COMMA_LEN ("le") },
15726   { STRING_COMMA_LEN ("unord") },
15727   { STRING_COMMA_LEN ("neq") },
15728   { STRING_COMMA_LEN ("nlt") },
15729   { STRING_COMMA_LEN ("nle") },
15730   { STRING_COMMA_LEN ("ord") }
15731 };
15732
15733 static void
15734 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15735 {
15736   unsigned int cmp_type;
15737
15738   FETCH_DATA (the_info, codep + 1);
15739   cmp_type = *codep++ & 0xff;
15740   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
15741     {
15742       char suffix [3];
15743       char *p = mnemonicendp - 2;
15744       suffix[0] = p[0];
15745       suffix[1] = p[1];
15746       suffix[2] = '\0';
15747       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
15748       mnemonicendp += simd_cmp_op[cmp_type].len;
15749     }
15750   else
15751     {
15752       /* We have a reserved extension byte.  Output it directly.  */
15753       scratchbuf[0] = '$';
15754       print_operand_value (scratchbuf + 1, 1, cmp_type);
15755       oappend_maybe_intel (scratchbuf);
15756       scratchbuf[0] = '\0';
15757     }
15758 }
15759
15760 static void
15761 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
15762           int sizeflag ATTRIBUTE_UNUSED)
15763 {
15764   /* mwait %eax,%ecx  */
15765   if (!intel_syntax)
15766     {
15767       const char **names = (address_mode == mode_64bit
15768                             ? names64 : names32);
15769       strcpy (op_out[0], names[0]);
15770       strcpy (op_out[1], names[1]);
15771       two_source_ops = 1;
15772     }
15773   /* Skip mod/rm byte.  */
15774   MODRM_CHECK;
15775   codep++;
15776 }
15777
15778 static void
15779 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
15780             int sizeflag ATTRIBUTE_UNUSED)
15781 {
15782   /* monitor %eax,%ecx,%edx"  */
15783   if (!intel_syntax)
15784     {
15785       const char **op1_names;
15786       const char **names = (address_mode == mode_64bit
15787                             ? names64 : names32);
15788
15789       if (!(prefixes & PREFIX_ADDR))
15790         op1_names = (address_mode == mode_16bit
15791                      ? names16 : names);
15792       else
15793         {
15794           /* Remove "addr16/addr32".  */
15795           all_prefixes[last_addr_prefix] = 0;
15796           op1_names = (address_mode != mode_32bit
15797                        ? names32 : names16);
15798           used_prefixes |= PREFIX_ADDR;
15799         }
15800       strcpy (op_out[0], op1_names[0]);
15801       strcpy (op_out[1], names[1]);
15802       strcpy (op_out[2], names[2]);
15803       two_source_ops = 1;
15804     }
15805   /* Skip mod/rm byte.  */
15806   MODRM_CHECK;
15807   codep++;
15808 }
15809
15810 static void
15811 BadOp (void)
15812 {
15813   /* Throw away prefixes and 1st. opcode byte.  */
15814   codep = insn_codep + 1;
15815   oappend ("(bad)");
15816 }
15817
15818 static void
15819 REP_Fixup (int bytemode, int sizeflag)
15820 {
15821   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
15822      lods and stos.  */
15823   if (prefixes & PREFIX_REPZ)
15824     all_prefixes[last_repz_prefix] = REP_PREFIX;
15825
15826   switch (bytemode)
15827     {
15828     case al_reg:
15829     case eAX_reg:
15830     case indir_dx_reg:
15831       OP_IMREG (bytemode, sizeflag);
15832       break;
15833     case eDI_reg:
15834       OP_ESreg (bytemode, sizeflag);
15835       break;
15836     case eSI_reg:
15837       OP_DSreg (bytemode, sizeflag);
15838       break;
15839     default:
15840       abort ();
15841       break;
15842     }
15843 }
15844
15845 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
15846    "bnd".  */
15847
15848 static void
15849 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15850 {
15851   if (prefixes & PREFIX_REPNZ)
15852     all_prefixes[last_repnz_prefix] = BND_PREFIX;
15853 }
15854
15855 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
15856    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
15857  */
15858
15859 static void
15860 HLE_Fixup1 (int bytemode, int sizeflag)
15861 {
15862   if (modrm.mod != 3
15863       && (prefixes & PREFIX_LOCK) != 0)
15864     {
15865       if (prefixes & PREFIX_REPZ)
15866         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15867       if (prefixes & PREFIX_REPNZ)
15868         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15869     }
15870
15871   OP_E (bytemode, sizeflag);
15872 }
15873
15874 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
15875    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
15876  */
15877
15878 static void
15879 HLE_Fixup2 (int bytemode, int sizeflag)
15880 {
15881   if (modrm.mod != 3)
15882     {
15883       if (prefixes & PREFIX_REPZ)
15884         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15885       if (prefixes & PREFIX_REPNZ)
15886         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15887     }
15888
15889   OP_E (bytemode, sizeflag);
15890 }
15891
15892 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
15893    "xrelease" for memory operand.  No check for LOCK prefix.   */
15894
15895 static void
15896 HLE_Fixup3 (int bytemode, int sizeflag)
15897 {
15898   if (modrm.mod != 3
15899       && last_repz_prefix > last_repnz_prefix
15900       && (prefixes & PREFIX_REPZ) != 0)
15901     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15902
15903   OP_E (bytemode, sizeflag);
15904 }
15905
15906 static void
15907 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
15908 {
15909   USED_REX (REX_W);
15910   if (rex & REX_W)
15911     {
15912       /* Change cmpxchg8b to cmpxchg16b.  */
15913       char *p = mnemonicendp - 2;
15914       mnemonicendp = stpcpy (p, "16b");
15915       bytemode = o_mode;
15916     }
15917   else if ((prefixes & PREFIX_LOCK) != 0)
15918     {
15919       if (prefixes & PREFIX_REPZ)
15920         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15921       if (prefixes & PREFIX_REPNZ)
15922         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15923     }
15924
15925   OP_M (bytemode, sizeflag);
15926 }
15927
15928 static void
15929 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
15930 {
15931   const char **names;
15932
15933   if (need_vex)
15934     {
15935       switch (vex.length)
15936         {
15937         case 128:
15938           names = names_xmm;
15939           break;
15940         case 256:
15941           names = names_ymm;
15942           break;
15943         default:
15944           abort ();
15945         }
15946     }
15947   else
15948     names = names_xmm;
15949   oappend (names[reg]);
15950 }
15951
15952 static void
15953 CRC32_Fixup (int bytemode, int sizeflag)
15954 {
15955   /* Add proper suffix to "crc32".  */
15956   char *p = mnemonicendp;
15957
15958   switch (bytemode)
15959     {
15960     case b_mode:
15961       if (intel_syntax)
15962         goto skip;
15963
15964       *p++ = 'b';
15965       break;
15966     case v_mode:
15967       if (intel_syntax)
15968         goto skip;
15969
15970       USED_REX (REX_W);
15971       if (rex & REX_W)
15972         *p++ = 'q';
15973       else
15974         {
15975           if (sizeflag & DFLAG)
15976             *p++ = 'l';
15977           else
15978             *p++ = 'w';
15979           used_prefixes |= (prefixes & PREFIX_DATA);
15980         }
15981       break;
15982     default:
15983       oappend (INTERNAL_DISASSEMBLER_ERROR);
15984       break;
15985     }
15986   mnemonicendp = p;
15987   *p = '\0';
15988
15989 skip:
15990   if (modrm.mod == 3)
15991     {
15992       int add;
15993
15994       /* Skip mod/rm byte.  */
15995       MODRM_CHECK;
15996       codep++;
15997
15998       USED_REX (REX_B);
15999       add = (rex & REX_B) ? 8 : 0;
16000       if (bytemode == b_mode)
16001         {
16002           USED_REX (0);
16003           if (rex)
16004             oappend (names8rex[modrm.rm + add]);
16005           else
16006             oappend (names8[modrm.rm + add]);
16007         }
16008       else
16009         {
16010           USED_REX (REX_W);
16011           if (rex & REX_W)
16012             oappend (names64[modrm.rm + add]);
16013           else if ((prefixes & PREFIX_DATA))
16014             oappend (names16[modrm.rm + add]);
16015           else
16016             oappend (names32[modrm.rm + add]);
16017         }
16018     }
16019   else
16020     OP_E (bytemode, sizeflag);
16021 }
16022
16023 static void
16024 FXSAVE_Fixup (int bytemode, int sizeflag)
16025 {
16026   /* Add proper suffix to "fxsave" and "fxrstor".  */
16027   USED_REX (REX_W);
16028   if (rex & REX_W)
16029     {
16030       char *p = mnemonicendp;
16031       *p++ = '6';
16032       *p++ = '4';
16033       *p = '\0';
16034       mnemonicendp = p;
16035     }
16036   OP_M (bytemode, sizeflag);
16037 }
16038
16039 /* Display the destination register operand for instructions with
16040    VEX. */
16041
16042 static void
16043 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16044 {
16045   int reg;
16046   const char **names;
16047
16048   if (!need_vex)
16049     abort ();
16050
16051   if (!need_vex_reg)
16052     return;
16053
16054   reg = vex.register_specifier;
16055   if (vex.evex)
16056     {
16057       if (!vex.v)
16058         reg += 16;
16059     }
16060
16061   if (bytemode == vex_scalar_mode)
16062     {
16063       oappend (names_xmm[reg]);
16064       return;
16065     }
16066
16067   switch (vex.length)
16068     {
16069     case 128:
16070       switch (bytemode)
16071         {
16072         case vex_mode:
16073         case vex128_mode:
16074         case vex_vsib_q_w_dq_mode:
16075           names = names_xmm;
16076           break;
16077         case dq_mode:
16078           if (vex.w)
16079             names = names64;
16080           else
16081             names = names32;
16082           break;
16083         case mask_mode:
16084           names = names_mask;
16085           break;
16086         default:
16087           abort ();
16088           return;
16089         }
16090       break;
16091     case 256:
16092       switch (bytemode)
16093         {
16094         case vex_mode:
16095         case vex256_mode:
16096           names = names_ymm;
16097           break;
16098         case vex_vsib_q_w_dq_mode:
16099           names = vex.w ? names_ymm : names_xmm;
16100           break;
16101         case mask_mode:
16102           names = names_mask;
16103           break;
16104         default:
16105           abort ();
16106           return;
16107         }
16108       break;
16109     case 512:
16110       names = names_zmm;
16111       break;
16112     default:
16113       abort ();
16114       break;
16115     }
16116   oappend (names[reg]);
16117 }
16118
16119 /* Get the VEX immediate byte without moving codep.  */
16120
16121 static unsigned char
16122 get_vex_imm8 (int sizeflag, int opnum)
16123 {
16124   int bytes_before_imm = 0;
16125
16126   if (modrm.mod != 3)
16127     {
16128       /* There are SIB/displacement bytes.  */
16129       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
16130         {
16131           /* 32/64 bit address mode */
16132           int base = modrm.rm;
16133
16134           /* Check SIB byte.  */
16135           if (base == 4)
16136             {
16137               FETCH_DATA (the_info, codep + 1);
16138               base = *codep & 7;
16139               /* When decoding the third source, don't increase
16140                  bytes_before_imm as this has already been incremented
16141                  by one in OP_E_memory while decoding the second
16142                  source operand.  */
16143               if (opnum == 0)
16144                 bytes_before_imm++;
16145             }
16146
16147           /* Don't increase bytes_before_imm when decoding the third source,
16148              it has already been incremented by OP_E_memory while decoding
16149              the second source operand.  */
16150           if (opnum == 0)
16151             {
16152               switch (modrm.mod)
16153                 {
16154                   case 0:
16155                     /* When modrm.rm == 5 or modrm.rm == 4 and base in
16156                        SIB == 5, there is a 4 byte displacement.  */
16157                     if (base != 5)
16158                       /* No displacement. */
16159                       break;
16160                   case 2:
16161                     /* 4 byte displacement.  */
16162                     bytes_before_imm += 4;
16163                     break;
16164                   case 1:
16165                     /* 1 byte displacement.  */
16166                     bytes_before_imm++;
16167                     break;
16168                 }
16169             }
16170         }
16171       else
16172         {
16173           /* 16 bit address mode */
16174           /* Don't increase bytes_before_imm when decoding the third source,
16175              it has already been incremented by OP_E_memory while decoding
16176              the second source operand.  */
16177           if (opnum == 0)
16178             {
16179               switch (modrm.mod)
16180                 {
16181                 case 0:
16182                   /* When modrm.rm == 6, there is a 2 byte displacement.  */
16183                   if (modrm.rm != 6)
16184                     /* No displacement. */
16185                     break;
16186                 case 2:
16187                   /* 2 byte displacement.  */
16188                   bytes_before_imm += 2;
16189                   break;
16190                 case 1:
16191                   /* 1 byte displacement: when decoding the third source,
16192                      don't increase bytes_before_imm as this has already
16193                      been incremented by one in OP_E_memory while decoding
16194                      the second source operand.  */
16195                   if (opnum == 0)
16196                     bytes_before_imm++;
16197
16198                   break;
16199                 }
16200             }
16201         }
16202     }
16203
16204   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
16205   return codep [bytes_before_imm];
16206 }
16207
16208 static void
16209 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
16210 {
16211   const char **names;
16212
16213   if (reg == -1 && modrm.mod != 3)
16214     {
16215       OP_E_memory (bytemode, sizeflag);
16216       return;
16217     }
16218   else
16219     {
16220       if (reg == -1)
16221         {
16222           reg = modrm.rm;
16223           USED_REX (REX_B);
16224           if (rex & REX_B)
16225             reg += 8;
16226         }
16227       else if (reg > 7 && address_mode != mode_64bit)
16228         BadOp ();
16229     }
16230
16231   switch (vex.length)
16232     {
16233     case 128:
16234       names = names_xmm;
16235       break;
16236     case 256:
16237       names = names_ymm;
16238       break;
16239     default:
16240       abort ();
16241     }
16242   oappend (names[reg]);
16243 }
16244
16245 static void
16246 OP_EX_VexImmW (int bytemode, int sizeflag)
16247 {
16248   int reg = -1;
16249   static unsigned char vex_imm8;
16250
16251   if (vex_w_done == 0)
16252     {
16253       vex_w_done = 1;
16254
16255       /* Skip mod/rm byte.  */
16256       MODRM_CHECK;
16257       codep++;
16258
16259       vex_imm8 = get_vex_imm8 (sizeflag, 0);
16260
16261       if (vex.w)
16262           reg = vex_imm8 >> 4;
16263
16264       OP_EX_VexReg (bytemode, sizeflag, reg);
16265     }
16266   else if (vex_w_done == 1)
16267     {
16268       vex_w_done = 2;
16269
16270       if (!vex.w)
16271           reg = vex_imm8 >> 4;
16272
16273       OP_EX_VexReg (bytemode, sizeflag, reg);
16274     }
16275   else
16276     {
16277       /* Output the imm8 directly.  */
16278       scratchbuf[0] = '$';
16279       print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
16280       oappend_maybe_intel (scratchbuf);
16281       scratchbuf[0] = '\0';
16282       codep++;
16283     }
16284 }
16285
16286 static void
16287 OP_Vex_2src (int bytemode, int sizeflag)
16288 {
16289   if (modrm.mod == 3)
16290     {
16291       int reg = modrm.rm;
16292       USED_REX (REX_B);
16293       if (rex & REX_B)
16294         reg += 8;
16295       oappend (names_xmm[reg]);
16296     }
16297   else
16298     {
16299       if (intel_syntax
16300           && (bytemode == v_mode || bytemode == v_swap_mode))
16301         {
16302           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16303           used_prefixes |= (prefixes & PREFIX_DATA);
16304         }
16305       OP_E (bytemode, sizeflag);
16306     }
16307 }
16308
16309 static void
16310 OP_Vex_2src_1 (int bytemode, int sizeflag)
16311 {
16312   if (modrm.mod == 3)
16313     {
16314       /* Skip mod/rm byte.   */
16315       MODRM_CHECK;
16316       codep++;
16317     }
16318
16319   if (vex.w)
16320     oappend (names_xmm[vex.register_specifier]);
16321   else
16322     OP_Vex_2src (bytemode, sizeflag);
16323 }
16324
16325 static void
16326 OP_Vex_2src_2 (int bytemode, int sizeflag)
16327 {
16328   if (vex.w)
16329     OP_Vex_2src (bytemode, sizeflag);
16330   else
16331     oappend (names_xmm[vex.register_specifier]);
16332 }
16333
16334 static void
16335 OP_EX_VexW (int bytemode, int sizeflag)
16336 {
16337   int reg = -1;
16338
16339   if (!vex_w_done)
16340     {
16341       vex_w_done = 1;
16342
16343       /* Skip mod/rm byte.  */
16344       MODRM_CHECK;
16345       codep++;
16346
16347       if (vex.w)
16348         reg = get_vex_imm8 (sizeflag, 0) >> 4;
16349     }
16350   else
16351     {
16352       if (!vex.w)
16353         reg = get_vex_imm8 (sizeflag, 1) >> 4;
16354     }
16355
16356   OP_EX_VexReg (bytemode, sizeflag, reg);
16357 }
16358
16359 static void
16360 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,
16361              int sizeflag ATTRIBUTE_UNUSED)
16362 {
16363   /* Skip the immediate byte and check for invalid bits.  */
16364   FETCH_DATA (the_info, codep + 1);
16365   if (*codep++ & 0xf)
16366     BadOp ();
16367 }
16368
16369 static void
16370 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16371 {
16372   int reg;
16373   const char **names;
16374
16375   FETCH_DATA (the_info, codep + 1);
16376   reg = *codep++;
16377
16378   if (bytemode != x_mode)
16379     abort ();
16380
16381   if (reg & 0xf)
16382       BadOp ();
16383
16384   reg >>= 4;
16385   if (reg > 7 && address_mode != mode_64bit)
16386     BadOp ();
16387
16388   switch (vex.length)
16389     {
16390     case 128:
16391       names = names_xmm;
16392       break;
16393     case 256:
16394       names = names_ymm;
16395       break;
16396     default:
16397       abort ();
16398     }
16399   oappend (names[reg]);
16400 }
16401
16402 static void
16403 OP_XMM_VexW (int bytemode, int sizeflag)
16404 {
16405   /* Turn off the REX.W bit since it is used for swapping operands
16406      now.  */
16407   rex &= ~REX_W;
16408   OP_XMM (bytemode, sizeflag);
16409 }
16410
16411 static void
16412 OP_EX_Vex (int bytemode, int sizeflag)
16413 {
16414   if (modrm.mod != 3)
16415     {
16416       if (vex.register_specifier != 0)
16417         BadOp ();
16418       need_vex_reg = 0;
16419     }
16420   OP_EX (bytemode, sizeflag);
16421 }
16422
16423 static void
16424 OP_XMM_Vex (int bytemode, int sizeflag)
16425 {
16426   if (modrm.mod != 3)
16427     {
16428       if (vex.register_specifier != 0)
16429         BadOp ();
16430       need_vex_reg = 0;
16431     }
16432   OP_XMM (bytemode, sizeflag);
16433 }
16434
16435 static void
16436 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16437 {
16438   switch (vex.length)
16439     {
16440     case 128:
16441       mnemonicendp = stpcpy (obuf, "vzeroupper");
16442       break;
16443     case 256:
16444       mnemonicendp = stpcpy (obuf, "vzeroall");
16445       break;
16446     default:
16447       abort ();
16448     }
16449 }
16450
16451 static struct op vex_cmp_op[] =
16452 {
16453   { STRING_COMMA_LEN ("eq") },
16454   { STRING_COMMA_LEN ("lt") },
16455   { STRING_COMMA_LEN ("le") },
16456   { STRING_COMMA_LEN ("unord") },
16457   { STRING_COMMA_LEN ("neq") },
16458   { STRING_COMMA_LEN ("nlt") },
16459   { STRING_COMMA_LEN ("nle") },
16460   { STRING_COMMA_LEN ("ord") },
16461   { STRING_COMMA_LEN ("eq_uq") },
16462   { STRING_COMMA_LEN ("nge") },
16463   { STRING_COMMA_LEN ("ngt") },
16464   { STRING_COMMA_LEN ("false") },
16465   { STRING_COMMA_LEN ("neq_oq") },
16466   { STRING_COMMA_LEN ("ge") },
16467   { STRING_COMMA_LEN ("gt") },
16468   { STRING_COMMA_LEN ("true") },
16469   { STRING_COMMA_LEN ("eq_os") },
16470   { STRING_COMMA_LEN ("lt_oq") },
16471   { STRING_COMMA_LEN ("le_oq") },
16472   { STRING_COMMA_LEN ("unord_s") },
16473   { STRING_COMMA_LEN ("neq_us") },
16474   { STRING_COMMA_LEN ("nlt_uq") },
16475   { STRING_COMMA_LEN ("nle_uq") },
16476   { STRING_COMMA_LEN ("ord_s") },
16477   { STRING_COMMA_LEN ("eq_us") },
16478   { STRING_COMMA_LEN ("nge_uq") },
16479   { STRING_COMMA_LEN ("ngt_uq") },
16480   { STRING_COMMA_LEN ("false_os") },
16481   { STRING_COMMA_LEN ("neq_os") },
16482   { STRING_COMMA_LEN ("ge_oq") },
16483   { STRING_COMMA_LEN ("gt_oq") },
16484   { STRING_COMMA_LEN ("true_us") },
16485 };
16486
16487 static void
16488 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16489 {
16490   unsigned int cmp_type;
16491
16492   FETCH_DATA (the_info, codep + 1);
16493   cmp_type = *codep++ & 0xff;
16494   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
16495     {
16496       char suffix [3];
16497       char *p = mnemonicendp - 2;
16498       suffix[0] = p[0];
16499       suffix[1] = p[1];
16500       suffix[2] = '\0';
16501       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
16502       mnemonicendp += vex_cmp_op[cmp_type].len;
16503     }
16504   else
16505     {
16506       /* We have a reserved extension byte.  Output it directly.  */
16507       scratchbuf[0] = '$';
16508       print_operand_value (scratchbuf + 1, 1, cmp_type);
16509       oappend_maybe_intel (scratchbuf);
16510       scratchbuf[0] = '\0';
16511     }
16512 }
16513
16514 static void
16515 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
16516              int sizeflag ATTRIBUTE_UNUSED)
16517 {
16518   unsigned int cmp_type;
16519
16520   if (!vex.evex)
16521     abort ();
16522
16523   FETCH_DATA (the_info, codep + 1);
16524   cmp_type = *codep++ & 0xff;
16525   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
16526      If it's the case, print suffix, otherwise - print the immediate.  */
16527   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
16528       && cmp_type != 3
16529       && cmp_type != 7)
16530     {
16531       char suffix [3];
16532       char *p = mnemonicendp - 2;
16533
16534       /* vpcmp* can have both one- and two-lettered suffix.  */
16535       if (p[0] == 'p')
16536         {
16537           p++;
16538           suffix[0] = p[0];
16539           suffix[1] = '\0';
16540         }
16541       else
16542         {
16543           suffix[0] = p[0];
16544           suffix[1] = p[1];
16545           suffix[2] = '\0';
16546         }
16547
16548       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16549       mnemonicendp += simd_cmp_op[cmp_type].len;
16550     }
16551   else
16552     {
16553       /* We have a reserved extension byte.  Output it directly.  */
16554       scratchbuf[0] = '$';
16555       print_operand_value (scratchbuf + 1, 1, cmp_type);
16556       oappend_maybe_intel (scratchbuf);
16557       scratchbuf[0] = '\0';
16558     }
16559 }
16560
16561 static const struct op pclmul_op[] =
16562 {
16563   { STRING_COMMA_LEN ("lql") },
16564   { STRING_COMMA_LEN ("hql") },
16565   { STRING_COMMA_LEN ("lqh") },
16566   { STRING_COMMA_LEN ("hqh") }
16567 };
16568
16569 static void
16570 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
16571               int sizeflag ATTRIBUTE_UNUSED)
16572 {
16573   unsigned int pclmul_type;
16574
16575   FETCH_DATA (the_info, codep + 1);
16576   pclmul_type = *codep++ & 0xff;
16577   switch (pclmul_type)
16578     {
16579     case 0x10:
16580       pclmul_type = 2;
16581       break;
16582     case 0x11:
16583       pclmul_type = 3;
16584       break;
16585     default:
16586       break;
16587     }
16588   if (pclmul_type < ARRAY_SIZE (pclmul_op))
16589     {
16590       char suffix [4];
16591       char *p = mnemonicendp - 3;
16592       suffix[0] = p[0];
16593       suffix[1] = p[1];
16594       suffix[2] = p[2];
16595       suffix[3] = '\0';
16596       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
16597       mnemonicendp += pclmul_op[pclmul_type].len;
16598     }
16599   else
16600     {
16601       /* We have a reserved extension byte.  Output it directly.  */
16602       scratchbuf[0] = '$';
16603       print_operand_value (scratchbuf + 1, 1, pclmul_type);
16604       oappend_maybe_intel (scratchbuf);
16605       scratchbuf[0] = '\0';
16606     }
16607 }
16608
16609 static void
16610 MOVBE_Fixup (int bytemode, int sizeflag)
16611 {
16612   /* Add proper suffix to "movbe".  */
16613   char *p = mnemonicendp;
16614
16615   switch (bytemode)
16616     {
16617     case v_mode:
16618       if (intel_syntax)
16619         goto skip;
16620
16621       USED_REX (REX_W);
16622       if (sizeflag & SUFFIX_ALWAYS)
16623         {
16624           if (rex & REX_W)
16625             *p++ = 'q';
16626           else
16627             {
16628               if (sizeflag & DFLAG)
16629                 *p++ = 'l';
16630               else
16631                 *p++ = 'w';
16632               used_prefixes |= (prefixes & PREFIX_DATA);
16633             }
16634         }
16635       break;
16636     default:
16637       oappend (INTERNAL_DISASSEMBLER_ERROR);
16638       break;
16639     }
16640   mnemonicendp = p;
16641   *p = '\0';
16642
16643 skip:
16644   OP_M (bytemode, sizeflag);
16645 }
16646
16647 static void
16648 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16649 {
16650   int reg;
16651   const char **names;
16652
16653   /* Skip mod/rm byte.  */
16654   MODRM_CHECK;
16655   codep++;
16656
16657   if (vex.w)
16658     names = names64;
16659   else
16660     names = names32;
16661
16662   reg = modrm.rm;
16663   USED_REX (REX_B);
16664   if (rex & REX_B)
16665     reg += 8;
16666
16667   oappend (names[reg]);
16668 }
16669
16670 static void
16671 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16672 {
16673   const char **names;
16674
16675   if (vex.w)
16676     names = names64;
16677   else
16678     names = names32;
16679
16680   oappend (names[vex.register_specifier]);
16681 }
16682
16683 static void
16684 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16685 {
16686   if (!vex.evex
16687       || bytemode != mask_mode)
16688     abort ();
16689
16690   USED_REX (REX_R);
16691   if ((rex & REX_R) != 0 || !vex.r)
16692     {
16693       BadOp ();
16694       return;
16695     }
16696
16697   oappend (names_mask [modrm.reg]);
16698 }
16699
16700 static void
16701 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16702 {
16703   if (!vex.evex
16704       || (bytemode != evex_rounding_mode
16705           && bytemode != evex_sae_mode))
16706     abort ();
16707   if (modrm.mod == 3 && vex.b)
16708     switch (bytemode)
16709       {
16710       case evex_rounding_mode:
16711         oappend (names_rounding[vex.ll]);
16712         break;
16713       case evex_sae_mode:
16714         oappend ("{sae}");
16715         break;
16716       default:
16717         break;
16718       }
16719 }