opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2018 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "disassemble.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40
  41 #include <setjmp.h>
  42
  43 static int print_insn (bfd_vma, disassemble_info *);
  44 static void dofloat (int);
  45 static void OP_ST (int, int);
  46 static void OP_STi (int, int);
  47 static int putop (const char *, int);
  48 static void oappend (const char *);
  49 static void append_seg (void);
  50 static void OP_indirE (int, int);
  51 static void print_operand_value (char *, int, bfd_vma);
  52 static void OP_E_register (int, int);
  53 static void OP_E_memory (int, int);
  54 static void print_displacement (char *, bfd_vma);
  55 static void OP_E (int, int);
  56 static void OP_G (int, int);
  57 static bfd_vma get64 (void);
  58 static bfd_signed_vma get32 (void);
  59 static bfd_signed_vma get32s (void);
  60 static int get16 (void);
  61 static void set_op (bfd_vma, int);
  62 static void OP_Skip_MODRM (int, int);
  63 static void OP_REG (int, int);
  64 static void OP_IMREG (int, int);
  65 static void OP_I (int, int);
  66 static void OP_I64 (int, int);
  67 static void OP_sI (int, int);
  68 static void OP_J (int, int);
  69 static void OP_SEG (int, int);
  70 static void OP_DIR (int, int);
  71 static void OP_OFF (int, int);
  72 static void OP_OFF64 (int, int);
  73 static void ptr_reg (int, int);
  74 static void OP_ESreg (int, int);
  75 static void OP_DSreg (int, int);
  76 static void OP_C (int, int);
  77 static void OP_D (int, int);
  78 static void OP_T (int, int);
  79 static void OP_R (int, int);
  80 static void OP_MMX (int, int);
  81 static void OP_XMM (int, int);
  82 static void OP_EM (int, int);
  83 static void OP_EX (int, int);
  84 static void OP_EMC (int,int);
  85 static void OP_MXC (int,int);
  86 static void OP_MS (int, int);
  87 static void OP_XS (int, int);
  88 static void OP_M (int, int);
  89 static void OP_VEX (int, int);
  90 static void OP_EX_Vex (int, int);
  91 static void OP_EX_VexW (int, int);
  92 static void OP_EX_VexImmW (int, int);
  93 static void OP_XMM_Vex (int, int);
  94 static void OP_XMM_VexW (int, int);
  95 static void OP_Rounding (int, int);
  96 static void OP_REG_VexI4 (int, int);
  97 static void PCLMUL_Fixup (int, int);
  98 static void VZERO_Fixup (int, int);
  99 static void VCMP_Fixup (int, int);
 100 static void VPCMP_Fixup (int, int);
 101 static void VPCOM_Fixup (int, int);
 102 static void OP_0f07 (int, int);
 103 static void OP_Monitor (int, int);
 104 static void OP_Mwait (int, int);
 105 static void OP_Mwaitx (int, int);
 106 static void NOP_Fixup1 (int, int);
 107 static void NOP_Fixup2 (int, int);
 108 static void OP_3DNowSuffix (int, int);
 109 static void CMP_Fixup (int, int);
 110 static void BadOp (void);
 111 static void REP_Fixup (int, int);
 112 static void BND_Fixup (int, int);
 113 static void NOTRACK_Fixup (int, int);
 114 static void HLE_Fixup1 (int, int);
 115 static void HLE_Fixup2 (int, int);
 116 static void HLE_Fixup3 (int, int);
 117 static void CMPXCHG8B_Fixup (int, int);
 118 static void XMM_Fixup (int, int);
 119 static void CRC32_Fixup (int, int);
 120 static void FXSAVE_Fixup (int, int);
 121 static void PCMPESTR_Fixup (int, int);
 122 static void OP_LWPCB_E (int, int);
 123 static void OP_LWP_E (int, int);
 124 static void OP_Vex_2src_1 (int, int);
 125 static void OP_Vex_2src_2 (int, int);
 126
 127 static void MOVBE_Fixup (int, int);
 128
 129 static void OP_Mask (int, int);
 130
 131 struct dis_private {
 132   /* Points to first byte not fetched.  */
 133   bfd_byte *max_fetched;
 134   bfd_byte the_buffer[MAX_MNEM_SIZE];
 135   bfd_vma insn_start;
 136   int orig_sizeflag;
 137   OPCODES_SIGJMP_BUF bailout;
 138 };
 139
 140 enum address_mode
 141 {
 142   mode_16bit,
 143   mode_32bit,
 144   mode_64bit
 145 };
 146
 147 enum address_mode address_mode;
 148
 149 /* Flags for the prefixes for the current instruction.  See below.  */
 150 static int prefixes;
 151
 152 /* REX prefix the current instruction.  See below.  */
 153 static int rex;
 154 /* Bits of REX we've already used.  */
 155 static int rex_used;
 156 /* REX bits in original REX prefix ignored.  */
 157 static int rex_ignored;
 158 /* Mark parts used in the REX prefix.  When we are testing for
 159    empty prefix (for 8bit register REX extension), just mask it
 160    out.  Otherwise test for REX bit is excuse for existence of REX
 161    only in case value is nonzero.  */
 162 #define USED_REX(value)                                 \
 163   {                                                     \
 164     if (value)                                          \
 165       {                                                 \
 166         if ((rex & value))                              \
 167           rex_used |= (value) | REX_OPCODE;             \
 168       }                                                 \
 169     else                                                \
 170       rex_used |= REX_OPCODE;                           \
 171   }
 172
 173 /* Flags for prefixes which we somehow handled when printing the
 174    current instruction.  */
 175 static int used_prefixes;
 176
 177 /* Flags stored in PREFIXES.  */
 178 #define PREFIX_REPZ 1
 179 #define PREFIX_REPNZ 2
 180 #define PREFIX_LOCK 4
 181 #define PREFIX_CS 8
 182 #define PREFIX_SS 0x10
 183 #define PREFIX_DS 0x20
 184 #define PREFIX_ES 0x40
 185 #define PREFIX_FS 0x80
 186 #define PREFIX_GS 0x100
 187 #define PREFIX_DATA 0x200
 188 #define PREFIX_ADDR 0x400
 189 #define PREFIX_FWAIT 0x800
 190
 191 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 192    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 193    on error.  */
 194 #define FETCH_DATA(info, addr) \
 195   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 196    ? 1 : fetch_data ((info), (addr)))
 197
 198 static int
 199 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 200 {
 201   int status;
 202   struct dis_private *priv = (struct dis_private *) info->private_data;
 203   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 204
 205   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 206     status = (*info->read_memory_func) (start,
 207                                         priv->max_fetched,
 208                                         addr - priv->max_fetched,
 209                                         info);
 210   else
 211     status = -1;
 212   if (status != 0)
 213     {
 214       /* If we did manage to read at least one byte, then
 215          print_insn_i386 will do something sensible.  Otherwise, print
 216          an error.  We do that here because this is where we know
 217          STATUS.  */
 218       if (priv->max_fetched == priv->the_buffer)
 219         (*info->memory_error_func) (status, start, info);
 220       OPCODES_SIGLONGJMP (priv->bailout, 1);
 221     }
 222   else
 223     priv->max_fetched = addr;
 224   return 1;
 225 }
 226
 227 /* Possible values for prefix requirement.  */
 228 #define PREFIX_IGNORED_SHIFT    16
 229 #define PREFIX_IGNORED_REPZ     (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
 230 #define PREFIX_IGNORED_REPNZ    (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
 231 #define PREFIX_IGNORED_DATA     (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
 232 #define PREFIX_IGNORED_ADDR     (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
 233 #define PREFIX_IGNORED_LOCK     (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
 234
 235 /* Opcode prefixes.  */
 236 #define PREFIX_OPCODE           (PREFIX_REPZ \
 237                                  | PREFIX_REPNZ \
 238                                  | PREFIX_DATA)
 239
 240 /* Prefixes ignored.  */
 241 #define PREFIX_IGNORED          (PREFIX_IGNORED_REPZ \
 242                                  | PREFIX_IGNORED_REPNZ \
 243                                  | PREFIX_IGNORED_DATA)
 244
 245 #define XX { NULL, 0 }
 246 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
 247
 248 #define Eb { OP_E, b_mode }
 249 #define Ebnd { OP_E, bnd_mode }
 250 #define EbS { OP_E, b_swap_mode }
 251 #define EbndS { OP_E, bnd_swap_mode }
 252 #define Ev { OP_E, v_mode }
 253 #define Eva { OP_E, va_mode }
 254 #define Ev_bnd { OP_E, v_bnd_mode }
 255 #define EvS { OP_E, v_swap_mode }
 256 #define Ed { OP_E, d_mode }
 257 #define Edq { OP_E, dq_mode }
 258 #define Edqw { OP_E, dqw_mode }
 259 #define Edqb { OP_E, dqb_mode }
 260 #define Edb { OP_E, db_mode }
 261 #define Edw { OP_E, dw_mode }
 262 #define Edqd { OP_E, dqd_mode }
 263 #define Edqa { OP_E, dqa_mode }
 264 #define Eq { OP_E, q_mode }
 265 #define indirEv { OP_indirE, indir_v_mode }
 266 #define indirEp { OP_indirE, f_mode }
 267 #define stackEv { OP_E, stack_v_mode }
 268 #define Em { OP_E, m_mode }
 269 #define Ew { OP_E, w_mode }
 270 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 271 #define Ma { OP_M, a_mode }
 272 #define Mb { OP_M, b_mode }
 273 #define Md { OP_M, d_mode }
 274 #define Mo { OP_M, o_mode }
 275 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 276 #define Mq { OP_M, q_mode }
 277 #define Mv_bnd { OP_M, v_bndmk_mode }
 278 #define Mx { OP_M, x_mode }
 279 #define Mxmm { OP_M, xmm_mode }
 280 #define Gb { OP_G, b_mode }
 281 #define Gbnd { OP_G, bnd_mode }
 282 #define Gv { OP_G, v_mode }
 283 #define Gd { OP_G, d_mode }
 284 #define Gdq { OP_G, dq_mode }
 285 #define Gm { OP_G, m_mode }
 286 #define Gva { OP_G, va_mode }
 287 #define Gw { OP_G, w_mode }
 288 #define Rd { OP_R, d_mode }
 289 #define Rdq { OP_R, dq_mode }
 290 #define Rm { OP_R, m_mode }
 291 #define Ib { OP_I, b_mode }
 292 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 293 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 294 #define Iv { OP_I, v_mode }
 295 #define sIv { OP_sI, v_mode }
 296 #define Iq { OP_I, q_mode }
 297 #define Iv64 { OP_I64, v_mode }
 298 #define Iw { OP_I, w_mode }
 299 #define I1 { OP_I, const_1_mode }
 300 #define Jb { OP_J, b_mode }
 301 #define Jv { OP_J, v_mode }
 302 #define Cm { OP_C, m_mode }
 303 #define Dm { OP_D, m_mode }
 304 #define Td { OP_T, d_mode }
 305 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 306
 307 #define RMeAX { OP_REG, eAX_reg }
 308 #define RMeBX { OP_REG, eBX_reg }
 309 #define RMeCX { OP_REG, eCX_reg }
 310 #define RMeDX { OP_REG, eDX_reg }
 311 #define RMeSP { OP_REG, eSP_reg }
 312 #define RMeBP { OP_REG, eBP_reg }
 313 #define RMeSI { OP_REG, eSI_reg }
 314 #define RMeDI { OP_REG, eDI_reg }
 315 #define RMrAX { OP_REG, rAX_reg }
 316 #define RMrBX { OP_REG, rBX_reg }
 317 #define RMrCX { OP_REG, rCX_reg }
 318 #define RMrDX { OP_REG, rDX_reg }
 319 #define RMrSP { OP_REG, rSP_reg }
 320 #define RMrBP { OP_REG, rBP_reg }
 321 #define RMrSI { OP_REG, rSI_reg }
 322 #define RMrDI { OP_REG, rDI_reg }
 323 #define RMAL { OP_REG, al_reg }
 324 #define RMCL { OP_REG, cl_reg }
 325 #define RMDL { OP_REG, dl_reg }
 326 #define RMBL { OP_REG, bl_reg }
 327 #define RMAH { OP_REG, ah_reg }
 328 #define RMCH { OP_REG, ch_reg }
 329 #define RMDH { OP_REG, dh_reg }
 330 #define RMBH { OP_REG, bh_reg }
 331 #define RMAX { OP_REG, ax_reg }
 332 #define RMDX { OP_REG, dx_reg }
 333
 334 #define eAX { OP_IMREG, eAX_reg }
 335 #define eBX { OP_IMREG, eBX_reg }
 336 #define eCX { OP_IMREG, eCX_reg }
 337 #define eDX { OP_IMREG, eDX_reg }
 338 #define eSP { OP_IMREG, eSP_reg }
 339 #define eBP { OP_IMREG, eBP_reg }
 340 #define eSI { OP_IMREG, eSI_reg }
 341 #define eDI { OP_IMREG, eDI_reg }
 342 #define AL { OP_IMREG, al_reg }
 343 #define CL { OP_IMREG, cl_reg }
 344 #define DL { OP_IMREG, dl_reg }
 345 #define BL { OP_IMREG, bl_reg }
 346 #define AH { OP_IMREG, ah_reg }
 347 #define CH { OP_IMREG, ch_reg }
 348 #define DH { OP_IMREG, dh_reg }
 349 #define BH { OP_IMREG, bh_reg }
 350 #define AX { OP_IMREG, ax_reg }
 351 #define DX { OP_IMREG, dx_reg }
 352 #define zAX { OP_IMREG, z_mode_ax_reg }
 353 #define indirDX { OP_IMREG, indir_dx_reg }
 354
 355 #define Sw { OP_SEG, w_mode }
 356 #define Sv { OP_SEG, v_mode }
 357 #define Ap { OP_DIR, 0 }
 358 #define Ob { OP_OFF64, b_mode }
 359 #define Ov { OP_OFF64, v_mode }
 360 #define Xb { OP_DSreg, eSI_reg }
 361 #define Xv { OP_DSreg, eSI_reg }
 362 #define Xz { OP_DSreg, eSI_reg }
 363 #define Yb { OP_ESreg, eDI_reg }
 364 #define Yv { OP_ESreg, eDI_reg }
 365 #define DSBX { OP_DSreg, eBX_reg }
 366
 367 #define es { OP_REG, es_reg }
 368 #define ss { OP_REG, ss_reg }
 369 #define cs { OP_REG, cs_reg }
 370 #define ds { OP_REG, ds_reg }
 371 #define fs { OP_REG, fs_reg }
 372 #define gs { OP_REG, gs_reg }
 373
 374 #define MX { OP_MMX, 0 }
 375 #define XM { OP_XMM, 0 }
 376 #define XMScalar { OP_XMM, scalar_mode }
 377 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 378 #define XMM { OP_XMM, xmm_mode }
 379 #define XMxmmq { OP_XMM, xmmq_mode }
 380 #define EM { OP_EM, v_mode }
 381 #define EMS { OP_EM, v_swap_mode }
 382 #define EMd { OP_EM, d_mode }
 383 #define EMx { OP_EM, x_mode }
 384 #define EXbScalar { OP_EX, b_scalar_mode }
 385 #define EXw { OP_EX, w_mode }
 386 #define EXwScalar { OP_EX, w_scalar_mode }
 387 #define EXd { OP_EX, d_mode }
 388 #define EXdScalar { OP_EX, d_scalar_mode }
 389 #define EXdS { OP_EX, d_swap_mode }
 390 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
 391 #define EXq { OP_EX, q_mode }
 392 #define EXqScalar { OP_EX, q_scalar_mode }
 393 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
 394 #define EXqS { OP_EX, q_swap_mode }
 395 #define EXx { OP_EX, x_mode }
 396 #define EXxS { OP_EX, x_swap_mode }
 397 #define EXxmm { OP_EX, xmm_mode }
 398 #define EXymm { OP_EX, ymm_mode }
 399 #define EXxmmq { OP_EX, xmmq_mode }
 400 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 401 #define EXxmm_mb { OP_EX, xmm_mb_mode }
 402 #define EXxmm_mw { OP_EX, xmm_mw_mode }
 403 #define EXxmm_md { OP_EX, xmm_md_mode }
 404 #define EXxmm_mq { OP_EX, xmm_mq_mode }
 405 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
 406 #define EXxmmdw { OP_EX, xmmdw_mode }
 407 #define EXxmmqd { OP_EX, xmmqd_mode }
 408 #define EXymmq { OP_EX, ymmq_mode }
 409 #define EXVexWdq { OP_EX, vex_w_dq_mode }
 410 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 411 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 412 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 413 #define MS { OP_MS, v_mode }
 414 #define XS { OP_XS, v_mode }
 415 #define EMCq { OP_EMC, q_mode }
 416 #define MXC { OP_MXC, 0 }
 417 #define OPSUF { OP_3DNowSuffix, 0 }
 418 #define CMP { CMP_Fixup, 0 }
 419 #define XMM0 { XMM_Fixup, 0 }
 420 #define FXSAVE { FXSAVE_Fixup, 0 }
 421 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
 422 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
 423
 424 #define Vex { OP_VEX, vex_mode }
 425 #define VexScalar { OP_VEX, vex_scalar_mode }
 426 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 427 #define Vex128 { OP_VEX, vex128_mode }
 428 #define Vex256 { OP_VEX, vex256_mode }
 429 #define VexGdq { OP_VEX, dq_mode }
 430 #define EXdVex { OP_EX_Vex, d_mode }
 431 #define EXdVexS { OP_EX_Vex, d_swap_mode }
 432 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
 433 #define EXqVex { OP_EX_Vex, q_mode }
 434 #define EXqVexS { OP_EX_Vex, q_swap_mode }
 435 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
 436 #define EXVexW { OP_EX_VexW, x_mode }
 437 #define EXdVexW { OP_EX_VexW, d_mode }
 438 #define EXqVexW { OP_EX_VexW, q_mode }
 439 #define EXVexImmW { OP_EX_VexImmW, x_mode }
 440 #define XMVex { OP_XMM_Vex, 0 }
 441 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
 442 #define XMVexW { OP_XMM_VexW, 0 }
 443 #define XMVexI4 { OP_REG_VexI4, x_mode }
 444 #define PCLMUL { PCLMUL_Fixup, 0 }
 445 #define VZERO { VZERO_Fixup, 0 }
 446 #define VCMP { VCMP_Fixup, 0 }
 447 #define VPCMP { VPCMP_Fixup, 0 }
 448 #define VPCOM { VPCOM_Fixup, 0 }
 449
 450 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 451 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 452
 453 #define XMask { OP_Mask, mask_mode }
 454 #define MaskG { OP_G, mask_mode }
 455 #define MaskE { OP_E, mask_mode }
 456 #define MaskBDE { OP_E, mask_bd_mode }
 457 #define MaskR { OP_R, mask_mode }
 458 #define MaskVex { OP_VEX, mask_mode }
 459
 460 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 461 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
 462 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 463 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
 464
 465 /* Used handle "rep" prefix for string instructions.  */
 466 #define Xbr { REP_Fixup, eSI_reg }
 467 #define Xvr { REP_Fixup, eSI_reg }
 468 #define Ybr { REP_Fixup, eDI_reg }
 469 #define Yvr { REP_Fixup, eDI_reg }
 470 #define Yzr { REP_Fixup, eDI_reg }
 471 #define indirDXr { REP_Fixup, indir_dx_reg }
 472 #define ALr { REP_Fixup, al_reg }
 473 #define eAXr { REP_Fixup, eAX_reg }
 474
 475 /* Used handle HLE prefix for lockable instructions.  */
 476 #define Ebh1 { HLE_Fixup1, b_mode }
 477 #define Evh1 { HLE_Fixup1, v_mode }
 478 #define Ebh2 { HLE_Fixup2, b_mode }
 479 #define Evh2 { HLE_Fixup2, v_mode }
 480 #define Ebh3 { HLE_Fixup3, b_mode }
 481 #define Evh3 { HLE_Fixup3, v_mode }
 482
 483 #define BND { BND_Fixup, 0 }
 484 #define NOTRACK { NOTRACK_Fixup, 0 }
 485
 486 #define cond_jump_flag { NULL, cond_jump_mode }
 487 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 488
 489 /* bits in sizeflag */
 490 #define SUFFIX_ALWAYS 4
 491 #define AFLAG 2
 492 #define DFLAG 1
 493
 494 enum
 495 {
 496   /* byte operand */
 497   b_mode = 1,
 498   /* byte operand with operand swapped */
 499   b_swap_mode,
 500   /* byte operand, sign extend like 'T' suffix */
 501   b_T_mode,
 502   /* operand size depends on prefixes */
 503   v_mode,
 504   /* operand size depends on prefixes with operand swapped */
 505   v_swap_mode,
 506   /* operand size depends on address prefix */
 507   va_mode,
 508   /* word operand */
 509   w_mode,
 510   /* double word operand  */
 511   d_mode,
 512   /* double word operand with operand swapped */
 513   d_swap_mode,
 514   /* quad word operand */
 515   q_mode,
 516   /* quad word operand with operand swapped */
 517   q_swap_mode,
 518   /* ten-byte operand */
 519   t_mode,
 520   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 521      broadcast enabled.  */
 522   x_mode,
 523   /* Similar to x_mode, but with different EVEX mem shifts.  */
 524   evex_x_gscat_mode,
 525   /* Similar to x_mode, but with disabled broadcast.  */
 526   evex_x_nobcst_mode,
 527   /* Similar to x_mode, but with operands swapped and disabled broadcast
 528      in EVEX.  */
 529   x_swap_mode,
 530   /* 16-byte XMM operand */
 531   xmm_mode,
 532   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 533      memory operand (depending on vector length).  Broadcast isn't
 534      allowed.  */
 535   xmmq_mode,
 536   /* Same as xmmq_mode, but broadcast is allowed.  */
 537   evex_half_bcst_xmmq_mode,
 538   /* XMM register or byte memory operand */
 539   xmm_mb_mode,
 540   /* XMM register or word memory operand */
 541   xmm_mw_mode,
 542   /* XMM register or double word memory operand */
 543   xmm_md_mode,
 544   /* XMM register or quad word memory operand */
 545   xmm_mq_mode,
 546   /* XMM register or double/quad word memory operand, depending on
 547      VEX.W.  */
 548   xmm_mdq_mode,
 549   /* 16-byte XMM, word, double word or quad word operand.  */
 550   xmmdw_mode,
 551   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 552   xmmqd_mode,
 553   /* 32-byte YMM operand */
 554   ymm_mode,
 555   /* quad word, ymmword or zmmword memory operand.  */
 556   ymmq_mode,
 557   /* 32-byte YMM or 16-byte word operand */
 558   ymmxmm_mode,
 559   /* d_mode in 32bit, q_mode in 64bit mode.  */
 560   m_mode,
 561   /* pair of v_mode operands */
 562   a_mode,
 563   cond_jump_mode,
 564   loop_jcxz_mode,
 565   v_bnd_mode,
 566   /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode.  */
 567   v_bndmk_mode,
 568   /* operand size depends on REX prefixes.  */
 569   dq_mode,
 570   /* registers like dq_mode, memory like w_mode.  */
 571   dqw_mode,
 572   /* bounds operand */
 573   bnd_mode,
 574   /* bounds operand with operand swapped */
 575   bnd_swap_mode,
 576   /* 4- or 6-byte pointer operand */
 577   f_mode,
 578   const_1_mode,
 579   /* v_mode for indirect branch opcodes.  */
 580   indir_v_mode,
 581   /* v_mode for stack-related opcodes.  */
 582   stack_v_mode,
 583   /* non-quad operand size depends on prefixes */
 584   z_mode,
 585   /* 16-byte operand */
 586   o_mode,
 587   /* registers like dq_mode, memory like b_mode.  */
 588   dqb_mode,
 589   /* registers like d_mode, memory like b_mode.  */
 590   db_mode,
 591   /* registers like d_mode, memory like w_mode.  */
 592   dw_mode,
 593   /* registers like dq_mode, memory like d_mode.  */
 594   dqd_mode,
 595   /* operand size depends on the W bit as well as address mode.  */
 596   dqa_mode,
 597   /* normal vex mode */
 598   vex_mode,
 599   /* 128bit vex mode */
 600   vex128_mode,
 601   /* 256bit vex mode */
 602   vex256_mode,
 603   /* operand size depends on the VEX.W bit.  */
 604   vex_w_dq_mode,
 605
 606   /* Similar to vex_w_dq_mode, with VSIB dword indices.  */
 607   vex_vsib_d_w_dq_mode,
 608   /* Similar to vex_vsib_d_w_dq_mode, with smaller memory.  */
 609   vex_vsib_d_w_d_mode,
 610   /* Similar to vex_w_dq_mode, with VSIB qword indices.  */
 611   vex_vsib_q_w_dq_mode,
 612   /* Similar to vex_vsib_q_w_dq_mode, with smaller memory.  */
 613   vex_vsib_q_w_d_mode,
 614
 615   /* scalar, ignore vector length.  */
 616   scalar_mode,
 617   /* like b_mode, ignore vector length.  */
 618   b_scalar_mode,
 619   /* like w_mode, ignore vector length.  */
 620   w_scalar_mode,
 621   /* like d_mode, ignore vector length.  */
 622   d_scalar_mode,
 623   /* like d_swap_mode, ignore vector length.  */
 624   d_scalar_swap_mode,
 625   /* like q_mode, ignore vector length.  */
 626   q_scalar_mode,
 627   /* like q_swap_mode, ignore vector length.  */
 628   q_scalar_swap_mode,
 629   /* like vex_mode, ignore vector length.  */
 630   vex_scalar_mode,
 631   /* like vex_w_dq_mode, ignore vector length.  */
 632   vex_scalar_w_dq_mode,
 633
 634   /* Static rounding.  */
 635   evex_rounding_mode,
 636   /* Supress all exceptions.  */
 637   evex_sae_mode,
 638
 639   /* Mask register operand.  */
 640   mask_mode,
 641   /* Mask register operand.  */
 642   mask_bd_mode,
 643
 644   es_reg,
 645   cs_reg,
 646   ss_reg,
 647   ds_reg,
 648   fs_reg,
 649   gs_reg,
 650
 651   eAX_reg,
 652   eCX_reg,
 653   eDX_reg,
 654   eBX_reg,
 655   eSP_reg,
 656   eBP_reg,
 657   eSI_reg,
 658   eDI_reg,
 659
 660   al_reg,
 661   cl_reg,
 662   dl_reg,
 663   bl_reg,
 664   ah_reg,
 665   ch_reg,
 666   dh_reg,
 667   bh_reg,
 668
 669   ax_reg,
 670   cx_reg,
 671   dx_reg,
 672   bx_reg,
 673   sp_reg,
 674   bp_reg,
 675   si_reg,
 676   di_reg,
 677
 678   rAX_reg,
 679   rCX_reg,
 680   rDX_reg,
 681   rBX_reg,
 682   rSP_reg,
 683   rBP_reg,
 684   rSI_reg,
 685   rDI_reg,
 686
 687   z_mode_ax_reg,
 688   indir_dx_reg
 689 };
 690
 691 enum
 692 {
 693   FLOATCODE = 1,
 694   USE_REG_TABLE,
 695   USE_MOD_TABLE,
 696   USE_RM_TABLE,
 697   USE_PREFIX_TABLE,
 698   USE_X86_64_TABLE,
 699   USE_3BYTE_TABLE,
 700   USE_XOP_8F_TABLE,
 701   USE_VEX_C4_TABLE,
 702   USE_VEX_C5_TABLE,
 703   USE_VEX_LEN_TABLE,
 704   USE_VEX_W_TABLE,
 705   USE_EVEX_TABLE
 706 };
 707
 708 #define FLOAT                   NULL, { { NULL, FLOATCODE } }, 0
 709
 710 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }, 0
 711 #define DIS386_PREFIX(T, I, P)          NULL, { { NULL, (T)}, { NULL,  (I) } }, P
 712 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 713 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 714 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 715 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 716 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 717 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 718 #define THREE_BYTE_TABLE_PREFIX(I, P)   DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
 719 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 720 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 721 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 722 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 723 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 724 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 725
 726 enum
 727 {
 728   REG_80 = 0,
 729   REG_81,
 730   REG_83,
 731   REG_8F,
 732   REG_C0,
 733   REG_C1,
 734   REG_C6,
 735   REG_C7,
 736   REG_D0,
 737   REG_D1,
 738   REG_D2,
 739   REG_D3,
 740   REG_F6,
 741   REG_F7,
 742   REG_FE,
 743   REG_FF,
 744   REG_0F00,
 745   REG_0F01,
 746   REG_0F0D,
 747   REG_0F18,
 748   REG_0F1C_MOD_0,
 749   REG_0F1E_MOD_3,
 750   REG_0F71,
 751   REG_0F72,
 752   REG_0F73,
 753   REG_0FA6,
 754   REG_0FA7,
 755   REG_0FAE,
 756   REG_0FBA,
 757   REG_0FC7,
 758   REG_VEX_0F71,
 759   REG_VEX_0F72,
 760   REG_VEX_0F73,
 761   REG_VEX_0FAE,
 762   REG_VEX_0F38F3,
 763   REG_XOP_LWPCB,
 764   REG_XOP_LWP,
 765   REG_XOP_TBM_01,
 766   REG_XOP_TBM_02,
 767
 768   REG_EVEX_0F71,
 769   REG_EVEX_0F72,
 770   REG_EVEX_0F73,
 771   REG_EVEX_0F38C6,
 772   REG_EVEX_0F38C7
 773 };
 774
 775 enum
 776 {
 777   MOD_8D = 0,
 778   MOD_C6_REG_7,
 779   MOD_C7_REG_7,
 780   MOD_FF_REG_3,
 781   MOD_FF_REG_5,
 782   MOD_0F01_REG_0,
 783   MOD_0F01_REG_1,
 784   MOD_0F01_REG_2,
 785   MOD_0F01_REG_3,
 786   MOD_0F01_REG_5,
 787   MOD_0F01_REG_7,
 788   MOD_0F12_PREFIX_0,
 789   MOD_0F13,
 790   MOD_0F16_PREFIX_0,
 791   MOD_0F17,
 792   MOD_0F18_REG_0,
 793   MOD_0F18_REG_1,
 794   MOD_0F18_REG_2,
 795   MOD_0F18_REG_3,
 796   MOD_0F18_REG_4,
 797   MOD_0F18_REG_5,
 798   MOD_0F18_REG_6,
 799   MOD_0F18_REG_7,
 800   MOD_0F1A_PREFIX_0,
 801   MOD_0F1B_PREFIX_0,
 802   MOD_0F1B_PREFIX_1,
 803   MOD_0F1C_PREFIX_0,
 804   MOD_0F1E_PREFIX_1,
 805   MOD_0F24,
 806   MOD_0F26,
 807   MOD_0F2B_PREFIX_0,
 808   MOD_0F2B_PREFIX_1,
 809   MOD_0F2B_PREFIX_2,
 810   MOD_0F2B_PREFIX_3,
 811   MOD_0F51,
 812   MOD_0F71_REG_2,
 813   MOD_0F71_REG_4,
 814   MOD_0F71_REG_6,
 815   MOD_0F72_REG_2,
 816   MOD_0F72_REG_4,
 817   MOD_0F72_REG_6,
 818   MOD_0F73_REG_2,
 819   MOD_0F73_REG_3,
 820   MOD_0F73_REG_6,
 821   MOD_0F73_REG_7,
 822   MOD_0FAE_REG_0,
 823   MOD_0FAE_REG_1,
 824   MOD_0FAE_REG_2,
 825   MOD_0FAE_REG_3,
 826   MOD_0FAE_REG_4,
 827   MOD_0FAE_REG_5,
 828   MOD_0FAE_REG_6,
 829   MOD_0FAE_REG_7,
 830   MOD_0FB2,
 831   MOD_0FB4,
 832   MOD_0FB5,
 833   MOD_0FC3,
 834   MOD_0FC7_REG_3,
 835   MOD_0FC7_REG_4,
 836   MOD_0FC7_REG_5,
 837   MOD_0FC7_REG_6,
 838   MOD_0FC7_REG_7,
 839   MOD_0FD7,
 840   MOD_0FE7_PREFIX_2,
 841   MOD_0FF0_PREFIX_3,
 842   MOD_0F382A_PREFIX_2,
 843   MOD_0F38F5_PREFIX_2,
 844   MOD_0F38F6_PREFIX_0,
 845   MOD_0F38F8_PREFIX_2,
 846   MOD_0F38F9_PREFIX_0,
 847   MOD_62_32BIT,
 848   MOD_C4_32BIT,
 849   MOD_C5_32BIT,
 850   MOD_VEX_0F12_PREFIX_0,
 851   MOD_VEX_0F13,
 852   MOD_VEX_0F16_PREFIX_0,
 853   MOD_VEX_0F17,
 854   MOD_VEX_0F2B,
 855   MOD_VEX_W_0_0F41_P_0_LEN_1,
 856   MOD_VEX_W_1_0F41_P_0_LEN_1,
 857   MOD_VEX_W_0_0F41_P_2_LEN_1,
 858   MOD_VEX_W_1_0F41_P_2_LEN_1,
 859   MOD_VEX_W_0_0F42_P_0_LEN_1,
 860   MOD_VEX_W_1_0F42_P_0_LEN_1,
 861   MOD_VEX_W_0_0F42_P_2_LEN_1,
 862   MOD_VEX_W_1_0F42_P_2_LEN_1,
 863   MOD_VEX_W_0_0F44_P_0_LEN_1,
 864   MOD_VEX_W_1_0F44_P_0_LEN_1,
 865   MOD_VEX_W_0_0F44_P_2_LEN_1,
 866   MOD_VEX_W_1_0F44_P_2_LEN_1,
 867   MOD_VEX_W_0_0F45_P_0_LEN_1,
 868   MOD_VEX_W_1_0F45_P_0_LEN_1,
 869   MOD_VEX_W_0_0F45_P_2_LEN_1,
 870   MOD_VEX_W_1_0F45_P_2_LEN_1,
 871   MOD_VEX_W_0_0F46_P_0_LEN_1,
 872   MOD_VEX_W_1_0F46_P_0_LEN_1,
 873   MOD_VEX_W_0_0F46_P_2_LEN_1,
 874   MOD_VEX_W_1_0F46_P_2_LEN_1,
 875   MOD_VEX_W_0_0F47_P_0_LEN_1,
 876   MOD_VEX_W_1_0F47_P_0_LEN_1,
 877   MOD_VEX_W_0_0F47_P_2_LEN_1,
 878   MOD_VEX_W_1_0F47_P_2_LEN_1,
 879   MOD_VEX_W_0_0F4A_P_0_LEN_1,
 880   MOD_VEX_W_1_0F4A_P_0_LEN_1,
 881   MOD_VEX_W_0_0F4A_P_2_LEN_1,
 882   MOD_VEX_W_1_0F4A_P_2_LEN_1,
 883   MOD_VEX_W_0_0F4B_P_0_LEN_1,
 884   MOD_VEX_W_1_0F4B_P_0_LEN_1,
 885   MOD_VEX_W_0_0F4B_P_2_LEN_1,
 886   MOD_VEX_0F50,
 887   MOD_VEX_0F71_REG_2,
 888   MOD_VEX_0F71_REG_4,
 889   MOD_VEX_0F71_REG_6,
 890   MOD_VEX_0F72_REG_2,
 891   MOD_VEX_0F72_REG_4,
 892   MOD_VEX_0F72_REG_6,
 893   MOD_VEX_0F73_REG_2,
 894   MOD_VEX_0F73_REG_3,
 895   MOD_VEX_0F73_REG_6,
 896   MOD_VEX_0F73_REG_7,
 897   MOD_VEX_W_0_0F91_P_0_LEN_0,
 898   MOD_VEX_W_1_0F91_P_0_LEN_0,
 899   MOD_VEX_W_0_0F91_P_2_LEN_0,
 900   MOD_VEX_W_1_0F91_P_2_LEN_0,
 901   MOD_VEX_W_0_0F92_P_0_LEN_0,
 902   MOD_VEX_W_0_0F92_P_2_LEN_0,
 903   MOD_VEX_W_0_0F92_P_3_LEN_0,
 904   MOD_VEX_W_1_0F92_P_3_LEN_0,
 905   MOD_VEX_W_0_0F93_P_0_LEN_0,
 906   MOD_VEX_W_0_0F93_P_2_LEN_0,
 907   MOD_VEX_W_0_0F93_P_3_LEN_0,
 908   MOD_VEX_W_1_0F93_P_3_LEN_0,
 909   MOD_VEX_W_0_0F98_P_0_LEN_0,
 910   MOD_VEX_W_1_0F98_P_0_LEN_0,
 911   MOD_VEX_W_0_0F98_P_2_LEN_0,
 912   MOD_VEX_W_1_0F98_P_2_LEN_0,
 913   MOD_VEX_W_0_0F99_P_0_LEN_0,
 914   MOD_VEX_W_1_0F99_P_0_LEN_0,
 915   MOD_VEX_W_0_0F99_P_2_LEN_0,
 916   MOD_VEX_W_1_0F99_P_2_LEN_0,
 917   MOD_VEX_0FAE_REG_2,
 918   MOD_VEX_0FAE_REG_3,
 919   MOD_VEX_0FD7_PREFIX_2,
 920   MOD_VEX_0FE7_PREFIX_2,
 921   MOD_VEX_0FF0_PREFIX_3,
 922   MOD_VEX_0F381A_PREFIX_2,
 923   MOD_VEX_0F382A_PREFIX_2,
 924   MOD_VEX_0F382C_PREFIX_2,
 925   MOD_VEX_0F382D_PREFIX_2,
 926   MOD_VEX_0F382E_PREFIX_2,
 927   MOD_VEX_0F382F_PREFIX_2,
 928   MOD_VEX_0F385A_PREFIX_2,
 929   MOD_VEX_0F388C_PREFIX_2,
 930   MOD_VEX_0F388E_PREFIX_2,
 931   MOD_VEX_W_0_0F3A30_P_2_LEN_0,
 932   MOD_VEX_W_1_0F3A30_P_2_LEN_0,
 933   MOD_VEX_W_0_0F3A31_P_2_LEN_0,
 934   MOD_VEX_W_1_0F3A31_P_2_LEN_0,
 935   MOD_VEX_W_0_0F3A32_P_2_LEN_0,
 936   MOD_VEX_W_1_0F3A32_P_2_LEN_0,
 937   MOD_VEX_W_0_0F3A33_P_2_LEN_0,
 938   MOD_VEX_W_1_0F3A33_P_2_LEN_0,
 939
 940   MOD_EVEX_0F10_PREFIX_1,
 941   MOD_EVEX_0F10_PREFIX_3,
 942   MOD_EVEX_0F11_PREFIX_1,
 943   MOD_EVEX_0F11_PREFIX_3,
 944   MOD_EVEX_0F12_PREFIX_0,
 945   MOD_EVEX_0F16_PREFIX_0,
 946   MOD_EVEX_0F38C6_REG_1,
 947   MOD_EVEX_0F38C6_REG_2,
 948   MOD_EVEX_0F38C6_REG_5,
 949   MOD_EVEX_0F38C6_REG_6,
 950   MOD_EVEX_0F38C7_REG_1,
 951   MOD_EVEX_0F38C7_REG_2,
 952   MOD_EVEX_0F38C7_REG_5,
 953   MOD_EVEX_0F38C7_REG_6
 954 };
 955
 956 enum
 957 {
 958   RM_C6_REG_7 = 0,
 959   RM_C7_REG_7,
 960   RM_0F01_REG_0,
 961   RM_0F01_REG_1,
 962   RM_0F01_REG_2,
 963   RM_0F01_REG_3,
 964   RM_0F01_REG_5,
 965   RM_0F01_REG_7,
 966   RM_0F1E_MOD_3_REG_7,
 967   RM_0FAE_REG_6,
 968   RM_0FAE_REG_7
 969 };
 970
 971 enum
 972 {
 973   PREFIX_90 = 0,
 974   PREFIX_MOD_0_0F01_REG_5,
 975   PREFIX_MOD_3_0F01_REG_5_RM_0,
 976   PREFIX_MOD_3_0F01_REG_5_RM_2,
 977   PREFIX_0F09,
 978   PREFIX_0F10,
 979   PREFIX_0F11,
 980   PREFIX_0F12,
 981   PREFIX_0F16,
 982   PREFIX_0F1A,
 983   PREFIX_0F1B,
 984   PREFIX_0F1C,
 985   PREFIX_0F1E,
 986   PREFIX_0F2A,
 987   PREFIX_0F2B,
 988   PREFIX_0F2C,
 989   PREFIX_0F2D,
 990   PREFIX_0F2E,
 991   PREFIX_0F2F,
 992   PREFIX_0F51,
 993   PREFIX_0F52,
 994   PREFIX_0F53,
 995   PREFIX_0F58,
 996   PREFIX_0F59,
 997   PREFIX_0F5A,
 998   PREFIX_0F5B,
 999   PREFIX_0F5C,
1000   PREFIX_0F5D,
1001   PREFIX_0F5E,
1002   PREFIX_0F5F,
1003   PREFIX_0F60,
1004   PREFIX_0F61,
1005   PREFIX_0F62,
1006   PREFIX_0F6C,
1007   PREFIX_0F6D,
1008   PREFIX_0F6F,
1009   PREFIX_0F70,
1010   PREFIX_0F73_REG_3,
1011   PREFIX_0F73_REG_7,
1012   PREFIX_0F78,
1013   PREFIX_0F79,
1014   PREFIX_0F7C,
1015   PREFIX_0F7D,
1016   PREFIX_0F7E,
1017   PREFIX_0F7F,
1018   PREFIX_0FAE_REG_0,
1019   PREFIX_0FAE_REG_1,
1020   PREFIX_0FAE_REG_2,
1021   PREFIX_0FAE_REG_3,
1022   PREFIX_MOD_0_0FAE_REG_4,
1023   PREFIX_MOD_3_0FAE_REG_4,
1024   PREFIX_MOD_0_0FAE_REG_5,
1025   PREFIX_MOD_3_0FAE_REG_5,
1026   PREFIX_MOD_0_0FAE_REG_6,
1027   PREFIX_MOD_1_0FAE_REG_6,
1028   PREFIX_0FAE_REG_7,
1029   PREFIX_0FB8,
1030   PREFIX_0FBC,
1031   PREFIX_0FBD,
1032   PREFIX_0FC2,
1033   PREFIX_MOD_0_0FC3,
1034   PREFIX_MOD_0_0FC7_REG_6,
1035   PREFIX_MOD_3_0FC7_REG_6,
1036   PREFIX_MOD_3_0FC7_REG_7,
1037   PREFIX_0FD0,
1038   PREFIX_0FD6,
1039   PREFIX_0FE6,
1040   PREFIX_0FE7,
1041   PREFIX_0FF0,
1042   PREFIX_0FF7,
1043   PREFIX_0F3810,
1044   PREFIX_0F3814,
1045   PREFIX_0F3815,
1046   PREFIX_0F3817,
1047   PREFIX_0F3820,
1048   PREFIX_0F3821,
1049   PREFIX_0F3822,
1050   PREFIX_0F3823,
1051   PREFIX_0F3824,
1052   PREFIX_0F3825,
1053   PREFIX_0F3828,
1054   PREFIX_0F3829,
1055   PREFIX_0F382A,
1056   PREFIX_0F382B,
1057   PREFIX_0F3830,
1058   PREFIX_0F3831,
1059   PREFIX_0F3832,
1060   PREFIX_0F3833,
1061   PREFIX_0F3834,
1062   PREFIX_0F3835,
1063   PREFIX_0F3837,
1064   PREFIX_0F3838,
1065   PREFIX_0F3839,
1066   PREFIX_0F383A,
1067   PREFIX_0F383B,
1068   PREFIX_0F383C,
1069   PREFIX_0F383D,
1070   PREFIX_0F383E,
1071   PREFIX_0F383F,
1072   PREFIX_0F3840,
1073   PREFIX_0F3841,
1074   PREFIX_0F3880,
1075   PREFIX_0F3881,
1076   PREFIX_0F3882,
1077   PREFIX_0F38C8,
1078   PREFIX_0F38C9,
1079   PREFIX_0F38CA,
1080   PREFIX_0F38CB,
1081   PREFIX_0F38CC,
1082   PREFIX_0F38CD,
1083   PREFIX_0F38CF,
1084   PREFIX_0F38DB,
1085   PREFIX_0F38DC,
1086   PREFIX_0F38DD,
1087   PREFIX_0F38DE,
1088   PREFIX_0F38DF,
1089   PREFIX_0F38F0,
1090   PREFIX_0F38F1,
1091   PREFIX_0F38F5,
1092   PREFIX_0F38F6,
1093   PREFIX_0F38F8,
1094   PREFIX_0F38F9,
1095   PREFIX_0F3A08,
1096   PREFIX_0F3A09,
1097   PREFIX_0F3A0A,
1098   PREFIX_0F3A0B,
1099   PREFIX_0F3A0C,
1100   PREFIX_0F3A0D,
1101   PREFIX_0F3A0E,
1102   PREFIX_0F3A14,
1103   PREFIX_0F3A15,
1104   PREFIX_0F3A16,
1105   PREFIX_0F3A17,
1106   PREFIX_0F3A20,
1107   PREFIX_0F3A21,
1108   PREFIX_0F3A22,
1109   PREFIX_0F3A40,
1110   PREFIX_0F3A41,
1111   PREFIX_0F3A42,
1112   PREFIX_0F3A44,
1113   PREFIX_0F3A60,
1114   PREFIX_0F3A61,
1115   PREFIX_0F3A62,
1116   PREFIX_0F3A63,
1117   PREFIX_0F3ACC,
1118   PREFIX_0F3ACE,
1119   PREFIX_0F3ACF,
1120   PREFIX_0F3ADF,
1121   PREFIX_VEX_0F10,
1122   PREFIX_VEX_0F11,
1123   PREFIX_VEX_0F12,
1124   PREFIX_VEX_0F16,
1125   PREFIX_VEX_0F2A,
1126   PREFIX_VEX_0F2C,
1127   PREFIX_VEX_0F2D,
1128   PREFIX_VEX_0F2E,
1129   PREFIX_VEX_0F2F,
1130   PREFIX_VEX_0F41,
1131   PREFIX_VEX_0F42,
1132   PREFIX_VEX_0F44,
1133   PREFIX_VEX_0F45,
1134   PREFIX_VEX_0F46,
1135   PREFIX_VEX_0F47,
1136   PREFIX_VEX_0F4A,
1137   PREFIX_VEX_0F4B,
1138   PREFIX_VEX_0F51,
1139   PREFIX_VEX_0F52,
1140   PREFIX_VEX_0F53,
1141   PREFIX_VEX_0F58,
1142   PREFIX_VEX_0F59,
1143   PREFIX_VEX_0F5A,
1144   PREFIX_VEX_0F5B,
1145   PREFIX_VEX_0F5C,
1146   PREFIX_VEX_0F5D,
1147   PREFIX_VEX_0F5E,
1148   PREFIX_VEX_0F5F,
1149   PREFIX_VEX_0F60,
1150   PREFIX_VEX_0F61,
1151   PREFIX_VEX_0F62,
1152   PREFIX_VEX_0F63,
1153   PREFIX_VEX_0F64,
1154   PREFIX_VEX_0F65,
1155   PREFIX_VEX_0F66,
1156   PREFIX_VEX_0F67,
1157   PREFIX_VEX_0F68,
1158   PREFIX_VEX_0F69,
1159   PREFIX_VEX_0F6A,
1160   PREFIX_VEX_0F6B,
1161   PREFIX_VEX_0F6C,
1162   PREFIX_VEX_0F6D,
1163   PREFIX_VEX_0F6E,
1164   PREFIX_VEX_0F6F,
1165   PREFIX_VEX_0F70,
1166   PREFIX_VEX_0F71_REG_2,
1167   PREFIX_VEX_0F71_REG_4,
1168   PREFIX_VEX_0F71_REG_6,
1169   PREFIX_VEX_0F72_REG_2,
1170   PREFIX_VEX_0F72_REG_4,
1171   PREFIX_VEX_0F72_REG_6,
1172   PREFIX_VEX_0F73_REG_2,
1173   PREFIX_VEX_0F73_REG_3,
1174   PREFIX_VEX_0F73_REG_6,
1175   PREFIX_VEX_0F73_REG_7,
1176   PREFIX_VEX_0F74,
1177   PREFIX_VEX_0F75,
1178   PREFIX_VEX_0F76,
1179   PREFIX_VEX_0F77,
1180   PREFIX_VEX_0F7C,
1181   PREFIX_VEX_0F7D,
1182   PREFIX_VEX_0F7E,
1183   PREFIX_VEX_0F7F,
1184   PREFIX_VEX_0F90,
1185   PREFIX_VEX_0F91,
1186   PREFIX_VEX_0F92,
1187   PREFIX_VEX_0F93,
1188   PREFIX_VEX_0F98,
1189   PREFIX_VEX_0F99,
1190   PREFIX_VEX_0FC2,
1191   PREFIX_VEX_0FC4,
1192   PREFIX_VEX_0FC5,
1193   PREFIX_VEX_0FD0,
1194   PREFIX_VEX_0FD1,
1195   PREFIX_VEX_0FD2,
1196   PREFIX_VEX_0FD3,
1197   PREFIX_VEX_0FD4,
1198   PREFIX_VEX_0FD5,
1199   PREFIX_VEX_0FD6,
1200   PREFIX_VEX_0FD7,
1201   PREFIX_VEX_0FD8,
1202   PREFIX_VEX_0FD9,
1203   PREFIX_VEX_0FDA,
1204   PREFIX_VEX_0FDB,
1205   PREFIX_VEX_0FDC,
1206   PREFIX_VEX_0FDD,
1207   PREFIX_VEX_0FDE,
1208   PREFIX_VEX_0FDF,
1209   PREFIX_VEX_0FE0,
1210   PREFIX_VEX_0FE1,
1211   PREFIX_VEX_0FE2,
1212   PREFIX_VEX_0FE3,
1213   PREFIX_VEX_0FE4,
1214   PREFIX_VEX_0FE5,
1215   PREFIX_VEX_0FE6,
1216   PREFIX_VEX_0FE7,
1217   PREFIX_VEX_0FE8,
1218   PREFIX_VEX_0FE9,
1219   PREFIX_VEX_0FEA,
1220   PREFIX_VEX_0FEB,
1221   PREFIX_VEX_0FEC,
1222   PREFIX_VEX_0FED,
1223   PREFIX_VEX_0FEE,
1224   PREFIX_VEX_0FEF,
1225   PREFIX_VEX_0FF0,
1226   PREFIX_VEX_0FF1,
1227   PREFIX_VEX_0FF2,
1228   PREFIX_VEX_0FF3,
1229   PREFIX_VEX_0FF4,
1230   PREFIX_VEX_0FF5,
1231   PREFIX_VEX_0FF6,
1232   PREFIX_VEX_0FF7,
1233   PREFIX_VEX_0FF8,
1234   PREFIX_VEX_0FF9,
1235   PREFIX_VEX_0FFA,
1236   PREFIX_VEX_0FFB,
1237   PREFIX_VEX_0FFC,
1238   PREFIX_VEX_0FFD,
1239   PREFIX_VEX_0FFE,
1240   PREFIX_VEX_0F3800,
1241   PREFIX_VEX_0F3801,
1242   PREFIX_VEX_0F3802,
1243   PREFIX_VEX_0F3803,
1244   PREFIX_VEX_0F3804,
1245   PREFIX_VEX_0F3805,
1246   PREFIX_VEX_0F3806,
1247   PREFIX_VEX_0F3807,
1248   PREFIX_VEX_0F3808,
1249   PREFIX_VEX_0F3809,
1250   PREFIX_VEX_0F380A,
1251   PREFIX_VEX_0F380B,
1252   PREFIX_VEX_0F380C,
1253   PREFIX_VEX_0F380D,
1254   PREFIX_VEX_0F380E,
1255   PREFIX_VEX_0F380F,
1256   PREFIX_VEX_0F3813,
1257   PREFIX_VEX_0F3816,
1258   PREFIX_VEX_0F3817,
1259   PREFIX_VEX_0F3818,
1260   PREFIX_VEX_0F3819,
1261   PREFIX_VEX_0F381A,
1262   PREFIX_VEX_0F381C,
1263   PREFIX_VEX_0F381D,
1264   PREFIX_VEX_0F381E,
1265   PREFIX_VEX_0F3820,
1266   PREFIX_VEX_0F3821,
1267   PREFIX_VEX_0F3822,
1268   PREFIX_VEX_0F3823,
1269   PREFIX_VEX_0F3824,
1270   PREFIX_VEX_0F3825,
1271   PREFIX_VEX_0F3828,
1272   PREFIX_VEX_0F3829,
1273   PREFIX_VEX_0F382A,
1274   PREFIX_VEX_0F382B,
1275   PREFIX_VEX_0F382C,
1276   PREFIX_VEX_0F382D,
1277   PREFIX_VEX_0F382E,
1278   PREFIX_VEX_0F382F,
1279   PREFIX_VEX_0F3830,
1280   PREFIX_VEX_0F3831,
1281   PREFIX_VEX_0F3832,
1282   PREFIX_VEX_0F3833,
1283   PREFIX_VEX_0F3834,
1284   PREFIX_VEX_0F3835,
1285   PREFIX_VEX_0F3836,
1286   PREFIX_VEX_0F3837,
1287   PREFIX_VEX_0F3838,
1288   PREFIX_VEX_0F3839,
1289   PREFIX_VEX_0F383A,
1290   PREFIX_VEX_0F383B,
1291   PREFIX_VEX_0F383C,
1292   PREFIX_VEX_0F383D,
1293   PREFIX_VEX_0F383E,
1294   PREFIX_VEX_0F383F,
1295   PREFIX_VEX_0F3840,
1296   PREFIX_VEX_0F3841,
1297   PREFIX_VEX_0F3845,
1298   PREFIX_VEX_0F3846,
1299   PREFIX_VEX_0F3847,
1300   PREFIX_VEX_0F3858,
1301   PREFIX_VEX_0F3859,
1302   PREFIX_VEX_0F385A,
1303   PREFIX_VEX_0F3878,
1304   PREFIX_VEX_0F3879,
1305   PREFIX_VEX_0F388C,
1306   PREFIX_VEX_0F388E,
1307   PREFIX_VEX_0F3890,
1308   PREFIX_VEX_0F3891,
1309   PREFIX_VEX_0F3892,
1310   PREFIX_VEX_0F3893,
1311   PREFIX_VEX_0F3896,
1312   PREFIX_VEX_0F3897,
1313   PREFIX_VEX_0F3898,
1314   PREFIX_VEX_0F3899,
1315   PREFIX_VEX_0F389A,
1316   PREFIX_VEX_0F389B,
1317   PREFIX_VEX_0F389C,
1318   PREFIX_VEX_0F389D,
1319   PREFIX_VEX_0F389E,
1320   PREFIX_VEX_0F389F,
1321   PREFIX_VEX_0F38A6,
1322   PREFIX_VEX_0F38A7,
1323   PREFIX_VEX_0F38A8,
1324   PREFIX_VEX_0F38A9,
1325   PREFIX_VEX_0F38AA,
1326   PREFIX_VEX_0F38AB,
1327   PREFIX_VEX_0F38AC,
1328   PREFIX_VEX_0F38AD,
1329   PREFIX_VEX_0F38AE,
1330   PREFIX_VEX_0F38AF,
1331   PREFIX_VEX_0F38B6,
1332   PREFIX_VEX_0F38B7,
1333   PREFIX_VEX_0F38B8,
1334   PREFIX_VEX_0F38B9,
1335   PREFIX_VEX_0F38BA,
1336   PREFIX_VEX_0F38BB,
1337   PREFIX_VEX_0F38BC,
1338   PREFIX_VEX_0F38BD,
1339   PREFIX_VEX_0F38BE,
1340   PREFIX_VEX_0F38BF,
1341   PREFIX_VEX_0F38CF,
1342   PREFIX_VEX_0F38DB,
1343   PREFIX_VEX_0F38DC,
1344   PREFIX_VEX_0F38DD,
1345   PREFIX_VEX_0F38DE,
1346   PREFIX_VEX_0F38DF,
1347   PREFIX_VEX_0F38F2,
1348   PREFIX_VEX_0F38F3_REG_1,
1349   PREFIX_VEX_0F38F3_REG_2,
1350   PREFIX_VEX_0F38F3_REG_3,
1351   PREFIX_VEX_0F38F5,
1352   PREFIX_VEX_0F38F6,
1353   PREFIX_VEX_0F38F7,
1354   PREFIX_VEX_0F3A00,
1355   PREFIX_VEX_0F3A01,
1356   PREFIX_VEX_0F3A02,
1357   PREFIX_VEX_0F3A04,
1358   PREFIX_VEX_0F3A05,
1359   PREFIX_VEX_0F3A06,
1360   PREFIX_VEX_0F3A08,
1361   PREFIX_VEX_0F3A09,
1362   PREFIX_VEX_0F3A0A,
1363   PREFIX_VEX_0F3A0B,
1364   PREFIX_VEX_0F3A0C,
1365   PREFIX_VEX_0F3A0D,
1366   PREFIX_VEX_0F3A0E,
1367   PREFIX_VEX_0F3A0F,
1368   PREFIX_VEX_0F3A14,
1369   PREFIX_VEX_0F3A15,
1370   PREFIX_VEX_0F3A16,
1371   PREFIX_VEX_0F3A17,
1372   PREFIX_VEX_0F3A18,
1373   PREFIX_VEX_0F3A19,
1374   PREFIX_VEX_0F3A1D,
1375   PREFIX_VEX_0F3A20,
1376   PREFIX_VEX_0F3A21,
1377   PREFIX_VEX_0F3A22,
1378   PREFIX_VEX_0F3A30,
1379   PREFIX_VEX_0F3A31,
1380   PREFIX_VEX_0F3A32,
1381   PREFIX_VEX_0F3A33,
1382   PREFIX_VEX_0F3A38,
1383   PREFIX_VEX_0F3A39,
1384   PREFIX_VEX_0F3A40,
1385   PREFIX_VEX_0F3A41,
1386   PREFIX_VEX_0F3A42,
1387   PREFIX_VEX_0F3A44,
1388   PREFIX_VEX_0F3A46,
1389   PREFIX_VEX_0F3A48,
1390   PREFIX_VEX_0F3A49,
1391   PREFIX_VEX_0F3A4A,
1392   PREFIX_VEX_0F3A4B,
1393   PREFIX_VEX_0F3A4C,
1394   PREFIX_VEX_0F3A5C,
1395   PREFIX_VEX_0F3A5D,
1396   PREFIX_VEX_0F3A5E,
1397   PREFIX_VEX_0F3A5F,
1398   PREFIX_VEX_0F3A60,
1399   PREFIX_VEX_0F3A61,
1400   PREFIX_VEX_0F3A62,
1401   PREFIX_VEX_0F3A63,
1402   PREFIX_VEX_0F3A68,
1403   PREFIX_VEX_0F3A69,
1404   PREFIX_VEX_0F3A6A,
1405   PREFIX_VEX_0F3A6B,
1406   PREFIX_VEX_0F3A6C,
1407   PREFIX_VEX_0F3A6D,
1408   PREFIX_VEX_0F3A6E,
1409   PREFIX_VEX_0F3A6F,
1410   PREFIX_VEX_0F3A78,
1411   PREFIX_VEX_0F3A79,
1412   PREFIX_VEX_0F3A7A,
1413   PREFIX_VEX_0F3A7B,
1414   PREFIX_VEX_0F3A7C,
1415   PREFIX_VEX_0F3A7D,
1416   PREFIX_VEX_0F3A7E,
1417   PREFIX_VEX_0F3A7F,
1418   PREFIX_VEX_0F3ACE,
1419   PREFIX_VEX_0F3ACF,
1420   PREFIX_VEX_0F3ADF,
1421   PREFIX_VEX_0F3AF0,
1422
1423   PREFIX_EVEX_0F10,
1424   PREFIX_EVEX_0F11,
1425   PREFIX_EVEX_0F12,
1426   PREFIX_EVEX_0F13,
1427   PREFIX_EVEX_0F14,
1428   PREFIX_EVEX_0F15,
1429   PREFIX_EVEX_0F16,
1430   PREFIX_EVEX_0F17,
1431   PREFIX_EVEX_0F28,
1432   PREFIX_EVEX_0F29,
1433   PREFIX_EVEX_0F2A,
1434   PREFIX_EVEX_0F2B,
1435   PREFIX_EVEX_0F2C,
1436   PREFIX_EVEX_0F2D,
1437   PREFIX_EVEX_0F2E,
1438   PREFIX_EVEX_0F2F,
1439   PREFIX_EVEX_0F51,
1440   PREFIX_EVEX_0F54,
1441   PREFIX_EVEX_0F55,
1442   PREFIX_EVEX_0F56,
1443   PREFIX_EVEX_0F57,
1444   PREFIX_EVEX_0F58,
1445   PREFIX_EVEX_0F59,
1446   PREFIX_EVEX_0F5A,
1447   PREFIX_EVEX_0F5B,
1448   PREFIX_EVEX_0F5C,
1449   PREFIX_EVEX_0F5D,
1450   PREFIX_EVEX_0F5E,
1451   PREFIX_EVEX_0F5F,
1452   PREFIX_EVEX_0F60,
1453   PREFIX_EVEX_0F61,
1454   PREFIX_EVEX_0F62,
1455   PREFIX_EVEX_0F63,
1456   PREFIX_EVEX_0F64,
1457   PREFIX_EVEX_0F65,
1458   PREFIX_EVEX_0F66,
1459   PREFIX_EVEX_0F67,
1460   PREFIX_EVEX_0F68,
1461   PREFIX_EVEX_0F69,
1462   PREFIX_EVEX_0F6A,
1463   PREFIX_EVEX_0F6B,
1464   PREFIX_EVEX_0F6C,
1465   PREFIX_EVEX_0F6D,
1466   PREFIX_EVEX_0F6E,
1467   PREFIX_EVEX_0F6F,
1468   PREFIX_EVEX_0F70,
1469   PREFIX_EVEX_0F71_REG_2,
1470   PREFIX_EVEX_0F71_REG_4,
1471   PREFIX_EVEX_0F71_REG_6,
1472   PREFIX_EVEX_0F72_REG_0,
1473   PREFIX_EVEX_0F72_REG_1,
1474   PREFIX_EVEX_0F72_REG_2,
1475   PREFIX_EVEX_0F72_REG_4,
1476   PREFIX_EVEX_0F72_REG_6,
1477   PREFIX_EVEX_0F73_REG_2,
1478   PREFIX_EVEX_0F73_REG_3,
1479   PREFIX_EVEX_0F73_REG_6,
1480   PREFIX_EVEX_0F73_REG_7,
1481   PREFIX_EVEX_0F74,
1482   PREFIX_EVEX_0F75,
1483   PREFIX_EVEX_0F76,
1484   PREFIX_EVEX_0F78,
1485   PREFIX_EVEX_0F79,
1486   PREFIX_EVEX_0F7A,
1487   PREFIX_EVEX_0F7B,
1488   PREFIX_EVEX_0F7E,
1489   PREFIX_EVEX_0F7F,
1490   PREFIX_EVEX_0FC2,
1491   PREFIX_EVEX_0FC4,
1492   PREFIX_EVEX_0FC5,
1493   PREFIX_EVEX_0FC6,
1494   PREFIX_EVEX_0FD1,
1495   PREFIX_EVEX_0FD2,
1496   PREFIX_EVEX_0FD3,
1497   PREFIX_EVEX_0FD4,
1498   PREFIX_EVEX_0FD5,
1499   PREFIX_EVEX_0FD6,
1500   PREFIX_EVEX_0FD8,
1501   PREFIX_EVEX_0FD9,
1502   PREFIX_EVEX_0FDA,
1503   PREFIX_EVEX_0FDB,
1504   PREFIX_EVEX_0FDC,
1505   PREFIX_EVEX_0FDD,
1506   PREFIX_EVEX_0FDE,
1507   PREFIX_EVEX_0FDF,
1508   PREFIX_EVEX_0FE0,
1509   PREFIX_EVEX_0FE1,
1510   PREFIX_EVEX_0FE2,
1511   PREFIX_EVEX_0FE3,
1512   PREFIX_EVEX_0FE4,
1513   PREFIX_EVEX_0FE5,
1514   PREFIX_EVEX_0FE6,
1515   PREFIX_EVEX_0FE7,
1516   PREFIX_EVEX_0FE8,
1517   PREFIX_EVEX_0FE9,
1518   PREFIX_EVEX_0FEA,
1519   PREFIX_EVEX_0FEB,
1520   PREFIX_EVEX_0FEC,
1521   PREFIX_EVEX_0FED,
1522   PREFIX_EVEX_0FEE,
1523   PREFIX_EVEX_0FEF,
1524   PREFIX_EVEX_0FF1,
1525   PREFIX_EVEX_0FF2,
1526   PREFIX_EVEX_0FF3,
1527   PREFIX_EVEX_0FF4,
1528   PREFIX_EVEX_0FF5,
1529   PREFIX_EVEX_0FF6,
1530   PREFIX_EVEX_0FF8,
1531   PREFIX_EVEX_0FF9,
1532   PREFIX_EVEX_0FFA,
1533   PREFIX_EVEX_0FFB,
1534   PREFIX_EVEX_0FFC,
1535   PREFIX_EVEX_0FFD,
1536   PREFIX_EVEX_0FFE,
1537   PREFIX_EVEX_0F3800,
1538   PREFIX_EVEX_0F3804,
1539   PREFIX_EVEX_0F380B,
1540   PREFIX_EVEX_0F380C,
1541   PREFIX_EVEX_0F380D,
1542   PREFIX_EVEX_0F3810,
1543   PREFIX_EVEX_0F3811,
1544   PREFIX_EVEX_0F3812,
1545   PREFIX_EVEX_0F3813,
1546   PREFIX_EVEX_0F3814,
1547   PREFIX_EVEX_0F3815,
1548   PREFIX_EVEX_0F3816,
1549   PREFIX_EVEX_0F3818,
1550   PREFIX_EVEX_0F3819,
1551   PREFIX_EVEX_0F381A,
1552   PREFIX_EVEX_0F381B,
1553   PREFIX_EVEX_0F381C,
1554   PREFIX_EVEX_0F381D,
1555   PREFIX_EVEX_0F381E,
1556   PREFIX_EVEX_0F381F,
1557   PREFIX_EVEX_0F3820,
1558   PREFIX_EVEX_0F3821,
1559   PREFIX_EVEX_0F3822,
1560   PREFIX_EVEX_0F3823,
1561   PREFIX_EVEX_0F3824,
1562   PREFIX_EVEX_0F3825,
1563   PREFIX_EVEX_0F3826,
1564   PREFIX_EVEX_0F3827,
1565   PREFIX_EVEX_0F3828,
1566   PREFIX_EVEX_0F3829,
1567   PREFIX_EVEX_0F382A,
1568   PREFIX_EVEX_0F382B,
1569   PREFIX_EVEX_0F382C,
1570   PREFIX_EVEX_0F382D,
1571   PREFIX_EVEX_0F3830,
1572   PREFIX_EVEX_0F3831,
1573   PREFIX_EVEX_0F3832,
1574   PREFIX_EVEX_0F3833,
1575   PREFIX_EVEX_0F3834,
1576   PREFIX_EVEX_0F3835,
1577   PREFIX_EVEX_0F3836,
1578   PREFIX_EVEX_0F3837,
1579   PREFIX_EVEX_0F3838,
1580   PREFIX_EVEX_0F3839,
1581   PREFIX_EVEX_0F383A,
1582   PREFIX_EVEX_0F383B,
1583   PREFIX_EVEX_0F383C,
1584   PREFIX_EVEX_0F383D,
1585   PREFIX_EVEX_0F383E,
1586   PREFIX_EVEX_0F383F,
1587   PREFIX_EVEX_0F3840,
1588   PREFIX_EVEX_0F3842,
1589   PREFIX_EVEX_0F3843,
1590   PREFIX_EVEX_0F3844,
1591   PREFIX_EVEX_0F3845,
1592   PREFIX_EVEX_0F3846,
1593   PREFIX_EVEX_0F3847,
1594   PREFIX_EVEX_0F384C,
1595   PREFIX_EVEX_0F384D,
1596   PREFIX_EVEX_0F384E,
1597   PREFIX_EVEX_0F384F,
1598   PREFIX_EVEX_0F3850,
1599   PREFIX_EVEX_0F3851,
1600   PREFIX_EVEX_0F3852,
1601   PREFIX_EVEX_0F3853,
1602   PREFIX_EVEX_0F3854,
1603   PREFIX_EVEX_0F3855,
1604   PREFIX_EVEX_0F3858,
1605   PREFIX_EVEX_0F3859,
1606   PREFIX_EVEX_0F385A,
1607   PREFIX_EVEX_0F385B,
1608   PREFIX_EVEX_0F3862,
1609   PREFIX_EVEX_0F3863,
1610   PREFIX_EVEX_0F3864,
1611   PREFIX_EVEX_0F3865,
1612   PREFIX_EVEX_0F3866,
1613   PREFIX_EVEX_0F3870,
1614   PREFIX_EVEX_0F3871,
1615   PREFIX_EVEX_0F3872,
1616   PREFIX_EVEX_0F3873,
1617   PREFIX_EVEX_0F3875,
1618   PREFIX_EVEX_0F3876,
1619   PREFIX_EVEX_0F3877,
1620   PREFIX_EVEX_0F3878,
1621   PREFIX_EVEX_0F3879,
1622   PREFIX_EVEX_0F387A,
1623   PREFIX_EVEX_0F387B,
1624   PREFIX_EVEX_0F387C,
1625   PREFIX_EVEX_0F387D,
1626   PREFIX_EVEX_0F387E,
1627   PREFIX_EVEX_0F387F,
1628   PREFIX_EVEX_0F3883,
1629   PREFIX_EVEX_0F3888,
1630   PREFIX_EVEX_0F3889,
1631   PREFIX_EVEX_0F388A,
1632   PREFIX_EVEX_0F388B,
1633   PREFIX_EVEX_0F388D,
1634   PREFIX_EVEX_0F388F,
1635   PREFIX_EVEX_0F3890,
1636   PREFIX_EVEX_0F3891,
1637   PREFIX_EVEX_0F3892,
1638   PREFIX_EVEX_0F3893,
1639   PREFIX_EVEX_0F3896,
1640   PREFIX_EVEX_0F3897,
1641   PREFIX_EVEX_0F3898,
1642   PREFIX_EVEX_0F3899,
1643   PREFIX_EVEX_0F389A,
1644   PREFIX_EVEX_0F389B,
1645   PREFIX_EVEX_0F389C,
1646   PREFIX_EVEX_0F389D,
1647   PREFIX_EVEX_0F389E,
1648   PREFIX_EVEX_0F389F,
1649   PREFIX_EVEX_0F38A0,
1650   PREFIX_EVEX_0F38A1,
1651   PREFIX_EVEX_0F38A2,
1652   PREFIX_EVEX_0F38A3,
1653   PREFIX_EVEX_0F38A6,
1654   PREFIX_EVEX_0F38A7,
1655   PREFIX_EVEX_0F38A8,
1656   PREFIX_EVEX_0F38A9,
1657   PREFIX_EVEX_0F38AA,
1658   PREFIX_EVEX_0F38AB,
1659   PREFIX_EVEX_0F38AC,
1660   PREFIX_EVEX_0F38AD,
1661   PREFIX_EVEX_0F38AE,
1662   PREFIX_EVEX_0F38AF,
1663   PREFIX_EVEX_0F38B4,
1664   PREFIX_EVEX_0F38B5,
1665   PREFIX_EVEX_0F38B6,
1666   PREFIX_EVEX_0F38B7,
1667   PREFIX_EVEX_0F38B8,
1668   PREFIX_EVEX_0F38B9,
1669   PREFIX_EVEX_0F38BA,
1670   PREFIX_EVEX_0F38BB,
1671   PREFIX_EVEX_0F38BC,
1672   PREFIX_EVEX_0F38BD,
1673   PREFIX_EVEX_0F38BE,
1674   PREFIX_EVEX_0F38BF,
1675   PREFIX_EVEX_0F38C4,
1676   PREFIX_EVEX_0F38C6_REG_1,
1677   PREFIX_EVEX_0F38C6_REG_2,
1678   PREFIX_EVEX_0F38C6_REG_5,
1679   PREFIX_EVEX_0F38C6_REG_6,
1680   PREFIX_EVEX_0F38C7_REG_1,
1681   PREFIX_EVEX_0F38C7_REG_2,
1682   PREFIX_EVEX_0F38C7_REG_5,
1683   PREFIX_EVEX_0F38C7_REG_6,
1684   PREFIX_EVEX_0F38C8,
1685   PREFIX_EVEX_0F38CA,
1686   PREFIX_EVEX_0F38CB,
1687   PREFIX_EVEX_0F38CC,
1688   PREFIX_EVEX_0F38CD,
1689   PREFIX_EVEX_0F38CF,
1690   PREFIX_EVEX_0F38DC,
1691   PREFIX_EVEX_0F38DD,
1692   PREFIX_EVEX_0F38DE,
1693   PREFIX_EVEX_0F38DF,
1694
1695   PREFIX_EVEX_0F3A00,
1696   PREFIX_EVEX_0F3A01,
1697   PREFIX_EVEX_0F3A03,
1698   PREFIX_EVEX_0F3A04,
1699   PREFIX_EVEX_0F3A05,
1700   PREFIX_EVEX_0F3A08,
1701   PREFIX_EVEX_0F3A09,
1702   PREFIX_EVEX_0F3A0A,
1703   PREFIX_EVEX_0F3A0B,
1704   PREFIX_EVEX_0F3A0F,
1705   PREFIX_EVEX_0F3A14,
1706   PREFIX_EVEX_0F3A15,
1707   PREFIX_EVEX_0F3A16,
1708   PREFIX_EVEX_0F3A17,
1709   PREFIX_EVEX_0F3A18,
1710   PREFIX_EVEX_0F3A19,
1711   PREFIX_EVEX_0F3A1A,
1712   PREFIX_EVEX_0F3A1B,
1713   PREFIX_EVEX_0F3A1D,
1714   PREFIX_EVEX_0F3A1E,
1715   PREFIX_EVEX_0F3A1F,
1716   PREFIX_EVEX_0F3A20,
1717   PREFIX_EVEX_0F3A21,
1718   PREFIX_EVEX_0F3A22,
1719   PREFIX_EVEX_0F3A23,
1720   PREFIX_EVEX_0F3A25,
1721   PREFIX_EVEX_0F3A26,
1722   PREFIX_EVEX_0F3A27,
1723   PREFIX_EVEX_0F3A38,
1724   PREFIX_EVEX_0F3A39,
1725   PREFIX_EVEX_0F3A3A,
1726   PREFIX_EVEX_0F3A3B,
1727   PREFIX_EVEX_0F3A3E,
1728   PREFIX_EVEX_0F3A3F,
1729   PREFIX_EVEX_0F3A42,
1730   PREFIX_EVEX_0F3A43,
1731   PREFIX_EVEX_0F3A44,
1732   PREFIX_EVEX_0F3A50,
1733   PREFIX_EVEX_0F3A51,
1734   PREFIX_EVEX_0F3A54,
1735   PREFIX_EVEX_0F3A55,
1736   PREFIX_EVEX_0F3A56,
1737   PREFIX_EVEX_0F3A57,
1738   PREFIX_EVEX_0F3A66,
1739   PREFIX_EVEX_0F3A67,
1740   PREFIX_EVEX_0F3A70,
1741   PREFIX_EVEX_0F3A71,
1742   PREFIX_EVEX_0F3A72,
1743   PREFIX_EVEX_0F3A73,
1744   PREFIX_EVEX_0F3ACE,
1745   PREFIX_EVEX_0F3ACF
1746 };
1747
1748 enum
1749 {
1750   X86_64_06 = 0,
1751   X86_64_07,
1752   X86_64_0D,
1753   X86_64_16,
1754   X86_64_17,
1755   X86_64_1E,
1756   X86_64_1F,
1757   X86_64_27,
1758   X86_64_2F,
1759   X86_64_37,
1760   X86_64_3F,
1761   X86_64_60,
1762   X86_64_61,
1763   X86_64_62,
1764   X86_64_63,
1765   X86_64_6D,
1766   X86_64_6F,
1767   X86_64_82,
1768   X86_64_9A,
1769   X86_64_C4,
1770   X86_64_C5,
1771   X86_64_CE,
1772   X86_64_D4,
1773   X86_64_D5,
1774   X86_64_E8,
1775   X86_64_E9,
1776   X86_64_EA,
1777   X86_64_0F01_REG_0,
1778   X86_64_0F01_REG_1,
1779   X86_64_0F01_REG_2,
1780   X86_64_0F01_REG_3
1781 };
1782
1783 enum
1784 {
1785   THREE_BYTE_0F38 = 0,
1786   THREE_BYTE_0F3A
1787 };
1788
1789 enum
1790 {
1791   XOP_08 = 0,
1792   XOP_09,
1793   XOP_0A
1794 };
1795
1796 enum
1797 {
1798   VEX_0F = 0,
1799   VEX_0F38,
1800   VEX_0F3A
1801 };
1802
1803 enum
1804 {
1805   EVEX_0F = 0,
1806   EVEX_0F38,
1807   EVEX_0F3A
1808 };
1809
1810 enum
1811 {
1812   VEX_LEN_0F10_P_1 = 0,
1813   VEX_LEN_0F10_P_3,
1814   VEX_LEN_0F11_P_1,
1815   VEX_LEN_0F11_P_3,
1816   VEX_LEN_0F12_P_0_M_0,
1817   VEX_LEN_0F12_P_0_M_1,
1818   VEX_LEN_0F12_P_2,
1819   VEX_LEN_0F13_M_0,
1820   VEX_LEN_0F16_P_0_M_0,
1821   VEX_LEN_0F16_P_0_M_1,
1822   VEX_LEN_0F16_P_2,
1823   VEX_LEN_0F17_M_0,
1824   VEX_LEN_0F2A_P_1,
1825   VEX_LEN_0F2A_P_3,
1826   VEX_LEN_0F2C_P_1,
1827   VEX_LEN_0F2C_P_3,
1828   VEX_LEN_0F2D_P_1,
1829   VEX_LEN_0F2D_P_3,
1830   VEX_LEN_0F2E_P_0,
1831   VEX_LEN_0F2E_P_2,
1832   VEX_LEN_0F2F_P_0,
1833   VEX_LEN_0F2F_P_2,
1834   VEX_LEN_0F41_P_0,
1835   VEX_LEN_0F41_P_2,
1836   VEX_LEN_0F42_P_0,
1837   VEX_LEN_0F42_P_2,
1838   VEX_LEN_0F44_P_0,
1839   VEX_LEN_0F44_P_2,
1840   VEX_LEN_0F45_P_0,
1841   VEX_LEN_0F45_P_2,
1842   VEX_LEN_0F46_P_0,
1843   VEX_LEN_0F46_P_2,
1844   VEX_LEN_0F47_P_0,
1845   VEX_LEN_0F47_P_2,
1846   VEX_LEN_0F4A_P_0,
1847   VEX_LEN_0F4A_P_2,
1848   VEX_LEN_0F4B_P_0,
1849   VEX_LEN_0F4B_P_2,
1850   VEX_LEN_0F51_P_1,
1851   VEX_LEN_0F51_P_3,
1852   VEX_LEN_0F52_P_1,
1853   VEX_LEN_0F53_P_1,
1854   VEX_LEN_0F58_P_1,
1855   VEX_LEN_0F58_P_3,
1856   VEX_LEN_0F59_P_1,
1857   VEX_LEN_0F59_P_3,
1858   VEX_LEN_0F5A_P_1,
1859   VEX_LEN_0F5A_P_3,
1860   VEX_LEN_0F5C_P_1,
1861   VEX_LEN_0F5C_P_3,
1862   VEX_LEN_0F5D_P_1,
1863   VEX_LEN_0F5D_P_3,
1864   VEX_LEN_0F5E_P_1,
1865   VEX_LEN_0F5E_P_3,
1866   VEX_LEN_0F5F_P_1,
1867   VEX_LEN_0F5F_P_3,
1868   VEX_LEN_0F6E_P_2,
1869   VEX_LEN_0F7E_P_1,
1870   VEX_LEN_0F7E_P_2,
1871   VEX_LEN_0F90_P_0,
1872   VEX_LEN_0F90_P_2,
1873   VEX_LEN_0F91_P_0,
1874   VEX_LEN_0F91_P_2,
1875   VEX_LEN_0F92_P_0,
1876   VEX_LEN_0F92_P_2,
1877   VEX_LEN_0F92_P_3,
1878   VEX_LEN_0F93_P_0,
1879   VEX_LEN_0F93_P_2,
1880   VEX_LEN_0F93_P_3,
1881   VEX_LEN_0F98_P_0,
1882   VEX_LEN_0F98_P_2,
1883   VEX_LEN_0F99_P_0,
1884   VEX_LEN_0F99_P_2,
1885   VEX_LEN_0FAE_R_2_M_0,
1886   VEX_LEN_0FAE_R_3_M_0,
1887   VEX_LEN_0FC2_P_1,
1888   VEX_LEN_0FC2_P_3,
1889   VEX_LEN_0FC4_P_2,
1890   VEX_LEN_0FC5_P_2,
1891   VEX_LEN_0FD6_P_2,
1892   VEX_LEN_0FF7_P_2,
1893   VEX_LEN_0F3816_P_2,
1894   VEX_LEN_0F3819_P_2,
1895   VEX_LEN_0F381A_P_2_M_0,
1896   VEX_LEN_0F3836_P_2,
1897   VEX_LEN_0F3841_P_2,
1898   VEX_LEN_0F385A_P_2_M_0,
1899   VEX_LEN_0F38DB_P_2,
1900   VEX_LEN_0F38F2_P_0,
1901   VEX_LEN_0F38F3_R_1_P_0,
1902   VEX_LEN_0F38F3_R_2_P_0,
1903   VEX_LEN_0F38F3_R_3_P_0,
1904   VEX_LEN_0F38F5_P_0,
1905   VEX_LEN_0F38F5_P_1,
1906   VEX_LEN_0F38F5_P_3,
1907   VEX_LEN_0F38F6_P_3,
1908   VEX_LEN_0F38F7_P_0,
1909   VEX_LEN_0F38F7_P_1,
1910   VEX_LEN_0F38F7_P_2,
1911   VEX_LEN_0F38F7_P_3,
1912   VEX_LEN_0F3A00_P_2,
1913   VEX_LEN_0F3A01_P_2,
1914   VEX_LEN_0F3A06_P_2,
1915   VEX_LEN_0F3A0A_P_2,
1916   VEX_LEN_0F3A0B_P_2,
1917   VEX_LEN_0F3A14_P_2,
1918   VEX_LEN_0F3A15_P_2,
1919   VEX_LEN_0F3A16_P_2,
1920   VEX_LEN_0F3A17_P_2,
1921   VEX_LEN_0F3A18_P_2,
1922   VEX_LEN_0F3A19_P_2,
1923   VEX_LEN_0F3A20_P_2,
1924   VEX_LEN_0F3A21_P_2,
1925   VEX_LEN_0F3A22_P_2,
1926   VEX_LEN_0F3A30_P_2,
1927   VEX_LEN_0F3A31_P_2,
1928   VEX_LEN_0F3A32_P_2,
1929   VEX_LEN_0F3A33_P_2,
1930   VEX_LEN_0F3A38_P_2,
1931   VEX_LEN_0F3A39_P_2,
1932   VEX_LEN_0F3A41_P_2,
1933   VEX_LEN_0F3A46_P_2,
1934   VEX_LEN_0F3A60_P_2,
1935   VEX_LEN_0F3A61_P_2,
1936   VEX_LEN_0F3A62_P_2,
1937   VEX_LEN_0F3A63_P_2,
1938   VEX_LEN_0F3A6A_P_2,
1939   VEX_LEN_0F3A6B_P_2,
1940   VEX_LEN_0F3A6E_P_2,
1941   VEX_LEN_0F3A6F_P_2,
1942   VEX_LEN_0F3A7A_P_2,
1943   VEX_LEN_0F3A7B_P_2,
1944   VEX_LEN_0F3A7E_P_2,
1945   VEX_LEN_0F3A7F_P_2,
1946   VEX_LEN_0F3ADF_P_2,
1947   VEX_LEN_0F3AF0_P_3,
1948   VEX_LEN_0FXOP_08_CC,
1949   VEX_LEN_0FXOP_08_CD,
1950   VEX_LEN_0FXOP_08_CE,
1951   VEX_LEN_0FXOP_08_CF,
1952   VEX_LEN_0FXOP_08_EC,
1953   VEX_LEN_0FXOP_08_ED,
1954   VEX_LEN_0FXOP_08_EE,
1955   VEX_LEN_0FXOP_08_EF,
1956   VEX_LEN_0FXOP_09_80,
1957   VEX_LEN_0FXOP_09_81
1958 };
1959
1960 enum
1961 {
1962   VEX_W_0F10_P_0 = 0,
1963   VEX_W_0F10_P_1,
1964   VEX_W_0F10_P_2,
1965   VEX_W_0F10_P_3,
1966   VEX_W_0F11_P_0,
1967   VEX_W_0F11_P_1,
1968   VEX_W_0F11_P_2,
1969   VEX_W_0F11_P_3,
1970   VEX_W_0F12_P_0_M_0,
1971   VEX_W_0F12_P_0_M_1,
1972   VEX_W_0F12_P_1,
1973   VEX_W_0F12_P_2,
1974   VEX_W_0F12_P_3,
1975   VEX_W_0F13_M_0,
1976   VEX_W_0F14,
1977   VEX_W_0F15,
1978   VEX_W_0F16_P_0_M_0,
1979   VEX_W_0F16_P_0_M_1,
1980   VEX_W_0F16_P_1,
1981   VEX_W_0F16_P_2,
1982   VEX_W_0F17_M_0,
1983   VEX_W_0F28,
1984   VEX_W_0F29,
1985   VEX_W_0F2B_M_0,
1986   VEX_W_0F2E_P_0,
1987   VEX_W_0F2E_P_2,
1988   VEX_W_0F2F_P_0,
1989   VEX_W_0F2F_P_2,
1990   VEX_W_0F41_P_0_LEN_1,
1991   VEX_W_0F41_P_2_LEN_1,
1992   VEX_W_0F42_P_0_LEN_1,
1993   VEX_W_0F42_P_2_LEN_1,
1994   VEX_W_0F44_P_0_LEN_0,
1995   VEX_W_0F44_P_2_LEN_0,
1996   VEX_W_0F45_P_0_LEN_1,
1997   VEX_W_0F45_P_2_LEN_1,
1998   VEX_W_0F46_P_0_LEN_1,
1999   VEX_W_0F46_P_2_LEN_1,
2000   VEX_W_0F47_P_0_LEN_1,
2001   VEX_W_0F47_P_2_LEN_1,
2002   VEX_W_0F4A_P_0_LEN_1,
2003   VEX_W_0F4A_P_2_LEN_1,
2004   VEX_W_0F4B_P_0_LEN_1,
2005   VEX_W_0F4B_P_2_LEN_1,
2006   VEX_W_0F50_M_0,
2007   VEX_W_0F51_P_0,
2008   VEX_W_0F51_P_1,
2009   VEX_W_0F51_P_2,
2010   VEX_W_0F51_P_3,
2011   VEX_W_0F52_P_0,
2012   VEX_W_0F52_P_1,
2013   VEX_W_0F53_P_0,
2014   VEX_W_0F53_P_1,
2015   VEX_W_0F58_P_0,
2016   VEX_W_0F58_P_1,
2017   VEX_W_0F58_P_2,
2018   VEX_W_0F58_P_3,
2019   VEX_W_0F59_P_0,
2020   VEX_W_0F59_P_1,
2021   VEX_W_0F59_P_2,
2022   VEX_W_0F59_P_3,
2023   VEX_W_0F5A_P_0,
2024   VEX_W_0F5A_P_1,
2025   VEX_W_0F5A_P_3,
2026   VEX_W_0F5B_P_0,
2027   VEX_W_0F5B_P_1,
2028   VEX_W_0F5B_P_2,
2029   VEX_W_0F5C_P_0,
2030   VEX_W_0F5C_P_1,
2031   VEX_W_0F5C_P_2,
2032   VEX_W_0F5C_P_3,
2033   VEX_W_0F5D_P_0,
2034   VEX_W_0F5D_P_1,
2035   VEX_W_0F5D_P_2,
2036   VEX_W_0F5D_P_3,
2037   VEX_W_0F5E_P_0,
2038   VEX_W_0F5E_P_1,
2039   VEX_W_0F5E_P_2,
2040   VEX_W_0F5E_P_3,
2041   VEX_W_0F5F_P_0,
2042   VEX_W_0F5F_P_1,
2043   VEX_W_0F5F_P_2,
2044   VEX_W_0F5F_P_3,
2045   VEX_W_0F60_P_2,
2046   VEX_W_0F61_P_2,
2047   VEX_W_0F62_P_2,
2048   VEX_W_0F63_P_2,
2049   VEX_W_0F64_P_2,
2050   VEX_W_0F65_P_2,
2051   VEX_W_0F66_P_2,
2052   VEX_W_0F67_P_2,
2053   VEX_W_0F68_P_2,
2054   VEX_W_0F69_P_2,
2055   VEX_W_0F6A_P_2,
2056   VEX_W_0F6B_P_2,
2057   VEX_W_0F6C_P_2,
2058   VEX_W_0F6D_P_2,
2059   VEX_W_0F6F_P_1,
2060   VEX_W_0F6F_P_2,
2061   VEX_W_0F70_P_1,
2062   VEX_W_0F70_P_2,
2063   VEX_W_0F70_P_3,
2064   VEX_W_0F71_R_2_P_2,
2065   VEX_W_0F71_R_4_P_2,
2066   VEX_W_0F71_R_6_P_2,
2067   VEX_W_0F72_R_2_P_2,
2068   VEX_W_0F72_R_4_P_2,
2069   VEX_W_0F72_R_6_P_2,
2070   VEX_W_0F73_R_2_P_2,
2071   VEX_W_0F73_R_3_P_2,
2072   VEX_W_0F73_R_6_P_2,
2073   VEX_W_0F73_R_7_P_2,
2074   VEX_W_0F74_P_2,
2075   VEX_W_0F75_P_2,
2076   VEX_W_0F76_P_2,
2077   VEX_W_0F77_P_0,
2078   VEX_W_0F7C_P_2,
2079   VEX_W_0F7C_P_3,
2080   VEX_W_0F7D_P_2,
2081   VEX_W_0F7D_P_3,
2082   VEX_W_0F7E_P_1,
2083   VEX_W_0F7F_P_1,
2084   VEX_W_0F7F_P_2,
2085   VEX_W_0F90_P_0_LEN_0,
2086   VEX_W_0F90_P_2_LEN_0,
2087   VEX_W_0F91_P_0_LEN_0,
2088   VEX_W_0F91_P_2_LEN_0,
2089   VEX_W_0F92_P_0_LEN_0,
2090   VEX_W_0F92_P_2_LEN_0,
2091   VEX_W_0F92_P_3_LEN_0,
2092   VEX_W_0F93_P_0_LEN_0,
2093   VEX_W_0F93_P_2_LEN_0,
2094   VEX_W_0F93_P_3_LEN_0,
2095   VEX_W_0F98_P_0_LEN_0,
2096   VEX_W_0F98_P_2_LEN_0,
2097   VEX_W_0F99_P_0_LEN_0,
2098   VEX_W_0F99_P_2_LEN_0,
2099   VEX_W_0FAE_R_2_M_0,
2100   VEX_W_0FAE_R_3_M_0,
2101   VEX_W_0FC2_P_0,
2102   VEX_W_0FC2_P_1,
2103   VEX_W_0FC2_P_2,
2104   VEX_W_0FC2_P_3,
2105   VEX_W_0FC4_P_2,
2106   VEX_W_0FC5_P_2,
2107   VEX_W_0FD0_P_2,
2108   VEX_W_0FD0_P_3,
2109   VEX_W_0FD1_P_2,
2110   VEX_W_0FD2_P_2,
2111   VEX_W_0FD3_P_2,
2112   VEX_W_0FD4_P_2,
2113   VEX_W_0FD5_P_2,
2114   VEX_W_0FD6_P_2,
2115   VEX_W_0FD7_P_2_M_1,
2116   VEX_W_0FD8_P_2,
2117   VEX_W_0FD9_P_2,
2118   VEX_W_0FDA_P_2,
2119   VEX_W_0FDB_P_2,
2120   VEX_W_0FDC_P_2,
2121   VEX_W_0FDD_P_2,
2122   VEX_W_0FDE_P_2,
2123   VEX_W_0FDF_P_2,
2124   VEX_W_0FE0_P_2,
2125   VEX_W_0FE1_P_2,
2126   VEX_W_0FE2_P_2,
2127   VEX_W_0FE3_P_2,
2128   VEX_W_0FE4_P_2,
2129   VEX_W_0FE5_P_2,
2130   VEX_W_0FE6_P_1,
2131   VEX_W_0FE6_P_2,
2132   VEX_W_0FE6_P_3,
2133   VEX_W_0FE7_P_2_M_0,
2134   VEX_W_0FE8_P_2,
2135   VEX_W_0FE9_P_2,
2136   VEX_W_0FEA_P_2,
2137   VEX_W_0FEB_P_2,
2138   VEX_W_0FEC_P_2,
2139   VEX_W_0FED_P_2,
2140   VEX_W_0FEE_P_2,
2141   VEX_W_0FEF_P_2,
2142   VEX_W_0FF0_P_3_M_0,
2143   VEX_W_0FF1_P_2,
2144   VEX_W_0FF2_P_2,
2145   VEX_W_0FF3_P_2,
2146   VEX_W_0FF4_P_2,
2147   VEX_W_0FF5_P_2,
2148   VEX_W_0FF6_P_2,
2149   VEX_W_0FF7_P_2,
2150   VEX_W_0FF8_P_2,
2151   VEX_W_0FF9_P_2,
2152   VEX_W_0FFA_P_2,
2153   VEX_W_0FFB_P_2,
2154   VEX_W_0FFC_P_2,
2155   VEX_W_0FFD_P_2,
2156   VEX_W_0FFE_P_2,
2157   VEX_W_0F3800_P_2,
2158   VEX_W_0F3801_P_2,
2159   VEX_W_0F3802_P_2,
2160   VEX_W_0F3803_P_2,
2161   VEX_W_0F3804_P_2,
2162   VEX_W_0F3805_P_2,
2163   VEX_W_0F3806_P_2,
2164   VEX_W_0F3807_P_2,
2165   VEX_W_0F3808_P_2,
2166   VEX_W_0F3809_P_2,
2167   VEX_W_0F380A_P_2,
2168   VEX_W_0F380B_P_2,
2169   VEX_W_0F380C_P_2,
2170   VEX_W_0F380D_P_2,
2171   VEX_W_0F380E_P_2,
2172   VEX_W_0F380F_P_2,
2173   VEX_W_0F3816_P_2,
2174   VEX_W_0F3817_P_2,
2175   VEX_W_0F3818_P_2,
2176   VEX_W_0F3819_P_2,
2177   VEX_W_0F381A_P_2_M_0,
2178   VEX_W_0F381C_P_2,
2179   VEX_W_0F381D_P_2,
2180   VEX_W_0F381E_P_2,
2181   VEX_W_0F3820_P_2,
2182   VEX_W_0F3821_P_2,
2183   VEX_W_0F3822_P_2,
2184   VEX_W_0F3823_P_2,
2185   VEX_W_0F3824_P_2,
2186   VEX_W_0F3825_P_2,
2187   VEX_W_0F3828_P_2,
2188   VEX_W_0F3829_P_2,
2189   VEX_W_0F382A_P_2_M_0,
2190   VEX_W_0F382B_P_2,
2191   VEX_W_0F382C_P_2_M_0,
2192   VEX_W_0F382D_P_2_M_0,
2193   VEX_W_0F382E_P_2_M_0,
2194   VEX_W_0F382F_P_2_M_0,
2195   VEX_W_0F3830_P_2,
2196   VEX_W_0F3831_P_2,
2197   VEX_W_0F3832_P_2,
2198   VEX_W_0F3833_P_2,
2199   VEX_W_0F3834_P_2,
2200   VEX_W_0F3835_P_2,
2201   VEX_W_0F3836_P_2,
2202   VEX_W_0F3837_P_2,
2203   VEX_W_0F3838_P_2,
2204   VEX_W_0F3839_P_2,
2205   VEX_W_0F383A_P_2,
2206   VEX_W_0F383B_P_2,
2207   VEX_W_0F383C_P_2,
2208   VEX_W_0F383D_P_2,
2209   VEX_W_0F383E_P_2,
2210   VEX_W_0F383F_P_2,
2211   VEX_W_0F3840_P_2,
2212   VEX_W_0F3841_P_2,
2213   VEX_W_0F3846_P_2,
2214   VEX_W_0F3858_P_2,
2215   VEX_W_0F3859_P_2,
2216   VEX_W_0F385A_P_2_M_0,
2217   VEX_W_0F3878_P_2,
2218   VEX_W_0F3879_P_2,
2219   VEX_W_0F38CF_P_2,
2220   VEX_W_0F38DB_P_2,
2221   VEX_W_0F3A00_P_2,
2222   VEX_W_0F3A01_P_2,
2223   VEX_W_0F3A02_P_2,
2224   VEX_W_0F3A04_P_2,
2225   VEX_W_0F3A05_P_2,
2226   VEX_W_0F3A06_P_2,
2227   VEX_W_0F3A08_P_2,
2228   VEX_W_0F3A09_P_2,
2229   VEX_W_0F3A0A_P_2,
2230   VEX_W_0F3A0B_P_2,
2231   VEX_W_0F3A0C_P_2,
2232   VEX_W_0F3A0D_P_2,
2233   VEX_W_0F3A0E_P_2,
2234   VEX_W_0F3A0F_P_2,
2235   VEX_W_0F3A14_P_2,
2236   VEX_W_0F3A15_P_2,
2237   VEX_W_0F3A18_P_2,
2238   VEX_W_0F3A19_P_2,
2239   VEX_W_0F3A20_P_2,
2240   VEX_W_0F3A21_P_2,
2241   VEX_W_0F3A30_P_2_LEN_0,
2242   VEX_W_0F3A31_P_2_LEN_0,
2243   VEX_W_0F3A32_P_2_LEN_0,
2244   VEX_W_0F3A33_P_2_LEN_0,
2245   VEX_W_0F3A38_P_2,
2246   VEX_W_0F3A39_P_2,
2247   VEX_W_0F3A40_P_2,
2248   VEX_W_0F3A41_P_2,
2249   VEX_W_0F3A42_P_2,
2250   VEX_W_0F3A46_P_2,
2251   VEX_W_0F3A48_P_2,
2252   VEX_W_0F3A49_P_2,
2253   VEX_W_0F3A4A_P_2,
2254   VEX_W_0F3A4B_P_2,
2255   VEX_W_0F3A4C_P_2,
2256   VEX_W_0F3A62_P_2,
2257   VEX_W_0F3A63_P_2,
2258   VEX_W_0F3ACE_P_2,
2259   VEX_W_0F3ACF_P_2,
2260   VEX_W_0F3ADF_P_2,
2261
2262   EVEX_W_0F10_P_0,
2263   EVEX_W_0F10_P_1_M_0,
2264   EVEX_W_0F10_P_1_M_1,
2265   EVEX_W_0F10_P_2,
2266   EVEX_W_0F10_P_3_M_0,
2267   EVEX_W_0F10_P_3_M_1,
2268   EVEX_W_0F11_P_0,
2269   EVEX_W_0F11_P_1_M_0,
2270   EVEX_W_0F11_P_1_M_1,
2271   EVEX_W_0F11_P_2,
2272   EVEX_W_0F11_P_3_M_0,
2273   EVEX_W_0F11_P_3_M_1,
2274   EVEX_W_0F12_P_0_M_0,
2275   EVEX_W_0F12_P_0_M_1,
2276   EVEX_W_0F12_P_1,
2277   EVEX_W_0F12_P_2,
2278   EVEX_W_0F12_P_3,
2279   EVEX_W_0F13_P_0,
2280   EVEX_W_0F13_P_2,
2281   EVEX_W_0F14_P_0,
2282   EVEX_W_0F14_P_2,
2283   EVEX_W_0F15_P_0,
2284   EVEX_W_0F15_P_2,
2285   EVEX_W_0F16_P_0_M_0,
2286   EVEX_W_0F16_P_0_M_1,
2287   EVEX_W_0F16_P_1,
2288   EVEX_W_0F16_P_2,
2289   EVEX_W_0F17_P_0,
2290   EVEX_W_0F17_P_2,
2291   EVEX_W_0F28_P_0,
2292   EVEX_W_0F28_P_2,
2293   EVEX_W_0F29_P_0,
2294   EVEX_W_0F29_P_2,
2295   EVEX_W_0F2A_P_1,
2296   EVEX_W_0F2A_P_3,
2297   EVEX_W_0F2B_P_0,
2298   EVEX_W_0F2B_P_2,
2299   EVEX_W_0F2E_P_0,
2300   EVEX_W_0F2E_P_2,
2301   EVEX_W_0F2F_P_0,
2302   EVEX_W_0F2F_P_2,
2303   EVEX_W_0F51_P_0,
2304   EVEX_W_0F51_P_1,
2305   EVEX_W_0F51_P_2,
2306   EVEX_W_0F51_P_3,
2307   EVEX_W_0F54_P_0,
2308   EVEX_W_0F54_P_2,
2309   EVEX_W_0F55_P_0,
2310   EVEX_W_0F55_P_2,
2311   EVEX_W_0F56_P_0,
2312   EVEX_W_0F56_P_2,
2313   EVEX_W_0F57_P_0,
2314   EVEX_W_0F57_P_2,
2315   EVEX_W_0F58_P_0,
2316   EVEX_W_0F58_P_1,
2317   EVEX_W_0F58_P_2,
2318   EVEX_W_0F58_P_3,
2319   EVEX_W_0F59_P_0,
2320   EVEX_W_0F59_P_1,
2321   EVEX_W_0F59_P_2,
2322   EVEX_W_0F59_P_3,
2323   EVEX_W_0F5A_P_0,
2324   EVEX_W_0F5A_P_1,
2325   EVEX_W_0F5A_P_2,
2326   EVEX_W_0F5A_P_3,
2327   EVEX_W_0F5B_P_0,
2328   EVEX_W_0F5B_P_1,
2329   EVEX_W_0F5B_P_2,
2330   EVEX_W_0F5C_P_0,
2331   EVEX_W_0F5C_P_1,
2332   EVEX_W_0F5C_P_2,
2333   EVEX_W_0F5C_P_3,
2334   EVEX_W_0F5D_P_0,
2335   EVEX_W_0F5D_P_1,
2336   EVEX_W_0F5D_P_2,
2337   EVEX_W_0F5D_P_3,
2338   EVEX_W_0F5E_P_0,
2339   EVEX_W_0F5E_P_1,
2340   EVEX_W_0F5E_P_2,
2341   EVEX_W_0F5E_P_3,
2342   EVEX_W_0F5F_P_0,
2343   EVEX_W_0F5F_P_1,
2344   EVEX_W_0F5F_P_2,
2345   EVEX_W_0F5F_P_3,
2346   EVEX_W_0F62_P_2,
2347   EVEX_W_0F66_P_2,
2348   EVEX_W_0F6A_P_2,
2349   EVEX_W_0F6B_P_2,
2350   EVEX_W_0F6C_P_2,
2351   EVEX_W_0F6D_P_2,
2352   EVEX_W_0F6E_P_2,
2353   EVEX_W_0F6F_P_1,
2354   EVEX_W_0F6F_P_2,
2355   EVEX_W_0F6F_P_3,
2356   EVEX_W_0F70_P_2,
2357   EVEX_W_0F72_R_2_P_2,
2358   EVEX_W_0F72_R_6_P_2,
2359   EVEX_W_0F73_R_2_P_2,
2360   EVEX_W_0F73_R_6_P_2,
2361   EVEX_W_0F76_P_2,
2362   EVEX_W_0F78_P_0,
2363   EVEX_W_0F78_P_2,
2364   EVEX_W_0F79_P_0,
2365   EVEX_W_0F79_P_2,
2366   EVEX_W_0F7A_P_1,
2367   EVEX_W_0F7A_P_2,
2368   EVEX_W_0F7A_P_3,
2369   EVEX_W_0F7B_P_1,
2370   EVEX_W_0F7B_P_2,
2371   EVEX_W_0F7B_P_3,
2372   EVEX_W_0F7E_P_1,
2373   EVEX_W_0F7E_P_2,
2374   EVEX_W_0F7F_P_1,
2375   EVEX_W_0F7F_P_2,
2376   EVEX_W_0F7F_P_3,
2377   EVEX_W_0FC2_P_0,
2378   EVEX_W_0FC2_P_1,
2379   EVEX_W_0FC2_P_2,
2380   EVEX_W_0FC2_P_3,
2381   EVEX_W_0FC6_P_0,
2382   EVEX_W_0FC6_P_2,
2383   EVEX_W_0FD2_P_2,
2384   EVEX_W_0FD3_P_2,
2385   EVEX_W_0FD4_P_2,
2386   EVEX_W_0FD6_P_2,
2387   EVEX_W_0FE6_P_1,
2388   EVEX_W_0FE6_P_2,
2389   EVEX_W_0FE6_P_3,
2390   EVEX_W_0FE7_P_2,
2391   EVEX_W_0FF2_P_2,
2392   EVEX_W_0FF3_P_2,
2393   EVEX_W_0FF4_P_2,
2394   EVEX_W_0FFA_P_2,
2395   EVEX_W_0FFB_P_2,
2396   EVEX_W_0FFE_P_2,
2397   EVEX_W_0F380C_P_2,
2398   EVEX_W_0F380D_P_2,
2399   EVEX_W_0F3810_P_1,
2400   EVEX_W_0F3810_P_2,
2401   EVEX_W_0F3811_P_1,
2402   EVEX_W_0F3811_P_2,
2403   EVEX_W_0F3812_P_1,
2404   EVEX_W_0F3812_P_2,
2405   EVEX_W_0F3813_P_1,
2406   EVEX_W_0F3813_P_2,
2407   EVEX_W_0F3814_P_1,
2408   EVEX_W_0F3815_P_1,
2409   EVEX_W_0F3818_P_2,
2410   EVEX_W_0F3819_P_2,
2411   EVEX_W_0F381A_P_2,
2412   EVEX_W_0F381B_P_2,
2413   EVEX_W_0F381E_P_2,
2414   EVEX_W_0F381F_P_2,
2415   EVEX_W_0F3820_P_1,
2416   EVEX_W_0F3821_P_1,
2417   EVEX_W_0F3822_P_1,
2418   EVEX_W_0F3823_P_1,
2419   EVEX_W_0F3824_P_1,
2420   EVEX_W_0F3825_P_1,
2421   EVEX_W_0F3825_P_2,
2422   EVEX_W_0F3826_P_1,
2423   EVEX_W_0F3826_P_2,
2424   EVEX_W_0F3828_P_1,
2425   EVEX_W_0F3828_P_2,
2426   EVEX_W_0F3829_P_1,
2427   EVEX_W_0F3829_P_2,
2428   EVEX_W_0F382A_P_1,
2429   EVEX_W_0F382A_P_2,
2430   EVEX_W_0F382B_P_2,
2431   EVEX_W_0F3830_P_1,
2432   EVEX_W_0F3831_P_1,
2433   EVEX_W_0F3832_P_1,
2434   EVEX_W_0F3833_P_1,
2435   EVEX_W_0F3834_P_1,
2436   EVEX_W_0F3835_P_1,
2437   EVEX_W_0F3835_P_2,
2438   EVEX_W_0F3837_P_2,
2439   EVEX_W_0F3838_P_1,
2440   EVEX_W_0F3839_P_1,
2441   EVEX_W_0F383A_P_1,
2442   EVEX_W_0F3840_P_2,
2443   EVEX_W_0F3854_P_2,
2444   EVEX_W_0F3855_P_2,
2445   EVEX_W_0F3858_P_2,
2446   EVEX_W_0F3859_P_2,
2447   EVEX_W_0F385A_P_2,
2448   EVEX_W_0F385B_P_2,
2449   EVEX_W_0F3862_P_2,
2450   EVEX_W_0F3863_P_2,
2451   EVEX_W_0F3866_P_2,
2452   EVEX_W_0F3870_P_2,
2453   EVEX_W_0F3871_P_2,
2454   EVEX_W_0F3872_P_2,
2455   EVEX_W_0F3873_P_2,
2456   EVEX_W_0F3875_P_2,
2457   EVEX_W_0F3878_P_2,
2458   EVEX_W_0F3879_P_2,
2459   EVEX_W_0F387A_P_2,
2460   EVEX_W_0F387B_P_2,
2461   EVEX_W_0F387D_P_2,
2462   EVEX_W_0F3883_P_2,
2463   EVEX_W_0F388D_P_2,
2464   EVEX_W_0F3891_P_2,
2465   EVEX_W_0F3893_P_2,
2466   EVEX_W_0F38A1_P_2,
2467   EVEX_W_0F38A3_P_2,
2468   EVEX_W_0F38C7_R_1_P_2,
2469   EVEX_W_0F38C7_R_2_P_2,
2470   EVEX_W_0F38C7_R_5_P_2,
2471   EVEX_W_0F38C7_R_6_P_2,
2472
2473   EVEX_W_0F3A00_P_2,
2474   EVEX_W_0F3A01_P_2,
2475   EVEX_W_0F3A04_P_2,
2476   EVEX_W_0F3A05_P_2,
2477   EVEX_W_0F3A08_P_2,
2478   EVEX_W_0F3A09_P_2,
2479   EVEX_W_0F3A0A_P_2,
2480   EVEX_W_0F3A0B_P_2,
2481   EVEX_W_0F3A16_P_2,
2482   EVEX_W_0F3A18_P_2,
2483   EVEX_W_0F3A19_P_2,
2484   EVEX_W_0F3A1A_P_2,
2485   EVEX_W_0F3A1B_P_2,
2486   EVEX_W_0F3A1D_P_2,
2487   EVEX_W_0F3A21_P_2,
2488   EVEX_W_0F3A22_P_2,
2489   EVEX_W_0F3A23_P_2,
2490   EVEX_W_0F3A38_P_2,
2491   EVEX_W_0F3A39_P_2,
2492   EVEX_W_0F3A3A_P_2,
2493   EVEX_W_0F3A3B_P_2,
2494   EVEX_W_0F3A3E_P_2,
2495   EVEX_W_0F3A3F_P_2,
2496   EVEX_W_0F3A42_P_2,
2497   EVEX_W_0F3A43_P_2,
2498   EVEX_W_0F3A50_P_2,
2499   EVEX_W_0F3A51_P_2,
2500   EVEX_W_0F3A56_P_2,
2501   EVEX_W_0F3A57_P_2,
2502   EVEX_W_0F3A66_P_2,
2503   EVEX_W_0F3A67_P_2,
2504   EVEX_W_0F3A70_P_2,
2505   EVEX_W_0F3A71_P_2,
2506   EVEX_W_0F3A72_P_2,
2507   EVEX_W_0F3A73_P_2,
2508   EVEX_W_0F3ACE_P_2,
2509   EVEX_W_0F3ACF_P_2
2510 };
2511
2512 typedef void (*op_rtn) (int bytemode, int sizeflag);
2513
2514 struct dis386 {
2515   const char *name;
2516   struct
2517     {
2518       op_rtn rtn;
2519       int bytemode;
2520     } op[MAX_OPERANDS];
2521   unsigned int prefix_requirement;
2522 };
2523
2524 /* Upper case letters in the instruction names here are macros.
2525    'A' => print 'b' if no register operands or suffix_always is true
2526    'B' => print 'b' if suffix_always is true
2527    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2528           size prefix
2529    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2530           suffix_always is true
2531    'E' => print 'e' if 32-bit form of jcxz
2532    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2533    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2534    'H' => print ",pt" or ",pn" branch hint
2535    'I' => honor following macro letter even in Intel mode (implemented only
2536           for some of the macro letters)
2537    'J' => print 'l'
2538    'K' => print 'd' or 'q' if rex prefix is present.
2539    'L' => print 'l' if suffix_always is true
2540    'M' => print 'r' if intel_mnemonic is false.
2541    'N' => print 'n' if instruction has no wait "prefix"
2542    'O' => print 'd' or 'o' (or 'q' in Intel mode)
2543    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2544           or suffix_always is true.  print 'q' if rex prefix is present.
2545    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2546           is true
2547    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2548    'S' => print 'w', 'l' or 'q' if suffix_always is true
2549    'T' => print 'q' in 64bit mode if instruction has no operand size
2550           prefix and behave as 'P' otherwise
2551    'U' => print 'q' in 64bit mode if instruction has no operand size
2552           prefix and behave as 'Q' otherwise
2553    'V' => print 'q' in 64bit mode if instruction has no operand size
2554           prefix and behave as 'S' otherwise
2555    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2556    'X' => print 's', 'd' depending on data16 prefix (for XMM)
2557    'Y' unused.
2558    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2559    '!' => change condition from true to false or from false to true.
2560    '%' => add 1 upper case letter to the macro.
2561    '^' => print 'w' or 'l' depending on operand size prefix or
2562           suffix_always is true (lcall/ljmp).
2563    '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2564           on operand size prefix.
2565    '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2566           has no operand size prefix for AMD64 ISA, behave as 'P'
2567           otherwise
2568
2569    2 upper case letter macros:
2570    "XY" => print 'x' or 'y' if suffix_always is true or no register
2571            operands and no broadcast.
2572    "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2573            register operands and no broadcast.
2574    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2575    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2576            or suffix_always is true
2577    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2578    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2579    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2580    "LW" => print 'd', 'q' depending on the VEX.W bit
2581    "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2582            an operand size prefix, or suffix_always is true.  print
2583            'q' if rex prefix is present.
2584
2585    Many of the above letters print nothing in Intel mode.  See "putop"
2586    for the details.
2587
2588    Braces '{' and '}', and vertical bars '|', indicate alternative
2589    mnemonic strings for AT&T and Intel.  */
2590
2591 static const struct dis386 dis386[] = {
2592   /* 00 */
2593   { "addB",             { Ebh1, Gb }, 0 },
2594   { "addS",             { Evh1, Gv }, 0 },
2595   { "addB",             { Gb, EbS }, 0 },
2596   { "addS",             { Gv, EvS }, 0 },
2597   { "addB",             { AL, Ib }, 0 },
2598   { "addS",             { eAX, Iv }, 0 },
2599   { X86_64_TABLE (X86_64_06) },
2600   { X86_64_TABLE (X86_64_07) },
2601   /* 08 */
2602   { "orB",              { Ebh1, Gb }, 0 },
2603   { "orS",              { Evh1, Gv }, 0 },
2604   { "orB",              { Gb, EbS }, 0 },
2605   { "orS",              { Gv, EvS }, 0 },
2606   { "orB",              { AL, Ib }, 0 },
2607   { "orS",              { eAX, Iv }, 0 },
2608   { X86_64_TABLE (X86_64_0D) },
2609   { Bad_Opcode },       /* 0x0f extended opcode escape */
2610   /* 10 */
2611   { "adcB",             { Ebh1, Gb }, 0 },
2612   { "adcS",             { Evh1, Gv }, 0 },
2613   { "adcB",             { Gb, EbS }, 0 },
2614   { "adcS",             { Gv, EvS }, 0 },
2615   { "adcB",             { AL, Ib }, 0 },
2616   { "adcS",             { eAX, Iv }, 0 },
2617   { X86_64_TABLE (X86_64_16) },
2618   { X86_64_TABLE (X86_64_17) },
2619   /* 18 */
2620   { "sbbB",             { Ebh1, Gb }, 0 },
2621   { "sbbS",             { Evh1, Gv }, 0 },
2622   { "sbbB",             { Gb, EbS }, 0 },
2623   { "sbbS",             { Gv, EvS }, 0 },
2624   { "sbbB",             { AL, Ib }, 0 },
2625   { "sbbS",             { eAX, Iv }, 0 },
2626   { X86_64_TABLE (X86_64_1E) },
2627   { X86_64_TABLE (X86_64_1F) },
2628   /* 20 */
2629   { "andB",             { Ebh1, Gb }, 0 },
2630   { "andS",             { Evh1, Gv }, 0 },
2631   { "andB",             { Gb, EbS }, 0 },
2632   { "andS",             { Gv, EvS }, 0 },
2633   { "andB",             { AL, Ib }, 0 },
2634   { "andS",             { eAX, Iv }, 0 },
2635   { Bad_Opcode },       /* SEG ES prefix */
2636   { X86_64_TABLE (X86_64_27) },
2637   /* 28 */
2638   { "subB",             { Ebh1, Gb }, 0 },
2639   { "subS",             { Evh1, Gv }, 0 },
2640   { "subB",             { Gb, EbS }, 0 },
2641   { "subS",             { Gv, EvS }, 0 },
2642   { "subB",             { AL, Ib }, 0 },
2643   { "subS",             { eAX, Iv }, 0 },
2644   { Bad_Opcode },       /* SEG CS prefix */
2645   { X86_64_TABLE (X86_64_2F) },
2646   /* 30 */
2647   { "xorB",             { Ebh1, Gb }, 0 },
2648   { "xorS",             { Evh1, Gv }, 0 },
2649   { "xorB",             { Gb, EbS }, 0 },
2650   { "xorS",             { Gv, EvS }, 0 },
2651   { "xorB",             { AL, Ib }, 0 },
2652   { "xorS",             { eAX, Iv }, 0 },
2653   { Bad_Opcode },       /* SEG SS prefix */
2654   { X86_64_TABLE (X86_64_37) },
2655   /* 38 */
2656   { "cmpB",             { Eb, Gb }, 0 },
2657   { "cmpS",             { Ev, Gv }, 0 },
2658   { "cmpB",             { Gb, EbS }, 0 },
2659   { "cmpS",             { Gv, EvS }, 0 },
2660   { "cmpB",             { AL, Ib }, 0 },
2661   { "cmpS",             { eAX, Iv }, 0 },
2662   { Bad_Opcode },       /* SEG DS prefix */
2663   { X86_64_TABLE (X86_64_3F) },
2664   /* 40 */
2665   { "inc{S|}",          { RMeAX }, 0 },
2666   { "inc{S|}",          { RMeCX }, 0 },
2667   { "inc{S|}",          { RMeDX }, 0 },
2668   { "inc{S|}",          { RMeBX }, 0 },
2669   { "inc{S|}",          { RMeSP }, 0 },
2670   { "inc{S|}",          { RMeBP }, 0 },
2671   { "inc{S|}",          { RMeSI }, 0 },
2672   { "inc{S|}",          { RMeDI }, 0 },
2673   /* 48 */
2674   { "dec{S|}",          { RMeAX }, 0 },
2675   { "dec{S|}",          { RMeCX }, 0 },
2676   { "dec{S|}",          { RMeDX }, 0 },
2677   { "dec{S|}",          { RMeBX }, 0 },
2678   { "dec{S|}",          { RMeSP }, 0 },
2679   { "dec{S|}",          { RMeBP }, 0 },
2680   { "dec{S|}",          { RMeSI }, 0 },
2681   { "dec{S|}",          { RMeDI }, 0 },
2682   /* 50 */
2683   { "pushV",            { RMrAX }, 0 },
2684   { "pushV",            { RMrCX }, 0 },
2685   { "pushV",            { RMrDX }, 0 },
2686   { "pushV",            { RMrBX }, 0 },
2687   { "pushV",            { RMrSP }, 0 },
2688   { "pushV",            { RMrBP }, 0 },
2689   { "pushV",            { RMrSI }, 0 },
2690   { "pushV",            { RMrDI }, 0 },
2691   /* 58 */
2692   { "popV",             { RMrAX }, 0 },
2693   { "popV",             { RMrCX }, 0 },
2694   { "popV",             { RMrDX }, 0 },
2695   { "popV",             { RMrBX }, 0 },
2696   { "popV",             { RMrSP }, 0 },
2697   { "popV",             { RMrBP }, 0 },
2698   { "popV",             { RMrSI }, 0 },
2699   { "popV",             { RMrDI }, 0 },
2700   /* 60 */
2701   { X86_64_TABLE (X86_64_60) },
2702   { X86_64_TABLE (X86_64_61) },
2703   { X86_64_TABLE (X86_64_62) },
2704   { X86_64_TABLE (X86_64_63) },
2705   { Bad_Opcode },       /* seg fs */
2706   { Bad_Opcode },       /* seg gs */
2707   { Bad_Opcode },       /* op size prefix */
2708   { Bad_Opcode },       /* adr size prefix */
2709   /* 68 */
2710   { "pushT",            { sIv }, 0 },
2711   { "imulS",            { Gv, Ev, Iv }, 0 },
2712   { "pushT",            { sIbT }, 0 },
2713   { "imulS",            { Gv, Ev, sIb }, 0 },
2714   { "ins{b|}",          { Ybr, indirDX }, 0 },
2715   { X86_64_TABLE (X86_64_6D) },
2716   { "outs{b|}",         { indirDXr, Xb }, 0 },
2717   { X86_64_TABLE (X86_64_6F) },
2718   /* 70 */
2719   { "joH",              { Jb, BND, cond_jump_flag }, 0 },
2720   { "jnoH",             { Jb, BND, cond_jump_flag }, 0 },
2721   { "jbH",              { Jb, BND, cond_jump_flag }, 0 },
2722   { "jaeH",             { Jb, BND, cond_jump_flag }, 0 },
2723   { "jeH",              { Jb, BND, cond_jump_flag }, 0 },
2724   { "jneH",             { Jb, BND, cond_jump_flag }, 0 },
2725   { "jbeH",             { Jb, BND, cond_jump_flag }, 0 },
2726   { "jaH",              { Jb, BND, cond_jump_flag }, 0 },
2727   /* 78 */
2728   { "jsH",              { Jb, BND, cond_jump_flag }, 0 },
2729   { "jnsH",             { Jb, BND, cond_jump_flag }, 0 },
2730   { "jpH",              { Jb, BND, cond_jump_flag }, 0 },
2731   { "jnpH",             { Jb, BND, cond_jump_flag }, 0 },
2732   { "jlH",              { Jb, BND, cond_jump_flag }, 0 },
2733   { "jgeH",             { Jb, BND, cond_jump_flag }, 0 },
2734   { "jleH",             { Jb, BND, cond_jump_flag }, 0 },
2735   { "jgH",              { Jb, BND, cond_jump_flag }, 0 },
2736   /* 80 */
2737   { REG_TABLE (REG_80) },
2738   { REG_TABLE (REG_81) },
2739   { X86_64_TABLE (X86_64_82) },
2740   { REG_TABLE (REG_83) },
2741   { "testB",            { Eb, Gb }, 0 },
2742   { "testS",            { Ev, Gv }, 0 },
2743   { "xchgB",            { Ebh2, Gb }, 0 },
2744   { "xchgS",            { Evh2, Gv }, 0 },
2745   /* 88 */
2746   { "movB",             { Ebh3, Gb }, 0 },
2747   { "movS",             { Evh3, Gv }, 0 },
2748   { "movB",             { Gb, EbS }, 0 },
2749   { "movS",             { Gv, EvS }, 0 },
2750   { "movD",             { Sv, Sw }, 0 },
2751   { MOD_TABLE (MOD_8D) },
2752   { "movD",             { Sw, Sv }, 0 },
2753   { REG_TABLE (REG_8F) },
2754   /* 90 */
2755   { PREFIX_TABLE (PREFIX_90) },
2756   { "xchgS",            { RMeCX, eAX }, 0 },
2757   { "xchgS",            { RMeDX, eAX }, 0 },
2758   { "xchgS",            { RMeBX, eAX }, 0 },
2759   { "xchgS",            { RMeSP, eAX }, 0 },
2760   { "xchgS",            { RMeBP, eAX }, 0 },
2761   { "xchgS",            { RMeSI, eAX }, 0 },
2762   { "xchgS",            { RMeDI, eAX }, 0 },
2763   /* 98 */
2764   { "cW{t|}R",          { XX }, 0 },
2765   { "cR{t|}O",          { XX }, 0 },
2766   { X86_64_TABLE (X86_64_9A) },
2767   { Bad_Opcode },       /* fwait */
2768   { "pushfT",           { XX }, 0 },
2769   { "popfT",            { XX }, 0 },
2770   { "sahf",             { XX }, 0 },
2771   { "lahf",             { XX }, 0 },
2772   /* a0 */
2773   { "mov%LB",           { AL, Ob }, 0 },
2774   { "mov%LS",           { eAX, Ov }, 0 },
2775   { "mov%LB",           { Ob, AL }, 0 },
2776   { "mov%LS",           { Ov, eAX }, 0 },
2777   { "movs{b|}",         { Ybr, Xb }, 0 },
2778   { "movs{R|}",         { Yvr, Xv }, 0 },
2779   { "cmps{b|}",         { Xb, Yb }, 0 },
2780   { "cmps{R|}",         { Xv, Yv }, 0 },
2781   /* a8 */
2782   { "testB",            { AL, Ib }, 0 },
2783   { "testS",            { eAX, Iv }, 0 },
2784   { "stosB",            { Ybr, AL }, 0 },
2785   { "stosS",            { Yvr, eAX }, 0 },
2786   { "lodsB",            { ALr, Xb }, 0 },
2787   { "lodsS",            { eAXr, Xv }, 0 },
2788   { "scasB",            { AL, Yb }, 0 },
2789   { "scasS",            { eAX, Yv }, 0 },
2790   /* b0 */
2791   { "movB",             { RMAL, Ib }, 0 },
2792   { "movB",             { RMCL, Ib }, 0 },
2793   { "movB",             { RMDL, Ib }, 0 },
2794   { "movB",             { RMBL, Ib }, 0 },
2795   { "movB",             { RMAH, Ib }, 0 },
2796   { "movB",             { RMCH, Ib }, 0 },
2797   { "movB",             { RMDH, Ib }, 0 },
2798   { "movB",             { RMBH, Ib }, 0 },
2799   /* b8 */
2800   { "mov%LV",           { RMeAX, Iv64 }, 0 },
2801   { "mov%LV",           { RMeCX, Iv64 }, 0 },
2802   { "mov%LV",           { RMeDX, Iv64 }, 0 },
2803   { "mov%LV",           { RMeBX, Iv64 }, 0 },
2804   { "mov%LV",           { RMeSP, Iv64 }, 0 },
2805   { "mov%LV",           { RMeBP, Iv64 }, 0 },
2806   { "mov%LV",           { RMeSI, Iv64 }, 0 },
2807   { "mov%LV",           { RMeDI, Iv64 }, 0 },
2808   /* c0 */
2809   { REG_TABLE (REG_C0) },
2810   { REG_TABLE (REG_C1) },
2811   { "retT",             { Iw, BND }, 0 },
2812   { "retT",             { BND }, 0 },
2813   { X86_64_TABLE (X86_64_C4) },
2814   { X86_64_TABLE (X86_64_C5) },
2815   { REG_TABLE (REG_C6) },
2816   { REG_TABLE (REG_C7) },
2817   /* c8 */
2818   { "enterT",           { Iw, Ib }, 0 },
2819   { "leaveT",           { XX }, 0 },
2820   { "Jret{|f}P",        { Iw }, 0 },
2821   { "Jret{|f}P",        { XX }, 0 },
2822   { "int3",             { XX }, 0 },
2823   { "int",              { Ib }, 0 },
2824   { X86_64_TABLE (X86_64_CE) },
2825   { "iret%LP",          { XX }, 0 },
2826   /* d0 */
2827   { REG_TABLE (REG_D0) },
2828   { REG_TABLE (REG_D1) },
2829   { REG_TABLE (REG_D2) },
2830   { REG_TABLE (REG_D3) },
2831   { X86_64_TABLE (X86_64_D4) },
2832   { X86_64_TABLE (X86_64_D5) },
2833   { Bad_Opcode },
2834   { "xlat",             { DSBX }, 0 },
2835   /* d8 */
2836   { FLOAT },
2837   { FLOAT },
2838   { FLOAT },
2839   { FLOAT },
2840   { FLOAT },
2841   { FLOAT },
2842   { FLOAT },
2843   { FLOAT },
2844   /* e0 */
2845   { "loopneFH",         { Jb, XX, loop_jcxz_flag }, 0 },
2846   { "loopeFH",          { Jb, XX, loop_jcxz_flag }, 0 },
2847   { "loopFH",           { Jb, XX, loop_jcxz_flag }, 0 },
2848   { "jEcxzH",           { Jb, XX, loop_jcxz_flag }, 0 },
2849   { "inB",              { AL, Ib }, 0 },
2850   { "inG",              { zAX, Ib }, 0 },
2851   { "outB",             { Ib, AL }, 0 },
2852   { "outG",             { Ib, zAX }, 0 },
2853   /* e8 */
2854   { X86_64_TABLE (X86_64_E8) },
2855   { X86_64_TABLE (X86_64_E9) },
2856   { X86_64_TABLE (X86_64_EA) },
2857   { "jmp",              { Jb, BND }, 0 },
2858   { "inB",              { AL, indirDX }, 0 },
2859   { "inG",              { zAX, indirDX }, 0 },
2860   { "outB",             { indirDX, AL }, 0 },
2861   { "outG",             { indirDX, zAX }, 0 },
2862   /* f0 */
2863   { Bad_Opcode },       /* lock prefix */
2864   { "icebp",            { XX }, 0 },
2865   { Bad_Opcode },       /* repne */
2866   { Bad_Opcode },       /* repz */
2867   { "hlt",              { XX }, 0 },
2868   { "cmc",              { XX }, 0 },
2869   { REG_TABLE (REG_F6) },
2870   { REG_TABLE (REG_F7) },
2871   /* f8 */
2872   { "clc",              { XX }, 0 },
2873   { "stc",              { XX }, 0 },
2874   { "cli",              { XX }, 0 },
2875   { "sti",              { XX }, 0 },
2876   { "cld",              { XX }, 0 },
2877   { "std",              { XX }, 0 },
2878   { REG_TABLE (REG_FE) },
2879   { REG_TABLE (REG_FF) },
2880 };
2881
2882 static const struct dis386 dis386_twobyte[] = {
2883   /* 00 */
2884   { REG_TABLE (REG_0F00 ) },
2885   { REG_TABLE (REG_0F01 ) },
2886   { "larS",             { Gv, Ew }, 0 },
2887   { "lslS",             { Gv, Ew }, 0 },
2888   { Bad_Opcode },
2889   { "syscall",          { XX }, 0 },
2890   { "clts",             { XX }, 0 },
2891   { "sysret%LP",                { XX }, 0 },
2892   /* 08 */
2893   { "invd",             { XX }, 0 },
2894   { PREFIX_TABLE (PREFIX_0F09) },
2895   { Bad_Opcode },
2896   { "ud2",              { XX }, 0 },
2897   { Bad_Opcode },
2898   { REG_TABLE (REG_0F0D) },
2899   { "femms",            { XX }, 0 },
2900   { "",                 { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix.  */
2901   /* 10 */
2902   { PREFIX_TABLE (PREFIX_0F10) },
2903   { PREFIX_TABLE (PREFIX_0F11) },
2904   { PREFIX_TABLE (PREFIX_0F12) },
2905   { MOD_TABLE (MOD_0F13) },
2906   { "unpcklpX",         { XM, EXx }, PREFIX_OPCODE },
2907   { "unpckhpX",         { XM, EXx }, PREFIX_OPCODE },
2908   { PREFIX_TABLE (PREFIX_0F16) },
2909   { MOD_TABLE (MOD_0F17) },
2910   /* 18 */
2911   { REG_TABLE (REG_0F18) },
2912   { "nopQ",             { Ev }, 0 },
2913   { PREFIX_TABLE (PREFIX_0F1A) },
2914   { PREFIX_TABLE (PREFIX_0F1B) },
2915   { PREFIX_TABLE (PREFIX_0F1C) },
2916   { "nopQ",             { Ev }, 0 },
2917   { PREFIX_TABLE (PREFIX_0F1E) },
2918   { "nopQ",             { Ev }, 0 },
2919   /* 20 */
2920   { "movZ",             { Rm, Cm }, 0 },
2921   { "movZ",             { Rm, Dm }, 0 },
2922   { "movZ",             { Cm, Rm }, 0 },
2923   { "movZ",             { Dm, Rm }, 0 },
2924   { MOD_TABLE (MOD_0F24) },
2925   { Bad_Opcode },
2926   { MOD_TABLE (MOD_0F26) },
2927   { Bad_Opcode },
2928   /* 28 */
2929   { "movapX",           { XM, EXx }, PREFIX_OPCODE },
2930   { "movapX",           { EXxS, XM }, PREFIX_OPCODE },
2931   { PREFIX_TABLE (PREFIX_0F2A) },
2932   { PREFIX_TABLE (PREFIX_0F2B) },
2933   { PREFIX_TABLE (PREFIX_0F2C) },
2934   { PREFIX_TABLE (PREFIX_0F2D) },
2935   { PREFIX_TABLE (PREFIX_0F2E) },
2936   { PREFIX_TABLE (PREFIX_0F2F) },
2937   /* 30 */
2938   { "wrmsr",            { XX }, 0 },
2939   { "rdtsc",            { XX }, 0 },
2940   { "rdmsr",            { XX }, 0 },
2941   { "rdpmc",            { XX }, 0 },
2942   { "sysenter",         { XX }, 0 },
2943   { "sysexit",          { XX }, 0 },
2944   { Bad_Opcode },
2945   { "getsec",           { XX }, 0 },
2946   /* 38 */
2947   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2948   { Bad_Opcode },
2949   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2950   { Bad_Opcode },
2951   { Bad_Opcode },
2952   { Bad_Opcode },
2953   { Bad_Opcode },
2954   { Bad_Opcode },
2955   /* 40 */
2956   { "cmovoS",           { Gv, Ev }, 0 },
2957   { "cmovnoS",          { Gv, Ev }, 0 },
2958   { "cmovbS",           { Gv, Ev }, 0 },
2959   { "cmovaeS",          { Gv, Ev }, 0 },
2960   { "cmoveS",           { Gv, Ev }, 0 },
2961   { "cmovneS",          { Gv, Ev }, 0 },
2962   { "cmovbeS",          { Gv, Ev }, 0 },
2963   { "cmovaS",           { Gv, Ev }, 0 },
2964   /* 48 */
2965   { "cmovsS",           { Gv, Ev }, 0 },
2966   { "cmovnsS",          { Gv, Ev }, 0 },
2967   { "cmovpS",           { Gv, Ev }, 0 },
2968   { "cmovnpS",          { Gv, Ev }, 0 },
2969   { "cmovlS",           { Gv, Ev }, 0 },
2970   { "cmovgeS",          { Gv, Ev }, 0 },
2971   { "cmovleS",          { Gv, Ev }, 0 },
2972   { "cmovgS",           { Gv, Ev }, 0 },
2973   /* 50 */
2974   { MOD_TABLE (MOD_0F51) },
2975   { PREFIX_TABLE (PREFIX_0F51) },
2976   { PREFIX_TABLE (PREFIX_0F52) },
2977   { PREFIX_TABLE (PREFIX_0F53) },
2978   { "andpX",            { XM, EXx }, PREFIX_OPCODE },
2979   { "andnpX",           { XM, EXx }, PREFIX_OPCODE },
2980   { "orpX",             { XM, EXx }, PREFIX_OPCODE },
2981   { "xorpX",            { XM, EXx }, PREFIX_OPCODE },
2982   /* 58 */
2983   { PREFIX_TABLE (PREFIX_0F58) },
2984   { PREFIX_TABLE (PREFIX_0F59) },
2985   { PREFIX_TABLE (PREFIX_0F5A) },
2986   { PREFIX_TABLE (PREFIX_0F5B) },
2987   { PREFIX_TABLE (PREFIX_0F5C) },
2988   { PREFIX_TABLE (PREFIX_0F5D) },
2989   { PREFIX_TABLE (PREFIX_0F5E) },
2990   { PREFIX_TABLE (PREFIX_0F5F) },
2991   /* 60 */
2992   { PREFIX_TABLE (PREFIX_0F60) },
2993   { PREFIX_TABLE (PREFIX_0F61) },
2994   { PREFIX_TABLE (PREFIX_0F62) },
2995   { "packsswb",         { MX, EM }, PREFIX_OPCODE },
2996   { "pcmpgtb",          { MX, EM }, PREFIX_OPCODE },
2997   { "pcmpgtw",          { MX, EM }, PREFIX_OPCODE },
2998   { "pcmpgtd",          { MX, EM }, PREFIX_OPCODE },
2999   { "packuswb",         { MX, EM }, PREFIX_OPCODE },
3000   /* 68 */
3001   { "punpckhbw",        { MX, EM }, PREFIX_OPCODE },
3002   { "punpckhwd",        { MX, EM }, PREFIX_OPCODE },
3003   { "punpckhdq",        { MX, EM }, PREFIX_OPCODE },
3004   { "packssdw",         { MX, EM }, PREFIX_OPCODE },
3005   { PREFIX_TABLE (PREFIX_0F6C) },
3006   { PREFIX_TABLE (PREFIX_0F6D) },
3007   { "movK",             { MX, Edq }, PREFIX_OPCODE },
3008   { PREFIX_TABLE (PREFIX_0F6F) },
3009   /* 70 */
3010   { PREFIX_TABLE (PREFIX_0F70) },
3011   { REG_TABLE (REG_0F71) },
3012   { REG_TABLE (REG_0F72) },
3013   { REG_TABLE (REG_0F73) },
3014   { "pcmpeqb",          { MX, EM }, PREFIX_OPCODE },
3015   { "pcmpeqw",          { MX, EM }, PREFIX_OPCODE },
3016   { "pcmpeqd",          { MX, EM }, PREFIX_OPCODE },
3017   { "emms",             { XX }, PREFIX_OPCODE },
3018   /* 78 */
3019   { PREFIX_TABLE (PREFIX_0F78) },
3020   { PREFIX_TABLE (PREFIX_0F79) },
3021   { Bad_Opcode },
3022   { Bad_Opcode },
3023   { PREFIX_TABLE (PREFIX_0F7C) },
3024   { PREFIX_TABLE (PREFIX_0F7D) },
3025   { PREFIX_TABLE (PREFIX_0F7E) },
3026   { PREFIX_TABLE (PREFIX_0F7F) },
3027   /* 80 */
3028   { "joH",              { Jv, BND, cond_jump_flag }, 0 },
3029   { "jnoH",             { Jv, BND, cond_jump_flag }, 0 },
3030   { "jbH",              { Jv, BND, cond_jump_flag }, 0 },
3031   { "jaeH",             { Jv, BND, cond_jump_flag }, 0 },
3032   { "jeH",              { Jv, BND, cond_jump_flag }, 0 },
3033   { "jneH",             { Jv, BND, cond_jump_flag }, 0 },
3034   { "jbeH",             { Jv, BND, cond_jump_flag }, 0 },
3035   { "jaH",              { Jv, BND, cond_jump_flag }, 0 },
3036   /* 88 */
3037   { "jsH",              { Jv, BND, cond_jump_flag }, 0 },
3038   { "jnsH",             { Jv, BND, cond_jump_flag }, 0 },
3039   { "jpH",              { Jv, BND, cond_jump_flag }, 0 },
3040   { "jnpH",             { Jv, BND, cond_jump_flag }, 0 },
3041   { "jlH",              { Jv, BND, cond_jump_flag }, 0 },
3042   { "jgeH",             { Jv, BND, cond_jump_flag }, 0 },
3043   { "jleH",             { Jv, BND, cond_jump_flag }, 0 },
3044   { "jgH",              { Jv, BND, cond_jump_flag }, 0 },
3045   /* 90 */
3046   { "seto",             { Eb }, 0 },
3047   { "setno",            { Eb }, 0 },
3048   { "setb",             { Eb }, 0 },
3049   { "setae",            { Eb }, 0 },
3050   { "sete",             { Eb }, 0 },
3051   { "setne",            { Eb }, 0 },
3052   { "setbe",            { Eb }, 0 },
3053   { "seta",             { Eb }, 0 },
3054   /* 98 */
3055   { "sets",             { Eb }, 0 },
3056   { "setns",            { Eb }, 0 },
3057   { "setp",             { Eb }, 0 },
3058   { "setnp",            { Eb }, 0 },
3059   { "setl",             { Eb }, 0 },
3060   { "setge",            { Eb }, 0 },
3061   { "setle",            { Eb }, 0 },
3062   { "setg",             { Eb }, 0 },
3063   /* a0 */
3064   { "pushT",            { fs }, 0 },
3065   { "popT",             { fs }, 0 },
3066   { "cpuid",            { XX }, 0 },
3067   { "btS",              { Ev, Gv }, 0 },
3068   { "shldS",            { Ev, Gv, Ib }, 0 },
3069   { "shldS",            { Ev, Gv, CL }, 0 },
3070   { REG_TABLE (REG_0FA6) },
3071   { REG_TABLE (REG_0FA7) },
3072   /* a8 */
3073   { "pushT",            { gs }, 0 },
3074   { "popT",             { gs }, 0 },
3075   { "rsm",              { XX }, 0 },
3076   { "btsS",             { Evh1, Gv }, 0 },
3077   { "shrdS",            { Ev, Gv, Ib }, 0 },
3078   { "shrdS",            { Ev, Gv, CL }, 0 },
3079   { REG_TABLE (REG_0FAE) },
3080   { "imulS",            { Gv, Ev }, 0 },
3081   /* b0 */
3082   { "cmpxchgB",         { Ebh1, Gb }, 0 },
3083   { "cmpxchgS",         { Evh1, Gv }, 0 },
3084   { MOD_TABLE (MOD_0FB2) },
3085   { "btrS",             { Evh1, Gv }, 0 },
3086   { MOD_TABLE (MOD_0FB4) },
3087   { MOD_TABLE (MOD_0FB5) },
3088   { "movz{bR|x}",       { Gv, Eb }, 0 },
3089   { "movz{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
3090   /* b8 */
3091   { PREFIX_TABLE (PREFIX_0FB8) },
3092   { "ud1S",             { Gv, Ev }, 0 },
3093   { REG_TABLE (REG_0FBA) },
3094   { "btcS",             { Evh1, Gv }, 0 },
3095   { PREFIX_TABLE (PREFIX_0FBC) },
3096   { PREFIX_TABLE (PREFIX_0FBD) },
3097   { "movs{bR|x}",       { Gv, Eb }, 0 },
3098   { "movs{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
3099   /* c0 */
3100   { "xaddB",            { Ebh1, Gb }, 0 },
3101   { "xaddS",            { Evh1, Gv }, 0 },
3102   { PREFIX_TABLE (PREFIX_0FC2) },
3103   { MOD_TABLE (MOD_0FC3) },
3104   { "pinsrw",           { MX, Edqw, Ib }, PREFIX_OPCODE },
3105   { "pextrw",           { Gdq, MS, Ib }, PREFIX_OPCODE },
3106   { "shufpX",           { XM, EXx, Ib }, PREFIX_OPCODE },
3107   { REG_TABLE (REG_0FC7) },
3108   /* c8 */
3109   { "bswap",            { RMeAX }, 0 },
3110   { "bswap",            { RMeCX }, 0 },
3111   { "bswap",            { RMeDX }, 0 },
3112   { "bswap",            { RMeBX }, 0 },
3113   { "bswap",            { RMeSP }, 0 },
3114   { "bswap",            { RMeBP }, 0 },
3115   { "bswap",            { RMeSI }, 0 },
3116   { "bswap",            { RMeDI }, 0 },
3117   /* d0 */
3118   { PREFIX_TABLE (PREFIX_0FD0) },
3119   { "psrlw",            { MX, EM }, PREFIX_OPCODE },
3120   { "psrld",            { MX, EM }, PREFIX_OPCODE },
3121   { "psrlq",            { MX, EM }, PREFIX_OPCODE },
3122   { "paddq",            { MX, EM }, PREFIX_OPCODE },
3123   { "pmullw",           { MX, EM }, PREFIX_OPCODE },
3124   { PREFIX_TABLE (PREFIX_0FD6) },
3125   { MOD_TABLE (MOD_0FD7) },
3126   /* d8 */
3127   { "psubusb",          { MX, EM }, PREFIX_OPCODE },
3128   { "psubusw",          { MX, EM }, PREFIX_OPCODE },
3129   { "pminub",           { MX, EM }, PREFIX_OPCODE },
3130   { "pand",             { MX, EM }, PREFIX_OPCODE },
3131   { "paddusb",          { MX, EM }, PREFIX_OPCODE },
3132   { "paddusw",          { MX, EM }, PREFIX_OPCODE },
3133   { "pmaxub",           { MX, EM }, PREFIX_OPCODE },
3134   { "pandn",            { MX, EM }, PREFIX_OPCODE },
3135   /* e0 */
3136   { "pavgb",            { MX, EM }, PREFIX_OPCODE },
3137   { "psraw",            { MX, EM }, PREFIX_OPCODE },
3138   { "psrad",            { MX, EM }, PREFIX_OPCODE },
3139   { "pavgw",            { MX, EM }, PREFIX_OPCODE },
3140   { "pmulhuw",          { MX, EM }, PREFIX_OPCODE },
3141   { "pmulhw",           { MX, EM }, PREFIX_OPCODE },
3142   { PREFIX_TABLE (PREFIX_0FE6) },
3143   { PREFIX_TABLE (PREFIX_0FE7) },
3144   /* e8 */
3145   { "psubsb",           { MX, EM }, PREFIX_OPCODE },
3146   { "psubsw",           { MX, EM }, PREFIX_OPCODE },
3147   { "pminsw",           { MX, EM }, PREFIX_OPCODE },
3148   { "por",              { MX, EM }, PREFIX_OPCODE },
3149   { "paddsb",           { MX, EM }, PREFIX_OPCODE },
3150   { "paddsw",           { MX, EM }, PREFIX_OPCODE },
3151   { "pmaxsw",           { MX, EM }, PREFIX_OPCODE },
3152   { "pxor",             { MX, EM }, PREFIX_OPCODE },
3153   /* f0 */
3154   { PREFIX_TABLE (PREFIX_0FF0) },
3155   { "psllw",            { MX, EM }, PREFIX_OPCODE },
3156   { "pslld",            { MX, EM }, PREFIX_OPCODE },
3157   { "psllq",            { MX, EM }, PREFIX_OPCODE },
3158   { "pmuludq",          { MX, EM }, PREFIX_OPCODE },
3159   { "pmaddwd",          { MX, EM }, PREFIX_OPCODE },
3160   { "psadbw",           { MX, EM }, PREFIX_OPCODE },
3161   { PREFIX_TABLE (PREFIX_0FF7) },
3162   /* f8 */
3163   { "psubb",            { MX, EM }, PREFIX_OPCODE },
3164   { "psubw",            { MX, EM }, PREFIX_OPCODE },
3165   { "psubd",            { MX, EM }, PREFIX_OPCODE },
3166   { "psubq",            { MX, EM }, PREFIX_OPCODE },
3167   { "paddb",            { MX, EM }, PREFIX_OPCODE },
3168   { "paddw",            { MX, EM }, PREFIX_OPCODE },
3169   { "paddd",            { MX, EM }, PREFIX_OPCODE },
3170   { "ud0S",             { Gv, Ev }, 0 },
3171 };
3172
3173 static const unsigned char onebyte_has_modrm[256] = {
3174   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3175   /*       -------------------------------        */
3176   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
3177   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
3178   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
3179   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
3180   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
3181   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
3182   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
3183   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
3184   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
3185   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
3186   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
3187   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
3188   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
3189   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
3190   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
3191   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
3192   /*       -------------------------------        */
3193   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3194 };
3195
3196 static const unsigned char twobyte_has_modrm[256] = {
3197   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3198   /*       -------------------------------        */
3199   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
3200   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
3201   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
3202   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
3203   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
3204   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
3205   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
3206   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
3207   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
3208   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
3209   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
3210   /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
3211   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
3212   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
3213   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
3214   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1  /* ff */
3215   /*       -------------------------------        */
3216   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3217 };
3218
3219 static char obuf[100];
3220 static char *obufp;
3221 static char *mnemonicendp;
3222 static char scratchbuf[100];
3223 static unsigned char *start_codep;
3224 static unsigned char *insn_codep;
3225 static unsigned char *codep;
3226 static unsigned char *end_codep;
3227 static int last_lock_prefix;
3228 static int last_repz_prefix;
3229 static int last_repnz_prefix;
3230 static int last_data_prefix;
3231 static int last_addr_prefix;
3232 static int last_rex_prefix;
3233 static int last_seg_prefix;
3234 static int fwait_prefix;
3235 /* The active segment register prefix.  */
3236 static int active_seg_prefix;
3237 #define MAX_CODE_LENGTH 15
3238 /* We can up to 14 prefixes since the maximum instruction length is
3239    15bytes.  */
3240 static int all_prefixes[MAX_CODE_LENGTH - 1];
3241 static disassemble_info *the_info;
3242 static struct
3243   {
3244     int mod;
3245     int reg;
3246     int rm;
3247   }
3248 modrm;
3249 static unsigned char need_modrm;
3250 static struct
3251   {
3252     int scale;
3253     int index;
3254     int base;
3255   }
3256 sib;
3257 static struct
3258   {
3259     int register_specifier;
3260     int length;
3261     int prefix;
3262     int w;
3263     int evex;
3264     int r;
3265     int v;
3266     int mask_register_specifier;
3267     int zeroing;
3268     int ll;
3269     int b;
3270   }
3271 vex;
3272 static unsigned char need_vex;
3273 static unsigned char need_vex_reg;
3274 static unsigned char vex_w_done;
3275
3276 struct op
3277   {
3278     const char *name;
3279     unsigned int len;
3280   };
3281
3282 /* If we are accessing mod/rm/reg without need_modrm set, then the
3283    values are stale.  Hitting this abort likely indicates that you
3284    need to update onebyte_has_modrm or twobyte_has_modrm.  */
3285 #define MODRM_CHECK  if (!need_modrm) abort ()
3286
3287 static const char **names64;
3288 static const char **names32;
3289 static const char **names16;
3290 static const char **names8;
3291 static const char **names8rex;
3292 static const char **names_seg;
3293 static const char *index64;
3294 static const char *index32;
3295 static const char **index16;
3296 static const char **names_bnd;
3297
3298 static const char *intel_names64[] = {
3299   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3300   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3301 };
3302 static const char *intel_names32[] = {
3303   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3304   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3305 };
3306 static const char *intel_names16[] = {
3307   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3308   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3309 };
3310 static const char *intel_names8[] = {
3311   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3312 };
3313 static const char *intel_names8rex[] = {
3314   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3315   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3316 };
3317 static const char *intel_names_seg[] = {
3318   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3319 };
3320 static const char *intel_index64 = "riz";
3321 static const char *intel_index32 = "eiz";
3322 static const char *intel_index16[] = {
3323   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3324 };
3325
3326 static const char *att_names64[] = {
3327   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3328   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3329 };
3330 static const char *att_names32[] = {
3331   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3332   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3333 };
3334 static const char *att_names16[] = {
3335   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3336   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3337 };
3338 static const char *att_names8[] = {
3339   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3340 };
3341 static const char *att_names8rex[] = {
3342   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3343   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3344 };
3345 static const char *att_names_seg[] = {
3346   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3347 };
3348 static const char *att_index64 = "%riz";
3349 static const char *att_index32 = "%eiz";
3350 static const char *att_index16[] = {
3351   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3352 };
3353
3354 static const char **names_mm;
3355 static const char *intel_names_mm[] = {
3356   "mm0", "mm1", "mm2", "mm3",
3357   "mm4", "mm5", "mm6", "mm7"
3358 };
3359 static const char *att_names_mm[] = {
3360   "%mm0", "%mm1", "%mm2", "%mm3",
3361   "%mm4", "%mm5", "%mm6", "%mm7"
3362 };
3363
3364 static const char *intel_names_bnd[] = {
3365   "bnd0", "bnd1", "bnd2", "bnd3"
3366 };
3367
3368 static const char *att_names_bnd[] = {
3369   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3370 };
3371
3372 static const char **names_xmm;
3373 static const char *intel_names_xmm[] = {
3374   "xmm0", "xmm1", "xmm2", "xmm3",
3375   "xmm4", "xmm5", "xmm6", "xmm7",
3376   "xmm8", "xmm9", "xmm10", "xmm11",
3377   "xmm12", "xmm13", "xmm14", "xmm15",
3378   "xmm16", "xmm17", "xmm18", "xmm19",
3379   "xmm20", "xmm21", "xmm22", "xmm23",
3380   "xmm24", "xmm25", "xmm26", "xmm27",
3381   "xmm28", "xmm29", "xmm30", "xmm31"
3382 };
3383 static const char *att_names_xmm[] = {
3384   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3385   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3386   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3387   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3388   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3389   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3390   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3391   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3392 };
3393
3394 static const char **names_ymm;
3395 static const char *intel_names_ymm[] = {
3396   "ymm0", "ymm1", "ymm2", "ymm3",
3397   "ymm4", "ymm5", "ymm6", "ymm7",
3398   "ymm8", "ymm9", "ymm10", "ymm11",
3399   "ymm12", "ymm13", "ymm14", "ymm15",
3400   "ymm16", "ymm17", "ymm18", "ymm19",
3401   "ymm20", "ymm21", "ymm22", "ymm23",
3402   "ymm24", "ymm25", "ymm26", "ymm27",
3403   "ymm28", "ymm29", "ymm30", "ymm31"
3404 };
3405 static const char *att_names_ymm[] = {
3406   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3407   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3408   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3409   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3410   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3411   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3412   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3413   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3414 };
3415
3416 static const char **names_zmm;
3417 static const char *intel_names_zmm[] = {
3418   "zmm0", "zmm1", "zmm2", "zmm3",
3419   "zmm4", "zmm5", "zmm6", "zmm7",
3420   "zmm8", "zmm9", "zmm10", "zmm11",
3421   "zmm12", "zmm13", "zmm14", "zmm15",
3422   "zmm16", "zmm17", "zmm18", "zmm19",
3423   "zmm20", "zmm21", "zmm22", "zmm23",
3424   "zmm24", "zmm25", "zmm26", "zmm27",
3425   "zmm28", "zmm29", "zmm30", "zmm31"
3426 };
3427 static const char *att_names_zmm[] = {
3428   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3429   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3430   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3431   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3432   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3433   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3434   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3435   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3436 };
3437
3438 static const char **names_mask;
3439 static const char *intel_names_mask[] = {
3440   "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3441 };
3442 static const char *att_names_mask[] = {
3443   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3444 };
3445
3446 static const char *names_rounding[] =
3447 {
3448   "{rn-sae}",
3449   "{rd-sae}",
3450   "{ru-sae}",
3451   "{rz-sae}"
3452 };
3453
3454 static const struct dis386 reg_table[][8] = {
3455   /* REG_80 */
3456   {
3457     { "addA",   { Ebh1, Ib }, 0 },
3458     { "orA",    { Ebh1, Ib }, 0 },
3459     { "adcA",   { Ebh1, Ib }, 0 },
3460     { "sbbA",   { Ebh1, Ib }, 0 },
3461     { "andA",   { Ebh1, Ib }, 0 },
3462     { "subA",   { Ebh1, Ib }, 0 },
3463     { "xorA",   { Ebh1, Ib }, 0 },
3464     { "cmpA",   { Eb, Ib }, 0 },
3465   },
3466   /* REG_81 */
3467   {
3468     { "addQ",   { Evh1, Iv }, 0 },
3469     { "orQ",    { Evh1, Iv }, 0 },
3470     { "adcQ",   { Evh1, Iv }, 0 },
3471     { "sbbQ",   { Evh1, Iv }, 0 },
3472     { "andQ",   { Evh1, Iv }, 0 },
3473     { "subQ",   { Evh1, Iv }, 0 },
3474     { "xorQ",   { Evh1, Iv }, 0 },
3475     { "cmpQ",   { Ev, Iv }, 0 },
3476   },
3477   /* REG_83 */
3478   {
3479     { "addQ",   { Evh1, sIb }, 0 },
3480     { "orQ",    { Evh1, sIb }, 0 },
3481     { "adcQ",   { Evh1, sIb }, 0 },
3482     { "sbbQ",   { Evh1, sIb }, 0 },
3483     { "andQ",   { Evh1, sIb }, 0 },
3484     { "subQ",   { Evh1, sIb }, 0 },
3485     { "xorQ",   { Evh1, sIb }, 0 },
3486     { "cmpQ",   { Ev, sIb }, 0 },
3487   },
3488   /* REG_8F */
3489   {
3490     { "popU",   { stackEv }, 0 },
3491     { XOP_8F_TABLE (XOP_09) },
3492     { Bad_Opcode },
3493     { Bad_Opcode },
3494     { Bad_Opcode },
3495     { XOP_8F_TABLE (XOP_09) },
3496   },
3497   /* REG_C0 */
3498   {
3499     { "rolA",   { Eb, Ib }, 0 },
3500     { "rorA",   { Eb, Ib }, 0 },
3501     { "rclA",   { Eb, Ib }, 0 },
3502     { "rcrA",   { Eb, Ib }, 0 },
3503     { "shlA",   { Eb, Ib }, 0 },
3504     { "shrA",   { Eb, Ib }, 0 },
3505     { "shlA",   { Eb, Ib }, 0 },
3506     { "sarA",   { Eb, Ib }, 0 },
3507   },
3508   /* REG_C1 */
3509   {
3510     { "rolQ",   { Ev, Ib }, 0 },
3511     { "rorQ",   { Ev, Ib }, 0 },
3512     { "rclQ",   { Ev, Ib }, 0 },
3513     { "rcrQ",   { Ev, Ib }, 0 },
3514     { "shlQ",   { Ev, Ib }, 0 },
3515     { "shrQ",   { Ev, Ib }, 0 },
3516     { "shlQ",   { Ev, Ib }, 0 },
3517     { "sarQ",   { Ev, Ib }, 0 },
3518   },
3519   /* REG_C6 */
3520   {
3521     { "movA",   { Ebh3, Ib }, 0 },
3522     { Bad_Opcode },
3523     { Bad_Opcode },
3524     { Bad_Opcode },
3525     { Bad_Opcode },
3526     { Bad_Opcode },
3527     { Bad_Opcode },
3528     { MOD_TABLE (MOD_C6_REG_7) },
3529   },
3530   /* REG_C7 */
3531   {
3532     { "movQ",   { Evh3, Iv }, 0 },
3533     { Bad_Opcode },
3534     { Bad_Opcode },
3535     { Bad_Opcode },
3536     { Bad_Opcode },
3537     { Bad_Opcode },
3538     { Bad_Opcode },
3539     { MOD_TABLE (MOD_C7_REG_7) },
3540   },
3541   /* REG_D0 */
3542   {
3543     { "rolA",   { Eb, I1 }, 0 },
3544     { "rorA",   { Eb, I1 }, 0 },
3545     { "rclA",   { Eb, I1 }, 0 },
3546     { "rcrA",   { Eb, I1 }, 0 },
3547     { "shlA",   { Eb, I1 }, 0 },
3548     { "shrA",   { Eb, I1 }, 0 },
3549     { "shlA",   { Eb, I1 }, 0 },
3550     { "sarA",   { Eb, I1 }, 0 },
3551   },
3552   /* REG_D1 */
3553   {
3554     { "rolQ",   { Ev, I1 }, 0 },
3555     { "rorQ",   { Ev, I1 }, 0 },
3556     { "rclQ",   { Ev, I1 }, 0 },
3557     { "rcrQ",   { Ev, I1 }, 0 },
3558     { "shlQ",   { Ev, I1 }, 0 },
3559     { "shrQ",   { Ev, I1 }, 0 },
3560     { "shlQ",   { Ev, I1 }, 0 },
3561     { "sarQ",   { Ev, I1 }, 0 },
3562   },
3563   /* REG_D2 */
3564   {
3565     { "rolA",   { Eb, CL }, 0 },
3566     { "rorA",   { Eb, CL }, 0 },
3567     { "rclA",   { Eb, CL }, 0 },
3568     { "rcrA",   { Eb, CL }, 0 },
3569     { "shlA",   { Eb, CL }, 0 },
3570     { "shrA",   { Eb, CL }, 0 },
3571     { "shlA",   { Eb, CL }, 0 },
3572     { "sarA",   { Eb, CL }, 0 },
3573   },
3574   /* REG_D3 */
3575   {
3576     { "rolQ",   { Ev, CL }, 0 },
3577     { "rorQ",   { Ev, CL }, 0 },
3578     { "rclQ",   { Ev, CL }, 0 },
3579     { "rcrQ",   { Ev, CL }, 0 },
3580     { "shlQ",   { Ev, CL }, 0 },
3581     { "shrQ",   { Ev, CL }, 0 },
3582     { "shlQ",   { Ev, CL }, 0 },
3583     { "sarQ",   { Ev, CL }, 0 },
3584   },
3585   /* REG_F6 */
3586   {
3587     { "testA",  { Eb, Ib }, 0 },
3588     { "testA",  { Eb, Ib }, 0 },
3589     { "notA",   { Ebh1 }, 0 },
3590     { "negA",   { Ebh1 }, 0 },
3591     { "mulA",   { Eb }, 0 },    /* Don't print the implicit %al register,  */
3592     { "imulA",  { Eb }, 0 },    /* to distinguish these opcodes from other */
3593     { "divA",   { Eb }, 0 },    /* mul/imul opcodes.  Do the same for div  */
3594     { "idivA",  { Eb }, 0 },    /* and idiv for consistency.               */
3595   },
3596   /* REG_F7 */
3597   {
3598     { "testQ",  { Ev, Iv }, 0 },
3599     { "testQ",  { Ev, Iv }, 0 },
3600     { "notQ",   { Evh1 }, 0 },
3601     { "negQ",   { Evh1 }, 0 },
3602     { "mulQ",   { Ev }, 0 },    /* Don't print the implicit register.  */
3603     { "imulQ",  { Ev }, 0 },
3604     { "divQ",   { Ev }, 0 },
3605     { "idivQ",  { Ev }, 0 },
3606   },
3607   /* REG_FE */
3608   {
3609     { "incA",   { Ebh1 }, 0 },
3610     { "decA",   { Ebh1 }, 0 },
3611   },
3612   /* REG_FF */
3613   {
3614     { "incQ",   { Evh1 }, 0 },
3615     { "decQ",   { Evh1 }, 0 },
3616     { "call{&|}", { NOTRACK, indirEv, BND }, 0 },
3617     { MOD_TABLE (MOD_FF_REG_3) },
3618     { "jmp{&|}", { NOTRACK, indirEv, BND }, 0 },
3619     { MOD_TABLE (MOD_FF_REG_5) },
3620     { "pushU",  { stackEv }, 0 },
3621     { Bad_Opcode },
3622   },
3623   /* REG_0F00 */
3624   {
3625     { "sldtD",  { Sv }, 0 },
3626     { "strD",   { Sv }, 0 },
3627     { "lldt",   { Ew }, 0 },
3628     { "ltr",    { Ew }, 0 },
3629     { "verr",   { Ew }, 0 },
3630     { "verw",   { Ew }, 0 },
3631     { Bad_Opcode },
3632     { Bad_Opcode },
3633   },
3634   /* REG_0F01 */
3635   {
3636     { MOD_TABLE (MOD_0F01_REG_0) },
3637     { MOD_TABLE (MOD_0F01_REG_1) },
3638     { MOD_TABLE (MOD_0F01_REG_2) },
3639     { MOD_TABLE (MOD_0F01_REG_3) },
3640     { "smswD",  { Sv }, 0 },
3641     { MOD_TABLE (MOD_0F01_REG_5) },
3642     { "lmsw",   { Ew }, 0 },
3643     { MOD_TABLE (MOD_0F01_REG_7) },
3644   },
3645   /* REG_0F0D */
3646   {
3647     { "prefetch",       { Mb }, 0 },
3648     { "prefetchw",      { Mb }, 0 },
3649     { "prefetchwt1",    { Mb }, 0 },
3650     { "prefetch",       { Mb }, 0 },
3651     { "prefetch",       { Mb }, 0 },
3652     { "prefetch",       { Mb }, 0 },
3653     { "prefetch",       { Mb }, 0 },
3654     { "prefetch",       { Mb }, 0 },
3655   },
3656   /* REG_0F18 */
3657   {
3658     { MOD_TABLE (MOD_0F18_REG_0) },
3659     { MOD_TABLE (MOD_0F18_REG_1) },
3660     { MOD_TABLE (MOD_0F18_REG_2) },
3661     { MOD_TABLE (MOD_0F18_REG_3) },
3662     { MOD_TABLE (MOD_0F18_REG_4) },
3663     { MOD_TABLE (MOD_0F18_REG_5) },
3664     { MOD_TABLE (MOD_0F18_REG_6) },
3665     { MOD_TABLE (MOD_0F18_REG_7) },
3666   },
3667   /* REG_0F1C_MOD_0 */
3668   {
3669     { "cldemote",       { Mb }, 0 },
3670     { "nopQ",           { Ev }, 0 },
3671     { "nopQ",           { Ev }, 0 },
3672     { "nopQ",           { Ev }, 0 },
3673     { "nopQ",           { Ev }, 0 },
3674     { "nopQ",           { Ev }, 0 },
3675     { "nopQ",           { Ev }, 0 },
3676     { "nopQ",           { Ev }, 0 },
3677   },
3678   /* REG_0F1E_MOD_3 */
3679   {
3680     { "nopQ",           { Ev }, 0 },
3681     { "rdsspK",         { Rdq }, PREFIX_OPCODE },
3682     { "nopQ",           { Ev }, 0 },
3683     { "nopQ",           { Ev }, 0 },
3684     { "nopQ",           { Ev }, 0 },
3685     { "nopQ",           { Ev }, 0 },
3686     { "nopQ",           { Ev }, 0 },
3687     { RM_TABLE (RM_0F1E_MOD_3_REG_7) },
3688   },
3689   /* REG_0F71 */
3690   {
3691     { Bad_Opcode },
3692     { Bad_Opcode },
3693     { MOD_TABLE (MOD_0F71_REG_2) },
3694     { Bad_Opcode },
3695     { MOD_TABLE (MOD_0F71_REG_4) },
3696     { Bad_Opcode },
3697     { MOD_TABLE (MOD_0F71_REG_6) },
3698   },
3699   /* REG_0F72 */
3700   {
3701     { Bad_Opcode },
3702     { Bad_Opcode },
3703     { MOD_TABLE (MOD_0F72_REG_2) },
3704     { Bad_Opcode },
3705     { MOD_TABLE (MOD_0F72_REG_4) },
3706     { Bad_Opcode },
3707     { MOD_TABLE (MOD_0F72_REG_6) },
3708   },
3709   /* REG_0F73 */
3710   {
3711     { Bad_Opcode },
3712     { Bad_Opcode },
3713     { MOD_TABLE (MOD_0F73_REG_2) },
3714     { MOD_TABLE (MOD_0F73_REG_3) },
3715     { Bad_Opcode },
3716     { Bad_Opcode },
3717     { MOD_TABLE (MOD_0F73_REG_6) },
3718     { MOD_TABLE (MOD_0F73_REG_7) },
3719   },
3720   /* REG_0FA6 */
3721   {
3722     { "montmul",        { { OP_0f07, 0 } }, 0 },
3723     { "xsha1",          { { OP_0f07, 0 } }, 0 },
3724     { "xsha256",        { { OP_0f07, 0 } }, 0 },
3725   },
3726   /* REG_0FA7 */
3727   {
3728     { "xstore-rng",     { { OP_0f07, 0 } }, 0 },
3729     { "xcrypt-ecb",     { { OP_0f07, 0 } }, 0 },
3730     { "xcrypt-cbc",     { { OP_0f07, 0 } }, 0 },
3731     { "xcrypt-ctr",     { { OP_0f07, 0 } }, 0 },
3732     { "xcrypt-cfb",     { { OP_0f07, 0 } }, 0 },
3733     { "xcrypt-ofb",     { { OP_0f07, 0 } }, 0 },
3734   },
3735   /* REG_0FAE */
3736   {
3737     { MOD_TABLE (MOD_0FAE_REG_0) },
3738     { MOD_TABLE (MOD_0FAE_REG_1) },
3739     { MOD_TABLE (MOD_0FAE_REG_2) },
3740     { MOD_TABLE (MOD_0FAE_REG_3) },
3741     { MOD_TABLE (MOD_0FAE_REG_4) },
3742     { MOD_TABLE (MOD_0FAE_REG_5) },
3743     { MOD_TABLE (MOD_0FAE_REG_6) },
3744     { MOD_TABLE (MOD_0FAE_REG_7) },
3745   },
3746   /* REG_0FBA */
3747   {
3748     { Bad_Opcode },
3749     { Bad_Opcode },
3750     { Bad_Opcode },
3751     { Bad_Opcode },
3752     { "btQ",    { Ev, Ib }, 0 },
3753     { "btsQ",   { Evh1, Ib }, 0 },
3754     { "btrQ",   { Evh1, Ib }, 0 },
3755     { "btcQ",   { Evh1, Ib }, 0 },
3756   },
3757   /* REG_0FC7 */
3758   {
3759     { Bad_Opcode },
3760     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
3761     { Bad_Opcode },
3762     { MOD_TABLE (MOD_0FC7_REG_3) },
3763     { MOD_TABLE (MOD_0FC7_REG_4) },
3764     { MOD_TABLE (MOD_0FC7_REG_5) },
3765     { MOD_TABLE (MOD_0FC7_REG_6) },
3766     { MOD_TABLE (MOD_0FC7_REG_7) },
3767   },
3768   /* REG_VEX_0F71 */
3769   {
3770     { Bad_Opcode },
3771     { Bad_Opcode },
3772     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3773     { Bad_Opcode },
3774     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3775     { Bad_Opcode },
3776     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3777   },
3778   /* REG_VEX_0F72 */
3779   {
3780     { Bad_Opcode },
3781     { Bad_Opcode },
3782     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3783     { Bad_Opcode },
3784     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3785     { Bad_Opcode },
3786     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3787   },
3788   /* REG_VEX_0F73 */
3789   {
3790     { Bad_Opcode },
3791     { Bad_Opcode },
3792     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3793     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3794     { Bad_Opcode },
3795     { Bad_Opcode },
3796     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3797     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3798   },
3799   /* REG_VEX_0FAE */
3800   {
3801     { Bad_Opcode },
3802     { Bad_Opcode },
3803     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3804     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3805   },
3806   /* REG_VEX_0F38F3 */
3807   {
3808     { Bad_Opcode },
3809     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3810     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3811     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3812   },
3813   /* REG_XOP_LWPCB */
3814   {
3815     { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3816     { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3817   },
3818   /* REG_XOP_LWP */
3819   {
3820     { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3821     { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3822   },
3823   /* REG_XOP_TBM_01 */
3824   {
3825     { Bad_Opcode },
3826     { "blcfill",        { { OP_LWP_E, 0 }, Ev }, 0 },
3827     { "blsfill",        { { OP_LWP_E, 0 }, Ev }, 0 },
3828     { "blcs",   { { OP_LWP_E, 0 }, Ev }, 0 },
3829     { "tzmsk",  { { OP_LWP_E, 0 }, Ev }, 0 },
3830     { "blcic",  { { OP_LWP_E, 0 }, Ev }, 0 },
3831     { "blsic",  { { OP_LWP_E, 0 }, Ev }, 0 },
3832     { "t1mskc", { { OP_LWP_E, 0 }, Ev }, 0 },
3833   },
3834   /* REG_XOP_TBM_02 */
3835   {
3836     { Bad_Opcode },
3837     { "blcmsk", { { OP_LWP_E, 0 }, Ev }, 0 },
3838     { Bad_Opcode },
3839     { Bad_Opcode },
3840     { Bad_Opcode },
3841     { Bad_Opcode },
3842     { "blci",   { { OP_LWP_E, 0 }, Ev }, 0 },
3843   },
3844 #define NEED_REG_TABLE
3845 #include "i386-dis-evex.h"
3846 #undef NEED_REG_TABLE
3847 };
3848
3849 static const struct dis386 prefix_table[][4] = {
3850   /* PREFIX_90 */
3851   {
3852     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3853     { "pause", { XX }, 0 },
3854     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3855     { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3856   },
3857
3858   /* PREFIX_MOD_0_0F01_REG_5 */
3859   {
3860     { Bad_Opcode },
3861     { "rstorssp",       { Mq }, PREFIX_OPCODE },
3862   },
3863
3864   /* PREFIX_MOD_3_0F01_REG_5_RM_0 */
3865   {
3866     { Bad_Opcode },
3867     { "setssbsy",       { Skip_MODRM }, PREFIX_OPCODE },
3868   },
3869
3870   /* PREFIX_MOD_3_0F01_REG_5_RM_2 */
3871   {
3872     { Bad_Opcode },
3873     { "saveprevssp",    { Skip_MODRM }, PREFIX_OPCODE },
3874   },
3875
3876   /* PREFIX_0F09 */
3877   {
3878     { "wbinvd",   { XX }, 0 },
3879     { "wbnoinvd", { XX }, 0 },
3880   },
3881
3882   /* PREFIX_0F10 */
3883   {
3884     { "movups", { XM, EXx }, PREFIX_OPCODE },
3885     { "movss",  { XM, EXd }, PREFIX_OPCODE },
3886     { "movupd", { XM, EXx }, PREFIX_OPCODE },
3887     { "movsd",  { XM, EXq }, PREFIX_OPCODE },
3888   },
3889
3890   /* PREFIX_0F11 */
3891   {
3892     { "movups", { EXxS, XM }, PREFIX_OPCODE },
3893     { "movss",  { EXdS, XM }, PREFIX_OPCODE },
3894     { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3895     { "movsd",  { EXqS, XM }, PREFIX_OPCODE },
3896   },
3897
3898   /* PREFIX_0F12 */
3899   {
3900     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3901     { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3902     { "movlpd", { XM, EXq }, PREFIX_OPCODE },
3903     { "movddup", { XM, EXq }, PREFIX_OPCODE },
3904   },
3905
3906   /* PREFIX_0F16 */
3907   {
3908     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3909     { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3910     { "movhpd", { XM, EXq }, PREFIX_OPCODE },
3911   },
3912
3913   /* PREFIX_0F1A */
3914   {
3915     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3916     { "bndcl",  { Gbnd, Ev_bnd }, 0 },
3917     { "bndmov", { Gbnd, Ebnd }, 0 },
3918     { "bndcu",  { Gbnd, Ev_bnd }, 0 },
3919   },
3920
3921   /* PREFIX_0F1B */
3922   {
3923     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3924     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3925     { "bndmov", { EbndS, Gbnd }, 0 },
3926     { "bndcn",  { Gbnd, Ev_bnd }, 0 },
3927   },
3928
3929   /* PREFIX_0F1C */
3930   {
3931     { MOD_TABLE (MOD_0F1C_PREFIX_0) },
3932     { "nopQ",   { Ev }, PREFIX_OPCODE },
3933     { "nopQ",   { Ev }, PREFIX_OPCODE },
3934     { "nopQ",   { Ev }, PREFIX_OPCODE },
3935   },
3936
3937   /* PREFIX_0F1E */
3938   {
3939     { "nopQ",   { Ev }, PREFIX_OPCODE },
3940     { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3941     { "nopQ",   { Ev }, PREFIX_OPCODE },
3942     { "nopQ",   { Ev }, PREFIX_OPCODE },
3943   },
3944
3945   /* PREFIX_0F2A */
3946   {
3947     { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3948     { "cvtsi2ss%LQ", { XM, Ev }, PREFIX_OPCODE },
3949     { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3950     { "cvtsi2sd%LQ", { XM, Ev }, 0 },
3951   },
3952
3953   /* PREFIX_0F2B */
3954   {
3955     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3956     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3957     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3958     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3959   },
3960
3961   /* PREFIX_0F2C */
3962   {
3963     { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3964     { "cvttss2si", { Gv, EXd }, PREFIX_OPCODE },
3965     { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3966     { "cvttsd2si", { Gv, EXq }, PREFIX_OPCODE },
3967   },
3968
3969   /* PREFIX_0F2D */
3970   {
3971     { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3972     { "cvtss2si", { Gv, EXd }, PREFIX_OPCODE },
3973     { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3974     { "cvtsd2si", { Gv, EXq }, PREFIX_OPCODE },
3975   },
3976
3977   /* PREFIX_0F2E */
3978   {
3979     { "ucomiss",{ XM, EXd }, 0 },
3980     { Bad_Opcode },
3981     { "ucomisd",{ XM, EXq }, 0 },
3982   },
3983
3984   /* PREFIX_0F2F */
3985   {
3986     { "comiss", { XM, EXd }, 0 },
3987     { Bad_Opcode },
3988     { "comisd", { XM, EXq }, 0 },
3989   },
3990
3991   /* PREFIX_0F51 */
3992   {
3993     { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3994     { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3995     { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3996     { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3997   },
3998
3999   /* PREFIX_0F52 */
4000   {
4001     { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
4002     { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
4003   },
4004
4005   /* PREFIX_0F53 */
4006   {
4007     { "rcpps",  { XM, EXx }, PREFIX_OPCODE },
4008     { "rcpss",  { XM, EXd }, PREFIX_OPCODE },
4009   },
4010
4011   /* PREFIX_0F58 */
4012   {
4013     { "addps", { XM, EXx }, PREFIX_OPCODE },
4014     { "addss", { XM, EXd }, PREFIX_OPCODE },
4015     { "addpd", { XM, EXx }, PREFIX_OPCODE },
4016     { "addsd", { XM, EXq }, PREFIX_OPCODE },
4017   },
4018
4019   /* PREFIX_0F59 */
4020   {
4021     { "mulps",  { XM, EXx }, PREFIX_OPCODE },
4022     { "mulss",  { XM, EXd }, PREFIX_OPCODE },
4023     { "mulpd",  { XM, EXx }, PREFIX_OPCODE },
4024     { "mulsd",  { XM, EXq }, PREFIX_OPCODE },
4025   },
4026
4027   /* PREFIX_0F5A */
4028   {
4029     { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
4030     { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
4031     { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
4032     { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
4033   },
4034
4035   /* PREFIX_0F5B */
4036   {
4037     { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
4038     { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
4039     { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
4040   },
4041
4042   /* PREFIX_0F5C */
4043   {
4044     { "subps",  { XM, EXx }, PREFIX_OPCODE },
4045     { "subss",  { XM, EXd }, PREFIX_OPCODE },
4046     { "subpd",  { XM, EXx }, PREFIX_OPCODE },
4047     { "subsd",  { XM, EXq }, PREFIX_OPCODE },
4048   },
4049
4050   /* PREFIX_0F5D */
4051   {
4052     { "minps",  { XM, EXx }, PREFIX_OPCODE },
4053     { "minss",  { XM, EXd }, PREFIX_OPCODE },
4054     { "minpd",  { XM, EXx }, PREFIX_OPCODE },
4055     { "minsd",  { XM, EXq }, PREFIX_OPCODE },
4056   },
4057
4058   /* PREFIX_0F5E */
4059   {
4060     { "divps",  { XM, EXx }, PREFIX_OPCODE },
4061     { "divss",  { XM, EXd }, PREFIX_OPCODE },
4062     { "divpd",  { XM, EXx }, PREFIX_OPCODE },
4063     { "divsd",  { XM, EXq }, PREFIX_OPCODE },
4064   },
4065
4066   /* PREFIX_0F5F */
4067   {
4068     { "maxps",  { XM, EXx }, PREFIX_OPCODE },
4069     { "maxss",  { XM, EXd }, PREFIX_OPCODE },
4070     { "maxpd",  { XM, EXx }, PREFIX_OPCODE },
4071     { "maxsd",  { XM, EXq }, PREFIX_OPCODE },
4072   },
4073
4074   /* PREFIX_0F60 */
4075   {
4076     { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
4077     { Bad_Opcode },
4078     { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
4079   },
4080
4081   /* PREFIX_0F61 */
4082   {
4083     { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
4084     { Bad_Opcode },
4085     { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
4086   },
4087
4088   /* PREFIX_0F62 */
4089   {
4090     { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
4091     { Bad_Opcode },
4092     { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
4093   },
4094
4095   /* PREFIX_0F6C */
4096   {
4097     { Bad_Opcode },
4098     { Bad_Opcode },
4099     { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE },
4100   },
4101
4102   /* PREFIX_0F6D */
4103   {
4104     { Bad_Opcode },
4105     { Bad_Opcode },
4106     { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE },
4107   },
4108
4109   /* PREFIX_0F6F */
4110   {
4111     { "movq",   { MX, EM }, PREFIX_OPCODE },
4112     { "movdqu", { XM, EXx }, PREFIX_OPCODE },
4113     { "movdqa", { XM, EXx }, PREFIX_OPCODE },
4114   },
4115
4116   /* PREFIX_0F70 */
4117   {
4118     { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
4119     { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
4120     { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
4121     { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
4122   },
4123
4124   /* PREFIX_0F73_REG_3 */
4125   {
4126     { Bad_Opcode },
4127     { Bad_Opcode },
4128     { "psrldq", { XS, Ib }, 0 },
4129   },
4130
4131   /* PREFIX_0F73_REG_7 */
4132   {
4133     { Bad_Opcode },
4134     { Bad_Opcode },
4135     { "pslldq", { XS, Ib }, 0 },
4136   },
4137
4138   /* PREFIX_0F78 */
4139   {
4140     {"vmread",  { Em, Gm }, 0 },
4141     { Bad_Opcode },
4142     {"extrq",   { XS, Ib, Ib }, 0 },
4143     {"insertq", { XM, XS, Ib, Ib }, 0 },
4144   },
4145
4146   /* PREFIX_0F79 */
4147   {
4148     {"vmwrite", { Gm, Em }, 0 },
4149     { Bad_Opcode },
4150     {"extrq",   { XM, XS }, 0 },
4151     {"insertq", { XM, XS }, 0 },
4152   },
4153
4154   /* PREFIX_0F7C */
4155   {
4156     { Bad_Opcode },
4157     { Bad_Opcode },
4158     { "haddpd", { XM, EXx }, PREFIX_OPCODE },
4159     { "haddps", { XM, EXx }, PREFIX_OPCODE },
4160   },
4161
4162   /* PREFIX_0F7D */
4163   {
4164     { Bad_Opcode },
4165     { Bad_Opcode },
4166     { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
4167     { "hsubps", { XM, EXx }, PREFIX_OPCODE },
4168   },
4169
4170   /* PREFIX_0F7E */
4171   {
4172     { "movK",   { Edq, MX }, PREFIX_OPCODE },
4173     { "movq",   { XM, EXq }, PREFIX_OPCODE },
4174     { "movK",   { Edq, XM }, PREFIX_OPCODE },
4175   },
4176
4177   /* PREFIX_0F7F */
4178   {
4179     { "movq",   { EMS, MX }, PREFIX_OPCODE },
4180     { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
4181     { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
4182   },
4183
4184   /* PREFIX_0FAE_REG_0 */
4185   {
4186     { Bad_Opcode },
4187     { "rdfsbase", { Ev }, 0 },
4188   },
4189
4190   /* PREFIX_0FAE_REG_1 */
4191   {
4192     { Bad_Opcode },
4193     { "rdgsbase", { Ev }, 0 },
4194   },
4195
4196   /* PREFIX_0FAE_REG_2 */
4197   {
4198     { Bad_Opcode },
4199     { "wrfsbase", { Ev }, 0 },
4200   },
4201
4202   /* PREFIX_0FAE_REG_3 */
4203   {
4204     { Bad_Opcode },
4205     { "wrgsbase", { Ev }, 0 },
4206   },
4207
4208   /* PREFIX_MOD_0_0FAE_REG_4 */
4209   {
4210     { "xsave",  { FXSAVE }, 0 },
4211     { "ptwrite%LQ", { Edq }, 0 },
4212   },
4213
4214   /* PREFIX_MOD_3_0FAE_REG_4 */
4215   {
4216     { Bad_Opcode },
4217     { "ptwrite%LQ", { Edq }, 0 },
4218   },
4219
4220   /* PREFIX_MOD_0_0FAE_REG_5 */
4221   {
4222     { "xrstor",         { FXSAVE }, PREFIX_OPCODE },
4223   },
4224
4225   /* PREFIX_MOD_3_0FAE_REG_5 */
4226   {
4227     { "lfence",         { Skip_MODRM }, 0 },
4228     { "incsspK",        { Rdq }, PREFIX_OPCODE },
4229   },
4230
4231   /* PREFIX_MOD_0_0FAE_REG_6 */
4232   {
4233     { "xsaveopt",       { FXSAVE }, PREFIX_OPCODE },
4234     { "clrssbsy",       { Mq }, PREFIX_OPCODE },
4235     { "clwb",   { Mb }, PREFIX_OPCODE },
4236   },
4237
4238   /* PREFIX_MOD_1_0FAE_REG_6 */
4239   {
4240     { RM_TABLE (RM_0FAE_REG_6) },
4241     { "umonitor",       { Eva }, PREFIX_OPCODE },
4242     { "tpause", { Edq }, PREFIX_OPCODE },
4243     { "umwait", { Edq }, PREFIX_OPCODE },
4244   },
4245
4246   /* PREFIX_0FAE_REG_7 */
4247   {
4248     { "clflush",        { Mb }, 0 },
4249     { Bad_Opcode },
4250     { "clflushopt",     { Mb }, 0 },
4251   },
4252
4253   /* PREFIX_0FB8 */
4254   {
4255     { Bad_Opcode },
4256     { "popcntS", { Gv, Ev }, 0 },
4257   },
4258
4259   /* PREFIX_0FBC */
4260   {
4261     { "bsfS",   { Gv, Ev }, 0 },
4262     { "tzcntS", { Gv, Ev }, 0 },
4263     { "bsfS",   { Gv, Ev }, 0 },
4264   },
4265
4266   /* PREFIX_0FBD */
4267   {
4268     { "bsrS",   { Gv, Ev }, 0 },
4269     { "lzcntS", { Gv, Ev }, 0 },
4270     { "bsrS",   { Gv, Ev }, 0 },
4271   },
4272
4273   /* PREFIX_0FC2 */
4274   {
4275     { "cmpps",  { XM, EXx, CMP }, PREFIX_OPCODE },
4276     { "cmpss",  { XM, EXd, CMP }, PREFIX_OPCODE },
4277     { "cmppd",  { XM, EXx, CMP }, PREFIX_OPCODE },
4278     { "cmpsd",  { XM, EXq, CMP }, PREFIX_OPCODE },
4279   },
4280
4281   /* PREFIX_MOD_0_0FC3 */
4282   {
4283     { "movntiS", { Ev, Gv }, PREFIX_OPCODE },
4284   },
4285
4286   /* PREFIX_MOD_0_0FC7_REG_6 */
4287   {
4288     { "vmptrld",{ Mq }, 0 },
4289     { "vmxon",  { Mq }, 0 },
4290     { "vmclear",{ Mq }, 0 },
4291   },
4292
4293   /* PREFIX_MOD_3_0FC7_REG_6 */
4294   {
4295     { "rdrand", { Ev }, 0 },
4296     { Bad_Opcode },
4297     { "rdrand", { Ev }, 0 }
4298   },
4299
4300   /* PREFIX_MOD_3_0FC7_REG_7 */
4301   {
4302     { "rdseed", { Ev }, 0 },
4303     { "rdpid",  { Em }, 0 },
4304     { "rdseed", { Ev }, 0 },
4305   },
4306
4307   /* PREFIX_0FD0 */
4308   {
4309     { Bad_Opcode },
4310     { Bad_Opcode },
4311     { "addsubpd", { XM, EXx }, 0 },
4312     { "addsubps", { XM, EXx }, 0 },
4313   },
4314
4315   /* PREFIX_0FD6 */
4316   {
4317     { Bad_Opcode },
4318     { "movq2dq",{ XM, MS }, 0 },
4319     { "movq",   { EXqS, XM }, 0 },
4320     { "movdq2q",{ MX, XS }, 0 },
4321   },
4322
4323   /* PREFIX_0FE6 */
4324   {
4325     { Bad_Opcode },
4326     { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
4327     { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
4328     { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
4329   },
4330
4331   /* PREFIX_0FE7 */
4332   {
4333     { "movntq", { Mq, MX }, PREFIX_OPCODE },
4334     { Bad_Opcode },
4335     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
4336   },
4337
4338   /* PREFIX_0FF0 */
4339   {
4340     { Bad_Opcode },
4341     { Bad_Opcode },
4342     { Bad_Opcode },
4343     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4344   },
4345
4346   /* PREFIX_0FF7 */
4347   {
4348     { "maskmovq", { MX, MS }, PREFIX_OPCODE },
4349     { Bad_Opcode },
4350     { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
4351   },
4352
4353   /* PREFIX_0F3810 */
4354   {
4355     { Bad_Opcode },
4356     { Bad_Opcode },
4357     { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4358   },
4359
4360   /* PREFIX_0F3814 */
4361   {
4362     { Bad_Opcode },
4363     { Bad_Opcode },
4364     { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4365   },
4366
4367   /* PREFIX_0F3815 */
4368   {
4369     { Bad_Opcode },
4370     { Bad_Opcode },
4371     { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4372   },
4373
4374   /* PREFIX_0F3817 */
4375   {
4376     { Bad_Opcode },
4377     { Bad_Opcode },
4378     { "ptest",  { XM, EXx }, PREFIX_OPCODE },
4379   },
4380
4381   /* PREFIX_0F3820 */
4382   {
4383     { Bad_Opcode },
4384     { Bad_Opcode },
4385     { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE },
4386   },
4387
4388   /* PREFIX_0F3821 */
4389   {
4390     { Bad_Opcode },
4391     { Bad_Opcode },
4392     { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE },
4393   },
4394
4395   /* PREFIX_0F3822 */
4396   {
4397     { Bad_Opcode },
4398     { Bad_Opcode },
4399     { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE },
4400   },
4401
4402   /* PREFIX_0F3823 */
4403   {
4404     { Bad_Opcode },
4405     { Bad_Opcode },
4406     { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE },
4407   },
4408
4409   /* PREFIX_0F3824 */
4410   {
4411     { Bad_Opcode },
4412     { Bad_Opcode },
4413     { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE },
4414   },
4415
4416   /* PREFIX_0F3825 */
4417   {
4418     { Bad_Opcode },
4419     { Bad_Opcode },
4420     { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE },
4421   },
4422
4423   /* PREFIX_0F3828 */
4424   {
4425     { Bad_Opcode },
4426     { Bad_Opcode },
4427     { "pmuldq", { XM, EXx }, PREFIX_OPCODE },
4428   },
4429
4430   /* PREFIX_0F3829 */
4431   {
4432     { Bad_Opcode },
4433     { Bad_Opcode },
4434     { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE },
4435   },
4436
4437   /* PREFIX_0F382A */
4438   {
4439     { Bad_Opcode },
4440     { Bad_Opcode },
4441     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4442   },
4443
4444   /* PREFIX_0F382B */
4445   {
4446     { Bad_Opcode },
4447     { Bad_Opcode },
4448     { "packusdw", { XM, EXx }, PREFIX_OPCODE },
4449   },
4450
4451   /* PREFIX_0F3830 */
4452   {
4453     { Bad_Opcode },
4454     { Bad_Opcode },
4455     { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE },
4456   },
4457
4458   /* PREFIX_0F3831 */
4459   {
4460     { Bad_Opcode },
4461     { Bad_Opcode },
4462     { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE },
4463   },
4464
4465   /* PREFIX_0F3832 */
4466   {
4467     { Bad_Opcode },
4468     { Bad_Opcode },
4469     { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE },
4470   },
4471
4472   /* PREFIX_0F3833 */
4473   {
4474     { Bad_Opcode },
4475     { Bad_Opcode },
4476     { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE },
4477   },
4478
4479   /* PREFIX_0F3834 */
4480   {
4481     { Bad_Opcode },
4482     { Bad_Opcode },
4483     { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE },
4484   },
4485
4486   /* PREFIX_0F3835 */
4487   {
4488     { Bad_Opcode },
4489     { Bad_Opcode },
4490     { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE },
4491   },
4492
4493   /* PREFIX_0F3837 */
4494   {
4495     { Bad_Opcode },
4496     { Bad_Opcode },
4497     { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE },
4498   },
4499
4500   /* PREFIX_0F3838 */
4501   {
4502     { Bad_Opcode },
4503     { Bad_Opcode },
4504     { "pminsb", { XM, EXx }, PREFIX_OPCODE },
4505   },
4506
4507   /* PREFIX_0F3839 */
4508   {
4509     { Bad_Opcode },
4510     { Bad_Opcode },
4511     { "pminsd", { XM, EXx }, PREFIX_OPCODE },
4512   },
4513
4514   /* PREFIX_0F383A */
4515   {
4516     { Bad_Opcode },
4517     { Bad_Opcode },
4518     { "pminuw", { XM, EXx }, PREFIX_OPCODE },
4519   },
4520
4521   /* PREFIX_0F383B */
4522   {
4523     { Bad_Opcode },
4524     { Bad_Opcode },
4525     { "pminud", { XM, EXx }, PREFIX_OPCODE },
4526   },
4527
4528   /* PREFIX_0F383C */
4529   {
4530     { Bad_Opcode },
4531     { Bad_Opcode },
4532     { "pmaxsb", { XM, EXx }, PREFIX_OPCODE },
4533   },
4534
4535   /* PREFIX_0F383D */
4536   {
4537     { Bad_Opcode },
4538     { Bad_Opcode },
4539     { "pmaxsd", { XM, EXx }, PREFIX_OPCODE },
4540   },
4541
4542   /* PREFIX_0F383E */
4543   {
4544     { Bad_Opcode },
4545     { Bad_Opcode },
4546     { "pmaxuw", { XM, EXx }, PREFIX_OPCODE },
4547   },
4548
4549   /* PREFIX_0F383F */
4550   {
4551     { Bad_Opcode },
4552     { Bad_Opcode },
4553     { "pmaxud", { XM, EXx }, PREFIX_OPCODE },
4554   },
4555
4556   /* PREFIX_0F3840 */
4557   {
4558     { Bad_Opcode },
4559     { Bad_Opcode },
4560     { "pmulld", { XM, EXx }, PREFIX_OPCODE },
4561   },
4562
4563   /* PREFIX_0F3841 */
4564   {
4565     { Bad_Opcode },
4566     { Bad_Opcode },
4567     { "phminposuw", { XM, EXx }, PREFIX_OPCODE },
4568   },
4569
4570   /* PREFIX_0F3880 */
4571   {
4572     { Bad_Opcode },
4573     { Bad_Opcode },
4574     { "invept", { Gm, Mo }, PREFIX_OPCODE },
4575   },
4576
4577   /* PREFIX_0F3881 */
4578   {
4579     { Bad_Opcode },
4580     { Bad_Opcode },
4581     { "invvpid", { Gm, Mo }, PREFIX_OPCODE },
4582   },
4583
4584   /* PREFIX_0F3882 */
4585   {
4586     { Bad_Opcode },
4587     { Bad_Opcode },
4588     { "invpcid", { Gm, M }, PREFIX_OPCODE },
4589   },
4590
4591   /* PREFIX_0F38C8 */
4592   {
4593     { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4594   },
4595
4596   /* PREFIX_0F38C9 */
4597   {
4598     { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4599   },
4600
4601   /* PREFIX_0F38CA */
4602   {
4603     { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4604   },
4605
4606   /* PREFIX_0F38CB */
4607   {
4608     { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4609   },
4610
4611   /* PREFIX_0F38CC */
4612   {
4613     { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4614   },
4615
4616   /* PREFIX_0F38CD */
4617   {
4618     { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4619   },
4620
4621   /* PREFIX_0F38CF */
4622   {
4623     { Bad_Opcode },
4624     { Bad_Opcode },
4625     { "gf2p8mulb", { XM, EXxmm }, PREFIX_OPCODE },
4626   },
4627
4628   /* PREFIX_0F38DB */
4629   {
4630     { Bad_Opcode },
4631     { Bad_Opcode },
4632     { "aesimc", { XM, EXx }, PREFIX_OPCODE },
4633   },
4634
4635   /* PREFIX_0F38DC */
4636   {
4637     { Bad_Opcode },
4638     { Bad_Opcode },
4639     { "aesenc", { XM, EXx }, PREFIX_OPCODE },
4640   },
4641
4642   /* PREFIX_0F38DD */
4643   {
4644     { Bad_Opcode },
4645     { Bad_Opcode },
4646     { "aesenclast", { XM, EXx }, PREFIX_OPCODE },
4647   },
4648
4649   /* PREFIX_0F38DE */
4650   {
4651     { Bad_Opcode },
4652     { Bad_Opcode },
4653     { "aesdec", { XM, EXx }, PREFIX_OPCODE },
4654   },
4655
4656   /* PREFIX_0F38DF */
4657   {
4658     { Bad_Opcode },
4659     { Bad_Opcode },
4660     { "aesdeclast", { XM, EXx }, PREFIX_OPCODE },
4661   },
4662
4663   /* PREFIX_0F38F0 */
4664   {
4665     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4666     { Bad_Opcode },
4667     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4668     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE },
4669   },
4670
4671   /* PREFIX_0F38F1 */
4672   {
4673     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4674     { Bad_Opcode },
4675     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4676     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE },
4677   },
4678
4679   /* PREFIX_0F38F5 */
4680   {
4681     { Bad_Opcode },
4682     { Bad_Opcode },
4683     { MOD_TABLE (MOD_0F38F5_PREFIX_2) },
4684   },
4685
4686   /* PREFIX_0F38F6 */
4687   {
4688     { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
4689     { "adoxS",  { Gdq, Edq}, PREFIX_OPCODE },
4690     { "adcxS",  { Gdq, Edq}, PREFIX_OPCODE },
4691     { Bad_Opcode },
4692   },
4693
4694   /* PREFIX_0F38F8 */
4695   {
4696     { Bad_Opcode },
4697     { Bad_Opcode },
4698     { MOD_TABLE (MOD_0F38F8_PREFIX_2) },
4699   },
4700
4701   /* PREFIX_0F38F9 */
4702   {
4703     { MOD_TABLE (MOD_0F38F9_PREFIX_0) },
4704   },
4705
4706   /* PREFIX_0F3A08 */
4707   {
4708     { Bad_Opcode },
4709     { Bad_Opcode },
4710     { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE },
4711   },
4712
4713   /* PREFIX_0F3A09 */
4714   {
4715     { Bad_Opcode },
4716     { Bad_Opcode },
4717     { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4718   },
4719
4720   /* PREFIX_0F3A0A */
4721   {
4722     { Bad_Opcode },
4723     { Bad_Opcode },
4724     { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE },
4725   },
4726
4727   /* PREFIX_0F3A0B */
4728   {
4729     { Bad_Opcode },
4730     { Bad_Opcode },
4731     { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE },
4732   },
4733
4734   /* PREFIX_0F3A0C */
4735   {
4736     { Bad_Opcode },
4737     { Bad_Opcode },
4738     { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE },
4739   },
4740
4741   /* PREFIX_0F3A0D */
4742   {
4743     { Bad_Opcode },
4744     { Bad_Opcode },
4745     { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4746   },
4747
4748   /* PREFIX_0F3A0E */
4749   {
4750     { Bad_Opcode },
4751     { Bad_Opcode },
4752     { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE },
4753   },
4754
4755   /* PREFIX_0F3A14 */
4756   {
4757     { Bad_Opcode },
4758     { Bad_Opcode },
4759     { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE },
4760   },
4761
4762   /* PREFIX_0F3A15 */
4763   {
4764     { Bad_Opcode },
4765     { Bad_Opcode },
4766     { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE },
4767   },
4768
4769   /* PREFIX_0F3A16 */
4770   {
4771     { Bad_Opcode },
4772     { Bad_Opcode },
4773     { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE },
4774   },
4775
4776   /* PREFIX_0F3A17 */
4777   {
4778     { Bad_Opcode },
4779     { Bad_Opcode },
4780     { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE },
4781   },
4782
4783   /* PREFIX_0F3A20 */
4784   {
4785     { Bad_Opcode },
4786     { Bad_Opcode },
4787     { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE },
4788   },
4789
4790   /* PREFIX_0F3A21 */
4791   {
4792     { Bad_Opcode },
4793     { Bad_Opcode },
4794     { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE },
4795   },
4796
4797   /* PREFIX_0F3A22 */
4798   {
4799     { Bad_Opcode },
4800     { Bad_Opcode },
4801     { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE },
4802   },
4803
4804   /* PREFIX_0F3A40 */
4805   {
4806     { Bad_Opcode },
4807     { Bad_Opcode },
4808     { "dpps",   { XM, EXx, Ib }, PREFIX_OPCODE },
4809   },
4810
4811   /* PREFIX_0F3A41 */
4812   {
4813     { Bad_Opcode },
4814     { Bad_Opcode },
4815     { "dppd",   { XM, EXx, Ib }, PREFIX_OPCODE },
4816   },
4817
4818   /* PREFIX_0F3A42 */
4819   {
4820     { Bad_Opcode },
4821     { Bad_Opcode },
4822     { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE },
4823   },
4824
4825   /* PREFIX_0F3A44 */
4826   {
4827     { Bad_Opcode },
4828     { Bad_Opcode },
4829     { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE },
4830   },
4831
4832   /* PREFIX_0F3A60 */
4833   {
4834     { Bad_Opcode },
4835     { Bad_Opcode },
4836     { "pcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4837   },
4838
4839   /* PREFIX_0F3A61 */
4840   {
4841     { Bad_Opcode },
4842     { Bad_Opcode },
4843     { "pcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4844   },
4845
4846   /* PREFIX_0F3A62 */
4847   {
4848     { Bad_Opcode },
4849     { Bad_Opcode },
4850     { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4851   },
4852
4853   /* PREFIX_0F3A63 */
4854   {
4855     { Bad_Opcode },
4856     { Bad_Opcode },
4857     { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE },
4858   },
4859
4860   /* PREFIX_0F3ACC */
4861   {
4862     { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4863   },
4864
4865   /* PREFIX_0F3ACE */
4866   {
4867     { Bad_Opcode },
4868     { Bad_Opcode },
4869     { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4870   },
4871
4872   /* PREFIX_0F3ACF */
4873   {
4874     { Bad_Opcode },
4875     { Bad_Opcode },
4876     { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4877   },
4878
4879   /* PREFIX_0F3ADF */
4880   {
4881     { Bad_Opcode },
4882     { Bad_Opcode },
4883     { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE },
4884   },
4885
4886   /* PREFIX_VEX_0F10 */
4887   {
4888     { VEX_W_TABLE (VEX_W_0F10_P_0) },
4889     { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) },
4890     { VEX_W_TABLE (VEX_W_0F10_P_2) },
4891     { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) },
4892   },
4893
4894   /* PREFIX_VEX_0F11 */
4895   {
4896     { VEX_W_TABLE (VEX_W_0F11_P_0) },
4897     { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) },
4898     { VEX_W_TABLE (VEX_W_0F11_P_2) },
4899     { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) },
4900   },
4901
4902   /* PREFIX_VEX_0F12 */
4903   {
4904     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4905     { VEX_W_TABLE (VEX_W_0F12_P_1) },
4906     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
4907     { VEX_W_TABLE (VEX_W_0F12_P_3) },
4908   },
4909
4910   /* PREFIX_VEX_0F16 */
4911   {
4912     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4913     { VEX_W_TABLE (VEX_W_0F16_P_1) },
4914     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
4915   },
4916
4917   /* PREFIX_VEX_0F2A */
4918   {
4919     { Bad_Opcode },
4920     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) },
4921     { Bad_Opcode },
4922     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) },
4923   },
4924
4925   /* PREFIX_VEX_0F2C */
4926   {
4927     { Bad_Opcode },
4928     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) },
4929     { Bad_Opcode },
4930     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) },
4931   },
4932
4933   /* PREFIX_VEX_0F2D */
4934   {
4935     { Bad_Opcode },
4936     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) },
4937     { Bad_Opcode },
4938     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) },
4939   },
4940
4941   /* PREFIX_VEX_0F2E */
4942   {
4943     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) },
4944     { Bad_Opcode },
4945     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) },
4946   },
4947
4948   /* PREFIX_VEX_0F2F */
4949   {
4950     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) },
4951     { Bad_Opcode },
4952     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) },
4953   },
4954
4955   /* PREFIX_VEX_0F41 */
4956   {
4957     { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4958     { Bad_Opcode },
4959     { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4960   },
4961
4962   /* PREFIX_VEX_0F42 */
4963   {
4964     { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4965     { Bad_Opcode },
4966     { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4967   },
4968
4969   /* PREFIX_VEX_0F44 */
4970   {
4971     { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4972     { Bad_Opcode },
4973     { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4974   },
4975
4976   /* PREFIX_VEX_0F45 */
4977   {
4978     { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4979     { Bad_Opcode },
4980     { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4981   },
4982
4983   /* PREFIX_VEX_0F46 */
4984   {
4985     { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4986     { Bad_Opcode },
4987     { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4988   },
4989
4990   /* PREFIX_VEX_0F47 */
4991   {
4992     { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4993     { Bad_Opcode },
4994     { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
4995   },
4996
4997   /* PREFIX_VEX_0F4A */
4998   {
4999     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
5000     { Bad_Opcode },
5001     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
5002   },
5003
5004   /* PREFIX_VEX_0F4B */
5005   {
5006     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
5007     { Bad_Opcode },
5008     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
5009   },
5010
5011   /* PREFIX_VEX_0F51 */
5012   {
5013     { VEX_W_TABLE (VEX_W_0F51_P_0) },
5014     { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) },
5015     { VEX_W_TABLE (VEX_W_0F51_P_2) },
5016     { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) },
5017   },
5018
5019   /* PREFIX_VEX_0F52 */
5020   {
5021     { VEX_W_TABLE (VEX_W_0F52_P_0) },
5022     { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) },
5023   },
5024
5025   /* PREFIX_VEX_0F53 */
5026   {
5027     { VEX_W_TABLE (VEX_W_0F53_P_0) },
5028     { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) },
5029   },
5030
5031   /* PREFIX_VEX_0F58 */
5032   {
5033     { VEX_W_TABLE (VEX_W_0F58_P_0) },
5034     { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) },
5035     { VEX_W_TABLE (VEX_W_0F58_P_2) },
5036     { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) },
5037   },
5038
5039   /* PREFIX_VEX_0F59 */
5040   {
5041     { VEX_W_TABLE (VEX_W_0F59_P_0) },
5042     { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) },
5043     { VEX_W_TABLE (VEX_W_0F59_P_2) },
5044     { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) },
5045   },
5046
5047   /* PREFIX_VEX_0F5A */
5048   {
5049     { VEX_W_TABLE (VEX_W_0F5A_P_0) },
5050     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) },
5051     { "vcvtpd2ps%XY", { XMM, EXx }, 0 },
5052     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) },
5053   },
5054
5055   /* PREFIX_VEX_0F5B */
5056   {
5057     { VEX_W_TABLE (VEX_W_0F5B_P_0) },
5058     { VEX_W_TABLE (VEX_W_0F5B_P_1) },
5059     { VEX_W_TABLE (VEX_W_0F5B_P_2) },
5060   },
5061
5062   /* PREFIX_VEX_0F5C */
5063   {
5064     { VEX_W_TABLE (VEX_W_0F5C_P_0) },
5065     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) },
5066     { VEX_W_TABLE (VEX_W_0F5C_P_2) },
5067     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) },
5068   },
5069
5070   /* PREFIX_VEX_0F5D */
5071   {
5072     { VEX_W_TABLE (VEX_W_0F5D_P_0) },
5073     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) },
5074     { VEX_W_TABLE (VEX_W_0F5D_P_2) },
5075     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) },
5076   },
5077
5078   /* PREFIX_VEX_0F5E */
5079   {
5080     { VEX_W_TABLE (VEX_W_0F5E_P_0) },
5081     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) },
5082     { VEX_W_TABLE (VEX_W_0F5E_P_2) },
5083     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) },
5084   },
5085
5086   /* PREFIX_VEX_0F5F */
5087   {
5088     { VEX_W_TABLE (VEX_W_0F5F_P_0) },
5089     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) },
5090     { VEX_W_TABLE (VEX_W_0F5F_P_2) },
5091     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) },
5092   },
5093
5094   /* PREFIX_VEX_0F60 */
5095   {
5096     { Bad_Opcode },
5097     { Bad_Opcode },
5098     { VEX_W_TABLE (VEX_W_0F60_P_2) },
5099   },
5100
5101   /* PREFIX_VEX_0F61 */
5102   {
5103     { Bad_Opcode },
5104     { Bad_Opcode },
5105     { VEX_W_TABLE (VEX_W_0F61_P_2) },
5106   },
5107
5108   /* PREFIX_VEX_0F62 */
5109   {
5110     { Bad_Opcode },
5111     { Bad_Opcode },
5112     { VEX_W_TABLE (VEX_W_0F62_P_2) },
5113   },
5114
5115   /* PREFIX_VEX_0F63 */
5116   {
5117     { Bad_Opcode },
5118     { Bad_Opcode },
5119     { VEX_W_TABLE (VEX_W_0F63_P_2) },
5120   },
5121
5122   /* PREFIX_VEX_0F64 */
5123   {
5124     { Bad_Opcode },
5125     { Bad_Opcode },
5126     { VEX_W_TABLE (VEX_W_0F64_P_2) },
5127   },
5128
5129   /* PREFIX_VEX_0F65 */
5130   {
5131     { Bad_Opcode },
5132     { Bad_Opcode },
5133     { VEX_W_TABLE (VEX_W_0F65_P_2) },
5134   },
5135
5136   /* PREFIX_VEX_0F66 */
5137   {
5138     { Bad_Opcode },
5139     { Bad_Opcode },
5140     { VEX_W_TABLE (VEX_W_0F66_P_2) },
5141   },
5142
5143   /* PREFIX_VEX_0F67 */
5144   {
5145     { Bad_Opcode },
5146     { Bad_Opcode },
5147     { VEX_W_TABLE (VEX_W_0F67_P_2) },
5148   },
5149
5150   /* PREFIX_VEX_0F68 */
5151   {
5152     { Bad_Opcode },
5153     { Bad_Opcode },
5154     { VEX_W_TABLE (VEX_W_0F68_P_2) },
5155   },
5156
5157   /* PREFIX_VEX_0F69 */
5158   {
5159     { Bad_Opcode },
5160     { Bad_Opcode },
5161     { VEX_W_TABLE (VEX_W_0F69_P_2) },
5162   },
5163
5164   /* PREFIX_VEX_0F6A */
5165   {
5166     { Bad_Opcode },
5167     { Bad_Opcode },
5168     { VEX_W_TABLE (VEX_W_0F6A_P_2) },
5169   },
5170
5171   /* PREFIX_VEX_0F6B */
5172   {
5173     { Bad_Opcode },
5174     { Bad_Opcode },
5175     { VEX_W_TABLE (VEX_W_0F6B_P_2) },
5176   },
5177
5178   /* PREFIX_VEX_0F6C */
5179   {
5180     { Bad_Opcode },
5181     { Bad_Opcode },
5182     { VEX_W_TABLE (VEX_W_0F6C_P_2) },
5183   },
5184
5185   /* PREFIX_VEX_0F6D */
5186   {
5187     { Bad_Opcode },
5188     { Bad_Opcode },
5189     { VEX_W_TABLE (VEX_W_0F6D_P_2) },
5190   },
5191
5192   /* PREFIX_VEX_0F6E */
5193   {
5194     { Bad_Opcode },
5195     { Bad_Opcode },
5196     { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
5197   },
5198
5199   /* PREFIX_VEX_0F6F */
5200   {
5201     { Bad_Opcode },
5202     { VEX_W_TABLE (VEX_W_0F6F_P_1) },
5203     { VEX_W_TABLE (VEX_W_0F6F_P_2) },
5204   },
5205
5206   /* PREFIX_VEX_0F70 */
5207   {
5208     { Bad_Opcode },
5209     { VEX_W_TABLE (VEX_W_0F70_P_1) },
5210     { VEX_W_TABLE (VEX_W_0F70_P_2) },
5211     { VEX_W_TABLE (VEX_W_0F70_P_3) },
5212   },
5213
5214   /* PREFIX_VEX_0F71_REG_2 */
5215   {
5216     { Bad_Opcode },
5217     { Bad_Opcode },
5218     { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) },
5219   },
5220
5221   /* PREFIX_VEX_0F71_REG_4 */
5222   {
5223     { Bad_Opcode },
5224     { Bad_Opcode },
5225     { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) },
5226   },
5227
5228   /* PREFIX_VEX_0F71_REG_6 */
5229   {
5230     { Bad_Opcode },
5231     { Bad_Opcode },
5232     { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) },
5233   },
5234
5235   /* PREFIX_VEX_0F72_REG_2 */
5236   {
5237     { Bad_Opcode },
5238     { Bad_Opcode },
5239     { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) },
5240   },
5241
5242   /* PREFIX_VEX_0F72_REG_4 */
5243   {
5244     { Bad_Opcode },
5245     { Bad_Opcode },
5246     { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) },
5247   },
5248
5249   /* PREFIX_VEX_0F72_REG_6 */
5250   {
5251     { Bad_Opcode },
5252     { Bad_Opcode },
5253     { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) },
5254   },
5255
5256   /* PREFIX_VEX_0F73_REG_2 */
5257   {
5258     { Bad_Opcode },
5259     { Bad_Opcode },
5260     { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) },
5261   },
5262
5263   /* PREFIX_VEX_0F73_REG_3 */
5264   {
5265     { Bad_Opcode },
5266     { Bad_Opcode },
5267     { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) },
5268   },
5269
5270   /* PREFIX_VEX_0F73_REG_6 */
5271   {
5272     { Bad_Opcode },
5273     { Bad_Opcode },
5274     { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) },
5275   },
5276
5277   /* PREFIX_VEX_0F73_REG_7 */
5278   {
5279     { Bad_Opcode },
5280     { Bad_Opcode },
5281     { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) },
5282   },
5283
5284   /* PREFIX_VEX_0F74 */
5285   {
5286     { Bad_Opcode },
5287     { Bad_Opcode },
5288     { VEX_W_TABLE (VEX_W_0F74_P_2) },
5289   },
5290
5291   /* PREFIX_VEX_0F75 */
5292   {
5293     { Bad_Opcode },
5294     { Bad_Opcode },
5295     { VEX_W_TABLE (VEX_W_0F75_P_2) },
5296   },
5297
5298   /* PREFIX_VEX_0F76 */
5299   {
5300     { Bad_Opcode },
5301     { Bad_Opcode },
5302     { VEX_W_TABLE (VEX_W_0F76_P_2) },
5303   },
5304
5305   /* PREFIX_VEX_0F77 */
5306   {
5307     { VEX_W_TABLE (VEX_W_0F77_P_0) },
5308   },
5309
5310   /* PREFIX_VEX_0F7C */
5311   {
5312     { Bad_Opcode },
5313     { Bad_Opcode },
5314     { VEX_W_TABLE (VEX_W_0F7C_P_2) },
5315     { VEX_W_TABLE (VEX_W_0F7C_P_3) },
5316   },
5317
5318   /* PREFIX_VEX_0F7D */
5319   {
5320     { Bad_Opcode },
5321     { Bad_Opcode },
5322     { VEX_W_TABLE (VEX_W_0F7D_P_2) },
5323     { VEX_W_TABLE (VEX_W_0F7D_P_3) },
5324   },
5325
5326   /* PREFIX_VEX_0F7E */
5327   {
5328     { Bad_Opcode },
5329     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
5330     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
5331   },
5332
5333   /* PREFIX_VEX_0F7F */
5334   {
5335     { Bad_Opcode },
5336     { VEX_W_TABLE (VEX_W_0F7F_P_1) },
5337     { VEX_W_TABLE (VEX_W_0F7F_P_2) },
5338   },
5339
5340   /* PREFIX_VEX_0F90 */
5341   {
5342     { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
5343     { Bad_Opcode },
5344     { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
5345   },
5346
5347   /* PREFIX_VEX_0F91 */
5348   {
5349     { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
5350     { Bad_Opcode },
5351     { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
5352   },
5353
5354   /* PREFIX_VEX_0F92 */
5355   {
5356     { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
5357     { Bad_Opcode },
5358     { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
5359     { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
5360   },
5361
5362   /* PREFIX_VEX_0F93 */
5363   {
5364     { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
5365     { Bad_Opcode },
5366     { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
5367     { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
5368   },
5369
5370   /* PREFIX_VEX_0F98 */
5371   {
5372     { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
5373     { Bad_Opcode },
5374     { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
5375   },
5376
5377   /* PREFIX_VEX_0F99 */
5378   {
5379     { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5380     { Bad_Opcode },
5381     { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5382   },
5383
5384   /* PREFIX_VEX_0FC2 */
5385   {
5386     { VEX_W_TABLE (VEX_W_0FC2_P_0) },
5387     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) },
5388     { VEX_W_TABLE (VEX_W_0FC2_P_2) },
5389     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) },
5390   },
5391
5392   /* PREFIX_VEX_0FC4 */
5393   {
5394     { Bad_Opcode },
5395     { Bad_Opcode },
5396     { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5397   },
5398
5399   /* PREFIX_VEX_0FC5 */
5400   {
5401     { Bad_Opcode },
5402     { Bad_Opcode },
5403     { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5404   },
5405
5406   /* PREFIX_VEX_0FD0 */
5407   {
5408     { Bad_Opcode },
5409     { Bad_Opcode },
5410     { VEX_W_TABLE (VEX_W_0FD0_P_2) },
5411     { VEX_W_TABLE (VEX_W_0FD0_P_3) },
5412   },
5413
5414   /* PREFIX_VEX_0FD1 */
5415   {
5416     { Bad_Opcode },
5417     { Bad_Opcode },
5418     { VEX_W_TABLE (VEX_W_0FD1_P_2) },
5419   },
5420
5421   /* PREFIX_VEX_0FD2 */
5422   {
5423     { Bad_Opcode },
5424     { Bad_Opcode },
5425     { VEX_W_TABLE (VEX_W_0FD2_P_2) },
5426   },
5427
5428   /* PREFIX_VEX_0FD3 */
5429   {
5430     { Bad_Opcode },
5431     { Bad_Opcode },
5432     { VEX_W_TABLE (VEX_W_0FD3_P_2) },
5433   },
5434
5435   /* PREFIX_VEX_0FD4 */
5436   {
5437     { Bad_Opcode },
5438     { Bad_Opcode },
5439     { VEX_W_TABLE (VEX_W_0FD4_P_2) },
5440   },
5441
5442   /* PREFIX_VEX_0FD5 */
5443   {
5444     { Bad_Opcode },
5445     { Bad_Opcode },
5446     { VEX_W_TABLE (VEX_W_0FD5_P_2) },
5447   },
5448
5449   /* PREFIX_VEX_0FD6 */
5450   {
5451     { Bad_Opcode },
5452     { Bad_Opcode },
5453     { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5454   },
5455
5456   /* PREFIX_VEX_0FD7 */
5457   {
5458     { Bad_Opcode },
5459     { Bad_Opcode },
5460     { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5461   },
5462
5463   /* PREFIX_VEX_0FD8 */
5464   {
5465     { Bad_Opcode },
5466     { Bad_Opcode },
5467     { VEX_W_TABLE (VEX_W_0FD8_P_2) },
5468   },
5469
5470   /* PREFIX_VEX_0FD9 */
5471   {
5472     { Bad_Opcode },
5473     { Bad_Opcode },
5474     { VEX_W_TABLE (VEX_W_0FD9_P_2) },
5475   },
5476
5477   /* PREFIX_VEX_0FDA */
5478   {
5479     { Bad_Opcode },
5480     { Bad_Opcode },
5481     { VEX_W_TABLE (VEX_W_0FDA_P_2) },
5482   },
5483
5484   /* PREFIX_VEX_0FDB */
5485   {
5486     { Bad_Opcode },
5487     { Bad_Opcode },
5488     { VEX_W_TABLE (VEX_W_0FDB_P_2) },
5489   },
5490
5491   /* PREFIX_VEX_0FDC */
5492   {
5493     { Bad_Opcode },
5494     { Bad_Opcode },
5495     { VEX_W_TABLE (VEX_W_0FDC_P_2) },
5496   },
5497
5498   /* PREFIX_VEX_0FDD */
5499   {
5500     { Bad_Opcode },
5501     { Bad_Opcode },
5502     { VEX_W_TABLE (VEX_W_0FDD_P_2) },
5503   },
5504
5505   /* PREFIX_VEX_0FDE */
5506   {
5507     { Bad_Opcode },
5508     { Bad_Opcode },
5509     { VEX_W_TABLE (VEX_W_0FDE_P_2) },
5510   },
5511
5512   /* PREFIX_VEX_0FDF */
5513   {
5514     { Bad_Opcode },
5515     { Bad_Opcode },
5516     { VEX_W_TABLE (VEX_W_0FDF_P_2) },
5517   },
5518
5519   /* PREFIX_VEX_0FE0 */
5520   {
5521     { Bad_Opcode },
5522     { Bad_Opcode },
5523     { VEX_W_TABLE (VEX_W_0FE0_P_2) },
5524   },
5525
5526   /* PREFIX_VEX_0FE1 */
5527   {
5528     { Bad_Opcode },
5529     { Bad_Opcode },
5530     { VEX_W_TABLE (VEX_W_0FE1_P_2) },
5531   },
5532
5533   /* PREFIX_VEX_0FE2 */
5534   {
5535     { Bad_Opcode },
5536     { Bad_Opcode },
5537     { VEX_W_TABLE (VEX_W_0FE2_P_2) },
5538   },
5539
5540   /* PREFIX_VEX_0FE3 */
5541   {
5542     { Bad_Opcode },
5543     { Bad_Opcode },
5544     { VEX_W_TABLE (VEX_W_0FE3_P_2) },
5545   },
5546
5547   /* PREFIX_VEX_0FE4 */
5548   {
5549     { Bad_Opcode },
5550     { Bad_Opcode },
5551     { VEX_W_TABLE (VEX_W_0FE4_P_2) },
5552   },
5553
5554   /* PREFIX_VEX_0FE5 */
5555   {
5556     { Bad_Opcode },
5557     { Bad_Opcode },
5558     { VEX_W_TABLE (VEX_W_0FE5_P_2) },
5559   },
5560
5561   /* PREFIX_VEX_0FE6 */
5562   {
5563     { Bad_Opcode },
5564     { VEX_W_TABLE (VEX_W_0FE6_P_1) },
5565     { VEX_W_TABLE (VEX_W_0FE6_P_2) },
5566     { VEX_W_TABLE (VEX_W_0FE6_P_3) },
5567   },
5568
5569   /* PREFIX_VEX_0FE7 */
5570   {
5571     { Bad_Opcode },
5572     { Bad_Opcode },
5573     { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5574   },
5575
5576   /* PREFIX_VEX_0FE8 */
5577   {
5578     { Bad_Opcode },
5579     { Bad_Opcode },
5580     { VEX_W_TABLE (VEX_W_0FE8_P_2) },
5581   },
5582
5583   /* PREFIX_VEX_0FE9 */
5584   {
5585     { Bad_Opcode },
5586     { Bad_Opcode },
5587     { VEX_W_TABLE (VEX_W_0FE9_P_2) },
5588   },
5589
5590   /* PREFIX_VEX_0FEA */
5591   {
5592     { Bad_Opcode },
5593     { Bad_Opcode },
5594     { VEX_W_TABLE (VEX_W_0FEA_P_2) },
5595   },
5596
5597   /* PREFIX_VEX_0FEB */
5598   {
5599     { Bad_Opcode },
5600     { Bad_Opcode },
5601     { VEX_W_TABLE (VEX_W_0FEB_P_2) },
5602   },
5603
5604   /* PREFIX_VEX_0FEC */
5605   {
5606     { Bad_Opcode },
5607     { Bad_Opcode },
5608     { VEX_W_TABLE (VEX_W_0FEC_P_2) },
5609   },
5610
5611   /* PREFIX_VEX_0FED */
5612   {
5613     { Bad_Opcode },
5614     { Bad_Opcode },
5615     { VEX_W_TABLE (VEX_W_0FED_P_2) },
5616   },
5617
5618   /* PREFIX_VEX_0FEE */
5619   {
5620     { Bad_Opcode },
5621     { Bad_Opcode },
5622     { VEX_W_TABLE (VEX_W_0FEE_P_2) },
5623   },
5624
5625   /* PREFIX_VEX_0FEF */
5626   {
5627     { Bad_Opcode },
5628     { Bad_Opcode },
5629     { VEX_W_TABLE (VEX_W_0FEF_P_2) },
5630   },
5631
5632   /* PREFIX_VEX_0FF0 */
5633   {
5634     { Bad_Opcode },
5635     { Bad_Opcode },
5636     { Bad_Opcode },
5637     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5638   },
5639
5640   /* PREFIX_VEX_0FF1 */
5641   {
5642     { Bad_Opcode },
5643     { Bad_Opcode },
5644     { VEX_W_TABLE (VEX_W_0FF1_P_2) },
5645   },
5646
5647   /* PREFIX_VEX_0FF2 */
5648   {
5649     { Bad_Opcode },
5650     { Bad_Opcode },
5651     { VEX_W_TABLE (VEX_W_0FF2_P_2) },
5652   },
5653
5654   /* PREFIX_VEX_0FF3 */
5655   {
5656     { Bad_Opcode },
5657     { Bad_Opcode },
5658     { VEX_W_TABLE (VEX_W_0FF3_P_2) },
5659   },
5660
5661   /* PREFIX_VEX_0FF4 */
5662   {
5663     { Bad_Opcode },
5664     { Bad_Opcode },
5665     { VEX_W_TABLE (VEX_W_0FF4_P_2) },
5666   },
5667
5668   /* PREFIX_VEX_0FF5 */
5669   {
5670     { Bad_Opcode },
5671     { Bad_Opcode },
5672     { VEX_W_TABLE (VEX_W_0FF5_P_2) },
5673   },
5674
5675   /* PREFIX_VEX_0FF6 */
5676   {
5677     { Bad_Opcode },
5678     { Bad_Opcode },
5679     { VEX_W_TABLE (VEX_W_0FF6_P_2) },
5680   },
5681
5682   /* PREFIX_VEX_0FF7 */
5683   {
5684     { Bad_Opcode },
5685     { Bad_Opcode },
5686     { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5687   },
5688
5689   /* PREFIX_VEX_0FF8 */
5690   {
5691     { Bad_Opcode },
5692     { Bad_Opcode },
5693     { VEX_W_TABLE (VEX_W_0FF8_P_2) },
5694   },
5695
5696   /* PREFIX_VEX_0FF9 */
5697   {
5698     { Bad_Opcode },
5699     { Bad_Opcode },
5700     { VEX_W_TABLE (VEX_W_0FF9_P_2) },
5701   },
5702
5703   /* PREFIX_VEX_0FFA */
5704   {
5705     { Bad_Opcode },
5706     { Bad_Opcode },
5707     { VEX_W_TABLE (VEX_W_0FFA_P_2) },
5708   },
5709
5710   /* PREFIX_VEX_0FFB */
5711   {
5712     { Bad_Opcode },
5713     { Bad_Opcode },
5714     { VEX_W_TABLE (VEX_W_0FFB_P_2) },
5715   },
5716
5717   /* PREFIX_VEX_0FFC */
5718   {
5719     { Bad_Opcode },
5720     { Bad_Opcode },
5721     { VEX_W_TABLE (VEX_W_0FFC_P_2) },
5722   },
5723
5724   /* PREFIX_VEX_0FFD */
5725   {
5726     { Bad_Opcode },
5727     { Bad_Opcode },
5728     { VEX_W_TABLE (VEX_W_0FFD_P_2) },
5729   },
5730
5731   /* PREFIX_VEX_0FFE */
5732   {
5733     { Bad_Opcode },
5734     { Bad_Opcode },
5735     { VEX_W_TABLE (VEX_W_0FFE_P_2) },
5736   },
5737
5738   /* PREFIX_VEX_0F3800 */
5739   {
5740     { Bad_Opcode },
5741     { Bad_Opcode },
5742     { VEX_W_TABLE (VEX_W_0F3800_P_2) },
5743   },
5744
5745   /* PREFIX_VEX_0F3801 */
5746   {
5747     { Bad_Opcode },
5748     { Bad_Opcode },
5749     { VEX_W_TABLE (VEX_W_0F3801_P_2) },
5750   },
5751
5752   /* PREFIX_VEX_0F3802 */
5753   {
5754     { Bad_Opcode },
5755     { Bad_Opcode },
5756     { VEX_W_TABLE (VEX_W_0F3802_P_2) },
5757   },
5758
5759   /* PREFIX_VEX_0F3803 */
5760   {
5761     { Bad_Opcode },
5762     { Bad_Opcode },
5763     { VEX_W_TABLE (VEX_W_0F3803_P_2) },
5764   },
5765
5766   /* PREFIX_VEX_0F3804 */
5767   {
5768     { Bad_Opcode },
5769     { Bad_Opcode },
5770     { VEX_W_TABLE (VEX_W_0F3804_P_2) },
5771   },
5772
5773   /* PREFIX_VEX_0F3805 */
5774   {
5775     { Bad_Opcode },
5776     { Bad_Opcode },
5777     { VEX_W_TABLE (VEX_W_0F3805_P_2) },
5778   },
5779
5780   /* PREFIX_VEX_0F3806 */
5781   {
5782     { Bad_Opcode },
5783     { Bad_Opcode },
5784     { VEX_W_TABLE (VEX_W_0F3806_P_2) },
5785   },
5786
5787   /* PREFIX_VEX_0F3807 */
5788   {
5789     { Bad_Opcode },
5790     { Bad_Opcode },
5791     { VEX_W_TABLE (VEX_W_0F3807_P_2) },
5792   },
5793
5794   /* PREFIX_VEX_0F3808 */
5795   {
5796     { Bad_Opcode },
5797     { Bad_Opcode },
5798     { VEX_W_TABLE (VEX_W_0F3808_P_2) },
5799   },
5800
5801   /* PREFIX_VEX_0F3809 */
5802   {
5803     { Bad_Opcode },
5804     { Bad_Opcode },
5805     { VEX_W_TABLE (VEX_W_0F3809_P_2) },
5806   },
5807
5808   /* PREFIX_VEX_0F380A */
5809   {
5810     { Bad_Opcode },
5811     { Bad_Opcode },
5812     { VEX_W_TABLE (VEX_W_0F380A_P_2) },
5813   },
5814
5815   /* PREFIX_VEX_0F380B */
5816   {
5817     { Bad_Opcode },
5818     { Bad_Opcode },
5819     { VEX_W_TABLE (VEX_W_0F380B_P_2) },
5820   },
5821
5822   /* PREFIX_VEX_0F380C */
5823   {
5824     { Bad_Opcode },
5825     { Bad_Opcode },
5826     { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5827   },
5828
5829   /* PREFIX_VEX_0F380D */
5830   {
5831     { Bad_Opcode },
5832     { Bad_Opcode },
5833     { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5834   },
5835
5836   /* PREFIX_VEX_0F380E */
5837   {
5838     { Bad_Opcode },
5839     { Bad_Opcode },
5840     { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5841   },
5842
5843   /* PREFIX_VEX_0F380F */
5844   {
5845     { Bad_Opcode },
5846     { Bad_Opcode },
5847     { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5848   },
5849
5850   /* PREFIX_VEX_0F3813 */
5851   {
5852     { Bad_Opcode },
5853     { Bad_Opcode },
5854     { "vcvtph2ps", { XM, EXxmmq }, 0 },
5855   },
5856
5857   /* PREFIX_VEX_0F3816 */
5858   {
5859     { Bad_Opcode },
5860     { Bad_Opcode },
5861     { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5862   },
5863
5864   /* PREFIX_VEX_0F3817 */
5865   {
5866     { Bad_Opcode },
5867     { Bad_Opcode },
5868     { VEX_W_TABLE (VEX_W_0F3817_P_2) },
5869   },
5870
5871   /* PREFIX_VEX_0F3818 */
5872   {
5873     { Bad_Opcode },
5874     { Bad_Opcode },
5875     { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5876   },
5877
5878   /* PREFIX_VEX_0F3819 */
5879   {
5880     { Bad_Opcode },
5881     { Bad_Opcode },
5882     { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5883   },
5884
5885   /* PREFIX_VEX_0F381A */
5886   {
5887     { Bad_Opcode },
5888     { Bad_Opcode },
5889     { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5890   },
5891
5892   /* PREFIX_VEX_0F381C */
5893   {
5894     { Bad_Opcode },
5895     { Bad_Opcode },
5896     { VEX_W_TABLE (VEX_W_0F381C_P_2) },
5897   },
5898
5899   /* PREFIX_VEX_0F381D */
5900   {
5901     { Bad_Opcode },
5902     { Bad_Opcode },
5903     { VEX_W_TABLE (VEX_W_0F381D_P_2) },
5904   },
5905
5906   /* PREFIX_VEX_0F381E */
5907   {
5908     { Bad_Opcode },
5909     { Bad_Opcode },
5910     { VEX_W_TABLE (VEX_W_0F381E_P_2) },
5911   },
5912
5913   /* PREFIX_VEX_0F3820 */
5914   {
5915     { Bad_Opcode },
5916     { Bad_Opcode },
5917     { VEX_W_TABLE (VEX_W_0F3820_P_2) },
5918   },
5919
5920   /* PREFIX_VEX_0F3821 */
5921   {
5922     { Bad_Opcode },
5923     { Bad_Opcode },
5924     { VEX_W_TABLE (VEX_W_0F3821_P_2) },
5925   },
5926
5927   /* PREFIX_VEX_0F3822 */
5928   {
5929     { Bad_Opcode },
5930     { Bad_Opcode },
5931     { VEX_W_TABLE (VEX_W_0F3822_P_2) },
5932   },
5933
5934   /* PREFIX_VEX_0F3823 */
5935   {
5936     { Bad_Opcode },
5937     { Bad_Opcode },
5938     { VEX_W_TABLE (VEX_W_0F3823_P_2) },
5939   },
5940
5941   /* PREFIX_VEX_0F3824 */
5942   {
5943     { Bad_Opcode },
5944     { Bad_Opcode },
5945     { VEX_W_TABLE (VEX_W_0F3824_P_2) },
5946   },
5947
5948   /* PREFIX_VEX_0F3825 */
5949   {
5950     { Bad_Opcode },
5951     { Bad_Opcode },
5952     { VEX_W_TABLE (VEX_W_0F3825_P_2) },
5953   },
5954
5955   /* PREFIX_VEX_0F3828 */
5956   {
5957     { Bad_Opcode },
5958     { Bad_Opcode },
5959     { VEX_W_TABLE (VEX_W_0F3828_P_2) },
5960   },
5961
5962   /* PREFIX_VEX_0F3829 */
5963   {
5964     { Bad_Opcode },
5965     { Bad_Opcode },
5966     { VEX_W_TABLE (VEX_W_0F3829_P_2) },
5967   },
5968
5969   /* PREFIX_VEX_0F382A */
5970   {
5971     { Bad_Opcode },
5972     { Bad_Opcode },
5973     { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5974   },
5975
5976   /* PREFIX_VEX_0F382B */
5977   {
5978     { Bad_Opcode },
5979     { Bad_Opcode },
5980     { VEX_W_TABLE (VEX_W_0F382B_P_2) },
5981   },
5982
5983   /* PREFIX_VEX_0F382C */
5984   {
5985     { Bad_Opcode },
5986     { Bad_Opcode },
5987      { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5988   },
5989
5990   /* PREFIX_VEX_0F382D */
5991   {
5992     { Bad_Opcode },
5993     { Bad_Opcode },
5994      { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5995   },
5996
5997   /* PREFIX_VEX_0F382E */
5998   {
5999     { Bad_Opcode },
6000     { Bad_Opcode },
6001      { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
6002   },
6003
6004   /* PREFIX_VEX_0F382F */
6005   {
6006     { Bad_Opcode },
6007     { Bad_Opcode },
6008      { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
6009   },
6010
6011   /* PREFIX_VEX_0F3830 */
6012   {
6013     { Bad_Opcode },
6014     { Bad_Opcode },
6015     { VEX_W_TABLE (VEX_W_0F3830_P_2) },
6016   },
6017
6018   /* PREFIX_VEX_0F3831 */
6019   {
6020     { Bad_Opcode },
6021     { Bad_Opcode },
6022     { VEX_W_TABLE (VEX_W_0F3831_P_2) },
6023   },
6024
6025   /* PREFIX_VEX_0F3832 */
6026   {
6027     { Bad_Opcode },
6028     { Bad_Opcode },
6029     { VEX_W_TABLE (VEX_W_0F3832_P_2) },
6030   },
6031
6032   /* PREFIX_VEX_0F3833 */
6033   {
6034     { Bad_Opcode },
6035     { Bad_Opcode },
6036     { VEX_W_TABLE (VEX_W_0F3833_P_2) },
6037   },
6038
6039   /* PREFIX_VEX_0F3834 */
6040   {
6041     { Bad_Opcode },
6042     { Bad_Opcode },
6043     { VEX_W_TABLE (VEX_W_0F3834_P_2) },
6044   },
6045
6046   /* PREFIX_VEX_0F3835 */
6047   {
6048     { Bad_Opcode },
6049     { Bad_Opcode },
6050     { VEX_W_TABLE (VEX_W_0F3835_P_2) },
6051   },
6052
6053   /* PREFIX_VEX_0F3836 */
6054   {
6055     { Bad_Opcode },
6056     { Bad_Opcode },
6057     { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
6058   },
6059
6060   /* PREFIX_VEX_0F3837 */
6061   {
6062     { Bad_Opcode },
6063     { Bad_Opcode },
6064     { VEX_W_TABLE (VEX_W_0F3837_P_2) },
6065   },
6066
6067   /* PREFIX_VEX_0F3838 */
6068   {
6069     { Bad_Opcode },
6070     { Bad_Opcode },
6071     { VEX_W_TABLE (VEX_W_0F3838_P_2) },
6072   },
6073
6074   /* PREFIX_VEX_0F3839 */
6075   {
6076     { Bad_Opcode },
6077     { Bad_Opcode },
6078     { VEX_W_TABLE (VEX_W_0F3839_P_2) },
6079   },
6080
6081   /* PREFIX_VEX_0F383A */
6082   {
6083     { Bad_Opcode },
6084     { Bad_Opcode },
6085     { VEX_W_TABLE (VEX_W_0F383A_P_2) },
6086   },
6087
6088   /* PREFIX_VEX_0F383B */
6089   {
6090     { Bad_Opcode },
6091     { Bad_Opcode },
6092     { VEX_W_TABLE (VEX_W_0F383B_P_2) },
6093   },
6094
6095   /* PREFIX_VEX_0F383C */
6096   {
6097     { Bad_Opcode },
6098     { Bad_Opcode },
6099     { VEX_W_TABLE (VEX_W_0F383C_P_2) },
6100   },
6101
6102   /* PREFIX_VEX_0F383D */
6103   {
6104     { Bad_Opcode },
6105     { Bad_Opcode },
6106     { VEX_W_TABLE (VEX_W_0F383D_P_2) },
6107   },
6108
6109   /* PREFIX_VEX_0F383E */
6110   {
6111     { Bad_Opcode },
6112     { Bad_Opcode },
6113     { VEX_W_TABLE (VEX_W_0F383E_P_2) },
6114   },
6115
6116   /* PREFIX_VEX_0F383F */
6117   {
6118     { Bad_Opcode },
6119     { Bad_Opcode },
6120     { VEX_W_TABLE (VEX_W_0F383F_P_2) },
6121   },
6122
6123   /* PREFIX_VEX_0F3840 */
6124   {
6125     { Bad_Opcode },
6126     { Bad_Opcode },
6127     { VEX_W_TABLE (VEX_W_0F3840_P_2) },
6128   },
6129
6130   /* PREFIX_VEX_0F3841 */
6131   {
6132     { Bad_Opcode },
6133     { Bad_Opcode },
6134     { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
6135   },
6136
6137   /* PREFIX_VEX_0F3845 */
6138   {
6139     { Bad_Opcode },
6140     { Bad_Opcode },
6141     { "vpsrlv%LW", { XM, Vex, EXx }, 0 },
6142   },
6143
6144   /* PREFIX_VEX_0F3846 */
6145   {
6146     { Bad_Opcode },
6147     { Bad_Opcode },
6148     { VEX_W_TABLE (VEX_W_0F3846_P_2) },
6149   },
6150
6151   /* PREFIX_VEX_0F3847 */
6152   {
6153     { Bad_Opcode },
6154     { Bad_Opcode },
6155     { "vpsllv%LW", { XM, Vex, EXx }, 0 },
6156   },
6157
6158   /* PREFIX_VEX_0F3858 */
6159   {
6160     { Bad_Opcode },
6161     { Bad_Opcode },
6162     { VEX_W_TABLE (VEX_W_0F3858_P_2) },
6163   },
6164
6165   /* PREFIX_VEX_0F3859 */
6166   {
6167     { Bad_Opcode },
6168     { Bad_Opcode },
6169     { VEX_W_TABLE (VEX_W_0F3859_P_2) },
6170   },
6171
6172   /* PREFIX_VEX_0F385A */
6173   {
6174     { Bad_Opcode },
6175     { Bad_Opcode },
6176     { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
6177   },
6178
6179   /* PREFIX_VEX_0F3878 */
6180   {
6181     { Bad_Opcode },
6182     { Bad_Opcode },
6183     { VEX_W_TABLE (VEX_W_0F3878_P_2) },
6184   },
6185
6186   /* PREFIX_VEX_0F3879 */
6187   {
6188     { Bad_Opcode },
6189     { Bad_Opcode },
6190     { VEX_W_TABLE (VEX_W_0F3879_P_2) },
6191   },
6192
6193   /* PREFIX_VEX_0F388C */
6194   {
6195     { Bad_Opcode },
6196     { Bad_Opcode },
6197     { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
6198   },
6199
6200   /* PREFIX_VEX_0F388E */
6201   {
6202     { Bad_Opcode },
6203     { Bad_Opcode },
6204     { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
6205   },
6206
6207   /* PREFIX_VEX_0F3890 */
6208   {
6209     { Bad_Opcode },
6210     { Bad_Opcode },
6211     { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 },
6212   },
6213
6214   /* PREFIX_VEX_0F3891 */
6215   {
6216     { Bad_Opcode },
6217     { Bad_Opcode },
6218     { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6219   },
6220
6221   /* PREFIX_VEX_0F3892 */
6222   {
6223     { Bad_Opcode },
6224     { Bad_Opcode },
6225     { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 },
6226   },
6227
6228   /* PREFIX_VEX_0F3893 */
6229   {
6230     { Bad_Opcode },
6231     { Bad_Opcode },
6232     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6233   },
6234
6235   /* PREFIX_VEX_0F3896 */
6236   {
6237     { Bad_Opcode },
6238     { Bad_Opcode },
6239     { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 },
6240   },
6241
6242   /* PREFIX_VEX_0F3897 */
6243   {
6244     { Bad_Opcode },
6245     { Bad_Opcode },
6246     { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 },
6247   },
6248
6249   /* PREFIX_VEX_0F3898 */
6250   {
6251     { Bad_Opcode },
6252     { Bad_Opcode },
6253     { "vfmadd132p%XW", { XM, Vex, EXx }, 0 },
6254   },
6255
6256   /* PREFIX_VEX_0F3899 */
6257   {
6258     { Bad_Opcode },
6259     { Bad_Opcode },
6260     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6261   },
6262
6263   /* PREFIX_VEX_0F389A */
6264   {
6265     { Bad_Opcode },
6266     { Bad_Opcode },
6267     { "vfmsub132p%XW", { XM, Vex, EXx }, 0 },
6268   },
6269
6270   /* PREFIX_VEX_0F389B */
6271   {
6272     { Bad_Opcode },
6273     { Bad_Opcode },
6274     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6275   },
6276
6277   /* PREFIX_VEX_0F389C */
6278   {
6279     { Bad_Opcode },
6280     { Bad_Opcode },
6281     { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 },
6282   },
6283
6284   /* PREFIX_VEX_0F389D */
6285   {
6286     { Bad_Opcode },
6287     { Bad_Opcode },
6288     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6289   },
6290
6291   /* PREFIX_VEX_0F389E */
6292   {
6293     { Bad_Opcode },
6294     { Bad_Opcode },
6295     { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 },
6296   },
6297
6298   /* PREFIX_VEX_0F389F */
6299   {
6300     { Bad_Opcode },
6301     { Bad_Opcode },
6302     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6303   },
6304
6305   /* PREFIX_VEX_0F38A6 */
6306   {
6307     { Bad_Opcode },
6308     { Bad_Opcode },
6309     { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 },
6310     { Bad_Opcode },
6311   },
6312
6313   /* PREFIX_VEX_0F38A7 */
6314   {
6315     { Bad_Opcode },
6316     { Bad_Opcode },
6317     { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 },
6318   },
6319
6320   /* PREFIX_VEX_0F38A8 */
6321   {
6322     { Bad_Opcode },
6323     { Bad_Opcode },
6324     { "vfmadd213p%XW", { XM, Vex, EXx }, 0 },
6325   },
6326
6327   /* PREFIX_VEX_0F38A9 */
6328   {
6329     { Bad_Opcode },
6330     { Bad_Opcode },
6331     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6332   },
6333
6334   /* PREFIX_VEX_0F38AA */
6335   {
6336     { Bad_Opcode },
6337     { Bad_Opcode },
6338     { "vfmsub213p%XW", { XM, Vex, EXx }, 0 },
6339   },
6340
6341   /* PREFIX_VEX_0F38AB */
6342   {
6343     { Bad_Opcode },
6344     { Bad_Opcode },
6345     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6346   },
6347
6348   /* PREFIX_VEX_0F38AC */
6349   {
6350     { Bad_Opcode },
6351     { Bad_Opcode },
6352     { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 },
6353   },
6354
6355   /* PREFIX_VEX_0F38AD */
6356   {
6357     { Bad_Opcode },
6358     { Bad_Opcode },
6359     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6360   },
6361
6362   /* PREFIX_VEX_0F38AE */
6363   {
6364     { Bad_Opcode },
6365     { Bad_Opcode },
6366     { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 },
6367   },
6368
6369   /* PREFIX_VEX_0F38AF */
6370   {
6371     { Bad_Opcode },
6372     { Bad_Opcode },
6373     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6374   },
6375
6376   /* PREFIX_VEX_0F38B6 */
6377   {
6378     { Bad_Opcode },
6379     { Bad_Opcode },
6380     { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 },
6381   },
6382
6383   /* PREFIX_VEX_0F38B7 */
6384   {
6385     { Bad_Opcode },
6386     { Bad_Opcode },
6387     { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 },
6388   },
6389
6390   /* PREFIX_VEX_0F38B8 */
6391   {
6392     { Bad_Opcode },
6393     { Bad_Opcode },
6394     { "vfmadd231p%XW", { XM, Vex, EXx }, 0 },
6395   },
6396
6397   /* PREFIX_VEX_0F38B9 */
6398   {
6399     { Bad_Opcode },
6400     { Bad_Opcode },
6401     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6402   },
6403
6404   /* PREFIX_VEX_0F38BA */
6405   {
6406     { Bad_Opcode },
6407     { Bad_Opcode },
6408     { "vfmsub231p%XW", { XM, Vex, EXx }, 0 },
6409   },
6410
6411   /* PREFIX_VEX_0F38BB */
6412   {
6413     { Bad_Opcode },
6414     { Bad_Opcode },
6415     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6416   },
6417
6418   /* PREFIX_VEX_0F38BC */
6419   {
6420     { Bad_Opcode },
6421     { Bad_Opcode },
6422     { "vfnmadd231p%XW", { XM, Vex, EXx }, 0 },
6423   },
6424
6425   /* PREFIX_VEX_0F38BD */
6426   {
6427     { Bad_Opcode },
6428     { Bad_Opcode },
6429     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6430   },
6431
6432   /* PREFIX_VEX_0F38BE */
6433   {
6434     { Bad_Opcode },
6435     { Bad_Opcode },
6436     { "vfnmsub231p%XW", { XM, Vex, EXx }, 0 },
6437   },
6438
6439   /* PREFIX_VEX_0F38BF */
6440   {
6441     { Bad_Opcode },
6442     { Bad_Opcode },
6443     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6444   },
6445
6446   /* PREFIX_VEX_0F38CF */
6447   {
6448     { Bad_Opcode },
6449     { Bad_Opcode },
6450     { VEX_W_TABLE (VEX_W_0F38CF_P_2) },
6451   },
6452
6453   /* PREFIX_VEX_0F38DB */
6454   {
6455     { Bad_Opcode },
6456     { Bad_Opcode },
6457     { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6458   },
6459
6460   /* PREFIX_VEX_0F38DC */
6461   {
6462     { Bad_Opcode },
6463     { Bad_Opcode },
6464     { "vaesenc",        { XM, Vex, EXx }, 0 },
6465   },
6466
6467   /* PREFIX_VEX_0F38DD */
6468   {
6469     { Bad_Opcode },
6470     { Bad_Opcode },
6471     { "vaesenclast",    { XM, Vex, EXx }, 0 },
6472   },
6473
6474   /* PREFIX_VEX_0F38DE */
6475   {
6476     { Bad_Opcode },
6477     { Bad_Opcode },
6478     { "vaesdec",        { XM, Vex, EXx }, 0 },
6479   },
6480
6481   /* PREFIX_VEX_0F38DF */
6482   {
6483     { Bad_Opcode },
6484     { Bad_Opcode },
6485     { "vaesdeclast",    { XM, Vex, EXx }, 0 },
6486   },
6487
6488   /* PREFIX_VEX_0F38F2 */
6489   {
6490     { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6491   },
6492
6493   /* PREFIX_VEX_0F38F3_REG_1 */
6494   {
6495     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6496   },
6497
6498   /* PREFIX_VEX_0F38F3_REG_2 */
6499   {
6500     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6501   },
6502
6503   /* PREFIX_VEX_0F38F3_REG_3 */
6504   {
6505     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6506   },
6507
6508   /* PREFIX_VEX_0F38F5 */
6509   {
6510     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6511     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6512     { Bad_Opcode },
6513     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6514   },
6515
6516   /* PREFIX_VEX_0F38F6 */
6517   {
6518     { Bad_Opcode },
6519     { Bad_Opcode },
6520     { Bad_Opcode },
6521     { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6522   },
6523
6524   /* PREFIX_VEX_0F38F7 */
6525   {
6526     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6527     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6528     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6529     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6530   },
6531
6532   /* PREFIX_VEX_0F3A00 */
6533   {
6534     { Bad_Opcode },
6535     { Bad_Opcode },
6536     { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6537   },
6538
6539   /* PREFIX_VEX_0F3A01 */
6540   {
6541     { Bad_Opcode },
6542     { Bad_Opcode },
6543     { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6544   },
6545
6546   /* PREFIX_VEX_0F3A02 */
6547   {
6548     { Bad_Opcode },
6549     { Bad_Opcode },
6550     { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6551   },
6552
6553   /* PREFIX_VEX_0F3A04 */
6554   {
6555     { Bad_Opcode },
6556     { Bad_Opcode },
6557     { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6558   },
6559
6560   /* PREFIX_VEX_0F3A05 */
6561   {
6562     { Bad_Opcode },
6563     { Bad_Opcode },
6564     { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6565   },
6566
6567   /* PREFIX_VEX_0F3A06 */
6568   {
6569     { Bad_Opcode },
6570     { Bad_Opcode },
6571     { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6572   },
6573
6574   /* PREFIX_VEX_0F3A08 */
6575   {
6576     { Bad_Opcode },
6577     { Bad_Opcode },
6578     { VEX_W_TABLE (VEX_W_0F3A08_P_2) },
6579   },
6580
6581   /* PREFIX_VEX_0F3A09 */
6582   {
6583     { Bad_Opcode },
6584     { Bad_Opcode },
6585     { VEX_W_TABLE (VEX_W_0F3A09_P_2) },
6586   },
6587
6588   /* PREFIX_VEX_0F3A0A */
6589   {
6590     { Bad_Opcode },
6591     { Bad_Opcode },
6592     { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) },
6593   },
6594
6595   /* PREFIX_VEX_0F3A0B */
6596   {
6597     { Bad_Opcode },
6598     { Bad_Opcode },
6599     { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) },
6600   },
6601
6602   /* PREFIX_VEX_0F3A0C */
6603   {
6604     { Bad_Opcode },
6605     { Bad_Opcode },
6606     { VEX_W_TABLE (VEX_W_0F3A0C_P_2) },
6607   },
6608
6609   /* PREFIX_VEX_0F3A0D */
6610   {
6611     { Bad_Opcode },
6612     { Bad_Opcode },
6613     { VEX_W_TABLE (VEX_W_0F3A0D_P_2) },
6614   },
6615
6616   /* PREFIX_VEX_0F3A0E */
6617   {
6618     { Bad_Opcode },
6619     { Bad_Opcode },
6620     { VEX_W_TABLE (VEX_W_0F3A0E_P_2) },
6621   },
6622
6623   /* PREFIX_VEX_0F3A0F */
6624   {
6625     { Bad_Opcode },
6626     { Bad_Opcode },
6627     { VEX_W_TABLE (VEX_W_0F3A0F_P_2) },
6628   },
6629
6630   /* PREFIX_VEX_0F3A14 */
6631   {
6632     { Bad_Opcode },
6633     { Bad_Opcode },
6634     { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6635   },
6636
6637   /* PREFIX_VEX_0F3A15 */
6638   {
6639     { Bad_Opcode },
6640     { Bad_Opcode },
6641     { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6642   },
6643
6644   /* PREFIX_VEX_0F3A16 */
6645   {
6646     { Bad_Opcode },
6647     { Bad_Opcode },
6648     { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6649   },
6650
6651   /* PREFIX_VEX_0F3A17 */
6652   {
6653     { Bad_Opcode },
6654     { Bad_Opcode },
6655     { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6656   },
6657
6658   /* PREFIX_VEX_0F3A18 */
6659   {
6660     { Bad_Opcode },
6661     { Bad_Opcode },
6662     { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6663   },
6664
6665   /* PREFIX_VEX_0F3A19 */
6666   {
6667     { Bad_Opcode },
6668     { Bad_Opcode },
6669     { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6670   },
6671
6672   /* PREFIX_VEX_0F3A1D */
6673   {
6674     { Bad_Opcode },
6675     { Bad_Opcode },
6676     { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 },
6677   },
6678
6679   /* PREFIX_VEX_0F3A20 */
6680   {
6681     { Bad_Opcode },
6682     { Bad_Opcode },
6683     { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6684   },
6685
6686   /* PREFIX_VEX_0F3A21 */
6687   {
6688     { Bad_Opcode },
6689     { Bad_Opcode },
6690     { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6691   },
6692
6693   /* PREFIX_VEX_0F3A22 */
6694   {
6695     { Bad_Opcode },
6696     { Bad_Opcode },
6697     { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6698   },
6699
6700   /* PREFIX_VEX_0F3A30 */
6701   {
6702     { Bad_Opcode },
6703     { Bad_Opcode },
6704     { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6705   },
6706
6707   /* PREFIX_VEX_0F3A31 */
6708   {
6709     { Bad_Opcode },
6710     { Bad_Opcode },
6711     { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6712   },
6713
6714   /* PREFIX_VEX_0F3A32 */
6715   {
6716     { Bad_Opcode },
6717     { Bad_Opcode },
6718     { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6719   },
6720
6721   /* PREFIX_VEX_0F3A33 */
6722   {
6723     { Bad_Opcode },
6724     { Bad_Opcode },
6725     { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6726   },
6727
6728   /* PREFIX_VEX_0F3A38 */
6729   {
6730     { Bad_Opcode },
6731     { Bad_Opcode },
6732     { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6733   },
6734
6735   /* PREFIX_VEX_0F3A39 */
6736   {
6737     { Bad_Opcode },
6738     { Bad_Opcode },
6739     { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6740   },
6741
6742   /* PREFIX_VEX_0F3A40 */
6743   {
6744     { Bad_Opcode },
6745     { Bad_Opcode },
6746     { VEX_W_TABLE (VEX_W_0F3A40_P_2) },
6747   },
6748
6749   /* PREFIX_VEX_0F3A41 */
6750   {
6751     { Bad_Opcode },
6752     { Bad_Opcode },
6753     { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6754   },
6755
6756   /* PREFIX_VEX_0F3A42 */
6757   {
6758     { Bad_Opcode },
6759     { Bad_Opcode },
6760     { VEX_W_TABLE (VEX_W_0F3A42_P_2) },
6761   },
6762
6763   /* PREFIX_VEX_0F3A44 */
6764   {
6765     { Bad_Opcode },
6766     { Bad_Opcode },
6767     { "vpclmulqdq",     { XM, Vex, EXx, PCLMUL }, 0 },
6768   },
6769
6770   /* PREFIX_VEX_0F3A46 */
6771   {
6772     { Bad_Opcode },
6773     { Bad_Opcode },
6774     { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6775   },
6776
6777   /* PREFIX_VEX_0F3A48 */
6778   {
6779     { Bad_Opcode },
6780     { Bad_Opcode },
6781     { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6782   },
6783
6784   /* PREFIX_VEX_0F3A49 */
6785   {
6786     { Bad_Opcode },
6787     { Bad_Opcode },
6788     { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6789   },
6790
6791   /* PREFIX_VEX_0F3A4A */
6792   {
6793     { Bad_Opcode },
6794     { Bad_Opcode },
6795     { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6796   },
6797
6798   /* PREFIX_VEX_0F3A4B */
6799   {
6800     { Bad_Opcode },
6801     { Bad_Opcode },
6802     { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6803   },
6804
6805   /* PREFIX_VEX_0F3A4C */
6806   {
6807     { Bad_Opcode },
6808     { Bad_Opcode },
6809     { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6810   },
6811
6812   /* PREFIX_VEX_0F3A5C */
6813   {
6814     { Bad_Opcode },
6815     { Bad_Opcode },
6816     { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6817   },
6818
6819   /* PREFIX_VEX_0F3A5D */
6820   {
6821     { Bad_Opcode },
6822     { Bad_Opcode },
6823     { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6824   },
6825
6826   /* PREFIX_VEX_0F3A5E */
6827   {
6828     { Bad_Opcode },
6829     { Bad_Opcode },
6830     { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6831   },
6832
6833   /* PREFIX_VEX_0F3A5F */
6834   {
6835     { Bad_Opcode },
6836     { Bad_Opcode },
6837     { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6838   },
6839
6840   /* PREFIX_VEX_0F3A60 */
6841   {
6842     { Bad_Opcode },
6843     { Bad_Opcode },
6844     { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6845     { Bad_Opcode },
6846   },
6847
6848   /* PREFIX_VEX_0F3A61 */
6849   {
6850     { Bad_Opcode },
6851     { Bad_Opcode },
6852     { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6853   },
6854
6855   /* PREFIX_VEX_0F3A62 */
6856   {
6857     { Bad_Opcode },
6858     { Bad_Opcode },
6859     { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6860   },
6861
6862   /* PREFIX_VEX_0F3A63 */
6863   {
6864     { Bad_Opcode },
6865     { Bad_Opcode },
6866     { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6867   },
6868
6869   /* PREFIX_VEX_0F3A68 */
6870   {
6871     { Bad_Opcode },
6872     { Bad_Opcode },
6873     { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6874   },
6875
6876   /* PREFIX_VEX_0F3A69 */
6877   {
6878     { Bad_Opcode },
6879     { Bad_Opcode },
6880     { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6881   },
6882
6883   /* PREFIX_VEX_0F3A6A */
6884   {
6885     { Bad_Opcode },
6886     { Bad_Opcode },
6887     { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6888   },
6889
6890   /* PREFIX_VEX_0F3A6B */
6891   {
6892     { Bad_Opcode },
6893     { Bad_Opcode },
6894     { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6895   },
6896
6897   /* PREFIX_VEX_0F3A6C */
6898   {
6899     { Bad_Opcode },
6900     { Bad_Opcode },
6901     { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6902   },
6903
6904   /* PREFIX_VEX_0F3A6D */
6905   {
6906     { Bad_Opcode },
6907     { Bad_Opcode },
6908     { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6909   },
6910
6911   /* PREFIX_VEX_0F3A6E */
6912   {
6913     { Bad_Opcode },
6914     { Bad_Opcode },
6915     { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6916   },
6917
6918   /* PREFIX_VEX_0F3A6F */
6919   {
6920     { Bad_Opcode },
6921     { Bad_Opcode },
6922     { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6923   },
6924
6925   /* PREFIX_VEX_0F3A78 */
6926   {
6927     { Bad_Opcode },
6928     { Bad_Opcode },
6929     { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6930   },
6931
6932   /* PREFIX_VEX_0F3A79 */
6933   {
6934     { Bad_Opcode },
6935     { Bad_Opcode },
6936     { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6937   },
6938
6939   /* PREFIX_VEX_0F3A7A */
6940   {
6941     { Bad_Opcode },
6942     { Bad_Opcode },
6943     { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6944   },
6945
6946   /* PREFIX_VEX_0F3A7B */
6947   {
6948     { Bad_Opcode },
6949     { Bad_Opcode },
6950     { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6951   },
6952
6953   /* PREFIX_VEX_0F3A7C */
6954   {
6955     { Bad_Opcode },
6956     { Bad_Opcode },
6957     { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6958     { Bad_Opcode },
6959   },
6960
6961   /* PREFIX_VEX_0F3A7D */
6962   {
6963     { Bad_Opcode },
6964     { Bad_Opcode },
6965     { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6966   },
6967
6968   /* PREFIX_VEX_0F3A7E */
6969   {
6970     { Bad_Opcode },
6971     { Bad_Opcode },
6972     { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6973   },
6974
6975   /* PREFIX_VEX_0F3A7F */
6976   {
6977     { Bad_Opcode },
6978     { Bad_Opcode },
6979     { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6980   },
6981
6982   /* PREFIX_VEX_0F3ACE */
6983   {
6984     { Bad_Opcode },
6985     { Bad_Opcode },
6986     { VEX_W_TABLE (VEX_W_0F3ACE_P_2) },
6987   },
6988
6989   /* PREFIX_VEX_0F3ACF */
6990   {
6991     { Bad_Opcode },
6992     { Bad_Opcode },
6993     { VEX_W_TABLE (VEX_W_0F3ACF_P_2) },
6994   },
6995
6996   /* PREFIX_VEX_0F3ADF */
6997   {
6998     { Bad_Opcode },
6999     { Bad_Opcode },
7000     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
7001   },
7002
7003   /* PREFIX_VEX_0F3AF0 */
7004   {
7005     { Bad_Opcode },
7006     { Bad_Opcode },
7007     { Bad_Opcode },
7008     { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
7009   },
7010
7011 #define NEED_PREFIX_TABLE
7012 #include "i386-dis-evex.h"
7013 #undef NEED_PREFIX_TABLE
7014 };
7015
7016 static const struct dis386 x86_64_table[][2] = {
7017   /* X86_64_06 */
7018   {
7019     { "pushP", { es }, 0 },
7020   },
7021
7022   /* X86_64_07 */
7023   {
7024     { "popP", { es }, 0 },
7025   },
7026
7027   /* X86_64_0D */
7028   {
7029     { "pushP", { cs }, 0 },
7030   },
7031
7032   /* X86_64_16 */
7033   {
7034     { "pushP", { ss }, 0 },
7035   },
7036
7037   /* X86_64_17 */
7038   {
7039     { "popP", { ss }, 0 },
7040   },
7041
7042   /* X86_64_1E */
7043   {
7044     { "pushP", { ds }, 0 },
7045   },
7046
7047   /* X86_64_1F */
7048   {
7049     { "popP", { ds }, 0 },
7050   },
7051
7052   /* X86_64_27 */
7053   {
7054     { "daa", { XX }, 0 },
7055   },
7056
7057   /* X86_64_2F */
7058   {
7059     { "das", { XX }, 0 },
7060   },
7061
7062   /* X86_64_37 */
7063   {
7064     { "aaa", { XX }, 0 },
7065   },
7066
7067   /* X86_64_3F */
7068   {
7069     { "aas", { XX }, 0 },
7070   },
7071
7072   /* X86_64_60 */
7073   {
7074     { "pushaP", { XX }, 0 },
7075   },
7076
7077   /* X86_64_61 */
7078   {
7079     { "popaP", { XX }, 0 },
7080   },
7081
7082   /* X86_64_62 */
7083   {
7084     { MOD_TABLE (MOD_62_32BIT) },
7085     { EVEX_TABLE (EVEX_0F) },
7086   },
7087
7088   /* X86_64_63 */
7089   {
7090     { "arpl", { Ew, Gw }, 0 },
7091     { "movs{lq|xd}", { Gv, Ed }, 0 },
7092   },
7093
7094   /* X86_64_6D */
7095   {
7096     { "ins{R|}", { Yzr, indirDX }, 0 },
7097     { "ins{G|}", { Yzr, indirDX }, 0 },
7098   },
7099
7100   /* X86_64_6F */
7101   {
7102     { "outs{R|}", { indirDXr, Xz }, 0 },
7103     { "outs{G|}", { indirDXr, Xz }, 0 },
7104   },
7105
7106   /* X86_64_82 */
7107   {
7108     /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode.  */
7109     { REG_TABLE (REG_80) },
7110   },
7111
7112   /* X86_64_9A */
7113   {
7114     { "Jcall{T|}", { Ap }, 0 },
7115   },
7116
7117   /* X86_64_C4 */
7118   {
7119     { MOD_TABLE (MOD_C4_32BIT) },
7120     { VEX_C4_TABLE (VEX_0F) },
7121   },
7122
7123   /* X86_64_C5 */
7124   {
7125     { MOD_TABLE (MOD_C5_32BIT) },
7126     { VEX_C5_TABLE (VEX_0F) },
7127   },
7128
7129   /* X86_64_CE */
7130   {
7131     { "into", { XX }, 0 },
7132   },
7133
7134   /* X86_64_D4 */
7135   {
7136     { "aam", { Ib }, 0 },
7137   },
7138
7139   /* X86_64_D5 */
7140   {
7141     { "aad", { Ib }, 0 },
7142   },
7143
7144   /* X86_64_E8 */
7145   {
7146     { "callP",          { Jv, BND }, 0 },
7147     { "call@",          { Jv, BND }, 0 }
7148   },
7149
7150   /* X86_64_E9 */
7151   {
7152     { "jmpP",           { Jv, BND }, 0 },
7153     { "jmp@",           { Jv, BND }, 0 }
7154   },
7155
7156   /* X86_64_EA */
7157   {
7158     { "Jjmp{T|}", { Ap }, 0 },
7159   },
7160
7161   /* X86_64_0F01_REG_0 */
7162   {
7163     { "sgdt{Q|IQ}", { M }, 0 },
7164     { "sgdt", { M }, 0 },
7165   },
7166
7167   /* X86_64_0F01_REG_1 */
7168   {
7169     { "sidt{Q|IQ}", { M }, 0 },
7170     { "sidt", { M }, 0 },
7171   },
7172
7173   /* X86_64_0F01_REG_2 */
7174   {
7175     { "lgdt{Q|Q}", { M }, 0 },
7176     { "lgdt", { M }, 0 },
7177   },
7178
7179   /* X86_64_0F01_REG_3 */
7180   {
7181     { "lidt{Q|Q}", { M }, 0 },
7182     { "lidt", { M }, 0 },
7183   },
7184 };
7185
7186 static const struct dis386 three_byte_table[][256] = {
7187
7188   /* THREE_BYTE_0F38 */
7189   {
7190     /* 00 */
7191     { "pshufb",         { MX, EM }, PREFIX_OPCODE },
7192     { "phaddw",         { MX, EM }, PREFIX_OPCODE },
7193     { "phaddd",         { MX, EM }, PREFIX_OPCODE },
7194     { "phaddsw",        { MX, EM }, PREFIX_OPCODE },
7195     { "pmaddubsw",      { MX, EM }, PREFIX_OPCODE },
7196     { "phsubw",         { MX, EM }, PREFIX_OPCODE },
7197     { "phsubd",         { MX, EM }, PREFIX_OPCODE },
7198     { "phsubsw",        { MX, EM }, PREFIX_OPCODE },
7199     /* 08 */
7200     { "psignb",         { MX, EM }, PREFIX_OPCODE },
7201     { "psignw",         { MX, EM }, PREFIX_OPCODE },
7202     { "psignd",         { MX, EM }, PREFIX_OPCODE },
7203     { "pmulhrsw",       { MX, EM }, PREFIX_OPCODE },
7204     { Bad_Opcode },
7205     { Bad_Opcode },
7206     { Bad_Opcode },
7207     { Bad_Opcode },
7208     /* 10 */
7209     { PREFIX_TABLE (PREFIX_0F3810) },
7210     { Bad_Opcode },
7211     { Bad_Opcode },
7212     { Bad_Opcode },
7213     { PREFIX_TABLE (PREFIX_0F3814) },
7214     { PREFIX_TABLE (PREFIX_0F3815) },
7215     { Bad_Opcode },
7216     { PREFIX_TABLE (PREFIX_0F3817) },
7217     /* 18 */
7218     { Bad_Opcode },
7219     { Bad_Opcode },
7220     { Bad_Opcode },
7221     { Bad_Opcode },
7222     { "pabsb",          { MX, EM }, PREFIX_OPCODE },
7223     { "pabsw",          { MX, EM }, PREFIX_OPCODE },
7224     { "pabsd",          { MX, EM }, PREFIX_OPCODE },
7225     { Bad_Opcode },
7226     /* 20 */
7227     { PREFIX_TABLE (PREFIX_0F3820) },
7228     { PREFIX_TABLE (PREFIX_0F3821) },
7229     { PREFIX_TABLE (PREFIX_0F3822) },
7230     { PREFIX_TABLE (PREFIX_0F3823) },
7231     { PREFIX_TABLE (PREFIX_0F3824) },
7232     { PREFIX_TABLE (PREFIX_0F3825) },
7233     { Bad_Opcode },
7234     { Bad_Opcode },
7235     /* 28 */
7236     { PREFIX_TABLE (PREFIX_0F3828) },
7237     { PREFIX_TABLE (PREFIX_0F3829) },
7238     { PREFIX_TABLE (PREFIX_0F382A) },
7239     { PREFIX_TABLE (PREFIX_0F382B) },
7240     { Bad_Opcode },
7241     { Bad_Opcode },
7242     { Bad_Opcode },
7243     { Bad_Opcode },
7244     /* 30 */
7245     { PREFIX_TABLE (PREFIX_0F3830) },
7246     { PREFIX_TABLE (PREFIX_0F3831) },
7247     { PREFIX_TABLE (PREFIX_0F3832) },
7248     { PREFIX_TABLE (PREFIX_0F3833) },
7249     { PREFIX_TABLE (PREFIX_0F3834) },
7250     { PREFIX_TABLE (PREFIX_0F3835) },
7251     { Bad_Opcode },
7252     { PREFIX_TABLE (PREFIX_0F3837) },
7253     /* 38 */
7254     { PREFIX_TABLE (PREFIX_0F3838) },
7255     { PREFIX_TABLE (PREFIX_0F3839) },
7256     { PREFIX_TABLE (PREFIX_0F383A) },
7257     { PREFIX_TABLE (PREFIX_0F383B) },
7258     { PREFIX_TABLE (PREFIX_0F383C) },
7259     { PREFIX_TABLE (PREFIX_0F383D) },
7260     { PREFIX_TABLE (PREFIX_0F383E) },
7261     { PREFIX_TABLE (PREFIX_0F383F) },
7262     /* 40 */
7263     { PREFIX_TABLE (PREFIX_0F3840) },
7264     { PREFIX_TABLE (PREFIX_0F3841) },
7265     { Bad_Opcode },
7266     { Bad_Opcode },
7267     { Bad_Opcode },
7268     { Bad_Opcode },
7269     { Bad_Opcode },
7270     { Bad_Opcode },
7271     /* 48 */
7272     { Bad_Opcode },
7273     { Bad_Opcode },
7274     { Bad_Opcode },
7275     { Bad_Opcode },
7276     { Bad_Opcode },
7277     { Bad_Opcode },
7278     { Bad_Opcode },
7279     { Bad_Opcode },
7280     /* 50 */
7281     { Bad_Opcode },
7282     { Bad_Opcode },
7283     { Bad_Opcode },
7284     { Bad_Opcode },
7285     { Bad_Opcode },
7286     { Bad_Opcode },
7287     { Bad_Opcode },
7288     { Bad_Opcode },
7289     /* 58 */
7290     { Bad_Opcode },
7291     { Bad_Opcode },
7292     { Bad_Opcode },
7293     { Bad_Opcode },
7294     { Bad_Opcode },
7295     { Bad_Opcode },
7296     { Bad_Opcode },
7297     { Bad_Opcode },
7298     /* 60 */
7299     { Bad_Opcode },
7300     { Bad_Opcode },
7301     { Bad_Opcode },
7302     { Bad_Opcode },
7303     { Bad_Opcode },
7304     { Bad_Opcode },
7305     { Bad_Opcode },
7306     { Bad_Opcode },
7307     /* 68 */
7308     { Bad_Opcode },
7309     { Bad_Opcode },
7310     { Bad_Opcode },
7311     { Bad_Opcode },
7312     { Bad_Opcode },
7313     { Bad_Opcode },
7314     { Bad_Opcode },
7315     { Bad_Opcode },
7316     /* 70 */
7317     { Bad_Opcode },
7318     { Bad_Opcode },
7319     { Bad_Opcode },
7320     { Bad_Opcode },
7321     { Bad_Opcode },
7322     { Bad_Opcode },
7323     { Bad_Opcode },
7324     { Bad_Opcode },
7325     /* 78 */
7326     { Bad_Opcode },
7327     { Bad_Opcode },
7328     { Bad_Opcode },
7329     { Bad_Opcode },
7330     { Bad_Opcode },
7331     { Bad_Opcode },
7332     { Bad_Opcode },
7333     { Bad_Opcode },
7334     /* 80 */
7335     { PREFIX_TABLE (PREFIX_0F3880) },
7336     { PREFIX_TABLE (PREFIX_0F3881) },
7337     { PREFIX_TABLE (PREFIX_0F3882) },
7338     { Bad_Opcode },
7339     { Bad_Opcode },
7340     { Bad_Opcode },
7341     { Bad_Opcode },
7342     { Bad_Opcode },
7343     /* 88 */
7344     { Bad_Opcode },
7345     { Bad_Opcode },
7346     { Bad_Opcode },
7347     { Bad_Opcode },
7348     { Bad_Opcode },
7349     { Bad_Opcode },
7350     { Bad_Opcode },
7351     { Bad_Opcode },
7352     /* 90 */
7353     { Bad_Opcode },
7354     { Bad_Opcode },
7355     { Bad_Opcode },
7356     { Bad_Opcode },
7357     { Bad_Opcode },
7358     { Bad_Opcode },
7359     { Bad_Opcode },
7360     { Bad_Opcode },
7361     /* 98 */
7362     { Bad_Opcode },
7363     { Bad_Opcode },
7364     { Bad_Opcode },
7365     { Bad_Opcode },
7366     { Bad_Opcode },
7367     { Bad_Opcode },
7368     { Bad_Opcode },
7369     { Bad_Opcode },
7370     /* a0 */
7371     { Bad_Opcode },
7372     { Bad_Opcode },
7373     { Bad_Opcode },
7374     { Bad_Opcode },
7375     { Bad_Opcode },
7376     { Bad_Opcode },
7377     { Bad_Opcode },
7378     { Bad_Opcode },
7379     /* a8 */
7380     { Bad_Opcode },
7381     { Bad_Opcode },
7382     { Bad_Opcode },
7383     { Bad_Opcode },
7384     { Bad_Opcode },
7385     { Bad_Opcode },
7386     { Bad_Opcode },
7387     { Bad_Opcode },
7388     /* b0 */
7389     { Bad_Opcode },
7390     { Bad_Opcode },
7391     { Bad_Opcode },
7392     { Bad_Opcode },
7393     { Bad_Opcode },
7394     { Bad_Opcode },
7395     { Bad_Opcode },
7396     { Bad_Opcode },
7397     /* b8 */
7398     { Bad_Opcode },
7399     { Bad_Opcode },
7400     { Bad_Opcode },
7401     { Bad_Opcode },
7402     { Bad_Opcode },
7403     { Bad_Opcode },
7404     { Bad_Opcode },
7405     { Bad_Opcode },
7406     /* c0 */
7407     { Bad_Opcode },
7408     { Bad_Opcode },
7409     { Bad_Opcode },
7410     { Bad_Opcode },
7411     { Bad_Opcode },
7412     { Bad_Opcode },
7413     { Bad_Opcode },
7414     { Bad_Opcode },
7415     /* c8 */
7416     { PREFIX_TABLE (PREFIX_0F38C8) },
7417     { PREFIX_TABLE (PREFIX_0F38C9) },
7418     { PREFIX_TABLE (PREFIX_0F38CA) },
7419     { PREFIX_TABLE (PREFIX_0F38CB) },
7420     { PREFIX_TABLE (PREFIX_0F38CC) },
7421     { PREFIX_TABLE (PREFIX_0F38CD) },
7422     { Bad_Opcode },
7423     { PREFIX_TABLE (PREFIX_0F38CF) },
7424     /* d0 */
7425     { Bad_Opcode },
7426     { Bad_Opcode },
7427     { Bad_Opcode },
7428     { Bad_Opcode },
7429     { Bad_Opcode },
7430     { Bad_Opcode },
7431     { Bad_Opcode },
7432     { Bad_Opcode },
7433     /* d8 */
7434     { Bad_Opcode },
7435     { Bad_Opcode },
7436     { Bad_Opcode },
7437     { PREFIX_TABLE (PREFIX_0F38DB) },
7438     { PREFIX_TABLE (PREFIX_0F38DC) },
7439     { PREFIX_TABLE (PREFIX_0F38DD) },
7440     { PREFIX_TABLE (PREFIX_0F38DE) },
7441     { PREFIX_TABLE (PREFIX_0F38DF) },
7442     /* e0 */
7443     { Bad_Opcode },
7444     { Bad_Opcode },
7445     { Bad_Opcode },
7446     { Bad_Opcode },
7447     { Bad_Opcode },
7448     { Bad_Opcode },
7449     { Bad_Opcode },
7450     { Bad_Opcode },
7451     /* e8 */
7452     { Bad_Opcode },
7453     { Bad_Opcode },
7454     { Bad_Opcode },
7455     { Bad_Opcode },
7456     { Bad_Opcode },
7457     { Bad_Opcode },
7458     { Bad_Opcode },
7459     { Bad_Opcode },
7460     /* f0 */
7461     { PREFIX_TABLE (PREFIX_0F38F0) },
7462     { PREFIX_TABLE (PREFIX_0F38F1) },
7463     { Bad_Opcode },
7464     { Bad_Opcode },
7465     { Bad_Opcode },
7466     { PREFIX_TABLE (PREFIX_0F38F5) },
7467     { PREFIX_TABLE (PREFIX_0F38F6) },
7468     { Bad_Opcode },
7469     /* f8 */
7470     { PREFIX_TABLE (PREFIX_0F38F8) },
7471     { PREFIX_TABLE (PREFIX_0F38F9) },
7472     { Bad_Opcode },
7473     { Bad_Opcode },
7474     { Bad_Opcode },
7475     { Bad_Opcode },
7476     { Bad_Opcode },
7477     { Bad_Opcode },
7478   },
7479   /* THREE_BYTE_0F3A */
7480   {
7481     /* 00 */
7482     { Bad_Opcode },
7483     { Bad_Opcode },
7484     { Bad_Opcode },
7485     { Bad_Opcode },
7486     { Bad_Opcode },
7487     { Bad_Opcode },
7488     { Bad_Opcode },
7489     { Bad_Opcode },
7490     /* 08 */
7491     { PREFIX_TABLE (PREFIX_0F3A08) },
7492     { PREFIX_TABLE (PREFIX_0F3A09) },
7493     { PREFIX_TABLE (PREFIX_0F3A0A) },
7494     { PREFIX_TABLE (PREFIX_0F3A0B) },
7495     { PREFIX_TABLE (PREFIX_0F3A0C) },
7496     { PREFIX_TABLE (PREFIX_0F3A0D) },
7497     { PREFIX_TABLE (PREFIX_0F3A0E) },
7498     { "palignr",        { MX, EM, Ib }, PREFIX_OPCODE },
7499     /* 10 */
7500     { Bad_Opcode },
7501     { Bad_Opcode },
7502     { Bad_Opcode },
7503     { Bad_Opcode },
7504     { PREFIX_TABLE (PREFIX_0F3A14) },
7505     { PREFIX_TABLE (PREFIX_0F3A15) },
7506     { PREFIX_TABLE (PREFIX_0F3A16) },
7507     { PREFIX_TABLE (PREFIX_0F3A17) },
7508     /* 18 */
7509     { Bad_Opcode },
7510     { Bad_Opcode },
7511     { Bad_Opcode },
7512     { Bad_Opcode },
7513     { Bad_Opcode },
7514     { Bad_Opcode },
7515     { Bad_Opcode },
7516     { Bad_Opcode },
7517     /* 20 */
7518     { PREFIX_TABLE (PREFIX_0F3A20) },
7519     { PREFIX_TABLE (PREFIX_0F3A21) },
7520     { PREFIX_TABLE (PREFIX_0F3A22) },
7521     { Bad_Opcode },
7522     { Bad_Opcode },
7523     { Bad_Opcode },
7524     { Bad_Opcode },
7525     { Bad_Opcode },
7526     /* 28 */
7527     { Bad_Opcode },
7528     { Bad_Opcode },
7529     { Bad_Opcode },
7530     { Bad_Opcode },
7531     { Bad_Opcode },
7532     { Bad_Opcode },
7533     { Bad_Opcode },
7534     { Bad_Opcode },
7535     /* 30 */
7536     { Bad_Opcode },
7537     { Bad_Opcode },
7538     { Bad_Opcode },
7539     { Bad_Opcode },
7540     { Bad_Opcode },
7541     { Bad_Opcode },
7542     { Bad_Opcode },
7543     { Bad_Opcode },
7544     /* 38 */
7545     { Bad_Opcode },
7546     { Bad_Opcode },
7547     { Bad_Opcode },
7548     { Bad_Opcode },
7549     { Bad_Opcode },
7550     { Bad_Opcode },
7551     { Bad_Opcode },
7552     { Bad_Opcode },
7553     /* 40 */
7554     { PREFIX_TABLE (PREFIX_0F3A40) },
7555     { PREFIX_TABLE (PREFIX_0F3A41) },
7556     { PREFIX_TABLE (PREFIX_0F3A42) },
7557     { Bad_Opcode },
7558     { PREFIX_TABLE (PREFIX_0F3A44) },
7559     { Bad_Opcode },
7560     { Bad_Opcode },
7561     { Bad_Opcode },
7562     /* 48 */
7563     { Bad_Opcode },
7564     { Bad_Opcode },
7565     { Bad_Opcode },
7566     { Bad_Opcode },
7567     { Bad_Opcode },
7568     { Bad_Opcode },
7569     { Bad_Opcode },
7570     { Bad_Opcode },
7571     /* 50 */
7572     { Bad_Opcode },
7573     { Bad_Opcode },
7574     { Bad_Opcode },
7575     { Bad_Opcode },
7576     { Bad_Opcode },
7577     { Bad_Opcode },
7578     { Bad_Opcode },
7579     { Bad_Opcode },
7580     /* 58 */
7581     { Bad_Opcode },
7582     { Bad_Opcode },
7583     { Bad_Opcode },
7584     { Bad_Opcode },
7585     { Bad_Opcode },
7586     { Bad_Opcode },
7587     { Bad_Opcode },
7588     { Bad_Opcode },
7589     /* 60 */
7590     { PREFIX_TABLE (PREFIX_0F3A60) },
7591     { PREFIX_TABLE (PREFIX_0F3A61) },
7592     { PREFIX_TABLE (PREFIX_0F3A62) },
7593     { PREFIX_TABLE (PREFIX_0F3A63) },
7594     { Bad_Opcode },
7595     { Bad_Opcode },
7596     { Bad_Opcode },
7597     { Bad_Opcode },
7598     /* 68 */
7599     { Bad_Opcode },
7600     { Bad_Opcode },
7601     { Bad_Opcode },
7602     { Bad_Opcode },
7603     { Bad_Opcode },
7604     { Bad_Opcode },
7605     { Bad_Opcode },
7606     { Bad_Opcode },
7607     /* 70 */
7608     { Bad_Opcode },
7609     { Bad_Opcode },
7610     { Bad_Opcode },
7611     { Bad_Opcode },
7612     { Bad_Opcode },
7613     { Bad_Opcode },
7614     { Bad_Opcode },
7615     { Bad_Opcode },
7616     /* 78 */
7617     { Bad_Opcode },
7618     { Bad_Opcode },
7619     { Bad_Opcode },
7620     { Bad_Opcode },
7621     { Bad_Opcode },
7622     { Bad_Opcode },
7623     { Bad_Opcode },
7624     { Bad_Opcode },
7625     /* 80 */
7626     { Bad_Opcode },
7627     { Bad_Opcode },
7628     { Bad_Opcode },
7629     { Bad_Opcode },
7630     { Bad_Opcode },
7631     { Bad_Opcode },
7632     { Bad_Opcode },
7633     { Bad_Opcode },
7634     /* 88 */
7635     { Bad_Opcode },
7636     { Bad_Opcode },
7637     { Bad_Opcode },
7638     { Bad_Opcode },
7639     { Bad_Opcode },
7640     { Bad_Opcode },
7641     { Bad_Opcode },
7642     { Bad_Opcode },
7643     /* 90 */
7644     { Bad_Opcode },
7645     { Bad_Opcode },
7646     { Bad_Opcode },
7647     { Bad_Opcode },
7648     { Bad_Opcode },
7649     { Bad_Opcode },
7650     { Bad_Opcode },
7651     { Bad_Opcode },
7652     /* 98 */
7653     { Bad_Opcode },
7654     { Bad_Opcode },
7655     { Bad_Opcode },
7656     { Bad_Opcode },
7657     { Bad_Opcode },
7658     { Bad_Opcode },
7659     { Bad_Opcode },
7660     { Bad_Opcode },
7661     /* a0 */
7662     { Bad_Opcode },
7663     { Bad_Opcode },
7664     { Bad_Opcode },
7665     { Bad_Opcode },
7666     { Bad_Opcode },
7667     { Bad_Opcode },
7668     { Bad_Opcode },
7669     { Bad_Opcode },
7670     /* a8 */
7671     { Bad_Opcode },
7672     { Bad_Opcode },
7673     { Bad_Opcode },
7674     { Bad_Opcode },
7675     { Bad_Opcode },
7676     { Bad_Opcode },
7677     { Bad_Opcode },
7678     { Bad_Opcode },
7679     /* b0 */
7680     { Bad_Opcode },
7681     { Bad_Opcode },
7682     { Bad_Opcode },
7683     { Bad_Opcode },
7684     { Bad_Opcode },
7685     { Bad_Opcode },
7686     { Bad_Opcode },
7687     { Bad_Opcode },
7688     /* b8 */
7689     { Bad_Opcode },
7690     { Bad_Opcode },
7691     { Bad_Opcode },
7692     { Bad_Opcode },
7693     { Bad_Opcode },
7694     { Bad_Opcode },
7695     { Bad_Opcode },
7696     { Bad_Opcode },
7697     /* c0 */
7698     { Bad_Opcode },
7699     { Bad_Opcode },
7700     { Bad_Opcode },
7701     { Bad_Opcode },
7702     { Bad_Opcode },
7703     { Bad_Opcode },
7704     { Bad_Opcode },
7705     { Bad_Opcode },
7706     /* c8 */
7707     { Bad_Opcode },
7708     { Bad_Opcode },
7709     { Bad_Opcode },
7710     { Bad_Opcode },
7711     { PREFIX_TABLE (PREFIX_0F3ACC) },
7712     { Bad_Opcode },
7713     { PREFIX_TABLE (PREFIX_0F3ACE) },
7714     { PREFIX_TABLE (PREFIX_0F3ACF) },
7715     /* d0 */
7716     { Bad_Opcode },
7717     { Bad_Opcode },
7718     { Bad_Opcode },
7719     { Bad_Opcode },
7720     { Bad_Opcode },
7721     { Bad_Opcode },
7722     { Bad_Opcode },
7723     { Bad_Opcode },
7724     /* d8 */
7725     { Bad_Opcode },
7726     { Bad_Opcode },
7727     { Bad_Opcode },
7728     { Bad_Opcode },
7729     { Bad_Opcode },
7730     { Bad_Opcode },
7731     { Bad_Opcode },
7732     { PREFIX_TABLE (PREFIX_0F3ADF) },
7733     /* e0 */
7734     { Bad_Opcode },
7735     { Bad_Opcode },
7736     { Bad_Opcode },
7737     { Bad_Opcode },
7738     { Bad_Opcode },
7739     { Bad_Opcode },
7740     { Bad_Opcode },
7741     { Bad_Opcode },
7742     /* e8 */
7743     { Bad_Opcode },
7744     { Bad_Opcode },
7745     { Bad_Opcode },
7746     { Bad_Opcode },
7747     { Bad_Opcode },
7748     { Bad_Opcode },
7749     { Bad_Opcode },
7750     { Bad_Opcode },
7751     /* f0 */
7752     { Bad_Opcode },
7753     { Bad_Opcode },
7754     { Bad_Opcode },
7755     { Bad_Opcode },
7756     { Bad_Opcode },
7757     { Bad_Opcode },
7758     { Bad_Opcode },
7759     { Bad_Opcode },
7760     /* f8 */
7761     { Bad_Opcode },
7762     { Bad_Opcode },
7763     { Bad_Opcode },
7764     { Bad_Opcode },
7765     { Bad_Opcode },
7766     { Bad_Opcode },
7767     { Bad_Opcode },
7768     { Bad_Opcode },
7769   },
7770 };
7771
7772 static const struct dis386 xop_table[][256] = {
7773   /* XOP_08 */
7774   {
7775     /* 00 */
7776     { Bad_Opcode },
7777     { Bad_Opcode },
7778     { Bad_Opcode },
7779     { Bad_Opcode },
7780     { Bad_Opcode },
7781     { Bad_Opcode },
7782     { Bad_Opcode },
7783     { Bad_Opcode },
7784     /* 08 */
7785     { Bad_Opcode },
7786     { Bad_Opcode },
7787     { Bad_Opcode },
7788     { Bad_Opcode },
7789     { Bad_Opcode },
7790     { Bad_Opcode },
7791     { Bad_Opcode },
7792     { Bad_Opcode },
7793     /* 10 */
7794     { Bad_Opcode },
7795     { Bad_Opcode },
7796     { Bad_Opcode },
7797     { Bad_Opcode },
7798     { Bad_Opcode },
7799     { Bad_Opcode },
7800     { Bad_Opcode },
7801     { Bad_Opcode },
7802     /* 18 */
7803     { Bad_Opcode },
7804     { Bad_Opcode },
7805     { Bad_Opcode },
7806     { Bad_Opcode },
7807     { Bad_Opcode },
7808     { Bad_Opcode },
7809     { Bad_Opcode },
7810     { Bad_Opcode },
7811     /* 20 */
7812     { Bad_Opcode },
7813     { Bad_Opcode },
7814     { Bad_Opcode },
7815     { Bad_Opcode },
7816     { Bad_Opcode },
7817     { Bad_Opcode },
7818     { Bad_Opcode },
7819     { Bad_Opcode },
7820     /* 28 */
7821     { Bad_Opcode },
7822     { Bad_Opcode },
7823     { Bad_Opcode },
7824     { Bad_Opcode },
7825     { Bad_Opcode },
7826     { Bad_Opcode },
7827     { Bad_Opcode },
7828     { Bad_Opcode },
7829     /* 30 */
7830     { Bad_Opcode },
7831     { Bad_Opcode },
7832     { Bad_Opcode },
7833     { Bad_Opcode },
7834     { Bad_Opcode },
7835     { Bad_Opcode },
7836     { Bad_Opcode },
7837     { Bad_Opcode },
7838     /* 38 */
7839     { Bad_Opcode },
7840     { Bad_Opcode },
7841     { Bad_Opcode },
7842     { Bad_Opcode },
7843     { Bad_Opcode },
7844     { Bad_Opcode },
7845     { Bad_Opcode },
7846     { Bad_Opcode },
7847     /* 40 */
7848     { Bad_Opcode },
7849     { Bad_Opcode },
7850     { Bad_Opcode },
7851     { Bad_Opcode },
7852     { Bad_Opcode },
7853     { Bad_Opcode },
7854     { Bad_Opcode },
7855     { Bad_Opcode },
7856     /* 48 */
7857     { Bad_Opcode },
7858     { Bad_Opcode },
7859     { Bad_Opcode },
7860     { Bad_Opcode },
7861     { Bad_Opcode },
7862     { Bad_Opcode },
7863     { Bad_Opcode },
7864     { Bad_Opcode },
7865     /* 50 */
7866     { Bad_Opcode },
7867     { Bad_Opcode },
7868     { Bad_Opcode },
7869     { Bad_Opcode },
7870     { Bad_Opcode },
7871     { Bad_Opcode },
7872     { Bad_Opcode },
7873     { Bad_Opcode },
7874     /* 58 */
7875     { Bad_Opcode },
7876     { Bad_Opcode },
7877     { Bad_Opcode },
7878     { Bad_Opcode },
7879     { Bad_Opcode },
7880     { Bad_Opcode },
7881     { Bad_Opcode },
7882     { Bad_Opcode },
7883     /* 60 */
7884     { Bad_Opcode },
7885     { Bad_Opcode },
7886     { Bad_Opcode },
7887     { Bad_Opcode },
7888     { Bad_Opcode },
7889     { Bad_Opcode },
7890     { Bad_Opcode },
7891     { Bad_Opcode },
7892     /* 68 */
7893     { Bad_Opcode },
7894     { Bad_Opcode },
7895     { Bad_Opcode },
7896     { Bad_Opcode },
7897     { Bad_Opcode },
7898     { Bad_Opcode },
7899     { Bad_Opcode },
7900     { Bad_Opcode },
7901     /* 70 */
7902     { Bad_Opcode },
7903     { Bad_Opcode },
7904     { Bad_Opcode },
7905     { Bad_Opcode },
7906     { Bad_Opcode },
7907     { Bad_Opcode },
7908     { Bad_Opcode },
7909     { Bad_Opcode },
7910     /* 78 */
7911     { Bad_Opcode },
7912     { Bad_Opcode },
7913     { Bad_Opcode },
7914     { Bad_Opcode },
7915     { Bad_Opcode },
7916     { Bad_Opcode },
7917     { Bad_Opcode },
7918     { Bad_Opcode },
7919     /* 80 */
7920     { Bad_Opcode },
7921     { Bad_Opcode },
7922     { Bad_Opcode },
7923     { Bad_Opcode },
7924     { Bad_Opcode },
7925     { "vpmacssww",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7926     { "vpmacsswd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7927     { "vpmacssdql",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7928     /* 88 */
7929     { Bad_Opcode },
7930     { Bad_Opcode },
7931     { Bad_Opcode },
7932     { Bad_Opcode },
7933     { Bad_Opcode },
7934     { Bad_Opcode },
7935     { "vpmacssdd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7936     { "vpmacssdqh",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7937     /* 90 */
7938     { Bad_Opcode },
7939     { Bad_Opcode },
7940     { Bad_Opcode },
7941     { Bad_Opcode },
7942     { Bad_Opcode },
7943     { "vpmacsww",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7944     { "vpmacswd",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7945     { "vpmacsdql",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7946     /* 98 */
7947     { Bad_Opcode },
7948     { Bad_Opcode },
7949     { Bad_Opcode },
7950     { Bad_Opcode },
7951     { Bad_Opcode },
7952     { Bad_Opcode },
7953     { "vpmacsdd",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7954     { "vpmacsdqh",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7955     /* a0 */
7956     { Bad_Opcode },
7957     { Bad_Opcode },
7958     { "vpcmov",         { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7959     { "vpperm",         { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7960     { Bad_Opcode },
7961     { Bad_Opcode },
7962     { "vpmadcsswd",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7963     { Bad_Opcode },
7964     /* a8 */
7965     { Bad_Opcode },
7966     { Bad_Opcode },
7967     { Bad_Opcode },
7968     { Bad_Opcode },
7969     { Bad_Opcode },
7970     { Bad_Opcode },
7971     { Bad_Opcode },
7972     { Bad_Opcode },
7973     /* b0 */
7974     { Bad_Opcode },
7975     { Bad_Opcode },
7976     { Bad_Opcode },
7977     { Bad_Opcode },
7978     { Bad_Opcode },
7979     { Bad_Opcode },
7980     { "vpmadcswd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7981     { Bad_Opcode },
7982     /* b8 */
7983     { Bad_Opcode },
7984     { Bad_Opcode },
7985     { Bad_Opcode },
7986     { Bad_Opcode },
7987     { Bad_Opcode },
7988     { Bad_Opcode },
7989     { Bad_Opcode },
7990     { Bad_Opcode },
7991     /* c0 */
7992     { "vprotb",         { XM, Vex_2src_1, Ib }, 0 },
7993     { "vprotw",         { XM, Vex_2src_1, Ib }, 0 },
7994     { "vprotd",         { XM, Vex_2src_1, Ib }, 0 },
7995     { "vprotq",         { XM, Vex_2src_1, Ib }, 0 },
7996     { Bad_Opcode },
7997     { Bad_Opcode },
7998     { Bad_Opcode },
7999     { Bad_Opcode },
8000     /* c8 */
8001     { Bad_Opcode },
8002     { Bad_Opcode },
8003     { Bad_Opcode },
8004     { Bad_Opcode },
8005     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
8006     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
8007     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
8008     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
8009     /* d0 */
8010     { Bad_Opcode },
8011     { Bad_Opcode },
8012     { Bad_Opcode },
8013     { Bad_Opcode },
8014     { Bad_Opcode },
8015     { Bad_Opcode },
8016     { Bad_Opcode },
8017     { Bad_Opcode },
8018     /* d8 */
8019     { Bad_Opcode },
8020     { Bad_Opcode },
8021     { Bad_Opcode },
8022     { Bad_Opcode },
8023     { Bad_Opcode },
8024     { Bad_Opcode },
8025     { Bad_Opcode },
8026     { Bad_Opcode },
8027     /* e0 */
8028     { Bad_Opcode },
8029     { Bad_Opcode },
8030     { Bad_Opcode },
8031     { Bad_Opcode },
8032     { Bad_Opcode },
8033     { Bad_Opcode },
8034     { Bad_Opcode },
8035     { Bad_Opcode },
8036     /* e8 */
8037     { Bad_Opcode },
8038     { Bad_Opcode },
8039     { Bad_Opcode },
8040     { Bad_Opcode },
8041     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
8042     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
8043     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
8044     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
8045     /* f0 */
8046     { Bad_Opcode },
8047     { Bad_Opcode },
8048     { Bad_Opcode },
8049     { Bad_Opcode },
8050     { Bad_Opcode },
8051     { Bad_Opcode },
8052     { Bad_Opcode },
8053     { Bad_Opcode },
8054     /* f8 */
8055     { Bad_Opcode },
8056     { Bad_Opcode },
8057     { Bad_Opcode },
8058     { Bad_Opcode },
8059     { Bad_Opcode },
8060     { Bad_Opcode },
8061     { Bad_Opcode },
8062     { Bad_Opcode },
8063   },
8064   /* XOP_09 */
8065   {
8066     /* 00 */
8067     { Bad_Opcode },
8068     { REG_TABLE (REG_XOP_TBM_01) },
8069     { REG_TABLE (REG_XOP_TBM_02) },
8070     { Bad_Opcode },
8071     { Bad_Opcode },
8072     { Bad_Opcode },
8073     { Bad_Opcode },
8074     { Bad_Opcode },
8075     /* 08 */
8076     { Bad_Opcode },
8077     { Bad_Opcode },
8078     { Bad_Opcode },
8079     { Bad_Opcode },
8080     { Bad_Opcode },
8081     { Bad_Opcode },
8082     { Bad_Opcode },
8083     { Bad_Opcode },
8084     /* 10 */
8085     { Bad_Opcode },
8086     { Bad_Opcode },
8087     { REG_TABLE (REG_XOP_LWPCB) },
8088     { Bad_Opcode },
8089     { Bad_Opcode },
8090     { Bad_Opcode },
8091     { Bad_Opcode },
8092     { Bad_Opcode },
8093     /* 18 */
8094     { Bad_Opcode },
8095     { Bad_Opcode },
8096     { Bad_Opcode },
8097     { Bad_Opcode },
8098     { Bad_Opcode },
8099     { Bad_Opcode },
8100     { Bad_Opcode },
8101     { Bad_Opcode },
8102     /* 20 */
8103     { Bad_Opcode },
8104     { Bad_Opcode },
8105     { Bad_Opcode },
8106     { Bad_Opcode },
8107     { Bad_Opcode },
8108     { Bad_Opcode },
8109     { Bad_Opcode },
8110     { Bad_Opcode },
8111     /* 28 */
8112     { Bad_Opcode },
8113     { Bad_Opcode },
8114     { Bad_Opcode },
8115     { Bad_Opcode },
8116     { Bad_Opcode },
8117     { Bad_Opcode },
8118     { Bad_Opcode },
8119     { Bad_Opcode },
8120     /* 30 */
8121     { Bad_Opcode },
8122     { Bad_Opcode },
8123     { Bad_Opcode },
8124     { Bad_Opcode },
8125     { Bad_Opcode },
8126     { Bad_Opcode },
8127     { Bad_Opcode },
8128     { Bad_Opcode },
8129     /* 38 */
8130     { Bad_Opcode },
8131     { Bad_Opcode },
8132     { Bad_Opcode },
8133     { Bad_Opcode },
8134     { Bad_Opcode },
8135     { Bad_Opcode },
8136     { Bad_Opcode },
8137     { Bad_Opcode },
8138     /* 40 */
8139     { Bad_Opcode },
8140     { Bad_Opcode },
8141     { Bad_Opcode },
8142     { Bad_Opcode },
8143     { Bad_Opcode },
8144     { Bad_Opcode },
8145     { Bad_Opcode },
8146     { Bad_Opcode },
8147     /* 48 */
8148     { Bad_Opcode },
8149     { Bad_Opcode },
8150     { Bad_Opcode },
8151     { Bad_Opcode },
8152     { Bad_Opcode },
8153     { Bad_Opcode },
8154     { Bad_Opcode },
8155     { Bad_Opcode },
8156     /* 50 */
8157     { Bad_Opcode },
8158     { Bad_Opcode },
8159     { Bad_Opcode },
8160     { Bad_Opcode },
8161     { Bad_Opcode },
8162     { Bad_Opcode },
8163     { Bad_Opcode },
8164     { Bad_Opcode },
8165     /* 58 */
8166     { Bad_Opcode },
8167     { Bad_Opcode },
8168     { Bad_Opcode },
8169     { Bad_Opcode },
8170     { Bad_Opcode },
8171     { Bad_Opcode },
8172     { Bad_Opcode },
8173     { Bad_Opcode },
8174     /* 60 */
8175     { Bad_Opcode },
8176     { Bad_Opcode },
8177     { Bad_Opcode },
8178     { Bad_Opcode },
8179     { Bad_Opcode },
8180     { Bad_Opcode },
8181     { Bad_Opcode },
8182     { Bad_Opcode },
8183     /* 68 */
8184     { Bad_Opcode },
8185     { Bad_Opcode },
8186     { Bad_Opcode },
8187     { Bad_Opcode },
8188     { Bad_Opcode },
8189     { Bad_Opcode },
8190     { Bad_Opcode },
8191     { Bad_Opcode },
8192     /* 70 */
8193     { Bad_Opcode },
8194     { Bad_Opcode },
8195     { Bad_Opcode },
8196     { Bad_Opcode },
8197     { Bad_Opcode },
8198     { Bad_Opcode },
8199     { Bad_Opcode },
8200     { Bad_Opcode },
8201     /* 78 */
8202     { Bad_Opcode },
8203     { Bad_Opcode },
8204     { Bad_Opcode },
8205     { Bad_Opcode },
8206     { Bad_Opcode },
8207     { Bad_Opcode },
8208     { Bad_Opcode },
8209     { Bad_Opcode },
8210     /* 80 */
8211     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
8212     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
8213     { "vfrczss",        { XM, EXd }, 0 },
8214     { "vfrczsd",        { XM, EXq }, 0 },
8215     { Bad_Opcode },
8216     { Bad_Opcode },
8217     { Bad_Opcode },
8218     { Bad_Opcode },
8219     /* 88 */
8220     { Bad_Opcode },
8221     { Bad_Opcode },
8222     { Bad_Opcode },
8223     { Bad_Opcode },
8224     { Bad_Opcode },
8225     { Bad_Opcode },
8226     { Bad_Opcode },
8227     { Bad_Opcode },
8228     /* 90 */
8229     { "vprotb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8230     { "vprotw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8231     { "vprotd",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8232     { "vprotq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8233     { "vpshlb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8234     { "vpshlw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8235     { "vpshld",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8236     { "vpshlq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8237     /* 98 */
8238     { "vpshab",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8239     { "vpshaw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8240     { "vpshad",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8241     { "vpshaq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8242     { Bad_Opcode },
8243     { Bad_Opcode },
8244     { Bad_Opcode },
8245     { Bad_Opcode },
8246     /* a0 */
8247     { Bad_Opcode },
8248     { Bad_Opcode },
8249     { Bad_Opcode },
8250     { Bad_Opcode },
8251     { Bad_Opcode },
8252     { Bad_Opcode },
8253     { Bad_Opcode },
8254     { Bad_Opcode },
8255     /* a8 */
8256     { Bad_Opcode },
8257     { Bad_Opcode },
8258     { Bad_Opcode },
8259     { Bad_Opcode },
8260     { Bad_Opcode },
8261     { Bad_Opcode },
8262     { Bad_Opcode },
8263     { Bad_Opcode },
8264     /* b0 */
8265     { Bad_Opcode },
8266     { Bad_Opcode },
8267     { Bad_Opcode },
8268     { Bad_Opcode },
8269     { Bad_Opcode },
8270     { Bad_Opcode },
8271     { Bad_Opcode },
8272     { Bad_Opcode },
8273     /* b8 */
8274     { Bad_Opcode },
8275     { Bad_Opcode },
8276     { Bad_Opcode },
8277     { Bad_Opcode },
8278     { Bad_Opcode },
8279     { Bad_Opcode },
8280     { Bad_Opcode },
8281     { Bad_Opcode },
8282     /* c0 */
8283     { Bad_Opcode },
8284     { "vphaddbw",       { XM, EXxmm }, 0 },
8285     { "vphaddbd",       { XM, EXxmm }, 0 },
8286     { "vphaddbq",       { XM, EXxmm }, 0 },
8287     { Bad_Opcode },
8288     { Bad_Opcode },
8289     { "vphaddwd",       { XM, EXxmm }, 0 },
8290     { "vphaddwq",       { XM, EXxmm }, 0 },
8291     /* c8 */
8292     { Bad_Opcode },
8293     { Bad_Opcode },
8294     { Bad_Opcode },
8295     { "vphadddq",       { XM, EXxmm }, 0 },
8296     { Bad_Opcode },
8297     { Bad_Opcode },
8298     { Bad_Opcode },
8299     { Bad_Opcode },
8300     /* d0 */
8301     { Bad_Opcode },
8302     { "vphaddubw",      { XM, EXxmm }, 0 },
8303     { "vphaddubd",      { XM, EXxmm }, 0 },
8304     { "vphaddubq",      { XM, EXxmm }, 0 },
8305     { Bad_Opcode },
8306     { Bad_Opcode },
8307     { "vphadduwd",      { XM, EXxmm }, 0 },
8308     { "vphadduwq",      { XM, EXxmm }, 0 },
8309     /* d8 */
8310     { Bad_Opcode },
8311     { Bad_Opcode },
8312     { Bad_Opcode },
8313     { "vphaddudq",      { XM, EXxmm }, 0 },
8314     { Bad_Opcode },
8315     { Bad_Opcode },
8316     { Bad_Opcode },
8317     { Bad_Opcode },
8318     /* e0 */
8319     { Bad_Opcode },
8320     { "vphsubbw",       { XM, EXxmm }, 0 },
8321     { "vphsubwd",       { XM, EXxmm }, 0 },
8322     { "vphsubdq",       { XM, EXxmm }, 0 },
8323     { Bad_Opcode },
8324     { Bad_Opcode },
8325     { Bad_Opcode },
8326     { Bad_Opcode },
8327     /* e8 */
8328     { Bad_Opcode },
8329     { Bad_Opcode },
8330     { Bad_Opcode },
8331     { Bad_Opcode },
8332     { Bad_Opcode },
8333     { Bad_Opcode },
8334     { Bad_Opcode },
8335     { Bad_Opcode },
8336     /* f0 */
8337     { Bad_Opcode },
8338     { Bad_Opcode },
8339     { Bad_Opcode },
8340     { Bad_Opcode },
8341     { Bad_Opcode },
8342     { Bad_Opcode },
8343     { Bad_Opcode },
8344     { Bad_Opcode },
8345     /* f8 */
8346     { Bad_Opcode },
8347     { Bad_Opcode },
8348     { Bad_Opcode },
8349     { Bad_Opcode },
8350     { Bad_Opcode },
8351     { Bad_Opcode },
8352     { Bad_Opcode },
8353     { Bad_Opcode },
8354   },
8355   /* XOP_0A */
8356   {
8357     /* 00 */
8358     { Bad_Opcode },
8359     { Bad_Opcode },
8360     { Bad_Opcode },
8361     { Bad_Opcode },
8362     { Bad_Opcode },
8363     { Bad_Opcode },
8364     { Bad_Opcode },
8365     { Bad_Opcode },
8366     /* 08 */
8367     { Bad_Opcode },
8368     { Bad_Opcode },
8369     { Bad_Opcode },
8370     { Bad_Opcode },
8371     { Bad_Opcode },
8372     { Bad_Opcode },
8373     { Bad_Opcode },
8374     { Bad_Opcode },
8375     /* 10 */
8376     { "bextr",  { Gv, Ev, Iq }, 0 },
8377     { Bad_Opcode },
8378     { REG_TABLE (REG_XOP_LWP) },
8379     { Bad_Opcode },
8380     { Bad_Opcode },
8381     { Bad_Opcode },
8382     { Bad_Opcode },
8383     { Bad_Opcode },
8384     /* 18 */
8385     { Bad_Opcode },
8386     { Bad_Opcode },
8387     { Bad_Opcode },
8388     { Bad_Opcode },
8389     { Bad_Opcode },
8390     { Bad_Opcode },
8391     { Bad_Opcode },
8392     { Bad_Opcode },
8393     /* 20 */
8394     { Bad_Opcode },
8395     { Bad_Opcode },
8396     { Bad_Opcode },
8397     { Bad_Opcode },
8398     { Bad_Opcode },
8399     { Bad_Opcode },
8400     { Bad_Opcode },
8401     { Bad_Opcode },
8402     /* 28 */
8403     { Bad_Opcode },
8404     { Bad_Opcode },
8405     { Bad_Opcode },
8406     { Bad_Opcode },
8407     { Bad_Opcode },
8408     { Bad_Opcode },
8409     { Bad_Opcode },
8410     { Bad_Opcode },
8411     /* 30 */
8412     { Bad_Opcode },
8413     { Bad_Opcode },
8414     { Bad_Opcode },
8415     { Bad_Opcode },
8416     { Bad_Opcode },
8417     { Bad_Opcode },
8418     { Bad_Opcode },
8419     { Bad_Opcode },
8420     /* 38 */
8421     { Bad_Opcode },
8422     { Bad_Opcode },
8423     { Bad_Opcode },
8424     { Bad_Opcode },
8425     { Bad_Opcode },
8426     { Bad_Opcode },
8427     { Bad_Opcode },
8428     { Bad_Opcode },
8429     /* 40 */
8430     { Bad_Opcode },
8431     { Bad_Opcode },
8432     { Bad_Opcode },
8433     { Bad_Opcode },
8434     { Bad_Opcode },
8435     { Bad_Opcode },
8436     { Bad_Opcode },
8437     { Bad_Opcode },
8438     /* 48 */
8439     { Bad_Opcode },
8440     { Bad_Opcode },
8441     { Bad_Opcode },
8442     { Bad_Opcode },
8443     { Bad_Opcode },
8444     { Bad_Opcode },
8445     { Bad_Opcode },
8446     { Bad_Opcode },
8447     /* 50 */
8448     { Bad_Opcode },
8449     { Bad_Opcode },
8450     { Bad_Opcode },
8451     { Bad_Opcode },
8452     { Bad_Opcode },
8453     { Bad_Opcode },
8454     { Bad_Opcode },
8455     { Bad_Opcode },
8456     /* 58 */
8457     { Bad_Opcode },
8458     { Bad_Opcode },
8459     { Bad_Opcode },
8460     { Bad_Opcode },
8461     { Bad_Opcode },
8462     { Bad_Opcode },
8463     { Bad_Opcode },
8464     { Bad_Opcode },
8465     /* 60 */
8466     { Bad_Opcode },
8467     { Bad_Opcode },
8468     { Bad_Opcode },
8469     { Bad_Opcode },
8470     { Bad_Opcode },
8471     { Bad_Opcode },
8472     { Bad_Opcode },
8473     { Bad_Opcode },
8474     /* 68 */
8475     { Bad_Opcode },
8476     { Bad_Opcode },
8477     { Bad_Opcode },
8478     { Bad_Opcode },
8479     { Bad_Opcode },
8480     { Bad_Opcode },
8481     { Bad_Opcode },
8482     { Bad_Opcode },
8483     /* 70 */
8484     { Bad_Opcode },
8485     { Bad_Opcode },
8486     { Bad_Opcode },
8487     { Bad_Opcode },
8488     { Bad_Opcode },
8489     { Bad_Opcode },
8490     { Bad_Opcode },
8491     { Bad_Opcode },
8492     /* 78 */
8493     { Bad_Opcode },
8494     { Bad_Opcode },
8495     { Bad_Opcode },
8496     { Bad_Opcode },
8497     { Bad_Opcode },
8498     { Bad_Opcode },
8499     { Bad_Opcode },
8500     { Bad_Opcode },
8501     /* 80 */
8502     { Bad_Opcode },
8503     { Bad_Opcode },
8504     { Bad_Opcode },
8505     { Bad_Opcode },
8506     { Bad_Opcode },
8507     { Bad_Opcode },
8508     { Bad_Opcode },
8509     { Bad_Opcode },
8510     /* 88 */
8511     { Bad_Opcode },
8512     { Bad_Opcode },
8513     { Bad_Opcode },
8514     { Bad_Opcode },
8515     { Bad_Opcode },
8516     { Bad_Opcode },
8517     { Bad_Opcode },
8518     { Bad_Opcode },
8519     /* 90 */
8520     { Bad_Opcode },
8521     { Bad_Opcode },
8522     { Bad_Opcode },
8523     { Bad_Opcode },
8524     { Bad_Opcode },
8525     { Bad_Opcode },
8526     { Bad_Opcode },
8527     { Bad_Opcode },
8528     /* 98 */
8529     { Bad_Opcode },
8530     { Bad_Opcode },
8531     { Bad_Opcode },
8532     { Bad_Opcode },
8533     { Bad_Opcode },
8534     { Bad_Opcode },
8535     { Bad_Opcode },
8536     { Bad_Opcode },
8537     /* a0 */
8538     { Bad_Opcode },
8539     { Bad_Opcode },
8540     { Bad_Opcode },
8541     { Bad_Opcode },
8542     { Bad_Opcode },
8543     { Bad_Opcode },
8544     { Bad_Opcode },
8545     { Bad_Opcode },
8546     /* a8 */
8547     { Bad_Opcode },
8548     { Bad_Opcode },
8549     { Bad_Opcode },
8550     { Bad_Opcode },
8551     { Bad_Opcode },
8552     { Bad_Opcode },
8553     { Bad_Opcode },
8554     { Bad_Opcode },
8555     /* b0 */
8556     { Bad_Opcode },
8557     { Bad_Opcode },
8558     { Bad_Opcode },
8559     { Bad_Opcode },
8560     { Bad_Opcode },
8561     { Bad_Opcode },
8562     { Bad_Opcode },
8563     { Bad_Opcode },
8564     /* b8 */
8565     { Bad_Opcode },
8566     { Bad_Opcode },
8567     { Bad_Opcode },
8568     { Bad_Opcode },
8569     { Bad_Opcode },
8570     { Bad_Opcode },
8571     { Bad_Opcode },
8572     { Bad_Opcode },
8573     /* c0 */
8574     { Bad_Opcode },
8575     { Bad_Opcode },
8576     { Bad_Opcode },
8577     { Bad_Opcode },
8578     { Bad_Opcode },
8579     { Bad_Opcode },
8580     { Bad_Opcode },
8581     { Bad_Opcode },
8582     /* c8 */
8583     { Bad_Opcode },
8584     { Bad_Opcode },
8585     { Bad_Opcode },
8586     { Bad_Opcode },
8587     { Bad_Opcode },
8588     { Bad_Opcode },
8589     { Bad_Opcode },
8590     { Bad_Opcode },
8591     /* d0 */
8592     { Bad_Opcode },
8593     { Bad_Opcode },
8594     { Bad_Opcode },
8595     { Bad_Opcode },
8596     { Bad_Opcode },
8597     { Bad_Opcode },
8598     { Bad_Opcode },
8599     { Bad_Opcode },
8600     /* d8 */
8601     { Bad_Opcode },
8602     { Bad_Opcode },
8603     { Bad_Opcode },
8604     { Bad_Opcode },
8605     { Bad_Opcode },
8606     { Bad_Opcode },
8607     { Bad_Opcode },
8608     { Bad_Opcode },
8609     /* e0 */
8610     { Bad_Opcode },
8611     { Bad_Opcode },
8612     { Bad_Opcode },
8613     { Bad_Opcode },
8614     { Bad_Opcode },
8615     { Bad_Opcode },
8616     { Bad_Opcode },
8617     { Bad_Opcode },
8618     /* e8 */
8619     { Bad_Opcode },
8620     { Bad_Opcode },
8621     { Bad_Opcode },
8622     { Bad_Opcode },
8623     { Bad_Opcode },
8624     { Bad_Opcode },
8625     { Bad_Opcode },
8626     { Bad_Opcode },
8627     /* f0 */
8628     { Bad_Opcode },
8629     { Bad_Opcode },
8630     { Bad_Opcode },
8631     { Bad_Opcode },
8632     { Bad_Opcode },
8633     { Bad_Opcode },
8634     { Bad_Opcode },
8635     { Bad_Opcode },
8636     /* f8 */
8637     { Bad_Opcode },
8638     { Bad_Opcode },
8639     { Bad_Opcode },
8640     { Bad_Opcode },
8641     { Bad_Opcode },
8642     { Bad_Opcode },
8643     { Bad_Opcode },
8644     { Bad_Opcode },
8645   },
8646 };
8647
8648 static const struct dis386 vex_table[][256] = {
8649   /* VEX_0F */
8650   {
8651     /* 00 */
8652     { Bad_Opcode },
8653     { Bad_Opcode },
8654     { Bad_Opcode },
8655     { Bad_Opcode },
8656     { Bad_Opcode },
8657     { Bad_Opcode },
8658     { Bad_Opcode },
8659     { Bad_Opcode },
8660     /* 08 */
8661     { Bad_Opcode },
8662     { Bad_Opcode },
8663     { Bad_Opcode },
8664     { Bad_Opcode },
8665     { Bad_Opcode },
8666     { Bad_Opcode },
8667     { Bad_Opcode },
8668     { Bad_Opcode },
8669     /* 10 */
8670     { PREFIX_TABLE (PREFIX_VEX_0F10) },
8671     { PREFIX_TABLE (PREFIX_VEX_0F11) },
8672     { PREFIX_TABLE (PREFIX_VEX_0F12) },
8673     { MOD_TABLE (MOD_VEX_0F13) },
8674     { VEX_W_TABLE (VEX_W_0F14) },
8675     { VEX_W_TABLE (VEX_W_0F15) },
8676     { PREFIX_TABLE (PREFIX_VEX_0F16) },
8677     { MOD_TABLE (MOD_VEX_0F17) },
8678     /* 18 */
8679     { Bad_Opcode },
8680     { Bad_Opcode },
8681     { Bad_Opcode },
8682     { Bad_Opcode },
8683     { Bad_Opcode },
8684     { Bad_Opcode },
8685     { Bad_Opcode },
8686     { Bad_Opcode },
8687     /* 20 */
8688     { Bad_Opcode },
8689     { Bad_Opcode },
8690     { Bad_Opcode },
8691     { Bad_Opcode },
8692     { Bad_Opcode },
8693     { Bad_Opcode },
8694     { Bad_Opcode },
8695     { Bad_Opcode },
8696     /* 28 */
8697     { VEX_W_TABLE (VEX_W_0F28) },
8698     { VEX_W_TABLE (VEX_W_0F29) },
8699     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8700     { MOD_TABLE (MOD_VEX_0F2B) },
8701     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8702     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8703     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8704     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8705     /* 30 */
8706     { Bad_Opcode },
8707     { Bad_Opcode },
8708     { Bad_Opcode },
8709     { Bad_Opcode },
8710     { Bad_Opcode },
8711     { Bad_Opcode },
8712     { Bad_Opcode },
8713     { Bad_Opcode },
8714     /* 38 */
8715     { Bad_Opcode },
8716     { Bad_Opcode },
8717     { Bad_Opcode },
8718     { Bad_Opcode },
8719     { Bad_Opcode },
8720     { Bad_Opcode },
8721     { Bad_Opcode },
8722     { Bad_Opcode },
8723     /* 40 */
8724     { Bad_Opcode },
8725     { PREFIX_TABLE (PREFIX_VEX_0F41) },
8726     { PREFIX_TABLE (PREFIX_VEX_0F42) },
8727     { Bad_Opcode },
8728     { PREFIX_TABLE (PREFIX_VEX_0F44) },
8729     { PREFIX_TABLE (PREFIX_VEX_0F45) },
8730     { PREFIX_TABLE (PREFIX_VEX_0F46) },
8731     { PREFIX_TABLE (PREFIX_VEX_0F47) },
8732     /* 48 */
8733     { Bad_Opcode },
8734     { Bad_Opcode },
8735     { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8736     { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8737     { Bad_Opcode },
8738     { Bad_Opcode },
8739     { Bad_Opcode },
8740     { Bad_Opcode },
8741     /* 50 */
8742     { MOD_TABLE (MOD_VEX_0F50) },
8743     { PREFIX_TABLE (PREFIX_VEX_0F51) },
8744     { PREFIX_TABLE (PREFIX_VEX_0F52) },
8745     { PREFIX_TABLE (PREFIX_VEX_0F53) },
8746     { "vandpX",         { XM, Vex, EXx }, 0 },
8747     { "vandnpX",        { XM, Vex, EXx }, 0 },
8748     { "vorpX",          { XM, Vex, EXx }, 0 },
8749     { "vxorpX",         { XM, Vex, EXx }, 0 },
8750     /* 58 */
8751     { PREFIX_TABLE (PREFIX_VEX_0F58) },
8752     { PREFIX_TABLE (PREFIX_VEX_0F59) },
8753     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8754     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8755     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8756     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8757     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8758     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8759     /* 60 */
8760     { PREFIX_TABLE (PREFIX_VEX_0F60) },
8761     { PREFIX_TABLE (PREFIX_VEX_0F61) },
8762     { PREFIX_TABLE (PREFIX_VEX_0F62) },
8763     { PREFIX_TABLE (PREFIX_VEX_0F63) },
8764     { PREFIX_TABLE (PREFIX_VEX_0F64) },
8765     { PREFIX_TABLE (PREFIX_VEX_0F65) },
8766     { PREFIX_TABLE (PREFIX_VEX_0F66) },
8767     { PREFIX_TABLE (PREFIX_VEX_0F67) },
8768     /* 68 */
8769     { PREFIX_TABLE (PREFIX_VEX_0F68) },
8770     { PREFIX_TABLE (PREFIX_VEX_0F69) },
8771     { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8772     { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8773     { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8774     { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8775     { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8776     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8777     /* 70 */
8778     { PREFIX_TABLE (PREFIX_VEX_0F70) },
8779     { REG_TABLE (REG_VEX_0F71) },
8780     { REG_TABLE (REG_VEX_0F72) },
8781     { REG_TABLE (REG_VEX_0F73) },
8782     { PREFIX_TABLE (PREFIX_VEX_0F74) },
8783     { PREFIX_TABLE (PREFIX_VEX_0F75) },
8784     { PREFIX_TABLE (PREFIX_VEX_0F76) },
8785     { PREFIX_TABLE (PREFIX_VEX_0F77) },
8786     /* 78 */
8787     { Bad_Opcode },
8788     { Bad_Opcode },
8789     { Bad_Opcode },
8790     { Bad_Opcode },
8791     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8792     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8793     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8794     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8795     /* 80 */
8796     { Bad_Opcode },
8797     { Bad_Opcode },
8798     { Bad_Opcode },
8799     { Bad_Opcode },
8800     { Bad_Opcode },
8801     { Bad_Opcode },
8802     { Bad_Opcode },
8803     { Bad_Opcode },
8804     /* 88 */
8805     { Bad_Opcode },
8806     { Bad_Opcode },
8807     { Bad_Opcode },
8808     { Bad_Opcode },
8809     { Bad_Opcode },
8810     { Bad_Opcode },
8811     { Bad_Opcode },
8812     { Bad_Opcode },
8813     /* 90 */
8814     { PREFIX_TABLE (PREFIX_VEX_0F90) },
8815     { PREFIX_TABLE (PREFIX_VEX_0F91) },
8816     { PREFIX_TABLE (PREFIX_VEX_0F92) },
8817     { PREFIX_TABLE (PREFIX_VEX_0F93) },
8818     { Bad_Opcode },
8819     { Bad_Opcode },
8820     { Bad_Opcode },
8821     { Bad_Opcode },
8822     /* 98 */
8823     { PREFIX_TABLE (PREFIX_VEX_0F98) },
8824     { PREFIX_TABLE (PREFIX_VEX_0F99) },
8825     { Bad_Opcode },
8826     { Bad_Opcode },
8827     { Bad_Opcode },
8828     { Bad_Opcode },
8829     { Bad_Opcode },
8830     { Bad_Opcode },
8831     /* a0 */
8832     { Bad_Opcode },
8833     { Bad_Opcode },
8834     { Bad_Opcode },
8835     { Bad_Opcode },
8836     { Bad_Opcode },
8837     { Bad_Opcode },
8838     { Bad_Opcode },
8839     { Bad_Opcode },
8840     /* a8 */
8841     { Bad_Opcode },
8842     { Bad_Opcode },
8843     { Bad_Opcode },
8844     { Bad_Opcode },
8845     { Bad_Opcode },
8846     { Bad_Opcode },
8847     { REG_TABLE (REG_VEX_0FAE) },
8848     { Bad_Opcode },
8849     /* b0 */
8850     { Bad_Opcode },
8851     { Bad_Opcode },
8852     { Bad_Opcode },
8853     { Bad_Opcode },
8854     { Bad_Opcode },
8855     { Bad_Opcode },
8856     { Bad_Opcode },
8857     { Bad_Opcode },
8858     /* b8 */
8859     { Bad_Opcode },
8860     { Bad_Opcode },
8861     { Bad_Opcode },
8862     { Bad_Opcode },
8863     { Bad_Opcode },
8864     { Bad_Opcode },
8865     { Bad_Opcode },
8866     { Bad_Opcode },
8867     /* c0 */
8868     { Bad_Opcode },
8869     { Bad_Opcode },
8870     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8871     { Bad_Opcode },
8872     { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8873     { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8874     { "vshufpX",        { XM, Vex, EXx, Ib }, 0 },
8875     { Bad_Opcode },
8876     /* c8 */
8877     { Bad_Opcode },
8878     { Bad_Opcode },
8879     { Bad_Opcode },
8880     { Bad_Opcode },
8881     { Bad_Opcode },
8882     { Bad_Opcode },
8883     { Bad_Opcode },
8884     { Bad_Opcode },
8885     /* d0 */
8886     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8887     { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8888     { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8889     { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8890     { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8891     { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8892     { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8893     { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8894     /* d8 */
8895     { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8896     { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8897     { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8898     { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8899     { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8900     { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8901     { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8902     { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8903     /* e0 */
8904     { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8905     { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8906     { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8907     { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8908     { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8909     { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8910     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8911     { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8912     /* e8 */
8913     { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8914     { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8915     { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8916     { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8917     { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8918     { PREFIX_TABLE (PREFIX_VEX_0FED) },
8919     { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8920     { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8921     /* f0 */
8922     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8923     { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8924     { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8925     { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8926     { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8927     { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8928     { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8929     { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8930     /* f8 */
8931     { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8932     { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8933     { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8934     { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8935     { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8936     { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8937     { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8938     { Bad_Opcode },
8939   },
8940   /* VEX_0F38 */
8941   {
8942     /* 00 */
8943     { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8944     { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8945     { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8946     { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8947     { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8948     { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8949     { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8950     { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8951     /* 08 */
8952     { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8953     { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8954     { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8955     { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8956     { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8957     { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8958     { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8959     { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8960     /* 10 */
8961     { Bad_Opcode },
8962     { Bad_Opcode },
8963     { Bad_Opcode },
8964     { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8965     { Bad_Opcode },
8966     { Bad_Opcode },
8967     { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8968     { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8969     /* 18 */
8970     { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8971     { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8972     { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8973     { Bad_Opcode },
8974     { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8975     { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8976     { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8977     { Bad_Opcode },
8978     /* 20 */
8979     { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8980     { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8981     { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8982     { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8983     { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8984     { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8985     { Bad_Opcode },
8986     { Bad_Opcode },
8987     /* 28 */
8988     { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8989     { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8990     { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8991     { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8992     { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8993     { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8994     { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8995     { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8996     /* 30 */
8997     { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8998     { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8999     { PREFIX_TABLE (PREFIX_VEX_0F3832) },
9000     { PREFIX_TABLE (PREFIX_VEX_0F3833) },
9001     { PREFIX_TABLE (PREFIX_VEX_0F3834) },
9002     { PREFIX_TABLE (PREFIX_VEX_0F3835) },
9003     { PREFIX_TABLE (PREFIX_VEX_0F3836) },
9004     { PREFIX_TABLE (PREFIX_VEX_0F3837) },
9005     /* 38 */
9006     { PREFIX_TABLE (PREFIX_VEX_0F3838) },
9007     { PREFIX_TABLE (PREFIX_VEX_0F3839) },
9008     { PREFIX_TABLE (PREFIX_VEX_0F383A) },
9009     { PREFIX_TABLE (PREFIX_VEX_0F383B) },
9010     { PREFIX_TABLE (PREFIX_VEX_0F383C) },
9011     { PREFIX_TABLE (PREFIX_VEX_0F383D) },
9012     { PREFIX_TABLE (PREFIX_VEX_0F383E) },
9013     { PREFIX_TABLE (PREFIX_VEX_0F383F) },
9014     /* 40 */
9015     { PREFIX_TABLE (PREFIX_VEX_0F3840) },
9016     { PREFIX_TABLE (PREFIX_VEX_0F3841) },
9017     { Bad_Opcode },
9018     { Bad_Opcode },
9019     { Bad_Opcode },
9020     { PREFIX_TABLE (PREFIX_VEX_0F3845) },
9021     { PREFIX_TABLE (PREFIX_VEX_0F3846) },
9022     { PREFIX_TABLE (PREFIX_VEX_0F3847) },
9023     /* 48 */
9024     { Bad_Opcode },
9025     { Bad_Opcode },
9026     { Bad_Opcode },
9027     { Bad_Opcode },
9028     { Bad_Opcode },
9029     { Bad_Opcode },
9030     { Bad_Opcode },
9031     { Bad_Opcode },
9032     /* 50 */
9033     { Bad_Opcode },
9034     { Bad_Opcode },
9035     { Bad_Opcode },
9036     { Bad_Opcode },
9037     { Bad_Opcode },
9038     { Bad_Opcode },
9039     { Bad_Opcode },
9040     { Bad_Opcode },
9041     /* 58 */
9042     { PREFIX_TABLE (PREFIX_VEX_0F3858) },
9043     { PREFIX_TABLE (PREFIX_VEX_0F3859) },
9044     { PREFIX_TABLE (PREFIX_VEX_0F385A) },
9045     { Bad_Opcode },
9046     { Bad_Opcode },
9047     { Bad_Opcode },
9048     { Bad_Opcode },
9049     { Bad_Opcode },
9050     /* 60 */
9051     { Bad_Opcode },
9052     { Bad_Opcode },
9053     { Bad_Opcode },
9054     { Bad_Opcode },
9055     { Bad_Opcode },
9056     { Bad_Opcode },
9057     { Bad_Opcode },
9058     { Bad_Opcode },
9059     /* 68 */
9060     { Bad_Opcode },
9061     { Bad_Opcode },
9062     { Bad_Opcode },
9063     { Bad_Opcode },
9064     { Bad_Opcode },
9065     { Bad_Opcode },
9066     { Bad_Opcode },
9067     { Bad_Opcode },
9068     /* 70 */
9069     { Bad_Opcode },
9070     { Bad_Opcode },
9071     { Bad_Opcode },
9072     { Bad_Opcode },
9073     { Bad_Opcode },
9074     { Bad_Opcode },
9075     { Bad_Opcode },
9076     { Bad_Opcode },
9077     /* 78 */
9078     { PREFIX_TABLE (PREFIX_VEX_0F3878) },
9079     { PREFIX_TABLE (PREFIX_VEX_0F3879) },
9080     { Bad_Opcode },
9081     { Bad_Opcode },
9082     { Bad_Opcode },
9083     { Bad_Opcode },
9084     { Bad_Opcode },
9085     { Bad_Opcode },
9086     /* 80 */
9087     { Bad_Opcode },
9088     { Bad_Opcode },
9089     { Bad_Opcode },
9090     { Bad_Opcode },
9091     { Bad_Opcode },
9092     { Bad_Opcode },
9093     { Bad_Opcode },
9094     { Bad_Opcode },
9095     /* 88 */
9096     { Bad_Opcode },
9097     { Bad_Opcode },
9098     { Bad_Opcode },
9099     { Bad_Opcode },
9100     { PREFIX_TABLE (PREFIX_VEX_0F388C) },
9101     { Bad_Opcode },
9102     { PREFIX_TABLE (PREFIX_VEX_0F388E) },
9103     { Bad_Opcode },
9104     /* 90 */
9105     { PREFIX_TABLE (PREFIX_VEX_0F3890) },
9106     { PREFIX_TABLE (PREFIX_VEX_0F3891) },
9107     { PREFIX_TABLE (PREFIX_VEX_0F3892) },
9108     { PREFIX_TABLE (PREFIX_VEX_0F3893) },
9109     { Bad_Opcode },
9110     { Bad_Opcode },
9111     { PREFIX_TABLE (PREFIX_VEX_0F3896) },
9112     { PREFIX_TABLE (PREFIX_VEX_0F3897) },
9113     /* 98 */
9114     { PREFIX_TABLE (PREFIX_VEX_0F3898) },
9115     { PREFIX_TABLE (PREFIX_VEX_0F3899) },
9116     { PREFIX_TABLE (PREFIX_VEX_0F389A) },
9117     { PREFIX_TABLE (PREFIX_VEX_0F389B) },
9118     { PREFIX_TABLE (PREFIX_VEX_0F389C) },
9119     { PREFIX_TABLE (PREFIX_VEX_0F389D) },
9120     { PREFIX_TABLE (PREFIX_VEX_0F389E) },
9121     { PREFIX_TABLE (PREFIX_VEX_0F389F) },
9122     /* a0 */
9123     { Bad_Opcode },
9124     { Bad_Opcode },
9125     { Bad_Opcode },
9126     { Bad_Opcode },
9127     { Bad_Opcode },
9128     { Bad_Opcode },
9129     { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
9130     { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
9131     /* a8 */
9132     { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
9133     { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
9134     { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
9135     { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
9136     { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
9137     { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
9138     { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
9139     { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
9140     /* b0 */
9141     { Bad_Opcode },
9142     { Bad_Opcode },
9143     { Bad_Opcode },
9144     { Bad_Opcode },
9145     { Bad_Opcode },
9146     { Bad_Opcode },
9147     { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
9148     { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
9149     /* b8 */
9150     { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
9151     { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
9152     { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
9153     { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
9154     { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
9155     { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
9156     { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
9157     { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
9158     /* c0 */
9159     { Bad_Opcode },
9160     { Bad_Opcode },
9161     { Bad_Opcode },
9162     { Bad_Opcode },
9163     { Bad_Opcode },
9164     { Bad_Opcode },
9165     { Bad_Opcode },
9166     { Bad_Opcode },
9167     /* c8 */
9168     { Bad_Opcode },
9169     { Bad_Opcode },
9170     { Bad_Opcode },
9171     { Bad_Opcode },
9172     { Bad_Opcode },
9173     { Bad_Opcode },
9174     { Bad_Opcode },
9175     { PREFIX_TABLE (PREFIX_VEX_0F38CF) },
9176     /* d0 */
9177     { Bad_Opcode },
9178     { Bad_Opcode },
9179     { Bad_Opcode },
9180     { Bad_Opcode },
9181     { Bad_Opcode },
9182     { Bad_Opcode },
9183     { Bad_Opcode },
9184     { Bad_Opcode },
9185     /* d8 */
9186     { Bad_Opcode },
9187     { Bad_Opcode },
9188     { Bad_Opcode },
9189     { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
9190     { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
9191     { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
9192     { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
9193     { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
9194     /* e0 */
9195     { Bad_Opcode },
9196     { Bad_Opcode },
9197     { Bad_Opcode },
9198     { Bad_Opcode },
9199     { Bad_Opcode },
9200     { Bad_Opcode },
9201     { Bad_Opcode },
9202     { Bad_Opcode },
9203     /* e8 */
9204     { Bad_Opcode },
9205     { Bad_Opcode },
9206     { Bad_Opcode },
9207     { Bad_Opcode },
9208     { Bad_Opcode },
9209     { Bad_Opcode },
9210     { Bad_Opcode },
9211     { Bad_Opcode },
9212     /* f0 */
9213     { Bad_Opcode },
9214     { Bad_Opcode },
9215     { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
9216     { REG_TABLE (REG_VEX_0F38F3) },
9217     { Bad_Opcode },
9218     { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
9219     { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
9220     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
9221     /* f8 */
9222     { Bad_Opcode },
9223     { Bad_Opcode },
9224     { Bad_Opcode },
9225     { Bad_Opcode },
9226     { Bad_Opcode },
9227     { Bad_Opcode },
9228     { Bad_Opcode },
9229     { Bad_Opcode },
9230   },
9231   /* VEX_0F3A */
9232   {
9233     /* 00 */
9234     { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
9235     { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
9236     { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
9237     { Bad_Opcode },
9238     { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
9239     { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
9240     { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
9241     { Bad_Opcode },
9242     /* 08 */
9243     { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
9244     { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
9245     { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
9246     { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
9247     { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
9248     { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
9249     { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
9250     { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
9251     /* 10 */
9252     { Bad_Opcode },
9253     { Bad_Opcode },
9254     { Bad_Opcode },
9255     { Bad_Opcode },
9256     { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
9257     { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
9258     { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
9259     { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
9260     /* 18 */
9261     { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
9262     { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
9263     { Bad_Opcode },
9264     { Bad_Opcode },
9265     { Bad_Opcode },
9266     { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
9267     { Bad_Opcode },
9268     { Bad_Opcode },
9269     /* 20 */
9270     { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
9271     { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
9272     { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
9273     { Bad_Opcode },
9274     { Bad_Opcode },
9275     { Bad_Opcode },
9276     { Bad_Opcode },
9277     { Bad_Opcode },
9278     /* 28 */
9279     { Bad_Opcode },
9280     { Bad_Opcode },
9281     { Bad_Opcode },
9282     { Bad_Opcode },
9283     { Bad_Opcode },
9284     { Bad_Opcode },
9285     { Bad_Opcode },
9286     { Bad_Opcode },
9287     /* 30 */
9288     { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
9289     { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
9290     { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
9291     { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
9292     { Bad_Opcode },
9293     { Bad_Opcode },
9294     { Bad_Opcode },
9295     { Bad_Opcode },
9296     /* 38 */
9297     { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
9298     { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
9299     { Bad_Opcode },
9300     { Bad_Opcode },
9301     { Bad_Opcode },
9302     { Bad_Opcode },
9303     { Bad_Opcode },
9304     { Bad_Opcode },
9305     /* 40 */
9306     { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
9307     { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
9308     { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
9309     { Bad_Opcode },
9310     { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
9311     { Bad_Opcode },
9312     { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
9313     { Bad_Opcode },
9314     /* 48 */
9315     { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
9316     { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
9317     { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
9318     { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
9319     { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
9320     { Bad_Opcode },
9321     { Bad_Opcode },
9322     { Bad_Opcode },
9323     /* 50 */
9324     { Bad_Opcode },
9325     { Bad_Opcode },
9326     { Bad_Opcode },
9327     { Bad_Opcode },
9328     { Bad_Opcode },
9329     { Bad_Opcode },
9330     { Bad_Opcode },
9331     { Bad_Opcode },
9332     /* 58 */
9333     { Bad_Opcode },
9334     { Bad_Opcode },
9335     { Bad_Opcode },
9336     { Bad_Opcode },
9337     { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9338     { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9339     { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9340     { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9341     /* 60 */
9342     { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9343     { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9344     { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9345     { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9346     { Bad_Opcode },
9347     { Bad_Opcode },
9348     { Bad_Opcode },
9349     { Bad_Opcode },
9350     /* 68 */
9351     { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9352     { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9353     { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9354     { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9355     { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9356     { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9357     { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9358     { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9359     /* 70 */
9360     { Bad_Opcode },
9361     { Bad_Opcode },
9362     { Bad_Opcode },
9363     { Bad_Opcode },
9364     { Bad_Opcode },
9365     { Bad_Opcode },
9366     { Bad_Opcode },
9367     { Bad_Opcode },
9368     /* 78 */
9369     { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9370     { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9371     { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9372     { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9373     { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9374     { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9375     { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9376     { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9377     /* 80 */
9378     { Bad_Opcode },
9379     { Bad_Opcode },
9380     { Bad_Opcode },
9381     { Bad_Opcode },
9382     { Bad_Opcode },
9383     { Bad_Opcode },
9384     { Bad_Opcode },
9385     { Bad_Opcode },
9386     /* 88 */
9387     { Bad_Opcode },
9388     { Bad_Opcode },
9389     { Bad_Opcode },
9390     { Bad_Opcode },
9391     { Bad_Opcode },
9392     { Bad_Opcode },
9393     { Bad_Opcode },
9394     { Bad_Opcode },
9395     /* 90 */
9396     { Bad_Opcode },
9397     { Bad_Opcode },
9398     { Bad_Opcode },
9399     { Bad_Opcode },
9400     { Bad_Opcode },
9401     { Bad_Opcode },
9402     { Bad_Opcode },
9403     { Bad_Opcode },
9404     /* 98 */
9405     { Bad_Opcode },
9406     { Bad_Opcode },
9407     { Bad_Opcode },
9408     { Bad_Opcode },
9409     { Bad_Opcode },
9410     { Bad_Opcode },
9411     { Bad_Opcode },
9412     { Bad_Opcode },
9413     /* a0 */
9414     { Bad_Opcode },
9415     { Bad_Opcode },
9416     { Bad_Opcode },
9417     { Bad_Opcode },
9418     { Bad_Opcode },
9419     { Bad_Opcode },
9420     { Bad_Opcode },
9421     { Bad_Opcode },
9422     /* a8 */
9423     { Bad_Opcode },
9424     { Bad_Opcode },
9425     { Bad_Opcode },
9426     { Bad_Opcode },
9427     { Bad_Opcode },
9428     { Bad_Opcode },
9429     { Bad_Opcode },
9430     { Bad_Opcode },
9431     /* b0 */
9432     { Bad_Opcode },
9433     { Bad_Opcode },
9434     { Bad_Opcode },
9435     { Bad_Opcode },
9436     { Bad_Opcode },
9437     { Bad_Opcode },
9438     { Bad_Opcode },
9439     { Bad_Opcode },
9440     /* b8 */
9441     { Bad_Opcode },
9442     { Bad_Opcode },
9443     { Bad_Opcode },
9444     { Bad_Opcode },
9445     { Bad_Opcode },
9446     { Bad_Opcode },
9447     { Bad_Opcode },
9448     { Bad_Opcode },
9449     /* c0 */
9450     { Bad_Opcode },
9451     { Bad_Opcode },
9452     { Bad_Opcode },
9453     { Bad_Opcode },
9454     { Bad_Opcode },
9455     { Bad_Opcode },
9456     { Bad_Opcode },
9457     { Bad_Opcode },
9458     /* c8 */
9459     { Bad_Opcode },
9460     { Bad_Opcode },
9461     { Bad_Opcode },
9462     { Bad_Opcode },
9463     { Bad_Opcode },
9464     { Bad_Opcode },
9465     { PREFIX_TABLE(PREFIX_VEX_0F3ACE) },
9466     { PREFIX_TABLE(PREFIX_VEX_0F3ACF) },
9467     /* d0 */
9468     { Bad_Opcode },
9469     { Bad_Opcode },
9470     { Bad_Opcode },
9471     { Bad_Opcode },
9472     { Bad_Opcode },
9473     { Bad_Opcode },
9474     { Bad_Opcode },
9475     { Bad_Opcode },
9476     /* d8 */
9477     { Bad_Opcode },
9478     { Bad_Opcode },
9479     { Bad_Opcode },
9480     { Bad_Opcode },
9481     { Bad_Opcode },
9482     { Bad_Opcode },
9483     { Bad_Opcode },
9484     { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9485     /* e0 */
9486     { Bad_Opcode },
9487     { Bad_Opcode },
9488     { Bad_Opcode },
9489     { Bad_Opcode },
9490     { Bad_Opcode },
9491     { Bad_Opcode },
9492     { Bad_Opcode },
9493     { Bad_Opcode },
9494     /* e8 */
9495     { Bad_Opcode },
9496     { Bad_Opcode },
9497     { Bad_Opcode },
9498     { Bad_Opcode },
9499     { Bad_Opcode },
9500     { Bad_Opcode },
9501     { Bad_Opcode },
9502     { Bad_Opcode },
9503     /* f0 */
9504     { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9505     { Bad_Opcode },
9506     { Bad_Opcode },
9507     { Bad_Opcode },
9508     { Bad_Opcode },
9509     { Bad_Opcode },
9510     { Bad_Opcode },
9511     { Bad_Opcode },
9512     /* f8 */
9513     { Bad_Opcode },
9514     { Bad_Opcode },
9515     { Bad_Opcode },
9516     { Bad_Opcode },
9517     { Bad_Opcode },
9518     { Bad_Opcode },
9519     { Bad_Opcode },
9520     { Bad_Opcode },
9521   },
9522 };
9523
9524 #define NEED_OPCODE_TABLE
9525 #include "i386-dis-evex.h"
9526 #undef NEED_OPCODE_TABLE
9527 static const struct dis386 vex_len_table[][2] = {
9528   /* VEX_LEN_0F10_P_1 */
9529   {
9530     { VEX_W_TABLE (VEX_W_0F10_P_1) },
9531     { VEX_W_TABLE (VEX_W_0F10_P_1) },
9532   },
9533
9534   /* VEX_LEN_0F10_P_3 */
9535   {
9536     { VEX_W_TABLE (VEX_W_0F10_P_3) },
9537     { VEX_W_TABLE (VEX_W_0F10_P_3) },
9538   },
9539
9540   /* VEX_LEN_0F11_P_1 */
9541   {
9542     { VEX_W_TABLE (VEX_W_0F11_P_1) },
9543     { VEX_W_TABLE (VEX_W_0F11_P_1) },
9544   },
9545
9546   /* VEX_LEN_0F11_P_3 */
9547   {
9548     { VEX_W_TABLE (VEX_W_0F11_P_3) },
9549     { VEX_W_TABLE (VEX_W_0F11_P_3) },
9550   },
9551
9552   /* VEX_LEN_0F12_P_0_M_0 */
9553   {
9554     { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) },
9555   },
9556
9557   /* VEX_LEN_0F12_P_0_M_1 */
9558   {
9559     { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) },
9560   },
9561
9562   /* VEX_LEN_0F12_P_2 */
9563   {
9564     { VEX_W_TABLE (VEX_W_0F12_P_2) },
9565   },
9566
9567   /* VEX_LEN_0F13_M_0 */
9568   {
9569     { VEX_W_TABLE (VEX_W_0F13_M_0) },
9570   },
9571
9572   /* VEX_LEN_0F16_P_0_M_0 */
9573   {
9574     { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) },
9575   },
9576
9577   /* VEX_LEN_0F16_P_0_M_1 */
9578   {
9579     { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) },
9580   },
9581
9582   /* VEX_LEN_0F16_P_2 */
9583   {
9584     { VEX_W_TABLE (VEX_W_0F16_P_2) },
9585   },
9586
9587   /* VEX_LEN_0F17_M_0 */
9588   {
9589     { VEX_W_TABLE (VEX_W_0F17_M_0) },
9590   },
9591
9592   /* VEX_LEN_0F2A_P_1 */
9593   {
9594     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9595     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9596   },
9597
9598   /* VEX_LEN_0F2A_P_3 */
9599   {
9600     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9601     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9602   },
9603
9604   /* VEX_LEN_0F2C_P_1 */
9605   {
9606     { "vcvttss2si",     { Gv, EXdScalar }, 0 },
9607     { "vcvttss2si",     { Gv, EXdScalar }, 0 },
9608   },
9609
9610   /* VEX_LEN_0F2C_P_3 */
9611   {
9612     { "vcvttsd2si",     { Gv, EXqScalar }, 0 },
9613     { "vcvttsd2si",     { Gv, EXqScalar }, 0 },
9614   },
9615
9616   /* VEX_LEN_0F2D_P_1 */
9617   {
9618     { "vcvtss2si",      { Gv, EXdScalar }, 0 },
9619     { "vcvtss2si",      { Gv, EXdScalar }, 0 },
9620   },
9621
9622   /* VEX_LEN_0F2D_P_3 */
9623   {
9624     { "vcvtsd2si",      { Gv, EXqScalar }, 0 },
9625     { "vcvtsd2si",      { Gv, EXqScalar }, 0 },
9626   },
9627
9628   /* VEX_LEN_0F2E_P_0 */
9629   {
9630     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9631     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9632   },
9633
9634   /* VEX_LEN_0F2E_P_2 */
9635   {
9636     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9637     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9638   },
9639
9640   /* VEX_LEN_0F2F_P_0 */
9641   {
9642     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9643     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9644   },
9645
9646   /* VEX_LEN_0F2F_P_2 */
9647   {
9648     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9649     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9650   },
9651
9652   /* VEX_LEN_0F41_P_0 */
9653   {
9654     { Bad_Opcode },
9655     { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9656   },
9657   /* VEX_LEN_0F41_P_2 */
9658   {
9659     { Bad_Opcode },
9660     { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9661   },
9662   /* VEX_LEN_0F42_P_0 */
9663   {
9664     { Bad_Opcode },
9665     { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9666   },
9667   /* VEX_LEN_0F42_P_2 */
9668   {
9669     { Bad_Opcode },
9670     { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9671   },
9672   /* VEX_LEN_0F44_P_0 */
9673   {
9674     { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9675   },
9676   /* VEX_LEN_0F44_P_2 */
9677   {
9678     { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9679   },
9680   /* VEX_LEN_0F45_P_0 */
9681   {
9682     { Bad_Opcode },
9683     { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9684   },
9685   /* VEX_LEN_0F45_P_2 */
9686   {
9687     { Bad_Opcode },
9688     { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9689   },
9690   /* VEX_LEN_0F46_P_0 */
9691   {
9692     { Bad_Opcode },
9693     { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9694   },
9695   /* VEX_LEN_0F46_P_2 */
9696   {
9697     { Bad_Opcode },
9698     { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9699   },
9700   /* VEX_LEN_0F47_P_0 */
9701   {
9702     { Bad_Opcode },
9703     { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9704   },
9705   /* VEX_LEN_0F47_P_2 */
9706   {
9707     { Bad_Opcode },
9708     { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9709   },
9710   /* VEX_LEN_0F4A_P_0 */
9711   {
9712     { Bad_Opcode },
9713     { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9714   },
9715   /* VEX_LEN_0F4A_P_2 */
9716   {
9717     { Bad_Opcode },
9718     { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9719   },
9720   /* VEX_LEN_0F4B_P_0 */
9721   {
9722     { Bad_Opcode },
9723     { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9724   },
9725   /* VEX_LEN_0F4B_P_2 */
9726   {
9727     { Bad_Opcode },
9728     { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9729   },
9730
9731   /* VEX_LEN_0F51_P_1 */
9732   {
9733     { VEX_W_TABLE (VEX_W_0F51_P_1) },
9734     { VEX_W_TABLE (VEX_W_0F51_P_1) },
9735   },
9736
9737   /* VEX_LEN_0F51_P_3 */
9738   {
9739     { VEX_W_TABLE (VEX_W_0F51_P_3) },
9740     { VEX_W_TABLE (VEX_W_0F51_P_3) },
9741   },
9742
9743   /* VEX_LEN_0F52_P_1 */
9744   {
9745     { VEX_W_TABLE (VEX_W_0F52_P_1) },
9746     { VEX_W_TABLE (VEX_W_0F52_P_1) },
9747   },
9748
9749   /* VEX_LEN_0F53_P_1 */
9750   {
9751     { VEX_W_TABLE (VEX_W_0F53_P_1) },
9752     { VEX_W_TABLE (VEX_W_0F53_P_1) },
9753   },
9754
9755   /* VEX_LEN_0F58_P_1 */
9756   {
9757     { VEX_W_TABLE (VEX_W_0F58_P_1) },
9758     { VEX_W_TABLE (VEX_W_0F58_P_1) },
9759   },
9760
9761   /* VEX_LEN_0F58_P_3 */
9762   {
9763     { VEX_W_TABLE (VEX_W_0F58_P_3) },
9764     { VEX_W_TABLE (VEX_W_0F58_P_3) },
9765   },
9766
9767   /* VEX_LEN_0F59_P_1 */
9768   {
9769     { VEX_W_TABLE (VEX_W_0F59_P_1) },
9770     { VEX_W_TABLE (VEX_W_0F59_P_1) },
9771   },
9772
9773   /* VEX_LEN_0F59_P_3 */
9774   {
9775     { VEX_W_TABLE (VEX_W_0F59_P_3) },
9776     { VEX_W_TABLE (VEX_W_0F59_P_3) },
9777   },
9778
9779   /* VEX_LEN_0F5A_P_1 */
9780   {
9781     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9782     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9783   },
9784
9785   /* VEX_LEN_0F5A_P_3 */
9786   {
9787     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9788     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9789   },
9790
9791   /* VEX_LEN_0F5C_P_1 */
9792   {
9793     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9794     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9795   },
9796
9797   /* VEX_LEN_0F5C_P_3 */
9798   {
9799     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9800     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9801   },
9802
9803   /* VEX_LEN_0F5D_P_1 */
9804   {
9805     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9806     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9807   },
9808
9809   /* VEX_LEN_0F5D_P_3 */
9810   {
9811     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9812     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9813   },
9814
9815   /* VEX_LEN_0F5E_P_1 */
9816   {
9817     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9818     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9819   },
9820
9821   /* VEX_LEN_0F5E_P_3 */
9822   {
9823     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9824     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9825   },
9826
9827   /* VEX_LEN_0F5F_P_1 */
9828   {
9829     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9830     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9831   },
9832
9833   /* VEX_LEN_0F5F_P_3 */
9834   {
9835     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9836     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9837   },
9838
9839   /* VEX_LEN_0F6E_P_2 */
9840   {
9841     { "vmovK",          { XMScalar, Edq }, 0 },
9842     { "vmovK",          { XMScalar, Edq }, 0 },
9843   },
9844
9845   /* VEX_LEN_0F7E_P_1 */
9846   {
9847     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9848     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9849   },
9850
9851   /* VEX_LEN_0F7E_P_2 */
9852   {
9853     { "vmovK",          { Edq, XMScalar }, 0 },
9854     { "vmovK",          { Edq, XMScalar }, 0 },
9855   },
9856
9857   /* VEX_LEN_0F90_P_0 */
9858   {
9859     { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9860   },
9861
9862   /* VEX_LEN_0F90_P_2 */
9863   {
9864     { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9865   },
9866
9867   /* VEX_LEN_0F91_P_0 */
9868   {
9869     { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9870   },
9871
9872   /* VEX_LEN_0F91_P_2 */
9873   {
9874     { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
9875   },
9876
9877   /* VEX_LEN_0F92_P_0 */
9878   {
9879     { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9880   },
9881
9882   /* VEX_LEN_0F92_P_2 */
9883   {
9884     { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
9885   },
9886
9887   /* VEX_LEN_0F92_P_3 */
9888   {
9889     { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0) },
9890   },
9891
9892   /* VEX_LEN_0F93_P_0 */
9893   {
9894     { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9895   },
9896
9897   /* VEX_LEN_0F93_P_2 */
9898   {
9899     { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
9900   },
9901
9902   /* VEX_LEN_0F93_P_3 */
9903   {
9904     { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0) },
9905   },
9906
9907   /* VEX_LEN_0F98_P_0 */
9908   {
9909     { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9910   },
9911
9912   /* VEX_LEN_0F98_P_2 */
9913   {
9914     { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
9915   },
9916
9917   /* VEX_LEN_0F99_P_0 */
9918   {
9919     { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
9920   },
9921
9922   /* VEX_LEN_0F99_P_2 */
9923   {
9924     { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
9925   },
9926
9927   /* VEX_LEN_0FAE_R_2_M_0 */
9928   {
9929     { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) },
9930   },
9931
9932   /* VEX_LEN_0FAE_R_3_M_0 */
9933   {
9934     { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) },
9935   },
9936
9937   /* VEX_LEN_0FC2_P_1 */
9938   {
9939     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9940     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9941   },
9942
9943   /* VEX_LEN_0FC2_P_3 */
9944   {
9945     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9946     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9947   },
9948
9949   /* VEX_LEN_0FC4_P_2 */
9950   {
9951     { VEX_W_TABLE (VEX_W_0FC4_P_2) },
9952   },
9953
9954   /* VEX_LEN_0FC5_P_2 */
9955   {
9956     { VEX_W_TABLE (VEX_W_0FC5_P_2) },
9957   },
9958
9959   /* VEX_LEN_0FD6_P_2 */
9960   {
9961     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9962     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9963   },
9964
9965   /* VEX_LEN_0FF7_P_2 */
9966   {
9967     { VEX_W_TABLE (VEX_W_0FF7_P_2) },
9968   },
9969
9970   /* VEX_LEN_0F3816_P_2 */
9971   {
9972     { Bad_Opcode },
9973     { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9974   },
9975
9976   /* VEX_LEN_0F3819_P_2 */
9977   {
9978     { Bad_Opcode },
9979     { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9980   },
9981
9982   /* VEX_LEN_0F381A_P_2_M_0 */
9983   {
9984     { Bad_Opcode },
9985     { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9986   },
9987
9988   /* VEX_LEN_0F3836_P_2 */
9989   {
9990     { Bad_Opcode },
9991     { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9992   },
9993
9994   /* VEX_LEN_0F3841_P_2 */
9995   {
9996     { VEX_W_TABLE (VEX_W_0F3841_P_2) },
9997   },
9998
9999   /* VEX_LEN_0F385A_P_2_M_0 */
10000   {
10001     { Bad_Opcode },
10002     { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
10003   },
10004
10005   /* VEX_LEN_0F38DB_P_2 */
10006   {
10007     { VEX_W_TABLE (VEX_W_0F38DB_P_2) },
10008   },
10009
10010   /* VEX_LEN_0F38F2_P_0 */
10011   {
10012     { "andnS",          { Gdq, VexGdq, Edq }, 0 },
10013   },
10014
10015   /* VEX_LEN_0F38F3_R_1_P_0 */
10016   {
10017     { "blsrS",          { VexGdq, Edq }, 0 },
10018   },
10019
10020   /* VEX_LEN_0F38F3_R_2_P_0 */
10021   {
10022     { "blsmskS",        { VexGdq, Edq }, 0 },
10023   },
10024
10025   /* VEX_LEN_0F38F3_R_3_P_0 */
10026   {
10027     { "blsiS",          { VexGdq, Edq }, 0 },
10028   },
10029
10030   /* VEX_LEN_0F38F5_P_0 */
10031   {
10032     { "bzhiS",          { Gdq, Edq, VexGdq }, 0 },
10033   },
10034
10035   /* VEX_LEN_0F38F5_P_1 */
10036   {
10037     { "pextS",          { Gdq, VexGdq, Edq }, 0 },
10038   },
10039
10040   /* VEX_LEN_0F38F5_P_3 */
10041   {
10042     { "pdepS",          { Gdq, VexGdq, Edq }, 0 },
10043   },
10044
10045   /* VEX_LEN_0F38F6_P_3 */
10046   {
10047     { "mulxS",          { Gdq, VexGdq, Edq }, 0 },
10048   },
10049
10050   /* VEX_LEN_0F38F7_P_0 */
10051   {
10052     { "bextrS",         { Gdq, Edq, VexGdq }, 0 },
10053   },
10054
10055   /* VEX_LEN_0F38F7_P_1 */
10056   {
10057     { "sarxS",          { Gdq, Edq, VexGdq }, 0 },
10058   },
10059
10060   /* VEX_LEN_0F38F7_P_2 */
10061   {
10062     { "shlxS",          { Gdq, Edq, VexGdq }, 0 },
10063   },
10064
10065   /* VEX_LEN_0F38F7_P_3 */
10066   {
10067     { "shrxS",          { Gdq, Edq, VexGdq }, 0 },
10068   },
10069
10070   /* VEX_LEN_0F3A00_P_2 */
10071   {
10072     { Bad_Opcode },
10073     { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
10074   },
10075
10076   /* VEX_LEN_0F3A01_P_2 */
10077   {
10078     { Bad_Opcode },
10079     { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
10080   },
10081
10082   /* VEX_LEN_0F3A06_P_2 */
10083   {
10084     { Bad_Opcode },
10085     { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
10086   },
10087
10088   /* VEX_LEN_0F3A0A_P_2 */
10089   {
10090     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
10091     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
10092   },
10093
10094   /* VEX_LEN_0F3A0B_P_2 */
10095   {
10096     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
10097     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
10098   },
10099
10100   /* VEX_LEN_0F3A14_P_2 */
10101   {
10102     { VEX_W_TABLE (VEX_W_0F3A14_P_2) },
10103   },
10104
10105   /* VEX_LEN_0F3A15_P_2 */
10106   {
10107     { VEX_W_TABLE (VEX_W_0F3A15_P_2) },
10108   },
10109
10110   /* VEX_LEN_0F3A16_P_2  */
10111   {
10112     { "vpextrK",        { Edq, XM, Ib }, 0 },
10113   },
10114
10115   /* VEX_LEN_0F3A17_P_2 */
10116   {
10117     { "vextractps",     { Edqd, XM, Ib }, 0 },
10118   },
10119
10120   /* VEX_LEN_0F3A18_P_2 */
10121   {
10122     { Bad_Opcode },
10123     { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
10124   },
10125
10126   /* VEX_LEN_0F3A19_P_2 */
10127   {
10128     { Bad_Opcode },
10129     { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
10130   },
10131
10132   /* VEX_LEN_0F3A20_P_2 */
10133   {
10134     { VEX_W_TABLE (VEX_W_0F3A20_P_2) },
10135   },
10136
10137   /* VEX_LEN_0F3A21_P_2 */
10138   {
10139     { VEX_W_TABLE (VEX_W_0F3A21_P_2) },
10140   },
10141
10142   /* VEX_LEN_0F3A22_P_2 */
10143   {
10144     { "vpinsrK",        { XM, Vex128, Edq, Ib }, 0 },
10145   },
10146
10147   /* VEX_LEN_0F3A30_P_2 */
10148   {
10149     { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
10150   },
10151
10152   /* VEX_LEN_0F3A31_P_2 */
10153   {
10154     { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
10155   },
10156
10157   /* VEX_LEN_0F3A32_P_2 */
10158   {
10159     { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
10160   },
10161
10162   /* VEX_LEN_0F3A33_P_2 */
10163   {
10164     { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
10165   },
10166
10167   /* VEX_LEN_0F3A38_P_2 */
10168   {
10169     { Bad_Opcode },
10170     { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
10171   },
10172
10173   /* VEX_LEN_0F3A39_P_2 */
10174   {
10175     { Bad_Opcode },
10176     { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
10177   },
10178
10179   /* VEX_LEN_0F3A41_P_2 */
10180   {
10181     { VEX_W_TABLE (VEX_W_0F3A41_P_2) },
10182   },
10183
10184   /* VEX_LEN_0F3A46_P_2 */
10185   {
10186     { Bad_Opcode },
10187     { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
10188   },
10189
10190   /* VEX_LEN_0F3A60_P_2 */
10191   {
10192     { "vpcmpestrm",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
10193   },
10194
10195   /* VEX_LEN_0F3A61_P_2 */
10196   {
10197     { "vpcmpestri",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
10198   },
10199
10200   /* VEX_LEN_0F3A62_P_2 */
10201   {
10202     { VEX_W_TABLE (VEX_W_0F3A62_P_2) },
10203   },
10204
10205   /* VEX_LEN_0F3A63_P_2 */
10206   {
10207     { VEX_W_TABLE (VEX_W_0F3A63_P_2) },
10208   },
10209
10210   /* VEX_LEN_0F3A6A_P_2 */
10211   {
10212     { "vfmaddss",       { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
10213   },
10214
10215   /* VEX_LEN_0F3A6B_P_2 */
10216   {
10217     { "vfmaddsd",       { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
10218   },
10219
10220   /* VEX_LEN_0F3A6E_P_2 */
10221   {
10222     { "vfmsubss",       { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
10223   },
10224
10225   /* VEX_LEN_0F3A6F_P_2 */
10226   {
10227     { "vfmsubsd",       { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
10228   },
10229
10230   /* VEX_LEN_0F3A7A_P_2 */
10231   {
10232     { "vfnmaddss",      { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
10233   },
10234
10235   /* VEX_LEN_0F3A7B_P_2 */
10236   {
10237     { "vfnmaddsd",      { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
10238   },
10239
10240   /* VEX_LEN_0F3A7E_P_2 */
10241   {
10242     { "vfnmsubss",      { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
10243   },
10244
10245   /* VEX_LEN_0F3A7F_P_2 */
10246   {
10247     { "vfnmsubsd",      { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
10248   },
10249
10250   /* VEX_LEN_0F3ADF_P_2 */
10251   {
10252     { VEX_W_TABLE (VEX_W_0F3ADF_P_2) },
10253   },
10254
10255   /* VEX_LEN_0F3AF0_P_3 */
10256   {
10257     { "rorxS",          { Gdq, Edq, Ib }, 0 },
10258   },
10259
10260   /* VEX_LEN_0FXOP_08_CC */
10261   {
10262      { "vpcomb",        { XM, Vex128, EXx, VPCOM }, 0 },
10263   },
10264
10265   /* VEX_LEN_0FXOP_08_CD */
10266   {
10267      { "vpcomw",        { XM, Vex128, EXx, VPCOM }, 0 },
10268   },
10269
10270   /* VEX_LEN_0FXOP_08_CE */
10271   {
10272      { "vpcomd",        { XM, Vex128, EXx, VPCOM }, 0 },
10273   },
10274
10275   /* VEX_LEN_0FXOP_08_CF */
10276   {
10277      { "vpcomq",        { XM, Vex128, EXx, VPCOM }, 0 },
10278   },
10279
10280   /* VEX_LEN_0FXOP_08_EC */
10281   {
10282      { "vpcomub",       { XM, Vex128, EXx, VPCOM }, 0 },
10283   },
10284
10285   /* VEX_LEN_0FXOP_08_ED */
10286   {
10287      { "vpcomuw",       { XM, Vex128, EXx, VPCOM }, 0 },
10288   },
10289
10290   /* VEX_LEN_0FXOP_08_EE */
10291   {
10292      { "vpcomud",       { XM, Vex128, EXx, VPCOM }, 0 },
10293   },
10294
10295   /* VEX_LEN_0FXOP_08_EF */
10296   {
10297      { "vpcomuq",       { XM, Vex128, EXx, VPCOM }, 0 },
10298   },
10299
10300   /* VEX_LEN_0FXOP_09_80 */
10301   {
10302     { "vfrczps",        { XM, EXxmm }, 0 },
10303     { "vfrczps",        { XM, EXymmq }, 0 },
10304   },
10305
10306   /* VEX_LEN_0FXOP_09_81 */
10307   {
10308     { "vfrczpd",        { XM, EXxmm }, 0 },
10309     { "vfrczpd",        { XM, EXymmq }, 0 },
10310   },
10311 };
10312
10313 static const struct dis386 vex_w_table[][2] = {
10314   {
10315     /* VEX_W_0F10_P_0 */
10316     { "vmovups",        { XM, EXx }, 0 },
10317   },
10318   {
10319     /* VEX_W_0F10_P_1 */
10320     { "vmovss",         { XMVexScalar, VexScalar, EXdScalar }, 0 },
10321   },
10322   {
10323     /* VEX_W_0F10_P_2 */
10324     { "vmovupd",        { XM, EXx }, 0 },
10325   },
10326   {
10327     /* VEX_W_0F10_P_3 */
10328     { "vmovsd",         { XMVexScalar, VexScalar, EXqScalar }, 0 },
10329   },
10330   {
10331     /* VEX_W_0F11_P_0 */
10332     { "vmovups",        { EXxS, XM }, 0 },
10333   },
10334   {
10335     /* VEX_W_0F11_P_1 */
10336     { "vmovss",         { EXdVexScalarS, VexScalar, XMScalar }, 0 },
10337   },
10338   {
10339     /* VEX_W_0F11_P_2 */
10340     { "vmovupd",        { EXxS, XM }, 0 },
10341   },
10342   {
10343     /* VEX_W_0F11_P_3 */
10344     { "vmovsd",         { EXqVexScalarS, VexScalar, XMScalar }, 0 },
10345   },
10346   {
10347     /* VEX_W_0F12_P_0_M_0 */
10348     { "vmovlps",        { XM, Vex128, EXq }, 0 },
10349   },
10350   {
10351     /* VEX_W_0F12_P_0_M_1 */
10352     { "vmovhlps",       { XM, Vex128, EXq }, 0 },
10353   },
10354   {
10355     /* VEX_W_0F12_P_1 */
10356     { "vmovsldup",      { XM, EXx }, 0 },
10357   },
10358   {
10359     /* VEX_W_0F12_P_2 */
10360     { "vmovlpd",        { XM, Vex128, EXq }, 0 },
10361   },
10362   {
10363     /* VEX_W_0F12_P_3 */
10364     { "vmovddup",       { XM, EXymmq }, 0 },
10365   },
10366   {
10367     /* VEX_W_0F13_M_0 */
10368     { "vmovlpX",        { EXq, XM }, 0 },
10369   },
10370   {
10371     /* VEX_W_0F14 */
10372     { "vunpcklpX",      { XM, Vex, EXx }, 0 },
10373   },
10374   {
10375     /* VEX_W_0F15 */
10376     { "vunpckhpX",      { XM, Vex, EXx }, 0 },
10377   },
10378   {
10379     /* VEX_W_0F16_P_0_M_0 */
10380     { "vmovhps",        { XM, Vex128, EXq }, 0 },
10381   },
10382   {
10383     /* VEX_W_0F16_P_0_M_1 */
10384     { "vmovlhps",       { XM, Vex128, EXq }, 0 },
10385   },
10386   {
10387     /* VEX_W_0F16_P_1 */
10388     { "vmovshdup",      { XM, EXx }, 0 },
10389   },
10390   {
10391     /* VEX_W_0F16_P_2 */
10392     { "vmovhpd",        { XM, Vex128, EXq }, 0 },
10393   },
10394   {
10395     /* VEX_W_0F17_M_0 */
10396     { "vmovhpX",        { EXq, XM }, 0 },
10397   },
10398   {
10399     /* VEX_W_0F28 */
10400     { "vmovapX",        { XM, EXx }, 0 },
10401   },
10402   {
10403     /* VEX_W_0F29 */
10404     { "vmovapX",        { EXxS, XM }, 0 },
10405   },
10406   {
10407     /* VEX_W_0F2B_M_0 */
10408     { "vmovntpX",       { Mx, XM }, 0 },
10409   },
10410   {
10411     /* VEX_W_0F2E_P_0 */
10412     { "vucomiss",       { XMScalar, EXdScalar }, 0 },
10413   },
10414   {
10415     /* VEX_W_0F2E_P_2 */
10416     { "vucomisd",       { XMScalar, EXqScalar }, 0 },
10417   },
10418   {
10419     /* VEX_W_0F2F_P_0 */
10420     { "vcomiss",        { XMScalar, EXdScalar }, 0 },
10421   },
10422   {
10423     /* VEX_W_0F2F_P_2 */
10424     { "vcomisd",        { XMScalar, EXqScalar }, 0 },
10425   },
10426   {
10427     /* VEX_W_0F41_P_0_LEN_1 */
10428     { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
10429     { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) },
10430   },
10431   {
10432     /* VEX_W_0F41_P_2_LEN_1 */
10433     { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) },
10434     { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) }
10435   },
10436   {
10437     /* VEX_W_0F42_P_0_LEN_1 */
10438     { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) },
10439     { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) },
10440   },
10441   {
10442     /* VEX_W_0F42_P_2_LEN_1 */
10443     { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) },
10444     { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) },
10445   },
10446   {
10447     /* VEX_W_0F44_P_0_LEN_0 */
10448     { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) },
10449     { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) },
10450   },
10451   {
10452     /* VEX_W_0F44_P_2_LEN_0 */
10453     { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) },
10454     { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) },
10455   },
10456   {
10457     /* VEX_W_0F45_P_0_LEN_1 */
10458     { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) },
10459     { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) },
10460   },
10461   {
10462     /* VEX_W_0F45_P_2_LEN_1 */
10463     { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) },
10464     { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) },
10465   },
10466   {
10467     /* VEX_W_0F46_P_0_LEN_1 */
10468     { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) },
10469     { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) },
10470   },
10471   {
10472     /* VEX_W_0F46_P_2_LEN_1 */
10473     { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) },
10474     { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) },
10475   },
10476   {
10477     /* VEX_W_0F47_P_0_LEN_1 */
10478     { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) },
10479     { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) },
10480   },
10481   {
10482     /* VEX_W_0F47_P_2_LEN_1 */
10483     { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) },
10484     { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) },
10485   },
10486   {
10487     /* VEX_W_0F4A_P_0_LEN_1 */
10488     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) },
10489     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) },
10490   },
10491   {
10492     /* VEX_W_0F4A_P_2_LEN_1 */
10493     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) },
10494     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) },
10495   },
10496   {
10497     /* VEX_W_0F4B_P_0_LEN_1 */
10498     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) },
10499     { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) },
10500   },
10501   {
10502     /* VEX_W_0F4B_P_2_LEN_1 */
10503     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
10504   },
10505   {
10506     /* VEX_W_0F50_M_0 */
10507     { "vmovmskpX",      { Gdq, XS }, 0 },
10508   },
10509   {
10510     /* VEX_W_0F51_P_0 */
10511     { "vsqrtps",        { XM, EXx }, 0 },
10512   },
10513   {
10514     /* VEX_W_0F51_P_1 */
10515     { "vsqrtss",        { XMScalar, VexScalar, EXdScalar }, 0 },
10516   },
10517   {
10518     /* VEX_W_0F51_P_2  */
10519     { "vsqrtpd",        { XM, EXx }, 0 },
10520   },
10521   {
10522     /* VEX_W_0F51_P_3 */
10523     { "vsqrtsd",        { XMScalar, VexScalar, EXqScalar }, 0 },
10524   },
10525   {
10526     /* VEX_W_0F52_P_0 */
10527     { "vrsqrtps",       { XM, EXx }, 0 },
10528   },
10529   {
10530     /* VEX_W_0F52_P_1 */
10531     { "vrsqrtss",       { XMScalar, VexScalar, EXdScalar }, 0 },
10532   },
10533   {
10534     /* VEX_W_0F53_P_0  */
10535     { "vrcpps",         { XM, EXx }, 0 },
10536   },
10537   {
10538     /* VEX_W_0F53_P_1  */
10539     { "vrcpss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10540   },
10541   {
10542     /* VEX_W_0F58_P_0  */
10543     { "vaddps",         { XM, Vex, EXx }, 0 },
10544   },
10545   {
10546     /* VEX_W_0F58_P_1  */
10547     { "vaddss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10548   },
10549   {
10550     /* VEX_W_0F58_P_2  */
10551     { "vaddpd",         { XM, Vex, EXx }, 0 },
10552   },
10553   {
10554     /* VEX_W_0F58_P_3  */
10555     { "vaddsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10556   },
10557   {
10558     /* VEX_W_0F59_P_0  */
10559     { "vmulps",         { XM, Vex, EXx }, 0 },
10560   },
10561   {
10562     /* VEX_W_0F59_P_1  */
10563     { "vmulss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10564   },
10565   {
10566     /* VEX_W_0F59_P_2  */
10567     { "vmulpd",         { XM, Vex, EXx }, 0 },
10568   },
10569   {
10570     /* VEX_W_0F59_P_3  */
10571     { "vmulsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10572   },
10573   {
10574     /* VEX_W_0F5A_P_0  */
10575     { "vcvtps2pd",      { XM, EXxmmq }, 0 },
10576   },
10577   {
10578     /* VEX_W_0F5A_P_1  */
10579     { "vcvtss2sd",      { XMScalar, VexScalar, EXdScalar }, 0 },
10580   },
10581   {
10582     /* VEX_W_0F5A_P_3  */
10583     { "vcvtsd2ss",      { XMScalar, VexScalar, EXqScalar }, 0 },
10584   },
10585   {
10586     /* VEX_W_0F5B_P_0  */
10587     { "vcvtdq2ps",      { XM, EXx }, 0 },
10588   },
10589   {
10590     /* VEX_W_0F5B_P_1  */
10591     { "vcvttps2dq",     { XM, EXx }, 0 },
10592   },
10593   {
10594     /* VEX_W_0F5B_P_2  */
10595     { "vcvtps2dq",      { XM, EXx }, 0 },
10596   },
10597   {
10598     /* VEX_W_0F5C_P_0  */
10599     { "vsubps",         { XM, Vex, EXx }, 0 },
10600   },
10601   {
10602     /* VEX_W_0F5C_P_1  */
10603     { "vsubss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10604   },
10605   {
10606     /* VEX_W_0F5C_P_2  */
10607     { "vsubpd",         { XM, Vex, EXx }, 0 },
10608   },
10609   {
10610     /* VEX_W_0F5C_P_3  */
10611     { "vsubsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10612   },
10613   {
10614     /* VEX_W_0F5D_P_0  */
10615     { "vminps",         { XM, Vex, EXx }, 0 },
10616   },
10617   {
10618     /* VEX_W_0F5D_P_1  */
10619     { "vminss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10620   },
10621   {
10622     /* VEX_W_0F5D_P_2  */
10623     { "vminpd",         { XM, Vex, EXx }, 0 },
10624   },
10625   {
10626     /* VEX_W_0F5D_P_3  */
10627     { "vminsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10628   },
10629   {
10630     /* VEX_W_0F5E_P_0  */
10631     { "vdivps",         { XM, Vex, EXx }, 0 },
10632   },
10633   {
10634     /* VEX_W_0F5E_P_1  */
10635     { "vdivss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10636   },
10637   {
10638     /* VEX_W_0F5E_P_2  */
10639     { "vdivpd",         { XM, Vex, EXx }, 0 },
10640   },
10641   {
10642     /* VEX_W_0F5E_P_3  */
10643     { "vdivsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10644   },
10645   {
10646     /* VEX_W_0F5F_P_0  */
10647     { "vmaxps",         { XM, Vex, EXx }, 0 },
10648   },
10649   {
10650     /* VEX_W_0F5F_P_1  */
10651     { "vmaxss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10652   },
10653   {
10654     /* VEX_W_0F5F_P_2  */
10655     { "vmaxpd",         { XM, Vex, EXx }, 0 },
10656   },
10657   {
10658     /* VEX_W_0F5F_P_3  */
10659     { "vmaxsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10660   },
10661   {
10662     /* VEX_W_0F60_P_2  */
10663     { "vpunpcklbw",     { XM, Vex, EXx }, 0 },
10664   },
10665   {
10666     /* VEX_W_0F61_P_2  */
10667     { "vpunpcklwd",     { XM, Vex, EXx }, 0 },
10668   },
10669   {
10670     /* VEX_W_0F62_P_2  */
10671     { "vpunpckldq",     { XM, Vex, EXx }, 0 },
10672   },
10673   {
10674     /* VEX_W_0F63_P_2  */
10675     { "vpacksswb",      { XM, Vex, EXx }, 0 },
10676   },
10677   {
10678     /* VEX_W_0F64_P_2  */
10679     { "vpcmpgtb",       { XM, Vex, EXx }, 0 },
10680   },
10681   {
10682     /* VEX_W_0F65_P_2  */
10683     { "vpcmpgtw",       { XM, Vex, EXx }, 0 },
10684   },
10685   {
10686     /* VEX_W_0F66_P_2  */
10687     { "vpcmpgtd",       { XM, Vex, EXx }, 0 },
10688   },
10689   {
10690     /* VEX_W_0F67_P_2  */
10691     { "vpackuswb",      { XM, Vex, EXx }, 0 },
10692   },
10693   {
10694     /* VEX_W_0F68_P_2  */
10695     { "vpunpckhbw",     { XM, Vex, EXx }, 0 },
10696   },
10697   {
10698     /* VEX_W_0F69_P_2  */
10699     { "vpunpckhwd",     { XM, Vex, EXx }, 0 },
10700   },
10701   {
10702     /* VEX_W_0F6A_P_2  */
10703     { "vpunpckhdq",     { XM, Vex, EXx }, 0 },
10704   },
10705   {
10706     /* VEX_W_0F6B_P_2  */
10707     { "vpackssdw",      { XM, Vex, EXx }, 0 },
10708   },
10709   {
10710     /* VEX_W_0F6C_P_2  */
10711     { "vpunpcklqdq",    { XM, Vex, EXx }, 0 },
10712   },
10713   {
10714     /* VEX_W_0F6D_P_2  */
10715     { "vpunpckhqdq",    { XM, Vex, EXx }, 0 },
10716   },
10717   {
10718     /* VEX_W_0F6F_P_1  */
10719     { "vmovdqu",        { XM, EXx }, 0 },
10720   },
10721   {
10722     /* VEX_W_0F6F_P_2  */
10723     { "vmovdqa",        { XM, EXx }, 0 },
10724   },
10725   {
10726     /* VEX_W_0F70_P_1 */
10727     { "vpshufhw",       { XM, EXx, Ib }, 0 },
10728   },
10729   {
10730     /* VEX_W_0F70_P_2 */
10731     { "vpshufd",        { XM, EXx, Ib }, 0 },
10732   },
10733   {
10734     /* VEX_W_0F70_P_3 */
10735     { "vpshuflw",       { XM, EXx, Ib }, 0 },
10736   },
10737   {
10738     /* VEX_W_0F71_R_2_P_2  */
10739     { "vpsrlw",         { Vex, XS, Ib }, 0 },
10740   },
10741   {
10742     /* VEX_W_0F71_R_4_P_2  */
10743     { "vpsraw",         { Vex, XS, Ib }, 0 },
10744   },
10745   {
10746     /* VEX_W_0F71_R_6_P_2  */
10747     { "vpsllw",         { Vex, XS, Ib }, 0 },
10748   },
10749   {
10750     /* VEX_W_0F72_R_2_P_2  */
10751     { "vpsrld",         { Vex, XS, Ib }, 0 },
10752   },
10753   {
10754     /* VEX_W_0F72_R_4_P_2  */
10755     { "vpsrad",         { Vex, XS, Ib }, 0 },
10756   },
10757   {
10758     /* VEX_W_0F72_R_6_P_2  */
10759     { "vpslld",         { Vex, XS, Ib }, 0 },
10760   },
10761   {
10762     /* VEX_W_0F73_R_2_P_2  */
10763     { "vpsrlq",         { Vex, XS, Ib }, 0 },
10764   },
10765   {
10766     /* VEX_W_0F73_R_3_P_2  */
10767     { "vpsrldq",        { Vex, XS, Ib }, 0 },
10768   },
10769   {
10770     /* VEX_W_0F73_R_6_P_2  */
10771     { "vpsllq",         { Vex, XS, Ib }, 0 },
10772   },
10773   {
10774     /* VEX_W_0F73_R_7_P_2  */
10775     { "vpslldq",        { Vex, XS, Ib }, 0 },
10776   },
10777   {
10778     /* VEX_W_0F74_P_2 */
10779     { "vpcmpeqb",       { XM, Vex, EXx }, 0 },
10780   },
10781   {
10782     /* VEX_W_0F75_P_2 */
10783     { "vpcmpeqw",       { XM, Vex, EXx }, 0 },
10784   },
10785   {
10786     /* VEX_W_0F76_P_2 */
10787     { "vpcmpeqd",       { XM, Vex, EXx }, 0 },
10788   },
10789   {
10790     /* VEX_W_0F77_P_0 */
10791     { "",               { VZERO }, 0 },
10792   },
10793   {
10794     /* VEX_W_0F7C_P_2 */
10795     { "vhaddpd",        { XM, Vex, EXx }, 0 },
10796   },
10797   {
10798     /* VEX_W_0F7C_P_3 */
10799     { "vhaddps",        { XM, Vex, EXx }, 0 },
10800   },
10801   {
10802     /* VEX_W_0F7D_P_2 */
10803     { "vhsubpd",        { XM, Vex, EXx }, 0 },
10804   },
10805   {
10806     /* VEX_W_0F7D_P_3 */
10807     { "vhsubps",        { XM, Vex, EXx }, 0 },
10808   },
10809   {
10810     /* VEX_W_0F7E_P_1 */
10811     { "vmovq",          { XMScalar, EXqScalar }, 0 },
10812   },
10813   {
10814     /* VEX_W_0F7F_P_1 */
10815     { "vmovdqu",        { EXxS, XM }, 0 },
10816   },
10817   {
10818     /* VEX_W_0F7F_P_2 */
10819     { "vmovdqa",        { EXxS, XM }, 0 },
10820   },
10821   {
10822     /* VEX_W_0F90_P_0_LEN_0 */
10823     { "kmovw",          { MaskG, MaskE }, 0 },
10824     { "kmovq",          { MaskG, MaskE }, 0 },
10825   },
10826   {
10827     /* VEX_W_0F90_P_2_LEN_0 */
10828     { "kmovb",          { MaskG, MaskBDE }, 0 },
10829     { "kmovd",          { MaskG, MaskBDE }, 0 },
10830   },
10831   {
10832     /* VEX_W_0F91_P_0_LEN_0 */
10833     { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
10834     { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
10835   },
10836   {
10837     /* VEX_W_0F91_P_2_LEN_0 */
10838     { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
10839     { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
10840   },
10841   {
10842     /* VEX_W_0F92_P_0_LEN_0 */
10843     { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
10844   },
10845   {
10846     /* VEX_W_0F92_P_2_LEN_0 */
10847     { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
10848   },
10849   {
10850     /* VEX_W_0F92_P_3_LEN_0 */
10851     { MOD_TABLE (MOD_VEX_W_0_0F92_P_3_LEN_0) },
10852     { MOD_TABLE (MOD_VEX_W_1_0F92_P_3_LEN_0) },
10853   },
10854   {
10855     /* VEX_W_0F93_P_0_LEN_0 */
10856     { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
10857   },
10858   {
10859     /* VEX_W_0F93_P_2_LEN_0 */
10860     { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
10861   },
10862   {
10863     /* VEX_W_0F93_P_3_LEN_0 */
10864     { MOD_TABLE (MOD_VEX_W_0_0F93_P_3_LEN_0) },
10865     { MOD_TABLE (MOD_VEX_W_1_0F93_P_3_LEN_0) },
10866   },
10867   {
10868     /* VEX_W_0F98_P_0_LEN_0 */
10869     { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
10870     { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
10871   },
10872   {
10873     /* VEX_W_0F98_P_2_LEN_0 */
10874     { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
10875     { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
10876   },
10877   {
10878     /* VEX_W_0F99_P_0_LEN_0 */
10879     { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
10880     { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
10881   },
10882   {
10883     /* VEX_W_0F99_P_2_LEN_0 */
10884     { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
10885     { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
10886   },
10887   {
10888     /* VEX_W_0FAE_R_2_M_0 */
10889     { "vldmxcsr",       { Md }, 0 },
10890   },
10891   {
10892     /* VEX_W_0FAE_R_3_M_0 */
10893     { "vstmxcsr",       { Md }, 0 },
10894   },
10895   {
10896     /* VEX_W_0FC2_P_0 */
10897     { "vcmpps",         { XM, Vex, EXx, VCMP }, 0 },
10898   },
10899   {
10900     /* VEX_W_0FC2_P_1 */
10901     { "vcmpss",         { XMScalar, VexScalar, EXdScalar, VCMP }, 0 },
10902   },
10903   {
10904     /* VEX_W_0FC2_P_2 */
10905     { "vcmppd",         { XM, Vex, EXx, VCMP }, 0 },
10906   },
10907   {
10908     /* VEX_W_0FC2_P_3 */
10909     { "vcmpsd",         { XMScalar, VexScalar, EXqScalar, VCMP }, 0 },
10910   },
10911   {
10912     /* VEX_W_0FC4_P_2 */
10913     { "vpinsrw",        { XM, Vex128, Edqw, Ib }, 0 },
10914   },
10915   {
10916     /* VEX_W_0FC5_P_2 */
10917     { "vpextrw",        { Gdq, XS, Ib }, 0 },
10918   },
10919   {
10920     /* VEX_W_0FD0_P_2 */
10921     { "vaddsubpd",      { XM, Vex, EXx }, 0 },
10922   },
10923   {
10924     /* VEX_W_0FD0_P_3 */
10925     { "vaddsubps",      { XM, Vex, EXx }, 0 },
10926   },
10927   {
10928     /* VEX_W_0FD1_P_2 */
10929     { "vpsrlw",         { XM, Vex, EXxmm }, 0 },
10930   },
10931   {
10932     /* VEX_W_0FD2_P_2 */
10933     { "vpsrld",         { XM, Vex, EXxmm }, 0 },
10934   },
10935   {
10936     /* VEX_W_0FD3_P_2 */
10937     { "vpsrlq",         { XM, Vex, EXxmm }, 0 },
10938   },
10939   {
10940     /* VEX_W_0FD4_P_2 */
10941     { "vpaddq",         { XM, Vex, EXx }, 0 },
10942   },
10943   {
10944     /* VEX_W_0FD5_P_2 */
10945     { "vpmullw",        { XM, Vex, EXx }, 0 },
10946   },
10947   {
10948     /* VEX_W_0FD6_P_2 */
10949     { "vmovq",          { EXqScalarS, XMScalar }, 0 },
10950   },
10951   {
10952     /* VEX_W_0FD7_P_2_M_1 */
10953     { "vpmovmskb",      { Gdq, XS }, 0 },
10954   },
10955   {
10956     /* VEX_W_0FD8_P_2 */
10957     { "vpsubusb",       { XM, Vex, EXx }, 0 },
10958   },
10959   {
10960     /* VEX_W_0FD9_P_2 */
10961     { "vpsubusw",       { XM, Vex, EXx }, 0 },
10962   },
10963   {
10964     /* VEX_W_0FDA_P_2 */
10965     { "vpminub",        { XM, Vex, EXx }, 0 },
10966   },
10967   {
10968     /* VEX_W_0FDB_P_2 */
10969     { "vpand",          { XM, Vex, EXx }, 0 },
10970   },
10971   {
10972     /* VEX_W_0FDC_P_2 */
10973     { "vpaddusb",       { XM, Vex, EXx }, 0 },
10974   },
10975   {
10976     /* VEX_W_0FDD_P_2 */
10977     { "vpaddusw",       { XM, Vex, EXx }, 0 },
10978   },
10979   {
10980     /* VEX_W_0FDE_P_2 */
10981     { "vpmaxub",        { XM, Vex, EXx }, 0 },
10982   },
10983   {
10984     /* VEX_W_0FDF_P_2 */
10985     { "vpandn",         { XM, Vex, EXx }, 0 },
10986   },
10987   {
10988     /* VEX_W_0FE0_P_2  */
10989     { "vpavgb",         { XM, Vex, EXx }, 0 },
10990   },
10991   {
10992     /* VEX_W_0FE1_P_2  */
10993     { "vpsraw",         { XM, Vex, EXxmm }, 0 },
10994   },
10995   {
10996     /* VEX_W_0FE2_P_2  */
10997     { "vpsrad",         { XM, Vex, EXxmm }, 0 },
10998   },
10999   {
11000     /* VEX_W_0FE3_P_2  */
11001     { "vpavgw",         { XM, Vex, EXx }, 0 },
11002   },
11003   {
11004     /* VEX_W_0FE4_P_2  */
11005     { "vpmulhuw",       { XM, Vex, EXx }, 0 },
11006   },
11007   {
11008     /* VEX_W_0FE5_P_2  */
11009     { "vpmulhw",        { XM, Vex, EXx }, 0 },
11010   },
11011   {
11012     /* VEX_W_0FE6_P_1  */
11013     { "vcvtdq2pd",      { XM, EXxmmq }, 0 },
11014   },
11015   {
11016     /* VEX_W_0FE6_P_2  */
11017     { "vcvttpd2dq%XY",  { XMM, EXx }, 0 },
11018   },
11019   {
11020     /* VEX_W_0FE6_P_3  */
11021     { "vcvtpd2dq%XY",   { XMM, EXx }, 0 },
11022   },
11023   {
11024     /* VEX_W_0FE7_P_2_M_0 */
11025     { "vmovntdq",       { Mx, XM }, 0 },
11026   },
11027   {
11028     /* VEX_W_0FE8_P_2  */
11029     { "vpsubsb",        { XM, Vex, EXx }, 0 },
11030   },
11031   {
11032     /* VEX_W_0FE9_P_2  */
11033     { "vpsubsw",        { XM, Vex, EXx }, 0 },
11034   },
11035   {
11036     /* VEX_W_0FEA_P_2  */
11037     { "vpminsw",        { XM, Vex, EXx }, 0 },
11038   },
11039   {
11040     /* VEX_W_0FEB_P_2  */
11041     { "vpor",           { XM, Vex, EXx }, 0 },
11042   },
11043   {
11044     /* VEX_W_0FEC_P_2  */
11045     { "vpaddsb",        { XM, Vex, EXx }, 0 },
11046   },
11047   {
11048     /* VEX_W_0FED_P_2  */
11049     { "vpaddsw",        { XM, Vex, EXx }, 0 },
11050   },
11051   {
11052     /* VEX_W_0FEE_P_2  */
11053     { "vpmaxsw",        { XM, Vex, EXx }, 0 },
11054   },
11055   {
11056     /* VEX_W_0FEF_P_2  */
11057     { "vpxor",          { XM, Vex, EXx }, 0 },
11058   },
11059   {
11060     /* VEX_W_0FF0_P_3_M_0 */
11061     { "vlddqu",         { XM, M }, 0 },
11062   },
11063   {
11064     /* VEX_W_0FF1_P_2 */
11065     { "vpsllw",         { XM, Vex, EXxmm }, 0 },
11066   },
11067   {
11068     /* VEX_W_0FF2_P_2 */
11069     { "vpslld",         { XM, Vex, EXxmm }, 0 },
11070   },
11071   {
11072     /* VEX_W_0FF3_P_2 */
11073     { "vpsllq",         { XM, Vex, EXxmm }, 0 },
11074   },
11075   {
11076     /* VEX_W_0FF4_P_2 */
11077     { "vpmuludq",       { XM, Vex, EXx }, 0 },
11078   },
11079   {
11080     /* VEX_W_0FF5_P_2 */
11081     { "vpmaddwd",       { XM, Vex, EXx }, 0 },
11082   },
11083   {
11084     /* VEX_W_0FF6_P_2 */
11085     { "vpsadbw",        { XM, Vex, EXx }, 0 },
11086   },
11087   {
11088     /* VEX_W_0FF7_P_2 */
11089     { "vmaskmovdqu",    { XM, XS }, 0 },
11090   },
11091   {
11092     /* VEX_W_0FF8_P_2 */
11093     { "vpsubb",         { XM, Vex, EXx }, 0 },
11094   },
11095   {
11096     /* VEX_W_0FF9_P_2 */
11097     { "vpsubw",         { XM, Vex, EXx }, 0 },
11098   },
11099   {
11100     /* VEX_W_0FFA_P_2 */
11101     { "vpsubd",         { XM, Vex, EXx }, 0 },
11102   },
11103   {
11104     /* VEX_W_0FFB_P_2 */
11105     { "vpsubq",         { XM, Vex, EXx }, 0 },
11106   },
11107   {
11108     /* VEX_W_0FFC_P_2 */
11109     { "vpaddb",         { XM, Vex, EXx }, 0 },
11110   },
11111   {
11112     /* VEX_W_0FFD_P_2 */
11113     { "vpaddw",         { XM, Vex, EXx }, 0 },
11114   },
11115   {
11116     /* VEX_W_0FFE_P_2 */
11117     { "vpaddd",         { XM, Vex, EXx }, 0 },
11118   },
11119   {
11120     /* VEX_W_0F3800_P_2  */
11121     { "vpshufb",        { XM, Vex, EXx }, 0 },
11122   },
11123   {
11124     /* VEX_W_0F3801_P_2  */
11125     { "vphaddw",        { XM, Vex, EXx }, 0 },
11126   },
11127   {
11128     /* VEX_W_0F3802_P_2  */
11129     { "vphaddd",        { XM, Vex, EXx }, 0 },
11130   },
11131   {
11132     /* VEX_W_0F3803_P_2  */
11133     { "vphaddsw",       { XM, Vex, EXx }, 0 },
11134   },
11135   {
11136     /* VEX_W_0F3804_P_2  */
11137     { "vpmaddubsw",     { XM, Vex, EXx }, 0 },
11138   },
11139   {
11140     /* VEX_W_0F3805_P_2  */
11141     { "vphsubw",        { XM, Vex, EXx }, 0 },
11142   },
11143   {
11144     /* VEX_W_0F3806_P_2  */
11145     { "vphsubd",        { XM, Vex, EXx }, 0 },
11146   },
11147   {
11148     /* VEX_W_0F3807_P_2  */
11149     { "vphsubsw",       { XM, Vex, EXx }, 0 },
11150   },
11151   {
11152     /* VEX_W_0F3808_P_2  */
11153     { "vpsignb",        { XM, Vex, EXx }, 0 },
11154   },
11155   {
11156     /* VEX_W_0F3809_P_2  */
11157     { "vpsignw",        { XM, Vex, EXx }, 0 },
11158   },
11159   {
11160     /* VEX_W_0F380A_P_2  */
11161     { "vpsignd",        { XM, Vex, EXx }, 0 },
11162   },
11163   {
11164     /* VEX_W_0F380B_P_2  */
11165     { "vpmulhrsw",      { XM, Vex, EXx }, 0 },
11166   },
11167   {
11168     /* VEX_W_0F380C_P_2  */
11169     { "vpermilps",      { XM, Vex, EXx }, 0 },
11170   },
11171   {
11172     /* VEX_W_0F380D_P_2  */
11173     { "vpermilpd",      { XM, Vex, EXx }, 0 },
11174   },
11175   {
11176     /* VEX_W_0F380E_P_2  */
11177     { "vtestps",        { XM, EXx }, 0 },
11178   },
11179   {
11180     /* VEX_W_0F380F_P_2  */
11181     { "vtestpd",        { XM, EXx }, 0 },
11182   },
11183   {
11184     /* VEX_W_0F3816_P_2  */
11185     { "vpermps",        { XM, Vex, EXx }, 0 },
11186   },
11187   {
11188     /* VEX_W_0F3817_P_2 */
11189     { "vptest",         { XM, EXx }, 0 },
11190   },
11191   {
11192     /* VEX_W_0F3818_P_2 */
11193     { "vbroadcastss",   { XM, EXxmm_md }, 0 },
11194   },
11195   {
11196     /* VEX_W_0F3819_P_2 */
11197     { "vbroadcastsd",   { XM, EXxmm_mq }, 0 },
11198   },
11199   {
11200     /* VEX_W_0F381A_P_2_M_0 */
11201     { "vbroadcastf128", { XM, Mxmm }, 0 },
11202   },
11203   {
11204     /* VEX_W_0F381C_P_2 */
11205     { "vpabsb",         { XM, EXx }, 0 },
11206   },
11207   {
11208     /* VEX_W_0F381D_P_2 */
11209     { "vpabsw",         { XM, EXx }, 0 },
11210   },
11211   {
11212     /* VEX_W_0F381E_P_2 */
11213     { "vpabsd",         { XM, EXx }, 0 },
11214   },
11215   {
11216     /* VEX_W_0F3820_P_2 */
11217     { "vpmovsxbw",      { XM, EXxmmq }, 0 },
11218   },
11219   {
11220     /* VEX_W_0F3821_P_2 */
11221     { "vpmovsxbd",      { XM, EXxmmqd }, 0 },
11222   },
11223   {
11224     /* VEX_W_0F3822_P_2 */
11225     { "vpmovsxbq",      { XM, EXxmmdw }, 0 },
11226   },
11227   {
11228     /* VEX_W_0F3823_P_2 */
11229     { "vpmovsxwd",      { XM, EXxmmq }, 0 },
11230   },
11231   {
11232     /* VEX_W_0F3824_P_2 */
11233     { "vpmovsxwq",      { XM, EXxmmqd }, 0 },
11234   },
11235   {
11236     /* VEX_W_0F3825_P_2 */
11237     { "vpmovsxdq",      { XM, EXxmmq }, 0 },
11238   },
11239   {
11240     /* VEX_W_0F3828_P_2 */
11241     { "vpmuldq",        { XM, Vex, EXx }, 0 },
11242   },
11243   {
11244     /* VEX_W_0F3829_P_2 */
11245     { "vpcmpeqq",       { XM, Vex, EXx }, 0 },
11246   },
11247   {
11248     /* VEX_W_0F382A_P_2_M_0 */
11249     { "vmovntdqa",      { XM, Mx }, 0 },
11250   },
11251   {
11252     /* VEX_W_0F382B_P_2 */
11253     { "vpackusdw",      { XM, Vex, EXx }, 0 },
11254   },
11255   {
11256     /* VEX_W_0F382C_P_2_M_0 */
11257     { "vmaskmovps",     { XM, Vex, Mx }, 0 },
11258   },
11259   {
11260     /* VEX_W_0F382D_P_2_M_0 */
11261     { "vmaskmovpd",     { XM, Vex, Mx }, 0 },
11262   },
11263   {
11264     /* VEX_W_0F382E_P_2_M_0 */
11265     { "vmaskmovps",     { Mx, Vex, XM }, 0 },
11266   },
11267   {
11268     /* VEX_W_0F382F_P_2_M_0 */
11269     { "vmaskmovpd",     { Mx, Vex, XM }, 0 },
11270   },
11271   {
11272     /* VEX_W_0F3830_P_2 */
11273     { "vpmovzxbw",      { XM, EXxmmq }, 0 },
11274   },
11275   {
11276     /* VEX_W_0F3831_P_2 */
11277     { "vpmovzxbd",      { XM, EXxmmqd }, 0 },
11278   },
11279   {
11280     /* VEX_W_0F3832_P_2 */
11281     { "vpmovzxbq",      { XM, EXxmmdw }, 0 },
11282   },
11283   {
11284     /* VEX_W_0F3833_P_2 */
11285     { "vpmovzxwd",      { XM, EXxmmq }, 0 },
11286   },
11287   {
11288     /* VEX_W_0F3834_P_2 */
11289     { "vpmovzxwq",      { XM, EXxmmqd }, 0 },
11290   },
11291   {
11292     /* VEX_W_0F3835_P_2 */
11293     { "vpmovzxdq",      { XM, EXxmmq }, 0 },
11294   },
11295   {
11296     /* VEX_W_0F3836_P_2  */
11297     { "vpermd",         { XM, Vex, EXx }, 0 },
11298   },
11299   {
11300     /* VEX_W_0F3837_P_2 */
11301     { "vpcmpgtq",       { XM, Vex, EXx }, 0 },
11302   },
11303   {
11304     /* VEX_W_0F3838_P_2 */
11305     { "vpminsb",        { XM, Vex, EXx }, 0 },
11306   },
11307   {
11308     /* VEX_W_0F3839_P_2 */
11309     { "vpminsd",        { XM, Vex, EXx }, 0 },
11310   },
11311   {
11312     /* VEX_W_0F383A_P_2 */
11313     { "vpminuw",        { XM, Vex, EXx }, 0 },
11314   },
11315   {
11316     /* VEX_W_0F383B_P_2 */
11317     { "vpminud",        { XM, Vex, EXx }, 0 },
11318   },
11319   {
11320     /* VEX_W_0F383C_P_2 */
11321     { "vpmaxsb",        { XM, Vex, EXx }, 0 },
11322   },
11323   {
11324     /* VEX_W_0F383D_P_2 */
11325     { "vpmaxsd",        { XM, Vex, EXx }, 0 },
11326   },
11327   {
11328     /* VEX_W_0F383E_P_2 */
11329     { "vpmaxuw",        { XM, Vex, EXx }, 0 },
11330   },
11331   {
11332     /* VEX_W_0F383F_P_2 */
11333     { "vpmaxud",        { XM, Vex, EXx }, 0 },
11334   },
11335   {
11336     /* VEX_W_0F3840_P_2 */
11337     { "vpmulld",        { XM, Vex, EXx }, 0 },
11338   },
11339   {
11340     /* VEX_W_0F3841_P_2 */
11341     { "vphminposuw",    { XM, EXx }, 0 },
11342   },
11343   {
11344     /* VEX_W_0F3846_P_2 */
11345     { "vpsravd",        { XM, Vex, EXx }, 0 },
11346   },
11347   {
11348     /* VEX_W_0F3858_P_2 */
11349     { "vpbroadcastd", { XM, EXxmm_md }, 0 },
11350   },
11351   {
11352     /* VEX_W_0F3859_P_2 */
11353     { "vpbroadcastq",   { XM, EXxmm_mq }, 0 },
11354   },
11355   {
11356     /* VEX_W_0F385A_P_2_M_0 */
11357     { "vbroadcasti128", { XM, Mxmm }, 0 },
11358   },
11359   {
11360     /* VEX_W_0F3878_P_2 */
11361     { "vpbroadcastb",   { XM, EXxmm_mb }, 0 },
11362   },
11363   {
11364     /* VEX_W_0F3879_P_2 */
11365     { "vpbroadcastw",   { XM, EXxmm_mw }, 0 },
11366   },
11367   {
11368     /* VEX_W_0F38CF_P_2 */
11369     { "vgf2p8mulb", { XM, Vex, EXx }, 0 },
11370   },
11371   {
11372     /* VEX_W_0F38DB_P_2 */
11373     { "vaesimc",        { XM, EXx }, 0 },
11374   },
11375   {
11376     /* VEX_W_0F3A00_P_2 */
11377     { Bad_Opcode },
11378     { "vpermq",         { XM, EXx, Ib }, 0 },
11379   },
11380   {
11381     /* VEX_W_0F3A01_P_2 */
11382     { Bad_Opcode },
11383     { "vpermpd",        { XM, EXx, Ib }, 0 },
11384   },
11385   {
11386     /* VEX_W_0F3A02_P_2 */
11387     { "vpblendd",       { XM, Vex, EXx, Ib }, 0 },
11388   },
11389   {
11390     /* VEX_W_0F3A04_P_2 */
11391     { "vpermilps",      { XM, EXx, Ib }, 0 },
11392   },
11393   {
11394     /* VEX_W_0F3A05_P_2 */
11395     { "vpermilpd",      { XM, EXx, Ib }, 0 },
11396   },
11397   {
11398     /* VEX_W_0F3A06_P_2 */
11399     { "vperm2f128",     { XM, Vex256, EXx, Ib }, 0 },
11400   },
11401   {
11402     /* VEX_W_0F3A08_P_2 */
11403     { "vroundps",       { XM, EXx, Ib }, 0 },
11404   },
11405   {
11406     /* VEX_W_0F3A09_P_2 */
11407     { "vroundpd",       { XM, EXx, Ib }, 0 },
11408   },
11409   {
11410     /* VEX_W_0F3A0A_P_2 */
11411     { "vroundss",       { XMScalar, VexScalar, EXdScalar, Ib }, 0 },
11412   },
11413   {
11414     /* VEX_W_0F3A0B_P_2 */
11415     { "vroundsd",       { XMScalar, VexScalar, EXqScalar, Ib }, 0 },
11416   },
11417   {
11418     /* VEX_W_0F3A0C_P_2 */
11419     { "vblendps",       { XM, Vex, EXx, Ib }, 0 },
11420   },
11421   {
11422     /* VEX_W_0F3A0D_P_2 */
11423     { "vblendpd",       { XM, Vex, EXx, Ib }, 0 },
11424   },
11425   {
11426     /* VEX_W_0F3A0E_P_2 */
11427     { "vpblendw",       { XM, Vex, EXx, Ib }, 0 },
11428   },
11429   {
11430     /* VEX_W_0F3A0F_P_2 */
11431     { "vpalignr",       { XM, Vex, EXx, Ib }, 0 },
11432   },
11433   {
11434     /* VEX_W_0F3A14_P_2 */
11435     { "vpextrb",        { Edqb, XM, Ib }, 0 },
11436   },
11437   {
11438     /* VEX_W_0F3A15_P_2 */
11439     { "vpextrw",        { Edqw, XM, Ib }, 0 },
11440   },
11441   {
11442     /* VEX_W_0F3A18_P_2 */
11443     { "vinsertf128",    { XM, Vex256, EXxmm, Ib }, 0 },
11444   },
11445   {
11446     /* VEX_W_0F3A19_P_2 */
11447     { "vextractf128",   { EXxmm, XM, Ib }, 0 },
11448   },
11449   {
11450     /* VEX_W_0F3A20_P_2 */
11451     { "vpinsrb",        { XM, Vex128, Edqb, Ib }, 0 },
11452   },
11453   {
11454     /* VEX_W_0F3A21_P_2 */
11455     { "vinsertps",      { XM, Vex128, EXd, Ib }, 0 },
11456   },
11457   {
11458     /* VEX_W_0F3A30_P_2_LEN_0 */
11459     { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) },
11460     { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) },
11461   },
11462   {
11463     /* VEX_W_0F3A31_P_2_LEN_0 */
11464     { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) },
11465     { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) },
11466   },
11467   {
11468     /* VEX_W_0F3A32_P_2_LEN_0 */
11469     { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) },
11470     { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) },
11471   },
11472   {
11473     /* VEX_W_0F3A33_P_2_LEN_0 */
11474     { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) },
11475     { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) },
11476   },
11477   {
11478     /* VEX_W_0F3A38_P_2 */
11479     { "vinserti128",    { XM, Vex256, EXxmm, Ib }, 0 },
11480   },
11481   {
11482     /* VEX_W_0F3A39_P_2 */
11483     { "vextracti128",   { EXxmm, XM, Ib }, 0 },
11484   },
11485   {
11486     /* VEX_W_0F3A40_P_2 */
11487     { "vdpps",          { XM, Vex, EXx, Ib }, 0 },
11488   },
11489   {
11490     /* VEX_W_0F3A41_P_2 */
11491     { "vdppd",          { XM, Vex128, EXx, Ib }, 0 },
11492   },
11493   {
11494     /* VEX_W_0F3A42_P_2 */
11495     { "vmpsadbw",       { XM, Vex, EXx, Ib }, 0 },
11496   },
11497   {
11498     /* VEX_W_0F3A46_P_2 */
11499     { "vperm2i128",     { XM, Vex256, EXx, Ib }, 0 },
11500   },
11501   {
11502     /* VEX_W_0F3A48_P_2 */
11503     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11504     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11505   },
11506   {
11507     /* VEX_W_0F3A49_P_2 */
11508     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11509     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11510   },
11511   {
11512     /* VEX_W_0F3A4A_P_2 */
11513     { "vblendvps",      { XM, Vex, EXx, XMVexI4 }, 0 },
11514   },
11515   {
11516     /* VEX_W_0F3A4B_P_2 */
11517     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 }, 0 },
11518   },
11519   {
11520     /* VEX_W_0F3A4C_P_2 */
11521     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 }, 0 },
11522   },
11523   {
11524     /* VEX_W_0F3A62_P_2 */
11525     { "vpcmpistrm",     { XM, EXx, Ib }, 0 },
11526   },
11527   {
11528     /* VEX_W_0F3A63_P_2 */
11529     { "vpcmpistri",     { XM, EXx, Ib }, 0 },
11530   },
11531   {
11532     /* VEX_W_0F3ACE_P_2 */
11533     { Bad_Opcode },
11534     { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, 0 },
11535   },
11536   {
11537     /* VEX_W_0F3ACF_P_2 */
11538     { Bad_Opcode },
11539     { "vgf2p8affineinvqb",  { XM, Vex, EXx, Ib }, 0 },
11540   },
11541   {
11542     /* VEX_W_0F3ADF_P_2 */
11543     { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
11544   },
11545 #define NEED_VEX_W_TABLE
11546 #include "i386-dis-evex.h"
11547 #undef NEED_VEX_W_TABLE
11548 };
11549
11550 static const struct dis386 mod_table[][2] = {
11551   {
11552     /* MOD_8D */
11553     { "leaS",           { Gv, M }, 0 },
11554   },
11555   {
11556     /* MOD_C6_REG_7 */
11557     { Bad_Opcode },
11558     { RM_TABLE (RM_C6_REG_7) },
11559   },
11560   {
11561     /* MOD_C7_REG_7 */
11562     { Bad_Opcode },
11563     { RM_TABLE (RM_C7_REG_7) },
11564   },
11565   {
11566     /* MOD_FF_REG_3 */
11567     { "Jcall^", { indirEp }, 0 },
11568   },
11569   {
11570     /* MOD_FF_REG_5 */
11571     { "Jjmp^", { indirEp }, 0 },
11572   },
11573   {
11574     /* MOD_0F01_REG_0 */
11575     { X86_64_TABLE (X86_64_0F01_REG_0) },
11576     { RM_TABLE (RM_0F01_REG_0) },
11577   },
11578   {
11579     /* MOD_0F01_REG_1 */
11580     { X86_64_TABLE (X86_64_0F01_REG_1) },
11581     { RM_TABLE (RM_0F01_REG_1) },
11582   },
11583   {
11584     /* MOD_0F01_REG_2 */
11585     { X86_64_TABLE (X86_64_0F01_REG_2) },
11586     { RM_TABLE (RM_0F01_REG_2) },
11587   },
11588   {
11589     /* MOD_0F01_REG_3 */
11590     { X86_64_TABLE (X86_64_0F01_REG_3) },
11591     { RM_TABLE (RM_0F01_REG_3) },
11592   },
11593   {
11594     /* MOD_0F01_REG_5 */
11595     { PREFIX_TABLE (PREFIX_MOD_0_0F01_REG_5) },
11596     { RM_TABLE (RM_0F01_REG_5) },
11597   },
11598   {
11599     /* MOD_0F01_REG_7 */
11600     { "invlpg",         { Mb }, 0 },
11601     { RM_TABLE (RM_0F01_REG_7) },
11602   },
11603   {
11604     /* MOD_0F12_PREFIX_0 */
11605     { "movlps",         { XM, EXq }, PREFIX_OPCODE },
11606     { "movhlps",        { XM, EXq }, PREFIX_OPCODE },
11607   },
11608   {
11609     /* MOD_0F13 */
11610     { "movlpX",         { EXq, XM }, PREFIX_OPCODE },
11611   },
11612   {
11613     /* MOD_0F16_PREFIX_0 */
11614     { "movhps",         { XM, EXq }, 0 },
11615     { "movlhps",        { XM, EXq }, 0 },
11616   },
11617   {
11618     /* MOD_0F17 */
11619     { "movhpX",         { EXq, XM }, PREFIX_OPCODE },
11620   },
11621   {
11622     /* MOD_0F18_REG_0 */
11623     { "prefetchnta",    { Mb }, 0 },
11624   },
11625   {
11626     /* MOD_0F18_REG_1 */
11627     { "prefetcht0",     { Mb }, 0 },
11628   },
11629   {
11630     /* MOD_0F18_REG_2 */
11631     { "prefetcht1",     { Mb }, 0 },
11632   },
11633   {
11634     /* MOD_0F18_REG_3 */
11635     { "prefetcht2",     { Mb }, 0 },
11636   },
11637   {
11638     /* MOD_0F18_REG_4 */
11639     { "nop/reserved",   { Mb }, 0 },
11640   },
11641   {
11642     /* MOD_0F18_REG_5 */
11643     { "nop/reserved",   { Mb }, 0 },
11644   },
11645   {
11646     /* MOD_0F18_REG_6 */
11647     { "nop/reserved",   { Mb }, 0 },
11648   },
11649   {
11650     /* MOD_0F18_REG_7 */
11651     { "nop/reserved",   { Mb }, 0 },
11652   },
11653   {
11654     /* MOD_0F1A_PREFIX_0 */
11655     { "bndldx",         { Gbnd, Mv_bnd }, 0 },
11656     { "nopQ",           { Ev }, 0 },
11657   },
11658   {
11659     /* MOD_0F1B_PREFIX_0 */
11660     { "bndstx",         { Mv_bnd, Gbnd }, 0 },
11661     { "nopQ",           { Ev }, 0 },
11662   },
11663   {
11664     /* MOD_0F1B_PREFIX_1 */
11665     { "bndmk",          { Gbnd, Mv_bnd }, 0 },
11666     { "nopQ",           { Ev }, 0 },
11667   },
11668   {
11669     /* MOD_0F1C_PREFIX_0 */
11670     { REG_TABLE (REG_0F1C_MOD_0) },
11671     { "nopQ",           { Ev }, 0 },
11672   },
11673   {
11674     /* MOD_0F1E_PREFIX_1 */
11675     { "nopQ",           { Ev }, 0 },
11676     { REG_TABLE (REG_0F1E_MOD_3) },
11677   },
11678   {
11679     /* MOD_0F24 */
11680     { Bad_Opcode },
11681     { "movL",           { Rd, Td }, 0 },
11682   },
11683   {
11684     /* MOD_0F26 */
11685     { Bad_Opcode },
11686     { "movL",           { Td, Rd }, 0 },
11687   },
11688   {
11689     /* MOD_0F2B_PREFIX_0 */
11690     {"movntps",         { Mx, XM }, PREFIX_OPCODE },
11691   },
11692   {
11693     /* MOD_0F2B_PREFIX_1 */
11694     {"movntss",         { Md, XM }, PREFIX_OPCODE },
11695   },
11696   {
11697     /* MOD_0F2B_PREFIX_2 */
11698     {"movntpd",         { Mx, XM }, PREFIX_OPCODE },
11699   },
11700   {
11701     /* MOD_0F2B_PREFIX_3 */
11702     {"movntsd",         { Mq, XM }, PREFIX_OPCODE },
11703   },
11704   {
11705     /* MOD_0F51 */
11706     { Bad_Opcode },
11707     { "movmskpX",       { Gdq, XS }, PREFIX_OPCODE },
11708   },
11709   {
11710     /* MOD_0F71_REG_2 */
11711     { Bad_Opcode },
11712     { "psrlw",          { MS, Ib }, 0 },
11713   },
11714   {
11715     /* MOD_0F71_REG_4 */
11716     { Bad_Opcode },
11717     { "psraw",          { MS, Ib }, 0 },
11718   },
11719   {
11720     /* MOD_0F71_REG_6 */
11721     { Bad_Opcode },
11722     { "psllw",          { MS, Ib }, 0 },
11723   },
11724   {
11725     /* MOD_0F72_REG_2 */
11726     { Bad_Opcode },
11727     { "psrld",          { MS, Ib }, 0 },
11728   },
11729   {
11730     /* MOD_0F72_REG_4 */
11731     { Bad_Opcode },
11732     { "psrad",          { MS, Ib }, 0 },
11733   },
11734   {
11735     /* MOD_0F72_REG_6 */
11736     { Bad_Opcode },
11737     { "pslld",          { MS, Ib }, 0 },
11738   },
11739   {
11740     /* MOD_0F73_REG_2 */
11741     { Bad_Opcode },
11742     { "psrlq",          { MS, Ib }, 0 },
11743   },
11744   {
11745     /* MOD_0F73_REG_3 */
11746     { Bad_Opcode },
11747     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
11748   },
11749   {
11750     /* MOD_0F73_REG_6 */
11751     { Bad_Opcode },
11752     { "psllq",          { MS, Ib }, 0 },
11753   },
11754   {
11755     /* MOD_0F73_REG_7 */
11756     { Bad_Opcode },
11757     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
11758   },
11759   {
11760     /* MOD_0FAE_REG_0 */
11761     { "fxsave",         { FXSAVE }, 0 },
11762     { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
11763   },
11764   {
11765     /* MOD_0FAE_REG_1 */
11766     { "fxrstor",        { FXSAVE }, 0 },
11767     { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
11768   },
11769   {
11770     /* MOD_0FAE_REG_2 */
11771     { "ldmxcsr",        { Md }, 0 },
11772     { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
11773   },
11774   {
11775     /* MOD_0FAE_REG_3 */
11776     { "stmxcsr",        { Md }, 0 },
11777     { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
11778   },
11779   {
11780     /* MOD_0FAE_REG_4 */
11781     { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_4) },
11782     { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_4) },
11783   },
11784   {
11785     /* MOD_0FAE_REG_5 */
11786     { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_5) },
11787     { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_5) },
11788   },
11789   {
11790     /* MOD_0FAE_REG_6 */
11791     { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_6) },
11792     { PREFIX_TABLE (PREFIX_MOD_1_0FAE_REG_6) },
11793   },
11794   {
11795     /* MOD_0FAE_REG_7 */
11796     { PREFIX_TABLE (PREFIX_0FAE_REG_7) },
11797     { RM_TABLE (RM_0FAE_REG_7) },
11798   },
11799   {
11800     /* MOD_0FB2 */
11801     { "lssS",           { Gv, Mp }, 0 },
11802   },
11803   {
11804     /* MOD_0FB4 */
11805     { "lfsS",           { Gv, Mp }, 0 },
11806   },
11807   {
11808     /* MOD_0FB5 */
11809     { "lgsS",           { Gv, Mp }, 0 },
11810   },
11811   {
11812     /* MOD_0FC3 */
11813     { PREFIX_TABLE (PREFIX_MOD_0_0FC3) },
11814   },
11815   {
11816     /* MOD_0FC7_REG_3 */
11817     { "xrstors",        { FXSAVE }, 0 },
11818   },
11819   {
11820     /* MOD_0FC7_REG_4 */
11821     { "xsavec",         { FXSAVE }, 0 },
11822   },
11823   {
11824     /* MOD_0FC7_REG_5 */
11825     { "xsaves",         { FXSAVE }, 0 },
11826   },
11827   {
11828     /* MOD_0FC7_REG_6 */
11829     { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6) },
11830     { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6) }
11831   },
11832   {
11833     /* MOD_0FC7_REG_7 */
11834     { "vmptrst",        { Mq }, 0 },
11835     { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7) }
11836   },
11837   {
11838     /* MOD_0FD7 */
11839     { Bad_Opcode },
11840     { "pmovmskb",       { Gdq, MS }, 0 },
11841   },
11842   {
11843     /* MOD_0FE7_PREFIX_2 */
11844     { "movntdq",        { Mx, XM }, 0 },
11845   },
11846   {
11847     /* MOD_0FF0_PREFIX_3 */
11848     { "lddqu",          { XM, M }, 0 },
11849   },
11850   {
11851     /* MOD_0F382A_PREFIX_2 */
11852     { "movntdqa",       { XM, Mx }, 0 },
11853   },
11854   {
11855     /* MOD_0F38F5_PREFIX_2 */
11856     { "wrussK",         { M, Gdq }, PREFIX_OPCODE },
11857   },
11858   {
11859     /* MOD_0F38F6_PREFIX_0 */
11860     { "wrssK",          { M, Gdq }, PREFIX_OPCODE },
11861   },
11862   {
11863     /* MOD_0F38F8_PREFIX_2 */
11864     { "movdir64b",      { Gva, M }, PREFIX_OPCODE },
11865   },
11866   {
11867     /* MOD_0F38F9_PREFIX_0 */
11868     { "movdiri",        { Em, Gv }, PREFIX_OPCODE },
11869   },
11870   {
11871     /* MOD_62_32BIT */
11872     { "bound{S|}",      { Gv, Ma }, 0 },
11873     { EVEX_TABLE (EVEX_0F) },
11874   },
11875   {
11876     /* MOD_C4_32BIT */
11877     { "lesS",           { Gv, Mp }, 0 },
11878     { VEX_C4_TABLE (VEX_0F) },
11879   },
11880   {
11881     /* MOD_C5_32BIT */
11882     { "ldsS",           { Gv, Mp }, 0 },
11883     { VEX_C5_TABLE (VEX_0F) },
11884   },
11885   {
11886     /* MOD_VEX_0F12_PREFIX_0 */
11887     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
11888     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
11889   },
11890   {
11891     /* MOD_VEX_0F13 */
11892     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
11893   },
11894   {
11895     /* MOD_VEX_0F16_PREFIX_0 */
11896     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
11897     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
11898   },
11899   {
11900     /* MOD_VEX_0F17 */
11901     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
11902   },
11903   {
11904     /* MOD_VEX_0F2B */
11905     { VEX_W_TABLE (VEX_W_0F2B_M_0) },
11906   },
11907   {
11908     /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
11909     { Bad_Opcode },
11910     { "kandw",          { MaskG, MaskVex, MaskR }, 0 },
11911   },
11912   {
11913     /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
11914     { Bad_Opcode },
11915     { "kandq",          { MaskG, MaskVex, MaskR }, 0 },
11916   },
11917   {
11918     /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
11919     { Bad_Opcode },
11920     { "kandb",          { MaskG, MaskVex, MaskR }, 0 },
11921   },
11922   {
11923     /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
11924     { Bad_Opcode },
11925     { "kandd",          { MaskG, MaskVex, MaskR }, 0 },
11926   },
11927   {
11928     /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
11929     { Bad_Opcode },
11930     { "kandnw",         { MaskG, MaskVex, MaskR }, 0 },
11931   },
11932   {
11933     /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
11934     { Bad_Opcode },
11935     { "kandnq",         { MaskG, MaskVex, MaskR }, 0 },
11936   },
11937   {
11938     /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
11939     { Bad_Opcode },
11940     { "kandnb",         { MaskG, MaskVex, MaskR }, 0 },
11941   },
11942   {
11943     /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
11944     { Bad_Opcode },
11945     { "kandnd",         { MaskG, MaskVex, MaskR }, 0 },
11946   },
11947   {
11948     /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
11949     { Bad_Opcode },
11950     { "knotw",          { MaskG, MaskR }, 0 },
11951   },
11952   {
11953     /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
11954     { Bad_Opcode },
11955     { "knotq",          { MaskG, MaskR }, 0 },
11956   },
11957   {
11958     /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
11959     { Bad_Opcode },
11960     { "knotb",          { MaskG, MaskR }, 0 },
11961   },
11962   {
11963     /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
11964     { Bad_Opcode },
11965     { "knotd",          { MaskG, MaskR }, 0 },
11966   },
11967   {
11968     /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
11969     { Bad_Opcode },
11970     { "korw",       { MaskG, MaskVex, MaskR }, 0 },
11971   },
11972   {
11973     /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
11974     { Bad_Opcode },
11975     { "korq",       { MaskG, MaskVex, MaskR }, 0 },
11976   },
11977   {
11978     /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
11979     { Bad_Opcode },
11980     { "korb",       { MaskG, MaskVex, MaskR }, 0 },
11981   },
11982   {
11983     /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
11984     { Bad_Opcode },
11985     { "kord",       { MaskG, MaskVex, MaskR }, 0 },
11986   },
11987  {
11988     /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
11989     { Bad_Opcode },
11990     { "kxnorw",     { MaskG, MaskVex, MaskR }, 0 },
11991   },
11992   {
11993     /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
11994     { Bad_Opcode },
11995     { "kxnorq",     { MaskG, MaskVex, MaskR }, 0 },
11996   },
11997   {
11998     /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
11999     { Bad_Opcode },
12000     { "kxnorb",     { MaskG, MaskVex, MaskR }, 0 },
12001   },
12002   {
12003     /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
12004     { Bad_Opcode },
12005     { "kxnord",     { MaskG, MaskVex, MaskR }, 0 },
12006   },
12007   {
12008     /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
12009     { Bad_Opcode },
12010     { "kxorw",      { MaskG, MaskVex, MaskR }, 0 },
12011   },
12012   {
12013     /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
12014     { Bad_Opcode },
12015     { "kxorq",      { MaskG, MaskVex, MaskR }, 0 },
12016   },
12017   {
12018     /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
12019     { Bad_Opcode },
12020     { "kxorb",      { MaskG, MaskVex, MaskR }, 0 },
12021   },
12022   {
12023     /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
12024     { Bad_Opcode },
12025     { "kxord",      { MaskG, MaskVex, MaskR }, 0 },
12026   },
12027   {
12028     /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
12029     { Bad_Opcode },
12030     { "kaddw",          { MaskG, MaskVex, MaskR }, 0 },
12031   },
12032   {
12033     /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
12034     { Bad_Opcode },
12035     { "kaddq",          { MaskG, MaskVex, MaskR }, 0 },
12036   },
12037   {
12038     /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
12039     { Bad_Opcode },
12040     { "kaddb",          { MaskG, MaskVex, MaskR }, 0 },
12041   },
12042   {
12043     /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
12044     { Bad_Opcode },
12045     { "kaddd",          { MaskG, MaskVex, MaskR }, 0 },
12046   },
12047   {
12048     /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
12049     { Bad_Opcode },
12050     { "kunpckwd",   { MaskG, MaskVex, MaskR }, 0 },
12051   },
12052   {
12053     /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
12054     { Bad_Opcode },
12055     { "kunpckdq",   { MaskG, MaskVex, MaskR }, 0 },
12056   },
12057   {
12058     /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
12059     { Bad_Opcode },
12060     { "kunpckbw",   { MaskG, MaskVex, MaskR }, 0 },
12061   },
12062   {
12063     /* MOD_VEX_0F50 */
12064     { Bad_Opcode },
12065     { VEX_W_TABLE (VEX_W_0F50_M_0) },
12066   },
12067   {
12068     /* MOD_VEX_0F71_REG_2 */
12069     { Bad_Opcode },
12070     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
12071   },
12072   {
12073     /* MOD_VEX_0F71_REG_4 */
12074     { Bad_Opcode },
12075     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
12076   },
12077   {
12078     /* MOD_VEX_0F71_REG_6 */
12079     { Bad_Opcode },
12080     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
12081   },
12082   {
12083     /* MOD_VEX_0F72_REG_2 */
12084     { Bad_Opcode },
12085     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
12086   },
12087   {
12088     /* MOD_VEX_0F72_REG_4 */
12089     { Bad_Opcode },
12090     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
12091   },
12092   {
12093     /* MOD_VEX_0F72_REG_6 */
12094     { Bad_Opcode },
12095     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
12096   },
12097   {
12098     /* MOD_VEX_0F73_REG_2 */
12099     { Bad_Opcode },
12100     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
12101   },
12102   {
12103     /* MOD_VEX_0F73_REG_3 */
12104     { Bad_Opcode },
12105     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
12106   },
12107   {
12108     /* MOD_VEX_0F73_REG_6 */
12109     { Bad_Opcode },
12110     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
12111   },
12112   {
12113     /* MOD_VEX_0F73_REG_7 */
12114     { Bad_Opcode },
12115     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
12116   },
12117   {
12118     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
12119     { "kmovw",          { Ew, MaskG }, 0 },
12120     { Bad_Opcode },
12121   },
12122   {
12123     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
12124     { "kmovq",          { Eq, MaskG }, 0 },
12125     { Bad_Opcode },
12126   },
12127   {
12128     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
12129     { "kmovb",          { Eb, MaskG }, 0 },
12130     { Bad_Opcode },
12131   },
12132   {
12133     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
12134     { "kmovd",          { Ed, MaskG }, 0 },
12135     { Bad_Opcode },
12136   },
12137   {
12138     /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
12139     { Bad_Opcode },
12140     { "kmovw",          { MaskG, Rdq }, 0 },
12141   },
12142   {
12143     /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
12144     { Bad_Opcode },
12145     { "kmovb",          { MaskG, Rdq }, 0 },
12146   },
12147   {
12148     /* MOD_VEX_W_0_0F92_P_3_LEN_0 */
12149     { Bad_Opcode },
12150     { "kmovd",          { MaskG, Rdq }, 0 },
12151   },
12152   {
12153     /* MOD_VEX_W_1_0F92_P_3_LEN_0 */
12154     { Bad_Opcode },
12155     { "kmovq",          { MaskG, Rdq }, 0 },
12156   },
12157   {
12158     /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
12159     { Bad_Opcode },
12160     { "kmovw",          { Gdq, MaskR }, 0 },
12161   },
12162   {
12163     /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
12164     { Bad_Opcode },
12165     { "kmovb",          { Gdq, MaskR }, 0 },
12166   },
12167   {
12168     /* MOD_VEX_W_0_0F93_P_3_LEN_0 */
12169     { Bad_Opcode },
12170     { "kmovd",          { Gdq, MaskR }, 0 },
12171   },
12172   {
12173     /* MOD_VEX_W_1_0F93_P_3_LEN_0 */
12174     { Bad_Opcode },
12175     { "kmovq",          { Gdq, MaskR }, 0 },
12176   },
12177   {
12178     /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
12179     { Bad_Opcode },
12180     { "kortestw", { MaskG, MaskR }, 0 },
12181   },
12182   {
12183     /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
12184     { Bad_Opcode },
12185     { "kortestq", { MaskG, MaskR }, 0 },
12186   },
12187   {
12188     /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
12189     { Bad_Opcode },
12190     { "kortestb", { MaskG, MaskR }, 0 },
12191   },
12192   {
12193     /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
12194     { Bad_Opcode },
12195     { "kortestd", { MaskG, MaskR }, 0 },
12196   },
12197   {
12198     /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
12199     { Bad_Opcode },
12200     { "ktestw", { MaskG, MaskR }, 0 },
12201   },
12202   {
12203     /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
12204     { Bad_Opcode },
12205     { "ktestq", { MaskG, MaskR }, 0 },
12206   },
12207   {
12208     /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
12209     { Bad_Opcode },
12210     { "ktestb", { MaskG, MaskR }, 0 },
12211   },
12212   {
12213     /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
12214     { Bad_Opcode },
12215     { "ktestd", { MaskG, MaskR }, 0 },
12216   },
12217   {
12218     /* MOD_VEX_0FAE_REG_2 */
12219     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
12220   },
12221   {
12222     /* MOD_VEX_0FAE_REG_3 */
12223     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
12224   },
12225   {
12226     /* MOD_VEX_0FD7_PREFIX_2 */
12227     { Bad_Opcode },
12228     { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) },
12229   },
12230   {
12231     /* MOD_VEX_0FE7_PREFIX_2 */
12232     { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) },
12233   },
12234   {
12235     /* MOD_VEX_0FF0_PREFIX_3 */
12236     { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) },
12237   },
12238   {
12239     /* MOD_VEX_0F381A_PREFIX_2 */
12240     { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
12241   },
12242   {
12243     /* MOD_VEX_0F382A_PREFIX_2 */
12244     { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) },
12245   },
12246   {
12247     /* MOD_VEX_0F382C_PREFIX_2 */
12248     { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
12249   },
12250   {
12251     /* MOD_VEX_0F382D_PREFIX_2 */
12252     { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
12253   },
12254   {
12255     /* MOD_VEX_0F382E_PREFIX_2 */
12256     { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
12257   },
12258   {
12259     /* MOD_VEX_0F382F_PREFIX_2 */
12260     { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
12261   },
12262   {
12263     /* MOD_VEX_0F385A_PREFIX_2 */
12264     { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
12265   },
12266   {
12267     /* MOD_VEX_0F388C_PREFIX_2 */
12268     { "vpmaskmov%LW",   { XM, Vex, Mx }, 0 },
12269   },
12270   {
12271     /* MOD_VEX_0F388E_PREFIX_2 */
12272     { "vpmaskmov%LW",   { Mx, Vex, XM }, 0 },
12273   },
12274   {
12275     /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
12276     { Bad_Opcode },
12277     { "kshiftrb",       { MaskG, MaskR, Ib }, 0 },
12278   },
12279   {
12280     /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
12281     { Bad_Opcode },
12282     { "kshiftrw",       { MaskG, MaskR, Ib }, 0 },
12283   },
12284   {
12285     /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
12286     { Bad_Opcode },
12287     { "kshiftrd",       { MaskG, MaskR, Ib }, 0 },
12288   },
12289   {
12290     /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
12291     { Bad_Opcode },
12292     { "kshiftrq",       { MaskG, MaskR, Ib }, 0 },
12293   },
12294   {
12295     /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
12296     { Bad_Opcode },
12297     { "kshiftlb",       { MaskG, MaskR, Ib }, 0 },
12298   },
12299   {
12300     /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
12301     { Bad_Opcode },
12302     { "kshiftlw",       { MaskG, MaskR, Ib }, 0 },
12303   },
12304   {
12305     /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
12306     { Bad_Opcode },
12307     { "kshiftld",       { MaskG, MaskR, Ib }, 0 },
12308   },
12309   {
12310     /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
12311     { Bad_Opcode },
12312     { "kshiftlq",       { MaskG, MaskR, Ib }, 0 },
12313   },
12314 #define NEED_MOD_TABLE
12315 #include "i386-dis-evex.h"
12316 #undef NEED_MOD_TABLE
12317 };
12318
12319 static const struct dis386 rm_table[][8] = {
12320   {
12321     /* RM_C6_REG_7 */
12322     { "xabort",         { Skip_MODRM, Ib }, 0 },
12323   },
12324   {
12325     /* RM_C7_REG_7 */
12326     { "xbeginT",        { Skip_MODRM, Jv }, 0 },
12327   },
12328   {
12329     /* RM_0F01_REG_0 */
12330     { Bad_Opcode },
12331     { "vmcall",         { Skip_MODRM }, 0 },
12332     { "vmlaunch",       { Skip_MODRM }, 0 },
12333     { "vmresume",       { Skip_MODRM }, 0 },
12334     { "vmxoff",         { Skip_MODRM }, 0 },
12335     { "pconfig",        { Skip_MODRM }, 0 },
12336   },
12337   {
12338     /* RM_0F01_REG_1 */
12339     { "monitor",        { { OP_Monitor, 0 } }, 0 },
12340     { "mwait",          { { OP_Mwait, 0 } }, 0 },
12341     { "clac",           { Skip_MODRM }, 0 },
12342     { "stac",           { Skip_MODRM }, 0 },
12343     { Bad_Opcode },
12344     { Bad_Opcode },
12345     { Bad_Opcode },
12346     { "encls",          { Skip_MODRM }, 0 },
12347   },
12348   {
12349     /* RM_0F01_REG_2 */
12350     { "xgetbv",         { Skip_MODRM }, 0 },
12351     { "xsetbv",         { Skip_MODRM }, 0 },
12352     { Bad_Opcode },
12353     { Bad_Opcode },
12354     { "vmfunc",         { Skip_MODRM }, 0 },
12355     { "xend",           { Skip_MODRM }, 0 },
12356     { "xtest",          { Skip_MODRM }, 0 },
12357     { "enclu",          { Skip_MODRM }, 0 },
12358   },
12359   {
12360     /* RM_0F01_REG_3 */
12361     { "vmrun",          { Skip_MODRM }, 0 },
12362     { "vmmcall",        { Skip_MODRM }, 0 },
12363     { "vmload",         { Skip_MODRM }, 0 },
12364     { "vmsave",         { Skip_MODRM }, 0 },
12365     { "stgi",           { Skip_MODRM }, 0 },
12366     { "clgi",           { Skip_MODRM }, 0 },
12367     { "skinit",         { Skip_MODRM }, 0 },
12368     { "invlpga",        { Skip_MODRM }, 0 },
12369   },
12370   {
12371     /* RM_0F01_REG_5 */
12372     { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_0) },
12373     { Bad_Opcode },
12374     { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_2) },
12375     { Bad_Opcode },
12376     { Bad_Opcode },
12377     { Bad_Opcode },
12378     { "rdpkru",         { Skip_MODRM }, 0 },
12379     { "wrpkru",         { Skip_MODRM }, 0 },
12380   },
12381   {
12382     /* RM_0F01_REG_7 */
12383     { "swapgs",         { Skip_MODRM }, 0  },
12384     { "rdtscp",         { Skip_MODRM }, 0  },
12385     { "monitorx",       { { OP_Monitor, 0 } }, 0  },
12386     { "mwaitx",         { { OP_Mwaitx,  0 } }, 0  },
12387     { "clzero",         { Skip_MODRM }, 0  },
12388   },
12389   {
12390     /* RM_0F1E_MOD_3_REG_7 */
12391     { "nopQ",           { Ev }, 0 },
12392     { "nopQ",           { Ev }, 0 },
12393     { "endbr64",        { Skip_MODRM },  PREFIX_OPCODE },
12394     { "endbr32",        { Skip_MODRM },  PREFIX_OPCODE },
12395     { "nopQ",           { Ev }, 0 },
12396     { "nopQ",           { Ev }, 0 },
12397     { "nopQ",           { Ev }, 0 },
12398     { "nopQ",           { Ev }, 0 },
12399   },
12400   {
12401     /* RM_0FAE_REG_6 */
12402     { "mfence",         { Skip_MODRM }, 0 },
12403   },
12404   {
12405     /* RM_0FAE_REG_7 */
12406     { "sfence",         { Skip_MODRM }, 0 },
12407
12408   },
12409 };
12410
12411 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
12412
12413 /* We use the high bit to indicate different name for the same
12414    prefix.  */
12415 #define REP_PREFIX      (0xf3 | 0x100)
12416 #define XACQUIRE_PREFIX (0xf2 | 0x200)
12417 #define XRELEASE_PREFIX (0xf3 | 0x400)
12418 #define BND_PREFIX      (0xf2 | 0x400)
12419 #define NOTRACK_PREFIX  (0x3e | 0x100)
12420
12421 static int
12422 ckprefix (void)
12423 {
12424   int newrex, i, length;
12425   rex = 0;
12426   rex_ignored = 0;
12427   prefixes = 0;
12428   used_prefixes = 0;
12429   rex_used = 0;
12430   last_lock_prefix = -1;
12431   last_repz_prefix = -1;
12432   last_repnz_prefix = -1;
12433   last_data_prefix = -1;
12434   last_addr_prefix = -1;
12435   last_rex_prefix = -1;
12436   last_seg_prefix = -1;
12437   fwait_prefix = -1;
12438   active_seg_prefix = 0;
12439   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12440     all_prefixes[i] = 0;
12441   i = 0;
12442   length = 0;
12443   /* The maximum instruction length is 15bytes.  */
12444   while (length < MAX_CODE_LENGTH - 1)
12445     {
12446       FETCH_DATA (the_info, codep + 1);
12447       newrex = 0;
12448       switch (*codep)
12449         {
12450         /* REX prefixes family.  */
12451         case 0x40:
12452         case 0x41:
12453         case 0x42:
12454         case 0x43:
12455         case 0x44:
12456         case 0x45:
12457         case 0x46:
12458         case 0x47:
12459         case 0x48:
12460         case 0x49:
12461         case 0x4a:
12462         case 0x4b:
12463         case 0x4c:
12464         case 0x4d:
12465         case 0x4e:
12466         case 0x4f:
12467           if (address_mode == mode_64bit)
12468             newrex = *codep;
12469           else
12470             return 1;
12471           last_rex_prefix = i;
12472           break;
12473         case 0xf3:
12474           prefixes |= PREFIX_REPZ;
12475           last_repz_prefix = i;
12476           break;
12477         case 0xf2:
12478           prefixes |= PREFIX_REPNZ;
12479           last_repnz_prefix = i;
12480           break;
12481         case 0xf0:
12482           prefixes |= PREFIX_LOCK;
12483           last_lock_prefix = i;
12484           break;
12485         case 0x2e:
12486           prefixes |= PREFIX_CS;
12487           last_seg_prefix = i;
12488           active_seg_prefix = PREFIX_CS;
12489           break;
12490         case 0x36:
12491           prefixes |= PREFIX_SS;
12492           last_seg_prefix = i;
12493           active_seg_prefix = PREFIX_SS;
12494           break;
12495         case 0x3e:
12496           prefixes |= PREFIX_DS;
12497           last_seg_prefix = i;
12498           active_seg_prefix = PREFIX_DS;
12499           break;
12500         case 0x26:
12501           prefixes |= PREFIX_ES;
12502           last_seg_prefix = i;
12503           active_seg_prefix = PREFIX_ES;
12504           break;
12505         case 0x64:
12506           prefixes |= PREFIX_FS;
12507           last_seg_prefix = i;
12508           active_seg_prefix = PREFIX_FS;
12509           break;
12510         case 0x65:
12511           prefixes |= PREFIX_GS;
12512           last_seg_prefix = i;
12513           active_seg_prefix = PREFIX_GS;
12514           break;
12515         case 0x66:
12516           prefixes |= PREFIX_DATA;
12517           last_data_prefix = i;
12518           break;
12519         case 0x67:
12520           prefixes |= PREFIX_ADDR;
12521           last_addr_prefix = i;
12522           break;
12523         case FWAIT_OPCODE:
12524           /* fwait is really an instruction.  If there are prefixes
12525              before the fwait, they belong to the fwait, *not* to the
12526              following instruction.  */
12527           fwait_prefix = i;
12528           if (prefixes || rex)
12529             {
12530               prefixes |= PREFIX_FWAIT;
12531               codep++;
12532               /* This ensures that the previous REX prefixes are noticed
12533                  as unused prefixes, as in the return case below.  */
12534               rex_used = rex;
12535               return 1;
12536             }
12537           prefixes = PREFIX_FWAIT;
12538           break;
12539         default:
12540           return 1;
12541         }
12542       /* Rex is ignored when followed by another prefix.  */
12543       if (rex)
12544         {
12545           rex_used = rex;
12546           return 1;
12547         }
12548       if (*codep != FWAIT_OPCODE)
12549         all_prefixes[i++] = *codep;
12550       rex = newrex;
12551       codep++;
12552       length++;
12553     }
12554   return 0;
12555 }
12556
12557 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
12558    prefix byte.  */
12559
12560 static const char *
12561 prefix_name (int pref, int sizeflag)
12562 {
12563   static const char *rexes [16] =
12564     {
12565       "rex",            /* 0x40 */
12566       "rex.B",          /* 0x41 */
12567       "rex.X",          /* 0x42 */
12568       "rex.XB",         /* 0x43 */
12569       "rex.R",          /* 0x44 */
12570       "rex.RB",         /* 0x45 */
12571       "rex.RX",         /* 0x46 */
12572       "rex.RXB",        /* 0x47 */
12573       "rex.W",          /* 0x48 */
12574       "rex.WB",         /* 0x49 */
12575       "rex.WX",         /* 0x4a */
12576       "rex.WXB",        /* 0x4b */
12577       "rex.WR",         /* 0x4c */
12578       "rex.WRB",        /* 0x4d */
12579       "rex.WRX",        /* 0x4e */
12580       "rex.WRXB",       /* 0x4f */
12581     };
12582
12583   switch (pref)
12584     {
12585     /* REX prefixes family.  */
12586     case 0x40:
12587     case 0x41:
12588     case 0x42:
12589     case 0x43:
12590     case 0x44:
12591     case 0x45:
12592     case 0x46:
12593     case 0x47:
12594     case 0x48:
12595     case 0x49:
12596     case 0x4a:
12597     case 0x4b:
12598     case 0x4c:
12599     case 0x4d:
12600     case 0x4e:
12601     case 0x4f:
12602       return rexes [pref - 0x40];
12603     case 0xf3:
12604       return "repz";
12605     case 0xf2:
12606       return "repnz";
12607     case 0xf0:
12608       return "lock";
12609     case 0x2e:
12610       return "cs";
12611     case 0x36:
12612       return "ss";
12613     case 0x3e:
12614       return "ds";
12615     case 0x26:
12616       return "es";
12617     case 0x64:
12618       return "fs";
12619     case 0x65:
12620       return "gs";
12621     case 0x66:
12622       return (sizeflag & DFLAG) ? "data16" : "data32";
12623     case 0x67:
12624       if (address_mode == mode_64bit)
12625         return (sizeflag & AFLAG) ? "addr32" : "addr64";
12626       else
12627         return (sizeflag & AFLAG) ? "addr16" : "addr32";
12628     case FWAIT_OPCODE:
12629       return "fwait";
12630     case REP_PREFIX:
12631       return "rep";
12632     case XACQUIRE_PREFIX:
12633       return "xacquire";
12634     case XRELEASE_PREFIX:
12635       return "xrelease";
12636     case BND_PREFIX:
12637       return "bnd";
12638     case NOTRACK_PREFIX:
12639       return "notrack";
12640     default:
12641       return NULL;
12642     }
12643 }
12644
12645 static char op_out[MAX_OPERANDS][100];
12646 static int op_ad, op_index[MAX_OPERANDS];
12647 static int two_source_ops;
12648 static bfd_vma op_address[MAX_OPERANDS];
12649 static bfd_vma op_riprel[MAX_OPERANDS];
12650 static bfd_vma start_pc;
12651
12652 /*
12653  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
12654  *   (see topic "Redundant prefixes" in the "Differences from 8086"
12655  *   section of the "Virtual 8086 Mode" chapter.)
12656  * 'pc' should be the address of this instruction, it will
12657  *   be used to print the target address if this is a relative jump or call
12658  * The function returns the length of this instruction in bytes.
12659  */
12660
12661 static char intel_syntax;
12662 static char intel_mnemonic = !SYSV386_COMPAT;
12663 static char open_char;
12664 static char close_char;
12665 static char separator_char;
12666 static char scale_char;
12667
12668 enum x86_64_isa
12669 {
12670   amd64 = 0,
12671   intel64
12672 };
12673
12674 static enum x86_64_isa isa64;
12675
12676 /* Here for backwards compatibility.  When gdb stops using
12677    print_insn_i386_att and print_insn_i386_intel these functions can
12678    disappear, and print_insn_i386 be merged into print_insn.  */
12679 int
12680 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
12681 {
12682   intel_syntax = 0;
12683
12684   return print_insn (pc, info);
12685 }
12686
12687 int
12688 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
12689 {
12690   intel_syntax = 1;
12691
12692   return print_insn (pc, info);
12693 }
12694
12695 int
12696 print_insn_i386 (bfd_vma pc, disassemble_info *info)
12697 {
12698   intel_syntax = -1;
12699
12700   return print_insn (pc, info);
12701 }
12702
12703 void
12704 print_i386_disassembler_options (FILE *stream)
12705 {
12706   fprintf (stream, _("\n\
12707 The following i386/x86-64 specific disassembler options are supported for use\n\
12708 with the -M switch (multiple options should be separated by commas):\n"));
12709
12710   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
12711   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
12712   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
12713   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
12714   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
12715   fprintf (stream, _("  att-mnemonic\n"
12716                      "              Display instruction in AT&T mnemonic\n"));
12717   fprintf (stream, _("  intel-mnemonic\n"
12718                      "              Display instruction in Intel mnemonic\n"));
12719   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
12720   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
12721   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
12722   fprintf (stream, _("  data32      Assume 32bit data size\n"));
12723   fprintf (stream, _("  data16      Assume 16bit data size\n"));
12724   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
12725   fprintf (stream, _("  amd64       Display instruction in AMD64 ISA\n"));
12726   fprintf (stream, _("  intel64     Display instruction in Intel64 ISA\n"));
12727 }
12728
12729 /* Bad opcode.  */
12730 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
12731
12732 /* Get a pointer to struct dis386 with a valid name.  */
12733
12734 static const struct dis386 *
12735 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
12736 {
12737   int vindex, vex_table_index;
12738
12739   if (dp->name != NULL)
12740     return dp;
12741
12742   switch (dp->op[0].bytemode)
12743     {
12744     case USE_REG_TABLE:
12745       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
12746       break;
12747
12748     case USE_MOD_TABLE:
12749       vindex = modrm.mod == 0x3 ? 1 : 0;
12750       dp = &mod_table[dp->op[1].bytemode][vindex];
12751       break;
12752
12753     case USE_RM_TABLE:
12754       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
12755       break;
12756
12757     case USE_PREFIX_TABLE:
12758       if (need_vex)
12759         {
12760           /* The prefix in VEX is implicit.  */
12761           switch (vex.prefix)
12762             {
12763             case 0:
12764               vindex = 0;
12765               break;
12766             case REPE_PREFIX_OPCODE:
12767               vindex = 1;
12768               break;
12769             case DATA_PREFIX_OPCODE:
12770               vindex = 2;
12771               break;
12772             case REPNE_PREFIX_OPCODE:
12773               vindex = 3;
12774               break;
12775             default:
12776               abort ();
12777               break;
12778             }
12779         }
12780       else
12781         {
12782           int last_prefix = -1;
12783           int prefix = 0;
12784           vindex = 0;
12785           /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
12786              When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
12787              last one wins.  */
12788           if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
12789             {
12790               if (last_repz_prefix > last_repnz_prefix)
12791                 {
12792                   vindex = 1;
12793                   prefix = PREFIX_REPZ;
12794                   last_prefix = last_repz_prefix;
12795                 }
12796               else
12797                 {
12798                   vindex = 3;
12799                   prefix = PREFIX_REPNZ;
12800                   last_prefix = last_repnz_prefix;
12801                 }
12802
12803               /* Check if prefix should be ignored.  */
12804               if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
12805                      & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
12806                    & prefix) != 0)
12807                 vindex = 0;
12808             }
12809
12810           if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
12811             {
12812               vindex = 2;
12813               prefix = PREFIX_DATA;
12814               last_prefix = last_data_prefix;
12815             }
12816
12817           if (vindex != 0)
12818             {
12819               used_prefixes |= prefix;
12820               all_prefixes[last_prefix] = 0;
12821             }
12822         }
12823       dp = &prefix_table[dp->op[1].bytemode][vindex];
12824       break;
12825
12826     case USE_X86_64_TABLE:
12827       vindex = address_mode == mode_64bit ? 1 : 0;
12828       dp = &x86_64_table[dp->op[1].bytemode][vindex];
12829       break;
12830
12831     case USE_3BYTE_TABLE:
12832       FETCH_DATA (info, codep + 2);
12833       vindex = *codep++;
12834       dp = &three_byte_table[dp->op[1].bytemode][vindex];
12835       end_codep = codep;
12836       modrm.mod = (*codep >> 6) & 3;
12837       modrm.reg = (*codep >> 3) & 7;
12838       modrm.rm = *codep & 7;
12839       break;
12840
12841     case USE_VEX_LEN_TABLE:
12842       if (!need_vex)
12843         abort ();
12844
12845       switch (vex.length)
12846         {
12847         case 128:
12848           vindex = 0;
12849           break;
12850         case 256:
12851           vindex = 1;
12852           break;
12853         default:
12854           abort ();
12855           break;
12856         }
12857
12858       dp = &vex_len_table[dp->op[1].bytemode][vindex];
12859       break;
12860
12861     case USE_XOP_8F_TABLE:
12862       FETCH_DATA (info, codep + 3);
12863       /* All bits in the REX prefix are ignored.  */
12864       rex_ignored = rex;
12865       rex = ~(*codep >> 5) & 0x7;
12866
12867       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
12868       switch ((*codep & 0x1f))
12869         {
12870         default:
12871           dp = &bad_opcode;
12872           return dp;
12873         case 0x8:
12874           vex_table_index = XOP_08;
12875           break;
12876         case 0x9:
12877           vex_table_index = XOP_09;
12878           break;
12879         case 0xa:
12880           vex_table_index = XOP_0A;
12881           break;
12882         }
12883       codep++;
12884       vex.w = *codep & 0x80;
12885       if (vex.w && address_mode == mode_64bit)
12886         rex |= REX_W;
12887
12888       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12889       if (address_mode != mode_64bit)
12890         {
12891           /* In 16/32-bit mode REX_B is silently ignored.  */
12892           rex &= ~REX_B;
12893         }
12894
12895       vex.length = (*codep & 0x4) ? 256 : 128;
12896       switch ((*codep & 0x3))
12897         {
12898         case 0:
12899           break;
12900         case 1:
12901           vex.prefix = DATA_PREFIX_OPCODE;
12902           break;
12903         case 2:
12904           vex.prefix = REPE_PREFIX_OPCODE;
12905           break;
12906         case 3:
12907           vex.prefix = REPNE_PREFIX_OPCODE;
12908           break;
12909         }
12910       need_vex = 1;
12911       need_vex_reg = 1;
12912       codep++;
12913       vindex = *codep++;
12914       dp = &xop_table[vex_table_index][vindex];
12915
12916       end_codep = codep;
12917       FETCH_DATA (info, codep + 1);
12918       modrm.mod = (*codep >> 6) & 3;
12919       modrm.reg = (*codep >> 3) & 7;
12920       modrm.rm = *codep & 7;
12921       break;
12922
12923     case USE_VEX_C4_TABLE:
12924       /* VEX prefix.  */
12925       FETCH_DATA (info, codep + 3);
12926       /* All bits in the REX prefix are ignored.  */
12927       rex_ignored = rex;
12928       rex = ~(*codep >> 5) & 0x7;
12929       switch ((*codep & 0x1f))
12930         {
12931         default:
12932           dp = &bad_opcode;
12933           return dp;
12934         case 0x1:
12935           vex_table_index = VEX_0F;
12936           break;
12937         case 0x2:
12938           vex_table_index = VEX_0F38;
12939           break;
12940         case 0x3:
12941           vex_table_index = VEX_0F3A;
12942           break;
12943         }
12944       codep++;
12945       vex.w = *codep & 0x80;
12946       if (address_mode == mode_64bit)
12947         {
12948           if (vex.w)
12949             rex |= REX_W;
12950         }
12951       else
12952         {
12953           /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
12954              is ignored, other REX bits are 0 and the highest bit in
12955              VEX.vvvv is also ignored (but we mustn't clear it here).  */
12956           rex = 0;
12957         }
12958       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12959       vex.length = (*codep & 0x4) ? 256 : 128;
12960       switch ((*codep & 0x3))
12961         {
12962         case 0:
12963           break;
12964         case 1:
12965           vex.prefix = DATA_PREFIX_OPCODE;
12966           break;
12967         case 2:
12968           vex.prefix = REPE_PREFIX_OPCODE;
12969           break;
12970         case 3:
12971           vex.prefix = REPNE_PREFIX_OPCODE;
12972           break;
12973         }
12974       need_vex = 1;
12975       need_vex_reg = 1;
12976       codep++;
12977       vindex = *codep++;
12978       dp = &vex_table[vex_table_index][vindex];
12979       end_codep = codep;
12980       /* There is no MODRM byte for VEX0F 77.  */
12981       if (vex_table_index != VEX_0F || vindex != 0x77)
12982         {
12983           FETCH_DATA (info, codep + 1);
12984           modrm.mod = (*codep >> 6) & 3;
12985           modrm.reg = (*codep >> 3) & 7;
12986           modrm.rm = *codep & 7;
12987         }
12988       break;
12989
12990     case USE_VEX_C5_TABLE:
12991       /* VEX prefix.  */
12992       FETCH_DATA (info, codep + 2);
12993       /* All bits in the REX prefix are ignored.  */
12994       rex_ignored = rex;
12995       rex = (*codep & 0x80) ? 0 : REX_R;
12996
12997       /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
12998          VEX.vvvv is 1.  */
12999       vex.register_specifier = (~(*codep >> 3)) & 0xf;
13000       vex.length = (*codep & 0x4) ? 256 : 128;
13001       switch ((*codep & 0x3))
13002         {
13003         case 0:
13004           break;
13005         case 1:
13006           vex.prefix = DATA_PREFIX_OPCODE;
13007           break;
13008         case 2:
13009           vex.prefix = REPE_PREFIX_OPCODE;
13010           break;
13011         case 3:
13012           vex.prefix = REPNE_PREFIX_OPCODE;
13013           break;
13014         }
13015       need_vex = 1;
13016       need_vex_reg = 1;
13017       codep++;
13018       vindex = *codep++;
13019       dp = &vex_table[dp->op[1].bytemode][vindex];
13020       end_codep = codep;
13021       /* There is no MODRM byte for VEX 77.  */
13022       if (vindex != 0x77)
13023         {
13024           FETCH_DATA (info, codep + 1);
13025           modrm.mod = (*codep >> 6) & 3;
13026           modrm.reg = (*codep >> 3) & 7;
13027           modrm.rm = *codep & 7;
13028         }
13029       break;
13030
13031     case USE_VEX_W_TABLE:
13032       if (!need_vex)
13033         abort ();
13034
13035       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
13036       break;
13037
13038     case USE_EVEX_TABLE:
13039       two_source_ops = 0;
13040       /* EVEX prefix.  */
13041       vex.evex = 1;
13042       FETCH_DATA (info, codep + 4);
13043       /* All bits in the REX prefix are ignored.  */
13044       rex_ignored = rex;
13045       /* The first byte after 0x62.  */
13046       rex = ~(*codep >> 5) & 0x7;
13047       vex.r = *codep & 0x10;
13048       switch ((*codep & 0xf))
13049         {
13050         default:
13051           return &bad_opcode;
13052         case 0x1:
13053           vex_table_index = EVEX_0F;
13054           break;
13055         case 0x2:
13056           vex_table_index = EVEX_0F38;
13057           break;
13058         case 0x3:
13059           vex_table_index = EVEX_0F3A;
13060           break;
13061         }
13062
13063       /* The second byte after 0x62.  */
13064       codep++;
13065       vex.w = *codep & 0x80;
13066       if (vex.w && address_mode == mode_64bit)
13067         rex |= REX_W;
13068
13069       vex.register_specifier = (~(*codep >> 3)) & 0xf;
13070
13071       /* The U bit.  */
13072       if (!(*codep & 0x4))
13073         return &bad_opcode;
13074
13075       switch ((*codep & 0x3))
13076         {
13077         case 0:
13078           break;
13079         case 1:
13080           vex.prefix = DATA_PREFIX_OPCODE;
13081           break;
13082         case 2:
13083           vex.prefix = REPE_PREFIX_OPCODE;
13084           break;
13085         case 3:
13086           vex.prefix = REPNE_PREFIX_OPCODE;
13087           break;
13088         }
13089
13090       /* The third byte after 0x62.  */
13091       codep++;
13092
13093       /* Remember the static rounding bits.  */
13094       vex.ll = (*codep >> 5) & 3;
13095       vex.b = (*codep & 0x10) != 0;
13096
13097       vex.v = *codep & 0x8;
13098       vex.mask_register_specifier = *codep & 0x7;
13099       vex.zeroing = *codep & 0x80;
13100
13101       if (address_mode != mode_64bit)
13102         {
13103           /* In 16/32-bit mode silently ignore following bits.  */
13104           rex &= ~REX_B;
13105           vex.r = 1;
13106           vex.v = 1;
13107         }
13108
13109       need_vex = 1;
13110       need_vex_reg = 1;
13111       codep++;
13112       vindex = *codep++;
13113       dp = &evex_table[vex_table_index][vindex];
13114       end_codep = codep;
13115       FETCH_DATA (info, codep + 1);
13116       modrm.mod = (*codep >> 6) & 3;
13117       modrm.reg = (*codep >> 3) & 7;
13118       modrm.rm = *codep & 7;
13119
13120       /* Set vector length.  */
13121       if (modrm.mod == 3 && vex.b)
13122         vex.length = 512;
13123       else
13124         {
13125           switch (vex.ll)
13126             {
13127             case 0x0:
13128               vex.length = 128;
13129               break;
13130             case 0x1:
13131               vex.length = 256;
13132               break;
13133             case 0x2:
13134               vex.length = 512;
13135               break;
13136             default:
13137               return &bad_opcode;
13138             }
13139         }
13140       break;
13141
13142     case 0:
13143       dp = &bad_opcode;
13144       break;
13145
13146     default:
13147       abort ();
13148     }
13149
13150   if (dp->name != NULL)
13151     return dp;
13152   else
13153     return get_valid_dis386 (dp, info);
13154 }
13155
13156 static void
13157 get_sib (disassemble_info *info, int sizeflag)
13158 {
13159   /* If modrm.mod == 3, operand must be register.  */
13160   if (need_modrm
13161       && ((sizeflag & AFLAG) || address_mode == mode_64bit)
13162       && modrm.mod != 3
13163       && modrm.rm == 4)
13164     {
13165       FETCH_DATA (info, codep + 2);
13166       sib.index = (codep [1] >> 3) & 7;
13167       sib.scale = (codep [1] >> 6) & 3;
13168       sib.base = codep [1] & 7;
13169     }
13170 }
13171
13172 static int
13173 print_insn (bfd_vma pc, disassemble_info *info)
13174 {
13175   const struct dis386 *dp;
13176   int i;
13177   char *op_txt[MAX_OPERANDS];
13178   int needcomma;
13179   int sizeflag, orig_sizeflag;
13180   const char *p;
13181   struct dis_private priv;
13182   int prefix_length;
13183
13184   priv.orig_sizeflag = AFLAG | DFLAG;
13185   if ((info->mach & bfd_mach_i386_i386) != 0)
13186     address_mode = mode_32bit;
13187   else if (info->mach == bfd_mach_i386_i8086)
13188     {
13189       address_mode = mode_16bit;
13190       priv.orig_sizeflag = 0;
13191     }
13192   else
13193     address_mode = mode_64bit;
13194
13195   if (intel_syntax == (char) -1)
13196     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
13197
13198   for (p = info->disassembler_options; p != NULL; )
13199     {
13200       if (CONST_STRNEQ (p, "amd64"))
13201         isa64 = amd64;
13202       else if (CONST_STRNEQ (p, "intel64"))
13203         isa64 = intel64;
13204       else if (CONST_STRNEQ (p, "x86-64"))
13205         {
13206           address_mode = mode_64bit;
13207           priv.orig_sizeflag = AFLAG | DFLAG;
13208         }
13209       else if (CONST_STRNEQ (p, "i386"))
13210         {
13211           address_mode = mode_32bit;
13212           priv.orig_sizeflag = AFLAG | DFLAG;
13213         }
13214       else if (CONST_STRNEQ (p, "i8086"))
13215         {
13216           address_mode = mode_16bit;
13217           priv.orig_sizeflag = 0;
13218         }
13219       else if (CONST_STRNEQ (p, "intel"))
13220         {
13221           intel_syntax = 1;
13222           if (CONST_STRNEQ (p + 5, "-mnemonic"))
13223             intel_mnemonic = 1;
13224         }
13225       else if (CONST_STRNEQ (p, "att"))
13226         {
13227           intel_syntax = 0;
13228           if (CONST_STRNEQ (p + 3, "-mnemonic"))
13229             intel_mnemonic = 0;
13230         }
13231       else if (CONST_STRNEQ (p, "addr"))
13232         {
13233           if (address_mode == mode_64bit)
13234             {
13235               if (p[4] == '3' && p[5] == '2')
13236                 priv.orig_sizeflag &= ~AFLAG;
13237               else if (p[4] == '6' && p[5] == '4')
13238                 priv.orig_sizeflag |= AFLAG;
13239             }
13240           else
13241             {
13242               if (p[4] == '1' && p[5] == '6')
13243                 priv.orig_sizeflag &= ~AFLAG;
13244               else if (p[4] == '3' && p[5] == '2')
13245                 priv.orig_sizeflag |= AFLAG;
13246             }
13247         }
13248       else if (CONST_STRNEQ (p, "data"))
13249         {
13250           if (p[4] == '1' && p[5] == '6')
13251             priv.orig_sizeflag &= ~DFLAG;
13252           else if (p[4] == '3' && p[5] == '2')
13253             priv.orig_sizeflag |= DFLAG;
13254         }
13255       else if (CONST_STRNEQ (p, "suffix"))
13256         priv.orig_sizeflag |= SUFFIX_ALWAYS;
13257
13258       p = strchr (p, ',');
13259       if (p != NULL)
13260         p++;
13261     }
13262
13263   if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
13264     {
13265       (*info->fprintf_func) (info->stream,
13266                              _("64-bit address is disabled"));
13267       return -1;
13268     }
13269
13270   if (intel_syntax)
13271     {
13272       names64 = intel_names64;
13273       names32 = intel_names32;
13274       names16 = intel_names16;
13275       names8 = intel_names8;
13276       names8rex = intel_names8rex;
13277       names_seg = intel_names_seg;
13278       names_mm = intel_names_mm;
13279       names_bnd = intel_names_bnd;
13280       names_xmm = intel_names_xmm;
13281       names_ymm = intel_names_ymm;
13282       names_zmm = intel_names_zmm;
13283       index64 = intel_index64;
13284       index32 = intel_index32;
13285       names_mask = intel_names_mask;
13286       index16 = intel_index16;
13287       open_char = '[';
13288       close_char = ']';
13289       separator_char = '+';
13290       scale_char = '*';
13291     }
13292   else
13293     {
13294       names64 = att_names64;
13295       names32 = att_names32;
13296       names16 = att_names16;
13297       names8 = att_names8;
13298       names8rex = att_names8rex;
13299       names_seg = att_names_seg;
13300       names_mm = att_names_mm;
13301       names_bnd = att_names_bnd;
13302       names_xmm = att_names_xmm;
13303       names_ymm = att_names_ymm;
13304       names_zmm = att_names_zmm;
13305       index64 = att_index64;
13306       index32 = att_index32;
13307       names_mask = att_names_mask;
13308       index16 = att_index16;
13309       open_char = '(';
13310       close_char =  ')';
13311       separator_char = ',';
13312       scale_char = ',';
13313     }
13314
13315   /* The output looks better if we put 7 bytes on a line, since that
13316      puts most long word instructions on a single line.  Use 8 bytes
13317      for Intel L1OM.  */
13318   if ((info->mach & bfd_mach_l1om) != 0)
13319     info->bytes_per_line = 8;
13320   else
13321     info->bytes_per_line = 7;
13322
13323   info->private_data = &priv;
13324   priv.max_fetched = priv.the_buffer;
13325   priv.insn_start = pc;
13326
13327   obuf[0] = 0;
13328   for (i = 0; i < MAX_OPERANDS; ++i)
13329     {
13330       op_out[i][0] = 0;
13331       op_index[i] = -1;
13332     }
13333
13334   the_info = info;
13335   start_pc = pc;
13336   start_codep = priv.the_buffer;
13337   codep = priv.the_buffer;
13338
13339   if (OPCODES_SIGSETJMP (priv.bailout) != 0)
13340     {
13341       const char *name;
13342
13343       /* Getting here means we tried for data but didn't get it.  That
13344          means we have an incomplete instruction of some sort.  Just
13345          print the first byte as a prefix or a .byte pseudo-op.  */
13346       if (codep > priv.the_buffer)
13347         {
13348           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
13349           if (name != NULL)
13350             (*info->fprintf_func) (info->stream, "%s", name);
13351           else
13352             {
13353               /* Just print the first byte as a .byte instruction.  */
13354               (*info->fprintf_func) (info->stream, ".byte 0x%x",
13355                                      (unsigned int) priv.the_buffer[0]);
13356             }
13357
13358           return 1;
13359         }
13360
13361       return -1;
13362     }
13363
13364   obufp = obuf;
13365   sizeflag = priv.orig_sizeflag;
13366
13367   if (!ckprefix () || rex_used)
13368     {
13369       /* Too many prefixes or unused REX prefixes.  */
13370       for (i = 0;
13371            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
13372            i++)
13373         (*info->fprintf_func) (info->stream, "%s%s",
13374                                i == 0 ? "" : " ",
13375                                prefix_name (all_prefixes[i], sizeflag));
13376       return i;
13377     }
13378
13379   insn_codep = codep;
13380
13381   FETCH_DATA (info, codep + 1);
13382   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
13383
13384   if (((prefixes & PREFIX_FWAIT)
13385        && ((*codep < 0xd8) || (*codep > 0xdf))))
13386     {
13387       /* Handle prefixes before fwait.  */
13388       for (i = 0; i < fwait_prefix && all_prefixes[i];
13389            i++)
13390         (*info->fprintf_func) (info->stream, "%s ",
13391                                prefix_name (all_prefixes[i], sizeflag));
13392       (*info->fprintf_func) (info->stream, "fwait");
13393       return i + 1;
13394     }
13395
13396   if (*codep == 0x0f)
13397     {
13398       unsigned char threebyte;
13399
13400       codep++;
13401       FETCH_DATA (info, codep + 1);
13402       threebyte = *codep;
13403       dp = &dis386_twobyte[threebyte];
13404       need_modrm = twobyte_has_modrm[*codep];
13405       codep++;
13406     }
13407   else
13408     {
13409       dp = &dis386[*codep];
13410       need_modrm = onebyte_has_modrm[*codep];
13411       codep++;
13412     }
13413
13414   /* Save sizeflag for printing the extra prefixes later before updating
13415      it for mnemonic and operand processing.  The prefix names depend
13416      only on the address mode.  */
13417   orig_sizeflag = sizeflag;
13418   if (prefixes & PREFIX_ADDR)
13419     sizeflag ^= AFLAG;
13420   if ((prefixes & PREFIX_DATA))
13421     sizeflag ^= DFLAG;
13422
13423   end_codep = codep;
13424   if (need_modrm)
13425     {
13426       FETCH_DATA (info, codep + 1);
13427       modrm.mod = (*codep >> 6) & 3;
13428       modrm.reg = (*codep >> 3) & 7;
13429       modrm.rm = *codep & 7;
13430     }
13431
13432   need_vex = 0;
13433   need_vex_reg = 0;
13434   vex_w_done = 0;
13435   memset (&vex, 0, sizeof (vex));
13436
13437   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
13438     {
13439       get_sib (info, sizeflag);
13440       dofloat (sizeflag);
13441     }
13442   else
13443     {
13444       dp = get_valid_dis386 (dp, info);
13445       if (dp != NULL && putop (dp->name, sizeflag) == 0)
13446         {
13447           get_sib (info, sizeflag);
13448           for (i = 0; i < MAX_OPERANDS; ++i)
13449             {
13450               obufp = op_out[i];
13451               op_ad = MAX_OPERANDS - 1 - i;
13452               if (dp->op[i].rtn)
13453                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
13454               /* For EVEX instruction after the last operand masking
13455                  should be printed.  */
13456               if (i == 0 && vex.evex)
13457                 {
13458                   /* Don't print {%k0}.  */
13459                   if (vex.mask_register_specifier)
13460                     {
13461                       oappend ("{");
13462                       oappend (names_mask[vex.mask_register_specifier]);
13463                       oappend ("}");
13464                     }
13465                   if (vex.zeroing)
13466                     oappend ("{z}");
13467                 }
13468             }
13469         }
13470     }
13471
13472   /* Check if the REX prefix is used.  */
13473   if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)
13474     all_prefixes[last_rex_prefix] = 0;
13475
13476   /* Check if the SEG prefix is used.  */
13477   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
13478                    | PREFIX_FS | PREFIX_GS)) != 0
13479       && (used_prefixes & active_seg_prefix) != 0)
13480     all_prefixes[last_seg_prefix] = 0;
13481
13482   /* Check if the ADDR prefix is used.  */
13483   if ((prefixes & PREFIX_ADDR) != 0
13484       && (used_prefixes & PREFIX_ADDR) != 0)
13485     all_prefixes[last_addr_prefix] = 0;
13486
13487   /* Check if the DATA prefix is used.  */
13488   if ((prefixes & PREFIX_DATA) != 0
13489       && (used_prefixes & PREFIX_DATA) != 0)
13490     all_prefixes[last_data_prefix] = 0;
13491
13492   /* Print the extra prefixes.  */
13493   prefix_length = 0;
13494   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
13495     if (all_prefixes[i])
13496       {
13497         const char *name;
13498         name = prefix_name (all_prefixes[i], orig_sizeflag);
13499         if (name == NULL)
13500           abort ();
13501         prefix_length += strlen (name) + 1;
13502         (*info->fprintf_func) (info->stream, "%s ", name);
13503       }
13504
13505   /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
13506      unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
13507      used by putop and MMX/SSE operand and may be overriden by the
13508      PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
13509      separately.  */
13510   if (dp->prefix_requirement == PREFIX_OPCODE
13511       && dp != &bad_opcode
13512       && (((prefixes
13513             & (PREFIX_REPZ | PREFIX_REPNZ)) != 0
13514            && (used_prefixes
13515                & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
13516           || ((((prefixes
13517                  & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
13518                 == PREFIX_DATA)
13519                && (used_prefixes & PREFIX_DATA) == 0))))
13520     {
13521       (*info->fprintf_func) (info->stream, "(bad)");
13522       return end_codep - priv.the_buffer;
13523     }
13524
13525   /* Check maximum code length.  */
13526   if ((codep - start_codep) > MAX_CODE_LENGTH)
13527     {
13528       (*info->fprintf_func) (info->stream, "(bad)");
13529       return MAX_CODE_LENGTH;
13530     }
13531
13532   obufp = mnemonicendp;
13533   for (i = strlen (obuf) + prefix_length; i < 6; i++)
13534     oappend (" ");
13535   oappend (" ");
13536   (*info->fprintf_func) (info->stream, "%s", obuf);
13537
13538   /* The enter and bound instructions are printed with operands in the same
13539      order as the intel book; everything else is printed in reverse order.  */
13540   if (intel_syntax || two_source_ops)
13541     {
13542       bfd_vma riprel;
13543
13544       for (i = 0; i < MAX_OPERANDS; ++i)
13545         op_txt[i] = op_out[i];
13546
13547       if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
13548           && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
13549         {
13550           op_txt[2] = op_out[3];
13551           op_txt[3] = op_out[2];
13552         }
13553
13554       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
13555         {
13556           op_ad = op_index[i];
13557           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
13558           op_index[MAX_OPERANDS - 1 - i] = op_ad;
13559           riprel = op_riprel[i];
13560           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
13561           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
13562         }
13563     }
13564   else
13565     {
13566       for (i = 0; i < MAX_OPERANDS; ++i)
13567         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
13568     }
13569
13570   needcomma = 0;
13571   for (i = 0; i < MAX_OPERANDS; ++i)
13572     if (*op_txt[i])
13573       {
13574         if (needcomma)
13575           (*info->fprintf_func) (info->stream, ",");
13576         if (op_index[i] != -1 && !op_riprel[i])
13577           (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
13578         else
13579           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
13580         needcomma = 1;
13581       }
13582
13583   for (i = 0; i < MAX_OPERANDS; i++)
13584     if (op_index[i] != -1 && op_riprel[i])
13585       {
13586         (*info->fprintf_func) (info->stream, "        # ");
13587         (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
13588                                                 + op_address[op_index[i]]), info);
13589         break;
13590       }
13591   return codep - priv.the_buffer;
13592 }
13593
13594 static const char *float_mem[] = {
13595   /* d8 */
13596   "fadd{s|}",
13597   "fmul{s|}",
13598   "fcom{s|}",
13599   "fcomp{s|}",
13600   "fsub{s|}",
13601   "fsubr{s|}",
13602   "fdiv{s|}",
13603   "fdivr{s|}",
13604   /* d9 */
13605   "fld{s|}",
13606   "(bad)",
13607   "fst{s|}",
13608   "fstp{s|}",
13609   "fldenvIC",
13610   "fldcw",
13611   "fNstenvIC",
13612   "fNstcw",
13613   /* da */
13614   "fiadd{l|}",
13615   "fimul{l|}",
13616   "ficom{l|}",
13617   "ficomp{l|}",
13618   "fisub{l|}",
13619   "fisubr{l|}",
13620   "fidiv{l|}",
13621   "fidivr{l|}",
13622   /* db */
13623   "fild{l|}",
13624   "fisttp{l|}",
13625   "fist{l|}",
13626   "fistp{l|}",
13627   "(bad)",
13628   "fld{t||t|}",
13629   "(bad)",
13630   "fstp{t||t|}",
13631   /* dc */
13632   "fadd{l|}",
13633   "fmul{l|}",
13634   "fcom{l|}",
13635   "fcomp{l|}",
13636   "fsub{l|}",
13637   "fsubr{l|}",
13638   "fdiv{l|}",
13639   "fdivr{l|}",
13640   /* dd */
13641   "fld{l|}",
13642   "fisttp{ll|}",
13643   "fst{l||}",
13644   "fstp{l|}",
13645   "frstorIC",
13646   "(bad)",
13647   "fNsaveIC",
13648   "fNstsw",
13649   /* de */
13650   "fiadd{s|}",
13651   "fimul{s|}",
13652   "ficom{s|}",
13653   "ficomp{s|}",
13654   "fisub{s|}",
13655   "fisubr{s|}",
13656   "fidiv{s|}",
13657   "fidivr{s|}",
13658   /* df */
13659   "fild{s|}",
13660   "fisttp{s|}",
13661   "fist{s|}",
13662   "fistp{s|}",
13663   "fbld",
13664   "fild{ll|}",
13665   "fbstp",
13666   "fistp{ll|}",
13667 };
13668
13669 static const unsigned char float_mem_mode[] = {
13670   /* d8 */
13671   d_mode,
13672   d_mode,
13673   d_mode,
13674   d_mode,
13675   d_mode,
13676   d_mode,
13677   d_mode,
13678   d_mode,
13679   /* d9 */
13680   d_mode,
13681   0,
13682   d_mode,
13683   d_mode,
13684   0,
13685   w_mode,
13686   0,
13687   w_mode,
13688   /* da */
13689   d_mode,
13690   d_mode,
13691   d_mode,
13692   d_mode,
13693   d_mode,
13694   d_mode,
13695   d_mode,
13696   d_mode,
13697   /* db */
13698   d_mode,
13699   d_mode,
13700   d_mode,
13701   d_mode,
13702   0,
13703   t_mode,
13704   0,
13705   t_mode,
13706   /* dc */
13707   q_mode,
13708   q_mode,
13709   q_mode,
13710   q_mode,
13711   q_mode,
13712   q_mode,
13713   q_mode,
13714   q_mode,
13715   /* dd */
13716   q_mode,
13717   q_mode,
13718   q_mode,
13719   q_mode,
13720   0,
13721   0,
13722   0,
13723   w_mode,
13724   /* de */
13725   w_mode,
13726   w_mode,
13727   w_mode,
13728   w_mode,
13729   w_mode,
13730   w_mode,
13731   w_mode,
13732   w_mode,
13733   /* df */
13734   w_mode,
13735   w_mode,
13736   w_mode,
13737   w_mode,
13738   t_mode,
13739   q_mode,
13740   t_mode,
13741   q_mode
13742 };
13743
13744 #define ST { OP_ST, 0 }
13745 #define STi { OP_STi, 0 }
13746
13747 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
13748 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
13749 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
13750 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
13751 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
13752 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
13753 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
13754 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
13755 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
13756
13757 static const struct dis386 float_reg[][8] = {
13758   /* d8 */
13759   {
13760     { "fadd",   { ST, STi }, 0 },
13761     { "fmul",   { ST, STi }, 0 },
13762     { "fcom",   { STi }, 0 },
13763     { "fcomp",  { STi }, 0 },
13764     { "fsub",   { ST, STi }, 0 },
13765     { "fsubr",  { ST, STi }, 0 },
13766     { "fdiv",   { ST, STi }, 0 },
13767     { "fdivr",  { ST, STi }, 0 },
13768   },
13769   /* d9 */
13770   {
13771     { "fld",    { STi }, 0 },
13772     { "fxch",   { STi }, 0 },
13773     { FGRPd9_2 },
13774     { Bad_Opcode },
13775     { FGRPd9_4 },
13776     { FGRPd9_5 },
13777     { FGRPd9_6 },
13778     { FGRPd9_7 },
13779   },
13780   /* da */
13781   {
13782     { "fcmovb", { ST, STi }, 0 },
13783     { "fcmove", { ST, STi }, 0 },
13784     { "fcmovbe",{ ST, STi }, 0 },
13785     { "fcmovu", { ST, STi }, 0 },
13786     { Bad_Opcode },
13787     { FGRPda_5 },
13788     { Bad_Opcode },
13789     { Bad_Opcode },
13790   },
13791   /* db */
13792   {
13793     { "fcmovnb",{ ST, STi }, 0 },
13794     { "fcmovne",{ ST, STi }, 0 },
13795     { "fcmovnbe",{ ST, STi }, 0 },
13796     { "fcmovnu",{ ST, STi }, 0 },
13797     { FGRPdb_4 },
13798     { "fucomi", { ST, STi }, 0 },
13799     { "fcomi",  { ST, STi }, 0 },
13800     { Bad_Opcode },
13801   },
13802   /* dc */
13803   {
13804     { "fadd",   { STi, ST }, 0 },
13805     { "fmul",   { STi, ST }, 0 },
13806     { Bad_Opcode },
13807     { Bad_Opcode },
13808     { "fsub{!M|r}",     { STi, ST }, 0 },
13809     { "fsub{M|}",       { STi, ST }, 0 },
13810     { "fdiv{!M|r}",     { STi, ST }, 0 },
13811     { "fdiv{M|}",       { STi, ST }, 0 },
13812   },
13813   /* dd */
13814   {
13815     { "ffree",  { STi }, 0 },
13816     { Bad_Opcode },
13817     { "fst",    { STi }, 0 },
13818     { "fstp",   { STi }, 0 },
13819     { "fucom",  { STi }, 0 },
13820     { "fucomp", { STi }, 0 },
13821     { Bad_Opcode },
13822     { Bad_Opcode },
13823   },
13824   /* de */
13825   {
13826     { "faddp",  { STi, ST }, 0 },
13827     { "fmulp",  { STi, ST }, 0 },
13828     { Bad_Opcode },
13829     { FGRPde_3 },
13830     { "fsub{!M|r}p",    { STi, ST }, 0 },
13831     { "fsub{M|}p",      { STi, ST }, 0 },
13832     { "fdiv{!M|r}p",    { STi, ST }, 0 },
13833     { "fdiv{M|}p",      { STi, ST }, 0 },
13834   },
13835   /* df */
13836   {
13837     { "ffreep", { STi }, 0 },
13838     { Bad_Opcode },
13839     { Bad_Opcode },
13840     { Bad_Opcode },
13841     { FGRPdf_4 },
13842     { "fucomip", { ST, STi }, 0 },
13843     { "fcomip", { ST, STi }, 0 },
13844     { Bad_Opcode },
13845   },
13846 };
13847
13848 static char *fgrps[][8] = {
13849   /* Bad opcode 0 */
13850   {
13851     "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13852   },
13853
13854   /* d9_2  1 */
13855   {
13856     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13857   },
13858
13859   /* d9_4  2 */
13860   {
13861     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
13862   },
13863
13864   /* d9_5  3 */
13865   {
13866     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
13867   },
13868
13869   /* d9_6  4 */
13870   {
13871     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
13872   },
13873
13874   /* d9_7  5 */
13875   {
13876     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
13877   },
13878
13879   /* da_5  6 */
13880   {
13881     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13882   },
13883
13884   /* db_4  7 */
13885   {
13886     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
13887     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
13888   },
13889
13890   /* de_3  8 */
13891   {
13892     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13893   },
13894
13895   /* df_4  9 */
13896   {
13897     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13898   },
13899 };
13900
13901 static void
13902 swap_operand (void)
13903 {
13904   mnemonicendp[0] = '.';
13905   mnemonicendp[1] = 's';
13906   mnemonicendp += 2;
13907 }
13908
13909 static void
13910 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
13911                int sizeflag ATTRIBUTE_UNUSED)
13912 {
13913   /* Skip mod/rm byte.  */
13914   MODRM_CHECK;
13915   codep++;
13916 }
13917
13918 static void
13919 dofloat (int sizeflag)
13920 {
13921   const struct dis386 *dp;
13922   unsigned char floatop;
13923
13924   floatop = codep[-1];
13925
13926   if (modrm.mod != 3)
13927     {
13928       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
13929
13930       putop (float_mem[fp_indx], sizeflag);
13931       obufp = op_out[0];
13932       op_ad = 2;
13933       OP_E (float_mem_mode[fp_indx], sizeflag);
13934       return;
13935     }
13936   /* Skip mod/rm byte.  */
13937   MODRM_CHECK;
13938   codep++;
13939
13940   dp = &float_reg[floatop - 0xd8][modrm.reg];
13941   if (dp->name == NULL)
13942     {
13943       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
13944
13945       /* Instruction fnstsw is only one with strange arg.  */
13946       if (floatop == 0xdf && codep[-1] == 0xe0)
13947         strcpy (op_out[0], names16[0]);
13948     }
13949   else
13950     {
13951       putop (dp->name, sizeflag);
13952
13953       obufp = op_out[0];
13954       op_ad = 2;
13955       if (dp->op[0].rtn)
13956         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
13957
13958       obufp = op_out[1];
13959       op_ad = 1;
13960       if (dp->op[1].rtn)
13961         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
13962     }
13963 }
13964
13965 /* Like oappend (below), but S is a string starting with '%'.
13966    In Intel syntax, the '%' is elided.  */
13967 static void
13968 oappend_maybe_intel (const char *s)
13969 {
13970   oappend (s + intel_syntax);
13971 }
13972
13973 static void
13974 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13975 {
13976   oappend_maybe_intel ("%st");
13977 }
13978
13979 static void
13980 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13981 {
13982   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
13983   oappend_maybe_intel (scratchbuf);
13984 }
13985
13986 /* Capital letters in template are macros.  */
13987 static int
13988 putop (const char *in_template, int sizeflag)
13989 {
13990   const char *p;
13991   int alt = 0;
13992   int cond = 1;
13993   unsigned int l = 0, len = 1;
13994   char last[4];
13995
13996 #define SAVE_LAST(c)                    \
13997   if (l < len && l < sizeof (last))     \
13998     last[l++] = c;                      \
13999   else                                  \
14000     abort ();
14001
14002   for (p = in_template; *p; p++)
14003     {
14004       switch (*p)
14005         {
14006         default:
14007           *obufp++ = *p;
14008           break;
14009         case '%':
14010           len++;
14011           break;
14012         case '!':
14013           cond = 0;
14014           break;
14015         case '{':
14016           if (intel_syntax)
14017             {
14018               while (*++p != '|')
14019                 if (*p == '}' || *p == '\0')
14020                   abort ();
14021             }
14022           /* Fall through.  */
14023         case 'I':
14024           alt = 1;
14025           continue;
14026         case '|':
14027           while (*++p != '}')
14028             {
14029               if (*p == '\0')
14030                 abort ();
14031             }
14032           break;
14033         case '}':
14034           break;
14035         case 'A':
14036           if (intel_syntax)
14037             break;
14038           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
14039             *obufp++ = 'b';
14040           break;
14041         case 'B':
14042           if (l == 0 && len == 1)
14043             {
14044 case_B:
14045               if (intel_syntax)
14046                 break;
14047               if (sizeflag & SUFFIX_ALWAYS)
14048                 *obufp++ = 'b';
14049             }
14050           else
14051             {
14052               if (l != 1
14053                   || len != 2
14054                   || last[0] != 'L')
14055                 {
14056                   SAVE_LAST (*p);
14057                   break;
14058                 }
14059
14060               if (address_mode == mode_64bit
14061                   && !(prefixes & PREFIX_ADDR))
14062                 {
14063                   *obufp++ = 'a';
14064                   *obufp++ = 'b';
14065                   *obufp++ = 's';
14066                 }
14067
14068               goto case_B;
14069             }
14070           break;
14071         case 'C':
14072           if (intel_syntax && !alt)
14073             break;
14074           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
14075             {
14076               if (sizeflag & DFLAG)
14077                 *obufp++ = intel_syntax ? 'd' : 'l';
14078               else
14079                 *obufp++ = intel_syntax ? 'w' : 's';
14080               used_prefixes |= (prefixes & PREFIX_DATA);
14081             }
14082           break;
14083         case 'D':
14084           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
14085             break;
14086           USED_REX (REX_W);
14087           if (modrm.mod == 3)
14088             {
14089               if (rex & REX_W)
14090                 *obufp++ = 'q';
14091               else
14092                 {
14093                   if (sizeflag & DFLAG)
14094                     *obufp++ = intel_syntax ? 'd' : 'l';
14095                   else
14096                     *obufp++ = 'w';
14097                   used_prefixes |= (prefixes & PREFIX_DATA);
14098                 }
14099             }
14100           else
14101             *obufp++ = 'w';
14102           break;
14103         case 'E':               /* For jcxz/jecxz */
14104           if (address_mode == mode_64bit)
14105             {
14106               if (sizeflag & AFLAG)
14107                 *obufp++ = 'r';
14108               else
14109                 *obufp++ = 'e';
14110             }
14111           else
14112             if (sizeflag & AFLAG)
14113               *obufp++ = 'e';
14114           used_prefixes |= (prefixes & PREFIX_ADDR);
14115           break;
14116         case 'F':
14117           if (intel_syntax)
14118             break;
14119           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
14120             {
14121               if (sizeflag & AFLAG)
14122                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
14123               else
14124                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
14125               used_prefixes |= (prefixes & PREFIX_ADDR);
14126             }
14127           break;
14128         case 'G':
14129           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
14130             break;
14131           if ((rex & REX_W) || (sizeflag & DFLAG))
14132             *obufp++ = 'l';
14133           else
14134             *obufp++ = 'w';
14135           if (!(rex & REX_W))
14136             used_prefixes |= (prefixes & PREFIX_DATA);
14137           break;
14138         case 'H':
14139           if (intel_syntax)
14140             break;
14141           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
14142               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
14143             {
14144               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
14145               *obufp++ = ',';
14146               *obufp++ = 'p';
14147               if (prefixes & PREFIX_DS)
14148                 *obufp++ = 't';
14149               else
14150                 *obufp++ = 'n';
14151             }
14152           break;
14153         case 'J':
14154           if (intel_syntax)
14155             break;
14156           *obufp++ = 'l';
14157           break;
14158         case 'K':
14159           USED_REX (REX_W);
14160           if (rex & REX_W)
14161             *obufp++ = 'q';
14162           else
14163             *obufp++ = 'd';
14164           break;
14165         case 'Z':
14166           if (l != 0 || len != 1)
14167             {
14168               if (l != 1 || len != 2 || last[0] != 'X')
14169                 {
14170                   SAVE_LAST (*p);
14171                   break;
14172                 }
14173               if (!need_vex || !vex.evex)
14174                 abort ();
14175               if (intel_syntax
14176                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
14177                 break;
14178               switch (vex.length)
14179                 {
14180                 case 128:
14181                   *obufp++ = 'x';
14182                   break;
14183                 case 256:
14184                   *obufp++ = 'y';
14185                   break;
14186                 case 512:
14187                   *obufp++ = 'z';
14188                   break;
14189                 default:
14190                   abort ();
14191                 }
14192               break;
14193             }
14194           if (intel_syntax)
14195             break;
14196           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
14197             {
14198               *obufp++ = 'q';
14199               break;
14200             }
14201           /* Fall through.  */
14202           goto case_L;
14203         case 'L':
14204           if (l != 0 || len != 1)
14205             {
14206               SAVE_LAST (*p);
14207               break;
14208             }
14209 case_L:
14210           if (intel_syntax)
14211             break;
14212           if (sizeflag & SUFFIX_ALWAYS)
14213             *obufp++ = 'l';
14214           break;
14215         case 'M':
14216           if (intel_mnemonic != cond)
14217             *obufp++ = 'r';
14218           break;
14219         case 'N':
14220           if ((prefixes & PREFIX_FWAIT) == 0)
14221             *obufp++ = 'n';
14222           else
14223             used_prefixes |= PREFIX_FWAIT;
14224           break;
14225         case 'O':
14226           USED_REX (REX_W);
14227           if (rex & REX_W)
14228             *obufp++ = 'o';
14229           else if (intel_syntax && (sizeflag & DFLAG))
14230             *obufp++ = 'q';
14231           else
14232             *obufp++ = 'd';
14233           if (!(rex & REX_W))
14234             used_prefixes |= (prefixes & PREFIX_DATA);
14235           break;
14236         case '&':
14237           if (!intel_syntax
14238               && address_mode == mode_64bit
14239               && isa64 == intel64)
14240             {
14241               *obufp++ = 'q';
14242               break;
14243             }
14244           /* Fall through.  */
14245         case 'T':
14246           if (!intel_syntax
14247               && address_mode == mode_64bit
14248               && ((sizeflag & DFLAG) || (rex & REX_W)))
14249             {
14250               *obufp++ = 'q';
14251               break;
14252             }
14253           /* Fall through.  */
14254           goto case_P;
14255         case 'P':
14256           if (l == 0 && len == 1)
14257             {
14258 case_P:
14259               if (intel_syntax)
14260                 {
14261                   if ((rex & REX_W) == 0
14262                       && (prefixes & PREFIX_DATA))
14263                     {
14264                       if ((sizeflag & DFLAG) == 0)
14265                         *obufp++ = 'w';
14266                       used_prefixes |= (prefixes & PREFIX_DATA);
14267                     }
14268                   break;
14269                 }
14270               if ((prefixes & PREFIX_DATA)
14271                   || (rex & REX_W)
14272                   || (sizeflag & SUFFIX_ALWAYS))
14273                 {
14274                   USED_REX (REX_W);
14275                   if (rex & REX_W)
14276                     *obufp++ = 'q';
14277                   else
14278                     {
14279                       if (sizeflag & DFLAG)
14280                         *obufp++ = 'l';
14281                       else
14282                         *obufp++ = 'w';
14283                       used_prefixes |= (prefixes & PREFIX_DATA);
14284                     }
14285                 }
14286             }
14287           else
14288             {
14289               if (l != 1 || len != 2 || last[0] != 'L')
14290                 {
14291                   SAVE_LAST (*p);
14292                   break;
14293                 }
14294
14295               if ((prefixes & PREFIX_DATA)
14296                   || (rex & REX_W)
14297                   || (sizeflag & SUFFIX_ALWAYS))
14298                 {
14299                   USED_REX (REX_W);
14300                   if (rex & REX_W)
14301                     *obufp++ = 'q';
14302                   else
14303                     {
14304                       if (sizeflag & DFLAG)
14305                         *obufp++ = intel_syntax ? 'd' : 'l';
14306                       else
14307                         *obufp++ = 'w';
14308                       used_prefixes |= (prefixes & PREFIX_DATA);
14309                     }
14310                 }
14311             }
14312           break;
14313         case 'U':
14314           if (intel_syntax)
14315             break;
14316           if (address_mode == mode_64bit
14317               && ((sizeflag & DFLAG) || (rex & REX_W)))
14318             {
14319               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
14320                 *obufp++ = 'q';
14321               break;
14322             }
14323           /* Fall through.  */
14324           goto case_Q;
14325         case 'Q':
14326           if (l == 0 && len == 1)
14327             {
14328 case_Q:
14329               if (intel_syntax && !alt)
14330                 break;
14331               USED_REX (REX_W);
14332               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
14333                 {
14334                   if (rex & REX_W)
14335                     *obufp++ = 'q';
14336                   else
14337                     {
14338                       if (sizeflag & DFLAG)
14339                         *obufp++ = intel_syntax ? 'd' : 'l';
14340                       else
14341                         *obufp++ = 'w';
14342                       used_prefixes |= (prefixes & PREFIX_DATA);
14343                     }
14344                 }
14345             }
14346           else
14347             {
14348               if (l != 1 || len != 2 || last[0] != 'L')
14349                 {
14350                   SAVE_LAST (*p);
14351                   break;
14352                 }
14353               if (intel_syntax
14354                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
14355                 break;
14356               if ((rex & REX_W))
14357                 {
14358                   USED_REX (REX_W);
14359                   *obufp++ = 'q';
14360                 }
14361               else
14362                 *obufp++ = 'l';
14363             }
14364           break;
14365         case 'R':
14366           USED_REX (REX_W);
14367           if (rex & REX_W)
14368             *obufp++ = 'q';
14369           else if (sizeflag & DFLAG)
14370             {
14371               if (intel_syntax)
14372                   *obufp++ = 'd';
14373               else
14374                   *obufp++ = 'l';
14375             }
14376           else
14377             *obufp++ = 'w';
14378           if (intel_syntax && !p[1]
14379               && ((rex & REX_W) || (sizeflag & DFLAG)))
14380             *obufp++ = 'e';
14381           if (!(rex & REX_W))
14382             used_prefixes |= (prefixes & PREFIX_DATA);
14383           break;
14384         case 'V':
14385           if (l == 0 && len == 1)
14386             {
14387               if (intel_syntax)
14388                 break;
14389               if (address_mode == mode_64bit
14390                   && ((sizeflag & DFLAG) || (rex & REX_W)))
14391                 {
14392                   if (sizeflag & SUFFIX_ALWAYS)
14393                     *obufp++ = 'q';
14394                   break;
14395                 }
14396             }
14397           else
14398             {
14399               if (l != 1
14400                   || len != 2
14401                   || last[0] != 'L')
14402                 {
14403                   SAVE_LAST (*p);
14404                   break;
14405                 }
14406
14407               if (rex & REX_W)
14408                 {
14409                   *obufp++ = 'a';
14410                   *obufp++ = 'b';
14411                   *obufp++ = 's';
14412                 }
14413             }
14414           /* Fall through.  */
14415           goto case_S;
14416         case 'S':
14417           if (l == 0 && len == 1)
14418             {
14419 case_S:
14420               if (intel_syntax)
14421                 break;
14422               if (sizeflag & SUFFIX_ALWAYS)
14423                 {
14424                   if (rex & REX_W)
14425                     *obufp++ = 'q';
14426                   else
14427                     {
14428                       if (sizeflag & DFLAG)
14429                         *obufp++ = 'l';
14430                       else
14431                         *obufp++ = 'w';
14432                       used_prefixes |= (prefixes & PREFIX_DATA);
14433                     }
14434                 }
14435             }
14436           else
14437             {
14438               if (l != 1
14439                   || len != 2
14440                   || last[0] != 'L')
14441                 {
14442                   SAVE_LAST (*p);
14443                   break;
14444                 }
14445
14446               if (address_mode == mode_64bit
14447                   && !(prefixes & PREFIX_ADDR))
14448                 {
14449                   *obufp++ = 'a';
14450                   *obufp++ = 'b';
14451                   *obufp++ = 's';
14452                 }
14453
14454               goto case_S;
14455             }
14456           break;
14457         case 'X':
14458           if (l != 0 || len != 1)
14459             {
14460               SAVE_LAST (*p);
14461               break;
14462             }
14463           if (need_vex && vex.prefix)
14464             {
14465               if (vex.prefix == DATA_PREFIX_OPCODE)
14466                 *obufp++ = 'd';
14467               else
14468                 *obufp++ = 's';
14469             }
14470           else
14471             {
14472               if (prefixes & PREFIX_DATA)
14473                 *obufp++ = 'd';
14474               else
14475                 *obufp++ = 's';
14476               used_prefixes |= (prefixes & PREFIX_DATA);
14477             }
14478           break;
14479         case 'Y':
14480           if (l == 0 && len == 1)
14481             abort ();
14482           else
14483             {
14484               if (l != 1 || len != 2 || last[0] != 'X')
14485                 {
14486                   SAVE_LAST (*p);
14487                   break;
14488                 }
14489               if (!need_vex)
14490                 abort ();
14491               if (intel_syntax
14492                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
14493                 break;
14494               switch (vex.length)
14495                 {
14496                 case 128:
14497                   *obufp++ = 'x';
14498                   break;
14499                 case 256:
14500                   *obufp++ = 'y';
14501                   break;
14502                 case 512:
14503                   if (!vex.evex)
14504                 default:
14505                     abort ();
14506                 }
14507             }
14508           break;
14509         case 'W':
14510           if (l == 0 && len == 1)
14511             {
14512               /* operand size flag for cwtl, cbtw */
14513               USED_REX (REX_W);
14514               if (rex & REX_W)
14515                 {
14516                   if (intel_syntax)
14517                     *obufp++ = 'd';
14518                   else
14519                     *obufp++ = 'l';
14520                 }
14521               else if (sizeflag & DFLAG)
14522                 *obufp++ = 'w';
14523               else
14524                 *obufp++ = 'b';
14525               if (!(rex & REX_W))
14526                 used_prefixes |= (prefixes & PREFIX_DATA);
14527             }
14528           else
14529             {
14530               if (l != 1
14531                   || len != 2
14532                   || (last[0] != 'X'
14533                       && last[0] != 'L'))
14534                 {
14535                   SAVE_LAST (*p);
14536                   break;
14537                 }
14538               if (!need_vex)
14539                 abort ();
14540               if (last[0] == 'X')
14541                 *obufp++ = vex.w ? 'd': 's';
14542               else
14543                 *obufp++ = vex.w ? 'q': 'd';
14544             }
14545           break;
14546         case '^':
14547           if (intel_syntax)
14548             break;
14549           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
14550             {
14551               if (sizeflag & DFLAG)
14552                 *obufp++ = 'l';
14553               else
14554                 *obufp++ = 'w';
14555               used_prefixes |= (prefixes & PREFIX_DATA);
14556             }
14557           break;
14558         case '@':
14559           if (intel_syntax)
14560             break;
14561           if (address_mode == mode_64bit
14562               && (isa64 == intel64
14563                   || ((sizeflag & DFLAG) || (rex & REX_W))))
14564               *obufp++ = 'q';
14565           else if ((prefixes & PREFIX_DATA))
14566             {
14567               if (!(sizeflag & DFLAG))
14568                 *obufp++ = 'w';
14569               used_prefixes |= (prefixes & PREFIX_DATA);
14570             }
14571           break;
14572         }
14573       alt = 0;
14574     }
14575   *obufp = 0;
14576   mnemonicendp = obufp;
14577   return 0;
14578 }
14579
14580 static void
14581 oappend (const char *s)
14582 {
14583   obufp = stpcpy (obufp, s);
14584 }
14585
14586 static void
14587 append_seg (void)
14588 {
14589   /* Only print the active segment register.  */
14590   if (!active_seg_prefix)
14591     return;
14592
14593   used_prefixes |= active_seg_prefix;
14594   switch (active_seg_prefix)
14595     {
14596     case PREFIX_CS:
14597       oappend_maybe_intel ("%cs:");
14598       break;
14599     case PREFIX_DS:
14600       oappend_maybe_intel ("%ds:");
14601       break;
14602     case PREFIX_SS:
14603       oappend_maybe_intel ("%ss:");
14604       break;
14605     case PREFIX_ES:
14606       oappend_maybe_intel ("%es:");
14607       break;
14608     case PREFIX_FS:
14609       oappend_maybe_intel ("%fs:");
14610       break;
14611     case PREFIX_GS:
14612       oappend_maybe_intel ("%gs:");
14613       break;
14614     default:
14615       break;
14616     }
14617 }
14618
14619 static void
14620 OP_indirE (int bytemode, int sizeflag)
14621 {
14622   if (!intel_syntax)
14623     oappend ("*");
14624   OP_E (bytemode, sizeflag);
14625 }
14626
14627 static void
14628 print_operand_value (char *buf, int hex, bfd_vma disp)
14629 {
14630   if (address_mode == mode_64bit)
14631     {
14632       if (hex)
14633         {
14634           char tmp[30];
14635           int i;
14636           buf[0] = '0';
14637           buf[1] = 'x';
14638           sprintf_vma (tmp, disp);
14639           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
14640           strcpy (buf + 2, tmp + i);
14641         }
14642       else
14643         {
14644           bfd_signed_vma v = disp;
14645           char tmp[30];
14646           int i;
14647           if (v < 0)
14648             {
14649               *(buf++) = '-';
14650               v = -disp;
14651               /* Check for possible overflow on 0x8000000000000000.  */
14652               if (v < 0)
14653                 {
14654                   strcpy (buf, "9223372036854775808");
14655                   return;
14656                 }
14657             }
14658           if (!v)
14659             {
14660               strcpy (buf, "0");
14661               return;
14662             }
14663
14664           i = 0;
14665           tmp[29] = 0;
14666           while (v)
14667             {
14668               tmp[28 - i] = (v % 10) + '0';
14669               v /= 10;
14670               i++;
14671             }
14672           strcpy (buf, tmp + 29 - i);
14673         }
14674     }
14675   else
14676     {
14677       if (hex)
14678         sprintf (buf, "0x%x", (unsigned int) disp);
14679       else
14680         sprintf (buf, "%d", (int) disp);
14681     }
14682 }
14683
14684 /* Put DISP in BUF as signed hex number.  */
14685
14686 static void
14687 print_displacement (char *buf, bfd_vma disp)
14688 {
14689   bfd_signed_vma val = disp;
14690   char tmp[30];
14691   int i, j = 0;
14692
14693   if (val < 0)
14694     {
14695       buf[j++] = '-';
14696       val = -disp;
14697
14698       /* Check for possible overflow.  */
14699       if (val < 0)
14700         {
14701           switch (address_mode)
14702             {
14703             case mode_64bit:
14704               strcpy (buf + j, "0x8000000000000000");
14705               break;
14706             case mode_32bit:
14707               strcpy (buf + j, "0x80000000");
14708               break;
14709             case mode_16bit:
14710               strcpy (buf + j, "0x8000");
14711               break;
14712             }
14713           return;
14714         }
14715     }
14716
14717   buf[j++] = '0';
14718   buf[j++] = 'x';
14719
14720   sprintf_vma (tmp, (bfd_vma) val);
14721   for (i = 0; tmp[i] == '0'; i++)
14722     continue;
14723   if (tmp[i] == '\0')
14724     i--;
14725   strcpy (buf + j, tmp + i);
14726 }
14727
14728 static void
14729 intel_operand_size (int bytemode, int sizeflag)
14730 {
14731   if (vex.evex
14732       && vex.b
14733       && (bytemode == x_mode
14734           || bytemode == evex_half_bcst_xmmq_mode))
14735     {
14736       if (vex.w)
14737         oappend ("QWORD PTR ");
14738       else
14739         oappend ("DWORD PTR ");
14740       return;
14741     }
14742   switch (bytemode)
14743     {
14744     case b_mode:
14745     case b_swap_mode:
14746     case dqb_mode:
14747     case db_mode:
14748       oappend ("BYTE PTR ");
14749       break;
14750     case w_mode:
14751     case dw_mode:
14752     case dqw_mode:
14753       oappend ("WORD PTR ");
14754       break;
14755     case indir_v_mode:
14756       if (address_mode == mode_64bit && isa64 == intel64)
14757         {
14758           oappend ("QWORD PTR ");
14759           break;
14760         }
14761       /* Fall through.  */
14762     case stack_v_mode:
14763       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14764         {
14765           oappend ("QWORD PTR ");
14766           break;
14767         }
14768       /* Fall through.  */
14769     case v_mode:
14770     case v_swap_mode:
14771     case dq_mode:
14772       USED_REX (REX_W);
14773       if (rex & REX_W)
14774         oappend ("QWORD PTR ");
14775       else
14776         {
14777           if ((sizeflag & DFLAG) || bytemode == dq_mode)
14778             oappend ("DWORD PTR ");
14779           else
14780             oappend ("WORD PTR ");
14781           used_prefixes |= (prefixes & PREFIX_DATA);
14782         }
14783       break;
14784     case z_mode:
14785       if ((rex & REX_W) || (sizeflag & DFLAG))
14786         *obufp++ = 'D';
14787       oappend ("WORD PTR ");
14788       if (!(rex & REX_W))
14789         used_prefixes |= (prefixes & PREFIX_DATA);
14790       break;
14791     case a_mode:
14792       if (sizeflag & DFLAG)
14793         oappend ("QWORD PTR ");
14794       else
14795         oappend ("DWORD PTR ");
14796       used_prefixes |= (prefixes & PREFIX_DATA);
14797       break;
14798     case d_mode:
14799     case d_scalar_mode:
14800     case d_scalar_swap_mode:
14801     case d_swap_mode:
14802     case dqd_mode:
14803       oappend ("DWORD PTR ");
14804       break;
14805     case q_mode:
14806     case q_scalar_mode:
14807     case q_scalar_swap_mode:
14808     case q_swap_mode:
14809       oappend ("QWORD PTR ");
14810       break;
14811     case dqa_mode:
14812     case m_mode:
14813       if (address_mode == mode_64bit)
14814         oappend ("QWORD PTR ");
14815       else
14816         oappend ("DWORD PTR ");
14817       break;
14818     case f_mode:
14819       if (sizeflag & DFLAG)
14820         oappend ("FWORD PTR ");
14821       else
14822         oappend ("DWORD PTR ");
14823       used_prefixes |= (prefixes & PREFIX_DATA);
14824       break;
14825     case t_mode:
14826       oappend ("TBYTE PTR ");
14827       break;
14828     case x_mode:
14829     case x_swap_mode:
14830     case evex_x_gscat_mode:
14831     case evex_x_nobcst_mode:
14832     case b_scalar_mode:
14833     case w_scalar_mode:
14834       if (need_vex)
14835         {
14836           switch (vex.length)
14837             {
14838             case 128:
14839               oappend ("XMMWORD PTR ");
14840               break;
14841             case 256:
14842               oappend ("YMMWORD PTR ");
14843               break;
14844             case 512:
14845               oappend ("ZMMWORD PTR ");
14846               break;
14847             default:
14848               abort ();
14849             }
14850         }
14851       else
14852         oappend ("XMMWORD PTR ");
14853       break;
14854     case xmm_mode:
14855       oappend ("XMMWORD PTR ");
14856       break;
14857     case ymm_mode:
14858       oappend ("YMMWORD PTR ");
14859       break;
14860     case xmmq_mode:
14861     case evex_half_bcst_xmmq_mode:
14862       if (!need_vex)
14863         abort ();
14864
14865       switch (vex.length)
14866         {
14867         case 128:
14868           oappend ("QWORD PTR ");
14869           break;
14870         case 256:
14871           oappend ("XMMWORD PTR ");
14872           break;
14873         case 512:
14874           oappend ("YMMWORD PTR ");
14875           break;
14876         default:
14877           abort ();
14878         }
14879       break;
14880     case xmm_mb_mode:
14881       if (!need_vex)
14882         abort ();
14883
14884       switch (vex.length)
14885         {
14886         case 128:
14887         case 256:
14888         case 512:
14889           oappend ("BYTE PTR ");
14890           break;
14891         default:
14892           abort ();
14893         }
14894       break;
14895     case xmm_mw_mode:
14896       if (!need_vex)
14897         abort ();
14898
14899       switch (vex.length)
14900         {
14901         case 128:
14902         case 256:
14903         case 512:
14904           oappend ("WORD PTR ");
14905           break;
14906         default:
14907           abort ();
14908         }
14909       break;
14910     case xmm_md_mode:
14911       if (!need_vex)
14912         abort ();
14913
14914       switch (vex.length)
14915         {
14916         case 128:
14917         case 256:
14918         case 512:
14919           oappend ("DWORD PTR ");
14920           break;
14921         default:
14922           abort ();
14923         }
14924       break;
14925     case xmm_mq_mode:
14926       if (!need_vex)
14927         abort ();
14928
14929       switch (vex.length)
14930         {
14931         case 128:
14932         case 256:
14933         case 512:
14934           oappend ("QWORD PTR ");
14935           break;
14936         default:
14937           abort ();
14938         }
14939       break;
14940     case xmmdw_mode:
14941       if (!need_vex)
14942         abort ();
14943
14944       switch (vex.length)
14945         {
14946         case 128:
14947           oappend ("WORD PTR ");
14948           break;
14949         case 256:
14950           oappend ("DWORD PTR ");
14951           break;
14952         case 512:
14953           oappend ("QWORD PTR ");
14954           break;
14955         default:
14956           abort ();
14957         }
14958       break;
14959     case xmmqd_mode:
14960       if (!need_vex)
14961         abort ();
14962
14963       switch (vex.length)
14964         {
14965         case 128:
14966           oappend ("DWORD PTR ");
14967           break;
14968         case 256:
14969           oappend ("QWORD PTR ");
14970           break;
14971         case 512:
14972           oappend ("XMMWORD PTR ");
14973           break;
14974         default:
14975           abort ();
14976         }
14977       break;
14978     case ymmq_mode:
14979       if (!need_vex)
14980         abort ();
14981
14982       switch (vex.length)
14983         {
14984         case 128:
14985           oappend ("QWORD PTR ");
14986           break;
14987         case 256:
14988           oappend ("YMMWORD PTR ");
14989           break;
14990         case 512:
14991           oappend ("ZMMWORD PTR ");
14992           break;
14993         default:
14994           abort ();
14995         }
14996       break;
14997     case ymmxmm_mode:
14998       if (!need_vex)
14999         abort ();
15000
15001       switch (vex.length)
15002         {
15003         case 128:
15004         case 256:
15005           oappend ("XMMWORD PTR ");
15006           break;
15007         default:
15008           abort ();
15009         }
15010       break;
15011     case o_mode:
15012       oappend ("OWORD PTR ");
15013       break;
15014     case xmm_mdq_mode:
15015     case vex_w_dq_mode:
15016     case vex_scalar_w_dq_mode:
15017       if (!need_vex)
15018         abort ();
15019
15020       if (vex.w)
15021         oappend ("QWORD PTR ");
15022       else
15023         oappend ("DWORD PTR ");
15024       break;
15025     case vex_vsib_d_w_dq_mode:
15026     case vex_vsib_q_w_dq_mode:
15027       if (!need_vex)
15028         abort ();
15029
15030       if (!vex.evex)
15031         {
15032           if (vex.w)
15033             oappend ("QWORD PTR ");
15034           else
15035             oappend ("DWORD PTR ");
15036         }
15037       else
15038         {
15039           switch (vex.length)
15040             {
15041             case 128:
15042               oappend ("XMMWORD PTR ");
15043               break;
15044             case 256:
15045               oappend ("YMMWORD PTR ");
15046               break;
15047             case 512:
15048               oappend ("ZMMWORD PTR ");
15049               break;
15050             default:
15051               abort ();
15052             }
15053         }
15054       break;
15055     case vex_vsib_q_w_d_mode:
15056     case vex_vsib_d_w_d_mode:
15057       if (!need_vex || !vex.evex)
15058         abort ();
15059
15060       switch (vex.length)
15061         {
15062         case 128:
15063           oappend ("QWORD PTR ");
15064           break;
15065         case 256:
15066           oappend ("XMMWORD PTR ");
15067           break;
15068         case 512:
15069           oappend ("YMMWORD PTR ");
15070           break;
15071         default:
15072           abort ();
15073         }
15074
15075       break;
15076     case mask_bd_mode:
15077       if (!need_vex || vex.length != 128)
15078         abort ();
15079       if (vex.w)
15080         oappend ("DWORD PTR ");
15081       else
15082         oappend ("BYTE PTR ");
15083       break;
15084     case mask_mode:
15085       if (!need_vex)
15086         abort ();
15087       if (vex.w)
15088         oappend ("QWORD PTR ");
15089       else
15090         oappend ("WORD PTR ");
15091       break;
15092     case v_bnd_mode:
15093     case v_bndmk_mode:
15094     default:
15095       break;
15096     }
15097 }
15098
15099 static void
15100 OP_E_register (int bytemode, int sizeflag)
15101 {
15102   int reg = modrm.rm;
15103   const char **names;
15104
15105   USED_REX (REX_B);
15106   if ((rex & REX_B))
15107     reg += 8;
15108
15109   if ((sizeflag & SUFFIX_ALWAYS)
15110       && (bytemode == b_swap_mode
15111           || bytemode == bnd_swap_mode
15112           || bytemode == v_swap_mode))
15113     swap_operand ();
15114
15115   switch (bytemode)
15116     {
15117     case b_mode:
15118     case b_swap_mode:
15119       USED_REX (0);
15120       if (rex)
15121         names = names8rex;
15122       else
15123         names = names8;
15124       break;
15125     case w_mode:
15126       names = names16;
15127       break;
15128     case d_mode:
15129     case dw_mode:
15130     case db_mode:
15131       names = names32;
15132       break;
15133     case q_mode:
15134       names = names64;
15135       break;
15136     case m_mode:
15137     case v_bnd_mode:
15138       names = address_mode == mode_64bit ? names64 : names32;
15139       break;
15140     case bnd_mode:
15141     case bnd_swap_mode:
15142       if (reg > 0x3)
15143         {
15144           oappend ("(bad)");
15145           return;
15146         }
15147       names = names_bnd;
15148       break;
15149     case indir_v_mode:
15150       if (address_mode == mode_64bit && isa64 == intel64)
15151         {
15152           names = names64;
15153           break;
15154         }
15155       /* Fall through.  */
15156     case stack_v_mode:
15157       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
15158         {
15159           names = names64;
15160           break;
15161         }
15162       bytemode = v_mode;
15163       /* Fall through.  */
15164     case v_mode:
15165     case v_swap_mode:
15166     case dq_mode:
15167     case dqb_mode:
15168     case dqd_mode:
15169     case dqw_mode:
15170     case dqa_mode:
15171       USED_REX (REX_W);
15172       if (rex & REX_W)
15173         names = names64;
15174       else
15175         {
15176           if ((sizeflag & DFLAG)
15177               || (bytemode != v_mode
15178                   && bytemode != v_swap_mode))
15179             names = names32;
15180           else
15181             names = names16;
15182           used_prefixes |= (prefixes & PREFIX_DATA);
15183         }
15184       break;
15185     case va_mode:
15186       names = (address_mode == mode_64bit
15187                ? names64 : names32);
15188       if (!(prefixes & PREFIX_ADDR))
15189         names = (address_mode == mode_16bit
15190                      ? names16 : names);
15191       else
15192         {
15193           /* Remove "addr16/addr32".  */
15194           all_prefixes[last_addr_prefix] = 0;
15195           names = (address_mode != mode_32bit
15196                        ? names32 : names16);
15197           used_prefixes |= PREFIX_ADDR;
15198         }
15199       break;
15200     case mask_bd_mode:
15201     case mask_mode:
15202       if (reg > 0x7)
15203         {
15204           oappend ("(bad)");
15205           return;
15206         }
15207       names = names_mask;
15208       break;
15209     case 0:
15210       return;
15211     default:
15212       oappend (INTERNAL_DISASSEMBLER_ERROR);
15213       return;
15214     }
15215   oappend (names[reg]);
15216 }
15217
15218 static void
15219 OP_E_memory (int bytemode, int sizeflag)
15220 {
15221   bfd_vma disp = 0;
15222   int add = (rex & REX_B) ? 8 : 0;
15223   int riprel = 0;
15224   int shift;
15225
15226   if (vex.evex)
15227     {
15228       /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0.  */
15229       if (vex.b
15230           && bytemode != x_mode
15231           && bytemode != xmmq_mode
15232           && bytemode != evex_half_bcst_xmmq_mode)
15233         {
15234           BadOp ();
15235           return;
15236         }
15237       switch (bytemode)
15238         {
15239         case dqw_mode:
15240         case dw_mode:
15241           shift = 1;
15242           break;
15243         case dqb_mode:
15244         case db_mode:
15245           shift = 0;
15246           break;
15247         case vex_vsib_d_w_dq_mode:
15248         case vex_vsib_d_w_d_mode:
15249         case vex_vsib_q_w_dq_mode:
15250         case vex_vsib_q_w_d_mode:
15251         case evex_x_gscat_mode:
15252         case xmm_mdq_mode:
15253           shift = vex.w ? 3 : 2;
15254           break;
15255         case x_mode:
15256         case evex_half_bcst_xmmq_mode:
15257         case xmmq_mode:
15258           if (vex.b)
15259             {
15260               shift = vex.w ? 3 : 2;
15261               break;
15262             }
15263           /* Fall through.  */
15264         case xmmqd_mode:
15265         case xmmdw_mode:
15266         case ymmq_mode:
15267         case evex_x_nobcst_mode:
15268         case x_swap_mode:
15269           switch (vex.length)
15270             {
15271             case 128:
15272               shift = 4;
15273               break;
15274             case 256:
15275               shift = 5;
15276               break;
15277             case 512:
15278               shift = 6;
15279               break;
15280             default:
15281               abort ();
15282             }
15283           break;
15284         case ymm_mode:
15285           shift = 5;
15286           break;
15287         case xmm_mode:
15288           shift = 4;
15289           break;
15290         case xmm_mq_mode:
15291         case q_mode:
15292         case q_scalar_mode:
15293         case q_swap_mode:
15294         case q_scalar_swap_mode:
15295           shift = 3;
15296           break;
15297         case dqd_mode:
15298         case xmm_md_mode:
15299         case d_mode:
15300         case d_scalar_mode:
15301         case d_swap_mode:
15302         case d_scalar_swap_mode:
15303           shift = 2;
15304           break;
15305         case w_scalar_mode:
15306         case xmm_mw_mode:
15307           shift = 1;
15308           break;
15309         case b_scalar_mode:
15310         case xmm_mb_mode:
15311           shift = 0;
15312           break;
15313         case dqa_mode:
15314           shift = address_mode == mode_64bit ? 3 : 2;
15315           break;
15316         default:
15317           abort ();
15318         }
15319       /* Make necessary corrections to shift for modes that need it.
15320          For these modes we currently have shift 4, 5 or 6 depending on
15321          vex.length (it corresponds to xmmword, ymmword or zmmword
15322          operand).  We might want to make it 3, 4 or 5 (e.g. for
15323          xmmq_mode).  In case of broadcast enabled the corrections
15324          aren't needed, as element size is always 32 or 64 bits.  */
15325       if (!vex.b
15326           && (bytemode == xmmq_mode
15327               || bytemode == evex_half_bcst_xmmq_mode))
15328         shift -= 1;
15329       else if (bytemode == xmmqd_mode)
15330         shift -= 2;
15331       else if (bytemode == xmmdw_mode)
15332         shift -= 3;
15333       else if (bytemode == ymmq_mode && vex.length == 128)
15334         shift -= 1;
15335     }
15336   else
15337     shift = 0;
15338
15339   USED_REX (REX_B);
15340   if (intel_syntax)
15341     intel_operand_size (bytemode, sizeflag);
15342   append_seg ();
15343
15344   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
15345     {
15346       /* 32/64 bit address mode */
15347       int havedisp;
15348       int havesib;
15349       int havebase;
15350       int haveindex;
15351       int needindex;
15352       int needaddr32;
15353       int base, rbase;
15354       int vindex = 0;
15355       int scale = 0;
15356       int addr32flag = !((sizeflag & AFLAG)
15357                          || bytemode == v_bnd_mode
15358                          || bytemode == v_bndmk_mode
15359                          || bytemode == bnd_mode
15360                          || bytemode == bnd_swap_mode);
15361       const char **indexes64 = names64;
15362       const char **indexes32 = names32;
15363
15364       havesib = 0;
15365       havebase = 1;
15366       haveindex = 0;
15367       base = modrm.rm;
15368
15369       if (base == 4)
15370         {
15371           havesib = 1;
15372           vindex = sib.index;
15373           USED_REX (REX_X);
15374           if (rex & REX_X)
15375             vindex += 8;
15376           switch (bytemode)
15377             {
15378             case vex_vsib_d_w_dq_mode:
15379             case vex_vsib_d_w_d_mode:
15380             case vex_vsib_q_w_dq_mode:
15381             case vex_vsib_q_w_d_mode:
15382               if (!need_vex)
15383                 abort ();
15384               if (vex.evex)
15385                 {
15386                   if (!vex.v)
15387                     vindex += 16;
15388                 }
15389
15390               haveindex = 1;
15391               switch (vex.length)
15392                 {
15393                 case 128:
15394                   indexes64 = indexes32 = names_xmm;
15395                   break;
15396                 case 256:
15397                   if (!vex.w
15398                       || bytemode == vex_vsib_q_w_dq_mode
15399                       || bytemode == vex_vsib_q_w_d_mode)
15400                     indexes64 = indexes32 = names_ymm;
15401                   else
15402                     indexes64 = indexes32 = names_xmm;
15403                   break;
15404                 case 512:
15405                   if (!vex.w
15406                       || bytemode == vex_vsib_q_w_dq_mode
15407                       || bytemode == vex_vsib_q_w_d_mode)
15408                     indexes64 = indexes32 = names_zmm;
15409                   else
15410                     indexes64 = indexes32 = names_ymm;
15411                   break;
15412                 default:
15413                   abort ();
15414                 }
15415               break;
15416             default:
15417               haveindex = vindex != 4;
15418               break;
15419             }
15420           scale = sib.scale;
15421           base = sib.base;
15422           codep++;
15423         }
15424       rbase = base + add;
15425
15426       switch (modrm.mod)
15427         {
15428         case 0:
15429           if (base == 5)
15430             {
15431               havebase = 0;
15432               if (address_mode == mode_64bit && !havesib)
15433                 riprel = 1;
15434               disp = get32s ();
15435               if (riprel && bytemode == v_bndmk_mode)
15436                 {
15437                   oappend ("(bad)");
15438                   return;
15439                 }
15440             }
15441           break;
15442         case 1:
15443           FETCH_DATA (the_info, codep + 1);
15444           disp = *codep++;
15445           if ((disp & 0x80) != 0)
15446             disp -= 0x100;
15447           if (vex.evex && shift > 0)
15448             disp <<= shift;
15449           break;
15450         case 2:
15451           disp = get32s ();
15452           break;
15453         }
15454
15455       needindex = 0;
15456       needaddr32 = 0;
15457       if (havesib
15458           && !havebase
15459           && !haveindex
15460           && address_mode != mode_16bit)
15461         {
15462           if (address_mode == mode_64bit)
15463             {
15464               /* Display eiz instead of addr32.  */
15465               needindex = addr32flag;
15466               needaddr32 = 1;
15467             }
15468           else
15469             {
15470               /* In 32-bit mode, we need index register to tell [offset]
15471                  from [eiz*1 + offset].  */
15472               needindex = 1;
15473             }
15474         }
15475
15476       havedisp = (havebase
15477                   || needindex
15478                   || (havesib && (haveindex || scale != 0)));
15479
15480       if (!intel_syntax)
15481         if (modrm.mod != 0 || base == 5)
15482           {
15483             if (havedisp || riprel)
15484               print_displacement (scratchbuf, disp);
15485             else
15486               print_operand_value (scratchbuf, 1, disp);
15487             oappend (scratchbuf);
15488             if (riprel)
15489               {
15490                 set_op (disp, 1);
15491                 oappend (!addr32flag ? "(%rip)" : "(%eip)");
15492               }
15493           }
15494
15495       if ((havebase || haveindex || needaddr32 || riprel)
15496           && (bytemode != v_bnd_mode)
15497           && (bytemode != v_bndmk_mode)
15498           && (bytemode != bnd_mode)
15499           && (bytemode != bnd_swap_mode))
15500         used_prefixes |= PREFIX_ADDR;
15501
15502       if (havedisp || (intel_syntax && riprel))
15503         {
15504           *obufp++ = open_char;
15505           if (intel_syntax && riprel)
15506             {
15507               set_op (disp, 1);
15508               oappend (!addr32flag ? "rip" : "eip");
15509             }
15510           *obufp = '\0';
15511           if (havebase)
15512             oappend (address_mode == mode_64bit && !addr32flag
15513                      ? names64[rbase] : names32[rbase]);
15514           if (havesib)
15515             {
15516               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
15517                  print index to tell base + index from base.  */
15518               if (scale != 0
15519                   || needindex
15520                   || haveindex
15521                   || (havebase && base != ESP_REG_NUM))
15522                 {
15523                   if (!intel_syntax || havebase)
15524                     {
15525                       *obufp++ = separator_char;
15526                       *obufp = '\0';
15527                     }
15528                   if (haveindex)
15529                     oappend (address_mode == mode_64bit && !addr32flag
15530                              ? indexes64[vindex] : indexes32[vindex]);
15531                   else
15532                     oappend (address_mode == mode_64bit && !addr32flag
15533                              ? index64 : index32);
15534
15535                   *obufp++ = scale_char;
15536                   *obufp = '\0';
15537                   sprintf (scratchbuf, "%d", 1 << scale);
15538                   oappend (scratchbuf);
15539                 }
15540             }
15541           if (intel_syntax
15542               && (disp || modrm.mod != 0 || base == 5))
15543             {
15544               if (!havedisp || (bfd_signed_vma) disp >= 0)
15545                 {
15546                   *obufp++ = '+';
15547                   *obufp = '\0';
15548                 }
15549               else if (modrm.mod != 1 && disp != -disp)
15550                 {
15551                   *obufp++ = '-';
15552                   *obufp = '\0';
15553                   disp = - (bfd_signed_vma) disp;
15554                 }
15555
15556               if (havedisp)
15557                 print_displacement (scratchbuf, disp);
15558               else
15559                 print_operand_value (scratchbuf, 1, disp);
15560               oappend (scratchbuf);
15561             }
15562
15563           *obufp++ = close_char;
15564           *obufp = '\0';
15565         }
15566       else if (intel_syntax)
15567         {
15568           if (modrm.mod != 0 || base == 5)
15569             {
15570               if (!active_seg_prefix)
15571                 {
15572                   oappend (names_seg[ds_reg - es_reg]);
15573                   oappend (":");
15574                 }
15575               print_operand_value (scratchbuf, 1, disp);
15576               oappend (scratchbuf);
15577             }
15578         }
15579     }
15580   else
15581     {
15582       /* 16 bit address mode */
15583       used_prefixes |= prefixes & PREFIX_ADDR;
15584       switch (modrm.mod)
15585         {
15586         case 0:
15587           if (modrm.rm == 6)
15588             {
15589               disp = get16 ();
15590               if ((disp & 0x8000) != 0)
15591                 disp -= 0x10000;
15592             }
15593           break;
15594         case 1:
15595           FETCH_DATA (the_info, codep + 1);
15596           disp = *codep++;
15597           if ((disp & 0x80) != 0)
15598             disp -= 0x100;
15599           if (vex.evex && shift > 0)
15600             disp <<= shift;
15601           break;
15602         case 2:
15603           disp = get16 ();
15604           if ((disp & 0x8000) != 0)
15605             disp -= 0x10000;
15606           break;
15607         }
15608
15609       if (!intel_syntax)
15610         if (modrm.mod != 0 || modrm.rm == 6)
15611           {
15612             print_displacement (scratchbuf, disp);
15613             oappend (scratchbuf);
15614           }
15615
15616       if (modrm.mod != 0 || modrm.rm != 6)
15617         {
15618           *obufp++ = open_char;
15619           *obufp = '\0';
15620           oappend (index16[modrm.rm]);
15621           if (intel_syntax
15622               && (disp || modrm.mod != 0 || modrm.rm == 6))
15623             {
15624               if ((bfd_signed_vma) disp >= 0)
15625                 {
15626                   *obufp++ = '+';
15627                   *obufp = '\0';
15628                 }
15629               else if (modrm.mod != 1)
15630                 {
15631                   *obufp++ = '-';
15632                   *obufp = '\0';
15633                   disp = - (bfd_signed_vma) disp;
15634                 }
15635
15636               print_displacement (scratchbuf, disp);
15637               oappend (scratchbuf);
15638             }
15639
15640           *obufp++ = close_char;
15641           *obufp = '\0';
15642         }
15643       else if (intel_syntax)
15644         {
15645           if (!active_seg_prefix)
15646             {
15647               oappend (names_seg[ds_reg - es_reg]);
15648               oappend (":");
15649             }
15650           print_operand_value (scratchbuf, 1, disp & 0xffff);
15651           oappend (scratchbuf);
15652         }
15653     }
15654   if (vex.evex && vex.b
15655       && (bytemode == x_mode
15656           || bytemode == xmmq_mode
15657           || bytemode == evex_half_bcst_xmmq_mode))
15658     {
15659       if (vex.w
15660           || bytemode == xmmq_mode
15661           || bytemode == evex_half_bcst_xmmq_mode)
15662         {
15663           switch (vex.length)
15664             {
15665             case 128:
15666               oappend ("{1to2}");
15667               break;
15668             case 256:
15669               oappend ("{1to4}");
15670               break;
15671             case 512:
15672               oappend ("{1to8}");
15673               break;
15674             default:
15675               abort ();
15676             }
15677         }
15678       else
15679         {
15680           switch (vex.length)
15681             {
15682             case 128:
15683               oappend ("{1to4}");
15684               break;
15685             case 256:
15686               oappend ("{1to8}");
15687               break;
15688             case 512:
15689               oappend ("{1to16}");
15690               break;
15691             default:
15692               abort ();
15693             }
15694         }
15695     }
15696 }
15697
15698 static void
15699 OP_E (int bytemode, int sizeflag)
15700 {
15701   /* Skip mod/rm byte.  */
15702   MODRM_CHECK;
15703   codep++;
15704
15705   if (modrm.mod == 3)
15706     OP_E_register (bytemode, sizeflag);
15707   else
15708     OP_E_memory (bytemode, sizeflag);
15709 }
15710
15711 static void
15712 OP_G (int bytemode, int sizeflag)
15713 {
15714   int add = 0;
15715   const char **names;
15716   USED_REX (REX_R);
15717   if (rex & REX_R)
15718     add += 8;
15719   switch (bytemode)
15720     {
15721     case b_mode:
15722       USED_REX (0);
15723       if (rex)
15724         oappend (names8rex[modrm.reg + add]);
15725       else
15726         oappend (names8[modrm.reg + add]);
15727       break;
15728     case w_mode:
15729       oappend (names16[modrm.reg + add]);
15730       break;
15731     case d_mode:
15732     case db_mode:
15733     case dw_mode:
15734       oappend (names32[modrm.reg + add]);
15735       break;
15736     case q_mode:
15737       oappend (names64[modrm.reg + add]);
15738       break;
15739     case bnd_mode:
15740       if (modrm.reg > 0x3)
15741         {
15742           oappend ("(bad)");
15743           return;
15744         }
15745       oappend (names_bnd[modrm.reg]);
15746       break;
15747     case v_mode:
15748     case dq_mode:
15749     case dqb_mode:
15750     case dqd_mode:
15751     case dqw_mode:
15752       USED_REX (REX_W);
15753       if (rex & REX_W)
15754         oappend (names64[modrm.reg + add]);
15755       else
15756         {
15757           if ((sizeflag & DFLAG) || bytemode != v_mode)
15758             oappend (names32[modrm.reg + add]);
15759           else
15760             oappend (names16[modrm.reg + add]);
15761           used_prefixes |= (prefixes & PREFIX_DATA);
15762         }
15763       break;
15764     case va_mode:
15765       names = (address_mode == mode_64bit
15766                ? names64 : names32);
15767       if (!(prefixes & PREFIX_ADDR))
15768         {
15769           if (address_mode == mode_16bit)
15770             names = names16;
15771         }
15772       else
15773         {
15774           /* Remove "addr16/addr32".  */
15775           all_prefixes[last_addr_prefix] = 0;
15776           names = (address_mode != mode_32bit
15777                        ? names32 : names16);
15778           used_prefixes |= PREFIX_ADDR;
15779         }
15780       oappend (names[modrm.reg + add]);
15781       break;
15782     case m_mode:
15783       if (address_mode == mode_64bit)
15784         oappend (names64[modrm.reg + add]);
15785       else
15786         oappend (names32[modrm.reg + add]);
15787       break;
15788     case mask_bd_mode:
15789     case mask_mode:
15790       if ((modrm.reg + add) > 0x7)
15791         {
15792           oappend ("(bad)");
15793           return;
15794         }
15795       oappend (names_mask[modrm.reg + add]);
15796       break;
15797     default:
15798       oappend (INTERNAL_DISASSEMBLER_ERROR);
15799       break;
15800     }
15801 }
15802
15803 static bfd_vma
15804 get64 (void)
15805 {
15806   bfd_vma x;
15807 #ifdef BFD64
15808   unsigned int a;
15809   unsigned int b;
15810
15811   FETCH_DATA (the_info, codep + 8);
15812   a = *codep++ & 0xff;
15813   a |= (*codep++ & 0xff) << 8;
15814   a |= (*codep++ & 0xff) << 16;
15815   a |= (*codep++ & 0xffu) << 24;
15816   b = *codep++ & 0xff;
15817   b |= (*codep++ & 0xff) << 8;
15818   b |= (*codep++ & 0xff) << 16;
15819   b |= (*codep++ & 0xffu) << 24;
15820   x = a + ((bfd_vma) b << 32);
15821 #else
15822   abort ();
15823   x = 0;
15824 #endif
15825   return x;
15826 }
15827
15828 static bfd_signed_vma
15829 get32 (void)
15830 {
15831   bfd_signed_vma x = 0;
15832
15833   FETCH_DATA (the_info, codep + 4);
15834   x = *codep++ & (bfd_signed_vma) 0xff;
15835   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15836   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15837   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15838   return x;
15839 }
15840
15841 static bfd_signed_vma
15842 get32s (void)
15843 {
15844   bfd_signed_vma x = 0;
15845
15846   FETCH_DATA (the_info, codep + 4);
15847   x = *codep++ & (bfd_signed_vma) 0xff;
15848   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15849   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15850   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15851
15852   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
15853
15854   return x;
15855 }
15856
15857 static int
15858 get16 (void)
15859 {
15860   int x = 0;
15861
15862   FETCH_DATA (the_info, codep + 2);
15863   x = *codep++ & 0xff;
15864   x |= (*codep++ & 0xff) << 8;
15865   return x;
15866 }
15867
15868 static void
15869 set_op (bfd_vma op, int riprel)
15870 {
15871   op_index[op_ad] = op_ad;
15872   if (address_mode == mode_64bit)
15873     {
15874       op_address[op_ad] = op;
15875       op_riprel[op_ad] = riprel;
15876     }
15877   else
15878     {
15879       /* Mask to get a 32-bit address.  */
15880       op_address[op_ad] = op & 0xffffffff;
15881       op_riprel[op_ad] = riprel & 0xffffffff;
15882     }
15883 }
15884
15885 static void
15886 OP_REG (int code, int sizeflag)
15887 {
15888   const char *s;
15889   int add;
15890
15891   switch (code)
15892     {
15893     case es_reg: case ss_reg: case cs_reg:
15894     case ds_reg: case fs_reg: case gs_reg:
15895       oappend (names_seg[code - es_reg]);
15896       return;
15897     }
15898
15899   USED_REX (REX_B);
15900   if (rex & REX_B)
15901     add = 8;
15902   else
15903     add = 0;
15904
15905   switch (code)
15906     {
15907     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15908     case sp_reg: case bp_reg: case si_reg: case di_reg:
15909       s = names16[code - ax_reg + add];
15910       break;
15911     case al_reg: case ah_reg: case cl_reg: case ch_reg:
15912     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15913       USED_REX (0);
15914       if (rex)
15915         s = names8rex[code - al_reg + add];
15916       else
15917         s = names8[code - al_reg];
15918       break;
15919     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
15920     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
15921       if (address_mode == mode_64bit
15922           && ((sizeflag & DFLAG) || (rex & REX_W)))
15923         {
15924           s = names64[code - rAX_reg + add];
15925           break;
15926         }
15927       code += eAX_reg - rAX_reg;
15928       /* Fall through.  */
15929     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15930     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15931       USED_REX (REX_W);
15932       if (rex & REX_W)
15933         s = names64[code - eAX_reg + add];
15934       else
15935         {
15936           if (sizeflag & DFLAG)
15937             s = names32[code - eAX_reg + add];
15938           else
15939             s = names16[code - eAX_reg + add];
15940           used_prefixes |= (prefixes & PREFIX_DATA);
15941         }
15942       break;
15943     default:
15944       s = INTERNAL_DISASSEMBLER_ERROR;
15945       break;
15946     }
15947   oappend (s);
15948 }
15949
15950 static void
15951 OP_IMREG (int code, int sizeflag)
15952 {
15953   const char *s;
15954
15955   switch (code)
15956     {
15957     case indir_dx_reg:
15958       if (intel_syntax)
15959         s = "dx";
15960       else
15961         s = "(%dx)";
15962       break;
15963     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15964     case sp_reg: case bp_reg: case si_reg: case di_reg:
15965       s = names16[code - ax_reg];
15966       break;
15967     case es_reg: case ss_reg: case cs_reg:
15968     case ds_reg: case fs_reg: case gs_reg:
15969       s = names_seg[code - es_reg];
15970       break;
15971     case al_reg: case ah_reg: case cl_reg: case ch_reg:
15972     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15973       USED_REX (0);
15974       if (rex)
15975         s = names8rex[code - al_reg];
15976       else
15977         s = names8[code - al_reg];
15978       break;
15979     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15980     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15981       USED_REX (REX_W);
15982       if (rex & REX_W)
15983         s = names64[code - eAX_reg];
15984       else
15985         {
15986           if (sizeflag & DFLAG)
15987             s = names32[code - eAX_reg];
15988           else
15989             s = names16[code - eAX_reg];
15990           used_prefixes |= (prefixes & PREFIX_DATA);
15991         }
15992       break;
15993     case z_mode_ax_reg:
15994       if ((rex & REX_W) || (sizeflag & DFLAG))
15995         s = *names32;
15996       else
15997         s = *names16;
15998       if (!(rex & REX_W))
15999         used_prefixes |= (prefixes & PREFIX_DATA);
16000       break;
16001     default:
16002       s = INTERNAL_DISASSEMBLER_ERROR;
16003       break;
16004     }
16005   oappend (s);
16006 }
16007
16008 static void
16009 OP_I (int bytemode, int sizeflag)
16010 {
16011   bfd_signed_vma op;
16012   bfd_signed_vma mask = -1;
16013
16014   switch (bytemode)
16015     {
16016     case b_mode:
16017       FETCH_DATA (the_info, codep + 1);
16018       op = *codep++;
16019       mask = 0xff;
16020       break;
16021     case q_mode:
16022       if (address_mode == mode_64bit)
16023         {
16024           op = get32s ();
16025           break;
16026         }
16027       /* Fall through.  */
16028     case v_mode:
16029       USED_REX (REX_W);
16030       if (rex & REX_W)
16031         op = get32s ();
16032       else
16033         {
16034           if (sizeflag & DFLAG)
16035             {
16036               op = get32 ();
16037               mask = 0xffffffff;
16038             }
16039           else
16040             {
16041               op = get16 ();
16042               mask = 0xfffff;
16043             }
16044           used_prefixes |= (prefixes & PREFIX_DATA);
16045         }
16046       break;
16047     case w_mode:
16048       mask = 0xfffff;
16049       op = get16 ();
16050       break;
16051     case const_1_mode:
16052       if (intel_syntax)
16053         oappend ("1");
16054       return;
16055     default:
16056       oappend (INTERNAL_DISASSEMBLER_ERROR);
16057       return;
16058     }
16059
16060   op &= mask;
16061   scratchbuf[0] = '$';
16062   print_operand_value (scratchbuf + 1, 1, op);
16063   oappend_maybe_intel (scratchbuf);
16064   scratchbuf[0] = '\0';
16065 }
16066
16067 static void
16068 OP_I64 (int bytemode, int sizeflag)
16069 {
16070   bfd_signed_vma op;
16071   bfd_signed_vma mask = -1;
16072
16073   if (address_mode != mode_64bit)
16074     {
16075       OP_I (bytemode, sizeflag);
16076       return;
16077     }
16078
16079   switch (bytemode)
16080     {
16081     case b_mode:
16082       FETCH_DATA (the_info, codep + 1);
16083       op = *codep++;
16084       mask = 0xff;
16085       break;
16086     case v_mode:
16087       USED_REX (REX_W);
16088       if (rex & REX_W)
16089         op = get64 ();
16090       else
16091         {
16092           if (sizeflag & DFLAG)
16093             {
16094               op = get32 ();
16095               mask = 0xffffffff;
16096             }
16097           else
16098             {
16099               op = get16 ();
16100               mask = 0xfffff;
16101             }
16102           used_prefixes |= (prefixes & PREFIX_DATA);
16103         }
16104       break;
16105     case w_mode:
16106       mask = 0xfffff;
16107       op = get16 ();
16108       break;
16109     default:
16110       oappend (INTERNAL_DISASSEMBLER_ERROR);
16111       return;
16112     }
16113
16114   op &= mask;
16115   scratchbuf[0] = '$';
16116   print_operand_value (scratchbuf + 1, 1, op);
16117   oappend_maybe_intel (scratchbuf);
16118   scratchbuf[0] = '\0';
16119 }
16120
16121 static void
16122 OP_sI (int bytemode, int sizeflag)
16123 {
16124   bfd_signed_vma op;
16125
16126   switch (bytemode)
16127     {
16128     case b_mode:
16129     case b_T_mode:
16130       FETCH_DATA (the_info, codep + 1);
16131       op = *codep++;
16132       if ((op & 0x80) != 0)
16133         op -= 0x100;
16134       if (bytemode == b_T_mode)
16135         {
16136           if (address_mode != mode_64bit
16137               || !((sizeflag & DFLAG) || (rex & REX_W)))
16138             {
16139               /* The operand-size prefix is overridden by a REX prefix.  */
16140               if ((sizeflag & DFLAG) || (rex & REX_W))
16141                 op &= 0xffffffff;
16142               else
16143                 op &= 0xffff;
16144           }
16145         }
16146       else
16147         {
16148           if (!(rex & REX_W))
16149             {
16150               if (sizeflag & DFLAG)
16151                 op &= 0xffffffff;
16152               else
16153                 op &= 0xffff;
16154             }
16155         }
16156       break;
16157     case v_mode:
16158       /* The operand-size prefix is overridden by a REX prefix.  */
16159       if ((sizeflag & DFLAG) || (rex & REX_W))
16160         op = get32s ();
16161       else
16162         op = get16 ();
16163       break;
16164     default:
16165       oappend (INTERNAL_DISASSEMBLER_ERROR);
16166       return;
16167     }
16168
16169   scratchbuf[0] = '$';
16170   print_operand_value (scratchbuf + 1, 1, op);
16171   oappend_maybe_intel (scratchbuf);
16172 }
16173
16174 static void
16175 OP_J (int bytemode, int sizeflag)
16176 {
16177   bfd_vma disp;
16178   bfd_vma mask = -1;
16179   bfd_vma segment = 0;
16180
16181   switch (bytemode)
16182     {
16183     case b_mode:
16184       FETCH_DATA (the_info, codep + 1);
16185       disp = *codep++;
16186       if ((disp & 0x80) != 0)
16187         disp -= 0x100;
16188       break;
16189     case v_mode:
16190       if (isa64 == amd64)
16191         USED_REX (REX_W);
16192       if ((sizeflag & DFLAG)
16193           || (address_mode == mode_64bit
16194               && (isa64 != amd64 || (rex & REX_W))))
16195         disp = get32s ();
16196       else
16197         {
16198           disp = get16 ();
16199           if ((disp & 0x8000) != 0)
16200             disp -= 0x10000;
16201           /* In 16bit mode, address is wrapped around at 64k within
16202              the same segment.  Otherwise, a data16 prefix on a jump
16203              instruction means that the pc is masked to 16 bits after
16204              the displacement is added!  */
16205           mask = 0xffff;
16206           if ((prefixes & PREFIX_DATA) == 0)
16207             segment = ((start_pc + (codep - start_codep))
16208                        & ~((bfd_vma) 0xffff));
16209         }
16210       if (address_mode != mode_64bit
16211           || (isa64 == amd64 && !(rex & REX_W)))
16212         used_prefixes |= (prefixes & PREFIX_DATA);
16213       break;
16214     default:
16215       oappend (INTERNAL_DISASSEMBLER_ERROR);
16216       return;
16217     }
16218   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
16219   set_op (disp, 0);
16220   print_operand_value (scratchbuf, 1, disp);
16221   oappend (scratchbuf);
16222 }
16223
16224 static void
16225 OP_SEG (int bytemode, int sizeflag)
16226 {
16227   if (bytemode == w_mode)
16228     oappend (names_seg[modrm.reg]);
16229   else
16230     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
16231 }
16232
16233 static void
16234 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
16235 {
16236   int seg, offset;
16237
16238   if (sizeflag & DFLAG)
16239     {
16240       offset = get32 ();
16241       seg = get16 ();
16242     }
16243   else
16244     {
16245       offset = get16 ();
16246       seg = get16 ();
16247     }
16248   used_prefixes |= (prefixes & PREFIX_DATA);
16249   if (intel_syntax)
16250     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
16251   else
16252     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
16253   oappend (scratchbuf);
16254 }
16255
16256 static void
16257 OP_OFF (int bytemode, int sizeflag)
16258 {
16259   bfd_vma off;
16260
16261   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
16262     intel_operand_size (bytemode, sizeflag);
16263   append_seg ();
16264
16265   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
16266     off = get32 ();
16267   else
16268     off = get16 ();
16269
16270   if (intel_syntax)
16271     {
16272       if (!active_seg_prefix)
16273         {
16274           oappend (names_seg[ds_reg - es_reg]);
16275           oappend (":");
16276         }
16277     }
16278   print_operand_value (scratchbuf, 1, off);
16279   oappend (scratchbuf);
16280 }
16281
16282 static void
16283 OP_OFF64 (int bytemode, int sizeflag)
16284 {
16285   bfd_vma off;
16286
16287   if (address_mode != mode_64bit
16288       || (prefixes & PREFIX_ADDR))
16289     {
16290       OP_OFF (bytemode, sizeflag);
16291       return;
16292     }
16293
16294   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
16295     intel_operand_size (bytemode, sizeflag);
16296   append_seg ();
16297
16298   off = get64 ();
16299
16300   if (intel_syntax)
16301     {
16302       if (!active_seg_prefix)
16303         {
16304           oappend (names_seg[ds_reg - es_reg]);
16305           oappend (":");
16306         }
16307     }
16308   print_operand_value (scratchbuf, 1, off);
16309   oappend (scratchbuf);
16310 }
16311
16312 static void
16313 ptr_reg (int code, int sizeflag)
16314 {
16315   const char *s;
16316
16317   *obufp++ = open_char;
16318   used_prefixes |= (prefixes & PREFIX_ADDR);
16319   if (address_mode == mode_64bit)
16320     {
16321       if (!(sizeflag & AFLAG))
16322         s = names32[code - eAX_reg];
16323       else
16324         s = names64[code - eAX_reg];
16325     }
16326   else if (sizeflag & AFLAG)
16327     s = names32[code - eAX_reg];
16328   else
16329     s = names16[code - eAX_reg];
16330   oappend (s);
16331   *obufp++ = close_char;
16332   *obufp = 0;
16333 }
16334
16335 static void
16336 OP_ESreg (int code, int sizeflag)
16337 {
16338   if (intel_syntax)
16339     {
16340       switch (codep[-1])
16341         {
16342         case 0x6d:      /* insw/insl */
16343           intel_operand_size (z_mode, sizeflag);
16344           break;
16345         case 0xa5:      /* movsw/movsl/movsq */
16346         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
16347         case 0xab:      /* stosw/stosl */
16348         case 0xaf:      /* scasw/scasl */
16349           intel_operand_size (v_mode, sizeflag);
16350           break;
16351         default:
16352           intel_operand_size (b_mode, sizeflag);
16353         }
16354     }
16355   oappend_maybe_intel ("%es:");
16356   ptr_reg (code, sizeflag);
16357 }
16358
16359 static void
16360 OP_DSreg (int code, int sizeflag)
16361 {
16362   if (intel_syntax)
16363     {
16364       switch (codep[-1])
16365         {
16366         case 0x6f:      /* outsw/outsl */
16367           intel_operand_size (z_mode, sizeflag);
16368           break;
16369         case 0xa5:      /* movsw/movsl/movsq */
16370         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
16371         case 0xad:      /* lodsw/lodsl/lodsq */
16372           intel_operand_size (v_mode, sizeflag);
16373           break;
16374         default:
16375           intel_operand_size (b_mode, sizeflag);
16376         }
16377     }
16378   /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
16379      default segment register DS is printed.  */
16380   if (!active_seg_prefix)
16381     active_seg_prefix = PREFIX_DS;
16382   append_seg ();
16383   ptr_reg (code, sizeflag);
16384 }
16385
16386 static void
16387 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16388 {
16389   int add;
16390   if (rex & REX_R)
16391     {
16392       USED_REX (REX_R);
16393       add = 8;
16394     }
16395   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
16396     {
16397       all_prefixes[last_lock_prefix] = 0;
16398       used_prefixes |= PREFIX_LOCK;
16399       add = 8;
16400     }
16401   else
16402     add = 0;
16403   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
16404   oappend_maybe_intel (scratchbuf);
16405 }
16406
16407 static void
16408 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16409 {
16410   int add;
16411   USED_REX (REX_R);
16412   if (rex & REX_R)
16413     add = 8;
16414   else
16415     add = 0;
16416   if (intel_syntax)
16417     sprintf (scratchbuf, "db%d", modrm.reg + add);
16418   else
16419     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
16420   oappend (scratchbuf);
16421 }
16422
16423 static void
16424 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16425 {
16426   sprintf (scratchbuf, "%%tr%d", modrm.reg);
16427   oappend_maybe_intel (scratchbuf);
16428 }
16429
16430 static void
16431 OP_R (int bytemode, int sizeflag)
16432 {
16433   /* Skip mod/rm byte.  */
16434   MODRM_CHECK;
16435   codep++;
16436   OP_E_register (bytemode, sizeflag);
16437 }
16438
16439 static void
16440 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16441 {
16442   int reg = modrm.reg;
16443   const char **names;
16444
16445   used_prefixes |= (prefixes & PREFIX_DATA);
16446   if (prefixes & PREFIX_DATA)
16447     {
16448       names = names_xmm;
16449       USED_REX (REX_R);
16450       if (rex & REX_R)
16451         reg += 8;
16452     }
16453   else
16454     names = names_mm;
16455   oappend (names[reg]);
16456 }
16457
16458 static void
16459 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16460 {
16461   int reg = modrm.reg;
16462   const char **names;
16463
16464   USED_REX (REX_R);
16465   if (rex & REX_R)
16466     reg += 8;
16467   if (vex.evex)
16468     {
16469       if (!vex.r)
16470         reg += 16;
16471     }
16472
16473   if (need_vex
16474       && bytemode != xmm_mode
16475       && bytemode != xmmq_mode
16476       && bytemode != evex_half_bcst_xmmq_mode
16477       && bytemode != ymm_mode
16478       && bytemode != scalar_mode)
16479     {
16480       switch (vex.length)
16481         {
16482         case 128:
16483           names = names_xmm;
16484           break;
16485         case 256:
16486           if (vex.w
16487               || (bytemode != vex_vsib_q_w_dq_mode
16488                   && bytemode != vex_vsib_q_w_d_mode))
16489             names = names_ymm;
16490           else
16491             names = names_xmm;
16492           break;
16493         case 512:
16494           names = names_zmm;
16495           break;
16496         default:
16497           abort ();
16498         }
16499     }
16500   else if (bytemode == xmmq_mode
16501            || bytemode == evex_half_bcst_xmmq_mode)
16502     {
16503       switch (vex.length)
16504         {
16505         case 128:
16506         case 256:
16507           names = names_xmm;
16508           break;
16509         case 512:
16510           names = names_ymm;
16511           break;
16512         default:
16513           abort ();
16514         }
16515     }
16516   else if (bytemode == ymm_mode)
16517     names = names_ymm;
16518   else
16519     names = names_xmm;
16520   oappend (names[reg]);
16521 }
16522
16523 static void
16524 OP_EM (int bytemode, int sizeflag)
16525 {
16526   int reg;
16527   const char **names;
16528
16529   if (modrm.mod != 3)
16530     {
16531       if (intel_syntax
16532           && (bytemode == v_mode || bytemode == v_swap_mode))
16533         {
16534           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16535           used_prefixes |= (prefixes & PREFIX_DATA);
16536         }
16537       OP_E (bytemode, sizeflag);
16538       return;
16539     }
16540
16541   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
16542     swap_operand ();
16543
16544   /* Skip mod/rm byte.  */
16545   MODRM_CHECK;
16546   codep++;
16547   used_prefixes |= (prefixes & PREFIX_DATA);
16548   reg = modrm.rm;
16549   if (prefixes & PREFIX_DATA)
16550     {
16551       names = names_xmm;
16552       USED_REX (REX_B);
16553       if (rex & REX_B)
16554         reg += 8;
16555     }
16556   else
16557     names = names_mm;
16558   oappend (names[reg]);
16559 }
16560
16561 /* cvt* are the only instructions in sse2 which have
16562    both SSE and MMX operands and also have 0x66 prefix
16563    in their opcode. 0x66 was originally used to differentiate
16564    between SSE and MMX instruction(operands). So we have to handle the
16565    cvt* separately using OP_EMC and OP_MXC */
16566 static void
16567 OP_EMC (int bytemode, int sizeflag)
16568 {
16569   if (modrm.mod != 3)
16570     {
16571       if (intel_syntax && bytemode == v_mode)
16572         {
16573           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16574           used_prefixes |= (prefixes & PREFIX_DATA);
16575         }
16576       OP_E (bytemode, sizeflag);
16577       return;
16578     }
16579
16580   /* Skip mod/rm byte.  */
16581   MODRM_CHECK;
16582   codep++;
16583   used_prefixes |= (prefixes & PREFIX_DATA);
16584   oappend (names_mm[modrm.rm]);
16585 }
16586
16587 static void
16588 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16589 {
16590   used_prefixes |= (prefixes & PREFIX_DATA);
16591   oappend (names_mm[modrm.reg]);
16592 }
16593
16594 static void
16595 OP_EX (int bytemode, int sizeflag)
16596 {
16597   int reg;
16598   const char **names;
16599
16600   /* Skip mod/rm byte.  */
16601   MODRM_CHECK;
16602   codep++;
16603
16604   if (modrm.mod != 3)
16605     {
16606       OP_E_memory (bytemode, sizeflag);
16607       return;
16608     }
16609
16610   reg = modrm.rm;
16611   USED_REX (REX_B);
16612   if (rex & REX_B)
16613     reg += 8;
16614   if (vex.evex)
16615     {
16616       USED_REX (REX_X);
16617       if ((rex & REX_X))
16618         reg += 16;
16619     }
16620
16621   if ((sizeflag & SUFFIX_ALWAYS)
16622       && (bytemode == x_swap_mode
16623           || bytemode == d_swap_mode
16624           || bytemode == d_scalar_swap_mode
16625           || bytemode == q_swap_mode
16626           || bytemode == q_scalar_swap_mode))
16627     swap_operand ();
16628
16629   if (need_vex
16630       && bytemode != xmm_mode
16631       && bytemode != xmmdw_mode
16632       && bytemode != xmmqd_mode
16633       && bytemode != xmm_mb_mode
16634       && bytemode != xmm_mw_mode
16635       && bytemode != xmm_md_mode
16636       && bytemode != xmm_mq_mode
16637       && bytemode != xmm_mdq_mode
16638       && bytemode != xmmq_mode
16639       && bytemode != evex_half_bcst_xmmq_mode
16640       && bytemode != ymm_mode
16641       && bytemode != d_scalar_mode
16642       && bytemode != d_scalar_swap_mode
16643       && bytemode != q_scalar_mode
16644       && bytemode != q_scalar_swap_mode
16645       && bytemode != vex_scalar_w_dq_mode)
16646     {
16647       switch (vex.length)
16648         {
16649         case 128:
16650           names = names_xmm;
16651           break;
16652         case 256:
16653           names = names_ymm;
16654           break;
16655         case 512:
16656           names = names_zmm;
16657           break;
16658         default:
16659           abort ();
16660         }
16661     }
16662   else if (bytemode == xmmq_mode
16663            || bytemode == evex_half_bcst_xmmq_mode)
16664     {
16665       switch (vex.length)
16666         {
16667         case 128:
16668         case 256:
16669           names = names_xmm;
16670           break;
16671         case 512:
16672           names = names_ymm;
16673           break;
16674         default:
16675           abort ();
16676         }
16677     }
16678   else if (bytemode == ymm_mode)
16679     names = names_ymm;
16680   else
16681     names = names_xmm;
16682   oappend (names[reg]);
16683 }
16684
16685 static void
16686 OP_MS (int bytemode, int sizeflag)
16687 {
16688   if (modrm.mod == 3)
16689     OP_EM (bytemode, sizeflag);
16690   else
16691     BadOp ();
16692 }
16693
16694 static void
16695 OP_XS (int bytemode, int sizeflag)
16696 {
16697   if (modrm.mod == 3)
16698     OP_EX (bytemode, sizeflag);
16699   else
16700     BadOp ();
16701 }
16702
16703 static void
16704 OP_M (int bytemode, int sizeflag)
16705 {
16706   if (modrm.mod == 3)
16707     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
16708     BadOp ();
16709   else
16710     OP_E (bytemode, sizeflag);
16711 }
16712
16713 static void
16714 OP_0f07 (int bytemode, int sizeflag)
16715 {
16716   if (modrm.mod != 3 || modrm.rm != 0)
16717     BadOp ();
16718   else
16719     OP_E (bytemode, sizeflag);
16720 }
16721
16722 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
16723    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
16724
16725 static void
16726 NOP_Fixup1 (int bytemode, int sizeflag)
16727 {
16728   if ((prefixes & PREFIX_DATA) != 0
16729       || (rex != 0
16730           && rex != 0x48
16731           && address_mode == mode_64bit))
16732     OP_REG (bytemode, sizeflag);
16733   else
16734     strcpy (obuf, "nop");
16735 }
16736
16737 static void
16738 NOP_Fixup2 (int bytemode, int sizeflag)
16739 {
16740   if ((prefixes & PREFIX_DATA) != 0
16741       || (rex != 0
16742           && rex != 0x48
16743           && address_mode == mode_64bit))
16744     OP_IMREG (bytemode, sizeflag);
16745 }
16746
16747 static const char *const Suffix3DNow[] = {
16748 /* 00 */        NULL,           NULL,           NULL,           NULL,
16749 /* 04 */        NULL,           NULL,           NULL,           NULL,
16750 /* 08 */        NULL,           NULL,           NULL,           NULL,
16751 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
16752 /* 10 */        NULL,           NULL,           NULL,           NULL,
16753 /* 14 */        NULL,           NULL,           NULL,           NULL,
16754 /* 18 */        NULL,           NULL,           NULL,           NULL,
16755 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
16756 /* 20 */        NULL,           NULL,           NULL,           NULL,
16757 /* 24 */        NULL,           NULL,           NULL,           NULL,
16758 /* 28 */        NULL,           NULL,           NULL,           NULL,
16759 /* 2C */        NULL,           NULL,           NULL,           NULL,
16760 /* 30 */        NULL,           NULL,           NULL,           NULL,
16761 /* 34 */        NULL,           NULL,           NULL,           NULL,
16762 /* 38 */        NULL,           NULL,           NULL,           NULL,
16763 /* 3C */        NULL,           NULL,           NULL,           NULL,
16764 /* 40 */        NULL,           NULL,           NULL,           NULL,
16765 /* 44 */        NULL,           NULL,           NULL,           NULL,
16766 /* 48 */        NULL,           NULL,           NULL,           NULL,
16767 /* 4C */        NULL,           NULL,           NULL,           NULL,
16768 /* 50 */        NULL,           NULL,           NULL,           NULL,
16769 /* 54 */        NULL,           NULL,           NULL,           NULL,
16770 /* 58 */        NULL,           NULL,           NULL,           NULL,
16771 /* 5C */        NULL,           NULL,           NULL,           NULL,
16772 /* 60 */        NULL,           NULL,           NULL,           NULL,
16773 /* 64 */        NULL,           NULL,           NULL,           NULL,
16774 /* 68 */        NULL,           NULL,           NULL,           NULL,
16775 /* 6C */        NULL,           NULL,           NULL,           NULL,
16776 /* 70 */        NULL,           NULL,           NULL,           NULL,
16777 /* 74 */        NULL,           NULL,           NULL,           NULL,
16778 /* 78 */        NULL,           NULL,           NULL,           NULL,
16779 /* 7C */        NULL,           NULL,           NULL,           NULL,
16780 /* 80 */        NULL,           NULL,           NULL,           NULL,
16781 /* 84 */        NULL,           NULL,           NULL,           NULL,
16782 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
16783 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
16784 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
16785 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
16786 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
16787 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
16788 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
16789 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
16790 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
16791 /* AC */        NULL,           NULL,           "pfacc",        NULL,
16792 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
16793 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
16794 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
16795 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
16796 /* C0 */        NULL,           NULL,           NULL,           NULL,
16797 /* C4 */        NULL,           NULL,           NULL,           NULL,
16798 /* C8 */        NULL,           NULL,           NULL,           NULL,
16799 /* CC */        NULL,           NULL,           NULL,           NULL,
16800 /* D0 */        NULL,           NULL,           NULL,           NULL,
16801 /* D4 */        NULL,           NULL,           NULL,           NULL,
16802 /* D8 */        NULL,           NULL,           NULL,           NULL,
16803 /* DC */        NULL,           NULL,           NULL,           NULL,
16804 /* E0 */        NULL,           NULL,           NULL,           NULL,
16805 /* E4 */        NULL,           NULL,           NULL,           NULL,
16806 /* E8 */        NULL,           NULL,           NULL,           NULL,
16807 /* EC */        NULL,           NULL,           NULL,           NULL,
16808 /* F0 */        NULL,           NULL,           NULL,           NULL,
16809 /* F4 */        NULL,           NULL,           NULL,           NULL,
16810 /* F8 */        NULL,           NULL,           NULL,           NULL,
16811 /* FC */        NULL,           NULL,           NULL,           NULL,
16812 };
16813
16814 static void
16815 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16816 {
16817   const char *mnemonic;
16818
16819   FETCH_DATA (the_info, codep + 1);
16820   /* AMD 3DNow! instructions are specified by an opcode suffix in the
16821      place where an 8-bit immediate would normally go.  ie. the last
16822      byte of the instruction.  */
16823   obufp = mnemonicendp;
16824   mnemonic = Suffix3DNow[*codep++ & 0xff];
16825   if (mnemonic)
16826     oappend (mnemonic);
16827   else
16828     {
16829       /* Since a variable sized modrm/sib chunk is between the start
16830          of the opcode (0x0f0f) and the opcode suffix, we need to do
16831          all the modrm processing first, and don't know until now that
16832          we have a bad opcode.  This necessitates some cleaning up.  */
16833       op_out[0][0] = '\0';
16834       op_out[1][0] = '\0';
16835       BadOp ();
16836     }
16837   mnemonicendp = obufp;
16838 }
16839
16840 static struct op simd_cmp_op[] =
16841 {
16842   { STRING_COMMA_LEN ("eq") },
16843   { STRING_COMMA_LEN ("lt") },
16844   { STRING_COMMA_LEN ("le") },
16845   { STRING_COMMA_LEN ("unord") },
16846   { STRING_COMMA_LEN ("neq") },
16847   { STRING_COMMA_LEN ("nlt") },
16848   { STRING_COMMA_LEN ("nle") },
16849   { STRING_COMMA_LEN ("ord") }
16850 };
16851
16852 static void
16853 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16854 {
16855   unsigned int cmp_type;
16856
16857   FETCH_DATA (the_info, codep + 1);
16858   cmp_type = *codep++ & 0xff;
16859   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
16860     {
16861       char suffix [3];
16862       char *p = mnemonicendp - 2;
16863       suffix[0] = p[0];
16864       suffix[1] = p[1];
16865       suffix[2] = '\0';
16866       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16867       mnemonicendp += simd_cmp_op[cmp_type].len;
16868     }
16869   else
16870     {
16871       /* We have a reserved extension byte.  Output it directly.  */
16872       scratchbuf[0] = '$';
16873       print_operand_value (scratchbuf + 1, 1, cmp_type);
16874       oappend_maybe_intel (scratchbuf);
16875       scratchbuf[0] = '\0';
16876     }
16877 }
16878
16879 static void
16880 OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED,
16881           int sizeflag ATTRIBUTE_UNUSED)
16882 {
16883   /* mwaitx %eax,%ecx,%ebx */
16884   if (!intel_syntax)
16885     {
16886       const char **names = (address_mode == mode_64bit
16887                             ? names64 : names32);
16888       strcpy (op_out[0], names[0]);
16889       strcpy (op_out[1], names[1]);
16890       strcpy (op_out[2], names[3]);
16891       two_source_ops = 1;
16892     }
16893   /* Skip mod/rm byte.  */
16894   MODRM_CHECK;
16895   codep++;
16896 }
16897
16898 static void
16899 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
16900           int sizeflag ATTRIBUTE_UNUSED)
16901 {
16902   /* mwait %eax,%ecx  */
16903   if (!intel_syntax)
16904     {
16905       const char **names = (address_mode == mode_64bit
16906                             ? names64 : names32);
16907       strcpy (op_out[0], names[0]);
16908       strcpy (op_out[1], names[1]);
16909       two_source_ops = 1;
16910     }
16911   /* Skip mod/rm byte.  */
16912   MODRM_CHECK;
16913   codep++;
16914 }
16915
16916 static void
16917 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
16918             int sizeflag ATTRIBUTE_UNUSED)
16919 {
16920   /* monitor %eax,%ecx,%edx"  */
16921   if (!intel_syntax)
16922     {
16923       const char **op1_names;
16924       const char **names = (address_mode == mode_64bit
16925                             ? names64 : names32);
16926
16927       if (!(prefixes & PREFIX_ADDR))
16928         op1_names = (address_mode == mode_16bit
16929                      ? names16 : names);
16930       else
16931         {
16932           /* Remove "addr16/addr32".  */
16933           all_prefixes[last_addr_prefix] = 0;
16934           op1_names = (address_mode != mode_32bit
16935                        ? names32 : names16);
16936           used_prefixes |= PREFIX_ADDR;
16937         }
16938       strcpy (op_out[0], op1_names[0]);
16939       strcpy (op_out[1], names[1]);
16940       strcpy (op_out[2], names[2]);
16941       two_source_ops = 1;
16942     }
16943   /* Skip mod/rm byte.  */
16944   MODRM_CHECK;
16945   codep++;
16946 }
16947
16948 static void
16949 BadOp (void)
16950 {
16951   /* Throw away prefixes and 1st. opcode byte.  */
16952   codep = insn_codep + 1;
16953   oappend ("(bad)");
16954 }
16955
16956 static void
16957 REP_Fixup (int bytemode, int sizeflag)
16958 {
16959   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
16960      lods and stos.  */
16961   if (prefixes & PREFIX_REPZ)
16962     all_prefixes[last_repz_prefix] = REP_PREFIX;
16963
16964   switch (bytemode)
16965     {
16966     case al_reg:
16967     case eAX_reg:
16968     case indir_dx_reg:
16969       OP_IMREG (bytemode, sizeflag);
16970       break;
16971     case eDI_reg:
16972       OP_ESreg (bytemode, sizeflag);
16973       break;
16974     case eSI_reg:
16975       OP_DSreg (bytemode, sizeflag);
16976       break;
16977     default:
16978       abort ();
16979       break;
16980     }
16981 }
16982
16983 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
16984    "bnd".  */
16985
16986 static void
16987 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16988 {
16989   if (prefixes & PREFIX_REPNZ)
16990     all_prefixes[last_repnz_prefix] = BND_PREFIX;
16991 }
16992
16993 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
16994    "notrack".  */
16995
16996 static void
16997 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED,
16998                int sizeflag ATTRIBUTE_UNUSED)
16999 {
17000   if (active_seg_prefix == PREFIX_DS
17001       && (address_mode != mode_64bit || last_data_prefix < 0))
17002     {
17003       /* NOTRACK prefix is only valid on indirect branch instructions.
17004          NB: DATA prefix is unsupported for Intel64.  */
17005       active_seg_prefix = 0;
17006       all_prefixes[last_seg_prefix] = NOTRACK_PREFIX;
17007     }
17008 }
17009
17010 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
17011    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
17012  */
17013
17014 static void
17015 HLE_Fixup1 (int bytemode, int sizeflag)
17016 {
17017   if (modrm.mod != 3
17018       && (prefixes & PREFIX_LOCK) != 0)
17019     {
17020       if (prefixes & PREFIX_REPZ)
17021         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
17022       if (prefixes & PREFIX_REPNZ)
17023         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
17024     }
17025
17026   OP_E (bytemode, sizeflag);
17027 }
17028
17029 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
17030    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
17031  */
17032
17033 static void
17034 HLE_Fixup2 (int bytemode, int sizeflag)
17035 {
17036   if (modrm.mod != 3)
17037     {
17038       if (prefixes & PREFIX_REPZ)
17039         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
17040       if (prefixes & PREFIX_REPNZ)
17041         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
17042     }
17043
17044   OP_E (bytemode, sizeflag);
17045 }
17046
17047 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
17048    "xrelease" for memory operand.  No check for LOCK prefix.   */
17049
17050 static void
17051 HLE_Fixup3 (int bytemode, int sizeflag)
17052 {
17053   if (modrm.mod != 3
17054       && last_repz_prefix > last_repnz_prefix
17055       && (prefixes & PREFIX_REPZ) != 0)
17056     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
17057
17058   OP_E (bytemode, sizeflag);
17059 }
17060
17061 static void
17062 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
17063 {
17064   USED_REX (REX_W);
17065   if (rex & REX_W)
17066     {
17067       /* Change cmpxchg8b to cmpxchg16b.  */
17068       char *p = mnemonicendp - 2;
17069       mnemonicendp = stpcpy (p, "16b");
17070       bytemode = o_mode;
17071     }
17072   else if ((prefixes & PREFIX_LOCK) != 0)
17073     {
17074       if (prefixes & PREFIX_REPZ)
17075         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
17076       if (prefixes & PREFIX_REPNZ)
17077         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
17078     }
17079
17080   OP_M (bytemode, sizeflag);
17081 }
17082
17083 static void
17084 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
17085 {
17086   const char **names;
17087
17088   if (need_vex)
17089     {
17090       switch (vex.length)
17091         {
17092         case 128:
17093           names = names_xmm;
17094           break;
17095         case 256:
17096           names = names_ymm;
17097           break;
17098         default:
17099           abort ();
17100         }
17101     }
17102   else
17103     names = names_xmm;
17104   oappend (names[reg]);
17105 }
17106
17107 static void
17108 CRC32_Fixup (int bytemode, int sizeflag)
17109 {
17110   /* Add proper suffix to "crc32".  */
17111   char *p = mnemonicendp;
17112
17113   switch (bytemode)
17114     {
17115     case b_mode:
17116       if (intel_syntax)
17117         goto skip;
17118
17119       *p++ = 'b';
17120       break;
17121     case v_mode:
17122       if (intel_syntax)
17123         goto skip;
17124
17125       USED_REX (REX_W);
17126       if (rex & REX_W)
17127         *p++ = 'q';
17128       else
17129         {
17130           if (sizeflag & DFLAG)
17131             *p++ = 'l';
17132           else
17133             *p++ = 'w';
17134           used_prefixes |= (prefixes & PREFIX_DATA);
17135         }
17136       break;
17137     default:
17138       oappend (INTERNAL_DISASSEMBLER_ERROR);
17139       break;
17140     }
17141   mnemonicendp = p;
17142   *p = '\0';
17143
17144 skip:
17145   if (modrm.mod == 3)
17146     {
17147       int add;
17148
17149       /* Skip mod/rm byte.  */
17150       MODRM_CHECK;
17151       codep++;
17152
17153       USED_REX (REX_B);
17154       add = (rex & REX_B) ? 8 : 0;
17155       if (bytemode == b_mode)
17156         {
17157           USED_REX (0);
17158           if (rex)
17159             oappend (names8rex[modrm.rm + add]);
17160           else
17161             oappend (names8[modrm.rm + add]);
17162         }
17163       else
17164         {
17165           USED_REX (REX_W);
17166           if (rex & REX_W)
17167             oappend (names64[modrm.rm + add]);
17168           else if ((prefixes & PREFIX_DATA))
17169             oappend (names16[modrm.rm + add]);
17170           else
17171             oappend (names32[modrm.rm + add]);
17172         }
17173     }
17174   else
17175     OP_E (bytemode, sizeflag);
17176 }
17177
17178 static void
17179 FXSAVE_Fixup (int bytemode, int sizeflag)
17180 {
17181   /* Add proper suffix to "fxsave" and "fxrstor".  */
17182   USED_REX (REX_W);
17183   if (rex & REX_W)
17184     {
17185       char *p = mnemonicendp;
17186       *p++ = '6';
17187       *p++ = '4';
17188       *p = '\0';
17189       mnemonicendp = p;
17190     }
17191   OP_M (bytemode, sizeflag);
17192 }
17193
17194 static void
17195 PCMPESTR_Fixup (int bytemode, int sizeflag)
17196 {
17197   /* Add proper suffix to "{,v}pcmpestr{i,m}".  */
17198   if (!intel_syntax)
17199     {
17200       char *p = mnemonicendp;
17201
17202       USED_REX (REX_W);
17203       if (rex & REX_W)
17204         *p++ = 'q';
17205       else if (sizeflag & SUFFIX_ALWAYS)
17206         *p++ = 'l';
17207
17208       *p = '\0';
17209       mnemonicendp = p;
17210     }
17211
17212   OP_EX (bytemode, sizeflag);
17213 }
17214
17215 /* Display the destination register operand for instructions with
17216    VEX. */
17217
17218 static void
17219 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17220 {
17221   int reg;
17222   const char **names;
17223
17224   if (!need_vex)
17225     abort ();
17226
17227   if (!need_vex_reg)
17228     return;
17229
17230   reg = vex.register_specifier;
17231   if (address_mode != mode_64bit)
17232     reg &= 7;
17233   else if (vex.evex && !vex.v)
17234     reg += 16;
17235
17236   if (bytemode == vex_scalar_mode)
17237     {
17238       oappend (names_xmm[reg]);
17239       return;
17240     }
17241
17242   switch (vex.length)
17243     {
17244     case 128:
17245       switch (bytemode)
17246         {
17247         case vex_mode:
17248         case vex128_mode:
17249         case vex_vsib_q_w_dq_mode:
17250         case vex_vsib_q_w_d_mode:
17251           names = names_xmm;
17252           break;
17253         case dq_mode:
17254           if (rex & REX_W)
17255             names = names64;
17256           else
17257             names = names32;
17258           break;
17259         case mask_bd_mode:
17260         case mask_mode:
17261           if (reg > 0x7)
17262             {
17263               oappend ("(bad)");
17264               return;
17265             }
17266           names = names_mask;
17267           break;
17268         default:
17269           abort ();
17270           return;
17271         }
17272       break;
17273     case 256:
17274       switch (bytemode)
17275         {
17276         case vex_mode:
17277         case vex256_mode:
17278           names = names_ymm;
17279           break;
17280         case vex_vsib_q_w_dq_mode:
17281         case vex_vsib_q_w_d_mode:
17282           names = vex.w ? names_ymm : names_xmm;
17283           break;
17284         case mask_bd_mode:
17285         case mask_mode:
17286           if (reg > 0x7)
17287             {
17288               oappend ("(bad)");
17289               return;
17290             }
17291           names = names_mask;
17292           break;
17293         default:
17294           /* See PR binutils/20893 for a reproducer.  */
17295           oappend ("(bad)");
17296           return;
17297         }
17298       break;
17299     case 512:
17300       names = names_zmm;
17301       break;
17302     default:
17303       abort ();
17304       break;
17305     }
17306   oappend (names[reg]);
17307 }
17308
17309 /* Get the VEX immediate byte without moving codep.  */
17310
17311 static unsigned char
17312 get_vex_imm8 (int sizeflag, int opnum)
17313 {
17314   int bytes_before_imm = 0;
17315
17316   if (modrm.mod != 3)
17317     {
17318       /* There are SIB/displacement bytes.  */
17319       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
17320         {
17321           /* 32/64 bit address mode */
17322           int base = modrm.rm;
17323
17324           /* Check SIB byte.  */
17325           if (base == 4)
17326             {
17327               FETCH_DATA (the_info, codep + 1);
17328               base = *codep & 7;
17329               /* When decoding the third source, don't increase
17330                  bytes_before_imm as this has already been incremented
17331                  by one in OP_E_memory while decoding the second
17332                  source operand.  */
17333               if (opnum == 0)
17334                 bytes_before_imm++;
17335             }
17336
17337           /* Don't increase bytes_before_imm when decoding the third source,
17338              it has already been incremented by OP_E_memory while decoding
17339              the second source operand.  */
17340           if (opnum == 0)
17341             {
17342               switch (modrm.mod)
17343                 {
17344                   case 0:
17345                     /* When modrm.rm == 5 or modrm.rm == 4 and base in
17346                        SIB == 5, there is a 4 byte displacement.  */
17347                     if (base != 5)
17348                       /* No displacement. */
17349                       break;
17350                     /* Fall through.  */
17351                   case 2:
17352                     /* 4 byte displacement.  */
17353                     bytes_before_imm += 4;
17354                     break;
17355                   case 1:
17356                     /* 1 byte displacement.  */
17357                     bytes_before_imm++;
17358                     break;
17359                 }
17360             }
17361         }
17362       else
17363         {
17364           /* 16 bit address mode */
17365           /* Don't increase bytes_before_imm when decoding the third source,
17366              it has already been incremented by OP_E_memory while decoding
17367              the second source operand.  */
17368           if (opnum == 0)
17369             {
17370               switch (modrm.mod)
17371                 {
17372                 case 0:
17373                   /* When modrm.rm == 6, there is a 2 byte displacement.  */
17374                   if (modrm.rm != 6)
17375                     /* No displacement. */
17376                     break;
17377                   /* Fall through.  */
17378                 case 2:
17379                   /* 2 byte displacement.  */
17380                   bytes_before_imm += 2;
17381                   break;
17382                 case 1:
17383                   /* 1 byte displacement: when decoding the third source,
17384                      don't increase bytes_before_imm as this has already
17385                      been incremented by one in OP_E_memory while decoding
17386                      the second source operand.  */
17387                   if (opnum == 0)
17388                     bytes_before_imm++;
17389
17390                   break;
17391                 }
17392             }
17393         }
17394     }
17395
17396   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
17397   return codep [bytes_before_imm];
17398 }
17399
17400 static void
17401 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
17402 {
17403   const char **names;
17404
17405   if (reg == -1 && modrm.mod != 3)
17406     {
17407       OP_E_memory (bytemode, sizeflag);
17408       return;
17409     }
17410   else
17411     {
17412       if (reg == -1)
17413         {
17414           reg = modrm.rm;
17415           USED_REX (REX_B);
17416           if (rex & REX_B)
17417             reg += 8;
17418         }
17419       if (address_mode != mode_64bit)
17420         reg &= 7;
17421     }
17422
17423   switch (vex.length)
17424     {
17425     case 128:
17426       names = names_xmm;
17427       break;
17428     case 256:
17429       names = names_ymm;
17430       break;
17431     default:
17432       abort ();
17433     }
17434   oappend (names[reg]);
17435 }
17436
17437 static void
17438 OP_EX_VexImmW (int bytemode, int sizeflag)
17439 {
17440   int reg = -1;
17441   static unsigned char vex_imm8;
17442
17443   if (vex_w_done == 0)
17444     {
17445       vex_w_done = 1;
17446
17447       /* Skip mod/rm byte.  */
17448       MODRM_CHECK;
17449       codep++;
17450
17451       vex_imm8 = get_vex_imm8 (sizeflag, 0);
17452
17453       if (vex.w)
17454           reg = vex_imm8 >> 4;
17455
17456       OP_EX_VexReg (bytemode, sizeflag, reg);
17457     }
17458   else if (vex_w_done == 1)
17459     {
17460       vex_w_done = 2;
17461
17462       if (!vex.w)
17463           reg = vex_imm8 >> 4;
17464
17465       OP_EX_VexReg (bytemode, sizeflag, reg);
17466     }
17467   else
17468     {
17469       /* Output the imm8 directly.  */
17470       scratchbuf[0] = '$';
17471       print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
17472       oappend_maybe_intel (scratchbuf);
17473       scratchbuf[0] = '\0';
17474       codep++;
17475     }
17476 }
17477
17478 static void
17479 OP_Vex_2src (int bytemode, int sizeflag)
17480 {
17481   if (modrm.mod == 3)
17482     {
17483       int reg = modrm.rm;
17484       USED_REX (REX_B);
17485       if (rex & REX_B)
17486         reg += 8;
17487       oappend (names_xmm[reg]);
17488     }
17489   else
17490     {
17491       if (intel_syntax
17492           && (bytemode == v_mode || bytemode == v_swap_mode))
17493         {
17494           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
17495           used_prefixes |= (prefixes & PREFIX_DATA);
17496         }
17497       OP_E (bytemode, sizeflag);
17498     }
17499 }
17500
17501 static void
17502 OP_Vex_2src_1 (int bytemode, int sizeflag)
17503 {
17504   if (modrm.mod == 3)
17505     {
17506       /* Skip mod/rm byte.   */
17507       MODRM_CHECK;
17508       codep++;
17509     }
17510
17511   if (vex.w)
17512     {
17513       unsigned int reg = vex.register_specifier;
17514
17515       if (address_mode != mode_64bit)
17516         reg &= 7;
17517       oappend (names_xmm[reg]);
17518     }
17519   else
17520     OP_Vex_2src (bytemode, sizeflag);
17521 }
17522
17523 static void
17524 OP_Vex_2src_2 (int bytemode, int sizeflag)
17525 {
17526   if (vex.w)
17527     OP_Vex_2src (bytemode, sizeflag);
17528   else
17529     {
17530       unsigned int reg = vex.register_specifier;
17531
17532       if (address_mode != mode_64bit)
17533         reg &= 7;
17534       oappend (names_xmm[reg]);
17535     }
17536 }
17537
17538 static void
17539 OP_EX_VexW (int bytemode, int sizeflag)
17540 {
17541   int reg = -1;
17542
17543   if (!vex_w_done)
17544     {
17545       /* Skip mod/rm byte.  */
17546       MODRM_CHECK;
17547       codep++;
17548
17549       if (vex.w)
17550         reg = get_vex_imm8 (sizeflag, 0) >> 4;
17551     }
17552   else
17553     {
17554       if (!vex.w)
17555         reg = get_vex_imm8 (sizeflag, 1) >> 4;
17556     }
17557
17558   OP_EX_VexReg (bytemode, sizeflag, reg);
17559
17560   if (vex_w_done)
17561     codep++;
17562   vex_w_done = 1;
17563 }
17564
17565 static void
17566 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17567 {
17568   int reg;
17569   const char **names;
17570
17571   FETCH_DATA (the_info, codep + 1);
17572   reg = *codep++;
17573
17574   if (bytemode != x_mode)
17575     abort ();
17576
17577   reg >>= 4;
17578   if (address_mode != mode_64bit)
17579     reg &= 7;
17580
17581   switch (vex.length)
17582     {
17583     case 128:
17584       names = names_xmm;
17585       break;
17586     case 256:
17587       names = names_ymm;
17588       break;
17589     default:
17590       abort ();
17591     }
17592   oappend (names[reg]);
17593 }
17594
17595 static void
17596 OP_XMM_VexW (int bytemode, int sizeflag)
17597 {
17598   /* Turn off the REX.W bit since it is used for swapping operands
17599      now.  */
17600   rex &= ~REX_W;
17601   OP_XMM (bytemode, sizeflag);
17602 }
17603
17604 static void
17605 OP_EX_Vex (int bytemode, int sizeflag)
17606 {
17607   if (modrm.mod != 3)
17608     {
17609       if (vex.register_specifier != 0)
17610         BadOp ();
17611       need_vex_reg = 0;
17612     }
17613   OP_EX (bytemode, sizeflag);
17614 }
17615
17616 static void
17617 OP_XMM_Vex (int bytemode, int sizeflag)
17618 {
17619   if (modrm.mod != 3)
17620     {
17621       if (vex.register_specifier != 0)
17622         BadOp ();
17623       need_vex_reg = 0;
17624     }
17625   OP_XMM (bytemode, sizeflag);
17626 }
17627
17628 static void
17629 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17630 {
17631   switch (vex.length)
17632     {
17633     case 128:
17634       mnemonicendp = stpcpy (obuf, "vzeroupper");
17635       break;
17636     case 256:
17637       mnemonicendp = stpcpy (obuf, "vzeroall");
17638       break;
17639     default:
17640       abort ();
17641     }
17642 }
17643
17644 static struct op vex_cmp_op[] =
17645 {
17646   { STRING_COMMA_LEN ("eq") },
17647   { STRING_COMMA_LEN ("lt") },
17648   { STRING_COMMA_LEN ("le") },
17649   { STRING_COMMA_LEN ("unord") },
17650   { STRING_COMMA_LEN ("neq") },
17651   { STRING_COMMA_LEN ("nlt") },
17652   { STRING_COMMA_LEN ("nle") },
17653   { STRING_COMMA_LEN ("ord") },
17654   { STRING_COMMA_LEN ("eq_uq") },
17655   { STRING_COMMA_LEN ("nge") },
17656   { STRING_COMMA_LEN ("ngt") },
17657   { STRING_COMMA_LEN ("false") },
17658   { STRING_COMMA_LEN ("neq_oq") },
17659   { STRING_COMMA_LEN ("ge") },
17660   { STRING_COMMA_LEN ("gt") },
17661   { STRING_COMMA_LEN ("true") },
17662   { STRING_COMMA_LEN ("eq_os") },
17663   { STRING_COMMA_LEN ("lt_oq") },
17664   { STRING_COMMA_LEN ("le_oq") },
17665   { STRING_COMMA_LEN ("unord_s") },
17666   { STRING_COMMA_LEN ("neq_us") },
17667   { STRING_COMMA_LEN ("nlt_uq") },
17668   { STRING_COMMA_LEN ("nle_uq") },
17669   { STRING_COMMA_LEN ("ord_s") },
17670   { STRING_COMMA_LEN ("eq_us") },
17671   { STRING_COMMA_LEN ("nge_uq") },
17672   { STRING_COMMA_LEN ("ngt_uq") },
17673   { STRING_COMMA_LEN ("false_os") },
17674   { STRING_COMMA_LEN ("neq_os") },
17675   { STRING_COMMA_LEN ("ge_oq") },
17676   { STRING_COMMA_LEN ("gt_oq") },
17677   { STRING_COMMA_LEN ("true_us") },
17678 };
17679
17680 static void
17681 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17682 {
17683   unsigned int cmp_type;
17684
17685   FETCH_DATA (the_info, codep + 1);
17686   cmp_type = *codep++ & 0xff;
17687   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
17688     {
17689       char suffix [3];
17690       char *p = mnemonicendp - 2;
17691       suffix[0] = p[0];
17692       suffix[1] = p[1];
17693       suffix[2] = '\0';
17694       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
17695       mnemonicendp += vex_cmp_op[cmp_type].len;
17696     }
17697   else
17698     {
17699       /* We have a reserved extension byte.  Output it directly.  */
17700       scratchbuf[0] = '$';
17701       print_operand_value (scratchbuf + 1, 1, cmp_type);
17702       oappend_maybe_intel (scratchbuf);
17703       scratchbuf[0] = '\0';
17704     }
17705 }
17706
17707 static void
17708 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
17709              int sizeflag ATTRIBUTE_UNUSED)
17710 {
17711   unsigned int cmp_type;
17712
17713   if (!vex.evex)
17714     abort ();
17715
17716   FETCH_DATA (the_info, codep + 1);
17717   cmp_type = *codep++ & 0xff;
17718   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
17719      If it's the case, print suffix, otherwise - print the immediate.  */
17720   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
17721       && cmp_type != 3
17722       && cmp_type != 7)
17723     {
17724       char suffix [3];
17725       char *p = mnemonicendp - 2;
17726
17727       /* vpcmp* can have both one- and two-lettered suffix.  */
17728       if (p[0] == 'p')
17729         {
17730           p++;
17731           suffix[0] = p[0];
17732           suffix[1] = '\0';
17733         }
17734       else
17735         {
17736           suffix[0] = p[0];
17737           suffix[1] = p[1];
17738           suffix[2] = '\0';
17739         }
17740
17741       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
17742       mnemonicendp += simd_cmp_op[cmp_type].len;
17743     }
17744   else
17745     {
17746       /* We have a reserved extension byte.  Output it directly.  */
17747       scratchbuf[0] = '$';
17748       print_operand_value (scratchbuf + 1, 1, cmp_type);
17749       oappend_maybe_intel (scratchbuf);
17750       scratchbuf[0] = '\0';
17751     }
17752 }
17753
17754 static const struct op xop_cmp_op[] =
17755 {
17756   { STRING_COMMA_LEN ("lt") },
17757   { STRING_COMMA_LEN ("le") },
17758   { STRING_COMMA_LEN ("gt") },
17759   { STRING_COMMA_LEN ("ge") },
17760   { STRING_COMMA_LEN ("eq") },
17761   { STRING_COMMA_LEN ("neq") },
17762   { STRING_COMMA_LEN ("false") },
17763   { STRING_COMMA_LEN ("true") }
17764 };
17765
17766 static void
17767 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED,
17768              int sizeflag ATTRIBUTE_UNUSED)
17769 {
17770   unsigned int cmp_type;
17771
17772   FETCH_DATA (the_info, codep + 1);
17773   cmp_type = *codep++ & 0xff;
17774   if (cmp_type < ARRAY_SIZE (xop_cmp_op))
17775     {
17776       char suffix[3];
17777       char *p = mnemonicendp - 2;
17778
17779       /* vpcom* can have both one- and two-lettered suffix.  */
17780       if (p[0] == 'm')
17781         {
17782           p++;
17783           suffix[0] = p[0];
17784           suffix[1] = '\0';
17785         }
17786       else
17787         {
17788           suffix[0] = p[0];
17789           suffix[1] = p[1];
17790           suffix[2] = '\0';
17791         }
17792
17793       sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix);
17794       mnemonicendp += xop_cmp_op[cmp_type].len;
17795     }
17796   else
17797     {
17798       /* We have a reserved extension byte.  Output it directly.  */
17799       scratchbuf[0] = '$';
17800       print_operand_value (scratchbuf + 1, 1, cmp_type);
17801       oappend_maybe_intel (scratchbuf);
17802       scratchbuf[0] = '\0';
17803     }
17804 }
17805
17806 static const struct op pclmul_op[] =
17807 {
17808   { STRING_COMMA_LEN ("lql") },
17809   { STRING_COMMA_LEN ("hql") },
17810   { STRING_COMMA_LEN ("lqh") },
17811   { STRING_COMMA_LEN ("hqh") }
17812 };
17813
17814 static void
17815 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
17816               int sizeflag ATTRIBUTE_UNUSED)
17817 {
17818   unsigned int pclmul_type;
17819
17820   FETCH_DATA (the_info, codep + 1);
17821   pclmul_type = *codep++ & 0xff;
17822   switch (pclmul_type)
17823     {
17824     case 0x10:
17825       pclmul_type = 2;
17826       break;
17827     case 0x11:
17828       pclmul_type = 3;
17829       break;
17830     default:
17831       break;
17832     }
17833   if (pclmul_type < ARRAY_SIZE (pclmul_op))
17834     {
17835       char suffix [4];
17836       char *p = mnemonicendp - 3;
17837       suffix[0] = p[0];
17838       suffix[1] = p[1];
17839       suffix[2] = p[2];
17840       suffix[3] = '\0';
17841       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
17842       mnemonicendp += pclmul_op[pclmul_type].len;
17843     }
17844   else
17845     {
17846       /* We have a reserved extension byte.  Output it directly.  */
17847       scratchbuf[0] = '$';
17848       print_operand_value (scratchbuf + 1, 1, pclmul_type);
17849       oappend_maybe_intel (scratchbuf);
17850       scratchbuf[0] = '\0';
17851     }
17852 }
17853
17854 static void
17855 MOVBE_Fixup (int bytemode, int sizeflag)
17856 {
17857   /* Add proper suffix to "movbe".  */
17858   char *p = mnemonicendp;
17859
17860   switch (bytemode)
17861     {
17862     case v_mode:
17863       if (intel_syntax)
17864         goto skip;
17865
17866       USED_REX (REX_W);
17867       if (sizeflag & SUFFIX_ALWAYS)
17868         {
17869           if (rex & REX_W)
17870             *p++ = 'q';
17871           else
17872             {
17873               if (sizeflag & DFLAG)
17874                 *p++ = 'l';
17875               else
17876                 *p++ = 'w';
17877               used_prefixes |= (prefixes & PREFIX_DATA);
17878             }
17879         }
17880       break;
17881     default:
17882       oappend (INTERNAL_DISASSEMBLER_ERROR);
17883       break;
17884     }
17885   mnemonicendp = p;
17886   *p = '\0';
17887
17888 skip:
17889   OP_M (bytemode, sizeflag);
17890 }
17891
17892 static void
17893 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17894 {
17895   int reg;
17896   const char **names;
17897
17898   /* Skip mod/rm byte.  */
17899   MODRM_CHECK;
17900   codep++;
17901
17902   if (rex & REX_W)
17903     names = names64;
17904   else
17905     names = names32;
17906
17907   reg = modrm.rm;
17908   USED_REX (REX_B);
17909   if (rex & REX_B)
17910     reg += 8;
17911
17912   oappend (names[reg]);
17913 }
17914
17915 static void
17916 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17917 {
17918   const char **names;
17919   unsigned int reg = vex.register_specifier;
17920
17921   if (rex & REX_W)
17922     names = names64;
17923   else
17924     names = names32;
17925
17926   if (address_mode != mode_64bit)
17927     reg &= 7;
17928   oappend (names[reg]);
17929 }
17930
17931 static void
17932 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17933 {
17934   if (!vex.evex
17935       || (bytemode != mask_mode && bytemode != mask_bd_mode))
17936     abort ();
17937
17938   USED_REX (REX_R);
17939   if ((rex & REX_R) != 0 || !vex.r)
17940     {
17941       BadOp ();
17942       return;
17943     }
17944
17945   oappend (names_mask [modrm.reg]);
17946 }
17947
17948 static void
17949 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17950 {
17951   if (!vex.evex
17952       || (bytemode != evex_rounding_mode
17953           && bytemode != evex_sae_mode))
17954     abort ();
17955   if (modrm.mod == 3 && vex.b)
17956     switch (bytemode)
17957       {
17958       case evex_rounding_mode:
17959         oappend (names_rounding[vex.ll]);
17960         break;
17961       case evex_sae_mode:
17962         oappend ("{sae}");
17963         break;
17964       default:
17965         break;
17966       }
17967 }