opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2017 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "disassemble.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40
  41 #include <setjmp.h>
  42
  43 static int print_insn (bfd_vma, disassemble_info *);
  44 static void dofloat (int);
  45 static void OP_ST (int, int);
  46 static void OP_STi (int, int);
  47 static int putop (const char *, int);
  48 static void oappend (const char *);
  49 static void append_seg (void);
  50 static void OP_indirE (int, int);
  51 static void print_operand_value (char *, int, bfd_vma);
  52 static void OP_E_register (int, int);
  53 static void OP_E_memory (int, int);
  54 static void print_displacement (char *, bfd_vma);
  55 static void OP_E (int, int);
  56 static void OP_G (int, int);
  57 static bfd_vma get64 (void);
  58 static bfd_signed_vma get32 (void);
  59 static bfd_signed_vma get32s (void);
  60 static int get16 (void);
  61 static void set_op (bfd_vma, int);
  62 static void OP_Skip_MODRM (int, int);
  63 static void OP_REG (int, int);
  64 static void OP_IMREG (int, int);
  65 static void OP_I (int, int);
  66 static void OP_I64 (int, int);
  67 static void OP_sI (int, int);
  68 static void OP_J (int, int);
  69 static void OP_SEG (int, int);
  70 static void OP_DIR (int, int);
  71 static void OP_OFF (int, int);
  72 static void OP_OFF64 (int, int);
  73 static void ptr_reg (int, int);
  74 static void OP_ESreg (int, int);
  75 static void OP_DSreg (int, int);
  76 static void OP_C (int, int);
  77 static void OP_D (int, int);
  78 static void OP_T (int, int);
  79 static void OP_R (int, int);
  80 static void OP_MMX (int, int);
  81 static void OP_XMM (int, int);
  82 static void OP_EM (int, int);
  83 static void OP_EX (int, int);
  84 static void OP_EMC (int,int);
  85 static void OP_MXC (int,int);
  86 static void OP_MS (int, int);
  87 static void OP_XS (int, int);
  88 static void OP_M (int, int);
  89 static void OP_VEX (int, int);
  90 static void OP_EX_Vex (int, int);
  91 static void OP_EX_VexW (int, int);
  92 static void OP_EX_VexImmW (int, int);
  93 static void OP_XMM_Vex (int, int);
  94 static void OP_XMM_VexW (int, int);
  95 static void OP_Rounding (int, int);
  96 static void OP_REG_VexI4 (int, int);
  97 static void PCLMUL_Fixup (int, int);
  98 static void VEXI4_Fixup (int, int);
  99 static void VZERO_Fixup (int, int);
 100 static void VCMP_Fixup (int, int);
 101 static void VPCMP_Fixup (int, int);
 102 static void OP_0f07 (int, int);
 103 static void OP_Monitor (int, int);
 104 static void OP_Mwait (int, int);
 105 static void OP_Mwaitx (int, int);
 106 static void NOP_Fixup1 (int, int);
 107 static void NOP_Fixup2 (int, int);
 108 static void OP_3DNowSuffix (int, int);
 109 static void CMP_Fixup (int, int);
 110 static void BadOp (void);
 111 static void REP_Fixup (int, int);
 112 static void BND_Fixup (int, int);
 113 static void NOTRACK_Fixup (int, int);
 114 static void HLE_Fixup1 (int, int);
 115 static void HLE_Fixup2 (int, int);
 116 static void HLE_Fixup3 (int, int);
 117 static void CMPXCHG8B_Fixup (int, int);
 118 static void XMM_Fixup (int, int);
 119 static void CRC32_Fixup (int, int);
 120 static void FXSAVE_Fixup (int, int);
 121 static void PCMPESTR_Fixup (int, int);
 122 static void OP_LWPCB_E (int, int);
 123 static void OP_LWP_E (int, int);
 124 static void OP_Vex_2src_1 (int, int);
 125 static void OP_Vex_2src_2 (int, int);
 126
 127 static void MOVBE_Fixup (int, int);
 128
 129 static void OP_Mask (int, int);
 130
 131 struct dis_private {
 132   /* Points to first byte not fetched.  */
 133   bfd_byte *max_fetched;
 134   bfd_byte the_buffer[MAX_MNEM_SIZE];
 135   bfd_vma insn_start;
 136   int orig_sizeflag;
 137   OPCODES_SIGJMP_BUF bailout;
 138 };
 139
 140 enum address_mode
 141 {
 142   mode_16bit,
 143   mode_32bit,
 144   mode_64bit
 145 };
 146
 147 enum address_mode address_mode;
 148
 149 /* Flags for the prefixes for the current instruction.  See below.  */
 150 static int prefixes;
 151
 152 /* REX prefix the current instruction.  See below.  */
 153 static int rex;
 154 /* Bits of REX we've already used.  */
 155 static int rex_used;
 156 /* REX bits in original REX prefix ignored.  */
 157 static int rex_ignored;
 158 /* Mark parts used in the REX prefix.  When we are testing for
 159    empty prefix (for 8bit register REX extension), just mask it
 160    out.  Otherwise test for REX bit is excuse for existence of REX
 161    only in case value is nonzero.  */
 162 #define USED_REX(value)                                 \
 163   {                                                     \
 164     if (value)                                          \
 165       {                                                 \
 166         if ((rex & value))                              \
 167           rex_used |= (value) | REX_OPCODE;             \
 168       }                                                 \
 169     else                                                \
 170       rex_used |= REX_OPCODE;                           \
 171   }
 172
 173 /* Flags for prefixes which we somehow handled when printing the
 174    current instruction.  */
 175 static int used_prefixes;
 176
 177 /* Flags stored in PREFIXES.  */
 178 #define PREFIX_REPZ 1
 179 #define PREFIX_REPNZ 2
 180 #define PREFIX_LOCK 4
 181 #define PREFIX_CS 8
 182 #define PREFIX_SS 0x10
 183 #define PREFIX_DS 0x20
 184 #define PREFIX_ES 0x40
 185 #define PREFIX_FS 0x80
 186 #define PREFIX_GS 0x100
 187 #define PREFIX_DATA 0x200
 188 #define PREFIX_ADDR 0x400
 189 #define PREFIX_FWAIT 0x800
 190
 191 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 192    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 193    on error.  */
 194 #define FETCH_DATA(info, addr) \
 195   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 196    ? 1 : fetch_data ((info), (addr)))
 197
 198 static int
 199 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 200 {
 201   int status;
 202   struct dis_private *priv = (struct dis_private *) info->private_data;
 203   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 204
 205   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 206     status = (*info->read_memory_func) (start,
 207                                         priv->max_fetched,
 208                                         addr - priv->max_fetched,
 209                                         info);
 210   else
 211     status = -1;
 212   if (status != 0)
 213     {
 214       /* If we did manage to read at least one byte, then
 215          print_insn_i386 will do something sensible.  Otherwise, print
 216          an error.  We do that here because this is where we know
 217          STATUS.  */
 218       if (priv->max_fetched == priv->the_buffer)
 219         (*info->memory_error_func) (status, start, info);
 220       OPCODES_SIGLONGJMP (priv->bailout, 1);
 221     }
 222   else
 223     priv->max_fetched = addr;
 224   return 1;
 225 }
 226
 227 /* Possible values for prefix requirement.  */
 228 #define PREFIX_IGNORED_SHIFT    16
 229 #define PREFIX_IGNORED_REPZ     (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
 230 #define PREFIX_IGNORED_REPNZ    (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
 231 #define PREFIX_IGNORED_DATA     (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
 232 #define PREFIX_IGNORED_ADDR     (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
 233 #define PREFIX_IGNORED_LOCK     (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
 234
 235 /* Opcode prefixes.  */
 236 #define PREFIX_OPCODE           (PREFIX_REPZ \
 237                                  | PREFIX_REPNZ \
 238                                  | PREFIX_DATA)
 239
 240 /* Prefixes ignored.  */
 241 #define PREFIX_IGNORED          (PREFIX_IGNORED_REPZ \
 242                                  | PREFIX_IGNORED_REPNZ \
 243                                  | PREFIX_IGNORED_DATA)
 244
 245 #define XX { NULL, 0 }
 246 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
 247
 248 #define Eb { OP_E, b_mode }
 249 #define Ebnd { OP_E, bnd_mode }
 250 #define EbS { OP_E, b_swap_mode }
 251 #define Ev { OP_E, v_mode }
 252 #define Ev_bnd { OP_E, v_bnd_mode }
 253 #define EvS { OP_E, v_swap_mode }
 254 #define Ed { OP_E, d_mode }
 255 #define Edq { OP_E, dq_mode }
 256 #define Edqw { OP_E, dqw_mode }
 257 #define Edqb { OP_E, dqb_mode }
 258 #define Edb { OP_E, db_mode }
 259 #define Edw { OP_E, dw_mode }
 260 #define Edqd { OP_E, dqd_mode }
 261 #define Eq { OP_E, q_mode }
 262 #define indirEv { OP_indirE, indir_v_mode }
 263 #define indirEp { OP_indirE, f_mode }
 264 #define stackEv { OP_E, stack_v_mode }
 265 #define Em { OP_E, m_mode }
 266 #define Ew { OP_E, w_mode }
 267 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 268 #define Ma { OP_M, a_mode }
 269 #define Mb { OP_M, b_mode }
 270 #define Md { OP_M, d_mode }
 271 #define Mo { OP_M, o_mode }
 272 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 273 #define Mq { OP_M, q_mode }
 274 #define Mx { OP_M, x_mode }
 275 #define Mxmm { OP_M, xmm_mode }
 276 #define Gb { OP_G, b_mode }
 277 #define Gbnd { OP_G, bnd_mode }
 278 #define Gv { OP_G, v_mode }
 279 #define Gd { OP_G, d_mode }
 280 #define Gdq { OP_G, dq_mode }
 281 #define Gm { OP_G, m_mode }
 282 #define Gw { OP_G, w_mode }
 283 #define Rd { OP_R, d_mode }
 284 #define Rdq { OP_R, dq_mode }
 285 #define Rm { OP_R, m_mode }
 286 #define Ib { OP_I, b_mode }
 287 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 288 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 289 #define Iv { OP_I, v_mode }
 290 #define sIv { OP_sI, v_mode }
 291 #define Iq { OP_I, q_mode }
 292 #define Iv64 { OP_I64, v_mode }
 293 #define Iw { OP_I, w_mode }
 294 #define I1 { OP_I, const_1_mode }
 295 #define Jb { OP_J, b_mode }
 296 #define Jv { OP_J, v_mode }
 297 #define Cm { OP_C, m_mode }
 298 #define Dm { OP_D, m_mode }
 299 #define Td { OP_T, d_mode }
 300 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 301
 302 #define RMeAX { OP_REG, eAX_reg }
 303 #define RMeBX { OP_REG, eBX_reg }
 304 #define RMeCX { OP_REG, eCX_reg }
 305 #define RMeDX { OP_REG, eDX_reg }
 306 #define RMeSP { OP_REG, eSP_reg }
 307 #define RMeBP { OP_REG, eBP_reg }
 308 #define RMeSI { OP_REG, eSI_reg }
 309 #define RMeDI { OP_REG, eDI_reg }
 310 #define RMrAX { OP_REG, rAX_reg }
 311 #define RMrBX { OP_REG, rBX_reg }
 312 #define RMrCX { OP_REG, rCX_reg }
 313 #define RMrDX { OP_REG, rDX_reg }
 314 #define RMrSP { OP_REG, rSP_reg }
 315 #define RMrBP { OP_REG, rBP_reg }
 316 #define RMrSI { OP_REG, rSI_reg }
 317 #define RMrDI { OP_REG, rDI_reg }
 318 #define RMAL { OP_REG, al_reg }
 319 #define RMCL { OP_REG, cl_reg }
 320 #define RMDL { OP_REG, dl_reg }
 321 #define RMBL { OP_REG, bl_reg }
 322 #define RMAH { OP_REG, ah_reg }
 323 #define RMCH { OP_REG, ch_reg }
 324 #define RMDH { OP_REG, dh_reg }
 325 #define RMBH { OP_REG, bh_reg }
 326 #define RMAX { OP_REG, ax_reg }
 327 #define RMDX { OP_REG, dx_reg }
 328
 329 #define eAX { OP_IMREG, eAX_reg }
 330 #define eBX { OP_IMREG, eBX_reg }
 331 #define eCX { OP_IMREG, eCX_reg }
 332 #define eDX { OP_IMREG, eDX_reg }
 333 #define eSP { OP_IMREG, eSP_reg }
 334 #define eBP { OP_IMREG, eBP_reg }
 335 #define eSI { OP_IMREG, eSI_reg }
 336 #define eDI { OP_IMREG, eDI_reg }
 337 #define AL { OP_IMREG, al_reg }
 338 #define CL { OP_IMREG, cl_reg }
 339 #define DL { OP_IMREG, dl_reg }
 340 #define BL { OP_IMREG, bl_reg }
 341 #define AH { OP_IMREG, ah_reg }
 342 #define CH { OP_IMREG, ch_reg }
 343 #define DH { OP_IMREG, dh_reg }
 344 #define BH { OP_IMREG, bh_reg }
 345 #define AX { OP_IMREG, ax_reg }
 346 #define DX { OP_IMREG, dx_reg }
 347 #define zAX { OP_IMREG, z_mode_ax_reg }
 348 #define indirDX { OP_IMREG, indir_dx_reg }
 349
 350 #define Sw { OP_SEG, w_mode }
 351 #define Sv { OP_SEG, v_mode }
 352 #define Ap { OP_DIR, 0 }
 353 #define Ob { OP_OFF64, b_mode }
 354 #define Ov { OP_OFF64, v_mode }
 355 #define Xb { OP_DSreg, eSI_reg }
 356 #define Xv { OP_DSreg, eSI_reg }
 357 #define Xz { OP_DSreg, eSI_reg }
 358 #define Yb { OP_ESreg, eDI_reg }
 359 #define Yv { OP_ESreg, eDI_reg }
 360 #define DSBX { OP_DSreg, eBX_reg }
 361
 362 #define es { OP_REG, es_reg }
 363 #define ss { OP_REG, ss_reg }
 364 #define cs { OP_REG, cs_reg }
 365 #define ds { OP_REG, ds_reg }
 366 #define fs { OP_REG, fs_reg }
 367 #define gs { OP_REG, gs_reg }
 368
 369 #define MX { OP_MMX, 0 }
 370 #define XM { OP_XMM, 0 }
 371 #define XMScalar { OP_XMM, scalar_mode }
 372 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 373 #define XMM { OP_XMM, xmm_mode }
 374 #define XMxmmq { OP_XMM, xmmq_mode }
 375 #define EM { OP_EM, v_mode }
 376 #define EMS { OP_EM, v_swap_mode }
 377 #define EMd { OP_EM, d_mode }
 378 #define EMx { OP_EM, x_mode }
 379 #define EXbScalar { OP_EX, b_scalar_mode }
 380 #define EXw { OP_EX, w_mode }
 381 #define EXwScalar { OP_EX, w_scalar_mode }
 382 #define EXd { OP_EX, d_mode }
 383 #define EXdScalar { OP_EX, d_scalar_mode }
 384 #define EXdS { OP_EX, d_swap_mode }
 385 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
 386 #define EXq { OP_EX, q_mode }
 387 #define EXqScalar { OP_EX, q_scalar_mode }
 388 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
 389 #define EXqS { OP_EX, q_swap_mode }
 390 #define EXx { OP_EX, x_mode }
 391 #define EXxS { OP_EX, x_swap_mode }
 392 #define EXxmm { OP_EX, xmm_mode }
 393 #define EXymm { OP_EX, ymm_mode }
 394 #define EXxmmq { OP_EX, xmmq_mode }
 395 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 396 #define EXxmm_mb { OP_EX, xmm_mb_mode }
 397 #define EXxmm_mw { OP_EX, xmm_mw_mode }
 398 #define EXxmm_md { OP_EX, xmm_md_mode }
 399 #define EXxmm_mq { OP_EX, xmm_mq_mode }
 400 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
 401 #define EXxmmdw { OP_EX, xmmdw_mode }
 402 #define EXxmmqd { OP_EX, xmmqd_mode }
 403 #define EXymmq { OP_EX, ymmq_mode }
 404 #define EXVexWdq { OP_EX, vex_w_dq_mode }
 405 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 406 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 407 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 408 #define MS { OP_MS, v_mode }
 409 #define XS { OP_XS, v_mode }
 410 #define EMCq { OP_EMC, q_mode }
 411 #define MXC { OP_MXC, 0 }
 412 #define OPSUF { OP_3DNowSuffix, 0 }
 413 #define CMP { CMP_Fixup, 0 }
 414 #define XMM0 { XMM_Fixup, 0 }
 415 #define FXSAVE { FXSAVE_Fixup, 0 }
 416 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
 417 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
 418
 419 #define Vex { OP_VEX, vex_mode }
 420 #define VexScalar { OP_VEX, vex_scalar_mode }
 421 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 422 #define Vex128 { OP_VEX, vex128_mode }
 423 #define Vex256 { OP_VEX, vex256_mode }
 424 #define VexGdq { OP_VEX, dq_mode }
 425 #define VexI4 { VEXI4_Fixup, 0}
 426 #define EXdVex { OP_EX_Vex, d_mode }
 427 #define EXdVexS { OP_EX_Vex, d_swap_mode }
 428 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
 429 #define EXqVex { OP_EX_Vex, q_mode }
 430 #define EXqVexS { OP_EX_Vex, q_swap_mode }
 431 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
 432 #define EXVexW { OP_EX_VexW, x_mode }
 433 #define EXdVexW { OP_EX_VexW, d_mode }
 434 #define EXqVexW { OP_EX_VexW, q_mode }
 435 #define EXVexImmW { OP_EX_VexImmW, x_mode }
 436 #define XMVex { OP_XMM_Vex, 0 }
 437 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
 438 #define XMVexW { OP_XMM_VexW, 0 }
 439 #define XMVexI4 { OP_REG_VexI4, x_mode }
 440 #define PCLMUL { PCLMUL_Fixup, 0 }
 441 #define VZERO { VZERO_Fixup, 0 }
 442 #define VCMP { VCMP_Fixup, 0 }
 443 #define VPCMP { VPCMP_Fixup, 0 }
 444
 445 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 446 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 447
 448 #define XMask { OP_Mask, mask_mode }
 449 #define MaskG { OP_G, mask_mode }
 450 #define MaskE { OP_E, mask_mode }
 451 #define MaskBDE { OP_E, mask_bd_mode }
 452 #define MaskR { OP_R, mask_mode }
 453 #define MaskVex { OP_VEX, mask_mode }
 454
 455 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 456 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
 457 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 458 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
 459
 460 /* Used handle "rep" prefix for string instructions.  */
 461 #define Xbr { REP_Fixup, eSI_reg }
 462 #define Xvr { REP_Fixup, eSI_reg }
 463 #define Ybr { REP_Fixup, eDI_reg }
 464 #define Yvr { REP_Fixup, eDI_reg }
 465 #define Yzr { REP_Fixup, eDI_reg }
 466 #define indirDXr { REP_Fixup, indir_dx_reg }
 467 #define ALr { REP_Fixup, al_reg }
 468 #define eAXr { REP_Fixup, eAX_reg }
 469
 470 /* Used handle HLE prefix for lockable instructions.  */
 471 #define Ebh1 { HLE_Fixup1, b_mode }
 472 #define Evh1 { HLE_Fixup1, v_mode }
 473 #define Ebh2 { HLE_Fixup2, b_mode }
 474 #define Evh2 { HLE_Fixup2, v_mode }
 475 #define Ebh3 { HLE_Fixup3, b_mode }
 476 #define Evh3 { HLE_Fixup3, v_mode }
 477
 478 #define BND { BND_Fixup, 0 }
 479 #define NOTRACK { NOTRACK_Fixup, 0 }
 480
 481 #define cond_jump_flag { NULL, cond_jump_mode }
 482 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 483
 484 /* bits in sizeflag */
 485 #define SUFFIX_ALWAYS 4
 486 #define AFLAG 2
 487 #define DFLAG 1
 488
 489 enum
 490 {
 491   /* byte operand */
 492   b_mode = 1,
 493   /* byte operand with operand swapped */
 494   b_swap_mode,
 495   /* byte operand, sign extend like 'T' suffix */
 496   b_T_mode,
 497   /* operand size depends on prefixes */
 498   v_mode,
 499   /* operand size depends on prefixes with operand swapped */
 500   v_swap_mode,
 501   /* word operand */
 502   w_mode,
 503   /* double word operand  */
 504   d_mode,
 505   /* double word operand with operand swapped */
 506   d_swap_mode,
 507   /* quad word operand */
 508   q_mode,
 509   /* quad word operand with operand swapped */
 510   q_swap_mode,
 511   /* ten-byte operand */
 512   t_mode,
 513   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 514      broadcast enabled.  */
 515   x_mode,
 516   /* Similar to x_mode, but with different EVEX mem shifts.  */
 517   evex_x_gscat_mode,
 518   /* Similar to x_mode, but with disabled broadcast.  */
 519   evex_x_nobcst_mode,
 520   /* Similar to x_mode, but with operands swapped and disabled broadcast
 521      in EVEX.  */
 522   x_swap_mode,
 523   /* 16-byte XMM operand */
 524   xmm_mode,
 525   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 526      memory operand (depending on vector length).  Broadcast isn't
 527      allowed.  */
 528   xmmq_mode,
 529   /* Same as xmmq_mode, but broadcast is allowed.  */
 530   evex_half_bcst_xmmq_mode,
 531   /* XMM register or byte memory operand */
 532   xmm_mb_mode,
 533   /* XMM register or word memory operand */
 534   xmm_mw_mode,
 535   /* XMM register or double word memory operand */
 536   xmm_md_mode,
 537   /* XMM register or quad word memory operand */
 538   xmm_mq_mode,
 539   /* XMM register or double/quad word memory operand, depending on
 540      VEX.W.  */
 541   xmm_mdq_mode,
 542   /* 16-byte XMM, word, double word or quad word operand.  */
 543   xmmdw_mode,
 544   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 545   xmmqd_mode,
 546   /* 32-byte YMM operand */
 547   ymm_mode,
 548   /* quad word, ymmword or zmmword memory operand.  */
 549   ymmq_mode,
 550   /* 32-byte YMM or 16-byte word operand */
 551   ymmxmm_mode,
 552   /* d_mode in 32bit, q_mode in 64bit mode.  */
 553   m_mode,
 554   /* pair of v_mode operands */
 555   a_mode,
 556   cond_jump_mode,
 557   loop_jcxz_mode,
 558   v_bnd_mode,
 559   /* operand size depends on REX prefixes.  */
 560   dq_mode,
 561   /* registers like dq_mode, memory like w_mode.  */
 562   dqw_mode,
 563   bnd_mode,
 564   /* 4- or 6-byte pointer operand */
 565   f_mode,
 566   const_1_mode,
 567   /* v_mode for indirect branch opcodes.  */
 568   indir_v_mode,
 569   /* v_mode for stack-related opcodes.  */
 570   stack_v_mode,
 571   /* non-quad operand size depends on prefixes */
 572   z_mode,
 573   /* 16-byte operand */
 574   o_mode,
 575   /* registers like dq_mode, memory like b_mode.  */
 576   dqb_mode,
 577   /* registers like d_mode, memory like b_mode.  */
 578   db_mode,
 579   /* registers like d_mode, memory like w_mode.  */
 580   dw_mode,
 581   /* registers like dq_mode, memory like d_mode.  */
 582   dqd_mode,
 583   /* normal vex mode */
 584   vex_mode,
 585   /* 128bit vex mode */
 586   vex128_mode,
 587   /* 256bit vex mode */
 588   vex256_mode,
 589   /* operand size depends on the VEX.W bit.  */
 590   vex_w_dq_mode,
 591
 592   /* Similar to vex_w_dq_mode, with VSIB dword indices.  */
 593   vex_vsib_d_w_dq_mode,
 594   /* Similar to vex_vsib_d_w_dq_mode, with smaller memory.  */
 595   vex_vsib_d_w_d_mode,
 596   /* Similar to vex_w_dq_mode, with VSIB qword indices.  */
 597   vex_vsib_q_w_dq_mode,
 598   /* Similar to vex_vsib_q_w_dq_mode, with smaller memory.  */
 599   vex_vsib_q_w_d_mode,
 600
 601   /* scalar, ignore vector length.  */
 602   scalar_mode,
 603   /* like b_mode, ignore vector length.  */
 604   b_scalar_mode,
 605   /* like w_mode, ignore vector length.  */
 606   w_scalar_mode,
 607   /* like d_mode, ignore vector length.  */
 608   d_scalar_mode,
 609   /* like d_swap_mode, ignore vector length.  */
 610   d_scalar_swap_mode,
 611   /* like q_mode, ignore vector length.  */
 612   q_scalar_mode,
 613   /* like q_swap_mode, ignore vector length.  */
 614   q_scalar_swap_mode,
 615   /* like vex_mode, ignore vector length.  */
 616   vex_scalar_mode,
 617   /* like vex_w_dq_mode, ignore vector length.  */
 618   vex_scalar_w_dq_mode,
 619
 620   /* Static rounding.  */
 621   evex_rounding_mode,
 622   /* Supress all exceptions.  */
 623   evex_sae_mode,
 624
 625   /* Mask register operand.  */
 626   mask_mode,
 627   /* Mask register operand.  */
 628   mask_bd_mode,
 629
 630   es_reg,
 631   cs_reg,
 632   ss_reg,
 633   ds_reg,
 634   fs_reg,
 635   gs_reg,
 636
 637   eAX_reg,
 638   eCX_reg,
 639   eDX_reg,
 640   eBX_reg,
 641   eSP_reg,
 642   eBP_reg,
 643   eSI_reg,
 644   eDI_reg,
 645
 646   al_reg,
 647   cl_reg,
 648   dl_reg,
 649   bl_reg,
 650   ah_reg,
 651   ch_reg,
 652   dh_reg,
 653   bh_reg,
 654
 655   ax_reg,
 656   cx_reg,
 657   dx_reg,
 658   bx_reg,
 659   sp_reg,
 660   bp_reg,
 661   si_reg,
 662   di_reg,
 663
 664   rAX_reg,
 665   rCX_reg,
 666   rDX_reg,
 667   rBX_reg,
 668   rSP_reg,
 669   rBP_reg,
 670   rSI_reg,
 671   rDI_reg,
 672
 673   z_mode_ax_reg,
 674   indir_dx_reg
 675 };
 676
 677 enum
 678 {
 679   FLOATCODE = 1,
 680   USE_REG_TABLE,
 681   USE_MOD_TABLE,
 682   USE_RM_TABLE,
 683   USE_PREFIX_TABLE,
 684   USE_X86_64_TABLE,
 685   USE_3BYTE_TABLE,
 686   USE_XOP_8F_TABLE,
 687   USE_VEX_C4_TABLE,
 688   USE_VEX_C5_TABLE,
 689   USE_VEX_LEN_TABLE,
 690   USE_VEX_W_TABLE,
 691   USE_EVEX_TABLE
 692 };
 693
 694 #define FLOAT                   NULL, { { NULL, FLOATCODE } }, 0
 695
 696 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }, 0
 697 #define DIS386_PREFIX(T, I, P)          NULL, { { NULL, (T)}, { NULL,  (I) } }, P
 698 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 699 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 700 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 701 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 702 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 703 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 704 #define THREE_BYTE_TABLE_PREFIX(I, P)   DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
 705 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 706 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 707 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 708 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 709 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 710 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 711
 712 enum
 713 {
 714   REG_80 = 0,
 715   REG_81,
 716   REG_83,
 717   REG_8F,
 718   REG_C0,
 719   REG_C1,
 720   REG_C6,
 721   REG_C7,
 722   REG_D0,
 723   REG_D1,
 724   REG_D2,
 725   REG_D3,
 726   REG_F6,
 727   REG_F7,
 728   REG_FE,
 729   REG_FF,
 730   REG_0F00,
 731   REG_0F01,
 732   REG_0F0D,
 733   REG_0F18,
 734   REG_0F1E_MOD_3,
 735   REG_0F71,
 736   REG_0F72,
 737   REG_0F73,
 738   REG_0FA6,
 739   REG_0FA7,
 740   REG_0FAE,
 741   REG_0FBA,
 742   REG_0FC7,
 743   REG_VEX_0F71,
 744   REG_VEX_0F72,
 745   REG_VEX_0F73,
 746   REG_VEX_0FAE,
 747   REG_VEX_0F38F3,
 748   REG_XOP_LWPCB,
 749   REG_XOP_LWP,
 750   REG_XOP_TBM_01,
 751   REG_XOP_TBM_02,
 752
 753   REG_EVEX_0F71,
 754   REG_EVEX_0F72,
 755   REG_EVEX_0F73,
 756   REG_EVEX_0F38C6,
 757   REG_EVEX_0F38C7
 758 };
 759
 760 enum
 761 {
 762   MOD_8D = 0,
 763   MOD_C6_REG_7,
 764   MOD_C7_REG_7,
 765   MOD_FF_REG_3,
 766   MOD_FF_REG_5,
 767   MOD_0F01_REG_0,
 768   MOD_0F01_REG_1,
 769   MOD_0F01_REG_2,
 770   MOD_0F01_REG_3,
 771   MOD_0F01_REG_5,
 772   MOD_0F01_REG_7,
 773   MOD_0F12_PREFIX_0,
 774   MOD_0F13,
 775   MOD_0F16_PREFIX_0,
 776   MOD_0F17,
 777   MOD_0F18_REG_0,
 778   MOD_0F18_REG_1,
 779   MOD_0F18_REG_2,
 780   MOD_0F18_REG_3,
 781   MOD_0F18_REG_4,
 782   MOD_0F18_REG_5,
 783   MOD_0F18_REG_6,
 784   MOD_0F18_REG_7,
 785   MOD_0F1A_PREFIX_0,
 786   MOD_0F1B_PREFIX_0,
 787   MOD_0F1B_PREFIX_1,
 788   MOD_0F1E_PREFIX_1,
 789   MOD_0F24,
 790   MOD_0F26,
 791   MOD_0F2B_PREFIX_0,
 792   MOD_0F2B_PREFIX_1,
 793   MOD_0F2B_PREFIX_2,
 794   MOD_0F2B_PREFIX_3,
 795   MOD_0F51,
 796   MOD_0F71_REG_2,
 797   MOD_0F71_REG_4,
 798   MOD_0F71_REG_6,
 799   MOD_0F72_REG_2,
 800   MOD_0F72_REG_4,
 801   MOD_0F72_REG_6,
 802   MOD_0F73_REG_2,
 803   MOD_0F73_REG_3,
 804   MOD_0F73_REG_6,
 805   MOD_0F73_REG_7,
 806   MOD_0FAE_REG_0,
 807   MOD_0FAE_REG_1,
 808   MOD_0FAE_REG_2,
 809   MOD_0FAE_REG_3,
 810   MOD_0FAE_REG_4,
 811   MOD_0FAE_REG_5,
 812   MOD_0FAE_REG_6,
 813   MOD_0FAE_REG_7,
 814   MOD_0FB2,
 815   MOD_0FB4,
 816   MOD_0FB5,
 817   MOD_0FC3,
 818   MOD_0FC7_REG_3,
 819   MOD_0FC7_REG_4,
 820   MOD_0FC7_REG_5,
 821   MOD_0FC7_REG_6,
 822   MOD_0FC7_REG_7,
 823   MOD_0FD7,
 824   MOD_0FE7_PREFIX_2,
 825   MOD_0FF0_PREFIX_3,
 826   MOD_0F382A_PREFIX_2,
 827   MOD_0F38F5_PREFIX_2,
 828   MOD_0F38F6_PREFIX_0,
 829   MOD_62_32BIT,
 830   MOD_C4_32BIT,
 831   MOD_C5_32BIT,
 832   MOD_VEX_0F12_PREFIX_0,
 833   MOD_VEX_0F13,
 834   MOD_VEX_0F16_PREFIX_0,
 835   MOD_VEX_0F17,
 836   MOD_VEX_0F2B,
 837   MOD_VEX_W_0_0F41_P_0_LEN_1,
 838   MOD_VEX_W_1_0F41_P_0_LEN_1,
 839   MOD_VEX_W_0_0F41_P_2_LEN_1,
 840   MOD_VEX_W_1_0F41_P_2_LEN_1,
 841   MOD_VEX_W_0_0F42_P_0_LEN_1,
 842   MOD_VEX_W_1_0F42_P_0_LEN_1,
 843   MOD_VEX_W_0_0F42_P_2_LEN_1,
 844   MOD_VEX_W_1_0F42_P_2_LEN_1,
 845   MOD_VEX_W_0_0F44_P_0_LEN_1,
 846   MOD_VEX_W_1_0F44_P_0_LEN_1,
 847   MOD_VEX_W_0_0F44_P_2_LEN_1,
 848   MOD_VEX_W_1_0F44_P_2_LEN_1,
 849   MOD_VEX_W_0_0F45_P_0_LEN_1,
 850   MOD_VEX_W_1_0F45_P_0_LEN_1,
 851   MOD_VEX_W_0_0F45_P_2_LEN_1,
 852   MOD_VEX_W_1_0F45_P_2_LEN_1,
 853   MOD_VEX_W_0_0F46_P_0_LEN_1,
 854   MOD_VEX_W_1_0F46_P_0_LEN_1,
 855   MOD_VEX_W_0_0F46_P_2_LEN_1,
 856   MOD_VEX_W_1_0F46_P_2_LEN_1,
 857   MOD_VEX_W_0_0F47_P_0_LEN_1,
 858   MOD_VEX_W_1_0F47_P_0_LEN_1,
 859   MOD_VEX_W_0_0F47_P_2_LEN_1,
 860   MOD_VEX_W_1_0F47_P_2_LEN_1,
 861   MOD_VEX_W_0_0F4A_P_0_LEN_1,
 862   MOD_VEX_W_1_0F4A_P_0_LEN_1,
 863   MOD_VEX_W_0_0F4A_P_2_LEN_1,
 864   MOD_VEX_W_1_0F4A_P_2_LEN_1,
 865   MOD_VEX_W_0_0F4B_P_0_LEN_1,
 866   MOD_VEX_W_1_0F4B_P_0_LEN_1,
 867   MOD_VEX_W_0_0F4B_P_2_LEN_1,
 868   MOD_VEX_0F50,
 869   MOD_VEX_0F71_REG_2,
 870   MOD_VEX_0F71_REG_4,
 871   MOD_VEX_0F71_REG_6,
 872   MOD_VEX_0F72_REG_2,
 873   MOD_VEX_0F72_REG_4,
 874   MOD_VEX_0F72_REG_6,
 875   MOD_VEX_0F73_REG_2,
 876   MOD_VEX_0F73_REG_3,
 877   MOD_VEX_0F73_REG_6,
 878   MOD_VEX_0F73_REG_7,
 879   MOD_VEX_W_0_0F91_P_0_LEN_0,
 880   MOD_VEX_W_1_0F91_P_0_LEN_0,
 881   MOD_VEX_W_0_0F91_P_2_LEN_0,
 882   MOD_VEX_W_1_0F91_P_2_LEN_0,
 883   MOD_VEX_W_0_0F92_P_0_LEN_0,
 884   MOD_VEX_W_0_0F92_P_2_LEN_0,
 885   MOD_VEX_W_0_0F92_P_3_LEN_0,
 886   MOD_VEX_W_1_0F92_P_3_LEN_0,
 887   MOD_VEX_W_0_0F93_P_0_LEN_0,
 888   MOD_VEX_W_0_0F93_P_2_LEN_0,
 889   MOD_VEX_W_0_0F93_P_3_LEN_0,
 890   MOD_VEX_W_1_0F93_P_3_LEN_0,
 891   MOD_VEX_W_0_0F98_P_0_LEN_0,
 892   MOD_VEX_W_1_0F98_P_0_LEN_0,
 893   MOD_VEX_W_0_0F98_P_2_LEN_0,
 894   MOD_VEX_W_1_0F98_P_2_LEN_0,
 895   MOD_VEX_W_0_0F99_P_0_LEN_0,
 896   MOD_VEX_W_1_0F99_P_0_LEN_0,
 897   MOD_VEX_W_0_0F99_P_2_LEN_0,
 898   MOD_VEX_W_1_0F99_P_2_LEN_0,
 899   MOD_VEX_0FAE_REG_2,
 900   MOD_VEX_0FAE_REG_3,
 901   MOD_VEX_0FD7_PREFIX_2,
 902   MOD_VEX_0FE7_PREFIX_2,
 903   MOD_VEX_0FF0_PREFIX_3,
 904   MOD_VEX_0F381A_PREFIX_2,
 905   MOD_VEX_0F382A_PREFIX_2,
 906   MOD_VEX_0F382C_PREFIX_2,
 907   MOD_VEX_0F382D_PREFIX_2,
 908   MOD_VEX_0F382E_PREFIX_2,
 909   MOD_VEX_0F382F_PREFIX_2,
 910   MOD_VEX_0F385A_PREFIX_2,
 911   MOD_VEX_0F388C_PREFIX_2,
 912   MOD_VEX_0F388E_PREFIX_2,
 913   MOD_VEX_W_0_0F3A30_P_2_LEN_0,
 914   MOD_VEX_W_1_0F3A30_P_2_LEN_0,
 915   MOD_VEX_W_0_0F3A31_P_2_LEN_0,
 916   MOD_VEX_W_1_0F3A31_P_2_LEN_0,
 917   MOD_VEX_W_0_0F3A32_P_2_LEN_0,
 918   MOD_VEX_W_1_0F3A32_P_2_LEN_0,
 919   MOD_VEX_W_0_0F3A33_P_2_LEN_0,
 920   MOD_VEX_W_1_0F3A33_P_2_LEN_0,
 921
 922   MOD_EVEX_0F10_PREFIX_1,
 923   MOD_EVEX_0F10_PREFIX_3,
 924   MOD_EVEX_0F11_PREFIX_1,
 925   MOD_EVEX_0F11_PREFIX_3,
 926   MOD_EVEX_0F12_PREFIX_0,
 927   MOD_EVEX_0F16_PREFIX_0,
 928   MOD_EVEX_0F38C6_REG_1,
 929   MOD_EVEX_0F38C6_REG_2,
 930   MOD_EVEX_0F38C6_REG_5,
 931   MOD_EVEX_0F38C6_REG_6,
 932   MOD_EVEX_0F38C7_REG_1,
 933   MOD_EVEX_0F38C7_REG_2,
 934   MOD_EVEX_0F38C7_REG_5,
 935   MOD_EVEX_0F38C7_REG_6
 936 };
 937
 938 enum
 939 {
 940   RM_C6_REG_7 = 0,
 941   RM_C7_REG_7,
 942   RM_0F01_REG_0,
 943   RM_0F01_REG_1,
 944   RM_0F01_REG_2,
 945   RM_0F01_REG_3,
 946   RM_0F01_REG_5,
 947   RM_0F01_REG_7,
 948   RM_0F1E_MOD_3_REG_7,
 949   RM_0FAE_REG_6,
 950   RM_0FAE_REG_7
 951 };
 952
 953 enum
 954 {
 955   PREFIX_90 = 0,
 956   PREFIX_MOD_0_0F01_REG_5,
 957   PREFIX_MOD_3_0F01_REG_5_RM_0,
 958   PREFIX_MOD_3_0F01_REG_5_RM_2,
 959   PREFIX_0F10,
 960   PREFIX_0F11,
 961   PREFIX_0F12,
 962   PREFIX_0F16,
 963   PREFIX_0F1A,
 964   PREFIX_0F1B,
 965   PREFIX_0F1E,
 966   PREFIX_0F2A,
 967   PREFIX_0F2B,
 968   PREFIX_0F2C,
 969   PREFIX_0F2D,
 970   PREFIX_0F2E,
 971   PREFIX_0F2F,
 972   PREFIX_0F51,
 973   PREFIX_0F52,
 974   PREFIX_0F53,
 975   PREFIX_0F58,
 976   PREFIX_0F59,
 977   PREFIX_0F5A,
 978   PREFIX_0F5B,
 979   PREFIX_0F5C,
 980   PREFIX_0F5D,
 981   PREFIX_0F5E,
 982   PREFIX_0F5F,
 983   PREFIX_0F60,
 984   PREFIX_0F61,
 985   PREFIX_0F62,
 986   PREFIX_0F6C,
 987   PREFIX_0F6D,
 988   PREFIX_0F6F,
 989   PREFIX_0F70,
 990   PREFIX_0F73_REG_3,
 991   PREFIX_0F73_REG_7,
 992   PREFIX_0F78,
 993   PREFIX_0F79,
 994   PREFIX_0F7C,
 995   PREFIX_0F7D,
 996   PREFIX_0F7E,
 997   PREFIX_0F7F,
 998   PREFIX_0FAE_REG_0,
 999   PREFIX_0FAE_REG_1,
1000   PREFIX_0FAE_REG_2,
1001   PREFIX_0FAE_REG_3,
1002   PREFIX_MOD_0_0FAE_REG_4,
1003   PREFIX_MOD_3_0FAE_REG_4,
1004   PREFIX_MOD_0_0FAE_REG_5,
1005   PREFIX_MOD_3_0FAE_REG_5,
1006   PREFIX_0FAE_REG_6,
1007   PREFIX_0FAE_REG_7,
1008   PREFIX_0FB8,
1009   PREFIX_0FBC,
1010   PREFIX_0FBD,
1011   PREFIX_0FC2,
1012   PREFIX_MOD_0_0FC3,
1013   PREFIX_MOD_0_0FC7_REG_6,
1014   PREFIX_MOD_3_0FC7_REG_6,
1015   PREFIX_MOD_3_0FC7_REG_7,
1016   PREFIX_0FD0,
1017   PREFIX_0FD6,
1018   PREFIX_0FE6,
1019   PREFIX_0FE7,
1020   PREFIX_0FF0,
1021   PREFIX_0FF7,
1022   PREFIX_0F3810,
1023   PREFIX_0F3814,
1024   PREFIX_0F3815,
1025   PREFIX_0F3817,
1026   PREFIX_0F3820,
1027   PREFIX_0F3821,
1028   PREFIX_0F3822,
1029   PREFIX_0F3823,
1030   PREFIX_0F3824,
1031   PREFIX_0F3825,
1032   PREFIX_0F3828,
1033   PREFIX_0F3829,
1034   PREFIX_0F382A,
1035   PREFIX_0F382B,
1036   PREFIX_0F3830,
1037   PREFIX_0F3831,
1038   PREFIX_0F3832,
1039   PREFIX_0F3833,
1040   PREFIX_0F3834,
1041   PREFIX_0F3835,
1042   PREFIX_0F3837,
1043   PREFIX_0F3838,
1044   PREFIX_0F3839,
1045   PREFIX_0F383A,
1046   PREFIX_0F383B,
1047   PREFIX_0F383C,
1048   PREFIX_0F383D,
1049   PREFIX_0F383E,
1050   PREFIX_0F383F,
1051   PREFIX_0F3840,
1052   PREFIX_0F3841,
1053   PREFIX_0F3880,
1054   PREFIX_0F3881,
1055   PREFIX_0F3882,
1056   PREFIX_0F38C8,
1057   PREFIX_0F38C9,
1058   PREFIX_0F38CA,
1059   PREFIX_0F38CB,
1060   PREFIX_0F38CC,
1061   PREFIX_0F38CD,
1062   PREFIX_0F38DB,
1063   PREFIX_0F38DC,
1064   PREFIX_0F38DD,
1065   PREFIX_0F38DE,
1066   PREFIX_0F38DF,
1067   PREFIX_0F38F0,
1068   PREFIX_0F38F1,
1069   PREFIX_0F38F5,
1070   PREFIX_0F38F6,
1071   PREFIX_0F3A08,
1072   PREFIX_0F3A09,
1073   PREFIX_0F3A0A,
1074   PREFIX_0F3A0B,
1075   PREFIX_0F3A0C,
1076   PREFIX_0F3A0D,
1077   PREFIX_0F3A0E,
1078   PREFIX_0F3A14,
1079   PREFIX_0F3A15,
1080   PREFIX_0F3A16,
1081   PREFIX_0F3A17,
1082   PREFIX_0F3A20,
1083   PREFIX_0F3A21,
1084   PREFIX_0F3A22,
1085   PREFIX_0F3A40,
1086   PREFIX_0F3A41,
1087   PREFIX_0F3A42,
1088   PREFIX_0F3A44,
1089   PREFIX_0F3A60,
1090   PREFIX_0F3A61,
1091   PREFIX_0F3A62,
1092   PREFIX_0F3A63,
1093   PREFIX_0F3ACC,
1094   PREFIX_0F3ADF,
1095   PREFIX_VEX_0F10,
1096   PREFIX_VEX_0F11,
1097   PREFIX_VEX_0F12,
1098   PREFIX_VEX_0F16,
1099   PREFIX_VEX_0F2A,
1100   PREFIX_VEX_0F2C,
1101   PREFIX_VEX_0F2D,
1102   PREFIX_VEX_0F2E,
1103   PREFIX_VEX_0F2F,
1104   PREFIX_VEX_0F41,
1105   PREFIX_VEX_0F42,
1106   PREFIX_VEX_0F44,
1107   PREFIX_VEX_0F45,
1108   PREFIX_VEX_0F46,
1109   PREFIX_VEX_0F47,
1110   PREFIX_VEX_0F4A,
1111   PREFIX_VEX_0F4B,
1112   PREFIX_VEX_0F51,
1113   PREFIX_VEX_0F52,
1114   PREFIX_VEX_0F53,
1115   PREFIX_VEX_0F58,
1116   PREFIX_VEX_0F59,
1117   PREFIX_VEX_0F5A,
1118   PREFIX_VEX_0F5B,
1119   PREFIX_VEX_0F5C,
1120   PREFIX_VEX_0F5D,
1121   PREFIX_VEX_0F5E,
1122   PREFIX_VEX_0F5F,
1123   PREFIX_VEX_0F60,
1124   PREFIX_VEX_0F61,
1125   PREFIX_VEX_0F62,
1126   PREFIX_VEX_0F63,
1127   PREFIX_VEX_0F64,
1128   PREFIX_VEX_0F65,
1129   PREFIX_VEX_0F66,
1130   PREFIX_VEX_0F67,
1131   PREFIX_VEX_0F68,
1132   PREFIX_VEX_0F69,
1133   PREFIX_VEX_0F6A,
1134   PREFIX_VEX_0F6B,
1135   PREFIX_VEX_0F6C,
1136   PREFIX_VEX_0F6D,
1137   PREFIX_VEX_0F6E,
1138   PREFIX_VEX_0F6F,
1139   PREFIX_VEX_0F70,
1140   PREFIX_VEX_0F71_REG_2,
1141   PREFIX_VEX_0F71_REG_4,
1142   PREFIX_VEX_0F71_REG_6,
1143   PREFIX_VEX_0F72_REG_2,
1144   PREFIX_VEX_0F72_REG_4,
1145   PREFIX_VEX_0F72_REG_6,
1146   PREFIX_VEX_0F73_REG_2,
1147   PREFIX_VEX_0F73_REG_3,
1148   PREFIX_VEX_0F73_REG_6,
1149   PREFIX_VEX_0F73_REG_7,
1150   PREFIX_VEX_0F74,
1151   PREFIX_VEX_0F75,
1152   PREFIX_VEX_0F76,
1153   PREFIX_VEX_0F77,
1154   PREFIX_VEX_0F7C,
1155   PREFIX_VEX_0F7D,
1156   PREFIX_VEX_0F7E,
1157   PREFIX_VEX_0F7F,
1158   PREFIX_VEX_0F90,
1159   PREFIX_VEX_0F91,
1160   PREFIX_VEX_0F92,
1161   PREFIX_VEX_0F93,
1162   PREFIX_VEX_0F98,
1163   PREFIX_VEX_0F99,
1164   PREFIX_VEX_0FC2,
1165   PREFIX_VEX_0FC4,
1166   PREFIX_VEX_0FC5,
1167   PREFIX_VEX_0FD0,
1168   PREFIX_VEX_0FD1,
1169   PREFIX_VEX_0FD2,
1170   PREFIX_VEX_0FD3,
1171   PREFIX_VEX_0FD4,
1172   PREFIX_VEX_0FD5,
1173   PREFIX_VEX_0FD6,
1174   PREFIX_VEX_0FD7,
1175   PREFIX_VEX_0FD8,
1176   PREFIX_VEX_0FD9,
1177   PREFIX_VEX_0FDA,
1178   PREFIX_VEX_0FDB,
1179   PREFIX_VEX_0FDC,
1180   PREFIX_VEX_0FDD,
1181   PREFIX_VEX_0FDE,
1182   PREFIX_VEX_0FDF,
1183   PREFIX_VEX_0FE0,
1184   PREFIX_VEX_0FE1,
1185   PREFIX_VEX_0FE2,
1186   PREFIX_VEX_0FE3,
1187   PREFIX_VEX_0FE4,
1188   PREFIX_VEX_0FE5,
1189   PREFIX_VEX_0FE6,
1190   PREFIX_VEX_0FE7,
1191   PREFIX_VEX_0FE8,
1192   PREFIX_VEX_0FE9,
1193   PREFIX_VEX_0FEA,
1194   PREFIX_VEX_0FEB,
1195   PREFIX_VEX_0FEC,
1196   PREFIX_VEX_0FED,
1197   PREFIX_VEX_0FEE,
1198   PREFIX_VEX_0FEF,
1199   PREFIX_VEX_0FF0,
1200   PREFIX_VEX_0FF1,
1201   PREFIX_VEX_0FF2,
1202   PREFIX_VEX_0FF3,
1203   PREFIX_VEX_0FF4,
1204   PREFIX_VEX_0FF5,
1205   PREFIX_VEX_0FF6,
1206   PREFIX_VEX_0FF7,
1207   PREFIX_VEX_0FF8,
1208   PREFIX_VEX_0FF9,
1209   PREFIX_VEX_0FFA,
1210   PREFIX_VEX_0FFB,
1211   PREFIX_VEX_0FFC,
1212   PREFIX_VEX_0FFD,
1213   PREFIX_VEX_0FFE,
1214   PREFIX_VEX_0F3800,
1215   PREFIX_VEX_0F3801,
1216   PREFIX_VEX_0F3802,
1217   PREFIX_VEX_0F3803,
1218   PREFIX_VEX_0F3804,
1219   PREFIX_VEX_0F3805,
1220   PREFIX_VEX_0F3806,
1221   PREFIX_VEX_0F3807,
1222   PREFIX_VEX_0F3808,
1223   PREFIX_VEX_0F3809,
1224   PREFIX_VEX_0F380A,
1225   PREFIX_VEX_0F380B,
1226   PREFIX_VEX_0F380C,
1227   PREFIX_VEX_0F380D,
1228   PREFIX_VEX_0F380E,
1229   PREFIX_VEX_0F380F,
1230   PREFIX_VEX_0F3813,
1231   PREFIX_VEX_0F3816,
1232   PREFIX_VEX_0F3817,
1233   PREFIX_VEX_0F3818,
1234   PREFIX_VEX_0F3819,
1235   PREFIX_VEX_0F381A,
1236   PREFIX_VEX_0F381C,
1237   PREFIX_VEX_0F381D,
1238   PREFIX_VEX_0F381E,
1239   PREFIX_VEX_0F3820,
1240   PREFIX_VEX_0F3821,
1241   PREFIX_VEX_0F3822,
1242   PREFIX_VEX_0F3823,
1243   PREFIX_VEX_0F3824,
1244   PREFIX_VEX_0F3825,
1245   PREFIX_VEX_0F3828,
1246   PREFIX_VEX_0F3829,
1247   PREFIX_VEX_0F382A,
1248   PREFIX_VEX_0F382B,
1249   PREFIX_VEX_0F382C,
1250   PREFIX_VEX_0F382D,
1251   PREFIX_VEX_0F382E,
1252   PREFIX_VEX_0F382F,
1253   PREFIX_VEX_0F3830,
1254   PREFIX_VEX_0F3831,
1255   PREFIX_VEX_0F3832,
1256   PREFIX_VEX_0F3833,
1257   PREFIX_VEX_0F3834,
1258   PREFIX_VEX_0F3835,
1259   PREFIX_VEX_0F3836,
1260   PREFIX_VEX_0F3837,
1261   PREFIX_VEX_0F3838,
1262   PREFIX_VEX_0F3839,
1263   PREFIX_VEX_0F383A,
1264   PREFIX_VEX_0F383B,
1265   PREFIX_VEX_0F383C,
1266   PREFIX_VEX_0F383D,
1267   PREFIX_VEX_0F383E,
1268   PREFIX_VEX_0F383F,
1269   PREFIX_VEX_0F3840,
1270   PREFIX_VEX_0F3841,
1271   PREFIX_VEX_0F3845,
1272   PREFIX_VEX_0F3846,
1273   PREFIX_VEX_0F3847,
1274   PREFIX_VEX_0F3858,
1275   PREFIX_VEX_0F3859,
1276   PREFIX_VEX_0F385A,
1277   PREFIX_VEX_0F3878,
1278   PREFIX_VEX_0F3879,
1279   PREFIX_VEX_0F388C,
1280   PREFIX_VEX_0F388E,
1281   PREFIX_VEX_0F3890,
1282   PREFIX_VEX_0F3891,
1283   PREFIX_VEX_0F3892,
1284   PREFIX_VEX_0F3893,
1285   PREFIX_VEX_0F3896,
1286   PREFIX_VEX_0F3897,
1287   PREFIX_VEX_0F3898,
1288   PREFIX_VEX_0F3899,
1289   PREFIX_VEX_0F389A,
1290   PREFIX_VEX_0F389B,
1291   PREFIX_VEX_0F389C,
1292   PREFIX_VEX_0F389D,
1293   PREFIX_VEX_0F389E,
1294   PREFIX_VEX_0F389F,
1295   PREFIX_VEX_0F38A6,
1296   PREFIX_VEX_0F38A7,
1297   PREFIX_VEX_0F38A8,
1298   PREFIX_VEX_0F38A9,
1299   PREFIX_VEX_0F38AA,
1300   PREFIX_VEX_0F38AB,
1301   PREFIX_VEX_0F38AC,
1302   PREFIX_VEX_0F38AD,
1303   PREFIX_VEX_0F38AE,
1304   PREFIX_VEX_0F38AF,
1305   PREFIX_VEX_0F38B6,
1306   PREFIX_VEX_0F38B7,
1307   PREFIX_VEX_0F38B8,
1308   PREFIX_VEX_0F38B9,
1309   PREFIX_VEX_0F38BA,
1310   PREFIX_VEX_0F38BB,
1311   PREFIX_VEX_0F38BC,
1312   PREFIX_VEX_0F38BD,
1313   PREFIX_VEX_0F38BE,
1314   PREFIX_VEX_0F38BF,
1315   PREFIX_VEX_0F38DB,
1316   PREFIX_VEX_0F38DC,
1317   PREFIX_VEX_0F38DD,
1318   PREFIX_VEX_0F38DE,
1319   PREFIX_VEX_0F38DF,
1320   PREFIX_VEX_0F38F2,
1321   PREFIX_VEX_0F38F3_REG_1,
1322   PREFIX_VEX_0F38F3_REG_2,
1323   PREFIX_VEX_0F38F3_REG_3,
1324   PREFIX_VEX_0F38F5,
1325   PREFIX_VEX_0F38F6,
1326   PREFIX_VEX_0F38F7,
1327   PREFIX_VEX_0F3A00,
1328   PREFIX_VEX_0F3A01,
1329   PREFIX_VEX_0F3A02,
1330   PREFIX_VEX_0F3A04,
1331   PREFIX_VEX_0F3A05,
1332   PREFIX_VEX_0F3A06,
1333   PREFIX_VEX_0F3A08,
1334   PREFIX_VEX_0F3A09,
1335   PREFIX_VEX_0F3A0A,
1336   PREFIX_VEX_0F3A0B,
1337   PREFIX_VEX_0F3A0C,
1338   PREFIX_VEX_0F3A0D,
1339   PREFIX_VEX_0F3A0E,
1340   PREFIX_VEX_0F3A0F,
1341   PREFIX_VEX_0F3A14,
1342   PREFIX_VEX_0F3A15,
1343   PREFIX_VEX_0F3A16,
1344   PREFIX_VEX_0F3A17,
1345   PREFIX_VEX_0F3A18,
1346   PREFIX_VEX_0F3A19,
1347   PREFIX_VEX_0F3A1D,
1348   PREFIX_VEX_0F3A20,
1349   PREFIX_VEX_0F3A21,
1350   PREFIX_VEX_0F3A22,
1351   PREFIX_VEX_0F3A30,
1352   PREFIX_VEX_0F3A31,
1353   PREFIX_VEX_0F3A32,
1354   PREFIX_VEX_0F3A33,
1355   PREFIX_VEX_0F3A38,
1356   PREFIX_VEX_0F3A39,
1357   PREFIX_VEX_0F3A40,
1358   PREFIX_VEX_0F3A41,
1359   PREFIX_VEX_0F3A42,
1360   PREFIX_VEX_0F3A44,
1361   PREFIX_VEX_0F3A46,
1362   PREFIX_VEX_0F3A48,
1363   PREFIX_VEX_0F3A49,
1364   PREFIX_VEX_0F3A4A,
1365   PREFIX_VEX_0F3A4B,
1366   PREFIX_VEX_0F3A4C,
1367   PREFIX_VEX_0F3A5C,
1368   PREFIX_VEX_0F3A5D,
1369   PREFIX_VEX_0F3A5E,
1370   PREFIX_VEX_0F3A5F,
1371   PREFIX_VEX_0F3A60,
1372   PREFIX_VEX_0F3A61,
1373   PREFIX_VEX_0F3A62,
1374   PREFIX_VEX_0F3A63,
1375   PREFIX_VEX_0F3A68,
1376   PREFIX_VEX_0F3A69,
1377   PREFIX_VEX_0F3A6A,
1378   PREFIX_VEX_0F3A6B,
1379   PREFIX_VEX_0F3A6C,
1380   PREFIX_VEX_0F3A6D,
1381   PREFIX_VEX_0F3A6E,
1382   PREFIX_VEX_0F3A6F,
1383   PREFIX_VEX_0F3A78,
1384   PREFIX_VEX_0F3A79,
1385   PREFIX_VEX_0F3A7A,
1386   PREFIX_VEX_0F3A7B,
1387   PREFIX_VEX_0F3A7C,
1388   PREFIX_VEX_0F3A7D,
1389   PREFIX_VEX_0F3A7E,
1390   PREFIX_VEX_0F3A7F,
1391   PREFIX_VEX_0F3ADF,
1392   PREFIX_VEX_0F3AF0,
1393
1394   PREFIX_EVEX_0F10,
1395   PREFIX_EVEX_0F11,
1396   PREFIX_EVEX_0F12,
1397   PREFIX_EVEX_0F13,
1398   PREFIX_EVEX_0F14,
1399   PREFIX_EVEX_0F15,
1400   PREFIX_EVEX_0F16,
1401   PREFIX_EVEX_0F17,
1402   PREFIX_EVEX_0F28,
1403   PREFIX_EVEX_0F29,
1404   PREFIX_EVEX_0F2A,
1405   PREFIX_EVEX_0F2B,
1406   PREFIX_EVEX_0F2C,
1407   PREFIX_EVEX_0F2D,
1408   PREFIX_EVEX_0F2E,
1409   PREFIX_EVEX_0F2F,
1410   PREFIX_EVEX_0F51,
1411   PREFIX_EVEX_0F54,
1412   PREFIX_EVEX_0F55,
1413   PREFIX_EVEX_0F56,
1414   PREFIX_EVEX_0F57,
1415   PREFIX_EVEX_0F58,
1416   PREFIX_EVEX_0F59,
1417   PREFIX_EVEX_0F5A,
1418   PREFIX_EVEX_0F5B,
1419   PREFIX_EVEX_0F5C,
1420   PREFIX_EVEX_0F5D,
1421   PREFIX_EVEX_0F5E,
1422   PREFIX_EVEX_0F5F,
1423   PREFIX_EVEX_0F60,
1424   PREFIX_EVEX_0F61,
1425   PREFIX_EVEX_0F62,
1426   PREFIX_EVEX_0F63,
1427   PREFIX_EVEX_0F64,
1428   PREFIX_EVEX_0F65,
1429   PREFIX_EVEX_0F66,
1430   PREFIX_EVEX_0F67,
1431   PREFIX_EVEX_0F68,
1432   PREFIX_EVEX_0F69,
1433   PREFIX_EVEX_0F6A,
1434   PREFIX_EVEX_0F6B,
1435   PREFIX_EVEX_0F6C,
1436   PREFIX_EVEX_0F6D,
1437   PREFIX_EVEX_0F6E,
1438   PREFIX_EVEX_0F6F,
1439   PREFIX_EVEX_0F70,
1440   PREFIX_EVEX_0F71_REG_2,
1441   PREFIX_EVEX_0F71_REG_4,
1442   PREFIX_EVEX_0F71_REG_6,
1443   PREFIX_EVEX_0F72_REG_0,
1444   PREFIX_EVEX_0F72_REG_1,
1445   PREFIX_EVEX_0F72_REG_2,
1446   PREFIX_EVEX_0F72_REG_4,
1447   PREFIX_EVEX_0F72_REG_6,
1448   PREFIX_EVEX_0F73_REG_2,
1449   PREFIX_EVEX_0F73_REG_3,
1450   PREFIX_EVEX_0F73_REG_6,
1451   PREFIX_EVEX_0F73_REG_7,
1452   PREFIX_EVEX_0F74,
1453   PREFIX_EVEX_0F75,
1454   PREFIX_EVEX_0F76,
1455   PREFIX_EVEX_0F78,
1456   PREFIX_EVEX_0F79,
1457   PREFIX_EVEX_0F7A,
1458   PREFIX_EVEX_0F7B,
1459   PREFIX_EVEX_0F7E,
1460   PREFIX_EVEX_0F7F,
1461   PREFIX_EVEX_0FC2,
1462   PREFIX_EVEX_0FC4,
1463   PREFIX_EVEX_0FC5,
1464   PREFIX_EVEX_0FC6,
1465   PREFIX_EVEX_0FD1,
1466   PREFIX_EVEX_0FD2,
1467   PREFIX_EVEX_0FD3,
1468   PREFIX_EVEX_0FD4,
1469   PREFIX_EVEX_0FD5,
1470   PREFIX_EVEX_0FD6,
1471   PREFIX_EVEX_0FD8,
1472   PREFIX_EVEX_0FD9,
1473   PREFIX_EVEX_0FDA,
1474   PREFIX_EVEX_0FDB,
1475   PREFIX_EVEX_0FDC,
1476   PREFIX_EVEX_0FDD,
1477   PREFIX_EVEX_0FDE,
1478   PREFIX_EVEX_0FDF,
1479   PREFIX_EVEX_0FE0,
1480   PREFIX_EVEX_0FE1,
1481   PREFIX_EVEX_0FE2,
1482   PREFIX_EVEX_0FE3,
1483   PREFIX_EVEX_0FE4,
1484   PREFIX_EVEX_0FE5,
1485   PREFIX_EVEX_0FE6,
1486   PREFIX_EVEX_0FE7,
1487   PREFIX_EVEX_0FE8,
1488   PREFIX_EVEX_0FE9,
1489   PREFIX_EVEX_0FEA,
1490   PREFIX_EVEX_0FEB,
1491   PREFIX_EVEX_0FEC,
1492   PREFIX_EVEX_0FED,
1493   PREFIX_EVEX_0FEE,
1494   PREFIX_EVEX_0FEF,
1495   PREFIX_EVEX_0FF1,
1496   PREFIX_EVEX_0FF2,
1497   PREFIX_EVEX_0FF3,
1498   PREFIX_EVEX_0FF4,
1499   PREFIX_EVEX_0FF5,
1500   PREFIX_EVEX_0FF6,
1501   PREFIX_EVEX_0FF8,
1502   PREFIX_EVEX_0FF9,
1503   PREFIX_EVEX_0FFA,
1504   PREFIX_EVEX_0FFB,
1505   PREFIX_EVEX_0FFC,
1506   PREFIX_EVEX_0FFD,
1507   PREFIX_EVEX_0FFE,
1508   PREFIX_EVEX_0F3800,
1509   PREFIX_EVEX_0F3804,
1510   PREFIX_EVEX_0F380B,
1511   PREFIX_EVEX_0F380C,
1512   PREFIX_EVEX_0F380D,
1513   PREFIX_EVEX_0F3810,
1514   PREFIX_EVEX_0F3811,
1515   PREFIX_EVEX_0F3812,
1516   PREFIX_EVEX_0F3813,
1517   PREFIX_EVEX_0F3814,
1518   PREFIX_EVEX_0F3815,
1519   PREFIX_EVEX_0F3816,
1520   PREFIX_EVEX_0F3818,
1521   PREFIX_EVEX_0F3819,
1522   PREFIX_EVEX_0F381A,
1523   PREFIX_EVEX_0F381B,
1524   PREFIX_EVEX_0F381C,
1525   PREFIX_EVEX_0F381D,
1526   PREFIX_EVEX_0F381E,
1527   PREFIX_EVEX_0F381F,
1528   PREFIX_EVEX_0F3820,
1529   PREFIX_EVEX_0F3821,
1530   PREFIX_EVEX_0F3822,
1531   PREFIX_EVEX_0F3823,
1532   PREFIX_EVEX_0F3824,
1533   PREFIX_EVEX_0F3825,
1534   PREFIX_EVEX_0F3826,
1535   PREFIX_EVEX_0F3827,
1536   PREFIX_EVEX_0F3828,
1537   PREFIX_EVEX_0F3829,
1538   PREFIX_EVEX_0F382A,
1539   PREFIX_EVEX_0F382B,
1540   PREFIX_EVEX_0F382C,
1541   PREFIX_EVEX_0F382D,
1542   PREFIX_EVEX_0F3830,
1543   PREFIX_EVEX_0F3831,
1544   PREFIX_EVEX_0F3832,
1545   PREFIX_EVEX_0F3833,
1546   PREFIX_EVEX_0F3834,
1547   PREFIX_EVEX_0F3835,
1548   PREFIX_EVEX_0F3836,
1549   PREFIX_EVEX_0F3837,
1550   PREFIX_EVEX_0F3838,
1551   PREFIX_EVEX_0F3839,
1552   PREFIX_EVEX_0F383A,
1553   PREFIX_EVEX_0F383B,
1554   PREFIX_EVEX_0F383C,
1555   PREFIX_EVEX_0F383D,
1556   PREFIX_EVEX_0F383E,
1557   PREFIX_EVEX_0F383F,
1558   PREFIX_EVEX_0F3840,
1559   PREFIX_EVEX_0F3842,
1560   PREFIX_EVEX_0F3843,
1561   PREFIX_EVEX_0F3844,
1562   PREFIX_EVEX_0F3845,
1563   PREFIX_EVEX_0F3846,
1564   PREFIX_EVEX_0F3847,
1565   PREFIX_EVEX_0F384C,
1566   PREFIX_EVEX_0F384D,
1567   PREFIX_EVEX_0F384E,
1568   PREFIX_EVEX_0F384F,
1569   PREFIX_EVEX_0F3852,
1570   PREFIX_EVEX_0F3853,
1571   PREFIX_EVEX_0F3855,
1572   PREFIX_EVEX_0F3858,
1573   PREFIX_EVEX_0F3859,
1574   PREFIX_EVEX_0F385A,
1575   PREFIX_EVEX_0F385B,
1576   PREFIX_EVEX_0F3862,
1577   PREFIX_EVEX_0F3863,
1578   PREFIX_EVEX_0F3864,
1579   PREFIX_EVEX_0F3865,
1580   PREFIX_EVEX_0F3866,
1581   PREFIX_EVEX_0F3870,
1582   PREFIX_EVEX_0F3871,
1583   PREFIX_EVEX_0F3872,
1584   PREFIX_EVEX_0F3873,
1585   PREFIX_EVEX_0F3875,
1586   PREFIX_EVEX_0F3876,
1587   PREFIX_EVEX_0F3877,
1588   PREFIX_EVEX_0F3878,
1589   PREFIX_EVEX_0F3879,
1590   PREFIX_EVEX_0F387A,
1591   PREFIX_EVEX_0F387B,
1592   PREFIX_EVEX_0F387C,
1593   PREFIX_EVEX_0F387D,
1594   PREFIX_EVEX_0F387E,
1595   PREFIX_EVEX_0F387F,
1596   PREFIX_EVEX_0F3883,
1597   PREFIX_EVEX_0F3888,
1598   PREFIX_EVEX_0F3889,
1599   PREFIX_EVEX_0F388A,
1600   PREFIX_EVEX_0F388B,
1601   PREFIX_EVEX_0F388D,
1602   PREFIX_EVEX_0F3890,
1603   PREFIX_EVEX_0F3891,
1604   PREFIX_EVEX_0F3892,
1605   PREFIX_EVEX_0F3893,
1606   PREFIX_EVEX_0F3896,
1607   PREFIX_EVEX_0F3897,
1608   PREFIX_EVEX_0F3898,
1609   PREFIX_EVEX_0F3899,
1610   PREFIX_EVEX_0F389A,
1611   PREFIX_EVEX_0F389B,
1612   PREFIX_EVEX_0F389C,
1613   PREFIX_EVEX_0F389D,
1614   PREFIX_EVEX_0F389E,
1615   PREFIX_EVEX_0F389F,
1616   PREFIX_EVEX_0F38A0,
1617   PREFIX_EVEX_0F38A1,
1618   PREFIX_EVEX_0F38A2,
1619   PREFIX_EVEX_0F38A3,
1620   PREFIX_EVEX_0F38A6,
1621   PREFIX_EVEX_0F38A7,
1622   PREFIX_EVEX_0F38A8,
1623   PREFIX_EVEX_0F38A9,
1624   PREFIX_EVEX_0F38AA,
1625   PREFIX_EVEX_0F38AB,
1626   PREFIX_EVEX_0F38AC,
1627   PREFIX_EVEX_0F38AD,
1628   PREFIX_EVEX_0F38AE,
1629   PREFIX_EVEX_0F38AF,
1630   PREFIX_EVEX_0F38B4,
1631   PREFIX_EVEX_0F38B5,
1632   PREFIX_EVEX_0F38B6,
1633   PREFIX_EVEX_0F38B7,
1634   PREFIX_EVEX_0F38B8,
1635   PREFIX_EVEX_0F38B9,
1636   PREFIX_EVEX_0F38BA,
1637   PREFIX_EVEX_0F38BB,
1638   PREFIX_EVEX_0F38BC,
1639   PREFIX_EVEX_0F38BD,
1640   PREFIX_EVEX_0F38BE,
1641   PREFIX_EVEX_0F38BF,
1642   PREFIX_EVEX_0F38C4,
1643   PREFIX_EVEX_0F38C6_REG_1,
1644   PREFIX_EVEX_0F38C6_REG_2,
1645   PREFIX_EVEX_0F38C6_REG_5,
1646   PREFIX_EVEX_0F38C6_REG_6,
1647   PREFIX_EVEX_0F38C7_REG_1,
1648   PREFIX_EVEX_0F38C7_REG_2,
1649   PREFIX_EVEX_0F38C7_REG_5,
1650   PREFIX_EVEX_0F38C7_REG_6,
1651   PREFIX_EVEX_0F38C8,
1652   PREFIX_EVEX_0F38CA,
1653   PREFIX_EVEX_0F38CB,
1654   PREFIX_EVEX_0F38CC,
1655   PREFIX_EVEX_0F38CD,
1656
1657   PREFIX_EVEX_0F3A00,
1658   PREFIX_EVEX_0F3A01,
1659   PREFIX_EVEX_0F3A03,
1660   PREFIX_EVEX_0F3A04,
1661   PREFIX_EVEX_0F3A05,
1662   PREFIX_EVEX_0F3A08,
1663   PREFIX_EVEX_0F3A09,
1664   PREFIX_EVEX_0F3A0A,
1665   PREFIX_EVEX_0F3A0B,
1666   PREFIX_EVEX_0F3A0F,
1667   PREFIX_EVEX_0F3A14,
1668   PREFIX_EVEX_0F3A15,
1669   PREFIX_EVEX_0F3A16,
1670   PREFIX_EVEX_0F3A17,
1671   PREFIX_EVEX_0F3A18,
1672   PREFIX_EVEX_0F3A19,
1673   PREFIX_EVEX_0F3A1A,
1674   PREFIX_EVEX_0F3A1B,
1675   PREFIX_EVEX_0F3A1D,
1676   PREFIX_EVEX_0F3A1E,
1677   PREFIX_EVEX_0F3A1F,
1678   PREFIX_EVEX_0F3A20,
1679   PREFIX_EVEX_0F3A21,
1680   PREFIX_EVEX_0F3A22,
1681   PREFIX_EVEX_0F3A23,
1682   PREFIX_EVEX_0F3A25,
1683   PREFIX_EVEX_0F3A26,
1684   PREFIX_EVEX_0F3A27,
1685   PREFIX_EVEX_0F3A38,
1686   PREFIX_EVEX_0F3A39,
1687   PREFIX_EVEX_0F3A3A,
1688   PREFIX_EVEX_0F3A3B,
1689   PREFIX_EVEX_0F3A3E,
1690   PREFIX_EVEX_0F3A3F,
1691   PREFIX_EVEX_0F3A42,
1692   PREFIX_EVEX_0F3A43,
1693   PREFIX_EVEX_0F3A50,
1694   PREFIX_EVEX_0F3A51,
1695   PREFIX_EVEX_0F3A54,
1696   PREFIX_EVEX_0F3A55,
1697   PREFIX_EVEX_0F3A56,
1698   PREFIX_EVEX_0F3A57,
1699   PREFIX_EVEX_0F3A66,
1700   PREFIX_EVEX_0F3A67,
1701   PREFIX_EVEX_0F3A70,
1702   PREFIX_EVEX_0F3A71,
1703   PREFIX_EVEX_0F3A72,
1704   PREFIX_EVEX_0F3A73
1705 };
1706
1707 enum
1708 {
1709   X86_64_06 = 0,
1710   X86_64_07,
1711   X86_64_0D,
1712   X86_64_16,
1713   X86_64_17,
1714   X86_64_1E,
1715   X86_64_1F,
1716   X86_64_27,
1717   X86_64_2F,
1718   X86_64_37,
1719   X86_64_3F,
1720   X86_64_60,
1721   X86_64_61,
1722   X86_64_62,
1723   X86_64_63,
1724   X86_64_6D,
1725   X86_64_6F,
1726   X86_64_82,
1727   X86_64_9A,
1728   X86_64_C4,
1729   X86_64_C5,
1730   X86_64_CE,
1731   X86_64_D4,
1732   X86_64_D5,
1733   X86_64_E8,
1734   X86_64_E9,
1735   X86_64_EA,
1736   X86_64_0F01_REG_0,
1737   X86_64_0F01_REG_1,
1738   X86_64_0F01_REG_2,
1739   X86_64_0F01_REG_3
1740 };
1741
1742 enum
1743 {
1744   THREE_BYTE_0F38 = 0,
1745   THREE_BYTE_0F3A
1746 };
1747
1748 enum
1749 {
1750   XOP_08 = 0,
1751   XOP_09,
1752   XOP_0A
1753 };
1754
1755 enum
1756 {
1757   VEX_0F = 0,
1758   VEX_0F38,
1759   VEX_0F3A
1760 };
1761
1762 enum
1763 {
1764   EVEX_0F = 0,
1765   EVEX_0F38,
1766   EVEX_0F3A
1767 };
1768
1769 enum
1770 {
1771   VEX_LEN_0F10_P_1 = 0,
1772   VEX_LEN_0F10_P_3,
1773   VEX_LEN_0F11_P_1,
1774   VEX_LEN_0F11_P_3,
1775   VEX_LEN_0F12_P_0_M_0,
1776   VEX_LEN_0F12_P_0_M_1,
1777   VEX_LEN_0F12_P_2,
1778   VEX_LEN_0F13_M_0,
1779   VEX_LEN_0F16_P_0_M_0,
1780   VEX_LEN_0F16_P_0_M_1,
1781   VEX_LEN_0F16_P_2,
1782   VEX_LEN_0F17_M_0,
1783   VEX_LEN_0F2A_P_1,
1784   VEX_LEN_0F2A_P_3,
1785   VEX_LEN_0F2C_P_1,
1786   VEX_LEN_0F2C_P_3,
1787   VEX_LEN_0F2D_P_1,
1788   VEX_LEN_0F2D_P_3,
1789   VEX_LEN_0F2E_P_0,
1790   VEX_LEN_0F2E_P_2,
1791   VEX_LEN_0F2F_P_0,
1792   VEX_LEN_0F2F_P_2,
1793   VEX_LEN_0F41_P_0,
1794   VEX_LEN_0F41_P_2,
1795   VEX_LEN_0F42_P_0,
1796   VEX_LEN_0F42_P_2,
1797   VEX_LEN_0F44_P_0,
1798   VEX_LEN_0F44_P_2,
1799   VEX_LEN_0F45_P_0,
1800   VEX_LEN_0F45_P_2,
1801   VEX_LEN_0F46_P_0,
1802   VEX_LEN_0F46_P_2,
1803   VEX_LEN_0F47_P_0,
1804   VEX_LEN_0F47_P_2,
1805   VEX_LEN_0F4A_P_0,
1806   VEX_LEN_0F4A_P_2,
1807   VEX_LEN_0F4B_P_0,
1808   VEX_LEN_0F4B_P_2,
1809   VEX_LEN_0F51_P_1,
1810   VEX_LEN_0F51_P_3,
1811   VEX_LEN_0F52_P_1,
1812   VEX_LEN_0F53_P_1,
1813   VEX_LEN_0F58_P_1,
1814   VEX_LEN_0F58_P_3,
1815   VEX_LEN_0F59_P_1,
1816   VEX_LEN_0F59_P_3,
1817   VEX_LEN_0F5A_P_1,
1818   VEX_LEN_0F5A_P_3,
1819   VEX_LEN_0F5C_P_1,
1820   VEX_LEN_0F5C_P_3,
1821   VEX_LEN_0F5D_P_1,
1822   VEX_LEN_0F5D_P_3,
1823   VEX_LEN_0F5E_P_1,
1824   VEX_LEN_0F5E_P_3,
1825   VEX_LEN_0F5F_P_1,
1826   VEX_LEN_0F5F_P_3,
1827   VEX_LEN_0F6E_P_2,
1828   VEX_LEN_0F7E_P_1,
1829   VEX_LEN_0F7E_P_2,
1830   VEX_LEN_0F90_P_0,
1831   VEX_LEN_0F90_P_2,
1832   VEX_LEN_0F91_P_0,
1833   VEX_LEN_0F91_P_2,
1834   VEX_LEN_0F92_P_0,
1835   VEX_LEN_0F92_P_2,
1836   VEX_LEN_0F92_P_3,
1837   VEX_LEN_0F93_P_0,
1838   VEX_LEN_0F93_P_2,
1839   VEX_LEN_0F93_P_3,
1840   VEX_LEN_0F98_P_0,
1841   VEX_LEN_0F98_P_2,
1842   VEX_LEN_0F99_P_0,
1843   VEX_LEN_0F99_P_2,
1844   VEX_LEN_0FAE_R_2_M_0,
1845   VEX_LEN_0FAE_R_3_M_0,
1846   VEX_LEN_0FC2_P_1,
1847   VEX_LEN_0FC2_P_3,
1848   VEX_LEN_0FC4_P_2,
1849   VEX_LEN_0FC5_P_2,
1850   VEX_LEN_0FD6_P_2,
1851   VEX_LEN_0FF7_P_2,
1852   VEX_LEN_0F3816_P_2,
1853   VEX_LEN_0F3819_P_2,
1854   VEX_LEN_0F381A_P_2_M_0,
1855   VEX_LEN_0F3836_P_2,
1856   VEX_LEN_0F3841_P_2,
1857   VEX_LEN_0F385A_P_2_M_0,
1858   VEX_LEN_0F38DB_P_2,
1859   VEX_LEN_0F38DC_P_2,
1860   VEX_LEN_0F38DD_P_2,
1861   VEX_LEN_0F38DE_P_2,
1862   VEX_LEN_0F38DF_P_2,
1863   VEX_LEN_0F38F2_P_0,
1864   VEX_LEN_0F38F3_R_1_P_0,
1865   VEX_LEN_0F38F3_R_2_P_0,
1866   VEX_LEN_0F38F3_R_3_P_0,
1867   VEX_LEN_0F38F5_P_0,
1868   VEX_LEN_0F38F5_P_1,
1869   VEX_LEN_0F38F5_P_3,
1870   VEX_LEN_0F38F6_P_3,
1871   VEX_LEN_0F38F7_P_0,
1872   VEX_LEN_0F38F7_P_1,
1873   VEX_LEN_0F38F7_P_2,
1874   VEX_LEN_0F38F7_P_3,
1875   VEX_LEN_0F3A00_P_2,
1876   VEX_LEN_0F3A01_P_2,
1877   VEX_LEN_0F3A06_P_2,
1878   VEX_LEN_0F3A0A_P_2,
1879   VEX_LEN_0F3A0B_P_2,
1880   VEX_LEN_0F3A14_P_2,
1881   VEX_LEN_0F3A15_P_2,
1882   VEX_LEN_0F3A16_P_2,
1883   VEX_LEN_0F3A17_P_2,
1884   VEX_LEN_0F3A18_P_2,
1885   VEX_LEN_0F3A19_P_2,
1886   VEX_LEN_0F3A20_P_2,
1887   VEX_LEN_0F3A21_P_2,
1888   VEX_LEN_0F3A22_P_2,
1889   VEX_LEN_0F3A30_P_2,
1890   VEX_LEN_0F3A31_P_2,
1891   VEX_LEN_0F3A32_P_2,
1892   VEX_LEN_0F3A33_P_2,
1893   VEX_LEN_0F3A38_P_2,
1894   VEX_LEN_0F3A39_P_2,
1895   VEX_LEN_0F3A41_P_2,
1896   VEX_LEN_0F3A44_P_2,
1897   VEX_LEN_0F3A46_P_2,
1898   VEX_LEN_0F3A60_P_2,
1899   VEX_LEN_0F3A61_P_2,
1900   VEX_LEN_0F3A62_P_2,
1901   VEX_LEN_0F3A63_P_2,
1902   VEX_LEN_0F3A6A_P_2,
1903   VEX_LEN_0F3A6B_P_2,
1904   VEX_LEN_0F3A6E_P_2,
1905   VEX_LEN_0F3A6F_P_2,
1906   VEX_LEN_0F3A7A_P_2,
1907   VEX_LEN_0F3A7B_P_2,
1908   VEX_LEN_0F3A7E_P_2,
1909   VEX_LEN_0F3A7F_P_2,
1910   VEX_LEN_0F3ADF_P_2,
1911   VEX_LEN_0F3AF0_P_3,
1912   VEX_LEN_0FXOP_08_CC,
1913   VEX_LEN_0FXOP_08_CD,
1914   VEX_LEN_0FXOP_08_CE,
1915   VEX_LEN_0FXOP_08_CF,
1916   VEX_LEN_0FXOP_08_EC,
1917   VEX_LEN_0FXOP_08_ED,
1918   VEX_LEN_0FXOP_08_EE,
1919   VEX_LEN_0FXOP_08_EF,
1920   VEX_LEN_0FXOP_09_80,
1921   VEX_LEN_0FXOP_09_81
1922 };
1923
1924 enum
1925 {
1926   VEX_W_0F10_P_0 = 0,
1927   VEX_W_0F10_P_1,
1928   VEX_W_0F10_P_2,
1929   VEX_W_0F10_P_3,
1930   VEX_W_0F11_P_0,
1931   VEX_W_0F11_P_1,
1932   VEX_W_0F11_P_2,
1933   VEX_W_0F11_P_3,
1934   VEX_W_0F12_P_0_M_0,
1935   VEX_W_0F12_P_0_M_1,
1936   VEX_W_0F12_P_1,
1937   VEX_W_0F12_P_2,
1938   VEX_W_0F12_P_3,
1939   VEX_W_0F13_M_0,
1940   VEX_W_0F14,
1941   VEX_W_0F15,
1942   VEX_W_0F16_P_0_M_0,
1943   VEX_W_0F16_P_0_M_1,
1944   VEX_W_0F16_P_1,
1945   VEX_W_0F16_P_2,
1946   VEX_W_0F17_M_0,
1947   VEX_W_0F28,
1948   VEX_W_0F29,
1949   VEX_W_0F2B_M_0,
1950   VEX_W_0F2E_P_0,
1951   VEX_W_0F2E_P_2,
1952   VEX_W_0F2F_P_0,
1953   VEX_W_0F2F_P_2,
1954   VEX_W_0F41_P_0_LEN_1,
1955   VEX_W_0F41_P_2_LEN_1,
1956   VEX_W_0F42_P_0_LEN_1,
1957   VEX_W_0F42_P_2_LEN_1,
1958   VEX_W_0F44_P_0_LEN_0,
1959   VEX_W_0F44_P_2_LEN_0,
1960   VEX_W_0F45_P_0_LEN_1,
1961   VEX_W_0F45_P_2_LEN_1,
1962   VEX_W_0F46_P_0_LEN_1,
1963   VEX_W_0F46_P_2_LEN_1,
1964   VEX_W_0F47_P_0_LEN_1,
1965   VEX_W_0F47_P_2_LEN_1,
1966   VEX_W_0F4A_P_0_LEN_1,
1967   VEX_W_0F4A_P_2_LEN_1,
1968   VEX_W_0F4B_P_0_LEN_1,
1969   VEX_W_0F4B_P_2_LEN_1,
1970   VEX_W_0F50_M_0,
1971   VEX_W_0F51_P_0,
1972   VEX_W_0F51_P_1,
1973   VEX_W_0F51_P_2,
1974   VEX_W_0F51_P_3,
1975   VEX_W_0F52_P_0,
1976   VEX_W_0F52_P_1,
1977   VEX_W_0F53_P_0,
1978   VEX_W_0F53_P_1,
1979   VEX_W_0F58_P_0,
1980   VEX_W_0F58_P_1,
1981   VEX_W_0F58_P_2,
1982   VEX_W_0F58_P_3,
1983   VEX_W_0F59_P_0,
1984   VEX_W_0F59_P_1,
1985   VEX_W_0F59_P_2,
1986   VEX_W_0F59_P_3,
1987   VEX_W_0F5A_P_0,
1988   VEX_W_0F5A_P_1,
1989   VEX_W_0F5A_P_3,
1990   VEX_W_0F5B_P_0,
1991   VEX_W_0F5B_P_1,
1992   VEX_W_0F5B_P_2,
1993   VEX_W_0F5C_P_0,
1994   VEX_W_0F5C_P_1,
1995   VEX_W_0F5C_P_2,
1996   VEX_W_0F5C_P_3,
1997   VEX_W_0F5D_P_0,
1998   VEX_W_0F5D_P_1,
1999   VEX_W_0F5D_P_2,
2000   VEX_W_0F5D_P_3,
2001   VEX_W_0F5E_P_0,
2002   VEX_W_0F5E_P_1,
2003   VEX_W_0F5E_P_2,
2004   VEX_W_0F5E_P_3,
2005   VEX_W_0F5F_P_0,
2006   VEX_W_0F5F_P_1,
2007   VEX_W_0F5F_P_2,
2008   VEX_W_0F5F_P_3,
2009   VEX_W_0F60_P_2,
2010   VEX_W_0F61_P_2,
2011   VEX_W_0F62_P_2,
2012   VEX_W_0F63_P_2,
2013   VEX_W_0F64_P_2,
2014   VEX_W_0F65_P_2,
2015   VEX_W_0F66_P_2,
2016   VEX_W_0F67_P_2,
2017   VEX_W_0F68_P_2,
2018   VEX_W_0F69_P_2,
2019   VEX_W_0F6A_P_2,
2020   VEX_W_0F6B_P_2,
2021   VEX_W_0F6C_P_2,
2022   VEX_W_0F6D_P_2,
2023   VEX_W_0F6F_P_1,
2024   VEX_W_0F6F_P_2,
2025   VEX_W_0F70_P_1,
2026   VEX_W_0F70_P_2,
2027   VEX_W_0F70_P_3,
2028   VEX_W_0F71_R_2_P_2,
2029   VEX_W_0F71_R_4_P_2,
2030   VEX_W_0F71_R_6_P_2,
2031   VEX_W_0F72_R_2_P_2,
2032   VEX_W_0F72_R_4_P_2,
2033   VEX_W_0F72_R_6_P_2,
2034   VEX_W_0F73_R_2_P_2,
2035   VEX_W_0F73_R_3_P_2,
2036   VEX_W_0F73_R_6_P_2,
2037   VEX_W_0F73_R_7_P_2,
2038   VEX_W_0F74_P_2,
2039   VEX_W_0F75_P_2,
2040   VEX_W_0F76_P_2,
2041   VEX_W_0F77_P_0,
2042   VEX_W_0F7C_P_2,
2043   VEX_W_0F7C_P_3,
2044   VEX_W_0F7D_P_2,
2045   VEX_W_0F7D_P_3,
2046   VEX_W_0F7E_P_1,
2047   VEX_W_0F7F_P_1,
2048   VEX_W_0F7F_P_2,
2049   VEX_W_0F90_P_0_LEN_0,
2050   VEX_W_0F90_P_2_LEN_0,
2051   VEX_W_0F91_P_0_LEN_0,
2052   VEX_W_0F91_P_2_LEN_0,
2053   VEX_W_0F92_P_0_LEN_0,
2054   VEX_W_0F92_P_2_LEN_0,
2055   VEX_W_0F92_P_3_LEN_0,
2056   VEX_W_0F93_P_0_LEN_0,
2057   VEX_W_0F93_P_2_LEN_0,
2058   VEX_W_0F93_P_3_LEN_0,
2059   VEX_W_0F98_P_0_LEN_0,
2060   VEX_W_0F98_P_2_LEN_0,
2061   VEX_W_0F99_P_0_LEN_0,
2062   VEX_W_0F99_P_2_LEN_0,
2063   VEX_W_0FAE_R_2_M_0,
2064   VEX_W_0FAE_R_3_M_0,
2065   VEX_W_0FC2_P_0,
2066   VEX_W_0FC2_P_1,
2067   VEX_W_0FC2_P_2,
2068   VEX_W_0FC2_P_3,
2069   VEX_W_0FC4_P_2,
2070   VEX_W_0FC5_P_2,
2071   VEX_W_0FD0_P_2,
2072   VEX_W_0FD0_P_3,
2073   VEX_W_0FD1_P_2,
2074   VEX_W_0FD2_P_2,
2075   VEX_W_0FD3_P_2,
2076   VEX_W_0FD4_P_2,
2077   VEX_W_0FD5_P_2,
2078   VEX_W_0FD6_P_2,
2079   VEX_W_0FD7_P_2_M_1,
2080   VEX_W_0FD8_P_2,
2081   VEX_W_0FD9_P_2,
2082   VEX_W_0FDA_P_2,
2083   VEX_W_0FDB_P_2,
2084   VEX_W_0FDC_P_2,
2085   VEX_W_0FDD_P_2,
2086   VEX_W_0FDE_P_2,
2087   VEX_W_0FDF_P_2,
2088   VEX_W_0FE0_P_2,
2089   VEX_W_0FE1_P_2,
2090   VEX_W_0FE2_P_2,
2091   VEX_W_0FE3_P_2,
2092   VEX_W_0FE4_P_2,
2093   VEX_W_0FE5_P_2,
2094   VEX_W_0FE6_P_1,
2095   VEX_W_0FE6_P_2,
2096   VEX_W_0FE6_P_3,
2097   VEX_W_0FE7_P_2_M_0,
2098   VEX_W_0FE8_P_2,
2099   VEX_W_0FE9_P_2,
2100   VEX_W_0FEA_P_2,
2101   VEX_W_0FEB_P_2,
2102   VEX_W_0FEC_P_2,
2103   VEX_W_0FED_P_2,
2104   VEX_W_0FEE_P_2,
2105   VEX_W_0FEF_P_2,
2106   VEX_W_0FF0_P_3_M_0,
2107   VEX_W_0FF1_P_2,
2108   VEX_W_0FF2_P_2,
2109   VEX_W_0FF3_P_2,
2110   VEX_W_0FF4_P_2,
2111   VEX_W_0FF5_P_2,
2112   VEX_W_0FF6_P_2,
2113   VEX_W_0FF7_P_2,
2114   VEX_W_0FF8_P_2,
2115   VEX_W_0FF9_P_2,
2116   VEX_W_0FFA_P_2,
2117   VEX_W_0FFB_P_2,
2118   VEX_W_0FFC_P_2,
2119   VEX_W_0FFD_P_2,
2120   VEX_W_0FFE_P_2,
2121   VEX_W_0F3800_P_2,
2122   VEX_W_0F3801_P_2,
2123   VEX_W_0F3802_P_2,
2124   VEX_W_0F3803_P_2,
2125   VEX_W_0F3804_P_2,
2126   VEX_W_0F3805_P_2,
2127   VEX_W_0F3806_P_2,
2128   VEX_W_0F3807_P_2,
2129   VEX_W_0F3808_P_2,
2130   VEX_W_0F3809_P_2,
2131   VEX_W_0F380A_P_2,
2132   VEX_W_0F380B_P_2,
2133   VEX_W_0F380C_P_2,
2134   VEX_W_0F380D_P_2,
2135   VEX_W_0F380E_P_2,
2136   VEX_W_0F380F_P_2,
2137   VEX_W_0F3816_P_2,
2138   VEX_W_0F3817_P_2,
2139   VEX_W_0F3818_P_2,
2140   VEX_W_0F3819_P_2,
2141   VEX_W_0F381A_P_2_M_0,
2142   VEX_W_0F381C_P_2,
2143   VEX_W_0F381D_P_2,
2144   VEX_W_0F381E_P_2,
2145   VEX_W_0F3820_P_2,
2146   VEX_W_0F3821_P_2,
2147   VEX_W_0F3822_P_2,
2148   VEX_W_0F3823_P_2,
2149   VEX_W_0F3824_P_2,
2150   VEX_W_0F3825_P_2,
2151   VEX_W_0F3828_P_2,
2152   VEX_W_0F3829_P_2,
2153   VEX_W_0F382A_P_2_M_0,
2154   VEX_W_0F382B_P_2,
2155   VEX_W_0F382C_P_2_M_0,
2156   VEX_W_0F382D_P_2_M_0,
2157   VEX_W_0F382E_P_2_M_0,
2158   VEX_W_0F382F_P_2_M_0,
2159   VEX_W_0F3830_P_2,
2160   VEX_W_0F3831_P_2,
2161   VEX_W_0F3832_P_2,
2162   VEX_W_0F3833_P_2,
2163   VEX_W_0F3834_P_2,
2164   VEX_W_0F3835_P_2,
2165   VEX_W_0F3836_P_2,
2166   VEX_W_0F3837_P_2,
2167   VEX_W_0F3838_P_2,
2168   VEX_W_0F3839_P_2,
2169   VEX_W_0F383A_P_2,
2170   VEX_W_0F383B_P_2,
2171   VEX_W_0F383C_P_2,
2172   VEX_W_0F383D_P_2,
2173   VEX_W_0F383E_P_2,
2174   VEX_W_0F383F_P_2,
2175   VEX_W_0F3840_P_2,
2176   VEX_W_0F3841_P_2,
2177   VEX_W_0F3846_P_2,
2178   VEX_W_0F3858_P_2,
2179   VEX_W_0F3859_P_2,
2180   VEX_W_0F385A_P_2_M_0,
2181   VEX_W_0F3878_P_2,
2182   VEX_W_0F3879_P_2,
2183   VEX_W_0F38DB_P_2,
2184   VEX_W_0F38DC_P_2,
2185   VEX_W_0F38DD_P_2,
2186   VEX_W_0F38DE_P_2,
2187   VEX_W_0F38DF_P_2,
2188   VEX_W_0F3A00_P_2,
2189   VEX_W_0F3A01_P_2,
2190   VEX_W_0F3A02_P_2,
2191   VEX_W_0F3A04_P_2,
2192   VEX_W_0F3A05_P_2,
2193   VEX_W_0F3A06_P_2,
2194   VEX_W_0F3A08_P_2,
2195   VEX_W_0F3A09_P_2,
2196   VEX_W_0F3A0A_P_2,
2197   VEX_W_0F3A0B_P_2,
2198   VEX_W_0F3A0C_P_2,
2199   VEX_W_0F3A0D_P_2,
2200   VEX_W_0F3A0E_P_2,
2201   VEX_W_0F3A0F_P_2,
2202   VEX_W_0F3A14_P_2,
2203   VEX_W_0F3A15_P_2,
2204   VEX_W_0F3A18_P_2,
2205   VEX_W_0F3A19_P_2,
2206   VEX_W_0F3A20_P_2,
2207   VEX_W_0F3A21_P_2,
2208   VEX_W_0F3A30_P_2_LEN_0,
2209   VEX_W_0F3A31_P_2_LEN_0,
2210   VEX_W_0F3A32_P_2_LEN_0,
2211   VEX_W_0F3A33_P_2_LEN_0,
2212   VEX_W_0F3A38_P_2,
2213   VEX_W_0F3A39_P_2,
2214   VEX_W_0F3A40_P_2,
2215   VEX_W_0F3A41_P_2,
2216   VEX_W_0F3A42_P_2,
2217   VEX_W_0F3A44_P_2,
2218   VEX_W_0F3A46_P_2,
2219   VEX_W_0F3A48_P_2,
2220   VEX_W_0F3A49_P_2,
2221   VEX_W_0F3A4A_P_2,
2222   VEX_W_0F3A4B_P_2,
2223   VEX_W_0F3A4C_P_2,
2224   VEX_W_0F3A62_P_2,
2225   VEX_W_0F3A63_P_2,
2226   VEX_W_0F3ADF_P_2,
2227
2228   EVEX_W_0F10_P_0,
2229   EVEX_W_0F10_P_1_M_0,
2230   EVEX_W_0F10_P_1_M_1,
2231   EVEX_W_0F10_P_2,
2232   EVEX_W_0F10_P_3_M_0,
2233   EVEX_W_0F10_P_3_M_1,
2234   EVEX_W_0F11_P_0,
2235   EVEX_W_0F11_P_1_M_0,
2236   EVEX_W_0F11_P_1_M_1,
2237   EVEX_W_0F11_P_2,
2238   EVEX_W_0F11_P_3_M_0,
2239   EVEX_W_0F11_P_3_M_1,
2240   EVEX_W_0F12_P_0_M_0,
2241   EVEX_W_0F12_P_0_M_1,
2242   EVEX_W_0F12_P_1,
2243   EVEX_W_0F12_P_2,
2244   EVEX_W_0F12_P_3,
2245   EVEX_W_0F13_P_0,
2246   EVEX_W_0F13_P_2,
2247   EVEX_W_0F14_P_0,
2248   EVEX_W_0F14_P_2,
2249   EVEX_W_0F15_P_0,
2250   EVEX_W_0F15_P_2,
2251   EVEX_W_0F16_P_0_M_0,
2252   EVEX_W_0F16_P_0_M_1,
2253   EVEX_W_0F16_P_1,
2254   EVEX_W_0F16_P_2,
2255   EVEX_W_0F17_P_0,
2256   EVEX_W_0F17_P_2,
2257   EVEX_W_0F28_P_0,
2258   EVEX_W_0F28_P_2,
2259   EVEX_W_0F29_P_0,
2260   EVEX_W_0F29_P_2,
2261   EVEX_W_0F2A_P_1,
2262   EVEX_W_0F2A_P_3,
2263   EVEX_W_0F2B_P_0,
2264   EVEX_W_0F2B_P_2,
2265   EVEX_W_0F2E_P_0,
2266   EVEX_W_0F2E_P_2,
2267   EVEX_W_0F2F_P_0,
2268   EVEX_W_0F2F_P_2,
2269   EVEX_W_0F51_P_0,
2270   EVEX_W_0F51_P_1,
2271   EVEX_W_0F51_P_2,
2272   EVEX_W_0F51_P_3,
2273   EVEX_W_0F54_P_0,
2274   EVEX_W_0F54_P_2,
2275   EVEX_W_0F55_P_0,
2276   EVEX_W_0F55_P_2,
2277   EVEX_W_0F56_P_0,
2278   EVEX_W_0F56_P_2,
2279   EVEX_W_0F57_P_0,
2280   EVEX_W_0F57_P_2,
2281   EVEX_W_0F58_P_0,
2282   EVEX_W_0F58_P_1,
2283   EVEX_W_0F58_P_2,
2284   EVEX_W_0F58_P_3,
2285   EVEX_W_0F59_P_0,
2286   EVEX_W_0F59_P_1,
2287   EVEX_W_0F59_P_2,
2288   EVEX_W_0F59_P_3,
2289   EVEX_W_0F5A_P_0,
2290   EVEX_W_0F5A_P_1,
2291   EVEX_W_0F5A_P_2,
2292   EVEX_W_0F5A_P_3,
2293   EVEX_W_0F5B_P_0,
2294   EVEX_W_0F5B_P_1,
2295   EVEX_W_0F5B_P_2,
2296   EVEX_W_0F5C_P_0,
2297   EVEX_W_0F5C_P_1,
2298   EVEX_W_0F5C_P_2,
2299   EVEX_W_0F5C_P_3,
2300   EVEX_W_0F5D_P_0,
2301   EVEX_W_0F5D_P_1,
2302   EVEX_W_0F5D_P_2,
2303   EVEX_W_0F5D_P_3,
2304   EVEX_W_0F5E_P_0,
2305   EVEX_W_0F5E_P_1,
2306   EVEX_W_0F5E_P_2,
2307   EVEX_W_0F5E_P_3,
2308   EVEX_W_0F5F_P_0,
2309   EVEX_W_0F5F_P_1,
2310   EVEX_W_0F5F_P_2,
2311   EVEX_W_0F5F_P_3,
2312   EVEX_W_0F62_P_2,
2313   EVEX_W_0F66_P_2,
2314   EVEX_W_0F6A_P_2,
2315   EVEX_W_0F6B_P_2,
2316   EVEX_W_0F6C_P_2,
2317   EVEX_W_0F6D_P_2,
2318   EVEX_W_0F6E_P_2,
2319   EVEX_W_0F6F_P_1,
2320   EVEX_W_0F6F_P_2,
2321   EVEX_W_0F6F_P_3,
2322   EVEX_W_0F70_P_2,
2323   EVEX_W_0F72_R_2_P_2,
2324   EVEX_W_0F72_R_6_P_2,
2325   EVEX_W_0F73_R_2_P_2,
2326   EVEX_W_0F73_R_6_P_2,
2327   EVEX_W_0F76_P_2,
2328   EVEX_W_0F78_P_0,
2329   EVEX_W_0F78_P_2,
2330   EVEX_W_0F79_P_0,
2331   EVEX_W_0F79_P_2,
2332   EVEX_W_0F7A_P_1,
2333   EVEX_W_0F7A_P_2,
2334   EVEX_W_0F7A_P_3,
2335   EVEX_W_0F7B_P_1,
2336   EVEX_W_0F7B_P_2,
2337   EVEX_W_0F7B_P_3,
2338   EVEX_W_0F7E_P_1,
2339   EVEX_W_0F7E_P_2,
2340   EVEX_W_0F7F_P_1,
2341   EVEX_W_0F7F_P_2,
2342   EVEX_W_0F7F_P_3,
2343   EVEX_W_0FC2_P_0,
2344   EVEX_W_0FC2_P_1,
2345   EVEX_W_0FC2_P_2,
2346   EVEX_W_0FC2_P_3,
2347   EVEX_W_0FC6_P_0,
2348   EVEX_W_0FC6_P_2,
2349   EVEX_W_0FD2_P_2,
2350   EVEX_W_0FD3_P_2,
2351   EVEX_W_0FD4_P_2,
2352   EVEX_W_0FD6_P_2,
2353   EVEX_W_0FE6_P_1,
2354   EVEX_W_0FE6_P_2,
2355   EVEX_W_0FE6_P_3,
2356   EVEX_W_0FE7_P_2,
2357   EVEX_W_0FF2_P_2,
2358   EVEX_W_0FF3_P_2,
2359   EVEX_W_0FF4_P_2,
2360   EVEX_W_0FFA_P_2,
2361   EVEX_W_0FFB_P_2,
2362   EVEX_W_0FFE_P_2,
2363   EVEX_W_0F380C_P_2,
2364   EVEX_W_0F380D_P_2,
2365   EVEX_W_0F3810_P_1,
2366   EVEX_W_0F3810_P_2,
2367   EVEX_W_0F3811_P_1,
2368   EVEX_W_0F3811_P_2,
2369   EVEX_W_0F3812_P_1,
2370   EVEX_W_0F3812_P_2,
2371   EVEX_W_0F3813_P_1,
2372   EVEX_W_0F3813_P_2,
2373   EVEX_W_0F3814_P_1,
2374   EVEX_W_0F3815_P_1,
2375   EVEX_W_0F3818_P_2,
2376   EVEX_W_0F3819_P_2,
2377   EVEX_W_0F381A_P_2,
2378   EVEX_W_0F381B_P_2,
2379   EVEX_W_0F381E_P_2,
2380   EVEX_W_0F381F_P_2,
2381   EVEX_W_0F3820_P_1,
2382   EVEX_W_0F3821_P_1,
2383   EVEX_W_0F3822_P_1,
2384   EVEX_W_0F3823_P_1,
2385   EVEX_W_0F3824_P_1,
2386   EVEX_W_0F3825_P_1,
2387   EVEX_W_0F3825_P_2,
2388   EVEX_W_0F3826_P_1,
2389   EVEX_W_0F3826_P_2,
2390   EVEX_W_0F3828_P_1,
2391   EVEX_W_0F3828_P_2,
2392   EVEX_W_0F3829_P_1,
2393   EVEX_W_0F3829_P_2,
2394   EVEX_W_0F382A_P_1,
2395   EVEX_W_0F382A_P_2,
2396   EVEX_W_0F382B_P_2,
2397   EVEX_W_0F3830_P_1,
2398   EVEX_W_0F3831_P_1,
2399   EVEX_W_0F3832_P_1,
2400   EVEX_W_0F3833_P_1,
2401   EVEX_W_0F3834_P_1,
2402   EVEX_W_0F3835_P_1,
2403   EVEX_W_0F3835_P_2,
2404   EVEX_W_0F3837_P_2,
2405   EVEX_W_0F3838_P_1,
2406   EVEX_W_0F3839_P_1,
2407   EVEX_W_0F383A_P_1,
2408   EVEX_W_0F3840_P_2,
2409   EVEX_W_0F3855_P_2,
2410   EVEX_W_0F3858_P_2,
2411   EVEX_W_0F3859_P_2,
2412   EVEX_W_0F385A_P_2,
2413   EVEX_W_0F385B_P_2,
2414   EVEX_W_0F3862_P_2,
2415   EVEX_W_0F3863_P_2,
2416   EVEX_W_0F3866_P_2,
2417   EVEX_W_0F3870_P_2,
2418   EVEX_W_0F3871_P_2,
2419   EVEX_W_0F3872_P_2,
2420   EVEX_W_0F3873_P_2,
2421   EVEX_W_0F3875_P_2,
2422   EVEX_W_0F3878_P_2,
2423   EVEX_W_0F3879_P_2,
2424   EVEX_W_0F387A_P_2,
2425   EVEX_W_0F387B_P_2,
2426   EVEX_W_0F387D_P_2,
2427   EVEX_W_0F3883_P_2,
2428   EVEX_W_0F388D_P_2,
2429   EVEX_W_0F3891_P_2,
2430   EVEX_W_0F3893_P_2,
2431   EVEX_W_0F38A1_P_2,
2432   EVEX_W_0F38A3_P_2,
2433   EVEX_W_0F38C7_R_1_P_2,
2434   EVEX_W_0F38C7_R_2_P_2,
2435   EVEX_W_0F38C7_R_5_P_2,
2436   EVEX_W_0F38C7_R_6_P_2,
2437
2438   EVEX_W_0F3A00_P_2,
2439   EVEX_W_0F3A01_P_2,
2440   EVEX_W_0F3A04_P_2,
2441   EVEX_W_0F3A05_P_2,
2442   EVEX_W_0F3A08_P_2,
2443   EVEX_W_0F3A09_P_2,
2444   EVEX_W_0F3A0A_P_2,
2445   EVEX_W_0F3A0B_P_2,
2446   EVEX_W_0F3A16_P_2,
2447   EVEX_W_0F3A18_P_2,
2448   EVEX_W_0F3A19_P_2,
2449   EVEX_W_0F3A1A_P_2,
2450   EVEX_W_0F3A1B_P_2,
2451   EVEX_W_0F3A1D_P_2,
2452   EVEX_W_0F3A21_P_2,
2453   EVEX_W_0F3A22_P_2,
2454   EVEX_W_0F3A23_P_2,
2455   EVEX_W_0F3A38_P_2,
2456   EVEX_W_0F3A39_P_2,
2457   EVEX_W_0F3A3A_P_2,
2458   EVEX_W_0F3A3B_P_2,
2459   EVEX_W_0F3A3E_P_2,
2460   EVEX_W_0F3A3F_P_2,
2461   EVEX_W_0F3A42_P_2,
2462   EVEX_W_0F3A43_P_2,
2463   EVEX_W_0F3A50_P_2,
2464   EVEX_W_0F3A51_P_2,
2465   EVEX_W_0F3A56_P_2,
2466   EVEX_W_0F3A57_P_2,
2467   EVEX_W_0F3A66_P_2,
2468   EVEX_W_0F3A67_P_2,
2469   EVEX_W_0F3A70_P_2,
2470   EVEX_W_0F3A71_P_2,
2471   EVEX_W_0F3A72_P_2,
2472   EVEX_W_0F3A73_P_2
2473 };
2474
2475 typedef void (*op_rtn) (int bytemode, int sizeflag);
2476
2477 struct dis386 {
2478   const char *name;
2479   struct
2480     {
2481       op_rtn rtn;
2482       int bytemode;
2483     } op[MAX_OPERANDS];
2484   unsigned int prefix_requirement;
2485 };
2486
2487 /* Upper case letters in the instruction names here are macros.
2488    'A' => print 'b' if no register operands or suffix_always is true
2489    'B' => print 'b' if suffix_always is true
2490    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2491           size prefix
2492    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2493           suffix_always is true
2494    'E' => print 'e' if 32-bit form of jcxz
2495    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2496    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2497    'H' => print ",pt" or ",pn" branch hint
2498    'I' => honor following macro letter even in Intel mode (implemented only
2499           for some of the macro letters)
2500    'J' => print 'l'
2501    'K' => print 'd' or 'q' if rex prefix is present.
2502    'L' => print 'l' if suffix_always is true
2503    'M' => print 'r' if intel_mnemonic is false.
2504    'N' => print 'n' if instruction has no wait "prefix"
2505    'O' => print 'd' or 'o' (or 'q' in Intel mode)
2506    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2507           or suffix_always is true.  print 'q' if rex prefix is present.
2508    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2509           is true
2510    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2511    'S' => print 'w', 'l' or 'q' if suffix_always is true
2512    'T' => print 'q' in 64bit mode if instruction has no operand size
2513           prefix and behave as 'P' otherwise
2514    'U' => print 'q' in 64bit mode if instruction has no operand size
2515           prefix and behave as 'Q' otherwise
2516    'V' => print 'q' in 64bit mode if instruction has no operand size
2517           prefix and behave as 'S' otherwise
2518    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2519    'X' => print 's', 'd' depending on data16 prefix (for XMM)
2520    'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
2521           suffix_always is true.
2522    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2523    '!' => change condition from true to false or from false to true.
2524    '%' => add 1 upper case letter to the macro.
2525    '^' => print 'w' or 'l' depending on operand size prefix or
2526           suffix_always is true (lcall/ljmp).
2527    '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2528           on operand size prefix.
2529    '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2530           has no operand size prefix for AMD64 ISA, behave as 'P'
2531           otherwise
2532
2533    2 upper case letter macros:
2534    "XY" => print 'x' or 'y' if suffix_always is true or no register
2535            operands and no broadcast.
2536    "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2537            register operands and no broadcast.
2538    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2539    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2540            or suffix_always is true
2541    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2542    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2543    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2544    "LW" => print 'd', 'q' depending on the VEX.W bit
2545    "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2546            an operand size prefix, or suffix_always is true.  print
2547            'q' if rex prefix is present.
2548
2549    Many of the above letters print nothing in Intel mode.  See "putop"
2550    for the details.
2551
2552    Braces '{' and '}', and vertical bars '|', indicate alternative
2553    mnemonic strings for AT&T and Intel.  */
2554
2555 static const struct dis386 dis386[] = {
2556   /* 00 */
2557   { "addB",             { Ebh1, Gb }, 0 },
2558   { "addS",             { Evh1, Gv }, 0 },
2559   { "addB",             { Gb, EbS }, 0 },
2560   { "addS",             { Gv, EvS }, 0 },
2561   { "addB",             { AL, Ib }, 0 },
2562   { "addS",             { eAX, Iv }, 0 },
2563   { X86_64_TABLE (X86_64_06) },
2564   { X86_64_TABLE (X86_64_07) },
2565   /* 08 */
2566   { "orB",              { Ebh1, Gb }, 0 },
2567   { "orS",              { Evh1, Gv }, 0 },
2568   { "orB",              { Gb, EbS }, 0 },
2569   { "orS",              { Gv, EvS }, 0 },
2570   { "orB",              { AL, Ib }, 0 },
2571   { "orS",              { eAX, Iv }, 0 },
2572   { X86_64_TABLE (X86_64_0D) },
2573   { Bad_Opcode },       /* 0x0f extended opcode escape */
2574   /* 10 */
2575   { "adcB",             { Ebh1, Gb }, 0 },
2576   { "adcS",             { Evh1, Gv }, 0 },
2577   { "adcB",             { Gb, EbS }, 0 },
2578   { "adcS",             { Gv, EvS }, 0 },
2579   { "adcB",             { AL, Ib }, 0 },
2580   { "adcS",             { eAX, Iv }, 0 },
2581   { X86_64_TABLE (X86_64_16) },
2582   { X86_64_TABLE (X86_64_17) },
2583   /* 18 */
2584   { "sbbB",             { Ebh1, Gb }, 0 },
2585   { "sbbS",             { Evh1, Gv }, 0 },
2586   { "sbbB",             { Gb, EbS }, 0 },
2587   { "sbbS",             { Gv, EvS }, 0 },
2588   { "sbbB",             { AL, Ib }, 0 },
2589   { "sbbS",             { eAX, Iv }, 0 },
2590   { X86_64_TABLE (X86_64_1E) },
2591   { X86_64_TABLE (X86_64_1F) },
2592   /* 20 */
2593   { "andB",             { Ebh1, Gb }, 0 },
2594   { "andS",             { Evh1, Gv }, 0 },
2595   { "andB",             { Gb, EbS }, 0 },
2596   { "andS",             { Gv, EvS }, 0 },
2597   { "andB",             { AL, Ib }, 0 },
2598   { "andS",             { eAX, Iv }, 0 },
2599   { Bad_Opcode },       /* SEG ES prefix */
2600   { X86_64_TABLE (X86_64_27) },
2601   /* 28 */
2602   { "subB",             { Ebh1, Gb }, 0 },
2603   { "subS",             { Evh1, Gv }, 0 },
2604   { "subB",             { Gb, EbS }, 0 },
2605   { "subS",             { Gv, EvS }, 0 },
2606   { "subB",             { AL, Ib }, 0 },
2607   { "subS",             { eAX, Iv }, 0 },
2608   { Bad_Opcode },       /* SEG CS prefix */
2609   { X86_64_TABLE (X86_64_2F) },
2610   /* 30 */
2611   { "xorB",             { Ebh1, Gb }, 0 },
2612   { "xorS",             { Evh1, Gv }, 0 },
2613   { "xorB",             { Gb, EbS }, 0 },
2614   { "xorS",             { Gv, EvS }, 0 },
2615   { "xorB",             { AL, Ib }, 0 },
2616   { "xorS",             { eAX, Iv }, 0 },
2617   { Bad_Opcode },       /* SEG SS prefix */
2618   { X86_64_TABLE (X86_64_37) },
2619   /* 38 */
2620   { "cmpB",             { Eb, Gb }, 0 },
2621   { "cmpS",             { Ev, Gv }, 0 },
2622   { "cmpB",             { Gb, EbS }, 0 },
2623   { "cmpS",             { Gv, EvS }, 0 },
2624   { "cmpB",             { AL, Ib }, 0 },
2625   { "cmpS",             { eAX, Iv }, 0 },
2626   { Bad_Opcode },       /* SEG DS prefix */
2627   { X86_64_TABLE (X86_64_3F) },
2628   /* 40 */
2629   { "inc{S|}",          { RMeAX }, 0 },
2630   { "inc{S|}",          { RMeCX }, 0 },
2631   { "inc{S|}",          { RMeDX }, 0 },
2632   { "inc{S|}",          { RMeBX }, 0 },
2633   { "inc{S|}",          { RMeSP }, 0 },
2634   { "inc{S|}",          { RMeBP }, 0 },
2635   { "inc{S|}",          { RMeSI }, 0 },
2636   { "inc{S|}",          { RMeDI }, 0 },
2637   /* 48 */
2638   { "dec{S|}",          { RMeAX }, 0 },
2639   { "dec{S|}",          { RMeCX }, 0 },
2640   { "dec{S|}",          { RMeDX }, 0 },
2641   { "dec{S|}",          { RMeBX }, 0 },
2642   { "dec{S|}",          { RMeSP }, 0 },
2643   { "dec{S|}",          { RMeBP }, 0 },
2644   { "dec{S|}",          { RMeSI }, 0 },
2645   { "dec{S|}",          { RMeDI }, 0 },
2646   /* 50 */
2647   { "pushV",            { RMrAX }, 0 },
2648   { "pushV",            { RMrCX }, 0 },
2649   { "pushV",            { RMrDX }, 0 },
2650   { "pushV",            { RMrBX }, 0 },
2651   { "pushV",            { RMrSP }, 0 },
2652   { "pushV",            { RMrBP }, 0 },
2653   { "pushV",            { RMrSI }, 0 },
2654   { "pushV",            { RMrDI }, 0 },
2655   /* 58 */
2656   { "popV",             { RMrAX }, 0 },
2657   { "popV",             { RMrCX }, 0 },
2658   { "popV",             { RMrDX }, 0 },
2659   { "popV",             { RMrBX }, 0 },
2660   { "popV",             { RMrSP }, 0 },
2661   { "popV",             { RMrBP }, 0 },
2662   { "popV",             { RMrSI }, 0 },
2663   { "popV",             { RMrDI }, 0 },
2664   /* 60 */
2665   { X86_64_TABLE (X86_64_60) },
2666   { X86_64_TABLE (X86_64_61) },
2667   { X86_64_TABLE (X86_64_62) },
2668   { X86_64_TABLE (X86_64_63) },
2669   { Bad_Opcode },       /* seg fs */
2670   { Bad_Opcode },       /* seg gs */
2671   { Bad_Opcode },       /* op size prefix */
2672   { Bad_Opcode },       /* adr size prefix */
2673   /* 68 */
2674   { "pushT",            { sIv }, 0 },
2675   { "imulS",            { Gv, Ev, Iv }, 0 },
2676   { "pushT",            { sIbT }, 0 },
2677   { "imulS",            { Gv, Ev, sIb }, 0 },
2678   { "ins{b|}",          { Ybr, indirDX }, 0 },
2679   { X86_64_TABLE (X86_64_6D) },
2680   { "outs{b|}",         { indirDXr, Xb }, 0 },
2681   { X86_64_TABLE (X86_64_6F) },
2682   /* 70 */
2683   { "joH",              { Jb, BND, cond_jump_flag }, 0 },
2684   { "jnoH",             { Jb, BND, cond_jump_flag }, 0 },
2685   { "jbH",              { Jb, BND, cond_jump_flag }, 0 },
2686   { "jaeH",             { Jb, BND, cond_jump_flag }, 0 },
2687   { "jeH",              { Jb, BND, cond_jump_flag }, 0 },
2688   { "jneH",             { Jb, BND, cond_jump_flag }, 0 },
2689   { "jbeH",             { Jb, BND, cond_jump_flag }, 0 },
2690   { "jaH",              { Jb, BND, cond_jump_flag }, 0 },
2691   /* 78 */
2692   { "jsH",              { Jb, BND, cond_jump_flag }, 0 },
2693   { "jnsH",             { Jb, BND, cond_jump_flag }, 0 },
2694   { "jpH",              { Jb, BND, cond_jump_flag }, 0 },
2695   { "jnpH",             { Jb, BND, cond_jump_flag }, 0 },
2696   { "jlH",              { Jb, BND, cond_jump_flag }, 0 },
2697   { "jgeH",             { Jb, BND, cond_jump_flag }, 0 },
2698   { "jleH",             { Jb, BND, cond_jump_flag }, 0 },
2699   { "jgH",              { Jb, BND, cond_jump_flag }, 0 },
2700   /* 80 */
2701   { REG_TABLE (REG_80) },
2702   { REG_TABLE (REG_81) },
2703   { X86_64_TABLE (X86_64_82) },
2704   { REG_TABLE (REG_83) },
2705   { "testB",            { Eb, Gb }, 0 },
2706   { "testS",            { Ev, Gv }, 0 },
2707   { "xchgB",            { Ebh2, Gb }, 0 },
2708   { "xchgS",            { Evh2, Gv }, 0 },
2709   /* 88 */
2710   { "movB",             { Ebh3, Gb }, 0 },
2711   { "movS",             { Evh3, Gv }, 0 },
2712   { "movB",             { Gb, EbS }, 0 },
2713   { "movS",             { Gv, EvS }, 0 },
2714   { "movD",             { Sv, Sw }, 0 },
2715   { MOD_TABLE (MOD_8D) },
2716   { "movD",             { Sw, Sv }, 0 },
2717   { REG_TABLE (REG_8F) },
2718   /* 90 */
2719   { PREFIX_TABLE (PREFIX_90) },
2720   { "xchgS",            { RMeCX, eAX }, 0 },
2721   { "xchgS",            { RMeDX, eAX }, 0 },
2722   { "xchgS",            { RMeBX, eAX }, 0 },
2723   { "xchgS",            { RMeSP, eAX }, 0 },
2724   { "xchgS",            { RMeBP, eAX }, 0 },
2725   { "xchgS",            { RMeSI, eAX }, 0 },
2726   { "xchgS",            { RMeDI, eAX }, 0 },
2727   /* 98 */
2728   { "cW{t|}R",          { XX }, 0 },
2729   { "cR{t|}O",          { XX }, 0 },
2730   { X86_64_TABLE (X86_64_9A) },
2731   { Bad_Opcode },       /* fwait */
2732   { "pushfT",           { XX }, 0 },
2733   { "popfT",            { XX }, 0 },
2734   { "sahf",             { XX }, 0 },
2735   { "lahf",             { XX }, 0 },
2736   /* a0 */
2737   { "mov%LB",           { AL, Ob }, 0 },
2738   { "mov%LS",           { eAX, Ov }, 0 },
2739   { "mov%LB",           { Ob, AL }, 0 },
2740   { "mov%LS",           { Ov, eAX }, 0 },
2741   { "movs{b|}",         { Ybr, Xb }, 0 },
2742   { "movs{R|}",         { Yvr, Xv }, 0 },
2743   { "cmps{b|}",         { Xb, Yb }, 0 },
2744   { "cmps{R|}",         { Xv, Yv }, 0 },
2745   /* a8 */
2746   { "testB",            { AL, Ib }, 0 },
2747   { "testS",            { eAX, Iv }, 0 },
2748   { "stosB",            { Ybr, AL }, 0 },
2749   { "stosS",            { Yvr, eAX }, 0 },
2750   { "lodsB",            { ALr, Xb }, 0 },
2751   { "lodsS",            { eAXr, Xv }, 0 },
2752   { "scasB",            { AL, Yb }, 0 },
2753   { "scasS",            { eAX, Yv }, 0 },
2754   /* b0 */
2755   { "movB",             { RMAL, Ib }, 0 },
2756   { "movB",             { RMCL, Ib }, 0 },
2757   { "movB",             { RMDL, Ib }, 0 },
2758   { "movB",             { RMBL, Ib }, 0 },
2759   { "movB",             { RMAH, Ib }, 0 },
2760   { "movB",             { RMCH, Ib }, 0 },
2761   { "movB",             { RMDH, Ib }, 0 },
2762   { "movB",             { RMBH, Ib }, 0 },
2763   /* b8 */
2764   { "mov%LV",           { RMeAX, Iv64 }, 0 },
2765   { "mov%LV",           { RMeCX, Iv64 }, 0 },
2766   { "mov%LV",           { RMeDX, Iv64 }, 0 },
2767   { "mov%LV",           { RMeBX, Iv64 }, 0 },
2768   { "mov%LV",           { RMeSP, Iv64 }, 0 },
2769   { "mov%LV",           { RMeBP, Iv64 }, 0 },
2770   { "mov%LV",           { RMeSI, Iv64 }, 0 },
2771   { "mov%LV",           { RMeDI, Iv64 }, 0 },
2772   /* c0 */
2773   { REG_TABLE (REG_C0) },
2774   { REG_TABLE (REG_C1) },
2775   { "retT",             { Iw, BND }, 0 },
2776   { "retT",             { BND }, 0 },
2777   { X86_64_TABLE (X86_64_C4) },
2778   { X86_64_TABLE (X86_64_C5) },
2779   { REG_TABLE (REG_C6) },
2780   { REG_TABLE (REG_C7) },
2781   /* c8 */
2782   { "enterT",           { Iw, Ib }, 0 },
2783   { "leaveT",           { XX }, 0 },
2784   { "Jret{|f}P",        { Iw }, 0 },
2785   { "Jret{|f}P",        { XX }, 0 },
2786   { "int3",             { XX }, 0 },
2787   { "int",              { Ib }, 0 },
2788   { X86_64_TABLE (X86_64_CE) },
2789   { "iret%LP",          { XX }, 0 },
2790   /* d0 */
2791   { REG_TABLE (REG_D0) },
2792   { REG_TABLE (REG_D1) },
2793   { REG_TABLE (REG_D2) },
2794   { REG_TABLE (REG_D3) },
2795   { X86_64_TABLE (X86_64_D4) },
2796   { X86_64_TABLE (X86_64_D5) },
2797   { Bad_Opcode },
2798   { "xlat",             { DSBX }, 0 },
2799   /* d8 */
2800   { FLOAT },
2801   { FLOAT },
2802   { FLOAT },
2803   { FLOAT },
2804   { FLOAT },
2805   { FLOAT },
2806   { FLOAT },
2807   { FLOAT },
2808   /* e0 */
2809   { "loopneFH",         { Jb, XX, loop_jcxz_flag }, 0 },
2810   { "loopeFH",          { Jb, XX, loop_jcxz_flag }, 0 },
2811   { "loopFH",           { Jb, XX, loop_jcxz_flag }, 0 },
2812   { "jEcxzH",           { Jb, XX, loop_jcxz_flag }, 0 },
2813   { "inB",              { AL, Ib }, 0 },
2814   { "inG",              { zAX, Ib }, 0 },
2815   { "outB",             { Ib, AL }, 0 },
2816   { "outG",             { Ib, zAX }, 0 },
2817   /* e8 */
2818   { X86_64_TABLE (X86_64_E8) },
2819   { X86_64_TABLE (X86_64_E9) },
2820   { X86_64_TABLE (X86_64_EA) },
2821   { "jmp",              { Jb, BND }, 0 },
2822   { "inB",              { AL, indirDX }, 0 },
2823   { "inG",              { zAX, indirDX }, 0 },
2824   { "outB",             { indirDX, AL }, 0 },
2825   { "outG",             { indirDX, zAX }, 0 },
2826   /* f0 */
2827   { Bad_Opcode },       /* lock prefix */
2828   { "icebp",            { XX }, 0 },
2829   { Bad_Opcode },       /* repne */
2830   { Bad_Opcode },       /* repz */
2831   { "hlt",              { XX }, 0 },
2832   { "cmc",              { XX }, 0 },
2833   { REG_TABLE (REG_F6) },
2834   { REG_TABLE (REG_F7) },
2835   /* f8 */
2836   { "clc",              { XX }, 0 },
2837   { "stc",              { XX }, 0 },
2838   { "cli",              { XX }, 0 },
2839   { "sti",              { XX }, 0 },
2840   { "cld",              { XX }, 0 },
2841   { "std",              { XX }, 0 },
2842   { REG_TABLE (REG_FE) },
2843   { REG_TABLE (REG_FF) },
2844 };
2845
2846 static const struct dis386 dis386_twobyte[] = {
2847   /* 00 */
2848   { REG_TABLE (REG_0F00 ) },
2849   { REG_TABLE (REG_0F01 ) },
2850   { "larS",             { Gv, Ew }, 0 },
2851   { "lslS",             { Gv, Ew }, 0 },
2852   { Bad_Opcode },
2853   { "syscall",          { XX }, 0 },
2854   { "clts",             { XX }, 0 },
2855   { "sysret%LP",                { XX }, 0 },
2856   /* 08 */
2857   { "invd",             { XX }, 0 },
2858   { "wbinvd",           { XX }, 0 },
2859   { Bad_Opcode },
2860   { "ud2",              { XX }, 0 },
2861   { Bad_Opcode },
2862   { REG_TABLE (REG_0F0D) },
2863   { "femms",            { XX }, 0 },
2864   { "",                 { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix.  */
2865   /* 10 */
2866   { PREFIX_TABLE (PREFIX_0F10) },
2867   { PREFIX_TABLE (PREFIX_0F11) },
2868   { PREFIX_TABLE (PREFIX_0F12) },
2869   { MOD_TABLE (MOD_0F13) },
2870   { "unpcklpX",         { XM, EXx }, PREFIX_OPCODE },
2871   { "unpckhpX",         { XM, EXx }, PREFIX_OPCODE },
2872   { PREFIX_TABLE (PREFIX_0F16) },
2873   { MOD_TABLE (MOD_0F17) },
2874   /* 18 */
2875   { REG_TABLE (REG_0F18) },
2876   { "nopQ",             { Ev }, 0 },
2877   { PREFIX_TABLE (PREFIX_0F1A) },
2878   { PREFIX_TABLE (PREFIX_0F1B) },
2879   { "nopQ",             { Ev }, 0 },
2880   { "nopQ",             { Ev }, 0 },
2881   { PREFIX_TABLE (PREFIX_0F1E) },
2882   { "nopQ",             { Ev }, 0 },
2883   /* 20 */
2884   { "movZ",             { Rm, Cm }, 0 },
2885   { "movZ",             { Rm, Dm }, 0 },
2886   { "movZ",             { Cm, Rm }, 0 },
2887   { "movZ",             { Dm, Rm }, 0 },
2888   { MOD_TABLE (MOD_0F24) },
2889   { Bad_Opcode },
2890   { MOD_TABLE (MOD_0F26) },
2891   { Bad_Opcode },
2892   /* 28 */
2893   { "movapX",           { XM, EXx }, PREFIX_OPCODE },
2894   { "movapX",           { EXxS, XM }, PREFIX_OPCODE },
2895   { PREFIX_TABLE (PREFIX_0F2A) },
2896   { PREFIX_TABLE (PREFIX_0F2B) },
2897   { PREFIX_TABLE (PREFIX_0F2C) },
2898   { PREFIX_TABLE (PREFIX_0F2D) },
2899   { PREFIX_TABLE (PREFIX_0F2E) },
2900   { PREFIX_TABLE (PREFIX_0F2F) },
2901   /* 30 */
2902   { "wrmsr",            { XX }, 0 },
2903   { "rdtsc",            { XX }, 0 },
2904   { "rdmsr",            { XX }, 0 },
2905   { "rdpmc",            { XX }, 0 },
2906   { "sysenter",         { XX }, 0 },
2907   { "sysexit",          { XX }, 0 },
2908   { Bad_Opcode },
2909   { "getsec",           { XX }, 0 },
2910   /* 38 */
2911   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2912   { Bad_Opcode },
2913   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2914   { Bad_Opcode },
2915   { Bad_Opcode },
2916   { Bad_Opcode },
2917   { Bad_Opcode },
2918   { Bad_Opcode },
2919   /* 40 */
2920   { "cmovoS",           { Gv, Ev }, 0 },
2921   { "cmovnoS",          { Gv, Ev }, 0 },
2922   { "cmovbS",           { Gv, Ev }, 0 },
2923   { "cmovaeS",          { Gv, Ev }, 0 },
2924   { "cmoveS",           { Gv, Ev }, 0 },
2925   { "cmovneS",          { Gv, Ev }, 0 },
2926   { "cmovbeS",          { Gv, Ev }, 0 },
2927   { "cmovaS",           { Gv, Ev }, 0 },
2928   /* 48 */
2929   { "cmovsS",           { Gv, Ev }, 0 },
2930   { "cmovnsS",          { Gv, Ev }, 0 },
2931   { "cmovpS",           { Gv, Ev }, 0 },
2932   { "cmovnpS",          { Gv, Ev }, 0 },
2933   { "cmovlS",           { Gv, Ev }, 0 },
2934   { "cmovgeS",          { Gv, Ev }, 0 },
2935   { "cmovleS",          { Gv, Ev }, 0 },
2936   { "cmovgS",           { Gv, Ev }, 0 },
2937   /* 50 */
2938   { MOD_TABLE (MOD_0F51) },
2939   { PREFIX_TABLE (PREFIX_0F51) },
2940   { PREFIX_TABLE (PREFIX_0F52) },
2941   { PREFIX_TABLE (PREFIX_0F53) },
2942   { "andpX",            { XM, EXx }, PREFIX_OPCODE },
2943   { "andnpX",           { XM, EXx }, PREFIX_OPCODE },
2944   { "orpX",             { XM, EXx }, PREFIX_OPCODE },
2945   { "xorpX",            { XM, EXx }, PREFIX_OPCODE },
2946   /* 58 */
2947   { PREFIX_TABLE (PREFIX_0F58) },
2948   { PREFIX_TABLE (PREFIX_0F59) },
2949   { PREFIX_TABLE (PREFIX_0F5A) },
2950   { PREFIX_TABLE (PREFIX_0F5B) },
2951   { PREFIX_TABLE (PREFIX_0F5C) },
2952   { PREFIX_TABLE (PREFIX_0F5D) },
2953   { PREFIX_TABLE (PREFIX_0F5E) },
2954   { PREFIX_TABLE (PREFIX_0F5F) },
2955   /* 60 */
2956   { PREFIX_TABLE (PREFIX_0F60) },
2957   { PREFIX_TABLE (PREFIX_0F61) },
2958   { PREFIX_TABLE (PREFIX_0F62) },
2959   { "packsswb",         { MX, EM }, PREFIX_OPCODE },
2960   { "pcmpgtb",          { MX, EM }, PREFIX_OPCODE },
2961   { "pcmpgtw",          { MX, EM }, PREFIX_OPCODE },
2962   { "pcmpgtd",          { MX, EM }, PREFIX_OPCODE },
2963   { "packuswb",         { MX, EM }, PREFIX_OPCODE },
2964   /* 68 */
2965   { "punpckhbw",        { MX, EM }, PREFIX_OPCODE },
2966   { "punpckhwd",        { MX, EM }, PREFIX_OPCODE },
2967   { "punpckhdq",        { MX, EM }, PREFIX_OPCODE },
2968   { "packssdw",         { MX, EM }, PREFIX_OPCODE },
2969   { PREFIX_TABLE (PREFIX_0F6C) },
2970   { PREFIX_TABLE (PREFIX_0F6D) },
2971   { "movK",             { MX, Edq }, PREFIX_OPCODE },
2972   { PREFIX_TABLE (PREFIX_0F6F) },
2973   /* 70 */
2974   { PREFIX_TABLE (PREFIX_0F70) },
2975   { REG_TABLE (REG_0F71) },
2976   { REG_TABLE (REG_0F72) },
2977   { REG_TABLE (REG_0F73) },
2978   { "pcmpeqb",          { MX, EM }, PREFIX_OPCODE },
2979   { "pcmpeqw",          { MX, EM }, PREFIX_OPCODE },
2980   { "pcmpeqd",          { MX, EM }, PREFIX_OPCODE },
2981   { "emms",             { XX }, PREFIX_OPCODE },
2982   /* 78 */
2983   { PREFIX_TABLE (PREFIX_0F78) },
2984   { PREFIX_TABLE (PREFIX_0F79) },
2985   { Bad_Opcode },
2986   { Bad_Opcode },
2987   { PREFIX_TABLE (PREFIX_0F7C) },
2988   { PREFIX_TABLE (PREFIX_0F7D) },
2989   { PREFIX_TABLE (PREFIX_0F7E) },
2990   { PREFIX_TABLE (PREFIX_0F7F) },
2991   /* 80 */
2992   { "joH",              { Jv, BND, cond_jump_flag }, 0 },
2993   { "jnoH",             { Jv, BND, cond_jump_flag }, 0 },
2994   { "jbH",              { Jv, BND, cond_jump_flag }, 0 },
2995   { "jaeH",             { Jv, BND, cond_jump_flag }, 0 },
2996   { "jeH",              { Jv, BND, cond_jump_flag }, 0 },
2997   { "jneH",             { Jv, BND, cond_jump_flag }, 0 },
2998   { "jbeH",             { Jv, BND, cond_jump_flag }, 0 },
2999   { "jaH",              { Jv, BND, cond_jump_flag }, 0 },
3000   /* 88 */
3001   { "jsH",              { Jv, BND, cond_jump_flag }, 0 },
3002   { "jnsH",             { Jv, BND, cond_jump_flag }, 0 },
3003   { "jpH",              { Jv, BND, cond_jump_flag }, 0 },
3004   { "jnpH",             { Jv, BND, cond_jump_flag }, 0 },
3005   { "jlH",              { Jv, BND, cond_jump_flag }, 0 },
3006   { "jgeH",             { Jv, BND, cond_jump_flag }, 0 },
3007   { "jleH",             { Jv, BND, cond_jump_flag }, 0 },
3008   { "jgH",              { Jv, BND, cond_jump_flag }, 0 },
3009   /* 90 */
3010   { "seto",             { Eb }, 0 },
3011   { "setno",            { Eb }, 0 },
3012   { "setb",             { Eb }, 0 },
3013   { "setae",            { Eb }, 0 },
3014   { "sete",             { Eb }, 0 },
3015   { "setne",            { Eb }, 0 },
3016   { "setbe",            { Eb }, 0 },
3017   { "seta",             { Eb }, 0 },
3018   /* 98 */
3019   { "sets",             { Eb }, 0 },
3020   { "setns",            { Eb }, 0 },
3021   { "setp",             { Eb }, 0 },
3022   { "setnp",            { Eb }, 0 },
3023   { "setl",             { Eb }, 0 },
3024   { "setge",            { Eb }, 0 },
3025   { "setle",            { Eb }, 0 },
3026   { "setg",             { Eb }, 0 },
3027   /* a0 */
3028   { "pushT",            { fs }, 0 },
3029   { "popT",             { fs }, 0 },
3030   { "cpuid",            { XX }, 0 },
3031   { "btS",              { Ev, Gv }, 0 },
3032   { "shldS",            { Ev, Gv, Ib }, 0 },
3033   { "shldS",            { Ev, Gv, CL }, 0 },
3034   { REG_TABLE (REG_0FA6) },
3035   { REG_TABLE (REG_0FA7) },
3036   /* a8 */
3037   { "pushT",            { gs }, 0 },
3038   { "popT",             { gs }, 0 },
3039   { "rsm",              { XX }, 0 },
3040   { "btsS",             { Evh1, Gv }, 0 },
3041   { "shrdS",            { Ev, Gv, Ib }, 0 },
3042   { "shrdS",            { Ev, Gv, CL }, 0 },
3043   { REG_TABLE (REG_0FAE) },
3044   { "imulS",            { Gv, Ev }, 0 },
3045   /* b0 */
3046   { "cmpxchgB",         { Ebh1, Gb }, 0 },
3047   { "cmpxchgS",         { Evh1, Gv }, 0 },
3048   { MOD_TABLE (MOD_0FB2) },
3049   { "btrS",             { Evh1, Gv }, 0 },
3050   { MOD_TABLE (MOD_0FB4) },
3051   { MOD_TABLE (MOD_0FB5) },
3052   { "movz{bR|x}",       { Gv, Eb }, 0 },
3053   { "movz{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
3054   /* b8 */
3055   { PREFIX_TABLE (PREFIX_0FB8) },
3056   { "ud1",              { XX }, 0 },
3057   { REG_TABLE (REG_0FBA) },
3058   { "btcS",             { Evh1, Gv }, 0 },
3059   { PREFIX_TABLE (PREFIX_0FBC) },
3060   { PREFIX_TABLE (PREFIX_0FBD) },
3061   { "movs{bR|x}",       { Gv, Eb }, 0 },
3062   { "movs{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
3063   /* c0 */
3064   { "xaddB",            { Ebh1, Gb }, 0 },
3065   { "xaddS",            { Evh1, Gv }, 0 },
3066   { PREFIX_TABLE (PREFIX_0FC2) },
3067   { MOD_TABLE (MOD_0FC3) },
3068   { "pinsrw",           { MX, Edqw, Ib }, PREFIX_OPCODE },
3069   { "pextrw",           { Gdq, MS, Ib }, PREFIX_OPCODE },
3070   { "shufpX",           { XM, EXx, Ib }, PREFIX_OPCODE },
3071   { REG_TABLE (REG_0FC7) },
3072   /* c8 */
3073   { "bswap",            { RMeAX }, 0 },
3074   { "bswap",            { RMeCX }, 0 },
3075   { "bswap",            { RMeDX }, 0 },
3076   { "bswap",            { RMeBX }, 0 },
3077   { "bswap",            { RMeSP }, 0 },
3078   { "bswap",            { RMeBP }, 0 },
3079   { "bswap",            { RMeSI }, 0 },
3080   { "bswap",            { RMeDI }, 0 },
3081   /* d0 */
3082   { PREFIX_TABLE (PREFIX_0FD0) },
3083   { "psrlw",            { MX, EM }, PREFIX_OPCODE },
3084   { "psrld",            { MX, EM }, PREFIX_OPCODE },
3085   { "psrlq",            { MX, EM }, PREFIX_OPCODE },
3086   { "paddq",            { MX, EM }, PREFIX_OPCODE },
3087   { "pmullw",           { MX, EM }, PREFIX_OPCODE },
3088   { PREFIX_TABLE (PREFIX_0FD6) },
3089   { MOD_TABLE (MOD_0FD7) },
3090   /* d8 */
3091   { "psubusb",          { MX, EM }, PREFIX_OPCODE },
3092   { "psubusw",          { MX, EM }, PREFIX_OPCODE },
3093   { "pminub",           { MX, EM }, PREFIX_OPCODE },
3094   { "pand",             { MX, EM }, PREFIX_OPCODE },
3095   { "paddusb",          { MX, EM }, PREFIX_OPCODE },
3096   { "paddusw",          { MX, EM }, PREFIX_OPCODE },
3097   { "pmaxub",           { MX, EM }, PREFIX_OPCODE },
3098   { "pandn",            { MX, EM }, PREFIX_OPCODE },
3099   /* e0 */
3100   { "pavgb",            { MX, EM }, PREFIX_OPCODE },
3101   { "psraw",            { MX, EM }, PREFIX_OPCODE },
3102   { "psrad",            { MX, EM }, PREFIX_OPCODE },
3103   { "pavgw",            { MX, EM }, PREFIX_OPCODE },
3104   { "pmulhuw",          { MX, EM }, PREFIX_OPCODE },
3105   { "pmulhw",           { MX, EM }, PREFIX_OPCODE },
3106   { PREFIX_TABLE (PREFIX_0FE6) },
3107   { PREFIX_TABLE (PREFIX_0FE7) },
3108   /* e8 */
3109   { "psubsb",           { MX, EM }, PREFIX_OPCODE },
3110   { "psubsw",           { MX, EM }, PREFIX_OPCODE },
3111   { "pminsw",           { MX, EM }, PREFIX_OPCODE },
3112   { "por",              { MX, EM }, PREFIX_OPCODE },
3113   { "paddsb",           { MX, EM }, PREFIX_OPCODE },
3114   { "paddsw",           { MX, EM }, PREFIX_OPCODE },
3115   { "pmaxsw",           { MX, EM }, PREFIX_OPCODE },
3116   { "pxor",             { MX, EM }, PREFIX_OPCODE },
3117   /* f0 */
3118   { PREFIX_TABLE (PREFIX_0FF0) },
3119   { "psllw",            { MX, EM }, PREFIX_OPCODE },
3120   { "pslld",            { MX, EM }, PREFIX_OPCODE },
3121   { "psllq",            { MX, EM }, PREFIX_OPCODE },
3122   { "pmuludq",          { MX, EM }, PREFIX_OPCODE },
3123   { "pmaddwd",          { MX, EM }, PREFIX_OPCODE },
3124   { "psadbw",           { MX, EM }, PREFIX_OPCODE },
3125   { PREFIX_TABLE (PREFIX_0FF7) },
3126   /* f8 */
3127   { "psubb",            { MX, EM }, PREFIX_OPCODE },
3128   { "psubw",            { MX, EM }, PREFIX_OPCODE },
3129   { "psubd",            { MX, EM }, PREFIX_OPCODE },
3130   { "psubq",            { MX, EM }, PREFIX_OPCODE },
3131   { "paddb",            { MX, EM }, PREFIX_OPCODE },
3132   { "paddw",            { MX, EM }, PREFIX_OPCODE },
3133   { "paddd",            { MX, EM }, PREFIX_OPCODE },
3134   { Bad_Opcode },
3135 };
3136
3137 static const unsigned char onebyte_has_modrm[256] = {
3138   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3139   /*       -------------------------------        */
3140   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
3141   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
3142   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
3143   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
3144   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
3145   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
3146   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
3147   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
3148   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
3149   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
3150   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
3151   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
3152   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
3153   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
3154   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
3155   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
3156   /*       -------------------------------        */
3157   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3158 };
3159
3160 static const unsigned char twobyte_has_modrm[256] = {
3161   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3162   /*       -------------------------------        */
3163   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
3164   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
3165   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
3166   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
3167   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
3168   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
3169   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
3170   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
3171   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
3172   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
3173   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
3174   /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
3175   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
3176   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
3177   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
3178   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0  /* ff */
3179   /*       -------------------------------        */
3180   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3181 };
3182
3183 static char obuf[100];
3184 static char *obufp;
3185 static char *mnemonicendp;
3186 static char scratchbuf[100];
3187 static unsigned char *start_codep;
3188 static unsigned char *insn_codep;
3189 static unsigned char *codep;
3190 static unsigned char *end_codep;
3191 static int last_lock_prefix;
3192 static int last_repz_prefix;
3193 static int last_repnz_prefix;
3194 static int last_data_prefix;
3195 static int last_addr_prefix;
3196 static int last_rex_prefix;
3197 static int last_seg_prefix;
3198 static int fwait_prefix;
3199 /* The active segment register prefix.  */
3200 static int active_seg_prefix;
3201 #define MAX_CODE_LENGTH 15
3202 /* We can up to 14 prefixes since the maximum instruction length is
3203    15bytes.  */
3204 static int all_prefixes[MAX_CODE_LENGTH - 1];
3205 static disassemble_info *the_info;
3206 static struct
3207   {
3208     int mod;
3209     int reg;
3210     int rm;
3211   }
3212 modrm;
3213 static unsigned char need_modrm;
3214 static struct
3215   {
3216     int scale;
3217     int index;
3218     int base;
3219   }
3220 sib;
3221 static struct
3222   {
3223     int register_specifier;
3224     int length;
3225     int prefix;
3226     int w;
3227     int evex;
3228     int r;
3229     int v;
3230     int mask_register_specifier;
3231     int zeroing;
3232     int ll;
3233     int b;
3234   }
3235 vex;
3236 static unsigned char need_vex;
3237 static unsigned char need_vex_reg;
3238 static unsigned char vex_w_done;
3239
3240 struct op
3241   {
3242     const char *name;
3243     unsigned int len;
3244   };
3245
3246 /* If we are accessing mod/rm/reg without need_modrm set, then the
3247    values are stale.  Hitting this abort likely indicates that you
3248    need to update onebyte_has_modrm or twobyte_has_modrm.  */
3249 #define MODRM_CHECK  if (!need_modrm) abort ()
3250
3251 static const char **names64;
3252 static const char **names32;
3253 static const char **names16;
3254 static const char **names8;
3255 static const char **names8rex;
3256 static const char **names_seg;
3257 static const char *index64;
3258 static const char *index32;
3259 static const char **index16;
3260 static const char **names_bnd;
3261
3262 static const char *intel_names64[] = {
3263   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3264   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3265 };
3266 static const char *intel_names32[] = {
3267   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3268   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3269 };
3270 static const char *intel_names16[] = {
3271   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3272   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3273 };
3274 static const char *intel_names8[] = {
3275   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3276 };
3277 static const char *intel_names8rex[] = {
3278   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3279   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3280 };
3281 static const char *intel_names_seg[] = {
3282   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3283 };
3284 static const char *intel_index64 = "riz";
3285 static const char *intel_index32 = "eiz";
3286 static const char *intel_index16[] = {
3287   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3288 };
3289
3290 static const char *att_names64[] = {
3291   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3292   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3293 };
3294 static const char *att_names32[] = {
3295   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3296   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3297 };
3298 static const char *att_names16[] = {
3299   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3300   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3301 };
3302 static const char *att_names8[] = {
3303   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3304 };
3305 static const char *att_names8rex[] = {
3306   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3307   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3308 };
3309 static const char *att_names_seg[] = {
3310   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3311 };
3312 static const char *att_index64 = "%riz";
3313 static const char *att_index32 = "%eiz";
3314 static const char *att_index16[] = {
3315   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3316 };
3317
3318 static const char **names_mm;
3319 static const char *intel_names_mm[] = {
3320   "mm0", "mm1", "mm2", "mm3",
3321   "mm4", "mm5", "mm6", "mm7"
3322 };
3323 static const char *att_names_mm[] = {
3324   "%mm0", "%mm1", "%mm2", "%mm3",
3325   "%mm4", "%mm5", "%mm6", "%mm7"
3326 };
3327
3328 static const char *intel_names_bnd[] = {
3329   "bnd0", "bnd1", "bnd2", "bnd3"
3330 };
3331
3332 static const char *att_names_bnd[] = {
3333   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3334 };
3335
3336 static const char **names_xmm;
3337 static const char *intel_names_xmm[] = {
3338   "xmm0", "xmm1", "xmm2", "xmm3",
3339   "xmm4", "xmm5", "xmm6", "xmm7",
3340   "xmm8", "xmm9", "xmm10", "xmm11",
3341   "xmm12", "xmm13", "xmm14", "xmm15",
3342   "xmm16", "xmm17", "xmm18", "xmm19",
3343   "xmm20", "xmm21", "xmm22", "xmm23",
3344   "xmm24", "xmm25", "xmm26", "xmm27",
3345   "xmm28", "xmm29", "xmm30", "xmm31"
3346 };
3347 static const char *att_names_xmm[] = {
3348   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3349   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3350   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3351   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3352   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3353   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3354   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3355   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3356 };
3357
3358 static const char **names_ymm;
3359 static const char *intel_names_ymm[] = {
3360   "ymm0", "ymm1", "ymm2", "ymm3",
3361   "ymm4", "ymm5", "ymm6", "ymm7",
3362   "ymm8", "ymm9", "ymm10", "ymm11",
3363   "ymm12", "ymm13", "ymm14", "ymm15",
3364   "ymm16", "ymm17", "ymm18", "ymm19",
3365   "ymm20", "ymm21", "ymm22", "ymm23",
3366   "ymm24", "ymm25", "ymm26", "ymm27",
3367   "ymm28", "ymm29", "ymm30", "ymm31"
3368 };
3369 static const char *att_names_ymm[] = {
3370   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3371   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3372   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3373   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3374   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3375   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3376   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3377   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3378 };
3379
3380 static const char **names_zmm;
3381 static const char *intel_names_zmm[] = {
3382   "zmm0", "zmm1", "zmm2", "zmm3",
3383   "zmm4", "zmm5", "zmm6", "zmm7",
3384   "zmm8", "zmm9", "zmm10", "zmm11",
3385   "zmm12", "zmm13", "zmm14", "zmm15",
3386   "zmm16", "zmm17", "zmm18", "zmm19",
3387   "zmm20", "zmm21", "zmm22", "zmm23",
3388   "zmm24", "zmm25", "zmm26", "zmm27",
3389   "zmm28", "zmm29", "zmm30", "zmm31"
3390 };
3391 static const char *att_names_zmm[] = {
3392   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3393   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3394   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3395   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3396   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3397   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3398   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3399   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3400 };
3401
3402 static const char **names_mask;
3403 static const char *intel_names_mask[] = {
3404   "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3405 };
3406 static const char *att_names_mask[] = {
3407   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3408 };
3409
3410 static const char *names_rounding[] =
3411 {
3412   "{rn-sae}",
3413   "{rd-sae}",
3414   "{ru-sae}",
3415   "{rz-sae}"
3416 };
3417
3418 static const struct dis386 reg_table[][8] = {
3419   /* REG_80 */
3420   {
3421     { "addA",   { Ebh1, Ib }, 0 },
3422     { "orA",    { Ebh1, Ib }, 0 },
3423     { "adcA",   { Ebh1, Ib }, 0 },
3424     { "sbbA",   { Ebh1, Ib }, 0 },
3425     { "andA",   { Ebh1, Ib }, 0 },
3426     { "subA",   { Ebh1, Ib }, 0 },
3427     { "xorA",   { Ebh1, Ib }, 0 },
3428     { "cmpA",   { Eb, Ib }, 0 },
3429   },
3430   /* REG_81 */
3431   {
3432     { "addQ",   { Evh1, Iv }, 0 },
3433     { "orQ",    { Evh1, Iv }, 0 },
3434     { "adcQ",   { Evh1, Iv }, 0 },
3435     { "sbbQ",   { Evh1, Iv }, 0 },
3436     { "andQ",   { Evh1, Iv }, 0 },
3437     { "subQ",   { Evh1, Iv }, 0 },
3438     { "xorQ",   { Evh1, Iv }, 0 },
3439     { "cmpQ",   { Ev, Iv }, 0 },
3440   },
3441   /* REG_83 */
3442   {
3443     { "addQ",   { Evh1, sIb }, 0 },
3444     { "orQ",    { Evh1, sIb }, 0 },
3445     { "adcQ",   { Evh1, sIb }, 0 },
3446     { "sbbQ",   { Evh1, sIb }, 0 },
3447     { "andQ",   { Evh1, sIb }, 0 },
3448     { "subQ",   { Evh1, sIb }, 0 },
3449     { "xorQ",   { Evh1, sIb }, 0 },
3450     { "cmpQ",   { Ev, sIb }, 0 },
3451   },
3452   /* REG_8F */
3453   {
3454     { "popU",   { stackEv }, 0 },
3455     { XOP_8F_TABLE (XOP_09) },
3456     { Bad_Opcode },
3457     { Bad_Opcode },
3458     { Bad_Opcode },
3459     { XOP_8F_TABLE (XOP_09) },
3460   },
3461   /* REG_C0 */
3462   {
3463     { "rolA",   { Eb, Ib }, 0 },
3464     { "rorA",   { Eb, Ib }, 0 },
3465     { "rclA",   { Eb, Ib }, 0 },
3466     { "rcrA",   { Eb, Ib }, 0 },
3467     { "shlA",   { Eb, Ib }, 0 },
3468     { "shrA",   { Eb, Ib }, 0 },
3469     { "shlA",   { Eb, Ib }, 0 },
3470     { "sarA",   { Eb, Ib }, 0 },
3471   },
3472   /* REG_C1 */
3473   {
3474     { "rolQ",   { Ev, Ib }, 0 },
3475     { "rorQ",   { Ev, Ib }, 0 },
3476     { "rclQ",   { Ev, Ib }, 0 },
3477     { "rcrQ",   { Ev, Ib }, 0 },
3478     { "shlQ",   { Ev, Ib }, 0 },
3479     { "shrQ",   { Ev, Ib }, 0 },
3480     { "shlQ",   { Ev, Ib }, 0 },
3481     { "sarQ",   { Ev, Ib }, 0 },
3482   },
3483   /* REG_C6 */
3484   {
3485     { "movA",   { Ebh3, Ib }, 0 },
3486     { Bad_Opcode },
3487     { Bad_Opcode },
3488     { Bad_Opcode },
3489     { Bad_Opcode },
3490     { Bad_Opcode },
3491     { Bad_Opcode },
3492     { MOD_TABLE (MOD_C6_REG_7) },
3493   },
3494   /* REG_C7 */
3495   {
3496     { "movQ",   { Evh3, Iv }, 0 },
3497     { Bad_Opcode },
3498     { Bad_Opcode },
3499     { Bad_Opcode },
3500     { Bad_Opcode },
3501     { Bad_Opcode },
3502     { Bad_Opcode },
3503     { MOD_TABLE (MOD_C7_REG_7) },
3504   },
3505   /* REG_D0 */
3506   {
3507     { "rolA",   { Eb, I1 }, 0 },
3508     { "rorA",   { Eb, I1 }, 0 },
3509     { "rclA",   { Eb, I1 }, 0 },
3510     { "rcrA",   { Eb, I1 }, 0 },
3511     { "shlA",   { Eb, I1 }, 0 },
3512     { "shrA",   { Eb, I1 }, 0 },
3513     { "shlA",   { Eb, I1 }, 0 },
3514     { "sarA",   { Eb, I1 }, 0 },
3515   },
3516   /* REG_D1 */
3517   {
3518     { "rolQ",   { Ev, I1 }, 0 },
3519     { "rorQ",   { Ev, I1 }, 0 },
3520     { "rclQ",   { Ev, I1 }, 0 },
3521     { "rcrQ",   { Ev, I1 }, 0 },
3522     { "shlQ",   { Ev, I1 }, 0 },
3523     { "shrQ",   { Ev, I1 }, 0 },
3524     { "shlQ",   { Ev, I1 }, 0 },
3525     { "sarQ",   { Ev, I1 }, 0 },
3526   },
3527   /* REG_D2 */
3528   {
3529     { "rolA",   { Eb, CL }, 0 },
3530     { "rorA",   { Eb, CL }, 0 },
3531     { "rclA",   { Eb, CL }, 0 },
3532     { "rcrA",   { Eb, CL }, 0 },
3533     { "shlA",   { Eb, CL }, 0 },
3534     { "shrA",   { Eb, CL }, 0 },
3535     { "shlA",   { Eb, CL }, 0 },
3536     { "sarA",   { Eb, CL }, 0 },
3537   },
3538   /* REG_D3 */
3539   {
3540     { "rolQ",   { Ev, CL }, 0 },
3541     { "rorQ",   { Ev, CL }, 0 },
3542     { "rclQ",   { Ev, CL }, 0 },
3543     { "rcrQ",   { Ev, CL }, 0 },
3544     { "shlQ",   { Ev, CL }, 0 },
3545     { "shrQ",   { Ev, CL }, 0 },
3546     { "shlQ",   { Ev, CL }, 0 },
3547     { "sarQ",   { Ev, CL }, 0 },
3548   },
3549   /* REG_F6 */
3550   {
3551     { "testA",  { Eb, Ib }, 0 },
3552     { "testA",  { Eb, Ib }, 0 },
3553     { "notA",   { Ebh1 }, 0 },
3554     { "negA",   { Ebh1 }, 0 },
3555     { "mulA",   { Eb }, 0 },    /* Don't print the implicit %al register,  */
3556     { "imulA",  { Eb }, 0 },    /* to distinguish these opcodes from other */
3557     { "divA",   { Eb }, 0 },    /* mul/imul opcodes.  Do the same for div  */
3558     { "idivA",  { Eb }, 0 },    /* and idiv for consistency.               */
3559   },
3560   /* REG_F7 */
3561   {
3562     { "testQ",  { Ev, Iv }, 0 },
3563     { "testQ",  { Ev, Iv }, 0 },
3564     { "notQ",   { Evh1 }, 0 },
3565     { "negQ",   { Evh1 }, 0 },
3566     { "mulQ",   { Ev }, 0 },    /* Don't print the implicit register.  */
3567     { "imulQ",  { Ev }, 0 },
3568     { "divQ",   { Ev }, 0 },
3569     { "idivQ",  { Ev }, 0 },
3570   },
3571   /* REG_FE */
3572   {
3573     { "incA",   { Ebh1 }, 0 },
3574     { "decA",   { Ebh1 }, 0 },
3575   },
3576   /* REG_FF */
3577   {
3578     { "incQ",   { Evh1 }, 0 },
3579     { "decQ",   { Evh1 }, 0 },
3580     { "call{&|}", { NOTRACK, indirEv, BND }, 0 },
3581     { MOD_TABLE (MOD_FF_REG_3) },
3582     { "jmp{&|}", { NOTRACK, indirEv, BND }, 0 },
3583     { MOD_TABLE (MOD_FF_REG_5) },
3584     { "pushU",  { stackEv }, 0 },
3585     { Bad_Opcode },
3586   },
3587   /* REG_0F00 */
3588   {
3589     { "sldtD",  { Sv }, 0 },
3590     { "strD",   { Sv }, 0 },
3591     { "lldt",   { Ew }, 0 },
3592     { "ltr",    { Ew }, 0 },
3593     { "verr",   { Ew }, 0 },
3594     { "verw",   { Ew }, 0 },
3595     { Bad_Opcode },
3596     { Bad_Opcode },
3597   },
3598   /* REG_0F01 */
3599   {
3600     { MOD_TABLE (MOD_0F01_REG_0) },
3601     { MOD_TABLE (MOD_0F01_REG_1) },
3602     { MOD_TABLE (MOD_0F01_REG_2) },
3603     { MOD_TABLE (MOD_0F01_REG_3) },
3604     { "smswD",  { Sv }, 0 },
3605     { MOD_TABLE (MOD_0F01_REG_5) },
3606     { "lmsw",   { Ew }, 0 },
3607     { MOD_TABLE (MOD_0F01_REG_7) },
3608   },
3609   /* REG_0F0D */
3610   {
3611     { "prefetch",       { Mb }, 0 },
3612     { "prefetchw",      { Mb }, 0 },
3613     { "prefetchwt1",    { Mb }, 0 },
3614     { "prefetch",       { Mb }, 0 },
3615     { "prefetch",       { Mb }, 0 },
3616     { "prefetch",       { Mb }, 0 },
3617     { "prefetch",       { Mb }, 0 },
3618     { "prefetch",       { Mb }, 0 },
3619   },
3620   /* REG_0F18 */
3621   {
3622     { MOD_TABLE (MOD_0F18_REG_0) },
3623     { MOD_TABLE (MOD_0F18_REG_1) },
3624     { MOD_TABLE (MOD_0F18_REG_2) },
3625     { MOD_TABLE (MOD_0F18_REG_3) },
3626     { MOD_TABLE (MOD_0F18_REG_4) },
3627     { MOD_TABLE (MOD_0F18_REG_5) },
3628     { MOD_TABLE (MOD_0F18_REG_6) },
3629     { MOD_TABLE (MOD_0F18_REG_7) },
3630   },
3631   /* REG_0F1E_MOD_3 */
3632   {
3633     { "nopQ",           { Ev }, 0 },
3634     { "rdsspK",         { Rdq }, PREFIX_OPCODE },
3635     { "nopQ",           { Ev }, 0 },
3636     { "nopQ",           { Ev }, 0 },
3637     { "nopQ",           { Ev }, 0 },
3638     { "nopQ",           { Ev }, 0 },
3639     { "nopQ",           { Ev }, 0 },
3640     { RM_TABLE (RM_0F1E_MOD_3_REG_7) },
3641   },
3642   /* REG_0F71 */
3643   {
3644     { Bad_Opcode },
3645     { Bad_Opcode },
3646     { MOD_TABLE (MOD_0F71_REG_2) },
3647     { Bad_Opcode },
3648     { MOD_TABLE (MOD_0F71_REG_4) },
3649     { Bad_Opcode },
3650     { MOD_TABLE (MOD_0F71_REG_6) },
3651   },
3652   /* REG_0F72 */
3653   {
3654     { Bad_Opcode },
3655     { Bad_Opcode },
3656     { MOD_TABLE (MOD_0F72_REG_2) },
3657     { Bad_Opcode },
3658     { MOD_TABLE (MOD_0F72_REG_4) },
3659     { Bad_Opcode },
3660     { MOD_TABLE (MOD_0F72_REG_6) },
3661   },
3662   /* REG_0F73 */
3663   {
3664     { Bad_Opcode },
3665     { Bad_Opcode },
3666     { MOD_TABLE (MOD_0F73_REG_2) },
3667     { MOD_TABLE (MOD_0F73_REG_3) },
3668     { Bad_Opcode },
3669     { Bad_Opcode },
3670     { MOD_TABLE (MOD_0F73_REG_6) },
3671     { MOD_TABLE (MOD_0F73_REG_7) },
3672   },
3673   /* REG_0FA6 */
3674   {
3675     { "montmul",        { { OP_0f07, 0 } }, 0 },
3676     { "xsha1",          { { OP_0f07, 0 } }, 0 },
3677     { "xsha256",        { { OP_0f07, 0 } }, 0 },
3678   },
3679   /* REG_0FA7 */
3680   {
3681     { "xstore-rng",     { { OP_0f07, 0 } }, 0 },
3682     { "xcrypt-ecb",     { { OP_0f07, 0 } }, 0 },
3683     { "xcrypt-cbc",     { { OP_0f07, 0 } }, 0 },
3684     { "xcrypt-ctr",     { { OP_0f07, 0 } }, 0 },
3685     { "xcrypt-cfb",     { { OP_0f07, 0 } }, 0 },
3686     { "xcrypt-ofb",     { { OP_0f07, 0 } }, 0 },
3687   },
3688   /* REG_0FAE */
3689   {
3690     { MOD_TABLE (MOD_0FAE_REG_0) },
3691     { MOD_TABLE (MOD_0FAE_REG_1) },
3692     { MOD_TABLE (MOD_0FAE_REG_2) },
3693     { MOD_TABLE (MOD_0FAE_REG_3) },
3694     { MOD_TABLE (MOD_0FAE_REG_4) },
3695     { MOD_TABLE (MOD_0FAE_REG_5) },
3696     { MOD_TABLE (MOD_0FAE_REG_6) },
3697     { MOD_TABLE (MOD_0FAE_REG_7) },
3698   },
3699   /* REG_0FBA */
3700   {
3701     { Bad_Opcode },
3702     { Bad_Opcode },
3703     { Bad_Opcode },
3704     { Bad_Opcode },
3705     { "btQ",    { Ev, Ib }, 0 },
3706     { "btsQ",   { Evh1, Ib }, 0 },
3707     { "btrQ",   { Evh1, Ib }, 0 },
3708     { "btcQ",   { Evh1, Ib }, 0 },
3709   },
3710   /* REG_0FC7 */
3711   {
3712     { Bad_Opcode },
3713     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
3714     { Bad_Opcode },
3715     { MOD_TABLE (MOD_0FC7_REG_3) },
3716     { MOD_TABLE (MOD_0FC7_REG_4) },
3717     { MOD_TABLE (MOD_0FC7_REG_5) },
3718     { MOD_TABLE (MOD_0FC7_REG_6) },
3719     { MOD_TABLE (MOD_0FC7_REG_7) },
3720   },
3721   /* REG_VEX_0F71 */
3722   {
3723     { Bad_Opcode },
3724     { Bad_Opcode },
3725     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3726     { Bad_Opcode },
3727     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3728     { Bad_Opcode },
3729     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3730   },
3731   /* REG_VEX_0F72 */
3732   {
3733     { Bad_Opcode },
3734     { Bad_Opcode },
3735     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3736     { Bad_Opcode },
3737     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3738     { Bad_Opcode },
3739     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3740   },
3741   /* REG_VEX_0F73 */
3742   {
3743     { Bad_Opcode },
3744     { Bad_Opcode },
3745     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3746     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3747     { Bad_Opcode },
3748     { Bad_Opcode },
3749     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3750     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3751   },
3752   /* REG_VEX_0FAE */
3753   {
3754     { Bad_Opcode },
3755     { Bad_Opcode },
3756     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3757     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3758   },
3759   /* REG_VEX_0F38F3 */
3760   {
3761     { Bad_Opcode },
3762     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3763     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3764     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3765   },
3766   /* REG_XOP_LWPCB */
3767   {
3768     { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3769     { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3770   },
3771   /* REG_XOP_LWP */
3772   {
3773     { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3774     { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3775   },
3776   /* REG_XOP_TBM_01 */
3777   {
3778     { Bad_Opcode },
3779     { "blcfill",        { { OP_LWP_E, 0 }, Ev }, 0 },
3780     { "blsfill",        { { OP_LWP_E, 0 }, Ev }, 0 },
3781     { "blcs",   { { OP_LWP_E, 0 }, Ev }, 0 },
3782     { "tzmsk",  { { OP_LWP_E, 0 }, Ev }, 0 },
3783     { "blcic",  { { OP_LWP_E, 0 }, Ev }, 0 },
3784     { "blsic",  { { OP_LWP_E, 0 }, Ev }, 0 },
3785     { "t1mskc", { { OP_LWP_E, 0 }, Ev }, 0 },
3786   },
3787   /* REG_XOP_TBM_02 */
3788   {
3789     { Bad_Opcode },
3790     { "blcmsk", { { OP_LWP_E, 0 }, Ev }, 0 },
3791     { Bad_Opcode },
3792     { Bad_Opcode },
3793     { Bad_Opcode },
3794     { Bad_Opcode },
3795     { "blci",   { { OP_LWP_E, 0 }, Ev }, 0 },
3796   },
3797 #define NEED_REG_TABLE
3798 #include "i386-dis-evex.h"
3799 #undef NEED_REG_TABLE
3800 };
3801
3802 static const struct dis386 prefix_table[][4] = {
3803   /* PREFIX_90 */
3804   {
3805     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3806     { "pause", { XX }, 0 },
3807     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3808     { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3809   },
3810
3811   /* PREFIX_MOD_0_0F01_REG_5 */
3812   {
3813     { Bad_Opcode },
3814     { "rstorssp",       { Mq }, PREFIX_OPCODE },
3815   },
3816
3817   /* PREFIX_MOD_3_0F01_REG_5_RM_0 */
3818   {
3819     { Bad_Opcode },
3820     { "setssbsy",       { Skip_MODRM }, PREFIX_OPCODE },
3821   },
3822
3823   /* PREFIX_MOD_3_0F01_REG_5_RM_2 */
3824   {
3825     { Bad_Opcode },
3826     { "saveprevssp",    { Skip_MODRM }, PREFIX_OPCODE },
3827   },
3828
3829   /* PREFIX_0F10 */
3830   {
3831     { "movups", { XM, EXx }, PREFIX_OPCODE },
3832     { "movss",  { XM, EXd }, PREFIX_OPCODE },
3833     { "movupd", { XM, EXx }, PREFIX_OPCODE },
3834     { "movsd",  { XM, EXq }, PREFIX_OPCODE },
3835   },
3836
3837   /* PREFIX_0F11 */
3838   {
3839     { "movups", { EXxS, XM }, PREFIX_OPCODE },
3840     { "movss",  { EXdS, XM }, PREFIX_OPCODE },
3841     { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3842     { "movsd",  { EXqS, XM }, PREFIX_OPCODE },
3843   },
3844
3845   /* PREFIX_0F12 */
3846   {
3847     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3848     { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3849     { "movlpd", { XM, EXq }, PREFIX_OPCODE },
3850     { "movddup", { XM, EXq }, PREFIX_OPCODE },
3851   },
3852
3853   /* PREFIX_0F16 */
3854   {
3855     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3856     { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3857     { "movhpd", { XM, EXq }, PREFIX_OPCODE },
3858   },
3859
3860   /* PREFIX_0F1A */
3861   {
3862     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3863     { "bndcl",  { Gbnd, Ev_bnd }, 0 },
3864     { "bndmov", { Gbnd, Ebnd }, 0 },
3865     { "bndcu",  { Gbnd, Ev_bnd }, 0 },
3866   },
3867
3868   /* PREFIX_0F1B */
3869   {
3870     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3871     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3872     { "bndmov", { Ebnd, Gbnd }, 0 },
3873     { "bndcn",  { Gbnd, Ev_bnd }, 0 },
3874   },
3875
3876   /* PREFIX_0F1E */
3877   {
3878     { "nopQ",   { Ev }, PREFIX_OPCODE },
3879     { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3880     { "nopQ",   { Ev }, PREFIX_OPCODE },
3881     { "nopQ",   { Ev }, PREFIX_OPCODE },
3882   },
3883
3884   /* PREFIX_0F2A */
3885   {
3886     { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3887     { "cvtsi2ss%LQ", { XM, Ev }, PREFIX_OPCODE },
3888     { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3889     { "cvtsi2sd%LQ", { XM, Ev }, 0 },
3890   },
3891
3892   /* PREFIX_0F2B */
3893   {
3894     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3895     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3896     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3897     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3898   },
3899
3900   /* PREFIX_0F2C */
3901   {
3902     { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3903     { "cvttss2siY", { Gv, EXd }, PREFIX_OPCODE },
3904     { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3905     { "cvttsd2siY", { Gv, EXq }, PREFIX_OPCODE },
3906   },
3907
3908   /* PREFIX_0F2D */
3909   {
3910     { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3911     { "cvtss2siY", { Gv, EXd }, PREFIX_OPCODE },
3912     { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3913     { "cvtsd2siY", { Gv, EXq }, PREFIX_OPCODE },
3914   },
3915
3916   /* PREFIX_0F2E */
3917   {
3918     { "ucomiss",{ XM, EXd }, 0 },
3919     { Bad_Opcode },
3920     { "ucomisd",{ XM, EXq }, 0 },
3921   },
3922
3923   /* PREFIX_0F2F */
3924   {
3925     { "comiss", { XM, EXd }, 0 },
3926     { Bad_Opcode },
3927     { "comisd", { XM, EXq }, 0 },
3928   },
3929
3930   /* PREFIX_0F51 */
3931   {
3932     { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3933     { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3934     { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3935     { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3936   },
3937
3938   /* PREFIX_0F52 */
3939   {
3940     { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3941     { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3942   },
3943
3944   /* PREFIX_0F53 */
3945   {
3946     { "rcpps",  { XM, EXx }, PREFIX_OPCODE },
3947     { "rcpss",  { XM, EXd }, PREFIX_OPCODE },
3948   },
3949
3950   /* PREFIX_0F58 */
3951   {
3952     { "addps", { XM, EXx }, PREFIX_OPCODE },
3953     { "addss", { XM, EXd }, PREFIX_OPCODE },
3954     { "addpd", { XM, EXx }, PREFIX_OPCODE },
3955     { "addsd", { XM, EXq }, PREFIX_OPCODE },
3956   },
3957
3958   /* PREFIX_0F59 */
3959   {
3960     { "mulps",  { XM, EXx }, PREFIX_OPCODE },
3961     { "mulss",  { XM, EXd }, PREFIX_OPCODE },
3962     { "mulpd",  { XM, EXx }, PREFIX_OPCODE },
3963     { "mulsd",  { XM, EXq }, PREFIX_OPCODE },
3964   },
3965
3966   /* PREFIX_0F5A */
3967   {
3968     { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3969     { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3970     { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3971     { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3972   },
3973
3974   /* PREFIX_0F5B */
3975   {
3976     { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3977     { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3978     { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3979   },
3980
3981   /* PREFIX_0F5C */
3982   {
3983     { "subps",  { XM, EXx }, PREFIX_OPCODE },
3984     { "subss",  { XM, EXd }, PREFIX_OPCODE },
3985     { "subpd",  { XM, EXx }, PREFIX_OPCODE },
3986     { "subsd",  { XM, EXq }, PREFIX_OPCODE },
3987   },
3988
3989   /* PREFIX_0F5D */
3990   {
3991     { "minps",  { XM, EXx }, PREFIX_OPCODE },
3992     { "minss",  { XM, EXd }, PREFIX_OPCODE },
3993     { "minpd",  { XM, EXx }, PREFIX_OPCODE },
3994     { "minsd",  { XM, EXq }, PREFIX_OPCODE },
3995   },
3996
3997   /* PREFIX_0F5E */
3998   {
3999     { "divps",  { XM, EXx }, PREFIX_OPCODE },
4000     { "divss",  { XM, EXd }, PREFIX_OPCODE },
4001     { "divpd",  { XM, EXx }, PREFIX_OPCODE },
4002     { "divsd",  { XM, EXq }, PREFIX_OPCODE },
4003   },
4004
4005   /* PREFIX_0F5F */
4006   {
4007     { "maxps",  { XM, EXx }, PREFIX_OPCODE },
4008     { "maxss",  { XM, EXd }, PREFIX_OPCODE },
4009     { "maxpd",  { XM, EXx }, PREFIX_OPCODE },
4010     { "maxsd",  { XM, EXq }, PREFIX_OPCODE },
4011   },
4012
4013   /* PREFIX_0F60 */
4014   {
4015     { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
4016     { Bad_Opcode },
4017     { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
4018   },
4019
4020   /* PREFIX_0F61 */
4021   {
4022     { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
4023     { Bad_Opcode },
4024     { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
4025   },
4026
4027   /* PREFIX_0F62 */
4028   {
4029     { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
4030     { Bad_Opcode },
4031     { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
4032   },
4033
4034   /* PREFIX_0F6C */
4035   {
4036     { Bad_Opcode },
4037     { Bad_Opcode },
4038     { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE },
4039   },
4040
4041   /* PREFIX_0F6D */
4042   {
4043     { Bad_Opcode },
4044     { Bad_Opcode },
4045     { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE },
4046   },
4047
4048   /* PREFIX_0F6F */
4049   {
4050     { "movq",   { MX, EM }, PREFIX_OPCODE },
4051     { "movdqu", { XM, EXx }, PREFIX_OPCODE },
4052     { "movdqa", { XM, EXx }, PREFIX_OPCODE },
4053   },
4054
4055   /* PREFIX_0F70 */
4056   {
4057     { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
4058     { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
4059     { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
4060     { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
4061   },
4062
4063   /* PREFIX_0F73_REG_3 */
4064   {
4065     { Bad_Opcode },
4066     { Bad_Opcode },
4067     { "psrldq", { XS, Ib }, 0 },
4068   },
4069
4070   /* PREFIX_0F73_REG_7 */
4071   {
4072     { Bad_Opcode },
4073     { Bad_Opcode },
4074     { "pslldq", { XS, Ib }, 0 },
4075   },
4076
4077   /* PREFIX_0F78 */
4078   {
4079     {"vmread",  { Em, Gm }, 0 },
4080     { Bad_Opcode },
4081     {"extrq",   { XS, Ib, Ib }, 0 },
4082     {"insertq", { XM, XS, Ib, Ib }, 0 },
4083   },
4084
4085   /* PREFIX_0F79 */
4086   {
4087     {"vmwrite", { Gm, Em }, 0 },
4088     { Bad_Opcode },
4089     {"extrq",   { XM, XS }, 0 },
4090     {"insertq", { XM, XS }, 0 },
4091   },
4092
4093   /* PREFIX_0F7C */
4094   {
4095     { Bad_Opcode },
4096     { Bad_Opcode },
4097     { "haddpd", { XM, EXx }, PREFIX_OPCODE },
4098     { "haddps", { XM, EXx }, PREFIX_OPCODE },
4099   },
4100
4101   /* PREFIX_0F7D */
4102   {
4103     { Bad_Opcode },
4104     { Bad_Opcode },
4105     { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
4106     { "hsubps", { XM, EXx }, PREFIX_OPCODE },
4107   },
4108
4109   /* PREFIX_0F7E */
4110   {
4111     { "movK",   { Edq, MX }, PREFIX_OPCODE },
4112     { "movq",   { XM, EXq }, PREFIX_OPCODE },
4113     { "movK",   { Edq, XM }, PREFIX_OPCODE },
4114   },
4115
4116   /* PREFIX_0F7F */
4117   {
4118     { "movq",   { EMS, MX }, PREFIX_OPCODE },
4119     { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
4120     { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
4121   },
4122
4123   /* PREFIX_0FAE_REG_0 */
4124   {
4125     { Bad_Opcode },
4126     { "rdfsbase", { Ev }, 0 },
4127   },
4128
4129   /* PREFIX_0FAE_REG_1 */
4130   {
4131     { Bad_Opcode },
4132     { "rdgsbase", { Ev }, 0 },
4133   },
4134
4135   /* PREFIX_0FAE_REG_2 */
4136   {
4137     { Bad_Opcode },
4138     { "wrfsbase", { Ev }, 0 },
4139   },
4140
4141   /* PREFIX_0FAE_REG_3 */
4142   {
4143     { Bad_Opcode },
4144     { "wrgsbase", { Ev }, 0 },
4145   },
4146
4147   /* PREFIX_MOD_0_0FAE_REG_4 */
4148   {
4149     { "xsave",  { FXSAVE }, 0 },
4150     { "ptwrite%LQ", { Edq }, 0 },
4151   },
4152
4153   /* PREFIX_MOD_3_0FAE_REG_4 */
4154   {
4155     { Bad_Opcode },
4156     { "ptwrite%LQ", { Edq }, 0 },
4157   },
4158
4159   /* PREFIX_MOD_0_0FAE_REG_5 */
4160   {
4161     { "xrstor",         { FXSAVE }, PREFIX_OPCODE },
4162   },
4163
4164   /* PREFIX_MOD_3_0FAE_REG_5 */
4165   {
4166     { "lfence",         { Skip_MODRM }, 0 },
4167     { "incsspK",        { Rdq }, PREFIX_OPCODE },
4168   },
4169
4170   /* PREFIX_0FAE_REG_6 */
4171   {
4172     { "xsaveopt",       { FXSAVE }, PREFIX_OPCODE },
4173     { "clrssbsy",       { Mq }, PREFIX_OPCODE },
4174     { "clwb",   { Mb }, PREFIX_OPCODE },
4175   },
4176
4177   /* PREFIX_0FAE_REG_7 */
4178   {
4179     { "clflush",        { Mb }, 0 },
4180     { Bad_Opcode },
4181     { "clflushopt",     { Mb }, 0 },
4182   },
4183
4184   /* PREFIX_0FB8 */
4185   {
4186     { Bad_Opcode },
4187     { "popcntS", { Gv, Ev }, 0 },
4188   },
4189
4190   /* PREFIX_0FBC */
4191   {
4192     { "bsfS",   { Gv, Ev }, 0 },
4193     { "tzcntS", { Gv, Ev }, 0 },
4194     { "bsfS",   { Gv, Ev }, 0 },
4195   },
4196
4197   /* PREFIX_0FBD */
4198   {
4199     { "bsrS",   { Gv, Ev }, 0 },
4200     { "lzcntS", { Gv, Ev }, 0 },
4201     { "bsrS",   { Gv, Ev }, 0 },
4202   },
4203
4204   /* PREFIX_0FC2 */
4205   {
4206     { "cmpps",  { XM, EXx, CMP }, PREFIX_OPCODE },
4207     { "cmpss",  { XM, EXd, CMP }, PREFIX_OPCODE },
4208     { "cmppd",  { XM, EXx, CMP }, PREFIX_OPCODE },
4209     { "cmpsd",  { XM, EXq, CMP }, PREFIX_OPCODE },
4210   },
4211
4212   /* PREFIX_MOD_0_0FC3 */
4213   {
4214     { "movntiS", { Ev, Gv }, PREFIX_OPCODE },
4215   },
4216
4217   /* PREFIX_MOD_0_0FC7_REG_6 */
4218   {
4219     { "vmptrld",{ Mq }, 0 },
4220     { "vmxon",  { Mq }, 0 },
4221     { "vmclear",{ Mq }, 0 },
4222   },
4223
4224   /* PREFIX_MOD_3_0FC7_REG_6 */
4225   {
4226     { "rdrand", { Ev }, 0 },
4227     { Bad_Opcode },
4228     { "rdrand", { Ev }, 0 }
4229   },
4230
4231   /* PREFIX_MOD_3_0FC7_REG_7 */
4232   {
4233     { "rdseed", { Ev }, 0 },
4234     { "rdpid",  { Em }, 0 },
4235     { "rdseed", { Ev }, 0 },
4236   },
4237
4238   /* PREFIX_0FD0 */
4239   {
4240     { Bad_Opcode },
4241     { Bad_Opcode },
4242     { "addsubpd", { XM, EXx }, 0 },
4243     { "addsubps", { XM, EXx }, 0 },
4244   },
4245
4246   /* PREFIX_0FD6 */
4247   {
4248     { Bad_Opcode },
4249     { "movq2dq",{ XM, MS }, 0 },
4250     { "movq",   { EXqS, XM }, 0 },
4251     { "movdq2q",{ MX, XS }, 0 },
4252   },
4253
4254   /* PREFIX_0FE6 */
4255   {
4256     { Bad_Opcode },
4257     { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
4258     { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
4259     { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
4260   },
4261
4262   /* PREFIX_0FE7 */
4263   {
4264     { "movntq", { Mq, MX }, PREFIX_OPCODE },
4265     { Bad_Opcode },
4266     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
4267   },
4268
4269   /* PREFIX_0FF0 */
4270   {
4271     { Bad_Opcode },
4272     { Bad_Opcode },
4273     { Bad_Opcode },
4274     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4275   },
4276
4277   /* PREFIX_0FF7 */
4278   {
4279     { "maskmovq", { MX, MS }, PREFIX_OPCODE },
4280     { Bad_Opcode },
4281     { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
4282   },
4283
4284   /* PREFIX_0F3810 */
4285   {
4286     { Bad_Opcode },
4287     { Bad_Opcode },
4288     { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4289   },
4290
4291   /* PREFIX_0F3814 */
4292   {
4293     { Bad_Opcode },
4294     { Bad_Opcode },
4295     { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4296   },
4297
4298   /* PREFIX_0F3815 */
4299   {
4300     { Bad_Opcode },
4301     { Bad_Opcode },
4302     { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4303   },
4304
4305   /* PREFIX_0F3817 */
4306   {
4307     { Bad_Opcode },
4308     { Bad_Opcode },
4309     { "ptest",  { XM, EXx }, PREFIX_OPCODE },
4310   },
4311
4312   /* PREFIX_0F3820 */
4313   {
4314     { Bad_Opcode },
4315     { Bad_Opcode },
4316     { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE },
4317   },
4318
4319   /* PREFIX_0F3821 */
4320   {
4321     { Bad_Opcode },
4322     { Bad_Opcode },
4323     { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE },
4324   },
4325
4326   /* PREFIX_0F3822 */
4327   {
4328     { Bad_Opcode },
4329     { Bad_Opcode },
4330     { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE },
4331   },
4332
4333   /* PREFIX_0F3823 */
4334   {
4335     { Bad_Opcode },
4336     { Bad_Opcode },
4337     { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE },
4338   },
4339
4340   /* PREFIX_0F3824 */
4341   {
4342     { Bad_Opcode },
4343     { Bad_Opcode },
4344     { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE },
4345   },
4346
4347   /* PREFIX_0F3825 */
4348   {
4349     { Bad_Opcode },
4350     { Bad_Opcode },
4351     { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE },
4352   },
4353
4354   /* PREFIX_0F3828 */
4355   {
4356     { Bad_Opcode },
4357     { Bad_Opcode },
4358     { "pmuldq", { XM, EXx }, PREFIX_OPCODE },
4359   },
4360
4361   /* PREFIX_0F3829 */
4362   {
4363     { Bad_Opcode },
4364     { Bad_Opcode },
4365     { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE },
4366   },
4367
4368   /* PREFIX_0F382A */
4369   {
4370     { Bad_Opcode },
4371     { Bad_Opcode },
4372     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4373   },
4374
4375   /* PREFIX_0F382B */
4376   {
4377     { Bad_Opcode },
4378     { Bad_Opcode },
4379     { "packusdw", { XM, EXx }, PREFIX_OPCODE },
4380   },
4381
4382   /* PREFIX_0F3830 */
4383   {
4384     { Bad_Opcode },
4385     { Bad_Opcode },
4386     { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE },
4387   },
4388
4389   /* PREFIX_0F3831 */
4390   {
4391     { Bad_Opcode },
4392     { Bad_Opcode },
4393     { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE },
4394   },
4395
4396   /* PREFIX_0F3832 */
4397   {
4398     { Bad_Opcode },
4399     { Bad_Opcode },
4400     { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE },
4401   },
4402
4403   /* PREFIX_0F3833 */
4404   {
4405     { Bad_Opcode },
4406     { Bad_Opcode },
4407     { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE },
4408   },
4409
4410   /* PREFIX_0F3834 */
4411   {
4412     { Bad_Opcode },
4413     { Bad_Opcode },
4414     { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE },
4415   },
4416
4417   /* PREFIX_0F3835 */
4418   {
4419     { Bad_Opcode },
4420     { Bad_Opcode },
4421     { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE },
4422   },
4423
4424   /* PREFIX_0F3837 */
4425   {
4426     { Bad_Opcode },
4427     { Bad_Opcode },
4428     { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE },
4429   },
4430
4431   /* PREFIX_0F3838 */
4432   {
4433     { Bad_Opcode },
4434     { Bad_Opcode },
4435     { "pminsb", { XM, EXx }, PREFIX_OPCODE },
4436   },
4437
4438   /* PREFIX_0F3839 */
4439   {
4440     { Bad_Opcode },
4441     { Bad_Opcode },
4442     { "pminsd", { XM, EXx }, PREFIX_OPCODE },
4443   },
4444
4445   /* PREFIX_0F383A */
4446   {
4447     { Bad_Opcode },
4448     { Bad_Opcode },
4449     { "pminuw", { XM, EXx }, PREFIX_OPCODE },
4450   },
4451
4452   /* PREFIX_0F383B */
4453   {
4454     { Bad_Opcode },
4455     { Bad_Opcode },
4456     { "pminud", { XM, EXx }, PREFIX_OPCODE },
4457   },
4458
4459   /* PREFIX_0F383C */
4460   {
4461     { Bad_Opcode },
4462     { Bad_Opcode },
4463     { "pmaxsb", { XM, EXx }, PREFIX_OPCODE },
4464   },
4465
4466   /* PREFIX_0F383D */
4467   {
4468     { Bad_Opcode },
4469     { Bad_Opcode },
4470     { "pmaxsd", { XM, EXx }, PREFIX_OPCODE },
4471   },
4472
4473   /* PREFIX_0F383E */
4474   {
4475     { Bad_Opcode },
4476     { Bad_Opcode },
4477     { "pmaxuw", { XM, EXx }, PREFIX_OPCODE },
4478   },
4479
4480   /* PREFIX_0F383F */
4481   {
4482     { Bad_Opcode },
4483     { Bad_Opcode },
4484     { "pmaxud", { XM, EXx }, PREFIX_OPCODE },
4485   },
4486
4487   /* PREFIX_0F3840 */
4488   {
4489     { Bad_Opcode },
4490     { Bad_Opcode },
4491     { "pmulld", { XM, EXx }, PREFIX_OPCODE },
4492   },
4493
4494   /* PREFIX_0F3841 */
4495   {
4496     { Bad_Opcode },
4497     { Bad_Opcode },
4498     { "phminposuw", { XM, EXx }, PREFIX_OPCODE },
4499   },
4500
4501   /* PREFIX_0F3880 */
4502   {
4503     { Bad_Opcode },
4504     { Bad_Opcode },
4505     { "invept", { Gm, Mo }, PREFIX_OPCODE },
4506   },
4507
4508   /* PREFIX_0F3881 */
4509   {
4510     { Bad_Opcode },
4511     { Bad_Opcode },
4512     { "invvpid", { Gm, Mo }, PREFIX_OPCODE },
4513   },
4514
4515   /* PREFIX_0F3882 */
4516   {
4517     { Bad_Opcode },
4518     { Bad_Opcode },
4519     { "invpcid", { Gm, M }, PREFIX_OPCODE },
4520   },
4521
4522   /* PREFIX_0F38C8 */
4523   {
4524     { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4525   },
4526
4527   /* PREFIX_0F38C9 */
4528   {
4529     { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4530   },
4531
4532   /* PREFIX_0F38CA */
4533   {
4534     { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4535   },
4536
4537   /* PREFIX_0F38CB */
4538   {
4539     { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4540   },
4541
4542   /* PREFIX_0F38CC */
4543   {
4544     { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4545   },
4546
4547   /* PREFIX_0F38CD */
4548   {
4549     { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4550   },
4551
4552   /* PREFIX_0F38DB */
4553   {
4554     { Bad_Opcode },
4555     { Bad_Opcode },
4556     { "aesimc", { XM, EXx }, PREFIX_OPCODE },
4557   },
4558
4559   /* PREFIX_0F38DC */
4560   {
4561     { Bad_Opcode },
4562     { Bad_Opcode },
4563     { "aesenc", { XM, EXx }, PREFIX_OPCODE },
4564   },
4565
4566   /* PREFIX_0F38DD */
4567   {
4568     { Bad_Opcode },
4569     { Bad_Opcode },
4570     { "aesenclast", { XM, EXx }, PREFIX_OPCODE },
4571   },
4572
4573   /* PREFIX_0F38DE */
4574   {
4575     { Bad_Opcode },
4576     { Bad_Opcode },
4577     { "aesdec", { XM, EXx }, PREFIX_OPCODE },
4578   },
4579
4580   /* PREFIX_0F38DF */
4581   {
4582     { Bad_Opcode },
4583     { Bad_Opcode },
4584     { "aesdeclast", { XM, EXx }, PREFIX_OPCODE },
4585   },
4586
4587   /* PREFIX_0F38F0 */
4588   {
4589     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4590     { Bad_Opcode },
4591     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4592     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE },
4593   },
4594
4595   /* PREFIX_0F38F1 */
4596   {
4597     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4598     { Bad_Opcode },
4599     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4600     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE },
4601   },
4602
4603   /* PREFIX_0F38F5 */
4604   {
4605     { Bad_Opcode },
4606     { Bad_Opcode },
4607     { MOD_TABLE (MOD_0F38F5_PREFIX_2) },
4608   },
4609
4610   /* PREFIX_0F38F6 */
4611   {
4612     { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
4613     { "adoxS",  { Gdq, Edq}, PREFIX_OPCODE },
4614     { "adcxS",  { Gdq, Edq}, PREFIX_OPCODE },
4615     { Bad_Opcode },
4616   },
4617
4618   /* PREFIX_0F3A08 */
4619   {
4620     { Bad_Opcode },
4621     { Bad_Opcode },
4622     { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE },
4623   },
4624
4625   /* PREFIX_0F3A09 */
4626   {
4627     { Bad_Opcode },
4628     { Bad_Opcode },
4629     { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4630   },
4631
4632   /* PREFIX_0F3A0A */
4633   {
4634     { Bad_Opcode },
4635     { Bad_Opcode },
4636     { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE },
4637   },
4638
4639   /* PREFIX_0F3A0B */
4640   {
4641     { Bad_Opcode },
4642     { Bad_Opcode },
4643     { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE },
4644   },
4645
4646   /* PREFIX_0F3A0C */
4647   {
4648     { Bad_Opcode },
4649     { Bad_Opcode },
4650     { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE },
4651   },
4652
4653   /* PREFIX_0F3A0D */
4654   {
4655     { Bad_Opcode },
4656     { Bad_Opcode },
4657     { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4658   },
4659
4660   /* PREFIX_0F3A0E */
4661   {
4662     { Bad_Opcode },
4663     { Bad_Opcode },
4664     { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE },
4665   },
4666
4667   /* PREFIX_0F3A14 */
4668   {
4669     { Bad_Opcode },
4670     { Bad_Opcode },
4671     { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE },
4672   },
4673
4674   /* PREFIX_0F3A15 */
4675   {
4676     { Bad_Opcode },
4677     { Bad_Opcode },
4678     { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE },
4679   },
4680
4681   /* PREFIX_0F3A16 */
4682   {
4683     { Bad_Opcode },
4684     { Bad_Opcode },
4685     { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE },
4686   },
4687
4688   /* PREFIX_0F3A17 */
4689   {
4690     { Bad_Opcode },
4691     { Bad_Opcode },
4692     { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE },
4693   },
4694
4695   /* PREFIX_0F3A20 */
4696   {
4697     { Bad_Opcode },
4698     { Bad_Opcode },
4699     { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE },
4700   },
4701
4702   /* PREFIX_0F3A21 */
4703   {
4704     { Bad_Opcode },
4705     { Bad_Opcode },
4706     { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE },
4707   },
4708
4709   /* PREFIX_0F3A22 */
4710   {
4711     { Bad_Opcode },
4712     { Bad_Opcode },
4713     { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE },
4714   },
4715
4716   /* PREFIX_0F3A40 */
4717   {
4718     { Bad_Opcode },
4719     { Bad_Opcode },
4720     { "dpps",   { XM, EXx, Ib }, PREFIX_OPCODE },
4721   },
4722
4723   /* PREFIX_0F3A41 */
4724   {
4725     { Bad_Opcode },
4726     { Bad_Opcode },
4727     { "dppd",   { XM, EXx, Ib }, PREFIX_OPCODE },
4728   },
4729
4730   /* PREFIX_0F3A42 */
4731   {
4732     { Bad_Opcode },
4733     { Bad_Opcode },
4734     { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE },
4735   },
4736
4737   /* PREFIX_0F3A44 */
4738   {
4739     { Bad_Opcode },
4740     { Bad_Opcode },
4741     { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE },
4742   },
4743
4744   /* PREFIX_0F3A60 */
4745   {
4746     { Bad_Opcode },
4747     { Bad_Opcode },
4748     { "pcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4749   },
4750
4751   /* PREFIX_0F3A61 */
4752   {
4753     { Bad_Opcode },
4754     { Bad_Opcode },
4755     { "pcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4756   },
4757
4758   /* PREFIX_0F3A62 */
4759   {
4760     { Bad_Opcode },
4761     { Bad_Opcode },
4762     { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4763   },
4764
4765   /* PREFIX_0F3A63 */
4766   {
4767     { Bad_Opcode },
4768     { Bad_Opcode },
4769     { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE },
4770   },
4771
4772   /* PREFIX_0F3ACC */
4773   {
4774     { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4775   },
4776
4777   /* PREFIX_0F3ADF */
4778   {
4779     { Bad_Opcode },
4780     { Bad_Opcode },
4781     { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE },
4782   },
4783
4784   /* PREFIX_VEX_0F10 */
4785   {
4786     { VEX_W_TABLE (VEX_W_0F10_P_0) },
4787     { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) },
4788     { VEX_W_TABLE (VEX_W_0F10_P_2) },
4789     { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) },
4790   },
4791
4792   /* PREFIX_VEX_0F11 */
4793   {
4794     { VEX_W_TABLE (VEX_W_0F11_P_0) },
4795     { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) },
4796     { VEX_W_TABLE (VEX_W_0F11_P_2) },
4797     { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) },
4798   },
4799
4800   /* PREFIX_VEX_0F12 */
4801   {
4802     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4803     { VEX_W_TABLE (VEX_W_0F12_P_1) },
4804     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
4805     { VEX_W_TABLE (VEX_W_0F12_P_3) },
4806   },
4807
4808   /* PREFIX_VEX_0F16 */
4809   {
4810     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4811     { VEX_W_TABLE (VEX_W_0F16_P_1) },
4812     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
4813   },
4814
4815   /* PREFIX_VEX_0F2A */
4816   {
4817     { Bad_Opcode },
4818     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) },
4819     { Bad_Opcode },
4820     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) },
4821   },
4822
4823   /* PREFIX_VEX_0F2C */
4824   {
4825     { Bad_Opcode },
4826     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) },
4827     { Bad_Opcode },
4828     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) },
4829   },
4830
4831   /* PREFIX_VEX_0F2D */
4832   {
4833     { Bad_Opcode },
4834     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) },
4835     { Bad_Opcode },
4836     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) },
4837   },
4838
4839   /* PREFIX_VEX_0F2E */
4840   {
4841     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) },
4842     { Bad_Opcode },
4843     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) },
4844   },
4845
4846   /* PREFIX_VEX_0F2F */
4847   {
4848     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) },
4849     { Bad_Opcode },
4850     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) },
4851   },
4852
4853   /* PREFIX_VEX_0F41 */
4854   {
4855     { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4856     { Bad_Opcode },
4857     { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4858   },
4859
4860   /* PREFIX_VEX_0F42 */
4861   {
4862     { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4863     { Bad_Opcode },
4864     { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4865   },
4866
4867   /* PREFIX_VEX_0F44 */
4868   {
4869     { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4870     { Bad_Opcode },
4871     { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4872   },
4873
4874   /* PREFIX_VEX_0F45 */
4875   {
4876     { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4877     { Bad_Opcode },
4878     { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4879   },
4880
4881   /* PREFIX_VEX_0F46 */
4882   {
4883     { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4884     { Bad_Opcode },
4885     { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4886   },
4887
4888   /* PREFIX_VEX_0F47 */
4889   {
4890     { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4891     { Bad_Opcode },
4892     { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
4893   },
4894
4895   /* PREFIX_VEX_0F4A */
4896   {
4897     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
4898     { Bad_Opcode },
4899     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
4900   },
4901
4902   /* PREFIX_VEX_0F4B */
4903   {
4904     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
4905     { Bad_Opcode },
4906     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4907   },
4908
4909   /* PREFIX_VEX_0F51 */
4910   {
4911     { VEX_W_TABLE (VEX_W_0F51_P_0) },
4912     { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) },
4913     { VEX_W_TABLE (VEX_W_0F51_P_2) },
4914     { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) },
4915   },
4916
4917   /* PREFIX_VEX_0F52 */
4918   {
4919     { VEX_W_TABLE (VEX_W_0F52_P_0) },
4920     { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) },
4921   },
4922
4923   /* PREFIX_VEX_0F53 */
4924   {
4925     { VEX_W_TABLE (VEX_W_0F53_P_0) },
4926     { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) },
4927   },
4928
4929   /* PREFIX_VEX_0F58 */
4930   {
4931     { VEX_W_TABLE (VEX_W_0F58_P_0) },
4932     { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) },
4933     { VEX_W_TABLE (VEX_W_0F58_P_2) },
4934     { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) },
4935   },
4936
4937   /* PREFIX_VEX_0F59 */
4938   {
4939     { VEX_W_TABLE (VEX_W_0F59_P_0) },
4940     { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) },
4941     { VEX_W_TABLE (VEX_W_0F59_P_2) },
4942     { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) },
4943   },
4944
4945   /* PREFIX_VEX_0F5A */
4946   {
4947     { VEX_W_TABLE (VEX_W_0F5A_P_0) },
4948     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) },
4949     { "vcvtpd2ps%XY", { XMM, EXx }, 0 },
4950     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) },
4951   },
4952
4953   /* PREFIX_VEX_0F5B */
4954   {
4955     { VEX_W_TABLE (VEX_W_0F5B_P_0) },
4956     { VEX_W_TABLE (VEX_W_0F5B_P_1) },
4957     { VEX_W_TABLE (VEX_W_0F5B_P_2) },
4958   },
4959
4960   /* PREFIX_VEX_0F5C */
4961   {
4962     { VEX_W_TABLE (VEX_W_0F5C_P_0) },
4963     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) },
4964     { VEX_W_TABLE (VEX_W_0F5C_P_2) },
4965     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) },
4966   },
4967
4968   /* PREFIX_VEX_0F5D */
4969   {
4970     { VEX_W_TABLE (VEX_W_0F5D_P_0) },
4971     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) },
4972     { VEX_W_TABLE (VEX_W_0F5D_P_2) },
4973     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) },
4974   },
4975
4976   /* PREFIX_VEX_0F5E */
4977   {
4978     { VEX_W_TABLE (VEX_W_0F5E_P_0) },
4979     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) },
4980     { VEX_W_TABLE (VEX_W_0F5E_P_2) },
4981     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) },
4982   },
4983
4984   /* PREFIX_VEX_0F5F */
4985   {
4986     { VEX_W_TABLE (VEX_W_0F5F_P_0) },
4987     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) },
4988     { VEX_W_TABLE (VEX_W_0F5F_P_2) },
4989     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) },
4990   },
4991
4992   /* PREFIX_VEX_0F60 */
4993   {
4994     { Bad_Opcode },
4995     { Bad_Opcode },
4996     { VEX_W_TABLE (VEX_W_0F60_P_2) },
4997   },
4998
4999   /* PREFIX_VEX_0F61 */
5000   {
5001     { Bad_Opcode },
5002     { Bad_Opcode },
5003     { VEX_W_TABLE (VEX_W_0F61_P_2) },
5004   },
5005
5006   /* PREFIX_VEX_0F62 */
5007   {
5008     { Bad_Opcode },
5009     { Bad_Opcode },
5010     { VEX_W_TABLE (VEX_W_0F62_P_2) },
5011   },
5012
5013   /* PREFIX_VEX_0F63 */
5014   {
5015     { Bad_Opcode },
5016     { Bad_Opcode },
5017     { VEX_W_TABLE (VEX_W_0F63_P_2) },
5018   },
5019
5020   /* PREFIX_VEX_0F64 */
5021   {
5022     { Bad_Opcode },
5023     { Bad_Opcode },
5024     { VEX_W_TABLE (VEX_W_0F64_P_2) },
5025   },
5026
5027   /* PREFIX_VEX_0F65 */
5028   {
5029     { Bad_Opcode },
5030     { Bad_Opcode },
5031     { VEX_W_TABLE (VEX_W_0F65_P_2) },
5032   },
5033
5034   /* PREFIX_VEX_0F66 */
5035   {
5036     { Bad_Opcode },
5037     { Bad_Opcode },
5038     { VEX_W_TABLE (VEX_W_0F66_P_2) },
5039   },
5040
5041   /* PREFIX_VEX_0F67 */
5042   {
5043     { Bad_Opcode },
5044     { Bad_Opcode },
5045     { VEX_W_TABLE (VEX_W_0F67_P_2) },
5046   },
5047
5048   /* PREFIX_VEX_0F68 */
5049   {
5050     { Bad_Opcode },
5051     { Bad_Opcode },
5052     { VEX_W_TABLE (VEX_W_0F68_P_2) },
5053   },
5054
5055   /* PREFIX_VEX_0F69 */
5056   {
5057     { Bad_Opcode },
5058     { Bad_Opcode },
5059     { VEX_W_TABLE (VEX_W_0F69_P_2) },
5060   },
5061
5062   /* PREFIX_VEX_0F6A */
5063   {
5064     { Bad_Opcode },
5065     { Bad_Opcode },
5066     { VEX_W_TABLE (VEX_W_0F6A_P_2) },
5067   },
5068
5069   /* PREFIX_VEX_0F6B */
5070   {
5071     { Bad_Opcode },
5072     { Bad_Opcode },
5073     { VEX_W_TABLE (VEX_W_0F6B_P_2) },
5074   },
5075
5076   /* PREFIX_VEX_0F6C */
5077   {
5078     { Bad_Opcode },
5079     { Bad_Opcode },
5080     { VEX_W_TABLE (VEX_W_0F6C_P_2) },
5081   },
5082
5083   /* PREFIX_VEX_0F6D */
5084   {
5085     { Bad_Opcode },
5086     { Bad_Opcode },
5087     { VEX_W_TABLE (VEX_W_0F6D_P_2) },
5088   },
5089
5090   /* PREFIX_VEX_0F6E */
5091   {
5092     { Bad_Opcode },
5093     { Bad_Opcode },
5094     { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
5095   },
5096
5097   /* PREFIX_VEX_0F6F */
5098   {
5099     { Bad_Opcode },
5100     { VEX_W_TABLE (VEX_W_0F6F_P_1) },
5101     { VEX_W_TABLE (VEX_W_0F6F_P_2) },
5102   },
5103
5104   /* PREFIX_VEX_0F70 */
5105   {
5106     { Bad_Opcode },
5107     { VEX_W_TABLE (VEX_W_0F70_P_1) },
5108     { VEX_W_TABLE (VEX_W_0F70_P_2) },
5109     { VEX_W_TABLE (VEX_W_0F70_P_3) },
5110   },
5111
5112   /* PREFIX_VEX_0F71_REG_2 */
5113   {
5114     { Bad_Opcode },
5115     { Bad_Opcode },
5116     { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) },
5117   },
5118
5119   /* PREFIX_VEX_0F71_REG_4 */
5120   {
5121     { Bad_Opcode },
5122     { Bad_Opcode },
5123     { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) },
5124   },
5125
5126   /* PREFIX_VEX_0F71_REG_6 */
5127   {
5128     { Bad_Opcode },
5129     { Bad_Opcode },
5130     { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) },
5131   },
5132
5133   /* PREFIX_VEX_0F72_REG_2 */
5134   {
5135     { Bad_Opcode },
5136     { Bad_Opcode },
5137     { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) },
5138   },
5139
5140   /* PREFIX_VEX_0F72_REG_4 */
5141   {
5142     { Bad_Opcode },
5143     { Bad_Opcode },
5144     { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) },
5145   },
5146
5147   /* PREFIX_VEX_0F72_REG_6 */
5148   {
5149     { Bad_Opcode },
5150     { Bad_Opcode },
5151     { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) },
5152   },
5153
5154   /* PREFIX_VEX_0F73_REG_2 */
5155   {
5156     { Bad_Opcode },
5157     { Bad_Opcode },
5158     { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) },
5159   },
5160
5161   /* PREFIX_VEX_0F73_REG_3 */
5162   {
5163     { Bad_Opcode },
5164     { Bad_Opcode },
5165     { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) },
5166   },
5167
5168   /* PREFIX_VEX_0F73_REG_6 */
5169   {
5170     { Bad_Opcode },
5171     { Bad_Opcode },
5172     { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) },
5173   },
5174
5175   /* PREFIX_VEX_0F73_REG_7 */
5176   {
5177     { Bad_Opcode },
5178     { Bad_Opcode },
5179     { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) },
5180   },
5181
5182   /* PREFIX_VEX_0F74 */
5183   {
5184     { Bad_Opcode },
5185     { Bad_Opcode },
5186     { VEX_W_TABLE (VEX_W_0F74_P_2) },
5187   },
5188
5189   /* PREFIX_VEX_0F75 */
5190   {
5191     { Bad_Opcode },
5192     { Bad_Opcode },
5193     { VEX_W_TABLE (VEX_W_0F75_P_2) },
5194   },
5195
5196   /* PREFIX_VEX_0F76 */
5197   {
5198     { Bad_Opcode },
5199     { Bad_Opcode },
5200     { VEX_W_TABLE (VEX_W_0F76_P_2) },
5201   },
5202
5203   /* PREFIX_VEX_0F77 */
5204   {
5205     { VEX_W_TABLE (VEX_W_0F77_P_0) },
5206   },
5207
5208   /* PREFIX_VEX_0F7C */
5209   {
5210     { Bad_Opcode },
5211     { Bad_Opcode },
5212     { VEX_W_TABLE (VEX_W_0F7C_P_2) },
5213     { VEX_W_TABLE (VEX_W_0F7C_P_3) },
5214   },
5215
5216   /* PREFIX_VEX_0F7D */
5217   {
5218     { Bad_Opcode },
5219     { Bad_Opcode },
5220     { VEX_W_TABLE (VEX_W_0F7D_P_2) },
5221     { VEX_W_TABLE (VEX_W_0F7D_P_3) },
5222   },
5223
5224   /* PREFIX_VEX_0F7E */
5225   {
5226     { Bad_Opcode },
5227     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
5228     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
5229   },
5230
5231   /* PREFIX_VEX_0F7F */
5232   {
5233     { Bad_Opcode },
5234     { VEX_W_TABLE (VEX_W_0F7F_P_1) },
5235     { VEX_W_TABLE (VEX_W_0F7F_P_2) },
5236   },
5237
5238   /* PREFIX_VEX_0F90 */
5239   {
5240     { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
5241     { Bad_Opcode },
5242     { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
5243   },
5244
5245   /* PREFIX_VEX_0F91 */
5246   {
5247     { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
5248     { Bad_Opcode },
5249     { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
5250   },
5251
5252   /* PREFIX_VEX_0F92 */
5253   {
5254     { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
5255     { Bad_Opcode },
5256     { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
5257     { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
5258   },
5259
5260   /* PREFIX_VEX_0F93 */
5261   {
5262     { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
5263     { Bad_Opcode },
5264     { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
5265     { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
5266   },
5267
5268   /* PREFIX_VEX_0F98 */
5269   {
5270     { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
5271     { Bad_Opcode },
5272     { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
5273   },
5274
5275   /* PREFIX_VEX_0F99 */
5276   {
5277     { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5278     { Bad_Opcode },
5279     { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5280   },
5281
5282   /* PREFIX_VEX_0FC2 */
5283   {
5284     { VEX_W_TABLE (VEX_W_0FC2_P_0) },
5285     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) },
5286     { VEX_W_TABLE (VEX_W_0FC2_P_2) },
5287     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) },
5288   },
5289
5290   /* PREFIX_VEX_0FC4 */
5291   {
5292     { Bad_Opcode },
5293     { Bad_Opcode },
5294     { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5295   },
5296
5297   /* PREFIX_VEX_0FC5 */
5298   {
5299     { Bad_Opcode },
5300     { Bad_Opcode },
5301     { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5302   },
5303
5304   /* PREFIX_VEX_0FD0 */
5305   {
5306     { Bad_Opcode },
5307     { Bad_Opcode },
5308     { VEX_W_TABLE (VEX_W_0FD0_P_2) },
5309     { VEX_W_TABLE (VEX_W_0FD0_P_3) },
5310   },
5311
5312   /* PREFIX_VEX_0FD1 */
5313   {
5314     { Bad_Opcode },
5315     { Bad_Opcode },
5316     { VEX_W_TABLE (VEX_W_0FD1_P_2) },
5317   },
5318
5319   /* PREFIX_VEX_0FD2 */
5320   {
5321     { Bad_Opcode },
5322     { Bad_Opcode },
5323     { VEX_W_TABLE (VEX_W_0FD2_P_2) },
5324   },
5325
5326   /* PREFIX_VEX_0FD3 */
5327   {
5328     { Bad_Opcode },
5329     { Bad_Opcode },
5330     { VEX_W_TABLE (VEX_W_0FD3_P_2) },
5331   },
5332
5333   /* PREFIX_VEX_0FD4 */
5334   {
5335     { Bad_Opcode },
5336     { Bad_Opcode },
5337     { VEX_W_TABLE (VEX_W_0FD4_P_2) },
5338   },
5339
5340   /* PREFIX_VEX_0FD5 */
5341   {
5342     { Bad_Opcode },
5343     { Bad_Opcode },
5344     { VEX_W_TABLE (VEX_W_0FD5_P_2) },
5345   },
5346
5347   /* PREFIX_VEX_0FD6 */
5348   {
5349     { Bad_Opcode },
5350     { Bad_Opcode },
5351     { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5352   },
5353
5354   /* PREFIX_VEX_0FD7 */
5355   {
5356     { Bad_Opcode },
5357     { Bad_Opcode },
5358     { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5359   },
5360
5361   /* PREFIX_VEX_0FD8 */
5362   {
5363     { Bad_Opcode },
5364     { Bad_Opcode },
5365     { VEX_W_TABLE (VEX_W_0FD8_P_2) },
5366   },
5367
5368   /* PREFIX_VEX_0FD9 */
5369   {
5370     { Bad_Opcode },
5371     { Bad_Opcode },
5372     { VEX_W_TABLE (VEX_W_0FD9_P_2) },
5373   },
5374
5375   /* PREFIX_VEX_0FDA */
5376   {
5377     { Bad_Opcode },
5378     { Bad_Opcode },
5379     { VEX_W_TABLE (VEX_W_0FDA_P_2) },
5380   },
5381
5382   /* PREFIX_VEX_0FDB */
5383   {
5384     { Bad_Opcode },
5385     { Bad_Opcode },
5386     { VEX_W_TABLE (VEX_W_0FDB_P_2) },
5387   },
5388
5389   /* PREFIX_VEX_0FDC */
5390   {
5391     { Bad_Opcode },
5392     { Bad_Opcode },
5393     { VEX_W_TABLE (VEX_W_0FDC_P_2) },
5394   },
5395
5396   /* PREFIX_VEX_0FDD */
5397   {
5398     { Bad_Opcode },
5399     { Bad_Opcode },
5400     { VEX_W_TABLE (VEX_W_0FDD_P_2) },
5401   },
5402
5403   /* PREFIX_VEX_0FDE */
5404   {
5405     { Bad_Opcode },
5406     { Bad_Opcode },
5407     { VEX_W_TABLE (VEX_W_0FDE_P_2) },
5408   },
5409
5410   /* PREFIX_VEX_0FDF */
5411   {
5412     { Bad_Opcode },
5413     { Bad_Opcode },
5414     { VEX_W_TABLE (VEX_W_0FDF_P_2) },
5415   },
5416
5417   /* PREFIX_VEX_0FE0 */
5418   {
5419     { Bad_Opcode },
5420     { Bad_Opcode },
5421     { VEX_W_TABLE (VEX_W_0FE0_P_2) },
5422   },
5423
5424   /* PREFIX_VEX_0FE1 */
5425   {
5426     { Bad_Opcode },
5427     { Bad_Opcode },
5428     { VEX_W_TABLE (VEX_W_0FE1_P_2) },
5429   },
5430
5431   /* PREFIX_VEX_0FE2 */
5432   {
5433     { Bad_Opcode },
5434     { Bad_Opcode },
5435     { VEX_W_TABLE (VEX_W_0FE2_P_2) },
5436   },
5437
5438   /* PREFIX_VEX_0FE3 */
5439   {
5440     { Bad_Opcode },
5441     { Bad_Opcode },
5442     { VEX_W_TABLE (VEX_W_0FE3_P_2) },
5443   },
5444
5445   /* PREFIX_VEX_0FE4 */
5446   {
5447     { Bad_Opcode },
5448     { Bad_Opcode },
5449     { VEX_W_TABLE (VEX_W_0FE4_P_2) },
5450   },
5451
5452   /* PREFIX_VEX_0FE5 */
5453   {
5454     { Bad_Opcode },
5455     { Bad_Opcode },
5456     { VEX_W_TABLE (VEX_W_0FE5_P_2) },
5457   },
5458
5459   /* PREFIX_VEX_0FE6 */
5460   {
5461     { Bad_Opcode },
5462     { VEX_W_TABLE (VEX_W_0FE6_P_1) },
5463     { VEX_W_TABLE (VEX_W_0FE6_P_2) },
5464     { VEX_W_TABLE (VEX_W_0FE6_P_3) },
5465   },
5466
5467   /* PREFIX_VEX_0FE7 */
5468   {
5469     { Bad_Opcode },
5470     { Bad_Opcode },
5471     { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5472   },
5473
5474   /* PREFIX_VEX_0FE8 */
5475   {
5476     { Bad_Opcode },
5477     { Bad_Opcode },
5478     { VEX_W_TABLE (VEX_W_0FE8_P_2) },
5479   },
5480
5481   /* PREFIX_VEX_0FE9 */
5482   {
5483     { Bad_Opcode },
5484     { Bad_Opcode },
5485     { VEX_W_TABLE (VEX_W_0FE9_P_2) },
5486   },
5487
5488   /* PREFIX_VEX_0FEA */
5489   {
5490     { Bad_Opcode },
5491     { Bad_Opcode },
5492     { VEX_W_TABLE (VEX_W_0FEA_P_2) },
5493   },
5494
5495   /* PREFIX_VEX_0FEB */
5496   {
5497     { Bad_Opcode },
5498     { Bad_Opcode },
5499     { VEX_W_TABLE (VEX_W_0FEB_P_2) },
5500   },
5501
5502   /* PREFIX_VEX_0FEC */
5503   {
5504     { Bad_Opcode },
5505     { Bad_Opcode },
5506     { VEX_W_TABLE (VEX_W_0FEC_P_2) },
5507   },
5508
5509   /* PREFIX_VEX_0FED */
5510   {
5511     { Bad_Opcode },
5512     { Bad_Opcode },
5513     { VEX_W_TABLE (VEX_W_0FED_P_2) },
5514   },
5515
5516   /* PREFIX_VEX_0FEE */
5517   {
5518     { Bad_Opcode },
5519     { Bad_Opcode },
5520     { VEX_W_TABLE (VEX_W_0FEE_P_2) },
5521   },
5522
5523   /* PREFIX_VEX_0FEF */
5524   {
5525     { Bad_Opcode },
5526     { Bad_Opcode },
5527     { VEX_W_TABLE (VEX_W_0FEF_P_2) },
5528   },
5529
5530   /* PREFIX_VEX_0FF0 */
5531   {
5532     { Bad_Opcode },
5533     { Bad_Opcode },
5534     { Bad_Opcode },
5535     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5536   },
5537
5538   /* PREFIX_VEX_0FF1 */
5539   {
5540     { Bad_Opcode },
5541     { Bad_Opcode },
5542     { VEX_W_TABLE (VEX_W_0FF1_P_2) },
5543   },
5544
5545   /* PREFIX_VEX_0FF2 */
5546   {
5547     { Bad_Opcode },
5548     { Bad_Opcode },
5549     { VEX_W_TABLE (VEX_W_0FF2_P_2) },
5550   },
5551
5552   /* PREFIX_VEX_0FF3 */
5553   {
5554     { Bad_Opcode },
5555     { Bad_Opcode },
5556     { VEX_W_TABLE (VEX_W_0FF3_P_2) },
5557   },
5558
5559   /* PREFIX_VEX_0FF4 */
5560   {
5561     { Bad_Opcode },
5562     { Bad_Opcode },
5563     { VEX_W_TABLE (VEX_W_0FF4_P_2) },
5564   },
5565
5566   /* PREFIX_VEX_0FF5 */
5567   {
5568     { Bad_Opcode },
5569     { Bad_Opcode },
5570     { VEX_W_TABLE (VEX_W_0FF5_P_2) },
5571   },
5572
5573   /* PREFIX_VEX_0FF6 */
5574   {
5575     { Bad_Opcode },
5576     { Bad_Opcode },
5577     { VEX_W_TABLE (VEX_W_0FF6_P_2) },
5578   },
5579
5580   /* PREFIX_VEX_0FF7 */
5581   {
5582     { Bad_Opcode },
5583     { Bad_Opcode },
5584     { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5585   },
5586
5587   /* PREFIX_VEX_0FF8 */
5588   {
5589     { Bad_Opcode },
5590     { Bad_Opcode },
5591     { VEX_W_TABLE (VEX_W_0FF8_P_2) },
5592   },
5593
5594   /* PREFIX_VEX_0FF9 */
5595   {
5596     { Bad_Opcode },
5597     { Bad_Opcode },
5598     { VEX_W_TABLE (VEX_W_0FF9_P_2) },
5599   },
5600
5601   /* PREFIX_VEX_0FFA */
5602   {
5603     { Bad_Opcode },
5604     { Bad_Opcode },
5605     { VEX_W_TABLE (VEX_W_0FFA_P_2) },
5606   },
5607
5608   /* PREFIX_VEX_0FFB */
5609   {
5610     { Bad_Opcode },
5611     { Bad_Opcode },
5612     { VEX_W_TABLE (VEX_W_0FFB_P_2) },
5613   },
5614
5615   /* PREFIX_VEX_0FFC */
5616   {
5617     { Bad_Opcode },
5618     { Bad_Opcode },
5619     { VEX_W_TABLE (VEX_W_0FFC_P_2) },
5620   },
5621
5622   /* PREFIX_VEX_0FFD */
5623   {
5624     { Bad_Opcode },
5625     { Bad_Opcode },
5626     { VEX_W_TABLE (VEX_W_0FFD_P_2) },
5627   },
5628
5629   /* PREFIX_VEX_0FFE */
5630   {
5631     { Bad_Opcode },
5632     { Bad_Opcode },
5633     { VEX_W_TABLE (VEX_W_0FFE_P_2) },
5634   },
5635
5636   /* PREFIX_VEX_0F3800 */
5637   {
5638     { Bad_Opcode },
5639     { Bad_Opcode },
5640     { VEX_W_TABLE (VEX_W_0F3800_P_2) },
5641   },
5642
5643   /* PREFIX_VEX_0F3801 */
5644   {
5645     { Bad_Opcode },
5646     { Bad_Opcode },
5647     { VEX_W_TABLE (VEX_W_0F3801_P_2) },
5648   },
5649
5650   /* PREFIX_VEX_0F3802 */
5651   {
5652     { Bad_Opcode },
5653     { Bad_Opcode },
5654     { VEX_W_TABLE (VEX_W_0F3802_P_2) },
5655   },
5656
5657   /* PREFIX_VEX_0F3803 */
5658   {
5659     { Bad_Opcode },
5660     { Bad_Opcode },
5661     { VEX_W_TABLE (VEX_W_0F3803_P_2) },
5662   },
5663
5664   /* PREFIX_VEX_0F3804 */
5665   {
5666     { Bad_Opcode },
5667     { Bad_Opcode },
5668     { VEX_W_TABLE (VEX_W_0F3804_P_2) },
5669   },
5670
5671   /* PREFIX_VEX_0F3805 */
5672   {
5673     { Bad_Opcode },
5674     { Bad_Opcode },
5675     { VEX_W_TABLE (VEX_W_0F3805_P_2) },
5676   },
5677
5678   /* PREFIX_VEX_0F3806 */
5679   {
5680     { Bad_Opcode },
5681     { Bad_Opcode },
5682     { VEX_W_TABLE (VEX_W_0F3806_P_2) },
5683   },
5684
5685   /* PREFIX_VEX_0F3807 */
5686   {
5687     { Bad_Opcode },
5688     { Bad_Opcode },
5689     { VEX_W_TABLE (VEX_W_0F3807_P_2) },
5690   },
5691
5692   /* PREFIX_VEX_0F3808 */
5693   {
5694     { Bad_Opcode },
5695     { Bad_Opcode },
5696     { VEX_W_TABLE (VEX_W_0F3808_P_2) },
5697   },
5698
5699   /* PREFIX_VEX_0F3809 */
5700   {
5701     { Bad_Opcode },
5702     { Bad_Opcode },
5703     { VEX_W_TABLE (VEX_W_0F3809_P_2) },
5704   },
5705
5706   /* PREFIX_VEX_0F380A */
5707   {
5708     { Bad_Opcode },
5709     { Bad_Opcode },
5710     { VEX_W_TABLE (VEX_W_0F380A_P_2) },
5711   },
5712
5713   /* PREFIX_VEX_0F380B */
5714   {
5715     { Bad_Opcode },
5716     { Bad_Opcode },
5717     { VEX_W_TABLE (VEX_W_0F380B_P_2) },
5718   },
5719
5720   /* PREFIX_VEX_0F380C */
5721   {
5722     { Bad_Opcode },
5723     { Bad_Opcode },
5724     { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5725   },
5726
5727   /* PREFIX_VEX_0F380D */
5728   {
5729     { Bad_Opcode },
5730     { Bad_Opcode },
5731     { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5732   },
5733
5734   /* PREFIX_VEX_0F380E */
5735   {
5736     { Bad_Opcode },
5737     { Bad_Opcode },
5738     { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5739   },
5740
5741   /* PREFIX_VEX_0F380F */
5742   {
5743     { Bad_Opcode },
5744     { Bad_Opcode },
5745     { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5746   },
5747
5748   /* PREFIX_VEX_0F3813 */
5749   {
5750     { Bad_Opcode },
5751     { Bad_Opcode },
5752     { "vcvtph2ps", { XM, EXxmmq }, 0 },
5753   },
5754
5755   /* PREFIX_VEX_0F3816 */
5756   {
5757     { Bad_Opcode },
5758     { Bad_Opcode },
5759     { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5760   },
5761
5762   /* PREFIX_VEX_0F3817 */
5763   {
5764     { Bad_Opcode },
5765     { Bad_Opcode },
5766     { VEX_W_TABLE (VEX_W_0F3817_P_2) },
5767   },
5768
5769   /* PREFIX_VEX_0F3818 */
5770   {
5771     { Bad_Opcode },
5772     { Bad_Opcode },
5773     { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5774   },
5775
5776   /* PREFIX_VEX_0F3819 */
5777   {
5778     { Bad_Opcode },
5779     { Bad_Opcode },
5780     { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5781   },
5782
5783   /* PREFIX_VEX_0F381A */
5784   {
5785     { Bad_Opcode },
5786     { Bad_Opcode },
5787     { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5788   },
5789
5790   /* PREFIX_VEX_0F381C */
5791   {
5792     { Bad_Opcode },
5793     { Bad_Opcode },
5794     { VEX_W_TABLE (VEX_W_0F381C_P_2) },
5795   },
5796
5797   /* PREFIX_VEX_0F381D */
5798   {
5799     { Bad_Opcode },
5800     { Bad_Opcode },
5801     { VEX_W_TABLE (VEX_W_0F381D_P_2) },
5802   },
5803
5804   /* PREFIX_VEX_0F381E */
5805   {
5806     { Bad_Opcode },
5807     { Bad_Opcode },
5808     { VEX_W_TABLE (VEX_W_0F381E_P_2) },
5809   },
5810
5811   /* PREFIX_VEX_0F3820 */
5812   {
5813     { Bad_Opcode },
5814     { Bad_Opcode },
5815     { VEX_W_TABLE (VEX_W_0F3820_P_2) },
5816   },
5817
5818   /* PREFIX_VEX_0F3821 */
5819   {
5820     { Bad_Opcode },
5821     { Bad_Opcode },
5822     { VEX_W_TABLE (VEX_W_0F3821_P_2) },
5823   },
5824
5825   /* PREFIX_VEX_0F3822 */
5826   {
5827     { Bad_Opcode },
5828     { Bad_Opcode },
5829     { VEX_W_TABLE (VEX_W_0F3822_P_2) },
5830   },
5831
5832   /* PREFIX_VEX_0F3823 */
5833   {
5834     { Bad_Opcode },
5835     { Bad_Opcode },
5836     { VEX_W_TABLE (VEX_W_0F3823_P_2) },
5837   },
5838
5839   /* PREFIX_VEX_0F3824 */
5840   {
5841     { Bad_Opcode },
5842     { Bad_Opcode },
5843     { VEX_W_TABLE (VEX_W_0F3824_P_2) },
5844   },
5845
5846   /* PREFIX_VEX_0F3825 */
5847   {
5848     { Bad_Opcode },
5849     { Bad_Opcode },
5850     { VEX_W_TABLE (VEX_W_0F3825_P_2) },
5851   },
5852
5853   /* PREFIX_VEX_0F3828 */
5854   {
5855     { Bad_Opcode },
5856     { Bad_Opcode },
5857     { VEX_W_TABLE (VEX_W_0F3828_P_2) },
5858   },
5859
5860   /* PREFIX_VEX_0F3829 */
5861   {
5862     { Bad_Opcode },
5863     { Bad_Opcode },
5864     { VEX_W_TABLE (VEX_W_0F3829_P_2) },
5865   },
5866
5867   /* PREFIX_VEX_0F382A */
5868   {
5869     { Bad_Opcode },
5870     { Bad_Opcode },
5871     { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5872   },
5873
5874   /* PREFIX_VEX_0F382B */
5875   {
5876     { Bad_Opcode },
5877     { Bad_Opcode },
5878     { VEX_W_TABLE (VEX_W_0F382B_P_2) },
5879   },
5880
5881   /* PREFIX_VEX_0F382C */
5882   {
5883     { Bad_Opcode },
5884     { Bad_Opcode },
5885      { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5886   },
5887
5888   /* PREFIX_VEX_0F382D */
5889   {
5890     { Bad_Opcode },
5891     { Bad_Opcode },
5892      { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5893   },
5894
5895   /* PREFIX_VEX_0F382E */
5896   {
5897     { Bad_Opcode },
5898     { Bad_Opcode },
5899      { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5900   },
5901
5902   /* PREFIX_VEX_0F382F */
5903   {
5904     { Bad_Opcode },
5905     { Bad_Opcode },
5906      { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5907   },
5908
5909   /* PREFIX_VEX_0F3830 */
5910   {
5911     { Bad_Opcode },
5912     { Bad_Opcode },
5913     { VEX_W_TABLE (VEX_W_0F3830_P_2) },
5914   },
5915
5916   /* PREFIX_VEX_0F3831 */
5917   {
5918     { Bad_Opcode },
5919     { Bad_Opcode },
5920     { VEX_W_TABLE (VEX_W_0F3831_P_2) },
5921   },
5922
5923   /* PREFIX_VEX_0F3832 */
5924   {
5925     { Bad_Opcode },
5926     { Bad_Opcode },
5927     { VEX_W_TABLE (VEX_W_0F3832_P_2) },
5928   },
5929
5930   /* PREFIX_VEX_0F3833 */
5931   {
5932     { Bad_Opcode },
5933     { Bad_Opcode },
5934     { VEX_W_TABLE (VEX_W_0F3833_P_2) },
5935   },
5936
5937   /* PREFIX_VEX_0F3834 */
5938   {
5939     { Bad_Opcode },
5940     { Bad_Opcode },
5941     { VEX_W_TABLE (VEX_W_0F3834_P_2) },
5942   },
5943
5944   /* PREFIX_VEX_0F3835 */
5945   {
5946     { Bad_Opcode },
5947     { Bad_Opcode },
5948     { VEX_W_TABLE (VEX_W_0F3835_P_2) },
5949   },
5950
5951   /* PREFIX_VEX_0F3836 */
5952   {
5953     { Bad_Opcode },
5954     { Bad_Opcode },
5955     { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5956   },
5957
5958   /* PREFIX_VEX_0F3837 */
5959   {
5960     { Bad_Opcode },
5961     { Bad_Opcode },
5962     { VEX_W_TABLE (VEX_W_0F3837_P_2) },
5963   },
5964
5965   /* PREFIX_VEX_0F3838 */
5966   {
5967     { Bad_Opcode },
5968     { Bad_Opcode },
5969     { VEX_W_TABLE (VEX_W_0F3838_P_2) },
5970   },
5971
5972   /* PREFIX_VEX_0F3839 */
5973   {
5974     { Bad_Opcode },
5975     { Bad_Opcode },
5976     { VEX_W_TABLE (VEX_W_0F3839_P_2) },
5977   },
5978
5979   /* PREFIX_VEX_0F383A */
5980   {
5981     { Bad_Opcode },
5982     { Bad_Opcode },
5983     { VEX_W_TABLE (VEX_W_0F383A_P_2) },
5984   },
5985
5986   /* PREFIX_VEX_0F383B */
5987   {
5988     { Bad_Opcode },
5989     { Bad_Opcode },
5990     { VEX_W_TABLE (VEX_W_0F383B_P_2) },
5991   },
5992
5993   /* PREFIX_VEX_0F383C */
5994   {
5995     { Bad_Opcode },
5996     { Bad_Opcode },
5997     { VEX_W_TABLE (VEX_W_0F383C_P_2) },
5998   },
5999
6000   /* PREFIX_VEX_0F383D */
6001   {
6002     { Bad_Opcode },
6003     { Bad_Opcode },
6004     { VEX_W_TABLE (VEX_W_0F383D_P_2) },
6005   },
6006
6007   /* PREFIX_VEX_0F383E */
6008   {
6009     { Bad_Opcode },
6010     { Bad_Opcode },
6011     { VEX_W_TABLE (VEX_W_0F383E_P_2) },
6012   },
6013
6014   /* PREFIX_VEX_0F383F */
6015   {
6016     { Bad_Opcode },
6017     { Bad_Opcode },
6018     { VEX_W_TABLE (VEX_W_0F383F_P_2) },
6019   },
6020
6021   /* PREFIX_VEX_0F3840 */
6022   {
6023     { Bad_Opcode },
6024     { Bad_Opcode },
6025     { VEX_W_TABLE (VEX_W_0F3840_P_2) },
6026   },
6027
6028   /* PREFIX_VEX_0F3841 */
6029   {
6030     { Bad_Opcode },
6031     { Bad_Opcode },
6032     { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
6033   },
6034
6035   /* PREFIX_VEX_0F3845 */
6036   {
6037     { Bad_Opcode },
6038     { Bad_Opcode },
6039     { "vpsrlv%LW", { XM, Vex, EXx }, 0 },
6040   },
6041
6042   /* PREFIX_VEX_0F3846 */
6043   {
6044     { Bad_Opcode },
6045     { Bad_Opcode },
6046     { VEX_W_TABLE (VEX_W_0F3846_P_2) },
6047   },
6048
6049   /* PREFIX_VEX_0F3847 */
6050   {
6051     { Bad_Opcode },
6052     { Bad_Opcode },
6053     { "vpsllv%LW", { XM, Vex, EXx }, 0 },
6054   },
6055
6056   /* PREFIX_VEX_0F3858 */
6057   {
6058     { Bad_Opcode },
6059     { Bad_Opcode },
6060     { VEX_W_TABLE (VEX_W_0F3858_P_2) },
6061   },
6062
6063   /* PREFIX_VEX_0F3859 */
6064   {
6065     { Bad_Opcode },
6066     { Bad_Opcode },
6067     { VEX_W_TABLE (VEX_W_0F3859_P_2) },
6068   },
6069
6070   /* PREFIX_VEX_0F385A */
6071   {
6072     { Bad_Opcode },
6073     { Bad_Opcode },
6074     { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
6075   },
6076
6077   /* PREFIX_VEX_0F3878 */
6078   {
6079     { Bad_Opcode },
6080     { Bad_Opcode },
6081     { VEX_W_TABLE (VEX_W_0F3878_P_2) },
6082   },
6083
6084   /* PREFIX_VEX_0F3879 */
6085   {
6086     { Bad_Opcode },
6087     { Bad_Opcode },
6088     { VEX_W_TABLE (VEX_W_0F3879_P_2) },
6089   },
6090
6091   /* PREFIX_VEX_0F388C */
6092   {
6093     { Bad_Opcode },
6094     { Bad_Opcode },
6095     { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
6096   },
6097
6098   /* PREFIX_VEX_0F388E */
6099   {
6100     { Bad_Opcode },
6101     { Bad_Opcode },
6102     { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
6103   },
6104
6105   /* PREFIX_VEX_0F3890 */
6106   {
6107     { Bad_Opcode },
6108     { Bad_Opcode },
6109     { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 },
6110   },
6111
6112   /* PREFIX_VEX_0F3891 */
6113   {
6114     { Bad_Opcode },
6115     { Bad_Opcode },
6116     { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6117   },
6118
6119   /* PREFIX_VEX_0F3892 */
6120   {
6121     { Bad_Opcode },
6122     { Bad_Opcode },
6123     { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 },
6124   },
6125
6126   /* PREFIX_VEX_0F3893 */
6127   {
6128     { Bad_Opcode },
6129     { Bad_Opcode },
6130     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6131   },
6132
6133   /* PREFIX_VEX_0F3896 */
6134   {
6135     { Bad_Opcode },
6136     { Bad_Opcode },
6137     { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 },
6138   },
6139
6140   /* PREFIX_VEX_0F3897 */
6141   {
6142     { Bad_Opcode },
6143     { Bad_Opcode },
6144     { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 },
6145   },
6146
6147   /* PREFIX_VEX_0F3898 */
6148   {
6149     { Bad_Opcode },
6150     { Bad_Opcode },
6151     { "vfmadd132p%XW", { XM, Vex, EXx }, 0 },
6152   },
6153
6154   /* PREFIX_VEX_0F3899 */
6155   {
6156     { Bad_Opcode },
6157     { Bad_Opcode },
6158     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6159   },
6160
6161   /* PREFIX_VEX_0F389A */
6162   {
6163     { Bad_Opcode },
6164     { Bad_Opcode },
6165     { "vfmsub132p%XW", { XM, Vex, EXx }, 0 },
6166   },
6167
6168   /* PREFIX_VEX_0F389B */
6169   {
6170     { Bad_Opcode },
6171     { Bad_Opcode },
6172     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6173   },
6174
6175   /* PREFIX_VEX_0F389C */
6176   {
6177     { Bad_Opcode },
6178     { Bad_Opcode },
6179     { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 },
6180   },
6181
6182   /* PREFIX_VEX_0F389D */
6183   {
6184     { Bad_Opcode },
6185     { Bad_Opcode },
6186     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6187   },
6188
6189   /* PREFIX_VEX_0F389E */
6190   {
6191     { Bad_Opcode },
6192     { Bad_Opcode },
6193     { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 },
6194   },
6195
6196   /* PREFIX_VEX_0F389F */
6197   {
6198     { Bad_Opcode },
6199     { Bad_Opcode },
6200     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6201   },
6202
6203   /* PREFIX_VEX_0F38A6 */
6204   {
6205     { Bad_Opcode },
6206     { Bad_Opcode },
6207     { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 },
6208     { Bad_Opcode },
6209   },
6210
6211   /* PREFIX_VEX_0F38A7 */
6212   {
6213     { Bad_Opcode },
6214     { Bad_Opcode },
6215     { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 },
6216   },
6217
6218   /* PREFIX_VEX_0F38A8 */
6219   {
6220     { Bad_Opcode },
6221     { Bad_Opcode },
6222     { "vfmadd213p%XW", { XM, Vex, EXx }, 0 },
6223   },
6224
6225   /* PREFIX_VEX_0F38A9 */
6226   {
6227     { Bad_Opcode },
6228     { Bad_Opcode },
6229     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6230   },
6231
6232   /* PREFIX_VEX_0F38AA */
6233   {
6234     { Bad_Opcode },
6235     { Bad_Opcode },
6236     { "vfmsub213p%XW", { XM, Vex, EXx }, 0 },
6237   },
6238
6239   /* PREFIX_VEX_0F38AB */
6240   {
6241     { Bad_Opcode },
6242     { Bad_Opcode },
6243     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6244   },
6245
6246   /* PREFIX_VEX_0F38AC */
6247   {
6248     { Bad_Opcode },
6249     { Bad_Opcode },
6250     { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 },
6251   },
6252
6253   /* PREFIX_VEX_0F38AD */
6254   {
6255     { Bad_Opcode },
6256     { Bad_Opcode },
6257     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6258   },
6259
6260   /* PREFIX_VEX_0F38AE */
6261   {
6262     { Bad_Opcode },
6263     { Bad_Opcode },
6264     { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 },
6265   },
6266
6267   /* PREFIX_VEX_0F38AF */
6268   {
6269     { Bad_Opcode },
6270     { Bad_Opcode },
6271     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6272   },
6273
6274   /* PREFIX_VEX_0F38B6 */
6275   {
6276     { Bad_Opcode },
6277     { Bad_Opcode },
6278     { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 },
6279   },
6280
6281   /* PREFIX_VEX_0F38B7 */
6282   {
6283     { Bad_Opcode },
6284     { Bad_Opcode },
6285     { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 },
6286   },
6287
6288   /* PREFIX_VEX_0F38B8 */
6289   {
6290     { Bad_Opcode },
6291     { Bad_Opcode },
6292     { "vfmadd231p%XW", { XM, Vex, EXx }, 0 },
6293   },
6294
6295   /* PREFIX_VEX_0F38B9 */
6296   {
6297     { Bad_Opcode },
6298     { Bad_Opcode },
6299     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6300   },
6301
6302   /* PREFIX_VEX_0F38BA */
6303   {
6304     { Bad_Opcode },
6305     { Bad_Opcode },
6306     { "vfmsub231p%XW", { XM, Vex, EXx }, 0 },
6307   },
6308
6309   /* PREFIX_VEX_0F38BB */
6310   {
6311     { Bad_Opcode },
6312     { Bad_Opcode },
6313     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6314   },
6315
6316   /* PREFIX_VEX_0F38BC */
6317   {
6318     { Bad_Opcode },
6319     { Bad_Opcode },
6320     { "vfnmadd231p%XW", { XM, Vex, EXx }, 0 },
6321   },
6322
6323   /* PREFIX_VEX_0F38BD */
6324   {
6325     { Bad_Opcode },
6326     { Bad_Opcode },
6327     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6328   },
6329
6330   /* PREFIX_VEX_0F38BE */
6331   {
6332     { Bad_Opcode },
6333     { Bad_Opcode },
6334     { "vfnmsub231p%XW", { XM, Vex, EXx }, 0 },
6335   },
6336
6337   /* PREFIX_VEX_0F38BF */
6338   {
6339     { Bad_Opcode },
6340     { Bad_Opcode },
6341     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6342   },
6343
6344   /* PREFIX_VEX_0F38DB */
6345   {
6346     { Bad_Opcode },
6347     { Bad_Opcode },
6348     { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6349   },
6350
6351   /* PREFIX_VEX_0F38DC */
6352   {
6353     { Bad_Opcode },
6354     { Bad_Opcode },
6355     { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2) },
6356   },
6357
6358   /* PREFIX_VEX_0F38DD */
6359   {
6360     { Bad_Opcode },
6361     { Bad_Opcode },
6362     { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2) },
6363   },
6364
6365   /* PREFIX_VEX_0F38DE */
6366   {
6367     { Bad_Opcode },
6368     { Bad_Opcode },
6369     { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2) },
6370   },
6371
6372   /* PREFIX_VEX_0F38DF */
6373   {
6374     { Bad_Opcode },
6375     { Bad_Opcode },
6376     { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2) },
6377   },
6378
6379   /* PREFIX_VEX_0F38F2 */
6380   {
6381     { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6382   },
6383
6384   /* PREFIX_VEX_0F38F3_REG_1 */
6385   {
6386     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6387   },
6388
6389   /* PREFIX_VEX_0F38F3_REG_2 */
6390   {
6391     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6392   },
6393
6394   /* PREFIX_VEX_0F38F3_REG_3 */
6395   {
6396     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6397   },
6398
6399   /* PREFIX_VEX_0F38F5 */
6400   {
6401     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6402     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6403     { Bad_Opcode },
6404     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6405   },
6406
6407   /* PREFIX_VEX_0F38F6 */
6408   {
6409     { Bad_Opcode },
6410     { Bad_Opcode },
6411     { Bad_Opcode },
6412     { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6413   },
6414
6415   /* PREFIX_VEX_0F38F7 */
6416   {
6417     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6418     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6419     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6420     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6421   },
6422
6423   /* PREFIX_VEX_0F3A00 */
6424   {
6425     { Bad_Opcode },
6426     { Bad_Opcode },
6427     { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6428   },
6429
6430   /* PREFIX_VEX_0F3A01 */
6431   {
6432     { Bad_Opcode },
6433     { Bad_Opcode },
6434     { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6435   },
6436
6437   /* PREFIX_VEX_0F3A02 */
6438   {
6439     { Bad_Opcode },
6440     { Bad_Opcode },
6441     { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6442   },
6443
6444   /* PREFIX_VEX_0F3A04 */
6445   {
6446     { Bad_Opcode },
6447     { Bad_Opcode },
6448     { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6449   },
6450
6451   /* PREFIX_VEX_0F3A05 */
6452   {
6453     { Bad_Opcode },
6454     { Bad_Opcode },
6455     { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6456   },
6457
6458   /* PREFIX_VEX_0F3A06 */
6459   {
6460     { Bad_Opcode },
6461     { Bad_Opcode },
6462     { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6463   },
6464
6465   /* PREFIX_VEX_0F3A08 */
6466   {
6467     { Bad_Opcode },
6468     { Bad_Opcode },
6469     { VEX_W_TABLE (VEX_W_0F3A08_P_2) },
6470   },
6471
6472   /* PREFIX_VEX_0F3A09 */
6473   {
6474     { Bad_Opcode },
6475     { Bad_Opcode },
6476     { VEX_W_TABLE (VEX_W_0F3A09_P_2) },
6477   },
6478
6479   /* PREFIX_VEX_0F3A0A */
6480   {
6481     { Bad_Opcode },
6482     { Bad_Opcode },
6483     { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) },
6484   },
6485
6486   /* PREFIX_VEX_0F3A0B */
6487   {
6488     { Bad_Opcode },
6489     { Bad_Opcode },
6490     { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) },
6491   },
6492
6493   /* PREFIX_VEX_0F3A0C */
6494   {
6495     { Bad_Opcode },
6496     { Bad_Opcode },
6497     { VEX_W_TABLE (VEX_W_0F3A0C_P_2) },
6498   },
6499
6500   /* PREFIX_VEX_0F3A0D */
6501   {
6502     { Bad_Opcode },
6503     { Bad_Opcode },
6504     { VEX_W_TABLE (VEX_W_0F3A0D_P_2) },
6505   },
6506
6507   /* PREFIX_VEX_0F3A0E */
6508   {
6509     { Bad_Opcode },
6510     { Bad_Opcode },
6511     { VEX_W_TABLE (VEX_W_0F3A0E_P_2) },
6512   },
6513
6514   /* PREFIX_VEX_0F3A0F */
6515   {
6516     { Bad_Opcode },
6517     { Bad_Opcode },
6518     { VEX_W_TABLE (VEX_W_0F3A0F_P_2) },
6519   },
6520
6521   /* PREFIX_VEX_0F3A14 */
6522   {
6523     { Bad_Opcode },
6524     { Bad_Opcode },
6525     { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6526   },
6527
6528   /* PREFIX_VEX_0F3A15 */
6529   {
6530     { Bad_Opcode },
6531     { Bad_Opcode },
6532     { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6533   },
6534
6535   /* PREFIX_VEX_0F3A16 */
6536   {
6537     { Bad_Opcode },
6538     { Bad_Opcode },
6539     { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6540   },
6541
6542   /* PREFIX_VEX_0F3A17 */
6543   {
6544     { Bad_Opcode },
6545     { Bad_Opcode },
6546     { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6547   },
6548
6549   /* PREFIX_VEX_0F3A18 */
6550   {
6551     { Bad_Opcode },
6552     { Bad_Opcode },
6553     { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6554   },
6555
6556   /* PREFIX_VEX_0F3A19 */
6557   {
6558     { Bad_Opcode },
6559     { Bad_Opcode },
6560     { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6561   },
6562
6563   /* PREFIX_VEX_0F3A1D */
6564   {
6565     { Bad_Opcode },
6566     { Bad_Opcode },
6567     { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 },
6568   },
6569
6570   /* PREFIX_VEX_0F3A20 */
6571   {
6572     { Bad_Opcode },
6573     { Bad_Opcode },
6574     { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6575   },
6576
6577   /* PREFIX_VEX_0F3A21 */
6578   {
6579     { Bad_Opcode },
6580     { Bad_Opcode },
6581     { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6582   },
6583
6584   /* PREFIX_VEX_0F3A22 */
6585   {
6586     { Bad_Opcode },
6587     { Bad_Opcode },
6588     { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6589   },
6590
6591   /* PREFIX_VEX_0F3A30 */
6592   {
6593     { Bad_Opcode },
6594     { Bad_Opcode },
6595     { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6596   },
6597
6598   /* PREFIX_VEX_0F3A31 */
6599   {
6600     { Bad_Opcode },
6601     { Bad_Opcode },
6602     { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6603   },
6604
6605   /* PREFIX_VEX_0F3A32 */
6606   {
6607     { Bad_Opcode },
6608     { Bad_Opcode },
6609     { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6610   },
6611
6612   /* PREFIX_VEX_0F3A33 */
6613   {
6614     { Bad_Opcode },
6615     { Bad_Opcode },
6616     { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6617   },
6618
6619   /* PREFIX_VEX_0F3A38 */
6620   {
6621     { Bad_Opcode },
6622     { Bad_Opcode },
6623     { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6624   },
6625
6626   /* PREFIX_VEX_0F3A39 */
6627   {
6628     { Bad_Opcode },
6629     { Bad_Opcode },
6630     { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6631   },
6632
6633   /* PREFIX_VEX_0F3A40 */
6634   {
6635     { Bad_Opcode },
6636     { Bad_Opcode },
6637     { VEX_W_TABLE (VEX_W_0F3A40_P_2) },
6638   },
6639
6640   /* PREFIX_VEX_0F3A41 */
6641   {
6642     { Bad_Opcode },
6643     { Bad_Opcode },
6644     { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6645   },
6646
6647   /* PREFIX_VEX_0F3A42 */
6648   {
6649     { Bad_Opcode },
6650     { Bad_Opcode },
6651     { VEX_W_TABLE (VEX_W_0F3A42_P_2) },
6652   },
6653
6654   /* PREFIX_VEX_0F3A44 */
6655   {
6656     { Bad_Opcode },
6657     { Bad_Opcode },
6658     { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2) },
6659   },
6660
6661   /* PREFIX_VEX_0F3A46 */
6662   {
6663     { Bad_Opcode },
6664     { Bad_Opcode },
6665     { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6666   },
6667
6668   /* PREFIX_VEX_0F3A48 */
6669   {
6670     { Bad_Opcode },
6671     { Bad_Opcode },
6672     { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6673   },
6674
6675   /* PREFIX_VEX_0F3A49 */
6676   {
6677     { Bad_Opcode },
6678     { Bad_Opcode },
6679     { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6680   },
6681
6682   /* PREFIX_VEX_0F3A4A */
6683   {
6684     { Bad_Opcode },
6685     { Bad_Opcode },
6686     { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6687   },
6688
6689   /* PREFIX_VEX_0F3A4B */
6690   {
6691     { Bad_Opcode },
6692     { Bad_Opcode },
6693     { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6694   },
6695
6696   /* PREFIX_VEX_0F3A4C */
6697   {
6698     { Bad_Opcode },
6699     { Bad_Opcode },
6700     { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6701   },
6702
6703   /* PREFIX_VEX_0F3A5C */
6704   {
6705     { Bad_Opcode },
6706     { Bad_Opcode },
6707     { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6708   },
6709
6710   /* PREFIX_VEX_0F3A5D */
6711   {
6712     { Bad_Opcode },
6713     { Bad_Opcode },
6714     { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6715   },
6716
6717   /* PREFIX_VEX_0F3A5E */
6718   {
6719     { Bad_Opcode },
6720     { Bad_Opcode },
6721     { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6722   },
6723
6724   /* PREFIX_VEX_0F3A5F */
6725   {
6726     { Bad_Opcode },
6727     { Bad_Opcode },
6728     { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6729   },
6730
6731   /* PREFIX_VEX_0F3A60 */
6732   {
6733     { Bad_Opcode },
6734     { Bad_Opcode },
6735     { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6736     { Bad_Opcode },
6737   },
6738
6739   /* PREFIX_VEX_0F3A61 */
6740   {
6741     { Bad_Opcode },
6742     { Bad_Opcode },
6743     { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6744   },
6745
6746   /* PREFIX_VEX_0F3A62 */
6747   {
6748     { Bad_Opcode },
6749     { Bad_Opcode },
6750     { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6751   },
6752
6753   /* PREFIX_VEX_0F3A63 */
6754   {
6755     { Bad_Opcode },
6756     { Bad_Opcode },
6757     { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6758   },
6759
6760   /* PREFIX_VEX_0F3A68 */
6761   {
6762     { Bad_Opcode },
6763     { Bad_Opcode },
6764     { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6765   },
6766
6767   /* PREFIX_VEX_0F3A69 */
6768   {
6769     { Bad_Opcode },
6770     { Bad_Opcode },
6771     { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6772   },
6773
6774   /* PREFIX_VEX_0F3A6A */
6775   {
6776     { Bad_Opcode },
6777     { Bad_Opcode },
6778     { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6779   },
6780
6781   /* PREFIX_VEX_0F3A6B */
6782   {
6783     { Bad_Opcode },
6784     { Bad_Opcode },
6785     { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6786   },
6787
6788   /* PREFIX_VEX_0F3A6C */
6789   {
6790     { Bad_Opcode },
6791     { Bad_Opcode },
6792     { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6793   },
6794
6795   /* PREFIX_VEX_0F3A6D */
6796   {
6797     { Bad_Opcode },
6798     { Bad_Opcode },
6799     { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6800   },
6801
6802   /* PREFIX_VEX_0F3A6E */
6803   {
6804     { Bad_Opcode },
6805     { Bad_Opcode },
6806     { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6807   },
6808
6809   /* PREFIX_VEX_0F3A6F */
6810   {
6811     { Bad_Opcode },
6812     { Bad_Opcode },
6813     { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6814   },
6815
6816   /* PREFIX_VEX_0F3A78 */
6817   {
6818     { Bad_Opcode },
6819     { Bad_Opcode },
6820     { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6821   },
6822
6823   /* PREFIX_VEX_0F3A79 */
6824   {
6825     { Bad_Opcode },
6826     { Bad_Opcode },
6827     { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6828   },
6829
6830   /* PREFIX_VEX_0F3A7A */
6831   {
6832     { Bad_Opcode },
6833     { Bad_Opcode },
6834     { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6835   },
6836
6837   /* PREFIX_VEX_0F3A7B */
6838   {
6839     { Bad_Opcode },
6840     { Bad_Opcode },
6841     { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6842   },
6843
6844   /* PREFIX_VEX_0F3A7C */
6845   {
6846     { Bad_Opcode },
6847     { Bad_Opcode },
6848     { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6849     { Bad_Opcode },
6850   },
6851
6852   /* PREFIX_VEX_0F3A7D */
6853   {
6854     { Bad_Opcode },
6855     { Bad_Opcode },
6856     { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6857   },
6858
6859   /* PREFIX_VEX_0F3A7E */
6860   {
6861     { Bad_Opcode },
6862     { Bad_Opcode },
6863     { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6864   },
6865
6866   /* PREFIX_VEX_0F3A7F */
6867   {
6868     { Bad_Opcode },
6869     { Bad_Opcode },
6870     { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6871   },
6872
6873   /* PREFIX_VEX_0F3ADF */
6874   {
6875     { Bad_Opcode },
6876     { Bad_Opcode },
6877     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6878   },
6879
6880   /* PREFIX_VEX_0F3AF0 */
6881   {
6882     { Bad_Opcode },
6883     { Bad_Opcode },
6884     { Bad_Opcode },
6885     { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6886   },
6887
6888 #define NEED_PREFIX_TABLE
6889 #include "i386-dis-evex.h"
6890 #undef NEED_PREFIX_TABLE
6891 };
6892
6893 static const struct dis386 x86_64_table[][2] = {
6894   /* X86_64_06 */
6895   {
6896     { "pushP", { es }, 0 },
6897   },
6898
6899   /* X86_64_07 */
6900   {
6901     { "popP", { es }, 0 },
6902   },
6903
6904   /* X86_64_0D */
6905   {
6906     { "pushP", { cs }, 0 },
6907   },
6908
6909   /* X86_64_16 */
6910   {
6911     { "pushP", { ss }, 0 },
6912   },
6913
6914   /* X86_64_17 */
6915   {
6916     { "popP", { ss }, 0 },
6917   },
6918
6919   /* X86_64_1E */
6920   {
6921     { "pushP", { ds }, 0 },
6922   },
6923
6924   /* X86_64_1F */
6925   {
6926     { "popP", { ds }, 0 },
6927   },
6928
6929   /* X86_64_27 */
6930   {
6931     { "daa", { XX }, 0 },
6932   },
6933
6934   /* X86_64_2F */
6935   {
6936     { "das", { XX }, 0 },
6937   },
6938
6939   /* X86_64_37 */
6940   {
6941     { "aaa", { XX }, 0 },
6942   },
6943
6944   /* X86_64_3F */
6945   {
6946     { "aas", { XX }, 0 },
6947   },
6948
6949   /* X86_64_60 */
6950   {
6951     { "pushaP", { XX }, 0 },
6952   },
6953
6954   /* X86_64_61 */
6955   {
6956     { "popaP", { XX }, 0 },
6957   },
6958
6959   /* X86_64_62 */
6960   {
6961     { MOD_TABLE (MOD_62_32BIT) },
6962     { EVEX_TABLE (EVEX_0F) },
6963   },
6964
6965   /* X86_64_63 */
6966   {
6967     { "arpl", { Ew, Gw }, 0 },
6968     { "movs{lq|xd}", { Gv, Ed }, 0 },
6969   },
6970
6971   /* X86_64_6D */
6972   {
6973     { "ins{R|}", { Yzr, indirDX }, 0 },
6974     { "ins{G|}", { Yzr, indirDX }, 0 },
6975   },
6976
6977   /* X86_64_6F */
6978   {
6979     { "outs{R|}", { indirDXr, Xz }, 0 },
6980     { "outs{G|}", { indirDXr, Xz }, 0 },
6981   },
6982
6983   /* X86_64_82 */
6984   {
6985     /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode.  */
6986     { REG_TABLE (REG_80) },
6987   },
6988
6989   /* X86_64_9A */
6990   {
6991     { "Jcall{T|}", { Ap }, 0 },
6992   },
6993
6994   /* X86_64_C4 */
6995   {
6996     { MOD_TABLE (MOD_C4_32BIT) },
6997     { VEX_C4_TABLE (VEX_0F) },
6998   },
6999
7000   /* X86_64_C5 */
7001   {
7002     { MOD_TABLE (MOD_C5_32BIT) },
7003     { VEX_C5_TABLE (VEX_0F) },
7004   },
7005
7006   /* X86_64_CE */
7007   {
7008     { "into", { XX }, 0 },
7009   },
7010
7011   /* X86_64_D4 */
7012   {
7013     { "aam", { Ib }, 0 },
7014   },
7015
7016   /* X86_64_D5 */
7017   {
7018     { "aad", { Ib }, 0 },
7019   },
7020
7021   /* X86_64_E8 */
7022   {
7023     { "callP",          { Jv, BND }, 0 },
7024     { "call@",          { Jv, BND }, 0 }
7025   },
7026
7027   /* X86_64_E9 */
7028   {
7029     { "jmpP",           { Jv, BND }, 0 },
7030     { "jmp@",           { Jv, BND }, 0 }
7031   },
7032
7033   /* X86_64_EA */
7034   {
7035     { "Jjmp{T|}", { Ap }, 0 },
7036   },
7037
7038   /* X86_64_0F01_REG_0 */
7039   {
7040     { "sgdt{Q|IQ}", { M }, 0 },
7041     { "sgdt", { M }, 0 },
7042   },
7043
7044   /* X86_64_0F01_REG_1 */
7045   {
7046     { "sidt{Q|IQ}", { M }, 0 },
7047     { "sidt", { M }, 0 },
7048   },
7049
7050   /* X86_64_0F01_REG_2 */
7051   {
7052     { "lgdt{Q|Q}", { M }, 0 },
7053     { "lgdt", { M }, 0 },
7054   },
7055
7056   /* X86_64_0F01_REG_3 */
7057   {
7058     { "lidt{Q|Q}", { M }, 0 },
7059     { "lidt", { M }, 0 },
7060   },
7061 };
7062
7063 static const struct dis386 three_byte_table[][256] = {
7064
7065   /* THREE_BYTE_0F38 */
7066   {
7067     /* 00 */
7068     { "pshufb",         { MX, EM }, PREFIX_OPCODE },
7069     { "phaddw",         { MX, EM }, PREFIX_OPCODE },
7070     { "phaddd",         { MX, EM }, PREFIX_OPCODE },
7071     { "phaddsw",        { MX, EM }, PREFIX_OPCODE },
7072     { "pmaddubsw",      { MX, EM }, PREFIX_OPCODE },
7073     { "phsubw",         { MX, EM }, PREFIX_OPCODE },
7074     { "phsubd",         { MX, EM }, PREFIX_OPCODE },
7075     { "phsubsw",        { MX, EM }, PREFIX_OPCODE },
7076     /* 08 */
7077     { "psignb",         { MX, EM }, PREFIX_OPCODE },
7078     { "psignw",         { MX, EM }, PREFIX_OPCODE },
7079     { "psignd",         { MX, EM }, PREFIX_OPCODE },
7080     { "pmulhrsw",       { MX, EM }, PREFIX_OPCODE },
7081     { Bad_Opcode },
7082     { Bad_Opcode },
7083     { Bad_Opcode },
7084     { Bad_Opcode },
7085     /* 10 */
7086     { PREFIX_TABLE (PREFIX_0F3810) },
7087     { Bad_Opcode },
7088     { Bad_Opcode },
7089     { Bad_Opcode },
7090     { PREFIX_TABLE (PREFIX_0F3814) },
7091     { PREFIX_TABLE (PREFIX_0F3815) },
7092     { Bad_Opcode },
7093     { PREFIX_TABLE (PREFIX_0F3817) },
7094     /* 18 */
7095     { Bad_Opcode },
7096     { Bad_Opcode },
7097     { Bad_Opcode },
7098     { Bad_Opcode },
7099     { "pabsb",          { MX, EM }, PREFIX_OPCODE },
7100     { "pabsw",          { MX, EM }, PREFIX_OPCODE },
7101     { "pabsd",          { MX, EM }, PREFIX_OPCODE },
7102     { Bad_Opcode },
7103     /* 20 */
7104     { PREFIX_TABLE (PREFIX_0F3820) },
7105     { PREFIX_TABLE (PREFIX_0F3821) },
7106     { PREFIX_TABLE (PREFIX_0F3822) },
7107     { PREFIX_TABLE (PREFIX_0F3823) },
7108     { PREFIX_TABLE (PREFIX_0F3824) },
7109     { PREFIX_TABLE (PREFIX_0F3825) },
7110     { Bad_Opcode },
7111     { Bad_Opcode },
7112     /* 28 */
7113     { PREFIX_TABLE (PREFIX_0F3828) },
7114     { PREFIX_TABLE (PREFIX_0F3829) },
7115     { PREFIX_TABLE (PREFIX_0F382A) },
7116     { PREFIX_TABLE (PREFIX_0F382B) },
7117     { Bad_Opcode },
7118     { Bad_Opcode },
7119     { Bad_Opcode },
7120     { Bad_Opcode },
7121     /* 30 */
7122     { PREFIX_TABLE (PREFIX_0F3830) },
7123     { PREFIX_TABLE (PREFIX_0F3831) },
7124     { PREFIX_TABLE (PREFIX_0F3832) },
7125     { PREFIX_TABLE (PREFIX_0F3833) },
7126     { PREFIX_TABLE (PREFIX_0F3834) },
7127     { PREFIX_TABLE (PREFIX_0F3835) },
7128     { Bad_Opcode },
7129     { PREFIX_TABLE (PREFIX_0F3837) },
7130     /* 38 */
7131     { PREFIX_TABLE (PREFIX_0F3838) },
7132     { PREFIX_TABLE (PREFIX_0F3839) },
7133     { PREFIX_TABLE (PREFIX_0F383A) },
7134     { PREFIX_TABLE (PREFIX_0F383B) },
7135     { PREFIX_TABLE (PREFIX_0F383C) },
7136     { PREFIX_TABLE (PREFIX_0F383D) },
7137     { PREFIX_TABLE (PREFIX_0F383E) },
7138     { PREFIX_TABLE (PREFIX_0F383F) },
7139     /* 40 */
7140     { PREFIX_TABLE (PREFIX_0F3840) },
7141     { PREFIX_TABLE (PREFIX_0F3841) },
7142     { Bad_Opcode },
7143     { Bad_Opcode },
7144     { Bad_Opcode },
7145     { Bad_Opcode },
7146     { Bad_Opcode },
7147     { Bad_Opcode },
7148     /* 48 */
7149     { Bad_Opcode },
7150     { Bad_Opcode },
7151     { Bad_Opcode },
7152     { Bad_Opcode },
7153     { Bad_Opcode },
7154     { Bad_Opcode },
7155     { Bad_Opcode },
7156     { Bad_Opcode },
7157     /* 50 */
7158     { Bad_Opcode },
7159     { Bad_Opcode },
7160     { Bad_Opcode },
7161     { Bad_Opcode },
7162     { Bad_Opcode },
7163     { Bad_Opcode },
7164     { Bad_Opcode },
7165     { Bad_Opcode },
7166     /* 58 */
7167     { Bad_Opcode },
7168     { Bad_Opcode },
7169     { Bad_Opcode },
7170     { Bad_Opcode },
7171     { Bad_Opcode },
7172     { Bad_Opcode },
7173     { Bad_Opcode },
7174     { Bad_Opcode },
7175     /* 60 */
7176     { Bad_Opcode },
7177     { Bad_Opcode },
7178     { Bad_Opcode },
7179     { Bad_Opcode },
7180     { Bad_Opcode },
7181     { Bad_Opcode },
7182     { Bad_Opcode },
7183     { Bad_Opcode },
7184     /* 68 */
7185     { Bad_Opcode },
7186     { Bad_Opcode },
7187     { Bad_Opcode },
7188     { Bad_Opcode },
7189     { Bad_Opcode },
7190     { Bad_Opcode },
7191     { Bad_Opcode },
7192     { Bad_Opcode },
7193     /* 70 */
7194     { Bad_Opcode },
7195     { Bad_Opcode },
7196     { Bad_Opcode },
7197     { Bad_Opcode },
7198     { Bad_Opcode },
7199     { Bad_Opcode },
7200     { Bad_Opcode },
7201     { Bad_Opcode },
7202     /* 78 */
7203     { Bad_Opcode },
7204     { Bad_Opcode },
7205     { Bad_Opcode },
7206     { Bad_Opcode },
7207     { Bad_Opcode },
7208     { Bad_Opcode },
7209     { Bad_Opcode },
7210     { Bad_Opcode },
7211     /* 80 */
7212     { PREFIX_TABLE (PREFIX_0F3880) },
7213     { PREFIX_TABLE (PREFIX_0F3881) },
7214     { PREFIX_TABLE (PREFIX_0F3882) },
7215     { Bad_Opcode },
7216     { Bad_Opcode },
7217     { Bad_Opcode },
7218     { Bad_Opcode },
7219     { Bad_Opcode },
7220     /* 88 */
7221     { Bad_Opcode },
7222     { Bad_Opcode },
7223     { Bad_Opcode },
7224     { Bad_Opcode },
7225     { Bad_Opcode },
7226     { Bad_Opcode },
7227     { Bad_Opcode },
7228     { Bad_Opcode },
7229     /* 90 */
7230     { Bad_Opcode },
7231     { Bad_Opcode },
7232     { Bad_Opcode },
7233     { Bad_Opcode },
7234     { Bad_Opcode },
7235     { Bad_Opcode },
7236     { Bad_Opcode },
7237     { Bad_Opcode },
7238     /* 98 */
7239     { Bad_Opcode },
7240     { Bad_Opcode },
7241     { Bad_Opcode },
7242     { Bad_Opcode },
7243     { Bad_Opcode },
7244     { Bad_Opcode },
7245     { Bad_Opcode },
7246     { Bad_Opcode },
7247     /* a0 */
7248     { Bad_Opcode },
7249     { Bad_Opcode },
7250     { Bad_Opcode },
7251     { Bad_Opcode },
7252     { Bad_Opcode },
7253     { Bad_Opcode },
7254     { Bad_Opcode },
7255     { Bad_Opcode },
7256     /* a8 */
7257     { Bad_Opcode },
7258     { Bad_Opcode },
7259     { Bad_Opcode },
7260     { Bad_Opcode },
7261     { Bad_Opcode },
7262     { Bad_Opcode },
7263     { Bad_Opcode },
7264     { Bad_Opcode },
7265     /* b0 */
7266     { Bad_Opcode },
7267     { Bad_Opcode },
7268     { Bad_Opcode },
7269     { Bad_Opcode },
7270     { Bad_Opcode },
7271     { Bad_Opcode },
7272     { Bad_Opcode },
7273     { Bad_Opcode },
7274     /* b8 */
7275     { Bad_Opcode },
7276     { Bad_Opcode },
7277     { Bad_Opcode },
7278     { Bad_Opcode },
7279     { Bad_Opcode },
7280     { Bad_Opcode },
7281     { Bad_Opcode },
7282     { Bad_Opcode },
7283     /* c0 */
7284     { Bad_Opcode },
7285     { Bad_Opcode },
7286     { Bad_Opcode },
7287     { Bad_Opcode },
7288     { Bad_Opcode },
7289     { Bad_Opcode },
7290     { Bad_Opcode },
7291     { Bad_Opcode },
7292     /* c8 */
7293     { PREFIX_TABLE (PREFIX_0F38C8) },
7294     { PREFIX_TABLE (PREFIX_0F38C9) },
7295     { PREFIX_TABLE (PREFIX_0F38CA) },
7296     { PREFIX_TABLE (PREFIX_0F38CB) },
7297     { PREFIX_TABLE (PREFIX_0F38CC) },
7298     { PREFIX_TABLE (PREFIX_0F38CD) },
7299     { Bad_Opcode },
7300     { Bad_Opcode },
7301     /* d0 */
7302     { Bad_Opcode },
7303     { Bad_Opcode },
7304     { Bad_Opcode },
7305     { Bad_Opcode },
7306     { Bad_Opcode },
7307     { Bad_Opcode },
7308     { Bad_Opcode },
7309     { Bad_Opcode },
7310     /* d8 */
7311     { Bad_Opcode },
7312     { Bad_Opcode },
7313     { Bad_Opcode },
7314     { PREFIX_TABLE (PREFIX_0F38DB) },
7315     { PREFIX_TABLE (PREFIX_0F38DC) },
7316     { PREFIX_TABLE (PREFIX_0F38DD) },
7317     { PREFIX_TABLE (PREFIX_0F38DE) },
7318     { PREFIX_TABLE (PREFIX_0F38DF) },
7319     /* e0 */
7320     { Bad_Opcode },
7321     { Bad_Opcode },
7322     { Bad_Opcode },
7323     { Bad_Opcode },
7324     { Bad_Opcode },
7325     { Bad_Opcode },
7326     { Bad_Opcode },
7327     { Bad_Opcode },
7328     /* e8 */
7329     { Bad_Opcode },
7330     { Bad_Opcode },
7331     { Bad_Opcode },
7332     { Bad_Opcode },
7333     { Bad_Opcode },
7334     { Bad_Opcode },
7335     { Bad_Opcode },
7336     { Bad_Opcode },
7337     /* f0 */
7338     { PREFIX_TABLE (PREFIX_0F38F0) },
7339     { PREFIX_TABLE (PREFIX_0F38F1) },
7340     { Bad_Opcode },
7341     { Bad_Opcode },
7342     { Bad_Opcode },
7343     { PREFIX_TABLE (PREFIX_0F38F5) },
7344     { PREFIX_TABLE (PREFIX_0F38F6) },
7345     { Bad_Opcode },
7346     /* f8 */
7347     { Bad_Opcode },
7348     { Bad_Opcode },
7349     { Bad_Opcode },
7350     { Bad_Opcode },
7351     { Bad_Opcode },
7352     { Bad_Opcode },
7353     { Bad_Opcode },
7354     { Bad_Opcode },
7355   },
7356   /* THREE_BYTE_0F3A */
7357   {
7358     /* 00 */
7359     { Bad_Opcode },
7360     { Bad_Opcode },
7361     { Bad_Opcode },
7362     { Bad_Opcode },
7363     { Bad_Opcode },
7364     { Bad_Opcode },
7365     { Bad_Opcode },
7366     { Bad_Opcode },
7367     /* 08 */
7368     { PREFIX_TABLE (PREFIX_0F3A08) },
7369     { PREFIX_TABLE (PREFIX_0F3A09) },
7370     { PREFIX_TABLE (PREFIX_0F3A0A) },
7371     { PREFIX_TABLE (PREFIX_0F3A0B) },
7372     { PREFIX_TABLE (PREFIX_0F3A0C) },
7373     { PREFIX_TABLE (PREFIX_0F3A0D) },
7374     { PREFIX_TABLE (PREFIX_0F3A0E) },
7375     { "palignr",        { MX, EM, Ib }, PREFIX_OPCODE },
7376     /* 10 */
7377     { Bad_Opcode },
7378     { Bad_Opcode },
7379     { Bad_Opcode },
7380     { Bad_Opcode },
7381     { PREFIX_TABLE (PREFIX_0F3A14) },
7382     { PREFIX_TABLE (PREFIX_0F3A15) },
7383     { PREFIX_TABLE (PREFIX_0F3A16) },
7384     { PREFIX_TABLE (PREFIX_0F3A17) },
7385     /* 18 */
7386     { Bad_Opcode },
7387     { Bad_Opcode },
7388     { Bad_Opcode },
7389     { Bad_Opcode },
7390     { Bad_Opcode },
7391     { Bad_Opcode },
7392     { Bad_Opcode },
7393     { Bad_Opcode },
7394     /* 20 */
7395     { PREFIX_TABLE (PREFIX_0F3A20) },
7396     { PREFIX_TABLE (PREFIX_0F3A21) },
7397     { PREFIX_TABLE (PREFIX_0F3A22) },
7398     { Bad_Opcode },
7399     { Bad_Opcode },
7400     { Bad_Opcode },
7401     { Bad_Opcode },
7402     { Bad_Opcode },
7403     /* 28 */
7404     { Bad_Opcode },
7405     { Bad_Opcode },
7406     { Bad_Opcode },
7407     { Bad_Opcode },
7408     { Bad_Opcode },
7409     { Bad_Opcode },
7410     { Bad_Opcode },
7411     { Bad_Opcode },
7412     /* 30 */
7413     { Bad_Opcode },
7414     { Bad_Opcode },
7415     { Bad_Opcode },
7416     { Bad_Opcode },
7417     { Bad_Opcode },
7418     { Bad_Opcode },
7419     { Bad_Opcode },
7420     { Bad_Opcode },
7421     /* 38 */
7422     { Bad_Opcode },
7423     { Bad_Opcode },
7424     { Bad_Opcode },
7425     { Bad_Opcode },
7426     { Bad_Opcode },
7427     { Bad_Opcode },
7428     { Bad_Opcode },
7429     { Bad_Opcode },
7430     /* 40 */
7431     { PREFIX_TABLE (PREFIX_0F3A40) },
7432     { PREFIX_TABLE (PREFIX_0F3A41) },
7433     { PREFIX_TABLE (PREFIX_0F3A42) },
7434     { Bad_Opcode },
7435     { PREFIX_TABLE (PREFIX_0F3A44) },
7436     { Bad_Opcode },
7437     { Bad_Opcode },
7438     { Bad_Opcode },
7439     /* 48 */
7440     { Bad_Opcode },
7441     { Bad_Opcode },
7442     { Bad_Opcode },
7443     { Bad_Opcode },
7444     { Bad_Opcode },
7445     { Bad_Opcode },
7446     { Bad_Opcode },
7447     { Bad_Opcode },
7448     /* 50 */
7449     { Bad_Opcode },
7450     { Bad_Opcode },
7451     { Bad_Opcode },
7452     { Bad_Opcode },
7453     { Bad_Opcode },
7454     { Bad_Opcode },
7455     { Bad_Opcode },
7456     { Bad_Opcode },
7457     /* 58 */
7458     { Bad_Opcode },
7459     { Bad_Opcode },
7460     { Bad_Opcode },
7461     { Bad_Opcode },
7462     { Bad_Opcode },
7463     { Bad_Opcode },
7464     { Bad_Opcode },
7465     { Bad_Opcode },
7466     /* 60 */
7467     { PREFIX_TABLE (PREFIX_0F3A60) },
7468     { PREFIX_TABLE (PREFIX_0F3A61) },
7469     { PREFIX_TABLE (PREFIX_0F3A62) },
7470     { PREFIX_TABLE (PREFIX_0F3A63) },
7471     { Bad_Opcode },
7472     { Bad_Opcode },
7473     { Bad_Opcode },
7474     { Bad_Opcode },
7475     /* 68 */
7476     { Bad_Opcode },
7477     { Bad_Opcode },
7478     { Bad_Opcode },
7479     { Bad_Opcode },
7480     { Bad_Opcode },
7481     { Bad_Opcode },
7482     { Bad_Opcode },
7483     { Bad_Opcode },
7484     /* 70 */
7485     { Bad_Opcode },
7486     { Bad_Opcode },
7487     { Bad_Opcode },
7488     { Bad_Opcode },
7489     { Bad_Opcode },
7490     { Bad_Opcode },
7491     { Bad_Opcode },
7492     { Bad_Opcode },
7493     /* 78 */
7494     { Bad_Opcode },
7495     { Bad_Opcode },
7496     { Bad_Opcode },
7497     { Bad_Opcode },
7498     { Bad_Opcode },
7499     { Bad_Opcode },
7500     { Bad_Opcode },
7501     { Bad_Opcode },
7502     /* 80 */
7503     { Bad_Opcode },
7504     { Bad_Opcode },
7505     { Bad_Opcode },
7506     { Bad_Opcode },
7507     { Bad_Opcode },
7508     { Bad_Opcode },
7509     { Bad_Opcode },
7510     { Bad_Opcode },
7511     /* 88 */
7512     { Bad_Opcode },
7513     { Bad_Opcode },
7514     { Bad_Opcode },
7515     { Bad_Opcode },
7516     { Bad_Opcode },
7517     { Bad_Opcode },
7518     { Bad_Opcode },
7519     { Bad_Opcode },
7520     /* 90 */
7521     { Bad_Opcode },
7522     { Bad_Opcode },
7523     { Bad_Opcode },
7524     { Bad_Opcode },
7525     { Bad_Opcode },
7526     { Bad_Opcode },
7527     { Bad_Opcode },
7528     { Bad_Opcode },
7529     /* 98 */
7530     { Bad_Opcode },
7531     { Bad_Opcode },
7532     { Bad_Opcode },
7533     { Bad_Opcode },
7534     { Bad_Opcode },
7535     { Bad_Opcode },
7536     { Bad_Opcode },
7537     { Bad_Opcode },
7538     /* a0 */
7539     { Bad_Opcode },
7540     { Bad_Opcode },
7541     { Bad_Opcode },
7542     { Bad_Opcode },
7543     { Bad_Opcode },
7544     { Bad_Opcode },
7545     { Bad_Opcode },
7546     { Bad_Opcode },
7547     /* a8 */
7548     { Bad_Opcode },
7549     { Bad_Opcode },
7550     { Bad_Opcode },
7551     { Bad_Opcode },
7552     { Bad_Opcode },
7553     { Bad_Opcode },
7554     { Bad_Opcode },
7555     { Bad_Opcode },
7556     /* b0 */
7557     { Bad_Opcode },
7558     { Bad_Opcode },
7559     { Bad_Opcode },
7560     { Bad_Opcode },
7561     { Bad_Opcode },
7562     { Bad_Opcode },
7563     { Bad_Opcode },
7564     { Bad_Opcode },
7565     /* b8 */
7566     { Bad_Opcode },
7567     { Bad_Opcode },
7568     { Bad_Opcode },
7569     { Bad_Opcode },
7570     { Bad_Opcode },
7571     { Bad_Opcode },
7572     { Bad_Opcode },
7573     { Bad_Opcode },
7574     /* c0 */
7575     { Bad_Opcode },
7576     { Bad_Opcode },
7577     { Bad_Opcode },
7578     { Bad_Opcode },
7579     { Bad_Opcode },
7580     { Bad_Opcode },
7581     { Bad_Opcode },
7582     { Bad_Opcode },
7583     /* c8 */
7584     { Bad_Opcode },
7585     { Bad_Opcode },
7586     { Bad_Opcode },
7587     { Bad_Opcode },
7588     { PREFIX_TABLE (PREFIX_0F3ACC) },
7589     { Bad_Opcode },
7590     { Bad_Opcode },
7591     { Bad_Opcode },
7592     /* d0 */
7593     { Bad_Opcode },
7594     { Bad_Opcode },
7595     { Bad_Opcode },
7596     { Bad_Opcode },
7597     { Bad_Opcode },
7598     { Bad_Opcode },
7599     { Bad_Opcode },
7600     { Bad_Opcode },
7601     /* d8 */
7602     { Bad_Opcode },
7603     { Bad_Opcode },
7604     { Bad_Opcode },
7605     { Bad_Opcode },
7606     { Bad_Opcode },
7607     { Bad_Opcode },
7608     { Bad_Opcode },
7609     { PREFIX_TABLE (PREFIX_0F3ADF) },
7610     /* e0 */
7611     { Bad_Opcode },
7612     { Bad_Opcode },
7613     { Bad_Opcode },
7614     { Bad_Opcode },
7615     { Bad_Opcode },
7616     { Bad_Opcode },
7617     { Bad_Opcode },
7618     { Bad_Opcode },
7619     /* e8 */
7620     { Bad_Opcode },
7621     { Bad_Opcode },
7622     { Bad_Opcode },
7623     { Bad_Opcode },
7624     { Bad_Opcode },
7625     { Bad_Opcode },
7626     { Bad_Opcode },
7627     { Bad_Opcode },
7628     /* f0 */
7629     { Bad_Opcode },
7630     { Bad_Opcode },
7631     { Bad_Opcode },
7632     { Bad_Opcode },
7633     { Bad_Opcode },
7634     { Bad_Opcode },
7635     { Bad_Opcode },
7636     { Bad_Opcode },
7637     /* f8 */
7638     { Bad_Opcode },
7639     { Bad_Opcode },
7640     { Bad_Opcode },
7641     { Bad_Opcode },
7642     { Bad_Opcode },
7643     { Bad_Opcode },
7644     { Bad_Opcode },
7645     { Bad_Opcode },
7646   },
7647 };
7648
7649 static const struct dis386 xop_table[][256] = {
7650   /* XOP_08 */
7651   {
7652     /* 00 */
7653     { Bad_Opcode },
7654     { Bad_Opcode },
7655     { Bad_Opcode },
7656     { Bad_Opcode },
7657     { Bad_Opcode },
7658     { Bad_Opcode },
7659     { Bad_Opcode },
7660     { Bad_Opcode },
7661     /* 08 */
7662     { Bad_Opcode },
7663     { Bad_Opcode },
7664     { Bad_Opcode },
7665     { Bad_Opcode },
7666     { Bad_Opcode },
7667     { Bad_Opcode },
7668     { Bad_Opcode },
7669     { Bad_Opcode },
7670     /* 10 */
7671     { Bad_Opcode },
7672     { Bad_Opcode },
7673     { Bad_Opcode },
7674     { Bad_Opcode },
7675     { Bad_Opcode },
7676     { Bad_Opcode },
7677     { Bad_Opcode },
7678     { Bad_Opcode },
7679     /* 18 */
7680     { Bad_Opcode },
7681     { Bad_Opcode },
7682     { Bad_Opcode },
7683     { Bad_Opcode },
7684     { Bad_Opcode },
7685     { Bad_Opcode },
7686     { Bad_Opcode },
7687     { Bad_Opcode },
7688     /* 20 */
7689     { Bad_Opcode },
7690     { Bad_Opcode },
7691     { Bad_Opcode },
7692     { Bad_Opcode },
7693     { Bad_Opcode },
7694     { Bad_Opcode },
7695     { Bad_Opcode },
7696     { Bad_Opcode },
7697     /* 28 */
7698     { Bad_Opcode },
7699     { Bad_Opcode },
7700     { Bad_Opcode },
7701     { Bad_Opcode },
7702     { Bad_Opcode },
7703     { Bad_Opcode },
7704     { Bad_Opcode },
7705     { Bad_Opcode },
7706     /* 30 */
7707     { Bad_Opcode },
7708     { Bad_Opcode },
7709     { Bad_Opcode },
7710     { Bad_Opcode },
7711     { Bad_Opcode },
7712     { Bad_Opcode },
7713     { Bad_Opcode },
7714     { Bad_Opcode },
7715     /* 38 */
7716     { Bad_Opcode },
7717     { Bad_Opcode },
7718     { Bad_Opcode },
7719     { Bad_Opcode },
7720     { Bad_Opcode },
7721     { Bad_Opcode },
7722     { Bad_Opcode },
7723     { Bad_Opcode },
7724     /* 40 */
7725     { Bad_Opcode },
7726     { Bad_Opcode },
7727     { Bad_Opcode },
7728     { Bad_Opcode },
7729     { Bad_Opcode },
7730     { Bad_Opcode },
7731     { Bad_Opcode },
7732     { Bad_Opcode },
7733     /* 48 */
7734     { Bad_Opcode },
7735     { Bad_Opcode },
7736     { Bad_Opcode },
7737     { Bad_Opcode },
7738     { Bad_Opcode },
7739     { Bad_Opcode },
7740     { Bad_Opcode },
7741     { Bad_Opcode },
7742     /* 50 */
7743     { Bad_Opcode },
7744     { Bad_Opcode },
7745     { Bad_Opcode },
7746     { Bad_Opcode },
7747     { Bad_Opcode },
7748     { Bad_Opcode },
7749     { Bad_Opcode },
7750     { Bad_Opcode },
7751     /* 58 */
7752     { Bad_Opcode },
7753     { Bad_Opcode },
7754     { Bad_Opcode },
7755     { Bad_Opcode },
7756     { Bad_Opcode },
7757     { Bad_Opcode },
7758     { Bad_Opcode },
7759     { Bad_Opcode },
7760     /* 60 */
7761     { Bad_Opcode },
7762     { Bad_Opcode },
7763     { Bad_Opcode },
7764     { Bad_Opcode },
7765     { Bad_Opcode },
7766     { Bad_Opcode },
7767     { Bad_Opcode },
7768     { Bad_Opcode },
7769     /* 68 */
7770     { Bad_Opcode },
7771     { Bad_Opcode },
7772     { Bad_Opcode },
7773     { Bad_Opcode },
7774     { Bad_Opcode },
7775     { Bad_Opcode },
7776     { Bad_Opcode },
7777     { Bad_Opcode },
7778     /* 70 */
7779     { Bad_Opcode },
7780     { Bad_Opcode },
7781     { Bad_Opcode },
7782     { Bad_Opcode },
7783     { Bad_Opcode },
7784     { Bad_Opcode },
7785     { Bad_Opcode },
7786     { Bad_Opcode },
7787     /* 78 */
7788     { Bad_Opcode },
7789     { Bad_Opcode },
7790     { Bad_Opcode },
7791     { Bad_Opcode },
7792     { Bad_Opcode },
7793     { Bad_Opcode },
7794     { Bad_Opcode },
7795     { Bad_Opcode },
7796     /* 80 */
7797     { Bad_Opcode },
7798     { Bad_Opcode },
7799     { Bad_Opcode },
7800     { Bad_Opcode },
7801     { Bad_Opcode },
7802     { "vpmacssww",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7803     { "vpmacsswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7804     { "vpmacssdql",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7805     /* 88 */
7806     { Bad_Opcode },
7807     { Bad_Opcode },
7808     { Bad_Opcode },
7809     { Bad_Opcode },
7810     { Bad_Opcode },
7811     { Bad_Opcode },
7812     { "vpmacssdd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7813     { "vpmacssdqh",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7814     /* 90 */
7815     { Bad_Opcode },
7816     { Bad_Opcode },
7817     { Bad_Opcode },
7818     { Bad_Opcode },
7819     { Bad_Opcode },
7820     { "vpmacsww",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7821     { "vpmacswd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7822     { "vpmacsdql",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7823     /* 98 */
7824     { Bad_Opcode },
7825     { Bad_Opcode },
7826     { Bad_Opcode },
7827     { Bad_Opcode },
7828     { Bad_Opcode },
7829     { Bad_Opcode },
7830     { "vpmacsdd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7831     { "vpmacsdqh",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7832     /* a0 */
7833     { Bad_Opcode },
7834     { Bad_Opcode },
7835     { "vpcmov",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7836     { "vpperm",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7837     { Bad_Opcode },
7838     { Bad_Opcode },
7839     { "vpmadcsswd",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7840     { Bad_Opcode },
7841     /* a8 */
7842     { Bad_Opcode },
7843     { Bad_Opcode },
7844     { Bad_Opcode },
7845     { Bad_Opcode },
7846     { Bad_Opcode },
7847     { Bad_Opcode },
7848     { Bad_Opcode },
7849     { Bad_Opcode },
7850     /* b0 */
7851     { Bad_Opcode },
7852     { Bad_Opcode },
7853     { Bad_Opcode },
7854     { Bad_Opcode },
7855     { Bad_Opcode },
7856     { Bad_Opcode },
7857     { "vpmadcswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7858     { Bad_Opcode },
7859     /* b8 */
7860     { Bad_Opcode },
7861     { Bad_Opcode },
7862     { Bad_Opcode },
7863     { Bad_Opcode },
7864     { Bad_Opcode },
7865     { Bad_Opcode },
7866     { Bad_Opcode },
7867     { Bad_Opcode },
7868     /* c0 */
7869     { "vprotb",         { XM, Vex_2src_1, Ib }, 0 },
7870     { "vprotw",         { XM, Vex_2src_1, Ib }, 0 },
7871     { "vprotd",         { XM, Vex_2src_1, Ib }, 0 },
7872     { "vprotq",         { XM, Vex_2src_1, Ib }, 0 },
7873     { Bad_Opcode },
7874     { Bad_Opcode },
7875     { Bad_Opcode },
7876     { Bad_Opcode },
7877     /* c8 */
7878     { Bad_Opcode },
7879     { Bad_Opcode },
7880     { Bad_Opcode },
7881     { Bad_Opcode },
7882     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
7883     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
7884     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
7885     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
7886     /* d0 */
7887     { Bad_Opcode },
7888     { Bad_Opcode },
7889     { Bad_Opcode },
7890     { Bad_Opcode },
7891     { Bad_Opcode },
7892     { Bad_Opcode },
7893     { Bad_Opcode },
7894     { Bad_Opcode },
7895     /* d8 */
7896     { Bad_Opcode },
7897     { Bad_Opcode },
7898     { Bad_Opcode },
7899     { Bad_Opcode },
7900     { Bad_Opcode },
7901     { Bad_Opcode },
7902     { Bad_Opcode },
7903     { Bad_Opcode },
7904     /* e0 */
7905     { Bad_Opcode },
7906     { Bad_Opcode },
7907     { Bad_Opcode },
7908     { Bad_Opcode },
7909     { Bad_Opcode },
7910     { Bad_Opcode },
7911     { Bad_Opcode },
7912     { Bad_Opcode },
7913     /* e8 */
7914     { Bad_Opcode },
7915     { Bad_Opcode },
7916     { Bad_Opcode },
7917     { Bad_Opcode },
7918     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
7919     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
7920     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
7921     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
7922     /* f0 */
7923     { Bad_Opcode },
7924     { Bad_Opcode },
7925     { Bad_Opcode },
7926     { Bad_Opcode },
7927     { Bad_Opcode },
7928     { Bad_Opcode },
7929     { Bad_Opcode },
7930     { Bad_Opcode },
7931     /* f8 */
7932     { Bad_Opcode },
7933     { Bad_Opcode },
7934     { Bad_Opcode },
7935     { Bad_Opcode },
7936     { Bad_Opcode },
7937     { Bad_Opcode },
7938     { Bad_Opcode },
7939     { Bad_Opcode },
7940   },
7941   /* XOP_09 */
7942   {
7943     /* 00 */
7944     { Bad_Opcode },
7945     { REG_TABLE (REG_XOP_TBM_01) },
7946     { REG_TABLE (REG_XOP_TBM_02) },
7947     { Bad_Opcode },
7948     { Bad_Opcode },
7949     { Bad_Opcode },
7950     { Bad_Opcode },
7951     { Bad_Opcode },
7952     /* 08 */
7953     { Bad_Opcode },
7954     { Bad_Opcode },
7955     { Bad_Opcode },
7956     { Bad_Opcode },
7957     { Bad_Opcode },
7958     { Bad_Opcode },
7959     { Bad_Opcode },
7960     { Bad_Opcode },
7961     /* 10 */
7962     { Bad_Opcode },
7963     { Bad_Opcode },
7964     { REG_TABLE (REG_XOP_LWPCB) },
7965     { Bad_Opcode },
7966     { Bad_Opcode },
7967     { Bad_Opcode },
7968     { Bad_Opcode },
7969     { Bad_Opcode },
7970     /* 18 */
7971     { Bad_Opcode },
7972     { Bad_Opcode },
7973     { Bad_Opcode },
7974     { Bad_Opcode },
7975     { Bad_Opcode },
7976     { Bad_Opcode },
7977     { Bad_Opcode },
7978     { Bad_Opcode },
7979     /* 20 */
7980     { Bad_Opcode },
7981     { Bad_Opcode },
7982     { Bad_Opcode },
7983     { Bad_Opcode },
7984     { Bad_Opcode },
7985     { Bad_Opcode },
7986     { Bad_Opcode },
7987     { Bad_Opcode },
7988     /* 28 */
7989     { Bad_Opcode },
7990     { Bad_Opcode },
7991     { Bad_Opcode },
7992     { Bad_Opcode },
7993     { Bad_Opcode },
7994     { Bad_Opcode },
7995     { Bad_Opcode },
7996     { Bad_Opcode },
7997     /* 30 */
7998     { Bad_Opcode },
7999     { Bad_Opcode },
8000     { Bad_Opcode },
8001     { Bad_Opcode },
8002     { Bad_Opcode },
8003     { Bad_Opcode },
8004     { Bad_Opcode },
8005     { Bad_Opcode },
8006     /* 38 */
8007     { Bad_Opcode },
8008     { Bad_Opcode },
8009     { Bad_Opcode },
8010     { Bad_Opcode },
8011     { Bad_Opcode },
8012     { Bad_Opcode },
8013     { Bad_Opcode },
8014     { Bad_Opcode },
8015     /* 40 */
8016     { Bad_Opcode },
8017     { Bad_Opcode },
8018     { Bad_Opcode },
8019     { Bad_Opcode },
8020     { Bad_Opcode },
8021     { Bad_Opcode },
8022     { Bad_Opcode },
8023     { Bad_Opcode },
8024     /* 48 */
8025     { Bad_Opcode },
8026     { Bad_Opcode },
8027     { Bad_Opcode },
8028     { Bad_Opcode },
8029     { Bad_Opcode },
8030     { Bad_Opcode },
8031     { Bad_Opcode },
8032     { Bad_Opcode },
8033     /* 50 */
8034     { Bad_Opcode },
8035     { Bad_Opcode },
8036     { Bad_Opcode },
8037     { Bad_Opcode },
8038     { Bad_Opcode },
8039     { Bad_Opcode },
8040     { Bad_Opcode },
8041     { Bad_Opcode },
8042     /* 58 */
8043     { Bad_Opcode },
8044     { Bad_Opcode },
8045     { Bad_Opcode },
8046     { Bad_Opcode },
8047     { Bad_Opcode },
8048     { Bad_Opcode },
8049     { Bad_Opcode },
8050     { Bad_Opcode },
8051     /* 60 */
8052     { Bad_Opcode },
8053     { Bad_Opcode },
8054     { Bad_Opcode },
8055     { Bad_Opcode },
8056     { Bad_Opcode },
8057     { Bad_Opcode },
8058     { Bad_Opcode },
8059     { Bad_Opcode },
8060     /* 68 */
8061     { Bad_Opcode },
8062     { Bad_Opcode },
8063     { Bad_Opcode },
8064     { Bad_Opcode },
8065     { Bad_Opcode },
8066     { Bad_Opcode },
8067     { Bad_Opcode },
8068     { Bad_Opcode },
8069     /* 70 */
8070     { Bad_Opcode },
8071     { Bad_Opcode },
8072     { Bad_Opcode },
8073     { Bad_Opcode },
8074     { Bad_Opcode },
8075     { Bad_Opcode },
8076     { Bad_Opcode },
8077     { Bad_Opcode },
8078     /* 78 */
8079     { Bad_Opcode },
8080     { Bad_Opcode },
8081     { Bad_Opcode },
8082     { Bad_Opcode },
8083     { Bad_Opcode },
8084     { Bad_Opcode },
8085     { Bad_Opcode },
8086     { Bad_Opcode },
8087     /* 80 */
8088     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
8089     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
8090     { "vfrczss",        { XM, EXd }, 0 },
8091     { "vfrczsd",        { XM, EXq }, 0 },
8092     { Bad_Opcode },
8093     { Bad_Opcode },
8094     { Bad_Opcode },
8095     { Bad_Opcode },
8096     /* 88 */
8097     { Bad_Opcode },
8098     { Bad_Opcode },
8099     { Bad_Opcode },
8100     { Bad_Opcode },
8101     { Bad_Opcode },
8102     { Bad_Opcode },
8103     { Bad_Opcode },
8104     { Bad_Opcode },
8105     /* 90 */
8106     { "vprotb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8107     { "vprotw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8108     { "vprotd",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8109     { "vprotq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8110     { "vpshlb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8111     { "vpshlw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8112     { "vpshld",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8113     { "vpshlq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8114     /* 98 */
8115     { "vpshab",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8116     { "vpshaw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8117     { "vpshad",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8118     { "vpshaq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8119     { Bad_Opcode },
8120     { Bad_Opcode },
8121     { Bad_Opcode },
8122     { Bad_Opcode },
8123     /* a0 */
8124     { Bad_Opcode },
8125     { Bad_Opcode },
8126     { Bad_Opcode },
8127     { Bad_Opcode },
8128     { Bad_Opcode },
8129     { Bad_Opcode },
8130     { Bad_Opcode },
8131     { Bad_Opcode },
8132     /* a8 */
8133     { Bad_Opcode },
8134     { Bad_Opcode },
8135     { Bad_Opcode },
8136     { Bad_Opcode },
8137     { Bad_Opcode },
8138     { Bad_Opcode },
8139     { Bad_Opcode },
8140     { Bad_Opcode },
8141     /* b0 */
8142     { Bad_Opcode },
8143     { Bad_Opcode },
8144     { Bad_Opcode },
8145     { Bad_Opcode },
8146     { Bad_Opcode },
8147     { Bad_Opcode },
8148     { Bad_Opcode },
8149     { Bad_Opcode },
8150     /* b8 */
8151     { Bad_Opcode },
8152     { Bad_Opcode },
8153     { Bad_Opcode },
8154     { Bad_Opcode },
8155     { Bad_Opcode },
8156     { Bad_Opcode },
8157     { Bad_Opcode },
8158     { Bad_Opcode },
8159     /* c0 */
8160     { Bad_Opcode },
8161     { "vphaddbw",       { XM, EXxmm }, 0 },
8162     { "vphaddbd",       { XM, EXxmm }, 0 },
8163     { "vphaddbq",       { XM, EXxmm }, 0 },
8164     { Bad_Opcode },
8165     { Bad_Opcode },
8166     { "vphaddwd",       { XM, EXxmm }, 0 },
8167     { "vphaddwq",       { XM, EXxmm }, 0 },
8168     /* c8 */
8169     { Bad_Opcode },
8170     { Bad_Opcode },
8171     { Bad_Opcode },
8172     { "vphadddq",       { XM, EXxmm }, 0 },
8173     { Bad_Opcode },
8174     { Bad_Opcode },
8175     { Bad_Opcode },
8176     { Bad_Opcode },
8177     /* d0 */
8178     { Bad_Opcode },
8179     { "vphaddubw",      { XM, EXxmm }, 0 },
8180     { "vphaddubd",      { XM, EXxmm }, 0 },
8181     { "vphaddubq",      { XM, EXxmm }, 0 },
8182     { Bad_Opcode },
8183     { Bad_Opcode },
8184     { "vphadduwd",      { XM, EXxmm }, 0 },
8185     { "vphadduwq",      { XM, EXxmm }, 0 },
8186     /* d8 */
8187     { Bad_Opcode },
8188     { Bad_Opcode },
8189     { Bad_Opcode },
8190     { "vphaddudq",      { XM, EXxmm }, 0 },
8191     { Bad_Opcode },
8192     { Bad_Opcode },
8193     { Bad_Opcode },
8194     { Bad_Opcode },
8195     /* e0 */
8196     { Bad_Opcode },
8197     { "vphsubbw",       { XM, EXxmm }, 0 },
8198     { "vphsubwd",       { XM, EXxmm }, 0 },
8199     { "vphsubdq",       { XM, EXxmm }, 0 },
8200     { Bad_Opcode },
8201     { Bad_Opcode },
8202     { Bad_Opcode },
8203     { Bad_Opcode },
8204     /* e8 */
8205     { Bad_Opcode },
8206     { Bad_Opcode },
8207     { Bad_Opcode },
8208     { Bad_Opcode },
8209     { Bad_Opcode },
8210     { Bad_Opcode },
8211     { Bad_Opcode },
8212     { Bad_Opcode },
8213     /* f0 */
8214     { Bad_Opcode },
8215     { Bad_Opcode },
8216     { Bad_Opcode },
8217     { Bad_Opcode },
8218     { Bad_Opcode },
8219     { Bad_Opcode },
8220     { Bad_Opcode },
8221     { Bad_Opcode },
8222     /* f8 */
8223     { Bad_Opcode },
8224     { Bad_Opcode },
8225     { Bad_Opcode },
8226     { Bad_Opcode },
8227     { Bad_Opcode },
8228     { Bad_Opcode },
8229     { Bad_Opcode },
8230     { Bad_Opcode },
8231   },
8232   /* XOP_0A */
8233   {
8234     /* 00 */
8235     { Bad_Opcode },
8236     { Bad_Opcode },
8237     { Bad_Opcode },
8238     { Bad_Opcode },
8239     { Bad_Opcode },
8240     { Bad_Opcode },
8241     { Bad_Opcode },
8242     { Bad_Opcode },
8243     /* 08 */
8244     { Bad_Opcode },
8245     { Bad_Opcode },
8246     { Bad_Opcode },
8247     { Bad_Opcode },
8248     { Bad_Opcode },
8249     { Bad_Opcode },
8250     { Bad_Opcode },
8251     { Bad_Opcode },
8252     /* 10 */
8253     { "bextr",  { Gv, Ev, Iq }, 0 },
8254     { Bad_Opcode },
8255     { REG_TABLE (REG_XOP_LWP) },
8256     { Bad_Opcode },
8257     { Bad_Opcode },
8258     { Bad_Opcode },
8259     { Bad_Opcode },
8260     { Bad_Opcode },
8261     /* 18 */
8262     { Bad_Opcode },
8263     { Bad_Opcode },
8264     { Bad_Opcode },
8265     { Bad_Opcode },
8266     { Bad_Opcode },
8267     { Bad_Opcode },
8268     { Bad_Opcode },
8269     { Bad_Opcode },
8270     /* 20 */
8271     { Bad_Opcode },
8272     { Bad_Opcode },
8273     { Bad_Opcode },
8274     { Bad_Opcode },
8275     { Bad_Opcode },
8276     { Bad_Opcode },
8277     { Bad_Opcode },
8278     { Bad_Opcode },
8279     /* 28 */
8280     { Bad_Opcode },
8281     { Bad_Opcode },
8282     { Bad_Opcode },
8283     { Bad_Opcode },
8284     { Bad_Opcode },
8285     { Bad_Opcode },
8286     { Bad_Opcode },
8287     { Bad_Opcode },
8288     /* 30 */
8289     { Bad_Opcode },
8290     { Bad_Opcode },
8291     { Bad_Opcode },
8292     { Bad_Opcode },
8293     { Bad_Opcode },
8294     { Bad_Opcode },
8295     { Bad_Opcode },
8296     { Bad_Opcode },
8297     /* 38 */
8298     { Bad_Opcode },
8299     { Bad_Opcode },
8300     { Bad_Opcode },
8301     { Bad_Opcode },
8302     { Bad_Opcode },
8303     { Bad_Opcode },
8304     { Bad_Opcode },
8305     { Bad_Opcode },
8306     /* 40 */
8307     { Bad_Opcode },
8308     { Bad_Opcode },
8309     { Bad_Opcode },
8310     { Bad_Opcode },
8311     { Bad_Opcode },
8312     { Bad_Opcode },
8313     { Bad_Opcode },
8314     { Bad_Opcode },
8315     /* 48 */
8316     { Bad_Opcode },
8317     { Bad_Opcode },
8318     { Bad_Opcode },
8319     { Bad_Opcode },
8320     { Bad_Opcode },
8321     { Bad_Opcode },
8322     { Bad_Opcode },
8323     { Bad_Opcode },
8324     /* 50 */
8325     { Bad_Opcode },
8326     { Bad_Opcode },
8327     { Bad_Opcode },
8328     { Bad_Opcode },
8329     { Bad_Opcode },
8330     { Bad_Opcode },
8331     { Bad_Opcode },
8332     { Bad_Opcode },
8333     /* 58 */
8334     { Bad_Opcode },
8335     { Bad_Opcode },
8336     { Bad_Opcode },
8337     { Bad_Opcode },
8338     { Bad_Opcode },
8339     { Bad_Opcode },
8340     { Bad_Opcode },
8341     { Bad_Opcode },
8342     /* 60 */
8343     { Bad_Opcode },
8344     { Bad_Opcode },
8345     { Bad_Opcode },
8346     { Bad_Opcode },
8347     { Bad_Opcode },
8348     { Bad_Opcode },
8349     { Bad_Opcode },
8350     { Bad_Opcode },
8351     /* 68 */
8352     { Bad_Opcode },
8353     { Bad_Opcode },
8354     { Bad_Opcode },
8355     { Bad_Opcode },
8356     { Bad_Opcode },
8357     { Bad_Opcode },
8358     { Bad_Opcode },
8359     { Bad_Opcode },
8360     /* 70 */
8361     { Bad_Opcode },
8362     { Bad_Opcode },
8363     { Bad_Opcode },
8364     { Bad_Opcode },
8365     { Bad_Opcode },
8366     { Bad_Opcode },
8367     { Bad_Opcode },
8368     { Bad_Opcode },
8369     /* 78 */
8370     { Bad_Opcode },
8371     { Bad_Opcode },
8372     { Bad_Opcode },
8373     { Bad_Opcode },
8374     { Bad_Opcode },
8375     { Bad_Opcode },
8376     { Bad_Opcode },
8377     { Bad_Opcode },
8378     /* 80 */
8379     { Bad_Opcode },
8380     { Bad_Opcode },
8381     { Bad_Opcode },
8382     { Bad_Opcode },
8383     { Bad_Opcode },
8384     { Bad_Opcode },
8385     { Bad_Opcode },
8386     { Bad_Opcode },
8387     /* 88 */
8388     { Bad_Opcode },
8389     { Bad_Opcode },
8390     { Bad_Opcode },
8391     { Bad_Opcode },
8392     { Bad_Opcode },
8393     { Bad_Opcode },
8394     { Bad_Opcode },
8395     { Bad_Opcode },
8396     /* 90 */
8397     { Bad_Opcode },
8398     { Bad_Opcode },
8399     { Bad_Opcode },
8400     { Bad_Opcode },
8401     { Bad_Opcode },
8402     { Bad_Opcode },
8403     { Bad_Opcode },
8404     { Bad_Opcode },
8405     /* 98 */
8406     { Bad_Opcode },
8407     { Bad_Opcode },
8408     { Bad_Opcode },
8409     { Bad_Opcode },
8410     { Bad_Opcode },
8411     { Bad_Opcode },
8412     { Bad_Opcode },
8413     { Bad_Opcode },
8414     /* a0 */
8415     { Bad_Opcode },
8416     { Bad_Opcode },
8417     { Bad_Opcode },
8418     { Bad_Opcode },
8419     { Bad_Opcode },
8420     { Bad_Opcode },
8421     { Bad_Opcode },
8422     { Bad_Opcode },
8423     /* a8 */
8424     { Bad_Opcode },
8425     { Bad_Opcode },
8426     { Bad_Opcode },
8427     { Bad_Opcode },
8428     { Bad_Opcode },
8429     { Bad_Opcode },
8430     { Bad_Opcode },
8431     { Bad_Opcode },
8432     /* b0 */
8433     { Bad_Opcode },
8434     { Bad_Opcode },
8435     { Bad_Opcode },
8436     { Bad_Opcode },
8437     { Bad_Opcode },
8438     { Bad_Opcode },
8439     { Bad_Opcode },
8440     { Bad_Opcode },
8441     /* b8 */
8442     { Bad_Opcode },
8443     { Bad_Opcode },
8444     { Bad_Opcode },
8445     { Bad_Opcode },
8446     { Bad_Opcode },
8447     { Bad_Opcode },
8448     { Bad_Opcode },
8449     { Bad_Opcode },
8450     /* c0 */
8451     { Bad_Opcode },
8452     { Bad_Opcode },
8453     { Bad_Opcode },
8454     { Bad_Opcode },
8455     { Bad_Opcode },
8456     { Bad_Opcode },
8457     { Bad_Opcode },
8458     { Bad_Opcode },
8459     /* c8 */
8460     { Bad_Opcode },
8461     { Bad_Opcode },
8462     { Bad_Opcode },
8463     { Bad_Opcode },
8464     { Bad_Opcode },
8465     { Bad_Opcode },
8466     { Bad_Opcode },
8467     { Bad_Opcode },
8468     /* d0 */
8469     { Bad_Opcode },
8470     { Bad_Opcode },
8471     { Bad_Opcode },
8472     { Bad_Opcode },
8473     { Bad_Opcode },
8474     { Bad_Opcode },
8475     { Bad_Opcode },
8476     { Bad_Opcode },
8477     /* d8 */
8478     { Bad_Opcode },
8479     { Bad_Opcode },
8480     { Bad_Opcode },
8481     { Bad_Opcode },
8482     { Bad_Opcode },
8483     { Bad_Opcode },
8484     { Bad_Opcode },
8485     { Bad_Opcode },
8486     /* e0 */
8487     { Bad_Opcode },
8488     { Bad_Opcode },
8489     { Bad_Opcode },
8490     { Bad_Opcode },
8491     { Bad_Opcode },
8492     { Bad_Opcode },
8493     { Bad_Opcode },
8494     { Bad_Opcode },
8495     /* e8 */
8496     { Bad_Opcode },
8497     { Bad_Opcode },
8498     { Bad_Opcode },
8499     { Bad_Opcode },
8500     { Bad_Opcode },
8501     { Bad_Opcode },
8502     { Bad_Opcode },
8503     { Bad_Opcode },
8504     /* f0 */
8505     { Bad_Opcode },
8506     { Bad_Opcode },
8507     { Bad_Opcode },
8508     { Bad_Opcode },
8509     { Bad_Opcode },
8510     { Bad_Opcode },
8511     { Bad_Opcode },
8512     { Bad_Opcode },
8513     /* f8 */
8514     { Bad_Opcode },
8515     { Bad_Opcode },
8516     { Bad_Opcode },
8517     { Bad_Opcode },
8518     { Bad_Opcode },
8519     { Bad_Opcode },
8520     { Bad_Opcode },
8521     { Bad_Opcode },
8522   },
8523 };
8524
8525 static const struct dis386 vex_table[][256] = {
8526   /* VEX_0F */
8527   {
8528     /* 00 */
8529     { Bad_Opcode },
8530     { Bad_Opcode },
8531     { Bad_Opcode },
8532     { Bad_Opcode },
8533     { Bad_Opcode },
8534     { Bad_Opcode },
8535     { Bad_Opcode },
8536     { Bad_Opcode },
8537     /* 08 */
8538     { Bad_Opcode },
8539     { Bad_Opcode },
8540     { Bad_Opcode },
8541     { Bad_Opcode },
8542     { Bad_Opcode },
8543     { Bad_Opcode },
8544     { Bad_Opcode },
8545     { Bad_Opcode },
8546     /* 10 */
8547     { PREFIX_TABLE (PREFIX_VEX_0F10) },
8548     { PREFIX_TABLE (PREFIX_VEX_0F11) },
8549     { PREFIX_TABLE (PREFIX_VEX_0F12) },
8550     { MOD_TABLE (MOD_VEX_0F13) },
8551     { VEX_W_TABLE (VEX_W_0F14) },
8552     { VEX_W_TABLE (VEX_W_0F15) },
8553     { PREFIX_TABLE (PREFIX_VEX_0F16) },
8554     { MOD_TABLE (MOD_VEX_0F17) },
8555     /* 18 */
8556     { Bad_Opcode },
8557     { Bad_Opcode },
8558     { Bad_Opcode },
8559     { Bad_Opcode },
8560     { Bad_Opcode },
8561     { Bad_Opcode },
8562     { Bad_Opcode },
8563     { Bad_Opcode },
8564     /* 20 */
8565     { Bad_Opcode },
8566     { Bad_Opcode },
8567     { Bad_Opcode },
8568     { Bad_Opcode },
8569     { Bad_Opcode },
8570     { Bad_Opcode },
8571     { Bad_Opcode },
8572     { Bad_Opcode },
8573     /* 28 */
8574     { VEX_W_TABLE (VEX_W_0F28) },
8575     { VEX_W_TABLE (VEX_W_0F29) },
8576     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8577     { MOD_TABLE (MOD_VEX_0F2B) },
8578     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8579     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8580     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8581     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8582     /* 30 */
8583     { Bad_Opcode },
8584     { Bad_Opcode },
8585     { Bad_Opcode },
8586     { Bad_Opcode },
8587     { Bad_Opcode },
8588     { Bad_Opcode },
8589     { Bad_Opcode },
8590     { Bad_Opcode },
8591     /* 38 */
8592     { Bad_Opcode },
8593     { Bad_Opcode },
8594     { Bad_Opcode },
8595     { Bad_Opcode },
8596     { Bad_Opcode },
8597     { Bad_Opcode },
8598     { Bad_Opcode },
8599     { Bad_Opcode },
8600     /* 40 */
8601     { Bad_Opcode },
8602     { PREFIX_TABLE (PREFIX_VEX_0F41) },
8603     { PREFIX_TABLE (PREFIX_VEX_0F42) },
8604     { Bad_Opcode },
8605     { PREFIX_TABLE (PREFIX_VEX_0F44) },
8606     { PREFIX_TABLE (PREFIX_VEX_0F45) },
8607     { PREFIX_TABLE (PREFIX_VEX_0F46) },
8608     { PREFIX_TABLE (PREFIX_VEX_0F47) },
8609     /* 48 */
8610     { Bad_Opcode },
8611     { Bad_Opcode },
8612     { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8613     { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8614     { Bad_Opcode },
8615     { Bad_Opcode },
8616     { Bad_Opcode },
8617     { Bad_Opcode },
8618     /* 50 */
8619     { MOD_TABLE (MOD_VEX_0F50) },
8620     { PREFIX_TABLE (PREFIX_VEX_0F51) },
8621     { PREFIX_TABLE (PREFIX_VEX_0F52) },
8622     { PREFIX_TABLE (PREFIX_VEX_0F53) },
8623     { "vandpX",         { XM, Vex, EXx }, 0 },
8624     { "vandnpX",        { XM, Vex, EXx }, 0 },
8625     { "vorpX",          { XM, Vex, EXx }, 0 },
8626     { "vxorpX",         { XM, Vex, EXx }, 0 },
8627     /* 58 */
8628     { PREFIX_TABLE (PREFIX_VEX_0F58) },
8629     { PREFIX_TABLE (PREFIX_VEX_0F59) },
8630     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8631     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8632     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8633     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8634     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8635     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8636     /* 60 */
8637     { PREFIX_TABLE (PREFIX_VEX_0F60) },
8638     { PREFIX_TABLE (PREFIX_VEX_0F61) },
8639     { PREFIX_TABLE (PREFIX_VEX_0F62) },
8640     { PREFIX_TABLE (PREFIX_VEX_0F63) },
8641     { PREFIX_TABLE (PREFIX_VEX_0F64) },
8642     { PREFIX_TABLE (PREFIX_VEX_0F65) },
8643     { PREFIX_TABLE (PREFIX_VEX_0F66) },
8644     { PREFIX_TABLE (PREFIX_VEX_0F67) },
8645     /* 68 */
8646     { PREFIX_TABLE (PREFIX_VEX_0F68) },
8647     { PREFIX_TABLE (PREFIX_VEX_0F69) },
8648     { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8649     { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8650     { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8651     { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8652     { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8653     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8654     /* 70 */
8655     { PREFIX_TABLE (PREFIX_VEX_0F70) },
8656     { REG_TABLE (REG_VEX_0F71) },
8657     { REG_TABLE (REG_VEX_0F72) },
8658     { REG_TABLE (REG_VEX_0F73) },
8659     { PREFIX_TABLE (PREFIX_VEX_0F74) },
8660     { PREFIX_TABLE (PREFIX_VEX_0F75) },
8661     { PREFIX_TABLE (PREFIX_VEX_0F76) },
8662     { PREFIX_TABLE (PREFIX_VEX_0F77) },
8663     /* 78 */
8664     { Bad_Opcode },
8665     { Bad_Opcode },
8666     { Bad_Opcode },
8667     { Bad_Opcode },
8668     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8669     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8670     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8671     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8672     /* 80 */
8673     { Bad_Opcode },
8674     { Bad_Opcode },
8675     { Bad_Opcode },
8676     { Bad_Opcode },
8677     { Bad_Opcode },
8678     { Bad_Opcode },
8679     { Bad_Opcode },
8680     { Bad_Opcode },
8681     /* 88 */
8682     { Bad_Opcode },
8683     { Bad_Opcode },
8684     { Bad_Opcode },
8685     { Bad_Opcode },
8686     { Bad_Opcode },
8687     { Bad_Opcode },
8688     { Bad_Opcode },
8689     { Bad_Opcode },
8690     /* 90 */
8691     { PREFIX_TABLE (PREFIX_VEX_0F90) },
8692     { PREFIX_TABLE (PREFIX_VEX_0F91) },
8693     { PREFIX_TABLE (PREFIX_VEX_0F92) },
8694     { PREFIX_TABLE (PREFIX_VEX_0F93) },
8695     { Bad_Opcode },
8696     { Bad_Opcode },
8697     { Bad_Opcode },
8698     { Bad_Opcode },
8699     /* 98 */
8700     { PREFIX_TABLE (PREFIX_VEX_0F98) },
8701     { PREFIX_TABLE (PREFIX_VEX_0F99) },
8702     { Bad_Opcode },
8703     { Bad_Opcode },
8704     { Bad_Opcode },
8705     { Bad_Opcode },
8706     { Bad_Opcode },
8707     { Bad_Opcode },
8708     /* a0 */
8709     { Bad_Opcode },
8710     { Bad_Opcode },
8711     { Bad_Opcode },
8712     { Bad_Opcode },
8713     { Bad_Opcode },
8714     { Bad_Opcode },
8715     { Bad_Opcode },
8716     { Bad_Opcode },
8717     /* a8 */
8718     { Bad_Opcode },
8719     { Bad_Opcode },
8720     { Bad_Opcode },
8721     { Bad_Opcode },
8722     { Bad_Opcode },
8723     { Bad_Opcode },
8724     { REG_TABLE (REG_VEX_0FAE) },
8725     { Bad_Opcode },
8726     /* b0 */
8727     { Bad_Opcode },
8728     { Bad_Opcode },
8729     { Bad_Opcode },
8730     { Bad_Opcode },
8731     { Bad_Opcode },
8732     { Bad_Opcode },
8733     { Bad_Opcode },
8734     { Bad_Opcode },
8735     /* b8 */
8736     { Bad_Opcode },
8737     { Bad_Opcode },
8738     { Bad_Opcode },
8739     { Bad_Opcode },
8740     { Bad_Opcode },
8741     { Bad_Opcode },
8742     { Bad_Opcode },
8743     { Bad_Opcode },
8744     /* c0 */
8745     { Bad_Opcode },
8746     { Bad_Opcode },
8747     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8748     { Bad_Opcode },
8749     { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8750     { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8751     { "vshufpX",        { XM, Vex, EXx, Ib }, 0 },
8752     { Bad_Opcode },
8753     /* c8 */
8754     { Bad_Opcode },
8755     { Bad_Opcode },
8756     { Bad_Opcode },
8757     { Bad_Opcode },
8758     { Bad_Opcode },
8759     { Bad_Opcode },
8760     { Bad_Opcode },
8761     { Bad_Opcode },
8762     /* d0 */
8763     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8764     { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8765     { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8766     { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8767     { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8768     { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8769     { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8770     { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8771     /* d8 */
8772     { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8773     { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8774     { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8775     { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8776     { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8777     { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8778     { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8779     { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8780     /* e0 */
8781     { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8782     { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8783     { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8784     { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8785     { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8786     { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8787     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8788     { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8789     /* e8 */
8790     { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8791     { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8792     { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8793     { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8794     { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8795     { PREFIX_TABLE (PREFIX_VEX_0FED) },
8796     { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8797     { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8798     /* f0 */
8799     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8800     { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8801     { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8802     { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8803     { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8804     { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8805     { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8806     { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8807     /* f8 */
8808     { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8809     { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8810     { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8811     { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8812     { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8813     { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8814     { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8815     { Bad_Opcode },
8816   },
8817   /* VEX_0F38 */
8818   {
8819     /* 00 */
8820     { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8821     { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8822     { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8823     { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8824     { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8825     { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8826     { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8827     { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8828     /* 08 */
8829     { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8830     { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8831     { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8832     { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8833     { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8834     { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8835     { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8836     { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8837     /* 10 */
8838     { Bad_Opcode },
8839     { Bad_Opcode },
8840     { Bad_Opcode },
8841     { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8842     { Bad_Opcode },
8843     { Bad_Opcode },
8844     { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8845     { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8846     /* 18 */
8847     { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8848     { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8849     { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8850     { Bad_Opcode },
8851     { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8852     { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8853     { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8854     { Bad_Opcode },
8855     /* 20 */
8856     { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8857     { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8858     { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8859     { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8860     { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8861     { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8862     { Bad_Opcode },
8863     { Bad_Opcode },
8864     /* 28 */
8865     { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8866     { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8867     { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8868     { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8869     { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8870     { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8871     { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8872     { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8873     /* 30 */
8874     { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8875     { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8876     { PREFIX_TABLE (PREFIX_VEX_0F3832) },
8877     { PREFIX_TABLE (PREFIX_VEX_0F3833) },
8878     { PREFIX_TABLE (PREFIX_VEX_0F3834) },
8879     { PREFIX_TABLE (PREFIX_VEX_0F3835) },
8880     { PREFIX_TABLE (PREFIX_VEX_0F3836) },
8881     { PREFIX_TABLE (PREFIX_VEX_0F3837) },
8882     /* 38 */
8883     { PREFIX_TABLE (PREFIX_VEX_0F3838) },
8884     { PREFIX_TABLE (PREFIX_VEX_0F3839) },
8885     { PREFIX_TABLE (PREFIX_VEX_0F383A) },
8886     { PREFIX_TABLE (PREFIX_VEX_0F383B) },
8887     { PREFIX_TABLE (PREFIX_VEX_0F383C) },
8888     { PREFIX_TABLE (PREFIX_VEX_0F383D) },
8889     { PREFIX_TABLE (PREFIX_VEX_0F383E) },
8890     { PREFIX_TABLE (PREFIX_VEX_0F383F) },
8891     /* 40 */
8892     { PREFIX_TABLE (PREFIX_VEX_0F3840) },
8893     { PREFIX_TABLE (PREFIX_VEX_0F3841) },
8894     { Bad_Opcode },
8895     { Bad_Opcode },
8896     { Bad_Opcode },
8897     { PREFIX_TABLE (PREFIX_VEX_0F3845) },
8898     { PREFIX_TABLE (PREFIX_VEX_0F3846) },
8899     { PREFIX_TABLE (PREFIX_VEX_0F3847) },
8900     /* 48 */
8901     { Bad_Opcode },
8902     { Bad_Opcode },
8903     { Bad_Opcode },
8904     { Bad_Opcode },
8905     { Bad_Opcode },
8906     { Bad_Opcode },
8907     { Bad_Opcode },
8908     { Bad_Opcode },
8909     /* 50 */
8910     { Bad_Opcode },
8911     { Bad_Opcode },
8912     { Bad_Opcode },
8913     { Bad_Opcode },
8914     { Bad_Opcode },
8915     { Bad_Opcode },
8916     { Bad_Opcode },
8917     { Bad_Opcode },
8918     /* 58 */
8919     { PREFIX_TABLE (PREFIX_VEX_0F3858) },
8920     { PREFIX_TABLE (PREFIX_VEX_0F3859) },
8921     { PREFIX_TABLE (PREFIX_VEX_0F385A) },
8922     { Bad_Opcode },
8923     { Bad_Opcode },
8924     { Bad_Opcode },
8925     { Bad_Opcode },
8926     { Bad_Opcode },
8927     /* 60 */
8928     { Bad_Opcode },
8929     { Bad_Opcode },
8930     { Bad_Opcode },
8931     { Bad_Opcode },
8932     { Bad_Opcode },
8933     { Bad_Opcode },
8934     { Bad_Opcode },
8935     { Bad_Opcode },
8936     /* 68 */
8937     { Bad_Opcode },
8938     { Bad_Opcode },
8939     { Bad_Opcode },
8940     { Bad_Opcode },
8941     { Bad_Opcode },
8942     { Bad_Opcode },
8943     { Bad_Opcode },
8944     { Bad_Opcode },
8945     /* 70 */
8946     { Bad_Opcode },
8947     { Bad_Opcode },
8948     { Bad_Opcode },
8949     { Bad_Opcode },
8950     { Bad_Opcode },
8951     { Bad_Opcode },
8952     { Bad_Opcode },
8953     { Bad_Opcode },
8954     /* 78 */
8955     { PREFIX_TABLE (PREFIX_VEX_0F3878) },
8956     { PREFIX_TABLE (PREFIX_VEX_0F3879) },
8957     { Bad_Opcode },
8958     { Bad_Opcode },
8959     { Bad_Opcode },
8960     { Bad_Opcode },
8961     { Bad_Opcode },
8962     { Bad_Opcode },
8963     /* 80 */
8964     { Bad_Opcode },
8965     { Bad_Opcode },
8966     { Bad_Opcode },
8967     { Bad_Opcode },
8968     { Bad_Opcode },
8969     { Bad_Opcode },
8970     { Bad_Opcode },
8971     { Bad_Opcode },
8972     /* 88 */
8973     { Bad_Opcode },
8974     { Bad_Opcode },
8975     { Bad_Opcode },
8976     { Bad_Opcode },
8977     { PREFIX_TABLE (PREFIX_VEX_0F388C) },
8978     { Bad_Opcode },
8979     { PREFIX_TABLE (PREFIX_VEX_0F388E) },
8980     { Bad_Opcode },
8981     /* 90 */
8982     { PREFIX_TABLE (PREFIX_VEX_0F3890) },
8983     { PREFIX_TABLE (PREFIX_VEX_0F3891) },
8984     { PREFIX_TABLE (PREFIX_VEX_0F3892) },
8985     { PREFIX_TABLE (PREFIX_VEX_0F3893) },
8986     { Bad_Opcode },
8987     { Bad_Opcode },
8988     { PREFIX_TABLE (PREFIX_VEX_0F3896) },
8989     { PREFIX_TABLE (PREFIX_VEX_0F3897) },
8990     /* 98 */
8991     { PREFIX_TABLE (PREFIX_VEX_0F3898) },
8992     { PREFIX_TABLE (PREFIX_VEX_0F3899) },
8993     { PREFIX_TABLE (PREFIX_VEX_0F389A) },
8994     { PREFIX_TABLE (PREFIX_VEX_0F389B) },
8995     { PREFIX_TABLE (PREFIX_VEX_0F389C) },
8996     { PREFIX_TABLE (PREFIX_VEX_0F389D) },
8997     { PREFIX_TABLE (PREFIX_VEX_0F389E) },
8998     { PREFIX_TABLE (PREFIX_VEX_0F389F) },
8999     /* a0 */
9000     { Bad_Opcode },
9001     { Bad_Opcode },
9002     { Bad_Opcode },
9003     { Bad_Opcode },
9004     { Bad_Opcode },
9005     { Bad_Opcode },
9006     { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
9007     { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
9008     /* a8 */
9009     { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
9010     { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
9011     { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
9012     { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
9013     { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
9014     { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
9015     { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
9016     { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
9017     /* b0 */
9018     { Bad_Opcode },
9019     { Bad_Opcode },
9020     { Bad_Opcode },
9021     { Bad_Opcode },
9022     { Bad_Opcode },
9023     { Bad_Opcode },
9024     { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
9025     { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
9026     /* b8 */
9027     { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
9028     { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
9029     { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
9030     { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
9031     { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
9032     { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
9033     { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
9034     { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
9035     /* c0 */
9036     { Bad_Opcode },
9037     { Bad_Opcode },
9038     { Bad_Opcode },
9039     { Bad_Opcode },
9040     { Bad_Opcode },
9041     { Bad_Opcode },
9042     { Bad_Opcode },
9043     { Bad_Opcode },
9044     /* c8 */
9045     { Bad_Opcode },
9046     { Bad_Opcode },
9047     { Bad_Opcode },
9048     { Bad_Opcode },
9049     { Bad_Opcode },
9050     { Bad_Opcode },
9051     { Bad_Opcode },
9052     { Bad_Opcode },
9053     /* d0 */
9054     { Bad_Opcode },
9055     { Bad_Opcode },
9056     { Bad_Opcode },
9057     { Bad_Opcode },
9058     { Bad_Opcode },
9059     { Bad_Opcode },
9060     { Bad_Opcode },
9061     { Bad_Opcode },
9062     /* d8 */
9063     { Bad_Opcode },
9064     { Bad_Opcode },
9065     { Bad_Opcode },
9066     { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
9067     { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
9068     { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
9069     { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
9070     { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
9071     /* e0 */
9072     { Bad_Opcode },
9073     { Bad_Opcode },
9074     { Bad_Opcode },
9075     { Bad_Opcode },
9076     { Bad_Opcode },
9077     { Bad_Opcode },
9078     { Bad_Opcode },
9079     { Bad_Opcode },
9080     /* e8 */
9081     { Bad_Opcode },
9082     { Bad_Opcode },
9083     { Bad_Opcode },
9084     { Bad_Opcode },
9085     { Bad_Opcode },
9086     { Bad_Opcode },
9087     { Bad_Opcode },
9088     { Bad_Opcode },
9089     /* f0 */
9090     { Bad_Opcode },
9091     { Bad_Opcode },
9092     { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
9093     { REG_TABLE (REG_VEX_0F38F3) },
9094     { Bad_Opcode },
9095     { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
9096     { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
9097     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
9098     /* f8 */
9099     { Bad_Opcode },
9100     { Bad_Opcode },
9101     { Bad_Opcode },
9102     { Bad_Opcode },
9103     { Bad_Opcode },
9104     { Bad_Opcode },
9105     { Bad_Opcode },
9106     { Bad_Opcode },
9107   },
9108   /* VEX_0F3A */
9109   {
9110     /* 00 */
9111     { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
9112     { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
9113     { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
9114     { Bad_Opcode },
9115     { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
9116     { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
9117     { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
9118     { Bad_Opcode },
9119     /* 08 */
9120     { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
9121     { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
9122     { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
9123     { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
9124     { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
9125     { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
9126     { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
9127     { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
9128     /* 10 */
9129     { Bad_Opcode },
9130     { Bad_Opcode },
9131     { Bad_Opcode },
9132     { Bad_Opcode },
9133     { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
9134     { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
9135     { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
9136     { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
9137     /* 18 */
9138     { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
9139     { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
9140     { Bad_Opcode },
9141     { Bad_Opcode },
9142     { Bad_Opcode },
9143     { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
9144     { Bad_Opcode },
9145     { Bad_Opcode },
9146     /* 20 */
9147     { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
9148     { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
9149     { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
9150     { Bad_Opcode },
9151     { Bad_Opcode },
9152     { Bad_Opcode },
9153     { Bad_Opcode },
9154     { Bad_Opcode },
9155     /* 28 */
9156     { Bad_Opcode },
9157     { Bad_Opcode },
9158     { Bad_Opcode },
9159     { Bad_Opcode },
9160     { Bad_Opcode },
9161     { Bad_Opcode },
9162     { Bad_Opcode },
9163     { Bad_Opcode },
9164     /* 30 */
9165     { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
9166     { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
9167     { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
9168     { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
9169     { Bad_Opcode },
9170     { Bad_Opcode },
9171     { Bad_Opcode },
9172     { Bad_Opcode },
9173     /* 38 */
9174     { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
9175     { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
9176     { Bad_Opcode },
9177     { Bad_Opcode },
9178     { Bad_Opcode },
9179     { Bad_Opcode },
9180     { Bad_Opcode },
9181     { Bad_Opcode },
9182     /* 40 */
9183     { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
9184     { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
9185     { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
9186     { Bad_Opcode },
9187     { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
9188     { Bad_Opcode },
9189     { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
9190     { Bad_Opcode },
9191     /* 48 */
9192     { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
9193     { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
9194     { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
9195     { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
9196     { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
9197     { Bad_Opcode },
9198     { Bad_Opcode },
9199     { Bad_Opcode },
9200     /* 50 */
9201     { Bad_Opcode },
9202     { Bad_Opcode },
9203     { Bad_Opcode },
9204     { Bad_Opcode },
9205     { Bad_Opcode },
9206     { Bad_Opcode },
9207     { Bad_Opcode },
9208     { Bad_Opcode },
9209     /* 58 */
9210     { Bad_Opcode },
9211     { Bad_Opcode },
9212     { Bad_Opcode },
9213     { Bad_Opcode },
9214     { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9215     { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9216     { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9217     { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9218     /* 60 */
9219     { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9220     { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9221     { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9222     { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9223     { Bad_Opcode },
9224     { Bad_Opcode },
9225     { Bad_Opcode },
9226     { Bad_Opcode },
9227     /* 68 */
9228     { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9229     { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9230     { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9231     { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9232     { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9233     { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9234     { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9235     { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9236     /* 70 */
9237     { Bad_Opcode },
9238     { Bad_Opcode },
9239     { Bad_Opcode },
9240     { Bad_Opcode },
9241     { Bad_Opcode },
9242     { Bad_Opcode },
9243     { Bad_Opcode },
9244     { Bad_Opcode },
9245     /* 78 */
9246     { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9247     { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9248     { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9249     { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9250     { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9251     { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9252     { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9253     { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9254     /* 80 */
9255     { Bad_Opcode },
9256     { Bad_Opcode },
9257     { Bad_Opcode },
9258     { Bad_Opcode },
9259     { Bad_Opcode },
9260     { Bad_Opcode },
9261     { Bad_Opcode },
9262     { Bad_Opcode },
9263     /* 88 */
9264     { Bad_Opcode },
9265     { Bad_Opcode },
9266     { Bad_Opcode },
9267     { Bad_Opcode },
9268     { Bad_Opcode },
9269     { Bad_Opcode },
9270     { Bad_Opcode },
9271     { Bad_Opcode },
9272     /* 90 */
9273     { Bad_Opcode },
9274     { Bad_Opcode },
9275     { Bad_Opcode },
9276     { Bad_Opcode },
9277     { Bad_Opcode },
9278     { Bad_Opcode },
9279     { Bad_Opcode },
9280     { Bad_Opcode },
9281     /* 98 */
9282     { Bad_Opcode },
9283     { Bad_Opcode },
9284     { Bad_Opcode },
9285     { Bad_Opcode },
9286     { Bad_Opcode },
9287     { Bad_Opcode },
9288     { Bad_Opcode },
9289     { Bad_Opcode },
9290     /* a0 */
9291     { Bad_Opcode },
9292     { Bad_Opcode },
9293     { Bad_Opcode },
9294     { Bad_Opcode },
9295     { Bad_Opcode },
9296     { Bad_Opcode },
9297     { Bad_Opcode },
9298     { Bad_Opcode },
9299     /* a8 */
9300     { Bad_Opcode },
9301     { Bad_Opcode },
9302     { Bad_Opcode },
9303     { Bad_Opcode },
9304     { Bad_Opcode },
9305     { Bad_Opcode },
9306     { Bad_Opcode },
9307     { Bad_Opcode },
9308     /* b0 */
9309     { Bad_Opcode },
9310     { Bad_Opcode },
9311     { Bad_Opcode },
9312     { Bad_Opcode },
9313     { Bad_Opcode },
9314     { Bad_Opcode },
9315     { Bad_Opcode },
9316     { Bad_Opcode },
9317     /* b8 */
9318     { Bad_Opcode },
9319     { Bad_Opcode },
9320     { Bad_Opcode },
9321     { Bad_Opcode },
9322     { Bad_Opcode },
9323     { Bad_Opcode },
9324     { Bad_Opcode },
9325     { Bad_Opcode },
9326     /* c0 */
9327     { Bad_Opcode },
9328     { Bad_Opcode },
9329     { Bad_Opcode },
9330     { Bad_Opcode },
9331     { Bad_Opcode },
9332     { Bad_Opcode },
9333     { Bad_Opcode },
9334     { Bad_Opcode },
9335     /* c8 */
9336     { Bad_Opcode },
9337     { Bad_Opcode },
9338     { Bad_Opcode },
9339     { Bad_Opcode },
9340     { Bad_Opcode },
9341     { Bad_Opcode },
9342     { Bad_Opcode },
9343     { Bad_Opcode },
9344     /* d0 */
9345     { Bad_Opcode },
9346     { Bad_Opcode },
9347     { Bad_Opcode },
9348     { Bad_Opcode },
9349     { Bad_Opcode },
9350     { Bad_Opcode },
9351     { Bad_Opcode },
9352     { Bad_Opcode },
9353     /* d8 */
9354     { Bad_Opcode },
9355     { Bad_Opcode },
9356     { Bad_Opcode },
9357     { Bad_Opcode },
9358     { Bad_Opcode },
9359     { Bad_Opcode },
9360     { Bad_Opcode },
9361     { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9362     /* e0 */
9363     { Bad_Opcode },
9364     { Bad_Opcode },
9365     { Bad_Opcode },
9366     { Bad_Opcode },
9367     { Bad_Opcode },
9368     { Bad_Opcode },
9369     { Bad_Opcode },
9370     { Bad_Opcode },
9371     /* e8 */
9372     { Bad_Opcode },
9373     { Bad_Opcode },
9374     { Bad_Opcode },
9375     { Bad_Opcode },
9376     { Bad_Opcode },
9377     { Bad_Opcode },
9378     { Bad_Opcode },
9379     { Bad_Opcode },
9380     /* f0 */
9381     { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9382     { Bad_Opcode },
9383     { Bad_Opcode },
9384     { Bad_Opcode },
9385     { Bad_Opcode },
9386     { Bad_Opcode },
9387     { Bad_Opcode },
9388     { Bad_Opcode },
9389     /* f8 */
9390     { Bad_Opcode },
9391     { Bad_Opcode },
9392     { Bad_Opcode },
9393     { Bad_Opcode },
9394     { Bad_Opcode },
9395     { Bad_Opcode },
9396     { Bad_Opcode },
9397     { Bad_Opcode },
9398   },
9399 };
9400
9401 #define NEED_OPCODE_TABLE
9402 #include "i386-dis-evex.h"
9403 #undef NEED_OPCODE_TABLE
9404 static const struct dis386 vex_len_table[][2] = {
9405   /* VEX_LEN_0F10_P_1 */
9406   {
9407     { VEX_W_TABLE (VEX_W_0F10_P_1) },
9408     { VEX_W_TABLE (VEX_W_0F10_P_1) },
9409   },
9410
9411   /* VEX_LEN_0F10_P_3 */
9412   {
9413     { VEX_W_TABLE (VEX_W_0F10_P_3) },
9414     { VEX_W_TABLE (VEX_W_0F10_P_3) },
9415   },
9416
9417   /* VEX_LEN_0F11_P_1 */
9418   {
9419     { VEX_W_TABLE (VEX_W_0F11_P_1) },
9420     { VEX_W_TABLE (VEX_W_0F11_P_1) },
9421   },
9422
9423   /* VEX_LEN_0F11_P_3 */
9424   {
9425     { VEX_W_TABLE (VEX_W_0F11_P_3) },
9426     { VEX_W_TABLE (VEX_W_0F11_P_3) },
9427   },
9428
9429   /* VEX_LEN_0F12_P_0_M_0 */
9430   {
9431     { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) },
9432   },
9433
9434   /* VEX_LEN_0F12_P_0_M_1 */
9435   {
9436     { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) },
9437   },
9438
9439   /* VEX_LEN_0F12_P_2 */
9440   {
9441     { VEX_W_TABLE (VEX_W_0F12_P_2) },
9442   },
9443
9444   /* VEX_LEN_0F13_M_0 */
9445   {
9446     { VEX_W_TABLE (VEX_W_0F13_M_0) },
9447   },
9448
9449   /* VEX_LEN_0F16_P_0_M_0 */
9450   {
9451     { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) },
9452   },
9453
9454   /* VEX_LEN_0F16_P_0_M_1 */
9455   {
9456     { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) },
9457   },
9458
9459   /* VEX_LEN_0F16_P_2 */
9460   {
9461     { VEX_W_TABLE (VEX_W_0F16_P_2) },
9462   },
9463
9464   /* VEX_LEN_0F17_M_0 */
9465   {
9466     { VEX_W_TABLE (VEX_W_0F17_M_0) },
9467   },
9468
9469   /* VEX_LEN_0F2A_P_1 */
9470   {
9471     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9472     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9473   },
9474
9475   /* VEX_LEN_0F2A_P_3 */
9476   {
9477     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9478     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9479   },
9480
9481   /* VEX_LEN_0F2C_P_1 */
9482   {
9483     { "vcvttss2siY",    { Gv, EXdScalar }, 0 },
9484     { "vcvttss2siY",    { Gv, EXdScalar }, 0 },
9485   },
9486
9487   /* VEX_LEN_0F2C_P_3 */
9488   {
9489     { "vcvttsd2siY",    { Gv, EXqScalar }, 0 },
9490     { "vcvttsd2siY",    { Gv, EXqScalar }, 0 },
9491   },
9492
9493   /* VEX_LEN_0F2D_P_1 */
9494   {
9495     { "vcvtss2siY",     { Gv, EXdScalar }, 0 },
9496     { "vcvtss2siY",     { Gv, EXdScalar }, 0 },
9497   },
9498
9499   /* VEX_LEN_0F2D_P_3 */
9500   {
9501     { "vcvtsd2siY",     { Gv, EXqScalar }, 0 },
9502     { "vcvtsd2siY",     { Gv, EXqScalar }, 0 },
9503   },
9504
9505   /* VEX_LEN_0F2E_P_0 */
9506   {
9507     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9508     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9509   },
9510
9511   /* VEX_LEN_0F2E_P_2 */
9512   {
9513     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9514     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9515   },
9516
9517   /* VEX_LEN_0F2F_P_0 */
9518   {
9519     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9520     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9521   },
9522
9523   /* VEX_LEN_0F2F_P_2 */
9524   {
9525     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9526     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9527   },
9528
9529   /* VEX_LEN_0F41_P_0 */
9530   {
9531     { Bad_Opcode },
9532     { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9533   },
9534   /* VEX_LEN_0F41_P_2 */
9535   {
9536     { Bad_Opcode },
9537     { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9538   },
9539   /* VEX_LEN_0F42_P_0 */
9540   {
9541     { Bad_Opcode },
9542     { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9543   },
9544   /* VEX_LEN_0F42_P_2 */
9545   {
9546     { Bad_Opcode },
9547     { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9548   },
9549   /* VEX_LEN_0F44_P_0 */
9550   {
9551     { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9552   },
9553   /* VEX_LEN_0F44_P_2 */
9554   {
9555     { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9556   },
9557   /* VEX_LEN_0F45_P_0 */
9558   {
9559     { Bad_Opcode },
9560     { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9561   },
9562   /* VEX_LEN_0F45_P_2 */
9563   {
9564     { Bad_Opcode },
9565     { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9566   },
9567   /* VEX_LEN_0F46_P_0 */
9568   {
9569     { Bad_Opcode },
9570     { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9571   },
9572   /* VEX_LEN_0F46_P_2 */
9573   {
9574     { Bad_Opcode },
9575     { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9576   },
9577   /* VEX_LEN_0F47_P_0 */
9578   {
9579     { Bad_Opcode },
9580     { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9581   },
9582   /* VEX_LEN_0F47_P_2 */
9583   {
9584     { Bad_Opcode },
9585     { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9586   },
9587   /* VEX_LEN_0F4A_P_0 */
9588   {
9589     { Bad_Opcode },
9590     { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9591   },
9592   /* VEX_LEN_0F4A_P_2 */
9593   {
9594     { Bad_Opcode },
9595     { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9596   },
9597   /* VEX_LEN_0F4B_P_0 */
9598   {
9599     { Bad_Opcode },
9600     { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9601   },
9602   /* VEX_LEN_0F4B_P_2 */
9603   {
9604     { Bad_Opcode },
9605     { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9606   },
9607
9608   /* VEX_LEN_0F51_P_1 */
9609   {
9610     { VEX_W_TABLE (VEX_W_0F51_P_1) },
9611     { VEX_W_TABLE (VEX_W_0F51_P_1) },
9612   },
9613
9614   /* VEX_LEN_0F51_P_3 */
9615   {
9616     { VEX_W_TABLE (VEX_W_0F51_P_3) },
9617     { VEX_W_TABLE (VEX_W_0F51_P_3) },
9618   },
9619
9620   /* VEX_LEN_0F52_P_1 */
9621   {
9622     { VEX_W_TABLE (VEX_W_0F52_P_1) },
9623     { VEX_W_TABLE (VEX_W_0F52_P_1) },
9624   },
9625
9626   /* VEX_LEN_0F53_P_1 */
9627   {
9628     { VEX_W_TABLE (VEX_W_0F53_P_1) },
9629     { VEX_W_TABLE (VEX_W_0F53_P_1) },
9630   },
9631
9632   /* VEX_LEN_0F58_P_1 */
9633   {
9634     { VEX_W_TABLE (VEX_W_0F58_P_1) },
9635     { VEX_W_TABLE (VEX_W_0F58_P_1) },
9636   },
9637
9638   /* VEX_LEN_0F58_P_3 */
9639   {
9640     { VEX_W_TABLE (VEX_W_0F58_P_3) },
9641     { VEX_W_TABLE (VEX_W_0F58_P_3) },
9642   },
9643
9644   /* VEX_LEN_0F59_P_1 */
9645   {
9646     { VEX_W_TABLE (VEX_W_0F59_P_1) },
9647     { VEX_W_TABLE (VEX_W_0F59_P_1) },
9648   },
9649
9650   /* VEX_LEN_0F59_P_3 */
9651   {
9652     { VEX_W_TABLE (VEX_W_0F59_P_3) },
9653     { VEX_W_TABLE (VEX_W_0F59_P_3) },
9654   },
9655
9656   /* VEX_LEN_0F5A_P_1 */
9657   {
9658     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9659     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9660   },
9661
9662   /* VEX_LEN_0F5A_P_3 */
9663   {
9664     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9665     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9666   },
9667
9668   /* VEX_LEN_0F5C_P_1 */
9669   {
9670     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9671     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9672   },
9673
9674   /* VEX_LEN_0F5C_P_3 */
9675   {
9676     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9677     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9678   },
9679
9680   /* VEX_LEN_0F5D_P_1 */
9681   {
9682     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9683     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9684   },
9685
9686   /* VEX_LEN_0F5D_P_3 */
9687   {
9688     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9689     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9690   },
9691
9692   /* VEX_LEN_0F5E_P_1 */
9693   {
9694     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9695     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9696   },
9697
9698   /* VEX_LEN_0F5E_P_3 */
9699   {
9700     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9701     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9702   },
9703
9704   /* VEX_LEN_0F5F_P_1 */
9705   {
9706     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9707     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9708   },
9709
9710   /* VEX_LEN_0F5F_P_3 */
9711   {
9712     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9713     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9714   },
9715
9716   /* VEX_LEN_0F6E_P_2 */
9717   {
9718     { "vmovK",          { XMScalar, Edq }, 0 },
9719     { "vmovK",          { XMScalar, Edq }, 0 },
9720   },
9721
9722   /* VEX_LEN_0F7E_P_1 */
9723   {
9724     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9725     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9726   },
9727
9728   /* VEX_LEN_0F7E_P_2 */
9729   {
9730     { "vmovK",          { Edq, XMScalar }, 0 },
9731     { "vmovK",          { Edq, XMScalar }, 0 },
9732   },
9733
9734   /* VEX_LEN_0F90_P_0 */
9735   {
9736     { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9737   },
9738
9739   /* VEX_LEN_0F90_P_2 */
9740   {
9741     { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9742   },
9743
9744   /* VEX_LEN_0F91_P_0 */
9745   {
9746     { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9747   },
9748
9749   /* VEX_LEN_0F91_P_2 */
9750   {
9751     { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
9752   },
9753
9754   /* VEX_LEN_0F92_P_0 */
9755   {
9756     { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9757   },
9758
9759   /* VEX_LEN_0F92_P_2 */
9760   {
9761     { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
9762   },
9763
9764   /* VEX_LEN_0F92_P_3 */
9765   {
9766     { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0) },
9767   },
9768
9769   /* VEX_LEN_0F93_P_0 */
9770   {
9771     { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9772   },
9773
9774   /* VEX_LEN_0F93_P_2 */
9775   {
9776     { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
9777   },
9778
9779   /* VEX_LEN_0F93_P_3 */
9780   {
9781     { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0) },
9782   },
9783
9784   /* VEX_LEN_0F98_P_0 */
9785   {
9786     { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9787   },
9788
9789   /* VEX_LEN_0F98_P_2 */
9790   {
9791     { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
9792   },
9793
9794   /* VEX_LEN_0F99_P_0 */
9795   {
9796     { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
9797   },
9798
9799   /* VEX_LEN_0F99_P_2 */
9800   {
9801     { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
9802   },
9803
9804   /* VEX_LEN_0FAE_R_2_M_0 */
9805   {
9806     { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) },
9807   },
9808
9809   /* VEX_LEN_0FAE_R_3_M_0 */
9810   {
9811     { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) },
9812   },
9813
9814   /* VEX_LEN_0FC2_P_1 */
9815   {
9816     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9817     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9818   },
9819
9820   /* VEX_LEN_0FC2_P_3 */
9821   {
9822     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9823     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9824   },
9825
9826   /* VEX_LEN_0FC4_P_2 */
9827   {
9828     { VEX_W_TABLE (VEX_W_0FC4_P_2) },
9829   },
9830
9831   /* VEX_LEN_0FC5_P_2 */
9832   {
9833     { VEX_W_TABLE (VEX_W_0FC5_P_2) },
9834   },
9835
9836   /* VEX_LEN_0FD6_P_2 */
9837   {
9838     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9839     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9840   },
9841
9842   /* VEX_LEN_0FF7_P_2 */
9843   {
9844     { VEX_W_TABLE (VEX_W_0FF7_P_2) },
9845   },
9846
9847   /* VEX_LEN_0F3816_P_2 */
9848   {
9849     { Bad_Opcode },
9850     { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9851   },
9852
9853   /* VEX_LEN_0F3819_P_2 */
9854   {
9855     { Bad_Opcode },
9856     { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9857   },
9858
9859   /* VEX_LEN_0F381A_P_2_M_0 */
9860   {
9861     { Bad_Opcode },
9862     { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9863   },
9864
9865   /* VEX_LEN_0F3836_P_2 */
9866   {
9867     { Bad_Opcode },
9868     { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9869   },
9870
9871   /* VEX_LEN_0F3841_P_2 */
9872   {
9873     { VEX_W_TABLE (VEX_W_0F3841_P_2) },
9874   },
9875
9876   /* VEX_LEN_0F385A_P_2_M_0 */
9877   {
9878     { Bad_Opcode },
9879     { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
9880   },
9881
9882   /* VEX_LEN_0F38DB_P_2 */
9883   {
9884     { VEX_W_TABLE (VEX_W_0F38DB_P_2) },
9885   },
9886
9887   /* VEX_LEN_0F38DC_P_2 */
9888   {
9889     { VEX_W_TABLE (VEX_W_0F38DC_P_2) },
9890   },
9891
9892   /* VEX_LEN_0F38DD_P_2 */
9893   {
9894     { VEX_W_TABLE (VEX_W_0F38DD_P_2) },
9895   },
9896
9897   /* VEX_LEN_0F38DE_P_2 */
9898   {
9899     { VEX_W_TABLE (VEX_W_0F38DE_P_2) },
9900   },
9901
9902   /* VEX_LEN_0F38DF_P_2 */
9903   {
9904     { VEX_W_TABLE (VEX_W_0F38DF_P_2) },
9905   },
9906
9907   /* VEX_LEN_0F38F2_P_0 */
9908   {
9909     { "andnS",          { Gdq, VexGdq, Edq }, 0 },
9910   },
9911
9912   /* VEX_LEN_0F38F3_R_1_P_0 */
9913   {
9914     { "blsrS",          { VexGdq, Edq }, 0 },
9915   },
9916
9917   /* VEX_LEN_0F38F3_R_2_P_0 */
9918   {
9919     { "blsmskS",        { VexGdq, Edq }, 0 },
9920   },
9921
9922   /* VEX_LEN_0F38F3_R_3_P_0 */
9923   {
9924     { "blsiS",          { VexGdq, Edq }, 0 },
9925   },
9926
9927   /* VEX_LEN_0F38F5_P_0 */
9928   {
9929     { "bzhiS",          { Gdq, Edq, VexGdq }, 0 },
9930   },
9931
9932   /* VEX_LEN_0F38F5_P_1 */
9933   {
9934     { "pextS",          { Gdq, VexGdq, Edq }, 0 },
9935   },
9936
9937   /* VEX_LEN_0F38F5_P_3 */
9938   {
9939     { "pdepS",          { Gdq, VexGdq, Edq }, 0 },
9940   },
9941
9942   /* VEX_LEN_0F38F6_P_3 */
9943   {
9944     { "mulxS",          { Gdq, VexGdq, Edq }, 0 },
9945   },
9946
9947   /* VEX_LEN_0F38F7_P_0 */
9948   {
9949     { "bextrS",         { Gdq, Edq, VexGdq }, 0 },
9950   },
9951
9952   /* VEX_LEN_0F38F7_P_1 */
9953   {
9954     { "sarxS",          { Gdq, Edq, VexGdq }, 0 },
9955   },
9956
9957   /* VEX_LEN_0F38F7_P_2 */
9958   {
9959     { "shlxS",          { Gdq, Edq, VexGdq }, 0 },
9960   },
9961
9962   /* VEX_LEN_0F38F7_P_3 */
9963   {
9964     { "shrxS",          { Gdq, Edq, VexGdq }, 0 },
9965   },
9966
9967   /* VEX_LEN_0F3A00_P_2 */
9968   {
9969     { Bad_Opcode },
9970     { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
9971   },
9972
9973   /* VEX_LEN_0F3A01_P_2 */
9974   {
9975     { Bad_Opcode },
9976     { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
9977   },
9978
9979   /* VEX_LEN_0F3A06_P_2 */
9980   {
9981     { Bad_Opcode },
9982     { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
9983   },
9984
9985   /* VEX_LEN_0F3A0A_P_2 */
9986   {
9987     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
9988     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
9989   },
9990
9991   /* VEX_LEN_0F3A0B_P_2 */
9992   {
9993     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
9994     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
9995   },
9996
9997   /* VEX_LEN_0F3A14_P_2 */
9998   {
9999     { VEX_W_TABLE (VEX_W_0F3A14_P_2) },
10000   },
10001
10002   /* VEX_LEN_0F3A15_P_2 */
10003   {
10004     { VEX_W_TABLE (VEX_W_0F3A15_P_2) },
10005   },
10006
10007   /* VEX_LEN_0F3A16_P_2  */
10008   {
10009     { "vpextrK",        { Edq, XM, Ib }, 0 },
10010   },
10011
10012   /* VEX_LEN_0F3A17_P_2 */
10013   {
10014     { "vextractps",     { Edqd, XM, Ib }, 0 },
10015   },
10016
10017   /* VEX_LEN_0F3A18_P_2 */
10018   {
10019     { Bad_Opcode },
10020     { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
10021   },
10022
10023   /* VEX_LEN_0F3A19_P_2 */
10024   {
10025     { Bad_Opcode },
10026     { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
10027   },
10028
10029   /* VEX_LEN_0F3A20_P_2 */
10030   {
10031     { VEX_W_TABLE (VEX_W_0F3A20_P_2) },
10032   },
10033
10034   /* VEX_LEN_0F3A21_P_2 */
10035   {
10036     { VEX_W_TABLE (VEX_W_0F3A21_P_2) },
10037   },
10038
10039   /* VEX_LEN_0F3A22_P_2 */
10040   {
10041     { "vpinsrK",        { XM, Vex128, Edq, Ib }, 0 },
10042   },
10043
10044   /* VEX_LEN_0F3A30_P_2 */
10045   {
10046     { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
10047   },
10048
10049   /* VEX_LEN_0F3A31_P_2 */
10050   {
10051     { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
10052   },
10053
10054   /* VEX_LEN_0F3A32_P_2 */
10055   {
10056     { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
10057   },
10058
10059   /* VEX_LEN_0F3A33_P_2 */
10060   {
10061     { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
10062   },
10063
10064   /* VEX_LEN_0F3A38_P_2 */
10065   {
10066     { Bad_Opcode },
10067     { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
10068   },
10069
10070   /* VEX_LEN_0F3A39_P_2 */
10071   {
10072     { Bad_Opcode },
10073     { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
10074   },
10075
10076   /* VEX_LEN_0F3A41_P_2 */
10077   {
10078     { VEX_W_TABLE (VEX_W_0F3A41_P_2) },
10079   },
10080
10081   /* VEX_LEN_0F3A44_P_2 */
10082   {
10083     { VEX_W_TABLE (VEX_W_0F3A44_P_2) },
10084   },
10085
10086   /* VEX_LEN_0F3A46_P_2 */
10087   {
10088     { Bad_Opcode },
10089     { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
10090   },
10091
10092   /* VEX_LEN_0F3A60_P_2 */
10093   {
10094     { "vpcmpestrm",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
10095   },
10096
10097   /* VEX_LEN_0F3A61_P_2 */
10098   {
10099     { "vpcmpestri",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
10100   },
10101
10102   /* VEX_LEN_0F3A62_P_2 */
10103   {
10104     { VEX_W_TABLE (VEX_W_0F3A62_P_2) },
10105   },
10106
10107   /* VEX_LEN_0F3A63_P_2 */
10108   {
10109     { VEX_W_TABLE (VEX_W_0F3A63_P_2) },
10110   },
10111
10112   /* VEX_LEN_0F3A6A_P_2 */
10113   {
10114     { "vfmaddss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10115   },
10116
10117   /* VEX_LEN_0F3A6B_P_2 */
10118   {
10119     { "vfmaddsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10120   },
10121
10122   /* VEX_LEN_0F3A6E_P_2 */
10123   {
10124     { "vfmsubss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10125   },
10126
10127   /* VEX_LEN_0F3A6F_P_2 */
10128   {
10129     { "vfmsubsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10130   },
10131
10132   /* VEX_LEN_0F3A7A_P_2 */
10133   {
10134     { "vfnmaddss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10135   },
10136
10137   /* VEX_LEN_0F3A7B_P_2 */
10138   {
10139     { "vfnmaddsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10140   },
10141
10142   /* VEX_LEN_0F3A7E_P_2 */
10143   {
10144     { "vfnmsubss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10145   },
10146
10147   /* VEX_LEN_0F3A7F_P_2 */
10148   {
10149     { "vfnmsubsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10150   },
10151
10152   /* VEX_LEN_0F3ADF_P_2 */
10153   {
10154     { VEX_W_TABLE (VEX_W_0F3ADF_P_2) },
10155   },
10156
10157   /* VEX_LEN_0F3AF0_P_3 */
10158   {
10159     { "rorxS",          { Gdq, Edq, Ib }, 0 },
10160   },
10161
10162   /* VEX_LEN_0FXOP_08_CC */
10163   {
10164      { "vpcomb",        { XM, Vex128, EXx, Ib }, 0 },
10165   },
10166
10167   /* VEX_LEN_0FXOP_08_CD */
10168   {
10169      { "vpcomw",        { XM, Vex128, EXx, Ib }, 0 },
10170   },
10171
10172   /* VEX_LEN_0FXOP_08_CE */
10173   {
10174      { "vpcomd",        { XM, Vex128, EXx, Ib }, 0 },
10175   },
10176
10177   /* VEX_LEN_0FXOP_08_CF */
10178   {
10179      { "vpcomq",        { XM, Vex128, EXx, Ib }, 0 },
10180   },
10181
10182   /* VEX_LEN_0FXOP_08_EC */
10183   {
10184      { "vpcomub",       { XM, Vex128, EXx, Ib }, 0 },
10185   },
10186
10187   /* VEX_LEN_0FXOP_08_ED */
10188   {
10189      { "vpcomuw",       { XM, Vex128, EXx, Ib }, 0 },
10190   },
10191
10192   /* VEX_LEN_0FXOP_08_EE */
10193   {
10194      { "vpcomud",       { XM, Vex128, EXx, Ib }, 0 },
10195   },
10196
10197   /* VEX_LEN_0FXOP_08_EF */
10198   {
10199      { "vpcomuq",       { XM, Vex128, EXx, Ib }, 0 },
10200   },
10201
10202   /* VEX_LEN_0FXOP_09_80 */
10203   {
10204     { "vfrczps",        { XM, EXxmm }, 0 },
10205     { "vfrczps",        { XM, EXymmq }, 0 },
10206   },
10207
10208   /* VEX_LEN_0FXOP_09_81 */
10209   {
10210     { "vfrczpd",        { XM, EXxmm }, 0 },
10211     { "vfrczpd",        { XM, EXymmq }, 0 },
10212   },
10213 };
10214
10215 static const struct dis386 vex_w_table[][2] = {
10216   {
10217     /* VEX_W_0F10_P_0 */
10218     { "vmovups",        { XM, EXx }, 0 },
10219   },
10220   {
10221     /* VEX_W_0F10_P_1 */
10222     { "vmovss",         { XMVexScalar, VexScalar, EXdScalar }, 0 },
10223   },
10224   {
10225     /* VEX_W_0F10_P_2 */
10226     { "vmovupd",        { XM, EXx }, 0 },
10227   },
10228   {
10229     /* VEX_W_0F10_P_3 */
10230     { "vmovsd",         { XMVexScalar, VexScalar, EXqScalar }, 0 },
10231   },
10232   {
10233     /* VEX_W_0F11_P_0 */
10234     { "vmovups",        { EXxS, XM }, 0 },
10235   },
10236   {
10237     /* VEX_W_0F11_P_1 */
10238     { "vmovss",         { EXdVexScalarS, VexScalar, XMScalar }, 0 },
10239   },
10240   {
10241     /* VEX_W_0F11_P_2 */
10242     { "vmovupd",        { EXxS, XM }, 0 },
10243   },
10244   {
10245     /* VEX_W_0F11_P_3 */
10246     { "vmovsd",         { EXqVexScalarS, VexScalar, XMScalar }, 0 },
10247   },
10248   {
10249     /* VEX_W_0F12_P_0_M_0 */
10250     { "vmovlps",        { XM, Vex128, EXq }, 0 },
10251   },
10252   {
10253     /* VEX_W_0F12_P_0_M_1 */
10254     { "vmovhlps",       { XM, Vex128, EXq }, 0 },
10255   },
10256   {
10257     /* VEX_W_0F12_P_1 */
10258     { "vmovsldup",      { XM, EXx }, 0 },
10259   },
10260   {
10261     /* VEX_W_0F12_P_2 */
10262     { "vmovlpd",        { XM, Vex128, EXq }, 0 },
10263   },
10264   {
10265     /* VEX_W_0F12_P_3 */
10266     { "vmovddup",       { XM, EXymmq }, 0 },
10267   },
10268   {
10269     /* VEX_W_0F13_M_0 */
10270     { "vmovlpX",        { EXq, XM }, 0 },
10271   },
10272   {
10273     /* VEX_W_0F14 */
10274     { "vunpcklpX",      { XM, Vex, EXx }, 0 },
10275   },
10276   {
10277     /* VEX_W_0F15 */
10278     { "vunpckhpX",      { XM, Vex, EXx }, 0 },
10279   },
10280   {
10281     /* VEX_W_0F16_P_0_M_0 */
10282     { "vmovhps",        { XM, Vex128, EXq }, 0 },
10283   },
10284   {
10285     /* VEX_W_0F16_P_0_M_1 */
10286     { "vmovlhps",       { XM, Vex128, EXq }, 0 },
10287   },
10288   {
10289     /* VEX_W_0F16_P_1 */
10290     { "vmovshdup",      { XM, EXx }, 0 },
10291   },
10292   {
10293     /* VEX_W_0F16_P_2 */
10294     { "vmovhpd",        { XM, Vex128, EXq }, 0 },
10295   },
10296   {
10297     /* VEX_W_0F17_M_0 */
10298     { "vmovhpX",        { EXq, XM }, 0 },
10299   },
10300   {
10301     /* VEX_W_0F28 */
10302     { "vmovapX",        { XM, EXx }, 0 },
10303   },
10304   {
10305     /* VEX_W_0F29 */
10306     { "vmovapX",        { EXxS, XM }, 0 },
10307   },
10308   {
10309     /* VEX_W_0F2B_M_0 */
10310     { "vmovntpX",       { Mx, XM }, 0 },
10311   },
10312   {
10313     /* VEX_W_0F2E_P_0 */
10314     { "vucomiss",       { XMScalar, EXdScalar }, 0 },
10315   },
10316   {
10317     /* VEX_W_0F2E_P_2 */
10318     { "vucomisd",       { XMScalar, EXqScalar }, 0 },
10319   },
10320   {
10321     /* VEX_W_0F2F_P_0 */
10322     { "vcomiss",        { XMScalar, EXdScalar }, 0 },
10323   },
10324   {
10325     /* VEX_W_0F2F_P_2 */
10326     { "vcomisd",        { XMScalar, EXqScalar }, 0 },
10327   },
10328   {
10329     /* VEX_W_0F41_P_0_LEN_1 */
10330     { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
10331     { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) },
10332   },
10333   {
10334     /* VEX_W_0F41_P_2_LEN_1 */
10335     { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) },
10336     { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) }
10337   },
10338   {
10339     /* VEX_W_0F42_P_0_LEN_1 */
10340     { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) },
10341     { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) },
10342   },
10343   {
10344     /* VEX_W_0F42_P_2_LEN_1 */
10345     { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) },
10346     { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) },
10347   },
10348   {
10349     /* VEX_W_0F44_P_0_LEN_0 */
10350     { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) },
10351     { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) },
10352   },
10353   {
10354     /* VEX_W_0F44_P_2_LEN_0 */
10355     { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) },
10356     { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) },
10357   },
10358   {
10359     /* VEX_W_0F45_P_0_LEN_1 */
10360     { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) },
10361     { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) },
10362   },
10363   {
10364     /* VEX_W_0F45_P_2_LEN_1 */
10365     { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) },
10366     { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) },
10367   },
10368   {
10369     /* VEX_W_0F46_P_0_LEN_1 */
10370     { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) },
10371     { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) },
10372   },
10373   {
10374     /* VEX_W_0F46_P_2_LEN_1 */
10375     { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) },
10376     { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) },
10377   },
10378   {
10379     /* VEX_W_0F47_P_0_LEN_1 */
10380     { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) },
10381     { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) },
10382   },
10383   {
10384     /* VEX_W_0F47_P_2_LEN_1 */
10385     { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) },
10386     { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) },
10387   },
10388   {
10389     /* VEX_W_0F4A_P_0_LEN_1 */
10390     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) },
10391     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) },
10392   },
10393   {
10394     /* VEX_W_0F4A_P_2_LEN_1 */
10395     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) },
10396     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) },
10397   },
10398   {
10399     /* VEX_W_0F4B_P_0_LEN_1 */
10400     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) },
10401     { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) },
10402   },
10403   {
10404     /* VEX_W_0F4B_P_2_LEN_1 */
10405     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
10406   },
10407   {
10408     /* VEX_W_0F50_M_0 */
10409     { "vmovmskpX",      { Gdq, XS }, 0 },
10410   },
10411   {
10412     /* VEX_W_0F51_P_0 */
10413     { "vsqrtps",        { XM, EXx }, 0 },
10414   },
10415   {
10416     /* VEX_W_0F51_P_1 */
10417     { "vsqrtss",        { XMScalar, VexScalar, EXdScalar }, 0 },
10418   },
10419   {
10420     /* VEX_W_0F51_P_2  */
10421     { "vsqrtpd",        { XM, EXx }, 0 },
10422   },
10423   {
10424     /* VEX_W_0F51_P_3 */
10425     { "vsqrtsd",        { XMScalar, VexScalar, EXqScalar }, 0 },
10426   },
10427   {
10428     /* VEX_W_0F52_P_0 */
10429     { "vrsqrtps",       { XM, EXx }, 0 },
10430   },
10431   {
10432     /* VEX_W_0F52_P_1 */
10433     { "vrsqrtss",       { XMScalar, VexScalar, EXdScalar }, 0 },
10434   },
10435   {
10436     /* VEX_W_0F53_P_0  */
10437     { "vrcpps",         { XM, EXx }, 0 },
10438   },
10439   {
10440     /* VEX_W_0F53_P_1  */
10441     { "vrcpss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10442   },
10443   {
10444     /* VEX_W_0F58_P_0  */
10445     { "vaddps",         { XM, Vex, EXx }, 0 },
10446   },
10447   {
10448     /* VEX_W_0F58_P_1  */
10449     { "vaddss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10450   },
10451   {
10452     /* VEX_W_0F58_P_2  */
10453     { "vaddpd",         { XM, Vex, EXx }, 0 },
10454   },
10455   {
10456     /* VEX_W_0F58_P_3  */
10457     { "vaddsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10458   },
10459   {
10460     /* VEX_W_0F59_P_0  */
10461     { "vmulps",         { XM, Vex, EXx }, 0 },
10462   },
10463   {
10464     /* VEX_W_0F59_P_1  */
10465     { "vmulss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10466   },
10467   {
10468     /* VEX_W_0F59_P_2  */
10469     { "vmulpd",         { XM, Vex, EXx }, 0 },
10470   },
10471   {
10472     /* VEX_W_0F59_P_3  */
10473     { "vmulsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10474   },
10475   {
10476     /* VEX_W_0F5A_P_0  */
10477     { "vcvtps2pd",      { XM, EXxmmq }, 0 },
10478   },
10479   {
10480     /* VEX_W_0F5A_P_1  */
10481     { "vcvtss2sd",      { XMScalar, VexScalar, EXdScalar }, 0 },
10482   },
10483   {
10484     /* VEX_W_0F5A_P_3  */
10485     { "vcvtsd2ss",      { XMScalar, VexScalar, EXqScalar }, 0 },
10486   },
10487   {
10488     /* VEX_W_0F5B_P_0  */
10489     { "vcvtdq2ps",      { XM, EXx }, 0 },
10490   },
10491   {
10492     /* VEX_W_0F5B_P_1  */
10493     { "vcvttps2dq",     { XM, EXx }, 0 },
10494   },
10495   {
10496     /* VEX_W_0F5B_P_2  */
10497     { "vcvtps2dq",      { XM, EXx }, 0 },
10498   },
10499   {
10500     /* VEX_W_0F5C_P_0  */
10501     { "vsubps",         { XM, Vex, EXx }, 0 },
10502   },
10503   {
10504     /* VEX_W_0F5C_P_1  */
10505     { "vsubss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10506   },
10507   {
10508     /* VEX_W_0F5C_P_2  */
10509     { "vsubpd",         { XM, Vex, EXx }, 0 },
10510   },
10511   {
10512     /* VEX_W_0F5C_P_3  */
10513     { "vsubsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10514   },
10515   {
10516     /* VEX_W_0F5D_P_0  */
10517     { "vminps",         { XM, Vex, EXx }, 0 },
10518   },
10519   {
10520     /* VEX_W_0F5D_P_1  */
10521     { "vminss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10522   },
10523   {
10524     /* VEX_W_0F5D_P_2  */
10525     { "vminpd",         { XM, Vex, EXx }, 0 },
10526   },
10527   {
10528     /* VEX_W_0F5D_P_3  */
10529     { "vminsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10530   },
10531   {
10532     /* VEX_W_0F5E_P_0  */
10533     { "vdivps",         { XM, Vex, EXx }, 0 },
10534   },
10535   {
10536     /* VEX_W_0F5E_P_1  */
10537     { "vdivss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10538   },
10539   {
10540     /* VEX_W_0F5E_P_2  */
10541     { "vdivpd",         { XM, Vex, EXx }, 0 },
10542   },
10543   {
10544     /* VEX_W_0F5E_P_3  */
10545     { "vdivsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10546   },
10547   {
10548     /* VEX_W_0F5F_P_0  */
10549     { "vmaxps",         { XM, Vex, EXx }, 0 },
10550   },
10551   {
10552     /* VEX_W_0F5F_P_1  */
10553     { "vmaxss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10554   },
10555   {
10556     /* VEX_W_0F5F_P_2  */
10557     { "vmaxpd",         { XM, Vex, EXx }, 0 },
10558   },
10559   {
10560     /* VEX_W_0F5F_P_3  */
10561     { "vmaxsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10562   },
10563   {
10564     /* VEX_W_0F60_P_2  */
10565     { "vpunpcklbw",     { XM, Vex, EXx }, 0 },
10566   },
10567   {
10568     /* VEX_W_0F61_P_2  */
10569     { "vpunpcklwd",     { XM, Vex, EXx }, 0 },
10570   },
10571   {
10572     /* VEX_W_0F62_P_2  */
10573     { "vpunpckldq",     { XM, Vex, EXx }, 0 },
10574   },
10575   {
10576     /* VEX_W_0F63_P_2  */
10577     { "vpacksswb",      { XM, Vex, EXx }, 0 },
10578   },
10579   {
10580     /* VEX_W_0F64_P_2  */
10581     { "vpcmpgtb",       { XM, Vex, EXx }, 0 },
10582   },
10583   {
10584     /* VEX_W_0F65_P_2  */
10585     { "vpcmpgtw",       { XM, Vex, EXx }, 0 },
10586   },
10587   {
10588     /* VEX_W_0F66_P_2  */
10589     { "vpcmpgtd",       { XM, Vex, EXx }, 0 },
10590   },
10591   {
10592     /* VEX_W_0F67_P_2  */
10593     { "vpackuswb",      { XM, Vex, EXx }, 0 },
10594   },
10595   {
10596     /* VEX_W_0F68_P_2  */
10597     { "vpunpckhbw",     { XM, Vex, EXx }, 0 },
10598   },
10599   {
10600     /* VEX_W_0F69_P_2  */
10601     { "vpunpckhwd",     { XM, Vex, EXx }, 0 },
10602   },
10603   {
10604     /* VEX_W_0F6A_P_2  */
10605     { "vpunpckhdq",     { XM, Vex, EXx }, 0 },
10606   },
10607   {
10608     /* VEX_W_0F6B_P_2  */
10609     { "vpackssdw",      { XM, Vex, EXx }, 0 },
10610   },
10611   {
10612     /* VEX_W_0F6C_P_2  */
10613     { "vpunpcklqdq",    { XM, Vex, EXx }, 0 },
10614   },
10615   {
10616     /* VEX_W_0F6D_P_2  */
10617     { "vpunpckhqdq",    { XM, Vex, EXx }, 0 },
10618   },
10619   {
10620     /* VEX_W_0F6F_P_1  */
10621     { "vmovdqu",        { XM, EXx }, 0 },
10622   },
10623   {
10624     /* VEX_W_0F6F_P_2  */
10625     { "vmovdqa",        { XM, EXx }, 0 },
10626   },
10627   {
10628     /* VEX_W_0F70_P_1 */
10629     { "vpshufhw",       { XM, EXx, Ib }, 0 },
10630   },
10631   {
10632     /* VEX_W_0F70_P_2 */
10633     { "vpshufd",        { XM, EXx, Ib }, 0 },
10634   },
10635   {
10636     /* VEX_W_0F70_P_3 */
10637     { "vpshuflw",       { XM, EXx, Ib }, 0 },
10638   },
10639   {
10640     /* VEX_W_0F71_R_2_P_2  */
10641     { "vpsrlw",         { Vex, XS, Ib }, 0 },
10642   },
10643   {
10644     /* VEX_W_0F71_R_4_P_2  */
10645     { "vpsraw",         { Vex, XS, Ib }, 0 },
10646   },
10647   {
10648     /* VEX_W_0F71_R_6_P_2  */
10649     { "vpsllw",         { Vex, XS, Ib }, 0 },
10650   },
10651   {
10652     /* VEX_W_0F72_R_2_P_2  */
10653     { "vpsrld",         { Vex, XS, Ib }, 0 },
10654   },
10655   {
10656     /* VEX_W_0F72_R_4_P_2  */
10657     { "vpsrad",         { Vex, XS, Ib }, 0 },
10658   },
10659   {
10660     /* VEX_W_0F72_R_6_P_2  */
10661     { "vpslld",         { Vex, XS, Ib }, 0 },
10662   },
10663   {
10664     /* VEX_W_0F73_R_2_P_2  */
10665     { "vpsrlq",         { Vex, XS, Ib }, 0 },
10666   },
10667   {
10668     /* VEX_W_0F73_R_3_P_2  */
10669     { "vpsrldq",        { Vex, XS, Ib }, 0 },
10670   },
10671   {
10672     /* VEX_W_0F73_R_6_P_2  */
10673     { "vpsllq",         { Vex, XS, Ib }, 0 },
10674   },
10675   {
10676     /* VEX_W_0F73_R_7_P_2  */
10677     { "vpslldq",        { Vex, XS, Ib }, 0 },
10678   },
10679   {
10680     /* VEX_W_0F74_P_2 */
10681     { "vpcmpeqb",       { XM, Vex, EXx }, 0 },
10682   },
10683   {
10684     /* VEX_W_0F75_P_2 */
10685     { "vpcmpeqw",       { XM, Vex, EXx }, 0 },
10686   },
10687   {
10688     /* VEX_W_0F76_P_2 */
10689     { "vpcmpeqd",       { XM, Vex, EXx }, 0 },
10690   },
10691   {
10692     /* VEX_W_0F77_P_0 */
10693     { "",               { VZERO }, 0 },
10694   },
10695   {
10696     /* VEX_W_0F7C_P_2 */
10697     { "vhaddpd",        { XM, Vex, EXx }, 0 },
10698   },
10699   {
10700     /* VEX_W_0F7C_P_3 */
10701     { "vhaddps",        { XM, Vex, EXx }, 0 },
10702   },
10703   {
10704     /* VEX_W_0F7D_P_2 */
10705     { "vhsubpd",        { XM, Vex, EXx }, 0 },
10706   },
10707   {
10708     /* VEX_W_0F7D_P_3 */
10709     { "vhsubps",        { XM, Vex, EXx }, 0 },
10710   },
10711   {
10712     /* VEX_W_0F7E_P_1 */
10713     { "vmovq",          { XMScalar, EXqScalar }, 0 },
10714   },
10715   {
10716     /* VEX_W_0F7F_P_1 */
10717     { "vmovdqu",        { EXxS, XM }, 0 },
10718   },
10719   {
10720     /* VEX_W_0F7F_P_2 */
10721     { "vmovdqa",        { EXxS, XM }, 0 },
10722   },
10723   {
10724     /* VEX_W_0F90_P_0_LEN_0 */
10725     { "kmovw",          { MaskG, MaskE }, 0 },
10726     { "kmovq",          { MaskG, MaskE }, 0 },
10727   },
10728   {
10729     /* VEX_W_0F90_P_2_LEN_0 */
10730     { "kmovb",          { MaskG, MaskBDE }, 0 },
10731     { "kmovd",          { MaskG, MaskBDE }, 0 },
10732   },
10733   {
10734     /* VEX_W_0F91_P_0_LEN_0 */
10735     { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
10736     { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
10737   },
10738   {
10739     /* VEX_W_0F91_P_2_LEN_0 */
10740     { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
10741     { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
10742   },
10743   {
10744     /* VEX_W_0F92_P_0_LEN_0 */
10745     { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
10746   },
10747   {
10748     /* VEX_W_0F92_P_2_LEN_0 */
10749     { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
10750   },
10751   {
10752     /* VEX_W_0F92_P_3_LEN_0 */
10753     { MOD_TABLE (MOD_VEX_W_0_0F92_P_3_LEN_0) },
10754     { MOD_TABLE (MOD_VEX_W_1_0F92_P_3_LEN_0) },
10755   },
10756   {
10757     /* VEX_W_0F93_P_0_LEN_0 */
10758     { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
10759   },
10760   {
10761     /* VEX_W_0F93_P_2_LEN_0 */
10762     { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
10763   },
10764   {
10765     /* VEX_W_0F93_P_3_LEN_0 */
10766     { MOD_TABLE (MOD_VEX_W_0_0F93_P_3_LEN_0) },
10767     { MOD_TABLE (MOD_VEX_W_1_0F93_P_3_LEN_0) },
10768   },
10769   {
10770     /* VEX_W_0F98_P_0_LEN_0 */
10771     { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
10772     { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
10773   },
10774   {
10775     /* VEX_W_0F98_P_2_LEN_0 */
10776     { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
10777     { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
10778   },
10779   {
10780     /* VEX_W_0F99_P_0_LEN_0 */
10781     { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
10782     { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
10783   },
10784   {
10785     /* VEX_W_0F99_P_2_LEN_0 */
10786     { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
10787     { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
10788   },
10789   {
10790     /* VEX_W_0FAE_R_2_M_0 */
10791     { "vldmxcsr",       { Md }, 0 },
10792   },
10793   {
10794     /* VEX_W_0FAE_R_3_M_0 */
10795     { "vstmxcsr",       { Md }, 0 },
10796   },
10797   {
10798     /* VEX_W_0FC2_P_0 */
10799     { "vcmpps",         { XM, Vex, EXx, VCMP }, 0 },
10800   },
10801   {
10802     /* VEX_W_0FC2_P_1 */
10803     { "vcmpss",         { XMScalar, VexScalar, EXdScalar, VCMP }, 0 },
10804   },
10805   {
10806     /* VEX_W_0FC2_P_2 */
10807     { "vcmppd",         { XM, Vex, EXx, VCMP }, 0 },
10808   },
10809   {
10810     /* VEX_W_0FC2_P_3 */
10811     { "vcmpsd",         { XMScalar, VexScalar, EXqScalar, VCMP }, 0 },
10812   },
10813   {
10814     /* VEX_W_0FC4_P_2 */
10815     { "vpinsrw",        { XM, Vex128, Edqw, Ib }, 0 },
10816   },
10817   {
10818     /* VEX_W_0FC5_P_2 */
10819     { "vpextrw",        { Gdq, XS, Ib }, 0 },
10820   },
10821   {
10822     /* VEX_W_0FD0_P_2 */
10823     { "vaddsubpd",      { XM, Vex, EXx }, 0 },
10824   },
10825   {
10826     /* VEX_W_0FD0_P_3 */
10827     { "vaddsubps",      { XM, Vex, EXx }, 0 },
10828   },
10829   {
10830     /* VEX_W_0FD1_P_2 */
10831     { "vpsrlw",         { XM, Vex, EXxmm }, 0 },
10832   },
10833   {
10834     /* VEX_W_0FD2_P_2 */
10835     { "vpsrld",         { XM, Vex, EXxmm }, 0 },
10836   },
10837   {
10838     /* VEX_W_0FD3_P_2 */
10839     { "vpsrlq",         { XM, Vex, EXxmm }, 0 },
10840   },
10841   {
10842     /* VEX_W_0FD4_P_2 */
10843     { "vpaddq",         { XM, Vex, EXx }, 0 },
10844   },
10845   {
10846     /* VEX_W_0FD5_P_2 */
10847     { "vpmullw",        { XM, Vex, EXx }, 0 },
10848   },
10849   {
10850     /* VEX_W_0FD6_P_2 */
10851     { "vmovq",          { EXqScalarS, XMScalar }, 0 },
10852   },
10853   {
10854     /* VEX_W_0FD7_P_2_M_1 */
10855     { "vpmovmskb",      { Gdq, XS }, 0 },
10856   },
10857   {
10858     /* VEX_W_0FD8_P_2 */
10859     { "vpsubusb",       { XM, Vex, EXx }, 0 },
10860   },
10861   {
10862     /* VEX_W_0FD9_P_2 */
10863     { "vpsubusw",       { XM, Vex, EXx }, 0 },
10864   },
10865   {
10866     /* VEX_W_0FDA_P_2 */
10867     { "vpminub",        { XM, Vex, EXx }, 0 },
10868   },
10869   {
10870     /* VEX_W_0FDB_P_2 */
10871     { "vpand",          { XM, Vex, EXx }, 0 },
10872   },
10873   {
10874     /* VEX_W_0FDC_P_2 */
10875     { "vpaddusb",       { XM, Vex, EXx }, 0 },
10876   },
10877   {
10878     /* VEX_W_0FDD_P_2 */
10879     { "vpaddusw",       { XM, Vex, EXx }, 0 },
10880   },
10881   {
10882     /* VEX_W_0FDE_P_2 */
10883     { "vpmaxub",        { XM, Vex, EXx }, 0 },
10884   },
10885   {
10886     /* VEX_W_0FDF_P_2 */
10887     { "vpandn",         { XM, Vex, EXx }, 0 },
10888   },
10889   {
10890     /* VEX_W_0FE0_P_2  */
10891     { "vpavgb",         { XM, Vex, EXx }, 0 },
10892   },
10893   {
10894     /* VEX_W_0FE1_P_2  */
10895     { "vpsraw",         { XM, Vex, EXxmm }, 0 },
10896   },
10897   {
10898     /* VEX_W_0FE2_P_2  */
10899     { "vpsrad",         { XM, Vex, EXxmm }, 0 },
10900   },
10901   {
10902     /* VEX_W_0FE3_P_2  */
10903     { "vpavgw",         { XM, Vex, EXx }, 0 },
10904   },
10905   {
10906     /* VEX_W_0FE4_P_2  */
10907     { "vpmulhuw",       { XM, Vex, EXx }, 0 },
10908   },
10909   {
10910     /* VEX_W_0FE5_P_2  */
10911     { "vpmulhw",        { XM, Vex, EXx }, 0 },
10912   },
10913   {
10914     /* VEX_W_0FE6_P_1  */
10915     { "vcvtdq2pd",      { XM, EXxmmq }, 0 },
10916   },
10917   {
10918     /* VEX_W_0FE6_P_2  */
10919     { "vcvttpd2dq%XY",  { XMM, EXx }, 0 },
10920   },
10921   {
10922     /* VEX_W_0FE6_P_3  */
10923     { "vcvtpd2dq%XY",   { XMM, EXx }, 0 },
10924   },
10925   {
10926     /* VEX_W_0FE7_P_2_M_0 */
10927     { "vmovntdq",       { Mx, XM }, 0 },
10928   },
10929   {
10930     /* VEX_W_0FE8_P_2  */
10931     { "vpsubsb",        { XM, Vex, EXx }, 0 },
10932   },
10933   {
10934     /* VEX_W_0FE9_P_2  */
10935     { "vpsubsw",        { XM, Vex, EXx }, 0 },
10936   },
10937   {
10938     /* VEX_W_0FEA_P_2  */
10939     { "vpminsw",        { XM, Vex, EXx }, 0 },
10940   },
10941   {
10942     /* VEX_W_0FEB_P_2  */
10943     { "vpor",           { XM, Vex, EXx }, 0 },
10944   },
10945   {
10946     /* VEX_W_0FEC_P_2  */
10947     { "vpaddsb",        { XM, Vex, EXx }, 0 },
10948   },
10949   {
10950     /* VEX_W_0FED_P_2  */
10951     { "vpaddsw",        { XM, Vex, EXx }, 0 },
10952   },
10953   {
10954     /* VEX_W_0FEE_P_2  */
10955     { "vpmaxsw",        { XM, Vex, EXx }, 0 },
10956   },
10957   {
10958     /* VEX_W_0FEF_P_2  */
10959     { "vpxor",          { XM, Vex, EXx }, 0 },
10960   },
10961   {
10962     /* VEX_W_0FF0_P_3_M_0 */
10963     { "vlddqu",         { XM, M }, 0 },
10964   },
10965   {
10966     /* VEX_W_0FF1_P_2 */
10967     { "vpsllw",         { XM, Vex, EXxmm }, 0 },
10968   },
10969   {
10970     /* VEX_W_0FF2_P_2 */
10971     { "vpslld",         { XM, Vex, EXxmm }, 0 },
10972   },
10973   {
10974     /* VEX_W_0FF3_P_2 */
10975     { "vpsllq",         { XM, Vex, EXxmm }, 0 },
10976   },
10977   {
10978     /* VEX_W_0FF4_P_2 */
10979     { "vpmuludq",       { XM, Vex, EXx }, 0 },
10980   },
10981   {
10982     /* VEX_W_0FF5_P_2 */
10983     { "vpmaddwd",       { XM, Vex, EXx }, 0 },
10984   },
10985   {
10986     /* VEX_W_0FF6_P_2 */
10987     { "vpsadbw",        { XM, Vex, EXx }, 0 },
10988   },
10989   {
10990     /* VEX_W_0FF7_P_2 */
10991     { "vmaskmovdqu",    { XM, XS }, 0 },
10992   },
10993   {
10994     /* VEX_W_0FF8_P_2 */
10995     { "vpsubb",         { XM, Vex, EXx }, 0 },
10996   },
10997   {
10998     /* VEX_W_0FF9_P_2 */
10999     { "vpsubw",         { XM, Vex, EXx }, 0 },
11000   },
11001   {
11002     /* VEX_W_0FFA_P_2 */
11003     { "vpsubd",         { XM, Vex, EXx }, 0 },
11004   },
11005   {
11006     /* VEX_W_0FFB_P_2 */
11007     { "vpsubq",         { XM, Vex, EXx }, 0 },
11008   },
11009   {
11010     /* VEX_W_0FFC_P_2 */
11011     { "vpaddb",         { XM, Vex, EXx }, 0 },
11012   },
11013   {
11014     /* VEX_W_0FFD_P_2 */
11015     { "vpaddw",         { XM, Vex, EXx }, 0 },
11016   },
11017   {
11018     /* VEX_W_0FFE_P_2 */
11019     { "vpaddd",         { XM, Vex, EXx }, 0 },
11020   },
11021   {
11022     /* VEX_W_0F3800_P_2  */
11023     { "vpshufb",        { XM, Vex, EXx }, 0 },
11024   },
11025   {
11026     /* VEX_W_0F3801_P_2  */
11027     { "vphaddw",        { XM, Vex, EXx }, 0 },
11028   },
11029   {
11030     /* VEX_W_0F3802_P_2  */
11031     { "vphaddd",        { XM, Vex, EXx }, 0 },
11032   },
11033   {
11034     /* VEX_W_0F3803_P_2  */
11035     { "vphaddsw",       { XM, Vex, EXx }, 0 },
11036   },
11037   {
11038     /* VEX_W_0F3804_P_2  */
11039     { "vpmaddubsw",     { XM, Vex, EXx }, 0 },
11040   },
11041   {
11042     /* VEX_W_0F3805_P_2  */
11043     { "vphsubw",        { XM, Vex, EXx }, 0 },
11044   },
11045   {
11046     /* VEX_W_0F3806_P_2  */
11047     { "vphsubd",        { XM, Vex, EXx }, 0 },
11048   },
11049   {
11050     /* VEX_W_0F3807_P_2  */
11051     { "vphsubsw",       { XM, Vex, EXx }, 0 },
11052   },
11053   {
11054     /* VEX_W_0F3808_P_2  */
11055     { "vpsignb",        { XM, Vex, EXx }, 0 },
11056   },
11057   {
11058     /* VEX_W_0F3809_P_2  */
11059     { "vpsignw",        { XM, Vex, EXx }, 0 },
11060   },
11061   {
11062     /* VEX_W_0F380A_P_2  */
11063     { "vpsignd",        { XM, Vex, EXx }, 0 },
11064   },
11065   {
11066     /* VEX_W_0F380B_P_2  */
11067     { "vpmulhrsw",      { XM, Vex, EXx }, 0 },
11068   },
11069   {
11070     /* VEX_W_0F380C_P_2  */
11071     { "vpermilps",      { XM, Vex, EXx }, 0 },
11072   },
11073   {
11074     /* VEX_W_0F380D_P_2  */
11075     { "vpermilpd",      { XM, Vex, EXx }, 0 },
11076   },
11077   {
11078     /* VEX_W_0F380E_P_2  */
11079     { "vtestps",        { XM, EXx }, 0 },
11080   },
11081   {
11082     /* VEX_W_0F380F_P_2  */
11083     { "vtestpd",        { XM, EXx }, 0 },
11084   },
11085   {
11086     /* VEX_W_0F3816_P_2  */
11087     { "vpermps",        { XM, Vex, EXx }, 0 },
11088   },
11089   {
11090     /* VEX_W_0F3817_P_2 */
11091     { "vptest",         { XM, EXx }, 0 },
11092   },
11093   {
11094     /* VEX_W_0F3818_P_2 */
11095     { "vbroadcastss",   { XM, EXxmm_md }, 0 },
11096   },
11097   {
11098     /* VEX_W_0F3819_P_2 */
11099     { "vbroadcastsd",   { XM, EXxmm_mq }, 0 },
11100   },
11101   {
11102     /* VEX_W_0F381A_P_2_M_0 */
11103     { "vbroadcastf128", { XM, Mxmm }, 0 },
11104   },
11105   {
11106     /* VEX_W_0F381C_P_2 */
11107     { "vpabsb",         { XM, EXx }, 0 },
11108   },
11109   {
11110     /* VEX_W_0F381D_P_2 */
11111     { "vpabsw",         { XM, EXx }, 0 },
11112   },
11113   {
11114     /* VEX_W_0F381E_P_2 */
11115     { "vpabsd",         { XM, EXx }, 0 },
11116   },
11117   {
11118     /* VEX_W_0F3820_P_2 */
11119     { "vpmovsxbw",      { XM, EXxmmq }, 0 },
11120   },
11121   {
11122     /* VEX_W_0F3821_P_2 */
11123     { "vpmovsxbd",      { XM, EXxmmqd }, 0 },
11124   },
11125   {
11126     /* VEX_W_0F3822_P_2 */
11127     { "vpmovsxbq",      { XM, EXxmmdw }, 0 },
11128   },
11129   {
11130     /* VEX_W_0F3823_P_2 */
11131     { "vpmovsxwd",      { XM, EXxmmq }, 0 },
11132   },
11133   {
11134     /* VEX_W_0F3824_P_2 */
11135     { "vpmovsxwq",      { XM, EXxmmqd }, 0 },
11136   },
11137   {
11138     /* VEX_W_0F3825_P_2 */
11139     { "vpmovsxdq",      { XM, EXxmmq }, 0 },
11140   },
11141   {
11142     /* VEX_W_0F3828_P_2 */
11143     { "vpmuldq",        { XM, Vex, EXx }, 0 },
11144   },
11145   {
11146     /* VEX_W_0F3829_P_2 */
11147     { "vpcmpeqq",       { XM, Vex, EXx }, 0 },
11148   },
11149   {
11150     /* VEX_W_0F382A_P_2_M_0 */
11151     { "vmovntdqa",      { XM, Mx }, 0 },
11152   },
11153   {
11154     /* VEX_W_0F382B_P_2 */
11155     { "vpackusdw",      { XM, Vex, EXx }, 0 },
11156   },
11157   {
11158     /* VEX_W_0F382C_P_2_M_0 */
11159     { "vmaskmovps",     { XM, Vex, Mx }, 0 },
11160   },
11161   {
11162     /* VEX_W_0F382D_P_2_M_0 */
11163     { "vmaskmovpd",     { XM, Vex, Mx }, 0 },
11164   },
11165   {
11166     /* VEX_W_0F382E_P_2_M_0 */
11167     { "vmaskmovps",     { Mx, Vex, XM }, 0 },
11168   },
11169   {
11170     /* VEX_W_0F382F_P_2_M_0 */
11171     { "vmaskmovpd",     { Mx, Vex, XM }, 0 },
11172   },
11173   {
11174     /* VEX_W_0F3830_P_2 */
11175     { "vpmovzxbw",      { XM, EXxmmq }, 0 },
11176   },
11177   {
11178     /* VEX_W_0F3831_P_2 */
11179     { "vpmovzxbd",      { XM, EXxmmqd }, 0 },
11180   },
11181   {
11182     /* VEX_W_0F3832_P_2 */
11183     { "vpmovzxbq",      { XM, EXxmmdw }, 0 },
11184   },
11185   {
11186     /* VEX_W_0F3833_P_2 */
11187     { "vpmovzxwd",      { XM, EXxmmq }, 0 },
11188   },
11189   {
11190     /* VEX_W_0F3834_P_2 */
11191     { "vpmovzxwq",      { XM, EXxmmqd }, 0 },
11192   },
11193   {
11194     /* VEX_W_0F3835_P_2 */
11195     { "vpmovzxdq",      { XM, EXxmmq }, 0 },
11196   },
11197   {
11198     /* VEX_W_0F3836_P_2  */
11199     { "vpermd",         { XM, Vex, EXx }, 0 },
11200   },
11201   {
11202     /* VEX_W_0F3837_P_2 */
11203     { "vpcmpgtq",       { XM, Vex, EXx }, 0 },
11204   },
11205   {
11206     /* VEX_W_0F3838_P_2 */
11207     { "vpminsb",        { XM, Vex, EXx }, 0 },
11208   },
11209   {
11210     /* VEX_W_0F3839_P_2 */
11211     { "vpminsd",        { XM, Vex, EXx }, 0 },
11212   },
11213   {
11214     /* VEX_W_0F383A_P_2 */
11215     { "vpminuw",        { XM, Vex, EXx }, 0 },
11216   },
11217   {
11218     /* VEX_W_0F383B_P_2 */
11219     { "vpminud",        { XM, Vex, EXx }, 0 },
11220   },
11221   {
11222     /* VEX_W_0F383C_P_2 */
11223     { "vpmaxsb",        { XM, Vex, EXx }, 0 },
11224   },
11225   {
11226     /* VEX_W_0F383D_P_2 */
11227     { "vpmaxsd",        { XM, Vex, EXx }, 0 },
11228   },
11229   {
11230     /* VEX_W_0F383E_P_2 */
11231     { "vpmaxuw",        { XM, Vex, EXx }, 0 },
11232   },
11233   {
11234     /* VEX_W_0F383F_P_2 */
11235     { "vpmaxud",        { XM, Vex, EXx }, 0 },
11236   },
11237   {
11238     /* VEX_W_0F3840_P_2 */
11239     { "vpmulld",        { XM, Vex, EXx }, 0 },
11240   },
11241   {
11242     /* VEX_W_0F3841_P_2 */
11243     { "vphminposuw",    { XM, EXx }, 0 },
11244   },
11245   {
11246     /* VEX_W_0F3846_P_2 */
11247     { "vpsravd",        { XM, Vex, EXx }, 0 },
11248   },
11249   {
11250     /* VEX_W_0F3858_P_2 */
11251     { "vpbroadcastd", { XM, EXxmm_md }, 0 },
11252   },
11253   {
11254     /* VEX_W_0F3859_P_2 */
11255     { "vpbroadcastq",   { XM, EXxmm_mq }, 0 },
11256   },
11257   {
11258     /* VEX_W_0F385A_P_2_M_0 */
11259     { "vbroadcasti128", { XM, Mxmm }, 0 },
11260   },
11261   {
11262     /* VEX_W_0F3878_P_2 */
11263     { "vpbroadcastb",   { XM, EXxmm_mb }, 0 },
11264   },
11265   {
11266     /* VEX_W_0F3879_P_2 */
11267     { "vpbroadcastw",   { XM, EXxmm_mw }, 0 },
11268   },
11269   {
11270     /* VEX_W_0F38DB_P_2 */
11271     { "vaesimc",        { XM, EXx }, 0 },
11272   },
11273   {
11274     /* VEX_W_0F38DC_P_2 */
11275     { "vaesenc",        { XM, Vex128, EXx }, 0 },
11276   },
11277   {
11278     /* VEX_W_0F38DD_P_2 */
11279     { "vaesenclast",    { XM, Vex128, EXx }, 0 },
11280   },
11281   {
11282     /* VEX_W_0F38DE_P_2 */
11283     { "vaesdec",        { XM, Vex128, EXx }, 0 },
11284   },
11285   {
11286     /* VEX_W_0F38DF_P_2 */
11287     { "vaesdeclast",    { XM, Vex128, EXx }, 0 },
11288   },
11289   {
11290     /* VEX_W_0F3A00_P_2 */
11291     { Bad_Opcode },
11292     { "vpermq",         { XM, EXx, Ib }, 0 },
11293   },
11294   {
11295     /* VEX_W_0F3A01_P_2 */
11296     { Bad_Opcode },
11297     { "vpermpd",        { XM, EXx, Ib }, 0 },
11298   },
11299   {
11300     /* VEX_W_0F3A02_P_2 */
11301     { "vpblendd",       { XM, Vex, EXx, Ib }, 0 },
11302   },
11303   {
11304     /* VEX_W_0F3A04_P_2 */
11305     { "vpermilps",      { XM, EXx, Ib }, 0 },
11306   },
11307   {
11308     /* VEX_W_0F3A05_P_2 */
11309     { "vpermilpd",      { XM, EXx, Ib }, 0 },
11310   },
11311   {
11312     /* VEX_W_0F3A06_P_2 */
11313     { "vperm2f128",     { XM, Vex256, EXx, Ib }, 0 },
11314   },
11315   {
11316     /* VEX_W_0F3A08_P_2 */
11317     { "vroundps",       { XM, EXx, Ib }, 0 },
11318   },
11319   {
11320     /* VEX_W_0F3A09_P_2 */
11321     { "vroundpd",       { XM, EXx, Ib }, 0 },
11322   },
11323   {
11324     /* VEX_W_0F3A0A_P_2 */
11325     { "vroundss",       { XMScalar, VexScalar, EXdScalar, Ib }, 0 },
11326   },
11327   {
11328     /* VEX_W_0F3A0B_P_2 */
11329     { "vroundsd",       { XMScalar, VexScalar, EXqScalar, Ib }, 0 },
11330   },
11331   {
11332     /* VEX_W_0F3A0C_P_2 */
11333     { "vblendps",       { XM, Vex, EXx, Ib }, 0 },
11334   },
11335   {
11336     /* VEX_W_0F3A0D_P_2 */
11337     { "vblendpd",       { XM, Vex, EXx, Ib }, 0 },
11338   },
11339   {
11340     /* VEX_W_0F3A0E_P_2 */
11341     { "vpblendw",       { XM, Vex, EXx, Ib }, 0 },
11342   },
11343   {
11344     /* VEX_W_0F3A0F_P_2 */
11345     { "vpalignr",       { XM, Vex, EXx, Ib }, 0 },
11346   },
11347   {
11348     /* VEX_W_0F3A14_P_2 */
11349     { "vpextrb",        { Edqb, XM, Ib }, 0 },
11350   },
11351   {
11352     /* VEX_W_0F3A15_P_2 */
11353     { "vpextrw",        { Edqw, XM, Ib }, 0 },
11354   },
11355   {
11356     /* VEX_W_0F3A18_P_2 */
11357     { "vinsertf128",    { XM, Vex256, EXxmm, Ib }, 0 },
11358   },
11359   {
11360     /* VEX_W_0F3A19_P_2 */
11361     { "vextractf128",   { EXxmm, XM, Ib }, 0 },
11362   },
11363   {
11364     /* VEX_W_0F3A20_P_2 */
11365     { "vpinsrb",        { XM, Vex128, Edqb, Ib }, 0 },
11366   },
11367   {
11368     /* VEX_W_0F3A21_P_2 */
11369     { "vinsertps",      { XM, Vex128, EXd, Ib }, 0 },
11370   },
11371   {
11372     /* VEX_W_0F3A30_P_2_LEN_0 */
11373     { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) },
11374     { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) },
11375   },
11376   {
11377     /* VEX_W_0F3A31_P_2_LEN_0 */
11378     { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) },
11379     { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) },
11380   },
11381   {
11382     /* VEX_W_0F3A32_P_2_LEN_0 */
11383     { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) },
11384     { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) },
11385   },
11386   {
11387     /* VEX_W_0F3A33_P_2_LEN_0 */
11388     { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) },
11389     { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) },
11390   },
11391   {
11392     /* VEX_W_0F3A38_P_2 */
11393     { "vinserti128",    { XM, Vex256, EXxmm, Ib }, 0 },
11394   },
11395   {
11396     /* VEX_W_0F3A39_P_2 */
11397     { "vextracti128",   { EXxmm, XM, Ib }, 0 },
11398   },
11399   {
11400     /* VEX_W_0F3A40_P_2 */
11401     { "vdpps",          { XM, Vex, EXx, Ib }, 0 },
11402   },
11403   {
11404     /* VEX_W_0F3A41_P_2 */
11405     { "vdppd",          { XM, Vex128, EXx, Ib }, 0 },
11406   },
11407   {
11408     /* VEX_W_0F3A42_P_2 */
11409     { "vmpsadbw",       { XM, Vex, EXx, Ib }, 0 },
11410   },
11411   {
11412     /* VEX_W_0F3A44_P_2 */
11413     { "vpclmulqdq",     { XM, Vex128, EXx, PCLMUL }, 0 },
11414   },
11415   {
11416     /* VEX_W_0F3A46_P_2 */
11417     { "vperm2i128",     { XM, Vex256, EXx, Ib }, 0 },
11418   },
11419   {
11420     /* VEX_W_0F3A48_P_2 */
11421     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11422     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11423   },
11424   {
11425     /* VEX_W_0F3A49_P_2 */
11426     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11427     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11428   },
11429   {
11430     /* VEX_W_0F3A4A_P_2 */
11431     { "vblendvps",      { XM, Vex, EXx, XMVexI4 }, 0 },
11432   },
11433   {
11434     /* VEX_W_0F3A4B_P_2 */
11435     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 }, 0 },
11436   },
11437   {
11438     /* VEX_W_0F3A4C_P_2 */
11439     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 }, 0 },
11440   },
11441   {
11442     /* VEX_W_0F3A62_P_2 */
11443     { "vpcmpistrm",     { XM, EXx, Ib }, 0 },
11444   },
11445   {
11446     /* VEX_W_0F3A63_P_2 */
11447     { "vpcmpistri",     { XM, EXx, Ib }, 0 },
11448   },
11449   {
11450     /* VEX_W_0F3ADF_P_2 */
11451     { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
11452   },
11453 #define NEED_VEX_W_TABLE
11454 #include "i386-dis-evex.h"
11455 #undef NEED_VEX_W_TABLE
11456 };
11457
11458 static const struct dis386 mod_table[][2] = {
11459   {
11460     /* MOD_8D */
11461     { "leaS",           { Gv, M }, 0 },
11462   },
11463   {
11464     /* MOD_C6_REG_7 */
11465     { Bad_Opcode },
11466     { RM_TABLE (RM_C6_REG_7) },
11467   },
11468   {
11469     /* MOD_C7_REG_7 */
11470     { Bad_Opcode },
11471     { RM_TABLE (RM_C7_REG_7) },
11472   },
11473   {
11474     /* MOD_FF_REG_3 */
11475     { "Jcall^", { indirEp }, 0 },
11476   },
11477   {
11478     /* MOD_FF_REG_5 */
11479     { "Jjmp^", { indirEp }, 0 },
11480   },
11481   {
11482     /* MOD_0F01_REG_0 */
11483     { X86_64_TABLE (X86_64_0F01_REG_0) },
11484     { RM_TABLE (RM_0F01_REG_0) },
11485   },
11486   {
11487     /* MOD_0F01_REG_1 */
11488     { X86_64_TABLE (X86_64_0F01_REG_1) },
11489     { RM_TABLE (RM_0F01_REG_1) },
11490   },
11491   {
11492     /* MOD_0F01_REG_2 */
11493     { X86_64_TABLE (X86_64_0F01_REG_2) },
11494     { RM_TABLE (RM_0F01_REG_2) },
11495   },
11496   {
11497     /* MOD_0F01_REG_3 */
11498     { X86_64_TABLE (X86_64_0F01_REG_3) },
11499     { RM_TABLE (RM_0F01_REG_3) },
11500   },
11501   {
11502     /* MOD_0F01_REG_5 */
11503     { PREFIX_TABLE (PREFIX_MOD_0_0F01_REG_5) },
11504     { RM_TABLE (RM_0F01_REG_5) },
11505   },
11506   {
11507     /* MOD_0F01_REG_7 */
11508     { "invlpg",         { Mb }, 0 },
11509     { RM_TABLE (RM_0F01_REG_7) },
11510   },
11511   {
11512     /* MOD_0F12_PREFIX_0 */
11513     { "movlps",         { XM, EXq }, PREFIX_OPCODE },
11514     { "movhlps",        { XM, EXq }, PREFIX_OPCODE },
11515   },
11516   {
11517     /* MOD_0F13 */
11518     { "movlpX",         { EXq, XM }, PREFIX_OPCODE },
11519   },
11520   {
11521     /* MOD_0F16_PREFIX_0 */
11522     { "movhps",         { XM, EXq }, 0 },
11523     { "movlhps",        { XM, EXq }, 0 },
11524   },
11525   {
11526     /* MOD_0F17 */
11527     { "movhpX",         { EXq, XM }, PREFIX_OPCODE },
11528   },
11529   {
11530     /* MOD_0F18_REG_0 */
11531     { "prefetchnta",    { Mb }, 0 },
11532   },
11533   {
11534     /* MOD_0F18_REG_1 */
11535     { "prefetcht0",     { Mb }, 0 },
11536   },
11537   {
11538     /* MOD_0F18_REG_2 */
11539     { "prefetcht1",     { Mb }, 0 },
11540   },
11541   {
11542     /* MOD_0F18_REG_3 */
11543     { "prefetcht2",     { Mb }, 0 },
11544   },
11545   {
11546     /* MOD_0F18_REG_4 */
11547     { "nop/reserved",   { Mb }, 0 },
11548   },
11549   {
11550     /* MOD_0F18_REG_5 */
11551     { "nop/reserved",   { Mb }, 0 },
11552   },
11553   {
11554     /* MOD_0F18_REG_6 */
11555     { "nop/reserved",   { Mb }, 0 },
11556   },
11557   {
11558     /* MOD_0F18_REG_7 */
11559     { "nop/reserved",   { Mb }, 0 },
11560   },
11561   {
11562     /* MOD_0F1A_PREFIX_0 */
11563     { "bndldx",         { Gbnd, Ev_bnd }, 0 },
11564     { "nopQ",           { Ev }, 0 },
11565   },
11566   {
11567     /* MOD_0F1B_PREFIX_0 */
11568     { "bndstx",         { Ev_bnd, Gbnd }, 0 },
11569     { "nopQ",           { Ev }, 0 },
11570   },
11571   {
11572     /* MOD_0F1B_PREFIX_1 */
11573     { "bndmk",          { Gbnd, Ev_bnd }, 0 },
11574     { "nopQ",           { Ev }, 0 },
11575   },
11576   {
11577     /* MOD_0F1E_PREFIX_1 */
11578     { "nopQ",           { Ev }, 0 },
11579     { REG_TABLE (REG_0F1E_MOD_3) },
11580   },
11581   {
11582     /* MOD_0F24 */
11583     { Bad_Opcode },
11584     { "movL",           { Rd, Td }, 0 },
11585   },
11586   {
11587     /* MOD_0F26 */
11588     { Bad_Opcode },
11589     { "movL",           { Td, Rd }, 0 },
11590   },
11591   {
11592     /* MOD_0F2B_PREFIX_0 */
11593     {"movntps",         { Mx, XM }, PREFIX_OPCODE },
11594   },
11595   {
11596     /* MOD_0F2B_PREFIX_1 */
11597     {"movntss",         { Md, XM }, PREFIX_OPCODE },
11598   },
11599   {
11600     /* MOD_0F2B_PREFIX_2 */
11601     {"movntpd",         { Mx, XM }, PREFIX_OPCODE },
11602   },
11603   {
11604     /* MOD_0F2B_PREFIX_3 */
11605     {"movntsd",         { Mq, XM }, PREFIX_OPCODE },
11606   },
11607   {
11608     /* MOD_0F51 */
11609     { Bad_Opcode },
11610     { "movmskpX",       { Gdq, XS }, PREFIX_OPCODE },
11611   },
11612   {
11613     /* MOD_0F71_REG_2 */
11614     { Bad_Opcode },
11615     { "psrlw",          { MS, Ib }, 0 },
11616   },
11617   {
11618     /* MOD_0F71_REG_4 */
11619     { Bad_Opcode },
11620     { "psraw",          { MS, Ib }, 0 },
11621   },
11622   {
11623     /* MOD_0F71_REG_6 */
11624     { Bad_Opcode },
11625     { "psllw",          { MS, Ib }, 0 },
11626   },
11627   {
11628     /* MOD_0F72_REG_2 */
11629     { Bad_Opcode },
11630     { "psrld",          { MS, Ib }, 0 },
11631   },
11632   {
11633     /* MOD_0F72_REG_4 */
11634     { Bad_Opcode },
11635     { "psrad",          { MS, Ib }, 0 },
11636   },
11637   {
11638     /* MOD_0F72_REG_6 */
11639     { Bad_Opcode },
11640     { "pslld",          { MS, Ib }, 0 },
11641   },
11642   {
11643     /* MOD_0F73_REG_2 */
11644     { Bad_Opcode },
11645     { "psrlq",          { MS, Ib }, 0 },
11646   },
11647   {
11648     /* MOD_0F73_REG_3 */
11649     { Bad_Opcode },
11650     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
11651   },
11652   {
11653     /* MOD_0F73_REG_6 */
11654     { Bad_Opcode },
11655     { "psllq",          { MS, Ib }, 0 },
11656   },
11657   {
11658     /* MOD_0F73_REG_7 */
11659     { Bad_Opcode },
11660     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
11661   },
11662   {
11663     /* MOD_0FAE_REG_0 */
11664     { "fxsave",         { FXSAVE }, 0 },
11665     { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
11666   },
11667   {
11668     /* MOD_0FAE_REG_1 */
11669     { "fxrstor",        { FXSAVE }, 0 },
11670     { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
11671   },
11672   {
11673     /* MOD_0FAE_REG_2 */
11674     { "ldmxcsr",        { Md }, 0 },
11675     { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
11676   },
11677   {
11678     /* MOD_0FAE_REG_3 */
11679     { "stmxcsr",        { Md }, 0 },
11680     { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
11681   },
11682   {
11683     /* MOD_0FAE_REG_4 */
11684     { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_4) },
11685     { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_4) },
11686   },
11687   {
11688     /* MOD_0FAE_REG_5 */
11689     { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_5) },
11690     { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_5) },
11691   },
11692   {
11693     /* MOD_0FAE_REG_6 */
11694     { PREFIX_TABLE (PREFIX_0FAE_REG_6) },
11695     { RM_TABLE (RM_0FAE_REG_6) },
11696   },
11697   {
11698     /* MOD_0FAE_REG_7 */
11699     { PREFIX_TABLE (PREFIX_0FAE_REG_7) },
11700     { RM_TABLE (RM_0FAE_REG_7) },
11701   },
11702   {
11703     /* MOD_0FB2 */
11704     { "lssS",           { Gv, Mp }, 0 },
11705   },
11706   {
11707     /* MOD_0FB4 */
11708     { "lfsS",           { Gv, Mp }, 0 },
11709   },
11710   {
11711     /* MOD_0FB5 */
11712     { "lgsS",           { Gv, Mp }, 0 },
11713   },
11714   {
11715     /* MOD_0FC3 */
11716     { PREFIX_TABLE (PREFIX_MOD_0_0FC3) },
11717   },
11718   {
11719     /* MOD_0FC7_REG_3 */
11720     { "xrstors",        { FXSAVE }, 0 },
11721   },
11722   {
11723     /* MOD_0FC7_REG_4 */
11724     { "xsavec",         { FXSAVE }, 0 },
11725   },
11726   {
11727     /* MOD_0FC7_REG_5 */
11728     { "xsaves",         { FXSAVE }, 0 },
11729   },
11730   {
11731     /* MOD_0FC7_REG_6 */
11732     { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6) },
11733     { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6) }
11734   },
11735   {
11736     /* MOD_0FC7_REG_7 */
11737     { "vmptrst",        { Mq }, 0 },
11738     { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7) }
11739   },
11740   {
11741     /* MOD_0FD7 */
11742     { Bad_Opcode },
11743     { "pmovmskb",       { Gdq, MS }, 0 },
11744   },
11745   {
11746     /* MOD_0FE7_PREFIX_2 */
11747     { "movntdq",        { Mx, XM }, 0 },
11748   },
11749   {
11750     /* MOD_0FF0_PREFIX_3 */
11751     { "lddqu",          { XM, M }, 0 },
11752   },
11753   {
11754     /* MOD_0F382A_PREFIX_2 */
11755     { "movntdqa",       { XM, Mx }, 0 },
11756   },
11757   {
11758     /* MOD_0F38F5_PREFIX_2 */
11759     { "wrussK",         { M, Gdq }, PREFIX_OPCODE },
11760   },
11761   {
11762     /* MOD_0F38F6_PREFIX_0 */
11763     { "wrssK",          { M, Gdq }, PREFIX_OPCODE },
11764   },
11765   {
11766     /* MOD_62_32BIT */
11767     { "bound{S|}",      { Gv, Ma }, 0 },
11768     { EVEX_TABLE (EVEX_0F) },
11769   },
11770   {
11771     /* MOD_C4_32BIT */
11772     { "lesS",           { Gv, Mp }, 0 },
11773     { VEX_C4_TABLE (VEX_0F) },
11774   },
11775   {
11776     /* MOD_C5_32BIT */
11777     { "ldsS",           { Gv, Mp }, 0 },
11778     { VEX_C5_TABLE (VEX_0F) },
11779   },
11780   {
11781     /* MOD_VEX_0F12_PREFIX_0 */
11782     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
11783     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
11784   },
11785   {
11786     /* MOD_VEX_0F13 */
11787     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
11788   },
11789   {
11790     /* MOD_VEX_0F16_PREFIX_0 */
11791     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
11792     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
11793   },
11794   {
11795     /* MOD_VEX_0F17 */
11796     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
11797   },
11798   {
11799     /* MOD_VEX_0F2B */
11800     { VEX_W_TABLE (VEX_W_0F2B_M_0) },
11801   },
11802   {
11803     /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
11804     { Bad_Opcode },
11805     { "kandw",          { MaskG, MaskVex, MaskR }, 0 },
11806   },
11807   {
11808     /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
11809     { Bad_Opcode },
11810     { "kandq",          { MaskG, MaskVex, MaskR }, 0 },
11811   },
11812   {
11813     /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
11814     { Bad_Opcode },
11815     { "kandb",          { MaskG, MaskVex, MaskR }, 0 },
11816   },
11817   {
11818     /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
11819     { Bad_Opcode },
11820     { "kandd",          { MaskG, MaskVex, MaskR }, 0 },
11821   },
11822   {
11823     /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
11824     { Bad_Opcode },
11825     { "kandnw",         { MaskG, MaskVex, MaskR }, 0 },
11826   },
11827   {
11828     /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
11829     { Bad_Opcode },
11830     { "kandnq",         { MaskG, MaskVex, MaskR }, 0 },
11831   },
11832   {
11833     /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
11834     { Bad_Opcode },
11835     { "kandnb",         { MaskG, MaskVex, MaskR }, 0 },
11836   },
11837   {
11838     /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
11839     { Bad_Opcode },
11840     { "kandnd",         { MaskG, MaskVex, MaskR }, 0 },
11841   },
11842   {
11843     /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
11844     { Bad_Opcode },
11845     { "knotw",          { MaskG, MaskR }, 0 },
11846   },
11847   {
11848     /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
11849     { Bad_Opcode },
11850     { "knotq",          { MaskG, MaskR }, 0 },
11851   },
11852   {
11853     /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
11854     { Bad_Opcode },
11855     { "knotb",          { MaskG, MaskR }, 0 },
11856   },
11857   {
11858     /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
11859     { Bad_Opcode },
11860     { "knotd",          { MaskG, MaskR }, 0 },
11861   },
11862   {
11863     /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
11864     { Bad_Opcode },
11865     { "korw",       { MaskG, MaskVex, MaskR }, 0 },
11866   },
11867   {
11868     /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
11869     { Bad_Opcode },
11870     { "korq",       { MaskG, MaskVex, MaskR }, 0 },
11871   },
11872   {
11873     /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
11874     { Bad_Opcode },
11875     { "korb",       { MaskG, MaskVex, MaskR }, 0 },
11876   },
11877   {
11878     /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
11879     { Bad_Opcode },
11880     { "kord",       { MaskG, MaskVex, MaskR }, 0 },
11881   },
11882  {
11883     /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
11884     { Bad_Opcode },
11885     { "kxnorw",     { MaskG, MaskVex, MaskR }, 0 },
11886   },
11887   {
11888     /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
11889     { Bad_Opcode },
11890     { "kxnorq",     { MaskG, MaskVex, MaskR }, 0 },
11891   },
11892   {
11893     /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
11894     { Bad_Opcode },
11895     { "kxnorb",     { MaskG, MaskVex, MaskR }, 0 },
11896   },
11897   {
11898     /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
11899     { Bad_Opcode },
11900     { "kxnord",     { MaskG, MaskVex, MaskR }, 0 },
11901   },
11902   {
11903     /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
11904     { Bad_Opcode },
11905     { "kxorw",      { MaskG, MaskVex, MaskR }, 0 },
11906   },
11907   {
11908     /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
11909     { Bad_Opcode },
11910     { "kxorq",      { MaskG, MaskVex, MaskR }, 0 },
11911   },
11912   {
11913     /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
11914     { Bad_Opcode },
11915     { "kxorb",      { MaskG, MaskVex, MaskR }, 0 },
11916   },
11917   {
11918     /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
11919     { Bad_Opcode },
11920     { "kxord",      { MaskG, MaskVex, MaskR }, 0 },
11921   },
11922   {
11923     /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
11924     { Bad_Opcode },
11925     { "kaddw",          { MaskG, MaskVex, MaskR }, 0 },
11926   },
11927   {
11928     /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
11929     { Bad_Opcode },
11930     { "kaddq",          { MaskG, MaskVex, MaskR }, 0 },
11931   },
11932   {
11933     /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
11934     { Bad_Opcode },
11935     { "kaddb",          { MaskG, MaskVex, MaskR }, 0 },
11936   },
11937   {
11938     /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
11939     { Bad_Opcode },
11940     { "kaddd",          { MaskG, MaskVex, MaskR }, 0 },
11941   },
11942   {
11943     /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
11944     { Bad_Opcode },
11945     { "kunpckwd",   { MaskG, MaskVex, MaskR }, 0 },
11946   },
11947   {
11948     /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
11949     { Bad_Opcode },
11950     { "kunpckdq",   { MaskG, MaskVex, MaskR }, 0 },
11951   },
11952   {
11953     /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
11954     { Bad_Opcode },
11955     { "kunpckbw",   { MaskG, MaskVex, MaskR }, 0 },
11956   },
11957   {
11958     /* MOD_VEX_0F50 */
11959     { Bad_Opcode },
11960     { VEX_W_TABLE (VEX_W_0F50_M_0) },
11961   },
11962   {
11963     /* MOD_VEX_0F71_REG_2 */
11964     { Bad_Opcode },
11965     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
11966   },
11967   {
11968     /* MOD_VEX_0F71_REG_4 */
11969     { Bad_Opcode },
11970     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
11971   },
11972   {
11973     /* MOD_VEX_0F71_REG_6 */
11974     { Bad_Opcode },
11975     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
11976   },
11977   {
11978     /* MOD_VEX_0F72_REG_2 */
11979     { Bad_Opcode },
11980     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
11981   },
11982   {
11983     /* MOD_VEX_0F72_REG_4 */
11984     { Bad_Opcode },
11985     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
11986   },
11987   {
11988     /* MOD_VEX_0F72_REG_6 */
11989     { Bad_Opcode },
11990     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
11991   },
11992   {
11993     /* MOD_VEX_0F73_REG_2 */
11994     { Bad_Opcode },
11995     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
11996   },
11997   {
11998     /* MOD_VEX_0F73_REG_3 */
11999     { Bad_Opcode },
12000     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
12001   },
12002   {
12003     /* MOD_VEX_0F73_REG_6 */
12004     { Bad_Opcode },
12005     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
12006   },
12007   {
12008     /* MOD_VEX_0F73_REG_7 */
12009     { Bad_Opcode },
12010     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
12011   },
12012   {
12013     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
12014     { "kmovw",          { Ew, MaskG }, 0 },
12015     { Bad_Opcode },
12016   },
12017   {
12018     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
12019     { "kmovq",          { Eq, MaskG }, 0 },
12020     { Bad_Opcode },
12021   },
12022   {
12023     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
12024     { "kmovb",          { Eb, MaskG }, 0 },
12025     { Bad_Opcode },
12026   },
12027   {
12028     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
12029     { "kmovd",          { Ed, MaskG }, 0 },
12030     { Bad_Opcode },
12031   },
12032   {
12033     /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
12034     { Bad_Opcode },
12035     { "kmovw",          { MaskG, Rdq }, 0 },
12036   },
12037   {
12038     /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
12039     { Bad_Opcode },
12040     { "kmovb",          { MaskG, Rdq }, 0 },
12041   },
12042   {
12043     /* MOD_VEX_W_0_0F92_P_3_LEN_0 */
12044     { Bad_Opcode },
12045     { "kmovd",          { MaskG, Rdq }, 0 },
12046   },
12047   {
12048     /* MOD_VEX_W_1_0F92_P_3_LEN_0 */
12049     { Bad_Opcode },
12050     { "kmovq",          { MaskG, Rdq }, 0 },
12051   },
12052   {
12053     /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
12054     { Bad_Opcode },
12055     { "kmovw",          { Gdq, MaskR }, 0 },
12056   },
12057   {
12058     /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
12059     { Bad_Opcode },
12060     { "kmovb",          { Gdq, MaskR }, 0 },
12061   },
12062   {
12063     /* MOD_VEX_W_0_0F93_P_3_LEN_0 */
12064     { Bad_Opcode },
12065     { "kmovd",          { Gdq, MaskR }, 0 },
12066   },
12067   {
12068     /* MOD_VEX_W_1_0F93_P_3_LEN_0 */
12069     { Bad_Opcode },
12070     { "kmovq",          { Gdq, MaskR }, 0 },
12071   },
12072   {
12073     /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
12074     { Bad_Opcode },
12075     { "kortestw", { MaskG, MaskR }, 0 },
12076   },
12077   {
12078     /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
12079     { Bad_Opcode },
12080     { "kortestq", { MaskG, MaskR }, 0 },
12081   },
12082   {
12083     /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
12084     { Bad_Opcode },
12085     { "kortestb", { MaskG, MaskR }, 0 },
12086   },
12087   {
12088     /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
12089     { Bad_Opcode },
12090     { "kortestd", { MaskG, MaskR }, 0 },
12091   },
12092   {
12093     /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
12094     { Bad_Opcode },
12095     { "ktestw", { MaskG, MaskR }, 0 },
12096   },
12097   {
12098     /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
12099     { Bad_Opcode },
12100     { "ktestq", { MaskG, MaskR }, 0 },
12101   },
12102   {
12103     /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
12104     { Bad_Opcode },
12105     { "ktestb", { MaskG, MaskR }, 0 },
12106   },
12107   {
12108     /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
12109     { Bad_Opcode },
12110     { "ktestd", { MaskG, MaskR }, 0 },
12111   },
12112   {
12113     /* MOD_VEX_0FAE_REG_2 */
12114     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
12115   },
12116   {
12117     /* MOD_VEX_0FAE_REG_3 */
12118     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
12119   },
12120   {
12121     /* MOD_VEX_0FD7_PREFIX_2 */
12122     { Bad_Opcode },
12123     { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) },
12124   },
12125   {
12126     /* MOD_VEX_0FE7_PREFIX_2 */
12127     { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) },
12128   },
12129   {
12130     /* MOD_VEX_0FF0_PREFIX_3 */
12131     { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) },
12132   },
12133   {
12134     /* MOD_VEX_0F381A_PREFIX_2 */
12135     { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
12136   },
12137   {
12138     /* MOD_VEX_0F382A_PREFIX_2 */
12139     { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) },
12140   },
12141   {
12142     /* MOD_VEX_0F382C_PREFIX_2 */
12143     { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
12144   },
12145   {
12146     /* MOD_VEX_0F382D_PREFIX_2 */
12147     { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
12148   },
12149   {
12150     /* MOD_VEX_0F382E_PREFIX_2 */
12151     { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
12152   },
12153   {
12154     /* MOD_VEX_0F382F_PREFIX_2 */
12155     { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
12156   },
12157   {
12158     /* MOD_VEX_0F385A_PREFIX_2 */
12159     { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
12160   },
12161   {
12162     /* MOD_VEX_0F388C_PREFIX_2 */
12163     { "vpmaskmov%LW",   { XM, Vex, Mx }, 0 },
12164   },
12165   {
12166     /* MOD_VEX_0F388E_PREFIX_2 */
12167     { "vpmaskmov%LW",   { Mx, Vex, XM }, 0 },
12168   },
12169   {
12170     /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
12171     { Bad_Opcode },
12172     { "kshiftrb",       { MaskG, MaskR, Ib }, 0 },
12173   },
12174   {
12175     /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
12176     { Bad_Opcode },
12177     { "kshiftrw",       { MaskG, MaskR, Ib }, 0 },
12178   },
12179   {
12180     /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
12181     { Bad_Opcode },
12182     { "kshiftrd",       { MaskG, MaskR, Ib }, 0 },
12183   },
12184   {
12185     /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
12186     { Bad_Opcode },
12187     { "kshiftrq",       { MaskG, MaskR, Ib }, 0 },
12188   },
12189   {
12190     /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
12191     { Bad_Opcode },
12192     { "kshiftlb",       { MaskG, MaskR, Ib }, 0 },
12193   },
12194   {
12195     /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
12196     { Bad_Opcode },
12197     { "kshiftlw",       { MaskG, MaskR, Ib }, 0 },
12198   },
12199   {
12200     /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
12201     { Bad_Opcode },
12202     { "kshiftld",       { MaskG, MaskR, Ib }, 0 },
12203   },
12204   {
12205     /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
12206     { Bad_Opcode },
12207     { "kshiftlq",       { MaskG, MaskR, Ib }, 0 },
12208   },
12209 #define NEED_MOD_TABLE
12210 #include "i386-dis-evex.h"
12211 #undef NEED_MOD_TABLE
12212 };
12213
12214 static const struct dis386 rm_table[][8] = {
12215   {
12216     /* RM_C6_REG_7 */
12217     { "xabort",         { Skip_MODRM, Ib }, 0 },
12218   },
12219   {
12220     /* RM_C7_REG_7 */
12221     { "xbeginT",        { Skip_MODRM, Jv }, 0 },
12222   },
12223   {
12224     /* RM_0F01_REG_0 */
12225     { Bad_Opcode },
12226     { "vmcall",         { Skip_MODRM }, 0 },
12227     { "vmlaunch",       { Skip_MODRM }, 0 },
12228     { "vmresume",       { Skip_MODRM }, 0 },
12229     { "vmxoff",         { Skip_MODRM }, 0 },
12230   },
12231   {
12232     /* RM_0F01_REG_1 */
12233     { "monitor",        { { OP_Monitor, 0 } }, 0 },
12234     { "mwait",          { { OP_Mwait, 0 } }, 0 },
12235     { "clac",           { Skip_MODRM }, 0 },
12236     { "stac",           { Skip_MODRM }, 0 },
12237     { Bad_Opcode },
12238     { Bad_Opcode },
12239     { Bad_Opcode },
12240     { "encls",          { Skip_MODRM }, 0 },
12241   },
12242   {
12243     /* RM_0F01_REG_2 */
12244     { "xgetbv",         { Skip_MODRM }, 0 },
12245     { "xsetbv",         { Skip_MODRM }, 0 },
12246     { Bad_Opcode },
12247     { Bad_Opcode },
12248     { "vmfunc",         { Skip_MODRM }, 0 },
12249     { "xend",           { Skip_MODRM }, 0 },
12250     { "xtest",          { Skip_MODRM }, 0 },
12251     { "enclu",          { Skip_MODRM }, 0 },
12252   },
12253   {
12254     /* RM_0F01_REG_3 */
12255     { "vmrun",          { Skip_MODRM }, 0 },
12256     { "vmmcall",        { Skip_MODRM }, 0 },
12257     { "vmload",         { Skip_MODRM }, 0 },
12258     { "vmsave",         { Skip_MODRM }, 0 },
12259     { "stgi",           { Skip_MODRM }, 0 },
12260     { "clgi",           { Skip_MODRM }, 0 },
12261     { "skinit",         { Skip_MODRM }, 0 },
12262     { "invlpga",        { Skip_MODRM }, 0 },
12263   },
12264   {
12265     /* RM_0F01_REG_5 */
12266     { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_0) },
12267     { Bad_Opcode },
12268     { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_2) },
12269     { Bad_Opcode },
12270     { Bad_Opcode },
12271     { Bad_Opcode },
12272     { "rdpkru",         { Skip_MODRM }, 0 },
12273     { "wrpkru",         { Skip_MODRM }, 0 },
12274   },
12275   {
12276     /* RM_0F01_REG_7 */
12277     { "swapgs",         { Skip_MODRM }, 0  },
12278     { "rdtscp",         { Skip_MODRM }, 0  },
12279     { "monitorx",       { { OP_Monitor, 0 } }, 0  },
12280     { "mwaitx",         { { OP_Mwaitx,  0 } }, 0  },
12281     { "clzero",         { Skip_MODRM }, 0  },
12282   },
12283   {
12284     /* RM_0F1E_MOD_3_REG_7 */
12285     { "nopQ",           { Ev }, 0 },
12286     { "nopQ",           { Ev }, 0 },
12287     { "endbr64",        { Skip_MODRM },  PREFIX_OPCODE },
12288     { "endbr32",        { Skip_MODRM },  PREFIX_OPCODE },
12289     { "nopQ",           { Ev }, 0 },
12290     { "nopQ",           { Ev }, 0 },
12291     { "nopQ",           { Ev }, 0 },
12292     { "nopQ",           { Ev }, 0 },
12293   },
12294   {
12295     /* RM_0FAE_REG_6 */
12296     { "mfence",         { Skip_MODRM }, 0 },
12297   },
12298   {
12299     /* RM_0FAE_REG_7 */
12300     { "sfence",         { Skip_MODRM }, 0 },
12301
12302   },
12303 };
12304
12305 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
12306
12307 /* We use the high bit to indicate different name for the same
12308    prefix.  */
12309 #define REP_PREFIX      (0xf3 | 0x100)
12310 #define XACQUIRE_PREFIX (0xf2 | 0x200)
12311 #define XRELEASE_PREFIX (0xf3 | 0x400)
12312 #define BND_PREFIX      (0xf2 | 0x400)
12313 #define NOTRACK_PREFIX  (0x3e | 0x100)
12314
12315 static int
12316 ckprefix (void)
12317 {
12318   int newrex, i, length;
12319   rex = 0;
12320   rex_ignored = 0;
12321   prefixes = 0;
12322   used_prefixes = 0;
12323   rex_used = 0;
12324   last_lock_prefix = -1;
12325   last_repz_prefix = -1;
12326   last_repnz_prefix = -1;
12327   last_data_prefix = -1;
12328   last_addr_prefix = -1;
12329   last_rex_prefix = -1;
12330   last_seg_prefix = -1;
12331   fwait_prefix = -1;
12332   active_seg_prefix = 0;
12333   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12334     all_prefixes[i] = 0;
12335   i = 0;
12336   length = 0;
12337   /* The maximum instruction length is 15bytes.  */
12338   while (length < MAX_CODE_LENGTH - 1)
12339     {
12340       FETCH_DATA (the_info, codep + 1);
12341       newrex = 0;
12342       switch (*codep)
12343         {
12344         /* REX prefixes family.  */
12345         case 0x40:
12346         case 0x41:
12347         case 0x42:
12348         case 0x43:
12349         case 0x44:
12350         case 0x45:
12351         case 0x46:
12352         case 0x47:
12353         case 0x48:
12354         case 0x49:
12355         case 0x4a:
12356         case 0x4b:
12357         case 0x4c:
12358         case 0x4d:
12359         case 0x4e:
12360         case 0x4f:
12361           if (address_mode == mode_64bit)
12362             newrex = *codep;
12363           else
12364             return 1;
12365           last_rex_prefix = i;
12366           break;
12367         case 0xf3:
12368           prefixes |= PREFIX_REPZ;
12369           last_repz_prefix = i;
12370           break;
12371         case 0xf2:
12372           prefixes |= PREFIX_REPNZ;
12373           last_repnz_prefix = i;
12374           break;
12375         case 0xf0:
12376           prefixes |= PREFIX_LOCK;
12377           last_lock_prefix = i;
12378           break;
12379         case 0x2e:
12380           prefixes |= PREFIX_CS;
12381           last_seg_prefix = i;
12382           active_seg_prefix = PREFIX_CS;
12383           break;
12384         case 0x36:
12385           prefixes |= PREFIX_SS;
12386           last_seg_prefix = i;
12387           active_seg_prefix = PREFIX_SS;
12388           break;
12389         case 0x3e:
12390           prefixes |= PREFIX_DS;
12391           last_seg_prefix = i;
12392           active_seg_prefix = PREFIX_DS;
12393           break;
12394         case 0x26:
12395           prefixes |= PREFIX_ES;
12396           last_seg_prefix = i;
12397           active_seg_prefix = PREFIX_ES;
12398           break;
12399         case 0x64:
12400           prefixes |= PREFIX_FS;
12401           last_seg_prefix = i;
12402           active_seg_prefix = PREFIX_FS;
12403           break;
12404         case 0x65:
12405           prefixes |= PREFIX_GS;
12406           last_seg_prefix = i;
12407           active_seg_prefix = PREFIX_GS;
12408           break;
12409         case 0x66:
12410           prefixes |= PREFIX_DATA;
12411           last_data_prefix = i;
12412           break;
12413         case 0x67:
12414           prefixes |= PREFIX_ADDR;
12415           last_addr_prefix = i;
12416           break;
12417         case FWAIT_OPCODE:
12418           /* fwait is really an instruction.  If there are prefixes
12419              before the fwait, they belong to the fwait, *not* to the
12420              following instruction.  */
12421           fwait_prefix = i;
12422           if (prefixes || rex)
12423             {
12424               prefixes |= PREFIX_FWAIT;
12425               codep++;
12426               /* This ensures that the previous REX prefixes are noticed
12427                  as unused prefixes, as in the return case below.  */
12428               rex_used = rex;
12429               return 1;
12430             }
12431           prefixes = PREFIX_FWAIT;
12432           break;
12433         default:
12434           return 1;
12435         }
12436       /* Rex is ignored when followed by another prefix.  */
12437       if (rex)
12438         {
12439           rex_used = rex;
12440           return 1;
12441         }
12442       if (*codep != FWAIT_OPCODE)
12443         all_prefixes[i++] = *codep;
12444       rex = newrex;
12445       codep++;
12446       length++;
12447     }
12448   return 0;
12449 }
12450
12451 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
12452    prefix byte.  */
12453
12454 static const char *
12455 prefix_name (int pref, int sizeflag)
12456 {
12457   static const char *rexes [16] =
12458     {
12459       "rex",            /* 0x40 */
12460       "rex.B",          /* 0x41 */
12461       "rex.X",          /* 0x42 */
12462       "rex.XB",         /* 0x43 */
12463       "rex.R",          /* 0x44 */
12464       "rex.RB",         /* 0x45 */
12465       "rex.RX",         /* 0x46 */
12466       "rex.RXB",        /* 0x47 */
12467       "rex.W",          /* 0x48 */
12468       "rex.WB",         /* 0x49 */
12469       "rex.WX",         /* 0x4a */
12470       "rex.WXB",        /* 0x4b */
12471       "rex.WR",         /* 0x4c */
12472       "rex.WRB",        /* 0x4d */
12473       "rex.WRX",        /* 0x4e */
12474       "rex.WRXB",       /* 0x4f */
12475     };
12476
12477   switch (pref)
12478     {
12479     /* REX prefixes family.  */
12480     case 0x40:
12481     case 0x41:
12482     case 0x42:
12483     case 0x43:
12484     case 0x44:
12485     case 0x45:
12486     case 0x46:
12487     case 0x47:
12488     case 0x48:
12489     case 0x49:
12490     case 0x4a:
12491     case 0x4b:
12492     case 0x4c:
12493     case 0x4d:
12494     case 0x4e:
12495     case 0x4f:
12496       return rexes [pref - 0x40];
12497     case 0xf3:
12498       return "repz";
12499     case 0xf2:
12500       return "repnz";
12501     case 0xf0:
12502       return "lock";
12503     case 0x2e:
12504       return "cs";
12505     case 0x36:
12506       return "ss";
12507     case 0x3e:
12508       return "ds";
12509     case 0x26:
12510       return "es";
12511     case 0x64:
12512       return "fs";
12513     case 0x65:
12514       return "gs";
12515     case 0x66:
12516       return (sizeflag & DFLAG) ? "data16" : "data32";
12517     case 0x67:
12518       if (address_mode == mode_64bit)
12519         return (sizeflag & AFLAG) ? "addr32" : "addr64";
12520       else
12521         return (sizeflag & AFLAG) ? "addr16" : "addr32";
12522     case FWAIT_OPCODE:
12523       return "fwait";
12524     case REP_PREFIX:
12525       return "rep";
12526     case XACQUIRE_PREFIX:
12527       return "xacquire";
12528     case XRELEASE_PREFIX:
12529       return "xrelease";
12530     case BND_PREFIX:
12531       return "bnd";
12532     case NOTRACK_PREFIX:
12533       return "notrack";
12534     default:
12535       return NULL;
12536     }
12537 }
12538
12539 static char op_out[MAX_OPERANDS][100];
12540 static int op_ad, op_index[MAX_OPERANDS];
12541 static int two_source_ops;
12542 static bfd_vma op_address[MAX_OPERANDS];
12543 static bfd_vma op_riprel[MAX_OPERANDS];
12544 static bfd_vma start_pc;
12545
12546 /*
12547  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
12548  *   (see topic "Redundant prefixes" in the "Differences from 8086"
12549  *   section of the "Virtual 8086 Mode" chapter.)
12550  * 'pc' should be the address of this instruction, it will
12551  *   be used to print the target address if this is a relative jump or call
12552  * The function returns the length of this instruction in bytes.
12553  */
12554
12555 static char intel_syntax;
12556 static char intel_mnemonic = !SYSV386_COMPAT;
12557 static char open_char;
12558 static char close_char;
12559 static char separator_char;
12560 static char scale_char;
12561
12562 enum x86_64_isa
12563 {
12564   amd64 = 0,
12565   intel64
12566 };
12567
12568 static enum x86_64_isa isa64;
12569
12570 /* Here for backwards compatibility.  When gdb stops using
12571    print_insn_i386_att and print_insn_i386_intel these functions can
12572    disappear, and print_insn_i386 be merged into print_insn.  */
12573 int
12574 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
12575 {
12576   intel_syntax = 0;
12577
12578   return print_insn (pc, info);
12579 }
12580
12581 int
12582 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
12583 {
12584   intel_syntax = 1;
12585
12586   return print_insn (pc, info);
12587 }
12588
12589 int
12590 print_insn_i386 (bfd_vma pc, disassemble_info *info)
12591 {
12592   intel_syntax = -1;
12593
12594   return print_insn (pc, info);
12595 }
12596
12597 void
12598 print_i386_disassembler_options (FILE *stream)
12599 {
12600   fprintf (stream, _("\n\
12601 The following i386/x86-64 specific disassembler options are supported for use\n\
12602 with the -M switch (multiple options should be separated by commas):\n"));
12603
12604   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
12605   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
12606   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
12607   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
12608   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
12609   fprintf (stream, _("  att-mnemonic\n"
12610                      "              Display instruction in AT&T mnemonic\n"));
12611   fprintf (stream, _("  intel-mnemonic\n"
12612                      "              Display instruction in Intel mnemonic\n"));
12613   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
12614   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
12615   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
12616   fprintf (stream, _("  data32      Assume 32bit data size\n"));
12617   fprintf (stream, _("  data16      Assume 16bit data size\n"));
12618   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
12619   fprintf (stream, _("  amd64       Display instruction in AMD64 ISA\n"));
12620   fprintf (stream, _("  intel64     Display instruction in Intel64 ISA\n"));
12621 }
12622
12623 /* Bad opcode.  */
12624 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
12625
12626 /* Get a pointer to struct dis386 with a valid name.  */
12627
12628 static const struct dis386 *
12629 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
12630 {
12631   int vindex, vex_table_index;
12632
12633   if (dp->name != NULL)
12634     return dp;
12635
12636   switch (dp->op[0].bytemode)
12637     {
12638     case USE_REG_TABLE:
12639       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
12640       break;
12641
12642     case USE_MOD_TABLE:
12643       vindex = modrm.mod == 0x3 ? 1 : 0;
12644       dp = &mod_table[dp->op[1].bytemode][vindex];
12645       break;
12646
12647     case USE_RM_TABLE:
12648       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
12649       break;
12650
12651     case USE_PREFIX_TABLE:
12652       if (need_vex)
12653         {
12654           /* The prefix in VEX is implicit.  */
12655           switch (vex.prefix)
12656             {
12657             case 0:
12658               vindex = 0;
12659               break;
12660             case REPE_PREFIX_OPCODE:
12661               vindex = 1;
12662               break;
12663             case DATA_PREFIX_OPCODE:
12664               vindex = 2;
12665               break;
12666             case REPNE_PREFIX_OPCODE:
12667               vindex = 3;
12668               break;
12669             default:
12670               abort ();
12671               break;
12672             }
12673         }
12674       else
12675         {
12676           int last_prefix = -1;
12677           int prefix = 0;
12678           vindex = 0;
12679           /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
12680              When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
12681              last one wins.  */
12682           if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
12683             {
12684               if (last_repz_prefix > last_repnz_prefix)
12685                 {
12686                   vindex = 1;
12687                   prefix = PREFIX_REPZ;
12688                   last_prefix = last_repz_prefix;
12689                 }
12690               else
12691                 {
12692                   vindex = 3;
12693                   prefix = PREFIX_REPNZ;
12694                   last_prefix = last_repnz_prefix;
12695                 }
12696
12697               /* Check if prefix should be ignored.  */
12698               if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
12699                      & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
12700                    & prefix) != 0)
12701                 vindex = 0;
12702             }
12703
12704           if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
12705             {
12706               vindex = 2;
12707               prefix = PREFIX_DATA;
12708               last_prefix = last_data_prefix;
12709             }
12710
12711           if (vindex != 0)
12712             {
12713               used_prefixes |= prefix;
12714               all_prefixes[last_prefix] = 0;
12715             }
12716         }
12717       dp = &prefix_table[dp->op[1].bytemode][vindex];
12718       break;
12719
12720     case USE_X86_64_TABLE:
12721       vindex = address_mode == mode_64bit ? 1 : 0;
12722       dp = &x86_64_table[dp->op[1].bytemode][vindex];
12723       break;
12724
12725     case USE_3BYTE_TABLE:
12726       FETCH_DATA (info, codep + 2);
12727       vindex = *codep++;
12728       dp = &three_byte_table[dp->op[1].bytemode][vindex];
12729       end_codep = codep;
12730       modrm.mod = (*codep >> 6) & 3;
12731       modrm.reg = (*codep >> 3) & 7;
12732       modrm.rm = *codep & 7;
12733       break;
12734
12735     case USE_VEX_LEN_TABLE:
12736       if (!need_vex)
12737         abort ();
12738
12739       switch (vex.length)
12740         {
12741         case 128:
12742           vindex = 0;
12743           break;
12744         case 256:
12745           vindex = 1;
12746           break;
12747         default:
12748           abort ();
12749           break;
12750         }
12751
12752       dp = &vex_len_table[dp->op[1].bytemode][vindex];
12753       break;
12754
12755     case USE_XOP_8F_TABLE:
12756       FETCH_DATA (info, codep + 3);
12757       /* All bits in the REX prefix are ignored.  */
12758       rex_ignored = rex;
12759       rex = ~(*codep >> 5) & 0x7;
12760
12761       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
12762       switch ((*codep & 0x1f))
12763         {
12764         default:
12765           dp = &bad_opcode;
12766           return dp;
12767         case 0x8:
12768           vex_table_index = XOP_08;
12769           break;
12770         case 0x9:
12771           vex_table_index = XOP_09;
12772           break;
12773         case 0xa:
12774           vex_table_index = XOP_0A;
12775           break;
12776         }
12777       codep++;
12778       vex.w = *codep & 0x80;
12779       if (vex.w && address_mode == mode_64bit)
12780         rex |= REX_W;
12781
12782       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12783       if (address_mode != mode_64bit)
12784         {
12785           /* In 16/32-bit mode REX_B is silently ignored.  */
12786           rex &= ~REX_B;
12787           if (vex.register_specifier > 0x7)
12788             {
12789               dp = &bad_opcode;
12790               return dp;
12791             }
12792         }
12793
12794       vex.length = (*codep & 0x4) ? 256 : 128;
12795       switch ((*codep & 0x3))
12796         {
12797         case 0:
12798           vex.prefix = 0;
12799           break;
12800         case 1:
12801           vex.prefix = DATA_PREFIX_OPCODE;
12802           break;
12803         case 2:
12804           vex.prefix = REPE_PREFIX_OPCODE;
12805           break;
12806         case 3:
12807           vex.prefix = REPNE_PREFIX_OPCODE;
12808           break;
12809         }
12810       need_vex = 1;
12811       need_vex_reg = 1;
12812       codep++;
12813       vindex = *codep++;
12814       dp = &xop_table[vex_table_index][vindex];
12815
12816       end_codep = codep;
12817       FETCH_DATA (info, codep + 1);
12818       modrm.mod = (*codep >> 6) & 3;
12819       modrm.reg = (*codep >> 3) & 7;
12820       modrm.rm = *codep & 7;
12821       break;
12822
12823     case USE_VEX_C4_TABLE:
12824       /* VEX prefix.  */
12825       FETCH_DATA (info, codep + 3);
12826       /* All bits in the REX prefix are ignored.  */
12827       rex_ignored = rex;
12828       rex = ~(*codep >> 5) & 0x7;
12829       switch ((*codep & 0x1f))
12830         {
12831         default:
12832           dp = &bad_opcode;
12833           return dp;
12834         case 0x1:
12835           vex_table_index = VEX_0F;
12836           break;
12837         case 0x2:
12838           vex_table_index = VEX_0F38;
12839           break;
12840         case 0x3:
12841           vex_table_index = VEX_0F3A;
12842           break;
12843         }
12844       codep++;
12845       vex.w = *codep & 0x80;
12846       if (address_mode == mode_64bit)
12847         {
12848           if (vex.w)
12849             rex |= REX_W;
12850           vex.register_specifier = (~(*codep >> 3)) & 0xf;
12851         }
12852       else
12853         {
12854           /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
12855              is ignored, other REX bits are 0 and the highest bit in
12856              VEX.vvvv is also ignored.  */
12857           rex = 0;
12858           vex.register_specifier = (~(*codep >> 3)) & 0x7;
12859         }
12860       vex.length = (*codep & 0x4) ? 256 : 128;
12861       switch ((*codep & 0x3))
12862         {
12863         case 0:
12864           vex.prefix = 0;
12865           break;
12866         case 1:
12867           vex.prefix = DATA_PREFIX_OPCODE;
12868           break;
12869         case 2:
12870           vex.prefix = REPE_PREFIX_OPCODE;
12871           break;
12872         case 3:
12873           vex.prefix = REPNE_PREFIX_OPCODE;
12874           break;
12875         }
12876       need_vex = 1;
12877       need_vex_reg = 1;
12878       codep++;
12879       vindex = *codep++;
12880       dp = &vex_table[vex_table_index][vindex];
12881       end_codep = codep;
12882       /* There is no MODRM byte for VEX0F 77.  */
12883       if (vex_table_index != VEX_0F || vindex != 0x77)
12884         {
12885           FETCH_DATA (info, codep + 1);
12886           modrm.mod = (*codep >> 6) & 3;
12887           modrm.reg = (*codep >> 3) & 7;
12888           modrm.rm = *codep & 7;
12889         }
12890       break;
12891
12892     case USE_VEX_C5_TABLE:
12893       /* VEX prefix.  */
12894       FETCH_DATA (info, codep + 2);
12895       /* All bits in the REX prefix are ignored.  */
12896       rex_ignored = rex;
12897       rex = (*codep & 0x80) ? 0 : REX_R;
12898
12899       /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
12900          VEX.vvvv is 1.  */
12901       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12902       vex.w = 0;
12903       vex.length = (*codep & 0x4) ? 256 : 128;
12904       switch ((*codep & 0x3))
12905         {
12906         case 0:
12907           vex.prefix = 0;
12908           break;
12909         case 1:
12910           vex.prefix = DATA_PREFIX_OPCODE;
12911           break;
12912         case 2:
12913           vex.prefix = REPE_PREFIX_OPCODE;
12914           break;
12915         case 3:
12916           vex.prefix = REPNE_PREFIX_OPCODE;
12917           break;
12918         }
12919       need_vex = 1;
12920       need_vex_reg = 1;
12921       codep++;
12922       vindex = *codep++;
12923       dp = &vex_table[dp->op[1].bytemode][vindex];
12924       end_codep = codep;
12925       /* There is no MODRM byte for VEX 77.  */
12926       if (vindex != 0x77)
12927         {
12928           FETCH_DATA (info, codep + 1);
12929           modrm.mod = (*codep >> 6) & 3;
12930           modrm.reg = (*codep >> 3) & 7;
12931           modrm.rm = *codep & 7;
12932         }
12933       break;
12934
12935     case USE_VEX_W_TABLE:
12936       if (!need_vex)
12937         abort ();
12938
12939       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
12940       break;
12941
12942     case USE_EVEX_TABLE:
12943       two_source_ops = 0;
12944       /* EVEX prefix.  */
12945       vex.evex = 1;
12946       FETCH_DATA (info, codep + 4);
12947       /* All bits in the REX prefix are ignored.  */
12948       rex_ignored = rex;
12949       /* The first byte after 0x62.  */
12950       rex = ~(*codep >> 5) & 0x7;
12951       vex.r = *codep & 0x10;
12952       switch ((*codep & 0xf))
12953         {
12954         default:
12955           return &bad_opcode;
12956         case 0x1:
12957           vex_table_index = EVEX_0F;
12958           break;
12959         case 0x2:
12960           vex_table_index = EVEX_0F38;
12961           break;
12962         case 0x3:
12963           vex_table_index = EVEX_0F3A;
12964           break;
12965         }
12966
12967       /* The second byte after 0x62.  */
12968       codep++;
12969       vex.w = *codep & 0x80;
12970       if (vex.w && address_mode == mode_64bit)
12971         rex |= REX_W;
12972
12973       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12974       if (address_mode != mode_64bit)
12975         {
12976           /* In 16/32-bit mode silently ignore following bits.  */
12977           rex &= ~REX_B;
12978           vex.r = 1;
12979           vex.v = 1;
12980           vex.register_specifier &= 0x7;
12981         }
12982
12983       /* The U bit.  */
12984       if (!(*codep & 0x4))
12985         return &bad_opcode;
12986
12987       switch ((*codep & 0x3))
12988         {
12989         case 0:
12990           vex.prefix = 0;
12991           break;
12992         case 1:
12993           vex.prefix = DATA_PREFIX_OPCODE;
12994           break;
12995         case 2:
12996           vex.prefix = REPE_PREFIX_OPCODE;
12997           break;
12998         case 3:
12999           vex.prefix = REPNE_PREFIX_OPCODE;
13000           break;
13001         }
13002
13003       /* The third byte after 0x62.  */
13004       codep++;
13005
13006       /* Remember the static rounding bits.  */
13007       vex.ll = (*codep >> 5) & 3;
13008       vex.b = (*codep & 0x10) != 0;
13009
13010       vex.v = *codep & 0x8;
13011       vex.mask_register_specifier = *codep & 0x7;
13012       vex.zeroing = *codep & 0x80;
13013
13014       need_vex = 1;
13015       need_vex_reg = 1;
13016       codep++;
13017       vindex = *codep++;
13018       dp = &evex_table[vex_table_index][vindex];
13019       end_codep = codep;
13020       FETCH_DATA (info, codep + 1);
13021       modrm.mod = (*codep >> 6) & 3;
13022       modrm.reg = (*codep >> 3) & 7;
13023       modrm.rm = *codep & 7;
13024
13025       /* Set vector length.  */
13026       if (modrm.mod == 3 && vex.b)
13027         vex.length = 512;
13028       else
13029         {
13030           switch (vex.ll)
13031             {
13032             case 0x0:
13033               vex.length = 128;
13034               break;
13035             case 0x1:
13036               vex.length = 256;
13037               break;
13038             case 0x2:
13039               vex.length = 512;
13040               break;
13041             default:
13042               return &bad_opcode;
13043             }
13044         }
13045       break;
13046
13047     case 0:
13048       dp = &bad_opcode;
13049       break;
13050
13051     default:
13052       abort ();
13053     }
13054
13055   if (dp->name != NULL)
13056     return dp;
13057   else
13058     return get_valid_dis386 (dp, info);
13059 }
13060
13061 static void
13062 get_sib (disassemble_info *info, int sizeflag)
13063 {
13064   /* If modrm.mod == 3, operand must be register.  */
13065   if (need_modrm
13066       && ((sizeflag & AFLAG) || address_mode == mode_64bit)
13067       && modrm.mod != 3
13068       && modrm.rm == 4)
13069     {
13070       FETCH_DATA (info, codep + 2);
13071       sib.index = (codep [1] >> 3) & 7;
13072       sib.scale = (codep [1] >> 6) & 3;
13073       sib.base = codep [1] & 7;
13074     }
13075 }
13076
13077 static int
13078 print_insn (bfd_vma pc, disassemble_info *info)
13079 {
13080   const struct dis386 *dp;
13081   int i;
13082   char *op_txt[MAX_OPERANDS];
13083   int needcomma;
13084   int sizeflag, orig_sizeflag;
13085   const char *p;
13086   struct dis_private priv;
13087   int prefix_length;
13088
13089   priv.orig_sizeflag = AFLAG | DFLAG;
13090   if ((info->mach & bfd_mach_i386_i386) != 0)
13091     address_mode = mode_32bit;
13092   else if (info->mach == bfd_mach_i386_i8086)
13093     {
13094       address_mode = mode_16bit;
13095       priv.orig_sizeflag = 0;
13096     }
13097   else
13098     address_mode = mode_64bit;
13099
13100   if (intel_syntax == (char) -1)
13101     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
13102
13103   for (p = info->disassembler_options; p != NULL; )
13104     {
13105       if (CONST_STRNEQ (p, "amd64"))
13106         isa64 = amd64;
13107       else if (CONST_STRNEQ (p, "intel64"))
13108         isa64 = intel64;
13109       else if (CONST_STRNEQ (p, "x86-64"))
13110         {
13111           address_mode = mode_64bit;
13112           priv.orig_sizeflag = AFLAG | DFLAG;
13113         }
13114       else if (CONST_STRNEQ (p, "i386"))
13115         {
13116           address_mode = mode_32bit;
13117           priv.orig_sizeflag = AFLAG | DFLAG;
13118         }
13119       else if (CONST_STRNEQ (p, "i8086"))
13120         {
13121           address_mode = mode_16bit;
13122           priv.orig_sizeflag = 0;
13123         }
13124       else if (CONST_STRNEQ (p, "intel"))
13125         {
13126           intel_syntax = 1;
13127           if (CONST_STRNEQ (p + 5, "-mnemonic"))
13128             intel_mnemonic = 1;
13129         }
13130       else if (CONST_STRNEQ (p, "att"))
13131         {
13132           intel_syntax = 0;
13133           if (CONST_STRNEQ (p + 3, "-mnemonic"))
13134             intel_mnemonic = 0;
13135         }
13136       else if (CONST_STRNEQ (p, "addr"))
13137         {
13138           if (address_mode == mode_64bit)
13139             {
13140               if (p[4] == '3' && p[5] == '2')
13141                 priv.orig_sizeflag &= ~AFLAG;
13142               else if (p[4] == '6' && p[5] == '4')
13143                 priv.orig_sizeflag |= AFLAG;
13144             }
13145           else
13146             {
13147               if (p[4] == '1' && p[5] == '6')
13148                 priv.orig_sizeflag &= ~AFLAG;
13149               else if (p[4] == '3' && p[5] == '2')
13150                 priv.orig_sizeflag |= AFLAG;
13151             }
13152         }
13153       else if (CONST_STRNEQ (p, "data"))
13154         {
13155           if (p[4] == '1' && p[5] == '6')
13156             priv.orig_sizeflag &= ~DFLAG;
13157           else if (p[4] == '3' && p[5] == '2')
13158             priv.orig_sizeflag |= DFLAG;
13159         }
13160       else if (CONST_STRNEQ (p, "suffix"))
13161         priv.orig_sizeflag |= SUFFIX_ALWAYS;
13162
13163       p = strchr (p, ',');
13164       if (p != NULL)
13165         p++;
13166     }
13167
13168   if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
13169     {
13170       (*info->fprintf_func) (info->stream,
13171                              _("64-bit address is disabled"));
13172       return -1;
13173     }
13174
13175   if (intel_syntax)
13176     {
13177       names64 = intel_names64;
13178       names32 = intel_names32;
13179       names16 = intel_names16;
13180       names8 = intel_names8;
13181       names8rex = intel_names8rex;
13182       names_seg = intel_names_seg;
13183       names_mm = intel_names_mm;
13184       names_bnd = intel_names_bnd;
13185       names_xmm = intel_names_xmm;
13186       names_ymm = intel_names_ymm;
13187       names_zmm = intel_names_zmm;
13188       index64 = intel_index64;
13189       index32 = intel_index32;
13190       names_mask = intel_names_mask;
13191       index16 = intel_index16;
13192       open_char = '[';
13193       close_char = ']';
13194       separator_char = '+';
13195       scale_char = '*';
13196     }
13197   else
13198     {
13199       names64 = att_names64;
13200       names32 = att_names32;
13201       names16 = att_names16;
13202       names8 = att_names8;
13203       names8rex = att_names8rex;
13204       names_seg = att_names_seg;
13205       names_mm = att_names_mm;
13206       names_bnd = att_names_bnd;
13207       names_xmm = att_names_xmm;
13208       names_ymm = att_names_ymm;
13209       names_zmm = att_names_zmm;
13210       index64 = att_index64;
13211       index32 = att_index32;
13212       names_mask = att_names_mask;
13213       index16 = att_index16;
13214       open_char = '(';
13215       close_char =  ')';
13216       separator_char = ',';
13217       scale_char = ',';
13218     }
13219
13220   /* The output looks better if we put 7 bytes on a line, since that
13221      puts most long word instructions on a single line.  Use 8 bytes
13222      for Intel L1OM.  */
13223   if ((info->mach & bfd_mach_l1om) != 0)
13224     info->bytes_per_line = 8;
13225   else
13226     info->bytes_per_line = 7;
13227
13228   info->private_data = &priv;
13229   priv.max_fetched = priv.the_buffer;
13230   priv.insn_start = pc;
13231
13232   obuf[0] = 0;
13233   for (i = 0; i < MAX_OPERANDS; ++i)
13234     {
13235       op_out[i][0] = 0;
13236       op_index[i] = -1;
13237     }
13238
13239   the_info = info;
13240   start_pc = pc;
13241   start_codep = priv.the_buffer;
13242   codep = priv.the_buffer;
13243
13244   if (OPCODES_SIGSETJMP (priv.bailout) != 0)
13245     {
13246       const char *name;
13247
13248       /* Getting here means we tried for data but didn't get it.  That
13249          means we have an incomplete instruction of some sort.  Just
13250          print the first byte as a prefix or a .byte pseudo-op.  */
13251       if (codep > priv.the_buffer)
13252         {
13253           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
13254           if (name != NULL)
13255             (*info->fprintf_func) (info->stream, "%s", name);
13256           else
13257             {
13258               /* Just print the first byte as a .byte instruction.  */
13259               (*info->fprintf_func) (info->stream, ".byte 0x%x",
13260                                      (unsigned int) priv.the_buffer[0]);
13261             }
13262
13263           return 1;
13264         }
13265
13266       return -1;
13267     }
13268
13269   obufp = obuf;
13270   sizeflag = priv.orig_sizeflag;
13271
13272   if (!ckprefix () || rex_used)
13273     {
13274       /* Too many prefixes or unused REX prefixes.  */
13275       for (i = 0;
13276            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
13277            i++)
13278         (*info->fprintf_func) (info->stream, "%s%s",
13279                                i == 0 ? "" : " ",
13280                                prefix_name (all_prefixes[i], sizeflag));
13281       return i;
13282     }
13283
13284   insn_codep = codep;
13285
13286   FETCH_DATA (info, codep + 1);
13287   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
13288
13289   if (((prefixes & PREFIX_FWAIT)
13290        && ((*codep < 0xd8) || (*codep > 0xdf))))
13291     {
13292       /* Handle prefixes before fwait.  */
13293       for (i = 0; i < fwait_prefix && all_prefixes[i];
13294            i++)
13295         (*info->fprintf_func) (info->stream, "%s ",
13296                                prefix_name (all_prefixes[i], sizeflag));
13297       (*info->fprintf_func) (info->stream, "fwait");
13298       return i + 1;
13299     }
13300
13301   if (*codep == 0x0f)
13302     {
13303       unsigned char threebyte;
13304
13305       codep++;
13306       FETCH_DATA (info, codep + 1);
13307       threebyte = *codep;
13308       dp = &dis386_twobyte[threebyte];
13309       need_modrm = twobyte_has_modrm[*codep];
13310       codep++;
13311     }
13312   else
13313     {
13314       dp = &dis386[*codep];
13315       need_modrm = onebyte_has_modrm[*codep];
13316       codep++;
13317     }
13318
13319   /* Save sizeflag for printing the extra prefixes later before updating
13320      it for mnemonic and operand processing.  The prefix names depend
13321      only on the address mode.  */
13322   orig_sizeflag = sizeflag;
13323   if (prefixes & PREFIX_ADDR)
13324     sizeflag ^= AFLAG;
13325   if ((prefixes & PREFIX_DATA))
13326     sizeflag ^= DFLAG;
13327
13328   end_codep = codep;
13329   if (need_modrm)
13330     {
13331       FETCH_DATA (info, codep + 1);
13332       modrm.mod = (*codep >> 6) & 3;
13333       modrm.reg = (*codep >> 3) & 7;
13334       modrm.rm = *codep & 7;
13335     }
13336
13337   need_vex = 0;
13338   need_vex_reg = 0;
13339   vex_w_done = 0;
13340   vex.evex = 0;
13341
13342   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
13343     {
13344       get_sib (info, sizeflag);
13345       dofloat (sizeflag);
13346     }
13347   else
13348     {
13349       dp = get_valid_dis386 (dp, info);
13350       if (dp != NULL && putop (dp->name, sizeflag) == 0)
13351         {
13352           get_sib (info, sizeflag);
13353           for (i = 0; i < MAX_OPERANDS; ++i)
13354             {
13355               obufp = op_out[i];
13356               op_ad = MAX_OPERANDS - 1 - i;
13357               if (dp->op[i].rtn)
13358                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
13359               /* For EVEX instruction after the last operand masking
13360                  should be printed.  */
13361               if (i == 0 && vex.evex)
13362                 {
13363                   /* Don't print {%k0}.  */
13364                   if (vex.mask_register_specifier)
13365                     {
13366                       oappend ("{");
13367                       oappend (names_mask[vex.mask_register_specifier]);
13368                       oappend ("}");
13369                     }
13370                   if (vex.zeroing)
13371                     oappend ("{z}");
13372                 }
13373             }
13374         }
13375     }
13376
13377   /* Check if the REX prefix is used.  */
13378   if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)
13379     all_prefixes[last_rex_prefix] = 0;
13380
13381   /* Check if the SEG prefix is used.  */
13382   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
13383                    | PREFIX_FS | PREFIX_GS)) != 0
13384       && (used_prefixes & active_seg_prefix) != 0)
13385     all_prefixes[last_seg_prefix] = 0;
13386
13387   /* Check if the ADDR prefix is used.  */
13388   if ((prefixes & PREFIX_ADDR) != 0
13389       && (used_prefixes & PREFIX_ADDR) != 0)
13390     all_prefixes[last_addr_prefix] = 0;
13391
13392   /* Check if the DATA prefix is used.  */
13393   if ((prefixes & PREFIX_DATA) != 0
13394       && (used_prefixes & PREFIX_DATA) != 0)
13395     all_prefixes[last_data_prefix] = 0;
13396
13397   /* Print the extra prefixes.  */
13398   prefix_length = 0;
13399   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
13400     if (all_prefixes[i])
13401       {
13402         const char *name;
13403         name = prefix_name (all_prefixes[i], orig_sizeflag);
13404         if (name == NULL)
13405           abort ();
13406         prefix_length += strlen (name) + 1;
13407         (*info->fprintf_func) (info->stream, "%s ", name);
13408       }
13409
13410   /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
13411      unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
13412      used by putop and MMX/SSE operand and may be overriden by the
13413      PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
13414      separately.  */
13415   if (dp->prefix_requirement == PREFIX_OPCODE
13416       && dp != &bad_opcode
13417       && (((prefixes
13418             & (PREFIX_REPZ | PREFIX_REPNZ)) != 0
13419            && (used_prefixes
13420                & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
13421           || ((((prefixes
13422                  & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
13423                 == PREFIX_DATA)
13424                && (used_prefixes & PREFIX_DATA) == 0))))
13425     {
13426       (*info->fprintf_func) (info->stream, "(bad)");
13427       return end_codep - priv.the_buffer;
13428     }
13429
13430   /* Check maximum code length.  */
13431   if ((codep - start_codep) > MAX_CODE_LENGTH)
13432     {
13433       (*info->fprintf_func) (info->stream, "(bad)");
13434       return MAX_CODE_LENGTH;
13435     }
13436
13437   obufp = mnemonicendp;
13438   for (i = strlen (obuf) + prefix_length; i < 6; i++)
13439     oappend (" ");
13440   oappend (" ");
13441   (*info->fprintf_func) (info->stream, "%s", obuf);
13442
13443   /* The enter and bound instructions are printed with operands in the same
13444      order as the intel book; everything else is printed in reverse order.  */
13445   if (intel_syntax || two_source_ops)
13446     {
13447       bfd_vma riprel;
13448
13449       for (i = 0; i < MAX_OPERANDS; ++i)
13450         op_txt[i] = op_out[i];
13451
13452       if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
13453           && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
13454         {
13455           op_txt[2] = op_out[3];
13456           op_txt[3] = op_out[2];
13457         }
13458
13459       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
13460         {
13461           op_ad = op_index[i];
13462           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
13463           op_index[MAX_OPERANDS - 1 - i] = op_ad;
13464           riprel = op_riprel[i];
13465           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
13466           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
13467         }
13468     }
13469   else
13470     {
13471       for (i = 0; i < MAX_OPERANDS; ++i)
13472         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
13473     }
13474
13475   needcomma = 0;
13476   for (i = 0; i < MAX_OPERANDS; ++i)
13477     if (*op_txt[i])
13478       {
13479         if (needcomma)
13480           (*info->fprintf_func) (info->stream, ",");
13481         if (op_index[i] != -1 && !op_riprel[i])
13482           (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
13483         else
13484           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
13485         needcomma = 1;
13486       }
13487
13488   for (i = 0; i < MAX_OPERANDS; i++)
13489     if (op_index[i] != -1 && op_riprel[i])
13490       {
13491         (*info->fprintf_func) (info->stream, "        # ");
13492         (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
13493                                                 + op_address[op_index[i]]), info);
13494         break;
13495       }
13496   return codep - priv.the_buffer;
13497 }
13498
13499 static const char *float_mem[] = {
13500   /* d8 */
13501   "fadd{s|}",
13502   "fmul{s|}",
13503   "fcom{s|}",
13504   "fcomp{s|}",
13505   "fsub{s|}",
13506   "fsubr{s|}",
13507   "fdiv{s|}",
13508   "fdivr{s|}",
13509   /* d9 */
13510   "fld{s|}",
13511   "(bad)",
13512   "fst{s|}",
13513   "fstp{s|}",
13514   "fldenvIC",
13515   "fldcw",
13516   "fNstenvIC",
13517   "fNstcw",
13518   /* da */
13519   "fiadd{l|}",
13520   "fimul{l|}",
13521   "ficom{l|}",
13522   "ficomp{l|}",
13523   "fisub{l|}",
13524   "fisubr{l|}",
13525   "fidiv{l|}",
13526   "fidivr{l|}",
13527   /* db */
13528   "fild{l|}",
13529   "fisttp{l|}",
13530   "fist{l|}",
13531   "fistp{l|}",
13532   "(bad)",
13533   "fld{t||t|}",
13534   "(bad)",
13535   "fstp{t||t|}",
13536   /* dc */
13537   "fadd{l|}",
13538   "fmul{l|}",
13539   "fcom{l|}",
13540   "fcomp{l|}",
13541   "fsub{l|}",
13542   "fsubr{l|}",
13543   "fdiv{l|}",
13544   "fdivr{l|}",
13545   /* dd */
13546   "fld{l|}",
13547   "fisttp{ll|}",
13548   "fst{l||}",
13549   "fstp{l|}",
13550   "frstorIC",
13551   "(bad)",
13552   "fNsaveIC",
13553   "fNstsw",
13554   /* de */
13555   "fiadd",
13556   "fimul",
13557   "ficom",
13558   "ficomp",
13559   "fisub",
13560   "fisubr",
13561   "fidiv",
13562   "fidivr",
13563   /* df */
13564   "fild",
13565   "fisttp",
13566   "fist",
13567   "fistp",
13568   "fbld",
13569   "fild{ll|}",
13570   "fbstp",
13571   "fistp{ll|}",
13572 };
13573
13574 static const unsigned char float_mem_mode[] = {
13575   /* d8 */
13576   d_mode,
13577   d_mode,
13578   d_mode,
13579   d_mode,
13580   d_mode,
13581   d_mode,
13582   d_mode,
13583   d_mode,
13584   /* d9 */
13585   d_mode,
13586   0,
13587   d_mode,
13588   d_mode,
13589   0,
13590   w_mode,
13591   0,
13592   w_mode,
13593   /* da */
13594   d_mode,
13595   d_mode,
13596   d_mode,
13597   d_mode,
13598   d_mode,
13599   d_mode,
13600   d_mode,
13601   d_mode,
13602   /* db */
13603   d_mode,
13604   d_mode,
13605   d_mode,
13606   d_mode,
13607   0,
13608   t_mode,
13609   0,
13610   t_mode,
13611   /* dc */
13612   q_mode,
13613   q_mode,
13614   q_mode,
13615   q_mode,
13616   q_mode,
13617   q_mode,
13618   q_mode,
13619   q_mode,
13620   /* dd */
13621   q_mode,
13622   q_mode,
13623   q_mode,
13624   q_mode,
13625   0,
13626   0,
13627   0,
13628   w_mode,
13629   /* de */
13630   w_mode,
13631   w_mode,
13632   w_mode,
13633   w_mode,
13634   w_mode,
13635   w_mode,
13636   w_mode,
13637   w_mode,
13638   /* df */
13639   w_mode,
13640   w_mode,
13641   w_mode,
13642   w_mode,
13643   t_mode,
13644   q_mode,
13645   t_mode,
13646   q_mode
13647 };
13648
13649 #define ST { OP_ST, 0 }
13650 #define STi { OP_STi, 0 }
13651
13652 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
13653 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
13654 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
13655 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
13656 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
13657 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
13658 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
13659 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
13660 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
13661
13662 static const struct dis386 float_reg[][8] = {
13663   /* d8 */
13664   {
13665     { "fadd",   { ST, STi }, 0 },
13666     { "fmul",   { ST, STi }, 0 },
13667     { "fcom",   { STi }, 0 },
13668     { "fcomp",  { STi }, 0 },
13669     { "fsub",   { ST, STi }, 0 },
13670     { "fsubr",  { ST, STi }, 0 },
13671     { "fdiv",   { ST, STi }, 0 },
13672     { "fdivr",  { ST, STi }, 0 },
13673   },
13674   /* d9 */
13675   {
13676     { "fld",    { STi }, 0 },
13677     { "fxch",   { STi }, 0 },
13678     { FGRPd9_2 },
13679     { Bad_Opcode },
13680     { FGRPd9_4 },
13681     { FGRPd9_5 },
13682     { FGRPd9_6 },
13683     { FGRPd9_7 },
13684   },
13685   /* da */
13686   {
13687     { "fcmovb", { ST, STi }, 0 },
13688     { "fcmove", { ST, STi }, 0 },
13689     { "fcmovbe",{ ST, STi }, 0 },
13690     { "fcmovu", { ST, STi }, 0 },
13691     { Bad_Opcode },
13692     { FGRPda_5 },
13693     { Bad_Opcode },
13694     { Bad_Opcode },
13695   },
13696   /* db */
13697   {
13698     { "fcmovnb",{ ST, STi }, 0 },
13699     { "fcmovne",{ ST, STi }, 0 },
13700     { "fcmovnbe",{ ST, STi }, 0 },
13701     { "fcmovnu",{ ST, STi }, 0 },
13702     { FGRPdb_4 },
13703     { "fucomi", { ST, STi }, 0 },
13704     { "fcomi",  { ST, STi }, 0 },
13705     { Bad_Opcode },
13706   },
13707   /* dc */
13708   {
13709     { "fadd",   { STi, ST }, 0 },
13710     { "fmul",   { STi, ST }, 0 },
13711     { Bad_Opcode },
13712     { Bad_Opcode },
13713     { "fsub!M", { STi, ST }, 0 },
13714     { "fsubM",  { STi, ST }, 0 },
13715     { "fdiv!M", { STi, ST }, 0 },
13716     { "fdivM",  { STi, ST }, 0 },
13717   },
13718   /* dd */
13719   {
13720     { "ffree",  { STi }, 0 },
13721     { Bad_Opcode },
13722     { "fst",    { STi }, 0 },
13723     { "fstp",   { STi }, 0 },
13724     { "fucom",  { STi }, 0 },
13725     { "fucomp", { STi }, 0 },
13726     { Bad_Opcode },
13727     { Bad_Opcode },
13728   },
13729   /* de */
13730   {
13731     { "faddp",  { STi, ST }, 0 },
13732     { "fmulp",  { STi, ST }, 0 },
13733     { Bad_Opcode },
13734     { FGRPde_3 },
13735     { "fsub!Mp", { STi, ST }, 0 },
13736     { "fsubMp", { STi, ST }, 0 },
13737     { "fdiv!Mp", { STi, ST }, 0 },
13738     { "fdivMp", { STi, ST }, 0 },
13739   },
13740   /* df */
13741   {
13742     { "ffreep", { STi }, 0 },
13743     { Bad_Opcode },
13744     { Bad_Opcode },
13745     { Bad_Opcode },
13746     { FGRPdf_4 },
13747     { "fucomip", { ST, STi }, 0 },
13748     { "fcomip", { ST, STi }, 0 },
13749     { Bad_Opcode },
13750   },
13751 };
13752
13753 static char *fgrps[][8] = {
13754   /* Bad opcode 0 */
13755   {
13756     "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13757   },
13758
13759   /* d9_2  1 */
13760   {
13761     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13762   },
13763
13764   /* d9_4  2 */
13765   {
13766     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
13767   },
13768
13769   /* d9_5  3 */
13770   {
13771     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
13772   },
13773
13774   /* d9_6  4 */
13775   {
13776     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
13777   },
13778
13779   /* d9_7  5 */
13780   {
13781     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
13782   },
13783
13784   /* da_5  6 */
13785   {
13786     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13787   },
13788
13789   /* db_4  7 */
13790   {
13791     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
13792     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
13793   },
13794
13795   /* de_3  8 */
13796   {
13797     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13798   },
13799
13800   /* df_4  9 */
13801   {
13802     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13803   },
13804 };
13805
13806 static void
13807 swap_operand (void)
13808 {
13809   mnemonicendp[0] = '.';
13810   mnemonicendp[1] = 's';
13811   mnemonicendp += 2;
13812 }
13813
13814 static void
13815 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
13816                int sizeflag ATTRIBUTE_UNUSED)
13817 {
13818   /* Skip mod/rm byte.  */
13819   MODRM_CHECK;
13820   codep++;
13821 }
13822
13823 static void
13824 dofloat (int sizeflag)
13825 {
13826   const struct dis386 *dp;
13827   unsigned char floatop;
13828
13829   floatop = codep[-1];
13830
13831   if (modrm.mod != 3)
13832     {
13833       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
13834
13835       putop (float_mem[fp_indx], sizeflag);
13836       obufp = op_out[0];
13837       op_ad = 2;
13838       OP_E (float_mem_mode[fp_indx], sizeflag);
13839       return;
13840     }
13841   /* Skip mod/rm byte.  */
13842   MODRM_CHECK;
13843   codep++;
13844
13845   dp = &float_reg[floatop - 0xd8][modrm.reg];
13846   if (dp->name == NULL)
13847     {
13848       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
13849
13850       /* Instruction fnstsw is only one with strange arg.  */
13851       if (floatop == 0xdf && codep[-1] == 0xe0)
13852         strcpy (op_out[0], names16[0]);
13853     }
13854   else
13855     {
13856       putop (dp->name, sizeflag);
13857
13858       obufp = op_out[0];
13859       op_ad = 2;
13860       if (dp->op[0].rtn)
13861         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
13862
13863       obufp = op_out[1];
13864       op_ad = 1;
13865       if (dp->op[1].rtn)
13866         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
13867     }
13868 }
13869
13870 /* Like oappend (below), but S is a string starting with '%'.
13871    In Intel syntax, the '%' is elided.  */
13872 static void
13873 oappend_maybe_intel (const char *s)
13874 {
13875   oappend (s + intel_syntax);
13876 }
13877
13878 static void
13879 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13880 {
13881   oappend_maybe_intel ("%st");
13882 }
13883
13884 static void
13885 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13886 {
13887   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
13888   oappend_maybe_intel (scratchbuf);
13889 }
13890
13891 /* Capital letters in template are macros.  */
13892 static int
13893 putop (const char *in_template, int sizeflag)
13894 {
13895   const char *p;
13896   int alt = 0;
13897   int cond = 1;
13898   unsigned int l = 0, len = 1;
13899   char last[4];
13900
13901 #define SAVE_LAST(c)                    \
13902   if (l < len && l < sizeof (last))     \
13903     last[l++] = c;                      \
13904   else                                  \
13905     abort ();
13906
13907   for (p = in_template; *p; p++)
13908     {
13909       switch (*p)
13910         {
13911         default:
13912           *obufp++ = *p;
13913           break;
13914         case '%':
13915           len++;
13916           break;
13917         case '!':
13918           cond = 0;
13919           break;
13920         case '{':
13921           if (intel_syntax)
13922             {
13923               while (*++p != '|')
13924                 if (*p == '}' || *p == '\0')
13925                   abort ();
13926             }
13927           /* Fall through.  */
13928         case 'I':
13929           alt = 1;
13930           continue;
13931         case '|':
13932           while (*++p != '}')
13933             {
13934               if (*p == '\0')
13935                 abort ();
13936             }
13937           break;
13938         case '}':
13939           break;
13940         case 'A':
13941           if (intel_syntax)
13942             break;
13943           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13944             *obufp++ = 'b';
13945           break;
13946         case 'B':
13947           if (l == 0 && len == 1)
13948             {
13949 case_B:
13950               if (intel_syntax)
13951                 break;
13952               if (sizeflag & SUFFIX_ALWAYS)
13953                 *obufp++ = 'b';
13954             }
13955           else
13956             {
13957               if (l != 1
13958                   || len != 2
13959                   || last[0] != 'L')
13960                 {
13961                   SAVE_LAST (*p);
13962                   break;
13963                 }
13964
13965               if (address_mode == mode_64bit
13966                   && !(prefixes & PREFIX_ADDR))
13967                 {
13968                   *obufp++ = 'a';
13969                   *obufp++ = 'b';
13970                   *obufp++ = 's';
13971                 }
13972
13973               goto case_B;
13974             }
13975           break;
13976         case 'C':
13977           if (intel_syntax && !alt)
13978             break;
13979           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
13980             {
13981               if (sizeflag & DFLAG)
13982                 *obufp++ = intel_syntax ? 'd' : 'l';
13983               else
13984                 *obufp++ = intel_syntax ? 'w' : 's';
13985               used_prefixes |= (prefixes & PREFIX_DATA);
13986             }
13987           break;
13988         case 'D':
13989           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
13990             break;
13991           USED_REX (REX_W);
13992           if (modrm.mod == 3)
13993             {
13994               if (rex & REX_W)
13995                 *obufp++ = 'q';
13996               else
13997                 {
13998                   if (sizeflag & DFLAG)
13999                     *obufp++ = intel_syntax ? 'd' : 'l';
14000                   else
14001                     *obufp++ = 'w';
14002                   used_prefixes |= (prefixes & PREFIX_DATA);
14003                 }
14004             }
14005           else
14006             *obufp++ = 'w';
14007           break;
14008         case 'E':               /* For jcxz/jecxz */
14009           if (address_mode == mode_64bit)
14010             {
14011               if (sizeflag & AFLAG)
14012                 *obufp++ = 'r';
14013               else
14014                 *obufp++ = 'e';
14015             }
14016           else
14017             if (sizeflag & AFLAG)
14018               *obufp++ = 'e';
14019           used_prefixes |= (prefixes & PREFIX_ADDR);
14020           break;
14021         case 'F':
14022           if (intel_syntax)
14023             break;
14024           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
14025             {
14026               if (sizeflag & AFLAG)
14027                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
14028               else
14029                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
14030               used_prefixes |= (prefixes & PREFIX_ADDR);
14031             }
14032           break;
14033         case 'G':
14034           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
14035             break;
14036           if ((rex & REX_W) || (sizeflag & DFLAG))
14037             *obufp++ = 'l';
14038           else
14039             *obufp++ = 'w';
14040           if (!(rex & REX_W))
14041             used_prefixes |= (prefixes & PREFIX_DATA);
14042           break;
14043         case 'H':
14044           if (intel_syntax)
14045             break;
14046           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
14047               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
14048             {
14049               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
14050               *obufp++ = ',';
14051               *obufp++ = 'p';
14052               if (prefixes & PREFIX_DS)
14053                 *obufp++ = 't';
14054               else
14055                 *obufp++ = 'n';
14056             }
14057           break;
14058         case 'J':
14059           if (intel_syntax)
14060             break;
14061           *obufp++ = 'l';
14062           break;
14063         case 'K':
14064           USED_REX (REX_W);
14065           if (rex & REX_W)
14066             *obufp++ = 'q';
14067           else
14068             *obufp++ = 'd';
14069           break;
14070         case 'Z':
14071           if (l != 0 || len != 1)
14072             {
14073               if (l != 1 || len != 2 || last[0] != 'X')
14074                 {
14075                   SAVE_LAST (*p);
14076                   break;
14077                 }
14078               if (!need_vex || !vex.evex)
14079                 abort ();
14080               if (intel_syntax
14081                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
14082                 break;
14083               switch (vex.length)
14084                 {
14085                 case 128:
14086                   *obufp++ = 'x';
14087                   break;
14088                 case 256:
14089                   *obufp++ = 'y';
14090                   break;
14091                 case 512:
14092                   *obufp++ = 'z';
14093                   break;
14094                 default:
14095                   abort ();
14096                 }
14097               break;
14098             }
14099           if (intel_syntax)
14100             break;
14101           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
14102             {
14103               *obufp++ = 'q';
14104               break;
14105             }
14106           /* Fall through.  */
14107           goto case_L;
14108         case 'L':
14109           if (l != 0 || len != 1)
14110             {
14111               SAVE_LAST (*p);
14112               break;
14113             }
14114 case_L:
14115           if (intel_syntax)
14116             break;
14117           if (sizeflag & SUFFIX_ALWAYS)
14118             *obufp++ = 'l';
14119           break;
14120         case 'M':
14121           if (intel_mnemonic != cond)
14122             *obufp++ = 'r';
14123           break;
14124         case 'N':
14125           if ((prefixes & PREFIX_FWAIT) == 0)
14126             *obufp++ = 'n';
14127           else
14128             used_prefixes |= PREFIX_FWAIT;
14129           break;
14130         case 'O':
14131           USED_REX (REX_W);
14132           if (rex & REX_W)
14133             *obufp++ = 'o';
14134           else if (intel_syntax && (sizeflag & DFLAG))
14135             *obufp++ = 'q';
14136           else
14137             *obufp++ = 'd';
14138           if (!(rex & REX_W))
14139             used_prefixes |= (prefixes & PREFIX_DATA);
14140           break;
14141         case '&':
14142           if (!intel_syntax
14143               && address_mode == mode_64bit
14144               && isa64 == intel64)
14145             {
14146               *obufp++ = 'q';
14147               break;
14148             }
14149           /* Fall through.  */
14150         case 'T':
14151           if (!intel_syntax
14152               && address_mode == mode_64bit
14153               && ((sizeflag & DFLAG) || (rex & REX_W)))
14154             {
14155               *obufp++ = 'q';
14156               break;
14157             }
14158           /* Fall through.  */
14159           goto case_P;
14160         case 'P':
14161           if (l == 0 && len == 1)
14162             {
14163 case_P:
14164               if (intel_syntax)
14165                 {
14166                   if ((rex & REX_W) == 0
14167                       && (prefixes & PREFIX_DATA))
14168                     {
14169                       if ((sizeflag & DFLAG) == 0)
14170                         *obufp++ = 'w';
14171                       used_prefixes |= (prefixes & PREFIX_DATA);
14172                     }
14173                   break;
14174                 }
14175               if ((prefixes & PREFIX_DATA)
14176                   || (rex & REX_W)
14177                   || (sizeflag & SUFFIX_ALWAYS))
14178                 {
14179                   USED_REX (REX_W);
14180                   if (rex & REX_W)
14181                     *obufp++ = 'q';
14182                   else
14183                     {
14184                       if (sizeflag & DFLAG)
14185                         *obufp++ = 'l';
14186                       else
14187                         *obufp++ = 'w';
14188                       used_prefixes |= (prefixes & PREFIX_DATA);
14189                     }
14190                 }
14191             }
14192           else
14193             {
14194               if (l != 1 || len != 2 || last[0] != 'L')
14195                 {
14196                   SAVE_LAST (*p);
14197                   break;
14198                 }
14199
14200               if ((prefixes & PREFIX_DATA)
14201                   || (rex & REX_W)
14202                   || (sizeflag & SUFFIX_ALWAYS))
14203                 {
14204                   USED_REX (REX_W);
14205                   if (rex & REX_W)
14206                     *obufp++ = 'q';
14207                   else
14208                     {
14209                       if (sizeflag & DFLAG)
14210                         *obufp++ = intel_syntax ? 'd' : 'l';
14211                       else
14212                         *obufp++ = 'w';
14213                       used_prefixes |= (prefixes & PREFIX_DATA);
14214                     }
14215                 }
14216             }
14217           break;
14218         case 'U':
14219           if (intel_syntax)
14220             break;
14221           if (address_mode == mode_64bit
14222               && ((sizeflag & DFLAG) || (rex & REX_W)))
14223             {
14224               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
14225                 *obufp++ = 'q';
14226               break;
14227             }
14228           /* Fall through.  */
14229           goto case_Q;
14230         case 'Q':
14231           if (l == 0 && len == 1)
14232             {
14233 case_Q:
14234               if (intel_syntax && !alt)
14235                 break;
14236               USED_REX (REX_W);
14237               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
14238                 {
14239                   if (rex & REX_W)
14240                     *obufp++ = 'q';
14241                   else
14242                     {
14243                       if (sizeflag & DFLAG)
14244                         *obufp++ = intel_syntax ? 'd' : 'l';
14245                       else
14246                         *obufp++ = 'w';
14247                       used_prefixes |= (prefixes & PREFIX_DATA);
14248                     }
14249                 }
14250             }
14251           else
14252             {
14253               if (l != 1 || len != 2 || last[0] != 'L')
14254                 {
14255                   SAVE_LAST (*p);
14256                   break;
14257                 }
14258               if (intel_syntax
14259                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
14260                 break;
14261               if ((rex & REX_W))
14262                 {
14263                   USED_REX (REX_W);
14264                   *obufp++ = 'q';
14265                 }
14266               else
14267                 *obufp++ = 'l';
14268             }
14269           break;
14270         case 'R':
14271           USED_REX (REX_W);
14272           if (rex & REX_W)
14273             *obufp++ = 'q';
14274           else if (sizeflag & DFLAG)
14275             {
14276               if (intel_syntax)
14277                   *obufp++ = 'd';
14278               else
14279                   *obufp++ = 'l';
14280             }
14281           else
14282             *obufp++ = 'w';
14283           if (intel_syntax && !p[1]
14284               && ((rex & REX_W) || (sizeflag & DFLAG)))
14285             *obufp++ = 'e';
14286           if (!(rex & REX_W))
14287             used_prefixes |= (prefixes & PREFIX_DATA);
14288           break;
14289         case 'V':
14290           if (l == 0 && len == 1)
14291             {
14292               if (intel_syntax)
14293                 break;
14294               if (address_mode == mode_64bit
14295                   && ((sizeflag & DFLAG) || (rex & REX_W)))
14296                 {
14297                   if (sizeflag & SUFFIX_ALWAYS)
14298                     *obufp++ = 'q';
14299                   break;
14300                 }
14301             }
14302           else
14303             {
14304               if (l != 1
14305                   || len != 2
14306                   || last[0] != 'L')
14307                 {
14308                   SAVE_LAST (*p);
14309                   break;
14310                 }
14311
14312               if (rex & REX_W)
14313                 {
14314                   *obufp++ = 'a';
14315                   *obufp++ = 'b';
14316                   *obufp++ = 's';
14317                 }
14318             }
14319           /* Fall through.  */
14320           goto case_S;
14321         case 'S':
14322           if (l == 0 && len == 1)
14323             {
14324 case_S:
14325               if (intel_syntax)
14326                 break;
14327               if (sizeflag & SUFFIX_ALWAYS)
14328                 {
14329                   if (rex & REX_W)
14330                     *obufp++ = 'q';
14331                   else
14332                     {
14333                       if (sizeflag & DFLAG)
14334                         *obufp++ = 'l';
14335                       else
14336                         *obufp++ = 'w';
14337                       used_prefixes |= (prefixes & PREFIX_DATA);
14338                     }
14339                 }
14340             }
14341           else
14342             {
14343               if (l != 1
14344                   || len != 2
14345                   || last[0] != 'L')
14346                 {
14347                   SAVE_LAST (*p);
14348                   break;
14349                 }
14350
14351               if (address_mode == mode_64bit
14352                   && !(prefixes & PREFIX_ADDR))
14353                 {
14354                   *obufp++ = 'a';
14355                   *obufp++ = 'b';
14356                   *obufp++ = 's';
14357                 }
14358
14359               goto case_S;
14360             }
14361           break;
14362         case 'X':
14363           if (l != 0 || len != 1)
14364             {
14365               SAVE_LAST (*p);
14366               break;
14367             }
14368           if (need_vex && vex.prefix)
14369             {
14370               if (vex.prefix == DATA_PREFIX_OPCODE)
14371                 *obufp++ = 'd';
14372               else
14373                 *obufp++ = 's';
14374             }
14375           else
14376             {
14377               if (prefixes & PREFIX_DATA)
14378                 *obufp++ = 'd';
14379               else
14380                 *obufp++ = 's';
14381               used_prefixes |= (prefixes & PREFIX_DATA);
14382             }
14383           break;
14384         case 'Y':
14385           if (l == 0 && len == 1)
14386             {
14387               if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
14388                 break;
14389               if (rex & REX_W)
14390                 {
14391                   USED_REX (REX_W);
14392                   *obufp++ = 'q';
14393                 }
14394               break;
14395             }
14396           else
14397             {
14398               if (l != 1 || len != 2 || last[0] != 'X')
14399                 {
14400                   SAVE_LAST (*p);
14401                   break;
14402                 }
14403               if (!need_vex)
14404                 abort ();
14405               if (intel_syntax
14406                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
14407                 break;
14408               switch (vex.length)
14409                 {
14410                 case 128:
14411                   *obufp++ = 'x';
14412                   break;
14413                 case 256:
14414                   *obufp++ = 'y';
14415                   break;
14416                 case 512:
14417                   if (!vex.evex)
14418                 default:
14419                     abort ();
14420                 }
14421             }
14422           break;
14423         case 'W':
14424           if (l == 0 && len == 1)
14425             {
14426               /* operand size flag for cwtl, cbtw */
14427               USED_REX (REX_W);
14428               if (rex & REX_W)
14429                 {
14430                   if (intel_syntax)
14431                     *obufp++ = 'd';
14432                   else
14433                     *obufp++ = 'l';
14434                 }
14435               else if (sizeflag & DFLAG)
14436                 *obufp++ = 'w';
14437               else
14438                 *obufp++ = 'b';
14439               if (!(rex & REX_W))
14440                 used_prefixes |= (prefixes & PREFIX_DATA);
14441             }
14442           else
14443             {
14444               if (l != 1
14445                   || len != 2
14446                   || (last[0] != 'X'
14447                       && last[0] != 'L'))
14448                 {
14449                   SAVE_LAST (*p);
14450                   break;
14451                 }
14452               if (!need_vex)
14453                 abort ();
14454               if (last[0] == 'X')
14455                 *obufp++ = vex.w ? 'd': 's';
14456               else
14457                 *obufp++ = vex.w ? 'q': 'd';
14458             }
14459           break;
14460         case '^':
14461           if (intel_syntax)
14462             break;
14463           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
14464             {
14465               if (sizeflag & DFLAG)
14466                 *obufp++ = 'l';
14467               else
14468                 *obufp++ = 'w';
14469               used_prefixes |= (prefixes & PREFIX_DATA);
14470             }
14471           break;
14472         case '@':
14473           if (intel_syntax)
14474             break;
14475           if (address_mode == mode_64bit
14476               && (isa64 == intel64
14477                   || ((sizeflag & DFLAG) || (rex & REX_W))))
14478               *obufp++ = 'q';
14479           else if ((prefixes & PREFIX_DATA))
14480             {
14481               if (!(sizeflag & DFLAG))
14482                 *obufp++ = 'w';
14483               used_prefixes |= (prefixes & PREFIX_DATA);
14484             }
14485           break;
14486         }
14487       alt = 0;
14488     }
14489   *obufp = 0;
14490   mnemonicendp = obufp;
14491   return 0;
14492 }
14493
14494 static void
14495 oappend (const char *s)
14496 {
14497   obufp = stpcpy (obufp, s);
14498 }
14499
14500 static void
14501 append_seg (void)
14502 {
14503   /* Only print the active segment register.  */
14504   if (!active_seg_prefix)
14505     return;
14506
14507   used_prefixes |= active_seg_prefix;
14508   switch (active_seg_prefix)
14509     {
14510     case PREFIX_CS:
14511       oappend_maybe_intel ("%cs:");
14512       break;
14513     case PREFIX_DS:
14514       oappend_maybe_intel ("%ds:");
14515       break;
14516     case PREFIX_SS:
14517       oappend_maybe_intel ("%ss:");
14518       break;
14519     case PREFIX_ES:
14520       oappend_maybe_intel ("%es:");
14521       break;
14522     case PREFIX_FS:
14523       oappend_maybe_intel ("%fs:");
14524       break;
14525     case PREFIX_GS:
14526       oappend_maybe_intel ("%gs:");
14527       break;
14528     default:
14529       break;
14530     }
14531 }
14532
14533 static void
14534 OP_indirE (int bytemode, int sizeflag)
14535 {
14536   if (!intel_syntax)
14537     oappend ("*");
14538   OP_E (bytemode, sizeflag);
14539 }
14540
14541 static void
14542 print_operand_value (char *buf, int hex, bfd_vma disp)
14543 {
14544   if (address_mode == mode_64bit)
14545     {
14546       if (hex)
14547         {
14548           char tmp[30];
14549           int i;
14550           buf[0] = '0';
14551           buf[1] = 'x';
14552           sprintf_vma (tmp, disp);
14553           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
14554           strcpy (buf + 2, tmp + i);
14555         }
14556       else
14557         {
14558           bfd_signed_vma v = disp;
14559           char tmp[30];
14560           int i;
14561           if (v < 0)
14562             {
14563               *(buf++) = '-';
14564               v = -disp;
14565               /* Check for possible overflow on 0x8000000000000000.  */
14566               if (v < 0)
14567                 {
14568                   strcpy (buf, "9223372036854775808");
14569                   return;
14570                 }
14571             }
14572           if (!v)
14573             {
14574               strcpy (buf, "0");
14575               return;
14576             }
14577
14578           i = 0;
14579           tmp[29] = 0;
14580           while (v)
14581             {
14582               tmp[28 - i] = (v % 10) + '0';
14583               v /= 10;
14584               i++;
14585             }
14586           strcpy (buf, tmp + 29 - i);
14587         }
14588     }
14589   else
14590     {
14591       if (hex)
14592         sprintf (buf, "0x%x", (unsigned int) disp);
14593       else
14594         sprintf (buf, "%d", (int) disp);
14595     }
14596 }
14597
14598 /* Put DISP in BUF as signed hex number.  */
14599
14600 static void
14601 print_displacement (char *buf, bfd_vma disp)
14602 {
14603   bfd_signed_vma val = disp;
14604   char tmp[30];
14605   int i, j = 0;
14606
14607   if (val < 0)
14608     {
14609       buf[j++] = '-';
14610       val = -disp;
14611
14612       /* Check for possible overflow.  */
14613       if (val < 0)
14614         {
14615           switch (address_mode)
14616             {
14617             case mode_64bit:
14618               strcpy (buf + j, "0x8000000000000000");
14619               break;
14620             case mode_32bit:
14621               strcpy (buf + j, "0x80000000");
14622               break;
14623             case mode_16bit:
14624               strcpy (buf + j, "0x8000");
14625               break;
14626             }
14627           return;
14628         }
14629     }
14630
14631   buf[j++] = '0';
14632   buf[j++] = 'x';
14633
14634   sprintf_vma (tmp, (bfd_vma) val);
14635   for (i = 0; tmp[i] == '0'; i++)
14636     continue;
14637   if (tmp[i] == '\0')
14638     i--;
14639   strcpy (buf + j, tmp + i);
14640 }
14641
14642 static void
14643 intel_operand_size (int bytemode, int sizeflag)
14644 {
14645   if (vex.evex
14646       && vex.b
14647       && (bytemode == x_mode
14648           || bytemode == evex_half_bcst_xmmq_mode))
14649     {
14650       if (vex.w)
14651         oappend ("QWORD PTR ");
14652       else
14653         oappend ("DWORD PTR ");
14654       return;
14655     }
14656   switch (bytemode)
14657     {
14658     case b_mode:
14659     case b_swap_mode:
14660     case dqb_mode:
14661     case db_mode:
14662       oappend ("BYTE PTR ");
14663       break;
14664     case w_mode:
14665     case dw_mode:
14666     case dqw_mode:
14667       oappend ("WORD PTR ");
14668       break;
14669     case indir_v_mode:
14670       if (address_mode == mode_64bit && isa64 == intel64)
14671         {
14672           oappend ("QWORD PTR ");
14673           break;
14674         }
14675       /* Fall through.  */
14676     case stack_v_mode:
14677       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14678         {
14679           oappend ("QWORD PTR ");
14680           break;
14681         }
14682       /* Fall through.  */
14683     case v_mode:
14684     case v_swap_mode:
14685     case dq_mode:
14686       USED_REX (REX_W);
14687       if (rex & REX_W)
14688         oappend ("QWORD PTR ");
14689       else
14690         {
14691           if ((sizeflag & DFLAG) || bytemode == dq_mode)
14692             oappend ("DWORD PTR ");
14693           else
14694             oappend ("WORD PTR ");
14695           used_prefixes |= (prefixes & PREFIX_DATA);
14696         }
14697       break;
14698     case z_mode:
14699       if ((rex & REX_W) || (sizeflag & DFLAG))
14700         *obufp++ = 'D';
14701       oappend ("WORD PTR ");
14702       if (!(rex & REX_W))
14703         used_prefixes |= (prefixes & PREFIX_DATA);
14704       break;
14705     case a_mode:
14706       if (sizeflag & DFLAG)
14707         oappend ("QWORD PTR ");
14708       else
14709         oappend ("DWORD PTR ");
14710       used_prefixes |= (prefixes & PREFIX_DATA);
14711       break;
14712     case d_mode:
14713     case d_scalar_mode:
14714     case d_scalar_swap_mode:
14715     case d_swap_mode:
14716     case dqd_mode:
14717       oappend ("DWORD PTR ");
14718       break;
14719     case q_mode:
14720     case q_scalar_mode:
14721     case q_scalar_swap_mode:
14722     case q_swap_mode:
14723       oappend ("QWORD PTR ");
14724       break;
14725     case m_mode:
14726       if (address_mode == mode_64bit)
14727         oappend ("QWORD PTR ");
14728       else
14729         oappend ("DWORD PTR ");
14730       break;
14731     case f_mode:
14732       if (sizeflag & DFLAG)
14733         oappend ("FWORD PTR ");
14734       else
14735         oappend ("DWORD PTR ");
14736       used_prefixes |= (prefixes & PREFIX_DATA);
14737       break;
14738     case t_mode:
14739       oappend ("TBYTE PTR ");
14740       break;
14741     case x_mode:
14742     case x_swap_mode:
14743     case evex_x_gscat_mode:
14744     case evex_x_nobcst_mode:
14745     case b_scalar_mode:
14746     case w_scalar_mode:
14747       if (need_vex)
14748         {
14749           switch (vex.length)
14750             {
14751             case 128:
14752               oappend ("XMMWORD PTR ");
14753               break;
14754             case 256:
14755               oappend ("YMMWORD PTR ");
14756               break;
14757             case 512:
14758               oappend ("ZMMWORD PTR ");
14759               break;
14760             default:
14761               abort ();
14762             }
14763         }
14764       else
14765         oappend ("XMMWORD PTR ");
14766       break;
14767     case xmm_mode:
14768       oappend ("XMMWORD PTR ");
14769       break;
14770     case ymm_mode:
14771       oappend ("YMMWORD PTR ");
14772       break;
14773     case xmmq_mode:
14774     case evex_half_bcst_xmmq_mode:
14775       if (!need_vex)
14776         abort ();
14777
14778       switch (vex.length)
14779         {
14780         case 128:
14781           oappend ("QWORD PTR ");
14782           break;
14783         case 256:
14784           oappend ("XMMWORD PTR ");
14785           break;
14786         case 512:
14787           oappend ("YMMWORD PTR ");
14788           break;
14789         default:
14790           abort ();
14791         }
14792       break;
14793     case xmm_mb_mode:
14794       if (!need_vex)
14795         abort ();
14796
14797       switch (vex.length)
14798         {
14799         case 128:
14800         case 256:
14801         case 512:
14802           oappend ("BYTE PTR ");
14803           break;
14804         default:
14805           abort ();
14806         }
14807       break;
14808     case xmm_mw_mode:
14809       if (!need_vex)
14810         abort ();
14811
14812       switch (vex.length)
14813         {
14814         case 128:
14815         case 256:
14816         case 512:
14817           oappend ("WORD PTR ");
14818           break;
14819         default:
14820           abort ();
14821         }
14822       break;
14823     case xmm_md_mode:
14824       if (!need_vex)
14825         abort ();
14826
14827       switch (vex.length)
14828         {
14829         case 128:
14830         case 256:
14831         case 512:
14832           oappend ("DWORD PTR ");
14833           break;
14834         default:
14835           abort ();
14836         }
14837       break;
14838     case xmm_mq_mode:
14839       if (!need_vex)
14840         abort ();
14841
14842       switch (vex.length)
14843         {
14844         case 128:
14845         case 256:
14846         case 512:
14847           oappend ("QWORD PTR ");
14848           break;
14849         default:
14850           abort ();
14851         }
14852       break;
14853     case xmmdw_mode:
14854       if (!need_vex)
14855         abort ();
14856
14857       switch (vex.length)
14858         {
14859         case 128:
14860           oappend ("WORD PTR ");
14861           break;
14862         case 256:
14863           oappend ("DWORD PTR ");
14864           break;
14865         case 512:
14866           oappend ("QWORD PTR ");
14867           break;
14868         default:
14869           abort ();
14870         }
14871       break;
14872     case xmmqd_mode:
14873       if (!need_vex)
14874         abort ();
14875
14876       switch (vex.length)
14877         {
14878         case 128:
14879           oappend ("DWORD PTR ");
14880           break;
14881         case 256:
14882           oappend ("QWORD PTR ");
14883           break;
14884         case 512:
14885           oappend ("XMMWORD PTR ");
14886           break;
14887         default:
14888           abort ();
14889         }
14890       break;
14891     case ymmq_mode:
14892       if (!need_vex)
14893         abort ();
14894
14895       switch (vex.length)
14896         {
14897         case 128:
14898           oappend ("QWORD PTR ");
14899           break;
14900         case 256:
14901           oappend ("YMMWORD PTR ");
14902           break;
14903         case 512:
14904           oappend ("ZMMWORD PTR ");
14905           break;
14906         default:
14907           abort ();
14908         }
14909       break;
14910     case ymmxmm_mode:
14911       if (!need_vex)
14912         abort ();
14913
14914       switch (vex.length)
14915         {
14916         case 128:
14917         case 256:
14918           oappend ("XMMWORD PTR ");
14919           break;
14920         default:
14921           abort ();
14922         }
14923       break;
14924     case o_mode:
14925       oappend ("OWORD PTR ");
14926       break;
14927     case xmm_mdq_mode:
14928     case vex_w_dq_mode:
14929     case vex_scalar_w_dq_mode:
14930       if (!need_vex)
14931         abort ();
14932
14933       if (vex.w)
14934         oappend ("QWORD PTR ");
14935       else
14936         oappend ("DWORD PTR ");
14937       break;
14938     case vex_vsib_d_w_dq_mode:
14939     case vex_vsib_q_w_dq_mode:
14940       if (!need_vex)
14941         abort ();
14942
14943       if (!vex.evex)
14944         {
14945           if (vex.w)
14946             oappend ("QWORD PTR ");
14947           else
14948             oappend ("DWORD PTR ");
14949         }
14950       else
14951         {
14952           switch (vex.length)
14953             {
14954             case 128:
14955               oappend ("XMMWORD PTR ");
14956               break;
14957             case 256:
14958               oappend ("YMMWORD PTR ");
14959               break;
14960             case 512:
14961               oappend ("ZMMWORD PTR ");
14962               break;
14963             default:
14964               abort ();
14965             }
14966         }
14967       break;
14968     case vex_vsib_q_w_d_mode:
14969     case vex_vsib_d_w_d_mode:
14970       if (!need_vex || !vex.evex)
14971         abort ();
14972
14973       switch (vex.length)
14974         {
14975         case 128:
14976           oappend ("QWORD PTR ");
14977           break;
14978         case 256:
14979           oappend ("XMMWORD PTR ");
14980           break;
14981         case 512:
14982           oappend ("YMMWORD PTR ");
14983           break;
14984         default:
14985           abort ();
14986         }
14987
14988       break;
14989     case mask_bd_mode:
14990       if (!need_vex || vex.length != 128)
14991         abort ();
14992       if (vex.w)
14993         oappend ("DWORD PTR ");
14994       else
14995         oappend ("BYTE PTR ");
14996       break;
14997     case mask_mode:
14998       if (!need_vex)
14999         abort ();
15000       if (vex.w)
15001         oappend ("QWORD PTR ");
15002       else
15003         oappend ("WORD PTR ");
15004       break;
15005     case v_bnd_mode:
15006     default:
15007       break;
15008     }
15009 }
15010
15011 static void
15012 OP_E_register (int bytemode, int sizeflag)
15013 {
15014   int reg = modrm.rm;
15015   const char **names;
15016
15017   USED_REX (REX_B);
15018   if ((rex & REX_B))
15019     reg += 8;
15020
15021   if ((sizeflag & SUFFIX_ALWAYS)
15022       && (bytemode == b_swap_mode
15023           || bytemode == v_swap_mode))
15024     swap_operand ();
15025
15026   switch (bytemode)
15027     {
15028     case b_mode:
15029     case b_swap_mode:
15030       USED_REX (0);
15031       if (rex)
15032         names = names8rex;
15033       else
15034         names = names8;
15035       break;
15036     case w_mode:
15037       names = names16;
15038       break;
15039     case d_mode:
15040     case dw_mode:
15041     case db_mode:
15042       names = names32;
15043       break;
15044     case q_mode:
15045       names = names64;
15046       break;
15047     case m_mode:
15048     case v_bnd_mode:
15049       names = address_mode == mode_64bit ? names64 : names32;
15050       break;
15051     case bnd_mode:
15052       if (reg > 0x3)
15053         {
15054           oappend ("(bad)");
15055           return;
15056         }
15057       names = names_bnd;
15058       break;
15059     case indir_v_mode:
15060       if (address_mode == mode_64bit && isa64 == intel64)
15061         {
15062           names = names64;
15063           break;
15064         }
15065       /* Fall through.  */
15066     case stack_v_mode:
15067       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
15068         {
15069           names = names64;
15070           break;
15071         }
15072       bytemode = v_mode;
15073       /* Fall through.  */
15074     case v_mode:
15075     case v_swap_mode:
15076     case dq_mode:
15077     case dqb_mode:
15078     case dqd_mode:
15079     case dqw_mode:
15080       USED_REX (REX_W);
15081       if (rex & REX_W)
15082         names = names64;
15083       else
15084         {
15085           if ((sizeflag & DFLAG)
15086               || (bytemode != v_mode
15087                   && bytemode != v_swap_mode))
15088             names = names32;
15089           else
15090             names = names16;
15091           used_prefixes |= (prefixes & PREFIX_DATA);
15092         }
15093       break;
15094     case mask_bd_mode:
15095     case mask_mode:
15096       if (reg > 0x7)
15097         {
15098           oappend ("(bad)");
15099           return;
15100         }
15101       names = names_mask;
15102       break;
15103     case 0:
15104       return;
15105     default:
15106       oappend (INTERNAL_DISASSEMBLER_ERROR);
15107       return;
15108     }
15109   oappend (names[reg]);
15110 }
15111
15112 static void
15113 OP_E_memory (int bytemode, int sizeflag)
15114 {
15115   bfd_vma disp = 0;
15116   int add = (rex & REX_B) ? 8 : 0;
15117   int riprel = 0;
15118   int shift;
15119
15120   if (vex.evex)
15121     {
15122       /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0.  */
15123       if (vex.b
15124           && bytemode != x_mode
15125           && bytemode != xmmq_mode
15126           && bytemode != evex_half_bcst_xmmq_mode)
15127         {
15128           BadOp ();
15129           return;
15130         }
15131       switch (bytemode)
15132         {
15133         case dqw_mode:
15134         case dw_mode:
15135           shift = 1;
15136           break;
15137         case dqb_mode:
15138         case db_mode:
15139           shift = 0;
15140           break;
15141         case vex_vsib_d_w_dq_mode:
15142         case vex_vsib_d_w_d_mode:
15143         case vex_vsib_q_w_dq_mode:
15144         case vex_vsib_q_w_d_mode:
15145         case evex_x_gscat_mode:
15146         case xmm_mdq_mode:
15147           shift = vex.w ? 3 : 2;
15148           break;
15149         case x_mode:
15150         case evex_half_bcst_xmmq_mode:
15151         case xmmq_mode:
15152           if (vex.b)
15153             {
15154               shift = vex.w ? 3 : 2;
15155               break;
15156             }
15157           /* Fall through.  */
15158         case xmmqd_mode:
15159         case xmmdw_mode:
15160         case ymmq_mode:
15161         case evex_x_nobcst_mode:
15162         case x_swap_mode:
15163           switch (vex.length)
15164             {
15165             case 128:
15166               shift = 4;
15167               break;
15168             case 256:
15169               shift = 5;
15170               break;
15171             case 512:
15172               shift = 6;
15173               break;
15174             default:
15175               abort ();
15176             }
15177           break;
15178         case ymm_mode:
15179           shift = 5;
15180           break;
15181         case xmm_mode:
15182           shift = 4;
15183           break;
15184         case xmm_mq_mode:
15185         case q_mode:
15186         case q_scalar_mode:
15187         case q_swap_mode:
15188         case q_scalar_swap_mode:
15189           shift = 3;
15190           break;
15191         case dqd_mode:
15192         case xmm_md_mode:
15193         case d_mode:
15194         case d_scalar_mode:
15195         case d_swap_mode:
15196         case d_scalar_swap_mode:
15197           shift = 2;
15198           break;
15199     case w_scalar_mode:
15200         case xmm_mw_mode:
15201           shift = 1;
15202           break;
15203     case b_scalar_mode:
15204         case xmm_mb_mode:
15205           shift = 0;
15206           break;
15207         default:
15208           abort ();
15209         }
15210       /* Make necessary corrections to shift for modes that need it.
15211          For these modes we currently have shift 4, 5 or 6 depending on
15212          vex.length (it corresponds to xmmword, ymmword or zmmword
15213          operand).  We might want to make it 3, 4 or 5 (e.g. for
15214          xmmq_mode).  In case of broadcast enabled the corrections
15215          aren't needed, as element size is always 32 or 64 bits.  */
15216       if (!vex.b
15217           && (bytemode == xmmq_mode
15218               || bytemode == evex_half_bcst_xmmq_mode))
15219         shift -= 1;
15220       else if (bytemode == xmmqd_mode)
15221         shift -= 2;
15222       else if (bytemode == xmmdw_mode)
15223         shift -= 3;
15224       else if (bytemode == ymmq_mode && vex.length == 128)
15225         shift -= 1;
15226     }
15227   else
15228     shift = 0;
15229
15230   USED_REX (REX_B);
15231   if (intel_syntax)
15232     intel_operand_size (bytemode, sizeflag);
15233   append_seg ();
15234
15235   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
15236     {
15237       /* 32/64 bit address mode */
15238       int havedisp;
15239       int havesib;
15240       int havebase;
15241       int haveindex;
15242       int needindex;
15243       int base, rbase;
15244       int vindex = 0;
15245       int scale = 0;
15246       int addr32flag = !((sizeflag & AFLAG)
15247                          || bytemode == v_bnd_mode
15248                          || bytemode == bnd_mode);
15249       const char **indexes64 = names64;
15250       const char **indexes32 = names32;
15251
15252       havesib = 0;
15253       havebase = 1;
15254       haveindex = 0;
15255       base = modrm.rm;
15256
15257       if (base == 4)
15258         {
15259           havesib = 1;
15260           vindex = sib.index;
15261           USED_REX (REX_X);
15262           if (rex & REX_X)
15263             vindex += 8;
15264           switch (bytemode)
15265             {
15266             case vex_vsib_d_w_dq_mode:
15267             case vex_vsib_d_w_d_mode:
15268             case vex_vsib_q_w_dq_mode:
15269             case vex_vsib_q_w_d_mode:
15270               if (!need_vex)
15271                 abort ();
15272               if (vex.evex)
15273                 {
15274                   if (!vex.v)
15275                     vindex += 16;
15276                 }
15277
15278               haveindex = 1;
15279               switch (vex.length)
15280                 {
15281                 case 128:
15282                   indexes64 = indexes32 = names_xmm;
15283                   break;
15284                 case 256:
15285                   if (!vex.w
15286                       || bytemode == vex_vsib_q_w_dq_mode
15287                       || bytemode == vex_vsib_q_w_d_mode)
15288                     indexes64 = indexes32 = names_ymm;
15289                   else
15290                     indexes64 = indexes32 = names_xmm;
15291                   break;
15292                 case 512:
15293                   if (!vex.w
15294                       || bytemode == vex_vsib_q_w_dq_mode
15295                       || bytemode == vex_vsib_q_w_d_mode)
15296                     indexes64 = indexes32 = names_zmm;
15297                   else
15298                     indexes64 = indexes32 = names_ymm;
15299                   break;
15300                 default:
15301                   abort ();
15302                 }
15303               break;
15304             default:
15305               haveindex = vindex != 4;
15306               break;
15307             }
15308           scale = sib.scale;
15309           base = sib.base;
15310           codep++;
15311         }
15312       rbase = base + add;
15313
15314       switch (modrm.mod)
15315         {
15316         case 0:
15317           if (base == 5)
15318             {
15319               havebase = 0;
15320               if (address_mode == mode_64bit && !havesib)
15321                 riprel = 1;
15322               disp = get32s ();
15323             }
15324           break;
15325         case 1:
15326           FETCH_DATA (the_info, codep + 1);
15327           disp = *codep++;
15328           if ((disp & 0x80) != 0)
15329             disp -= 0x100;
15330           if (vex.evex && shift > 0)
15331             disp <<= shift;
15332           break;
15333         case 2:
15334           disp = get32s ();
15335           break;
15336         }
15337
15338       /* In 32bit mode, we need index register to tell [offset] from
15339          [eiz*1 + offset].  */
15340       needindex = (havesib
15341                    && !havebase
15342                    && !haveindex
15343                    && address_mode == mode_32bit);
15344       havedisp = (havebase
15345                   || needindex
15346                   || (havesib && (haveindex || scale != 0)));
15347
15348       if (!intel_syntax)
15349         if (modrm.mod != 0 || base == 5)
15350           {
15351             if (havedisp || riprel)
15352               print_displacement (scratchbuf, disp);
15353             else
15354               print_operand_value (scratchbuf, 1, disp);
15355             oappend (scratchbuf);
15356             if (riprel)
15357               {
15358                 set_op (disp, 1);
15359                 oappend (!addr32flag ? "(%rip)" : "(%eip)");
15360               }
15361           }
15362
15363       if ((havebase || haveindex || riprel)
15364           && (bytemode != v_bnd_mode)
15365           && (bytemode != bnd_mode))
15366         used_prefixes |= PREFIX_ADDR;
15367
15368       if (havedisp || (intel_syntax && riprel))
15369         {
15370           *obufp++ = open_char;
15371           if (intel_syntax && riprel)
15372             {
15373               set_op (disp, 1);
15374               oappend (!addr32flag ? "rip" : "eip");
15375             }
15376           *obufp = '\0';
15377           if (havebase)
15378             oappend (address_mode == mode_64bit && !addr32flag
15379                      ? names64[rbase] : names32[rbase]);
15380           if (havesib)
15381             {
15382               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
15383                  print index to tell base + index from base.  */
15384               if (scale != 0
15385                   || needindex
15386                   || haveindex
15387                   || (havebase && base != ESP_REG_NUM))
15388                 {
15389                   if (!intel_syntax || havebase)
15390                     {
15391                       *obufp++ = separator_char;
15392                       *obufp = '\0';
15393                     }
15394                   if (haveindex)
15395                     oappend (address_mode == mode_64bit && !addr32flag
15396                              ? indexes64[vindex] : indexes32[vindex]);
15397                   else
15398                     oappend (address_mode == mode_64bit && !addr32flag
15399                              ? index64 : index32);
15400
15401                   *obufp++ = scale_char;
15402                   *obufp = '\0';
15403                   sprintf (scratchbuf, "%d", 1 << scale);
15404                   oappend (scratchbuf);
15405                 }
15406             }
15407           if (intel_syntax
15408               && (disp || modrm.mod != 0 || base == 5))
15409             {
15410               if (!havedisp || (bfd_signed_vma) disp >= 0)
15411                 {
15412                   *obufp++ = '+';
15413                   *obufp = '\0';
15414                 }
15415               else if (modrm.mod != 1 && disp != -disp)
15416                 {
15417                   *obufp++ = '-';
15418                   *obufp = '\0';
15419                   disp = - (bfd_signed_vma) disp;
15420                 }
15421
15422               if (havedisp)
15423                 print_displacement (scratchbuf, disp);
15424               else
15425                 print_operand_value (scratchbuf, 1, disp);
15426               oappend (scratchbuf);
15427             }
15428
15429           *obufp++ = close_char;
15430           *obufp = '\0';
15431         }
15432       else if (intel_syntax)
15433         {
15434           if (modrm.mod != 0 || base == 5)
15435             {
15436               if (!active_seg_prefix)
15437                 {
15438                   oappend (names_seg[ds_reg - es_reg]);
15439                   oappend (":");
15440                 }
15441               print_operand_value (scratchbuf, 1, disp);
15442               oappend (scratchbuf);
15443             }
15444         }
15445     }
15446   else
15447     {
15448       /* 16 bit address mode */
15449       used_prefixes |= prefixes & PREFIX_ADDR;
15450       switch (modrm.mod)
15451         {
15452         case 0:
15453           if (modrm.rm == 6)
15454             {
15455               disp = get16 ();
15456               if ((disp & 0x8000) != 0)
15457                 disp -= 0x10000;
15458             }
15459           break;
15460         case 1:
15461           FETCH_DATA (the_info, codep + 1);
15462           disp = *codep++;
15463           if ((disp & 0x80) != 0)
15464             disp -= 0x100;
15465           break;
15466         case 2:
15467           disp = get16 ();
15468           if ((disp & 0x8000) != 0)
15469             disp -= 0x10000;
15470           break;
15471         }
15472
15473       if (!intel_syntax)
15474         if (modrm.mod != 0 || modrm.rm == 6)
15475           {
15476             print_displacement (scratchbuf, disp);
15477             oappend (scratchbuf);
15478           }
15479
15480       if (modrm.mod != 0 || modrm.rm != 6)
15481         {
15482           *obufp++ = open_char;
15483           *obufp = '\0';
15484           oappend (index16[modrm.rm]);
15485           if (intel_syntax
15486               && (disp || modrm.mod != 0 || modrm.rm == 6))
15487             {
15488               if ((bfd_signed_vma) disp >= 0)
15489                 {
15490                   *obufp++ = '+';
15491                   *obufp = '\0';
15492                 }
15493               else if (modrm.mod != 1)
15494                 {
15495                   *obufp++ = '-';
15496                   *obufp = '\0';
15497                   disp = - (bfd_signed_vma) disp;
15498                 }
15499
15500               print_displacement (scratchbuf, disp);
15501               oappend (scratchbuf);
15502             }
15503
15504           *obufp++ = close_char;
15505           *obufp = '\0';
15506         }
15507       else if (intel_syntax)
15508         {
15509           if (!active_seg_prefix)
15510             {
15511               oappend (names_seg[ds_reg - es_reg]);
15512               oappend (":");
15513             }
15514           print_operand_value (scratchbuf, 1, disp & 0xffff);
15515           oappend (scratchbuf);
15516         }
15517     }
15518   if (vex.evex && vex.b
15519       && (bytemode == x_mode
15520           || bytemode == xmmq_mode
15521           || bytemode == evex_half_bcst_xmmq_mode))
15522     {
15523       if (vex.w
15524           || bytemode == xmmq_mode
15525           || bytemode == evex_half_bcst_xmmq_mode)
15526         {
15527           switch (vex.length)
15528             {
15529             case 128:
15530               oappend ("{1to2}");
15531               break;
15532             case 256:
15533               oappend ("{1to4}");
15534               break;
15535             case 512:
15536               oappend ("{1to8}");
15537               break;
15538             default:
15539               abort ();
15540             }
15541         }
15542       else
15543         {
15544           switch (vex.length)
15545             {
15546             case 128:
15547               oappend ("{1to4}");
15548               break;
15549             case 256:
15550               oappend ("{1to8}");
15551               break;
15552             case 512:
15553               oappend ("{1to16}");
15554               break;
15555             default:
15556               abort ();
15557             }
15558         }
15559     }
15560 }
15561
15562 static void
15563 OP_E (int bytemode, int sizeflag)
15564 {
15565   /* Skip mod/rm byte.  */
15566   MODRM_CHECK;
15567   codep++;
15568
15569   if (modrm.mod == 3)
15570     OP_E_register (bytemode, sizeflag);
15571   else
15572     OP_E_memory (bytemode, sizeflag);
15573 }
15574
15575 static void
15576 OP_G (int bytemode, int sizeflag)
15577 {
15578   int add = 0;
15579   USED_REX (REX_R);
15580   if (rex & REX_R)
15581     add += 8;
15582   switch (bytemode)
15583     {
15584     case b_mode:
15585       USED_REX (0);
15586       if (rex)
15587         oappend (names8rex[modrm.reg + add]);
15588       else
15589         oappend (names8[modrm.reg + add]);
15590       break;
15591     case w_mode:
15592       oappend (names16[modrm.reg + add]);
15593       break;
15594     case d_mode:
15595     case db_mode:
15596     case dw_mode:
15597       oappend (names32[modrm.reg + add]);
15598       break;
15599     case q_mode:
15600       oappend (names64[modrm.reg + add]);
15601       break;
15602     case bnd_mode:
15603       if (modrm.reg > 0x3)
15604         {
15605           oappend ("(bad)");
15606           return;
15607         }
15608       oappend (names_bnd[modrm.reg]);
15609       break;
15610     case v_mode:
15611     case dq_mode:
15612     case dqb_mode:
15613     case dqd_mode:
15614     case dqw_mode:
15615       USED_REX (REX_W);
15616       if (rex & REX_W)
15617         oappend (names64[modrm.reg + add]);
15618       else
15619         {
15620           if ((sizeflag & DFLAG) || bytemode != v_mode)
15621             oappend (names32[modrm.reg + add]);
15622           else
15623             oappend (names16[modrm.reg + add]);
15624           used_prefixes |= (prefixes & PREFIX_DATA);
15625         }
15626       break;
15627     case m_mode:
15628       if (address_mode == mode_64bit)
15629         oappend (names64[modrm.reg + add]);
15630       else
15631         oappend (names32[modrm.reg + add]);
15632       break;
15633     case mask_bd_mode:
15634     case mask_mode:
15635       if ((modrm.reg + add) > 0x7)
15636         {
15637           oappend ("(bad)");
15638           return;
15639         }
15640       oappend (names_mask[modrm.reg + add]);
15641       break;
15642     default:
15643       oappend (INTERNAL_DISASSEMBLER_ERROR);
15644       break;
15645     }
15646 }
15647
15648 static bfd_vma
15649 get64 (void)
15650 {
15651   bfd_vma x;
15652 #ifdef BFD64
15653   unsigned int a;
15654   unsigned int b;
15655
15656   FETCH_DATA (the_info, codep + 8);
15657   a = *codep++ & 0xff;
15658   a |= (*codep++ & 0xff) << 8;
15659   a |= (*codep++ & 0xff) << 16;
15660   a |= (*codep++ & 0xffu) << 24;
15661   b = *codep++ & 0xff;
15662   b |= (*codep++ & 0xff) << 8;
15663   b |= (*codep++ & 0xff) << 16;
15664   b |= (*codep++ & 0xffu) << 24;
15665   x = a + ((bfd_vma) b << 32);
15666 #else
15667   abort ();
15668   x = 0;
15669 #endif
15670   return x;
15671 }
15672
15673 static bfd_signed_vma
15674 get32 (void)
15675 {
15676   bfd_signed_vma x = 0;
15677
15678   FETCH_DATA (the_info, codep + 4);
15679   x = *codep++ & (bfd_signed_vma) 0xff;
15680   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15681   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15682   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15683   return x;
15684 }
15685
15686 static bfd_signed_vma
15687 get32s (void)
15688 {
15689   bfd_signed_vma x = 0;
15690
15691   FETCH_DATA (the_info, codep + 4);
15692   x = *codep++ & (bfd_signed_vma) 0xff;
15693   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15694   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15695   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15696
15697   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
15698
15699   return x;
15700 }
15701
15702 static int
15703 get16 (void)
15704 {
15705   int x = 0;
15706
15707   FETCH_DATA (the_info, codep + 2);
15708   x = *codep++ & 0xff;
15709   x |= (*codep++ & 0xff) << 8;
15710   return x;
15711 }
15712
15713 static void
15714 set_op (bfd_vma op, int riprel)
15715 {
15716   op_index[op_ad] = op_ad;
15717   if (address_mode == mode_64bit)
15718     {
15719       op_address[op_ad] = op;
15720       op_riprel[op_ad] = riprel;
15721     }
15722   else
15723     {
15724       /* Mask to get a 32-bit address.  */
15725       op_address[op_ad] = op & 0xffffffff;
15726       op_riprel[op_ad] = riprel & 0xffffffff;
15727     }
15728 }
15729
15730 static void
15731 OP_REG (int code, int sizeflag)
15732 {
15733   const char *s;
15734   int add;
15735
15736   switch (code)
15737     {
15738     case es_reg: case ss_reg: case cs_reg:
15739     case ds_reg: case fs_reg: case gs_reg:
15740       oappend (names_seg[code - es_reg]);
15741       return;
15742     }
15743
15744   USED_REX (REX_B);
15745   if (rex & REX_B)
15746     add = 8;
15747   else
15748     add = 0;
15749
15750   switch (code)
15751     {
15752     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15753     case sp_reg: case bp_reg: case si_reg: case di_reg:
15754       s = names16[code - ax_reg + add];
15755       break;
15756     case al_reg: case ah_reg: case cl_reg: case ch_reg:
15757     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15758       USED_REX (0);
15759       if (rex)
15760         s = names8rex[code - al_reg + add];
15761       else
15762         s = names8[code - al_reg];
15763       break;
15764     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
15765     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
15766       if (address_mode == mode_64bit
15767           && ((sizeflag & DFLAG) || (rex & REX_W)))
15768         {
15769           s = names64[code - rAX_reg + add];
15770           break;
15771         }
15772       code += eAX_reg - rAX_reg;
15773       /* Fall through.  */
15774     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15775     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15776       USED_REX (REX_W);
15777       if (rex & REX_W)
15778         s = names64[code - eAX_reg + add];
15779       else
15780         {
15781           if (sizeflag & DFLAG)
15782             s = names32[code - eAX_reg + add];
15783           else
15784             s = names16[code - eAX_reg + add];
15785           used_prefixes |= (prefixes & PREFIX_DATA);
15786         }
15787       break;
15788     default:
15789       s = INTERNAL_DISASSEMBLER_ERROR;
15790       break;
15791     }
15792   oappend (s);
15793 }
15794
15795 static void
15796 OP_IMREG (int code, int sizeflag)
15797 {
15798   const char *s;
15799
15800   switch (code)
15801     {
15802     case indir_dx_reg:
15803       if (intel_syntax)
15804         s = "dx";
15805       else
15806         s = "(%dx)";
15807       break;
15808     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15809     case sp_reg: case bp_reg: case si_reg: case di_reg:
15810       s = names16[code - ax_reg];
15811       break;
15812     case es_reg: case ss_reg: case cs_reg:
15813     case ds_reg: case fs_reg: case gs_reg:
15814       s = names_seg[code - es_reg];
15815       break;
15816     case al_reg: case ah_reg: case cl_reg: case ch_reg:
15817     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15818       USED_REX (0);
15819       if (rex)
15820         s = names8rex[code - al_reg];
15821       else
15822         s = names8[code - al_reg];
15823       break;
15824     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15825     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15826       USED_REX (REX_W);
15827       if (rex & REX_W)
15828         s = names64[code - eAX_reg];
15829       else
15830         {
15831           if (sizeflag & DFLAG)
15832             s = names32[code - eAX_reg];
15833           else
15834             s = names16[code - eAX_reg];
15835           used_prefixes |= (prefixes & PREFIX_DATA);
15836         }
15837       break;
15838     case z_mode_ax_reg:
15839       if ((rex & REX_W) || (sizeflag & DFLAG))
15840         s = *names32;
15841       else
15842         s = *names16;
15843       if (!(rex & REX_W))
15844         used_prefixes |= (prefixes & PREFIX_DATA);
15845       break;
15846     default:
15847       s = INTERNAL_DISASSEMBLER_ERROR;
15848       break;
15849     }
15850   oappend (s);
15851 }
15852
15853 static void
15854 OP_I (int bytemode, int sizeflag)
15855 {
15856   bfd_signed_vma op;
15857   bfd_signed_vma mask = -1;
15858
15859   switch (bytemode)
15860     {
15861     case b_mode:
15862       FETCH_DATA (the_info, codep + 1);
15863       op = *codep++;
15864       mask = 0xff;
15865       break;
15866     case q_mode:
15867       if (address_mode == mode_64bit)
15868         {
15869           op = get32s ();
15870           break;
15871         }
15872       /* Fall through.  */
15873     case v_mode:
15874       USED_REX (REX_W);
15875       if (rex & REX_W)
15876         op = get32s ();
15877       else
15878         {
15879           if (sizeflag & DFLAG)
15880             {
15881               op = get32 ();
15882               mask = 0xffffffff;
15883             }
15884           else
15885             {
15886               op = get16 ();
15887               mask = 0xfffff;
15888             }
15889           used_prefixes |= (prefixes & PREFIX_DATA);
15890         }
15891       break;
15892     case w_mode:
15893       mask = 0xfffff;
15894       op = get16 ();
15895       break;
15896     case const_1_mode:
15897       if (intel_syntax)
15898         oappend ("1");
15899       return;
15900     default:
15901       oappend (INTERNAL_DISASSEMBLER_ERROR);
15902       return;
15903     }
15904
15905   op &= mask;
15906   scratchbuf[0] = '$';
15907   print_operand_value (scratchbuf + 1, 1, op);
15908   oappend_maybe_intel (scratchbuf);
15909   scratchbuf[0] = '\0';
15910 }
15911
15912 static void
15913 OP_I64 (int bytemode, int sizeflag)
15914 {
15915   bfd_signed_vma op;
15916   bfd_signed_vma mask = -1;
15917
15918   if (address_mode != mode_64bit)
15919     {
15920       OP_I (bytemode, sizeflag);
15921       return;
15922     }
15923
15924   switch (bytemode)
15925     {
15926     case b_mode:
15927       FETCH_DATA (the_info, codep + 1);
15928       op = *codep++;
15929       mask = 0xff;
15930       break;
15931     case v_mode:
15932       USED_REX (REX_W);
15933       if (rex & REX_W)
15934         op = get64 ();
15935       else
15936         {
15937           if (sizeflag & DFLAG)
15938             {
15939               op = get32 ();
15940               mask = 0xffffffff;
15941             }
15942           else
15943             {
15944               op = get16 ();
15945               mask = 0xfffff;
15946             }
15947           used_prefixes |= (prefixes & PREFIX_DATA);
15948         }
15949       break;
15950     case w_mode:
15951       mask = 0xfffff;
15952       op = get16 ();
15953       break;
15954     default:
15955       oappend (INTERNAL_DISASSEMBLER_ERROR);
15956       return;
15957     }
15958
15959   op &= mask;
15960   scratchbuf[0] = '$';
15961   print_operand_value (scratchbuf + 1, 1, op);
15962   oappend_maybe_intel (scratchbuf);
15963   scratchbuf[0] = '\0';
15964 }
15965
15966 static void
15967 OP_sI (int bytemode, int sizeflag)
15968 {
15969   bfd_signed_vma op;
15970
15971   switch (bytemode)
15972     {
15973     case b_mode:
15974     case b_T_mode:
15975       FETCH_DATA (the_info, codep + 1);
15976       op = *codep++;
15977       if ((op & 0x80) != 0)
15978         op -= 0x100;
15979       if (bytemode == b_T_mode)
15980         {
15981           if (address_mode != mode_64bit
15982               || !((sizeflag & DFLAG) || (rex & REX_W)))
15983             {
15984               /* The operand-size prefix is overridden by a REX prefix.  */
15985               if ((sizeflag & DFLAG) || (rex & REX_W))
15986                 op &= 0xffffffff;
15987               else
15988                 op &= 0xffff;
15989           }
15990         }
15991       else
15992         {
15993           if (!(rex & REX_W))
15994             {
15995               if (sizeflag & DFLAG)
15996                 op &= 0xffffffff;
15997               else
15998                 op &= 0xffff;
15999             }
16000         }
16001       break;
16002     case v_mode:
16003       /* The operand-size prefix is overridden by a REX prefix.  */
16004       if ((sizeflag & DFLAG) || (rex & REX_W))
16005         op = get32s ();
16006       else
16007         op = get16 ();
16008       break;
16009     default:
16010       oappend (INTERNAL_DISASSEMBLER_ERROR);
16011       return;
16012     }
16013
16014   scratchbuf[0] = '$';
16015   print_operand_value (scratchbuf + 1, 1, op);
16016   oappend_maybe_intel (scratchbuf);
16017 }
16018
16019 static void
16020 OP_J (int bytemode, int sizeflag)
16021 {
16022   bfd_vma disp;
16023   bfd_vma mask = -1;
16024   bfd_vma segment = 0;
16025
16026   switch (bytemode)
16027     {
16028     case b_mode:
16029       FETCH_DATA (the_info, codep + 1);
16030       disp = *codep++;
16031       if ((disp & 0x80) != 0)
16032         disp -= 0x100;
16033       break;
16034     case v_mode:
16035       if (isa64 == amd64)
16036         USED_REX (REX_W);
16037       if ((sizeflag & DFLAG)
16038           || (address_mode == mode_64bit
16039               && (isa64 != amd64 || (rex & REX_W))))
16040         disp = get32s ();
16041       else
16042         {
16043           disp = get16 ();
16044           if ((disp & 0x8000) != 0)
16045             disp -= 0x10000;
16046           /* In 16bit mode, address is wrapped around at 64k within
16047              the same segment.  Otherwise, a data16 prefix on a jump
16048              instruction means that the pc is masked to 16 bits after
16049              the displacement is added!  */
16050           mask = 0xffff;
16051           if ((prefixes & PREFIX_DATA) == 0)
16052             segment = ((start_pc + (codep - start_codep))
16053                        & ~((bfd_vma) 0xffff));
16054         }
16055       if (address_mode != mode_64bit
16056           || (isa64 == amd64 && !(rex & REX_W)))
16057         used_prefixes |= (prefixes & PREFIX_DATA);
16058       break;
16059     default:
16060       oappend (INTERNAL_DISASSEMBLER_ERROR);
16061       return;
16062     }
16063   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
16064   set_op (disp, 0);
16065   print_operand_value (scratchbuf, 1, disp);
16066   oappend (scratchbuf);
16067 }
16068
16069 static void
16070 OP_SEG (int bytemode, int sizeflag)
16071 {
16072   if (bytemode == w_mode)
16073     oappend (names_seg[modrm.reg]);
16074   else
16075     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
16076 }
16077
16078 static void
16079 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
16080 {
16081   int seg, offset;
16082
16083   if (sizeflag & DFLAG)
16084     {
16085       offset = get32 ();
16086       seg = get16 ();
16087     }
16088   else
16089     {
16090       offset = get16 ();
16091       seg = get16 ();
16092     }
16093   used_prefixes |= (prefixes & PREFIX_DATA);
16094   if (intel_syntax)
16095     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
16096   else
16097     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
16098   oappend (scratchbuf);
16099 }
16100
16101 static void
16102 OP_OFF (int bytemode, int sizeflag)
16103 {
16104   bfd_vma off;
16105
16106   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
16107     intel_operand_size (bytemode, sizeflag);
16108   append_seg ();
16109
16110   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
16111     off = get32 ();
16112   else
16113     off = get16 ();
16114
16115   if (intel_syntax)
16116     {
16117       if (!active_seg_prefix)
16118         {
16119           oappend (names_seg[ds_reg - es_reg]);
16120           oappend (":");
16121         }
16122     }
16123   print_operand_value (scratchbuf, 1, off);
16124   oappend (scratchbuf);
16125 }
16126
16127 static void
16128 OP_OFF64 (int bytemode, int sizeflag)
16129 {
16130   bfd_vma off;
16131
16132   if (address_mode != mode_64bit
16133       || (prefixes & PREFIX_ADDR))
16134     {
16135       OP_OFF (bytemode, sizeflag);
16136       return;
16137     }
16138
16139   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
16140     intel_operand_size (bytemode, sizeflag);
16141   append_seg ();
16142
16143   off = get64 ();
16144
16145   if (intel_syntax)
16146     {
16147       if (!active_seg_prefix)
16148         {
16149           oappend (names_seg[ds_reg - es_reg]);
16150           oappend (":");
16151         }
16152     }
16153   print_operand_value (scratchbuf, 1, off);
16154   oappend (scratchbuf);
16155 }
16156
16157 static void
16158 ptr_reg (int code, int sizeflag)
16159 {
16160   const char *s;
16161
16162   *obufp++ = open_char;
16163   used_prefixes |= (prefixes & PREFIX_ADDR);
16164   if (address_mode == mode_64bit)
16165     {
16166       if (!(sizeflag & AFLAG))
16167         s = names32[code - eAX_reg];
16168       else
16169         s = names64[code - eAX_reg];
16170     }
16171   else if (sizeflag & AFLAG)
16172     s = names32[code - eAX_reg];
16173   else
16174     s = names16[code - eAX_reg];
16175   oappend (s);
16176   *obufp++ = close_char;
16177   *obufp = 0;
16178 }
16179
16180 static void
16181 OP_ESreg (int code, int sizeflag)
16182 {
16183   if (intel_syntax)
16184     {
16185       switch (codep[-1])
16186         {
16187         case 0x6d:      /* insw/insl */
16188           intel_operand_size (z_mode, sizeflag);
16189           break;
16190         case 0xa5:      /* movsw/movsl/movsq */
16191         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
16192         case 0xab:      /* stosw/stosl */
16193         case 0xaf:      /* scasw/scasl */
16194           intel_operand_size (v_mode, sizeflag);
16195           break;
16196         default:
16197           intel_operand_size (b_mode, sizeflag);
16198         }
16199     }
16200   oappend_maybe_intel ("%es:");
16201   ptr_reg (code, sizeflag);
16202 }
16203
16204 static void
16205 OP_DSreg (int code, int sizeflag)
16206 {
16207   if (intel_syntax)
16208     {
16209       switch (codep[-1])
16210         {
16211         case 0x6f:      /* outsw/outsl */
16212           intel_operand_size (z_mode, sizeflag);
16213           break;
16214         case 0xa5:      /* movsw/movsl/movsq */
16215         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
16216         case 0xad:      /* lodsw/lodsl/lodsq */
16217           intel_operand_size (v_mode, sizeflag);
16218           break;
16219         default:
16220           intel_operand_size (b_mode, sizeflag);
16221         }
16222     }
16223   /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
16224      default segment register DS is printed.  */
16225   if (!active_seg_prefix)
16226     active_seg_prefix = PREFIX_DS;
16227   append_seg ();
16228   ptr_reg (code, sizeflag);
16229 }
16230
16231 static void
16232 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16233 {
16234   int add;
16235   if (rex & REX_R)
16236     {
16237       USED_REX (REX_R);
16238       add = 8;
16239     }
16240   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
16241     {
16242       all_prefixes[last_lock_prefix] = 0;
16243       used_prefixes |= PREFIX_LOCK;
16244       add = 8;
16245     }
16246   else
16247     add = 0;
16248   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
16249   oappend_maybe_intel (scratchbuf);
16250 }
16251
16252 static void
16253 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16254 {
16255   int add;
16256   USED_REX (REX_R);
16257   if (rex & REX_R)
16258     add = 8;
16259   else
16260     add = 0;
16261   if (intel_syntax)
16262     sprintf (scratchbuf, "db%d", modrm.reg + add);
16263   else
16264     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
16265   oappend (scratchbuf);
16266 }
16267
16268 static void
16269 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16270 {
16271   sprintf (scratchbuf, "%%tr%d", modrm.reg);
16272   oappend_maybe_intel (scratchbuf);
16273 }
16274
16275 static void
16276 OP_R (int bytemode, int sizeflag)
16277 {
16278   /* Skip mod/rm byte.  */
16279   MODRM_CHECK;
16280   codep++;
16281   OP_E_register (bytemode, sizeflag);
16282 }
16283
16284 static void
16285 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16286 {
16287   int reg = modrm.reg;
16288   const char **names;
16289
16290   used_prefixes |= (prefixes & PREFIX_DATA);
16291   if (prefixes & PREFIX_DATA)
16292     {
16293       names = names_xmm;
16294       USED_REX (REX_R);
16295       if (rex & REX_R)
16296         reg += 8;
16297     }
16298   else
16299     names = names_mm;
16300   oappend (names[reg]);
16301 }
16302
16303 static void
16304 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16305 {
16306   int reg = modrm.reg;
16307   const char **names;
16308
16309   USED_REX (REX_R);
16310   if (rex & REX_R)
16311     reg += 8;
16312   if (vex.evex)
16313     {
16314       if (!vex.r)
16315         reg += 16;
16316     }
16317
16318   if (need_vex
16319       && bytemode != xmm_mode
16320       && bytemode != xmmq_mode
16321       && bytemode != evex_half_bcst_xmmq_mode
16322       && bytemode != ymm_mode
16323       && bytemode != scalar_mode)
16324     {
16325       switch (vex.length)
16326         {
16327         case 128:
16328           names = names_xmm;
16329           break;
16330         case 256:
16331           if (vex.w
16332               || (bytemode != vex_vsib_q_w_dq_mode
16333                   && bytemode != vex_vsib_q_w_d_mode))
16334             names = names_ymm;
16335           else
16336             names = names_xmm;
16337           break;
16338         case 512:
16339           names = names_zmm;
16340           break;
16341         default:
16342           abort ();
16343         }
16344     }
16345   else if (bytemode == xmmq_mode
16346            || bytemode == evex_half_bcst_xmmq_mode)
16347     {
16348       switch (vex.length)
16349         {
16350         case 128:
16351         case 256:
16352           names = names_xmm;
16353           break;
16354         case 512:
16355           names = names_ymm;
16356           break;
16357         default:
16358           abort ();
16359         }
16360     }
16361   else if (bytemode == ymm_mode)
16362     names = names_ymm;
16363   else
16364     names = names_xmm;
16365   oappend (names[reg]);
16366 }
16367
16368 static void
16369 OP_EM (int bytemode, int sizeflag)
16370 {
16371   int reg;
16372   const char **names;
16373
16374   if (modrm.mod != 3)
16375     {
16376       if (intel_syntax
16377           && (bytemode == v_mode || bytemode == v_swap_mode))
16378         {
16379           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16380           used_prefixes |= (prefixes & PREFIX_DATA);
16381         }
16382       OP_E (bytemode, sizeflag);
16383       return;
16384     }
16385
16386   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
16387     swap_operand ();
16388
16389   /* Skip mod/rm byte.  */
16390   MODRM_CHECK;
16391   codep++;
16392   used_prefixes |= (prefixes & PREFIX_DATA);
16393   reg = modrm.rm;
16394   if (prefixes & PREFIX_DATA)
16395     {
16396       names = names_xmm;
16397       USED_REX (REX_B);
16398       if (rex & REX_B)
16399         reg += 8;
16400     }
16401   else
16402     names = names_mm;
16403   oappend (names[reg]);
16404 }
16405
16406 /* cvt* are the only instructions in sse2 which have
16407    both SSE and MMX operands and also have 0x66 prefix
16408    in their opcode. 0x66 was originally used to differentiate
16409    between SSE and MMX instruction(operands). So we have to handle the
16410    cvt* separately using OP_EMC and OP_MXC */
16411 static void
16412 OP_EMC (int bytemode, int sizeflag)
16413 {
16414   if (modrm.mod != 3)
16415     {
16416       if (intel_syntax && bytemode == v_mode)
16417         {
16418           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16419           used_prefixes |= (prefixes & PREFIX_DATA);
16420         }
16421       OP_E (bytemode, sizeflag);
16422       return;
16423     }
16424
16425   /* Skip mod/rm byte.  */
16426   MODRM_CHECK;
16427   codep++;
16428   used_prefixes |= (prefixes & PREFIX_DATA);
16429   oappend (names_mm[modrm.rm]);
16430 }
16431
16432 static void
16433 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16434 {
16435   used_prefixes |= (prefixes & PREFIX_DATA);
16436   oappend (names_mm[modrm.reg]);
16437 }
16438
16439 static void
16440 OP_EX (int bytemode, int sizeflag)
16441 {
16442   int reg;
16443   const char **names;
16444
16445   /* Skip mod/rm byte.  */
16446   MODRM_CHECK;
16447   codep++;
16448
16449   if (modrm.mod != 3)
16450     {
16451       OP_E_memory (bytemode, sizeflag);
16452       return;
16453     }
16454
16455   reg = modrm.rm;
16456   USED_REX (REX_B);
16457   if (rex & REX_B)
16458     reg += 8;
16459   if (vex.evex)
16460     {
16461       USED_REX (REX_X);
16462       if ((rex & REX_X))
16463         reg += 16;
16464     }
16465
16466   if ((sizeflag & SUFFIX_ALWAYS)
16467       && (bytemode == x_swap_mode
16468           || bytemode == d_swap_mode
16469           || bytemode == d_scalar_swap_mode
16470           || bytemode == q_swap_mode
16471           || bytemode == q_scalar_swap_mode))
16472     swap_operand ();
16473
16474   if (need_vex
16475       && bytemode != xmm_mode
16476       && bytemode != xmmdw_mode
16477       && bytemode != xmmqd_mode
16478       && bytemode != xmm_mb_mode
16479       && bytemode != xmm_mw_mode
16480       && bytemode != xmm_md_mode
16481       && bytemode != xmm_mq_mode
16482       && bytemode != xmm_mdq_mode
16483       && bytemode != xmmq_mode
16484       && bytemode != evex_half_bcst_xmmq_mode
16485       && bytemode != ymm_mode
16486       && bytemode != d_scalar_mode
16487       && bytemode != d_scalar_swap_mode
16488       && bytemode != q_scalar_mode
16489       && bytemode != q_scalar_swap_mode
16490       && bytemode != vex_scalar_w_dq_mode)
16491     {
16492       switch (vex.length)
16493         {
16494         case 128:
16495           names = names_xmm;
16496           break;
16497         case 256:
16498           names = names_ymm;
16499           break;
16500         case 512:
16501           names = names_zmm;
16502           break;
16503         default:
16504           abort ();
16505         }
16506     }
16507   else if (bytemode == xmmq_mode
16508            || bytemode == evex_half_bcst_xmmq_mode)
16509     {
16510       switch (vex.length)
16511         {
16512         case 128:
16513         case 256:
16514           names = names_xmm;
16515           break;
16516         case 512:
16517           names = names_ymm;
16518           break;
16519         default:
16520           abort ();
16521         }
16522     }
16523   else if (bytemode == ymm_mode)
16524     names = names_ymm;
16525   else
16526     names = names_xmm;
16527   oappend (names[reg]);
16528 }
16529
16530 static void
16531 OP_MS (int bytemode, int sizeflag)
16532 {
16533   if (modrm.mod == 3)
16534     OP_EM (bytemode, sizeflag);
16535   else
16536     BadOp ();
16537 }
16538
16539 static void
16540 OP_XS (int bytemode, int sizeflag)
16541 {
16542   if (modrm.mod == 3)
16543     OP_EX (bytemode, sizeflag);
16544   else
16545     BadOp ();
16546 }
16547
16548 static void
16549 OP_M (int bytemode, int sizeflag)
16550 {
16551   if (modrm.mod == 3)
16552     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
16553     BadOp ();
16554   else
16555     OP_E (bytemode, sizeflag);
16556 }
16557
16558 static void
16559 OP_0f07 (int bytemode, int sizeflag)
16560 {
16561   if (modrm.mod != 3 || modrm.rm != 0)
16562     BadOp ();
16563   else
16564     OP_E (bytemode, sizeflag);
16565 }
16566
16567 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
16568    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
16569
16570 static void
16571 NOP_Fixup1 (int bytemode, int sizeflag)
16572 {
16573   if ((prefixes & PREFIX_DATA) != 0
16574       || (rex != 0
16575           && rex != 0x48
16576           && address_mode == mode_64bit))
16577     OP_REG (bytemode, sizeflag);
16578   else
16579     strcpy (obuf, "nop");
16580 }
16581
16582 static void
16583 NOP_Fixup2 (int bytemode, int sizeflag)
16584 {
16585   if ((prefixes & PREFIX_DATA) != 0
16586       || (rex != 0
16587           && rex != 0x48
16588           && address_mode == mode_64bit))
16589     OP_IMREG (bytemode, sizeflag);
16590 }
16591
16592 static const char *const Suffix3DNow[] = {
16593 /* 00 */        NULL,           NULL,           NULL,           NULL,
16594 /* 04 */        NULL,           NULL,           NULL,           NULL,
16595 /* 08 */        NULL,           NULL,           NULL,           NULL,
16596 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
16597 /* 10 */        NULL,           NULL,           NULL,           NULL,
16598 /* 14 */        NULL,           NULL,           NULL,           NULL,
16599 /* 18 */        NULL,           NULL,           NULL,           NULL,
16600 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
16601 /* 20 */        NULL,           NULL,           NULL,           NULL,
16602 /* 24 */        NULL,           NULL,           NULL,           NULL,
16603 /* 28 */        NULL,           NULL,           NULL,           NULL,
16604 /* 2C */        NULL,           NULL,           NULL,           NULL,
16605 /* 30 */        NULL,           NULL,           NULL,           NULL,
16606 /* 34 */        NULL,           NULL,           NULL,           NULL,
16607 /* 38 */        NULL,           NULL,           NULL,           NULL,
16608 /* 3C */        NULL,           NULL,           NULL,           NULL,
16609 /* 40 */        NULL,           NULL,           NULL,           NULL,
16610 /* 44 */        NULL,           NULL,           NULL,           NULL,
16611 /* 48 */        NULL,           NULL,           NULL,           NULL,
16612 /* 4C */        NULL,           NULL,           NULL,           NULL,
16613 /* 50 */        NULL,           NULL,           NULL,           NULL,
16614 /* 54 */        NULL,           NULL,           NULL,           NULL,
16615 /* 58 */        NULL,           NULL,           NULL,           NULL,
16616 /* 5C */        NULL,           NULL,           NULL,           NULL,
16617 /* 60 */        NULL,           NULL,           NULL,           NULL,
16618 /* 64 */        NULL,           NULL,           NULL,           NULL,
16619 /* 68 */        NULL,           NULL,           NULL,           NULL,
16620 /* 6C */        NULL,           NULL,           NULL,           NULL,
16621 /* 70 */        NULL,           NULL,           NULL,           NULL,
16622 /* 74 */        NULL,           NULL,           NULL,           NULL,
16623 /* 78 */        NULL,           NULL,           NULL,           NULL,
16624 /* 7C */        NULL,           NULL,           NULL,           NULL,
16625 /* 80 */        NULL,           NULL,           NULL,           NULL,
16626 /* 84 */        NULL,           NULL,           NULL,           NULL,
16627 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
16628 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
16629 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
16630 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
16631 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
16632 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
16633 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
16634 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
16635 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
16636 /* AC */        NULL,           NULL,           "pfacc",        NULL,
16637 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
16638 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
16639 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
16640 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
16641 /* C0 */        NULL,           NULL,           NULL,           NULL,
16642 /* C4 */        NULL,           NULL,           NULL,           NULL,
16643 /* C8 */        NULL,           NULL,           NULL,           NULL,
16644 /* CC */        NULL,           NULL,           NULL,           NULL,
16645 /* D0 */        NULL,           NULL,           NULL,           NULL,
16646 /* D4 */        NULL,           NULL,           NULL,           NULL,
16647 /* D8 */        NULL,           NULL,           NULL,           NULL,
16648 /* DC */        NULL,           NULL,           NULL,           NULL,
16649 /* E0 */        NULL,           NULL,           NULL,           NULL,
16650 /* E4 */        NULL,           NULL,           NULL,           NULL,
16651 /* E8 */        NULL,           NULL,           NULL,           NULL,
16652 /* EC */        NULL,           NULL,           NULL,           NULL,
16653 /* F0 */        NULL,           NULL,           NULL,           NULL,
16654 /* F4 */        NULL,           NULL,           NULL,           NULL,
16655 /* F8 */        NULL,           NULL,           NULL,           NULL,
16656 /* FC */        NULL,           NULL,           NULL,           NULL,
16657 };
16658
16659 static void
16660 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16661 {
16662   const char *mnemonic;
16663
16664   FETCH_DATA (the_info, codep + 1);
16665   /* AMD 3DNow! instructions are specified by an opcode suffix in the
16666      place where an 8-bit immediate would normally go.  ie. the last
16667      byte of the instruction.  */
16668   obufp = mnemonicendp;
16669   mnemonic = Suffix3DNow[*codep++ & 0xff];
16670   if (mnemonic)
16671     oappend (mnemonic);
16672   else
16673     {
16674       /* Since a variable sized modrm/sib chunk is between the start
16675          of the opcode (0x0f0f) and the opcode suffix, we need to do
16676          all the modrm processing first, and don't know until now that
16677          we have a bad opcode.  This necessitates some cleaning up.  */
16678       op_out[0][0] = '\0';
16679       op_out[1][0] = '\0';
16680       BadOp ();
16681     }
16682   mnemonicendp = obufp;
16683 }
16684
16685 static struct op simd_cmp_op[] =
16686 {
16687   { STRING_COMMA_LEN ("eq") },
16688   { STRING_COMMA_LEN ("lt") },
16689   { STRING_COMMA_LEN ("le") },
16690   { STRING_COMMA_LEN ("unord") },
16691   { STRING_COMMA_LEN ("neq") },
16692   { STRING_COMMA_LEN ("nlt") },
16693   { STRING_COMMA_LEN ("nle") },
16694   { STRING_COMMA_LEN ("ord") }
16695 };
16696
16697 static void
16698 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16699 {
16700   unsigned int cmp_type;
16701
16702   FETCH_DATA (the_info, codep + 1);
16703   cmp_type = *codep++ & 0xff;
16704   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
16705     {
16706       char suffix [3];
16707       char *p = mnemonicendp - 2;
16708       suffix[0] = p[0];
16709       suffix[1] = p[1];
16710       suffix[2] = '\0';
16711       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16712       mnemonicendp += simd_cmp_op[cmp_type].len;
16713     }
16714   else
16715     {
16716       /* We have a reserved extension byte.  Output it directly.  */
16717       scratchbuf[0] = '$';
16718       print_operand_value (scratchbuf + 1, 1, cmp_type);
16719       oappend_maybe_intel (scratchbuf);
16720       scratchbuf[0] = '\0';
16721     }
16722 }
16723
16724 static void
16725 OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED,
16726           int sizeflag ATTRIBUTE_UNUSED)
16727 {
16728   /* mwaitx %eax,%ecx,%ebx */
16729   if (!intel_syntax)
16730     {
16731       const char **names = (address_mode == mode_64bit
16732                             ? names64 : names32);
16733       strcpy (op_out[0], names[0]);
16734       strcpy (op_out[1], names[1]);
16735       strcpy (op_out[2], names[3]);
16736       two_source_ops = 1;
16737     }
16738   /* Skip mod/rm byte.  */
16739   MODRM_CHECK;
16740   codep++;
16741 }
16742
16743 static void
16744 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
16745           int sizeflag ATTRIBUTE_UNUSED)
16746 {
16747   /* mwait %eax,%ecx  */
16748   if (!intel_syntax)
16749     {
16750       const char **names = (address_mode == mode_64bit
16751                             ? names64 : names32);
16752       strcpy (op_out[0], names[0]);
16753       strcpy (op_out[1], names[1]);
16754       two_source_ops = 1;
16755     }
16756   /* Skip mod/rm byte.  */
16757   MODRM_CHECK;
16758   codep++;
16759 }
16760
16761 static void
16762 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
16763             int sizeflag ATTRIBUTE_UNUSED)
16764 {
16765   /* monitor %eax,%ecx,%edx"  */
16766   if (!intel_syntax)
16767     {
16768       const char **op1_names;
16769       const char **names = (address_mode == mode_64bit
16770                             ? names64 : names32);
16771
16772       if (!(prefixes & PREFIX_ADDR))
16773         op1_names = (address_mode == mode_16bit
16774                      ? names16 : names);
16775       else
16776         {
16777           /* Remove "addr16/addr32".  */
16778           all_prefixes[last_addr_prefix] = 0;
16779           op1_names = (address_mode != mode_32bit
16780                        ? names32 : names16);
16781           used_prefixes |= PREFIX_ADDR;
16782         }
16783       strcpy (op_out[0], op1_names[0]);
16784       strcpy (op_out[1], names[1]);
16785       strcpy (op_out[2], names[2]);
16786       two_source_ops = 1;
16787     }
16788   /* Skip mod/rm byte.  */
16789   MODRM_CHECK;
16790   codep++;
16791 }
16792
16793 static void
16794 BadOp (void)
16795 {
16796   /* Throw away prefixes and 1st. opcode byte.  */
16797   codep = insn_codep + 1;
16798   oappend ("(bad)");
16799 }
16800
16801 static void
16802 REP_Fixup (int bytemode, int sizeflag)
16803 {
16804   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
16805      lods and stos.  */
16806   if (prefixes & PREFIX_REPZ)
16807     all_prefixes[last_repz_prefix] = REP_PREFIX;
16808
16809   switch (bytemode)
16810     {
16811     case al_reg:
16812     case eAX_reg:
16813     case indir_dx_reg:
16814       OP_IMREG (bytemode, sizeflag);
16815       break;
16816     case eDI_reg:
16817       OP_ESreg (bytemode, sizeflag);
16818       break;
16819     case eSI_reg:
16820       OP_DSreg (bytemode, sizeflag);
16821       break;
16822     default:
16823       abort ();
16824       break;
16825     }
16826 }
16827
16828 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
16829    "bnd".  */
16830
16831 static void
16832 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16833 {
16834   if (prefixes & PREFIX_REPNZ)
16835     all_prefixes[last_repnz_prefix] = BND_PREFIX;
16836 }
16837
16838 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
16839    "notrack".  */
16840
16841 static void
16842 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED,
16843                int sizeflag ATTRIBUTE_UNUSED)
16844 {
16845   if (active_seg_prefix == PREFIX_DS
16846       && (address_mode != mode_64bit || last_data_prefix < 0))
16847     {
16848       /* NOTRACK prefix is only valid on indirect branch instructions.
16849          NB: DATA prefix is unsupported for Intel64.  */
16850       active_seg_prefix = 0;
16851       all_prefixes[last_seg_prefix] = NOTRACK_PREFIX;
16852     }
16853 }
16854
16855 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
16856    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
16857  */
16858
16859 static void
16860 HLE_Fixup1 (int bytemode, int sizeflag)
16861 {
16862   if (modrm.mod != 3
16863       && (prefixes & PREFIX_LOCK) != 0)
16864     {
16865       if (prefixes & PREFIX_REPZ)
16866         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16867       if (prefixes & PREFIX_REPNZ)
16868         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16869     }
16870
16871   OP_E (bytemode, sizeflag);
16872 }
16873
16874 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
16875    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
16876  */
16877
16878 static void
16879 HLE_Fixup2 (int bytemode, int sizeflag)
16880 {
16881   if (modrm.mod != 3)
16882     {
16883       if (prefixes & PREFIX_REPZ)
16884         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16885       if (prefixes & PREFIX_REPNZ)
16886         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16887     }
16888
16889   OP_E (bytemode, sizeflag);
16890 }
16891
16892 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
16893    "xrelease" for memory operand.  No check for LOCK prefix.   */
16894
16895 static void
16896 HLE_Fixup3 (int bytemode, int sizeflag)
16897 {
16898   if (modrm.mod != 3
16899       && last_repz_prefix > last_repnz_prefix
16900       && (prefixes & PREFIX_REPZ) != 0)
16901     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16902
16903   OP_E (bytemode, sizeflag);
16904 }
16905
16906 static void
16907 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
16908 {
16909   USED_REX (REX_W);
16910   if (rex & REX_W)
16911     {
16912       /* Change cmpxchg8b to cmpxchg16b.  */
16913       char *p = mnemonicendp - 2;
16914       mnemonicendp = stpcpy (p, "16b");
16915       bytemode = o_mode;
16916     }
16917   else if ((prefixes & PREFIX_LOCK) != 0)
16918     {
16919       if (prefixes & PREFIX_REPZ)
16920         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16921       if (prefixes & PREFIX_REPNZ)
16922         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16923     }
16924
16925   OP_M (bytemode, sizeflag);
16926 }
16927
16928 static void
16929 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
16930 {
16931   const char **names;
16932
16933   if (need_vex)
16934     {
16935       switch (vex.length)
16936         {
16937         case 128:
16938           names = names_xmm;
16939           break;
16940         case 256:
16941           names = names_ymm;
16942           break;
16943         default:
16944           abort ();
16945         }
16946     }
16947   else
16948     names = names_xmm;
16949   oappend (names[reg]);
16950 }
16951
16952 static void
16953 CRC32_Fixup (int bytemode, int sizeflag)
16954 {
16955   /* Add proper suffix to "crc32".  */
16956   char *p = mnemonicendp;
16957
16958   switch (bytemode)
16959     {
16960     case b_mode:
16961       if (intel_syntax)
16962         goto skip;
16963
16964       *p++ = 'b';
16965       break;
16966     case v_mode:
16967       if (intel_syntax)
16968         goto skip;
16969
16970       USED_REX (REX_W);
16971       if (rex & REX_W)
16972         *p++ = 'q';
16973       else
16974         {
16975           if (sizeflag & DFLAG)
16976             *p++ = 'l';
16977           else
16978             *p++ = 'w';
16979           used_prefixes |= (prefixes & PREFIX_DATA);
16980         }
16981       break;
16982     default:
16983       oappend (INTERNAL_DISASSEMBLER_ERROR);
16984       break;
16985     }
16986   mnemonicendp = p;
16987   *p = '\0';
16988
16989 skip:
16990   if (modrm.mod == 3)
16991     {
16992       int add;
16993
16994       /* Skip mod/rm byte.  */
16995       MODRM_CHECK;
16996       codep++;
16997
16998       USED_REX (REX_B);
16999       add = (rex & REX_B) ? 8 : 0;
17000       if (bytemode == b_mode)
17001         {
17002           USED_REX (0);
17003           if (rex)
17004             oappend (names8rex[modrm.rm + add]);
17005           else
17006             oappend (names8[modrm.rm + add]);
17007         }
17008       else
17009         {
17010           USED_REX (REX_W);
17011           if (rex & REX_W)
17012             oappend (names64[modrm.rm + add]);
17013           else if ((prefixes & PREFIX_DATA))
17014             oappend (names16[modrm.rm + add]);
17015           else
17016             oappend (names32[modrm.rm + add]);
17017         }
17018     }
17019   else
17020     OP_E (bytemode, sizeflag);
17021 }
17022
17023 static void
17024 FXSAVE_Fixup (int bytemode, int sizeflag)
17025 {
17026   /* Add proper suffix to "fxsave" and "fxrstor".  */
17027   USED_REX (REX_W);
17028   if (rex & REX_W)
17029     {
17030       char *p = mnemonicendp;
17031       *p++ = '6';
17032       *p++ = '4';
17033       *p = '\0';
17034       mnemonicendp = p;
17035     }
17036   OP_M (bytemode, sizeflag);
17037 }
17038
17039 static void
17040 PCMPESTR_Fixup (int bytemode, int sizeflag)
17041 {
17042   /* Add proper suffix to "{,v}pcmpestr{i,m}".  */
17043   if (!intel_syntax)
17044     {
17045       char *p = mnemonicendp;
17046
17047       USED_REX (REX_W);
17048       if (rex & REX_W)
17049         *p++ = 'q';
17050       else if (sizeflag & SUFFIX_ALWAYS)
17051         *p++ = 'l';
17052
17053       *p = '\0';
17054       mnemonicendp = p;
17055     }
17056
17057   OP_EX (bytemode, sizeflag);
17058 }
17059
17060 /* Display the destination register operand for instructions with
17061    VEX. */
17062
17063 static void
17064 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17065 {
17066   int reg;
17067   const char **names;
17068
17069   if (!need_vex)
17070     abort ();
17071
17072   if (!need_vex_reg)
17073     return;
17074
17075   reg = vex.register_specifier;
17076   if (vex.evex)
17077     {
17078       if (!vex.v)
17079         reg += 16;
17080     }
17081
17082   if (bytemode == vex_scalar_mode)
17083     {
17084       oappend (names_xmm[reg]);
17085       return;
17086     }
17087
17088   switch (vex.length)
17089     {
17090     case 128:
17091       switch (bytemode)
17092         {
17093         case vex_mode:
17094         case vex128_mode:
17095         case vex_vsib_q_w_dq_mode:
17096         case vex_vsib_q_w_d_mode:
17097           names = names_xmm;
17098           break;
17099         case dq_mode:
17100           if (vex.w)
17101             names = names64;
17102           else
17103             names = names32;
17104           break;
17105         case mask_bd_mode:
17106         case mask_mode:
17107           if (reg > 0x7)
17108             {
17109               oappend ("(bad)");
17110               return;
17111             }
17112           names = names_mask;
17113           break;
17114         default:
17115           abort ();
17116           return;
17117         }
17118       break;
17119     case 256:
17120       switch (bytemode)
17121         {
17122         case vex_mode:
17123         case vex256_mode:
17124           names = names_ymm;
17125           break;
17126         case vex_vsib_q_w_dq_mode:
17127         case vex_vsib_q_w_d_mode:
17128           names = vex.w ? names_ymm : names_xmm;
17129           break;
17130         case mask_bd_mode:
17131         case mask_mode:
17132           if (reg > 0x7)
17133             {
17134               oappend ("(bad)");
17135               return;
17136             }
17137           names = names_mask;
17138           break;
17139         default:
17140           /* See PR binutils/20893 for a reproducer.  */
17141           oappend ("(bad)");
17142           return;
17143         }
17144       break;
17145     case 512:
17146       names = names_zmm;
17147       break;
17148     default:
17149       abort ();
17150       break;
17151     }
17152   oappend (names[reg]);
17153 }
17154
17155 /* Get the VEX immediate byte without moving codep.  */
17156
17157 static unsigned char
17158 get_vex_imm8 (int sizeflag, int opnum)
17159 {
17160   int bytes_before_imm = 0;
17161
17162   if (modrm.mod != 3)
17163     {
17164       /* There are SIB/displacement bytes.  */
17165       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
17166         {
17167           /* 32/64 bit address mode */
17168           int base = modrm.rm;
17169
17170           /* Check SIB byte.  */
17171           if (base == 4)
17172             {
17173               FETCH_DATA (the_info, codep + 1);
17174               base = *codep & 7;
17175               /* When decoding the third source, don't increase
17176                  bytes_before_imm as this has already been incremented
17177                  by one in OP_E_memory while decoding the second
17178                  source operand.  */
17179               if (opnum == 0)
17180                 bytes_before_imm++;
17181             }
17182
17183           /* Don't increase bytes_before_imm when decoding the third source,
17184              it has already been incremented by OP_E_memory while decoding
17185              the second source operand.  */
17186           if (opnum == 0)
17187             {
17188               switch (modrm.mod)
17189                 {
17190                   case 0:
17191                     /* When modrm.rm == 5 or modrm.rm == 4 and base in
17192                        SIB == 5, there is a 4 byte displacement.  */
17193                     if (base != 5)
17194                       /* No displacement. */
17195                       break;
17196                     /* Fall through.  */
17197                   case 2:
17198                     /* 4 byte displacement.  */
17199                     bytes_before_imm += 4;
17200                     break;
17201                   case 1:
17202                     /* 1 byte displacement.  */
17203                     bytes_before_imm++;
17204                     break;
17205                 }
17206             }
17207         }
17208       else
17209         {
17210           /* 16 bit address mode */
17211           /* Don't increase bytes_before_imm when decoding the third source,
17212              it has already been incremented by OP_E_memory while decoding
17213              the second source operand.  */
17214           if (opnum == 0)
17215             {
17216               switch (modrm.mod)
17217                 {
17218                 case 0:
17219                   /* When modrm.rm == 6, there is a 2 byte displacement.  */
17220                   if (modrm.rm != 6)
17221                     /* No displacement. */
17222                     break;
17223                   /* Fall through.  */
17224                 case 2:
17225                   /* 2 byte displacement.  */
17226                   bytes_before_imm += 2;
17227                   break;
17228                 case 1:
17229                   /* 1 byte displacement: when decoding the third source,
17230                      don't increase bytes_before_imm as this has already
17231                      been incremented by one in OP_E_memory while decoding
17232                      the second source operand.  */
17233                   if (opnum == 0)
17234                     bytes_before_imm++;
17235
17236                   break;
17237                 }
17238             }
17239         }
17240     }
17241
17242   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
17243   return codep [bytes_before_imm];
17244 }
17245
17246 static void
17247 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
17248 {
17249   const char **names;
17250
17251   if (reg == -1 && modrm.mod != 3)
17252     {
17253       OP_E_memory (bytemode, sizeflag);
17254       return;
17255     }
17256   else
17257     {
17258       if (reg == -1)
17259         {
17260           reg = modrm.rm;
17261           USED_REX (REX_B);
17262           if (rex & REX_B)
17263             reg += 8;
17264         }
17265       else if (reg > 7 && address_mode != mode_64bit)
17266         BadOp ();
17267     }
17268
17269   switch (vex.length)
17270     {
17271     case 128:
17272       names = names_xmm;
17273       break;
17274     case 256:
17275       names = names_ymm;
17276       break;
17277     default:
17278       abort ();
17279     }
17280   oappend (names[reg]);
17281 }
17282
17283 static void
17284 OP_EX_VexImmW (int bytemode, int sizeflag)
17285 {
17286   int reg = -1;
17287   static unsigned char vex_imm8;
17288
17289   if (vex_w_done == 0)
17290     {
17291       vex_w_done = 1;
17292
17293       /* Skip mod/rm byte.  */
17294       MODRM_CHECK;
17295       codep++;
17296
17297       vex_imm8 = get_vex_imm8 (sizeflag, 0);
17298
17299       if (vex.w)
17300           reg = vex_imm8 >> 4;
17301
17302       OP_EX_VexReg (bytemode, sizeflag, reg);
17303     }
17304   else if (vex_w_done == 1)
17305     {
17306       vex_w_done = 2;
17307
17308       if (!vex.w)
17309           reg = vex_imm8 >> 4;
17310
17311       OP_EX_VexReg (bytemode, sizeflag, reg);
17312     }
17313   else
17314     {
17315       /* Output the imm8 directly.  */
17316       scratchbuf[0] = '$';
17317       print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
17318       oappend_maybe_intel (scratchbuf);
17319       scratchbuf[0] = '\0';
17320       codep++;
17321     }
17322 }
17323
17324 static void
17325 OP_Vex_2src (int bytemode, int sizeflag)
17326 {
17327   if (modrm.mod == 3)
17328     {
17329       int reg = modrm.rm;
17330       USED_REX (REX_B);
17331       if (rex & REX_B)
17332         reg += 8;
17333       oappend (names_xmm[reg]);
17334     }
17335   else
17336     {
17337       if (intel_syntax
17338           && (bytemode == v_mode || bytemode == v_swap_mode))
17339         {
17340           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
17341           used_prefixes |= (prefixes & PREFIX_DATA);
17342         }
17343       OP_E (bytemode, sizeflag);
17344     }
17345 }
17346
17347 static void
17348 OP_Vex_2src_1 (int bytemode, int sizeflag)
17349 {
17350   if (modrm.mod == 3)
17351     {
17352       /* Skip mod/rm byte.   */
17353       MODRM_CHECK;
17354       codep++;
17355     }
17356
17357   if (vex.w)
17358     oappend (names_xmm[vex.register_specifier]);
17359   else
17360     OP_Vex_2src (bytemode, sizeflag);
17361 }
17362
17363 static void
17364 OP_Vex_2src_2 (int bytemode, int sizeflag)
17365 {
17366   if (vex.w)
17367     OP_Vex_2src (bytemode, sizeflag);
17368   else
17369     oappend (names_xmm[vex.register_specifier]);
17370 }
17371
17372 static void
17373 OP_EX_VexW (int bytemode, int sizeflag)
17374 {
17375   int reg = -1;
17376
17377   if (!vex_w_done)
17378     {
17379       vex_w_done = 1;
17380
17381       /* Skip mod/rm byte.  */
17382       MODRM_CHECK;
17383       codep++;
17384
17385       if (vex.w)
17386         reg = get_vex_imm8 (sizeflag, 0) >> 4;
17387     }
17388   else
17389     {
17390       if (!vex.w)
17391         reg = get_vex_imm8 (sizeflag, 1) >> 4;
17392     }
17393
17394   OP_EX_VexReg (bytemode, sizeflag, reg);
17395 }
17396
17397 static void
17398 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,
17399              int sizeflag ATTRIBUTE_UNUSED)
17400 {
17401   /* Skip the immediate byte and check for invalid bits.  */
17402   FETCH_DATA (the_info, codep + 1);
17403   if (*codep++ & 0xf)
17404     BadOp ();
17405 }
17406
17407 static void
17408 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17409 {
17410   int reg;
17411   const char **names;
17412
17413   FETCH_DATA (the_info, codep + 1);
17414   reg = *codep++;
17415
17416   if (bytemode != x_mode)
17417     abort ();
17418
17419   if (reg & 0xf)
17420       BadOp ();
17421
17422   reg >>= 4;
17423   if (reg > 7 && address_mode != mode_64bit)
17424     BadOp ();
17425
17426   switch (vex.length)
17427     {
17428     case 128:
17429       names = names_xmm;
17430       break;
17431     case 256:
17432       names = names_ymm;
17433       break;
17434     default:
17435       abort ();
17436     }
17437   oappend (names[reg]);
17438 }
17439
17440 static void
17441 OP_XMM_VexW (int bytemode, int sizeflag)
17442 {
17443   /* Turn off the REX.W bit since it is used for swapping operands
17444      now.  */
17445   rex &= ~REX_W;
17446   OP_XMM (bytemode, sizeflag);
17447 }
17448
17449 static void
17450 OP_EX_Vex (int bytemode, int sizeflag)
17451 {
17452   if (modrm.mod != 3)
17453     {
17454       if (vex.register_specifier != 0)
17455         BadOp ();
17456       need_vex_reg = 0;
17457     }
17458   OP_EX (bytemode, sizeflag);
17459 }
17460
17461 static void
17462 OP_XMM_Vex (int bytemode, int sizeflag)
17463 {
17464   if (modrm.mod != 3)
17465     {
17466       if (vex.register_specifier != 0)
17467         BadOp ();
17468       need_vex_reg = 0;
17469     }
17470   OP_XMM (bytemode, sizeflag);
17471 }
17472
17473 static void
17474 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17475 {
17476   switch (vex.length)
17477     {
17478     case 128:
17479       mnemonicendp = stpcpy (obuf, "vzeroupper");
17480       break;
17481     case 256:
17482       mnemonicendp = stpcpy (obuf, "vzeroall");
17483       break;
17484     default:
17485       abort ();
17486     }
17487 }
17488
17489 static struct op vex_cmp_op[] =
17490 {
17491   { STRING_COMMA_LEN ("eq") },
17492   { STRING_COMMA_LEN ("lt") },
17493   { STRING_COMMA_LEN ("le") },
17494   { STRING_COMMA_LEN ("unord") },
17495   { STRING_COMMA_LEN ("neq") },
17496   { STRING_COMMA_LEN ("nlt") },
17497   { STRING_COMMA_LEN ("nle") },
17498   { STRING_COMMA_LEN ("ord") },
17499   { STRING_COMMA_LEN ("eq_uq") },
17500   { STRING_COMMA_LEN ("nge") },
17501   { STRING_COMMA_LEN ("ngt") },
17502   { STRING_COMMA_LEN ("false") },
17503   { STRING_COMMA_LEN ("neq_oq") },
17504   { STRING_COMMA_LEN ("ge") },
17505   { STRING_COMMA_LEN ("gt") },
17506   { STRING_COMMA_LEN ("true") },
17507   { STRING_COMMA_LEN ("eq_os") },
17508   { STRING_COMMA_LEN ("lt_oq") },
17509   { STRING_COMMA_LEN ("le_oq") },
17510   { STRING_COMMA_LEN ("unord_s") },
17511   { STRING_COMMA_LEN ("neq_us") },
17512   { STRING_COMMA_LEN ("nlt_uq") },
17513   { STRING_COMMA_LEN ("nle_uq") },
17514   { STRING_COMMA_LEN ("ord_s") },
17515   { STRING_COMMA_LEN ("eq_us") },
17516   { STRING_COMMA_LEN ("nge_uq") },
17517   { STRING_COMMA_LEN ("ngt_uq") },
17518   { STRING_COMMA_LEN ("false_os") },
17519   { STRING_COMMA_LEN ("neq_os") },
17520   { STRING_COMMA_LEN ("ge_oq") },
17521   { STRING_COMMA_LEN ("gt_oq") },
17522   { STRING_COMMA_LEN ("true_us") },
17523 };
17524
17525 static void
17526 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17527 {
17528   unsigned int cmp_type;
17529
17530   FETCH_DATA (the_info, codep + 1);
17531   cmp_type = *codep++ & 0xff;
17532   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
17533     {
17534       char suffix [3];
17535       char *p = mnemonicendp - 2;
17536       suffix[0] = p[0];
17537       suffix[1] = p[1];
17538       suffix[2] = '\0';
17539       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
17540       mnemonicendp += vex_cmp_op[cmp_type].len;
17541     }
17542   else
17543     {
17544       /* We have a reserved extension byte.  Output it directly.  */
17545       scratchbuf[0] = '$';
17546       print_operand_value (scratchbuf + 1, 1, cmp_type);
17547       oappend_maybe_intel (scratchbuf);
17548       scratchbuf[0] = '\0';
17549     }
17550 }
17551
17552 static void
17553 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
17554              int sizeflag ATTRIBUTE_UNUSED)
17555 {
17556   unsigned int cmp_type;
17557
17558   if (!vex.evex)
17559     abort ();
17560
17561   FETCH_DATA (the_info, codep + 1);
17562   cmp_type = *codep++ & 0xff;
17563   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
17564      If it's the case, print suffix, otherwise - print the immediate.  */
17565   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
17566       && cmp_type != 3
17567       && cmp_type != 7)
17568     {
17569       char suffix [3];
17570       char *p = mnemonicendp - 2;
17571
17572       /* vpcmp* can have both one- and two-lettered suffix.  */
17573       if (p[0] == 'p')
17574         {
17575           p++;
17576           suffix[0] = p[0];
17577           suffix[1] = '\0';
17578         }
17579       else
17580         {
17581           suffix[0] = p[0];
17582           suffix[1] = p[1];
17583           suffix[2] = '\0';
17584         }
17585
17586       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
17587       mnemonicendp += simd_cmp_op[cmp_type].len;
17588     }
17589   else
17590     {
17591       /* We have a reserved extension byte.  Output it directly.  */
17592       scratchbuf[0] = '$';
17593       print_operand_value (scratchbuf + 1, 1, cmp_type);
17594       oappend_maybe_intel (scratchbuf);
17595       scratchbuf[0] = '\0';
17596     }
17597 }
17598
17599 static const struct op pclmul_op[] =
17600 {
17601   { STRING_COMMA_LEN ("lql") },
17602   { STRING_COMMA_LEN ("hql") },
17603   { STRING_COMMA_LEN ("lqh") },
17604   { STRING_COMMA_LEN ("hqh") }
17605 };
17606
17607 static void
17608 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
17609               int sizeflag ATTRIBUTE_UNUSED)
17610 {
17611   unsigned int pclmul_type;
17612
17613   FETCH_DATA (the_info, codep + 1);
17614   pclmul_type = *codep++ & 0xff;
17615   switch (pclmul_type)
17616     {
17617     case 0x10:
17618       pclmul_type = 2;
17619       break;
17620     case 0x11:
17621       pclmul_type = 3;
17622       break;
17623     default:
17624       break;
17625     }
17626   if (pclmul_type < ARRAY_SIZE (pclmul_op))
17627     {
17628       char suffix [4];
17629       char *p = mnemonicendp - 3;
17630       suffix[0] = p[0];
17631       suffix[1] = p[1];
17632       suffix[2] = p[2];
17633       suffix[3] = '\0';
17634       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
17635       mnemonicendp += pclmul_op[pclmul_type].len;
17636     }
17637   else
17638     {
17639       /* We have a reserved extension byte.  Output it directly.  */
17640       scratchbuf[0] = '$';
17641       print_operand_value (scratchbuf + 1, 1, pclmul_type);
17642       oappend_maybe_intel (scratchbuf);
17643       scratchbuf[0] = '\0';
17644     }
17645 }
17646
17647 static void
17648 MOVBE_Fixup (int bytemode, int sizeflag)
17649 {
17650   /* Add proper suffix to "movbe".  */
17651   char *p = mnemonicendp;
17652
17653   switch (bytemode)
17654     {
17655     case v_mode:
17656       if (intel_syntax)
17657         goto skip;
17658
17659       USED_REX (REX_W);
17660       if (sizeflag & SUFFIX_ALWAYS)
17661         {
17662           if (rex & REX_W)
17663             *p++ = 'q';
17664           else
17665             {
17666               if (sizeflag & DFLAG)
17667                 *p++ = 'l';
17668               else
17669                 *p++ = 'w';
17670               used_prefixes |= (prefixes & PREFIX_DATA);
17671             }
17672         }
17673       break;
17674     default:
17675       oappend (INTERNAL_DISASSEMBLER_ERROR);
17676       break;
17677     }
17678   mnemonicendp = p;
17679   *p = '\0';
17680
17681 skip:
17682   OP_M (bytemode, sizeflag);
17683 }
17684
17685 static void
17686 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17687 {
17688   int reg;
17689   const char **names;
17690
17691   /* Skip mod/rm byte.  */
17692   MODRM_CHECK;
17693   codep++;
17694
17695   if (vex.w)
17696     names = names64;
17697   else
17698     names = names32;
17699
17700   reg = modrm.rm;
17701   USED_REX (REX_B);
17702   if (rex & REX_B)
17703     reg += 8;
17704
17705   oappend (names[reg]);
17706 }
17707
17708 static void
17709 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17710 {
17711   const char **names;
17712
17713   if (vex.w)
17714     names = names64;
17715   else
17716     names = names32;
17717
17718   oappend (names[vex.register_specifier]);
17719 }
17720
17721 static void
17722 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17723 {
17724   if (!vex.evex
17725       || (bytemode != mask_mode && bytemode != mask_bd_mode))
17726     abort ();
17727
17728   USED_REX (REX_R);
17729   if ((rex & REX_R) != 0 || !vex.r)
17730     {
17731       BadOp ();
17732       return;
17733     }
17734
17735   oappend (names_mask [modrm.reg]);
17736 }
17737
17738 static void
17739 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17740 {
17741   if (!vex.evex
17742       || (bytemode != evex_rounding_mode
17743           && bytemode != evex_sae_mode))
17744     abort ();
17745   if (modrm.mod == 3 && vex.b)
17746     switch (bytemode)
17747       {
17748       case evex_rounding_mode:
17749         oappend (names_rounding[vex.ll]);
17750         break;
17751       case evex_sae_mode:
17752         oappend ("{sae}");
17753         break;
17754       default:
17755         break;
17756       }
17757 }