1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright (C) 1988-2020 Free Software Foundation, Inc.
4 This file is part of the GNU opcodes library.
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
24 modified by John Hassey (hassey@dg-rtp.dg.com)
25 x86-64 support added by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
28 /* The main tables describing the instructions is essentially a copy
29 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
30 Programmers Manual. Usually, there is a capital letter, followed
31 by a small letter. The capital letter tell the addressing mode,
32 and the small letter tells about the operand size. Refer to
33 the Intel manual for details. */
36 #include "disassemble.h"
38 #include "opcode/i386.h"
39 #include "libiberty.h"
43 static int print_insn (bfd_vma
, disassemble_info
*);
44 static void dofloat (int);
45 static void OP_ST (int, int);
46 static void OP_STi (int, int);
47 static int putop (const char *, int);
48 static void oappend (const char *);
49 static void append_seg (void);
50 static void OP_indirE (int, int);
51 static void print_operand_value (char *, int, bfd_vma
);
52 static void OP_E_register (int, int);
53 static void OP_E_memory (int, int);
54 static void print_displacement (char *, bfd_vma
);
55 static void OP_E (int, int);
56 static void OP_G (int, int);
57 static bfd_vma
get64 (void);
58 static bfd_signed_vma
get32 (void);
59 static bfd_signed_vma
get32s (void);
60 static int get16 (void);
61 static void set_op (bfd_vma
, int);
62 static void OP_Skip_MODRM (int, int);
63 static void OP_REG (int, int);
64 static void OP_IMREG (int, int);
65 static void OP_I (int, int);
66 static void OP_I64 (int, int);
67 static void OP_sI (int, int);
68 static void OP_J (int, int);
69 static void OP_SEG (int, int);
70 static void OP_DIR (int, int);
71 static void OP_OFF (int, int);
72 static void OP_OFF64 (int, int);
73 static void ptr_reg (int, int);
74 static void OP_ESreg (int, int);
75 static void OP_DSreg (int, int);
76 static void OP_C (int, int);
77 static void OP_D (int, int);
78 static void OP_T (int, int);
79 static void OP_R (int, int);
80 static void OP_MMX (int, int);
81 static void OP_XMM (int, int);
82 static void OP_EM (int, int);
83 static void OP_EX (int, int);
84 static void OP_EMC (int,int);
85 static void OP_MXC (int,int);
86 static void OP_MS (int, int);
87 static void OP_XS (int, int);
88 static void OP_M (int, int);
89 static void OP_VEX (int, int);
90 static void OP_EX_Vex (int, int);
91 static void OP_EX_VexW (int, int);
92 static void OP_EX_VexImmW (int, int);
93 static void OP_XMM_Vex (int, int);
94 static void OP_XMM_VexW (int, int);
95 static void OP_Rounding (int, int);
96 static void OP_REG_VexI4 (int, int);
97 static void PCLMUL_Fixup (int, int);
98 static void VCMP_Fixup (int, int);
99 static void VPCMP_Fixup (int, int);
100 static void VPCOM_Fixup (int, int);
101 static void OP_0f07 (int, int);
102 static void OP_Monitor (int, int);
103 static void OP_Mwait (int, int);
104 static void NOP_Fixup1 (int, int);
105 static void NOP_Fixup2 (int, int);
106 static void OP_3DNowSuffix (int, int);
107 static void CMP_Fixup (int, int);
108 static void BadOp (void);
109 static void REP_Fixup (int, int);
110 static void SEP_Fixup (int, int);
111 static void BND_Fixup (int, int);
112 static void NOTRACK_Fixup (int, int);
113 static void HLE_Fixup1 (int, int);
114 static void HLE_Fixup2 (int, int);
115 static void HLE_Fixup3 (int, int);
116 static void CMPXCHG8B_Fixup (int, int);
117 static void XMM_Fixup (int, int);
118 static void CRC32_Fixup (int, int);
119 static void FXSAVE_Fixup (int, int);
120 static void PCMPESTR_Fixup (int, int);
121 static void OP_LWPCB_E (int, int);
122 static void OP_LWP_E (int, int);
123 static void OP_Vex_2src_1 (int, int);
124 static void OP_Vex_2src_2 (int, int);
126 static void MOVBE_Fixup (int, int);
127 static void MOVSXD_Fixup (int, int);
129 static void OP_Mask (int, int);
132 /* Points to first byte not fetched. */
133 bfd_byte
*max_fetched
;
134 bfd_byte the_buffer
[MAX_MNEM_SIZE
];
137 OPCODES_SIGJMP_BUF bailout
;
147 enum address_mode address_mode
;
149 /* Flags for the prefixes for the current instruction. See below. */
152 /* REX prefix the current instruction. See below. */
154 /* Bits of REX we've already used. */
156 /* REX bits in original REX prefix ignored. */
157 static int rex_ignored
;
158 /* Mark parts used in the REX prefix. When we are testing for
159 empty prefix (for 8bit register REX extension), just mask it
160 out. Otherwise test for REX bit is excuse for existence of REX
161 only in case value is nonzero. */
162 #define USED_REX(value) \
167 rex_used |= (value) | REX_OPCODE; \
170 rex_used |= REX_OPCODE; \
173 /* Flags for prefixes which we somehow handled when printing the
174 current instruction. */
175 static int used_prefixes
;
177 /* Flags stored in PREFIXES. */
178 #define PREFIX_REPZ 1
179 #define PREFIX_REPNZ 2
180 #define PREFIX_LOCK 4
182 #define PREFIX_SS 0x10
183 #define PREFIX_DS 0x20
184 #define PREFIX_ES 0x40
185 #define PREFIX_FS 0x80
186 #define PREFIX_GS 0x100
187 #define PREFIX_DATA 0x200
188 #define PREFIX_ADDR 0x400
189 #define PREFIX_FWAIT 0x800
191 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
192 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
194 #define FETCH_DATA(info, addr) \
195 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
196 ? 1 : fetch_data ((info), (addr)))
199 fetch_data (struct disassemble_info
*info
, bfd_byte
*addr
)
202 struct dis_private
*priv
= (struct dis_private
*) info
->private_data
;
203 bfd_vma start
= priv
->insn_start
+ (priv
->max_fetched
- priv
->the_buffer
);
205 if (addr
<= priv
->the_buffer
+ MAX_MNEM_SIZE
)
206 status
= (*info
->read_memory_func
) (start
,
208 addr
- priv
->max_fetched
,
214 /* If we did manage to read at least one byte, then
215 print_insn_i386 will do something sensible. Otherwise, print
216 an error. We do that here because this is where we know
218 if (priv
->max_fetched
== priv
->the_buffer
)
219 (*info
->memory_error_func
) (status
, start
, info
);
220 OPCODES_SIGLONGJMP (priv
->bailout
, 1);
223 priv
->max_fetched
= addr
;
227 /* Possible values for prefix requirement. */
228 #define PREFIX_IGNORED_SHIFT 16
229 #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
230 #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
231 #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
232 #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
233 #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
235 /* Opcode prefixes. */
236 #define PREFIX_OPCODE (PREFIX_REPZ \
240 /* Prefixes ignored. */
241 #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \
242 | PREFIX_IGNORED_REPNZ \
243 | PREFIX_IGNORED_DATA)
245 #define XX { NULL, 0 }
246 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
248 #define Eb { OP_E, b_mode }
249 #define Ebnd { OP_E, bnd_mode }
250 #define EbS { OP_E, b_swap_mode }
251 #define EbndS { OP_E, bnd_swap_mode }
252 #define Ev { OP_E, v_mode }
253 #define Eva { OP_E, va_mode }
254 #define Ev_bnd { OP_E, v_bnd_mode }
255 #define EvS { OP_E, v_swap_mode }
256 #define Ed { OP_E, d_mode }
257 #define Edq { OP_E, dq_mode }
258 #define Edqw { OP_E, dqw_mode }
259 #define Edqb { OP_E, dqb_mode }
260 #define Edb { OP_E, db_mode }
261 #define Edw { OP_E, dw_mode }
262 #define Edqd { OP_E, dqd_mode }
263 #define Eq { OP_E, q_mode }
264 #define indirEv { OP_indirE, indir_v_mode }
265 #define indirEp { OP_indirE, f_mode }
266 #define stackEv { OP_E, stack_v_mode }
267 #define Em { OP_E, m_mode }
268 #define Ew { OP_E, w_mode }
269 #define M { OP_M, 0 } /* lea, lgdt, etc. */
270 #define Ma { OP_M, a_mode }
271 #define Mb { OP_M, b_mode }
272 #define Md { OP_M, d_mode }
273 #define Mo { OP_M, o_mode }
274 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
275 #define Mq { OP_M, q_mode }
276 #define Mv_bnd { OP_M, v_bndmk_mode }
277 #define Mx { OP_M, x_mode }
278 #define Mxmm { OP_M, xmm_mode }
279 #define Gb { OP_G, b_mode }
280 #define Gbnd { OP_G, bnd_mode }
281 #define Gv { OP_G, v_mode }
282 #define Gd { OP_G, d_mode }
283 #define Gdq { OP_G, dq_mode }
284 #define Gm { OP_G, m_mode }
285 #define Gva { OP_G, va_mode }
286 #define Gw { OP_G, w_mode }
287 #define Rd { OP_R, d_mode }
288 #define Rdq { OP_R, dq_mode }
289 #define Rm { OP_R, m_mode }
290 #define Ib { OP_I, b_mode }
291 #define sIb { OP_sI, b_mode } /* sign extened byte */
292 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
293 #define Iv { OP_I, v_mode }
294 #define sIv { OP_sI, v_mode }
295 #define Iv64 { OP_I64, v_mode }
296 #define Id { OP_I, d_mode }
297 #define Iw { OP_I, w_mode }
298 #define I1 { OP_I, const_1_mode }
299 #define Jb { OP_J, b_mode }
300 #define Jv { OP_J, v_mode }
301 #define Jdqw { OP_J, dqw_mode }
302 #define Cm { OP_C, m_mode }
303 #define Dm { OP_D, m_mode }
304 #define Td { OP_T, d_mode }
305 #define Skip_MODRM { OP_Skip_MODRM, 0 }
307 #define RMeAX { OP_REG, eAX_reg }
308 #define RMeBX { OP_REG, eBX_reg }
309 #define RMeCX { OP_REG, eCX_reg }
310 #define RMeDX { OP_REG, eDX_reg }
311 #define RMeSP { OP_REG, eSP_reg }
312 #define RMeBP { OP_REG, eBP_reg }
313 #define RMeSI { OP_REG, eSI_reg }
314 #define RMeDI { OP_REG, eDI_reg }
315 #define RMrAX { OP_REG, rAX_reg }
316 #define RMrBX { OP_REG, rBX_reg }
317 #define RMrCX { OP_REG, rCX_reg }
318 #define RMrDX { OP_REG, rDX_reg }
319 #define RMrSP { OP_REG, rSP_reg }
320 #define RMrBP { OP_REG, rBP_reg }
321 #define RMrSI { OP_REG, rSI_reg }
322 #define RMrDI { OP_REG, rDI_reg }
323 #define RMAL { OP_REG, al_reg }
324 #define RMCL { OP_REG, cl_reg }
325 #define RMDL { OP_REG, dl_reg }
326 #define RMBL { OP_REG, bl_reg }
327 #define RMAH { OP_REG, ah_reg }
328 #define RMCH { OP_REG, ch_reg }
329 #define RMDH { OP_REG, dh_reg }
330 #define RMBH { OP_REG, bh_reg }
331 #define RMAX { OP_REG, ax_reg }
332 #define RMDX { OP_REG, dx_reg }
334 #define eAX { OP_IMREG, eAX_reg }
335 #define eBX { OP_IMREG, eBX_reg }
336 #define eCX { OP_IMREG, eCX_reg }
337 #define eDX { OP_IMREG, eDX_reg }
338 #define eSP { OP_IMREG, eSP_reg }
339 #define eBP { OP_IMREG, eBP_reg }
340 #define eSI { OP_IMREG, eSI_reg }
341 #define eDI { OP_IMREG, eDI_reg }
342 #define AL { OP_IMREG, al_reg }
343 #define CL { OP_IMREG, cl_reg }
344 #define DL { OP_IMREG, dl_reg }
345 #define BL { OP_IMREG, bl_reg }
346 #define AH { OP_IMREG, ah_reg }
347 #define CH { OP_IMREG, ch_reg }
348 #define DH { OP_IMREG, dh_reg }
349 #define BH { OP_IMREG, bh_reg }
350 #define AX { OP_IMREG, ax_reg }
351 #define DX { OP_IMREG, dx_reg }
352 #define zAX { OP_IMREG, z_mode_ax_reg }
353 #define indirDX { OP_IMREG, indir_dx_reg }
355 #define Sw { OP_SEG, w_mode }
356 #define Sv { OP_SEG, v_mode }
357 #define Ap { OP_DIR, 0 }
358 #define Ob { OP_OFF64, b_mode }
359 #define Ov { OP_OFF64, v_mode }
360 #define Xb { OP_DSreg, eSI_reg }
361 #define Xv { OP_DSreg, eSI_reg }
362 #define Xz { OP_DSreg, eSI_reg }
363 #define Yb { OP_ESreg, eDI_reg }
364 #define Yv { OP_ESreg, eDI_reg }
365 #define DSBX { OP_DSreg, eBX_reg }
367 #define es { OP_REG, es_reg }
368 #define ss { OP_REG, ss_reg }
369 #define cs { OP_REG, cs_reg }
370 #define ds { OP_REG, ds_reg }
371 #define fs { OP_REG, fs_reg }
372 #define gs { OP_REG, gs_reg }
374 #define MX { OP_MMX, 0 }
375 #define XM { OP_XMM, 0 }
376 #define XMScalar { OP_XMM, scalar_mode }
377 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
378 #define XMM { OP_XMM, xmm_mode }
379 #define XMxmmq { OP_XMM, xmmq_mode }
380 #define EM { OP_EM, v_mode }
381 #define EMS { OP_EM, v_swap_mode }
382 #define EMd { OP_EM, d_mode }
383 #define EMx { OP_EM, x_mode }
384 #define EXbScalar { OP_EX, b_scalar_mode }
385 #define EXw { OP_EX, w_mode }
386 #define EXwScalar { OP_EX, w_scalar_mode }
387 #define EXd { OP_EX, d_mode }
388 #define EXdScalar { OP_EX, d_scalar_mode }
389 #define EXdS { OP_EX, d_swap_mode }
390 #define EXq { OP_EX, q_mode }
391 #define EXqScalar { OP_EX, q_scalar_mode }
392 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
393 #define EXqS { OP_EX, q_swap_mode }
394 #define EXx { OP_EX, x_mode }
395 #define EXxS { OP_EX, x_swap_mode }
396 #define EXxmm { OP_EX, xmm_mode }
397 #define EXymm { OP_EX, ymm_mode }
398 #define EXxmmq { OP_EX, xmmq_mode }
399 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
400 #define EXxmm_mb { OP_EX, xmm_mb_mode }
401 #define EXxmm_mw { OP_EX, xmm_mw_mode }
402 #define EXxmm_md { OP_EX, xmm_md_mode }
403 #define EXxmm_mq { OP_EX, xmm_mq_mode }
404 #define EXxmmdw { OP_EX, xmmdw_mode }
405 #define EXxmmqd { OP_EX, xmmqd_mode }
406 #define EXymmq { OP_EX, ymmq_mode }
407 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
408 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
409 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
410 #define MS { OP_MS, v_mode }
411 #define XS { OP_XS, v_mode }
412 #define EMCq { OP_EMC, q_mode }
413 #define MXC { OP_MXC, 0 }
414 #define OPSUF { OP_3DNowSuffix, 0 }
415 #define SEP { SEP_Fixup, 0 }
416 #define CMP { CMP_Fixup, 0 }
417 #define XMM0 { XMM_Fixup, 0 }
418 #define FXSAVE { FXSAVE_Fixup, 0 }
419 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
420 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
422 #define Vex { OP_VEX, vex_mode }
423 #define VexScalar { OP_VEX, vex_scalar_mode }
424 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
425 #define Vex128 { OP_VEX, vex128_mode }
426 #define Vex256 { OP_VEX, vex256_mode }
427 #define VexGdq { OP_VEX, dq_mode }
428 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
429 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
430 #define EXVexW { OP_EX_VexW, x_mode }
431 #define EXdVexW { OP_EX_VexW, d_mode }
432 #define EXqVexW { OP_EX_VexW, q_mode }
433 #define EXVexImmW { OP_EX_VexImmW, x_mode }
434 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
435 #define XMVexW { OP_XMM_VexW, 0 }
436 #define XMVexI4 { OP_REG_VexI4, x_mode }
437 #define PCLMUL { PCLMUL_Fixup, 0 }
438 #define VCMP { VCMP_Fixup, 0 }
439 #define VPCMP { VPCMP_Fixup, 0 }
440 #define VPCOM { VPCOM_Fixup, 0 }
442 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
443 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
444 #define EXxEVexS { OP_Rounding, evex_sae_mode }
446 #define XMask { OP_Mask, mask_mode }
447 #define MaskG { OP_G, mask_mode }
448 #define MaskE { OP_E, mask_mode }
449 #define MaskBDE { OP_E, mask_bd_mode }
450 #define MaskR { OP_R, mask_mode }
451 #define MaskVex { OP_VEX, mask_mode }
453 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
454 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
455 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
456 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
458 /* Used handle "rep" prefix for string instructions. */
459 #define Xbr { REP_Fixup, eSI_reg }
460 #define Xvr { REP_Fixup, eSI_reg }
461 #define Ybr { REP_Fixup, eDI_reg }
462 #define Yvr { REP_Fixup, eDI_reg }
463 #define Yzr { REP_Fixup, eDI_reg }
464 #define indirDXr { REP_Fixup, indir_dx_reg }
465 #define ALr { REP_Fixup, al_reg }
466 #define eAXr { REP_Fixup, eAX_reg }
468 /* Used handle HLE prefix for lockable instructions. */
469 #define Ebh1 { HLE_Fixup1, b_mode }
470 #define Evh1 { HLE_Fixup1, v_mode }
471 #define Ebh2 { HLE_Fixup2, b_mode }
472 #define Evh2 { HLE_Fixup2, v_mode }
473 #define Ebh3 { HLE_Fixup3, b_mode }
474 #define Evh3 { HLE_Fixup3, v_mode }
476 #define BND { BND_Fixup, 0 }
477 #define NOTRACK { NOTRACK_Fixup, 0 }
479 #define cond_jump_flag { NULL, cond_jump_mode }
480 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
482 /* bits in sizeflag */
483 #define SUFFIX_ALWAYS 4
491 /* byte operand with operand swapped */
493 /* byte operand, sign extend like 'T' suffix */
495 /* operand size depends on prefixes */
497 /* operand size depends on prefixes with operand swapped */
499 /* operand size depends on address prefix */
503 /* double word operand */
505 /* double word operand with operand swapped */
507 /* quad word operand */
509 /* quad word operand with operand swapped */
511 /* ten-byte operand */
513 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
514 broadcast enabled. */
516 /* Similar to x_mode, but with different EVEX mem shifts. */
518 /* Similar to x_mode, but with disabled broadcast. */
520 /* Similar to x_mode, but with operands swapped and disabled broadcast
523 /* 16-byte XMM operand */
525 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
526 memory operand (depending on vector length). Broadcast isn't
529 /* Same as xmmq_mode, but broadcast is allowed. */
530 evex_half_bcst_xmmq_mode
,
531 /* XMM register or byte memory operand */
533 /* XMM register or word memory operand */
535 /* XMM register or double word memory operand */
537 /* XMM register or quad word memory operand */
539 /* 16-byte XMM, word, double word or quad word operand. */
541 /* 16-byte XMM, double word, quad word operand or xmm word operand. */
543 /* 32-byte YMM operand */
545 /* quad word, ymmword or zmmword memory operand. */
547 /* 32-byte YMM or 16-byte word operand */
549 /* d_mode in 32bit, q_mode in 64bit mode. */
551 /* pair of v_mode operands */
557 /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode. */
559 /* operand size depends on REX prefixes. */
561 /* registers like dq_mode, memory like w_mode, displacements like
562 v_mode without considering Intel64 ISA. */
566 /* bounds operand with operand swapped */
568 /* 4- or 6-byte pointer operand */
571 /* v_mode for indirect branch opcodes. */
573 /* v_mode for stack-related opcodes. */
575 /* non-quad operand size depends on prefixes */
577 /* 16-byte operand */
579 /* registers like dq_mode, memory like b_mode. */
581 /* registers like d_mode, memory like b_mode. */
583 /* registers like d_mode, memory like w_mode. */
585 /* registers like dq_mode, memory like d_mode. */
587 /* normal vex mode */
589 /* 128bit vex mode */
591 /* 256bit vex mode */
594 /* Operand size depends on the VEX.W bit, with VSIB dword indices. */
595 vex_vsib_d_w_dq_mode
,
596 /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */
598 /* Operand size depends on the VEX.W bit, with VSIB qword indices. */
599 vex_vsib_q_w_dq_mode
,
600 /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */
603 /* scalar, ignore vector length. */
605 /* like b_mode, ignore vector length. */
607 /* like w_mode, ignore vector length. */
609 /* like d_mode, ignore vector length. */
611 /* like d_swap_mode, ignore vector length. */
613 /* like q_mode, ignore vector length. */
615 /* like q_swap_mode, ignore vector length. */
617 /* like vex_mode, ignore vector length. */
619 /* Operand size depends on the VEX.W bit, ignore vector length. */
620 vex_scalar_w_dq_mode
,
622 /* Static rounding. */
624 /* Static rounding, 64-bit mode only. */
625 evex_rounding_64_mode
,
626 /* Supress all exceptions. */
629 /* Mask register operand. */
631 /* Mask register operand. */
699 #define FLOAT NULL, { { NULL, FLOATCODE } }, 0
701 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0
702 #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P
703 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
704 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
705 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
706 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
707 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
708 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
709 #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
710 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
711 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
712 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
713 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
714 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
715 #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I))
716 #define EVEX_LEN_TABLE(I) DIS386 (USE_EVEX_LEN_TABLE, (I))
844 MOD_VEX_0F12_PREFIX_0
,
846 MOD_VEX_0F16_PREFIX_0
,
849 MOD_VEX_W_0_0F41_P_0_LEN_1
,
850 MOD_VEX_W_1_0F41_P_0_LEN_1
,
851 MOD_VEX_W_0_0F41_P_2_LEN_1
,
852 MOD_VEX_W_1_0F41_P_2_LEN_1
,
853 MOD_VEX_W_0_0F42_P_0_LEN_1
,
854 MOD_VEX_W_1_0F42_P_0_LEN_1
,
855 MOD_VEX_W_0_0F42_P_2_LEN_1
,
856 MOD_VEX_W_1_0F42_P_2_LEN_1
,
857 MOD_VEX_W_0_0F44_P_0_LEN_1
,
858 MOD_VEX_W_1_0F44_P_0_LEN_1
,
859 MOD_VEX_W_0_0F44_P_2_LEN_1
,
860 MOD_VEX_W_1_0F44_P_2_LEN_1
,
861 MOD_VEX_W_0_0F45_P_0_LEN_1
,
862 MOD_VEX_W_1_0F45_P_0_LEN_1
,
863 MOD_VEX_W_0_0F45_P_2_LEN_1
,
864 MOD_VEX_W_1_0F45_P_2_LEN_1
,
865 MOD_VEX_W_0_0F46_P_0_LEN_1
,
866 MOD_VEX_W_1_0F46_P_0_LEN_1
,
867 MOD_VEX_W_0_0F46_P_2_LEN_1
,
868 MOD_VEX_W_1_0F46_P_2_LEN_1
,
869 MOD_VEX_W_0_0F47_P_0_LEN_1
,
870 MOD_VEX_W_1_0F47_P_0_LEN_1
,
871 MOD_VEX_W_0_0F47_P_2_LEN_1
,
872 MOD_VEX_W_1_0F47_P_2_LEN_1
,
873 MOD_VEX_W_0_0F4A_P_0_LEN_1
,
874 MOD_VEX_W_1_0F4A_P_0_LEN_1
,
875 MOD_VEX_W_0_0F4A_P_2_LEN_1
,
876 MOD_VEX_W_1_0F4A_P_2_LEN_1
,
877 MOD_VEX_W_0_0F4B_P_0_LEN_1
,
878 MOD_VEX_W_1_0F4B_P_0_LEN_1
,
879 MOD_VEX_W_0_0F4B_P_2_LEN_1
,
891 MOD_VEX_W_0_0F91_P_0_LEN_0
,
892 MOD_VEX_W_1_0F91_P_0_LEN_0
,
893 MOD_VEX_W_0_0F91_P_2_LEN_0
,
894 MOD_VEX_W_1_0F91_P_2_LEN_0
,
895 MOD_VEX_W_0_0F92_P_0_LEN_0
,
896 MOD_VEX_W_0_0F92_P_2_LEN_0
,
897 MOD_VEX_0F92_P_3_LEN_0
,
898 MOD_VEX_W_0_0F93_P_0_LEN_0
,
899 MOD_VEX_W_0_0F93_P_2_LEN_0
,
900 MOD_VEX_0F93_P_3_LEN_0
,
901 MOD_VEX_W_0_0F98_P_0_LEN_0
,
902 MOD_VEX_W_1_0F98_P_0_LEN_0
,
903 MOD_VEX_W_0_0F98_P_2_LEN_0
,
904 MOD_VEX_W_1_0F98_P_2_LEN_0
,
905 MOD_VEX_W_0_0F99_P_0_LEN_0
,
906 MOD_VEX_W_1_0F99_P_0_LEN_0
,
907 MOD_VEX_W_0_0F99_P_2_LEN_0
,
908 MOD_VEX_W_1_0F99_P_2_LEN_0
,
911 MOD_VEX_0FD7_PREFIX_2
,
912 MOD_VEX_0FE7_PREFIX_2
,
913 MOD_VEX_0FF0_PREFIX_3
,
914 MOD_VEX_0F381A_PREFIX_2
,
915 MOD_VEX_0F382A_PREFIX_2
,
916 MOD_VEX_0F382C_PREFIX_2
,
917 MOD_VEX_0F382D_PREFIX_2
,
918 MOD_VEX_0F382E_PREFIX_2
,
919 MOD_VEX_0F382F_PREFIX_2
,
920 MOD_VEX_0F385A_PREFIX_2
,
921 MOD_VEX_0F388C_PREFIX_2
,
922 MOD_VEX_0F388E_PREFIX_2
,
923 MOD_VEX_W_0_0F3A30_P_2_LEN_0
,
924 MOD_VEX_W_1_0F3A30_P_2_LEN_0
,
925 MOD_VEX_W_0_0F3A31_P_2_LEN_0
,
926 MOD_VEX_W_1_0F3A31_P_2_LEN_0
,
927 MOD_VEX_W_0_0F3A32_P_2_LEN_0
,
928 MOD_VEX_W_1_0F3A32_P_2_LEN_0
,
929 MOD_VEX_W_0_0F3A33_P_2_LEN_0
,
930 MOD_VEX_W_1_0F3A33_P_2_LEN_0
,
932 MOD_EVEX_0F12_PREFIX_0
,
933 MOD_EVEX_0F16_PREFIX_0
,
934 MOD_EVEX_0F38C6_REG_1
,
935 MOD_EVEX_0F38C6_REG_2
,
936 MOD_EVEX_0F38C6_REG_5
,
937 MOD_EVEX_0F38C6_REG_6
,
938 MOD_EVEX_0F38C7_REG_1
,
939 MOD_EVEX_0F38C7_REG_2
,
940 MOD_EVEX_0F38C7_REG_5
,
941 MOD_EVEX_0F38C7_REG_6
954 RM_0F1E_P_1_MOD_3_REG_7
,
955 RM_0FAE_REG_6_MOD_3_P_0
,
962 PREFIX_0F01_REG_5_MOD_0
,
963 PREFIX_0F01_REG_5_MOD_3_RM_0
,
964 PREFIX_0F01_REG_5_MOD_3_RM_2
,
965 PREFIX_0F01_REG_7_MOD_3_RM_2
,
966 PREFIX_0F01_REG_7_MOD_3_RM_3
,
1008 PREFIX_0FAE_REG_0_MOD_3
,
1009 PREFIX_0FAE_REG_1_MOD_3
,
1010 PREFIX_0FAE_REG_2_MOD_3
,
1011 PREFIX_0FAE_REG_3_MOD_3
,
1012 PREFIX_0FAE_REG_4_MOD_0
,
1013 PREFIX_0FAE_REG_4_MOD_3
,
1014 PREFIX_0FAE_REG_5_MOD_0
,
1015 PREFIX_0FAE_REG_5_MOD_3
,
1016 PREFIX_0FAE_REG_6_MOD_0
,
1017 PREFIX_0FAE_REG_6_MOD_3
,
1018 PREFIX_0FAE_REG_7_MOD_0
,
1024 PREFIX_0FC7_REG_6_MOD_0
,
1025 PREFIX_0FC7_REG_6_MOD_3
,
1026 PREFIX_0FC7_REG_7_MOD_3
,
1156 PREFIX_VEX_0F71_REG_2
,
1157 PREFIX_VEX_0F71_REG_4
,
1158 PREFIX_VEX_0F71_REG_6
,
1159 PREFIX_VEX_0F72_REG_2
,
1160 PREFIX_VEX_0F72_REG_4
,
1161 PREFIX_VEX_0F72_REG_6
,
1162 PREFIX_VEX_0F73_REG_2
,
1163 PREFIX_VEX_0F73_REG_3
,
1164 PREFIX_VEX_0F73_REG_6
,
1165 PREFIX_VEX_0F73_REG_7
,
1338 PREFIX_VEX_0F38F3_REG_1
,
1339 PREFIX_VEX_0F38F3_REG_2
,
1340 PREFIX_VEX_0F38F3_REG_3
,
1459 PREFIX_EVEX_0F71_REG_2
,
1460 PREFIX_EVEX_0F71_REG_4
,
1461 PREFIX_EVEX_0F71_REG_6
,
1462 PREFIX_EVEX_0F72_REG_0
,
1463 PREFIX_EVEX_0F72_REG_1
,
1464 PREFIX_EVEX_0F72_REG_2
,
1465 PREFIX_EVEX_0F72_REG_4
,
1466 PREFIX_EVEX_0F72_REG_6
,
1467 PREFIX_EVEX_0F73_REG_2
,
1468 PREFIX_EVEX_0F73_REG_3
,
1469 PREFIX_EVEX_0F73_REG_6
,
1470 PREFIX_EVEX_0F73_REG_7
,
1667 PREFIX_EVEX_0F38C6_REG_1
,
1668 PREFIX_EVEX_0F38C6_REG_2
,
1669 PREFIX_EVEX_0F38C6_REG_5
,
1670 PREFIX_EVEX_0F38C6_REG_6
,
1671 PREFIX_EVEX_0F38C7_REG_1
,
1672 PREFIX_EVEX_0F38C7_REG_2
,
1673 PREFIX_EVEX_0F38C7_REG_5
,
1674 PREFIX_EVEX_0F38C7_REG_6
,
1778 THREE_BYTE_0F38
= 0,
1805 VEX_LEN_0F12_P_0_M_0
= 0,
1806 VEX_LEN_0F12_P_0_M_1
,
1809 VEX_LEN_0F16_P_0_M_0
,
1810 VEX_LEN_0F16_P_0_M_1
,
1847 VEX_LEN_0FAE_R_2_M_0
,
1848 VEX_LEN_0FAE_R_3_M_0
,
1855 VEX_LEN_0F381A_P_2_M_0
,
1858 VEX_LEN_0F385A_P_2_M_0
,
1861 VEX_LEN_0F38F3_R_1_P_0
,
1862 VEX_LEN_0F38F3_R_2_P_0
,
1863 VEX_LEN_0F38F3_R_3_P_0
,
1906 VEX_LEN_0FXOP_08_CC
,
1907 VEX_LEN_0FXOP_08_CD
,
1908 VEX_LEN_0FXOP_08_CE
,
1909 VEX_LEN_0FXOP_08_CF
,
1910 VEX_LEN_0FXOP_08_EC
,
1911 VEX_LEN_0FXOP_08_ED
,
1912 VEX_LEN_0FXOP_08_EE
,
1913 VEX_LEN_0FXOP_08_EF
,
1914 VEX_LEN_0FXOP_09_80
,
1920 EVEX_LEN_0F6E_P_2
= 0,
1924 EVEX_LEN_0F3819_P_2_W_0
,
1925 EVEX_LEN_0F3819_P_2_W_1
,
1926 EVEX_LEN_0F381A_P_2_W_0
,
1927 EVEX_LEN_0F381A_P_2_W_1
,
1928 EVEX_LEN_0F381B_P_2_W_0
,
1929 EVEX_LEN_0F381B_P_2_W_1
,
1930 EVEX_LEN_0F385A_P_2_W_0
,
1931 EVEX_LEN_0F385A_P_2_W_1
,
1932 EVEX_LEN_0F385B_P_2_W_0
,
1933 EVEX_LEN_0F385B_P_2_W_1
,
1934 EVEX_LEN_0F38C6_REG_1_PREFIX_2
,
1935 EVEX_LEN_0F38C6_REG_2_PREFIX_2
,
1936 EVEX_LEN_0F38C6_REG_5_PREFIX_2
,
1937 EVEX_LEN_0F38C6_REG_6_PREFIX_2
,
1938 EVEX_LEN_0F38C7_R_1_P_2_W_0
,
1939 EVEX_LEN_0F38C7_R_1_P_2_W_1
,
1940 EVEX_LEN_0F38C7_R_2_P_2_W_0
,
1941 EVEX_LEN_0F38C7_R_2_P_2_W_1
,
1942 EVEX_LEN_0F38C7_R_5_P_2_W_0
,
1943 EVEX_LEN_0F38C7_R_5_P_2_W_1
,
1944 EVEX_LEN_0F38C7_R_6_P_2_W_0
,
1945 EVEX_LEN_0F38C7_R_6_P_2_W_1
,
1946 EVEX_LEN_0F3A18_P_2_W_0
,
1947 EVEX_LEN_0F3A18_P_2_W_1
,
1948 EVEX_LEN_0F3A19_P_2_W_0
,
1949 EVEX_LEN_0F3A19_P_2_W_1
,
1950 EVEX_LEN_0F3A1A_P_2_W_0
,
1951 EVEX_LEN_0F3A1A_P_2_W_1
,
1952 EVEX_LEN_0F3A1B_P_2_W_0
,
1953 EVEX_LEN_0F3A1B_P_2_W_1
,
1954 EVEX_LEN_0F3A23_P_2_W_0
,
1955 EVEX_LEN_0F3A23_P_2_W_1
,
1956 EVEX_LEN_0F3A38_P_2_W_0
,
1957 EVEX_LEN_0F3A38_P_2_W_1
,
1958 EVEX_LEN_0F3A39_P_2_W_0
,
1959 EVEX_LEN_0F3A39_P_2_W_1
,
1960 EVEX_LEN_0F3A3A_P_2_W_0
,
1961 EVEX_LEN_0F3A3A_P_2_W_1
,
1962 EVEX_LEN_0F3A3B_P_2_W_0
,
1963 EVEX_LEN_0F3A3B_P_2_W_1
,
1964 EVEX_LEN_0F3A43_P_2_W_0
,
1965 EVEX_LEN_0F3A43_P_2_W_1
1970 VEX_W_0F41_P_0_LEN_1
= 0,
1971 VEX_W_0F41_P_2_LEN_1
,
1972 VEX_W_0F42_P_0_LEN_1
,
1973 VEX_W_0F42_P_2_LEN_1
,
1974 VEX_W_0F44_P_0_LEN_0
,
1975 VEX_W_0F44_P_2_LEN_0
,
1976 VEX_W_0F45_P_0_LEN_1
,
1977 VEX_W_0F45_P_2_LEN_1
,
1978 VEX_W_0F46_P_0_LEN_1
,
1979 VEX_W_0F46_P_2_LEN_1
,
1980 VEX_W_0F47_P_0_LEN_1
,
1981 VEX_W_0F47_P_2_LEN_1
,
1982 VEX_W_0F4A_P_0_LEN_1
,
1983 VEX_W_0F4A_P_2_LEN_1
,
1984 VEX_W_0F4B_P_0_LEN_1
,
1985 VEX_W_0F4B_P_2_LEN_1
,
1986 VEX_W_0F90_P_0_LEN_0
,
1987 VEX_W_0F90_P_2_LEN_0
,
1988 VEX_W_0F91_P_0_LEN_0
,
1989 VEX_W_0F91_P_2_LEN_0
,
1990 VEX_W_0F92_P_0_LEN_0
,
1991 VEX_W_0F92_P_2_LEN_0
,
1992 VEX_W_0F93_P_0_LEN_0
,
1993 VEX_W_0F93_P_2_LEN_0
,
1994 VEX_W_0F98_P_0_LEN_0
,
1995 VEX_W_0F98_P_2_LEN_0
,
1996 VEX_W_0F99_P_0_LEN_0
,
1997 VEX_W_0F99_P_2_LEN_0
,
2005 VEX_W_0F381A_P_2_M_0
,
2006 VEX_W_0F382C_P_2_M_0
,
2007 VEX_W_0F382D_P_2_M_0
,
2008 VEX_W_0F382E_P_2_M_0
,
2009 VEX_W_0F382F_P_2_M_0
,
2014 VEX_W_0F385A_P_2_M_0
,
2026 VEX_W_0F3A30_P_2_LEN_0
,
2027 VEX_W_0F3A31_P_2_LEN_0
,
2028 VEX_W_0F3A32_P_2_LEN_0
,
2029 VEX_W_0F3A33_P_2_LEN_0
,
2049 EVEX_W_0F12_P_0_M_0
,
2050 EVEX_W_0F12_P_0_M_1
,
2060 EVEX_W_0F16_P_0_M_0
,
2061 EVEX_W_0F16_P_0_M_1
,
2130 EVEX_W_0F72_R_2_P_2
,
2131 EVEX_W_0F72_R_6_P_2
,
2132 EVEX_W_0F73_R_2_P_2
,
2133 EVEX_W_0F73_R_6_P_2
,
2243 EVEX_W_0F38C7_R_1_P_2
,
2244 EVEX_W_0F38C7_R_2_P_2
,
2245 EVEX_W_0F38C7_R_5_P_2
,
2246 EVEX_W_0F38C7_R_6_P_2
,
2285 typedef void (*op_rtn
) (int bytemode
, int sizeflag
);
2294 unsigned int prefix_requirement
;
2297 /* Upper case letters in the instruction names here are macros.
2298 'A' => print 'b' if no register operands or suffix_always is true
2299 'B' => print 'b' if suffix_always is true
2300 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2302 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2303 suffix_always is true
2304 'E' => print 'e' if 32-bit form of jcxz
2305 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2306 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2307 'H' => print ",pt" or ",pn" branch hint
2308 'I' => honor following macro letter even in Intel mode (implemented only
2309 for some of the macro letters)
2311 'K' => print 'd' or 'q' if rex prefix is present.
2312 'L' => print 'l' if suffix_always is true
2313 'M' => print 'r' if intel_mnemonic is false.
2314 'N' => print 'n' if instruction has no wait "prefix"
2315 'O' => print 'd' or 'o' (or 'q' in Intel mode)
2316 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2317 or suffix_always is true. print 'q' if rex prefix is present.
2318 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2320 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2321 'S' => print 'w', 'l' or 'q' if suffix_always is true
2322 'T' => print 'q' in 64bit mode if instruction has no operand size
2323 prefix and behave as 'P' otherwise
2324 'U' => print 'q' in 64bit mode if instruction has no operand size
2325 prefix and behave as 'Q' otherwise
2326 'V' => print 'q' in 64bit mode if instruction has no operand size
2327 prefix and behave as 'S' otherwise
2328 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2329 'X' => print 's', 'd' depending on data16 prefix (for XMM)
2331 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2332 '!' => change condition from true to false or from false to true.
2333 '%' => add 1 upper case letter to the macro.
2334 '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size
2335 prefix or suffix_always is true (lcall/ljmp).
2336 '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2337 on operand size prefix.
2338 '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2339 has no operand size prefix for AMD64 ISA, behave as 'P'
2342 2 upper case letter macros:
2343 "XY" => print 'x' or 'y' if suffix_always is true or no register
2344 operands and no broadcast.
2345 "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2346 register operands and no broadcast.
2347 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2348 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2349 or suffix_always is true
2350 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2351 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2352 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2353 "LW" => print 'd', 'q' depending on the VEX.W bit
2354 "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2355 an operand size prefix, or suffix_always is true. print
2356 'q' if rex prefix is present.
2358 Many of the above letters print nothing in Intel mode. See "putop"
2361 Braces '{' and '}', and vertical bars '|', indicate alternative
2362 mnemonic strings for AT&T and Intel. */
2364 static const struct dis386 dis386
[] = {
2366 { "addB", { Ebh1
, Gb
}, 0 },
2367 { "addS", { Evh1
, Gv
}, 0 },
2368 { "addB", { Gb
, EbS
}, 0 },
2369 { "addS", { Gv
, EvS
}, 0 },
2370 { "addB", { AL
, Ib
}, 0 },
2371 { "addS", { eAX
, Iv
}, 0 },
2372 { X86_64_TABLE (X86_64_06
) },
2373 { X86_64_TABLE (X86_64_07
) },
2375 { "orB", { Ebh1
, Gb
}, 0 },
2376 { "orS", { Evh1
, Gv
}, 0 },
2377 { "orB", { Gb
, EbS
}, 0 },
2378 { "orS", { Gv
, EvS
}, 0 },
2379 { "orB", { AL
, Ib
}, 0 },
2380 { "orS", { eAX
, Iv
}, 0 },
2381 { X86_64_TABLE (X86_64_0D
) },
2382 { Bad_Opcode
}, /* 0x0f extended opcode escape */
2384 { "adcB", { Ebh1
, Gb
}, 0 },
2385 { "adcS", { Evh1
, Gv
}, 0 },
2386 { "adcB", { Gb
, EbS
}, 0 },
2387 { "adcS", { Gv
, EvS
}, 0 },
2388 { "adcB", { AL
, Ib
}, 0 },
2389 { "adcS", { eAX
, Iv
}, 0 },
2390 { X86_64_TABLE (X86_64_16
) },
2391 { X86_64_TABLE (X86_64_17
) },
2393 { "sbbB", { Ebh1
, Gb
}, 0 },
2394 { "sbbS", { Evh1
, Gv
}, 0 },
2395 { "sbbB", { Gb
, EbS
}, 0 },
2396 { "sbbS", { Gv
, EvS
}, 0 },
2397 { "sbbB", { AL
, Ib
}, 0 },
2398 { "sbbS", { eAX
, Iv
}, 0 },
2399 { X86_64_TABLE (X86_64_1E
) },
2400 { X86_64_TABLE (X86_64_1F
) },
2402 { "andB", { Ebh1
, Gb
}, 0 },
2403 { "andS", { Evh1
, Gv
}, 0 },
2404 { "andB", { Gb
, EbS
}, 0 },
2405 { "andS", { Gv
, EvS
}, 0 },
2406 { "andB", { AL
, Ib
}, 0 },
2407 { "andS", { eAX
, Iv
}, 0 },
2408 { Bad_Opcode
}, /* SEG ES prefix */
2409 { X86_64_TABLE (X86_64_27
) },
2411 { "subB", { Ebh1
, Gb
}, 0 },
2412 { "subS", { Evh1
, Gv
}, 0 },
2413 { "subB", { Gb
, EbS
}, 0 },
2414 { "subS", { Gv
, EvS
}, 0 },
2415 { "subB", { AL
, Ib
}, 0 },
2416 { "subS", { eAX
, Iv
}, 0 },
2417 { Bad_Opcode
}, /* SEG CS prefix */
2418 { X86_64_TABLE (X86_64_2F
) },
2420 { "xorB", { Ebh1
, Gb
}, 0 },
2421 { "xorS", { Evh1
, Gv
}, 0 },
2422 { "xorB", { Gb
, EbS
}, 0 },
2423 { "xorS", { Gv
, EvS
}, 0 },
2424 { "xorB", { AL
, Ib
}, 0 },
2425 { "xorS", { eAX
, Iv
}, 0 },
2426 { Bad_Opcode
}, /* SEG SS prefix */
2427 { X86_64_TABLE (X86_64_37
) },
2429 { "cmpB", { Eb
, Gb
}, 0 },
2430 { "cmpS", { Ev
, Gv
}, 0 },
2431 { "cmpB", { Gb
, EbS
}, 0 },
2432 { "cmpS", { Gv
, EvS
}, 0 },
2433 { "cmpB", { AL
, Ib
}, 0 },
2434 { "cmpS", { eAX
, Iv
}, 0 },
2435 { Bad_Opcode
}, /* SEG DS prefix */
2436 { X86_64_TABLE (X86_64_3F
) },
2438 { "inc{S|}", { RMeAX
}, 0 },
2439 { "inc{S|}", { RMeCX
}, 0 },
2440 { "inc{S|}", { RMeDX
}, 0 },
2441 { "inc{S|}", { RMeBX
}, 0 },
2442 { "inc{S|}", { RMeSP
}, 0 },
2443 { "inc{S|}", { RMeBP
}, 0 },
2444 { "inc{S|}", { RMeSI
}, 0 },
2445 { "inc{S|}", { RMeDI
}, 0 },
2447 { "dec{S|}", { RMeAX
}, 0 },
2448 { "dec{S|}", { RMeCX
}, 0 },
2449 { "dec{S|}", { RMeDX
}, 0 },
2450 { "dec{S|}", { RMeBX
}, 0 },
2451 { "dec{S|}", { RMeSP
}, 0 },
2452 { "dec{S|}", { RMeBP
}, 0 },
2453 { "dec{S|}", { RMeSI
}, 0 },
2454 { "dec{S|}", { RMeDI
}, 0 },
2456 { "pushV", { RMrAX
}, 0 },
2457 { "pushV", { RMrCX
}, 0 },
2458 { "pushV", { RMrDX
}, 0 },
2459 { "pushV", { RMrBX
}, 0 },
2460 { "pushV", { RMrSP
}, 0 },
2461 { "pushV", { RMrBP
}, 0 },
2462 { "pushV", { RMrSI
}, 0 },
2463 { "pushV", { RMrDI
}, 0 },
2465 { "popV", { RMrAX
}, 0 },
2466 { "popV", { RMrCX
}, 0 },
2467 { "popV", { RMrDX
}, 0 },
2468 { "popV", { RMrBX
}, 0 },
2469 { "popV", { RMrSP
}, 0 },
2470 { "popV", { RMrBP
}, 0 },
2471 { "popV", { RMrSI
}, 0 },
2472 { "popV", { RMrDI
}, 0 },
2474 { X86_64_TABLE (X86_64_60
) },
2475 { X86_64_TABLE (X86_64_61
) },
2476 { X86_64_TABLE (X86_64_62
) },
2477 { X86_64_TABLE (X86_64_63
) },
2478 { Bad_Opcode
}, /* seg fs */
2479 { Bad_Opcode
}, /* seg gs */
2480 { Bad_Opcode
}, /* op size prefix */
2481 { Bad_Opcode
}, /* adr size prefix */
2483 { "pushT", { sIv
}, 0 },
2484 { "imulS", { Gv
, Ev
, Iv
}, 0 },
2485 { "pushT", { sIbT
}, 0 },
2486 { "imulS", { Gv
, Ev
, sIb
}, 0 },
2487 { "ins{b|}", { Ybr
, indirDX
}, 0 },
2488 { X86_64_TABLE (X86_64_6D
) },
2489 { "outs{b|}", { indirDXr
, Xb
}, 0 },
2490 { X86_64_TABLE (X86_64_6F
) },
2492 { "joH", { Jb
, BND
, cond_jump_flag
}, 0 },
2493 { "jnoH", { Jb
, BND
, cond_jump_flag
}, 0 },
2494 { "jbH", { Jb
, BND
, cond_jump_flag
}, 0 },
2495 { "jaeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2496 { "jeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2497 { "jneH", { Jb
, BND
, cond_jump_flag
}, 0 },
2498 { "jbeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2499 { "jaH", { Jb
, BND
, cond_jump_flag
}, 0 },
2501 { "jsH", { Jb
, BND
, cond_jump_flag
}, 0 },
2502 { "jnsH", { Jb
, BND
, cond_jump_flag
}, 0 },
2503 { "jpH", { Jb
, BND
, cond_jump_flag
}, 0 },
2504 { "jnpH", { Jb
, BND
, cond_jump_flag
}, 0 },
2505 { "jlH", { Jb
, BND
, cond_jump_flag
}, 0 },
2506 { "jgeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2507 { "jleH", { Jb
, BND
, cond_jump_flag
}, 0 },
2508 { "jgH", { Jb
, BND
, cond_jump_flag
}, 0 },
2510 { REG_TABLE (REG_80
) },
2511 { REG_TABLE (REG_81
) },
2512 { X86_64_TABLE (X86_64_82
) },
2513 { REG_TABLE (REG_83
) },
2514 { "testB", { Eb
, Gb
}, 0 },
2515 { "testS", { Ev
, Gv
}, 0 },
2516 { "xchgB", { Ebh2
, Gb
}, 0 },
2517 { "xchgS", { Evh2
, Gv
}, 0 },
2519 { "movB", { Ebh3
, Gb
}, 0 },
2520 { "movS", { Evh3
, Gv
}, 0 },
2521 { "movB", { Gb
, EbS
}, 0 },
2522 { "movS", { Gv
, EvS
}, 0 },
2523 { "movD", { Sv
, Sw
}, 0 },
2524 { MOD_TABLE (MOD_8D
) },
2525 { "movD", { Sw
, Sv
}, 0 },
2526 { REG_TABLE (REG_8F
) },
2528 { PREFIX_TABLE (PREFIX_90
) },
2529 { "xchgS", { RMeCX
, eAX
}, 0 },
2530 { "xchgS", { RMeDX
, eAX
}, 0 },
2531 { "xchgS", { RMeBX
, eAX
}, 0 },
2532 { "xchgS", { RMeSP
, eAX
}, 0 },
2533 { "xchgS", { RMeBP
, eAX
}, 0 },
2534 { "xchgS", { RMeSI
, eAX
}, 0 },
2535 { "xchgS", { RMeDI
, eAX
}, 0 },
2537 { "cW{t|}R", { XX
}, 0 },
2538 { "cR{t|}O", { XX
}, 0 },
2539 { X86_64_TABLE (X86_64_9A
) },
2540 { Bad_Opcode
}, /* fwait */
2541 { "pushfT", { XX
}, 0 },
2542 { "popfT", { XX
}, 0 },
2543 { "sahf", { XX
}, 0 },
2544 { "lahf", { XX
}, 0 },
2546 { "mov%LB", { AL
, Ob
}, 0 },
2547 { "mov%LS", { eAX
, Ov
}, 0 },
2548 { "mov%LB", { Ob
, AL
}, 0 },
2549 { "mov%LS", { Ov
, eAX
}, 0 },
2550 { "movs{b|}", { Ybr
, Xb
}, 0 },
2551 { "movs{R|}", { Yvr
, Xv
}, 0 },
2552 { "cmps{b|}", { Xb
, Yb
}, 0 },
2553 { "cmps{R|}", { Xv
, Yv
}, 0 },
2555 { "testB", { AL
, Ib
}, 0 },
2556 { "testS", { eAX
, Iv
}, 0 },
2557 { "stosB", { Ybr
, AL
}, 0 },
2558 { "stosS", { Yvr
, eAX
}, 0 },
2559 { "lodsB", { ALr
, Xb
}, 0 },
2560 { "lodsS", { eAXr
, Xv
}, 0 },
2561 { "scasB", { AL
, Yb
}, 0 },
2562 { "scasS", { eAX
, Yv
}, 0 },
2564 { "movB", { RMAL
, Ib
}, 0 },
2565 { "movB", { RMCL
, Ib
}, 0 },
2566 { "movB", { RMDL
, Ib
}, 0 },
2567 { "movB", { RMBL
, Ib
}, 0 },
2568 { "movB", { RMAH
, Ib
}, 0 },
2569 { "movB", { RMCH
, Ib
}, 0 },
2570 { "movB", { RMDH
, Ib
}, 0 },
2571 { "movB", { RMBH
, Ib
}, 0 },
2573 { "mov%LV", { RMeAX
, Iv64
}, 0 },
2574 { "mov%LV", { RMeCX
, Iv64
}, 0 },
2575 { "mov%LV", { RMeDX
, Iv64
}, 0 },
2576 { "mov%LV", { RMeBX
, Iv64
}, 0 },
2577 { "mov%LV", { RMeSP
, Iv64
}, 0 },
2578 { "mov%LV", { RMeBP
, Iv64
}, 0 },
2579 { "mov%LV", { RMeSI
, Iv64
}, 0 },
2580 { "mov%LV", { RMeDI
, Iv64
}, 0 },
2582 { REG_TABLE (REG_C0
) },
2583 { REG_TABLE (REG_C1
) },
2584 { X86_64_TABLE (X86_64_C2
) },
2585 { X86_64_TABLE (X86_64_C3
) },
2586 { X86_64_TABLE (X86_64_C4
) },
2587 { X86_64_TABLE (X86_64_C5
) },
2588 { REG_TABLE (REG_C6
) },
2589 { REG_TABLE (REG_C7
) },
2591 { "enterT", { Iw
, Ib
}, 0 },
2592 { "leaveT", { XX
}, 0 },
2593 { "Jret{|f}P", { Iw
}, 0 },
2594 { "Jret{|f}P", { XX
}, 0 },
2595 { "int3", { XX
}, 0 },
2596 { "int", { Ib
}, 0 },
2597 { X86_64_TABLE (X86_64_CE
) },
2598 { "iret%LP", { XX
}, 0 },
2600 { REG_TABLE (REG_D0
) },
2601 { REG_TABLE (REG_D1
) },
2602 { REG_TABLE (REG_D2
) },
2603 { REG_TABLE (REG_D3
) },
2604 { X86_64_TABLE (X86_64_D4
) },
2605 { X86_64_TABLE (X86_64_D5
) },
2607 { "xlat", { DSBX
}, 0 },
2618 { "loopneFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2619 { "loopeFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2620 { "loopFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2621 { "jEcxzH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2622 { "inB", { AL
, Ib
}, 0 },
2623 { "inG", { zAX
, Ib
}, 0 },
2624 { "outB", { Ib
, AL
}, 0 },
2625 { "outG", { Ib
, zAX
}, 0 },
2627 { X86_64_TABLE (X86_64_E8
) },
2628 { X86_64_TABLE (X86_64_E9
) },
2629 { X86_64_TABLE (X86_64_EA
) },
2630 { "jmp", { Jb
, BND
}, 0 },
2631 { "inB", { AL
, indirDX
}, 0 },
2632 { "inG", { zAX
, indirDX
}, 0 },
2633 { "outB", { indirDX
, AL
}, 0 },
2634 { "outG", { indirDX
, zAX
}, 0 },
2636 { Bad_Opcode
}, /* lock prefix */
2637 { "icebp", { XX
}, 0 },
2638 { Bad_Opcode
}, /* repne */
2639 { Bad_Opcode
}, /* repz */
2640 { "hlt", { XX
}, 0 },
2641 { "cmc", { XX
}, 0 },
2642 { REG_TABLE (REG_F6
) },
2643 { REG_TABLE (REG_F7
) },
2645 { "clc", { XX
}, 0 },
2646 { "stc", { XX
}, 0 },
2647 { "cli", { XX
}, 0 },
2648 { "sti", { XX
}, 0 },
2649 { "cld", { XX
}, 0 },
2650 { "std", { XX
}, 0 },
2651 { REG_TABLE (REG_FE
) },
2652 { REG_TABLE (REG_FF
) },
2655 static const struct dis386 dis386_twobyte
[] = {
2657 { REG_TABLE (REG_0F00
) },
2658 { REG_TABLE (REG_0F01
) },
2659 { "larS", { Gv
, Ew
}, 0 },
2660 { "lslS", { Gv
, Ew
}, 0 },
2662 { "syscall", { XX
}, 0 },
2663 { "clts", { XX
}, 0 },
2664 { "sysret%LP", { XX
}, 0 },
2666 { "invd", { XX
}, 0 },
2667 { PREFIX_TABLE (PREFIX_0F09
) },
2669 { "ud2", { XX
}, 0 },
2671 { REG_TABLE (REG_0F0D
) },
2672 { "femms", { XX
}, 0 },
2673 { "", { MX
, EM
, OPSUF
}, 0 }, /* See OP_3DNowSuffix. */
2675 { PREFIX_TABLE (PREFIX_0F10
) },
2676 { PREFIX_TABLE (PREFIX_0F11
) },
2677 { PREFIX_TABLE (PREFIX_0F12
) },
2678 { MOD_TABLE (MOD_0F13
) },
2679 { "unpcklpX", { XM
, EXx
}, PREFIX_OPCODE
},
2680 { "unpckhpX", { XM
, EXx
}, PREFIX_OPCODE
},
2681 { PREFIX_TABLE (PREFIX_0F16
) },
2682 { MOD_TABLE (MOD_0F17
) },
2684 { REG_TABLE (REG_0F18
) },
2685 { "nopQ", { Ev
}, 0 },
2686 { PREFIX_TABLE (PREFIX_0F1A
) },
2687 { PREFIX_TABLE (PREFIX_0F1B
) },
2688 { PREFIX_TABLE (PREFIX_0F1C
) },
2689 { "nopQ", { Ev
}, 0 },
2690 { PREFIX_TABLE (PREFIX_0F1E
) },
2691 { "nopQ", { Ev
}, 0 },
2693 { "movZ", { Rm
, Cm
}, 0 },
2694 { "movZ", { Rm
, Dm
}, 0 },
2695 { "movZ", { Cm
, Rm
}, 0 },
2696 { "movZ", { Dm
, Rm
}, 0 },
2697 { MOD_TABLE (MOD_0F24
) },
2699 { MOD_TABLE (MOD_0F26
) },
2702 { "movapX", { XM
, EXx
}, PREFIX_OPCODE
},
2703 { "movapX", { EXxS
, XM
}, PREFIX_OPCODE
},
2704 { PREFIX_TABLE (PREFIX_0F2A
) },
2705 { PREFIX_TABLE (PREFIX_0F2B
) },
2706 { PREFIX_TABLE (PREFIX_0F2C
) },
2707 { PREFIX_TABLE (PREFIX_0F2D
) },
2708 { PREFIX_TABLE (PREFIX_0F2E
) },
2709 { PREFIX_TABLE (PREFIX_0F2F
) },
2711 { "wrmsr", { XX
}, 0 },
2712 { "rdtsc", { XX
}, 0 },
2713 { "rdmsr", { XX
}, 0 },
2714 { "rdpmc", { XX
}, 0 },
2715 { "sysenter", { SEP
}, 0 },
2716 { "sysexit", { SEP
}, 0 },
2718 { "getsec", { XX
}, 0 },
2720 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38
, PREFIX_OPCODE
) },
2722 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A
, PREFIX_OPCODE
) },
2729 { "cmovoS", { Gv
, Ev
}, 0 },
2730 { "cmovnoS", { Gv
, Ev
}, 0 },
2731 { "cmovbS", { Gv
, Ev
}, 0 },
2732 { "cmovaeS", { Gv
, Ev
}, 0 },
2733 { "cmoveS", { Gv
, Ev
}, 0 },
2734 { "cmovneS", { Gv
, Ev
}, 0 },
2735 { "cmovbeS", { Gv
, Ev
}, 0 },
2736 { "cmovaS", { Gv
, Ev
}, 0 },
2738 { "cmovsS", { Gv
, Ev
}, 0 },
2739 { "cmovnsS", { Gv
, Ev
}, 0 },
2740 { "cmovpS", { Gv
, Ev
}, 0 },
2741 { "cmovnpS", { Gv
, Ev
}, 0 },
2742 { "cmovlS", { Gv
, Ev
}, 0 },
2743 { "cmovgeS", { Gv
, Ev
}, 0 },
2744 { "cmovleS", { Gv
, Ev
}, 0 },
2745 { "cmovgS", { Gv
, Ev
}, 0 },
2747 { MOD_TABLE (MOD_0F51
) },
2748 { PREFIX_TABLE (PREFIX_0F51
) },
2749 { PREFIX_TABLE (PREFIX_0F52
) },
2750 { PREFIX_TABLE (PREFIX_0F53
) },
2751 { "andpX", { XM
, EXx
}, PREFIX_OPCODE
},
2752 { "andnpX", { XM
, EXx
}, PREFIX_OPCODE
},
2753 { "orpX", { XM
, EXx
}, PREFIX_OPCODE
},
2754 { "xorpX", { XM
, EXx
}, PREFIX_OPCODE
},
2756 { PREFIX_TABLE (PREFIX_0F58
) },
2757 { PREFIX_TABLE (PREFIX_0F59
) },
2758 { PREFIX_TABLE (PREFIX_0F5A
) },
2759 { PREFIX_TABLE (PREFIX_0F5B
) },
2760 { PREFIX_TABLE (PREFIX_0F5C
) },
2761 { PREFIX_TABLE (PREFIX_0F5D
) },
2762 { PREFIX_TABLE (PREFIX_0F5E
) },
2763 { PREFIX_TABLE (PREFIX_0F5F
) },
2765 { PREFIX_TABLE (PREFIX_0F60
) },
2766 { PREFIX_TABLE (PREFIX_0F61
) },
2767 { PREFIX_TABLE (PREFIX_0F62
) },
2768 { "packsswb", { MX
, EM
}, PREFIX_OPCODE
},
2769 { "pcmpgtb", { MX
, EM
}, PREFIX_OPCODE
},
2770 { "pcmpgtw", { MX
, EM
}, PREFIX_OPCODE
},
2771 { "pcmpgtd", { MX
, EM
}, PREFIX_OPCODE
},
2772 { "packuswb", { MX
, EM
}, PREFIX_OPCODE
},
2774 { "punpckhbw", { MX
, EM
}, PREFIX_OPCODE
},
2775 { "punpckhwd", { MX
, EM
}, PREFIX_OPCODE
},
2776 { "punpckhdq", { MX
, EM
}, PREFIX_OPCODE
},
2777 { "packssdw", { MX
, EM
}, PREFIX_OPCODE
},
2778 { PREFIX_TABLE (PREFIX_0F6C
) },
2779 { PREFIX_TABLE (PREFIX_0F6D
) },
2780 { "movK", { MX
, Edq
}, PREFIX_OPCODE
},
2781 { PREFIX_TABLE (PREFIX_0F6F
) },
2783 { PREFIX_TABLE (PREFIX_0F70
) },
2784 { REG_TABLE (REG_0F71
) },
2785 { REG_TABLE (REG_0F72
) },
2786 { REG_TABLE (REG_0F73
) },
2787 { "pcmpeqb", { MX
, EM
}, PREFIX_OPCODE
},
2788 { "pcmpeqw", { MX
, EM
}, PREFIX_OPCODE
},
2789 { "pcmpeqd", { MX
, EM
}, PREFIX_OPCODE
},
2790 { "emms", { XX
}, PREFIX_OPCODE
},
2792 { PREFIX_TABLE (PREFIX_0F78
) },
2793 { PREFIX_TABLE (PREFIX_0F79
) },
2796 { PREFIX_TABLE (PREFIX_0F7C
) },
2797 { PREFIX_TABLE (PREFIX_0F7D
) },
2798 { PREFIX_TABLE (PREFIX_0F7E
) },
2799 { PREFIX_TABLE (PREFIX_0F7F
) },
2801 { "joH", { Jv
, BND
, cond_jump_flag
}, 0 },
2802 { "jnoH", { Jv
, BND
, cond_jump_flag
}, 0 },
2803 { "jbH", { Jv
, BND
, cond_jump_flag
}, 0 },
2804 { "jaeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2805 { "jeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2806 { "jneH", { Jv
, BND
, cond_jump_flag
}, 0 },
2807 { "jbeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2808 { "jaH", { Jv
, BND
, cond_jump_flag
}, 0 },
2810 { "jsH", { Jv
, BND
, cond_jump_flag
}, 0 },
2811 { "jnsH", { Jv
, BND
, cond_jump_flag
}, 0 },
2812 { "jpH", { Jv
, BND
, cond_jump_flag
}, 0 },
2813 { "jnpH", { Jv
, BND
, cond_jump_flag
}, 0 },
2814 { "jlH", { Jv
, BND
, cond_jump_flag
}, 0 },
2815 { "jgeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2816 { "jleH", { Jv
, BND
, cond_jump_flag
}, 0 },
2817 { "jgH", { Jv
, BND
, cond_jump_flag
}, 0 },
2819 { "seto", { Eb
}, 0 },
2820 { "setno", { Eb
}, 0 },
2821 { "setb", { Eb
}, 0 },
2822 { "setae", { Eb
}, 0 },
2823 { "sete", { Eb
}, 0 },
2824 { "setne", { Eb
}, 0 },
2825 { "setbe", { Eb
}, 0 },
2826 { "seta", { Eb
}, 0 },
2828 { "sets", { Eb
}, 0 },
2829 { "setns", { Eb
}, 0 },
2830 { "setp", { Eb
}, 0 },
2831 { "setnp", { Eb
}, 0 },
2832 { "setl", { Eb
}, 0 },
2833 { "setge", { Eb
}, 0 },
2834 { "setle", { Eb
}, 0 },
2835 { "setg", { Eb
}, 0 },
2837 { "pushT", { fs
}, 0 },
2838 { "popT", { fs
}, 0 },
2839 { "cpuid", { XX
}, 0 },
2840 { "btS", { Ev
, Gv
}, 0 },
2841 { "shldS", { Ev
, Gv
, Ib
}, 0 },
2842 { "shldS", { Ev
, Gv
, CL
}, 0 },
2843 { REG_TABLE (REG_0FA6
) },
2844 { REG_TABLE (REG_0FA7
) },
2846 { "pushT", { gs
}, 0 },
2847 { "popT", { gs
}, 0 },
2848 { "rsm", { XX
}, 0 },
2849 { "btsS", { Evh1
, Gv
}, 0 },
2850 { "shrdS", { Ev
, Gv
, Ib
}, 0 },
2851 { "shrdS", { Ev
, Gv
, CL
}, 0 },
2852 { REG_TABLE (REG_0FAE
) },
2853 { "imulS", { Gv
, Ev
}, 0 },
2855 { "cmpxchgB", { Ebh1
, Gb
}, 0 },
2856 { "cmpxchgS", { Evh1
, Gv
}, 0 },
2857 { MOD_TABLE (MOD_0FB2
) },
2858 { "btrS", { Evh1
, Gv
}, 0 },
2859 { MOD_TABLE (MOD_0FB4
) },
2860 { MOD_TABLE (MOD_0FB5
) },
2861 { "movz{bR|x}", { Gv
, Eb
}, 0 },
2862 { "movz{wR|x}", { Gv
, Ew
}, 0 }, /* yes, there really is movzww ! */
2864 { PREFIX_TABLE (PREFIX_0FB8
) },
2865 { "ud1S", { Gv
, Ev
}, 0 },
2866 { REG_TABLE (REG_0FBA
) },
2867 { "btcS", { Evh1
, Gv
}, 0 },
2868 { PREFIX_TABLE (PREFIX_0FBC
) },
2869 { PREFIX_TABLE (PREFIX_0FBD
) },
2870 { "movs{bR|x}", { Gv
, Eb
}, 0 },
2871 { "movs{wR|x}", { Gv
, Ew
}, 0 }, /* yes, there really is movsww ! */
2873 { "xaddB", { Ebh1
, Gb
}, 0 },
2874 { "xaddS", { Evh1
, Gv
}, 0 },
2875 { PREFIX_TABLE (PREFIX_0FC2
) },
2876 { MOD_TABLE (MOD_0FC3
) },
2877 { "pinsrw", { MX
, Edqw
, Ib
}, PREFIX_OPCODE
},
2878 { "pextrw", { Gdq
, MS
, Ib
}, PREFIX_OPCODE
},
2879 { "shufpX", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
2880 { REG_TABLE (REG_0FC7
) },
2882 { "bswap", { RMeAX
}, 0 },
2883 { "bswap", { RMeCX
}, 0 },
2884 { "bswap", { RMeDX
}, 0 },
2885 { "bswap", { RMeBX
}, 0 },
2886 { "bswap", { RMeSP
}, 0 },
2887 { "bswap", { RMeBP
}, 0 },
2888 { "bswap", { RMeSI
}, 0 },
2889 { "bswap", { RMeDI
}, 0 },
2891 { PREFIX_TABLE (PREFIX_0FD0
) },
2892 { "psrlw", { MX
, EM
}, PREFIX_OPCODE
},
2893 { "psrld", { MX
, EM
}, PREFIX_OPCODE
},
2894 { "psrlq", { MX
, EM
}, PREFIX_OPCODE
},
2895 { "paddq", { MX
, EM
}, PREFIX_OPCODE
},
2896 { "pmullw", { MX
, EM
}, PREFIX_OPCODE
},
2897 { PREFIX_TABLE (PREFIX_0FD6
) },
2898 { MOD_TABLE (MOD_0FD7
) },
2900 { "psubusb", { MX
, EM
}, PREFIX_OPCODE
},
2901 { "psubusw", { MX
, EM
}, PREFIX_OPCODE
},
2902 { "pminub", { MX
, EM
}, PREFIX_OPCODE
},
2903 { "pand", { MX
, EM
}, PREFIX_OPCODE
},
2904 { "paddusb", { MX
, EM
}, PREFIX_OPCODE
},
2905 { "paddusw", { MX
, EM
}, PREFIX_OPCODE
},
2906 { "pmaxub", { MX
, EM
}, PREFIX_OPCODE
},
2907 { "pandn", { MX
, EM
}, PREFIX_OPCODE
},
2909 { "pavgb", { MX
, EM
}, PREFIX_OPCODE
},
2910 { "psraw", { MX
, EM
}, PREFIX_OPCODE
},
2911 { "psrad", { MX
, EM
}, PREFIX_OPCODE
},
2912 { "pavgw", { MX
, EM
}, PREFIX_OPCODE
},
2913 { "pmulhuw", { MX
, EM
}, PREFIX_OPCODE
},
2914 { "pmulhw", { MX
, EM
}, PREFIX_OPCODE
},
2915 { PREFIX_TABLE (PREFIX_0FE6
) },
2916 { PREFIX_TABLE (PREFIX_0FE7
) },
2918 { "psubsb", { MX
, EM
}, PREFIX_OPCODE
},
2919 { "psubsw", { MX
, EM
}, PREFIX_OPCODE
},
2920 { "pminsw", { MX
, EM
}, PREFIX_OPCODE
},
2921 { "por", { MX
, EM
}, PREFIX_OPCODE
},
2922 { "paddsb", { MX
, EM
}, PREFIX_OPCODE
},
2923 { "paddsw", { MX
, EM
}, PREFIX_OPCODE
},
2924 { "pmaxsw", { MX
, EM
}, PREFIX_OPCODE
},
2925 { "pxor", { MX
, EM
}, PREFIX_OPCODE
},
2927 { PREFIX_TABLE (PREFIX_0FF0
) },
2928 { "psllw", { MX
, EM
}, PREFIX_OPCODE
},
2929 { "pslld", { MX
, EM
}, PREFIX_OPCODE
},
2930 { "psllq", { MX
, EM
}, PREFIX_OPCODE
},
2931 { "pmuludq", { MX
, EM
}, PREFIX_OPCODE
},
2932 { "pmaddwd", { MX
, EM
}, PREFIX_OPCODE
},
2933 { "psadbw", { MX
, EM
}, PREFIX_OPCODE
},
2934 { PREFIX_TABLE (PREFIX_0FF7
) },
2936 { "psubb", { MX
, EM
}, PREFIX_OPCODE
},
2937 { "psubw", { MX
, EM
}, PREFIX_OPCODE
},
2938 { "psubd", { MX
, EM
}, PREFIX_OPCODE
},
2939 { "psubq", { MX
, EM
}, PREFIX_OPCODE
},
2940 { "paddb", { MX
, EM
}, PREFIX_OPCODE
},
2941 { "paddw", { MX
, EM
}, PREFIX_OPCODE
},
2942 { "paddd", { MX
, EM
}, PREFIX_OPCODE
},
2943 { "ud0S", { Gv
, Ev
}, 0 },
2946 static const unsigned char onebyte_has_modrm
[256] = {
2947 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2948 /* ------------------------------- */
2949 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2950 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2951 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2952 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2953 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2954 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2955 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2956 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2957 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2958 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2959 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2960 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2961 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2962 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2963 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2964 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
2965 /* ------------------------------- */
2966 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2969 static const unsigned char twobyte_has_modrm
[256] = {
2970 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2971 /* ------------------------------- */
2972 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2973 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2974 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2975 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2976 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2977 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2978 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2979 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2980 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2981 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2982 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2983 /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2984 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2985 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2986 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2987 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 /* ff */
2988 /* ------------------------------- */
2989 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2992 static char obuf
[100];
2994 static char *mnemonicendp
;
2995 static char scratchbuf
[100];
2996 static unsigned char *start_codep
;
2997 static unsigned char *insn_codep
;
2998 static unsigned char *codep
;
2999 static unsigned char *end_codep
;
3000 static int last_lock_prefix
;
3001 static int last_repz_prefix
;
3002 static int last_repnz_prefix
;
3003 static int last_data_prefix
;
3004 static int last_addr_prefix
;
3005 static int last_rex_prefix
;
3006 static int last_seg_prefix
;
3007 static int fwait_prefix
;
3008 /* The active segment register prefix. */
3009 static int active_seg_prefix
;
3010 #define MAX_CODE_LENGTH 15
3011 /* We can up to 14 prefixes since the maximum instruction length is
3013 static int all_prefixes
[MAX_CODE_LENGTH
- 1];
3014 static disassemble_info
*the_info
;
3022 static unsigned char need_modrm
;
3032 int register_specifier
;
3039 int mask_register_specifier
;
3045 static unsigned char need_vex
;
3046 static unsigned char need_vex_reg
;
3047 static unsigned char vex_w_done
;
3055 /* If we are accessing mod/rm/reg without need_modrm set, then the
3056 values are stale. Hitting this abort likely indicates that you
3057 need to update onebyte_has_modrm or twobyte_has_modrm. */
3058 #define MODRM_CHECK if (!need_modrm) abort ()
3060 static const char **names64
;
3061 static const char **names32
;
3062 static const char **names16
;
3063 static const char **names8
;
3064 static const char **names8rex
;
3065 static const char **names_seg
;
3066 static const char *index64
;
3067 static const char *index32
;
3068 static const char **index16
;
3069 static const char **names_bnd
;
3071 static const char *intel_names64
[] = {
3072 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3073 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3075 static const char *intel_names32
[] = {
3076 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3077 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3079 static const char *intel_names16
[] = {
3080 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3081 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3083 static const char *intel_names8
[] = {
3084 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3086 static const char *intel_names8rex
[] = {
3087 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3088 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3090 static const char *intel_names_seg
[] = {
3091 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3093 static const char *intel_index64
= "riz";
3094 static const char *intel_index32
= "eiz";
3095 static const char *intel_index16
[] = {
3096 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3099 static const char *att_names64
[] = {
3100 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3101 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3103 static const char *att_names32
[] = {
3104 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3105 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3107 static const char *att_names16
[] = {
3108 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3109 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3111 static const char *att_names8
[] = {
3112 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3114 static const char *att_names8rex
[] = {
3115 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3116 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3118 static const char *att_names_seg
[] = {
3119 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3121 static const char *att_index64
= "%riz";
3122 static const char *att_index32
= "%eiz";
3123 static const char *att_index16
[] = {
3124 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3127 static const char **names_mm
;
3128 static const char *intel_names_mm
[] = {
3129 "mm0", "mm1", "mm2", "mm3",
3130 "mm4", "mm5", "mm6", "mm7"
3132 static const char *att_names_mm
[] = {
3133 "%mm0", "%mm1", "%mm2", "%mm3",
3134 "%mm4", "%mm5", "%mm6", "%mm7"
3137 static const char *intel_names_bnd
[] = {
3138 "bnd0", "bnd1", "bnd2", "bnd3"
3141 static const char *att_names_bnd
[] = {
3142 "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3145 static const char **names_xmm
;
3146 static const char *intel_names_xmm
[] = {
3147 "xmm0", "xmm1", "xmm2", "xmm3",
3148 "xmm4", "xmm5", "xmm6", "xmm7",
3149 "xmm8", "xmm9", "xmm10", "xmm11",
3150 "xmm12", "xmm13", "xmm14", "xmm15",
3151 "xmm16", "xmm17", "xmm18", "xmm19",
3152 "xmm20", "xmm21", "xmm22", "xmm23",
3153 "xmm24", "xmm25", "xmm26", "xmm27",
3154 "xmm28", "xmm29", "xmm30", "xmm31"
3156 static const char *att_names_xmm
[] = {
3157 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3158 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3159 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3160 "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3161 "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3162 "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3163 "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3164 "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3167 static const char **names_ymm
;
3168 static const char *intel_names_ymm
[] = {
3169 "ymm0", "ymm1", "ymm2", "ymm3",
3170 "ymm4", "ymm5", "ymm6", "ymm7",
3171 "ymm8", "ymm9", "ymm10", "ymm11",
3172 "ymm12", "ymm13", "ymm14", "ymm15",
3173 "ymm16", "ymm17", "ymm18", "ymm19",
3174 "ymm20", "ymm21", "ymm22", "ymm23",
3175 "ymm24", "ymm25", "ymm26", "ymm27",
3176 "ymm28", "ymm29", "ymm30", "ymm31"
3178 static const char *att_names_ymm
[] = {
3179 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3180 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3181 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3182 "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3183 "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3184 "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3185 "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3186 "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3189 static const char **names_zmm
;
3190 static const char *intel_names_zmm
[] = {
3191 "zmm0", "zmm1", "zmm2", "zmm3",
3192 "zmm4", "zmm5", "zmm6", "zmm7",
3193 "zmm8", "zmm9", "zmm10", "zmm11",
3194 "zmm12", "zmm13", "zmm14", "zmm15",
3195 "zmm16", "zmm17", "zmm18", "zmm19",
3196 "zmm20", "zmm21", "zmm22", "zmm23",
3197 "zmm24", "zmm25", "zmm26", "zmm27",
3198 "zmm28", "zmm29", "zmm30", "zmm31"
3200 static const char *att_names_zmm
[] = {
3201 "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3202 "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3203 "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3204 "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3205 "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3206 "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3207 "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3208 "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3211 static const char **names_mask
;
3212 static const char *intel_names_mask
[] = {
3213 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3215 static const char *att_names_mask
[] = {
3216 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3219 static const char *names_rounding
[] =
3227 static const struct dis386 reg_table
[][8] = {
3230 { "addA", { Ebh1
, Ib
}, 0 },
3231 { "orA", { Ebh1
, Ib
}, 0 },
3232 { "adcA", { Ebh1
, Ib
}, 0 },
3233 { "sbbA", { Ebh1
, Ib
}, 0 },
3234 { "andA", { Ebh1
, Ib
}, 0 },
3235 { "subA", { Ebh1
, Ib
}, 0 },
3236 { "xorA", { Ebh1
, Ib
}, 0 },
3237 { "cmpA", { Eb
, Ib
}, 0 },
3241 { "addQ", { Evh1
, Iv
}, 0 },
3242 { "orQ", { Evh1
, Iv
}, 0 },
3243 { "adcQ", { Evh1
, Iv
}, 0 },
3244 { "sbbQ", { Evh1
, Iv
}, 0 },
3245 { "andQ", { Evh1
, Iv
}, 0 },
3246 { "subQ", { Evh1
, Iv
}, 0 },
3247 { "xorQ", { Evh1
, Iv
}, 0 },
3248 { "cmpQ", { Ev
, Iv
}, 0 },
3252 { "addQ", { Evh1
, sIb
}, 0 },
3253 { "orQ", { Evh1
, sIb
}, 0 },
3254 { "adcQ", { Evh1
, sIb
}, 0 },
3255 { "sbbQ", { Evh1
, sIb
}, 0 },
3256 { "andQ", { Evh1
, sIb
}, 0 },
3257 { "subQ", { Evh1
, sIb
}, 0 },
3258 { "xorQ", { Evh1
, sIb
}, 0 },
3259 { "cmpQ", { Ev
, sIb
}, 0 },
3263 { "popU", { stackEv
}, 0 },
3264 { XOP_8F_TABLE (XOP_09
) },
3268 { XOP_8F_TABLE (XOP_09
) },
3272 { "rolA", { Eb
, Ib
}, 0 },
3273 { "rorA", { Eb
, Ib
}, 0 },
3274 { "rclA", { Eb
, Ib
}, 0 },
3275 { "rcrA", { Eb
, Ib
}, 0 },
3276 { "shlA", { Eb
, Ib
}, 0 },
3277 { "shrA", { Eb
, Ib
}, 0 },
3278 { "shlA", { Eb
, Ib
}, 0 },
3279 { "sarA", { Eb
, Ib
}, 0 },
3283 { "rolQ", { Ev
, Ib
}, 0 },
3284 { "rorQ", { Ev
, Ib
}, 0 },
3285 { "rclQ", { Ev
, Ib
}, 0 },
3286 { "rcrQ", { Ev
, Ib
}, 0 },
3287 { "shlQ", { Ev
, Ib
}, 0 },
3288 { "shrQ", { Ev
, Ib
}, 0 },
3289 { "shlQ", { Ev
, Ib
}, 0 },
3290 { "sarQ", { Ev
, Ib
}, 0 },
3294 { "movA", { Ebh3
, Ib
}, 0 },
3301 { MOD_TABLE (MOD_C6_REG_7
) },
3305 { "movQ", { Evh3
, Iv
}, 0 },
3312 { MOD_TABLE (MOD_C7_REG_7
) },
3316 { "rolA", { Eb
, I1
}, 0 },
3317 { "rorA", { Eb
, I1
}, 0 },
3318 { "rclA", { Eb
, I1
}, 0 },
3319 { "rcrA", { Eb
, I1
}, 0 },
3320 { "shlA", { Eb
, I1
}, 0 },
3321 { "shrA", { Eb
, I1
}, 0 },
3322 { "shlA", { Eb
, I1
}, 0 },
3323 { "sarA", { Eb
, I1
}, 0 },
3327 { "rolQ", { Ev
, I1
}, 0 },
3328 { "rorQ", { Ev
, I1
}, 0 },
3329 { "rclQ", { Ev
, I1
}, 0 },
3330 { "rcrQ", { Ev
, I1
}, 0 },
3331 { "shlQ", { Ev
, I1
}, 0 },
3332 { "shrQ", { Ev
, I1
}, 0 },
3333 { "shlQ", { Ev
, I1
}, 0 },
3334 { "sarQ", { Ev
, I1
}, 0 },
3338 { "rolA", { Eb
, CL
}, 0 },
3339 { "rorA", { Eb
, CL
}, 0 },
3340 { "rclA", { Eb
, CL
}, 0 },
3341 { "rcrA", { Eb
, CL
}, 0 },
3342 { "shlA", { Eb
, CL
}, 0 },
3343 { "shrA", { Eb
, CL
}, 0 },
3344 { "shlA", { Eb
, CL
}, 0 },
3345 { "sarA", { Eb
, CL
}, 0 },
3349 { "rolQ", { Ev
, CL
}, 0 },
3350 { "rorQ", { Ev
, CL
}, 0 },
3351 { "rclQ", { Ev
, CL
}, 0 },
3352 { "rcrQ", { Ev
, CL
}, 0 },
3353 { "shlQ", { Ev
, CL
}, 0 },
3354 { "shrQ", { Ev
, CL
}, 0 },
3355 { "shlQ", { Ev
, CL
}, 0 },
3356 { "sarQ", { Ev
, CL
}, 0 },
3360 { "testA", { Eb
, Ib
}, 0 },
3361 { "testA", { Eb
, Ib
}, 0 },
3362 { "notA", { Ebh1
}, 0 },
3363 { "negA", { Ebh1
}, 0 },
3364 { "mulA", { Eb
}, 0 }, /* Don't print the implicit %al register, */
3365 { "imulA", { Eb
}, 0 }, /* to distinguish these opcodes from other */
3366 { "divA", { Eb
}, 0 }, /* mul/imul opcodes. Do the same for div */
3367 { "idivA", { Eb
}, 0 }, /* and idiv for consistency. */
3371 { "testQ", { Ev
, Iv
}, 0 },
3372 { "testQ", { Ev
, Iv
}, 0 },
3373 { "notQ", { Evh1
}, 0 },
3374 { "negQ", { Evh1
}, 0 },
3375 { "mulQ", { Ev
}, 0 }, /* Don't print the implicit register. */
3376 { "imulQ", { Ev
}, 0 },
3377 { "divQ", { Ev
}, 0 },
3378 { "idivQ", { Ev
}, 0 },
3382 { "incA", { Ebh1
}, 0 },
3383 { "decA", { Ebh1
}, 0 },
3387 { "incQ", { Evh1
}, 0 },
3388 { "decQ", { Evh1
}, 0 },
3389 { "call{&|}", { NOTRACK
, indirEv
, BND
}, 0 },
3390 { MOD_TABLE (MOD_FF_REG_3
) },
3391 { "jmp{&|}", { NOTRACK
, indirEv
, BND
}, 0 },
3392 { MOD_TABLE (MOD_FF_REG_5
) },
3393 { "pushU", { stackEv
}, 0 },
3398 { "sldtD", { Sv
}, 0 },
3399 { "strD", { Sv
}, 0 },
3400 { "lldt", { Ew
}, 0 },
3401 { "ltr", { Ew
}, 0 },
3402 { "verr", { Ew
}, 0 },
3403 { "verw", { Ew
}, 0 },
3409 { MOD_TABLE (MOD_0F01_REG_0
) },
3410 { MOD_TABLE (MOD_0F01_REG_1
) },
3411 { MOD_TABLE (MOD_0F01_REG_2
) },
3412 { MOD_TABLE (MOD_0F01_REG_3
) },
3413 { "smswD", { Sv
}, 0 },
3414 { MOD_TABLE (MOD_0F01_REG_5
) },
3415 { "lmsw", { Ew
}, 0 },
3416 { MOD_TABLE (MOD_0F01_REG_7
) },
3420 { "prefetch", { Mb
}, 0 },
3421 { "prefetchw", { Mb
}, 0 },
3422 { "prefetchwt1", { Mb
}, 0 },
3423 { "prefetch", { Mb
}, 0 },
3424 { "prefetch", { Mb
}, 0 },
3425 { "prefetch", { Mb
}, 0 },
3426 { "prefetch", { Mb
}, 0 },
3427 { "prefetch", { Mb
}, 0 },
3431 { MOD_TABLE (MOD_0F18_REG_0
) },
3432 { MOD_TABLE (MOD_0F18_REG_1
) },
3433 { MOD_TABLE (MOD_0F18_REG_2
) },
3434 { MOD_TABLE (MOD_0F18_REG_3
) },
3435 { MOD_TABLE (MOD_0F18_REG_4
) },
3436 { MOD_TABLE (MOD_0F18_REG_5
) },
3437 { MOD_TABLE (MOD_0F18_REG_6
) },
3438 { MOD_TABLE (MOD_0F18_REG_7
) },
3440 /* REG_0F1C_P_0_MOD_0 */
3442 { "cldemote", { Mb
}, 0 },
3443 { "nopQ", { Ev
}, 0 },
3444 { "nopQ", { Ev
}, 0 },
3445 { "nopQ", { Ev
}, 0 },
3446 { "nopQ", { Ev
}, 0 },
3447 { "nopQ", { Ev
}, 0 },
3448 { "nopQ", { Ev
}, 0 },
3449 { "nopQ", { Ev
}, 0 },
3451 /* REG_0F1E_P_1_MOD_3 */
3453 { "nopQ", { Ev
}, 0 },
3454 { "rdsspK", { Rdq
}, PREFIX_OPCODE
},
3455 { "nopQ", { Ev
}, 0 },
3456 { "nopQ", { Ev
}, 0 },
3457 { "nopQ", { Ev
}, 0 },
3458 { "nopQ", { Ev
}, 0 },
3459 { "nopQ", { Ev
}, 0 },
3460 { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7
) },
3466 { MOD_TABLE (MOD_0F71_REG_2
) },
3468 { MOD_TABLE (MOD_0F71_REG_4
) },
3470 { MOD_TABLE (MOD_0F71_REG_6
) },
3476 { MOD_TABLE (MOD_0F72_REG_2
) },
3478 { MOD_TABLE (MOD_0F72_REG_4
) },
3480 { MOD_TABLE (MOD_0F72_REG_6
) },
3486 { MOD_TABLE (MOD_0F73_REG_2
) },
3487 { MOD_TABLE (MOD_0F73_REG_3
) },
3490 { MOD_TABLE (MOD_0F73_REG_6
) },
3491 { MOD_TABLE (MOD_0F73_REG_7
) },
3495 { "montmul", { { OP_0f07
, 0 } }, 0 },
3496 { "xsha1", { { OP_0f07
, 0 } }, 0 },
3497 { "xsha256", { { OP_0f07
, 0 } }, 0 },
3501 { "xstore-rng", { { OP_0f07
, 0 } }, 0 },
3502 { "xcrypt-ecb", { { OP_0f07
, 0 } }, 0 },
3503 { "xcrypt-cbc", { { OP_0f07
, 0 } }, 0 },
3504 { "xcrypt-ctr", { { OP_0f07
, 0 } }, 0 },
3505 { "xcrypt-cfb", { { OP_0f07
, 0 } }, 0 },
3506 { "xcrypt-ofb", { { OP_0f07
, 0 } }, 0 },
3510 { MOD_TABLE (MOD_0FAE_REG_0
) },
3511 { MOD_TABLE (MOD_0FAE_REG_1
) },
3512 { MOD_TABLE (MOD_0FAE_REG_2
) },
3513 { MOD_TABLE (MOD_0FAE_REG_3
) },
3514 { MOD_TABLE (MOD_0FAE_REG_4
) },
3515 { MOD_TABLE (MOD_0FAE_REG_5
) },
3516 { MOD_TABLE (MOD_0FAE_REG_6
) },
3517 { MOD_TABLE (MOD_0FAE_REG_7
) },
3525 { "btQ", { Ev
, Ib
}, 0 },
3526 { "btsQ", { Evh1
, Ib
}, 0 },
3527 { "btrQ", { Evh1
, Ib
}, 0 },
3528 { "btcQ", { Evh1
, Ib
}, 0 },
3533 { "cmpxchg8b", { { CMPXCHG8B_Fixup
, q_mode
} }, 0 },
3535 { MOD_TABLE (MOD_0FC7_REG_3
) },
3536 { MOD_TABLE (MOD_0FC7_REG_4
) },
3537 { MOD_TABLE (MOD_0FC7_REG_5
) },
3538 { MOD_TABLE (MOD_0FC7_REG_6
) },
3539 { MOD_TABLE (MOD_0FC7_REG_7
) },
3545 { MOD_TABLE (MOD_VEX_0F71_REG_2
) },
3547 { MOD_TABLE (MOD_VEX_0F71_REG_4
) },
3549 { MOD_TABLE (MOD_VEX_0F71_REG_6
) },
3555 { MOD_TABLE (MOD_VEX_0F72_REG_2
) },
3557 { MOD_TABLE (MOD_VEX_0F72_REG_4
) },
3559 { MOD_TABLE (MOD_VEX_0F72_REG_6
) },
3565 { MOD_TABLE (MOD_VEX_0F73_REG_2
) },
3566 { MOD_TABLE (MOD_VEX_0F73_REG_3
) },
3569 { MOD_TABLE (MOD_VEX_0F73_REG_6
) },
3570 { MOD_TABLE (MOD_VEX_0F73_REG_7
) },
3576 { MOD_TABLE (MOD_VEX_0FAE_REG_2
) },
3577 { MOD_TABLE (MOD_VEX_0FAE_REG_3
) },
3579 /* REG_VEX_0F38F3 */
3582 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1
) },
3583 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2
) },
3584 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3
) },
3588 { "llwpcb", { { OP_LWPCB_E
, 0 } }, 0 },
3589 { "slwpcb", { { OP_LWPCB_E
, 0 } }, 0 },
3593 { "lwpins", { { OP_LWP_E
, 0 }, Ed
, Id
}, 0 },
3594 { "lwpval", { { OP_LWP_E
, 0 }, Ed
, Id
}, 0 },
3596 /* REG_XOP_TBM_01 */
3599 { "blcfill", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3600 { "blsfill", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3601 { "blcs", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3602 { "tzmsk", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3603 { "blcic", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3604 { "blsic", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3605 { "t1mskc", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3607 /* REG_XOP_TBM_02 */
3610 { "blcmsk", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3615 { "blci", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3618 #include "i386-dis-evex-reg.h"
3621 static const struct dis386 prefix_table
[][4] = {
3624 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} }, 0 },
3625 { "pause", { XX
}, 0 },
3626 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} }, 0 },
3627 { NULL
, { { NULL
, 0 } }, PREFIX_IGNORED
}
3630 /* PREFIX_0F01_REG_5_MOD_0 */
3633 { "rstorssp", { Mq
}, PREFIX_OPCODE
},
3636 /* PREFIX_0F01_REG_5_MOD_3_RM_0 */
3639 { "setssbsy", { Skip_MODRM
}, PREFIX_OPCODE
},
3642 /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
3645 { "saveprevssp", { Skip_MODRM
}, PREFIX_OPCODE
},
3648 /* PREFIX_0F01_REG_7_MOD_3_RM_2 */
3650 { "monitorx", { { OP_Monitor
, 0 } }, 0 },
3651 { "mcommit", { Skip_MODRM
}, 0 },
3654 /* PREFIX_0F01_REG_7_MOD_3_RM_3 */
3656 { "mwaitx", { { OP_Mwait
, eBX_reg
} }, 0 },
3661 { "wbinvd", { XX
}, 0 },
3662 { "wbnoinvd", { XX
}, 0 },
3667 { "movups", { XM
, EXx
}, PREFIX_OPCODE
},
3668 { "movss", { XM
, EXd
}, PREFIX_OPCODE
},
3669 { "movupd", { XM
, EXx
}, PREFIX_OPCODE
},
3670 { "movsd", { XM
, EXq
}, PREFIX_OPCODE
},
3675 { "movups", { EXxS
, XM
}, PREFIX_OPCODE
},
3676 { "movss", { EXdS
, XM
}, PREFIX_OPCODE
},
3677 { "movupd", { EXxS
, XM
}, PREFIX_OPCODE
},
3678 { "movsd", { EXqS
, XM
}, PREFIX_OPCODE
},
3683 { MOD_TABLE (MOD_0F12_PREFIX_0
) },
3684 { "movsldup", { XM
, EXx
}, PREFIX_OPCODE
},
3685 { "movlpd", { XM
, EXq
}, PREFIX_OPCODE
},
3686 { "movddup", { XM
, EXq
}, PREFIX_OPCODE
},
3691 { MOD_TABLE (MOD_0F16_PREFIX_0
) },
3692 { "movshdup", { XM
, EXx
}, PREFIX_OPCODE
},
3693 { "movhpd", { XM
, EXq
}, PREFIX_OPCODE
},
3698 { MOD_TABLE (MOD_0F1A_PREFIX_0
) },
3699 { "bndcl", { Gbnd
, Ev_bnd
}, 0 },
3700 { "bndmov", { Gbnd
, Ebnd
}, 0 },
3701 { "bndcu", { Gbnd
, Ev_bnd
}, 0 },
3706 { MOD_TABLE (MOD_0F1B_PREFIX_0
) },
3707 { MOD_TABLE (MOD_0F1B_PREFIX_1
) },
3708 { "bndmov", { EbndS
, Gbnd
}, 0 },
3709 { "bndcn", { Gbnd
, Ev_bnd
}, 0 },
3714 { MOD_TABLE (MOD_0F1C_PREFIX_0
) },
3715 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3716 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3717 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3722 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3723 { MOD_TABLE (MOD_0F1E_PREFIX_1
) },
3724 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3725 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3730 { "cvtpi2ps", { XM
, EMCq
}, PREFIX_OPCODE
},
3731 { "cvtsi2ss%LQ", { XM
, Edq
}, PREFIX_OPCODE
},
3732 { "cvtpi2pd", { XM
, EMCq
}, PREFIX_OPCODE
},
3733 { "cvtsi2sd%LQ", { XM
, Edq
}, 0 },
3738 { MOD_TABLE (MOD_0F2B_PREFIX_0
) },
3739 { MOD_TABLE (MOD_0F2B_PREFIX_1
) },
3740 { MOD_TABLE (MOD_0F2B_PREFIX_2
) },
3741 { MOD_TABLE (MOD_0F2B_PREFIX_3
) },
3746 { "cvttps2pi", { MXC
, EXq
}, PREFIX_OPCODE
},
3747 { "cvttss2si", { Gdq
, EXd
}, PREFIX_OPCODE
},
3748 { "cvttpd2pi", { MXC
, EXx
}, PREFIX_OPCODE
},
3749 { "cvttsd2si", { Gdq
, EXq
}, PREFIX_OPCODE
},
3754 { "cvtps2pi", { MXC
, EXq
}, PREFIX_OPCODE
},
3755 { "cvtss2si", { Gdq
, EXd
}, PREFIX_OPCODE
},
3756 { "cvtpd2pi", { MXC
, EXx
}, PREFIX_OPCODE
},
3757 { "cvtsd2si", { Gdq
, EXq
}, PREFIX_OPCODE
},
3762 { "ucomiss",{ XM
, EXd
}, 0 },
3764 { "ucomisd",{ XM
, EXq
}, 0 },
3769 { "comiss", { XM
, EXd
}, 0 },
3771 { "comisd", { XM
, EXq
}, 0 },
3776 { "sqrtps", { XM
, EXx
}, PREFIX_OPCODE
},
3777 { "sqrtss", { XM
, EXd
}, PREFIX_OPCODE
},
3778 { "sqrtpd", { XM
, EXx
}, PREFIX_OPCODE
},
3779 { "sqrtsd", { XM
, EXq
}, PREFIX_OPCODE
},
3784 { "rsqrtps",{ XM
, EXx
}, PREFIX_OPCODE
},
3785 { "rsqrtss",{ XM
, EXd
}, PREFIX_OPCODE
},
3790 { "rcpps", { XM
, EXx
}, PREFIX_OPCODE
},
3791 { "rcpss", { XM
, EXd
}, PREFIX_OPCODE
},
3796 { "addps", { XM
, EXx
}, PREFIX_OPCODE
},
3797 { "addss", { XM
, EXd
}, PREFIX_OPCODE
},
3798 { "addpd", { XM
, EXx
}, PREFIX_OPCODE
},
3799 { "addsd", { XM
, EXq
}, PREFIX_OPCODE
},
3804 { "mulps", { XM
, EXx
}, PREFIX_OPCODE
},
3805 { "mulss", { XM
, EXd
}, PREFIX_OPCODE
},
3806 { "mulpd", { XM
, EXx
}, PREFIX_OPCODE
},
3807 { "mulsd", { XM
, EXq
}, PREFIX_OPCODE
},
3812 { "cvtps2pd", { XM
, EXq
}, PREFIX_OPCODE
},
3813 { "cvtss2sd", { XM
, EXd
}, PREFIX_OPCODE
},
3814 { "cvtpd2ps", { XM
, EXx
}, PREFIX_OPCODE
},
3815 { "cvtsd2ss", { XM
, EXq
}, PREFIX_OPCODE
},
3820 { "cvtdq2ps", { XM
, EXx
}, PREFIX_OPCODE
},
3821 { "cvttps2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3822 { "cvtps2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3827 { "subps", { XM
, EXx
}, PREFIX_OPCODE
},
3828 { "subss", { XM
, EXd
}, PREFIX_OPCODE
},
3829 { "subpd", { XM
, EXx
}, PREFIX_OPCODE
},
3830 { "subsd", { XM
, EXq
}, PREFIX_OPCODE
},
3835 { "minps", { XM
, EXx
}, PREFIX_OPCODE
},
3836 { "minss", { XM
, EXd
}, PREFIX_OPCODE
},
3837 { "minpd", { XM
, EXx
}, PREFIX_OPCODE
},
3838 { "minsd", { XM
, EXq
}, PREFIX_OPCODE
},
3843 { "divps", { XM
, EXx
}, PREFIX_OPCODE
},
3844 { "divss", { XM
, EXd
}, PREFIX_OPCODE
},
3845 { "divpd", { XM
, EXx
}, PREFIX_OPCODE
},
3846 { "divsd", { XM
, EXq
}, PREFIX_OPCODE
},
3851 { "maxps", { XM
, EXx
}, PREFIX_OPCODE
},
3852 { "maxss", { XM
, EXd
}, PREFIX_OPCODE
},
3853 { "maxpd", { XM
, EXx
}, PREFIX_OPCODE
},
3854 { "maxsd", { XM
, EXq
}, PREFIX_OPCODE
},
3859 { "punpcklbw",{ MX
, EMd
}, PREFIX_OPCODE
},
3861 { "punpcklbw",{ MX
, EMx
}, PREFIX_OPCODE
},
3866 { "punpcklwd",{ MX
, EMd
}, PREFIX_OPCODE
},
3868 { "punpcklwd",{ MX
, EMx
}, PREFIX_OPCODE
},
3873 { "punpckldq",{ MX
, EMd
}, PREFIX_OPCODE
},
3875 { "punpckldq",{ MX
, EMx
}, PREFIX_OPCODE
},
3882 { "punpcklqdq", { XM
, EXx
}, PREFIX_OPCODE
},
3889 { "punpckhqdq", { XM
, EXx
}, PREFIX_OPCODE
},
3894 { "movq", { MX
, EM
}, PREFIX_OPCODE
},
3895 { "movdqu", { XM
, EXx
}, PREFIX_OPCODE
},
3896 { "movdqa", { XM
, EXx
}, PREFIX_OPCODE
},
3901 { "pshufw", { MX
, EM
, Ib
}, PREFIX_OPCODE
},
3902 { "pshufhw",{ XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3903 { "pshufd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3904 { "pshuflw",{ XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3907 /* PREFIX_0F73_REG_3 */
3911 { "psrldq", { XS
, Ib
}, 0 },
3914 /* PREFIX_0F73_REG_7 */
3918 { "pslldq", { XS
, Ib
}, 0 },
3923 {"vmread", { Em
, Gm
}, 0 },
3925 {"extrq", { XS
, Ib
, Ib
}, 0 },
3926 {"insertq", { XM
, XS
, Ib
, Ib
}, 0 },
3931 {"vmwrite", { Gm
, Em
}, 0 },
3933 {"extrq", { XM
, XS
}, 0 },
3934 {"insertq", { XM
, XS
}, 0 },
3941 { "haddpd", { XM
, EXx
}, PREFIX_OPCODE
},
3942 { "haddps", { XM
, EXx
}, PREFIX_OPCODE
},
3949 { "hsubpd", { XM
, EXx
}, PREFIX_OPCODE
},
3950 { "hsubps", { XM
, EXx
}, PREFIX_OPCODE
},
3955 { "movK", { Edq
, MX
}, PREFIX_OPCODE
},
3956 { "movq", { XM
, EXq
}, PREFIX_OPCODE
},
3957 { "movK", { Edq
, XM
}, PREFIX_OPCODE
},
3962 { "movq", { EMS
, MX
}, PREFIX_OPCODE
},
3963 { "movdqu", { EXxS
, XM
}, PREFIX_OPCODE
},
3964 { "movdqa", { EXxS
, XM
}, PREFIX_OPCODE
},
3967 /* PREFIX_0FAE_REG_0_MOD_3 */
3970 { "rdfsbase", { Ev
}, 0 },
3973 /* PREFIX_0FAE_REG_1_MOD_3 */
3976 { "rdgsbase", { Ev
}, 0 },
3979 /* PREFIX_0FAE_REG_2_MOD_3 */
3982 { "wrfsbase", { Ev
}, 0 },
3985 /* PREFIX_0FAE_REG_3_MOD_3 */
3988 { "wrgsbase", { Ev
}, 0 },
3991 /* PREFIX_0FAE_REG_4_MOD_0 */
3993 { "xsave", { FXSAVE
}, 0 },
3994 { "ptwrite%LQ", { Edq
}, 0 },
3997 /* PREFIX_0FAE_REG_4_MOD_3 */
4000 { "ptwrite%LQ", { Edq
}, 0 },
4003 /* PREFIX_0FAE_REG_5_MOD_0 */
4005 { "xrstor", { FXSAVE
}, PREFIX_OPCODE
},
4008 /* PREFIX_0FAE_REG_5_MOD_3 */
4010 { "lfence", { Skip_MODRM
}, 0 },
4011 { "incsspK", { Rdq
}, PREFIX_OPCODE
},
4014 /* PREFIX_0FAE_REG_6_MOD_0 */
4016 { "xsaveopt", { FXSAVE
}, PREFIX_OPCODE
},
4017 { "clrssbsy", { Mq
}, PREFIX_OPCODE
},
4018 { "clwb", { Mb
}, PREFIX_OPCODE
},
4021 /* PREFIX_0FAE_REG_6_MOD_3 */
4023 { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0
) },
4024 { "umonitor", { Eva
}, PREFIX_OPCODE
},
4025 { "tpause", { Edq
}, PREFIX_OPCODE
},
4026 { "umwait", { Edq
}, PREFIX_OPCODE
},
4029 /* PREFIX_0FAE_REG_7_MOD_0 */
4031 { "clflush", { Mb
}, 0 },
4033 { "clflushopt", { Mb
}, 0 },
4039 { "popcntS", { Gv
, Ev
}, 0 },
4044 { "bsfS", { Gv
, Ev
}, 0 },
4045 { "tzcntS", { Gv
, Ev
}, 0 },
4046 { "bsfS", { Gv
, Ev
}, 0 },
4051 { "bsrS", { Gv
, Ev
}, 0 },
4052 { "lzcntS", { Gv
, Ev
}, 0 },
4053 { "bsrS", { Gv
, Ev
}, 0 },
4058 { "cmpps", { XM
, EXx
, CMP
}, PREFIX_OPCODE
},
4059 { "cmpss", { XM
, EXd
, CMP
}, PREFIX_OPCODE
},
4060 { "cmppd", { XM
, EXx
, CMP
}, PREFIX_OPCODE
},
4061 { "cmpsd", { XM
, EXq
, CMP
}, PREFIX_OPCODE
},
4064 /* PREFIX_0FC3_MOD_0 */
4066 { "movntiS", { Edq
, Gdq
}, PREFIX_OPCODE
},
4069 /* PREFIX_0FC7_REG_6_MOD_0 */
4071 { "vmptrld",{ Mq
}, 0 },
4072 { "vmxon", { Mq
}, 0 },
4073 { "vmclear",{ Mq
}, 0 },
4076 /* PREFIX_0FC7_REG_6_MOD_3 */
4078 { "rdrand", { Ev
}, 0 },
4080 { "rdrand", { Ev
}, 0 }
4083 /* PREFIX_0FC7_REG_7_MOD_3 */
4085 { "rdseed", { Ev
}, 0 },
4086 { "rdpid", { Em
}, 0 },
4087 { "rdseed", { Ev
}, 0 },
4094 { "addsubpd", { XM
, EXx
}, 0 },
4095 { "addsubps", { XM
, EXx
}, 0 },
4101 { "movq2dq",{ XM
, MS
}, 0 },
4102 { "movq", { EXqS
, XM
}, 0 },
4103 { "movdq2q",{ MX
, XS
}, 0 },
4109 { "cvtdq2pd", { XM
, EXq
}, PREFIX_OPCODE
},
4110 { "cvttpd2dq", { XM
, EXx
}, PREFIX_OPCODE
},
4111 { "cvtpd2dq", { XM
, EXx
}, PREFIX_OPCODE
},
4116 { "movntq", { Mq
, MX
}, PREFIX_OPCODE
},
4118 { MOD_TABLE (MOD_0FE7_PREFIX_2
) },
4126 { MOD_TABLE (MOD_0FF0_PREFIX_3
) },
4131 { "maskmovq", { MX
, MS
}, PREFIX_OPCODE
},
4133 { "maskmovdqu", { XM
, XS
}, PREFIX_OPCODE
},
4140 { "pblendvb", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4147 { "blendvps", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4154 { "blendvpd", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4161 { "ptest", { XM
, EXx
}, PREFIX_OPCODE
},
4168 { "pmovsxbw", { XM
, EXq
}, PREFIX_OPCODE
},
4175 { "pmovsxbd", { XM
, EXd
}, PREFIX_OPCODE
},
4182 { "pmovsxbq", { XM
, EXw
}, PREFIX_OPCODE
},
4189 { "pmovsxwd", { XM
, EXq
}, PREFIX_OPCODE
},
4196 { "pmovsxwq", { XM
, EXd
}, PREFIX_OPCODE
},
4203 { "pmovsxdq", { XM
, EXq
}, PREFIX_OPCODE
},
4210 { "pmuldq", { XM
, EXx
}, PREFIX_OPCODE
},
4217 { "pcmpeqq", { XM
, EXx
}, PREFIX_OPCODE
},
4224 { MOD_TABLE (MOD_0F382A_PREFIX_2
) },
4231 { "packusdw", { XM
, EXx
}, PREFIX_OPCODE
},
4238 { "pmovzxbw", { XM
, EXq
}, PREFIX_OPCODE
},
4245 { "pmovzxbd", { XM
, EXd
}, PREFIX_OPCODE
},
4252 { "pmovzxbq", { XM
, EXw
}, PREFIX_OPCODE
},
4259 { "pmovzxwd", { XM
, EXq
}, PREFIX_OPCODE
},
4266 { "pmovzxwq", { XM
, EXd
}, PREFIX_OPCODE
},
4273 { "pmovzxdq", { XM
, EXq
}, PREFIX_OPCODE
},
4280 { "pcmpgtq", { XM
, EXx
}, PREFIX_OPCODE
},
4287 { "pminsb", { XM
, EXx
}, PREFIX_OPCODE
},
4294 { "pminsd", { XM
, EXx
}, PREFIX_OPCODE
},
4301 { "pminuw", { XM
, EXx
}, PREFIX_OPCODE
},
4308 { "pminud", { XM
, EXx
}, PREFIX_OPCODE
},
4315 { "pmaxsb", { XM
, EXx
}, PREFIX_OPCODE
},
4322 { "pmaxsd", { XM
, EXx
}, PREFIX_OPCODE
},
4329 { "pmaxuw", { XM
, EXx
}, PREFIX_OPCODE
},
4336 { "pmaxud", { XM
, EXx
}, PREFIX_OPCODE
},
4343 { "pmulld", { XM
, EXx
}, PREFIX_OPCODE
},
4350 { "phminposuw", { XM
, EXx
}, PREFIX_OPCODE
},
4357 { "invept", { Gm
, Mo
}, PREFIX_OPCODE
},
4364 { "invvpid", { Gm
, Mo
}, PREFIX_OPCODE
},
4371 { "invpcid", { Gm
, M
}, PREFIX_OPCODE
},
4376 { "sha1nexte", { XM
, EXxmm
}, PREFIX_OPCODE
},
4381 { "sha1msg1", { XM
, EXxmm
}, PREFIX_OPCODE
},
4386 { "sha1msg2", { XM
, EXxmm
}, PREFIX_OPCODE
},
4391 { "sha256rnds2", { XM
, EXxmm
, XMM0
}, PREFIX_OPCODE
},
4396 { "sha256msg1", { XM
, EXxmm
}, PREFIX_OPCODE
},
4401 { "sha256msg2", { XM
, EXxmm
}, PREFIX_OPCODE
},
4408 { "gf2p8mulb", { XM
, EXxmm
}, PREFIX_OPCODE
},
4415 { "aesimc", { XM
, EXx
}, PREFIX_OPCODE
},
4422 { "aesenc", { XM
, EXx
}, PREFIX_OPCODE
},
4429 { "aesenclast", { XM
, EXx
}, PREFIX_OPCODE
},
4436 { "aesdec", { XM
, EXx
}, PREFIX_OPCODE
},
4443 { "aesdeclast", { XM
, EXx
}, PREFIX_OPCODE
},
4448 { "movbeS", { Gv
, { MOVBE_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4450 { "movbeS", { Gv
, { MOVBE_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4451 { "crc32", { Gdq
, { CRC32_Fixup
, b_mode
} }, PREFIX_OPCODE
},
4456 { "movbeS", { { MOVBE_Fixup
, v_mode
}, Gv
}, PREFIX_OPCODE
},
4458 { "movbeS", { { MOVBE_Fixup
, v_mode
}, Gv
}, PREFIX_OPCODE
},
4459 { "crc32", { Gdq
, { CRC32_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4466 { MOD_TABLE (MOD_0F38F5_PREFIX_2
) },
4471 { MOD_TABLE (MOD_0F38F6_PREFIX_0
) },
4472 { "adoxS", { Gdq
, Edq
}, PREFIX_OPCODE
},
4473 { "adcxS", { Gdq
, Edq
}, PREFIX_OPCODE
},
4480 { MOD_TABLE (MOD_0F38F8_PREFIX_1
) },
4481 { MOD_TABLE (MOD_0F38F8_PREFIX_2
) },
4482 { MOD_TABLE (MOD_0F38F8_PREFIX_3
) },
4487 { MOD_TABLE (MOD_0F38F9_PREFIX_0
) },
4494 { "roundps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4501 { "roundpd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4508 { "roundss", { XM
, EXd
, Ib
}, PREFIX_OPCODE
},
4515 { "roundsd", { XM
, EXq
, Ib
}, PREFIX_OPCODE
},
4522 { "blendps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4529 { "blendpd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4536 { "pblendw", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4543 { "pextrb", { Edqb
, XM
, Ib
}, PREFIX_OPCODE
},
4550 { "pextrw", { Edqw
, XM
, Ib
}, PREFIX_OPCODE
},
4557 { "pextrK", { Edq
, XM
, Ib
}, PREFIX_OPCODE
},
4564 { "extractps", { Edqd
, XM
, Ib
}, PREFIX_OPCODE
},
4571 { "pinsrb", { XM
, Edqb
, Ib
}, PREFIX_OPCODE
},
4578 { "insertps", { XM
, EXd
, Ib
}, PREFIX_OPCODE
},
4585 { "pinsrK", { XM
, Edq
, Ib
}, PREFIX_OPCODE
},
4592 { "dpps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4599 { "dppd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4606 { "mpsadbw", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4613 { "pclmulqdq", { XM
, EXx
, PCLMUL
}, PREFIX_OPCODE
},
4620 { "pcmpestrm", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, PREFIX_OPCODE
},
4627 { "pcmpestri", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, PREFIX_OPCODE
},
4634 { "pcmpistrm", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4641 { "pcmpistri", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4646 { "sha1rnds4", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4653 { "gf2p8affineqb", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4660 { "gf2p8affineinvqb", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4667 { "aeskeygenassist", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4670 /* PREFIX_VEX_0F10 */
4672 { "vmovups", { XM
, EXx
}, 0 },
4673 { "vmovss", { XMVexScalar
, VexScalar
, EXdScalar
}, 0 },
4674 { "vmovupd", { XM
, EXx
}, 0 },
4675 { "vmovsd", { XMVexScalar
, VexScalar
, EXqScalar
}, 0 },
4678 /* PREFIX_VEX_0F11 */
4680 { "vmovups", { EXxS
, XM
}, 0 },
4681 { "vmovss", { EXdVexScalarS
, VexScalar
, XMScalar
}, 0 },
4682 { "vmovupd", { EXxS
, XM
}, 0 },
4683 { "vmovsd", { EXqVexScalarS
, VexScalar
, XMScalar
}, 0 },
4686 /* PREFIX_VEX_0F12 */
4688 { MOD_TABLE (MOD_VEX_0F12_PREFIX_0
) },
4689 { "vmovsldup", { XM
, EXx
}, 0 },
4690 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2
) },
4691 { "vmovddup", { XM
, EXymmq
}, 0 },
4694 /* PREFIX_VEX_0F16 */
4696 { MOD_TABLE (MOD_VEX_0F16_PREFIX_0
) },
4697 { "vmovshdup", { XM
, EXx
}, 0 },
4698 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2
) },
4701 /* PREFIX_VEX_0F2A */
4704 { "vcvtsi2ss%LQ", { XMScalar
, VexScalar
, Edq
}, 0 },
4706 { "vcvtsi2sd%LQ", { XMScalar
, VexScalar
, Edq
}, 0 },
4709 /* PREFIX_VEX_0F2C */
4712 { "vcvttss2si", { Gdq
, EXdScalar
}, 0 },
4714 { "vcvttsd2si", { Gdq
, EXqScalar
}, 0 },
4717 /* PREFIX_VEX_0F2D */
4720 { "vcvtss2si", { Gdq
, EXdScalar
}, 0 },
4722 { "vcvtsd2si", { Gdq
, EXqScalar
}, 0 },
4725 /* PREFIX_VEX_0F2E */
4727 { "vucomiss", { XMScalar
, EXdScalar
}, 0 },
4729 { "vucomisd", { XMScalar
, EXqScalar
}, 0 },
4732 /* PREFIX_VEX_0F2F */
4734 { "vcomiss", { XMScalar
, EXdScalar
}, 0 },
4736 { "vcomisd", { XMScalar
, EXqScalar
}, 0 },
4739 /* PREFIX_VEX_0F41 */
4741 { VEX_LEN_TABLE (VEX_LEN_0F41_P_0
) },
4743 { VEX_LEN_TABLE (VEX_LEN_0F41_P_2
) },
4746 /* PREFIX_VEX_0F42 */
4748 { VEX_LEN_TABLE (VEX_LEN_0F42_P_0
) },
4750 { VEX_LEN_TABLE (VEX_LEN_0F42_P_2
) },
4753 /* PREFIX_VEX_0F44 */
4755 { VEX_LEN_TABLE (VEX_LEN_0F44_P_0
) },
4757 { VEX_LEN_TABLE (VEX_LEN_0F44_P_2
) },
4760 /* PREFIX_VEX_0F45 */
4762 { VEX_LEN_TABLE (VEX_LEN_0F45_P_0
) },
4764 { VEX_LEN_TABLE (VEX_LEN_0F45_P_2
) },
4767 /* PREFIX_VEX_0F46 */
4769 { VEX_LEN_TABLE (VEX_LEN_0F46_P_0
) },
4771 { VEX_LEN_TABLE (VEX_LEN_0F46_P_2
) },
4774 /* PREFIX_VEX_0F47 */
4776 { VEX_LEN_TABLE (VEX_LEN_0F47_P_0
) },
4778 { VEX_LEN_TABLE (VEX_LEN_0F47_P_2
) },
4781 /* PREFIX_VEX_0F4A */
4783 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0
) },
4785 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2
) },
4788 /* PREFIX_VEX_0F4B */
4790 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0
) },
4792 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2
) },
4795 /* PREFIX_VEX_0F51 */
4797 { "vsqrtps", { XM
, EXx
}, 0 },
4798 { "vsqrtss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4799 { "vsqrtpd", { XM
, EXx
}, 0 },
4800 { "vsqrtsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4803 /* PREFIX_VEX_0F52 */
4805 { "vrsqrtps", { XM
, EXx
}, 0 },
4806 { "vrsqrtss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4809 /* PREFIX_VEX_0F53 */
4811 { "vrcpps", { XM
, EXx
}, 0 },
4812 { "vrcpss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4815 /* PREFIX_VEX_0F58 */
4817 { "vaddps", { XM
, Vex
, EXx
}, 0 },
4818 { "vaddss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4819 { "vaddpd", { XM
, Vex
, EXx
}, 0 },
4820 { "vaddsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4823 /* PREFIX_VEX_0F59 */
4825 { "vmulps", { XM
, Vex
, EXx
}, 0 },
4826 { "vmulss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4827 { "vmulpd", { XM
, Vex
, EXx
}, 0 },
4828 { "vmulsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4831 /* PREFIX_VEX_0F5A */
4833 { "vcvtps2pd", { XM
, EXxmmq
}, 0 },
4834 { "vcvtss2sd", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4835 { "vcvtpd2ps%XY",{ XMM
, EXx
}, 0 },
4836 { "vcvtsd2ss", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4839 /* PREFIX_VEX_0F5B */
4841 { "vcvtdq2ps", { XM
, EXx
}, 0 },
4842 { "vcvttps2dq", { XM
, EXx
}, 0 },
4843 { "vcvtps2dq", { XM
, EXx
}, 0 },
4846 /* PREFIX_VEX_0F5C */
4848 { "vsubps", { XM
, Vex
, EXx
}, 0 },
4849 { "vsubss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4850 { "vsubpd", { XM
, Vex
, EXx
}, 0 },
4851 { "vsubsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4854 /* PREFIX_VEX_0F5D */
4856 { "vminps", { XM
, Vex
, EXx
}, 0 },
4857 { "vminss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4858 { "vminpd", { XM
, Vex
, EXx
}, 0 },
4859 { "vminsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4862 /* PREFIX_VEX_0F5E */
4864 { "vdivps", { XM
, Vex
, EXx
}, 0 },
4865 { "vdivss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4866 { "vdivpd", { XM
, Vex
, EXx
}, 0 },
4867 { "vdivsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4870 /* PREFIX_VEX_0F5F */
4872 { "vmaxps", { XM
, Vex
, EXx
}, 0 },
4873 { "vmaxss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4874 { "vmaxpd", { XM
, Vex
, EXx
}, 0 },
4875 { "vmaxsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4878 /* PREFIX_VEX_0F60 */
4882 { "vpunpcklbw", { XM
, Vex
, EXx
}, 0 },
4885 /* PREFIX_VEX_0F61 */
4889 { "vpunpcklwd", { XM
, Vex
, EXx
}, 0 },
4892 /* PREFIX_VEX_0F62 */
4896 { "vpunpckldq", { XM
, Vex
, EXx
}, 0 },
4899 /* PREFIX_VEX_0F63 */
4903 { "vpacksswb", { XM
, Vex
, EXx
}, 0 },
4906 /* PREFIX_VEX_0F64 */
4910 { "vpcmpgtb", { XM
, Vex
, EXx
}, 0 },
4913 /* PREFIX_VEX_0F65 */
4917 { "vpcmpgtw", { XM
, Vex
, EXx
}, 0 },
4920 /* PREFIX_VEX_0F66 */
4924 { "vpcmpgtd", { XM
, Vex
, EXx
}, 0 },
4927 /* PREFIX_VEX_0F67 */
4931 { "vpackuswb", { XM
, Vex
, EXx
}, 0 },
4934 /* PREFIX_VEX_0F68 */
4938 { "vpunpckhbw", { XM
, Vex
, EXx
}, 0 },
4941 /* PREFIX_VEX_0F69 */
4945 { "vpunpckhwd", { XM
, Vex
, EXx
}, 0 },
4948 /* PREFIX_VEX_0F6A */
4952 { "vpunpckhdq", { XM
, Vex
, EXx
}, 0 },
4955 /* PREFIX_VEX_0F6B */
4959 { "vpackssdw", { XM
, Vex
, EXx
}, 0 },
4962 /* PREFIX_VEX_0F6C */
4966 { "vpunpcklqdq", { XM
, Vex
, EXx
}, 0 },
4969 /* PREFIX_VEX_0F6D */
4973 { "vpunpckhqdq", { XM
, Vex
, EXx
}, 0 },
4976 /* PREFIX_VEX_0F6E */
4980 { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2
) },
4983 /* PREFIX_VEX_0F6F */
4986 { "vmovdqu", { XM
, EXx
}, 0 },
4987 { "vmovdqa", { XM
, EXx
}, 0 },
4990 /* PREFIX_VEX_0F70 */
4993 { "vpshufhw", { XM
, EXx
, Ib
}, 0 },
4994 { "vpshufd", { XM
, EXx
, Ib
}, 0 },
4995 { "vpshuflw", { XM
, EXx
, Ib
}, 0 },
4998 /* PREFIX_VEX_0F71_REG_2 */
5002 { "vpsrlw", { Vex
, XS
, Ib
}, 0 },
5005 /* PREFIX_VEX_0F71_REG_4 */
5009 { "vpsraw", { Vex
, XS
, Ib
}, 0 },
5012 /* PREFIX_VEX_0F71_REG_6 */
5016 { "vpsllw", { Vex
, XS
, Ib
}, 0 },
5019 /* PREFIX_VEX_0F72_REG_2 */
5023 { "vpsrld", { Vex
, XS
, Ib
}, 0 },
5026 /* PREFIX_VEX_0F72_REG_4 */
5030 { "vpsrad", { Vex
, XS
, Ib
}, 0 },
5033 /* PREFIX_VEX_0F72_REG_6 */
5037 { "vpslld", { Vex
, XS
, Ib
}, 0 },
5040 /* PREFIX_VEX_0F73_REG_2 */
5044 { "vpsrlq", { Vex
, XS
, Ib
}, 0 },
5047 /* PREFIX_VEX_0F73_REG_3 */
5051 { "vpsrldq", { Vex
, XS
, Ib
}, 0 },
5054 /* PREFIX_VEX_0F73_REG_6 */
5058 { "vpsllq", { Vex
, XS
, Ib
}, 0 },
5061 /* PREFIX_VEX_0F73_REG_7 */
5065 { "vpslldq", { Vex
, XS
, Ib
}, 0 },
5068 /* PREFIX_VEX_0F74 */
5072 { "vpcmpeqb", { XM
, Vex
, EXx
}, 0 },
5075 /* PREFIX_VEX_0F75 */
5079 { "vpcmpeqw", { XM
, Vex
, EXx
}, 0 },
5082 /* PREFIX_VEX_0F76 */
5086 { "vpcmpeqd", { XM
, Vex
, EXx
}, 0 },
5089 /* PREFIX_VEX_0F77 */
5091 { VEX_LEN_TABLE (VEX_LEN_0F77_P_0
) },
5094 /* PREFIX_VEX_0F7C */
5098 { "vhaddpd", { XM
, Vex
, EXx
}, 0 },
5099 { "vhaddps", { XM
, Vex
, EXx
}, 0 },
5102 /* PREFIX_VEX_0F7D */
5106 { "vhsubpd", { XM
, Vex
, EXx
}, 0 },
5107 { "vhsubps", { XM
, Vex
, EXx
}, 0 },
5110 /* PREFIX_VEX_0F7E */
5113 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1
) },
5114 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2
) },
5117 /* PREFIX_VEX_0F7F */
5120 { "vmovdqu", { EXxS
, XM
}, 0 },
5121 { "vmovdqa", { EXxS
, XM
}, 0 },
5124 /* PREFIX_VEX_0F90 */
5126 { VEX_LEN_TABLE (VEX_LEN_0F90_P_0
) },
5128 { VEX_LEN_TABLE (VEX_LEN_0F90_P_2
) },
5131 /* PREFIX_VEX_0F91 */
5133 { VEX_LEN_TABLE (VEX_LEN_0F91_P_0
) },
5135 { VEX_LEN_TABLE (VEX_LEN_0F91_P_2
) },
5138 /* PREFIX_VEX_0F92 */
5140 { VEX_LEN_TABLE (VEX_LEN_0F92_P_0
) },
5142 { VEX_LEN_TABLE (VEX_LEN_0F92_P_2
) },
5143 { VEX_LEN_TABLE (VEX_LEN_0F92_P_3
) },
5146 /* PREFIX_VEX_0F93 */
5148 { VEX_LEN_TABLE (VEX_LEN_0F93_P_0
) },
5150 { VEX_LEN_TABLE (VEX_LEN_0F93_P_2
) },
5151 { VEX_LEN_TABLE (VEX_LEN_0F93_P_3
) },
5154 /* PREFIX_VEX_0F98 */
5156 { VEX_LEN_TABLE (VEX_LEN_0F98_P_0
) },
5158 { VEX_LEN_TABLE (VEX_LEN_0F98_P_2
) },
5161 /* PREFIX_VEX_0F99 */
5163 { VEX_LEN_TABLE (VEX_LEN_0F99_P_0
) },
5165 { VEX_LEN_TABLE (VEX_LEN_0F99_P_2
) },
5168 /* PREFIX_VEX_0FC2 */
5170 { "vcmpps", { XM
, Vex
, EXx
, VCMP
}, 0 },
5171 { "vcmpss", { XMScalar
, VexScalar
, EXdScalar
, VCMP
}, 0 },
5172 { "vcmppd", { XM
, Vex
, EXx
, VCMP
}, 0 },
5173 { "vcmpsd", { XMScalar
, VexScalar
, EXqScalar
, VCMP
}, 0 },
5176 /* PREFIX_VEX_0FC4 */
5180 { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2
) },
5183 /* PREFIX_VEX_0FC5 */
5187 { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2
) },
5190 /* PREFIX_VEX_0FD0 */
5194 { "vaddsubpd", { XM
, Vex
, EXx
}, 0 },
5195 { "vaddsubps", { XM
, Vex
, EXx
}, 0 },
5198 /* PREFIX_VEX_0FD1 */
5202 { "vpsrlw", { XM
, Vex
, EXxmm
}, 0 },
5205 /* PREFIX_VEX_0FD2 */
5209 { "vpsrld", { XM
, Vex
, EXxmm
}, 0 },
5212 /* PREFIX_VEX_0FD3 */
5216 { "vpsrlq", { XM
, Vex
, EXxmm
}, 0 },
5219 /* PREFIX_VEX_0FD4 */
5223 { "vpaddq", { XM
, Vex
, EXx
}, 0 },
5226 /* PREFIX_VEX_0FD5 */
5230 { "vpmullw", { XM
, Vex
, EXx
}, 0 },
5233 /* PREFIX_VEX_0FD6 */
5237 { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2
) },
5240 /* PREFIX_VEX_0FD7 */
5244 { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2
) },
5247 /* PREFIX_VEX_0FD8 */
5251 { "vpsubusb", { XM
, Vex
, EXx
}, 0 },
5254 /* PREFIX_VEX_0FD9 */
5258 { "vpsubusw", { XM
, Vex
, EXx
}, 0 },
5261 /* PREFIX_VEX_0FDA */
5265 { "vpminub", { XM
, Vex
, EXx
}, 0 },
5268 /* PREFIX_VEX_0FDB */
5272 { "vpand", { XM
, Vex
, EXx
}, 0 },
5275 /* PREFIX_VEX_0FDC */
5279 { "vpaddusb", { XM
, Vex
, EXx
}, 0 },
5282 /* PREFIX_VEX_0FDD */
5286 { "vpaddusw", { XM
, Vex
, EXx
}, 0 },
5289 /* PREFIX_VEX_0FDE */
5293 { "vpmaxub", { XM
, Vex
, EXx
}, 0 },
5296 /* PREFIX_VEX_0FDF */
5300 { "vpandn", { XM
, Vex
, EXx
}, 0 },
5303 /* PREFIX_VEX_0FE0 */
5307 { "vpavgb", { XM
, Vex
, EXx
}, 0 },
5310 /* PREFIX_VEX_0FE1 */
5314 { "vpsraw", { XM
, Vex
, EXxmm
}, 0 },
5317 /* PREFIX_VEX_0FE2 */
5321 { "vpsrad", { XM
, Vex
, EXxmm
}, 0 },
5324 /* PREFIX_VEX_0FE3 */
5328 { "vpavgw", { XM
, Vex
, EXx
}, 0 },
5331 /* PREFIX_VEX_0FE4 */
5335 { "vpmulhuw", { XM
, Vex
, EXx
}, 0 },
5338 /* PREFIX_VEX_0FE5 */
5342 { "vpmulhw", { XM
, Vex
, EXx
}, 0 },
5345 /* PREFIX_VEX_0FE6 */
5348 { "vcvtdq2pd", { XM
, EXxmmq
}, 0 },
5349 { "vcvttpd2dq%XY", { XMM
, EXx
}, 0 },
5350 { "vcvtpd2dq%XY", { XMM
, EXx
}, 0 },
5353 /* PREFIX_VEX_0FE7 */
5357 { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2
) },
5360 /* PREFIX_VEX_0FE8 */
5364 { "vpsubsb", { XM
, Vex
, EXx
}, 0 },
5367 /* PREFIX_VEX_0FE9 */
5371 { "vpsubsw", { XM
, Vex
, EXx
}, 0 },
5374 /* PREFIX_VEX_0FEA */
5378 { "vpminsw", { XM
, Vex
, EXx
}, 0 },
5381 /* PREFIX_VEX_0FEB */
5385 { "vpor", { XM
, Vex
, EXx
}, 0 },
5388 /* PREFIX_VEX_0FEC */
5392 { "vpaddsb", { XM
, Vex
, EXx
}, 0 },
5395 /* PREFIX_VEX_0FED */
5399 { "vpaddsw", { XM
, Vex
, EXx
}, 0 },
5402 /* PREFIX_VEX_0FEE */
5406 { "vpmaxsw", { XM
, Vex
, EXx
}, 0 },
5409 /* PREFIX_VEX_0FEF */
5413 { "vpxor", { XM
, Vex
, EXx
}, 0 },
5416 /* PREFIX_VEX_0FF0 */
5421 { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3
) },
5424 /* PREFIX_VEX_0FF1 */
5428 { "vpsllw", { XM
, Vex
, EXxmm
}, 0 },
5431 /* PREFIX_VEX_0FF2 */
5435 { "vpslld", { XM
, Vex
, EXxmm
}, 0 },
5438 /* PREFIX_VEX_0FF3 */
5442 { "vpsllq", { XM
, Vex
, EXxmm
}, 0 },
5445 /* PREFIX_VEX_0FF4 */
5449 { "vpmuludq", { XM
, Vex
, EXx
}, 0 },
5452 /* PREFIX_VEX_0FF5 */
5456 { "vpmaddwd", { XM
, Vex
, EXx
}, 0 },
5459 /* PREFIX_VEX_0FF6 */
5463 { "vpsadbw", { XM
, Vex
, EXx
}, 0 },
5466 /* PREFIX_VEX_0FF7 */
5470 { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2
) },
5473 /* PREFIX_VEX_0FF8 */
5477 { "vpsubb", { XM
, Vex
, EXx
}, 0 },
5480 /* PREFIX_VEX_0FF9 */
5484 { "vpsubw", { XM
, Vex
, EXx
}, 0 },
5487 /* PREFIX_VEX_0FFA */
5491 { "vpsubd", { XM
, Vex
, EXx
}, 0 },
5494 /* PREFIX_VEX_0FFB */
5498 { "vpsubq", { XM
, Vex
, EXx
}, 0 },
5501 /* PREFIX_VEX_0FFC */
5505 { "vpaddb", { XM
, Vex
, EXx
}, 0 },
5508 /* PREFIX_VEX_0FFD */
5512 { "vpaddw", { XM
, Vex
, EXx
}, 0 },
5515 /* PREFIX_VEX_0FFE */
5519 { "vpaddd", { XM
, Vex
, EXx
}, 0 },
5522 /* PREFIX_VEX_0F3800 */
5526 { "vpshufb", { XM
, Vex
, EXx
}, 0 },
5529 /* PREFIX_VEX_0F3801 */
5533 { "vphaddw", { XM
, Vex
, EXx
}, 0 },
5536 /* PREFIX_VEX_0F3802 */
5540 { "vphaddd", { XM
, Vex
, EXx
}, 0 },
5543 /* PREFIX_VEX_0F3803 */
5547 { "vphaddsw", { XM
, Vex
, EXx
}, 0 },
5550 /* PREFIX_VEX_0F3804 */
5554 { "vpmaddubsw", { XM
, Vex
, EXx
}, 0 },
5557 /* PREFIX_VEX_0F3805 */
5561 { "vphsubw", { XM
, Vex
, EXx
}, 0 },
5564 /* PREFIX_VEX_0F3806 */
5568 { "vphsubd", { XM
, Vex
, EXx
}, 0 },
5571 /* PREFIX_VEX_0F3807 */
5575 { "vphsubsw", { XM
, Vex
, EXx
}, 0 },
5578 /* PREFIX_VEX_0F3808 */
5582 { "vpsignb", { XM
, Vex
, EXx
}, 0 },
5585 /* PREFIX_VEX_0F3809 */
5589 { "vpsignw", { XM
, Vex
, EXx
}, 0 },
5592 /* PREFIX_VEX_0F380A */
5596 { "vpsignd", { XM
, Vex
, EXx
}, 0 },
5599 /* PREFIX_VEX_0F380B */
5603 { "vpmulhrsw", { XM
, Vex
, EXx
}, 0 },
5606 /* PREFIX_VEX_0F380C */
5610 { VEX_W_TABLE (VEX_W_0F380C_P_2
) },
5613 /* PREFIX_VEX_0F380D */
5617 { VEX_W_TABLE (VEX_W_0F380D_P_2
) },
5620 /* PREFIX_VEX_0F380E */
5624 { VEX_W_TABLE (VEX_W_0F380E_P_2
) },
5627 /* PREFIX_VEX_0F380F */
5631 { VEX_W_TABLE (VEX_W_0F380F_P_2
) },
5634 /* PREFIX_VEX_0F3813 */
5638 { "vcvtph2ps", { XM
, EXxmmq
}, 0 },
5641 /* PREFIX_VEX_0F3816 */
5645 { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2
) },
5648 /* PREFIX_VEX_0F3817 */
5652 { "vptest", { XM
, EXx
}, 0 },
5655 /* PREFIX_VEX_0F3818 */
5659 { VEX_W_TABLE (VEX_W_0F3818_P_2
) },
5662 /* PREFIX_VEX_0F3819 */
5666 { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2
) },
5669 /* PREFIX_VEX_0F381A */
5673 { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2
) },
5676 /* PREFIX_VEX_0F381C */
5680 { "vpabsb", { XM
, EXx
}, 0 },
5683 /* PREFIX_VEX_0F381D */
5687 { "vpabsw", { XM
, EXx
}, 0 },
5690 /* PREFIX_VEX_0F381E */
5694 { "vpabsd", { XM
, EXx
}, 0 },
5697 /* PREFIX_VEX_0F3820 */
5701 { "vpmovsxbw", { XM
, EXxmmq
}, 0 },
5704 /* PREFIX_VEX_0F3821 */
5708 { "vpmovsxbd", { XM
, EXxmmqd
}, 0 },
5711 /* PREFIX_VEX_0F3822 */
5715 { "vpmovsxbq", { XM
, EXxmmdw
}, 0 },
5718 /* PREFIX_VEX_0F3823 */
5722 { "vpmovsxwd", { XM
, EXxmmq
}, 0 },
5725 /* PREFIX_VEX_0F3824 */
5729 { "vpmovsxwq", { XM
, EXxmmqd
}, 0 },
5732 /* PREFIX_VEX_0F3825 */
5736 { "vpmovsxdq", { XM
, EXxmmq
}, 0 },
5739 /* PREFIX_VEX_0F3828 */
5743 { "vpmuldq", { XM
, Vex
, EXx
}, 0 },
5746 /* PREFIX_VEX_0F3829 */
5750 { "vpcmpeqq", { XM
, Vex
, EXx
}, 0 },
5753 /* PREFIX_VEX_0F382A */
5757 { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2
) },
5760 /* PREFIX_VEX_0F382B */
5764 { "vpackusdw", { XM
, Vex
, EXx
}, 0 },
5767 /* PREFIX_VEX_0F382C */
5771 { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2
) },
5774 /* PREFIX_VEX_0F382D */
5778 { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2
) },
5781 /* PREFIX_VEX_0F382E */
5785 { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2
) },
5788 /* PREFIX_VEX_0F382F */
5792 { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2
) },
5795 /* PREFIX_VEX_0F3830 */
5799 { "vpmovzxbw", { XM
, EXxmmq
}, 0 },
5802 /* PREFIX_VEX_0F3831 */
5806 { "vpmovzxbd", { XM
, EXxmmqd
}, 0 },
5809 /* PREFIX_VEX_0F3832 */
5813 { "vpmovzxbq", { XM
, EXxmmdw
}, 0 },
5816 /* PREFIX_VEX_0F3833 */
5820 { "vpmovzxwd", { XM
, EXxmmq
}, 0 },
5823 /* PREFIX_VEX_0F3834 */
5827 { "vpmovzxwq", { XM
, EXxmmqd
}, 0 },
5830 /* PREFIX_VEX_0F3835 */
5834 { "vpmovzxdq", { XM
, EXxmmq
}, 0 },
5837 /* PREFIX_VEX_0F3836 */
5841 { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2
) },
5844 /* PREFIX_VEX_0F3837 */
5848 { "vpcmpgtq", { XM
, Vex
, EXx
}, 0 },
5851 /* PREFIX_VEX_0F3838 */
5855 { "vpminsb", { XM
, Vex
, EXx
}, 0 },
5858 /* PREFIX_VEX_0F3839 */
5862 { "vpminsd", { XM
, Vex
, EXx
}, 0 },
5865 /* PREFIX_VEX_0F383A */
5869 { "vpminuw", { XM
, Vex
, EXx
}, 0 },
5872 /* PREFIX_VEX_0F383B */
5876 { "vpminud", { XM
, Vex
, EXx
}, 0 },
5879 /* PREFIX_VEX_0F383C */
5883 { "vpmaxsb", { XM
, Vex
, EXx
}, 0 },
5886 /* PREFIX_VEX_0F383D */
5890 { "vpmaxsd", { XM
, Vex
, EXx
}, 0 },
5893 /* PREFIX_VEX_0F383E */
5897 { "vpmaxuw", { XM
, Vex
, EXx
}, 0 },
5900 /* PREFIX_VEX_0F383F */
5904 { "vpmaxud", { XM
, Vex
, EXx
}, 0 },
5907 /* PREFIX_VEX_0F3840 */
5911 { "vpmulld", { XM
, Vex
, EXx
}, 0 },
5914 /* PREFIX_VEX_0F3841 */
5918 { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2
) },
5921 /* PREFIX_VEX_0F3845 */
5925 { "vpsrlv%LW", { XM
, Vex
, EXx
}, 0 },
5928 /* PREFIX_VEX_0F3846 */
5932 { VEX_W_TABLE (VEX_W_0F3846_P_2
) },
5935 /* PREFIX_VEX_0F3847 */
5939 { "vpsllv%LW", { XM
, Vex
, EXx
}, 0 },
5942 /* PREFIX_VEX_0F3858 */
5946 { VEX_W_TABLE (VEX_W_0F3858_P_2
) },
5949 /* PREFIX_VEX_0F3859 */
5953 { VEX_W_TABLE (VEX_W_0F3859_P_2
) },
5956 /* PREFIX_VEX_0F385A */
5960 { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2
) },
5963 /* PREFIX_VEX_0F3878 */
5967 { VEX_W_TABLE (VEX_W_0F3878_P_2
) },
5970 /* PREFIX_VEX_0F3879 */
5974 { VEX_W_TABLE (VEX_W_0F3879_P_2
) },
5977 /* PREFIX_VEX_0F388C */
5981 { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2
) },
5984 /* PREFIX_VEX_0F388E */
5988 { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2
) },
5991 /* PREFIX_VEX_0F3890 */
5995 { "vpgatherd%LW", { XM
, MVexVSIBDWpX
, Vex
}, 0 },
5998 /* PREFIX_VEX_0F3891 */
6002 { "vpgatherq%LW", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
}, 0 },
6005 /* PREFIX_VEX_0F3892 */
6009 { "vgatherdp%XW", { XM
, MVexVSIBDWpX
, Vex
}, 0 },
6012 /* PREFIX_VEX_0F3893 */
6016 { "vgatherqp%XW", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
}, 0 },
6019 /* PREFIX_VEX_0F3896 */
6023 { "vfmaddsub132p%XW", { XM
, Vex
, EXx
}, 0 },
6026 /* PREFIX_VEX_0F3897 */
6030 { "vfmsubadd132p%XW", { XM
, Vex
, EXx
}, 0 },
6033 /* PREFIX_VEX_0F3898 */
6037 { "vfmadd132p%XW", { XM
, Vex
, EXx
}, 0 },
6040 /* PREFIX_VEX_0F3899 */
6044 { "vfmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6047 /* PREFIX_VEX_0F389A */
6051 { "vfmsub132p%XW", { XM
, Vex
, EXx
}, 0 },
6054 /* PREFIX_VEX_0F389B */
6058 { "vfmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6061 /* PREFIX_VEX_0F389C */
6065 { "vfnmadd132p%XW", { XM
, Vex
, EXx
}, 0 },
6068 /* PREFIX_VEX_0F389D */
6072 { "vfnmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6075 /* PREFIX_VEX_0F389E */
6079 { "vfnmsub132p%XW", { XM
, Vex
, EXx
}, 0 },
6082 /* PREFIX_VEX_0F389F */
6086 { "vfnmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6089 /* PREFIX_VEX_0F38A6 */
6093 { "vfmaddsub213p%XW", { XM
, Vex
, EXx
}, 0 },
6097 /* PREFIX_VEX_0F38A7 */
6101 { "vfmsubadd213p%XW", { XM
, Vex
, EXx
}, 0 },
6104 /* PREFIX_VEX_0F38A8 */
6108 { "vfmadd213p%XW", { XM
, Vex
, EXx
}, 0 },
6111 /* PREFIX_VEX_0F38A9 */
6115 { "vfmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6118 /* PREFIX_VEX_0F38AA */
6122 { "vfmsub213p%XW", { XM
, Vex
, EXx
}, 0 },
6125 /* PREFIX_VEX_0F38AB */
6129 { "vfmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6132 /* PREFIX_VEX_0F38AC */
6136 { "vfnmadd213p%XW", { XM
, Vex
, EXx
}, 0 },
6139 /* PREFIX_VEX_0F38AD */
6143 { "vfnmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6146 /* PREFIX_VEX_0F38AE */
6150 { "vfnmsub213p%XW", { XM
, Vex
, EXx
}, 0 },
6153 /* PREFIX_VEX_0F38AF */
6157 { "vfnmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6160 /* PREFIX_VEX_0F38B6 */
6164 { "vfmaddsub231p%XW", { XM
, Vex
, EXx
}, 0 },
6167 /* PREFIX_VEX_0F38B7 */
6171 { "vfmsubadd231p%XW", { XM
, Vex
, EXx
}, 0 },
6174 /* PREFIX_VEX_0F38B8 */
6178 { "vfmadd231p%XW", { XM
, Vex
, EXx
}, 0 },
6181 /* PREFIX_VEX_0F38B9 */
6185 { "vfmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6188 /* PREFIX_VEX_0F38BA */
6192 { "vfmsub231p%XW", { XM
, Vex
, EXx
}, 0 },
6195 /* PREFIX_VEX_0F38BB */
6199 { "vfmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6202 /* PREFIX_VEX_0F38BC */
6206 { "vfnmadd231p%XW", { XM
, Vex
, EXx
}, 0 },
6209 /* PREFIX_VEX_0F38BD */
6213 { "vfnmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6216 /* PREFIX_VEX_0F38BE */
6220 { "vfnmsub231p%XW", { XM
, Vex
, EXx
}, 0 },
6223 /* PREFIX_VEX_0F38BF */
6227 { "vfnmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6230 /* PREFIX_VEX_0F38CF */
6234 { VEX_W_TABLE (VEX_W_0F38CF_P_2
) },
6237 /* PREFIX_VEX_0F38DB */
6241 { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2
) },
6244 /* PREFIX_VEX_0F38DC */
6248 { "vaesenc", { XM
, Vex
, EXx
}, 0 },
6251 /* PREFIX_VEX_0F38DD */
6255 { "vaesenclast", { XM
, Vex
, EXx
}, 0 },
6258 /* PREFIX_VEX_0F38DE */
6262 { "vaesdec", { XM
, Vex
, EXx
}, 0 },
6265 /* PREFIX_VEX_0F38DF */
6269 { "vaesdeclast", { XM
, Vex
, EXx
}, 0 },
6272 /* PREFIX_VEX_0F38F2 */
6274 { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0
) },
6277 /* PREFIX_VEX_0F38F3_REG_1 */
6279 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0
) },
6282 /* PREFIX_VEX_0F38F3_REG_2 */
6284 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0
) },
6287 /* PREFIX_VEX_0F38F3_REG_3 */
6289 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0
) },
6292 /* PREFIX_VEX_0F38F5 */
6294 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0
) },
6295 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1
) },
6297 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3
) },
6300 /* PREFIX_VEX_0F38F6 */
6305 { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3
) },
6308 /* PREFIX_VEX_0F38F7 */
6310 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0
) },
6311 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1
) },
6312 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2
) },
6313 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3
) },
6316 /* PREFIX_VEX_0F3A00 */
6320 { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2
) },
6323 /* PREFIX_VEX_0F3A01 */
6327 { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2
) },
6330 /* PREFIX_VEX_0F3A02 */
6334 { VEX_W_TABLE (VEX_W_0F3A02_P_2
) },
6337 /* PREFIX_VEX_0F3A04 */
6341 { VEX_W_TABLE (VEX_W_0F3A04_P_2
) },
6344 /* PREFIX_VEX_0F3A05 */
6348 { VEX_W_TABLE (VEX_W_0F3A05_P_2
) },
6351 /* PREFIX_VEX_0F3A06 */
6355 { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2
) },
6358 /* PREFIX_VEX_0F3A08 */
6362 { "vroundps", { XM
, EXx
, Ib
}, 0 },
6365 /* PREFIX_VEX_0F3A09 */
6369 { "vroundpd", { XM
, EXx
, Ib
}, 0 },
6372 /* PREFIX_VEX_0F3A0A */
6376 { "vroundss", { XMScalar
, VexScalar
, EXdScalar
, Ib
}, 0 },
6379 /* PREFIX_VEX_0F3A0B */
6383 { "vroundsd", { XMScalar
, VexScalar
, EXqScalar
, Ib
}, 0 },
6386 /* PREFIX_VEX_0F3A0C */
6390 { "vblendps", { XM
, Vex
, EXx
, Ib
}, 0 },
6393 /* PREFIX_VEX_0F3A0D */
6397 { "vblendpd", { XM
, Vex
, EXx
, Ib
}, 0 },
6400 /* PREFIX_VEX_0F3A0E */
6404 { "vpblendw", { XM
, Vex
, EXx
, Ib
}, 0 },
6407 /* PREFIX_VEX_0F3A0F */
6411 { "vpalignr", { XM
, Vex
, EXx
, Ib
}, 0 },
6414 /* PREFIX_VEX_0F3A14 */
6418 { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2
) },
6421 /* PREFIX_VEX_0F3A15 */
6425 { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2
) },
6428 /* PREFIX_VEX_0F3A16 */
6432 { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2
) },
6435 /* PREFIX_VEX_0F3A17 */
6439 { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2
) },
6442 /* PREFIX_VEX_0F3A18 */
6446 { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2
) },
6449 /* PREFIX_VEX_0F3A19 */
6453 { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2
) },
6456 /* PREFIX_VEX_0F3A1D */
6460 { "vcvtps2ph", { EXxmmq
, XM
, Ib
}, 0 },
6463 /* PREFIX_VEX_0F3A20 */
6467 { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2
) },
6470 /* PREFIX_VEX_0F3A21 */
6474 { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2
) },
6477 /* PREFIX_VEX_0F3A22 */
6481 { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2
) },
6484 /* PREFIX_VEX_0F3A30 */
6488 { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2
) },
6491 /* PREFIX_VEX_0F3A31 */
6495 { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2
) },
6498 /* PREFIX_VEX_0F3A32 */
6502 { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2
) },
6505 /* PREFIX_VEX_0F3A33 */
6509 { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2
) },
6512 /* PREFIX_VEX_0F3A38 */
6516 { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2
) },
6519 /* PREFIX_VEX_0F3A39 */
6523 { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2
) },
6526 /* PREFIX_VEX_0F3A40 */
6530 { "vdpps", { XM
, Vex
, EXx
, Ib
}, 0 },
6533 /* PREFIX_VEX_0F3A41 */
6537 { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2
) },
6540 /* PREFIX_VEX_0F3A42 */
6544 { "vmpsadbw", { XM
, Vex
, EXx
, Ib
}, 0 },
6547 /* PREFIX_VEX_0F3A44 */
6551 { "vpclmulqdq", { XM
, Vex
, EXx
, PCLMUL
}, 0 },
6554 /* PREFIX_VEX_0F3A46 */
6558 { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2
) },
6561 /* PREFIX_VEX_0F3A48 */
6565 { VEX_W_TABLE (VEX_W_0F3A48_P_2
) },
6568 /* PREFIX_VEX_0F3A49 */
6572 { VEX_W_TABLE (VEX_W_0F3A49_P_2
) },
6575 /* PREFIX_VEX_0F3A4A */
6579 { VEX_W_TABLE (VEX_W_0F3A4A_P_2
) },
6582 /* PREFIX_VEX_0F3A4B */
6586 { VEX_W_TABLE (VEX_W_0F3A4B_P_2
) },
6589 /* PREFIX_VEX_0F3A4C */
6593 { VEX_W_TABLE (VEX_W_0F3A4C_P_2
) },
6596 /* PREFIX_VEX_0F3A5C */
6600 { "vfmaddsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6603 /* PREFIX_VEX_0F3A5D */
6607 { "vfmaddsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6610 /* PREFIX_VEX_0F3A5E */
6614 { "vfmsubaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6617 /* PREFIX_VEX_0F3A5F */
6621 { "vfmsubaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6624 /* PREFIX_VEX_0F3A60 */
6628 { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2
) },
6632 /* PREFIX_VEX_0F3A61 */
6636 { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2
) },
6639 /* PREFIX_VEX_0F3A62 */
6643 { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2
) },
6646 /* PREFIX_VEX_0F3A63 */
6650 { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2
) },
6653 /* PREFIX_VEX_0F3A68 */
6657 { "vfmaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6660 /* PREFIX_VEX_0F3A69 */
6664 { "vfmaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6667 /* PREFIX_VEX_0F3A6A */
6671 { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2
) },
6674 /* PREFIX_VEX_0F3A6B */
6678 { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2
) },
6681 /* PREFIX_VEX_0F3A6C */
6685 { "vfmsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6688 /* PREFIX_VEX_0F3A6D */
6692 { "vfmsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6695 /* PREFIX_VEX_0F3A6E */
6699 { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2
) },
6702 /* PREFIX_VEX_0F3A6F */
6706 { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2
) },
6709 /* PREFIX_VEX_0F3A78 */
6713 { "vfnmaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6716 /* PREFIX_VEX_0F3A79 */
6720 { "vfnmaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6723 /* PREFIX_VEX_0F3A7A */
6727 { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2
) },
6730 /* PREFIX_VEX_0F3A7B */
6734 { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2
) },
6737 /* PREFIX_VEX_0F3A7C */
6741 { "vfnmsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6745 /* PREFIX_VEX_0F3A7D */
6749 { "vfnmsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6752 /* PREFIX_VEX_0F3A7E */
6756 { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2
) },
6759 /* PREFIX_VEX_0F3A7F */
6763 { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2
) },
6766 /* PREFIX_VEX_0F3ACE */
6770 { VEX_W_TABLE (VEX_W_0F3ACE_P_2
) },
6773 /* PREFIX_VEX_0F3ACF */
6777 { VEX_W_TABLE (VEX_W_0F3ACF_P_2
) },
6780 /* PREFIX_VEX_0F3ADF */
6784 { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2
) },
6787 /* PREFIX_VEX_0F3AF0 */
6792 { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3
) },
6795 #include "i386-dis-evex-prefix.h"
6798 static const struct dis386 x86_64_table
[][2] = {
6801 { "pushP", { es
}, 0 },
6806 { "popP", { es
}, 0 },
6811 { "pushP", { cs
}, 0 },
6816 { "pushP", { ss
}, 0 },
6821 { "popP", { ss
}, 0 },
6826 { "pushP", { ds
}, 0 },
6831 { "popP", { ds
}, 0 },
6836 { "daa", { XX
}, 0 },
6841 { "das", { XX
}, 0 },
6846 { "aaa", { XX
}, 0 },
6851 { "aas", { XX
}, 0 },
6856 { "pushaP", { XX
}, 0 },
6861 { "popaP", { XX
}, 0 },
6866 { MOD_TABLE (MOD_62_32BIT
) },
6867 { EVEX_TABLE (EVEX_0F
) },
6872 { "arpl", { Ew
, Gw
}, 0 },
6873 { "movs", { { OP_G
, movsxd_mode
}, { MOVSXD_Fixup
, movsxd_mode
} }, 0 },
6878 { "ins{R|}", { Yzr
, indirDX
}, 0 },
6879 { "ins{G|}", { Yzr
, indirDX
}, 0 },
6884 { "outs{R|}", { indirDXr
, Xz
}, 0 },
6885 { "outs{G|}", { indirDXr
, Xz
}, 0 },
6890 /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode. */
6891 { REG_TABLE (REG_80
) },
6896 { "Jcall{T|}", { Ap
}, 0 },
6901 { "retP", { Iw
, BND
}, 0 },
6902 { "ret@", { Iw
, BND
}, 0 },
6907 { "retP", { BND
}, 0 },
6908 { "ret@", { BND
}, 0 },
6913 { MOD_TABLE (MOD_C4_32BIT
) },
6914 { VEX_C4_TABLE (VEX_0F
) },
6919 { MOD_TABLE (MOD_C5_32BIT
) },
6920 { VEX_C5_TABLE (VEX_0F
) },
6925 { "into", { XX
}, 0 },
6930 { "aam", { Ib
}, 0 },
6935 { "aad", { Ib
}, 0 },
6940 { "callP", { Jv
, BND
}, 0 },
6941 { "call@", { Jv
, BND
}, 0 }
6946 { "jmpP", { Jv
, BND
}, 0 },
6947 { "jmp@", { Jv
, BND
}, 0 }
6952 { "Jjmp{T|}", { Ap
}, 0 },
6955 /* X86_64_0F01_REG_0 */
6957 { "sgdt{Q|IQ}", { M
}, 0 },
6958 { "sgdt", { M
}, 0 },
6961 /* X86_64_0F01_REG_1 */
6963 { "sidt{Q|IQ}", { M
}, 0 },
6964 { "sidt", { M
}, 0 },
6967 /* X86_64_0F01_REG_2 */
6969 { "lgdt{Q|Q}", { M
}, 0 },
6970 { "lgdt", { M
}, 0 },
6973 /* X86_64_0F01_REG_3 */
6975 { "lidt{Q|Q}", { M
}, 0 },
6976 { "lidt", { M
}, 0 },
6980 static const struct dis386 three_byte_table
[][256] = {
6982 /* THREE_BYTE_0F38 */
6985 { "pshufb", { MX
, EM
}, PREFIX_OPCODE
},
6986 { "phaddw", { MX
, EM
}, PREFIX_OPCODE
},
6987 { "phaddd", { MX
, EM
}, PREFIX_OPCODE
},
6988 { "phaddsw", { MX
, EM
}, PREFIX_OPCODE
},
6989 { "pmaddubsw", { MX
, EM
}, PREFIX_OPCODE
},
6990 { "phsubw", { MX
, EM
}, PREFIX_OPCODE
},
6991 { "phsubd", { MX
, EM
}, PREFIX_OPCODE
},
6992 { "phsubsw", { MX
, EM
}, PREFIX_OPCODE
},
6994 { "psignb", { MX
, EM
}, PREFIX_OPCODE
},
6995 { "psignw", { MX
, EM
}, PREFIX_OPCODE
},
6996 { "psignd", { MX
, EM
}, PREFIX_OPCODE
},
6997 { "pmulhrsw", { MX
, EM
}, PREFIX_OPCODE
},
7003 { PREFIX_TABLE (PREFIX_0F3810
) },
7007 { PREFIX_TABLE (PREFIX_0F3814
) },
7008 { PREFIX_TABLE (PREFIX_0F3815
) },
7010 { PREFIX_TABLE (PREFIX_0F3817
) },
7016 { "pabsb", { MX
, EM
}, PREFIX_OPCODE
},
7017 { "pabsw", { MX
, EM
}, PREFIX_OPCODE
},
7018 { "pabsd", { MX
, EM
}, PREFIX_OPCODE
},
7021 { PREFIX_TABLE (PREFIX_0F3820
) },
7022 { PREFIX_TABLE (PREFIX_0F3821
) },
7023 { PREFIX_TABLE (PREFIX_0F3822
) },
7024 { PREFIX_TABLE (PREFIX_0F3823
) },
7025 { PREFIX_TABLE (PREFIX_0F3824
) },
7026 { PREFIX_TABLE (PREFIX_0F3825
) },
7030 { PREFIX_TABLE (PREFIX_0F3828
) },
7031 { PREFIX_TABLE (PREFIX_0F3829
) },
7032 { PREFIX_TABLE (PREFIX_0F382A
) },
7033 { PREFIX_TABLE (PREFIX_0F382B
) },
7039 { PREFIX_TABLE (PREFIX_0F3830
) },
7040 { PREFIX_TABLE (PREFIX_0F3831
) },
7041 { PREFIX_TABLE (PREFIX_0F3832
) },
7042 { PREFIX_TABLE (PREFIX_0F3833
) },
7043 { PREFIX_TABLE (PREFIX_0F3834
) },
7044 { PREFIX_TABLE (PREFIX_0F3835
) },
7046 { PREFIX_TABLE (PREFIX_0F3837
) },
7048 { PREFIX_TABLE (PREFIX_0F3838
) },
7049 { PREFIX_TABLE (PREFIX_0F3839
) },
7050 { PREFIX_TABLE (PREFIX_0F383A
) },
7051 { PREFIX_TABLE (PREFIX_0F383B
) },
7052 { PREFIX_TABLE (PREFIX_0F383C
) },
7053 { PREFIX_TABLE (PREFIX_0F383D
) },
7054 { PREFIX_TABLE (PREFIX_0F383E
) },
7055 { PREFIX_TABLE (PREFIX_0F383F
) },
7057 { PREFIX_TABLE (PREFIX_0F3840
) },
7058 { PREFIX_TABLE (PREFIX_0F3841
) },
7129 { PREFIX_TABLE (PREFIX_0F3880
) },
7130 { PREFIX_TABLE (PREFIX_0F3881
) },
7131 { PREFIX_TABLE (PREFIX_0F3882
) },
7210 { PREFIX_TABLE (PREFIX_0F38C8
) },
7211 { PREFIX_TABLE (PREFIX_0F38C9
) },
7212 { PREFIX_TABLE (PREFIX_0F38CA
) },
7213 { PREFIX_TABLE (PREFIX_0F38CB
) },
7214 { PREFIX_TABLE (PREFIX_0F38CC
) },
7215 { PREFIX_TABLE (PREFIX_0F38CD
) },
7217 { PREFIX_TABLE (PREFIX_0F38CF
) },
7231 { PREFIX_TABLE (PREFIX_0F38DB
) },
7232 { PREFIX_TABLE (PREFIX_0F38DC
) },
7233 { PREFIX_TABLE (PREFIX_0F38DD
) },
7234 { PREFIX_TABLE (PREFIX_0F38DE
) },
7235 { PREFIX_TABLE (PREFIX_0F38DF
) },
7255 { PREFIX_TABLE (PREFIX_0F38F0
) },
7256 { PREFIX_TABLE (PREFIX_0F38F1
) },
7260 { PREFIX_TABLE (PREFIX_0F38F5
) },
7261 { PREFIX_TABLE (PREFIX_0F38F6
) },
7264 { PREFIX_TABLE (PREFIX_0F38F8
) },
7265 { PREFIX_TABLE (PREFIX_0F38F9
) },
7273 /* THREE_BYTE_0F3A */
7285 { PREFIX_TABLE (PREFIX_0F3A08
) },
7286 { PREFIX_TABLE (PREFIX_0F3A09
) },
7287 { PREFIX_TABLE (PREFIX_0F3A0A
) },
7288 { PREFIX_TABLE (PREFIX_0F3A0B
) },
7289 { PREFIX_TABLE (PREFIX_0F3A0C
) },
7290 { PREFIX_TABLE (PREFIX_0F3A0D
) },
7291 { PREFIX_TABLE (PREFIX_0F3A0E
) },
7292 { "palignr", { MX
, EM
, Ib
}, PREFIX_OPCODE
},
7298 { PREFIX_TABLE (PREFIX_0F3A14
) },
7299 { PREFIX_TABLE (PREFIX_0F3A15
) },
7300 { PREFIX_TABLE (PREFIX_0F3A16
) },
7301 { PREFIX_TABLE (PREFIX_0F3A17
) },
7312 { PREFIX_TABLE (PREFIX_0F3A20
) },
7313 { PREFIX_TABLE (PREFIX_0F3A21
) },
7314 { PREFIX_TABLE (PREFIX_0F3A22
) },
7348 { PREFIX_TABLE (PREFIX_0F3A40
) },
7349 { PREFIX_TABLE (PREFIX_0F3A41
) },
7350 { PREFIX_TABLE (PREFIX_0F3A42
) },
7352 { PREFIX_TABLE (PREFIX_0F3A44
) },
7384 { PREFIX_TABLE (PREFIX_0F3A60
) },
7385 { PREFIX_TABLE (PREFIX_0F3A61
) },
7386 { PREFIX_TABLE (PREFIX_0F3A62
) },
7387 { PREFIX_TABLE (PREFIX_0F3A63
) },
7505 { PREFIX_TABLE (PREFIX_0F3ACC
) },
7507 { PREFIX_TABLE (PREFIX_0F3ACE
) },
7508 { PREFIX_TABLE (PREFIX_0F3ACF
) },
7526 { PREFIX_TABLE (PREFIX_0F3ADF
) },
7566 static const struct dis386 xop_table
[][256] = {
7719 { "vpmacssww", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7720 { "vpmacsswd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7721 { "vpmacssdql", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7729 { "vpmacssdd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7730 { "vpmacssdqh", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7737 { "vpmacsww", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7738 { "vpmacswd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7739 { "vpmacsdql", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7747 { "vpmacsdd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7748 { "vpmacsdqh", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7752 { "vpcmov", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7753 { "vpperm", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7756 { "vpmadcsswd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7774 { "vpmadcswd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7786 { "vprotb", { XM
, Vex_2src_1
, Ib
}, 0 },
7787 { "vprotw", { XM
, Vex_2src_1
, Ib
}, 0 },
7788 { "vprotd", { XM
, Vex_2src_1
, Ib
}, 0 },
7789 { "vprotq", { XM
, Vex_2src_1
, Ib
}, 0 },
7799 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC
) },
7800 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD
) },
7801 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE
) },
7802 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF
) },
7835 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC
) },
7836 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED
) },
7837 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE
) },
7838 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF
) },
7862 { REG_TABLE (REG_XOP_TBM_01
) },
7863 { REG_TABLE (REG_XOP_TBM_02
) },
7881 { REG_TABLE (REG_XOP_LWPCB
) },
8005 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80
) },
8006 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81
) },
8007 { "vfrczss", { XM
, EXd
}, 0 },
8008 { "vfrczsd", { XM
, EXq
}, 0 },
8023 { "vprotb", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8024 { "vprotw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8025 { "vprotd", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8026 { "vprotq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8027 { "vpshlb", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8028 { "vpshlw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8029 { "vpshld", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8030 { "vpshlq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8032 { "vpshab", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8033 { "vpshaw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8034 { "vpshad", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8035 { "vpshaq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8078 { "vphaddbw", { XM
, EXxmm
}, 0 },
8079 { "vphaddbd", { XM
, EXxmm
}, 0 },
8080 { "vphaddbq", { XM
, EXxmm
}, 0 },
8083 { "vphaddwd", { XM
, EXxmm
}, 0 },
8084 { "vphaddwq", { XM
, EXxmm
}, 0 },
8089 { "vphadddq", { XM
, EXxmm
}, 0 },
8096 { "vphaddubw", { XM
, EXxmm
}, 0 },
8097 { "vphaddubd", { XM
, EXxmm
}, 0 },
8098 { "vphaddubq", { XM
, EXxmm
}, 0 },
8101 { "vphadduwd", { XM
, EXxmm
}, 0 },
8102 { "vphadduwq", { XM
, EXxmm
}, 0 },
8107 { "vphaddudq", { XM
, EXxmm
}, 0 },
8114 { "vphsubbw", { XM
, EXxmm
}, 0 },
8115 { "vphsubwd", { XM
, EXxmm
}, 0 },
8116 { "vphsubdq", { XM
, EXxmm
}, 0 },
8170 { "bextrS", { Gdq
, Edq
, Id
}, 0 },
8172 { REG_TABLE (REG_XOP_LWP
) },
8442 static const struct dis386 vex_table
[][256] = {
8464 { PREFIX_TABLE (PREFIX_VEX_0F10
) },
8465 { PREFIX_TABLE (PREFIX_VEX_0F11
) },
8466 { PREFIX_TABLE (PREFIX_VEX_0F12
) },
8467 { MOD_TABLE (MOD_VEX_0F13
) },
8468 { "vunpcklpX", { XM
, Vex
, EXx
}, 0 },
8469 { "vunpckhpX", { XM
, Vex
, EXx
}, 0 },
8470 { PREFIX_TABLE (PREFIX_VEX_0F16
) },
8471 { MOD_TABLE (MOD_VEX_0F17
) },
8491 { "vmovapX", { XM
, EXx
}, 0 },
8492 { "vmovapX", { EXxS
, XM
}, 0 },
8493 { PREFIX_TABLE (PREFIX_VEX_0F2A
) },
8494 { MOD_TABLE (MOD_VEX_0F2B
) },
8495 { PREFIX_TABLE (PREFIX_VEX_0F2C
) },
8496 { PREFIX_TABLE (PREFIX_VEX_0F2D
) },
8497 { PREFIX_TABLE (PREFIX_VEX_0F2E
) },
8498 { PREFIX_TABLE (PREFIX_VEX_0F2F
) },
8519 { PREFIX_TABLE (PREFIX_VEX_0F41
) },
8520 { PREFIX_TABLE (PREFIX_VEX_0F42
) },
8522 { PREFIX_TABLE (PREFIX_VEX_0F44
) },
8523 { PREFIX_TABLE (PREFIX_VEX_0F45
) },
8524 { PREFIX_TABLE (PREFIX_VEX_0F46
) },
8525 { PREFIX_TABLE (PREFIX_VEX_0F47
) },
8529 { PREFIX_TABLE (PREFIX_VEX_0F4A
) },
8530 { PREFIX_TABLE (PREFIX_VEX_0F4B
) },
8536 { MOD_TABLE (MOD_VEX_0F50
) },
8537 { PREFIX_TABLE (PREFIX_VEX_0F51
) },
8538 { PREFIX_TABLE (PREFIX_VEX_0F52
) },
8539 { PREFIX_TABLE (PREFIX_VEX_0F53
) },
8540 { "vandpX", { XM
, Vex
, EXx
}, 0 },
8541 { "vandnpX", { XM
, Vex
, EXx
}, 0 },
8542 { "vorpX", { XM
, Vex
, EXx
}, 0 },
8543 { "vxorpX", { XM
, Vex
, EXx
}, 0 },
8545 { PREFIX_TABLE (PREFIX_VEX_0F58
) },
8546 { PREFIX_TABLE (PREFIX_VEX_0F59
) },
8547 { PREFIX_TABLE (PREFIX_VEX_0F5A
) },
8548 { PREFIX_TABLE (PREFIX_VEX_0F5B
) },
8549 { PREFIX_TABLE (PREFIX_VEX_0F5C
) },
8550 { PREFIX_TABLE (PREFIX_VEX_0F5D
) },
8551 { PREFIX_TABLE (PREFIX_VEX_0F5E
) },
8552 { PREFIX_TABLE (PREFIX_VEX_0F5F
) },
8554 { PREFIX_TABLE (PREFIX_VEX_0F60
) },
8555 { PREFIX_TABLE (PREFIX_VEX_0F61
) },
8556 { PREFIX_TABLE (PREFIX_VEX_0F62
) },
8557 { PREFIX_TABLE (PREFIX_VEX_0F63
) },
8558 { PREFIX_TABLE (PREFIX_VEX_0F64
) },
8559 { PREFIX_TABLE (PREFIX_VEX_0F65
) },
8560 { PREFIX_TABLE (PREFIX_VEX_0F66
) },
8561 { PREFIX_TABLE (PREFIX_VEX_0F67
) },
8563 { PREFIX_TABLE (PREFIX_VEX_0F68
) },
8564 { PREFIX_TABLE (PREFIX_VEX_0F69
) },
8565 { PREFIX_TABLE (PREFIX_VEX_0F6A
) },
8566 { PREFIX_TABLE (PREFIX_VEX_0F6B
) },
8567 { PREFIX_TABLE (PREFIX_VEX_0F6C
) },
8568 { PREFIX_TABLE (PREFIX_VEX_0F6D
) },
8569 { PREFIX_TABLE (PREFIX_VEX_0F6E
) },
8570 { PREFIX_TABLE (PREFIX_VEX_0F6F
) },
8572 { PREFIX_TABLE (PREFIX_VEX_0F70
) },
8573 { REG_TABLE (REG_VEX_0F71
) },
8574 { REG_TABLE (REG_VEX_0F72
) },
8575 { REG_TABLE (REG_VEX_0F73
) },
8576 { PREFIX_TABLE (PREFIX_VEX_0F74
) },
8577 { PREFIX_TABLE (PREFIX_VEX_0F75
) },
8578 { PREFIX_TABLE (PREFIX_VEX_0F76
) },
8579 { PREFIX_TABLE (PREFIX_VEX_0F77
) },
8585 { PREFIX_TABLE (PREFIX_VEX_0F7C
) },
8586 { PREFIX_TABLE (PREFIX_VEX_0F7D
) },
8587 { PREFIX_TABLE (PREFIX_VEX_0F7E
) },
8588 { PREFIX_TABLE (PREFIX_VEX_0F7F
) },
8608 { PREFIX_TABLE (PREFIX_VEX_0F90
) },
8609 { PREFIX_TABLE (PREFIX_VEX_0F91
) },
8610 { PREFIX_TABLE (PREFIX_VEX_0F92
) },
8611 { PREFIX_TABLE (PREFIX_VEX_0F93
) },
8617 { PREFIX_TABLE (PREFIX_VEX_0F98
) },
8618 { PREFIX_TABLE (PREFIX_VEX_0F99
) },
8641 { REG_TABLE (REG_VEX_0FAE
) },
8664 { PREFIX_TABLE (PREFIX_VEX_0FC2
) },
8666 { PREFIX_TABLE (PREFIX_VEX_0FC4
) },
8667 { PREFIX_TABLE (PREFIX_VEX_0FC5
) },
8668 { "vshufpX", { XM
, Vex
, EXx
, Ib
}, 0 },
8680 { PREFIX_TABLE (PREFIX_VEX_0FD0
) },
8681 { PREFIX_TABLE (PREFIX_VEX_0FD1
) },
8682 { PREFIX_TABLE (PREFIX_VEX_0FD2
) },
8683 { PREFIX_TABLE (PREFIX_VEX_0FD3
) },
8684 { PREFIX_TABLE (PREFIX_VEX_0FD4
) },
8685 { PREFIX_TABLE (PREFIX_VEX_0FD5
) },
8686 { PREFIX_TABLE (PREFIX_VEX_0FD6
) },
8687 { PREFIX_TABLE (PREFIX_VEX_0FD7
) },
8689 { PREFIX_TABLE (PREFIX_VEX_0FD8
) },
8690 { PREFIX_TABLE (PREFIX_VEX_0FD9
) },
8691 { PREFIX_TABLE (PREFIX_VEX_0FDA
) },
8692 { PREFIX_TABLE (PREFIX_VEX_0FDB
) },
8693 { PREFIX_TABLE (PREFIX_VEX_0FDC
) },
8694 { PREFIX_TABLE (PREFIX_VEX_0FDD
) },
8695 { PREFIX_TABLE (PREFIX_VEX_0FDE
) },
8696 { PREFIX_TABLE (PREFIX_VEX_0FDF
) },
8698 { PREFIX_TABLE (PREFIX_VEX_0FE0
) },
8699 { PREFIX_TABLE (PREFIX_VEX_0FE1
) },
8700 { PREFIX_TABLE (PREFIX_VEX_0FE2
) },
8701 { PREFIX_TABLE (PREFIX_VEX_0FE3
) },
8702 { PREFIX_TABLE (PREFIX_VEX_0FE4
) },
8703 { PREFIX_TABLE (PREFIX_VEX_0FE5
) },
8704 { PREFIX_TABLE (PREFIX_VEX_0FE6
) },
8705 { PREFIX_TABLE (PREFIX_VEX_0FE7
) },
8707 { PREFIX_TABLE (PREFIX_VEX_0FE8
) },
8708 { PREFIX_TABLE (PREFIX_VEX_0FE9
) },
8709 { PREFIX_TABLE (PREFIX_VEX_0FEA
) },
8710 { PREFIX_TABLE (PREFIX_VEX_0FEB
) },
8711 { PREFIX_TABLE (PREFIX_VEX_0FEC
) },
8712 { PREFIX_TABLE (PREFIX_VEX_0FED
) },
8713 { PREFIX_TABLE (PREFIX_VEX_0FEE
) },
8714 { PREFIX_TABLE (PREFIX_VEX_0FEF
) },
8716 { PREFIX_TABLE (PREFIX_VEX_0FF0
) },
8717 { PREFIX_TABLE (PREFIX_VEX_0FF1
) },
8718 { PREFIX_TABLE (PREFIX_VEX_0FF2
) },
8719 { PREFIX_TABLE (PREFIX_VEX_0FF3
) },
8720 { PREFIX_TABLE (PREFIX_VEX_0FF4
) },
8721 { PREFIX_TABLE (PREFIX_VEX_0FF5
) },
8722 { PREFIX_TABLE (PREFIX_VEX_0FF6
) },
8723 { PREFIX_TABLE (PREFIX_VEX_0FF7
) },
8725 { PREFIX_TABLE (PREFIX_VEX_0FF8
) },
8726 { PREFIX_TABLE (PREFIX_VEX_0FF9
) },
8727 { PREFIX_TABLE (PREFIX_VEX_0FFA
) },
8728 { PREFIX_TABLE (PREFIX_VEX_0FFB
) },
8729 { PREFIX_TABLE (PREFIX_VEX_0FFC
) },
8730 { PREFIX_TABLE (PREFIX_VEX_0FFD
) },
8731 { PREFIX_TABLE (PREFIX_VEX_0FFE
) },
8737 { PREFIX_TABLE (PREFIX_VEX_0F3800
) },
8738 { PREFIX_TABLE (PREFIX_VEX_0F3801
) },
8739 { PREFIX_TABLE (PREFIX_VEX_0F3802
) },
8740 { PREFIX_TABLE (PREFIX_VEX_0F3803
) },
8741 { PREFIX_TABLE (PREFIX_VEX_0F3804
) },
8742 { PREFIX_TABLE (PREFIX_VEX_0F3805
) },
8743 { PREFIX_TABLE (PREFIX_VEX_0F3806
) },
8744 { PREFIX_TABLE (PREFIX_VEX_0F3807
) },
8746 { PREFIX_TABLE (PREFIX_VEX_0F3808
) },
8747 { PREFIX_TABLE (PREFIX_VEX_0F3809
) },
8748 { PREFIX_TABLE (PREFIX_VEX_0F380A
) },
8749 { PREFIX_TABLE (PREFIX_VEX_0F380B
) },
8750 { PREFIX_TABLE (PREFIX_VEX_0F380C
) },
8751 { PREFIX_TABLE (PREFIX_VEX_0F380D
) },
8752 { PREFIX_TABLE (PREFIX_VEX_0F380E
) },
8753 { PREFIX_TABLE (PREFIX_VEX_0F380F
) },
8758 { PREFIX_TABLE (PREFIX_VEX_0F3813
) },
8761 { PREFIX_TABLE (PREFIX_VEX_0F3816
) },
8762 { PREFIX_TABLE (PREFIX_VEX_0F3817
) },
8764 { PREFIX_TABLE (PREFIX_VEX_0F3818
) },
8765 { PREFIX_TABLE (PREFIX_VEX_0F3819
) },
8766 { PREFIX_TABLE (PREFIX_VEX_0F381A
) },
8768 { PREFIX_TABLE (PREFIX_VEX_0F381C
) },
8769 { PREFIX_TABLE (PREFIX_VEX_0F381D
) },
8770 { PREFIX_TABLE (PREFIX_VEX_0F381E
) },
8773 { PREFIX_TABLE (PREFIX_VEX_0F3820
) },
8774 { PREFIX_TABLE (PREFIX_VEX_0F3821
) },
8775 { PREFIX_TABLE (PREFIX_VEX_0F3822
) },
8776 { PREFIX_TABLE (PREFIX_VEX_0F3823
) },
8777 { PREFIX_TABLE (PREFIX_VEX_0F3824
) },
8778 { PREFIX_TABLE (PREFIX_VEX_0F3825
) },
8782 { PREFIX_TABLE (PREFIX_VEX_0F3828
) },
8783 { PREFIX_TABLE (PREFIX_VEX_0F3829
) },
8784 { PREFIX_TABLE (PREFIX_VEX_0F382A
) },
8785 { PREFIX_TABLE (PREFIX_VEX_0F382B
) },
8786 { PREFIX_TABLE (PREFIX_VEX_0F382C
) },
8787 { PREFIX_TABLE (PREFIX_VEX_0F382D
) },
8788 { PREFIX_TABLE (PREFIX_VEX_0F382E
) },
8789 { PREFIX_TABLE (PREFIX_VEX_0F382F
) },
8791 { PREFIX_TABLE (PREFIX_VEX_0F3830
) },
8792 { PREFIX_TABLE (PREFIX_VEX_0F3831
) },
8793 { PREFIX_TABLE (PREFIX_VEX_0F3832
) },
8794 { PREFIX_TABLE (PREFIX_VEX_0F3833
) },
8795 { PREFIX_TABLE (PREFIX_VEX_0F3834
) },
8796 { PREFIX_TABLE (PREFIX_VEX_0F3835
) },
8797 { PREFIX_TABLE (PREFIX_VEX_0F3836
) },
8798 { PREFIX_TABLE (PREFIX_VEX_0F3837
) },
8800 { PREFIX_TABLE (PREFIX_VEX_0F3838
) },
8801 { PREFIX_TABLE (PREFIX_VEX_0F3839
) },
8802 { PREFIX_TABLE (PREFIX_VEX_0F383A
) },
8803 { PREFIX_TABLE (PREFIX_VEX_0F383B
) },
8804 { PREFIX_TABLE (PREFIX_VEX_0F383C
) },
8805 { PREFIX_TABLE (PREFIX_VEX_0F383D
) },
8806 { PREFIX_TABLE (PREFIX_VEX_0F383E
) },
8807 { PREFIX_TABLE (PREFIX_VEX_0F383F
) },
8809 { PREFIX_TABLE (PREFIX_VEX_0F3840
) },
8810 { PREFIX_TABLE (PREFIX_VEX_0F3841
) },
8814 { PREFIX_TABLE (PREFIX_VEX_0F3845
) },
8815 { PREFIX_TABLE (PREFIX_VEX_0F3846
) },
8816 { PREFIX_TABLE (PREFIX_VEX_0F3847
) },
8836 { PREFIX_TABLE (PREFIX_VEX_0F3858
) },
8837 { PREFIX_TABLE (PREFIX_VEX_0F3859
) },
8838 { PREFIX_TABLE (PREFIX_VEX_0F385A
) },
8872 { PREFIX_TABLE (PREFIX_VEX_0F3878
) },
8873 { PREFIX_TABLE (PREFIX_VEX_0F3879
) },
8894 { PREFIX_TABLE (PREFIX_VEX_0F388C
) },
8896 { PREFIX_TABLE (PREFIX_VEX_0F388E
) },
8899 { PREFIX_TABLE (PREFIX_VEX_0F3890
) },
8900 { PREFIX_TABLE (PREFIX_VEX_0F3891
) },
8901 { PREFIX_TABLE (PREFIX_VEX_0F3892
) },
8902 { PREFIX_TABLE (PREFIX_VEX_0F3893
) },
8905 { PREFIX_TABLE (PREFIX_VEX_0F3896
) },
8906 { PREFIX_TABLE (PREFIX_VEX_0F3897
) },
8908 { PREFIX_TABLE (PREFIX_VEX_0F3898
) },
8909 { PREFIX_TABLE (PREFIX_VEX_0F3899
) },
8910 { PREFIX_TABLE (PREFIX_VEX_0F389A
) },
8911 { PREFIX_TABLE (PREFIX_VEX_0F389B
) },
8912 { PREFIX_TABLE (PREFIX_VEX_0F389C
) },
8913 { PREFIX_TABLE (PREFIX_VEX_0F389D
) },
8914 { PREFIX_TABLE (PREFIX_VEX_0F389E
) },
8915 { PREFIX_TABLE (PREFIX_VEX_0F389F
) },
8923 { PREFIX_TABLE (PREFIX_VEX_0F38A6
) },
8924 { PREFIX_TABLE (PREFIX_VEX_0F38A7
) },
8926 { PREFIX_TABLE (PREFIX_VEX_0F38A8
) },
8927 { PREFIX_TABLE (PREFIX_VEX_0F38A9
) },
8928 { PREFIX_TABLE (PREFIX_VEX_0F38AA
) },
8929 { PREFIX_TABLE (PREFIX_VEX_0F38AB
) },
8930 { PREFIX_TABLE (PREFIX_VEX_0F38AC
) },
8931 { PREFIX_TABLE (PREFIX_VEX_0F38AD
) },
8932 { PREFIX_TABLE (PREFIX_VEX_0F38AE
) },
8933 { PREFIX_TABLE (PREFIX_VEX_0F38AF
) },
8941 { PREFIX_TABLE (PREFIX_VEX_0F38B6
) },
8942 { PREFIX_TABLE (PREFIX_VEX_0F38B7
) },
8944 { PREFIX_TABLE (PREFIX_VEX_0F38B8
) },
8945 { PREFIX_TABLE (PREFIX_VEX_0F38B9
) },
8946 { PREFIX_TABLE (PREFIX_VEX_0F38BA
) },
8947 { PREFIX_TABLE (PREFIX_VEX_0F38BB
) },
8948 { PREFIX_TABLE (PREFIX_VEX_0F38BC
) },
8949 { PREFIX_TABLE (PREFIX_VEX_0F38BD
) },
8950 { PREFIX_TABLE (PREFIX_VEX_0F38BE
) },
8951 { PREFIX_TABLE (PREFIX_VEX_0F38BF
) },
8969 { PREFIX_TABLE (PREFIX_VEX_0F38CF
) },
8983 { PREFIX_TABLE (PREFIX_VEX_0F38DB
) },
8984 { PREFIX_TABLE (PREFIX_VEX_0F38DC
) },
8985 { PREFIX_TABLE (PREFIX_VEX_0F38DD
) },
8986 { PREFIX_TABLE (PREFIX_VEX_0F38DE
) },
8987 { PREFIX_TABLE (PREFIX_VEX_0F38DF
) },
9009 { PREFIX_TABLE (PREFIX_VEX_0F38F2
) },
9010 { REG_TABLE (REG_VEX_0F38F3
) },
9012 { PREFIX_TABLE (PREFIX_VEX_0F38F5
) },
9013 { PREFIX_TABLE (PREFIX_VEX_0F38F6
) },
9014 { PREFIX_TABLE (PREFIX_VEX_0F38F7
) },
9028 { PREFIX_TABLE (PREFIX_VEX_0F3A00
) },
9029 { PREFIX_TABLE (PREFIX_VEX_0F3A01
) },
9030 { PREFIX_TABLE (PREFIX_VEX_0F3A02
) },
9032 { PREFIX_TABLE (PREFIX_VEX_0F3A04
) },
9033 { PREFIX_TABLE (PREFIX_VEX_0F3A05
) },
9034 { PREFIX_TABLE (PREFIX_VEX_0F3A06
) },
9037 { PREFIX_TABLE (PREFIX_VEX_0F3A08
) },
9038 { PREFIX_TABLE (PREFIX_VEX_0F3A09
) },
9039 { PREFIX_TABLE (PREFIX_VEX_0F3A0A
) },
9040 { PREFIX_TABLE (PREFIX_VEX_0F3A0B
) },
9041 { PREFIX_TABLE (PREFIX_VEX_0F3A0C
) },
9042 { PREFIX_TABLE (PREFIX_VEX_0F3A0D
) },
9043 { PREFIX_TABLE (PREFIX_VEX_0F3A0E
) },
9044 { PREFIX_TABLE (PREFIX_VEX_0F3A0F
) },
9050 { PREFIX_TABLE (PREFIX_VEX_0F3A14
) },
9051 { PREFIX_TABLE (PREFIX_VEX_0F3A15
) },
9052 { PREFIX_TABLE (PREFIX_VEX_0F3A16
) },
9053 { PREFIX_TABLE (PREFIX_VEX_0F3A17
) },
9055 { PREFIX_TABLE (PREFIX_VEX_0F3A18
) },
9056 { PREFIX_TABLE (PREFIX_VEX_0F3A19
) },
9060 { PREFIX_TABLE (PREFIX_VEX_0F3A1D
) },
9064 { PREFIX_TABLE (PREFIX_VEX_0F3A20
) },
9065 { PREFIX_TABLE (PREFIX_VEX_0F3A21
) },
9066 { PREFIX_TABLE (PREFIX_VEX_0F3A22
) },
9082 { PREFIX_TABLE (PREFIX_VEX_0F3A30
) },
9083 { PREFIX_TABLE (PREFIX_VEX_0F3A31
) },
9084 { PREFIX_TABLE (PREFIX_VEX_0F3A32
) },
9085 { PREFIX_TABLE (PREFIX_VEX_0F3A33
) },
9091 { PREFIX_TABLE (PREFIX_VEX_0F3A38
) },
9092 { PREFIX_TABLE (PREFIX_VEX_0F3A39
) },
9100 { PREFIX_TABLE (PREFIX_VEX_0F3A40
) },
9101 { PREFIX_TABLE (PREFIX_VEX_0F3A41
) },
9102 { PREFIX_TABLE (PREFIX_VEX_0F3A42
) },
9104 { PREFIX_TABLE (PREFIX_VEX_0F3A44
) },
9106 { PREFIX_TABLE (PREFIX_VEX_0F3A46
) },
9109 { PREFIX_TABLE (PREFIX_VEX_0F3A48
) },
9110 { PREFIX_TABLE (PREFIX_VEX_0F3A49
) },
9111 { PREFIX_TABLE (PREFIX_VEX_0F3A4A
) },
9112 { PREFIX_TABLE (PREFIX_VEX_0F3A4B
) },
9113 { PREFIX_TABLE (PREFIX_VEX_0F3A4C
) },
9131 { PREFIX_TABLE (PREFIX_VEX_0F3A5C
) },
9132 { PREFIX_TABLE (PREFIX_VEX_0F3A5D
) },
9133 { PREFIX_TABLE (PREFIX_VEX_0F3A5E
) },
9134 { PREFIX_TABLE (PREFIX_VEX_0F3A5F
) },
9136 { PREFIX_TABLE (PREFIX_VEX_0F3A60
) },
9137 { PREFIX_TABLE (PREFIX_VEX_0F3A61
) },
9138 { PREFIX_TABLE (PREFIX_VEX_0F3A62
) },
9139 { PREFIX_TABLE (PREFIX_VEX_0F3A63
) },
9145 { PREFIX_TABLE (PREFIX_VEX_0F3A68
) },
9146 { PREFIX_TABLE (PREFIX_VEX_0F3A69
) },
9147 { PREFIX_TABLE (PREFIX_VEX_0F3A6A
) },
9148 { PREFIX_TABLE (PREFIX_VEX_0F3A6B
) },
9149 { PREFIX_TABLE (PREFIX_VEX_0F3A6C
) },
9150 { PREFIX_TABLE (PREFIX_VEX_0F3A6D
) },
9151 { PREFIX_TABLE (PREFIX_VEX_0F3A6E
) },
9152 { PREFIX_TABLE (PREFIX_VEX_0F3A6F
) },
9163 { PREFIX_TABLE (PREFIX_VEX_0F3A78
) },
9164 { PREFIX_TABLE (PREFIX_VEX_0F3A79
) },
9165 { PREFIX_TABLE (PREFIX_VEX_0F3A7A
) },
9166 { PREFIX_TABLE (PREFIX_VEX_0F3A7B
) },
9167 { PREFIX_TABLE (PREFIX_VEX_0F3A7C
) },
9168 { PREFIX_TABLE (PREFIX_VEX_0F3A7D
) },
9169 { PREFIX_TABLE (PREFIX_VEX_0F3A7E
) },
9170 { PREFIX_TABLE (PREFIX_VEX_0F3A7F
) },
9259 { PREFIX_TABLE(PREFIX_VEX_0F3ACE
) },
9260 { PREFIX_TABLE(PREFIX_VEX_0F3ACF
) },
9278 { PREFIX_TABLE (PREFIX_VEX_0F3ADF
) },
9298 { PREFIX_TABLE (PREFIX_VEX_0F3AF0
) },
9318 #include "i386-dis-evex.h"
9320 static const struct dis386 vex_len_table
[][2] = {
9321 /* VEX_LEN_0F12_P_0_M_0 */
9323 { "vmovlps", { XM
, Vex128
, EXq
}, 0 },
9326 /* VEX_LEN_0F12_P_0_M_1 */
9328 { "vmovhlps", { XM
, Vex128
, EXq
}, 0 },
9331 /* VEX_LEN_0F12_P_2 */
9333 { "vmovlpd", { XM
, Vex128
, EXq
}, 0 },
9336 /* VEX_LEN_0F13_M_0 */
9338 { "vmovlpX", { EXq
, XM
}, 0 },
9341 /* VEX_LEN_0F16_P_0_M_0 */
9343 { "vmovhps", { XM
, Vex128
, EXq
}, 0 },
9346 /* VEX_LEN_0F16_P_0_M_1 */
9348 { "vmovlhps", { XM
, Vex128
, EXq
}, 0 },
9351 /* VEX_LEN_0F16_P_2 */
9353 { "vmovhpd", { XM
, Vex128
, EXq
}, 0 },
9356 /* VEX_LEN_0F17_M_0 */
9358 { "vmovhpX", { EXq
, XM
}, 0 },
9361 /* VEX_LEN_0F41_P_0 */
9364 { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1
) },
9366 /* VEX_LEN_0F41_P_2 */
9369 { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1
) },
9371 /* VEX_LEN_0F42_P_0 */
9374 { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1
) },
9376 /* VEX_LEN_0F42_P_2 */
9379 { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1
) },
9381 /* VEX_LEN_0F44_P_0 */
9383 { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0
) },
9385 /* VEX_LEN_0F44_P_2 */
9387 { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0
) },
9389 /* VEX_LEN_0F45_P_0 */
9392 { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1
) },
9394 /* VEX_LEN_0F45_P_2 */
9397 { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1
) },
9399 /* VEX_LEN_0F46_P_0 */
9402 { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1
) },
9404 /* VEX_LEN_0F46_P_2 */
9407 { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1
) },
9409 /* VEX_LEN_0F47_P_0 */
9412 { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1
) },
9414 /* VEX_LEN_0F47_P_2 */
9417 { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1
) },
9419 /* VEX_LEN_0F4A_P_0 */
9422 { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1
) },
9424 /* VEX_LEN_0F4A_P_2 */
9427 { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1
) },
9429 /* VEX_LEN_0F4B_P_0 */
9432 { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1
) },
9434 /* VEX_LEN_0F4B_P_2 */
9437 { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1
) },
9440 /* VEX_LEN_0F6E_P_2 */
9442 { "vmovK", { XMScalar
, Edq
}, 0 },
9445 /* VEX_LEN_0F77_P_1 */
9447 { "vzeroupper", { XX
}, 0 },
9448 { "vzeroall", { XX
}, 0 },
9451 /* VEX_LEN_0F7E_P_1 */
9453 { "vmovq", { XMScalar
, EXqScalar
}, 0 },
9456 /* VEX_LEN_0F7E_P_2 */
9458 { "vmovK", { Edq
, XMScalar
}, 0 },
9461 /* VEX_LEN_0F90_P_0 */
9463 { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0
) },
9466 /* VEX_LEN_0F90_P_2 */
9468 { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0
) },
9471 /* VEX_LEN_0F91_P_0 */
9473 { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0
) },
9476 /* VEX_LEN_0F91_P_2 */
9478 { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0
) },
9481 /* VEX_LEN_0F92_P_0 */
9483 { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0
) },
9486 /* VEX_LEN_0F92_P_2 */
9488 { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0
) },
9491 /* VEX_LEN_0F92_P_3 */
9493 { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0
) },
9496 /* VEX_LEN_0F93_P_0 */
9498 { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0
) },
9501 /* VEX_LEN_0F93_P_2 */
9503 { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0
) },
9506 /* VEX_LEN_0F93_P_3 */
9508 { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0
) },
9511 /* VEX_LEN_0F98_P_0 */
9513 { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0
) },
9516 /* VEX_LEN_0F98_P_2 */
9518 { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0
) },
9521 /* VEX_LEN_0F99_P_0 */
9523 { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0
) },
9526 /* VEX_LEN_0F99_P_2 */
9528 { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0
) },
9531 /* VEX_LEN_0FAE_R_2_M_0 */
9533 { "vldmxcsr", { Md
}, 0 },
9536 /* VEX_LEN_0FAE_R_3_M_0 */
9538 { "vstmxcsr", { Md
}, 0 },
9541 /* VEX_LEN_0FC4_P_2 */
9543 { "vpinsrw", { XM
, Vex128
, Edqw
, Ib
}, 0 },
9546 /* VEX_LEN_0FC5_P_2 */
9548 { "vpextrw", { Gdq
, XS
, Ib
}, 0 },
9551 /* VEX_LEN_0FD6_P_2 */
9553 { "vmovq", { EXqScalarS
, XMScalar
}, 0 },
9556 /* VEX_LEN_0FF7_P_2 */
9558 { "vmaskmovdqu", { XM
, XS
}, 0 },
9561 /* VEX_LEN_0F3816_P_2 */
9564 { VEX_W_TABLE (VEX_W_0F3816_P_2
) },
9567 /* VEX_LEN_0F3819_P_2 */
9570 { VEX_W_TABLE (VEX_W_0F3819_P_2
) },
9573 /* VEX_LEN_0F381A_P_2_M_0 */
9576 { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0
) },
9579 /* VEX_LEN_0F3836_P_2 */
9582 { VEX_W_TABLE (VEX_W_0F3836_P_2
) },
9585 /* VEX_LEN_0F3841_P_2 */
9587 { "vphminposuw", { XM
, EXx
}, 0 },
9590 /* VEX_LEN_0F385A_P_2_M_0 */
9593 { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0
) },
9596 /* VEX_LEN_0F38DB_P_2 */
9598 { "vaesimc", { XM
, EXx
}, 0 },
9601 /* VEX_LEN_0F38F2_P_0 */
9603 { "andnS", { Gdq
, VexGdq
, Edq
}, 0 },
9606 /* VEX_LEN_0F38F3_R_1_P_0 */
9608 { "blsrS", { VexGdq
, Edq
}, 0 },
9611 /* VEX_LEN_0F38F3_R_2_P_0 */
9613 { "blsmskS", { VexGdq
, Edq
}, 0 },
9616 /* VEX_LEN_0F38F3_R_3_P_0 */
9618 { "blsiS", { VexGdq
, Edq
}, 0 },
9621 /* VEX_LEN_0F38F5_P_0 */
9623 { "bzhiS", { Gdq
, Edq
, VexGdq
}, 0 },
9626 /* VEX_LEN_0F38F5_P_1 */
9628 { "pextS", { Gdq
, VexGdq
, Edq
}, 0 },
9631 /* VEX_LEN_0F38F5_P_3 */
9633 { "pdepS", { Gdq
, VexGdq
, Edq
}, 0 },
9636 /* VEX_LEN_0F38F6_P_3 */
9638 { "mulxS", { Gdq
, VexGdq
, Edq
}, 0 },
9641 /* VEX_LEN_0F38F7_P_0 */
9643 { "bextrS", { Gdq
, Edq
, VexGdq
}, 0 },
9646 /* VEX_LEN_0F38F7_P_1 */
9648 { "sarxS", { Gdq
, Edq
, VexGdq
}, 0 },
9651 /* VEX_LEN_0F38F7_P_2 */
9653 { "shlxS", { Gdq
, Edq
, VexGdq
}, 0 },
9656 /* VEX_LEN_0F38F7_P_3 */
9658 { "shrxS", { Gdq
, Edq
, VexGdq
}, 0 },
9661 /* VEX_LEN_0F3A00_P_2 */
9664 { VEX_W_TABLE (VEX_W_0F3A00_P_2
) },
9667 /* VEX_LEN_0F3A01_P_2 */
9670 { VEX_W_TABLE (VEX_W_0F3A01_P_2
) },
9673 /* VEX_LEN_0F3A06_P_2 */
9676 { VEX_W_TABLE (VEX_W_0F3A06_P_2
) },
9679 /* VEX_LEN_0F3A14_P_2 */
9681 { "vpextrb", { Edqb
, XM
, Ib
}, 0 },
9684 /* VEX_LEN_0F3A15_P_2 */
9686 { "vpextrw", { Edqw
, XM
, Ib
}, 0 },
9689 /* VEX_LEN_0F3A16_P_2 */
9691 { "vpextrK", { Edq
, XM
, Ib
}, 0 },
9694 /* VEX_LEN_0F3A17_P_2 */
9696 { "vextractps", { Edqd
, XM
, Ib
}, 0 },
9699 /* VEX_LEN_0F3A18_P_2 */
9702 { VEX_W_TABLE (VEX_W_0F3A18_P_2
) },
9705 /* VEX_LEN_0F3A19_P_2 */
9708 { VEX_W_TABLE (VEX_W_0F3A19_P_2
) },
9711 /* VEX_LEN_0F3A20_P_2 */
9713 { "vpinsrb", { XM
, Vex128
, Edqb
, Ib
}, 0 },
9716 /* VEX_LEN_0F3A21_P_2 */
9718 { "vinsertps", { XM
, Vex128
, EXd
, Ib
}, 0 },
9721 /* VEX_LEN_0F3A22_P_2 */
9723 { "vpinsrK", { XM
, Vex128
, Edq
, Ib
}, 0 },
9726 /* VEX_LEN_0F3A30_P_2 */
9728 { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0
) },
9731 /* VEX_LEN_0F3A31_P_2 */
9733 { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0
) },
9736 /* VEX_LEN_0F3A32_P_2 */
9738 { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0
) },
9741 /* VEX_LEN_0F3A33_P_2 */
9743 { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0
) },
9746 /* VEX_LEN_0F3A38_P_2 */
9749 { VEX_W_TABLE (VEX_W_0F3A38_P_2
) },
9752 /* VEX_LEN_0F3A39_P_2 */
9755 { VEX_W_TABLE (VEX_W_0F3A39_P_2
) },
9758 /* VEX_LEN_0F3A41_P_2 */
9760 { "vdppd", { XM
, Vex128
, EXx
, Ib
}, 0 },
9763 /* VEX_LEN_0F3A46_P_2 */
9766 { VEX_W_TABLE (VEX_W_0F3A46_P_2
) },
9769 /* VEX_LEN_0F3A60_P_2 */
9771 { "vpcmpestrm", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, 0 },
9774 /* VEX_LEN_0F3A61_P_2 */
9776 { "vpcmpestri", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, 0 },
9779 /* VEX_LEN_0F3A62_P_2 */
9781 { "vpcmpistrm", { XM
, EXx
, Ib
}, 0 },
9784 /* VEX_LEN_0F3A63_P_2 */
9786 { "vpcmpistri", { XM
, EXx
, Ib
}, 0 },
9789 /* VEX_LEN_0F3A6A_P_2 */
9791 { "vfmaddss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
}, 0 },
9794 /* VEX_LEN_0F3A6B_P_2 */
9796 { "vfmaddsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
}, 0 },
9799 /* VEX_LEN_0F3A6E_P_2 */
9801 { "vfmsubss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
}, 0 },
9804 /* VEX_LEN_0F3A6F_P_2 */
9806 { "vfmsubsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
}, 0 },
9809 /* VEX_LEN_0F3A7A_P_2 */
9811 { "vfnmaddss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
}, 0 },
9814 /* VEX_LEN_0F3A7B_P_2 */
9816 { "vfnmaddsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
}, 0 },
9819 /* VEX_LEN_0F3A7E_P_2 */
9821 { "vfnmsubss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
}, 0 },
9824 /* VEX_LEN_0F3A7F_P_2 */
9826 { "vfnmsubsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
}, 0 },
9829 /* VEX_LEN_0F3ADF_P_2 */
9831 { "vaeskeygenassist", { XM
, EXx
, Ib
}, 0 },
9834 /* VEX_LEN_0F3AF0_P_3 */
9836 { "rorxS", { Gdq
, Edq
, Ib
}, 0 },
9839 /* VEX_LEN_0FXOP_08_CC */
9841 { "vpcomb", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9844 /* VEX_LEN_0FXOP_08_CD */
9846 { "vpcomw", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9849 /* VEX_LEN_0FXOP_08_CE */
9851 { "vpcomd", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9854 /* VEX_LEN_0FXOP_08_CF */
9856 { "vpcomq", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9859 /* VEX_LEN_0FXOP_08_EC */
9861 { "vpcomub", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9864 /* VEX_LEN_0FXOP_08_ED */
9866 { "vpcomuw", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9869 /* VEX_LEN_0FXOP_08_EE */
9871 { "vpcomud", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9874 /* VEX_LEN_0FXOP_08_EF */
9876 { "vpcomuq", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9879 /* VEX_LEN_0FXOP_09_80 */
9881 { "vfrczps", { XM
, EXxmm
}, 0 },
9882 { "vfrczps", { XM
, EXymmq
}, 0 },
9885 /* VEX_LEN_0FXOP_09_81 */
9887 { "vfrczpd", { XM
, EXxmm
}, 0 },
9888 { "vfrczpd", { XM
, EXymmq
}, 0 },
9892 #include "i386-dis-evex-len.h"
9894 static const struct dis386 vex_w_table
[][2] = {
9896 /* VEX_W_0F41_P_0_LEN_1 */
9897 { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1
) },
9898 { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1
) },
9901 /* VEX_W_0F41_P_2_LEN_1 */
9902 { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1
) },
9903 { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1
) }
9906 /* VEX_W_0F42_P_0_LEN_1 */
9907 { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1
) },
9908 { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1
) },
9911 /* VEX_W_0F42_P_2_LEN_1 */
9912 { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1
) },
9913 { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1
) },
9916 /* VEX_W_0F44_P_0_LEN_0 */
9917 { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1
) },
9918 { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1
) },
9921 /* VEX_W_0F44_P_2_LEN_0 */
9922 { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1
) },
9923 { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1
) },
9926 /* VEX_W_0F45_P_0_LEN_1 */
9927 { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1
) },
9928 { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1
) },
9931 /* VEX_W_0F45_P_2_LEN_1 */
9932 { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1
) },
9933 { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1
) },
9936 /* VEX_W_0F46_P_0_LEN_1 */
9937 { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1
) },
9938 { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1
) },
9941 /* VEX_W_0F46_P_2_LEN_1 */
9942 { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1
) },
9943 { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1
) },
9946 /* VEX_W_0F47_P_0_LEN_1 */
9947 { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1
) },
9948 { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1
) },
9951 /* VEX_W_0F47_P_2_LEN_1 */
9952 { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1
) },
9953 { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1
) },
9956 /* VEX_W_0F4A_P_0_LEN_1 */
9957 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1
) },
9958 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1
) },
9961 /* VEX_W_0F4A_P_2_LEN_1 */
9962 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1
) },
9963 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1
) },
9966 /* VEX_W_0F4B_P_0_LEN_1 */
9967 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1
) },
9968 { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1
) },
9971 /* VEX_W_0F4B_P_2_LEN_1 */
9972 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1
) },
9975 /* VEX_W_0F90_P_0_LEN_0 */
9976 { "kmovw", { MaskG
, MaskE
}, 0 },
9977 { "kmovq", { MaskG
, MaskE
}, 0 },
9980 /* VEX_W_0F90_P_2_LEN_0 */
9981 { "kmovb", { MaskG
, MaskBDE
}, 0 },
9982 { "kmovd", { MaskG
, MaskBDE
}, 0 },
9985 /* VEX_W_0F91_P_0_LEN_0 */
9986 { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0
) },
9987 { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0
) },
9990 /* VEX_W_0F91_P_2_LEN_0 */
9991 { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0
) },
9992 { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0
) },
9995 /* VEX_W_0F92_P_0_LEN_0 */
9996 { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0
) },
9999 /* VEX_W_0F92_P_2_LEN_0 */
10000 { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0
) },
10003 /* VEX_W_0F93_P_0_LEN_0 */
10004 { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0
) },
10007 /* VEX_W_0F93_P_2_LEN_0 */
10008 { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0
) },
10011 /* VEX_W_0F98_P_0_LEN_0 */
10012 { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0
) },
10013 { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0
) },
10016 /* VEX_W_0F98_P_2_LEN_0 */
10017 { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0
) },
10018 { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0
) },
10021 /* VEX_W_0F99_P_0_LEN_0 */
10022 { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0
) },
10023 { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0
) },
10026 /* VEX_W_0F99_P_2_LEN_0 */
10027 { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0
) },
10028 { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0
) },
10031 /* VEX_W_0F380C_P_2 */
10032 { "vpermilps", { XM
, Vex
, EXx
}, 0 },
10035 /* VEX_W_0F380D_P_2 */
10036 { "vpermilpd", { XM
, Vex
, EXx
}, 0 },
10039 /* VEX_W_0F380E_P_2 */
10040 { "vtestps", { XM
, EXx
}, 0 },
10043 /* VEX_W_0F380F_P_2 */
10044 { "vtestpd", { XM
, EXx
}, 0 },
10047 /* VEX_W_0F3816_P_2 */
10048 { "vpermps", { XM
, Vex
, EXx
}, 0 },
10051 /* VEX_W_0F3818_P_2 */
10052 { "vbroadcastss", { XM
, EXxmm_md
}, 0 },
10055 /* VEX_W_0F3819_P_2 */
10056 { "vbroadcastsd", { XM
, EXxmm_mq
}, 0 },
10059 /* VEX_W_0F381A_P_2_M_0 */
10060 { "vbroadcastf128", { XM
, Mxmm
}, 0 },
10063 /* VEX_W_0F382C_P_2_M_0 */
10064 { "vmaskmovps", { XM
, Vex
, Mx
}, 0 },
10067 /* VEX_W_0F382D_P_2_M_0 */
10068 { "vmaskmovpd", { XM
, Vex
, Mx
}, 0 },
10071 /* VEX_W_0F382E_P_2_M_0 */
10072 { "vmaskmovps", { Mx
, Vex
, XM
}, 0 },
10075 /* VEX_W_0F382F_P_2_M_0 */
10076 { "vmaskmovpd", { Mx
, Vex
, XM
}, 0 },
10079 /* VEX_W_0F3836_P_2 */
10080 { "vpermd", { XM
, Vex
, EXx
}, 0 },
10083 /* VEX_W_0F3846_P_2 */
10084 { "vpsravd", { XM
, Vex
, EXx
}, 0 },
10087 /* VEX_W_0F3858_P_2 */
10088 { "vpbroadcastd", { XM
, EXxmm_md
}, 0 },
10091 /* VEX_W_0F3859_P_2 */
10092 { "vpbroadcastq", { XM
, EXxmm_mq
}, 0 },
10095 /* VEX_W_0F385A_P_2_M_0 */
10096 { "vbroadcasti128", { XM
, Mxmm
}, 0 },
10099 /* VEX_W_0F3878_P_2 */
10100 { "vpbroadcastb", { XM
, EXxmm_mb
}, 0 },
10103 /* VEX_W_0F3879_P_2 */
10104 { "vpbroadcastw", { XM
, EXxmm_mw
}, 0 },
10107 /* VEX_W_0F38CF_P_2 */
10108 { "vgf2p8mulb", { XM
, Vex
, EXx
}, 0 },
10111 /* VEX_W_0F3A00_P_2 */
10113 { "vpermq", { XM
, EXx
, Ib
}, 0 },
10116 /* VEX_W_0F3A01_P_2 */
10118 { "vpermpd", { XM
, EXx
, Ib
}, 0 },
10121 /* VEX_W_0F3A02_P_2 */
10122 { "vpblendd", { XM
, Vex
, EXx
, Ib
}, 0 },
10125 /* VEX_W_0F3A04_P_2 */
10126 { "vpermilps", { XM
, EXx
, Ib
}, 0 },
10129 /* VEX_W_0F3A05_P_2 */
10130 { "vpermilpd", { XM
, EXx
, Ib
}, 0 },
10133 /* VEX_W_0F3A06_P_2 */
10134 { "vperm2f128", { XM
, Vex256
, EXx
, Ib
}, 0 },
10137 /* VEX_W_0F3A18_P_2 */
10138 { "vinsertf128", { XM
, Vex256
, EXxmm
, Ib
}, 0 },
10141 /* VEX_W_0F3A19_P_2 */
10142 { "vextractf128", { EXxmm
, XM
, Ib
}, 0 },
10145 /* VEX_W_0F3A30_P_2_LEN_0 */
10146 { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0
) },
10147 { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0
) },
10150 /* VEX_W_0F3A31_P_2_LEN_0 */
10151 { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0
) },
10152 { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0
) },
10155 /* VEX_W_0F3A32_P_2_LEN_0 */
10156 { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0
) },
10157 { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0
) },
10160 /* VEX_W_0F3A33_P_2_LEN_0 */
10161 { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0
) },
10162 { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0
) },
10165 /* VEX_W_0F3A38_P_2 */
10166 { "vinserti128", { XM
, Vex256
, EXxmm
, Ib
}, 0 },
10169 /* VEX_W_0F3A39_P_2 */
10170 { "vextracti128", { EXxmm
, XM
, Ib
}, 0 },
10173 /* VEX_W_0F3A46_P_2 */
10174 { "vperm2i128", { XM
, Vex256
, EXx
, Ib
}, 0 },
10177 /* VEX_W_0F3A48_P_2 */
10178 { "vpermil2ps", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
10179 { "vpermil2ps", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
10182 /* VEX_W_0F3A49_P_2 */
10183 { "vpermil2pd", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
10184 { "vpermil2pd", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
10187 /* VEX_W_0F3A4A_P_2 */
10188 { "vblendvps", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10191 /* VEX_W_0F3A4B_P_2 */
10192 { "vblendvpd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10195 /* VEX_W_0F3A4C_P_2 */
10196 { "vpblendvb", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10199 /* VEX_W_0F3ACE_P_2 */
10201 { "vgf2p8affineqb", { XM
, Vex
, EXx
, Ib
}, 0 },
10204 /* VEX_W_0F3ACF_P_2 */
10206 { "vgf2p8affineinvqb", { XM
, Vex
, EXx
, Ib
}, 0 },
10209 #include "i386-dis-evex-w.h"
10212 static const struct dis386 mod_table
[][2] = {
10215 { "leaS", { Gv
, M
}, 0 },
10220 { RM_TABLE (RM_C6_REG_7
) },
10225 { RM_TABLE (RM_C7_REG_7
) },
10229 { "Jcall^", { indirEp
}, 0 },
10233 { "Jjmp^", { indirEp
}, 0 },
10236 /* MOD_0F01_REG_0 */
10237 { X86_64_TABLE (X86_64_0F01_REG_0
) },
10238 { RM_TABLE (RM_0F01_REG_0
) },
10241 /* MOD_0F01_REG_1 */
10242 { X86_64_TABLE (X86_64_0F01_REG_1
) },
10243 { RM_TABLE (RM_0F01_REG_1
) },
10246 /* MOD_0F01_REG_2 */
10247 { X86_64_TABLE (X86_64_0F01_REG_2
) },
10248 { RM_TABLE (RM_0F01_REG_2
) },
10251 /* MOD_0F01_REG_3 */
10252 { X86_64_TABLE (X86_64_0F01_REG_3
) },
10253 { RM_TABLE (RM_0F01_REG_3
) },
10256 /* MOD_0F01_REG_5 */
10257 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0
) },
10258 { RM_TABLE (RM_0F01_REG_5_MOD_3
) },
10261 /* MOD_0F01_REG_7 */
10262 { "invlpg", { Mb
}, 0 },
10263 { RM_TABLE (RM_0F01_REG_7_MOD_3
) },
10266 /* MOD_0F12_PREFIX_0 */
10267 { "movlps", { XM
, EXq
}, PREFIX_OPCODE
},
10268 { "movhlps", { XM
, EXq
}, PREFIX_OPCODE
},
10272 { "movlpX", { EXq
, XM
}, PREFIX_OPCODE
},
10275 /* MOD_0F16_PREFIX_0 */
10276 { "movhps", { XM
, EXq
}, 0 },
10277 { "movlhps", { XM
, EXq
}, 0 },
10281 { "movhpX", { EXq
, XM
}, PREFIX_OPCODE
},
10284 /* MOD_0F18_REG_0 */
10285 { "prefetchnta", { Mb
}, 0 },
10288 /* MOD_0F18_REG_1 */
10289 { "prefetcht0", { Mb
}, 0 },
10292 /* MOD_0F18_REG_2 */
10293 { "prefetcht1", { Mb
}, 0 },
10296 /* MOD_0F18_REG_3 */
10297 { "prefetcht2", { Mb
}, 0 },
10300 /* MOD_0F18_REG_4 */
10301 { "nop/reserved", { Mb
}, 0 },
10304 /* MOD_0F18_REG_5 */
10305 { "nop/reserved", { Mb
}, 0 },
10308 /* MOD_0F18_REG_6 */
10309 { "nop/reserved", { Mb
}, 0 },
10312 /* MOD_0F18_REG_7 */
10313 { "nop/reserved", { Mb
}, 0 },
10316 /* MOD_0F1A_PREFIX_0 */
10317 { "bndldx", { Gbnd
, Mv_bnd
}, 0 },
10318 { "nopQ", { Ev
}, 0 },
10321 /* MOD_0F1B_PREFIX_0 */
10322 { "bndstx", { Mv_bnd
, Gbnd
}, 0 },
10323 { "nopQ", { Ev
}, 0 },
10326 /* MOD_0F1B_PREFIX_1 */
10327 { "bndmk", { Gbnd
, Mv_bnd
}, 0 },
10328 { "nopQ", { Ev
}, 0 },
10331 /* MOD_0F1C_PREFIX_0 */
10332 { REG_TABLE (REG_0F1C_P_0_MOD_0
) },
10333 { "nopQ", { Ev
}, 0 },
10336 /* MOD_0F1E_PREFIX_1 */
10337 { "nopQ", { Ev
}, 0 },
10338 { REG_TABLE (REG_0F1E_P_1_MOD_3
) },
10343 { "movL", { Rd
, Td
}, 0 },
10348 { "movL", { Td
, Rd
}, 0 },
10351 /* MOD_0F2B_PREFIX_0 */
10352 {"movntps", { Mx
, XM
}, PREFIX_OPCODE
},
10355 /* MOD_0F2B_PREFIX_1 */
10356 {"movntss", { Md
, XM
}, PREFIX_OPCODE
},
10359 /* MOD_0F2B_PREFIX_2 */
10360 {"movntpd", { Mx
, XM
}, PREFIX_OPCODE
},
10363 /* MOD_0F2B_PREFIX_3 */
10364 {"movntsd", { Mq
, XM
}, PREFIX_OPCODE
},
10369 { "movmskpX", { Gdq
, XS
}, PREFIX_OPCODE
},
10372 /* MOD_0F71_REG_2 */
10374 { "psrlw", { MS
, Ib
}, 0 },
10377 /* MOD_0F71_REG_4 */
10379 { "psraw", { MS
, Ib
}, 0 },
10382 /* MOD_0F71_REG_6 */
10384 { "psllw", { MS
, Ib
}, 0 },
10387 /* MOD_0F72_REG_2 */
10389 { "psrld", { MS
, Ib
}, 0 },
10392 /* MOD_0F72_REG_4 */
10394 { "psrad", { MS
, Ib
}, 0 },
10397 /* MOD_0F72_REG_6 */
10399 { "pslld", { MS
, Ib
}, 0 },
10402 /* MOD_0F73_REG_2 */
10404 { "psrlq", { MS
, Ib
}, 0 },
10407 /* MOD_0F73_REG_3 */
10409 { PREFIX_TABLE (PREFIX_0F73_REG_3
) },
10412 /* MOD_0F73_REG_6 */
10414 { "psllq", { MS
, Ib
}, 0 },
10417 /* MOD_0F73_REG_7 */
10419 { PREFIX_TABLE (PREFIX_0F73_REG_7
) },
10422 /* MOD_0FAE_REG_0 */
10423 { "fxsave", { FXSAVE
}, 0 },
10424 { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3
) },
10427 /* MOD_0FAE_REG_1 */
10428 { "fxrstor", { FXSAVE
}, 0 },
10429 { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3
) },
10432 /* MOD_0FAE_REG_2 */
10433 { "ldmxcsr", { Md
}, 0 },
10434 { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3
) },
10437 /* MOD_0FAE_REG_3 */
10438 { "stmxcsr", { Md
}, 0 },
10439 { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3
) },
10442 /* MOD_0FAE_REG_4 */
10443 { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0
) },
10444 { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3
) },
10447 /* MOD_0FAE_REG_5 */
10448 { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_0
) },
10449 { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3
) },
10452 /* MOD_0FAE_REG_6 */
10453 { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0
) },
10454 { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3
) },
10457 /* MOD_0FAE_REG_7 */
10458 { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0
) },
10459 { RM_TABLE (RM_0FAE_REG_7_MOD_3
) },
10463 { "lssS", { Gv
, Mp
}, 0 },
10467 { "lfsS", { Gv
, Mp
}, 0 },
10471 { "lgsS", { Gv
, Mp
}, 0 },
10475 { PREFIX_TABLE (PREFIX_0FC3_MOD_0
) },
10478 /* MOD_0FC7_REG_3 */
10479 { "xrstors", { FXSAVE
}, 0 },
10482 /* MOD_0FC7_REG_4 */
10483 { "xsavec", { FXSAVE
}, 0 },
10486 /* MOD_0FC7_REG_5 */
10487 { "xsaves", { FXSAVE
}, 0 },
10490 /* MOD_0FC7_REG_6 */
10491 { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0
) },
10492 { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3
) }
10495 /* MOD_0FC7_REG_7 */
10496 { "vmptrst", { Mq
}, 0 },
10497 { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3
) }
10502 { "pmovmskb", { Gdq
, MS
}, 0 },
10505 /* MOD_0FE7_PREFIX_2 */
10506 { "movntdq", { Mx
, XM
}, 0 },
10509 /* MOD_0FF0_PREFIX_3 */
10510 { "lddqu", { XM
, M
}, 0 },
10513 /* MOD_0F382A_PREFIX_2 */
10514 { "movntdqa", { XM
, Mx
}, 0 },
10517 /* MOD_0F38F5_PREFIX_2 */
10518 { "wrussK", { M
, Gdq
}, PREFIX_OPCODE
},
10521 /* MOD_0F38F6_PREFIX_0 */
10522 { "wrssK", { M
, Gdq
}, PREFIX_OPCODE
},
10525 /* MOD_0F38F8_PREFIX_1 */
10526 { "enqcmds", { Gva
, M
}, PREFIX_OPCODE
},
10529 /* MOD_0F38F8_PREFIX_2 */
10530 { "movdir64b", { Gva
, M
}, PREFIX_OPCODE
},
10533 /* MOD_0F38F8_PREFIX_3 */
10534 { "enqcmd", { Gva
, M
}, PREFIX_OPCODE
},
10537 /* MOD_0F38F9_PREFIX_0 */
10538 { "movdiri", { Ev
, Gv
}, PREFIX_OPCODE
},
10542 { "bound{S|}", { Gv
, Ma
}, 0 },
10543 { EVEX_TABLE (EVEX_0F
) },
10547 { "lesS", { Gv
, Mp
}, 0 },
10548 { VEX_C4_TABLE (VEX_0F
) },
10552 { "ldsS", { Gv
, Mp
}, 0 },
10553 { VEX_C5_TABLE (VEX_0F
) },
10556 /* MOD_VEX_0F12_PREFIX_0 */
10557 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0
) },
10558 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1
) },
10562 { VEX_LEN_TABLE (VEX_LEN_0F13_M_0
) },
10565 /* MOD_VEX_0F16_PREFIX_0 */
10566 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0
) },
10567 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1
) },
10571 { VEX_LEN_TABLE (VEX_LEN_0F17_M_0
) },
10575 { "vmovntpX", { Mx
, XM
}, 0 },
10578 /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
10580 { "kandw", { MaskG
, MaskVex
, MaskR
}, 0 },
10583 /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
10585 { "kandq", { MaskG
, MaskVex
, MaskR
}, 0 },
10588 /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
10590 { "kandb", { MaskG
, MaskVex
, MaskR
}, 0 },
10593 /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
10595 { "kandd", { MaskG
, MaskVex
, MaskR
}, 0 },
10598 /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
10600 { "kandnw", { MaskG
, MaskVex
, MaskR
}, 0 },
10603 /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
10605 { "kandnq", { MaskG
, MaskVex
, MaskR
}, 0 },
10608 /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
10610 { "kandnb", { MaskG
, MaskVex
, MaskR
}, 0 },
10613 /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
10615 { "kandnd", { MaskG
, MaskVex
, MaskR
}, 0 },
10618 /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
10620 { "knotw", { MaskG
, MaskR
}, 0 },
10623 /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
10625 { "knotq", { MaskG
, MaskR
}, 0 },
10628 /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
10630 { "knotb", { MaskG
, MaskR
}, 0 },
10633 /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
10635 { "knotd", { MaskG
, MaskR
}, 0 },
10638 /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
10640 { "korw", { MaskG
, MaskVex
, MaskR
}, 0 },
10643 /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
10645 { "korq", { MaskG
, MaskVex
, MaskR
}, 0 },
10648 /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
10650 { "korb", { MaskG
, MaskVex
, MaskR
}, 0 },
10653 /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
10655 { "kord", { MaskG
, MaskVex
, MaskR
}, 0 },
10658 /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
10660 { "kxnorw", { MaskG
, MaskVex
, MaskR
}, 0 },
10663 /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
10665 { "kxnorq", { MaskG
, MaskVex
, MaskR
}, 0 },
10668 /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
10670 { "kxnorb", { MaskG
, MaskVex
, MaskR
}, 0 },
10673 /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
10675 { "kxnord", { MaskG
, MaskVex
, MaskR
}, 0 },
10678 /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
10680 { "kxorw", { MaskG
, MaskVex
, MaskR
}, 0 },
10683 /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
10685 { "kxorq", { MaskG
, MaskVex
, MaskR
}, 0 },
10688 /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
10690 { "kxorb", { MaskG
, MaskVex
, MaskR
}, 0 },
10693 /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
10695 { "kxord", { MaskG
, MaskVex
, MaskR
}, 0 },
10698 /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
10700 { "kaddw", { MaskG
, MaskVex
, MaskR
}, 0 },
10703 /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
10705 { "kaddq", { MaskG
, MaskVex
, MaskR
}, 0 },
10708 /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
10710 { "kaddb", { MaskG
, MaskVex
, MaskR
}, 0 },
10713 /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
10715 { "kaddd", { MaskG
, MaskVex
, MaskR
}, 0 },
10718 /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
10720 { "kunpckwd", { MaskG
, MaskVex
, MaskR
}, 0 },
10723 /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
10725 { "kunpckdq", { MaskG
, MaskVex
, MaskR
}, 0 },
10728 /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
10730 { "kunpckbw", { MaskG
, MaskVex
, MaskR
}, 0 },
10735 { "vmovmskpX", { Gdq
, XS
}, 0 },
10738 /* MOD_VEX_0F71_REG_2 */
10740 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2
) },
10743 /* MOD_VEX_0F71_REG_4 */
10745 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4
) },
10748 /* MOD_VEX_0F71_REG_6 */
10750 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6
) },
10753 /* MOD_VEX_0F72_REG_2 */
10755 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2
) },
10758 /* MOD_VEX_0F72_REG_4 */
10760 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4
) },
10763 /* MOD_VEX_0F72_REG_6 */
10765 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6
) },
10768 /* MOD_VEX_0F73_REG_2 */
10770 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2
) },
10773 /* MOD_VEX_0F73_REG_3 */
10775 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3
) },
10778 /* MOD_VEX_0F73_REG_6 */
10780 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6
) },
10783 /* MOD_VEX_0F73_REG_7 */
10785 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7
) },
10788 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10789 { "kmovw", { Ew
, MaskG
}, 0 },
10793 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10794 { "kmovq", { Eq
, MaskG
}, 0 },
10798 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10799 { "kmovb", { Eb
, MaskG
}, 0 },
10803 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10804 { "kmovd", { Ed
, MaskG
}, 0 },
10808 /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
10810 { "kmovw", { MaskG
, Rdq
}, 0 },
10813 /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
10815 { "kmovb", { MaskG
, Rdq
}, 0 },
10818 /* MOD_VEX_0F92_P_3_LEN_0 */
10820 { "kmovK", { MaskG
, Rdq
}, 0 },
10823 /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
10825 { "kmovw", { Gdq
, MaskR
}, 0 },
10828 /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
10830 { "kmovb", { Gdq
, MaskR
}, 0 },
10833 /* MOD_VEX_0F93_P_3_LEN_0 */
10835 { "kmovK", { Gdq
, MaskR
}, 0 },
10838 /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
10840 { "kortestw", { MaskG
, MaskR
}, 0 },
10843 /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
10845 { "kortestq", { MaskG
, MaskR
}, 0 },
10848 /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
10850 { "kortestb", { MaskG
, MaskR
}, 0 },
10853 /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
10855 { "kortestd", { MaskG
, MaskR
}, 0 },
10858 /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
10860 { "ktestw", { MaskG
, MaskR
}, 0 },
10863 /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
10865 { "ktestq", { MaskG
, MaskR
}, 0 },
10868 /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
10870 { "ktestb", { MaskG
, MaskR
}, 0 },
10873 /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
10875 { "ktestd", { MaskG
, MaskR
}, 0 },
10878 /* MOD_VEX_0FAE_REG_2 */
10879 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0
) },
10882 /* MOD_VEX_0FAE_REG_3 */
10883 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0
) },
10886 /* MOD_VEX_0FD7_PREFIX_2 */
10888 { "vpmovmskb", { Gdq
, XS
}, 0 },
10891 /* MOD_VEX_0FE7_PREFIX_2 */
10892 { "vmovntdq", { Mx
, XM
}, 0 },
10895 /* MOD_VEX_0FF0_PREFIX_3 */
10896 { "vlddqu", { XM
, M
}, 0 },
10899 /* MOD_VEX_0F381A_PREFIX_2 */
10900 { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0
) },
10903 /* MOD_VEX_0F382A_PREFIX_2 */
10904 { "vmovntdqa", { XM
, Mx
}, 0 },
10907 /* MOD_VEX_0F382C_PREFIX_2 */
10908 { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0
) },
10911 /* MOD_VEX_0F382D_PREFIX_2 */
10912 { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0
) },
10915 /* MOD_VEX_0F382E_PREFIX_2 */
10916 { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0
) },
10919 /* MOD_VEX_0F382F_PREFIX_2 */
10920 { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0
) },
10923 /* MOD_VEX_0F385A_PREFIX_2 */
10924 { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0
) },
10927 /* MOD_VEX_0F388C_PREFIX_2 */
10928 { "vpmaskmov%LW", { XM
, Vex
, Mx
}, 0 },
10931 /* MOD_VEX_0F388E_PREFIX_2 */
10932 { "vpmaskmov%LW", { Mx
, Vex
, XM
}, 0 },
10935 /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
10937 { "kshiftrb", { MaskG
, MaskR
, Ib
}, 0 },
10940 /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
10942 { "kshiftrw", { MaskG
, MaskR
, Ib
}, 0 },
10945 /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
10947 { "kshiftrd", { MaskG
, MaskR
, Ib
}, 0 },
10950 /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
10952 { "kshiftrq", { MaskG
, MaskR
, Ib
}, 0 },
10955 /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
10957 { "kshiftlb", { MaskG
, MaskR
, Ib
}, 0 },
10960 /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
10962 { "kshiftlw", { MaskG
, MaskR
, Ib
}, 0 },
10965 /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
10967 { "kshiftld", { MaskG
, MaskR
, Ib
}, 0 },
10970 /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
10972 { "kshiftlq", { MaskG
, MaskR
, Ib
}, 0 },
10975 #include "i386-dis-evex-mod.h"
10978 static const struct dis386 rm_table
[][8] = {
10981 { "xabort", { Skip_MODRM
, Ib
}, 0 },
10985 { "xbeginT", { Skip_MODRM
, Jdqw
}, 0 },
10988 /* RM_0F01_REG_0 */
10989 { "enclv", { Skip_MODRM
}, 0 },
10990 { "vmcall", { Skip_MODRM
}, 0 },
10991 { "vmlaunch", { Skip_MODRM
}, 0 },
10992 { "vmresume", { Skip_MODRM
}, 0 },
10993 { "vmxoff", { Skip_MODRM
}, 0 },
10994 { "pconfig", { Skip_MODRM
}, 0 },
10997 /* RM_0F01_REG_1 */
10998 { "monitor", { { OP_Monitor
, 0 } }, 0 },
10999 { "mwait", { { OP_Mwait
, 0 } }, 0 },
11000 { "clac", { Skip_MODRM
}, 0 },
11001 { "stac", { Skip_MODRM
}, 0 },
11005 { "encls", { Skip_MODRM
}, 0 },
11008 /* RM_0F01_REG_2 */
11009 { "xgetbv", { Skip_MODRM
}, 0 },
11010 { "xsetbv", { Skip_MODRM
}, 0 },
11013 { "vmfunc", { Skip_MODRM
}, 0 },
11014 { "xend", { Skip_MODRM
}, 0 },
11015 { "xtest", { Skip_MODRM
}, 0 },
11016 { "enclu", { Skip_MODRM
}, 0 },
11019 /* RM_0F01_REG_3 */
11020 { "vmrun", { Skip_MODRM
}, 0 },
11021 { "vmmcall", { Skip_MODRM
}, 0 },
11022 { "vmload", { Skip_MODRM
}, 0 },
11023 { "vmsave", { Skip_MODRM
}, 0 },
11024 { "stgi", { Skip_MODRM
}, 0 },
11025 { "clgi", { Skip_MODRM
}, 0 },
11026 { "skinit", { Skip_MODRM
}, 0 },
11027 { "invlpga", { Skip_MODRM
}, 0 },
11030 /* RM_0F01_REG_5_MOD_3 */
11031 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0
) },
11033 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2
) },
11037 { "rdpkru", { Skip_MODRM
}, 0 },
11038 { "wrpkru", { Skip_MODRM
}, 0 },
11041 /* RM_0F01_REG_7_MOD_3 */
11042 { "swapgs", { Skip_MODRM
}, 0 },
11043 { "rdtscp", { Skip_MODRM
}, 0 },
11044 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2
) },
11045 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_3
) },
11046 { "clzero", { Skip_MODRM
}, 0 },
11047 { "rdpru", { Skip_MODRM
}, 0 },
11050 /* RM_0F1E_P_1_MOD_3_REG_7 */
11051 { "nopQ", { Ev
}, 0 },
11052 { "nopQ", { Ev
}, 0 },
11053 { "endbr64", { Skip_MODRM
}, PREFIX_OPCODE
},
11054 { "endbr32", { Skip_MODRM
}, PREFIX_OPCODE
},
11055 { "nopQ", { Ev
}, 0 },
11056 { "nopQ", { Ev
}, 0 },
11057 { "nopQ", { Ev
}, 0 },
11058 { "nopQ", { Ev
}, 0 },
11061 /* RM_0FAE_REG_6_MOD_3 */
11062 { "mfence", { Skip_MODRM
}, 0 },
11065 /* RM_0FAE_REG_7_MOD_3 */
11066 { "sfence", { Skip_MODRM
}, 0 },
11071 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
11073 /* We use the high bit to indicate different name for the same
11075 #define REP_PREFIX (0xf3 | 0x100)
11076 #define XACQUIRE_PREFIX (0xf2 | 0x200)
11077 #define XRELEASE_PREFIX (0xf3 | 0x400)
11078 #define BND_PREFIX (0xf2 | 0x400)
11079 #define NOTRACK_PREFIX (0x3e | 0x100)
11081 /* Remember if the current op is a jump instruction. */
11082 static bfd_boolean op_is_jump
= FALSE
;
11087 int newrex
, i
, length
;
11093 last_lock_prefix
= -1;
11094 last_repz_prefix
= -1;
11095 last_repnz_prefix
= -1;
11096 last_data_prefix
= -1;
11097 last_addr_prefix
= -1;
11098 last_rex_prefix
= -1;
11099 last_seg_prefix
= -1;
11101 active_seg_prefix
= 0;
11102 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
11103 all_prefixes
[i
] = 0;
11106 /* The maximum instruction length is 15bytes. */
11107 while (length
< MAX_CODE_LENGTH
- 1)
11109 FETCH_DATA (the_info
, codep
+ 1);
11113 /* REX prefixes family. */
11130 if (address_mode
== mode_64bit
)
11134 last_rex_prefix
= i
;
11137 prefixes
|= PREFIX_REPZ
;
11138 last_repz_prefix
= i
;
11141 prefixes
|= PREFIX_REPNZ
;
11142 last_repnz_prefix
= i
;
11145 prefixes
|= PREFIX_LOCK
;
11146 last_lock_prefix
= i
;
11149 prefixes
|= PREFIX_CS
;
11150 last_seg_prefix
= i
;
11151 active_seg_prefix
= PREFIX_CS
;
11154 prefixes
|= PREFIX_SS
;
11155 last_seg_prefix
= i
;
11156 active_seg_prefix
= PREFIX_SS
;
11159 prefixes
|= PREFIX_DS
;
11160 last_seg_prefix
= i
;
11161 active_seg_prefix
= PREFIX_DS
;
11164 prefixes
|= PREFIX_ES
;
11165 last_seg_prefix
= i
;
11166 active_seg_prefix
= PREFIX_ES
;
11169 prefixes
|= PREFIX_FS
;
11170 last_seg_prefix
= i
;
11171 active_seg_prefix
= PREFIX_FS
;
11174 prefixes
|= PREFIX_GS
;
11175 last_seg_prefix
= i
;
11176 active_seg_prefix
= PREFIX_GS
;
11179 prefixes
|= PREFIX_DATA
;
11180 last_data_prefix
= i
;
11183 prefixes
|= PREFIX_ADDR
;
11184 last_addr_prefix
= i
;
11187 /* fwait is really an instruction. If there are prefixes
11188 before the fwait, they belong to the fwait, *not* to the
11189 following instruction. */
11191 if (prefixes
|| rex
)
11193 prefixes
|= PREFIX_FWAIT
;
11195 /* This ensures that the previous REX prefixes are noticed
11196 as unused prefixes, as in the return case below. */
11200 prefixes
= PREFIX_FWAIT
;
11205 /* Rex is ignored when followed by another prefix. */
11211 if (*codep
!= FWAIT_OPCODE
)
11212 all_prefixes
[i
++] = *codep
;
11220 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
11223 static const char *
11224 prefix_name (int pref
, int sizeflag
)
11226 static const char *rexes
[16] =
11229 "rex.B", /* 0x41 */
11230 "rex.X", /* 0x42 */
11231 "rex.XB", /* 0x43 */
11232 "rex.R", /* 0x44 */
11233 "rex.RB", /* 0x45 */
11234 "rex.RX", /* 0x46 */
11235 "rex.RXB", /* 0x47 */
11236 "rex.W", /* 0x48 */
11237 "rex.WB", /* 0x49 */
11238 "rex.WX", /* 0x4a */
11239 "rex.WXB", /* 0x4b */
11240 "rex.WR", /* 0x4c */
11241 "rex.WRB", /* 0x4d */
11242 "rex.WRX", /* 0x4e */
11243 "rex.WRXB", /* 0x4f */
11248 /* REX prefixes family. */
11265 return rexes
[pref
- 0x40];
11285 return (sizeflag
& DFLAG
) ? "data16" : "data32";
11287 if (address_mode
== mode_64bit
)
11288 return (sizeflag
& AFLAG
) ? "addr32" : "addr64";
11290 return (sizeflag
& AFLAG
) ? "addr16" : "addr32";
11295 case XACQUIRE_PREFIX
:
11297 case XRELEASE_PREFIX
:
11301 case NOTRACK_PREFIX
:
11308 static char op_out
[MAX_OPERANDS
][100];
11309 static int op_ad
, op_index
[MAX_OPERANDS
];
11310 static int two_source_ops
;
11311 static bfd_vma op_address
[MAX_OPERANDS
];
11312 static bfd_vma op_riprel
[MAX_OPERANDS
];
11313 static bfd_vma start_pc
;
11316 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
11317 * (see topic "Redundant prefixes" in the "Differences from 8086"
11318 * section of the "Virtual 8086 Mode" chapter.)
11319 * 'pc' should be the address of this instruction, it will
11320 * be used to print the target address if this is a relative jump or call
11321 * The function returns the length of this instruction in bytes.
11324 static char intel_syntax
;
11325 static char intel_mnemonic
= !SYSV386_COMPAT
;
11326 static char open_char
;
11327 static char close_char
;
11328 static char separator_char
;
11329 static char scale_char
;
11337 static enum x86_64_isa isa64
;
11339 /* Here for backwards compatibility. When gdb stops using
11340 print_insn_i386_att and print_insn_i386_intel these functions can
11341 disappear, and print_insn_i386 be merged into print_insn. */
11343 print_insn_i386_att (bfd_vma pc
, disassemble_info
*info
)
11347 return print_insn (pc
, info
);
11351 print_insn_i386_intel (bfd_vma pc
, disassemble_info
*info
)
11355 return print_insn (pc
, info
);
11359 print_insn_i386 (bfd_vma pc
, disassemble_info
*info
)
11363 return print_insn (pc
, info
);
11367 print_i386_disassembler_options (FILE *stream
)
11369 fprintf (stream
, _("\n\
11370 The following i386/x86-64 specific disassembler options are supported for use\n\
11371 with the -M switch (multiple options should be separated by commas):\n"));
11373 fprintf (stream
, _(" x86-64 Disassemble in 64bit mode\n"));
11374 fprintf (stream
, _(" i386 Disassemble in 32bit mode\n"));
11375 fprintf (stream
, _(" i8086 Disassemble in 16bit mode\n"));
11376 fprintf (stream
, _(" att Display instruction in AT&T syntax\n"));
11377 fprintf (stream
, _(" intel Display instruction in Intel syntax\n"));
11378 fprintf (stream
, _(" att-mnemonic\n"
11379 " Display instruction in AT&T mnemonic\n"));
11380 fprintf (stream
, _(" intel-mnemonic\n"
11381 " Display instruction in Intel mnemonic\n"));
11382 fprintf (stream
, _(" addr64 Assume 64bit address size\n"));
11383 fprintf (stream
, _(" addr32 Assume 32bit address size\n"));
11384 fprintf (stream
, _(" addr16 Assume 16bit address size\n"));
11385 fprintf (stream
, _(" data32 Assume 32bit data size\n"));
11386 fprintf (stream
, _(" data16 Assume 16bit data size\n"));
11387 fprintf (stream
, _(" suffix Always display instruction suffix in AT&T syntax\n"));
11388 fprintf (stream
, _(" amd64 Display instruction in AMD64 ISA\n"));
11389 fprintf (stream
, _(" intel64 Display instruction in Intel64 ISA\n"));
11393 static const struct dis386 bad_opcode
= { "(bad)", { XX
}, 0 };
11395 /* Get a pointer to struct dis386 with a valid name. */
11397 static const struct dis386
*
11398 get_valid_dis386 (const struct dis386
*dp
, disassemble_info
*info
)
11400 int vindex
, vex_table_index
;
11402 if (dp
->name
!= NULL
)
11405 switch (dp
->op
[0].bytemode
)
11407 case USE_REG_TABLE
:
11408 dp
= ®_table
[dp
->op
[1].bytemode
][modrm
.reg
];
11411 case USE_MOD_TABLE
:
11412 vindex
= modrm
.mod
== 0x3 ? 1 : 0;
11413 dp
= &mod_table
[dp
->op
[1].bytemode
][vindex
];
11417 dp
= &rm_table
[dp
->op
[1].bytemode
][modrm
.rm
];
11420 case USE_PREFIX_TABLE
:
11423 /* The prefix in VEX is implicit. */
11424 switch (vex
.prefix
)
11429 case REPE_PREFIX_OPCODE
:
11432 case DATA_PREFIX_OPCODE
:
11435 case REPNE_PREFIX_OPCODE
:
11445 int last_prefix
= -1;
11448 /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
11449 When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
11451 if ((prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0)
11453 if (last_repz_prefix
> last_repnz_prefix
)
11456 prefix
= PREFIX_REPZ
;
11457 last_prefix
= last_repz_prefix
;
11462 prefix
= PREFIX_REPNZ
;
11463 last_prefix
= last_repnz_prefix
;
11466 /* Check if prefix should be ignored. */
11467 if ((((prefix_table
[dp
->op
[1].bytemode
][vindex
].prefix_requirement
11468 & PREFIX_IGNORED
) >> PREFIX_IGNORED_SHIFT
)
11473 if (vindex
== 0 && (prefixes
& PREFIX_DATA
) != 0)
11476 prefix
= PREFIX_DATA
;
11477 last_prefix
= last_data_prefix
;
11482 used_prefixes
|= prefix
;
11483 all_prefixes
[last_prefix
] = 0;
11486 dp
= &prefix_table
[dp
->op
[1].bytemode
][vindex
];
11489 case USE_X86_64_TABLE
:
11490 vindex
= address_mode
== mode_64bit
? 1 : 0;
11491 dp
= &x86_64_table
[dp
->op
[1].bytemode
][vindex
];
11494 case USE_3BYTE_TABLE
:
11495 FETCH_DATA (info
, codep
+ 2);
11497 dp
= &three_byte_table
[dp
->op
[1].bytemode
][vindex
];
11499 modrm
.mod
= (*codep
>> 6) & 3;
11500 modrm
.reg
= (*codep
>> 3) & 7;
11501 modrm
.rm
= *codep
& 7;
11504 case USE_VEX_LEN_TABLE
:
11508 switch (vex
.length
)
11521 dp
= &vex_len_table
[dp
->op
[1].bytemode
][vindex
];
11524 case USE_EVEX_LEN_TABLE
:
11528 switch (vex
.length
)
11544 dp
= &evex_len_table
[dp
->op
[1].bytemode
][vindex
];
11547 case USE_XOP_8F_TABLE
:
11548 FETCH_DATA (info
, codep
+ 3);
11549 /* All bits in the REX prefix are ignored. */
11551 rex
= ~(*codep
>> 5) & 0x7;
11553 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
11554 switch ((*codep
& 0x1f))
11560 vex_table_index
= XOP_08
;
11563 vex_table_index
= XOP_09
;
11566 vex_table_index
= XOP_0A
;
11570 vex
.w
= *codep
& 0x80;
11571 if (vex
.w
&& address_mode
== mode_64bit
)
11574 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11575 if (address_mode
!= mode_64bit
)
11577 /* In 16/32-bit mode REX_B is silently ignored. */
11581 vex
.length
= (*codep
& 0x4) ? 256 : 128;
11582 switch ((*codep
& 0x3))
11587 vex
.prefix
= DATA_PREFIX_OPCODE
;
11590 vex
.prefix
= REPE_PREFIX_OPCODE
;
11593 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11600 dp
= &xop_table
[vex_table_index
][vindex
];
11603 FETCH_DATA (info
, codep
+ 1);
11604 modrm
.mod
= (*codep
>> 6) & 3;
11605 modrm
.reg
= (*codep
>> 3) & 7;
11606 modrm
.rm
= *codep
& 7;
11609 case USE_VEX_C4_TABLE
:
11611 FETCH_DATA (info
, codep
+ 3);
11612 /* All bits in the REX prefix are ignored. */
11614 rex
= ~(*codep
>> 5) & 0x7;
11615 switch ((*codep
& 0x1f))
11621 vex_table_index
= VEX_0F
;
11624 vex_table_index
= VEX_0F38
;
11627 vex_table_index
= VEX_0F3A
;
11631 vex
.w
= *codep
& 0x80;
11632 if (address_mode
== mode_64bit
)
11639 /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
11640 is ignored, other REX bits are 0 and the highest bit in
11641 VEX.vvvv is also ignored (but we mustn't clear it here). */
11644 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11645 vex
.length
= (*codep
& 0x4) ? 256 : 128;
11646 switch ((*codep
& 0x3))
11651 vex
.prefix
= DATA_PREFIX_OPCODE
;
11654 vex
.prefix
= REPE_PREFIX_OPCODE
;
11657 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11664 dp
= &vex_table
[vex_table_index
][vindex
];
11666 /* There is no MODRM byte for VEX0F 77. */
11667 if (vex_table_index
!= VEX_0F
|| vindex
!= 0x77)
11669 FETCH_DATA (info
, codep
+ 1);
11670 modrm
.mod
= (*codep
>> 6) & 3;
11671 modrm
.reg
= (*codep
>> 3) & 7;
11672 modrm
.rm
= *codep
& 7;
11676 case USE_VEX_C5_TABLE
:
11678 FETCH_DATA (info
, codep
+ 2);
11679 /* All bits in the REX prefix are ignored. */
11681 rex
= (*codep
& 0x80) ? 0 : REX_R
;
11683 /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
11685 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11686 vex
.length
= (*codep
& 0x4) ? 256 : 128;
11687 switch ((*codep
& 0x3))
11692 vex
.prefix
= DATA_PREFIX_OPCODE
;
11695 vex
.prefix
= REPE_PREFIX_OPCODE
;
11698 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11705 dp
= &vex_table
[dp
->op
[1].bytemode
][vindex
];
11707 /* There is no MODRM byte for VEX 77. */
11708 if (vindex
!= 0x77)
11710 FETCH_DATA (info
, codep
+ 1);
11711 modrm
.mod
= (*codep
>> 6) & 3;
11712 modrm
.reg
= (*codep
>> 3) & 7;
11713 modrm
.rm
= *codep
& 7;
11717 case USE_VEX_W_TABLE
:
11721 dp
= &vex_w_table
[dp
->op
[1].bytemode
][vex
.w
? 1 : 0];
11724 case USE_EVEX_TABLE
:
11725 two_source_ops
= 0;
11728 FETCH_DATA (info
, codep
+ 4);
11729 /* All bits in the REX prefix are ignored. */
11731 /* The first byte after 0x62. */
11732 rex
= ~(*codep
>> 5) & 0x7;
11733 vex
.r
= *codep
& 0x10;
11734 switch ((*codep
& 0xf))
11737 return &bad_opcode
;
11739 vex_table_index
= EVEX_0F
;
11742 vex_table_index
= EVEX_0F38
;
11745 vex_table_index
= EVEX_0F3A
;
11749 /* The second byte after 0x62. */
11751 vex
.w
= *codep
& 0x80;
11752 if (vex
.w
&& address_mode
== mode_64bit
)
11755 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11758 if (!(*codep
& 0x4))
11759 return &bad_opcode
;
11761 switch ((*codep
& 0x3))
11766 vex
.prefix
= DATA_PREFIX_OPCODE
;
11769 vex
.prefix
= REPE_PREFIX_OPCODE
;
11772 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11776 /* The third byte after 0x62. */
11779 /* Remember the static rounding bits. */
11780 vex
.ll
= (*codep
>> 5) & 3;
11781 vex
.b
= (*codep
& 0x10) != 0;
11783 vex
.v
= *codep
& 0x8;
11784 vex
.mask_register_specifier
= *codep
& 0x7;
11785 vex
.zeroing
= *codep
& 0x80;
11787 if (address_mode
!= mode_64bit
)
11789 /* In 16/32-bit mode silently ignore following bits. */
11799 dp
= &evex_table
[vex_table_index
][vindex
];
11801 FETCH_DATA (info
, codep
+ 1);
11802 modrm
.mod
= (*codep
>> 6) & 3;
11803 modrm
.reg
= (*codep
>> 3) & 7;
11804 modrm
.rm
= *codep
& 7;
11806 /* Set vector length. */
11807 if (modrm
.mod
== 3 && vex
.b
)
11823 return &bad_opcode
;
11836 if (dp
->name
!= NULL
)
11839 return get_valid_dis386 (dp
, info
);
11843 get_sib (disassemble_info
*info
, int sizeflag
)
11845 /* If modrm.mod == 3, operand must be register. */
11847 && ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
11851 FETCH_DATA (info
, codep
+ 2);
11852 sib
.index
= (codep
[1] >> 3) & 7;
11853 sib
.scale
= (codep
[1] >> 6) & 3;
11854 sib
.base
= codep
[1] & 7;
11859 print_insn (bfd_vma pc
, disassemble_info
*info
)
11861 const struct dis386
*dp
;
11863 char *op_txt
[MAX_OPERANDS
];
11865 int sizeflag
, orig_sizeflag
;
11867 struct dis_private priv
;
11870 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
11871 if ((info
->mach
& bfd_mach_i386_i386
) != 0)
11872 address_mode
= mode_32bit
;
11873 else if (info
->mach
== bfd_mach_i386_i8086
)
11875 address_mode
= mode_16bit
;
11876 priv
.orig_sizeflag
= 0;
11879 address_mode
= mode_64bit
;
11881 if (intel_syntax
== (char) -1)
11882 intel_syntax
= (info
->mach
& bfd_mach_i386_intel_syntax
) != 0;
11884 for (p
= info
->disassembler_options
; p
!= NULL
; )
11886 if (CONST_STRNEQ (p
, "amd64"))
11888 else if (CONST_STRNEQ (p
, "intel64"))
11890 else if (CONST_STRNEQ (p
, "x86-64"))
11892 address_mode
= mode_64bit
;
11893 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
11895 else if (CONST_STRNEQ (p
, "i386"))
11897 address_mode
= mode_32bit
;
11898 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
11900 else if (CONST_STRNEQ (p
, "i8086"))
11902 address_mode
= mode_16bit
;
11903 priv
.orig_sizeflag
= 0;
11905 else if (CONST_STRNEQ (p
, "intel"))
11908 if (CONST_STRNEQ (p
+ 5, "-mnemonic"))
11909 intel_mnemonic
= 1;
11911 else if (CONST_STRNEQ (p
, "att"))
11914 if (CONST_STRNEQ (p
+ 3, "-mnemonic"))
11915 intel_mnemonic
= 0;
11917 else if (CONST_STRNEQ (p
, "addr"))
11919 if (address_mode
== mode_64bit
)
11921 if (p
[4] == '3' && p
[5] == '2')
11922 priv
.orig_sizeflag
&= ~AFLAG
;
11923 else if (p
[4] == '6' && p
[5] == '4')
11924 priv
.orig_sizeflag
|= AFLAG
;
11928 if (p
[4] == '1' && p
[5] == '6')
11929 priv
.orig_sizeflag
&= ~AFLAG
;
11930 else if (p
[4] == '3' && p
[5] == '2')
11931 priv
.orig_sizeflag
|= AFLAG
;
11934 else if (CONST_STRNEQ (p
, "data"))
11936 if (p
[4] == '1' && p
[5] == '6')
11937 priv
.orig_sizeflag
&= ~DFLAG
;
11938 else if (p
[4] == '3' && p
[5] == '2')
11939 priv
.orig_sizeflag
|= DFLAG
;
11941 else if (CONST_STRNEQ (p
, "suffix"))
11942 priv
.orig_sizeflag
|= SUFFIX_ALWAYS
;
11944 p
= strchr (p
, ',');
11949 if (address_mode
== mode_64bit
&& sizeof (bfd_vma
) < 8)
11951 (*info
->fprintf_func
) (info
->stream
,
11952 _("64-bit address is disabled"));
11958 names64
= intel_names64
;
11959 names32
= intel_names32
;
11960 names16
= intel_names16
;
11961 names8
= intel_names8
;
11962 names8rex
= intel_names8rex
;
11963 names_seg
= intel_names_seg
;
11964 names_mm
= intel_names_mm
;
11965 names_bnd
= intel_names_bnd
;
11966 names_xmm
= intel_names_xmm
;
11967 names_ymm
= intel_names_ymm
;
11968 names_zmm
= intel_names_zmm
;
11969 index64
= intel_index64
;
11970 index32
= intel_index32
;
11971 names_mask
= intel_names_mask
;
11972 index16
= intel_index16
;
11975 separator_char
= '+';
11980 names64
= att_names64
;
11981 names32
= att_names32
;
11982 names16
= att_names16
;
11983 names8
= att_names8
;
11984 names8rex
= att_names8rex
;
11985 names_seg
= att_names_seg
;
11986 names_mm
= att_names_mm
;
11987 names_bnd
= att_names_bnd
;
11988 names_xmm
= att_names_xmm
;
11989 names_ymm
= att_names_ymm
;
11990 names_zmm
= att_names_zmm
;
11991 index64
= att_index64
;
11992 index32
= att_index32
;
11993 names_mask
= att_names_mask
;
11994 index16
= att_index16
;
11997 separator_char
= ',';
12001 /* The output looks better if we put 7 bytes on a line, since that
12002 puts most long word instructions on a single line. Use 8 bytes
12004 if ((info
->mach
& bfd_mach_l1om
) != 0)
12005 info
->bytes_per_line
= 8;
12007 info
->bytes_per_line
= 7;
12009 info
->private_data
= &priv
;
12010 priv
.max_fetched
= priv
.the_buffer
;
12011 priv
.insn_start
= pc
;
12014 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12022 start_codep
= priv
.the_buffer
;
12023 codep
= priv
.the_buffer
;
12025 if (OPCODES_SIGSETJMP (priv
.bailout
) != 0)
12029 /* Getting here means we tried for data but didn't get it. That
12030 means we have an incomplete instruction of some sort. Just
12031 print the first byte as a prefix or a .byte pseudo-op. */
12032 if (codep
> priv
.the_buffer
)
12034 name
= prefix_name (priv
.the_buffer
[0], priv
.orig_sizeflag
);
12036 (*info
->fprintf_func
) (info
->stream
, "%s", name
);
12039 /* Just print the first byte as a .byte instruction. */
12040 (*info
->fprintf_func
) (info
->stream
, ".byte 0x%x",
12041 (unsigned int) priv
.the_buffer
[0]);
12051 sizeflag
= priv
.orig_sizeflag
;
12053 if (!ckprefix () || rex_used
)
12055 /* Too many prefixes or unused REX prefixes. */
12057 i
< (int) ARRAY_SIZE (all_prefixes
) && all_prefixes
[i
];
12059 (*info
->fprintf_func
) (info
->stream
, "%s%s",
12061 prefix_name (all_prefixes
[i
], sizeflag
));
12065 insn_codep
= codep
;
12067 FETCH_DATA (info
, codep
+ 1);
12068 two_source_ops
= (*codep
== 0x62) || (*codep
== 0xc8);
12070 if (((prefixes
& PREFIX_FWAIT
)
12071 && ((*codep
< 0xd8) || (*codep
> 0xdf))))
12073 /* Handle prefixes before fwait. */
12074 for (i
= 0; i
< fwait_prefix
&& all_prefixes
[i
];
12076 (*info
->fprintf_func
) (info
->stream
, "%s ",
12077 prefix_name (all_prefixes
[i
], sizeflag
));
12078 (*info
->fprintf_func
) (info
->stream
, "fwait");
12082 if (*codep
== 0x0f)
12084 unsigned char threebyte
;
12087 FETCH_DATA (info
, codep
+ 1);
12088 threebyte
= *codep
;
12089 dp
= &dis386_twobyte
[threebyte
];
12090 need_modrm
= twobyte_has_modrm
[*codep
];
12095 dp
= &dis386
[*codep
];
12096 need_modrm
= onebyte_has_modrm
[*codep
];
12100 /* Save sizeflag for printing the extra prefixes later before updating
12101 it for mnemonic and operand processing. The prefix names depend
12102 only on the address mode. */
12103 orig_sizeflag
= sizeflag
;
12104 if (prefixes
& PREFIX_ADDR
)
12106 if ((prefixes
& PREFIX_DATA
))
12112 FETCH_DATA (info
, codep
+ 1);
12113 modrm
.mod
= (*codep
>> 6) & 3;
12114 modrm
.reg
= (*codep
>> 3) & 7;
12115 modrm
.rm
= *codep
& 7;
12121 memset (&vex
, 0, sizeof (vex
));
12123 if (dp
->name
== NULL
&& dp
->op
[0].bytemode
== FLOATCODE
)
12125 get_sib (info
, sizeflag
);
12126 dofloat (sizeflag
);
12130 dp
= get_valid_dis386 (dp
, info
);
12131 if (dp
!= NULL
&& putop (dp
->name
, sizeflag
) == 0)
12133 get_sib (info
, sizeflag
);
12134 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12137 op_ad
= MAX_OPERANDS
- 1 - i
;
12139 (*dp
->op
[i
].rtn
) (dp
->op
[i
].bytemode
, sizeflag
);
12140 /* For EVEX instruction after the last operand masking
12141 should be printed. */
12142 if (i
== 0 && vex
.evex
)
12144 /* Don't print {%k0}. */
12145 if (vex
.mask_register_specifier
)
12148 oappend (names_mask
[vex
.mask_register_specifier
]);
12158 /* Clear instruction information. */
12161 the_info
->insn_info_valid
= 0;
12162 the_info
->branch_delay_insns
= 0;
12163 the_info
->data_size
= 0;
12164 the_info
->insn_type
= dis_noninsn
;
12165 the_info
->target
= 0;
12166 the_info
->target2
= 0;
12169 /* Reset jump operation indicator. */
12170 op_is_jump
= FALSE
;
12173 int jump_detection
= 0;
12175 /* Extract flags. */
12176 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12178 if ((dp
->op
[i
].rtn
== OP_J
)
12179 || (dp
->op
[i
].rtn
== OP_indirE
))
12180 jump_detection
|= 1;
12181 else if ((dp
->op
[i
].rtn
== BND_Fixup
)
12182 || (!dp
->op
[i
].rtn
&& !dp
->op
[i
].bytemode
))
12183 jump_detection
|= 2;
12184 else if ((dp
->op
[i
].bytemode
== cond_jump_mode
)
12185 || (dp
->op
[i
].bytemode
== loop_jcxz_mode
))
12186 jump_detection
|= 4;
12189 /* Determine if this is a jump or branch. */
12190 if ((jump_detection
& 0x3) == 0x3)
12193 if (jump_detection
& 0x4)
12194 the_info
->insn_type
= dis_condbranch
;
12196 the_info
->insn_type
=
12197 (dp
->name
&& !strncmp(dp
->name
, "call", 4))
12198 ? dis_jsr
: dis_branch
;
12202 /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
12203 are all 0s in inverted form. */
12204 if (need_vex
&& vex
.register_specifier
!= 0)
12206 (*info
->fprintf_func
) (info
->stream
, "(bad)");
12207 return end_codep
- priv
.the_buffer
;
12210 /* Check if the REX prefix is used. */
12211 if (rex_ignored
== 0 && (rex
^ rex_used
) == 0 && last_rex_prefix
>= 0)
12212 all_prefixes
[last_rex_prefix
] = 0;
12214 /* Check if the SEG prefix is used. */
12215 if ((prefixes
& (PREFIX_CS
| PREFIX_SS
| PREFIX_DS
| PREFIX_ES
12216 | PREFIX_FS
| PREFIX_GS
)) != 0
12217 && (used_prefixes
& active_seg_prefix
) != 0)
12218 all_prefixes
[last_seg_prefix
] = 0;
12220 /* Check if the ADDR prefix is used. */
12221 if ((prefixes
& PREFIX_ADDR
) != 0
12222 && (used_prefixes
& PREFIX_ADDR
) != 0)
12223 all_prefixes
[last_addr_prefix
] = 0;
12225 /* Check if the DATA prefix is used. */
12226 if ((prefixes
& PREFIX_DATA
) != 0
12227 && (used_prefixes
& PREFIX_DATA
) != 0)
12228 all_prefixes
[last_data_prefix
] = 0;
12230 /* Print the extra prefixes. */
12232 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
12233 if (all_prefixes
[i
])
12236 name
= prefix_name (all_prefixes
[i
], orig_sizeflag
);
12239 prefix_length
+= strlen (name
) + 1;
12240 (*info
->fprintf_func
) (info
->stream
, "%s ", name
);
12243 /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
12244 unused, opcode is invalid. Since the PREFIX_DATA prefix may be
12245 used by putop and MMX/SSE operand and may be overriden by the
12246 PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
12248 if (dp
->prefix_requirement
== PREFIX_OPCODE
12249 && dp
!= &bad_opcode
12251 & (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0
12253 & (PREFIX_REPZ
| PREFIX_REPNZ
)) == 0)
12255 & (PREFIX_REPZ
| PREFIX_REPNZ
| PREFIX_DATA
))
12257 && (used_prefixes
& PREFIX_DATA
) == 0))))
12259 (*info
->fprintf_func
) (info
->stream
, "(bad)");
12260 return end_codep
- priv
.the_buffer
;
12263 /* Check maximum code length. */
12264 if ((codep
- start_codep
) > MAX_CODE_LENGTH
)
12266 (*info
->fprintf_func
) (info
->stream
, "(bad)");
12267 return MAX_CODE_LENGTH
;
12270 obufp
= mnemonicendp
;
12271 for (i
= strlen (obuf
) + prefix_length
; i
< 6; i
++)
12274 (*info
->fprintf_func
) (info
->stream
, "%s", obuf
);
12276 /* The enter and bound instructions are printed with operands in the same
12277 order as the intel book; everything else is printed in reverse order. */
12278 if (intel_syntax
|| two_source_ops
)
12282 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12283 op_txt
[i
] = op_out
[i
];
12285 if (intel_syntax
&& dp
&& dp
->op
[2].rtn
== OP_Rounding
12286 && dp
->op
[3].rtn
== OP_E
&& dp
->op
[4].rtn
== NULL
)
12288 op_txt
[2] = op_out
[3];
12289 op_txt
[3] = op_out
[2];
12292 for (i
= 0; i
< (MAX_OPERANDS
>> 1); ++i
)
12294 op_ad
= op_index
[i
];
12295 op_index
[i
] = op_index
[MAX_OPERANDS
- 1 - i
];
12296 op_index
[MAX_OPERANDS
- 1 - i
] = op_ad
;
12297 riprel
= op_riprel
[i
];
12298 op_riprel
[i
] = op_riprel
[MAX_OPERANDS
- 1 - i
];
12299 op_riprel
[MAX_OPERANDS
- 1 - i
] = riprel
;
12304 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12305 op_txt
[MAX_OPERANDS
- 1 - i
] = op_out
[i
];
12309 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12313 (*info
->fprintf_func
) (info
->stream
, ",");
12314 if (op_index
[i
] != -1 && !op_riprel
[i
])
12316 bfd_vma target
= (bfd_vma
) op_address
[op_index
[i
]];
12318 if (the_info
&& op_is_jump
)
12320 the_info
->insn_info_valid
= 1;
12321 the_info
->branch_delay_insns
= 0;
12322 the_info
->data_size
= 0;
12323 the_info
->target
= target
;
12324 the_info
->target2
= 0;
12326 (*info
->print_address_func
) (target
, info
);
12329 (*info
->fprintf_func
) (info
->stream
, "%s", op_txt
[i
]);
12333 for (i
= 0; i
< MAX_OPERANDS
; i
++)
12334 if (op_index
[i
] != -1 && op_riprel
[i
])
12336 (*info
->fprintf_func
) (info
->stream
, " # ");
12337 (*info
->print_address_func
) ((bfd_vma
) (start_pc
+ (codep
- start_codep
)
12338 + op_address
[op_index
[i
]]), info
);
12341 return codep
- priv
.the_buffer
;
12344 static const char *float_mem
[] = {
12419 static const unsigned char float_mem_mode
[] = {
12494 #define ST { OP_ST, 0 }
12495 #define STi { OP_STi, 0 }
12497 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
12498 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
12499 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
12500 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
12501 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
12502 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
12503 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
12504 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
12505 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
12507 static const struct dis386 float_reg
[][8] = {
12510 { "fadd", { ST
, STi
}, 0 },
12511 { "fmul", { ST
, STi
}, 0 },
12512 { "fcom", { STi
}, 0 },
12513 { "fcomp", { STi
}, 0 },
12514 { "fsub", { ST
, STi
}, 0 },
12515 { "fsubr", { ST
, STi
}, 0 },
12516 { "fdiv", { ST
, STi
}, 0 },
12517 { "fdivr", { ST
, STi
}, 0 },
12521 { "fld", { STi
}, 0 },
12522 { "fxch", { STi
}, 0 },
12532 { "fcmovb", { ST
, STi
}, 0 },
12533 { "fcmove", { ST
, STi
}, 0 },
12534 { "fcmovbe",{ ST
, STi
}, 0 },
12535 { "fcmovu", { ST
, STi
}, 0 },
12543 { "fcmovnb",{ ST
, STi
}, 0 },
12544 { "fcmovne",{ ST
, STi
}, 0 },
12545 { "fcmovnbe",{ ST
, STi
}, 0 },
12546 { "fcmovnu",{ ST
, STi
}, 0 },
12548 { "fucomi", { ST
, STi
}, 0 },
12549 { "fcomi", { ST
, STi
}, 0 },
12554 { "fadd", { STi
, ST
}, 0 },
12555 { "fmul", { STi
, ST
}, 0 },
12558 { "fsub{!M|r}", { STi
, ST
}, 0 },
12559 { "fsub{M|}", { STi
, ST
}, 0 },
12560 { "fdiv{!M|r}", { STi
, ST
}, 0 },
12561 { "fdiv{M|}", { STi
, ST
}, 0 },
12565 { "ffree", { STi
}, 0 },
12567 { "fst", { STi
}, 0 },
12568 { "fstp", { STi
}, 0 },
12569 { "fucom", { STi
}, 0 },
12570 { "fucomp", { STi
}, 0 },
12576 { "faddp", { STi
, ST
}, 0 },
12577 { "fmulp", { STi
, ST
}, 0 },
12580 { "fsub{!M|r}p", { STi
, ST
}, 0 },
12581 { "fsub{M|}p", { STi
, ST
}, 0 },
12582 { "fdiv{!M|r}p", { STi
, ST
}, 0 },
12583 { "fdiv{M|}p", { STi
, ST
}, 0 },
12587 { "ffreep", { STi
}, 0 },
12592 { "fucomip", { ST
, STi
}, 0 },
12593 { "fcomip", { ST
, STi
}, 0 },
12598 static char *fgrps
[][8] = {
12601 "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12606 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12611 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
12616 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
12621 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
12626 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
12631 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12636 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
12637 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
12642 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12647 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12652 swap_operand (void)
12654 mnemonicendp
[0] = '.';
12655 mnemonicendp
[1] = 's';
12660 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED
,
12661 int sizeflag ATTRIBUTE_UNUSED
)
12663 /* Skip mod/rm byte. */
12669 dofloat (int sizeflag
)
12671 const struct dis386
*dp
;
12672 unsigned char floatop
;
12674 floatop
= codep
[-1];
12676 if (modrm
.mod
!= 3)
12678 int fp_indx
= (floatop
- 0xd8) * 8 + modrm
.reg
;
12680 putop (float_mem
[fp_indx
], sizeflag
);
12683 OP_E (float_mem_mode
[fp_indx
], sizeflag
);
12686 /* Skip mod/rm byte. */
12690 dp
= &float_reg
[floatop
- 0xd8][modrm
.reg
];
12691 if (dp
->name
== NULL
)
12693 putop (fgrps
[dp
->op
[0].bytemode
][modrm
.rm
], sizeflag
);
12695 /* Instruction fnstsw is only one with strange arg. */
12696 if (floatop
== 0xdf && codep
[-1] == 0xe0)
12697 strcpy (op_out
[0], names16
[0]);
12701 putop (dp
->name
, sizeflag
);
12706 (*dp
->op
[0].rtn
) (dp
->op
[0].bytemode
, sizeflag
);
12711 (*dp
->op
[1].rtn
) (dp
->op
[1].bytemode
, sizeflag
);
12715 /* Like oappend (below), but S is a string starting with '%'.
12716 In Intel syntax, the '%' is elided. */
12718 oappend_maybe_intel (const char *s
)
12720 oappend (s
+ intel_syntax
);
12724 OP_ST (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
12726 oappend_maybe_intel ("%st");
12730 OP_STi (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
12732 sprintf (scratchbuf
, "%%st(%d)", modrm
.rm
);
12733 oappend_maybe_intel (scratchbuf
);
12736 /* Capital letters in template are macros. */
12738 putop (const char *in_template
, int sizeflag
)
12743 unsigned int l
= 0, len
= 1;
12746 #define SAVE_LAST(c) \
12747 if (l < len && l < sizeof (last)) \
12752 for (p
= in_template
; *p
; p
++)
12768 while (*++p
!= '|')
12769 if (*p
== '}' || *p
== '\0')
12772 /* Fall through. */
12777 while (*++p
!= '}')
12788 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
12792 if (l
== 0 && len
== 1)
12797 if (sizeflag
& SUFFIX_ALWAYS
)
12810 if (address_mode
== mode_64bit
12811 && !(prefixes
& PREFIX_ADDR
))
12822 if (intel_syntax
&& !alt
)
12824 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
12826 if (sizeflag
& DFLAG
)
12827 *obufp
++ = intel_syntax
? 'd' : 'l';
12829 *obufp
++ = intel_syntax
? 'w' : 's';
12830 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12834 if (intel_syntax
|| !(sizeflag
& SUFFIX_ALWAYS
))
12837 if (modrm
.mod
== 3)
12843 if (sizeflag
& DFLAG
)
12844 *obufp
++ = intel_syntax
? 'd' : 'l';
12847 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12853 case 'E': /* For jcxz/jecxz */
12854 if (address_mode
== mode_64bit
)
12856 if (sizeflag
& AFLAG
)
12862 if (sizeflag
& AFLAG
)
12864 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
12869 if ((prefixes
& PREFIX_ADDR
) || (sizeflag
& SUFFIX_ALWAYS
))
12871 if (sizeflag
& AFLAG
)
12872 *obufp
++ = address_mode
== mode_64bit
? 'q' : 'l';
12874 *obufp
++ = address_mode
== mode_64bit
? 'l' : 'w';
12875 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
12879 if (intel_syntax
|| (obufp
[-1] != 's' && !(sizeflag
& SUFFIX_ALWAYS
)))
12881 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
12885 if (!(rex
& REX_W
))
12886 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12891 if ((prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_CS
12892 || (prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_DS
)
12894 used_prefixes
|= prefixes
& (PREFIX_CS
| PREFIX_DS
);
12897 if (prefixes
& PREFIX_DS
)
12916 if (l
!= 0 || len
!= 1)
12918 if (l
!= 1 || len
!= 2 || last
[0] != 'X')
12923 if (!need_vex
|| !vex
.evex
)
12926 || ((modrm
.mod
== 3 || vex
.b
) && !(sizeflag
& SUFFIX_ALWAYS
)))
12928 switch (vex
.length
)
12946 if (address_mode
== mode_64bit
&& (sizeflag
& SUFFIX_ALWAYS
))
12951 /* Fall through. */
12954 if (l
!= 0 || len
!= 1)
12962 if (sizeflag
& SUFFIX_ALWAYS
)
12966 if (intel_mnemonic
!= cond
)
12970 if ((prefixes
& PREFIX_FWAIT
) == 0)
12973 used_prefixes
|= PREFIX_FWAIT
;
12979 else if (intel_syntax
&& (sizeflag
& DFLAG
))
12983 if (!(rex
& REX_W
))
12984 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12988 && address_mode
== mode_64bit
12989 && isa64
== intel64
)
12994 /* Fall through. */
12997 && address_mode
== mode_64bit
12998 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13003 /* Fall through. */
13006 if (l
== 0 && len
== 1)
13011 if ((rex
& REX_W
) == 0
13012 && (prefixes
& PREFIX_DATA
))
13014 if ((sizeflag
& DFLAG
) == 0)
13016 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13020 if ((prefixes
& PREFIX_DATA
)
13022 || (sizeflag
& SUFFIX_ALWAYS
))
13029 if (sizeflag
& DFLAG
)
13033 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13039 if (l
!= 1 || len
!= 2 || last
[0] != 'L')
13045 if ((prefixes
& PREFIX_DATA
)
13047 || (sizeflag
& SUFFIX_ALWAYS
))
13054 if (sizeflag
& DFLAG
)
13055 *obufp
++ = intel_syntax
? 'd' : 'l';
13058 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13066 if (address_mode
== mode_64bit
13067 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13069 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
13073 /* Fall through. */
13076 if (l
== 0 && len
== 1)
13079 if (intel_syntax
&& !alt
)
13082 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
13088 if (sizeflag
& DFLAG
)
13089 *obufp
++ = intel_syntax
? 'd' : 'l';
13092 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13098 if (l
!= 1 || len
!= 2 || last
[0] != 'L')
13104 || (modrm
.mod
== 3 && !(sizeflag
& SUFFIX_ALWAYS
)))
13119 else if (sizeflag
& DFLAG
)
13128 if (intel_syntax
&& !p
[1]
13129 && ((rex
& REX_W
) || (sizeflag
& DFLAG
)))
13131 if (!(rex
& REX_W
))
13132 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13135 if (l
== 0 && len
== 1)
13139 if (address_mode
== mode_64bit
13140 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13142 if (sizeflag
& SUFFIX_ALWAYS
)
13164 /* Fall through. */
13167 if (l
== 0 && len
== 1)
13172 if (sizeflag
& SUFFIX_ALWAYS
)
13178 if (sizeflag
& DFLAG
)
13182 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13196 if (address_mode
== mode_64bit
13197 && !(prefixes
& PREFIX_ADDR
))
13208 if (l
!= 0 || len
!= 1)
13213 if (need_vex
&& vex
.prefix
)
13215 if (vex
.prefix
== DATA_PREFIX_OPCODE
)
13222 if (prefixes
& PREFIX_DATA
)
13226 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13230 if (l
== 0 && len
== 1)
13234 if (l
!= 1 || len
!= 2 || last
[0] != 'X')
13242 || ((modrm
.mod
== 3 || vex
.b
) && !(sizeflag
& SUFFIX_ALWAYS
)))
13244 switch (vex
.length
)
13260 if (l
== 0 && len
== 1)
13262 /* operand size flag for cwtl, cbtw */
13271 else if (sizeflag
& DFLAG
)
13275 if (!(rex
& REX_W
))
13276 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13283 && last
[0] != 'L'))
13290 if (last
[0] == 'X')
13291 *obufp
++ = vex
.w
? 'd': 's';
13293 *obufp
++ = vex
.w
? 'q': 'd';
13299 if (isa64
== intel64
&& (rex
& REX_W
))
13305 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
13307 if (sizeflag
& DFLAG
)
13311 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13317 if (address_mode
== mode_64bit
13318 && (isa64
== intel64
13319 || ((sizeflag
& DFLAG
) || (rex
& REX_W
))))
13321 else if ((prefixes
& PREFIX_DATA
))
13323 if (!(sizeflag
& DFLAG
))
13325 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13332 mnemonicendp
= obufp
;
13337 oappend (const char *s
)
13339 obufp
= stpcpy (obufp
, s
);
13345 /* Only print the active segment register. */
13346 if (!active_seg_prefix
)
13349 used_prefixes
|= active_seg_prefix
;
13350 switch (active_seg_prefix
)
13353 oappend_maybe_intel ("%cs:");
13356 oappend_maybe_intel ("%ds:");
13359 oappend_maybe_intel ("%ss:");
13362 oappend_maybe_intel ("%es:");
13365 oappend_maybe_intel ("%fs:");
13368 oappend_maybe_intel ("%gs:");
13376 OP_indirE (int bytemode
, int sizeflag
)
13380 OP_E (bytemode
, sizeflag
);
13384 print_operand_value (char *buf
, int hex
, bfd_vma disp
)
13386 if (address_mode
== mode_64bit
)
13394 sprintf_vma (tmp
, disp
);
13395 for (i
= 0; tmp
[i
] == '0' && tmp
[i
+ 1]; i
++);
13396 strcpy (buf
+ 2, tmp
+ i
);
13400 bfd_signed_vma v
= disp
;
13407 /* Check for possible overflow on 0x8000000000000000. */
13410 strcpy (buf
, "9223372036854775808");
13424 tmp
[28 - i
] = (v
% 10) + '0';
13428 strcpy (buf
, tmp
+ 29 - i
);
13434 sprintf (buf
, "0x%x", (unsigned int) disp
);
13436 sprintf (buf
, "%d", (int) disp
);
13440 /* Put DISP in BUF as signed hex number. */
13443 print_displacement (char *buf
, bfd_vma disp
)
13445 bfd_signed_vma val
= disp
;
13454 /* Check for possible overflow. */
13457 switch (address_mode
)
13460 strcpy (buf
+ j
, "0x8000000000000000");
13463 strcpy (buf
+ j
, "0x80000000");
13466 strcpy (buf
+ j
, "0x8000");
13476 sprintf_vma (tmp
, (bfd_vma
) val
);
13477 for (i
= 0; tmp
[i
] == '0'; i
++)
13479 if (tmp
[i
] == '\0')
13481 strcpy (buf
+ j
, tmp
+ i
);
13485 intel_operand_size (int bytemode
, int sizeflag
)
13489 && (bytemode
== x_mode
13490 || bytemode
== evex_half_bcst_xmmq_mode
))
13493 oappend ("QWORD PTR ");
13495 oappend ("DWORD PTR ");
13504 oappend ("BYTE PTR ");
13509 oappend ("WORD PTR ");
13512 if (address_mode
== mode_64bit
&& isa64
== intel64
)
13514 oappend ("QWORD PTR ");
13517 /* Fall through. */
13519 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13521 oappend ("QWORD PTR ");
13524 /* Fall through. */
13530 oappend ("QWORD PTR ");
13533 if ((sizeflag
& DFLAG
) || bytemode
== dq_mode
)
13534 oappend ("DWORD PTR ");
13536 oappend ("WORD PTR ");
13537 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13541 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
13543 oappend ("WORD PTR ");
13544 if (!(rex
& REX_W
))
13545 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13548 if (sizeflag
& DFLAG
)
13549 oappend ("QWORD PTR ");
13551 oappend ("DWORD PTR ");
13552 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13555 if (!(sizeflag
& DFLAG
) && isa64
== intel64
)
13556 oappend ("WORD PTR ");
13558 oappend ("DWORD PTR ");
13559 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13562 case d_scalar_mode
:
13563 case d_scalar_swap_mode
:
13566 oappend ("DWORD PTR ");
13569 case q_scalar_mode
:
13570 case q_scalar_swap_mode
:
13572 oappend ("QWORD PTR ");
13575 if (address_mode
== mode_64bit
)
13576 oappend ("QWORD PTR ");
13578 oappend ("DWORD PTR ");
13581 if (sizeflag
& DFLAG
)
13582 oappend ("FWORD PTR ");
13584 oappend ("DWORD PTR ");
13585 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13588 oappend ("TBYTE PTR ");
13592 case evex_x_gscat_mode
:
13593 case evex_x_nobcst_mode
:
13594 case b_scalar_mode
:
13595 case w_scalar_mode
:
13598 switch (vex
.length
)
13601 oappend ("XMMWORD PTR ");
13604 oappend ("YMMWORD PTR ");
13607 oappend ("ZMMWORD PTR ");
13614 oappend ("XMMWORD PTR ");
13617 oappend ("XMMWORD PTR ");
13620 oappend ("YMMWORD PTR ");
13623 case evex_half_bcst_xmmq_mode
:
13627 switch (vex
.length
)
13630 oappend ("QWORD PTR ");
13633 oappend ("XMMWORD PTR ");
13636 oappend ("YMMWORD PTR ");
13646 switch (vex
.length
)
13651 oappend ("BYTE PTR ");
13661 switch (vex
.length
)
13666 oappend ("WORD PTR ");
13676 switch (vex
.length
)
13681 oappend ("DWORD PTR ");
13691 switch (vex
.length
)
13696 oappend ("QWORD PTR ");
13706 switch (vex
.length
)
13709 oappend ("WORD PTR ");
13712 oappend ("DWORD PTR ");
13715 oappend ("QWORD PTR ");
13725 switch (vex
.length
)
13728 oappend ("DWORD PTR ");
13731 oappend ("QWORD PTR ");
13734 oappend ("XMMWORD PTR ");
13744 switch (vex
.length
)
13747 oappend ("QWORD PTR ");
13750 oappend ("YMMWORD PTR ");
13753 oappend ("ZMMWORD PTR ");
13763 switch (vex
.length
)
13767 oappend ("XMMWORD PTR ");
13774 oappend ("OWORD PTR ");
13776 case vex_scalar_w_dq_mode
:
13781 oappend ("QWORD PTR ");
13783 oappend ("DWORD PTR ");
13785 case vex_vsib_d_w_dq_mode
:
13786 case vex_vsib_q_w_dq_mode
:
13793 oappend ("QWORD PTR ");
13795 oappend ("DWORD PTR ");
13799 switch (vex
.length
)
13802 oappend ("XMMWORD PTR ");
13805 oappend ("YMMWORD PTR ");
13808 oappend ("ZMMWORD PTR ");
13815 case vex_vsib_q_w_d_mode
:
13816 case vex_vsib_d_w_d_mode
:
13817 if (!need_vex
|| !vex
.evex
)
13820 switch (vex
.length
)
13823 oappend ("QWORD PTR ");
13826 oappend ("XMMWORD PTR ");
13829 oappend ("YMMWORD PTR ");
13837 if (!need_vex
|| vex
.length
!= 128)
13840 oappend ("DWORD PTR ");
13842 oappend ("BYTE PTR ");
13848 oappend ("QWORD PTR ");
13850 oappend ("WORD PTR ");
13860 OP_E_register (int bytemode
, int sizeflag
)
13862 int reg
= modrm
.rm
;
13863 const char **names
;
13869 if ((sizeflag
& SUFFIX_ALWAYS
)
13870 && (bytemode
== b_swap_mode
13871 || bytemode
== bnd_swap_mode
13872 || bytemode
== v_swap_mode
))
13898 names
= address_mode
== mode_64bit
? names64
: names32
;
13901 case bnd_swap_mode
:
13910 if (address_mode
== mode_64bit
&& isa64
== intel64
)
13915 /* Fall through. */
13917 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13923 /* Fall through. */
13935 if ((sizeflag
& DFLAG
)
13936 || (bytemode
!= v_mode
13937 && bytemode
!= v_swap_mode
))
13941 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13945 if (!(sizeflag
& DFLAG
) && isa64
== intel64
)
13949 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13952 names
= (address_mode
== mode_64bit
13953 ? names64
: names32
);
13954 if (!(prefixes
& PREFIX_ADDR
))
13955 names
= (address_mode
== mode_16bit
13956 ? names16
: names
);
13959 /* Remove "addr16/addr32". */
13960 all_prefixes
[last_addr_prefix
] = 0;
13961 names
= (address_mode
!= mode_32bit
13962 ? names32
: names16
);
13963 used_prefixes
|= PREFIX_ADDR
;
13973 names
= names_mask
;
13978 oappend (INTERNAL_DISASSEMBLER_ERROR
);
13981 oappend (names
[reg
]);
13985 OP_E_memory (int bytemode
, int sizeflag
)
13988 int add
= (rex
& REX_B
) ? 8 : 0;
13994 /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */
13996 && bytemode
!= x_mode
13997 && bytemode
!= xmmq_mode
13998 && bytemode
!= evex_half_bcst_xmmq_mode
)
14014 if (address_mode
!= mode_64bit
)
14020 case vex_scalar_w_dq_mode
:
14021 case vex_vsib_d_w_dq_mode
:
14022 case vex_vsib_d_w_d_mode
:
14023 case vex_vsib_q_w_dq_mode
:
14024 case vex_vsib_q_w_d_mode
:
14025 case evex_x_gscat_mode
:
14026 shift
= vex
.w
? 3 : 2;
14029 case evex_half_bcst_xmmq_mode
:
14033 shift
= vex
.w
? 3 : 2;
14036 /* Fall through. */
14040 case evex_x_nobcst_mode
:
14042 switch (vex
.length
)
14065 case q_scalar_mode
:
14067 case q_scalar_swap_mode
:
14073 case d_scalar_mode
:
14075 case d_scalar_swap_mode
:
14078 case w_scalar_mode
:
14082 case b_scalar_mode
:
14089 /* Make necessary corrections to shift for modes that need it.
14090 For these modes we currently have shift 4, 5 or 6 depending on
14091 vex.length (it corresponds to xmmword, ymmword or zmmword
14092 operand). We might want to make it 3, 4 or 5 (e.g. for
14093 xmmq_mode). In case of broadcast enabled the corrections
14094 aren't needed, as element size is always 32 or 64 bits. */
14096 && (bytemode
== xmmq_mode
14097 || bytemode
== evex_half_bcst_xmmq_mode
))
14099 else if (bytemode
== xmmqd_mode
)
14101 else if (bytemode
== xmmdw_mode
)
14103 else if (bytemode
== ymmq_mode
&& vex
.length
== 128)
14111 intel_operand_size (bytemode
, sizeflag
);
14114 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
14116 /* 32/64 bit address mode */
14126 int addr32flag
= !((sizeflag
& AFLAG
)
14127 || bytemode
== v_bnd_mode
14128 || bytemode
== v_bndmk_mode
14129 || bytemode
== bnd_mode
14130 || bytemode
== bnd_swap_mode
);
14131 const char **indexes64
= names64
;
14132 const char **indexes32
= names32
;
14142 vindex
= sib
.index
;
14148 case vex_vsib_d_w_dq_mode
:
14149 case vex_vsib_d_w_d_mode
:
14150 case vex_vsib_q_w_dq_mode
:
14151 case vex_vsib_q_w_d_mode
:
14161 switch (vex
.length
)
14164 indexes64
= indexes32
= names_xmm
;
14168 || bytemode
== vex_vsib_q_w_dq_mode
14169 || bytemode
== vex_vsib_q_w_d_mode
)
14170 indexes64
= indexes32
= names_ymm
;
14172 indexes64
= indexes32
= names_xmm
;
14176 || bytemode
== vex_vsib_q_w_dq_mode
14177 || bytemode
== vex_vsib_q_w_d_mode
)
14178 indexes64
= indexes32
= names_zmm
;
14180 indexes64
= indexes32
= names_ymm
;
14187 haveindex
= vindex
!= 4;
14194 rbase
= base
+ add
;
14202 if (address_mode
== mode_64bit
&& !havesib
)
14205 if (riprel
&& bytemode
== v_bndmk_mode
)
14213 FETCH_DATA (the_info
, codep
+ 1);
14215 if ((disp
& 0x80) != 0)
14217 if (vex
.evex
&& shift
> 0)
14230 && address_mode
!= mode_16bit
)
14232 if (address_mode
== mode_64bit
)
14234 /* Display eiz instead of addr32. */
14235 needindex
= addr32flag
;
14240 /* In 32-bit mode, we need index register to tell [offset]
14241 from [eiz*1 + offset]. */
14246 havedisp
= (havebase
14248 || (havesib
&& (haveindex
|| scale
!= 0)));
14251 if (modrm
.mod
!= 0 || base
== 5)
14253 if (havedisp
|| riprel
)
14254 print_displacement (scratchbuf
, disp
);
14256 print_operand_value (scratchbuf
, 1, disp
);
14257 oappend (scratchbuf
);
14261 oappend (!addr32flag
? "(%rip)" : "(%eip)");
14265 if ((havebase
|| haveindex
|| needindex
|| needaddr32
|| riprel
)
14266 && (bytemode
!= v_bnd_mode
)
14267 && (bytemode
!= v_bndmk_mode
)
14268 && (bytemode
!= bnd_mode
)
14269 && (bytemode
!= bnd_swap_mode
))
14270 used_prefixes
|= PREFIX_ADDR
;
14272 if (havedisp
|| (intel_syntax
&& riprel
))
14274 *obufp
++ = open_char
;
14275 if (intel_syntax
&& riprel
)
14278 oappend (!addr32flag
? "rip" : "eip");
14282 oappend (address_mode
== mode_64bit
&& !addr32flag
14283 ? names64
[rbase
] : names32
[rbase
]);
14286 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
14287 print index to tell base + index from base. */
14291 || (havebase
&& base
!= ESP_REG_NUM
))
14293 if (!intel_syntax
|| havebase
)
14295 *obufp
++ = separator_char
;
14299 oappend (address_mode
== mode_64bit
&& !addr32flag
14300 ? indexes64
[vindex
] : indexes32
[vindex
]);
14302 oappend (address_mode
== mode_64bit
&& !addr32flag
14303 ? index64
: index32
);
14305 *obufp
++ = scale_char
;
14307 sprintf (scratchbuf
, "%d", 1 << scale
);
14308 oappend (scratchbuf
);
14312 && (disp
|| modrm
.mod
!= 0 || base
== 5))
14314 if (!havedisp
|| (bfd_signed_vma
) disp
>= 0)
14319 else if (modrm
.mod
!= 1 && disp
!= -disp
)
14323 disp
= - (bfd_signed_vma
) disp
;
14327 print_displacement (scratchbuf
, disp
);
14329 print_operand_value (scratchbuf
, 1, disp
);
14330 oappend (scratchbuf
);
14333 *obufp
++ = close_char
;
14336 else if (intel_syntax
)
14338 if (modrm
.mod
!= 0 || base
== 5)
14340 if (!active_seg_prefix
)
14342 oappend (names_seg
[ds_reg
- es_reg
]);
14345 print_operand_value (scratchbuf
, 1, disp
);
14346 oappend (scratchbuf
);
14352 /* 16 bit address mode */
14353 used_prefixes
|= prefixes
& PREFIX_ADDR
;
14360 if ((disp
& 0x8000) != 0)
14365 FETCH_DATA (the_info
, codep
+ 1);
14367 if ((disp
& 0x80) != 0)
14369 if (vex
.evex
&& shift
> 0)
14374 if ((disp
& 0x8000) != 0)
14380 if (modrm
.mod
!= 0 || modrm
.rm
== 6)
14382 print_displacement (scratchbuf
, disp
);
14383 oappend (scratchbuf
);
14386 if (modrm
.mod
!= 0 || modrm
.rm
!= 6)
14388 *obufp
++ = open_char
;
14390 oappend (index16
[modrm
.rm
]);
14392 && (disp
|| modrm
.mod
!= 0 || modrm
.rm
== 6))
14394 if ((bfd_signed_vma
) disp
>= 0)
14399 else if (modrm
.mod
!= 1)
14403 disp
= - (bfd_signed_vma
) disp
;
14406 print_displacement (scratchbuf
, disp
);
14407 oappend (scratchbuf
);
14410 *obufp
++ = close_char
;
14413 else if (intel_syntax
)
14415 if (!active_seg_prefix
)
14417 oappend (names_seg
[ds_reg
- es_reg
]);
14420 print_operand_value (scratchbuf
, 1, disp
& 0xffff);
14421 oappend (scratchbuf
);
14424 if (vex
.evex
&& vex
.b
14425 && (bytemode
== x_mode
14426 || bytemode
== xmmq_mode
14427 || bytemode
== evex_half_bcst_xmmq_mode
))
14430 || bytemode
== xmmq_mode
14431 || bytemode
== evex_half_bcst_xmmq_mode
)
14433 switch (vex
.length
)
14436 oappend ("{1to2}");
14439 oappend ("{1to4}");
14442 oappend ("{1to8}");
14450 switch (vex
.length
)
14453 oappend ("{1to4}");
14456 oappend ("{1to8}");
14459 oappend ("{1to16}");
14469 OP_E (int bytemode
, int sizeflag
)
14471 /* Skip mod/rm byte. */
14475 if (modrm
.mod
== 3)
14476 OP_E_register (bytemode
, sizeflag
);
14478 OP_E_memory (bytemode
, sizeflag
);
14482 OP_G (int bytemode
, int sizeflag
)
14485 const char **names
;
14494 oappend (names8rex
[modrm
.reg
+ add
]);
14496 oappend (names8
[modrm
.reg
+ add
]);
14499 oappend (names16
[modrm
.reg
+ add
]);
14504 oappend (names32
[modrm
.reg
+ add
]);
14507 oappend (names64
[modrm
.reg
+ add
]);
14510 if (modrm
.reg
> 0x3)
14515 oappend (names_bnd
[modrm
.reg
]);
14525 oappend (names64
[modrm
.reg
+ add
]);
14528 if ((sizeflag
& DFLAG
)
14529 || (bytemode
!= v_mode
&& bytemode
!= movsxd_mode
))
14530 oappend (names32
[modrm
.reg
+ add
]);
14532 oappend (names16
[modrm
.reg
+ add
]);
14533 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14537 names
= (address_mode
== mode_64bit
14538 ? names64
: names32
);
14539 if (!(prefixes
& PREFIX_ADDR
))
14541 if (address_mode
== mode_16bit
)
14546 /* Remove "addr16/addr32". */
14547 all_prefixes
[last_addr_prefix
] = 0;
14548 names
= (address_mode
!= mode_32bit
14549 ? names32
: names16
);
14550 used_prefixes
|= PREFIX_ADDR
;
14552 oappend (names
[modrm
.reg
+ add
]);
14555 if (address_mode
== mode_64bit
)
14556 oappend (names64
[modrm
.reg
+ add
]);
14558 oappend (names32
[modrm
.reg
+ add
]);
14562 if ((modrm
.reg
+ add
) > 0x7)
14567 oappend (names_mask
[modrm
.reg
+ add
]);
14570 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14583 FETCH_DATA (the_info
, codep
+ 8);
14584 a
= *codep
++ & 0xff;
14585 a
|= (*codep
++ & 0xff) << 8;
14586 a
|= (*codep
++ & 0xff) << 16;
14587 a
|= (*codep
++ & 0xffu
) << 24;
14588 b
= *codep
++ & 0xff;
14589 b
|= (*codep
++ & 0xff) << 8;
14590 b
|= (*codep
++ & 0xff) << 16;
14591 b
|= (*codep
++ & 0xffu
) << 24;
14592 x
= a
+ ((bfd_vma
) b
<< 32);
14600 static bfd_signed_vma
14603 bfd_signed_vma x
= 0;
14605 FETCH_DATA (the_info
, codep
+ 4);
14606 x
= *codep
++ & (bfd_signed_vma
) 0xff;
14607 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
14608 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
14609 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
14613 static bfd_signed_vma
14616 bfd_signed_vma x
= 0;
14618 FETCH_DATA (the_info
, codep
+ 4);
14619 x
= *codep
++ & (bfd_signed_vma
) 0xff;
14620 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
14621 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
14622 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
14624 x
= (x
^ ((bfd_signed_vma
) 1 << 31)) - ((bfd_signed_vma
) 1 << 31);
14634 FETCH_DATA (the_info
, codep
+ 2);
14635 x
= *codep
++ & 0xff;
14636 x
|= (*codep
++ & 0xff) << 8;
14641 set_op (bfd_vma op
, int riprel
)
14643 op_index
[op_ad
] = op_ad
;
14644 if (address_mode
== mode_64bit
)
14646 op_address
[op_ad
] = op
;
14647 op_riprel
[op_ad
] = riprel
;
14651 /* Mask to get a 32-bit address. */
14652 op_address
[op_ad
] = op
& 0xffffffff;
14653 op_riprel
[op_ad
] = riprel
& 0xffffffff;
14658 OP_REG (int code
, int sizeflag
)
14665 case es_reg
: case ss_reg
: case cs_reg
:
14666 case ds_reg
: case fs_reg
: case gs_reg
:
14667 oappend (names_seg
[code
- es_reg
]);
14679 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
14680 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
14681 s
= names16
[code
- ax_reg
+ add
];
14683 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
14684 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
14687 s
= names8rex
[code
- al_reg
+ add
];
14689 s
= names8
[code
- al_reg
];
14691 case rAX_reg
: case rCX_reg
: case rDX_reg
: case rBX_reg
:
14692 case rSP_reg
: case rBP_reg
: case rSI_reg
: case rDI_reg
:
14693 if (address_mode
== mode_64bit
14694 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14696 s
= names64
[code
- rAX_reg
+ add
];
14699 code
+= eAX_reg
- rAX_reg
;
14700 /* Fall through. */
14701 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
14702 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
14705 s
= names64
[code
- eAX_reg
+ add
];
14708 if (sizeflag
& DFLAG
)
14709 s
= names32
[code
- eAX_reg
+ add
];
14711 s
= names16
[code
- eAX_reg
+ add
];
14712 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14716 s
= INTERNAL_DISASSEMBLER_ERROR
;
14723 OP_IMREG (int code
, int sizeflag
)
14735 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
14736 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
14737 s
= names16
[code
- ax_reg
];
14739 case es_reg
: case ss_reg
: case cs_reg
:
14740 case ds_reg
: case fs_reg
: case gs_reg
:
14741 s
= names_seg
[code
- es_reg
];
14743 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
14744 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
14747 s
= names8rex
[code
- al_reg
];
14749 s
= names8
[code
- al_reg
];
14751 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
14752 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
14755 s
= names64
[code
- eAX_reg
];
14758 if (sizeflag
& DFLAG
)
14759 s
= names32
[code
- eAX_reg
];
14761 s
= names16
[code
- eAX_reg
];
14762 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14765 case z_mode_ax_reg
:
14766 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
14770 if (!(rex
& REX_W
))
14771 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14774 s
= INTERNAL_DISASSEMBLER_ERROR
;
14781 OP_I (int bytemode
, int sizeflag
)
14784 bfd_signed_vma mask
= -1;
14789 FETCH_DATA (the_info
, codep
+ 1);
14799 if (sizeflag
& DFLAG
)
14809 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14825 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14830 scratchbuf
[0] = '$';
14831 print_operand_value (scratchbuf
+ 1, 1, op
);
14832 oappend_maybe_intel (scratchbuf
);
14833 scratchbuf
[0] = '\0';
14837 OP_I64 (int bytemode
, int sizeflag
)
14839 if (bytemode
!= v_mode
|| address_mode
!= mode_64bit
|| !(rex
& REX_W
))
14841 OP_I (bytemode
, sizeflag
);
14847 scratchbuf
[0] = '$';
14848 print_operand_value (scratchbuf
+ 1, 1, get64 ());
14849 oappend_maybe_intel (scratchbuf
);
14850 scratchbuf
[0] = '\0';
14854 OP_sI (int bytemode
, int sizeflag
)
14862 FETCH_DATA (the_info
, codep
+ 1);
14864 if ((op
& 0x80) != 0)
14866 if (bytemode
== b_T_mode
)
14868 if (address_mode
!= mode_64bit
14869 || !((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14871 /* The operand-size prefix is overridden by a REX prefix. */
14872 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
14880 if (!(rex
& REX_W
))
14882 if (sizeflag
& DFLAG
)
14890 /* The operand-size prefix is overridden by a REX prefix. */
14891 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
14897 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14901 scratchbuf
[0] = '$';
14902 print_operand_value (scratchbuf
+ 1, 1, op
);
14903 oappend_maybe_intel (scratchbuf
);
14907 OP_J (int bytemode
, int sizeflag
)
14911 bfd_vma segment
= 0;
14916 FETCH_DATA (the_info
, codep
+ 1);
14918 if ((disp
& 0x80) != 0)
14922 if (isa64
!= intel64
)
14925 if ((sizeflag
& DFLAG
)
14926 || (address_mode
== mode_64bit
14927 && ((isa64
== intel64
&& bytemode
!= dqw_mode
)
14928 || (rex
& REX_W
))))
14933 if ((disp
& 0x8000) != 0)
14935 /* In 16bit mode, address is wrapped around at 64k within
14936 the same segment. Otherwise, a data16 prefix on a jump
14937 instruction means that the pc is masked to 16 bits after
14938 the displacement is added! */
14940 if ((prefixes
& PREFIX_DATA
) == 0)
14941 segment
= ((start_pc
+ (codep
- start_codep
))
14942 & ~((bfd_vma
) 0xffff));
14944 if (address_mode
!= mode_64bit
14945 || (isa64
!= intel64
&& !(rex
& REX_W
)))
14946 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14949 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14952 disp
= ((start_pc
+ (codep
- start_codep
) + disp
) & mask
) | segment
;
14954 print_operand_value (scratchbuf
, 1, disp
);
14955 oappend (scratchbuf
);
14959 OP_SEG (int bytemode
, int sizeflag
)
14961 if (bytemode
== w_mode
)
14962 oappend (names_seg
[modrm
.reg
]);
14964 OP_E (modrm
.mod
== 3 ? bytemode
: w_mode
, sizeflag
);
14968 OP_DIR (int dummy ATTRIBUTE_UNUSED
, int sizeflag
)
14972 if (sizeflag
& DFLAG
)
14982 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14984 sprintf (scratchbuf
, "0x%x:0x%x", seg
, offset
);
14986 sprintf (scratchbuf
, "$0x%x,$0x%x", seg
, offset
);
14987 oappend (scratchbuf
);
14991 OP_OFF (int bytemode
, int sizeflag
)
14995 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
14996 intel_operand_size (bytemode
, sizeflag
);
14999 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
15006 if (!active_seg_prefix
)
15008 oappend (names_seg
[ds_reg
- es_reg
]);
15012 print_operand_value (scratchbuf
, 1, off
);
15013 oappend (scratchbuf
);
15017 OP_OFF64 (int bytemode
, int sizeflag
)
15021 if (address_mode
!= mode_64bit
15022 || (prefixes
& PREFIX_ADDR
))
15024 OP_OFF (bytemode
, sizeflag
);
15028 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
15029 intel_operand_size (bytemode
, sizeflag
);
15036 if (!active_seg_prefix
)
15038 oappend (names_seg
[ds_reg
- es_reg
]);
15042 print_operand_value (scratchbuf
, 1, off
);
15043 oappend (scratchbuf
);
15047 ptr_reg (int code
, int sizeflag
)
15051 *obufp
++ = open_char
;
15052 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
15053 if (address_mode
== mode_64bit
)
15055 if (!(sizeflag
& AFLAG
))
15056 s
= names32
[code
- eAX_reg
];
15058 s
= names64
[code
- eAX_reg
];
15060 else if (sizeflag
& AFLAG
)
15061 s
= names32
[code
- eAX_reg
];
15063 s
= names16
[code
- eAX_reg
];
15065 *obufp
++ = close_char
;
15070 OP_ESreg (int code
, int sizeflag
)
15076 case 0x6d: /* insw/insl */
15077 intel_operand_size (z_mode
, sizeflag
);
15079 case 0xa5: /* movsw/movsl/movsq */
15080 case 0xa7: /* cmpsw/cmpsl/cmpsq */
15081 case 0xab: /* stosw/stosl */
15082 case 0xaf: /* scasw/scasl */
15083 intel_operand_size (v_mode
, sizeflag
);
15086 intel_operand_size (b_mode
, sizeflag
);
15089 oappend_maybe_intel ("%es:");
15090 ptr_reg (code
, sizeflag
);
15094 OP_DSreg (int code
, int sizeflag
)
15100 case 0x6f: /* outsw/outsl */
15101 intel_operand_size (z_mode
, sizeflag
);
15103 case 0xa5: /* movsw/movsl/movsq */
15104 case 0xa7: /* cmpsw/cmpsl/cmpsq */
15105 case 0xad: /* lodsw/lodsl/lodsq */
15106 intel_operand_size (v_mode
, sizeflag
);
15109 intel_operand_size (b_mode
, sizeflag
);
15112 /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
15113 default segment register DS is printed. */
15114 if (!active_seg_prefix
)
15115 active_seg_prefix
= PREFIX_DS
;
15117 ptr_reg (code
, sizeflag
);
15121 OP_C (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15129 else if (address_mode
!= mode_64bit
&& (prefixes
& PREFIX_LOCK
))
15131 all_prefixes
[last_lock_prefix
] = 0;
15132 used_prefixes
|= PREFIX_LOCK
;
15137 sprintf (scratchbuf
, "%%cr%d", modrm
.reg
+ add
);
15138 oappend_maybe_intel (scratchbuf
);
15142 OP_D (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15151 sprintf (scratchbuf
, "db%d", modrm
.reg
+ add
);
15153 sprintf (scratchbuf
, "%%db%d", modrm
.reg
+ add
);
15154 oappend (scratchbuf
);
15158 OP_T (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15160 sprintf (scratchbuf
, "%%tr%d", modrm
.reg
);
15161 oappend_maybe_intel (scratchbuf
);
15165 OP_R (int bytemode
, int sizeflag
)
15167 /* Skip mod/rm byte. */
15170 OP_E_register (bytemode
, sizeflag
);
15174 OP_MMX (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15176 int reg
= modrm
.reg
;
15177 const char **names
;
15179 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15180 if (prefixes
& PREFIX_DATA
)
15189 oappend (names
[reg
]);
15193 OP_XMM (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
15195 int reg
= modrm
.reg
;
15196 const char **names
;
15208 && bytemode
!= xmm_mode
15209 && bytemode
!= xmmq_mode
15210 && bytemode
!= evex_half_bcst_xmmq_mode
15211 && bytemode
!= ymm_mode
15212 && bytemode
!= scalar_mode
)
15214 switch (vex
.length
)
15221 || (bytemode
!= vex_vsib_q_w_dq_mode
15222 && bytemode
!= vex_vsib_q_w_d_mode
))
15234 else if (bytemode
== xmmq_mode
15235 || bytemode
== evex_half_bcst_xmmq_mode
)
15237 switch (vex
.length
)
15250 else if (bytemode
== ymm_mode
)
15254 oappend (names
[reg
]);
15258 OP_EM (int bytemode
, int sizeflag
)
15261 const char **names
;
15263 if (modrm
.mod
!= 3)
15266 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
15268 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
15269 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15271 OP_E (bytemode
, sizeflag
);
15275 if ((sizeflag
& SUFFIX_ALWAYS
) && bytemode
== v_swap_mode
)
15278 /* Skip mod/rm byte. */
15281 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15283 if (prefixes
& PREFIX_DATA
)
15292 oappend (names
[reg
]);
15295 /* cvt* are the only instructions in sse2 which have
15296 both SSE and MMX operands and also have 0x66 prefix
15297 in their opcode. 0x66 was originally used to differentiate
15298 between SSE and MMX instruction(operands). So we have to handle the
15299 cvt* separately using OP_EMC and OP_MXC */
15301 OP_EMC (int bytemode
, int sizeflag
)
15303 if (modrm
.mod
!= 3)
15305 if (intel_syntax
&& bytemode
== v_mode
)
15307 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
15308 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15310 OP_E (bytemode
, sizeflag
);
15314 /* Skip mod/rm byte. */
15317 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15318 oappend (names_mm
[modrm
.rm
]);
15322 OP_MXC (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15324 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15325 oappend (names_mm
[modrm
.reg
]);
15329 OP_EX (int bytemode
, int sizeflag
)
15332 const char **names
;
15334 /* Skip mod/rm byte. */
15338 if (modrm
.mod
!= 3)
15340 OP_E_memory (bytemode
, sizeflag
);
15355 if ((sizeflag
& SUFFIX_ALWAYS
)
15356 && (bytemode
== x_swap_mode
15357 || bytemode
== d_swap_mode
15358 || bytemode
== d_scalar_swap_mode
15359 || bytemode
== q_swap_mode
15360 || bytemode
== q_scalar_swap_mode
))
15364 && bytemode
!= xmm_mode
15365 && bytemode
!= xmmdw_mode
15366 && bytemode
!= xmmqd_mode
15367 && bytemode
!= xmm_mb_mode
15368 && bytemode
!= xmm_mw_mode
15369 && bytemode
!= xmm_md_mode
15370 && bytemode
!= xmm_mq_mode
15371 && bytemode
!= xmmq_mode
15372 && bytemode
!= evex_half_bcst_xmmq_mode
15373 && bytemode
!= ymm_mode
15374 && bytemode
!= d_scalar_mode
15375 && bytemode
!= d_scalar_swap_mode
15376 && bytemode
!= q_scalar_mode
15377 && bytemode
!= q_scalar_swap_mode
15378 && bytemode
!= vex_scalar_w_dq_mode
)
15380 switch (vex
.length
)
15395 else if (bytemode
== xmmq_mode
15396 || bytemode
== evex_half_bcst_xmmq_mode
)
15398 switch (vex
.length
)
15411 else if (bytemode
== ymm_mode
)
15415 oappend (names
[reg
]);
15419 OP_MS (int bytemode
, int sizeflag
)
15421 if (modrm
.mod
== 3)
15422 OP_EM (bytemode
, sizeflag
);
15428 OP_XS (int bytemode
, int sizeflag
)
15430 if (modrm
.mod
== 3)
15431 OP_EX (bytemode
, sizeflag
);
15437 OP_M (int bytemode
, int sizeflag
)
15439 if (modrm
.mod
== 3)
15440 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
15443 OP_E (bytemode
, sizeflag
);
15447 OP_0f07 (int bytemode
, int sizeflag
)
15449 if (modrm
.mod
!= 3 || modrm
.rm
!= 0)
15452 OP_E (bytemode
, sizeflag
);
15455 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
15456 32bit mode and "xchg %rax,%rax" in 64bit mode. */
15459 NOP_Fixup1 (int bytemode
, int sizeflag
)
15461 if ((prefixes
& PREFIX_DATA
) != 0
15464 && address_mode
== mode_64bit
))
15465 OP_REG (bytemode
, sizeflag
);
15467 strcpy (obuf
, "nop");
15471 NOP_Fixup2 (int bytemode
, int sizeflag
)
15473 if ((prefixes
& PREFIX_DATA
) != 0
15476 && address_mode
== mode_64bit
))
15477 OP_IMREG (bytemode
, sizeflag
);
15480 static const char *const Suffix3DNow
[] = {
15481 /* 00 */ NULL
, NULL
, NULL
, NULL
,
15482 /* 04 */ NULL
, NULL
, NULL
, NULL
,
15483 /* 08 */ NULL
, NULL
, NULL
, NULL
,
15484 /* 0C */ "pi2fw", "pi2fd", NULL
, NULL
,
15485 /* 10 */ NULL
, NULL
, NULL
, NULL
,
15486 /* 14 */ NULL
, NULL
, NULL
, NULL
,
15487 /* 18 */ NULL
, NULL
, NULL
, NULL
,
15488 /* 1C */ "pf2iw", "pf2id", NULL
, NULL
,
15489 /* 20 */ NULL
, NULL
, NULL
, NULL
,
15490 /* 24 */ NULL
, NULL
, NULL
, NULL
,
15491 /* 28 */ NULL
, NULL
, NULL
, NULL
,
15492 /* 2C */ NULL
, NULL
, NULL
, NULL
,
15493 /* 30 */ NULL
, NULL
, NULL
, NULL
,
15494 /* 34 */ NULL
, NULL
, NULL
, NULL
,
15495 /* 38 */ NULL
, NULL
, NULL
, NULL
,
15496 /* 3C */ NULL
, NULL
, NULL
, NULL
,
15497 /* 40 */ NULL
, NULL
, NULL
, NULL
,
15498 /* 44 */ NULL
, NULL
, NULL
, NULL
,
15499 /* 48 */ NULL
, NULL
, NULL
, NULL
,
15500 /* 4C */ NULL
, NULL
, NULL
, NULL
,
15501 /* 50 */ NULL
, NULL
, NULL
, NULL
,
15502 /* 54 */ NULL
, NULL
, NULL
, NULL
,
15503 /* 58 */ NULL
, NULL
, NULL
, NULL
,
15504 /* 5C */ NULL
, NULL
, NULL
, NULL
,
15505 /* 60 */ NULL
, NULL
, NULL
, NULL
,
15506 /* 64 */ NULL
, NULL
, NULL
, NULL
,
15507 /* 68 */ NULL
, NULL
, NULL
, NULL
,
15508 /* 6C */ NULL
, NULL
, NULL
, NULL
,
15509 /* 70 */ NULL
, NULL
, NULL
, NULL
,
15510 /* 74 */ NULL
, NULL
, NULL
, NULL
,
15511 /* 78 */ NULL
, NULL
, NULL
, NULL
,
15512 /* 7C */ NULL
, NULL
, NULL
, NULL
,
15513 /* 80 */ NULL
, NULL
, NULL
, NULL
,
15514 /* 84 */ NULL
, NULL
, NULL
, NULL
,
15515 /* 88 */ NULL
, NULL
, "pfnacc", NULL
,
15516 /* 8C */ NULL
, NULL
, "pfpnacc", NULL
,
15517 /* 90 */ "pfcmpge", NULL
, NULL
, NULL
,
15518 /* 94 */ "pfmin", NULL
, "pfrcp", "pfrsqrt",
15519 /* 98 */ NULL
, NULL
, "pfsub", NULL
,
15520 /* 9C */ NULL
, NULL
, "pfadd", NULL
,
15521 /* A0 */ "pfcmpgt", NULL
, NULL
, NULL
,
15522 /* A4 */ "pfmax", NULL
, "pfrcpit1", "pfrsqit1",
15523 /* A8 */ NULL
, NULL
, "pfsubr", NULL
,
15524 /* AC */ NULL
, NULL
, "pfacc", NULL
,
15525 /* B0 */ "pfcmpeq", NULL
, NULL
, NULL
,
15526 /* B4 */ "pfmul", NULL
, "pfrcpit2", "pmulhrw",
15527 /* B8 */ NULL
, NULL
, NULL
, "pswapd",
15528 /* BC */ NULL
, NULL
, NULL
, "pavgusb",
15529 /* C0 */ NULL
, NULL
, NULL
, NULL
,
15530 /* C4 */ NULL
, NULL
, NULL
, NULL
,
15531 /* C8 */ NULL
, NULL
, NULL
, NULL
,
15532 /* CC */ NULL
, NULL
, NULL
, NULL
,
15533 /* D0 */ NULL
, NULL
, NULL
, NULL
,
15534 /* D4 */ NULL
, NULL
, NULL
, NULL
,
15535 /* D8 */ NULL
, NULL
, NULL
, NULL
,
15536 /* DC */ NULL
, NULL
, NULL
, NULL
,
15537 /* E0 */ NULL
, NULL
, NULL
, NULL
,
15538 /* E4 */ NULL
, NULL
, NULL
, NULL
,
15539 /* E8 */ NULL
, NULL
, NULL
, NULL
,
15540 /* EC */ NULL
, NULL
, NULL
, NULL
,
15541 /* F0 */ NULL
, NULL
, NULL
, NULL
,
15542 /* F4 */ NULL
, NULL
, NULL
, NULL
,
15543 /* F8 */ NULL
, NULL
, NULL
, NULL
,
15544 /* FC */ NULL
, NULL
, NULL
, NULL
,
15548 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15550 const char *mnemonic
;
15552 FETCH_DATA (the_info
, codep
+ 1);
15553 /* AMD 3DNow! instructions are specified by an opcode suffix in the
15554 place where an 8-bit immediate would normally go. ie. the last
15555 byte of the instruction. */
15556 obufp
= mnemonicendp
;
15557 mnemonic
= Suffix3DNow
[*codep
++ & 0xff];
15559 oappend (mnemonic
);
15562 /* Since a variable sized modrm/sib chunk is between the start
15563 of the opcode (0x0f0f) and the opcode suffix, we need to do
15564 all the modrm processing first, and don't know until now that
15565 we have a bad opcode. This necessitates some cleaning up. */
15566 op_out
[0][0] = '\0';
15567 op_out
[1][0] = '\0';
15570 mnemonicendp
= obufp
;
15573 static struct op simd_cmp_op
[] =
15575 { STRING_COMMA_LEN ("eq") },
15576 { STRING_COMMA_LEN ("lt") },
15577 { STRING_COMMA_LEN ("le") },
15578 { STRING_COMMA_LEN ("unord") },
15579 { STRING_COMMA_LEN ("neq") },
15580 { STRING_COMMA_LEN ("nlt") },
15581 { STRING_COMMA_LEN ("nle") },
15582 { STRING_COMMA_LEN ("ord") }
15586 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15588 unsigned int cmp_type
;
15590 FETCH_DATA (the_info
, codep
+ 1);
15591 cmp_type
= *codep
++ & 0xff;
15592 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
))
15595 char *p
= mnemonicendp
- 2;
15599 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
15600 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
15604 /* We have a reserved extension byte. Output it directly. */
15605 scratchbuf
[0] = '$';
15606 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
15607 oappend_maybe_intel (scratchbuf
);
15608 scratchbuf
[0] = '\0';
15613 OP_Mwait (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
15615 /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx */
15618 strcpy (op_out
[0], names32
[0]);
15619 strcpy (op_out
[1], names32
[1]);
15620 if (bytemode
== eBX_reg
)
15621 strcpy (op_out
[2], names32
[3]);
15622 two_source_ops
= 1;
15624 /* Skip mod/rm byte. */
15630 OP_Monitor (int bytemode ATTRIBUTE_UNUSED
,
15631 int sizeflag ATTRIBUTE_UNUSED
)
15633 /* monitor %{e,r,}ax,%ecx,%edx" */
15636 const char **names
= (address_mode
== mode_64bit
15637 ? names64
: names32
);
15639 if (prefixes
& PREFIX_ADDR
)
15641 /* Remove "addr16/addr32". */
15642 all_prefixes
[last_addr_prefix
] = 0;
15643 names
= (address_mode
!= mode_32bit
15644 ? names32
: names16
);
15645 used_prefixes
|= PREFIX_ADDR
;
15647 else if (address_mode
== mode_16bit
)
15649 strcpy (op_out
[0], names
[0]);
15650 strcpy (op_out
[1], names32
[1]);
15651 strcpy (op_out
[2], names32
[2]);
15652 two_source_ops
= 1;
15654 /* Skip mod/rm byte. */
15662 /* Throw away prefixes and 1st. opcode byte. */
15663 codep
= insn_codep
+ 1;
15668 REP_Fixup (int bytemode
, int sizeflag
)
15670 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
15672 if (prefixes
& PREFIX_REPZ
)
15673 all_prefixes
[last_repz_prefix
] = REP_PREFIX
;
15680 OP_IMREG (bytemode
, sizeflag
);
15683 OP_ESreg (bytemode
, sizeflag
);
15686 OP_DSreg (bytemode
, sizeflag
);
15695 SEP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15697 if ( isa64
!= amd64
)
15702 mnemonicendp
= obufp
;
15706 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
15710 BND_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15712 if (prefixes
& PREFIX_REPNZ
)
15713 all_prefixes
[last_repnz_prefix
] = BND_PREFIX
;
15716 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
15720 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED
,
15721 int sizeflag ATTRIBUTE_UNUSED
)
15723 if (active_seg_prefix
== PREFIX_DS
15724 && (address_mode
!= mode_64bit
|| last_data_prefix
< 0))
15726 /* NOTRACK prefix is only valid on indirect branch instructions.
15727 NB: DATA prefix is unsupported for Intel64. */
15728 active_seg_prefix
= 0;
15729 all_prefixes
[last_seg_prefix
] = NOTRACK_PREFIX
;
15733 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
15734 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
15738 HLE_Fixup1 (int bytemode
, int sizeflag
)
15741 && (prefixes
& PREFIX_LOCK
) != 0)
15743 if (prefixes
& PREFIX_REPZ
)
15744 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
15745 if (prefixes
& PREFIX_REPNZ
)
15746 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
15749 OP_E (bytemode
, sizeflag
);
15752 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
15753 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
15757 HLE_Fixup2 (int bytemode
, int sizeflag
)
15759 if (modrm
.mod
!= 3)
15761 if (prefixes
& PREFIX_REPZ
)
15762 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
15763 if (prefixes
& PREFIX_REPNZ
)
15764 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
15767 OP_E (bytemode
, sizeflag
);
15770 /* Similar to OP_E. But the 0xf3 prefixes should be displayed as
15771 "xrelease" for memory operand. No check for LOCK prefix. */
15774 HLE_Fixup3 (int bytemode
, int sizeflag
)
15777 && last_repz_prefix
> last_repnz_prefix
15778 && (prefixes
& PREFIX_REPZ
) != 0)
15779 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
15781 OP_E (bytemode
, sizeflag
);
15785 CMPXCHG8B_Fixup (int bytemode
, int sizeflag
)
15790 /* Change cmpxchg8b to cmpxchg16b. */
15791 char *p
= mnemonicendp
- 2;
15792 mnemonicendp
= stpcpy (p
, "16b");
15795 else if ((prefixes
& PREFIX_LOCK
) != 0)
15797 if (prefixes
& PREFIX_REPZ
)
15798 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
15799 if (prefixes
& PREFIX_REPNZ
)
15800 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
15803 OP_M (bytemode
, sizeflag
);
15807 XMM_Fixup (int reg
, int sizeflag ATTRIBUTE_UNUSED
)
15809 const char **names
;
15813 switch (vex
.length
)
15827 oappend (names
[reg
]);
15831 CRC32_Fixup (int bytemode
, int sizeflag
)
15833 /* Add proper suffix to "crc32". */
15834 char *p
= mnemonicendp
;
15853 if (sizeflag
& DFLAG
)
15857 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15861 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15868 if (modrm
.mod
== 3)
15872 /* Skip mod/rm byte. */
15877 add
= (rex
& REX_B
) ? 8 : 0;
15878 if (bytemode
== b_mode
)
15882 oappend (names8rex
[modrm
.rm
+ add
]);
15884 oappend (names8
[modrm
.rm
+ add
]);
15890 oappend (names64
[modrm
.rm
+ add
]);
15891 else if ((prefixes
& PREFIX_DATA
))
15892 oappend (names16
[modrm
.rm
+ add
]);
15894 oappend (names32
[modrm
.rm
+ add
]);
15898 OP_E (bytemode
, sizeflag
);
15902 FXSAVE_Fixup (int bytemode
, int sizeflag
)
15904 /* Add proper suffix to "fxsave" and "fxrstor". */
15908 char *p
= mnemonicendp
;
15914 OP_M (bytemode
, sizeflag
);
15918 PCMPESTR_Fixup (int bytemode
, int sizeflag
)
15920 /* Add proper suffix to "{,v}pcmpestr{i,m}". */
15923 char *p
= mnemonicendp
;
15928 else if (sizeflag
& SUFFIX_ALWAYS
)
15935 OP_EX (bytemode
, sizeflag
);
15938 /* Display the destination register operand for instructions with
15942 OP_VEX (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
15945 const char **names
;
15953 reg
= vex
.register_specifier
;
15954 vex
.register_specifier
= 0;
15955 if (address_mode
!= mode_64bit
)
15957 else if (vex
.evex
&& !vex
.v
)
15960 if (bytemode
== vex_scalar_mode
)
15962 oappend (names_xmm
[reg
]);
15966 switch (vex
.length
)
15973 case vex_vsib_q_w_dq_mode
:
15974 case vex_vsib_q_w_d_mode
:
15990 names
= names_mask
;
16004 case vex_vsib_q_w_dq_mode
:
16005 case vex_vsib_q_w_d_mode
:
16006 names
= vex
.w
? names_ymm
: names_xmm
;
16015 names
= names_mask
;
16018 /* See PR binutils/20893 for a reproducer. */
16030 oappend (names
[reg
]);
16033 /* Get the VEX immediate byte without moving codep. */
16035 static unsigned char
16036 get_vex_imm8 (int sizeflag
, int opnum
)
16038 int bytes_before_imm
= 0;
16040 if (modrm
.mod
!= 3)
16042 /* There are SIB/displacement bytes. */
16043 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
16045 /* 32/64 bit address mode */
16046 int base
= modrm
.rm
;
16048 /* Check SIB byte. */
16051 FETCH_DATA (the_info
, codep
+ 1);
16053 /* When decoding the third source, don't increase
16054 bytes_before_imm as this has already been incremented
16055 by one in OP_E_memory while decoding the second
16058 bytes_before_imm
++;
16061 /* Don't increase bytes_before_imm when decoding the third source,
16062 it has already been incremented by OP_E_memory while decoding
16063 the second source operand. */
16069 /* When modrm.rm == 5 or modrm.rm == 4 and base in
16070 SIB == 5, there is a 4 byte displacement. */
16072 /* No displacement. */
16074 /* Fall through. */
16076 /* 4 byte displacement. */
16077 bytes_before_imm
+= 4;
16080 /* 1 byte displacement. */
16081 bytes_before_imm
++;
16088 /* 16 bit address mode */
16089 /* Don't increase bytes_before_imm when decoding the third source,
16090 it has already been incremented by OP_E_memory while decoding
16091 the second source operand. */
16097 /* When modrm.rm == 6, there is a 2 byte displacement. */
16099 /* No displacement. */
16101 /* Fall through. */
16103 /* 2 byte displacement. */
16104 bytes_before_imm
+= 2;
16107 /* 1 byte displacement: when decoding the third source,
16108 don't increase bytes_before_imm as this has already
16109 been incremented by one in OP_E_memory while decoding
16110 the second source operand. */
16112 bytes_before_imm
++;
16120 FETCH_DATA (the_info
, codep
+ bytes_before_imm
+ 1);
16121 return codep
[bytes_before_imm
];
16125 OP_EX_VexReg (int bytemode
, int sizeflag
, int reg
)
16127 const char **names
;
16129 if (reg
== -1 && modrm
.mod
!= 3)
16131 OP_E_memory (bytemode
, sizeflag
);
16143 if (address_mode
!= mode_64bit
)
16147 switch (vex
.length
)
16158 oappend (names
[reg
]);
16162 OP_EX_VexImmW (int bytemode
, int sizeflag
)
16165 static unsigned char vex_imm8
;
16167 if (vex_w_done
== 0)
16171 /* Skip mod/rm byte. */
16175 vex_imm8
= get_vex_imm8 (sizeflag
, 0);
16178 reg
= vex_imm8
>> 4;
16180 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
16182 else if (vex_w_done
== 1)
16187 reg
= vex_imm8
>> 4;
16189 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
16193 /* Output the imm8 directly. */
16194 scratchbuf
[0] = '$';
16195 print_operand_value (scratchbuf
+ 1, 1, vex_imm8
& 0xf);
16196 oappend_maybe_intel (scratchbuf
);
16197 scratchbuf
[0] = '\0';
16203 OP_Vex_2src (int bytemode
, int sizeflag
)
16205 if (modrm
.mod
== 3)
16207 int reg
= modrm
.rm
;
16211 oappend (names_xmm
[reg
]);
16216 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
16218 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
16219 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16221 OP_E (bytemode
, sizeflag
);
16226 OP_Vex_2src_1 (int bytemode
, int sizeflag
)
16228 if (modrm
.mod
== 3)
16230 /* Skip mod/rm byte. */
16237 unsigned int reg
= vex
.register_specifier
;
16238 vex
.register_specifier
= 0;
16240 if (address_mode
!= mode_64bit
)
16242 oappend (names_xmm
[reg
]);
16245 OP_Vex_2src (bytemode
, sizeflag
);
16249 OP_Vex_2src_2 (int bytemode
, int sizeflag
)
16252 OP_Vex_2src (bytemode
, sizeflag
);
16255 unsigned int reg
= vex
.register_specifier
;
16256 vex
.register_specifier
= 0;
16258 if (address_mode
!= mode_64bit
)
16260 oappend (names_xmm
[reg
]);
16265 OP_EX_VexW (int bytemode
, int sizeflag
)
16271 /* Skip mod/rm byte. */
16276 reg
= get_vex_imm8 (sizeflag
, 0) >> 4;
16281 reg
= get_vex_imm8 (sizeflag
, 1) >> 4;
16284 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
16292 OP_REG_VexI4 (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16295 const char **names
;
16297 FETCH_DATA (the_info
, codep
+ 1);
16300 if (bytemode
!= x_mode
)
16304 if (address_mode
!= mode_64bit
)
16307 switch (vex
.length
)
16318 oappend (names
[reg
]);
16322 OP_XMM_VexW (int bytemode
, int sizeflag
)
16324 /* Turn off the REX.W bit since it is used for swapping operands
16327 OP_XMM (bytemode
, sizeflag
);
16331 OP_EX_Vex (int bytemode
, int sizeflag
)
16333 if (modrm
.mod
!= 3)
16335 OP_EX (bytemode
, sizeflag
);
16339 OP_XMM_Vex (int bytemode
, int sizeflag
)
16341 if (modrm
.mod
!= 3)
16343 OP_XMM (bytemode
, sizeflag
);
16346 static struct op vex_cmp_op
[] =
16348 { STRING_COMMA_LEN ("eq") },
16349 { STRING_COMMA_LEN ("lt") },
16350 { STRING_COMMA_LEN ("le") },
16351 { STRING_COMMA_LEN ("unord") },
16352 { STRING_COMMA_LEN ("neq") },
16353 { STRING_COMMA_LEN ("nlt") },
16354 { STRING_COMMA_LEN ("nle") },
16355 { STRING_COMMA_LEN ("ord") },
16356 { STRING_COMMA_LEN ("eq_uq") },
16357 { STRING_COMMA_LEN ("nge") },
16358 { STRING_COMMA_LEN ("ngt") },
16359 { STRING_COMMA_LEN ("false") },
16360 { STRING_COMMA_LEN ("neq_oq") },
16361 { STRING_COMMA_LEN ("ge") },
16362 { STRING_COMMA_LEN ("gt") },
16363 { STRING_COMMA_LEN ("true") },
16364 { STRING_COMMA_LEN ("eq_os") },
16365 { STRING_COMMA_LEN ("lt_oq") },
16366 { STRING_COMMA_LEN ("le_oq") },
16367 { STRING_COMMA_LEN ("unord_s") },
16368 { STRING_COMMA_LEN ("neq_us") },
16369 { STRING_COMMA_LEN ("nlt_uq") },
16370 { STRING_COMMA_LEN ("nle_uq") },
16371 { STRING_COMMA_LEN ("ord_s") },
16372 { STRING_COMMA_LEN ("eq_us") },
16373 { STRING_COMMA_LEN ("nge_uq") },
16374 { STRING_COMMA_LEN ("ngt_uq") },
16375 { STRING_COMMA_LEN ("false_os") },
16376 { STRING_COMMA_LEN ("neq_os") },
16377 { STRING_COMMA_LEN ("ge_oq") },
16378 { STRING_COMMA_LEN ("gt_oq") },
16379 { STRING_COMMA_LEN ("true_us") },
16383 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16385 unsigned int cmp_type
;
16387 FETCH_DATA (the_info
, codep
+ 1);
16388 cmp_type
= *codep
++ & 0xff;
16389 if (cmp_type
< ARRAY_SIZE (vex_cmp_op
))
16392 char *p
= mnemonicendp
- 2;
16396 sprintf (p
, "%s%s", vex_cmp_op
[cmp_type
].name
, suffix
);
16397 mnemonicendp
+= vex_cmp_op
[cmp_type
].len
;
16401 /* We have a reserved extension byte. Output it directly. */
16402 scratchbuf
[0] = '$';
16403 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
16404 oappend_maybe_intel (scratchbuf
);
16405 scratchbuf
[0] = '\0';
16410 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
,
16411 int sizeflag ATTRIBUTE_UNUSED
)
16413 unsigned int cmp_type
;
16418 FETCH_DATA (the_info
, codep
+ 1);
16419 cmp_type
= *codep
++ & 0xff;
16420 /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
16421 If it's the case, print suffix, otherwise - print the immediate. */
16422 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
)
16427 char *p
= mnemonicendp
- 2;
16429 /* vpcmp* can have both one- and two-lettered suffix. */
16443 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
16444 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
16448 /* We have a reserved extension byte. Output it directly. */
16449 scratchbuf
[0] = '$';
16450 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
16451 oappend_maybe_intel (scratchbuf
);
16452 scratchbuf
[0] = '\0';
16456 static const struct op xop_cmp_op
[] =
16458 { STRING_COMMA_LEN ("lt") },
16459 { STRING_COMMA_LEN ("le") },
16460 { STRING_COMMA_LEN ("gt") },
16461 { STRING_COMMA_LEN ("ge") },
16462 { STRING_COMMA_LEN ("eq") },
16463 { STRING_COMMA_LEN ("neq") },
16464 { STRING_COMMA_LEN ("false") },
16465 { STRING_COMMA_LEN ("true") }
16469 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED
,
16470 int sizeflag ATTRIBUTE_UNUSED
)
16472 unsigned int cmp_type
;
16474 FETCH_DATA (the_info
, codep
+ 1);
16475 cmp_type
= *codep
++ & 0xff;
16476 if (cmp_type
< ARRAY_SIZE (xop_cmp_op
))
16479 char *p
= mnemonicendp
- 2;
16481 /* vpcom* can have both one- and two-lettered suffix. */
16495 sprintf (p
, "%s%s", xop_cmp_op
[cmp_type
].name
, suffix
);
16496 mnemonicendp
+= xop_cmp_op
[cmp_type
].len
;
16500 /* We have a reserved extension byte. Output it directly. */
16501 scratchbuf
[0] = '$';
16502 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
16503 oappend_maybe_intel (scratchbuf
);
16504 scratchbuf
[0] = '\0';
16508 static const struct op pclmul_op
[] =
16510 { STRING_COMMA_LEN ("lql") },
16511 { STRING_COMMA_LEN ("hql") },
16512 { STRING_COMMA_LEN ("lqh") },
16513 { STRING_COMMA_LEN ("hqh") }
16517 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED
,
16518 int sizeflag ATTRIBUTE_UNUSED
)
16520 unsigned int pclmul_type
;
16522 FETCH_DATA (the_info
, codep
+ 1);
16523 pclmul_type
= *codep
++ & 0xff;
16524 switch (pclmul_type
)
16535 if (pclmul_type
< ARRAY_SIZE (pclmul_op
))
16538 char *p
= mnemonicendp
- 3;
16543 sprintf (p
, "%s%s", pclmul_op
[pclmul_type
].name
, suffix
);
16544 mnemonicendp
+= pclmul_op
[pclmul_type
].len
;
16548 /* We have a reserved extension byte. Output it directly. */
16549 scratchbuf
[0] = '$';
16550 print_operand_value (scratchbuf
+ 1, 1, pclmul_type
);
16551 oappend_maybe_intel (scratchbuf
);
16552 scratchbuf
[0] = '\0';
16557 MOVBE_Fixup (int bytemode
, int sizeflag
)
16559 /* Add proper suffix to "movbe". */
16560 char *p
= mnemonicendp
;
16569 if (sizeflag
& SUFFIX_ALWAYS
)
16575 if (sizeflag
& DFLAG
)
16579 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16584 oappend (INTERNAL_DISASSEMBLER_ERROR
);
16591 OP_M (bytemode
, sizeflag
);
16595 MOVSXD_Fixup (int bytemode
, int sizeflag
)
16597 /* Add proper suffix to "movsxd". */
16598 char *p
= mnemonicendp
;
16623 oappend (INTERNAL_DISASSEMBLER_ERROR
);
16630 OP_E (bytemode
, sizeflag
);
16634 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16637 const char **names
;
16639 /* Skip mod/rm byte. */
16653 oappend (names
[reg
]);
16657 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16659 const char **names
;
16660 unsigned int reg
= vex
.register_specifier
;
16661 vex
.register_specifier
= 0;
16668 if (address_mode
!= mode_64bit
)
16670 oappend (names
[reg
]);
16674 OP_Mask (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16677 || (bytemode
!= mask_mode
&& bytemode
!= mask_bd_mode
))
16681 if ((rex
& REX_R
) != 0 || !vex
.r
)
16687 oappend (names_mask
[modrm
.reg
]);
16691 OP_Rounding (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16694 || (bytemode
!= evex_rounding_mode
16695 && bytemode
!= evex_rounding_64_mode
16696 && bytemode
!= evex_sae_mode
))
16698 if (modrm
.mod
== 3 && vex
.b
)
16701 case evex_rounding_64_mode
:
16702 if (address_mode
!= mode_64bit
)
16707 /* Fall through. */
16708 case evex_rounding_mode
:
16709 oappend (names_rounding
[vex
.ll
]);
16711 case evex_sae_mode
: