opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2018 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "disassemble.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40
  41 #include <setjmp.h>
  42
  43 static int print_insn (bfd_vma, disassemble_info *);
  44 static void dofloat (int);
  45 static void OP_ST (int, int);
  46 static void OP_STi (int, int);
  47 static int putop (const char *, int);
  48 static void oappend (const char *);
  49 static void append_seg (void);
  50 static void OP_indirE (int, int);
  51 static void print_operand_value (char *, int, bfd_vma);
  52 static void OP_E_register (int, int);
  53 static void OP_E_memory (int, int);
  54 static void print_displacement (char *, bfd_vma);
  55 static void OP_E (int, int);
  56 static void OP_G (int, int);
  57 static bfd_vma get64 (void);
  58 static bfd_signed_vma get32 (void);
  59 static bfd_signed_vma get32s (void);
  60 static int get16 (void);
  61 static void set_op (bfd_vma, int);
  62 static void OP_Skip_MODRM (int, int);
  63 static void OP_REG (int, int);
  64 static void OP_IMREG (int, int);
  65 static void OP_I (int, int);
  66 static void OP_I64 (int, int);
  67 static void OP_sI (int, int);
  68 static void OP_J (int, int);
  69 static void OP_SEG (int, int);
  70 static void OP_DIR (int, int);
  71 static void OP_OFF (int, int);
  72 static void OP_OFF64 (int, int);
  73 static void ptr_reg (int, int);
  74 static void OP_ESreg (int, int);
  75 static void OP_DSreg (int, int);
  76 static void OP_C (int, int);
  77 static void OP_D (int, int);
  78 static void OP_T (int, int);
  79 static void OP_R (int, int);
  80 static void OP_MMX (int, int);
  81 static void OP_XMM (int, int);
  82 static void OP_EM (int, int);
  83 static void OP_EX (int, int);
  84 static void OP_EMC (int,int);
  85 static void OP_MXC (int,int);
  86 static void OP_MS (int, int);
  87 static void OP_XS (int, int);
  88 static void OP_M (int, int);
  89 static void OP_VEX (int, int);
  90 static void OP_EX_Vex (int, int);
  91 static void OP_EX_VexW (int, int);
  92 static void OP_EX_VexImmW (int, int);
  93 static void OP_XMM_Vex (int, int);
  94 static void OP_XMM_VexW (int, int);
  95 static void OP_Rounding (int, int);
  96 static void OP_REG_VexI4 (int, int);
  97 static void PCLMUL_Fixup (int, int);
  98 static void VZERO_Fixup (int, int);
  99 static void VCMP_Fixup (int, int);
 100 static void VPCMP_Fixup (int, int);
 101 static void VPCOM_Fixup (int, int);
 102 static void OP_0f07 (int, int);
 103 static void OP_Monitor (int, int);
 104 static void OP_Mwait (int, int);
 105 static void OP_Mwaitx (int, int);
 106 static void NOP_Fixup1 (int, int);
 107 static void NOP_Fixup2 (int, int);
 108 static void OP_3DNowSuffix (int, int);
 109 static void CMP_Fixup (int, int);
 110 static void BadOp (void);
 111 static void REP_Fixup (int, int);
 112 static void BND_Fixup (int, int);
 113 static void NOTRACK_Fixup (int, int);
 114 static void HLE_Fixup1 (int, int);
 115 static void HLE_Fixup2 (int, int);
 116 static void HLE_Fixup3 (int, int);
 117 static void CMPXCHG8B_Fixup (int, int);
 118 static void XMM_Fixup (int, int);
 119 static void CRC32_Fixup (int, int);
 120 static void FXSAVE_Fixup (int, int);
 121 static void PCMPESTR_Fixup (int, int);
 122 static void OP_LWPCB_E (int, int);
 123 static void OP_LWP_E (int, int);
 124 static void OP_Vex_2src_1 (int, int);
 125 static void OP_Vex_2src_2 (int, int);
 126
 127 static void MOVBE_Fixup (int, int);
 128
 129 static void OP_Mask (int, int);
 130
 131 struct dis_private {
 132   /* Points to first byte not fetched.  */
 133   bfd_byte *max_fetched;
 134   bfd_byte the_buffer[MAX_MNEM_SIZE];
 135   bfd_vma insn_start;
 136   int orig_sizeflag;
 137   OPCODES_SIGJMP_BUF bailout;
 138 };
 139
 140 enum address_mode
 141 {
 142   mode_16bit,
 143   mode_32bit,
 144   mode_64bit
 145 };
 146
 147 enum address_mode address_mode;
 148
 149 /* Flags for the prefixes for the current instruction.  See below.  */
 150 static int prefixes;
 151
 152 /* REX prefix the current instruction.  See below.  */
 153 static int rex;
 154 /* Bits of REX we've already used.  */
 155 static int rex_used;
 156 /* REX bits in original REX prefix ignored.  */
 157 static int rex_ignored;
 158 /* Mark parts used in the REX prefix.  When we are testing for
 159    empty prefix (for 8bit register REX extension), just mask it
 160    out.  Otherwise test for REX bit is excuse for existence of REX
 161    only in case value is nonzero.  */
 162 #define USED_REX(value)                                 \
 163   {                                                     \
 164     if (value)                                          \
 165       {                                                 \
 166         if ((rex & value))                              \
 167           rex_used |= (value) | REX_OPCODE;             \
 168       }                                                 \
 169     else                                                \
 170       rex_used |= REX_OPCODE;                           \
 171   }
 172
 173 /* Flags for prefixes which we somehow handled when printing the
 174    current instruction.  */
 175 static int used_prefixes;
 176
 177 /* Flags stored in PREFIXES.  */
 178 #define PREFIX_REPZ 1
 179 #define PREFIX_REPNZ 2
 180 #define PREFIX_LOCK 4
 181 #define PREFIX_CS 8
 182 #define PREFIX_SS 0x10
 183 #define PREFIX_DS 0x20
 184 #define PREFIX_ES 0x40
 185 #define PREFIX_FS 0x80
 186 #define PREFIX_GS 0x100
 187 #define PREFIX_DATA 0x200
 188 #define PREFIX_ADDR 0x400
 189 #define PREFIX_FWAIT 0x800
 190
 191 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 192    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 193    on error.  */
 194 #define FETCH_DATA(info, addr) \
 195   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 196    ? 1 : fetch_data ((info), (addr)))
 197
 198 static int
 199 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 200 {
 201   int status;
 202   struct dis_private *priv = (struct dis_private *) info->private_data;
 203   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 204
 205   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 206     status = (*info->read_memory_func) (start,
 207                                         priv->max_fetched,
 208                                         addr - priv->max_fetched,
 209                                         info);
 210   else
 211     status = -1;
 212   if (status != 0)
 213     {
 214       /* If we did manage to read at least one byte, then
 215          print_insn_i386 will do something sensible.  Otherwise, print
 216          an error.  We do that here because this is where we know
 217          STATUS.  */
 218       if (priv->max_fetched == priv->the_buffer)
 219         (*info->memory_error_func) (status, start, info);
 220       OPCODES_SIGLONGJMP (priv->bailout, 1);
 221     }
 222   else
 223     priv->max_fetched = addr;
 224   return 1;
 225 }
 226
 227 /* Possible values for prefix requirement.  */
 228 #define PREFIX_IGNORED_SHIFT    16
 229 #define PREFIX_IGNORED_REPZ     (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
 230 #define PREFIX_IGNORED_REPNZ    (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
 231 #define PREFIX_IGNORED_DATA     (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
 232 #define PREFIX_IGNORED_ADDR     (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
 233 #define PREFIX_IGNORED_LOCK     (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
 234
 235 /* Opcode prefixes.  */
 236 #define PREFIX_OPCODE           (PREFIX_REPZ \
 237                                  | PREFIX_REPNZ \
 238                                  | PREFIX_DATA)
 239
 240 /* Prefixes ignored.  */
 241 #define PREFIX_IGNORED          (PREFIX_IGNORED_REPZ \
 242                                  | PREFIX_IGNORED_REPNZ \
 243                                  | PREFIX_IGNORED_DATA)
 244
 245 #define XX { NULL, 0 }
 246 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
 247
 248 #define Eb { OP_E, b_mode }
 249 #define Ebnd { OP_E, bnd_mode }
 250 #define EbS { OP_E, b_swap_mode }
 251 #define EbndS { OP_E, bnd_swap_mode }
 252 #define Ev { OP_E, v_mode }
 253 #define Eva { OP_E, va_mode }
 254 #define Ev_bnd { OP_E, v_bnd_mode }
 255 #define EvS { OP_E, v_swap_mode }
 256 #define Ed { OP_E, d_mode }
 257 #define Edq { OP_E, dq_mode }
 258 #define Edqw { OP_E, dqw_mode }
 259 #define Edqb { OP_E, dqb_mode }
 260 #define Edb { OP_E, db_mode }
 261 #define Edw { OP_E, dw_mode }
 262 #define Edqd { OP_E, dqd_mode }
 263 #define Eq { OP_E, q_mode }
 264 #define indirEv { OP_indirE, indir_v_mode }
 265 #define indirEp { OP_indirE, f_mode }
 266 #define stackEv { OP_E, stack_v_mode }
 267 #define Em { OP_E, m_mode }
 268 #define Ew { OP_E, w_mode }
 269 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 270 #define Ma { OP_M, a_mode }
 271 #define Mb { OP_M, b_mode }
 272 #define Md { OP_M, d_mode }
 273 #define Mo { OP_M, o_mode }
 274 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 275 #define Mq { OP_M, q_mode }
 276 #define Mx { OP_M, x_mode }
 277 #define Mxmm { OP_M, xmm_mode }
 278 #define Gb { OP_G, b_mode }
 279 #define Gbnd { OP_G, bnd_mode }
 280 #define Gv { OP_G, v_mode }
 281 #define Gd { OP_G, d_mode }
 282 #define Gdq { OP_G, dq_mode }
 283 #define Gm { OP_G, m_mode }
 284 #define Gw { OP_G, w_mode }
 285 #define Rd { OP_R, d_mode }
 286 #define Rdq { OP_R, dq_mode }
 287 #define Rm { OP_R, m_mode }
 288 #define Ib { OP_I, b_mode }
 289 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 290 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 291 #define Iv { OP_I, v_mode }
 292 #define sIv { OP_sI, v_mode }
 293 #define Iq { OP_I, q_mode }
 294 #define Iv64 { OP_I64, v_mode }
 295 #define Iw { OP_I, w_mode }
 296 #define I1 { OP_I, const_1_mode }
 297 #define Jb { OP_J, b_mode }
 298 #define Jv { OP_J, v_mode }
 299 #define Cm { OP_C, m_mode }
 300 #define Dm { OP_D, m_mode }
 301 #define Td { OP_T, d_mode }
 302 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 303
 304 #define RMeAX { OP_REG, eAX_reg }
 305 #define RMeBX { OP_REG, eBX_reg }
 306 #define RMeCX { OP_REG, eCX_reg }
 307 #define RMeDX { OP_REG, eDX_reg }
 308 #define RMeSP { OP_REG, eSP_reg }
 309 #define RMeBP { OP_REG, eBP_reg }
 310 #define RMeSI { OP_REG, eSI_reg }
 311 #define RMeDI { OP_REG, eDI_reg }
 312 #define RMrAX { OP_REG, rAX_reg }
 313 #define RMrBX { OP_REG, rBX_reg }
 314 #define RMrCX { OP_REG, rCX_reg }
 315 #define RMrDX { OP_REG, rDX_reg }
 316 #define RMrSP { OP_REG, rSP_reg }
 317 #define RMrBP { OP_REG, rBP_reg }
 318 #define RMrSI { OP_REG, rSI_reg }
 319 #define RMrDI { OP_REG, rDI_reg }
 320 #define RMAL { OP_REG, al_reg }
 321 #define RMCL { OP_REG, cl_reg }
 322 #define RMDL { OP_REG, dl_reg }
 323 #define RMBL { OP_REG, bl_reg }
 324 #define RMAH { OP_REG, ah_reg }
 325 #define RMCH { OP_REG, ch_reg }
 326 #define RMDH { OP_REG, dh_reg }
 327 #define RMBH { OP_REG, bh_reg }
 328 #define RMAX { OP_REG, ax_reg }
 329 #define RMDX { OP_REG, dx_reg }
 330
 331 #define eAX { OP_IMREG, eAX_reg }
 332 #define eBX { OP_IMREG, eBX_reg }
 333 #define eCX { OP_IMREG, eCX_reg }
 334 #define eDX { OP_IMREG, eDX_reg }
 335 #define eSP { OP_IMREG, eSP_reg }
 336 #define eBP { OP_IMREG, eBP_reg }
 337 #define eSI { OP_IMREG, eSI_reg }
 338 #define eDI { OP_IMREG, eDI_reg }
 339 #define AL { OP_IMREG, al_reg }
 340 #define CL { OP_IMREG, cl_reg }
 341 #define DL { OP_IMREG, dl_reg }
 342 #define BL { OP_IMREG, bl_reg }
 343 #define AH { OP_IMREG, ah_reg }
 344 #define CH { OP_IMREG, ch_reg }
 345 #define DH { OP_IMREG, dh_reg }
 346 #define BH { OP_IMREG, bh_reg }
 347 #define AX { OP_IMREG, ax_reg }
 348 #define DX { OP_IMREG, dx_reg }
 349 #define zAX { OP_IMREG, z_mode_ax_reg }
 350 #define indirDX { OP_IMREG, indir_dx_reg }
 351
 352 #define Sw { OP_SEG, w_mode }
 353 #define Sv { OP_SEG, v_mode }
 354 #define Ap { OP_DIR, 0 }
 355 #define Ob { OP_OFF64, b_mode }
 356 #define Ov { OP_OFF64, v_mode }
 357 #define Xb { OP_DSreg, eSI_reg }
 358 #define Xv { OP_DSreg, eSI_reg }
 359 #define Xz { OP_DSreg, eSI_reg }
 360 #define Yb { OP_ESreg, eDI_reg }
 361 #define Yv { OP_ESreg, eDI_reg }
 362 #define DSBX { OP_DSreg, eBX_reg }
 363
 364 #define es { OP_REG, es_reg }
 365 #define ss { OP_REG, ss_reg }
 366 #define cs { OP_REG, cs_reg }
 367 #define ds { OP_REG, ds_reg }
 368 #define fs { OP_REG, fs_reg }
 369 #define gs { OP_REG, gs_reg }
 370
 371 #define MX { OP_MMX, 0 }
 372 #define XM { OP_XMM, 0 }
 373 #define XMScalar { OP_XMM, scalar_mode }
 374 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 375 #define XMM { OP_XMM, xmm_mode }
 376 #define XMxmmq { OP_XMM, xmmq_mode }
 377 #define EM { OP_EM, v_mode }
 378 #define EMS { OP_EM, v_swap_mode }
 379 #define EMd { OP_EM, d_mode }
 380 #define EMx { OP_EM, x_mode }
 381 #define EXbScalar { OP_EX, b_scalar_mode }
 382 #define EXw { OP_EX, w_mode }
 383 #define EXwScalar { OP_EX, w_scalar_mode }
 384 #define EXd { OP_EX, d_mode }
 385 #define EXdScalar { OP_EX, d_scalar_mode }
 386 #define EXdS { OP_EX, d_swap_mode }
 387 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
 388 #define EXq { OP_EX, q_mode }
 389 #define EXqScalar { OP_EX, q_scalar_mode }
 390 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
 391 #define EXqS { OP_EX, q_swap_mode }
 392 #define EXx { OP_EX, x_mode }
 393 #define EXxS { OP_EX, x_swap_mode }
 394 #define EXxmm { OP_EX, xmm_mode }
 395 #define EXymm { OP_EX, ymm_mode }
 396 #define EXxmmq { OP_EX, xmmq_mode }
 397 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 398 #define EXxmm_mb { OP_EX, xmm_mb_mode }
 399 #define EXxmm_mw { OP_EX, xmm_mw_mode }
 400 #define EXxmm_md { OP_EX, xmm_md_mode }
 401 #define EXxmm_mq { OP_EX, xmm_mq_mode }
 402 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
 403 #define EXxmmdw { OP_EX, xmmdw_mode }
 404 #define EXxmmqd { OP_EX, xmmqd_mode }
 405 #define EXymmq { OP_EX, ymmq_mode }
 406 #define EXVexWdq { OP_EX, vex_w_dq_mode }
 407 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 408 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 409 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 410 #define MS { OP_MS, v_mode }
 411 #define XS { OP_XS, v_mode }
 412 #define EMCq { OP_EMC, q_mode }
 413 #define MXC { OP_MXC, 0 }
 414 #define OPSUF { OP_3DNowSuffix, 0 }
 415 #define CMP { CMP_Fixup, 0 }
 416 #define XMM0 { XMM_Fixup, 0 }
 417 #define FXSAVE { FXSAVE_Fixup, 0 }
 418 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
 419 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
 420
 421 #define Vex { OP_VEX, vex_mode }
 422 #define VexScalar { OP_VEX, vex_scalar_mode }
 423 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 424 #define Vex128 { OP_VEX, vex128_mode }
 425 #define Vex256 { OP_VEX, vex256_mode }
 426 #define VexGdq { OP_VEX, dq_mode }
 427 #define EXdVex { OP_EX_Vex, d_mode }
 428 #define EXdVexS { OP_EX_Vex, d_swap_mode }
 429 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
 430 #define EXqVex { OP_EX_Vex, q_mode }
 431 #define EXqVexS { OP_EX_Vex, q_swap_mode }
 432 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
 433 #define EXVexW { OP_EX_VexW, x_mode }
 434 #define EXdVexW { OP_EX_VexW, d_mode }
 435 #define EXqVexW { OP_EX_VexW, q_mode }
 436 #define EXVexImmW { OP_EX_VexImmW, x_mode }
 437 #define XMVex { OP_XMM_Vex, 0 }
 438 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
 439 #define XMVexW { OP_XMM_VexW, 0 }
 440 #define XMVexI4 { OP_REG_VexI4, x_mode }
 441 #define PCLMUL { PCLMUL_Fixup, 0 }
 442 #define VZERO { VZERO_Fixup, 0 }
 443 #define VCMP { VCMP_Fixup, 0 }
 444 #define VPCMP { VPCMP_Fixup, 0 }
 445 #define VPCOM { VPCOM_Fixup, 0 }
 446
 447 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 448 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 449
 450 #define XMask { OP_Mask, mask_mode }
 451 #define MaskG { OP_G, mask_mode }
 452 #define MaskE { OP_E, mask_mode }
 453 #define MaskBDE { OP_E, mask_bd_mode }
 454 #define MaskR { OP_R, mask_mode }
 455 #define MaskVex { OP_VEX, mask_mode }
 456
 457 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 458 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
 459 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 460 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
 461
 462 /* Used handle "rep" prefix for string instructions.  */
 463 #define Xbr { REP_Fixup, eSI_reg }
 464 #define Xvr { REP_Fixup, eSI_reg }
 465 #define Ybr { REP_Fixup, eDI_reg }
 466 #define Yvr { REP_Fixup, eDI_reg }
 467 #define Yzr { REP_Fixup, eDI_reg }
 468 #define indirDXr { REP_Fixup, indir_dx_reg }
 469 #define ALr { REP_Fixup, al_reg }
 470 #define eAXr { REP_Fixup, eAX_reg }
 471
 472 /* Used handle HLE prefix for lockable instructions.  */
 473 #define Ebh1 { HLE_Fixup1, b_mode }
 474 #define Evh1 { HLE_Fixup1, v_mode }
 475 #define Ebh2 { HLE_Fixup2, b_mode }
 476 #define Evh2 { HLE_Fixup2, v_mode }
 477 #define Ebh3 { HLE_Fixup3, b_mode }
 478 #define Evh3 { HLE_Fixup3, v_mode }
 479
 480 #define BND { BND_Fixup, 0 }
 481 #define NOTRACK { NOTRACK_Fixup, 0 }
 482
 483 #define cond_jump_flag { NULL, cond_jump_mode }
 484 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 485
 486 /* bits in sizeflag */
 487 #define SUFFIX_ALWAYS 4
 488 #define AFLAG 2
 489 #define DFLAG 1
 490
 491 enum
 492 {
 493   /* byte operand */
 494   b_mode = 1,
 495   /* byte operand with operand swapped */
 496   b_swap_mode,
 497   /* byte operand, sign extend like 'T' suffix */
 498   b_T_mode,
 499   /* operand size depends on prefixes */
 500   v_mode,
 501   /* operand size depends on prefixes with operand swapped */
 502   v_swap_mode,
 503   /* operand size depends on address prefix */
 504   va_mode,
 505   /* word operand */
 506   w_mode,
 507   /* double word operand  */
 508   d_mode,
 509   /* double word operand with operand swapped */
 510   d_swap_mode,
 511   /* quad word operand */
 512   q_mode,
 513   /* quad word operand with operand swapped */
 514   q_swap_mode,
 515   /* ten-byte operand */
 516   t_mode,
 517   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 518      broadcast enabled.  */
 519   x_mode,
 520   /* Similar to x_mode, but with different EVEX mem shifts.  */
 521   evex_x_gscat_mode,
 522   /* Similar to x_mode, but with disabled broadcast.  */
 523   evex_x_nobcst_mode,
 524   /* Similar to x_mode, but with operands swapped and disabled broadcast
 525      in EVEX.  */
 526   x_swap_mode,
 527   /* 16-byte XMM operand */
 528   xmm_mode,
 529   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 530      memory operand (depending on vector length).  Broadcast isn't
 531      allowed.  */
 532   xmmq_mode,
 533   /* Same as xmmq_mode, but broadcast is allowed.  */
 534   evex_half_bcst_xmmq_mode,
 535   /* XMM register or byte memory operand */
 536   xmm_mb_mode,
 537   /* XMM register or word memory operand */
 538   xmm_mw_mode,
 539   /* XMM register or double word memory operand */
 540   xmm_md_mode,
 541   /* XMM register or quad word memory operand */
 542   xmm_mq_mode,
 543   /* XMM register or double/quad word memory operand, depending on
 544      VEX.W.  */
 545   xmm_mdq_mode,
 546   /* 16-byte XMM, word, double word or quad word operand.  */
 547   xmmdw_mode,
 548   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 549   xmmqd_mode,
 550   /* 32-byte YMM operand */
 551   ymm_mode,
 552   /* quad word, ymmword or zmmword memory operand.  */
 553   ymmq_mode,
 554   /* 32-byte YMM or 16-byte word operand */
 555   ymmxmm_mode,
 556   /* d_mode in 32bit, q_mode in 64bit mode.  */
 557   m_mode,
 558   /* pair of v_mode operands */
 559   a_mode,
 560   cond_jump_mode,
 561   loop_jcxz_mode,
 562   v_bnd_mode,
 563   /* operand size depends on REX prefixes.  */
 564   dq_mode,
 565   /* registers like dq_mode, memory like w_mode.  */
 566   dqw_mode,
 567   /* bounds operand */
 568   bnd_mode,
 569   /* bounds operand with operand swapped */
 570   bnd_swap_mode,
 571   /* 4- or 6-byte pointer operand */
 572   f_mode,
 573   const_1_mode,
 574   /* v_mode for indirect branch opcodes.  */
 575   indir_v_mode,
 576   /* v_mode for stack-related opcodes.  */
 577   stack_v_mode,
 578   /* non-quad operand size depends on prefixes */
 579   z_mode,
 580   /* 16-byte operand */
 581   o_mode,
 582   /* registers like dq_mode, memory like b_mode.  */
 583   dqb_mode,
 584   /* registers like d_mode, memory like b_mode.  */
 585   db_mode,
 586   /* registers like d_mode, memory like w_mode.  */
 587   dw_mode,
 588   /* registers like dq_mode, memory like d_mode.  */
 589   dqd_mode,
 590   /* normal vex mode */
 591   vex_mode,
 592   /* 128bit vex mode */
 593   vex128_mode,
 594   /* 256bit vex mode */
 595   vex256_mode,
 596   /* operand size depends on the VEX.W bit.  */
 597   vex_w_dq_mode,
 598
 599   /* Similar to vex_w_dq_mode, with VSIB dword indices.  */
 600   vex_vsib_d_w_dq_mode,
 601   /* Similar to vex_vsib_d_w_dq_mode, with smaller memory.  */
 602   vex_vsib_d_w_d_mode,
 603   /* Similar to vex_w_dq_mode, with VSIB qword indices.  */
 604   vex_vsib_q_w_dq_mode,
 605   /* Similar to vex_vsib_q_w_dq_mode, with smaller memory.  */
 606   vex_vsib_q_w_d_mode,
 607
 608   /* scalar, ignore vector length.  */
 609   scalar_mode,
 610   /* like b_mode, ignore vector length.  */
 611   b_scalar_mode,
 612   /* like w_mode, ignore vector length.  */
 613   w_scalar_mode,
 614   /* like d_mode, ignore vector length.  */
 615   d_scalar_mode,
 616   /* like d_swap_mode, ignore vector length.  */
 617   d_scalar_swap_mode,
 618   /* like q_mode, ignore vector length.  */
 619   q_scalar_mode,
 620   /* like q_swap_mode, ignore vector length.  */
 621   q_scalar_swap_mode,
 622   /* like vex_mode, ignore vector length.  */
 623   vex_scalar_mode,
 624   /* like vex_w_dq_mode, ignore vector length.  */
 625   vex_scalar_w_dq_mode,
 626
 627   /* Static rounding.  */
 628   evex_rounding_mode,
 629   /* Supress all exceptions.  */
 630   evex_sae_mode,
 631
 632   /* Mask register operand.  */
 633   mask_mode,
 634   /* Mask register operand.  */
 635   mask_bd_mode,
 636
 637   es_reg,
 638   cs_reg,
 639   ss_reg,
 640   ds_reg,
 641   fs_reg,
 642   gs_reg,
 643
 644   eAX_reg,
 645   eCX_reg,
 646   eDX_reg,
 647   eBX_reg,
 648   eSP_reg,
 649   eBP_reg,
 650   eSI_reg,
 651   eDI_reg,
 652
 653   al_reg,
 654   cl_reg,
 655   dl_reg,
 656   bl_reg,
 657   ah_reg,
 658   ch_reg,
 659   dh_reg,
 660   bh_reg,
 661
 662   ax_reg,
 663   cx_reg,
 664   dx_reg,
 665   bx_reg,
 666   sp_reg,
 667   bp_reg,
 668   si_reg,
 669   di_reg,
 670
 671   rAX_reg,
 672   rCX_reg,
 673   rDX_reg,
 674   rBX_reg,
 675   rSP_reg,
 676   rBP_reg,
 677   rSI_reg,
 678   rDI_reg,
 679
 680   z_mode_ax_reg,
 681   indir_dx_reg
 682 };
 683
 684 enum
 685 {
 686   FLOATCODE = 1,
 687   USE_REG_TABLE,
 688   USE_MOD_TABLE,
 689   USE_RM_TABLE,
 690   USE_PREFIX_TABLE,
 691   USE_X86_64_TABLE,
 692   USE_3BYTE_TABLE,
 693   USE_XOP_8F_TABLE,
 694   USE_VEX_C4_TABLE,
 695   USE_VEX_C5_TABLE,
 696   USE_VEX_LEN_TABLE,
 697   USE_VEX_W_TABLE,
 698   USE_EVEX_TABLE
 699 };
 700
 701 #define FLOAT                   NULL, { { NULL, FLOATCODE } }, 0
 702
 703 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }, 0
 704 #define DIS386_PREFIX(T, I, P)          NULL, { { NULL, (T)}, { NULL,  (I) } }, P
 705 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 706 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 707 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 708 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 709 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 710 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 711 #define THREE_BYTE_TABLE_PREFIX(I, P)   DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
 712 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 713 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 714 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 715 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 716 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 717 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 718
 719 enum
 720 {
 721   REG_80 = 0,
 722   REG_81,
 723   REG_83,
 724   REG_8F,
 725   REG_C0,
 726   REG_C1,
 727   REG_C6,
 728   REG_C7,
 729   REG_D0,
 730   REG_D1,
 731   REG_D2,
 732   REG_D3,
 733   REG_F6,
 734   REG_F7,
 735   REG_FE,
 736   REG_FF,
 737   REG_0F00,
 738   REG_0F01,
 739   REG_0F0D,
 740   REG_0F18,
 741   REG_0F1C_MOD_0,
 742   REG_0F1E_MOD_3,
 743   REG_0F71,
 744   REG_0F72,
 745   REG_0F73,
 746   REG_0FA6,
 747   REG_0FA7,
 748   REG_0FAE,
 749   REG_0FBA,
 750   REG_0FC7,
 751   REG_VEX_0F71,
 752   REG_VEX_0F72,
 753   REG_VEX_0F73,
 754   REG_VEX_0FAE,
 755   REG_VEX_0F38F3,
 756   REG_XOP_LWPCB,
 757   REG_XOP_LWP,
 758   REG_XOP_TBM_01,
 759   REG_XOP_TBM_02,
 760
 761   REG_EVEX_0F71,
 762   REG_EVEX_0F72,
 763   REG_EVEX_0F73,
 764   REG_EVEX_0F38C6,
 765   REG_EVEX_0F38C7
 766 };
 767
 768 enum
 769 {
 770   MOD_8D = 0,
 771   MOD_C6_REG_7,
 772   MOD_C7_REG_7,
 773   MOD_FF_REG_3,
 774   MOD_FF_REG_5,
 775   MOD_0F01_REG_0,
 776   MOD_0F01_REG_1,
 777   MOD_0F01_REG_2,
 778   MOD_0F01_REG_3,
 779   MOD_0F01_REG_5,
 780   MOD_0F01_REG_7,
 781   MOD_0F12_PREFIX_0,
 782   MOD_0F13,
 783   MOD_0F16_PREFIX_0,
 784   MOD_0F17,
 785   MOD_0F18_REG_0,
 786   MOD_0F18_REG_1,
 787   MOD_0F18_REG_2,
 788   MOD_0F18_REG_3,
 789   MOD_0F18_REG_4,
 790   MOD_0F18_REG_5,
 791   MOD_0F18_REG_6,
 792   MOD_0F18_REG_7,
 793   MOD_0F1A_PREFIX_0,
 794   MOD_0F1B_PREFIX_0,
 795   MOD_0F1B_PREFIX_1,
 796   MOD_0F1C_PREFIX_0,
 797   MOD_0F1E_PREFIX_1,
 798   MOD_0F24,
 799   MOD_0F26,
 800   MOD_0F2B_PREFIX_0,
 801   MOD_0F2B_PREFIX_1,
 802   MOD_0F2B_PREFIX_2,
 803   MOD_0F2B_PREFIX_3,
 804   MOD_0F51,
 805   MOD_0F71_REG_2,
 806   MOD_0F71_REG_4,
 807   MOD_0F71_REG_6,
 808   MOD_0F72_REG_2,
 809   MOD_0F72_REG_4,
 810   MOD_0F72_REG_6,
 811   MOD_0F73_REG_2,
 812   MOD_0F73_REG_3,
 813   MOD_0F73_REG_6,
 814   MOD_0F73_REG_7,
 815   MOD_0FAE_REG_0,
 816   MOD_0FAE_REG_1,
 817   MOD_0FAE_REG_2,
 818   MOD_0FAE_REG_3,
 819   MOD_0FAE_REG_4,
 820   MOD_0FAE_REG_5,
 821   MOD_0FAE_REG_6,
 822   MOD_0FAE_REG_7,
 823   MOD_0FB2,
 824   MOD_0FB4,
 825   MOD_0FB5,
 826   MOD_0FC3,
 827   MOD_0FC7_REG_3,
 828   MOD_0FC7_REG_4,
 829   MOD_0FC7_REG_5,
 830   MOD_0FC7_REG_6,
 831   MOD_0FC7_REG_7,
 832   MOD_0FD7,
 833   MOD_0FE7_PREFIX_2,
 834   MOD_0FF0_PREFIX_3,
 835   MOD_0F382A_PREFIX_2,
 836   MOD_0F38F5_PREFIX_2,
 837   MOD_0F38F6_PREFIX_0,
 838   MOD_62_32BIT,
 839   MOD_C4_32BIT,
 840   MOD_C5_32BIT,
 841   MOD_VEX_0F12_PREFIX_0,
 842   MOD_VEX_0F13,
 843   MOD_VEX_0F16_PREFIX_0,
 844   MOD_VEX_0F17,
 845   MOD_VEX_0F2B,
 846   MOD_VEX_W_0_0F41_P_0_LEN_1,
 847   MOD_VEX_W_1_0F41_P_0_LEN_1,
 848   MOD_VEX_W_0_0F41_P_2_LEN_1,
 849   MOD_VEX_W_1_0F41_P_2_LEN_1,
 850   MOD_VEX_W_0_0F42_P_0_LEN_1,
 851   MOD_VEX_W_1_0F42_P_0_LEN_1,
 852   MOD_VEX_W_0_0F42_P_2_LEN_1,
 853   MOD_VEX_W_1_0F42_P_2_LEN_1,
 854   MOD_VEX_W_0_0F44_P_0_LEN_1,
 855   MOD_VEX_W_1_0F44_P_0_LEN_1,
 856   MOD_VEX_W_0_0F44_P_2_LEN_1,
 857   MOD_VEX_W_1_0F44_P_2_LEN_1,
 858   MOD_VEX_W_0_0F45_P_0_LEN_1,
 859   MOD_VEX_W_1_0F45_P_0_LEN_1,
 860   MOD_VEX_W_0_0F45_P_2_LEN_1,
 861   MOD_VEX_W_1_0F45_P_2_LEN_1,
 862   MOD_VEX_W_0_0F46_P_0_LEN_1,
 863   MOD_VEX_W_1_0F46_P_0_LEN_1,
 864   MOD_VEX_W_0_0F46_P_2_LEN_1,
 865   MOD_VEX_W_1_0F46_P_2_LEN_1,
 866   MOD_VEX_W_0_0F47_P_0_LEN_1,
 867   MOD_VEX_W_1_0F47_P_0_LEN_1,
 868   MOD_VEX_W_0_0F47_P_2_LEN_1,
 869   MOD_VEX_W_1_0F47_P_2_LEN_1,
 870   MOD_VEX_W_0_0F4A_P_0_LEN_1,
 871   MOD_VEX_W_1_0F4A_P_0_LEN_1,
 872   MOD_VEX_W_0_0F4A_P_2_LEN_1,
 873   MOD_VEX_W_1_0F4A_P_2_LEN_1,
 874   MOD_VEX_W_0_0F4B_P_0_LEN_1,
 875   MOD_VEX_W_1_0F4B_P_0_LEN_1,
 876   MOD_VEX_W_0_0F4B_P_2_LEN_1,
 877   MOD_VEX_0F50,
 878   MOD_VEX_0F71_REG_2,
 879   MOD_VEX_0F71_REG_4,
 880   MOD_VEX_0F71_REG_6,
 881   MOD_VEX_0F72_REG_2,
 882   MOD_VEX_0F72_REG_4,
 883   MOD_VEX_0F72_REG_6,
 884   MOD_VEX_0F73_REG_2,
 885   MOD_VEX_0F73_REG_3,
 886   MOD_VEX_0F73_REG_6,
 887   MOD_VEX_0F73_REG_7,
 888   MOD_VEX_W_0_0F91_P_0_LEN_0,
 889   MOD_VEX_W_1_0F91_P_0_LEN_0,
 890   MOD_VEX_W_0_0F91_P_2_LEN_0,
 891   MOD_VEX_W_1_0F91_P_2_LEN_0,
 892   MOD_VEX_W_0_0F92_P_0_LEN_0,
 893   MOD_VEX_W_0_0F92_P_2_LEN_0,
 894   MOD_VEX_W_0_0F92_P_3_LEN_0,
 895   MOD_VEX_W_1_0F92_P_3_LEN_0,
 896   MOD_VEX_W_0_0F93_P_0_LEN_0,
 897   MOD_VEX_W_0_0F93_P_2_LEN_0,
 898   MOD_VEX_W_0_0F93_P_3_LEN_0,
 899   MOD_VEX_W_1_0F93_P_3_LEN_0,
 900   MOD_VEX_W_0_0F98_P_0_LEN_0,
 901   MOD_VEX_W_1_0F98_P_0_LEN_0,
 902   MOD_VEX_W_0_0F98_P_2_LEN_0,
 903   MOD_VEX_W_1_0F98_P_2_LEN_0,
 904   MOD_VEX_W_0_0F99_P_0_LEN_0,
 905   MOD_VEX_W_1_0F99_P_0_LEN_0,
 906   MOD_VEX_W_0_0F99_P_2_LEN_0,
 907   MOD_VEX_W_1_0F99_P_2_LEN_0,
 908   MOD_VEX_0FAE_REG_2,
 909   MOD_VEX_0FAE_REG_3,
 910   MOD_VEX_0FD7_PREFIX_2,
 911   MOD_VEX_0FE7_PREFIX_2,
 912   MOD_VEX_0FF0_PREFIX_3,
 913   MOD_VEX_0F381A_PREFIX_2,
 914   MOD_VEX_0F382A_PREFIX_2,
 915   MOD_VEX_0F382C_PREFIX_2,
 916   MOD_VEX_0F382D_PREFIX_2,
 917   MOD_VEX_0F382E_PREFIX_2,
 918   MOD_VEX_0F382F_PREFIX_2,
 919   MOD_VEX_0F385A_PREFIX_2,
 920   MOD_VEX_0F388C_PREFIX_2,
 921   MOD_VEX_0F388E_PREFIX_2,
 922   MOD_VEX_W_0_0F3A30_P_2_LEN_0,
 923   MOD_VEX_W_1_0F3A30_P_2_LEN_0,
 924   MOD_VEX_W_0_0F3A31_P_2_LEN_0,
 925   MOD_VEX_W_1_0F3A31_P_2_LEN_0,
 926   MOD_VEX_W_0_0F3A32_P_2_LEN_0,
 927   MOD_VEX_W_1_0F3A32_P_2_LEN_0,
 928   MOD_VEX_W_0_0F3A33_P_2_LEN_0,
 929   MOD_VEX_W_1_0F3A33_P_2_LEN_0,
 930
 931   MOD_EVEX_0F10_PREFIX_1,
 932   MOD_EVEX_0F10_PREFIX_3,
 933   MOD_EVEX_0F11_PREFIX_1,
 934   MOD_EVEX_0F11_PREFIX_3,
 935   MOD_EVEX_0F12_PREFIX_0,
 936   MOD_EVEX_0F16_PREFIX_0,
 937   MOD_EVEX_0F38C6_REG_1,
 938   MOD_EVEX_0F38C6_REG_2,
 939   MOD_EVEX_0F38C6_REG_5,
 940   MOD_EVEX_0F38C6_REG_6,
 941   MOD_EVEX_0F38C7_REG_1,
 942   MOD_EVEX_0F38C7_REG_2,
 943   MOD_EVEX_0F38C7_REG_5,
 944   MOD_EVEX_0F38C7_REG_6
 945 };
 946
 947 enum
 948 {
 949   RM_C6_REG_7 = 0,
 950   RM_C7_REG_7,
 951   RM_0F01_REG_0,
 952   RM_0F01_REG_1,
 953   RM_0F01_REG_2,
 954   RM_0F01_REG_3,
 955   RM_0F01_REG_5,
 956   RM_0F01_REG_7,
 957   RM_0F1E_MOD_3_REG_7,
 958   RM_0FAE_REG_6,
 959   RM_0FAE_REG_7
 960 };
 961
 962 enum
 963 {
 964   PREFIX_90 = 0,
 965   PREFIX_MOD_0_0F01_REG_5,
 966   PREFIX_MOD_3_0F01_REG_5_RM_0,
 967   PREFIX_MOD_3_0F01_REG_5_RM_2,
 968   PREFIX_0F09,
 969   PREFIX_0F10,
 970   PREFIX_0F11,
 971   PREFIX_0F12,
 972   PREFIX_0F16,
 973   PREFIX_0F1A,
 974   PREFIX_0F1B,
 975   PREFIX_0F1C,
 976   PREFIX_0F1E,
 977   PREFIX_0F2A,
 978   PREFIX_0F2B,
 979   PREFIX_0F2C,
 980   PREFIX_0F2D,
 981   PREFIX_0F2E,
 982   PREFIX_0F2F,
 983   PREFIX_0F51,
 984   PREFIX_0F52,
 985   PREFIX_0F53,
 986   PREFIX_0F58,
 987   PREFIX_0F59,
 988   PREFIX_0F5A,
 989   PREFIX_0F5B,
 990   PREFIX_0F5C,
 991   PREFIX_0F5D,
 992   PREFIX_0F5E,
 993   PREFIX_0F5F,
 994   PREFIX_0F60,
 995   PREFIX_0F61,
 996   PREFIX_0F62,
 997   PREFIX_0F6C,
 998   PREFIX_0F6D,
 999   PREFIX_0F6F,
1000   PREFIX_0F70,
1001   PREFIX_0F73_REG_3,
1002   PREFIX_0F73_REG_7,
1003   PREFIX_0F78,
1004   PREFIX_0F79,
1005   PREFIX_0F7C,
1006   PREFIX_0F7D,
1007   PREFIX_0F7E,
1008   PREFIX_0F7F,
1009   PREFIX_0FAE_REG_0,
1010   PREFIX_0FAE_REG_1,
1011   PREFIX_0FAE_REG_2,
1012   PREFIX_0FAE_REG_3,
1013   PREFIX_MOD_0_0FAE_REG_4,
1014   PREFIX_MOD_3_0FAE_REG_4,
1015   PREFIX_MOD_0_0FAE_REG_5,
1016   PREFIX_MOD_3_0FAE_REG_5,
1017   PREFIX_MOD_0_0FAE_REG_6,
1018   PREFIX_MOD_1_0FAE_REG_6,
1019   PREFIX_0FAE_REG_7,
1020   PREFIX_0FB8,
1021   PREFIX_0FBC,
1022   PREFIX_0FBD,
1023   PREFIX_0FC2,
1024   PREFIX_MOD_0_0FC3,
1025   PREFIX_MOD_0_0FC7_REG_6,
1026   PREFIX_MOD_3_0FC7_REG_6,
1027   PREFIX_MOD_3_0FC7_REG_7,
1028   PREFIX_0FD0,
1029   PREFIX_0FD6,
1030   PREFIX_0FE6,
1031   PREFIX_0FE7,
1032   PREFIX_0FF0,
1033   PREFIX_0FF7,
1034   PREFIX_0F3810,
1035   PREFIX_0F3814,
1036   PREFIX_0F3815,
1037   PREFIX_0F3817,
1038   PREFIX_0F3820,
1039   PREFIX_0F3821,
1040   PREFIX_0F3822,
1041   PREFIX_0F3823,
1042   PREFIX_0F3824,
1043   PREFIX_0F3825,
1044   PREFIX_0F3828,
1045   PREFIX_0F3829,
1046   PREFIX_0F382A,
1047   PREFIX_0F382B,
1048   PREFIX_0F3830,
1049   PREFIX_0F3831,
1050   PREFIX_0F3832,
1051   PREFIX_0F3833,
1052   PREFIX_0F3834,
1053   PREFIX_0F3835,
1054   PREFIX_0F3837,
1055   PREFIX_0F3838,
1056   PREFIX_0F3839,
1057   PREFIX_0F383A,
1058   PREFIX_0F383B,
1059   PREFIX_0F383C,
1060   PREFIX_0F383D,
1061   PREFIX_0F383E,
1062   PREFIX_0F383F,
1063   PREFIX_0F3840,
1064   PREFIX_0F3841,
1065   PREFIX_0F3880,
1066   PREFIX_0F3881,
1067   PREFIX_0F3882,
1068   PREFIX_0F38C8,
1069   PREFIX_0F38C9,
1070   PREFIX_0F38CA,
1071   PREFIX_0F38CB,
1072   PREFIX_0F38CC,
1073   PREFIX_0F38CD,
1074   PREFIX_0F38CF,
1075   PREFIX_0F38DB,
1076   PREFIX_0F38DC,
1077   PREFIX_0F38DD,
1078   PREFIX_0F38DE,
1079   PREFIX_0F38DF,
1080   PREFIX_0F38F0,
1081   PREFIX_0F38F1,
1082   PREFIX_0F38F5,
1083   PREFIX_0F38F6,
1084   PREFIX_0F3A08,
1085   PREFIX_0F3A09,
1086   PREFIX_0F3A0A,
1087   PREFIX_0F3A0B,
1088   PREFIX_0F3A0C,
1089   PREFIX_0F3A0D,
1090   PREFIX_0F3A0E,
1091   PREFIX_0F3A14,
1092   PREFIX_0F3A15,
1093   PREFIX_0F3A16,
1094   PREFIX_0F3A17,
1095   PREFIX_0F3A20,
1096   PREFIX_0F3A21,
1097   PREFIX_0F3A22,
1098   PREFIX_0F3A40,
1099   PREFIX_0F3A41,
1100   PREFIX_0F3A42,
1101   PREFIX_0F3A44,
1102   PREFIX_0F3A60,
1103   PREFIX_0F3A61,
1104   PREFIX_0F3A62,
1105   PREFIX_0F3A63,
1106   PREFIX_0F3ACC,
1107   PREFIX_0F3ACE,
1108   PREFIX_0F3ACF,
1109   PREFIX_0F3ADF,
1110   PREFIX_VEX_0F10,
1111   PREFIX_VEX_0F11,
1112   PREFIX_VEX_0F12,
1113   PREFIX_VEX_0F16,
1114   PREFIX_VEX_0F2A,
1115   PREFIX_VEX_0F2C,
1116   PREFIX_VEX_0F2D,
1117   PREFIX_VEX_0F2E,
1118   PREFIX_VEX_0F2F,
1119   PREFIX_VEX_0F41,
1120   PREFIX_VEX_0F42,
1121   PREFIX_VEX_0F44,
1122   PREFIX_VEX_0F45,
1123   PREFIX_VEX_0F46,
1124   PREFIX_VEX_0F47,
1125   PREFIX_VEX_0F4A,
1126   PREFIX_VEX_0F4B,
1127   PREFIX_VEX_0F51,
1128   PREFIX_VEX_0F52,
1129   PREFIX_VEX_0F53,
1130   PREFIX_VEX_0F58,
1131   PREFIX_VEX_0F59,
1132   PREFIX_VEX_0F5A,
1133   PREFIX_VEX_0F5B,
1134   PREFIX_VEX_0F5C,
1135   PREFIX_VEX_0F5D,
1136   PREFIX_VEX_0F5E,
1137   PREFIX_VEX_0F5F,
1138   PREFIX_VEX_0F60,
1139   PREFIX_VEX_0F61,
1140   PREFIX_VEX_0F62,
1141   PREFIX_VEX_0F63,
1142   PREFIX_VEX_0F64,
1143   PREFIX_VEX_0F65,
1144   PREFIX_VEX_0F66,
1145   PREFIX_VEX_0F67,
1146   PREFIX_VEX_0F68,
1147   PREFIX_VEX_0F69,
1148   PREFIX_VEX_0F6A,
1149   PREFIX_VEX_0F6B,
1150   PREFIX_VEX_0F6C,
1151   PREFIX_VEX_0F6D,
1152   PREFIX_VEX_0F6E,
1153   PREFIX_VEX_0F6F,
1154   PREFIX_VEX_0F70,
1155   PREFIX_VEX_0F71_REG_2,
1156   PREFIX_VEX_0F71_REG_4,
1157   PREFIX_VEX_0F71_REG_6,
1158   PREFIX_VEX_0F72_REG_2,
1159   PREFIX_VEX_0F72_REG_4,
1160   PREFIX_VEX_0F72_REG_6,
1161   PREFIX_VEX_0F73_REG_2,
1162   PREFIX_VEX_0F73_REG_3,
1163   PREFIX_VEX_0F73_REG_6,
1164   PREFIX_VEX_0F73_REG_7,
1165   PREFIX_VEX_0F74,
1166   PREFIX_VEX_0F75,
1167   PREFIX_VEX_0F76,
1168   PREFIX_VEX_0F77,
1169   PREFIX_VEX_0F7C,
1170   PREFIX_VEX_0F7D,
1171   PREFIX_VEX_0F7E,
1172   PREFIX_VEX_0F7F,
1173   PREFIX_VEX_0F90,
1174   PREFIX_VEX_0F91,
1175   PREFIX_VEX_0F92,
1176   PREFIX_VEX_0F93,
1177   PREFIX_VEX_0F98,
1178   PREFIX_VEX_0F99,
1179   PREFIX_VEX_0FC2,
1180   PREFIX_VEX_0FC4,
1181   PREFIX_VEX_0FC5,
1182   PREFIX_VEX_0FD0,
1183   PREFIX_VEX_0FD1,
1184   PREFIX_VEX_0FD2,
1185   PREFIX_VEX_0FD3,
1186   PREFIX_VEX_0FD4,
1187   PREFIX_VEX_0FD5,
1188   PREFIX_VEX_0FD6,
1189   PREFIX_VEX_0FD7,
1190   PREFIX_VEX_0FD8,
1191   PREFIX_VEX_0FD9,
1192   PREFIX_VEX_0FDA,
1193   PREFIX_VEX_0FDB,
1194   PREFIX_VEX_0FDC,
1195   PREFIX_VEX_0FDD,
1196   PREFIX_VEX_0FDE,
1197   PREFIX_VEX_0FDF,
1198   PREFIX_VEX_0FE0,
1199   PREFIX_VEX_0FE1,
1200   PREFIX_VEX_0FE2,
1201   PREFIX_VEX_0FE3,
1202   PREFIX_VEX_0FE4,
1203   PREFIX_VEX_0FE5,
1204   PREFIX_VEX_0FE6,
1205   PREFIX_VEX_0FE7,
1206   PREFIX_VEX_0FE8,
1207   PREFIX_VEX_0FE9,
1208   PREFIX_VEX_0FEA,
1209   PREFIX_VEX_0FEB,
1210   PREFIX_VEX_0FEC,
1211   PREFIX_VEX_0FED,
1212   PREFIX_VEX_0FEE,
1213   PREFIX_VEX_0FEF,
1214   PREFIX_VEX_0FF0,
1215   PREFIX_VEX_0FF1,
1216   PREFIX_VEX_0FF2,
1217   PREFIX_VEX_0FF3,
1218   PREFIX_VEX_0FF4,
1219   PREFIX_VEX_0FF5,
1220   PREFIX_VEX_0FF6,
1221   PREFIX_VEX_0FF7,
1222   PREFIX_VEX_0FF8,
1223   PREFIX_VEX_0FF9,
1224   PREFIX_VEX_0FFA,
1225   PREFIX_VEX_0FFB,
1226   PREFIX_VEX_0FFC,
1227   PREFIX_VEX_0FFD,
1228   PREFIX_VEX_0FFE,
1229   PREFIX_VEX_0F3800,
1230   PREFIX_VEX_0F3801,
1231   PREFIX_VEX_0F3802,
1232   PREFIX_VEX_0F3803,
1233   PREFIX_VEX_0F3804,
1234   PREFIX_VEX_0F3805,
1235   PREFIX_VEX_0F3806,
1236   PREFIX_VEX_0F3807,
1237   PREFIX_VEX_0F3808,
1238   PREFIX_VEX_0F3809,
1239   PREFIX_VEX_0F380A,
1240   PREFIX_VEX_0F380B,
1241   PREFIX_VEX_0F380C,
1242   PREFIX_VEX_0F380D,
1243   PREFIX_VEX_0F380E,
1244   PREFIX_VEX_0F380F,
1245   PREFIX_VEX_0F3813,
1246   PREFIX_VEX_0F3816,
1247   PREFIX_VEX_0F3817,
1248   PREFIX_VEX_0F3818,
1249   PREFIX_VEX_0F3819,
1250   PREFIX_VEX_0F381A,
1251   PREFIX_VEX_0F381C,
1252   PREFIX_VEX_0F381D,
1253   PREFIX_VEX_0F381E,
1254   PREFIX_VEX_0F3820,
1255   PREFIX_VEX_0F3821,
1256   PREFIX_VEX_0F3822,
1257   PREFIX_VEX_0F3823,
1258   PREFIX_VEX_0F3824,
1259   PREFIX_VEX_0F3825,
1260   PREFIX_VEX_0F3828,
1261   PREFIX_VEX_0F3829,
1262   PREFIX_VEX_0F382A,
1263   PREFIX_VEX_0F382B,
1264   PREFIX_VEX_0F382C,
1265   PREFIX_VEX_0F382D,
1266   PREFIX_VEX_0F382E,
1267   PREFIX_VEX_0F382F,
1268   PREFIX_VEX_0F3830,
1269   PREFIX_VEX_0F3831,
1270   PREFIX_VEX_0F3832,
1271   PREFIX_VEX_0F3833,
1272   PREFIX_VEX_0F3834,
1273   PREFIX_VEX_0F3835,
1274   PREFIX_VEX_0F3836,
1275   PREFIX_VEX_0F3837,
1276   PREFIX_VEX_0F3838,
1277   PREFIX_VEX_0F3839,
1278   PREFIX_VEX_0F383A,
1279   PREFIX_VEX_0F383B,
1280   PREFIX_VEX_0F383C,
1281   PREFIX_VEX_0F383D,
1282   PREFIX_VEX_0F383E,
1283   PREFIX_VEX_0F383F,
1284   PREFIX_VEX_0F3840,
1285   PREFIX_VEX_0F3841,
1286   PREFIX_VEX_0F3845,
1287   PREFIX_VEX_0F3846,
1288   PREFIX_VEX_0F3847,
1289   PREFIX_VEX_0F3858,
1290   PREFIX_VEX_0F3859,
1291   PREFIX_VEX_0F385A,
1292   PREFIX_VEX_0F3878,
1293   PREFIX_VEX_0F3879,
1294   PREFIX_VEX_0F388C,
1295   PREFIX_VEX_0F388E,
1296   PREFIX_VEX_0F3890,
1297   PREFIX_VEX_0F3891,
1298   PREFIX_VEX_0F3892,
1299   PREFIX_VEX_0F3893,
1300   PREFIX_VEX_0F3896,
1301   PREFIX_VEX_0F3897,
1302   PREFIX_VEX_0F3898,
1303   PREFIX_VEX_0F3899,
1304   PREFIX_VEX_0F389A,
1305   PREFIX_VEX_0F389B,
1306   PREFIX_VEX_0F389C,
1307   PREFIX_VEX_0F389D,
1308   PREFIX_VEX_0F389E,
1309   PREFIX_VEX_0F389F,
1310   PREFIX_VEX_0F38A6,
1311   PREFIX_VEX_0F38A7,
1312   PREFIX_VEX_0F38A8,
1313   PREFIX_VEX_0F38A9,
1314   PREFIX_VEX_0F38AA,
1315   PREFIX_VEX_0F38AB,
1316   PREFIX_VEX_0F38AC,
1317   PREFIX_VEX_0F38AD,
1318   PREFIX_VEX_0F38AE,
1319   PREFIX_VEX_0F38AF,
1320   PREFIX_VEX_0F38B6,
1321   PREFIX_VEX_0F38B7,
1322   PREFIX_VEX_0F38B8,
1323   PREFIX_VEX_0F38B9,
1324   PREFIX_VEX_0F38BA,
1325   PREFIX_VEX_0F38BB,
1326   PREFIX_VEX_0F38BC,
1327   PREFIX_VEX_0F38BD,
1328   PREFIX_VEX_0F38BE,
1329   PREFIX_VEX_0F38BF,
1330   PREFIX_VEX_0F38CF,
1331   PREFIX_VEX_0F38DB,
1332   PREFIX_VEX_0F38DC,
1333   PREFIX_VEX_0F38DD,
1334   PREFIX_VEX_0F38DE,
1335   PREFIX_VEX_0F38DF,
1336   PREFIX_VEX_0F38F2,
1337   PREFIX_VEX_0F38F3_REG_1,
1338   PREFIX_VEX_0F38F3_REG_2,
1339   PREFIX_VEX_0F38F3_REG_3,
1340   PREFIX_VEX_0F38F5,
1341   PREFIX_VEX_0F38F6,
1342   PREFIX_VEX_0F38F7,
1343   PREFIX_VEX_0F3A00,
1344   PREFIX_VEX_0F3A01,
1345   PREFIX_VEX_0F3A02,
1346   PREFIX_VEX_0F3A04,
1347   PREFIX_VEX_0F3A05,
1348   PREFIX_VEX_0F3A06,
1349   PREFIX_VEX_0F3A08,
1350   PREFIX_VEX_0F3A09,
1351   PREFIX_VEX_0F3A0A,
1352   PREFIX_VEX_0F3A0B,
1353   PREFIX_VEX_0F3A0C,
1354   PREFIX_VEX_0F3A0D,
1355   PREFIX_VEX_0F3A0E,
1356   PREFIX_VEX_0F3A0F,
1357   PREFIX_VEX_0F3A14,
1358   PREFIX_VEX_0F3A15,
1359   PREFIX_VEX_0F3A16,
1360   PREFIX_VEX_0F3A17,
1361   PREFIX_VEX_0F3A18,
1362   PREFIX_VEX_0F3A19,
1363   PREFIX_VEX_0F3A1D,
1364   PREFIX_VEX_0F3A20,
1365   PREFIX_VEX_0F3A21,
1366   PREFIX_VEX_0F3A22,
1367   PREFIX_VEX_0F3A30,
1368   PREFIX_VEX_0F3A31,
1369   PREFIX_VEX_0F3A32,
1370   PREFIX_VEX_0F3A33,
1371   PREFIX_VEX_0F3A38,
1372   PREFIX_VEX_0F3A39,
1373   PREFIX_VEX_0F3A40,
1374   PREFIX_VEX_0F3A41,
1375   PREFIX_VEX_0F3A42,
1376   PREFIX_VEX_0F3A44,
1377   PREFIX_VEX_0F3A46,
1378   PREFIX_VEX_0F3A48,
1379   PREFIX_VEX_0F3A49,
1380   PREFIX_VEX_0F3A4A,
1381   PREFIX_VEX_0F3A4B,
1382   PREFIX_VEX_0F3A4C,
1383   PREFIX_VEX_0F3A5C,
1384   PREFIX_VEX_0F3A5D,
1385   PREFIX_VEX_0F3A5E,
1386   PREFIX_VEX_0F3A5F,
1387   PREFIX_VEX_0F3A60,
1388   PREFIX_VEX_0F3A61,
1389   PREFIX_VEX_0F3A62,
1390   PREFIX_VEX_0F3A63,
1391   PREFIX_VEX_0F3A68,
1392   PREFIX_VEX_0F3A69,
1393   PREFIX_VEX_0F3A6A,
1394   PREFIX_VEX_0F3A6B,
1395   PREFIX_VEX_0F3A6C,
1396   PREFIX_VEX_0F3A6D,
1397   PREFIX_VEX_0F3A6E,
1398   PREFIX_VEX_0F3A6F,
1399   PREFIX_VEX_0F3A78,
1400   PREFIX_VEX_0F3A79,
1401   PREFIX_VEX_0F3A7A,
1402   PREFIX_VEX_0F3A7B,
1403   PREFIX_VEX_0F3A7C,
1404   PREFIX_VEX_0F3A7D,
1405   PREFIX_VEX_0F3A7E,
1406   PREFIX_VEX_0F3A7F,
1407   PREFIX_VEX_0F3ACE,
1408   PREFIX_VEX_0F3ACF,
1409   PREFIX_VEX_0F3ADF,
1410   PREFIX_VEX_0F3AF0,
1411
1412   PREFIX_EVEX_0F10,
1413   PREFIX_EVEX_0F11,
1414   PREFIX_EVEX_0F12,
1415   PREFIX_EVEX_0F13,
1416   PREFIX_EVEX_0F14,
1417   PREFIX_EVEX_0F15,
1418   PREFIX_EVEX_0F16,
1419   PREFIX_EVEX_0F17,
1420   PREFIX_EVEX_0F28,
1421   PREFIX_EVEX_0F29,
1422   PREFIX_EVEX_0F2A,
1423   PREFIX_EVEX_0F2B,
1424   PREFIX_EVEX_0F2C,
1425   PREFIX_EVEX_0F2D,
1426   PREFIX_EVEX_0F2E,
1427   PREFIX_EVEX_0F2F,
1428   PREFIX_EVEX_0F51,
1429   PREFIX_EVEX_0F54,
1430   PREFIX_EVEX_0F55,
1431   PREFIX_EVEX_0F56,
1432   PREFIX_EVEX_0F57,
1433   PREFIX_EVEX_0F58,
1434   PREFIX_EVEX_0F59,
1435   PREFIX_EVEX_0F5A,
1436   PREFIX_EVEX_0F5B,
1437   PREFIX_EVEX_0F5C,
1438   PREFIX_EVEX_0F5D,
1439   PREFIX_EVEX_0F5E,
1440   PREFIX_EVEX_0F5F,
1441   PREFIX_EVEX_0F60,
1442   PREFIX_EVEX_0F61,
1443   PREFIX_EVEX_0F62,
1444   PREFIX_EVEX_0F63,
1445   PREFIX_EVEX_0F64,
1446   PREFIX_EVEX_0F65,
1447   PREFIX_EVEX_0F66,
1448   PREFIX_EVEX_0F67,
1449   PREFIX_EVEX_0F68,
1450   PREFIX_EVEX_0F69,
1451   PREFIX_EVEX_0F6A,
1452   PREFIX_EVEX_0F6B,
1453   PREFIX_EVEX_0F6C,
1454   PREFIX_EVEX_0F6D,
1455   PREFIX_EVEX_0F6E,
1456   PREFIX_EVEX_0F6F,
1457   PREFIX_EVEX_0F70,
1458   PREFIX_EVEX_0F71_REG_2,
1459   PREFIX_EVEX_0F71_REG_4,
1460   PREFIX_EVEX_0F71_REG_6,
1461   PREFIX_EVEX_0F72_REG_0,
1462   PREFIX_EVEX_0F72_REG_1,
1463   PREFIX_EVEX_0F72_REG_2,
1464   PREFIX_EVEX_0F72_REG_4,
1465   PREFIX_EVEX_0F72_REG_6,
1466   PREFIX_EVEX_0F73_REG_2,
1467   PREFIX_EVEX_0F73_REG_3,
1468   PREFIX_EVEX_0F73_REG_6,
1469   PREFIX_EVEX_0F73_REG_7,
1470   PREFIX_EVEX_0F74,
1471   PREFIX_EVEX_0F75,
1472   PREFIX_EVEX_0F76,
1473   PREFIX_EVEX_0F78,
1474   PREFIX_EVEX_0F79,
1475   PREFIX_EVEX_0F7A,
1476   PREFIX_EVEX_0F7B,
1477   PREFIX_EVEX_0F7E,
1478   PREFIX_EVEX_0F7F,
1479   PREFIX_EVEX_0FC2,
1480   PREFIX_EVEX_0FC4,
1481   PREFIX_EVEX_0FC5,
1482   PREFIX_EVEX_0FC6,
1483   PREFIX_EVEX_0FD1,
1484   PREFIX_EVEX_0FD2,
1485   PREFIX_EVEX_0FD3,
1486   PREFIX_EVEX_0FD4,
1487   PREFIX_EVEX_0FD5,
1488   PREFIX_EVEX_0FD6,
1489   PREFIX_EVEX_0FD8,
1490   PREFIX_EVEX_0FD9,
1491   PREFIX_EVEX_0FDA,
1492   PREFIX_EVEX_0FDB,
1493   PREFIX_EVEX_0FDC,
1494   PREFIX_EVEX_0FDD,
1495   PREFIX_EVEX_0FDE,
1496   PREFIX_EVEX_0FDF,
1497   PREFIX_EVEX_0FE0,
1498   PREFIX_EVEX_0FE1,
1499   PREFIX_EVEX_0FE2,
1500   PREFIX_EVEX_0FE3,
1501   PREFIX_EVEX_0FE4,
1502   PREFIX_EVEX_0FE5,
1503   PREFIX_EVEX_0FE6,
1504   PREFIX_EVEX_0FE7,
1505   PREFIX_EVEX_0FE8,
1506   PREFIX_EVEX_0FE9,
1507   PREFIX_EVEX_0FEA,
1508   PREFIX_EVEX_0FEB,
1509   PREFIX_EVEX_0FEC,
1510   PREFIX_EVEX_0FED,
1511   PREFIX_EVEX_0FEE,
1512   PREFIX_EVEX_0FEF,
1513   PREFIX_EVEX_0FF1,
1514   PREFIX_EVEX_0FF2,
1515   PREFIX_EVEX_0FF3,
1516   PREFIX_EVEX_0FF4,
1517   PREFIX_EVEX_0FF5,
1518   PREFIX_EVEX_0FF6,
1519   PREFIX_EVEX_0FF8,
1520   PREFIX_EVEX_0FF9,
1521   PREFIX_EVEX_0FFA,
1522   PREFIX_EVEX_0FFB,
1523   PREFIX_EVEX_0FFC,
1524   PREFIX_EVEX_0FFD,
1525   PREFIX_EVEX_0FFE,
1526   PREFIX_EVEX_0F3800,
1527   PREFIX_EVEX_0F3804,
1528   PREFIX_EVEX_0F380B,
1529   PREFIX_EVEX_0F380C,
1530   PREFIX_EVEX_0F380D,
1531   PREFIX_EVEX_0F3810,
1532   PREFIX_EVEX_0F3811,
1533   PREFIX_EVEX_0F3812,
1534   PREFIX_EVEX_0F3813,
1535   PREFIX_EVEX_0F3814,
1536   PREFIX_EVEX_0F3815,
1537   PREFIX_EVEX_0F3816,
1538   PREFIX_EVEX_0F3818,
1539   PREFIX_EVEX_0F3819,
1540   PREFIX_EVEX_0F381A,
1541   PREFIX_EVEX_0F381B,
1542   PREFIX_EVEX_0F381C,
1543   PREFIX_EVEX_0F381D,
1544   PREFIX_EVEX_0F381E,
1545   PREFIX_EVEX_0F381F,
1546   PREFIX_EVEX_0F3820,
1547   PREFIX_EVEX_0F3821,
1548   PREFIX_EVEX_0F3822,
1549   PREFIX_EVEX_0F3823,
1550   PREFIX_EVEX_0F3824,
1551   PREFIX_EVEX_0F3825,
1552   PREFIX_EVEX_0F3826,
1553   PREFIX_EVEX_0F3827,
1554   PREFIX_EVEX_0F3828,
1555   PREFIX_EVEX_0F3829,
1556   PREFIX_EVEX_0F382A,
1557   PREFIX_EVEX_0F382B,
1558   PREFIX_EVEX_0F382C,
1559   PREFIX_EVEX_0F382D,
1560   PREFIX_EVEX_0F3830,
1561   PREFIX_EVEX_0F3831,
1562   PREFIX_EVEX_0F3832,
1563   PREFIX_EVEX_0F3833,
1564   PREFIX_EVEX_0F3834,
1565   PREFIX_EVEX_0F3835,
1566   PREFIX_EVEX_0F3836,
1567   PREFIX_EVEX_0F3837,
1568   PREFIX_EVEX_0F3838,
1569   PREFIX_EVEX_0F3839,
1570   PREFIX_EVEX_0F383A,
1571   PREFIX_EVEX_0F383B,
1572   PREFIX_EVEX_0F383C,
1573   PREFIX_EVEX_0F383D,
1574   PREFIX_EVEX_0F383E,
1575   PREFIX_EVEX_0F383F,
1576   PREFIX_EVEX_0F3840,
1577   PREFIX_EVEX_0F3842,
1578   PREFIX_EVEX_0F3843,
1579   PREFIX_EVEX_0F3844,
1580   PREFIX_EVEX_0F3845,
1581   PREFIX_EVEX_0F3846,
1582   PREFIX_EVEX_0F3847,
1583   PREFIX_EVEX_0F384C,
1584   PREFIX_EVEX_0F384D,
1585   PREFIX_EVEX_0F384E,
1586   PREFIX_EVEX_0F384F,
1587   PREFIX_EVEX_0F3850,
1588   PREFIX_EVEX_0F3851,
1589   PREFIX_EVEX_0F3852,
1590   PREFIX_EVEX_0F3853,
1591   PREFIX_EVEX_0F3854,
1592   PREFIX_EVEX_0F3855,
1593   PREFIX_EVEX_0F3858,
1594   PREFIX_EVEX_0F3859,
1595   PREFIX_EVEX_0F385A,
1596   PREFIX_EVEX_0F385B,
1597   PREFIX_EVEX_0F3862,
1598   PREFIX_EVEX_0F3863,
1599   PREFIX_EVEX_0F3864,
1600   PREFIX_EVEX_0F3865,
1601   PREFIX_EVEX_0F3866,
1602   PREFIX_EVEX_0F3870,
1603   PREFIX_EVEX_0F3871,
1604   PREFIX_EVEX_0F3872,
1605   PREFIX_EVEX_0F3873,
1606   PREFIX_EVEX_0F3875,
1607   PREFIX_EVEX_0F3876,
1608   PREFIX_EVEX_0F3877,
1609   PREFIX_EVEX_0F3878,
1610   PREFIX_EVEX_0F3879,
1611   PREFIX_EVEX_0F387A,
1612   PREFIX_EVEX_0F387B,
1613   PREFIX_EVEX_0F387C,
1614   PREFIX_EVEX_0F387D,
1615   PREFIX_EVEX_0F387E,
1616   PREFIX_EVEX_0F387F,
1617   PREFIX_EVEX_0F3883,
1618   PREFIX_EVEX_0F3888,
1619   PREFIX_EVEX_0F3889,
1620   PREFIX_EVEX_0F388A,
1621   PREFIX_EVEX_0F388B,
1622   PREFIX_EVEX_0F388D,
1623   PREFIX_EVEX_0F388F,
1624   PREFIX_EVEX_0F3890,
1625   PREFIX_EVEX_0F3891,
1626   PREFIX_EVEX_0F3892,
1627   PREFIX_EVEX_0F3893,
1628   PREFIX_EVEX_0F3896,
1629   PREFIX_EVEX_0F3897,
1630   PREFIX_EVEX_0F3898,
1631   PREFIX_EVEX_0F3899,
1632   PREFIX_EVEX_0F389A,
1633   PREFIX_EVEX_0F389B,
1634   PREFIX_EVEX_0F389C,
1635   PREFIX_EVEX_0F389D,
1636   PREFIX_EVEX_0F389E,
1637   PREFIX_EVEX_0F389F,
1638   PREFIX_EVEX_0F38A0,
1639   PREFIX_EVEX_0F38A1,
1640   PREFIX_EVEX_0F38A2,
1641   PREFIX_EVEX_0F38A3,
1642   PREFIX_EVEX_0F38A6,
1643   PREFIX_EVEX_0F38A7,
1644   PREFIX_EVEX_0F38A8,
1645   PREFIX_EVEX_0F38A9,
1646   PREFIX_EVEX_0F38AA,
1647   PREFIX_EVEX_0F38AB,
1648   PREFIX_EVEX_0F38AC,
1649   PREFIX_EVEX_0F38AD,
1650   PREFIX_EVEX_0F38AE,
1651   PREFIX_EVEX_0F38AF,
1652   PREFIX_EVEX_0F38B4,
1653   PREFIX_EVEX_0F38B5,
1654   PREFIX_EVEX_0F38B6,
1655   PREFIX_EVEX_0F38B7,
1656   PREFIX_EVEX_0F38B8,
1657   PREFIX_EVEX_0F38B9,
1658   PREFIX_EVEX_0F38BA,
1659   PREFIX_EVEX_0F38BB,
1660   PREFIX_EVEX_0F38BC,
1661   PREFIX_EVEX_0F38BD,
1662   PREFIX_EVEX_0F38BE,
1663   PREFIX_EVEX_0F38BF,
1664   PREFIX_EVEX_0F38C4,
1665   PREFIX_EVEX_0F38C6_REG_1,
1666   PREFIX_EVEX_0F38C6_REG_2,
1667   PREFIX_EVEX_0F38C6_REG_5,
1668   PREFIX_EVEX_0F38C6_REG_6,
1669   PREFIX_EVEX_0F38C7_REG_1,
1670   PREFIX_EVEX_0F38C7_REG_2,
1671   PREFIX_EVEX_0F38C7_REG_5,
1672   PREFIX_EVEX_0F38C7_REG_6,
1673   PREFIX_EVEX_0F38C8,
1674   PREFIX_EVEX_0F38CA,
1675   PREFIX_EVEX_0F38CB,
1676   PREFIX_EVEX_0F38CC,
1677   PREFIX_EVEX_0F38CD,
1678   PREFIX_EVEX_0F38CF,
1679   PREFIX_EVEX_0F38DC,
1680   PREFIX_EVEX_0F38DD,
1681   PREFIX_EVEX_0F38DE,
1682   PREFIX_EVEX_0F38DF,
1683
1684   PREFIX_EVEX_0F3A00,
1685   PREFIX_EVEX_0F3A01,
1686   PREFIX_EVEX_0F3A03,
1687   PREFIX_EVEX_0F3A04,
1688   PREFIX_EVEX_0F3A05,
1689   PREFIX_EVEX_0F3A08,
1690   PREFIX_EVEX_0F3A09,
1691   PREFIX_EVEX_0F3A0A,
1692   PREFIX_EVEX_0F3A0B,
1693   PREFIX_EVEX_0F3A0F,
1694   PREFIX_EVEX_0F3A14,
1695   PREFIX_EVEX_0F3A15,
1696   PREFIX_EVEX_0F3A16,
1697   PREFIX_EVEX_0F3A17,
1698   PREFIX_EVEX_0F3A18,
1699   PREFIX_EVEX_0F3A19,
1700   PREFIX_EVEX_0F3A1A,
1701   PREFIX_EVEX_0F3A1B,
1702   PREFIX_EVEX_0F3A1D,
1703   PREFIX_EVEX_0F3A1E,
1704   PREFIX_EVEX_0F3A1F,
1705   PREFIX_EVEX_0F3A20,
1706   PREFIX_EVEX_0F3A21,
1707   PREFIX_EVEX_0F3A22,
1708   PREFIX_EVEX_0F3A23,
1709   PREFIX_EVEX_0F3A25,
1710   PREFIX_EVEX_0F3A26,
1711   PREFIX_EVEX_0F3A27,
1712   PREFIX_EVEX_0F3A38,
1713   PREFIX_EVEX_0F3A39,
1714   PREFIX_EVEX_0F3A3A,
1715   PREFIX_EVEX_0F3A3B,
1716   PREFIX_EVEX_0F3A3E,
1717   PREFIX_EVEX_0F3A3F,
1718   PREFIX_EVEX_0F3A42,
1719   PREFIX_EVEX_0F3A43,
1720   PREFIX_EVEX_0F3A44,
1721   PREFIX_EVEX_0F3A50,
1722   PREFIX_EVEX_0F3A51,
1723   PREFIX_EVEX_0F3A54,
1724   PREFIX_EVEX_0F3A55,
1725   PREFIX_EVEX_0F3A56,
1726   PREFIX_EVEX_0F3A57,
1727   PREFIX_EVEX_0F3A66,
1728   PREFIX_EVEX_0F3A67,
1729   PREFIX_EVEX_0F3A70,
1730   PREFIX_EVEX_0F3A71,
1731   PREFIX_EVEX_0F3A72,
1732   PREFIX_EVEX_0F3A73,
1733   PREFIX_EVEX_0F3ACE,
1734   PREFIX_EVEX_0F3ACF
1735 };
1736
1737 enum
1738 {
1739   X86_64_06 = 0,
1740   X86_64_07,
1741   X86_64_0D,
1742   X86_64_16,
1743   X86_64_17,
1744   X86_64_1E,
1745   X86_64_1F,
1746   X86_64_27,
1747   X86_64_2F,
1748   X86_64_37,
1749   X86_64_3F,
1750   X86_64_60,
1751   X86_64_61,
1752   X86_64_62,
1753   X86_64_63,
1754   X86_64_6D,
1755   X86_64_6F,
1756   X86_64_82,
1757   X86_64_9A,
1758   X86_64_C4,
1759   X86_64_C5,
1760   X86_64_CE,
1761   X86_64_D4,
1762   X86_64_D5,
1763   X86_64_E8,
1764   X86_64_E9,
1765   X86_64_EA,
1766   X86_64_0F01_REG_0,
1767   X86_64_0F01_REG_1,
1768   X86_64_0F01_REG_2,
1769   X86_64_0F01_REG_3
1770 };
1771
1772 enum
1773 {
1774   THREE_BYTE_0F38 = 0,
1775   THREE_BYTE_0F3A
1776 };
1777
1778 enum
1779 {
1780   XOP_08 = 0,
1781   XOP_09,
1782   XOP_0A
1783 };
1784
1785 enum
1786 {
1787   VEX_0F = 0,
1788   VEX_0F38,
1789   VEX_0F3A
1790 };
1791
1792 enum
1793 {
1794   EVEX_0F = 0,
1795   EVEX_0F38,
1796   EVEX_0F3A
1797 };
1798
1799 enum
1800 {
1801   VEX_LEN_0F10_P_1 = 0,
1802   VEX_LEN_0F10_P_3,
1803   VEX_LEN_0F11_P_1,
1804   VEX_LEN_0F11_P_3,
1805   VEX_LEN_0F12_P_0_M_0,
1806   VEX_LEN_0F12_P_0_M_1,
1807   VEX_LEN_0F12_P_2,
1808   VEX_LEN_0F13_M_0,
1809   VEX_LEN_0F16_P_0_M_0,
1810   VEX_LEN_0F16_P_0_M_1,
1811   VEX_LEN_0F16_P_2,
1812   VEX_LEN_0F17_M_0,
1813   VEX_LEN_0F2A_P_1,
1814   VEX_LEN_0F2A_P_3,
1815   VEX_LEN_0F2C_P_1,
1816   VEX_LEN_0F2C_P_3,
1817   VEX_LEN_0F2D_P_1,
1818   VEX_LEN_0F2D_P_3,
1819   VEX_LEN_0F2E_P_0,
1820   VEX_LEN_0F2E_P_2,
1821   VEX_LEN_0F2F_P_0,
1822   VEX_LEN_0F2F_P_2,
1823   VEX_LEN_0F41_P_0,
1824   VEX_LEN_0F41_P_2,
1825   VEX_LEN_0F42_P_0,
1826   VEX_LEN_0F42_P_2,
1827   VEX_LEN_0F44_P_0,
1828   VEX_LEN_0F44_P_2,
1829   VEX_LEN_0F45_P_0,
1830   VEX_LEN_0F45_P_2,
1831   VEX_LEN_0F46_P_0,
1832   VEX_LEN_0F46_P_2,
1833   VEX_LEN_0F47_P_0,
1834   VEX_LEN_0F47_P_2,
1835   VEX_LEN_0F4A_P_0,
1836   VEX_LEN_0F4A_P_2,
1837   VEX_LEN_0F4B_P_0,
1838   VEX_LEN_0F4B_P_2,
1839   VEX_LEN_0F51_P_1,
1840   VEX_LEN_0F51_P_3,
1841   VEX_LEN_0F52_P_1,
1842   VEX_LEN_0F53_P_1,
1843   VEX_LEN_0F58_P_1,
1844   VEX_LEN_0F58_P_3,
1845   VEX_LEN_0F59_P_1,
1846   VEX_LEN_0F59_P_3,
1847   VEX_LEN_0F5A_P_1,
1848   VEX_LEN_0F5A_P_3,
1849   VEX_LEN_0F5C_P_1,
1850   VEX_LEN_0F5C_P_3,
1851   VEX_LEN_0F5D_P_1,
1852   VEX_LEN_0F5D_P_3,
1853   VEX_LEN_0F5E_P_1,
1854   VEX_LEN_0F5E_P_3,
1855   VEX_LEN_0F5F_P_1,
1856   VEX_LEN_0F5F_P_3,
1857   VEX_LEN_0F6E_P_2,
1858   VEX_LEN_0F7E_P_1,
1859   VEX_LEN_0F7E_P_2,
1860   VEX_LEN_0F90_P_0,
1861   VEX_LEN_0F90_P_2,
1862   VEX_LEN_0F91_P_0,
1863   VEX_LEN_0F91_P_2,
1864   VEX_LEN_0F92_P_0,
1865   VEX_LEN_0F92_P_2,
1866   VEX_LEN_0F92_P_3,
1867   VEX_LEN_0F93_P_0,
1868   VEX_LEN_0F93_P_2,
1869   VEX_LEN_0F93_P_3,
1870   VEX_LEN_0F98_P_0,
1871   VEX_LEN_0F98_P_2,
1872   VEX_LEN_0F99_P_0,
1873   VEX_LEN_0F99_P_2,
1874   VEX_LEN_0FAE_R_2_M_0,
1875   VEX_LEN_0FAE_R_3_M_0,
1876   VEX_LEN_0FC2_P_1,
1877   VEX_LEN_0FC2_P_3,
1878   VEX_LEN_0FC4_P_2,
1879   VEX_LEN_0FC5_P_2,
1880   VEX_LEN_0FD6_P_2,
1881   VEX_LEN_0FF7_P_2,
1882   VEX_LEN_0F3816_P_2,
1883   VEX_LEN_0F3819_P_2,
1884   VEX_LEN_0F381A_P_2_M_0,
1885   VEX_LEN_0F3836_P_2,
1886   VEX_LEN_0F3841_P_2,
1887   VEX_LEN_0F385A_P_2_M_0,
1888   VEX_LEN_0F38DB_P_2,
1889   VEX_LEN_0F38F2_P_0,
1890   VEX_LEN_0F38F3_R_1_P_0,
1891   VEX_LEN_0F38F3_R_2_P_0,
1892   VEX_LEN_0F38F3_R_3_P_0,
1893   VEX_LEN_0F38F5_P_0,
1894   VEX_LEN_0F38F5_P_1,
1895   VEX_LEN_0F38F5_P_3,
1896   VEX_LEN_0F38F6_P_3,
1897   VEX_LEN_0F38F7_P_0,
1898   VEX_LEN_0F38F7_P_1,
1899   VEX_LEN_0F38F7_P_2,
1900   VEX_LEN_0F38F7_P_3,
1901   VEX_LEN_0F3A00_P_2,
1902   VEX_LEN_0F3A01_P_2,
1903   VEX_LEN_0F3A06_P_2,
1904   VEX_LEN_0F3A0A_P_2,
1905   VEX_LEN_0F3A0B_P_2,
1906   VEX_LEN_0F3A14_P_2,
1907   VEX_LEN_0F3A15_P_2,
1908   VEX_LEN_0F3A16_P_2,
1909   VEX_LEN_0F3A17_P_2,
1910   VEX_LEN_0F3A18_P_2,
1911   VEX_LEN_0F3A19_P_2,
1912   VEX_LEN_0F3A20_P_2,
1913   VEX_LEN_0F3A21_P_2,
1914   VEX_LEN_0F3A22_P_2,
1915   VEX_LEN_0F3A30_P_2,
1916   VEX_LEN_0F3A31_P_2,
1917   VEX_LEN_0F3A32_P_2,
1918   VEX_LEN_0F3A33_P_2,
1919   VEX_LEN_0F3A38_P_2,
1920   VEX_LEN_0F3A39_P_2,
1921   VEX_LEN_0F3A41_P_2,
1922   VEX_LEN_0F3A46_P_2,
1923   VEX_LEN_0F3A60_P_2,
1924   VEX_LEN_0F3A61_P_2,
1925   VEX_LEN_0F3A62_P_2,
1926   VEX_LEN_0F3A63_P_2,
1927   VEX_LEN_0F3A6A_P_2,
1928   VEX_LEN_0F3A6B_P_2,
1929   VEX_LEN_0F3A6E_P_2,
1930   VEX_LEN_0F3A6F_P_2,
1931   VEX_LEN_0F3A7A_P_2,
1932   VEX_LEN_0F3A7B_P_2,
1933   VEX_LEN_0F3A7E_P_2,
1934   VEX_LEN_0F3A7F_P_2,
1935   VEX_LEN_0F3ADF_P_2,
1936   VEX_LEN_0F3AF0_P_3,
1937   VEX_LEN_0FXOP_08_CC,
1938   VEX_LEN_0FXOP_08_CD,
1939   VEX_LEN_0FXOP_08_CE,
1940   VEX_LEN_0FXOP_08_CF,
1941   VEX_LEN_0FXOP_08_EC,
1942   VEX_LEN_0FXOP_08_ED,
1943   VEX_LEN_0FXOP_08_EE,
1944   VEX_LEN_0FXOP_08_EF,
1945   VEX_LEN_0FXOP_09_80,
1946   VEX_LEN_0FXOP_09_81
1947 };
1948
1949 enum
1950 {
1951   VEX_W_0F10_P_0 = 0,
1952   VEX_W_0F10_P_1,
1953   VEX_W_0F10_P_2,
1954   VEX_W_0F10_P_3,
1955   VEX_W_0F11_P_0,
1956   VEX_W_0F11_P_1,
1957   VEX_W_0F11_P_2,
1958   VEX_W_0F11_P_3,
1959   VEX_W_0F12_P_0_M_0,
1960   VEX_W_0F12_P_0_M_1,
1961   VEX_W_0F12_P_1,
1962   VEX_W_0F12_P_2,
1963   VEX_W_0F12_P_3,
1964   VEX_W_0F13_M_0,
1965   VEX_W_0F14,
1966   VEX_W_0F15,
1967   VEX_W_0F16_P_0_M_0,
1968   VEX_W_0F16_P_0_M_1,
1969   VEX_W_0F16_P_1,
1970   VEX_W_0F16_P_2,
1971   VEX_W_0F17_M_0,
1972   VEX_W_0F28,
1973   VEX_W_0F29,
1974   VEX_W_0F2B_M_0,
1975   VEX_W_0F2E_P_0,
1976   VEX_W_0F2E_P_2,
1977   VEX_W_0F2F_P_0,
1978   VEX_W_0F2F_P_2,
1979   VEX_W_0F41_P_0_LEN_1,
1980   VEX_W_0F41_P_2_LEN_1,
1981   VEX_W_0F42_P_0_LEN_1,
1982   VEX_W_0F42_P_2_LEN_1,
1983   VEX_W_0F44_P_0_LEN_0,
1984   VEX_W_0F44_P_2_LEN_0,
1985   VEX_W_0F45_P_0_LEN_1,
1986   VEX_W_0F45_P_2_LEN_1,
1987   VEX_W_0F46_P_0_LEN_1,
1988   VEX_W_0F46_P_2_LEN_1,
1989   VEX_W_0F47_P_0_LEN_1,
1990   VEX_W_0F47_P_2_LEN_1,
1991   VEX_W_0F4A_P_0_LEN_1,
1992   VEX_W_0F4A_P_2_LEN_1,
1993   VEX_W_0F4B_P_0_LEN_1,
1994   VEX_W_0F4B_P_2_LEN_1,
1995   VEX_W_0F50_M_0,
1996   VEX_W_0F51_P_0,
1997   VEX_W_0F51_P_1,
1998   VEX_W_0F51_P_2,
1999   VEX_W_0F51_P_3,
2000   VEX_W_0F52_P_0,
2001   VEX_W_0F52_P_1,
2002   VEX_W_0F53_P_0,
2003   VEX_W_0F53_P_1,
2004   VEX_W_0F58_P_0,
2005   VEX_W_0F58_P_1,
2006   VEX_W_0F58_P_2,
2007   VEX_W_0F58_P_3,
2008   VEX_W_0F59_P_0,
2009   VEX_W_0F59_P_1,
2010   VEX_W_0F59_P_2,
2011   VEX_W_0F59_P_3,
2012   VEX_W_0F5A_P_0,
2013   VEX_W_0F5A_P_1,
2014   VEX_W_0F5A_P_3,
2015   VEX_W_0F5B_P_0,
2016   VEX_W_0F5B_P_1,
2017   VEX_W_0F5B_P_2,
2018   VEX_W_0F5C_P_0,
2019   VEX_W_0F5C_P_1,
2020   VEX_W_0F5C_P_2,
2021   VEX_W_0F5C_P_3,
2022   VEX_W_0F5D_P_0,
2023   VEX_W_0F5D_P_1,
2024   VEX_W_0F5D_P_2,
2025   VEX_W_0F5D_P_3,
2026   VEX_W_0F5E_P_0,
2027   VEX_W_0F5E_P_1,
2028   VEX_W_0F5E_P_2,
2029   VEX_W_0F5E_P_3,
2030   VEX_W_0F5F_P_0,
2031   VEX_W_0F5F_P_1,
2032   VEX_W_0F5F_P_2,
2033   VEX_W_0F5F_P_3,
2034   VEX_W_0F60_P_2,
2035   VEX_W_0F61_P_2,
2036   VEX_W_0F62_P_2,
2037   VEX_W_0F63_P_2,
2038   VEX_W_0F64_P_2,
2039   VEX_W_0F65_P_2,
2040   VEX_W_0F66_P_2,
2041   VEX_W_0F67_P_2,
2042   VEX_W_0F68_P_2,
2043   VEX_W_0F69_P_2,
2044   VEX_W_0F6A_P_2,
2045   VEX_W_0F6B_P_2,
2046   VEX_W_0F6C_P_2,
2047   VEX_W_0F6D_P_2,
2048   VEX_W_0F6F_P_1,
2049   VEX_W_0F6F_P_2,
2050   VEX_W_0F70_P_1,
2051   VEX_W_0F70_P_2,
2052   VEX_W_0F70_P_3,
2053   VEX_W_0F71_R_2_P_2,
2054   VEX_W_0F71_R_4_P_2,
2055   VEX_W_0F71_R_6_P_2,
2056   VEX_W_0F72_R_2_P_2,
2057   VEX_W_0F72_R_4_P_2,
2058   VEX_W_0F72_R_6_P_2,
2059   VEX_W_0F73_R_2_P_2,
2060   VEX_W_0F73_R_3_P_2,
2061   VEX_W_0F73_R_6_P_2,
2062   VEX_W_0F73_R_7_P_2,
2063   VEX_W_0F74_P_2,
2064   VEX_W_0F75_P_2,
2065   VEX_W_0F76_P_2,
2066   VEX_W_0F77_P_0,
2067   VEX_W_0F7C_P_2,
2068   VEX_W_0F7C_P_3,
2069   VEX_W_0F7D_P_2,
2070   VEX_W_0F7D_P_3,
2071   VEX_W_0F7E_P_1,
2072   VEX_W_0F7F_P_1,
2073   VEX_W_0F7F_P_2,
2074   VEX_W_0F90_P_0_LEN_0,
2075   VEX_W_0F90_P_2_LEN_0,
2076   VEX_W_0F91_P_0_LEN_0,
2077   VEX_W_0F91_P_2_LEN_0,
2078   VEX_W_0F92_P_0_LEN_0,
2079   VEX_W_0F92_P_2_LEN_0,
2080   VEX_W_0F92_P_3_LEN_0,
2081   VEX_W_0F93_P_0_LEN_0,
2082   VEX_W_0F93_P_2_LEN_0,
2083   VEX_W_0F93_P_3_LEN_0,
2084   VEX_W_0F98_P_0_LEN_0,
2085   VEX_W_0F98_P_2_LEN_0,
2086   VEX_W_0F99_P_0_LEN_0,
2087   VEX_W_0F99_P_2_LEN_0,
2088   VEX_W_0FAE_R_2_M_0,
2089   VEX_W_0FAE_R_3_M_0,
2090   VEX_W_0FC2_P_0,
2091   VEX_W_0FC2_P_1,
2092   VEX_W_0FC2_P_2,
2093   VEX_W_0FC2_P_3,
2094   VEX_W_0FC4_P_2,
2095   VEX_W_0FC5_P_2,
2096   VEX_W_0FD0_P_2,
2097   VEX_W_0FD0_P_3,
2098   VEX_W_0FD1_P_2,
2099   VEX_W_0FD2_P_2,
2100   VEX_W_0FD3_P_2,
2101   VEX_W_0FD4_P_2,
2102   VEX_W_0FD5_P_2,
2103   VEX_W_0FD6_P_2,
2104   VEX_W_0FD7_P_2_M_1,
2105   VEX_W_0FD8_P_2,
2106   VEX_W_0FD9_P_2,
2107   VEX_W_0FDA_P_2,
2108   VEX_W_0FDB_P_2,
2109   VEX_W_0FDC_P_2,
2110   VEX_W_0FDD_P_2,
2111   VEX_W_0FDE_P_2,
2112   VEX_W_0FDF_P_2,
2113   VEX_W_0FE0_P_2,
2114   VEX_W_0FE1_P_2,
2115   VEX_W_0FE2_P_2,
2116   VEX_W_0FE3_P_2,
2117   VEX_W_0FE4_P_2,
2118   VEX_W_0FE5_P_2,
2119   VEX_W_0FE6_P_1,
2120   VEX_W_0FE6_P_2,
2121   VEX_W_0FE6_P_3,
2122   VEX_W_0FE7_P_2_M_0,
2123   VEX_W_0FE8_P_2,
2124   VEX_W_0FE9_P_2,
2125   VEX_W_0FEA_P_2,
2126   VEX_W_0FEB_P_2,
2127   VEX_W_0FEC_P_2,
2128   VEX_W_0FED_P_2,
2129   VEX_W_0FEE_P_2,
2130   VEX_W_0FEF_P_2,
2131   VEX_W_0FF0_P_3_M_0,
2132   VEX_W_0FF1_P_2,
2133   VEX_W_0FF2_P_2,
2134   VEX_W_0FF3_P_2,
2135   VEX_W_0FF4_P_2,
2136   VEX_W_0FF5_P_2,
2137   VEX_W_0FF6_P_2,
2138   VEX_W_0FF7_P_2,
2139   VEX_W_0FF8_P_2,
2140   VEX_W_0FF9_P_2,
2141   VEX_W_0FFA_P_2,
2142   VEX_W_0FFB_P_2,
2143   VEX_W_0FFC_P_2,
2144   VEX_W_0FFD_P_2,
2145   VEX_W_0FFE_P_2,
2146   VEX_W_0F3800_P_2,
2147   VEX_W_0F3801_P_2,
2148   VEX_W_0F3802_P_2,
2149   VEX_W_0F3803_P_2,
2150   VEX_W_0F3804_P_2,
2151   VEX_W_0F3805_P_2,
2152   VEX_W_0F3806_P_2,
2153   VEX_W_0F3807_P_2,
2154   VEX_W_0F3808_P_2,
2155   VEX_W_0F3809_P_2,
2156   VEX_W_0F380A_P_2,
2157   VEX_W_0F380B_P_2,
2158   VEX_W_0F380C_P_2,
2159   VEX_W_0F380D_P_2,
2160   VEX_W_0F380E_P_2,
2161   VEX_W_0F380F_P_2,
2162   VEX_W_0F3816_P_2,
2163   VEX_W_0F3817_P_2,
2164   VEX_W_0F3818_P_2,
2165   VEX_W_0F3819_P_2,
2166   VEX_W_0F381A_P_2_M_0,
2167   VEX_W_0F381C_P_2,
2168   VEX_W_0F381D_P_2,
2169   VEX_W_0F381E_P_2,
2170   VEX_W_0F3820_P_2,
2171   VEX_W_0F3821_P_2,
2172   VEX_W_0F3822_P_2,
2173   VEX_W_0F3823_P_2,
2174   VEX_W_0F3824_P_2,
2175   VEX_W_0F3825_P_2,
2176   VEX_W_0F3828_P_2,
2177   VEX_W_0F3829_P_2,
2178   VEX_W_0F382A_P_2_M_0,
2179   VEX_W_0F382B_P_2,
2180   VEX_W_0F382C_P_2_M_0,
2181   VEX_W_0F382D_P_2_M_0,
2182   VEX_W_0F382E_P_2_M_0,
2183   VEX_W_0F382F_P_2_M_0,
2184   VEX_W_0F3830_P_2,
2185   VEX_W_0F3831_P_2,
2186   VEX_W_0F3832_P_2,
2187   VEX_W_0F3833_P_2,
2188   VEX_W_0F3834_P_2,
2189   VEX_W_0F3835_P_2,
2190   VEX_W_0F3836_P_2,
2191   VEX_W_0F3837_P_2,
2192   VEX_W_0F3838_P_2,
2193   VEX_W_0F3839_P_2,
2194   VEX_W_0F383A_P_2,
2195   VEX_W_0F383B_P_2,
2196   VEX_W_0F383C_P_2,
2197   VEX_W_0F383D_P_2,
2198   VEX_W_0F383E_P_2,
2199   VEX_W_0F383F_P_2,
2200   VEX_W_0F3840_P_2,
2201   VEX_W_0F3841_P_2,
2202   VEX_W_0F3846_P_2,
2203   VEX_W_0F3858_P_2,
2204   VEX_W_0F3859_P_2,
2205   VEX_W_0F385A_P_2_M_0,
2206   VEX_W_0F3878_P_2,
2207   VEX_W_0F3879_P_2,
2208   VEX_W_0F38CF_P_2,
2209   VEX_W_0F38DB_P_2,
2210   VEX_W_0F3A00_P_2,
2211   VEX_W_0F3A01_P_2,
2212   VEX_W_0F3A02_P_2,
2213   VEX_W_0F3A04_P_2,
2214   VEX_W_0F3A05_P_2,
2215   VEX_W_0F3A06_P_2,
2216   VEX_W_0F3A08_P_2,
2217   VEX_W_0F3A09_P_2,
2218   VEX_W_0F3A0A_P_2,
2219   VEX_W_0F3A0B_P_2,
2220   VEX_W_0F3A0C_P_2,
2221   VEX_W_0F3A0D_P_2,
2222   VEX_W_0F3A0E_P_2,
2223   VEX_W_0F3A0F_P_2,
2224   VEX_W_0F3A14_P_2,
2225   VEX_W_0F3A15_P_2,
2226   VEX_W_0F3A18_P_2,
2227   VEX_W_0F3A19_P_2,
2228   VEX_W_0F3A20_P_2,
2229   VEX_W_0F3A21_P_2,
2230   VEX_W_0F3A30_P_2_LEN_0,
2231   VEX_W_0F3A31_P_2_LEN_0,
2232   VEX_W_0F3A32_P_2_LEN_0,
2233   VEX_W_0F3A33_P_2_LEN_0,
2234   VEX_W_0F3A38_P_2,
2235   VEX_W_0F3A39_P_2,
2236   VEX_W_0F3A40_P_2,
2237   VEX_W_0F3A41_P_2,
2238   VEX_W_0F3A42_P_2,
2239   VEX_W_0F3A46_P_2,
2240   VEX_W_0F3A48_P_2,
2241   VEX_W_0F3A49_P_2,
2242   VEX_W_0F3A4A_P_2,
2243   VEX_W_0F3A4B_P_2,
2244   VEX_W_0F3A4C_P_2,
2245   VEX_W_0F3A62_P_2,
2246   VEX_W_0F3A63_P_2,
2247   VEX_W_0F3ACE_P_2,
2248   VEX_W_0F3ACF_P_2,
2249   VEX_W_0F3ADF_P_2,
2250
2251   EVEX_W_0F10_P_0,
2252   EVEX_W_0F10_P_1_M_0,
2253   EVEX_W_0F10_P_1_M_1,
2254   EVEX_W_0F10_P_2,
2255   EVEX_W_0F10_P_3_M_0,
2256   EVEX_W_0F10_P_3_M_1,
2257   EVEX_W_0F11_P_0,
2258   EVEX_W_0F11_P_1_M_0,
2259   EVEX_W_0F11_P_1_M_1,
2260   EVEX_W_0F11_P_2,
2261   EVEX_W_0F11_P_3_M_0,
2262   EVEX_W_0F11_P_3_M_1,
2263   EVEX_W_0F12_P_0_M_0,
2264   EVEX_W_0F12_P_0_M_1,
2265   EVEX_W_0F12_P_1,
2266   EVEX_W_0F12_P_2,
2267   EVEX_W_0F12_P_3,
2268   EVEX_W_0F13_P_0,
2269   EVEX_W_0F13_P_2,
2270   EVEX_W_0F14_P_0,
2271   EVEX_W_0F14_P_2,
2272   EVEX_W_0F15_P_0,
2273   EVEX_W_0F15_P_2,
2274   EVEX_W_0F16_P_0_M_0,
2275   EVEX_W_0F16_P_0_M_1,
2276   EVEX_W_0F16_P_1,
2277   EVEX_W_0F16_P_2,
2278   EVEX_W_0F17_P_0,
2279   EVEX_W_0F17_P_2,
2280   EVEX_W_0F28_P_0,
2281   EVEX_W_0F28_P_2,
2282   EVEX_W_0F29_P_0,
2283   EVEX_W_0F29_P_2,
2284   EVEX_W_0F2A_P_1,
2285   EVEX_W_0F2A_P_3,
2286   EVEX_W_0F2B_P_0,
2287   EVEX_W_0F2B_P_2,
2288   EVEX_W_0F2E_P_0,
2289   EVEX_W_0F2E_P_2,
2290   EVEX_W_0F2F_P_0,
2291   EVEX_W_0F2F_P_2,
2292   EVEX_W_0F51_P_0,
2293   EVEX_W_0F51_P_1,
2294   EVEX_W_0F51_P_2,
2295   EVEX_W_0F51_P_3,
2296   EVEX_W_0F54_P_0,
2297   EVEX_W_0F54_P_2,
2298   EVEX_W_0F55_P_0,
2299   EVEX_W_0F55_P_2,
2300   EVEX_W_0F56_P_0,
2301   EVEX_W_0F56_P_2,
2302   EVEX_W_0F57_P_0,
2303   EVEX_W_0F57_P_2,
2304   EVEX_W_0F58_P_0,
2305   EVEX_W_0F58_P_1,
2306   EVEX_W_0F58_P_2,
2307   EVEX_W_0F58_P_3,
2308   EVEX_W_0F59_P_0,
2309   EVEX_W_0F59_P_1,
2310   EVEX_W_0F59_P_2,
2311   EVEX_W_0F59_P_3,
2312   EVEX_W_0F5A_P_0,
2313   EVEX_W_0F5A_P_1,
2314   EVEX_W_0F5A_P_2,
2315   EVEX_W_0F5A_P_3,
2316   EVEX_W_0F5B_P_0,
2317   EVEX_W_0F5B_P_1,
2318   EVEX_W_0F5B_P_2,
2319   EVEX_W_0F5C_P_0,
2320   EVEX_W_0F5C_P_1,
2321   EVEX_W_0F5C_P_2,
2322   EVEX_W_0F5C_P_3,
2323   EVEX_W_0F5D_P_0,
2324   EVEX_W_0F5D_P_1,
2325   EVEX_W_0F5D_P_2,
2326   EVEX_W_0F5D_P_3,
2327   EVEX_W_0F5E_P_0,
2328   EVEX_W_0F5E_P_1,
2329   EVEX_W_0F5E_P_2,
2330   EVEX_W_0F5E_P_3,
2331   EVEX_W_0F5F_P_0,
2332   EVEX_W_0F5F_P_1,
2333   EVEX_W_0F5F_P_2,
2334   EVEX_W_0F5F_P_3,
2335   EVEX_W_0F62_P_2,
2336   EVEX_W_0F66_P_2,
2337   EVEX_W_0F6A_P_2,
2338   EVEX_W_0F6B_P_2,
2339   EVEX_W_0F6C_P_2,
2340   EVEX_W_0F6D_P_2,
2341   EVEX_W_0F6E_P_2,
2342   EVEX_W_0F6F_P_1,
2343   EVEX_W_0F6F_P_2,
2344   EVEX_W_0F6F_P_3,
2345   EVEX_W_0F70_P_2,
2346   EVEX_W_0F72_R_2_P_2,
2347   EVEX_W_0F72_R_6_P_2,
2348   EVEX_W_0F73_R_2_P_2,
2349   EVEX_W_0F73_R_6_P_2,
2350   EVEX_W_0F76_P_2,
2351   EVEX_W_0F78_P_0,
2352   EVEX_W_0F78_P_2,
2353   EVEX_W_0F79_P_0,
2354   EVEX_W_0F79_P_2,
2355   EVEX_W_0F7A_P_1,
2356   EVEX_W_0F7A_P_2,
2357   EVEX_W_0F7A_P_3,
2358   EVEX_W_0F7B_P_1,
2359   EVEX_W_0F7B_P_2,
2360   EVEX_W_0F7B_P_3,
2361   EVEX_W_0F7E_P_1,
2362   EVEX_W_0F7E_P_2,
2363   EVEX_W_0F7F_P_1,
2364   EVEX_W_0F7F_P_2,
2365   EVEX_W_0F7F_P_3,
2366   EVEX_W_0FC2_P_0,
2367   EVEX_W_0FC2_P_1,
2368   EVEX_W_0FC2_P_2,
2369   EVEX_W_0FC2_P_3,
2370   EVEX_W_0FC6_P_0,
2371   EVEX_W_0FC6_P_2,
2372   EVEX_W_0FD2_P_2,
2373   EVEX_W_0FD3_P_2,
2374   EVEX_W_0FD4_P_2,
2375   EVEX_W_0FD6_P_2,
2376   EVEX_W_0FE6_P_1,
2377   EVEX_W_0FE6_P_2,
2378   EVEX_W_0FE6_P_3,
2379   EVEX_W_0FE7_P_2,
2380   EVEX_W_0FF2_P_2,
2381   EVEX_W_0FF3_P_2,
2382   EVEX_W_0FF4_P_2,
2383   EVEX_W_0FFA_P_2,
2384   EVEX_W_0FFB_P_2,
2385   EVEX_W_0FFE_P_2,
2386   EVEX_W_0F380C_P_2,
2387   EVEX_W_0F380D_P_2,
2388   EVEX_W_0F3810_P_1,
2389   EVEX_W_0F3810_P_2,
2390   EVEX_W_0F3811_P_1,
2391   EVEX_W_0F3811_P_2,
2392   EVEX_W_0F3812_P_1,
2393   EVEX_W_0F3812_P_2,
2394   EVEX_W_0F3813_P_1,
2395   EVEX_W_0F3813_P_2,
2396   EVEX_W_0F3814_P_1,
2397   EVEX_W_0F3815_P_1,
2398   EVEX_W_0F3818_P_2,
2399   EVEX_W_0F3819_P_2,
2400   EVEX_W_0F381A_P_2,
2401   EVEX_W_0F381B_P_2,
2402   EVEX_W_0F381E_P_2,
2403   EVEX_W_0F381F_P_2,
2404   EVEX_W_0F3820_P_1,
2405   EVEX_W_0F3821_P_1,
2406   EVEX_W_0F3822_P_1,
2407   EVEX_W_0F3823_P_1,
2408   EVEX_W_0F3824_P_1,
2409   EVEX_W_0F3825_P_1,
2410   EVEX_W_0F3825_P_2,
2411   EVEX_W_0F3826_P_1,
2412   EVEX_W_0F3826_P_2,
2413   EVEX_W_0F3828_P_1,
2414   EVEX_W_0F3828_P_2,
2415   EVEX_W_0F3829_P_1,
2416   EVEX_W_0F3829_P_2,
2417   EVEX_W_0F382A_P_1,
2418   EVEX_W_0F382A_P_2,
2419   EVEX_W_0F382B_P_2,
2420   EVEX_W_0F3830_P_1,
2421   EVEX_W_0F3831_P_1,
2422   EVEX_W_0F3832_P_1,
2423   EVEX_W_0F3833_P_1,
2424   EVEX_W_0F3834_P_1,
2425   EVEX_W_0F3835_P_1,
2426   EVEX_W_0F3835_P_2,
2427   EVEX_W_0F3837_P_2,
2428   EVEX_W_0F3838_P_1,
2429   EVEX_W_0F3839_P_1,
2430   EVEX_W_0F383A_P_1,
2431   EVEX_W_0F3840_P_2,
2432   EVEX_W_0F3854_P_2,
2433   EVEX_W_0F3855_P_2,
2434   EVEX_W_0F3858_P_2,
2435   EVEX_W_0F3859_P_2,
2436   EVEX_W_0F385A_P_2,
2437   EVEX_W_0F385B_P_2,
2438   EVEX_W_0F3862_P_2,
2439   EVEX_W_0F3863_P_2,
2440   EVEX_W_0F3866_P_2,
2441   EVEX_W_0F3870_P_2,
2442   EVEX_W_0F3871_P_2,
2443   EVEX_W_0F3872_P_2,
2444   EVEX_W_0F3873_P_2,
2445   EVEX_W_0F3875_P_2,
2446   EVEX_W_0F3878_P_2,
2447   EVEX_W_0F3879_P_2,
2448   EVEX_W_0F387A_P_2,
2449   EVEX_W_0F387B_P_2,
2450   EVEX_W_0F387D_P_2,
2451   EVEX_W_0F3883_P_2,
2452   EVEX_W_0F388D_P_2,
2453   EVEX_W_0F3891_P_2,
2454   EVEX_W_0F3893_P_2,
2455   EVEX_W_0F38A1_P_2,
2456   EVEX_W_0F38A3_P_2,
2457   EVEX_W_0F38C7_R_1_P_2,
2458   EVEX_W_0F38C7_R_2_P_2,
2459   EVEX_W_0F38C7_R_5_P_2,
2460   EVEX_W_0F38C7_R_6_P_2,
2461
2462   EVEX_W_0F3A00_P_2,
2463   EVEX_W_0F3A01_P_2,
2464   EVEX_W_0F3A04_P_2,
2465   EVEX_W_0F3A05_P_2,
2466   EVEX_W_0F3A08_P_2,
2467   EVEX_W_0F3A09_P_2,
2468   EVEX_W_0F3A0A_P_2,
2469   EVEX_W_0F3A0B_P_2,
2470   EVEX_W_0F3A16_P_2,
2471   EVEX_W_0F3A18_P_2,
2472   EVEX_W_0F3A19_P_2,
2473   EVEX_W_0F3A1A_P_2,
2474   EVEX_W_0F3A1B_P_2,
2475   EVEX_W_0F3A1D_P_2,
2476   EVEX_W_0F3A21_P_2,
2477   EVEX_W_0F3A22_P_2,
2478   EVEX_W_0F3A23_P_2,
2479   EVEX_W_0F3A38_P_2,
2480   EVEX_W_0F3A39_P_2,
2481   EVEX_W_0F3A3A_P_2,
2482   EVEX_W_0F3A3B_P_2,
2483   EVEX_W_0F3A3E_P_2,
2484   EVEX_W_0F3A3F_P_2,
2485   EVEX_W_0F3A42_P_2,
2486   EVEX_W_0F3A43_P_2,
2487   EVEX_W_0F3A50_P_2,
2488   EVEX_W_0F3A51_P_2,
2489   EVEX_W_0F3A56_P_2,
2490   EVEX_W_0F3A57_P_2,
2491   EVEX_W_0F3A66_P_2,
2492   EVEX_W_0F3A67_P_2,
2493   EVEX_W_0F3A70_P_2,
2494   EVEX_W_0F3A71_P_2,
2495   EVEX_W_0F3A72_P_2,
2496   EVEX_W_0F3A73_P_2,
2497   EVEX_W_0F3ACE_P_2,
2498   EVEX_W_0F3ACF_P_2
2499 };
2500
2501 typedef void (*op_rtn) (int bytemode, int sizeflag);
2502
2503 struct dis386 {
2504   const char *name;
2505   struct
2506     {
2507       op_rtn rtn;
2508       int bytemode;
2509     } op[MAX_OPERANDS];
2510   unsigned int prefix_requirement;
2511 };
2512
2513 /* Upper case letters in the instruction names here are macros.
2514    'A' => print 'b' if no register operands or suffix_always is true
2515    'B' => print 'b' if suffix_always is true
2516    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2517           size prefix
2518    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2519           suffix_always is true
2520    'E' => print 'e' if 32-bit form of jcxz
2521    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2522    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2523    'H' => print ",pt" or ",pn" branch hint
2524    'I' => honor following macro letter even in Intel mode (implemented only
2525           for some of the macro letters)
2526    'J' => print 'l'
2527    'K' => print 'd' or 'q' if rex prefix is present.
2528    'L' => print 'l' if suffix_always is true
2529    'M' => print 'r' if intel_mnemonic is false.
2530    'N' => print 'n' if instruction has no wait "prefix"
2531    'O' => print 'd' or 'o' (or 'q' in Intel mode)
2532    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2533           or suffix_always is true.  print 'q' if rex prefix is present.
2534    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2535           is true
2536    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2537    'S' => print 'w', 'l' or 'q' if suffix_always is true
2538    'T' => print 'q' in 64bit mode if instruction has no operand size
2539           prefix and behave as 'P' otherwise
2540    'U' => print 'q' in 64bit mode if instruction has no operand size
2541           prefix and behave as 'Q' otherwise
2542    'V' => print 'q' in 64bit mode if instruction has no operand size
2543           prefix and behave as 'S' otherwise
2544    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2545    'X' => print 's', 'd' depending on data16 prefix (for XMM)
2546    'Y' unused.
2547    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2548    '!' => change condition from true to false or from false to true.
2549    '%' => add 1 upper case letter to the macro.
2550    '^' => print 'w' or 'l' depending on operand size prefix or
2551           suffix_always is true (lcall/ljmp).
2552    '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2553           on operand size prefix.
2554    '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2555           has no operand size prefix for AMD64 ISA, behave as 'P'
2556           otherwise
2557
2558    2 upper case letter macros:
2559    "XY" => print 'x' or 'y' if suffix_always is true or no register
2560            operands and no broadcast.
2561    "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2562            register operands and no broadcast.
2563    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2564    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2565            or suffix_always is true
2566    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2567    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2568    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2569    "LW" => print 'd', 'q' depending on the VEX.W bit
2570    "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2571            an operand size prefix, or suffix_always is true.  print
2572            'q' if rex prefix is present.
2573
2574    Many of the above letters print nothing in Intel mode.  See "putop"
2575    for the details.
2576
2577    Braces '{' and '}', and vertical bars '|', indicate alternative
2578    mnemonic strings for AT&T and Intel.  */
2579
2580 static const struct dis386 dis386[] = {
2581   /* 00 */
2582   { "addB",             { Ebh1, Gb }, 0 },
2583   { "addS",             { Evh1, Gv }, 0 },
2584   { "addB",             { Gb, EbS }, 0 },
2585   { "addS",             { Gv, EvS }, 0 },
2586   { "addB",             { AL, Ib }, 0 },
2587   { "addS",             { eAX, Iv }, 0 },
2588   { X86_64_TABLE (X86_64_06) },
2589   { X86_64_TABLE (X86_64_07) },
2590   /* 08 */
2591   { "orB",              { Ebh1, Gb }, 0 },
2592   { "orS",              { Evh1, Gv }, 0 },
2593   { "orB",              { Gb, EbS }, 0 },
2594   { "orS",              { Gv, EvS }, 0 },
2595   { "orB",              { AL, Ib }, 0 },
2596   { "orS",              { eAX, Iv }, 0 },
2597   { X86_64_TABLE (X86_64_0D) },
2598   { Bad_Opcode },       /* 0x0f extended opcode escape */
2599   /* 10 */
2600   { "adcB",             { Ebh1, Gb }, 0 },
2601   { "adcS",             { Evh1, Gv }, 0 },
2602   { "adcB",             { Gb, EbS }, 0 },
2603   { "adcS",             { Gv, EvS }, 0 },
2604   { "adcB",             { AL, Ib }, 0 },
2605   { "adcS",             { eAX, Iv }, 0 },
2606   { X86_64_TABLE (X86_64_16) },
2607   { X86_64_TABLE (X86_64_17) },
2608   /* 18 */
2609   { "sbbB",             { Ebh1, Gb }, 0 },
2610   { "sbbS",             { Evh1, Gv }, 0 },
2611   { "sbbB",             { Gb, EbS }, 0 },
2612   { "sbbS",             { Gv, EvS }, 0 },
2613   { "sbbB",             { AL, Ib }, 0 },
2614   { "sbbS",             { eAX, Iv }, 0 },
2615   { X86_64_TABLE (X86_64_1E) },
2616   { X86_64_TABLE (X86_64_1F) },
2617   /* 20 */
2618   { "andB",             { Ebh1, Gb }, 0 },
2619   { "andS",             { Evh1, Gv }, 0 },
2620   { "andB",             { Gb, EbS }, 0 },
2621   { "andS",             { Gv, EvS }, 0 },
2622   { "andB",             { AL, Ib }, 0 },
2623   { "andS",             { eAX, Iv }, 0 },
2624   { Bad_Opcode },       /* SEG ES prefix */
2625   { X86_64_TABLE (X86_64_27) },
2626   /* 28 */
2627   { "subB",             { Ebh1, Gb }, 0 },
2628   { "subS",             { Evh1, Gv }, 0 },
2629   { "subB",             { Gb, EbS }, 0 },
2630   { "subS",             { Gv, EvS }, 0 },
2631   { "subB",             { AL, Ib }, 0 },
2632   { "subS",             { eAX, Iv }, 0 },
2633   { Bad_Opcode },       /* SEG CS prefix */
2634   { X86_64_TABLE (X86_64_2F) },
2635   /* 30 */
2636   { "xorB",             { Ebh1, Gb }, 0 },
2637   { "xorS",             { Evh1, Gv }, 0 },
2638   { "xorB",             { Gb, EbS }, 0 },
2639   { "xorS",             { Gv, EvS }, 0 },
2640   { "xorB",             { AL, Ib }, 0 },
2641   { "xorS",             { eAX, Iv }, 0 },
2642   { Bad_Opcode },       /* SEG SS prefix */
2643   { X86_64_TABLE (X86_64_37) },
2644   /* 38 */
2645   { "cmpB",             { Eb, Gb }, 0 },
2646   { "cmpS",             { Ev, Gv }, 0 },
2647   { "cmpB",             { Gb, EbS }, 0 },
2648   { "cmpS",             { Gv, EvS }, 0 },
2649   { "cmpB",             { AL, Ib }, 0 },
2650   { "cmpS",             { eAX, Iv }, 0 },
2651   { Bad_Opcode },       /* SEG DS prefix */
2652   { X86_64_TABLE (X86_64_3F) },
2653   /* 40 */
2654   { "inc{S|}",          { RMeAX }, 0 },
2655   { "inc{S|}",          { RMeCX }, 0 },
2656   { "inc{S|}",          { RMeDX }, 0 },
2657   { "inc{S|}",          { RMeBX }, 0 },
2658   { "inc{S|}",          { RMeSP }, 0 },
2659   { "inc{S|}",          { RMeBP }, 0 },
2660   { "inc{S|}",          { RMeSI }, 0 },
2661   { "inc{S|}",          { RMeDI }, 0 },
2662   /* 48 */
2663   { "dec{S|}",          { RMeAX }, 0 },
2664   { "dec{S|}",          { RMeCX }, 0 },
2665   { "dec{S|}",          { RMeDX }, 0 },
2666   { "dec{S|}",          { RMeBX }, 0 },
2667   { "dec{S|}",          { RMeSP }, 0 },
2668   { "dec{S|}",          { RMeBP }, 0 },
2669   { "dec{S|}",          { RMeSI }, 0 },
2670   { "dec{S|}",          { RMeDI }, 0 },
2671   /* 50 */
2672   { "pushV",            { RMrAX }, 0 },
2673   { "pushV",            { RMrCX }, 0 },
2674   { "pushV",            { RMrDX }, 0 },
2675   { "pushV",            { RMrBX }, 0 },
2676   { "pushV",            { RMrSP }, 0 },
2677   { "pushV",            { RMrBP }, 0 },
2678   { "pushV",            { RMrSI }, 0 },
2679   { "pushV",            { RMrDI }, 0 },
2680   /* 58 */
2681   { "popV",             { RMrAX }, 0 },
2682   { "popV",             { RMrCX }, 0 },
2683   { "popV",             { RMrDX }, 0 },
2684   { "popV",             { RMrBX }, 0 },
2685   { "popV",             { RMrSP }, 0 },
2686   { "popV",             { RMrBP }, 0 },
2687   { "popV",             { RMrSI }, 0 },
2688   { "popV",             { RMrDI }, 0 },
2689   /* 60 */
2690   { X86_64_TABLE (X86_64_60) },
2691   { X86_64_TABLE (X86_64_61) },
2692   { X86_64_TABLE (X86_64_62) },
2693   { X86_64_TABLE (X86_64_63) },
2694   { Bad_Opcode },       /* seg fs */
2695   { Bad_Opcode },       /* seg gs */
2696   { Bad_Opcode },       /* op size prefix */
2697   { Bad_Opcode },       /* adr size prefix */
2698   /* 68 */
2699   { "pushT",            { sIv }, 0 },
2700   { "imulS",            { Gv, Ev, Iv }, 0 },
2701   { "pushT",            { sIbT }, 0 },
2702   { "imulS",            { Gv, Ev, sIb }, 0 },
2703   { "ins{b|}",          { Ybr, indirDX }, 0 },
2704   { X86_64_TABLE (X86_64_6D) },
2705   { "outs{b|}",         { indirDXr, Xb }, 0 },
2706   { X86_64_TABLE (X86_64_6F) },
2707   /* 70 */
2708   { "joH",              { Jb, BND, cond_jump_flag }, 0 },
2709   { "jnoH",             { Jb, BND, cond_jump_flag }, 0 },
2710   { "jbH",              { Jb, BND, cond_jump_flag }, 0 },
2711   { "jaeH",             { Jb, BND, cond_jump_flag }, 0 },
2712   { "jeH",              { Jb, BND, cond_jump_flag }, 0 },
2713   { "jneH",             { Jb, BND, cond_jump_flag }, 0 },
2714   { "jbeH",             { Jb, BND, cond_jump_flag }, 0 },
2715   { "jaH",              { Jb, BND, cond_jump_flag }, 0 },
2716   /* 78 */
2717   { "jsH",              { Jb, BND, cond_jump_flag }, 0 },
2718   { "jnsH",             { Jb, BND, cond_jump_flag }, 0 },
2719   { "jpH",              { Jb, BND, cond_jump_flag }, 0 },
2720   { "jnpH",             { Jb, BND, cond_jump_flag }, 0 },
2721   { "jlH",              { Jb, BND, cond_jump_flag }, 0 },
2722   { "jgeH",             { Jb, BND, cond_jump_flag }, 0 },
2723   { "jleH",             { Jb, BND, cond_jump_flag }, 0 },
2724   { "jgH",              { Jb, BND, cond_jump_flag }, 0 },
2725   /* 80 */
2726   { REG_TABLE (REG_80) },
2727   { REG_TABLE (REG_81) },
2728   { X86_64_TABLE (X86_64_82) },
2729   { REG_TABLE (REG_83) },
2730   { "testB",            { Eb, Gb }, 0 },
2731   { "testS",            { Ev, Gv }, 0 },
2732   { "xchgB",            { Ebh2, Gb }, 0 },
2733   { "xchgS",            { Evh2, Gv }, 0 },
2734   /* 88 */
2735   { "movB",             { Ebh3, Gb }, 0 },
2736   { "movS",             { Evh3, Gv }, 0 },
2737   { "movB",             { Gb, EbS }, 0 },
2738   { "movS",             { Gv, EvS }, 0 },
2739   { "movD",             { Sv, Sw }, 0 },
2740   { MOD_TABLE (MOD_8D) },
2741   { "movD",             { Sw, Sv }, 0 },
2742   { REG_TABLE (REG_8F) },
2743   /* 90 */
2744   { PREFIX_TABLE (PREFIX_90) },
2745   { "xchgS",            { RMeCX, eAX }, 0 },
2746   { "xchgS",            { RMeDX, eAX }, 0 },
2747   { "xchgS",            { RMeBX, eAX }, 0 },
2748   { "xchgS",            { RMeSP, eAX }, 0 },
2749   { "xchgS",            { RMeBP, eAX }, 0 },
2750   { "xchgS",            { RMeSI, eAX }, 0 },
2751   { "xchgS",            { RMeDI, eAX }, 0 },
2752   /* 98 */
2753   { "cW{t|}R",          { XX }, 0 },
2754   { "cR{t|}O",          { XX }, 0 },
2755   { X86_64_TABLE (X86_64_9A) },
2756   { Bad_Opcode },       /* fwait */
2757   { "pushfT",           { XX }, 0 },
2758   { "popfT",            { XX }, 0 },
2759   { "sahf",             { XX }, 0 },
2760   { "lahf",             { XX }, 0 },
2761   /* a0 */
2762   { "mov%LB",           { AL, Ob }, 0 },
2763   { "mov%LS",           { eAX, Ov }, 0 },
2764   { "mov%LB",           { Ob, AL }, 0 },
2765   { "mov%LS",           { Ov, eAX }, 0 },
2766   { "movs{b|}",         { Ybr, Xb }, 0 },
2767   { "movs{R|}",         { Yvr, Xv }, 0 },
2768   { "cmps{b|}",         { Xb, Yb }, 0 },
2769   { "cmps{R|}",         { Xv, Yv }, 0 },
2770   /* a8 */
2771   { "testB",            { AL, Ib }, 0 },
2772   { "testS",            { eAX, Iv }, 0 },
2773   { "stosB",            { Ybr, AL }, 0 },
2774   { "stosS",            { Yvr, eAX }, 0 },
2775   { "lodsB",            { ALr, Xb }, 0 },
2776   { "lodsS",            { eAXr, Xv }, 0 },
2777   { "scasB",            { AL, Yb }, 0 },
2778   { "scasS",            { eAX, Yv }, 0 },
2779   /* b0 */
2780   { "movB",             { RMAL, Ib }, 0 },
2781   { "movB",             { RMCL, Ib }, 0 },
2782   { "movB",             { RMDL, Ib }, 0 },
2783   { "movB",             { RMBL, Ib }, 0 },
2784   { "movB",             { RMAH, Ib }, 0 },
2785   { "movB",             { RMCH, Ib }, 0 },
2786   { "movB",             { RMDH, Ib }, 0 },
2787   { "movB",             { RMBH, Ib }, 0 },
2788   /* b8 */
2789   { "mov%LV",           { RMeAX, Iv64 }, 0 },
2790   { "mov%LV",           { RMeCX, Iv64 }, 0 },
2791   { "mov%LV",           { RMeDX, Iv64 }, 0 },
2792   { "mov%LV",           { RMeBX, Iv64 }, 0 },
2793   { "mov%LV",           { RMeSP, Iv64 }, 0 },
2794   { "mov%LV",           { RMeBP, Iv64 }, 0 },
2795   { "mov%LV",           { RMeSI, Iv64 }, 0 },
2796   { "mov%LV",           { RMeDI, Iv64 }, 0 },
2797   /* c0 */
2798   { REG_TABLE (REG_C0) },
2799   { REG_TABLE (REG_C1) },
2800   { "retT",             { Iw, BND }, 0 },
2801   { "retT",             { BND }, 0 },
2802   { X86_64_TABLE (X86_64_C4) },
2803   { X86_64_TABLE (X86_64_C5) },
2804   { REG_TABLE (REG_C6) },
2805   { REG_TABLE (REG_C7) },
2806   /* c8 */
2807   { "enterT",           { Iw, Ib }, 0 },
2808   { "leaveT",           { XX }, 0 },
2809   { "Jret{|f}P",        { Iw }, 0 },
2810   { "Jret{|f}P",        { XX }, 0 },
2811   { "int3",             { XX }, 0 },
2812   { "int",              { Ib }, 0 },
2813   { X86_64_TABLE (X86_64_CE) },
2814   { "iret%LP",          { XX }, 0 },
2815   /* d0 */
2816   { REG_TABLE (REG_D0) },
2817   { REG_TABLE (REG_D1) },
2818   { REG_TABLE (REG_D2) },
2819   { REG_TABLE (REG_D3) },
2820   { X86_64_TABLE (X86_64_D4) },
2821   { X86_64_TABLE (X86_64_D5) },
2822   { Bad_Opcode },
2823   { "xlat",             { DSBX }, 0 },
2824   /* d8 */
2825   { FLOAT },
2826   { FLOAT },
2827   { FLOAT },
2828   { FLOAT },
2829   { FLOAT },
2830   { FLOAT },
2831   { FLOAT },
2832   { FLOAT },
2833   /* e0 */
2834   { "loopneFH",         { Jb, XX, loop_jcxz_flag }, 0 },
2835   { "loopeFH",          { Jb, XX, loop_jcxz_flag }, 0 },
2836   { "loopFH",           { Jb, XX, loop_jcxz_flag }, 0 },
2837   { "jEcxzH",           { Jb, XX, loop_jcxz_flag }, 0 },
2838   { "inB",              { AL, Ib }, 0 },
2839   { "inG",              { zAX, Ib }, 0 },
2840   { "outB",             { Ib, AL }, 0 },
2841   { "outG",             { Ib, zAX }, 0 },
2842   /* e8 */
2843   { X86_64_TABLE (X86_64_E8) },
2844   { X86_64_TABLE (X86_64_E9) },
2845   { X86_64_TABLE (X86_64_EA) },
2846   { "jmp",              { Jb, BND }, 0 },
2847   { "inB",              { AL, indirDX }, 0 },
2848   { "inG",              { zAX, indirDX }, 0 },
2849   { "outB",             { indirDX, AL }, 0 },
2850   { "outG",             { indirDX, zAX }, 0 },
2851   /* f0 */
2852   { Bad_Opcode },       /* lock prefix */
2853   { "icebp",            { XX }, 0 },
2854   { Bad_Opcode },       /* repne */
2855   { Bad_Opcode },       /* repz */
2856   { "hlt",              { XX }, 0 },
2857   { "cmc",              { XX }, 0 },
2858   { REG_TABLE (REG_F6) },
2859   { REG_TABLE (REG_F7) },
2860   /* f8 */
2861   { "clc",              { XX }, 0 },
2862   { "stc",              { XX }, 0 },
2863   { "cli",              { XX }, 0 },
2864   { "sti",              { XX }, 0 },
2865   { "cld",              { XX }, 0 },
2866   { "std",              { XX }, 0 },
2867   { REG_TABLE (REG_FE) },
2868   { REG_TABLE (REG_FF) },
2869 };
2870
2871 static const struct dis386 dis386_twobyte[] = {
2872   /* 00 */
2873   { REG_TABLE (REG_0F00 ) },
2874   { REG_TABLE (REG_0F01 ) },
2875   { "larS",             { Gv, Ew }, 0 },
2876   { "lslS",             { Gv, Ew }, 0 },
2877   { Bad_Opcode },
2878   { "syscall",          { XX }, 0 },
2879   { "clts",             { XX }, 0 },
2880   { "sysret%LP",                { XX }, 0 },
2881   /* 08 */
2882   { "invd",             { XX }, 0 },
2883   { PREFIX_TABLE (PREFIX_0F09) },
2884   { Bad_Opcode },
2885   { "ud2",              { XX }, 0 },
2886   { Bad_Opcode },
2887   { REG_TABLE (REG_0F0D) },
2888   { "femms",            { XX }, 0 },
2889   { "",                 { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix.  */
2890   /* 10 */
2891   { PREFIX_TABLE (PREFIX_0F10) },
2892   { PREFIX_TABLE (PREFIX_0F11) },
2893   { PREFIX_TABLE (PREFIX_0F12) },
2894   { MOD_TABLE (MOD_0F13) },
2895   { "unpcklpX",         { XM, EXx }, PREFIX_OPCODE },
2896   { "unpckhpX",         { XM, EXx }, PREFIX_OPCODE },
2897   { PREFIX_TABLE (PREFIX_0F16) },
2898   { MOD_TABLE (MOD_0F17) },
2899   /* 18 */
2900   { REG_TABLE (REG_0F18) },
2901   { "nopQ",             { Ev }, 0 },
2902   { PREFIX_TABLE (PREFIX_0F1A) },
2903   { PREFIX_TABLE (PREFIX_0F1B) },
2904   { PREFIX_TABLE (PREFIX_0F1C) },
2905   { "nopQ",             { Ev }, 0 },
2906   { PREFIX_TABLE (PREFIX_0F1E) },
2907   { "nopQ",             { Ev }, 0 },
2908   /* 20 */
2909   { "movZ",             { Rm, Cm }, 0 },
2910   { "movZ",             { Rm, Dm }, 0 },
2911   { "movZ",             { Cm, Rm }, 0 },
2912   { "movZ",             { Dm, Rm }, 0 },
2913   { MOD_TABLE (MOD_0F24) },
2914   { Bad_Opcode },
2915   { MOD_TABLE (MOD_0F26) },
2916   { Bad_Opcode },
2917   /* 28 */
2918   { "movapX",           { XM, EXx }, PREFIX_OPCODE },
2919   { "movapX",           { EXxS, XM }, PREFIX_OPCODE },
2920   { PREFIX_TABLE (PREFIX_0F2A) },
2921   { PREFIX_TABLE (PREFIX_0F2B) },
2922   { PREFIX_TABLE (PREFIX_0F2C) },
2923   { PREFIX_TABLE (PREFIX_0F2D) },
2924   { PREFIX_TABLE (PREFIX_0F2E) },
2925   { PREFIX_TABLE (PREFIX_0F2F) },
2926   /* 30 */
2927   { "wrmsr",            { XX }, 0 },
2928   { "rdtsc",            { XX }, 0 },
2929   { "rdmsr",            { XX }, 0 },
2930   { "rdpmc",            { XX }, 0 },
2931   { "sysenter",         { XX }, 0 },
2932   { "sysexit",          { XX }, 0 },
2933   { Bad_Opcode },
2934   { "getsec",           { XX }, 0 },
2935   /* 38 */
2936   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2937   { Bad_Opcode },
2938   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2939   { Bad_Opcode },
2940   { Bad_Opcode },
2941   { Bad_Opcode },
2942   { Bad_Opcode },
2943   { Bad_Opcode },
2944   /* 40 */
2945   { "cmovoS",           { Gv, Ev }, 0 },
2946   { "cmovnoS",          { Gv, Ev }, 0 },
2947   { "cmovbS",           { Gv, Ev }, 0 },
2948   { "cmovaeS",          { Gv, Ev }, 0 },
2949   { "cmoveS",           { Gv, Ev }, 0 },
2950   { "cmovneS",          { Gv, Ev }, 0 },
2951   { "cmovbeS",          { Gv, Ev }, 0 },
2952   { "cmovaS",           { Gv, Ev }, 0 },
2953   /* 48 */
2954   { "cmovsS",           { Gv, Ev }, 0 },
2955   { "cmovnsS",          { Gv, Ev }, 0 },
2956   { "cmovpS",           { Gv, Ev }, 0 },
2957   { "cmovnpS",          { Gv, Ev }, 0 },
2958   { "cmovlS",           { Gv, Ev }, 0 },
2959   { "cmovgeS",          { Gv, Ev }, 0 },
2960   { "cmovleS",          { Gv, Ev }, 0 },
2961   { "cmovgS",           { Gv, Ev }, 0 },
2962   /* 50 */
2963   { MOD_TABLE (MOD_0F51) },
2964   { PREFIX_TABLE (PREFIX_0F51) },
2965   { PREFIX_TABLE (PREFIX_0F52) },
2966   { PREFIX_TABLE (PREFIX_0F53) },
2967   { "andpX",            { XM, EXx }, PREFIX_OPCODE },
2968   { "andnpX",           { XM, EXx }, PREFIX_OPCODE },
2969   { "orpX",             { XM, EXx }, PREFIX_OPCODE },
2970   { "xorpX",            { XM, EXx }, PREFIX_OPCODE },
2971   /* 58 */
2972   { PREFIX_TABLE (PREFIX_0F58) },
2973   { PREFIX_TABLE (PREFIX_0F59) },
2974   { PREFIX_TABLE (PREFIX_0F5A) },
2975   { PREFIX_TABLE (PREFIX_0F5B) },
2976   { PREFIX_TABLE (PREFIX_0F5C) },
2977   { PREFIX_TABLE (PREFIX_0F5D) },
2978   { PREFIX_TABLE (PREFIX_0F5E) },
2979   { PREFIX_TABLE (PREFIX_0F5F) },
2980   /* 60 */
2981   { PREFIX_TABLE (PREFIX_0F60) },
2982   { PREFIX_TABLE (PREFIX_0F61) },
2983   { PREFIX_TABLE (PREFIX_0F62) },
2984   { "packsswb",         { MX, EM }, PREFIX_OPCODE },
2985   { "pcmpgtb",          { MX, EM }, PREFIX_OPCODE },
2986   { "pcmpgtw",          { MX, EM }, PREFIX_OPCODE },
2987   { "pcmpgtd",          { MX, EM }, PREFIX_OPCODE },
2988   { "packuswb",         { MX, EM }, PREFIX_OPCODE },
2989   /* 68 */
2990   { "punpckhbw",        { MX, EM }, PREFIX_OPCODE },
2991   { "punpckhwd",        { MX, EM }, PREFIX_OPCODE },
2992   { "punpckhdq",        { MX, EM }, PREFIX_OPCODE },
2993   { "packssdw",         { MX, EM }, PREFIX_OPCODE },
2994   { PREFIX_TABLE (PREFIX_0F6C) },
2995   { PREFIX_TABLE (PREFIX_0F6D) },
2996   { "movK",             { MX, Edq }, PREFIX_OPCODE },
2997   { PREFIX_TABLE (PREFIX_0F6F) },
2998   /* 70 */
2999   { PREFIX_TABLE (PREFIX_0F70) },
3000   { REG_TABLE (REG_0F71) },
3001   { REG_TABLE (REG_0F72) },
3002   { REG_TABLE (REG_0F73) },
3003   { "pcmpeqb",          { MX, EM }, PREFIX_OPCODE },
3004   { "pcmpeqw",          { MX, EM }, PREFIX_OPCODE },
3005   { "pcmpeqd",          { MX, EM }, PREFIX_OPCODE },
3006   { "emms",             { XX }, PREFIX_OPCODE },
3007   /* 78 */
3008   { PREFIX_TABLE (PREFIX_0F78) },
3009   { PREFIX_TABLE (PREFIX_0F79) },
3010   { Bad_Opcode },
3011   { Bad_Opcode },
3012   { PREFIX_TABLE (PREFIX_0F7C) },
3013   { PREFIX_TABLE (PREFIX_0F7D) },
3014   { PREFIX_TABLE (PREFIX_0F7E) },
3015   { PREFIX_TABLE (PREFIX_0F7F) },
3016   /* 80 */
3017   { "joH",              { Jv, BND, cond_jump_flag }, 0 },
3018   { "jnoH",             { Jv, BND, cond_jump_flag }, 0 },
3019   { "jbH",              { Jv, BND, cond_jump_flag }, 0 },
3020   { "jaeH",             { Jv, BND, cond_jump_flag }, 0 },
3021   { "jeH",              { Jv, BND, cond_jump_flag }, 0 },
3022   { "jneH",             { Jv, BND, cond_jump_flag }, 0 },
3023   { "jbeH",             { Jv, BND, cond_jump_flag }, 0 },
3024   { "jaH",              { Jv, BND, cond_jump_flag }, 0 },
3025   /* 88 */
3026   { "jsH",              { Jv, BND, cond_jump_flag }, 0 },
3027   { "jnsH",             { Jv, BND, cond_jump_flag }, 0 },
3028   { "jpH",              { Jv, BND, cond_jump_flag }, 0 },
3029   { "jnpH",             { Jv, BND, cond_jump_flag }, 0 },
3030   { "jlH",              { Jv, BND, cond_jump_flag }, 0 },
3031   { "jgeH",             { Jv, BND, cond_jump_flag }, 0 },
3032   { "jleH",             { Jv, BND, cond_jump_flag }, 0 },
3033   { "jgH",              { Jv, BND, cond_jump_flag }, 0 },
3034   /* 90 */
3035   { "seto",             { Eb }, 0 },
3036   { "setno",            { Eb }, 0 },
3037   { "setb",             { Eb }, 0 },
3038   { "setae",            { Eb }, 0 },
3039   { "sete",             { Eb }, 0 },
3040   { "setne",            { Eb }, 0 },
3041   { "setbe",            { Eb }, 0 },
3042   { "seta",             { Eb }, 0 },
3043   /* 98 */
3044   { "sets",             { Eb }, 0 },
3045   { "setns",            { Eb }, 0 },
3046   { "setp",             { Eb }, 0 },
3047   { "setnp",            { Eb }, 0 },
3048   { "setl",             { Eb }, 0 },
3049   { "setge",            { Eb }, 0 },
3050   { "setle",            { Eb }, 0 },
3051   { "setg",             { Eb }, 0 },
3052   /* a0 */
3053   { "pushT",            { fs }, 0 },
3054   { "popT",             { fs }, 0 },
3055   { "cpuid",            { XX }, 0 },
3056   { "btS",              { Ev, Gv }, 0 },
3057   { "shldS",            { Ev, Gv, Ib }, 0 },
3058   { "shldS",            { Ev, Gv, CL }, 0 },
3059   { REG_TABLE (REG_0FA6) },
3060   { REG_TABLE (REG_0FA7) },
3061   /* a8 */
3062   { "pushT",            { gs }, 0 },
3063   { "popT",             { gs }, 0 },
3064   { "rsm",              { XX }, 0 },
3065   { "btsS",             { Evh1, Gv }, 0 },
3066   { "shrdS",            { Ev, Gv, Ib }, 0 },
3067   { "shrdS",            { Ev, Gv, CL }, 0 },
3068   { REG_TABLE (REG_0FAE) },
3069   { "imulS",            { Gv, Ev }, 0 },
3070   /* b0 */
3071   { "cmpxchgB",         { Ebh1, Gb }, 0 },
3072   { "cmpxchgS",         { Evh1, Gv }, 0 },
3073   { MOD_TABLE (MOD_0FB2) },
3074   { "btrS",             { Evh1, Gv }, 0 },
3075   { MOD_TABLE (MOD_0FB4) },
3076   { MOD_TABLE (MOD_0FB5) },
3077   { "movz{bR|x}",       { Gv, Eb }, 0 },
3078   { "movz{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
3079   /* b8 */
3080   { PREFIX_TABLE (PREFIX_0FB8) },
3081   { "ud1S",             { Gv, Ev }, 0 },
3082   { REG_TABLE (REG_0FBA) },
3083   { "btcS",             { Evh1, Gv }, 0 },
3084   { PREFIX_TABLE (PREFIX_0FBC) },
3085   { PREFIX_TABLE (PREFIX_0FBD) },
3086   { "movs{bR|x}",       { Gv, Eb }, 0 },
3087   { "movs{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
3088   /* c0 */
3089   { "xaddB",            { Ebh1, Gb }, 0 },
3090   { "xaddS",            { Evh1, Gv }, 0 },
3091   { PREFIX_TABLE (PREFIX_0FC2) },
3092   { MOD_TABLE (MOD_0FC3) },
3093   { "pinsrw",           { MX, Edqw, Ib }, PREFIX_OPCODE },
3094   { "pextrw",           { Gdq, MS, Ib }, PREFIX_OPCODE },
3095   { "shufpX",           { XM, EXx, Ib }, PREFIX_OPCODE },
3096   { REG_TABLE (REG_0FC7) },
3097   /* c8 */
3098   { "bswap",            { RMeAX }, 0 },
3099   { "bswap",            { RMeCX }, 0 },
3100   { "bswap",            { RMeDX }, 0 },
3101   { "bswap",            { RMeBX }, 0 },
3102   { "bswap",            { RMeSP }, 0 },
3103   { "bswap",            { RMeBP }, 0 },
3104   { "bswap",            { RMeSI }, 0 },
3105   { "bswap",            { RMeDI }, 0 },
3106   /* d0 */
3107   { PREFIX_TABLE (PREFIX_0FD0) },
3108   { "psrlw",            { MX, EM }, PREFIX_OPCODE },
3109   { "psrld",            { MX, EM }, PREFIX_OPCODE },
3110   { "psrlq",            { MX, EM }, PREFIX_OPCODE },
3111   { "paddq",            { MX, EM }, PREFIX_OPCODE },
3112   { "pmullw",           { MX, EM }, PREFIX_OPCODE },
3113   { PREFIX_TABLE (PREFIX_0FD6) },
3114   { MOD_TABLE (MOD_0FD7) },
3115   /* d8 */
3116   { "psubusb",          { MX, EM }, PREFIX_OPCODE },
3117   { "psubusw",          { MX, EM }, PREFIX_OPCODE },
3118   { "pminub",           { MX, EM }, PREFIX_OPCODE },
3119   { "pand",             { MX, EM }, PREFIX_OPCODE },
3120   { "paddusb",          { MX, EM }, PREFIX_OPCODE },
3121   { "paddusw",          { MX, EM }, PREFIX_OPCODE },
3122   { "pmaxub",           { MX, EM }, PREFIX_OPCODE },
3123   { "pandn",            { MX, EM }, PREFIX_OPCODE },
3124   /* e0 */
3125   { "pavgb",            { MX, EM }, PREFIX_OPCODE },
3126   { "psraw",            { MX, EM }, PREFIX_OPCODE },
3127   { "psrad",            { MX, EM }, PREFIX_OPCODE },
3128   { "pavgw",            { MX, EM }, PREFIX_OPCODE },
3129   { "pmulhuw",          { MX, EM }, PREFIX_OPCODE },
3130   { "pmulhw",           { MX, EM }, PREFIX_OPCODE },
3131   { PREFIX_TABLE (PREFIX_0FE6) },
3132   { PREFIX_TABLE (PREFIX_0FE7) },
3133   /* e8 */
3134   { "psubsb",           { MX, EM }, PREFIX_OPCODE },
3135   { "psubsw",           { MX, EM }, PREFIX_OPCODE },
3136   { "pminsw",           { MX, EM }, PREFIX_OPCODE },
3137   { "por",              { MX, EM }, PREFIX_OPCODE },
3138   { "paddsb",           { MX, EM }, PREFIX_OPCODE },
3139   { "paddsw",           { MX, EM }, PREFIX_OPCODE },
3140   { "pmaxsw",           { MX, EM }, PREFIX_OPCODE },
3141   { "pxor",             { MX, EM }, PREFIX_OPCODE },
3142   /* f0 */
3143   { PREFIX_TABLE (PREFIX_0FF0) },
3144   { "psllw",            { MX, EM }, PREFIX_OPCODE },
3145   { "pslld",            { MX, EM }, PREFIX_OPCODE },
3146   { "psllq",            { MX, EM }, PREFIX_OPCODE },
3147   { "pmuludq",          { MX, EM }, PREFIX_OPCODE },
3148   { "pmaddwd",          { MX, EM }, PREFIX_OPCODE },
3149   { "psadbw",           { MX, EM }, PREFIX_OPCODE },
3150   { PREFIX_TABLE (PREFIX_0FF7) },
3151   /* f8 */
3152   { "psubb",            { MX, EM }, PREFIX_OPCODE },
3153   { "psubw",            { MX, EM }, PREFIX_OPCODE },
3154   { "psubd",            { MX, EM }, PREFIX_OPCODE },
3155   { "psubq",            { MX, EM }, PREFIX_OPCODE },
3156   { "paddb",            { MX, EM }, PREFIX_OPCODE },
3157   { "paddw",            { MX, EM }, PREFIX_OPCODE },
3158   { "paddd",            { MX, EM }, PREFIX_OPCODE },
3159   { "ud0S",             { Gv, Ev }, 0 },
3160 };
3161
3162 static const unsigned char onebyte_has_modrm[256] = {
3163   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3164   /*       -------------------------------        */
3165   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
3166   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
3167   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
3168   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
3169   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
3170   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
3171   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
3172   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
3173   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
3174   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
3175   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
3176   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
3177   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
3178   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
3179   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
3180   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
3181   /*       -------------------------------        */
3182   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3183 };
3184
3185 static const unsigned char twobyte_has_modrm[256] = {
3186   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3187   /*       -------------------------------        */
3188   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
3189   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
3190   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
3191   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
3192   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
3193   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
3194   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
3195   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
3196   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
3197   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
3198   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
3199   /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
3200   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
3201   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
3202   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
3203   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1  /* ff */
3204   /*       -------------------------------        */
3205   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3206 };
3207
3208 static char obuf[100];
3209 static char *obufp;
3210 static char *mnemonicendp;
3211 static char scratchbuf[100];
3212 static unsigned char *start_codep;
3213 static unsigned char *insn_codep;
3214 static unsigned char *codep;
3215 static unsigned char *end_codep;
3216 static int last_lock_prefix;
3217 static int last_repz_prefix;
3218 static int last_repnz_prefix;
3219 static int last_data_prefix;
3220 static int last_addr_prefix;
3221 static int last_rex_prefix;
3222 static int last_seg_prefix;
3223 static int fwait_prefix;
3224 /* The active segment register prefix.  */
3225 static int active_seg_prefix;
3226 #define MAX_CODE_LENGTH 15
3227 /* We can up to 14 prefixes since the maximum instruction length is
3228    15bytes.  */
3229 static int all_prefixes[MAX_CODE_LENGTH - 1];
3230 static disassemble_info *the_info;
3231 static struct
3232   {
3233     int mod;
3234     int reg;
3235     int rm;
3236   }
3237 modrm;
3238 static unsigned char need_modrm;
3239 static struct
3240   {
3241     int scale;
3242     int index;
3243     int base;
3244   }
3245 sib;
3246 static struct
3247   {
3248     int register_specifier;
3249     int length;
3250     int prefix;
3251     int w;
3252     int evex;
3253     int r;
3254     int v;
3255     int mask_register_specifier;
3256     int zeroing;
3257     int ll;
3258     int b;
3259   }
3260 vex;
3261 static unsigned char need_vex;
3262 static unsigned char need_vex_reg;
3263 static unsigned char vex_w_done;
3264
3265 struct op
3266   {
3267     const char *name;
3268     unsigned int len;
3269   };
3270
3271 /* If we are accessing mod/rm/reg without need_modrm set, then the
3272    values are stale.  Hitting this abort likely indicates that you
3273    need to update onebyte_has_modrm or twobyte_has_modrm.  */
3274 #define MODRM_CHECK  if (!need_modrm) abort ()
3275
3276 static const char **names64;
3277 static const char **names32;
3278 static const char **names16;
3279 static const char **names8;
3280 static const char **names8rex;
3281 static const char **names_seg;
3282 static const char *index64;
3283 static const char *index32;
3284 static const char **index16;
3285 static const char **names_bnd;
3286
3287 static const char *intel_names64[] = {
3288   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3289   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3290 };
3291 static const char *intel_names32[] = {
3292   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3293   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3294 };
3295 static const char *intel_names16[] = {
3296   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3297   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3298 };
3299 static const char *intel_names8[] = {
3300   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3301 };
3302 static const char *intel_names8rex[] = {
3303   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3304   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3305 };
3306 static const char *intel_names_seg[] = {
3307   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3308 };
3309 static const char *intel_index64 = "riz";
3310 static const char *intel_index32 = "eiz";
3311 static const char *intel_index16[] = {
3312   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3313 };
3314
3315 static const char *att_names64[] = {
3316   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3317   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3318 };
3319 static const char *att_names32[] = {
3320   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3321   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3322 };
3323 static const char *att_names16[] = {
3324   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3325   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3326 };
3327 static const char *att_names8[] = {
3328   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3329 };
3330 static const char *att_names8rex[] = {
3331   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3332   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3333 };
3334 static const char *att_names_seg[] = {
3335   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3336 };
3337 static const char *att_index64 = "%riz";
3338 static const char *att_index32 = "%eiz";
3339 static const char *att_index16[] = {
3340   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3341 };
3342
3343 static const char **names_mm;
3344 static const char *intel_names_mm[] = {
3345   "mm0", "mm1", "mm2", "mm3",
3346   "mm4", "mm5", "mm6", "mm7"
3347 };
3348 static const char *att_names_mm[] = {
3349   "%mm0", "%mm1", "%mm2", "%mm3",
3350   "%mm4", "%mm5", "%mm6", "%mm7"
3351 };
3352
3353 static const char *intel_names_bnd[] = {
3354   "bnd0", "bnd1", "bnd2", "bnd3"
3355 };
3356
3357 static const char *att_names_bnd[] = {
3358   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3359 };
3360
3361 static const char **names_xmm;
3362 static const char *intel_names_xmm[] = {
3363   "xmm0", "xmm1", "xmm2", "xmm3",
3364   "xmm4", "xmm5", "xmm6", "xmm7",
3365   "xmm8", "xmm9", "xmm10", "xmm11",
3366   "xmm12", "xmm13", "xmm14", "xmm15",
3367   "xmm16", "xmm17", "xmm18", "xmm19",
3368   "xmm20", "xmm21", "xmm22", "xmm23",
3369   "xmm24", "xmm25", "xmm26", "xmm27",
3370   "xmm28", "xmm29", "xmm30", "xmm31"
3371 };
3372 static const char *att_names_xmm[] = {
3373   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3374   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3375   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3376   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3377   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3378   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3379   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3380   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3381 };
3382
3383 static const char **names_ymm;
3384 static const char *intel_names_ymm[] = {
3385   "ymm0", "ymm1", "ymm2", "ymm3",
3386   "ymm4", "ymm5", "ymm6", "ymm7",
3387   "ymm8", "ymm9", "ymm10", "ymm11",
3388   "ymm12", "ymm13", "ymm14", "ymm15",
3389   "ymm16", "ymm17", "ymm18", "ymm19",
3390   "ymm20", "ymm21", "ymm22", "ymm23",
3391   "ymm24", "ymm25", "ymm26", "ymm27",
3392   "ymm28", "ymm29", "ymm30", "ymm31"
3393 };
3394 static const char *att_names_ymm[] = {
3395   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3396   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3397   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3398   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3399   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3400   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3401   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3402   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3403 };
3404
3405 static const char **names_zmm;
3406 static const char *intel_names_zmm[] = {
3407   "zmm0", "zmm1", "zmm2", "zmm3",
3408   "zmm4", "zmm5", "zmm6", "zmm7",
3409   "zmm8", "zmm9", "zmm10", "zmm11",
3410   "zmm12", "zmm13", "zmm14", "zmm15",
3411   "zmm16", "zmm17", "zmm18", "zmm19",
3412   "zmm20", "zmm21", "zmm22", "zmm23",
3413   "zmm24", "zmm25", "zmm26", "zmm27",
3414   "zmm28", "zmm29", "zmm30", "zmm31"
3415 };
3416 static const char *att_names_zmm[] = {
3417   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3418   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3419   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3420   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3421   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3422   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3423   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3424   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3425 };
3426
3427 static const char **names_mask;
3428 static const char *intel_names_mask[] = {
3429   "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3430 };
3431 static const char *att_names_mask[] = {
3432   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3433 };
3434
3435 static const char *names_rounding[] =
3436 {
3437   "{rn-sae}",
3438   "{rd-sae}",
3439   "{ru-sae}",
3440   "{rz-sae}"
3441 };
3442
3443 static const struct dis386 reg_table[][8] = {
3444   /* REG_80 */
3445   {
3446     { "addA",   { Ebh1, Ib }, 0 },
3447     { "orA",    { Ebh1, Ib }, 0 },
3448     { "adcA",   { Ebh1, Ib }, 0 },
3449     { "sbbA",   { Ebh1, Ib }, 0 },
3450     { "andA",   { Ebh1, Ib }, 0 },
3451     { "subA",   { Ebh1, Ib }, 0 },
3452     { "xorA",   { Ebh1, Ib }, 0 },
3453     { "cmpA",   { Eb, Ib }, 0 },
3454   },
3455   /* REG_81 */
3456   {
3457     { "addQ",   { Evh1, Iv }, 0 },
3458     { "orQ",    { Evh1, Iv }, 0 },
3459     { "adcQ",   { Evh1, Iv }, 0 },
3460     { "sbbQ",   { Evh1, Iv }, 0 },
3461     { "andQ",   { Evh1, Iv }, 0 },
3462     { "subQ",   { Evh1, Iv }, 0 },
3463     { "xorQ",   { Evh1, Iv }, 0 },
3464     { "cmpQ",   { Ev, Iv }, 0 },
3465   },
3466   /* REG_83 */
3467   {
3468     { "addQ",   { Evh1, sIb }, 0 },
3469     { "orQ",    { Evh1, sIb }, 0 },
3470     { "adcQ",   { Evh1, sIb }, 0 },
3471     { "sbbQ",   { Evh1, sIb }, 0 },
3472     { "andQ",   { Evh1, sIb }, 0 },
3473     { "subQ",   { Evh1, sIb }, 0 },
3474     { "xorQ",   { Evh1, sIb }, 0 },
3475     { "cmpQ",   { Ev, sIb }, 0 },
3476   },
3477   /* REG_8F */
3478   {
3479     { "popU",   { stackEv }, 0 },
3480     { XOP_8F_TABLE (XOP_09) },
3481     { Bad_Opcode },
3482     { Bad_Opcode },
3483     { Bad_Opcode },
3484     { XOP_8F_TABLE (XOP_09) },
3485   },
3486   /* REG_C0 */
3487   {
3488     { "rolA",   { Eb, Ib }, 0 },
3489     { "rorA",   { Eb, Ib }, 0 },
3490     { "rclA",   { Eb, Ib }, 0 },
3491     { "rcrA",   { Eb, Ib }, 0 },
3492     { "shlA",   { Eb, Ib }, 0 },
3493     { "shrA",   { Eb, Ib }, 0 },
3494     { "shlA",   { Eb, Ib }, 0 },
3495     { "sarA",   { Eb, Ib }, 0 },
3496   },
3497   /* REG_C1 */
3498   {
3499     { "rolQ",   { Ev, Ib }, 0 },
3500     { "rorQ",   { Ev, Ib }, 0 },
3501     { "rclQ",   { Ev, Ib }, 0 },
3502     { "rcrQ",   { Ev, Ib }, 0 },
3503     { "shlQ",   { Ev, Ib }, 0 },
3504     { "shrQ",   { Ev, Ib }, 0 },
3505     { "shlQ",   { Ev, Ib }, 0 },
3506     { "sarQ",   { Ev, Ib }, 0 },
3507   },
3508   /* REG_C6 */
3509   {
3510     { "movA",   { Ebh3, Ib }, 0 },
3511     { Bad_Opcode },
3512     { Bad_Opcode },
3513     { Bad_Opcode },
3514     { Bad_Opcode },
3515     { Bad_Opcode },
3516     { Bad_Opcode },
3517     { MOD_TABLE (MOD_C6_REG_7) },
3518   },
3519   /* REG_C7 */
3520   {
3521     { "movQ",   { Evh3, Iv }, 0 },
3522     { Bad_Opcode },
3523     { Bad_Opcode },
3524     { Bad_Opcode },
3525     { Bad_Opcode },
3526     { Bad_Opcode },
3527     { Bad_Opcode },
3528     { MOD_TABLE (MOD_C7_REG_7) },
3529   },
3530   /* REG_D0 */
3531   {
3532     { "rolA",   { Eb, I1 }, 0 },
3533     { "rorA",   { Eb, I1 }, 0 },
3534     { "rclA",   { Eb, I1 }, 0 },
3535     { "rcrA",   { Eb, I1 }, 0 },
3536     { "shlA",   { Eb, I1 }, 0 },
3537     { "shrA",   { Eb, I1 }, 0 },
3538     { "shlA",   { Eb, I1 }, 0 },
3539     { "sarA",   { Eb, I1 }, 0 },
3540   },
3541   /* REG_D1 */
3542   {
3543     { "rolQ",   { Ev, I1 }, 0 },
3544     { "rorQ",   { Ev, I1 }, 0 },
3545     { "rclQ",   { Ev, I1 }, 0 },
3546     { "rcrQ",   { Ev, I1 }, 0 },
3547     { "shlQ",   { Ev, I1 }, 0 },
3548     { "shrQ",   { Ev, I1 }, 0 },
3549     { "shlQ",   { Ev, I1 }, 0 },
3550     { "sarQ",   { Ev, I1 }, 0 },
3551   },
3552   /* REG_D2 */
3553   {
3554     { "rolA",   { Eb, CL }, 0 },
3555     { "rorA",   { Eb, CL }, 0 },
3556     { "rclA",   { Eb, CL }, 0 },
3557     { "rcrA",   { Eb, CL }, 0 },
3558     { "shlA",   { Eb, CL }, 0 },
3559     { "shrA",   { Eb, CL }, 0 },
3560     { "shlA",   { Eb, CL }, 0 },
3561     { "sarA",   { Eb, CL }, 0 },
3562   },
3563   /* REG_D3 */
3564   {
3565     { "rolQ",   { Ev, CL }, 0 },
3566     { "rorQ",   { Ev, CL }, 0 },
3567     { "rclQ",   { Ev, CL }, 0 },
3568     { "rcrQ",   { Ev, CL }, 0 },
3569     { "shlQ",   { Ev, CL }, 0 },
3570     { "shrQ",   { Ev, CL }, 0 },
3571     { "shlQ",   { Ev, CL }, 0 },
3572     { "sarQ",   { Ev, CL }, 0 },
3573   },
3574   /* REG_F6 */
3575   {
3576     { "testA",  { Eb, Ib }, 0 },
3577     { "testA",  { Eb, Ib }, 0 },
3578     { "notA",   { Ebh1 }, 0 },
3579     { "negA",   { Ebh1 }, 0 },
3580     { "mulA",   { Eb }, 0 },    /* Don't print the implicit %al register,  */
3581     { "imulA",  { Eb }, 0 },    /* to distinguish these opcodes from other */
3582     { "divA",   { Eb }, 0 },    /* mul/imul opcodes.  Do the same for div  */
3583     { "idivA",  { Eb }, 0 },    /* and idiv for consistency.               */
3584   },
3585   /* REG_F7 */
3586   {
3587     { "testQ",  { Ev, Iv }, 0 },
3588     { "testQ",  { Ev, Iv }, 0 },
3589     { "notQ",   { Evh1 }, 0 },
3590     { "negQ",   { Evh1 }, 0 },
3591     { "mulQ",   { Ev }, 0 },    /* Don't print the implicit register.  */
3592     { "imulQ",  { Ev }, 0 },
3593     { "divQ",   { Ev }, 0 },
3594     { "idivQ",  { Ev }, 0 },
3595   },
3596   /* REG_FE */
3597   {
3598     { "incA",   { Ebh1 }, 0 },
3599     { "decA",   { Ebh1 }, 0 },
3600   },
3601   /* REG_FF */
3602   {
3603     { "incQ",   { Evh1 }, 0 },
3604     { "decQ",   { Evh1 }, 0 },
3605     { "call{&|}", { NOTRACK, indirEv, BND }, 0 },
3606     { MOD_TABLE (MOD_FF_REG_3) },
3607     { "jmp{&|}", { NOTRACK, indirEv, BND }, 0 },
3608     { MOD_TABLE (MOD_FF_REG_5) },
3609     { "pushU",  { stackEv }, 0 },
3610     { Bad_Opcode },
3611   },
3612   /* REG_0F00 */
3613   {
3614     { "sldtD",  { Sv }, 0 },
3615     { "strD",   { Sv }, 0 },
3616     { "lldt",   { Ew }, 0 },
3617     { "ltr",    { Ew }, 0 },
3618     { "verr",   { Ew }, 0 },
3619     { "verw",   { Ew }, 0 },
3620     { Bad_Opcode },
3621     { Bad_Opcode },
3622   },
3623   /* REG_0F01 */
3624   {
3625     { MOD_TABLE (MOD_0F01_REG_0) },
3626     { MOD_TABLE (MOD_0F01_REG_1) },
3627     { MOD_TABLE (MOD_0F01_REG_2) },
3628     { MOD_TABLE (MOD_0F01_REG_3) },
3629     { "smswD",  { Sv }, 0 },
3630     { MOD_TABLE (MOD_0F01_REG_5) },
3631     { "lmsw",   { Ew }, 0 },
3632     { MOD_TABLE (MOD_0F01_REG_7) },
3633   },
3634   /* REG_0F0D */
3635   {
3636     { "prefetch",       { Mb }, 0 },
3637     { "prefetchw",      { Mb }, 0 },
3638     { "prefetchwt1",    { Mb }, 0 },
3639     { "prefetch",       { Mb }, 0 },
3640     { "prefetch",       { Mb }, 0 },
3641     { "prefetch",       { Mb }, 0 },
3642     { "prefetch",       { Mb }, 0 },
3643     { "prefetch",       { Mb }, 0 },
3644   },
3645   /* REG_0F18 */
3646   {
3647     { MOD_TABLE (MOD_0F18_REG_0) },
3648     { MOD_TABLE (MOD_0F18_REG_1) },
3649     { MOD_TABLE (MOD_0F18_REG_2) },
3650     { MOD_TABLE (MOD_0F18_REG_3) },
3651     { MOD_TABLE (MOD_0F18_REG_4) },
3652     { MOD_TABLE (MOD_0F18_REG_5) },
3653     { MOD_TABLE (MOD_0F18_REG_6) },
3654     { MOD_TABLE (MOD_0F18_REG_7) },
3655   },
3656   /* REG_0F1C_MOD_0 */
3657   {
3658     { "cldemote",       { Mb }, 0 },
3659     { "nopQ",           { Ev }, 0 },
3660     { "nopQ",           { Ev }, 0 },
3661     { "nopQ",           { Ev }, 0 },
3662     { "nopQ",           { Ev }, 0 },
3663     { "nopQ",           { Ev }, 0 },
3664     { "nopQ",           { Ev }, 0 },
3665     { "nopQ",           { Ev }, 0 },
3666   },
3667   /* REG_0F1E_MOD_3 */
3668   {
3669     { "nopQ",           { Ev }, 0 },
3670     { "rdsspK",         { Rdq }, PREFIX_OPCODE },
3671     { "nopQ",           { Ev }, 0 },
3672     { "nopQ",           { Ev }, 0 },
3673     { "nopQ",           { Ev }, 0 },
3674     { "nopQ",           { Ev }, 0 },
3675     { "nopQ",           { Ev }, 0 },
3676     { RM_TABLE (RM_0F1E_MOD_3_REG_7) },
3677   },
3678   /* REG_0F71 */
3679   {
3680     { Bad_Opcode },
3681     { Bad_Opcode },
3682     { MOD_TABLE (MOD_0F71_REG_2) },
3683     { Bad_Opcode },
3684     { MOD_TABLE (MOD_0F71_REG_4) },
3685     { Bad_Opcode },
3686     { MOD_TABLE (MOD_0F71_REG_6) },
3687   },
3688   /* REG_0F72 */
3689   {
3690     { Bad_Opcode },
3691     { Bad_Opcode },
3692     { MOD_TABLE (MOD_0F72_REG_2) },
3693     { Bad_Opcode },
3694     { MOD_TABLE (MOD_0F72_REG_4) },
3695     { Bad_Opcode },
3696     { MOD_TABLE (MOD_0F72_REG_6) },
3697   },
3698   /* REG_0F73 */
3699   {
3700     { Bad_Opcode },
3701     { Bad_Opcode },
3702     { MOD_TABLE (MOD_0F73_REG_2) },
3703     { MOD_TABLE (MOD_0F73_REG_3) },
3704     { Bad_Opcode },
3705     { Bad_Opcode },
3706     { MOD_TABLE (MOD_0F73_REG_6) },
3707     { MOD_TABLE (MOD_0F73_REG_7) },
3708   },
3709   /* REG_0FA6 */
3710   {
3711     { "montmul",        { { OP_0f07, 0 } }, 0 },
3712     { "xsha1",          { { OP_0f07, 0 } }, 0 },
3713     { "xsha256",        { { OP_0f07, 0 } }, 0 },
3714   },
3715   /* REG_0FA7 */
3716   {
3717     { "xstore-rng",     { { OP_0f07, 0 } }, 0 },
3718     { "xcrypt-ecb",     { { OP_0f07, 0 } }, 0 },
3719     { "xcrypt-cbc",     { { OP_0f07, 0 } }, 0 },
3720     { "xcrypt-ctr",     { { OP_0f07, 0 } }, 0 },
3721     { "xcrypt-cfb",     { { OP_0f07, 0 } }, 0 },
3722     { "xcrypt-ofb",     { { OP_0f07, 0 } }, 0 },
3723   },
3724   /* REG_0FAE */
3725   {
3726     { MOD_TABLE (MOD_0FAE_REG_0) },
3727     { MOD_TABLE (MOD_0FAE_REG_1) },
3728     { MOD_TABLE (MOD_0FAE_REG_2) },
3729     { MOD_TABLE (MOD_0FAE_REG_3) },
3730     { MOD_TABLE (MOD_0FAE_REG_4) },
3731     { MOD_TABLE (MOD_0FAE_REG_5) },
3732     { MOD_TABLE (MOD_0FAE_REG_6) },
3733     { MOD_TABLE (MOD_0FAE_REG_7) },
3734   },
3735   /* REG_0FBA */
3736   {
3737     { Bad_Opcode },
3738     { Bad_Opcode },
3739     { Bad_Opcode },
3740     { Bad_Opcode },
3741     { "btQ",    { Ev, Ib }, 0 },
3742     { "btsQ",   { Evh1, Ib }, 0 },
3743     { "btrQ",   { Evh1, Ib }, 0 },
3744     { "btcQ",   { Evh1, Ib }, 0 },
3745   },
3746   /* REG_0FC7 */
3747   {
3748     { Bad_Opcode },
3749     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
3750     { Bad_Opcode },
3751     { MOD_TABLE (MOD_0FC7_REG_3) },
3752     { MOD_TABLE (MOD_0FC7_REG_4) },
3753     { MOD_TABLE (MOD_0FC7_REG_5) },
3754     { MOD_TABLE (MOD_0FC7_REG_6) },
3755     { MOD_TABLE (MOD_0FC7_REG_7) },
3756   },
3757   /* REG_VEX_0F71 */
3758   {
3759     { Bad_Opcode },
3760     { Bad_Opcode },
3761     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3762     { Bad_Opcode },
3763     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3764     { Bad_Opcode },
3765     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3766   },
3767   /* REG_VEX_0F72 */
3768   {
3769     { Bad_Opcode },
3770     { Bad_Opcode },
3771     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3772     { Bad_Opcode },
3773     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3774     { Bad_Opcode },
3775     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3776   },
3777   /* REG_VEX_0F73 */
3778   {
3779     { Bad_Opcode },
3780     { Bad_Opcode },
3781     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3782     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3783     { Bad_Opcode },
3784     { Bad_Opcode },
3785     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3786     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3787   },
3788   /* REG_VEX_0FAE */
3789   {
3790     { Bad_Opcode },
3791     { Bad_Opcode },
3792     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3793     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3794   },
3795   /* REG_VEX_0F38F3 */
3796   {
3797     { Bad_Opcode },
3798     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3799     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3800     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3801   },
3802   /* REG_XOP_LWPCB */
3803   {
3804     { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3805     { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3806   },
3807   /* REG_XOP_LWP */
3808   {
3809     { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3810     { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3811   },
3812   /* REG_XOP_TBM_01 */
3813   {
3814     { Bad_Opcode },
3815     { "blcfill",        { { OP_LWP_E, 0 }, Ev }, 0 },
3816     { "blsfill",        { { OP_LWP_E, 0 }, Ev }, 0 },
3817     { "blcs",   { { OP_LWP_E, 0 }, Ev }, 0 },
3818     { "tzmsk",  { { OP_LWP_E, 0 }, Ev }, 0 },
3819     { "blcic",  { { OP_LWP_E, 0 }, Ev }, 0 },
3820     { "blsic",  { { OP_LWP_E, 0 }, Ev }, 0 },
3821     { "t1mskc", { { OP_LWP_E, 0 }, Ev }, 0 },
3822   },
3823   /* REG_XOP_TBM_02 */
3824   {
3825     { Bad_Opcode },
3826     { "blcmsk", { { OP_LWP_E, 0 }, Ev }, 0 },
3827     { Bad_Opcode },
3828     { Bad_Opcode },
3829     { Bad_Opcode },
3830     { Bad_Opcode },
3831     { "blci",   { { OP_LWP_E, 0 }, Ev }, 0 },
3832   },
3833 #define NEED_REG_TABLE
3834 #include "i386-dis-evex.h"
3835 #undef NEED_REG_TABLE
3836 };
3837
3838 static const struct dis386 prefix_table[][4] = {
3839   /* PREFIX_90 */
3840   {
3841     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3842     { "pause", { XX }, 0 },
3843     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3844     { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3845   },
3846
3847   /* PREFIX_MOD_0_0F01_REG_5 */
3848   {
3849     { Bad_Opcode },
3850     { "rstorssp",       { Mq }, PREFIX_OPCODE },
3851   },
3852
3853   /* PREFIX_MOD_3_0F01_REG_5_RM_0 */
3854   {
3855     { Bad_Opcode },
3856     { "setssbsy",       { Skip_MODRM }, PREFIX_OPCODE },
3857   },
3858
3859   /* PREFIX_MOD_3_0F01_REG_5_RM_2 */
3860   {
3861     { Bad_Opcode },
3862     { "saveprevssp",    { Skip_MODRM }, PREFIX_OPCODE },
3863   },
3864
3865   /* PREFIX_0F09 */
3866   {
3867     { "wbinvd",   { XX }, 0 },
3868     { "wbnoinvd", { XX }, 0 },
3869   },
3870
3871   /* PREFIX_0F10 */
3872   {
3873     { "movups", { XM, EXx }, PREFIX_OPCODE },
3874     { "movss",  { XM, EXd }, PREFIX_OPCODE },
3875     { "movupd", { XM, EXx }, PREFIX_OPCODE },
3876     { "movsd",  { XM, EXq }, PREFIX_OPCODE },
3877   },
3878
3879   /* PREFIX_0F11 */
3880   {
3881     { "movups", { EXxS, XM }, PREFIX_OPCODE },
3882     { "movss",  { EXdS, XM }, PREFIX_OPCODE },
3883     { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3884     { "movsd",  { EXqS, XM }, PREFIX_OPCODE },
3885   },
3886
3887   /* PREFIX_0F12 */
3888   {
3889     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3890     { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3891     { "movlpd", { XM, EXq }, PREFIX_OPCODE },
3892     { "movddup", { XM, EXq }, PREFIX_OPCODE },
3893   },
3894
3895   /* PREFIX_0F16 */
3896   {
3897     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3898     { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3899     { "movhpd", { XM, EXq }, PREFIX_OPCODE },
3900   },
3901
3902   /* PREFIX_0F1A */
3903   {
3904     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3905     { "bndcl",  { Gbnd, Ev_bnd }, 0 },
3906     { "bndmov", { Gbnd, Ebnd }, 0 },
3907     { "bndcu",  { Gbnd, Ev_bnd }, 0 },
3908   },
3909
3910   /* PREFIX_0F1B */
3911   {
3912     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3913     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3914     { "bndmov", { EbndS, Gbnd }, 0 },
3915     { "bndcn",  { Gbnd, Ev_bnd }, 0 },
3916   },
3917
3918   /* PREFIX_0F1C */
3919   {
3920     { MOD_TABLE (MOD_0F1C_PREFIX_0) },
3921     { "nopQ",   { Ev }, PREFIX_OPCODE },
3922     { "nopQ",   { Ev }, PREFIX_OPCODE },
3923     { "nopQ",   { Ev }, PREFIX_OPCODE },
3924   },
3925
3926   /* PREFIX_0F1E */
3927   {
3928     { "nopQ",   { Ev }, PREFIX_OPCODE },
3929     { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3930     { "nopQ",   { Ev }, PREFIX_OPCODE },
3931     { "nopQ",   { Ev }, PREFIX_OPCODE },
3932   },
3933
3934   /* PREFIX_0F2A */
3935   {
3936     { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3937     { "cvtsi2ss%LQ", { XM, Ev }, PREFIX_OPCODE },
3938     { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3939     { "cvtsi2sd%LQ", { XM, Ev }, 0 },
3940   },
3941
3942   /* PREFIX_0F2B */
3943   {
3944     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3945     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3946     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3947     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3948   },
3949
3950   /* PREFIX_0F2C */
3951   {
3952     { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3953     { "cvttss2si", { Gv, EXd }, PREFIX_OPCODE },
3954     { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3955     { "cvttsd2si", { Gv, EXq }, PREFIX_OPCODE },
3956   },
3957
3958   /* PREFIX_0F2D */
3959   {
3960     { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3961     { "cvtss2si", { Gv, EXd }, PREFIX_OPCODE },
3962     { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3963     { "cvtsd2si", { Gv, EXq }, PREFIX_OPCODE },
3964   },
3965
3966   /* PREFIX_0F2E */
3967   {
3968     { "ucomiss",{ XM, EXd }, 0 },
3969     { Bad_Opcode },
3970     { "ucomisd",{ XM, EXq }, 0 },
3971   },
3972
3973   /* PREFIX_0F2F */
3974   {
3975     { "comiss", { XM, EXd }, 0 },
3976     { Bad_Opcode },
3977     { "comisd", { XM, EXq }, 0 },
3978   },
3979
3980   /* PREFIX_0F51 */
3981   {
3982     { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3983     { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3984     { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3985     { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3986   },
3987
3988   /* PREFIX_0F52 */
3989   {
3990     { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3991     { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3992   },
3993
3994   /* PREFIX_0F53 */
3995   {
3996     { "rcpps",  { XM, EXx }, PREFIX_OPCODE },
3997     { "rcpss",  { XM, EXd }, PREFIX_OPCODE },
3998   },
3999
4000   /* PREFIX_0F58 */
4001   {
4002     { "addps", { XM, EXx }, PREFIX_OPCODE },
4003     { "addss", { XM, EXd }, PREFIX_OPCODE },
4004     { "addpd", { XM, EXx }, PREFIX_OPCODE },
4005     { "addsd", { XM, EXq }, PREFIX_OPCODE },
4006   },
4007
4008   /* PREFIX_0F59 */
4009   {
4010     { "mulps",  { XM, EXx }, PREFIX_OPCODE },
4011     { "mulss",  { XM, EXd }, PREFIX_OPCODE },
4012     { "mulpd",  { XM, EXx }, PREFIX_OPCODE },
4013     { "mulsd",  { XM, EXq }, PREFIX_OPCODE },
4014   },
4015
4016   /* PREFIX_0F5A */
4017   {
4018     { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
4019     { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
4020     { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
4021     { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
4022   },
4023
4024   /* PREFIX_0F5B */
4025   {
4026     { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
4027     { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
4028     { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
4029   },
4030
4031   /* PREFIX_0F5C */
4032   {
4033     { "subps",  { XM, EXx }, PREFIX_OPCODE },
4034     { "subss",  { XM, EXd }, PREFIX_OPCODE },
4035     { "subpd",  { XM, EXx }, PREFIX_OPCODE },
4036     { "subsd",  { XM, EXq }, PREFIX_OPCODE },
4037   },
4038
4039   /* PREFIX_0F5D */
4040   {
4041     { "minps",  { XM, EXx }, PREFIX_OPCODE },
4042     { "minss",  { XM, EXd }, PREFIX_OPCODE },
4043     { "minpd",  { XM, EXx }, PREFIX_OPCODE },
4044     { "minsd",  { XM, EXq }, PREFIX_OPCODE },
4045   },
4046
4047   /* PREFIX_0F5E */
4048   {
4049     { "divps",  { XM, EXx }, PREFIX_OPCODE },
4050     { "divss",  { XM, EXd }, PREFIX_OPCODE },
4051     { "divpd",  { XM, EXx }, PREFIX_OPCODE },
4052     { "divsd",  { XM, EXq }, PREFIX_OPCODE },
4053   },
4054
4055   /* PREFIX_0F5F */
4056   {
4057     { "maxps",  { XM, EXx }, PREFIX_OPCODE },
4058     { "maxss",  { XM, EXd }, PREFIX_OPCODE },
4059     { "maxpd",  { XM, EXx }, PREFIX_OPCODE },
4060     { "maxsd",  { XM, EXq }, PREFIX_OPCODE },
4061   },
4062
4063   /* PREFIX_0F60 */
4064   {
4065     { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
4066     { Bad_Opcode },
4067     { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
4068   },
4069
4070   /* PREFIX_0F61 */
4071   {
4072     { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
4073     { Bad_Opcode },
4074     { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
4075   },
4076
4077   /* PREFIX_0F62 */
4078   {
4079     { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
4080     { Bad_Opcode },
4081     { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
4082   },
4083
4084   /* PREFIX_0F6C */
4085   {
4086     { Bad_Opcode },
4087     { Bad_Opcode },
4088     { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE },
4089   },
4090
4091   /* PREFIX_0F6D */
4092   {
4093     { Bad_Opcode },
4094     { Bad_Opcode },
4095     { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE },
4096   },
4097
4098   /* PREFIX_0F6F */
4099   {
4100     { "movq",   { MX, EM }, PREFIX_OPCODE },
4101     { "movdqu", { XM, EXx }, PREFIX_OPCODE },
4102     { "movdqa", { XM, EXx }, PREFIX_OPCODE },
4103   },
4104
4105   /* PREFIX_0F70 */
4106   {
4107     { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
4108     { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
4109     { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
4110     { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
4111   },
4112
4113   /* PREFIX_0F73_REG_3 */
4114   {
4115     { Bad_Opcode },
4116     { Bad_Opcode },
4117     { "psrldq", { XS, Ib }, 0 },
4118   },
4119
4120   /* PREFIX_0F73_REG_7 */
4121   {
4122     { Bad_Opcode },
4123     { Bad_Opcode },
4124     { "pslldq", { XS, Ib }, 0 },
4125   },
4126
4127   /* PREFIX_0F78 */
4128   {
4129     {"vmread",  { Em, Gm }, 0 },
4130     { Bad_Opcode },
4131     {"extrq",   { XS, Ib, Ib }, 0 },
4132     {"insertq", { XM, XS, Ib, Ib }, 0 },
4133   },
4134
4135   /* PREFIX_0F79 */
4136   {
4137     {"vmwrite", { Gm, Em }, 0 },
4138     { Bad_Opcode },
4139     {"extrq",   { XM, XS }, 0 },
4140     {"insertq", { XM, XS }, 0 },
4141   },
4142
4143   /* PREFIX_0F7C */
4144   {
4145     { Bad_Opcode },
4146     { Bad_Opcode },
4147     { "haddpd", { XM, EXx }, PREFIX_OPCODE },
4148     { "haddps", { XM, EXx }, PREFIX_OPCODE },
4149   },
4150
4151   /* PREFIX_0F7D */
4152   {
4153     { Bad_Opcode },
4154     { Bad_Opcode },
4155     { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
4156     { "hsubps", { XM, EXx }, PREFIX_OPCODE },
4157   },
4158
4159   /* PREFIX_0F7E */
4160   {
4161     { "movK",   { Edq, MX }, PREFIX_OPCODE },
4162     { "movq",   { XM, EXq }, PREFIX_OPCODE },
4163     { "movK",   { Edq, XM }, PREFIX_OPCODE },
4164   },
4165
4166   /* PREFIX_0F7F */
4167   {
4168     { "movq",   { EMS, MX }, PREFIX_OPCODE },
4169     { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
4170     { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
4171   },
4172
4173   /* PREFIX_0FAE_REG_0 */
4174   {
4175     { Bad_Opcode },
4176     { "rdfsbase", { Ev }, 0 },
4177   },
4178
4179   /* PREFIX_0FAE_REG_1 */
4180   {
4181     { Bad_Opcode },
4182     { "rdgsbase", { Ev }, 0 },
4183   },
4184
4185   /* PREFIX_0FAE_REG_2 */
4186   {
4187     { Bad_Opcode },
4188     { "wrfsbase", { Ev }, 0 },
4189   },
4190
4191   /* PREFIX_0FAE_REG_3 */
4192   {
4193     { Bad_Opcode },
4194     { "wrgsbase", { Ev }, 0 },
4195   },
4196
4197   /* PREFIX_MOD_0_0FAE_REG_4 */
4198   {
4199     { "xsave",  { FXSAVE }, 0 },
4200     { "ptwrite%LQ", { Edq }, 0 },
4201   },
4202
4203   /* PREFIX_MOD_3_0FAE_REG_4 */
4204   {
4205     { Bad_Opcode },
4206     { "ptwrite%LQ", { Edq }, 0 },
4207   },
4208
4209   /* PREFIX_MOD_0_0FAE_REG_5 */
4210   {
4211     { "xrstor",         { FXSAVE }, PREFIX_OPCODE },
4212   },
4213
4214   /* PREFIX_MOD_3_0FAE_REG_5 */
4215   {
4216     { "lfence",         { Skip_MODRM }, 0 },
4217     { "incsspK",        { Rdq }, PREFIX_OPCODE },
4218   },
4219
4220   /* PREFIX_MOD_0_0FAE_REG_6 */
4221   {
4222     { "xsaveopt",       { FXSAVE }, PREFIX_OPCODE },
4223     { "clrssbsy",       { Mq }, PREFIX_OPCODE },
4224     { "clwb",   { Mb }, PREFIX_OPCODE },
4225   },
4226
4227   /* PREFIX_MOD_1_0FAE_REG_6 */
4228   {
4229     { RM_TABLE (RM_0FAE_REG_6) },
4230     { "umonitor",       { Eva }, PREFIX_OPCODE },
4231     { "tpause", { Edq }, PREFIX_OPCODE },
4232     { "umwait", { Edq }, PREFIX_OPCODE },
4233   },
4234
4235   /* PREFIX_0FAE_REG_7 */
4236   {
4237     { "clflush",        { Mb }, 0 },
4238     { Bad_Opcode },
4239     { "clflushopt",     { Mb }, 0 },
4240   },
4241
4242   /* PREFIX_0FB8 */
4243   {
4244     { Bad_Opcode },
4245     { "popcntS", { Gv, Ev }, 0 },
4246   },
4247
4248   /* PREFIX_0FBC */
4249   {
4250     { "bsfS",   { Gv, Ev }, 0 },
4251     { "tzcntS", { Gv, Ev }, 0 },
4252     { "bsfS",   { Gv, Ev }, 0 },
4253   },
4254
4255   /* PREFIX_0FBD */
4256   {
4257     { "bsrS",   { Gv, Ev }, 0 },
4258     { "lzcntS", { Gv, Ev }, 0 },
4259     { "bsrS",   { Gv, Ev }, 0 },
4260   },
4261
4262   /* PREFIX_0FC2 */
4263   {
4264     { "cmpps",  { XM, EXx, CMP }, PREFIX_OPCODE },
4265     { "cmpss",  { XM, EXd, CMP }, PREFIX_OPCODE },
4266     { "cmppd",  { XM, EXx, CMP }, PREFIX_OPCODE },
4267     { "cmpsd",  { XM, EXq, CMP }, PREFIX_OPCODE },
4268   },
4269
4270   /* PREFIX_MOD_0_0FC3 */
4271   {
4272     { "movntiS", { Ev, Gv }, PREFIX_OPCODE },
4273   },
4274
4275   /* PREFIX_MOD_0_0FC7_REG_6 */
4276   {
4277     { "vmptrld",{ Mq }, 0 },
4278     { "vmxon",  { Mq }, 0 },
4279     { "vmclear",{ Mq }, 0 },
4280   },
4281
4282   /* PREFIX_MOD_3_0FC7_REG_6 */
4283   {
4284     { "rdrand", { Ev }, 0 },
4285     { Bad_Opcode },
4286     { "rdrand", { Ev }, 0 }
4287   },
4288
4289   /* PREFIX_MOD_3_0FC7_REG_7 */
4290   {
4291     { "rdseed", { Ev }, 0 },
4292     { "rdpid",  { Em }, 0 },
4293     { "rdseed", { Ev }, 0 },
4294   },
4295
4296   /* PREFIX_0FD0 */
4297   {
4298     { Bad_Opcode },
4299     { Bad_Opcode },
4300     { "addsubpd", { XM, EXx }, 0 },
4301     { "addsubps", { XM, EXx }, 0 },
4302   },
4303
4304   /* PREFIX_0FD6 */
4305   {
4306     { Bad_Opcode },
4307     { "movq2dq",{ XM, MS }, 0 },
4308     { "movq",   { EXqS, XM }, 0 },
4309     { "movdq2q",{ MX, XS }, 0 },
4310   },
4311
4312   /* PREFIX_0FE6 */
4313   {
4314     { Bad_Opcode },
4315     { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
4316     { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
4317     { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
4318   },
4319
4320   /* PREFIX_0FE7 */
4321   {
4322     { "movntq", { Mq, MX }, PREFIX_OPCODE },
4323     { Bad_Opcode },
4324     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
4325   },
4326
4327   /* PREFIX_0FF0 */
4328   {
4329     { Bad_Opcode },
4330     { Bad_Opcode },
4331     { Bad_Opcode },
4332     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4333   },
4334
4335   /* PREFIX_0FF7 */
4336   {
4337     { "maskmovq", { MX, MS }, PREFIX_OPCODE },
4338     { Bad_Opcode },
4339     { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
4340   },
4341
4342   /* PREFIX_0F3810 */
4343   {
4344     { Bad_Opcode },
4345     { Bad_Opcode },
4346     { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4347   },
4348
4349   /* PREFIX_0F3814 */
4350   {
4351     { Bad_Opcode },
4352     { Bad_Opcode },
4353     { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4354   },
4355
4356   /* PREFIX_0F3815 */
4357   {
4358     { Bad_Opcode },
4359     { Bad_Opcode },
4360     { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4361   },
4362
4363   /* PREFIX_0F3817 */
4364   {
4365     { Bad_Opcode },
4366     { Bad_Opcode },
4367     { "ptest",  { XM, EXx }, PREFIX_OPCODE },
4368   },
4369
4370   /* PREFIX_0F3820 */
4371   {
4372     { Bad_Opcode },
4373     { Bad_Opcode },
4374     { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE },
4375   },
4376
4377   /* PREFIX_0F3821 */
4378   {
4379     { Bad_Opcode },
4380     { Bad_Opcode },
4381     { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE },
4382   },
4383
4384   /* PREFIX_0F3822 */
4385   {
4386     { Bad_Opcode },
4387     { Bad_Opcode },
4388     { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE },
4389   },
4390
4391   /* PREFIX_0F3823 */
4392   {
4393     { Bad_Opcode },
4394     { Bad_Opcode },
4395     { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE },
4396   },
4397
4398   /* PREFIX_0F3824 */
4399   {
4400     { Bad_Opcode },
4401     { Bad_Opcode },
4402     { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE },
4403   },
4404
4405   /* PREFIX_0F3825 */
4406   {
4407     { Bad_Opcode },
4408     { Bad_Opcode },
4409     { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE },
4410   },
4411
4412   /* PREFIX_0F3828 */
4413   {
4414     { Bad_Opcode },
4415     { Bad_Opcode },
4416     { "pmuldq", { XM, EXx }, PREFIX_OPCODE },
4417   },
4418
4419   /* PREFIX_0F3829 */
4420   {
4421     { Bad_Opcode },
4422     { Bad_Opcode },
4423     { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE },
4424   },
4425
4426   /* PREFIX_0F382A */
4427   {
4428     { Bad_Opcode },
4429     { Bad_Opcode },
4430     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4431   },
4432
4433   /* PREFIX_0F382B */
4434   {
4435     { Bad_Opcode },
4436     { Bad_Opcode },
4437     { "packusdw", { XM, EXx }, PREFIX_OPCODE },
4438   },
4439
4440   /* PREFIX_0F3830 */
4441   {
4442     { Bad_Opcode },
4443     { Bad_Opcode },
4444     { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE },
4445   },
4446
4447   /* PREFIX_0F3831 */
4448   {
4449     { Bad_Opcode },
4450     { Bad_Opcode },
4451     { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE },
4452   },
4453
4454   /* PREFIX_0F3832 */
4455   {
4456     { Bad_Opcode },
4457     { Bad_Opcode },
4458     { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE },
4459   },
4460
4461   /* PREFIX_0F3833 */
4462   {
4463     { Bad_Opcode },
4464     { Bad_Opcode },
4465     { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE },
4466   },
4467
4468   /* PREFIX_0F3834 */
4469   {
4470     { Bad_Opcode },
4471     { Bad_Opcode },
4472     { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE },
4473   },
4474
4475   /* PREFIX_0F3835 */
4476   {
4477     { Bad_Opcode },
4478     { Bad_Opcode },
4479     { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE },
4480   },
4481
4482   /* PREFIX_0F3837 */
4483   {
4484     { Bad_Opcode },
4485     { Bad_Opcode },
4486     { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE },
4487   },
4488
4489   /* PREFIX_0F3838 */
4490   {
4491     { Bad_Opcode },
4492     { Bad_Opcode },
4493     { "pminsb", { XM, EXx }, PREFIX_OPCODE },
4494   },
4495
4496   /* PREFIX_0F3839 */
4497   {
4498     { Bad_Opcode },
4499     { Bad_Opcode },
4500     { "pminsd", { XM, EXx }, PREFIX_OPCODE },
4501   },
4502
4503   /* PREFIX_0F383A */
4504   {
4505     { Bad_Opcode },
4506     { Bad_Opcode },
4507     { "pminuw", { XM, EXx }, PREFIX_OPCODE },
4508   },
4509
4510   /* PREFIX_0F383B */
4511   {
4512     { Bad_Opcode },
4513     { Bad_Opcode },
4514     { "pminud", { XM, EXx }, PREFIX_OPCODE },
4515   },
4516
4517   /* PREFIX_0F383C */
4518   {
4519     { Bad_Opcode },
4520     { Bad_Opcode },
4521     { "pmaxsb", { XM, EXx }, PREFIX_OPCODE },
4522   },
4523
4524   /* PREFIX_0F383D */
4525   {
4526     { Bad_Opcode },
4527     { Bad_Opcode },
4528     { "pmaxsd", { XM, EXx }, PREFIX_OPCODE },
4529   },
4530
4531   /* PREFIX_0F383E */
4532   {
4533     { Bad_Opcode },
4534     { Bad_Opcode },
4535     { "pmaxuw", { XM, EXx }, PREFIX_OPCODE },
4536   },
4537
4538   /* PREFIX_0F383F */
4539   {
4540     { Bad_Opcode },
4541     { Bad_Opcode },
4542     { "pmaxud", { XM, EXx }, PREFIX_OPCODE },
4543   },
4544
4545   /* PREFIX_0F3840 */
4546   {
4547     { Bad_Opcode },
4548     { Bad_Opcode },
4549     { "pmulld", { XM, EXx }, PREFIX_OPCODE },
4550   },
4551
4552   /* PREFIX_0F3841 */
4553   {
4554     { Bad_Opcode },
4555     { Bad_Opcode },
4556     { "phminposuw", { XM, EXx }, PREFIX_OPCODE },
4557   },
4558
4559   /* PREFIX_0F3880 */
4560   {
4561     { Bad_Opcode },
4562     { Bad_Opcode },
4563     { "invept", { Gm, Mo }, PREFIX_OPCODE },
4564   },
4565
4566   /* PREFIX_0F3881 */
4567   {
4568     { Bad_Opcode },
4569     { Bad_Opcode },
4570     { "invvpid", { Gm, Mo }, PREFIX_OPCODE },
4571   },
4572
4573   /* PREFIX_0F3882 */
4574   {
4575     { Bad_Opcode },
4576     { Bad_Opcode },
4577     { "invpcid", { Gm, M }, PREFIX_OPCODE },
4578   },
4579
4580   /* PREFIX_0F38C8 */
4581   {
4582     { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4583   },
4584
4585   /* PREFIX_0F38C9 */
4586   {
4587     { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4588   },
4589
4590   /* PREFIX_0F38CA */
4591   {
4592     { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4593   },
4594
4595   /* PREFIX_0F38CB */
4596   {
4597     { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4598   },
4599
4600   /* PREFIX_0F38CC */
4601   {
4602     { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4603   },
4604
4605   /* PREFIX_0F38CD */
4606   {
4607     { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4608   },
4609
4610   /* PREFIX_0F38CF */
4611   {
4612     { Bad_Opcode },
4613     { Bad_Opcode },
4614     { "gf2p8mulb", { XM, EXxmm }, PREFIX_OPCODE },
4615   },
4616
4617   /* PREFIX_0F38DB */
4618   {
4619     { Bad_Opcode },
4620     { Bad_Opcode },
4621     { "aesimc", { XM, EXx }, PREFIX_OPCODE },
4622   },
4623
4624   /* PREFIX_0F38DC */
4625   {
4626     { Bad_Opcode },
4627     { Bad_Opcode },
4628     { "aesenc", { XM, EXx }, PREFIX_OPCODE },
4629   },
4630
4631   /* PREFIX_0F38DD */
4632   {
4633     { Bad_Opcode },
4634     { Bad_Opcode },
4635     { "aesenclast", { XM, EXx }, PREFIX_OPCODE },
4636   },
4637
4638   /* PREFIX_0F38DE */
4639   {
4640     { Bad_Opcode },
4641     { Bad_Opcode },
4642     { "aesdec", { XM, EXx }, PREFIX_OPCODE },
4643   },
4644
4645   /* PREFIX_0F38DF */
4646   {
4647     { Bad_Opcode },
4648     { Bad_Opcode },
4649     { "aesdeclast", { XM, EXx }, PREFIX_OPCODE },
4650   },
4651
4652   /* PREFIX_0F38F0 */
4653   {
4654     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4655     { Bad_Opcode },
4656     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4657     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE },
4658   },
4659
4660   /* PREFIX_0F38F1 */
4661   {
4662     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4663     { Bad_Opcode },
4664     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4665     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE },
4666   },
4667
4668   /* PREFIX_0F38F5 */
4669   {
4670     { Bad_Opcode },
4671     { Bad_Opcode },
4672     { MOD_TABLE (MOD_0F38F5_PREFIX_2) },
4673   },
4674
4675   /* PREFIX_0F38F6 */
4676   {
4677     { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
4678     { "adoxS",  { Gdq, Edq}, PREFIX_OPCODE },
4679     { "adcxS",  { Gdq, Edq}, PREFIX_OPCODE },
4680     { Bad_Opcode },
4681   },
4682
4683   /* PREFIX_0F3A08 */
4684   {
4685     { Bad_Opcode },
4686     { Bad_Opcode },
4687     { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE },
4688   },
4689
4690   /* PREFIX_0F3A09 */
4691   {
4692     { Bad_Opcode },
4693     { Bad_Opcode },
4694     { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4695   },
4696
4697   /* PREFIX_0F3A0A */
4698   {
4699     { Bad_Opcode },
4700     { Bad_Opcode },
4701     { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE },
4702   },
4703
4704   /* PREFIX_0F3A0B */
4705   {
4706     { Bad_Opcode },
4707     { Bad_Opcode },
4708     { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE },
4709   },
4710
4711   /* PREFIX_0F3A0C */
4712   {
4713     { Bad_Opcode },
4714     { Bad_Opcode },
4715     { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE },
4716   },
4717
4718   /* PREFIX_0F3A0D */
4719   {
4720     { Bad_Opcode },
4721     { Bad_Opcode },
4722     { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4723   },
4724
4725   /* PREFIX_0F3A0E */
4726   {
4727     { Bad_Opcode },
4728     { Bad_Opcode },
4729     { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE },
4730   },
4731
4732   /* PREFIX_0F3A14 */
4733   {
4734     { Bad_Opcode },
4735     { Bad_Opcode },
4736     { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE },
4737   },
4738
4739   /* PREFIX_0F3A15 */
4740   {
4741     { Bad_Opcode },
4742     { Bad_Opcode },
4743     { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE },
4744   },
4745
4746   /* PREFIX_0F3A16 */
4747   {
4748     { Bad_Opcode },
4749     { Bad_Opcode },
4750     { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE },
4751   },
4752
4753   /* PREFIX_0F3A17 */
4754   {
4755     { Bad_Opcode },
4756     { Bad_Opcode },
4757     { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE },
4758   },
4759
4760   /* PREFIX_0F3A20 */
4761   {
4762     { Bad_Opcode },
4763     { Bad_Opcode },
4764     { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE },
4765   },
4766
4767   /* PREFIX_0F3A21 */
4768   {
4769     { Bad_Opcode },
4770     { Bad_Opcode },
4771     { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE },
4772   },
4773
4774   /* PREFIX_0F3A22 */
4775   {
4776     { Bad_Opcode },
4777     { Bad_Opcode },
4778     { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE },
4779   },
4780
4781   /* PREFIX_0F3A40 */
4782   {
4783     { Bad_Opcode },
4784     { Bad_Opcode },
4785     { "dpps",   { XM, EXx, Ib }, PREFIX_OPCODE },
4786   },
4787
4788   /* PREFIX_0F3A41 */
4789   {
4790     { Bad_Opcode },
4791     { Bad_Opcode },
4792     { "dppd",   { XM, EXx, Ib }, PREFIX_OPCODE },
4793   },
4794
4795   /* PREFIX_0F3A42 */
4796   {
4797     { Bad_Opcode },
4798     { Bad_Opcode },
4799     { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE },
4800   },
4801
4802   /* PREFIX_0F3A44 */
4803   {
4804     { Bad_Opcode },
4805     { Bad_Opcode },
4806     { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE },
4807   },
4808
4809   /* PREFIX_0F3A60 */
4810   {
4811     { Bad_Opcode },
4812     { Bad_Opcode },
4813     { "pcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4814   },
4815
4816   /* PREFIX_0F3A61 */
4817   {
4818     { Bad_Opcode },
4819     { Bad_Opcode },
4820     { "pcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4821   },
4822
4823   /* PREFIX_0F3A62 */
4824   {
4825     { Bad_Opcode },
4826     { Bad_Opcode },
4827     { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4828   },
4829
4830   /* PREFIX_0F3A63 */
4831   {
4832     { Bad_Opcode },
4833     { Bad_Opcode },
4834     { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE },
4835   },
4836
4837   /* PREFIX_0F3ACC */
4838   {
4839     { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4840   },
4841
4842   /* PREFIX_0F3ACE */
4843   {
4844     { Bad_Opcode },
4845     { Bad_Opcode },
4846     { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4847   },
4848
4849   /* PREFIX_0F3ACF */
4850   {
4851     { Bad_Opcode },
4852     { Bad_Opcode },
4853     { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4854   },
4855
4856   /* PREFIX_0F3ADF */
4857   {
4858     { Bad_Opcode },
4859     { Bad_Opcode },
4860     { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE },
4861   },
4862
4863   /* PREFIX_VEX_0F10 */
4864   {
4865     { VEX_W_TABLE (VEX_W_0F10_P_0) },
4866     { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) },
4867     { VEX_W_TABLE (VEX_W_0F10_P_2) },
4868     { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) },
4869   },
4870
4871   /* PREFIX_VEX_0F11 */
4872   {
4873     { VEX_W_TABLE (VEX_W_0F11_P_0) },
4874     { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) },
4875     { VEX_W_TABLE (VEX_W_0F11_P_2) },
4876     { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) },
4877   },
4878
4879   /* PREFIX_VEX_0F12 */
4880   {
4881     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4882     { VEX_W_TABLE (VEX_W_0F12_P_1) },
4883     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
4884     { VEX_W_TABLE (VEX_W_0F12_P_3) },
4885   },
4886
4887   /* PREFIX_VEX_0F16 */
4888   {
4889     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4890     { VEX_W_TABLE (VEX_W_0F16_P_1) },
4891     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
4892   },
4893
4894   /* PREFIX_VEX_0F2A */
4895   {
4896     { Bad_Opcode },
4897     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) },
4898     { Bad_Opcode },
4899     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) },
4900   },
4901
4902   /* PREFIX_VEX_0F2C */
4903   {
4904     { Bad_Opcode },
4905     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) },
4906     { Bad_Opcode },
4907     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) },
4908   },
4909
4910   /* PREFIX_VEX_0F2D */
4911   {
4912     { Bad_Opcode },
4913     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) },
4914     { Bad_Opcode },
4915     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) },
4916   },
4917
4918   /* PREFIX_VEX_0F2E */
4919   {
4920     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) },
4921     { Bad_Opcode },
4922     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) },
4923   },
4924
4925   /* PREFIX_VEX_0F2F */
4926   {
4927     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) },
4928     { Bad_Opcode },
4929     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) },
4930   },
4931
4932   /* PREFIX_VEX_0F41 */
4933   {
4934     { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4935     { Bad_Opcode },
4936     { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4937   },
4938
4939   /* PREFIX_VEX_0F42 */
4940   {
4941     { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4942     { Bad_Opcode },
4943     { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4944   },
4945
4946   /* PREFIX_VEX_0F44 */
4947   {
4948     { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4949     { Bad_Opcode },
4950     { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4951   },
4952
4953   /* PREFIX_VEX_0F45 */
4954   {
4955     { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4956     { Bad_Opcode },
4957     { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4958   },
4959
4960   /* PREFIX_VEX_0F46 */
4961   {
4962     { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4963     { Bad_Opcode },
4964     { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4965   },
4966
4967   /* PREFIX_VEX_0F47 */
4968   {
4969     { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4970     { Bad_Opcode },
4971     { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
4972   },
4973
4974   /* PREFIX_VEX_0F4A */
4975   {
4976     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
4977     { Bad_Opcode },
4978     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
4979   },
4980
4981   /* PREFIX_VEX_0F4B */
4982   {
4983     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
4984     { Bad_Opcode },
4985     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4986   },
4987
4988   /* PREFIX_VEX_0F51 */
4989   {
4990     { VEX_W_TABLE (VEX_W_0F51_P_0) },
4991     { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) },
4992     { VEX_W_TABLE (VEX_W_0F51_P_2) },
4993     { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) },
4994   },
4995
4996   /* PREFIX_VEX_0F52 */
4997   {
4998     { VEX_W_TABLE (VEX_W_0F52_P_0) },
4999     { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) },
5000   },
5001
5002   /* PREFIX_VEX_0F53 */
5003   {
5004     { VEX_W_TABLE (VEX_W_0F53_P_0) },
5005     { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) },
5006   },
5007
5008   /* PREFIX_VEX_0F58 */
5009   {
5010     { VEX_W_TABLE (VEX_W_0F58_P_0) },
5011     { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) },
5012     { VEX_W_TABLE (VEX_W_0F58_P_2) },
5013     { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) },
5014   },
5015
5016   /* PREFIX_VEX_0F59 */
5017   {
5018     { VEX_W_TABLE (VEX_W_0F59_P_0) },
5019     { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) },
5020     { VEX_W_TABLE (VEX_W_0F59_P_2) },
5021     { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) },
5022   },
5023
5024   /* PREFIX_VEX_0F5A */
5025   {
5026     { VEX_W_TABLE (VEX_W_0F5A_P_0) },
5027     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) },
5028     { "vcvtpd2ps%XY", { XMM, EXx }, 0 },
5029     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) },
5030   },
5031
5032   /* PREFIX_VEX_0F5B */
5033   {
5034     { VEX_W_TABLE (VEX_W_0F5B_P_0) },
5035     { VEX_W_TABLE (VEX_W_0F5B_P_1) },
5036     { VEX_W_TABLE (VEX_W_0F5B_P_2) },
5037   },
5038
5039   /* PREFIX_VEX_0F5C */
5040   {
5041     { VEX_W_TABLE (VEX_W_0F5C_P_0) },
5042     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) },
5043     { VEX_W_TABLE (VEX_W_0F5C_P_2) },
5044     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) },
5045   },
5046
5047   /* PREFIX_VEX_0F5D */
5048   {
5049     { VEX_W_TABLE (VEX_W_0F5D_P_0) },
5050     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) },
5051     { VEX_W_TABLE (VEX_W_0F5D_P_2) },
5052     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) },
5053   },
5054
5055   /* PREFIX_VEX_0F5E */
5056   {
5057     { VEX_W_TABLE (VEX_W_0F5E_P_0) },
5058     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) },
5059     { VEX_W_TABLE (VEX_W_0F5E_P_2) },
5060     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) },
5061   },
5062
5063   /* PREFIX_VEX_0F5F */
5064   {
5065     { VEX_W_TABLE (VEX_W_0F5F_P_0) },
5066     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) },
5067     { VEX_W_TABLE (VEX_W_0F5F_P_2) },
5068     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) },
5069   },
5070
5071   /* PREFIX_VEX_0F60 */
5072   {
5073     { Bad_Opcode },
5074     { Bad_Opcode },
5075     { VEX_W_TABLE (VEX_W_0F60_P_2) },
5076   },
5077
5078   /* PREFIX_VEX_0F61 */
5079   {
5080     { Bad_Opcode },
5081     { Bad_Opcode },
5082     { VEX_W_TABLE (VEX_W_0F61_P_2) },
5083   },
5084
5085   /* PREFIX_VEX_0F62 */
5086   {
5087     { Bad_Opcode },
5088     { Bad_Opcode },
5089     { VEX_W_TABLE (VEX_W_0F62_P_2) },
5090   },
5091
5092   /* PREFIX_VEX_0F63 */
5093   {
5094     { Bad_Opcode },
5095     { Bad_Opcode },
5096     { VEX_W_TABLE (VEX_W_0F63_P_2) },
5097   },
5098
5099   /* PREFIX_VEX_0F64 */
5100   {
5101     { Bad_Opcode },
5102     { Bad_Opcode },
5103     { VEX_W_TABLE (VEX_W_0F64_P_2) },
5104   },
5105
5106   /* PREFIX_VEX_0F65 */
5107   {
5108     { Bad_Opcode },
5109     { Bad_Opcode },
5110     { VEX_W_TABLE (VEX_W_0F65_P_2) },
5111   },
5112
5113   /* PREFIX_VEX_0F66 */
5114   {
5115     { Bad_Opcode },
5116     { Bad_Opcode },
5117     { VEX_W_TABLE (VEX_W_0F66_P_2) },
5118   },
5119
5120   /* PREFIX_VEX_0F67 */
5121   {
5122     { Bad_Opcode },
5123     { Bad_Opcode },
5124     { VEX_W_TABLE (VEX_W_0F67_P_2) },
5125   },
5126
5127   /* PREFIX_VEX_0F68 */
5128   {
5129     { Bad_Opcode },
5130     { Bad_Opcode },
5131     { VEX_W_TABLE (VEX_W_0F68_P_2) },
5132   },
5133
5134   /* PREFIX_VEX_0F69 */
5135   {
5136     { Bad_Opcode },
5137     { Bad_Opcode },
5138     { VEX_W_TABLE (VEX_W_0F69_P_2) },
5139   },
5140
5141   /* PREFIX_VEX_0F6A */
5142   {
5143     { Bad_Opcode },
5144     { Bad_Opcode },
5145     { VEX_W_TABLE (VEX_W_0F6A_P_2) },
5146   },
5147
5148   /* PREFIX_VEX_0F6B */
5149   {
5150     { Bad_Opcode },
5151     { Bad_Opcode },
5152     { VEX_W_TABLE (VEX_W_0F6B_P_2) },
5153   },
5154
5155   /* PREFIX_VEX_0F6C */
5156   {
5157     { Bad_Opcode },
5158     { Bad_Opcode },
5159     { VEX_W_TABLE (VEX_W_0F6C_P_2) },
5160   },
5161
5162   /* PREFIX_VEX_0F6D */
5163   {
5164     { Bad_Opcode },
5165     { Bad_Opcode },
5166     { VEX_W_TABLE (VEX_W_0F6D_P_2) },
5167   },
5168
5169   /* PREFIX_VEX_0F6E */
5170   {
5171     { Bad_Opcode },
5172     { Bad_Opcode },
5173     { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
5174   },
5175
5176   /* PREFIX_VEX_0F6F */
5177   {
5178     { Bad_Opcode },
5179     { VEX_W_TABLE (VEX_W_0F6F_P_1) },
5180     { VEX_W_TABLE (VEX_W_0F6F_P_2) },
5181   },
5182
5183   /* PREFIX_VEX_0F70 */
5184   {
5185     { Bad_Opcode },
5186     { VEX_W_TABLE (VEX_W_0F70_P_1) },
5187     { VEX_W_TABLE (VEX_W_0F70_P_2) },
5188     { VEX_W_TABLE (VEX_W_0F70_P_3) },
5189   },
5190
5191   /* PREFIX_VEX_0F71_REG_2 */
5192   {
5193     { Bad_Opcode },
5194     { Bad_Opcode },
5195     { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) },
5196   },
5197
5198   /* PREFIX_VEX_0F71_REG_4 */
5199   {
5200     { Bad_Opcode },
5201     { Bad_Opcode },
5202     { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) },
5203   },
5204
5205   /* PREFIX_VEX_0F71_REG_6 */
5206   {
5207     { Bad_Opcode },
5208     { Bad_Opcode },
5209     { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) },
5210   },
5211
5212   /* PREFIX_VEX_0F72_REG_2 */
5213   {
5214     { Bad_Opcode },
5215     { Bad_Opcode },
5216     { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) },
5217   },
5218
5219   /* PREFIX_VEX_0F72_REG_4 */
5220   {
5221     { Bad_Opcode },
5222     { Bad_Opcode },
5223     { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) },
5224   },
5225
5226   /* PREFIX_VEX_0F72_REG_6 */
5227   {
5228     { Bad_Opcode },
5229     { Bad_Opcode },
5230     { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) },
5231   },
5232
5233   /* PREFIX_VEX_0F73_REG_2 */
5234   {
5235     { Bad_Opcode },
5236     { Bad_Opcode },
5237     { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) },
5238   },
5239
5240   /* PREFIX_VEX_0F73_REG_3 */
5241   {
5242     { Bad_Opcode },
5243     { Bad_Opcode },
5244     { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) },
5245   },
5246
5247   /* PREFIX_VEX_0F73_REG_6 */
5248   {
5249     { Bad_Opcode },
5250     { Bad_Opcode },
5251     { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) },
5252   },
5253
5254   /* PREFIX_VEX_0F73_REG_7 */
5255   {
5256     { Bad_Opcode },
5257     { Bad_Opcode },
5258     { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) },
5259   },
5260
5261   /* PREFIX_VEX_0F74 */
5262   {
5263     { Bad_Opcode },
5264     { Bad_Opcode },
5265     { VEX_W_TABLE (VEX_W_0F74_P_2) },
5266   },
5267
5268   /* PREFIX_VEX_0F75 */
5269   {
5270     { Bad_Opcode },
5271     { Bad_Opcode },
5272     { VEX_W_TABLE (VEX_W_0F75_P_2) },
5273   },
5274
5275   /* PREFIX_VEX_0F76 */
5276   {
5277     { Bad_Opcode },
5278     { Bad_Opcode },
5279     { VEX_W_TABLE (VEX_W_0F76_P_2) },
5280   },
5281
5282   /* PREFIX_VEX_0F77 */
5283   {
5284     { VEX_W_TABLE (VEX_W_0F77_P_0) },
5285   },
5286
5287   /* PREFIX_VEX_0F7C */
5288   {
5289     { Bad_Opcode },
5290     { Bad_Opcode },
5291     { VEX_W_TABLE (VEX_W_0F7C_P_2) },
5292     { VEX_W_TABLE (VEX_W_0F7C_P_3) },
5293   },
5294
5295   /* PREFIX_VEX_0F7D */
5296   {
5297     { Bad_Opcode },
5298     { Bad_Opcode },
5299     { VEX_W_TABLE (VEX_W_0F7D_P_2) },
5300     { VEX_W_TABLE (VEX_W_0F7D_P_3) },
5301   },
5302
5303   /* PREFIX_VEX_0F7E */
5304   {
5305     { Bad_Opcode },
5306     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
5307     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
5308   },
5309
5310   /* PREFIX_VEX_0F7F */
5311   {
5312     { Bad_Opcode },
5313     { VEX_W_TABLE (VEX_W_0F7F_P_1) },
5314     { VEX_W_TABLE (VEX_W_0F7F_P_2) },
5315   },
5316
5317   /* PREFIX_VEX_0F90 */
5318   {
5319     { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
5320     { Bad_Opcode },
5321     { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
5322   },
5323
5324   /* PREFIX_VEX_0F91 */
5325   {
5326     { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
5327     { Bad_Opcode },
5328     { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
5329   },
5330
5331   /* PREFIX_VEX_0F92 */
5332   {
5333     { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
5334     { Bad_Opcode },
5335     { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
5336     { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
5337   },
5338
5339   /* PREFIX_VEX_0F93 */
5340   {
5341     { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
5342     { Bad_Opcode },
5343     { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
5344     { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
5345   },
5346
5347   /* PREFIX_VEX_0F98 */
5348   {
5349     { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
5350     { Bad_Opcode },
5351     { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
5352   },
5353
5354   /* PREFIX_VEX_0F99 */
5355   {
5356     { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5357     { Bad_Opcode },
5358     { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5359   },
5360
5361   /* PREFIX_VEX_0FC2 */
5362   {
5363     { VEX_W_TABLE (VEX_W_0FC2_P_0) },
5364     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) },
5365     { VEX_W_TABLE (VEX_W_0FC2_P_2) },
5366     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) },
5367   },
5368
5369   /* PREFIX_VEX_0FC4 */
5370   {
5371     { Bad_Opcode },
5372     { Bad_Opcode },
5373     { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5374   },
5375
5376   /* PREFIX_VEX_0FC5 */
5377   {
5378     { Bad_Opcode },
5379     { Bad_Opcode },
5380     { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5381   },
5382
5383   /* PREFIX_VEX_0FD0 */
5384   {
5385     { Bad_Opcode },
5386     { Bad_Opcode },
5387     { VEX_W_TABLE (VEX_W_0FD0_P_2) },
5388     { VEX_W_TABLE (VEX_W_0FD0_P_3) },
5389   },
5390
5391   /* PREFIX_VEX_0FD1 */
5392   {
5393     { Bad_Opcode },
5394     { Bad_Opcode },
5395     { VEX_W_TABLE (VEX_W_0FD1_P_2) },
5396   },
5397
5398   /* PREFIX_VEX_0FD2 */
5399   {
5400     { Bad_Opcode },
5401     { Bad_Opcode },
5402     { VEX_W_TABLE (VEX_W_0FD2_P_2) },
5403   },
5404
5405   /* PREFIX_VEX_0FD3 */
5406   {
5407     { Bad_Opcode },
5408     { Bad_Opcode },
5409     { VEX_W_TABLE (VEX_W_0FD3_P_2) },
5410   },
5411
5412   /* PREFIX_VEX_0FD4 */
5413   {
5414     { Bad_Opcode },
5415     { Bad_Opcode },
5416     { VEX_W_TABLE (VEX_W_0FD4_P_2) },
5417   },
5418
5419   /* PREFIX_VEX_0FD5 */
5420   {
5421     { Bad_Opcode },
5422     { Bad_Opcode },
5423     { VEX_W_TABLE (VEX_W_0FD5_P_2) },
5424   },
5425
5426   /* PREFIX_VEX_0FD6 */
5427   {
5428     { Bad_Opcode },
5429     { Bad_Opcode },
5430     { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5431   },
5432
5433   /* PREFIX_VEX_0FD7 */
5434   {
5435     { Bad_Opcode },
5436     { Bad_Opcode },
5437     { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5438   },
5439
5440   /* PREFIX_VEX_0FD8 */
5441   {
5442     { Bad_Opcode },
5443     { Bad_Opcode },
5444     { VEX_W_TABLE (VEX_W_0FD8_P_2) },
5445   },
5446
5447   /* PREFIX_VEX_0FD9 */
5448   {
5449     { Bad_Opcode },
5450     { Bad_Opcode },
5451     { VEX_W_TABLE (VEX_W_0FD9_P_2) },
5452   },
5453
5454   /* PREFIX_VEX_0FDA */
5455   {
5456     { Bad_Opcode },
5457     { Bad_Opcode },
5458     { VEX_W_TABLE (VEX_W_0FDA_P_2) },
5459   },
5460
5461   /* PREFIX_VEX_0FDB */
5462   {
5463     { Bad_Opcode },
5464     { Bad_Opcode },
5465     { VEX_W_TABLE (VEX_W_0FDB_P_2) },
5466   },
5467
5468   /* PREFIX_VEX_0FDC */
5469   {
5470     { Bad_Opcode },
5471     { Bad_Opcode },
5472     { VEX_W_TABLE (VEX_W_0FDC_P_2) },
5473   },
5474
5475   /* PREFIX_VEX_0FDD */
5476   {
5477     { Bad_Opcode },
5478     { Bad_Opcode },
5479     { VEX_W_TABLE (VEX_W_0FDD_P_2) },
5480   },
5481
5482   /* PREFIX_VEX_0FDE */
5483   {
5484     { Bad_Opcode },
5485     { Bad_Opcode },
5486     { VEX_W_TABLE (VEX_W_0FDE_P_2) },
5487   },
5488
5489   /* PREFIX_VEX_0FDF */
5490   {
5491     { Bad_Opcode },
5492     { Bad_Opcode },
5493     { VEX_W_TABLE (VEX_W_0FDF_P_2) },
5494   },
5495
5496   /* PREFIX_VEX_0FE0 */
5497   {
5498     { Bad_Opcode },
5499     { Bad_Opcode },
5500     { VEX_W_TABLE (VEX_W_0FE0_P_2) },
5501   },
5502
5503   /* PREFIX_VEX_0FE1 */
5504   {
5505     { Bad_Opcode },
5506     { Bad_Opcode },
5507     { VEX_W_TABLE (VEX_W_0FE1_P_2) },
5508   },
5509
5510   /* PREFIX_VEX_0FE2 */
5511   {
5512     { Bad_Opcode },
5513     { Bad_Opcode },
5514     { VEX_W_TABLE (VEX_W_0FE2_P_2) },
5515   },
5516
5517   /* PREFIX_VEX_0FE3 */
5518   {
5519     { Bad_Opcode },
5520     { Bad_Opcode },
5521     { VEX_W_TABLE (VEX_W_0FE3_P_2) },
5522   },
5523
5524   /* PREFIX_VEX_0FE4 */
5525   {
5526     { Bad_Opcode },
5527     { Bad_Opcode },
5528     { VEX_W_TABLE (VEX_W_0FE4_P_2) },
5529   },
5530
5531   /* PREFIX_VEX_0FE5 */
5532   {
5533     { Bad_Opcode },
5534     { Bad_Opcode },
5535     { VEX_W_TABLE (VEX_W_0FE5_P_2) },
5536   },
5537
5538   /* PREFIX_VEX_0FE6 */
5539   {
5540     { Bad_Opcode },
5541     { VEX_W_TABLE (VEX_W_0FE6_P_1) },
5542     { VEX_W_TABLE (VEX_W_0FE6_P_2) },
5543     { VEX_W_TABLE (VEX_W_0FE6_P_3) },
5544   },
5545
5546   /* PREFIX_VEX_0FE7 */
5547   {
5548     { Bad_Opcode },
5549     { Bad_Opcode },
5550     { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5551   },
5552
5553   /* PREFIX_VEX_0FE8 */
5554   {
5555     { Bad_Opcode },
5556     { Bad_Opcode },
5557     { VEX_W_TABLE (VEX_W_0FE8_P_2) },
5558   },
5559
5560   /* PREFIX_VEX_0FE9 */
5561   {
5562     { Bad_Opcode },
5563     { Bad_Opcode },
5564     { VEX_W_TABLE (VEX_W_0FE9_P_2) },
5565   },
5566
5567   /* PREFIX_VEX_0FEA */
5568   {
5569     { Bad_Opcode },
5570     { Bad_Opcode },
5571     { VEX_W_TABLE (VEX_W_0FEA_P_2) },
5572   },
5573
5574   /* PREFIX_VEX_0FEB */
5575   {
5576     { Bad_Opcode },
5577     { Bad_Opcode },
5578     { VEX_W_TABLE (VEX_W_0FEB_P_2) },
5579   },
5580
5581   /* PREFIX_VEX_0FEC */
5582   {
5583     { Bad_Opcode },
5584     { Bad_Opcode },
5585     { VEX_W_TABLE (VEX_W_0FEC_P_2) },
5586   },
5587
5588   /* PREFIX_VEX_0FED */
5589   {
5590     { Bad_Opcode },
5591     { Bad_Opcode },
5592     { VEX_W_TABLE (VEX_W_0FED_P_2) },
5593   },
5594
5595   /* PREFIX_VEX_0FEE */
5596   {
5597     { Bad_Opcode },
5598     { Bad_Opcode },
5599     { VEX_W_TABLE (VEX_W_0FEE_P_2) },
5600   },
5601
5602   /* PREFIX_VEX_0FEF */
5603   {
5604     { Bad_Opcode },
5605     { Bad_Opcode },
5606     { VEX_W_TABLE (VEX_W_0FEF_P_2) },
5607   },
5608
5609   /* PREFIX_VEX_0FF0 */
5610   {
5611     { Bad_Opcode },
5612     { Bad_Opcode },
5613     { Bad_Opcode },
5614     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5615   },
5616
5617   /* PREFIX_VEX_0FF1 */
5618   {
5619     { Bad_Opcode },
5620     { Bad_Opcode },
5621     { VEX_W_TABLE (VEX_W_0FF1_P_2) },
5622   },
5623
5624   /* PREFIX_VEX_0FF2 */
5625   {
5626     { Bad_Opcode },
5627     { Bad_Opcode },
5628     { VEX_W_TABLE (VEX_W_0FF2_P_2) },
5629   },
5630
5631   /* PREFIX_VEX_0FF3 */
5632   {
5633     { Bad_Opcode },
5634     { Bad_Opcode },
5635     { VEX_W_TABLE (VEX_W_0FF3_P_2) },
5636   },
5637
5638   /* PREFIX_VEX_0FF4 */
5639   {
5640     { Bad_Opcode },
5641     { Bad_Opcode },
5642     { VEX_W_TABLE (VEX_W_0FF4_P_2) },
5643   },
5644
5645   /* PREFIX_VEX_0FF5 */
5646   {
5647     { Bad_Opcode },
5648     { Bad_Opcode },
5649     { VEX_W_TABLE (VEX_W_0FF5_P_2) },
5650   },
5651
5652   /* PREFIX_VEX_0FF6 */
5653   {
5654     { Bad_Opcode },
5655     { Bad_Opcode },
5656     { VEX_W_TABLE (VEX_W_0FF6_P_2) },
5657   },
5658
5659   /* PREFIX_VEX_0FF7 */
5660   {
5661     { Bad_Opcode },
5662     { Bad_Opcode },
5663     { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5664   },
5665
5666   /* PREFIX_VEX_0FF8 */
5667   {
5668     { Bad_Opcode },
5669     { Bad_Opcode },
5670     { VEX_W_TABLE (VEX_W_0FF8_P_2) },
5671   },
5672
5673   /* PREFIX_VEX_0FF9 */
5674   {
5675     { Bad_Opcode },
5676     { Bad_Opcode },
5677     { VEX_W_TABLE (VEX_W_0FF9_P_2) },
5678   },
5679
5680   /* PREFIX_VEX_0FFA */
5681   {
5682     { Bad_Opcode },
5683     { Bad_Opcode },
5684     { VEX_W_TABLE (VEX_W_0FFA_P_2) },
5685   },
5686
5687   /* PREFIX_VEX_0FFB */
5688   {
5689     { Bad_Opcode },
5690     { Bad_Opcode },
5691     { VEX_W_TABLE (VEX_W_0FFB_P_2) },
5692   },
5693
5694   /* PREFIX_VEX_0FFC */
5695   {
5696     { Bad_Opcode },
5697     { Bad_Opcode },
5698     { VEX_W_TABLE (VEX_W_0FFC_P_2) },
5699   },
5700
5701   /* PREFIX_VEX_0FFD */
5702   {
5703     { Bad_Opcode },
5704     { Bad_Opcode },
5705     { VEX_W_TABLE (VEX_W_0FFD_P_2) },
5706   },
5707
5708   /* PREFIX_VEX_0FFE */
5709   {
5710     { Bad_Opcode },
5711     { Bad_Opcode },
5712     { VEX_W_TABLE (VEX_W_0FFE_P_2) },
5713   },
5714
5715   /* PREFIX_VEX_0F3800 */
5716   {
5717     { Bad_Opcode },
5718     { Bad_Opcode },
5719     { VEX_W_TABLE (VEX_W_0F3800_P_2) },
5720   },
5721
5722   /* PREFIX_VEX_0F3801 */
5723   {
5724     { Bad_Opcode },
5725     { Bad_Opcode },
5726     { VEX_W_TABLE (VEX_W_0F3801_P_2) },
5727   },
5728
5729   /* PREFIX_VEX_0F3802 */
5730   {
5731     { Bad_Opcode },
5732     { Bad_Opcode },
5733     { VEX_W_TABLE (VEX_W_0F3802_P_2) },
5734   },
5735
5736   /* PREFIX_VEX_0F3803 */
5737   {
5738     { Bad_Opcode },
5739     { Bad_Opcode },
5740     { VEX_W_TABLE (VEX_W_0F3803_P_2) },
5741   },
5742
5743   /* PREFIX_VEX_0F3804 */
5744   {
5745     { Bad_Opcode },
5746     { Bad_Opcode },
5747     { VEX_W_TABLE (VEX_W_0F3804_P_2) },
5748   },
5749
5750   /* PREFIX_VEX_0F3805 */
5751   {
5752     { Bad_Opcode },
5753     { Bad_Opcode },
5754     { VEX_W_TABLE (VEX_W_0F3805_P_2) },
5755   },
5756
5757   /* PREFIX_VEX_0F3806 */
5758   {
5759     { Bad_Opcode },
5760     { Bad_Opcode },
5761     { VEX_W_TABLE (VEX_W_0F3806_P_2) },
5762   },
5763
5764   /* PREFIX_VEX_0F3807 */
5765   {
5766     { Bad_Opcode },
5767     { Bad_Opcode },
5768     { VEX_W_TABLE (VEX_W_0F3807_P_2) },
5769   },
5770
5771   /* PREFIX_VEX_0F3808 */
5772   {
5773     { Bad_Opcode },
5774     { Bad_Opcode },
5775     { VEX_W_TABLE (VEX_W_0F3808_P_2) },
5776   },
5777
5778   /* PREFIX_VEX_0F3809 */
5779   {
5780     { Bad_Opcode },
5781     { Bad_Opcode },
5782     { VEX_W_TABLE (VEX_W_0F3809_P_2) },
5783   },
5784
5785   /* PREFIX_VEX_0F380A */
5786   {
5787     { Bad_Opcode },
5788     { Bad_Opcode },
5789     { VEX_W_TABLE (VEX_W_0F380A_P_2) },
5790   },
5791
5792   /* PREFIX_VEX_0F380B */
5793   {
5794     { Bad_Opcode },
5795     { Bad_Opcode },
5796     { VEX_W_TABLE (VEX_W_0F380B_P_2) },
5797   },
5798
5799   /* PREFIX_VEX_0F380C */
5800   {
5801     { Bad_Opcode },
5802     { Bad_Opcode },
5803     { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5804   },
5805
5806   /* PREFIX_VEX_0F380D */
5807   {
5808     { Bad_Opcode },
5809     { Bad_Opcode },
5810     { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5811   },
5812
5813   /* PREFIX_VEX_0F380E */
5814   {
5815     { Bad_Opcode },
5816     { Bad_Opcode },
5817     { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5818   },
5819
5820   /* PREFIX_VEX_0F380F */
5821   {
5822     { Bad_Opcode },
5823     { Bad_Opcode },
5824     { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5825   },
5826
5827   /* PREFIX_VEX_0F3813 */
5828   {
5829     { Bad_Opcode },
5830     { Bad_Opcode },
5831     { "vcvtph2ps", { XM, EXxmmq }, 0 },
5832   },
5833
5834   /* PREFIX_VEX_0F3816 */
5835   {
5836     { Bad_Opcode },
5837     { Bad_Opcode },
5838     { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5839   },
5840
5841   /* PREFIX_VEX_0F3817 */
5842   {
5843     { Bad_Opcode },
5844     { Bad_Opcode },
5845     { VEX_W_TABLE (VEX_W_0F3817_P_2) },
5846   },
5847
5848   /* PREFIX_VEX_0F3818 */
5849   {
5850     { Bad_Opcode },
5851     { Bad_Opcode },
5852     { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5853   },
5854
5855   /* PREFIX_VEX_0F3819 */
5856   {
5857     { Bad_Opcode },
5858     { Bad_Opcode },
5859     { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5860   },
5861
5862   /* PREFIX_VEX_0F381A */
5863   {
5864     { Bad_Opcode },
5865     { Bad_Opcode },
5866     { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5867   },
5868
5869   /* PREFIX_VEX_0F381C */
5870   {
5871     { Bad_Opcode },
5872     { Bad_Opcode },
5873     { VEX_W_TABLE (VEX_W_0F381C_P_2) },
5874   },
5875
5876   /* PREFIX_VEX_0F381D */
5877   {
5878     { Bad_Opcode },
5879     { Bad_Opcode },
5880     { VEX_W_TABLE (VEX_W_0F381D_P_2) },
5881   },
5882
5883   /* PREFIX_VEX_0F381E */
5884   {
5885     { Bad_Opcode },
5886     { Bad_Opcode },
5887     { VEX_W_TABLE (VEX_W_0F381E_P_2) },
5888   },
5889
5890   /* PREFIX_VEX_0F3820 */
5891   {
5892     { Bad_Opcode },
5893     { Bad_Opcode },
5894     { VEX_W_TABLE (VEX_W_0F3820_P_2) },
5895   },
5896
5897   /* PREFIX_VEX_0F3821 */
5898   {
5899     { Bad_Opcode },
5900     { Bad_Opcode },
5901     { VEX_W_TABLE (VEX_W_0F3821_P_2) },
5902   },
5903
5904   /* PREFIX_VEX_0F3822 */
5905   {
5906     { Bad_Opcode },
5907     { Bad_Opcode },
5908     { VEX_W_TABLE (VEX_W_0F3822_P_2) },
5909   },
5910
5911   /* PREFIX_VEX_0F3823 */
5912   {
5913     { Bad_Opcode },
5914     { Bad_Opcode },
5915     { VEX_W_TABLE (VEX_W_0F3823_P_2) },
5916   },
5917
5918   /* PREFIX_VEX_0F3824 */
5919   {
5920     { Bad_Opcode },
5921     { Bad_Opcode },
5922     { VEX_W_TABLE (VEX_W_0F3824_P_2) },
5923   },
5924
5925   /* PREFIX_VEX_0F3825 */
5926   {
5927     { Bad_Opcode },
5928     { Bad_Opcode },
5929     { VEX_W_TABLE (VEX_W_0F3825_P_2) },
5930   },
5931
5932   /* PREFIX_VEX_0F3828 */
5933   {
5934     { Bad_Opcode },
5935     { Bad_Opcode },
5936     { VEX_W_TABLE (VEX_W_0F3828_P_2) },
5937   },
5938
5939   /* PREFIX_VEX_0F3829 */
5940   {
5941     { Bad_Opcode },
5942     { Bad_Opcode },
5943     { VEX_W_TABLE (VEX_W_0F3829_P_2) },
5944   },
5945
5946   /* PREFIX_VEX_0F382A */
5947   {
5948     { Bad_Opcode },
5949     { Bad_Opcode },
5950     { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5951   },
5952
5953   /* PREFIX_VEX_0F382B */
5954   {
5955     { Bad_Opcode },
5956     { Bad_Opcode },
5957     { VEX_W_TABLE (VEX_W_0F382B_P_2) },
5958   },
5959
5960   /* PREFIX_VEX_0F382C */
5961   {
5962     { Bad_Opcode },
5963     { Bad_Opcode },
5964      { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5965   },
5966
5967   /* PREFIX_VEX_0F382D */
5968   {
5969     { Bad_Opcode },
5970     { Bad_Opcode },
5971      { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5972   },
5973
5974   /* PREFIX_VEX_0F382E */
5975   {
5976     { Bad_Opcode },
5977     { Bad_Opcode },
5978      { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5979   },
5980
5981   /* PREFIX_VEX_0F382F */
5982   {
5983     { Bad_Opcode },
5984     { Bad_Opcode },
5985      { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5986   },
5987
5988   /* PREFIX_VEX_0F3830 */
5989   {
5990     { Bad_Opcode },
5991     { Bad_Opcode },
5992     { VEX_W_TABLE (VEX_W_0F3830_P_2) },
5993   },
5994
5995   /* PREFIX_VEX_0F3831 */
5996   {
5997     { Bad_Opcode },
5998     { Bad_Opcode },
5999     { VEX_W_TABLE (VEX_W_0F3831_P_2) },
6000   },
6001
6002   /* PREFIX_VEX_0F3832 */
6003   {
6004     { Bad_Opcode },
6005     { Bad_Opcode },
6006     { VEX_W_TABLE (VEX_W_0F3832_P_2) },
6007   },
6008
6009   /* PREFIX_VEX_0F3833 */
6010   {
6011     { Bad_Opcode },
6012     { Bad_Opcode },
6013     { VEX_W_TABLE (VEX_W_0F3833_P_2) },
6014   },
6015
6016   /* PREFIX_VEX_0F3834 */
6017   {
6018     { Bad_Opcode },
6019     { Bad_Opcode },
6020     { VEX_W_TABLE (VEX_W_0F3834_P_2) },
6021   },
6022
6023   /* PREFIX_VEX_0F3835 */
6024   {
6025     { Bad_Opcode },
6026     { Bad_Opcode },
6027     { VEX_W_TABLE (VEX_W_0F3835_P_2) },
6028   },
6029
6030   /* PREFIX_VEX_0F3836 */
6031   {
6032     { Bad_Opcode },
6033     { Bad_Opcode },
6034     { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
6035   },
6036
6037   /* PREFIX_VEX_0F3837 */
6038   {
6039     { Bad_Opcode },
6040     { Bad_Opcode },
6041     { VEX_W_TABLE (VEX_W_0F3837_P_2) },
6042   },
6043
6044   /* PREFIX_VEX_0F3838 */
6045   {
6046     { Bad_Opcode },
6047     { Bad_Opcode },
6048     { VEX_W_TABLE (VEX_W_0F3838_P_2) },
6049   },
6050
6051   /* PREFIX_VEX_0F3839 */
6052   {
6053     { Bad_Opcode },
6054     { Bad_Opcode },
6055     { VEX_W_TABLE (VEX_W_0F3839_P_2) },
6056   },
6057
6058   /* PREFIX_VEX_0F383A */
6059   {
6060     { Bad_Opcode },
6061     { Bad_Opcode },
6062     { VEX_W_TABLE (VEX_W_0F383A_P_2) },
6063   },
6064
6065   /* PREFIX_VEX_0F383B */
6066   {
6067     { Bad_Opcode },
6068     { Bad_Opcode },
6069     { VEX_W_TABLE (VEX_W_0F383B_P_2) },
6070   },
6071
6072   /* PREFIX_VEX_0F383C */
6073   {
6074     { Bad_Opcode },
6075     { Bad_Opcode },
6076     { VEX_W_TABLE (VEX_W_0F383C_P_2) },
6077   },
6078
6079   /* PREFIX_VEX_0F383D */
6080   {
6081     { Bad_Opcode },
6082     { Bad_Opcode },
6083     { VEX_W_TABLE (VEX_W_0F383D_P_2) },
6084   },
6085
6086   /* PREFIX_VEX_0F383E */
6087   {
6088     { Bad_Opcode },
6089     { Bad_Opcode },
6090     { VEX_W_TABLE (VEX_W_0F383E_P_2) },
6091   },
6092
6093   /* PREFIX_VEX_0F383F */
6094   {
6095     { Bad_Opcode },
6096     { Bad_Opcode },
6097     { VEX_W_TABLE (VEX_W_0F383F_P_2) },
6098   },
6099
6100   /* PREFIX_VEX_0F3840 */
6101   {
6102     { Bad_Opcode },
6103     { Bad_Opcode },
6104     { VEX_W_TABLE (VEX_W_0F3840_P_2) },
6105   },
6106
6107   /* PREFIX_VEX_0F3841 */
6108   {
6109     { Bad_Opcode },
6110     { Bad_Opcode },
6111     { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
6112   },
6113
6114   /* PREFIX_VEX_0F3845 */
6115   {
6116     { Bad_Opcode },
6117     { Bad_Opcode },
6118     { "vpsrlv%LW", { XM, Vex, EXx }, 0 },
6119   },
6120
6121   /* PREFIX_VEX_0F3846 */
6122   {
6123     { Bad_Opcode },
6124     { Bad_Opcode },
6125     { VEX_W_TABLE (VEX_W_0F3846_P_2) },
6126   },
6127
6128   /* PREFIX_VEX_0F3847 */
6129   {
6130     { Bad_Opcode },
6131     { Bad_Opcode },
6132     { "vpsllv%LW", { XM, Vex, EXx }, 0 },
6133   },
6134
6135   /* PREFIX_VEX_0F3858 */
6136   {
6137     { Bad_Opcode },
6138     { Bad_Opcode },
6139     { VEX_W_TABLE (VEX_W_0F3858_P_2) },
6140   },
6141
6142   /* PREFIX_VEX_0F3859 */
6143   {
6144     { Bad_Opcode },
6145     { Bad_Opcode },
6146     { VEX_W_TABLE (VEX_W_0F3859_P_2) },
6147   },
6148
6149   /* PREFIX_VEX_0F385A */
6150   {
6151     { Bad_Opcode },
6152     { Bad_Opcode },
6153     { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
6154   },
6155
6156   /* PREFIX_VEX_0F3878 */
6157   {
6158     { Bad_Opcode },
6159     { Bad_Opcode },
6160     { VEX_W_TABLE (VEX_W_0F3878_P_2) },
6161   },
6162
6163   /* PREFIX_VEX_0F3879 */
6164   {
6165     { Bad_Opcode },
6166     { Bad_Opcode },
6167     { VEX_W_TABLE (VEX_W_0F3879_P_2) },
6168   },
6169
6170   /* PREFIX_VEX_0F388C */
6171   {
6172     { Bad_Opcode },
6173     { Bad_Opcode },
6174     { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
6175   },
6176
6177   /* PREFIX_VEX_0F388E */
6178   {
6179     { Bad_Opcode },
6180     { Bad_Opcode },
6181     { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
6182   },
6183
6184   /* PREFIX_VEX_0F3890 */
6185   {
6186     { Bad_Opcode },
6187     { Bad_Opcode },
6188     { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 },
6189   },
6190
6191   /* PREFIX_VEX_0F3891 */
6192   {
6193     { Bad_Opcode },
6194     { Bad_Opcode },
6195     { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6196   },
6197
6198   /* PREFIX_VEX_0F3892 */
6199   {
6200     { Bad_Opcode },
6201     { Bad_Opcode },
6202     { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 },
6203   },
6204
6205   /* PREFIX_VEX_0F3893 */
6206   {
6207     { Bad_Opcode },
6208     { Bad_Opcode },
6209     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6210   },
6211
6212   /* PREFIX_VEX_0F3896 */
6213   {
6214     { Bad_Opcode },
6215     { Bad_Opcode },
6216     { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 },
6217   },
6218
6219   /* PREFIX_VEX_0F3897 */
6220   {
6221     { Bad_Opcode },
6222     { Bad_Opcode },
6223     { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 },
6224   },
6225
6226   /* PREFIX_VEX_0F3898 */
6227   {
6228     { Bad_Opcode },
6229     { Bad_Opcode },
6230     { "vfmadd132p%XW", { XM, Vex, EXx }, 0 },
6231   },
6232
6233   /* PREFIX_VEX_0F3899 */
6234   {
6235     { Bad_Opcode },
6236     { Bad_Opcode },
6237     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6238   },
6239
6240   /* PREFIX_VEX_0F389A */
6241   {
6242     { Bad_Opcode },
6243     { Bad_Opcode },
6244     { "vfmsub132p%XW", { XM, Vex, EXx }, 0 },
6245   },
6246
6247   /* PREFIX_VEX_0F389B */
6248   {
6249     { Bad_Opcode },
6250     { Bad_Opcode },
6251     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6252   },
6253
6254   /* PREFIX_VEX_0F389C */
6255   {
6256     { Bad_Opcode },
6257     { Bad_Opcode },
6258     { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 },
6259   },
6260
6261   /* PREFIX_VEX_0F389D */
6262   {
6263     { Bad_Opcode },
6264     { Bad_Opcode },
6265     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6266   },
6267
6268   /* PREFIX_VEX_0F389E */
6269   {
6270     { Bad_Opcode },
6271     { Bad_Opcode },
6272     { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 },
6273   },
6274
6275   /* PREFIX_VEX_0F389F */
6276   {
6277     { Bad_Opcode },
6278     { Bad_Opcode },
6279     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6280   },
6281
6282   /* PREFIX_VEX_0F38A6 */
6283   {
6284     { Bad_Opcode },
6285     { Bad_Opcode },
6286     { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 },
6287     { Bad_Opcode },
6288   },
6289
6290   /* PREFIX_VEX_0F38A7 */
6291   {
6292     { Bad_Opcode },
6293     { Bad_Opcode },
6294     { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 },
6295   },
6296
6297   /* PREFIX_VEX_0F38A8 */
6298   {
6299     { Bad_Opcode },
6300     { Bad_Opcode },
6301     { "vfmadd213p%XW", { XM, Vex, EXx }, 0 },
6302   },
6303
6304   /* PREFIX_VEX_0F38A9 */
6305   {
6306     { Bad_Opcode },
6307     { Bad_Opcode },
6308     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6309   },
6310
6311   /* PREFIX_VEX_0F38AA */
6312   {
6313     { Bad_Opcode },
6314     { Bad_Opcode },
6315     { "vfmsub213p%XW", { XM, Vex, EXx }, 0 },
6316   },
6317
6318   /* PREFIX_VEX_0F38AB */
6319   {
6320     { Bad_Opcode },
6321     { Bad_Opcode },
6322     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6323   },
6324
6325   /* PREFIX_VEX_0F38AC */
6326   {
6327     { Bad_Opcode },
6328     { Bad_Opcode },
6329     { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 },
6330   },
6331
6332   /* PREFIX_VEX_0F38AD */
6333   {
6334     { Bad_Opcode },
6335     { Bad_Opcode },
6336     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6337   },
6338
6339   /* PREFIX_VEX_0F38AE */
6340   {
6341     { Bad_Opcode },
6342     { Bad_Opcode },
6343     { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 },
6344   },
6345
6346   /* PREFIX_VEX_0F38AF */
6347   {
6348     { Bad_Opcode },
6349     { Bad_Opcode },
6350     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6351   },
6352
6353   /* PREFIX_VEX_0F38B6 */
6354   {
6355     { Bad_Opcode },
6356     { Bad_Opcode },
6357     { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 },
6358   },
6359
6360   /* PREFIX_VEX_0F38B7 */
6361   {
6362     { Bad_Opcode },
6363     { Bad_Opcode },
6364     { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 },
6365   },
6366
6367   /* PREFIX_VEX_0F38B8 */
6368   {
6369     { Bad_Opcode },
6370     { Bad_Opcode },
6371     { "vfmadd231p%XW", { XM, Vex, EXx }, 0 },
6372   },
6373
6374   /* PREFIX_VEX_0F38B9 */
6375   {
6376     { Bad_Opcode },
6377     { Bad_Opcode },
6378     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6379   },
6380
6381   /* PREFIX_VEX_0F38BA */
6382   {
6383     { Bad_Opcode },
6384     { Bad_Opcode },
6385     { "vfmsub231p%XW", { XM, Vex, EXx }, 0 },
6386   },
6387
6388   /* PREFIX_VEX_0F38BB */
6389   {
6390     { Bad_Opcode },
6391     { Bad_Opcode },
6392     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6393   },
6394
6395   /* PREFIX_VEX_0F38BC */
6396   {
6397     { Bad_Opcode },
6398     { Bad_Opcode },
6399     { "vfnmadd231p%XW", { XM, Vex, EXx }, 0 },
6400   },
6401
6402   /* PREFIX_VEX_0F38BD */
6403   {
6404     { Bad_Opcode },
6405     { Bad_Opcode },
6406     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6407   },
6408
6409   /* PREFIX_VEX_0F38BE */
6410   {
6411     { Bad_Opcode },
6412     { Bad_Opcode },
6413     { "vfnmsub231p%XW", { XM, Vex, EXx }, 0 },
6414   },
6415
6416   /* PREFIX_VEX_0F38BF */
6417   {
6418     { Bad_Opcode },
6419     { Bad_Opcode },
6420     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6421   },
6422
6423   /* PREFIX_VEX_0F38CF */
6424   {
6425     { Bad_Opcode },
6426     { Bad_Opcode },
6427     { VEX_W_TABLE (VEX_W_0F38CF_P_2) },
6428   },
6429
6430   /* PREFIX_VEX_0F38DB */
6431   {
6432     { Bad_Opcode },
6433     { Bad_Opcode },
6434     { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6435   },
6436
6437   /* PREFIX_VEX_0F38DC */
6438   {
6439     { Bad_Opcode },
6440     { Bad_Opcode },
6441     { "vaesenc",        { XM, Vex, EXx }, 0 },
6442   },
6443
6444   /* PREFIX_VEX_0F38DD */
6445   {
6446     { Bad_Opcode },
6447     { Bad_Opcode },
6448     { "vaesenclast",    { XM, Vex, EXx }, 0 },
6449   },
6450
6451   /* PREFIX_VEX_0F38DE */
6452   {
6453     { Bad_Opcode },
6454     { Bad_Opcode },
6455     { "vaesdec",        { XM, Vex, EXx }, 0 },
6456   },
6457
6458   /* PREFIX_VEX_0F38DF */
6459   {
6460     { Bad_Opcode },
6461     { Bad_Opcode },
6462     { "vaesdeclast",    { XM, Vex, EXx }, 0 },
6463   },
6464
6465   /* PREFIX_VEX_0F38F2 */
6466   {
6467     { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6468   },
6469
6470   /* PREFIX_VEX_0F38F3_REG_1 */
6471   {
6472     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6473   },
6474
6475   /* PREFIX_VEX_0F38F3_REG_2 */
6476   {
6477     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6478   },
6479
6480   /* PREFIX_VEX_0F38F3_REG_3 */
6481   {
6482     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6483   },
6484
6485   /* PREFIX_VEX_0F38F5 */
6486   {
6487     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6488     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6489     { Bad_Opcode },
6490     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6491   },
6492
6493   /* PREFIX_VEX_0F38F6 */
6494   {
6495     { Bad_Opcode },
6496     { Bad_Opcode },
6497     { Bad_Opcode },
6498     { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6499   },
6500
6501   /* PREFIX_VEX_0F38F7 */
6502   {
6503     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6504     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6505     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6506     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6507   },
6508
6509   /* PREFIX_VEX_0F3A00 */
6510   {
6511     { Bad_Opcode },
6512     { Bad_Opcode },
6513     { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6514   },
6515
6516   /* PREFIX_VEX_0F3A01 */
6517   {
6518     { Bad_Opcode },
6519     { Bad_Opcode },
6520     { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6521   },
6522
6523   /* PREFIX_VEX_0F3A02 */
6524   {
6525     { Bad_Opcode },
6526     { Bad_Opcode },
6527     { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6528   },
6529
6530   /* PREFIX_VEX_0F3A04 */
6531   {
6532     { Bad_Opcode },
6533     { Bad_Opcode },
6534     { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6535   },
6536
6537   /* PREFIX_VEX_0F3A05 */
6538   {
6539     { Bad_Opcode },
6540     { Bad_Opcode },
6541     { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6542   },
6543
6544   /* PREFIX_VEX_0F3A06 */
6545   {
6546     { Bad_Opcode },
6547     { Bad_Opcode },
6548     { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6549   },
6550
6551   /* PREFIX_VEX_0F3A08 */
6552   {
6553     { Bad_Opcode },
6554     { Bad_Opcode },
6555     { VEX_W_TABLE (VEX_W_0F3A08_P_2) },
6556   },
6557
6558   /* PREFIX_VEX_0F3A09 */
6559   {
6560     { Bad_Opcode },
6561     { Bad_Opcode },
6562     { VEX_W_TABLE (VEX_W_0F3A09_P_2) },
6563   },
6564
6565   /* PREFIX_VEX_0F3A0A */
6566   {
6567     { Bad_Opcode },
6568     { Bad_Opcode },
6569     { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) },
6570   },
6571
6572   /* PREFIX_VEX_0F3A0B */
6573   {
6574     { Bad_Opcode },
6575     { Bad_Opcode },
6576     { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) },
6577   },
6578
6579   /* PREFIX_VEX_0F3A0C */
6580   {
6581     { Bad_Opcode },
6582     { Bad_Opcode },
6583     { VEX_W_TABLE (VEX_W_0F3A0C_P_2) },
6584   },
6585
6586   /* PREFIX_VEX_0F3A0D */
6587   {
6588     { Bad_Opcode },
6589     { Bad_Opcode },
6590     { VEX_W_TABLE (VEX_W_0F3A0D_P_2) },
6591   },
6592
6593   /* PREFIX_VEX_0F3A0E */
6594   {
6595     { Bad_Opcode },
6596     { Bad_Opcode },
6597     { VEX_W_TABLE (VEX_W_0F3A0E_P_2) },
6598   },
6599
6600   /* PREFIX_VEX_0F3A0F */
6601   {
6602     { Bad_Opcode },
6603     { Bad_Opcode },
6604     { VEX_W_TABLE (VEX_W_0F3A0F_P_2) },
6605   },
6606
6607   /* PREFIX_VEX_0F3A14 */
6608   {
6609     { Bad_Opcode },
6610     { Bad_Opcode },
6611     { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6612   },
6613
6614   /* PREFIX_VEX_0F3A15 */
6615   {
6616     { Bad_Opcode },
6617     { Bad_Opcode },
6618     { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6619   },
6620
6621   /* PREFIX_VEX_0F3A16 */
6622   {
6623     { Bad_Opcode },
6624     { Bad_Opcode },
6625     { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6626   },
6627
6628   /* PREFIX_VEX_0F3A17 */
6629   {
6630     { Bad_Opcode },
6631     { Bad_Opcode },
6632     { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6633   },
6634
6635   /* PREFIX_VEX_0F3A18 */
6636   {
6637     { Bad_Opcode },
6638     { Bad_Opcode },
6639     { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6640   },
6641
6642   /* PREFIX_VEX_0F3A19 */
6643   {
6644     { Bad_Opcode },
6645     { Bad_Opcode },
6646     { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6647   },
6648
6649   /* PREFIX_VEX_0F3A1D */
6650   {
6651     { Bad_Opcode },
6652     { Bad_Opcode },
6653     { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 },
6654   },
6655
6656   /* PREFIX_VEX_0F3A20 */
6657   {
6658     { Bad_Opcode },
6659     { Bad_Opcode },
6660     { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6661   },
6662
6663   /* PREFIX_VEX_0F3A21 */
6664   {
6665     { Bad_Opcode },
6666     { Bad_Opcode },
6667     { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6668   },
6669
6670   /* PREFIX_VEX_0F3A22 */
6671   {
6672     { Bad_Opcode },
6673     { Bad_Opcode },
6674     { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6675   },
6676
6677   /* PREFIX_VEX_0F3A30 */
6678   {
6679     { Bad_Opcode },
6680     { Bad_Opcode },
6681     { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6682   },
6683
6684   /* PREFIX_VEX_0F3A31 */
6685   {
6686     { Bad_Opcode },
6687     { Bad_Opcode },
6688     { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6689   },
6690
6691   /* PREFIX_VEX_0F3A32 */
6692   {
6693     { Bad_Opcode },
6694     { Bad_Opcode },
6695     { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6696   },
6697
6698   /* PREFIX_VEX_0F3A33 */
6699   {
6700     { Bad_Opcode },
6701     { Bad_Opcode },
6702     { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6703   },
6704
6705   /* PREFIX_VEX_0F3A38 */
6706   {
6707     { Bad_Opcode },
6708     { Bad_Opcode },
6709     { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6710   },
6711
6712   /* PREFIX_VEX_0F3A39 */
6713   {
6714     { Bad_Opcode },
6715     { Bad_Opcode },
6716     { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6717   },
6718
6719   /* PREFIX_VEX_0F3A40 */
6720   {
6721     { Bad_Opcode },
6722     { Bad_Opcode },
6723     { VEX_W_TABLE (VEX_W_0F3A40_P_2) },
6724   },
6725
6726   /* PREFIX_VEX_0F3A41 */
6727   {
6728     { Bad_Opcode },
6729     { Bad_Opcode },
6730     { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6731   },
6732
6733   /* PREFIX_VEX_0F3A42 */
6734   {
6735     { Bad_Opcode },
6736     { Bad_Opcode },
6737     { VEX_W_TABLE (VEX_W_0F3A42_P_2) },
6738   },
6739
6740   /* PREFIX_VEX_0F3A44 */
6741   {
6742     { Bad_Opcode },
6743     { Bad_Opcode },
6744     { "vpclmulqdq",     { XM, Vex, EXx, PCLMUL }, 0 },
6745   },
6746
6747   /* PREFIX_VEX_0F3A46 */
6748   {
6749     { Bad_Opcode },
6750     { Bad_Opcode },
6751     { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6752   },
6753
6754   /* PREFIX_VEX_0F3A48 */
6755   {
6756     { Bad_Opcode },
6757     { Bad_Opcode },
6758     { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6759   },
6760
6761   /* PREFIX_VEX_0F3A49 */
6762   {
6763     { Bad_Opcode },
6764     { Bad_Opcode },
6765     { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6766   },
6767
6768   /* PREFIX_VEX_0F3A4A */
6769   {
6770     { Bad_Opcode },
6771     { Bad_Opcode },
6772     { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6773   },
6774
6775   /* PREFIX_VEX_0F3A4B */
6776   {
6777     { Bad_Opcode },
6778     { Bad_Opcode },
6779     { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6780   },
6781
6782   /* PREFIX_VEX_0F3A4C */
6783   {
6784     { Bad_Opcode },
6785     { Bad_Opcode },
6786     { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6787   },
6788
6789   /* PREFIX_VEX_0F3A5C */
6790   {
6791     { Bad_Opcode },
6792     { Bad_Opcode },
6793     { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6794   },
6795
6796   /* PREFIX_VEX_0F3A5D */
6797   {
6798     { Bad_Opcode },
6799     { Bad_Opcode },
6800     { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6801   },
6802
6803   /* PREFIX_VEX_0F3A5E */
6804   {
6805     { Bad_Opcode },
6806     { Bad_Opcode },
6807     { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6808   },
6809
6810   /* PREFIX_VEX_0F3A5F */
6811   {
6812     { Bad_Opcode },
6813     { Bad_Opcode },
6814     { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6815   },
6816
6817   /* PREFIX_VEX_0F3A60 */
6818   {
6819     { Bad_Opcode },
6820     { Bad_Opcode },
6821     { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6822     { Bad_Opcode },
6823   },
6824
6825   /* PREFIX_VEX_0F3A61 */
6826   {
6827     { Bad_Opcode },
6828     { Bad_Opcode },
6829     { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6830   },
6831
6832   /* PREFIX_VEX_0F3A62 */
6833   {
6834     { Bad_Opcode },
6835     { Bad_Opcode },
6836     { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6837   },
6838
6839   /* PREFIX_VEX_0F3A63 */
6840   {
6841     { Bad_Opcode },
6842     { Bad_Opcode },
6843     { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6844   },
6845
6846   /* PREFIX_VEX_0F3A68 */
6847   {
6848     { Bad_Opcode },
6849     { Bad_Opcode },
6850     { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6851   },
6852
6853   /* PREFIX_VEX_0F3A69 */
6854   {
6855     { Bad_Opcode },
6856     { Bad_Opcode },
6857     { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6858   },
6859
6860   /* PREFIX_VEX_0F3A6A */
6861   {
6862     { Bad_Opcode },
6863     { Bad_Opcode },
6864     { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6865   },
6866
6867   /* PREFIX_VEX_0F3A6B */
6868   {
6869     { Bad_Opcode },
6870     { Bad_Opcode },
6871     { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6872   },
6873
6874   /* PREFIX_VEX_0F3A6C */
6875   {
6876     { Bad_Opcode },
6877     { Bad_Opcode },
6878     { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6879   },
6880
6881   /* PREFIX_VEX_0F3A6D */
6882   {
6883     { Bad_Opcode },
6884     { Bad_Opcode },
6885     { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6886   },
6887
6888   /* PREFIX_VEX_0F3A6E */
6889   {
6890     { Bad_Opcode },
6891     { Bad_Opcode },
6892     { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6893   },
6894
6895   /* PREFIX_VEX_0F3A6F */
6896   {
6897     { Bad_Opcode },
6898     { Bad_Opcode },
6899     { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6900   },
6901
6902   /* PREFIX_VEX_0F3A78 */
6903   {
6904     { Bad_Opcode },
6905     { Bad_Opcode },
6906     { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6907   },
6908
6909   /* PREFIX_VEX_0F3A79 */
6910   {
6911     { Bad_Opcode },
6912     { Bad_Opcode },
6913     { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6914   },
6915
6916   /* PREFIX_VEX_0F3A7A */
6917   {
6918     { Bad_Opcode },
6919     { Bad_Opcode },
6920     { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6921   },
6922
6923   /* PREFIX_VEX_0F3A7B */
6924   {
6925     { Bad_Opcode },
6926     { Bad_Opcode },
6927     { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6928   },
6929
6930   /* PREFIX_VEX_0F3A7C */
6931   {
6932     { Bad_Opcode },
6933     { Bad_Opcode },
6934     { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6935     { Bad_Opcode },
6936   },
6937
6938   /* PREFIX_VEX_0F3A7D */
6939   {
6940     { Bad_Opcode },
6941     { Bad_Opcode },
6942     { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6943   },
6944
6945   /* PREFIX_VEX_0F3A7E */
6946   {
6947     { Bad_Opcode },
6948     { Bad_Opcode },
6949     { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6950   },
6951
6952   /* PREFIX_VEX_0F3A7F */
6953   {
6954     { Bad_Opcode },
6955     { Bad_Opcode },
6956     { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6957   },
6958
6959   /* PREFIX_VEX_0F3ACE */
6960   {
6961     { Bad_Opcode },
6962     { Bad_Opcode },
6963     { VEX_W_TABLE (VEX_W_0F3ACE_P_2) },
6964   },
6965
6966   /* PREFIX_VEX_0F3ACF */
6967   {
6968     { Bad_Opcode },
6969     { Bad_Opcode },
6970     { VEX_W_TABLE (VEX_W_0F3ACF_P_2) },
6971   },
6972
6973   /* PREFIX_VEX_0F3ADF */
6974   {
6975     { Bad_Opcode },
6976     { Bad_Opcode },
6977     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6978   },
6979
6980   /* PREFIX_VEX_0F3AF0 */
6981   {
6982     { Bad_Opcode },
6983     { Bad_Opcode },
6984     { Bad_Opcode },
6985     { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6986   },
6987
6988 #define NEED_PREFIX_TABLE
6989 #include "i386-dis-evex.h"
6990 #undef NEED_PREFIX_TABLE
6991 };
6992
6993 static const struct dis386 x86_64_table[][2] = {
6994   /* X86_64_06 */
6995   {
6996     { "pushP", { es }, 0 },
6997   },
6998
6999   /* X86_64_07 */
7000   {
7001     { "popP", { es }, 0 },
7002   },
7003
7004   /* X86_64_0D */
7005   {
7006     { "pushP", { cs }, 0 },
7007   },
7008
7009   /* X86_64_16 */
7010   {
7011     { "pushP", { ss }, 0 },
7012   },
7013
7014   /* X86_64_17 */
7015   {
7016     { "popP", { ss }, 0 },
7017   },
7018
7019   /* X86_64_1E */
7020   {
7021     { "pushP", { ds }, 0 },
7022   },
7023
7024   /* X86_64_1F */
7025   {
7026     { "popP", { ds }, 0 },
7027   },
7028
7029   /* X86_64_27 */
7030   {
7031     { "daa", { XX }, 0 },
7032   },
7033
7034   /* X86_64_2F */
7035   {
7036     { "das", { XX }, 0 },
7037   },
7038
7039   /* X86_64_37 */
7040   {
7041     { "aaa", { XX }, 0 },
7042   },
7043
7044   /* X86_64_3F */
7045   {
7046     { "aas", { XX }, 0 },
7047   },
7048
7049   /* X86_64_60 */
7050   {
7051     { "pushaP", { XX }, 0 },
7052   },
7053
7054   /* X86_64_61 */
7055   {
7056     { "popaP", { XX }, 0 },
7057   },
7058
7059   /* X86_64_62 */
7060   {
7061     { MOD_TABLE (MOD_62_32BIT) },
7062     { EVEX_TABLE (EVEX_0F) },
7063   },
7064
7065   /* X86_64_63 */
7066   {
7067     { "arpl", { Ew, Gw }, 0 },
7068     { "movs{lq|xd}", { Gv, Ed }, 0 },
7069   },
7070
7071   /* X86_64_6D */
7072   {
7073     { "ins{R|}", { Yzr, indirDX }, 0 },
7074     { "ins{G|}", { Yzr, indirDX }, 0 },
7075   },
7076
7077   /* X86_64_6F */
7078   {
7079     { "outs{R|}", { indirDXr, Xz }, 0 },
7080     { "outs{G|}", { indirDXr, Xz }, 0 },
7081   },
7082
7083   /* X86_64_82 */
7084   {
7085     /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode.  */
7086     { REG_TABLE (REG_80) },
7087   },
7088
7089   /* X86_64_9A */
7090   {
7091     { "Jcall{T|}", { Ap }, 0 },
7092   },
7093
7094   /* X86_64_C4 */
7095   {
7096     { MOD_TABLE (MOD_C4_32BIT) },
7097     { VEX_C4_TABLE (VEX_0F) },
7098   },
7099
7100   /* X86_64_C5 */
7101   {
7102     { MOD_TABLE (MOD_C5_32BIT) },
7103     { VEX_C5_TABLE (VEX_0F) },
7104   },
7105
7106   /* X86_64_CE */
7107   {
7108     { "into", { XX }, 0 },
7109   },
7110
7111   /* X86_64_D4 */
7112   {
7113     { "aam", { Ib }, 0 },
7114   },
7115
7116   /* X86_64_D5 */
7117   {
7118     { "aad", { Ib }, 0 },
7119   },
7120
7121   /* X86_64_E8 */
7122   {
7123     { "callP",          { Jv, BND }, 0 },
7124     { "call@",          { Jv, BND }, 0 }
7125   },
7126
7127   /* X86_64_E9 */
7128   {
7129     { "jmpP",           { Jv, BND }, 0 },
7130     { "jmp@",           { Jv, BND }, 0 }
7131   },
7132
7133   /* X86_64_EA */
7134   {
7135     { "Jjmp{T|}", { Ap }, 0 },
7136   },
7137
7138   /* X86_64_0F01_REG_0 */
7139   {
7140     { "sgdt{Q|IQ}", { M }, 0 },
7141     { "sgdt", { M }, 0 },
7142   },
7143
7144   /* X86_64_0F01_REG_1 */
7145   {
7146     { "sidt{Q|IQ}", { M }, 0 },
7147     { "sidt", { M }, 0 },
7148   },
7149
7150   /* X86_64_0F01_REG_2 */
7151   {
7152     { "lgdt{Q|Q}", { M }, 0 },
7153     { "lgdt", { M }, 0 },
7154   },
7155
7156   /* X86_64_0F01_REG_3 */
7157   {
7158     { "lidt{Q|Q}", { M }, 0 },
7159     { "lidt", { M }, 0 },
7160   },
7161 };
7162
7163 static const struct dis386 three_byte_table[][256] = {
7164
7165   /* THREE_BYTE_0F38 */
7166   {
7167     /* 00 */
7168     { "pshufb",         { MX, EM }, PREFIX_OPCODE },
7169     { "phaddw",         { MX, EM }, PREFIX_OPCODE },
7170     { "phaddd",         { MX, EM }, PREFIX_OPCODE },
7171     { "phaddsw",        { MX, EM }, PREFIX_OPCODE },
7172     { "pmaddubsw",      { MX, EM }, PREFIX_OPCODE },
7173     { "phsubw",         { MX, EM }, PREFIX_OPCODE },
7174     { "phsubd",         { MX, EM }, PREFIX_OPCODE },
7175     { "phsubsw",        { MX, EM }, PREFIX_OPCODE },
7176     /* 08 */
7177     { "psignb",         { MX, EM }, PREFIX_OPCODE },
7178     { "psignw",         { MX, EM }, PREFIX_OPCODE },
7179     { "psignd",         { MX, EM }, PREFIX_OPCODE },
7180     { "pmulhrsw",       { MX, EM }, PREFIX_OPCODE },
7181     { Bad_Opcode },
7182     { Bad_Opcode },
7183     { Bad_Opcode },
7184     { Bad_Opcode },
7185     /* 10 */
7186     { PREFIX_TABLE (PREFIX_0F3810) },
7187     { Bad_Opcode },
7188     { Bad_Opcode },
7189     { Bad_Opcode },
7190     { PREFIX_TABLE (PREFIX_0F3814) },
7191     { PREFIX_TABLE (PREFIX_0F3815) },
7192     { Bad_Opcode },
7193     { PREFIX_TABLE (PREFIX_0F3817) },
7194     /* 18 */
7195     { Bad_Opcode },
7196     { Bad_Opcode },
7197     { Bad_Opcode },
7198     { Bad_Opcode },
7199     { "pabsb",          { MX, EM }, PREFIX_OPCODE },
7200     { "pabsw",          { MX, EM }, PREFIX_OPCODE },
7201     { "pabsd",          { MX, EM }, PREFIX_OPCODE },
7202     { Bad_Opcode },
7203     /* 20 */
7204     { PREFIX_TABLE (PREFIX_0F3820) },
7205     { PREFIX_TABLE (PREFIX_0F3821) },
7206     { PREFIX_TABLE (PREFIX_0F3822) },
7207     { PREFIX_TABLE (PREFIX_0F3823) },
7208     { PREFIX_TABLE (PREFIX_0F3824) },
7209     { PREFIX_TABLE (PREFIX_0F3825) },
7210     { Bad_Opcode },
7211     { Bad_Opcode },
7212     /* 28 */
7213     { PREFIX_TABLE (PREFIX_0F3828) },
7214     { PREFIX_TABLE (PREFIX_0F3829) },
7215     { PREFIX_TABLE (PREFIX_0F382A) },
7216     { PREFIX_TABLE (PREFIX_0F382B) },
7217     { Bad_Opcode },
7218     { Bad_Opcode },
7219     { Bad_Opcode },
7220     { Bad_Opcode },
7221     /* 30 */
7222     { PREFIX_TABLE (PREFIX_0F3830) },
7223     { PREFIX_TABLE (PREFIX_0F3831) },
7224     { PREFIX_TABLE (PREFIX_0F3832) },
7225     { PREFIX_TABLE (PREFIX_0F3833) },
7226     { PREFIX_TABLE (PREFIX_0F3834) },
7227     { PREFIX_TABLE (PREFIX_0F3835) },
7228     { Bad_Opcode },
7229     { PREFIX_TABLE (PREFIX_0F3837) },
7230     /* 38 */
7231     { PREFIX_TABLE (PREFIX_0F3838) },
7232     { PREFIX_TABLE (PREFIX_0F3839) },
7233     { PREFIX_TABLE (PREFIX_0F383A) },
7234     { PREFIX_TABLE (PREFIX_0F383B) },
7235     { PREFIX_TABLE (PREFIX_0F383C) },
7236     { PREFIX_TABLE (PREFIX_0F383D) },
7237     { PREFIX_TABLE (PREFIX_0F383E) },
7238     { PREFIX_TABLE (PREFIX_0F383F) },
7239     /* 40 */
7240     { PREFIX_TABLE (PREFIX_0F3840) },
7241     { PREFIX_TABLE (PREFIX_0F3841) },
7242     { Bad_Opcode },
7243     { Bad_Opcode },
7244     { Bad_Opcode },
7245     { Bad_Opcode },
7246     { Bad_Opcode },
7247     { Bad_Opcode },
7248     /* 48 */
7249     { Bad_Opcode },
7250     { Bad_Opcode },
7251     { Bad_Opcode },
7252     { Bad_Opcode },
7253     { Bad_Opcode },
7254     { Bad_Opcode },
7255     { Bad_Opcode },
7256     { Bad_Opcode },
7257     /* 50 */
7258     { Bad_Opcode },
7259     { Bad_Opcode },
7260     { Bad_Opcode },
7261     { Bad_Opcode },
7262     { Bad_Opcode },
7263     { Bad_Opcode },
7264     { Bad_Opcode },
7265     { Bad_Opcode },
7266     /* 58 */
7267     { Bad_Opcode },
7268     { Bad_Opcode },
7269     { Bad_Opcode },
7270     { Bad_Opcode },
7271     { Bad_Opcode },
7272     { Bad_Opcode },
7273     { Bad_Opcode },
7274     { Bad_Opcode },
7275     /* 60 */
7276     { Bad_Opcode },
7277     { Bad_Opcode },
7278     { Bad_Opcode },
7279     { Bad_Opcode },
7280     { Bad_Opcode },
7281     { Bad_Opcode },
7282     { Bad_Opcode },
7283     { Bad_Opcode },
7284     /* 68 */
7285     { Bad_Opcode },
7286     { Bad_Opcode },
7287     { Bad_Opcode },
7288     { Bad_Opcode },
7289     { Bad_Opcode },
7290     { Bad_Opcode },
7291     { Bad_Opcode },
7292     { Bad_Opcode },
7293     /* 70 */
7294     { Bad_Opcode },
7295     { Bad_Opcode },
7296     { Bad_Opcode },
7297     { Bad_Opcode },
7298     { Bad_Opcode },
7299     { Bad_Opcode },
7300     { Bad_Opcode },
7301     { Bad_Opcode },
7302     /* 78 */
7303     { Bad_Opcode },
7304     { Bad_Opcode },
7305     { Bad_Opcode },
7306     { Bad_Opcode },
7307     { Bad_Opcode },
7308     { Bad_Opcode },
7309     { Bad_Opcode },
7310     { Bad_Opcode },
7311     /* 80 */
7312     { PREFIX_TABLE (PREFIX_0F3880) },
7313     { PREFIX_TABLE (PREFIX_0F3881) },
7314     { PREFIX_TABLE (PREFIX_0F3882) },
7315     { Bad_Opcode },
7316     { Bad_Opcode },
7317     { Bad_Opcode },
7318     { Bad_Opcode },
7319     { Bad_Opcode },
7320     /* 88 */
7321     { Bad_Opcode },
7322     { Bad_Opcode },
7323     { Bad_Opcode },
7324     { Bad_Opcode },
7325     { Bad_Opcode },
7326     { Bad_Opcode },
7327     { Bad_Opcode },
7328     { Bad_Opcode },
7329     /* 90 */
7330     { Bad_Opcode },
7331     { Bad_Opcode },
7332     { Bad_Opcode },
7333     { Bad_Opcode },
7334     { Bad_Opcode },
7335     { Bad_Opcode },
7336     { Bad_Opcode },
7337     { Bad_Opcode },
7338     /* 98 */
7339     { Bad_Opcode },
7340     { Bad_Opcode },
7341     { Bad_Opcode },
7342     { Bad_Opcode },
7343     { Bad_Opcode },
7344     { Bad_Opcode },
7345     { Bad_Opcode },
7346     { Bad_Opcode },
7347     /* a0 */
7348     { Bad_Opcode },
7349     { Bad_Opcode },
7350     { Bad_Opcode },
7351     { Bad_Opcode },
7352     { Bad_Opcode },
7353     { Bad_Opcode },
7354     { Bad_Opcode },
7355     { Bad_Opcode },
7356     /* a8 */
7357     { Bad_Opcode },
7358     { Bad_Opcode },
7359     { Bad_Opcode },
7360     { Bad_Opcode },
7361     { Bad_Opcode },
7362     { Bad_Opcode },
7363     { Bad_Opcode },
7364     { Bad_Opcode },
7365     /* b0 */
7366     { Bad_Opcode },
7367     { Bad_Opcode },
7368     { Bad_Opcode },
7369     { Bad_Opcode },
7370     { Bad_Opcode },
7371     { Bad_Opcode },
7372     { Bad_Opcode },
7373     { Bad_Opcode },
7374     /* b8 */
7375     { Bad_Opcode },
7376     { Bad_Opcode },
7377     { Bad_Opcode },
7378     { Bad_Opcode },
7379     { Bad_Opcode },
7380     { Bad_Opcode },
7381     { Bad_Opcode },
7382     { Bad_Opcode },
7383     /* c0 */
7384     { Bad_Opcode },
7385     { Bad_Opcode },
7386     { Bad_Opcode },
7387     { Bad_Opcode },
7388     { Bad_Opcode },
7389     { Bad_Opcode },
7390     { Bad_Opcode },
7391     { Bad_Opcode },
7392     /* c8 */
7393     { PREFIX_TABLE (PREFIX_0F38C8) },
7394     { PREFIX_TABLE (PREFIX_0F38C9) },
7395     { PREFIX_TABLE (PREFIX_0F38CA) },
7396     { PREFIX_TABLE (PREFIX_0F38CB) },
7397     { PREFIX_TABLE (PREFIX_0F38CC) },
7398     { PREFIX_TABLE (PREFIX_0F38CD) },
7399     { Bad_Opcode },
7400     { PREFIX_TABLE (PREFIX_0F38CF) },
7401     /* d0 */
7402     { Bad_Opcode },
7403     { Bad_Opcode },
7404     { Bad_Opcode },
7405     { Bad_Opcode },
7406     { Bad_Opcode },
7407     { Bad_Opcode },
7408     { Bad_Opcode },
7409     { Bad_Opcode },
7410     /* d8 */
7411     { Bad_Opcode },
7412     { Bad_Opcode },
7413     { Bad_Opcode },
7414     { PREFIX_TABLE (PREFIX_0F38DB) },
7415     { PREFIX_TABLE (PREFIX_0F38DC) },
7416     { PREFIX_TABLE (PREFIX_0F38DD) },
7417     { PREFIX_TABLE (PREFIX_0F38DE) },
7418     { PREFIX_TABLE (PREFIX_0F38DF) },
7419     /* e0 */
7420     { Bad_Opcode },
7421     { Bad_Opcode },
7422     { Bad_Opcode },
7423     { Bad_Opcode },
7424     { Bad_Opcode },
7425     { Bad_Opcode },
7426     { Bad_Opcode },
7427     { Bad_Opcode },
7428     /* e8 */
7429     { Bad_Opcode },
7430     { Bad_Opcode },
7431     { Bad_Opcode },
7432     { Bad_Opcode },
7433     { Bad_Opcode },
7434     { Bad_Opcode },
7435     { Bad_Opcode },
7436     { Bad_Opcode },
7437     /* f0 */
7438     { PREFIX_TABLE (PREFIX_0F38F0) },
7439     { PREFIX_TABLE (PREFIX_0F38F1) },
7440     { Bad_Opcode },
7441     { Bad_Opcode },
7442     { Bad_Opcode },
7443     { PREFIX_TABLE (PREFIX_0F38F5) },
7444     { PREFIX_TABLE (PREFIX_0F38F6) },
7445     { Bad_Opcode },
7446     /* f8 */
7447     { Bad_Opcode },
7448     { Bad_Opcode },
7449     { Bad_Opcode },
7450     { Bad_Opcode },
7451     { Bad_Opcode },
7452     { Bad_Opcode },
7453     { Bad_Opcode },
7454     { Bad_Opcode },
7455   },
7456   /* THREE_BYTE_0F3A */
7457   {
7458     /* 00 */
7459     { Bad_Opcode },
7460     { Bad_Opcode },
7461     { Bad_Opcode },
7462     { Bad_Opcode },
7463     { Bad_Opcode },
7464     { Bad_Opcode },
7465     { Bad_Opcode },
7466     { Bad_Opcode },
7467     /* 08 */
7468     { PREFIX_TABLE (PREFIX_0F3A08) },
7469     { PREFIX_TABLE (PREFIX_0F3A09) },
7470     { PREFIX_TABLE (PREFIX_0F3A0A) },
7471     { PREFIX_TABLE (PREFIX_0F3A0B) },
7472     { PREFIX_TABLE (PREFIX_0F3A0C) },
7473     { PREFIX_TABLE (PREFIX_0F3A0D) },
7474     { PREFIX_TABLE (PREFIX_0F3A0E) },
7475     { "palignr",        { MX, EM, Ib }, PREFIX_OPCODE },
7476     /* 10 */
7477     { Bad_Opcode },
7478     { Bad_Opcode },
7479     { Bad_Opcode },
7480     { Bad_Opcode },
7481     { PREFIX_TABLE (PREFIX_0F3A14) },
7482     { PREFIX_TABLE (PREFIX_0F3A15) },
7483     { PREFIX_TABLE (PREFIX_0F3A16) },
7484     { PREFIX_TABLE (PREFIX_0F3A17) },
7485     /* 18 */
7486     { Bad_Opcode },
7487     { Bad_Opcode },
7488     { Bad_Opcode },
7489     { Bad_Opcode },
7490     { Bad_Opcode },
7491     { Bad_Opcode },
7492     { Bad_Opcode },
7493     { Bad_Opcode },
7494     /* 20 */
7495     { PREFIX_TABLE (PREFIX_0F3A20) },
7496     { PREFIX_TABLE (PREFIX_0F3A21) },
7497     { PREFIX_TABLE (PREFIX_0F3A22) },
7498     { Bad_Opcode },
7499     { Bad_Opcode },
7500     { Bad_Opcode },
7501     { Bad_Opcode },
7502     { Bad_Opcode },
7503     /* 28 */
7504     { Bad_Opcode },
7505     { Bad_Opcode },
7506     { Bad_Opcode },
7507     { Bad_Opcode },
7508     { Bad_Opcode },
7509     { Bad_Opcode },
7510     { Bad_Opcode },
7511     { Bad_Opcode },
7512     /* 30 */
7513     { Bad_Opcode },
7514     { Bad_Opcode },
7515     { Bad_Opcode },
7516     { Bad_Opcode },
7517     { Bad_Opcode },
7518     { Bad_Opcode },
7519     { Bad_Opcode },
7520     { Bad_Opcode },
7521     /* 38 */
7522     { Bad_Opcode },
7523     { Bad_Opcode },
7524     { Bad_Opcode },
7525     { Bad_Opcode },
7526     { Bad_Opcode },
7527     { Bad_Opcode },
7528     { Bad_Opcode },
7529     { Bad_Opcode },
7530     /* 40 */
7531     { PREFIX_TABLE (PREFIX_0F3A40) },
7532     { PREFIX_TABLE (PREFIX_0F3A41) },
7533     { PREFIX_TABLE (PREFIX_0F3A42) },
7534     { Bad_Opcode },
7535     { PREFIX_TABLE (PREFIX_0F3A44) },
7536     { Bad_Opcode },
7537     { Bad_Opcode },
7538     { Bad_Opcode },
7539     /* 48 */
7540     { Bad_Opcode },
7541     { Bad_Opcode },
7542     { Bad_Opcode },
7543     { Bad_Opcode },
7544     { Bad_Opcode },
7545     { Bad_Opcode },
7546     { Bad_Opcode },
7547     { Bad_Opcode },
7548     /* 50 */
7549     { Bad_Opcode },
7550     { Bad_Opcode },
7551     { Bad_Opcode },
7552     { Bad_Opcode },
7553     { Bad_Opcode },
7554     { Bad_Opcode },
7555     { Bad_Opcode },
7556     { Bad_Opcode },
7557     /* 58 */
7558     { Bad_Opcode },
7559     { Bad_Opcode },
7560     { Bad_Opcode },
7561     { Bad_Opcode },
7562     { Bad_Opcode },
7563     { Bad_Opcode },
7564     { Bad_Opcode },
7565     { Bad_Opcode },
7566     /* 60 */
7567     { PREFIX_TABLE (PREFIX_0F3A60) },
7568     { PREFIX_TABLE (PREFIX_0F3A61) },
7569     { PREFIX_TABLE (PREFIX_0F3A62) },
7570     { PREFIX_TABLE (PREFIX_0F3A63) },
7571     { Bad_Opcode },
7572     { Bad_Opcode },
7573     { Bad_Opcode },
7574     { Bad_Opcode },
7575     /* 68 */
7576     { Bad_Opcode },
7577     { Bad_Opcode },
7578     { Bad_Opcode },
7579     { Bad_Opcode },
7580     { Bad_Opcode },
7581     { Bad_Opcode },
7582     { Bad_Opcode },
7583     { Bad_Opcode },
7584     /* 70 */
7585     { Bad_Opcode },
7586     { Bad_Opcode },
7587     { Bad_Opcode },
7588     { Bad_Opcode },
7589     { Bad_Opcode },
7590     { Bad_Opcode },
7591     { Bad_Opcode },
7592     { Bad_Opcode },
7593     /* 78 */
7594     { Bad_Opcode },
7595     { Bad_Opcode },
7596     { Bad_Opcode },
7597     { Bad_Opcode },
7598     { Bad_Opcode },
7599     { Bad_Opcode },
7600     { Bad_Opcode },
7601     { Bad_Opcode },
7602     /* 80 */
7603     { Bad_Opcode },
7604     { Bad_Opcode },
7605     { Bad_Opcode },
7606     { Bad_Opcode },
7607     { Bad_Opcode },
7608     { Bad_Opcode },
7609     { Bad_Opcode },
7610     { Bad_Opcode },
7611     /* 88 */
7612     { Bad_Opcode },
7613     { Bad_Opcode },
7614     { Bad_Opcode },
7615     { Bad_Opcode },
7616     { Bad_Opcode },
7617     { Bad_Opcode },
7618     { Bad_Opcode },
7619     { Bad_Opcode },
7620     /* 90 */
7621     { Bad_Opcode },
7622     { Bad_Opcode },
7623     { Bad_Opcode },
7624     { Bad_Opcode },
7625     { Bad_Opcode },
7626     { Bad_Opcode },
7627     { Bad_Opcode },
7628     { Bad_Opcode },
7629     /* 98 */
7630     { Bad_Opcode },
7631     { Bad_Opcode },
7632     { Bad_Opcode },
7633     { Bad_Opcode },
7634     { Bad_Opcode },
7635     { Bad_Opcode },
7636     { Bad_Opcode },
7637     { Bad_Opcode },
7638     /* a0 */
7639     { Bad_Opcode },
7640     { Bad_Opcode },
7641     { Bad_Opcode },
7642     { Bad_Opcode },
7643     { Bad_Opcode },
7644     { Bad_Opcode },
7645     { Bad_Opcode },
7646     { Bad_Opcode },
7647     /* a8 */
7648     { Bad_Opcode },
7649     { Bad_Opcode },
7650     { Bad_Opcode },
7651     { Bad_Opcode },
7652     { Bad_Opcode },
7653     { Bad_Opcode },
7654     { Bad_Opcode },
7655     { Bad_Opcode },
7656     /* b0 */
7657     { Bad_Opcode },
7658     { Bad_Opcode },
7659     { Bad_Opcode },
7660     { Bad_Opcode },
7661     { Bad_Opcode },
7662     { Bad_Opcode },
7663     { Bad_Opcode },
7664     { Bad_Opcode },
7665     /* b8 */
7666     { Bad_Opcode },
7667     { Bad_Opcode },
7668     { Bad_Opcode },
7669     { Bad_Opcode },
7670     { Bad_Opcode },
7671     { Bad_Opcode },
7672     { Bad_Opcode },
7673     { Bad_Opcode },
7674     /* c0 */
7675     { Bad_Opcode },
7676     { Bad_Opcode },
7677     { Bad_Opcode },
7678     { Bad_Opcode },
7679     { Bad_Opcode },
7680     { Bad_Opcode },
7681     { Bad_Opcode },
7682     { Bad_Opcode },
7683     /* c8 */
7684     { Bad_Opcode },
7685     { Bad_Opcode },
7686     { Bad_Opcode },
7687     { Bad_Opcode },
7688     { PREFIX_TABLE (PREFIX_0F3ACC) },
7689     { Bad_Opcode },
7690     { PREFIX_TABLE (PREFIX_0F3ACE) },
7691     { PREFIX_TABLE (PREFIX_0F3ACF) },
7692     /* d0 */
7693     { Bad_Opcode },
7694     { Bad_Opcode },
7695     { Bad_Opcode },
7696     { Bad_Opcode },
7697     { Bad_Opcode },
7698     { Bad_Opcode },
7699     { Bad_Opcode },
7700     { Bad_Opcode },
7701     /* d8 */
7702     { Bad_Opcode },
7703     { Bad_Opcode },
7704     { Bad_Opcode },
7705     { Bad_Opcode },
7706     { Bad_Opcode },
7707     { Bad_Opcode },
7708     { Bad_Opcode },
7709     { PREFIX_TABLE (PREFIX_0F3ADF) },
7710     /* e0 */
7711     { Bad_Opcode },
7712     { Bad_Opcode },
7713     { Bad_Opcode },
7714     { Bad_Opcode },
7715     { Bad_Opcode },
7716     { Bad_Opcode },
7717     { Bad_Opcode },
7718     { Bad_Opcode },
7719     /* e8 */
7720     { Bad_Opcode },
7721     { Bad_Opcode },
7722     { Bad_Opcode },
7723     { Bad_Opcode },
7724     { Bad_Opcode },
7725     { Bad_Opcode },
7726     { Bad_Opcode },
7727     { Bad_Opcode },
7728     /* f0 */
7729     { Bad_Opcode },
7730     { Bad_Opcode },
7731     { Bad_Opcode },
7732     { Bad_Opcode },
7733     { Bad_Opcode },
7734     { Bad_Opcode },
7735     { Bad_Opcode },
7736     { Bad_Opcode },
7737     /* f8 */
7738     { Bad_Opcode },
7739     { Bad_Opcode },
7740     { Bad_Opcode },
7741     { Bad_Opcode },
7742     { Bad_Opcode },
7743     { Bad_Opcode },
7744     { Bad_Opcode },
7745     { Bad_Opcode },
7746   },
7747 };
7748
7749 static const struct dis386 xop_table[][256] = {
7750   /* XOP_08 */
7751   {
7752     /* 00 */
7753     { Bad_Opcode },
7754     { Bad_Opcode },
7755     { Bad_Opcode },
7756     { Bad_Opcode },
7757     { Bad_Opcode },
7758     { Bad_Opcode },
7759     { Bad_Opcode },
7760     { Bad_Opcode },
7761     /* 08 */
7762     { Bad_Opcode },
7763     { Bad_Opcode },
7764     { Bad_Opcode },
7765     { Bad_Opcode },
7766     { Bad_Opcode },
7767     { Bad_Opcode },
7768     { Bad_Opcode },
7769     { Bad_Opcode },
7770     /* 10 */
7771     { Bad_Opcode },
7772     { Bad_Opcode },
7773     { Bad_Opcode },
7774     { Bad_Opcode },
7775     { Bad_Opcode },
7776     { Bad_Opcode },
7777     { Bad_Opcode },
7778     { Bad_Opcode },
7779     /* 18 */
7780     { Bad_Opcode },
7781     { Bad_Opcode },
7782     { Bad_Opcode },
7783     { Bad_Opcode },
7784     { Bad_Opcode },
7785     { Bad_Opcode },
7786     { Bad_Opcode },
7787     { Bad_Opcode },
7788     /* 20 */
7789     { Bad_Opcode },
7790     { Bad_Opcode },
7791     { Bad_Opcode },
7792     { Bad_Opcode },
7793     { Bad_Opcode },
7794     { Bad_Opcode },
7795     { Bad_Opcode },
7796     { Bad_Opcode },
7797     /* 28 */
7798     { Bad_Opcode },
7799     { Bad_Opcode },
7800     { Bad_Opcode },
7801     { Bad_Opcode },
7802     { Bad_Opcode },
7803     { Bad_Opcode },
7804     { Bad_Opcode },
7805     { Bad_Opcode },
7806     /* 30 */
7807     { Bad_Opcode },
7808     { Bad_Opcode },
7809     { Bad_Opcode },
7810     { Bad_Opcode },
7811     { Bad_Opcode },
7812     { Bad_Opcode },
7813     { Bad_Opcode },
7814     { Bad_Opcode },
7815     /* 38 */
7816     { Bad_Opcode },
7817     { Bad_Opcode },
7818     { Bad_Opcode },
7819     { Bad_Opcode },
7820     { Bad_Opcode },
7821     { Bad_Opcode },
7822     { Bad_Opcode },
7823     { Bad_Opcode },
7824     /* 40 */
7825     { Bad_Opcode },
7826     { Bad_Opcode },
7827     { Bad_Opcode },
7828     { Bad_Opcode },
7829     { Bad_Opcode },
7830     { Bad_Opcode },
7831     { Bad_Opcode },
7832     { Bad_Opcode },
7833     /* 48 */
7834     { Bad_Opcode },
7835     { Bad_Opcode },
7836     { Bad_Opcode },
7837     { Bad_Opcode },
7838     { Bad_Opcode },
7839     { Bad_Opcode },
7840     { Bad_Opcode },
7841     { Bad_Opcode },
7842     /* 50 */
7843     { Bad_Opcode },
7844     { Bad_Opcode },
7845     { Bad_Opcode },
7846     { Bad_Opcode },
7847     { Bad_Opcode },
7848     { Bad_Opcode },
7849     { Bad_Opcode },
7850     { Bad_Opcode },
7851     /* 58 */
7852     { Bad_Opcode },
7853     { Bad_Opcode },
7854     { Bad_Opcode },
7855     { Bad_Opcode },
7856     { Bad_Opcode },
7857     { Bad_Opcode },
7858     { Bad_Opcode },
7859     { Bad_Opcode },
7860     /* 60 */
7861     { Bad_Opcode },
7862     { Bad_Opcode },
7863     { Bad_Opcode },
7864     { Bad_Opcode },
7865     { Bad_Opcode },
7866     { Bad_Opcode },
7867     { Bad_Opcode },
7868     { Bad_Opcode },
7869     /* 68 */
7870     { Bad_Opcode },
7871     { Bad_Opcode },
7872     { Bad_Opcode },
7873     { Bad_Opcode },
7874     { Bad_Opcode },
7875     { Bad_Opcode },
7876     { Bad_Opcode },
7877     { Bad_Opcode },
7878     /* 70 */
7879     { Bad_Opcode },
7880     { Bad_Opcode },
7881     { Bad_Opcode },
7882     { Bad_Opcode },
7883     { Bad_Opcode },
7884     { Bad_Opcode },
7885     { Bad_Opcode },
7886     { Bad_Opcode },
7887     /* 78 */
7888     { Bad_Opcode },
7889     { Bad_Opcode },
7890     { Bad_Opcode },
7891     { Bad_Opcode },
7892     { Bad_Opcode },
7893     { Bad_Opcode },
7894     { Bad_Opcode },
7895     { Bad_Opcode },
7896     /* 80 */
7897     { Bad_Opcode },
7898     { Bad_Opcode },
7899     { Bad_Opcode },
7900     { Bad_Opcode },
7901     { Bad_Opcode },
7902     { "vpmacssww",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7903     { "vpmacsswd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7904     { "vpmacssdql",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7905     /* 88 */
7906     { Bad_Opcode },
7907     { Bad_Opcode },
7908     { Bad_Opcode },
7909     { Bad_Opcode },
7910     { Bad_Opcode },
7911     { Bad_Opcode },
7912     { "vpmacssdd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7913     { "vpmacssdqh",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7914     /* 90 */
7915     { Bad_Opcode },
7916     { Bad_Opcode },
7917     { Bad_Opcode },
7918     { Bad_Opcode },
7919     { Bad_Opcode },
7920     { "vpmacsww",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7921     { "vpmacswd",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7922     { "vpmacsdql",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7923     /* 98 */
7924     { Bad_Opcode },
7925     { Bad_Opcode },
7926     { Bad_Opcode },
7927     { Bad_Opcode },
7928     { Bad_Opcode },
7929     { Bad_Opcode },
7930     { "vpmacsdd",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7931     { "vpmacsdqh",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7932     /* a0 */
7933     { Bad_Opcode },
7934     { Bad_Opcode },
7935     { "vpcmov",         { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7936     { "vpperm",         { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7937     { Bad_Opcode },
7938     { Bad_Opcode },
7939     { "vpmadcsswd",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7940     { Bad_Opcode },
7941     /* a8 */
7942     { Bad_Opcode },
7943     { Bad_Opcode },
7944     { Bad_Opcode },
7945     { Bad_Opcode },
7946     { Bad_Opcode },
7947     { Bad_Opcode },
7948     { Bad_Opcode },
7949     { Bad_Opcode },
7950     /* b0 */
7951     { Bad_Opcode },
7952     { Bad_Opcode },
7953     { Bad_Opcode },
7954     { Bad_Opcode },
7955     { Bad_Opcode },
7956     { Bad_Opcode },
7957     { "vpmadcswd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7958     { Bad_Opcode },
7959     /* b8 */
7960     { Bad_Opcode },
7961     { Bad_Opcode },
7962     { Bad_Opcode },
7963     { Bad_Opcode },
7964     { Bad_Opcode },
7965     { Bad_Opcode },
7966     { Bad_Opcode },
7967     { Bad_Opcode },
7968     /* c0 */
7969     { "vprotb",         { XM, Vex_2src_1, Ib }, 0 },
7970     { "vprotw",         { XM, Vex_2src_1, Ib }, 0 },
7971     { "vprotd",         { XM, Vex_2src_1, Ib }, 0 },
7972     { "vprotq",         { XM, Vex_2src_1, Ib }, 0 },
7973     { Bad_Opcode },
7974     { Bad_Opcode },
7975     { Bad_Opcode },
7976     { Bad_Opcode },
7977     /* c8 */
7978     { Bad_Opcode },
7979     { Bad_Opcode },
7980     { Bad_Opcode },
7981     { Bad_Opcode },
7982     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
7983     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
7984     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
7985     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
7986     /* d0 */
7987     { Bad_Opcode },
7988     { Bad_Opcode },
7989     { Bad_Opcode },
7990     { Bad_Opcode },
7991     { Bad_Opcode },
7992     { Bad_Opcode },
7993     { Bad_Opcode },
7994     { Bad_Opcode },
7995     /* d8 */
7996     { Bad_Opcode },
7997     { Bad_Opcode },
7998     { Bad_Opcode },
7999     { Bad_Opcode },
8000     { Bad_Opcode },
8001     { Bad_Opcode },
8002     { Bad_Opcode },
8003     { Bad_Opcode },
8004     /* e0 */
8005     { Bad_Opcode },
8006     { Bad_Opcode },
8007     { Bad_Opcode },
8008     { Bad_Opcode },
8009     { Bad_Opcode },
8010     { Bad_Opcode },
8011     { Bad_Opcode },
8012     { Bad_Opcode },
8013     /* e8 */
8014     { Bad_Opcode },
8015     { Bad_Opcode },
8016     { Bad_Opcode },
8017     { Bad_Opcode },
8018     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
8019     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
8020     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
8021     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
8022     /* f0 */
8023     { Bad_Opcode },
8024     { Bad_Opcode },
8025     { Bad_Opcode },
8026     { Bad_Opcode },
8027     { Bad_Opcode },
8028     { Bad_Opcode },
8029     { Bad_Opcode },
8030     { Bad_Opcode },
8031     /* f8 */
8032     { Bad_Opcode },
8033     { Bad_Opcode },
8034     { Bad_Opcode },
8035     { Bad_Opcode },
8036     { Bad_Opcode },
8037     { Bad_Opcode },
8038     { Bad_Opcode },
8039     { Bad_Opcode },
8040   },
8041   /* XOP_09 */
8042   {
8043     /* 00 */
8044     { Bad_Opcode },
8045     { REG_TABLE (REG_XOP_TBM_01) },
8046     { REG_TABLE (REG_XOP_TBM_02) },
8047     { Bad_Opcode },
8048     { Bad_Opcode },
8049     { Bad_Opcode },
8050     { Bad_Opcode },
8051     { Bad_Opcode },
8052     /* 08 */
8053     { Bad_Opcode },
8054     { Bad_Opcode },
8055     { Bad_Opcode },
8056     { Bad_Opcode },
8057     { Bad_Opcode },
8058     { Bad_Opcode },
8059     { Bad_Opcode },
8060     { Bad_Opcode },
8061     /* 10 */
8062     { Bad_Opcode },
8063     { Bad_Opcode },
8064     { REG_TABLE (REG_XOP_LWPCB) },
8065     { Bad_Opcode },
8066     { Bad_Opcode },
8067     { Bad_Opcode },
8068     { Bad_Opcode },
8069     { Bad_Opcode },
8070     /* 18 */
8071     { Bad_Opcode },
8072     { Bad_Opcode },
8073     { Bad_Opcode },
8074     { Bad_Opcode },
8075     { Bad_Opcode },
8076     { Bad_Opcode },
8077     { Bad_Opcode },
8078     { Bad_Opcode },
8079     /* 20 */
8080     { Bad_Opcode },
8081     { Bad_Opcode },
8082     { Bad_Opcode },
8083     { Bad_Opcode },
8084     { Bad_Opcode },
8085     { Bad_Opcode },
8086     { Bad_Opcode },
8087     { Bad_Opcode },
8088     /* 28 */
8089     { Bad_Opcode },
8090     { Bad_Opcode },
8091     { Bad_Opcode },
8092     { Bad_Opcode },
8093     { Bad_Opcode },
8094     { Bad_Opcode },
8095     { Bad_Opcode },
8096     { Bad_Opcode },
8097     /* 30 */
8098     { Bad_Opcode },
8099     { Bad_Opcode },
8100     { Bad_Opcode },
8101     { Bad_Opcode },
8102     { Bad_Opcode },
8103     { Bad_Opcode },
8104     { Bad_Opcode },
8105     { Bad_Opcode },
8106     /* 38 */
8107     { Bad_Opcode },
8108     { Bad_Opcode },
8109     { Bad_Opcode },
8110     { Bad_Opcode },
8111     { Bad_Opcode },
8112     { Bad_Opcode },
8113     { Bad_Opcode },
8114     { Bad_Opcode },
8115     /* 40 */
8116     { Bad_Opcode },
8117     { Bad_Opcode },
8118     { Bad_Opcode },
8119     { Bad_Opcode },
8120     { Bad_Opcode },
8121     { Bad_Opcode },
8122     { Bad_Opcode },
8123     { Bad_Opcode },
8124     /* 48 */
8125     { Bad_Opcode },
8126     { Bad_Opcode },
8127     { Bad_Opcode },
8128     { Bad_Opcode },
8129     { Bad_Opcode },
8130     { Bad_Opcode },
8131     { Bad_Opcode },
8132     { Bad_Opcode },
8133     /* 50 */
8134     { Bad_Opcode },
8135     { Bad_Opcode },
8136     { Bad_Opcode },
8137     { Bad_Opcode },
8138     { Bad_Opcode },
8139     { Bad_Opcode },
8140     { Bad_Opcode },
8141     { Bad_Opcode },
8142     /* 58 */
8143     { Bad_Opcode },
8144     { Bad_Opcode },
8145     { Bad_Opcode },
8146     { Bad_Opcode },
8147     { Bad_Opcode },
8148     { Bad_Opcode },
8149     { Bad_Opcode },
8150     { Bad_Opcode },
8151     /* 60 */
8152     { Bad_Opcode },
8153     { Bad_Opcode },
8154     { Bad_Opcode },
8155     { Bad_Opcode },
8156     { Bad_Opcode },
8157     { Bad_Opcode },
8158     { Bad_Opcode },
8159     { Bad_Opcode },
8160     /* 68 */
8161     { Bad_Opcode },
8162     { Bad_Opcode },
8163     { Bad_Opcode },
8164     { Bad_Opcode },
8165     { Bad_Opcode },
8166     { Bad_Opcode },
8167     { Bad_Opcode },
8168     { Bad_Opcode },
8169     /* 70 */
8170     { Bad_Opcode },
8171     { Bad_Opcode },
8172     { Bad_Opcode },
8173     { Bad_Opcode },
8174     { Bad_Opcode },
8175     { Bad_Opcode },
8176     { Bad_Opcode },
8177     { Bad_Opcode },
8178     /* 78 */
8179     { Bad_Opcode },
8180     { Bad_Opcode },
8181     { Bad_Opcode },
8182     { Bad_Opcode },
8183     { Bad_Opcode },
8184     { Bad_Opcode },
8185     { Bad_Opcode },
8186     { Bad_Opcode },
8187     /* 80 */
8188     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
8189     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
8190     { "vfrczss",        { XM, EXd }, 0 },
8191     { "vfrczsd",        { XM, EXq }, 0 },
8192     { Bad_Opcode },
8193     { Bad_Opcode },
8194     { Bad_Opcode },
8195     { Bad_Opcode },
8196     /* 88 */
8197     { Bad_Opcode },
8198     { Bad_Opcode },
8199     { Bad_Opcode },
8200     { Bad_Opcode },
8201     { Bad_Opcode },
8202     { Bad_Opcode },
8203     { Bad_Opcode },
8204     { Bad_Opcode },
8205     /* 90 */
8206     { "vprotb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8207     { "vprotw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8208     { "vprotd",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8209     { "vprotq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8210     { "vpshlb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8211     { "vpshlw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8212     { "vpshld",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8213     { "vpshlq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8214     /* 98 */
8215     { "vpshab",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8216     { "vpshaw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8217     { "vpshad",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8218     { "vpshaq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8219     { Bad_Opcode },
8220     { Bad_Opcode },
8221     { Bad_Opcode },
8222     { Bad_Opcode },
8223     /* a0 */
8224     { Bad_Opcode },
8225     { Bad_Opcode },
8226     { Bad_Opcode },
8227     { Bad_Opcode },
8228     { Bad_Opcode },
8229     { Bad_Opcode },
8230     { Bad_Opcode },
8231     { Bad_Opcode },
8232     /* a8 */
8233     { Bad_Opcode },
8234     { Bad_Opcode },
8235     { Bad_Opcode },
8236     { Bad_Opcode },
8237     { Bad_Opcode },
8238     { Bad_Opcode },
8239     { Bad_Opcode },
8240     { Bad_Opcode },
8241     /* b0 */
8242     { Bad_Opcode },
8243     { Bad_Opcode },
8244     { Bad_Opcode },
8245     { Bad_Opcode },
8246     { Bad_Opcode },
8247     { Bad_Opcode },
8248     { Bad_Opcode },
8249     { Bad_Opcode },
8250     /* b8 */
8251     { Bad_Opcode },
8252     { Bad_Opcode },
8253     { Bad_Opcode },
8254     { Bad_Opcode },
8255     { Bad_Opcode },
8256     { Bad_Opcode },
8257     { Bad_Opcode },
8258     { Bad_Opcode },
8259     /* c0 */
8260     { Bad_Opcode },
8261     { "vphaddbw",       { XM, EXxmm }, 0 },
8262     { "vphaddbd",       { XM, EXxmm }, 0 },
8263     { "vphaddbq",       { XM, EXxmm }, 0 },
8264     { Bad_Opcode },
8265     { Bad_Opcode },
8266     { "vphaddwd",       { XM, EXxmm }, 0 },
8267     { "vphaddwq",       { XM, EXxmm }, 0 },
8268     /* c8 */
8269     { Bad_Opcode },
8270     { Bad_Opcode },
8271     { Bad_Opcode },
8272     { "vphadddq",       { XM, EXxmm }, 0 },
8273     { Bad_Opcode },
8274     { Bad_Opcode },
8275     { Bad_Opcode },
8276     { Bad_Opcode },
8277     /* d0 */
8278     { Bad_Opcode },
8279     { "vphaddubw",      { XM, EXxmm }, 0 },
8280     { "vphaddubd",      { XM, EXxmm }, 0 },
8281     { "vphaddubq",      { XM, EXxmm }, 0 },
8282     { Bad_Opcode },
8283     { Bad_Opcode },
8284     { "vphadduwd",      { XM, EXxmm }, 0 },
8285     { "vphadduwq",      { XM, EXxmm }, 0 },
8286     /* d8 */
8287     { Bad_Opcode },
8288     { Bad_Opcode },
8289     { Bad_Opcode },
8290     { "vphaddudq",      { XM, EXxmm }, 0 },
8291     { Bad_Opcode },
8292     { Bad_Opcode },
8293     { Bad_Opcode },
8294     { Bad_Opcode },
8295     /* e0 */
8296     { Bad_Opcode },
8297     { "vphsubbw",       { XM, EXxmm }, 0 },
8298     { "vphsubwd",       { XM, EXxmm }, 0 },
8299     { "vphsubdq",       { XM, EXxmm }, 0 },
8300     { Bad_Opcode },
8301     { Bad_Opcode },
8302     { Bad_Opcode },
8303     { Bad_Opcode },
8304     /* e8 */
8305     { Bad_Opcode },
8306     { Bad_Opcode },
8307     { Bad_Opcode },
8308     { Bad_Opcode },
8309     { Bad_Opcode },
8310     { Bad_Opcode },
8311     { Bad_Opcode },
8312     { Bad_Opcode },
8313     /* f0 */
8314     { Bad_Opcode },
8315     { Bad_Opcode },
8316     { Bad_Opcode },
8317     { Bad_Opcode },
8318     { Bad_Opcode },
8319     { Bad_Opcode },
8320     { Bad_Opcode },
8321     { Bad_Opcode },
8322     /* f8 */
8323     { Bad_Opcode },
8324     { Bad_Opcode },
8325     { Bad_Opcode },
8326     { Bad_Opcode },
8327     { Bad_Opcode },
8328     { Bad_Opcode },
8329     { Bad_Opcode },
8330     { Bad_Opcode },
8331   },
8332   /* XOP_0A */
8333   {
8334     /* 00 */
8335     { Bad_Opcode },
8336     { Bad_Opcode },
8337     { Bad_Opcode },
8338     { Bad_Opcode },
8339     { Bad_Opcode },
8340     { Bad_Opcode },
8341     { Bad_Opcode },
8342     { Bad_Opcode },
8343     /* 08 */
8344     { Bad_Opcode },
8345     { Bad_Opcode },
8346     { Bad_Opcode },
8347     { Bad_Opcode },
8348     { Bad_Opcode },
8349     { Bad_Opcode },
8350     { Bad_Opcode },
8351     { Bad_Opcode },
8352     /* 10 */
8353     { "bextr",  { Gv, Ev, Iq }, 0 },
8354     { Bad_Opcode },
8355     { REG_TABLE (REG_XOP_LWP) },
8356     { Bad_Opcode },
8357     { Bad_Opcode },
8358     { Bad_Opcode },
8359     { Bad_Opcode },
8360     { Bad_Opcode },
8361     /* 18 */
8362     { Bad_Opcode },
8363     { Bad_Opcode },
8364     { Bad_Opcode },
8365     { Bad_Opcode },
8366     { Bad_Opcode },
8367     { Bad_Opcode },
8368     { Bad_Opcode },
8369     { Bad_Opcode },
8370     /* 20 */
8371     { Bad_Opcode },
8372     { Bad_Opcode },
8373     { Bad_Opcode },
8374     { Bad_Opcode },
8375     { Bad_Opcode },
8376     { Bad_Opcode },
8377     { Bad_Opcode },
8378     { Bad_Opcode },
8379     /* 28 */
8380     { Bad_Opcode },
8381     { Bad_Opcode },
8382     { Bad_Opcode },
8383     { Bad_Opcode },
8384     { Bad_Opcode },
8385     { Bad_Opcode },
8386     { Bad_Opcode },
8387     { Bad_Opcode },
8388     /* 30 */
8389     { Bad_Opcode },
8390     { Bad_Opcode },
8391     { Bad_Opcode },
8392     { Bad_Opcode },
8393     { Bad_Opcode },
8394     { Bad_Opcode },
8395     { Bad_Opcode },
8396     { Bad_Opcode },
8397     /* 38 */
8398     { Bad_Opcode },
8399     { Bad_Opcode },
8400     { Bad_Opcode },
8401     { Bad_Opcode },
8402     { Bad_Opcode },
8403     { Bad_Opcode },
8404     { Bad_Opcode },
8405     { Bad_Opcode },
8406     /* 40 */
8407     { Bad_Opcode },
8408     { Bad_Opcode },
8409     { Bad_Opcode },
8410     { Bad_Opcode },
8411     { Bad_Opcode },
8412     { Bad_Opcode },
8413     { Bad_Opcode },
8414     { Bad_Opcode },
8415     /* 48 */
8416     { Bad_Opcode },
8417     { Bad_Opcode },
8418     { Bad_Opcode },
8419     { Bad_Opcode },
8420     { Bad_Opcode },
8421     { Bad_Opcode },
8422     { Bad_Opcode },
8423     { Bad_Opcode },
8424     /* 50 */
8425     { Bad_Opcode },
8426     { Bad_Opcode },
8427     { Bad_Opcode },
8428     { Bad_Opcode },
8429     { Bad_Opcode },
8430     { Bad_Opcode },
8431     { Bad_Opcode },
8432     { Bad_Opcode },
8433     /* 58 */
8434     { Bad_Opcode },
8435     { Bad_Opcode },
8436     { Bad_Opcode },
8437     { Bad_Opcode },
8438     { Bad_Opcode },
8439     { Bad_Opcode },
8440     { Bad_Opcode },
8441     { Bad_Opcode },
8442     /* 60 */
8443     { Bad_Opcode },
8444     { Bad_Opcode },
8445     { Bad_Opcode },
8446     { Bad_Opcode },
8447     { Bad_Opcode },
8448     { Bad_Opcode },
8449     { Bad_Opcode },
8450     { Bad_Opcode },
8451     /* 68 */
8452     { Bad_Opcode },
8453     { Bad_Opcode },
8454     { Bad_Opcode },
8455     { Bad_Opcode },
8456     { Bad_Opcode },
8457     { Bad_Opcode },
8458     { Bad_Opcode },
8459     { Bad_Opcode },
8460     /* 70 */
8461     { Bad_Opcode },
8462     { Bad_Opcode },
8463     { Bad_Opcode },
8464     { Bad_Opcode },
8465     { Bad_Opcode },
8466     { Bad_Opcode },
8467     { Bad_Opcode },
8468     { Bad_Opcode },
8469     /* 78 */
8470     { Bad_Opcode },
8471     { Bad_Opcode },
8472     { Bad_Opcode },
8473     { Bad_Opcode },
8474     { Bad_Opcode },
8475     { Bad_Opcode },
8476     { Bad_Opcode },
8477     { Bad_Opcode },
8478     /* 80 */
8479     { Bad_Opcode },
8480     { Bad_Opcode },
8481     { Bad_Opcode },
8482     { Bad_Opcode },
8483     { Bad_Opcode },
8484     { Bad_Opcode },
8485     { Bad_Opcode },
8486     { Bad_Opcode },
8487     /* 88 */
8488     { Bad_Opcode },
8489     { Bad_Opcode },
8490     { Bad_Opcode },
8491     { Bad_Opcode },
8492     { Bad_Opcode },
8493     { Bad_Opcode },
8494     { Bad_Opcode },
8495     { Bad_Opcode },
8496     /* 90 */
8497     { Bad_Opcode },
8498     { Bad_Opcode },
8499     { Bad_Opcode },
8500     { Bad_Opcode },
8501     { Bad_Opcode },
8502     { Bad_Opcode },
8503     { Bad_Opcode },
8504     { Bad_Opcode },
8505     /* 98 */
8506     { Bad_Opcode },
8507     { Bad_Opcode },
8508     { Bad_Opcode },
8509     { Bad_Opcode },
8510     { Bad_Opcode },
8511     { Bad_Opcode },
8512     { Bad_Opcode },
8513     { Bad_Opcode },
8514     /* a0 */
8515     { Bad_Opcode },
8516     { Bad_Opcode },
8517     { Bad_Opcode },
8518     { Bad_Opcode },
8519     { Bad_Opcode },
8520     { Bad_Opcode },
8521     { Bad_Opcode },
8522     { Bad_Opcode },
8523     /* a8 */
8524     { Bad_Opcode },
8525     { Bad_Opcode },
8526     { Bad_Opcode },
8527     { Bad_Opcode },
8528     { Bad_Opcode },
8529     { Bad_Opcode },
8530     { Bad_Opcode },
8531     { Bad_Opcode },
8532     /* b0 */
8533     { Bad_Opcode },
8534     { Bad_Opcode },
8535     { Bad_Opcode },
8536     { Bad_Opcode },
8537     { Bad_Opcode },
8538     { Bad_Opcode },
8539     { Bad_Opcode },
8540     { Bad_Opcode },
8541     /* b8 */
8542     { Bad_Opcode },
8543     { Bad_Opcode },
8544     { Bad_Opcode },
8545     { Bad_Opcode },
8546     { Bad_Opcode },
8547     { Bad_Opcode },
8548     { Bad_Opcode },
8549     { Bad_Opcode },
8550     /* c0 */
8551     { Bad_Opcode },
8552     { Bad_Opcode },
8553     { Bad_Opcode },
8554     { Bad_Opcode },
8555     { Bad_Opcode },
8556     { Bad_Opcode },
8557     { Bad_Opcode },
8558     { Bad_Opcode },
8559     /* c8 */
8560     { Bad_Opcode },
8561     { Bad_Opcode },
8562     { Bad_Opcode },
8563     { Bad_Opcode },
8564     { Bad_Opcode },
8565     { Bad_Opcode },
8566     { Bad_Opcode },
8567     { Bad_Opcode },
8568     /* d0 */
8569     { Bad_Opcode },
8570     { Bad_Opcode },
8571     { Bad_Opcode },
8572     { Bad_Opcode },
8573     { Bad_Opcode },
8574     { Bad_Opcode },
8575     { Bad_Opcode },
8576     { Bad_Opcode },
8577     /* d8 */
8578     { Bad_Opcode },
8579     { Bad_Opcode },
8580     { Bad_Opcode },
8581     { Bad_Opcode },
8582     { Bad_Opcode },
8583     { Bad_Opcode },
8584     { Bad_Opcode },
8585     { Bad_Opcode },
8586     /* e0 */
8587     { Bad_Opcode },
8588     { Bad_Opcode },
8589     { Bad_Opcode },
8590     { Bad_Opcode },
8591     { Bad_Opcode },
8592     { Bad_Opcode },
8593     { Bad_Opcode },
8594     { Bad_Opcode },
8595     /* e8 */
8596     { Bad_Opcode },
8597     { Bad_Opcode },
8598     { Bad_Opcode },
8599     { Bad_Opcode },
8600     { Bad_Opcode },
8601     { Bad_Opcode },
8602     { Bad_Opcode },
8603     { Bad_Opcode },
8604     /* f0 */
8605     { Bad_Opcode },
8606     { Bad_Opcode },
8607     { Bad_Opcode },
8608     { Bad_Opcode },
8609     { Bad_Opcode },
8610     { Bad_Opcode },
8611     { Bad_Opcode },
8612     { Bad_Opcode },
8613     /* f8 */
8614     { Bad_Opcode },
8615     { Bad_Opcode },
8616     { Bad_Opcode },
8617     { Bad_Opcode },
8618     { Bad_Opcode },
8619     { Bad_Opcode },
8620     { Bad_Opcode },
8621     { Bad_Opcode },
8622   },
8623 };
8624
8625 static const struct dis386 vex_table[][256] = {
8626   /* VEX_0F */
8627   {
8628     /* 00 */
8629     { Bad_Opcode },
8630     { Bad_Opcode },
8631     { Bad_Opcode },
8632     { Bad_Opcode },
8633     { Bad_Opcode },
8634     { Bad_Opcode },
8635     { Bad_Opcode },
8636     { Bad_Opcode },
8637     /* 08 */
8638     { Bad_Opcode },
8639     { Bad_Opcode },
8640     { Bad_Opcode },
8641     { Bad_Opcode },
8642     { Bad_Opcode },
8643     { Bad_Opcode },
8644     { Bad_Opcode },
8645     { Bad_Opcode },
8646     /* 10 */
8647     { PREFIX_TABLE (PREFIX_VEX_0F10) },
8648     { PREFIX_TABLE (PREFIX_VEX_0F11) },
8649     { PREFIX_TABLE (PREFIX_VEX_0F12) },
8650     { MOD_TABLE (MOD_VEX_0F13) },
8651     { VEX_W_TABLE (VEX_W_0F14) },
8652     { VEX_W_TABLE (VEX_W_0F15) },
8653     { PREFIX_TABLE (PREFIX_VEX_0F16) },
8654     { MOD_TABLE (MOD_VEX_0F17) },
8655     /* 18 */
8656     { Bad_Opcode },
8657     { Bad_Opcode },
8658     { Bad_Opcode },
8659     { Bad_Opcode },
8660     { Bad_Opcode },
8661     { Bad_Opcode },
8662     { Bad_Opcode },
8663     { Bad_Opcode },
8664     /* 20 */
8665     { Bad_Opcode },
8666     { Bad_Opcode },
8667     { Bad_Opcode },
8668     { Bad_Opcode },
8669     { Bad_Opcode },
8670     { Bad_Opcode },
8671     { Bad_Opcode },
8672     { Bad_Opcode },
8673     /* 28 */
8674     { VEX_W_TABLE (VEX_W_0F28) },
8675     { VEX_W_TABLE (VEX_W_0F29) },
8676     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8677     { MOD_TABLE (MOD_VEX_0F2B) },
8678     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8679     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8680     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8681     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8682     /* 30 */
8683     { Bad_Opcode },
8684     { Bad_Opcode },
8685     { Bad_Opcode },
8686     { Bad_Opcode },
8687     { Bad_Opcode },
8688     { Bad_Opcode },
8689     { Bad_Opcode },
8690     { Bad_Opcode },
8691     /* 38 */
8692     { Bad_Opcode },
8693     { Bad_Opcode },
8694     { Bad_Opcode },
8695     { Bad_Opcode },
8696     { Bad_Opcode },
8697     { Bad_Opcode },
8698     { Bad_Opcode },
8699     { Bad_Opcode },
8700     /* 40 */
8701     { Bad_Opcode },
8702     { PREFIX_TABLE (PREFIX_VEX_0F41) },
8703     { PREFIX_TABLE (PREFIX_VEX_0F42) },
8704     { Bad_Opcode },
8705     { PREFIX_TABLE (PREFIX_VEX_0F44) },
8706     { PREFIX_TABLE (PREFIX_VEX_0F45) },
8707     { PREFIX_TABLE (PREFIX_VEX_0F46) },
8708     { PREFIX_TABLE (PREFIX_VEX_0F47) },
8709     /* 48 */
8710     { Bad_Opcode },
8711     { Bad_Opcode },
8712     { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8713     { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8714     { Bad_Opcode },
8715     { Bad_Opcode },
8716     { Bad_Opcode },
8717     { Bad_Opcode },
8718     /* 50 */
8719     { MOD_TABLE (MOD_VEX_0F50) },
8720     { PREFIX_TABLE (PREFIX_VEX_0F51) },
8721     { PREFIX_TABLE (PREFIX_VEX_0F52) },
8722     { PREFIX_TABLE (PREFIX_VEX_0F53) },
8723     { "vandpX",         { XM, Vex, EXx }, 0 },
8724     { "vandnpX",        { XM, Vex, EXx }, 0 },
8725     { "vorpX",          { XM, Vex, EXx }, 0 },
8726     { "vxorpX",         { XM, Vex, EXx }, 0 },
8727     /* 58 */
8728     { PREFIX_TABLE (PREFIX_VEX_0F58) },
8729     { PREFIX_TABLE (PREFIX_VEX_0F59) },
8730     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8731     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8732     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8733     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8734     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8735     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8736     /* 60 */
8737     { PREFIX_TABLE (PREFIX_VEX_0F60) },
8738     { PREFIX_TABLE (PREFIX_VEX_0F61) },
8739     { PREFIX_TABLE (PREFIX_VEX_0F62) },
8740     { PREFIX_TABLE (PREFIX_VEX_0F63) },
8741     { PREFIX_TABLE (PREFIX_VEX_0F64) },
8742     { PREFIX_TABLE (PREFIX_VEX_0F65) },
8743     { PREFIX_TABLE (PREFIX_VEX_0F66) },
8744     { PREFIX_TABLE (PREFIX_VEX_0F67) },
8745     /* 68 */
8746     { PREFIX_TABLE (PREFIX_VEX_0F68) },
8747     { PREFIX_TABLE (PREFIX_VEX_0F69) },
8748     { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8749     { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8750     { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8751     { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8752     { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8753     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8754     /* 70 */
8755     { PREFIX_TABLE (PREFIX_VEX_0F70) },
8756     { REG_TABLE (REG_VEX_0F71) },
8757     { REG_TABLE (REG_VEX_0F72) },
8758     { REG_TABLE (REG_VEX_0F73) },
8759     { PREFIX_TABLE (PREFIX_VEX_0F74) },
8760     { PREFIX_TABLE (PREFIX_VEX_0F75) },
8761     { PREFIX_TABLE (PREFIX_VEX_0F76) },
8762     { PREFIX_TABLE (PREFIX_VEX_0F77) },
8763     /* 78 */
8764     { Bad_Opcode },
8765     { Bad_Opcode },
8766     { Bad_Opcode },
8767     { Bad_Opcode },
8768     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8769     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8770     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8771     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8772     /* 80 */
8773     { Bad_Opcode },
8774     { Bad_Opcode },
8775     { Bad_Opcode },
8776     { Bad_Opcode },
8777     { Bad_Opcode },
8778     { Bad_Opcode },
8779     { Bad_Opcode },
8780     { Bad_Opcode },
8781     /* 88 */
8782     { Bad_Opcode },
8783     { Bad_Opcode },
8784     { Bad_Opcode },
8785     { Bad_Opcode },
8786     { Bad_Opcode },
8787     { Bad_Opcode },
8788     { Bad_Opcode },
8789     { Bad_Opcode },
8790     /* 90 */
8791     { PREFIX_TABLE (PREFIX_VEX_0F90) },
8792     { PREFIX_TABLE (PREFIX_VEX_0F91) },
8793     { PREFIX_TABLE (PREFIX_VEX_0F92) },
8794     { PREFIX_TABLE (PREFIX_VEX_0F93) },
8795     { Bad_Opcode },
8796     { Bad_Opcode },
8797     { Bad_Opcode },
8798     { Bad_Opcode },
8799     /* 98 */
8800     { PREFIX_TABLE (PREFIX_VEX_0F98) },
8801     { PREFIX_TABLE (PREFIX_VEX_0F99) },
8802     { Bad_Opcode },
8803     { Bad_Opcode },
8804     { Bad_Opcode },
8805     { Bad_Opcode },
8806     { Bad_Opcode },
8807     { Bad_Opcode },
8808     /* a0 */
8809     { Bad_Opcode },
8810     { Bad_Opcode },
8811     { Bad_Opcode },
8812     { Bad_Opcode },
8813     { Bad_Opcode },
8814     { Bad_Opcode },
8815     { Bad_Opcode },
8816     { Bad_Opcode },
8817     /* a8 */
8818     { Bad_Opcode },
8819     { Bad_Opcode },
8820     { Bad_Opcode },
8821     { Bad_Opcode },
8822     { Bad_Opcode },
8823     { Bad_Opcode },
8824     { REG_TABLE (REG_VEX_0FAE) },
8825     { Bad_Opcode },
8826     /* b0 */
8827     { Bad_Opcode },
8828     { Bad_Opcode },
8829     { Bad_Opcode },
8830     { Bad_Opcode },
8831     { Bad_Opcode },
8832     { Bad_Opcode },
8833     { Bad_Opcode },
8834     { Bad_Opcode },
8835     /* b8 */
8836     { Bad_Opcode },
8837     { Bad_Opcode },
8838     { Bad_Opcode },
8839     { Bad_Opcode },
8840     { Bad_Opcode },
8841     { Bad_Opcode },
8842     { Bad_Opcode },
8843     { Bad_Opcode },
8844     /* c0 */
8845     { Bad_Opcode },
8846     { Bad_Opcode },
8847     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8848     { Bad_Opcode },
8849     { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8850     { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8851     { "vshufpX",        { XM, Vex, EXx, Ib }, 0 },
8852     { Bad_Opcode },
8853     /* c8 */
8854     { Bad_Opcode },
8855     { Bad_Opcode },
8856     { Bad_Opcode },
8857     { Bad_Opcode },
8858     { Bad_Opcode },
8859     { Bad_Opcode },
8860     { Bad_Opcode },
8861     { Bad_Opcode },
8862     /* d0 */
8863     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8864     { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8865     { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8866     { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8867     { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8868     { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8869     { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8870     { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8871     /* d8 */
8872     { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8873     { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8874     { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8875     { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8876     { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8877     { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8878     { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8879     { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8880     /* e0 */
8881     { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8882     { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8883     { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8884     { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8885     { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8886     { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8887     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8888     { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8889     /* e8 */
8890     { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8891     { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8892     { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8893     { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8894     { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8895     { PREFIX_TABLE (PREFIX_VEX_0FED) },
8896     { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8897     { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8898     /* f0 */
8899     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8900     { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8901     { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8902     { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8903     { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8904     { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8905     { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8906     { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8907     /* f8 */
8908     { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8909     { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8910     { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8911     { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8912     { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8913     { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8914     { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8915     { Bad_Opcode },
8916   },
8917   /* VEX_0F38 */
8918   {
8919     /* 00 */
8920     { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8921     { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8922     { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8923     { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8924     { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8925     { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8926     { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8927     { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8928     /* 08 */
8929     { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8930     { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8931     { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8932     { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8933     { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8934     { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8935     { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8936     { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8937     /* 10 */
8938     { Bad_Opcode },
8939     { Bad_Opcode },
8940     { Bad_Opcode },
8941     { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8942     { Bad_Opcode },
8943     { Bad_Opcode },
8944     { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8945     { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8946     /* 18 */
8947     { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8948     { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8949     { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8950     { Bad_Opcode },
8951     { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8952     { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8953     { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8954     { Bad_Opcode },
8955     /* 20 */
8956     { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8957     { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8958     { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8959     { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8960     { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8961     { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8962     { Bad_Opcode },
8963     { Bad_Opcode },
8964     /* 28 */
8965     { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8966     { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8967     { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8968     { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8969     { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8970     { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8971     { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8972     { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8973     /* 30 */
8974     { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8975     { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8976     { PREFIX_TABLE (PREFIX_VEX_0F3832) },
8977     { PREFIX_TABLE (PREFIX_VEX_0F3833) },
8978     { PREFIX_TABLE (PREFIX_VEX_0F3834) },
8979     { PREFIX_TABLE (PREFIX_VEX_0F3835) },
8980     { PREFIX_TABLE (PREFIX_VEX_0F3836) },
8981     { PREFIX_TABLE (PREFIX_VEX_0F3837) },
8982     /* 38 */
8983     { PREFIX_TABLE (PREFIX_VEX_0F3838) },
8984     { PREFIX_TABLE (PREFIX_VEX_0F3839) },
8985     { PREFIX_TABLE (PREFIX_VEX_0F383A) },
8986     { PREFIX_TABLE (PREFIX_VEX_0F383B) },
8987     { PREFIX_TABLE (PREFIX_VEX_0F383C) },
8988     { PREFIX_TABLE (PREFIX_VEX_0F383D) },
8989     { PREFIX_TABLE (PREFIX_VEX_0F383E) },
8990     { PREFIX_TABLE (PREFIX_VEX_0F383F) },
8991     /* 40 */
8992     { PREFIX_TABLE (PREFIX_VEX_0F3840) },
8993     { PREFIX_TABLE (PREFIX_VEX_0F3841) },
8994     { Bad_Opcode },
8995     { Bad_Opcode },
8996     { Bad_Opcode },
8997     { PREFIX_TABLE (PREFIX_VEX_0F3845) },
8998     { PREFIX_TABLE (PREFIX_VEX_0F3846) },
8999     { PREFIX_TABLE (PREFIX_VEX_0F3847) },
9000     /* 48 */
9001     { Bad_Opcode },
9002     { Bad_Opcode },
9003     { Bad_Opcode },
9004     { Bad_Opcode },
9005     { Bad_Opcode },
9006     { Bad_Opcode },
9007     { Bad_Opcode },
9008     { Bad_Opcode },
9009     /* 50 */
9010     { Bad_Opcode },
9011     { Bad_Opcode },
9012     { Bad_Opcode },
9013     { Bad_Opcode },
9014     { Bad_Opcode },
9015     { Bad_Opcode },
9016     { Bad_Opcode },
9017     { Bad_Opcode },
9018     /* 58 */
9019     { PREFIX_TABLE (PREFIX_VEX_0F3858) },
9020     { PREFIX_TABLE (PREFIX_VEX_0F3859) },
9021     { PREFIX_TABLE (PREFIX_VEX_0F385A) },
9022     { Bad_Opcode },
9023     { Bad_Opcode },
9024     { Bad_Opcode },
9025     { Bad_Opcode },
9026     { Bad_Opcode },
9027     /* 60 */
9028     { Bad_Opcode },
9029     { Bad_Opcode },
9030     { Bad_Opcode },
9031     { Bad_Opcode },
9032     { Bad_Opcode },
9033     { Bad_Opcode },
9034     { Bad_Opcode },
9035     { Bad_Opcode },
9036     /* 68 */
9037     { Bad_Opcode },
9038     { Bad_Opcode },
9039     { Bad_Opcode },
9040     { Bad_Opcode },
9041     { Bad_Opcode },
9042     { Bad_Opcode },
9043     { Bad_Opcode },
9044     { Bad_Opcode },
9045     /* 70 */
9046     { Bad_Opcode },
9047     { Bad_Opcode },
9048     { Bad_Opcode },
9049     { Bad_Opcode },
9050     { Bad_Opcode },
9051     { Bad_Opcode },
9052     { Bad_Opcode },
9053     { Bad_Opcode },
9054     /* 78 */
9055     { PREFIX_TABLE (PREFIX_VEX_0F3878) },
9056     { PREFIX_TABLE (PREFIX_VEX_0F3879) },
9057     { Bad_Opcode },
9058     { Bad_Opcode },
9059     { Bad_Opcode },
9060     { Bad_Opcode },
9061     { Bad_Opcode },
9062     { Bad_Opcode },
9063     /* 80 */
9064     { Bad_Opcode },
9065     { Bad_Opcode },
9066     { Bad_Opcode },
9067     { Bad_Opcode },
9068     { Bad_Opcode },
9069     { Bad_Opcode },
9070     { Bad_Opcode },
9071     { Bad_Opcode },
9072     /* 88 */
9073     { Bad_Opcode },
9074     { Bad_Opcode },
9075     { Bad_Opcode },
9076     { Bad_Opcode },
9077     { PREFIX_TABLE (PREFIX_VEX_0F388C) },
9078     { Bad_Opcode },
9079     { PREFIX_TABLE (PREFIX_VEX_0F388E) },
9080     { Bad_Opcode },
9081     /* 90 */
9082     { PREFIX_TABLE (PREFIX_VEX_0F3890) },
9083     { PREFIX_TABLE (PREFIX_VEX_0F3891) },
9084     { PREFIX_TABLE (PREFIX_VEX_0F3892) },
9085     { PREFIX_TABLE (PREFIX_VEX_0F3893) },
9086     { Bad_Opcode },
9087     { Bad_Opcode },
9088     { PREFIX_TABLE (PREFIX_VEX_0F3896) },
9089     { PREFIX_TABLE (PREFIX_VEX_0F3897) },
9090     /* 98 */
9091     { PREFIX_TABLE (PREFIX_VEX_0F3898) },
9092     { PREFIX_TABLE (PREFIX_VEX_0F3899) },
9093     { PREFIX_TABLE (PREFIX_VEX_0F389A) },
9094     { PREFIX_TABLE (PREFIX_VEX_0F389B) },
9095     { PREFIX_TABLE (PREFIX_VEX_0F389C) },
9096     { PREFIX_TABLE (PREFIX_VEX_0F389D) },
9097     { PREFIX_TABLE (PREFIX_VEX_0F389E) },
9098     { PREFIX_TABLE (PREFIX_VEX_0F389F) },
9099     /* a0 */
9100     { Bad_Opcode },
9101     { Bad_Opcode },
9102     { Bad_Opcode },
9103     { Bad_Opcode },
9104     { Bad_Opcode },
9105     { Bad_Opcode },
9106     { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
9107     { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
9108     /* a8 */
9109     { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
9110     { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
9111     { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
9112     { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
9113     { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
9114     { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
9115     { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
9116     { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
9117     /* b0 */
9118     { Bad_Opcode },
9119     { Bad_Opcode },
9120     { Bad_Opcode },
9121     { Bad_Opcode },
9122     { Bad_Opcode },
9123     { Bad_Opcode },
9124     { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
9125     { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
9126     /* b8 */
9127     { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
9128     { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
9129     { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
9130     { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
9131     { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
9132     { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
9133     { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
9134     { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
9135     /* c0 */
9136     { Bad_Opcode },
9137     { Bad_Opcode },
9138     { Bad_Opcode },
9139     { Bad_Opcode },
9140     { Bad_Opcode },
9141     { Bad_Opcode },
9142     { Bad_Opcode },
9143     { Bad_Opcode },
9144     /* c8 */
9145     { Bad_Opcode },
9146     { Bad_Opcode },
9147     { Bad_Opcode },
9148     { Bad_Opcode },
9149     { Bad_Opcode },
9150     { Bad_Opcode },
9151     { Bad_Opcode },
9152     { PREFIX_TABLE (PREFIX_VEX_0F38CF) },
9153     /* d0 */
9154     { Bad_Opcode },
9155     { Bad_Opcode },
9156     { Bad_Opcode },
9157     { Bad_Opcode },
9158     { Bad_Opcode },
9159     { Bad_Opcode },
9160     { Bad_Opcode },
9161     { Bad_Opcode },
9162     /* d8 */
9163     { Bad_Opcode },
9164     { Bad_Opcode },
9165     { Bad_Opcode },
9166     { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
9167     { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
9168     { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
9169     { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
9170     { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
9171     /* e0 */
9172     { Bad_Opcode },
9173     { Bad_Opcode },
9174     { Bad_Opcode },
9175     { Bad_Opcode },
9176     { Bad_Opcode },
9177     { Bad_Opcode },
9178     { Bad_Opcode },
9179     { Bad_Opcode },
9180     /* e8 */
9181     { Bad_Opcode },
9182     { Bad_Opcode },
9183     { Bad_Opcode },
9184     { Bad_Opcode },
9185     { Bad_Opcode },
9186     { Bad_Opcode },
9187     { Bad_Opcode },
9188     { Bad_Opcode },
9189     /* f0 */
9190     { Bad_Opcode },
9191     { Bad_Opcode },
9192     { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
9193     { REG_TABLE (REG_VEX_0F38F3) },
9194     { Bad_Opcode },
9195     { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
9196     { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
9197     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
9198     /* f8 */
9199     { Bad_Opcode },
9200     { Bad_Opcode },
9201     { Bad_Opcode },
9202     { Bad_Opcode },
9203     { Bad_Opcode },
9204     { Bad_Opcode },
9205     { Bad_Opcode },
9206     { Bad_Opcode },
9207   },
9208   /* VEX_0F3A */
9209   {
9210     /* 00 */
9211     { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
9212     { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
9213     { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
9214     { Bad_Opcode },
9215     { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
9216     { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
9217     { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
9218     { Bad_Opcode },
9219     /* 08 */
9220     { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
9221     { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
9222     { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
9223     { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
9224     { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
9225     { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
9226     { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
9227     { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
9228     /* 10 */
9229     { Bad_Opcode },
9230     { Bad_Opcode },
9231     { Bad_Opcode },
9232     { Bad_Opcode },
9233     { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
9234     { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
9235     { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
9236     { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
9237     /* 18 */
9238     { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
9239     { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
9240     { Bad_Opcode },
9241     { Bad_Opcode },
9242     { Bad_Opcode },
9243     { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
9244     { Bad_Opcode },
9245     { Bad_Opcode },
9246     /* 20 */
9247     { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
9248     { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
9249     { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
9250     { Bad_Opcode },
9251     { Bad_Opcode },
9252     { Bad_Opcode },
9253     { Bad_Opcode },
9254     { Bad_Opcode },
9255     /* 28 */
9256     { Bad_Opcode },
9257     { Bad_Opcode },
9258     { Bad_Opcode },
9259     { Bad_Opcode },
9260     { Bad_Opcode },
9261     { Bad_Opcode },
9262     { Bad_Opcode },
9263     { Bad_Opcode },
9264     /* 30 */
9265     { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
9266     { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
9267     { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
9268     { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
9269     { Bad_Opcode },
9270     { Bad_Opcode },
9271     { Bad_Opcode },
9272     { Bad_Opcode },
9273     /* 38 */
9274     { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
9275     { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
9276     { Bad_Opcode },
9277     { Bad_Opcode },
9278     { Bad_Opcode },
9279     { Bad_Opcode },
9280     { Bad_Opcode },
9281     { Bad_Opcode },
9282     /* 40 */
9283     { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
9284     { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
9285     { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
9286     { Bad_Opcode },
9287     { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
9288     { Bad_Opcode },
9289     { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
9290     { Bad_Opcode },
9291     /* 48 */
9292     { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
9293     { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
9294     { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
9295     { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
9296     { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
9297     { Bad_Opcode },
9298     { Bad_Opcode },
9299     { Bad_Opcode },
9300     /* 50 */
9301     { Bad_Opcode },
9302     { Bad_Opcode },
9303     { Bad_Opcode },
9304     { Bad_Opcode },
9305     { Bad_Opcode },
9306     { Bad_Opcode },
9307     { Bad_Opcode },
9308     { Bad_Opcode },
9309     /* 58 */
9310     { Bad_Opcode },
9311     { Bad_Opcode },
9312     { Bad_Opcode },
9313     { Bad_Opcode },
9314     { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9315     { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9316     { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9317     { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9318     /* 60 */
9319     { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9320     { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9321     { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9322     { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9323     { Bad_Opcode },
9324     { Bad_Opcode },
9325     { Bad_Opcode },
9326     { Bad_Opcode },
9327     /* 68 */
9328     { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9329     { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9330     { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9331     { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9332     { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9333     { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9334     { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9335     { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9336     /* 70 */
9337     { Bad_Opcode },
9338     { Bad_Opcode },
9339     { Bad_Opcode },
9340     { Bad_Opcode },
9341     { Bad_Opcode },
9342     { Bad_Opcode },
9343     { Bad_Opcode },
9344     { Bad_Opcode },
9345     /* 78 */
9346     { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9347     { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9348     { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9349     { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9350     { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9351     { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9352     { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9353     { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9354     /* 80 */
9355     { Bad_Opcode },
9356     { Bad_Opcode },
9357     { Bad_Opcode },
9358     { Bad_Opcode },
9359     { Bad_Opcode },
9360     { Bad_Opcode },
9361     { Bad_Opcode },
9362     { Bad_Opcode },
9363     /* 88 */
9364     { Bad_Opcode },
9365     { Bad_Opcode },
9366     { Bad_Opcode },
9367     { Bad_Opcode },
9368     { Bad_Opcode },
9369     { Bad_Opcode },
9370     { Bad_Opcode },
9371     { Bad_Opcode },
9372     /* 90 */
9373     { Bad_Opcode },
9374     { Bad_Opcode },
9375     { Bad_Opcode },
9376     { Bad_Opcode },
9377     { Bad_Opcode },
9378     { Bad_Opcode },
9379     { Bad_Opcode },
9380     { Bad_Opcode },
9381     /* 98 */
9382     { Bad_Opcode },
9383     { Bad_Opcode },
9384     { Bad_Opcode },
9385     { Bad_Opcode },
9386     { Bad_Opcode },
9387     { Bad_Opcode },
9388     { Bad_Opcode },
9389     { Bad_Opcode },
9390     /* a0 */
9391     { Bad_Opcode },
9392     { Bad_Opcode },
9393     { Bad_Opcode },
9394     { Bad_Opcode },
9395     { Bad_Opcode },
9396     { Bad_Opcode },
9397     { Bad_Opcode },
9398     { Bad_Opcode },
9399     /* a8 */
9400     { Bad_Opcode },
9401     { Bad_Opcode },
9402     { Bad_Opcode },
9403     { Bad_Opcode },
9404     { Bad_Opcode },
9405     { Bad_Opcode },
9406     { Bad_Opcode },
9407     { Bad_Opcode },
9408     /* b0 */
9409     { Bad_Opcode },
9410     { Bad_Opcode },
9411     { Bad_Opcode },
9412     { Bad_Opcode },
9413     { Bad_Opcode },
9414     { Bad_Opcode },
9415     { Bad_Opcode },
9416     { Bad_Opcode },
9417     /* b8 */
9418     { Bad_Opcode },
9419     { Bad_Opcode },
9420     { Bad_Opcode },
9421     { Bad_Opcode },
9422     { Bad_Opcode },
9423     { Bad_Opcode },
9424     { Bad_Opcode },
9425     { Bad_Opcode },
9426     /* c0 */
9427     { Bad_Opcode },
9428     { Bad_Opcode },
9429     { Bad_Opcode },
9430     { Bad_Opcode },
9431     { Bad_Opcode },
9432     { Bad_Opcode },
9433     { Bad_Opcode },
9434     { Bad_Opcode },
9435     /* c8 */
9436     { Bad_Opcode },
9437     { Bad_Opcode },
9438     { Bad_Opcode },
9439     { Bad_Opcode },
9440     { Bad_Opcode },
9441     { Bad_Opcode },
9442     { PREFIX_TABLE(PREFIX_VEX_0F3ACE) },
9443     { PREFIX_TABLE(PREFIX_VEX_0F3ACF) },
9444     /* d0 */
9445     { Bad_Opcode },
9446     { Bad_Opcode },
9447     { Bad_Opcode },
9448     { Bad_Opcode },
9449     { Bad_Opcode },
9450     { Bad_Opcode },
9451     { Bad_Opcode },
9452     { Bad_Opcode },
9453     /* d8 */
9454     { Bad_Opcode },
9455     { Bad_Opcode },
9456     { Bad_Opcode },
9457     { Bad_Opcode },
9458     { Bad_Opcode },
9459     { Bad_Opcode },
9460     { Bad_Opcode },
9461     { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9462     /* e0 */
9463     { Bad_Opcode },
9464     { Bad_Opcode },
9465     { Bad_Opcode },
9466     { Bad_Opcode },
9467     { Bad_Opcode },
9468     { Bad_Opcode },
9469     { Bad_Opcode },
9470     { Bad_Opcode },
9471     /* e8 */
9472     { Bad_Opcode },
9473     { Bad_Opcode },
9474     { Bad_Opcode },
9475     { Bad_Opcode },
9476     { Bad_Opcode },
9477     { Bad_Opcode },
9478     { Bad_Opcode },
9479     { Bad_Opcode },
9480     /* f0 */
9481     { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9482     { Bad_Opcode },
9483     { Bad_Opcode },
9484     { Bad_Opcode },
9485     { Bad_Opcode },
9486     { Bad_Opcode },
9487     { Bad_Opcode },
9488     { Bad_Opcode },
9489     /* f8 */
9490     { Bad_Opcode },
9491     { Bad_Opcode },
9492     { Bad_Opcode },
9493     { Bad_Opcode },
9494     { Bad_Opcode },
9495     { Bad_Opcode },
9496     { Bad_Opcode },
9497     { Bad_Opcode },
9498   },
9499 };
9500
9501 #define NEED_OPCODE_TABLE
9502 #include "i386-dis-evex.h"
9503 #undef NEED_OPCODE_TABLE
9504 static const struct dis386 vex_len_table[][2] = {
9505   /* VEX_LEN_0F10_P_1 */
9506   {
9507     { VEX_W_TABLE (VEX_W_0F10_P_1) },
9508     { VEX_W_TABLE (VEX_W_0F10_P_1) },
9509   },
9510
9511   /* VEX_LEN_0F10_P_3 */
9512   {
9513     { VEX_W_TABLE (VEX_W_0F10_P_3) },
9514     { VEX_W_TABLE (VEX_W_0F10_P_3) },
9515   },
9516
9517   /* VEX_LEN_0F11_P_1 */
9518   {
9519     { VEX_W_TABLE (VEX_W_0F11_P_1) },
9520     { VEX_W_TABLE (VEX_W_0F11_P_1) },
9521   },
9522
9523   /* VEX_LEN_0F11_P_3 */
9524   {
9525     { VEX_W_TABLE (VEX_W_0F11_P_3) },
9526     { VEX_W_TABLE (VEX_W_0F11_P_3) },
9527   },
9528
9529   /* VEX_LEN_0F12_P_0_M_0 */
9530   {
9531     { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) },
9532   },
9533
9534   /* VEX_LEN_0F12_P_0_M_1 */
9535   {
9536     { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) },
9537   },
9538
9539   /* VEX_LEN_0F12_P_2 */
9540   {
9541     { VEX_W_TABLE (VEX_W_0F12_P_2) },
9542   },
9543
9544   /* VEX_LEN_0F13_M_0 */
9545   {
9546     { VEX_W_TABLE (VEX_W_0F13_M_0) },
9547   },
9548
9549   /* VEX_LEN_0F16_P_0_M_0 */
9550   {
9551     { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) },
9552   },
9553
9554   /* VEX_LEN_0F16_P_0_M_1 */
9555   {
9556     { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) },
9557   },
9558
9559   /* VEX_LEN_0F16_P_2 */
9560   {
9561     { VEX_W_TABLE (VEX_W_0F16_P_2) },
9562   },
9563
9564   /* VEX_LEN_0F17_M_0 */
9565   {
9566     { VEX_W_TABLE (VEX_W_0F17_M_0) },
9567   },
9568
9569   /* VEX_LEN_0F2A_P_1 */
9570   {
9571     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9572     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9573   },
9574
9575   /* VEX_LEN_0F2A_P_3 */
9576   {
9577     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9578     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9579   },
9580
9581   /* VEX_LEN_0F2C_P_1 */
9582   {
9583     { "vcvttss2si",     { Gv, EXdScalar }, 0 },
9584     { "vcvttss2si",     { Gv, EXdScalar }, 0 },
9585   },
9586
9587   /* VEX_LEN_0F2C_P_3 */
9588   {
9589     { "vcvttsd2si",     { Gv, EXqScalar }, 0 },
9590     { "vcvttsd2si",     { Gv, EXqScalar }, 0 },
9591   },
9592
9593   /* VEX_LEN_0F2D_P_1 */
9594   {
9595     { "vcvtss2si",      { Gv, EXdScalar }, 0 },
9596     { "vcvtss2si",      { Gv, EXdScalar }, 0 },
9597   },
9598
9599   /* VEX_LEN_0F2D_P_3 */
9600   {
9601     { "vcvtsd2si",      { Gv, EXqScalar }, 0 },
9602     { "vcvtsd2si",      { Gv, EXqScalar }, 0 },
9603   },
9604
9605   /* VEX_LEN_0F2E_P_0 */
9606   {
9607     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9608     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9609   },
9610
9611   /* VEX_LEN_0F2E_P_2 */
9612   {
9613     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9614     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9615   },
9616
9617   /* VEX_LEN_0F2F_P_0 */
9618   {
9619     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9620     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9621   },
9622
9623   /* VEX_LEN_0F2F_P_2 */
9624   {
9625     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9626     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9627   },
9628
9629   /* VEX_LEN_0F41_P_0 */
9630   {
9631     { Bad_Opcode },
9632     { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9633   },
9634   /* VEX_LEN_0F41_P_2 */
9635   {
9636     { Bad_Opcode },
9637     { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9638   },
9639   /* VEX_LEN_0F42_P_0 */
9640   {
9641     { Bad_Opcode },
9642     { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9643   },
9644   /* VEX_LEN_0F42_P_2 */
9645   {
9646     { Bad_Opcode },
9647     { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9648   },
9649   /* VEX_LEN_0F44_P_0 */
9650   {
9651     { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9652   },
9653   /* VEX_LEN_0F44_P_2 */
9654   {
9655     { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9656   },
9657   /* VEX_LEN_0F45_P_0 */
9658   {
9659     { Bad_Opcode },
9660     { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9661   },
9662   /* VEX_LEN_0F45_P_2 */
9663   {
9664     { Bad_Opcode },
9665     { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9666   },
9667   /* VEX_LEN_0F46_P_0 */
9668   {
9669     { Bad_Opcode },
9670     { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9671   },
9672   /* VEX_LEN_0F46_P_2 */
9673   {
9674     { Bad_Opcode },
9675     { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9676   },
9677   /* VEX_LEN_0F47_P_0 */
9678   {
9679     { Bad_Opcode },
9680     { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9681   },
9682   /* VEX_LEN_0F47_P_2 */
9683   {
9684     { Bad_Opcode },
9685     { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9686   },
9687   /* VEX_LEN_0F4A_P_0 */
9688   {
9689     { Bad_Opcode },
9690     { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9691   },
9692   /* VEX_LEN_0F4A_P_2 */
9693   {
9694     { Bad_Opcode },
9695     { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9696   },
9697   /* VEX_LEN_0F4B_P_0 */
9698   {
9699     { Bad_Opcode },
9700     { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9701   },
9702   /* VEX_LEN_0F4B_P_2 */
9703   {
9704     { Bad_Opcode },
9705     { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9706   },
9707
9708   /* VEX_LEN_0F51_P_1 */
9709   {
9710     { VEX_W_TABLE (VEX_W_0F51_P_1) },
9711     { VEX_W_TABLE (VEX_W_0F51_P_1) },
9712   },
9713
9714   /* VEX_LEN_0F51_P_3 */
9715   {
9716     { VEX_W_TABLE (VEX_W_0F51_P_3) },
9717     { VEX_W_TABLE (VEX_W_0F51_P_3) },
9718   },
9719
9720   /* VEX_LEN_0F52_P_1 */
9721   {
9722     { VEX_W_TABLE (VEX_W_0F52_P_1) },
9723     { VEX_W_TABLE (VEX_W_0F52_P_1) },
9724   },
9725
9726   /* VEX_LEN_0F53_P_1 */
9727   {
9728     { VEX_W_TABLE (VEX_W_0F53_P_1) },
9729     { VEX_W_TABLE (VEX_W_0F53_P_1) },
9730   },
9731
9732   /* VEX_LEN_0F58_P_1 */
9733   {
9734     { VEX_W_TABLE (VEX_W_0F58_P_1) },
9735     { VEX_W_TABLE (VEX_W_0F58_P_1) },
9736   },
9737
9738   /* VEX_LEN_0F58_P_3 */
9739   {
9740     { VEX_W_TABLE (VEX_W_0F58_P_3) },
9741     { VEX_W_TABLE (VEX_W_0F58_P_3) },
9742   },
9743
9744   /* VEX_LEN_0F59_P_1 */
9745   {
9746     { VEX_W_TABLE (VEX_W_0F59_P_1) },
9747     { VEX_W_TABLE (VEX_W_0F59_P_1) },
9748   },
9749
9750   /* VEX_LEN_0F59_P_3 */
9751   {
9752     { VEX_W_TABLE (VEX_W_0F59_P_3) },
9753     { VEX_W_TABLE (VEX_W_0F59_P_3) },
9754   },
9755
9756   /* VEX_LEN_0F5A_P_1 */
9757   {
9758     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9759     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9760   },
9761
9762   /* VEX_LEN_0F5A_P_3 */
9763   {
9764     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9765     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9766   },
9767
9768   /* VEX_LEN_0F5C_P_1 */
9769   {
9770     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9771     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9772   },
9773
9774   /* VEX_LEN_0F5C_P_3 */
9775   {
9776     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9777     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9778   },
9779
9780   /* VEX_LEN_0F5D_P_1 */
9781   {
9782     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9783     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9784   },
9785
9786   /* VEX_LEN_0F5D_P_3 */
9787   {
9788     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9789     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9790   },
9791
9792   /* VEX_LEN_0F5E_P_1 */
9793   {
9794     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9795     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9796   },
9797
9798   /* VEX_LEN_0F5E_P_3 */
9799   {
9800     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9801     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9802   },
9803
9804   /* VEX_LEN_0F5F_P_1 */
9805   {
9806     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9807     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9808   },
9809
9810   /* VEX_LEN_0F5F_P_3 */
9811   {
9812     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9813     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9814   },
9815
9816   /* VEX_LEN_0F6E_P_2 */
9817   {
9818     { "vmovK",          { XMScalar, Edq }, 0 },
9819     { "vmovK",          { XMScalar, Edq }, 0 },
9820   },
9821
9822   /* VEX_LEN_0F7E_P_1 */
9823   {
9824     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9825     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9826   },
9827
9828   /* VEX_LEN_0F7E_P_2 */
9829   {
9830     { "vmovK",          { Edq, XMScalar }, 0 },
9831     { "vmovK",          { Edq, XMScalar }, 0 },
9832   },
9833
9834   /* VEX_LEN_0F90_P_0 */
9835   {
9836     { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9837   },
9838
9839   /* VEX_LEN_0F90_P_2 */
9840   {
9841     { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9842   },
9843
9844   /* VEX_LEN_0F91_P_0 */
9845   {
9846     { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9847   },
9848
9849   /* VEX_LEN_0F91_P_2 */
9850   {
9851     { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
9852   },
9853
9854   /* VEX_LEN_0F92_P_0 */
9855   {
9856     { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9857   },
9858
9859   /* VEX_LEN_0F92_P_2 */
9860   {
9861     { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
9862   },
9863
9864   /* VEX_LEN_0F92_P_3 */
9865   {
9866     { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0) },
9867   },
9868
9869   /* VEX_LEN_0F93_P_0 */
9870   {
9871     { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9872   },
9873
9874   /* VEX_LEN_0F93_P_2 */
9875   {
9876     { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
9877   },
9878
9879   /* VEX_LEN_0F93_P_3 */
9880   {
9881     { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0) },
9882   },
9883
9884   /* VEX_LEN_0F98_P_0 */
9885   {
9886     { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9887   },
9888
9889   /* VEX_LEN_0F98_P_2 */
9890   {
9891     { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
9892   },
9893
9894   /* VEX_LEN_0F99_P_0 */
9895   {
9896     { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
9897   },
9898
9899   /* VEX_LEN_0F99_P_2 */
9900   {
9901     { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
9902   },
9903
9904   /* VEX_LEN_0FAE_R_2_M_0 */
9905   {
9906     { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) },
9907   },
9908
9909   /* VEX_LEN_0FAE_R_3_M_0 */
9910   {
9911     { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) },
9912   },
9913
9914   /* VEX_LEN_0FC2_P_1 */
9915   {
9916     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9917     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9918   },
9919
9920   /* VEX_LEN_0FC2_P_3 */
9921   {
9922     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9923     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9924   },
9925
9926   /* VEX_LEN_0FC4_P_2 */
9927   {
9928     { VEX_W_TABLE (VEX_W_0FC4_P_2) },
9929   },
9930
9931   /* VEX_LEN_0FC5_P_2 */
9932   {
9933     { VEX_W_TABLE (VEX_W_0FC5_P_2) },
9934   },
9935
9936   /* VEX_LEN_0FD6_P_2 */
9937   {
9938     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9939     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9940   },
9941
9942   /* VEX_LEN_0FF7_P_2 */
9943   {
9944     { VEX_W_TABLE (VEX_W_0FF7_P_2) },
9945   },
9946
9947   /* VEX_LEN_0F3816_P_2 */
9948   {
9949     { Bad_Opcode },
9950     { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9951   },
9952
9953   /* VEX_LEN_0F3819_P_2 */
9954   {
9955     { Bad_Opcode },
9956     { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9957   },
9958
9959   /* VEX_LEN_0F381A_P_2_M_0 */
9960   {
9961     { Bad_Opcode },
9962     { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9963   },
9964
9965   /* VEX_LEN_0F3836_P_2 */
9966   {
9967     { Bad_Opcode },
9968     { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9969   },
9970
9971   /* VEX_LEN_0F3841_P_2 */
9972   {
9973     { VEX_W_TABLE (VEX_W_0F3841_P_2) },
9974   },
9975
9976   /* VEX_LEN_0F385A_P_2_M_0 */
9977   {
9978     { Bad_Opcode },
9979     { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
9980   },
9981
9982   /* VEX_LEN_0F38DB_P_2 */
9983   {
9984     { VEX_W_TABLE (VEX_W_0F38DB_P_2) },
9985   },
9986
9987   /* VEX_LEN_0F38F2_P_0 */
9988   {
9989     { "andnS",          { Gdq, VexGdq, Edq }, 0 },
9990   },
9991
9992   /* VEX_LEN_0F38F3_R_1_P_0 */
9993   {
9994     { "blsrS",          { VexGdq, Edq }, 0 },
9995   },
9996
9997   /* VEX_LEN_0F38F3_R_2_P_0 */
9998   {
9999     { "blsmskS",        { VexGdq, Edq }, 0 },
10000   },
10001
10002   /* VEX_LEN_0F38F3_R_3_P_0 */
10003   {
10004     { "blsiS",          { VexGdq, Edq }, 0 },
10005   },
10006
10007   /* VEX_LEN_0F38F5_P_0 */
10008   {
10009     { "bzhiS",          { Gdq, Edq, VexGdq }, 0 },
10010   },
10011
10012   /* VEX_LEN_0F38F5_P_1 */
10013   {
10014     { "pextS",          { Gdq, VexGdq, Edq }, 0 },
10015   },
10016
10017   /* VEX_LEN_0F38F5_P_3 */
10018   {
10019     { "pdepS",          { Gdq, VexGdq, Edq }, 0 },
10020   },
10021
10022   /* VEX_LEN_0F38F6_P_3 */
10023   {
10024     { "mulxS",          { Gdq, VexGdq, Edq }, 0 },
10025   },
10026
10027   /* VEX_LEN_0F38F7_P_0 */
10028   {
10029     { "bextrS",         { Gdq, Edq, VexGdq }, 0 },
10030   },
10031
10032   /* VEX_LEN_0F38F7_P_1 */
10033   {
10034     { "sarxS",          { Gdq, Edq, VexGdq }, 0 },
10035   },
10036
10037   /* VEX_LEN_0F38F7_P_2 */
10038   {
10039     { "shlxS",          { Gdq, Edq, VexGdq }, 0 },
10040   },
10041
10042   /* VEX_LEN_0F38F7_P_3 */
10043   {
10044     { "shrxS",          { Gdq, Edq, VexGdq }, 0 },
10045   },
10046
10047   /* VEX_LEN_0F3A00_P_2 */
10048   {
10049     { Bad_Opcode },
10050     { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
10051   },
10052
10053   /* VEX_LEN_0F3A01_P_2 */
10054   {
10055     { Bad_Opcode },
10056     { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
10057   },
10058
10059   /* VEX_LEN_0F3A06_P_2 */
10060   {
10061     { Bad_Opcode },
10062     { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
10063   },
10064
10065   /* VEX_LEN_0F3A0A_P_2 */
10066   {
10067     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
10068     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
10069   },
10070
10071   /* VEX_LEN_0F3A0B_P_2 */
10072   {
10073     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
10074     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
10075   },
10076
10077   /* VEX_LEN_0F3A14_P_2 */
10078   {
10079     { VEX_W_TABLE (VEX_W_0F3A14_P_2) },
10080   },
10081
10082   /* VEX_LEN_0F3A15_P_2 */
10083   {
10084     { VEX_W_TABLE (VEX_W_0F3A15_P_2) },
10085   },
10086
10087   /* VEX_LEN_0F3A16_P_2  */
10088   {
10089     { "vpextrK",        { Edq, XM, Ib }, 0 },
10090   },
10091
10092   /* VEX_LEN_0F3A17_P_2 */
10093   {
10094     { "vextractps",     { Edqd, XM, Ib }, 0 },
10095   },
10096
10097   /* VEX_LEN_0F3A18_P_2 */
10098   {
10099     { Bad_Opcode },
10100     { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
10101   },
10102
10103   /* VEX_LEN_0F3A19_P_2 */
10104   {
10105     { Bad_Opcode },
10106     { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
10107   },
10108
10109   /* VEX_LEN_0F3A20_P_2 */
10110   {
10111     { VEX_W_TABLE (VEX_W_0F3A20_P_2) },
10112   },
10113
10114   /* VEX_LEN_0F3A21_P_2 */
10115   {
10116     { VEX_W_TABLE (VEX_W_0F3A21_P_2) },
10117   },
10118
10119   /* VEX_LEN_0F3A22_P_2 */
10120   {
10121     { "vpinsrK",        { XM, Vex128, Edq, Ib }, 0 },
10122   },
10123
10124   /* VEX_LEN_0F3A30_P_2 */
10125   {
10126     { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
10127   },
10128
10129   /* VEX_LEN_0F3A31_P_2 */
10130   {
10131     { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
10132   },
10133
10134   /* VEX_LEN_0F3A32_P_2 */
10135   {
10136     { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
10137   },
10138
10139   /* VEX_LEN_0F3A33_P_2 */
10140   {
10141     { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
10142   },
10143
10144   /* VEX_LEN_0F3A38_P_2 */
10145   {
10146     { Bad_Opcode },
10147     { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
10148   },
10149
10150   /* VEX_LEN_0F3A39_P_2 */
10151   {
10152     { Bad_Opcode },
10153     { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
10154   },
10155
10156   /* VEX_LEN_0F3A41_P_2 */
10157   {
10158     { VEX_W_TABLE (VEX_W_0F3A41_P_2) },
10159   },
10160
10161   /* VEX_LEN_0F3A46_P_2 */
10162   {
10163     { Bad_Opcode },
10164     { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
10165   },
10166
10167   /* VEX_LEN_0F3A60_P_2 */
10168   {
10169     { "vpcmpestrm",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
10170   },
10171
10172   /* VEX_LEN_0F3A61_P_2 */
10173   {
10174     { "vpcmpestri",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
10175   },
10176
10177   /* VEX_LEN_0F3A62_P_2 */
10178   {
10179     { VEX_W_TABLE (VEX_W_0F3A62_P_2) },
10180   },
10181
10182   /* VEX_LEN_0F3A63_P_2 */
10183   {
10184     { VEX_W_TABLE (VEX_W_0F3A63_P_2) },
10185   },
10186
10187   /* VEX_LEN_0F3A6A_P_2 */
10188   {
10189     { "vfmaddss",       { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
10190   },
10191
10192   /* VEX_LEN_0F3A6B_P_2 */
10193   {
10194     { "vfmaddsd",       { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
10195   },
10196
10197   /* VEX_LEN_0F3A6E_P_2 */
10198   {
10199     { "vfmsubss",       { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
10200   },
10201
10202   /* VEX_LEN_0F3A6F_P_2 */
10203   {
10204     { "vfmsubsd",       { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
10205   },
10206
10207   /* VEX_LEN_0F3A7A_P_2 */
10208   {
10209     { "vfnmaddss",      { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
10210   },
10211
10212   /* VEX_LEN_0F3A7B_P_2 */
10213   {
10214     { "vfnmaddsd",      { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
10215   },
10216
10217   /* VEX_LEN_0F3A7E_P_2 */
10218   {
10219     { "vfnmsubss",      { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
10220   },
10221
10222   /* VEX_LEN_0F3A7F_P_2 */
10223   {
10224     { "vfnmsubsd",      { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
10225   },
10226
10227   /* VEX_LEN_0F3ADF_P_2 */
10228   {
10229     { VEX_W_TABLE (VEX_W_0F3ADF_P_2) },
10230   },
10231
10232   /* VEX_LEN_0F3AF0_P_3 */
10233   {
10234     { "rorxS",          { Gdq, Edq, Ib }, 0 },
10235   },
10236
10237   /* VEX_LEN_0FXOP_08_CC */
10238   {
10239      { "vpcomb",        { XM, Vex128, EXx, VPCOM }, 0 },
10240   },
10241
10242   /* VEX_LEN_0FXOP_08_CD */
10243   {
10244      { "vpcomw",        { XM, Vex128, EXx, VPCOM }, 0 },
10245   },
10246
10247   /* VEX_LEN_0FXOP_08_CE */
10248   {
10249      { "vpcomd",        { XM, Vex128, EXx, VPCOM }, 0 },
10250   },
10251
10252   /* VEX_LEN_0FXOP_08_CF */
10253   {
10254      { "vpcomq",        { XM, Vex128, EXx, VPCOM }, 0 },
10255   },
10256
10257   /* VEX_LEN_0FXOP_08_EC */
10258   {
10259      { "vpcomub",       { XM, Vex128, EXx, VPCOM }, 0 },
10260   },
10261
10262   /* VEX_LEN_0FXOP_08_ED */
10263   {
10264      { "vpcomuw",       { XM, Vex128, EXx, VPCOM }, 0 },
10265   },
10266
10267   /* VEX_LEN_0FXOP_08_EE */
10268   {
10269      { "vpcomud",       { XM, Vex128, EXx, VPCOM }, 0 },
10270   },
10271
10272   /* VEX_LEN_0FXOP_08_EF */
10273   {
10274      { "vpcomuq",       { XM, Vex128, EXx, VPCOM }, 0 },
10275   },
10276
10277   /* VEX_LEN_0FXOP_09_80 */
10278   {
10279     { "vfrczps",        { XM, EXxmm }, 0 },
10280     { "vfrczps",        { XM, EXymmq }, 0 },
10281   },
10282
10283   /* VEX_LEN_0FXOP_09_81 */
10284   {
10285     { "vfrczpd",        { XM, EXxmm }, 0 },
10286     { "vfrczpd",        { XM, EXymmq }, 0 },
10287   },
10288 };
10289
10290 static const struct dis386 vex_w_table[][2] = {
10291   {
10292     /* VEX_W_0F10_P_0 */
10293     { "vmovups",        { XM, EXx }, 0 },
10294   },
10295   {
10296     /* VEX_W_0F10_P_1 */
10297     { "vmovss",         { XMVexScalar, VexScalar, EXdScalar }, 0 },
10298   },
10299   {
10300     /* VEX_W_0F10_P_2 */
10301     { "vmovupd",        { XM, EXx }, 0 },
10302   },
10303   {
10304     /* VEX_W_0F10_P_3 */
10305     { "vmovsd",         { XMVexScalar, VexScalar, EXqScalar }, 0 },
10306   },
10307   {
10308     /* VEX_W_0F11_P_0 */
10309     { "vmovups",        { EXxS, XM }, 0 },
10310   },
10311   {
10312     /* VEX_W_0F11_P_1 */
10313     { "vmovss",         { EXdVexScalarS, VexScalar, XMScalar }, 0 },
10314   },
10315   {
10316     /* VEX_W_0F11_P_2 */
10317     { "vmovupd",        { EXxS, XM }, 0 },
10318   },
10319   {
10320     /* VEX_W_0F11_P_3 */
10321     { "vmovsd",         { EXqVexScalarS, VexScalar, XMScalar }, 0 },
10322   },
10323   {
10324     /* VEX_W_0F12_P_0_M_0 */
10325     { "vmovlps",        { XM, Vex128, EXq }, 0 },
10326   },
10327   {
10328     /* VEX_W_0F12_P_0_M_1 */
10329     { "vmovhlps",       { XM, Vex128, EXq }, 0 },
10330   },
10331   {
10332     /* VEX_W_0F12_P_1 */
10333     { "vmovsldup",      { XM, EXx }, 0 },
10334   },
10335   {
10336     /* VEX_W_0F12_P_2 */
10337     { "vmovlpd",        { XM, Vex128, EXq }, 0 },
10338   },
10339   {
10340     /* VEX_W_0F12_P_3 */
10341     { "vmovddup",       { XM, EXymmq }, 0 },
10342   },
10343   {
10344     /* VEX_W_0F13_M_0 */
10345     { "vmovlpX",        { EXq, XM }, 0 },
10346   },
10347   {
10348     /* VEX_W_0F14 */
10349     { "vunpcklpX",      { XM, Vex, EXx }, 0 },
10350   },
10351   {
10352     /* VEX_W_0F15 */
10353     { "vunpckhpX",      { XM, Vex, EXx }, 0 },
10354   },
10355   {
10356     /* VEX_W_0F16_P_0_M_0 */
10357     { "vmovhps",        { XM, Vex128, EXq }, 0 },
10358   },
10359   {
10360     /* VEX_W_0F16_P_0_M_1 */
10361     { "vmovlhps",       { XM, Vex128, EXq }, 0 },
10362   },
10363   {
10364     /* VEX_W_0F16_P_1 */
10365     { "vmovshdup",      { XM, EXx }, 0 },
10366   },
10367   {
10368     /* VEX_W_0F16_P_2 */
10369     { "vmovhpd",        { XM, Vex128, EXq }, 0 },
10370   },
10371   {
10372     /* VEX_W_0F17_M_0 */
10373     { "vmovhpX",        { EXq, XM }, 0 },
10374   },
10375   {
10376     /* VEX_W_0F28 */
10377     { "vmovapX",        { XM, EXx }, 0 },
10378   },
10379   {
10380     /* VEX_W_0F29 */
10381     { "vmovapX",        { EXxS, XM }, 0 },
10382   },
10383   {
10384     /* VEX_W_0F2B_M_0 */
10385     { "vmovntpX",       { Mx, XM }, 0 },
10386   },
10387   {
10388     /* VEX_W_0F2E_P_0 */
10389     { "vucomiss",       { XMScalar, EXdScalar }, 0 },
10390   },
10391   {
10392     /* VEX_W_0F2E_P_2 */
10393     { "vucomisd",       { XMScalar, EXqScalar }, 0 },
10394   },
10395   {
10396     /* VEX_W_0F2F_P_0 */
10397     { "vcomiss",        { XMScalar, EXdScalar }, 0 },
10398   },
10399   {
10400     /* VEX_W_0F2F_P_2 */
10401     { "vcomisd",        { XMScalar, EXqScalar }, 0 },
10402   },
10403   {
10404     /* VEX_W_0F41_P_0_LEN_1 */
10405     { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
10406     { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) },
10407   },
10408   {
10409     /* VEX_W_0F41_P_2_LEN_1 */
10410     { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) },
10411     { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) }
10412   },
10413   {
10414     /* VEX_W_0F42_P_0_LEN_1 */
10415     { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) },
10416     { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) },
10417   },
10418   {
10419     /* VEX_W_0F42_P_2_LEN_1 */
10420     { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) },
10421     { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) },
10422   },
10423   {
10424     /* VEX_W_0F44_P_0_LEN_0 */
10425     { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) },
10426     { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) },
10427   },
10428   {
10429     /* VEX_W_0F44_P_2_LEN_0 */
10430     { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) },
10431     { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) },
10432   },
10433   {
10434     /* VEX_W_0F45_P_0_LEN_1 */
10435     { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) },
10436     { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) },
10437   },
10438   {
10439     /* VEX_W_0F45_P_2_LEN_1 */
10440     { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) },
10441     { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) },
10442   },
10443   {
10444     /* VEX_W_0F46_P_0_LEN_1 */
10445     { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) },
10446     { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) },
10447   },
10448   {
10449     /* VEX_W_0F46_P_2_LEN_1 */
10450     { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) },
10451     { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) },
10452   },
10453   {
10454     /* VEX_W_0F47_P_0_LEN_1 */
10455     { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) },
10456     { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) },
10457   },
10458   {
10459     /* VEX_W_0F47_P_2_LEN_1 */
10460     { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) },
10461     { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) },
10462   },
10463   {
10464     /* VEX_W_0F4A_P_0_LEN_1 */
10465     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) },
10466     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) },
10467   },
10468   {
10469     /* VEX_W_0F4A_P_2_LEN_1 */
10470     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) },
10471     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) },
10472   },
10473   {
10474     /* VEX_W_0F4B_P_0_LEN_1 */
10475     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) },
10476     { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) },
10477   },
10478   {
10479     /* VEX_W_0F4B_P_2_LEN_1 */
10480     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
10481   },
10482   {
10483     /* VEX_W_0F50_M_0 */
10484     { "vmovmskpX",      { Gdq, XS }, 0 },
10485   },
10486   {
10487     /* VEX_W_0F51_P_0 */
10488     { "vsqrtps",        { XM, EXx }, 0 },
10489   },
10490   {
10491     /* VEX_W_0F51_P_1 */
10492     { "vsqrtss",        { XMScalar, VexScalar, EXdScalar }, 0 },
10493   },
10494   {
10495     /* VEX_W_0F51_P_2  */
10496     { "vsqrtpd",        { XM, EXx }, 0 },
10497   },
10498   {
10499     /* VEX_W_0F51_P_3 */
10500     { "vsqrtsd",        { XMScalar, VexScalar, EXqScalar }, 0 },
10501   },
10502   {
10503     /* VEX_W_0F52_P_0 */
10504     { "vrsqrtps",       { XM, EXx }, 0 },
10505   },
10506   {
10507     /* VEX_W_0F52_P_1 */
10508     { "vrsqrtss",       { XMScalar, VexScalar, EXdScalar }, 0 },
10509   },
10510   {
10511     /* VEX_W_0F53_P_0  */
10512     { "vrcpps",         { XM, EXx }, 0 },
10513   },
10514   {
10515     /* VEX_W_0F53_P_1  */
10516     { "vrcpss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10517   },
10518   {
10519     /* VEX_W_0F58_P_0  */
10520     { "vaddps",         { XM, Vex, EXx }, 0 },
10521   },
10522   {
10523     /* VEX_W_0F58_P_1  */
10524     { "vaddss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10525   },
10526   {
10527     /* VEX_W_0F58_P_2  */
10528     { "vaddpd",         { XM, Vex, EXx }, 0 },
10529   },
10530   {
10531     /* VEX_W_0F58_P_3  */
10532     { "vaddsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10533   },
10534   {
10535     /* VEX_W_0F59_P_0  */
10536     { "vmulps",         { XM, Vex, EXx }, 0 },
10537   },
10538   {
10539     /* VEX_W_0F59_P_1  */
10540     { "vmulss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10541   },
10542   {
10543     /* VEX_W_0F59_P_2  */
10544     { "vmulpd",         { XM, Vex, EXx }, 0 },
10545   },
10546   {
10547     /* VEX_W_0F59_P_3  */
10548     { "vmulsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10549   },
10550   {
10551     /* VEX_W_0F5A_P_0  */
10552     { "vcvtps2pd",      { XM, EXxmmq }, 0 },
10553   },
10554   {
10555     /* VEX_W_0F5A_P_1  */
10556     { "vcvtss2sd",      { XMScalar, VexScalar, EXdScalar }, 0 },
10557   },
10558   {
10559     /* VEX_W_0F5A_P_3  */
10560     { "vcvtsd2ss",      { XMScalar, VexScalar, EXqScalar }, 0 },
10561   },
10562   {
10563     /* VEX_W_0F5B_P_0  */
10564     { "vcvtdq2ps",      { XM, EXx }, 0 },
10565   },
10566   {
10567     /* VEX_W_0F5B_P_1  */
10568     { "vcvttps2dq",     { XM, EXx }, 0 },
10569   },
10570   {
10571     /* VEX_W_0F5B_P_2  */
10572     { "vcvtps2dq",      { XM, EXx }, 0 },
10573   },
10574   {
10575     /* VEX_W_0F5C_P_0  */
10576     { "vsubps",         { XM, Vex, EXx }, 0 },
10577   },
10578   {
10579     /* VEX_W_0F5C_P_1  */
10580     { "vsubss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10581   },
10582   {
10583     /* VEX_W_0F5C_P_2  */
10584     { "vsubpd",         { XM, Vex, EXx }, 0 },
10585   },
10586   {
10587     /* VEX_W_0F5C_P_3  */
10588     { "vsubsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10589   },
10590   {
10591     /* VEX_W_0F5D_P_0  */
10592     { "vminps",         { XM, Vex, EXx }, 0 },
10593   },
10594   {
10595     /* VEX_W_0F5D_P_1  */
10596     { "vminss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10597   },
10598   {
10599     /* VEX_W_0F5D_P_2  */
10600     { "vminpd",         { XM, Vex, EXx }, 0 },
10601   },
10602   {
10603     /* VEX_W_0F5D_P_3  */
10604     { "vminsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10605   },
10606   {
10607     /* VEX_W_0F5E_P_0  */
10608     { "vdivps",         { XM, Vex, EXx }, 0 },
10609   },
10610   {
10611     /* VEX_W_0F5E_P_1  */
10612     { "vdivss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10613   },
10614   {
10615     /* VEX_W_0F5E_P_2  */
10616     { "vdivpd",         { XM, Vex, EXx }, 0 },
10617   },
10618   {
10619     /* VEX_W_0F5E_P_3  */
10620     { "vdivsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10621   },
10622   {
10623     /* VEX_W_0F5F_P_0  */
10624     { "vmaxps",         { XM, Vex, EXx }, 0 },
10625   },
10626   {
10627     /* VEX_W_0F5F_P_1  */
10628     { "vmaxss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10629   },
10630   {
10631     /* VEX_W_0F5F_P_2  */
10632     { "vmaxpd",         { XM, Vex, EXx }, 0 },
10633   },
10634   {
10635     /* VEX_W_0F5F_P_3  */
10636     { "vmaxsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10637   },
10638   {
10639     /* VEX_W_0F60_P_2  */
10640     { "vpunpcklbw",     { XM, Vex, EXx }, 0 },
10641   },
10642   {
10643     /* VEX_W_0F61_P_2  */
10644     { "vpunpcklwd",     { XM, Vex, EXx }, 0 },
10645   },
10646   {
10647     /* VEX_W_0F62_P_2  */
10648     { "vpunpckldq",     { XM, Vex, EXx }, 0 },
10649   },
10650   {
10651     /* VEX_W_0F63_P_2  */
10652     { "vpacksswb",      { XM, Vex, EXx }, 0 },
10653   },
10654   {
10655     /* VEX_W_0F64_P_2  */
10656     { "vpcmpgtb",       { XM, Vex, EXx }, 0 },
10657   },
10658   {
10659     /* VEX_W_0F65_P_2  */
10660     { "vpcmpgtw",       { XM, Vex, EXx }, 0 },
10661   },
10662   {
10663     /* VEX_W_0F66_P_2  */
10664     { "vpcmpgtd",       { XM, Vex, EXx }, 0 },
10665   },
10666   {
10667     /* VEX_W_0F67_P_2  */
10668     { "vpackuswb",      { XM, Vex, EXx }, 0 },
10669   },
10670   {
10671     /* VEX_W_0F68_P_2  */
10672     { "vpunpckhbw",     { XM, Vex, EXx }, 0 },
10673   },
10674   {
10675     /* VEX_W_0F69_P_2  */
10676     { "vpunpckhwd",     { XM, Vex, EXx }, 0 },
10677   },
10678   {
10679     /* VEX_W_0F6A_P_2  */
10680     { "vpunpckhdq",     { XM, Vex, EXx }, 0 },
10681   },
10682   {
10683     /* VEX_W_0F6B_P_2  */
10684     { "vpackssdw",      { XM, Vex, EXx }, 0 },
10685   },
10686   {
10687     /* VEX_W_0F6C_P_2  */
10688     { "vpunpcklqdq",    { XM, Vex, EXx }, 0 },
10689   },
10690   {
10691     /* VEX_W_0F6D_P_2  */
10692     { "vpunpckhqdq",    { XM, Vex, EXx }, 0 },
10693   },
10694   {
10695     /* VEX_W_0F6F_P_1  */
10696     { "vmovdqu",        { XM, EXx }, 0 },
10697   },
10698   {
10699     /* VEX_W_0F6F_P_2  */
10700     { "vmovdqa",        { XM, EXx }, 0 },
10701   },
10702   {
10703     /* VEX_W_0F70_P_1 */
10704     { "vpshufhw",       { XM, EXx, Ib }, 0 },
10705   },
10706   {
10707     /* VEX_W_0F70_P_2 */
10708     { "vpshufd",        { XM, EXx, Ib }, 0 },
10709   },
10710   {
10711     /* VEX_W_0F70_P_3 */
10712     { "vpshuflw",       { XM, EXx, Ib }, 0 },
10713   },
10714   {
10715     /* VEX_W_0F71_R_2_P_2  */
10716     { "vpsrlw",         { Vex, XS, Ib }, 0 },
10717   },
10718   {
10719     /* VEX_W_0F71_R_4_P_2  */
10720     { "vpsraw",         { Vex, XS, Ib }, 0 },
10721   },
10722   {
10723     /* VEX_W_0F71_R_6_P_2  */
10724     { "vpsllw",         { Vex, XS, Ib }, 0 },
10725   },
10726   {
10727     /* VEX_W_0F72_R_2_P_2  */
10728     { "vpsrld",         { Vex, XS, Ib }, 0 },
10729   },
10730   {
10731     /* VEX_W_0F72_R_4_P_2  */
10732     { "vpsrad",         { Vex, XS, Ib }, 0 },
10733   },
10734   {
10735     /* VEX_W_0F72_R_6_P_2  */
10736     { "vpslld",         { Vex, XS, Ib }, 0 },
10737   },
10738   {
10739     /* VEX_W_0F73_R_2_P_2  */
10740     { "vpsrlq",         { Vex, XS, Ib }, 0 },
10741   },
10742   {
10743     /* VEX_W_0F73_R_3_P_2  */
10744     { "vpsrldq",        { Vex, XS, Ib }, 0 },
10745   },
10746   {
10747     /* VEX_W_0F73_R_6_P_2  */
10748     { "vpsllq",         { Vex, XS, Ib }, 0 },
10749   },
10750   {
10751     /* VEX_W_0F73_R_7_P_2  */
10752     { "vpslldq",        { Vex, XS, Ib }, 0 },
10753   },
10754   {
10755     /* VEX_W_0F74_P_2 */
10756     { "vpcmpeqb",       { XM, Vex, EXx }, 0 },
10757   },
10758   {
10759     /* VEX_W_0F75_P_2 */
10760     { "vpcmpeqw",       { XM, Vex, EXx }, 0 },
10761   },
10762   {
10763     /* VEX_W_0F76_P_2 */
10764     { "vpcmpeqd",       { XM, Vex, EXx }, 0 },
10765   },
10766   {
10767     /* VEX_W_0F77_P_0 */
10768     { "",               { VZERO }, 0 },
10769   },
10770   {
10771     /* VEX_W_0F7C_P_2 */
10772     { "vhaddpd",        { XM, Vex, EXx }, 0 },
10773   },
10774   {
10775     /* VEX_W_0F7C_P_3 */
10776     { "vhaddps",        { XM, Vex, EXx }, 0 },
10777   },
10778   {
10779     /* VEX_W_0F7D_P_2 */
10780     { "vhsubpd",        { XM, Vex, EXx }, 0 },
10781   },
10782   {
10783     /* VEX_W_0F7D_P_3 */
10784     { "vhsubps",        { XM, Vex, EXx }, 0 },
10785   },
10786   {
10787     /* VEX_W_0F7E_P_1 */
10788     { "vmovq",          { XMScalar, EXqScalar }, 0 },
10789   },
10790   {
10791     /* VEX_W_0F7F_P_1 */
10792     { "vmovdqu",        { EXxS, XM }, 0 },
10793   },
10794   {
10795     /* VEX_W_0F7F_P_2 */
10796     { "vmovdqa",        { EXxS, XM }, 0 },
10797   },
10798   {
10799     /* VEX_W_0F90_P_0_LEN_0 */
10800     { "kmovw",          { MaskG, MaskE }, 0 },
10801     { "kmovq",          { MaskG, MaskE }, 0 },
10802   },
10803   {
10804     /* VEX_W_0F90_P_2_LEN_0 */
10805     { "kmovb",          { MaskG, MaskBDE }, 0 },
10806     { "kmovd",          { MaskG, MaskBDE }, 0 },
10807   },
10808   {
10809     /* VEX_W_0F91_P_0_LEN_0 */
10810     { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
10811     { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
10812   },
10813   {
10814     /* VEX_W_0F91_P_2_LEN_0 */
10815     { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
10816     { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
10817   },
10818   {
10819     /* VEX_W_0F92_P_0_LEN_0 */
10820     { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
10821   },
10822   {
10823     /* VEX_W_0F92_P_2_LEN_0 */
10824     { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
10825   },
10826   {
10827     /* VEX_W_0F92_P_3_LEN_0 */
10828     { MOD_TABLE (MOD_VEX_W_0_0F92_P_3_LEN_0) },
10829     { MOD_TABLE (MOD_VEX_W_1_0F92_P_3_LEN_0) },
10830   },
10831   {
10832     /* VEX_W_0F93_P_0_LEN_0 */
10833     { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
10834   },
10835   {
10836     /* VEX_W_0F93_P_2_LEN_0 */
10837     { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
10838   },
10839   {
10840     /* VEX_W_0F93_P_3_LEN_0 */
10841     { MOD_TABLE (MOD_VEX_W_0_0F93_P_3_LEN_0) },
10842     { MOD_TABLE (MOD_VEX_W_1_0F93_P_3_LEN_0) },
10843   },
10844   {
10845     /* VEX_W_0F98_P_0_LEN_0 */
10846     { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
10847     { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
10848   },
10849   {
10850     /* VEX_W_0F98_P_2_LEN_0 */
10851     { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
10852     { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
10853   },
10854   {
10855     /* VEX_W_0F99_P_0_LEN_0 */
10856     { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
10857     { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
10858   },
10859   {
10860     /* VEX_W_0F99_P_2_LEN_0 */
10861     { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
10862     { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
10863   },
10864   {
10865     /* VEX_W_0FAE_R_2_M_0 */
10866     { "vldmxcsr",       { Md }, 0 },
10867   },
10868   {
10869     /* VEX_W_0FAE_R_3_M_0 */
10870     { "vstmxcsr",       { Md }, 0 },
10871   },
10872   {
10873     /* VEX_W_0FC2_P_0 */
10874     { "vcmpps",         { XM, Vex, EXx, VCMP }, 0 },
10875   },
10876   {
10877     /* VEX_W_0FC2_P_1 */
10878     { "vcmpss",         { XMScalar, VexScalar, EXdScalar, VCMP }, 0 },
10879   },
10880   {
10881     /* VEX_W_0FC2_P_2 */
10882     { "vcmppd",         { XM, Vex, EXx, VCMP }, 0 },
10883   },
10884   {
10885     /* VEX_W_0FC2_P_3 */
10886     { "vcmpsd",         { XMScalar, VexScalar, EXqScalar, VCMP }, 0 },
10887   },
10888   {
10889     /* VEX_W_0FC4_P_2 */
10890     { "vpinsrw",        { XM, Vex128, Edqw, Ib }, 0 },
10891   },
10892   {
10893     /* VEX_W_0FC5_P_2 */
10894     { "vpextrw",        { Gdq, XS, Ib }, 0 },
10895   },
10896   {
10897     /* VEX_W_0FD0_P_2 */
10898     { "vaddsubpd",      { XM, Vex, EXx }, 0 },
10899   },
10900   {
10901     /* VEX_W_0FD0_P_3 */
10902     { "vaddsubps",      { XM, Vex, EXx }, 0 },
10903   },
10904   {
10905     /* VEX_W_0FD1_P_2 */
10906     { "vpsrlw",         { XM, Vex, EXxmm }, 0 },
10907   },
10908   {
10909     /* VEX_W_0FD2_P_2 */
10910     { "vpsrld",         { XM, Vex, EXxmm }, 0 },
10911   },
10912   {
10913     /* VEX_W_0FD3_P_2 */
10914     { "vpsrlq",         { XM, Vex, EXxmm }, 0 },
10915   },
10916   {
10917     /* VEX_W_0FD4_P_2 */
10918     { "vpaddq",         { XM, Vex, EXx }, 0 },
10919   },
10920   {
10921     /* VEX_W_0FD5_P_2 */
10922     { "vpmullw",        { XM, Vex, EXx }, 0 },
10923   },
10924   {
10925     /* VEX_W_0FD6_P_2 */
10926     { "vmovq",          { EXqScalarS, XMScalar }, 0 },
10927   },
10928   {
10929     /* VEX_W_0FD7_P_2_M_1 */
10930     { "vpmovmskb",      { Gdq, XS }, 0 },
10931   },
10932   {
10933     /* VEX_W_0FD8_P_2 */
10934     { "vpsubusb",       { XM, Vex, EXx }, 0 },
10935   },
10936   {
10937     /* VEX_W_0FD9_P_2 */
10938     { "vpsubusw",       { XM, Vex, EXx }, 0 },
10939   },
10940   {
10941     /* VEX_W_0FDA_P_2 */
10942     { "vpminub",        { XM, Vex, EXx }, 0 },
10943   },
10944   {
10945     /* VEX_W_0FDB_P_2 */
10946     { "vpand",          { XM, Vex, EXx }, 0 },
10947   },
10948   {
10949     /* VEX_W_0FDC_P_2 */
10950     { "vpaddusb",       { XM, Vex, EXx }, 0 },
10951   },
10952   {
10953     /* VEX_W_0FDD_P_2 */
10954     { "vpaddusw",       { XM, Vex, EXx }, 0 },
10955   },
10956   {
10957     /* VEX_W_0FDE_P_2 */
10958     { "vpmaxub",        { XM, Vex, EXx }, 0 },
10959   },
10960   {
10961     /* VEX_W_0FDF_P_2 */
10962     { "vpandn",         { XM, Vex, EXx }, 0 },
10963   },
10964   {
10965     /* VEX_W_0FE0_P_2  */
10966     { "vpavgb",         { XM, Vex, EXx }, 0 },
10967   },
10968   {
10969     /* VEX_W_0FE1_P_2  */
10970     { "vpsraw",         { XM, Vex, EXxmm }, 0 },
10971   },
10972   {
10973     /* VEX_W_0FE2_P_2  */
10974     { "vpsrad",         { XM, Vex, EXxmm }, 0 },
10975   },
10976   {
10977     /* VEX_W_0FE3_P_2  */
10978     { "vpavgw",         { XM, Vex, EXx }, 0 },
10979   },
10980   {
10981     /* VEX_W_0FE4_P_2  */
10982     { "vpmulhuw",       { XM, Vex, EXx }, 0 },
10983   },
10984   {
10985     /* VEX_W_0FE5_P_2  */
10986     { "vpmulhw",        { XM, Vex, EXx }, 0 },
10987   },
10988   {
10989     /* VEX_W_0FE6_P_1  */
10990     { "vcvtdq2pd",      { XM, EXxmmq }, 0 },
10991   },
10992   {
10993     /* VEX_W_0FE6_P_2  */
10994     { "vcvttpd2dq%XY",  { XMM, EXx }, 0 },
10995   },
10996   {
10997     /* VEX_W_0FE6_P_3  */
10998     { "vcvtpd2dq%XY",   { XMM, EXx }, 0 },
10999   },
11000   {
11001     /* VEX_W_0FE7_P_2_M_0 */
11002     { "vmovntdq",       { Mx, XM }, 0 },
11003   },
11004   {
11005     /* VEX_W_0FE8_P_2  */
11006     { "vpsubsb",        { XM, Vex, EXx }, 0 },
11007   },
11008   {
11009     /* VEX_W_0FE9_P_2  */
11010     { "vpsubsw",        { XM, Vex, EXx }, 0 },
11011   },
11012   {
11013     /* VEX_W_0FEA_P_2  */
11014     { "vpminsw",        { XM, Vex, EXx }, 0 },
11015   },
11016   {
11017     /* VEX_W_0FEB_P_2  */
11018     { "vpor",           { XM, Vex, EXx }, 0 },
11019   },
11020   {
11021     /* VEX_W_0FEC_P_2  */
11022     { "vpaddsb",        { XM, Vex, EXx }, 0 },
11023   },
11024   {
11025     /* VEX_W_0FED_P_2  */
11026     { "vpaddsw",        { XM, Vex, EXx }, 0 },
11027   },
11028   {
11029     /* VEX_W_0FEE_P_2  */
11030     { "vpmaxsw",        { XM, Vex, EXx }, 0 },
11031   },
11032   {
11033     /* VEX_W_0FEF_P_2  */
11034     { "vpxor",          { XM, Vex, EXx }, 0 },
11035   },
11036   {
11037     /* VEX_W_0FF0_P_3_M_0 */
11038     { "vlddqu",         { XM, M }, 0 },
11039   },
11040   {
11041     /* VEX_W_0FF1_P_2 */
11042     { "vpsllw",         { XM, Vex, EXxmm }, 0 },
11043   },
11044   {
11045     /* VEX_W_0FF2_P_2 */
11046     { "vpslld",         { XM, Vex, EXxmm }, 0 },
11047   },
11048   {
11049     /* VEX_W_0FF3_P_2 */
11050     { "vpsllq",         { XM, Vex, EXxmm }, 0 },
11051   },
11052   {
11053     /* VEX_W_0FF4_P_2 */
11054     { "vpmuludq",       { XM, Vex, EXx }, 0 },
11055   },
11056   {
11057     /* VEX_W_0FF5_P_2 */
11058     { "vpmaddwd",       { XM, Vex, EXx }, 0 },
11059   },
11060   {
11061     /* VEX_W_0FF6_P_2 */
11062     { "vpsadbw",        { XM, Vex, EXx }, 0 },
11063   },
11064   {
11065     /* VEX_W_0FF7_P_2 */
11066     { "vmaskmovdqu",    { XM, XS }, 0 },
11067   },
11068   {
11069     /* VEX_W_0FF8_P_2 */
11070     { "vpsubb",         { XM, Vex, EXx }, 0 },
11071   },
11072   {
11073     /* VEX_W_0FF9_P_2 */
11074     { "vpsubw",         { XM, Vex, EXx }, 0 },
11075   },
11076   {
11077     /* VEX_W_0FFA_P_2 */
11078     { "vpsubd",         { XM, Vex, EXx }, 0 },
11079   },
11080   {
11081     /* VEX_W_0FFB_P_2 */
11082     { "vpsubq",         { XM, Vex, EXx }, 0 },
11083   },
11084   {
11085     /* VEX_W_0FFC_P_2 */
11086     { "vpaddb",         { XM, Vex, EXx }, 0 },
11087   },
11088   {
11089     /* VEX_W_0FFD_P_2 */
11090     { "vpaddw",         { XM, Vex, EXx }, 0 },
11091   },
11092   {
11093     /* VEX_W_0FFE_P_2 */
11094     { "vpaddd",         { XM, Vex, EXx }, 0 },
11095   },
11096   {
11097     /* VEX_W_0F3800_P_2  */
11098     { "vpshufb",        { XM, Vex, EXx }, 0 },
11099   },
11100   {
11101     /* VEX_W_0F3801_P_2  */
11102     { "vphaddw",        { XM, Vex, EXx }, 0 },
11103   },
11104   {
11105     /* VEX_W_0F3802_P_2  */
11106     { "vphaddd",        { XM, Vex, EXx }, 0 },
11107   },
11108   {
11109     /* VEX_W_0F3803_P_2  */
11110     { "vphaddsw",       { XM, Vex, EXx }, 0 },
11111   },
11112   {
11113     /* VEX_W_0F3804_P_2  */
11114     { "vpmaddubsw",     { XM, Vex, EXx }, 0 },
11115   },
11116   {
11117     /* VEX_W_0F3805_P_2  */
11118     { "vphsubw",        { XM, Vex, EXx }, 0 },
11119   },
11120   {
11121     /* VEX_W_0F3806_P_2  */
11122     { "vphsubd",        { XM, Vex, EXx }, 0 },
11123   },
11124   {
11125     /* VEX_W_0F3807_P_2  */
11126     { "vphsubsw",       { XM, Vex, EXx }, 0 },
11127   },
11128   {
11129     /* VEX_W_0F3808_P_2  */
11130     { "vpsignb",        { XM, Vex, EXx }, 0 },
11131   },
11132   {
11133     /* VEX_W_0F3809_P_2  */
11134     { "vpsignw",        { XM, Vex, EXx }, 0 },
11135   },
11136   {
11137     /* VEX_W_0F380A_P_2  */
11138     { "vpsignd",        { XM, Vex, EXx }, 0 },
11139   },
11140   {
11141     /* VEX_W_0F380B_P_2  */
11142     { "vpmulhrsw",      { XM, Vex, EXx }, 0 },
11143   },
11144   {
11145     /* VEX_W_0F380C_P_2  */
11146     { "vpermilps",      { XM, Vex, EXx }, 0 },
11147   },
11148   {
11149     /* VEX_W_0F380D_P_2  */
11150     { "vpermilpd",      { XM, Vex, EXx }, 0 },
11151   },
11152   {
11153     /* VEX_W_0F380E_P_2  */
11154     { "vtestps",        { XM, EXx }, 0 },
11155   },
11156   {
11157     /* VEX_W_0F380F_P_2  */
11158     { "vtestpd",        { XM, EXx }, 0 },
11159   },
11160   {
11161     /* VEX_W_0F3816_P_2  */
11162     { "vpermps",        { XM, Vex, EXx }, 0 },
11163   },
11164   {
11165     /* VEX_W_0F3817_P_2 */
11166     { "vptest",         { XM, EXx }, 0 },
11167   },
11168   {
11169     /* VEX_W_0F3818_P_2 */
11170     { "vbroadcastss",   { XM, EXxmm_md }, 0 },
11171   },
11172   {
11173     /* VEX_W_0F3819_P_2 */
11174     { "vbroadcastsd",   { XM, EXxmm_mq }, 0 },
11175   },
11176   {
11177     /* VEX_W_0F381A_P_2_M_0 */
11178     { "vbroadcastf128", { XM, Mxmm }, 0 },
11179   },
11180   {
11181     /* VEX_W_0F381C_P_2 */
11182     { "vpabsb",         { XM, EXx }, 0 },
11183   },
11184   {
11185     /* VEX_W_0F381D_P_2 */
11186     { "vpabsw",         { XM, EXx }, 0 },
11187   },
11188   {
11189     /* VEX_W_0F381E_P_2 */
11190     { "vpabsd",         { XM, EXx }, 0 },
11191   },
11192   {
11193     /* VEX_W_0F3820_P_2 */
11194     { "vpmovsxbw",      { XM, EXxmmq }, 0 },
11195   },
11196   {
11197     /* VEX_W_0F3821_P_2 */
11198     { "vpmovsxbd",      { XM, EXxmmqd }, 0 },
11199   },
11200   {
11201     /* VEX_W_0F3822_P_2 */
11202     { "vpmovsxbq",      { XM, EXxmmdw }, 0 },
11203   },
11204   {
11205     /* VEX_W_0F3823_P_2 */
11206     { "vpmovsxwd",      { XM, EXxmmq }, 0 },
11207   },
11208   {
11209     /* VEX_W_0F3824_P_2 */
11210     { "vpmovsxwq",      { XM, EXxmmqd }, 0 },
11211   },
11212   {
11213     /* VEX_W_0F3825_P_2 */
11214     { "vpmovsxdq",      { XM, EXxmmq }, 0 },
11215   },
11216   {
11217     /* VEX_W_0F3828_P_2 */
11218     { "vpmuldq",        { XM, Vex, EXx }, 0 },
11219   },
11220   {
11221     /* VEX_W_0F3829_P_2 */
11222     { "vpcmpeqq",       { XM, Vex, EXx }, 0 },
11223   },
11224   {
11225     /* VEX_W_0F382A_P_2_M_0 */
11226     { "vmovntdqa",      { XM, Mx }, 0 },
11227   },
11228   {
11229     /* VEX_W_0F382B_P_2 */
11230     { "vpackusdw",      { XM, Vex, EXx }, 0 },
11231   },
11232   {
11233     /* VEX_W_0F382C_P_2_M_0 */
11234     { "vmaskmovps",     { XM, Vex, Mx }, 0 },
11235   },
11236   {
11237     /* VEX_W_0F382D_P_2_M_0 */
11238     { "vmaskmovpd",     { XM, Vex, Mx }, 0 },
11239   },
11240   {
11241     /* VEX_W_0F382E_P_2_M_0 */
11242     { "vmaskmovps",     { Mx, Vex, XM }, 0 },
11243   },
11244   {
11245     /* VEX_W_0F382F_P_2_M_0 */
11246     { "vmaskmovpd",     { Mx, Vex, XM }, 0 },
11247   },
11248   {
11249     /* VEX_W_0F3830_P_2 */
11250     { "vpmovzxbw",      { XM, EXxmmq }, 0 },
11251   },
11252   {
11253     /* VEX_W_0F3831_P_2 */
11254     { "vpmovzxbd",      { XM, EXxmmqd }, 0 },
11255   },
11256   {
11257     /* VEX_W_0F3832_P_2 */
11258     { "vpmovzxbq",      { XM, EXxmmdw }, 0 },
11259   },
11260   {
11261     /* VEX_W_0F3833_P_2 */
11262     { "vpmovzxwd",      { XM, EXxmmq }, 0 },
11263   },
11264   {
11265     /* VEX_W_0F3834_P_2 */
11266     { "vpmovzxwq",      { XM, EXxmmqd }, 0 },
11267   },
11268   {
11269     /* VEX_W_0F3835_P_2 */
11270     { "vpmovzxdq",      { XM, EXxmmq }, 0 },
11271   },
11272   {
11273     /* VEX_W_0F3836_P_2  */
11274     { "vpermd",         { XM, Vex, EXx }, 0 },
11275   },
11276   {
11277     /* VEX_W_0F3837_P_2 */
11278     { "vpcmpgtq",       { XM, Vex, EXx }, 0 },
11279   },
11280   {
11281     /* VEX_W_0F3838_P_2 */
11282     { "vpminsb",        { XM, Vex, EXx }, 0 },
11283   },
11284   {
11285     /* VEX_W_0F3839_P_2 */
11286     { "vpminsd",        { XM, Vex, EXx }, 0 },
11287   },
11288   {
11289     /* VEX_W_0F383A_P_2 */
11290     { "vpminuw",        { XM, Vex, EXx }, 0 },
11291   },
11292   {
11293     /* VEX_W_0F383B_P_2 */
11294     { "vpminud",        { XM, Vex, EXx }, 0 },
11295   },
11296   {
11297     /* VEX_W_0F383C_P_2 */
11298     { "vpmaxsb",        { XM, Vex, EXx }, 0 },
11299   },
11300   {
11301     /* VEX_W_0F383D_P_2 */
11302     { "vpmaxsd",        { XM, Vex, EXx }, 0 },
11303   },
11304   {
11305     /* VEX_W_0F383E_P_2 */
11306     { "vpmaxuw",        { XM, Vex, EXx }, 0 },
11307   },
11308   {
11309     /* VEX_W_0F383F_P_2 */
11310     { "vpmaxud",        { XM, Vex, EXx }, 0 },
11311   },
11312   {
11313     /* VEX_W_0F3840_P_2 */
11314     { "vpmulld",        { XM, Vex, EXx }, 0 },
11315   },
11316   {
11317     /* VEX_W_0F3841_P_2 */
11318     { "vphminposuw",    { XM, EXx }, 0 },
11319   },
11320   {
11321     /* VEX_W_0F3846_P_2 */
11322     { "vpsravd",        { XM, Vex, EXx }, 0 },
11323   },
11324   {
11325     /* VEX_W_0F3858_P_2 */
11326     { "vpbroadcastd", { XM, EXxmm_md }, 0 },
11327   },
11328   {
11329     /* VEX_W_0F3859_P_2 */
11330     { "vpbroadcastq",   { XM, EXxmm_mq }, 0 },
11331   },
11332   {
11333     /* VEX_W_0F385A_P_2_M_0 */
11334     { "vbroadcasti128", { XM, Mxmm }, 0 },
11335   },
11336   {
11337     /* VEX_W_0F3878_P_2 */
11338     { "vpbroadcastb",   { XM, EXxmm_mb }, 0 },
11339   },
11340   {
11341     /* VEX_W_0F3879_P_2 */
11342     { "vpbroadcastw",   { XM, EXxmm_mw }, 0 },
11343   },
11344   {
11345     /* VEX_W_0F38CF_P_2 */
11346     { "vgf2p8mulb", { XM, Vex, EXx }, 0 },
11347   },
11348   {
11349     /* VEX_W_0F38DB_P_2 */
11350     { "vaesimc",        { XM, EXx }, 0 },
11351   },
11352   {
11353     /* VEX_W_0F3A00_P_2 */
11354     { Bad_Opcode },
11355     { "vpermq",         { XM, EXx, Ib }, 0 },
11356   },
11357   {
11358     /* VEX_W_0F3A01_P_2 */
11359     { Bad_Opcode },
11360     { "vpermpd",        { XM, EXx, Ib }, 0 },
11361   },
11362   {
11363     /* VEX_W_0F3A02_P_2 */
11364     { "vpblendd",       { XM, Vex, EXx, Ib }, 0 },
11365   },
11366   {
11367     /* VEX_W_0F3A04_P_2 */
11368     { "vpermilps",      { XM, EXx, Ib }, 0 },
11369   },
11370   {
11371     /* VEX_W_0F3A05_P_2 */
11372     { "vpermilpd",      { XM, EXx, Ib }, 0 },
11373   },
11374   {
11375     /* VEX_W_0F3A06_P_2 */
11376     { "vperm2f128",     { XM, Vex256, EXx, Ib }, 0 },
11377   },
11378   {
11379     /* VEX_W_0F3A08_P_2 */
11380     { "vroundps",       { XM, EXx, Ib }, 0 },
11381   },
11382   {
11383     /* VEX_W_0F3A09_P_2 */
11384     { "vroundpd",       { XM, EXx, Ib }, 0 },
11385   },
11386   {
11387     /* VEX_W_0F3A0A_P_2 */
11388     { "vroundss",       { XMScalar, VexScalar, EXdScalar, Ib }, 0 },
11389   },
11390   {
11391     /* VEX_W_0F3A0B_P_2 */
11392     { "vroundsd",       { XMScalar, VexScalar, EXqScalar, Ib }, 0 },
11393   },
11394   {
11395     /* VEX_W_0F3A0C_P_2 */
11396     { "vblendps",       { XM, Vex, EXx, Ib }, 0 },
11397   },
11398   {
11399     /* VEX_W_0F3A0D_P_2 */
11400     { "vblendpd",       { XM, Vex, EXx, Ib }, 0 },
11401   },
11402   {
11403     /* VEX_W_0F3A0E_P_2 */
11404     { "vpblendw",       { XM, Vex, EXx, Ib }, 0 },
11405   },
11406   {
11407     /* VEX_W_0F3A0F_P_2 */
11408     { "vpalignr",       { XM, Vex, EXx, Ib }, 0 },
11409   },
11410   {
11411     /* VEX_W_0F3A14_P_2 */
11412     { "vpextrb",        { Edqb, XM, Ib }, 0 },
11413   },
11414   {
11415     /* VEX_W_0F3A15_P_2 */
11416     { "vpextrw",        { Edqw, XM, Ib }, 0 },
11417   },
11418   {
11419     /* VEX_W_0F3A18_P_2 */
11420     { "vinsertf128",    { XM, Vex256, EXxmm, Ib }, 0 },
11421   },
11422   {
11423     /* VEX_W_0F3A19_P_2 */
11424     { "vextractf128",   { EXxmm, XM, Ib }, 0 },
11425   },
11426   {
11427     /* VEX_W_0F3A20_P_2 */
11428     { "vpinsrb",        { XM, Vex128, Edqb, Ib }, 0 },
11429   },
11430   {
11431     /* VEX_W_0F3A21_P_2 */
11432     { "vinsertps",      { XM, Vex128, EXd, Ib }, 0 },
11433   },
11434   {
11435     /* VEX_W_0F3A30_P_2_LEN_0 */
11436     { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) },
11437     { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) },
11438   },
11439   {
11440     /* VEX_W_0F3A31_P_2_LEN_0 */
11441     { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) },
11442     { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) },
11443   },
11444   {
11445     /* VEX_W_0F3A32_P_2_LEN_0 */
11446     { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) },
11447     { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) },
11448   },
11449   {
11450     /* VEX_W_0F3A33_P_2_LEN_0 */
11451     { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) },
11452     { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) },
11453   },
11454   {
11455     /* VEX_W_0F3A38_P_2 */
11456     { "vinserti128",    { XM, Vex256, EXxmm, Ib }, 0 },
11457   },
11458   {
11459     /* VEX_W_0F3A39_P_2 */
11460     { "vextracti128",   { EXxmm, XM, Ib }, 0 },
11461   },
11462   {
11463     /* VEX_W_0F3A40_P_2 */
11464     { "vdpps",          { XM, Vex, EXx, Ib }, 0 },
11465   },
11466   {
11467     /* VEX_W_0F3A41_P_2 */
11468     { "vdppd",          { XM, Vex128, EXx, Ib }, 0 },
11469   },
11470   {
11471     /* VEX_W_0F3A42_P_2 */
11472     { "vmpsadbw",       { XM, Vex, EXx, Ib }, 0 },
11473   },
11474   {
11475     /* VEX_W_0F3A46_P_2 */
11476     { "vperm2i128",     { XM, Vex256, EXx, Ib }, 0 },
11477   },
11478   {
11479     /* VEX_W_0F3A48_P_2 */
11480     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11481     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11482   },
11483   {
11484     /* VEX_W_0F3A49_P_2 */
11485     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11486     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11487   },
11488   {
11489     /* VEX_W_0F3A4A_P_2 */
11490     { "vblendvps",      { XM, Vex, EXx, XMVexI4 }, 0 },
11491   },
11492   {
11493     /* VEX_W_0F3A4B_P_2 */
11494     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 }, 0 },
11495   },
11496   {
11497     /* VEX_W_0F3A4C_P_2 */
11498     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 }, 0 },
11499   },
11500   {
11501     /* VEX_W_0F3A62_P_2 */
11502     { "vpcmpistrm",     { XM, EXx, Ib }, 0 },
11503   },
11504   {
11505     /* VEX_W_0F3A63_P_2 */
11506     { "vpcmpistri",     { XM, EXx, Ib }, 0 },
11507   },
11508   {
11509     /* VEX_W_0F3ACE_P_2 */
11510     { Bad_Opcode },
11511     { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, 0 },
11512   },
11513   {
11514     /* VEX_W_0F3ACF_P_2 */
11515     { Bad_Opcode },
11516     { "vgf2p8affineinvqb",  { XM, Vex, EXx, Ib }, 0 },
11517   },
11518   {
11519     /* VEX_W_0F3ADF_P_2 */
11520     { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
11521   },
11522 #define NEED_VEX_W_TABLE
11523 #include "i386-dis-evex.h"
11524 #undef NEED_VEX_W_TABLE
11525 };
11526
11527 static const struct dis386 mod_table[][2] = {
11528   {
11529     /* MOD_8D */
11530     { "leaS",           { Gv, M }, 0 },
11531   },
11532   {
11533     /* MOD_C6_REG_7 */
11534     { Bad_Opcode },
11535     { RM_TABLE (RM_C6_REG_7) },
11536   },
11537   {
11538     /* MOD_C7_REG_7 */
11539     { Bad_Opcode },
11540     { RM_TABLE (RM_C7_REG_7) },
11541   },
11542   {
11543     /* MOD_FF_REG_3 */
11544     { "Jcall^", { indirEp }, 0 },
11545   },
11546   {
11547     /* MOD_FF_REG_5 */
11548     { "Jjmp^", { indirEp }, 0 },
11549   },
11550   {
11551     /* MOD_0F01_REG_0 */
11552     { X86_64_TABLE (X86_64_0F01_REG_0) },
11553     { RM_TABLE (RM_0F01_REG_0) },
11554   },
11555   {
11556     /* MOD_0F01_REG_1 */
11557     { X86_64_TABLE (X86_64_0F01_REG_1) },
11558     { RM_TABLE (RM_0F01_REG_1) },
11559   },
11560   {
11561     /* MOD_0F01_REG_2 */
11562     { X86_64_TABLE (X86_64_0F01_REG_2) },
11563     { RM_TABLE (RM_0F01_REG_2) },
11564   },
11565   {
11566     /* MOD_0F01_REG_3 */
11567     { X86_64_TABLE (X86_64_0F01_REG_3) },
11568     { RM_TABLE (RM_0F01_REG_3) },
11569   },
11570   {
11571     /* MOD_0F01_REG_5 */
11572     { PREFIX_TABLE (PREFIX_MOD_0_0F01_REG_5) },
11573     { RM_TABLE (RM_0F01_REG_5) },
11574   },
11575   {
11576     /* MOD_0F01_REG_7 */
11577     { "invlpg",         { Mb }, 0 },
11578     { RM_TABLE (RM_0F01_REG_7) },
11579   },
11580   {
11581     /* MOD_0F12_PREFIX_0 */
11582     { "movlps",         { XM, EXq }, PREFIX_OPCODE },
11583     { "movhlps",        { XM, EXq }, PREFIX_OPCODE },
11584   },
11585   {
11586     /* MOD_0F13 */
11587     { "movlpX",         { EXq, XM }, PREFIX_OPCODE },
11588   },
11589   {
11590     /* MOD_0F16_PREFIX_0 */
11591     { "movhps",         { XM, EXq }, 0 },
11592     { "movlhps",        { XM, EXq }, 0 },
11593   },
11594   {
11595     /* MOD_0F17 */
11596     { "movhpX",         { EXq, XM }, PREFIX_OPCODE },
11597   },
11598   {
11599     /* MOD_0F18_REG_0 */
11600     { "prefetchnta",    { Mb }, 0 },
11601   },
11602   {
11603     /* MOD_0F18_REG_1 */
11604     { "prefetcht0",     { Mb }, 0 },
11605   },
11606   {
11607     /* MOD_0F18_REG_2 */
11608     { "prefetcht1",     { Mb }, 0 },
11609   },
11610   {
11611     /* MOD_0F18_REG_3 */
11612     { "prefetcht2",     { Mb }, 0 },
11613   },
11614   {
11615     /* MOD_0F18_REG_4 */
11616     { "nop/reserved",   { Mb }, 0 },
11617   },
11618   {
11619     /* MOD_0F18_REG_5 */
11620     { "nop/reserved",   { Mb }, 0 },
11621   },
11622   {
11623     /* MOD_0F18_REG_6 */
11624     { "nop/reserved",   { Mb }, 0 },
11625   },
11626   {
11627     /* MOD_0F18_REG_7 */
11628     { "nop/reserved",   { Mb }, 0 },
11629   },
11630   {
11631     /* MOD_0F1A_PREFIX_0 */
11632     { "bndldx",         { Gbnd, Ev_bnd }, 0 },
11633     { "nopQ",           { Ev }, 0 },
11634   },
11635   {
11636     /* MOD_0F1B_PREFIX_0 */
11637     { "bndstx",         { Ev_bnd, Gbnd }, 0 },
11638     { "nopQ",           { Ev }, 0 },
11639   },
11640   {
11641     /* MOD_0F1B_PREFIX_1 */
11642     { "bndmk",          { Gbnd, Ev_bnd }, 0 },
11643     { "nopQ",           { Ev }, 0 },
11644   },
11645   {
11646     /* MOD_0F1C_PREFIX_0 */
11647     { REG_TABLE (REG_0F1C_MOD_0) },
11648     { "nopQ",           { Ev }, 0 },
11649   },
11650   {
11651     /* MOD_0F1E_PREFIX_1 */
11652     { "nopQ",           { Ev }, 0 },
11653     { REG_TABLE (REG_0F1E_MOD_3) },
11654   },
11655   {
11656     /* MOD_0F24 */
11657     { Bad_Opcode },
11658     { "movL",           { Rd, Td }, 0 },
11659   },
11660   {
11661     /* MOD_0F26 */
11662     { Bad_Opcode },
11663     { "movL",           { Td, Rd }, 0 },
11664   },
11665   {
11666     /* MOD_0F2B_PREFIX_0 */
11667     {"movntps",         { Mx, XM }, PREFIX_OPCODE },
11668   },
11669   {
11670     /* MOD_0F2B_PREFIX_1 */
11671     {"movntss",         { Md, XM }, PREFIX_OPCODE },
11672   },
11673   {
11674     /* MOD_0F2B_PREFIX_2 */
11675     {"movntpd",         { Mx, XM }, PREFIX_OPCODE },
11676   },
11677   {
11678     /* MOD_0F2B_PREFIX_3 */
11679     {"movntsd",         { Mq, XM }, PREFIX_OPCODE },
11680   },
11681   {
11682     /* MOD_0F51 */
11683     { Bad_Opcode },
11684     { "movmskpX",       { Gdq, XS }, PREFIX_OPCODE },
11685   },
11686   {
11687     /* MOD_0F71_REG_2 */
11688     { Bad_Opcode },
11689     { "psrlw",          { MS, Ib }, 0 },
11690   },
11691   {
11692     /* MOD_0F71_REG_4 */
11693     { Bad_Opcode },
11694     { "psraw",          { MS, Ib }, 0 },
11695   },
11696   {
11697     /* MOD_0F71_REG_6 */
11698     { Bad_Opcode },
11699     { "psllw",          { MS, Ib }, 0 },
11700   },
11701   {
11702     /* MOD_0F72_REG_2 */
11703     { Bad_Opcode },
11704     { "psrld",          { MS, Ib }, 0 },
11705   },
11706   {
11707     /* MOD_0F72_REG_4 */
11708     { Bad_Opcode },
11709     { "psrad",          { MS, Ib }, 0 },
11710   },
11711   {
11712     /* MOD_0F72_REG_6 */
11713     { Bad_Opcode },
11714     { "pslld",          { MS, Ib }, 0 },
11715   },
11716   {
11717     /* MOD_0F73_REG_2 */
11718     { Bad_Opcode },
11719     { "psrlq",          { MS, Ib }, 0 },
11720   },
11721   {
11722     /* MOD_0F73_REG_3 */
11723     { Bad_Opcode },
11724     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
11725   },
11726   {
11727     /* MOD_0F73_REG_6 */
11728     { Bad_Opcode },
11729     { "psllq",          { MS, Ib }, 0 },
11730   },
11731   {
11732     /* MOD_0F73_REG_7 */
11733     { Bad_Opcode },
11734     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
11735   },
11736   {
11737     /* MOD_0FAE_REG_0 */
11738     { "fxsave",         { FXSAVE }, 0 },
11739     { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
11740   },
11741   {
11742     /* MOD_0FAE_REG_1 */
11743     { "fxrstor",        { FXSAVE }, 0 },
11744     { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
11745   },
11746   {
11747     /* MOD_0FAE_REG_2 */
11748     { "ldmxcsr",        { Md }, 0 },
11749     { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
11750   },
11751   {
11752     /* MOD_0FAE_REG_3 */
11753     { "stmxcsr",        { Md }, 0 },
11754     { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
11755   },
11756   {
11757     /* MOD_0FAE_REG_4 */
11758     { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_4) },
11759     { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_4) },
11760   },
11761   {
11762     /* MOD_0FAE_REG_5 */
11763     { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_5) },
11764     { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_5) },
11765   },
11766   {
11767     /* MOD_0FAE_REG_6 */
11768     { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_6) },
11769     { PREFIX_TABLE (PREFIX_MOD_1_0FAE_REG_6) },
11770   },
11771   {
11772     /* MOD_0FAE_REG_7 */
11773     { PREFIX_TABLE (PREFIX_0FAE_REG_7) },
11774     { RM_TABLE (RM_0FAE_REG_7) },
11775   },
11776   {
11777     /* MOD_0FB2 */
11778     { "lssS",           { Gv, Mp }, 0 },
11779   },
11780   {
11781     /* MOD_0FB4 */
11782     { "lfsS",           { Gv, Mp }, 0 },
11783   },
11784   {
11785     /* MOD_0FB5 */
11786     { "lgsS",           { Gv, Mp }, 0 },
11787   },
11788   {
11789     /* MOD_0FC3 */
11790     { PREFIX_TABLE (PREFIX_MOD_0_0FC3) },
11791   },
11792   {
11793     /* MOD_0FC7_REG_3 */
11794     { "xrstors",        { FXSAVE }, 0 },
11795   },
11796   {
11797     /* MOD_0FC7_REG_4 */
11798     { "xsavec",         { FXSAVE }, 0 },
11799   },
11800   {
11801     /* MOD_0FC7_REG_5 */
11802     { "xsaves",         { FXSAVE }, 0 },
11803   },
11804   {
11805     /* MOD_0FC7_REG_6 */
11806     { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6) },
11807     { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6) }
11808   },
11809   {
11810     /* MOD_0FC7_REG_7 */
11811     { "vmptrst",        { Mq }, 0 },
11812     { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7) }
11813   },
11814   {
11815     /* MOD_0FD7 */
11816     { Bad_Opcode },
11817     { "pmovmskb",       { Gdq, MS }, 0 },
11818   },
11819   {
11820     /* MOD_0FE7_PREFIX_2 */
11821     { "movntdq",        { Mx, XM }, 0 },
11822   },
11823   {
11824     /* MOD_0FF0_PREFIX_3 */
11825     { "lddqu",          { XM, M }, 0 },
11826   },
11827   {
11828     /* MOD_0F382A_PREFIX_2 */
11829     { "movntdqa",       { XM, Mx }, 0 },
11830   },
11831   {
11832     /* MOD_0F38F5_PREFIX_2 */
11833     { "wrussK",         { M, Gdq }, PREFIX_OPCODE },
11834   },
11835   {
11836     /* MOD_0F38F6_PREFIX_0 */
11837     { "wrssK",          { M, Gdq }, PREFIX_OPCODE },
11838   },
11839   {
11840     /* MOD_62_32BIT */
11841     { "bound{S|}",      { Gv, Ma }, 0 },
11842     { EVEX_TABLE (EVEX_0F) },
11843   },
11844   {
11845     /* MOD_C4_32BIT */
11846     { "lesS",           { Gv, Mp }, 0 },
11847     { VEX_C4_TABLE (VEX_0F) },
11848   },
11849   {
11850     /* MOD_C5_32BIT */
11851     { "ldsS",           { Gv, Mp }, 0 },
11852     { VEX_C5_TABLE (VEX_0F) },
11853   },
11854   {
11855     /* MOD_VEX_0F12_PREFIX_0 */
11856     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
11857     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
11858   },
11859   {
11860     /* MOD_VEX_0F13 */
11861     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
11862   },
11863   {
11864     /* MOD_VEX_0F16_PREFIX_0 */
11865     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
11866     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
11867   },
11868   {
11869     /* MOD_VEX_0F17 */
11870     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
11871   },
11872   {
11873     /* MOD_VEX_0F2B */
11874     { VEX_W_TABLE (VEX_W_0F2B_M_0) },
11875   },
11876   {
11877     /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
11878     { Bad_Opcode },
11879     { "kandw",          { MaskG, MaskVex, MaskR }, 0 },
11880   },
11881   {
11882     /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
11883     { Bad_Opcode },
11884     { "kandq",          { MaskG, MaskVex, MaskR }, 0 },
11885   },
11886   {
11887     /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
11888     { Bad_Opcode },
11889     { "kandb",          { MaskG, MaskVex, MaskR }, 0 },
11890   },
11891   {
11892     /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
11893     { Bad_Opcode },
11894     { "kandd",          { MaskG, MaskVex, MaskR }, 0 },
11895   },
11896   {
11897     /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
11898     { Bad_Opcode },
11899     { "kandnw",         { MaskG, MaskVex, MaskR }, 0 },
11900   },
11901   {
11902     /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
11903     { Bad_Opcode },
11904     { "kandnq",         { MaskG, MaskVex, MaskR }, 0 },
11905   },
11906   {
11907     /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
11908     { Bad_Opcode },
11909     { "kandnb",         { MaskG, MaskVex, MaskR }, 0 },
11910   },
11911   {
11912     /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
11913     { Bad_Opcode },
11914     { "kandnd",         { MaskG, MaskVex, MaskR }, 0 },
11915   },
11916   {
11917     /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
11918     { Bad_Opcode },
11919     { "knotw",          { MaskG, MaskR }, 0 },
11920   },
11921   {
11922     /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
11923     { Bad_Opcode },
11924     { "knotq",          { MaskG, MaskR }, 0 },
11925   },
11926   {
11927     /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
11928     { Bad_Opcode },
11929     { "knotb",          { MaskG, MaskR }, 0 },
11930   },
11931   {
11932     /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
11933     { Bad_Opcode },
11934     { "knotd",          { MaskG, MaskR }, 0 },
11935   },
11936   {
11937     /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
11938     { Bad_Opcode },
11939     { "korw",       { MaskG, MaskVex, MaskR }, 0 },
11940   },
11941   {
11942     /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
11943     { Bad_Opcode },
11944     { "korq",       { MaskG, MaskVex, MaskR }, 0 },
11945   },
11946   {
11947     /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
11948     { Bad_Opcode },
11949     { "korb",       { MaskG, MaskVex, MaskR }, 0 },
11950   },
11951   {
11952     /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
11953     { Bad_Opcode },
11954     { "kord",       { MaskG, MaskVex, MaskR }, 0 },
11955   },
11956  {
11957     /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
11958     { Bad_Opcode },
11959     { "kxnorw",     { MaskG, MaskVex, MaskR }, 0 },
11960   },
11961   {
11962     /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
11963     { Bad_Opcode },
11964     { "kxnorq",     { MaskG, MaskVex, MaskR }, 0 },
11965   },
11966   {
11967     /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
11968     { Bad_Opcode },
11969     { "kxnorb",     { MaskG, MaskVex, MaskR }, 0 },
11970   },
11971   {
11972     /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
11973     { Bad_Opcode },
11974     { "kxnord",     { MaskG, MaskVex, MaskR }, 0 },
11975   },
11976   {
11977     /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
11978     { Bad_Opcode },
11979     { "kxorw",      { MaskG, MaskVex, MaskR }, 0 },
11980   },
11981   {
11982     /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
11983     { Bad_Opcode },
11984     { "kxorq",      { MaskG, MaskVex, MaskR }, 0 },
11985   },
11986   {
11987     /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
11988     { Bad_Opcode },
11989     { "kxorb",      { MaskG, MaskVex, MaskR }, 0 },
11990   },
11991   {
11992     /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
11993     { Bad_Opcode },
11994     { "kxord",      { MaskG, MaskVex, MaskR }, 0 },
11995   },
11996   {
11997     /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
11998     { Bad_Opcode },
11999     { "kaddw",          { MaskG, MaskVex, MaskR }, 0 },
12000   },
12001   {
12002     /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
12003     { Bad_Opcode },
12004     { "kaddq",          { MaskG, MaskVex, MaskR }, 0 },
12005   },
12006   {
12007     /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
12008     { Bad_Opcode },
12009     { "kaddb",          { MaskG, MaskVex, MaskR }, 0 },
12010   },
12011   {
12012     /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
12013     { Bad_Opcode },
12014     { "kaddd",          { MaskG, MaskVex, MaskR }, 0 },
12015   },
12016   {
12017     /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
12018     { Bad_Opcode },
12019     { "kunpckwd",   { MaskG, MaskVex, MaskR }, 0 },
12020   },
12021   {
12022     /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
12023     { Bad_Opcode },
12024     { "kunpckdq",   { MaskG, MaskVex, MaskR }, 0 },
12025   },
12026   {
12027     /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
12028     { Bad_Opcode },
12029     { "kunpckbw",   { MaskG, MaskVex, MaskR }, 0 },
12030   },
12031   {
12032     /* MOD_VEX_0F50 */
12033     { Bad_Opcode },
12034     { VEX_W_TABLE (VEX_W_0F50_M_0) },
12035   },
12036   {
12037     /* MOD_VEX_0F71_REG_2 */
12038     { Bad_Opcode },
12039     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
12040   },
12041   {
12042     /* MOD_VEX_0F71_REG_4 */
12043     { Bad_Opcode },
12044     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
12045   },
12046   {
12047     /* MOD_VEX_0F71_REG_6 */
12048     { Bad_Opcode },
12049     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
12050   },
12051   {
12052     /* MOD_VEX_0F72_REG_2 */
12053     { Bad_Opcode },
12054     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
12055   },
12056   {
12057     /* MOD_VEX_0F72_REG_4 */
12058     { Bad_Opcode },
12059     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
12060   },
12061   {
12062     /* MOD_VEX_0F72_REG_6 */
12063     { Bad_Opcode },
12064     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
12065   },
12066   {
12067     /* MOD_VEX_0F73_REG_2 */
12068     { Bad_Opcode },
12069     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
12070   },
12071   {
12072     /* MOD_VEX_0F73_REG_3 */
12073     { Bad_Opcode },
12074     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
12075   },
12076   {
12077     /* MOD_VEX_0F73_REG_6 */
12078     { Bad_Opcode },
12079     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
12080   },
12081   {
12082     /* MOD_VEX_0F73_REG_7 */
12083     { Bad_Opcode },
12084     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
12085   },
12086   {
12087     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
12088     { "kmovw",          { Ew, MaskG }, 0 },
12089     { Bad_Opcode },
12090   },
12091   {
12092     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
12093     { "kmovq",          { Eq, MaskG }, 0 },
12094     { Bad_Opcode },
12095   },
12096   {
12097     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
12098     { "kmovb",          { Eb, MaskG }, 0 },
12099     { Bad_Opcode },
12100   },
12101   {
12102     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
12103     { "kmovd",          { Ed, MaskG }, 0 },
12104     { Bad_Opcode },
12105   },
12106   {
12107     /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
12108     { Bad_Opcode },
12109     { "kmovw",          { MaskG, Rdq }, 0 },
12110   },
12111   {
12112     /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
12113     { Bad_Opcode },
12114     { "kmovb",          { MaskG, Rdq }, 0 },
12115   },
12116   {
12117     /* MOD_VEX_W_0_0F92_P_3_LEN_0 */
12118     { Bad_Opcode },
12119     { "kmovd",          { MaskG, Rdq }, 0 },
12120   },
12121   {
12122     /* MOD_VEX_W_1_0F92_P_3_LEN_0 */
12123     { Bad_Opcode },
12124     { "kmovq",          { MaskG, Rdq }, 0 },
12125   },
12126   {
12127     /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
12128     { Bad_Opcode },
12129     { "kmovw",          { Gdq, MaskR }, 0 },
12130   },
12131   {
12132     /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
12133     { Bad_Opcode },
12134     { "kmovb",          { Gdq, MaskR }, 0 },
12135   },
12136   {
12137     /* MOD_VEX_W_0_0F93_P_3_LEN_0 */
12138     { Bad_Opcode },
12139     { "kmovd",          { Gdq, MaskR }, 0 },
12140   },
12141   {
12142     /* MOD_VEX_W_1_0F93_P_3_LEN_0 */
12143     { Bad_Opcode },
12144     { "kmovq",          { Gdq, MaskR }, 0 },
12145   },
12146   {
12147     /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
12148     { Bad_Opcode },
12149     { "kortestw", { MaskG, MaskR }, 0 },
12150   },
12151   {
12152     /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
12153     { Bad_Opcode },
12154     { "kortestq", { MaskG, MaskR }, 0 },
12155   },
12156   {
12157     /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
12158     { Bad_Opcode },
12159     { "kortestb", { MaskG, MaskR }, 0 },
12160   },
12161   {
12162     /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
12163     { Bad_Opcode },
12164     { "kortestd", { MaskG, MaskR }, 0 },
12165   },
12166   {
12167     /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
12168     { Bad_Opcode },
12169     { "ktestw", { MaskG, MaskR }, 0 },
12170   },
12171   {
12172     /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
12173     { Bad_Opcode },
12174     { "ktestq", { MaskG, MaskR }, 0 },
12175   },
12176   {
12177     /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
12178     { Bad_Opcode },
12179     { "ktestb", { MaskG, MaskR }, 0 },
12180   },
12181   {
12182     /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
12183     { Bad_Opcode },
12184     { "ktestd", { MaskG, MaskR }, 0 },
12185   },
12186   {
12187     /* MOD_VEX_0FAE_REG_2 */
12188     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
12189   },
12190   {
12191     /* MOD_VEX_0FAE_REG_3 */
12192     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
12193   },
12194   {
12195     /* MOD_VEX_0FD7_PREFIX_2 */
12196     { Bad_Opcode },
12197     { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) },
12198   },
12199   {
12200     /* MOD_VEX_0FE7_PREFIX_2 */
12201     { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) },
12202   },
12203   {
12204     /* MOD_VEX_0FF0_PREFIX_3 */
12205     { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) },
12206   },
12207   {
12208     /* MOD_VEX_0F381A_PREFIX_2 */
12209     { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
12210   },
12211   {
12212     /* MOD_VEX_0F382A_PREFIX_2 */
12213     { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) },
12214   },
12215   {
12216     /* MOD_VEX_0F382C_PREFIX_2 */
12217     { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
12218   },
12219   {
12220     /* MOD_VEX_0F382D_PREFIX_2 */
12221     { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
12222   },
12223   {
12224     /* MOD_VEX_0F382E_PREFIX_2 */
12225     { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
12226   },
12227   {
12228     /* MOD_VEX_0F382F_PREFIX_2 */
12229     { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
12230   },
12231   {
12232     /* MOD_VEX_0F385A_PREFIX_2 */
12233     { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
12234   },
12235   {
12236     /* MOD_VEX_0F388C_PREFIX_2 */
12237     { "vpmaskmov%LW",   { XM, Vex, Mx }, 0 },
12238   },
12239   {
12240     /* MOD_VEX_0F388E_PREFIX_2 */
12241     { "vpmaskmov%LW",   { Mx, Vex, XM }, 0 },
12242   },
12243   {
12244     /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
12245     { Bad_Opcode },
12246     { "kshiftrb",       { MaskG, MaskR, Ib }, 0 },
12247   },
12248   {
12249     /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
12250     { Bad_Opcode },
12251     { "kshiftrw",       { MaskG, MaskR, Ib }, 0 },
12252   },
12253   {
12254     /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
12255     { Bad_Opcode },
12256     { "kshiftrd",       { MaskG, MaskR, Ib }, 0 },
12257   },
12258   {
12259     /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
12260     { Bad_Opcode },
12261     { "kshiftrq",       { MaskG, MaskR, Ib }, 0 },
12262   },
12263   {
12264     /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
12265     { Bad_Opcode },
12266     { "kshiftlb",       { MaskG, MaskR, Ib }, 0 },
12267   },
12268   {
12269     /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
12270     { Bad_Opcode },
12271     { "kshiftlw",       { MaskG, MaskR, Ib }, 0 },
12272   },
12273   {
12274     /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
12275     { Bad_Opcode },
12276     { "kshiftld",       { MaskG, MaskR, Ib }, 0 },
12277   },
12278   {
12279     /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
12280     { Bad_Opcode },
12281     { "kshiftlq",       { MaskG, MaskR, Ib }, 0 },
12282   },
12283 #define NEED_MOD_TABLE
12284 #include "i386-dis-evex.h"
12285 #undef NEED_MOD_TABLE
12286 };
12287
12288 static const struct dis386 rm_table[][8] = {
12289   {
12290     /* RM_C6_REG_7 */
12291     { "xabort",         { Skip_MODRM, Ib }, 0 },
12292   },
12293   {
12294     /* RM_C7_REG_7 */
12295     { "xbeginT",        { Skip_MODRM, Jv }, 0 },
12296   },
12297   {
12298     /* RM_0F01_REG_0 */
12299     { Bad_Opcode },
12300     { "vmcall",         { Skip_MODRM }, 0 },
12301     { "vmlaunch",       { Skip_MODRM }, 0 },
12302     { "vmresume",       { Skip_MODRM }, 0 },
12303     { "vmxoff",         { Skip_MODRM }, 0 },
12304     { "pconfig",        { Skip_MODRM }, 0 },
12305   },
12306   {
12307     /* RM_0F01_REG_1 */
12308     { "monitor",        { { OP_Monitor, 0 } }, 0 },
12309     { "mwait",          { { OP_Mwait, 0 } }, 0 },
12310     { "clac",           { Skip_MODRM }, 0 },
12311     { "stac",           { Skip_MODRM }, 0 },
12312     { Bad_Opcode },
12313     { Bad_Opcode },
12314     { Bad_Opcode },
12315     { "encls",          { Skip_MODRM }, 0 },
12316   },
12317   {
12318     /* RM_0F01_REG_2 */
12319     { "xgetbv",         { Skip_MODRM }, 0 },
12320     { "xsetbv",         { Skip_MODRM }, 0 },
12321     { Bad_Opcode },
12322     { Bad_Opcode },
12323     { "vmfunc",         { Skip_MODRM }, 0 },
12324     { "xend",           { Skip_MODRM }, 0 },
12325     { "xtest",          { Skip_MODRM }, 0 },
12326     { "enclu",          { Skip_MODRM }, 0 },
12327   },
12328   {
12329     /* RM_0F01_REG_3 */
12330     { "vmrun",          { Skip_MODRM }, 0 },
12331     { "vmmcall",        { Skip_MODRM }, 0 },
12332     { "vmload",         { Skip_MODRM }, 0 },
12333     { "vmsave",         { Skip_MODRM }, 0 },
12334     { "stgi",           { Skip_MODRM }, 0 },
12335     { "clgi",           { Skip_MODRM }, 0 },
12336     { "skinit",         { Skip_MODRM }, 0 },
12337     { "invlpga",        { Skip_MODRM }, 0 },
12338   },
12339   {
12340     /* RM_0F01_REG_5 */
12341     { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_0) },
12342     { Bad_Opcode },
12343     { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_2) },
12344     { Bad_Opcode },
12345     { Bad_Opcode },
12346     { Bad_Opcode },
12347     { "rdpkru",         { Skip_MODRM }, 0 },
12348     { "wrpkru",         { Skip_MODRM }, 0 },
12349   },
12350   {
12351     /* RM_0F01_REG_7 */
12352     { "swapgs",         { Skip_MODRM }, 0  },
12353     { "rdtscp",         { Skip_MODRM }, 0  },
12354     { "monitorx",       { { OP_Monitor, 0 } }, 0  },
12355     { "mwaitx",         { { OP_Mwaitx,  0 } }, 0  },
12356     { "clzero",         { Skip_MODRM }, 0  },
12357   },
12358   {
12359     /* RM_0F1E_MOD_3_REG_7 */
12360     { "nopQ",           { Ev }, 0 },
12361     { "nopQ",           { Ev }, 0 },
12362     { "endbr64",        { Skip_MODRM },  PREFIX_OPCODE },
12363     { "endbr32",        { Skip_MODRM },  PREFIX_OPCODE },
12364     { "nopQ",           { Ev }, 0 },
12365     { "nopQ",           { Ev }, 0 },
12366     { "nopQ",           { Ev }, 0 },
12367     { "nopQ",           { Ev }, 0 },
12368   },
12369   {
12370     /* RM_0FAE_REG_6 */
12371     { "mfence",         { Skip_MODRM }, 0 },
12372   },
12373   {
12374     /* RM_0FAE_REG_7 */
12375     { "sfence",         { Skip_MODRM }, 0 },
12376
12377   },
12378 };
12379
12380 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
12381
12382 /* We use the high bit to indicate different name for the same
12383    prefix.  */
12384 #define REP_PREFIX      (0xf3 | 0x100)
12385 #define XACQUIRE_PREFIX (0xf2 | 0x200)
12386 #define XRELEASE_PREFIX (0xf3 | 0x400)
12387 #define BND_PREFIX      (0xf2 | 0x400)
12388 #define NOTRACK_PREFIX  (0x3e | 0x100)
12389
12390 static int
12391 ckprefix (void)
12392 {
12393   int newrex, i, length;
12394   rex = 0;
12395   rex_ignored = 0;
12396   prefixes = 0;
12397   used_prefixes = 0;
12398   rex_used = 0;
12399   last_lock_prefix = -1;
12400   last_repz_prefix = -1;
12401   last_repnz_prefix = -1;
12402   last_data_prefix = -1;
12403   last_addr_prefix = -1;
12404   last_rex_prefix = -1;
12405   last_seg_prefix = -1;
12406   fwait_prefix = -1;
12407   active_seg_prefix = 0;
12408   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12409     all_prefixes[i] = 0;
12410   i = 0;
12411   length = 0;
12412   /* The maximum instruction length is 15bytes.  */
12413   while (length < MAX_CODE_LENGTH - 1)
12414     {
12415       FETCH_DATA (the_info, codep + 1);
12416       newrex = 0;
12417       switch (*codep)
12418         {
12419         /* REX prefixes family.  */
12420         case 0x40:
12421         case 0x41:
12422         case 0x42:
12423         case 0x43:
12424         case 0x44:
12425         case 0x45:
12426         case 0x46:
12427         case 0x47:
12428         case 0x48:
12429         case 0x49:
12430         case 0x4a:
12431         case 0x4b:
12432         case 0x4c:
12433         case 0x4d:
12434         case 0x4e:
12435         case 0x4f:
12436           if (address_mode == mode_64bit)
12437             newrex = *codep;
12438           else
12439             return 1;
12440           last_rex_prefix = i;
12441           break;
12442         case 0xf3:
12443           prefixes |= PREFIX_REPZ;
12444           last_repz_prefix = i;
12445           break;
12446         case 0xf2:
12447           prefixes |= PREFIX_REPNZ;
12448           last_repnz_prefix = i;
12449           break;
12450         case 0xf0:
12451           prefixes |= PREFIX_LOCK;
12452           last_lock_prefix = i;
12453           break;
12454         case 0x2e:
12455           prefixes |= PREFIX_CS;
12456           last_seg_prefix = i;
12457           active_seg_prefix = PREFIX_CS;
12458           break;
12459         case 0x36:
12460           prefixes |= PREFIX_SS;
12461           last_seg_prefix = i;
12462           active_seg_prefix = PREFIX_SS;
12463           break;
12464         case 0x3e:
12465           prefixes |= PREFIX_DS;
12466           last_seg_prefix = i;
12467           active_seg_prefix = PREFIX_DS;
12468           break;
12469         case 0x26:
12470           prefixes |= PREFIX_ES;
12471           last_seg_prefix = i;
12472           active_seg_prefix = PREFIX_ES;
12473           break;
12474         case 0x64:
12475           prefixes |= PREFIX_FS;
12476           last_seg_prefix = i;
12477           active_seg_prefix = PREFIX_FS;
12478           break;
12479         case 0x65:
12480           prefixes |= PREFIX_GS;
12481           last_seg_prefix = i;
12482           active_seg_prefix = PREFIX_GS;
12483           break;
12484         case 0x66:
12485           prefixes |= PREFIX_DATA;
12486           last_data_prefix = i;
12487           break;
12488         case 0x67:
12489           prefixes |= PREFIX_ADDR;
12490           last_addr_prefix = i;
12491           break;
12492         case FWAIT_OPCODE:
12493           /* fwait is really an instruction.  If there are prefixes
12494              before the fwait, they belong to the fwait, *not* to the
12495              following instruction.  */
12496           fwait_prefix = i;
12497           if (prefixes || rex)
12498             {
12499               prefixes |= PREFIX_FWAIT;
12500               codep++;
12501               /* This ensures that the previous REX prefixes are noticed
12502                  as unused prefixes, as in the return case below.  */
12503               rex_used = rex;
12504               return 1;
12505             }
12506           prefixes = PREFIX_FWAIT;
12507           break;
12508         default:
12509           return 1;
12510         }
12511       /* Rex is ignored when followed by another prefix.  */
12512       if (rex)
12513         {
12514           rex_used = rex;
12515           return 1;
12516         }
12517       if (*codep != FWAIT_OPCODE)
12518         all_prefixes[i++] = *codep;
12519       rex = newrex;
12520       codep++;
12521       length++;
12522     }
12523   return 0;
12524 }
12525
12526 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
12527    prefix byte.  */
12528
12529 static const char *
12530 prefix_name (int pref, int sizeflag)
12531 {
12532   static const char *rexes [16] =
12533     {
12534       "rex",            /* 0x40 */
12535       "rex.B",          /* 0x41 */
12536       "rex.X",          /* 0x42 */
12537       "rex.XB",         /* 0x43 */
12538       "rex.R",          /* 0x44 */
12539       "rex.RB",         /* 0x45 */
12540       "rex.RX",         /* 0x46 */
12541       "rex.RXB",        /* 0x47 */
12542       "rex.W",          /* 0x48 */
12543       "rex.WB",         /* 0x49 */
12544       "rex.WX",         /* 0x4a */
12545       "rex.WXB",        /* 0x4b */
12546       "rex.WR",         /* 0x4c */
12547       "rex.WRB",        /* 0x4d */
12548       "rex.WRX",        /* 0x4e */
12549       "rex.WRXB",       /* 0x4f */
12550     };
12551
12552   switch (pref)
12553     {
12554     /* REX prefixes family.  */
12555     case 0x40:
12556     case 0x41:
12557     case 0x42:
12558     case 0x43:
12559     case 0x44:
12560     case 0x45:
12561     case 0x46:
12562     case 0x47:
12563     case 0x48:
12564     case 0x49:
12565     case 0x4a:
12566     case 0x4b:
12567     case 0x4c:
12568     case 0x4d:
12569     case 0x4e:
12570     case 0x4f:
12571       return rexes [pref - 0x40];
12572     case 0xf3:
12573       return "repz";
12574     case 0xf2:
12575       return "repnz";
12576     case 0xf0:
12577       return "lock";
12578     case 0x2e:
12579       return "cs";
12580     case 0x36:
12581       return "ss";
12582     case 0x3e:
12583       return "ds";
12584     case 0x26:
12585       return "es";
12586     case 0x64:
12587       return "fs";
12588     case 0x65:
12589       return "gs";
12590     case 0x66:
12591       return (sizeflag & DFLAG) ? "data16" : "data32";
12592     case 0x67:
12593       if (address_mode == mode_64bit)
12594         return (sizeflag & AFLAG) ? "addr32" : "addr64";
12595       else
12596         return (sizeflag & AFLAG) ? "addr16" : "addr32";
12597     case FWAIT_OPCODE:
12598       return "fwait";
12599     case REP_PREFIX:
12600       return "rep";
12601     case XACQUIRE_PREFIX:
12602       return "xacquire";
12603     case XRELEASE_PREFIX:
12604       return "xrelease";
12605     case BND_PREFIX:
12606       return "bnd";
12607     case NOTRACK_PREFIX:
12608       return "notrack";
12609     default:
12610       return NULL;
12611     }
12612 }
12613
12614 static char op_out[MAX_OPERANDS][100];
12615 static int op_ad, op_index[MAX_OPERANDS];
12616 static int two_source_ops;
12617 static bfd_vma op_address[MAX_OPERANDS];
12618 static bfd_vma op_riprel[MAX_OPERANDS];
12619 static bfd_vma start_pc;
12620
12621 /*
12622  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
12623  *   (see topic "Redundant prefixes" in the "Differences from 8086"
12624  *   section of the "Virtual 8086 Mode" chapter.)
12625  * 'pc' should be the address of this instruction, it will
12626  *   be used to print the target address if this is a relative jump or call
12627  * The function returns the length of this instruction in bytes.
12628  */
12629
12630 static char intel_syntax;
12631 static char intel_mnemonic = !SYSV386_COMPAT;
12632 static char open_char;
12633 static char close_char;
12634 static char separator_char;
12635 static char scale_char;
12636
12637 enum x86_64_isa
12638 {
12639   amd64 = 0,
12640   intel64
12641 };
12642
12643 static enum x86_64_isa isa64;
12644
12645 /* Here for backwards compatibility.  When gdb stops using
12646    print_insn_i386_att and print_insn_i386_intel these functions can
12647    disappear, and print_insn_i386 be merged into print_insn.  */
12648 int
12649 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
12650 {
12651   intel_syntax = 0;
12652
12653   return print_insn (pc, info);
12654 }
12655
12656 int
12657 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
12658 {
12659   intel_syntax = 1;
12660
12661   return print_insn (pc, info);
12662 }
12663
12664 int
12665 print_insn_i386 (bfd_vma pc, disassemble_info *info)
12666 {
12667   intel_syntax = -1;
12668
12669   return print_insn (pc, info);
12670 }
12671
12672 void
12673 print_i386_disassembler_options (FILE *stream)
12674 {
12675   fprintf (stream, _("\n\
12676 The following i386/x86-64 specific disassembler options are supported for use\n\
12677 with the -M switch (multiple options should be separated by commas):\n"));
12678
12679   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
12680   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
12681   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
12682   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
12683   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
12684   fprintf (stream, _("  att-mnemonic\n"
12685                      "              Display instruction in AT&T mnemonic\n"));
12686   fprintf (stream, _("  intel-mnemonic\n"
12687                      "              Display instruction in Intel mnemonic\n"));
12688   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
12689   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
12690   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
12691   fprintf (stream, _("  data32      Assume 32bit data size\n"));
12692   fprintf (stream, _("  data16      Assume 16bit data size\n"));
12693   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
12694   fprintf (stream, _("  amd64       Display instruction in AMD64 ISA\n"));
12695   fprintf (stream, _("  intel64     Display instruction in Intel64 ISA\n"));
12696 }
12697
12698 /* Bad opcode.  */
12699 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
12700
12701 /* Get a pointer to struct dis386 with a valid name.  */
12702
12703 static const struct dis386 *
12704 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
12705 {
12706   int vindex, vex_table_index;
12707
12708   if (dp->name != NULL)
12709     return dp;
12710
12711   switch (dp->op[0].bytemode)
12712     {
12713     case USE_REG_TABLE:
12714       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
12715       break;
12716
12717     case USE_MOD_TABLE:
12718       vindex = modrm.mod == 0x3 ? 1 : 0;
12719       dp = &mod_table[dp->op[1].bytemode][vindex];
12720       break;
12721
12722     case USE_RM_TABLE:
12723       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
12724       break;
12725
12726     case USE_PREFIX_TABLE:
12727       if (need_vex)
12728         {
12729           /* The prefix in VEX is implicit.  */
12730           switch (vex.prefix)
12731             {
12732             case 0:
12733               vindex = 0;
12734               break;
12735             case REPE_PREFIX_OPCODE:
12736               vindex = 1;
12737               break;
12738             case DATA_PREFIX_OPCODE:
12739               vindex = 2;
12740               break;
12741             case REPNE_PREFIX_OPCODE:
12742               vindex = 3;
12743               break;
12744             default:
12745               abort ();
12746               break;
12747             }
12748         }
12749       else
12750         {
12751           int last_prefix = -1;
12752           int prefix = 0;
12753           vindex = 0;
12754           /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
12755              When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
12756              last one wins.  */
12757           if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
12758             {
12759               if (last_repz_prefix > last_repnz_prefix)
12760                 {
12761                   vindex = 1;
12762                   prefix = PREFIX_REPZ;
12763                   last_prefix = last_repz_prefix;
12764                 }
12765               else
12766                 {
12767                   vindex = 3;
12768                   prefix = PREFIX_REPNZ;
12769                   last_prefix = last_repnz_prefix;
12770                 }
12771
12772               /* Check if prefix should be ignored.  */
12773               if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
12774                      & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
12775                    & prefix) != 0)
12776                 vindex = 0;
12777             }
12778
12779           if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
12780             {
12781               vindex = 2;
12782               prefix = PREFIX_DATA;
12783               last_prefix = last_data_prefix;
12784             }
12785
12786           if (vindex != 0)
12787             {
12788               used_prefixes |= prefix;
12789               all_prefixes[last_prefix] = 0;
12790             }
12791         }
12792       dp = &prefix_table[dp->op[1].bytemode][vindex];
12793       break;
12794
12795     case USE_X86_64_TABLE:
12796       vindex = address_mode == mode_64bit ? 1 : 0;
12797       dp = &x86_64_table[dp->op[1].bytemode][vindex];
12798       break;
12799
12800     case USE_3BYTE_TABLE:
12801       FETCH_DATA (info, codep + 2);
12802       vindex = *codep++;
12803       dp = &three_byte_table[dp->op[1].bytemode][vindex];
12804       end_codep = codep;
12805       modrm.mod = (*codep >> 6) & 3;
12806       modrm.reg = (*codep >> 3) & 7;
12807       modrm.rm = *codep & 7;
12808       break;
12809
12810     case USE_VEX_LEN_TABLE:
12811       if (!need_vex)
12812         abort ();
12813
12814       switch (vex.length)
12815         {
12816         case 128:
12817           vindex = 0;
12818           break;
12819         case 256:
12820           vindex = 1;
12821           break;
12822         default:
12823           abort ();
12824           break;
12825         }
12826
12827       dp = &vex_len_table[dp->op[1].bytemode][vindex];
12828       break;
12829
12830     case USE_XOP_8F_TABLE:
12831       FETCH_DATA (info, codep + 3);
12832       /* All bits in the REX prefix are ignored.  */
12833       rex_ignored = rex;
12834       rex = ~(*codep >> 5) & 0x7;
12835
12836       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
12837       switch ((*codep & 0x1f))
12838         {
12839         default:
12840           dp = &bad_opcode;
12841           return dp;
12842         case 0x8:
12843           vex_table_index = XOP_08;
12844           break;
12845         case 0x9:
12846           vex_table_index = XOP_09;
12847           break;
12848         case 0xa:
12849           vex_table_index = XOP_0A;
12850           break;
12851         }
12852       codep++;
12853       vex.w = *codep & 0x80;
12854       if (vex.w && address_mode == mode_64bit)
12855         rex |= REX_W;
12856
12857       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12858       if (address_mode != mode_64bit)
12859         {
12860           /* In 16/32-bit mode REX_B is silently ignored.  */
12861           rex &= ~REX_B;
12862         }
12863
12864       vex.length = (*codep & 0x4) ? 256 : 128;
12865       switch ((*codep & 0x3))
12866         {
12867         case 0:
12868           break;
12869         case 1:
12870           vex.prefix = DATA_PREFIX_OPCODE;
12871           break;
12872         case 2:
12873           vex.prefix = REPE_PREFIX_OPCODE;
12874           break;
12875         case 3:
12876           vex.prefix = REPNE_PREFIX_OPCODE;
12877           break;
12878         }
12879       need_vex = 1;
12880       need_vex_reg = 1;
12881       codep++;
12882       vindex = *codep++;
12883       dp = &xop_table[vex_table_index][vindex];
12884
12885       end_codep = codep;
12886       FETCH_DATA (info, codep + 1);
12887       modrm.mod = (*codep >> 6) & 3;
12888       modrm.reg = (*codep >> 3) & 7;
12889       modrm.rm = *codep & 7;
12890       break;
12891
12892     case USE_VEX_C4_TABLE:
12893       /* VEX prefix.  */
12894       FETCH_DATA (info, codep + 3);
12895       /* All bits in the REX prefix are ignored.  */
12896       rex_ignored = rex;
12897       rex = ~(*codep >> 5) & 0x7;
12898       switch ((*codep & 0x1f))
12899         {
12900         default:
12901           dp = &bad_opcode;
12902           return dp;
12903         case 0x1:
12904           vex_table_index = VEX_0F;
12905           break;
12906         case 0x2:
12907           vex_table_index = VEX_0F38;
12908           break;
12909         case 0x3:
12910           vex_table_index = VEX_0F3A;
12911           break;
12912         }
12913       codep++;
12914       vex.w = *codep & 0x80;
12915       if (address_mode == mode_64bit)
12916         {
12917           if (vex.w)
12918             rex |= REX_W;
12919         }
12920       else
12921         {
12922           /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
12923              is ignored, other REX bits are 0 and the highest bit in
12924              VEX.vvvv is also ignored (but we mustn't clear it here).  */
12925           rex = 0;
12926         }
12927       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12928       vex.length = (*codep & 0x4) ? 256 : 128;
12929       switch ((*codep & 0x3))
12930         {
12931         case 0:
12932           break;
12933         case 1:
12934           vex.prefix = DATA_PREFIX_OPCODE;
12935           break;
12936         case 2:
12937           vex.prefix = REPE_PREFIX_OPCODE;
12938           break;
12939         case 3:
12940           vex.prefix = REPNE_PREFIX_OPCODE;
12941           break;
12942         }
12943       need_vex = 1;
12944       need_vex_reg = 1;
12945       codep++;
12946       vindex = *codep++;
12947       dp = &vex_table[vex_table_index][vindex];
12948       end_codep = codep;
12949       /* There is no MODRM byte for VEX0F 77.  */
12950       if (vex_table_index != VEX_0F || vindex != 0x77)
12951         {
12952           FETCH_DATA (info, codep + 1);
12953           modrm.mod = (*codep >> 6) & 3;
12954           modrm.reg = (*codep >> 3) & 7;
12955           modrm.rm = *codep & 7;
12956         }
12957       break;
12958
12959     case USE_VEX_C5_TABLE:
12960       /* VEX prefix.  */
12961       FETCH_DATA (info, codep + 2);
12962       /* All bits in the REX prefix are ignored.  */
12963       rex_ignored = rex;
12964       rex = (*codep & 0x80) ? 0 : REX_R;
12965
12966       /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
12967          VEX.vvvv is 1.  */
12968       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12969       vex.length = (*codep & 0x4) ? 256 : 128;
12970       switch ((*codep & 0x3))
12971         {
12972         case 0:
12973           break;
12974         case 1:
12975           vex.prefix = DATA_PREFIX_OPCODE;
12976           break;
12977         case 2:
12978           vex.prefix = REPE_PREFIX_OPCODE;
12979           break;
12980         case 3:
12981           vex.prefix = REPNE_PREFIX_OPCODE;
12982           break;
12983         }
12984       need_vex = 1;
12985       need_vex_reg = 1;
12986       codep++;
12987       vindex = *codep++;
12988       dp = &vex_table[dp->op[1].bytemode][vindex];
12989       end_codep = codep;
12990       /* There is no MODRM byte for VEX 77.  */
12991       if (vindex != 0x77)
12992         {
12993           FETCH_DATA (info, codep + 1);
12994           modrm.mod = (*codep >> 6) & 3;
12995           modrm.reg = (*codep >> 3) & 7;
12996           modrm.rm = *codep & 7;
12997         }
12998       break;
12999
13000     case USE_VEX_W_TABLE:
13001       if (!need_vex)
13002         abort ();
13003
13004       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
13005       break;
13006
13007     case USE_EVEX_TABLE:
13008       two_source_ops = 0;
13009       /* EVEX prefix.  */
13010       vex.evex = 1;
13011       FETCH_DATA (info, codep + 4);
13012       /* All bits in the REX prefix are ignored.  */
13013       rex_ignored = rex;
13014       /* The first byte after 0x62.  */
13015       rex = ~(*codep >> 5) & 0x7;
13016       vex.r = *codep & 0x10;
13017       switch ((*codep & 0xf))
13018         {
13019         default:
13020           return &bad_opcode;
13021         case 0x1:
13022           vex_table_index = EVEX_0F;
13023           break;
13024         case 0x2:
13025           vex_table_index = EVEX_0F38;
13026           break;
13027         case 0x3:
13028           vex_table_index = EVEX_0F3A;
13029           break;
13030         }
13031
13032       /* The second byte after 0x62.  */
13033       codep++;
13034       vex.w = *codep & 0x80;
13035       if (vex.w && address_mode == mode_64bit)
13036         rex |= REX_W;
13037
13038       vex.register_specifier = (~(*codep >> 3)) & 0xf;
13039
13040       /* The U bit.  */
13041       if (!(*codep & 0x4))
13042         return &bad_opcode;
13043
13044       switch ((*codep & 0x3))
13045         {
13046         case 0:
13047           break;
13048         case 1:
13049           vex.prefix = DATA_PREFIX_OPCODE;
13050           break;
13051         case 2:
13052           vex.prefix = REPE_PREFIX_OPCODE;
13053           break;
13054         case 3:
13055           vex.prefix = REPNE_PREFIX_OPCODE;
13056           break;
13057         }
13058
13059       /* The third byte after 0x62.  */
13060       codep++;
13061
13062       /* Remember the static rounding bits.  */
13063       vex.ll = (*codep >> 5) & 3;
13064       vex.b = (*codep & 0x10) != 0;
13065
13066       vex.v = *codep & 0x8;
13067       vex.mask_register_specifier = *codep & 0x7;
13068       vex.zeroing = *codep & 0x80;
13069
13070       if (address_mode != mode_64bit)
13071         {
13072           /* In 16/32-bit mode silently ignore following bits.  */
13073           rex &= ~REX_B;
13074           vex.r = 1;
13075           vex.v = 1;
13076         }
13077
13078       need_vex = 1;
13079       need_vex_reg = 1;
13080       codep++;
13081       vindex = *codep++;
13082       dp = &evex_table[vex_table_index][vindex];
13083       end_codep = codep;
13084       FETCH_DATA (info, codep + 1);
13085       modrm.mod = (*codep >> 6) & 3;
13086       modrm.reg = (*codep >> 3) & 7;
13087       modrm.rm = *codep & 7;
13088
13089       /* Set vector length.  */
13090       if (modrm.mod == 3 && vex.b)
13091         vex.length = 512;
13092       else
13093         {
13094           switch (vex.ll)
13095             {
13096             case 0x0:
13097               vex.length = 128;
13098               break;
13099             case 0x1:
13100               vex.length = 256;
13101               break;
13102             case 0x2:
13103               vex.length = 512;
13104               break;
13105             default:
13106               return &bad_opcode;
13107             }
13108         }
13109       break;
13110
13111     case 0:
13112       dp = &bad_opcode;
13113       break;
13114
13115     default:
13116       abort ();
13117     }
13118
13119   if (dp->name != NULL)
13120     return dp;
13121   else
13122     return get_valid_dis386 (dp, info);
13123 }
13124
13125 static void
13126 get_sib (disassemble_info *info, int sizeflag)
13127 {
13128   /* If modrm.mod == 3, operand must be register.  */
13129   if (need_modrm
13130       && ((sizeflag & AFLAG) || address_mode == mode_64bit)
13131       && modrm.mod != 3
13132       && modrm.rm == 4)
13133     {
13134       FETCH_DATA (info, codep + 2);
13135       sib.index = (codep [1] >> 3) & 7;
13136       sib.scale = (codep [1] >> 6) & 3;
13137       sib.base = codep [1] & 7;
13138     }
13139 }
13140
13141 static int
13142 print_insn (bfd_vma pc, disassemble_info *info)
13143 {
13144   const struct dis386 *dp;
13145   int i;
13146   char *op_txt[MAX_OPERANDS];
13147   int needcomma;
13148   int sizeflag, orig_sizeflag;
13149   const char *p;
13150   struct dis_private priv;
13151   int prefix_length;
13152
13153   priv.orig_sizeflag = AFLAG | DFLAG;
13154   if ((info->mach & bfd_mach_i386_i386) != 0)
13155     address_mode = mode_32bit;
13156   else if (info->mach == bfd_mach_i386_i8086)
13157     {
13158       address_mode = mode_16bit;
13159       priv.orig_sizeflag = 0;
13160     }
13161   else
13162     address_mode = mode_64bit;
13163
13164   if (intel_syntax == (char) -1)
13165     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
13166
13167   for (p = info->disassembler_options; p != NULL; )
13168     {
13169       if (CONST_STRNEQ (p, "amd64"))
13170         isa64 = amd64;
13171       else if (CONST_STRNEQ (p, "intel64"))
13172         isa64 = intel64;
13173       else if (CONST_STRNEQ (p, "x86-64"))
13174         {
13175           address_mode = mode_64bit;
13176           priv.orig_sizeflag = AFLAG | DFLAG;
13177         }
13178       else if (CONST_STRNEQ (p, "i386"))
13179         {
13180           address_mode = mode_32bit;
13181           priv.orig_sizeflag = AFLAG | DFLAG;
13182         }
13183       else if (CONST_STRNEQ (p, "i8086"))
13184         {
13185           address_mode = mode_16bit;
13186           priv.orig_sizeflag = 0;
13187         }
13188       else if (CONST_STRNEQ (p, "intel"))
13189         {
13190           intel_syntax = 1;
13191           if (CONST_STRNEQ (p + 5, "-mnemonic"))
13192             intel_mnemonic = 1;
13193         }
13194       else if (CONST_STRNEQ (p, "att"))
13195         {
13196           intel_syntax = 0;
13197           if (CONST_STRNEQ (p + 3, "-mnemonic"))
13198             intel_mnemonic = 0;
13199         }
13200       else if (CONST_STRNEQ (p, "addr"))
13201         {
13202           if (address_mode == mode_64bit)
13203             {
13204               if (p[4] == '3' && p[5] == '2')
13205                 priv.orig_sizeflag &= ~AFLAG;
13206               else if (p[4] == '6' && p[5] == '4')
13207                 priv.orig_sizeflag |= AFLAG;
13208             }
13209           else
13210             {
13211               if (p[4] == '1' && p[5] == '6')
13212                 priv.orig_sizeflag &= ~AFLAG;
13213               else if (p[4] == '3' && p[5] == '2')
13214                 priv.orig_sizeflag |= AFLAG;
13215             }
13216         }
13217       else if (CONST_STRNEQ (p, "data"))
13218         {
13219           if (p[4] == '1' && p[5] == '6')
13220             priv.orig_sizeflag &= ~DFLAG;
13221           else if (p[4] == '3' && p[5] == '2')
13222             priv.orig_sizeflag |= DFLAG;
13223         }
13224       else if (CONST_STRNEQ (p, "suffix"))
13225         priv.orig_sizeflag |= SUFFIX_ALWAYS;
13226
13227       p = strchr (p, ',');
13228       if (p != NULL)
13229         p++;
13230     }
13231
13232   if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
13233     {
13234       (*info->fprintf_func) (info->stream,
13235                              _("64-bit address is disabled"));
13236       return -1;
13237     }
13238
13239   if (intel_syntax)
13240     {
13241       names64 = intel_names64;
13242       names32 = intel_names32;
13243       names16 = intel_names16;
13244       names8 = intel_names8;
13245       names8rex = intel_names8rex;
13246       names_seg = intel_names_seg;
13247       names_mm = intel_names_mm;
13248       names_bnd = intel_names_bnd;
13249       names_xmm = intel_names_xmm;
13250       names_ymm = intel_names_ymm;
13251       names_zmm = intel_names_zmm;
13252       index64 = intel_index64;
13253       index32 = intel_index32;
13254       names_mask = intel_names_mask;
13255       index16 = intel_index16;
13256       open_char = '[';
13257       close_char = ']';
13258       separator_char = '+';
13259       scale_char = '*';
13260     }
13261   else
13262     {
13263       names64 = att_names64;
13264       names32 = att_names32;
13265       names16 = att_names16;
13266       names8 = att_names8;
13267       names8rex = att_names8rex;
13268       names_seg = att_names_seg;
13269       names_mm = att_names_mm;
13270       names_bnd = att_names_bnd;
13271       names_xmm = att_names_xmm;
13272       names_ymm = att_names_ymm;
13273       names_zmm = att_names_zmm;
13274       index64 = att_index64;
13275       index32 = att_index32;
13276       names_mask = att_names_mask;
13277       index16 = att_index16;
13278       open_char = '(';
13279       close_char =  ')';
13280       separator_char = ',';
13281       scale_char = ',';
13282     }
13283
13284   /* The output looks better if we put 7 bytes on a line, since that
13285      puts most long word instructions on a single line.  Use 8 bytes
13286      for Intel L1OM.  */
13287   if ((info->mach & bfd_mach_l1om) != 0)
13288     info->bytes_per_line = 8;
13289   else
13290     info->bytes_per_line = 7;
13291
13292   info->private_data = &priv;
13293   priv.max_fetched = priv.the_buffer;
13294   priv.insn_start = pc;
13295
13296   obuf[0] = 0;
13297   for (i = 0; i < MAX_OPERANDS; ++i)
13298     {
13299       op_out[i][0] = 0;
13300       op_index[i] = -1;
13301     }
13302
13303   the_info = info;
13304   start_pc = pc;
13305   start_codep = priv.the_buffer;
13306   codep = priv.the_buffer;
13307
13308   if (OPCODES_SIGSETJMP (priv.bailout) != 0)
13309     {
13310       const char *name;
13311
13312       /* Getting here means we tried for data but didn't get it.  That
13313          means we have an incomplete instruction of some sort.  Just
13314          print the first byte as a prefix or a .byte pseudo-op.  */
13315       if (codep > priv.the_buffer)
13316         {
13317           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
13318           if (name != NULL)
13319             (*info->fprintf_func) (info->stream, "%s", name);
13320           else
13321             {
13322               /* Just print the first byte as a .byte instruction.  */
13323               (*info->fprintf_func) (info->stream, ".byte 0x%x",
13324                                      (unsigned int) priv.the_buffer[0]);
13325             }
13326
13327           return 1;
13328         }
13329
13330       return -1;
13331     }
13332
13333   obufp = obuf;
13334   sizeflag = priv.orig_sizeflag;
13335
13336   if (!ckprefix () || rex_used)
13337     {
13338       /* Too many prefixes or unused REX prefixes.  */
13339       for (i = 0;
13340            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
13341            i++)
13342         (*info->fprintf_func) (info->stream, "%s%s",
13343                                i == 0 ? "" : " ",
13344                                prefix_name (all_prefixes[i], sizeflag));
13345       return i;
13346     }
13347
13348   insn_codep = codep;
13349
13350   FETCH_DATA (info, codep + 1);
13351   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
13352
13353   if (((prefixes & PREFIX_FWAIT)
13354        && ((*codep < 0xd8) || (*codep > 0xdf))))
13355     {
13356       /* Handle prefixes before fwait.  */
13357       for (i = 0; i < fwait_prefix && all_prefixes[i];
13358            i++)
13359         (*info->fprintf_func) (info->stream, "%s ",
13360                                prefix_name (all_prefixes[i], sizeflag));
13361       (*info->fprintf_func) (info->stream, "fwait");
13362       return i + 1;
13363     }
13364
13365   if (*codep == 0x0f)
13366     {
13367       unsigned char threebyte;
13368
13369       codep++;
13370       FETCH_DATA (info, codep + 1);
13371       threebyte = *codep;
13372       dp = &dis386_twobyte[threebyte];
13373       need_modrm = twobyte_has_modrm[*codep];
13374       codep++;
13375     }
13376   else
13377     {
13378       dp = &dis386[*codep];
13379       need_modrm = onebyte_has_modrm[*codep];
13380       codep++;
13381     }
13382
13383   /* Save sizeflag for printing the extra prefixes later before updating
13384      it for mnemonic and operand processing.  The prefix names depend
13385      only on the address mode.  */
13386   orig_sizeflag = sizeflag;
13387   if (prefixes & PREFIX_ADDR)
13388     sizeflag ^= AFLAG;
13389   if ((prefixes & PREFIX_DATA))
13390     sizeflag ^= DFLAG;
13391
13392   end_codep = codep;
13393   if (need_modrm)
13394     {
13395       FETCH_DATA (info, codep + 1);
13396       modrm.mod = (*codep >> 6) & 3;
13397       modrm.reg = (*codep >> 3) & 7;
13398       modrm.rm = *codep & 7;
13399     }
13400
13401   need_vex = 0;
13402   need_vex_reg = 0;
13403   vex_w_done = 0;
13404   memset (&vex, 0, sizeof (vex));
13405
13406   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
13407     {
13408       get_sib (info, sizeflag);
13409       dofloat (sizeflag);
13410     }
13411   else
13412     {
13413       dp = get_valid_dis386 (dp, info);
13414       if (dp != NULL && putop (dp->name, sizeflag) == 0)
13415         {
13416           get_sib (info, sizeflag);
13417           for (i = 0; i < MAX_OPERANDS; ++i)
13418             {
13419               obufp = op_out[i];
13420               op_ad = MAX_OPERANDS - 1 - i;
13421               if (dp->op[i].rtn)
13422                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
13423               /* For EVEX instruction after the last operand masking
13424                  should be printed.  */
13425               if (i == 0 && vex.evex)
13426                 {
13427                   /* Don't print {%k0}.  */
13428                   if (vex.mask_register_specifier)
13429                     {
13430                       oappend ("{");
13431                       oappend (names_mask[vex.mask_register_specifier]);
13432                       oappend ("}");
13433                     }
13434                   if (vex.zeroing)
13435                     oappend ("{z}");
13436                 }
13437             }
13438         }
13439     }
13440
13441   /* Check if the REX prefix is used.  */
13442   if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)
13443     all_prefixes[last_rex_prefix] = 0;
13444
13445   /* Check if the SEG prefix is used.  */
13446   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
13447                    | PREFIX_FS | PREFIX_GS)) != 0
13448       && (used_prefixes & active_seg_prefix) != 0)
13449     all_prefixes[last_seg_prefix] = 0;
13450
13451   /* Check if the ADDR prefix is used.  */
13452   if ((prefixes & PREFIX_ADDR) != 0
13453       && (used_prefixes & PREFIX_ADDR) != 0)
13454     all_prefixes[last_addr_prefix] = 0;
13455
13456   /* Check if the DATA prefix is used.  */
13457   if ((prefixes & PREFIX_DATA) != 0
13458       && (used_prefixes & PREFIX_DATA) != 0)
13459     all_prefixes[last_data_prefix] = 0;
13460
13461   /* Print the extra prefixes.  */
13462   prefix_length = 0;
13463   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
13464     if (all_prefixes[i])
13465       {
13466         const char *name;
13467         name = prefix_name (all_prefixes[i], orig_sizeflag);
13468         if (name == NULL)
13469           abort ();
13470         prefix_length += strlen (name) + 1;
13471         (*info->fprintf_func) (info->stream, "%s ", name);
13472       }
13473
13474   /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
13475      unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
13476      used by putop and MMX/SSE operand and may be overriden by the
13477      PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
13478      separately.  */
13479   if (dp->prefix_requirement == PREFIX_OPCODE
13480       && dp != &bad_opcode
13481       && (((prefixes
13482             & (PREFIX_REPZ | PREFIX_REPNZ)) != 0
13483            && (used_prefixes
13484                & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
13485           || ((((prefixes
13486                  & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
13487                 == PREFIX_DATA)
13488                && (used_prefixes & PREFIX_DATA) == 0))))
13489     {
13490       (*info->fprintf_func) (info->stream, "(bad)");
13491       return end_codep - priv.the_buffer;
13492     }
13493
13494   /* Check maximum code length.  */
13495   if ((codep - start_codep) > MAX_CODE_LENGTH)
13496     {
13497       (*info->fprintf_func) (info->stream, "(bad)");
13498       return MAX_CODE_LENGTH;
13499     }
13500
13501   obufp = mnemonicendp;
13502   for (i = strlen (obuf) + prefix_length; i < 6; i++)
13503     oappend (" ");
13504   oappend (" ");
13505   (*info->fprintf_func) (info->stream, "%s", obuf);
13506
13507   /* The enter and bound instructions are printed with operands in the same
13508      order as the intel book; everything else is printed in reverse order.  */
13509   if (intel_syntax || two_source_ops)
13510     {
13511       bfd_vma riprel;
13512
13513       for (i = 0; i < MAX_OPERANDS; ++i)
13514         op_txt[i] = op_out[i];
13515
13516       if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
13517           && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
13518         {
13519           op_txt[2] = op_out[3];
13520           op_txt[3] = op_out[2];
13521         }
13522
13523       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
13524         {
13525           op_ad = op_index[i];
13526           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
13527           op_index[MAX_OPERANDS - 1 - i] = op_ad;
13528           riprel = op_riprel[i];
13529           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
13530           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
13531         }
13532     }
13533   else
13534     {
13535       for (i = 0; i < MAX_OPERANDS; ++i)
13536         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
13537     }
13538
13539   needcomma = 0;
13540   for (i = 0; i < MAX_OPERANDS; ++i)
13541     if (*op_txt[i])
13542       {
13543         if (needcomma)
13544           (*info->fprintf_func) (info->stream, ",");
13545         if (op_index[i] != -1 && !op_riprel[i])
13546           (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
13547         else
13548           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
13549         needcomma = 1;
13550       }
13551
13552   for (i = 0; i < MAX_OPERANDS; i++)
13553     if (op_index[i] != -1 && op_riprel[i])
13554       {
13555         (*info->fprintf_func) (info->stream, "        # ");
13556         (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
13557                                                 + op_address[op_index[i]]), info);
13558         break;
13559       }
13560   return codep - priv.the_buffer;
13561 }
13562
13563 static const char *float_mem[] = {
13564   /* d8 */
13565   "fadd{s|}",
13566   "fmul{s|}",
13567   "fcom{s|}",
13568   "fcomp{s|}",
13569   "fsub{s|}",
13570   "fsubr{s|}",
13571   "fdiv{s|}",
13572   "fdivr{s|}",
13573   /* d9 */
13574   "fld{s|}",
13575   "(bad)",
13576   "fst{s|}",
13577   "fstp{s|}",
13578   "fldenvIC",
13579   "fldcw",
13580   "fNstenvIC",
13581   "fNstcw",
13582   /* da */
13583   "fiadd{l|}",
13584   "fimul{l|}",
13585   "ficom{l|}",
13586   "ficomp{l|}",
13587   "fisub{l|}",
13588   "fisubr{l|}",
13589   "fidiv{l|}",
13590   "fidivr{l|}",
13591   /* db */
13592   "fild{l|}",
13593   "fisttp{l|}",
13594   "fist{l|}",
13595   "fistp{l|}",
13596   "(bad)",
13597   "fld{t||t|}",
13598   "(bad)",
13599   "fstp{t||t|}",
13600   /* dc */
13601   "fadd{l|}",
13602   "fmul{l|}",
13603   "fcom{l|}",
13604   "fcomp{l|}",
13605   "fsub{l|}",
13606   "fsubr{l|}",
13607   "fdiv{l|}",
13608   "fdivr{l|}",
13609   /* dd */
13610   "fld{l|}",
13611   "fisttp{ll|}",
13612   "fst{l||}",
13613   "fstp{l|}",
13614   "frstorIC",
13615   "(bad)",
13616   "fNsaveIC",
13617   "fNstsw",
13618   /* de */
13619   "fiadd{s|}",
13620   "fimul{s|}",
13621   "ficom{s|}",
13622   "ficomp{s|}",
13623   "fisub{s|}",
13624   "fisubr{s|}",
13625   "fidiv{s|}",
13626   "fidivr{s|}",
13627   /* df */
13628   "fild{s|}",
13629   "fisttp{s|}",
13630   "fist{s|}",
13631   "fistp{s|}",
13632   "fbld",
13633   "fild{ll|}",
13634   "fbstp",
13635   "fistp{ll|}",
13636 };
13637
13638 static const unsigned char float_mem_mode[] = {
13639   /* d8 */
13640   d_mode,
13641   d_mode,
13642   d_mode,
13643   d_mode,
13644   d_mode,
13645   d_mode,
13646   d_mode,
13647   d_mode,
13648   /* d9 */
13649   d_mode,
13650   0,
13651   d_mode,
13652   d_mode,
13653   0,
13654   w_mode,
13655   0,
13656   w_mode,
13657   /* da */
13658   d_mode,
13659   d_mode,
13660   d_mode,
13661   d_mode,
13662   d_mode,
13663   d_mode,
13664   d_mode,
13665   d_mode,
13666   /* db */
13667   d_mode,
13668   d_mode,
13669   d_mode,
13670   d_mode,
13671   0,
13672   t_mode,
13673   0,
13674   t_mode,
13675   /* dc */
13676   q_mode,
13677   q_mode,
13678   q_mode,
13679   q_mode,
13680   q_mode,
13681   q_mode,
13682   q_mode,
13683   q_mode,
13684   /* dd */
13685   q_mode,
13686   q_mode,
13687   q_mode,
13688   q_mode,
13689   0,
13690   0,
13691   0,
13692   w_mode,
13693   /* de */
13694   w_mode,
13695   w_mode,
13696   w_mode,
13697   w_mode,
13698   w_mode,
13699   w_mode,
13700   w_mode,
13701   w_mode,
13702   /* df */
13703   w_mode,
13704   w_mode,
13705   w_mode,
13706   w_mode,
13707   t_mode,
13708   q_mode,
13709   t_mode,
13710   q_mode
13711 };
13712
13713 #define ST { OP_ST, 0 }
13714 #define STi { OP_STi, 0 }
13715
13716 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
13717 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
13718 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
13719 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
13720 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
13721 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
13722 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
13723 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
13724 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
13725
13726 static const struct dis386 float_reg[][8] = {
13727   /* d8 */
13728   {
13729     { "fadd",   { ST, STi }, 0 },
13730     { "fmul",   { ST, STi }, 0 },
13731     { "fcom",   { STi }, 0 },
13732     { "fcomp",  { STi }, 0 },
13733     { "fsub",   { ST, STi }, 0 },
13734     { "fsubr",  { ST, STi }, 0 },
13735     { "fdiv",   { ST, STi }, 0 },
13736     { "fdivr",  { ST, STi }, 0 },
13737   },
13738   /* d9 */
13739   {
13740     { "fld",    { STi }, 0 },
13741     { "fxch",   { STi }, 0 },
13742     { FGRPd9_2 },
13743     { Bad_Opcode },
13744     { FGRPd9_4 },
13745     { FGRPd9_5 },
13746     { FGRPd9_6 },
13747     { FGRPd9_7 },
13748   },
13749   /* da */
13750   {
13751     { "fcmovb", { ST, STi }, 0 },
13752     { "fcmove", { ST, STi }, 0 },
13753     { "fcmovbe",{ ST, STi }, 0 },
13754     { "fcmovu", { ST, STi }, 0 },
13755     { Bad_Opcode },
13756     { FGRPda_5 },
13757     { Bad_Opcode },
13758     { Bad_Opcode },
13759   },
13760   /* db */
13761   {
13762     { "fcmovnb",{ ST, STi }, 0 },
13763     { "fcmovne",{ ST, STi }, 0 },
13764     { "fcmovnbe",{ ST, STi }, 0 },
13765     { "fcmovnu",{ ST, STi }, 0 },
13766     { FGRPdb_4 },
13767     { "fucomi", { ST, STi }, 0 },
13768     { "fcomi",  { ST, STi }, 0 },
13769     { Bad_Opcode },
13770   },
13771   /* dc */
13772   {
13773     { "fadd",   { STi, ST }, 0 },
13774     { "fmul",   { STi, ST }, 0 },
13775     { Bad_Opcode },
13776     { Bad_Opcode },
13777     { "fsub{!M|r}",     { STi, ST }, 0 },
13778     { "fsub{M|}",       { STi, ST }, 0 },
13779     { "fdiv{!M|r}",     { STi, ST }, 0 },
13780     { "fdiv{M|}",       { STi, ST }, 0 },
13781   },
13782   /* dd */
13783   {
13784     { "ffree",  { STi }, 0 },
13785     { Bad_Opcode },
13786     { "fst",    { STi }, 0 },
13787     { "fstp",   { STi }, 0 },
13788     { "fucom",  { STi }, 0 },
13789     { "fucomp", { STi }, 0 },
13790     { Bad_Opcode },
13791     { Bad_Opcode },
13792   },
13793   /* de */
13794   {
13795     { "faddp",  { STi, ST }, 0 },
13796     { "fmulp",  { STi, ST }, 0 },
13797     { Bad_Opcode },
13798     { FGRPde_3 },
13799     { "fsub{!M|r}p",    { STi, ST }, 0 },
13800     { "fsub{M|}p",      { STi, ST }, 0 },
13801     { "fdiv{!M|r}p",    { STi, ST }, 0 },
13802     { "fdiv{M|}p",      { STi, ST }, 0 },
13803   },
13804   /* df */
13805   {
13806     { "ffreep", { STi }, 0 },
13807     { Bad_Opcode },
13808     { Bad_Opcode },
13809     { Bad_Opcode },
13810     { FGRPdf_4 },
13811     { "fucomip", { ST, STi }, 0 },
13812     { "fcomip", { ST, STi }, 0 },
13813     { Bad_Opcode },
13814   },
13815 };
13816
13817 static char *fgrps[][8] = {
13818   /* Bad opcode 0 */
13819   {
13820     "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13821   },
13822
13823   /* d9_2  1 */
13824   {
13825     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13826   },
13827
13828   /* d9_4  2 */
13829   {
13830     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
13831   },
13832
13833   /* d9_5  3 */
13834   {
13835     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
13836   },
13837
13838   /* d9_6  4 */
13839   {
13840     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
13841   },
13842
13843   /* d9_7  5 */
13844   {
13845     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
13846   },
13847
13848   /* da_5  6 */
13849   {
13850     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13851   },
13852
13853   /* db_4  7 */
13854   {
13855     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
13856     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
13857   },
13858
13859   /* de_3  8 */
13860   {
13861     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13862   },
13863
13864   /* df_4  9 */
13865   {
13866     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13867   },
13868 };
13869
13870 static void
13871 swap_operand (void)
13872 {
13873   mnemonicendp[0] = '.';
13874   mnemonicendp[1] = 's';
13875   mnemonicendp += 2;
13876 }
13877
13878 static void
13879 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
13880                int sizeflag ATTRIBUTE_UNUSED)
13881 {
13882   /* Skip mod/rm byte.  */
13883   MODRM_CHECK;
13884   codep++;
13885 }
13886
13887 static void
13888 dofloat (int sizeflag)
13889 {
13890   const struct dis386 *dp;
13891   unsigned char floatop;
13892
13893   floatop = codep[-1];
13894
13895   if (modrm.mod != 3)
13896     {
13897       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
13898
13899       putop (float_mem[fp_indx], sizeflag);
13900       obufp = op_out[0];
13901       op_ad = 2;
13902       OP_E (float_mem_mode[fp_indx], sizeflag);
13903       return;
13904     }
13905   /* Skip mod/rm byte.  */
13906   MODRM_CHECK;
13907   codep++;
13908
13909   dp = &float_reg[floatop - 0xd8][modrm.reg];
13910   if (dp->name == NULL)
13911     {
13912       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
13913
13914       /* Instruction fnstsw is only one with strange arg.  */
13915       if (floatop == 0xdf && codep[-1] == 0xe0)
13916         strcpy (op_out[0], names16[0]);
13917     }
13918   else
13919     {
13920       putop (dp->name, sizeflag);
13921
13922       obufp = op_out[0];
13923       op_ad = 2;
13924       if (dp->op[0].rtn)
13925         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
13926
13927       obufp = op_out[1];
13928       op_ad = 1;
13929       if (dp->op[1].rtn)
13930         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
13931     }
13932 }
13933
13934 /* Like oappend (below), but S is a string starting with '%'.
13935    In Intel syntax, the '%' is elided.  */
13936 static void
13937 oappend_maybe_intel (const char *s)
13938 {
13939   oappend (s + intel_syntax);
13940 }
13941
13942 static void
13943 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13944 {
13945   oappend_maybe_intel ("%st");
13946 }
13947
13948 static void
13949 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13950 {
13951   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
13952   oappend_maybe_intel (scratchbuf);
13953 }
13954
13955 /* Capital letters in template are macros.  */
13956 static int
13957 putop (const char *in_template, int sizeflag)
13958 {
13959   const char *p;
13960   int alt = 0;
13961   int cond = 1;
13962   unsigned int l = 0, len = 1;
13963   char last[4];
13964
13965 #define SAVE_LAST(c)                    \
13966   if (l < len && l < sizeof (last))     \
13967     last[l++] = c;                      \
13968   else                                  \
13969     abort ();
13970
13971   for (p = in_template; *p; p++)
13972     {
13973       switch (*p)
13974         {
13975         default:
13976           *obufp++ = *p;
13977           break;
13978         case '%':
13979           len++;
13980           break;
13981         case '!':
13982           cond = 0;
13983           break;
13984         case '{':
13985           if (intel_syntax)
13986             {
13987               while (*++p != '|')
13988                 if (*p == '}' || *p == '\0')
13989                   abort ();
13990             }
13991           /* Fall through.  */
13992         case 'I':
13993           alt = 1;
13994           continue;
13995         case '|':
13996           while (*++p != '}')
13997             {
13998               if (*p == '\0')
13999                 abort ();
14000             }
14001           break;
14002         case '}':
14003           break;
14004         case 'A':
14005           if (intel_syntax)
14006             break;
14007           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
14008             *obufp++ = 'b';
14009           break;
14010         case 'B':
14011           if (l == 0 && len == 1)
14012             {
14013 case_B:
14014               if (intel_syntax)
14015                 break;
14016               if (sizeflag & SUFFIX_ALWAYS)
14017                 *obufp++ = 'b';
14018             }
14019           else
14020             {
14021               if (l != 1
14022                   || len != 2
14023                   || last[0] != 'L')
14024                 {
14025                   SAVE_LAST (*p);
14026                   break;
14027                 }
14028
14029               if (address_mode == mode_64bit
14030                   && !(prefixes & PREFIX_ADDR))
14031                 {
14032                   *obufp++ = 'a';
14033                   *obufp++ = 'b';
14034                   *obufp++ = 's';
14035                 }
14036
14037               goto case_B;
14038             }
14039           break;
14040         case 'C':
14041           if (intel_syntax && !alt)
14042             break;
14043           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
14044             {
14045               if (sizeflag & DFLAG)
14046                 *obufp++ = intel_syntax ? 'd' : 'l';
14047               else
14048                 *obufp++ = intel_syntax ? 'w' : 's';
14049               used_prefixes |= (prefixes & PREFIX_DATA);
14050             }
14051           break;
14052         case 'D':
14053           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
14054             break;
14055           USED_REX (REX_W);
14056           if (modrm.mod == 3)
14057             {
14058               if (rex & REX_W)
14059                 *obufp++ = 'q';
14060               else
14061                 {
14062                   if (sizeflag & DFLAG)
14063                     *obufp++ = intel_syntax ? 'd' : 'l';
14064                   else
14065                     *obufp++ = 'w';
14066                   used_prefixes |= (prefixes & PREFIX_DATA);
14067                 }
14068             }
14069           else
14070             *obufp++ = 'w';
14071           break;
14072         case 'E':               /* For jcxz/jecxz */
14073           if (address_mode == mode_64bit)
14074             {
14075               if (sizeflag & AFLAG)
14076                 *obufp++ = 'r';
14077               else
14078                 *obufp++ = 'e';
14079             }
14080           else
14081             if (sizeflag & AFLAG)
14082               *obufp++ = 'e';
14083           used_prefixes |= (prefixes & PREFIX_ADDR);
14084           break;
14085         case 'F':
14086           if (intel_syntax)
14087             break;
14088           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
14089             {
14090               if (sizeflag & AFLAG)
14091                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
14092               else
14093                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
14094               used_prefixes |= (prefixes & PREFIX_ADDR);
14095             }
14096           break;
14097         case 'G':
14098           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
14099             break;
14100           if ((rex & REX_W) || (sizeflag & DFLAG))
14101             *obufp++ = 'l';
14102           else
14103             *obufp++ = 'w';
14104           if (!(rex & REX_W))
14105             used_prefixes |= (prefixes & PREFIX_DATA);
14106           break;
14107         case 'H':
14108           if (intel_syntax)
14109             break;
14110           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
14111               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
14112             {
14113               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
14114               *obufp++ = ',';
14115               *obufp++ = 'p';
14116               if (prefixes & PREFIX_DS)
14117                 *obufp++ = 't';
14118               else
14119                 *obufp++ = 'n';
14120             }
14121           break;
14122         case 'J':
14123           if (intel_syntax)
14124             break;
14125           *obufp++ = 'l';
14126           break;
14127         case 'K':
14128           USED_REX (REX_W);
14129           if (rex & REX_W)
14130             *obufp++ = 'q';
14131           else
14132             *obufp++ = 'd';
14133           break;
14134         case 'Z':
14135           if (l != 0 || len != 1)
14136             {
14137               if (l != 1 || len != 2 || last[0] != 'X')
14138                 {
14139                   SAVE_LAST (*p);
14140                   break;
14141                 }
14142               if (!need_vex || !vex.evex)
14143                 abort ();
14144               if (intel_syntax
14145                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
14146                 break;
14147               switch (vex.length)
14148                 {
14149                 case 128:
14150                   *obufp++ = 'x';
14151                   break;
14152                 case 256:
14153                   *obufp++ = 'y';
14154                   break;
14155                 case 512:
14156                   *obufp++ = 'z';
14157                   break;
14158                 default:
14159                   abort ();
14160                 }
14161               break;
14162             }
14163           if (intel_syntax)
14164             break;
14165           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
14166             {
14167               *obufp++ = 'q';
14168               break;
14169             }
14170           /* Fall through.  */
14171           goto case_L;
14172         case 'L':
14173           if (l != 0 || len != 1)
14174             {
14175               SAVE_LAST (*p);
14176               break;
14177             }
14178 case_L:
14179           if (intel_syntax)
14180             break;
14181           if (sizeflag & SUFFIX_ALWAYS)
14182             *obufp++ = 'l';
14183           break;
14184         case 'M':
14185           if (intel_mnemonic != cond)
14186             *obufp++ = 'r';
14187           break;
14188         case 'N':
14189           if ((prefixes & PREFIX_FWAIT) == 0)
14190             *obufp++ = 'n';
14191           else
14192             used_prefixes |= PREFIX_FWAIT;
14193           break;
14194         case 'O':
14195           USED_REX (REX_W);
14196           if (rex & REX_W)
14197             *obufp++ = 'o';
14198           else if (intel_syntax && (sizeflag & DFLAG))
14199             *obufp++ = 'q';
14200           else
14201             *obufp++ = 'd';
14202           if (!(rex & REX_W))
14203             used_prefixes |= (prefixes & PREFIX_DATA);
14204           break;
14205         case '&':
14206           if (!intel_syntax
14207               && address_mode == mode_64bit
14208               && isa64 == intel64)
14209             {
14210               *obufp++ = 'q';
14211               break;
14212             }
14213           /* Fall through.  */
14214         case 'T':
14215           if (!intel_syntax
14216               && address_mode == mode_64bit
14217               && ((sizeflag & DFLAG) || (rex & REX_W)))
14218             {
14219               *obufp++ = 'q';
14220               break;
14221             }
14222           /* Fall through.  */
14223           goto case_P;
14224         case 'P':
14225           if (l == 0 && len == 1)
14226             {
14227 case_P:
14228               if (intel_syntax)
14229                 {
14230                   if ((rex & REX_W) == 0
14231                       && (prefixes & PREFIX_DATA))
14232                     {
14233                       if ((sizeflag & DFLAG) == 0)
14234                         *obufp++ = 'w';
14235                       used_prefixes |= (prefixes & PREFIX_DATA);
14236                     }
14237                   break;
14238                 }
14239               if ((prefixes & PREFIX_DATA)
14240                   || (rex & REX_W)
14241                   || (sizeflag & SUFFIX_ALWAYS))
14242                 {
14243                   USED_REX (REX_W);
14244                   if (rex & REX_W)
14245                     *obufp++ = 'q';
14246                   else
14247                     {
14248                       if (sizeflag & DFLAG)
14249                         *obufp++ = 'l';
14250                       else
14251                         *obufp++ = 'w';
14252                       used_prefixes |= (prefixes & PREFIX_DATA);
14253                     }
14254                 }
14255             }
14256           else
14257             {
14258               if (l != 1 || len != 2 || last[0] != 'L')
14259                 {
14260                   SAVE_LAST (*p);
14261                   break;
14262                 }
14263
14264               if ((prefixes & PREFIX_DATA)
14265                   || (rex & REX_W)
14266                   || (sizeflag & SUFFIX_ALWAYS))
14267                 {
14268                   USED_REX (REX_W);
14269                   if (rex & REX_W)
14270                     *obufp++ = 'q';
14271                   else
14272                     {
14273                       if (sizeflag & DFLAG)
14274                         *obufp++ = intel_syntax ? 'd' : 'l';
14275                       else
14276                         *obufp++ = 'w';
14277                       used_prefixes |= (prefixes & PREFIX_DATA);
14278                     }
14279                 }
14280             }
14281           break;
14282         case 'U':
14283           if (intel_syntax)
14284             break;
14285           if (address_mode == mode_64bit
14286               && ((sizeflag & DFLAG) || (rex & REX_W)))
14287             {
14288               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
14289                 *obufp++ = 'q';
14290               break;
14291             }
14292           /* Fall through.  */
14293           goto case_Q;
14294         case 'Q':
14295           if (l == 0 && len == 1)
14296             {
14297 case_Q:
14298               if (intel_syntax && !alt)
14299                 break;
14300               USED_REX (REX_W);
14301               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
14302                 {
14303                   if (rex & REX_W)
14304                     *obufp++ = 'q';
14305                   else
14306                     {
14307                       if (sizeflag & DFLAG)
14308                         *obufp++ = intel_syntax ? 'd' : 'l';
14309                       else
14310                         *obufp++ = 'w';
14311                       used_prefixes |= (prefixes & PREFIX_DATA);
14312                     }
14313                 }
14314             }
14315           else
14316             {
14317               if (l != 1 || len != 2 || last[0] != 'L')
14318                 {
14319                   SAVE_LAST (*p);
14320                   break;
14321                 }
14322               if (intel_syntax
14323                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
14324                 break;
14325               if ((rex & REX_W))
14326                 {
14327                   USED_REX (REX_W);
14328                   *obufp++ = 'q';
14329                 }
14330               else
14331                 *obufp++ = 'l';
14332             }
14333           break;
14334         case 'R':
14335           USED_REX (REX_W);
14336           if (rex & REX_W)
14337             *obufp++ = 'q';
14338           else if (sizeflag & DFLAG)
14339             {
14340               if (intel_syntax)
14341                   *obufp++ = 'd';
14342               else
14343                   *obufp++ = 'l';
14344             }
14345           else
14346             *obufp++ = 'w';
14347           if (intel_syntax && !p[1]
14348               && ((rex & REX_W) || (sizeflag & DFLAG)))
14349             *obufp++ = 'e';
14350           if (!(rex & REX_W))
14351             used_prefixes |= (prefixes & PREFIX_DATA);
14352           break;
14353         case 'V':
14354           if (l == 0 && len == 1)
14355             {
14356               if (intel_syntax)
14357                 break;
14358               if (address_mode == mode_64bit
14359                   && ((sizeflag & DFLAG) || (rex & REX_W)))
14360                 {
14361                   if (sizeflag & SUFFIX_ALWAYS)
14362                     *obufp++ = 'q';
14363                   break;
14364                 }
14365             }
14366           else
14367             {
14368               if (l != 1
14369                   || len != 2
14370                   || last[0] != 'L')
14371                 {
14372                   SAVE_LAST (*p);
14373                   break;
14374                 }
14375
14376               if (rex & REX_W)
14377                 {
14378                   *obufp++ = 'a';
14379                   *obufp++ = 'b';
14380                   *obufp++ = 's';
14381                 }
14382             }
14383           /* Fall through.  */
14384           goto case_S;
14385         case 'S':
14386           if (l == 0 && len == 1)
14387             {
14388 case_S:
14389               if (intel_syntax)
14390                 break;
14391               if (sizeflag & SUFFIX_ALWAYS)
14392                 {
14393                   if (rex & REX_W)
14394                     *obufp++ = 'q';
14395                   else
14396                     {
14397                       if (sizeflag & DFLAG)
14398                         *obufp++ = 'l';
14399                       else
14400                         *obufp++ = 'w';
14401                       used_prefixes |= (prefixes & PREFIX_DATA);
14402                     }
14403                 }
14404             }
14405           else
14406             {
14407               if (l != 1
14408                   || len != 2
14409                   || last[0] != 'L')
14410                 {
14411                   SAVE_LAST (*p);
14412                   break;
14413                 }
14414
14415               if (address_mode == mode_64bit
14416                   && !(prefixes & PREFIX_ADDR))
14417                 {
14418                   *obufp++ = 'a';
14419                   *obufp++ = 'b';
14420                   *obufp++ = 's';
14421                 }
14422
14423               goto case_S;
14424             }
14425           break;
14426         case 'X':
14427           if (l != 0 || len != 1)
14428             {
14429               SAVE_LAST (*p);
14430               break;
14431             }
14432           if (need_vex && vex.prefix)
14433             {
14434               if (vex.prefix == DATA_PREFIX_OPCODE)
14435                 *obufp++ = 'd';
14436               else
14437                 *obufp++ = 's';
14438             }
14439           else
14440             {
14441               if (prefixes & PREFIX_DATA)
14442                 *obufp++ = 'd';
14443               else
14444                 *obufp++ = 's';
14445               used_prefixes |= (prefixes & PREFIX_DATA);
14446             }
14447           break;
14448         case 'Y':
14449           if (l == 0 && len == 1)
14450             abort ();
14451           else
14452             {
14453               if (l != 1 || len != 2 || last[0] != 'X')
14454                 {
14455                   SAVE_LAST (*p);
14456                   break;
14457                 }
14458               if (!need_vex)
14459                 abort ();
14460               if (intel_syntax
14461                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
14462                 break;
14463               switch (vex.length)
14464                 {
14465                 case 128:
14466                   *obufp++ = 'x';
14467                   break;
14468                 case 256:
14469                   *obufp++ = 'y';
14470                   break;
14471                 case 512:
14472                   if (!vex.evex)
14473                 default:
14474                     abort ();
14475                 }
14476             }
14477           break;
14478         case 'W':
14479           if (l == 0 && len == 1)
14480             {
14481               /* operand size flag for cwtl, cbtw */
14482               USED_REX (REX_W);
14483               if (rex & REX_W)
14484                 {
14485                   if (intel_syntax)
14486                     *obufp++ = 'd';
14487                   else
14488                     *obufp++ = 'l';
14489                 }
14490               else if (sizeflag & DFLAG)
14491                 *obufp++ = 'w';
14492               else
14493                 *obufp++ = 'b';
14494               if (!(rex & REX_W))
14495                 used_prefixes |= (prefixes & PREFIX_DATA);
14496             }
14497           else
14498             {
14499               if (l != 1
14500                   || len != 2
14501                   || (last[0] != 'X'
14502                       && last[0] != 'L'))
14503                 {
14504                   SAVE_LAST (*p);
14505                   break;
14506                 }
14507               if (!need_vex)
14508                 abort ();
14509               if (last[0] == 'X')
14510                 *obufp++ = vex.w ? 'd': 's';
14511               else
14512                 *obufp++ = vex.w ? 'q': 'd';
14513             }
14514           break;
14515         case '^':
14516           if (intel_syntax)
14517             break;
14518           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
14519             {
14520               if (sizeflag & DFLAG)
14521                 *obufp++ = 'l';
14522               else
14523                 *obufp++ = 'w';
14524               used_prefixes |= (prefixes & PREFIX_DATA);
14525             }
14526           break;
14527         case '@':
14528           if (intel_syntax)
14529             break;
14530           if (address_mode == mode_64bit
14531               && (isa64 == intel64
14532                   || ((sizeflag & DFLAG) || (rex & REX_W))))
14533               *obufp++ = 'q';
14534           else if ((prefixes & PREFIX_DATA))
14535             {
14536               if (!(sizeflag & DFLAG))
14537                 *obufp++ = 'w';
14538               used_prefixes |= (prefixes & PREFIX_DATA);
14539             }
14540           break;
14541         }
14542       alt = 0;
14543     }
14544   *obufp = 0;
14545   mnemonicendp = obufp;
14546   return 0;
14547 }
14548
14549 static void
14550 oappend (const char *s)
14551 {
14552   obufp = stpcpy (obufp, s);
14553 }
14554
14555 static void
14556 append_seg (void)
14557 {
14558   /* Only print the active segment register.  */
14559   if (!active_seg_prefix)
14560     return;
14561
14562   used_prefixes |= active_seg_prefix;
14563   switch (active_seg_prefix)
14564     {
14565     case PREFIX_CS:
14566       oappend_maybe_intel ("%cs:");
14567       break;
14568     case PREFIX_DS:
14569       oappend_maybe_intel ("%ds:");
14570       break;
14571     case PREFIX_SS:
14572       oappend_maybe_intel ("%ss:");
14573       break;
14574     case PREFIX_ES:
14575       oappend_maybe_intel ("%es:");
14576       break;
14577     case PREFIX_FS:
14578       oappend_maybe_intel ("%fs:");
14579       break;
14580     case PREFIX_GS:
14581       oappend_maybe_intel ("%gs:");
14582       break;
14583     default:
14584       break;
14585     }
14586 }
14587
14588 static void
14589 OP_indirE (int bytemode, int sizeflag)
14590 {
14591   if (!intel_syntax)
14592     oappend ("*");
14593   OP_E (bytemode, sizeflag);
14594 }
14595
14596 static void
14597 print_operand_value (char *buf, int hex, bfd_vma disp)
14598 {
14599   if (address_mode == mode_64bit)
14600     {
14601       if (hex)
14602         {
14603           char tmp[30];
14604           int i;
14605           buf[0] = '0';
14606           buf[1] = 'x';
14607           sprintf_vma (tmp, disp);
14608           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
14609           strcpy (buf + 2, tmp + i);
14610         }
14611       else
14612         {
14613           bfd_signed_vma v = disp;
14614           char tmp[30];
14615           int i;
14616           if (v < 0)
14617             {
14618               *(buf++) = '-';
14619               v = -disp;
14620               /* Check for possible overflow on 0x8000000000000000.  */
14621               if (v < 0)
14622                 {
14623                   strcpy (buf, "9223372036854775808");
14624                   return;
14625                 }
14626             }
14627           if (!v)
14628             {
14629               strcpy (buf, "0");
14630               return;
14631             }
14632
14633           i = 0;
14634           tmp[29] = 0;
14635           while (v)
14636             {
14637               tmp[28 - i] = (v % 10) + '0';
14638               v /= 10;
14639               i++;
14640             }
14641           strcpy (buf, tmp + 29 - i);
14642         }
14643     }
14644   else
14645     {
14646       if (hex)
14647         sprintf (buf, "0x%x", (unsigned int) disp);
14648       else
14649         sprintf (buf, "%d", (int) disp);
14650     }
14651 }
14652
14653 /* Put DISP in BUF as signed hex number.  */
14654
14655 static void
14656 print_displacement (char *buf, bfd_vma disp)
14657 {
14658   bfd_signed_vma val = disp;
14659   char tmp[30];
14660   int i, j = 0;
14661
14662   if (val < 0)
14663     {
14664       buf[j++] = '-';
14665       val = -disp;
14666
14667       /* Check for possible overflow.  */
14668       if (val < 0)
14669         {
14670           switch (address_mode)
14671             {
14672             case mode_64bit:
14673               strcpy (buf + j, "0x8000000000000000");
14674               break;
14675             case mode_32bit:
14676               strcpy (buf + j, "0x80000000");
14677               break;
14678             case mode_16bit:
14679               strcpy (buf + j, "0x8000");
14680               break;
14681             }
14682           return;
14683         }
14684     }
14685
14686   buf[j++] = '0';
14687   buf[j++] = 'x';
14688
14689   sprintf_vma (tmp, (bfd_vma) val);
14690   for (i = 0; tmp[i] == '0'; i++)
14691     continue;
14692   if (tmp[i] == '\0')
14693     i--;
14694   strcpy (buf + j, tmp + i);
14695 }
14696
14697 static void
14698 intel_operand_size (int bytemode, int sizeflag)
14699 {
14700   if (vex.evex
14701       && vex.b
14702       && (bytemode == x_mode
14703           || bytemode == evex_half_bcst_xmmq_mode))
14704     {
14705       if (vex.w)
14706         oappend ("QWORD PTR ");
14707       else
14708         oappend ("DWORD PTR ");
14709       return;
14710     }
14711   switch (bytemode)
14712     {
14713     case b_mode:
14714     case b_swap_mode:
14715     case dqb_mode:
14716     case db_mode:
14717       oappend ("BYTE PTR ");
14718       break;
14719     case w_mode:
14720     case dw_mode:
14721     case dqw_mode:
14722       oappend ("WORD PTR ");
14723       break;
14724     case indir_v_mode:
14725       if (address_mode == mode_64bit && isa64 == intel64)
14726         {
14727           oappend ("QWORD PTR ");
14728           break;
14729         }
14730       /* Fall through.  */
14731     case stack_v_mode:
14732       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14733         {
14734           oappend ("QWORD PTR ");
14735           break;
14736         }
14737       /* Fall through.  */
14738     case v_mode:
14739     case v_swap_mode:
14740     case dq_mode:
14741       USED_REX (REX_W);
14742       if (rex & REX_W)
14743         oappend ("QWORD PTR ");
14744       else
14745         {
14746           if ((sizeflag & DFLAG) || bytemode == dq_mode)
14747             oappend ("DWORD PTR ");
14748           else
14749             oappend ("WORD PTR ");
14750           used_prefixes |= (prefixes & PREFIX_DATA);
14751         }
14752       break;
14753     case z_mode:
14754       if ((rex & REX_W) || (sizeflag & DFLAG))
14755         *obufp++ = 'D';
14756       oappend ("WORD PTR ");
14757       if (!(rex & REX_W))
14758         used_prefixes |= (prefixes & PREFIX_DATA);
14759       break;
14760     case a_mode:
14761       if (sizeflag & DFLAG)
14762         oappend ("QWORD PTR ");
14763       else
14764         oappend ("DWORD PTR ");
14765       used_prefixes |= (prefixes & PREFIX_DATA);
14766       break;
14767     case d_mode:
14768     case d_scalar_mode:
14769     case d_scalar_swap_mode:
14770     case d_swap_mode:
14771     case dqd_mode:
14772       oappend ("DWORD PTR ");
14773       break;
14774     case q_mode:
14775     case q_scalar_mode:
14776     case q_scalar_swap_mode:
14777     case q_swap_mode:
14778       oappend ("QWORD PTR ");
14779       break;
14780     case m_mode:
14781       if (address_mode == mode_64bit)
14782         oappend ("QWORD PTR ");
14783       else
14784         oappend ("DWORD PTR ");
14785       break;
14786     case f_mode:
14787       if (sizeflag & DFLAG)
14788         oappend ("FWORD PTR ");
14789       else
14790         oappend ("DWORD PTR ");
14791       used_prefixes |= (prefixes & PREFIX_DATA);
14792       break;
14793     case t_mode:
14794       oappend ("TBYTE PTR ");
14795       break;
14796     case x_mode:
14797     case x_swap_mode:
14798     case evex_x_gscat_mode:
14799     case evex_x_nobcst_mode:
14800     case b_scalar_mode:
14801     case w_scalar_mode:
14802       if (need_vex)
14803         {
14804           switch (vex.length)
14805             {
14806             case 128:
14807               oappend ("XMMWORD PTR ");
14808               break;
14809             case 256:
14810               oappend ("YMMWORD PTR ");
14811               break;
14812             case 512:
14813               oappend ("ZMMWORD PTR ");
14814               break;
14815             default:
14816               abort ();
14817             }
14818         }
14819       else
14820         oappend ("XMMWORD PTR ");
14821       break;
14822     case xmm_mode:
14823       oappend ("XMMWORD PTR ");
14824       break;
14825     case ymm_mode:
14826       oappend ("YMMWORD PTR ");
14827       break;
14828     case xmmq_mode:
14829     case evex_half_bcst_xmmq_mode:
14830       if (!need_vex)
14831         abort ();
14832
14833       switch (vex.length)
14834         {
14835         case 128:
14836           oappend ("QWORD PTR ");
14837           break;
14838         case 256:
14839           oappend ("XMMWORD PTR ");
14840           break;
14841         case 512:
14842           oappend ("YMMWORD PTR ");
14843           break;
14844         default:
14845           abort ();
14846         }
14847       break;
14848     case xmm_mb_mode:
14849       if (!need_vex)
14850         abort ();
14851
14852       switch (vex.length)
14853         {
14854         case 128:
14855         case 256:
14856         case 512:
14857           oappend ("BYTE PTR ");
14858           break;
14859         default:
14860           abort ();
14861         }
14862       break;
14863     case xmm_mw_mode:
14864       if (!need_vex)
14865         abort ();
14866
14867       switch (vex.length)
14868         {
14869         case 128:
14870         case 256:
14871         case 512:
14872           oappend ("WORD PTR ");
14873           break;
14874         default:
14875           abort ();
14876         }
14877       break;
14878     case xmm_md_mode:
14879       if (!need_vex)
14880         abort ();
14881
14882       switch (vex.length)
14883         {
14884         case 128:
14885         case 256:
14886         case 512:
14887           oappend ("DWORD PTR ");
14888           break;
14889         default:
14890           abort ();
14891         }
14892       break;
14893     case xmm_mq_mode:
14894       if (!need_vex)
14895         abort ();
14896
14897       switch (vex.length)
14898         {
14899         case 128:
14900         case 256:
14901         case 512:
14902           oappend ("QWORD PTR ");
14903           break;
14904         default:
14905           abort ();
14906         }
14907       break;
14908     case xmmdw_mode:
14909       if (!need_vex)
14910         abort ();
14911
14912       switch (vex.length)
14913         {
14914         case 128:
14915           oappend ("WORD PTR ");
14916           break;
14917         case 256:
14918           oappend ("DWORD PTR ");
14919           break;
14920         case 512:
14921           oappend ("QWORD PTR ");
14922           break;
14923         default:
14924           abort ();
14925         }
14926       break;
14927     case xmmqd_mode:
14928       if (!need_vex)
14929         abort ();
14930
14931       switch (vex.length)
14932         {
14933         case 128:
14934           oappend ("DWORD PTR ");
14935           break;
14936         case 256:
14937           oappend ("QWORD PTR ");
14938           break;
14939         case 512:
14940           oappend ("XMMWORD PTR ");
14941           break;
14942         default:
14943           abort ();
14944         }
14945       break;
14946     case ymmq_mode:
14947       if (!need_vex)
14948         abort ();
14949
14950       switch (vex.length)
14951         {
14952         case 128:
14953           oappend ("QWORD PTR ");
14954           break;
14955         case 256:
14956           oappend ("YMMWORD PTR ");
14957           break;
14958         case 512:
14959           oappend ("ZMMWORD PTR ");
14960           break;
14961         default:
14962           abort ();
14963         }
14964       break;
14965     case ymmxmm_mode:
14966       if (!need_vex)
14967         abort ();
14968
14969       switch (vex.length)
14970         {
14971         case 128:
14972         case 256:
14973           oappend ("XMMWORD PTR ");
14974           break;
14975         default:
14976           abort ();
14977         }
14978       break;
14979     case o_mode:
14980       oappend ("OWORD PTR ");
14981       break;
14982     case xmm_mdq_mode:
14983     case vex_w_dq_mode:
14984     case vex_scalar_w_dq_mode:
14985       if (!need_vex)
14986         abort ();
14987
14988       if (vex.w)
14989         oappend ("QWORD PTR ");
14990       else
14991         oappend ("DWORD PTR ");
14992       break;
14993     case vex_vsib_d_w_dq_mode:
14994     case vex_vsib_q_w_dq_mode:
14995       if (!need_vex)
14996         abort ();
14997
14998       if (!vex.evex)
14999         {
15000           if (vex.w)
15001             oappend ("QWORD PTR ");
15002           else
15003             oappend ("DWORD PTR ");
15004         }
15005       else
15006         {
15007           switch (vex.length)
15008             {
15009             case 128:
15010               oappend ("XMMWORD PTR ");
15011               break;
15012             case 256:
15013               oappend ("YMMWORD PTR ");
15014               break;
15015             case 512:
15016               oappend ("ZMMWORD PTR ");
15017               break;
15018             default:
15019               abort ();
15020             }
15021         }
15022       break;
15023     case vex_vsib_q_w_d_mode:
15024     case vex_vsib_d_w_d_mode:
15025       if (!need_vex || !vex.evex)
15026         abort ();
15027
15028       switch (vex.length)
15029         {
15030         case 128:
15031           oappend ("QWORD PTR ");
15032           break;
15033         case 256:
15034           oappend ("XMMWORD PTR ");
15035           break;
15036         case 512:
15037           oappend ("YMMWORD PTR ");
15038           break;
15039         default:
15040           abort ();
15041         }
15042
15043       break;
15044     case mask_bd_mode:
15045       if (!need_vex || vex.length != 128)
15046         abort ();
15047       if (vex.w)
15048         oappend ("DWORD PTR ");
15049       else
15050         oappend ("BYTE PTR ");
15051       break;
15052     case mask_mode:
15053       if (!need_vex)
15054         abort ();
15055       if (vex.w)
15056         oappend ("QWORD PTR ");
15057       else
15058         oappend ("WORD PTR ");
15059       break;
15060     case v_bnd_mode:
15061     default:
15062       break;
15063     }
15064 }
15065
15066 static void
15067 OP_E_register (int bytemode, int sizeflag)
15068 {
15069   int reg = modrm.rm;
15070   const char **names;
15071
15072   USED_REX (REX_B);
15073   if ((rex & REX_B))
15074     reg += 8;
15075
15076   if ((sizeflag & SUFFIX_ALWAYS)
15077       && (bytemode == b_swap_mode
15078           || bytemode == bnd_swap_mode
15079           || bytemode == v_swap_mode))
15080     swap_operand ();
15081
15082   switch (bytemode)
15083     {
15084     case b_mode:
15085     case b_swap_mode:
15086       USED_REX (0);
15087       if (rex)
15088         names = names8rex;
15089       else
15090         names = names8;
15091       break;
15092     case w_mode:
15093       names = names16;
15094       break;
15095     case d_mode:
15096     case dw_mode:
15097     case db_mode:
15098       names = names32;
15099       break;
15100     case q_mode:
15101       names = names64;
15102       break;
15103     case m_mode:
15104     case v_bnd_mode:
15105       names = address_mode == mode_64bit ? names64 : names32;
15106       break;
15107     case bnd_mode:
15108     case bnd_swap_mode:
15109       if (reg > 0x3)
15110         {
15111           oappend ("(bad)");
15112           return;
15113         }
15114       names = names_bnd;
15115       break;
15116     case indir_v_mode:
15117       if (address_mode == mode_64bit && isa64 == intel64)
15118         {
15119           names = names64;
15120           break;
15121         }
15122       /* Fall through.  */
15123     case stack_v_mode:
15124       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
15125         {
15126           names = names64;
15127           break;
15128         }
15129       bytemode = v_mode;
15130       /* Fall through.  */
15131     case v_mode:
15132     case v_swap_mode:
15133     case dq_mode:
15134     case dqb_mode:
15135     case dqd_mode:
15136     case dqw_mode:
15137       USED_REX (REX_W);
15138       if (rex & REX_W)
15139         names = names64;
15140       else
15141         {
15142           if ((sizeflag & DFLAG)
15143               || (bytemode != v_mode
15144                   && bytemode != v_swap_mode))
15145             names = names32;
15146           else
15147             names = names16;
15148           used_prefixes |= (prefixes & PREFIX_DATA);
15149         }
15150       break;
15151     case va_mode:
15152       names = (address_mode == mode_64bit
15153                ? names64 : names32);
15154       if (!(prefixes & PREFIX_ADDR))
15155         names = (address_mode == mode_16bit
15156                      ? names16 : names);
15157       else
15158         {
15159           /* Remove "addr16/addr32".  */
15160           all_prefixes[last_addr_prefix] = 0;
15161           names = (address_mode != mode_32bit
15162                        ? names32 : names16);
15163           used_prefixes |= PREFIX_ADDR;
15164         }
15165       break;
15166     case mask_bd_mode:
15167     case mask_mode:
15168       if (reg > 0x7)
15169         {
15170           oappend ("(bad)");
15171           return;
15172         }
15173       names = names_mask;
15174       break;
15175     case 0:
15176       return;
15177     default:
15178       oappend (INTERNAL_DISASSEMBLER_ERROR);
15179       return;
15180     }
15181   oappend (names[reg]);
15182 }
15183
15184 static void
15185 OP_E_memory (int bytemode, int sizeflag)
15186 {
15187   bfd_vma disp = 0;
15188   int add = (rex & REX_B) ? 8 : 0;
15189   int riprel = 0;
15190   int shift;
15191
15192   if (vex.evex)
15193     {
15194       /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0.  */
15195       if (vex.b
15196           && bytemode != x_mode
15197           && bytemode != xmmq_mode
15198           && bytemode != evex_half_bcst_xmmq_mode)
15199         {
15200           BadOp ();
15201           return;
15202         }
15203       switch (bytemode)
15204         {
15205         case dqw_mode:
15206         case dw_mode:
15207           shift = 1;
15208           break;
15209         case dqb_mode:
15210         case db_mode:
15211           shift = 0;
15212           break;
15213         case vex_vsib_d_w_dq_mode:
15214         case vex_vsib_d_w_d_mode:
15215         case vex_vsib_q_w_dq_mode:
15216         case vex_vsib_q_w_d_mode:
15217         case evex_x_gscat_mode:
15218         case xmm_mdq_mode:
15219           shift = vex.w ? 3 : 2;
15220           break;
15221         case x_mode:
15222         case evex_half_bcst_xmmq_mode:
15223         case xmmq_mode:
15224           if (vex.b)
15225             {
15226               shift = vex.w ? 3 : 2;
15227               break;
15228             }
15229           /* Fall through.  */
15230         case xmmqd_mode:
15231         case xmmdw_mode:
15232         case ymmq_mode:
15233         case evex_x_nobcst_mode:
15234         case x_swap_mode:
15235           switch (vex.length)
15236             {
15237             case 128:
15238               shift = 4;
15239               break;
15240             case 256:
15241               shift = 5;
15242               break;
15243             case 512:
15244               shift = 6;
15245               break;
15246             default:
15247               abort ();
15248             }
15249           break;
15250         case ymm_mode:
15251           shift = 5;
15252           break;
15253         case xmm_mode:
15254           shift = 4;
15255           break;
15256         case xmm_mq_mode:
15257         case q_mode:
15258         case q_scalar_mode:
15259         case q_swap_mode:
15260         case q_scalar_swap_mode:
15261           shift = 3;
15262           break;
15263         case dqd_mode:
15264         case xmm_md_mode:
15265         case d_mode:
15266         case d_scalar_mode:
15267         case d_swap_mode:
15268         case d_scalar_swap_mode:
15269           shift = 2;
15270           break;
15271     case w_scalar_mode:
15272         case xmm_mw_mode:
15273           shift = 1;
15274           break;
15275     case b_scalar_mode:
15276         case xmm_mb_mode:
15277           shift = 0;
15278           break;
15279         default:
15280           abort ();
15281         }
15282       /* Make necessary corrections to shift for modes that need it.
15283          For these modes we currently have shift 4, 5 or 6 depending on
15284          vex.length (it corresponds to xmmword, ymmword or zmmword
15285          operand).  We might want to make it 3, 4 or 5 (e.g. for
15286          xmmq_mode).  In case of broadcast enabled the corrections
15287          aren't needed, as element size is always 32 or 64 bits.  */
15288       if (!vex.b
15289           && (bytemode == xmmq_mode
15290               || bytemode == evex_half_bcst_xmmq_mode))
15291         shift -= 1;
15292       else if (bytemode == xmmqd_mode)
15293         shift -= 2;
15294       else if (bytemode == xmmdw_mode)
15295         shift -= 3;
15296       else if (bytemode == ymmq_mode && vex.length == 128)
15297         shift -= 1;
15298     }
15299   else
15300     shift = 0;
15301
15302   USED_REX (REX_B);
15303   if (intel_syntax)
15304     intel_operand_size (bytemode, sizeflag);
15305   append_seg ();
15306
15307   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
15308     {
15309       /* 32/64 bit address mode */
15310       int havedisp;
15311       int havesib;
15312       int havebase;
15313       int haveindex;
15314       int needindex;
15315       int base, rbase;
15316       int vindex = 0;
15317       int scale = 0;
15318       int addr32flag = !((sizeflag & AFLAG)
15319                          || bytemode == v_bnd_mode
15320                          || bytemode == bnd_mode
15321                          || bytemode == bnd_swap_mode);
15322       const char **indexes64 = names64;
15323       const char **indexes32 = names32;
15324
15325       havesib = 0;
15326       havebase = 1;
15327       haveindex = 0;
15328       base = modrm.rm;
15329
15330       if (base == 4)
15331         {
15332           havesib = 1;
15333           vindex = sib.index;
15334           USED_REX (REX_X);
15335           if (rex & REX_X)
15336             vindex += 8;
15337           switch (bytemode)
15338             {
15339             case vex_vsib_d_w_dq_mode:
15340             case vex_vsib_d_w_d_mode:
15341             case vex_vsib_q_w_dq_mode:
15342             case vex_vsib_q_w_d_mode:
15343               if (!need_vex)
15344                 abort ();
15345               if (vex.evex)
15346                 {
15347                   if (!vex.v)
15348                     vindex += 16;
15349                 }
15350
15351               haveindex = 1;
15352               switch (vex.length)
15353                 {
15354                 case 128:
15355                   indexes64 = indexes32 = names_xmm;
15356                   break;
15357                 case 256:
15358                   if (!vex.w
15359                       || bytemode == vex_vsib_q_w_dq_mode
15360                       || bytemode == vex_vsib_q_w_d_mode)
15361                     indexes64 = indexes32 = names_ymm;
15362                   else
15363                     indexes64 = indexes32 = names_xmm;
15364                   break;
15365                 case 512:
15366                   if (!vex.w
15367                       || bytemode == vex_vsib_q_w_dq_mode
15368                       || bytemode == vex_vsib_q_w_d_mode)
15369                     indexes64 = indexes32 = names_zmm;
15370                   else
15371                     indexes64 = indexes32 = names_ymm;
15372                   break;
15373                 default:
15374                   abort ();
15375                 }
15376               break;
15377             default:
15378               haveindex = vindex != 4;
15379               break;
15380             }
15381           scale = sib.scale;
15382           base = sib.base;
15383           codep++;
15384         }
15385       rbase = base + add;
15386
15387       switch (modrm.mod)
15388         {
15389         case 0:
15390           if (base == 5)
15391             {
15392               havebase = 0;
15393               if (address_mode == mode_64bit && !havesib)
15394                 riprel = 1;
15395               disp = get32s ();
15396             }
15397           break;
15398         case 1:
15399           FETCH_DATA (the_info, codep + 1);
15400           disp = *codep++;
15401           if ((disp & 0x80) != 0)
15402             disp -= 0x100;
15403           if (vex.evex && shift > 0)
15404             disp <<= shift;
15405           break;
15406         case 2:
15407           disp = get32s ();
15408           break;
15409         }
15410
15411       /* In 32bit mode, we need index register to tell [offset] from
15412          [eiz*1 + offset].  */
15413       needindex = (havesib
15414                    && !havebase
15415                    && !haveindex
15416                    && address_mode == mode_32bit);
15417       havedisp = (havebase
15418                   || needindex
15419                   || (havesib && (haveindex || scale != 0)));
15420
15421       if (!intel_syntax)
15422         if (modrm.mod != 0 || base == 5)
15423           {
15424             if (havedisp || riprel)
15425               print_displacement (scratchbuf, disp);
15426             else
15427               print_operand_value (scratchbuf, 1, disp);
15428             oappend (scratchbuf);
15429             if (riprel)
15430               {
15431                 set_op (disp, 1);
15432                 oappend (!addr32flag ? "(%rip)" : "(%eip)");
15433               }
15434           }
15435
15436       if ((havebase || haveindex || riprel)
15437           && (bytemode != v_bnd_mode)
15438           && (bytemode != bnd_mode)
15439           && (bytemode != bnd_swap_mode))
15440         used_prefixes |= PREFIX_ADDR;
15441
15442       if (havedisp || (intel_syntax && riprel))
15443         {
15444           *obufp++ = open_char;
15445           if (intel_syntax && riprel)
15446             {
15447               set_op (disp, 1);
15448               oappend (!addr32flag ? "rip" : "eip");
15449             }
15450           *obufp = '\0';
15451           if (havebase)
15452             oappend (address_mode == mode_64bit && !addr32flag
15453                      ? names64[rbase] : names32[rbase]);
15454           if (havesib)
15455             {
15456               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
15457                  print index to tell base + index from base.  */
15458               if (scale != 0
15459                   || needindex
15460                   || haveindex
15461                   || (havebase && base != ESP_REG_NUM))
15462                 {
15463                   if (!intel_syntax || havebase)
15464                     {
15465                       *obufp++ = separator_char;
15466                       *obufp = '\0';
15467                     }
15468                   if (haveindex)
15469                     oappend (address_mode == mode_64bit && !addr32flag
15470                              ? indexes64[vindex] : indexes32[vindex]);
15471                   else
15472                     oappend (address_mode == mode_64bit && !addr32flag
15473                              ? index64 : index32);
15474
15475                   *obufp++ = scale_char;
15476                   *obufp = '\0';
15477                   sprintf (scratchbuf, "%d", 1 << scale);
15478                   oappend (scratchbuf);
15479                 }
15480             }
15481           if (intel_syntax
15482               && (disp || modrm.mod != 0 || base == 5))
15483             {
15484               if (!havedisp || (bfd_signed_vma) disp >= 0)
15485                 {
15486                   *obufp++ = '+';
15487                   *obufp = '\0';
15488                 }
15489               else if (modrm.mod != 1 && disp != -disp)
15490                 {
15491                   *obufp++ = '-';
15492                   *obufp = '\0';
15493                   disp = - (bfd_signed_vma) disp;
15494                 }
15495
15496               if (havedisp)
15497                 print_displacement (scratchbuf, disp);
15498               else
15499                 print_operand_value (scratchbuf, 1, disp);
15500               oappend (scratchbuf);
15501             }
15502
15503           *obufp++ = close_char;
15504           *obufp = '\0';
15505         }
15506       else if (intel_syntax)
15507         {
15508           if (modrm.mod != 0 || base == 5)
15509             {
15510               if (!active_seg_prefix)
15511                 {
15512                   oappend (names_seg[ds_reg - es_reg]);
15513                   oappend (":");
15514                 }
15515               print_operand_value (scratchbuf, 1, disp);
15516               oappend (scratchbuf);
15517             }
15518         }
15519     }
15520   else
15521     {
15522       /* 16 bit address mode */
15523       used_prefixes |= prefixes & PREFIX_ADDR;
15524       switch (modrm.mod)
15525         {
15526         case 0:
15527           if (modrm.rm == 6)
15528             {
15529               disp = get16 ();
15530               if ((disp & 0x8000) != 0)
15531                 disp -= 0x10000;
15532             }
15533           break;
15534         case 1:
15535           FETCH_DATA (the_info, codep + 1);
15536           disp = *codep++;
15537           if ((disp & 0x80) != 0)
15538             disp -= 0x100;
15539           if (vex.evex && shift > 0)
15540             disp <<= shift;
15541           break;
15542         case 2:
15543           disp = get16 ();
15544           if ((disp & 0x8000) != 0)
15545             disp -= 0x10000;
15546           break;
15547         }
15548
15549       if (!intel_syntax)
15550         if (modrm.mod != 0 || modrm.rm == 6)
15551           {
15552             print_displacement (scratchbuf, disp);
15553             oappend (scratchbuf);
15554           }
15555
15556       if (modrm.mod != 0 || modrm.rm != 6)
15557         {
15558           *obufp++ = open_char;
15559           *obufp = '\0';
15560           oappend (index16[modrm.rm]);
15561           if (intel_syntax
15562               && (disp || modrm.mod != 0 || modrm.rm == 6))
15563             {
15564               if ((bfd_signed_vma) disp >= 0)
15565                 {
15566                   *obufp++ = '+';
15567                   *obufp = '\0';
15568                 }
15569               else if (modrm.mod != 1)
15570                 {
15571                   *obufp++ = '-';
15572                   *obufp = '\0';
15573                   disp = - (bfd_signed_vma) disp;
15574                 }
15575
15576               print_displacement (scratchbuf, disp);
15577               oappend (scratchbuf);
15578             }
15579
15580           *obufp++ = close_char;
15581           *obufp = '\0';
15582         }
15583       else if (intel_syntax)
15584         {
15585           if (!active_seg_prefix)
15586             {
15587               oappend (names_seg[ds_reg - es_reg]);
15588               oappend (":");
15589             }
15590           print_operand_value (scratchbuf, 1, disp & 0xffff);
15591           oappend (scratchbuf);
15592         }
15593     }
15594   if (vex.evex && vex.b
15595       && (bytemode == x_mode
15596           || bytemode == xmmq_mode
15597           || bytemode == evex_half_bcst_xmmq_mode))
15598     {
15599       if (vex.w
15600           || bytemode == xmmq_mode
15601           || bytemode == evex_half_bcst_xmmq_mode)
15602         {
15603           switch (vex.length)
15604             {
15605             case 128:
15606               oappend ("{1to2}");
15607               break;
15608             case 256:
15609               oappend ("{1to4}");
15610               break;
15611             case 512:
15612               oappend ("{1to8}");
15613               break;
15614             default:
15615               abort ();
15616             }
15617         }
15618       else
15619         {
15620           switch (vex.length)
15621             {
15622             case 128:
15623               oappend ("{1to4}");
15624               break;
15625             case 256:
15626               oappend ("{1to8}");
15627               break;
15628             case 512:
15629               oappend ("{1to16}");
15630               break;
15631             default:
15632               abort ();
15633             }
15634         }
15635     }
15636 }
15637
15638 static void
15639 OP_E (int bytemode, int sizeflag)
15640 {
15641   /* Skip mod/rm byte.  */
15642   MODRM_CHECK;
15643   codep++;
15644
15645   if (modrm.mod == 3)
15646     OP_E_register (bytemode, sizeflag);
15647   else
15648     OP_E_memory (bytemode, sizeflag);
15649 }
15650
15651 static void
15652 OP_G (int bytemode, int sizeflag)
15653 {
15654   int add = 0;
15655   USED_REX (REX_R);
15656   if (rex & REX_R)
15657     add += 8;
15658   switch (bytemode)
15659     {
15660     case b_mode:
15661       USED_REX (0);
15662       if (rex)
15663         oappend (names8rex[modrm.reg + add]);
15664       else
15665         oappend (names8[modrm.reg + add]);
15666       break;
15667     case w_mode:
15668       oappend (names16[modrm.reg + add]);
15669       break;
15670     case d_mode:
15671     case db_mode:
15672     case dw_mode:
15673       oappend (names32[modrm.reg + add]);
15674       break;
15675     case q_mode:
15676       oappend (names64[modrm.reg + add]);
15677       break;
15678     case bnd_mode:
15679       if (modrm.reg > 0x3)
15680         {
15681           oappend ("(bad)");
15682           return;
15683         }
15684       oappend (names_bnd[modrm.reg]);
15685       break;
15686     case v_mode:
15687     case dq_mode:
15688     case dqb_mode:
15689     case dqd_mode:
15690     case dqw_mode:
15691       USED_REX (REX_W);
15692       if (rex & REX_W)
15693         oappend (names64[modrm.reg + add]);
15694       else
15695         {
15696           if ((sizeflag & DFLAG) || bytemode != v_mode)
15697             oappend (names32[modrm.reg + add]);
15698           else
15699             oappend (names16[modrm.reg + add]);
15700           used_prefixes |= (prefixes & PREFIX_DATA);
15701         }
15702       break;
15703     case m_mode:
15704       if (address_mode == mode_64bit)
15705         oappend (names64[modrm.reg + add]);
15706       else
15707         oappend (names32[modrm.reg + add]);
15708       break;
15709     case mask_bd_mode:
15710     case mask_mode:
15711       if ((modrm.reg + add) > 0x7)
15712         {
15713           oappend ("(bad)");
15714           return;
15715         }
15716       oappend (names_mask[modrm.reg + add]);
15717       break;
15718     default:
15719       oappend (INTERNAL_DISASSEMBLER_ERROR);
15720       break;
15721     }
15722 }
15723
15724 static bfd_vma
15725 get64 (void)
15726 {
15727   bfd_vma x;
15728 #ifdef BFD64
15729   unsigned int a;
15730   unsigned int b;
15731
15732   FETCH_DATA (the_info, codep + 8);
15733   a = *codep++ & 0xff;
15734   a |= (*codep++ & 0xff) << 8;
15735   a |= (*codep++ & 0xff) << 16;
15736   a |= (*codep++ & 0xffu) << 24;
15737   b = *codep++ & 0xff;
15738   b |= (*codep++ & 0xff) << 8;
15739   b |= (*codep++ & 0xff) << 16;
15740   b |= (*codep++ & 0xffu) << 24;
15741   x = a + ((bfd_vma) b << 32);
15742 #else
15743   abort ();
15744   x = 0;
15745 #endif
15746   return x;
15747 }
15748
15749 static bfd_signed_vma
15750 get32 (void)
15751 {
15752   bfd_signed_vma x = 0;
15753
15754   FETCH_DATA (the_info, codep + 4);
15755   x = *codep++ & (bfd_signed_vma) 0xff;
15756   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15757   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15758   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15759   return x;
15760 }
15761
15762 static bfd_signed_vma
15763 get32s (void)
15764 {
15765   bfd_signed_vma x = 0;
15766
15767   FETCH_DATA (the_info, codep + 4);
15768   x = *codep++ & (bfd_signed_vma) 0xff;
15769   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15770   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15771   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15772
15773   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
15774
15775   return x;
15776 }
15777
15778 static int
15779 get16 (void)
15780 {
15781   int x = 0;
15782
15783   FETCH_DATA (the_info, codep + 2);
15784   x = *codep++ & 0xff;
15785   x |= (*codep++ & 0xff) << 8;
15786   return x;
15787 }
15788
15789 static void
15790 set_op (bfd_vma op, int riprel)
15791 {
15792   op_index[op_ad] = op_ad;
15793   if (address_mode == mode_64bit)
15794     {
15795       op_address[op_ad] = op;
15796       op_riprel[op_ad] = riprel;
15797     }
15798   else
15799     {
15800       /* Mask to get a 32-bit address.  */
15801       op_address[op_ad] = op & 0xffffffff;
15802       op_riprel[op_ad] = riprel & 0xffffffff;
15803     }
15804 }
15805
15806 static void
15807 OP_REG (int code, int sizeflag)
15808 {
15809   const char *s;
15810   int add;
15811
15812   switch (code)
15813     {
15814     case es_reg: case ss_reg: case cs_reg:
15815     case ds_reg: case fs_reg: case gs_reg:
15816       oappend (names_seg[code - es_reg]);
15817       return;
15818     }
15819
15820   USED_REX (REX_B);
15821   if (rex & REX_B)
15822     add = 8;
15823   else
15824     add = 0;
15825
15826   switch (code)
15827     {
15828     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15829     case sp_reg: case bp_reg: case si_reg: case di_reg:
15830       s = names16[code - ax_reg + add];
15831       break;
15832     case al_reg: case ah_reg: case cl_reg: case ch_reg:
15833     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15834       USED_REX (0);
15835       if (rex)
15836         s = names8rex[code - al_reg + add];
15837       else
15838         s = names8[code - al_reg];
15839       break;
15840     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
15841     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
15842       if (address_mode == mode_64bit
15843           && ((sizeflag & DFLAG) || (rex & REX_W)))
15844         {
15845           s = names64[code - rAX_reg + add];
15846           break;
15847         }
15848       code += eAX_reg - rAX_reg;
15849       /* Fall through.  */
15850     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15851     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15852       USED_REX (REX_W);
15853       if (rex & REX_W)
15854         s = names64[code - eAX_reg + add];
15855       else
15856         {
15857           if (sizeflag & DFLAG)
15858             s = names32[code - eAX_reg + add];
15859           else
15860             s = names16[code - eAX_reg + add];
15861           used_prefixes |= (prefixes & PREFIX_DATA);
15862         }
15863       break;
15864     default:
15865       s = INTERNAL_DISASSEMBLER_ERROR;
15866       break;
15867     }
15868   oappend (s);
15869 }
15870
15871 static void
15872 OP_IMREG (int code, int sizeflag)
15873 {
15874   const char *s;
15875
15876   switch (code)
15877     {
15878     case indir_dx_reg:
15879       if (intel_syntax)
15880         s = "dx";
15881       else
15882         s = "(%dx)";
15883       break;
15884     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15885     case sp_reg: case bp_reg: case si_reg: case di_reg:
15886       s = names16[code - ax_reg];
15887       break;
15888     case es_reg: case ss_reg: case cs_reg:
15889     case ds_reg: case fs_reg: case gs_reg:
15890       s = names_seg[code - es_reg];
15891       break;
15892     case al_reg: case ah_reg: case cl_reg: case ch_reg:
15893     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15894       USED_REX (0);
15895       if (rex)
15896         s = names8rex[code - al_reg];
15897       else
15898         s = names8[code - al_reg];
15899       break;
15900     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15901     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15902       USED_REX (REX_W);
15903       if (rex & REX_W)
15904         s = names64[code - eAX_reg];
15905       else
15906         {
15907           if (sizeflag & DFLAG)
15908             s = names32[code - eAX_reg];
15909           else
15910             s = names16[code - eAX_reg];
15911           used_prefixes |= (prefixes & PREFIX_DATA);
15912         }
15913       break;
15914     case z_mode_ax_reg:
15915       if ((rex & REX_W) || (sizeflag & DFLAG))
15916         s = *names32;
15917       else
15918         s = *names16;
15919       if (!(rex & REX_W))
15920         used_prefixes |= (prefixes & PREFIX_DATA);
15921       break;
15922     default:
15923       s = INTERNAL_DISASSEMBLER_ERROR;
15924       break;
15925     }
15926   oappend (s);
15927 }
15928
15929 static void
15930 OP_I (int bytemode, int sizeflag)
15931 {
15932   bfd_signed_vma op;
15933   bfd_signed_vma mask = -1;
15934
15935   switch (bytemode)
15936     {
15937     case b_mode:
15938       FETCH_DATA (the_info, codep + 1);
15939       op = *codep++;
15940       mask = 0xff;
15941       break;
15942     case q_mode:
15943       if (address_mode == mode_64bit)
15944         {
15945           op = get32s ();
15946           break;
15947         }
15948       /* Fall through.  */
15949     case v_mode:
15950       USED_REX (REX_W);
15951       if (rex & REX_W)
15952         op = get32s ();
15953       else
15954         {
15955           if (sizeflag & DFLAG)
15956             {
15957               op = get32 ();
15958               mask = 0xffffffff;
15959             }
15960           else
15961             {
15962               op = get16 ();
15963               mask = 0xfffff;
15964             }
15965           used_prefixes |= (prefixes & PREFIX_DATA);
15966         }
15967       break;
15968     case w_mode:
15969       mask = 0xfffff;
15970       op = get16 ();
15971       break;
15972     case const_1_mode:
15973       if (intel_syntax)
15974         oappend ("1");
15975       return;
15976     default:
15977       oappend (INTERNAL_DISASSEMBLER_ERROR);
15978       return;
15979     }
15980
15981   op &= mask;
15982   scratchbuf[0] = '$';
15983   print_operand_value (scratchbuf + 1, 1, op);
15984   oappend_maybe_intel (scratchbuf);
15985   scratchbuf[0] = '\0';
15986 }
15987
15988 static void
15989 OP_I64 (int bytemode, int sizeflag)
15990 {
15991   bfd_signed_vma op;
15992   bfd_signed_vma mask = -1;
15993
15994   if (address_mode != mode_64bit)
15995     {
15996       OP_I (bytemode, sizeflag);
15997       return;
15998     }
15999
16000   switch (bytemode)
16001     {
16002     case b_mode:
16003       FETCH_DATA (the_info, codep + 1);
16004       op = *codep++;
16005       mask = 0xff;
16006       break;
16007     case v_mode:
16008       USED_REX (REX_W);
16009       if (rex & REX_W)
16010         op = get64 ();
16011       else
16012         {
16013           if (sizeflag & DFLAG)
16014             {
16015               op = get32 ();
16016               mask = 0xffffffff;
16017             }
16018           else
16019             {
16020               op = get16 ();
16021               mask = 0xfffff;
16022             }
16023           used_prefixes |= (prefixes & PREFIX_DATA);
16024         }
16025       break;
16026     case w_mode:
16027       mask = 0xfffff;
16028       op = get16 ();
16029       break;
16030     default:
16031       oappend (INTERNAL_DISASSEMBLER_ERROR);
16032       return;
16033     }
16034
16035   op &= mask;
16036   scratchbuf[0] = '$';
16037   print_operand_value (scratchbuf + 1, 1, op);
16038   oappend_maybe_intel (scratchbuf);
16039   scratchbuf[0] = '\0';
16040 }
16041
16042 static void
16043 OP_sI (int bytemode, int sizeflag)
16044 {
16045   bfd_signed_vma op;
16046
16047   switch (bytemode)
16048     {
16049     case b_mode:
16050     case b_T_mode:
16051       FETCH_DATA (the_info, codep + 1);
16052       op = *codep++;
16053       if ((op & 0x80) != 0)
16054         op -= 0x100;
16055       if (bytemode == b_T_mode)
16056         {
16057           if (address_mode != mode_64bit
16058               || !((sizeflag & DFLAG) || (rex & REX_W)))
16059             {
16060               /* The operand-size prefix is overridden by a REX prefix.  */
16061               if ((sizeflag & DFLAG) || (rex & REX_W))
16062                 op &= 0xffffffff;
16063               else
16064                 op &= 0xffff;
16065           }
16066         }
16067       else
16068         {
16069           if (!(rex & REX_W))
16070             {
16071               if (sizeflag & DFLAG)
16072                 op &= 0xffffffff;
16073               else
16074                 op &= 0xffff;
16075             }
16076         }
16077       break;
16078     case v_mode:
16079       /* The operand-size prefix is overridden by a REX prefix.  */
16080       if ((sizeflag & DFLAG) || (rex & REX_W))
16081         op = get32s ();
16082       else
16083         op = get16 ();
16084       break;
16085     default:
16086       oappend (INTERNAL_DISASSEMBLER_ERROR);
16087       return;
16088     }
16089
16090   scratchbuf[0] = '$';
16091   print_operand_value (scratchbuf + 1, 1, op);
16092   oappend_maybe_intel (scratchbuf);
16093 }
16094
16095 static void
16096 OP_J (int bytemode, int sizeflag)
16097 {
16098   bfd_vma disp;
16099   bfd_vma mask = -1;
16100   bfd_vma segment = 0;
16101
16102   switch (bytemode)
16103     {
16104     case b_mode:
16105       FETCH_DATA (the_info, codep + 1);
16106       disp = *codep++;
16107       if ((disp & 0x80) != 0)
16108         disp -= 0x100;
16109       break;
16110     case v_mode:
16111       if (isa64 == amd64)
16112         USED_REX (REX_W);
16113       if ((sizeflag & DFLAG)
16114           || (address_mode == mode_64bit
16115               && (isa64 != amd64 || (rex & REX_W))))
16116         disp = get32s ();
16117       else
16118         {
16119           disp = get16 ();
16120           if ((disp & 0x8000) != 0)
16121             disp -= 0x10000;
16122           /* In 16bit mode, address is wrapped around at 64k within
16123              the same segment.  Otherwise, a data16 prefix on a jump
16124              instruction means that the pc is masked to 16 bits after
16125              the displacement is added!  */
16126           mask = 0xffff;
16127           if ((prefixes & PREFIX_DATA) == 0)
16128             segment = ((start_pc + (codep - start_codep))
16129                        & ~((bfd_vma) 0xffff));
16130         }
16131       if (address_mode != mode_64bit
16132           || (isa64 == amd64 && !(rex & REX_W)))
16133         used_prefixes |= (prefixes & PREFIX_DATA);
16134       break;
16135     default:
16136       oappend (INTERNAL_DISASSEMBLER_ERROR);
16137       return;
16138     }
16139   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
16140   set_op (disp, 0);
16141   print_operand_value (scratchbuf, 1, disp);
16142   oappend (scratchbuf);
16143 }
16144
16145 static void
16146 OP_SEG (int bytemode, int sizeflag)
16147 {
16148   if (bytemode == w_mode)
16149     oappend (names_seg[modrm.reg]);
16150   else
16151     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
16152 }
16153
16154 static void
16155 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
16156 {
16157   int seg, offset;
16158
16159   if (sizeflag & DFLAG)
16160     {
16161       offset = get32 ();
16162       seg = get16 ();
16163     }
16164   else
16165     {
16166       offset = get16 ();
16167       seg = get16 ();
16168     }
16169   used_prefixes |= (prefixes & PREFIX_DATA);
16170   if (intel_syntax)
16171     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
16172   else
16173     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
16174   oappend (scratchbuf);
16175 }
16176
16177 static void
16178 OP_OFF (int bytemode, int sizeflag)
16179 {
16180   bfd_vma off;
16181
16182   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
16183     intel_operand_size (bytemode, sizeflag);
16184   append_seg ();
16185
16186   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
16187     off = get32 ();
16188   else
16189     off = get16 ();
16190
16191   if (intel_syntax)
16192     {
16193       if (!active_seg_prefix)
16194         {
16195           oappend (names_seg[ds_reg - es_reg]);
16196           oappend (":");
16197         }
16198     }
16199   print_operand_value (scratchbuf, 1, off);
16200   oappend (scratchbuf);
16201 }
16202
16203 static void
16204 OP_OFF64 (int bytemode, int sizeflag)
16205 {
16206   bfd_vma off;
16207
16208   if (address_mode != mode_64bit
16209       || (prefixes & PREFIX_ADDR))
16210     {
16211       OP_OFF (bytemode, sizeflag);
16212       return;
16213     }
16214
16215   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
16216     intel_operand_size (bytemode, sizeflag);
16217   append_seg ();
16218
16219   off = get64 ();
16220
16221   if (intel_syntax)
16222     {
16223       if (!active_seg_prefix)
16224         {
16225           oappend (names_seg[ds_reg - es_reg]);
16226           oappend (":");
16227         }
16228     }
16229   print_operand_value (scratchbuf, 1, off);
16230   oappend (scratchbuf);
16231 }
16232
16233 static void
16234 ptr_reg (int code, int sizeflag)
16235 {
16236   const char *s;
16237
16238   *obufp++ = open_char;
16239   used_prefixes |= (prefixes & PREFIX_ADDR);
16240   if (address_mode == mode_64bit)
16241     {
16242       if (!(sizeflag & AFLAG))
16243         s = names32[code - eAX_reg];
16244       else
16245         s = names64[code - eAX_reg];
16246     }
16247   else if (sizeflag & AFLAG)
16248     s = names32[code - eAX_reg];
16249   else
16250     s = names16[code - eAX_reg];
16251   oappend (s);
16252   *obufp++ = close_char;
16253   *obufp = 0;
16254 }
16255
16256 static void
16257 OP_ESreg (int code, int sizeflag)
16258 {
16259   if (intel_syntax)
16260     {
16261       switch (codep[-1])
16262         {
16263         case 0x6d:      /* insw/insl */
16264           intel_operand_size (z_mode, sizeflag);
16265           break;
16266         case 0xa5:      /* movsw/movsl/movsq */
16267         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
16268         case 0xab:      /* stosw/stosl */
16269         case 0xaf:      /* scasw/scasl */
16270           intel_operand_size (v_mode, sizeflag);
16271           break;
16272         default:
16273           intel_operand_size (b_mode, sizeflag);
16274         }
16275     }
16276   oappend_maybe_intel ("%es:");
16277   ptr_reg (code, sizeflag);
16278 }
16279
16280 static void
16281 OP_DSreg (int code, int sizeflag)
16282 {
16283   if (intel_syntax)
16284     {
16285       switch (codep[-1])
16286         {
16287         case 0x6f:      /* outsw/outsl */
16288           intel_operand_size (z_mode, sizeflag);
16289           break;
16290         case 0xa5:      /* movsw/movsl/movsq */
16291         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
16292         case 0xad:      /* lodsw/lodsl/lodsq */
16293           intel_operand_size (v_mode, sizeflag);
16294           break;
16295         default:
16296           intel_operand_size (b_mode, sizeflag);
16297         }
16298     }
16299   /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
16300      default segment register DS is printed.  */
16301   if (!active_seg_prefix)
16302     active_seg_prefix = PREFIX_DS;
16303   append_seg ();
16304   ptr_reg (code, sizeflag);
16305 }
16306
16307 static void
16308 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16309 {
16310   int add;
16311   if (rex & REX_R)
16312     {
16313       USED_REX (REX_R);
16314       add = 8;
16315     }
16316   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
16317     {
16318       all_prefixes[last_lock_prefix] = 0;
16319       used_prefixes |= PREFIX_LOCK;
16320       add = 8;
16321     }
16322   else
16323     add = 0;
16324   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
16325   oappend_maybe_intel (scratchbuf);
16326 }
16327
16328 static void
16329 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16330 {
16331   int add;
16332   USED_REX (REX_R);
16333   if (rex & REX_R)
16334     add = 8;
16335   else
16336     add = 0;
16337   if (intel_syntax)
16338     sprintf (scratchbuf, "db%d", modrm.reg + add);
16339   else
16340     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
16341   oappend (scratchbuf);
16342 }
16343
16344 static void
16345 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16346 {
16347   sprintf (scratchbuf, "%%tr%d", modrm.reg);
16348   oappend_maybe_intel (scratchbuf);
16349 }
16350
16351 static void
16352 OP_R (int bytemode, int sizeflag)
16353 {
16354   /* Skip mod/rm byte.  */
16355   MODRM_CHECK;
16356   codep++;
16357   OP_E_register (bytemode, sizeflag);
16358 }
16359
16360 static void
16361 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16362 {
16363   int reg = modrm.reg;
16364   const char **names;
16365
16366   used_prefixes |= (prefixes & PREFIX_DATA);
16367   if (prefixes & PREFIX_DATA)
16368     {
16369       names = names_xmm;
16370       USED_REX (REX_R);
16371       if (rex & REX_R)
16372         reg += 8;
16373     }
16374   else
16375     names = names_mm;
16376   oappend (names[reg]);
16377 }
16378
16379 static void
16380 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16381 {
16382   int reg = modrm.reg;
16383   const char **names;
16384
16385   USED_REX (REX_R);
16386   if (rex & REX_R)
16387     reg += 8;
16388   if (vex.evex)
16389     {
16390       if (!vex.r)
16391         reg += 16;
16392     }
16393
16394   if (need_vex
16395       && bytemode != xmm_mode
16396       && bytemode != xmmq_mode
16397       && bytemode != evex_half_bcst_xmmq_mode
16398       && bytemode != ymm_mode
16399       && bytemode != scalar_mode)
16400     {
16401       switch (vex.length)
16402         {
16403         case 128:
16404           names = names_xmm;
16405           break;
16406         case 256:
16407           if (vex.w
16408               || (bytemode != vex_vsib_q_w_dq_mode
16409                   && bytemode != vex_vsib_q_w_d_mode))
16410             names = names_ymm;
16411           else
16412             names = names_xmm;
16413           break;
16414         case 512:
16415           names = names_zmm;
16416           break;
16417         default:
16418           abort ();
16419         }
16420     }
16421   else if (bytemode == xmmq_mode
16422            || bytemode == evex_half_bcst_xmmq_mode)
16423     {
16424       switch (vex.length)
16425         {
16426         case 128:
16427         case 256:
16428           names = names_xmm;
16429           break;
16430         case 512:
16431           names = names_ymm;
16432           break;
16433         default:
16434           abort ();
16435         }
16436     }
16437   else if (bytemode == ymm_mode)
16438     names = names_ymm;
16439   else
16440     names = names_xmm;
16441   oappend (names[reg]);
16442 }
16443
16444 static void
16445 OP_EM (int bytemode, int sizeflag)
16446 {
16447   int reg;
16448   const char **names;
16449
16450   if (modrm.mod != 3)
16451     {
16452       if (intel_syntax
16453           && (bytemode == v_mode || bytemode == v_swap_mode))
16454         {
16455           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16456           used_prefixes |= (prefixes & PREFIX_DATA);
16457         }
16458       OP_E (bytemode, sizeflag);
16459       return;
16460     }
16461
16462   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
16463     swap_operand ();
16464
16465   /* Skip mod/rm byte.  */
16466   MODRM_CHECK;
16467   codep++;
16468   used_prefixes |= (prefixes & PREFIX_DATA);
16469   reg = modrm.rm;
16470   if (prefixes & PREFIX_DATA)
16471     {
16472       names = names_xmm;
16473       USED_REX (REX_B);
16474       if (rex & REX_B)
16475         reg += 8;
16476     }
16477   else
16478     names = names_mm;
16479   oappend (names[reg]);
16480 }
16481
16482 /* cvt* are the only instructions in sse2 which have
16483    both SSE and MMX operands and also have 0x66 prefix
16484    in their opcode. 0x66 was originally used to differentiate
16485    between SSE and MMX instruction(operands). So we have to handle the
16486    cvt* separately using OP_EMC and OP_MXC */
16487 static void
16488 OP_EMC (int bytemode, int sizeflag)
16489 {
16490   if (modrm.mod != 3)
16491     {
16492       if (intel_syntax && bytemode == v_mode)
16493         {
16494           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16495           used_prefixes |= (prefixes & PREFIX_DATA);
16496         }
16497       OP_E (bytemode, sizeflag);
16498       return;
16499     }
16500
16501   /* Skip mod/rm byte.  */
16502   MODRM_CHECK;
16503   codep++;
16504   used_prefixes |= (prefixes & PREFIX_DATA);
16505   oappend (names_mm[modrm.rm]);
16506 }
16507
16508 static void
16509 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16510 {
16511   used_prefixes |= (prefixes & PREFIX_DATA);
16512   oappend (names_mm[modrm.reg]);
16513 }
16514
16515 static void
16516 OP_EX (int bytemode, int sizeflag)
16517 {
16518   int reg;
16519   const char **names;
16520
16521   /* Skip mod/rm byte.  */
16522   MODRM_CHECK;
16523   codep++;
16524
16525   if (modrm.mod != 3)
16526     {
16527       OP_E_memory (bytemode, sizeflag);
16528       return;
16529     }
16530
16531   reg = modrm.rm;
16532   USED_REX (REX_B);
16533   if (rex & REX_B)
16534     reg += 8;
16535   if (vex.evex)
16536     {
16537       USED_REX (REX_X);
16538       if ((rex & REX_X))
16539         reg += 16;
16540     }
16541
16542   if ((sizeflag & SUFFIX_ALWAYS)
16543       && (bytemode == x_swap_mode
16544           || bytemode == d_swap_mode
16545           || bytemode == d_scalar_swap_mode
16546           || bytemode == q_swap_mode
16547           || bytemode == q_scalar_swap_mode))
16548     swap_operand ();
16549
16550   if (need_vex
16551       && bytemode != xmm_mode
16552       && bytemode != xmmdw_mode
16553       && bytemode != xmmqd_mode
16554       && bytemode != xmm_mb_mode
16555       && bytemode != xmm_mw_mode
16556       && bytemode != xmm_md_mode
16557       && bytemode != xmm_mq_mode
16558       && bytemode != xmm_mdq_mode
16559       && bytemode != xmmq_mode
16560       && bytemode != evex_half_bcst_xmmq_mode
16561       && bytemode != ymm_mode
16562       && bytemode != d_scalar_mode
16563       && bytemode != d_scalar_swap_mode
16564       && bytemode != q_scalar_mode
16565       && bytemode != q_scalar_swap_mode
16566       && bytemode != vex_scalar_w_dq_mode)
16567     {
16568       switch (vex.length)
16569         {
16570         case 128:
16571           names = names_xmm;
16572           break;
16573         case 256:
16574           names = names_ymm;
16575           break;
16576         case 512:
16577           names = names_zmm;
16578           break;
16579         default:
16580           abort ();
16581         }
16582     }
16583   else if (bytemode == xmmq_mode
16584            || bytemode == evex_half_bcst_xmmq_mode)
16585     {
16586       switch (vex.length)
16587         {
16588         case 128:
16589         case 256:
16590           names = names_xmm;
16591           break;
16592         case 512:
16593           names = names_ymm;
16594           break;
16595         default:
16596           abort ();
16597         }
16598     }
16599   else if (bytemode == ymm_mode)
16600     names = names_ymm;
16601   else
16602     names = names_xmm;
16603   oappend (names[reg]);
16604 }
16605
16606 static void
16607 OP_MS (int bytemode, int sizeflag)
16608 {
16609   if (modrm.mod == 3)
16610     OP_EM (bytemode, sizeflag);
16611   else
16612     BadOp ();
16613 }
16614
16615 static void
16616 OP_XS (int bytemode, int sizeflag)
16617 {
16618   if (modrm.mod == 3)
16619     OP_EX (bytemode, sizeflag);
16620   else
16621     BadOp ();
16622 }
16623
16624 static void
16625 OP_M (int bytemode, int sizeflag)
16626 {
16627   if (modrm.mod == 3)
16628     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
16629     BadOp ();
16630   else
16631     OP_E (bytemode, sizeflag);
16632 }
16633
16634 static void
16635 OP_0f07 (int bytemode, int sizeflag)
16636 {
16637   if (modrm.mod != 3 || modrm.rm != 0)
16638     BadOp ();
16639   else
16640     OP_E (bytemode, sizeflag);
16641 }
16642
16643 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
16644    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
16645
16646 static void
16647 NOP_Fixup1 (int bytemode, int sizeflag)
16648 {
16649   if ((prefixes & PREFIX_DATA) != 0
16650       || (rex != 0
16651           && rex != 0x48
16652           && address_mode == mode_64bit))
16653     OP_REG (bytemode, sizeflag);
16654   else
16655     strcpy (obuf, "nop");
16656 }
16657
16658 static void
16659 NOP_Fixup2 (int bytemode, int sizeflag)
16660 {
16661   if ((prefixes & PREFIX_DATA) != 0
16662       || (rex != 0
16663           && rex != 0x48
16664           && address_mode == mode_64bit))
16665     OP_IMREG (bytemode, sizeflag);
16666 }
16667
16668 static const char *const Suffix3DNow[] = {
16669 /* 00 */        NULL,           NULL,           NULL,           NULL,
16670 /* 04 */        NULL,           NULL,           NULL,           NULL,
16671 /* 08 */        NULL,           NULL,           NULL,           NULL,
16672 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
16673 /* 10 */        NULL,           NULL,           NULL,           NULL,
16674 /* 14 */        NULL,           NULL,           NULL,           NULL,
16675 /* 18 */        NULL,           NULL,           NULL,           NULL,
16676 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
16677 /* 20 */        NULL,           NULL,           NULL,           NULL,
16678 /* 24 */        NULL,           NULL,           NULL,           NULL,
16679 /* 28 */        NULL,           NULL,           NULL,           NULL,
16680 /* 2C */        NULL,           NULL,           NULL,           NULL,
16681 /* 30 */        NULL,           NULL,           NULL,           NULL,
16682 /* 34 */        NULL,           NULL,           NULL,           NULL,
16683 /* 38 */        NULL,           NULL,           NULL,           NULL,
16684 /* 3C */        NULL,           NULL,           NULL,           NULL,
16685 /* 40 */        NULL,           NULL,           NULL,           NULL,
16686 /* 44 */        NULL,           NULL,           NULL,           NULL,
16687 /* 48 */        NULL,           NULL,           NULL,           NULL,
16688 /* 4C */        NULL,           NULL,           NULL,           NULL,
16689 /* 50 */        NULL,           NULL,           NULL,           NULL,
16690 /* 54 */        NULL,           NULL,           NULL,           NULL,
16691 /* 58 */        NULL,           NULL,           NULL,           NULL,
16692 /* 5C */        NULL,           NULL,           NULL,           NULL,
16693 /* 60 */        NULL,           NULL,           NULL,           NULL,
16694 /* 64 */        NULL,           NULL,           NULL,           NULL,
16695 /* 68 */        NULL,           NULL,           NULL,           NULL,
16696 /* 6C */        NULL,           NULL,           NULL,           NULL,
16697 /* 70 */        NULL,           NULL,           NULL,           NULL,
16698 /* 74 */        NULL,           NULL,           NULL,           NULL,
16699 /* 78 */        NULL,           NULL,           NULL,           NULL,
16700 /* 7C */        NULL,           NULL,           NULL,           NULL,
16701 /* 80 */        NULL,           NULL,           NULL,           NULL,
16702 /* 84 */        NULL,           NULL,           NULL,           NULL,
16703 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
16704 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
16705 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
16706 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
16707 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
16708 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
16709 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
16710 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
16711 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
16712 /* AC */        NULL,           NULL,           "pfacc",        NULL,
16713 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
16714 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
16715 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
16716 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
16717 /* C0 */        NULL,           NULL,           NULL,           NULL,
16718 /* C4 */        NULL,           NULL,           NULL,           NULL,
16719 /* C8 */        NULL,           NULL,           NULL,           NULL,
16720 /* CC */        NULL,           NULL,           NULL,           NULL,
16721 /* D0 */        NULL,           NULL,           NULL,           NULL,
16722 /* D4 */        NULL,           NULL,           NULL,           NULL,
16723 /* D8 */        NULL,           NULL,           NULL,           NULL,
16724 /* DC */        NULL,           NULL,           NULL,           NULL,
16725 /* E0 */        NULL,           NULL,           NULL,           NULL,
16726 /* E4 */        NULL,           NULL,           NULL,           NULL,
16727 /* E8 */        NULL,           NULL,           NULL,           NULL,
16728 /* EC */        NULL,           NULL,           NULL,           NULL,
16729 /* F0 */        NULL,           NULL,           NULL,           NULL,
16730 /* F4 */        NULL,           NULL,           NULL,           NULL,
16731 /* F8 */        NULL,           NULL,           NULL,           NULL,
16732 /* FC */        NULL,           NULL,           NULL,           NULL,
16733 };
16734
16735 static void
16736 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16737 {
16738   const char *mnemonic;
16739
16740   FETCH_DATA (the_info, codep + 1);
16741   /* AMD 3DNow! instructions are specified by an opcode suffix in the
16742      place where an 8-bit immediate would normally go.  ie. the last
16743      byte of the instruction.  */
16744   obufp = mnemonicendp;
16745   mnemonic = Suffix3DNow[*codep++ & 0xff];
16746   if (mnemonic)
16747     oappend (mnemonic);
16748   else
16749     {
16750       /* Since a variable sized modrm/sib chunk is between the start
16751          of the opcode (0x0f0f) and the opcode suffix, we need to do
16752          all the modrm processing first, and don't know until now that
16753          we have a bad opcode.  This necessitates some cleaning up.  */
16754       op_out[0][0] = '\0';
16755       op_out[1][0] = '\0';
16756       BadOp ();
16757     }
16758   mnemonicendp = obufp;
16759 }
16760
16761 static struct op simd_cmp_op[] =
16762 {
16763   { STRING_COMMA_LEN ("eq") },
16764   { STRING_COMMA_LEN ("lt") },
16765   { STRING_COMMA_LEN ("le") },
16766   { STRING_COMMA_LEN ("unord") },
16767   { STRING_COMMA_LEN ("neq") },
16768   { STRING_COMMA_LEN ("nlt") },
16769   { STRING_COMMA_LEN ("nle") },
16770   { STRING_COMMA_LEN ("ord") }
16771 };
16772
16773 static void
16774 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16775 {
16776   unsigned int cmp_type;
16777
16778   FETCH_DATA (the_info, codep + 1);
16779   cmp_type = *codep++ & 0xff;
16780   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
16781     {
16782       char suffix [3];
16783       char *p = mnemonicendp - 2;
16784       suffix[0] = p[0];
16785       suffix[1] = p[1];
16786       suffix[2] = '\0';
16787       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16788       mnemonicendp += simd_cmp_op[cmp_type].len;
16789     }
16790   else
16791     {
16792       /* We have a reserved extension byte.  Output it directly.  */
16793       scratchbuf[0] = '$';
16794       print_operand_value (scratchbuf + 1, 1, cmp_type);
16795       oappend_maybe_intel (scratchbuf);
16796       scratchbuf[0] = '\0';
16797     }
16798 }
16799
16800 static void
16801 OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED,
16802           int sizeflag ATTRIBUTE_UNUSED)
16803 {
16804   /* mwaitx %eax,%ecx,%ebx */
16805   if (!intel_syntax)
16806     {
16807       const char **names = (address_mode == mode_64bit
16808                             ? names64 : names32);
16809       strcpy (op_out[0], names[0]);
16810       strcpy (op_out[1], names[1]);
16811       strcpy (op_out[2], names[3]);
16812       two_source_ops = 1;
16813     }
16814   /* Skip mod/rm byte.  */
16815   MODRM_CHECK;
16816   codep++;
16817 }
16818
16819 static void
16820 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
16821           int sizeflag ATTRIBUTE_UNUSED)
16822 {
16823   /* mwait %eax,%ecx  */
16824   if (!intel_syntax)
16825     {
16826       const char **names = (address_mode == mode_64bit
16827                             ? names64 : names32);
16828       strcpy (op_out[0], names[0]);
16829       strcpy (op_out[1], names[1]);
16830       two_source_ops = 1;
16831     }
16832   /* Skip mod/rm byte.  */
16833   MODRM_CHECK;
16834   codep++;
16835 }
16836
16837 static void
16838 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
16839             int sizeflag ATTRIBUTE_UNUSED)
16840 {
16841   /* monitor %eax,%ecx,%edx"  */
16842   if (!intel_syntax)
16843     {
16844       const char **op1_names;
16845       const char **names = (address_mode == mode_64bit
16846                             ? names64 : names32);
16847
16848       if (!(prefixes & PREFIX_ADDR))
16849         op1_names = (address_mode == mode_16bit
16850                      ? names16 : names);
16851       else
16852         {
16853           /* Remove "addr16/addr32".  */
16854           all_prefixes[last_addr_prefix] = 0;
16855           op1_names = (address_mode != mode_32bit
16856                        ? names32 : names16);
16857           used_prefixes |= PREFIX_ADDR;
16858         }
16859       strcpy (op_out[0], op1_names[0]);
16860       strcpy (op_out[1], names[1]);
16861       strcpy (op_out[2], names[2]);
16862       two_source_ops = 1;
16863     }
16864   /* Skip mod/rm byte.  */
16865   MODRM_CHECK;
16866   codep++;
16867 }
16868
16869 static void
16870 BadOp (void)
16871 {
16872   /* Throw away prefixes and 1st. opcode byte.  */
16873   codep = insn_codep + 1;
16874   oappend ("(bad)");
16875 }
16876
16877 static void
16878 REP_Fixup (int bytemode, int sizeflag)
16879 {
16880   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
16881      lods and stos.  */
16882   if (prefixes & PREFIX_REPZ)
16883     all_prefixes[last_repz_prefix] = REP_PREFIX;
16884
16885   switch (bytemode)
16886     {
16887     case al_reg:
16888     case eAX_reg:
16889     case indir_dx_reg:
16890       OP_IMREG (bytemode, sizeflag);
16891       break;
16892     case eDI_reg:
16893       OP_ESreg (bytemode, sizeflag);
16894       break;
16895     case eSI_reg:
16896       OP_DSreg (bytemode, sizeflag);
16897       break;
16898     default:
16899       abort ();
16900       break;
16901     }
16902 }
16903
16904 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
16905    "bnd".  */
16906
16907 static void
16908 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16909 {
16910   if (prefixes & PREFIX_REPNZ)
16911     all_prefixes[last_repnz_prefix] = BND_PREFIX;
16912 }
16913
16914 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
16915    "notrack".  */
16916
16917 static void
16918 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED,
16919                int sizeflag ATTRIBUTE_UNUSED)
16920 {
16921   if (active_seg_prefix == PREFIX_DS
16922       && (address_mode != mode_64bit || last_data_prefix < 0))
16923     {
16924       /* NOTRACK prefix is only valid on indirect branch instructions.
16925          NB: DATA prefix is unsupported for Intel64.  */
16926       active_seg_prefix = 0;
16927       all_prefixes[last_seg_prefix] = NOTRACK_PREFIX;
16928     }
16929 }
16930
16931 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
16932    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
16933  */
16934
16935 static void
16936 HLE_Fixup1 (int bytemode, int sizeflag)
16937 {
16938   if (modrm.mod != 3
16939       && (prefixes & PREFIX_LOCK) != 0)
16940     {
16941       if (prefixes & PREFIX_REPZ)
16942         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16943       if (prefixes & PREFIX_REPNZ)
16944         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16945     }
16946
16947   OP_E (bytemode, sizeflag);
16948 }
16949
16950 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
16951    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
16952  */
16953
16954 static void
16955 HLE_Fixup2 (int bytemode, int sizeflag)
16956 {
16957   if (modrm.mod != 3)
16958     {
16959       if (prefixes & PREFIX_REPZ)
16960         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16961       if (prefixes & PREFIX_REPNZ)
16962         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16963     }
16964
16965   OP_E (bytemode, sizeflag);
16966 }
16967
16968 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
16969    "xrelease" for memory operand.  No check for LOCK prefix.   */
16970
16971 static void
16972 HLE_Fixup3 (int bytemode, int sizeflag)
16973 {
16974   if (modrm.mod != 3
16975       && last_repz_prefix > last_repnz_prefix
16976       && (prefixes & PREFIX_REPZ) != 0)
16977     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16978
16979   OP_E (bytemode, sizeflag);
16980 }
16981
16982 static void
16983 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
16984 {
16985   USED_REX (REX_W);
16986   if (rex & REX_W)
16987     {
16988       /* Change cmpxchg8b to cmpxchg16b.  */
16989       char *p = mnemonicendp - 2;
16990       mnemonicendp = stpcpy (p, "16b");
16991       bytemode = o_mode;
16992     }
16993   else if ((prefixes & PREFIX_LOCK) != 0)
16994     {
16995       if (prefixes & PREFIX_REPZ)
16996         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16997       if (prefixes & PREFIX_REPNZ)
16998         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16999     }
17000
17001   OP_M (bytemode, sizeflag);
17002 }
17003
17004 static void
17005 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
17006 {
17007   const char **names;
17008
17009   if (need_vex)
17010     {
17011       switch (vex.length)
17012         {
17013         case 128:
17014           names = names_xmm;
17015           break;
17016         case 256:
17017           names = names_ymm;
17018           break;
17019         default:
17020           abort ();
17021         }
17022     }
17023   else
17024     names = names_xmm;
17025   oappend (names[reg]);
17026 }
17027
17028 static void
17029 CRC32_Fixup (int bytemode, int sizeflag)
17030 {
17031   /* Add proper suffix to "crc32".  */
17032   char *p = mnemonicendp;
17033
17034   switch (bytemode)
17035     {
17036     case b_mode:
17037       if (intel_syntax)
17038         goto skip;
17039
17040       *p++ = 'b';
17041       break;
17042     case v_mode:
17043       if (intel_syntax)
17044         goto skip;
17045
17046       USED_REX (REX_W);
17047       if (rex & REX_W)
17048         *p++ = 'q';
17049       else
17050         {
17051           if (sizeflag & DFLAG)
17052             *p++ = 'l';
17053           else
17054             *p++ = 'w';
17055           used_prefixes |= (prefixes & PREFIX_DATA);
17056         }
17057       break;
17058     default:
17059       oappend (INTERNAL_DISASSEMBLER_ERROR);
17060       break;
17061     }
17062   mnemonicendp = p;
17063   *p = '\0';
17064
17065 skip:
17066   if (modrm.mod == 3)
17067     {
17068       int add;
17069
17070       /* Skip mod/rm byte.  */
17071       MODRM_CHECK;
17072       codep++;
17073
17074       USED_REX (REX_B);
17075       add = (rex & REX_B) ? 8 : 0;
17076       if (bytemode == b_mode)
17077         {
17078           USED_REX (0);
17079           if (rex)
17080             oappend (names8rex[modrm.rm + add]);
17081           else
17082             oappend (names8[modrm.rm + add]);
17083         }
17084       else
17085         {
17086           USED_REX (REX_W);
17087           if (rex & REX_W)
17088             oappend (names64[modrm.rm + add]);
17089           else if ((prefixes & PREFIX_DATA))
17090             oappend (names16[modrm.rm + add]);
17091           else
17092             oappend (names32[modrm.rm + add]);
17093         }
17094     }
17095   else
17096     OP_E (bytemode, sizeflag);
17097 }
17098
17099 static void
17100 FXSAVE_Fixup (int bytemode, int sizeflag)
17101 {
17102   /* Add proper suffix to "fxsave" and "fxrstor".  */
17103   USED_REX (REX_W);
17104   if (rex & REX_W)
17105     {
17106       char *p = mnemonicendp;
17107       *p++ = '6';
17108       *p++ = '4';
17109       *p = '\0';
17110       mnemonicendp = p;
17111     }
17112   OP_M (bytemode, sizeflag);
17113 }
17114
17115 static void
17116 PCMPESTR_Fixup (int bytemode, int sizeflag)
17117 {
17118   /* Add proper suffix to "{,v}pcmpestr{i,m}".  */
17119   if (!intel_syntax)
17120     {
17121       char *p = mnemonicendp;
17122
17123       USED_REX (REX_W);
17124       if (rex & REX_W)
17125         *p++ = 'q';
17126       else if (sizeflag & SUFFIX_ALWAYS)
17127         *p++ = 'l';
17128
17129       *p = '\0';
17130       mnemonicendp = p;
17131     }
17132
17133   OP_EX (bytemode, sizeflag);
17134 }
17135
17136 /* Display the destination register operand for instructions with
17137    VEX. */
17138
17139 static void
17140 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17141 {
17142   int reg;
17143   const char **names;
17144
17145   if (!need_vex)
17146     abort ();
17147
17148   if (!need_vex_reg)
17149     return;
17150
17151   reg = vex.register_specifier;
17152   if (address_mode != mode_64bit)
17153     reg &= 7;
17154   else if (vex.evex && !vex.v)
17155     reg += 16;
17156
17157   if (bytemode == vex_scalar_mode)
17158     {
17159       oappend (names_xmm[reg]);
17160       return;
17161     }
17162
17163   switch (vex.length)
17164     {
17165     case 128:
17166       switch (bytemode)
17167         {
17168         case vex_mode:
17169         case vex128_mode:
17170         case vex_vsib_q_w_dq_mode:
17171         case vex_vsib_q_w_d_mode:
17172           names = names_xmm;
17173           break;
17174         case dq_mode:
17175           if (rex & REX_W)
17176             names = names64;
17177           else
17178             names = names32;
17179           break;
17180         case mask_bd_mode:
17181         case mask_mode:
17182           if (reg > 0x7)
17183             {
17184               oappend ("(bad)");
17185               return;
17186             }
17187           names = names_mask;
17188           break;
17189         default:
17190           abort ();
17191           return;
17192         }
17193       break;
17194     case 256:
17195       switch (bytemode)
17196         {
17197         case vex_mode:
17198         case vex256_mode:
17199           names = names_ymm;
17200           break;
17201         case vex_vsib_q_w_dq_mode:
17202         case vex_vsib_q_w_d_mode:
17203           names = vex.w ? names_ymm : names_xmm;
17204           break;
17205         case mask_bd_mode:
17206         case mask_mode:
17207           if (reg > 0x7)
17208             {
17209               oappend ("(bad)");
17210               return;
17211             }
17212           names = names_mask;
17213           break;
17214         default:
17215           /* See PR binutils/20893 for a reproducer.  */
17216           oappend ("(bad)");
17217           return;
17218         }
17219       break;
17220     case 512:
17221       names = names_zmm;
17222       break;
17223     default:
17224       abort ();
17225       break;
17226     }
17227   oappend (names[reg]);
17228 }
17229
17230 /* Get the VEX immediate byte without moving codep.  */
17231
17232 static unsigned char
17233 get_vex_imm8 (int sizeflag, int opnum)
17234 {
17235   int bytes_before_imm = 0;
17236
17237   if (modrm.mod != 3)
17238     {
17239       /* There are SIB/displacement bytes.  */
17240       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
17241         {
17242           /* 32/64 bit address mode */
17243           int base = modrm.rm;
17244
17245           /* Check SIB byte.  */
17246           if (base == 4)
17247             {
17248               FETCH_DATA (the_info, codep + 1);
17249               base = *codep & 7;
17250               /* When decoding the third source, don't increase
17251                  bytes_before_imm as this has already been incremented
17252                  by one in OP_E_memory while decoding the second
17253                  source operand.  */
17254               if (opnum == 0)
17255                 bytes_before_imm++;
17256             }
17257
17258           /* Don't increase bytes_before_imm when decoding the third source,
17259              it has already been incremented by OP_E_memory while decoding
17260              the second source operand.  */
17261           if (opnum == 0)
17262             {
17263               switch (modrm.mod)
17264                 {
17265                   case 0:
17266                     /* When modrm.rm == 5 or modrm.rm == 4 and base in
17267                        SIB == 5, there is a 4 byte displacement.  */
17268                     if (base != 5)
17269                       /* No displacement. */
17270                       break;
17271                     /* Fall through.  */
17272                   case 2:
17273                     /* 4 byte displacement.  */
17274                     bytes_before_imm += 4;
17275                     break;
17276                   case 1:
17277                     /* 1 byte displacement.  */
17278                     bytes_before_imm++;
17279                     break;
17280                 }
17281             }
17282         }
17283       else
17284         {
17285           /* 16 bit address mode */
17286           /* Don't increase bytes_before_imm when decoding the third source,
17287              it has already been incremented by OP_E_memory while decoding
17288              the second source operand.  */
17289           if (opnum == 0)
17290             {
17291               switch (modrm.mod)
17292                 {
17293                 case 0:
17294                   /* When modrm.rm == 6, there is a 2 byte displacement.  */
17295                   if (modrm.rm != 6)
17296                     /* No displacement. */
17297                     break;
17298                   /* Fall through.  */
17299                 case 2:
17300                   /* 2 byte displacement.  */
17301                   bytes_before_imm += 2;
17302                   break;
17303                 case 1:
17304                   /* 1 byte displacement: when decoding the third source,
17305                      don't increase bytes_before_imm as this has already
17306                      been incremented by one in OP_E_memory while decoding
17307                      the second source operand.  */
17308                   if (opnum == 0)
17309                     bytes_before_imm++;
17310
17311                   break;
17312                 }
17313             }
17314         }
17315     }
17316
17317   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
17318   return codep [bytes_before_imm];
17319 }
17320
17321 static void
17322 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
17323 {
17324   const char **names;
17325
17326   if (reg == -1 && modrm.mod != 3)
17327     {
17328       OP_E_memory (bytemode, sizeflag);
17329       return;
17330     }
17331   else
17332     {
17333       if (reg == -1)
17334         {
17335           reg = modrm.rm;
17336           USED_REX (REX_B);
17337           if (rex & REX_B)
17338             reg += 8;
17339         }
17340       if (address_mode != mode_64bit)
17341         reg &= 7;
17342     }
17343
17344   switch (vex.length)
17345     {
17346     case 128:
17347       names = names_xmm;
17348       break;
17349     case 256:
17350       names = names_ymm;
17351       break;
17352     default:
17353       abort ();
17354     }
17355   oappend (names[reg]);
17356 }
17357
17358 static void
17359 OP_EX_VexImmW (int bytemode, int sizeflag)
17360 {
17361   int reg = -1;
17362   static unsigned char vex_imm8;
17363
17364   if (vex_w_done == 0)
17365     {
17366       vex_w_done = 1;
17367
17368       /* Skip mod/rm byte.  */
17369       MODRM_CHECK;
17370       codep++;
17371
17372       vex_imm8 = get_vex_imm8 (sizeflag, 0);
17373
17374       if (vex.w)
17375           reg = vex_imm8 >> 4;
17376
17377       OP_EX_VexReg (bytemode, sizeflag, reg);
17378     }
17379   else if (vex_w_done == 1)
17380     {
17381       vex_w_done = 2;
17382
17383       if (!vex.w)
17384           reg = vex_imm8 >> 4;
17385
17386       OP_EX_VexReg (bytemode, sizeflag, reg);
17387     }
17388   else
17389     {
17390       /* Output the imm8 directly.  */
17391       scratchbuf[0] = '$';
17392       print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
17393       oappend_maybe_intel (scratchbuf);
17394       scratchbuf[0] = '\0';
17395       codep++;
17396     }
17397 }
17398
17399 static void
17400 OP_Vex_2src (int bytemode, int sizeflag)
17401 {
17402   if (modrm.mod == 3)
17403     {
17404       int reg = modrm.rm;
17405       USED_REX (REX_B);
17406       if (rex & REX_B)
17407         reg += 8;
17408       oappend (names_xmm[reg]);
17409     }
17410   else
17411     {
17412       if (intel_syntax
17413           && (bytemode == v_mode || bytemode == v_swap_mode))
17414         {
17415           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
17416           used_prefixes |= (prefixes & PREFIX_DATA);
17417         }
17418       OP_E (bytemode, sizeflag);
17419     }
17420 }
17421
17422 static void
17423 OP_Vex_2src_1 (int bytemode, int sizeflag)
17424 {
17425   if (modrm.mod == 3)
17426     {
17427       /* Skip mod/rm byte.   */
17428       MODRM_CHECK;
17429       codep++;
17430     }
17431
17432   if (vex.w)
17433     {
17434       unsigned int reg = vex.register_specifier;
17435
17436       if (address_mode != mode_64bit)
17437         reg &= 7;
17438       oappend (names_xmm[reg]);
17439     }
17440   else
17441     OP_Vex_2src (bytemode, sizeflag);
17442 }
17443
17444 static void
17445 OP_Vex_2src_2 (int bytemode, int sizeflag)
17446 {
17447   if (vex.w)
17448     OP_Vex_2src (bytemode, sizeflag);
17449   else
17450     {
17451       unsigned int reg = vex.register_specifier;
17452
17453       if (address_mode != mode_64bit)
17454         reg &= 7;
17455       oappend (names_xmm[reg]);
17456     }
17457 }
17458
17459 static void
17460 OP_EX_VexW (int bytemode, int sizeflag)
17461 {
17462   int reg = -1;
17463
17464   if (!vex_w_done)
17465     {
17466       /* Skip mod/rm byte.  */
17467       MODRM_CHECK;
17468       codep++;
17469
17470       if (vex.w)
17471         reg = get_vex_imm8 (sizeflag, 0) >> 4;
17472     }
17473   else
17474     {
17475       if (!vex.w)
17476         reg = get_vex_imm8 (sizeflag, 1) >> 4;
17477     }
17478
17479   OP_EX_VexReg (bytemode, sizeflag, reg);
17480
17481   if (vex_w_done)
17482     codep++;
17483   vex_w_done = 1;
17484 }
17485
17486 static void
17487 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17488 {
17489   int reg;
17490   const char **names;
17491
17492   FETCH_DATA (the_info, codep + 1);
17493   reg = *codep++;
17494
17495   if (bytemode != x_mode)
17496     abort ();
17497
17498   reg >>= 4;
17499   if (address_mode != mode_64bit)
17500     reg &= 7;
17501
17502   switch (vex.length)
17503     {
17504     case 128:
17505       names = names_xmm;
17506       break;
17507     case 256:
17508       names = names_ymm;
17509       break;
17510     default:
17511       abort ();
17512     }
17513   oappend (names[reg]);
17514 }
17515
17516 static void
17517 OP_XMM_VexW (int bytemode, int sizeflag)
17518 {
17519   /* Turn off the REX.W bit since it is used for swapping operands
17520      now.  */
17521   rex &= ~REX_W;
17522   OP_XMM (bytemode, sizeflag);
17523 }
17524
17525 static void
17526 OP_EX_Vex (int bytemode, int sizeflag)
17527 {
17528   if (modrm.mod != 3)
17529     {
17530       if (vex.register_specifier != 0)
17531         BadOp ();
17532       need_vex_reg = 0;
17533     }
17534   OP_EX (bytemode, sizeflag);
17535 }
17536
17537 static void
17538 OP_XMM_Vex (int bytemode, int sizeflag)
17539 {
17540   if (modrm.mod != 3)
17541     {
17542       if (vex.register_specifier != 0)
17543         BadOp ();
17544       need_vex_reg = 0;
17545     }
17546   OP_XMM (bytemode, sizeflag);
17547 }
17548
17549 static void
17550 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17551 {
17552   switch (vex.length)
17553     {
17554     case 128:
17555       mnemonicendp = stpcpy (obuf, "vzeroupper");
17556       break;
17557     case 256:
17558       mnemonicendp = stpcpy (obuf, "vzeroall");
17559       break;
17560     default:
17561       abort ();
17562     }
17563 }
17564
17565 static struct op vex_cmp_op[] =
17566 {
17567   { STRING_COMMA_LEN ("eq") },
17568   { STRING_COMMA_LEN ("lt") },
17569   { STRING_COMMA_LEN ("le") },
17570   { STRING_COMMA_LEN ("unord") },
17571   { STRING_COMMA_LEN ("neq") },
17572   { STRING_COMMA_LEN ("nlt") },
17573   { STRING_COMMA_LEN ("nle") },
17574   { STRING_COMMA_LEN ("ord") },
17575   { STRING_COMMA_LEN ("eq_uq") },
17576   { STRING_COMMA_LEN ("nge") },
17577   { STRING_COMMA_LEN ("ngt") },
17578   { STRING_COMMA_LEN ("false") },
17579   { STRING_COMMA_LEN ("neq_oq") },
17580   { STRING_COMMA_LEN ("ge") },
17581   { STRING_COMMA_LEN ("gt") },
17582   { STRING_COMMA_LEN ("true") },
17583   { STRING_COMMA_LEN ("eq_os") },
17584   { STRING_COMMA_LEN ("lt_oq") },
17585   { STRING_COMMA_LEN ("le_oq") },
17586   { STRING_COMMA_LEN ("unord_s") },
17587   { STRING_COMMA_LEN ("neq_us") },
17588   { STRING_COMMA_LEN ("nlt_uq") },
17589   { STRING_COMMA_LEN ("nle_uq") },
17590   { STRING_COMMA_LEN ("ord_s") },
17591   { STRING_COMMA_LEN ("eq_us") },
17592   { STRING_COMMA_LEN ("nge_uq") },
17593   { STRING_COMMA_LEN ("ngt_uq") },
17594   { STRING_COMMA_LEN ("false_os") },
17595   { STRING_COMMA_LEN ("neq_os") },
17596   { STRING_COMMA_LEN ("ge_oq") },
17597   { STRING_COMMA_LEN ("gt_oq") },
17598   { STRING_COMMA_LEN ("true_us") },
17599 };
17600
17601 static void
17602 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17603 {
17604   unsigned int cmp_type;
17605
17606   FETCH_DATA (the_info, codep + 1);
17607   cmp_type = *codep++ & 0xff;
17608   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
17609     {
17610       char suffix [3];
17611       char *p = mnemonicendp - 2;
17612       suffix[0] = p[0];
17613       suffix[1] = p[1];
17614       suffix[2] = '\0';
17615       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
17616       mnemonicendp += vex_cmp_op[cmp_type].len;
17617     }
17618   else
17619     {
17620       /* We have a reserved extension byte.  Output it directly.  */
17621       scratchbuf[0] = '$';
17622       print_operand_value (scratchbuf + 1, 1, cmp_type);
17623       oappend_maybe_intel (scratchbuf);
17624       scratchbuf[0] = '\0';
17625     }
17626 }
17627
17628 static void
17629 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
17630              int sizeflag ATTRIBUTE_UNUSED)
17631 {
17632   unsigned int cmp_type;
17633
17634   if (!vex.evex)
17635     abort ();
17636
17637   FETCH_DATA (the_info, codep + 1);
17638   cmp_type = *codep++ & 0xff;
17639   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
17640      If it's the case, print suffix, otherwise - print the immediate.  */
17641   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
17642       && cmp_type != 3
17643       && cmp_type != 7)
17644     {
17645       char suffix [3];
17646       char *p = mnemonicendp - 2;
17647
17648       /* vpcmp* can have both one- and two-lettered suffix.  */
17649       if (p[0] == 'p')
17650         {
17651           p++;
17652           suffix[0] = p[0];
17653           suffix[1] = '\0';
17654         }
17655       else
17656         {
17657           suffix[0] = p[0];
17658           suffix[1] = p[1];
17659           suffix[2] = '\0';
17660         }
17661
17662       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
17663       mnemonicendp += simd_cmp_op[cmp_type].len;
17664     }
17665   else
17666     {
17667       /* We have a reserved extension byte.  Output it directly.  */
17668       scratchbuf[0] = '$';
17669       print_operand_value (scratchbuf + 1, 1, cmp_type);
17670       oappend_maybe_intel (scratchbuf);
17671       scratchbuf[0] = '\0';
17672     }
17673 }
17674
17675 static const struct op xop_cmp_op[] =
17676 {
17677   { STRING_COMMA_LEN ("lt") },
17678   { STRING_COMMA_LEN ("le") },
17679   { STRING_COMMA_LEN ("gt") },
17680   { STRING_COMMA_LEN ("ge") },
17681   { STRING_COMMA_LEN ("eq") },
17682   { STRING_COMMA_LEN ("neq") },
17683   { STRING_COMMA_LEN ("false") },
17684   { STRING_COMMA_LEN ("true") }
17685 };
17686
17687 static void
17688 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED,
17689              int sizeflag ATTRIBUTE_UNUSED)
17690 {
17691   unsigned int cmp_type;
17692
17693   FETCH_DATA (the_info, codep + 1);
17694   cmp_type = *codep++ & 0xff;
17695   if (cmp_type < ARRAY_SIZE (xop_cmp_op))
17696     {
17697       char suffix[3];
17698       char *p = mnemonicendp - 2;
17699
17700       /* vpcom* can have both one- and two-lettered suffix.  */
17701       if (p[0] == 'm')
17702         {
17703           p++;
17704           suffix[0] = p[0];
17705           suffix[1] = '\0';
17706         }
17707       else
17708         {
17709           suffix[0] = p[0];
17710           suffix[1] = p[1];
17711           suffix[2] = '\0';
17712         }
17713
17714       sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix);
17715       mnemonicendp += xop_cmp_op[cmp_type].len;
17716     }
17717   else
17718     {
17719       /* We have a reserved extension byte.  Output it directly.  */
17720       scratchbuf[0] = '$';
17721       print_operand_value (scratchbuf + 1, 1, cmp_type);
17722       oappend_maybe_intel (scratchbuf);
17723       scratchbuf[0] = '\0';
17724     }
17725 }
17726
17727 static const struct op pclmul_op[] =
17728 {
17729   { STRING_COMMA_LEN ("lql") },
17730   { STRING_COMMA_LEN ("hql") },
17731   { STRING_COMMA_LEN ("lqh") },
17732   { STRING_COMMA_LEN ("hqh") }
17733 };
17734
17735 static void
17736 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
17737               int sizeflag ATTRIBUTE_UNUSED)
17738 {
17739   unsigned int pclmul_type;
17740
17741   FETCH_DATA (the_info, codep + 1);
17742   pclmul_type = *codep++ & 0xff;
17743   switch (pclmul_type)
17744     {
17745     case 0x10:
17746       pclmul_type = 2;
17747       break;
17748     case 0x11:
17749       pclmul_type = 3;
17750       break;
17751     default:
17752       break;
17753     }
17754   if (pclmul_type < ARRAY_SIZE (pclmul_op))
17755     {
17756       char suffix [4];
17757       char *p = mnemonicendp - 3;
17758       suffix[0] = p[0];
17759       suffix[1] = p[1];
17760       suffix[2] = p[2];
17761       suffix[3] = '\0';
17762       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
17763       mnemonicendp += pclmul_op[pclmul_type].len;
17764     }
17765   else
17766     {
17767       /* We have a reserved extension byte.  Output it directly.  */
17768       scratchbuf[0] = '$';
17769       print_operand_value (scratchbuf + 1, 1, pclmul_type);
17770       oappend_maybe_intel (scratchbuf);
17771       scratchbuf[0] = '\0';
17772     }
17773 }
17774
17775 static void
17776 MOVBE_Fixup (int bytemode, int sizeflag)
17777 {
17778   /* Add proper suffix to "movbe".  */
17779   char *p = mnemonicendp;
17780
17781   switch (bytemode)
17782     {
17783     case v_mode:
17784       if (intel_syntax)
17785         goto skip;
17786
17787       USED_REX (REX_W);
17788       if (sizeflag & SUFFIX_ALWAYS)
17789         {
17790           if (rex & REX_W)
17791             *p++ = 'q';
17792           else
17793             {
17794               if (sizeflag & DFLAG)
17795                 *p++ = 'l';
17796               else
17797                 *p++ = 'w';
17798               used_prefixes |= (prefixes & PREFIX_DATA);
17799             }
17800         }
17801       break;
17802     default:
17803       oappend (INTERNAL_DISASSEMBLER_ERROR);
17804       break;
17805     }
17806   mnemonicendp = p;
17807   *p = '\0';
17808
17809 skip:
17810   OP_M (bytemode, sizeflag);
17811 }
17812
17813 static void
17814 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17815 {
17816   int reg;
17817   const char **names;
17818
17819   /* Skip mod/rm byte.  */
17820   MODRM_CHECK;
17821   codep++;
17822
17823   if (rex & REX_W)
17824     names = names64;
17825   else
17826     names = names32;
17827
17828   reg = modrm.rm;
17829   USED_REX (REX_B);
17830   if (rex & REX_B)
17831     reg += 8;
17832
17833   oappend (names[reg]);
17834 }
17835
17836 static void
17837 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17838 {
17839   const char **names;
17840   unsigned int reg = vex.register_specifier;
17841
17842   if (rex & REX_W)
17843     names = names64;
17844   else
17845     names = names32;
17846
17847   if (address_mode != mode_64bit)
17848     reg &= 7;
17849   oappend (names[reg]);
17850 }
17851
17852 static void
17853 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17854 {
17855   if (!vex.evex
17856       || (bytemode != mask_mode && bytemode != mask_bd_mode))
17857     abort ();
17858
17859   USED_REX (REX_R);
17860   if ((rex & REX_R) != 0 || !vex.r)
17861     {
17862       BadOp ();
17863       return;
17864     }
17865
17866   oappend (names_mask [modrm.reg]);
17867 }
17868
17869 static void
17870 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17871 {
17872   if (!vex.evex
17873       || (bytemode != evex_rounding_mode
17874           && bytemode != evex_sae_mode))
17875     abort ();
17876   if (modrm.mod == 3 && vex.b)
17877     switch (bytemode)
17878       {
17879       case evex_rounding_mode:
17880         oappend (names_rounding[vex.ll]);
17881         break;
17882       case evex_sae_mode:
17883         oappend ("{sae}");
17884         break;
17885       default:
17886         break;
17887       }
17888 }