opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2014 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "dis-asm.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40
  41 #include <setjmp.h>
  42
  43 static int print_insn (bfd_vma, disassemble_info *);
  44 static void dofloat (int);
  45 static void OP_ST (int, int);
  46 static void OP_STi (int, int);
  47 static int putop (const char *, int);
  48 static void oappend (const char *);
  49 static void append_seg (void);
  50 static void OP_indirE (int, int);
  51 static void print_operand_value (char *, int, bfd_vma);
  52 static void OP_E_register (int, int);
  53 static void OP_E_memory (int, int);
  54 static void print_displacement (char *, bfd_vma);
  55 static void OP_E (int, int);
  56 static void OP_G (int, int);
  57 static bfd_vma get64 (void);
  58 static bfd_signed_vma get32 (void);
  59 static bfd_signed_vma get32s (void);
  60 static int get16 (void);
  61 static void set_op (bfd_vma, int);
  62 static void OP_Skip_MODRM (int, int);
  63 static void OP_REG (int, int);
  64 static void OP_IMREG (int, int);
  65 static void OP_I (int, int);
  66 static void OP_I64 (int, int);
  67 static void OP_sI (int, int);
  68 static void OP_J (int, int);
  69 static void OP_SEG (int, int);
  70 static void OP_DIR (int, int);
  71 static void OP_OFF (int, int);
  72 static void OP_OFF64 (int, int);
  73 static void ptr_reg (int, int);
  74 static void OP_ESreg (int, int);
  75 static void OP_DSreg (int, int);
  76 static void OP_C (int, int);
  77 static void OP_D (int, int);
  78 static void OP_T (int, int);
  79 static void OP_R (int, int);
  80 static void OP_MMX (int, int);
  81 static void OP_XMM (int, int);
  82 static void OP_EM (int, int);
  83 static void OP_EX (int, int);
  84 static void OP_EMC (int,int);
  85 static void OP_MXC (int,int);
  86 static void OP_MS (int, int);
  87 static void OP_XS (int, int);
  88 static void OP_M (int, int);
  89 static void OP_VEX (int, int);
  90 static void OP_EX_Vex (int, int);
  91 static void OP_EX_VexW (int, int);
  92 static void OP_EX_VexImmW (int, int);
  93 static void OP_XMM_Vex (int, int);
  94 static void OP_XMM_VexW (int, int);
  95 static void OP_Rounding (int, int);
  96 static void OP_REG_VexI4 (int, int);
  97 static void PCLMUL_Fixup (int, int);
  98 static void VEXI4_Fixup (int, int);
  99 static void VZERO_Fixup (int, int);
 100 static void VCMP_Fixup (int, int);
 101 static void VPCMP_Fixup (int, int);
 102 static void OP_0f07 (int, int);
 103 static void OP_Monitor (int, int);
 104 static void OP_Mwait (int, int);
 105 static void NOP_Fixup1 (int, int);
 106 static void NOP_Fixup2 (int, int);
 107 static void OP_3DNowSuffix (int, int);
 108 static void CMP_Fixup (int, int);
 109 static void BadOp (void);
 110 static void REP_Fixup (int, int);
 111 static void BND_Fixup (int, int);
 112 static void HLE_Fixup1 (int, int);
 113 static void HLE_Fixup2 (int, int);
 114 static void HLE_Fixup3 (int, int);
 115 static void CMPXCHG8B_Fixup (int, int);
 116 static void XMM_Fixup (int, int);
 117 static void CRC32_Fixup (int, int);
 118 static void FXSAVE_Fixup (int, int);
 119 static void OP_LWPCB_E (int, int);
 120 static void OP_LWP_E (int, int);
 121 static void OP_Vex_2src_1 (int, int);
 122 static void OP_Vex_2src_2 (int, int);
 123
 124 static void MOVBE_Fixup (int, int);
 125
 126 static void OP_Mask (int, int);
 127
 128 struct dis_private {
 129   /* Points to first byte not fetched.  */
 130   bfd_byte *max_fetched;
 131   bfd_byte the_buffer[MAX_MNEM_SIZE];
 132   bfd_vma insn_start;
 133   int orig_sizeflag;
 134   OPCODES_SIGJMP_BUF bailout;
 135 };
 136
 137 enum address_mode
 138 {
 139   mode_16bit,
 140   mode_32bit,
 141   mode_64bit
 142 };
 143
 144 enum address_mode address_mode;
 145
 146 /* Flags for the prefixes for the current instruction.  See below.  */
 147 static int prefixes;
 148
 149 /* REX prefix the current instruction.  See below.  */
 150 static int rex;
 151 /* Bits of REX we've already used.  */
 152 static int rex_used;
 153 /* REX bits in original REX prefix ignored.  */
 154 static int rex_ignored;
 155 /* Mark parts used in the REX prefix.  When we are testing for
 156    empty prefix (for 8bit register REX extension), just mask it
 157    out.  Otherwise test for REX bit is excuse for existence of REX
 158    only in case value is nonzero.  */
 159 #define USED_REX(value)                                 \
 160   {                                                     \
 161     if (value)                                          \
 162       {                                                 \
 163         if ((rex & value))                              \
 164           rex_used |= (value) | REX_OPCODE;             \
 165       }                                                 \
 166     else                                                \
 167       rex_used |= REX_OPCODE;                           \
 168   }
 169
 170 /* Flags for prefixes which we somehow handled when printing the
 171    current instruction.  */
 172 static int used_prefixes;
 173
 174 /* Flags stored in PREFIXES.  */
 175 #define PREFIX_REPZ 1
 176 #define PREFIX_REPNZ 2
 177 #define PREFIX_LOCK 4
 178 #define PREFIX_CS 8
 179 #define PREFIX_SS 0x10
 180 #define PREFIX_DS 0x20
 181 #define PREFIX_ES 0x40
 182 #define PREFIX_FS 0x80
 183 #define PREFIX_GS 0x100
 184 #define PREFIX_DATA 0x200
 185 #define PREFIX_ADDR 0x400
 186 #define PREFIX_FWAIT 0x800
 187
 188 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 189    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 190    on error.  */
 191 #define FETCH_DATA(info, addr) \
 192   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 193    ? 1 : fetch_data ((info), (addr)))
 194
 195 static int
 196 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 197 {
 198   int status;
 199   struct dis_private *priv = (struct dis_private *) info->private_data;
 200   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 201
 202   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 203     status = (*info->read_memory_func) (start,
 204                                         priv->max_fetched,
 205                                         addr - priv->max_fetched,
 206                                         info);
 207   else
 208     status = -1;
 209   if (status != 0)
 210     {
 211       /* If we did manage to read at least one byte, then
 212          print_insn_i386 will do something sensible.  Otherwise, print
 213          an error.  We do that here because this is where we know
 214          STATUS.  */
 215       if (priv->max_fetched == priv->the_buffer)
 216         (*info->memory_error_func) (status, start, info);
 217       OPCODES_SIGLONGJMP (priv->bailout, 1);
 218     }
 219   else
 220     priv->max_fetched = addr;
 221   return 1;
 222 }
 223
 224 #define XX { NULL, 0 }
 225 #define Bad_Opcode NULL, { { NULL, 0 } }
 226
 227 #define Eb { OP_E, b_mode }
 228 #define Ebnd { OP_E, bnd_mode }
 229 #define EbS { OP_E, b_swap_mode }
 230 #define Ev { OP_E, v_mode }
 231 #define Ev_bnd { OP_E, v_bnd_mode }
 232 #define EvS { OP_E, v_swap_mode }
 233 #define Ed { OP_E, d_mode }
 234 #define Edq { OP_E, dq_mode }
 235 #define Edqw { OP_E, dqw_mode }
 236 #define Edqb { OP_E, dqb_mode }
 237 #define Edqd { OP_E, dqd_mode }
 238 #define Eq { OP_E, q_mode }
 239 #define indirEv { OP_indirE, stack_v_mode }
 240 #define indirEp { OP_indirE, f_mode }
 241 #define stackEv { OP_E, stack_v_mode }
 242 #define Em { OP_E, m_mode }
 243 #define Ew { OP_E, w_mode }
 244 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 245 #define Ma { OP_M, a_mode }
 246 #define Mb { OP_M, b_mode }
 247 #define Md { OP_M, d_mode }
 248 #define Mo { OP_M, o_mode }
 249 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 250 #define Mq { OP_M, q_mode }
 251 #define Mx { OP_M, x_mode }
 252 #define Mxmm { OP_M, xmm_mode }
 253 #define Gb { OP_G, b_mode }
 254 #define Gbnd { OP_G, bnd_mode }
 255 #define Gv { OP_G, v_mode }
 256 #define Gd { OP_G, d_mode }
 257 #define Gdq { OP_G, dq_mode }
 258 #define Gm { OP_G, m_mode }
 259 #define Gw { OP_G, w_mode }
 260 #define Rd { OP_R, d_mode }
 261 #define Rdq { OP_R, dq_mode }
 262 #define Rm { OP_R, m_mode }
 263 #define Ib { OP_I, b_mode }
 264 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 265 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 266 #define Iv { OP_I, v_mode }
 267 #define sIv { OP_sI, v_mode }
 268 #define Iq { OP_I, q_mode }
 269 #define Iv64 { OP_I64, v_mode }
 270 #define Iw { OP_I, w_mode }
 271 #define I1 { OP_I, const_1_mode }
 272 #define Jb { OP_J, b_mode }
 273 #define Jv { OP_J, v_mode }
 274 #define Cm { OP_C, m_mode }
 275 #define Dm { OP_D, m_mode }
 276 #define Td { OP_T, d_mode }
 277 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 278
 279 #define RMeAX { OP_REG, eAX_reg }
 280 #define RMeBX { OP_REG, eBX_reg }
 281 #define RMeCX { OP_REG, eCX_reg }
 282 #define RMeDX { OP_REG, eDX_reg }
 283 #define RMeSP { OP_REG, eSP_reg }
 284 #define RMeBP { OP_REG, eBP_reg }
 285 #define RMeSI { OP_REG, eSI_reg }
 286 #define RMeDI { OP_REG, eDI_reg }
 287 #define RMrAX { OP_REG, rAX_reg }
 288 #define RMrBX { OP_REG, rBX_reg }
 289 #define RMrCX { OP_REG, rCX_reg }
 290 #define RMrDX { OP_REG, rDX_reg }
 291 #define RMrSP { OP_REG, rSP_reg }
 292 #define RMrBP { OP_REG, rBP_reg }
 293 #define RMrSI { OP_REG, rSI_reg }
 294 #define RMrDI { OP_REG, rDI_reg }
 295 #define RMAL { OP_REG, al_reg }
 296 #define RMCL { OP_REG, cl_reg }
 297 #define RMDL { OP_REG, dl_reg }
 298 #define RMBL { OP_REG, bl_reg }
 299 #define RMAH { OP_REG, ah_reg }
 300 #define RMCH { OP_REG, ch_reg }
 301 #define RMDH { OP_REG, dh_reg }
 302 #define RMBH { OP_REG, bh_reg }
 303 #define RMAX { OP_REG, ax_reg }
 304 #define RMDX { OP_REG, dx_reg }
 305
 306 #define eAX { OP_IMREG, eAX_reg }
 307 #define eBX { OP_IMREG, eBX_reg }
 308 #define eCX { OP_IMREG, eCX_reg }
 309 #define eDX { OP_IMREG, eDX_reg }
 310 #define eSP { OP_IMREG, eSP_reg }
 311 #define eBP { OP_IMREG, eBP_reg }
 312 #define eSI { OP_IMREG, eSI_reg }
 313 #define eDI { OP_IMREG, eDI_reg }
 314 #define AL { OP_IMREG, al_reg }
 315 #define CL { OP_IMREG, cl_reg }
 316 #define DL { OP_IMREG, dl_reg }
 317 #define BL { OP_IMREG, bl_reg }
 318 #define AH { OP_IMREG, ah_reg }
 319 #define CH { OP_IMREG, ch_reg }
 320 #define DH { OP_IMREG, dh_reg }
 321 #define BH { OP_IMREG, bh_reg }
 322 #define AX { OP_IMREG, ax_reg }
 323 #define DX { OP_IMREG, dx_reg }
 324 #define zAX { OP_IMREG, z_mode_ax_reg }
 325 #define indirDX { OP_IMREG, indir_dx_reg }
 326
 327 #define Sw { OP_SEG, w_mode }
 328 #define Sv { OP_SEG, v_mode }
 329 #define Ap { OP_DIR, 0 }
 330 #define Ob { OP_OFF64, b_mode }
 331 #define Ov { OP_OFF64, v_mode }
 332 #define Xb { OP_DSreg, eSI_reg }
 333 #define Xv { OP_DSreg, eSI_reg }
 334 #define Xz { OP_DSreg, eSI_reg }
 335 #define Yb { OP_ESreg, eDI_reg }
 336 #define Yv { OP_ESreg, eDI_reg }
 337 #define DSBX { OP_DSreg, eBX_reg }
 338
 339 #define es { OP_REG, es_reg }
 340 #define ss { OP_REG, ss_reg }
 341 #define cs { OP_REG, cs_reg }
 342 #define ds { OP_REG, ds_reg }
 343 #define fs { OP_REG, fs_reg }
 344 #define gs { OP_REG, gs_reg }
 345
 346 #define MX { OP_MMX, 0 }
 347 #define XM { OP_XMM, 0 }
 348 #define XMScalar { OP_XMM, scalar_mode }
 349 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 350 #define XMM { OP_XMM, xmm_mode }
 351 #define XMxmmq { OP_XMM, xmmq_mode }
 352 #define EM { OP_EM, v_mode }
 353 #define EMS { OP_EM, v_swap_mode }
 354 #define EMd { OP_EM, d_mode }
 355 #define EMx { OP_EM, x_mode }
 356 #define EXw { OP_EX, w_mode }
 357 #define EXd { OP_EX, d_mode }
 358 #define EXdScalar { OP_EX, d_scalar_mode }
 359 #define EXdS { OP_EX, d_swap_mode }
 360 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
 361 #define EXq { OP_EX, q_mode }
 362 #define EXqScalar { OP_EX, q_scalar_mode }
 363 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
 364 #define EXqS { OP_EX, q_swap_mode }
 365 #define EXx { OP_EX, x_mode }
 366 #define EXxS { OP_EX, x_swap_mode }
 367 #define EXxmm { OP_EX, xmm_mode }
 368 #define EXymm { OP_EX, ymm_mode }
 369 #define EXxmmq { OP_EX, xmmq_mode }
 370 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 371 #define EXxmm_mb { OP_EX, xmm_mb_mode }
 372 #define EXxmm_mw { OP_EX, xmm_mw_mode }
 373 #define EXxmm_md { OP_EX, xmm_md_mode }
 374 #define EXxmm_mq { OP_EX, xmm_mq_mode }
 375 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
 376 #define EXxmmdw { OP_EX, xmmdw_mode }
 377 #define EXxmmqd { OP_EX, xmmqd_mode }
 378 #define EXymmq { OP_EX, ymmq_mode }
 379 #define EXVexWdq { OP_EX, vex_w_dq_mode }
 380 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 381 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 382 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 383 #define MS { OP_MS, v_mode }
 384 #define XS { OP_XS, v_mode }
 385 #define EMCq { OP_EMC, q_mode }
 386 #define MXC { OP_MXC, 0 }
 387 #define OPSUF { OP_3DNowSuffix, 0 }
 388 #define CMP { CMP_Fixup, 0 }
 389 #define XMM0 { XMM_Fixup, 0 }
 390 #define FXSAVE { FXSAVE_Fixup, 0 }
 391 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
 392 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
 393
 394 #define Vex { OP_VEX, vex_mode }
 395 #define VexScalar { OP_VEX, vex_scalar_mode }
 396 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 397 #define Vex128 { OP_VEX, vex128_mode }
 398 #define Vex256 { OP_VEX, vex256_mode }
 399 #define VexGdq { OP_VEX, dq_mode }
 400 #define VexI4 { VEXI4_Fixup, 0}
 401 #define EXdVex { OP_EX_Vex, d_mode }
 402 #define EXdVexS { OP_EX_Vex, d_swap_mode }
 403 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
 404 #define EXqVex { OP_EX_Vex, q_mode }
 405 #define EXqVexS { OP_EX_Vex, q_swap_mode }
 406 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
 407 #define EXVexW { OP_EX_VexW, x_mode }
 408 #define EXdVexW { OP_EX_VexW, d_mode }
 409 #define EXqVexW { OP_EX_VexW, q_mode }
 410 #define EXVexImmW { OP_EX_VexImmW, x_mode }
 411 #define XMVex { OP_XMM_Vex, 0 }
 412 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
 413 #define XMVexW { OP_XMM_VexW, 0 }
 414 #define XMVexI4 { OP_REG_VexI4, x_mode }
 415 #define PCLMUL { PCLMUL_Fixup, 0 }
 416 #define VZERO { VZERO_Fixup, 0 }
 417 #define VCMP { VCMP_Fixup, 0 }
 418 #define VPCMP { VPCMP_Fixup, 0 }
 419
 420 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 421 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 422
 423 #define XMask { OP_Mask, mask_mode }
 424 #define MaskG { OP_G, mask_mode }
 425 #define MaskE { OP_E, mask_mode }
 426 #define MaskR { OP_R, mask_mode }
 427 #define MaskVex { OP_VEX, mask_mode }
 428
 429 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 430 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
 431 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 432 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
 433
 434 /* Used handle "rep" prefix for string instructions.  */
 435 #define Xbr { REP_Fixup, eSI_reg }
 436 #define Xvr { REP_Fixup, eSI_reg }
 437 #define Ybr { REP_Fixup, eDI_reg }
 438 #define Yvr { REP_Fixup, eDI_reg }
 439 #define Yzr { REP_Fixup, eDI_reg }
 440 #define indirDXr { REP_Fixup, indir_dx_reg }
 441 #define ALr { REP_Fixup, al_reg }
 442 #define eAXr { REP_Fixup, eAX_reg }
 443
 444 /* Used handle HLE prefix for lockable instructions.  */
 445 #define Ebh1 { HLE_Fixup1, b_mode }
 446 #define Evh1 { HLE_Fixup1, v_mode }
 447 #define Ebh2 { HLE_Fixup2, b_mode }
 448 #define Evh2 { HLE_Fixup2, v_mode }
 449 #define Ebh3 { HLE_Fixup3, b_mode }
 450 #define Evh3 { HLE_Fixup3, v_mode }
 451
 452 #define BND { BND_Fixup, 0 }
 453
 454 #define cond_jump_flag { NULL, cond_jump_mode }
 455 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 456
 457 /* bits in sizeflag */
 458 #define SUFFIX_ALWAYS 4
 459 #define AFLAG 2
 460 #define DFLAG 1
 461
 462 enum
 463 {
 464   /* byte operand */
 465   b_mode = 1,
 466   /* byte operand with operand swapped */
 467   b_swap_mode,
 468   /* byte operand, sign extend like 'T' suffix */
 469   b_T_mode,
 470   /* operand size depends on prefixes */
 471   v_mode,
 472   /* operand size depends on prefixes with operand swapped */
 473   v_swap_mode,
 474   /* word operand */
 475   w_mode,
 476   /* double word operand  */
 477   d_mode,
 478   /* double word operand with operand swapped */
 479   d_swap_mode,
 480   /* quad word operand */
 481   q_mode,
 482   /* quad word operand with operand swapped */
 483   q_swap_mode,
 484   /* ten-byte operand */
 485   t_mode,
 486   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 487      broadcast enabled.  */
 488   x_mode,
 489   /* Similar to x_mode, but with different EVEX mem shifts.  */
 490   evex_x_gscat_mode,
 491   /* Similar to x_mode, but with disabled broadcast.  */
 492   evex_x_nobcst_mode,
 493   /* Similar to x_mode, but with operands swapped and disabled broadcast
 494      in EVEX.  */
 495   x_swap_mode,
 496   /* 16-byte XMM operand */
 497   xmm_mode,
 498   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 499      memory operand (depending on vector length).  Broadcast isn't
 500      allowed.  */
 501   xmmq_mode,
 502   /* Same as xmmq_mode, but broadcast is allowed.  */
 503   evex_half_bcst_xmmq_mode,
 504   /* XMM register or byte memory operand */
 505   xmm_mb_mode,
 506   /* XMM register or word memory operand */
 507   xmm_mw_mode,
 508   /* XMM register or double word memory operand */
 509   xmm_md_mode,
 510   /* XMM register or quad word memory operand */
 511   xmm_mq_mode,
 512   /* XMM register or double/quad word memory operand, depending on
 513      VEX.W.  */
 514   xmm_mdq_mode,
 515   /* 16-byte XMM, word, double word or quad word operand.  */
 516   xmmdw_mode,
 517   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 518   xmmqd_mode,
 519   /* 32-byte YMM operand */
 520   ymm_mode,
 521   /* quad word, ymmword or zmmword memory operand.  */
 522   ymmq_mode,
 523   /* 32-byte YMM or 16-byte word operand */
 524   ymmxmm_mode,
 525   /* d_mode in 32bit, q_mode in 64bit mode.  */
 526   m_mode,
 527   /* pair of v_mode operands */
 528   a_mode,
 529   cond_jump_mode,
 530   loop_jcxz_mode,
 531   v_bnd_mode,
 532   /* operand size depends on REX prefixes.  */
 533   dq_mode,
 534   /* registers like dq_mode, memory like w_mode.  */
 535   dqw_mode,
 536   bnd_mode,
 537   /* 4- or 6-byte pointer operand */
 538   f_mode,
 539   const_1_mode,
 540   /* v_mode for stack-related opcodes.  */
 541   stack_v_mode,
 542   /* non-quad operand size depends on prefixes */
 543   z_mode,
 544   /* 16-byte operand */
 545   o_mode,
 546   /* registers like dq_mode, memory like b_mode.  */
 547   dqb_mode,
 548   /* registers like dq_mode, memory like d_mode.  */
 549   dqd_mode,
 550   /* normal vex mode */
 551   vex_mode,
 552   /* 128bit vex mode */
 553   vex128_mode,
 554   /* 256bit vex mode */
 555   vex256_mode,
 556   /* operand size depends on the VEX.W bit.  */
 557   vex_w_dq_mode,
 558
 559   /* Similar to vex_w_dq_mode, with VSIB dword indices.  */
 560   vex_vsib_d_w_dq_mode,
 561   /* Similar to vex_vsib_d_w_dq_mode, with smaller memory.  */
 562   vex_vsib_d_w_d_mode,
 563   /* Similar to vex_w_dq_mode, with VSIB qword indices.  */
 564   vex_vsib_q_w_dq_mode,
 565   /* Similar to vex_vsib_q_w_dq_mode, with smaller memory.  */
 566   vex_vsib_q_w_d_mode,
 567
 568   /* scalar, ignore vector length.  */
 569   scalar_mode,
 570   /* like d_mode, ignore vector length.  */
 571   d_scalar_mode,
 572   /* like d_swap_mode, ignore vector length.  */
 573   d_scalar_swap_mode,
 574   /* like q_mode, ignore vector length.  */
 575   q_scalar_mode,
 576   /* like q_swap_mode, ignore vector length.  */
 577   q_scalar_swap_mode,
 578   /* like vex_mode, ignore vector length.  */
 579   vex_scalar_mode,
 580   /* like vex_w_dq_mode, ignore vector length.  */
 581   vex_scalar_w_dq_mode,
 582
 583   /* Static rounding.  */
 584   evex_rounding_mode,
 585   /* Supress all exceptions.  */
 586   evex_sae_mode,
 587
 588   /* Mask register operand.  */
 589   mask_mode,
 590
 591   es_reg,
 592   cs_reg,
 593   ss_reg,
 594   ds_reg,
 595   fs_reg,
 596   gs_reg,
 597
 598   eAX_reg,
 599   eCX_reg,
 600   eDX_reg,
 601   eBX_reg,
 602   eSP_reg,
 603   eBP_reg,
 604   eSI_reg,
 605   eDI_reg,
 606
 607   al_reg,
 608   cl_reg,
 609   dl_reg,
 610   bl_reg,
 611   ah_reg,
 612   ch_reg,
 613   dh_reg,
 614   bh_reg,
 615
 616   ax_reg,
 617   cx_reg,
 618   dx_reg,
 619   bx_reg,
 620   sp_reg,
 621   bp_reg,
 622   si_reg,
 623   di_reg,
 624
 625   rAX_reg,
 626   rCX_reg,
 627   rDX_reg,
 628   rBX_reg,
 629   rSP_reg,
 630   rBP_reg,
 631   rSI_reg,
 632   rDI_reg,
 633
 634   z_mode_ax_reg,
 635   indir_dx_reg
 636 };
 637
 638 enum
 639 {
 640   FLOATCODE = 1,
 641   USE_REG_TABLE,
 642   USE_MOD_TABLE,
 643   USE_RM_TABLE,
 644   USE_PREFIX_TABLE,
 645   USE_X86_64_TABLE,
 646   USE_3BYTE_TABLE,
 647   USE_XOP_8F_TABLE,
 648   USE_VEX_C4_TABLE,
 649   USE_VEX_C5_TABLE,
 650   USE_VEX_LEN_TABLE,
 651   USE_VEX_W_TABLE,
 652   USE_EVEX_TABLE
 653 };
 654
 655 #define FLOAT                   NULL, { { NULL, FLOATCODE } }
 656
 657 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }
 658 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 659 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 660 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 661 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 662 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 663 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 664 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 665 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 666 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 667 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 668 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 669 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 670
 671 enum
 672 {
 673   REG_80 = 0,
 674   REG_81,
 675   REG_82,
 676   REG_8F,
 677   REG_C0,
 678   REG_C1,
 679   REG_C6,
 680   REG_C7,
 681   REG_D0,
 682   REG_D1,
 683   REG_D2,
 684   REG_D3,
 685   REG_F6,
 686   REG_F7,
 687   REG_FE,
 688   REG_FF,
 689   REG_0F00,
 690   REG_0F01,
 691   REG_0F0D,
 692   REG_0F18,
 693   REG_0F71,
 694   REG_0F72,
 695   REG_0F73,
 696   REG_0FA6,
 697   REG_0FA7,
 698   REG_0FAE,
 699   REG_0FBA,
 700   REG_0FC7,
 701   REG_VEX_0F71,
 702   REG_VEX_0F72,
 703   REG_VEX_0F73,
 704   REG_VEX_0FAE,
 705   REG_VEX_0F38F3,
 706   REG_XOP_LWPCB,
 707   REG_XOP_LWP,
 708   REG_XOP_TBM_01,
 709   REG_XOP_TBM_02,
 710
 711   REG_EVEX_0F72,
 712   REG_EVEX_0F73,
 713   REG_EVEX_0F38C6,
 714   REG_EVEX_0F38C7
 715 };
 716
 717 enum
 718 {
 719   MOD_8D = 0,
 720   MOD_C6_REG_7,
 721   MOD_C7_REG_7,
 722   MOD_FF_REG_3,
 723   MOD_FF_REG_5,
 724   MOD_0F01_REG_0,
 725   MOD_0F01_REG_1,
 726   MOD_0F01_REG_2,
 727   MOD_0F01_REG_3,
 728   MOD_0F01_REG_7,
 729   MOD_0F12_PREFIX_0,
 730   MOD_0F13,
 731   MOD_0F16_PREFIX_0,
 732   MOD_0F17,
 733   MOD_0F18_REG_0,
 734   MOD_0F18_REG_1,
 735   MOD_0F18_REG_2,
 736   MOD_0F18_REG_3,
 737   MOD_0F18_REG_4,
 738   MOD_0F18_REG_5,
 739   MOD_0F18_REG_6,
 740   MOD_0F18_REG_7,
 741   MOD_0F1A_PREFIX_0,
 742   MOD_0F1B_PREFIX_0,
 743   MOD_0F1B_PREFIX_1,
 744   MOD_0F20,
 745   MOD_0F21,
 746   MOD_0F22,
 747   MOD_0F23,
 748   MOD_0F24,
 749   MOD_0F26,
 750   MOD_0F2B_PREFIX_0,
 751   MOD_0F2B_PREFIX_1,
 752   MOD_0F2B_PREFIX_2,
 753   MOD_0F2B_PREFIX_3,
 754   MOD_0F51,
 755   MOD_0F71_REG_2,
 756   MOD_0F71_REG_4,
 757   MOD_0F71_REG_6,
 758   MOD_0F72_REG_2,
 759   MOD_0F72_REG_4,
 760   MOD_0F72_REG_6,
 761   MOD_0F73_REG_2,
 762   MOD_0F73_REG_3,
 763   MOD_0F73_REG_6,
 764   MOD_0F73_REG_7,
 765   MOD_0FAE_REG_0,
 766   MOD_0FAE_REG_1,
 767   MOD_0FAE_REG_2,
 768   MOD_0FAE_REG_3,
 769   MOD_0FAE_REG_4,
 770   MOD_0FAE_REG_5,
 771   MOD_0FAE_REG_6,
 772   MOD_0FAE_REG_7,
 773   MOD_0FB2,
 774   MOD_0FB4,
 775   MOD_0FB5,
 776   MOD_0FC7_REG_3,
 777   MOD_0FC7_REG_4,
 778   MOD_0FC7_REG_5,
 779   MOD_0FC7_REG_6,
 780   MOD_0FC7_REG_7,
 781   MOD_0FD7,
 782   MOD_0FE7_PREFIX_2,
 783   MOD_0FF0_PREFIX_3,
 784   MOD_0F382A_PREFIX_2,
 785   MOD_62_32BIT,
 786   MOD_C4_32BIT,
 787   MOD_C5_32BIT,
 788   MOD_VEX_0F12_PREFIX_0,
 789   MOD_VEX_0F13,
 790   MOD_VEX_0F16_PREFIX_0,
 791   MOD_VEX_0F17,
 792   MOD_VEX_0F2B,
 793   MOD_VEX_0F50,
 794   MOD_VEX_0F71_REG_2,
 795   MOD_VEX_0F71_REG_4,
 796   MOD_VEX_0F71_REG_6,
 797   MOD_VEX_0F72_REG_2,
 798   MOD_VEX_0F72_REG_4,
 799   MOD_VEX_0F72_REG_6,
 800   MOD_VEX_0F73_REG_2,
 801   MOD_VEX_0F73_REG_3,
 802   MOD_VEX_0F73_REG_6,
 803   MOD_VEX_0F73_REG_7,
 804   MOD_VEX_0FAE_REG_2,
 805   MOD_VEX_0FAE_REG_3,
 806   MOD_VEX_0FD7_PREFIX_2,
 807   MOD_VEX_0FE7_PREFIX_2,
 808   MOD_VEX_0FF0_PREFIX_3,
 809   MOD_VEX_0F381A_PREFIX_2,
 810   MOD_VEX_0F382A_PREFIX_2,
 811   MOD_VEX_0F382C_PREFIX_2,
 812   MOD_VEX_0F382D_PREFIX_2,
 813   MOD_VEX_0F382E_PREFIX_2,
 814   MOD_VEX_0F382F_PREFIX_2,
 815   MOD_VEX_0F385A_PREFIX_2,
 816   MOD_VEX_0F388C_PREFIX_2,
 817   MOD_VEX_0F388E_PREFIX_2,
 818
 819   MOD_EVEX_0F10_PREFIX_1,
 820   MOD_EVEX_0F10_PREFIX_3,
 821   MOD_EVEX_0F11_PREFIX_1,
 822   MOD_EVEX_0F11_PREFIX_3,
 823   MOD_EVEX_0F12_PREFIX_0,
 824   MOD_EVEX_0F16_PREFIX_0,
 825   MOD_EVEX_0F38C6_REG_1,
 826   MOD_EVEX_0F38C6_REG_2,
 827   MOD_EVEX_0F38C6_REG_5,
 828   MOD_EVEX_0F38C6_REG_6,
 829   MOD_EVEX_0F38C7_REG_1,
 830   MOD_EVEX_0F38C7_REG_2,
 831   MOD_EVEX_0F38C7_REG_5,
 832   MOD_EVEX_0F38C7_REG_6
 833 };
 834
 835 enum
 836 {
 837   RM_C6_REG_7 = 0,
 838   RM_C7_REG_7,
 839   RM_0F01_REG_0,
 840   RM_0F01_REG_1,
 841   RM_0F01_REG_2,
 842   RM_0F01_REG_3,
 843   RM_0F01_REG_7,
 844   RM_0FAE_REG_5,
 845   RM_0FAE_REG_6,
 846   RM_0FAE_REG_7
 847 };
 848
 849 enum
 850 {
 851   PREFIX_90 = 0,
 852   PREFIX_0F10,
 853   PREFIX_0F11,
 854   PREFIX_0F12,
 855   PREFIX_0F16,
 856   PREFIX_0F1A,
 857   PREFIX_0F1B,
 858   PREFIX_0F2A,
 859   PREFIX_0F2B,
 860   PREFIX_0F2C,
 861   PREFIX_0F2D,
 862   PREFIX_0F2E,
 863   PREFIX_0F2F,
 864   PREFIX_0F51,
 865   PREFIX_0F52,
 866   PREFIX_0F53,
 867   PREFIX_0F58,
 868   PREFIX_0F59,
 869   PREFIX_0F5A,
 870   PREFIX_0F5B,
 871   PREFIX_0F5C,
 872   PREFIX_0F5D,
 873   PREFIX_0F5E,
 874   PREFIX_0F5F,
 875   PREFIX_0F60,
 876   PREFIX_0F61,
 877   PREFIX_0F62,
 878   PREFIX_0F6C,
 879   PREFIX_0F6D,
 880   PREFIX_0F6F,
 881   PREFIX_0F70,
 882   PREFIX_0F73_REG_3,
 883   PREFIX_0F73_REG_7,
 884   PREFIX_0F78,
 885   PREFIX_0F79,
 886   PREFIX_0F7C,
 887   PREFIX_0F7D,
 888   PREFIX_0F7E,
 889   PREFIX_0F7F,
 890   PREFIX_0FAE_REG_0,
 891   PREFIX_0FAE_REG_1,
 892   PREFIX_0FAE_REG_2,
 893   PREFIX_0FAE_REG_3,
 894   PREFIX_0FAE_REG_7,
 895   PREFIX_0FB8,
 896   PREFIX_0FBC,
 897   PREFIX_0FBD,
 898   PREFIX_0FC2,
 899   PREFIX_0FC3,
 900   PREFIX_0FC7_REG_6,
 901   PREFIX_0FD0,
 902   PREFIX_0FD6,
 903   PREFIX_0FE6,
 904   PREFIX_0FE7,
 905   PREFIX_0FF0,
 906   PREFIX_0FF7,
 907   PREFIX_0F3810,
 908   PREFIX_0F3814,
 909   PREFIX_0F3815,
 910   PREFIX_0F3817,
 911   PREFIX_0F3820,
 912   PREFIX_0F3821,
 913   PREFIX_0F3822,
 914   PREFIX_0F3823,
 915   PREFIX_0F3824,
 916   PREFIX_0F3825,
 917   PREFIX_0F3828,
 918   PREFIX_0F3829,
 919   PREFIX_0F382A,
 920   PREFIX_0F382B,
 921   PREFIX_0F3830,
 922   PREFIX_0F3831,
 923   PREFIX_0F3832,
 924   PREFIX_0F3833,
 925   PREFIX_0F3834,
 926   PREFIX_0F3835,
 927   PREFIX_0F3837,
 928   PREFIX_0F3838,
 929   PREFIX_0F3839,
 930   PREFIX_0F383A,
 931   PREFIX_0F383B,
 932   PREFIX_0F383C,
 933   PREFIX_0F383D,
 934   PREFIX_0F383E,
 935   PREFIX_0F383F,
 936   PREFIX_0F3840,
 937   PREFIX_0F3841,
 938   PREFIX_0F3880,
 939   PREFIX_0F3881,
 940   PREFIX_0F3882,
 941   PREFIX_0F38C8,
 942   PREFIX_0F38C9,
 943   PREFIX_0F38CA,
 944   PREFIX_0F38CB,
 945   PREFIX_0F38CC,
 946   PREFIX_0F38CD,
 947   PREFIX_0F38DB,
 948   PREFIX_0F38DC,
 949   PREFIX_0F38DD,
 950   PREFIX_0F38DE,
 951   PREFIX_0F38DF,
 952   PREFIX_0F38F0,
 953   PREFIX_0F38F1,
 954   PREFIX_0F38F6,
 955   PREFIX_0F3A08,
 956   PREFIX_0F3A09,
 957   PREFIX_0F3A0A,
 958   PREFIX_0F3A0B,
 959   PREFIX_0F3A0C,
 960   PREFIX_0F3A0D,
 961   PREFIX_0F3A0E,
 962   PREFIX_0F3A14,
 963   PREFIX_0F3A15,
 964   PREFIX_0F3A16,
 965   PREFIX_0F3A17,
 966   PREFIX_0F3A20,
 967   PREFIX_0F3A21,
 968   PREFIX_0F3A22,
 969   PREFIX_0F3A40,
 970   PREFIX_0F3A41,
 971   PREFIX_0F3A42,
 972   PREFIX_0F3A44,
 973   PREFIX_0F3A60,
 974   PREFIX_0F3A61,
 975   PREFIX_0F3A62,
 976   PREFIX_0F3A63,
 977   PREFIX_0F3ACC,
 978   PREFIX_0F3ADF,
 979   PREFIX_VEX_0F10,
 980   PREFIX_VEX_0F11,
 981   PREFIX_VEX_0F12,
 982   PREFIX_VEX_0F16,
 983   PREFIX_VEX_0F2A,
 984   PREFIX_VEX_0F2C,
 985   PREFIX_VEX_0F2D,
 986   PREFIX_VEX_0F2E,
 987   PREFIX_VEX_0F2F,
 988   PREFIX_VEX_0F41,
 989   PREFIX_VEX_0F42,
 990   PREFIX_VEX_0F44,
 991   PREFIX_VEX_0F45,
 992   PREFIX_VEX_0F46,
 993   PREFIX_VEX_0F47,
 994   PREFIX_VEX_0F4B,
 995   PREFIX_VEX_0F51,
 996   PREFIX_VEX_0F52,
 997   PREFIX_VEX_0F53,
 998   PREFIX_VEX_0F58,
 999   PREFIX_VEX_0F59,
1000   PREFIX_VEX_0F5A,
1001   PREFIX_VEX_0F5B,
1002   PREFIX_VEX_0F5C,
1003   PREFIX_VEX_0F5D,
1004   PREFIX_VEX_0F5E,
1005   PREFIX_VEX_0F5F,
1006   PREFIX_VEX_0F60,
1007   PREFIX_VEX_0F61,
1008   PREFIX_VEX_0F62,
1009   PREFIX_VEX_0F63,
1010   PREFIX_VEX_0F64,
1011   PREFIX_VEX_0F65,
1012   PREFIX_VEX_0F66,
1013   PREFIX_VEX_0F67,
1014   PREFIX_VEX_0F68,
1015   PREFIX_VEX_0F69,
1016   PREFIX_VEX_0F6A,
1017   PREFIX_VEX_0F6B,
1018   PREFIX_VEX_0F6C,
1019   PREFIX_VEX_0F6D,
1020   PREFIX_VEX_0F6E,
1021   PREFIX_VEX_0F6F,
1022   PREFIX_VEX_0F70,
1023   PREFIX_VEX_0F71_REG_2,
1024   PREFIX_VEX_0F71_REG_4,
1025   PREFIX_VEX_0F71_REG_6,
1026   PREFIX_VEX_0F72_REG_2,
1027   PREFIX_VEX_0F72_REG_4,
1028   PREFIX_VEX_0F72_REG_6,
1029   PREFIX_VEX_0F73_REG_2,
1030   PREFIX_VEX_0F73_REG_3,
1031   PREFIX_VEX_0F73_REG_6,
1032   PREFIX_VEX_0F73_REG_7,
1033   PREFIX_VEX_0F74,
1034   PREFIX_VEX_0F75,
1035   PREFIX_VEX_0F76,
1036   PREFIX_VEX_0F77,
1037   PREFIX_VEX_0F7C,
1038   PREFIX_VEX_0F7D,
1039   PREFIX_VEX_0F7E,
1040   PREFIX_VEX_0F7F,
1041   PREFIX_VEX_0F90,
1042   PREFIX_VEX_0F91,
1043   PREFIX_VEX_0F92,
1044   PREFIX_VEX_0F93,
1045   PREFIX_VEX_0F98,
1046   PREFIX_VEX_0FC2,
1047   PREFIX_VEX_0FC4,
1048   PREFIX_VEX_0FC5,
1049   PREFIX_VEX_0FD0,
1050   PREFIX_VEX_0FD1,
1051   PREFIX_VEX_0FD2,
1052   PREFIX_VEX_0FD3,
1053   PREFIX_VEX_0FD4,
1054   PREFIX_VEX_0FD5,
1055   PREFIX_VEX_0FD6,
1056   PREFIX_VEX_0FD7,
1057   PREFIX_VEX_0FD8,
1058   PREFIX_VEX_0FD9,
1059   PREFIX_VEX_0FDA,
1060   PREFIX_VEX_0FDB,
1061   PREFIX_VEX_0FDC,
1062   PREFIX_VEX_0FDD,
1063   PREFIX_VEX_0FDE,
1064   PREFIX_VEX_0FDF,
1065   PREFIX_VEX_0FE0,
1066   PREFIX_VEX_0FE1,
1067   PREFIX_VEX_0FE2,
1068   PREFIX_VEX_0FE3,
1069   PREFIX_VEX_0FE4,
1070   PREFIX_VEX_0FE5,
1071   PREFIX_VEX_0FE6,
1072   PREFIX_VEX_0FE7,
1073   PREFIX_VEX_0FE8,
1074   PREFIX_VEX_0FE9,
1075   PREFIX_VEX_0FEA,
1076   PREFIX_VEX_0FEB,
1077   PREFIX_VEX_0FEC,
1078   PREFIX_VEX_0FED,
1079   PREFIX_VEX_0FEE,
1080   PREFIX_VEX_0FEF,
1081   PREFIX_VEX_0FF0,
1082   PREFIX_VEX_0FF1,
1083   PREFIX_VEX_0FF2,
1084   PREFIX_VEX_0FF3,
1085   PREFIX_VEX_0FF4,
1086   PREFIX_VEX_0FF5,
1087   PREFIX_VEX_0FF6,
1088   PREFIX_VEX_0FF7,
1089   PREFIX_VEX_0FF8,
1090   PREFIX_VEX_0FF9,
1091   PREFIX_VEX_0FFA,
1092   PREFIX_VEX_0FFB,
1093   PREFIX_VEX_0FFC,
1094   PREFIX_VEX_0FFD,
1095   PREFIX_VEX_0FFE,
1096   PREFIX_VEX_0F3800,
1097   PREFIX_VEX_0F3801,
1098   PREFIX_VEX_0F3802,
1099   PREFIX_VEX_0F3803,
1100   PREFIX_VEX_0F3804,
1101   PREFIX_VEX_0F3805,
1102   PREFIX_VEX_0F3806,
1103   PREFIX_VEX_0F3807,
1104   PREFIX_VEX_0F3808,
1105   PREFIX_VEX_0F3809,
1106   PREFIX_VEX_0F380A,
1107   PREFIX_VEX_0F380B,
1108   PREFIX_VEX_0F380C,
1109   PREFIX_VEX_0F380D,
1110   PREFIX_VEX_0F380E,
1111   PREFIX_VEX_0F380F,
1112   PREFIX_VEX_0F3813,
1113   PREFIX_VEX_0F3816,
1114   PREFIX_VEX_0F3817,
1115   PREFIX_VEX_0F3818,
1116   PREFIX_VEX_0F3819,
1117   PREFIX_VEX_0F381A,
1118   PREFIX_VEX_0F381C,
1119   PREFIX_VEX_0F381D,
1120   PREFIX_VEX_0F381E,
1121   PREFIX_VEX_0F3820,
1122   PREFIX_VEX_0F3821,
1123   PREFIX_VEX_0F3822,
1124   PREFIX_VEX_0F3823,
1125   PREFIX_VEX_0F3824,
1126   PREFIX_VEX_0F3825,
1127   PREFIX_VEX_0F3828,
1128   PREFIX_VEX_0F3829,
1129   PREFIX_VEX_0F382A,
1130   PREFIX_VEX_0F382B,
1131   PREFIX_VEX_0F382C,
1132   PREFIX_VEX_0F382D,
1133   PREFIX_VEX_0F382E,
1134   PREFIX_VEX_0F382F,
1135   PREFIX_VEX_0F3830,
1136   PREFIX_VEX_0F3831,
1137   PREFIX_VEX_0F3832,
1138   PREFIX_VEX_0F3833,
1139   PREFIX_VEX_0F3834,
1140   PREFIX_VEX_0F3835,
1141   PREFIX_VEX_0F3836,
1142   PREFIX_VEX_0F3837,
1143   PREFIX_VEX_0F3838,
1144   PREFIX_VEX_0F3839,
1145   PREFIX_VEX_0F383A,
1146   PREFIX_VEX_0F383B,
1147   PREFIX_VEX_0F383C,
1148   PREFIX_VEX_0F383D,
1149   PREFIX_VEX_0F383E,
1150   PREFIX_VEX_0F383F,
1151   PREFIX_VEX_0F3840,
1152   PREFIX_VEX_0F3841,
1153   PREFIX_VEX_0F3845,
1154   PREFIX_VEX_0F3846,
1155   PREFIX_VEX_0F3847,
1156   PREFIX_VEX_0F3858,
1157   PREFIX_VEX_0F3859,
1158   PREFIX_VEX_0F385A,
1159   PREFIX_VEX_0F3878,
1160   PREFIX_VEX_0F3879,
1161   PREFIX_VEX_0F388C,
1162   PREFIX_VEX_0F388E,
1163   PREFIX_VEX_0F3890,
1164   PREFIX_VEX_0F3891,
1165   PREFIX_VEX_0F3892,
1166   PREFIX_VEX_0F3893,
1167   PREFIX_VEX_0F3896,
1168   PREFIX_VEX_0F3897,
1169   PREFIX_VEX_0F3898,
1170   PREFIX_VEX_0F3899,
1171   PREFIX_VEX_0F389A,
1172   PREFIX_VEX_0F389B,
1173   PREFIX_VEX_0F389C,
1174   PREFIX_VEX_0F389D,
1175   PREFIX_VEX_0F389E,
1176   PREFIX_VEX_0F389F,
1177   PREFIX_VEX_0F38A6,
1178   PREFIX_VEX_0F38A7,
1179   PREFIX_VEX_0F38A8,
1180   PREFIX_VEX_0F38A9,
1181   PREFIX_VEX_0F38AA,
1182   PREFIX_VEX_0F38AB,
1183   PREFIX_VEX_0F38AC,
1184   PREFIX_VEX_0F38AD,
1185   PREFIX_VEX_0F38AE,
1186   PREFIX_VEX_0F38AF,
1187   PREFIX_VEX_0F38B6,
1188   PREFIX_VEX_0F38B7,
1189   PREFIX_VEX_0F38B8,
1190   PREFIX_VEX_0F38B9,
1191   PREFIX_VEX_0F38BA,
1192   PREFIX_VEX_0F38BB,
1193   PREFIX_VEX_0F38BC,
1194   PREFIX_VEX_0F38BD,
1195   PREFIX_VEX_0F38BE,
1196   PREFIX_VEX_0F38BF,
1197   PREFIX_VEX_0F38DB,
1198   PREFIX_VEX_0F38DC,
1199   PREFIX_VEX_0F38DD,
1200   PREFIX_VEX_0F38DE,
1201   PREFIX_VEX_0F38DF,
1202   PREFIX_VEX_0F38F2,
1203   PREFIX_VEX_0F38F3_REG_1,
1204   PREFIX_VEX_0F38F3_REG_2,
1205   PREFIX_VEX_0F38F3_REG_3,
1206   PREFIX_VEX_0F38F5,
1207   PREFIX_VEX_0F38F6,
1208   PREFIX_VEX_0F38F7,
1209   PREFIX_VEX_0F3A00,
1210   PREFIX_VEX_0F3A01,
1211   PREFIX_VEX_0F3A02,
1212   PREFIX_VEX_0F3A04,
1213   PREFIX_VEX_0F3A05,
1214   PREFIX_VEX_0F3A06,
1215   PREFIX_VEX_0F3A08,
1216   PREFIX_VEX_0F3A09,
1217   PREFIX_VEX_0F3A0A,
1218   PREFIX_VEX_0F3A0B,
1219   PREFIX_VEX_0F3A0C,
1220   PREFIX_VEX_0F3A0D,
1221   PREFIX_VEX_0F3A0E,
1222   PREFIX_VEX_0F3A0F,
1223   PREFIX_VEX_0F3A14,
1224   PREFIX_VEX_0F3A15,
1225   PREFIX_VEX_0F3A16,
1226   PREFIX_VEX_0F3A17,
1227   PREFIX_VEX_0F3A18,
1228   PREFIX_VEX_0F3A19,
1229   PREFIX_VEX_0F3A1D,
1230   PREFIX_VEX_0F3A20,
1231   PREFIX_VEX_0F3A21,
1232   PREFIX_VEX_0F3A22,
1233   PREFIX_VEX_0F3A30,
1234   PREFIX_VEX_0F3A32,
1235   PREFIX_VEX_0F3A38,
1236   PREFIX_VEX_0F3A39,
1237   PREFIX_VEX_0F3A40,
1238   PREFIX_VEX_0F3A41,
1239   PREFIX_VEX_0F3A42,
1240   PREFIX_VEX_0F3A44,
1241   PREFIX_VEX_0F3A46,
1242   PREFIX_VEX_0F3A48,
1243   PREFIX_VEX_0F3A49,
1244   PREFIX_VEX_0F3A4A,
1245   PREFIX_VEX_0F3A4B,
1246   PREFIX_VEX_0F3A4C,
1247   PREFIX_VEX_0F3A5C,
1248   PREFIX_VEX_0F3A5D,
1249   PREFIX_VEX_0F3A5E,
1250   PREFIX_VEX_0F3A5F,
1251   PREFIX_VEX_0F3A60,
1252   PREFIX_VEX_0F3A61,
1253   PREFIX_VEX_0F3A62,
1254   PREFIX_VEX_0F3A63,
1255   PREFIX_VEX_0F3A68,
1256   PREFIX_VEX_0F3A69,
1257   PREFIX_VEX_0F3A6A,
1258   PREFIX_VEX_0F3A6B,
1259   PREFIX_VEX_0F3A6C,
1260   PREFIX_VEX_0F3A6D,
1261   PREFIX_VEX_0F3A6E,
1262   PREFIX_VEX_0F3A6F,
1263   PREFIX_VEX_0F3A78,
1264   PREFIX_VEX_0F3A79,
1265   PREFIX_VEX_0F3A7A,
1266   PREFIX_VEX_0F3A7B,
1267   PREFIX_VEX_0F3A7C,
1268   PREFIX_VEX_0F3A7D,
1269   PREFIX_VEX_0F3A7E,
1270   PREFIX_VEX_0F3A7F,
1271   PREFIX_VEX_0F3ADF,
1272   PREFIX_VEX_0F3AF0,
1273
1274   PREFIX_EVEX_0F10,
1275   PREFIX_EVEX_0F11,
1276   PREFIX_EVEX_0F12,
1277   PREFIX_EVEX_0F13,
1278   PREFIX_EVEX_0F14,
1279   PREFIX_EVEX_0F15,
1280   PREFIX_EVEX_0F16,
1281   PREFIX_EVEX_0F17,
1282   PREFIX_EVEX_0F28,
1283   PREFIX_EVEX_0F29,
1284   PREFIX_EVEX_0F2A,
1285   PREFIX_EVEX_0F2B,
1286   PREFIX_EVEX_0F2C,
1287   PREFIX_EVEX_0F2D,
1288   PREFIX_EVEX_0F2E,
1289   PREFIX_EVEX_0F2F,
1290   PREFIX_EVEX_0F51,
1291   PREFIX_EVEX_0F58,
1292   PREFIX_EVEX_0F59,
1293   PREFIX_EVEX_0F5A,
1294   PREFIX_EVEX_0F5B,
1295   PREFIX_EVEX_0F5C,
1296   PREFIX_EVEX_0F5D,
1297   PREFIX_EVEX_0F5E,
1298   PREFIX_EVEX_0F5F,
1299   PREFIX_EVEX_0F62,
1300   PREFIX_EVEX_0F66,
1301   PREFIX_EVEX_0F6A,
1302   PREFIX_EVEX_0F6C,
1303   PREFIX_EVEX_0F6D,
1304   PREFIX_EVEX_0F6E,
1305   PREFIX_EVEX_0F6F,
1306   PREFIX_EVEX_0F70,
1307   PREFIX_EVEX_0F72_REG_0,
1308   PREFIX_EVEX_0F72_REG_1,
1309   PREFIX_EVEX_0F72_REG_2,
1310   PREFIX_EVEX_0F72_REG_4,
1311   PREFIX_EVEX_0F72_REG_6,
1312   PREFIX_EVEX_0F73_REG_2,
1313   PREFIX_EVEX_0F73_REG_6,
1314   PREFIX_EVEX_0F76,
1315   PREFIX_EVEX_0F78,
1316   PREFIX_EVEX_0F79,
1317   PREFIX_EVEX_0F7A,
1318   PREFIX_EVEX_0F7B,
1319   PREFIX_EVEX_0F7E,
1320   PREFIX_EVEX_0F7F,
1321   PREFIX_EVEX_0FC2,
1322   PREFIX_EVEX_0FC6,
1323   PREFIX_EVEX_0FD2,
1324   PREFIX_EVEX_0FD3,
1325   PREFIX_EVEX_0FD4,
1326   PREFIX_EVEX_0FD6,
1327   PREFIX_EVEX_0FDB,
1328   PREFIX_EVEX_0FDF,
1329   PREFIX_EVEX_0FE2,
1330   PREFIX_EVEX_0FE6,
1331   PREFIX_EVEX_0FE7,
1332   PREFIX_EVEX_0FEB,
1333   PREFIX_EVEX_0FEF,
1334   PREFIX_EVEX_0FF2,
1335   PREFIX_EVEX_0FF3,
1336   PREFIX_EVEX_0FF4,
1337   PREFIX_EVEX_0FFA,
1338   PREFIX_EVEX_0FFB,
1339   PREFIX_EVEX_0FFE,
1340   PREFIX_EVEX_0F380C,
1341   PREFIX_EVEX_0F380D,
1342   PREFIX_EVEX_0F3811,
1343   PREFIX_EVEX_0F3812,
1344   PREFIX_EVEX_0F3813,
1345   PREFIX_EVEX_0F3814,
1346   PREFIX_EVEX_0F3815,
1347   PREFIX_EVEX_0F3816,
1348   PREFIX_EVEX_0F3818,
1349   PREFIX_EVEX_0F3819,
1350   PREFIX_EVEX_0F381A,
1351   PREFIX_EVEX_0F381B,
1352   PREFIX_EVEX_0F381E,
1353   PREFIX_EVEX_0F381F,
1354   PREFIX_EVEX_0F3821,
1355   PREFIX_EVEX_0F3822,
1356   PREFIX_EVEX_0F3823,
1357   PREFIX_EVEX_0F3824,
1358   PREFIX_EVEX_0F3825,
1359   PREFIX_EVEX_0F3827,
1360   PREFIX_EVEX_0F3828,
1361   PREFIX_EVEX_0F3829,
1362   PREFIX_EVEX_0F382A,
1363   PREFIX_EVEX_0F382C,
1364   PREFIX_EVEX_0F382D,
1365   PREFIX_EVEX_0F3831,
1366   PREFIX_EVEX_0F3832,
1367   PREFIX_EVEX_0F3833,
1368   PREFIX_EVEX_0F3834,
1369   PREFIX_EVEX_0F3835,
1370   PREFIX_EVEX_0F3836,
1371   PREFIX_EVEX_0F3837,
1372   PREFIX_EVEX_0F3839,
1373   PREFIX_EVEX_0F383A,
1374   PREFIX_EVEX_0F383B,
1375   PREFIX_EVEX_0F383D,
1376   PREFIX_EVEX_0F383F,
1377   PREFIX_EVEX_0F3840,
1378   PREFIX_EVEX_0F3842,
1379   PREFIX_EVEX_0F3843,
1380   PREFIX_EVEX_0F3844,
1381   PREFIX_EVEX_0F3845,
1382   PREFIX_EVEX_0F3846,
1383   PREFIX_EVEX_0F3847,
1384   PREFIX_EVEX_0F384C,
1385   PREFIX_EVEX_0F384D,
1386   PREFIX_EVEX_0F384E,
1387   PREFIX_EVEX_0F384F,
1388   PREFIX_EVEX_0F3858,
1389   PREFIX_EVEX_0F3859,
1390   PREFIX_EVEX_0F385A,
1391   PREFIX_EVEX_0F385B,
1392   PREFIX_EVEX_0F3864,
1393   PREFIX_EVEX_0F3865,
1394   PREFIX_EVEX_0F3876,
1395   PREFIX_EVEX_0F3877,
1396   PREFIX_EVEX_0F387C,
1397   PREFIX_EVEX_0F387E,
1398   PREFIX_EVEX_0F387F,
1399   PREFIX_EVEX_0F3888,
1400   PREFIX_EVEX_0F3889,
1401   PREFIX_EVEX_0F388A,
1402   PREFIX_EVEX_0F388B,
1403   PREFIX_EVEX_0F3890,
1404   PREFIX_EVEX_0F3891,
1405   PREFIX_EVEX_0F3892,
1406   PREFIX_EVEX_0F3893,
1407   PREFIX_EVEX_0F3896,
1408   PREFIX_EVEX_0F3897,
1409   PREFIX_EVEX_0F3898,
1410   PREFIX_EVEX_0F3899,
1411   PREFIX_EVEX_0F389A,
1412   PREFIX_EVEX_0F389B,
1413   PREFIX_EVEX_0F389C,
1414   PREFIX_EVEX_0F389D,
1415   PREFIX_EVEX_0F389E,
1416   PREFIX_EVEX_0F389F,
1417   PREFIX_EVEX_0F38A0,
1418   PREFIX_EVEX_0F38A1,
1419   PREFIX_EVEX_0F38A2,
1420   PREFIX_EVEX_0F38A3,
1421   PREFIX_EVEX_0F38A6,
1422   PREFIX_EVEX_0F38A7,
1423   PREFIX_EVEX_0F38A8,
1424   PREFIX_EVEX_0F38A9,
1425   PREFIX_EVEX_0F38AA,
1426   PREFIX_EVEX_0F38AB,
1427   PREFIX_EVEX_0F38AC,
1428   PREFIX_EVEX_0F38AD,
1429   PREFIX_EVEX_0F38AE,
1430   PREFIX_EVEX_0F38AF,
1431   PREFIX_EVEX_0F38B6,
1432   PREFIX_EVEX_0F38B7,
1433   PREFIX_EVEX_0F38B8,
1434   PREFIX_EVEX_0F38B9,
1435   PREFIX_EVEX_0F38BA,
1436   PREFIX_EVEX_0F38BB,
1437   PREFIX_EVEX_0F38BC,
1438   PREFIX_EVEX_0F38BD,
1439   PREFIX_EVEX_0F38BE,
1440   PREFIX_EVEX_0F38BF,
1441   PREFIX_EVEX_0F38C4,
1442   PREFIX_EVEX_0F38C6_REG_1,
1443   PREFIX_EVEX_0F38C6_REG_2,
1444   PREFIX_EVEX_0F38C6_REG_5,
1445   PREFIX_EVEX_0F38C6_REG_6,
1446   PREFIX_EVEX_0F38C7_REG_1,
1447   PREFIX_EVEX_0F38C7_REG_2,
1448   PREFIX_EVEX_0F38C7_REG_5,
1449   PREFIX_EVEX_0F38C7_REG_6,
1450   PREFIX_EVEX_0F38C8,
1451   PREFIX_EVEX_0F38CA,
1452   PREFIX_EVEX_0F38CB,
1453   PREFIX_EVEX_0F38CC,
1454   PREFIX_EVEX_0F38CD,
1455
1456   PREFIX_EVEX_0F3A00,
1457   PREFIX_EVEX_0F3A01,
1458   PREFIX_EVEX_0F3A03,
1459   PREFIX_EVEX_0F3A04,
1460   PREFIX_EVEX_0F3A05,
1461   PREFIX_EVEX_0F3A08,
1462   PREFIX_EVEX_0F3A09,
1463   PREFIX_EVEX_0F3A0A,
1464   PREFIX_EVEX_0F3A0B,
1465   PREFIX_EVEX_0F3A17,
1466   PREFIX_EVEX_0F3A18,
1467   PREFIX_EVEX_0F3A19,
1468   PREFIX_EVEX_0F3A1A,
1469   PREFIX_EVEX_0F3A1B,
1470   PREFIX_EVEX_0F3A1D,
1471   PREFIX_EVEX_0F3A1E,
1472   PREFIX_EVEX_0F3A1F,
1473   PREFIX_EVEX_0F3A21,
1474   PREFIX_EVEX_0F3A23,
1475   PREFIX_EVEX_0F3A25,
1476   PREFIX_EVEX_0F3A26,
1477   PREFIX_EVEX_0F3A27,
1478   PREFIX_EVEX_0F3A38,
1479   PREFIX_EVEX_0F3A39,
1480   PREFIX_EVEX_0F3A3A,
1481   PREFIX_EVEX_0F3A3B,
1482   PREFIX_EVEX_0F3A43,
1483   PREFIX_EVEX_0F3A54,
1484   PREFIX_EVEX_0F3A55,
1485 };
1486
1487 enum
1488 {
1489   X86_64_06 = 0,
1490   X86_64_07,
1491   X86_64_0D,
1492   X86_64_16,
1493   X86_64_17,
1494   X86_64_1E,
1495   X86_64_1F,
1496   X86_64_27,
1497   X86_64_2F,
1498   X86_64_37,
1499   X86_64_3F,
1500   X86_64_60,
1501   X86_64_61,
1502   X86_64_62,
1503   X86_64_63,
1504   X86_64_6D,
1505   X86_64_6F,
1506   X86_64_9A,
1507   X86_64_C4,
1508   X86_64_C5,
1509   X86_64_CE,
1510   X86_64_D4,
1511   X86_64_D5,
1512   X86_64_EA,
1513   X86_64_0F01_REG_0,
1514   X86_64_0F01_REG_1,
1515   X86_64_0F01_REG_2,
1516   X86_64_0F01_REG_3
1517 };
1518
1519 enum
1520 {
1521   THREE_BYTE_0F38 = 0,
1522   THREE_BYTE_0F3A,
1523   THREE_BYTE_0F7A
1524 };
1525
1526 enum
1527 {
1528   XOP_08 = 0,
1529   XOP_09,
1530   XOP_0A
1531 };
1532
1533 enum
1534 {
1535   VEX_0F = 0,
1536   VEX_0F38,
1537   VEX_0F3A
1538 };
1539
1540 enum
1541 {
1542   EVEX_0F = 0,
1543   EVEX_0F38,
1544   EVEX_0F3A
1545 };
1546
1547 enum
1548 {
1549   VEX_LEN_0F10_P_1 = 0,
1550   VEX_LEN_0F10_P_3,
1551   VEX_LEN_0F11_P_1,
1552   VEX_LEN_0F11_P_3,
1553   VEX_LEN_0F12_P_0_M_0,
1554   VEX_LEN_0F12_P_0_M_1,
1555   VEX_LEN_0F12_P_2,
1556   VEX_LEN_0F13_M_0,
1557   VEX_LEN_0F16_P_0_M_0,
1558   VEX_LEN_0F16_P_0_M_1,
1559   VEX_LEN_0F16_P_2,
1560   VEX_LEN_0F17_M_0,
1561   VEX_LEN_0F2A_P_1,
1562   VEX_LEN_0F2A_P_3,
1563   VEX_LEN_0F2C_P_1,
1564   VEX_LEN_0F2C_P_3,
1565   VEX_LEN_0F2D_P_1,
1566   VEX_LEN_0F2D_P_3,
1567   VEX_LEN_0F2E_P_0,
1568   VEX_LEN_0F2E_P_2,
1569   VEX_LEN_0F2F_P_0,
1570   VEX_LEN_0F2F_P_2,
1571   VEX_LEN_0F41_P_0,
1572   VEX_LEN_0F42_P_0,
1573   VEX_LEN_0F44_P_0,
1574   VEX_LEN_0F45_P_0,
1575   VEX_LEN_0F46_P_0,
1576   VEX_LEN_0F47_P_0,
1577   VEX_LEN_0F4B_P_2,
1578   VEX_LEN_0F51_P_1,
1579   VEX_LEN_0F51_P_3,
1580   VEX_LEN_0F52_P_1,
1581   VEX_LEN_0F53_P_1,
1582   VEX_LEN_0F58_P_1,
1583   VEX_LEN_0F58_P_3,
1584   VEX_LEN_0F59_P_1,
1585   VEX_LEN_0F59_P_3,
1586   VEX_LEN_0F5A_P_1,
1587   VEX_LEN_0F5A_P_3,
1588   VEX_LEN_0F5C_P_1,
1589   VEX_LEN_0F5C_P_3,
1590   VEX_LEN_0F5D_P_1,
1591   VEX_LEN_0F5D_P_3,
1592   VEX_LEN_0F5E_P_1,
1593   VEX_LEN_0F5E_P_3,
1594   VEX_LEN_0F5F_P_1,
1595   VEX_LEN_0F5F_P_3,
1596   VEX_LEN_0F6E_P_2,
1597   VEX_LEN_0F7E_P_1,
1598   VEX_LEN_0F7E_P_2,
1599   VEX_LEN_0F90_P_0,
1600   VEX_LEN_0F91_P_0,
1601   VEX_LEN_0F92_P_0,
1602   VEX_LEN_0F93_P_0,
1603   VEX_LEN_0F98_P_0,
1604   VEX_LEN_0FAE_R_2_M_0,
1605   VEX_LEN_0FAE_R_3_M_0,
1606   VEX_LEN_0FC2_P_1,
1607   VEX_LEN_0FC2_P_3,
1608   VEX_LEN_0FC4_P_2,
1609   VEX_LEN_0FC5_P_2,
1610   VEX_LEN_0FD6_P_2,
1611   VEX_LEN_0FF7_P_2,
1612   VEX_LEN_0F3816_P_2,
1613   VEX_LEN_0F3819_P_2,
1614   VEX_LEN_0F381A_P_2_M_0,
1615   VEX_LEN_0F3836_P_2,
1616   VEX_LEN_0F3841_P_2,
1617   VEX_LEN_0F385A_P_2_M_0,
1618   VEX_LEN_0F38DB_P_2,
1619   VEX_LEN_0F38DC_P_2,
1620   VEX_LEN_0F38DD_P_2,
1621   VEX_LEN_0F38DE_P_2,
1622   VEX_LEN_0F38DF_P_2,
1623   VEX_LEN_0F38F2_P_0,
1624   VEX_LEN_0F38F3_R_1_P_0,
1625   VEX_LEN_0F38F3_R_2_P_0,
1626   VEX_LEN_0F38F3_R_3_P_0,
1627   VEX_LEN_0F38F5_P_0,
1628   VEX_LEN_0F38F5_P_1,
1629   VEX_LEN_0F38F5_P_3,
1630   VEX_LEN_0F38F6_P_3,
1631   VEX_LEN_0F38F7_P_0,
1632   VEX_LEN_0F38F7_P_1,
1633   VEX_LEN_0F38F7_P_2,
1634   VEX_LEN_0F38F7_P_3,
1635   VEX_LEN_0F3A00_P_2,
1636   VEX_LEN_0F3A01_P_2,
1637   VEX_LEN_0F3A06_P_2,
1638   VEX_LEN_0F3A0A_P_2,
1639   VEX_LEN_0F3A0B_P_2,
1640   VEX_LEN_0F3A14_P_2,
1641   VEX_LEN_0F3A15_P_2,
1642   VEX_LEN_0F3A16_P_2,
1643   VEX_LEN_0F3A17_P_2,
1644   VEX_LEN_0F3A18_P_2,
1645   VEX_LEN_0F3A19_P_2,
1646   VEX_LEN_0F3A20_P_2,
1647   VEX_LEN_0F3A21_P_2,
1648   VEX_LEN_0F3A22_P_2,
1649   VEX_LEN_0F3A30_P_2,
1650   VEX_LEN_0F3A32_P_2,
1651   VEX_LEN_0F3A38_P_2,
1652   VEX_LEN_0F3A39_P_2,
1653   VEX_LEN_0F3A41_P_2,
1654   VEX_LEN_0F3A44_P_2,
1655   VEX_LEN_0F3A46_P_2,
1656   VEX_LEN_0F3A60_P_2,
1657   VEX_LEN_0F3A61_P_2,
1658   VEX_LEN_0F3A62_P_2,
1659   VEX_LEN_0F3A63_P_2,
1660   VEX_LEN_0F3A6A_P_2,
1661   VEX_LEN_0F3A6B_P_2,
1662   VEX_LEN_0F3A6E_P_2,
1663   VEX_LEN_0F3A6F_P_2,
1664   VEX_LEN_0F3A7A_P_2,
1665   VEX_LEN_0F3A7B_P_2,
1666   VEX_LEN_0F3A7E_P_2,
1667   VEX_LEN_0F3A7F_P_2,
1668   VEX_LEN_0F3ADF_P_2,
1669   VEX_LEN_0F3AF0_P_3,
1670   VEX_LEN_0FXOP_08_CC,
1671   VEX_LEN_0FXOP_08_CD,
1672   VEX_LEN_0FXOP_08_CE,
1673   VEX_LEN_0FXOP_08_CF,
1674   VEX_LEN_0FXOP_08_EC,
1675   VEX_LEN_0FXOP_08_ED,
1676   VEX_LEN_0FXOP_08_EE,
1677   VEX_LEN_0FXOP_08_EF,
1678   VEX_LEN_0FXOP_09_80,
1679   VEX_LEN_0FXOP_09_81
1680 };
1681
1682 enum
1683 {
1684   VEX_W_0F10_P_0 = 0,
1685   VEX_W_0F10_P_1,
1686   VEX_W_0F10_P_2,
1687   VEX_W_0F10_P_3,
1688   VEX_W_0F11_P_0,
1689   VEX_W_0F11_P_1,
1690   VEX_W_0F11_P_2,
1691   VEX_W_0F11_P_3,
1692   VEX_W_0F12_P_0_M_0,
1693   VEX_W_0F12_P_0_M_1,
1694   VEX_W_0F12_P_1,
1695   VEX_W_0F12_P_2,
1696   VEX_W_0F12_P_3,
1697   VEX_W_0F13_M_0,
1698   VEX_W_0F14,
1699   VEX_W_0F15,
1700   VEX_W_0F16_P_0_M_0,
1701   VEX_W_0F16_P_0_M_1,
1702   VEX_W_0F16_P_1,
1703   VEX_W_0F16_P_2,
1704   VEX_W_0F17_M_0,
1705   VEX_W_0F28,
1706   VEX_W_0F29,
1707   VEX_W_0F2B_M_0,
1708   VEX_W_0F2E_P_0,
1709   VEX_W_0F2E_P_2,
1710   VEX_W_0F2F_P_0,
1711   VEX_W_0F2F_P_2,
1712   VEX_W_0F41_P_0_LEN_1,
1713   VEX_W_0F42_P_0_LEN_1,
1714   VEX_W_0F44_P_0_LEN_0,
1715   VEX_W_0F45_P_0_LEN_1,
1716   VEX_W_0F46_P_0_LEN_1,
1717   VEX_W_0F47_P_0_LEN_1,
1718   VEX_W_0F4B_P_2_LEN_1,
1719   VEX_W_0F50_M_0,
1720   VEX_W_0F51_P_0,
1721   VEX_W_0F51_P_1,
1722   VEX_W_0F51_P_2,
1723   VEX_W_0F51_P_3,
1724   VEX_W_0F52_P_0,
1725   VEX_W_0F52_P_1,
1726   VEX_W_0F53_P_0,
1727   VEX_W_0F53_P_1,
1728   VEX_W_0F58_P_0,
1729   VEX_W_0F58_P_1,
1730   VEX_W_0F58_P_2,
1731   VEX_W_0F58_P_3,
1732   VEX_W_0F59_P_0,
1733   VEX_W_0F59_P_1,
1734   VEX_W_0F59_P_2,
1735   VEX_W_0F59_P_3,
1736   VEX_W_0F5A_P_0,
1737   VEX_W_0F5A_P_1,
1738   VEX_W_0F5A_P_3,
1739   VEX_W_0F5B_P_0,
1740   VEX_W_0F5B_P_1,
1741   VEX_W_0F5B_P_2,
1742   VEX_W_0F5C_P_0,
1743   VEX_W_0F5C_P_1,
1744   VEX_W_0F5C_P_2,
1745   VEX_W_0F5C_P_3,
1746   VEX_W_0F5D_P_0,
1747   VEX_W_0F5D_P_1,
1748   VEX_W_0F5D_P_2,
1749   VEX_W_0F5D_P_3,
1750   VEX_W_0F5E_P_0,
1751   VEX_W_0F5E_P_1,
1752   VEX_W_0F5E_P_2,
1753   VEX_W_0F5E_P_3,
1754   VEX_W_0F5F_P_0,
1755   VEX_W_0F5F_P_1,
1756   VEX_W_0F5F_P_2,
1757   VEX_W_0F5F_P_3,
1758   VEX_W_0F60_P_2,
1759   VEX_W_0F61_P_2,
1760   VEX_W_0F62_P_2,
1761   VEX_W_0F63_P_2,
1762   VEX_W_0F64_P_2,
1763   VEX_W_0F65_P_2,
1764   VEX_W_0F66_P_2,
1765   VEX_W_0F67_P_2,
1766   VEX_W_0F68_P_2,
1767   VEX_W_0F69_P_2,
1768   VEX_W_0F6A_P_2,
1769   VEX_W_0F6B_P_2,
1770   VEX_W_0F6C_P_2,
1771   VEX_W_0F6D_P_2,
1772   VEX_W_0F6F_P_1,
1773   VEX_W_0F6F_P_2,
1774   VEX_W_0F70_P_1,
1775   VEX_W_0F70_P_2,
1776   VEX_W_0F70_P_3,
1777   VEX_W_0F71_R_2_P_2,
1778   VEX_W_0F71_R_4_P_2,
1779   VEX_W_0F71_R_6_P_2,
1780   VEX_W_0F72_R_2_P_2,
1781   VEX_W_0F72_R_4_P_2,
1782   VEX_W_0F72_R_6_P_2,
1783   VEX_W_0F73_R_2_P_2,
1784   VEX_W_0F73_R_3_P_2,
1785   VEX_W_0F73_R_6_P_2,
1786   VEX_W_0F73_R_7_P_2,
1787   VEX_W_0F74_P_2,
1788   VEX_W_0F75_P_2,
1789   VEX_W_0F76_P_2,
1790   VEX_W_0F77_P_0,
1791   VEX_W_0F7C_P_2,
1792   VEX_W_0F7C_P_3,
1793   VEX_W_0F7D_P_2,
1794   VEX_W_0F7D_P_3,
1795   VEX_W_0F7E_P_1,
1796   VEX_W_0F7F_P_1,
1797   VEX_W_0F7F_P_2,
1798   VEX_W_0F90_P_0_LEN_0,
1799   VEX_W_0F91_P_0_LEN_0,
1800   VEX_W_0F92_P_0_LEN_0,
1801   VEX_W_0F93_P_0_LEN_0,
1802   VEX_W_0F98_P_0_LEN_0,
1803   VEX_W_0FAE_R_2_M_0,
1804   VEX_W_0FAE_R_3_M_0,
1805   VEX_W_0FC2_P_0,
1806   VEX_W_0FC2_P_1,
1807   VEX_W_0FC2_P_2,
1808   VEX_W_0FC2_P_3,
1809   VEX_W_0FC4_P_2,
1810   VEX_W_0FC5_P_2,
1811   VEX_W_0FD0_P_2,
1812   VEX_W_0FD0_P_3,
1813   VEX_W_0FD1_P_2,
1814   VEX_W_0FD2_P_2,
1815   VEX_W_0FD3_P_2,
1816   VEX_W_0FD4_P_2,
1817   VEX_W_0FD5_P_2,
1818   VEX_W_0FD6_P_2,
1819   VEX_W_0FD7_P_2_M_1,
1820   VEX_W_0FD8_P_2,
1821   VEX_W_0FD9_P_2,
1822   VEX_W_0FDA_P_2,
1823   VEX_W_0FDB_P_2,
1824   VEX_W_0FDC_P_2,
1825   VEX_W_0FDD_P_2,
1826   VEX_W_0FDE_P_2,
1827   VEX_W_0FDF_P_2,
1828   VEX_W_0FE0_P_2,
1829   VEX_W_0FE1_P_2,
1830   VEX_W_0FE2_P_2,
1831   VEX_W_0FE3_P_2,
1832   VEX_W_0FE4_P_2,
1833   VEX_W_0FE5_P_2,
1834   VEX_W_0FE6_P_1,
1835   VEX_W_0FE6_P_2,
1836   VEX_W_0FE6_P_3,
1837   VEX_W_0FE7_P_2_M_0,
1838   VEX_W_0FE8_P_2,
1839   VEX_W_0FE9_P_2,
1840   VEX_W_0FEA_P_2,
1841   VEX_W_0FEB_P_2,
1842   VEX_W_0FEC_P_2,
1843   VEX_W_0FED_P_2,
1844   VEX_W_0FEE_P_2,
1845   VEX_W_0FEF_P_2,
1846   VEX_W_0FF0_P_3_M_0,
1847   VEX_W_0FF1_P_2,
1848   VEX_W_0FF2_P_2,
1849   VEX_W_0FF3_P_2,
1850   VEX_W_0FF4_P_2,
1851   VEX_W_0FF5_P_2,
1852   VEX_W_0FF6_P_2,
1853   VEX_W_0FF7_P_2,
1854   VEX_W_0FF8_P_2,
1855   VEX_W_0FF9_P_2,
1856   VEX_W_0FFA_P_2,
1857   VEX_W_0FFB_P_2,
1858   VEX_W_0FFC_P_2,
1859   VEX_W_0FFD_P_2,
1860   VEX_W_0FFE_P_2,
1861   VEX_W_0F3800_P_2,
1862   VEX_W_0F3801_P_2,
1863   VEX_W_0F3802_P_2,
1864   VEX_W_0F3803_P_2,
1865   VEX_W_0F3804_P_2,
1866   VEX_W_0F3805_P_2,
1867   VEX_W_0F3806_P_2,
1868   VEX_W_0F3807_P_2,
1869   VEX_W_0F3808_P_2,
1870   VEX_W_0F3809_P_2,
1871   VEX_W_0F380A_P_2,
1872   VEX_W_0F380B_P_2,
1873   VEX_W_0F380C_P_2,
1874   VEX_W_0F380D_P_2,
1875   VEX_W_0F380E_P_2,
1876   VEX_W_0F380F_P_2,
1877   VEX_W_0F3816_P_2,
1878   VEX_W_0F3817_P_2,
1879   VEX_W_0F3818_P_2,
1880   VEX_W_0F3819_P_2,
1881   VEX_W_0F381A_P_2_M_0,
1882   VEX_W_0F381C_P_2,
1883   VEX_W_0F381D_P_2,
1884   VEX_W_0F381E_P_2,
1885   VEX_W_0F3820_P_2,
1886   VEX_W_0F3821_P_2,
1887   VEX_W_0F3822_P_2,
1888   VEX_W_0F3823_P_2,
1889   VEX_W_0F3824_P_2,
1890   VEX_W_0F3825_P_2,
1891   VEX_W_0F3828_P_2,
1892   VEX_W_0F3829_P_2,
1893   VEX_W_0F382A_P_2_M_0,
1894   VEX_W_0F382B_P_2,
1895   VEX_W_0F382C_P_2_M_0,
1896   VEX_W_0F382D_P_2_M_0,
1897   VEX_W_0F382E_P_2_M_0,
1898   VEX_W_0F382F_P_2_M_0,
1899   VEX_W_0F3830_P_2,
1900   VEX_W_0F3831_P_2,
1901   VEX_W_0F3832_P_2,
1902   VEX_W_0F3833_P_2,
1903   VEX_W_0F3834_P_2,
1904   VEX_W_0F3835_P_2,
1905   VEX_W_0F3836_P_2,
1906   VEX_W_0F3837_P_2,
1907   VEX_W_0F3838_P_2,
1908   VEX_W_0F3839_P_2,
1909   VEX_W_0F383A_P_2,
1910   VEX_W_0F383B_P_2,
1911   VEX_W_0F383C_P_2,
1912   VEX_W_0F383D_P_2,
1913   VEX_W_0F383E_P_2,
1914   VEX_W_0F383F_P_2,
1915   VEX_W_0F3840_P_2,
1916   VEX_W_0F3841_P_2,
1917   VEX_W_0F3846_P_2,
1918   VEX_W_0F3858_P_2,
1919   VEX_W_0F3859_P_2,
1920   VEX_W_0F385A_P_2_M_0,
1921   VEX_W_0F3878_P_2,
1922   VEX_W_0F3879_P_2,
1923   VEX_W_0F38DB_P_2,
1924   VEX_W_0F38DC_P_2,
1925   VEX_W_0F38DD_P_2,
1926   VEX_W_0F38DE_P_2,
1927   VEX_W_0F38DF_P_2,
1928   VEX_W_0F3A00_P_2,
1929   VEX_W_0F3A01_P_2,
1930   VEX_W_0F3A02_P_2,
1931   VEX_W_0F3A04_P_2,
1932   VEX_W_0F3A05_P_2,
1933   VEX_W_0F3A06_P_2,
1934   VEX_W_0F3A08_P_2,
1935   VEX_W_0F3A09_P_2,
1936   VEX_W_0F3A0A_P_2,
1937   VEX_W_0F3A0B_P_2,
1938   VEX_W_0F3A0C_P_2,
1939   VEX_W_0F3A0D_P_2,
1940   VEX_W_0F3A0E_P_2,
1941   VEX_W_0F3A0F_P_2,
1942   VEX_W_0F3A14_P_2,
1943   VEX_W_0F3A15_P_2,
1944   VEX_W_0F3A18_P_2,
1945   VEX_W_0F3A19_P_2,
1946   VEX_W_0F3A20_P_2,
1947   VEX_W_0F3A21_P_2,
1948   VEX_W_0F3A30_P_2_LEN_0,
1949   VEX_W_0F3A32_P_2_LEN_0,
1950   VEX_W_0F3A38_P_2,
1951   VEX_W_0F3A39_P_2,
1952   VEX_W_0F3A40_P_2,
1953   VEX_W_0F3A41_P_2,
1954   VEX_W_0F3A42_P_2,
1955   VEX_W_0F3A44_P_2,
1956   VEX_W_0F3A46_P_2,
1957   VEX_W_0F3A48_P_2,
1958   VEX_W_0F3A49_P_2,
1959   VEX_W_0F3A4A_P_2,
1960   VEX_W_0F3A4B_P_2,
1961   VEX_W_0F3A4C_P_2,
1962   VEX_W_0F3A60_P_2,
1963   VEX_W_0F3A61_P_2,
1964   VEX_W_0F3A62_P_2,
1965   VEX_W_0F3A63_P_2,
1966   VEX_W_0F3ADF_P_2,
1967
1968   EVEX_W_0F10_P_0,
1969   EVEX_W_0F10_P_1_M_0,
1970   EVEX_W_0F10_P_1_M_1,
1971   EVEX_W_0F10_P_2,
1972   EVEX_W_0F10_P_3_M_0,
1973   EVEX_W_0F10_P_3_M_1,
1974   EVEX_W_0F11_P_0,
1975   EVEX_W_0F11_P_1_M_0,
1976   EVEX_W_0F11_P_1_M_1,
1977   EVEX_W_0F11_P_2,
1978   EVEX_W_0F11_P_3_M_0,
1979   EVEX_W_0F11_P_3_M_1,
1980   EVEX_W_0F12_P_0_M_0,
1981   EVEX_W_0F12_P_0_M_1,
1982   EVEX_W_0F12_P_1,
1983   EVEX_W_0F12_P_2,
1984   EVEX_W_0F12_P_3,
1985   EVEX_W_0F13_P_0,
1986   EVEX_W_0F13_P_2,
1987   EVEX_W_0F14_P_0,
1988   EVEX_W_0F14_P_2,
1989   EVEX_W_0F15_P_0,
1990   EVEX_W_0F15_P_2,
1991   EVEX_W_0F16_P_0_M_0,
1992   EVEX_W_0F16_P_0_M_1,
1993   EVEX_W_0F16_P_1,
1994   EVEX_W_0F16_P_2,
1995   EVEX_W_0F17_P_0,
1996   EVEX_W_0F17_P_2,
1997   EVEX_W_0F28_P_0,
1998   EVEX_W_0F28_P_2,
1999   EVEX_W_0F29_P_0,
2000   EVEX_W_0F29_P_2,
2001   EVEX_W_0F2A_P_1,
2002   EVEX_W_0F2A_P_3,
2003   EVEX_W_0F2B_P_0,
2004   EVEX_W_0F2B_P_2,
2005   EVEX_W_0F2E_P_0,
2006   EVEX_W_0F2E_P_2,
2007   EVEX_W_0F2F_P_0,
2008   EVEX_W_0F2F_P_2,
2009   EVEX_W_0F51_P_0,
2010   EVEX_W_0F51_P_1,
2011   EVEX_W_0F51_P_2,
2012   EVEX_W_0F51_P_3,
2013   EVEX_W_0F58_P_0,
2014   EVEX_W_0F58_P_1,
2015   EVEX_W_0F58_P_2,
2016   EVEX_W_0F58_P_3,
2017   EVEX_W_0F59_P_0,
2018   EVEX_W_0F59_P_1,
2019   EVEX_W_0F59_P_2,
2020   EVEX_W_0F59_P_3,
2021   EVEX_W_0F5A_P_0,
2022   EVEX_W_0F5A_P_1,
2023   EVEX_W_0F5A_P_2,
2024   EVEX_W_0F5A_P_3,
2025   EVEX_W_0F5B_P_0,
2026   EVEX_W_0F5B_P_1,
2027   EVEX_W_0F5B_P_2,
2028   EVEX_W_0F5C_P_0,
2029   EVEX_W_0F5C_P_1,
2030   EVEX_W_0F5C_P_2,
2031   EVEX_W_0F5C_P_3,
2032   EVEX_W_0F5D_P_0,
2033   EVEX_W_0F5D_P_1,
2034   EVEX_W_0F5D_P_2,
2035   EVEX_W_0F5D_P_3,
2036   EVEX_W_0F5E_P_0,
2037   EVEX_W_0F5E_P_1,
2038   EVEX_W_0F5E_P_2,
2039   EVEX_W_0F5E_P_3,
2040   EVEX_W_0F5F_P_0,
2041   EVEX_W_0F5F_P_1,
2042   EVEX_W_0F5F_P_2,
2043   EVEX_W_0F5F_P_3,
2044   EVEX_W_0F62_P_2,
2045   EVEX_W_0F66_P_2,
2046   EVEX_W_0F6A_P_2,
2047   EVEX_W_0F6C_P_2,
2048   EVEX_W_0F6D_P_2,
2049   EVEX_W_0F6E_P_2,
2050   EVEX_W_0F6F_P_1,
2051   EVEX_W_0F6F_P_2,
2052   EVEX_W_0F70_P_2,
2053   EVEX_W_0F72_R_2_P_2,
2054   EVEX_W_0F72_R_6_P_2,
2055   EVEX_W_0F73_R_2_P_2,
2056   EVEX_W_0F73_R_6_P_2,
2057   EVEX_W_0F76_P_2,
2058   EVEX_W_0F78_P_0,
2059   EVEX_W_0F79_P_0,
2060   EVEX_W_0F7A_P_1,
2061   EVEX_W_0F7A_P_3,
2062   EVEX_W_0F7B_P_1,
2063   EVEX_W_0F7B_P_3,
2064   EVEX_W_0F7E_P_1,
2065   EVEX_W_0F7E_P_2,
2066   EVEX_W_0F7F_P_1,
2067   EVEX_W_0F7F_P_2,
2068   EVEX_W_0FC2_P_0,
2069   EVEX_W_0FC2_P_1,
2070   EVEX_W_0FC2_P_2,
2071   EVEX_W_0FC2_P_3,
2072   EVEX_W_0FC6_P_0,
2073   EVEX_W_0FC6_P_2,
2074   EVEX_W_0FD2_P_2,
2075   EVEX_W_0FD3_P_2,
2076   EVEX_W_0FD4_P_2,
2077   EVEX_W_0FD6_P_2,
2078   EVEX_W_0FE6_P_1,
2079   EVEX_W_0FE6_P_2,
2080   EVEX_W_0FE6_P_3,
2081   EVEX_W_0FE7_P_2,
2082   EVEX_W_0FF2_P_2,
2083   EVEX_W_0FF3_P_2,
2084   EVEX_W_0FF4_P_2,
2085   EVEX_W_0FFA_P_2,
2086   EVEX_W_0FFB_P_2,
2087   EVEX_W_0FFE_P_2,
2088   EVEX_W_0F380C_P_2,
2089   EVEX_W_0F380D_P_2,
2090   EVEX_W_0F3811_P_1,
2091   EVEX_W_0F3812_P_1,
2092   EVEX_W_0F3813_P_1,
2093   EVEX_W_0F3813_P_2,
2094   EVEX_W_0F3814_P_1,
2095   EVEX_W_0F3815_P_1,
2096   EVEX_W_0F3818_P_2,
2097   EVEX_W_0F3819_P_2,
2098   EVEX_W_0F381A_P_2,
2099   EVEX_W_0F381B_P_2,
2100   EVEX_W_0F381E_P_2,
2101   EVEX_W_0F381F_P_2,
2102   EVEX_W_0F3821_P_1,
2103   EVEX_W_0F3822_P_1,
2104   EVEX_W_0F3823_P_1,
2105   EVEX_W_0F3824_P_1,
2106   EVEX_W_0F3825_P_1,
2107   EVEX_W_0F3825_P_2,
2108   EVEX_W_0F3828_P_2,
2109   EVEX_W_0F3829_P_2,
2110   EVEX_W_0F382A_P_1,
2111   EVEX_W_0F382A_P_2,
2112   EVEX_W_0F3831_P_1,
2113   EVEX_W_0F3832_P_1,
2114   EVEX_W_0F3833_P_1,
2115   EVEX_W_0F3834_P_1,
2116   EVEX_W_0F3835_P_1,
2117   EVEX_W_0F3835_P_2,
2118   EVEX_W_0F3837_P_2,
2119   EVEX_W_0F383A_P_1,
2120   EVEX_W_0F3840_P_2,
2121   EVEX_W_0F3858_P_2,
2122   EVEX_W_0F3859_P_2,
2123   EVEX_W_0F385A_P_2,
2124   EVEX_W_0F385B_P_2,
2125   EVEX_W_0F3891_P_2,
2126   EVEX_W_0F3893_P_2,
2127   EVEX_W_0F38A1_P_2,
2128   EVEX_W_0F38A3_P_2,
2129   EVEX_W_0F38C7_R_1_P_2,
2130   EVEX_W_0F38C7_R_2_P_2,
2131   EVEX_W_0F38C7_R_5_P_2,
2132   EVEX_W_0F38C7_R_6_P_2,
2133
2134   EVEX_W_0F3A00_P_2,
2135   EVEX_W_0F3A01_P_2,
2136   EVEX_W_0F3A04_P_2,
2137   EVEX_W_0F3A05_P_2,
2138   EVEX_W_0F3A08_P_2,
2139   EVEX_W_0F3A09_P_2,
2140   EVEX_W_0F3A0A_P_2,
2141   EVEX_W_0F3A0B_P_2,
2142   EVEX_W_0F3A18_P_2,
2143   EVEX_W_0F3A19_P_2,
2144   EVEX_W_0F3A1A_P_2,
2145   EVEX_W_0F3A1B_P_2,
2146   EVEX_W_0F3A1D_P_2,
2147   EVEX_W_0F3A21_P_2,
2148   EVEX_W_0F3A23_P_2,
2149   EVEX_W_0F3A38_P_2,
2150   EVEX_W_0F3A39_P_2,
2151   EVEX_W_0F3A3A_P_2,
2152   EVEX_W_0F3A3B_P_2,
2153   EVEX_W_0F3A43_P_2,
2154 };
2155
2156 typedef void (*op_rtn) (int bytemode, int sizeflag);
2157
2158 struct dis386 {
2159   const char *name;
2160   struct
2161     {
2162       op_rtn rtn;
2163       int bytemode;
2164     } op[MAX_OPERANDS];
2165 };
2166
2167 /* Upper case letters in the instruction names here are macros.
2168    'A' => print 'b' if no register operands or suffix_always is true
2169    'B' => print 'b' if suffix_always is true
2170    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2171           size prefix
2172    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2173           suffix_always is true
2174    'E' => print 'e' if 32-bit form of jcxz
2175    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2176    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2177    'H' => print ",pt" or ",pn" branch hint
2178    'I' => honor following macro letter even in Intel mode (implemented only
2179           for some of the macro letters)
2180    'J' => print 'l'
2181    'K' => print 'd' or 'q' if rex prefix is present.
2182    'L' => print 'l' if suffix_always is true
2183    'M' => print 'r' if intel_mnemonic is false.
2184    'N' => print 'n' if instruction has no wait "prefix"
2185    'O' => print 'd' or 'o' (or 'q' in Intel mode)
2186    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2187           or suffix_always is true.  print 'q' if rex prefix is present.
2188    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2189           is true
2190    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2191    'S' => print 'w', 'l' or 'q' if suffix_always is true
2192    'T' => print 'q' in 64bit mode and behave as 'P' otherwise
2193    'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
2194    'V' => print 'q' in 64bit mode and behave as 'S' otherwise
2195    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2196    'X' => print 's', 'd' depending on data16 prefix (for XMM)
2197    'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
2198           suffix_always is true.
2199    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2200    '!' => change condition from true to false or from false to true.
2201    '%' => add 1 upper case letter to the macro.
2202
2203    2 upper case letter macros:
2204    "XY" => print 'x' or 'y' if no register operands or suffix_always
2205            is true.
2206    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2207    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2208            or suffix_always is true
2209    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2210    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2211    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2212    "LW" => print 'd', 'q' depending on the VEX.W bit
2213
2214    Many of the above letters print nothing in Intel mode.  See "putop"
2215    for the details.
2216
2217    Braces '{' and '}', and vertical bars '|', indicate alternative
2218    mnemonic strings for AT&T and Intel.  */
2219
2220 static const struct dis386 dis386[] = {
2221   /* 00 */
2222   { "addB",             { Ebh1, Gb } },
2223   { "addS",             { Evh1, Gv } },
2224   { "addB",             { Gb, EbS } },
2225   { "addS",             { Gv, EvS } },
2226   { "addB",             { AL, Ib } },
2227   { "addS",             { eAX, Iv } },
2228   { X86_64_TABLE (X86_64_06) },
2229   { X86_64_TABLE (X86_64_07) },
2230   /* 08 */
2231   { "orB",              { Ebh1, Gb } },
2232   { "orS",              { Evh1, Gv } },
2233   { "orB",              { Gb, EbS } },
2234   { "orS",              { Gv, EvS } },
2235   { "orB",              { AL, Ib } },
2236   { "orS",              { eAX, Iv } },
2237   { X86_64_TABLE (X86_64_0D) },
2238   { Bad_Opcode },       /* 0x0f extended opcode escape */
2239   /* 10 */
2240   { "adcB",             { Ebh1, Gb } },
2241   { "adcS",             { Evh1, Gv } },
2242   { "adcB",             { Gb, EbS } },
2243   { "adcS",             { Gv, EvS } },
2244   { "adcB",             { AL, Ib } },
2245   { "adcS",             { eAX, Iv } },
2246   { X86_64_TABLE (X86_64_16) },
2247   { X86_64_TABLE (X86_64_17) },
2248   /* 18 */
2249   { "sbbB",             { Ebh1, Gb } },
2250   { "sbbS",             { Evh1, Gv } },
2251   { "sbbB",             { Gb, EbS } },
2252   { "sbbS",             { Gv, EvS } },
2253   { "sbbB",             { AL, Ib } },
2254   { "sbbS",             { eAX, Iv } },
2255   { X86_64_TABLE (X86_64_1E) },
2256   { X86_64_TABLE (X86_64_1F) },
2257   /* 20 */
2258   { "andB",             { Ebh1, Gb } },
2259   { "andS",             { Evh1, Gv } },
2260   { "andB",             { Gb, EbS } },
2261   { "andS",             { Gv, EvS } },
2262   { "andB",             { AL, Ib } },
2263   { "andS",             { eAX, Iv } },
2264   { Bad_Opcode },       /* SEG ES prefix */
2265   { X86_64_TABLE (X86_64_27) },
2266   /* 28 */
2267   { "subB",             { Ebh1, Gb } },
2268   { "subS",             { Evh1, Gv } },
2269   { "subB",             { Gb, EbS } },
2270   { "subS",             { Gv, EvS } },
2271   { "subB",             { AL, Ib } },
2272   { "subS",             { eAX, Iv } },
2273   { Bad_Opcode },       /* SEG CS prefix */
2274   { X86_64_TABLE (X86_64_2F) },
2275   /* 30 */
2276   { "xorB",             { Ebh1, Gb } },
2277   { "xorS",             { Evh1, Gv } },
2278   { "xorB",             { Gb, EbS } },
2279   { "xorS",             { Gv, EvS } },
2280   { "xorB",             { AL, Ib } },
2281   { "xorS",             { eAX, Iv } },
2282   { Bad_Opcode },       /* SEG SS prefix */
2283   { X86_64_TABLE (X86_64_37) },
2284   /* 38 */
2285   { "cmpB",             { Eb, Gb } },
2286   { "cmpS",             { Ev, Gv } },
2287   { "cmpB",             { Gb, EbS } },
2288   { "cmpS",             { Gv, EvS } },
2289   { "cmpB",             { AL, Ib } },
2290   { "cmpS",             { eAX, Iv } },
2291   { Bad_Opcode },       /* SEG DS prefix */
2292   { X86_64_TABLE (X86_64_3F) },
2293   /* 40 */
2294   { "inc{S|}",          { RMeAX } },
2295   { "inc{S|}",          { RMeCX } },
2296   { "inc{S|}",          { RMeDX } },
2297   { "inc{S|}",          { RMeBX } },
2298   { "inc{S|}",          { RMeSP } },
2299   { "inc{S|}",          { RMeBP } },
2300   { "inc{S|}",          { RMeSI } },
2301   { "inc{S|}",          { RMeDI } },
2302   /* 48 */
2303   { "dec{S|}",          { RMeAX } },
2304   { "dec{S|}",          { RMeCX } },
2305   { "dec{S|}",          { RMeDX } },
2306   { "dec{S|}",          { RMeBX } },
2307   { "dec{S|}",          { RMeSP } },
2308   { "dec{S|}",          { RMeBP } },
2309   { "dec{S|}",          { RMeSI } },
2310   { "dec{S|}",          { RMeDI } },
2311   /* 50 */
2312   { "pushV",            { RMrAX } },
2313   { "pushV",            { RMrCX } },
2314   { "pushV",            { RMrDX } },
2315   { "pushV",            { RMrBX } },
2316   { "pushV",            { RMrSP } },
2317   { "pushV",            { RMrBP } },
2318   { "pushV",            { RMrSI } },
2319   { "pushV",            { RMrDI } },
2320   /* 58 */
2321   { "popV",             { RMrAX } },
2322   { "popV",             { RMrCX } },
2323   { "popV",             { RMrDX } },
2324   { "popV",             { RMrBX } },
2325   { "popV",             { RMrSP } },
2326   { "popV",             { RMrBP } },
2327   { "popV",             { RMrSI } },
2328   { "popV",             { RMrDI } },
2329   /* 60 */
2330   { X86_64_TABLE (X86_64_60) },
2331   { X86_64_TABLE (X86_64_61) },
2332   { X86_64_TABLE (X86_64_62) },
2333   { X86_64_TABLE (X86_64_63) },
2334   { Bad_Opcode },       /* seg fs */
2335   { Bad_Opcode },       /* seg gs */
2336   { Bad_Opcode },       /* op size prefix */
2337   { Bad_Opcode },       /* adr size prefix */
2338   /* 68 */
2339   { "pushT",            { sIv } },
2340   { "imulS",            { Gv, Ev, Iv } },
2341   { "pushT",            { sIbT } },
2342   { "imulS",            { Gv, Ev, sIb } },
2343   { "ins{b|}",          { Ybr, indirDX } },
2344   { X86_64_TABLE (X86_64_6D) },
2345   { "outs{b|}",         { indirDXr, Xb } },
2346   { X86_64_TABLE (X86_64_6F) },
2347   /* 70 */
2348   { "joH",              { Jb, BND, cond_jump_flag } },
2349   { "jnoH",             { Jb, BND, cond_jump_flag } },
2350   { "jbH",              { Jb, BND, cond_jump_flag } },
2351   { "jaeH",             { Jb, BND, cond_jump_flag } },
2352   { "jeH",              { Jb, BND, cond_jump_flag } },
2353   { "jneH",             { Jb, BND, cond_jump_flag } },
2354   { "jbeH",             { Jb, BND, cond_jump_flag } },
2355   { "jaH",              { Jb, BND, cond_jump_flag } },
2356   /* 78 */
2357   { "jsH",              { Jb, BND, cond_jump_flag } },
2358   { "jnsH",             { Jb, BND, cond_jump_flag } },
2359   { "jpH",              { Jb, BND, cond_jump_flag } },
2360   { "jnpH",             { Jb, BND, cond_jump_flag } },
2361   { "jlH",              { Jb, BND, cond_jump_flag } },
2362   { "jgeH",             { Jb, BND, cond_jump_flag } },
2363   { "jleH",             { Jb, BND, cond_jump_flag } },
2364   { "jgH",              { Jb, BND, cond_jump_flag } },
2365   /* 80 */
2366   { REG_TABLE (REG_80) },
2367   { REG_TABLE (REG_81) },
2368   { Bad_Opcode },
2369   { REG_TABLE (REG_82) },
2370   { "testB",            { Eb, Gb } },
2371   { "testS",            { Ev, Gv } },
2372   { "xchgB",            { Ebh2, Gb } },
2373   { "xchgS",            { Evh2, Gv } },
2374   /* 88 */
2375   { "movB",             { Ebh3, Gb } },
2376   { "movS",             { Evh3, Gv } },
2377   { "movB",             { Gb, EbS } },
2378   { "movS",             { Gv, EvS } },
2379   { "movD",             { Sv, Sw } },
2380   { MOD_TABLE (MOD_8D) },
2381   { "movD",             { Sw, Sv } },
2382   { REG_TABLE (REG_8F) },
2383   /* 90 */
2384   { PREFIX_TABLE (PREFIX_90) },
2385   { "xchgS",            { RMeCX, eAX } },
2386   { "xchgS",            { RMeDX, eAX } },
2387   { "xchgS",            { RMeBX, eAX } },
2388   { "xchgS",            { RMeSP, eAX } },
2389   { "xchgS",            { RMeBP, eAX } },
2390   { "xchgS",            { RMeSI, eAX } },
2391   { "xchgS",            { RMeDI, eAX } },
2392   /* 98 */
2393   { "cW{t|}R",          { XX } },
2394   { "cR{t|}O",          { XX } },
2395   { X86_64_TABLE (X86_64_9A) },
2396   { Bad_Opcode },       /* fwait */
2397   { "pushfT",           { XX } },
2398   { "popfT",            { XX } },
2399   { "sahf",             { XX } },
2400   { "lahf",             { XX } },
2401   /* a0 */
2402   { "mov%LB",           { AL, Ob } },
2403   { "mov%LS",           { eAX, Ov } },
2404   { "mov%LB",           { Ob, AL } },
2405   { "mov%LS",           { Ov, eAX } },
2406   { "movs{b|}",         { Ybr, Xb } },
2407   { "movs{R|}",         { Yvr, Xv } },
2408   { "cmps{b|}",         { Xb, Yb } },
2409   { "cmps{R|}",         { Xv, Yv } },
2410   /* a8 */
2411   { "testB",            { AL, Ib } },
2412   { "testS",            { eAX, Iv } },
2413   { "stosB",            { Ybr, AL } },
2414   { "stosS",            { Yvr, eAX } },
2415   { "lodsB",            { ALr, Xb } },
2416   { "lodsS",            { eAXr, Xv } },
2417   { "scasB",            { AL, Yb } },
2418   { "scasS",            { eAX, Yv } },
2419   /* b0 */
2420   { "movB",             { RMAL, Ib } },
2421   { "movB",             { RMCL, Ib } },
2422   { "movB",             { RMDL, Ib } },
2423   { "movB",             { RMBL, Ib } },
2424   { "movB",             { RMAH, Ib } },
2425   { "movB",             { RMCH, Ib } },
2426   { "movB",             { RMDH, Ib } },
2427   { "movB",             { RMBH, Ib } },
2428   /* b8 */
2429   { "mov%LV",           { RMeAX, Iv64 } },
2430   { "mov%LV",           { RMeCX, Iv64 } },
2431   { "mov%LV",           { RMeDX, Iv64 } },
2432   { "mov%LV",           { RMeBX, Iv64 } },
2433   { "mov%LV",           { RMeSP, Iv64 } },
2434   { "mov%LV",           { RMeBP, Iv64 } },
2435   { "mov%LV",           { RMeSI, Iv64 } },
2436   { "mov%LV",           { RMeDI, Iv64 } },
2437   /* c0 */
2438   { REG_TABLE (REG_C0) },
2439   { REG_TABLE (REG_C1) },
2440   { "retT",             { Iw, BND } },
2441   { "retT",             { BND } },
2442   { X86_64_TABLE (X86_64_C4) },
2443   { X86_64_TABLE (X86_64_C5) },
2444   { REG_TABLE (REG_C6) },
2445   { REG_TABLE (REG_C7) },
2446   /* c8 */
2447   { "enterT",           { Iw, Ib } },
2448   { "leaveT",           { XX } },
2449   { "Jret{|f}P",        { Iw } },
2450   { "Jret{|f}P",        { XX } },
2451   { "int3",             { XX } },
2452   { "int",              { Ib } },
2453   { X86_64_TABLE (X86_64_CE) },
2454   { "iretP",            { XX } },
2455   /* d0 */
2456   { REG_TABLE (REG_D0) },
2457   { REG_TABLE (REG_D1) },
2458   { REG_TABLE (REG_D2) },
2459   { REG_TABLE (REG_D3) },
2460   { X86_64_TABLE (X86_64_D4) },
2461   { X86_64_TABLE (X86_64_D5) },
2462   { Bad_Opcode },
2463   { "xlat",             { DSBX } },
2464   /* d8 */
2465   { FLOAT },
2466   { FLOAT },
2467   { FLOAT },
2468   { FLOAT },
2469   { FLOAT },
2470   { FLOAT },
2471   { FLOAT },
2472   { FLOAT },
2473   /* e0 */
2474   { "loopneFH",         { Jb, XX, loop_jcxz_flag } },
2475   { "loopeFH",          { Jb, XX, loop_jcxz_flag } },
2476   { "loopFH",           { Jb, XX, loop_jcxz_flag } },
2477   { "jEcxzH",           { Jb, XX, loop_jcxz_flag } },
2478   { "inB",              { AL, Ib } },
2479   { "inG",              { zAX, Ib } },
2480   { "outB",             { Ib, AL } },
2481   { "outG",             { Ib, zAX } },
2482   /* e8 */
2483   { "callT",            { Jv, BND } },
2484   { "jmpT",             { Jv, BND } },
2485   { X86_64_TABLE (X86_64_EA) },
2486   { "jmp",              { Jb, BND } },
2487   { "inB",              { AL, indirDX } },
2488   { "inG",              { zAX, indirDX } },
2489   { "outB",             { indirDX, AL } },
2490   { "outG",             { indirDX, zAX } },
2491   /* f0 */
2492   { Bad_Opcode },       /* lock prefix */
2493   { "icebp",            { XX } },
2494   { Bad_Opcode },       /* repne */
2495   { Bad_Opcode },       /* repz */
2496   { "hlt",              { XX } },
2497   { "cmc",              { XX } },
2498   { REG_TABLE (REG_F6) },
2499   { REG_TABLE (REG_F7) },
2500   /* f8 */
2501   { "clc",              { XX } },
2502   { "stc",              { XX } },
2503   { "cli",              { XX } },
2504   { "sti",              { XX } },
2505   { "cld",              { XX } },
2506   { "std",              { XX } },
2507   { REG_TABLE (REG_FE) },
2508   { REG_TABLE (REG_FF) },
2509 };
2510
2511 static const struct dis386 dis386_twobyte[] = {
2512   /* 00 */
2513   { REG_TABLE (REG_0F00 ) },
2514   { REG_TABLE (REG_0F01 ) },
2515   { "larS",             { Gv, Ew } },
2516   { "lslS",             { Gv, Ew } },
2517   { Bad_Opcode },
2518   { "syscall",          { XX } },
2519   { "clts",             { XX } },
2520   { "sysretP",          { XX } },
2521   /* 08 */
2522   { "invd",             { XX } },
2523   { "wbinvd",           { XX } },
2524   { Bad_Opcode },
2525   { "ud2",              { XX } },
2526   { Bad_Opcode },
2527   { REG_TABLE (REG_0F0D) },
2528   { "femms",            { XX } },
2529   { "",                 { MX, EM, OPSUF } }, /* See OP_3DNowSuffix.  */
2530   /* 10 */
2531   { PREFIX_TABLE (PREFIX_0F10) },
2532   { PREFIX_TABLE (PREFIX_0F11) },
2533   { PREFIX_TABLE (PREFIX_0F12) },
2534   { MOD_TABLE (MOD_0F13) },
2535   { "unpcklpX",         { XM, EXx } },
2536   { "unpckhpX",         { XM, EXx } },
2537   { PREFIX_TABLE (PREFIX_0F16) },
2538   { MOD_TABLE (MOD_0F17) },
2539   /* 18 */
2540   { REG_TABLE (REG_0F18) },
2541   { "nopQ",             { Ev } },
2542   { PREFIX_TABLE (PREFIX_0F1A) },
2543   { PREFIX_TABLE (PREFIX_0F1B) },
2544   { "nopQ",             { Ev } },
2545   { "nopQ",             { Ev } },
2546   { "nopQ",             { Ev } },
2547   { "nopQ",             { Ev } },
2548   /* 20 */
2549   { MOD_TABLE (MOD_0F20) },
2550   { MOD_TABLE (MOD_0F21) },
2551   { MOD_TABLE (MOD_0F22) },
2552   { MOD_TABLE (MOD_0F23) },
2553   { MOD_TABLE (MOD_0F24) },
2554   { Bad_Opcode },
2555   { MOD_TABLE (MOD_0F26) },
2556   { Bad_Opcode },
2557   /* 28 */
2558   { "movapX",           { XM, EXx } },
2559   { "movapX",           { EXxS, XM } },
2560   { PREFIX_TABLE (PREFIX_0F2A) },
2561   { PREFIX_TABLE (PREFIX_0F2B) },
2562   { PREFIX_TABLE (PREFIX_0F2C) },
2563   { PREFIX_TABLE (PREFIX_0F2D) },
2564   { PREFIX_TABLE (PREFIX_0F2E) },
2565   { PREFIX_TABLE (PREFIX_0F2F) },
2566   /* 30 */
2567   { "wrmsr",            { XX } },
2568   { "rdtsc",            { XX } },
2569   { "rdmsr",            { XX } },
2570   { "rdpmc",            { XX } },
2571   { "sysenter",         { XX } },
2572   { "sysexit",          { XX } },
2573   { Bad_Opcode },
2574   { "getsec",           { XX } },
2575   /* 38 */
2576   { THREE_BYTE_TABLE (THREE_BYTE_0F38) },
2577   { Bad_Opcode },
2578   { THREE_BYTE_TABLE (THREE_BYTE_0F3A) },
2579   { Bad_Opcode },
2580   { Bad_Opcode },
2581   { Bad_Opcode },
2582   { Bad_Opcode },
2583   { Bad_Opcode },
2584   /* 40 */
2585   { "cmovoS",           { Gv, Ev } },
2586   { "cmovnoS",          { Gv, Ev } },
2587   { "cmovbS",           { Gv, Ev } },
2588   { "cmovaeS",          { Gv, Ev } },
2589   { "cmoveS",           { Gv, Ev } },
2590   { "cmovneS",          { Gv, Ev } },
2591   { "cmovbeS",          { Gv, Ev } },
2592   { "cmovaS",           { Gv, Ev } },
2593   /* 48 */
2594   { "cmovsS",           { Gv, Ev } },
2595   { "cmovnsS",          { Gv, Ev } },
2596   { "cmovpS",           { Gv, Ev } },
2597   { "cmovnpS",          { Gv, Ev } },
2598   { "cmovlS",           { Gv, Ev } },
2599   { "cmovgeS",          { Gv, Ev } },
2600   { "cmovleS",          { Gv, Ev } },
2601   { "cmovgS",           { Gv, Ev } },
2602   /* 50 */
2603   { MOD_TABLE (MOD_0F51) },
2604   { PREFIX_TABLE (PREFIX_0F51) },
2605   { PREFIX_TABLE (PREFIX_0F52) },
2606   { PREFIX_TABLE (PREFIX_0F53) },
2607   { "andpX",            { XM, EXx } },
2608   { "andnpX",           { XM, EXx } },
2609   { "orpX",             { XM, EXx } },
2610   { "xorpX",            { XM, EXx } },
2611   /* 58 */
2612   { PREFIX_TABLE (PREFIX_0F58) },
2613   { PREFIX_TABLE (PREFIX_0F59) },
2614   { PREFIX_TABLE (PREFIX_0F5A) },
2615   { PREFIX_TABLE (PREFIX_0F5B) },
2616   { PREFIX_TABLE (PREFIX_0F5C) },
2617   { PREFIX_TABLE (PREFIX_0F5D) },
2618   { PREFIX_TABLE (PREFIX_0F5E) },
2619   { PREFIX_TABLE (PREFIX_0F5F) },
2620   /* 60 */
2621   { PREFIX_TABLE (PREFIX_0F60) },
2622   { PREFIX_TABLE (PREFIX_0F61) },
2623   { PREFIX_TABLE (PREFIX_0F62) },
2624   { "packsswb",         { MX, EM } },
2625   { "pcmpgtb",          { MX, EM } },
2626   { "pcmpgtw",          { MX, EM } },
2627   { "pcmpgtd",          { MX, EM } },
2628   { "packuswb",         { MX, EM } },
2629   /* 68 */
2630   { "punpckhbw",        { MX, EM } },
2631   { "punpckhwd",        { MX, EM } },
2632   { "punpckhdq",        { MX, EM } },
2633   { "packssdw",         { MX, EM } },
2634   { PREFIX_TABLE (PREFIX_0F6C) },
2635   { PREFIX_TABLE (PREFIX_0F6D) },
2636   { "movK",             { MX, Edq } },
2637   { PREFIX_TABLE (PREFIX_0F6F) },
2638   /* 70 */
2639   { PREFIX_TABLE (PREFIX_0F70) },
2640   { REG_TABLE (REG_0F71) },
2641   { REG_TABLE (REG_0F72) },
2642   { REG_TABLE (REG_0F73) },
2643   { "pcmpeqb",          { MX, EM } },
2644   { "pcmpeqw",          { MX, EM } },
2645   { "pcmpeqd",          { MX, EM } },
2646   { "emms",             { XX } },
2647   /* 78 */
2648   { PREFIX_TABLE (PREFIX_0F78) },
2649   { PREFIX_TABLE (PREFIX_0F79) },
2650   { THREE_BYTE_TABLE (THREE_BYTE_0F7A) },
2651   { Bad_Opcode },
2652   { PREFIX_TABLE (PREFIX_0F7C) },
2653   { PREFIX_TABLE (PREFIX_0F7D) },
2654   { PREFIX_TABLE (PREFIX_0F7E) },
2655   { PREFIX_TABLE (PREFIX_0F7F) },
2656   /* 80 */
2657   { "joH",              { Jv, BND, cond_jump_flag } },
2658   { "jnoH",             { Jv, BND, cond_jump_flag } },
2659   { "jbH",              { Jv, BND, cond_jump_flag } },
2660   { "jaeH",             { Jv, BND, cond_jump_flag } },
2661   { "jeH",              { Jv, BND, cond_jump_flag } },
2662   { "jneH",             { Jv, BND, cond_jump_flag } },
2663   { "jbeH",             { Jv, BND, cond_jump_flag } },
2664   { "jaH",              { Jv, BND, cond_jump_flag } },
2665   /* 88 */
2666   { "jsH",              { Jv, BND, cond_jump_flag } },
2667   { "jnsH",             { Jv, BND, cond_jump_flag } },
2668   { "jpH",              { Jv, BND, cond_jump_flag } },
2669   { "jnpH",             { Jv, BND, cond_jump_flag } },
2670   { "jlH",              { Jv, BND, cond_jump_flag } },
2671   { "jgeH",             { Jv, BND, cond_jump_flag } },
2672   { "jleH",             { Jv, BND, cond_jump_flag } },
2673   { "jgH",              { Jv, BND, cond_jump_flag } },
2674   /* 90 */
2675   { "seto",             { Eb } },
2676   { "setno",            { Eb } },
2677   { "setb",             { Eb } },
2678   { "setae",            { Eb } },
2679   { "sete",             { Eb } },
2680   { "setne",            { Eb } },
2681   { "setbe",            { Eb } },
2682   { "seta",             { Eb } },
2683   /* 98 */
2684   { "sets",             { Eb } },
2685   { "setns",            { Eb } },
2686   { "setp",             { Eb } },
2687   { "setnp",            { Eb } },
2688   { "setl",             { Eb } },
2689   { "setge",            { Eb } },
2690   { "setle",            { Eb } },
2691   { "setg",             { Eb } },
2692   /* a0 */
2693   { "pushT",            { fs } },
2694   { "popT",             { fs } },
2695   { "cpuid",            { XX } },
2696   { "btS",              { Ev, Gv } },
2697   { "shldS",            { Ev, Gv, Ib } },
2698   { "shldS",            { Ev, Gv, CL } },
2699   { REG_TABLE (REG_0FA6) },
2700   { REG_TABLE (REG_0FA7) },
2701   /* a8 */
2702   { "pushT",            { gs } },
2703   { "popT",             { gs } },
2704   { "rsm",              { XX } },
2705   { "btsS",             { Evh1, Gv } },
2706   { "shrdS",            { Ev, Gv, Ib } },
2707   { "shrdS",            { Ev, Gv, CL } },
2708   { REG_TABLE (REG_0FAE) },
2709   { "imulS",            { Gv, Ev } },
2710   /* b0 */
2711   { "cmpxchgB",         { Ebh1, Gb } },
2712   { "cmpxchgS",         { Evh1, Gv } },
2713   { MOD_TABLE (MOD_0FB2) },
2714   { "btrS",             { Evh1, Gv } },
2715   { MOD_TABLE (MOD_0FB4) },
2716   { MOD_TABLE (MOD_0FB5) },
2717   { "movz{bR|x}",       { Gv, Eb } },
2718   { "movz{wR|x}",       { Gv, Ew } }, /* yes, there really is movzww ! */
2719   /* b8 */
2720   { PREFIX_TABLE (PREFIX_0FB8) },
2721   { "ud1",              { XX } },
2722   { REG_TABLE (REG_0FBA) },
2723   { "btcS",             { Evh1, Gv } },
2724   { PREFIX_TABLE (PREFIX_0FBC) },
2725   { PREFIX_TABLE (PREFIX_0FBD) },
2726   { "movs{bR|x}",       { Gv, Eb } },
2727   { "movs{wR|x}",       { Gv, Ew } }, /* yes, there really is movsww ! */
2728   /* c0 */
2729   { "xaddB",            { Ebh1, Gb } },
2730   { "xaddS",            { Evh1, Gv } },
2731   { PREFIX_TABLE (PREFIX_0FC2) },
2732   { PREFIX_TABLE (PREFIX_0FC3) },
2733   { "pinsrw",           { MX, Edqw, Ib } },
2734   { "pextrw",           { Gdq, MS, Ib } },
2735   { "shufpX",           { XM, EXx, Ib } },
2736   { REG_TABLE (REG_0FC7) },
2737   /* c8 */
2738   { "bswap",            { RMeAX } },
2739   { "bswap",            { RMeCX } },
2740   { "bswap",            { RMeDX } },
2741   { "bswap",            { RMeBX } },
2742   { "bswap",            { RMeSP } },
2743   { "bswap",            { RMeBP } },
2744   { "bswap",            { RMeSI } },
2745   { "bswap",            { RMeDI } },
2746   /* d0 */
2747   { PREFIX_TABLE (PREFIX_0FD0) },
2748   { "psrlw",            { MX, EM } },
2749   { "psrld",            { MX, EM } },
2750   { "psrlq",            { MX, EM } },
2751   { "paddq",            { MX, EM } },
2752   { "pmullw",           { MX, EM } },
2753   { PREFIX_TABLE (PREFIX_0FD6) },
2754   { MOD_TABLE (MOD_0FD7) },
2755   /* d8 */
2756   { "psubusb",          { MX, EM } },
2757   { "psubusw",          { MX, EM } },
2758   { "pminub",           { MX, EM } },
2759   { "pand",             { MX, EM } },
2760   { "paddusb",          { MX, EM } },
2761   { "paddusw",          { MX, EM } },
2762   { "pmaxub",           { MX, EM } },
2763   { "pandn",            { MX, EM } },
2764   /* e0 */
2765   { "pavgb",            { MX, EM } },
2766   { "psraw",            { MX, EM } },
2767   { "psrad",            { MX, EM } },
2768   { "pavgw",            { MX, EM } },
2769   { "pmulhuw",          { MX, EM } },
2770   { "pmulhw",           { MX, EM } },
2771   { PREFIX_TABLE (PREFIX_0FE6) },
2772   { PREFIX_TABLE (PREFIX_0FE7) },
2773   /* e8 */
2774   { "psubsb",           { MX, EM } },
2775   { "psubsw",           { MX, EM } },
2776   { "pminsw",           { MX, EM } },
2777   { "por",              { MX, EM } },
2778   { "paddsb",           { MX, EM } },
2779   { "paddsw",           { MX, EM } },
2780   { "pmaxsw",           { MX, EM } },
2781   { "pxor",             { MX, EM } },
2782   /* f0 */
2783   { PREFIX_TABLE (PREFIX_0FF0) },
2784   { "psllw",            { MX, EM } },
2785   { "pslld",            { MX, EM } },
2786   { "psllq",            { MX, EM } },
2787   { "pmuludq",          { MX, EM } },
2788   { "pmaddwd",          { MX, EM } },
2789   { "psadbw",           { MX, EM } },
2790   { PREFIX_TABLE (PREFIX_0FF7) },
2791   /* f8 */
2792   { "psubb",            { MX, EM } },
2793   { "psubw",            { MX, EM } },
2794   { "psubd",            { MX, EM } },
2795   { "psubq",            { MX, EM } },
2796   { "paddb",            { MX, EM } },
2797   { "paddw",            { MX, EM } },
2798   { "paddd",            { MX, EM } },
2799   { Bad_Opcode },
2800 };
2801
2802 static const unsigned char onebyte_has_modrm[256] = {
2803   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2804   /*       -------------------------------        */
2805   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2806   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2807   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2808   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2809   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2810   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2811   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2812   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2813   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2814   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2815   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2816   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2817   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2818   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2819   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2820   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
2821   /*       -------------------------------        */
2822   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2823 };
2824
2825 static const unsigned char twobyte_has_modrm[256] = {
2826   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2827   /*       -------------------------------        */
2828   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2829   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2830   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2831   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2832   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2833   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2834   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2835   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2836   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2837   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2838   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2839   /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
2840   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2841   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2842   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2843   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0  /* ff */
2844   /*       -------------------------------        */
2845   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2846 };
2847
2848 static char obuf[100];
2849 static char *obufp;
2850 static char *mnemonicendp;
2851 static char scratchbuf[100];
2852 static unsigned char *start_codep;
2853 static unsigned char *insn_codep;
2854 static unsigned char *codep;
2855 static int last_lock_prefix;
2856 static int last_repz_prefix;
2857 static int last_repnz_prefix;
2858 static int last_data_prefix;
2859 static int last_addr_prefix;
2860 static int last_rex_prefix;
2861 static int last_seg_prefix;
2862 #define MAX_CODE_LENGTH 15
2863 /* We can up to 14 prefixes since the maximum instruction length is
2864    15bytes.  */
2865 static int all_prefixes[MAX_CODE_LENGTH - 1];
2866 static disassemble_info *the_info;
2867 static struct
2868   {
2869     int mod;
2870     int reg;
2871     int rm;
2872   }
2873 modrm;
2874 static unsigned char need_modrm;
2875 static struct
2876   {
2877     int scale;
2878     int index;
2879     int base;
2880   }
2881 sib;
2882 static struct
2883   {
2884     int register_specifier;
2885     int length;
2886     int prefix;
2887     int w;
2888     int evex;
2889     int r;
2890     int v;
2891     int mask_register_specifier;
2892     int zeroing;
2893     int ll;
2894     int b;
2895   }
2896 vex;
2897 static unsigned char need_vex;
2898 static unsigned char need_vex_reg;
2899 static unsigned char vex_w_done;
2900
2901 struct op
2902   {
2903     const char *name;
2904     unsigned int len;
2905   };
2906
2907 /* If we are accessing mod/rm/reg without need_modrm set, then the
2908    values are stale.  Hitting this abort likely indicates that you
2909    need to update onebyte_has_modrm or twobyte_has_modrm.  */
2910 #define MODRM_CHECK  if (!need_modrm) abort ()
2911
2912 static const char **names64;
2913 static const char **names32;
2914 static const char **names16;
2915 static const char **names8;
2916 static const char **names8rex;
2917 static const char **names_seg;
2918 static const char *index64;
2919 static const char *index32;
2920 static const char **index16;
2921 static const char **names_bnd;
2922
2923 static const char *intel_names64[] = {
2924   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2925   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2926 };
2927 static const char *intel_names32[] = {
2928   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
2929   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
2930 };
2931 static const char *intel_names16[] = {
2932   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
2933   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
2934 };
2935 static const char *intel_names8[] = {
2936   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2937 };
2938 static const char *intel_names8rex[] = {
2939   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2940   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2941 };
2942 static const char *intel_names_seg[] = {
2943   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2944 };
2945 static const char *intel_index64 = "riz";
2946 static const char *intel_index32 = "eiz";
2947 static const char *intel_index16[] = {
2948   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2949 };
2950
2951 static const char *att_names64[] = {
2952   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2953   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2954 };
2955 static const char *att_names32[] = {
2956   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2957   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2958 };
2959 static const char *att_names16[] = {
2960   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2961   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2962 };
2963 static const char *att_names8[] = {
2964   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2965 };
2966 static const char *att_names8rex[] = {
2967   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2968   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2969 };
2970 static const char *att_names_seg[] = {
2971   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2972 };
2973 static const char *att_index64 = "%riz";
2974 static const char *att_index32 = "%eiz";
2975 static const char *att_index16[] = {
2976   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2977 };
2978
2979 static const char **names_mm;
2980 static const char *intel_names_mm[] = {
2981   "mm0", "mm1", "mm2", "mm3",
2982   "mm4", "mm5", "mm6", "mm7"
2983 };
2984 static const char *att_names_mm[] = {
2985   "%mm0", "%mm1", "%mm2", "%mm3",
2986   "%mm4", "%mm5", "%mm6", "%mm7"
2987 };
2988
2989 static const char *intel_names_bnd[] = {
2990   "bnd0", "bnd1", "bnd2", "bnd3"
2991 };
2992
2993 static const char *att_names_bnd[] = {
2994   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
2995 };
2996
2997 static const char **names_xmm;
2998 static const char *intel_names_xmm[] = {
2999   "xmm0", "xmm1", "xmm2", "xmm3",
3000   "xmm4", "xmm5", "xmm6", "xmm7",
3001   "xmm8", "xmm9", "xmm10", "xmm11",
3002   "xmm12", "xmm13", "xmm14", "xmm15",
3003   "xmm16", "xmm17", "xmm18", "xmm19",
3004   "xmm20", "xmm21", "xmm22", "xmm23",
3005   "xmm24", "xmm25", "xmm26", "xmm27",
3006   "xmm28", "xmm29", "xmm30", "xmm31"
3007 };
3008 static const char *att_names_xmm[] = {
3009   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3010   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3011   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3012   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3013   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3014   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3015   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3016   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3017 };
3018
3019 static const char **names_ymm;
3020 static const char *intel_names_ymm[] = {
3021   "ymm0", "ymm1", "ymm2", "ymm3",
3022   "ymm4", "ymm5", "ymm6", "ymm7",
3023   "ymm8", "ymm9", "ymm10", "ymm11",
3024   "ymm12", "ymm13", "ymm14", "ymm15",
3025   "ymm16", "ymm17", "ymm18", "ymm19",
3026   "ymm20", "ymm21", "ymm22", "ymm23",
3027   "ymm24", "ymm25", "ymm26", "ymm27",
3028   "ymm28", "ymm29", "ymm30", "ymm31"
3029 };
3030 static const char *att_names_ymm[] = {
3031   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3032   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3033   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3034   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3035   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3036   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3037   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3038   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3039 };
3040
3041 static const char **names_zmm;
3042 static const char *intel_names_zmm[] = {
3043   "zmm0", "zmm1", "zmm2", "zmm3",
3044   "zmm4", "zmm5", "zmm6", "zmm7",
3045   "zmm8", "zmm9", "zmm10", "zmm11",
3046   "zmm12", "zmm13", "zmm14", "zmm15",
3047   "zmm16", "zmm17", "zmm18", "zmm19",
3048   "zmm20", "zmm21", "zmm22", "zmm23",
3049   "zmm24", "zmm25", "zmm26", "zmm27",
3050   "zmm28", "zmm29", "zmm30", "zmm31"
3051 };
3052 static const char *att_names_zmm[] = {
3053   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3054   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3055   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3056   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3057   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3058   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3059   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3060   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3061 };
3062
3063 static const char **names_mask;
3064 static const char *intel_names_mask[] = {
3065   "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3066 };
3067 static const char *att_names_mask[] = {
3068   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3069 };
3070
3071 static const char *names_rounding[] =
3072 {
3073   "{rn-sae}",
3074   "{rd-sae}",
3075   "{ru-sae}",
3076   "{rz-sae}"
3077 };
3078
3079 static const struct dis386 reg_table[][8] = {
3080   /* REG_80 */
3081   {
3082     { "addA",   { Ebh1, Ib } },
3083     { "orA",    { Ebh1, Ib } },
3084     { "adcA",   { Ebh1, Ib } },
3085     { "sbbA",   { Ebh1, Ib } },
3086     { "andA",   { Ebh1, Ib } },
3087     { "subA",   { Ebh1, Ib } },
3088     { "xorA",   { Ebh1, Ib } },
3089     { "cmpA",   { Eb, Ib } },
3090   },
3091   /* REG_81 */
3092   {
3093     { "addQ",   { Evh1, Iv } },
3094     { "orQ",    { Evh1, Iv } },
3095     { "adcQ",   { Evh1, Iv } },
3096     { "sbbQ",   { Evh1, Iv } },
3097     { "andQ",   { Evh1, Iv } },
3098     { "subQ",   { Evh1, Iv } },
3099     { "xorQ",   { Evh1, Iv } },
3100     { "cmpQ",   { Ev, Iv } },
3101   },
3102   /* REG_82 */
3103   {
3104     { "addQ",   { Evh1, sIb } },
3105     { "orQ",    { Evh1, sIb } },
3106     { "adcQ",   { Evh1, sIb } },
3107     { "sbbQ",   { Evh1, sIb } },
3108     { "andQ",   { Evh1, sIb } },
3109     { "subQ",   { Evh1, sIb } },
3110     { "xorQ",   { Evh1, sIb } },
3111     { "cmpQ",   { Ev, sIb } },
3112   },
3113   /* REG_8F */
3114   {
3115     { "popU",   { stackEv } },
3116     { XOP_8F_TABLE (XOP_09) },
3117     { Bad_Opcode },
3118     { Bad_Opcode },
3119     { Bad_Opcode },
3120     { XOP_8F_TABLE (XOP_09) },
3121   },
3122   /* REG_C0 */
3123   {
3124     { "rolA",   { Eb, Ib } },
3125     { "rorA",   { Eb, Ib } },
3126     { "rclA",   { Eb, Ib } },
3127     { "rcrA",   { Eb, Ib } },
3128     { "shlA",   { Eb, Ib } },
3129     { "shrA",   { Eb, Ib } },
3130     { Bad_Opcode },
3131     { "sarA",   { Eb, Ib } },
3132   },
3133   /* REG_C1 */
3134   {
3135     { "rolQ",   { Ev, Ib } },
3136     { "rorQ",   { Ev, Ib } },
3137     { "rclQ",   { Ev, Ib } },
3138     { "rcrQ",   { Ev, Ib } },
3139     { "shlQ",   { Ev, Ib } },
3140     { "shrQ",   { Ev, Ib } },
3141     { Bad_Opcode },
3142     { "sarQ",   { Ev, Ib } },
3143   },
3144   /* REG_C6 */
3145   {
3146     { "movA",   { Ebh3, Ib } },
3147     { Bad_Opcode },
3148     { Bad_Opcode },
3149     { Bad_Opcode },
3150     { Bad_Opcode },
3151     { Bad_Opcode },
3152     { Bad_Opcode },
3153     { MOD_TABLE (MOD_C6_REG_7) },
3154   },
3155   /* REG_C7 */
3156   {
3157     { "movQ",   { Evh3, Iv } },
3158     { Bad_Opcode },
3159     { Bad_Opcode },
3160     { Bad_Opcode },
3161     { Bad_Opcode },
3162     { Bad_Opcode },
3163     { Bad_Opcode },
3164     { MOD_TABLE (MOD_C7_REG_7) },
3165   },
3166   /* REG_D0 */
3167   {
3168     { "rolA",   { Eb, I1 } },
3169     { "rorA",   { Eb, I1 } },
3170     { "rclA",   { Eb, I1 } },
3171     { "rcrA",   { Eb, I1 } },
3172     { "shlA",   { Eb, I1 } },
3173     { "shrA",   { Eb, I1 } },
3174     { Bad_Opcode },
3175     { "sarA",   { Eb, I1 } },
3176   },
3177   /* REG_D1 */
3178   {
3179     { "rolQ",   { Ev, I1 } },
3180     { "rorQ",   { Ev, I1 } },
3181     { "rclQ",   { Ev, I1 } },
3182     { "rcrQ",   { Ev, I1 } },
3183     { "shlQ",   { Ev, I1 } },
3184     { "shrQ",   { Ev, I1 } },
3185     { Bad_Opcode },
3186     { "sarQ",   { Ev, I1 } },
3187   },
3188   /* REG_D2 */
3189   {
3190     { "rolA",   { Eb, CL } },
3191     { "rorA",   { Eb, CL } },
3192     { "rclA",   { Eb, CL } },
3193     { "rcrA",   { Eb, CL } },
3194     { "shlA",   { Eb, CL } },
3195     { "shrA",   { Eb, CL } },
3196     { Bad_Opcode },
3197     { "sarA",   { Eb, CL } },
3198   },
3199   /* REG_D3 */
3200   {
3201     { "rolQ",   { Ev, CL } },
3202     { "rorQ",   { Ev, CL } },
3203     { "rclQ",   { Ev, CL } },
3204     { "rcrQ",   { Ev, CL } },
3205     { "shlQ",   { Ev, CL } },
3206     { "shrQ",   { Ev, CL } },
3207     { Bad_Opcode },
3208     { "sarQ",   { Ev, CL } },
3209   },
3210   /* REG_F6 */
3211   {
3212     { "testA",  { Eb, Ib } },
3213     { Bad_Opcode },
3214     { "notA",   { Ebh1 } },
3215     { "negA",   { Ebh1 } },
3216     { "mulA",   { Eb } },       /* Don't print the implicit %al register,  */
3217     { "imulA",  { Eb } },       /* to distinguish these opcodes from other */
3218     { "divA",   { Eb } },       /* mul/imul opcodes.  Do the same for div  */
3219     { "idivA",  { Eb } },       /* and idiv for consistency.               */
3220   },
3221   /* REG_F7 */
3222   {
3223     { "testQ",  { Ev, Iv } },
3224     { Bad_Opcode },
3225     { "notQ",   { Evh1 } },
3226     { "negQ",   { Evh1 } },
3227     { "mulQ",   { Ev } },       /* Don't print the implicit register.  */
3228     { "imulQ",  { Ev } },
3229     { "divQ",   { Ev } },
3230     { "idivQ",  { Ev } },
3231   },
3232   /* REG_FE */
3233   {
3234     { "incA",   { Ebh1 } },
3235     { "decA",   { Ebh1 } },
3236   },
3237   /* REG_FF */
3238   {
3239     { "incQ",   { Evh1 } },
3240     { "decQ",   { Evh1 } },
3241     { "call{T|}", { indirEv, BND } },
3242     { MOD_TABLE (MOD_FF_REG_3) },
3243     { "jmp{T|}", { indirEv, BND } },
3244     { MOD_TABLE (MOD_FF_REG_5) },
3245     { "pushU",  { stackEv } },
3246     { Bad_Opcode },
3247   },
3248   /* REG_0F00 */
3249   {
3250     { "sldtD",  { Sv } },
3251     { "strD",   { Sv } },
3252     { "lldt",   { Ew } },
3253     { "ltr",    { Ew } },
3254     { "verr",   { Ew } },
3255     { "verw",   { Ew } },
3256     { Bad_Opcode },
3257     { Bad_Opcode },
3258   },
3259   /* REG_0F01 */
3260   {
3261     { MOD_TABLE (MOD_0F01_REG_0) },
3262     { MOD_TABLE (MOD_0F01_REG_1) },
3263     { MOD_TABLE (MOD_0F01_REG_2) },
3264     { MOD_TABLE (MOD_0F01_REG_3) },
3265     { "smswD",  { Sv } },
3266     { Bad_Opcode },
3267     { "lmsw",   { Ew } },
3268     { MOD_TABLE (MOD_0F01_REG_7) },
3269   },
3270   /* REG_0F0D */
3271   {
3272     { "prefetch",       { Mb } },
3273     { "prefetchw",      { Mb } },
3274     { "prefetchwt1",    { Mb } },
3275     { "prefetch",       { Mb } },
3276     { "prefetch",       { Mb } },
3277     { "prefetch",       { Mb } },
3278     { "prefetch",       { Mb } },
3279     { "prefetch",       { Mb } },
3280   },
3281   /* REG_0F18 */
3282   {
3283     { MOD_TABLE (MOD_0F18_REG_0) },
3284     { MOD_TABLE (MOD_0F18_REG_1) },
3285     { MOD_TABLE (MOD_0F18_REG_2) },
3286     { MOD_TABLE (MOD_0F18_REG_3) },
3287     { MOD_TABLE (MOD_0F18_REG_4) },
3288     { MOD_TABLE (MOD_0F18_REG_5) },
3289     { MOD_TABLE (MOD_0F18_REG_6) },
3290     { MOD_TABLE (MOD_0F18_REG_7) },
3291   },
3292   /* REG_0F71 */
3293   {
3294     { Bad_Opcode },
3295     { Bad_Opcode },
3296     { MOD_TABLE (MOD_0F71_REG_2) },
3297     { Bad_Opcode },
3298     { MOD_TABLE (MOD_0F71_REG_4) },
3299     { Bad_Opcode },
3300     { MOD_TABLE (MOD_0F71_REG_6) },
3301   },
3302   /* REG_0F72 */
3303   {
3304     { Bad_Opcode },
3305     { Bad_Opcode },
3306     { MOD_TABLE (MOD_0F72_REG_2) },
3307     { Bad_Opcode },
3308     { MOD_TABLE (MOD_0F72_REG_4) },
3309     { Bad_Opcode },
3310     { MOD_TABLE (MOD_0F72_REG_6) },
3311   },
3312   /* REG_0F73 */
3313   {
3314     { Bad_Opcode },
3315     { Bad_Opcode },
3316     { MOD_TABLE (MOD_0F73_REG_2) },
3317     { MOD_TABLE (MOD_0F73_REG_3) },
3318     { Bad_Opcode },
3319     { Bad_Opcode },
3320     { MOD_TABLE (MOD_0F73_REG_6) },
3321     { MOD_TABLE (MOD_0F73_REG_7) },
3322   },
3323   /* REG_0FA6 */
3324   {
3325     { "montmul",        { { OP_0f07, 0 } } },
3326     { "xsha1",          { { OP_0f07, 0 } } },
3327     { "xsha256",        { { OP_0f07, 0 } } },
3328   },
3329   /* REG_0FA7 */
3330   {
3331     { "xstore-rng",     { { OP_0f07, 0 } } },
3332     { "xcrypt-ecb",     { { OP_0f07, 0 } } },
3333     { "xcrypt-cbc",     { { OP_0f07, 0 } } },
3334     { "xcrypt-ctr",     { { OP_0f07, 0 } } },
3335     { "xcrypt-cfb",     { { OP_0f07, 0 } } },
3336     { "xcrypt-ofb",     { { OP_0f07, 0 } } },
3337   },
3338   /* REG_0FAE */
3339   {
3340     { MOD_TABLE (MOD_0FAE_REG_0) },
3341     { MOD_TABLE (MOD_0FAE_REG_1) },
3342     { MOD_TABLE (MOD_0FAE_REG_2) },
3343     { MOD_TABLE (MOD_0FAE_REG_3) },
3344     { MOD_TABLE (MOD_0FAE_REG_4) },
3345     { MOD_TABLE (MOD_0FAE_REG_5) },
3346     { MOD_TABLE (MOD_0FAE_REG_6) },
3347     { MOD_TABLE (MOD_0FAE_REG_7) },
3348   },
3349   /* REG_0FBA */
3350   {
3351     { Bad_Opcode },
3352     { Bad_Opcode },
3353     { Bad_Opcode },
3354     { Bad_Opcode },
3355     { "btQ",    { Ev, Ib } },
3356     { "btsQ",   { Evh1, Ib } },
3357     { "btrQ",   { Evh1, Ib } },
3358     { "btcQ",   { Evh1, Ib } },
3359   },
3360   /* REG_0FC7 */
3361   {
3362     { Bad_Opcode },
3363     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } },
3364     { Bad_Opcode },
3365     { MOD_TABLE (MOD_0FC7_REG_3) },
3366     { MOD_TABLE (MOD_0FC7_REG_4) },
3367     { MOD_TABLE (MOD_0FC7_REG_5) },
3368     { MOD_TABLE (MOD_0FC7_REG_6) },
3369     { MOD_TABLE (MOD_0FC7_REG_7) },
3370   },
3371   /* REG_VEX_0F71 */
3372   {
3373     { Bad_Opcode },
3374     { Bad_Opcode },
3375     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3376     { Bad_Opcode },
3377     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3378     { Bad_Opcode },
3379     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3380   },
3381   /* REG_VEX_0F72 */
3382   {
3383     { Bad_Opcode },
3384     { Bad_Opcode },
3385     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3386     { Bad_Opcode },
3387     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3388     { Bad_Opcode },
3389     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3390   },
3391   /* REG_VEX_0F73 */
3392   {
3393     { Bad_Opcode },
3394     { Bad_Opcode },
3395     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3396     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3397     { Bad_Opcode },
3398     { Bad_Opcode },
3399     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3400     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3401   },
3402   /* REG_VEX_0FAE */
3403   {
3404     { Bad_Opcode },
3405     { Bad_Opcode },
3406     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3407     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3408   },
3409   /* REG_VEX_0F38F3 */
3410   {
3411     { Bad_Opcode },
3412     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3413     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3414     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3415   },
3416   /* REG_XOP_LWPCB */
3417   {
3418     { "llwpcb", { { OP_LWPCB_E, 0 } } },
3419     { "slwpcb", { { OP_LWPCB_E, 0 } } },
3420   },
3421   /* REG_XOP_LWP */
3422   {
3423     { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq } },
3424     { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq } },
3425   },
3426   /* REG_XOP_TBM_01 */
3427   {
3428     { Bad_Opcode },
3429     { "blcfill",        { { OP_LWP_E, 0 }, Ev } },
3430     { "blsfill",        { { OP_LWP_E, 0 }, Ev } },
3431     { "blcs",   { { OP_LWP_E, 0 }, Ev } },
3432     { "tzmsk",  { { OP_LWP_E, 0 }, Ev } },
3433     { "blcic",  { { OP_LWP_E, 0 }, Ev } },
3434     { "blsic",  { { OP_LWP_E, 0 }, Ev } },
3435     { "t1mskc", { { OP_LWP_E, 0 }, Ev } },
3436   },
3437   /* REG_XOP_TBM_02 */
3438   {
3439     { Bad_Opcode },
3440     { "blcmsk", { { OP_LWP_E, 0 }, Ev } },
3441     { Bad_Opcode },
3442     { Bad_Opcode },
3443     { Bad_Opcode },
3444     { Bad_Opcode },
3445     { "blci",   { { OP_LWP_E, 0 }, Ev } },
3446   },
3447 #define NEED_REG_TABLE
3448 #include "i386-dis-evex.h"
3449 #undef NEED_REG_TABLE
3450 };
3451
3452 static const struct dis386 prefix_table[][4] = {
3453   /* PREFIX_90 */
3454   {
3455     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
3456     { "pause", { XX } },
3457     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
3458   },
3459
3460   /* PREFIX_0F10 */
3461   {
3462     { "movups", { XM, EXx } },
3463     { "movss",  { XM, EXd } },
3464     { "movupd", { XM, EXx } },
3465     { "movsd",  { XM, EXq } },
3466   },
3467
3468   /* PREFIX_0F11 */
3469   {
3470     { "movups", { EXxS, XM } },
3471     { "movss",  { EXdS, XM } },
3472     { "movupd", { EXxS, XM } },
3473     { "movsd",  { EXqS, XM } },
3474   },
3475
3476   /* PREFIX_0F12 */
3477   {
3478     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3479     { "movsldup", { XM, EXx } },
3480     { "movlpd", { XM, EXq } },
3481     { "movddup", { XM, EXq } },
3482   },
3483
3484   /* PREFIX_0F16 */
3485   {
3486     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3487     { "movshdup", { XM, EXx } },
3488     { "movhpd", { XM, EXq } },
3489   },
3490
3491   /* PREFIX_0F1A */
3492   {
3493     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3494     { "bndcl",  { Gbnd, Ev_bnd } },
3495     { "bndmov", { Gbnd, Ebnd } },
3496     { "bndcu",  { Gbnd, Ev_bnd } },
3497   },
3498
3499   /* PREFIX_0F1B */
3500   {
3501     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3502     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3503     { "bndmov", { Ebnd, Gbnd } },
3504     { "bndcn",  { Gbnd, Ev_bnd } },
3505   },
3506
3507   /* PREFIX_0F2A */
3508   {
3509     { "cvtpi2ps", { XM, EMCq } },
3510     { "cvtsi2ss%LQ", { XM, Ev } },
3511     { "cvtpi2pd", { XM, EMCq } },
3512     { "cvtsi2sd%LQ", { XM, Ev } },
3513   },
3514
3515   /* PREFIX_0F2B */
3516   {
3517     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3518     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3519     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3520     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3521   },
3522
3523   /* PREFIX_0F2C */
3524   {
3525     { "cvttps2pi", { MXC, EXq } },
3526     { "cvttss2siY", { Gv, EXd } },
3527     { "cvttpd2pi", { MXC, EXx } },
3528     { "cvttsd2siY", { Gv, EXq } },
3529   },
3530
3531   /* PREFIX_0F2D */
3532   {
3533     { "cvtps2pi", { MXC, EXq } },
3534     { "cvtss2siY", { Gv, EXd } },
3535     { "cvtpd2pi", { MXC, EXx } },
3536     { "cvtsd2siY", { Gv, EXq } },
3537   },
3538
3539   /* PREFIX_0F2E */
3540   {
3541     { "ucomiss",{ XM, EXd } },
3542     { Bad_Opcode },
3543     { "ucomisd",{ XM, EXq } },
3544   },
3545
3546   /* PREFIX_0F2F */
3547   {
3548     { "comiss", { XM, EXd } },
3549     { Bad_Opcode },
3550     { "comisd", { XM, EXq } },
3551   },
3552
3553   /* PREFIX_0F51 */
3554   {
3555     { "sqrtps", { XM, EXx } },
3556     { "sqrtss", { XM, EXd } },
3557     { "sqrtpd", { XM, EXx } },
3558     { "sqrtsd", { XM, EXq } },
3559   },
3560
3561   /* PREFIX_0F52 */
3562   {
3563     { "rsqrtps",{ XM, EXx } },
3564     { "rsqrtss",{ XM, EXd } },
3565   },
3566
3567   /* PREFIX_0F53 */
3568   {
3569     { "rcpps",  { XM, EXx } },
3570     { "rcpss",  { XM, EXd } },
3571   },
3572
3573   /* PREFIX_0F58 */
3574   {
3575     { "addps", { XM, EXx } },
3576     { "addss", { XM, EXd } },
3577     { "addpd", { XM, EXx } },
3578     { "addsd", { XM, EXq } },
3579   },
3580
3581   /* PREFIX_0F59 */
3582   {
3583     { "mulps",  { XM, EXx } },
3584     { "mulss",  { XM, EXd } },
3585     { "mulpd",  { XM, EXx } },
3586     { "mulsd",  { XM, EXq } },
3587   },
3588
3589   /* PREFIX_0F5A */
3590   {
3591     { "cvtps2pd", { XM, EXq } },
3592     { "cvtss2sd", { XM, EXd } },
3593     { "cvtpd2ps", { XM, EXx } },
3594     { "cvtsd2ss", { XM, EXq } },
3595   },
3596
3597   /* PREFIX_0F5B */
3598   {
3599     { "cvtdq2ps", { XM, EXx } },
3600     { "cvttps2dq", { XM, EXx } },
3601     { "cvtps2dq", { XM, EXx } },
3602   },
3603
3604   /* PREFIX_0F5C */
3605   {
3606     { "subps",  { XM, EXx } },
3607     { "subss",  { XM, EXd } },
3608     { "subpd",  { XM, EXx } },
3609     { "subsd",  { XM, EXq } },
3610   },
3611
3612   /* PREFIX_0F5D */
3613   {
3614     { "minps",  { XM, EXx } },
3615     { "minss",  { XM, EXd } },
3616     { "minpd",  { XM, EXx } },
3617     { "minsd",  { XM, EXq } },
3618   },
3619
3620   /* PREFIX_0F5E */
3621   {
3622     { "divps",  { XM, EXx } },
3623     { "divss",  { XM, EXd } },
3624     { "divpd",  { XM, EXx } },
3625     { "divsd",  { XM, EXq } },
3626   },
3627
3628   /* PREFIX_0F5F */
3629   {
3630     { "maxps",  { XM, EXx } },
3631     { "maxss",  { XM, EXd } },
3632     { "maxpd",  { XM, EXx } },
3633     { "maxsd",  { XM, EXq } },
3634   },
3635
3636   /* PREFIX_0F60 */
3637   {
3638     { "punpcklbw",{ MX, EMd } },
3639     { Bad_Opcode },
3640     { "punpcklbw",{ MX, EMx } },
3641   },
3642
3643   /* PREFIX_0F61 */
3644   {
3645     { "punpcklwd",{ MX, EMd } },
3646     { Bad_Opcode },
3647     { "punpcklwd",{ MX, EMx } },
3648   },
3649
3650   /* PREFIX_0F62 */
3651   {
3652     { "punpckldq",{ MX, EMd } },
3653     { Bad_Opcode },
3654     { "punpckldq",{ MX, EMx } },
3655   },
3656
3657   /* PREFIX_0F6C */
3658   {
3659     { Bad_Opcode },
3660     { Bad_Opcode },
3661     { "punpcklqdq", { XM, EXx } },
3662   },
3663
3664   /* PREFIX_0F6D */
3665   {
3666     { Bad_Opcode },
3667     { Bad_Opcode },
3668     { "punpckhqdq", { XM, EXx } },
3669   },
3670
3671   /* PREFIX_0F6F */
3672   {
3673     { "movq",   { MX, EM } },
3674     { "movdqu", { XM, EXx } },
3675     { "movdqa", { XM, EXx } },
3676   },
3677
3678   /* PREFIX_0F70 */
3679   {
3680     { "pshufw", { MX, EM, Ib } },
3681     { "pshufhw",{ XM, EXx, Ib } },
3682     { "pshufd", { XM, EXx, Ib } },
3683     { "pshuflw",{ XM, EXx, Ib } },
3684   },
3685
3686   /* PREFIX_0F73_REG_3 */
3687   {
3688     { Bad_Opcode },
3689     { Bad_Opcode },
3690     { "psrldq", { XS, Ib } },
3691   },
3692
3693   /* PREFIX_0F73_REG_7 */
3694   {
3695     { Bad_Opcode },
3696     { Bad_Opcode },
3697     { "pslldq", { XS, Ib } },
3698   },
3699
3700   /* PREFIX_0F78 */
3701   {
3702     {"vmread",  { Em, Gm } },
3703     { Bad_Opcode },
3704     {"extrq",   { XS, Ib, Ib } },
3705     {"insertq", { XM, XS, Ib, Ib } },
3706   },
3707
3708   /* PREFIX_0F79 */
3709   {
3710     {"vmwrite", { Gm, Em } },
3711     { Bad_Opcode },
3712     {"extrq",   { XM, XS } },
3713     {"insertq", { XM, XS } },
3714   },
3715
3716   /* PREFIX_0F7C */
3717   {
3718     { Bad_Opcode },
3719     { Bad_Opcode },
3720     { "haddpd", { XM, EXx } },
3721     { "haddps", { XM, EXx } },
3722   },
3723
3724   /* PREFIX_0F7D */
3725   {
3726     { Bad_Opcode },
3727     { Bad_Opcode },
3728     { "hsubpd", { XM, EXx } },
3729     { "hsubps", { XM, EXx } },
3730   },
3731
3732   /* PREFIX_0F7E */
3733   {
3734     { "movK",   { Edq, MX } },
3735     { "movq",   { XM, EXq } },
3736     { "movK",   { Edq, XM } },
3737   },
3738
3739   /* PREFIX_0F7F */
3740   {
3741     { "movq",   { EMS, MX } },
3742     { "movdqu", { EXxS, XM } },
3743     { "movdqa", { EXxS, XM } },
3744   },
3745
3746   /* PREFIX_0FAE_REG_0 */
3747   {
3748     { Bad_Opcode },
3749     { "rdfsbase", { Ev } },
3750   },
3751
3752   /* PREFIX_0FAE_REG_1 */
3753   {
3754     { Bad_Opcode },
3755     { "rdgsbase", { Ev } },
3756   },
3757
3758   /* PREFIX_0FAE_REG_2 */
3759   {
3760     { Bad_Opcode },
3761     { "wrfsbase", { Ev } },
3762   },
3763
3764   /* PREFIX_0FAE_REG_3 */
3765   {
3766     { Bad_Opcode },
3767     { "wrgsbase", { Ev } },
3768   },
3769
3770   /* PREFIX_0FAE_REG_7 */
3771   {
3772     { "clflush",        { Mb } },
3773     { Bad_Opcode },
3774     { "clflushopt",     { Mb } },
3775   },
3776
3777   /* PREFIX_0FB8 */
3778   {
3779     { Bad_Opcode },
3780     { "popcntS", { Gv, Ev } },
3781   },
3782
3783   /* PREFIX_0FBC */
3784   {
3785     { "bsfS",   { Gv, Ev } },
3786     { "tzcntS", { Gv, Ev } },
3787     { "bsfS",   { Gv, Ev } },
3788   },
3789
3790   /* PREFIX_0FBD */
3791   {
3792     { "bsrS",   { Gv, Ev } },
3793     { "lzcntS", { Gv, Ev } },
3794     { "bsrS",   { Gv, Ev } },
3795   },
3796
3797   /* PREFIX_0FC2 */
3798   {
3799     { "cmpps",  { XM, EXx, CMP } },
3800     { "cmpss",  { XM, EXd, CMP } },
3801     { "cmppd",  { XM, EXx, CMP } },
3802     { "cmpsd",  { XM, EXq, CMP } },
3803   },
3804
3805   /* PREFIX_0FC3 */
3806   {
3807     { "movntiS", { Ma, Gv } },
3808   },
3809
3810   /* PREFIX_0FC7_REG_6 */
3811   {
3812     { "vmptrld",{ Mq } },
3813     { "vmxon",  { Mq } },
3814     { "vmclear",{ Mq } },
3815   },
3816
3817   /* PREFIX_0FD0 */
3818   {
3819     { Bad_Opcode },
3820     { Bad_Opcode },
3821     { "addsubpd", { XM, EXx } },
3822     { "addsubps", { XM, EXx } },
3823   },
3824
3825   /* PREFIX_0FD6 */
3826   {
3827     { Bad_Opcode },
3828     { "movq2dq",{ XM, MS } },
3829     { "movq",   { EXqS, XM } },
3830     { "movdq2q",{ MX, XS } },
3831   },
3832
3833   /* PREFIX_0FE6 */
3834   {
3835     { Bad_Opcode },
3836     { "cvtdq2pd", { XM, EXq } },
3837     { "cvttpd2dq", { XM, EXx } },
3838     { "cvtpd2dq", { XM, EXx } },
3839   },
3840
3841   /* PREFIX_0FE7 */
3842   {
3843     { "movntq", { Mq, MX } },
3844     { Bad_Opcode },
3845     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
3846   },
3847
3848   /* PREFIX_0FF0 */
3849   {
3850     { Bad_Opcode },
3851     { Bad_Opcode },
3852     { Bad_Opcode },
3853     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
3854   },
3855
3856   /* PREFIX_0FF7 */
3857   {
3858     { "maskmovq", { MX, MS } },
3859     { Bad_Opcode },
3860     { "maskmovdqu", { XM, XS } },
3861   },
3862
3863   /* PREFIX_0F3810 */
3864   {
3865     { Bad_Opcode },
3866     { Bad_Opcode },
3867     { "pblendvb", { XM, EXx, XMM0 } },
3868   },
3869
3870   /* PREFIX_0F3814 */
3871   {
3872     { Bad_Opcode },
3873     { Bad_Opcode },
3874     { "blendvps", { XM, EXx, XMM0 } },
3875   },
3876
3877   /* PREFIX_0F3815 */
3878   {
3879     { Bad_Opcode },
3880     { Bad_Opcode },
3881     { "blendvpd", { XM, EXx, XMM0 } },
3882   },
3883
3884   /* PREFIX_0F3817 */
3885   {
3886     { Bad_Opcode },
3887     { Bad_Opcode },
3888     { "ptest",  { XM, EXx } },
3889   },
3890
3891   /* PREFIX_0F3820 */
3892   {
3893     { Bad_Opcode },
3894     { Bad_Opcode },
3895     { "pmovsxbw", { XM, EXq } },
3896   },
3897
3898   /* PREFIX_0F3821 */
3899   {
3900     { Bad_Opcode },
3901     { Bad_Opcode },
3902     { "pmovsxbd", { XM, EXd } },
3903   },
3904
3905   /* PREFIX_0F3822 */
3906   {
3907     { Bad_Opcode },
3908     { Bad_Opcode },
3909     { "pmovsxbq", { XM, EXw } },
3910   },
3911
3912   /* PREFIX_0F3823 */
3913   {
3914     { Bad_Opcode },
3915     { Bad_Opcode },
3916     { "pmovsxwd", { XM, EXq } },
3917   },
3918
3919   /* PREFIX_0F3824 */
3920   {
3921     { Bad_Opcode },
3922     { Bad_Opcode },
3923     { "pmovsxwq", { XM, EXd } },
3924   },
3925
3926   /* PREFIX_0F3825 */
3927   {
3928     { Bad_Opcode },
3929     { Bad_Opcode },
3930     { "pmovsxdq", { XM, EXq } },
3931   },
3932
3933   /* PREFIX_0F3828 */
3934   {
3935     { Bad_Opcode },
3936     { Bad_Opcode },
3937     { "pmuldq", { XM, EXx } },
3938   },
3939
3940   /* PREFIX_0F3829 */
3941   {
3942     { Bad_Opcode },
3943     { Bad_Opcode },
3944     { "pcmpeqq", { XM, EXx } },
3945   },
3946
3947   /* PREFIX_0F382A */
3948   {
3949     { Bad_Opcode },
3950     { Bad_Opcode },
3951     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
3952   },
3953
3954   /* PREFIX_0F382B */
3955   {
3956     { Bad_Opcode },
3957     { Bad_Opcode },
3958     { "packusdw", { XM, EXx } },
3959   },
3960
3961   /* PREFIX_0F3830 */
3962   {
3963     { Bad_Opcode },
3964     { Bad_Opcode },
3965     { "pmovzxbw", { XM, EXq } },
3966   },
3967
3968   /* PREFIX_0F3831 */
3969   {
3970     { Bad_Opcode },
3971     { Bad_Opcode },
3972     { "pmovzxbd", { XM, EXd } },
3973   },
3974
3975   /* PREFIX_0F3832 */
3976   {
3977     { Bad_Opcode },
3978     { Bad_Opcode },
3979     { "pmovzxbq", { XM, EXw } },
3980   },
3981
3982   /* PREFIX_0F3833 */
3983   {
3984     { Bad_Opcode },
3985     { Bad_Opcode },
3986     { "pmovzxwd", { XM, EXq } },
3987   },
3988
3989   /* PREFIX_0F3834 */
3990   {
3991     { Bad_Opcode },
3992     { Bad_Opcode },
3993     { "pmovzxwq", { XM, EXd } },
3994   },
3995
3996   /* PREFIX_0F3835 */
3997   {
3998     { Bad_Opcode },
3999     { Bad_Opcode },
4000     { "pmovzxdq", { XM, EXq } },
4001   },
4002
4003   /* PREFIX_0F3837 */
4004   {
4005     { Bad_Opcode },
4006     { Bad_Opcode },
4007     { "pcmpgtq", { XM, EXx } },
4008   },
4009
4010   /* PREFIX_0F3838 */
4011   {
4012     { Bad_Opcode },
4013     { Bad_Opcode },
4014     { "pminsb", { XM, EXx } },
4015   },
4016
4017   /* PREFIX_0F3839 */
4018   {
4019     { Bad_Opcode },
4020     { Bad_Opcode },
4021     { "pminsd", { XM, EXx } },
4022   },
4023
4024   /* PREFIX_0F383A */
4025   {
4026     { Bad_Opcode },
4027     { Bad_Opcode },
4028     { "pminuw", { XM, EXx } },
4029   },
4030
4031   /* PREFIX_0F383B */
4032   {
4033     { Bad_Opcode },
4034     { Bad_Opcode },
4035     { "pminud", { XM, EXx } },
4036   },
4037
4038   /* PREFIX_0F383C */
4039   {
4040     { Bad_Opcode },
4041     { Bad_Opcode },
4042     { "pmaxsb", { XM, EXx } },
4043   },
4044
4045   /* PREFIX_0F383D */
4046   {
4047     { Bad_Opcode },
4048     { Bad_Opcode },
4049     { "pmaxsd", { XM, EXx } },
4050   },
4051
4052   /* PREFIX_0F383E */
4053   {
4054     { Bad_Opcode },
4055     { Bad_Opcode },
4056     { "pmaxuw", { XM, EXx } },
4057   },
4058
4059   /* PREFIX_0F383F */
4060   {
4061     { Bad_Opcode },
4062     { Bad_Opcode },
4063     { "pmaxud", { XM, EXx } },
4064   },
4065
4066   /* PREFIX_0F3840 */
4067   {
4068     { Bad_Opcode },
4069     { Bad_Opcode },
4070     { "pmulld", { XM, EXx } },
4071   },
4072
4073   /* PREFIX_0F3841 */
4074   {
4075     { Bad_Opcode },
4076     { Bad_Opcode },
4077     { "phminposuw", { XM, EXx } },
4078   },
4079
4080   /* PREFIX_0F3880 */
4081   {
4082     { Bad_Opcode },
4083     { Bad_Opcode },
4084     { "invept", { Gm, Mo } },
4085   },
4086
4087   /* PREFIX_0F3881 */
4088   {
4089     { Bad_Opcode },
4090     { Bad_Opcode },
4091     { "invvpid", { Gm, Mo } },
4092   },
4093
4094   /* PREFIX_0F3882 */
4095   {
4096     { Bad_Opcode },
4097     { Bad_Opcode },
4098     { "invpcid", { Gm, M } },
4099   },
4100
4101   /* PREFIX_0F38C8 */
4102   {
4103     { "sha1nexte", { XM, EXxmm } },
4104   },
4105
4106   /* PREFIX_0F38C9 */
4107   {
4108     { "sha1msg1", { XM, EXxmm } },
4109   },
4110
4111   /* PREFIX_0F38CA */
4112   {
4113     { "sha1msg2", { XM, EXxmm } },
4114   },
4115
4116   /* PREFIX_0F38CB */
4117   {
4118     { "sha256rnds2", { XM, EXxmm, XMM0 } },
4119   },
4120
4121   /* PREFIX_0F38CC */
4122   {
4123     { "sha256msg1", { XM, EXxmm } },
4124   },
4125
4126   /* PREFIX_0F38CD */
4127   {
4128     { "sha256msg2", { XM, EXxmm } },
4129   },
4130
4131   /* PREFIX_0F38DB */
4132   {
4133     { Bad_Opcode },
4134     { Bad_Opcode },
4135     { "aesimc", { XM, EXx } },
4136   },
4137
4138   /* PREFIX_0F38DC */
4139   {
4140     { Bad_Opcode },
4141     { Bad_Opcode },
4142     { "aesenc", { XM, EXx } },
4143   },
4144
4145   /* PREFIX_0F38DD */
4146   {
4147     { Bad_Opcode },
4148     { Bad_Opcode },
4149     { "aesenclast", { XM, EXx } },
4150   },
4151
4152   /* PREFIX_0F38DE */
4153   {
4154     { Bad_Opcode },
4155     { Bad_Opcode },
4156     { "aesdec", { XM, EXx } },
4157   },
4158
4159   /* PREFIX_0F38DF */
4160   {
4161     { Bad_Opcode },
4162     { Bad_Opcode },
4163     { "aesdeclast", { XM, EXx } },
4164   },
4165
4166   /* PREFIX_0F38F0 */
4167   {
4168     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
4169     { Bad_Opcode },
4170     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
4171     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } } },
4172   },
4173
4174   /* PREFIX_0F38F1 */
4175   {
4176     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
4177     { Bad_Opcode },
4178     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
4179     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } } },
4180   },
4181
4182   /* PREFIX_0F38F6 */
4183   {
4184     { Bad_Opcode },
4185     { "adoxS",  { Gdq, Edq} },
4186     { "adcxS",  { Gdq, Edq} },
4187     { Bad_Opcode },
4188   },
4189
4190   /* PREFIX_0F3A08 */
4191   {
4192     { Bad_Opcode },
4193     { Bad_Opcode },
4194     { "roundps", { XM, EXx, Ib } },
4195   },
4196
4197   /* PREFIX_0F3A09 */
4198   {
4199     { Bad_Opcode },
4200     { Bad_Opcode },
4201     { "roundpd", { XM, EXx, Ib } },
4202   },
4203
4204   /* PREFIX_0F3A0A */
4205   {
4206     { Bad_Opcode },
4207     { Bad_Opcode },
4208     { "roundss", { XM, EXd, Ib } },
4209   },
4210
4211   /* PREFIX_0F3A0B */
4212   {
4213     { Bad_Opcode },
4214     { Bad_Opcode },
4215     { "roundsd", { XM, EXq, Ib } },
4216   },
4217
4218   /* PREFIX_0F3A0C */
4219   {
4220     { Bad_Opcode },
4221     { Bad_Opcode },
4222     { "blendps", { XM, EXx, Ib } },
4223   },
4224
4225   /* PREFIX_0F3A0D */
4226   {
4227     { Bad_Opcode },
4228     { Bad_Opcode },
4229     { "blendpd", { XM, EXx, Ib } },
4230   },
4231
4232   /* PREFIX_0F3A0E */
4233   {
4234     { Bad_Opcode },
4235     { Bad_Opcode },
4236     { "pblendw", { XM, EXx, Ib } },
4237   },
4238
4239   /* PREFIX_0F3A14 */
4240   {
4241     { Bad_Opcode },
4242     { Bad_Opcode },
4243     { "pextrb", { Edqb, XM, Ib } },
4244   },
4245
4246   /* PREFIX_0F3A15 */
4247   {
4248     { Bad_Opcode },
4249     { Bad_Opcode },
4250     { "pextrw", { Edqw, XM, Ib } },
4251   },
4252
4253   /* PREFIX_0F3A16 */
4254   {
4255     { Bad_Opcode },
4256     { Bad_Opcode },
4257     { "pextrK", { Edq, XM, Ib } },
4258   },
4259
4260   /* PREFIX_0F3A17 */
4261   {
4262     { Bad_Opcode },
4263     { Bad_Opcode },
4264     { "extractps", { Edqd, XM, Ib } },
4265   },
4266
4267   /* PREFIX_0F3A20 */
4268   {
4269     { Bad_Opcode },
4270     { Bad_Opcode },
4271     { "pinsrb", { XM, Edqb, Ib } },
4272   },
4273
4274   /* PREFIX_0F3A21 */
4275   {
4276     { Bad_Opcode },
4277     { Bad_Opcode },
4278     { "insertps", { XM, EXd, Ib } },
4279   },
4280
4281   /* PREFIX_0F3A22 */
4282   {
4283     { Bad_Opcode },
4284     { Bad_Opcode },
4285     { "pinsrK", { XM, Edq, Ib } },
4286   },
4287
4288   /* PREFIX_0F3A40 */
4289   {
4290     { Bad_Opcode },
4291     { Bad_Opcode },
4292     { "dpps",   { XM, EXx, Ib } },
4293   },
4294
4295   /* PREFIX_0F3A41 */
4296   {
4297     { Bad_Opcode },
4298     { Bad_Opcode },
4299     { "dppd",   { XM, EXx, Ib } },
4300   },
4301
4302   /* PREFIX_0F3A42 */
4303   {
4304     { Bad_Opcode },
4305     { Bad_Opcode },
4306     { "mpsadbw", { XM, EXx, Ib } },
4307   },
4308
4309   /* PREFIX_0F3A44 */
4310   {
4311     { Bad_Opcode },
4312     { Bad_Opcode },
4313     { "pclmulqdq", { XM, EXx, PCLMUL } },
4314   },
4315
4316   /* PREFIX_0F3A60 */
4317   {
4318     { Bad_Opcode },
4319     { Bad_Opcode },
4320     { "pcmpestrm", { XM, EXx, Ib } },
4321   },
4322
4323   /* PREFIX_0F3A61 */
4324   {
4325     { Bad_Opcode },
4326     { Bad_Opcode },
4327     { "pcmpestri", { XM, EXx, Ib } },
4328   },
4329
4330   /* PREFIX_0F3A62 */
4331   {
4332     { Bad_Opcode },
4333     { Bad_Opcode },
4334     { "pcmpistrm", { XM, EXx, Ib } },
4335   },
4336
4337   /* PREFIX_0F3A63 */
4338   {
4339     { Bad_Opcode },
4340     { Bad_Opcode },
4341     { "pcmpistri", { XM, EXx, Ib } },
4342   },
4343
4344   /* PREFIX_0F3ACC */
4345   {
4346     { "sha1rnds4", { XM, EXxmm, Ib } },
4347   },
4348
4349   /* PREFIX_0F3ADF */
4350   {
4351     { Bad_Opcode },
4352     { Bad_Opcode },
4353     { "aeskeygenassist", { XM, EXx, Ib } },
4354   },
4355
4356   /* PREFIX_VEX_0F10 */
4357   {
4358     { VEX_W_TABLE (VEX_W_0F10_P_0) },
4359     { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) },
4360     { VEX_W_TABLE (VEX_W_0F10_P_2) },
4361     { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) },
4362   },
4363
4364   /* PREFIX_VEX_0F11 */
4365   {
4366     { VEX_W_TABLE (VEX_W_0F11_P_0) },
4367     { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) },
4368     { VEX_W_TABLE (VEX_W_0F11_P_2) },
4369     { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) },
4370   },
4371
4372   /* PREFIX_VEX_0F12 */
4373   {
4374     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4375     { VEX_W_TABLE (VEX_W_0F12_P_1) },
4376     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
4377     { VEX_W_TABLE (VEX_W_0F12_P_3) },
4378   },
4379
4380   /* PREFIX_VEX_0F16 */
4381   {
4382     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4383     { VEX_W_TABLE (VEX_W_0F16_P_1) },
4384     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
4385   },
4386
4387   /* PREFIX_VEX_0F2A */
4388   {
4389     { Bad_Opcode },
4390     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) },
4391     { Bad_Opcode },
4392     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) },
4393   },
4394
4395   /* PREFIX_VEX_0F2C */
4396   {
4397     { Bad_Opcode },
4398     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) },
4399     { Bad_Opcode },
4400     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) },
4401   },
4402
4403   /* PREFIX_VEX_0F2D */
4404   {
4405     { Bad_Opcode },
4406     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) },
4407     { Bad_Opcode },
4408     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) },
4409   },
4410
4411   /* PREFIX_VEX_0F2E */
4412   {
4413     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) },
4414     { Bad_Opcode },
4415     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) },
4416   },
4417
4418   /* PREFIX_VEX_0F2F */
4419   {
4420     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) },
4421     { Bad_Opcode },
4422     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) },
4423   },
4424
4425   /* PREFIX_VEX_0F41 */
4426   {
4427     { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4428   },
4429
4430   /* PREFIX_VEX_0F42 */
4431   {
4432     { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4433   },
4434
4435   /* PREFIX_VEX_0F44 */
4436   {
4437     { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4438   },
4439
4440   /* PREFIX_VEX_0F45 */
4441   {
4442     { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4443   },
4444
4445   /* PREFIX_VEX_0F46 */
4446   {
4447     { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4448   },
4449
4450   /* PREFIX_VEX_0F47 */
4451   {
4452     { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4453   },
4454
4455   /* PREFIX_VEX_0F4B */
4456   {
4457     { Bad_Opcode },
4458     { Bad_Opcode },
4459     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4460   },
4461
4462   /* PREFIX_VEX_0F51 */
4463   {
4464     { VEX_W_TABLE (VEX_W_0F51_P_0) },
4465     { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) },
4466     { VEX_W_TABLE (VEX_W_0F51_P_2) },
4467     { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) },
4468   },
4469
4470   /* PREFIX_VEX_0F52 */
4471   {
4472     { VEX_W_TABLE (VEX_W_0F52_P_0) },
4473     { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) },
4474   },
4475
4476   /* PREFIX_VEX_0F53 */
4477   {
4478     { VEX_W_TABLE (VEX_W_0F53_P_0) },
4479     { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) },
4480   },
4481
4482   /* PREFIX_VEX_0F58 */
4483   {
4484     { VEX_W_TABLE (VEX_W_0F58_P_0) },
4485     { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) },
4486     { VEX_W_TABLE (VEX_W_0F58_P_2) },
4487     { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) },
4488   },
4489
4490   /* PREFIX_VEX_0F59 */
4491   {
4492     { VEX_W_TABLE (VEX_W_0F59_P_0) },
4493     { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) },
4494     { VEX_W_TABLE (VEX_W_0F59_P_2) },
4495     { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) },
4496   },
4497
4498   /* PREFIX_VEX_0F5A */
4499   {
4500     { VEX_W_TABLE (VEX_W_0F5A_P_0) },
4501     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) },
4502     { "vcvtpd2ps%XY", { XMM, EXx } },
4503     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) },
4504   },
4505
4506   /* PREFIX_VEX_0F5B */
4507   {
4508     { VEX_W_TABLE (VEX_W_0F5B_P_0) },
4509     { VEX_W_TABLE (VEX_W_0F5B_P_1) },
4510     { VEX_W_TABLE (VEX_W_0F5B_P_2) },
4511   },
4512
4513   /* PREFIX_VEX_0F5C */
4514   {
4515     { VEX_W_TABLE (VEX_W_0F5C_P_0) },
4516     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) },
4517     { VEX_W_TABLE (VEX_W_0F5C_P_2) },
4518     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) },
4519   },
4520
4521   /* PREFIX_VEX_0F5D */
4522   {
4523     { VEX_W_TABLE (VEX_W_0F5D_P_0) },
4524     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) },
4525     { VEX_W_TABLE (VEX_W_0F5D_P_2) },
4526     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) },
4527   },
4528
4529   /* PREFIX_VEX_0F5E */
4530   {
4531     { VEX_W_TABLE (VEX_W_0F5E_P_0) },
4532     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) },
4533     { VEX_W_TABLE (VEX_W_0F5E_P_2) },
4534     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) },
4535   },
4536
4537   /* PREFIX_VEX_0F5F */
4538   {
4539     { VEX_W_TABLE (VEX_W_0F5F_P_0) },
4540     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) },
4541     { VEX_W_TABLE (VEX_W_0F5F_P_2) },
4542     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) },
4543   },
4544
4545   /* PREFIX_VEX_0F60 */
4546   {
4547     { Bad_Opcode },
4548     { Bad_Opcode },
4549     { VEX_W_TABLE (VEX_W_0F60_P_2) },
4550   },
4551
4552   /* PREFIX_VEX_0F61 */
4553   {
4554     { Bad_Opcode },
4555     { Bad_Opcode },
4556     { VEX_W_TABLE (VEX_W_0F61_P_2) },
4557   },
4558
4559   /* PREFIX_VEX_0F62 */
4560   {
4561     { Bad_Opcode },
4562     { Bad_Opcode },
4563     { VEX_W_TABLE (VEX_W_0F62_P_2) },
4564   },
4565
4566   /* PREFIX_VEX_0F63 */
4567   {
4568     { Bad_Opcode },
4569     { Bad_Opcode },
4570     { VEX_W_TABLE (VEX_W_0F63_P_2) },
4571   },
4572
4573   /* PREFIX_VEX_0F64 */
4574   {
4575     { Bad_Opcode },
4576     { Bad_Opcode },
4577     { VEX_W_TABLE (VEX_W_0F64_P_2) },
4578   },
4579
4580   /* PREFIX_VEX_0F65 */
4581   {
4582     { Bad_Opcode },
4583     { Bad_Opcode },
4584     { VEX_W_TABLE (VEX_W_0F65_P_2) },
4585   },
4586
4587   /* PREFIX_VEX_0F66 */
4588   {
4589     { Bad_Opcode },
4590     { Bad_Opcode },
4591     { VEX_W_TABLE (VEX_W_0F66_P_2) },
4592   },
4593
4594   /* PREFIX_VEX_0F67 */
4595   {
4596     { Bad_Opcode },
4597     { Bad_Opcode },
4598     { VEX_W_TABLE (VEX_W_0F67_P_2) },
4599   },
4600
4601   /* PREFIX_VEX_0F68 */
4602   {
4603     { Bad_Opcode },
4604     { Bad_Opcode },
4605     { VEX_W_TABLE (VEX_W_0F68_P_2) },
4606   },
4607
4608   /* PREFIX_VEX_0F69 */
4609   {
4610     { Bad_Opcode },
4611     { Bad_Opcode },
4612     { VEX_W_TABLE (VEX_W_0F69_P_2) },
4613   },
4614
4615   /* PREFIX_VEX_0F6A */
4616   {
4617     { Bad_Opcode },
4618     { Bad_Opcode },
4619     { VEX_W_TABLE (VEX_W_0F6A_P_2) },
4620   },
4621
4622   /* PREFIX_VEX_0F6B */
4623   {
4624     { Bad_Opcode },
4625     { Bad_Opcode },
4626     { VEX_W_TABLE (VEX_W_0F6B_P_2) },
4627   },
4628
4629   /* PREFIX_VEX_0F6C */
4630   {
4631     { Bad_Opcode },
4632     { Bad_Opcode },
4633     { VEX_W_TABLE (VEX_W_0F6C_P_2) },
4634   },
4635
4636   /* PREFIX_VEX_0F6D */
4637   {
4638     { Bad_Opcode },
4639     { Bad_Opcode },
4640     { VEX_W_TABLE (VEX_W_0F6D_P_2) },
4641   },
4642
4643   /* PREFIX_VEX_0F6E */
4644   {
4645     { Bad_Opcode },
4646     { Bad_Opcode },
4647     { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
4648   },
4649
4650   /* PREFIX_VEX_0F6F */
4651   {
4652     { Bad_Opcode },
4653     { VEX_W_TABLE (VEX_W_0F6F_P_1) },
4654     { VEX_W_TABLE (VEX_W_0F6F_P_2) },
4655   },
4656
4657   /* PREFIX_VEX_0F70 */
4658   {
4659     { Bad_Opcode },
4660     { VEX_W_TABLE (VEX_W_0F70_P_1) },
4661     { VEX_W_TABLE (VEX_W_0F70_P_2) },
4662     { VEX_W_TABLE (VEX_W_0F70_P_3) },
4663   },
4664
4665   /* PREFIX_VEX_0F71_REG_2 */
4666   {
4667     { Bad_Opcode },
4668     { Bad_Opcode },
4669     { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) },
4670   },
4671
4672   /* PREFIX_VEX_0F71_REG_4 */
4673   {
4674     { Bad_Opcode },
4675     { Bad_Opcode },
4676     { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) },
4677   },
4678
4679   /* PREFIX_VEX_0F71_REG_6 */
4680   {
4681     { Bad_Opcode },
4682     { Bad_Opcode },
4683     { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) },
4684   },
4685
4686   /* PREFIX_VEX_0F72_REG_2 */
4687   {
4688     { Bad_Opcode },
4689     { Bad_Opcode },
4690     { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) },
4691   },
4692
4693   /* PREFIX_VEX_0F72_REG_4 */
4694   {
4695     { Bad_Opcode },
4696     { Bad_Opcode },
4697     { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) },
4698   },
4699
4700   /* PREFIX_VEX_0F72_REG_6 */
4701   {
4702     { Bad_Opcode },
4703     { Bad_Opcode },
4704     { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) },
4705   },
4706
4707   /* PREFIX_VEX_0F73_REG_2 */
4708   {
4709     { Bad_Opcode },
4710     { Bad_Opcode },
4711     { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) },
4712   },
4713
4714   /* PREFIX_VEX_0F73_REG_3 */
4715   {
4716     { Bad_Opcode },
4717     { Bad_Opcode },
4718     { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) },
4719   },
4720
4721   /* PREFIX_VEX_0F73_REG_6 */
4722   {
4723     { Bad_Opcode },
4724     { Bad_Opcode },
4725     { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) },
4726   },
4727
4728   /* PREFIX_VEX_0F73_REG_7 */
4729   {
4730     { Bad_Opcode },
4731     { Bad_Opcode },
4732     { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) },
4733   },
4734
4735   /* PREFIX_VEX_0F74 */
4736   {
4737     { Bad_Opcode },
4738     { Bad_Opcode },
4739     { VEX_W_TABLE (VEX_W_0F74_P_2) },
4740   },
4741
4742   /* PREFIX_VEX_0F75 */
4743   {
4744     { Bad_Opcode },
4745     { Bad_Opcode },
4746     { VEX_W_TABLE (VEX_W_0F75_P_2) },
4747   },
4748
4749   /* PREFIX_VEX_0F76 */
4750   {
4751     { Bad_Opcode },
4752     { Bad_Opcode },
4753     { VEX_W_TABLE (VEX_W_0F76_P_2) },
4754   },
4755
4756   /* PREFIX_VEX_0F77 */
4757   {
4758     { VEX_W_TABLE (VEX_W_0F77_P_0) },
4759   },
4760
4761   /* PREFIX_VEX_0F7C */
4762   {
4763     { Bad_Opcode },
4764     { Bad_Opcode },
4765     { VEX_W_TABLE (VEX_W_0F7C_P_2) },
4766     { VEX_W_TABLE (VEX_W_0F7C_P_3) },
4767   },
4768
4769   /* PREFIX_VEX_0F7D */
4770   {
4771     { Bad_Opcode },
4772     { Bad_Opcode },
4773     { VEX_W_TABLE (VEX_W_0F7D_P_2) },
4774     { VEX_W_TABLE (VEX_W_0F7D_P_3) },
4775   },
4776
4777   /* PREFIX_VEX_0F7E */
4778   {
4779     { Bad_Opcode },
4780     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
4781     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
4782   },
4783
4784   /* PREFIX_VEX_0F7F */
4785   {
4786     { Bad_Opcode },
4787     { VEX_W_TABLE (VEX_W_0F7F_P_1) },
4788     { VEX_W_TABLE (VEX_W_0F7F_P_2) },
4789   },
4790
4791   /* PREFIX_VEX_0F90 */
4792   {
4793     { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
4794   },
4795
4796   /* PREFIX_VEX_0F91 */
4797   {
4798     { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
4799   },
4800
4801   /* PREFIX_VEX_0F92 */
4802   {
4803     { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
4804   },
4805
4806   /* PREFIX_VEX_0F93 */
4807   {
4808     { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
4809   },
4810
4811   /* PREFIX_VEX_0F98 */
4812   {
4813     { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
4814   },
4815
4816   /* PREFIX_VEX_0FC2 */
4817   {
4818     { VEX_W_TABLE (VEX_W_0FC2_P_0) },
4819     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) },
4820     { VEX_W_TABLE (VEX_W_0FC2_P_2) },
4821     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) },
4822   },
4823
4824   /* PREFIX_VEX_0FC4 */
4825   {
4826     { Bad_Opcode },
4827     { Bad_Opcode },
4828     { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
4829   },
4830
4831   /* PREFIX_VEX_0FC5 */
4832   {
4833     { Bad_Opcode },
4834     { Bad_Opcode },
4835     { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
4836   },
4837
4838   /* PREFIX_VEX_0FD0 */
4839   {
4840     { Bad_Opcode },
4841     { Bad_Opcode },
4842     { VEX_W_TABLE (VEX_W_0FD0_P_2) },
4843     { VEX_W_TABLE (VEX_W_0FD0_P_3) },
4844   },
4845
4846   /* PREFIX_VEX_0FD1 */
4847   {
4848     { Bad_Opcode },
4849     { Bad_Opcode },
4850     { VEX_W_TABLE (VEX_W_0FD1_P_2) },
4851   },
4852
4853   /* PREFIX_VEX_0FD2 */
4854   {
4855     { Bad_Opcode },
4856     { Bad_Opcode },
4857     { VEX_W_TABLE (VEX_W_0FD2_P_2) },
4858   },
4859
4860   /* PREFIX_VEX_0FD3 */
4861   {
4862     { Bad_Opcode },
4863     { Bad_Opcode },
4864     { VEX_W_TABLE (VEX_W_0FD3_P_2) },
4865   },
4866
4867   /* PREFIX_VEX_0FD4 */
4868   {
4869     { Bad_Opcode },
4870     { Bad_Opcode },
4871     { VEX_W_TABLE (VEX_W_0FD4_P_2) },
4872   },
4873
4874   /* PREFIX_VEX_0FD5 */
4875   {
4876     { Bad_Opcode },
4877     { Bad_Opcode },
4878     { VEX_W_TABLE (VEX_W_0FD5_P_2) },
4879   },
4880
4881   /* PREFIX_VEX_0FD6 */
4882   {
4883     { Bad_Opcode },
4884     { Bad_Opcode },
4885     { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
4886   },
4887
4888   /* PREFIX_VEX_0FD7 */
4889   {
4890     { Bad_Opcode },
4891     { Bad_Opcode },
4892     { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
4893   },
4894
4895   /* PREFIX_VEX_0FD8 */
4896   {
4897     { Bad_Opcode },
4898     { Bad_Opcode },
4899     { VEX_W_TABLE (VEX_W_0FD8_P_2) },
4900   },
4901
4902   /* PREFIX_VEX_0FD9 */
4903   {
4904     { Bad_Opcode },
4905     { Bad_Opcode },
4906     { VEX_W_TABLE (VEX_W_0FD9_P_2) },
4907   },
4908
4909   /* PREFIX_VEX_0FDA */
4910   {
4911     { Bad_Opcode },
4912     { Bad_Opcode },
4913     { VEX_W_TABLE (VEX_W_0FDA_P_2) },
4914   },
4915
4916   /* PREFIX_VEX_0FDB */
4917   {
4918     { Bad_Opcode },
4919     { Bad_Opcode },
4920     { VEX_W_TABLE (VEX_W_0FDB_P_2) },
4921   },
4922
4923   /* PREFIX_VEX_0FDC */
4924   {
4925     { Bad_Opcode },
4926     { Bad_Opcode },
4927     { VEX_W_TABLE (VEX_W_0FDC_P_2) },
4928   },
4929
4930   /* PREFIX_VEX_0FDD */
4931   {
4932     { Bad_Opcode },
4933     { Bad_Opcode },
4934     { VEX_W_TABLE (VEX_W_0FDD_P_2) },
4935   },
4936
4937   /* PREFIX_VEX_0FDE */
4938   {
4939     { Bad_Opcode },
4940     { Bad_Opcode },
4941     { VEX_W_TABLE (VEX_W_0FDE_P_2) },
4942   },
4943
4944   /* PREFIX_VEX_0FDF */
4945   {
4946     { Bad_Opcode },
4947     { Bad_Opcode },
4948     { VEX_W_TABLE (VEX_W_0FDF_P_2) },
4949   },
4950
4951   /* PREFIX_VEX_0FE0 */
4952   {
4953     { Bad_Opcode },
4954     { Bad_Opcode },
4955     { VEX_W_TABLE (VEX_W_0FE0_P_2) },
4956   },
4957
4958   /* PREFIX_VEX_0FE1 */
4959   {
4960     { Bad_Opcode },
4961     { Bad_Opcode },
4962     { VEX_W_TABLE (VEX_W_0FE1_P_2) },
4963   },
4964
4965   /* PREFIX_VEX_0FE2 */
4966   {
4967     { Bad_Opcode },
4968     { Bad_Opcode },
4969     { VEX_W_TABLE (VEX_W_0FE2_P_2) },
4970   },
4971
4972   /* PREFIX_VEX_0FE3 */
4973   {
4974     { Bad_Opcode },
4975     { Bad_Opcode },
4976     { VEX_W_TABLE (VEX_W_0FE3_P_2) },
4977   },
4978
4979   /* PREFIX_VEX_0FE4 */
4980   {
4981     { Bad_Opcode },
4982     { Bad_Opcode },
4983     { VEX_W_TABLE (VEX_W_0FE4_P_2) },
4984   },
4985
4986   /* PREFIX_VEX_0FE5 */
4987   {
4988     { Bad_Opcode },
4989     { Bad_Opcode },
4990     { VEX_W_TABLE (VEX_W_0FE5_P_2) },
4991   },
4992
4993   /* PREFIX_VEX_0FE6 */
4994   {
4995     { Bad_Opcode },
4996     { VEX_W_TABLE (VEX_W_0FE6_P_1) },
4997     { VEX_W_TABLE (VEX_W_0FE6_P_2) },
4998     { VEX_W_TABLE (VEX_W_0FE6_P_3) },
4999   },
5000
5001   /* PREFIX_VEX_0FE7 */
5002   {
5003     { Bad_Opcode },
5004     { Bad_Opcode },
5005     { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5006   },
5007
5008   /* PREFIX_VEX_0FE8 */
5009   {
5010     { Bad_Opcode },
5011     { Bad_Opcode },
5012     { VEX_W_TABLE (VEX_W_0FE8_P_2) },
5013   },
5014
5015   /* PREFIX_VEX_0FE9 */
5016   {
5017     { Bad_Opcode },
5018     { Bad_Opcode },
5019     { VEX_W_TABLE (VEX_W_0FE9_P_2) },
5020   },
5021
5022   /* PREFIX_VEX_0FEA */
5023   {
5024     { Bad_Opcode },
5025     { Bad_Opcode },
5026     { VEX_W_TABLE (VEX_W_0FEA_P_2) },
5027   },
5028
5029   /* PREFIX_VEX_0FEB */
5030   {
5031     { Bad_Opcode },
5032     { Bad_Opcode },
5033     { VEX_W_TABLE (VEX_W_0FEB_P_2) },
5034   },
5035
5036   /* PREFIX_VEX_0FEC */
5037   {
5038     { Bad_Opcode },
5039     { Bad_Opcode },
5040     { VEX_W_TABLE (VEX_W_0FEC_P_2) },
5041   },
5042
5043   /* PREFIX_VEX_0FED */
5044   {
5045     { Bad_Opcode },
5046     { Bad_Opcode },
5047     { VEX_W_TABLE (VEX_W_0FED_P_2) },
5048   },
5049
5050   /* PREFIX_VEX_0FEE */
5051   {
5052     { Bad_Opcode },
5053     { Bad_Opcode },
5054     { VEX_W_TABLE (VEX_W_0FEE_P_2) },
5055   },
5056
5057   /* PREFIX_VEX_0FEF */
5058   {
5059     { Bad_Opcode },
5060     { Bad_Opcode },
5061     { VEX_W_TABLE (VEX_W_0FEF_P_2) },
5062   },
5063
5064   /* PREFIX_VEX_0FF0 */
5065   {
5066     { Bad_Opcode },
5067     { Bad_Opcode },
5068     { Bad_Opcode },
5069     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5070   },
5071
5072   /* PREFIX_VEX_0FF1 */
5073   {
5074     { Bad_Opcode },
5075     { Bad_Opcode },
5076     { VEX_W_TABLE (VEX_W_0FF1_P_2) },
5077   },
5078
5079   /* PREFIX_VEX_0FF2 */
5080   {
5081     { Bad_Opcode },
5082     { Bad_Opcode },
5083     { VEX_W_TABLE (VEX_W_0FF2_P_2) },
5084   },
5085
5086   /* PREFIX_VEX_0FF3 */
5087   {
5088     { Bad_Opcode },
5089     { Bad_Opcode },
5090     { VEX_W_TABLE (VEX_W_0FF3_P_2) },
5091   },
5092
5093   /* PREFIX_VEX_0FF4 */
5094   {
5095     { Bad_Opcode },
5096     { Bad_Opcode },
5097     { VEX_W_TABLE (VEX_W_0FF4_P_2) },
5098   },
5099
5100   /* PREFIX_VEX_0FF5 */
5101   {
5102     { Bad_Opcode },
5103     { Bad_Opcode },
5104     { VEX_W_TABLE (VEX_W_0FF5_P_2) },
5105   },
5106
5107   /* PREFIX_VEX_0FF6 */
5108   {
5109     { Bad_Opcode },
5110     { Bad_Opcode },
5111     { VEX_W_TABLE (VEX_W_0FF6_P_2) },
5112   },
5113
5114   /* PREFIX_VEX_0FF7 */
5115   {
5116     { Bad_Opcode },
5117     { Bad_Opcode },
5118     { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5119   },
5120
5121   /* PREFIX_VEX_0FF8 */
5122   {
5123     { Bad_Opcode },
5124     { Bad_Opcode },
5125     { VEX_W_TABLE (VEX_W_0FF8_P_2) },
5126   },
5127
5128   /* PREFIX_VEX_0FF9 */
5129   {
5130     { Bad_Opcode },
5131     { Bad_Opcode },
5132     { VEX_W_TABLE (VEX_W_0FF9_P_2) },
5133   },
5134
5135   /* PREFIX_VEX_0FFA */
5136   {
5137     { Bad_Opcode },
5138     { Bad_Opcode },
5139     { VEX_W_TABLE (VEX_W_0FFA_P_2) },
5140   },
5141
5142   /* PREFIX_VEX_0FFB */
5143   {
5144     { Bad_Opcode },
5145     { Bad_Opcode },
5146     { VEX_W_TABLE (VEX_W_0FFB_P_2) },
5147   },
5148
5149   /* PREFIX_VEX_0FFC */
5150   {
5151     { Bad_Opcode },
5152     { Bad_Opcode },
5153     { VEX_W_TABLE (VEX_W_0FFC_P_2) },
5154   },
5155
5156   /* PREFIX_VEX_0FFD */
5157   {
5158     { Bad_Opcode },
5159     { Bad_Opcode },
5160     { VEX_W_TABLE (VEX_W_0FFD_P_2) },
5161   },
5162
5163   /* PREFIX_VEX_0FFE */
5164   {
5165     { Bad_Opcode },
5166     { Bad_Opcode },
5167     { VEX_W_TABLE (VEX_W_0FFE_P_2) },
5168   },
5169
5170   /* PREFIX_VEX_0F3800 */
5171   {
5172     { Bad_Opcode },
5173     { Bad_Opcode },
5174     { VEX_W_TABLE (VEX_W_0F3800_P_2) },
5175   },
5176
5177   /* PREFIX_VEX_0F3801 */
5178   {
5179     { Bad_Opcode },
5180     { Bad_Opcode },
5181     { VEX_W_TABLE (VEX_W_0F3801_P_2) },
5182   },
5183
5184   /* PREFIX_VEX_0F3802 */
5185   {
5186     { Bad_Opcode },
5187     { Bad_Opcode },
5188     { VEX_W_TABLE (VEX_W_0F3802_P_2) },
5189   },
5190
5191   /* PREFIX_VEX_0F3803 */
5192   {
5193     { Bad_Opcode },
5194     { Bad_Opcode },
5195     { VEX_W_TABLE (VEX_W_0F3803_P_2) },
5196   },
5197
5198   /* PREFIX_VEX_0F3804 */
5199   {
5200     { Bad_Opcode },
5201     { Bad_Opcode },
5202     { VEX_W_TABLE (VEX_W_0F3804_P_2) },
5203   },
5204
5205   /* PREFIX_VEX_0F3805 */
5206   {
5207     { Bad_Opcode },
5208     { Bad_Opcode },
5209     { VEX_W_TABLE (VEX_W_0F3805_P_2) },
5210   },
5211
5212   /* PREFIX_VEX_0F3806 */
5213   {
5214     { Bad_Opcode },
5215     { Bad_Opcode },
5216     { VEX_W_TABLE (VEX_W_0F3806_P_2) },
5217   },
5218
5219   /* PREFIX_VEX_0F3807 */
5220   {
5221     { Bad_Opcode },
5222     { Bad_Opcode },
5223     { VEX_W_TABLE (VEX_W_0F3807_P_2) },
5224   },
5225
5226   /* PREFIX_VEX_0F3808 */
5227   {
5228     { Bad_Opcode },
5229     { Bad_Opcode },
5230     { VEX_W_TABLE (VEX_W_0F3808_P_2) },
5231   },
5232
5233   /* PREFIX_VEX_0F3809 */
5234   {
5235     { Bad_Opcode },
5236     { Bad_Opcode },
5237     { VEX_W_TABLE (VEX_W_0F3809_P_2) },
5238   },
5239
5240   /* PREFIX_VEX_0F380A */
5241   {
5242     { Bad_Opcode },
5243     { Bad_Opcode },
5244     { VEX_W_TABLE (VEX_W_0F380A_P_2) },
5245   },
5246
5247   /* PREFIX_VEX_0F380B */
5248   {
5249     { Bad_Opcode },
5250     { Bad_Opcode },
5251     { VEX_W_TABLE (VEX_W_0F380B_P_2) },
5252   },
5253
5254   /* PREFIX_VEX_0F380C */
5255   {
5256     { Bad_Opcode },
5257     { Bad_Opcode },
5258     { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5259   },
5260
5261   /* PREFIX_VEX_0F380D */
5262   {
5263     { Bad_Opcode },
5264     { Bad_Opcode },
5265     { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5266   },
5267
5268   /* PREFIX_VEX_0F380E */
5269   {
5270     { Bad_Opcode },
5271     { Bad_Opcode },
5272     { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5273   },
5274
5275   /* PREFIX_VEX_0F380F */
5276   {
5277     { Bad_Opcode },
5278     { Bad_Opcode },
5279     { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5280   },
5281
5282   /* PREFIX_VEX_0F3813 */
5283   {
5284     { Bad_Opcode },
5285     { Bad_Opcode },
5286     { "vcvtph2ps", { XM, EXxmmq } },
5287   },
5288
5289   /* PREFIX_VEX_0F3816 */
5290   {
5291     { Bad_Opcode },
5292     { Bad_Opcode },
5293     { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5294   },
5295
5296   /* PREFIX_VEX_0F3817 */
5297   {
5298     { Bad_Opcode },
5299     { Bad_Opcode },
5300     { VEX_W_TABLE (VEX_W_0F3817_P_2) },
5301   },
5302
5303   /* PREFIX_VEX_0F3818 */
5304   {
5305     { Bad_Opcode },
5306     { Bad_Opcode },
5307     { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5308   },
5309
5310   /* PREFIX_VEX_0F3819 */
5311   {
5312     { Bad_Opcode },
5313     { Bad_Opcode },
5314     { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5315   },
5316
5317   /* PREFIX_VEX_0F381A */
5318   {
5319     { Bad_Opcode },
5320     { Bad_Opcode },
5321     { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5322   },
5323
5324   /* PREFIX_VEX_0F381C */
5325   {
5326     { Bad_Opcode },
5327     { Bad_Opcode },
5328     { VEX_W_TABLE (VEX_W_0F381C_P_2) },
5329   },
5330
5331   /* PREFIX_VEX_0F381D */
5332   {
5333     { Bad_Opcode },
5334     { Bad_Opcode },
5335     { VEX_W_TABLE (VEX_W_0F381D_P_2) },
5336   },
5337
5338   /* PREFIX_VEX_0F381E */
5339   {
5340     { Bad_Opcode },
5341     { Bad_Opcode },
5342     { VEX_W_TABLE (VEX_W_0F381E_P_2) },
5343   },
5344
5345   /* PREFIX_VEX_0F3820 */
5346   {
5347     { Bad_Opcode },
5348     { Bad_Opcode },
5349     { VEX_W_TABLE (VEX_W_0F3820_P_2) },
5350   },
5351
5352   /* PREFIX_VEX_0F3821 */
5353   {
5354     { Bad_Opcode },
5355     { Bad_Opcode },
5356     { VEX_W_TABLE (VEX_W_0F3821_P_2) },
5357   },
5358
5359   /* PREFIX_VEX_0F3822 */
5360   {
5361     { Bad_Opcode },
5362     { Bad_Opcode },
5363     { VEX_W_TABLE (VEX_W_0F3822_P_2) },
5364   },
5365
5366   /* PREFIX_VEX_0F3823 */
5367   {
5368     { Bad_Opcode },
5369     { Bad_Opcode },
5370     { VEX_W_TABLE (VEX_W_0F3823_P_2) },
5371   },
5372
5373   /* PREFIX_VEX_0F3824 */
5374   {
5375     { Bad_Opcode },
5376     { Bad_Opcode },
5377     { VEX_W_TABLE (VEX_W_0F3824_P_2) },
5378   },
5379
5380   /* PREFIX_VEX_0F3825 */
5381   {
5382     { Bad_Opcode },
5383     { Bad_Opcode },
5384     { VEX_W_TABLE (VEX_W_0F3825_P_2) },
5385   },
5386
5387   /* PREFIX_VEX_0F3828 */
5388   {
5389     { Bad_Opcode },
5390     { Bad_Opcode },
5391     { VEX_W_TABLE (VEX_W_0F3828_P_2) },
5392   },
5393
5394   /* PREFIX_VEX_0F3829 */
5395   {
5396     { Bad_Opcode },
5397     { Bad_Opcode },
5398     { VEX_W_TABLE (VEX_W_0F3829_P_2) },
5399   },
5400
5401   /* PREFIX_VEX_0F382A */
5402   {
5403     { Bad_Opcode },
5404     { Bad_Opcode },
5405     { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5406   },
5407
5408   /* PREFIX_VEX_0F382B */
5409   {
5410     { Bad_Opcode },
5411     { Bad_Opcode },
5412     { VEX_W_TABLE (VEX_W_0F382B_P_2) },
5413   },
5414
5415   /* PREFIX_VEX_0F382C */
5416   {
5417     { Bad_Opcode },
5418     { Bad_Opcode },
5419      { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5420   },
5421
5422   /* PREFIX_VEX_0F382D */
5423   {
5424     { Bad_Opcode },
5425     { Bad_Opcode },
5426      { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5427   },
5428
5429   /* PREFIX_VEX_0F382E */
5430   {
5431     { Bad_Opcode },
5432     { Bad_Opcode },
5433      { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5434   },
5435
5436   /* PREFIX_VEX_0F382F */
5437   {
5438     { Bad_Opcode },
5439     { Bad_Opcode },
5440      { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5441   },
5442
5443   /* PREFIX_VEX_0F3830 */
5444   {
5445     { Bad_Opcode },
5446     { Bad_Opcode },
5447     { VEX_W_TABLE (VEX_W_0F3830_P_2) },
5448   },
5449
5450   /* PREFIX_VEX_0F3831 */
5451   {
5452     { Bad_Opcode },
5453     { Bad_Opcode },
5454     { VEX_W_TABLE (VEX_W_0F3831_P_2) },
5455   },
5456
5457   /* PREFIX_VEX_0F3832 */
5458   {
5459     { Bad_Opcode },
5460     { Bad_Opcode },
5461     { VEX_W_TABLE (VEX_W_0F3832_P_2) },
5462   },
5463
5464   /* PREFIX_VEX_0F3833 */
5465   {
5466     { Bad_Opcode },
5467     { Bad_Opcode },
5468     { VEX_W_TABLE (VEX_W_0F3833_P_2) },
5469   },
5470
5471   /* PREFIX_VEX_0F3834 */
5472   {
5473     { Bad_Opcode },
5474     { Bad_Opcode },
5475     { VEX_W_TABLE (VEX_W_0F3834_P_2) },
5476   },
5477
5478   /* PREFIX_VEX_0F3835 */
5479   {
5480     { Bad_Opcode },
5481     { Bad_Opcode },
5482     { VEX_W_TABLE (VEX_W_0F3835_P_2) },
5483   },
5484
5485   /* PREFIX_VEX_0F3836 */
5486   {
5487     { Bad_Opcode },
5488     { Bad_Opcode },
5489     { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5490   },
5491
5492   /* PREFIX_VEX_0F3837 */
5493   {
5494     { Bad_Opcode },
5495     { Bad_Opcode },
5496     { VEX_W_TABLE (VEX_W_0F3837_P_2) },
5497   },
5498
5499   /* PREFIX_VEX_0F3838 */
5500   {
5501     { Bad_Opcode },
5502     { Bad_Opcode },
5503     { VEX_W_TABLE (VEX_W_0F3838_P_2) },
5504   },
5505
5506   /* PREFIX_VEX_0F3839 */
5507   {
5508     { Bad_Opcode },
5509     { Bad_Opcode },
5510     { VEX_W_TABLE (VEX_W_0F3839_P_2) },
5511   },
5512
5513   /* PREFIX_VEX_0F383A */
5514   {
5515     { Bad_Opcode },
5516     { Bad_Opcode },
5517     { VEX_W_TABLE (VEX_W_0F383A_P_2) },
5518   },
5519
5520   /* PREFIX_VEX_0F383B */
5521   {
5522     { Bad_Opcode },
5523     { Bad_Opcode },
5524     { VEX_W_TABLE (VEX_W_0F383B_P_2) },
5525   },
5526
5527   /* PREFIX_VEX_0F383C */
5528   {
5529     { Bad_Opcode },
5530     { Bad_Opcode },
5531     { VEX_W_TABLE (VEX_W_0F383C_P_2) },
5532   },
5533
5534   /* PREFIX_VEX_0F383D */
5535   {
5536     { Bad_Opcode },
5537     { Bad_Opcode },
5538     { VEX_W_TABLE (VEX_W_0F383D_P_2) },
5539   },
5540
5541   /* PREFIX_VEX_0F383E */
5542   {
5543     { Bad_Opcode },
5544     { Bad_Opcode },
5545     { VEX_W_TABLE (VEX_W_0F383E_P_2) },
5546   },
5547
5548   /* PREFIX_VEX_0F383F */
5549   {
5550     { Bad_Opcode },
5551     { Bad_Opcode },
5552     { VEX_W_TABLE (VEX_W_0F383F_P_2) },
5553   },
5554
5555   /* PREFIX_VEX_0F3840 */
5556   {
5557     { Bad_Opcode },
5558     { Bad_Opcode },
5559     { VEX_W_TABLE (VEX_W_0F3840_P_2) },
5560   },
5561
5562   /* PREFIX_VEX_0F3841 */
5563   {
5564     { Bad_Opcode },
5565     { Bad_Opcode },
5566     { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
5567   },
5568
5569   /* PREFIX_VEX_0F3845 */
5570   {
5571     { Bad_Opcode },
5572     { Bad_Opcode },
5573     { "vpsrlv%LW", { XM, Vex, EXx } },
5574   },
5575
5576   /* PREFIX_VEX_0F3846 */
5577   {
5578     { Bad_Opcode },
5579     { Bad_Opcode },
5580     { VEX_W_TABLE (VEX_W_0F3846_P_2) },
5581   },
5582
5583   /* PREFIX_VEX_0F3847 */
5584   {
5585     { Bad_Opcode },
5586     { Bad_Opcode },
5587     { "vpsllv%LW", { XM, Vex, EXx } },
5588   },
5589
5590   /* PREFIX_VEX_0F3858 */
5591   {
5592     { Bad_Opcode },
5593     { Bad_Opcode },
5594     { VEX_W_TABLE (VEX_W_0F3858_P_2) },
5595   },
5596
5597   /* PREFIX_VEX_0F3859 */
5598   {
5599     { Bad_Opcode },
5600     { Bad_Opcode },
5601     { VEX_W_TABLE (VEX_W_0F3859_P_2) },
5602   },
5603
5604   /* PREFIX_VEX_0F385A */
5605   {
5606     { Bad_Opcode },
5607     { Bad_Opcode },
5608     { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
5609   },
5610
5611   /* PREFIX_VEX_0F3878 */
5612   {
5613     { Bad_Opcode },
5614     { Bad_Opcode },
5615     { VEX_W_TABLE (VEX_W_0F3878_P_2) },
5616   },
5617
5618   /* PREFIX_VEX_0F3879 */
5619   {
5620     { Bad_Opcode },
5621     { Bad_Opcode },
5622     { VEX_W_TABLE (VEX_W_0F3879_P_2) },
5623   },
5624
5625   /* PREFIX_VEX_0F388C */
5626   {
5627     { Bad_Opcode },
5628     { Bad_Opcode },
5629     { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
5630   },
5631
5632   /* PREFIX_VEX_0F388E */
5633   {
5634     { Bad_Opcode },
5635     { Bad_Opcode },
5636     { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
5637   },
5638
5639   /* PREFIX_VEX_0F3890 */
5640   {
5641     { Bad_Opcode },
5642     { Bad_Opcode },
5643     { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex } },
5644   },
5645
5646   /* PREFIX_VEX_0F3891 */
5647   {
5648     { Bad_Opcode },
5649     { Bad_Opcode },
5650     { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ } },
5651   },
5652
5653   /* PREFIX_VEX_0F3892 */
5654   {
5655     { Bad_Opcode },
5656     { Bad_Opcode },
5657     { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex } },
5658   },
5659
5660   /* PREFIX_VEX_0F3893 */
5661   {
5662     { Bad_Opcode },
5663     { Bad_Opcode },
5664     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ } },
5665   },
5666
5667   /* PREFIX_VEX_0F3896 */
5668   {
5669     { Bad_Opcode },
5670     { Bad_Opcode },
5671     { "vfmaddsub132p%XW", { XM, Vex, EXx } },
5672   },
5673
5674   /* PREFIX_VEX_0F3897 */
5675   {
5676     { Bad_Opcode },
5677     { Bad_Opcode },
5678     { "vfmsubadd132p%XW", { XM, Vex, EXx } },
5679   },
5680
5681   /* PREFIX_VEX_0F3898 */
5682   {
5683     { Bad_Opcode },
5684     { Bad_Opcode },
5685     { "vfmadd132p%XW", { XM, Vex, EXx } },
5686   },
5687
5688   /* PREFIX_VEX_0F3899 */
5689   {
5690     { Bad_Opcode },
5691     { Bad_Opcode },
5692     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5693   },
5694
5695   /* PREFIX_VEX_0F389A */
5696   {
5697     { Bad_Opcode },
5698     { Bad_Opcode },
5699     { "vfmsub132p%XW", { XM, Vex, EXx } },
5700   },
5701
5702   /* PREFIX_VEX_0F389B */
5703   {
5704     { Bad_Opcode },
5705     { Bad_Opcode },
5706     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5707   },
5708
5709   /* PREFIX_VEX_0F389C */
5710   {
5711     { Bad_Opcode },
5712     { Bad_Opcode },
5713     { "vfnmadd132p%XW", { XM, Vex, EXx } },
5714   },
5715
5716   /* PREFIX_VEX_0F389D */
5717   {
5718     { Bad_Opcode },
5719     { Bad_Opcode },
5720     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5721   },
5722
5723   /* PREFIX_VEX_0F389E */
5724   {
5725     { Bad_Opcode },
5726     { Bad_Opcode },
5727     { "vfnmsub132p%XW", { XM, Vex, EXx } },
5728   },
5729
5730   /* PREFIX_VEX_0F389F */
5731   {
5732     { Bad_Opcode },
5733     { Bad_Opcode },
5734     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5735   },
5736
5737   /* PREFIX_VEX_0F38A6 */
5738   {
5739     { Bad_Opcode },
5740     { Bad_Opcode },
5741     { "vfmaddsub213p%XW", { XM, Vex, EXx } },
5742     { Bad_Opcode },
5743   },
5744
5745   /* PREFIX_VEX_0F38A7 */
5746   {
5747     { Bad_Opcode },
5748     { Bad_Opcode },
5749     { "vfmsubadd213p%XW", { XM, Vex, EXx } },
5750   },
5751
5752   /* PREFIX_VEX_0F38A8 */
5753   {
5754     { Bad_Opcode },
5755     { Bad_Opcode },
5756     { "vfmadd213p%XW", { XM, Vex, EXx } },
5757   },
5758
5759   /* PREFIX_VEX_0F38A9 */
5760   {
5761     { Bad_Opcode },
5762     { Bad_Opcode },
5763     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5764   },
5765
5766   /* PREFIX_VEX_0F38AA */
5767   {
5768     { Bad_Opcode },
5769     { Bad_Opcode },
5770     { "vfmsub213p%XW", { XM, Vex, EXx } },
5771   },
5772
5773   /* PREFIX_VEX_0F38AB */
5774   {
5775     { Bad_Opcode },
5776     { Bad_Opcode },
5777     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5778   },
5779
5780   /* PREFIX_VEX_0F38AC */
5781   {
5782     { Bad_Opcode },
5783     { Bad_Opcode },
5784     { "vfnmadd213p%XW", { XM, Vex, EXx } },
5785   },
5786
5787   /* PREFIX_VEX_0F38AD */
5788   {
5789     { Bad_Opcode },
5790     { Bad_Opcode },
5791     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5792   },
5793
5794   /* PREFIX_VEX_0F38AE */
5795   {
5796     { Bad_Opcode },
5797     { Bad_Opcode },
5798     { "vfnmsub213p%XW", { XM, Vex, EXx } },
5799   },
5800
5801   /* PREFIX_VEX_0F38AF */
5802   {
5803     { Bad_Opcode },
5804     { Bad_Opcode },
5805     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5806   },
5807
5808   /* PREFIX_VEX_0F38B6 */
5809   {
5810     { Bad_Opcode },
5811     { Bad_Opcode },
5812     { "vfmaddsub231p%XW", { XM, Vex, EXx } },
5813   },
5814
5815   /* PREFIX_VEX_0F38B7 */
5816   {
5817     { Bad_Opcode },
5818     { Bad_Opcode },
5819     { "vfmsubadd231p%XW", { XM, Vex, EXx } },
5820   },
5821
5822   /* PREFIX_VEX_0F38B8 */
5823   {
5824     { Bad_Opcode },
5825     { Bad_Opcode },
5826     { "vfmadd231p%XW", { XM, Vex, EXx } },
5827   },
5828
5829   /* PREFIX_VEX_0F38B9 */
5830   {
5831     { Bad_Opcode },
5832     { Bad_Opcode },
5833     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5834   },
5835
5836   /* PREFIX_VEX_0F38BA */
5837   {
5838     { Bad_Opcode },
5839     { Bad_Opcode },
5840     { "vfmsub231p%XW", { XM, Vex, EXx } },
5841   },
5842
5843   /* PREFIX_VEX_0F38BB */
5844   {
5845     { Bad_Opcode },
5846     { Bad_Opcode },
5847     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5848   },
5849
5850   /* PREFIX_VEX_0F38BC */
5851   {
5852     { Bad_Opcode },
5853     { Bad_Opcode },
5854     { "vfnmadd231p%XW", { XM, Vex, EXx } },
5855   },
5856
5857   /* PREFIX_VEX_0F38BD */
5858   {
5859     { Bad_Opcode },
5860     { Bad_Opcode },
5861     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5862   },
5863
5864   /* PREFIX_VEX_0F38BE */
5865   {
5866     { Bad_Opcode },
5867     { Bad_Opcode },
5868     { "vfnmsub231p%XW", { XM, Vex, EXx } },
5869   },
5870
5871   /* PREFIX_VEX_0F38BF */
5872   {
5873     { Bad_Opcode },
5874     { Bad_Opcode },
5875     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5876   },
5877
5878   /* PREFIX_VEX_0F38DB */
5879   {
5880     { Bad_Opcode },
5881     { Bad_Opcode },
5882     { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
5883   },
5884
5885   /* PREFIX_VEX_0F38DC */
5886   {
5887     { Bad_Opcode },
5888     { Bad_Opcode },
5889     { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2) },
5890   },
5891
5892   /* PREFIX_VEX_0F38DD */
5893   {
5894     { Bad_Opcode },
5895     { Bad_Opcode },
5896     { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2) },
5897   },
5898
5899   /* PREFIX_VEX_0F38DE */
5900   {
5901     { Bad_Opcode },
5902     { Bad_Opcode },
5903     { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2) },
5904   },
5905
5906   /* PREFIX_VEX_0F38DF */
5907   {
5908     { Bad_Opcode },
5909     { Bad_Opcode },
5910     { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2) },
5911   },
5912
5913   /* PREFIX_VEX_0F38F2 */
5914   {
5915     { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
5916   },
5917
5918   /* PREFIX_VEX_0F38F3_REG_1 */
5919   {
5920     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
5921   },
5922
5923   /* PREFIX_VEX_0F38F3_REG_2 */
5924   {
5925     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
5926   },
5927
5928   /* PREFIX_VEX_0F38F3_REG_3 */
5929   {
5930     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
5931   },
5932
5933   /* PREFIX_VEX_0F38F5 */
5934   {
5935     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
5936     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
5937     { Bad_Opcode },
5938     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
5939   },
5940
5941   /* PREFIX_VEX_0F38F6 */
5942   {
5943     { Bad_Opcode },
5944     { Bad_Opcode },
5945     { Bad_Opcode },
5946     { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
5947   },
5948
5949   /* PREFIX_VEX_0F38F7 */
5950   {
5951     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
5952     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
5953     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
5954     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
5955   },
5956
5957   /* PREFIX_VEX_0F3A00 */
5958   {
5959     { Bad_Opcode },
5960     { Bad_Opcode },
5961     { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
5962   },
5963
5964   /* PREFIX_VEX_0F3A01 */
5965   {
5966     { Bad_Opcode },
5967     { Bad_Opcode },
5968     { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
5969   },
5970
5971   /* PREFIX_VEX_0F3A02 */
5972   {
5973     { Bad_Opcode },
5974     { Bad_Opcode },
5975     { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
5976   },
5977
5978   /* PREFIX_VEX_0F3A04 */
5979   {
5980     { Bad_Opcode },
5981     { Bad_Opcode },
5982     { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
5983   },
5984
5985   /* PREFIX_VEX_0F3A05 */
5986   {
5987     { Bad_Opcode },
5988     { Bad_Opcode },
5989     { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
5990   },
5991
5992   /* PREFIX_VEX_0F3A06 */
5993   {
5994     { Bad_Opcode },
5995     { Bad_Opcode },
5996     { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
5997   },
5998
5999   /* PREFIX_VEX_0F3A08 */
6000   {
6001     { Bad_Opcode },
6002     { Bad_Opcode },
6003     { VEX_W_TABLE (VEX_W_0F3A08_P_2) },
6004   },
6005
6006   /* PREFIX_VEX_0F3A09 */
6007   {
6008     { Bad_Opcode },
6009     { Bad_Opcode },
6010     { VEX_W_TABLE (VEX_W_0F3A09_P_2) },
6011   },
6012
6013   /* PREFIX_VEX_0F3A0A */
6014   {
6015     { Bad_Opcode },
6016     { Bad_Opcode },
6017     { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) },
6018   },
6019
6020   /* PREFIX_VEX_0F3A0B */
6021   {
6022     { Bad_Opcode },
6023     { Bad_Opcode },
6024     { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) },
6025   },
6026
6027   /* PREFIX_VEX_0F3A0C */
6028   {
6029     { Bad_Opcode },
6030     { Bad_Opcode },
6031     { VEX_W_TABLE (VEX_W_0F3A0C_P_2) },
6032   },
6033
6034   /* PREFIX_VEX_0F3A0D */
6035   {
6036     { Bad_Opcode },
6037     { Bad_Opcode },
6038     { VEX_W_TABLE (VEX_W_0F3A0D_P_2) },
6039   },
6040
6041   /* PREFIX_VEX_0F3A0E */
6042   {
6043     { Bad_Opcode },
6044     { Bad_Opcode },
6045     { VEX_W_TABLE (VEX_W_0F3A0E_P_2) },
6046   },
6047
6048   /* PREFIX_VEX_0F3A0F */
6049   {
6050     { Bad_Opcode },
6051     { Bad_Opcode },
6052     { VEX_W_TABLE (VEX_W_0F3A0F_P_2) },
6053   },
6054
6055   /* PREFIX_VEX_0F3A14 */
6056   {
6057     { Bad_Opcode },
6058     { Bad_Opcode },
6059     { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6060   },
6061
6062   /* PREFIX_VEX_0F3A15 */
6063   {
6064     { Bad_Opcode },
6065     { Bad_Opcode },
6066     { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6067   },
6068
6069   /* PREFIX_VEX_0F3A16 */
6070   {
6071     { Bad_Opcode },
6072     { Bad_Opcode },
6073     { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6074   },
6075
6076   /* PREFIX_VEX_0F3A17 */
6077   {
6078     { Bad_Opcode },
6079     { Bad_Opcode },
6080     { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6081   },
6082
6083   /* PREFIX_VEX_0F3A18 */
6084   {
6085     { Bad_Opcode },
6086     { Bad_Opcode },
6087     { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6088   },
6089
6090   /* PREFIX_VEX_0F3A19 */
6091   {
6092     { Bad_Opcode },
6093     { Bad_Opcode },
6094     { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6095   },
6096
6097   /* PREFIX_VEX_0F3A1D */
6098   {
6099     { Bad_Opcode },
6100     { Bad_Opcode },
6101     { "vcvtps2ph", { EXxmmq, XM, Ib } },
6102   },
6103
6104   /* PREFIX_VEX_0F3A20 */
6105   {
6106     { Bad_Opcode },
6107     { Bad_Opcode },
6108     { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6109   },
6110
6111   /* PREFIX_VEX_0F3A21 */
6112   {
6113     { Bad_Opcode },
6114     { Bad_Opcode },
6115     { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6116   },
6117
6118   /* PREFIX_VEX_0F3A22 */
6119   {
6120     { Bad_Opcode },
6121     { Bad_Opcode },
6122     { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6123   },
6124
6125   /* PREFIX_VEX_0F3A30 */
6126   {
6127     { Bad_Opcode },
6128     { Bad_Opcode },
6129     { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6130   },
6131
6132   /* PREFIX_VEX_0F3A32 */
6133   {
6134     { Bad_Opcode },
6135     { Bad_Opcode },
6136     { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6137   },
6138
6139   /* PREFIX_VEX_0F3A38 */
6140   {
6141     { Bad_Opcode },
6142     { Bad_Opcode },
6143     { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6144   },
6145
6146   /* PREFIX_VEX_0F3A39 */
6147   {
6148     { Bad_Opcode },
6149     { Bad_Opcode },
6150     { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6151   },
6152
6153   /* PREFIX_VEX_0F3A40 */
6154   {
6155     { Bad_Opcode },
6156     { Bad_Opcode },
6157     { VEX_W_TABLE (VEX_W_0F3A40_P_2) },
6158   },
6159
6160   /* PREFIX_VEX_0F3A41 */
6161   {
6162     { Bad_Opcode },
6163     { Bad_Opcode },
6164     { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6165   },
6166
6167   /* PREFIX_VEX_0F3A42 */
6168   {
6169     { Bad_Opcode },
6170     { Bad_Opcode },
6171     { VEX_W_TABLE (VEX_W_0F3A42_P_2) },
6172   },
6173
6174   /* PREFIX_VEX_0F3A44 */
6175   {
6176     { Bad_Opcode },
6177     { Bad_Opcode },
6178     { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2) },
6179   },
6180
6181   /* PREFIX_VEX_0F3A46 */
6182   {
6183     { Bad_Opcode },
6184     { Bad_Opcode },
6185     { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6186   },
6187
6188   /* PREFIX_VEX_0F3A48 */
6189   {
6190     { Bad_Opcode },
6191     { Bad_Opcode },
6192     { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6193   },
6194
6195   /* PREFIX_VEX_0F3A49 */
6196   {
6197     { Bad_Opcode },
6198     { Bad_Opcode },
6199     { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6200   },
6201
6202   /* PREFIX_VEX_0F3A4A */
6203   {
6204     { Bad_Opcode },
6205     { Bad_Opcode },
6206     { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6207   },
6208
6209   /* PREFIX_VEX_0F3A4B */
6210   {
6211     { Bad_Opcode },
6212     { Bad_Opcode },
6213     { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6214   },
6215
6216   /* PREFIX_VEX_0F3A4C */
6217   {
6218     { Bad_Opcode },
6219     { Bad_Opcode },
6220     { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6221   },
6222
6223   /* PREFIX_VEX_0F3A5C */
6224   {
6225     { Bad_Opcode },
6226     { Bad_Opcode },
6227     { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6228   },
6229
6230   /* PREFIX_VEX_0F3A5D */
6231   {
6232     { Bad_Opcode },
6233     { Bad_Opcode },
6234     { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6235   },
6236
6237   /* PREFIX_VEX_0F3A5E */
6238   {
6239     { Bad_Opcode },
6240     { Bad_Opcode },
6241     { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6242   },
6243
6244   /* PREFIX_VEX_0F3A5F */
6245   {
6246     { Bad_Opcode },
6247     { Bad_Opcode },
6248     { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6249   },
6250
6251   /* PREFIX_VEX_0F3A60 */
6252   {
6253     { Bad_Opcode },
6254     { Bad_Opcode },
6255     { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6256     { Bad_Opcode },
6257   },
6258
6259   /* PREFIX_VEX_0F3A61 */
6260   {
6261     { Bad_Opcode },
6262     { Bad_Opcode },
6263     { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6264   },
6265
6266   /* PREFIX_VEX_0F3A62 */
6267   {
6268     { Bad_Opcode },
6269     { Bad_Opcode },
6270     { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6271   },
6272
6273   /* PREFIX_VEX_0F3A63 */
6274   {
6275     { Bad_Opcode },
6276     { Bad_Opcode },
6277     { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6278   },
6279
6280   /* PREFIX_VEX_0F3A68 */
6281   {
6282     { Bad_Opcode },
6283     { Bad_Opcode },
6284     { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6285   },
6286
6287   /* PREFIX_VEX_0F3A69 */
6288   {
6289     { Bad_Opcode },
6290     { Bad_Opcode },
6291     { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6292   },
6293
6294   /* PREFIX_VEX_0F3A6A */
6295   {
6296     { Bad_Opcode },
6297     { Bad_Opcode },
6298     { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6299   },
6300
6301   /* PREFIX_VEX_0F3A6B */
6302   {
6303     { Bad_Opcode },
6304     { Bad_Opcode },
6305     { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6306   },
6307
6308   /* PREFIX_VEX_0F3A6C */
6309   {
6310     { Bad_Opcode },
6311     { Bad_Opcode },
6312     { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6313   },
6314
6315   /* PREFIX_VEX_0F3A6D */
6316   {
6317     { Bad_Opcode },
6318     { Bad_Opcode },
6319     { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6320   },
6321
6322   /* PREFIX_VEX_0F3A6E */
6323   {
6324     { Bad_Opcode },
6325     { Bad_Opcode },
6326     { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6327   },
6328
6329   /* PREFIX_VEX_0F3A6F */
6330   {
6331     { Bad_Opcode },
6332     { Bad_Opcode },
6333     { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6334   },
6335
6336   /* PREFIX_VEX_0F3A78 */
6337   {
6338     { Bad_Opcode },
6339     { Bad_Opcode },
6340     { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6341   },
6342
6343   /* PREFIX_VEX_0F3A79 */
6344   {
6345     { Bad_Opcode },
6346     { Bad_Opcode },
6347     { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6348   },
6349
6350   /* PREFIX_VEX_0F3A7A */
6351   {
6352     { Bad_Opcode },
6353     { Bad_Opcode },
6354     { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6355   },
6356
6357   /* PREFIX_VEX_0F3A7B */
6358   {
6359     { Bad_Opcode },
6360     { Bad_Opcode },
6361     { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6362   },
6363
6364   /* PREFIX_VEX_0F3A7C */
6365   {
6366     { Bad_Opcode },
6367     { Bad_Opcode },
6368     { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6369     { Bad_Opcode },
6370   },
6371
6372   /* PREFIX_VEX_0F3A7D */
6373   {
6374     { Bad_Opcode },
6375     { Bad_Opcode },
6376     { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6377   },
6378
6379   /* PREFIX_VEX_0F3A7E */
6380   {
6381     { Bad_Opcode },
6382     { Bad_Opcode },
6383     { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6384   },
6385
6386   /* PREFIX_VEX_0F3A7F */
6387   {
6388     { Bad_Opcode },
6389     { Bad_Opcode },
6390     { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6391   },
6392
6393   /* PREFIX_VEX_0F3ADF */
6394   {
6395     { Bad_Opcode },
6396     { Bad_Opcode },
6397     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6398   },
6399
6400   /* PREFIX_VEX_0F3AF0 */
6401   {
6402     { Bad_Opcode },
6403     { Bad_Opcode },
6404     { Bad_Opcode },
6405     { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6406   },
6407
6408 #define NEED_PREFIX_TABLE
6409 #include "i386-dis-evex.h"
6410 #undef NEED_PREFIX_TABLE
6411 };
6412
6413 static const struct dis386 x86_64_table[][2] = {
6414   /* X86_64_06 */
6415   {
6416     { "pushP", { es } },
6417   },
6418
6419   /* X86_64_07 */
6420   {
6421     { "popP", { es } },
6422   },
6423
6424   /* X86_64_0D */
6425   {
6426     { "pushP", { cs } },
6427   },
6428
6429   /* X86_64_16 */
6430   {
6431     { "pushP", { ss } },
6432   },
6433
6434   /* X86_64_17 */
6435   {
6436     { "popP", { ss } },
6437   },
6438
6439   /* X86_64_1E */
6440   {
6441     { "pushP", { ds } },
6442   },
6443
6444   /* X86_64_1F */
6445   {
6446     { "popP", { ds } },
6447   },
6448
6449   /* X86_64_27 */
6450   {
6451     { "daa", { XX } },
6452   },
6453
6454   /* X86_64_2F */
6455   {
6456     { "das", { XX } },
6457   },
6458
6459   /* X86_64_37 */
6460   {
6461     { "aaa", { XX } },
6462   },
6463
6464   /* X86_64_3F */
6465   {
6466     { "aas", { XX } },
6467   },
6468
6469   /* X86_64_60 */
6470   {
6471     { "pushaP", { XX } },
6472   },
6473
6474   /* X86_64_61 */
6475   {
6476     { "popaP", { XX } },
6477   },
6478
6479   /* X86_64_62 */
6480   {
6481     { MOD_TABLE (MOD_62_32BIT) },
6482     { EVEX_TABLE (EVEX_0F) },
6483   },
6484
6485   /* X86_64_63 */
6486   {
6487     { "arpl", { Ew, Gw } },
6488     { "movs{lq|xd}", { Gv, Ed } },
6489   },
6490
6491   /* X86_64_6D */
6492   {
6493     { "ins{R|}", { Yzr, indirDX } },
6494     { "ins{G|}", { Yzr, indirDX } },
6495   },
6496
6497   /* X86_64_6F */
6498   {
6499     { "outs{R|}", { indirDXr, Xz } },
6500     { "outs{G|}", { indirDXr, Xz } },
6501   },
6502
6503   /* X86_64_9A */
6504   {
6505     { "Jcall{T|}", { Ap } },
6506   },
6507
6508   /* X86_64_C4 */
6509   {
6510     { MOD_TABLE (MOD_C4_32BIT) },
6511     { VEX_C4_TABLE (VEX_0F) },
6512   },
6513
6514   /* X86_64_C5 */
6515   {
6516     { MOD_TABLE (MOD_C5_32BIT) },
6517     { VEX_C5_TABLE (VEX_0F) },
6518   },
6519
6520   /* X86_64_CE */
6521   {
6522     { "into", { XX } },
6523   },
6524
6525   /* X86_64_D4 */
6526   {
6527     { "aam", { Ib } },
6528   },
6529
6530   /* X86_64_D5 */
6531   {
6532     { "aad", { Ib } },
6533   },
6534
6535   /* X86_64_EA */
6536   {
6537     { "Jjmp{T|}", { Ap } },
6538   },
6539
6540   /* X86_64_0F01_REG_0 */
6541   {
6542     { "sgdt{Q|IQ}", { M } },
6543     { "sgdt", { M } },
6544   },
6545
6546   /* X86_64_0F01_REG_1 */
6547   {
6548     { "sidt{Q|IQ}", { M } },
6549     { "sidt", { M } },
6550   },
6551
6552   /* X86_64_0F01_REG_2 */
6553   {
6554     { "lgdt{Q|Q}", { M } },
6555     { "lgdt", { M } },
6556   },
6557
6558   /* X86_64_0F01_REG_3 */
6559   {
6560     { "lidt{Q|Q}", { M } },
6561     { "lidt", { M } },
6562   },
6563 };
6564
6565 static const struct dis386 three_byte_table[][256] = {
6566
6567   /* THREE_BYTE_0F38 */
6568   {
6569     /* 00 */
6570     { "pshufb",         { MX, EM } },
6571     { "phaddw",         { MX, EM } },
6572     { "phaddd",         { MX, EM } },
6573     { "phaddsw",        { MX, EM } },
6574     { "pmaddubsw",      { MX, EM } },
6575     { "phsubw",         { MX, EM } },
6576     { "phsubd",         { MX, EM } },
6577     { "phsubsw",        { MX, EM } },
6578     /* 08 */
6579     { "psignb",         { MX, EM } },
6580     { "psignw",         { MX, EM } },
6581     { "psignd",         { MX, EM } },
6582     { "pmulhrsw",       { MX, EM } },
6583     { Bad_Opcode },
6584     { Bad_Opcode },
6585     { Bad_Opcode },
6586     { Bad_Opcode },
6587     /* 10 */
6588     { PREFIX_TABLE (PREFIX_0F3810) },
6589     { Bad_Opcode },
6590     { Bad_Opcode },
6591     { Bad_Opcode },
6592     { PREFIX_TABLE (PREFIX_0F3814) },
6593     { PREFIX_TABLE (PREFIX_0F3815) },
6594     { Bad_Opcode },
6595     { PREFIX_TABLE (PREFIX_0F3817) },
6596     /* 18 */
6597     { Bad_Opcode },
6598     { Bad_Opcode },
6599     { Bad_Opcode },
6600     { Bad_Opcode },
6601     { "pabsb",          { MX, EM } },
6602     { "pabsw",          { MX, EM } },
6603     { "pabsd",          { MX, EM } },
6604     { Bad_Opcode },
6605     /* 20 */
6606     { PREFIX_TABLE (PREFIX_0F3820) },
6607     { PREFIX_TABLE (PREFIX_0F3821) },
6608     { PREFIX_TABLE (PREFIX_0F3822) },
6609     { PREFIX_TABLE (PREFIX_0F3823) },
6610     { PREFIX_TABLE (PREFIX_0F3824) },
6611     { PREFIX_TABLE (PREFIX_0F3825) },
6612     { Bad_Opcode },
6613     { Bad_Opcode },
6614     /* 28 */
6615     { PREFIX_TABLE (PREFIX_0F3828) },
6616     { PREFIX_TABLE (PREFIX_0F3829) },
6617     { PREFIX_TABLE (PREFIX_0F382A) },
6618     { PREFIX_TABLE (PREFIX_0F382B) },
6619     { Bad_Opcode },
6620     { Bad_Opcode },
6621     { Bad_Opcode },
6622     { Bad_Opcode },
6623     /* 30 */
6624     { PREFIX_TABLE (PREFIX_0F3830) },
6625     { PREFIX_TABLE (PREFIX_0F3831) },
6626     { PREFIX_TABLE (PREFIX_0F3832) },
6627     { PREFIX_TABLE (PREFIX_0F3833) },
6628     { PREFIX_TABLE (PREFIX_0F3834) },
6629     { PREFIX_TABLE (PREFIX_0F3835) },
6630     { Bad_Opcode },
6631     { PREFIX_TABLE (PREFIX_0F3837) },
6632     /* 38 */
6633     { PREFIX_TABLE (PREFIX_0F3838) },
6634     { PREFIX_TABLE (PREFIX_0F3839) },
6635     { PREFIX_TABLE (PREFIX_0F383A) },
6636     { PREFIX_TABLE (PREFIX_0F383B) },
6637     { PREFIX_TABLE (PREFIX_0F383C) },
6638     { PREFIX_TABLE (PREFIX_0F383D) },
6639     { PREFIX_TABLE (PREFIX_0F383E) },
6640     { PREFIX_TABLE (PREFIX_0F383F) },
6641     /* 40 */
6642     { PREFIX_TABLE (PREFIX_0F3840) },
6643     { PREFIX_TABLE (PREFIX_0F3841) },
6644     { Bad_Opcode },
6645     { Bad_Opcode },
6646     { Bad_Opcode },
6647     { Bad_Opcode },
6648     { Bad_Opcode },
6649     { Bad_Opcode },
6650     /* 48 */
6651     { Bad_Opcode },
6652     { Bad_Opcode },
6653     { Bad_Opcode },
6654     { Bad_Opcode },
6655     { Bad_Opcode },
6656     { Bad_Opcode },
6657     { Bad_Opcode },
6658     { Bad_Opcode },
6659     /* 50 */
6660     { Bad_Opcode },
6661     { Bad_Opcode },
6662     { Bad_Opcode },
6663     { Bad_Opcode },
6664     { Bad_Opcode },
6665     { Bad_Opcode },
6666     { Bad_Opcode },
6667     { Bad_Opcode },
6668     /* 58 */
6669     { Bad_Opcode },
6670     { Bad_Opcode },
6671     { Bad_Opcode },
6672     { Bad_Opcode },
6673     { Bad_Opcode },
6674     { Bad_Opcode },
6675     { Bad_Opcode },
6676     { Bad_Opcode },
6677     /* 60 */
6678     { Bad_Opcode },
6679     { Bad_Opcode },
6680     { Bad_Opcode },
6681     { Bad_Opcode },
6682     { Bad_Opcode },
6683     { Bad_Opcode },
6684     { Bad_Opcode },
6685     { Bad_Opcode },
6686     /* 68 */
6687     { Bad_Opcode },
6688     { Bad_Opcode },
6689     { Bad_Opcode },
6690     { Bad_Opcode },
6691     { Bad_Opcode },
6692     { Bad_Opcode },
6693     { Bad_Opcode },
6694     { Bad_Opcode },
6695     /* 70 */
6696     { Bad_Opcode },
6697     { Bad_Opcode },
6698     { Bad_Opcode },
6699     { Bad_Opcode },
6700     { Bad_Opcode },
6701     { Bad_Opcode },
6702     { Bad_Opcode },
6703     { Bad_Opcode },
6704     /* 78 */
6705     { Bad_Opcode },
6706     { Bad_Opcode },
6707     { Bad_Opcode },
6708     { Bad_Opcode },
6709     { Bad_Opcode },
6710     { Bad_Opcode },
6711     { Bad_Opcode },
6712     { Bad_Opcode },
6713     /* 80 */
6714     { PREFIX_TABLE (PREFIX_0F3880) },
6715     { PREFIX_TABLE (PREFIX_0F3881) },
6716     { PREFIX_TABLE (PREFIX_0F3882) },
6717     { Bad_Opcode },
6718     { Bad_Opcode },
6719     { Bad_Opcode },
6720     { Bad_Opcode },
6721     { Bad_Opcode },
6722     /* 88 */
6723     { Bad_Opcode },
6724     { Bad_Opcode },
6725     { Bad_Opcode },
6726     { Bad_Opcode },
6727     { Bad_Opcode },
6728     { Bad_Opcode },
6729     { Bad_Opcode },
6730     { Bad_Opcode },
6731     /* 90 */
6732     { Bad_Opcode },
6733     { Bad_Opcode },
6734     { Bad_Opcode },
6735     { Bad_Opcode },
6736     { Bad_Opcode },
6737     { Bad_Opcode },
6738     { Bad_Opcode },
6739     { Bad_Opcode },
6740     /* 98 */
6741     { Bad_Opcode },
6742     { Bad_Opcode },
6743     { Bad_Opcode },
6744     { Bad_Opcode },
6745     { Bad_Opcode },
6746     { Bad_Opcode },
6747     { Bad_Opcode },
6748     { Bad_Opcode },
6749     /* a0 */
6750     { Bad_Opcode },
6751     { Bad_Opcode },
6752     { Bad_Opcode },
6753     { Bad_Opcode },
6754     { Bad_Opcode },
6755     { Bad_Opcode },
6756     { Bad_Opcode },
6757     { Bad_Opcode },
6758     /* a8 */
6759     { Bad_Opcode },
6760     { Bad_Opcode },
6761     { Bad_Opcode },
6762     { Bad_Opcode },
6763     { Bad_Opcode },
6764     { Bad_Opcode },
6765     { Bad_Opcode },
6766     { Bad_Opcode },
6767     /* b0 */
6768     { Bad_Opcode },
6769     { Bad_Opcode },
6770     { Bad_Opcode },
6771     { Bad_Opcode },
6772     { Bad_Opcode },
6773     { Bad_Opcode },
6774     { Bad_Opcode },
6775     { Bad_Opcode },
6776     /* b8 */
6777     { Bad_Opcode },
6778     { Bad_Opcode },
6779     { Bad_Opcode },
6780     { Bad_Opcode },
6781     { Bad_Opcode },
6782     { Bad_Opcode },
6783     { Bad_Opcode },
6784     { Bad_Opcode },
6785     /* c0 */
6786     { Bad_Opcode },
6787     { Bad_Opcode },
6788     { Bad_Opcode },
6789     { Bad_Opcode },
6790     { Bad_Opcode },
6791     { Bad_Opcode },
6792     { Bad_Opcode },
6793     { Bad_Opcode },
6794     /* c8 */
6795     { PREFIX_TABLE (PREFIX_0F38C8) },
6796     { PREFIX_TABLE (PREFIX_0F38C9) },
6797     { PREFIX_TABLE (PREFIX_0F38CA) },
6798     { PREFIX_TABLE (PREFIX_0F38CB) },
6799     { PREFIX_TABLE (PREFIX_0F38CC) },
6800     { PREFIX_TABLE (PREFIX_0F38CD) },
6801     { Bad_Opcode },
6802     { Bad_Opcode },
6803     /* d0 */
6804     { Bad_Opcode },
6805     { Bad_Opcode },
6806     { Bad_Opcode },
6807     { Bad_Opcode },
6808     { Bad_Opcode },
6809     { Bad_Opcode },
6810     { Bad_Opcode },
6811     { Bad_Opcode },
6812     /* d8 */
6813     { Bad_Opcode },
6814     { Bad_Opcode },
6815     { Bad_Opcode },
6816     { PREFIX_TABLE (PREFIX_0F38DB) },
6817     { PREFIX_TABLE (PREFIX_0F38DC) },
6818     { PREFIX_TABLE (PREFIX_0F38DD) },
6819     { PREFIX_TABLE (PREFIX_0F38DE) },
6820     { PREFIX_TABLE (PREFIX_0F38DF) },
6821     /* e0 */
6822     { Bad_Opcode },
6823     { Bad_Opcode },
6824     { Bad_Opcode },
6825     { Bad_Opcode },
6826     { Bad_Opcode },
6827     { Bad_Opcode },
6828     { Bad_Opcode },
6829     { Bad_Opcode },
6830     /* e8 */
6831     { Bad_Opcode },
6832     { Bad_Opcode },
6833     { Bad_Opcode },
6834     { Bad_Opcode },
6835     { Bad_Opcode },
6836     { Bad_Opcode },
6837     { Bad_Opcode },
6838     { Bad_Opcode },
6839     /* f0 */
6840     { PREFIX_TABLE (PREFIX_0F38F0) },
6841     { PREFIX_TABLE (PREFIX_0F38F1) },
6842     { Bad_Opcode },
6843     { Bad_Opcode },
6844     { Bad_Opcode },
6845     { Bad_Opcode },
6846     { PREFIX_TABLE (PREFIX_0F38F6) },
6847     { Bad_Opcode },
6848     /* f8 */
6849     { Bad_Opcode },
6850     { Bad_Opcode },
6851     { Bad_Opcode },
6852     { Bad_Opcode },
6853     { Bad_Opcode },
6854     { Bad_Opcode },
6855     { Bad_Opcode },
6856     { Bad_Opcode },
6857   },
6858   /* THREE_BYTE_0F3A */
6859   {
6860     /* 00 */
6861     { Bad_Opcode },
6862     { Bad_Opcode },
6863     { Bad_Opcode },
6864     { Bad_Opcode },
6865     { Bad_Opcode },
6866     { Bad_Opcode },
6867     { Bad_Opcode },
6868     { Bad_Opcode },
6869     /* 08 */
6870     { PREFIX_TABLE (PREFIX_0F3A08) },
6871     { PREFIX_TABLE (PREFIX_0F3A09) },
6872     { PREFIX_TABLE (PREFIX_0F3A0A) },
6873     { PREFIX_TABLE (PREFIX_0F3A0B) },
6874     { PREFIX_TABLE (PREFIX_0F3A0C) },
6875     { PREFIX_TABLE (PREFIX_0F3A0D) },
6876     { PREFIX_TABLE (PREFIX_0F3A0E) },
6877     { "palignr",        { MX, EM, Ib } },
6878     /* 10 */
6879     { Bad_Opcode },
6880     { Bad_Opcode },
6881     { Bad_Opcode },
6882     { Bad_Opcode },
6883     { PREFIX_TABLE (PREFIX_0F3A14) },
6884     { PREFIX_TABLE (PREFIX_0F3A15) },
6885     { PREFIX_TABLE (PREFIX_0F3A16) },
6886     { PREFIX_TABLE (PREFIX_0F3A17) },
6887     /* 18 */
6888     { Bad_Opcode },
6889     { Bad_Opcode },
6890     { Bad_Opcode },
6891     { Bad_Opcode },
6892     { Bad_Opcode },
6893     { Bad_Opcode },
6894     { Bad_Opcode },
6895     { Bad_Opcode },
6896     /* 20 */
6897     { PREFIX_TABLE (PREFIX_0F3A20) },
6898     { PREFIX_TABLE (PREFIX_0F3A21) },
6899     { PREFIX_TABLE (PREFIX_0F3A22) },
6900     { Bad_Opcode },
6901     { Bad_Opcode },
6902     { Bad_Opcode },
6903     { Bad_Opcode },
6904     { Bad_Opcode },
6905     /* 28 */
6906     { Bad_Opcode },
6907     { Bad_Opcode },
6908     { Bad_Opcode },
6909     { Bad_Opcode },
6910     { Bad_Opcode },
6911     { Bad_Opcode },
6912     { Bad_Opcode },
6913     { Bad_Opcode },
6914     /* 30 */
6915     { Bad_Opcode },
6916     { Bad_Opcode },
6917     { Bad_Opcode },
6918     { Bad_Opcode },
6919     { Bad_Opcode },
6920     { Bad_Opcode },
6921     { Bad_Opcode },
6922     { Bad_Opcode },
6923     /* 38 */
6924     { Bad_Opcode },
6925     { Bad_Opcode },
6926     { Bad_Opcode },
6927     { Bad_Opcode },
6928     { Bad_Opcode },
6929     { Bad_Opcode },
6930     { Bad_Opcode },
6931     { Bad_Opcode },
6932     /* 40 */
6933     { PREFIX_TABLE (PREFIX_0F3A40) },
6934     { PREFIX_TABLE (PREFIX_0F3A41) },
6935     { PREFIX_TABLE (PREFIX_0F3A42) },
6936     { Bad_Opcode },
6937     { PREFIX_TABLE (PREFIX_0F3A44) },
6938     { Bad_Opcode },
6939     { Bad_Opcode },
6940     { Bad_Opcode },
6941     /* 48 */
6942     { Bad_Opcode },
6943     { Bad_Opcode },
6944     { Bad_Opcode },
6945     { Bad_Opcode },
6946     { Bad_Opcode },
6947     { Bad_Opcode },
6948     { Bad_Opcode },
6949     { Bad_Opcode },
6950     /* 50 */
6951     { Bad_Opcode },
6952     { Bad_Opcode },
6953     { Bad_Opcode },
6954     { Bad_Opcode },
6955     { Bad_Opcode },
6956     { Bad_Opcode },
6957     { Bad_Opcode },
6958     { Bad_Opcode },
6959     /* 58 */
6960     { Bad_Opcode },
6961     { Bad_Opcode },
6962     { Bad_Opcode },
6963     { Bad_Opcode },
6964     { Bad_Opcode },
6965     { Bad_Opcode },
6966     { Bad_Opcode },
6967     { Bad_Opcode },
6968     /* 60 */
6969     { PREFIX_TABLE (PREFIX_0F3A60) },
6970     { PREFIX_TABLE (PREFIX_0F3A61) },
6971     { PREFIX_TABLE (PREFIX_0F3A62) },
6972     { PREFIX_TABLE (PREFIX_0F3A63) },
6973     { Bad_Opcode },
6974     { Bad_Opcode },
6975     { Bad_Opcode },
6976     { Bad_Opcode },
6977     /* 68 */
6978     { Bad_Opcode },
6979     { Bad_Opcode },
6980     { Bad_Opcode },
6981     { Bad_Opcode },
6982     { Bad_Opcode },
6983     { Bad_Opcode },
6984     { Bad_Opcode },
6985     { Bad_Opcode },
6986     /* 70 */
6987     { Bad_Opcode },
6988     { Bad_Opcode },
6989     { Bad_Opcode },
6990     { Bad_Opcode },
6991     { Bad_Opcode },
6992     { Bad_Opcode },
6993     { Bad_Opcode },
6994     { Bad_Opcode },
6995     /* 78 */
6996     { Bad_Opcode },
6997     { Bad_Opcode },
6998     { Bad_Opcode },
6999     { Bad_Opcode },
7000     { Bad_Opcode },
7001     { Bad_Opcode },
7002     { Bad_Opcode },
7003     { Bad_Opcode },
7004     /* 80 */
7005     { Bad_Opcode },
7006     { Bad_Opcode },
7007     { Bad_Opcode },
7008     { Bad_Opcode },
7009     { Bad_Opcode },
7010     { Bad_Opcode },
7011     { Bad_Opcode },
7012     { Bad_Opcode },
7013     /* 88 */
7014     { Bad_Opcode },
7015     { Bad_Opcode },
7016     { Bad_Opcode },
7017     { Bad_Opcode },
7018     { Bad_Opcode },
7019     { Bad_Opcode },
7020     { Bad_Opcode },
7021     { Bad_Opcode },
7022     /* 90 */
7023     { Bad_Opcode },
7024     { Bad_Opcode },
7025     { Bad_Opcode },
7026     { Bad_Opcode },
7027     { Bad_Opcode },
7028     { Bad_Opcode },
7029     { Bad_Opcode },
7030     { Bad_Opcode },
7031     /* 98 */
7032     { Bad_Opcode },
7033     { Bad_Opcode },
7034     { Bad_Opcode },
7035     { Bad_Opcode },
7036     { Bad_Opcode },
7037     { Bad_Opcode },
7038     { Bad_Opcode },
7039     { Bad_Opcode },
7040     /* a0 */
7041     { Bad_Opcode },
7042     { Bad_Opcode },
7043     { Bad_Opcode },
7044     { Bad_Opcode },
7045     { Bad_Opcode },
7046     { Bad_Opcode },
7047     { Bad_Opcode },
7048     { Bad_Opcode },
7049     /* a8 */
7050     { Bad_Opcode },
7051     { Bad_Opcode },
7052     { Bad_Opcode },
7053     { Bad_Opcode },
7054     { Bad_Opcode },
7055     { Bad_Opcode },
7056     { Bad_Opcode },
7057     { Bad_Opcode },
7058     /* b0 */
7059     { Bad_Opcode },
7060     { Bad_Opcode },
7061     { Bad_Opcode },
7062     { Bad_Opcode },
7063     { Bad_Opcode },
7064     { Bad_Opcode },
7065     { Bad_Opcode },
7066     { Bad_Opcode },
7067     /* b8 */
7068     { Bad_Opcode },
7069     { Bad_Opcode },
7070     { Bad_Opcode },
7071     { Bad_Opcode },
7072     { Bad_Opcode },
7073     { Bad_Opcode },
7074     { Bad_Opcode },
7075     { Bad_Opcode },
7076     /* c0 */
7077     { Bad_Opcode },
7078     { Bad_Opcode },
7079     { Bad_Opcode },
7080     { Bad_Opcode },
7081     { Bad_Opcode },
7082     { Bad_Opcode },
7083     { Bad_Opcode },
7084     { Bad_Opcode },
7085     /* c8 */
7086     { Bad_Opcode },
7087     { Bad_Opcode },
7088     { Bad_Opcode },
7089     { Bad_Opcode },
7090     { PREFIX_TABLE (PREFIX_0F3ACC) },
7091     { Bad_Opcode },
7092     { Bad_Opcode },
7093     { Bad_Opcode },
7094     /* d0 */
7095     { Bad_Opcode },
7096     { Bad_Opcode },
7097     { Bad_Opcode },
7098     { Bad_Opcode },
7099     { Bad_Opcode },
7100     { Bad_Opcode },
7101     { Bad_Opcode },
7102     { Bad_Opcode },
7103     /* d8 */
7104     { Bad_Opcode },
7105     { Bad_Opcode },
7106     { Bad_Opcode },
7107     { Bad_Opcode },
7108     { Bad_Opcode },
7109     { Bad_Opcode },
7110     { Bad_Opcode },
7111     { PREFIX_TABLE (PREFIX_0F3ADF) },
7112     /* e0 */
7113     { Bad_Opcode },
7114     { Bad_Opcode },
7115     { Bad_Opcode },
7116     { Bad_Opcode },
7117     { Bad_Opcode },
7118     { Bad_Opcode },
7119     { Bad_Opcode },
7120     { Bad_Opcode },
7121     /* e8 */
7122     { Bad_Opcode },
7123     { Bad_Opcode },
7124     { Bad_Opcode },
7125     { Bad_Opcode },
7126     { Bad_Opcode },
7127     { Bad_Opcode },
7128     { Bad_Opcode },
7129     { Bad_Opcode },
7130     /* f0 */
7131     { Bad_Opcode },
7132     { Bad_Opcode },
7133     { Bad_Opcode },
7134     { Bad_Opcode },
7135     { Bad_Opcode },
7136     { Bad_Opcode },
7137     { Bad_Opcode },
7138     { Bad_Opcode },
7139     /* f8 */
7140     { Bad_Opcode },
7141     { Bad_Opcode },
7142     { Bad_Opcode },
7143     { Bad_Opcode },
7144     { Bad_Opcode },
7145     { Bad_Opcode },
7146     { Bad_Opcode },
7147     { Bad_Opcode },
7148   },
7149
7150   /* THREE_BYTE_0F7A */
7151   {
7152     /* 00 */
7153     { Bad_Opcode },
7154     { Bad_Opcode },
7155     { Bad_Opcode },
7156     { Bad_Opcode },
7157     { Bad_Opcode },
7158     { Bad_Opcode },
7159     { Bad_Opcode },
7160     { Bad_Opcode },
7161     /* 08 */
7162     { Bad_Opcode },
7163     { Bad_Opcode },
7164     { Bad_Opcode },
7165     { Bad_Opcode },
7166     { Bad_Opcode },
7167     { Bad_Opcode },
7168     { Bad_Opcode },
7169     { Bad_Opcode },
7170     /* 10 */
7171     { Bad_Opcode },
7172     { Bad_Opcode },
7173     { Bad_Opcode },
7174     { Bad_Opcode },
7175     { Bad_Opcode },
7176     { Bad_Opcode },
7177     { Bad_Opcode },
7178     { Bad_Opcode },
7179     /* 18 */
7180     { Bad_Opcode },
7181     { Bad_Opcode },
7182     { Bad_Opcode },
7183     { Bad_Opcode },
7184     { Bad_Opcode },
7185     { Bad_Opcode },
7186     { Bad_Opcode },
7187     { Bad_Opcode },
7188     /* 20 */
7189     { "ptest",          { XX } },
7190     { Bad_Opcode },
7191     { Bad_Opcode },
7192     { Bad_Opcode },
7193     { Bad_Opcode },
7194     { Bad_Opcode },
7195     { Bad_Opcode },
7196     { Bad_Opcode },
7197     /* 28 */
7198     { Bad_Opcode },
7199     { Bad_Opcode },
7200     { Bad_Opcode },
7201     { Bad_Opcode },
7202     { Bad_Opcode },
7203     { Bad_Opcode },
7204     { Bad_Opcode },
7205     { Bad_Opcode },
7206     /* 30 */
7207     { Bad_Opcode },
7208     { Bad_Opcode },
7209     { Bad_Opcode },
7210     { Bad_Opcode },
7211     { Bad_Opcode },
7212     { Bad_Opcode },
7213     { Bad_Opcode },
7214     { Bad_Opcode },
7215     /* 38 */
7216     { Bad_Opcode },
7217     { Bad_Opcode },
7218     { Bad_Opcode },
7219     { Bad_Opcode },
7220     { Bad_Opcode },
7221     { Bad_Opcode },
7222     { Bad_Opcode },
7223     { Bad_Opcode },
7224     /* 40 */
7225     { Bad_Opcode },
7226     { "phaddbw",        { XM, EXq } },
7227     { "phaddbd",        { XM, EXq } },
7228     { "phaddbq",        { XM, EXq } },
7229     { Bad_Opcode },
7230     { Bad_Opcode },
7231     { "phaddwd",        { XM, EXq } },
7232     { "phaddwq",        { XM, EXq } },
7233     /* 48 */
7234     { Bad_Opcode },
7235     { Bad_Opcode },
7236     { Bad_Opcode },
7237     { "phadddq",        { XM, EXq } },
7238     { Bad_Opcode },
7239     { Bad_Opcode },
7240     { Bad_Opcode },
7241     { Bad_Opcode },
7242     /* 50 */
7243     { Bad_Opcode },
7244     { "phaddubw",       { XM, EXq } },
7245     { "phaddubd",       { XM, EXq } },
7246     { "phaddubq",       { XM, EXq } },
7247     { Bad_Opcode },
7248     { Bad_Opcode },
7249     { "phadduwd",       { XM, EXq } },
7250     { "phadduwq",       { XM, EXq } },
7251     /* 58 */
7252     { Bad_Opcode },
7253     { Bad_Opcode },
7254     { Bad_Opcode },
7255     { "phaddudq",       { XM, EXq } },
7256     { Bad_Opcode },
7257     { Bad_Opcode },
7258     { Bad_Opcode },
7259     { Bad_Opcode },
7260     /* 60 */
7261     { Bad_Opcode },
7262     { "phsubbw",        { XM, EXq } },
7263     { "phsubbd",        { XM, EXq } },
7264     { "phsubbq",        { XM, EXq } },
7265     { Bad_Opcode },
7266     { Bad_Opcode },
7267     { Bad_Opcode },
7268     { Bad_Opcode },
7269     /* 68 */
7270     { Bad_Opcode },
7271     { Bad_Opcode },
7272     { Bad_Opcode },
7273     { Bad_Opcode },
7274     { Bad_Opcode },
7275     { Bad_Opcode },
7276     { Bad_Opcode },
7277     { Bad_Opcode },
7278     /* 70 */
7279     { Bad_Opcode },
7280     { Bad_Opcode },
7281     { Bad_Opcode },
7282     { Bad_Opcode },
7283     { Bad_Opcode },
7284     { Bad_Opcode },
7285     { Bad_Opcode },
7286     { Bad_Opcode },
7287     /* 78 */
7288     { Bad_Opcode },
7289     { Bad_Opcode },
7290     { Bad_Opcode },
7291     { Bad_Opcode },
7292     { Bad_Opcode },
7293     { Bad_Opcode },
7294     { Bad_Opcode },
7295     { Bad_Opcode },
7296     /* 80 */
7297     { Bad_Opcode },
7298     { Bad_Opcode },
7299     { Bad_Opcode },
7300     { Bad_Opcode },
7301     { Bad_Opcode },
7302     { Bad_Opcode },
7303     { Bad_Opcode },
7304     { Bad_Opcode },
7305     /* 88 */
7306     { Bad_Opcode },
7307     { Bad_Opcode },
7308     { Bad_Opcode },
7309     { Bad_Opcode },
7310     { Bad_Opcode },
7311     { Bad_Opcode },
7312     { Bad_Opcode },
7313     { Bad_Opcode },
7314     /* 90 */
7315     { Bad_Opcode },
7316     { Bad_Opcode },
7317     { Bad_Opcode },
7318     { Bad_Opcode },
7319     { Bad_Opcode },
7320     { Bad_Opcode },
7321     { Bad_Opcode },
7322     { Bad_Opcode },
7323     /* 98 */
7324     { Bad_Opcode },
7325     { Bad_Opcode },
7326     { Bad_Opcode },
7327     { Bad_Opcode },
7328     { Bad_Opcode },
7329     { Bad_Opcode },
7330     { Bad_Opcode },
7331     { Bad_Opcode },
7332     /* a0 */
7333     { Bad_Opcode },
7334     { Bad_Opcode },
7335     { Bad_Opcode },
7336     { Bad_Opcode },
7337     { Bad_Opcode },
7338     { Bad_Opcode },
7339     { Bad_Opcode },
7340     { Bad_Opcode },
7341     /* a8 */
7342     { Bad_Opcode },
7343     { Bad_Opcode },
7344     { Bad_Opcode },
7345     { Bad_Opcode },
7346     { Bad_Opcode },
7347     { Bad_Opcode },
7348     { Bad_Opcode },
7349     { Bad_Opcode },
7350     /* b0 */
7351     { Bad_Opcode },
7352     { Bad_Opcode },
7353     { Bad_Opcode },
7354     { Bad_Opcode },
7355     { Bad_Opcode },
7356     { Bad_Opcode },
7357     { Bad_Opcode },
7358     { Bad_Opcode },
7359     /* b8 */
7360     { Bad_Opcode },
7361     { Bad_Opcode },
7362     { Bad_Opcode },
7363     { Bad_Opcode },
7364     { Bad_Opcode },
7365     { Bad_Opcode },
7366     { Bad_Opcode },
7367     { Bad_Opcode },
7368     /* c0 */
7369     { Bad_Opcode },
7370     { Bad_Opcode },
7371     { Bad_Opcode },
7372     { Bad_Opcode },
7373     { Bad_Opcode },
7374     { Bad_Opcode },
7375     { Bad_Opcode },
7376     { Bad_Opcode },
7377     /* c8 */
7378     { Bad_Opcode },
7379     { Bad_Opcode },
7380     { Bad_Opcode },
7381     { Bad_Opcode },
7382     { Bad_Opcode },
7383     { Bad_Opcode },
7384     { Bad_Opcode },
7385     { Bad_Opcode },
7386     /* d0 */
7387     { Bad_Opcode },
7388     { Bad_Opcode },
7389     { Bad_Opcode },
7390     { Bad_Opcode },
7391     { Bad_Opcode },
7392     { Bad_Opcode },
7393     { Bad_Opcode },
7394     { Bad_Opcode },
7395     /* d8 */
7396     { Bad_Opcode },
7397     { Bad_Opcode },
7398     { Bad_Opcode },
7399     { Bad_Opcode },
7400     { Bad_Opcode },
7401     { Bad_Opcode },
7402     { Bad_Opcode },
7403     { Bad_Opcode },
7404     /* e0 */
7405     { Bad_Opcode },
7406     { Bad_Opcode },
7407     { Bad_Opcode },
7408     { Bad_Opcode },
7409     { Bad_Opcode },
7410     { Bad_Opcode },
7411     { Bad_Opcode },
7412     { Bad_Opcode },
7413     /* e8 */
7414     { Bad_Opcode },
7415     { Bad_Opcode },
7416     { Bad_Opcode },
7417     { Bad_Opcode },
7418     { Bad_Opcode },
7419     { Bad_Opcode },
7420     { Bad_Opcode },
7421     { Bad_Opcode },
7422     /* f0 */
7423     { Bad_Opcode },
7424     { Bad_Opcode },
7425     { Bad_Opcode },
7426     { Bad_Opcode },
7427     { Bad_Opcode },
7428     { Bad_Opcode },
7429     { Bad_Opcode },
7430     { Bad_Opcode },
7431     /* f8 */
7432     { Bad_Opcode },
7433     { Bad_Opcode },
7434     { Bad_Opcode },
7435     { Bad_Opcode },
7436     { Bad_Opcode },
7437     { Bad_Opcode },
7438     { Bad_Opcode },
7439     { Bad_Opcode },
7440   },
7441 };
7442
7443 static const struct dis386 xop_table[][256] = {
7444   /* XOP_08 */
7445   {
7446     /* 00 */
7447     { Bad_Opcode },
7448     { Bad_Opcode },
7449     { Bad_Opcode },
7450     { Bad_Opcode },
7451     { Bad_Opcode },
7452     { Bad_Opcode },
7453     { Bad_Opcode },
7454     { Bad_Opcode },
7455     /* 08 */
7456     { Bad_Opcode },
7457     { Bad_Opcode },
7458     { Bad_Opcode },
7459     { Bad_Opcode },
7460     { Bad_Opcode },
7461     { Bad_Opcode },
7462     { Bad_Opcode },
7463     { Bad_Opcode },
7464     /* 10 */
7465     { Bad_Opcode },
7466     { Bad_Opcode },
7467     { Bad_Opcode },
7468     { Bad_Opcode },
7469     { Bad_Opcode },
7470     { Bad_Opcode },
7471     { Bad_Opcode },
7472     { Bad_Opcode },
7473     /* 18 */
7474     { Bad_Opcode },
7475     { Bad_Opcode },
7476     { Bad_Opcode },
7477     { Bad_Opcode },
7478     { Bad_Opcode },
7479     { Bad_Opcode },
7480     { Bad_Opcode },
7481     { Bad_Opcode },
7482     /* 20 */
7483     { Bad_Opcode },
7484     { Bad_Opcode },
7485     { Bad_Opcode },
7486     { Bad_Opcode },
7487     { Bad_Opcode },
7488     { Bad_Opcode },
7489     { Bad_Opcode },
7490     { Bad_Opcode },
7491     /* 28 */
7492     { Bad_Opcode },
7493     { Bad_Opcode },
7494     { Bad_Opcode },
7495     { Bad_Opcode },
7496     { Bad_Opcode },
7497     { Bad_Opcode },
7498     { Bad_Opcode },
7499     { Bad_Opcode },
7500     /* 30 */
7501     { Bad_Opcode },
7502     { Bad_Opcode },
7503     { Bad_Opcode },
7504     { Bad_Opcode },
7505     { Bad_Opcode },
7506     { Bad_Opcode },
7507     { Bad_Opcode },
7508     { Bad_Opcode },
7509     /* 38 */
7510     { Bad_Opcode },
7511     { Bad_Opcode },
7512     { Bad_Opcode },
7513     { Bad_Opcode },
7514     { Bad_Opcode },
7515     { Bad_Opcode },
7516     { Bad_Opcode },
7517     { Bad_Opcode },
7518     /* 40 */
7519     { Bad_Opcode },
7520     { Bad_Opcode },
7521     { Bad_Opcode },
7522     { Bad_Opcode },
7523     { Bad_Opcode },
7524     { Bad_Opcode },
7525     { Bad_Opcode },
7526     { Bad_Opcode },
7527     /* 48 */
7528     { Bad_Opcode },
7529     { Bad_Opcode },
7530     { Bad_Opcode },
7531     { Bad_Opcode },
7532     { Bad_Opcode },
7533     { Bad_Opcode },
7534     { Bad_Opcode },
7535     { Bad_Opcode },
7536     /* 50 */
7537     { Bad_Opcode },
7538     { Bad_Opcode },
7539     { Bad_Opcode },
7540     { Bad_Opcode },
7541     { Bad_Opcode },
7542     { Bad_Opcode },
7543     { Bad_Opcode },
7544     { Bad_Opcode },
7545     /* 58 */
7546     { Bad_Opcode },
7547     { Bad_Opcode },
7548     { Bad_Opcode },
7549     { Bad_Opcode },
7550     { Bad_Opcode },
7551     { Bad_Opcode },
7552     { Bad_Opcode },
7553     { Bad_Opcode },
7554     /* 60 */
7555     { Bad_Opcode },
7556     { Bad_Opcode },
7557     { Bad_Opcode },
7558     { Bad_Opcode },
7559     { Bad_Opcode },
7560     { Bad_Opcode },
7561     { Bad_Opcode },
7562     { Bad_Opcode },
7563     /* 68 */
7564     { Bad_Opcode },
7565     { Bad_Opcode },
7566     { Bad_Opcode },
7567     { Bad_Opcode },
7568     { Bad_Opcode },
7569     { Bad_Opcode },
7570     { Bad_Opcode },
7571     { Bad_Opcode },
7572     /* 70 */
7573     { Bad_Opcode },
7574     { Bad_Opcode },
7575     { Bad_Opcode },
7576     { Bad_Opcode },
7577     { Bad_Opcode },
7578     { Bad_Opcode },
7579     { Bad_Opcode },
7580     { Bad_Opcode },
7581     /* 78 */
7582     { Bad_Opcode },
7583     { Bad_Opcode },
7584     { Bad_Opcode },
7585     { Bad_Opcode },
7586     { Bad_Opcode },
7587     { Bad_Opcode },
7588     { Bad_Opcode },
7589     { Bad_Opcode },
7590     /* 80 */
7591     { Bad_Opcode },
7592     { Bad_Opcode },
7593     { Bad_Opcode },
7594     { Bad_Opcode },
7595     { Bad_Opcode },
7596     { "vpmacssww",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7597     { "vpmacsswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7598     { "vpmacssdql",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7599     /* 88 */
7600     { Bad_Opcode },
7601     { Bad_Opcode },
7602     { Bad_Opcode },
7603     { Bad_Opcode },
7604     { Bad_Opcode },
7605     { Bad_Opcode },
7606     { "vpmacssdd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7607     { "vpmacssdqh",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7608     /* 90 */
7609     { Bad_Opcode },
7610     { Bad_Opcode },
7611     { Bad_Opcode },
7612     { Bad_Opcode },
7613     { Bad_Opcode },
7614     { "vpmacsww",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7615     { "vpmacswd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7616     { "vpmacsdql",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7617     /* 98 */
7618     { Bad_Opcode },
7619     { Bad_Opcode },
7620     { Bad_Opcode },
7621     { Bad_Opcode },
7622     { Bad_Opcode },
7623     { Bad_Opcode },
7624     { "vpmacsdd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7625     { "vpmacsdqh",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7626     /* a0 */
7627     { Bad_Opcode },
7628     { Bad_Opcode },
7629     { "vpcmov",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7630     { "vpperm",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7631     { Bad_Opcode },
7632     { Bad_Opcode },
7633     { "vpmadcsswd",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7634     { Bad_Opcode },
7635     /* a8 */
7636     { Bad_Opcode },
7637     { Bad_Opcode },
7638     { Bad_Opcode },
7639     { Bad_Opcode },
7640     { Bad_Opcode },
7641     { Bad_Opcode },
7642     { Bad_Opcode },
7643     { Bad_Opcode },
7644     /* b0 */
7645     { Bad_Opcode },
7646     { Bad_Opcode },
7647     { Bad_Opcode },
7648     { Bad_Opcode },
7649     { Bad_Opcode },
7650     { Bad_Opcode },
7651     { "vpmadcswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7652     { Bad_Opcode },
7653     /* b8 */
7654     { Bad_Opcode },
7655     { Bad_Opcode },
7656     { Bad_Opcode },
7657     { Bad_Opcode },
7658     { Bad_Opcode },
7659     { Bad_Opcode },
7660     { Bad_Opcode },
7661     { Bad_Opcode },
7662     /* c0 */
7663     { "vprotb",         { XM, Vex_2src_1, Ib } },
7664     { "vprotw",         { XM, Vex_2src_1, Ib } },
7665     { "vprotd",         { XM, Vex_2src_1, Ib } },
7666     { "vprotq",         { XM, Vex_2src_1, Ib } },
7667     { Bad_Opcode },
7668     { Bad_Opcode },
7669     { Bad_Opcode },
7670     { Bad_Opcode },
7671     /* c8 */
7672     { Bad_Opcode },
7673     { Bad_Opcode },
7674     { Bad_Opcode },
7675     { Bad_Opcode },
7676     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
7677     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
7678     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
7679     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
7680     /* d0 */
7681     { Bad_Opcode },
7682     { Bad_Opcode },
7683     { Bad_Opcode },
7684     { Bad_Opcode },
7685     { Bad_Opcode },
7686     { Bad_Opcode },
7687     { Bad_Opcode },
7688     { Bad_Opcode },
7689     /* d8 */
7690     { Bad_Opcode },
7691     { Bad_Opcode },
7692     { Bad_Opcode },
7693     { Bad_Opcode },
7694     { Bad_Opcode },
7695     { Bad_Opcode },
7696     { Bad_Opcode },
7697     { Bad_Opcode },
7698     /* e0 */
7699     { Bad_Opcode },
7700     { Bad_Opcode },
7701     { Bad_Opcode },
7702     { Bad_Opcode },
7703     { Bad_Opcode },
7704     { Bad_Opcode },
7705     { Bad_Opcode },
7706     { Bad_Opcode },
7707     /* e8 */
7708     { Bad_Opcode },
7709     { Bad_Opcode },
7710     { Bad_Opcode },
7711     { Bad_Opcode },
7712     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
7713     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
7714     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
7715     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
7716     /* f0 */
7717     { Bad_Opcode },
7718     { Bad_Opcode },
7719     { Bad_Opcode },
7720     { Bad_Opcode },
7721     { Bad_Opcode },
7722     { Bad_Opcode },
7723     { Bad_Opcode },
7724     { Bad_Opcode },
7725     /* f8 */
7726     { Bad_Opcode },
7727     { Bad_Opcode },
7728     { Bad_Opcode },
7729     { Bad_Opcode },
7730     { Bad_Opcode },
7731     { Bad_Opcode },
7732     { Bad_Opcode },
7733     { Bad_Opcode },
7734   },
7735   /* XOP_09 */
7736   {
7737     /* 00 */
7738     { Bad_Opcode },
7739     { REG_TABLE (REG_XOP_TBM_01) },
7740     { REG_TABLE (REG_XOP_TBM_02) },
7741     { Bad_Opcode },
7742     { Bad_Opcode },
7743     { Bad_Opcode },
7744     { Bad_Opcode },
7745     { Bad_Opcode },
7746     /* 08 */
7747     { Bad_Opcode },
7748     { Bad_Opcode },
7749     { Bad_Opcode },
7750     { Bad_Opcode },
7751     { Bad_Opcode },
7752     { Bad_Opcode },
7753     { Bad_Opcode },
7754     { Bad_Opcode },
7755     /* 10 */
7756     { Bad_Opcode },
7757     { Bad_Opcode },
7758     { REG_TABLE (REG_XOP_LWPCB) },
7759     { Bad_Opcode },
7760     { Bad_Opcode },
7761     { Bad_Opcode },
7762     { Bad_Opcode },
7763     { Bad_Opcode },
7764     /* 18 */
7765     { Bad_Opcode },
7766     { Bad_Opcode },
7767     { Bad_Opcode },
7768     { Bad_Opcode },
7769     { Bad_Opcode },
7770     { Bad_Opcode },
7771     { Bad_Opcode },
7772     { Bad_Opcode },
7773     /* 20 */
7774     { Bad_Opcode },
7775     { Bad_Opcode },
7776     { Bad_Opcode },
7777     { Bad_Opcode },
7778     { Bad_Opcode },
7779     { Bad_Opcode },
7780     { Bad_Opcode },
7781     { Bad_Opcode },
7782     /* 28 */
7783     { Bad_Opcode },
7784     { Bad_Opcode },
7785     { Bad_Opcode },
7786     { Bad_Opcode },
7787     { Bad_Opcode },
7788     { Bad_Opcode },
7789     { Bad_Opcode },
7790     { Bad_Opcode },
7791     /* 30 */
7792     { Bad_Opcode },
7793     { Bad_Opcode },
7794     { Bad_Opcode },
7795     { Bad_Opcode },
7796     { Bad_Opcode },
7797     { Bad_Opcode },
7798     { Bad_Opcode },
7799     { Bad_Opcode },
7800     /* 38 */
7801     { Bad_Opcode },
7802     { Bad_Opcode },
7803     { Bad_Opcode },
7804     { Bad_Opcode },
7805     { Bad_Opcode },
7806     { Bad_Opcode },
7807     { Bad_Opcode },
7808     { Bad_Opcode },
7809     /* 40 */
7810     { Bad_Opcode },
7811     { Bad_Opcode },
7812     { Bad_Opcode },
7813     { Bad_Opcode },
7814     { Bad_Opcode },
7815     { Bad_Opcode },
7816     { Bad_Opcode },
7817     { Bad_Opcode },
7818     /* 48 */
7819     { Bad_Opcode },
7820     { Bad_Opcode },
7821     { Bad_Opcode },
7822     { Bad_Opcode },
7823     { Bad_Opcode },
7824     { Bad_Opcode },
7825     { Bad_Opcode },
7826     { Bad_Opcode },
7827     /* 50 */
7828     { Bad_Opcode },
7829     { Bad_Opcode },
7830     { Bad_Opcode },
7831     { Bad_Opcode },
7832     { Bad_Opcode },
7833     { Bad_Opcode },
7834     { Bad_Opcode },
7835     { Bad_Opcode },
7836     /* 58 */
7837     { Bad_Opcode },
7838     { Bad_Opcode },
7839     { Bad_Opcode },
7840     { Bad_Opcode },
7841     { Bad_Opcode },
7842     { Bad_Opcode },
7843     { Bad_Opcode },
7844     { Bad_Opcode },
7845     /* 60 */
7846     { Bad_Opcode },
7847     { Bad_Opcode },
7848     { Bad_Opcode },
7849     { Bad_Opcode },
7850     { Bad_Opcode },
7851     { Bad_Opcode },
7852     { Bad_Opcode },
7853     { Bad_Opcode },
7854     /* 68 */
7855     { Bad_Opcode },
7856     { Bad_Opcode },
7857     { Bad_Opcode },
7858     { Bad_Opcode },
7859     { Bad_Opcode },
7860     { Bad_Opcode },
7861     { Bad_Opcode },
7862     { Bad_Opcode },
7863     /* 70 */
7864     { Bad_Opcode },
7865     { Bad_Opcode },
7866     { Bad_Opcode },
7867     { Bad_Opcode },
7868     { Bad_Opcode },
7869     { Bad_Opcode },
7870     { Bad_Opcode },
7871     { Bad_Opcode },
7872     /* 78 */
7873     { Bad_Opcode },
7874     { Bad_Opcode },
7875     { Bad_Opcode },
7876     { Bad_Opcode },
7877     { Bad_Opcode },
7878     { Bad_Opcode },
7879     { Bad_Opcode },
7880     { Bad_Opcode },
7881     /* 80 */
7882     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
7883     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
7884     { "vfrczss",        { XM, EXd } },
7885     { "vfrczsd",        { XM, EXq } },
7886     { Bad_Opcode },
7887     { Bad_Opcode },
7888     { Bad_Opcode },
7889     { Bad_Opcode },
7890     /* 88 */
7891     { Bad_Opcode },
7892     { Bad_Opcode },
7893     { Bad_Opcode },
7894     { Bad_Opcode },
7895     { Bad_Opcode },
7896     { Bad_Opcode },
7897     { Bad_Opcode },
7898     { Bad_Opcode },
7899     /* 90 */
7900     { "vprotb",         { XM, Vex_2src_1, Vex_2src_2 } },
7901     { "vprotw",         { XM, Vex_2src_1, Vex_2src_2 } },
7902     { "vprotd",         { XM, Vex_2src_1, Vex_2src_2 } },
7903     { "vprotq",         { XM, Vex_2src_1, Vex_2src_2 } },
7904     { "vpshlb",         { XM, Vex_2src_1, Vex_2src_2 } },
7905     { "vpshlw",         { XM, Vex_2src_1, Vex_2src_2 } },
7906     { "vpshld",         { XM, Vex_2src_1, Vex_2src_2 } },
7907     { "vpshlq",         { XM, Vex_2src_1, Vex_2src_2 } },
7908     /* 98 */
7909     { "vpshab",         { XM, Vex_2src_1, Vex_2src_2 } },
7910     { "vpshaw",         { XM, Vex_2src_1, Vex_2src_2 } },
7911     { "vpshad",         { XM, Vex_2src_1, Vex_2src_2 } },
7912     { "vpshaq",         { XM, Vex_2src_1, Vex_2src_2 } },
7913     { Bad_Opcode },
7914     { Bad_Opcode },
7915     { Bad_Opcode },
7916     { Bad_Opcode },
7917     /* a0 */
7918     { Bad_Opcode },
7919     { Bad_Opcode },
7920     { Bad_Opcode },
7921     { Bad_Opcode },
7922     { Bad_Opcode },
7923     { Bad_Opcode },
7924     { Bad_Opcode },
7925     { Bad_Opcode },
7926     /* a8 */
7927     { Bad_Opcode },
7928     { Bad_Opcode },
7929     { Bad_Opcode },
7930     { Bad_Opcode },
7931     { Bad_Opcode },
7932     { Bad_Opcode },
7933     { Bad_Opcode },
7934     { Bad_Opcode },
7935     /* b0 */
7936     { Bad_Opcode },
7937     { Bad_Opcode },
7938     { Bad_Opcode },
7939     { Bad_Opcode },
7940     { Bad_Opcode },
7941     { Bad_Opcode },
7942     { Bad_Opcode },
7943     { Bad_Opcode },
7944     /* b8 */
7945     { Bad_Opcode },
7946     { Bad_Opcode },
7947     { Bad_Opcode },
7948     { Bad_Opcode },
7949     { Bad_Opcode },
7950     { Bad_Opcode },
7951     { Bad_Opcode },
7952     { Bad_Opcode },
7953     /* c0 */
7954     { Bad_Opcode },
7955     { "vphaddbw",       { XM, EXxmm } },
7956     { "vphaddbd",       { XM, EXxmm } },
7957     { "vphaddbq",       { XM, EXxmm } },
7958     { Bad_Opcode },
7959     { Bad_Opcode },
7960     { "vphaddwd",       { XM, EXxmm } },
7961     { "vphaddwq",       { XM, EXxmm } },
7962     /* c8 */
7963     { Bad_Opcode },
7964     { Bad_Opcode },
7965     { Bad_Opcode },
7966     { "vphadddq",       { XM, EXxmm } },
7967     { Bad_Opcode },
7968     { Bad_Opcode },
7969     { Bad_Opcode },
7970     { Bad_Opcode },
7971     /* d0 */
7972     { Bad_Opcode },
7973     { "vphaddubw",      { XM, EXxmm } },
7974     { "vphaddubd",      { XM, EXxmm } },
7975     { "vphaddubq",      { XM, EXxmm } },
7976     { Bad_Opcode },
7977     { Bad_Opcode },
7978     { "vphadduwd",      { XM, EXxmm } },
7979     { "vphadduwq",      { XM, EXxmm } },
7980     /* d8 */
7981     { Bad_Opcode },
7982     { Bad_Opcode },
7983     { Bad_Opcode },
7984     { "vphaddudq",      { XM, EXxmm } },
7985     { Bad_Opcode },
7986     { Bad_Opcode },
7987     { Bad_Opcode },
7988     { Bad_Opcode },
7989     /* e0 */
7990     { Bad_Opcode },
7991     { "vphsubbw",       { XM, EXxmm } },
7992     { "vphsubwd",       { XM, EXxmm } },
7993     { "vphsubdq",       { XM, EXxmm } },
7994     { Bad_Opcode },
7995     { Bad_Opcode },
7996     { Bad_Opcode },
7997     { Bad_Opcode },
7998     /* e8 */
7999     { Bad_Opcode },
8000     { Bad_Opcode },
8001     { Bad_Opcode },
8002     { Bad_Opcode },
8003     { Bad_Opcode },
8004     { Bad_Opcode },
8005     { Bad_Opcode },
8006     { Bad_Opcode },
8007     /* f0 */
8008     { Bad_Opcode },
8009     { Bad_Opcode },
8010     { Bad_Opcode },
8011     { Bad_Opcode },
8012     { Bad_Opcode },
8013     { Bad_Opcode },
8014     { Bad_Opcode },
8015     { Bad_Opcode },
8016     /* f8 */
8017     { Bad_Opcode },
8018     { Bad_Opcode },
8019     { Bad_Opcode },
8020     { Bad_Opcode },
8021     { Bad_Opcode },
8022     { Bad_Opcode },
8023     { Bad_Opcode },
8024     { Bad_Opcode },
8025   },
8026   /* XOP_0A */
8027   {
8028     /* 00 */
8029     { Bad_Opcode },
8030     { Bad_Opcode },
8031     { Bad_Opcode },
8032     { Bad_Opcode },
8033     { Bad_Opcode },
8034     { Bad_Opcode },
8035     { Bad_Opcode },
8036     { Bad_Opcode },
8037     /* 08 */
8038     { Bad_Opcode },
8039     { Bad_Opcode },
8040     { Bad_Opcode },
8041     { Bad_Opcode },
8042     { Bad_Opcode },
8043     { Bad_Opcode },
8044     { Bad_Opcode },
8045     { Bad_Opcode },
8046     /* 10 */
8047     { "bextr",  { Gv, Ev, Iq } },
8048     { Bad_Opcode },
8049     { REG_TABLE (REG_XOP_LWP) },
8050     { Bad_Opcode },
8051     { Bad_Opcode },
8052     { Bad_Opcode },
8053     { Bad_Opcode },
8054     { Bad_Opcode },
8055     /* 18 */
8056     { Bad_Opcode },
8057     { Bad_Opcode },
8058     { Bad_Opcode },
8059     { Bad_Opcode },
8060     { Bad_Opcode },
8061     { Bad_Opcode },
8062     { Bad_Opcode },
8063     { Bad_Opcode },
8064     /* 20 */
8065     { Bad_Opcode },
8066     { Bad_Opcode },
8067     { Bad_Opcode },
8068     { Bad_Opcode },
8069     { Bad_Opcode },
8070     { Bad_Opcode },
8071     { Bad_Opcode },
8072     { Bad_Opcode },
8073     /* 28 */
8074     { Bad_Opcode },
8075     { Bad_Opcode },
8076     { Bad_Opcode },
8077     { Bad_Opcode },
8078     { Bad_Opcode },
8079     { Bad_Opcode },
8080     { Bad_Opcode },
8081     { Bad_Opcode },
8082     /* 30 */
8083     { Bad_Opcode },
8084     { Bad_Opcode },
8085     { Bad_Opcode },
8086     { Bad_Opcode },
8087     { Bad_Opcode },
8088     { Bad_Opcode },
8089     { Bad_Opcode },
8090     { Bad_Opcode },
8091     /* 38 */
8092     { Bad_Opcode },
8093     { Bad_Opcode },
8094     { Bad_Opcode },
8095     { Bad_Opcode },
8096     { Bad_Opcode },
8097     { Bad_Opcode },
8098     { Bad_Opcode },
8099     { Bad_Opcode },
8100     /* 40 */
8101     { Bad_Opcode },
8102     { Bad_Opcode },
8103     { Bad_Opcode },
8104     { Bad_Opcode },
8105     { Bad_Opcode },
8106     { Bad_Opcode },
8107     { Bad_Opcode },
8108     { Bad_Opcode },
8109     /* 48 */
8110     { Bad_Opcode },
8111     { Bad_Opcode },
8112     { Bad_Opcode },
8113     { Bad_Opcode },
8114     { Bad_Opcode },
8115     { Bad_Opcode },
8116     { Bad_Opcode },
8117     { Bad_Opcode },
8118     /* 50 */
8119     { Bad_Opcode },
8120     { Bad_Opcode },
8121     { Bad_Opcode },
8122     { Bad_Opcode },
8123     { Bad_Opcode },
8124     { Bad_Opcode },
8125     { Bad_Opcode },
8126     { Bad_Opcode },
8127     /* 58 */
8128     { Bad_Opcode },
8129     { Bad_Opcode },
8130     { Bad_Opcode },
8131     { Bad_Opcode },
8132     { Bad_Opcode },
8133     { Bad_Opcode },
8134     { Bad_Opcode },
8135     { Bad_Opcode },
8136     /* 60 */
8137     { Bad_Opcode },
8138     { Bad_Opcode },
8139     { Bad_Opcode },
8140     { Bad_Opcode },
8141     { Bad_Opcode },
8142     { Bad_Opcode },
8143     { Bad_Opcode },
8144     { Bad_Opcode },
8145     /* 68 */
8146     { Bad_Opcode },
8147     { Bad_Opcode },
8148     { Bad_Opcode },
8149     { Bad_Opcode },
8150     { Bad_Opcode },
8151     { Bad_Opcode },
8152     { Bad_Opcode },
8153     { Bad_Opcode },
8154     /* 70 */
8155     { Bad_Opcode },
8156     { Bad_Opcode },
8157     { Bad_Opcode },
8158     { Bad_Opcode },
8159     { Bad_Opcode },
8160     { Bad_Opcode },
8161     { Bad_Opcode },
8162     { Bad_Opcode },
8163     /* 78 */
8164     { Bad_Opcode },
8165     { Bad_Opcode },
8166     { Bad_Opcode },
8167     { Bad_Opcode },
8168     { Bad_Opcode },
8169     { Bad_Opcode },
8170     { Bad_Opcode },
8171     { Bad_Opcode },
8172     /* 80 */
8173     { Bad_Opcode },
8174     { Bad_Opcode },
8175     { Bad_Opcode },
8176     { Bad_Opcode },
8177     { Bad_Opcode },
8178     { Bad_Opcode },
8179     { Bad_Opcode },
8180     { Bad_Opcode },
8181     /* 88 */
8182     { Bad_Opcode },
8183     { Bad_Opcode },
8184     { Bad_Opcode },
8185     { Bad_Opcode },
8186     { Bad_Opcode },
8187     { Bad_Opcode },
8188     { Bad_Opcode },
8189     { Bad_Opcode },
8190     /* 90 */
8191     { Bad_Opcode },
8192     { Bad_Opcode },
8193     { Bad_Opcode },
8194     { Bad_Opcode },
8195     { Bad_Opcode },
8196     { Bad_Opcode },
8197     { Bad_Opcode },
8198     { Bad_Opcode },
8199     /* 98 */
8200     { Bad_Opcode },
8201     { Bad_Opcode },
8202     { Bad_Opcode },
8203     { Bad_Opcode },
8204     { Bad_Opcode },
8205     { Bad_Opcode },
8206     { Bad_Opcode },
8207     { Bad_Opcode },
8208     /* a0 */
8209     { Bad_Opcode },
8210     { Bad_Opcode },
8211     { Bad_Opcode },
8212     { Bad_Opcode },
8213     { Bad_Opcode },
8214     { Bad_Opcode },
8215     { Bad_Opcode },
8216     { Bad_Opcode },
8217     /* a8 */
8218     { Bad_Opcode },
8219     { Bad_Opcode },
8220     { Bad_Opcode },
8221     { Bad_Opcode },
8222     { Bad_Opcode },
8223     { Bad_Opcode },
8224     { Bad_Opcode },
8225     { Bad_Opcode },
8226     /* b0 */
8227     { Bad_Opcode },
8228     { Bad_Opcode },
8229     { Bad_Opcode },
8230     { Bad_Opcode },
8231     { Bad_Opcode },
8232     { Bad_Opcode },
8233     { Bad_Opcode },
8234     { Bad_Opcode },
8235     /* b8 */
8236     { Bad_Opcode },
8237     { Bad_Opcode },
8238     { Bad_Opcode },
8239     { Bad_Opcode },
8240     { Bad_Opcode },
8241     { Bad_Opcode },
8242     { Bad_Opcode },
8243     { Bad_Opcode },
8244     /* c0 */
8245     { Bad_Opcode },
8246     { Bad_Opcode },
8247     { Bad_Opcode },
8248     { Bad_Opcode },
8249     { Bad_Opcode },
8250     { Bad_Opcode },
8251     { Bad_Opcode },
8252     { Bad_Opcode },
8253     /* c8 */
8254     { Bad_Opcode },
8255     { Bad_Opcode },
8256     { Bad_Opcode },
8257     { Bad_Opcode },
8258     { Bad_Opcode },
8259     { Bad_Opcode },
8260     { Bad_Opcode },
8261     { Bad_Opcode },
8262     /* d0 */
8263     { Bad_Opcode },
8264     { Bad_Opcode },
8265     { Bad_Opcode },
8266     { Bad_Opcode },
8267     { Bad_Opcode },
8268     { Bad_Opcode },
8269     { Bad_Opcode },
8270     { Bad_Opcode },
8271     /* d8 */
8272     { Bad_Opcode },
8273     { Bad_Opcode },
8274     { Bad_Opcode },
8275     { Bad_Opcode },
8276     { Bad_Opcode },
8277     { Bad_Opcode },
8278     { Bad_Opcode },
8279     { Bad_Opcode },
8280     /* e0 */
8281     { Bad_Opcode },
8282     { Bad_Opcode },
8283     { Bad_Opcode },
8284     { Bad_Opcode },
8285     { Bad_Opcode },
8286     { Bad_Opcode },
8287     { Bad_Opcode },
8288     { Bad_Opcode },
8289     /* e8 */
8290     { Bad_Opcode },
8291     { Bad_Opcode },
8292     { Bad_Opcode },
8293     { Bad_Opcode },
8294     { Bad_Opcode },
8295     { Bad_Opcode },
8296     { Bad_Opcode },
8297     { Bad_Opcode },
8298     /* f0 */
8299     { Bad_Opcode },
8300     { Bad_Opcode },
8301     { Bad_Opcode },
8302     { Bad_Opcode },
8303     { Bad_Opcode },
8304     { Bad_Opcode },
8305     { Bad_Opcode },
8306     { Bad_Opcode },
8307     /* f8 */
8308     { Bad_Opcode },
8309     { Bad_Opcode },
8310     { Bad_Opcode },
8311     { Bad_Opcode },
8312     { Bad_Opcode },
8313     { Bad_Opcode },
8314     { Bad_Opcode },
8315     { Bad_Opcode },
8316   },
8317 };
8318
8319 static const struct dis386 vex_table[][256] = {
8320   /* VEX_0F */
8321   {
8322     /* 00 */
8323     { Bad_Opcode },
8324     { Bad_Opcode },
8325     { Bad_Opcode },
8326     { Bad_Opcode },
8327     { Bad_Opcode },
8328     { Bad_Opcode },
8329     { Bad_Opcode },
8330     { Bad_Opcode },
8331     /* 08 */
8332     { Bad_Opcode },
8333     { Bad_Opcode },
8334     { Bad_Opcode },
8335     { Bad_Opcode },
8336     { Bad_Opcode },
8337     { Bad_Opcode },
8338     { Bad_Opcode },
8339     { Bad_Opcode },
8340     /* 10 */
8341     { PREFIX_TABLE (PREFIX_VEX_0F10) },
8342     { PREFIX_TABLE (PREFIX_VEX_0F11) },
8343     { PREFIX_TABLE (PREFIX_VEX_0F12) },
8344     { MOD_TABLE (MOD_VEX_0F13) },
8345     { VEX_W_TABLE (VEX_W_0F14) },
8346     { VEX_W_TABLE (VEX_W_0F15) },
8347     { PREFIX_TABLE (PREFIX_VEX_0F16) },
8348     { MOD_TABLE (MOD_VEX_0F17) },
8349     /* 18 */
8350     { Bad_Opcode },
8351     { Bad_Opcode },
8352     { Bad_Opcode },
8353     { Bad_Opcode },
8354     { Bad_Opcode },
8355     { Bad_Opcode },
8356     { Bad_Opcode },
8357     { Bad_Opcode },
8358     /* 20 */
8359     { Bad_Opcode },
8360     { Bad_Opcode },
8361     { Bad_Opcode },
8362     { Bad_Opcode },
8363     { Bad_Opcode },
8364     { Bad_Opcode },
8365     { Bad_Opcode },
8366     { Bad_Opcode },
8367     /* 28 */
8368     { VEX_W_TABLE (VEX_W_0F28) },
8369     { VEX_W_TABLE (VEX_W_0F29) },
8370     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8371     { MOD_TABLE (MOD_VEX_0F2B) },
8372     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8373     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8374     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8375     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8376     /* 30 */
8377     { Bad_Opcode },
8378     { Bad_Opcode },
8379     { Bad_Opcode },
8380     { Bad_Opcode },
8381     { Bad_Opcode },
8382     { Bad_Opcode },
8383     { Bad_Opcode },
8384     { Bad_Opcode },
8385     /* 38 */
8386     { Bad_Opcode },
8387     { Bad_Opcode },
8388     { Bad_Opcode },
8389     { Bad_Opcode },
8390     { Bad_Opcode },
8391     { Bad_Opcode },
8392     { Bad_Opcode },
8393     { Bad_Opcode },
8394     /* 40 */
8395     { Bad_Opcode },
8396     { PREFIX_TABLE (PREFIX_VEX_0F41) },
8397     { PREFIX_TABLE (PREFIX_VEX_0F42) },
8398     { Bad_Opcode },
8399     { PREFIX_TABLE (PREFIX_VEX_0F44) },
8400     { PREFIX_TABLE (PREFIX_VEX_0F45) },
8401     { PREFIX_TABLE (PREFIX_VEX_0F46) },
8402     { PREFIX_TABLE (PREFIX_VEX_0F47) },
8403     /* 48 */
8404     { Bad_Opcode },
8405     { Bad_Opcode },
8406     { Bad_Opcode },
8407     { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8408     { Bad_Opcode },
8409     { Bad_Opcode },
8410     { Bad_Opcode },
8411     { Bad_Opcode },
8412     /* 50 */
8413     { MOD_TABLE (MOD_VEX_0F50) },
8414     { PREFIX_TABLE (PREFIX_VEX_0F51) },
8415     { PREFIX_TABLE (PREFIX_VEX_0F52) },
8416     { PREFIX_TABLE (PREFIX_VEX_0F53) },
8417     { "vandpX",         { XM, Vex, EXx } },
8418     { "vandnpX",        { XM, Vex, EXx } },
8419     { "vorpX",          { XM, Vex, EXx } },
8420     { "vxorpX",         { XM, Vex, EXx } },
8421     /* 58 */
8422     { PREFIX_TABLE (PREFIX_VEX_0F58) },
8423     { PREFIX_TABLE (PREFIX_VEX_0F59) },
8424     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8425     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8426     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8427     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8428     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8429     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8430     /* 60 */
8431     { PREFIX_TABLE (PREFIX_VEX_0F60) },
8432     { PREFIX_TABLE (PREFIX_VEX_0F61) },
8433     { PREFIX_TABLE (PREFIX_VEX_0F62) },
8434     { PREFIX_TABLE (PREFIX_VEX_0F63) },
8435     { PREFIX_TABLE (PREFIX_VEX_0F64) },
8436     { PREFIX_TABLE (PREFIX_VEX_0F65) },
8437     { PREFIX_TABLE (PREFIX_VEX_0F66) },
8438     { PREFIX_TABLE (PREFIX_VEX_0F67) },
8439     /* 68 */
8440     { PREFIX_TABLE (PREFIX_VEX_0F68) },
8441     { PREFIX_TABLE (PREFIX_VEX_0F69) },
8442     { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8443     { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8444     { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8445     { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8446     { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8447     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8448     /* 70 */
8449     { PREFIX_TABLE (PREFIX_VEX_0F70) },
8450     { REG_TABLE (REG_VEX_0F71) },
8451     { REG_TABLE (REG_VEX_0F72) },
8452     { REG_TABLE (REG_VEX_0F73) },
8453     { PREFIX_TABLE (PREFIX_VEX_0F74) },
8454     { PREFIX_TABLE (PREFIX_VEX_0F75) },
8455     { PREFIX_TABLE (PREFIX_VEX_0F76) },
8456     { PREFIX_TABLE (PREFIX_VEX_0F77) },
8457     /* 78 */
8458     { Bad_Opcode },
8459     { Bad_Opcode },
8460     { Bad_Opcode },
8461     { Bad_Opcode },
8462     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8463     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8464     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8465     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8466     /* 80 */
8467     { Bad_Opcode },
8468     { Bad_Opcode },
8469     { Bad_Opcode },
8470     { Bad_Opcode },
8471     { Bad_Opcode },
8472     { Bad_Opcode },
8473     { Bad_Opcode },
8474     { Bad_Opcode },
8475     /* 88 */
8476     { Bad_Opcode },
8477     { Bad_Opcode },
8478     { Bad_Opcode },
8479     { Bad_Opcode },
8480     { Bad_Opcode },
8481     { Bad_Opcode },
8482     { Bad_Opcode },
8483     { Bad_Opcode },
8484     /* 90 */
8485     { PREFIX_TABLE (PREFIX_VEX_0F90) },
8486     { PREFIX_TABLE (PREFIX_VEX_0F91) },
8487     { PREFIX_TABLE (PREFIX_VEX_0F92) },
8488     { PREFIX_TABLE (PREFIX_VEX_0F93) },
8489     { Bad_Opcode },
8490     { Bad_Opcode },
8491     { Bad_Opcode },
8492     { Bad_Opcode },
8493     /* 98 */
8494     { PREFIX_TABLE (PREFIX_VEX_0F98) },
8495     { Bad_Opcode },
8496     { Bad_Opcode },
8497     { Bad_Opcode },
8498     { Bad_Opcode },
8499     { Bad_Opcode },
8500     { Bad_Opcode },
8501     { Bad_Opcode },
8502     /* a0 */
8503     { Bad_Opcode },
8504     { Bad_Opcode },
8505     { Bad_Opcode },
8506     { Bad_Opcode },
8507     { Bad_Opcode },
8508     { Bad_Opcode },
8509     { Bad_Opcode },
8510     { Bad_Opcode },
8511     /* a8 */
8512     { Bad_Opcode },
8513     { Bad_Opcode },
8514     { Bad_Opcode },
8515     { Bad_Opcode },
8516     { Bad_Opcode },
8517     { Bad_Opcode },
8518     { REG_TABLE (REG_VEX_0FAE) },
8519     { Bad_Opcode },
8520     /* b0 */
8521     { Bad_Opcode },
8522     { Bad_Opcode },
8523     { Bad_Opcode },
8524     { Bad_Opcode },
8525     { Bad_Opcode },
8526     { Bad_Opcode },
8527     { Bad_Opcode },
8528     { Bad_Opcode },
8529     /* b8 */
8530     { Bad_Opcode },
8531     { Bad_Opcode },
8532     { Bad_Opcode },
8533     { Bad_Opcode },
8534     { Bad_Opcode },
8535     { Bad_Opcode },
8536     { Bad_Opcode },
8537     { Bad_Opcode },
8538     /* c0 */
8539     { Bad_Opcode },
8540     { Bad_Opcode },
8541     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8542     { Bad_Opcode },
8543     { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8544     { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8545     { "vshufpX",        { XM, Vex, EXx, Ib } },
8546     { Bad_Opcode },
8547     /* c8 */
8548     { Bad_Opcode },
8549     { Bad_Opcode },
8550     { Bad_Opcode },
8551     { Bad_Opcode },
8552     { Bad_Opcode },
8553     { Bad_Opcode },
8554     { Bad_Opcode },
8555     { Bad_Opcode },
8556     /* d0 */
8557     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8558     { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8559     { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8560     { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8561     { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8562     { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8563     { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8564     { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8565     /* d8 */
8566     { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8567     { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8568     { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8569     { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8570     { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8571     { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8572     { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8573     { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8574     /* e0 */
8575     { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8576     { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8577     { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8578     { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8579     { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8580     { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8581     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8582     { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8583     /* e8 */
8584     { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8585     { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8586     { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8587     { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8588     { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8589     { PREFIX_TABLE (PREFIX_VEX_0FED) },
8590     { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8591     { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8592     /* f0 */
8593     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8594     { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8595     { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8596     { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8597     { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8598     { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8599     { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8600     { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8601     /* f8 */
8602     { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8603     { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8604     { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8605     { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8606     { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8607     { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8608     { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8609     { Bad_Opcode },
8610   },
8611   /* VEX_0F38 */
8612   {
8613     /* 00 */
8614     { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8615     { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8616     { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8617     { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8618     { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8619     { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8620     { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8621     { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8622     /* 08 */
8623     { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8624     { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8625     { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8626     { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8627     { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8628     { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8629     { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8630     { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8631     /* 10 */
8632     { Bad_Opcode },
8633     { Bad_Opcode },
8634     { Bad_Opcode },
8635     { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8636     { Bad_Opcode },
8637     { Bad_Opcode },
8638     { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8639     { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8640     /* 18 */
8641     { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8642     { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8643     { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8644     { Bad_Opcode },
8645     { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8646     { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8647     { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8648     { Bad_Opcode },
8649     /* 20 */
8650     { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8651     { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8652     { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8653     { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8654     { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8655     { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8656     { Bad_Opcode },
8657     { Bad_Opcode },
8658     /* 28 */
8659     { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8660     { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8661     { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8662     { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8663     { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8664     { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8665     { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8666     { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8667     /* 30 */
8668     { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8669     { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8670     { PREFIX_TABLE (PREFIX_VEX_0F3832) },
8671     { PREFIX_TABLE (PREFIX_VEX_0F3833) },
8672     { PREFIX_TABLE (PREFIX_VEX_0F3834) },
8673     { PREFIX_TABLE (PREFIX_VEX_0F3835) },
8674     { PREFIX_TABLE (PREFIX_VEX_0F3836) },
8675     { PREFIX_TABLE (PREFIX_VEX_0F3837) },
8676     /* 38 */
8677     { PREFIX_TABLE (PREFIX_VEX_0F3838) },
8678     { PREFIX_TABLE (PREFIX_VEX_0F3839) },
8679     { PREFIX_TABLE (PREFIX_VEX_0F383A) },
8680     { PREFIX_TABLE (PREFIX_VEX_0F383B) },
8681     { PREFIX_TABLE (PREFIX_VEX_0F383C) },
8682     { PREFIX_TABLE (PREFIX_VEX_0F383D) },
8683     { PREFIX_TABLE (PREFIX_VEX_0F383E) },
8684     { PREFIX_TABLE (PREFIX_VEX_0F383F) },
8685     /* 40 */
8686     { PREFIX_TABLE (PREFIX_VEX_0F3840) },
8687     { PREFIX_TABLE (PREFIX_VEX_0F3841) },
8688     { Bad_Opcode },
8689     { Bad_Opcode },
8690     { Bad_Opcode },
8691     { PREFIX_TABLE (PREFIX_VEX_0F3845) },
8692     { PREFIX_TABLE (PREFIX_VEX_0F3846) },
8693     { PREFIX_TABLE (PREFIX_VEX_0F3847) },
8694     /* 48 */
8695     { Bad_Opcode },
8696     { Bad_Opcode },
8697     { Bad_Opcode },
8698     { Bad_Opcode },
8699     { Bad_Opcode },
8700     { Bad_Opcode },
8701     { Bad_Opcode },
8702     { Bad_Opcode },
8703     /* 50 */
8704     { Bad_Opcode },
8705     { Bad_Opcode },
8706     { Bad_Opcode },
8707     { Bad_Opcode },
8708     { Bad_Opcode },
8709     { Bad_Opcode },
8710     { Bad_Opcode },
8711     { Bad_Opcode },
8712     /* 58 */
8713     { PREFIX_TABLE (PREFIX_VEX_0F3858) },
8714     { PREFIX_TABLE (PREFIX_VEX_0F3859) },
8715     { PREFIX_TABLE (PREFIX_VEX_0F385A) },
8716     { Bad_Opcode },
8717     { Bad_Opcode },
8718     { Bad_Opcode },
8719     { Bad_Opcode },
8720     { Bad_Opcode },
8721     /* 60 */
8722     { Bad_Opcode },
8723     { Bad_Opcode },
8724     { Bad_Opcode },
8725     { Bad_Opcode },
8726     { Bad_Opcode },
8727     { Bad_Opcode },
8728     { Bad_Opcode },
8729     { Bad_Opcode },
8730     /* 68 */
8731     { Bad_Opcode },
8732     { Bad_Opcode },
8733     { Bad_Opcode },
8734     { Bad_Opcode },
8735     { Bad_Opcode },
8736     { Bad_Opcode },
8737     { Bad_Opcode },
8738     { Bad_Opcode },
8739     /* 70 */
8740     { Bad_Opcode },
8741     { Bad_Opcode },
8742     { Bad_Opcode },
8743     { Bad_Opcode },
8744     { Bad_Opcode },
8745     { Bad_Opcode },
8746     { Bad_Opcode },
8747     { Bad_Opcode },
8748     /* 78 */
8749     { PREFIX_TABLE (PREFIX_VEX_0F3878) },
8750     { PREFIX_TABLE (PREFIX_VEX_0F3879) },
8751     { Bad_Opcode },
8752     { Bad_Opcode },
8753     { Bad_Opcode },
8754     { Bad_Opcode },
8755     { Bad_Opcode },
8756     { Bad_Opcode },
8757     /* 80 */
8758     { Bad_Opcode },
8759     { Bad_Opcode },
8760     { Bad_Opcode },
8761     { Bad_Opcode },
8762     { Bad_Opcode },
8763     { Bad_Opcode },
8764     { Bad_Opcode },
8765     { Bad_Opcode },
8766     /* 88 */
8767     { Bad_Opcode },
8768     { Bad_Opcode },
8769     { Bad_Opcode },
8770     { Bad_Opcode },
8771     { PREFIX_TABLE (PREFIX_VEX_0F388C) },
8772     { Bad_Opcode },
8773     { PREFIX_TABLE (PREFIX_VEX_0F388E) },
8774     { Bad_Opcode },
8775     /* 90 */
8776     { PREFIX_TABLE (PREFIX_VEX_0F3890) },
8777     { PREFIX_TABLE (PREFIX_VEX_0F3891) },
8778     { PREFIX_TABLE (PREFIX_VEX_0F3892) },
8779     { PREFIX_TABLE (PREFIX_VEX_0F3893) },
8780     { Bad_Opcode },
8781     { Bad_Opcode },
8782     { PREFIX_TABLE (PREFIX_VEX_0F3896) },
8783     { PREFIX_TABLE (PREFIX_VEX_0F3897) },
8784     /* 98 */
8785     { PREFIX_TABLE (PREFIX_VEX_0F3898) },
8786     { PREFIX_TABLE (PREFIX_VEX_0F3899) },
8787     { PREFIX_TABLE (PREFIX_VEX_0F389A) },
8788     { PREFIX_TABLE (PREFIX_VEX_0F389B) },
8789     { PREFIX_TABLE (PREFIX_VEX_0F389C) },
8790     { PREFIX_TABLE (PREFIX_VEX_0F389D) },
8791     { PREFIX_TABLE (PREFIX_VEX_0F389E) },
8792     { PREFIX_TABLE (PREFIX_VEX_0F389F) },
8793     /* a0 */
8794     { Bad_Opcode },
8795     { Bad_Opcode },
8796     { Bad_Opcode },
8797     { Bad_Opcode },
8798     { Bad_Opcode },
8799     { Bad_Opcode },
8800     { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
8801     { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
8802     /* a8 */
8803     { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
8804     { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
8805     { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
8806     { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
8807     { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
8808     { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
8809     { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
8810     { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
8811     /* b0 */
8812     { Bad_Opcode },
8813     { Bad_Opcode },
8814     { Bad_Opcode },
8815     { Bad_Opcode },
8816     { Bad_Opcode },
8817     { Bad_Opcode },
8818     { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
8819     { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
8820     /* b8 */
8821     { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
8822     { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
8823     { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
8824     { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
8825     { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
8826     { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
8827     { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
8828     { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
8829     /* c0 */
8830     { Bad_Opcode },
8831     { Bad_Opcode },
8832     { Bad_Opcode },
8833     { Bad_Opcode },
8834     { Bad_Opcode },
8835     { Bad_Opcode },
8836     { Bad_Opcode },
8837     { Bad_Opcode },
8838     /* c8 */
8839     { Bad_Opcode },
8840     { Bad_Opcode },
8841     { Bad_Opcode },
8842     { Bad_Opcode },
8843     { Bad_Opcode },
8844     { Bad_Opcode },
8845     { Bad_Opcode },
8846     { Bad_Opcode },
8847     /* d0 */
8848     { Bad_Opcode },
8849     { Bad_Opcode },
8850     { Bad_Opcode },
8851     { Bad_Opcode },
8852     { Bad_Opcode },
8853     { Bad_Opcode },
8854     { Bad_Opcode },
8855     { Bad_Opcode },
8856     /* d8 */
8857     { Bad_Opcode },
8858     { Bad_Opcode },
8859     { Bad_Opcode },
8860     { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
8861     { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
8862     { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
8863     { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
8864     { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
8865     /* e0 */
8866     { Bad_Opcode },
8867     { Bad_Opcode },
8868     { Bad_Opcode },
8869     { Bad_Opcode },
8870     { Bad_Opcode },
8871     { Bad_Opcode },
8872     { Bad_Opcode },
8873     { Bad_Opcode },
8874     /* e8 */
8875     { Bad_Opcode },
8876     { Bad_Opcode },
8877     { Bad_Opcode },
8878     { Bad_Opcode },
8879     { Bad_Opcode },
8880     { Bad_Opcode },
8881     { Bad_Opcode },
8882     { Bad_Opcode },
8883     /* f0 */
8884     { Bad_Opcode },
8885     { Bad_Opcode },
8886     { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
8887     { REG_TABLE (REG_VEX_0F38F3) },
8888     { Bad_Opcode },
8889     { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
8890     { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
8891     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
8892     /* f8 */
8893     { Bad_Opcode },
8894     { Bad_Opcode },
8895     { Bad_Opcode },
8896     { Bad_Opcode },
8897     { Bad_Opcode },
8898     { Bad_Opcode },
8899     { Bad_Opcode },
8900     { Bad_Opcode },
8901   },
8902   /* VEX_0F3A */
8903   {
8904     /* 00 */
8905     { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
8906     { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
8907     { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
8908     { Bad_Opcode },
8909     { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
8910     { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
8911     { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
8912     { Bad_Opcode },
8913     /* 08 */
8914     { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
8915     { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
8916     { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
8917     { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
8918     { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
8919     { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
8920     { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
8921     { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
8922     /* 10 */
8923     { Bad_Opcode },
8924     { Bad_Opcode },
8925     { Bad_Opcode },
8926     { Bad_Opcode },
8927     { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
8928     { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
8929     { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
8930     { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
8931     /* 18 */
8932     { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
8933     { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
8934     { Bad_Opcode },
8935     { Bad_Opcode },
8936     { Bad_Opcode },
8937     { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
8938     { Bad_Opcode },
8939     { Bad_Opcode },
8940     /* 20 */
8941     { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
8942     { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
8943     { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
8944     { Bad_Opcode },
8945     { Bad_Opcode },
8946     { Bad_Opcode },
8947     { Bad_Opcode },
8948     { Bad_Opcode },
8949     /* 28 */
8950     { Bad_Opcode },
8951     { Bad_Opcode },
8952     { Bad_Opcode },
8953     { Bad_Opcode },
8954     { Bad_Opcode },
8955     { Bad_Opcode },
8956     { Bad_Opcode },
8957     { Bad_Opcode },
8958     /* 30 */
8959     { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
8960     { Bad_Opcode },
8961     { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
8962     { Bad_Opcode },
8963     { Bad_Opcode },
8964     { Bad_Opcode },
8965     { Bad_Opcode },
8966     { Bad_Opcode },
8967     /* 38 */
8968     { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
8969     { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
8970     { Bad_Opcode },
8971     { Bad_Opcode },
8972     { Bad_Opcode },
8973     { Bad_Opcode },
8974     { Bad_Opcode },
8975     { Bad_Opcode },
8976     /* 40 */
8977     { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
8978     { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
8979     { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
8980     { Bad_Opcode },
8981     { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
8982     { Bad_Opcode },
8983     { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
8984     { Bad_Opcode },
8985     /* 48 */
8986     { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
8987     { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
8988     { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
8989     { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
8990     { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
8991     { Bad_Opcode },
8992     { Bad_Opcode },
8993     { Bad_Opcode },
8994     /* 50 */
8995     { Bad_Opcode },
8996     { Bad_Opcode },
8997     { Bad_Opcode },
8998     { Bad_Opcode },
8999     { Bad_Opcode },
9000     { Bad_Opcode },
9001     { Bad_Opcode },
9002     { Bad_Opcode },
9003     /* 58 */
9004     { Bad_Opcode },
9005     { Bad_Opcode },
9006     { Bad_Opcode },
9007     { Bad_Opcode },
9008     { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9009     { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9010     { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9011     { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9012     /* 60 */
9013     { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9014     { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9015     { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9016     { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9017     { Bad_Opcode },
9018     { Bad_Opcode },
9019     { Bad_Opcode },
9020     { Bad_Opcode },
9021     /* 68 */
9022     { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9023     { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9024     { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9025     { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9026     { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9027     { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9028     { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9029     { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9030     /* 70 */
9031     { Bad_Opcode },
9032     { Bad_Opcode },
9033     { Bad_Opcode },
9034     { Bad_Opcode },
9035     { Bad_Opcode },
9036     { Bad_Opcode },
9037     { Bad_Opcode },
9038     { Bad_Opcode },
9039     /* 78 */
9040     { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9041     { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9042     { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9043     { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9044     { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9045     { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9046     { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9047     { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9048     /* 80 */
9049     { Bad_Opcode },
9050     { Bad_Opcode },
9051     { Bad_Opcode },
9052     { Bad_Opcode },
9053     { Bad_Opcode },
9054     { Bad_Opcode },
9055     { Bad_Opcode },
9056     { Bad_Opcode },
9057     /* 88 */
9058     { Bad_Opcode },
9059     { Bad_Opcode },
9060     { Bad_Opcode },
9061     { Bad_Opcode },
9062     { Bad_Opcode },
9063     { Bad_Opcode },
9064     { Bad_Opcode },
9065     { Bad_Opcode },
9066     /* 90 */
9067     { Bad_Opcode },
9068     { Bad_Opcode },
9069     { Bad_Opcode },
9070     { Bad_Opcode },
9071     { Bad_Opcode },
9072     { Bad_Opcode },
9073     { Bad_Opcode },
9074     { Bad_Opcode },
9075     /* 98 */
9076     { Bad_Opcode },
9077     { Bad_Opcode },
9078     { Bad_Opcode },
9079     { Bad_Opcode },
9080     { Bad_Opcode },
9081     { Bad_Opcode },
9082     { Bad_Opcode },
9083     { Bad_Opcode },
9084     /* a0 */
9085     { Bad_Opcode },
9086     { Bad_Opcode },
9087     { Bad_Opcode },
9088     { Bad_Opcode },
9089     { Bad_Opcode },
9090     { Bad_Opcode },
9091     { Bad_Opcode },
9092     { Bad_Opcode },
9093     /* a8 */
9094     { Bad_Opcode },
9095     { Bad_Opcode },
9096     { Bad_Opcode },
9097     { Bad_Opcode },
9098     { Bad_Opcode },
9099     { Bad_Opcode },
9100     { Bad_Opcode },
9101     { Bad_Opcode },
9102     /* b0 */
9103     { Bad_Opcode },
9104     { Bad_Opcode },
9105     { Bad_Opcode },
9106     { Bad_Opcode },
9107     { Bad_Opcode },
9108     { Bad_Opcode },
9109     { Bad_Opcode },
9110     { Bad_Opcode },
9111     /* b8 */
9112     { Bad_Opcode },
9113     { Bad_Opcode },
9114     { Bad_Opcode },
9115     { Bad_Opcode },
9116     { Bad_Opcode },
9117     { Bad_Opcode },
9118     { Bad_Opcode },
9119     { Bad_Opcode },
9120     /* c0 */
9121     { Bad_Opcode },
9122     { Bad_Opcode },
9123     { Bad_Opcode },
9124     { Bad_Opcode },
9125     { Bad_Opcode },
9126     { Bad_Opcode },
9127     { Bad_Opcode },
9128     { Bad_Opcode },
9129     /* c8 */
9130     { Bad_Opcode },
9131     { Bad_Opcode },
9132     { Bad_Opcode },
9133     { Bad_Opcode },
9134     { Bad_Opcode },
9135     { Bad_Opcode },
9136     { Bad_Opcode },
9137     { Bad_Opcode },
9138     /* d0 */
9139     { Bad_Opcode },
9140     { Bad_Opcode },
9141     { Bad_Opcode },
9142     { Bad_Opcode },
9143     { Bad_Opcode },
9144     { Bad_Opcode },
9145     { Bad_Opcode },
9146     { Bad_Opcode },
9147     /* d8 */
9148     { Bad_Opcode },
9149     { Bad_Opcode },
9150     { Bad_Opcode },
9151     { Bad_Opcode },
9152     { Bad_Opcode },
9153     { Bad_Opcode },
9154     { Bad_Opcode },
9155     { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9156     /* e0 */
9157     { Bad_Opcode },
9158     { Bad_Opcode },
9159     { Bad_Opcode },
9160     { Bad_Opcode },
9161     { Bad_Opcode },
9162     { Bad_Opcode },
9163     { Bad_Opcode },
9164     { Bad_Opcode },
9165     /* e8 */
9166     { Bad_Opcode },
9167     { Bad_Opcode },
9168     { Bad_Opcode },
9169     { Bad_Opcode },
9170     { Bad_Opcode },
9171     { Bad_Opcode },
9172     { Bad_Opcode },
9173     { Bad_Opcode },
9174     /* f0 */
9175     { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9176     { Bad_Opcode },
9177     { Bad_Opcode },
9178     { Bad_Opcode },
9179     { Bad_Opcode },
9180     { Bad_Opcode },
9181     { Bad_Opcode },
9182     { Bad_Opcode },
9183     /* f8 */
9184     { Bad_Opcode },
9185     { Bad_Opcode },
9186     { Bad_Opcode },
9187     { Bad_Opcode },
9188     { Bad_Opcode },
9189     { Bad_Opcode },
9190     { Bad_Opcode },
9191     { Bad_Opcode },
9192   },
9193 };
9194
9195 #define NEED_OPCODE_TABLE
9196 #include "i386-dis-evex.h"
9197 #undef NEED_OPCODE_TABLE
9198 static const struct dis386 vex_len_table[][2] = {
9199   /* VEX_LEN_0F10_P_1 */
9200   {
9201     { VEX_W_TABLE (VEX_W_0F10_P_1) },
9202     { VEX_W_TABLE (VEX_W_0F10_P_1) },
9203   },
9204
9205   /* VEX_LEN_0F10_P_3 */
9206   {
9207     { VEX_W_TABLE (VEX_W_0F10_P_3) },
9208     { VEX_W_TABLE (VEX_W_0F10_P_3) },
9209   },
9210
9211   /* VEX_LEN_0F11_P_1 */
9212   {
9213     { VEX_W_TABLE (VEX_W_0F11_P_1) },
9214     { VEX_W_TABLE (VEX_W_0F11_P_1) },
9215   },
9216
9217   /* VEX_LEN_0F11_P_3 */
9218   {
9219     { VEX_W_TABLE (VEX_W_0F11_P_3) },
9220     { VEX_W_TABLE (VEX_W_0F11_P_3) },
9221   },
9222
9223   /* VEX_LEN_0F12_P_0_M_0 */
9224   {
9225     { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) },
9226   },
9227
9228   /* VEX_LEN_0F12_P_0_M_1 */
9229   {
9230     { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) },
9231   },
9232
9233   /* VEX_LEN_0F12_P_2 */
9234   {
9235     { VEX_W_TABLE (VEX_W_0F12_P_2) },
9236   },
9237
9238   /* VEX_LEN_0F13_M_0 */
9239   {
9240     { VEX_W_TABLE (VEX_W_0F13_M_0) },
9241   },
9242
9243   /* VEX_LEN_0F16_P_0_M_0 */
9244   {
9245     { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) },
9246   },
9247
9248   /* VEX_LEN_0F16_P_0_M_1 */
9249   {
9250     { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) },
9251   },
9252
9253   /* VEX_LEN_0F16_P_2 */
9254   {
9255     { VEX_W_TABLE (VEX_W_0F16_P_2) },
9256   },
9257
9258   /* VEX_LEN_0F17_M_0 */
9259   {
9260     { VEX_W_TABLE (VEX_W_0F17_M_0) },
9261   },
9262
9263   /* VEX_LEN_0F2A_P_1 */
9264   {
9265     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev } },
9266     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev } },
9267   },
9268
9269   /* VEX_LEN_0F2A_P_3 */
9270   {
9271     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev } },
9272     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev } },
9273   },
9274
9275   /* VEX_LEN_0F2C_P_1 */
9276   {
9277     { "vcvttss2siY",    { Gv, EXdScalar } },
9278     { "vcvttss2siY",    { Gv, EXdScalar } },
9279   },
9280
9281   /* VEX_LEN_0F2C_P_3 */
9282   {
9283     { "vcvttsd2siY",    { Gv, EXqScalar } },
9284     { "vcvttsd2siY",    { Gv, EXqScalar } },
9285   },
9286
9287   /* VEX_LEN_0F2D_P_1 */
9288   {
9289     { "vcvtss2siY",     { Gv, EXdScalar } },
9290     { "vcvtss2siY",     { Gv, EXdScalar } },
9291   },
9292
9293   /* VEX_LEN_0F2D_P_3 */
9294   {
9295     { "vcvtsd2siY",     { Gv, EXqScalar } },
9296     { "vcvtsd2siY",     { Gv, EXqScalar } },
9297   },
9298
9299   /* VEX_LEN_0F2E_P_0 */
9300   {
9301     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9302     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9303   },
9304
9305   /* VEX_LEN_0F2E_P_2 */
9306   {
9307     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9308     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9309   },
9310
9311   /* VEX_LEN_0F2F_P_0 */
9312   {
9313     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9314     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9315   },
9316
9317   /* VEX_LEN_0F2F_P_2 */
9318   {
9319     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9320     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9321   },
9322
9323   /* VEX_LEN_0F41_P_0 */
9324   {
9325     { Bad_Opcode },
9326     { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9327   },
9328   /* VEX_LEN_0F42_P_0 */
9329   {
9330     { Bad_Opcode },
9331     { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9332   },
9333   /* VEX_LEN_0F44_P_0 */
9334   {
9335     { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9336   },
9337   /* VEX_LEN_0F45_P_0 */
9338   {
9339     { Bad_Opcode },
9340     { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9341   },
9342   /* VEX_LEN_0F46_P_0 */
9343   {
9344     { Bad_Opcode },
9345     { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9346   },
9347   /* VEX_LEN_0F47_P_0 */
9348   {
9349     { Bad_Opcode },
9350     { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9351   },
9352   /* VEX_LEN_0F4B_P_2 */
9353   {
9354     { Bad_Opcode },
9355     { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9356   },
9357
9358   /* VEX_LEN_0F51_P_1 */
9359   {
9360     { VEX_W_TABLE (VEX_W_0F51_P_1) },
9361     { VEX_W_TABLE (VEX_W_0F51_P_1) },
9362   },
9363
9364   /* VEX_LEN_0F51_P_3 */
9365   {
9366     { VEX_W_TABLE (VEX_W_0F51_P_3) },
9367     { VEX_W_TABLE (VEX_W_0F51_P_3) },
9368   },
9369
9370   /* VEX_LEN_0F52_P_1 */
9371   {
9372     { VEX_W_TABLE (VEX_W_0F52_P_1) },
9373     { VEX_W_TABLE (VEX_W_0F52_P_1) },
9374   },
9375
9376   /* VEX_LEN_0F53_P_1 */
9377   {
9378     { VEX_W_TABLE (VEX_W_0F53_P_1) },
9379     { VEX_W_TABLE (VEX_W_0F53_P_1) },
9380   },
9381
9382   /* VEX_LEN_0F58_P_1 */
9383   {
9384     { VEX_W_TABLE (VEX_W_0F58_P_1) },
9385     { VEX_W_TABLE (VEX_W_0F58_P_1) },
9386   },
9387
9388   /* VEX_LEN_0F58_P_3 */
9389   {
9390     { VEX_W_TABLE (VEX_W_0F58_P_3) },
9391     { VEX_W_TABLE (VEX_W_0F58_P_3) },
9392   },
9393
9394   /* VEX_LEN_0F59_P_1 */
9395   {
9396     { VEX_W_TABLE (VEX_W_0F59_P_1) },
9397     { VEX_W_TABLE (VEX_W_0F59_P_1) },
9398   },
9399
9400   /* VEX_LEN_0F59_P_3 */
9401   {
9402     { VEX_W_TABLE (VEX_W_0F59_P_3) },
9403     { VEX_W_TABLE (VEX_W_0F59_P_3) },
9404   },
9405
9406   /* VEX_LEN_0F5A_P_1 */
9407   {
9408     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9409     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9410   },
9411
9412   /* VEX_LEN_0F5A_P_3 */
9413   {
9414     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9415     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9416   },
9417
9418   /* VEX_LEN_0F5C_P_1 */
9419   {
9420     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9421     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9422   },
9423
9424   /* VEX_LEN_0F5C_P_3 */
9425   {
9426     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9427     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9428   },
9429
9430   /* VEX_LEN_0F5D_P_1 */
9431   {
9432     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9433     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9434   },
9435
9436   /* VEX_LEN_0F5D_P_3 */
9437   {
9438     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9439     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9440   },
9441
9442   /* VEX_LEN_0F5E_P_1 */
9443   {
9444     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9445     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9446   },
9447
9448   /* VEX_LEN_0F5E_P_3 */
9449   {
9450     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9451     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9452   },
9453
9454   /* VEX_LEN_0F5F_P_1 */
9455   {
9456     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9457     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9458   },
9459
9460   /* VEX_LEN_0F5F_P_3 */
9461   {
9462     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9463     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9464   },
9465
9466   /* VEX_LEN_0F6E_P_2 */
9467   {
9468     { "vmovK",          { XMScalar, Edq } },
9469     { "vmovK",          { XMScalar, Edq } },
9470   },
9471
9472   /* VEX_LEN_0F7E_P_1 */
9473   {
9474     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9475     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9476   },
9477
9478   /* VEX_LEN_0F7E_P_2 */
9479   {
9480     { "vmovK",          { Edq, XMScalar } },
9481     { "vmovK",          { Edq, XMScalar } },
9482   },
9483
9484   /* VEX_LEN_0F90_P_0 */
9485   {
9486     { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9487   },
9488
9489   /* VEX_LEN_0F91_P_0 */
9490   {
9491     { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9492   },
9493
9494   /* VEX_LEN_0F92_P_0 */
9495   {
9496     { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9497   },
9498
9499   /* VEX_LEN_0F93_P_0 */
9500   {
9501     { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9502   },
9503
9504   /* VEX_LEN_0F98_P_0 */
9505   {
9506     { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9507   },
9508
9509   /* VEX_LEN_0FAE_R_2_M_0 */
9510   {
9511     { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) },
9512   },
9513
9514   /* VEX_LEN_0FAE_R_3_M_0 */
9515   {
9516     { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) },
9517   },
9518
9519   /* VEX_LEN_0FC2_P_1 */
9520   {
9521     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9522     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9523   },
9524
9525   /* VEX_LEN_0FC2_P_3 */
9526   {
9527     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9528     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9529   },
9530
9531   /* VEX_LEN_0FC4_P_2 */
9532   {
9533     { VEX_W_TABLE (VEX_W_0FC4_P_2) },
9534   },
9535
9536   /* VEX_LEN_0FC5_P_2 */
9537   {
9538     { VEX_W_TABLE (VEX_W_0FC5_P_2) },
9539   },
9540
9541   /* VEX_LEN_0FD6_P_2 */
9542   {
9543     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9544     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9545   },
9546
9547   /* VEX_LEN_0FF7_P_2 */
9548   {
9549     { VEX_W_TABLE (VEX_W_0FF7_P_2) },
9550   },
9551
9552   /* VEX_LEN_0F3816_P_2 */
9553   {
9554     { Bad_Opcode },
9555     { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9556   },
9557
9558   /* VEX_LEN_0F3819_P_2 */
9559   {
9560     { Bad_Opcode },
9561     { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9562   },
9563
9564   /* VEX_LEN_0F381A_P_2_M_0 */
9565   {
9566     { Bad_Opcode },
9567     { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9568   },
9569
9570   /* VEX_LEN_0F3836_P_2 */
9571   {
9572     { Bad_Opcode },
9573     { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9574   },
9575
9576   /* VEX_LEN_0F3841_P_2 */
9577   {
9578     { VEX_W_TABLE (VEX_W_0F3841_P_2) },
9579   },
9580
9581   /* VEX_LEN_0F385A_P_2_M_0 */
9582   {
9583     { Bad_Opcode },
9584     { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
9585   },
9586
9587   /* VEX_LEN_0F38DB_P_2 */
9588   {
9589     { VEX_W_TABLE (VEX_W_0F38DB_P_2) },
9590   },
9591
9592   /* VEX_LEN_0F38DC_P_2 */
9593   {
9594     { VEX_W_TABLE (VEX_W_0F38DC_P_2) },
9595   },
9596
9597   /* VEX_LEN_0F38DD_P_2 */
9598   {
9599     { VEX_W_TABLE (VEX_W_0F38DD_P_2) },
9600   },
9601
9602   /* VEX_LEN_0F38DE_P_2 */
9603   {
9604     { VEX_W_TABLE (VEX_W_0F38DE_P_2) },
9605   },
9606
9607   /* VEX_LEN_0F38DF_P_2 */
9608   {
9609     { VEX_W_TABLE (VEX_W_0F38DF_P_2) },
9610   },
9611
9612   /* VEX_LEN_0F38F2_P_0 */
9613   {
9614     { "andnS",          { Gdq, VexGdq, Edq } },
9615   },
9616
9617   /* VEX_LEN_0F38F3_R_1_P_0 */
9618   {
9619     { "blsrS",          { VexGdq, Edq } },
9620   },
9621
9622   /* VEX_LEN_0F38F3_R_2_P_0 */
9623   {
9624     { "blsmskS",        { VexGdq, Edq } },
9625   },
9626
9627   /* VEX_LEN_0F38F3_R_3_P_0 */
9628   {
9629     { "blsiS",          { VexGdq, Edq } },
9630   },
9631
9632   /* VEX_LEN_0F38F5_P_0 */
9633   {
9634     { "bzhiS",          { Gdq, Edq, VexGdq } },
9635   },
9636
9637   /* VEX_LEN_0F38F5_P_1 */
9638   {
9639     { "pextS",          { Gdq, VexGdq, Edq } },
9640   },
9641
9642   /* VEX_LEN_0F38F5_P_3 */
9643   {
9644     { "pdepS",          { Gdq, VexGdq, Edq } },
9645   },
9646
9647   /* VEX_LEN_0F38F6_P_3 */
9648   {
9649     { "mulxS",          { Gdq, VexGdq, Edq } },
9650   },
9651
9652   /* VEX_LEN_0F38F7_P_0 */
9653   {
9654     { "bextrS",         { Gdq, Edq, VexGdq } },
9655   },
9656
9657   /* VEX_LEN_0F38F7_P_1 */
9658   {
9659     { "sarxS",          { Gdq, Edq, VexGdq } },
9660   },
9661
9662   /* VEX_LEN_0F38F7_P_2 */
9663   {
9664     { "shlxS",          { Gdq, Edq, VexGdq } },
9665   },
9666
9667   /* VEX_LEN_0F38F7_P_3 */
9668   {
9669     { "shrxS",          { Gdq, Edq, VexGdq } },
9670   },
9671
9672   /* VEX_LEN_0F3A00_P_2 */
9673   {
9674     { Bad_Opcode },
9675     { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
9676   },
9677
9678   /* VEX_LEN_0F3A01_P_2 */
9679   {
9680     { Bad_Opcode },
9681     { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
9682   },
9683
9684   /* VEX_LEN_0F3A06_P_2 */
9685   {
9686     { Bad_Opcode },
9687     { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
9688   },
9689
9690   /* VEX_LEN_0F3A0A_P_2 */
9691   {
9692     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
9693     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
9694   },
9695
9696   /* VEX_LEN_0F3A0B_P_2 */
9697   {
9698     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
9699     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
9700   },
9701
9702   /* VEX_LEN_0F3A14_P_2 */
9703   {
9704     { VEX_W_TABLE (VEX_W_0F3A14_P_2) },
9705   },
9706
9707   /* VEX_LEN_0F3A15_P_2 */
9708   {
9709     { VEX_W_TABLE (VEX_W_0F3A15_P_2) },
9710   },
9711
9712   /* VEX_LEN_0F3A16_P_2  */
9713   {
9714     { "vpextrK",        { Edq, XM, Ib } },
9715   },
9716
9717   /* VEX_LEN_0F3A17_P_2 */
9718   {
9719     { "vextractps",     { Edqd, XM, Ib } },
9720   },
9721
9722   /* VEX_LEN_0F3A18_P_2 */
9723   {
9724     { Bad_Opcode },
9725     { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
9726   },
9727
9728   /* VEX_LEN_0F3A19_P_2 */
9729   {
9730     { Bad_Opcode },
9731     { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
9732   },
9733
9734   /* VEX_LEN_0F3A20_P_2 */
9735   {
9736     { VEX_W_TABLE (VEX_W_0F3A20_P_2) },
9737   },
9738
9739   /* VEX_LEN_0F3A21_P_2 */
9740   {
9741     { VEX_W_TABLE (VEX_W_0F3A21_P_2) },
9742   },
9743
9744   /* VEX_LEN_0F3A22_P_2 */
9745   {
9746     { "vpinsrK",        { XM, Vex128, Edq, Ib } },
9747   },
9748
9749   /* VEX_LEN_0F3A30_P_2 */
9750   {
9751     { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
9752   },
9753
9754   /* VEX_LEN_0F3A32_P_2 */
9755   {
9756     { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
9757   },
9758
9759   /* VEX_LEN_0F3A38_P_2 */
9760   {
9761     { Bad_Opcode },
9762     { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
9763   },
9764
9765   /* VEX_LEN_0F3A39_P_2 */
9766   {
9767     { Bad_Opcode },
9768     { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
9769   },
9770
9771   /* VEX_LEN_0F3A41_P_2 */
9772   {
9773     { VEX_W_TABLE (VEX_W_0F3A41_P_2) },
9774   },
9775
9776   /* VEX_LEN_0F3A44_P_2 */
9777   {
9778     { VEX_W_TABLE (VEX_W_0F3A44_P_2) },
9779   },
9780
9781   /* VEX_LEN_0F3A46_P_2 */
9782   {
9783     { Bad_Opcode },
9784     { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
9785   },
9786
9787   /* VEX_LEN_0F3A60_P_2 */
9788   {
9789     { VEX_W_TABLE (VEX_W_0F3A60_P_2) },
9790   },
9791
9792   /* VEX_LEN_0F3A61_P_2 */
9793   {
9794     { VEX_W_TABLE (VEX_W_0F3A61_P_2) },
9795   },
9796
9797   /* VEX_LEN_0F3A62_P_2 */
9798   {
9799     { VEX_W_TABLE (VEX_W_0F3A62_P_2) },
9800   },
9801
9802   /* VEX_LEN_0F3A63_P_2 */
9803   {
9804     { VEX_W_TABLE (VEX_W_0F3A63_P_2) },
9805   },
9806
9807   /* VEX_LEN_0F3A6A_P_2 */
9808   {
9809     { "vfmaddss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9810   },
9811
9812   /* VEX_LEN_0F3A6B_P_2 */
9813   {
9814     { "vfmaddsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9815   },
9816
9817   /* VEX_LEN_0F3A6E_P_2 */
9818   {
9819     { "vfmsubss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9820   },
9821
9822   /* VEX_LEN_0F3A6F_P_2 */
9823   {
9824     { "vfmsubsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9825   },
9826
9827   /* VEX_LEN_0F3A7A_P_2 */
9828   {
9829     { "vfnmaddss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9830   },
9831
9832   /* VEX_LEN_0F3A7B_P_2 */
9833   {
9834     { "vfnmaddsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9835   },
9836
9837   /* VEX_LEN_0F3A7E_P_2 */
9838   {
9839     { "vfnmsubss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9840   },
9841
9842   /* VEX_LEN_0F3A7F_P_2 */
9843   {
9844     { "vfnmsubsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9845   },
9846
9847   /* VEX_LEN_0F3ADF_P_2 */
9848   {
9849     { VEX_W_TABLE (VEX_W_0F3ADF_P_2) },
9850   },
9851
9852   /* VEX_LEN_0F3AF0_P_3 */
9853   {
9854     { "rorxS",          { Gdq, Edq, Ib } },
9855   },
9856
9857   /* VEX_LEN_0FXOP_08_CC */
9858   {
9859      { "vpcomb",        { XM, Vex128, EXx, Ib } },
9860   },
9861
9862   /* VEX_LEN_0FXOP_08_CD */
9863   {
9864      { "vpcomw",        { XM, Vex128, EXx, Ib } },
9865   },
9866
9867   /* VEX_LEN_0FXOP_08_CE */
9868   {
9869      { "vpcomd",        { XM, Vex128, EXx, Ib } },
9870   },
9871
9872   /* VEX_LEN_0FXOP_08_CF */
9873   {
9874      { "vpcomq",        { XM, Vex128, EXx, Ib } },
9875   },
9876
9877   /* VEX_LEN_0FXOP_08_EC */
9878   {
9879      { "vpcomub",       { XM, Vex128, EXx, Ib } },
9880   },
9881
9882   /* VEX_LEN_0FXOP_08_ED */
9883   {
9884      { "vpcomuw",       { XM, Vex128, EXx, Ib } },
9885   },
9886
9887   /* VEX_LEN_0FXOP_08_EE */
9888   {
9889      { "vpcomud",       { XM, Vex128, EXx, Ib } },
9890   },
9891
9892   /* VEX_LEN_0FXOP_08_EF */
9893   {
9894      { "vpcomuq",       { XM, Vex128, EXx, Ib } },
9895   },
9896
9897   /* VEX_LEN_0FXOP_09_80 */
9898   {
9899     { "vfrczps",        { XM, EXxmm } },
9900     { "vfrczps",        { XM, EXymmq } },
9901   },
9902
9903   /* VEX_LEN_0FXOP_09_81 */
9904   {
9905     { "vfrczpd",        { XM, EXxmm } },
9906     { "vfrczpd",        { XM, EXymmq } },
9907   },
9908 };
9909
9910 static const struct dis386 vex_w_table[][2] = {
9911   {
9912     /* VEX_W_0F10_P_0 */
9913     { "vmovups",        { XM, EXx } },
9914   },
9915   {
9916     /* VEX_W_0F10_P_1 */
9917     { "vmovss",         { XMVexScalar, VexScalar, EXdScalar } },
9918   },
9919   {
9920     /* VEX_W_0F10_P_2 */
9921     { "vmovupd",        { XM, EXx } },
9922   },
9923   {
9924     /* VEX_W_0F10_P_3 */
9925     { "vmovsd",         { XMVexScalar, VexScalar, EXqScalar } },
9926   },
9927   {
9928     /* VEX_W_0F11_P_0 */
9929     { "vmovups",        { EXxS, XM } },
9930   },
9931   {
9932     /* VEX_W_0F11_P_1 */
9933     { "vmovss",         { EXdVexScalarS, VexScalar, XMScalar } },
9934   },
9935   {
9936     /* VEX_W_0F11_P_2 */
9937     { "vmovupd",        { EXxS, XM } },
9938   },
9939   {
9940     /* VEX_W_0F11_P_3 */
9941     { "vmovsd",         { EXqVexScalarS, VexScalar, XMScalar } },
9942   },
9943   {
9944     /* VEX_W_0F12_P_0_M_0 */
9945     { "vmovlps",        { XM, Vex128, EXq } },
9946   },
9947   {
9948     /* VEX_W_0F12_P_0_M_1 */
9949     { "vmovhlps",       { XM, Vex128, EXq } },
9950   },
9951   {
9952     /* VEX_W_0F12_P_1 */
9953     { "vmovsldup",      { XM, EXx } },
9954   },
9955   {
9956     /* VEX_W_0F12_P_2 */
9957     { "vmovlpd",        { XM, Vex128, EXq } },
9958   },
9959   {
9960     /* VEX_W_0F12_P_3 */
9961     { "vmovddup",       { XM, EXymmq } },
9962   },
9963   {
9964     /* VEX_W_0F13_M_0 */
9965     { "vmovlpX",        { EXq, XM } },
9966   },
9967   {
9968     /* VEX_W_0F14 */
9969     { "vunpcklpX",      { XM, Vex, EXx } },
9970   },
9971   {
9972     /* VEX_W_0F15 */
9973     { "vunpckhpX",      { XM, Vex, EXx } },
9974   },
9975   {
9976     /* VEX_W_0F16_P_0_M_0 */
9977     { "vmovhps",        { XM, Vex128, EXq } },
9978   },
9979   {
9980     /* VEX_W_0F16_P_0_M_1 */
9981     { "vmovlhps",       { XM, Vex128, EXq } },
9982   },
9983   {
9984     /* VEX_W_0F16_P_1 */
9985     { "vmovshdup",      { XM, EXx } },
9986   },
9987   {
9988     /* VEX_W_0F16_P_2 */
9989     { "vmovhpd",        { XM, Vex128, EXq } },
9990   },
9991   {
9992     /* VEX_W_0F17_M_0 */
9993     { "vmovhpX",        { EXq, XM } },
9994   },
9995   {
9996     /* VEX_W_0F28 */
9997     { "vmovapX",        { XM, EXx } },
9998   },
9999   {
10000     /* VEX_W_0F29 */
10001     { "vmovapX",        { EXxS, XM } },
10002   },
10003   {
10004     /* VEX_W_0F2B_M_0 */
10005     { "vmovntpX",       { Mx, XM } },
10006   },
10007   {
10008     /* VEX_W_0F2E_P_0 */
10009     { "vucomiss",       { XMScalar, EXdScalar } },
10010   },
10011   {
10012     /* VEX_W_0F2E_P_2 */
10013     { "vucomisd",       { XMScalar, EXqScalar } },
10014   },
10015   {
10016     /* VEX_W_0F2F_P_0 */
10017     { "vcomiss",        { XMScalar, EXdScalar } },
10018   },
10019   {
10020     /* VEX_W_0F2F_P_2 */
10021     { "vcomisd",        { XMScalar, EXqScalar } },
10022   },
10023   {
10024     /* VEX_W_0F41_P_0_LEN_1 */
10025     { "kandw",          { MaskG, MaskVex, MaskR } },
10026   },
10027   {
10028     /* VEX_W_0F42_P_0_LEN_1 */
10029     { "kandnw",         { MaskG, MaskVex, MaskR } },
10030   },
10031   {
10032     /* VEX_W_0F44_P_0_LEN_0 */
10033     { "knotw",          { MaskG, MaskR } },
10034   },
10035   {
10036     /* VEX_W_0F45_P_0_LEN_1 */
10037     { "korw",           { MaskG, MaskVex, MaskR } },
10038   },
10039   {
10040     /* VEX_W_0F46_P_0_LEN_1 */
10041     { "kxnorw",         { MaskG, MaskVex, MaskR } },
10042   },
10043   {
10044     /* VEX_W_0F47_P_0_LEN_1 */
10045     { "kxorw",          { MaskG, MaskVex, MaskR } },
10046   },
10047   {
10048     /* VEX_W_0F4B_P_2_LEN_1 */
10049     { "kunpckbw",       { MaskG, MaskVex, MaskR } },
10050   },
10051   {
10052     /* VEX_W_0F50_M_0 */
10053     { "vmovmskpX",      { Gdq, XS } },
10054   },
10055   {
10056     /* VEX_W_0F51_P_0 */
10057     { "vsqrtps",        { XM, EXx } },
10058   },
10059   {
10060     /* VEX_W_0F51_P_1 */
10061     { "vsqrtss",        { XMScalar, VexScalar, EXdScalar } },
10062   },
10063   {
10064     /* VEX_W_0F51_P_2  */
10065     { "vsqrtpd",        { XM, EXx } },
10066   },
10067   {
10068     /* VEX_W_0F51_P_3 */
10069     { "vsqrtsd",        { XMScalar, VexScalar, EXqScalar } },
10070   },
10071   {
10072     /* VEX_W_0F52_P_0 */
10073     { "vrsqrtps",       { XM, EXx } },
10074   },
10075   {
10076     /* VEX_W_0F52_P_1 */
10077     { "vrsqrtss",       { XMScalar, VexScalar, EXdScalar } },
10078   },
10079   {
10080     /* VEX_W_0F53_P_0  */
10081     { "vrcpps",         { XM, EXx } },
10082   },
10083   {
10084     /* VEX_W_0F53_P_1  */
10085     { "vrcpss",         { XMScalar, VexScalar, EXdScalar } },
10086   },
10087   {
10088     /* VEX_W_0F58_P_0  */
10089     { "vaddps",         { XM, Vex, EXx } },
10090   },
10091   {
10092     /* VEX_W_0F58_P_1  */
10093     { "vaddss",         { XMScalar, VexScalar, EXdScalar } },
10094   },
10095   {
10096     /* VEX_W_0F58_P_2  */
10097     { "vaddpd",         { XM, Vex, EXx } },
10098   },
10099   {
10100     /* VEX_W_0F58_P_3  */
10101     { "vaddsd",         { XMScalar, VexScalar, EXqScalar } },
10102   },
10103   {
10104     /* VEX_W_0F59_P_0  */
10105     { "vmulps",         { XM, Vex, EXx } },
10106   },
10107   {
10108     /* VEX_W_0F59_P_1  */
10109     { "vmulss",         { XMScalar, VexScalar, EXdScalar } },
10110   },
10111   {
10112     /* VEX_W_0F59_P_2  */
10113     { "vmulpd",         { XM, Vex, EXx } },
10114   },
10115   {
10116     /* VEX_W_0F59_P_3  */
10117     { "vmulsd",         { XMScalar, VexScalar, EXqScalar } },
10118   },
10119   {
10120     /* VEX_W_0F5A_P_0  */
10121     { "vcvtps2pd",      { XM, EXxmmq } },
10122   },
10123   {
10124     /* VEX_W_0F5A_P_1  */
10125     { "vcvtss2sd",      { XMScalar, VexScalar, EXdScalar } },
10126   },
10127   {
10128     /* VEX_W_0F5A_P_3  */
10129     { "vcvtsd2ss",      { XMScalar, VexScalar, EXqScalar } },
10130   },
10131   {
10132     /* VEX_W_0F5B_P_0  */
10133     { "vcvtdq2ps",      { XM, EXx } },
10134   },
10135   {
10136     /* VEX_W_0F5B_P_1  */
10137     { "vcvttps2dq",     { XM, EXx } },
10138   },
10139   {
10140     /* VEX_W_0F5B_P_2  */
10141     { "vcvtps2dq",      { XM, EXx } },
10142   },
10143   {
10144     /* VEX_W_0F5C_P_0  */
10145     { "vsubps",         { XM, Vex, EXx } },
10146   },
10147   {
10148     /* VEX_W_0F5C_P_1  */
10149     { "vsubss",         { XMScalar, VexScalar, EXdScalar } },
10150   },
10151   {
10152     /* VEX_W_0F5C_P_2  */
10153     { "vsubpd",         { XM, Vex, EXx } },
10154   },
10155   {
10156     /* VEX_W_0F5C_P_3  */
10157     { "vsubsd",         { XMScalar, VexScalar, EXqScalar } },
10158   },
10159   {
10160     /* VEX_W_0F5D_P_0  */
10161     { "vminps",         { XM, Vex, EXx } },
10162   },
10163   {
10164     /* VEX_W_0F5D_P_1  */
10165     { "vminss",         { XMScalar, VexScalar, EXdScalar } },
10166   },
10167   {
10168     /* VEX_W_0F5D_P_2  */
10169     { "vminpd",         { XM, Vex, EXx } },
10170   },
10171   {
10172     /* VEX_W_0F5D_P_3  */
10173     { "vminsd",         { XMScalar, VexScalar, EXqScalar } },
10174   },
10175   {
10176     /* VEX_W_0F5E_P_0  */
10177     { "vdivps",         { XM, Vex, EXx } },
10178   },
10179   {
10180     /* VEX_W_0F5E_P_1  */
10181     { "vdivss",         { XMScalar, VexScalar, EXdScalar } },
10182   },
10183   {
10184     /* VEX_W_0F5E_P_2  */
10185     { "vdivpd",         { XM, Vex, EXx } },
10186   },
10187   {
10188     /* VEX_W_0F5E_P_3  */
10189     { "vdivsd",         { XMScalar, VexScalar, EXqScalar } },
10190   },
10191   {
10192     /* VEX_W_0F5F_P_0  */
10193     { "vmaxps",         { XM, Vex, EXx } },
10194   },
10195   {
10196     /* VEX_W_0F5F_P_1  */
10197     { "vmaxss",         { XMScalar, VexScalar, EXdScalar } },
10198   },
10199   {
10200     /* VEX_W_0F5F_P_2  */
10201     { "vmaxpd",         { XM, Vex, EXx } },
10202   },
10203   {
10204     /* VEX_W_0F5F_P_3  */
10205     { "vmaxsd",         { XMScalar, VexScalar, EXqScalar } },
10206   },
10207   {
10208     /* VEX_W_0F60_P_2  */
10209     { "vpunpcklbw",     { XM, Vex, EXx } },
10210   },
10211   {
10212     /* VEX_W_0F61_P_2  */
10213     { "vpunpcklwd",     { XM, Vex, EXx } },
10214   },
10215   {
10216     /* VEX_W_0F62_P_2  */
10217     { "vpunpckldq",     { XM, Vex, EXx } },
10218   },
10219   {
10220     /* VEX_W_0F63_P_2  */
10221     { "vpacksswb",      { XM, Vex, EXx } },
10222   },
10223   {
10224     /* VEX_W_0F64_P_2  */
10225     { "vpcmpgtb",       { XM, Vex, EXx } },
10226   },
10227   {
10228     /* VEX_W_0F65_P_2  */
10229     { "vpcmpgtw",       { XM, Vex, EXx } },
10230   },
10231   {
10232     /* VEX_W_0F66_P_2  */
10233     { "vpcmpgtd",       { XM, Vex, EXx } },
10234   },
10235   {
10236     /* VEX_W_0F67_P_2  */
10237     { "vpackuswb",      { XM, Vex, EXx } },
10238   },
10239   {
10240     /* VEX_W_0F68_P_2  */
10241     { "vpunpckhbw",     { XM, Vex, EXx } },
10242   },
10243   {
10244     /* VEX_W_0F69_P_2  */
10245     { "vpunpckhwd",     { XM, Vex, EXx } },
10246   },
10247   {
10248     /* VEX_W_0F6A_P_2  */
10249     { "vpunpckhdq",     { XM, Vex, EXx } },
10250   },
10251   {
10252     /* VEX_W_0F6B_P_2  */
10253     { "vpackssdw",      { XM, Vex, EXx } },
10254   },
10255   {
10256     /* VEX_W_0F6C_P_2  */
10257     { "vpunpcklqdq",    { XM, Vex, EXx } },
10258   },
10259   {
10260     /* VEX_W_0F6D_P_2  */
10261     { "vpunpckhqdq",    { XM, Vex, EXx } },
10262   },
10263   {
10264     /* VEX_W_0F6F_P_1  */
10265     { "vmovdqu",        { XM, EXx } },
10266   },
10267   {
10268     /* VEX_W_0F6F_P_2  */
10269     { "vmovdqa",        { XM, EXx } },
10270   },
10271   {
10272     /* VEX_W_0F70_P_1 */
10273     { "vpshufhw",       { XM, EXx, Ib } },
10274   },
10275   {
10276     /* VEX_W_0F70_P_2 */
10277     { "vpshufd",        { XM, EXx, Ib } },
10278   },
10279   {
10280     /* VEX_W_0F70_P_3 */
10281     { "vpshuflw",       { XM, EXx, Ib } },
10282   },
10283   {
10284     /* VEX_W_0F71_R_2_P_2  */
10285     { "vpsrlw",         { Vex, XS, Ib } },
10286   },
10287   {
10288     /* VEX_W_0F71_R_4_P_2  */
10289     { "vpsraw",         { Vex, XS, Ib } },
10290   },
10291   {
10292     /* VEX_W_0F71_R_6_P_2  */
10293     { "vpsllw",         { Vex, XS, Ib } },
10294   },
10295   {
10296     /* VEX_W_0F72_R_2_P_2  */
10297     { "vpsrld",         { Vex, XS, Ib } },
10298   },
10299   {
10300     /* VEX_W_0F72_R_4_P_2  */
10301     { "vpsrad",         { Vex, XS, Ib } },
10302   },
10303   {
10304     /* VEX_W_0F72_R_6_P_2  */
10305     { "vpslld",         { Vex, XS, Ib } },
10306   },
10307   {
10308     /* VEX_W_0F73_R_2_P_2  */
10309     { "vpsrlq",         { Vex, XS, Ib } },
10310   },
10311   {
10312     /* VEX_W_0F73_R_3_P_2  */
10313     { "vpsrldq",        { Vex, XS, Ib } },
10314   },
10315   {
10316     /* VEX_W_0F73_R_6_P_2  */
10317     { "vpsllq",         { Vex, XS, Ib } },
10318   },
10319   {
10320     /* VEX_W_0F73_R_7_P_2  */
10321     { "vpslldq",        { Vex, XS, Ib } },
10322   },
10323   {
10324     /* VEX_W_0F74_P_2 */
10325     { "vpcmpeqb",       { XM, Vex, EXx } },
10326   },
10327   {
10328     /* VEX_W_0F75_P_2 */
10329     { "vpcmpeqw",       { XM, Vex, EXx } },
10330   },
10331   {
10332     /* VEX_W_0F76_P_2 */
10333     { "vpcmpeqd",       { XM, Vex, EXx } },
10334   },
10335   {
10336     /* VEX_W_0F77_P_0 */
10337     { "",               { VZERO } },
10338   },
10339   {
10340     /* VEX_W_0F7C_P_2 */
10341     { "vhaddpd",        { XM, Vex, EXx } },
10342   },
10343   {
10344     /* VEX_W_0F7C_P_3 */
10345     { "vhaddps",        { XM, Vex, EXx } },
10346   },
10347   {
10348     /* VEX_W_0F7D_P_2 */
10349     { "vhsubpd",        { XM, Vex, EXx } },
10350   },
10351   {
10352     /* VEX_W_0F7D_P_3 */
10353     { "vhsubps",        { XM, Vex, EXx } },
10354   },
10355   {
10356     /* VEX_W_0F7E_P_1 */
10357     { "vmovq",          { XMScalar, EXqScalar } },
10358   },
10359   {
10360     /* VEX_W_0F7F_P_1 */
10361     { "vmovdqu",        { EXxS, XM } },
10362   },
10363   {
10364     /* VEX_W_0F7F_P_2 */
10365     { "vmovdqa",        { EXxS, XM } },
10366   },
10367   {
10368     /* VEX_W_0F90_P_0_LEN_0 */
10369     { "kmovw",          { MaskG, MaskE } },
10370   },
10371   {
10372     /* VEX_W_0F91_P_0_LEN_0 */
10373     { "kmovw",          { Ew, MaskG } },
10374   },
10375   {
10376     /* VEX_W_0F92_P_0_LEN_0 */
10377     { "kmovw",          { MaskG, Rdq } },
10378   },
10379   {
10380     /* VEX_W_0F93_P_0_LEN_0 */
10381     { "kmovw",          { Gdq, MaskR } },
10382   },
10383   {
10384     /* VEX_W_0F98_P_0_LEN_0 */
10385     { "kortestw",       { MaskG, MaskR } },
10386   },
10387   {
10388     /* VEX_W_0FAE_R_2_M_0 */
10389     { "vldmxcsr",       { Md } },
10390   },
10391   {
10392     /* VEX_W_0FAE_R_3_M_0 */
10393     { "vstmxcsr",       { Md } },
10394   },
10395   {
10396     /* VEX_W_0FC2_P_0 */
10397     { "vcmpps",         { XM, Vex, EXx, VCMP } },
10398   },
10399   {
10400     /* VEX_W_0FC2_P_1 */
10401     { "vcmpss",         { XMScalar, VexScalar, EXdScalar, VCMP } },
10402   },
10403   {
10404     /* VEX_W_0FC2_P_2 */
10405     { "vcmppd",         { XM, Vex, EXx, VCMP } },
10406   },
10407   {
10408     /* VEX_W_0FC2_P_3 */
10409     { "vcmpsd",         { XMScalar, VexScalar, EXqScalar, VCMP } },
10410   },
10411   {
10412     /* VEX_W_0FC4_P_2 */
10413     { "vpinsrw",        { XM, Vex128, Edqw, Ib } },
10414   },
10415   {
10416     /* VEX_W_0FC5_P_2 */
10417     { "vpextrw",        { Gdq, XS, Ib } },
10418   },
10419   {
10420     /* VEX_W_0FD0_P_2 */
10421     { "vaddsubpd",      { XM, Vex, EXx } },
10422   },
10423   {
10424     /* VEX_W_0FD0_P_3 */
10425     { "vaddsubps",      { XM, Vex, EXx } },
10426   },
10427   {
10428     /* VEX_W_0FD1_P_2 */
10429     { "vpsrlw",         { XM, Vex, EXxmm } },
10430   },
10431   {
10432     /* VEX_W_0FD2_P_2 */
10433     { "vpsrld",         { XM, Vex, EXxmm } },
10434   },
10435   {
10436     /* VEX_W_0FD3_P_2 */
10437     { "vpsrlq",         { XM, Vex, EXxmm } },
10438   },
10439   {
10440     /* VEX_W_0FD4_P_2 */
10441     { "vpaddq",         { XM, Vex, EXx } },
10442   },
10443   {
10444     /* VEX_W_0FD5_P_2 */
10445     { "vpmullw",        { XM, Vex, EXx } },
10446   },
10447   {
10448     /* VEX_W_0FD6_P_2 */
10449     { "vmovq",          { EXqScalarS, XMScalar } },
10450   },
10451   {
10452     /* VEX_W_0FD7_P_2_M_1 */
10453     { "vpmovmskb",      { Gdq, XS } },
10454   },
10455   {
10456     /* VEX_W_0FD8_P_2 */
10457     { "vpsubusb",       { XM, Vex, EXx } },
10458   },
10459   {
10460     /* VEX_W_0FD9_P_2 */
10461     { "vpsubusw",       { XM, Vex, EXx } },
10462   },
10463   {
10464     /* VEX_W_0FDA_P_2 */
10465     { "vpminub",        { XM, Vex, EXx } },
10466   },
10467   {
10468     /* VEX_W_0FDB_P_2 */
10469     { "vpand",          { XM, Vex, EXx } },
10470   },
10471   {
10472     /* VEX_W_0FDC_P_2 */
10473     { "vpaddusb",       { XM, Vex, EXx } },
10474   },
10475   {
10476     /* VEX_W_0FDD_P_2 */
10477     { "vpaddusw",       { XM, Vex, EXx } },
10478   },
10479   {
10480     /* VEX_W_0FDE_P_2 */
10481     { "vpmaxub",        { XM, Vex, EXx } },
10482   },
10483   {
10484     /* VEX_W_0FDF_P_2 */
10485     { "vpandn",         { XM, Vex, EXx } },
10486   },
10487   {
10488     /* VEX_W_0FE0_P_2  */
10489     { "vpavgb",         { XM, Vex, EXx } },
10490   },
10491   {
10492     /* VEX_W_0FE1_P_2  */
10493     { "vpsraw",         { XM, Vex, EXxmm } },
10494   },
10495   {
10496     /* VEX_W_0FE2_P_2  */
10497     { "vpsrad",         { XM, Vex, EXxmm } },
10498   },
10499   {
10500     /* VEX_W_0FE3_P_2  */
10501     { "vpavgw",         { XM, Vex, EXx } },
10502   },
10503   {
10504     /* VEX_W_0FE4_P_2  */
10505     { "vpmulhuw",       { XM, Vex, EXx } },
10506   },
10507   {
10508     /* VEX_W_0FE5_P_2  */
10509     { "vpmulhw",        { XM, Vex, EXx } },
10510   },
10511   {
10512     /* VEX_W_0FE6_P_1  */
10513     { "vcvtdq2pd",      { XM, EXxmmq } },
10514   },
10515   {
10516     /* VEX_W_0FE6_P_2  */
10517     { "vcvttpd2dq%XY",  { XMM, EXx } },
10518   },
10519   {
10520     /* VEX_W_0FE6_P_3  */
10521     { "vcvtpd2dq%XY",   { XMM, EXx } },
10522   },
10523   {
10524     /* VEX_W_0FE7_P_2_M_0 */
10525     { "vmovntdq",       { Mx, XM } },
10526   },
10527   {
10528     /* VEX_W_0FE8_P_2  */
10529     { "vpsubsb",        { XM, Vex, EXx } },
10530   },
10531   {
10532     /* VEX_W_0FE9_P_2  */
10533     { "vpsubsw",        { XM, Vex, EXx } },
10534   },
10535   {
10536     /* VEX_W_0FEA_P_2  */
10537     { "vpminsw",        { XM, Vex, EXx } },
10538   },
10539   {
10540     /* VEX_W_0FEB_P_2  */
10541     { "vpor",           { XM, Vex, EXx } },
10542   },
10543   {
10544     /* VEX_W_0FEC_P_2  */
10545     { "vpaddsb",        { XM, Vex, EXx } },
10546   },
10547   {
10548     /* VEX_W_0FED_P_2  */
10549     { "vpaddsw",        { XM, Vex, EXx } },
10550   },
10551   {
10552     /* VEX_W_0FEE_P_2  */
10553     { "vpmaxsw",        { XM, Vex, EXx } },
10554   },
10555   {
10556     /* VEX_W_0FEF_P_2  */
10557     { "vpxor",          { XM, Vex, EXx } },
10558   },
10559   {
10560     /* VEX_W_0FF0_P_3_M_0 */
10561     { "vlddqu",         { XM, M } },
10562   },
10563   {
10564     /* VEX_W_0FF1_P_2 */
10565     { "vpsllw",         { XM, Vex, EXxmm } },
10566   },
10567   {
10568     /* VEX_W_0FF2_P_2 */
10569     { "vpslld",         { XM, Vex, EXxmm } },
10570   },
10571   {
10572     /* VEX_W_0FF3_P_2 */
10573     { "vpsllq",         { XM, Vex, EXxmm } },
10574   },
10575   {
10576     /* VEX_W_0FF4_P_2 */
10577     { "vpmuludq",       { XM, Vex, EXx } },
10578   },
10579   {
10580     /* VEX_W_0FF5_P_2 */
10581     { "vpmaddwd",       { XM, Vex, EXx } },
10582   },
10583   {
10584     /* VEX_W_0FF6_P_2 */
10585     { "vpsadbw",        { XM, Vex, EXx } },
10586   },
10587   {
10588     /* VEX_W_0FF7_P_2 */
10589     { "vmaskmovdqu",    { XM, XS } },
10590   },
10591   {
10592     /* VEX_W_0FF8_P_2 */
10593     { "vpsubb",         { XM, Vex, EXx } },
10594   },
10595   {
10596     /* VEX_W_0FF9_P_2 */
10597     { "vpsubw",         { XM, Vex, EXx } },
10598   },
10599   {
10600     /* VEX_W_0FFA_P_2 */
10601     { "vpsubd",         { XM, Vex, EXx } },
10602   },
10603   {
10604     /* VEX_W_0FFB_P_2 */
10605     { "vpsubq",         { XM, Vex, EXx } },
10606   },
10607   {
10608     /* VEX_W_0FFC_P_2 */
10609     { "vpaddb",         { XM, Vex, EXx } },
10610   },
10611   {
10612     /* VEX_W_0FFD_P_2 */
10613     { "vpaddw",         { XM, Vex, EXx } },
10614   },
10615   {
10616     /* VEX_W_0FFE_P_2 */
10617     { "vpaddd",         { XM, Vex, EXx } },
10618   },
10619   {
10620     /* VEX_W_0F3800_P_2  */
10621     { "vpshufb",        { XM, Vex, EXx } },
10622   },
10623   {
10624     /* VEX_W_0F3801_P_2  */
10625     { "vphaddw",        { XM, Vex, EXx } },
10626   },
10627   {
10628     /* VEX_W_0F3802_P_2  */
10629     { "vphaddd",        { XM, Vex, EXx } },
10630   },
10631   {
10632     /* VEX_W_0F3803_P_2  */
10633     { "vphaddsw",       { XM, Vex, EXx } },
10634   },
10635   {
10636     /* VEX_W_0F3804_P_2  */
10637     { "vpmaddubsw",     { XM, Vex, EXx } },
10638   },
10639   {
10640     /* VEX_W_0F3805_P_2  */
10641     { "vphsubw",        { XM, Vex, EXx } },
10642   },
10643   {
10644     /* VEX_W_0F3806_P_2  */
10645     { "vphsubd",        { XM, Vex, EXx } },
10646   },
10647   {
10648     /* VEX_W_0F3807_P_2  */
10649     { "vphsubsw",       { XM, Vex, EXx } },
10650   },
10651   {
10652     /* VEX_W_0F3808_P_2  */
10653     { "vpsignb",        { XM, Vex, EXx } },
10654   },
10655   {
10656     /* VEX_W_0F3809_P_2  */
10657     { "vpsignw",        { XM, Vex, EXx } },
10658   },
10659   {
10660     /* VEX_W_0F380A_P_2  */
10661     { "vpsignd",        { XM, Vex, EXx } },
10662   },
10663   {
10664     /* VEX_W_0F380B_P_2  */
10665     { "vpmulhrsw",      { XM, Vex, EXx } },
10666   },
10667   {
10668     /* VEX_W_0F380C_P_2  */
10669     { "vpermilps",      { XM, Vex, EXx } },
10670   },
10671   {
10672     /* VEX_W_0F380D_P_2  */
10673     { "vpermilpd",      { XM, Vex, EXx } },
10674   },
10675   {
10676     /* VEX_W_0F380E_P_2  */
10677     { "vtestps",        { XM, EXx } },
10678   },
10679   {
10680     /* VEX_W_0F380F_P_2  */
10681     { "vtestpd",        { XM, EXx } },
10682   },
10683   {
10684     /* VEX_W_0F3816_P_2  */
10685     { "vpermps",        { XM, Vex, EXx } },
10686   },
10687   {
10688     /* VEX_W_0F3817_P_2 */
10689     { "vptest",         { XM, EXx } },
10690   },
10691   {
10692     /* VEX_W_0F3818_P_2 */
10693     { "vbroadcastss",   { XM, EXxmm_md } },
10694   },
10695   {
10696     /* VEX_W_0F3819_P_2 */
10697     { "vbroadcastsd",   { XM, EXxmm_mq } },
10698   },
10699   {
10700     /* VEX_W_0F381A_P_2_M_0 */
10701     { "vbroadcastf128", { XM, Mxmm } },
10702   },
10703   {
10704     /* VEX_W_0F381C_P_2 */
10705     { "vpabsb",         { XM, EXx } },
10706   },
10707   {
10708     /* VEX_W_0F381D_P_2 */
10709     { "vpabsw",         { XM, EXx } },
10710   },
10711   {
10712     /* VEX_W_0F381E_P_2 */
10713     { "vpabsd",         { XM, EXx } },
10714   },
10715   {
10716     /* VEX_W_0F3820_P_2 */
10717     { "vpmovsxbw",      { XM, EXxmmq } },
10718   },
10719   {
10720     /* VEX_W_0F3821_P_2 */
10721     { "vpmovsxbd",      { XM, EXxmmqd } },
10722   },
10723   {
10724     /* VEX_W_0F3822_P_2 */
10725     { "vpmovsxbq",      { XM, EXxmmdw } },
10726   },
10727   {
10728     /* VEX_W_0F3823_P_2 */
10729     { "vpmovsxwd",      { XM, EXxmmq } },
10730   },
10731   {
10732     /* VEX_W_0F3824_P_2 */
10733     { "vpmovsxwq",      { XM, EXxmmqd } },
10734   },
10735   {
10736     /* VEX_W_0F3825_P_2 */
10737     { "vpmovsxdq",      { XM, EXxmmq } },
10738   },
10739   {
10740     /* VEX_W_0F3828_P_2 */
10741     { "vpmuldq",        { XM, Vex, EXx } },
10742   },
10743   {
10744     /* VEX_W_0F3829_P_2 */
10745     { "vpcmpeqq",       { XM, Vex, EXx } },
10746   },
10747   {
10748     /* VEX_W_0F382A_P_2_M_0 */
10749     { "vmovntdqa",      { XM, Mx } },
10750   },
10751   {
10752     /* VEX_W_0F382B_P_2 */
10753     { "vpackusdw",      { XM, Vex, EXx } },
10754   },
10755   {
10756     /* VEX_W_0F382C_P_2_M_0 */
10757     { "vmaskmovps",     { XM, Vex, Mx } },
10758   },
10759   {
10760     /* VEX_W_0F382D_P_2_M_0 */
10761     { "vmaskmovpd",     { XM, Vex, Mx } },
10762   },
10763   {
10764     /* VEX_W_0F382E_P_2_M_0 */
10765     { "vmaskmovps",     { Mx, Vex, XM } },
10766   },
10767   {
10768     /* VEX_W_0F382F_P_2_M_0 */
10769     { "vmaskmovpd",     { Mx, Vex, XM } },
10770   },
10771   {
10772     /* VEX_W_0F3830_P_2 */
10773     { "vpmovzxbw",      { XM, EXxmmq } },
10774   },
10775   {
10776     /* VEX_W_0F3831_P_2 */
10777     { "vpmovzxbd",      { XM, EXxmmqd } },
10778   },
10779   {
10780     /* VEX_W_0F3832_P_2 */
10781     { "vpmovzxbq",      { XM, EXxmmdw } },
10782   },
10783   {
10784     /* VEX_W_0F3833_P_2 */
10785     { "vpmovzxwd",      { XM, EXxmmq } },
10786   },
10787   {
10788     /* VEX_W_0F3834_P_2 */
10789     { "vpmovzxwq",      { XM, EXxmmqd } },
10790   },
10791   {
10792     /* VEX_W_0F3835_P_2 */
10793     { "vpmovzxdq",      { XM, EXxmmq } },
10794   },
10795   {
10796     /* VEX_W_0F3836_P_2  */
10797     { "vpermd",         { XM, Vex, EXx } },
10798   },
10799   {
10800     /* VEX_W_0F3837_P_2 */
10801     { "vpcmpgtq",       { XM, Vex, EXx } },
10802   },
10803   {
10804     /* VEX_W_0F3838_P_2 */
10805     { "vpminsb",        { XM, Vex, EXx } },
10806   },
10807   {
10808     /* VEX_W_0F3839_P_2 */
10809     { "vpminsd",        { XM, Vex, EXx } },
10810   },
10811   {
10812     /* VEX_W_0F383A_P_2 */
10813     { "vpminuw",        { XM, Vex, EXx } },
10814   },
10815   {
10816     /* VEX_W_0F383B_P_2 */
10817     { "vpminud",        { XM, Vex, EXx } },
10818   },
10819   {
10820     /* VEX_W_0F383C_P_2 */
10821     { "vpmaxsb",        { XM, Vex, EXx } },
10822   },
10823   {
10824     /* VEX_W_0F383D_P_2 */
10825     { "vpmaxsd",        { XM, Vex, EXx } },
10826   },
10827   {
10828     /* VEX_W_0F383E_P_2 */
10829     { "vpmaxuw",        { XM, Vex, EXx } },
10830   },
10831   {
10832     /* VEX_W_0F383F_P_2 */
10833     { "vpmaxud",        { XM, Vex, EXx } },
10834   },
10835   {
10836     /* VEX_W_0F3840_P_2 */
10837     { "vpmulld",        { XM, Vex, EXx } },
10838   },
10839   {
10840     /* VEX_W_0F3841_P_2 */
10841     { "vphminposuw",    { XM, EXx } },
10842   },
10843   {
10844     /* VEX_W_0F3846_P_2 */
10845     { "vpsravd",        { XM, Vex, EXx } },
10846   },
10847   {
10848     /* VEX_W_0F3858_P_2 */
10849     { "vpbroadcastd", { XM, EXxmm_md } },
10850   },
10851   {
10852     /* VEX_W_0F3859_P_2 */
10853     { "vpbroadcastq",   { XM, EXxmm_mq } },
10854   },
10855   {
10856     /* VEX_W_0F385A_P_2_M_0 */
10857     { "vbroadcasti128", { XM, Mxmm } },
10858   },
10859   {
10860     /* VEX_W_0F3878_P_2 */
10861     { "vpbroadcastb",   { XM, EXxmm_mb } },
10862   },
10863   {
10864     /* VEX_W_0F3879_P_2 */
10865     { "vpbroadcastw",   { XM, EXxmm_mw } },
10866   },
10867   {
10868     /* VEX_W_0F38DB_P_2 */
10869     { "vaesimc",        { XM, EXx } },
10870   },
10871   {
10872     /* VEX_W_0F38DC_P_2 */
10873     { "vaesenc",        { XM, Vex128, EXx } },
10874   },
10875   {
10876     /* VEX_W_0F38DD_P_2 */
10877     { "vaesenclast",    { XM, Vex128, EXx } },
10878   },
10879   {
10880     /* VEX_W_0F38DE_P_2 */
10881     { "vaesdec",        { XM, Vex128, EXx } },
10882   },
10883   {
10884     /* VEX_W_0F38DF_P_2 */
10885     { "vaesdeclast",    { XM, Vex128, EXx } },
10886   },
10887   {
10888     /* VEX_W_0F3A00_P_2 */
10889     { Bad_Opcode },
10890     { "vpermq",         { XM, EXx, Ib } },
10891   },
10892   {
10893     /* VEX_W_0F3A01_P_2 */
10894     { Bad_Opcode },
10895     { "vpermpd",        { XM, EXx, Ib } },
10896   },
10897   {
10898     /* VEX_W_0F3A02_P_2 */
10899     { "vpblendd",       { XM, Vex, EXx, Ib } },
10900   },
10901   {
10902     /* VEX_W_0F3A04_P_2 */
10903     { "vpermilps",      { XM, EXx, Ib } },
10904   },
10905   {
10906     /* VEX_W_0F3A05_P_2 */
10907     { "vpermilpd",      { XM, EXx, Ib } },
10908   },
10909   {
10910     /* VEX_W_0F3A06_P_2 */
10911     { "vperm2f128",     { XM, Vex256, EXx, Ib } },
10912   },
10913   {
10914     /* VEX_W_0F3A08_P_2 */
10915     { "vroundps",       { XM, EXx, Ib } },
10916   },
10917   {
10918     /* VEX_W_0F3A09_P_2 */
10919     { "vroundpd",       { XM, EXx, Ib } },
10920   },
10921   {
10922     /* VEX_W_0F3A0A_P_2 */
10923     { "vroundss",       { XMScalar, VexScalar, EXdScalar, Ib } },
10924   },
10925   {
10926     /* VEX_W_0F3A0B_P_2 */
10927     { "vroundsd",       { XMScalar, VexScalar, EXqScalar, Ib } },
10928   },
10929   {
10930     /* VEX_W_0F3A0C_P_2 */
10931     { "vblendps",       { XM, Vex, EXx, Ib } },
10932   },
10933   {
10934     /* VEX_W_0F3A0D_P_2 */
10935     { "vblendpd",       { XM, Vex, EXx, Ib } },
10936   },
10937   {
10938     /* VEX_W_0F3A0E_P_2 */
10939     { "vpblendw",       { XM, Vex, EXx, Ib } },
10940   },
10941   {
10942     /* VEX_W_0F3A0F_P_2 */
10943     { "vpalignr",       { XM, Vex, EXx, Ib } },
10944   },
10945   {
10946     /* VEX_W_0F3A14_P_2 */
10947     { "vpextrb",        { Edqb, XM, Ib } },
10948   },
10949   {
10950     /* VEX_W_0F3A15_P_2 */
10951     { "vpextrw",        { Edqw, XM, Ib } },
10952   },
10953   {
10954     /* VEX_W_0F3A18_P_2 */
10955     { "vinsertf128",    { XM, Vex256, EXxmm, Ib } },
10956   },
10957   {
10958     /* VEX_W_0F3A19_P_2 */
10959     { "vextractf128",   { EXxmm, XM, Ib } },
10960   },
10961   {
10962     /* VEX_W_0F3A20_P_2 */
10963     { "vpinsrb",        { XM, Vex128, Edqb, Ib } },
10964   },
10965   {
10966     /* VEX_W_0F3A21_P_2 */
10967     { "vinsertps",      { XM, Vex128, EXd, Ib } },
10968   },
10969   {
10970     /* VEX_W_0F3A30_P_2 */
10971     { Bad_Opcode },
10972     { "kshiftrw",       { MaskG, MaskR, Ib } },
10973   },
10974   {
10975     /* VEX_W_0F3A32_P_2 */
10976     { Bad_Opcode },
10977     { "kshiftlw",       { MaskG, MaskR, Ib } },
10978   },
10979   {
10980     /* VEX_W_0F3A38_P_2 */
10981     { "vinserti128",    { XM, Vex256, EXxmm, Ib } },
10982   },
10983   {
10984     /* VEX_W_0F3A39_P_2 */
10985     { "vextracti128",   { EXxmm, XM, Ib } },
10986   },
10987   {
10988     /* VEX_W_0F3A40_P_2 */
10989     { "vdpps",          { XM, Vex, EXx, Ib } },
10990   },
10991   {
10992     /* VEX_W_0F3A41_P_2 */
10993     { "vdppd",          { XM, Vex128, EXx, Ib } },
10994   },
10995   {
10996     /* VEX_W_0F3A42_P_2 */
10997     { "vmpsadbw",       { XM, Vex, EXx, Ib } },
10998   },
10999   {
11000     /* VEX_W_0F3A44_P_2 */
11001     { "vpclmulqdq",     { XM, Vex128, EXx, PCLMUL } },
11002   },
11003   {
11004     /* VEX_W_0F3A46_P_2 */
11005     { "vperm2i128",     { XM, Vex256, EXx, Ib } },
11006   },
11007   {
11008     /* VEX_W_0F3A48_P_2 */
11009     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
11010     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
11011   },
11012   {
11013     /* VEX_W_0F3A49_P_2 */
11014     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
11015     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
11016   },
11017   {
11018     /* VEX_W_0F3A4A_P_2 */
11019     { "vblendvps",      { XM, Vex, EXx, XMVexI4 } },
11020   },
11021   {
11022     /* VEX_W_0F3A4B_P_2 */
11023     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 } },
11024   },
11025   {
11026     /* VEX_W_0F3A4C_P_2 */
11027     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 } },
11028   },
11029   {
11030     /* VEX_W_0F3A60_P_2 */
11031     { "vpcmpestrm",     { XM, EXx, Ib } },
11032   },
11033   {
11034     /* VEX_W_0F3A61_P_2 */
11035     { "vpcmpestri",     { XM, EXx, Ib } },
11036   },
11037   {
11038     /* VEX_W_0F3A62_P_2 */
11039     { "vpcmpistrm",     { XM, EXx, Ib } },
11040   },
11041   {
11042     /* VEX_W_0F3A63_P_2 */
11043     { "vpcmpistri",     { XM, EXx, Ib } },
11044   },
11045   {
11046     /* VEX_W_0F3ADF_P_2 */
11047     { "vaeskeygenassist", { XM, EXx, Ib } },
11048   },
11049 #define NEED_VEX_W_TABLE
11050 #include "i386-dis-evex.h"
11051 #undef NEED_VEX_W_TABLE
11052 };
11053
11054 static const struct dis386 mod_table[][2] = {
11055   {
11056     /* MOD_8D */
11057     { "leaS",           { Gv, M } },
11058   },
11059   {
11060     /* MOD_C6_REG_7 */
11061     { Bad_Opcode },
11062     { RM_TABLE (RM_C6_REG_7) },
11063   },
11064   {
11065     /* MOD_C7_REG_7 */
11066     { Bad_Opcode },
11067     { RM_TABLE (RM_C7_REG_7) },
11068   },
11069   {
11070     /* MOD_FF_REG_3 */
11071     { "Jcall{T|}", { indirEp } },
11072   },
11073   {
11074     /* MOD_FF_REG_5 */
11075     { "Jjmp{T|}", { indirEp } },
11076   },
11077   {
11078     /* MOD_0F01_REG_0 */
11079     { X86_64_TABLE (X86_64_0F01_REG_0) },
11080     { RM_TABLE (RM_0F01_REG_0) },
11081   },
11082   {
11083     /* MOD_0F01_REG_1 */
11084     { X86_64_TABLE (X86_64_0F01_REG_1) },
11085     { RM_TABLE (RM_0F01_REG_1) },
11086   },
11087   {
11088     /* MOD_0F01_REG_2 */
11089     { X86_64_TABLE (X86_64_0F01_REG_2) },
11090     { RM_TABLE (RM_0F01_REG_2) },
11091   },
11092   {
11093     /* MOD_0F01_REG_3 */
11094     { X86_64_TABLE (X86_64_0F01_REG_3) },
11095     { RM_TABLE (RM_0F01_REG_3) },
11096   },
11097   {
11098     /* MOD_0F01_REG_7 */
11099     { "invlpg",         { Mb } },
11100     { RM_TABLE (RM_0F01_REG_7) },
11101   },
11102   {
11103     /* MOD_0F12_PREFIX_0 */
11104     { "movlps",         { XM, EXq } },
11105     { "movhlps",        { XM, EXq } },
11106   },
11107   {
11108     /* MOD_0F13 */
11109     { "movlpX",         { EXq, XM } },
11110   },
11111   {
11112     /* MOD_0F16_PREFIX_0 */
11113     { "movhps",         { XM, EXq } },
11114     { "movlhps",        { XM, EXq } },
11115   },
11116   {
11117     /* MOD_0F17 */
11118     { "movhpX",         { EXq, XM } },
11119   },
11120   {
11121     /* MOD_0F18_REG_0 */
11122     { "prefetchnta",    { Mb } },
11123   },
11124   {
11125     /* MOD_0F18_REG_1 */
11126     { "prefetcht0",     { Mb } },
11127   },
11128   {
11129     /* MOD_0F18_REG_2 */
11130     { "prefetcht1",     { Mb } },
11131   },
11132   {
11133     /* MOD_0F18_REG_3 */
11134     { "prefetcht2",     { Mb } },
11135   },
11136   {
11137     /* MOD_0F18_REG_4 */
11138     { "nop/reserved",   { Mb } },
11139   },
11140   {
11141     /* MOD_0F18_REG_5 */
11142     { "nop/reserved",   { Mb } },
11143   },
11144   {
11145     /* MOD_0F18_REG_6 */
11146     { "nop/reserved",   { Mb } },
11147   },
11148   {
11149     /* MOD_0F18_REG_7 */
11150     { "nop/reserved",   { Mb } },
11151   },
11152   {
11153     /* MOD_0F1A_PREFIX_0 */
11154     { "bndldx",         { Gbnd, Ev_bnd } },
11155     { "nopQ",           { Ev } },
11156   },
11157   {
11158     /* MOD_0F1B_PREFIX_0 */
11159     { "bndstx",         { Ev_bnd, Gbnd } },
11160     { "nopQ",           { Ev } },
11161   },
11162   {
11163     /* MOD_0F1B_PREFIX_1 */
11164     { "bndmk",          { Gbnd, Ev_bnd } },
11165     { "nopQ",           { Ev } },
11166   },
11167   {
11168     /* MOD_0F20 */
11169     { Bad_Opcode },
11170     { "movZ",           { Rm, Cm } },
11171   },
11172   {
11173     /* MOD_0F21 */
11174     { Bad_Opcode },
11175     { "movZ",           { Rm, Dm } },
11176   },
11177   {
11178     /* MOD_0F22 */
11179     { Bad_Opcode },
11180     { "movZ",           { Cm, Rm } },
11181   },
11182   {
11183     /* MOD_0F23 */
11184     { Bad_Opcode },
11185     { "movZ",           { Dm, Rm } },
11186   },
11187   {
11188     /* MOD_0F24 */
11189     { Bad_Opcode },
11190     { "movL",           { Rd, Td } },
11191   },
11192   {
11193     /* MOD_0F26 */
11194     { Bad_Opcode },
11195     { "movL",           { Td, Rd } },
11196   },
11197   {
11198     /* MOD_0F2B_PREFIX_0 */
11199     {"movntps",         { Mx, XM } },
11200   },
11201   {
11202     /* MOD_0F2B_PREFIX_1 */
11203     {"movntss",         { Md, XM } },
11204   },
11205   {
11206     /* MOD_0F2B_PREFIX_2 */
11207     {"movntpd",         { Mx, XM } },
11208   },
11209   {
11210     /* MOD_0F2B_PREFIX_3 */
11211     {"movntsd",         { Mq, XM } },
11212   },
11213   {
11214     /* MOD_0F51 */
11215     { Bad_Opcode },
11216     { "movmskpX",       { Gdq, XS } },
11217   },
11218   {
11219     /* MOD_0F71_REG_2 */
11220     { Bad_Opcode },
11221     { "psrlw",          { MS, Ib } },
11222   },
11223   {
11224     /* MOD_0F71_REG_4 */
11225     { Bad_Opcode },
11226     { "psraw",          { MS, Ib } },
11227   },
11228   {
11229     /* MOD_0F71_REG_6 */
11230     { Bad_Opcode },
11231     { "psllw",          { MS, Ib } },
11232   },
11233   {
11234     /* MOD_0F72_REG_2 */
11235     { Bad_Opcode },
11236     { "psrld",          { MS, Ib } },
11237   },
11238   {
11239     /* MOD_0F72_REG_4 */
11240     { Bad_Opcode },
11241     { "psrad",          { MS, Ib } },
11242   },
11243   {
11244     /* MOD_0F72_REG_6 */
11245     { Bad_Opcode },
11246     { "pslld",          { MS, Ib } },
11247   },
11248   {
11249     /* MOD_0F73_REG_2 */
11250     { Bad_Opcode },
11251     { "psrlq",          { MS, Ib } },
11252   },
11253   {
11254     /* MOD_0F73_REG_3 */
11255     { Bad_Opcode },
11256     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
11257   },
11258   {
11259     /* MOD_0F73_REG_6 */
11260     { Bad_Opcode },
11261     { "psllq",          { MS, Ib } },
11262   },
11263   {
11264     /* MOD_0F73_REG_7 */
11265     { Bad_Opcode },
11266     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
11267   },
11268   {
11269     /* MOD_0FAE_REG_0 */
11270     { "fxsave",         { FXSAVE } },
11271     { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
11272   },
11273   {
11274     /* MOD_0FAE_REG_1 */
11275     { "fxrstor",        { FXSAVE } },
11276     { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
11277   },
11278   {
11279     /* MOD_0FAE_REG_2 */
11280     { "ldmxcsr",        { Md } },
11281     { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
11282   },
11283   {
11284     /* MOD_0FAE_REG_3 */
11285     { "stmxcsr",        { Md } },
11286     { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
11287   },
11288   {
11289     /* MOD_0FAE_REG_4 */
11290     { "xsave",          { FXSAVE } },
11291   },
11292   {
11293     /* MOD_0FAE_REG_5 */
11294     { "xrstor",         { FXSAVE } },
11295     { RM_TABLE (RM_0FAE_REG_5) },
11296   },
11297   {
11298     /* MOD_0FAE_REG_6 */
11299     { "xsaveopt",       { FXSAVE } },
11300     { RM_TABLE (RM_0FAE_REG_6) },
11301   },
11302   {
11303     /* MOD_0FAE_REG_7 */
11304     { PREFIX_TABLE (PREFIX_0FAE_REG_7) },
11305     { RM_TABLE (RM_0FAE_REG_7) },
11306   },
11307   {
11308     /* MOD_0FB2 */
11309     { "lssS",           { Gv, Mp } },
11310   },
11311   {
11312     /* MOD_0FB4 */
11313     { "lfsS",           { Gv, Mp } },
11314   },
11315   {
11316     /* MOD_0FB5 */
11317     { "lgsS",           { Gv, Mp } },
11318   },
11319   {
11320     /* MOD_0FC7_REG_3 */
11321     { "xrstors",                { FXSAVE } },
11322   },
11323   {
11324     /* MOD_0FC7_REG_4 */
11325     { "xsavec",         { FXSAVE } },
11326   },
11327   {
11328     /* MOD_0FC7_REG_5 */
11329     { "xsaves",         { FXSAVE } },
11330   },
11331   {
11332     /* MOD_0FC7_REG_6 */
11333     { PREFIX_TABLE (PREFIX_0FC7_REG_6) },
11334     { "rdrand",         { Ev } },
11335   },
11336   {
11337     /* MOD_0FC7_REG_7 */
11338     { "vmptrst",        { Mq } },
11339     { "rdseed",         { Ev } },
11340   },
11341   {
11342     /* MOD_0FD7 */
11343     { Bad_Opcode },
11344     { "pmovmskb",       { Gdq, MS } },
11345   },
11346   {
11347     /* MOD_0FE7_PREFIX_2 */
11348     { "movntdq",        { Mx, XM } },
11349   },
11350   {
11351     /* MOD_0FF0_PREFIX_3 */
11352     { "lddqu",          { XM, M } },
11353   },
11354   {
11355     /* MOD_0F382A_PREFIX_2 */
11356     { "movntdqa",       { XM, Mx } },
11357   },
11358   {
11359     /* MOD_62_32BIT */
11360     { "bound{S|}",      { Gv, Ma } },
11361     { EVEX_TABLE (EVEX_0F) },
11362   },
11363   {
11364     /* MOD_C4_32BIT */
11365     { "lesS",           { Gv, Mp } },
11366     { VEX_C4_TABLE (VEX_0F) },
11367   },
11368   {
11369     /* MOD_C5_32BIT */
11370     { "ldsS",           { Gv, Mp } },
11371     { VEX_C5_TABLE (VEX_0F) },
11372   },
11373   {
11374     /* MOD_VEX_0F12_PREFIX_0 */
11375     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
11376     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
11377   },
11378   {
11379     /* MOD_VEX_0F13 */
11380     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
11381   },
11382   {
11383     /* MOD_VEX_0F16_PREFIX_0 */
11384     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
11385     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
11386   },
11387   {
11388     /* MOD_VEX_0F17 */
11389     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
11390   },
11391   {
11392     /* MOD_VEX_0F2B */
11393     { VEX_W_TABLE (VEX_W_0F2B_M_0) },
11394   },
11395   {
11396     /* MOD_VEX_0F50 */
11397     { Bad_Opcode },
11398     { VEX_W_TABLE (VEX_W_0F50_M_0) },
11399   },
11400   {
11401     /* MOD_VEX_0F71_REG_2 */
11402     { Bad_Opcode },
11403     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
11404   },
11405   {
11406     /* MOD_VEX_0F71_REG_4 */
11407     { Bad_Opcode },
11408     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
11409   },
11410   {
11411     /* MOD_VEX_0F71_REG_6 */
11412     { Bad_Opcode },
11413     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
11414   },
11415   {
11416     /* MOD_VEX_0F72_REG_2 */
11417     { Bad_Opcode },
11418     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
11419   },
11420   {
11421     /* MOD_VEX_0F72_REG_4 */
11422     { Bad_Opcode },
11423     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
11424   },
11425   {
11426     /* MOD_VEX_0F72_REG_6 */
11427     { Bad_Opcode },
11428     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
11429   },
11430   {
11431     /* MOD_VEX_0F73_REG_2 */
11432     { Bad_Opcode },
11433     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
11434   },
11435   {
11436     /* MOD_VEX_0F73_REG_3 */
11437     { Bad_Opcode },
11438     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
11439   },
11440   {
11441     /* MOD_VEX_0F73_REG_6 */
11442     { Bad_Opcode },
11443     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
11444   },
11445   {
11446     /* MOD_VEX_0F73_REG_7 */
11447     { Bad_Opcode },
11448     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
11449   },
11450   {
11451     /* MOD_VEX_0FAE_REG_2 */
11452     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
11453   },
11454   {
11455     /* MOD_VEX_0FAE_REG_3 */
11456     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
11457   },
11458   {
11459     /* MOD_VEX_0FD7_PREFIX_2 */
11460     { Bad_Opcode },
11461     { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) },
11462   },
11463   {
11464     /* MOD_VEX_0FE7_PREFIX_2 */
11465     { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) },
11466   },
11467   {
11468     /* MOD_VEX_0FF0_PREFIX_3 */
11469     { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) },
11470   },
11471   {
11472     /* MOD_VEX_0F381A_PREFIX_2 */
11473     { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
11474   },
11475   {
11476     /* MOD_VEX_0F382A_PREFIX_2 */
11477     { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) },
11478   },
11479   {
11480     /* MOD_VEX_0F382C_PREFIX_2 */
11481     { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
11482   },
11483   {
11484     /* MOD_VEX_0F382D_PREFIX_2 */
11485     { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
11486   },
11487   {
11488     /* MOD_VEX_0F382E_PREFIX_2 */
11489     { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
11490   },
11491   {
11492     /* MOD_VEX_0F382F_PREFIX_2 */
11493     { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
11494   },
11495   {
11496     /* MOD_VEX_0F385A_PREFIX_2 */
11497     { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
11498   },
11499   {
11500     /* MOD_VEX_0F388C_PREFIX_2 */
11501     { "vpmaskmov%LW",   { XM, Vex, Mx } },
11502   },
11503   {
11504     /* MOD_VEX_0F388E_PREFIX_2 */
11505     { "vpmaskmov%LW",   { Mx, Vex, XM } },
11506   },
11507 #define NEED_MOD_TABLE
11508 #include "i386-dis-evex.h"
11509 #undef NEED_MOD_TABLE
11510 };
11511
11512 static const struct dis386 rm_table[][8] = {
11513   {
11514     /* RM_C6_REG_7 */
11515     { "xabort",         { Skip_MODRM, Ib } },
11516   },
11517   {
11518     /* RM_C7_REG_7 */
11519     { "xbeginT",        { Skip_MODRM, Jv } },
11520   },
11521   {
11522     /* RM_0F01_REG_0 */
11523     { Bad_Opcode },
11524     { "vmcall",         { Skip_MODRM } },
11525     { "vmlaunch",       { Skip_MODRM } },
11526     { "vmresume",       { Skip_MODRM } },
11527     { "vmxoff",         { Skip_MODRM } },
11528   },
11529   {
11530     /* RM_0F01_REG_1 */
11531     { "monitor",        { { OP_Monitor, 0 } } },
11532     { "mwait",          { { OP_Mwait, 0 } } },
11533     { "clac",           { Skip_MODRM } },
11534     { "stac",           { Skip_MODRM } },
11535     { Bad_Opcode },
11536     { Bad_Opcode },
11537     { Bad_Opcode },
11538     { "encls",          { Skip_MODRM } },
11539   },
11540   {
11541     /* RM_0F01_REG_2 */
11542     { "xgetbv",         { Skip_MODRM } },
11543     { "xsetbv",         { Skip_MODRM } },
11544     { Bad_Opcode },
11545     { Bad_Opcode },
11546     { "vmfunc",         { Skip_MODRM } },
11547     { "xend",           { Skip_MODRM } },
11548     { "xtest",          { Skip_MODRM } },
11549     { "enclu",          { Skip_MODRM } },
11550   },
11551   {
11552     /* RM_0F01_REG_3 */
11553     { "vmrun",          { Skip_MODRM } },
11554     { "vmmcall",        { Skip_MODRM } },
11555     { "vmload",         { Skip_MODRM } },
11556     { "vmsave",         { Skip_MODRM } },
11557     { "stgi",           { Skip_MODRM } },
11558     { "clgi",           { Skip_MODRM } },
11559     { "skinit",         { Skip_MODRM } },
11560     { "invlpga",        { Skip_MODRM } },
11561   },
11562   {
11563     /* RM_0F01_REG_7 */
11564     { "swapgs",         { Skip_MODRM } },
11565     { "rdtscp",         { Skip_MODRM } },
11566   },
11567   {
11568     /* RM_0FAE_REG_5 */
11569     { "lfence",         { Skip_MODRM } },
11570   },
11571   {
11572     /* RM_0FAE_REG_6 */
11573     { "mfence",         { Skip_MODRM } },
11574   },
11575   {
11576     /* RM_0FAE_REG_7 */
11577     { "sfence",         { Skip_MODRM } },
11578   },
11579 };
11580
11581 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
11582
11583 /* We use the high bit to indicate different name for the same
11584    prefix.  */
11585 #define ADDR16_PREFIX   (0x67 | 0x100)
11586 #define ADDR32_PREFIX   (0x67 | 0x200)
11587 #define DATA16_PREFIX   (0x66 | 0x100)
11588 #define DATA32_PREFIX   (0x66 | 0x200)
11589 #define REP_PREFIX      (0xf3 | 0x100)
11590 #define XACQUIRE_PREFIX (0xf2 | 0x200)
11591 #define XRELEASE_PREFIX (0xf3 | 0x400)
11592 #define BND_PREFIX      (0xf2 | 0x400)
11593
11594 static int
11595 ckprefix (void)
11596 {
11597   int newrex, i, length;
11598   rex = 0;
11599   rex_ignored = 0;
11600   prefixes = 0;
11601   used_prefixes = 0;
11602   rex_used = 0;
11603   last_lock_prefix = -1;
11604   last_repz_prefix = -1;
11605   last_repnz_prefix = -1;
11606   last_data_prefix = -1;
11607   last_addr_prefix = -1;
11608   last_rex_prefix = -1;
11609   last_seg_prefix = -1;
11610   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
11611     all_prefixes[i] = 0;
11612   i = 0;
11613   length = 0;
11614   /* The maximum instruction length is 15bytes.  */
11615   while (length < MAX_CODE_LENGTH - 1)
11616     {
11617       FETCH_DATA (the_info, codep + 1);
11618       newrex = 0;
11619       switch (*codep)
11620         {
11621         /* REX prefixes family.  */
11622         case 0x40:
11623         case 0x41:
11624         case 0x42:
11625         case 0x43:
11626         case 0x44:
11627         case 0x45:
11628         case 0x46:
11629         case 0x47:
11630         case 0x48:
11631         case 0x49:
11632         case 0x4a:
11633         case 0x4b:
11634         case 0x4c:
11635         case 0x4d:
11636         case 0x4e:
11637         case 0x4f:
11638           if (address_mode == mode_64bit)
11639             newrex = *codep;
11640           else
11641             return 1;
11642           last_rex_prefix = i;
11643           break;
11644         case 0xf3:
11645           prefixes |= PREFIX_REPZ;
11646           last_repz_prefix = i;
11647           break;
11648         case 0xf2:
11649           prefixes |= PREFIX_REPNZ;
11650           last_repnz_prefix = i;
11651           break;
11652         case 0xf0:
11653           prefixes |= PREFIX_LOCK;
11654           last_lock_prefix = i;
11655           break;
11656         case 0x2e:
11657           prefixes |= PREFIX_CS;
11658           last_seg_prefix = i;
11659           break;
11660         case 0x36:
11661           prefixes |= PREFIX_SS;
11662           last_seg_prefix = i;
11663           break;
11664         case 0x3e:
11665           prefixes |= PREFIX_DS;
11666           last_seg_prefix = i;
11667           break;
11668         case 0x26:
11669           prefixes |= PREFIX_ES;
11670           last_seg_prefix = i;
11671           break;
11672         case 0x64:
11673           prefixes |= PREFIX_FS;
11674           last_seg_prefix = i;
11675           break;
11676         case 0x65:
11677           prefixes |= PREFIX_GS;
11678           last_seg_prefix = i;
11679           break;
11680         case 0x66:
11681           prefixes |= PREFIX_DATA;
11682           last_data_prefix = i;
11683           break;
11684         case 0x67:
11685           prefixes |= PREFIX_ADDR;
11686           last_addr_prefix = i;
11687           break;
11688         case FWAIT_OPCODE:
11689           /* fwait is really an instruction.  If there are prefixes
11690              before the fwait, they belong to the fwait, *not* to the
11691              following instruction.  */
11692           if (prefixes || rex)
11693             {
11694               prefixes |= PREFIX_FWAIT;
11695               codep++;
11696               /* This ensures that the previous REX prefixes are noticed
11697                  as unused prefixes, as in the return case below.  */
11698               rex_used = rex;
11699               return 1;
11700             }
11701           prefixes = PREFIX_FWAIT;
11702           break;
11703         default:
11704           return 1;
11705         }
11706       /* Rex is ignored when followed by another prefix.  */
11707       if (rex)
11708         {
11709           rex_used = rex;
11710           return 1;
11711         }
11712       if (*codep != FWAIT_OPCODE)
11713         all_prefixes[i++] = *codep;
11714       rex = newrex;
11715       codep++;
11716       length++;
11717     }
11718   return 0;
11719 }
11720
11721 static int
11722 seg_prefix (int pref)
11723 {
11724   switch (pref)
11725     {
11726     case 0x2e:
11727       return PREFIX_CS;
11728     case 0x36:
11729       return PREFIX_SS;
11730     case 0x3e:
11731       return PREFIX_DS;
11732     case 0x26:
11733       return PREFIX_ES;
11734     case 0x64:
11735       return PREFIX_FS;
11736     case 0x65:
11737       return PREFIX_GS;
11738     default:
11739       return 0;
11740     }
11741 }
11742
11743 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
11744    prefix byte.  */
11745
11746 static const char *
11747 prefix_name (int pref, int sizeflag)
11748 {
11749   static const char *rexes [16] =
11750     {
11751       "rex",            /* 0x40 */
11752       "rex.B",          /* 0x41 */
11753       "rex.X",          /* 0x42 */
11754       "rex.XB",         /* 0x43 */
11755       "rex.R",          /* 0x44 */
11756       "rex.RB",         /* 0x45 */
11757       "rex.RX",         /* 0x46 */
11758       "rex.RXB",        /* 0x47 */
11759       "rex.W",          /* 0x48 */
11760       "rex.WB",         /* 0x49 */
11761       "rex.WX",         /* 0x4a */
11762       "rex.WXB",        /* 0x4b */
11763       "rex.WR",         /* 0x4c */
11764       "rex.WRB",        /* 0x4d */
11765       "rex.WRX",        /* 0x4e */
11766       "rex.WRXB",       /* 0x4f */
11767     };
11768
11769   switch (pref)
11770     {
11771     /* REX prefixes family.  */
11772     case 0x40:
11773     case 0x41:
11774     case 0x42:
11775     case 0x43:
11776     case 0x44:
11777     case 0x45:
11778     case 0x46:
11779     case 0x47:
11780     case 0x48:
11781     case 0x49:
11782     case 0x4a:
11783     case 0x4b:
11784     case 0x4c:
11785     case 0x4d:
11786     case 0x4e:
11787     case 0x4f:
11788       return rexes [pref - 0x40];
11789     case 0xf3:
11790       return "repz";
11791     case 0xf2:
11792       return "repnz";
11793     case 0xf0:
11794       return "lock";
11795     case 0x2e:
11796       return "cs";
11797     case 0x36:
11798       return "ss";
11799     case 0x3e:
11800       return "ds";
11801     case 0x26:
11802       return "es";
11803     case 0x64:
11804       return "fs";
11805     case 0x65:
11806       return "gs";
11807     case 0x66:
11808       return (sizeflag & DFLAG) ? "data16" : "data32";
11809     case 0x67:
11810       if (address_mode == mode_64bit)
11811         return (sizeflag & AFLAG) ? "addr32" : "addr64";
11812       else
11813         return (sizeflag & AFLAG) ? "addr16" : "addr32";
11814     case FWAIT_OPCODE:
11815       return "fwait";
11816     case ADDR16_PREFIX:
11817       return "addr16";
11818     case ADDR32_PREFIX:
11819       return "addr32";
11820     case DATA16_PREFIX:
11821       return "data16";
11822     case DATA32_PREFIX:
11823       return "data32";
11824     case REP_PREFIX:
11825       return "rep";
11826     case XACQUIRE_PREFIX:
11827       return "xacquire";
11828     case XRELEASE_PREFIX:
11829       return "xrelease";
11830     case BND_PREFIX:
11831       return "bnd";
11832     default:
11833       return NULL;
11834     }
11835 }
11836
11837 static char op_out[MAX_OPERANDS][100];
11838 static int op_ad, op_index[MAX_OPERANDS];
11839 static int two_source_ops;
11840 static bfd_vma op_address[MAX_OPERANDS];
11841 static bfd_vma op_riprel[MAX_OPERANDS];
11842 static bfd_vma start_pc;
11843
11844 /*
11845  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
11846  *   (see topic "Redundant prefixes" in the "Differences from 8086"
11847  *   section of the "Virtual 8086 Mode" chapter.)
11848  * 'pc' should be the address of this instruction, it will
11849  *   be used to print the target address if this is a relative jump or call
11850  * The function returns the length of this instruction in bytes.
11851  */
11852
11853 static char intel_syntax;
11854 static char intel_mnemonic = !SYSV386_COMPAT;
11855 static char open_char;
11856 static char close_char;
11857 static char separator_char;
11858 static char scale_char;
11859
11860 /* Here for backwards compatibility.  When gdb stops using
11861    print_insn_i386_att and print_insn_i386_intel these functions can
11862    disappear, and print_insn_i386 be merged into print_insn.  */
11863 int
11864 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
11865 {
11866   intel_syntax = 0;
11867
11868   return print_insn (pc, info);
11869 }
11870
11871 int
11872 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
11873 {
11874   intel_syntax = 1;
11875
11876   return print_insn (pc, info);
11877 }
11878
11879 int
11880 print_insn_i386 (bfd_vma pc, disassemble_info *info)
11881 {
11882   intel_syntax = -1;
11883
11884   return print_insn (pc, info);
11885 }
11886
11887 void
11888 print_i386_disassembler_options (FILE *stream)
11889 {
11890   fprintf (stream, _("\n\
11891 The following i386/x86-64 specific disassembler options are supported for use\n\
11892 with the -M switch (multiple options should be separated by commas):\n"));
11893
11894   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
11895   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
11896   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
11897   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
11898   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
11899   fprintf (stream, _("  att-mnemonic\n"
11900                      "              Display instruction in AT&T mnemonic\n"));
11901   fprintf (stream, _("  intel-mnemonic\n"
11902                      "              Display instruction in Intel mnemonic\n"));
11903   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
11904   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
11905   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
11906   fprintf (stream, _("  data32      Assume 32bit data size\n"));
11907   fprintf (stream, _("  data16      Assume 16bit data size\n"));
11908   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
11909 }
11910
11911 /* Bad opcode.  */
11912 static const struct dis386 bad_opcode = { "(bad)", { XX } };
11913
11914 /* Get a pointer to struct dis386 with a valid name.  */
11915
11916 static const struct dis386 *
11917 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
11918 {
11919   int vindex, vex_table_index;
11920
11921   if (dp->name != NULL)
11922     return dp;
11923
11924   switch (dp->op[0].bytemode)
11925     {
11926     case USE_REG_TABLE:
11927       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
11928       break;
11929
11930     case USE_MOD_TABLE:
11931       vindex = modrm.mod == 0x3 ? 1 : 0;
11932       dp = &mod_table[dp->op[1].bytemode][vindex];
11933       break;
11934
11935     case USE_RM_TABLE:
11936       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
11937       break;
11938
11939     case USE_PREFIX_TABLE:
11940       if (need_vex)
11941         {
11942           /* The prefix in VEX is implicit.  */
11943           switch (vex.prefix)
11944             {
11945             case 0:
11946               vindex = 0;
11947               break;
11948             case REPE_PREFIX_OPCODE:
11949               vindex = 1;
11950               break;
11951             case DATA_PREFIX_OPCODE:
11952               vindex = 2;
11953               break;
11954             case REPNE_PREFIX_OPCODE:
11955               vindex = 3;
11956               break;
11957             default:
11958               abort ();
11959               break;
11960             }
11961         }
11962       else
11963         {
11964           vindex = 0;
11965           used_prefixes |= (prefixes & PREFIX_REPZ);
11966           if (prefixes & PREFIX_REPZ)
11967             {
11968               vindex = 1;
11969               all_prefixes[last_repz_prefix] = 0;
11970             }
11971           else
11972             {
11973               /* We should check PREFIX_REPNZ and PREFIX_REPZ before
11974                  PREFIX_DATA.  */
11975               used_prefixes |= (prefixes & PREFIX_REPNZ);
11976               if (prefixes & PREFIX_REPNZ)
11977                 {
11978                   vindex = 3;
11979                   all_prefixes[last_repnz_prefix] = 0;
11980                 }
11981               else
11982                 {
11983                   used_prefixes |= (prefixes & PREFIX_DATA);
11984                   if (prefixes & PREFIX_DATA)
11985                     {
11986                       vindex = 2;
11987                       all_prefixes[last_data_prefix] = 0;
11988                     }
11989                 }
11990             }
11991         }
11992       dp = &prefix_table[dp->op[1].bytemode][vindex];
11993       break;
11994
11995     case USE_X86_64_TABLE:
11996       vindex = address_mode == mode_64bit ? 1 : 0;
11997       dp = &x86_64_table[dp->op[1].bytemode][vindex];
11998       break;
11999
12000     case USE_3BYTE_TABLE:
12001       FETCH_DATA (info, codep + 2);
12002       vindex = *codep++;
12003       dp = &three_byte_table[dp->op[1].bytemode][vindex];
12004       modrm.mod = (*codep >> 6) & 3;
12005       modrm.reg = (*codep >> 3) & 7;
12006       modrm.rm = *codep & 7;
12007       break;
12008
12009     case USE_VEX_LEN_TABLE:
12010       if (!need_vex)
12011         abort ();
12012
12013       switch (vex.length)
12014         {
12015         case 128:
12016           vindex = 0;
12017           break;
12018         case 256:
12019           vindex = 1;
12020           break;
12021         default:
12022           abort ();
12023           break;
12024         }
12025
12026       dp = &vex_len_table[dp->op[1].bytemode][vindex];
12027       break;
12028
12029     case USE_XOP_8F_TABLE:
12030       FETCH_DATA (info, codep + 3);
12031       /* All bits in the REX prefix are ignored.  */
12032       rex_ignored = rex;
12033       rex = ~(*codep >> 5) & 0x7;
12034
12035       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
12036       switch ((*codep & 0x1f))
12037         {
12038         default:
12039           dp = &bad_opcode;
12040           return dp;
12041         case 0x8:
12042           vex_table_index = XOP_08;
12043           break;
12044         case 0x9:
12045           vex_table_index = XOP_09;
12046           break;
12047         case 0xa:
12048           vex_table_index = XOP_0A;
12049           break;
12050         }
12051       codep++;
12052       vex.w = *codep & 0x80;
12053       if (vex.w && address_mode == mode_64bit)
12054         rex |= REX_W;
12055
12056       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12057       if (address_mode != mode_64bit
12058           && vex.register_specifier > 0x7)
12059         {
12060           dp = &bad_opcode;
12061           return dp;
12062         }
12063
12064       vex.length = (*codep & 0x4) ? 256 : 128;
12065       switch ((*codep & 0x3))
12066         {
12067         case 0:
12068           vex.prefix = 0;
12069           break;
12070         case 1:
12071           vex.prefix = DATA_PREFIX_OPCODE;
12072           break;
12073         case 2:
12074           vex.prefix = REPE_PREFIX_OPCODE;
12075           break;
12076         case 3:
12077           vex.prefix = REPNE_PREFIX_OPCODE;
12078           break;
12079         }
12080       need_vex = 1;
12081       need_vex_reg = 1;
12082       codep++;
12083       vindex = *codep++;
12084       dp = &xop_table[vex_table_index][vindex];
12085
12086       FETCH_DATA (info, codep + 1);
12087       modrm.mod = (*codep >> 6) & 3;
12088       modrm.reg = (*codep >> 3) & 7;
12089       modrm.rm = *codep & 7;
12090       break;
12091
12092     case USE_VEX_C4_TABLE:
12093       /* VEX prefix.  */
12094       FETCH_DATA (info, codep + 3);
12095       /* All bits in the REX prefix are ignored.  */
12096       rex_ignored = rex;
12097       rex = ~(*codep >> 5) & 0x7;
12098       switch ((*codep & 0x1f))
12099         {
12100         default:
12101           dp = &bad_opcode;
12102           return dp;
12103         case 0x1:
12104           vex_table_index = VEX_0F;
12105           break;
12106         case 0x2:
12107           vex_table_index = VEX_0F38;
12108           break;
12109         case 0x3:
12110           vex_table_index = VEX_0F3A;
12111           break;
12112         }
12113       codep++;
12114       vex.w = *codep & 0x80;
12115       if (vex.w && address_mode == mode_64bit)
12116         rex |= REX_W;
12117
12118       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12119       if (address_mode != mode_64bit
12120           && vex.register_specifier > 0x7)
12121         {
12122           dp = &bad_opcode;
12123           return dp;
12124         }
12125
12126       vex.length = (*codep & 0x4) ? 256 : 128;
12127       switch ((*codep & 0x3))
12128         {
12129         case 0:
12130           vex.prefix = 0;
12131           break;
12132         case 1:
12133           vex.prefix = DATA_PREFIX_OPCODE;
12134           break;
12135         case 2:
12136           vex.prefix = REPE_PREFIX_OPCODE;
12137           break;
12138         case 3:
12139           vex.prefix = REPNE_PREFIX_OPCODE;
12140           break;
12141         }
12142       need_vex = 1;
12143       need_vex_reg = 1;
12144       codep++;
12145       vindex = *codep++;
12146       dp = &vex_table[vex_table_index][vindex];
12147       /* There is no MODRM byte for VEX [82|77].  */
12148       if (vindex != 0x77 && vindex != 0x82)
12149         {
12150           FETCH_DATA (info, codep + 1);
12151           modrm.mod = (*codep >> 6) & 3;
12152           modrm.reg = (*codep >> 3) & 7;
12153           modrm.rm = *codep & 7;
12154         }
12155       break;
12156
12157     case USE_VEX_C5_TABLE:
12158       /* VEX prefix.  */
12159       FETCH_DATA (info, codep + 2);
12160       /* All bits in the REX prefix are ignored.  */
12161       rex_ignored = rex;
12162       rex = (*codep & 0x80) ? 0 : REX_R;
12163
12164       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12165       if (address_mode != mode_64bit
12166           && vex.register_specifier > 0x7)
12167         {
12168           dp = &bad_opcode;
12169           return dp;
12170         }
12171
12172       vex.w = 0;
12173
12174       vex.length = (*codep & 0x4) ? 256 : 128;
12175       switch ((*codep & 0x3))
12176         {
12177         case 0:
12178           vex.prefix = 0;
12179           break;
12180         case 1:
12181           vex.prefix = DATA_PREFIX_OPCODE;
12182           break;
12183         case 2:
12184           vex.prefix = REPE_PREFIX_OPCODE;
12185           break;
12186         case 3:
12187           vex.prefix = REPNE_PREFIX_OPCODE;
12188           break;
12189         }
12190       need_vex = 1;
12191       need_vex_reg = 1;
12192       codep++;
12193       vindex = *codep++;
12194       dp = &vex_table[dp->op[1].bytemode][vindex];
12195       /* There is no MODRM byte for VEX [82|77].  */
12196       if (vindex != 0x77 && vindex != 0x82)
12197         {
12198           FETCH_DATA (info, codep + 1);
12199           modrm.mod = (*codep >> 6) & 3;
12200           modrm.reg = (*codep >> 3) & 7;
12201           modrm.rm = *codep & 7;
12202         }
12203       break;
12204
12205     case USE_VEX_W_TABLE:
12206       if (!need_vex)
12207         abort ();
12208
12209       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
12210       break;
12211
12212     case USE_EVEX_TABLE:
12213       two_source_ops = 0;
12214       /* EVEX prefix.  */
12215       vex.evex = 1;
12216       FETCH_DATA (info, codep + 4);
12217       /* All bits in the REX prefix are ignored.  */
12218       rex_ignored = rex;
12219       /* The first byte after 0x62.  */
12220       rex = ~(*codep >> 5) & 0x7;
12221       vex.r = *codep & 0x10;
12222       switch ((*codep & 0xf))
12223         {
12224         default:
12225           return &bad_opcode;
12226         case 0x1:
12227           vex_table_index = EVEX_0F;
12228           break;
12229         case 0x2:
12230           vex_table_index = EVEX_0F38;
12231           break;
12232         case 0x3:
12233           vex_table_index = EVEX_0F3A;
12234           break;
12235         }
12236
12237       /* The second byte after 0x62.  */
12238       codep++;
12239       vex.w = *codep & 0x80;
12240       if (vex.w && address_mode == mode_64bit)
12241         rex |= REX_W;
12242
12243       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12244       if (address_mode != mode_64bit)
12245         {
12246           /* In 16/32-bit mode silently ignore following bits.  */
12247           rex &= ~REX_B;
12248           vex.r = 1;
12249           vex.v = 1;
12250           vex.register_specifier &= 0x7;
12251         }
12252
12253       /* The U bit.  */
12254       if (!(*codep & 0x4))
12255         return &bad_opcode;
12256
12257       switch ((*codep & 0x3))
12258         {
12259         case 0:
12260           vex.prefix = 0;
12261           break;
12262         case 1:
12263           vex.prefix = DATA_PREFIX_OPCODE;
12264           break;
12265         case 2:
12266           vex.prefix = REPE_PREFIX_OPCODE;
12267           break;
12268         case 3:
12269           vex.prefix = REPNE_PREFIX_OPCODE;
12270           break;
12271         }
12272
12273       /* The third byte after 0x62.  */
12274       codep++;
12275
12276       /* Remember the static rounding bits.  */
12277       vex.ll = (*codep >> 5) & 3;
12278       vex.b = (*codep & 0x10) != 0;
12279
12280       vex.v = *codep & 0x8;
12281       vex.mask_register_specifier = *codep & 0x7;
12282       vex.zeroing = *codep & 0x80;
12283
12284       need_vex = 1;
12285       need_vex_reg = 1;
12286       codep++;
12287       vindex = *codep++;
12288       dp = &evex_table[vex_table_index][vindex];
12289       FETCH_DATA (info, codep + 1);
12290       modrm.mod = (*codep >> 6) & 3;
12291       modrm.reg = (*codep >> 3) & 7;
12292       modrm.rm = *codep & 7;
12293
12294       /* Set vector length.  */
12295       if (modrm.mod == 3 && vex.b)
12296         vex.length = 512;
12297       else
12298         {
12299           switch (vex.ll)
12300             {
12301             case 0x0:
12302               vex.length = 128;
12303               break;
12304             case 0x1:
12305               vex.length = 256;
12306               break;
12307             case 0x2:
12308               vex.length = 512;
12309               break;
12310             default:
12311               return &bad_opcode;
12312             }
12313         }
12314       break;
12315
12316     case 0:
12317       dp = &bad_opcode;
12318       break;
12319
12320     default:
12321       abort ();
12322     }
12323
12324   if (dp->name != NULL)
12325     return dp;
12326   else
12327     return get_valid_dis386 (dp, info);
12328 }
12329
12330 static void
12331 get_sib (disassemble_info *info, int sizeflag)
12332 {
12333   /* If modrm.mod == 3, operand must be register.  */
12334   if (need_modrm
12335       && ((sizeflag & AFLAG) || address_mode == mode_64bit)
12336       && modrm.mod != 3
12337       && modrm.rm == 4)
12338     {
12339       FETCH_DATA (info, codep + 2);
12340       sib.index = (codep [1] >> 3) & 7;
12341       sib.scale = (codep [1] >> 6) & 3;
12342       sib.base = codep [1] & 7;
12343     }
12344 }
12345
12346 static int
12347 print_insn (bfd_vma pc, disassemble_info *info)
12348 {
12349   const struct dis386 *dp;
12350   int i;
12351   char *op_txt[MAX_OPERANDS];
12352   int needcomma;
12353   int sizeflag;
12354   const char *p;
12355   struct dis_private priv;
12356   int prefix_length;
12357   int default_prefixes;
12358
12359   priv.orig_sizeflag = AFLAG | DFLAG;
12360   if ((info->mach & bfd_mach_i386_i386) != 0)
12361     address_mode = mode_32bit;
12362   else if (info->mach == bfd_mach_i386_i8086)
12363     {
12364       address_mode = mode_16bit;
12365       priv.orig_sizeflag = 0;
12366     }
12367   else
12368     address_mode = mode_64bit;
12369
12370   if (intel_syntax == (char) -1)
12371     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
12372
12373   for (p = info->disassembler_options; p != NULL; )
12374     {
12375       if (CONST_STRNEQ (p, "x86-64"))
12376         {
12377           address_mode = mode_64bit;
12378           priv.orig_sizeflag = AFLAG | DFLAG;
12379         }
12380       else if (CONST_STRNEQ (p, "i386"))
12381         {
12382           address_mode = mode_32bit;
12383           priv.orig_sizeflag = AFLAG | DFLAG;
12384         }
12385       else if (CONST_STRNEQ (p, "i8086"))
12386         {
12387           address_mode = mode_16bit;
12388           priv.orig_sizeflag = 0;
12389         }
12390       else if (CONST_STRNEQ (p, "intel"))
12391         {
12392           intel_syntax = 1;
12393           if (CONST_STRNEQ (p + 5, "-mnemonic"))
12394             intel_mnemonic = 1;
12395         }
12396       else if (CONST_STRNEQ (p, "att"))
12397         {
12398           intel_syntax = 0;
12399           if (CONST_STRNEQ (p + 3, "-mnemonic"))
12400             intel_mnemonic = 0;
12401         }
12402       else if (CONST_STRNEQ (p, "addr"))
12403         {
12404           if (address_mode == mode_64bit)
12405             {
12406               if (p[4] == '3' && p[5] == '2')
12407                 priv.orig_sizeflag &= ~AFLAG;
12408               else if (p[4] == '6' && p[5] == '4')
12409                 priv.orig_sizeflag |= AFLAG;
12410             }
12411           else
12412             {
12413               if (p[4] == '1' && p[5] == '6')
12414                 priv.orig_sizeflag &= ~AFLAG;
12415               else if (p[4] == '3' && p[5] == '2')
12416                 priv.orig_sizeflag |= AFLAG;
12417             }
12418         }
12419       else if (CONST_STRNEQ (p, "data"))
12420         {
12421           if (p[4] == '1' && p[5] == '6')
12422             priv.orig_sizeflag &= ~DFLAG;
12423           else if (p[4] == '3' && p[5] == '2')
12424             priv.orig_sizeflag |= DFLAG;
12425         }
12426       else if (CONST_STRNEQ (p, "suffix"))
12427         priv.orig_sizeflag |= SUFFIX_ALWAYS;
12428
12429       p = strchr (p, ',');
12430       if (p != NULL)
12431         p++;
12432     }
12433
12434   if (intel_syntax)
12435     {
12436       names64 = intel_names64;
12437       names32 = intel_names32;
12438       names16 = intel_names16;
12439       names8 = intel_names8;
12440       names8rex = intel_names8rex;
12441       names_seg = intel_names_seg;
12442       names_mm = intel_names_mm;
12443       names_bnd = intel_names_bnd;
12444       names_xmm = intel_names_xmm;
12445       names_ymm = intel_names_ymm;
12446       names_zmm = intel_names_zmm;
12447       index64 = intel_index64;
12448       index32 = intel_index32;
12449       names_mask = intel_names_mask;
12450       index16 = intel_index16;
12451       open_char = '[';
12452       close_char = ']';
12453       separator_char = '+';
12454       scale_char = '*';
12455     }
12456   else
12457     {
12458       names64 = att_names64;
12459       names32 = att_names32;
12460       names16 = att_names16;
12461       names8 = att_names8;
12462       names8rex = att_names8rex;
12463       names_seg = att_names_seg;
12464       names_mm = att_names_mm;
12465       names_bnd = att_names_bnd;
12466       names_xmm = att_names_xmm;
12467       names_ymm = att_names_ymm;
12468       names_zmm = att_names_zmm;
12469       index64 = att_index64;
12470       index32 = att_index32;
12471       names_mask = att_names_mask;
12472       index16 = att_index16;
12473       open_char = '(';
12474       close_char =  ')';
12475       separator_char = ',';
12476       scale_char = ',';
12477     }
12478
12479   /* The output looks better if we put 7 bytes on a line, since that
12480      puts most long word instructions on a single line.  Use 8 bytes
12481      for Intel L1OM.  */
12482   if ((info->mach & bfd_mach_l1om) != 0)
12483     info->bytes_per_line = 8;
12484   else
12485     info->bytes_per_line = 7;
12486
12487   info->private_data = &priv;
12488   priv.max_fetched = priv.the_buffer;
12489   priv.insn_start = pc;
12490
12491   obuf[0] = 0;
12492   for (i = 0; i < MAX_OPERANDS; ++i)
12493     {
12494       op_out[i][0] = 0;
12495       op_index[i] = -1;
12496     }
12497
12498   the_info = info;
12499   start_pc = pc;
12500   start_codep = priv.the_buffer;
12501   codep = priv.the_buffer;
12502
12503   if (OPCODES_SIGSETJMP (priv.bailout) != 0)
12504     {
12505       const char *name;
12506
12507       /* Getting here means we tried for data but didn't get it.  That
12508          means we have an incomplete instruction of some sort.  Just
12509          print the first byte as a prefix or a .byte pseudo-op.  */
12510       if (codep > priv.the_buffer)
12511         {
12512           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
12513           if (name != NULL)
12514             (*info->fprintf_func) (info->stream, "%s", name);
12515           else
12516             {
12517               /* Just print the first byte as a .byte instruction.  */
12518               (*info->fprintf_func) (info->stream, ".byte 0x%x",
12519                                      (unsigned int) priv.the_buffer[0]);
12520             }
12521
12522           return 1;
12523         }
12524
12525       return -1;
12526     }
12527
12528   obufp = obuf;
12529   sizeflag = priv.orig_sizeflag;
12530
12531   if (!ckprefix () || rex_used)
12532     {
12533       /* Too many prefixes or unused REX prefixes.  */
12534       for (i = 0;
12535            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
12536            i++)
12537         (*info->fprintf_func) (info->stream, "%s%s",
12538                                i == 0 ? "" : " ",
12539                                prefix_name (all_prefixes[i], sizeflag));
12540       return i;
12541     }
12542
12543   insn_codep = codep;
12544
12545   FETCH_DATA (info, codep + 1);
12546   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
12547
12548   if (((prefixes & PREFIX_FWAIT)
12549        && ((*codep < 0xd8) || (*codep > 0xdf))))
12550     {
12551       /* Handle prefixes before fwait.  */
12552       for (i = 0;
12553            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
12554            i++)
12555         (*info->fprintf_func) (info->stream, "%s ",
12556                                prefix_name (all_prefixes[i], sizeflag));
12557       (*info->fprintf_func) (info->stream, "fwait");
12558       return i + 1;
12559     }
12560
12561   if (*codep == 0x0f)
12562     {
12563       unsigned char threebyte;
12564       FETCH_DATA (info, codep + 2);
12565       threebyte = *++codep;
12566       dp = &dis386_twobyte[threebyte];
12567       need_modrm = twobyte_has_modrm[*codep];
12568       codep++;
12569     }
12570   else
12571     {
12572       dp = &dis386[*codep];
12573       need_modrm = onebyte_has_modrm[*codep];
12574       codep++;
12575     }
12576
12577   if ((prefixes & PREFIX_REPZ))
12578     used_prefixes |= PREFIX_REPZ;
12579   if ((prefixes & PREFIX_REPNZ))
12580     used_prefixes |= PREFIX_REPNZ;
12581   if ((prefixes & PREFIX_LOCK))
12582     used_prefixes |= PREFIX_LOCK;
12583
12584   default_prefixes = 0;
12585   if (prefixes & PREFIX_ADDR)
12586     {
12587       sizeflag ^= AFLAG;
12588       if (dp->op[2].bytemode != loop_jcxz_mode || intel_syntax)
12589         {
12590           if ((sizeflag & AFLAG) || address_mode == mode_64bit)
12591             all_prefixes[last_addr_prefix] = ADDR32_PREFIX;
12592           else
12593             all_prefixes[last_addr_prefix] = ADDR16_PREFIX;
12594           default_prefixes |= PREFIX_ADDR;
12595         }
12596     }
12597
12598   if ((prefixes & PREFIX_DATA))
12599     {
12600       sizeflag ^= DFLAG;
12601       if (dp->op[2].bytemode == cond_jump_mode
12602           && dp->op[0].bytemode == v_mode
12603           && !intel_syntax)
12604         {
12605           if (sizeflag & DFLAG)
12606             all_prefixes[last_data_prefix] = DATA32_PREFIX;
12607           else
12608             all_prefixes[last_data_prefix] = DATA16_PREFIX;
12609           default_prefixes |= PREFIX_DATA;
12610         }
12611       else if (rex & REX_W)
12612         {
12613           /* REX_W will override PREFIX_DATA.  */
12614           default_prefixes |= PREFIX_DATA;
12615         }
12616     }
12617
12618   if (need_modrm)
12619     {
12620       FETCH_DATA (info, codep + 1);
12621       modrm.mod = (*codep >> 6) & 3;
12622       modrm.reg = (*codep >> 3) & 7;
12623       modrm.rm = *codep & 7;
12624     }
12625
12626   need_vex = 0;
12627   need_vex_reg = 0;
12628   vex_w_done = 0;
12629   vex.evex = 0;
12630
12631   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
12632     {
12633       get_sib (info, sizeflag);
12634       dofloat (sizeflag);
12635     }
12636   else
12637     {
12638       dp = get_valid_dis386 (dp, info);
12639       if (dp != NULL && putop (dp->name, sizeflag) == 0)
12640         {
12641           get_sib (info, sizeflag);
12642           for (i = 0; i < MAX_OPERANDS; ++i)
12643             {
12644               obufp = op_out[i];
12645               op_ad = MAX_OPERANDS - 1 - i;
12646               if (dp->op[i].rtn)
12647                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
12648               /* For EVEX instruction after the last operand masking
12649                  should be printed.  */
12650               if (i == 0 && vex.evex)
12651                 {
12652                   /* Don't print {%k0}.  */
12653                   if (vex.mask_register_specifier)
12654                     {
12655                       oappend ("{");
12656                       oappend (names_mask[vex.mask_register_specifier]);
12657                       oappend ("}");
12658                     }
12659                   if (vex.zeroing)
12660                     oappend ("{z}");
12661                 }
12662             }
12663         }
12664     }
12665
12666   /* See if any prefixes were not used.  If so, print the first one
12667      separately.  If we don't do this, we'll wind up printing an
12668      instruction stream which does not precisely correspond to the
12669      bytes we are disassembling.  */
12670   if ((prefixes & ~(used_prefixes | default_prefixes)) != 0)
12671     {
12672       for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12673         if (all_prefixes[i])
12674           {
12675             const char *name;
12676             name = prefix_name (all_prefixes[i], priv.orig_sizeflag);
12677             if (name == NULL)
12678               name = INTERNAL_DISASSEMBLER_ERROR;
12679             (*info->fprintf_func) (info->stream, "%s", name);
12680             return 1;
12681           }
12682     }
12683
12684   /* Check if the REX prefix is used.  */
12685   if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)
12686     all_prefixes[last_rex_prefix] = 0;
12687
12688   /* Check if the SEG prefix is used.  */
12689   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
12690                    | PREFIX_FS | PREFIX_GS)) != 0
12691       && (used_prefixes
12692           & seg_prefix (all_prefixes[last_seg_prefix])) != 0)
12693     all_prefixes[last_seg_prefix] = 0;
12694
12695   /* Check if the ADDR prefix is used.  */
12696   if ((prefixes & PREFIX_ADDR) != 0
12697       && (used_prefixes & PREFIX_ADDR) != 0)
12698     all_prefixes[last_addr_prefix] = 0;
12699
12700   /* Check if the DATA prefix is used.  */
12701   if ((prefixes & PREFIX_DATA) != 0
12702       && (used_prefixes & PREFIX_DATA) != 0)
12703     all_prefixes[last_data_prefix] = 0;
12704
12705   prefix_length = 0;
12706   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12707     if (all_prefixes[i])
12708       {
12709         const char *name;
12710         name = prefix_name (all_prefixes[i], sizeflag);
12711         if (name == NULL)
12712           abort ();
12713         prefix_length += strlen (name) + 1;
12714         (*info->fprintf_func) (info->stream, "%s ", name);
12715       }
12716
12717   /* Check maximum code length.  */
12718   if ((codep - start_codep) > MAX_CODE_LENGTH)
12719     {
12720       (*info->fprintf_func) (info->stream, "(bad)");
12721       return MAX_CODE_LENGTH;
12722     }
12723
12724   obufp = mnemonicendp;
12725   for (i = strlen (obuf) + prefix_length; i < 6; i++)
12726     oappend (" ");
12727   oappend (" ");
12728   (*info->fprintf_func) (info->stream, "%s", obuf);
12729
12730   /* The enter and bound instructions are printed with operands in the same
12731      order as the intel book; everything else is printed in reverse order.  */
12732   if (intel_syntax || two_source_ops)
12733     {
12734       bfd_vma riprel;
12735
12736       for (i = 0; i < MAX_OPERANDS; ++i)
12737         op_txt[i] = op_out[i];
12738
12739       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
12740         {
12741           op_ad = op_index[i];
12742           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
12743           op_index[MAX_OPERANDS - 1 - i] = op_ad;
12744           riprel = op_riprel[i];
12745           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
12746           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
12747         }
12748     }
12749   else
12750     {
12751       for (i = 0; i < MAX_OPERANDS; ++i)
12752         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
12753     }
12754
12755   needcomma = 0;
12756   for (i = 0; i < MAX_OPERANDS; ++i)
12757     if (*op_txt[i])
12758       {
12759         if (needcomma)
12760           (*info->fprintf_func) (info->stream, ",");
12761         if (op_index[i] != -1 && !op_riprel[i])
12762           (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
12763         else
12764           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
12765         needcomma = 1;
12766       }
12767
12768   for (i = 0; i < MAX_OPERANDS; i++)
12769     if (op_index[i] != -1 && op_riprel[i])
12770       {
12771         (*info->fprintf_func) (info->stream, "        # ");
12772         (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep
12773                                                 + op_address[op_index[i]]), info);
12774         break;
12775       }
12776   return codep - priv.the_buffer;
12777 }
12778
12779 static const char *float_mem[] = {
12780   /* d8 */
12781   "fadd{s|}",
12782   "fmul{s|}",
12783   "fcom{s|}",
12784   "fcomp{s|}",
12785   "fsub{s|}",
12786   "fsubr{s|}",
12787   "fdiv{s|}",
12788   "fdivr{s|}",
12789   /* d9 */
12790   "fld{s|}",
12791   "(bad)",
12792   "fst{s|}",
12793   "fstp{s|}",
12794   "fldenvIC",
12795   "fldcw",
12796   "fNstenvIC",
12797   "fNstcw",
12798   /* da */
12799   "fiadd{l|}",
12800   "fimul{l|}",
12801   "ficom{l|}",
12802   "ficomp{l|}",
12803   "fisub{l|}",
12804   "fisubr{l|}",
12805   "fidiv{l|}",
12806   "fidivr{l|}",
12807   /* db */
12808   "fild{l|}",
12809   "fisttp{l|}",
12810   "fist{l|}",
12811   "fistp{l|}",
12812   "(bad)",
12813   "fld{t||t|}",
12814   "(bad)",
12815   "fstp{t||t|}",
12816   /* dc */
12817   "fadd{l|}",
12818   "fmul{l|}",
12819   "fcom{l|}",
12820   "fcomp{l|}",
12821   "fsub{l|}",
12822   "fsubr{l|}",
12823   "fdiv{l|}",
12824   "fdivr{l|}",
12825   /* dd */
12826   "fld{l|}",
12827   "fisttp{ll|}",
12828   "fst{l||}",
12829   "fstp{l|}",
12830   "frstorIC",
12831   "(bad)",
12832   "fNsaveIC",
12833   "fNstsw",
12834   /* de */
12835   "fiadd",
12836   "fimul",
12837   "ficom",
12838   "ficomp",
12839   "fisub",
12840   "fisubr",
12841   "fidiv",
12842   "fidivr",
12843   /* df */
12844   "fild",
12845   "fisttp",
12846   "fist",
12847   "fistp",
12848   "fbld",
12849   "fild{ll|}",
12850   "fbstp",
12851   "fistp{ll|}",
12852 };
12853
12854 static const unsigned char float_mem_mode[] = {
12855   /* d8 */
12856   d_mode,
12857   d_mode,
12858   d_mode,
12859   d_mode,
12860   d_mode,
12861   d_mode,
12862   d_mode,
12863   d_mode,
12864   /* d9 */
12865   d_mode,
12866   0,
12867   d_mode,
12868   d_mode,
12869   0,
12870   w_mode,
12871   0,
12872   w_mode,
12873   /* da */
12874   d_mode,
12875   d_mode,
12876   d_mode,
12877   d_mode,
12878   d_mode,
12879   d_mode,
12880   d_mode,
12881   d_mode,
12882   /* db */
12883   d_mode,
12884   d_mode,
12885   d_mode,
12886   d_mode,
12887   0,
12888   t_mode,
12889   0,
12890   t_mode,
12891   /* dc */
12892   q_mode,
12893   q_mode,
12894   q_mode,
12895   q_mode,
12896   q_mode,
12897   q_mode,
12898   q_mode,
12899   q_mode,
12900   /* dd */
12901   q_mode,
12902   q_mode,
12903   q_mode,
12904   q_mode,
12905   0,
12906   0,
12907   0,
12908   w_mode,
12909   /* de */
12910   w_mode,
12911   w_mode,
12912   w_mode,
12913   w_mode,
12914   w_mode,
12915   w_mode,
12916   w_mode,
12917   w_mode,
12918   /* df */
12919   w_mode,
12920   w_mode,
12921   w_mode,
12922   w_mode,
12923   t_mode,
12924   q_mode,
12925   t_mode,
12926   q_mode
12927 };
12928
12929 #define ST { OP_ST, 0 }
12930 #define STi { OP_STi, 0 }
12931
12932 #define FGRPd9_2 NULL, { { NULL, 0 } }
12933 #define FGRPd9_4 NULL, { { NULL, 1 } }
12934 #define FGRPd9_5 NULL, { { NULL, 2 } }
12935 #define FGRPd9_6 NULL, { { NULL, 3 } }
12936 #define FGRPd9_7 NULL, { { NULL, 4 } }
12937 #define FGRPda_5 NULL, { { NULL, 5 } }
12938 #define FGRPdb_4 NULL, { { NULL, 6 } }
12939 #define FGRPde_3 NULL, { { NULL, 7 } }
12940 #define FGRPdf_4 NULL, { { NULL, 8 } }
12941
12942 static const struct dis386 float_reg[][8] = {
12943   /* d8 */
12944   {
12945     { "fadd",   { ST, STi } },
12946     { "fmul",   { ST, STi } },
12947     { "fcom",   { STi } },
12948     { "fcomp",  { STi } },
12949     { "fsub",   { ST, STi } },
12950     { "fsubr",  { ST, STi } },
12951     { "fdiv",   { ST, STi } },
12952     { "fdivr",  { ST, STi } },
12953   },
12954   /* d9 */
12955   {
12956     { "fld",    { STi } },
12957     { "fxch",   { STi } },
12958     { FGRPd9_2 },
12959     { Bad_Opcode },
12960     { FGRPd9_4 },
12961     { FGRPd9_5 },
12962     { FGRPd9_6 },
12963     { FGRPd9_7 },
12964   },
12965   /* da */
12966   {
12967     { "fcmovb", { ST, STi } },
12968     { "fcmove", { ST, STi } },
12969     { "fcmovbe",{ ST, STi } },
12970     { "fcmovu", { ST, STi } },
12971     { Bad_Opcode },
12972     { FGRPda_5 },
12973     { Bad_Opcode },
12974     { Bad_Opcode },
12975   },
12976   /* db */
12977   {
12978     { "fcmovnb",{ ST, STi } },
12979     { "fcmovne",{ ST, STi } },
12980     { "fcmovnbe",{ ST, STi } },
12981     { "fcmovnu",{ ST, STi } },
12982     { FGRPdb_4 },
12983     { "fucomi", { ST, STi } },
12984     { "fcomi",  { ST, STi } },
12985     { Bad_Opcode },
12986   },
12987   /* dc */
12988   {
12989     { "fadd",   { STi, ST } },
12990     { "fmul",   { STi, ST } },
12991     { Bad_Opcode },
12992     { Bad_Opcode },
12993     { "fsub!M", { STi, ST } },
12994     { "fsubM",  { STi, ST } },
12995     { "fdiv!M", { STi, ST } },
12996     { "fdivM",  { STi, ST } },
12997   },
12998   /* dd */
12999   {
13000     { "ffree",  { STi } },
13001     { Bad_Opcode },
13002     { "fst",    { STi } },
13003     { "fstp",   { STi } },
13004     { "fucom",  { STi } },
13005     { "fucomp", { STi } },
13006     { Bad_Opcode },
13007     { Bad_Opcode },
13008   },
13009   /* de */
13010   {
13011     { "faddp",  { STi, ST } },
13012     { "fmulp",  { STi, ST } },
13013     { Bad_Opcode },
13014     { FGRPde_3 },
13015     { "fsub!Mp", { STi, ST } },
13016     { "fsubMp", { STi, ST } },
13017     { "fdiv!Mp", { STi, ST } },
13018     { "fdivMp", { STi, ST } },
13019   },
13020   /* df */
13021   {
13022     { "ffreep", { STi } },
13023     { Bad_Opcode },
13024     { Bad_Opcode },
13025     { Bad_Opcode },
13026     { FGRPdf_4 },
13027     { "fucomip", { ST, STi } },
13028     { "fcomip", { ST, STi } },
13029     { Bad_Opcode },
13030   },
13031 };
13032
13033 static char *fgrps[][8] = {
13034   /* d9_2  0 */
13035   {
13036     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13037   },
13038
13039   /* d9_4  1 */
13040   {
13041     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
13042   },
13043
13044   /* d9_5  2 */
13045   {
13046     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
13047   },
13048
13049   /* d9_6  3 */
13050   {
13051     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
13052   },
13053
13054   /* d9_7  4 */
13055   {
13056     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
13057   },
13058
13059   /* da_5  5 */
13060   {
13061     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13062   },
13063
13064   /* db_4  6 */
13065   {
13066     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
13067     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
13068   },
13069
13070   /* de_3  7 */
13071   {
13072     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13073   },
13074
13075   /* df_4  8 */
13076   {
13077     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13078   },
13079 };
13080
13081 static void
13082 swap_operand (void)
13083 {
13084   mnemonicendp[0] = '.';
13085   mnemonicendp[1] = 's';
13086   mnemonicendp += 2;
13087 }
13088
13089 static void
13090 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
13091                int sizeflag ATTRIBUTE_UNUSED)
13092 {
13093   /* Skip mod/rm byte.  */
13094   MODRM_CHECK;
13095   codep++;
13096 }
13097
13098 static void
13099 dofloat (int sizeflag)
13100 {
13101   const struct dis386 *dp;
13102   unsigned char floatop;
13103
13104   floatop = codep[-1];
13105
13106   if (modrm.mod != 3)
13107     {
13108       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
13109
13110       putop (float_mem[fp_indx], sizeflag);
13111       obufp = op_out[0];
13112       op_ad = 2;
13113       OP_E (float_mem_mode[fp_indx], sizeflag);
13114       return;
13115     }
13116   /* Skip mod/rm byte.  */
13117   MODRM_CHECK;
13118   codep++;
13119
13120   dp = &float_reg[floatop - 0xd8][modrm.reg];
13121   if (dp->name == NULL)
13122     {
13123       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
13124
13125       /* Instruction fnstsw is only one with strange arg.  */
13126       if (floatop == 0xdf && codep[-1] == 0xe0)
13127         strcpy (op_out[0], names16[0]);
13128     }
13129   else
13130     {
13131       putop (dp->name, sizeflag);
13132
13133       obufp = op_out[0];
13134       op_ad = 2;
13135       if (dp->op[0].rtn)
13136         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
13137
13138       obufp = op_out[1];
13139       op_ad = 1;
13140       if (dp->op[1].rtn)
13141         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
13142     }
13143 }
13144
13145 /* Like oappend (below), but S is a string starting with '%'.
13146    In Intel syntax, the '%' is elided.  */
13147 static void
13148 oappend_maybe_intel (const char *s)
13149 {
13150   oappend (s + intel_syntax);
13151 }
13152
13153 static void
13154 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13155 {
13156   oappend_maybe_intel ("%st");
13157 }
13158
13159 static void
13160 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13161 {
13162   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
13163   oappend_maybe_intel (scratchbuf);
13164 }
13165
13166 /* Capital letters in template are macros.  */
13167 static int
13168 putop (const char *in_template, int sizeflag)
13169 {
13170   const char *p;
13171   int alt = 0;
13172   int cond = 1;
13173   unsigned int l = 0, len = 1;
13174   char last[4];
13175
13176 #define SAVE_LAST(c)                    \
13177   if (l < len && l < sizeof (last))     \
13178     last[l++] = c;                      \
13179   else                                  \
13180     abort ();
13181
13182   for (p = in_template; *p; p++)
13183     {
13184       switch (*p)
13185         {
13186         default:
13187           *obufp++ = *p;
13188           break;
13189         case '%':
13190           len++;
13191           break;
13192         case '!':
13193           cond = 0;
13194           break;
13195         case '{':
13196           alt = 0;
13197           if (intel_syntax)
13198             {
13199               while (*++p != '|')
13200                 if (*p == '}' || *p == '\0')
13201                   abort ();
13202             }
13203           /* Fall through.  */
13204         case 'I':
13205           alt = 1;
13206           continue;
13207         case '|':
13208           while (*++p != '}')
13209             {
13210               if (*p == '\0')
13211                 abort ();
13212             }
13213           break;
13214         case '}':
13215           break;
13216         case 'A':
13217           if (intel_syntax)
13218             break;
13219           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13220             *obufp++ = 'b';
13221           break;
13222         case 'B':
13223           if (l == 0 && len == 1)
13224             {
13225 case_B:
13226               if (intel_syntax)
13227                 break;
13228               if (sizeflag & SUFFIX_ALWAYS)
13229                 *obufp++ = 'b';
13230             }
13231           else
13232             {
13233               if (l != 1
13234                   || len != 2
13235                   || last[0] != 'L')
13236                 {
13237                   SAVE_LAST (*p);
13238                   break;
13239                 }
13240
13241               if (address_mode == mode_64bit
13242                   && !(prefixes & PREFIX_ADDR))
13243                 {
13244                   *obufp++ = 'a';
13245                   *obufp++ = 'b';
13246                   *obufp++ = 's';
13247                 }
13248
13249               goto case_B;
13250             }
13251           break;
13252         case 'C':
13253           if (intel_syntax && !alt)
13254             break;
13255           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
13256             {
13257               if (sizeflag & DFLAG)
13258                 *obufp++ = intel_syntax ? 'd' : 'l';
13259               else
13260                 *obufp++ = intel_syntax ? 'w' : 's';
13261               used_prefixes |= (prefixes & PREFIX_DATA);
13262             }
13263           break;
13264         case 'D':
13265           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
13266             break;
13267           USED_REX (REX_W);
13268           if (modrm.mod == 3)
13269             {
13270               if (rex & REX_W)
13271                 *obufp++ = 'q';
13272               else
13273                 {
13274                   if (sizeflag & DFLAG)
13275                     *obufp++ = intel_syntax ? 'd' : 'l';
13276                   else
13277                     *obufp++ = 'w';
13278                   used_prefixes |= (prefixes & PREFIX_DATA);
13279                 }
13280             }
13281           else
13282             *obufp++ = 'w';
13283           break;
13284         case 'E':               /* For jcxz/jecxz */
13285           if (address_mode == mode_64bit)
13286             {
13287               if (sizeflag & AFLAG)
13288                 *obufp++ = 'r';
13289               else
13290                 *obufp++ = 'e';
13291             }
13292           else
13293             if (sizeflag & AFLAG)
13294               *obufp++ = 'e';
13295           used_prefixes |= (prefixes & PREFIX_ADDR);
13296           break;
13297         case 'F':
13298           if (intel_syntax)
13299             break;
13300           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
13301             {
13302               if (sizeflag & AFLAG)
13303                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
13304               else
13305                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
13306               used_prefixes |= (prefixes & PREFIX_ADDR);
13307             }
13308           break;
13309         case 'G':
13310           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
13311             break;
13312           if ((rex & REX_W) || (sizeflag & DFLAG))
13313             *obufp++ = 'l';
13314           else
13315             *obufp++ = 'w';
13316           if (!(rex & REX_W))
13317             used_prefixes |= (prefixes & PREFIX_DATA);
13318           break;
13319         case 'H':
13320           if (intel_syntax)
13321             break;
13322           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
13323               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
13324             {
13325               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
13326               *obufp++ = ',';
13327               *obufp++ = 'p';
13328               if (prefixes & PREFIX_DS)
13329                 *obufp++ = 't';
13330               else
13331                 *obufp++ = 'n';
13332             }
13333           break;
13334         case 'J':
13335           if (intel_syntax)
13336             break;
13337           *obufp++ = 'l';
13338           break;
13339         case 'K':
13340           USED_REX (REX_W);
13341           if (rex & REX_W)
13342             *obufp++ = 'q';
13343           else
13344             *obufp++ = 'd';
13345           break;
13346         case 'Z':
13347           if (intel_syntax)
13348             break;
13349           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
13350             {
13351               *obufp++ = 'q';
13352               break;
13353             }
13354           /* Fall through.  */
13355           goto case_L;
13356         case 'L':
13357           if (l != 0 || len != 1)
13358             {
13359               SAVE_LAST (*p);
13360               break;
13361             }
13362 case_L:
13363           if (intel_syntax)
13364             break;
13365           if (sizeflag & SUFFIX_ALWAYS)
13366             *obufp++ = 'l';
13367           break;
13368         case 'M':
13369           if (intel_mnemonic != cond)
13370             *obufp++ = 'r';
13371           break;
13372         case 'N':
13373           if ((prefixes & PREFIX_FWAIT) == 0)
13374             *obufp++ = 'n';
13375           else
13376             used_prefixes |= PREFIX_FWAIT;
13377           break;
13378         case 'O':
13379           USED_REX (REX_W);
13380           if (rex & REX_W)
13381             *obufp++ = 'o';
13382           else if (intel_syntax && (sizeflag & DFLAG))
13383             *obufp++ = 'q';
13384           else
13385             *obufp++ = 'd';
13386           if (!(rex & REX_W))
13387             used_prefixes |= (prefixes & PREFIX_DATA);
13388           break;
13389         case 'T':
13390           if (!intel_syntax
13391               && address_mode == mode_64bit
13392               && ((sizeflag & DFLAG) || (rex & REX_W)))
13393             {
13394               *obufp++ = 'q';
13395               break;
13396             }
13397           /* Fall through.  */
13398         case 'P':
13399           if (intel_syntax)
13400             {
13401               if ((rex & REX_W) == 0
13402                   && (prefixes & PREFIX_DATA))
13403                 {
13404                   if ((sizeflag & DFLAG) == 0)
13405                     *obufp++ = 'w';
13406                    used_prefixes |= (prefixes & PREFIX_DATA);
13407                 }
13408               break;
13409             }
13410           if ((prefixes & PREFIX_DATA)
13411               || (rex & REX_W)
13412               || (sizeflag & SUFFIX_ALWAYS))
13413             {
13414               USED_REX (REX_W);
13415               if (rex & REX_W)
13416                 *obufp++ = 'q';
13417               else
13418                 {
13419                    if (sizeflag & DFLAG)
13420                       *obufp++ = 'l';
13421                    else
13422                      *obufp++ = 'w';
13423                    used_prefixes |= (prefixes & PREFIX_DATA);
13424                 }
13425             }
13426           break;
13427         case 'U':
13428           if (intel_syntax)
13429             break;
13430           if (address_mode == mode_64bit
13431               && ((sizeflag & DFLAG) || (rex & REX_W)))
13432             {
13433               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13434                 *obufp++ = 'q';
13435               break;
13436             }
13437           /* Fall through.  */
13438           goto case_Q;
13439         case 'Q':
13440           if (l == 0 && len == 1)
13441             {
13442 case_Q:
13443               if (intel_syntax && !alt)
13444                 break;
13445               USED_REX (REX_W);
13446               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13447                 {
13448                   if (rex & REX_W)
13449                     *obufp++ = 'q';
13450                   else
13451                     {
13452                       if (sizeflag & DFLAG)
13453                         *obufp++ = intel_syntax ? 'd' : 'l';
13454                       else
13455                         *obufp++ = 'w';
13456                       used_prefixes |= (prefixes & PREFIX_DATA);
13457                     }
13458                 }
13459             }
13460           else
13461             {
13462               if (l != 1 || len != 2 || last[0] != 'L')
13463                 {
13464                   SAVE_LAST (*p);
13465                   break;
13466                 }
13467               if (intel_syntax
13468                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
13469                 break;
13470               if ((rex & REX_W))
13471                 {
13472                   USED_REX (REX_W);
13473                   *obufp++ = 'q';
13474                 }
13475               else
13476                 *obufp++ = 'l';
13477             }
13478           break;
13479         case 'R':
13480           USED_REX (REX_W);
13481           if (rex & REX_W)
13482             *obufp++ = 'q';
13483           else if (sizeflag & DFLAG)
13484             {
13485               if (intel_syntax)
13486                   *obufp++ = 'd';
13487               else
13488                   *obufp++ = 'l';
13489             }
13490           else
13491             *obufp++ = 'w';
13492           if (intel_syntax && !p[1]
13493               && ((rex & REX_W) || (sizeflag & DFLAG)))
13494             *obufp++ = 'e';
13495           if (!(rex & REX_W))
13496             used_prefixes |= (prefixes & PREFIX_DATA);
13497           break;
13498         case 'V':
13499           if (l == 0 && len == 1)
13500             {
13501               if (intel_syntax)
13502                 break;
13503               if (address_mode == mode_64bit
13504                   && ((sizeflag & DFLAG) || (rex & REX_W)))
13505                 {
13506                   if (sizeflag & SUFFIX_ALWAYS)
13507                     *obufp++ = 'q';
13508                   break;
13509                 }
13510             }
13511           else
13512             {
13513               if (l != 1
13514                   || len != 2
13515                   || last[0] != 'L')
13516                 {
13517                   SAVE_LAST (*p);
13518                   break;
13519                 }
13520
13521               if (rex & REX_W)
13522                 {
13523                   *obufp++ = 'a';
13524                   *obufp++ = 'b';
13525                   *obufp++ = 's';
13526                 }
13527             }
13528           /* Fall through.  */
13529           goto case_S;
13530         case 'S':
13531           if (l == 0 && len == 1)
13532             {
13533 case_S:
13534               if (intel_syntax)
13535                 break;
13536               if (sizeflag & SUFFIX_ALWAYS)
13537                 {
13538                   if (rex & REX_W)
13539                     *obufp++ = 'q';
13540                   else
13541                     {
13542                       if (sizeflag & DFLAG)
13543                         *obufp++ = 'l';
13544                       else
13545                         *obufp++ = 'w';
13546                       used_prefixes |= (prefixes & PREFIX_DATA);
13547                     }
13548                 }
13549             }
13550           else
13551             {
13552               if (l != 1
13553                   || len != 2
13554                   || last[0] != 'L')
13555                 {
13556                   SAVE_LAST (*p);
13557                   break;
13558                 }
13559
13560               if (address_mode == mode_64bit
13561                   && !(prefixes & PREFIX_ADDR))
13562                 {
13563                   *obufp++ = 'a';
13564                   *obufp++ = 'b';
13565                   *obufp++ = 's';
13566                 }
13567
13568               goto case_S;
13569             }
13570           break;
13571         case 'X':
13572           if (l != 0 || len != 1)
13573             {
13574               SAVE_LAST (*p);
13575               break;
13576             }
13577           if (need_vex && vex.prefix)
13578             {
13579               if (vex.prefix == DATA_PREFIX_OPCODE)
13580                 *obufp++ = 'd';
13581               else
13582                 *obufp++ = 's';
13583             }
13584           else
13585             {
13586               if (prefixes & PREFIX_DATA)
13587                 *obufp++ = 'd';
13588               else
13589                 *obufp++ = 's';
13590               used_prefixes |= (prefixes & PREFIX_DATA);
13591             }
13592           break;
13593         case 'Y':
13594           if (l == 0 && len == 1)
13595             {
13596               if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
13597                 break;
13598               if (rex & REX_W)
13599                 {
13600                   USED_REX (REX_W);
13601                   *obufp++ = 'q';
13602                 }
13603               break;
13604             }
13605           else
13606             {
13607               if (l != 1 || len != 2 || last[0] != 'X')
13608                 {
13609                   SAVE_LAST (*p);
13610                   break;
13611                 }
13612               if (!need_vex)
13613                 abort ();
13614               if (intel_syntax
13615                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
13616                 break;
13617               switch (vex.length)
13618                 {
13619                 case 128:
13620                   *obufp++ = 'x';
13621                   break;
13622                 case 256:
13623                   *obufp++ = 'y';
13624                   break;
13625                 default:
13626                   abort ();
13627                 }
13628             }
13629           break;
13630         case 'W':
13631           if (l == 0 && len == 1)
13632             {
13633               /* operand size flag for cwtl, cbtw */
13634               USED_REX (REX_W);
13635               if (rex & REX_W)
13636                 {
13637                   if (intel_syntax)
13638                     *obufp++ = 'd';
13639                   else
13640                     *obufp++ = 'l';
13641                 }
13642               else if (sizeflag & DFLAG)
13643                 *obufp++ = 'w';
13644               else
13645                 *obufp++ = 'b';
13646               if (!(rex & REX_W))
13647                 used_prefixes |= (prefixes & PREFIX_DATA);
13648             }
13649           else
13650             {
13651               if (l != 1
13652                   || len != 2
13653                   || (last[0] != 'X'
13654                       && last[0] != 'L'))
13655                 {
13656                   SAVE_LAST (*p);
13657                   break;
13658                 }
13659               if (!need_vex)
13660                 abort ();
13661               if (last[0] == 'X')
13662                 *obufp++ = vex.w ? 'd': 's';
13663               else
13664                 *obufp++ = vex.w ? 'q': 'd';
13665             }
13666           break;
13667         }
13668       alt = 0;
13669     }
13670   *obufp = 0;
13671   mnemonicendp = obufp;
13672   return 0;
13673 }
13674
13675 static void
13676 oappend (const char *s)
13677 {
13678   obufp = stpcpy (obufp, s);
13679 }
13680
13681 static void
13682 append_seg (void)
13683 {
13684   if (prefixes & PREFIX_CS)
13685     {
13686       used_prefixes |= PREFIX_CS;
13687       oappend_maybe_intel ("%cs:");
13688     }
13689   if (prefixes & PREFIX_DS)
13690     {
13691       used_prefixes |= PREFIX_DS;
13692       oappend_maybe_intel ("%ds:");
13693     }
13694   if (prefixes & PREFIX_SS)
13695     {
13696       used_prefixes |= PREFIX_SS;
13697       oappend_maybe_intel ("%ss:");
13698     }
13699   if (prefixes & PREFIX_ES)
13700     {
13701       used_prefixes |= PREFIX_ES;
13702       oappend_maybe_intel ("%es:");
13703     }
13704   if (prefixes & PREFIX_FS)
13705     {
13706       used_prefixes |= PREFIX_FS;
13707       oappend_maybe_intel ("%fs:");
13708     }
13709   if (prefixes & PREFIX_GS)
13710     {
13711       used_prefixes |= PREFIX_GS;
13712       oappend_maybe_intel ("%gs:");
13713     }
13714 }
13715
13716 static void
13717 OP_indirE (int bytemode, int sizeflag)
13718 {
13719   if (!intel_syntax)
13720     oappend ("*");
13721   OP_E (bytemode, sizeflag);
13722 }
13723
13724 static void
13725 print_operand_value (char *buf, int hex, bfd_vma disp)
13726 {
13727   if (address_mode == mode_64bit)
13728     {
13729       if (hex)
13730         {
13731           char tmp[30];
13732           int i;
13733           buf[0] = '0';
13734           buf[1] = 'x';
13735           sprintf_vma (tmp, disp);
13736           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
13737           strcpy (buf + 2, tmp + i);
13738         }
13739       else
13740         {
13741           bfd_signed_vma v = disp;
13742           char tmp[30];
13743           int i;
13744           if (v < 0)
13745             {
13746               *(buf++) = '-';
13747               v = -disp;
13748               /* Check for possible overflow on 0x8000000000000000.  */
13749               if (v < 0)
13750                 {
13751                   strcpy (buf, "9223372036854775808");
13752                   return;
13753                 }
13754             }
13755           if (!v)
13756             {
13757               strcpy (buf, "0");
13758               return;
13759             }
13760
13761           i = 0;
13762           tmp[29] = 0;
13763           while (v)
13764             {
13765               tmp[28 - i] = (v % 10) + '0';
13766               v /= 10;
13767               i++;
13768             }
13769           strcpy (buf, tmp + 29 - i);
13770         }
13771     }
13772   else
13773     {
13774       if (hex)
13775         sprintf (buf, "0x%x", (unsigned int) disp);
13776       else
13777         sprintf (buf, "%d", (int) disp);
13778     }
13779 }
13780
13781 /* Put DISP in BUF as signed hex number.  */
13782
13783 static void
13784 print_displacement (char *buf, bfd_vma disp)
13785 {
13786   bfd_signed_vma val = disp;
13787   char tmp[30];
13788   int i, j = 0;
13789
13790   if (val < 0)
13791     {
13792       buf[j++] = '-';
13793       val = -disp;
13794
13795       /* Check for possible overflow.  */
13796       if (val < 0)
13797         {
13798           switch (address_mode)
13799             {
13800             case mode_64bit:
13801               strcpy (buf + j, "0x8000000000000000");
13802               break;
13803             case mode_32bit:
13804               strcpy (buf + j, "0x80000000");
13805               break;
13806             case mode_16bit:
13807               strcpy (buf + j, "0x8000");
13808               break;
13809             }
13810           return;
13811         }
13812     }
13813
13814   buf[j++] = '0';
13815   buf[j++] = 'x';
13816
13817   sprintf_vma (tmp, (bfd_vma) val);
13818   for (i = 0; tmp[i] == '0'; i++)
13819     continue;
13820   if (tmp[i] == '\0')
13821     i--;
13822   strcpy (buf + j, tmp + i);
13823 }
13824
13825 static void
13826 intel_operand_size (int bytemode, int sizeflag)
13827 {
13828   if (vex.evex
13829       && vex.b
13830       && (bytemode == x_mode
13831           || bytemode == evex_half_bcst_xmmq_mode))
13832     {
13833       if (vex.w)
13834         oappend ("QWORD PTR ");
13835       else
13836         oappend ("DWORD PTR ");
13837       return;
13838     }
13839   switch (bytemode)
13840     {
13841     case b_mode:
13842     case b_swap_mode:
13843     case dqb_mode:
13844       oappend ("BYTE PTR ");
13845       break;
13846     case w_mode:
13847     case dqw_mode:
13848       oappend ("WORD PTR ");
13849       break;
13850     case stack_v_mode:
13851       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
13852         {
13853           oappend ("QWORD PTR ");
13854           break;
13855         }
13856       /* FALLTHRU */
13857     case v_mode:
13858     case v_swap_mode:
13859     case dq_mode:
13860       USED_REX (REX_W);
13861       if (rex & REX_W)
13862         oappend ("QWORD PTR ");
13863       else
13864         {
13865           if ((sizeflag & DFLAG) || bytemode == dq_mode)
13866             oappend ("DWORD PTR ");
13867           else
13868             oappend ("WORD PTR ");
13869           used_prefixes |= (prefixes & PREFIX_DATA);
13870         }
13871       break;
13872     case z_mode:
13873       if ((rex & REX_W) || (sizeflag & DFLAG))
13874         *obufp++ = 'D';
13875       oappend ("WORD PTR ");
13876       if (!(rex & REX_W))
13877         used_prefixes |= (prefixes & PREFIX_DATA);
13878       break;
13879     case a_mode:
13880       if (sizeflag & DFLAG)
13881         oappend ("QWORD PTR ");
13882       else
13883         oappend ("DWORD PTR ");
13884       used_prefixes |= (prefixes & PREFIX_DATA);
13885       break;
13886     case d_mode:
13887     case d_scalar_mode:
13888     case d_scalar_swap_mode:
13889     case d_swap_mode:
13890     case dqd_mode:
13891       oappend ("DWORD PTR ");
13892       break;
13893     case q_mode:
13894     case q_scalar_mode:
13895     case q_scalar_swap_mode:
13896     case q_swap_mode:
13897       oappend ("QWORD PTR ");
13898       break;
13899     case m_mode:
13900       if (address_mode == mode_64bit)
13901         oappend ("QWORD PTR ");
13902       else
13903         oappend ("DWORD PTR ");
13904       break;
13905     case f_mode:
13906       if (sizeflag & DFLAG)
13907         oappend ("FWORD PTR ");
13908       else
13909         oappend ("DWORD PTR ");
13910       used_prefixes |= (prefixes & PREFIX_DATA);
13911       break;
13912     case t_mode:
13913       oappend ("TBYTE PTR ");
13914       break;
13915     case x_mode:
13916     case x_swap_mode:
13917     case evex_x_gscat_mode:
13918     case evex_x_nobcst_mode:
13919       if (need_vex)
13920         {
13921           switch (vex.length)
13922             {
13923             case 128:
13924               oappend ("XMMWORD PTR ");
13925               break;
13926             case 256:
13927               oappend ("YMMWORD PTR ");
13928               break;
13929             case 512:
13930               oappend ("ZMMWORD PTR ");
13931               break;
13932             default:
13933               abort ();
13934             }
13935         }
13936       else
13937         oappend ("XMMWORD PTR ");
13938       break;
13939     case xmm_mode:
13940       oappend ("XMMWORD PTR ");
13941       break;
13942     case ymm_mode:
13943       oappend ("YMMWORD PTR ");
13944       break;
13945     case xmmq_mode:
13946     case evex_half_bcst_xmmq_mode:
13947       if (!need_vex)
13948         abort ();
13949
13950       switch (vex.length)
13951         {
13952         case 128:
13953           oappend ("QWORD PTR ");
13954           break;
13955         case 256:
13956           oappend ("XMMWORD PTR ");
13957           break;
13958         case 512:
13959           oappend ("YMMWORD PTR ");
13960           break;
13961         default:
13962           abort ();
13963         }
13964       break;
13965     case xmm_mb_mode:
13966       if (!need_vex)
13967         abort ();
13968
13969       switch (vex.length)
13970         {
13971         case 128:
13972         case 256:
13973         case 512:
13974           oappend ("BYTE PTR ");
13975           break;
13976         default:
13977           abort ();
13978         }
13979       break;
13980     case xmm_mw_mode:
13981       if (!need_vex)
13982         abort ();
13983
13984       switch (vex.length)
13985         {
13986         case 128:
13987         case 256:
13988         case 512:
13989           oappend ("WORD PTR ");
13990           break;
13991         default:
13992           abort ();
13993         }
13994       break;
13995     case xmm_md_mode:
13996       if (!need_vex)
13997         abort ();
13998
13999       switch (vex.length)
14000         {
14001         case 128:
14002         case 256:
14003         case 512:
14004           oappend ("DWORD PTR ");
14005           break;
14006         default:
14007           abort ();
14008         }
14009       break;
14010     case xmm_mq_mode:
14011       if (!need_vex)
14012         abort ();
14013
14014       switch (vex.length)
14015         {
14016         case 128:
14017         case 256:
14018         case 512:
14019           oappend ("QWORD PTR ");
14020           break;
14021         default:
14022           abort ();
14023         }
14024       break;
14025     case xmmdw_mode:
14026       if (!need_vex)
14027         abort ();
14028
14029       switch (vex.length)
14030         {
14031         case 128:
14032           oappend ("WORD PTR ");
14033           break;
14034         case 256:
14035           oappend ("DWORD PTR ");
14036           break;
14037         case 512:
14038           oappend ("QWORD PTR ");
14039           break;
14040         default:
14041           abort ();
14042         }
14043       break;
14044     case xmmqd_mode:
14045       if (!need_vex)
14046         abort ();
14047
14048       switch (vex.length)
14049         {
14050         case 128:
14051           oappend ("DWORD PTR ");
14052           break;
14053         case 256:
14054           oappend ("QWORD PTR ");
14055           break;
14056         case 512:
14057           oappend ("XMMWORD PTR ");
14058           break;
14059         default:
14060           abort ();
14061         }
14062       break;
14063     case ymmq_mode:
14064       if (!need_vex)
14065         abort ();
14066
14067       switch (vex.length)
14068         {
14069         case 128:
14070           oappend ("QWORD PTR ");
14071           break;
14072         case 256:
14073           oappend ("YMMWORD PTR ");
14074           break;
14075         case 512:
14076           oappend ("ZMMWORD PTR ");
14077           break;
14078         default:
14079           abort ();
14080         }
14081       break;
14082     case ymmxmm_mode:
14083       if (!need_vex)
14084         abort ();
14085
14086       switch (vex.length)
14087         {
14088         case 128:
14089         case 256:
14090           oappend ("XMMWORD PTR ");
14091           break;
14092         default:
14093           abort ();
14094         }
14095       break;
14096     case o_mode:
14097       oappend ("OWORD PTR ");
14098       break;
14099     case xmm_mdq_mode:
14100     case vex_w_dq_mode:
14101     case vex_scalar_w_dq_mode:
14102       if (!need_vex)
14103         abort ();
14104
14105       if (vex.w)
14106         oappend ("QWORD PTR ");
14107       else
14108         oappend ("DWORD PTR ");
14109       break;
14110     case vex_vsib_d_w_dq_mode:
14111     case vex_vsib_q_w_dq_mode:
14112       if (!need_vex)
14113         abort ();
14114
14115       if (!vex.evex)
14116         {
14117           if (vex.w)
14118             oappend ("QWORD PTR ");
14119           else
14120             oappend ("DWORD PTR ");
14121         }
14122       else
14123         {
14124           if (vex.length != 512)
14125             abort ();
14126           oappend ("ZMMWORD PTR ");
14127         }
14128       break;
14129     case vex_vsib_q_w_d_mode:
14130     case vex_vsib_d_w_d_mode:
14131       if (!need_vex || !vex.evex || vex.length != 512)
14132         abort ();
14133
14134       oappend ("YMMWORD PTR ");
14135
14136       break;
14137     case mask_mode:
14138       if (!need_vex)
14139         abort ();
14140       /* Currently the only instructions, which allows either mask or
14141          memory operand, are AVX512's KMOVW instructions.  They need
14142          Word-sized operand.  */
14143       if (vex.w || vex.length != 128)
14144         abort ();
14145       oappend ("WORD PTR ");
14146       break;
14147     case v_bnd_mode:
14148     default:
14149       break;
14150     }
14151 }
14152
14153 static void
14154 OP_E_register (int bytemode, int sizeflag)
14155 {
14156   int reg = modrm.rm;
14157   const char **names;
14158
14159   USED_REX (REX_B);
14160   if ((rex & REX_B))
14161     reg += 8;
14162
14163   if ((sizeflag & SUFFIX_ALWAYS)
14164       && (bytemode == b_swap_mode || bytemode == v_swap_mode))
14165     swap_operand ();
14166
14167   switch (bytemode)
14168     {
14169     case b_mode:
14170     case b_swap_mode:
14171       USED_REX (0);
14172       if (rex)
14173         names = names8rex;
14174       else
14175         names = names8;
14176       break;
14177     case w_mode:
14178       names = names16;
14179       break;
14180     case d_mode:
14181       names = names32;
14182       break;
14183     case q_mode:
14184       names = names64;
14185       break;
14186     case m_mode:
14187     case v_bnd_mode:
14188       names = address_mode == mode_64bit ? names64 : names32;
14189       break;
14190     case bnd_mode:
14191       names = names_bnd;
14192       break;
14193     case stack_v_mode:
14194       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14195         {
14196           names = names64;
14197           break;
14198         }
14199       bytemode = v_mode;
14200       /* FALLTHRU */
14201     case v_mode:
14202     case v_swap_mode:
14203     case dq_mode:
14204     case dqb_mode:
14205     case dqd_mode:
14206     case dqw_mode:
14207       USED_REX (REX_W);
14208       if (rex & REX_W)
14209         names = names64;
14210       else
14211         {
14212           if ((sizeflag & DFLAG)
14213               || (bytemode != v_mode
14214                   && bytemode != v_swap_mode))
14215             names = names32;
14216           else
14217             names = names16;
14218           used_prefixes |= (prefixes & PREFIX_DATA);
14219         }
14220       break;
14221     case mask_mode:
14222       names = names_mask;
14223       break;
14224     case 0:
14225       return;
14226     default:
14227       oappend (INTERNAL_DISASSEMBLER_ERROR);
14228       return;
14229     }
14230   oappend (names[reg]);
14231 }
14232
14233 static void
14234 OP_E_memory (int bytemode, int sizeflag)
14235 {
14236   bfd_vma disp = 0;
14237   int add = (rex & REX_B) ? 8 : 0;
14238   int riprel = 0;
14239   int shift;
14240
14241   if (vex.evex)
14242     {
14243       /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0.  */
14244       if (vex.b
14245           && bytemode != x_mode
14246           && bytemode != evex_half_bcst_xmmq_mode)
14247         {
14248           BadOp ();
14249           return;
14250         }
14251       switch (bytemode)
14252         {
14253         case vex_vsib_d_w_dq_mode:
14254         case vex_vsib_d_w_d_mode:
14255         case vex_vsib_q_w_dq_mode:
14256         case vex_vsib_q_w_d_mode:
14257         case evex_x_gscat_mode:
14258         case xmm_mdq_mode:
14259           shift = vex.w ? 3 : 2;
14260           break;
14261         case x_mode:
14262         case evex_half_bcst_xmmq_mode:
14263           if (vex.b)
14264             {
14265               shift = vex.w ? 3 : 2;
14266               break;
14267             }
14268           /* Fall through if vex.b == 0.  */
14269         case xmmqd_mode:
14270         case xmmdw_mode:
14271         case xmmq_mode:
14272         case ymmq_mode:
14273         case evex_x_nobcst_mode:
14274         case x_swap_mode:
14275           switch (vex.length)
14276             {
14277             case 128:
14278               shift = 4;
14279               break;
14280             case 256:
14281               shift = 5;
14282               break;
14283             case 512:
14284               shift = 6;
14285               break;
14286             default:
14287               abort ();
14288             }
14289           break;
14290         case ymm_mode:
14291           shift = 5;
14292           break;
14293         case xmm_mode:
14294           shift = 4;
14295           break;
14296         case xmm_mq_mode:
14297         case q_mode:
14298         case q_scalar_mode:
14299         case q_swap_mode:
14300         case q_scalar_swap_mode:
14301           shift = 3;
14302           break;
14303         case dqd_mode:
14304         case xmm_md_mode:
14305         case d_mode:
14306         case d_scalar_mode:
14307         case d_swap_mode:
14308         case d_scalar_swap_mode:
14309           shift = 2;
14310           break;
14311         case xmm_mw_mode:
14312           shift = 1;
14313           break;
14314         case xmm_mb_mode:
14315           shift = 0;
14316           break;
14317         default:
14318           abort ();
14319         }
14320       /* Make necessary corrections to shift for modes that need it.
14321          For these modes we currently have shift 4, 5 or 6 depending on
14322          vex.length (it corresponds to xmmword, ymmword or zmmword
14323          operand).  We might want to make it 3, 4 or 5 (e.g. for
14324          xmmq_mode).  In case of broadcast enabled the corrections
14325          aren't needed, as element size is always 32 or 64 bits.  */
14326       if (bytemode == xmmq_mode
14327           || (bytemode == evex_half_bcst_xmmq_mode
14328               && !vex.b))
14329         shift -= 1;
14330       else if (bytemode == xmmqd_mode)
14331         shift -= 2;
14332       else if (bytemode == xmmdw_mode)
14333         shift -= 3;
14334     }
14335   else
14336     shift = 0;
14337
14338   USED_REX (REX_B);
14339   if (intel_syntax)
14340     intel_operand_size (bytemode, sizeflag);
14341   append_seg ();
14342
14343   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14344     {
14345       /* 32/64 bit address mode */
14346       int havedisp;
14347       int havesib;
14348       int havebase;
14349       int haveindex;
14350       int needindex;
14351       int base, rbase;
14352       int vindex = 0;
14353       int scale = 0;
14354       int addr32flag = !((sizeflag & AFLAG)
14355                          || bytemode == v_bnd_mode
14356                          || bytemode == bnd_mode);
14357       const char **indexes64 = names64;
14358       const char **indexes32 = names32;
14359
14360       havesib = 0;
14361       havebase = 1;
14362       haveindex = 0;
14363       base = modrm.rm;
14364
14365       if (base == 4)
14366         {
14367           havesib = 1;
14368           vindex = sib.index;
14369           USED_REX (REX_X);
14370           if (rex & REX_X)
14371             vindex += 8;
14372           switch (bytemode)
14373             {
14374             case vex_vsib_d_w_dq_mode:
14375             case vex_vsib_d_w_d_mode:
14376             case vex_vsib_q_w_dq_mode:
14377             case vex_vsib_q_w_d_mode:
14378               if (!need_vex)
14379                 abort ();
14380               if (vex.evex)
14381                 {
14382                   if (!vex.v)
14383                     vindex += 16;
14384                 }
14385
14386               haveindex = 1;
14387               switch (vex.length)
14388                 {
14389                 case 128:
14390                   indexes64 = indexes32 = names_xmm;
14391                   break;
14392                 case 256:
14393                   if (!vex.w
14394                       || bytemode == vex_vsib_q_w_dq_mode
14395                       || bytemode == vex_vsib_q_w_d_mode)
14396                     indexes64 = indexes32 = names_ymm;
14397                   else
14398                     indexes64 = indexes32 = names_xmm;
14399                   break;
14400                 case 512:
14401                   if (!vex.w
14402                       || bytemode == vex_vsib_q_w_dq_mode
14403                       || bytemode == vex_vsib_q_w_d_mode)
14404                     indexes64 = indexes32 = names_zmm;
14405                   else
14406                     indexes64 = indexes32 = names_ymm;
14407                   break;
14408                 default:
14409                   abort ();
14410                 }
14411               break;
14412             default:
14413               haveindex = vindex != 4;
14414               break;
14415             }
14416           scale = sib.scale;
14417           base = sib.base;
14418           codep++;
14419         }
14420       rbase = base + add;
14421
14422       switch (modrm.mod)
14423         {
14424         case 0:
14425           if (base == 5)
14426             {
14427               havebase = 0;
14428               if (address_mode == mode_64bit && !havesib)
14429                 riprel = 1;
14430               disp = get32s ();
14431             }
14432           break;
14433         case 1:
14434           FETCH_DATA (the_info, codep + 1);
14435           disp = *codep++;
14436           if ((disp & 0x80) != 0)
14437             disp -= 0x100;
14438           if (vex.evex && shift > 0)
14439             disp <<= shift;
14440           break;
14441         case 2:
14442           disp = get32s ();
14443           break;
14444         }
14445
14446       /* In 32bit mode, we need index register to tell [offset] from
14447          [eiz*1 + offset].  */
14448       needindex = (havesib
14449                    && !havebase
14450                    && !haveindex
14451                    && address_mode == mode_32bit);
14452       havedisp = (havebase
14453                   || needindex
14454                   || (havesib && (haveindex || scale != 0)));
14455
14456       if (!intel_syntax)
14457         if (modrm.mod != 0 || base == 5)
14458           {
14459             if (havedisp || riprel)
14460               print_displacement (scratchbuf, disp);
14461             else
14462               print_operand_value (scratchbuf, 1, disp);
14463             oappend (scratchbuf);
14464             if (riprel)
14465               {
14466                 set_op (disp, 1);
14467                 oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)");
14468               }
14469           }
14470
14471       if ((havebase || haveindex || riprel)
14472           && (bytemode != v_bnd_mode)
14473           && (bytemode != bnd_mode))
14474         used_prefixes |= PREFIX_ADDR;
14475
14476       if (havedisp || (intel_syntax && riprel))
14477         {
14478           *obufp++ = open_char;
14479           if (intel_syntax && riprel)
14480             {
14481               set_op (disp, 1);
14482               oappend (sizeflag & AFLAG ? "rip" : "eip");
14483             }
14484           *obufp = '\0';
14485           if (havebase)
14486             oappend (address_mode == mode_64bit && !addr32flag
14487                      ? names64[rbase] : names32[rbase]);
14488           if (havesib)
14489             {
14490               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
14491                  print index to tell base + index from base.  */
14492               if (scale != 0
14493                   || needindex
14494                   || haveindex
14495                   || (havebase && base != ESP_REG_NUM))
14496                 {
14497                   if (!intel_syntax || havebase)
14498                     {
14499                       *obufp++ = separator_char;
14500                       *obufp = '\0';
14501                     }
14502                   if (haveindex)
14503                     oappend (address_mode == mode_64bit && !addr32flag
14504                              ? indexes64[vindex] : indexes32[vindex]);
14505                   else
14506                     oappend (address_mode == mode_64bit && !addr32flag
14507                              ? index64 : index32);
14508
14509                   *obufp++ = scale_char;
14510                   *obufp = '\0';
14511                   sprintf (scratchbuf, "%d", 1 << scale);
14512                   oappend (scratchbuf);
14513                 }
14514             }
14515           if (intel_syntax
14516               && (disp || modrm.mod != 0 || base == 5))
14517             {
14518               if (!havedisp || (bfd_signed_vma) disp >= 0)
14519                 {
14520                   *obufp++ = '+';
14521                   *obufp = '\0';
14522                 }
14523               else if (modrm.mod != 1 && disp != -disp)
14524                 {
14525                   *obufp++ = '-';
14526                   *obufp = '\0';
14527                   disp = - (bfd_signed_vma) disp;
14528                 }
14529
14530               if (havedisp)
14531                 print_displacement (scratchbuf, disp);
14532               else
14533                 print_operand_value (scratchbuf, 1, disp);
14534               oappend (scratchbuf);
14535             }
14536
14537           *obufp++ = close_char;
14538           *obufp = '\0';
14539         }
14540       else if (intel_syntax)
14541         {
14542           if (modrm.mod != 0 || base == 5)
14543             {
14544               if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
14545                               | PREFIX_ES | PREFIX_FS | PREFIX_GS))
14546                 ;
14547               else
14548                 {
14549                   oappend (names_seg[ds_reg - es_reg]);
14550                   oappend (":");
14551                 }
14552               print_operand_value (scratchbuf, 1, disp);
14553               oappend (scratchbuf);
14554             }
14555         }
14556     }
14557   else
14558     {
14559       /* 16 bit address mode */
14560       used_prefixes |= prefixes & PREFIX_ADDR;
14561       switch (modrm.mod)
14562         {
14563         case 0:
14564           if (modrm.rm == 6)
14565             {
14566               disp = get16 ();
14567               if ((disp & 0x8000) != 0)
14568                 disp -= 0x10000;
14569             }
14570           break;
14571         case 1:
14572           FETCH_DATA (the_info, codep + 1);
14573           disp = *codep++;
14574           if ((disp & 0x80) != 0)
14575             disp -= 0x100;
14576           break;
14577         case 2:
14578           disp = get16 ();
14579           if ((disp & 0x8000) != 0)
14580             disp -= 0x10000;
14581           break;
14582         }
14583
14584       if (!intel_syntax)
14585         if (modrm.mod != 0 || modrm.rm == 6)
14586           {
14587             print_displacement (scratchbuf, disp);
14588             oappend (scratchbuf);
14589           }
14590
14591       if (modrm.mod != 0 || modrm.rm != 6)
14592         {
14593           *obufp++ = open_char;
14594           *obufp = '\0';
14595           oappend (index16[modrm.rm]);
14596           if (intel_syntax
14597               && (disp || modrm.mod != 0 || modrm.rm == 6))
14598             {
14599               if ((bfd_signed_vma) disp >= 0)
14600                 {
14601                   *obufp++ = '+';
14602                   *obufp = '\0';
14603                 }
14604               else if (modrm.mod != 1)
14605                 {
14606                   *obufp++ = '-';
14607                   *obufp = '\0';
14608                   disp = - (bfd_signed_vma) disp;
14609                 }
14610
14611               print_displacement (scratchbuf, disp);
14612               oappend (scratchbuf);
14613             }
14614
14615           *obufp++ = close_char;
14616           *obufp = '\0';
14617         }
14618       else if (intel_syntax)
14619         {
14620           if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
14621                           | PREFIX_ES | PREFIX_FS | PREFIX_GS))
14622             ;
14623           else
14624             {
14625               oappend (names_seg[ds_reg - es_reg]);
14626               oappend (":");
14627             }
14628           print_operand_value (scratchbuf, 1, disp & 0xffff);
14629           oappend (scratchbuf);
14630         }
14631     }
14632   if (vex.evex && vex.b
14633       && (bytemode == x_mode
14634           || bytemode == evex_half_bcst_xmmq_mode))
14635     {
14636       if (vex.w || bytemode == evex_half_bcst_xmmq_mode)
14637         oappend ("{1to8}");
14638       else
14639         oappend ("{1to16}");
14640     }
14641 }
14642
14643 static void
14644 OP_E (int bytemode, int sizeflag)
14645 {
14646   /* Skip mod/rm byte.  */
14647   MODRM_CHECK;
14648   codep++;
14649
14650   if (modrm.mod == 3)
14651     OP_E_register (bytemode, sizeflag);
14652   else
14653     OP_E_memory (bytemode, sizeflag);
14654 }
14655
14656 static void
14657 OP_G (int bytemode, int sizeflag)
14658 {
14659   int add = 0;
14660   USED_REX (REX_R);
14661   if (rex & REX_R)
14662     add += 8;
14663   switch (bytemode)
14664     {
14665     case b_mode:
14666       USED_REX (0);
14667       if (rex)
14668         oappend (names8rex[modrm.reg + add]);
14669       else
14670         oappend (names8[modrm.reg + add]);
14671       break;
14672     case w_mode:
14673       oappend (names16[modrm.reg + add]);
14674       break;
14675     case d_mode:
14676       oappend (names32[modrm.reg + add]);
14677       break;
14678     case q_mode:
14679       oappend (names64[modrm.reg + add]);
14680       break;
14681     case bnd_mode:
14682       oappend (names_bnd[modrm.reg]);
14683       break;
14684     case v_mode:
14685     case dq_mode:
14686     case dqb_mode:
14687     case dqd_mode:
14688     case dqw_mode:
14689       USED_REX (REX_W);
14690       if (rex & REX_W)
14691         oappend (names64[modrm.reg + add]);
14692       else
14693         {
14694           if ((sizeflag & DFLAG) || bytemode != v_mode)
14695             oappend (names32[modrm.reg + add]);
14696           else
14697             oappend (names16[modrm.reg + add]);
14698           used_prefixes |= (prefixes & PREFIX_DATA);
14699         }
14700       break;
14701     case m_mode:
14702       if (address_mode == mode_64bit)
14703         oappend (names64[modrm.reg + add]);
14704       else
14705         oappend (names32[modrm.reg + add]);
14706       break;
14707     case mask_mode:
14708       oappend (names_mask[modrm.reg + add]);
14709       break;
14710     default:
14711       oappend (INTERNAL_DISASSEMBLER_ERROR);
14712       break;
14713     }
14714 }
14715
14716 static bfd_vma
14717 get64 (void)
14718 {
14719   bfd_vma x;
14720 #ifdef BFD64
14721   unsigned int a;
14722   unsigned int b;
14723
14724   FETCH_DATA (the_info, codep + 8);
14725   a = *codep++ & 0xff;
14726   a |= (*codep++ & 0xff) << 8;
14727   a |= (*codep++ & 0xff) << 16;
14728   a |= (*codep++ & 0xff) << 24;
14729   b = *codep++ & 0xff;
14730   b |= (*codep++ & 0xff) << 8;
14731   b |= (*codep++ & 0xff) << 16;
14732   b |= (*codep++ & 0xff) << 24;
14733   x = a + ((bfd_vma) b << 32);
14734 #else
14735   abort ();
14736   x = 0;
14737 #endif
14738   return x;
14739 }
14740
14741 static bfd_signed_vma
14742 get32 (void)
14743 {
14744   bfd_signed_vma x = 0;
14745
14746   FETCH_DATA (the_info, codep + 4);
14747   x = *codep++ & (bfd_signed_vma) 0xff;
14748   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14749   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14750   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14751   return x;
14752 }
14753
14754 static bfd_signed_vma
14755 get32s (void)
14756 {
14757   bfd_signed_vma x = 0;
14758
14759   FETCH_DATA (the_info, codep + 4);
14760   x = *codep++ & (bfd_signed_vma) 0xff;
14761   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14762   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14763   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14764
14765   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
14766
14767   return x;
14768 }
14769
14770 static int
14771 get16 (void)
14772 {
14773   int x = 0;
14774
14775   FETCH_DATA (the_info, codep + 2);
14776   x = *codep++ & 0xff;
14777   x |= (*codep++ & 0xff) << 8;
14778   return x;
14779 }
14780
14781 static void
14782 set_op (bfd_vma op, int riprel)
14783 {
14784   op_index[op_ad] = op_ad;
14785   if (address_mode == mode_64bit)
14786     {
14787       op_address[op_ad] = op;
14788       op_riprel[op_ad] = riprel;
14789     }
14790   else
14791     {
14792       /* Mask to get a 32-bit address.  */
14793       op_address[op_ad] = op & 0xffffffff;
14794       op_riprel[op_ad] = riprel & 0xffffffff;
14795     }
14796 }
14797
14798 static void
14799 OP_REG (int code, int sizeflag)
14800 {
14801   const char *s;
14802   int add;
14803
14804   switch (code)
14805     {
14806     case es_reg: case ss_reg: case cs_reg:
14807     case ds_reg: case fs_reg: case gs_reg:
14808       oappend (names_seg[code - es_reg]);
14809       return;
14810     }
14811
14812   USED_REX (REX_B);
14813   if (rex & REX_B)
14814     add = 8;
14815   else
14816     add = 0;
14817
14818   switch (code)
14819     {
14820     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14821     case sp_reg: case bp_reg: case si_reg: case di_reg:
14822       s = names16[code - ax_reg + add];
14823       break;
14824     case al_reg: case ah_reg: case cl_reg: case ch_reg:
14825     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14826       USED_REX (0);
14827       if (rex)
14828         s = names8rex[code - al_reg + add];
14829       else
14830         s = names8[code - al_reg];
14831       break;
14832     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
14833     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
14834       if (address_mode == mode_64bit
14835           && ((sizeflag & DFLAG) || (rex & REX_W)))
14836         {
14837           s = names64[code - rAX_reg + add];
14838           break;
14839         }
14840       code += eAX_reg - rAX_reg;
14841       /* Fall through.  */
14842     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14843     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14844       USED_REX (REX_W);
14845       if (rex & REX_W)
14846         s = names64[code - eAX_reg + add];
14847       else
14848         {
14849           if (sizeflag & DFLAG)
14850             s = names32[code - eAX_reg + add];
14851           else
14852             s = names16[code - eAX_reg + add];
14853           used_prefixes |= (prefixes & PREFIX_DATA);
14854         }
14855       break;
14856     default:
14857       s = INTERNAL_DISASSEMBLER_ERROR;
14858       break;
14859     }
14860   oappend (s);
14861 }
14862
14863 static void
14864 OP_IMREG (int code, int sizeflag)
14865 {
14866   const char *s;
14867
14868   switch (code)
14869     {
14870     case indir_dx_reg:
14871       if (intel_syntax)
14872         s = "dx";
14873       else
14874         s = "(%dx)";
14875       break;
14876     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14877     case sp_reg: case bp_reg: case si_reg: case di_reg:
14878       s = names16[code - ax_reg];
14879       break;
14880     case es_reg: case ss_reg: case cs_reg:
14881     case ds_reg: case fs_reg: case gs_reg:
14882       s = names_seg[code - es_reg];
14883       break;
14884     case al_reg: case ah_reg: case cl_reg: case ch_reg:
14885     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14886       USED_REX (0);
14887       if (rex)
14888         s = names8rex[code - al_reg];
14889       else
14890         s = names8[code - al_reg];
14891       break;
14892     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14893     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14894       USED_REX (REX_W);
14895       if (rex & REX_W)
14896         s = names64[code - eAX_reg];
14897       else
14898         {
14899           if (sizeflag & DFLAG)
14900             s = names32[code - eAX_reg];
14901           else
14902             s = names16[code - eAX_reg];
14903           used_prefixes |= (prefixes & PREFIX_DATA);
14904         }
14905       break;
14906     case z_mode_ax_reg:
14907       if ((rex & REX_W) || (sizeflag & DFLAG))
14908         s = *names32;
14909       else
14910         s = *names16;
14911       if (!(rex & REX_W))
14912         used_prefixes |= (prefixes & PREFIX_DATA);
14913       break;
14914     default:
14915       s = INTERNAL_DISASSEMBLER_ERROR;
14916       break;
14917     }
14918   oappend (s);
14919 }
14920
14921 static void
14922 OP_I (int bytemode, int sizeflag)
14923 {
14924   bfd_signed_vma op;
14925   bfd_signed_vma mask = -1;
14926
14927   switch (bytemode)
14928     {
14929     case b_mode:
14930       FETCH_DATA (the_info, codep + 1);
14931       op = *codep++;
14932       mask = 0xff;
14933       break;
14934     case q_mode:
14935       if (address_mode == mode_64bit)
14936         {
14937           op = get32s ();
14938           break;
14939         }
14940       /* Fall through.  */
14941     case v_mode:
14942       USED_REX (REX_W);
14943       if (rex & REX_W)
14944         op = get32s ();
14945       else
14946         {
14947           if (sizeflag & DFLAG)
14948             {
14949               op = get32 ();
14950               mask = 0xffffffff;
14951             }
14952           else
14953             {
14954               op = get16 ();
14955               mask = 0xfffff;
14956             }
14957           used_prefixes |= (prefixes & PREFIX_DATA);
14958         }
14959       break;
14960     case w_mode:
14961       mask = 0xfffff;
14962       op = get16 ();
14963       break;
14964     case const_1_mode:
14965       if (intel_syntax)
14966         oappend ("1");
14967       return;
14968     default:
14969       oappend (INTERNAL_DISASSEMBLER_ERROR);
14970       return;
14971     }
14972
14973   op &= mask;
14974   scratchbuf[0] = '$';
14975   print_operand_value (scratchbuf + 1, 1, op);
14976   oappend_maybe_intel (scratchbuf);
14977   scratchbuf[0] = '\0';
14978 }
14979
14980 static void
14981 OP_I64 (int bytemode, int sizeflag)
14982 {
14983   bfd_signed_vma op;
14984   bfd_signed_vma mask = -1;
14985
14986   if (address_mode != mode_64bit)
14987     {
14988       OP_I (bytemode, sizeflag);
14989       return;
14990     }
14991
14992   switch (bytemode)
14993     {
14994     case b_mode:
14995       FETCH_DATA (the_info, codep + 1);
14996       op = *codep++;
14997       mask = 0xff;
14998       break;
14999     case v_mode:
15000       USED_REX (REX_W);
15001       if (rex & REX_W)
15002         op = get64 ();
15003       else
15004         {
15005           if (sizeflag & DFLAG)
15006             {
15007               op = get32 ();
15008               mask = 0xffffffff;
15009             }
15010           else
15011             {
15012               op = get16 ();
15013               mask = 0xfffff;
15014             }
15015           used_prefixes |= (prefixes & PREFIX_DATA);
15016         }
15017       break;
15018     case w_mode:
15019       mask = 0xfffff;
15020       op = get16 ();
15021       break;
15022     default:
15023       oappend (INTERNAL_DISASSEMBLER_ERROR);
15024       return;
15025     }
15026
15027   op &= mask;
15028   scratchbuf[0] = '$';
15029   print_operand_value (scratchbuf + 1, 1, op);
15030   oappend_maybe_intel (scratchbuf);
15031   scratchbuf[0] = '\0';
15032 }
15033
15034 static void
15035 OP_sI (int bytemode, int sizeflag)
15036 {
15037   bfd_signed_vma op;
15038
15039   switch (bytemode)
15040     {
15041     case b_mode:
15042     case b_T_mode:
15043       FETCH_DATA (the_info, codep + 1);
15044       op = *codep++;
15045       if ((op & 0x80) != 0)
15046         op -= 0x100;
15047       if (bytemode == b_T_mode)
15048         {
15049           if (address_mode != mode_64bit
15050               || !((sizeflag & DFLAG) || (rex & REX_W)))
15051             {
15052               /* The operand-size prefix is overridden by a REX prefix.  */
15053               if ((sizeflag & DFLAG) || (rex & REX_W))
15054                 op &= 0xffffffff;
15055               else
15056                 op &= 0xffff;
15057           }
15058         }
15059       else
15060         {
15061           if (!(rex & REX_W))
15062             {
15063               if (sizeflag & DFLAG)
15064                 op &= 0xffffffff;
15065               else
15066                 op &= 0xffff;
15067             }
15068         }
15069       break;
15070     case v_mode:
15071       /* The operand-size prefix is overridden by a REX prefix.  */
15072       if ((sizeflag & DFLAG) || (rex & REX_W))
15073         op = get32s ();
15074       else
15075         op = get16 ();
15076       break;
15077     default:
15078       oappend (INTERNAL_DISASSEMBLER_ERROR);
15079       return;
15080     }
15081
15082   scratchbuf[0] = '$';
15083   print_operand_value (scratchbuf + 1, 1, op);
15084   oappend_maybe_intel (scratchbuf);
15085 }
15086
15087 static void
15088 OP_J (int bytemode, int sizeflag)
15089 {
15090   bfd_vma disp;
15091   bfd_vma mask = -1;
15092   bfd_vma segment = 0;
15093
15094   switch (bytemode)
15095     {
15096     case b_mode:
15097       FETCH_DATA (the_info, codep + 1);
15098       disp = *codep++;
15099       if ((disp & 0x80) != 0)
15100         disp -= 0x100;
15101       break;
15102     case v_mode:
15103       USED_REX (REX_W);
15104       if ((sizeflag & DFLAG) || (rex & REX_W))
15105         disp = get32s ();
15106       else
15107         {
15108           disp = get16 ();
15109           if ((disp & 0x8000) != 0)
15110             disp -= 0x10000;
15111           /* In 16bit mode, address is wrapped around at 64k within
15112              the same segment.  Otherwise, a data16 prefix on a jump
15113              instruction means that the pc is masked to 16 bits after
15114              the displacement is added!  */
15115           mask = 0xffff;
15116           if ((prefixes & PREFIX_DATA) == 0)
15117             segment = ((start_pc + codep - start_codep)
15118                        & ~((bfd_vma) 0xffff));
15119         }
15120       if (!(rex & REX_W))
15121         used_prefixes |= (prefixes & PREFIX_DATA);
15122       break;
15123     default:
15124       oappend (INTERNAL_DISASSEMBLER_ERROR);
15125       return;
15126     }
15127   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
15128   set_op (disp, 0);
15129   print_operand_value (scratchbuf, 1, disp);
15130   oappend (scratchbuf);
15131 }
15132
15133 static void
15134 OP_SEG (int bytemode, int sizeflag)
15135 {
15136   if (bytemode == w_mode)
15137     oappend (names_seg[modrm.reg]);
15138   else
15139     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
15140 }
15141
15142 static void
15143 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
15144 {
15145   int seg, offset;
15146
15147   if (sizeflag & DFLAG)
15148     {
15149       offset = get32 ();
15150       seg = get16 ();
15151     }
15152   else
15153     {
15154       offset = get16 ();
15155       seg = get16 ();
15156     }
15157   used_prefixes |= (prefixes & PREFIX_DATA);
15158   if (intel_syntax)
15159     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
15160   else
15161     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
15162   oappend (scratchbuf);
15163 }
15164
15165 static void
15166 OP_OFF (int bytemode, int sizeflag)
15167 {
15168   bfd_vma off;
15169
15170   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
15171     intel_operand_size (bytemode, sizeflag);
15172   append_seg ();
15173
15174   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
15175     off = get32 ();
15176   else
15177     off = get16 ();
15178
15179   if (intel_syntax)
15180     {
15181       if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
15182                         | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
15183         {
15184           oappend (names_seg[ds_reg - es_reg]);
15185           oappend (":");
15186         }
15187     }
15188   print_operand_value (scratchbuf, 1, off);
15189   oappend (scratchbuf);
15190 }
15191
15192 static void
15193 OP_OFF64 (int bytemode, int sizeflag)
15194 {
15195   bfd_vma off;
15196
15197   if (address_mode != mode_64bit
15198       || (prefixes & PREFIX_ADDR))
15199     {
15200       OP_OFF (bytemode, sizeflag);
15201       return;
15202     }
15203
15204   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
15205     intel_operand_size (bytemode, sizeflag);
15206   append_seg ();
15207
15208   off = get64 ();
15209
15210   if (intel_syntax)
15211     {
15212       if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
15213                         | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
15214         {
15215           oappend (names_seg[ds_reg - es_reg]);
15216           oappend (":");
15217         }
15218     }
15219   print_operand_value (scratchbuf, 1, off);
15220   oappend (scratchbuf);
15221 }
15222
15223 static void
15224 ptr_reg (int code, int sizeflag)
15225 {
15226   const char *s;
15227
15228   *obufp++ = open_char;
15229   used_prefixes |= (prefixes & PREFIX_ADDR);
15230   if (address_mode == mode_64bit)
15231     {
15232       if (!(sizeflag & AFLAG))
15233         s = names32[code - eAX_reg];
15234       else
15235         s = names64[code - eAX_reg];
15236     }
15237   else if (sizeflag & AFLAG)
15238     s = names32[code - eAX_reg];
15239   else
15240     s = names16[code - eAX_reg];
15241   oappend (s);
15242   *obufp++ = close_char;
15243   *obufp = 0;
15244 }
15245
15246 static void
15247 OP_ESreg (int code, int sizeflag)
15248 {
15249   if (intel_syntax)
15250     {
15251       switch (codep[-1])
15252         {
15253         case 0x6d:      /* insw/insl */
15254           intel_operand_size (z_mode, sizeflag);
15255           break;
15256         case 0xa5:      /* movsw/movsl/movsq */
15257         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15258         case 0xab:      /* stosw/stosl */
15259         case 0xaf:      /* scasw/scasl */
15260           intel_operand_size (v_mode, sizeflag);
15261           break;
15262         default:
15263           intel_operand_size (b_mode, sizeflag);
15264         }
15265     }
15266   oappend_maybe_intel ("%es:");
15267   ptr_reg (code, sizeflag);
15268 }
15269
15270 static void
15271 OP_DSreg (int code, int sizeflag)
15272 {
15273   if (intel_syntax)
15274     {
15275       switch (codep[-1])
15276         {
15277         case 0x6f:      /* outsw/outsl */
15278           intel_operand_size (z_mode, sizeflag);
15279           break;
15280         case 0xa5:      /* movsw/movsl/movsq */
15281         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15282         case 0xad:      /* lodsw/lodsl/lodsq */
15283           intel_operand_size (v_mode, sizeflag);
15284           break;
15285         default:
15286           intel_operand_size (b_mode, sizeflag);
15287         }
15288     }
15289   if ((prefixes
15290        & (PREFIX_CS
15291           | PREFIX_DS
15292           | PREFIX_SS
15293           | PREFIX_ES
15294           | PREFIX_FS
15295           | PREFIX_GS)) == 0)
15296     prefixes |= PREFIX_DS;
15297   append_seg ();
15298   ptr_reg (code, sizeflag);
15299 }
15300
15301 static void
15302 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15303 {
15304   int add;
15305   if (rex & REX_R)
15306     {
15307       USED_REX (REX_R);
15308       add = 8;
15309     }
15310   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
15311     {
15312       all_prefixes[last_lock_prefix] = 0;
15313       used_prefixes |= PREFIX_LOCK;
15314       add = 8;
15315     }
15316   else
15317     add = 0;
15318   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
15319   oappend_maybe_intel (scratchbuf);
15320 }
15321
15322 static void
15323 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15324 {
15325   int add;
15326   USED_REX (REX_R);
15327   if (rex & REX_R)
15328     add = 8;
15329   else
15330     add = 0;
15331   if (intel_syntax)
15332     sprintf (scratchbuf, "db%d", modrm.reg + add);
15333   else
15334     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
15335   oappend (scratchbuf);
15336 }
15337
15338 static void
15339 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15340 {
15341   sprintf (scratchbuf, "%%tr%d", modrm.reg);
15342   oappend_maybe_intel (scratchbuf);
15343 }
15344
15345 static void
15346 OP_R (int bytemode, int sizeflag)
15347 {
15348   if (modrm.mod == 3)
15349     OP_E (bytemode, sizeflag);
15350   else
15351     BadOp ();
15352 }
15353
15354 static void
15355 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15356 {
15357   int reg = modrm.reg;
15358   const char **names;
15359
15360   used_prefixes |= (prefixes & PREFIX_DATA);
15361   if (prefixes & PREFIX_DATA)
15362     {
15363       names = names_xmm;
15364       USED_REX (REX_R);
15365       if (rex & REX_R)
15366         reg += 8;
15367     }
15368   else
15369     names = names_mm;
15370   oappend (names[reg]);
15371 }
15372
15373 static void
15374 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15375 {
15376   int reg = modrm.reg;
15377   const char **names;
15378
15379   USED_REX (REX_R);
15380   if (rex & REX_R)
15381     reg += 8;
15382   if (vex.evex)
15383     {
15384       if (!vex.r)
15385         reg += 16;
15386     }
15387
15388   if (need_vex
15389       && bytemode != xmm_mode
15390       && bytemode != xmmq_mode
15391       && bytemode != evex_half_bcst_xmmq_mode
15392       && bytemode != ymm_mode
15393       && bytemode != scalar_mode)
15394     {
15395       switch (vex.length)
15396         {
15397         case 128:
15398           names = names_xmm;
15399           break;
15400         case 256:
15401           if (vex.w
15402               || (bytemode != vex_vsib_q_w_dq_mode
15403                   && bytemode != vex_vsib_q_w_d_mode))
15404             names = names_ymm;
15405           else
15406             names = names_xmm;
15407           break;
15408         case 512:
15409           names = names_zmm;
15410           break;
15411         default:
15412           abort ();
15413         }
15414     }
15415   else if (bytemode == xmmq_mode
15416            || bytemode == evex_half_bcst_xmmq_mode)
15417     {
15418       switch (vex.length)
15419         {
15420         case 128:
15421         case 256:
15422           names = names_xmm;
15423           break;
15424         case 512:
15425           names = names_ymm;
15426           break;
15427         default:
15428           abort ();
15429         }
15430     }
15431   else if (bytemode == ymm_mode)
15432     names = names_ymm;
15433   else
15434     names = names_xmm;
15435   oappend (names[reg]);
15436 }
15437
15438 static void
15439 OP_EM (int bytemode, int sizeflag)
15440 {
15441   int reg;
15442   const char **names;
15443
15444   if (modrm.mod != 3)
15445     {
15446       if (intel_syntax
15447           && (bytemode == v_mode || bytemode == v_swap_mode))
15448         {
15449           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15450           used_prefixes |= (prefixes & PREFIX_DATA);
15451         }
15452       OP_E (bytemode, sizeflag);
15453       return;
15454     }
15455
15456   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
15457     swap_operand ();
15458
15459   /* Skip mod/rm byte.  */
15460   MODRM_CHECK;
15461   codep++;
15462   used_prefixes |= (prefixes & PREFIX_DATA);
15463   reg = modrm.rm;
15464   if (prefixes & PREFIX_DATA)
15465     {
15466       names = names_xmm;
15467       USED_REX (REX_B);
15468       if (rex & REX_B)
15469         reg += 8;
15470     }
15471   else
15472     names = names_mm;
15473   oappend (names[reg]);
15474 }
15475
15476 /* cvt* are the only instructions in sse2 which have
15477    both SSE and MMX operands and also have 0x66 prefix
15478    in their opcode. 0x66 was originally used to differentiate
15479    between SSE and MMX instruction(operands). So we have to handle the
15480    cvt* separately using OP_EMC and OP_MXC */
15481 static void
15482 OP_EMC (int bytemode, int sizeflag)
15483 {
15484   if (modrm.mod != 3)
15485     {
15486       if (intel_syntax && bytemode == v_mode)
15487         {
15488           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15489           used_prefixes |= (prefixes & PREFIX_DATA);
15490         }
15491       OP_E (bytemode, sizeflag);
15492       return;
15493     }
15494
15495   /* Skip mod/rm byte.  */
15496   MODRM_CHECK;
15497   codep++;
15498   used_prefixes |= (prefixes & PREFIX_DATA);
15499   oappend (names_mm[modrm.rm]);
15500 }
15501
15502 static void
15503 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15504 {
15505   used_prefixes |= (prefixes & PREFIX_DATA);
15506   oappend (names_mm[modrm.reg]);
15507 }
15508
15509 static void
15510 OP_EX (int bytemode, int sizeflag)
15511 {
15512   int reg;
15513   const char **names;
15514
15515   /* Skip mod/rm byte.  */
15516   MODRM_CHECK;
15517   codep++;
15518
15519   if (modrm.mod != 3)
15520     {
15521       OP_E_memory (bytemode, sizeflag);
15522       return;
15523     }
15524
15525   reg = modrm.rm;
15526   USED_REX (REX_B);
15527   if (rex & REX_B)
15528     reg += 8;
15529   if (vex.evex)
15530     {
15531       USED_REX (REX_X);
15532       if ((rex & REX_X))
15533         reg += 16;
15534     }
15535
15536   if ((sizeflag & SUFFIX_ALWAYS)
15537       && (bytemode == x_swap_mode
15538           || bytemode == d_swap_mode
15539           || bytemode == d_scalar_swap_mode
15540           || bytemode == q_swap_mode
15541           || bytemode == q_scalar_swap_mode))
15542     swap_operand ();
15543
15544   if (need_vex
15545       && bytemode != xmm_mode
15546       && bytemode != xmmdw_mode
15547       && bytemode != xmmqd_mode
15548       && bytemode != xmm_mb_mode
15549       && bytemode != xmm_mw_mode
15550       && bytemode != xmm_md_mode
15551       && bytemode != xmm_mq_mode
15552       && bytemode != xmm_mdq_mode
15553       && bytemode != xmmq_mode
15554       && bytemode != evex_half_bcst_xmmq_mode
15555       && bytemode != ymm_mode
15556       && bytemode != d_scalar_mode
15557       && bytemode != d_scalar_swap_mode
15558       && bytemode != q_scalar_mode
15559       && bytemode != q_scalar_swap_mode
15560       && bytemode != vex_scalar_w_dq_mode)
15561     {
15562       switch (vex.length)
15563         {
15564         case 128:
15565           names = names_xmm;
15566           break;
15567         case 256:
15568           names = names_ymm;
15569           break;
15570         case 512:
15571           names = names_zmm;
15572           break;
15573         default:
15574           abort ();
15575         }
15576     }
15577   else if (bytemode == xmmq_mode
15578            || bytemode == evex_half_bcst_xmmq_mode)
15579     {
15580       switch (vex.length)
15581         {
15582         case 128:
15583         case 256:
15584           names = names_xmm;
15585           break;
15586         case 512:
15587           names = names_ymm;
15588           break;
15589         default:
15590           abort ();
15591         }
15592     }
15593   else if (bytemode == ymm_mode)
15594     names = names_ymm;
15595   else
15596     names = names_xmm;
15597   oappend (names[reg]);
15598 }
15599
15600 static void
15601 OP_MS (int bytemode, int sizeflag)
15602 {
15603   if (modrm.mod == 3)
15604     OP_EM (bytemode, sizeflag);
15605   else
15606     BadOp ();
15607 }
15608
15609 static void
15610 OP_XS (int bytemode, int sizeflag)
15611 {
15612   if (modrm.mod == 3)
15613     OP_EX (bytemode, sizeflag);
15614   else
15615     BadOp ();
15616 }
15617
15618 static void
15619 OP_M (int bytemode, int sizeflag)
15620 {
15621   if (modrm.mod == 3)
15622     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
15623     BadOp ();
15624   else
15625     OP_E (bytemode, sizeflag);
15626 }
15627
15628 static void
15629 OP_0f07 (int bytemode, int sizeflag)
15630 {
15631   if (modrm.mod != 3 || modrm.rm != 0)
15632     BadOp ();
15633   else
15634     OP_E (bytemode, sizeflag);
15635 }
15636
15637 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
15638    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
15639
15640 static void
15641 NOP_Fixup1 (int bytemode, int sizeflag)
15642 {
15643   if ((prefixes & PREFIX_DATA) != 0
15644       || (rex != 0
15645           && rex != 0x48
15646           && address_mode == mode_64bit))
15647     OP_REG (bytemode, sizeflag);
15648   else
15649     strcpy (obuf, "nop");
15650 }
15651
15652 static void
15653 NOP_Fixup2 (int bytemode, int sizeflag)
15654 {
15655   if ((prefixes & PREFIX_DATA) != 0
15656       || (rex != 0
15657           && rex != 0x48
15658           && address_mode == mode_64bit))
15659     OP_IMREG (bytemode, sizeflag);
15660 }
15661
15662 static const char *const Suffix3DNow[] = {
15663 /* 00 */        NULL,           NULL,           NULL,           NULL,
15664 /* 04 */        NULL,           NULL,           NULL,           NULL,
15665 /* 08 */        NULL,           NULL,           NULL,           NULL,
15666 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
15667 /* 10 */        NULL,           NULL,           NULL,           NULL,
15668 /* 14 */        NULL,           NULL,           NULL,           NULL,
15669 /* 18 */        NULL,           NULL,           NULL,           NULL,
15670 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
15671 /* 20 */        NULL,           NULL,           NULL,           NULL,
15672 /* 24 */        NULL,           NULL,           NULL,           NULL,
15673 /* 28 */        NULL,           NULL,           NULL,           NULL,
15674 /* 2C */        NULL,           NULL,           NULL,           NULL,
15675 /* 30 */        NULL,           NULL,           NULL,           NULL,
15676 /* 34 */        NULL,           NULL,           NULL,           NULL,
15677 /* 38 */        NULL,           NULL,           NULL,           NULL,
15678 /* 3C */        NULL,           NULL,           NULL,           NULL,
15679 /* 40 */        NULL,           NULL,           NULL,           NULL,
15680 /* 44 */        NULL,           NULL,           NULL,           NULL,
15681 /* 48 */        NULL,           NULL,           NULL,           NULL,
15682 /* 4C */        NULL,           NULL,           NULL,           NULL,
15683 /* 50 */        NULL,           NULL,           NULL,           NULL,
15684 /* 54 */        NULL,           NULL,           NULL,           NULL,
15685 /* 58 */        NULL,           NULL,           NULL,           NULL,
15686 /* 5C */        NULL,           NULL,           NULL,           NULL,
15687 /* 60 */        NULL,           NULL,           NULL,           NULL,
15688 /* 64 */        NULL,           NULL,           NULL,           NULL,
15689 /* 68 */        NULL,           NULL,           NULL,           NULL,
15690 /* 6C */        NULL,           NULL,           NULL,           NULL,
15691 /* 70 */        NULL,           NULL,           NULL,           NULL,
15692 /* 74 */        NULL,           NULL,           NULL,           NULL,
15693 /* 78 */        NULL,           NULL,           NULL,           NULL,
15694 /* 7C */        NULL,           NULL,           NULL,           NULL,
15695 /* 80 */        NULL,           NULL,           NULL,           NULL,
15696 /* 84 */        NULL,           NULL,           NULL,           NULL,
15697 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
15698 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
15699 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
15700 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
15701 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
15702 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
15703 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
15704 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
15705 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
15706 /* AC */        NULL,           NULL,           "pfacc",        NULL,
15707 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
15708 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
15709 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
15710 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
15711 /* C0 */        NULL,           NULL,           NULL,           NULL,
15712 /* C4 */        NULL,           NULL,           NULL,           NULL,
15713 /* C8 */        NULL,           NULL,           NULL,           NULL,
15714 /* CC */        NULL,           NULL,           NULL,           NULL,
15715 /* D0 */        NULL,           NULL,           NULL,           NULL,
15716 /* D4 */        NULL,           NULL,           NULL,           NULL,
15717 /* D8 */        NULL,           NULL,           NULL,           NULL,
15718 /* DC */        NULL,           NULL,           NULL,           NULL,
15719 /* E0 */        NULL,           NULL,           NULL,           NULL,
15720 /* E4 */        NULL,           NULL,           NULL,           NULL,
15721 /* E8 */        NULL,           NULL,           NULL,           NULL,
15722 /* EC */        NULL,           NULL,           NULL,           NULL,
15723 /* F0 */        NULL,           NULL,           NULL,           NULL,
15724 /* F4 */        NULL,           NULL,           NULL,           NULL,
15725 /* F8 */        NULL,           NULL,           NULL,           NULL,
15726 /* FC */        NULL,           NULL,           NULL,           NULL,
15727 };
15728
15729 static void
15730 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15731 {
15732   const char *mnemonic;
15733
15734   FETCH_DATA (the_info, codep + 1);
15735   /* AMD 3DNow! instructions are specified by an opcode suffix in the
15736      place where an 8-bit immediate would normally go.  ie. the last
15737      byte of the instruction.  */
15738   obufp = mnemonicendp;
15739   mnemonic = Suffix3DNow[*codep++ & 0xff];
15740   if (mnemonic)
15741     oappend (mnemonic);
15742   else
15743     {
15744       /* Since a variable sized modrm/sib chunk is between the start
15745          of the opcode (0x0f0f) and the opcode suffix, we need to do
15746          all the modrm processing first, and don't know until now that
15747          we have a bad opcode.  This necessitates some cleaning up.  */
15748       op_out[0][0] = '\0';
15749       op_out[1][0] = '\0';
15750       BadOp ();
15751     }
15752   mnemonicendp = obufp;
15753 }
15754
15755 static struct op simd_cmp_op[] =
15756 {
15757   { STRING_COMMA_LEN ("eq") },
15758   { STRING_COMMA_LEN ("lt") },
15759   { STRING_COMMA_LEN ("le") },
15760   { STRING_COMMA_LEN ("unord") },
15761   { STRING_COMMA_LEN ("neq") },
15762   { STRING_COMMA_LEN ("nlt") },
15763   { STRING_COMMA_LEN ("nle") },
15764   { STRING_COMMA_LEN ("ord") }
15765 };
15766
15767 static void
15768 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15769 {
15770   unsigned int cmp_type;
15771
15772   FETCH_DATA (the_info, codep + 1);
15773   cmp_type = *codep++ & 0xff;
15774   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
15775     {
15776       char suffix [3];
15777       char *p = mnemonicendp - 2;
15778       suffix[0] = p[0];
15779       suffix[1] = p[1];
15780       suffix[2] = '\0';
15781       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
15782       mnemonicendp += simd_cmp_op[cmp_type].len;
15783     }
15784   else
15785     {
15786       /* We have a reserved extension byte.  Output it directly.  */
15787       scratchbuf[0] = '$';
15788       print_operand_value (scratchbuf + 1, 1, cmp_type);
15789       oappend_maybe_intel (scratchbuf);
15790       scratchbuf[0] = '\0';
15791     }
15792 }
15793
15794 static void
15795 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
15796           int sizeflag ATTRIBUTE_UNUSED)
15797 {
15798   /* mwait %eax,%ecx  */
15799   if (!intel_syntax)
15800     {
15801       const char **names = (address_mode == mode_64bit
15802                             ? names64 : names32);
15803       strcpy (op_out[0], names[0]);
15804       strcpy (op_out[1], names[1]);
15805       two_source_ops = 1;
15806     }
15807   /* Skip mod/rm byte.  */
15808   MODRM_CHECK;
15809   codep++;
15810 }
15811
15812 static void
15813 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
15814             int sizeflag ATTRIBUTE_UNUSED)
15815 {
15816   /* monitor %eax,%ecx,%edx"  */
15817   if (!intel_syntax)
15818     {
15819       const char **op1_names;
15820       const char **names = (address_mode == mode_64bit
15821                             ? names64 : names32);
15822
15823       if (!(prefixes & PREFIX_ADDR))
15824         op1_names = (address_mode == mode_16bit
15825                      ? names16 : names);
15826       else
15827         {
15828           /* Remove "addr16/addr32".  */
15829           all_prefixes[last_addr_prefix] = 0;
15830           op1_names = (address_mode != mode_32bit
15831                        ? names32 : names16);
15832           used_prefixes |= PREFIX_ADDR;
15833         }
15834       strcpy (op_out[0], op1_names[0]);
15835       strcpy (op_out[1], names[1]);
15836       strcpy (op_out[2], names[2]);
15837       two_source_ops = 1;
15838     }
15839   /* Skip mod/rm byte.  */
15840   MODRM_CHECK;
15841   codep++;
15842 }
15843
15844 static void
15845 BadOp (void)
15846 {
15847   /* Throw away prefixes and 1st. opcode byte.  */
15848   codep = insn_codep + 1;
15849   oappend ("(bad)");
15850 }
15851
15852 static void
15853 REP_Fixup (int bytemode, int sizeflag)
15854 {
15855   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
15856      lods and stos.  */
15857   if (prefixes & PREFIX_REPZ)
15858     all_prefixes[last_repz_prefix] = REP_PREFIX;
15859
15860   switch (bytemode)
15861     {
15862     case al_reg:
15863     case eAX_reg:
15864     case indir_dx_reg:
15865       OP_IMREG (bytemode, sizeflag);
15866       break;
15867     case eDI_reg:
15868       OP_ESreg (bytemode, sizeflag);
15869       break;
15870     case eSI_reg:
15871       OP_DSreg (bytemode, sizeflag);
15872       break;
15873     default:
15874       abort ();
15875       break;
15876     }
15877 }
15878
15879 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
15880    "bnd".  */
15881
15882 static void
15883 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15884 {
15885   if (prefixes & PREFIX_REPNZ)
15886     all_prefixes[last_repnz_prefix] = BND_PREFIX;
15887 }
15888
15889 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
15890    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
15891  */
15892
15893 static void
15894 HLE_Fixup1 (int bytemode, int sizeflag)
15895 {
15896   if (modrm.mod != 3
15897       && (prefixes & PREFIX_LOCK) != 0)
15898     {
15899       if (prefixes & PREFIX_REPZ)
15900         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15901       if (prefixes & PREFIX_REPNZ)
15902         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15903     }
15904
15905   OP_E (bytemode, sizeflag);
15906 }
15907
15908 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
15909    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
15910  */
15911
15912 static void
15913 HLE_Fixup2 (int bytemode, int sizeflag)
15914 {
15915   if (modrm.mod != 3)
15916     {
15917       if (prefixes & PREFIX_REPZ)
15918         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15919       if (prefixes & PREFIX_REPNZ)
15920         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15921     }
15922
15923   OP_E (bytemode, sizeflag);
15924 }
15925
15926 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
15927    "xrelease" for memory operand.  No check for LOCK prefix.   */
15928
15929 static void
15930 HLE_Fixup3 (int bytemode, int sizeflag)
15931 {
15932   if (modrm.mod != 3
15933       && last_repz_prefix > last_repnz_prefix
15934       && (prefixes & PREFIX_REPZ) != 0)
15935     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15936
15937   OP_E (bytemode, sizeflag);
15938 }
15939
15940 static void
15941 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
15942 {
15943   USED_REX (REX_W);
15944   if (rex & REX_W)
15945     {
15946       /* Change cmpxchg8b to cmpxchg16b.  */
15947       char *p = mnemonicendp - 2;
15948       mnemonicendp = stpcpy (p, "16b");
15949       bytemode = o_mode;
15950     }
15951   else if ((prefixes & PREFIX_LOCK) != 0)
15952     {
15953       if (prefixes & PREFIX_REPZ)
15954         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15955       if (prefixes & PREFIX_REPNZ)
15956         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15957     }
15958
15959   OP_M (bytemode, sizeflag);
15960 }
15961
15962 static void
15963 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
15964 {
15965   const char **names;
15966
15967   if (need_vex)
15968     {
15969       switch (vex.length)
15970         {
15971         case 128:
15972           names = names_xmm;
15973           break;
15974         case 256:
15975           names = names_ymm;
15976           break;
15977         default:
15978           abort ();
15979         }
15980     }
15981   else
15982     names = names_xmm;
15983   oappend (names[reg]);
15984 }
15985
15986 static void
15987 CRC32_Fixup (int bytemode, int sizeflag)
15988 {
15989   /* Add proper suffix to "crc32".  */
15990   char *p = mnemonicendp;
15991
15992   switch (bytemode)
15993     {
15994     case b_mode:
15995       if (intel_syntax)
15996         goto skip;
15997
15998       *p++ = 'b';
15999       break;
16000     case v_mode:
16001       if (intel_syntax)
16002         goto skip;
16003
16004       USED_REX (REX_W);
16005       if (rex & REX_W)
16006         *p++ = 'q';
16007       else
16008         {
16009           if (sizeflag & DFLAG)
16010             *p++ = 'l';
16011           else
16012             *p++ = 'w';
16013           used_prefixes |= (prefixes & PREFIX_DATA);
16014         }
16015       break;
16016     default:
16017       oappend (INTERNAL_DISASSEMBLER_ERROR);
16018       break;
16019     }
16020   mnemonicendp = p;
16021   *p = '\0';
16022
16023 skip:
16024   if (modrm.mod == 3)
16025     {
16026       int add;
16027
16028       /* Skip mod/rm byte.  */
16029       MODRM_CHECK;
16030       codep++;
16031
16032       USED_REX (REX_B);
16033       add = (rex & REX_B) ? 8 : 0;
16034       if (bytemode == b_mode)
16035         {
16036           USED_REX (0);
16037           if (rex)
16038             oappend (names8rex[modrm.rm + add]);
16039           else
16040             oappend (names8[modrm.rm + add]);
16041         }
16042       else
16043         {
16044           USED_REX (REX_W);
16045           if (rex & REX_W)
16046             oappend (names64[modrm.rm + add]);
16047           else if ((prefixes & PREFIX_DATA))
16048             oappend (names16[modrm.rm + add]);
16049           else
16050             oappend (names32[modrm.rm + add]);
16051         }
16052     }
16053   else
16054     OP_E (bytemode, sizeflag);
16055 }
16056
16057 static void
16058 FXSAVE_Fixup (int bytemode, int sizeflag)
16059 {
16060   /* Add proper suffix to "fxsave" and "fxrstor".  */
16061   USED_REX (REX_W);
16062   if (rex & REX_W)
16063     {
16064       char *p = mnemonicendp;
16065       *p++ = '6';
16066       *p++ = '4';
16067       *p = '\0';
16068       mnemonicendp = p;
16069     }
16070   OP_M (bytemode, sizeflag);
16071 }
16072
16073 /* Display the destination register operand for instructions with
16074    VEX. */
16075
16076 static void
16077 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16078 {
16079   int reg;
16080   const char **names;
16081
16082   if (!need_vex)
16083     abort ();
16084
16085   if (!need_vex_reg)
16086     return;
16087
16088   reg = vex.register_specifier;
16089   if (vex.evex)
16090     {
16091       if (!vex.v)
16092         reg += 16;
16093     }
16094
16095   if (bytemode == vex_scalar_mode)
16096     {
16097       oappend (names_xmm[reg]);
16098       return;
16099     }
16100
16101   switch (vex.length)
16102     {
16103     case 128:
16104       switch (bytemode)
16105         {
16106         case vex_mode:
16107         case vex128_mode:
16108         case vex_vsib_q_w_dq_mode:
16109         case vex_vsib_q_w_d_mode:
16110           names = names_xmm;
16111           break;
16112         case dq_mode:
16113           if (vex.w)
16114             names = names64;
16115           else
16116             names = names32;
16117           break;
16118         case mask_mode:
16119           names = names_mask;
16120           break;
16121         default:
16122           abort ();
16123           return;
16124         }
16125       break;
16126     case 256:
16127       switch (bytemode)
16128         {
16129         case vex_mode:
16130         case vex256_mode:
16131           names = names_ymm;
16132           break;
16133         case vex_vsib_q_w_dq_mode:
16134         case vex_vsib_q_w_d_mode:
16135           names = vex.w ? names_ymm : names_xmm;
16136           break;
16137         case mask_mode:
16138           names = names_mask;
16139           break;
16140         default:
16141           abort ();
16142           return;
16143         }
16144       break;
16145     case 512:
16146       names = names_zmm;
16147       break;
16148     default:
16149       abort ();
16150       break;
16151     }
16152   oappend (names[reg]);
16153 }
16154
16155 /* Get the VEX immediate byte without moving codep.  */
16156
16157 static unsigned char
16158 get_vex_imm8 (int sizeflag, int opnum)
16159 {
16160   int bytes_before_imm = 0;
16161
16162   if (modrm.mod != 3)
16163     {
16164       /* There are SIB/displacement bytes.  */
16165       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
16166         {
16167           /* 32/64 bit address mode */
16168           int base = modrm.rm;
16169
16170           /* Check SIB byte.  */
16171           if (base == 4)
16172             {
16173               FETCH_DATA (the_info, codep + 1);
16174               base = *codep & 7;
16175               /* When decoding the third source, don't increase
16176                  bytes_before_imm as this has already been incremented
16177                  by one in OP_E_memory while decoding the second
16178                  source operand.  */
16179               if (opnum == 0)
16180                 bytes_before_imm++;
16181             }
16182
16183           /* Don't increase bytes_before_imm when decoding the third source,
16184              it has already been incremented by OP_E_memory while decoding
16185              the second source operand.  */
16186           if (opnum == 0)
16187             {
16188               switch (modrm.mod)
16189                 {
16190                   case 0:
16191                     /* When modrm.rm == 5 or modrm.rm == 4 and base in
16192                        SIB == 5, there is a 4 byte displacement.  */
16193                     if (base != 5)
16194                       /* No displacement. */
16195                       break;
16196                   case 2:
16197                     /* 4 byte displacement.  */
16198                     bytes_before_imm += 4;
16199                     break;
16200                   case 1:
16201                     /* 1 byte displacement.  */
16202                     bytes_before_imm++;
16203                     break;
16204                 }
16205             }
16206         }
16207       else
16208         {
16209           /* 16 bit address mode */
16210           /* Don't increase bytes_before_imm when decoding the third source,
16211              it has already been incremented by OP_E_memory while decoding
16212              the second source operand.  */
16213           if (opnum == 0)
16214             {
16215               switch (modrm.mod)
16216                 {
16217                 case 0:
16218                   /* When modrm.rm == 6, there is a 2 byte displacement.  */
16219                   if (modrm.rm != 6)
16220                     /* No displacement. */
16221                     break;
16222                 case 2:
16223                   /* 2 byte displacement.  */
16224                   bytes_before_imm += 2;
16225                   break;
16226                 case 1:
16227                   /* 1 byte displacement: when decoding the third source,
16228                      don't increase bytes_before_imm as this has already
16229                      been incremented by one in OP_E_memory while decoding
16230                      the second source operand.  */
16231                   if (opnum == 0)
16232                     bytes_before_imm++;
16233
16234                   break;
16235                 }
16236             }
16237         }
16238     }
16239
16240   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
16241   return codep [bytes_before_imm];
16242 }
16243
16244 static void
16245 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
16246 {
16247   const char **names;
16248
16249   if (reg == -1 && modrm.mod != 3)
16250     {
16251       OP_E_memory (bytemode, sizeflag);
16252       return;
16253     }
16254   else
16255     {
16256       if (reg == -1)
16257         {
16258           reg = modrm.rm;
16259           USED_REX (REX_B);
16260           if (rex & REX_B)
16261             reg += 8;
16262         }
16263       else if (reg > 7 && address_mode != mode_64bit)
16264         BadOp ();
16265     }
16266
16267   switch (vex.length)
16268     {
16269     case 128:
16270       names = names_xmm;
16271       break;
16272     case 256:
16273       names = names_ymm;
16274       break;
16275     default:
16276       abort ();
16277     }
16278   oappend (names[reg]);
16279 }
16280
16281 static void
16282 OP_EX_VexImmW (int bytemode, int sizeflag)
16283 {
16284   int reg = -1;
16285   static unsigned char vex_imm8;
16286
16287   if (vex_w_done == 0)
16288     {
16289       vex_w_done = 1;
16290
16291       /* Skip mod/rm byte.  */
16292       MODRM_CHECK;
16293       codep++;
16294
16295       vex_imm8 = get_vex_imm8 (sizeflag, 0);
16296
16297       if (vex.w)
16298           reg = vex_imm8 >> 4;
16299
16300       OP_EX_VexReg (bytemode, sizeflag, reg);
16301     }
16302   else if (vex_w_done == 1)
16303     {
16304       vex_w_done = 2;
16305
16306       if (!vex.w)
16307           reg = vex_imm8 >> 4;
16308
16309       OP_EX_VexReg (bytemode, sizeflag, reg);
16310     }
16311   else
16312     {
16313       /* Output the imm8 directly.  */
16314       scratchbuf[0] = '$';
16315       print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
16316       oappend_maybe_intel (scratchbuf);
16317       scratchbuf[0] = '\0';
16318       codep++;
16319     }
16320 }
16321
16322 static void
16323 OP_Vex_2src (int bytemode, int sizeflag)
16324 {
16325   if (modrm.mod == 3)
16326     {
16327       int reg = modrm.rm;
16328       USED_REX (REX_B);
16329       if (rex & REX_B)
16330         reg += 8;
16331       oappend (names_xmm[reg]);
16332     }
16333   else
16334     {
16335       if (intel_syntax
16336           && (bytemode == v_mode || bytemode == v_swap_mode))
16337         {
16338           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16339           used_prefixes |= (prefixes & PREFIX_DATA);
16340         }
16341       OP_E (bytemode, sizeflag);
16342     }
16343 }
16344
16345 static void
16346 OP_Vex_2src_1 (int bytemode, int sizeflag)
16347 {
16348   if (modrm.mod == 3)
16349     {
16350       /* Skip mod/rm byte.   */
16351       MODRM_CHECK;
16352       codep++;
16353     }
16354
16355   if (vex.w)
16356     oappend (names_xmm[vex.register_specifier]);
16357   else
16358     OP_Vex_2src (bytemode, sizeflag);
16359 }
16360
16361 static void
16362 OP_Vex_2src_2 (int bytemode, int sizeflag)
16363 {
16364   if (vex.w)
16365     OP_Vex_2src (bytemode, sizeflag);
16366   else
16367     oappend (names_xmm[vex.register_specifier]);
16368 }
16369
16370 static void
16371 OP_EX_VexW (int bytemode, int sizeflag)
16372 {
16373   int reg = -1;
16374
16375   if (!vex_w_done)
16376     {
16377       vex_w_done = 1;
16378
16379       /* Skip mod/rm byte.  */
16380       MODRM_CHECK;
16381       codep++;
16382
16383       if (vex.w)
16384         reg = get_vex_imm8 (sizeflag, 0) >> 4;
16385     }
16386   else
16387     {
16388       if (!vex.w)
16389         reg = get_vex_imm8 (sizeflag, 1) >> 4;
16390     }
16391
16392   OP_EX_VexReg (bytemode, sizeflag, reg);
16393 }
16394
16395 static void
16396 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,
16397              int sizeflag ATTRIBUTE_UNUSED)
16398 {
16399   /* Skip the immediate byte and check for invalid bits.  */
16400   FETCH_DATA (the_info, codep + 1);
16401   if (*codep++ & 0xf)
16402     BadOp ();
16403 }
16404
16405 static void
16406 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16407 {
16408   int reg;
16409   const char **names;
16410
16411   FETCH_DATA (the_info, codep + 1);
16412   reg = *codep++;
16413
16414   if (bytemode != x_mode)
16415     abort ();
16416
16417   if (reg & 0xf)
16418       BadOp ();
16419
16420   reg >>= 4;
16421   if (reg > 7 && address_mode != mode_64bit)
16422     BadOp ();
16423
16424   switch (vex.length)
16425     {
16426     case 128:
16427       names = names_xmm;
16428       break;
16429     case 256:
16430       names = names_ymm;
16431       break;
16432     default:
16433       abort ();
16434     }
16435   oappend (names[reg]);
16436 }
16437
16438 static void
16439 OP_XMM_VexW (int bytemode, int sizeflag)
16440 {
16441   /* Turn off the REX.W bit since it is used for swapping operands
16442      now.  */
16443   rex &= ~REX_W;
16444   OP_XMM (bytemode, sizeflag);
16445 }
16446
16447 static void
16448 OP_EX_Vex (int bytemode, int sizeflag)
16449 {
16450   if (modrm.mod != 3)
16451     {
16452       if (vex.register_specifier != 0)
16453         BadOp ();
16454       need_vex_reg = 0;
16455     }
16456   OP_EX (bytemode, sizeflag);
16457 }
16458
16459 static void
16460 OP_XMM_Vex (int bytemode, int sizeflag)
16461 {
16462   if (modrm.mod != 3)
16463     {
16464       if (vex.register_specifier != 0)
16465         BadOp ();
16466       need_vex_reg = 0;
16467     }
16468   OP_XMM (bytemode, sizeflag);
16469 }
16470
16471 static void
16472 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16473 {
16474   switch (vex.length)
16475     {
16476     case 128:
16477       mnemonicendp = stpcpy (obuf, "vzeroupper");
16478       break;
16479     case 256:
16480       mnemonicendp = stpcpy (obuf, "vzeroall");
16481       break;
16482     default:
16483       abort ();
16484     }
16485 }
16486
16487 static struct op vex_cmp_op[] =
16488 {
16489   { STRING_COMMA_LEN ("eq") },
16490   { STRING_COMMA_LEN ("lt") },
16491   { STRING_COMMA_LEN ("le") },
16492   { STRING_COMMA_LEN ("unord") },
16493   { STRING_COMMA_LEN ("neq") },
16494   { STRING_COMMA_LEN ("nlt") },
16495   { STRING_COMMA_LEN ("nle") },
16496   { STRING_COMMA_LEN ("ord") },
16497   { STRING_COMMA_LEN ("eq_uq") },
16498   { STRING_COMMA_LEN ("nge") },
16499   { STRING_COMMA_LEN ("ngt") },
16500   { STRING_COMMA_LEN ("false") },
16501   { STRING_COMMA_LEN ("neq_oq") },
16502   { STRING_COMMA_LEN ("ge") },
16503   { STRING_COMMA_LEN ("gt") },
16504   { STRING_COMMA_LEN ("true") },
16505   { STRING_COMMA_LEN ("eq_os") },
16506   { STRING_COMMA_LEN ("lt_oq") },
16507   { STRING_COMMA_LEN ("le_oq") },
16508   { STRING_COMMA_LEN ("unord_s") },
16509   { STRING_COMMA_LEN ("neq_us") },
16510   { STRING_COMMA_LEN ("nlt_uq") },
16511   { STRING_COMMA_LEN ("nle_uq") },
16512   { STRING_COMMA_LEN ("ord_s") },
16513   { STRING_COMMA_LEN ("eq_us") },
16514   { STRING_COMMA_LEN ("nge_uq") },
16515   { STRING_COMMA_LEN ("ngt_uq") },
16516   { STRING_COMMA_LEN ("false_os") },
16517   { STRING_COMMA_LEN ("neq_os") },
16518   { STRING_COMMA_LEN ("ge_oq") },
16519   { STRING_COMMA_LEN ("gt_oq") },
16520   { STRING_COMMA_LEN ("true_us") },
16521 };
16522
16523 static void
16524 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16525 {
16526   unsigned int cmp_type;
16527
16528   FETCH_DATA (the_info, codep + 1);
16529   cmp_type = *codep++ & 0xff;
16530   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
16531     {
16532       char suffix [3];
16533       char *p = mnemonicendp - 2;
16534       suffix[0] = p[0];
16535       suffix[1] = p[1];
16536       suffix[2] = '\0';
16537       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
16538       mnemonicendp += vex_cmp_op[cmp_type].len;
16539     }
16540   else
16541     {
16542       /* We have a reserved extension byte.  Output it directly.  */
16543       scratchbuf[0] = '$';
16544       print_operand_value (scratchbuf + 1, 1, cmp_type);
16545       oappend_maybe_intel (scratchbuf);
16546       scratchbuf[0] = '\0';
16547     }
16548 }
16549
16550 static void
16551 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
16552              int sizeflag ATTRIBUTE_UNUSED)
16553 {
16554   unsigned int cmp_type;
16555
16556   if (!vex.evex)
16557     abort ();
16558
16559   FETCH_DATA (the_info, codep + 1);
16560   cmp_type = *codep++ & 0xff;
16561   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
16562      If it's the case, print suffix, otherwise - print the immediate.  */
16563   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
16564       && cmp_type != 3
16565       && cmp_type != 7)
16566     {
16567       char suffix [3];
16568       char *p = mnemonicendp - 2;
16569
16570       /* vpcmp* can have both one- and two-lettered suffix.  */
16571       if (p[0] == 'p')
16572         {
16573           p++;
16574           suffix[0] = p[0];
16575           suffix[1] = '\0';
16576         }
16577       else
16578         {
16579           suffix[0] = p[0];
16580           suffix[1] = p[1];
16581           suffix[2] = '\0';
16582         }
16583
16584       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16585       mnemonicendp += simd_cmp_op[cmp_type].len;
16586     }
16587   else
16588     {
16589       /* We have a reserved extension byte.  Output it directly.  */
16590       scratchbuf[0] = '$';
16591       print_operand_value (scratchbuf + 1, 1, cmp_type);
16592       oappend_maybe_intel (scratchbuf);
16593       scratchbuf[0] = '\0';
16594     }
16595 }
16596
16597 static const struct op pclmul_op[] =
16598 {
16599   { STRING_COMMA_LEN ("lql") },
16600   { STRING_COMMA_LEN ("hql") },
16601   { STRING_COMMA_LEN ("lqh") },
16602   { STRING_COMMA_LEN ("hqh") }
16603 };
16604
16605 static void
16606 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
16607               int sizeflag ATTRIBUTE_UNUSED)
16608 {
16609   unsigned int pclmul_type;
16610
16611   FETCH_DATA (the_info, codep + 1);
16612   pclmul_type = *codep++ & 0xff;
16613   switch (pclmul_type)
16614     {
16615     case 0x10:
16616       pclmul_type = 2;
16617       break;
16618     case 0x11:
16619       pclmul_type = 3;
16620       break;
16621     default:
16622       break;
16623     }
16624   if (pclmul_type < ARRAY_SIZE (pclmul_op))
16625     {
16626       char suffix [4];
16627       char *p = mnemonicendp - 3;
16628       suffix[0] = p[0];
16629       suffix[1] = p[1];
16630       suffix[2] = p[2];
16631       suffix[3] = '\0';
16632       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
16633       mnemonicendp += pclmul_op[pclmul_type].len;
16634     }
16635   else
16636     {
16637       /* We have a reserved extension byte.  Output it directly.  */
16638       scratchbuf[0] = '$';
16639       print_operand_value (scratchbuf + 1, 1, pclmul_type);
16640       oappend_maybe_intel (scratchbuf);
16641       scratchbuf[0] = '\0';
16642     }
16643 }
16644
16645 static void
16646 MOVBE_Fixup (int bytemode, int sizeflag)
16647 {
16648   /* Add proper suffix to "movbe".  */
16649   char *p = mnemonicendp;
16650
16651   switch (bytemode)
16652     {
16653     case v_mode:
16654       if (intel_syntax)
16655         goto skip;
16656
16657       USED_REX (REX_W);
16658       if (sizeflag & SUFFIX_ALWAYS)
16659         {
16660           if (rex & REX_W)
16661             *p++ = 'q';
16662           else
16663             {
16664               if (sizeflag & DFLAG)
16665                 *p++ = 'l';
16666               else
16667                 *p++ = 'w';
16668               used_prefixes |= (prefixes & PREFIX_DATA);
16669             }
16670         }
16671       break;
16672     default:
16673       oappend (INTERNAL_DISASSEMBLER_ERROR);
16674       break;
16675     }
16676   mnemonicendp = p;
16677   *p = '\0';
16678
16679 skip:
16680   OP_M (bytemode, sizeflag);
16681 }
16682
16683 static void
16684 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16685 {
16686   int reg;
16687   const char **names;
16688
16689   /* Skip mod/rm byte.  */
16690   MODRM_CHECK;
16691   codep++;
16692
16693   if (vex.w)
16694     names = names64;
16695   else
16696     names = names32;
16697
16698   reg = modrm.rm;
16699   USED_REX (REX_B);
16700   if (rex & REX_B)
16701     reg += 8;
16702
16703   oappend (names[reg]);
16704 }
16705
16706 static void
16707 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16708 {
16709   const char **names;
16710
16711   if (vex.w)
16712     names = names64;
16713   else
16714     names = names32;
16715
16716   oappend (names[vex.register_specifier]);
16717 }
16718
16719 static void
16720 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16721 {
16722   if (!vex.evex
16723       || bytemode != mask_mode)
16724     abort ();
16725
16726   USED_REX (REX_R);
16727   if ((rex & REX_R) != 0 || !vex.r)
16728     {
16729       BadOp ();
16730       return;
16731     }
16732
16733   oappend (names_mask [modrm.reg]);
16734 }
16735
16736 static void
16737 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16738 {
16739   if (!vex.evex
16740       || (bytemode != evex_rounding_mode
16741           && bytemode != evex_sae_mode))
16742     abort ();
16743   if (modrm.mod == 3 && vex.b)
16744     switch (bytemode)
16745       {
16746       case evex_rounding_mode:
16747         oappend (names_rounding[vex.ll]);
16748         break;
16749       case evex_sae_mode:
16750         oappend ("{sae}");
16751         break;
16752       default:
16753         break;
16754       }
16755 }