1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
6 This file is part of the GNU opcodes library.
8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
24 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
26 modified by John Hassey (hassey@dg-rtp.dg.com)
27 x86-64 support added by Jan Hubicka (jh@suse.cz)
28 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
30 /* The main tables describing the instructions is essentially a copy
31 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
32 Programmers Manual. Usually, there is a capital letter, followed
33 by a small letter. The capital letter tell the addressing mode,
34 and the small letter tells about the operand size. Refer to
35 the Intel manual for details. */
40 #include "opcode/i386.h"
41 #include "libiberty.h"
45 static int print_insn (bfd_vma
, disassemble_info
*);
46 static void dofloat (int);
47 static void OP_ST (int, int);
48 static void OP_STi (int, int);
49 static int putop (const char *, int);
50 static void oappend (const char *);
51 static void append_seg (void);
52 static void OP_indirE (int, int);
53 static void print_operand_value (char *, int, bfd_vma
);
54 static void OP_E_register (int, int);
55 static void OP_E_memory (int, int);
56 static void print_displacement (char *, bfd_vma
);
57 static void OP_E (int, int);
58 static void OP_G (int, int);
59 static bfd_vma
get64 (void);
60 static bfd_signed_vma
get32 (void);
61 static bfd_signed_vma
get32s (void);
62 static int get16 (void);
63 static void set_op (bfd_vma
, int);
64 static void OP_Skip_MODRM (int, int);
65 static void OP_REG (int, int);
66 static void OP_IMREG (int, int);
67 static void OP_I (int, int);
68 static void OP_I64 (int, int);
69 static void OP_sI (int, int);
70 static void OP_J (int, int);
71 static void OP_SEG (int, int);
72 static void OP_DIR (int, int);
73 static void OP_OFF (int, int);
74 static void OP_OFF64 (int, int);
75 static void ptr_reg (int, int);
76 static void OP_ESreg (int, int);
77 static void OP_DSreg (int, int);
78 static void OP_C (int, int);
79 static void OP_D (int, int);
80 static void OP_T (int, int);
81 static void OP_R (int, int);
82 static void OP_MMX (int, int);
83 static void OP_XMM (int, int);
84 static void OP_EM (int, int);
85 static void OP_EX (int, int);
86 static void OP_EMC (int,int);
87 static void OP_MXC (int,int);
88 static void OP_MS (int, int);
89 static void OP_XS (int, int);
90 static void OP_M (int, int);
91 static void OP_VEX (int, int);
92 static void OP_EX_Vex (int, int);
93 static void OP_EX_VexW (int, int);
94 static void OP_XMM_Vex (int, int);
95 static void OP_XMM_VexW (int, int);
96 static void OP_REG_VexI4 (int, int);
97 static void PCLMUL_Fixup (int, int);
98 static void VEXI4_Fixup (int, int);
99 static void VZERO_Fixup (int, int);
100 static void VCMP_Fixup (int, int);
101 static void OP_0f07 (int, int);
102 static void OP_Monitor (int, int);
103 static void OP_Mwait (int, int);
104 static void NOP_Fixup1 (int, int);
105 static void NOP_Fixup2 (int, int);
106 static void OP_3DNowSuffix (int, int);
107 static void CMP_Fixup (int, int);
108 static void BadOp (void);
109 static void REP_Fixup (int, int);
110 static void CMPXCHG8B_Fixup (int, int);
111 static void XMM_Fixup (int, int);
112 static void CRC32_Fixup (int, int);
113 static void FXSAVE_Fixup (int, int);
114 static void OP_LWPCB_E (int, int);
115 static void OP_LWP_E (int, int);
116 static void OP_LWP_I (int, int);
117 static void OP_Vex_2src_1 (int, int);
118 static void OP_Vex_2src_2 (int, int);
120 static void MOVBE_Fixup (int, int);
123 /* Points to first byte not fetched. */
124 bfd_byte
*max_fetched
;
125 bfd_byte the_buffer
[MAX_MNEM_SIZE
];
138 enum address_mode address_mode
;
140 /* Flags for the prefixes for the current instruction. See below. */
143 /* REX prefix the current instruction. See below. */
145 /* Bits of REX we've already used. */
147 /* REX bits in original REX prefix ignored. */
148 static int rex_ignored
;
149 /* Mark parts used in the REX prefix. When we are testing for
150 empty prefix (for 8bit register REX extension), just mask it
151 out. Otherwise test for REX bit is excuse for existence of REX
152 only in case value is nonzero. */
153 #define USED_REX(value) \
158 rex_used |= (value) | REX_OPCODE; \
161 rex_used |= REX_OPCODE; \
164 /* Flags for prefixes which we somehow handled when printing the
165 current instruction. */
166 static int used_prefixes
;
168 /* Flags stored in PREFIXES. */
169 #define PREFIX_REPZ 1
170 #define PREFIX_REPNZ 2
171 #define PREFIX_LOCK 4
173 #define PREFIX_SS 0x10
174 #define PREFIX_DS 0x20
175 #define PREFIX_ES 0x40
176 #define PREFIX_FS 0x80
177 #define PREFIX_GS 0x100
178 #define PREFIX_DATA 0x200
179 #define PREFIX_ADDR 0x400
180 #define PREFIX_FWAIT 0x800
182 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
183 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
185 #define FETCH_DATA(info, addr) \
186 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
187 ? 1 : fetch_data ((info), (addr)))
190 fetch_data (struct disassemble_info
*info
, bfd_byte
*addr
)
193 struct dis_private
*priv
= (struct dis_private
*) info
->private_data
;
194 bfd_vma start
= priv
->insn_start
+ (priv
->max_fetched
- priv
->the_buffer
);
196 if (addr
<= priv
->the_buffer
+ MAX_MNEM_SIZE
)
197 status
= (*info
->read_memory_func
) (start
,
199 addr
- priv
->max_fetched
,
205 /* If we did manage to read at least one byte, then
206 print_insn_i386 will do something sensible. Otherwise, print
207 an error. We do that here because this is where we know
209 if (priv
->max_fetched
== priv
->the_buffer
)
210 (*info
->memory_error_func
) (status
, start
, info
);
211 longjmp (priv
->bailout
, 1);
214 priv
->max_fetched
= addr
;
218 #define XX { NULL, 0 }
219 #define Bad_Opcode NULL, { { NULL, 0 } }
221 #define Eb { OP_E, b_mode }
222 #define EbS { OP_E, b_swap_mode }
223 #define Ev { OP_E, v_mode }
224 #define EvS { OP_E, v_swap_mode }
225 #define Ed { OP_E, d_mode }
226 #define Edq { OP_E, dq_mode }
227 #define Edqw { OP_E, dqw_mode }
228 #define Edqb { OP_E, dqb_mode }
229 #define Edqd { OP_E, dqd_mode }
230 #define Eq { OP_E, q_mode }
231 #define indirEv { OP_indirE, stack_v_mode }
232 #define indirEp { OP_indirE, f_mode }
233 #define stackEv { OP_E, stack_v_mode }
234 #define Em { OP_E, m_mode }
235 #define Ew { OP_E, w_mode }
236 #define M { OP_M, 0 } /* lea, lgdt, etc. */
237 #define Ma { OP_M, a_mode }
238 #define Mb { OP_M, b_mode }
239 #define Md { OP_M, d_mode }
240 #define Mo { OP_M, o_mode }
241 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
242 #define Mq { OP_M, q_mode }
243 #define Mx { OP_M, x_mode }
244 #define Mxmm { OP_M, xmm_mode }
245 #define Gb { OP_G, b_mode }
246 #define Gv { OP_G, v_mode }
247 #define Gd { OP_G, d_mode }
248 #define Gdq { OP_G, dq_mode }
249 #define Gm { OP_G, m_mode }
250 #define Gw { OP_G, w_mode }
251 #define Rd { OP_R, d_mode }
252 #define Rm { OP_R, m_mode }
253 #define Ib { OP_I, b_mode }
254 #define sIb { OP_sI, b_mode } /* sign extened byte */
255 #define Iv { OP_I, v_mode }
256 #define Iq { OP_I, q_mode }
257 #define Iv64 { OP_I64, v_mode }
258 #define Iw { OP_I, w_mode }
259 #define I1 { OP_I, const_1_mode }
260 #define Jb { OP_J, b_mode }
261 #define Jv { OP_J, v_mode }
262 #define Cm { OP_C, m_mode }
263 #define Dm { OP_D, m_mode }
264 #define Td { OP_T, d_mode }
265 #define Skip_MODRM { OP_Skip_MODRM, 0 }
267 #define RMeAX { OP_REG, eAX_reg }
268 #define RMeBX { OP_REG, eBX_reg }
269 #define RMeCX { OP_REG, eCX_reg }
270 #define RMeDX { OP_REG, eDX_reg }
271 #define RMeSP { OP_REG, eSP_reg }
272 #define RMeBP { OP_REG, eBP_reg }
273 #define RMeSI { OP_REG, eSI_reg }
274 #define RMeDI { OP_REG, eDI_reg }
275 #define RMrAX { OP_REG, rAX_reg }
276 #define RMrBX { OP_REG, rBX_reg }
277 #define RMrCX { OP_REG, rCX_reg }
278 #define RMrDX { OP_REG, rDX_reg }
279 #define RMrSP { OP_REG, rSP_reg }
280 #define RMrBP { OP_REG, rBP_reg }
281 #define RMrSI { OP_REG, rSI_reg }
282 #define RMrDI { OP_REG, rDI_reg }
283 #define RMAL { OP_REG, al_reg }
284 #define RMAL { OP_REG, al_reg }
285 #define RMCL { OP_REG, cl_reg }
286 #define RMDL { OP_REG, dl_reg }
287 #define RMBL { OP_REG, bl_reg }
288 #define RMAH { OP_REG, ah_reg }
289 #define RMCH { OP_REG, ch_reg }
290 #define RMDH { OP_REG, dh_reg }
291 #define RMBH { OP_REG, bh_reg }
292 #define RMAX { OP_REG, ax_reg }
293 #define RMDX { OP_REG, dx_reg }
295 #define eAX { OP_IMREG, eAX_reg }
296 #define eBX { OP_IMREG, eBX_reg }
297 #define eCX { OP_IMREG, eCX_reg }
298 #define eDX { OP_IMREG, eDX_reg }
299 #define eSP { OP_IMREG, eSP_reg }
300 #define eBP { OP_IMREG, eBP_reg }
301 #define eSI { OP_IMREG, eSI_reg }
302 #define eDI { OP_IMREG, eDI_reg }
303 #define AL { OP_IMREG, al_reg }
304 #define CL { OP_IMREG, cl_reg }
305 #define DL { OP_IMREG, dl_reg }
306 #define BL { OP_IMREG, bl_reg }
307 #define AH { OP_IMREG, ah_reg }
308 #define CH { OP_IMREG, ch_reg }
309 #define DH { OP_IMREG, dh_reg }
310 #define BH { OP_IMREG, bh_reg }
311 #define AX { OP_IMREG, ax_reg }
312 #define DX { OP_IMREG, dx_reg }
313 #define zAX { OP_IMREG, z_mode_ax_reg }
314 #define indirDX { OP_IMREG, indir_dx_reg }
316 #define Sw { OP_SEG, w_mode }
317 #define Sv { OP_SEG, v_mode }
318 #define Ap { OP_DIR, 0 }
319 #define Ob { OP_OFF64, b_mode }
320 #define Ov { OP_OFF64, v_mode }
321 #define Xb { OP_DSreg, eSI_reg }
322 #define Xv { OP_DSreg, eSI_reg }
323 #define Xz { OP_DSreg, eSI_reg }
324 #define Yb { OP_ESreg, eDI_reg }
325 #define Yv { OP_ESreg, eDI_reg }
326 #define DSBX { OP_DSreg, eBX_reg }
328 #define es { OP_REG, es_reg }
329 #define ss { OP_REG, ss_reg }
330 #define cs { OP_REG, cs_reg }
331 #define ds { OP_REG, ds_reg }
332 #define fs { OP_REG, fs_reg }
333 #define gs { OP_REG, gs_reg }
335 #define MX { OP_MMX, 0 }
336 #define XM { OP_XMM, 0 }
337 #define XMScalar { OP_XMM, scalar_mode }
338 #define XMM { OP_XMM, xmm_mode }
339 #define EM { OP_EM, v_mode }
340 #define EMS { OP_EM, v_swap_mode }
341 #define EMd { OP_EM, d_mode }
342 #define EMx { OP_EM, x_mode }
343 #define EXw { OP_EX, w_mode }
344 #define EXd { OP_EX, d_mode }
345 #define EXdScalar { OP_EX, d_scalar_mode }
346 #define EXdS { OP_EX, d_swap_mode }
347 #define EXq { OP_EX, q_mode }
348 #define EXqScalar { OP_EX, q_scalar_mode }
349 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
350 #define EXqS { OP_EX, q_swap_mode }
351 #define EXx { OP_EX, x_mode }
352 #define EXxS { OP_EX, x_swap_mode }
353 #define EXxmm { OP_EX, xmm_mode }
354 #define EXxmmq { OP_EX, xmmq_mode }
355 #define EXymmq { OP_EX, ymmq_mode }
356 #define EXVexWdq { OP_EX, vex_w_dq_mode }
357 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
358 #define MS { OP_MS, v_mode }
359 #define XS { OP_XS, v_mode }
360 #define EMCq { OP_EMC, q_mode }
361 #define MXC { OP_MXC, 0 }
362 #define OPSUF { OP_3DNowSuffix, 0 }
363 #define CMP { CMP_Fixup, 0 }
364 #define XMM0 { XMM_Fixup, 0 }
365 #define FXSAVE { FXSAVE_Fixup, 0 }
366 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
367 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
369 #define Vex { OP_VEX, vex_mode }
370 #define VexScalar { OP_VEX, vex_scalar_mode }
371 #define Vex128 { OP_VEX, vex128_mode }
372 #define Vex256 { OP_VEX, vex256_mode }
373 #define VexI4 { VEXI4_Fixup, 0}
374 #define EXdVex { OP_EX_Vex, d_mode }
375 #define EXdVexS { OP_EX_Vex, d_swap_mode }
376 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
377 #define EXqVex { OP_EX_Vex, q_mode }
378 #define EXqVexS { OP_EX_Vex, q_swap_mode }
379 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
380 #define EXVexW { OP_EX_VexW, x_mode }
381 #define EXdVexW { OP_EX_VexW, d_mode }
382 #define EXqVexW { OP_EX_VexW, q_mode }
383 #define XMVex { OP_XMM_Vex, 0 }
384 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
385 #define XMVexW { OP_XMM_VexW, 0 }
386 #define XMVexI4 { OP_REG_VexI4, x_mode }
387 #define PCLMUL { PCLMUL_Fixup, 0 }
388 #define VZERO { VZERO_Fixup, 0 }
389 #define VCMP { VCMP_Fixup, 0 }
391 /* Used handle "rep" prefix for string instructions. */
392 #define Xbr { REP_Fixup, eSI_reg }
393 #define Xvr { REP_Fixup, eSI_reg }
394 #define Ybr { REP_Fixup, eDI_reg }
395 #define Yvr { REP_Fixup, eDI_reg }
396 #define Yzr { REP_Fixup, eDI_reg }
397 #define indirDXr { REP_Fixup, indir_dx_reg }
398 #define ALr { REP_Fixup, al_reg }
399 #define eAXr { REP_Fixup, eAX_reg }
401 #define cond_jump_flag { NULL, cond_jump_mode }
402 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
404 /* bits in sizeflag */
405 #define SUFFIX_ALWAYS 4
413 /* byte operand with operand swapped */
415 /* operand size depends on prefixes */
417 /* operand size depends on prefixes with operand swapped */
421 /* double word operand */
423 /* double word operand with operand swapped */
425 /* quad word operand */
427 /* quad word operand with operand swapped */
429 /* ten-byte operand */
431 /* 16-byte XMM or 32-byte YMM operand */
433 /* 16-byte XMM or 32-byte YMM operand with operand swapped */
435 /* 16-byte XMM operand */
437 /* 16-byte XMM or quad word operand */
439 /* 32-byte YMM or quad word operand */
441 /* d_mode in 32bit, q_mode in 64bit mode. */
443 /* pair of v_mode operands */
447 /* operand size depends on REX prefixes. */
449 /* registers like dq_mode, memory like w_mode. */
451 /* 4- or 6-byte pointer operand */
454 /* v_mode for stack-related opcodes. */
456 /* non-quad operand size depends on prefixes */
458 /* 16-byte operand */
460 /* registers like dq_mode, memory like b_mode. */
462 /* registers like dq_mode, memory like d_mode. */
464 /* normal vex mode */
466 /* 128bit vex mode */
468 /* 256bit vex mode */
470 /* operand size depends on the VEX.W bit. */
473 /* scalar, ignore vector length. */
475 /* like d_mode, ignore vector length. */
477 /* like d_swap_mode, ignore vector length. */
479 /* like q_mode, ignore vector length. */
481 /* like q_swap_mode, ignore vector length. */
483 /* like vex_mode, ignore vector length. */
485 /* like vex_w_dq_mode, ignore vector length. */
486 vex_scalar_w_dq_mode
,
551 #define FLOAT NULL, { { NULL, FLOATCODE } }
553 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }
554 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
555 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
556 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
557 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
558 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
559 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
560 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
561 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
562 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
563 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
564 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
682 MOD_VEX_3818_PREFIX_2
,
683 MOD_VEX_3819_PREFIX_2
,
684 MOD_VEX_381A_PREFIX_2
,
685 MOD_VEX_382A_PREFIX_2
,
686 MOD_VEX_382C_PREFIX_2
,
687 MOD_VEX_382D_PREFIX_2
,
688 MOD_VEX_382E_PREFIX_2
,
689 MOD_VEX_382F_PREFIX_2
1099 THREE_BYTE_0F38
= 0,
1254 VEX_LEN_3819_P_2_M_0
,
1255 VEX_LEN_381A_P_2_M_0
,
1267 VEX_LEN_382A_P_2_M_0
,
1583 typedef void (*op_rtn
) (int bytemode
, int sizeflag
);
1594 /* Upper case letters in the instruction names here are macros.
1595 'A' => print 'b' if no register operands or suffix_always is true
1596 'B' => print 'b' if suffix_always is true
1597 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
1599 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
1600 suffix_always is true
1601 'E' => print 'e' if 32-bit form of jcxz
1602 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
1603 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
1604 'H' => print ",pt" or ",pn" branch hint
1605 'I' => honor following macro letter even in Intel mode (implemented only
1606 for some of the macro letters)
1608 'K' => print 'd' or 'q' if rex prefix is present.
1609 'L' => print 'l' if suffix_always is true
1610 'M' => print 'r' if intel_mnemonic is false.
1611 'N' => print 'n' if instruction has no wait "prefix"
1612 'O' => print 'd' or 'o' (or 'q' in Intel mode)
1613 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
1614 or suffix_always is true. print 'q' if rex prefix is present.
1615 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
1617 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
1618 'S' => print 'w', 'l' or 'q' if suffix_always is true
1619 'T' => print 'q' in 64bit mode and behave as 'P' otherwise
1620 'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
1621 'V' => print 'q' in 64bit mode and behave as 'S' otherwise
1622 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
1623 'X' => print 's', 'd' depending on data16 prefix (for XMM)
1624 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
1625 suffix_always is true.
1626 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
1627 '!' => change condition from true to false or from false to true.
1628 '%' => add 1 upper case letter to the macro.
1630 2 upper case letter macros:
1631 "XY" => print 'x' or 'y' if no register operands or suffix_always
1633 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
1634 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
1635 or suffix_always is true
1636 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
1637 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
1638 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
1640 Many of the above letters print nothing in Intel mode. See "putop"
1643 Braces '{' and '}', and vertical bars '|', indicate alternative
1644 mnemonic strings for AT&T and Intel. */
1646 static const struct dis386 dis386
[] = {
1648 { "addB", { Eb
, Gb
} },
1649 { "addS", { Ev
, Gv
} },
1650 { "addB", { Gb
, EbS
} },
1651 { "addS", { Gv
, EvS
} },
1652 { "addB", { AL
, Ib
} },
1653 { "addS", { eAX
, Iv
} },
1654 { X86_64_TABLE (X86_64_06
) },
1655 { X86_64_TABLE (X86_64_07
) },
1657 { "orB", { Eb
, Gb
} },
1658 { "orS", { Ev
, Gv
} },
1659 { "orB", { Gb
, EbS
} },
1660 { "orS", { Gv
, EvS
} },
1661 { "orB", { AL
, Ib
} },
1662 { "orS", { eAX
, Iv
} },
1663 { X86_64_TABLE (X86_64_0D
) },
1664 { Bad_Opcode
}, /* 0x0f extended opcode escape */
1666 { "adcB", { Eb
, Gb
} },
1667 { "adcS", { Ev
, Gv
} },
1668 { "adcB", { Gb
, EbS
} },
1669 { "adcS", { Gv
, EvS
} },
1670 { "adcB", { AL
, Ib
} },
1671 { "adcS", { eAX
, Iv
} },
1672 { X86_64_TABLE (X86_64_16
) },
1673 { X86_64_TABLE (X86_64_17
) },
1675 { "sbbB", { Eb
, Gb
} },
1676 { "sbbS", { Ev
, Gv
} },
1677 { "sbbB", { Gb
, EbS
} },
1678 { "sbbS", { Gv
, EvS
} },
1679 { "sbbB", { AL
, Ib
} },
1680 { "sbbS", { eAX
, Iv
} },
1681 { X86_64_TABLE (X86_64_1E
) },
1682 { X86_64_TABLE (X86_64_1F
) },
1684 { "andB", { Eb
, Gb
} },
1685 { "andS", { Ev
, Gv
} },
1686 { "andB", { Gb
, EbS
} },
1687 { "andS", { Gv
, EvS
} },
1688 { "andB", { AL
, Ib
} },
1689 { "andS", { eAX
, Iv
} },
1690 { Bad_Opcode
}, /* SEG ES prefix */
1691 { X86_64_TABLE (X86_64_27
) },
1693 { "subB", { Eb
, Gb
} },
1694 { "subS", { Ev
, Gv
} },
1695 { "subB", { Gb
, EbS
} },
1696 { "subS", { Gv
, EvS
} },
1697 { "subB", { AL
, Ib
} },
1698 { "subS", { eAX
, Iv
} },
1699 { Bad_Opcode
}, /* SEG CS prefix */
1700 { X86_64_TABLE (X86_64_2F
) },
1702 { "xorB", { Eb
, Gb
} },
1703 { "xorS", { Ev
, Gv
} },
1704 { "xorB", { Gb
, EbS
} },
1705 { "xorS", { Gv
, EvS
} },
1706 { "xorB", { AL
, Ib
} },
1707 { "xorS", { eAX
, Iv
} },
1708 { Bad_Opcode
}, /* SEG SS prefix */
1709 { X86_64_TABLE (X86_64_37
) },
1711 { "cmpB", { Eb
, Gb
} },
1712 { "cmpS", { Ev
, Gv
} },
1713 { "cmpB", { Gb
, EbS
} },
1714 { "cmpS", { Gv
, EvS
} },
1715 { "cmpB", { AL
, Ib
} },
1716 { "cmpS", { eAX
, Iv
} },
1717 { Bad_Opcode
}, /* SEG DS prefix */
1718 { X86_64_TABLE (X86_64_3F
) },
1720 { "inc{S|}", { RMeAX
} },
1721 { "inc{S|}", { RMeCX
} },
1722 { "inc{S|}", { RMeDX
} },
1723 { "inc{S|}", { RMeBX
} },
1724 { "inc{S|}", { RMeSP
} },
1725 { "inc{S|}", { RMeBP
} },
1726 { "inc{S|}", { RMeSI
} },
1727 { "inc{S|}", { RMeDI
} },
1729 { "dec{S|}", { RMeAX
} },
1730 { "dec{S|}", { RMeCX
} },
1731 { "dec{S|}", { RMeDX
} },
1732 { "dec{S|}", { RMeBX
} },
1733 { "dec{S|}", { RMeSP
} },
1734 { "dec{S|}", { RMeBP
} },
1735 { "dec{S|}", { RMeSI
} },
1736 { "dec{S|}", { RMeDI
} },
1738 { "pushV", { RMrAX
} },
1739 { "pushV", { RMrCX
} },
1740 { "pushV", { RMrDX
} },
1741 { "pushV", { RMrBX
} },
1742 { "pushV", { RMrSP
} },
1743 { "pushV", { RMrBP
} },
1744 { "pushV", { RMrSI
} },
1745 { "pushV", { RMrDI
} },
1747 { "popV", { RMrAX
} },
1748 { "popV", { RMrCX
} },
1749 { "popV", { RMrDX
} },
1750 { "popV", { RMrBX
} },
1751 { "popV", { RMrSP
} },
1752 { "popV", { RMrBP
} },
1753 { "popV", { RMrSI
} },
1754 { "popV", { RMrDI
} },
1756 { X86_64_TABLE (X86_64_60
) },
1757 { X86_64_TABLE (X86_64_61
) },
1758 { X86_64_TABLE (X86_64_62
) },
1759 { X86_64_TABLE (X86_64_63
) },
1760 { Bad_Opcode
}, /* seg fs */
1761 { Bad_Opcode
}, /* seg gs */
1762 { Bad_Opcode
}, /* op size prefix */
1763 { Bad_Opcode
}, /* adr size prefix */
1765 { "pushT", { Iq
} },
1766 { "imulS", { Gv
, Ev
, Iv
} },
1767 { "pushT", { sIb
} },
1768 { "imulS", { Gv
, Ev
, sIb
} },
1769 { "ins{b|}", { Ybr
, indirDX
} },
1770 { X86_64_TABLE (X86_64_6D
) },
1771 { "outs{b|}", { indirDXr
, Xb
} },
1772 { X86_64_TABLE (X86_64_6F
) },
1774 { "joH", { Jb
, XX
, cond_jump_flag
} },
1775 { "jnoH", { Jb
, XX
, cond_jump_flag
} },
1776 { "jbH", { Jb
, XX
, cond_jump_flag
} },
1777 { "jaeH", { Jb
, XX
, cond_jump_flag
} },
1778 { "jeH", { Jb
, XX
, cond_jump_flag
} },
1779 { "jneH", { Jb
, XX
, cond_jump_flag
} },
1780 { "jbeH", { Jb
, XX
, cond_jump_flag
} },
1781 { "jaH", { Jb
, XX
, cond_jump_flag
} },
1783 { "jsH", { Jb
, XX
, cond_jump_flag
} },
1784 { "jnsH", { Jb
, XX
, cond_jump_flag
} },
1785 { "jpH", { Jb
, XX
, cond_jump_flag
} },
1786 { "jnpH", { Jb
, XX
, cond_jump_flag
} },
1787 { "jlH", { Jb
, XX
, cond_jump_flag
} },
1788 { "jgeH", { Jb
, XX
, cond_jump_flag
} },
1789 { "jleH", { Jb
, XX
, cond_jump_flag
} },
1790 { "jgH", { Jb
, XX
, cond_jump_flag
} },
1792 { REG_TABLE (REG_80
) },
1793 { REG_TABLE (REG_81
) },
1795 { REG_TABLE (REG_82
) },
1796 { "testB", { Eb
, Gb
} },
1797 { "testS", { Ev
, Gv
} },
1798 { "xchgB", { Eb
, Gb
} },
1799 { "xchgS", { Ev
, Gv
} },
1801 { "movB", { Eb
, Gb
} },
1802 { "movS", { Ev
, Gv
} },
1803 { "movB", { Gb
, EbS
} },
1804 { "movS", { Gv
, EvS
} },
1805 { "movD", { Sv
, Sw
} },
1806 { MOD_TABLE (MOD_8D
) },
1807 { "movD", { Sw
, Sv
} },
1808 { REG_TABLE (REG_8F
) },
1810 { PREFIX_TABLE (PREFIX_90
) },
1811 { "xchgS", { RMeCX
, eAX
} },
1812 { "xchgS", { RMeDX
, eAX
} },
1813 { "xchgS", { RMeBX
, eAX
} },
1814 { "xchgS", { RMeSP
, eAX
} },
1815 { "xchgS", { RMeBP
, eAX
} },
1816 { "xchgS", { RMeSI
, eAX
} },
1817 { "xchgS", { RMeDI
, eAX
} },
1819 { "cW{t|}R", { XX
} },
1820 { "cR{t|}O", { XX
} },
1821 { X86_64_TABLE (X86_64_9A
) },
1822 { Bad_Opcode
}, /* fwait */
1823 { "pushfT", { XX
} },
1824 { "popfT", { XX
} },
1828 { "mov%LB", { AL
, Ob
} },
1829 { "mov%LS", { eAX
, Ov
} },
1830 { "mov%LB", { Ob
, AL
} },
1831 { "mov%LS", { Ov
, eAX
} },
1832 { "movs{b|}", { Ybr
, Xb
} },
1833 { "movs{R|}", { Yvr
, Xv
} },
1834 { "cmps{b|}", { Xb
, Yb
} },
1835 { "cmps{R|}", { Xv
, Yv
} },
1837 { "testB", { AL
, Ib
} },
1838 { "testS", { eAX
, Iv
} },
1839 { "stosB", { Ybr
, AL
} },
1840 { "stosS", { Yvr
, eAX
} },
1841 { "lodsB", { ALr
, Xb
} },
1842 { "lodsS", { eAXr
, Xv
} },
1843 { "scasB", { AL
, Yb
} },
1844 { "scasS", { eAX
, Yv
} },
1846 { "movB", { RMAL
, Ib
} },
1847 { "movB", { RMCL
, Ib
} },
1848 { "movB", { RMDL
, Ib
} },
1849 { "movB", { RMBL
, Ib
} },
1850 { "movB", { RMAH
, Ib
} },
1851 { "movB", { RMCH
, Ib
} },
1852 { "movB", { RMDH
, Ib
} },
1853 { "movB", { RMBH
, Ib
} },
1855 { "mov%LV", { RMeAX
, Iv64
} },
1856 { "mov%LV", { RMeCX
, Iv64
} },
1857 { "mov%LV", { RMeDX
, Iv64
} },
1858 { "mov%LV", { RMeBX
, Iv64
} },
1859 { "mov%LV", { RMeSP
, Iv64
} },
1860 { "mov%LV", { RMeBP
, Iv64
} },
1861 { "mov%LV", { RMeSI
, Iv64
} },
1862 { "mov%LV", { RMeDI
, Iv64
} },
1864 { REG_TABLE (REG_C0
) },
1865 { REG_TABLE (REG_C1
) },
1868 { X86_64_TABLE (X86_64_C4
) },
1869 { X86_64_TABLE (X86_64_C5
) },
1870 { REG_TABLE (REG_C6
) },
1871 { REG_TABLE (REG_C7
) },
1873 { "enterT", { Iw
, Ib
} },
1874 { "leaveT", { XX
} },
1875 { "Jret{|f}P", { Iw
} },
1876 { "Jret{|f}P", { XX
} },
1879 { X86_64_TABLE (X86_64_CE
) },
1880 { "iretP", { XX
} },
1882 { REG_TABLE (REG_D0
) },
1883 { REG_TABLE (REG_D1
) },
1884 { REG_TABLE (REG_D2
) },
1885 { REG_TABLE (REG_D3
) },
1886 { X86_64_TABLE (X86_64_D4
) },
1887 { X86_64_TABLE (X86_64_D5
) },
1889 { "xlat", { DSBX
} },
1900 { "loopneFH", { Jb
, XX
, loop_jcxz_flag
} },
1901 { "loopeFH", { Jb
, XX
, loop_jcxz_flag
} },
1902 { "loopFH", { Jb
, XX
, loop_jcxz_flag
} },
1903 { "jEcxzH", { Jb
, XX
, loop_jcxz_flag
} },
1904 { "inB", { AL
, Ib
} },
1905 { "inG", { zAX
, Ib
} },
1906 { "outB", { Ib
, AL
} },
1907 { "outG", { Ib
, zAX
} },
1909 { "callT", { Jv
} },
1911 { X86_64_TABLE (X86_64_EA
) },
1913 { "inB", { AL
, indirDX
} },
1914 { "inG", { zAX
, indirDX
} },
1915 { "outB", { indirDX
, AL
} },
1916 { "outG", { indirDX
, zAX
} },
1918 { Bad_Opcode
}, /* lock prefix */
1919 { "icebp", { XX
} },
1920 { Bad_Opcode
}, /* repne */
1921 { Bad_Opcode
}, /* repz */
1924 { REG_TABLE (REG_F6
) },
1925 { REG_TABLE (REG_F7
) },
1933 { REG_TABLE (REG_FE
) },
1934 { REG_TABLE (REG_FF
) },
1937 static const struct dis386 dis386_twobyte
[] = {
1939 { REG_TABLE (REG_0F00
) },
1940 { REG_TABLE (REG_0F01
) },
1941 { "larS", { Gv
, Ew
} },
1942 { "lslS", { Gv
, Ew
} },
1944 { "syscall", { XX
} },
1946 { "sysretP", { XX
} },
1949 { "wbinvd", { XX
} },
1953 { REG_TABLE (REG_0F0D
) },
1954 { "femms", { XX
} },
1955 { "", { MX
, EM
, OPSUF
} }, /* See OP_3DNowSuffix. */
1957 { PREFIX_TABLE (PREFIX_0F10
) },
1958 { PREFIX_TABLE (PREFIX_0F11
) },
1959 { PREFIX_TABLE (PREFIX_0F12
) },
1960 { MOD_TABLE (MOD_0F13
) },
1961 { "unpcklpX", { XM
, EXx
} },
1962 { "unpckhpX", { XM
, EXx
} },
1963 { PREFIX_TABLE (PREFIX_0F16
) },
1964 { MOD_TABLE (MOD_0F17
) },
1966 { REG_TABLE (REG_0F18
) },
1975 { MOD_TABLE (MOD_0F20
) },
1976 { MOD_TABLE (MOD_0F21
) },
1977 { MOD_TABLE (MOD_0F22
) },
1978 { MOD_TABLE (MOD_0F23
) },
1979 { MOD_TABLE (MOD_0F24
) },
1981 { MOD_TABLE (MOD_0F26
) },
1984 { "movapX", { XM
, EXx
} },
1985 { "movapX", { EXxS
, XM
} },
1986 { PREFIX_TABLE (PREFIX_0F2A
) },
1987 { PREFIX_TABLE (PREFIX_0F2B
) },
1988 { PREFIX_TABLE (PREFIX_0F2C
) },
1989 { PREFIX_TABLE (PREFIX_0F2D
) },
1990 { PREFIX_TABLE (PREFIX_0F2E
) },
1991 { PREFIX_TABLE (PREFIX_0F2F
) },
1993 { "wrmsr", { XX
} },
1994 { "rdtsc", { XX
} },
1995 { "rdmsr", { XX
} },
1996 { "rdpmc", { XX
} },
1997 { "sysenter", { XX
} },
1998 { "sysexit", { XX
} },
2000 { "getsec", { XX
} },
2002 { THREE_BYTE_TABLE (THREE_BYTE_0F38
) },
2004 { THREE_BYTE_TABLE (THREE_BYTE_0F3A
) },
2011 { "cmovoS", { Gv
, Ev
} },
2012 { "cmovnoS", { Gv
, Ev
} },
2013 { "cmovbS", { Gv
, Ev
} },
2014 { "cmovaeS", { Gv
, Ev
} },
2015 { "cmoveS", { Gv
, Ev
} },
2016 { "cmovneS", { Gv
, Ev
} },
2017 { "cmovbeS", { Gv
, Ev
} },
2018 { "cmovaS", { Gv
, Ev
} },
2020 { "cmovsS", { Gv
, Ev
} },
2021 { "cmovnsS", { Gv
, Ev
} },
2022 { "cmovpS", { Gv
, Ev
} },
2023 { "cmovnpS", { Gv
, Ev
} },
2024 { "cmovlS", { Gv
, Ev
} },
2025 { "cmovgeS", { Gv
, Ev
} },
2026 { "cmovleS", { Gv
, Ev
} },
2027 { "cmovgS", { Gv
, Ev
} },
2029 { MOD_TABLE (MOD_0F51
) },
2030 { PREFIX_TABLE (PREFIX_0F51
) },
2031 { PREFIX_TABLE (PREFIX_0F52
) },
2032 { PREFIX_TABLE (PREFIX_0F53
) },
2033 { "andpX", { XM
, EXx
} },
2034 { "andnpX", { XM
, EXx
} },
2035 { "orpX", { XM
, EXx
} },
2036 { "xorpX", { XM
, EXx
} },
2038 { PREFIX_TABLE (PREFIX_0F58
) },
2039 { PREFIX_TABLE (PREFIX_0F59
) },
2040 { PREFIX_TABLE (PREFIX_0F5A
) },
2041 { PREFIX_TABLE (PREFIX_0F5B
) },
2042 { PREFIX_TABLE (PREFIX_0F5C
) },
2043 { PREFIX_TABLE (PREFIX_0F5D
) },
2044 { PREFIX_TABLE (PREFIX_0F5E
) },
2045 { PREFIX_TABLE (PREFIX_0F5F
) },
2047 { PREFIX_TABLE (PREFIX_0F60
) },
2048 { PREFIX_TABLE (PREFIX_0F61
) },
2049 { PREFIX_TABLE (PREFIX_0F62
) },
2050 { "packsswb", { MX
, EM
} },
2051 { "pcmpgtb", { MX
, EM
} },
2052 { "pcmpgtw", { MX
, EM
} },
2053 { "pcmpgtd", { MX
, EM
} },
2054 { "packuswb", { MX
, EM
} },
2056 { "punpckhbw", { MX
, EM
} },
2057 { "punpckhwd", { MX
, EM
} },
2058 { "punpckhdq", { MX
, EM
} },
2059 { "packssdw", { MX
, EM
} },
2060 { PREFIX_TABLE (PREFIX_0F6C
) },
2061 { PREFIX_TABLE (PREFIX_0F6D
) },
2062 { "movK", { MX
, Edq
} },
2063 { PREFIX_TABLE (PREFIX_0F6F
) },
2065 { PREFIX_TABLE (PREFIX_0F70
) },
2066 { REG_TABLE (REG_0F71
) },
2067 { REG_TABLE (REG_0F72
) },
2068 { REG_TABLE (REG_0F73
) },
2069 { "pcmpeqb", { MX
, EM
} },
2070 { "pcmpeqw", { MX
, EM
} },
2071 { "pcmpeqd", { MX
, EM
} },
2074 { PREFIX_TABLE (PREFIX_0F78
) },
2075 { PREFIX_TABLE (PREFIX_0F79
) },
2076 { THREE_BYTE_TABLE (THREE_BYTE_0F7A
) },
2078 { PREFIX_TABLE (PREFIX_0F7C
) },
2079 { PREFIX_TABLE (PREFIX_0F7D
) },
2080 { PREFIX_TABLE (PREFIX_0F7E
) },
2081 { PREFIX_TABLE (PREFIX_0F7F
) },
2083 { "joH", { Jv
, XX
, cond_jump_flag
} },
2084 { "jnoH", { Jv
, XX
, cond_jump_flag
} },
2085 { "jbH", { Jv
, XX
, cond_jump_flag
} },
2086 { "jaeH", { Jv
, XX
, cond_jump_flag
} },
2087 { "jeH", { Jv
, XX
, cond_jump_flag
} },
2088 { "jneH", { Jv
, XX
, cond_jump_flag
} },
2089 { "jbeH", { Jv
, XX
, cond_jump_flag
} },
2090 { "jaH", { Jv
, XX
, cond_jump_flag
} },
2092 { "jsH", { Jv
, XX
, cond_jump_flag
} },
2093 { "jnsH", { Jv
, XX
, cond_jump_flag
} },
2094 { "jpH", { Jv
, XX
, cond_jump_flag
} },
2095 { "jnpH", { Jv
, XX
, cond_jump_flag
} },
2096 { "jlH", { Jv
, XX
, cond_jump_flag
} },
2097 { "jgeH", { Jv
, XX
, cond_jump_flag
} },
2098 { "jleH", { Jv
, XX
, cond_jump_flag
} },
2099 { "jgH", { Jv
, XX
, cond_jump_flag
} },
2102 { "setno", { Eb
} },
2104 { "setae", { Eb
} },
2106 { "setne", { Eb
} },
2107 { "setbe", { Eb
} },
2111 { "setns", { Eb
} },
2113 { "setnp", { Eb
} },
2115 { "setge", { Eb
} },
2116 { "setle", { Eb
} },
2119 { "pushT", { fs
} },
2121 { "cpuid", { XX
} },
2122 { "btS", { Ev
, Gv
} },
2123 { "shldS", { Ev
, Gv
, Ib
} },
2124 { "shldS", { Ev
, Gv
, CL
} },
2125 { REG_TABLE (REG_0FA6
) },
2126 { REG_TABLE (REG_0FA7
) },
2128 { "pushT", { gs
} },
2131 { "btsS", { Ev
, Gv
} },
2132 { "shrdS", { Ev
, Gv
, Ib
} },
2133 { "shrdS", { Ev
, Gv
, CL
} },
2134 { REG_TABLE (REG_0FAE
) },
2135 { "imulS", { Gv
, Ev
} },
2137 { "cmpxchgB", { Eb
, Gb
} },
2138 { "cmpxchgS", { Ev
, Gv
} },
2139 { MOD_TABLE (MOD_0FB2
) },
2140 { "btrS", { Ev
, Gv
} },
2141 { MOD_TABLE (MOD_0FB4
) },
2142 { MOD_TABLE (MOD_0FB5
) },
2143 { "movz{bR|x}", { Gv
, Eb
} },
2144 { "movz{wR|x}", { Gv
, Ew
} }, /* yes, there really is movzww ! */
2146 { PREFIX_TABLE (PREFIX_0FB8
) },
2148 { REG_TABLE (REG_0FBA
) },
2149 { "btcS", { Ev
, Gv
} },
2150 { "bsfS", { Gv
, Ev
} },
2151 { PREFIX_TABLE (PREFIX_0FBD
) },
2152 { "movs{bR|x}", { Gv
, Eb
} },
2153 { "movs{wR|x}", { Gv
, Ew
} }, /* yes, there really is movsww ! */
2155 { "xaddB", { Eb
, Gb
} },
2156 { "xaddS", { Ev
, Gv
} },
2157 { PREFIX_TABLE (PREFIX_0FC2
) },
2158 { PREFIX_TABLE (PREFIX_0FC3
) },
2159 { "pinsrw", { MX
, Edqw
, Ib
} },
2160 { "pextrw", { Gdq
, MS
, Ib
} },
2161 { "shufpX", { XM
, EXx
, Ib
} },
2162 { REG_TABLE (REG_0FC7
) },
2164 { "bswap", { RMeAX
} },
2165 { "bswap", { RMeCX
} },
2166 { "bswap", { RMeDX
} },
2167 { "bswap", { RMeBX
} },
2168 { "bswap", { RMeSP
} },
2169 { "bswap", { RMeBP
} },
2170 { "bswap", { RMeSI
} },
2171 { "bswap", { RMeDI
} },
2173 { PREFIX_TABLE (PREFIX_0FD0
) },
2174 { "psrlw", { MX
, EM
} },
2175 { "psrld", { MX
, EM
} },
2176 { "psrlq", { MX
, EM
} },
2177 { "paddq", { MX
, EM
} },
2178 { "pmullw", { MX
, EM
} },
2179 { PREFIX_TABLE (PREFIX_0FD6
) },
2180 { MOD_TABLE (MOD_0FD7
) },
2182 { "psubusb", { MX
, EM
} },
2183 { "psubusw", { MX
, EM
} },
2184 { "pminub", { MX
, EM
} },
2185 { "pand", { MX
, EM
} },
2186 { "paddusb", { MX
, EM
} },
2187 { "paddusw", { MX
, EM
} },
2188 { "pmaxub", { MX
, EM
} },
2189 { "pandn", { MX
, EM
} },
2191 { "pavgb", { MX
, EM
} },
2192 { "psraw", { MX
, EM
} },
2193 { "psrad", { MX
, EM
} },
2194 { "pavgw", { MX
, EM
} },
2195 { "pmulhuw", { MX
, EM
} },
2196 { "pmulhw", { MX
, EM
} },
2197 { PREFIX_TABLE (PREFIX_0FE6
) },
2198 { PREFIX_TABLE (PREFIX_0FE7
) },
2200 { "psubsb", { MX
, EM
} },
2201 { "psubsw", { MX
, EM
} },
2202 { "pminsw", { MX
, EM
} },
2203 { "por", { MX
, EM
} },
2204 { "paddsb", { MX
, EM
} },
2205 { "paddsw", { MX
, EM
} },
2206 { "pmaxsw", { MX
, EM
} },
2207 { "pxor", { MX
, EM
} },
2209 { PREFIX_TABLE (PREFIX_0FF0
) },
2210 { "psllw", { MX
, EM
} },
2211 { "pslld", { MX
, EM
} },
2212 { "psllq", { MX
, EM
} },
2213 { "pmuludq", { MX
, EM
} },
2214 { "pmaddwd", { MX
, EM
} },
2215 { "psadbw", { MX
, EM
} },
2216 { PREFIX_TABLE (PREFIX_0FF7
) },
2218 { "psubb", { MX
, EM
} },
2219 { "psubw", { MX
, EM
} },
2220 { "psubd", { MX
, EM
} },
2221 { "psubq", { MX
, EM
} },
2222 { "paddb", { MX
, EM
} },
2223 { "paddw", { MX
, EM
} },
2224 { "paddd", { MX
, EM
} },
2228 static const unsigned char onebyte_has_modrm
[256] = {
2229 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2230 /* ------------------------------- */
2231 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2232 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2233 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2234 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2235 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2236 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2237 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2238 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2239 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2240 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2241 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2242 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2243 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2244 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2245 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2246 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
2247 /* ------------------------------- */
2248 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2251 static const unsigned char twobyte_has_modrm
[256] = {
2252 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2253 /* ------------------------------- */
2254 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2255 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2256 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2257 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2258 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2259 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2260 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2261 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2262 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2263 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2264 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2265 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
2266 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2267 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2268 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2269 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
2270 /* ------------------------------- */
2271 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2274 static char obuf
[100];
2276 static char *mnemonicendp
;
2277 static char scratchbuf
[100];
2278 static unsigned char *start_codep
;
2279 static unsigned char *insn_codep
;
2280 static unsigned char *codep
;
2281 static int last_lock_prefix
;
2282 static int last_repz_prefix
;
2283 static int last_repnz_prefix
;
2284 static int last_data_prefix
;
2285 static int last_addr_prefix
;
2286 static int last_rex_prefix
;
2287 static int last_seg_prefix
;
2288 #define MAX_CODE_LENGTH 15
2289 /* We can up to 14 prefixes since the maximum instruction length is
2291 static int all_prefixes
[MAX_CODE_LENGTH
- 1];
2292 static disassemble_info
*the_info
;
2300 static unsigned char need_modrm
;
2303 int register_specifier
;
2309 static unsigned char need_vex
;
2310 static unsigned char need_vex_reg
;
2311 static unsigned char vex_w_done
;
2319 /* If we are accessing mod/rm/reg without need_modrm set, then the
2320 values are stale. Hitting this abort likely indicates that you
2321 need to update onebyte_has_modrm or twobyte_has_modrm. */
2322 #define MODRM_CHECK if (!need_modrm) abort ()
2324 static const char **names64
;
2325 static const char **names32
;
2326 static const char **names16
;
2327 static const char **names8
;
2328 static const char **names8rex
;
2329 static const char **names_seg
;
2330 static const char *index64
;
2331 static const char *index32
;
2332 static const char **index16
;
2334 static const char *intel_names64
[] = {
2335 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2336 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2338 static const char *intel_names32
[] = {
2339 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
2340 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
2342 static const char *intel_names16
[] = {
2343 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
2344 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
2346 static const char *intel_names8
[] = {
2347 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2349 static const char *intel_names8rex
[] = {
2350 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2351 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2353 static const char *intel_names_seg
[] = {
2354 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2356 static const char *intel_index64
= "riz";
2357 static const char *intel_index32
= "eiz";
2358 static const char *intel_index16
[] = {
2359 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2362 static const char *att_names64
[] = {
2363 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2364 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2366 static const char *att_names32
[] = {
2367 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2368 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2370 static const char *att_names16
[] = {
2371 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2372 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2374 static const char *att_names8
[] = {
2375 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2377 static const char *att_names8rex
[] = {
2378 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2379 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2381 static const char *att_names_seg
[] = {
2382 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2384 static const char *att_index64
= "%riz";
2385 static const char *att_index32
= "%eiz";
2386 static const char *att_index16
[] = {
2387 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2390 static const char **names_mm
;
2391 static const char *intel_names_mm
[] = {
2392 "mm0", "mm1", "mm2", "mm3",
2393 "mm4", "mm5", "mm6", "mm7"
2395 static const char *att_names_mm
[] = {
2396 "%mm0", "%mm1", "%mm2", "%mm3",
2397 "%mm4", "%mm5", "%mm6", "%mm7"
2400 static const char **names_xmm
;
2401 static const char *intel_names_xmm
[] = {
2402 "xmm0", "xmm1", "xmm2", "xmm3",
2403 "xmm4", "xmm5", "xmm6", "xmm7",
2404 "xmm8", "xmm9", "xmm10", "xmm11",
2405 "xmm12", "xmm13", "xmm14", "xmm15"
2407 static const char *att_names_xmm
[] = {
2408 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
2409 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
2410 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
2411 "%xmm12", "%xmm13", "%xmm14", "%xmm15"
2414 static const char **names_ymm
;
2415 static const char *intel_names_ymm
[] = {
2416 "ymm0", "ymm1", "ymm2", "ymm3",
2417 "ymm4", "ymm5", "ymm6", "ymm7",
2418 "ymm8", "ymm9", "ymm10", "ymm11",
2419 "ymm12", "ymm13", "ymm14", "ymm15"
2421 static const char *att_names_ymm
[] = {
2422 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
2423 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
2424 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
2425 "%ymm12", "%ymm13", "%ymm14", "%ymm15"
2428 static const struct dis386 reg_table
[][8] = {
2431 { "addA", { Eb
, Ib
} },
2432 { "orA", { Eb
, Ib
} },
2433 { "adcA", { Eb
, Ib
} },
2434 { "sbbA", { Eb
, Ib
} },
2435 { "andA", { Eb
, Ib
} },
2436 { "subA", { Eb
, Ib
} },
2437 { "xorA", { Eb
, Ib
} },
2438 { "cmpA", { Eb
, Ib
} },
2442 { "addQ", { Ev
, Iv
} },
2443 { "orQ", { Ev
, Iv
} },
2444 { "adcQ", { Ev
, Iv
} },
2445 { "sbbQ", { Ev
, Iv
} },
2446 { "andQ", { Ev
, Iv
} },
2447 { "subQ", { Ev
, Iv
} },
2448 { "xorQ", { Ev
, Iv
} },
2449 { "cmpQ", { Ev
, Iv
} },
2453 { "addQ", { Ev
, sIb
} },
2454 { "orQ", { Ev
, sIb
} },
2455 { "adcQ", { Ev
, sIb
} },
2456 { "sbbQ", { Ev
, sIb
} },
2457 { "andQ", { Ev
, sIb
} },
2458 { "subQ", { Ev
, sIb
} },
2459 { "xorQ", { Ev
, sIb
} },
2460 { "cmpQ", { Ev
, sIb
} },
2464 { "popU", { stackEv
} },
2465 { XOP_8F_TABLE (XOP_09
) },
2469 { XOP_8F_TABLE (XOP_09
) },
2473 { "rolA", { Eb
, Ib
} },
2474 { "rorA", { Eb
, Ib
} },
2475 { "rclA", { Eb
, Ib
} },
2476 { "rcrA", { Eb
, Ib
} },
2477 { "shlA", { Eb
, Ib
} },
2478 { "shrA", { Eb
, Ib
} },
2480 { "sarA", { Eb
, Ib
} },
2484 { "rolQ", { Ev
, Ib
} },
2485 { "rorQ", { Ev
, Ib
} },
2486 { "rclQ", { Ev
, Ib
} },
2487 { "rcrQ", { Ev
, Ib
} },
2488 { "shlQ", { Ev
, Ib
} },
2489 { "shrQ", { Ev
, Ib
} },
2491 { "sarQ", { Ev
, Ib
} },
2495 { "movA", { Eb
, Ib
} },
2499 { "movQ", { Ev
, Iv
} },
2503 { "rolA", { Eb
, I1
} },
2504 { "rorA", { Eb
, I1
} },
2505 { "rclA", { Eb
, I1
} },
2506 { "rcrA", { Eb
, I1
} },
2507 { "shlA", { Eb
, I1
} },
2508 { "shrA", { Eb
, I1
} },
2510 { "sarA", { Eb
, I1
} },
2514 { "rolQ", { Ev
, I1
} },
2515 { "rorQ", { Ev
, I1
} },
2516 { "rclQ", { Ev
, I1
} },
2517 { "rcrQ", { Ev
, I1
} },
2518 { "shlQ", { Ev
, I1
} },
2519 { "shrQ", { Ev
, I1
} },
2521 { "sarQ", { Ev
, I1
} },
2525 { "rolA", { Eb
, CL
} },
2526 { "rorA", { Eb
, CL
} },
2527 { "rclA", { Eb
, CL
} },
2528 { "rcrA", { Eb
, CL
} },
2529 { "shlA", { Eb
, CL
} },
2530 { "shrA", { Eb
, CL
} },
2532 { "sarA", { Eb
, CL
} },
2536 { "rolQ", { Ev
, CL
} },
2537 { "rorQ", { Ev
, CL
} },
2538 { "rclQ", { Ev
, CL
} },
2539 { "rcrQ", { Ev
, CL
} },
2540 { "shlQ", { Ev
, CL
} },
2541 { "shrQ", { Ev
, CL
} },
2543 { "sarQ", { Ev
, CL
} },
2547 { "testA", { Eb
, Ib
} },
2551 { "mulA", { Eb
} }, /* Don't print the implicit %al register, */
2552 { "imulA", { Eb
} }, /* to distinguish these opcodes from other */
2553 { "divA", { Eb
} }, /* mul/imul opcodes. Do the same for div */
2554 { "idivA", { Eb
} }, /* and idiv for consistency. */
2558 { "testQ", { Ev
, Iv
} },
2562 { "mulQ", { Ev
} }, /* Don't print the implicit register. */
2563 { "imulQ", { Ev
} },
2565 { "idivQ", { Ev
} },
2576 { "callT", { indirEv
} },
2577 { "JcallT", { indirEp
} },
2578 { "jmpT", { indirEv
} },
2579 { "JjmpT", { indirEp
} },
2580 { "pushU", { stackEv
} },
2585 { "sldtD", { Sv
} },
2596 { MOD_TABLE (MOD_0F01_REG_0
) },
2597 { MOD_TABLE (MOD_0F01_REG_1
) },
2598 { MOD_TABLE (MOD_0F01_REG_2
) },
2599 { MOD_TABLE (MOD_0F01_REG_3
) },
2600 { "smswD", { Sv
} },
2603 { MOD_TABLE (MOD_0F01_REG_7
) },
2607 { "prefetch", { Eb
} },
2608 { "prefetchw", { Eb
} },
2612 { MOD_TABLE (MOD_0F18_REG_0
) },
2613 { MOD_TABLE (MOD_0F18_REG_1
) },
2614 { MOD_TABLE (MOD_0F18_REG_2
) },
2615 { MOD_TABLE (MOD_0F18_REG_3
) },
2621 { MOD_TABLE (MOD_0F71_REG_2
) },
2623 { MOD_TABLE (MOD_0F71_REG_4
) },
2625 { MOD_TABLE (MOD_0F71_REG_6
) },
2631 { MOD_TABLE (MOD_0F72_REG_2
) },
2633 { MOD_TABLE (MOD_0F72_REG_4
) },
2635 { MOD_TABLE (MOD_0F72_REG_6
) },
2641 { MOD_TABLE (MOD_0F73_REG_2
) },
2642 { MOD_TABLE (MOD_0F73_REG_3
) },
2645 { MOD_TABLE (MOD_0F73_REG_6
) },
2646 { MOD_TABLE (MOD_0F73_REG_7
) },
2650 { "montmul", { { OP_0f07
, 0 } } },
2651 { "xsha1", { { OP_0f07
, 0 } } },
2652 { "xsha256", { { OP_0f07
, 0 } } },
2656 { "xstore-rng", { { OP_0f07
, 0 } } },
2657 { "xcrypt-ecb", { { OP_0f07
, 0 } } },
2658 { "xcrypt-cbc", { { OP_0f07
, 0 } } },
2659 { "xcrypt-ctr", { { OP_0f07
, 0 } } },
2660 { "xcrypt-cfb", { { OP_0f07
, 0 } } },
2661 { "xcrypt-ofb", { { OP_0f07
, 0 } } },
2665 { MOD_TABLE (MOD_0FAE_REG_0
) },
2666 { MOD_TABLE (MOD_0FAE_REG_1
) },
2667 { MOD_TABLE (MOD_0FAE_REG_2
) },
2668 { MOD_TABLE (MOD_0FAE_REG_3
) },
2669 { MOD_TABLE (MOD_0FAE_REG_4
) },
2670 { MOD_TABLE (MOD_0FAE_REG_5
) },
2671 { MOD_TABLE (MOD_0FAE_REG_6
) },
2672 { MOD_TABLE (MOD_0FAE_REG_7
) },
2680 { "btQ", { Ev
, Ib
} },
2681 { "btsQ", { Ev
, Ib
} },
2682 { "btrQ", { Ev
, Ib
} },
2683 { "btcQ", { Ev
, Ib
} },
2688 { "cmpxchg8b", { { CMPXCHG8B_Fixup
, q_mode
} } },
2693 { MOD_TABLE (MOD_0FC7_REG_6
) },
2694 { MOD_TABLE (MOD_0FC7_REG_7
) },
2700 { MOD_TABLE (MOD_VEX_71_REG_2
) },
2702 { MOD_TABLE (MOD_VEX_71_REG_4
) },
2704 { MOD_TABLE (MOD_VEX_71_REG_6
) },
2710 { MOD_TABLE (MOD_VEX_72_REG_2
) },
2712 { MOD_TABLE (MOD_VEX_72_REG_4
) },
2714 { MOD_TABLE (MOD_VEX_72_REG_6
) },
2720 { MOD_TABLE (MOD_VEX_73_REG_2
) },
2721 { MOD_TABLE (MOD_VEX_73_REG_3
) },
2724 { MOD_TABLE (MOD_VEX_73_REG_6
) },
2725 { MOD_TABLE (MOD_VEX_73_REG_7
) },
2731 { MOD_TABLE (MOD_VEX_AE_REG_2
) },
2732 { MOD_TABLE (MOD_VEX_AE_REG_3
) },
2736 { "llwpcb", { { OP_LWPCB_E
, 0 } } },
2737 { "slwpcb", { { OP_LWPCB_E
, 0 } } },
2741 { "lwpins", { { OP_LWP_E
, 0 }, Ed
, { OP_LWP_I
, 0 } } },
2742 { "lwpval", { { OP_LWP_E
, 0 }, Ed
, { OP_LWP_I
, 0 } } },
2746 static const struct dis386 prefix_table
[][4] = {
2749 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} } },
2750 { "pause", { XX
} },
2751 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} } },
2756 { "movups", { XM
, EXx
} },
2757 { "movss", { XM
, EXd
} },
2758 { "movupd", { XM
, EXx
} },
2759 { "movsd", { XM
, EXq
} },
2764 { "movups", { EXxS
, XM
} },
2765 { "movss", { EXdS
, XM
} },
2766 { "movupd", { EXxS
, XM
} },
2767 { "movsd", { EXqS
, XM
} },
2772 { MOD_TABLE (MOD_0F12_PREFIX_0
) },
2773 { "movsldup", { XM
, EXx
} },
2774 { "movlpd", { XM
, EXq
} },
2775 { "movddup", { XM
, EXq
} },
2780 { MOD_TABLE (MOD_0F16_PREFIX_0
) },
2781 { "movshdup", { XM
, EXx
} },
2782 { "movhpd", { XM
, EXq
} },
2787 { "cvtpi2ps", { XM
, EMCq
} },
2788 { "cvtsi2ss%LQ", { XM
, Ev
} },
2789 { "cvtpi2pd", { XM
, EMCq
} },
2790 { "cvtsi2sd%LQ", { XM
, Ev
} },
2795 { MOD_TABLE (MOD_0F2B_PREFIX_0
) },
2796 { MOD_TABLE (MOD_0F2B_PREFIX_1
) },
2797 { MOD_TABLE (MOD_0F2B_PREFIX_2
) },
2798 { MOD_TABLE (MOD_0F2B_PREFIX_3
) },
2803 { "cvttps2pi", { MXC
, EXq
} },
2804 { "cvttss2siY", { Gv
, EXd
} },
2805 { "cvttpd2pi", { MXC
, EXx
} },
2806 { "cvttsd2siY", { Gv
, EXq
} },
2811 { "cvtps2pi", { MXC
, EXq
} },
2812 { "cvtss2siY", { Gv
, EXd
} },
2813 { "cvtpd2pi", { MXC
, EXx
} },
2814 { "cvtsd2siY", { Gv
, EXq
} },
2819 { "ucomiss",{ XM
, EXd
} },
2821 { "ucomisd",{ XM
, EXq
} },
2826 { "comiss", { XM
, EXd
} },
2828 { "comisd", { XM
, EXq
} },
2833 { "sqrtps", { XM
, EXx
} },
2834 { "sqrtss", { XM
, EXd
} },
2835 { "sqrtpd", { XM
, EXx
} },
2836 { "sqrtsd", { XM
, EXq
} },
2841 { "rsqrtps",{ XM
, EXx
} },
2842 { "rsqrtss",{ XM
, EXd
} },
2847 { "rcpps", { XM
, EXx
} },
2848 { "rcpss", { XM
, EXd
} },
2853 { "addps", { XM
, EXx
} },
2854 { "addss", { XM
, EXd
} },
2855 { "addpd", { XM
, EXx
} },
2856 { "addsd", { XM
, EXq
} },
2861 { "mulps", { XM
, EXx
} },
2862 { "mulss", { XM
, EXd
} },
2863 { "mulpd", { XM
, EXx
} },
2864 { "mulsd", { XM
, EXq
} },
2869 { "cvtps2pd", { XM
, EXq
} },
2870 { "cvtss2sd", { XM
, EXd
} },
2871 { "cvtpd2ps", { XM
, EXx
} },
2872 { "cvtsd2ss", { XM
, EXq
} },
2877 { "cvtdq2ps", { XM
, EXx
} },
2878 { "cvttps2dq", { XM
, EXx
} },
2879 { "cvtps2dq", { XM
, EXx
} },
2884 { "subps", { XM
, EXx
} },
2885 { "subss", { XM
, EXd
} },
2886 { "subpd", { XM
, EXx
} },
2887 { "subsd", { XM
, EXq
} },
2892 { "minps", { XM
, EXx
} },
2893 { "minss", { XM
, EXd
} },
2894 { "minpd", { XM
, EXx
} },
2895 { "minsd", { XM
, EXq
} },
2900 { "divps", { XM
, EXx
} },
2901 { "divss", { XM
, EXd
} },
2902 { "divpd", { XM
, EXx
} },
2903 { "divsd", { XM
, EXq
} },
2908 { "maxps", { XM
, EXx
} },
2909 { "maxss", { XM
, EXd
} },
2910 { "maxpd", { XM
, EXx
} },
2911 { "maxsd", { XM
, EXq
} },
2916 { "punpcklbw",{ MX
, EMd
} },
2918 { "punpcklbw",{ MX
, EMx
} },
2923 { "punpcklwd",{ MX
, EMd
} },
2925 { "punpcklwd",{ MX
, EMx
} },
2930 { "punpckldq",{ MX
, EMd
} },
2932 { "punpckldq",{ MX
, EMx
} },
2939 { "punpcklqdq", { XM
, EXx
} },
2946 { "punpckhqdq", { XM
, EXx
} },
2951 { "movq", { MX
, EM
} },
2952 { "movdqu", { XM
, EXx
} },
2953 { "movdqa", { XM
, EXx
} },
2958 { "pshufw", { MX
, EM
, Ib
} },
2959 { "pshufhw",{ XM
, EXx
, Ib
} },
2960 { "pshufd", { XM
, EXx
, Ib
} },
2961 { "pshuflw",{ XM
, EXx
, Ib
} },
2964 /* PREFIX_0F73_REG_3 */
2968 { "psrldq", { XS
, Ib
} },
2971 /* PREFIX_0F73_REG_7 */
2975 { "pslldq", { XS
, Ib
} },
2980 {"vmread", { Em
, Gm
} },
2982 {"extrq", { XS
, Ib
, Ib
} },
2983 {"insertq", { XM
, XS
, Ib
, Ib
} },
2988 {"vmwrite", { Gm
, Em
} },
2990 {"extrq", { XM
, XS
} },
2991 {"insertq", { XM
, XS
} },
2998 { "haddpd", { XM
, EXx
} },
2999 { "haddps", { XM
, EXx
} },
3006 { "hsubpd", { XM
, EXx
} },
3007 { "hsubps", { XM
, EXx
} },
3012 { "movK", { Edq
, MX
} },
3013 { "movq", { XM
, EXq
} },
3014 { "movK", { Edq
, XM
} },
3019 { "movq", { EMS
, MX
} },
3020 { "movdqu", { EXxS
, XM
} },
3021 { "movdqa", { EXxS
, XM
} },
3027 { "popcntS", { Gv
, Ev
} },
3032 { "bsrS", { Gv
, Ev
} },
3033 { "lzcntS", { Gv
, Ev
} },
3034 { "bsrS", { Gv
, Ev
} },
3039 { "cmpps", { XM
, EXx
, CMP
} },
3040 { "cmpss", { XM
, EXd
, CMP
} },
3041 { "cmppd", { XM
, EXx
, CMP
} },
3042 { "cmpsd", { XM
, EXq
, CMP
} },
3047 { "movntiS", { Ma
, Gv
} },
3050 /* PREFIX_0FC7_REG_6 */
3052 { "vmptrld",{ Mq
} },
3053 { "vmxon", { Mq
} },
3054 { "vmclear",{ Mq
} },
3061 { "addsubpd", { XM
, EXx
} },
3062 { "addsubps", { XM
, EXx
} },
3068 { "movq2dq",{ XM
, MS
} },
3069 { "movq", { EXqS
, XM
} },
3070 { "movdq2q",{ MX
, XS
} },
3076 { "cvtdq2pd", { XM
, EXq
} },
3077 { "cvttpd2dq", { XM
, EXx
} },
3078 { "cvtpd2dq", { XM
, EXx
} },
3083 { "movntq", { Mq
, MX
} },
3085 { MOD_TABLE (MOD_0FE7_PREFIX_2
) },
3093 { MOD_TABLE (MOD_0FF0_PREFIX_3
) },
3098 { "maskmovq", { MX
, MS
} },
3100 { "maskmovdqu", { XM
, XS
} },
3107 { "pblendvb", { XM
, EXx
, XMM0
} },
3114 { "blendvps", { XM
, EXx
, XMM0
} },
3121 { "blendvpd", { XM
, EXx
, XMM0
} },
3128 { "ptest", { XM
, EXx
} },
3135 { "pmovsxbw", { XM
, EXq
} },
3142 { "pmovsxbd", { XM
, EXd
} },
3149 { "pmovsxbq", { XM
, EXw
} },
3156 { "pmovsxwd", { XM
, EXq
} },
3163 { "pmovsxwq", { XM
, EXd
} },
3170 { "pmovsxdq", { XM
, EXq
} },
3177 { "pmuldq", { XM
, EXx
} },
3184 { "pcmpeqq", { XM
, EXx
} },
3191 { MOD_TABLE (MOD_0F382A_PREFIX_2
) },
3198 { "packusdw", { XM
, EXx
} },
3205 { "pmovzxbw", { XM
, EXq
} },
3212 { "pmovzxbd", { XM
, EXd
} },
3219 { "pmovzxbq", { XM
, EXw
} },
3226 { "pmovzxwd", { XM
, EXq
} },
3233 { "pmovzxwq", { XM
, EXd
} },
3240 { "pmovzxdq", { XM
, EXq
} },
3247 { "pcmpgtq", { XM
, EXx
} },
3254 { "pminsb", { XM
, EXx
} },
3261 { "pminsd", { XM
, EXx
} },
3268 { "pminuw", { XM
, EXx
} },
3275 { "pminud", { XM
, EXx
} },
3282 { "pmaxsb", { XM
, EXx
} },
3289 { "pmaxsd", { XM
, EXx
} },
3296 { "pmaxuw", { XM
, EXx
} },
3303 { "pmaxud", { XM
, EXx
} },
3310 { "pmulld", { XM
, EXx
} },
3317 { "phminposuw", { XM
, EXx
} },
3324 { "invept", { Gm
, Mo
} },
3331 { "invvpid", { Gm
, Mo
} },
3338 { "aesimc", { XM
, EXx
} },
3345 { "aesenc", { XM
, EXx
} },
3352 { "aesenclast", { XM
, EXx
} },
3359 { "aesdec", { XM
, EXx
} },
3366 { "aesdeclast", { XM
, EXx
} },
3371 { "movbeS", { Gv
, { MOVBE_Fixup
, v_mode
} } },
3373 { "movbeS", { Gv
, { MOVBE_Fixup
, v_mode
} } },
3374 { "crc32", { Gdq
, { CRC32_Fixup
, b_mode
} } },
3379 { "movbeS", { { MOVBE_Fixup
, v_mode
}, Gv
} },
3381 { "movbeS", { { MOVBE_Fixup
, v_mode
}, Gv
} },
3382 { "crc32", { Gdq
, { CRC32_Fixup
, v_mode
} } },
3389 { "roundps", { XM
, EXx
, Ib
} },
3396 { "roundpd", { XM
, EXx
, Ib
} },
3403 { "roundss", { XM
, EXd
, Ib
} },
3410 { "roundsd", { XM
, EXq
, Ib
} },
3417 { "blendps", { XM
, EXx
, Ib
} },
3424 { "blendpd", { XM
, EXx
, Ib
} },
3431 { "pblendw", { XM
, EXx
, Ib
} },
3438 { "pextrb", { Edqb
, XM
, Ib
} },
3445 { "pextrw", { Edqw
, XM
, Ib
} },
3452 { "pextrK", { Edq
, XM
, Ib
} },
3459 { "extractps", { Edqd
, XM
, Ib
} },
3466 { "pinsrb", { XM
, Edqb
, Ib
} },
3473 { "insertps", { XM
, EXd
, Ib
} },
3480 { "pinsrK", { XM
, Edq
, Ib
} },
3487 { "dpps", { XM
, EXx
, Ib
} },
3494 { "dppd", { XM
, EXx
, Ib
} },
3501 { "mpsadbw", { XM
, EXx
, Ib
} },
3508 { "pclmulqdq", { XM
, EXx
, PCLMUL
} },
3515 { "pcmpestrm", { XM
, EXx
, Ib
} },
3522 { "pcmpestri", { XM
, EXx
, Ib
} },
3529 { "pcmpistrm", { XM
, EXx
, Ib
} },
3536 { "pcmpistri", { XM
, EXx
, Ib
} },
3543 { "aeskeygenassist", { XM
, EXx
, Ib
} },
3548 { VEX_W_TABLE (VEX_W_10_P_0
) },
3549 { VEX_LEN_TABLE (VEX_LEN_10_P_1
) },
3550 { VEX_W_TABLE (VEX_W_10_P_2
) },
3551 { VEX_LEN_TABLE (VEX_LEN_10_P_3
) },
3556 { VEX_W_TABLE (VEX_W_11_P_0
) },
3557 { VEX_LEN_TABLE (VEX_LEN_11_P_1
) },
3558 { VEX_W_TABLE (VEX_W_11_P_2
) },
3559 { VEX_LEN_TABLE (VEX_LEN_11_P_3
) },
3564 { MOD_TABLE (MOD_VEX_12_PREFIX_0
) },
3565 { VEX_W_TABLE (VEX_W_12_P_1
) },
3566 { VEX_LEN_TABLE (VEX_LEN_12_P_2
) },
3567 { VEX_W_TABLE (VEX_W_12_P_3
) },
3572 { MOD_TABLE (MOD_VEX_16_PREFIX_0
) },
3573 { VEX_W_TABLE (VEX_W_16_P_1
) },
3574 { VEX_LEN_TABLE (VEX_LEN_16_P_2
) },
3580 { VEX_LEN_TABLE (VEX_LEN_2A_P_1
) },
3582 { VEX_LEN_TABLE (VEX_LEN_2A_P_3
) },
3588 { VEX_LEN_TABLE (VEX_LEN_2C_P_1
) },
3590 { VEX_LEN_TABLE (VEX_LEN_2C_P_3
) },
3596 { VEX_LEN_TABLE (VEX_LEN_2D_P_1
) },
3598 { VEX_LEN_TABLE (VEX_LEN_2D_P_3
) },
3603 { VEX_LEN_TABLE (VEX_LEN_2E_P_0
) },
3605 { VEX_LEN_TABLE (VEX_LEN_2E_P_2
) },
3610 { VEX_LEN_TABLE (VEX_LEN_2F_P_0
) },
3612 { VEX_LEN_TABLE (VEX_LEN_2F_P_2
) },
3617 { VEX_W_TABLE (VEX_W_51_P_0
) },
3618 { VEX_LEN_TABLE (VEX_LEN_51_P_1
) },
3619 { VEX_W_TABLE (VEX_W_51_P_2
) },
3620 { VEX_LEN_TABLE (VEX_LEN_51_P_3
) },
3625 { VEX_W_TABLE (VEX_W_52_P_0
) },
3626 { VEX_LEN_TABLE (VEX_LEN_52_P_1
) },
3631 { VEX_W_TABLE (VEX_W_53_P_0
) },
3632 { VEX_LEN_TABLE (VEX_LEN_53_P_1
) },
3637 { VEX_W_TABLE (VEX_W_58_P_0
) },
3638 { VEX_LEN_TABLE (VEX_LEN_58_P_1
) },
3639 { VEX_W_TABLE (VEX_W_58_P_2
) },
3640 { VEX_LEN_TABLE (VEX_LEN_58_P_3
) },
3645 { VEX_W_TABLE (VEX_W_59_P_0
) },
3646 { VEX_LEN_TABLE (VEX_LEN_59_P_1
) },
3647 { VEX_W_TABLE (VEX_W_59_P_2
) },
3648 { VEX_LEN_TABLE (VEX_LEN_59_P_3
) },
3653 { VEX_W_TABLE (VEX_W_5A_P_0
) },
3654 { VEX_LEN_TABLE (VEX_LEN_5A_P_1
) },
3655 { "vcvtpd2ps%XY", { XMM
, EXx
} },
3656 { VEX_LEN_TABLE (VEX_LEN_5A_P_3
) },
3661 { VEX_W_TABLE (VEX_W_5B_P_0
) },
3662 { VEX_W_TABLE (VEX_W_5B_P_1
) },
3663 { VEX_W_TABLE (VEX_W_5B_P_2
) },
3668 { VEX_W_TABLE (VEX_W_5C_P_0
) },
3669 { VEX_LEN_TABLE (VEX_LEN_5C_P_1
) },
3670 { VEX_W_TABLE (VEX_W_5C_P_2
) },
3671 { VEX_LEN_TABLE (VEX_LEN_5C_P_3
) },
3676 { VEX_W_TABLE (VEX_W_5D_P_0
) },
3677 { VEX_LEN_TABLE (VEX_LEN_5D_P_1
) },
3678 { VEX_W_TABLE (VEX_W_5D_P_2
) },
3679 { VEX_LEN_TABLE (VEX_LEN_5D_P_3
) },
3684 { VEX_W_TABLE (VEX_W_5E_P_0
) },
3685 { VEX_LEN_TABLE (VEX_LEN_5E_P_1
) },
3686 { VEX_W_TABLE (VEX_W_5E_P_2
) },
3687 { VEX_LEN_TABLE (VEX_LEN_5E_P_3
) },
3692 { VEX_W_TABLE (VEX_W_5F_P_0
) },
3693 { VEX_LEN_TABLE (VEX_LEN_5F_P_1
) },
3694 { VEX_W_TABLE (VEX_W_5F_P_2
) },
3695 { VEX_LEN_TABLE (VEX_LEN_5F_P_3
) },
3702 { VEX_LEN_TABLE (VEX_LEN_60_P_2
) },
3709 { VEX_LEN_TABLE (VEX_LEN_61_P_2
) },
3716 { VEX_LEN_TABLE (VEX_LEN_62_P_2
) },
3723 { VEX_LEN_TABLE (VEX_LEN_63_P_2
) },
3730 { VEX_LEN_TABLE (VEX_LEN_64_P_2
) },
3737 { VEX_LEN_TABLE (VEX_LEN_65_P_2
) },
3744 { VEX_LEN_TABLE (VEX_LEN_66_P_2
) },
3751 { VEX_LEN_TABLE (VEX_LEN_67_P_2
) },
3758 { VEX_LEN_TABLE (VEX_LEN_68_P_2
) },
3765 { VEX_LEN_TABLE (VEX_LEN_69_P_2
) },
3772 { VEX_LEN_TABLE (VEX_LEN_6A_P_2
) },
3779 { VEX_LEN_TABLE (VEX_LEN_6B_P_2
) },
3786 { VEX_LEN_TABLE (VEX_LEN_6C_P_2
) },
3793 { VEX_LEN_TABLE (VEX_LEN_6D_P_2
) },
3800 { VEX_LEN_TABLE (VEX_LEN_6E_P_2
) },
3806 { VEX_W_TABLE (VEX_W_6F_P_1
) },
3807 { VEX_W_TABLE (VEX_W_6F_P_2
) },
3813 { VEX_LEN_TABLE (VEX_LEN_70_P_1
) },
3814 { VEX_LEN_TABLE (VEX_LEN_70_P_2
) },
3815 { VEX_LEN_TABLE (VEX_LEN_70_P_3
) },
3818 /* PREFIX_VEX_71_REG_2 */
3822 { VEX_LEN_TABLE (VEX_LEN_71_R_2_P_2
) },
3825 /* PREFIX_VEX_71_REG_4 */
3829 { VEX_LEN_TABLE (VEX_LEN_71_R_4_P_2
) },
3832 /* PREFIX_VEX_71_REG_6 */
3836 { VEX_LEN_TABLE (VEX_LEN_71_R_6_P_2
) },
3839 /* PREFIX_VEX_72_REG_2 */
3843 { VEX_LEN_TABLE (VEX_LEN_72_R_2_P_2
) },
3846 /* PREFIX_VEX_72_REG_4 */
3850 { VEX_LEN_TABLE (VEX_LEN_72_R_4_P_2
) },
3853 /* PREFIX_VEX_72_REG_6 */
3857 { VEX_LEN_TABLE (VEX_LEN_72_R_6_P_2
) },
3860 /* PREFIX_VEX_73_REG_2 */
3864 { VEX_LEN_TABLE (VEX_LEN_73_R_2_P_2
) },
3867 /* PREFIX_VEX_73_REG_3 */
3871 { VEX_LEN_TABLE (VEX_LEN_73_R_3_P_2
) },
3874 /* PREFIX_VEX_73_REG_6 */
3878 { VEX_LEN_TABLE (VEX_LEN_73_R_6_P_2
) },
3881 /* PREFIX_VEX_73_REG_7 */
3885 { VEX_LEN_TABLE (VEX_LEN_73_R_7_P_2
) },
3892 { VEX_LEN_TABLE (VEX_LEN_74_P_2
) },
3899 { VEX_LEN_TABLE (VEX_LEN_75_P_2
) },
3906 { VEX_LEN_TABLE (VEX_LEN_76_P_2
) },
3911 { VEX_W_TABLE (VEX_W_77_P_0
) },
3918 { VEX_W_TABLE (VEX_W_7C_P_2
) },
3919 { VEX_W_TABLE (VEX_W_7C_P_3
) },
3926 { VEX_W_TABLE (VEX_W_7D_P_2
) },
3927 { VEX_W_TABLE (VEX_W_7D_P_3
) },
3933 { VEX_LEN_TABLE (VEX_LEN_7E_P_1
) },
3934 { VEX_LEN_TABLE (VEX_LEN_7E_P_2
) },
3940 { VEX_W_TABLE (VEX_W_7F_P_1
) },
3941 { VEX_W_TABLE (VEX_W_7F_P_2
) },
3946 { VEX_W_TABLE (VEX_W_C2_P_0
) },
3947 { VEX_LEN_TABLE (VEX_LEN_C2_P_1
) },
3948 { VEX_W_TABLE (VEX_W_C2_P_2
) },
3949 { VEX_LEN_TABLE (VEX_LEN_C2_P_3
) },
3956 { VEX_LEN_TABLE (VEX_LEN_C4_P_2
) },
3963 { VEX_LEN_TABLE (VEX_LEN_C5_P_2
) },
3970 { VEX_W_TABLE (VEX_W_D0_P_2
) },
3971 { VEX_W_TABLE (VEX_W_D0_P_3
) },
3978 { VEX_LEN_TABLE (VEX_LEN_D1_P_2
) },
3985 { VEX_LEN_TABLE (VEX_LEN_D2_P_2
) },
3992 { VEX_LEN_TABLE (VEX_LEN_D3_P_2
) },
3999 { VEX_LEN_TABLE (VEX_LEN_D4_P_2
) },
4006 { VEX_LEN_TABLE (VEX_LEN_D5_P_2
) },
4013 { VEX_LEN_TABLE (VEX_LEN_D6_P_2
) },
4020 { MOD_TABLE (MOD_VEX_D7_PREFIX_2
) },
4027 { VEX_LEN_TABLE (VEX_LEN_D8_P_2
) },
4034 { VEX_LEN_TABLE (VEX_LEN_D9_P_2
) },
4041 { VEX_LEN_TABLE (VEX_LEN_DA_P_2
) },
4048 { VEX_LEN_TABLE (VEX_LEN_DB_P_2
) },
4055 { VEX_LEN_TABLE (VEX_LEN_DC_P_2
) },
4062 { VEX_LEN_TABLE (VEX_LEN_DD_P_2
) },
4069 { VEX_LEN_TABLE (VEX_LEN_DE_P_2
) },
4076 { VEX_LEN_TABLE (VEX_LEN_DF_P_2
) },
4083 { VEX_LEN_TABLE (VEX_LEN_E0_P_2
) },
4090 { VEX_LEN_TABLE (VEX_LEN_E1_P_2
) },
4097 { VEX_LEN_TABLE (VEX_LEN_E2_P_2
) },
4104 { VEX_LEN_TABLE (VEX_LEN_E3_P_2
) },
4111 { VEX_LEN_TABLE (VEX_LEN_E4_P_2
) },
4118 { VEX_LEN_TABLE (VEX_LEN_E5_P_2
) },
4124 { VEX_W_TABLE (VEX_W_E6_P_1
) },
4125 { VEX_W_TABLE (VEX_W_E6_P_2
) },
4126 { VEX_W_TABLE (VEX_W_E6_P_3
) },
4133 { MOD_TABLE (MOD_VEX_E7_PREFIX_2
) },
4140 { VEX_LEN_TABLE (VEX_LEN_E8_P_2
) },
4147 { VEX_LEN_TABLE (VEX_LEN_E9_P_2
) },
4154 { VEX_LEN_TABLE (VEX_LEN_EA_P_2
) },
4161 { VEX_LEN_TABLE (VEX_LEN_EB_P_2
) },
4168 { VEX_LEN_TABLE (VEX_LEN_EC_P_2
) },
4175 { VEX_LEN_TABLE (VEX_LEN_ED_P_2
) },
4182 { VEX_LEN_TABLE (VEX_LEN_EE_P_2
) },
4189 { VEX_LEN_TABLE (VEX_LEN_EF_P_2
) },
4197 { MOD_TABLE (MOD_VEX_F0_PREFIX_3
) },
4204 { VEX_LEN_TABLE (VEX_LEN_F1_P_2
) },
4211 { VEX_LEN_TABLE (VEX_LEN_F2_P_2
) },
4218 { VEX_LEN_TABLE (VEX_LEN_F3_P_2
) },
4225 { VEX_LEN_TABLE (VEX_LEN_F4_P_2
) },
4232 { VEX_LEN_TABLE (VEX_LEN_F5_P_2
) },
4239 { VEX_LEN_TABLE (VEX_LEN_F6_P_2
) },
4246 { VEX_LEN_TABLE (VEX_LEN_F7_P_2
) },
4253 { VEX_LEN_TABLE (VEX_LEN_F8_P_2
) },
4260 { VEX_LEN_TABLE (VEX_LEN_F9_P_2
) },
4267 { VEX_LEN_TABLE (VEX_LEN_FA_P_2
) },
4274 { VEX_LEN_TABLE (VEX_LEN_FB_P_2
) },
4281 { VEX_LEN_TABLE (VEX_LEN_FC_P_2
) },
4288 { VEX_LEN_TABLE (VEX_LEN_FD_P_2
) },
4295 { VEX_LEN_TABLE (VEX_LEN_FE_P_2
) },
4298 /* PREFIX_VEX_3800 */
4302 { VEX_LEN_TABLE (VEX_LEN_3800_P_2
) },
4305 /* PREFIX_VEX_3801 */
4309 { VEX_LEN_TABLE (VEX_LEN_3801_P_2
) },
4312 /* PREFIX_VEX_3802 */
4316 { VEX_LEN_TABLE (VEX_LEN_3802_P_2
) },
4319 /* PREFIX_VEX_3803 */
4323 { VEX_LEN_TABLE (VEX_LEN_3803_P_2
) },
4326 /* PREFIX_VEX_3804 */
4330 { VEX_LEN_TABLE (VEX_LEN_3804_P_2
) },
4333 /* PREFIX_VEX_3805 */
4337 { VEX_LEN_TABLE (VEX_LEN_3805_P_2
) },
4340 /* PREFIX_VEX_3806 */
4344 { VEX_LEN_TABLE (VEX_LEN_3806_P_2
) },
4347 /* PREFIX_VEX_3807 */
4351 { VEX_LEN_TABLE (VEX_LEN_3807_P_2
) },
4354 /* PREFIX_VEX_3808 */
4358 { VEX_LEN_TABLE (VEX_LEN_3808_P_2
) },
4361 /* PREFIX_VEX_3809 */
4365 { VEX_LEN_TABLE (VEX_LEN_3809_P_2
) },
4368 /* PREFIX_VEX_380A */
4372 { VEX_LEN_TABLE (VEX_LEN_380A_P_2
) },
4375 /* PREFIX_VEX_380B */
4379 { VEX_LEN_TABLE (VEX_LEN_380B_P_2
) },
4382 /* PREFIX_VEX_380C */
4386 { VEX_W_TABLE (VEX_W_380C_P_2
) },
4389 /* PREFIX_VEX_380D */
4393 { VEX_W_TABLE (VEX_W_380D_P_2
) },
4396 /* PREFIX_VEX_380E */
4400 { VEX_W_TABLE (VEX_W_380E_P_2
) },
4403 /* PREFIX_VEX_380F */
4407 { VEX_W_TABLE (VEX_W_380F_P_2
) },
4410 /* PREFIX_VEX_3817 */
4414 { VEX_W_TABLE (VEX_W_3817_P_2
) },
4417 /* PREFIX_VEX_3818 */
4421 { MOD_TABLE (MOD_VEX_3818_PREFIX_2
) },
4424 /* PREFIX_VEX_3819 */
4428 { MOD_TABLE (MOD_VEX_3819_PREFIX_2
) },
4431 /* PREFIX_VEX_381A */
4435 { MOD_TABLE (MOD_VEX_381A_PREFIX_2
) },
4438 /* PREFIX_VEX_381C */
4442 { VEX_LEN_TABLE (VEX_LEN_381C_P_2
) },
4445 /* PREFIX_VEX_381D */
4449 { VEX_LEN_TABLE (VEX_LEN_381D_P_2
) },
4452 /* PREFIX_VEX_381E */
4456 { VEX_LEN_TABLE (VEX_LEN_381E_P_2
) },
4459 /* PREFIX_VEX_3820 */
4463 { VEX_LEN_TABLE (VEX_LEN_3820_P_2
) },
4466 /* PREFIX_VEX_3821 */
4470 { VEX_LEN_TABLE (VEX_LEN_3821_P_2
) },
4473 /* PREFIX_VEX_3822 */
4477 { VEX_LEN_TABLE (VEX_LEN_3822_P_2
) },
4480 /* PREFIX_VEX_3823 */
4484 { VEX_LEN_TABLE (VEX_LEN_3823_P_2
) },
4487 /* PREFIX_VEX_3824 */
4491 { VEX_LEN_TABLE (VEX_LEN_3824_P_2
) },
4494 /* PREFIX_VEX_3825 */
4498 { VEX_LEN_TABLE (VEX_LEN_3825_P_2
) },
4501 /* PREFIX_VEX_3828 */
4505 { VEX_LEN_TABLE (VEX_LEN_3828_P_2
) },
4508 /* PREFIX_VEX_3829 */
4512 { VEX_LEN_TABLE (VEX_LEN_3829_P_2
) },
4515 /* PREFIX_VEX_382A */
4519 { MOD_TABLE (MOD_VEX_382A_PREFIX_2
) },
4522 /* PREFIX_VEX_382B */
4526 { VEX_LEN_TABLE (VEX_LEN_382B_P_2
) },
4529 /* PREFIX_VEX_382C */
4533 { MOD_TABLE (MOD_VEX_382C_PREFIX_2
) },
4536 /* PREFIX_VEX_382D */
4540 { MOD_TABLE (MOD_VEX_382D_PREFIX_2
) },
4543 /* PREFIX_VEX_382E */
4547 { MOD_TABLE (MOD_VEX_382E_PREFIX_2
) },
4550 /* PREFIX_VEX_382F */
4554 { MOD_TABLE (MOD_VEX_382F_PREFIX_2
) },
4557 /* PREFIX_VEX_3830 */
4561 { VEX_LEN_TABLE (VEX_LEN_3830_P_2
) },
4564 /* PREFIX_VEX_3831 */
4568 { VEX_LEN_TABLE (VEX_LEN_3831_P_2
) },
4571 /* PREFIX_VEX_3832 */
4575 { VEX_LEN_TABLE (VEX_LEN_3832_P_2
) },
4578 /* PREFIX_VEX_3833 */
4582 { VEX_LEN_TABLE (VEX_LEN_3833_P_2
) },
4585 /* PREFIX_VEX_3834 */
4589 { VEX_LEN_TABLE (VEX_LEN_3834_P_2
) },
4592 /* PREFIX_VEX_3835 */
4596 { VEX_LEN_TABLE (VEX_LEN_3835_P_2
) },
4599 /* PREFIX_VEX_3837 */
4603 { VEX_LEN_TABLE (VEX_LEN_3837_P_2
) },
4606 /* PREFIX_VEX_3838 */
4610 { VEX_LEN_TABLE (VEX_LEN_3838_P_2
) },
4613 /* PREFIX_VEX_3839 */
4617 { VEX_LEN_TABLE (VEX_LEN_3839_P_2
) },
4620 /* PREFIX_VEX_383A */
4624 { VEX_LEN_TABLE (VEX_LEN_383A_P_2
) },
4627 /* PREFIX_VEX_383B */
4631 { VEX_LEN_TABLE (VEX_LEN_383B_P_2
) },
4634 /* PREFIX_VEX_383C */
4638 { VEX_LEN_TABLE (VEX_LEN_383C_P_2
) },
4641 /* PREFIX_VEX_383D */
4645 { VEX_LEN_TABLE (VEX_LEN_383D_P_2
) },
4648 /* PREFIX_VEX_383E */
4652 { VEX_LEN_TABLE (VEX_LEN_383E_P_2
) },
4655 /* PREFIX_VEX_383F */
4659 { VEX_LEN_TABLE (VEX_LEN_383F_P_2
) },
4662 /* PREFIX_VEX_3840 */
4666 { VEX_LEN_TABLE (VEX_LEN_3840_P_2
) },
4669 /* PREFIX_VEX_3841 */
4673 { VEX_LEN_TABLE (VEX_LEN_3841_P_2
) },
4676 /* PREFIX_VEX_3896 */
4680 { "vfmaddsub132p%XW", { XM
, Vex
, EXx
} },
4683 /* PREFIX_VEX_3897 */
4687 { "vfmsubadd132p%XW", { XM
, Vex
, EXx
} },
4690 /* PREFIX_VEX_3898 */
4694 { "vfmadd132p%XW", { XM
, Vex
, EXx
} },
4697 /* PREFIX_VEX_3899 */
4701 { "vfmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
4704 /* PREFIX_VEX_389A */
4708 { "vfmsub132p%XW", { XM
, Vex
, EXx
} },
4711 /* PREFIX_VEX_389B */
4715 { "vfmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
4718 /* PREFIX_VEX_389C */
4722 { "vfnmadd132p%XW", { XM
, Vex
, EXx
} },
4725 /* PREFIX_VEX_389D */
4729 { "vfnmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
4732 /* PREFIX_VEX_389E */
4736 { "vfnmsub132p%XW", { XM
, Vex
, EXx
} },
4739 /* PREFIX_VEX_389F */
4743 { "vfnmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
4746 /* PREFIX_VEX_38A6 */
4750 { "vfmaddsub213p%XW", { XM
, Vex
, EXx
} },
4754 /* PREFIX_VEX_38A7 */
4758 { "vfmsubadd213p%XW", { XM
, Vex
, EXx
} },
4761 /* PREFIX_VEX_38A8 */
4765 { "vfmadd213p%XW", { XM
, Vex
, EXx
} },
4768 /* PREFIX_VEX_38A9 */
4772 { "vfmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
4775 /* PREFIX_VEX_38AA */
4779 { "vfmsub213p%XW", { XM
, Vex
, EXx
} },
4782 /* PREFIX_VEX_38AB */
4786 { "vfmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
4789 /* PREFIX_VEX_38AC */
4793 { "vfnmadd213p%XW", { XM
, Vex
, EXx
} },
4796 /* PREFIX_VEX_38AD */
4800 { "vfnmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
4803 /* PREFIX_VEX_38AE */
4807 { "vfnmsub213p%XW", { XM
, Vex
, EXx
} },
4810 /* PREFIX_VEX_38AF */
4814 { "vfnmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
4817 /* PREFIX_VEX_38B6 */
4821 { "vfmaddsub231p%XW", { XM
, Vex
, EXx
} },
4824 /* PREFIX_VEX_38B7 */
4828 { "vfmsubadd231p%XW", { XM
, Vex
, EXx
} },
4831 /* PREFIX_VEX_38B8 */
4835 { "vfmadd231p%XW", { XM
, Vex
, EXx
} },
4838 /* PREFIX_VEX_38B9 */
4842 { "vfmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
4845 /* PREFIX_VEX_38BA */
4849 { "vfmsub231p%XW", { XM
, Vex
, EXx
} },
4852 /* PREFIX_VEX_38BB */
4856 { "vfmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
4859 /* PREFIX_VEX_38BC */
4863 { "vfnmadd231p%XW", { XM
, Vex
, EXx
} },
4866 /* PREFIX_VEX_38BD */
4870 { "vfnmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
4873 /* PREFIX_VEX_38BE */
4877 { "vfnmsub231p%XW", { XM
, Vex
, EXx
} },
4880 /* PREFIX_VEX_38BF */
4884 { "vfnmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
4887 /* PREFIX_VEX_38DB */
4891 { VEX_LEN_TABLE (VEX_LEN_38DB_P_2
) },
4894 /* PREFIX_VEX_38DC */
4898 { VEX_LEN_TABLE (VEX_LEN_38DC_P_2
) },
4901 /* PREFIX_VEX_38DD */
4905 { VEX_LEN_TABLE (VEX_LEN_38DD_P_2
) },
4908 /* PREFIX_VEX_38DE */
4912 { VEX_LEN_TABLE (VEX_LEN_38DE_P_2
) },
4915 /* PREFIX_VEX_38DF */
4919 { VEX_LEN_TABLE (VEX_LEN_38DF_P_2
) },
4922 /* PREFIX_VEX_3A04 */
4926 { VEX_W_TABLE (VEX_W_3A04_P_2
) },
4929 /* PREFIX_VEX_3A05 */
4933 { VEX_W_TABLE (VEX_W_3A05_P_2
) },
4936 /* PREFIX_VEX_3A06 */
4940 { VEX_LEN_TABLE (VEX_LEN_3A06_P_2
) },
4943 /* PREFIX_VEX_3A08 */
4947 { VEX_W_TABLE (VEX_W_3A08_P_2
) },
4950 /* PREFIX_VEX_3A09 */
4954 { VEX_W_TABLE (VEX_W_3A09_P_2
) },
4957 /* PREFIX_VEX_3A0A */
4961 { VEX_LEN_TABLE (VEX_LEN_3A0A_P_2
) },
4964 /* PREFIX_VEX_3A0B */
4968 { VEX_LEN_TABLE (VEX_LEN_3A0B_P_2
) },
4971 /* PREFIX_VEX_3A0C */
4975 { VEX_W_TABLE (VEX_W_3A0C_P_2
) },
4978 /* PREFIX_VEX_3A0D */
4982 { VEX_W_TABLE (VEX_W_3A0D_P_2
) },
4985 /* PREFIX_VEX_3A0E */
4989 { VEX_LEN_TABLE (VEX_LEN_3A0E_P_2
) },
4992 /* PREFIX_VEX_3A0F */
4996 { VEX_LEN_TABLE (VEX_LEN_3A0F_P_2
) },
4999 /* PREFIX_VEX_3A14 */
5003 { VEX_LEN_TABLE (VEX_LEN_3A14_P_2
) },
5006 /* PREFIX_VEX_3A15 */
5010 { VEX_LEN_TABLE (VEX_LEN_3A15_P_2
) },
5013 /* PREFIX_VEX_3A16 */
5017 { VEX_LEN_TABLE (VEX_LEN_3A16_P_2
) },
5020 /* PREFIX_VEX_3A17 */
5024 { VEX_LEN_TABLE (VEX_LEN_3A17_P_2
) },
5027 /* PREFIX_VEX_3A18 */
5031 { VEX_LEN_TABLE (VEX_LEN_3A18_P_2
) },
5034 /* PREFIX_VEX_3A19 */
5038 { VEX_LEN_TABLE (VEX_LEN_3A19_P_2
) },
5041 /* PREFIX_VEX_3A20 */
5045 { VEX_LEN_TABLE (VEX_LEN_3A20_P_2
) },
5048 /* PREFIX_VEX_3A21 */
5052 { VEX_LEN_TABLE (VEX_LEN_3A21_P_2
) },
5055 /* PREFIX_VEX_3A22 */
5059 { VEX_LEN_TABLE (VEX_LEN_3A22_P_2
) },
5062 /* PREFIX_VEX_3A40 */
5066 { VEX_W_TABLE (VEX_W_3A40_P_2
) },
5069 /* PREFIX_VEX_3A41 */
5073 { VEX_LEN_TABLE (VEX_LEN_3A41_P_2
) },
5076 /* PREFIX_VEX_3A42 */
5080 { VEX_LEN_TABLE (VEX_LEN_3A42_P_2
) },
5083 /* PREFIX_VEX_3A44 */
5087 { VEX_LEN_TABLE (VEX_LEN_3A44_P_2
) },
5090 /* PREFIX_VEX_3A4A */
5094 { VEX_W_TABLE (VEX_W_3A4A_P_2
) },
5097 /* PREFIX_VEX_3A4B */
5101 { VEX_W_TABLE (VEX_W_3A4B_P_2
) },
5104 /* PREFIX_VEX_3A4C */
5108 { VEX_LEN_TABLE (VEX_LEN_3A4C_P_2
) },
5111 /* PREFIX_VEX_3A5C */
5115 { "vfmaddsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
5118 /* PREFIX_VEX_3A5D */
5122 { "vfmaddsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
5125 /* PREFIX_VEX_3A5E */
5129 { "vfmsubaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
5132 /* PREFIX_VEX_3A5F */
5136 { "vfmsubaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
5139 /* PREFIX_VEX_3A60 */
5143 { VEX_LEN_TABLE (VEX_LEN_3A60_P_2
) },
5147 /* PREFIX_VEX_3A61 */
5151 { VEX_LEN_TABLE (VEX_LEN_3A61_P_2
) },
5154 /* PREFIX_VEX_3A62 */
5158 { VEX_LEN_TABLE (VEX_LEN_3A62_P_2
) },
5161 /* PREFIX_VEX_3A63 */
5165 { VEX_LEN_TABLE (VEX_LEN_3A63_P_2
) },
5168 /* PREFIX_VEX_3A68 */
5172 { "vfmaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
5175 /* PREFIX_VEX_3A69 */
5179 { "vfmaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
5182 /* PREFIX_VEX_3A6A */
5186 { VEX_LEN_TABLE (VEX_LEN_3A6A_P_2
) },
5189 /* PREFIX_VEX_3A6B */
5193 { VEX_LEN_TABLE (VEX_LEN_3A6B_P_2
) },
5196 /* PREFIX_VEX_3A6C */
5200 { "vfmsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
5203 /* PREFIX_VEX_3A6D */
5207 { "vfmsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
5210 /* PREFIX_VEX_3A6E */
5214 { VEX_LEN_TABLE (VEX_LEN_3A6E_P_2
) },
5217 /* PREFIX_VEX_3A6F */
5221 { VEX_LEN_TABLE (VEX_LEN_3A6F_P_2
) },
5224 /* PREFIX_VEX_3A78 */
5228 { "vfnmaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
5231 /* PREFIX_VEX_3A79 */
5235 { "vfnmaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
5238 /* PREFIX_VEX_3A7A */
5242 { VEX_LEN_TABLE (VEX_LEN_3A7A_P_2
) },
5245 /* PREFIX_VEX_3A7B */
5249 { VEX_LEN_TABLE (VEX_LEN_3A7B_P_2
) },
5252 /* PREFIX_VEX_3A7C */
5256 { "vfnmsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
5260 /* PREFIX_VEX_3A7D */
5264 { "vfnmsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
5267 /* PREFIX_VEX_3A7E */
5271 { VEX_LEN_TABLE (VEX_LEN_3A7E_P_2
) },
5274 /* PREFIX_VEX_3A7F */
5278 { VEX_LEN_TABLE (VEX_LEN_3A7F_P_2
) },
5281 /* PREFIX_VEX_3ADF */
5285 { VEX_LEN_TABLE (VEX_LEN_3ADF_P_2
) },
5289 static const struct dis386 x86_64_table
[][2] = {
5292 { "push{T|}", { es
} },
5297 { "pop{T|}", { es
} },
5302 { "push{T|}", { cs
} },
5307 { "push{T|}", { ss
} },
5312 { "pop{T|}", { ss
} },
5317 { "push{T|}", { ds
} },
5322 { "pop{T|}", { ds
} },
5347 { "pusha{P|}", { XX
} },
5352 { "popa{P|}", { XX
} },
5357 { MOD_TABLE (MOD_62_32BIT
) },
5362 { "arpl", { Ew
, Gw
} },
5363 { "movs{lq|xd}", { Gv
, Ed
} },
5368 { "ins{R|}", { Yzr
, indirDX
} },
5369 { "ins{G|}", { Yzr
, indirDX
} },
5374 { "outs{R|}", { indirDXr
, Xz
} },
5375 { "outs{G|}", { indirDXr
, Xz
} },
5380 { "Jcall{T|}", { Ap
} },
5385 { MOD_TABLE (MOD_C4_32BIT
) },
5386 { VEX_C4_TABLE (VEX_0F
) },
5391 { MOD_TABLE (MOD_C5_32BIT
) },
5392 { VEX_C5_TABLE (VEX_0F
) },
5412 { "Jjmp{T|}", { Ap
} },
5415 /* X86_64_0F01_REG_0 */
5417 { "sgdt{Q|IQ}", { M
} },
5421 /* X86_64_0F01_REG_1 */
5423 { "sidt{Q|IQ}", { M
} },
5427 /* X86_64_0F01_REG_2 */
5429 { "lgdt{Q|Q}", { M
} },
5433 /* X86_64_0F01_REG_3 */
5435 { "lidt{Q|Q}", { M
} },
5440 static const struct dis386 three_byte_table
[][256] = {
5442 /* THREE_BYTE_0F38 */
5445 { "pshufb", { MX
, EM
} },
5446 { "phaddw", { MX
, EM
} },
5447 { "phaddd", { MX
, EM
} },
5448 { "phaddsw", { MX
, EM
} },
5449 { "pmaddubsw", { MX
, EM
} },
5450 { "phsubw", { MX
, EM
} },
5451 { "phsubd", { MX
, EM
} },
5452 { "phsubsw", { MX
, EM
} },
5454 { "psignb", { MX
, EM
} },
5455 { "psignw", { MX
, EM
} },
5456 { "psignd", { MX
, EM
} },
5457 { "pmulhrsw", { MX
, EM
} },
5463 { PREFIX_TABLE (PREFIX_0F3810
) },
5467 { PREFIX_TABLE (PREFIX_0F3814
) },
5468 { PREFIX_TABLE (PREFIX_0F3815
) },
5470 { PREFIX_TABLE (PREFIX_0F3817
) },
5476 { "pabsb", { MX
, EM
} },
5477 { "pabsw", { MX
, EM
} },
5478 { "pabsd", { MX
, EM
} },
5481 { PREFIX_TABLE (PREFIX_0F3820
) },
5482 { PREFIX_TABLE (PREFIX_0F3821
) },
5483 { PREFIX_TABLE (PREFIX_0F3822
) },
5484 { PREFIX_TABLE (PREFIX_0F3823
) },
5485 { PREFIX_TABLE (PREFIX_0F3824
) },
5486 { PREFIX_TABLE (PREFIX_0F3825
) },
5490 { PREFIX_TABLE (PREFIX_0F3828
) },
5491 { PREFIX_TABLE (PREFIX_0F3829
) },
5492 { PREFIX_TABLE (PREFIX_0F382A
) },
5493 { PREFIX_TABLE (PREFIX_0F382B
) },
5499 { PREFIX_TABLE (PREFIX_0F3830
) },
5500 { PREFIX_TABLE (PREFIX_0F3831
) },
5501 { PREFIX_TABLE (PREFIX_0F3832
) },
5502 { PREFIX_TABLE (PREFIX_0F3833
) },
5503 { PREFIX_TABLE (PREFIX_0F3834
) },
5504 { PREFIX_TABLE (PREFIX_0F3835
) },
5506 { PREFIX_TABLE (PREFIX_0F3837
) },
5508 { PREFIX_TABLE (PREFIX_0F3838
) },
5509 { PREFIX_TABLE (PREFIX_0F3839
) },
5510 { PREFIX_TABLE (PREFIX_0F383A
) },
5511 { PREFIX_TABLE (PREFIX_0F383B
) },
5512 { PREFIX_TABLE (PREFIX_0F383C
) },
5513 { PREFIX_TABLE (PREFIX_0F383D
) },
5514 { PREFIX_TABLE (PREFIX_0F383E
) },
5515 { PREFIX_TABLE (PREFIX_0F383F
) },
5517 { PREFIX_TABLE (PREFIX_0F3840
) },
5518 { PREFIX_TABLE (PREFIX_0F3841
) },
5589 { PREFIX_TABLE (PREFIX_0F3880
) },
5590 { PREFIX_TABLE (PREFIX_0F3881
) },
5691 { PREFIX_TABLE (PREFIX_0F38DB
) },
5692 { PREFIX_TABLE (PREFIX_0F38DC
) },
5693 { PREFIX_TABLE (PREFIX_0F38DD
) },
5694 { PREFIX_TABLE (PREFIX_0F38DE
) },
5695 { PREFIX_TABLE (PREFIX_0F38DF
) },
5715 { PREFIX_TABLE (PREFIX_0F38F0
) },
5716 { PREFIX_TABLE (PREFIX_0F38F1
) },
5733 /* THREE_BYTE_0F3A */
5745 { PREFIX_TABLE (PREFIX_0F3A08
) },
5746 { PREFIX_TABLE (PREFIX_0F3A09
) },
5747 { PREFIX_TABLE (PREFIX_0F3A0A
) },
5748 { PREFIX_TABLE (PREFIX_0F3A0B
) },
5749 { PREFIX_TABLE (PREFIX_0F3A0C
) },
5750 { PREFIX_TABLE (PREFIX_0F3A0D
) },
5751 { PREFIX_TABLE (PREFIX_0F3A0E
) },
5752 { "palignr", { MX
, EM
, Ib
} },
5758 { PREFIX_TABLE (PREFIX_0F3A14
) },
5759 { PREFIX_TABLE (PREFIX_0F3A15
) },
5760 { PREFIX_TABLE (PREFIX_0F3A16
) },
5761 { PREFIX_TABLE (PREFIX_0F3A17
) },
5772 { PREFIX_TABLE (PREFIX_0F3A20
) },
5773 { PREFIX_TABLE (PREFIX_0F3A21
) },
5774 { PREFIX_TABLE (PREFIX_0F3A22
) },
5808 { PREFIX_TABLE (PREFIX_0F3A40
) },
5809 { PREFIX_TABLE (PREFIX_0F3A41
) },
5810 { PREFIX_TABLE (PREFIX_0F3A42
) },
5812 { PREFIX_TABLE (PREFIX_0F3A44
) },
5844 { PREFIX_TABLE (PREFIX_0F3A60
) },
5845 { PREFIX_TABLE (PREFIX_0F3A61
) },
5846 { PREFIX_TABLE (PREFIX_0F3A62
) },
5847 { PREFIX_TABLE (PREFIX_0F3A63
) },
5986 { PREFIX_TABLE (PREFIX_0F3ADF
) },
6025 /* THREE_BYTE_0F7A */
6064 { "ptest", { XX
} },
6101 { "phaddbw", { XM
, EXq
} },
6102 { "phaddbd", { XM
, EXq
} },
6103 { "phaddbq", { XM
, EXq
} },
6106 { "phaddwd", { XM
, EXq
} },
6107 { "phaddwq", { XM
, EXq
} },
6112 { "phadddq", { XM
, EXq
} },
6119 { "phaddubw", { XM
, EXq
} },
6120 { "phaddubd", { XM
, EXq
} },
6121 { "phaddubq", { XM
, EXq
} },
6124 { "phadduwd", { XM
, EXq
} },
6125 { "phadduwq", { XM
, EXq
} },
6130 { "phaddudq", { XM
, EXq
} },
6137 { "phsubbw", { XM
, EXq
} },
6138 { "phsubbd", { XM
, EXq
} },
6139 { "phsubbq", { XM
, EXq
} },
6318 static const struct dis386 xop_table
[][256] = {
6471 { "vpmacssww", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6472 { "vpmacsswd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6473 { "vpmacssdql", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6481 { "vpmacssdd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6482 { "vpmacssdqh", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6489 { "vpmacsww", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6490 { "vpmacswd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6491 { "vpmacsdql", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6499 { "vpmacsdd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6500 { "vpmacsdqh", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6504 { "vpcmov", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6505 { "vpperm", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6508 { "vpmadcsswd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6526 { "vpmadcswd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6538 { "vprotb", { XM
, Vex_2src_1
, Ib
} },
6539 { "vprotw", { XM
, Vex_2src_1
, Ib
} },
6540 { "vprotd", { XM
, Vex_2src_1
, Ib
} },
6541 { "vprotq", { XM
, Vex_2src_1
, Ib
} },
6551 { "vpcomb", { XM
, Vex128
, EXx
, Ib
} },
6552 { "vpcomw", { XM
, Vex128
, EXx
, Ib
} },
6553 { "vpcomd", { XM
, Vex128
, EXx
, Ib
} },
6554 { "vpcomq", { XM
, Vex128
, EXx
, Ib
} },
6587 { "vpcomub", { XM
, Vex128
, EXx
, Ib
} },
6588 { "vpcomuw", { XM
, Vex128
, EXx
, Ib
} },
6589 { "vpcomud", { XM
, Vex128
, EXx
, Ib
} },
6590 { "vpcomuq", { XM
, Vex128
, EXx
, Ib
} },
6633 { REG_TABLE (REG_XOP_LWPCB
) },
6757 { VEX_LEN_TABLE (VEX_LEN_XOP_09_80
) },
6758 { VEX_LEN_TABLE (VEX_LEN_XOP_09_81
) },
6759 { "vfrczss", { XM
, EXd
} },
6760 { "vfrczsd", { XM
, EXq
} },
6775 { "vprotb", { XM
, Vex_2src_1
, Vex_2src_2
} },
6776 { "vprotw", { XM
, Vex_2src_1
, Vex_2src_2
} },
6777 { "vprotd", { XM
, Vex_2src_1
, Vex_2src_2
} },
6778 { "vprotq", { XM
, Vex_2src_1
, Vex_2src_2
} },
6779 { "vpshlb", { XM
, Vex_2src_1
, Vex_2src_2
} },
6780 { "vpshlw", { XM
, Vex_2src_1
, Vex_2src_2
} },
6781 { "vpshld", { XM
, Vex_2src_1
, Vex_2src_2
} },
6782 { "vpshlq", { XM
, Vex_2src_1
, Vex_2src_2
} },
6784 { "vpshab", { XM
, Vex_2src_1
, Vex_2src_2
} },
6785 { "vpshaw", { XM
, Vex_2src_1
, Vex_2src_2
} },
6786 { "vpshad", { XM
, Vex_2src_1
, Vex_2src_2
} },
6787 { "vpshaq", { XM
, Vex_2src_1
, Vex_2src_2
} },
6830 { "vphaddbw", { XM
, EXxmm
} },
6831 { "vphaddbd", { XM
, EXxmm
} },
6832 { "vphaddbq", { XM
, EXxmm
} },
6835 { "vphaddwd", { XM
, EXxmm
} },
6836 { "vphaddwq", { XM
, EXxmm
} },
6841 { "vphadddq", { XM
, EXxmm
} },
6848 { "vphaddubw", { XM
, EXxmm
} },
6849 { "vphaddubd", { XM
, EXxmm
} },
6850 { "vphaddubq", { XM
, EXxmm
} },
6853 { "vphadduwd", { XM
, EXxmm
} },
6854 { "vphadduwq", { XM
, EXxmm
} },
6859 { "vphaddudq", { XM
, EXxmm
} },
6866 { "vphsubbw", { XM
, EXxmm
} },
6867 { "vphsubwd", { XM
, EXxmm
} },
6868 { "vphsubdq", { XM
, EXxmm
} },
6924 { REG_TABLE (REG_XOP_LWP
) },
7194 static const struct dis386 vex_table
[][256] = {
7216 { PREFIX_TABLE (PREFIX_VEX_10
) },
7217 { PREFIX_TABLE (PREFIX_VEX_11
) },
7218 { PREFIX_TABLE (PREFIX_VEX_12
) },
7219 { MOD_TABLE (MOD_VEX_13
) },
7220 { VEX_W_TABLE (VEX_W_14
) },
7221 { VEX_W_TABLE (VEX_W_15
) },
7222 { PREFIX_TABLE (PREFIX_VEX_16
) },
7223 { MOD_TABLE (MOD_VEX_17
) },
7243 { VEX_W_TABLE (VEX_W_28
) },
7244 { VEX_W_TABLE (VEX_W_29
) },
7245 { PREFIX_TABLE (PREFIX_VEX_2A
) },
7246 { MOD_TABLE (MOD_VEX_2B
) },
7247 { PREFIX_TABLE (PREFIX_VEX_2C
) },
7248 { PREFIX_TABLE (PREFIX_VEX_2D
) },
7249 { PREFIX_TABLE (PREFIX_VEX_2E
) },
7250 { PREFIX_TABLE (PREFIX_VEX_2F
) },
7288 { MOD_TABLE (MOD_VEX_50
) },
7289 { PREFIX_TABLE (PREFIX_VEX_51
) },
7290 { PREFIX_TABLE (PREFIX_VEX_52
) },
7291 { PREFIX_TABLE (PREFIX_VEX_53
) },
7292 { "vandpX", { XM
, Vex
, EXx
} },
7293 { "vandnpX", { XM
, Vex
, EXx
} },
7294 { "vorpX", { XM
, Vex
, EXx
} },
7295 { "vxorpX", { XM
, Vex
, EXx
} },
7297 { PREFIX_TABLE (PREFIX_VEX_58
) },
7298 { PREFIX_TABLE (PREFIX_VEX_59
) },
7299 { PREFIX_TABLE (PREFIX_VEX_5A
) },
7300 { PREFIX_TABLE (PREFIX_VEX_5B
) },
7301 { PREFIX_TABLE (PREFIX_VEX_5C
) },
7302 { PREFIX_TABLE (PREFIX_VEX_5D
) },
7303 { PREFIX_TABLE (PREFIX_VEX_5E
) },
7304 { PREFIX_TABLE (PREFIX_VEX_5F
) },
7306 { PREFIX_TABLE (PREFIX_VEX_60
) },
7307 { PREFIX_TABLE (PREFIX_VEX_61
) },
7308 { PREFIX_TABLE (PREFIX_VEX_62
) },
7309 { PREFIX_TABLE (PREFIX_VEX_63
) },
7310 { PREFIX_TABLE (PREFIX_VEX_64
) },
7311 { PREFIX_TABLE (PREFIX_VEX_65
) },
7312 { PREFIX_TABLE (PREFIX_VEX_66
) },
7313 { PREFIX_TABLE (PREFIX_VEX_67
) },
7315 { PREFIX_TABLE (PREFIX_VEX_68
) },
7316 { PREFIX_TABLE (PREFIX_VEX_69
) },
7317 { PREFIX_TABLE (PREFIX_VEX_6A
) },
7318 { PREFIX_TABLE (PREFIX_VEX_6B
) },
7319 { PREFIX_TABLE (PREFIX_VEX_6C
) },
7320 { PREFIX_TABLE (PREFIX_VEX_6D
) },
7321 { PREFIX_TABLE (PREFIX_VEX_6E
) },
7322 { PREFIX_TABLE (PREFIX_VEX_6F
) },
7324 { PREFIX_TABLE (PREFIX_VEX_70
) },
7325 { REG_TABLE (REG_VEX_71
) },
7326 { REG_TABLE (REG_VEX_72
) },
7327 { REG_TABLE (REG_VEX_73
) },
7328 { PREFIX_TABLE (PREFIX_VEX_74
) },
7329 { PREFIX_TABLE (PREFIX_VEX_75
) },
7330 { PREFIX_TABLE (PREFIX_VEX_76
) },
7331 { PREFIX_TABLE (PREFIX_VEX_77
) },
7337 { PREFIX_TABLE (PREFIX_VEX_7C
) },
7338 { PREFIX_TABLE (PREFIX_VEX_7D
) },
7339 { PREFIX_TABLE (PREFIX_VEX_7E
) },
7340 { PREFIX_TABLE (PREFIX_VEX_7F
) },
7393 { REG_TABLE (REG_VEX_AE
) },
7416 { PREFIX_TABLE (PREFIX_VEX_C2
) },
7418 { PREFIX_TABLE (PREFIX_VEX_C4
) },
7419 { PREFIX_TABLE (PREFIX_VEX_C5
) },
7420 { "vshufpX", { XM
, Vex
, EXx
, Ib
} },
7432 { PREFIX_TABLE (PREFIX_VEX_D0
) },
7433 { PREFIX_TABLE (PREFIX_VEX_D1
) },
7434 { PREFIX_TABLE (PREFIX_VEX_D2
) },
7435 { PREFIX_TABLE (PREFIX_VEX_D3
) },
7436 { PREFIX_TABLE (PREFIX_VEX_D4
) },
7437 { PREFIX_TABLE (PREFIX_VEX_D5
) },
7438 { PREFIX_TABLE (PREFIX_VEX_D6
) },
7439 { PREFIX_TABLE (PREFIX_VEX_D7
) },
7441 { PREFIX_TABLE (PREFIX_VEX_D8
) },
7442 { PREFIX_TABLE (PREFIX_VEX_D9
) },
7443 { PREFIX_TABLE (PREFIX_VEX_DA
) },
7444 { PREFIX_TABLE (PREFIX_VEX_DB
) },
7445 { PREFIX_TABLE (PREFIX_VEX_DC
) },
7446 { PREFIX_TABLE (PREFIX_VEX_DD
) },
7447 { PREFIX_TABLE (PREFIX_VEX_DE
) },
7448 { PREFIX_TABLE (PREFIX_VEX_DF
) },
7450 { PREFIX_TABLE (PREFIX_VEX_E0
) },
7451 { PREFIX_TABLE (PREFIX_VEX_E1
) },
7452 { PREFIX_TABLE (PREFIX_VEX_E2
) },
7453 { PREFIX_TABLE (PREFIX_VEX_E3
) },
7454 { PREFIX_TABLE (PREFIX_VEX_E4
) },
7455 { PREFIX_TABLE (PREFIX_VEX_E5
) },
7456 { PREFIX_TABLE (PREFIX_VEX_E6
) },
7457 { PREFIX_TABLE (PREFIX_VEX_E7
) },
7459 { PREFIX_TABLE (PREFIX_VEX_E8
) },
7460 { PREFIX_TABLE (PREFIX_VEX_E9
) },
7461 { PREFIX_TABLE (PREFIX_VEX_EA
) },
7462 { PREFIX_TABLE (PREFIX_VEX_EB
) },
7463 { PREFIX_TABLE (PREFIX_VEX_EC
) },
7464 { PREFIX_TABLE (PREFIX_VEX_ED
) },
7465 { PREFIX_TABLE (PREFIX_VEX_EE
) },
7466 { PREFIX_TABLE (PREFIX_VEX_EF
) },
7468 { PREFIX_TABLE (PREFIX_VEX_F0
) },
7469 { PREFIX_TABLE (PREFIX_VEX_F1
) },
7470 { PREFIX_TABLE (PREFIX_VEX_F2
) },
7471 { PREFIX_TABLE (PREFIX_VEX_F3
) },
7472 { PREFIX_TABLE (PREFIX_VEX_F4
) },
7473 { PREFIX_TABLE (PREFIX_VEX_F5
) },
7474 { PREFIX_TABLE (PREFIX_VEX_F6
) },
7475 { PREFIX_TABLE (PREFIX_VEX_F7
) },
7477 { PREFIX_TABLE (PREFIX_VEX_F8
) },
7478 { PREFIX_TABLE (PREFIX_VEX_F9
) },
7479 { PREFIX_TABLE (PREFIX_VEX_FA
) },
7480 { PREFIX_TABLE (PREFIX_VEX_FB
) },
7481 { PREFIX_TABLE (PREFIX_VEX_FC
) },
7482 { PREFIX_TABLE (PREFIX_VEX_FD
) },
7483 { PREFIX_TABLE (PREFIX_VEX_FE
) },
7489 { PREFIX_TABLE (PREFIX_VEX_3800
) },
7490 { PREFIX_TABLE (PREFIX_VEX_3801
) },
7491 { PREFIX_TABLE (PREFIX_VEX_3802
) },
7492 { PREFIX_TABLE (PREFIX_VEX_3803
) },
7493 { PREFIX_TABLE (PREFIX_VEX_3804
) },
7494 { PREFIX_TABLE (PREFIX_VEX_3805
) },
7495 { PREFIX_TABLE (PREFIX_VEX_3806
) },
7496 { PREFIX_TABLE (PREFIX_VEX_3807
) },
7498 { PREFIX_TABLE (PREFIX_VEX_3808
) },
7499 { PREFIX_TABLE (PREFIX_VEX_3809
) },
7500 { PREFIX_TABLE (PREFIX_VEX_380A
) },
7501 { PREFIX_TABLE (PREFIX_VEX_380B
) },
7502 { PREFIX_TABLE (PREFIX_VEX_380C
) },
7503 { PREFIX_TABLE (PREFIX_VEX_380D
) },
7504 { PREFIX_TABLE (PREFIX_VEX_380E
) },
7505 { PREFIX_TABLE (PREFIX_VEX_380F
) },
7514 { PREFIX_TABLE (PREFIX_VEX_3817
) },
7516 { PREFIX_TABLE (PREFIX_VEX_3818
) },
7517 { PREFIX_TABLE (PREFIX_VEX_3819
) },
7518 { PREFIX_TABLE (PREFIX_VEX_381A
) },
7520 { PREFIX_TABLE (PREFIX_VEX_381C
) },
7521 { PREFIX_TABLE (PREFIX_VEX_381D
) },
7522 { PREFIX_TABLE (PREFIX_VEX_381E
) },
7525 { PREFIX_TABLE (PREFIX_VEX_3820
) },
7526 { PREFIX_TABLE (PREFIX_VEX_3821
) },
7527 { PREFIX_TABLE (PREFIX_VEX_3822
) },
7528 { PREFIX_TABLE (PREFIX_VEX_3823
) },
7529 { PREFIX_TABLE (PREFIX_VEX_3824
) },
7530 { PREFIX_TABLE (PREFIX_VEX_3825
) },
7534 { PREFIX_TABLE (PREFIX_VEX_3828
) },
7535 { PREFIX_TABLE (PREFIX_VEX_3829
) },
7536 { PREFIX_TABLE (PREFIX_VEX_382A
) },
7537 { PREFIX_TABLE (PREFIX_VEX_382B
) },
7538 { PREFIX_TABLE (PREFIX_VEX_382C
) },
7539 { PREFIX_TABLE (PREFIX_VEX_382D
) },
7540 { PREFIX_TABLE (PREFIX_VEX_382E
) },
7541 { PREFIX_TABLE (PREFIX_VEX_382F
) },
7543 { PREFIX_TABLE (PREFIX_VEX_3830
) },
7544 { PREFIX_TABLE (PREFIX_VEX_3831
) },
7545 { PREFIX_TABLE (PREFIX_VEX_3832
) },
7546 { PREFIX_TABLE (PREFIX_VEX_3833
) },
7547 { PREFIX_TABLE (PREFIX_VEX_3834
) },
7548 { PREFIX_TABLE (PREFIX_VEX_3835
) },
7550 { PREFIX_TABLE (PREFIX_VEX_3837
) },
7552 { PREFIX_TABLE (PREFIX_VEX_3838
) },
7553 { PREFIX_TABLE (PREFIX_VEX_3839
) },
7554 { PREFIX_TABLE (PREFIX_VEX_383A
) },
7555 { PREFIX_TABLE (PREFIX_VEX_383B
) },
7556 { PREFIX_TABLE (PREFIX_VEX_383C
) },
7557 { PREFIX_TABLE (PREFIX_VEX_383D
) },
7558 { PREFIX_TABLE (PREFIX_VEX_383E
) },
7559 { PREFIX_TABLE (PREFIX_VEX_383F
) },
7561 { PREFIX_TABLE (PREFIX_VEX_3840
) },
7562 { PREFIX_TABLE (PREFIX_VEX_3841
) },
7657 { PREFIX_TABLE (PREFIX_VEX_3896
) },
7658 { PREFIX_TABLE (PREFIX_VEX_3897
) },
7660 { PREFIX_TABLE (PREFIX_VEX_3898
) },
7661 { PREFIX_TABLE (PREFIX_VEX_3899
) },
7662 { PREFIX_TABLE (PREFIX_VEX_389A
) },
7663 { PREFIX_TABLE (PREFIX_VEX_389B
) },
7664 { PREFIX_TABLE (PREFIX_VEX_389C
) },
7665 { PREFIX_TABLE (PREFIX_VEX_389D
) },
7666 { PREFIX_TABLE (PREFIX_VEX_389E
) },
7667 { PREFIX_TABLE (PREFIX_VEX_389F
) },
7675 { PREFIX_TABLE (PREFIX_VEX_38A6
) },
7676 { PREFIX_TABLE (PREFIX_VEX_38A7
) },
7678 { PREFIX_TABLE (PREFIX_VEX_38A8
) },
7679 { PREFIX_TABLE (PREFIX_VEX_38A9
) },
7680 { PREFIX_TABLE (PREFIX_VEX_38AA
) },
7681 { PREFIX_TABLE (PREFIX_VEX_38AB
) },
7682 { PREFIX_TABLE (PREFIX_VEX_38AC
) },
7683 { PREFIX_TABLE (PREFIX_VEX_38AD
) },
7684 { PREFIX_TABLE (PREFIX_VEX_38AE
) },
7685 { PREFIX_TABLE (PREFIX_VEX_38AF
) },
7693 { PREFIX_TABLE (PREFIX_VEX_38B6
) },
7694 { PREFIX_TABLE (PREFIX_VEX_38B7
) },
7696 { PREFIX_TABLE (PREFIX_VEX_38B8
) },
7697 { PREFIX_TABLE (PREFIX_VEX_38B9
) },
7698 { PREFIX_TABLE (PREFIX_VEX_38BA
) },
7699 { PREFIX_TABLE (PREFIX_VEX_38BB
) },
7700 { PREFIX_TABLE (PREFIX_VEX_38BC
) },
7701 { PREFIX_TABLE (PREFIX_VEX_38BD
) },
7702 { PREFIX_TABLE (PREFIX_VEX_38BE
) },
7703 { PREFIX_TABLE (PREFIX_VEX_38BF
) },
7735 { PREFIX_TABLE (PREFIX_VEX_38DB
) },
7736 { PREFIX_TABLE (PREFIX_VEX_38DC
) },
7737 { PREFIX_TABLE (PREFIX_VEX_38DD
) },
7738 { PREFIX_TABLE (PREFIX_VEX_38DE
) },
7739 { PREFIX_TABLE (PREFIX_VEX_38DF
) },
7784 { PREFIX_TABLE (PREFIX_VEX_3A04
) },
7785 { PREFIX_TABLE (PREFIX_VEX_3A05
) },
7786 { PREFIX_TABLE (PREFIX_VEX_3A06
) },
7789 { PREFIX_TABLE (PREFIX_VEX_3A08
) },
7790 { PREFIX_TABLE (PREFIX_VEX_3A09
) },
7791 { PREFIX_TABLE (PREFIX_VEX_3A0A
) },
7792 { PREFIX_TABLE (PREFIX_VEX_3A0B
) },
7793 { PREFIX_TABLE (PREFIX_VEX_3A0C
) },
7794 { PREFIX_TABLE (PREFIX_VEX_3A0D
) },
7795 { PREFIX_TABLE (PREFIX_VEX_3A0E
) },
7796 { PREFIX_TABLE (PREFIX_VEX_3A0F
) },
7802 { PREFIX_TABLE (PREFIX_VEX_3A14
) },
7803 { PREFIX_TABLE (PREFIX_VEX_3A15
) },
7804 { PREFIX_TABLE (PREFIX_VEX_3A16
) },
7805 { PREFIX_TABLE (PREFIX_VEX_3A17
) },
7807 { PREFIX_TABLE (PREFIX_VEX_3A18
) },
7808 { PREFIX_TABLE (PREFIX_VEX_3A19
) },
7816 { PREFIX_TABLE (PREFIX_VEX_3A20
) },
7817 { PREFIX_TABLE (PREFIX_VEX_3A21
) },
7818 { PREFIX_TABLE (PREFIX_VEX_3A22
) },
7852 { PREFIX_TABLE (PREFIX_VEX_3A40
) },
7853 { PREFIX_TABLE (PREFIX_VEX_3A41
) },
7854 { PREFIX_TABLE (PREFIX_VEX_3A42
) },
7856 { PREFIX_TABLE (PREFIX_VEX_3A44
) },
7863 { PREFIX_TABLE (PREFIX_VEX_3A4A
) },
7864 { PREFIX_TABLE (PREFIX_VEX_3A4B
) },
7865 { PREFIX_TABLE (PREFIX_VEX_3A4C
) },
7883 { PREFIX_TABLE (PREFIX_VEX_3A5C
) },
7884 { PREFIX_TABLE (PREFIX_VEX_3A5D
) },
7885 { PREFIX_TABLE (PREFIX_VEX_3A5E
) },
7886 { PREFIX_TABLE (PREFIX_VEX_3A5F
) },
7888 { PREFIX_TABLE (PREFIX_VEX_3A60
) },
7889 { PREFIX_TABLE (PREFIX_VEX_3A61
) },
7890 { PREFIX_TABLE (PREFIX_VEX_3A62
) },
7891 { PREFIX_TABLE (PREFIX_VEX_3A63
) },
7897 { PREFIX_TABLE (PREFIX_VEX_3A68
) },
7898 { PREFIX_TABLE (PREFIX_VEX_3A69
) },
7899 { PREFIX_TABLE (PREFIX_VEX_3A6A
) },
7900 { PREFIX_TABLE (PREFIX_VEX_3A6B
) },
7901 { PREFIX_TABLE (PREFIX_VEX_3A6C
) },
7902 { PREFIX_TABLE (PREFIX_VEX_3A6D
) },
7903 { PREFIX_TABLE (PREFIX_VEX_3A6E
) },
7904 { PREFIX_TABLE (PREFIX_VEX_3A6F
) },
7915 { PREFIX_TABLE (PREFIX_VEX_3A78
) },
7916 { PREFIX_TABLE (PREFIX_VEX_3A79
) },
7917 { PREFIX_TABLE (PREFIX_VEX_3A7A
) },
7918 { PREFIX_TABLE (PREFIX_VEX_3A7B
) },
7919 { PREFIX_TABLE (PREFIX_VEX_3A7C
) },
7920 { PREFIX_TABLE (PREFIX_VEX_3A7D
) },
7921 { PREFIX_TABLE (PREFIX_VEX_3A7E
) },
7922 { PREFIX_TABLE (PREFIX_VEX_3A7F
) },
8030 { PREFIX_TABLE (PREFIX_VEX_3ADF
) },
8070 static const struct dis386 vex_len_table
[][2] = {
8071 /* VEX_LEN_10_P_1 */
8073 { VEX_W_TABLE (VEX_W_10_P_1
) },
8074 { VEX_W_TABLE (VEX_W_10_P_1
) },
8077 /* VEX_LEN_10_P_3 */
8079 { VEX_W_TABLE (VEX_W_10_P_3
) },
8080 { VEX_W_TABLE (VEX_W_10_P_3
) },
8083 /* VEX_LEN_11_P_1 */
8085 { VEX_W_TABLE (VEX_W_11_P_1
) },
8086 { VEX_W_TABLE (VEX_W_11_P_1
) },
8089 /* VEX_LEN_11_P_3 */
8091 { VEX_W_TABLE (VEX_W_11_P_3
) },
8092 { VEX_W_TABLE (VEX_W_11_P_3
) },
8095 /* VEX_LEN_12_P_0_M_0 */
8097 { VEX_W_TABLE (VEX_W_12_P_0_M_0
) },
8100 /* VEX_LEN_12_P_0_M_1 */
8102 { VEX_W_TABLE (VEX_W_12_P_0_M_1
) },
8105 /* VEX_LEN_12_P_2 */
8107 { VEX_W_TABLE (VEX_W_12_P_2
) },
8110 /* VEX_LEN_13_M_0 */
8112 { VEX_W_TABLE (VEX_W_13_M_0
) },
8115 /* VEX_LEN_16_P_0_M_0 */
8117 { VEX_W_TABLE (VEX_W_16_P_0_M_0
) },
8120 /* VEX_LEN_16_P_0_M_1 */
8122 { VEX_W_TABLE (VEX_W_16_P_0_M_1
) },
8125 /* VEX_LEN_16_P_2 */
8127 { VEX_W_TABLE (VEX_W_16_P_2
) },
8130 /* VEX_LEN_17_M_0 */
8132 { VEX_W_TABLE (VEX_W_17_M_0
) },
8135 /* VEX_LEN_2A_P_1 */
8137 { "vcvtsi2ss%LQ", { XMScalar
, VexScalar
, Ev
} },
8138 { "vcvtsi2ss%LQ", { XMScalar
, VexScalar
, Ev
} },
8141 /* VEX_LEN_2A_P_3 */
8143 { "vcvtsi2sd%LQ", { XMScalar
, VexScalar
, Ev
} },
8144 { "vcvtsi2sd%LQ", { XMScalar
, VexScalar
, Ev
} },
8147 /* VEX_LEN_2C_P_1 */
8149 { "vcvttss2siY", { Gv
, EXdScalar
} },
8150 { "vcvttss2siY", { Gv
, EXdScalar
} },
8153 /* VEX_LEN_2C_P_3 */
8155 { "vcvttsd2siY", { Gv
, EXqScalar
} },
8156 { "vcvttsd2siY", { Gv
, EXqScalar
} },
8159 /* VEX_LEN_2D_P_1 */
8161 { "vcvtss2siY", { Gv
, EXdScalar
} },
8162 { "vcvtss2siY", { Gv
, EXdScalar
} },
8165 /* VEX_LEN_2D_P_3 */
8167 { "vcvtsd2siY", { Gv
, EXqScalar
} },
8168 { "vcvtsd2siY", { Gv
, EXqScalar
} },
8171 /* VEX_LEN_2E_P_0 */
8173 { VEX_W_TABLE (VEX_W_2E_P_0
) },
8174 { VEX_W_TABLE (VEX_W_2E_P_0
) },
8177 /* VEX_LEN_2E_P_2 */
8179 { VEX_W_TABLE (VEX_W_2E_P_2
) },
8180 { VEX_W_TABLE (VEX_W_2E_P_2
) },
8183 /* VEX_LEN_2F_P_0 */
8185 { VEX_W_TABLE (VEX_W_2F_P_0
) },
8186 { VEX_W_TABLE (VEX_W_2F_P_0
) },
8189 /* VEX_LEN_2F_P_2 */
8191 { VEX_W_TABLE (VEX_W_2F_P_2
) },
8192 { VEX_W_TABLE (VEX_W_2F_P_2
) },
8195 /* VEX_LEN_51_P_1 */
8197 { VEX_W_TABLE (VEX_W_51_P_1
) },
8198 { VEX_W_TABLE (VEX_W_51_P_1
) },
8201 /* VEX_LEN_51_P_3 */
8203 { VEX_W_TABLE (VEX_W_51_P_3
) },
8204 { VEX_W_TABLE (VEX_W_51_P_3
) },
8207 /* VEX_LEN_52_P_1 */
8209 { VEX_W_TABLE (VEX_W_52_P_1
) },
8210 { VEX_W_TABLE (VEX_W_52_P_1
) },
8213 /* VEX_LEN_53_P_1 */
8215 { VEX_W_TABLE (VEX_W_53_P_1
) },
8216 { VEX_W_TABLE (VEX_W_53_P_1
) },
8219 /* VEX_LEN_58_P_1 */
8221 { VEX_W_TABLE (VEX_W_58_P_1
) },
8222 { VEX_W_TABLE (VEX_W_58_P_1
) },
8225 /* VEX_LEN_58_P_3 */
8227 { VEX_W_TABLE (VEX_W_58_P_3
) },
8228 { VEX_W_TABLE (VEX_W_58_P_3
) },
8231 /* VEX_LEN_59_P_1 */
8233 { VEX_W_TABLE (VEX_W_59_P_1
) },
8234 { VEX_W_TABLE (VEX_W_59_P_1
) },
8237 /* VEX_LEN_59_P_3 */
8239 { VEX_W_TABLE (VEX_W_59_P_3
) },
8240 { VEX_W_TABLE (VEX_W_59_P_3
) },
8243 /* VEX_LEN_5A_P_1 */
8245 { VEX_W_TABLE (VEX_W_5A_P_1
) },
8246 { VEX_W_TABLE (VEX_W_5A_P_1
) },
8249 /* VEX_LEN_5A_P_3 */
8251 { VEX_W_TABLE (VEX_W_5A_P_3
) },
8252 { VEX_W_TABLE (VEX_W_5A_P_3
) },
8255 /* VEX_LEN_5C_P_1 */
8257 { VEX_W_TABLE (VEX_W_5C_P_1
) },
8258 { VEX_W_TABLE (VEX_W_5C_P_1
) },
8261 /* VEX_LEN_5C_P_3 */
8263 { VEX_W_TABLE (VEX_W_5C_P_3
) },
8264 { VEX_W_TABLE (VEX_W_5C_P_3
) },
8267 /* VEX_LEN_5D_P_1 */
8269 { VEX_W_TABLE (VEX_W_5D_P_1
) },
8270 { VEX_W_TABLE (VEX_W_5D_P_1
) },
8273 /* VEX_LEN_5D_P_3 */
8275 { VEX_W_TABLE (VEX_W_5D_P_3
) },
8276 { VEX_W_TABLE (VEX_W_5D_P_3
) },
8279 /* VEX_LEN_5E_P_1 */
8281 { VEX_W_TABLE (VEX_W_5E_P_1
) },
8282 { VEX_W_TABLE (VEX_W_5E_P_1
) },
8285 /* VEX_LEN_5E_P_3 */
8287 { VEX_W_TABLE (VEX_W_5E_P_3
) },
8288 { VEX_W_TABLE (VEX_W_5E_P_3
) },
8291 /* VEX_LEN_5F_P_1 */
8293 { VEX_W_TABLE (VEX_W_5F_P_1
) },
8294 { VEX_W_TABLE (VEX_W_5F_P_1
) },
8297 /* VEX_LEN_5F_P_3 */
8299 { VEX_W_TABLE (VEX_W_5F_P_3
) },
8300 { VEX_W_TABLE (VEX_W_5F_P_3
) },
8303 /* VEX_LEN_60_P_2 */
8305 { VEX_W_TABLE (VEX_W_60_P_2
) },
8308 /* VEX_LEN_61_P_2 */
8310 { VEX_W_TABLE (VEX_W_61_P_2
) },
8313 /* VEX_LEN_62_P_2 */
8315 { VEX_W_TABLE (VEX_W_62_P_2
) },
8318 /* VEX_LEN_63_P_2 */
8320 { VEX_W_TABLE (VEX_W_63_P_2
) },
8323 /* VEX_LEN_64_P_2 */
8325 { VEX_W_TABLE (VEX_W_64_P_2
) },
8328 /* VEX_LEN_65_P_2 */
8330 { VEX_W_TABLE (VEX_W_65_P_2
) },
8333 /* VEX_LEN_66_P_2 */
8335 { VEX_W_TABLE (VEX_W_66_P_2
) },
8338 /* VEX_LEN_67_P_2 */
8340 { VEX_W_TABLE (VEX_W_67_P_2
) },
8343 /* VEX_LEN_68_P_2 */
8345 { VEX_W_TABLE (VEX_W_68_P_2
) },
8348 /* VEX_LEN_69_P_2 */
8350 { VEX_W_TABLE (VEX_W_69_P_2
) },
8353 /* VEX_LEN_6A_P_2 */
8355 { VEX_W_TABLE (VEX_W_6A_P_2
) },
8358 /* VEX_LEN_6B_P_2 */
8360 { VEX_W_TABLE (VEX_W_6B_P_2
) },
8363 /* VEX_LEN_6C_P_2 */
8365 { VEX_W_TABLE (VEX_W_6C_P_2
) },
8368 /* VEX_LEN_6D_P_2 */
8370 { VEX_W_TABLE (VEX_W_6D_P_2
) },
8373 /* VEX_LEN_6E_P_2 */
8375 { "vmovK", { XMScalar
, Edq
} },
8376 { "vmovK", { XMScalar
, Edq
} },
8379 /* VEX_LEN_70_P_1 */
8381 { VEX_W_TABLE (VEX_W_70_P_1
) },
8384 /* VEX_LEN_70_P_2 */
8386 { VEX_W_TABLE (VEX_W_70_P_2
) },
8389 /* VEX_LEN_70_P_3 */
8391 { VEX_W_TABLE (VEX_W_70_P_3
) },
8394 /* VEX_LEN_71_R_2_P_2 */
8396 { VEX_W_TABLE (VEX_W_71_R_2_P_2
) },
8399 /* VEX_LEN_71_R_4_P_2 */
8401 { VEX_W_TABLE (VEX_W_71_R_4_P_2
) },
8404 /* VEX_LEN_71_R_6_P_2 */
8406 { VEX_W_TABLE (VEX_W_71_R_6_P_2
) },
8409 /* VEX_LEN_72_R_2_P_2 */
8411 { VEX_W_TABLE (VEX_W_72_R_2_P_2
) },
8414 /* VEX_LEN_72_R_4_P_2 */
8416 { VEX_W_TABLE (VEX_W_72_R_4_P_2
) },
8419 /* VEX_LEN_72_R_6_P_2 */
8421 { VEX_W_TABLE (VEX_W_72_R_6_P_2
) },
8424 /* VEX_LEN_73_R_2_P_2 */
8426 { VEX_W_TABLE (VEX_W_73_R_2_P_2
) },
8429 /* VEX_LEN_73_R_3_P_2 */
8431 { VEX_W_TABLE (VEX_W_73_R_3_P_2
) },
8434 /* VEX_LEN_73_R_6_P_2 */
8436 { VEX_W_TABLE (VEX_W_73_R_6_P_2
) },
8439 /* VEX_LEN_73_R_7_P_2 */
8441 { VEX_W_TABLE (VEX_W_73_R_7_P_2
) },
8444 /* VEX_LEN_74_P_2 */
8446 { VEX_W_TABLE (VEX_W_74_P_2
) },
8449 /* VEX_LEN_75_P_2 */
8451 { VEX_W_TABLE (VEX_W_75_P_2
) },
8454 /* VEX_LEN_76_P_2 */
8456 { VEX_W_TABLE (VEX_W_76_P_2
) },
8459 /* VEX_LEN_7E_P_1 */
8461 { VEX_W_TABLE (VEX_W_7E_P_1
) },
8462 { VEX_W_TABLE (VEX_W_7E_P_1
) },
8465 /* VEX_LEN_7E_P_2 */
8467 { "vmovK", { Edq
, XMScalar
} },
8468 { "vmovK", { Edq
, XMScalar
} },
8471 /* VEX_LEN_AE_R_2_M_0 */
8473 { VEX_W_TABLE (VEX_W_AE_R_2_M_0
) },
8476 /* VEX_LEN_AE_R_3_M_0 */
8478 { VEX_W_TABLE (VEX_W_AE_R_3_M_0
) },
8481 /* VEX_LEN_C2_P_1 */
8483 { VEX_W_TABLE (VEX_W_C2_P_1
) },
8484 { VEX_W_TABLE (VEX_W_C2_P_1
) },
8487 /* VEX_LEN_C2_P_3 */
8489 { VEX_W_TABLE (VEX_W_C2_P_3
) },
8490 { VEX_W_TABLE (VEX_W_C2_P_3
) },
8493 /* VEX_LEN_C4_P_2 */
8495 { VEX_W_TABLE (VEX_W_C4_P_2
) },
8498 /* VEX_LEN_C5_P_2 */
8500 { VEX_W_TABLE (VEX_W_C5_P_2
) },
8503 /* VEX_LEN_D1_P_2 */
8505 { VEX_W_TABLE (VEX_W_D1_P_2
) },
8508 /* VEX_LEN_D2_P_2 */
8510 { VEX_W_TABLE (VEX_W_D2_P_2
) },
8513 /* VEX_LEN_D3_P_2 */
8515 { VEX_W_TABLE (VEX_W_D3_P_2
) },
8518 /* VEX_LEN_D4_P_2 */
8520 { VEX_W_TABLE (VEX_W_D4_P_2
) },
8523 /* VEX_LEN_D5_P_2 */
8525 { VEX_W_TABLE (VEX_W_D5_P_2
) },
8528 /* VEX_LEN_D6_P_2 */
8530 { VEX_W_TABLE (VEX_W_D6_P_2
) },
8531 { VEX_W_TABLE (VEX_W_D6_P_2
) },
8534 /* VEX_LEN_D7_P_2_M_1 */
8536 { VEX_W_TABLE (VEX_W_D7_P_2_M_1
) },
8539 /* VEX_LEN_D8_P_2 */
8541 { VEX_W_TABLE (VEX_W_D8_P_2
) },
8544 /* VEX_LEN_D9_P_2 */
8546 { VEX_W_TABLE (VEX_W_D9_P_2
) },
8549 /* VEX_LEN_DA_P_2 */
8551 { VEX_W_TABLE (VEX_W_DA_P_2
) },
8554 /* VEX_LEN_DB_P_2 */
8556 { VEX_W_TABLE (VEX_W_DB_P_2
) },
8559 /* VEX_LEN_DC_P_2 */
8561 { VEX_W_TABLE (VEX_W_DC_P_2
) },
8564 /* VEX_LEN_DD_P_2 */
8566 { VEX_W_TABLE (VEX_W_DD_P_2
) },
8569 /* VEX_LEN_DE_P_2 */
8571 { VEX_W_TABLE (VEX_W_DE_P_2
) },
8574 /* VEX_LEN_DF_P_2 */
8576 { VEX_W_TABLE (VEX_W_DF_P_2
) },
8579 /* VEX_LEN_E0_P_2 */
8581 { VEX_W_TABLE (VEX_W_E0_P_2
) },
8584 /* VEX_LEN_E1_P_2 */
8586 { VEX_W_TABLE (VEX_W_E1_P_2
) },
8589 /* VEX_LEN_E2_P_2 */
8591 { VEX_W_TABLE (VEX_W_E2_P_2
) },
8594 /* VEX_LEN_E3_P_2 */
8596 { VEX_W_TABLE (VEX_W_E3_P_2
) },
8599 /* VEX_LEN_E4_P_2 */
8601 { VEX_W_TABLE (VEX_W_E4_P_2
) },
8604 /* VEX_LEN_E5_P_2 */
8606 { VEX_W_TABLE (VEX_W_E5_P_2
) },
8609 /* VEX_LEN_E8_P_2 */
8611 { VEX_W_TABLE (VEX_W_E8_P_2
) },
8614 /* VEX_LEN_E9_P_2 */
8616 { VEX_W_TABLE (VEX_W_E9_P_2
) },
8619 /* VEX_LEN_EA_P_2 */
8621 { VEX_W_TABLE (VEX_W_EA_P_2
) },
8624 /* VEX_LEN_EB_P_2 */
8626 { VEX_W_TABLE (VEX_W_EB_P_2
) },
8629 /* VEX_LEN_EC_P_2 */
8631 { VEX_W_TABLE (VEX_W_EC_P_2
) },
8634 /* VEX_LEN_ED_P_2 */
8636 { VEX_W_TABLE (VEX_W_ED_P_2
) },
8639 /* VEX_LEN_EE_P_2 */
8641 { VEX_W_TABLE (VEX_W_EE_P_2
) },
8644 /* VEX_LEN_EF_P_2 */
8646 { VEX_W_TABLE (VEX_W_EF_P_2
) },
8649 /* VEX_LEN_F1_P_2 */
8651 { VEX_W_TABLE (VEX_W_F1_P_2
) },
8654 /* VEX_LEN_F2_P_2 */
8656 { VEX_W_TABLE (VEX_W_F2_P_2
) },
8659 /* VEX_LEN_F3_P_2 */
8661 { VEX_W_TABLE (VEX_W_F3_P_2
) },
8664 /* VEX_LEN_F4_P_2 */
8666 { VEX_W_TABLE (VEX_W_F4_P_2
) },
8669 /* VEX_LEN_F5_P_2 */
8671 { VEX_W_TABLE (VEX_W_F5_P_2
) },
8674 /* VEX_LEN_F6_P_2 */
8676 { VEX_W_TABLE (VEX_W_F6_P_2
) },
8679 /* VEX_LEN_F7_P_2 */
8681 { VEX_W_TABLE (VEX_W_F7_P_2
) },
8684 /* VEX_LEN_F8_P_2 */
8686 { VEX_W_TABLE (VEX_W_F8_P_2
) },
8689 /* VEX_LEN_F9_P_2 */
8691 { VEX_W_TABLE (VEX_W_F9_P_2
) },
8694 /* VEX_LEN_FA_P_2 */
8696 { VEX_W_TABLE (VEX_W_FA_P_2
) },
8699 /* VEX_LEN_FB_P_2 */
8701 { VEX_W_TABLE (VEX_W_FB_P_2
) },
8704 /* VEX_LEN_FC_P_2 */
8706 { VEX_W_TABLE (VEX_W_FC_P_2
) },
8709 /* VEX_LEN_FD_P_2 */
8711 { VEX_W_TABLE (VEX_W_FD_P_2
) },
8714 /* VEX_LEN_FE_P_2 */
8716 { VEX_W_TABLE (VEX_W_FE_P_2
) },
8719 /* VEX_LEN_3800_P_2 */
8721 { VEX_W_TABLE (VEX_W_3800_P_2
) },
8724 /* VEX_LEN_3801_P_2 */
8726 { VEX_W_TABLE (VEX_W_3801_P_2
) },
8729 /* VEX_LEN_3802_P_2 */
8731 { VEX_W_TABLE (VEX_W_3802_P_2
) },
8734 /* VEX_LEN_3803_P_2 */
8736 { VEX_W_TABLE (VEX_W_3803_P_2
) },
8739 /* VEX_LEN_3804_P_2 */
8741 { VEX_W_TABLE (VEX_W_3804_P_2
) },
8744 /* VEX_LEN_3805_P_2 */
8746 { VEX_W_TABLE (VEX_W_3805_P_2
) },
8749 /* VEX_LEN_3806_P_2 */
8751 { VEX_W_TABLE (VEX_W_3806_P_2
) },
8754 /* VEX_LEN_3807_P_2 */
8756 { VEX_W_TABLE (VEX_W_3807_P_2
) },
8759 /* VEX_LEN_3808_P_2 */
8761 { VEX_W_TABLE (VEX_W_3808_P_2
) },
8764 /* VEX_LEN_3809_P_2 */
8766 { VEX_W_TABLE (VEX_W_3809_P_2
) },
8769 /* VEX_LEN_380A_P_2 */
8771 { VEX_W_TABLE (VEX_W_380A_P_2
) },
8774 /* VEX_LEN_380B_P_2 */
8776 { VEX_W_TABLE (VEX_W_380B_P_2
) },
8779 /* VEX_LEN_3819_P_2_M_0 */
8782 { VEX_W_TABLE (VEX_W_3819_P_2_M_0
) },
8785 /* VEX_LEN_381A_P_2_M_0 */
8788 { VEX_W_TABLE (VEX_W_381A_P_2_M_0
) },
8791 /* VEX_LEN_381C_P_2 */
8793 { VEX_W_TABLE (VEX_W_381C_P_2
) },
8796 /* VEX_LEN_381D_P_2 */
8798 { VEX_W_TABLE (VEX_W_381D_P_2
) },
8801 /* VEX_LEN_381E_P_2 */
8803 { VEX_W_TABLE (VEX_W_381E_P_2
) },
8806 /* VEX_LEN_3820_P_2 */
8808 { VEX_W_TABLE (VEX_W_3820_P_2
) },
8811 /* VEX_LEN_3821_P_2 */
8813 { VEX_W_TABLE (VEX_W_3821_P_2
) },
8816 /* VEX_LEN_3822_P_2 */
8818 { VEX_W_TABLE (VEX_W_3822_P_2
) },
8821 /* VEX_LEN_3823_P_2 */
8823 { VEX_W_TABLE (VEX_W_3823_P_2
) },
8826 /* VEX_LEN_3824_P_2 */
8828 { VEX_W_TABLE (VEX_W_3824_P_2
) },
8831 /* VEX_LEN_3825_P_2 */
8833 { VEX_W_TABLE (VEX_W_3825_P_2
) },
8836 /* VEX_LEN_3828_P_2 */
8838 { VEX_W_TABLE (VEX_W_3828_P_2
) },
8841 /* VEX_LEN_3829_P_2 */
8843 { VEX_W_TABLE (VEX_W_3829_P_2
) },
8846 /* VEX_LEN_382A_P_2_M_0 */
8848 { VEX_W_TABLE (VEX_W_382A_P_2_M_0
) },
8851 /* VEX_LEN_382B_P_2 */
8853 { VEX_W_TABLE (VEX_W_382B_P_2
) },
8856 /* VEX_LEN_3830_P_2 */
8858 { VEX_W_TABLE (VEX_W_3830_P_2
) },
8861 /* VEX_LEN_3831_P_2 */
8863 { VEX_W_TABLE (VEX_W_3831_P_2
) },
8866 /* VEX_LEN_3832_P_2 */
8868 { VEX_W_TABLE (VEX_W_3832_P_2
) },
8871 /* VEX_LEN_3833_P_2 */
8873 { VEX_W_TABLE (VEX_W_3833_P_2
) },
8876 /* VEX_LEN_3834_P_2 */
8878 { VEX_W_TABLE (VEX_W_3834_P_2
) },
8881 /* VEX_LEN_3835_P_2 */
8883 { VEX_W_TABLE (VEX_W_3835_P_2
) },
8886 /* VEX_LEN_3837_P_2 */
8888 { VEX_W_TABLE (VEX_W_3837_P_2
) },
8891 /* VEX_LEN_3838_P_2 */
8893 { VEX_W_TABLE (VEX_W_3838_P_2
) },
8896 /* VEX_LEN_3839_P_2 */
8898 { VEX_W_TABLE (VEX_W_3839_P_2
) },
8901 /* VEX_LEN_383A_P_2 */
8903 { VEX_W_TABLE (VEX_W_383A_P_2
) },
8906 /* VEX_LEN_383B_P_2 */
8908 { VEX_W_TABLE (VEX_W_383B_P_2
) },
8911 /* VEX_LEN_383C_P_2 */
8913 { VEX_W_TABLE (VEX_W_383C_P_2
) },
8916 /* VEX_LEN_383D_P_2 */
8918 { VEX_W_TABLE (VEX_W_383D_P_2
) },
8921 /* VEX_LEN_383E_P_2 */
8923 { VEX_W_TABLE (VEX_W_383E_P_2
) },
8926 /* VEX_LEN_383F_P_2 */
8928 { VEX_W_TABLE (VEX_W_383F_P_2
) },
8931 /* VEX_LEN_3840_P_2 */
8933 { VEX_W_TABLE (VEX_W_3840_P_2
) },
8936 /* VEX_LEN_3841_P_2 */
8938 { VEX_W_TABLE (VEX_W_3841_P_2
) },
8941 /* VEX_LEN_38DB_P_2 */
8943 { VEX_W_TABLE (VEX_W_38DB_P_2
) },
8946 /* VEX_LEN_38DC_P_2 */
8948 { VEX_W_TABLE (VEX_W_38DC_P_2
) },
8951 /* VEX_LEN_38DD_P_2 */
8953 { VEX_W_TABLE (VEX_W_38DD_P_2
) },
8956 /* VEX_LEN_38DE_P_2 */
8958 { VEX_W_TABLE (VEX_W_38DE_P_2
) },
8961 /* VEX_LEN_38DF_P_2 */
8963 { VEX_W_TABLE (VEX_W_38DF_P_2
) },
8966 /* VEX_LEN_3A06_P_2 */
8969 { VEX_W_TABLE (VEX_W_3A06_P_2
) },
8972 /* VEX_LEN_3A0A_P_2 */
8974 { VEX_W_TABLE (VEX_W_3A0A_P_2
) },
8975 { VEX_W_TABLE (VEX_W_3A0A_P_2
) },
8978 /* VEX_LEN_3A0B_P_2 */
8980 { VEX_W_TABLE (VEX_W_3A0B_P_2
) },
8981 { VEX_W_TABLE (VEX_W_3A0B_P_2
) },
8984 /* VEX_LEN_3A0E_P_2 */
8986 { VEX_W_TABLE (VEX_W_3A0E_P_2
) },
8989 /* VEX_LEN_3A0F_P_2 */
8991 { VEX_W_TABLE (VEX_W_3A0F_P_2
) },
8994 /* VEX_LEN_3A14_P_2 */
8996 { VEX_W_TABLE (VEX_W_3A14_P_2
) },
8999 /* VEX_LEN_3A15_P_2 */
9001 { VEX_W_TABLE (VEX_W_3A15_P_2
) },
9004 /* VEX_LEN_3A16_P_2 */
9006 { "vpextrK", { Edq
, XM
, Ib
} },
9009 /* VEX_LEN_3A17_P_2 */
9011 { "vextractps", { Edqd
, XM
, Ib
} },
9014 /* VEX_LEN_3A18_P_2 */
9017 { VEX_W_TABLE (VEX_W_3A18_P_2
) },
9020 /* VEX_LEN_3A19_P_2 */
9023 { VEX_W_TABLE (VEX_W_3A19_P_2
) },
9026 /* VEX_LEN_3A20_P_2 */
9028 { VEX_W_TABLE (VEX_W_3A20_P_2
) },
9031 /* VEX_LEN_3A21_P_2 */
9033 { VEX_W_TABLE (VEX_W_3A21_P_2
) },
9036 /* VEX_LEN_3A22_P_2 */
9038 { "vpinsrK", { XM
, Vex128
, Edq
, Ib
} },
9041 /* VEX_LEN_3A41_P_2 */
9043 { VEX_W_TABLE (VEX_W_3A41_P_2
) },
9046 /* VEX_LEN_3A42_P_2 */
9048 { VEX_W_TABLE (VEX_W_3A42_P_2
) },
9051 /* VEX_LEN_3A44_P_2 */
9053 { VEX_W_TABLE (VEX_W_3A44_P_2
) },
9056 /* VEX_LEN_3A4C_P_2 */
9058 { VEX_W_TABLE (VEX_W_3A4C_P_2
) },
9061 /* VEX_LEN_3A60_P_2 */
9063 { VEX_W_TABLE (VEX_W_3A60_P_2
) },
9066 /* VEX_LEN_3A61_P_2 */
9068 { VEX_W_TABLE (VEX_W_3A61_P_2
) },
9071 /* VEX_LEN_3A62_P_2 */
9073 { VEX_W_TABLE (VEX_W_3A62_P_2
) },
9076 /* VEX_LEN_3A63_P_2 */
9078 { VEX_W_TABLE (VEX_W_3A63_P_2
) },
9081 /* VEX_LEN_3A6A_P_2 */
9083 { "vfmaddss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
, VexI4
} },
9086 /* VEX_LEN_3A6B_P_2 */
9088 { "vfmaddsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
, VexI4
} },
9091 /* VEX_LEN_3A6E_P_2 */
9093 { "vfmsubss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
, VexI4
} },
9096 /* VEX_LEN_3A6F_P_2 */
9098 { "vfmsubsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
, VexI4
} },
9101 /* VEX_LEN_3A7A_P_2 */
9103 { "vfnmaddss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
, VexI4
} },
9106 /* VEX_LEN_3A7B_P_2 */
9108 { "vfnmaddsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
, VexI4
} },
9111 /* VEX_LEN_3A7E_P_2 */
9113 { "vfnmsubss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
, VexI4
} },
9116 /* VEX_LEN_3A7F_P_2 */
9118 { "vfnmsubsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
, VexI4
} },
9121 /* VEX_LEN_3ADF_P_2 */
9123 { VEX_W_TABLE (VEX_W_3ADF_P_2
) },
9126 /* VEX_LEN_XOP_09_80 */
9128 { "vfrczps", { XM
, EXxmm
} },
9129 { "vfrczps", { XM
, EXymmq
} },
9132 /* VEX_LEN_XOP_09_81 */
9134 { "vfrczpd", { XM
, EXxmm
} },
9135 { "vfrczpd", { XM
, EXymmq
} },
9139 static const struct dis386 vex_w_table
[][2] = {
9142 { "vmovups", { XM
, EXx
} },
9146 { "vmovss", { XMVexScalar
, VexScalar
, EXdScalar
} },
9150 { "vmovupd", { XM
, EXx
} },
9154 { "vmovsd", { XMVexScalar
, VexScalar
, EXqScalar
} },
9158 { "vmovups", { EXxS
, XM
} },
9162 { "vmovss", { EXdVexScalarS
, VexScalar
, XMScalar
} },
9166 { "vmovupd", { EXxS
, XM
} },
9170 { "vmovsd", { EXqVexScalarS
, VexScalar
, XMScalar
} },
9173 /* VEX_W_12_P_0_M_0 */
9174 { "vmovlps", { XM
, Vex128
, EXq
} },
9177 /* VEX_W_12_P_0_M_1 */
9178 { "vmovhlps", { XM
, Vex128
, EXq
} },
9182 { "vmovsldup", { XM
, EXx
} },
9186 { "vmovlpd", { XM
, Vex128
, EXq
} },
9190 { "vmovddup", { XM
, EXymmq
} },
9194 { "vmovlpX", { EXq
, XM
} },
9198 { "vunpcklpX", { XM
, Vex
, EXx
} },
9202 { "vunpckhpX", { XM
, Vex
, EXx
} },
9205 /* VEX_W_16_P_0_M_0 */
9206 { "vmovhps", { XM
, Vex128
, EXq
} },
9209 /* VEX_W_16_P_0_M_1 */
9210 { "vmovlhps", { XM
, Vex128
, EXq
} },
9214 { "vmovshdup", { XM
, EXx
} },
9218 { "vmovhpd", { XM
, Vex128
, EXq
} },
9222 { "vmovhpX", { EXq
, XM
} },
9226 { "vmovapX", { XM
, EXx
} },
9230 { "vmovapX", { EXxS
, XM
} },
9234 { "vmovntpX", { Mx
, XM
} },
9238 { "vucomiss", { XMScalar
, EXdScalar
} },
9242 { "vucomisd", { XMScalar
, EXqScalar
} },
9246 { "vcomiss", { XMScalar
, EXdScalar
} },
9250 { "vcomisd", { XMScalar
, EXqScalar
} },
9254 { "vmovmskpX", { Gdq
, XS
} },
9258 { "vsqrtps", { XM
, EXx
} },
9262 { "vsqrtss", { XMScalar
, VexScalar
, EXdScalar
} },
9266 { "vsqrtpd", { XM
, EXx
} },
9270 { "vsqrtsd", { XMScalar
, VexScalar
, EXqScalar
} },
9274 { "vrsqrtps", { XM
, EXx
} },
9278 { "vrsqrtss", { XMScalar
, VexScalar
, EXdScalar
} },
9282 { "vrcpps", { XM
, EXx
} },
9286 { "vrcpss", { XMScalar
, VexScalar
, EXdScalar
} },
9290 { "vaddps", { XM
, Vex
, EXx
} },
9294 { "vaddss", { XMScalar
, VexScalar
, EXdScalar
} },
9298 { "vaddpd", { XM
, Vex
, EXx
} },
9302 { "vaddsd", { XMScalar
, VexScalar
, EXqScalar
} },
9306 { "vmulps", { XM
, Vex
, EXx
} },
9310 { "vmulss", { XMScalar
, VexScalar
, EXdScalar
} },
9314 { "vmulpd", { XM
, Vex
, EXx
} },
9318 { "vmulsd", { XMScalar
, VexScalar
, EXqScalar
} },
9322 { "vcvtps2pd", { XM
, EXxmmq
} },
9326 { "vcvtss2sd", { XMScalar
, VexScalar
, EXdScalar
} },
9330 { "vcvtsd2ss", { XMScalar
, VexScalar
, EXqScalar
} },
9334 { "vcvtdq2ps", { XM
, EXx
} },
9338 { "vcvttps2dq", { XM
, EXx
} },
9342 { "vcvtps2dq", { XM
, EXx
} },
9346 { "vsubps", { XM
, Vex
, EXx
} },
9350 { "vsubss", { XMScalar
, VexScalar
, EXdScalar
} },
9354 { "vsubpd", { XM
, Vex
, EXx
} },
9358 { "vsubsd", { XMScalar
, VexScalar
, EXqScalar
} },
9362 { "vminps", { XM
, Vex
, EXx
} },
9366 { "vminss", { XMScalar
, VexScalar
, EXdScalar
} },
9370 { "vminpd", { XM
, Vex
, EXx
} },
9374 { "vminsd", { XMScalar
, VexScalar
, EXqScalar
} },
9378 { "vdivps", { XM
, Vex
, EXx
} },
9382 { "vdivss", { XMScalar
, VexScalar
, EXdScalar
} },
9386 { "vdivpd", { XM
, Vex
, EXx
} },
9390 { "vdivsd", { XMScalar
, VexScalar
, EXqScalar
} },
9394 { "vmaxps", { XM
, Vex
, EXx
} },
9398 { "vmaxss", { XMScalar
, VexScalar
, EXdScalar
} },
9402 { "vmaxpd", { XM
, Vex
, EXx
} },
9406 { "vmaxsd", { XMScalar
, VexScalar
, EXqScalar
} },
9410 { "vpunpcklbw", { XM
, Vex128
, EXx
} },
9414 { "vpunpcklwd", { XM
, Vex128
, EXx
} },
9418 { "vpunpckldq", { XM
, Vex128
, EXx
} },
9422 { "vpacksswb", { XM
, Vex128
, EXx
} },
9426 { "vpcmpgtb", { XM
, Vex128
, EXx
} },
9430 { "vpcmpgtw", { XM
, Vex128
, EXx
} },
9434 { "vpcmpgtd", { XM
, Vex128
, EXx
} },
9438 { "vpackuswb", { XM
, Vex128
, EXx
} },
9442 { "vpunpckhbw", { XM
, Vex128
, EXx
} },
9446 { "vpunpckhwd", { XM
, Vex128
, EXx
} },
9450 { "vpunpckhdq", { XM
, Vex128
, EXx
} },
9454 { "vpackssdw", { XM
, Vex128
, EXx
} },
9458 { "vpunpcklqdq", { XM
, Vex128
, EXx
} },
9462 { "vpunpckhqdq", { XM
, Vex128
, EXx
} },
9466 { "vmovdqu", { XM
, EXx
} },
9470 { "vmovdqa", { XM
, EXx
} },
9474 { "vpshufhw", { XM
, EXx
, Ib
} },
9478 { "vpshufd", { XM
, EXx
, Ib
} },
9482 { "vpshuflw", { XM
, EXx
, Ib
} },
9485 /* VEX_W_71_R_2_P_2 */
9486 { "vpsrlw", { Vex128
, XS
, Ib
} },
9489 /* VEX_W_71_R_4_P_2 */
9490 { "vpsraw", { Vex128
, XS
, Ib
} },
9493 /* VEX_W_71_R_6_P_2 */
9494 { "vpsllw", { Vex128
, XS
, Ib
} },
9497 /* VEX_W_72_R_2_P_2 */
9498 { "vpsrld", { Vex128
, XS
, Ib
} },
9501 /* VEX_W_72_R_4_P_2 */
9502 { "vpsrad", { Vex128
, XS
, Ib
} },
9505 /* VEX_W_72_R_6_P_2 */
9506 { "vpslld", { Vex128
, XS
, Ib
} },
9509 /* VEX_W_73_R_2_P_2 */
9510 { "vpsrlq", { Vex128
, XS
, Ib
} },
9513 /* VEX_W_73_R_3_P_2 */
9514 { "vpsrldq", { Vex128
, XS
, Ib
} },
9517 /* VEX_W_73_R_6_P_2 */
9518 { "vpsllq", { Vex128
, XS
, Ib
} },
9521 /* VEX_W_73_R_7_P_2 */
9522 { "vpslldq", { Vex128
, XS
, Ib
} },
9526 { "vpcmpeqb", { XM
, Vex128
, EXx
} },
9530 { "vpcmpeqw", { XM
, Vex128
, EXx
} },
9534 { "vpcmpeqd", { XM
, Vex128
, EXx
} },
9542 { "vhaddpd", { XM
, Vex
, EXx
} },
9546 { "vhaddps", { XM
, Vex
, EXx
} },
9550 { "vhsubpd", { XM
, Vex
, EXx
} },
9554 { "vhsubps", { XM
, Vex
, EXx
} },
9558 { "vmovq", { XMScalar
, EXqScalar
} },
9562 { "vmovdqu", { EXxS
, XM
} },
9566 { "vmovdqa", { EXxS
, XM
} },
9569 /* VEX_W_AE_R_2_M_0 */
9570 { "vldmxcsr", { Md
} },
9573 /* VEX_W_AE_R_3_M_0 */
9574 { "vstmxcsr", { Md
} },
9578 { "vcmpps", { XM
, Vex
, EXx
, VCMP
} },
9582 { "vcmpss", { XMScalar
, VexScalar
, EXdScalar
, VCMP
} },
9586 { "vcmppd", { XM
, Vex
, EXx
, VCMP
} },
9590 { "vcmpsd", { XMScalar
, VexScalar
, EXqScalar
, VCMP
} },
9594 { "vpinsrw", { XM
, Vex128
, Edqw
, Ib
} },
9598 { "vpextrw", { Gdq
, XS
, Ib
} },
9602 { "vaddsubpd", { XM
, Vex
, EXx
} },
9606 { "vaddsubps", { XM
, Vex
, EXx
} },
9610 { "vpsrlw", { XM
, Vex128
, EXx
} },
9614 { "vpsrld", { XM
, Vex128
, EXx
} },
9618 { "vpsrlq", { XM
, Vex128
, EXx
} },
9622 { "vpaddq", { XM
, Vex128
, EXx
} },
9626 { "vpmullw", { XM
, Vex128
, EXx
} },
9630 { "vmovq", { EXqScalarS
, XMScalar
} },
9633 /* VEX_W_D7_P_2_M_1 */
9634 { "vpmovmskb", { Gdq
, XS
} },
9638 { "vpsubusb", { XM
, Vex128
, EXx
} },
9642 { "vpsubusw", { XM
, Vex128
, EXx
} },
9646 { "vpminub", { XM
, Vex128
, EXx
} },
9650 { "vpand", { XM
, Vex128
, EXx
} },
9654 { "vpaddusb", { XM
, Vex128
, EXx
} },
9658 { "vpaddusw", { XM
, Vex128
, EXx
} },
9662 { "vpmaxub", { XM
, Vex128
, EXx
} },
9666 { "vpandn", { XM
, Vex128
, EXx
} },
9670 { "vpavgb", { XM
, Vex128
, EXx
} },
9674 { "vpsraw", { XM
, Vex128
, EXx
} },
9678 { "vpsrad", { XM
, Vex128
, EXx
} },
9682 { "vpavgw", { XM
, Vex128
, EXx
} },
9686 { "vpmulhuw", { XM
, Vex128
, EXx
} },
9690 { "vpmulhw", { XM
, Vex128
, EXx
} },
9694 { "vcvtdq2pd", { XM
, EXxmmq
} },
9698 { "vcvttpd2dq%XY", { XMM
, EXx
} },
9702 { "vcvtpd2dq%XY", { XMM
, EXx
} },
9705 /* VEX_W_E7_P_2_M_0 */
9706 { "vmovntdq", { Mx
, XM
} },
9710 { "vpsubsb", { XM
, Vex128
, EXx
} },
9714 { "vpsubsw", { XM
, Vex128
, EXx
} },
9718 { "vpminsw", { XM
, Vex128
, EXx
} },
9722 { "vpor", { XM
, Vex128
, EXx
} },
9726 { "vpaddsb", { XM
, Vex128
, EXx
} },
9730 { "vpaddsw", { XM
, Vex128
, EXx
} },
9734 { "vpmaxsw", { XM
, Vex128
, EXx
} },
9738 { "vpxor", { XM
, Vex128
, EXx
} },
9741 /* VEX_W_F0_P_3_M_0 */
9742 { "vlddqu", { XM
, M
} },
9746 { "vpsllw", { XM
, Vex128
, EXx
} },
9750 { "vpslld", { XM
, Vex128
, EXx
} },
9754 { "vpsllq", { XM
, Vex128
, EXx
} },
9758 { "vpmuludq", { XM
, Vex128
, EXx
} },
9762 { "vpmaddwd", { XM
, Vex128
, EXx
} },
9766 { "vpsadbw", { XM
, Vex128
, EXx
} },
9770 { "vmaskmovdqu", { XM
, XS
} },
9774 { "vpsubb", { XM
, Vex128
, EXx
} },
9778 { "vpsubw", { XM
, Vex128
, EXx
} },
9782 { "vpsubd", { XM
, Vex128
, EXx
} },
9786 { "vpsubq", { XM
, Vex128
, EXx
} },
9790 { "vpaddb", { XM
, Vex128
, EXx
} },
9794 { "vpaddw", { XM
, Vex128
, EXx
} },
9798 { "vpaddd", { XM
, Vex128
, EXx
} },
9801 /* VEX_W_3800_P_2 */
9802 { "vpshufb", { XM
, Vex128
, EXx
} },
9805 /* VEX_W_3801_P_2 */
9806 { "vphaddw", { XM
, Vex128
, EXx
} },
9809 /* VEX_W_3802_P_2 */
9810 { "vphaddd", { XM
, Vex128
, EXx
} },
9813 /* VEX_W_3803_P_2 */
9814 { "vphaddsw", { XM
, Vex128
, EXx
} },
9817 /* VEX_W_3804_P_2 */
9818 { "vpmaddubsw", { XM
, Vex128
, EXx
} },
9821 /* VEX_W_3805_P_2 */
9822 { "vphsubw", { XM
, Vex128
, EXx
} },
9825 /* VEX_W_3806_P_2 */
9826 { "vphsubd", { XM
, Vex128
, EXx
} },
9829 /* VEX_W_3807_P_2 */
9830 { "vphsubsw", { XM
, Vex128
, EXx
} },
9833 /* VEX_W_3808_P_2 */
9834 { "vpsignb", { XM
, Vex128
, EXx
} },
9837 /* VEX_W_3809_P_2 */
9838 { "vpsignw", { XM
, Vex128
, EXx
} },
9841 /* VEX_W_380A_P_2 */
9842 { "vpsignd", { XM
, Vex128
, EXx
} },
9845 /* VEX_W_380B_P_2 */
9846 { "vpmulhrsw", { XM
, Vex128
, EXx
} },
9849 /* VEX_W_380C_P_2 */
9850 { "vpermilps", { XM
, Vex
, EXx
} },
9853 /* VEX_W_380D_P_2 */
9854 { "vpermilpd", { XM
, Vex
, EXx
} },
9857 /* VEX_W_380E_P_2 */
9858 { "vtestps", { XM
, EXx
} },
9861 /* VEX_W_380F_P_2 */
9862 { "vtestpd", { XM
, EXx
} },
9865 /* VEX_W_3817_P_2 */
9866 { "vptest", { XM
, EXx
} },
9869 /* VEX_W_3818_P_2_M_0 */
9870 { "vbroadcastss", { XM
, Md
} },
9873 /* VEX_W_3819_P_2_M_0 */
9874 { "vbroadcastsd", { XM
, Mq
} },
9877 /* VEX_W_381A_P_2_M_0 */
9878 { "vbroadcastf128", { XM
, Mxmm
} },
9881 /* VEX_W_381C_P_2 */
9882 { "vpabsb", { XM
, EXx
} },
9885 /* VEX_W_381D_P_2 */
9886 { "vpabsw", { XM
, EXx
} },
9889 /* VEX_W_381E_P_2 */
9890 { "vpabsd", { XM
, EXx
} },
9893 /* VEX_W_3820_P_2 */
9894 { "vpmovsxbw", { XM
, EXq
} },
9897 /* VEX_W_3821_P_2 */
9898 { "vpmovsxbd", { XM
, EXd
} },
9901 /* VEX_W_3822_P_2 */
9902 { "vpmovsxbq", { XM
, EXw
} },
9905 /* VEX_W_3823_P_2 */
9906 { "vpmovsxwd", { XM
, EXq
} },
9909 /* VEX_W_3824_P_2 */
9910 { "vpmovsxwq", { XM
, EXd
} },
9913 /* VEX_W_3825_P_2 */
9914 { "vpmovsxdq", { XM
, EXq
} },
9917 /* VEX_W_3828_P_2 */
9918 { "vpmuldq", { XM
, Vex128
, EXx
} },
9921 /* VEX_W_3829_P_2 */
9922 { "vpcmpeqq", { XM
, Vex128
, EXx
} },
9925 /* VEX_W_382A_P_2_M_0 */
9926 { "vmovntdqa", { XM
, Mx
} },
9929 /* VEX_W_382B_P_2 */
9930 { "vpackusdw", { XM
, Vex128
, EXx
} },
9933 /* VEX_W_382C_P_2_M_0 */
9934 { "vmaskmovps", { XM
, Vex
, Mx
} },
9937 /* VEX_W_382D_P_2_M_0 */
9938 { "vmaskmovpd", { XM
, Vex
, Mx
} },
9941 /* VEX_W_382E_P_2_M_0 */
9942 { "vmaskmovps", { Mx
, Vex
, XM
} },
9945 /* VEX_W_382F_P_2_M_0 */
9946 { "vmaskmovpd", { Mx
, Vex
, XM
} },
9949 /* VEX_W_3830_P_2 */
9950 { "vpmovzxbw", { XM
, EXq
} },
9953 /* VEX_W_3831_P_2 */
9954 { "vpmovzxbd", { XM
, EXd
} },
9957 /* VEX_W_3832_P_2 */
9958 { "vpmovzxbq", { XM
, EXw
} },
9961 /* VEX_W_3833_P_2 */
9962 { "vpmovzxwd", { XM
, EXq
} },
9965 /* VEX_W_3834_P_2 */
9966 { "vpmovzxwq", { XM
, EXd
} },
9969 /* VEX_W_3835_P_2 */
9970 { "vpmovzxdq", { XM
, EXq
} },
9973 /* VEX_W_3837_P_2 */
9974 { "vpcmpgtq", { XM
, Vex128
, EXx
} },
9977 /* VEX_W_3838_P_2 */
9978 { "vpminsb", { XM
, Vex128
, EXx
} },
9981 /* VEX_W_3839_P_2 */
9982 { "vpminsd", { XM
, Vex128
, EXx
} },
9985 /* VEX_W_383A_P_2 */
9986 { "vpminuw", { XM
, Vex128
, EXx
} },
9989 /* VEX_W_383B_P_2 */
9990 { "vpminud", { XM
, Vex128
, EXx
} },
9993 /* VEX_W_383C_P_2 */
9994 { "vpmaxsb", { XM
, Vex128
, EXx
} },
9997 /* VEX_W_383D_P_2 */
9998 { "vpmaxsd", { XM
, Vex128
, EXx
} },
10001 /* VEX_W_383E_P_2 */
10002 { "vpmaxuw", { XM
, Vex128
, EXx
} },
10005 /* VEX_W_383F_P_2 */
10006 { "vpmaxud", { XM
, Vex128
, EXx
} },
10009 /* VEX_W_3840_P_2 */
10010 { "vpmulld", { XM
, Vex128
, EXx
} },
10013 /* VEX_W_3841_P_2 */
10014 { "vphminposuw", { XM
, EXx
} },
10017 /* VEX_W_38DB_P_2 */
10018 { "vaesimc", { XM
, EXx
} },
10021 /* VEX_W_38DC_P_2 */
10022 { "vaesenc", { XM
, Vex128
, EXx
} },
10025 /* VEX_W_38DD_P_2 */
10026 { "vaesenclast", { XM
, Vex128
, EXx
} },
10029 /* VEX_W_38DE_P_2 */
10030 { "vaesdec", { XM
, Vex128
, EXx
} },
10033 /* VEX_W_38DF_P_2 */
10034 { "vaesdeclast", { XM
, Vex128
, EXx
} },
10037 /* VEX_W_3A04_P_2 */
10038 { "vpermilps", { XM
, EXx
, Ib
} },
10041 /* VEX_W_3A05_P_2 */
10042 { "vpermilpd", { XM
, EXx
, Ib
} },
10045 /* VEX_W_3A06_P_2 */
10046 { "vperm2f128", { XM
, Vex256
, EXx
, Ib
} },
10049 /* VEX_W_3A08_P_2 */
10050 { "vroundps", { XM
, EXx
, Ib
} },
10053 /* VEX_W_3A09_P_2 */
10054 { "vroundpd", { XM
, EXx
, Ib
} },
10057 /* VEX_W_3A0A_P_2 */
10058 { "vroundss", { XMScalar
, VexScalar
, EXdScalar
, Ib
} },
10061 /* VEX_W_3A0B_P_2 */
10062 { "vroundsd", { XMScalar
, VexScalar
, EXqScalar
, Ib
} },
10065 /* VEX_W_3A0C_P_2 */
10066 { "vblendps", { XM
, Vex
, EXx
, Ib
} },
10069 /* VEX_W_3A0D_P_2 */
10070 { "vblendpd", { XM
, Vex
, EXx
, Ib
} },
10073 /* VEX_W_3A0E_P_2 */
10074 { "vpblendw", { XM
, Vex128
, EXx
, Ib
} },
10077 /* VEX_W_3A0F_P_2 */
10078 { "vpalignr", { XM
, Vex128
, EXx
, Ib
} },
10081 /* VEX_W_3A14_P_2 */
10082 { "vpextrb", { Edqb
, XM
, Ib
} },
10085 /* VEX_W_3A15_P_2 */
10086 { "vpextrw", { Edqw
, XM
, Ib
} },
10089 /* VEX_W_3A18_P_2 */
10090 { "vinsertf128", { XM
, Vex256
, EXxmm
, Ib
} },
10093 /* VEX_W_3A19_P_2 */
10094 { "vextractf128", { EXxmm
, XM
, Ib
} },
10097 /* VEX_W_3A20_P_2 */
10098 { "vpinsrb", { XM
, Vex128
, Edqb
, Ib
} },
10101 /* VEX_W_3A21_P_2 */
10102 { "vinsertps", { XM
, Vex128
, EXd
, Ib
} },
10105 /* VEX_W_3A40_P_2 */
10106 { "vdpps", { XM
, Vex
, EXx
, Ib
} },
10109 /* VEX_W_3A41_P_2 */
10110 { "vdppd", { XM
, Vex128
, EXx
, Ib
} },
10113 /* VEX_W_3A42_P_2 */
10114 { "vmpsadbw", { XM
, Vex128
, EXx
, Ib
} },
10117 /* VEX_W_3A44_P_2 */
10118 { "vpclmulqdq", { XM
, Vex128
, EXx
, PCLMUL
} },
10121 /* VEX_W_3A4A_P_2 */
10122 { "vblendvps", { XM
, Vex
, EXx
, XMVexI4
} },
10125 /* VEX_W_3A4B_P_2 */
10126 { "vblendvpd", { XM
, Vex
, EXx
, XMVexI4
} },
10129 /* VEX_W_3A4C_P_2 */
10130 { "vpblendvb", { XM
, Vex128
, EXx
, XMVexI4
} },
10133 /* VEX_W_3A60_P_2 */
10134 { "vpcmpestrm", { XM
, EXx
, Ib
} },
10137 /* VEX_W_3A61_P_2 */
10138 { "vpcmpestri", { XM
, EXx
, Ib
} },
10141 /* VEX_W_3A62_P_2 */
10142 { "vpcmpistrm", { XM
, EXx
, Ib
} },
10145 /* VEX_W_3A63_P_2 */
10146 { "vpcmpistri", { XM
, EXx
, Ib
} },
10149 /* VEX_W_3ADF_P_2 */
10150 { "vaeskeygenassist", { XM
, EXx
, Ib
} },
10154 static const struct dis386 mod_table
[][2] = {
10157 { "leaS", { Gv
, M
} },
10160 /* MOD_0F01_REG_0 */
10161 { X86_64_TABLE (X86_64_0F01_REG_0
) },
10162 { RM_TABLE (RM_0F01_REG_0
) },
10165 /* MOD_0F01_REG_1 */
10166 { X86_64_TABLE (X86_64_0F01_REG_1
) },
10167 { RM_TABLE (RM_0F01_REG_1
) },
10170 /* MOD_0F01_REG_2 */
10171 { X86_64_TABLE (X86_64_0F01_REG_2
) },
10172 { RM_TABLE (RM_0F01_REG_2
) },
10175 /* MOD_0F01_REG_3 */
10176 { X86_64_TABLE (X86_64_0F01_REG_3
) },
10177 { RM_TABLE (RM_0F01_REG_3
) },
10180 /* MOD_0F01_REG_7 */
10181 { "invlpg", { Mb
} },
10182 { RM_TABLE (RM_0F01_REG_7
) },
10185 /* MOD_0F12_PREFIX_0 */
10186 { "movlps", { XM
, EXq
} },
10187 { "movhlps", { XM
, EXq
} },
10191 { "movlpX", { EXq
, XM
} },
10194 /* MOD_0F16_PREFIX_0 */
10195 { "movhps", { XM
, EXq
} },
10196 { "movlhps", { XM
, EXq
} },
10200 { "movhpX", { EXq
, XM
} },
10203 /* MOD_0F18_REG_0 */
10204 { "prefetchnta", { Mb
} },
10207 /* MOD_0F18_REG_1 */
10208 { "prefetcht0", { Mb
} },
10211 /* MOD_0F18_REG_2 */
10212 { "prefetcht1", { Mb
} },
10215 /* MOD_0F18_REG_3 */
10216 { "prefetcht2", { Mb
} },
10221 { "movZ", { Rm
, Cm
} },
10226 { "movZ", { Rm
, Dm
} },
10231 { "movZ", { Cm
, Rm
} },
10236 { "movZ", { Dm
, Rm
} },
10241 { "movL", { Rd
, Td
} },
10246 { "movL", { Td
, Rd
} },
10249 /* MOD_0F2B_PREFIX_0 */
10250 {"movntps", { Mx
, XM
} },
10253 /* MOD_0F2B_PREFIX_1 */
10254 {"movntss", { Md
, XM
} },
10257 /* MOD_0F2B_PREFIX_2 */
10258 {"movntpd", { Mx
, XM
} },
10261 /* MOD_0F2B_PREFIX_3 */
10262 {"movntsd", { Mq
, XM
} },
10267 { "movmskpX", { Gdq
, XS
} },
10270 /* MOD_0F71_REG_2 */
10272 { "psrlw", { MS
, Ib
} },
10275 /* MOD_0F71_REG_4 */
10277 { "psraw", { MS
, Ib
} },
10280 /* MOD_0F71_REG_6 */
10282 { "psllw", { MS
, Ib
} },
10285 /* MOD_0F72_REG_2 */
10287 { "psrld", { MS
, Ib
} },
10290 /* MOD_0F72_REG_4 */
10292 { "psrad", { MS
, Ib
} },
10295 /* MOD_0F72_REG_6 */
10297 { "pslld", { MS
, Ib
} },
10300 /* MOD_0F73_REG_2 */
10302 { "psrlq", { MS
, Ib
} },
10305 /* MOD_0F73_REG_3 */
10307 { PREFIX_TABLE (PREFIX_0F73_REG_3
) },
10310 /* MOD_0F73_REG_6 */
10312 { "psllq", { MS
, Ib
} },
10315 /* MOD_0F73_REG_7 */
10317 { PREFIX_TABLE (PREFIX_0F73_REG_7
) },
10320 /* MOD_0FAE_REG_0 */
10321 { "fxsave", { FXSAVE
} },
10324 /* MOD_0FAE_REG_1 */
10325 { "fxrstor", { FXSAVE
} },
10328 /* MOD_0FAE_REG_2 */
10329 { "ldmxcsr", { Md
} },
10332 /* MOD_0FAE_REG_3 */
10333 { "stmxcsr", { Md
} },
10336 /* MOD_0FAE_REG_4 */
10337 { "xsave", { FXSAVE
} },
10340 /* MOD_0FAE_REG_5 */
10341 { "xrstor", { FXSAVE
} },
10342 { RM_TABLE (RM_0FAE_REG_5
) },
10345 /* MOD_0FAE_REG_6 */
10347 { RM_TABLE (RM_0FAE_REG_6
) },
10350 /* MOD_0FAE_REG_7 */
10351 { "clflush", { Mb
} },
10352 { RM_TABLE (RM_0FAE_REG_7
) },
10356 { "lssS", { Gv
, Mp
} },
10360 { "lfsS", { Gv
, Mp
} },
10364 { "lgsS", { Gv
, Mp
} },
10367 /* MOD_0FC7_REG_6 */
10368 { PREFIX_TABLE (PREFIX_0FC7_REG_6
) },
10371 /* MOD_0FC7_REG_7 */
10372 { "vmptrst", { Mq
} },
10377 { "pmovmskb", { Gdq
, MS
} },
10380 /* MOD_0FE7_PREFIX_2 */
10381 { "movntdq", { Mx
, XM
} },
10384 /* MOD_0FF0_PREFIX_3 */
10385 { "lddqu", { XM
, M
} },
10388 /* MOD_0F382A_PREFIX_2 */
10389 { "movntdqa", { XM
, Mx
} },
10393 { "bound{S|}", { Gv
, Ma
} },
10397 { "lesS", { Gv
, Mp
} },
10398 { VEX_C4_TABLE (VEX_0F
) },
10402 { "ldsS", { Gv
, Mp
} },
10403 { VEX_C5_TABLE (VEX_0F
) },
10406 /* MOD_VEX_12_PREFIX_0 */
10407 { VEX_LEN_TABLE (VEX_LEN_12_P_0_M_0
) },
10408 { VEX_LEN_TABLE (VEX_LEN_12_P_0_M_1
) },
10412 { VEX_LEN_TABLE (VEX_LEN_13_M_0
) },
10415 /* MOD_VEX_16_PREFIX_0 */
10416 { VEX_LEN_TABLE (VEX_LEN_16_P_0_M_0
) },
10417 { VEX_LEN_TABLE (VEX_LEN_16_P_0_M_1
) },
10421 { VEX_LEN_TABLE (VEX_LEN_17_M_0
) },
10425 { VEX_W_TABLE (VEX_W_2B_M_0
) },
10430 { VEX_W_TABLE (VEX_W_50_M_0
) },
10433 /* MOD_VEX_71_REG_2 */
10435 { PREFIX_TABLE (PREFIX_VEX_71_REG_2
) },
10438 /* MOD_VEX_71_REG_4 */
10440 { PREFIX_TABLE (PREFIX_VEX_71_REG_4
) },
10443 /* MOD_VEX_71_REG_6 */
10445 { PREFIX_TABLE (PREFIX_VEX_71_REG_6
) },
10448 /* MOD_VEX_72_REG_2 */
10450 { PREFIX_TABLE (PREFIX_VEX_72_REG_2
) },
10453 /* MOD_VEX_72_REG_4 */
10455 { PREFIX_TABLE (PREFIX_VEX_72_REG_4
) },
10458 /* MOD_VEX_72_REG_6 */
10460 { PREFIX_TABLE (PREFIX_VEX_72_REG_6
) },
10463 /* MOD_VEX_73_REG_2 */
10465 { PREFIX_TABLE (PREFIX_VEX_73_REG_2
) },
10468 /* MOD_VEX_73_REG_3 */
10470 { PREFIX_TABLE (PREFIX_VEX_73_REG_3
) },
10473 /* MOD_VEX_73_REG_6 */
10475 { PREFIX_TABLE (PREFIX_VEX_73_REG_6
) },
10478 /* MOD_VEX_73_REG_7 */
10480 { PREFIX_TABLE (PREFIX_VEX_73_REG_7
) },
10483 /* MOD_VEX_AE_REG_2 */
10484 { VEX_LEN_TABLE (VEX_LEN_AE_R_2_M_0
) },
10487 /* MOD_VEX_AE_REG_3 */
10488 { VEX_LEN_TABLE (VEX_LEN_AE_R_3_M_0
) },
10491 /* MOD_VEX_D7_PREFIX_2 */
10493 { VEX_LEN_TABLE (VEX_LEN_D7_P_2_M_1
) },
10496 /* MOD_VEX_E7_PREFIX_2 */
10497 { VEX_W_TABLE (VEX_W_E7_P_2_M_0
) },
10500 /* MOD_VEX_F0_PREFIX_3 */
10501 { VEX_W_TABLE (VEX_W_F0_P_3_M_0
) },
10504 /* MOD_VEX_3818_PREFIX_2 */
10505 { VEX_W_TABLE (VEX_W_3818_P_2_M_0
) },
10508 /* MOD_VEX_3819_PREFIX_2 */
10509 { VEX_LEN_TABLE (VEX_LEN_3819_P_2_M_0
) },
10512 /* MOD_VEX_381A_PREFIX_2 */
10513 { VEX_LEN_TABLE (VEX_LEN_381A_P_2_M_0
) },
10516 /* MOD_VEX_382A_PREFIX_2 */
10517 { VEX_LEN_TABLE (VEX_LEN_382A_P_2_M_0
) },
10520 /* MOD_VEX_382C_PREFIX_2 */
10521 { VEX_W_TABLE (VEX_W_382C_P_2_M_0
) },
10524 /* MOD_VEX_382D_PREFIX_2 */
10525 { VEX_W_TABLE (VEX_W_382D_P_2_M_0
) },
10528 /* MOD_VEX_382E_PREFIX_2 */
10529 { VEX_W_TABLE (VEX_W_382E_P_2_M_0
) },
10532 /* MOD_VEX_382F_PREFIX_2 */
10533 { VEX_W_TABLE (VEX_W_382F_P_2_M_0
) },
10537 static const struct dis386 rm_table
[][8] = {
10539 /* RM_0F01_REG_0 */
10541 { "vmcall", { Skip_MODRM
} },
10542 { "vmlaunch", { Skip_MODRM
} },
10543 { "vmresume", { Skip_MODRM
} },
10544 { "vmxoff", { Skip_MODRM
} },
10547 /* RM_0F01_REG_1 */
10548 { "monitor", { { OP_Monitor
, 0 } } },
10549 { "mwait", { { OP_Mwait
, 0 } } },
10552 /* RM_0F01_REG_2 */
10553 { "xgetbv", { Skip_MODRM
} },
10554 { "xsetbv", { Skip_MODRM
} },
10557 /* RM_0F01_REG_3 */
10558 { "vmrun", { Skip_MODRM
} },
10559 { "vmmcall", { Skip_MODRM
} },
10560 { "vmload", { Skip_MODRM
} },
10561 { "vmsave", { Skip_MODRM
} },
10562 { "stgi", { Skip_MODRM
} },
10563 { "clgi", { Skip_MODRM
} },
10564 { "skinit", { Skip_MODRM
} },
10565 { "invlpga", { Skip_MODRM
} },
10568 /* RM_0F01_REG_7 */
10569 { "swapgs", { Skip_MODRM
} },
10570 { "rdtscp", { Skip_MODRM
} },
10573 /* RM_0FAE_REG_5 */
10574 { "lfence", { Skip_MODRM
} },
10577 /* RM_0FAE_REG_6 */
10578 { "mfence", { Skip_MODRM
} },
10581 /* RM_0FAE_REG_7 */
10582 { "sfence", { Skip_MODRM
} },
10586 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
10588 /* We use the high bit to indicate different name for the same
10590 #define ADDR16_PREFIX (0x67 | 0x100)
10591 #define ADDR32_PREFIX (0x67 | 0x200)
10592 #define DATA16_PREFIX (0x66 | 0x100)
10593 #define DATA32_PREFIX (0x66 | 0x200)
10594 #define REP_PREFIX (0xf3 | 0x100)
10599 int newrex
, i
, length
;
10605 last_lock_prefix
= -1;
10606 last_repz_prefix
= -1;
10607 last_repnz_prefix
= -1;
10608 last_data_prefix
= -1;
10609 last_addr_prefix
= -1;
10610 last_rex_prefix
= -1;
10611 last_seg_prefix
= -1;
10612 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
10613 all_prefixes
[i
] = 0;
10616 /* The maximum instruction length is 15bytes. */
10617 while (length
< MAX_CODE_LENGTH
- 1)
10619 FETCH_DATA (the_info
, codep
+ 1);
10623 /* REX prefixes family. */
10640 if (address_mode
== mode_64bit
)
10644 last_rex_prefix
= i
;
10647 prefixes
|= PREFIX_REPZ
;
10648 last_repz_prefix
= i
;
10651 prefixes
|= PREFIX_REPNZ
;
10652 last_repnz_prefix
= i
;
10655 prefixes
|= PREFIX_LOCK
;
10656 last_lock_prefix
= i
;
10659 prefixes
|= PREFIX_CS
;
10660 last_seg_prefix
= i
;
10663 prefixes
|= PREFIX_SS
;
10664 last_seg_prefix
= i
;
10667 prefixes
|= PREFIX_DS
;
10668 last_seg_prefix
= i
;
10671 prefixes
|= PREFIX_ES
;
10672 last_seg_prefix
= i
;
10675 prefixes
|= PREFIX_FS
;
10676 last_seg_prefix
= i
;
10679 prefixes
|= PREFIX_GS
;
10680 last_seg_prefix
= i
;
10683 prefixes
|= PREFIX_DATA
;
10684 last_data_prefix
= i
;
10687 prefixes
|= PREFIX_ADDR
;
10688 last_addr_prefix
= i
;
10691 /* fwait is really an instruction. If there are prefixes
10692 before the fwait, they belong to the fwait, *not* to the
10693 following instruction. */
10694 if (prefixes
|| rex
)
10696 prefixes
|= PREFIX_FWAIT
;
10700 prefixes
= PREFIX_FWAIT
;
10705 /* Rex is ignored when followed by another prefix. */
10711 if (*codep
!= FWAIT_OPCODE
)
10712 all_prefixes
[i
++] = *codep
;
10721 seg_prefix (int pref
)
10742 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
10745 static const char *
10746 prefix_name (int pref
, int sizeflag
)
10748 static const char *rexes
[16] =
10751 "rex.B", /* 0x41 */
10752 "rex.X", /* 0x42 */
10753 "rex.XB", /* 0x43 */
10754 "rex.R", /* 0x44 */
10755 "rex.RB", /* 0x45 */
10756 "rex.RX", /* 0x46 */
10757 "rex.RXB", /* 0x47 */
10758 "rex.W", /* 0x48 */
10759 "rex.WB", /* 0x49 */
10760 "rex.WX", /* 0x4a */
10761 "rex.WXB", /* 0x4b */
10762 "rex.WR", /* 0x4c */
10763 "rex.WRB", /* 0x4d */
10764 "rex.WRX", /* 0x4e */
10765 "rex.WRXB", /* 0x4f */
10770 /* REX prefixes family. */
10787 return rexes
[pref
- 0x40];
10807 return (sizeflag
& DFLAG
) ? "data16" : "data32";
10809 if (address_mode
== mode_64bit
)
10810 return (sizeflag
& AFLAG
) ? "addr32" : "addr64";
10812 return (sizeflag
& AFLAG
) ? "addr16" : "addr32";
10815 case ADDR16_PREFIX
:
10817 case ADDR32_PREFIX
:
10819 case DATA16_PREFIX
:
10821 case DATA32_PREFIX
:
10830 static char op_out
[MAX_OPERANDS
][100];
10831 static int op_ad
, op_index
[MAX_OPERANDS
];
10832 static int two_source_ops
;
10833 static bfd_vma op_address
[MAX_OPERANDS
];
10834 static bfd_vma op_riprel
[MAX_OPERANDS
];
10835 static bfd_vma start_pc
;
10838 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
10839 * (see topic "Redundant prefixes" in the "Differences from 8086"
10840 * section of the "Virtual 8086 Mode" chapter.)
10841 * 'pc' should be the address of this instruction, it will
10842 * be used to print the target address if this is a relative jump or call
10843 * The function returns the length of this instruction in bytes.
10846 static char intel_syntax
;
10847 static char intel_mnemonic
= !SYSV386_COMPAT
;
10848 static char open_char
;
10849 static char close_char
;
10850 static char separator_char
;
10851 static char scale_char
;
10853 /* Here for backwards compatibility. When gdb stops using
10854 print_insn_i386_att and print_insn_i386_intel these functions can
10855 disappear, and print_insn_i386 be merged into print_insn. */
10857 print_insn_i386_att (bfd_vma pc
, disassemble_info
*info
)
10861 return print_insn (pc
, info
);
10865 print_insn_i386_intel (bfd_vma pc
, disassemble_info
*info
)
10869 return print_insn (pc
, info
);
10873 print_insn_i386 (bfd_vma pc
, disassemble_info
*info
)
10877 return print_insn (pc
, info
);
10881 print_i386_disassembler_options (FILE *stream
)
10883 fprintf (stream
, _("\n\
10884 The following i386/x86-64 specific disassembler options are supported for use\n\
10885 with the -M switch (multiple options should be separated by commas):\n"));
10887 fprintf (stream
, _(" x86-64 Disassemble in 64bit mode\n"));
10888 fprintf (stream
, _(" i386 Disassemble in 32bit mode\n"));
10889 fprintf (stream
, _(" i8086 Disassemble in 16bit mode\n"));
10890 fprintf (stream
, _(" att Display instruction in AT&T syntax\n"));
10891 fprintf (stream
, _(" intel Display instruction in Intel syntax\n"));
10892 fprintf (stream
, _(" att-mnemonic\n"
10893 " Display instruction in AT&T mnemonic\n"));
10894 fprintf (stream
, _(" intel-mnemonic\n"
10895 " Display instruction in Intel mnemonic\n"));
10896 fprintf (stream
, _(" addr64 Assume 64bit address size\n"));
10897 fprintf (stream
, _(" addr32 Assume 32bit address size\n"));
10898 fprintf (stream
, _(" addr16 Assume 16bit address size\n"));
10899 fprintf (stream
, _(" data32 Assume 32bit data size\n"));
10900 fprintf (stream
, _(" data16 Assume 16bit data size\n"));
10901 fprintf (stream
, _(" suffix Always display instruction suffix in AT&T syntax\n"));
10905 static const struct dis386 bad_opcode
= { "(bad)", { XX
} };
10907 /* Get a pointer to struct dis386 with a valid name. */
10909 static const struct dis386
*
10910 get_valid_dis386 (const struct dis386
*dp
, disassemble_info
*info
)
10912 int vindex
, vex_table_index
;
10914 if (dp
->name
!= NULL
)
10917 switch (dp
->op
[0].bytemode
)
10919 case USE_REG_TABLE
:
10920 dp
= ®_table
[dp
->op
[1].bytemode
][modrm
.reg
];
10923 case USE_MOD_TABLE
:
10924 vindex
= modrm
.mod
== 0x3 ? 1 : 0;
10925 dp
= &mod_table
[dp
->op
[1].bytemode
][vindex
];
10929 dp
= &rm_table
[dp
->op
[1].bytemode
][modrm
.rm
];
10932 case USE_PREFIX_TABLE
:
10935 /* The prefix in VEX is implicit. */
10936 switch (vex
.prefix
)
10941 case REPE_PREFIX_OPCODE
:
10944 case DATA_PREFIX_OPCODE
:
10947 case REPNE_PREFIX_OPCODE
:
10958 used_prefixes
|= (prefixes
& PREFIX_REPZ
);
10959 if (prefixes
& PREFIX_REPZ
)
10962 all_prefixes
[last_repz_prefix
] = 0;
10966 /* We should check PREFIX_REPNZ and PREFIX_REPZ before
10968 used_prefixes
|= (prefixes
& PREFIX_REPNZ
);
10969 if (prefixes
& PREFIX_REPNZ
)
10972 all_prefixes
[last_repnz_prefix
] = 0;
10976 used_prefixes
|= (prefixes
& PREFIX_DATA
);
10977 if (prefixes
& PREFIX_DATA
)
10980 all_prefixes
[last_data_prefix
] = 0;
10985 dp
= &prefix_table
[dp
->op
[1].bytemode
][vindex
];
10988 case USE_X86_64_TABLE
:
10989 vindex
= address_mode
== mode_64bit
? 1 : 0;
10990 dp
= &x86_64_table
[dp
->op
[1].bytemode
][vindex
];
10993 case USE_3BYTE_TABLE
:
10994 FETCH_DATA (info
, codep
+ 2);
10996 dp
= &three_byte_table
[dp
->op
[1].bytemode
][vindex
];
10997 modrm
.mod
= (*codep
>> 6) & 3;
10998 modrm
.reg
= (*codep
>> 3) & 7;
10999 modrm
.rm
= *codep
& 7;
11002 case USE_VEX_LEN_TABLE
:
11006 switch (vex
.length
)
11019 dp
= &vex_len_table
[dp
->op
[1].bytemode
][vindex
];
11022 case USE_XOP_8F_TABLE
:
11023 FETCH_DATA (info
, codep
+ 3);
11024 /* All bits in the REX prefix are ignored. */
11026 rex
= ~(*codep
>> 5) & 0x7;
11028 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
11029 switch ((*codep
& 0x1f))
11034 vex_table_index
= XOP_08
;
11037 vex_table_index
= XOP_09
;
11040 vex_table_index
= XOP_0A
;
11044 vex
.w
= *codep
& 0x80;
11045 if (vex
.w
&& address_mode
== mode_64bit
)
11048 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11049 if (address_mode
!= mode_64bit
11050 && vex
.register_specifier
> 0x7)
11053 vex
.length
= (*codep
& 0x4) ? 256 : 128;
11054 switch ((*codep
& 0x3))
11060 vex
.prefix
= DATA_PREFIX_OPCODE
;
11063 vex
.prefix
= REPE_PREFIX_OPCODE
;
11066 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11073 dp
= &xop_table
[vex_table_index
][vindex
];
11075 FETCH_DATA (info
, codep
+ 1);
11076 modrm
.mod
= (*codep
>> 6) & 3;
11077 modrm
.reg
= (*codep
>> 3) & 7;
11078 modrm
.rm
= *codep
& 7;
11081 case USE_VEX_C4_TABLE
:
11082 FETCH_DATA (info
, codep
+ 3);
11083 /* All bits in the REX prefix are ignored. */
11085 rex
= ~(*codep
>> 5) & 0x7;
11086 switch ((*codep
& 0x1f))
11091 vex_table_index
= VEX_0F
;
11094 vex_table_index
= VEX_0F38
;
11097 vex_table_index
= VEX_0F3A
;
11101 vex
.w
= *codep
& 0x80;
11102 if (vex
.w
&& address_mode
== mode_64bit
)
11105 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11106 if (address_mode
!= mode_64bit
11107 && vex
.register_specifier
> 0x7)
11110 vex
.length
= (*codep
& 0x4) ? 256 : 128;
11111 switch ((*codep
& 0x3))
11117 vex
.prefix
= DATA_PREFIX_OPCODE
;
11120 vex
.prefix
= REPE_PREFIX_OPCODE
;
11123 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11130 dp
= &vex_table
[vex_table_index
][vindex
];
11131 /* There is no MODRM byte for VEX [82|77]. */
11132 if (vindex
!= 0x77 && vindex
!= 0x82)
11134 FETCH_DATA (info
, codep
+ 1);
11135 modrm
.mod
= (*codep
>> 6) & 3;
11136 modrm
.reg
= (*codep
>> 3) & 7;
11137 modrm
.rm
= *codep
& 7;
11141 case USE_VEX_C5_TABLE
:
11142 FETCH_DATA (info
, codep
+ 2);
11143 /* All bits in the REX prefix are ignored. */
11145 rex
= (*codep
& 0x80) ? 0 : REX_R
;
11147 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11148 if (address_mode
!= mode_64bit
11149 && vex
.register_specifier
> 0x7)
11154 vex
.length
= (*codep
& 0x4) ? 256 : 128;
11155 switch ((*codep
& 0x3))
11161 vex
.prefix
= DATA_PREFIX_OPCODE
;
11164 vex
.prefix
= REPE_PREFIX_OPCODE
;
11167 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11174 dp
= &vex_table
[dp
->op
[1].bytemode
][vindex
];
11175 /* There is no MODRM byte for VEX [82|77]. */
11176 if (vindex
!= 0x77 && vindex
!= 0x82)
11178 FETCH_DATA (info
, codep
+ 1);
11179 modrm
.mod
= (*codep
>> 6) & 3;
11180 modrm
.reg
= (*codep
>> 3) & 7;
11181 modrm
.rm
= *codep
& 7;
11185 case USE_VEX_W_TABLE
:
11189 dp
= &vex_w_table
[dp
->op
[1].bytemode
][vex
.w
? 1 : 0];
11200 if (dp
->name
!= NULL
)
11203 return get_valid_dis386 (dp
, info
);
11207 print_insn (bfd_vma pc
, disassemble_info
*info
)
11209 const struct dis386
*dp
;
11211 char *op_txt
[MAX_OPERANDS
];
11215 struct dis_private priv
;
11218 int default_prefixes
;
11220 if (info
->mach
== bfd_mach_x86_64_intel_syntax
11221 || info
->mach
== bfd_mach_x86_64
11222 || info
->mach
== bfd_mach_l1om
11223 || info
->mach
== bfd_mach_l1om_intel_syntax
)
11224 address_mode
= mode_64bit
;
11226 address_mode
= mode_32bit
;
11228 if (intel_syntax
== (char) -1)
11229 intel_syntax
= (info
->mach
== bfd_mach_i386_i386_intel_syntax
11230 || info
->mach
== bfd_mach_x86_64_intel_syntax
11231 || info
->mach
== bfd_mach_l1om_intel_syntax
);
11233 if (info
->mach
== bfd_mach_i386_i386
11234 || info
->mach
== bfd_mach_x86_64
11235 || info
->mach
== bfd_mach_l1om
11236 || info
->mach
== bfd_mach_i386_i386_intel_syntax
11237 || info
->mach
== bfd_mach_x86_64_intel_syntax
11238 || info
->mach
== bfd_mach_l1om_intel_syntax
)
11239 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
11240 else if (info
->mach
== bfd_mach_i386_i8086
)
11241 priv
.orig_sizeflag
= 0;
11245 for (p
= info
->disassembler_options
; p
!= NULL
; )
11247 if (CONST_STRNEQ (p
, "x86-64"))
11249 address_mode
= mode_64bit
;
11250 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
11252 else if (CONST_STRNEQ (p
, "i386"))
11254 address_mode
= mode_32bit
;
11255 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
11257 else if (CONST_STRNEQ (p
, "i8086"))
11259 address_mode
= mode_16bit
;
11260 priv
.orig_sizeflag
= 0;
11262 else if (CONST_STRNEQ (p
, "intel"))
11265 if (CONST_STRNEQ (p
+ 5, "-mnemonic"))
11266 intel_mnemonic
= 1;
11268 else if (CONST_STRNEQ (p
, "att"))
11271 if (CONST_STRNEQ (p
+ 3, "-mnemonic"))
11272 intel_mnemonic
= 0;
11274 else if (CONST_STRNEQ (p
, "addr"))
11276 if (address_mode
== mode_64bit
)
11278 if (p
[4] == '3' && p
[5] == '2')
11279 priv
.orig_sizeflag
&= ~AFLAG
;
11280 else if (p
[4] == '6' && p
[5] == '4')
11281 priv
.orig_sizeflag
|= AFLAG
;
11285 if (p
[4] == '1' && p
[5] == '6')
11286 priv
.orig_sizeflag
&= ~AFLAG
;
11287 else if (p
[4] == '3' && p
[5] == '2')
11288 priv
.orig_sizeflag
|= AFLAG
;
11291 else if (CONST_STRNEQ (p
, "data"))
11293 if (p
[4] == '1' && p
[5] == '6')
11294 priv
.orig_sizeflag
&= ~DFLAG
;
11295 else if (p
[4] == '3' && p
[5] == '2')
11296 priv
.orig_sizeflag
|= DFLAG
;
11298 else if (CONST_STRNEQ (p
, "suffix"))
11299 priv
.orig_sizeflag
|= SUFFIX_ALWAYS
;
11301 p
= strchr (p
, ',');
11308 names64
= intel_names64
;
11309 names32
= intel_names32
;
11310 names16
= intel_names16
;
11311 names8
= intel_names8
;
11312 names8rex
= intel_names8rex
;
11313 names_seg
= intel_names_seg
;
11314 names_mm
= intel_names_mm
;
11315 names_xmm
= intel_names_xmm
;
11316 names_ymm
= intel_names_ymm
;
11317 index64
= intel_index64
;
11318 index32
= intel_index32
;
11319 index16
= intel_index16
;
11322 separator_char
= '+';
11327 names64
= att_names64
;
11328 names32
= att_names32
;
11329 names16
= att_names16
;
11330 names8
= att_names8
;
11331 names8rex
= att_names8rex
;
11332 names_seg
= att_names_seg
;
11333 names_mm
= att_names_mm
;
11334 names_xmm
= att_names_xmm
;
11335 names_ymm
= att_names_ymm
;
11336 index64
= att_index64
;
11337 index32
= att_index32
;
11338 index16
= att_index16
;
11341 separator_char
= ',';
11345 /* The output looks better if we put 7 bytes on a line, since that
11346 puts most long word instructions on a single line. Use 8 bytes
11348 if (info
->mach
== bfd_mach_l1om
11349 || info
->mach
== bfd_mach_l1om_intel_syntax
)
11350 info
->bytes_per_line
= 8;
11352 info
->bytes_per_line
= 7;
11354 info
->private_data
= &priv
;
11355 priv
.max_fetched
= priv
.the_buffer
;
11356 priv
.insn_start
= pc
;
11359 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
11367 start_codep
= priv
.the_buffer
;
11368 codep
= priv
.the_buffer
;
11370 if (setjmp (priv
.bailout
) != 0)
11374 /* Getting here means we tried for data but didn't get it. That
11375 means we have an incomplete instruction of some sort. Just
11376 print the first byte as a prefix or a .byte pseudo-op. */
11377 if (codep
> priv
.the_buffer
)
11379 name
= prefix_name (priv
.the_buffer
[0], priv
.orig_sizeflag
);
11381 (*info
->fprintf_func
) (info
->stream
, "%s", name
);
11384 /* Just print the first byte as a .byte instruction. */
11385 (*info
->fprintf_func
) (info
->stream
, ".byte 0x%x",
11386 (unsigned int) priv
.the_buffer
[0]);
11396 sizeflag
= priv
.orig_sizeflag
;
11398 if (!ckprefix () || rex_used
)
11400 /* Too many prefixes or unused REX prefixes. */
11402 all_prefixes
[i
] && i
< (int) ARRAY_SIZE (all_prefixes
);
11404 (*info
->fprintf_func
) (info
->stream
, "%s",
11405 prefix_name (all_prefixes
[i
], sizeflag
));
11409 insn_codep
= codep
;
11411 FETCH_DATA (info
, codep
+ 1);
11412 two_source_ops
= (*codep
== 0x62) || (*codep
== 0xc8);
11414 if (((prefixes
& PREFIX_FWAIT
)
11415 && ((*codep
< 0xd8) || (*codep
> 0xdf))))
11417 (*info
->fprintf_func
) (info
->stream
, "fwait");
11423 if (*codep
== 0x0f)
11425 unsigned char threebyte
;
11426 FETCH_DATA (info
, codep
+ 2);
11427 threebyte
= *++codep
;
11428 dp
= &dis386_twobyte
[threebyte
];
11429 need_modrm
= twobyte_has_modrm
[*codep
];
11434 dp
= &dis386
[*codep
];
11435 need_modrm
= onebyte_has_modrm
[*codep
];
11439 if ((prefixes
& PREFIX_REPZ
))
11440 used_prefixes
|= PREFIX_REPZ
;
11441 if ((prefixes
& PREFIX_REPNZ
))
11442 used_prefixes
|= PREFIX_REPNZ
;
11443 if ((prefixes
& PREFIX_LOCK
))
11444 used_prefixes
|= PREFIX_LOCK
;
11446 default_prefixes
= 0;
11447 if (prefixes
& PREFIX_ADDR
)
11450 if (dp
->op
[2].bytemode
!= loop_jcxz_mode
|| intel_syntax
)
11452 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
11453 all_prefixes
[last_addr_prefix
] = ADDR32_PREFIX
;
11455 all_prefixes
[last_addr_prefix
] = ADDR16_PREFIX
;
11456 default_prefixes
|= PREFIX_ADDR
;
11460 if ((prefixes
& PREFIX_DATA
))
11463 if (dp
->op
[2].bytemode
== cond_jump_mode
11464 && dp
->op
[0].bytemode
== v_mode
11467 if (sizeflag
& DFLAG
)
11468 all_prefixes
[last_data_prefix
] = DATA32_PREFIX
;
11470 all_prefixes
[last_data_prefix
] = DATA16_PREFIX
;
11471 default_prefixes
|= PREFIX_DATA
;
11473 else if (rex
& REX_W
)
11475 /* REX_W will override PREFIX_DATA. */
11476 default_prefixes
|= PREFIX_DATA
;
11482 FETCH_DATA (info
, codep
+ 1);
11483 modrm
.mod
= (*codep
>> 6) & 3;
11484 modrm
.reg
= (*codep
>> 3) & 7;
11485 modrm
.rm
= *codep
& 7;
11492 if (dp
->name
== NULL
&& dp
->op
[0].bytemode
== FLOATCODE
)
11494 dofloat (sizeflag
);
11498 dp
= get_valid_dis386 (dp
, info
);
11499 if (dp
!= NULL
&& putop (dp
->name
, sizeflag
) == 0)
11501 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
11504 op_ad
= MAX_OPERANDS
- 1 - i
;
11506 (*dp
->op
[i
].rtn
) (dp
->op
[i
].bytemode
, sizeflag
);
11511 /* See if any prefixes were not used. If so, print the first one
11512 separately. If we don't do this, we'll wind up printing an
11513 instruction stream which does not precisely correspond to the
11514 bytes we are disassembling. */
11515 if ((prefixes
& ~(used_prefixes
| default_prefixes
)) != 0)
11517 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
11518 if (all_prefixes
[i
])
11521 name
= prefix_name (all_prefixes
[i
], priv
.orig_sizeflag
);
11523 name
= INTERNAL_DISASSEMBLER_ERROR
;
11524 (*info
->fprintf_func
) (info
->stream
, "%s", name
);
11529 /* Check if the REX prefix is used. */
11530 if (rex_ignored
== 0 && (rex
^ rex_used
) == 0)
11531 all_prefixes
[last_rex_prefix
] = 0;
11533 /* Check if the SEG prefix is used. */
11534 if ((prefixes
& (PREFIX_CS
| PREFIX_SS
| PREFIX_DS
| PREFIX_ES
11535 | PREFIX_FS
| PREFIX_GS
)) != 0
11537 & seg_prefix (all_prefixes
[last_seg_prefix
])) != 0)
11538 all_prefixes
[last_seg_prefix
] = 0;
11540 /* Check if the ADDR prefix is used. */
11541 if ((prefixes
& PREFIX_ADDR
) != 0
11542 && (used_prefixes
& PREFIX_ADDR
) != 0)
11543 all_prefixes
[last_addr_prefix
] = 0;
11545 /* Check if the DATA prefix is used. */
11546 if ((prefixes
& PREFIX_DATA
) != 0
11547 && (used_prefixes
& PREFIX_DATA
) != 0)
11548 all_prefixes
[last_data_prefix
] = 0;
11551 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
11552 if (all_prefixes
[i
])
11555 name
= prefix_name (all_prefixes
[i
], sizeflag
);
11558 prefix_length
+= strlen (name
) + 1;
11559 (*info
->fprintf_func
) (info
->stream
, "%s ", name
);
11562 /* Check maximum code length. */
11563 if ((codep
- start_codep
) > MAX_CODE_LENGTH
)
11565 (*info
->fprintf_func
) (info
->stream
, "(bad)");
11566 return MAX_CODE_LENGTH
;
11569 obufp
= mnemonicendp
;
11570 for (i
= strlen (obuf
) + prefix_length
; i
< 6; i
++)
11573 (*info
->fprintf_func
) (info
->stream
, "%s", obuf
);
11575 /* The enter and bound instructions are printed with operands in the same
11576 order as the intel book; everything else is printed in reverse order. */
11577 if (intel_syntax
|| two_source_ops
)
11581 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
11582 op_txt
[i
] = op_out
[i
];
11584 for (i
= 0; i
< (MAX_OPERANDS
>> 1); ++i
)
11586 op_ad
= op_index
[i
];
11587 op_index
[i
] = op_index
[MAX_OPERANDS
- 1 - i
];
11588 op_index
[MAX_OPERANDS
- 1 - i
] = op_ad
;
11589 riprel
= op_riprel
[i
];
11590 op_riprel
[i
] = op_riprel
[MAX_OPERANDS
- 1 - i
];
11591 op_riprel
[MAX_OPERANDS
- 1 - i
] = riprel
;
11596 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
11597 op_txt
[MAX_OPERANDS
- 1 - i
] = op_out
[i
];
11601 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
11605 (*info
->fprintf_func
) (info
->stream
, ",");
11606 if (op_index
[i
] != -1 && !op_riprel
[i
])
11607 (*info
->print_address_func
) ((bfd_vma
) op_address
[op_index
[i
]], info
);
11609 (*info
->fprintf_func
) (info
->stream
, "%s", op_txt
[i
]);
11613 for (i
= 0; i
< MAX_OPERANDS
; i
++)
11614 if (op_index
[i
] != -1 && op_riprel
[i
])
11616 (*info
->fprintf_func
) (info
->stream
, " # ");
11617 (*info
->print_address_func
) ((bfd_vma
) (start_pc
+ codep
- start_codep
11618 + op_address
[op_index
[i
]]), info
);
11621 return codep
- priv
.the_buffer
;
11624 static const char *float_mem
[] = {
11699 static const unsigned char float_mem_mode
[] = {
11774 #define ST { OP_ST, 0 }
11775 #define STi { OP_STi, 0 }
11777 #define FGRPd9_2 NULL, { { NULL, 0 } }
11778 #define FGRPd9_4 NULL, { { NULL, 1 } }
11779 #define FGRPd9_5 NULL, { { NULL, 2 } }
11780 #define FGRPd9_6 NULL, { { NULL, 3 } }
11781 #define FGRPd9_7 NULL, { { NULL, 4 } }
11782 #define FGRPda_5 NULL, { { NULL, 5 } }
11783 #define FGRPdb_4 NULL, { { NULL, 6 } }
11784 #define FGRPde_3 NULL, { { NULL, 7 } }
11785 #define FGRPdf_4 NULL, { { NULL, 8 } }
11787 static const struct dis386 float_reg
[][8] = {
11790 { "fadd", { ST
, STi
} },
11791 { "fmul", { ST
, STi
} },
11792 { "fcom", { STi
} },
11793 { "fcomp", { STi
} },
11794 { "fsub", { ST
, STi
} },
11795 { "fsubr", { ST
, STi
} },
11796 { "fdiv", { ST
, STi
} },
11797 { "fdivr", { ST
, STi
} },
11801 { "fld", { STi
} },
11802 { "fxch", { STi
} },
11812 { "fcmovb", { ST
, STi
} },
11813 { "fcmove", { ST
, STi
} },
11814 { "fcmovbe",{ ST
, STi
} },
11815 { "fcmovu", { ST
, STi
} },
11823 { "fcmovnb",{ ST
, STi
} },
11824 { "fcmovne",{ ST
, STi
} },
11825 { "fcmovnbe",{ ST
, STi
} },
11826 { "fcmovnu",{ ST
, STi
} },
11828 { "fucomi", { ST
, STi
} },
11829 { "fcomi", { ST
, STi
} },
11834 { "fadd", { STi
, ST
} },
11835 { "fmul", { STi
, ST
} },
11838 { "fsub!M", { STi
, ST
} },
11839 { "fsubM", { STi
, ST
} },
11840 { "fdiv!M", { STi
, ST
} },
11841 { "fdivM", { STi
, ST
} },
11845 { "ffree", { STi
} },
11847 { "fst", { STi
} },
11848 { "fstp", { STi
} },
11849 { "fucom", { STi
} },
11850 { "fucomp", { STi
} },
11856 { "faddp", { STi
, ST
} },
11857 { "fmulp", { STi
, ST
} },
11860 { "fsub!Mp", { STi
, ST
} },
11861 { "fsubMp", { STi
, ST
} },
11862 { "fdiv!Mp", { STi
, ST
} },
11863 { "fdivMp", { STi
, ST
} },
11867 { "ffreep", { STi
} },
11872 { "fucomip", { ST
, STi
} },
11873 { "fcomip", { ST
, STi
} },
11878 static char *fgrps
[][8] = {
11881 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
11886 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
11891 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
11896 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
11901 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
11906 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
11911 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
11912 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
11917 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
11922 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
11927 swap_operand (void)
11929 mnemonicendp
[0] = '.';
11930 mnemonicendp
[1] = 's';
11935 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED
,
11936 int sizeflag ATTRIBUTE_UNUSED
)
11938 /* Skip mod/rm byte. */
11944 dofloat (int sizeflag
)
11946 const struct dis386
*dp
;
11947 unsigned char floatop
;
11949 floatop
= codep
[-1];
11951 if (modrm
.mod
!= 3)
11953 int fp_indx
= (floatop
- 0xd8) * 8 + modrm
.reg
;
11955 putop (float_mem
[fp_indx
], sizeflag
);
11958 OP_E (float_mem_mode
[fp_indx
], sizeflag
);
11961 /* Skip mod/rm byte. */
11965 dp
= &float_reg
[floatop
- 0xd8][modrm
.reg
];
11966 if (dp
->name
== NULL
)
11968 putop (fgrps
[dp
->op
[0].bytemode
][modrm
.rm
], sizeflag
);
11970 /* Instruction fnstsw is only one with strange arg. */
11971 if (floatop
== 0xdf && codep
[-1] == 0xe0)
11972 strcpy (op_out
[0], names16
[0]);
11976 putop (dp
->name
, sizeflag
);
11981 (*dp
->op
[0].rtn
) (dp
->op
[0].bytemode
, sizeflag
);
11986 (*dp
->op
[1].rtn
) (dp
->op
[1].bytemode
, sizeflag
);
11991 OP_ST (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
11993 oappend ("%st" + intel_syntax
);
11997 OP_STi (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
11999 sprintf (scratchbuf
, "%%st(%d)", modrm
.rm
);
12000 oappend (scratchbuf
+ intel_syntax
);
12003 /* Capital letters in template are macros. */
12005 putop (const char *in_template
, int sizeflag
)
12010 unsigned int l
= 0, len
= 1;
12013 #define SAVE_LAST(c) \
12014 if (l < len && l < sizeof (last)) \
12019 for (p
= in_template
; *p
; p
++)
12036 while (*++p
!= '|')
12037 if (*p
== '}' || *p
== '\0')
12040 /* Fall through. */
12045 while (*++p
!= '}')
12056 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
12060 if (l
== 0 && len
== 1)
12065 if (sizeflag
& SUFFIX_ALWAYS
)
12078 if (address_mode
== mode_64bit
12079 && !(prefixes
& PREFIX_ADDR
))
12090 if (intel_syntax
&& !alt
)
12092 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
12094 if (sizeflag
& DFLAG
)
12095 *obufp
++ = intel_syntax
? 'd' : 'l';
12097 *obufp
++ = intel_syntax
? 'w' : 's';
12098 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12102 if (intel_syntax
|| !(sizeflag
& SUFFIX_ALWAYS
))
12105 if (modrm
.mod
== 3)
12111 if (sizeflag
& DFLAG
)
12112 *obufp
++ = intel_syntax
? 'd' : 'l';
12115 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12121 case 'E': /* For jcxz/jecxz */
12122 if (address_mode
== mode_64bit
)
12124 if (sizeflag
& AFLAG
)
12130 if (sizeflag
& AFLAG
)
12132 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
12137 if ((prefixes
& PREFIX_ADDR
) || (sizeflag
& SUFFIX_ALWAYS
))
12139 if (sizeflag
& AFLAG
)
12140 *obufp
++ = address_mode
== mode_64bit
? 'q' : 'l';
12142 *obufp
++ = address_mode
== mode_64bit
? 'l' : 'w';
12143 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
12147 if (intel_syntax
|| (obufp
[-1] != 's' && !(sizeflag
& SUFFIX_ALWAYS
)))
12149 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
12153 if (!(rex
& REX_W
))
12154 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12159 if ((prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_CS
12160 || (prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_DS
)
12162 used_prefixes
|= prefixes
& (PREFIX_CS
| PREFIX_DS
);
12165 if (prefixes
& PREFIX_DS
)
12186 if (address_mode
== mode_64bit
&& (sizeflag
& SUFFIX_ALWAYS
))
12191 /* Fall through. */
12194 if (l
!= 0 || len
!= 1)
12202 if (sizeflag
& SUFFIX_ALWAYS
)
12206 if (intel_mnemonic
!= cond
)
12210 if ((prefixes
& PREFIX_FWAIT
) == 0)
12213 used_prefixes
|= PREFIX_FWAIT
;
12219 else if (intel_syntax
&& (sizeflag
& DFLAG
))
12223 if (!(rex
& REX_W
))
12224 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12229 if (address_mode
== mode_64bit
&& (sizeflag
& DFLAG
))
12234 /* Fall through. */
12238 if ((prefixes
& PREFIX_DATA
)
12240 || (sizeflag
& SUFFIX_ALWAYS
))
12247 if (sizeflag
& DFLAG
)
12251 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12258 if (address_mode
== mode_64bit
&& (sizeflag
& DFLAG
))
12260 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
12264 /* Fall through. */
12267 if (l
== 0 && len
== 1)
12270 if (intel_syntax
&& !alt
)
12273 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
12279 if (sizeflag
& DFLAG
)
12280 *obufp
++ = intel_syntax
? 'd' : 'l';
12283 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12289 if (l
!= 1 || len
!= 2 || last
[0] != 'L')
12295 || (modrm
.mod
== 3 && !(sizeflag
& SUFFIX_ALWAYS
)))
12310 else if (sizeflag
& DFLAG
)
12319 if (intel_syntax
&& !p
[1]
12320 && ((rex
& REX_W
) || (sizeflag
& DFLAG
)))
12322 if (!(rex
& REX_W
))
12323 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12326 if (l
== 0 && len
== 1)
12330 if (address_mode
== mode_64bit
&& (sizeflag
& DFLAG
))
12332 if (sizeflag
& SUFFIX_ALWAYS
)
12354 /* Fall through. */
12357 if (l
== 0 && len
== 1)
12362 if (sizeflag
& SUFFIX_ALWAYS
)
12368 if (sizeflag
& DFLAG
)
12372 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12386 if (address_mode
== mode_64bit
12387 && !(prefixes
& PREFIX_ADDR
))
12398 if (l
!= 0 || len
!= 1)
12403 if (need_vex
&& vex
.prefix
)
12405 if (vex
.prefix
== DATA_PREFIX_OPCODE
)
12412 if (prefixes
& PREFIX_DATA
)
12416 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12420 if (l
== 0 && len
== 1)
12422 if (intel_syntax
|| !(sizeflag
& SUFFIX_ALWAYS
))
12433 if (l
!= 1 || len
!= 2 || last
[0] != 'X')
12441 || (modrm
.mod
== 3 && !(sizeflag
& SUFFIX_ALWAYS
)))
12443 switch (vex
.length
)
12457 if (l
== 0 && len
== 1)
12459 /* operand size flag for cwtl, cbtw */
12468 else if (sizeflag
& DFLAG
)
12472 if (!(rex
& REX_W
))
12473 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12477 if (l
!= 1 || len
!= 2 || last
[0] != 'X')
12484 *obufp
++ = vex
.w
? 'd': 's';
12491 mnemonicendp
= obufp
;
12496 oappend (const char *s
)
12498 obufp
= stpcpy (obufp
, s
);
12504 if (prefixes
& PREFIX_CS
)
12506 used_prefixes
|= PREFIX_CS
;
12507 oappend ("%cs:" + intel_syntax
);
12509 if (prefixes
& PREFIX_DS
)
12511 used_prefixes
|= PREFIX_DS
;
12512 oappend ("%ds:" + intel_syntax
);
12514 if (prefixes
& PREFIX_SS
)
12516 used_prefixes
|= PREFIX_SS
;
12517 oappend ("%ss:" + intel_syntax
);
12519 if (prefixes
& PREFIX_ES
)
12521 used_prefixes
|= PREFIX_ES
;
12522 oappend ("%es:" + intel_syntax
);
12524 if (prefixes
& PREFIX_FS
)
12526 used_prefixes
|= PREFIX_FS
;
12527 oappend ("%fs:" + intel_syntax
);
12529 if (prefixes
& PREFIX_GS
)
12531 used_prefixes
|= PREFIX_GS
;
12532 oappend ("%gs:" + intel_syntax
);
12537 OP_indirE (int bytemode
, int sizeflag
)
12541 OP_E (bytemode
, sizeflag
);
12545 print_operand_value (char *buf
, int hex
, bfd_vma disp
)
12547 if (address_mode
== mode_64bit
)
12555 sprintf_vma (tmp
, disp
);
12556 for (i
= 0; tmp
[i
] == '0' && tmp
[i
+ 1]; i
++);
12557 strcpy (buf
+ 2, tmp
+ i
);
12561 bfd_signed_vma v
= disp
;
12568 /* Check for possible overflow on 0x8000000000000000. */
12571 strcpy (buf
, "9223372036854775808");
12585 tmp
[28 - i
] = (v
% 10) + '0';
12589 strcpy (buf
, tmp
+ 29 - i
);
12595 sprintf (buf
, "0x%x", (unsigned int) disp
);
12597 sprintf (buf
, "%d", (int) disp
);
12601 /* Put DISP in BUF as signed hex number. */
12604 print_displacement (char *buf
, bfd_vma disp
)
12606 bfd_signed_vma val
= disp
;
12615 /* Check for possible overflow. */
12618 switch (address_mode
)
12621 strcpy (buf
+ j
, "0x8000000000000000");
12624 strcpy (buf
+ j
, "0x80000000");
12627 strcpy (buf
+ j
, "0x8000");
12637 sprintf_vma (tmp
, (bfd_vma
) val
);
12638 for (i
= 0; tmp
[i
] == '0'; i
++)
12640 if (tmp
[i
] == '\0')
12642 strcpy (buf
+ j
, tmp
+ i
);
12646 intel_operand_size (int bytemode
, int sizeflag
)
12653 oappend ("BYTE PTR ");
12657 oappend ("WORD PTR ");
12660 if (address_mode
== mode_64bit
&& (sizeflag
& DFLAG
))
12662 oappend ("QWORD PTR ");
12671 oappend ("QWORD PTR ");
12674 if ((sizeflag
& DFLAG
) || bytemode
== dq_mode
)
12675 oappend ("DWORD PTR ");
12677 oappend ("WORD PTR ");
12678 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12682 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
12684 oappend ("WORD PTR ");
12685 if (!(rex
& REX_W
))
12686 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12689 if (sizeflag
& DFLAG
)
12690 oappend ("QWORD PTR ");
12692 oappend ("DWORD PTR ");
12693 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12696 case d_scalar_mode
:
12697 case d_scalar_swap_mode
:
12700 oappend ("DWORD PTR ");
12703 case q_scalar_mode
:
12704 case q_scalar_swap_mode
:
12706 oappend ("QWORD PTR ");
12709 if (address_mode
== mode_64bit
)
12710 oappend ("QWORD PTR ");
12712 oappend ("DWORD PTR ");
12715 if (sizeflag
& DFLAG
)
12716 oappend ("FWORD PTR ");
12718 oappend ("DWORD PTR ");
12719 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12722 oappend ("TBYTE PTR ");
12728 switch (vex
.length
)
12731 oappend ("XMMWORD PTR ");
12734 oappend ("YMMWORD PTR ");
12741 oappend ("XMMWORD PTR ");
12744 oappend ("XMMWORD PTR ");
12750 switch (vex
.length
)
12753 oappend ("QWORD PTR ");
12756 oappend ("XMMWORD PTR ");
12766 switch (vex
.length
)
12769 oappend ("QWORD PTR ");
12772 oappend ("YMMWORD PTR ");
12779 oappend ("OWORD PTR ");
12781 case vex_w_dq_mode
:
12782 case vex_scalar_w_dq_mode
:
12787 oappend ("QWORD PTR ");
12789 oappend ("DWORD PTR ");
12797 OP_E_register (int bytemode
, int sizeflag
)
12799 int reg
= modrm
.rm
;
12800 const char **names
;
12806 if ((sizeflag
& SUFFIX_ALWAYS
)
12807 && (bytemode
== b_swap_mode
|| bytemode
== v_swap_mode
))
12830 names
= address_mode
== mode_64bit
? names64
: names32
;
12833 if (address_mode
== mode_64bit
&& (sizeflag
& DFLAG
))
12851 if ((sizeflag
& DFLAG
)
12852 || (bytemode
!= v_mode
12853 && bytemode
!= v_swap_mode
))
12857 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12863 oappend (INTERNAL_DISASSEMBLER_ERROR
);
12866 oappend (names
[reg
]);
12870 OP_E_memory (int bytemode
, int sizeflag
)
12873 int add
= (rex
& REX_B
) ? 8 : 0;
12878 intel_operand_size (bytemode
, sizeflag
);
12881 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
12883 /* 32/64 bit address mode */
12901 FETCH_DATA (the_info
, codep
+ 1);
12902 vindex
= (*codep
>> 3) & 7;
12903 scale
= (*codep
>> 6) & 3;
12908 haveindex
= vindex
!= 4;
12911 rbase
= base
+ add
;
12919 if (address_mode
== mode_64bit
&& !havesib
)
12925 FETCH_DATA (the_info
, codep
+ 1);
12927 if ((disp
& 0x80) != 0)
12935 /* In 32bit mode, we need index register to tell [offset] from
12936 [eiz*1 + offset]. */
12937 needindex
= (havesib
12940 && address_mode
== mode_32bit
);
12941 havedisp
= (havebase
12943 || (havesib
&& (haveindex
|| scale
!= 0)));
12946 if (modrm
.mod
!= 0 || base
== 5)
12948 if (havedisp
|| riprel
)
12949 print_displacement (scratchbuf
, disp
);
12951 print_operand_value (scratchbuf
, 1, disp
);
12952 oappend (scratchbuf
);
12956 oappend (sizeflag
& AFLAG
? "(%rip)" : "(%eip)");
12960 if (havebase
|| haveindex
|| riprel
)
12961 used_prefixes
|= PREFIX_ADDR
;
12963 if (havedisp
|| (intel_syntax
&& riprel
))
12965 *obufp
++ = open_char
;
12966 if (intel_syntax
&& riprel
)
12969 oappend (sizeflag
& AFLAG
? "rip" : "eip");
12973 oappend (address_mode
== mode_64bit
&& (sizeflag
& AFLAG
)
12974 ? names64
[rbase
] : names32
[rbase
]);
12977 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
12978 print index to tell base + index from base. */
12982 || (havebase
&& base
!= ESP_REG_NUM
))
12984 if (!intel_syntax
|| havebase
)
12986 *obufp
++ = separator_char
;
12990 oappend (address_mode
== mode_64bit
12991 && (sizeflag
& AFLAG
)
12992 ? names64
[vindex
] : names32
[vindex
]);
12994 oappend (address_mode
== mode_64bit
12995 && (sizeflag
& AFLAG
)
12996 ? index64
: index32
);
12998 *obufp
++ = scale_char
;
13000 sprintf (scratchbuf
, "%d", 1 << scale
);
13001 oappend (scratchbuf
);
13005 && (disp
|| modrm
.mod
!= 0 || base
== 5))
13007 if (!havedisp
|| (bfd_signed_vma
) disp
>= 0)
13012 else if (modrm
.mod
!= 1 && disp
!= -disp
)
13016 disp
= - (bfd_signed_vma
) disp
;
13020 print_displacement (scratchbuf
, disp
);
13022 print_operand_value (scratchbuf
, 1, disp
);
13023 oappend (scratchbuf
);
13026 *obufp
++ = close_char
;
13029 else if (intel_syntax
)
13031 if (modrm
.mod
!= 0 || base
== 5)
13033 if (prefixes
& (PREFIX_CS
| PREFIX_SS
| PREFIX_DS
13034 | PREFIX_ES
| PREFIX_FS
| PREFIX_GS
))
13038 oappend (names_seg
[ds_reg
- es_reg
]);
13041 print_operand_value (scratchbuf
, 1, disp
);
13042 oappend (scratchbuf
);
13048 /* 16 bit address mode */
13049 used_prefixes
|= prefixes
& PREFIX_ADDR
;
13056 if ((disp
& 0x8000) != 0)
13061 FETCH_DATA (the_info
, codep
+ 1);
13063 if ((disp
& 0x80) != 0)
13068 if ((disp
& 0x8000) != 0)
13074 if (modrm
.mod
!= 0 || modrm
.rm
== 6)
13076 print_displacement (scratchbuf
, disp
);
13077 oappend (scratchbuf
);
13080 if (modrm
.mod
!= 0 || modrm
.rm
!= 6)
13082 *obufp
++ = open_char
;
13084 oappend (index16
[modrm
.rm
]);
13086 && (disp
|| modrm
.mod
!= 0 || modrm
.rm
== 6))
13088 if ((bfd_signed_vma
) disp
>= 0)
13093 else if (modrm
.mod
!= 1)
13097 disp
= - (bfd_signed_vma
) disp
;
13100 print_displacement (scratchbuf
, disp
);
13101 oappend (scratchbuf
);
13104 *obufp
++ = close_char
;
13107 else if (intel_syntax
)
13109 if (prefixes
& (PREFIX_CS
| PREFIX_SS
| PREFIX_DS
13110 | PREFIX_ES
| PREFIX_FS
| PREFIX_GS
))
13114 oappend (names_seg
[ds_reg
- es_reg
]);
13117 print_operand_value (scratchbuf
, 1, disp
& 0xffff);
13118 oappend (scratchbuf
);
13124 OP_E (int bytemode
, int sizeflag
)
13126 /* Skip mod/rm byte. */
13130 if (modrm
.mod
== 3)
13131 OP_E_register (bytemode
, sizeflag
);
13133 OP_E_memory (bytemode
, sizeflag
);
13137 OP_G (int bytemode
, int sizeflag
)
13148 oappend (names8rex
[modrm
.reg
+ add
]);
13150 oappend (names8
[modrm
.reg
+ add
]);
13153 oappend (names16
[modrm
.reg
+ add
]);
13156 oappend (names32
[modrm
.reg
+ add
]);
13159 oappend (names64
[modrm
.reg
+ add
]);
13168 oappend (names64
[modrm
.reg
+ add
]);
13171 if ((sizeflag
& DFLAG
) || bytemode
!= v_mode
)
13172 oappend (names32
[modrm
.reg
+ add
]);
13174 oappend (names16
[modrm
.reg
+ add
]);
13175 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13179 if (address_mode
== mode_64bit
)
13180 oappend (names64
[modrm
.reg
+ add
]);
13182 oappend (names32
[modrm
.reg
+ add
]);
13185 oappend (INTERNAL_DISASSEMBLER_ERROR
);
13198 FETCH_DATA (the_info
, codep
+ 8);
13199 a
= *codep
++ & 0xff;
13200 a
|= (*codep
++ & 0xff) << 8;
13201 a
|= (*codep
++ & 0xff) << 16;
13202 a
|= (*codep
++ & 0xff) << 24;
13203 b
= *codep
++ & 0xff;
13204 b
|= (*codep
++ & 0xff) << 8;
13205 b
|= (*codep
++ & 0xff) << 16;
13206 b
|= (*codep
++ & 0xff) << 24;
13207 x
= a
+ ((bfd_vma
) b
<< 32);
13215 static bfd_signed_vma
13218 bfd_signed_vma x
= 0;
13220 FETCH_DATA (the_info
, codep
+ 4);
13221 x
= *codep
++ & (bfd_signed_vma
) 0xff;
13222 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
13223 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
13224 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
13228 static bfd_signed_vma
13231 bfd_signed_vma x
= 0;
13233 FETCH_DATA (the_info
, codep
+ 4);
13234 x
= *codep
++ & (bfd_signed_vma
) 0xff;
13235 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
13236 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
13237 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
13239 x
= (x
^ ((bfd_signed_vma
) 1 << 31)) - ((bfd_signed_vma
) 1 << 31);
13249 FETCH_DATA (the_info
, codep
+ 2);
13250 x
= *codep
++ & 0xff;
13251 x
|= (*codep
++ & 0xff) << 8;
13256 set_op (bfd_vma op
, int riprel
)
13258 op_index
[op_ad
] = op_ad
;
13259 if (address_mode
== mode_64bit
)
13261 op_address
[op_ad
] = op
;
13262 op_riprel
[op_ad
] = riprel
;
13266 /* Mask to get a 32-bit address. */
13267 op_address
[op_ad
] = op
& 0xffffffff;
13268 op_riprel
[op_ad
] = riprel
& 0xffffffff;
13273 OP_REG (int code
, int sizeflag
)
13285 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
13286 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
13287 s
= names16
[code
- ax_reg
+ add
];
13289 case es_reg
: case ss_reg
: case cs_reg
:
13290 case ds_reg
: case fs_reg
: case gs_reg
:
13291 s
= names_seg
[code
- es_reg
+ add
];
13293 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
13294 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
13297 s
= names8rex
[code
- al_reg
+ add
];
13299 s
= names8
[code
- al_reg
];
13301 case rAX_reg
: case rCX_reg
: case rDX_reg
: case rBX_reg
:
13302 case rSP_reg
: case rBP_reg
: case rSI_reg
: case rDI_reg
:
13303 if (address_mode
== mode_64bit
&& (sizeflag
& DFLAG
))
13305 s
= names64
[code
- rAX_reg
+ add
];
13308 code
+= eAX_reg
- rAX_reg
;
13309 /* Fall through. */
13310 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
13311 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
13314 s
= names64
[code
- eAX_reg
+ add
];
13317 if (sizeflag
& DFLAG
)
13318 s
= names32
[code
- eAX_reg
+ add
];
13320 s
= names16
[code
- eAX_reg
+ add
];
13321 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13325 s
= INTERNAL_DISASSEMBLER_ERROR
;
13332 OP_IMREG (int code
, int sizeflag
)
13344 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
13345 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
13346 s
= names16
[code
- ax_reg
];
13348 case es_reg
: case ss_reg
: case cs_reg
:
13349 case ds_reg
: case fs_reg
: case gs_reg
:
13350 s
= names_seg
[code
- es_reg
];
13352 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
13353 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
13356 s
= names8rex
[code
- al_reg
];
13358 s
= names8
[code
- al_reg
];
13360 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
13361 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
13364 s
= names64
[code
- eAX_reg
];
13367 if (sizeflag
& DFLAG
)
13368 s
= names32
[code
- eAX_reg
];
13370 s
= names16
[code
- eAX_reg
];
13371 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13374 case z_mode_ax_reg
:
13375 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
13379 if (!(rex
& REX_W
))
13380 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13383 s
= INTERNAL_DISASSEMBLER_ERROR
;
13390 OP_I (int bytemode
, int sizeflag
)
13393 bfd_signed_vma mask
= -1;
13398 FETCH_DATA (the_info
, codep
+ 1);
13403 if (address_mode
== mode_64bit
)
13408 /* Fall through. */
13415 if (sizeflag
& DFLAG
)
13425 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13437 oappend (INTERNAL_DISASSEMBLER_ERROR
);
13442 scratchbuf
[0] = '$';
13443 print_operand_value (scratchbuf
+ 1, 1, op
);
13444 oappend (scratchbuf
+ intel_syntax
);
13445 scratchbuf
[0] = '\0';
13449 OP_I64 (int bytemode
, int sizeflag
)
13452 bfd_signed_vma mask
= -1;
13454 if (address_mode
!= mode_64bit
)
13456 OP_I (bytemode
, sizeflag
);
13463 FETCH_DATA (the_info
, codep
+ 1);
13473 if (sizeflag
& DFLAG
)
13483 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13491 oappend (INTERNAL_DISASSEMBLER_ERROR
);
13496 scratchbuf
[0] = '$';
13497 print_operand_value (scratchbuf
+ 1, 1, op
);
13498 oappend (scratchbuf
+ intel_syntax
);
13499 scratchbuf
[0] = '\0';
13503 OP_sI (int bytemode
, int sizeflag
)
13506 bfd_signed_vma mask
= -1;
13511 FETCH_DATA (the_info
, codep
+ 1);
13513 if ((op
& 0x80) != 0)
13523 if (sizeflag
& DFLAG
)
13532 if ((op
& 0x8000) != 0)
13535 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13541 if ((op
& 0x8000) != 0)
13545 oappend (INTERNAL_DISASSEMBLER_ERROR
);
13549 scratchbuf
[0] = '$';
13550 print_operand_value (scratchbuf
+ 1, 1, op
);
13551 oappend (scratchbuf
+ intel_syntax
);
13555 OP_J (int bytemode
, int sizeflag
)
13559 bfd_vma segment
= 0;
13564 FETCH_DATA (the_info
, codep
+ 1);
13566 if ((disp
& 0x80) != 0)
13571 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
13576 if ((disp
& 0x8000) != 0)
13578 /* In 16bit mode, address is wrapped around at 64k within
13579 the same segment. Otherwise, a data16 prefix on a jump
13580 instruction means that the pc is masked to 16 bits after
13581 the displacement is added! */
13583 if ((prefixes
& PREFIX_DATA
) == 0)
13584 segment
= ((start_pc
+ codep
- start_codep
)
13585 & ~((bfd_vma
) 0xffff));
13587 if (!(rex
& REX_W
))
13588 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13591 oappend (INTERNAL_DISASSEMBLER_ERROR
);
13594 disp
= ((start_pc
+ codep
- start_codep
+ disp
) & mask
) | segment
;
13596 print_operand_value (scratchbuf
, 1, disp
);
13597 oappend (scratchbuf
);
13601 OP_SEG (int bytemode
, int sizeflag
)
13603 if (bytemode
== w_mode
)
13604 oappend (names_seg
[modrm
.reg
]);
13606 OP_E (modrm
.mod
== 3 ? bytemode
: w_mode
, sizeflag
);
13610 OP_DIR (int dummy ATTRIBUTE_UNUSED
, int sizeflag
)
13614 if (sizeflag
& DFLAG
)
13624 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13626 sprintf (scratchbuf
, "0x%x:0x%x", seg
, offset
);
13628 sprintf (scratchbuf
, "$0x%x,$0x%x", seg
, offset
);
13629 oappend (scratchbuf
);
13633 OP_OFF (int bytemode
, int sizeflag
)
13637 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
13638 intel_operand_size (bytemode
, sizeflag
);
13641 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
13648 if (!(prefixes
& (PREFIX_CS
| PREFIX_SS
| PREFIX_DS
13649 | PREFIX_ES
| PREFIX_FS
| PREFIX_GS
)))
13651 oappend (names_seg
[ds_reg
- es_reg
]);
13655 print_operand_value (scratchbuf
, 1, off
);
13656 oappend (scratchbuf
);
13660 OP_OFF64 (int bytemode
, int sizeflag
)
13664 if (address_mode
!= mode_64bit
13665 || (prefixes
& PREFIX_ADDR
))
13667 OP_OFF (bytemode
, sizeflag
);
13671 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
13672 intel_operand_size (bytemode
, sizeflag
);
13679 if (!(prefixes
& (PREFIX_CS
| PREFIX_SS
| PREFIX_DS
13680 | PREFIX_ES
| PREFIX_FS
| PREFIX_GS
)))
13682 oappend (names_seg
[ds_reg
- es_reg
]);
13686 print_operand_value (scratchbuf
, 1, off
);
13687 oappend (scratchbuf
);
13691 ptr_reg (int code
, int sizeflag
)
13695 *obufp
++ = open_char
;
13696 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
13697 if (address_mode
== mode_64bit
)
13699 if (!(sizeflag
& AFLAG
))
13700 s
= names32
[code
- eAX_reg
];
13702 s
= names64
[code
- eAX_reg
];
13704 else if (sizeflag
& AFLAG
)
13705 s
= names32
[code
- eAX_reg
];
13707 s
= names16
[code
- eAX_reg
];
13709 *obufp
++ = close_char
;
13714 OP_ESreg (int code
, int sizeflag
)
13720 case 0x6d: /* insw/insl */
13721 intel_operand_size (z_mode
, sizeflag
);
13723 case 0xa5: /* movsw/movsl/movsq */
13724 case 0xa7: /* cmpsw/cmpsl/cmpsq */
13725 case 0xab: /* stosw/stosl */
13726 case 0xaf: /* scasw/scasl */
13727 intel_operand_size (v_mode
, sizeflag
);
13730 intel_operand_size (b_mode
, sizeflag
);
13733 oappend ("%es:" + intel_syntax
);
13734 ptr_reg (code
, sizeflag
);
13738 OP_DSreg (int code
, int sizeflag
)
13744 case 0x6f: /* outsw/outsl */
13745 intel_operand_size (z_mode
, sizeflag
);
13747 case 0xa5: /* movsw/movsl/movsq */
13748 case 0xa7: /* cmpsw/cmpsl/cmpsq */
13749 case 0xad: /* lodsw/lodsl/lodsq */
13750 intel_operand_size (v_mode
, sizeflag
);
13753 intel_operand_size (b_mode
, sizeflag
);
13762 | PREFIX_GS
)) == 0)
13763 prefixes
|= PREFIX_DS
;
13765 ptr_reg (code
, sizeflag
);
13769 OP_C (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
13777 else if (address_mode
!= mode_64bit
&& (prefixes
& PREFIX_LOCK
))
13779 all_prefixes
[last_lock_prefix
] = 0;
13780 used_prefixes
|= PREFIX_LOCK
;
13785 sprintf (scratchbuf
, "%%cr%d", modrm
.reg
+ add
);
13786 oappend (scratchbuf
+ intel_syntax
);
13790 OP_D (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
13799 sprintf (scratchbuf
, "db%d", modrm
.reg
+ add
);
13801 sprintf (scratchbuf
, "%%db%d", modrm
.reg
+ add
);
13802 oappend (scratchbuf
);
13806 OP_T (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
13808 sprintf (scratchbuf
, "%%tr%d", modrm
.reg
);
13809 oappend (scratchbuf
+ intel_syntax
);
13813 OP_R (int bytemode
, int sizeflag
)
13815 if (modrm
.mod
== 3)
13816 OP_E (bytemode
, sizeflag
);
13822 OP_MMX (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
13824 int reg
= modrm
.reg
;
13825 const char **names
;
13827 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13828 if (prefixes
& PREFIX_DATA
)
13837 oappend (names
[reg
]);
13841 OP_XMM (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
13843 int reg
= modrm
.reg
;
13844 const char **names
;
13850 && bytemode
!= xmm_mode
13851 && bytemode
!= scalar_mode
)
13853 switch (vex
.length
)
13867 oappend (names
[reg
]);
13871 OP_EM (int bytemode
, int sizeflag
)
13874 const char **names
;
13876 if (modrm
.mod
!= 3)
13879 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
13881 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
13882 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13884 OP_E (bytemode
, sizeflag
);
13888 if ((sizeflag
& SUFFIX_ALWAYS
) && bytemode
== v_swap_mode
)
13891 /* Skip mod/rm byte. */
13894 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13896 if (prefixes
& PREFIX_DATA
)
13905 oappend (names
[reg
]);
13908 /* cvt* are the only instructions in sse2 which have
13909 both SSE and MMX operands and also have 0x66 prefix
13910 in their opcode. 0x66 was originally used to differentiate
13911 between SSE and MMX instruction(operands). So we have to handle the
13912 cvt* separately using OP_EMC and OP_MXC */
13914 OP_EMC (int bytemode
, int sizeflag
)
13916 if (modrm
.mod
!= 3)
13918 if (intel_syntax
&& bytemode
== v_mode
)
13920 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
13921 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13923 OP_E (bytemode
, sizeflag
);
13927 /* Skip mod/rm byte. */
13930 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13931 oappend (names_mm
[modrm
.rm
]);
13935 OP_MXC (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
13937 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13938 oappend (names_mm
[modrm
.reg
]);
13942 OP_EX (int bytemode
, int sizeflag
)
13945 const char **names
;
13947 /* Skip mod/rm byte. */
13951 if (modrm
.mod
!= 3)
13953 OP_E_memory (bytemode
, sizeflag
);
13962 if ((sizeflag
& SUFFIX_ALWAYS
)
13963 && (bytemode
== x_swap_mode
13964 || bytemode
== d_swap_mode
13965 || bytemode
== d_scalar_swap_mode
13966 || bytemode
== q_swap_mode
13967 || bytemode
== q_scalar_swap_mode
))
13971 && bytemode
!= xmm_mode
13972 && bytemode
!= xmmq_mode
13973 && bytemode
!= d_scalar_mode
13974 && bytemode
!= d_scalar_swap_mode
13975 && bytemode
!= q_scalar_mode
13976 && bytemode
!= q_scalar_swap_mode
13977 && bytemode
!= vex_scalar_w_dq_mode
)
13979 switch (vex
.length
)
13993 oappend (names
[reg
]);
13997 OP_MS (int bytemode
, int sizeflag
)
13999 if (modrm
.mod
== 3)
14000 OP_EM (bytemode
, sizeflag
);
14006 OP_XS (int bytemode
, int sizeflag
)
14008 if (modrm
.mod
== 3)
14009 OP_EX (bytemode
, sizeflag
);
14015 OP_M (int bytemode
, int sizeflag
)
14017 if (modrm
.mod
== 3)
14018 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
14021 OP_E (bytemode
, sizeflag
);
14025 OP_0f07 (int bytemode
, int sizeflag
)
14027 if (modrm
.mod
!= 3 || modrm
.rm
!= 0)
14030 OP_E (bytemode
, sizeflag
);
14033 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
14034 32bit mode and "xchg %rax,%rax" in 64bit mode. */
14037 NOP_Fixup1 (int bytemode
, int sizeflag
)
14039 if ((prefixes
& PREFIX_DATA
) != 0
14042 && address_mode
== mode_64bit
))
14043 OP_REG (bytemode
, sizeflag
);
14045 strcpy (obuf
, "nop");
14049 NOP_Fixup2 (int bytemode
, int sizeflag
)
14051 if ((prefixes
& PREFIX_DATA
) != 0
14054 && address_mode
== mode_64bit
))
14055 OP_IMREG (bytemode
, sizeflag
);
14058 static const char *const Suffix3DNow
[] = {
14059 /* 00 */ NULL
, NULL
, NULL
, NULL
,
14060 /* 04 */ NULL
, NULL
, NULL
, NULL
,
14061 /* 08 */ NULL
, NULL
, NULL
, NULL
,
14062 /* 0C */ "pi2fw", "pi2fd", NULL
, NULL
,
14063 /* 10 */ NULL
, NULL
, NULL
, NULL
,
14064 /* 14 */ NULL
, NULL
, NULL
, NULL
,
14065 /* 18 */ NULL
, NULL
, NULL
, NULL
,
14066 /* 1C */ "pf2iw", "pf2id", NULL
, NULL
,
14067 /* 20 */ NULL
, NULL
, NULL
, NULL
,
14068 /* 24 */ NULL
, NULL
, NULL
, NULL
,
14069 /* 28 */ NULL
, NULL
, NULL
, NULL
,
14070 /* 2C */ NULL
, NULL
, NULL
, NULL
,
14071 /* 30 */ NULL
, NULL
, NULL
, NULL
,
14072 /* 34 */ NULL
, NULL
, NULL
, NULL
,
14073 /* 38 */ NULL
, NULL
, NULL
, NULL
,
14074 /* 3C */ NULL
, NULL
, NULL
, NULL
,
14075 /* 40 */ NULL
, NULL
, NULL
, NULL
,
14076 /* 44 */ NULL
, NULL
, NULL
, NULL
,
14077 /* 48 */ NULL
, NULL
, NULL
, NULL
,
14078 /* 4C */ NULL
, NULL
, NULL
, NULL
,
14079 /* 50 */ NULL
, NULL
, NULL
, NULL
,
14080 /* 54 */ NULL
, NULL
, NULL
, NULL
,
14081 /* 58 */ NULL
, NULL
, NULL
, NULL
,
14082 /* 5C */ NULL
, NULL
, NULL
, NULL
,
14083 /* 60 */ NULL
, NULL
, NULL
, NULL
,
14084 /* 64 */ NULL
, NULL
, NULL
, NULL
,
14085 /* 68 */ NULL
, NULL
, NULL
, NULL
,
14086 /* 6C */ NULL
, NULL
, NULL
, NULL
,
14087 /* 70 */ NULL
, NULL
, NULL
, NULL
,
14088 /* 74 */ NULL
, NULL
, NULL
, NULL
,
14089 /* 78 */ NULL
, NULL
, NULL
, NULL
,
14090 /* 7C */ NULL
, NULL
, NULL
, NULL
,
14091 /* 80 */ NULL
, NULL
, NULL
, NULL
,
14092 /* 84 */ NULL
, NULL
, NULL
, NULL
,
14093 /* 88 */ NULL
, NULL
, "pfnacc", NULL
,
14094 /* 8C */ NULL
, NULL
, "pfpnacc", NULL
,
14095 /* 90 */ "pfcmpge", NULL
, NULL
, NULL
,
14096 /* 94 */ "pfmin", NULL
, "pfrcp", "pfrsqrt",
14097 /* 98 */ NULL
, NULL
, "pfsub", NULL
,
14098 /* 9C */ NULL
, NULL
, "pfadd", NULL
,
14099 /* A0 */ "pfcmpgt", NULL
, NULL
, NULL
,
14100 /* A4 */ "pfmax", NULL
, "pfrcpit1", "pfrsqit1",
14101 /* A8 */ NULL
, NULL
, "pfsubr", NULL
,
14102 /* AC */ NULL
, NULL
, "pfacc", NULL
,
14103 /* B0 */ "pfcmpeq", NULL
, NULL
, NULL
,
14104 /* B4 */ "pfmul", NULL
, "pfrcpit2", "pmulhrw",
14105 /* B8 */ NULL
, NULL
, NULL
, "pswapd",
14106 /* BC */ NULL
, NULL
, NULL
, "pavgusb",
14107 /* C0 */ NULL
, NULL
, NULL
, NULL
,
14108 /* C4 */ NULL
, NULL
, NULL
, NULL
,
14109 /* C8 */ NULL
, NULL
, NULL
, NULL
,
14110 /* CC */ NULL
, NULL
, NULL
, NULL
,
14111 /* D0 */ NULL
, NULL
, NULL
, NULL
,
14112 /* D4 */ NULL
, NULL
, NULL
, NULL
,
14113 /* D8 */ NULL
, NULL
, NULL
, NULL
,
14114 /* DC */ NULL
, NULL
, NULL
, NULL
,
14115 /* E0 */ NULL
, NULL
, NULL
, NULL
,
14116 /* E4 */ NULL
, NULL
, NULL
, NULL
,
14117 /* E8 */ NULL
, NULL
, NULL
, NULL
,
14118 /* EC */ NULL
, NULL
, NULL
, NULL
,
14119 /* F0 */ NULL
, NULL
, NULL
, NULL
,
14120 /* F4 */ NULL
, NULL
, NULL
, NULL
,
14121 /* F8 */ NULL
, NULL
, NULL
, NULL
,
14122 /* FC */ NULL
, NULL
, NULL
, NULL
,
14126 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
14128 const char *mnemonic
;
14130 FETCH_DATA (the_info
, codep
+ 1);
14131 /* AMD 3DNow! instructions are specified by an opcode suffix in the
14132 place where an 8-bit immediate would normally go. ie. the last
14133 byte of the instruction. */
14134 obufp
= mnemonicendp
;
14135 mnemonic
= Suffix3DNow
[*codep
++ & 0xff];
14137 oappend (mnemonic
);
14140 /* Since a variable sized modrm/sib chunk is between the start
14141 of the opcode (0x0f0f) and the opcode suffix, we need to do
14142 all the modrm processing first, and don't know until now that
14143 we have a bad opcode. This necessitates some cleaning up. */
14144 op_out
[0][0] = '\0';
14145 op_out
[1][0] = '\0';
14148 mnemonicendp
= obufp
;
14151 static struct op simd_cmp_op
[] =
14153 { STRING_COMMA_LEN ("eq") },
14154 { STRING_COMMA_LEN ("lt") },
14155 { STRING_COMMA_LEN ("le") },
14156 { STRING_COMMA_LEN ("unord") },
14157 { STRING_COMMA_LEN ("neq") },
14158 { STRING_COMMA_LEN ("nlt") },
14159 { STRING_COMMA_LEN ("nle") },
14160 { STRING_COMMA_LEN ("ord") }
14164 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
14166 unsigned int cmp_type
;
14168 FETCH_DATA (the_info
, codep
+ 1);
14169 cmp_type
= *codep
++ & 0xff;
14170 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
))
14173 char *p
= mnemonicendp
- 2;
14177 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
14178 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
14182 /* We have a reserved extension byte. Output it directly. */
14183 scratchbuf
[0] = '$';
14184 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
14185 oappend (scratchbuf
+ intel_syntax
);
14186 scratchbuf
[0] = '\0';
14191 OP_Mwait (int bytemode ATTRIBUTE_UNUSED
,
14192 int sizeflag ATTRIBUTE_UNUSED
)
14194 /* mwait %eax,%ecx */
14197 const char **names
= (address_mode
== mode_64bit
14198 ? names64
: names32
);
14199 strcpy (op_out
[0], names
[0]);
14200 strcpy (op_out
[1], names
[1]);
14201 two_source_ops
= 1;
14203 /* Skip mod/rm byte. */
14209 OP_Monitor (int bytemode ATTRIBUTE_UNUSED
,
14210 int sizeflag ATTRIBUTE_UNUSED
)
14212 /* monitor %eax,%ecx,%edx" */
14215 const char **op1_names
;
14216 const char **names
= (address_mode
== mode_64bit
14217 ? names64
: names32
);
14219 if (!(prefixes
& PREFIX_ADDR
))
14220 op1_names
= (address_mode
== mode_16bit
14221 ? names16
: names
);
14224 /* Remove "addr16/addr32". */
14225 all_prefixes
[last_addr_prefix
] = 0;
14226 op1_names
= (address_mode
!= mode_32bit
14227 ? names32
: names16
);
14228 used_prefixes
|= PREFIX_ADDR
;
14230 strcpy (op_out
[0], op1_names
[0]);
14231 strcpy (op_out
[1], names
[1]);
14232 strcpy (op_out
[2], names
[2]);
14233 two_source_ops
= 1;
14235 /* Skip mod/rm byte. */
14243 /* Throw away prefixes and 1st. opcode byte. */
14244 codep
= insn_codep
+ 1;
14249 REP_Fixup (int bytemode
, int sizeflag
)
14251 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
14253 if (prefixes
& PREFIX_REPZ
)
14254 all_prefixes
[last_repz_prefix
] = REP_PREFIX
;
14261 OP_IMREG (bytemode
, sizeflag
);
14264 OP_ESreg (bytemode
, sizeflag
);
14267 OP_DSreg (bytemode
, sizeflag
);
14276 CMPXCHG8B_Fixup (int bytemode
, int sizeflag
)
14281 /* Change cmpxchg8b to cmpxchg16b. */
14282 char *p
= mnemonicendp
- 2;
14283 mnemonicendp
= stpcpy (p
, "16b");
14286 OP_M (bytemode
, sizeflag
);
14290 XMM_Fixup (int reg
, int sizeflag ATTRIBUTE_UNUSED
)
14292 const char **names
;
14296 switch (vex
.length
)
14310 oappend (names
[reg
]);
14314 CRC32_Fixup (int bytemode
, int sizeflag
)
14316 /* Add proper suffix to "crc32". */
14317 char *p
= mnemonicendp
;
14336 if (sizeflag
& DFLAG
)
14340 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14344 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14351 if (modrm
.mod
== 3)
14355 /* Skip mod/rm byte. */
14360 add
= (rex
& REX_B
) ? 8 : 0;
14361 if (bytemode
== b_mode
)
14365 oappend (names8rex
[modrm
.rm
+ add
]);
14367 oappend (names8
[modrm
.rm
+ add
]);
14373 oappend (names64
[modrm
.rm
+ add
]);
14374 else if ((prefixes
& PREFIX_DATA
))
14375 oappend (names16
[modrm
.rm
+ add
]);
14377 oappend (names32
[modrm
.rm
+ add
]);
14381 OP_E (bytemode
, sizeflag
);
14385 FXSAVE_Fixup (int bytemode
, int sizeflag
)
14387 /* Add proper suffix to "fxsave" and "fxrstor". */
14391 char *p
= mnemonicendp
;
14397 OP_M (bytemode
, sizeflag
);
14400 /* Display the destination register operand for instructions with
14404 OP_VEX (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
14407 const char **names
;
14415 reg
= vex
.register_specifier
;
14416 if (bytemode
== vex_scalar_mode
)
14418 oappend (names_xmm
[reg
]);
14422 switch (vex
.length
)
14454 oappend (names
[reg
]);
14457 /* Get the VEX immediate byte without moving codep. */
14459 static unsigned char
14460 get_vex_imm8 (int sizeflag
, int opnum
)
14462 int bytes_before_imm
= 0;
14464 if (modrm
.mod
!= 3)
14466 /* There are SIB/displacement bytes. */
14467 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
14469 /* 32/64 bit address mode */
14470 int base
= modrm
.rm
;
14472 /* Check SIB byte. */
14475 FETCH_DATA (the_info
, codep
+ 1);
14477 /* When decoding the third source, don't increase
14478 bytes_before_imm as this has already been incremented
14479 by one in OP_E_memory while decoding the second
14482 bytes_before_imm
++;
14485 /* Don't increase bytes_before_imm when decoding the third source,
14486 it has already been incremented by OP_E_memory while decoding
14487 the second source operand. */
14493 /* When modrm.rm == 5 or modrm.rm == 4 and base in
14494 SIB == 5, there is a 4 byte displacement. */
14496 /* No displacement. */
14499 /* 4 byte displacement. */
14500 bytes_before_imm
+= 4;
14503 /* 1 byte displacement. */
14504 bytes_before_imm
++;
14511 /* 16 bit address mode */
14512 /* Don't increase bytes_before_imm when decoding the third source,
14513 it has already been incremented by OP_E_memory while decoding
14514 the second source operand. */
14520 /* When modrm.rm == 6, there is a 2 byte displacement. */
14522 /* No displacement. */
14525 /* 2 byte displacement. */
14526 bytes_before_imm
+= 2;
14529 /* 1 byte displacement: when decoding the third source,
14530 don't increase bytes_before_imm as this has already
14531 been incremented by one in OP_E_memory while decoding
14532 the second source operand. */
14534 bytes_before_imm
++;
14542 FETCH_DATA (the_info
, codep
+ bytes_before_imm
+ 1);
14543 return codep
[bytes_before_imm
];
14547 OP_EX_VexReg (int bytemode
, int sizeflag
, int reg
)
14549 const char **names
;
14551 if (reg
== -1 && modrm
.mod
!= 3)
14553 OP_E_memory (bytemode
, sizeflag
);
14565 else if (reg
> 7 && address_mode
!= mode_64bit
)
14569 switch (vex
.length
)
14580 oappend (names
[reg
]);
14584 OP_Vex_2src (int bytemode
, int sizeflag
)
14586 if (modrm
.mod
== 3)
14588 int reg
= modrm
.rm
;
14592 oappend (names_xmm
[reg
]);
14597 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
14599 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
14600 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14602 OP_E (bytemode
, sizeflag
);
14607 OP_Vex_2src_1 (int bytemode
, int sizeflag
)
14609 if (modrm
.mod
== 3)
14611 /* Skip mod/rm byte. */
14617 oappend (names_xmm
[vex
.register_specifier
]);
14619 OP_Vex_2src (bytemode
, sizeflag
);
14623 OP_Vex_2src_2 (int bytemode
, int sizeflag
)
14626 OP_Vex_2src (bytemode
, sizeflag
);
14628 oappend (names_xmm
[vex
.register_specifier
]);
14632 OP_EX_VexW (int bytemode
, int sizeflag
)
14640 /* Skip mod/rm byte. */
14645 reg
= get_vex_imm8 (sizeflag
, 0) >> 4;
14650 reg
= get_vex_imm8 (sizeflag
, 1) >> 4;
14653 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
14657 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED
,
14658 int sizeflag ATTRIBUTE_UNUSED
)
14660 /* Skip the immediate byte and check for invalid bits. */
14661 FETCH_DATA (the_info
, codep
+ 1);
14662 if (*codep
++ & 0xf)
14667 OP_REG_VexI4 (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
14670 const char **names
;
14672 FETCH_DATA (the_info
, codep
+ 1);
14675 if (bytemode
!= x_mode
)
14682 if (reg
> 7 && address_mode
!= mode_64bit
)
14685 switch (vex
.length
)
14696 oappend (names
[reg
]);
14700 OP_XMM_VexW (int bytemode
, int sizeflag
)
14702 /* Turn off the REX.W bit since it is used for swapping operands
14705 OP_XMM (bytemode
, sizeflag
);
14709 OP_EX_Vex (int bytemode
, int sizeflag
)
14711 if (modrm
.mod
!= 3)
14713 if (vex
.register_specifier
!= 0)
14717 OP_EX (bytemode
, sizeflag
);
14721 OP_XMM_Vex (int bytemode
, int sizeflag
)
14723 if (modrm
.mod
!= 3)
14725 if (vex
.register_specifier
!= 0)
14729 OP_XMM (bytemode
, sizeflag
);
14733 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
14735 switch (vex
.length
)
14738 mnemonicendp
= stpcpy (obuf
, "vzeroupper");
14741 mnemonicendp
= stpcpy (obuf
, "vzeroall");
14748 static struct op vex_cmp_op
[] =
14750 { STRING_COMMA_LEN ("eq") },
14751 { STRING_COMMA_LEN ("lt") },
14752 { STRING_COMMA_LEN ("le") },
14753 { STRING_COMMA_LEN ("unord") },
14754 { STRING_COMMA_LEN ("neq") },
14755 { STRING_COMMA_LEN ("nlt") },
14756 { STRING_COMMA_LEN ("nle") },
14757 { STRING_COMMA_LEN ("ord") },
14758 { STRING_COMMA_LEN ("eq_uq") },
14759 { STRING_COMMA_LEN ("nge") },
14760 { STRING_COMMA_LEN ("ngt") },
14761 { STRING_COMMA_LEN ("false") },
14762 { STRING_COMMA_LEN ("neq_oq") },
14763 { STRING_COMMA_LEN ("ge") },
14764 { STRING_COMMA_LEN ("gt") },
14765 { STRING_COMMA_LEN ("true") },
14766 { STRING_COMMA_LEN ("eq_os") },
14767 { STRING_COMMA_LEN ("lt_oq") },
14768 { STRING_COMMA_LEN ("le_oq") },
14769 { STRING_COMMA_LEN ("unord_s") },
14770 { STRING_COMMA_LEN ("neq_us") },
14771 { STRING_COMMA_LEN ("nlt_uq") },
14772 { STRING_COMMA_LEN ("nle_uq") },
14773 { STRING_COMMA_LEN ("ord_s") },
14774 { STRING_COMMA_LEN ("eq_us") },
14775 { STRING_COMMA_LEN ("nge_uq") },
14776 { STRING_COMMA_LEN ("ngt_uq") },
14777 { STRING_COMMA_LEN ("false_os") },
14778 { STRING_COMMA_LEN ("neq_os") },
14779 { STRING_COMMA_LEN ("ge_oq") },
14780 { STRING_COMMA_LEN ("gt_oq") },
14781 { STRING_COMMA_LEN ("true_us") },
14785 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
14787 unsigned int cmp_type
;
14789 FETCH_DATA (the_info
, codep
+ 1);
14790 cmp_type
= *codep
++ & 0xff;
14791 if (cmp_type
< ARRAY_SIZE (vex_cmp_op
))
14794 char *p
= mnemonicendp
- 2;
14798 sprintf (p
, "%s%s", vex_cmp_op
[cmp_type
].name
, suffix
);
14799 mnemonicendp
+= vex_cmp_op
[cmp_type
].len
;
14803 /* We have a reserved extension byte. Output it directly. */
14804 scratchbuf
[0] = '$';
14805 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
14806 oappend (scratchbuf
+ intel_syntax
);
14807 scratchbuf
[0] = '\0';
14811 static const struct op pclmul_op
[] =
14813 { STRING_COMMA_LEN ("lql") },
14814 { STRING_COMMA_LEN ("hql") },
14815 { STRING_COMMA_LEN ("lqh") },
14816 { STRING_COMMA_LEN ("hqh") }
14820 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED
,
14821 int sizeflag ATTRIBUTE_UNUSED
)
14823 unsigned int pclmul_type
;
14825 FETCH_DATA (the_info
, codep
+ 1);
14826 pclmul_type
= *codep
++ & 0xff;
14827 switch (pclmul_type
)
14838 if (pclmul_type
< ARRAY_SIZE (pclmul_op
))
14841 char *p
= mnemonicendp
- 3;
14846 sprintf (p
, "%s%s", pclmul_op
[pclmul_type
].name
, suffix
);
14847 mnemonicendp
+= pclmul_op
[pclmul_type
].len
;
14851 /* We have a reserved extension byte. Output it directly. */
14852 scratchbuf
[0] = '$';
14853 print_operand_value (scratchbuf
+ 1, 1, pclmul_type
);
14854 oappend (scratchbuf
+ intel_syntax
);
14855 scratchbuf
[0] = '\0';
14860 MOVBE_Fixup (int bytemode
, int sizeflag
)
14862 /* Add proper suffix to "movbe". */
14863 char *p
= mnemonicendp
;
14872 if (sizeflag
& SUFFIX_ALWAYS
)
14878 if (sizeflag
& DFLAG
)
14882 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14887 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14894 OP_M (bytemode
, sizeflag
);
14898 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
14901 const char **names
;
14903 /* Skip mod/rm byte. */
14909 else if (vex
.length
== 256)
14919 oappend (names
[reg
]);
14923 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
14925 const char **names
;
14929 else if (vex
.length
== 256)
14934 oappend (names
[vex
.register_specifier
]);
14938 OP_LWP_I (int bytemode ATTRIBUTE_UNUSED
, int sizeflag
)
14940 if (vex
.w
|| vex
.length
== 256)
14941 OP_I (q_mode
, sizeflag
);
14943 OP_I (w_mode
, sizeflag
);