opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2016 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "dis-asm.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40
  41 #include <setjmp.h>
  42
  43 static int print_insn (bfd_vma, disassemble_info *);
  44 static void dofloat (int);
  45 static void OP_ST (int, int);
  46 static void OP_STi (int, int);
  47 static int putop (const char *, int);
  48 static void oappend (const char *);
  49 static void append_seg (void);
  50 static void OP_indirE (int, int);
  51 static void print_operand_value (char *, int, bfd_vma);
  52 static void OP_E_register (int, int);
  53 static void OP_E_memory (int, int);
  54 static void print_displacement (char *, bfd_vma);
  55 static void OP_E (int, int);
  56 static void OP_G (int, int);
  57 static bfd_vma get64 (void);
  58 static bfd_signed_vma get32 (void);
  59 static bfd_signed_vma get32s (void);
  60 static int get16 (void);
  61 static void set_op (bfd_vma, int);
  62 static void OP_Skip_MODRM (int, int);
  63 static void OP_REG (int, int);
  64 static void OP_IMREG (int, int);
  65 static void OP_I (int, int);
  66 static void OP_I64 (int, int);
  67 static void OP_sI (int, int);
  68 static void OP_J (int, int);
  69 static void OP_SEG (int, int);
  70 static void OP_DIR (int, int);
  71 static void OP_OFF (int, int);
  72 static void OP_OFF64 (int, int);
  73 static void ptr_reg (int, int);
  74 static void OP_ESreg (int, int);
  75 static void OP_DSreg (int, int);
  76 static void OP_C (int, int);
  77 static void OP_D (int, int);
  78 static void OP_T (int, int);
  79 static void OP_R (int, int);
  80 static void OP_MMX (int, int);
  81 static void OP_XMM (int, int);
  82 static void OP_EM (int, int);
  83 static void OP_EX (int, int);
  84 static void OP_EMC (int,int);
  85 static void OP_MXC (int,int);
  86 static void OP_MS (int, int);
  87 static void OP_XS (int, int);
  88 static void OP_M (int, int);
  89 static void OP_VEX (int, int);
  90 static void OP_EX_Vex (int, int);
  91 static void OP_EX_VexW (int, int);
  92 static void OP_EX_VexImmW (int, int);
  93 static void OP_XMM_Vex (int, int);
  94 static void OP_XMM_VexW (int, int);
  95 static void OP_Rounding (int, int);
  96 static void OP_REG_VexI4 (int, int);
  97 static void PCLMUL_Fixup (int, int);
  98 static void VEXI4_Fixup (int, int);
  99 static void VZERO_Fixup (int, int);
 100 static void VCMP_Fixup (int, int);
 101 static void VPCMP_Fixup (int, int);
 102 static void OP_0f07 (int, int);
 103 static void OP_Monitor (int, int);
 104 static void OP_Mwait (int, int);
 105 static void OP_Mwaitx (int, int);
 106 static void NOP_Fixup1 (int, int);
 107 static void NOP_Fixup2 (int, int);
 108 static void OP_3DNowSuffix (int, int);
 109 static void CMP_Fixup (int, int);
 110 static void BadOp (void);
 111 static void REP_Fixup (int, int);
 112 static void BND_Fixup (int, int);
 113 static void HLE_Fixup1 (int, int);
 114 static void HLE_Fixup2 (int, int);
 115 static void HLE_Fixup3 (int, int);
 116 static void CMPXCHG8B_Fixup (int, int);
 117 static void XMM_Fixup (int, int);
 118 static void CRC32_Fixup (int, int);
 119 static void FXSAVE_Fixup (int, int);
 120 static void OP_LWPCB_E (int, int);
 121 static void OP_LWP_E (int, int);
 122 static void OP_Vex_2src_1 (int, int);
 123 static void OP_Vex_2src_2 (int, int);
 124
 125 static void MOVBE_Fixup (int, int);
 126
 127 static void OP_Mask (int, int);
 128
 129 struct dis_private {
 130   /* Points to first byte not fetched.  */
 131   bfd_byte *max_fetched;
 132   bfd_byte the_buffer[MAX_MNEM_SIZE];
 133   bfd_vma insn_start;
 134   int orig_sizeflag;
 135   OPCODES_SIGJMP_BUF bailout;
 136 };
 137
 138 enum address_mode
 139 {
 140   mode_16bit,
 141   mode_32bit,
 142   mode_64bit
 143 };
 144
 145 enum address_mode address_mode;
 146
 147 /* Flags for the prefixes for the current instruction.  See below.  */
 148 static int prefixes;
 149
 150 /* REX prefix the current instruction.  See below.  */
 151 static int rex;
 152 /* Bits of REX we've already used.  */
 153 static int rex_used;
 154 /* REX bits in original REX prefix ignored.  */
 155 static int rex_ignored;
 156 /* Mark parts used in the REX prefix.  When we are testing for
 157    empty prefix (for 8bit register REX extension), just mask it
 158    out.  Otherwise test for REX bit is excuse for existence of REX
 159    only in case value is nonzero.  */
 160 #define USED_REX(value)                                 \
 161   {                                                     \
 162     if (value)                                          \
 163       {                                                 \
 164         if ((rex & value))                              \
 165           rex_used |= (value) | REX_OPCODE;             \
 166       }                                                 \
 167     else                                                \
 168       rex_used |= REX_OPCODE;                           \
 169   }
 170
 171 /* Flags for prefixes which we somehow handled when printing the
 172    current instruction.  */
 173 static int used_prefixes;
 174
 175 /* Flags stored in PREFIXES.  */
 176 #define PREFIX_REPZ 1
 177 #define PREFIX_REPNZ 2
 178 #define PREFIX_LOCK 4
 179 #define PREFIX_CS 8
 180 #define PREFIX_SS 0x10
 181 #define PREFIX_DS 0x20
 182 #define PREFIX_ES 0x40
 183 #define PREFIX_FS 0x80
 184 #define PREFIX_GS 0x100
 185 #define PREFIX_DATA 0x200
 186 #define PREFIX_ADDR 0x400
 187 #define PREFIX_FWAIT 0x800
 188
 189 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 190    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 191    on error.  */
 192 #define FETCH_DATA(info, addr) \
 193   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 194    ? 1 : fetch_data ((info), (addr)))
 195
 196 static int
 197 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 198 {
 199   int status;
 200   struct dis_private *priv = (struct dis_private *) info->private_data;
 201   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 202
 203   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 204     status = (*info->read_memory_func) (start,
 205                                         priv->max_fetched,
 206                                         addr - priv->max_fetched,
 207                                         info);
 208   else
 209     status = -1;
 210   if (status != 0)
 211     {
 212       /* If we did manage to read at least one byte, then
 213          print_insn_i386 will do something sensible.  Otherwise, print
 214          an error.  We do that here because this is where we know
 215          STATUS.  */
 216       if (priv->max_fetched == priv->the_buffer)
 217         (*info->memory_error_func) (status, start, info);
 218       OPCODES_SIGLONGJMP (priv->bailout, 1);
 219     }
 220   else
 221     priv->max_fetched = addr;
 222   return 1;
 223 }
 224
 225 /* Possible values for prefix requirement.  */
 226 #define PREFIX_IGNORED_SHIFT    16
 227 #define PREFIX_IGNORED_REPZ     (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
 228 #define PREFIX_IGNORED_REPNZ    (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
 229 #define PREFIX_IGNORED_DATA     (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
 230 #define PREFIX_IGNORED_ADDR     (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
 231 #define PREFIX_IGNORED_LOCK     (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
 232
 233 /* Opcode prefixes.  */
 234 #define PREFIX_OPCODE           (PREFIX_REPZ \
 235                                  | PREFIX_REPNZ \
 236                                  | PREFIX_DATA)
 237
 238 /* Prefixes ignored.  */
 239 #define PREFIX_IGNORED          (PREFIX_IGNORED_REPZ \
 240                                  | PREFIX_IGNORED_REPNZ \
 241                                  | PREFIX_IGNORED_DATA)
 242
 243 #define XX { NULL, 0 }
 244 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
 245
 246 #define Eb { OP_E, b_mode }
 247 #define Ebnd { OP_E, bnd_mode }
 248 #define EbS { OP_E, b_swap_mode }
 249 #define Ev { OP_E, v_mode }
 250 #define Ev_bnd { OP_E, v_bnd_mode }
 251 #define EvS { OP_E, v_swap_mode }
 252 #define Ed { OP_E, d_mode }
 253 #define Edq { OP_E, dq_mode }
 254 #define Edqw { OP_E, dqw_mode }
 255 #define EdqwS { OP_E, dqw_swap_mode }
 256 #define Edqb { OP_E, dqb_mode }
 257 #define Edb { OP_E, db_mode }
 258 #define Edw { OP_E, dw_mode }
 259 #define Edqd { OP_E, dqd_mode }
 260 #define Eq { OP_E, q_mode }
 261 #define indirEv { OP_indirE, stack_v_mode }
 262 #define indirEp { OP_indirE, f_mode }
 263 #define stackEv { OP_E, stack_v_mode }
 264 #define Em { OP_E, m_mode }
 265 #define Ew { OP_E, w_mode }
 266 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 267 #define Ma { OP_M, a_mode }
 268 #define Mb { OP_M, b_mode }
 269 #define Md { OP_M, d_mode }
 270 #define Mo { OP_M, o_mode }
 271 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 272 #define Mq { OP_M, q_mode }
 273 #define Mx { OP_M, x_mode }
 274 #define Mxmm { OP_M, xmm_mode }
 275 #define Gb { OP_G, b_mode }
 276 #define Gbnd { OP_G, bnd_mode }
 277 #define Gv { OP_G, v_mode }
 278 #define Gd { OP_G, d_mode }
 279 #define Gdq { OP_G, dq_mode }
 280 #define Gm { OP_G, m_mode }
 281 #define Gw { OP_G, w_mode }
 282 #define Rd { OP_R, d_mode }
 283 #define Rdq { OP_R, dq_mode }
 284 #define Rm { OP_R, m_mode }
 285 #define Ib { OP_I, b_mode }
 286 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 287 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 288 #define Iv { OP_I, v_mode }
 289 #define sIv { OP_sI, v_mode }
 290 #define Iq { OP_I, q_mode }
 291 #define Iv64 { OP_I64, v_mode }
 292 #define Iw { OP_I, w_mode }
 293 #define I1 { OP_I, const_1_mode }
 294 #define Jb { OP_J, b_mode }
 295 #define Jv { OP_J, v_mode }
 296 #define Cm { OP_C, m_mode }
 297 #define Dm { OP_D, m_mode }
 298 #define Td { OP_T, d_mode }
 299 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 300
 301 #define RMeAX { OP_REG, eAX_reg }
 302 #define RMeBX { OP_REG, eBX_reg }
 303 #define RMeCX { OP_REG, eCX_reg }
 304 #define RMeDX { OP_REG, eDX_reg }
 305 #define RMeSP { OP_REG, eSP_reg }
 306 #define RMeBP { OP_REG, eBP_reg }
 307 #define RMeSI { OP_REG, eSI_reg }
 308 #define RMeDI { OP_REG, eDI_reg }
 309 #define RMrAX { OP_REG, rAX_reg }
 310 #define RMrBX { OP_REG, rBX_reg }
 311 #define RMrCX { OP_REG, rCX_reg }
 312 #define RMrDX { OP_REG, rDX_reg }
 313 #define RMrSP { OP_REG, rSP_reg }
 314 #define RMrBP { OP_REG, rBP_reg }
 315 #define RMrSI { OP_REG, rSI_reg }
 316 #define RMrDI { OP_REG, rDI_reg }
 317 #define RMAL { OP_REG, al_reg }
 318 #define RMCL { OP_REG, cl_reg }
 319 #define RMDL { OP_REG, dl_reg }
 320 #define RMBL { OP_REG, bl_reg }
 321 #define RMAH { OP_REG, ah_reg }
 322 #define RMCH { OP_REG, ch_reg }
 323 #define RMDH { OP_REG, dh_reg }
 324 #define RMBH { OP_REG, bh_reg }
 325 #define RMAX { OP_REG, ax_reg }
 326 #define RMDX { OP_REG, dx_reg }
 327
 328 #define eAX { OP_IMREG, eAX_reg }
 329 #define eBX { OP_IMREG, eBX_reg }
 330 #define eCX { OP_IMREG, eCX_reg }
 331 #define eDX { OP_IMREG, eDX_reg }
 332 #define eSP { OP_IMREG, eSP_reg }
 333 #define eBP { OP_IMREG, eBP_reg }
 334 #define eSI { OP_IMREG, eSI_reg }
 335 #define eDI { OP_IMREG, eDI_reg }
 336 #define AL { OP_IMREG, al_reg }
 337 #define CL { OP_IMREG, cl_reg }
 338 #define DL { OP_IMREG, dl_reg }
 339 #define BL { OP_IMREG, bl_reg }
 340 #define AH { OP_IMREG, ah_reg }
 341 #define CH { OP_IMREG, ch_reg }
 342 #define DH { OP_IMREG, dh_reg }
 343 #define BH { OP_IMREG, bh_reg }
 344 #define AX { OP_IMREG, ax_reg }
 345 #define DX { OP_IMREG, dx_reg }
 346 #define zAX { OP_IMREG, z_mode_ax_reg }
 347 #define indirDX { OP_IMREG, indir_dx_reg }
 348
 349 #define Sw { OP_SEG, w_mode }
 350 #define Sv { OP_SEG, v_mode }
 351 #define Ap { OP_DIR, 0 }
 352 #define Ob { OP_OFF64, b_mode }
 353 #define Ov { OP_OFF64, v_mode }
 354 #define Xb { OP_DSreg, eSI_reg }
 355 #define Xv { OP_DSreg, eSI_reg }
 356 #define Xz { OP_DSreg, eSI_reg }
 357 #define Yb { OP_ESreg, eDI_reg }
 358 #define Yv { OP_ESreg, eDI_reg }
 359 #define DSBX { OP_DSreg, eBX_reg }
 360
 361 #define es { OP_REG, es_reg }
 362 #define ss { OP_REG, ss_reg }
 363 #define cs { OP_REG, cs_reg }
 364 #define ds { OP_REG, ds_reg }
 365 #define fs { OP_REG, fs_reg }
 366 #define gs { OP_REG, gs_reg }
 367
 368 #define MX { OP_MMX, 0 }
 369 #define XM { OP_XMM, 0 }
 370 #define XMScalar { OP_XMM, scalar_mode }
 371 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 372 #define XMM { OP_XMM, xmm_mode }
 373 #define XMxmmq { OP_XMM, xmmq_mode }
 374 #define EM { OP_EM, v_mode }
 375 #define EMS { OP_EM, v_swap_mode }
 376 #define EMd { OP_EM, d_mode }
 377 #define EMx { OP_EM, x_mode }
 378 #define EXw { OP_EX, w_mode }
 379 #define EXd { OP_EX, d_mode }
 380 #define EXdScalar { OP_EX, d_scalar_mode }
 381 #define EXdS { OP_EX, d_swap_mode }
 382 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
 383 #define EXq { OP_EX, q_mode }
 384 #define EXqScalar { OP_EX, q_scalar_mode }
 385 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
 386 #define EXqS { OP_EX, q_swap_mode }
 387 #define EXx { OP_EX, x_mode }
 388 #define EXxS { OP_EX, x_swap_mode }
 389 #define EXxmm { OP_EX, xmm_mode }
 390 #define EXymm { OP_EX, ymm_mode }
 391 #define EXxmmq { OP_EX, xmmq_mode }
 392 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 393 #define EXxmm_mb { OP_EX, xmm_mb_mode }
 394 #define EXxmm_mw { OP_EX, xmm_mw_mode }
 395 #define EXxmm_md { OP_EX, xmm_md_mode }
 396 #define EXxmm_mq { OP_EX, xmm_mq_mode }
 397 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
 398 #define EXxmmdw { OP_EX, xmmdw_mode }
 399 #define EXxmmqd { OP_EX, xmmqd_mode }
 400 #define EXymmq { OP_EX, ymmq_mode }
 401 #define EXVexWdq { OP_EX, vex_w_dq_mode }
 402 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 403 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 404 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 405 #define MS { OP_MS, v_mode }
 406 #define XS { OP_XS, v_mode }
 407 #define EMCq { OP_EMC, q_mode }
 408 #define MXC { OP_MXC, 0 }
 409 #define OPSUF { OP_3DNowSuffix, 0 }
 410 #define CMP { CMP_Fixup, 0 }
 411 #define XMM0 { XMM_Fixup, 0 }
 412 #define FXSAVE { FXSAVE_Fixup, 0 }
 413 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
 414 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
 415
 416 #define Vex { OP_VEX, vex_mode }
 417 #define VexScalar { OP_VEX, vex_scalar_mode }
 418 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 419 #define Vex128 { OP_VEX, vex128_mode }
 420 #define Vex256 { OP_VEX, vex256_mode }
 421 #define VexGdq { OP_VEX, dq_mode }
 422 #define VexI4 { VEXI4_Fixup, 0}
 423 #define EXdVex { OP_EX_Vex, d_mode }
 424 #define EXdVexS { OP_EX_Vex, d_swap_mode }
 425 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
 426 #define EXqVex { OP_EX_Vex, q_mode }
 427 #define EXqVexS { OP_EX_Vex, q_swap_mode }
 428 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
 429 #define EXVexW { OP_EX_VexW, x_mode }
 430 #define EXdVexW { OP_EX_VexW, d_mode }
 431 #define EXqVexW { OP_EX_VexW, q_mode }
 432 #define EXVexImmW { OP_EX_VexImmW, x_mode }
 433 #define XMVex { OP_XMM_Vex, 0 }
 434 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
 435 #define XMVexW { OP_XMM_VexW, 0 }
 436 #define XMVexI4 { OP_REG_VexI4, x_mode }
 437 #define PCLMUL { PCLMUL_Fixup, 0 }
 438 #define VZERO { VZERO_Fixup, 0 }
 439 #define VCMP { VCMP_Fixup, 0 }
 440 #define VPCMP { VPCMP_Fixup, 0 }
 441
 442 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 443 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 444
 445 #define XMask { OP_Mask, mask_mode }
 446 #define MaskG { OP_G, mask_mode }
 447 #define MaskE { OP_E, mask_mode }
 448 #define MaskBDE { OP_E, mask_bd_mode }
 449 #define MaskR { OP_R, mask_mode }
 450 #define MaskVex { OP_VEX, mask_mode }
 451
 452 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 453 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
 454 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 455 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
 456
 457 /* Used handle "rep" prefix for string instructions.  */
 458 #define Xbr { REP_Fixup, eSI_reg }
 459 #define Xvr { REP_Fixup, eSI_reg }
 460 #define Ybr { REP_Fixup, eDI_reg }
 461 #define Yvr { REP_Fixup, eDI_reg }
 462 #define Yzr { REP_Fixup, eDI_reg }
 463 #define indirDXr { REP_Fixup, indir_dx_reg }
 464 #define ALr { REP_Fixup, al_reg }
 465 #define eAXr { REP_Fixup, eAX_reg }
 466
 467 /* Used handle HLE prefix for lockable instructions.  */
 468 #define Ebh1 { HLE_Fixup1, b_mode }
 469 #define Evh1 { HLE_Fixup1, v_mode }
 470 #define Ebh2 { HLE_Fixup2, b_mode }
 471 #define Evh2 { HLE_Fixup2, v_mode }
 472 #define Ebh3 { HLE_Fixup3, b_mode }
 473 #define Evh3 { HLE_Fixup3, v_mode }
 474
 475 #define BND { BND_Fixup, 0 }
 476
 477 #define cond_jump_flag { NULL, cond_jump_mode }
 478 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 479
 480 /* bits in sizeflag */
 481 #define SUFFIX_ALWAYS 4
 482 #define AFLAG 2
 483 #define DFLAG 1
 484
 485 enum
 486 {
 487   /* byte operand */
 488   b_mode = 1,
 489   /* byte operand with operand swapped */
 490   b_swap_mode,
 491   /* byte operand, sign extend like 'T' suffix */
 492   b_T_mode,
 493   /* operand size depends on prefixes */
 494   v_mode,
 495   /* operand size depends on prefixes with operand swapped */
 496   v_swap_mode,
 497   /* word operand */
 498   w_mode,
 499   /* double word operand  */
 500   d_mode,
 501   /* double word operand with operand swapped */
 502   d_swap_mode,
 503   /* quad word operand */
 504   q_mode,
 505   /* quad word operand with operand swapped */
 506   q_swap_mode,
 507   /* ten-byte operand */
 508   t_mode,
 509   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 510      broadcast enabled.  */
 511   x_mode,
 512   /* Similar to x_mode, but with different EVEX mem shifts.  */
 513   evex_x_gscat_mode,
 514   /* Similar to x_mode, but with disabled broadcast.  */
 515   evex_x_nobcst_mode,
 516   /* Similar to x_mode, but with operands swapped and disabled broadcast
 517      in EVEX.  */
 518   x_swap_mode,
 519   /* 16-byte XMM operand */
 520   xmm_mode,
 521   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 522      memory operand (depending on vector length).  Broadcast isn't
 523      allowed.  */
 524   xmmq_mode,
 525   /* Same as xmmq_mode, but broadcast is allowed.  */
 526   evex_half_bcst_xmmq_mode,
 527   /* XMM register or byte memory operand */
 528   xmm_mb_mode,
 529   /* XMM register or word memory operand */
 530   xmm_mw_mode,
 531   /* XMM register or double word memory operand */
 532   xmm_md_mode,
 533   /* XMM register or quad word memory operand */
 534   xmm_mq_mode,
 535   /* XMM register or double/quad word memory operand, depending on
 536      VEX.W.  */
 537   xmm_mdq_mode,
 538   /* 16-byte XMM, word, double word or quad word operand.  */
 539   xmmdw_mode,
 540   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 541   xmmqd_mode,
 542   /* 32-byte YMM operand */
 543   ymm_mode,
 544   /* quad word, ymmword or zmmword memory operand.  */
 545   ymmq_mode,
 546   /* 32-byte YMM or 16-byte word operand */
 547   ymmxmm_mode,
 548   /* d_mode in 32bit, q_mode in 64bit mode.  */
 549   m_mode,
 550   /* pair of v_mode operands */
 551   a_mode,
 552   cond_jump_mode,
 553   loop_jcxz_mode,
 554   v_bnd_mode,
 555   /* operand size depends on REX prefixes.  */
 556   dq_mode,
 557   /* registers like dq_mode, memory like w_mode.  */
 558   dqw_mode,
 559   dqw_swap_mode,
 560   bnd_mode,
 561   /* 4- or 6-byte pointer operand */
 562   f_mode,
 563   const_1_mode,
 564   /* v_mode for stack-related opcodes.  */
 565   stack_v_mode,
 566   /* non-quad operand size depends on prefixes */
 567   z_mode,
 568   /* 16-byte operand */
 569   o_mode,
 570   /* registers like dq_mode, memory like b_mode.  */
 571   dqb_mode,
 572   /* registers like d_mode, memory like b_mode.  */
 573   db_mode,
 574   /* registers like d_mode, memory like w_mode.  */
 575   dw_mode,
 576   /* registers like dq_mode, memory like d_mode.  */
 577   dqd_mode,
 578   /* normal vex mode */
 579   vex_mode,
 580   /* 128bit vex mode */
 581   vex128_mode,
 582   /* 256bit vex mode */
 583   vex256_mode,
 584   /* operand size depends on the VEX.W bit.  */
 585   vex_w_dq_mode,
 586
 587   /* Similar to vex_w_dq_mode, with VSIB dword indices.  */
 588   vex_vsib_d_w_dq_mode,
 589   /* Similar to vex_vsib_d_w_dq_mode, with smaller memory.  */
 590   vex_vsib_d_w_d_mode,
 591   /* Similar to vex_w_dq_mode, with VSIB qword indices.  */
 592   vex_vsib_q_w_dq_mode,
 593   /* Similar to vex_vsib_q_w_dq_mode, with smaller memory.  */
 594   vex_vsib_q_w_d_mode,
 595
 596   /* scalar, ignore vector length.  */
 597   scalar_mode,
 598   /* like d_mode, ignore vector length.  */
 599   d_scalar_mode,
 600   /* like d_swap_mode, ignore vector length.  */
 601   d_scalar_swap_mode,
 602   /* like q_mode, ignore vector length.  */
 603   q_scalar_mode,
 604   /* like q_swap_mode, ignore vector length.  */
 605   q_scalar_swap_mode,
 606   /* like vex_mode, ignore vector length.  */
 607   vex_scalar_mode,
 608   /* like vex_w_dq_mode, ignore vector length.  */
 609   vex_scalar_w_dq_mode,
 610
 611   /* Static rounding.  */
 612   evex_rounding_mode,
 613   /* Supress all exceptions.  */
 614   evex_sae_mode,
 615
 616   /* Mask register operand.  */
 617   mask_mode,
 618   /* Mask register operand.  */
 619   mask_bd_mode,
 620
 621   es_reg,
 622   cs_reg,
 623   ss_reg,
 624   ds_reg,
 625   fs_reg,
 626   gs_reg,
 627
 628   eAX_reg,
 629   eCX_reg,
 630   eDX_reg,
 631   eBX_reg,
 632   eSP_reg,
 633   eBP_reg,
 634   eSI_reg,
 635   eDI_reg,
 636
 637   al_reg,
 638   cl_reg,
 639   dl_reg,
 640   bl_reg,
 641   ah_reg,
 642   ch_reg,
 643   dh_reg,
 644   bh_reg,
 645
 646   ax_reg,
 647   cx_reg,
 648   dx_reg,
 649   bx_reg,
 650   sp_reg,
 651   bp_reg,
 652   si_reg,
 653   di_reg,
 654
 655   rAX_reg,
 656   rCX_reg,
 657   rDX_reg,
 658   rBX_reg,
 659   rSP_reg,
 660   rBP_reg,
 661   rSI_reg,
 662   rDI_reg,
 663
 664   z_mode_ax_reg,
 665   indir_dx_reg
 666 };
 667
 668 enum
 669 {
 670   FLOATCODE = 1,
 671   USE_REG_TABLE,
 672   USE_MOD_TABLE,
 673   USE_RM_TABLE,
 674   USE_PREFIX_TABLE,
 675   USE_X86_64_TABLE,
 676   USE_3BYTE_TABLE,
 677   USE_XOP_8F_TABLE,
 678   USE_VEX_C4_TABLE,
 679   USE_VEX_C5_TABLE,
 680   USE_VEX_LEN_TABLE,
 681   USE_VEX_W_TABLE,
 682   USE_EVEX_TABLE
 683 };
 684
 685 #define FLOAT                   NULL, { { NULL, FLOATCODE } }, 0
 686
 687 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }, 0
 688 #define DIS386_PREFIX(T, I, P)          NULL, { { NULL, (T)}, { NULL,  (I) } }, P
 689 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 690 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 691 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 692 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 693 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 694 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 695 #define THREE_BYTE_TABLE_PREFIX(I, P)   DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
 696 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 697 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 698 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 699 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 700 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 701 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 702
 703 enum
 704 {
 705   REG_80 = 0,
 706   REG_81,
 707   REG_82,
 708   REG_8F,
 709   REG_C0,
 710   REG_C1,
 711   REG_C6,
 712   REG_C7,
 713   REG_D0,
 714   REG_D1,
 715   REG_D2,
 716   REG_D3,
 717   REG_F6,
 718   REG_F7,
 719   REG_FE,
 720   REG_FF,
 721   REG_0F00,
 722   REG_0F01,
 723   REG_0F0D,
 724   REG_0F18,
 725   REG_0F71,
 726   REG_0F72,
 727   REG_0F73,
 728   REG_0FA6,
 729   REG_0FA7,
 730   REG_0FAE,
 731   REG_0FBA,
 732   REG_0FC7,
 733   REG_VEX_0F71,
 734   REG_VEX_0F72,
 735   REG_VEX_0F73,
 736   REG_VEX_0FAE,
 737   REG_VEX_0F38F3,
 738   REG_XOP_LWPCB,
 739   REG_XOP_LWP,
 740   REG_XOP_TBM_01,
 741   REG_XOP_TBM_02,
 742
 743   REG_EVEX_0F71,
 744   REG_EVEX_0F72,
 745   REG_EVEX_0F73,
 746   REG_EVEX_0F38C6,
 747   REG_EVEX_0F38C7
 748 };
 749
 750 enum
 751 {
 752   MOD_8D = 0,
 753   MOD_C6_REG_7,
 754   MOD_C7_REG_7,
 755   MOD_FF_REG_3,
 756   MOD_FF_REG_5,
 757   MOD_0F01_REG_0,
 758   MOD_0F01_REG_1,
 759   MOD_0F01_REG_2,
 760   MOD_0F01_REG_3,
 761   MOD_0F01_REG_5,
 762   MOD_0F01_REG_7,
 763   MOD_0F12_PREFIX_0,
 764   MOD_0F13,
 765   MOD_0F16_PREFIX_0,
 766   MOD_0F17,
 767   MOD_0F18_REG_0,
 768   MOD_0F18_REG_1,
 769   MOD_0F18_REG_2,
 770   MOD_0F18_REG_3,
 771   MOD_0F18_REG_4,
 772   MOD_0F18_REG_5,
 773   MOD_0F18_REG_6,
 774   MOD_0F18_REG_7,
 775   MOD_0F1A_PREFIX_0,
 776   MOD_0F1B_PREFIX_0,
 777   MOD_0F1B_PREFIX_1,
 778   MOD_0F24,
 779   MOD_0F26,
 780   MOD_0F2B_PREFIX_0,
 781   MOD_0F2B_PREFIX_1,
 782   MOD_0F2B_PREFIX_2,
 783   MOD_0F2B_PREFIX_3,
 784   MOD_0F51,
 785   MOD_0F71_REG_2,
 786   MOD_0F71_REG_4,
 787   MOD_0F71_REG_6,
 788   MOD_0F72_REG_2,
 789   MOD_0F72_REG_4,
 790   MOD_0F72_REG_6,
 791   MOD_0F73_REG_2,
 792   MOD_0F73_REG_3,
 793   MOD_0F73_REG_6,
 794   MOD_0F73_REG_7,
 795   MOD_0FAE_REG_0,
 796   MOD_0FAE_REG_1,
 797   MOD_0FAE_REG_2,
 798   MOD_0FAE_REG_3,
 799   MOD_0FAE_REG_4,
 800   MOD_0FAE_REG_5,
 801   MOD_0FAE_REG_6,
 802   MOD_0FAE_REG_7,
 803   MOD_0FB2,
 804   MOD_0FB4,
 805   MOD_0FB5,
 806   MOD_0FC3,
 807   MOD_0FC7_REG_3,
 808   MOD_0FC7_REG_4,
 809   MOD_0FC7_REG_5,
 810   MOD_0FC7_REG_6,
 811   MOD_0FC7_REG_7,
 812   MOD_0FD7,
 813   MOD_0FE7_PREFIX_2,
 814   MOD_0FF0_PREFIX_3,
 815   MOD_0F382A_PREFIX_2,
 816   MOD_62_32BIT,
 817   MOD_C4_32BIT,
 818   MOD_C5_32BIT,
 819   MOD_VEX_0F12_PREFIX_0,
 820   MOD_VEX_0F13,
 821   MOD_VEX_0F16_PREFIX_0,
 822   MOD_VEX_0F17,
 823   MOD_VEX_0F2B,
 824   MOD_VEX_W_0_0F41_P_0_LEN_1,
 825   MOD_VEX_W_1_0F41_P_0_LEN_1,
 826   MOD_VEX_W_0_0F41_P_2_LEN_1,
 827   MOD_VEX_W_1_0F41_P_2_LEN_1,
 828   MOD_VEX_W_0_0F42_P_0_LEN_1,
 829   MOD_VEX_W_1_0F42_P_0_LEN_1,
 830   MOD_VEX_W_0_0F42_P_2_LEN_1,
 831   MOD_VEX_W_1_0F42_P_2_LEN_1,
 832   MOD_VEX_W_0_0F44_P_0_LEN_1,
 833   MOD_VEX_W_1_0F44_P_0_LEN_1,
 834   MOD_VEX_W_0_0F44_P_2_LEN_1,
 835   MOD_VEX_W_1_0F44_P_2_LEN_1,
 836   MOD_VEX_W_0_0F45_P_0_LEN_1,
 837   MOD_VEX_W_1_0F45_P_0_LEN_1,
 838   MOD_VEX_W_0_0F45_P_2_LEN_1,
 839   MOD_VEX_W_1_0F45_P_2_LEN_1,
 840   MOD_VEX_W_0_0F46_P_0_LEN_1,
 841   MOD_VEX_W_1_0F46_P_0_LEN_1,
 842   MOD_VEX_W_0_0F46_P_2_LEN_1,
 843   MOD_VEX_W_1_0F46_P_2_LEN_1,
 844   MOD_VEX_W_0_0F47_P_0_LEN_1,
 845   MOD_VEX_W_1_0F47_P_0_LEN_1,
 846   MOD_VEX_W_0_0F47_P_2_LEN_1,
 847   MOD_VEX_W_1_0F47_P_2_LEN_1,
 848   MOD_VEX_W_0_0F4A_P_0_LEN_1,
 849   MOD_VEX_W_1_0F4A_P_0_LEN_1,
 850   MOD_VEX_W_0_0F4A_P_2_LEN_1,
 851   MOD_VEX_W_1_0F4A_P_2_LEN_1,
 852   MOD_VEX_W_0_0F4B_P_0_LEN_1,
 853   MOD_VEX_W_1_0F4B_P_0_LEN_1,
 854   MOD_VEX_W_0_0F4B_P_2_LEN_1,
 855   MOD_VEX_0F50,
 856   MOD_VEX_0F71_REG_2,
 857   MOD_VEX_0F71_REG_4,
 858   MOD_VEX_0F71_REG_6,
 859   MOD_VEX_0F72_REG_2,
 860   MOD_VEX_0F72_REG_4,
 861   MOD_VEX_0F72_REG_6,
 862   MOD_VEX_0F73_REG_2,
 863   MOD_VEX_0F73_REG_3,
 864   MOD_VEX_0F73_REG_6,
 865   MOD_VEX_0F73_REG_7,
 866   MOD_VEX_W_0_0F91_P_0_LEN_0,
 867   MOD_VEX_W_1_0F91_P_0_LEN_0,
 868   MOD_VEX_W_0_0F91_P_2_LEN_0,
 869   MOD_VEX_W_1_0F91_P_2_LEN_0,
 870   MOD_VEX_W_0_0F92_P_0_LEN_0,
 871   MOD_VEX_W_0_0F92_P_2_LEN_0,
 872   MOD_VEX_W_0_0F92_P_3_LEN_0,
 873   MOD_VEX_W_1_0F92_P_3_LEN_0,
 874   MOD_VEX_W_0_0F93_P_0_LEN_0,
 875   MOD_VEX_W_0_0F93_P_2_LEN_0,
 876   MOD_VEX_W_0_0F93_P_3_LEN_0,
 877   MOD_VEX_W_1_0F93_P_3_LEN_0,
 878   MOD_VEX_W_0_0F98_P_0_LEN_0,
 879   MOD_VEX_W_1_0F98_P_0_LEN_0,
 880   MOD_VEX_W_0_0F98_P_2_LEN_0,
 881   MOD_VEX_W_1_0F98_P_2_LEN_0,
 882   MOD_VEX_W_0_0F99_P_0_LEN_0,
 883   MOD_VEX_W_1_0F99_P_0_LEN_0,
 884   MOD_VEX_W_0_0F99_P_2_LEN_0,
 885   MOD_VEX_W_1_0F99_P_2_LEN_0,
 886   MOD_VEX_0FAE_REG_2,
 887   MOD_VEX_0FAE_REG_3,
 888   MOD_VEX_0FD7_PREFIX_2,
 889   MOD_VEX_0FE7_PREFIX_2,
 890   MOD_VEX_0FF0_PREFIX_3,
 891   MOD_VEX_0F381A_PREFIX_2,
 892   MOD_VEX_0F382A_PREFIX_2,
 893   MOD_VEX_0F382C_PREFIX_2,
 894   MOD_VEX_0F382D_PREFIX_2,
 895   MOD_VEX_0F382E_PREFIX_2,
 896   MOD_VEX_0F382F_PREFIX_2,
 897   MOD_VEX_0F385A_PREFIX_2,
 898   MOD_VEX_0F388C_PREFIX_2,
 899   MOD_VEX_0F388E_PREFIX_2,
 900   MOD_VEX_W_0_0F3A30_P_2_LEN_0,
 901   MOD_VEX_W_1_0F3A30_P_2_LEN_0,
 902   MOD_VEX_W_0_0F3A31_P_2_LEN_0,
 903   MOD_VEX_W_1_0F3A31_P_2_LEN_0,
 904   MOD_VEX_W_0_0F3A32_P_2_LEN_0,
 905   MOD_VEX_W_1_0F3A32_P_2_LEN_0,
 906   MOD_VEX_W_0_0F3A33_P_2_LEN_0,
 907   MOD_VEX_W_1_0F3A33_P_2_LEN_0,
 908
 909   MOD_EVEX_0F10_PREFIX_1,
 910   MOD_EVEX_0F10_PREFIX_3,
 911   MOD_EVEX_0F11_PREFIX_1,
 912   MOD_EVEX_0F11_PREFIX_3,
 913   MOD_EVEX_0F12_PREFIX_0,
 914   MOD_EVEX_0F16_PREFIX_0,
 915   MOD_EVEX_0F38C6_REG_1,
 916   MOD_EVEX_0F38C6_REG_2,
 917   MOD_EVEX_0F38C6_REG_5,
 918   MOD_EVEX_0F38C6_REG_6,
 919   MOD_EVEX_0F38C7_REG_1,
 920   MOD_EVEX_0F38C7_REG_2,
 921   MOD_EVEX_0F38C7_REG_5,
 922   MOD_EVEX_0F38C7_REG_6
 923 };
 924
 925 enum
 926 {
 927   RM_C6_REG_7 = 0,
 928   RM_C7_REG_7,
 929   RM_0F01_REG_0,
 930   RM_0F01_REG_1,
 931   RM_0F01_REG_2,
 932   RM_0F01_REG_3,
 933   RM_0F01_REG_5,
 934   RM_0F01_REG_7,
 935   RM_0FAE_REG_5,
 936   RM_0FAE_REG_6,
 937   RM_0FAE_REG_7
 938 };
 939
 940 enum
 941 {
 942   PREFIX_90 = 0,
 943   PREFIX_0F10,
 944   PREFIX_0F11,
 945   PREFIX_0F12,
 946   PREFIX_0F16,
 947   PREFIX_0F1A,
 948   PREFIX_0F1B,
 949   PREFIX_0F2A,
 950   PREFIX_0F2B,
 951   PREFIX_0F2C,
 952   PREFIX_0F2D,
 953   PREFIX_0F2E,
 954   PREFIX_0F2F,
 955   PREFIX_0F51,
 956   PREFIX_0F52,
 957   PREFIX_0F53,
 958   PREFIX_0F58,
 959   PREFIX_0F59,
 960   PREFIX_0F5A,
 961   PREFIX_0F5B,
 962   PREFIX_0F5C,
 963   PREFIX_0F5D,
 964   PREFIX_0F5E,
 965   PREFIX_0F5F,
 966   PREFIX_0F60,
 967   PREFIX_0F61,
 968   PREFIX_0F62,
 969   PREFIX_0F6C,
 970   PREFIX_0F6D,
 971   PREFIX_0F6F,
 972   PREFIX_0F70,
 973   PREFIX_0F73_REG_3,
 974   PREFIX_0F73_REG_7,
 975   PREFIX_0F78,
 976   PREFIX_0F79,
 977   PREFIX_0F7C,
 978   PREFIX_0F7D,
 979   PREFIX_0F7E,
 980   PREFIX_0F7F,
 981   PREFIX_0FAE_REG_0,
 982   PREFIX_0FAE_REG_1,
 983   PREFIX_0FAE_REG_2,
 984   PREFIX_0FAE_REG_3,
 985   PREFIX_0FAE_REG_6,
 986   PREFIX_0FAE_REG_7,
 987   PREFIX_RM_0_0FAE_REG_7,
 988   PREFIX_0FB8,
 989   PREFIX_0FBC,
 990   PREFIX_0FBD,
 991   PREFIX_0FC2,
 992   PREFIX_MOD_0_0FC3,
 993   PREFIX_MOD_0_0FC7_REG_6,
 994   PREFIX_MOD_3_0FC7_REG_6,
 995   PREFIX_MOD_3_0FC7_REG_7,
 996   PREFIX_0FD0,
 997   PREFIX_0FD6,
 998   PREFIX_0FE6,
 999   PREFIX_0FE7,
1000   PREFIX_0FF0,
1001   PREFIX_0FF7,
1002   PREFIX_0F3810,
1003   PREFIX_0F3814,
1004   PREFIX_0F3815,
1005   PREFIX_0F3817,
1006   PREFIX_0F3820,
1007   PREFIX_0F3821,
1008   PREFIX_0F3822,
1009   PREFIX_0F3823,
1010   PREFIX_0F3824,
1011   PREFIX_0F3825,
1012   PREFIX_0F3828,
1013   PREFIX_0F3829,
1014   PREFIX_0F382A,
1015   PREFIX_0F382B,
1016   PREFIX_0F3830,
1017   PREFIX_0F3831,
1018   PREFIX_0F3832,
1019   PREFIX_0F3833,
1020   PREFIX_0F3834,
1021   PREFIX_0F3835,
1022   PREFIX_0F3837,
1023   PREFIX_0F3838,
1024   PREFIX_0F3839,
1025   PREFIX_0F383A,
1026   PREFIX_0F383B,
1027   PREFIX_0F383C,
1028   PREFIX_0F383D,
1029   PREFIX_0F383E,
1030   PREFIX_0F383F,
1031   PREFIX_0F3840,
1032   PREFIX_0F3841,
1033   PREFIX_0F3880,
1034   PREFIX_0F3881,
1035   PREFIX_0F3882,
1036   PREFIX_0F38C8,
1037   PREFIX_0F38C9,
1038   PREFIX_0F38CA,
1039   PREFIX_0F38CB,
1040   PREFIX_0F38CC,
1041   PREFIX_0F38CD,
1042   PREFIX_0F38DB,
1043   PREFIX_0F38DC,
1044   PREFIX_0F38DD,
1045   PREFIX_0F38DE,
1046   PREFIX_0F38DF,
1047   PREFIX_0F38F0,
1048   PREFIX_0F38F1,
1049   PREFIX_0F38F6,
1050   PREFIX_0F3A08,
1051   PREFIX_0F3A09,
1052   PREFIX_0F3A0A,
1053   PREFIX_0F3A0B,
1054   PREFIX_0F3A0C,
1055   PREFIX_0F3A0D,
1056   PREFIX_0F3A0E,
1057   PREFIX_0F3A14,
1058   PREFIX_0F3A15,
1059   PREFIX_0F3A16,
1060   PREFIX_0F3A17,
1061   PREFIX_0F3A20,
1062   PREFIX_0F3A21,
1063   PREFIX_0F3A22,
1064   PREFIX_0F3A40,
1065   PREFIX_0F3A41,
1066   PREFIX_0F3A42,
1067   PREFIX_0F3A44,
1068   PREFIX_0F3A60,
1069   PREFIX_0F3A61,
1070   PREFIX_0F3A62,
1071   PREFIX_0F3A63,
1072   PREFIX_0F3ACC,
1073   PREFIX_0F3ADF,
1074   PREFIX_VEX_0F10,
1075   PREFIX_VEX_0F11,
1076   PREFIX_VEX_0F12,
1077   PREFIX_VEX_0F16,
1078   PREFIX_VEX_0F2A,
1079   PREFIX_VEX_0F2C,
1080   PREFIX_VEX_0F2D,
1081   PREFIX_VEX_0F2E,
1082   PREFIX_VEX_0F2F,
1083   PREFIX_VEX_0F41,
1084   PREFIX_VEX_0F42,
1085   PREFIX_VEX_0F44,
1086   PREFIX_VEX_0F45,
1087   PREFIX_VEX_0F46,
1088   PREFIX_VEX_0F47,
1089   PREFIX_VEX_0F4A,
1090   PREFIX_VEX_0F4B,
1091   PREFIX_VEX_0F51,
1092   PREFIX_VEX_0F52,
1093   PREFIX_VEX_0F53,
1094   PREFIX_VEX_0F58,
1095   PREFIX_VEX_0F59,
1096   PREFIX_VEX_0F5A,
1097   PREFIX_VEX_0F5B,
1098   PREFIX_VEX_0F5C,
1099   PREFIX_VEX_0F5D,
1100   PREFIX_VEX_0F5E,
1101   PREFIX_VEX_0F5F,
1102   PREFIX_VEX_0F60,
1103   PREFIX_VEX_0F61,
1104   PREFIX_VEX_0F62,
1105   PREFIX_VEX_0F63,
1106   PREFIX_VEX_0F64,
1107   PREFIX_VEX_0F65,
1108   PREFIX_VEX_0F66,
1109   PREFIX_VEX_0F67,
1110   PREFIX_VEX_0F68,
1111   PREFIX_VEX_0F69,
1112   PREFIX_VEX_0F6A,
1113   PREFIX_VEX_0F6B,
1114   PREFIX_VEX_0F6C,
1115   PREFIX_VEX_0F6D,
1116   PREFIX_VEX_0F6E,
1117   PREFIX_VEX_0F6F,
1118   PREFIX_VEX_0F70,
1119   PREFIX_VEX_0F71_REG_2,
1120   PREFIX_VEX_0F71_REG_4,
1121   PREFIX_VEX_0F71_REG_6,
1122   PREFIX_VEX_0F72_REG_2,
1123   PREFIX_VEX_0F72_REG_4,
1124   PREFIX_VEX_0F72_REG_6,
1125   PREFIX_VEX_0F73_REG_2,
1126   PREFIX_VEX_0F73_REG_3,
1127   PREFIX_VEX_0F73_REG_6,
1128   PREFIX_VEX_0F73_REG_7,
1129   PREFIX_VEX_0F74,
1130   PREFIX_VEX_0F75,
1131   PREFIX_VEX_0F76,
1132   PREFIX_VEX_0F77,
1133   PREFIX_VEX_0F7C,
1134   PREFIX_VEX_0F7D,
1135   PREFIX_VEX_0F7E,
1136   PREFIX_VEX_0F7F,
1137   PREFIX_VEX_0F90,
1138   PREFIX_VEX_0F91,
1139   PREFIX_VEX_0F92,
1140   PREFIX_VEX_0F93,
1141   PREFIX_VEX_0F98,
1142   PREFIX_VEX_0F99,
1143   PREFIX_VEX_0FC2,
1144   PREFIX_VEX_0FC4,
1145   PREFIX_VEX_0FC5,
1146   PREFIX_VEX_0FD0,
1147   PREFIX_VEX_0FD1,
1148   PREFIX_VEX_0FD2,
1149   PREFIX_VEX_0FD3,
1150   PREFIX_VEX_0FD4,
1151   PREFIX_VEX_0FD5,
1152   PREFIX_VEX_0FD6,
1153   PREFIX_VEX_0FD7,
1154   PREFIX_VEX_0FD8,
1155   PREFIX_VEX_0FD9,
1156   PREFIX_VEX_0FDA,
1157   PREFIX_VEX_0FDB,
1158   PREFIX_VEX_0FDC,
1159   PREFIX_VEX_0FDD,
1160   PREFIX_VEX_0FDE,
1161   PREFIX_VEX_0FDF,
1162   PREFIX_VEX_0FE0,
1163   PREFIX_VEX_0FE1,
1164   PREFIX_VEX_0FE2,
1165   PREFIX_VEX_0FE3,
1166   PREFIX_VEX_0FE4,
1167   PREFIX_VEX_0FE5,
1168   PREFIX_VEX_0FE6,
1169   PREFIX_VEX_0FE7,
1170   PREFIX_VEX_0FE8,
1171   PREFIX_VEX_0FE9,
1172   PREFIX_VEX_0FEA,
1173   PREFIX_VEX_0FEB,
1174   PREFIX_VEX_0FEC,
1175   PREFIX_VEX_0FED,
1176   PREFIX_VEX_0FEE,
1177   PREFIX_VEX_0FEF,
1178   PREFIX_VEX_0FF0,
1179   PREFIX_VEX_0FF1,
1180   PREFIX_VEX_0FF2,
1181   PREFIX_VEX_0FF3,
1182   PREFIX_VEX_0FF4,
1183   PREFIX_VEX_0FF5,
1184   PREFIX_VEX_0FF6,
1185   PREFIX_VEX_0FF7,
1186   PREFIX_VEX_0FF8,
1187   PREFIX_VEX_0FF9,
1188   PREFIX_VEX_0FFA,
1189   PREFIX_VEX_0FFB,
1190   PREFIX_VEX_0FFC,
1191   PREFIX_VEX_0FFD,
1192   PREFIX_VEX_0FFE,
1193   PREFIX_VEX_0F3800,
1194   PREFIX_VEX_0F3801,
1195   PREFIX_VEX_0F3802,
1196   PREFIX_VEX_0F3803,
1197   PREFIX_VEX_0F3804,
1198   PREFIX_VEX_0F3805,
1199   PREFIX_VEX_0F3806,
1200   PREFIX_VEX_0F3807,
1201   PREFIX_VEX_0F3808,
1202   PREFIX_VEX_0F3809,
1203   PREFIX_VEX_0F380A,
1204   PREFIX_VEX_0F380B,
1205   PREFIX_VEX_0F380C,
1206   PREFIX_VEX_0F380D,
1207   PREFIX_VEX_0F380E,
1208   PREFIX_VEX_0F380F,
1209   PREFIX_VEX_0F3813,
1210   PREFIX_VEX_0F3816,
1211   PREFIX_VEX_0F3817,
1212   PREFIX_VEX_0F3818,
1213   PREFIX_VEX_0F3819,
1214   PREFIX_VEX_0F381A,
1215   PREFIX_VEX_0F381C,
1216   PREFIX_VEX_0F381D,
1217   PREFIX_VEX_0F381E,
1218   PREFIX_VEX_0F3820,
1219   PREFIX_VEX_0F3821,
1220   PREFIX_VEX_0F3822,
1221   PREFIX_VEX_0F3823,
1222   PREFIX_VEX_0F3824,
1223   PREFIX_VEX_0F3825,
1224   PREFIX_VEX_0F3828,
1225   PREFIX_VEX_0F3829,
1226   PREFIX_VEX_0F382A,
1227   PREFIX_VEX_0F382B,
1228   PREFIX_VEX_0F382C,
1229   PREFIX_VEX_0F382D,
1230   PREFIX_VEX_0F382E,
1231   PREFIX_VEX_0F382F,
1232   PREFIX_VEX_0F3830,
1233   PREFIX_VEX_0F3831,
1234   PREFIX_VEX_0F3832,
1235   PREFIX_VEX_0F3833,
1236   PREFIX_VEX_0F3834,
1237   PREFIX_VEX_0F3835,
1238   PREFIX_VEX_0F3836,
1239   PREFIX_VEX_0F3837,
1240   PREFIX_VEX_0F3838,
1241   PREFIX_VEX_0F3839,
1242   PREFIX_VEX_0F383A,
1243   PREFIX_VEX_0F383B,
1244   PREFIX_VEX_0F383C,
1245   PREFIX_VEX_0F383D,
1246   PREFIX_VEX_0F383E,
1247   PREFIX_VEX_0F383F,
1248   PREFIX_VEX_0F3840,
1249   PREFIX_VEX_0F3841,
1250   PREFIX_VEX_0F3845,
1251   PREFIX_VEX_0F3846,
1252   PREFIX_VEX_0F3847,
1253   PREFIX_VEX_0F3858,
1254   PREFIX_VEX_0F3859,
1255   PREFIX_VEX_0F385A,
1256   PREFIX_VEX_0F3878,
1257   PREFIX_VEX_0F3879,
1258   PREFIX_VEX_0F388C,
1259   PREFIX_VEX_0F388E,
1260   PREFIX_VEX_0F3890,
1261   PREFIX_VEX_0F3891,
1262   PREFIX_VEX_0F3892,
1263   PREFIX_VEX_0F3893,
1264   PREFIX_VEX_0F3896,
1265   PREFIX_VEX_0F3897,
1266   PREFIX_VEX_0F3898,
1267   PREFIX_VEX_0F3899,
1268   PREFIX_VEX_0F389A,
1269   PREFIX_VEX_0F389B,
1270   PREFIX_VEX_0F389C,
1271   PREFIX_VEX_0F389D,
1272   PREFIX_VEX_0F389E,
1273   PREFIX_VEX_0F389F,
1274   PREFIX_VEX_0F38A6,
1275   PREFIX_VEX_0F38A7,
1276   PREFIX_VEX_0F38A8,
1277   PREFIX_VEX_0F38A9,
1278   PREFIX_VEX_0F38AA,
1279   PREFIX_VEX_0F38AB,
1280   PREFIX_VEX_0F38AC,
1281   PREFIX_VEX_0F38AD,
1282   PREFIX_VEX_0F38AE,
1283   PREFIX_VEX_0F38AF,
1284   PREFIX_VEX_0F38B6,
1285   PREFIX_VEX_0F38B7,
1286   PREFIX_VEX_0F38B8,
1287   PREFIX_VEX_0F38B9,
1288   PREFIX_VEX_0F38BA,
1289   PREFIX_VEX_0F38BB,
1290   PREFIX_VEX_0F38BC,
1291   PREFIX_VEX_0F38BD,
1292   PREFIX_VEX_0F38BE,
1293   PREFIX_VEX_0F38BF,
1294   PREFIX_VEX_0F38DB,
1295   PREFIX_VEX_0F38DC,
1296   PREFIX_VEX_0F38DD,
1297   PREFIX_VEX_0F38DE,
1298   PREFIX_VEX_0F38DF,
1299   PREFIX_VEX_0F38F2,
1300   PREFIX_VEX_0F38F3_REG_1,
1301   PREFIX_VEX_0F38F3_REG_2,
1302   PREFIX_VEX_0F38F3_REG_3,
1303   PREFIX_VEX_0F38F5,
1304   PREFIX_VEX_0F38F6,
1305   PREFIX_VEX_0F38F7,
1306   PREFIX_VEX_0F3A00,
1307   PREFIX_VEX_0F3A01,
1308   PREFIX_VEX_0F3A02,
1309   PREFIX_VEX_0F3A04,
1310   PREFIX_VEX_0F3A05,
1311   PREFIX_VEX_0F3A06,
1312   PREFIX_VEX_0F3A08,
1313   PREFIX_VEX_0F3A09,
1314   PREFIX_VEX_0F3A0A,
1315   PREFIX_VEX_0F3A0B,
1316   PREFIX_VEX_0F3A0C,
1317   PREFIX_VEX_0F3A0D,
1318   PREFIX_VEX_0F3A0E,
1319   PREFIX_VEX_0F3A0F,
1320   PREFIX_VEX_0F3A14,
1321   PREFIX_VEX_0F3A15,
1322   PREFIX_VEX_0F3A16,
1323   PREFIX_VEX_0F3A17,
1324   PREFIX_VEX_0F3A18,
1325   PREFIX_VEX_0F3A19,
1326   PREFIX_VEX_0F3A1D,
1327   PREFIX_VEX_0F3A20,
1328   PREFIX_VEX_0F3A21,
1329   PREFIX_VEX_0F3A22,
1330   PREFIX_VEX_0F3A30,
1331   PREFIX_VEX_0F3A31,
1332   PREFIX_VEX_0F3A32,
1333   PREFIX_VEX_0F3A33,
1334   PREFIX_VEX_0F3A38,
1335   PREFIX_VEX_0F3A39,
1336   PREFIX_VEX_0F3A40,
1337   PREFIX_VEX_0F3A41,
1338   PREFIX_VEX_0F3A42,
1339   PREFIX_VEX_0F3A44,
1340   PREFIX_VEX_0F3A46,
1341   PREFIX_VEX_0F3A48,
1342   PREFIX_VEX_0F3A49,
1343   PREFIX_VEX_0F3A4A,
1344   PREFIX_VEX_0F3A4B,
1345   PREFIX_VEX_0F3A4C,
1346   PREFIX_VEX_0F3A5C,
1347   PREFIX_VEX_0F3A5D,
1348   PREFIX_VEX_0F3A5E,
1349   PREFIX_VEX_0F3A5F,
1350   PREFIX_VEX_0F3A60,
1351   PREFIX_VEX_0F3A61,
1352   PREFIX_VEX_0F3A62,
1353   PREFIX_VEX_0F3A63,
1354   PREFIX_VEX_0F3A68,
1355   PREFIX_VEX_0F3A69,
1356   PREFIX_VEX_0F3A6A,
1357   PREFIX_VEX_0F3A6B,
1358   PREFIX_VEX_0F3A6C,
1359   PREFIX_VEX_0F3A6D,
1360   PREFIX_VEX_0F3A6E,
1361   PREFIX_VEX_0F3A6F,
1362   PREFIX_VEX_0F3A78,
1363   PREFIX_VEX_0F3A79,
1364   PREFIX_VEX_0F3A7A,
1365   PREFIX_VEX_0F3A7B,
1366   PREFIX_VEX_0F3A7C,
1367   PREFIX_VEX_0F3A7D,
1368   PREFIX_VEX_0F3A7E,
1369   PREFIX_VEX_0F3A7F,
1370   PREFIX_VEX_0F3ADF,
1371   PREFIX_VEX_0F3AF0,
1372
1373   PREFIX_EVEX_0F10,
1374   PREFIX_EVEX_0F11,
1375   PREFIX_EVEX_0F12,
1376   PREFIX_EVEX_0F13,
1377   PREFIX_EVEX_0F14,
1378   PREFIX_EVEX_0F15,
1379   PREFIX_EVEX_0F16,
1380   PREFIX_EVEX_0F17,
1381   PREFIX_EVEX_0F28,
1382   PREFIX_EVEX_0F29,
1383   PREFIX_EVEX_0F2A,
1384   PREFIX_EVEX_0F2B,
1385   PREFIX_EVEX_0F2C,
1386   PREFIX_EVEX_0F2D,
1387   PREFIX_EVEX_0F2E,
1388   PREFIX_EVEX_0F2F,
1389   PREFIX_EVEX_0F51,
1390   PREFIX_EVEX_0F54,
1391   PREFIX_EVEX_0F55,
1392   PREFIX_EVEX_0F56,
1393   PREFIX_EVEX_0F57,
1394   PREFIX_EVEX_0F58,
1395   PREFIX_EVEX_0F59,
1396   PREFIX_EVEX_0F5A,
1397   PREFIX_EVEX_0F5B,
1398   PREFIX_EVEX_0F5C,
1399   PREFIX_EVEX_0F5D,
1400   PREFIX_EVEX_0F5E,
1401   PREFIX_EVEX_0F5F,
1402   PREFIX_EVEX_0F60,
1403   PREFIX_EVEX_0F61,
1404   PREFIX_EVEX_0F62,
1405   PREFIX_EVEX_0F63,
1406   PREFIX_EVEX_0F64,
1407   PREFIX_EVEX_0F65,
1408   PREFIX_EVEX_0F66,
1409   PREFIX_EVEX_0F67,
1410   PREFIX_EVEX_0F68,
1411   PREFIX_EVEX_0F69,
1412   PREFIX_EVEX_0F6A,
1413   PREFIX_EVEX_0F6B,
1414   PREFIX_EVEX_0F6C,
1415   PREFIX_EVEX_0F6D,
1416   PREFIX_EVEX_0F6E,
1417   PREFIX_EVEX_0F6F,
1418   PREFIX_EVEX_0F70,
1419   PREFIX_EVEX_0F71_REG_2,
1420   PREFIX_EVEX_0F71_REG_4,
1421   PREFIX_EVEX_0F71_REG_6,
1422   PREFIX_EVEX_0F72_REG_0,
1423   PREFIX_EVEX_0F72_REG_1,
1424   PREFIX_EVEX_0F72_REG_2,
1425   PREFIX_EVEX_0F72_REG_4,
1426   PREFIX_EVEX_0F72_REG_6,
1427   PREFIX_EVEX_0F73_REG_2,
1428   PREFIX_EVEX_0F73_REG_3,
1429   PREFIX_EVEX_0F73_REG_6,
1430   PREFIX_EVEX_0F73_REG_7,
1431   PREFIX_EVEX_0F74,
1432   PREFIX_EVEX_0F75,
1433   PREFIX_EVEX_0F76,
1434   PREFIX_EVEX_0F78,
1435   PREFIX_EVEX_0F79,
1436   PREFIX_EVEX_0F7A,
1437   PREFIX_EVEX_0F7B,
1438   PREFIX_EVEX_0F7E,
1439   PREFIX_EVEX_0F7F,
1440   PREFIX_EVEX_0FC2,
1441   PREFIX_EVEX_0FC4,
1442   PREFIX_EVEX_0FC5,
1443   PREFIX_EVEX_0FC6,
1444   PREFIX_EVEX_0FD1,
1445   PREFIX_EVEX_0FD2,
1446   PREFIX_EVEX_0FD3,
1447   PREFIX_EVEX_0FD4,
1448   PREFIX_EVEX_0FD5,
1449   PREFIX_EVEX_0FD6,
1450   PREFIX_EVEX_0FD8,
1451   PREFIX_EVEX_0FD9,
1452   PREFIX_EVEX_0FDA,
1453   PREFIX_EVEX_0FDB,
1454   PREFIX_EVEX_0FDC,
1455   PREFIX_EVEX_0FDD,
1456   PREFIX_EVEX_0FDE,
1457   PREFIX_EVEX_0FDF,
1458   PREFIX_EVEX_0FE0,
1459   PREFIX_EVEX_0FE1,
1460   PREFIX_EVEX_0FE2,
1461   PREFIX_EVEX_0FE3,
1462   PREFIX_EVEX_0FE4,
1463   PREFIX_EVEX_0FE5,
1464   PREFIX_EVEX_0FE6,
1465   PREFIX_EVEX_0FE7,
1466   PREFIX_EVEX_0FE8,
1467   PREFIX_EVEX_0FE9,
1468   PREFIX_EVEX_0FEA,
1469   PREFIX_EVEX_0FEB,
1470   PREFIX_EVEX_0FEC,
1471   PREFIX_EVEX_0FED,
1472   PREFIX_EVEX_0FEE,
1473   PREFIX_EVEX_0FEF,
1474   PREFIX_EVEX_0FF1,
1475   PREFIX_EVEX_0FF2,
1476   PREFIX_EVEX_0FF3,
1477   PREFIX_EVEX_0FF4,
1478   PREFIX_EVEX_0FF5,
1479   PREFIX_EVEX_0FF6,
1480   PREFIX_EVEX_0FF8,
1481   PREFIX_EVEX_0FF9,
1482   PREFIX_EVEX_0FFA,
1483   PREFIX_EVEX_0FFB,
1484   PREFIX_EVEX_0FFC,
1485   PREFIX_EVEX_0FFD,
1486   PREFIX_EVEX_0FFE,
1487   PREFIX_EVEX_0F3800,
1488   PREFIX_EVEX_0F3804,
1489   PREFIX_EVEX_0F380B,
1490   PREFIX_EVEX_0F380C,
1491   PREFIX_EVEX_0F380D,
1492   PREFIX_EVEX_0F3810,
1493   PREFIX_EVEX_0F3811,
1494   PREFIX_EVEX_0F3812,
1495   PREFIX_EVEX_0F3813,
1496   PREFIX_EVEX_0F3814,
1497   PREFIX_EVEX_0F3815,
1498   PREFIX_EVEX_0F3816,
1499   PREFIX_EVEX_0F3818,
1500   PREFIX_EVEX_0F3819,
1501   PREFIX_EVEX_0F381A,
1502   PREFIX_EVEX_0F381B,
1503   PREFIX_EVEX_0F381C,
1504   PREFIX_EVEX_0F381D,
1505   PREFIX_EVEX_0F381E,
1506   PREFIX_EVEX_0F381F,
1507   PREFIX_EVEX_0F3820,
1508   PREFIX_EVEX_0F3821,
1509   PREFIX_EVEX_0F3822,
1510   PREFIX_EVEX_0F3823,
1511   PREFIX_EVEX_0F3824,
1512   PREFIX_EVEX_0F3825,
1513   PREFIX_EVEX_0F3826,
1514   PREFIX_EVEX_0F3827,
1515   PREFIX_EVEX_0F3828,
1516   PREFIX_EVEX_0F3829,
1517   PREFIX_EVEX_0F382A,
1518   PREFIX_EVEX_0F382B,
1519   PREFIX_EVEX_0F382C,
1520   PREFIX_EVEX_0F382D,
1521   PREFIX_EVEX_0F3830,
1522   PREFIX_EVEX_0F3831,
1523   PREFIX_EVEX_0F3832,
1524   PREFIX_EVEX_0F3833,
1525   PREFIX_EVEX_0F3834,
1526   PREFIX_EVEX_0F3835,
1527   PREFIX_EVEX_0F3836,
1528   PREFIX_EVEX_0F3837,
1529   PREFIX_EVEX_0F3838,
1530   PREFIX_EVEX_0F3839,
1531   PREFIX_EVEX_0F383A,
1532   PREFIX_EVEX_0F383B,
1533   PREFIX_EVEX_0F383C,
1534   PREFIX_EVEX_0F383D,
1535   PREFIX_EVEX_0F383E,
1536   PREFIX_EVEX_0F383F,
1537   PREFIX_EVEX_0F3840,
1538   PREFIX_EVEX_0F3842,
1539   PREFIX_EVEX_0F3843,
1540   PREFIX_EVEX_0F3844,
1541   PREFIX_EVEX_0F3845,
1542   PREFIX_EVEX_0F3846,
1543   PREFIX_EVEX_0F3847,
1544   PREFIX_EVEX_0F384C,
1545   PREFIX_EVEX_0F384D,
1546   PREFIX_EVEX_0F384E,
1547   PREFIX_EVEX_0F384F,
1548   PREFIX_EVEX_0F3858,
1549   PREFIX_EVEX_0F3859,
1550   PREFIX_EVEX_0F385A,
1551   PREFIX_EVEX_0F385B,
1552   PREFIX_EVEX_0F3864,
1553   PREFIX_EVEX_0F3865,
1554   PREFIX_EVEX_0F3866,
1555   PREFIX_EVEX_0F3875,
1556   PREFIX_EVEX_0F3876,
1557   PREFIX_EVEX_0F3877,
1558   PREFIX_EVEX_0F3878,
1559   PREFIX_EVEX_0F3879,
1560   PREFIX_EVEX_0F387A,
1561   PREFIX_EVEX_0F387B,
1562   PREFIX_EVEX_0F387C,
1563   PREFIX_EVEX_0F387D,
1564   PREFIX_EVEX_0F387E,
1565   PREFIX_EVEX_0F387F,
1566   PREFIX_EVEX_0F3883,
1567   PREFIX_EVEX_0F3888,
1568   PREFIX_EVEX_0F3889,
1569   PREFIX_EVEX_0F388A,
1570   PREFIX_EVEX_0F388B,
1571   PREFIX_EVEX_0F388D,
1572   PREFIX_EVEX_0F3890,
1573   PREFIX_EVEX_0F3891,
1574   PREFIX_EVEX_0F3892,
1575   PREFIX_EVEX_0F3893,
1576   PREFIX_EVEX_0F3896,
1577   PREFIX_EVEX_0F3897,
1578   PREFIX_EVEX_0F3898,
1579   PREFIX_EVEX_0F3899,
1580   PREFIX_EVEX_0F389A,
1581   PREFIX_EVEX_0F389B,
1582   PREFIX_EVEX_0F389C,
1583   PREFIX_EVEX_0F389D,
1584   PREFIX_EVEX_0F389E,
1585   PREFIX_EVEX_0F389F,
1586   PREFIX_EVEX_0F38A0,
1587   PREFIX_EVEX_0F38A1,
1588   PREFIX_EVEX_0F38A2,
1589   PREFIX_EVEX_0F38A3,
1590   PREFIX_EVEX_0F38A6,
1591   PREFIX_EVEX_0F38A7,
1592   PREFIX_EVEX_0F38A8,
1593   PREFIX_EVEX_0F38A9,
1594   PREFIX_EVEX_0F38AA,
1595   PREFIX_EVEX_0F38AB,
1596   PREFIX_EVEX_0F38AC,
1597   PREFIX_EVEX_0F38AD,
1598   PREFIX_EVEX_0F38AE,
1599   PREFIX_EVEX_0F38AF,
1600   PREFIX_EVEX_0F38B4,
1601   PREFIX_EVEX_0F38B5,
1602   PREFIX_EVEX_0F38B6,
1603   PREFIX_EVEX_0F38B7,
1604   PREFIX_EVEX_0F38B8,
1605   PREFIX_EVEX_0F38B9,
1606   PREFIX_EVEX_0F38BA,
1607   PREFIX_EVEX_0F38BB,
1608   PREFIX_EVEX_0F38BC,
1609   PREFIX_EVEX_0F38BD,
1610   PREFIX_EVEX_0F38BE,
1611   PREFIX_EVEX_0F38BF,
1612   PREFIX_EVEX_0F38C4,
1613   PREFIX_EVEX_0F38C6_REG_1,
1614   PREFIX_EVEX_0F38C6_REG_2,
1615   PREFIX_EVEX_0F38C6_REG_5,
1616   PREFIX_EVEX_0F38C6_REG_6,
1617   PREFIX_EVEX_0F38C7_REG_1,
1618   PREFIX_EVEX_0F38C7_REG_2,
1619   PREFIX_EVEX_0F38C7_REG_5,
1620   PREFIX_EVEX_0F38C7_REG_6,
1621   PREFIX_EVEX_0F38C8,
1622   PREFIX_EVEX_0F38CA,
1623   PREFIX_EVEX_0F38CB,
1624   PREFIX_EVEX_0F38CC,
1625   PREFIX_EVEX_0F38CD,
1626
1627   PREFIX_EVEX_0F3A00,
1628   PREFIX_EVEX_0F3A01,
1629   PREFIX_EVEX_0F3A03,
1630   PREFIX_EVEX_0F3A04,
1631   PREFIX_EVEX_0F3A05,
1632   PREFIX_EVEX_0F3A08,
1633   PREFIX_EVEX_0F3A09,
1634   PREFIX_EVEX_0F3A0A,
1635   PREFIX_EVEX_0F3A0B,
1636   PREFIX_EVEX_0F3A0F,
1637   PREFIX_EVEX_0F3A14,
1638   PREFIX_EVEX_0F3A15,
1639   PREFIX_EVEX_0F3A16,
1640   PREFIX_EVEX_0F3A17,
1641   PREFIX_EVEX_0F3A18,
1642   PREFIX_EVEX_0F3A19,
1643   PREFIX_EVEX_0F3A1A,
1644   PREFIX_EVEX_0F3A1B,
1645   PREFIX_EVEX_0F3A1D,
1646   PREFIX_EVEX_0F3A1E,
1647   PREFIX_EVEX_0F3A1F,
1648   PREFIX_EVEX_0F3A20,
1649   PREFIX_EVEX_0F3A21,
1650   PREFIX_EVEX_0F3A22,
1651   PREFIX_EVEX_0F3A23,
1652   PREFIX_EVEX_0F3A25,
1653   PREFIX_EVEX_0F3A26,
1654   PREFIX_EVEX_0F3A27,
1655   PREFIX_EVEX_0F3A38,
1656   PREFIX_EVEX_0F3A39,
1657   PREFIX_EVEX_0F3A3A,
1658   PREFIX_EVEX_0F3A3B,
1659   PREFIX_EVEX_0F3A3E,
1660   PREFIX_EVEX_0F3A3F,
1661   PREFIX_EVEX_0F3A42,
1662   PREFIX_EVEX_0F3A43,
1663   PREFIX_EVEX_0F3A50,
1664   PREFIX_EVEX_0F3A51,
1665   PREFIX_EVEX_0F3A54,
1666   PREFIX_EVEX_0F3A55,
1667   PREFIX_EVEX_0F3A56,
1668   PREFIX_EVEX_0F3A57,
1669   PREFIX_EVEX_0F3A66,
1670   PREFIX_EVEX_0F3A67
1671 };
1672
1673 enum
1674 {
1675   X86_64_06 = 0,
1676   X86_64_07,
1677   X86_64_0D,
1678   X86_64_16,
1679   X86_64_17,
1680   X86_64_1E,
1681   X86_64_1F,
1682   X86_64_27,
1683   X86_64_2F,
1684   X86_64_37,
1685   X86_64_3F,
1686   X86_64_60,
1687   X86_64_61,
1688   X86_64_62,
1689   X86_64_63,
1690   X86_64_6D,
1691   X86_64_6F,
1692   X86_64_9A,
1693   X86_64_C4,
1694   X86_64_C5,
1695   X86_64_CE,
1696   X86_64_D4,
1697   X86_64_D5,
1698   X86_64_E8,
1699   X86_64_E9,
1700   X86_64_EA,
1701   X86_64_0F01_REG_0,
1702   X86_64_0F01_REG_1,
1703   X86_64_0F01_REG_2,
1704   X86_64_0F01_REG_3
1705 };
1706
1707 enum
1708 {
1709   THREE_BYTE_0F38 = 0,
1710   THREE_BYTE_0F3A,
1711   THREE_BYTE_0F7A
1712 };
1713
1714 enum
1715 {
1716   XOP_08 = 0,
1717   XOP_09,
1718   XOP_0A
1719 };
1720
1721 enum
1722 {
1723   VEX_0F = 0,
1724   VEX_0F38,
1725   VEX_0F3A
1726 };
1727
1728 enum
1729 {
1730   EVEX_0F = 0,
1731   EVEX_0F38,
1732   EVEX_0F3A
1733 };
1734
1735 enum
1736 {
1737   VEX_LEN_0F10_P_1 = 0,
1738   VEX_LEN_0F10_P_3,
1739   VEX_LEN_0F11_P_1,
1740   VEX_LEN_0F11_P_3,
1741   VEX_LEN_0F12_P_0_M_0,
1742   VEX_LEN_0F12_P_0_M_1,
1743   VEX_LEN_0F12_P_2,
1744   VEX_LEN_0F13_M_0,
1745   VEX_LEN_0F16_P_0_M_0,
1746   VEX_LEN_0F16_P_0_M_1,
1747   VEX_LEN_0F16_P_2,
1748   VEX_LEN_0F17_M_0,
1749   VEX_LEN_0F2A_P_1,
1750   VEX_LEN_0F2A_P_3,
1751   VEX_LEN_0F2C_P_1,
1752   VEX_LEN_0F2C_P_3,
1753   VEX_LEN_0F2D_P_1,
1754   VEX_LEN_0F2D_P_3,
1755   VEX_LEN_0F2E_P_0,
1756   VEX_LEN_0F2E_P_2,
1757   VEX_LEN_0F2F_P_0,
1758   VEX_LEN_0F2F_P_2,
1759   VEX_LEN_0F41_P_0,
1760   VEX_LEN_0F41_P_2,
1761   VEX_LEN_0F42_P_0,
1762   VEX_LEN_0F42_P_2,
1763   VEX_LEN_0F44_P_0,
1764   VEX_LEN_0F44_P_2,
1765   VEX_LEN_0F45_P_0,
1766   VEX_LEN_0F45_P_2,
1767   VEX_LEN_0F46_P_0,
1768   VEX_LEN_0F46_P_2,
1769   VEX_LEN_0F47_P_0,
1770   VEX_LEN_0F47_P_2,
1771   VEX_LEN_0F4A_P_0,
1772   VEX_LEN_0F4A_P_2,
1773   VEX_LEN_0F4B_P_0,
1774   VEX_LEN_0F4B_P_2,
1775   VEX_LEN_0F51_P_1,
1776   VEX_LEN_0F51_P_3,
1777   VEX_LEN_0F52_P_1,
1778   VEX_LEN_0F53_P_1,
1779   VEX_LEN_0F58_P_1,
1780   VEX_LEN_0F58_P_3,
1781   VEX_LEN_0F59_P_1,
1782   VEX_LEN_0F59_P_3,
1783   VEX_LEN_0F5A_P_1,
1784   VEX_LEN_0F5A_P_3,
1785   VEX_LEN_0F5C_P_1,
1786   VEX_LEN_0F5C_P_3,
1787   VEX_LEN_0F5D_P_1,
1788   VEX_LEN_0F5D_P_3,
1789   VEX_LEN_0F5E_P_1,
1790   VEX_LEN_0F5E_P_3,
1791   VEX_LEN_0F5F_P_1,
1792   VEX_LEN_0F5F_P_3,
1793   VEX_LEN_0F6E_P_2,
1794   VEX_LEN_0F7E_P_1,
1795   VEX_LEN_0F7E_P_2,
1796   VEX_LEN_0F90_P_0,
1797   VEX_LEN_0F90_P_2,
1798   VEX_LEN_0F91_P_0,
1799   VEX_LEN_0F91_P_2,
1800   VEX_LEN_0F92_P_0,
1801   VEX_LEN_0F92_P_2,
1802   VEX_LEN_0F92_P_3,
1803   VEX_LEN_0F93_P_0,
1804   VEX_LEN_0F93_P_2,
1805   VEX_LEN_0F93_P_3,
1806   VEX_LEN_0F98_P_0,
1807   VEX_LEN_0F98_P_2,
1808   VEX_LEN_0F99_P_0,
1809   VEX_LEN_0F99_P_2,
1810   VEX_LEN_0FAE_R_2_M_0,
1811   VEX_LEN_0FAE_R_3_M_0,
1812   VEX_LEN_0FC2_P_1,
1813   VEX_LEN_0FC2_P_3,
1814   VEX_LEN_0FC4_P_2,
1815   VEX_LEN_0FC5_P_2,
1816   VEX_LEN_0FD6_P_2,
1817   VEX_LEN_0FF7_P_2,
1818   VEX_LEN_0F3816_P_2,
1819   VEX_LEN_0F3819_P_2,
1820   VEX_LEN_0F381A_P_2_M_0,
1821   VEX_LEN_0F3836_P_2,
1822   VEX_LEN_0F3841_P_2,
1823   VEX_LEN_0F385A_P_2_M_0,
1824   VEX_LEN_0F38DB_P_2,
1825   VEX_LEN_0F38DC_P_2,
1826   VEX_LEN_0F38DD_P_2,
1827   VEX_LEN_0F38DE_P_2,
1828   VEX_LEN_0F38DF_P_2,
1829   VEX_LEN_0F38F2_P_0,
1830   VEX_LEN_0F38F3_R_1_P_0,
1831   VEX_LEN_0F38F3_R_2_P_0,
1832   VEX_LEN_0F38F3_R_3_P_0,
1833   VEX_LEN_0F38F5_P_0,
1834   VEX_LEN_0F38F5_P_1,
1835   VEX_LEN_0F38F5_P_3,
1836   VEX_LEN_0F38F6_P_3,
1837   VEX_LEN_0F38F7_P_0,
1838   VEX_LEN_0F38F7_P_1,
1839   VEX_LEN_0F38F7_P_2,
1840   VEX_LEN_0F38F7_P_3,
1841   VEX_LEN_0F3A00_P_2,
1842   VEX_LEN_0F3A01_P_2,
1843   VEX_LEN_0F3A06_P_2,
1844   VEX_LEN_0F3A0A_P_2,
1845   VEX_LEN_0F3A0B_P_2,
1846   VEX_LEN_0F3A14_P_2,
1847   VEX_LEN_0F3A15_P_2,
1848   VEX_LEN_0F3A16_P_2,
1849   VEX_LEN_0F3A17_P_2,
1850   VEX_LEN_0F3A18_P_2,
1851   VEX_LEN_0F3A19_P_2,
1852   VEX_LEN_0F3A20_P_2,
1853   VEX_LEN_0F3A21_P_2,
1854   VEX_LEN_0F3A22_P_2,
1855   VEX_LEN_0F3A30_P_2,
1856   VEX_LEN_0F3A31_P_2,
1857   VEX_LEN_0F3A32_P_2,
1858   VEX_LEN_0F3A33_P_2,
1859   VEX_LEN_0F3A38_P_2,
1860   VEX_LEN_0F3A39_P_2,
1861   VEX_LEN_0F3A41_P_2,
1862   VEX_LEN_0F3A44_P_2,
1863   VEX_LEN_0F3A46_P_2,
1864   VEX_LEN_0F3A60_P_2,
1865   VEX_LEN_0F3A61_P_2,
1866   VEX_LEN_0F3A62_P_2,
1867   VEX_LEN_0F3A63_P_2,
1868   VEX_LEN_0F3A6A_P_2,
1869   VEX_LEN_0F3A6B_P_2,
1870   VEX_LEN_0F3A6E_P_2,
1871   VEX_LEN_0F3A6F_P_2,
1872   VEX_LEN_0F3A7A_P_2,
1873   VEX_LEN_0F3A7B_P_2,
1874   VEX_LEN_0F3A7E_P_2,
1875   VEX_LEN_0F3A7F_P_2,
1876   VEX_LEN_0F3ADF_P_2,
1877   VEX_LEN_0F3AF0_P_3,
1878   VEX_LEN_0FXOP_08_CC,
1879   VEX_LEN_0FXOP_08_CD,
1880   VEX_LEN_0FXOP_08_CE,
1881   VEX_LEN_0FXOP_08_CF,
1882   VEX_LEN_0FXOP_08_EC,
1883   VEX_LEN_0FXOP_08_ED,
1884   VEX_LEN_0FXOP_08_EE,
1885   VEX_LEN_0FXOP_08_EF,
1886   VEX_LEN_0FXOP_09_80,
1887   VEX_LEN_0FXOP_09_81
1888 };
1889
1890 enum
1891 {
1892   VEX_W_0F10_P_0 = 0,
1893   VEX_W_0F10_P_1,
1894   VEX_W_0F10_P_2,
1895   VEX_W_0F10_P_3,
1896   VEX_W_0F11_P_0,
1897   VEX_W_0F11_P_1,
1898   VEX_W_0F11_P_2,
1899   VEX_W_0F11_P_3,
1900   VEX_W_0F12_P_0_M_0,
1901   VEX_W_0F12_P_0_M_1,
1902   VEX_W_0F12_P_1,
1903   VEX_W_0F12_P_2,
1904   VEX_W_0F12_P_3,
1905   VEX_W_0F13_M_0,
1906   VEX_W_0F14,
1907   VEX_W_0F15,
1908   VEX_W_0F16_P_0_M_0,
1909   VEX_W_0F16_P_0_M_1,
1910   VEX_W_0F16_P_1,
1911   VEX_W_0F16_P_2,
1912   VEX_W_0F17_M_0,
1913   VEX_W_0F28,
1914   VEX_W_0F29,
1915   VEX_W_0F2B_M_0,
1916   VEX_W_0F2E_P_0,
1917   VEX_W_0F2E_P_2,
1918   VEX_W_0F2F_P_0,
1919   VEX_W_0F2F_P_2,
1920   VEX_W_0F41_P_0_LEN_1,
1921   VEX_W_0F41_P_2_LEN_1,
1922   VEX_W_0F42_P_0_LEN_1,
1923   VEX_W_0F42_P_2_LEN_1,
1924   VEX_W_0F44_P_0_LEN_0,
1925   VEX_W_0F44_P_2_LEN_0,
1926   VEX_W_0F45_P_0_LEN_1,
1927   VEX_W_0F45_P_2_LEN_1,
1928   VEX_W_0F46_P_0_LEN_1,
1929   VEX_W_0F46_P_2_LEN_1,
1930   VEX_W_0F47_P_0_LEN_1,
1931   VEX_W_0F47_P_2_LEN_1,
1932   VEX_W_0F4A_P_0_LEN_1,
1933   VEX_W_0F4A_P_2_LEN_1,
1934   VEX_W_0F4B_P_0_LEN_1,
1935   VEX_W_0F4B_P_2_LEN_1,
1936   VEX_W_0F50_M_0,
1937   VEX_W_0F51_P_0,
1938   VEX_W_0F51_P_1,
1939   VEX_W_0F51_P_2,
1940   VEX_W_0F51_P_3,
1941   VEX_W_0F52_P_0,
1942   VEX_W_0F52_P_1,
1943   VEX_W_0F53_P_0,
1944   VEX_W_0F53_P_1,
1945   VEX_W_0F58_P_0,
1946   VEX_W_0F58_P_1,
1947   VEX_W_0F58_P_2,
1948   VEX_W_0F58_P_3,
1949   VEX_W_0F59_P_0,
1950   VEX_W_0F59_P_1,
1951   VEX_W_0F59_P_2,
1952   VEX_W_0F59_P_3,
1953   VEX_W_0F5A_P_0,
1954   VEX_W_0F5A_P_1,
1955   VEX_W_0F5A_P_3,
1956   VEX_W_0F5B_P_0,
1957   VEX_W_0F5B_P_1,
1958   VEX_W_0F5B_P_2,
1959   VEX_W_0F5C_P_0,
1960   VEX_W_0F5C_P_1,
1961   VEX_W_0F5C_P_2,
1962   VEX_W_0F5C_P_3,
1963   VEX_W_0F5D_P_0,
1964   VEX_W_0F5D_P_1,
1965   VEX_W_0F5D_P_2,
1966   VEX_W_0F5D_P_3,
1967   VEX_W_0F5E_P_0,
1968   VEX_W_0F5E_P_1,
1969   VEX_W_0F5E_P_2,
1970   VEX_W_0F5E_P_3,
1971   VEX_W_0F5F_P_0,
1972   VEX_W_0F5F_P_1,
1973   VEX_W_0F5F_P_2,
1974   VEX_W_0F5F_P_3,
1975   VEX_W_0F60_P_2,
1976   VEX_W_0F61_P_2,
1977   VEX_W_0F62_P_2,
1978   VEX_W_0F63_P_2,
1979   VEX_W_0F64_P_2,
1980   VEX_W_0F65_P_2,
1981   VEX_W_0F66_P_2,
1982   VEX_W_0F67_P_2,
1983   VEX_W_0F68_P_2,
1984   VEX_W_0F69_P_2,
1985   VEX_W_0F6A_P_2,
1986   VEX_W_0F6B_P_2,
1987   VEX_W_0F6C_P_2,
1988   VEX_W_0F6D_P_2,
1989   VEX_W_0F6F_P_1,
1990   VEX_W_0F6F_P_2,
1991   VEX_W_0F70_P_1,
1992   VEX_W_0F70_P_2,
1993   VEX_W_0F70_P_3,
1994   VEX_W_0F71_R_2_P_2,
1995   VEX_W_0F71_R_4_P_2,
1996   VEX_W_0F71_R_6_P_2,
1997   VEX_W_0F72_R_2_P_2,
1998   VEX_W_0F72_R_4_P_2,
1999   VEX_W_0F72_R_6_P_2,
2000   VEX_W_0F73_R_2_P_2,
2001   VEX_W_0F73_R_3_P_2,
2002   VEX_W_0F73_R_6_P_2,
2003   VEX_W_0F73_R_7_P_2,
2004   VEX_W_0F74_P_2,
2005   VEX_W_0F75_P_2,
2006   VEX_W_0F76_P_2,
2007   VEX_W_0F77_P_0,
2008   VEX_W_0F7C_P_2,
2009   VEX_W_0F7C_P_3,
2010   VEX_W_0F7D_P_2,
2011   VEX_W_0F7D_P_3,
2012   VEX_W_0F7E_P_1,
2013   VEX_W_0F7F_P_1,
2014   VEX_W_0F7F_P_2,
2015   VEX_W_0F90_P_0_LEN_0,
2016   VEX_W_0F90_P_2_LEN_0,
2017   VEX_W_0F91_P_0_LEN_0,
2018   VEX_W_0F91_P_2_LEN_0,
2019   VEX_W_0F92_P_0_LEN_0,
2020   VEX_W_0F92_P_2_LEN_0,
2021   VEX_W_0F92_P_3_LEN_0,
2022   VEX_W_0F93_P_0_LEN_0,
2023   VEX_W_0F93_P_2_LEN_0,
2024   VEX_W_0F93_P_3_LEN_0,
2025   VEX_W_0F98_P_0_LEN_0,
2026   VEX_W_0F98_P_2_LEN_0,
2027   VEX_W_0F99_P_0_LEN_0,
2028   VEX_W_0F99_P_2_LEN_0,
2029   VEX_W_0FAE_R_2_M_0,
2030   VEX_W_0FAE_R_3_M_0,
2031   VEX_W_0FC2_P_0,
2032   VEX_W_0FC2_P_1,
2033   VEX_W_0FC2_P_2,
2034   VEX_W_0FC2_P_3,
2035   VEX_W_0FC4_P_2,
2036   VEX_W_0FC5_P_2,
2037   VEX_W_0FD0_P_2,
2038   VEX_W_0FD0_P_3,
2039   VEX_W_0FD1_P_2,
2040   VEX_W_0FD2_P_2,
2041   VEX_W_0FD3_P_2,
2042   VEX_W_0FD4_P_2,
2043   VEX_W_0FD5_P_2,
2044   VEX_W_0FD6_P_2,
2045   VEX_W_0FD7_P_2_M_1,
2046   VEX_W_0FD8_P_2,
2047   VEX_W_0FD9_P_2,
2048   VEX_W_0FDA_P_2,
2049   VEX_W_0FDB_P_2,
2050   VEX_W_0FDC_P_2,
2051   VEX_W_0FDD_P_2,
2052   VEX_W_0FDE_P_2,
2053   VEX_W_0FDF_P_2,
2054   VEX_W_0FE0_P_2,
2055   VEX_W_0FE1_P_2,
2056   VEX_W_0FE2_P_2,
2057   VEX_W_0FE3_P_2,
2058   VEX_W_0FE4_P_2,
2059   VEX_W_0FE5_P_2,
2060   VEX_W_0FE6_P_1,
2061   VEX_W_0FE6_P_2,
2062   VEX_W_0FE6_P_3,
2063   VEX_W_0FE7_P_2_M_0,
2064   VEX_W_0FE8_P_2,
2065   VEX_W_0FE9_P_2,
2066   VEX_W_0FEA_P_2,
2067   VEX_W_0FEB_P_2,
2068   VEX_W_0FEC_P_2,
2069   VEX_W_0FED_P_2,
2070   VEX_W_0FEE_P_2,
2071   VEX_W_0FEF_P_2,
2072   VEX_W_0FF0_P_3_M_0,
2073   VEX_W_0FF1_P_2,
2074   VEX_W_0FF2_P_2,
2075   VEX_W_0FF3_P_2,
2076   VEX_W_0FF4_P_2,
2077   VEX_W_0FF5_P_2,
2078   VEX_W_0FF6_P_2,
2079   VEX_W_0FF7_P_2,
2080   VEX_W_0FF8_P_2,
2081   VEX_W_0FF9_P_2,
2082   VEX_W_0FFA_P_2,
2083   VEX_W_0FFB_P_2,
2084   VEX_W_0FFC_P_2,
2085   VEX_W_0FFD_P_2,
2086   VEX_W_0FFE_P_2,
2087   VEX_W_0F3800_P_2,
2088   VEX_W_0F3801_P_2,
2089   VEX_W_0F3802_P_2,
2090   VEX_W_0F3803_P_2,
2091   VEX_W_0F3804_P_2,
2092   VEX_W_0F3805_P_2,
2093   VEX_W_0F3806_P_2,
2094   VEX_W_0F3807_P_2,
2095   VEX_W_0F3808_P_2,
2096   VEX_W_0F3809_P_2,
2097   VEX_W_0F380A_P_2,
2098   VEX_W_0F380B_P_2,
2099   VEX_W_0F380C_P_2,
2100   VEX_W_0F380D_P_2,
2101   VEX_W_0F380E_P_2,
2102   VEX_W_0F380F_P_2,
2103   VEX_W_0F3816_P_2,
2104   VEX_W_0F3817_P_2,
2105   VEX_W_0F3818_P_2,
2106   VEX_W_0F3819_P_2,
2107   VEX_W_0F381A_P_2_M_0,
2108   VEX_W_0F381C_P_2,
2109   VEX_W_0F381D_P_2,
2110   VEX_W_0F381E_P_2,
2111   VEX_W_0F3820_P_2,
2112   VEX_W_0F3821_P_2,
2113   VEX_W_0F3822_P_2,
2114   VEX_W_0F3823_P_2,
2115   VEX_W_0F3824_P_2,
2116   VEX_W_0F3825_P_2,
2117   VEX_W_0F3828_P_2,
2118   VEX_W_0F3829_P_2,
2119   VEX_W_0F382A_P_2_M_0,
2120   VEX_W_0F382B_P_2,
2121   VEX_W_0F382C_P_2_M_0,
2122   VEX_W_0F382D_P_2_M_0,
2123   VEX_W_0F382E_P_2_M_0,
2124   VEX_W_0F382F_P_2_M_0,
2125   VEX_W_0F3830_P_2,
2126   VEX_W_0F3831_P_2,
2127   VEX_W_0F3832_P_2,
2128   VEX_W_0F3833_P_2,
2129   VEX_W_0F3834_P_2,
2130   VEX_W_0F3835_P_2,
2131   VEX_W_0F3836_P_2,
2132   VEX_W_0F3837_P_2,
2133   VEX_W_0F3838_P_2,
2134   VEX_W_0F3839_P_2,
2135   VEX_W_0F383A_P_2,
2136   VEX_W_0F383B_P_2,
2137   VEX_W_0F383C_P_2,
2138   VEX_W_0F383D_P_2,
2139   VEX_W_0F383E_P_2,
2140   VEX_W_0F383F_P_2,
2141   VEX_W_0F3840_P_2,
2142   VEX_W_0F3841_P_2,
2143   VEX_W_0F3846_P_2,
2144   VEX_W_0F3858_P_2,
2145   VEX_W_0F3859_P_2,
2146   VEX_W_0F385A_P_2_M_0,
2147   VEX_W_0F3878_P_2,
2148   VEX_W_0F3879_P_2,
2149   VEX_W_0F38DB_P_2,
2150   VEX_W_0F38DC_P_2,
2151   VEX_W_0F38DD_P_2,
2152   VEX_W_0F38DE_P_2,
2153   VEX_W_0F38DF_P_2,
2154   VEX_W_0F3A00_P_2,
2155   VEX_W_0F3A01_P_2,
2156   VEX_W_0F3A02_P_2,
2157   VEX_W_0F3A04_P_2,
2158   VEX_W_0F3A05_P_2,
2159   VEX_W_0F3A06_P_2,
2160   VEX_W_0F3A08_P_2,
2161   VEX_W_0F3A09_P_2,
2162   VEX_W_0F3A0A_P_2,
2163   VEX_W_0F3A0B_P_2,
2164   VEX_W_0F3A0C_P_2,
2165   VEX_W_0F3A0D_P_2,
2166   VEX_W_0F3A0E_P_2,
2167   VEX_W_0F3A0F_P_2,
2168   VEX_W_0F3A14_P_2,
2169   VEX_W_0F3A15_P_2,
2170   VEX_W_0F3A18_P_2,
2171   VEX_W_0F3A19_P_2,
2172   VEX_W_0F3A20_P_2,
2173   VEX_W_0F3A21_P_2,
2174   VEX_W_0F3A30_P_2_LEN_0,
2175   VEX_W_0F3A31_P_2_LEN_0,
2176   VEX_W_0F3A32_P_2_LEN_0,
2177   VEX_W_0F3A33_P_2_LEN_0,
2178   VEX_W_0F3A38_P_2,
2179   VEX_W_0F3A39_P_2,
2180   VEX_W_0F3A40_P_2,
2181   VEX_W_0F3A41_P_2,
2182   VEX_W_0F3A42_P_2,
2183   VEX_W_0F3A44_P_2,
2184   VEX_W_0F3A46_P_2,
2185   VEX_W_0F3A48_P_2,
2186   VEX_W_0F3A49_P_2,
2187   VEX_W_0F3A4A_P_2,
2188   VEX_W_0F3A4B_P_2,
2189   VEX_W_0F3A4C_P_2,
2190   VEX_W_0F3A60_P_2,
2191   VEX_W_0F3A61_P_2,
2192   VEX_W_0F3A62_P_2,
2193   VEX_W_0F3A63_P_2,
2194   VEX_W_0F3ADF_P_2,
2195
2196   EVEX_W_0F10_P_0,
2197   EVEX_W_0F10_P_1_M_0,
2198   EVEX_W_0F10_P_1_M_1,
2199   EVEX_W_0F10_P_2,
2200   EVEX_W_0F10_P_3_M_0,
2201   EVEX_W_0F10_P_3_M_1,
2202   EVEX_W_0F11_P_0,
2203   EVEX_W_0F11_P_1_M_0,
2204   EVEX_W_0F11_P_1_M_1,
2205   EVEX_W_0F11_P_2,
2206   EVEX_W_0F11_P_3_M_0,
2207   EVEX_W_0F11_P_3_M_1,
2208   EVEX_W_0F12_P_0_M_0,
2209   EVEX_W_0F12_P_0_M_1,
2210   EVEX_W_0F12_P_1,
2211   EVEX_W_0F12_P_2,
2212   EVEX_W_0F12_P_3,
2213   EVEX_W_0F13_P_0,
2214   EVEX_W_0F13_P_2,
2215   EVEX_W_0F14_P_0,
2216   EVEX_W_0F14_P_2,
2217   EVEX_W_0F15_P_0,
2218   EVEX_W_0F15_P_2,
2219   EVEX_W_0F16_P_0_M_0,
2220   EVEX_W_0F16_P_0_M_1,
2221   EVEX_W_0F16_P_1,
2222   EVEX_W_0F16_P_2,
2223   EVEX_W_0F17_P_0,
2224   EVEX_W_0F17_P_2,
2225   EVEX_W_0F28_P_0,
2226   EVEX_W_0F28_P_2,
2227   EVEX_W_0F29_P_0,
2228   EVEX_W_0F29_P_2,
2229   EVEX_W_0F2A_P_1,
2230   EVEX_W_0F2A_P_3,
2231   EVEX_W_0F2B_P_0,
2232   EVEX_W_0F2B_P_2,
2233   EVEX_W_0F2E_P_0,
2234   EVEX_W_0F2E_P_2,
2235   EVEX_W_0F2F_P_0,
2236   EVEX_W_0F2F_P_2,
2237   EVEX_W_0F51_P_0,
2238   EVEX_W_0F51_P_1,
2239   EVEX_W_0F51_P_2,
2240   EVEX_W_0F51_P_3,
2241   EVEX_W_0F54_P_0,
2242   EVEX_W_0F54_P_2,
2243   EVEX_W_0F55_P_0,
2244   EVEX_W_0F55_P_2,
2245   EVEX_W_0F56_P_0,
2246   EVEX_W_0F56_P_2,
2247   EVEX_W_0F57_P_0,
2248   EVEX_W_0F57_P_2,
2249   EVEX_W_0F58_P_0,
2250   EVEX_W_0F58_P_1,
2251   EVEX_W_0F58_P_2,
2252   EVEX_W_0F58_P_3,
2253   EVEX_W_0F59_P_0,
2254   EVEX_W_0F59_P_1,
2255   EVEX_W_0F59_P_2,
2256   EVEX_W_0F59_P_3,
2257   EVEX_W_0F5A_P_0,
2258   EVEX_W_0F5A_P_1,
2259   EVEX_W_0F5A_P_2,
2260   EVEX_W_0F5A_P_3,
2261   EVEX_W_0F5B_P_0,
2262   EVEX_W_0F5B_P_1,
2263   EVEX_W_0F5B_P_2,
2264   EVEX_W_0F5C_P_0,
2265   EVEX_W_0F5C_P_1,
2266   EVEX_W_0F5C_P_2,
2267   EVEX_W_0F5C_P_3,
2268   EVEX_W_0F5D_P_0,
2269   EVEX_W_0F5D_P_1,
2270   EVEX_W_0F5D_P_2,
2271   EVEX_W_0F5D_P_3,
2272   EVEX_W_0F5E_P_0,
2273   EVEX_W_0F5E_P_1,
2274   EVEX_W_0F5E_P_2,
2275   EVEX_W_0F5E_P_3,
2276   EVEX_W_0F5F_P_0,
2277   EVEX_W_0F5F_P_1,
2278   EVEX_W_0F5F_P_2,
2279   EVEX_W_0F5F_P_3,
2280   EVEX_W_0F62_P_2,
2281   EVEX_W_0F66_P_2,
2282   EVEX_W_0F6A_P_2,
2283   EVEX_W_0F6B_P_2,
2284   EVEX_W_0F6C_P_2,
2285   EVEX_W_0F6D_P_2,
2286   EVEX_W_0F6E_P_2,
2287   EVEX_W_0F6F_P_1,
2288   EVEX_W_0F6F_P_2,
2289   EVEX_W_0F6F_P_3,
2290   EVEX_W_0F70_P_2,
2291   EVEX_W_0F72_R_2_P_2,
2292   EVEX_W_0F72_R_6_P_2,
2293   EVEX_W_0F73_R_2_P_2,
2294   EVEX_W_0F73_R_6_P_2,
2295   EVEX_W_0F76_P_2,
2296   EVEX_W_0F78_P_0,
2297   EVEX_W_0F78_P_2,
2298   EVEX_W_0F79_P_0,
2299   EVEX_W_0F79_P_2,
2300   EVEX_W_0F7A_P_1,
2301   EVEX_W_0F7A_P_2,
2302   EVEX_W_0F7A_P_3,
2303   EVEX_W_0F7B_P_1,
2304   EVEX_W_0F7B_P_2,
2305   EVEX_W_0F7B_P_3,
2306   EVEX_W_0F7E_P_1,
2307   EVEX_W_0F7E_P_2,
2308   EVEX_W_0F7F_P_1,
2309   EVEX_W_0F7F_P_2,
2310   EVEX_W_0F7F_P_3,
2311   EVEX_W_0FC2_P_0,
2312   EVEX_W_0FC2_P_1,
2313   EVEX_W_0FC2_P_2,
2314   EVEX_W_0FC2_P_3,
2315   EVEX_W_0FC6_P_0,
2316   EVEX_W_0FC6_P_2,
2317   EVEX_W_0FD2_P_2,
2318   EVEX_W_0FD3_P_2,
2319   EVEX_W_0FD4_P_2,
2320   EVEX_W_0FD6_P_2,
2321   EVEX_W_0FE6_P_1,
2322   EVEX_W_0FE6_P_2,
2323   EVEX_W_0FE6_P_3,
2324   EVEX_W_0FE7_P_2,
2325   EVEX_W_0FF2_P_2,
2326   EVEX_W_0FF3_P_2,
2327   EVEX_W_0FF4_P_2,
2328   EVEX_W_0FFA_P_2,
2329   EVEX_W_0FFB_P_2,
2330   EVEX_W_0FFE_P_2,
2331   EVEX_W_0F380C_P_2,
2332   EVEX_W_0F380D_P_2,
2333   EVEX_W_0F3810_P_1,
2334   EVEX_W_0F3810_P_2,
2335   EVEX_W_0F3811_P_1,
2336   EVEX_W_0F3811_P_2,
2337   EVEX_W_0F3812_P_1,
2338   EVEX_W_0F3812_P_2,
2339   EVEX_W_0F3813_P_1,
2340   EVEX_W_0F3813_P_2,
2341   EVEX_W_0F3814_P_1,
2342   EVEX_W_0F3815_P_1,
2343   EVEX_W_0F3818_P_2,
2344   EVEX_W_0F3819_P_2,
2345   EVEX_W_0F381A_P_2,
2346   EVEX_W_0F381B_P_2,
2347   EVEX_W_0F381E_P_2,
2348   EVEX_W_0F381F_P_2,
2349   EVEX_W_0F3820_P_1,
2350   EVEX_W_0F3821_P_1,
2351   EVEX_W_0F3822_P_1,
2352   EVEX_W_0F3823_P_1,
2353   EVEX_W_0F3824_P_1,
2354   EVEX_W_0F3825_P_1,
2355   EVEX_W_0F3825_P_2,
2356   EVEX_W_0F3826_P_1,
2357   EVEX_W_0F3826_P_2,
2358   EVEX_W_0F3828_P_1,
2359   EVEX_W_0F3828_P_2,
2360   EVEX_W_0F3829_P_1,
2361   EVEX_W_0F3829_P_2,
2362   EVEX_W_0F382A_P_1,
2363   EVEX_W_0F382A_P_2,
2364   EVEX_W_0F382B_P_2,
2365   EVEX_W_0F3830_P_1,
2366   EVEX_W_0F3831_P_1,
2367   EVEX_W_0F3832_P_1,
2368   EVEX_W_0F3833_P_1,
2369   EVEX_W_0F3834_P_1,
2370   EVEX_W_0F3835_P_1,
2371   EVEX_W_0F3835_P_2,
2372   EVEX_W_0F3837_P_2,
2373   EVEX_W_0F3838_P_1,
2374   EVEX_W_0F3839_P_1,
2375   EVEX_W_0F383A_P_1,
2376   EVEX_W_0F3840_P_2,
2377   EVEX_W_0F3858_P_2,
2378   EVEX_W_0F3859_P_2,
2379   EVEX_W_0F385A_P_2,
2380   EVEX_W_0F385B_P_2,
2381   EVEX_W_0F3866_P_2,
2382   EVEX_W_0F3875_P_2,
2383   EVEX_W_0F3878_P_2,
2384   EVEX_W_0F3879_P_2,
2385   EVEX_W_0F387A_P_2,
2386   EVEX_W_0F387B_P_2,
2387   EVEX_W_0F387D_P_2,
2388   EVEX_W_0F3883_P_2,
2389   EVEX_W_0F388D_P_2,
2390   EVEX_W_0F3891_P_2,
2391   EVEX_W_0F3893_P_2,
2392   EVEX_W_0F38A1_P_2,
2393   EVEX_W_0F38A3_P_2,
2394   EVEX_W_0F38C7_R_1_P_2,
2395   EVEX_W_0F38C7_R_2_P_2,
2396   EVEX_W_0F38C7_R_5_P_2,
2397   EVEX_W_0F38C7_R_6_P_2,
2398
2399   EVEX_W_0F3A00_P_2,
2400   EVEX_W_0F3A01_P_2,
2401   EVEX_W_0F3A04_P_2,
2402   EVEX_W_0F3A05_P_2,
2403   EVEX_W_0F3A08_P_2,
2404   EVEX_W_0F3A09_P_2,
2405   EVEX_W_0F3A0A_P_2,
2406   EVEX_W_0F3A0B_P_2,
2407   EVEX_W_0F3A16_P_2,
2408   EVEX_W_0F3A18_P_2,
2409   EVEX_W_0F3A19_P_2,
2410   EVEX_W_0F3A1A_P_2,
2411   EVEX_W_0F3A1B_P_2,
2412   EVEX_W_0F3A1D_P_2,
2413   EVEX_W_0F3A21_P_2,
2414   EVEX_W_0F3A22_P_2,
2415   EVEX_W_0F3A23_P_2,
2416   EVEX_W_0F3A38_P_2,
2417   EVEX_W_0F3A39_P_2,
2418   EVEX_W_0F3A3A_P_2,
2419   EVEX_W_0F3A3B_P_2,
2420   EVEX_W_0F3A3E_P_2,
2421   EVEX_W_0F3A3F_P_2,
2422   EVEX_W_0F3A42_P_2,
2423   EVEX_W_0F3A43_P_2,
2424   EVEX_W_0F3A50_P_2,
2425   EVEX_W_0F3A51_P_2,
2426   EVEX_W_0F3A56_P_2,
2427   EVEX_W_0F3A57_P_2,
2428   EVEX_W_0F3A66_P_2,
2429   EVEX_W_0F3A67_P_2
2430 };
2431
2432 typedef void (*op_rtn) (int bytemode, int sizeflag);
2433
2434 struct dis386 {
2435   const char *name;
2436   struct
2437     {
2438       op_rtn rtn;
2439       int bytemode;
2440     } op[MAX_OPERANDS];
2441   unsigned int prefix_requirement;
2442 };
2443
2444 /* Upper case letters in the instruction names here are macros.
2445    'A' => print 'b' if no register operands or suffix_always is true
2446    'B' => print 'b' if suffix_always is true
2447    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2448           size prefix
2449    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2450           suffix_always is true
2451    'E' => print 'e' if 32-bit form of jcxz
2452    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2453    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2454    'H' => print ",pt" or ",pn" branch hint
2455    'I' => honor following macro letter even in Intel mode (implemented only
2456           for some of the macro letters)
2457    'J' => print 'l'
2458    'K' => print 'd' or 'q' if rex prefix is present.
2459    'L' => print 'l' if suffix_always is true
2460    'M' => print 'r' if intel_mnemonic is false.
2461    'N' => print 'n' if instruction has no wait "prefix"
2462    'O' => print 'd' or 'o' (or 'q' in Intel mode)
2463    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2464           or suffix_always is true.  print 'q' if rex prefix is present.
2465    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2466           is true
2467    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2468    'S' => print 'w', 'l' or 'q' if suffix_always is true
2469    'T' => print 'q' in 64bit mode if instruction has no operand size
2470           prefix and behave as 'P' otherwise
2471    'U' => print 'q' in 64bit mode if instruction has no operand size
2472           prefix and behave as 'Q' otherwise
2473    'V' => print 'q' in 64bit mode if instruction has no operand size
2474           prefix and behave as 'S' otherwise
2475    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2476    'X' => print 's', 'd' depending on data16 prefix (for XMM)
2477    'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
2478           suffix_always is true.
2479    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2480    '!' => change condition from true to false or from false to true.
2481    '%' => add 1 upper case letter to the macro.
2482    '^' => print 'w' or 'l' depending on operand size prefix or
2483           suffix_always is true (lcall/ljmp).
2484    '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2485           on operand size prefix.
2486
2487    2 upper case letter macros:
2488    "XY" => print 'x' or 'y' if suffix_always is true or no register
2489            operands and no broadcast.
2490    "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2491            register operands and no broadcast.
2492    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2493    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2494            or suffix_always is true
2495    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2496    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2497    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2498    "LW" => print 'd', 'q' depending on the VEX.W bit
2499    "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2500            an operand size prefix, or suffix_always is true.  print
2501            'q' if rex prefix is present.
2502
2503    Many of the above letters print nothing in Intel mode.  See "putop"
2504    for the details.
2505
2506    Braces '{' and '}', and vertical bars '|', indicate alternative
2507    mnemonic strings for AT&T and Intel.  */
2508
2509 static const struct dis386 dis386[] = {
2510   /* 00 */
2511   { "addB",             { Ebh1, Gb }, 0 },
2512   { "addS",             { Evh1, Gv }, 0 },
2513   { "addB",             { Gb, EbS }, 0 },
2514   { "addS",             { Gv, EvS }, 0 },
2515   { "addB",             { AL, Ib }, 0 },
2516   { "addS",             { eAX, Iv }, 0 },
2517   { X86_64_TABLE (X86_64_06) },
2518   { X86_64_TABLE (X86_64_07) },
2519   /* 08 */
2520   { "orB",              { Ebh1, Gb }, 0 },
2521   { "orS",              { Evh1, Gv }, 0 },
2522   { "orB",              { Gb, EbS }, 0 },
2523   { "orS",              { Gv, EvS }, 0 },
2524   { "orB",              { AL, Ib }, 0 },
2525   { "orS",              { eAX, Iv }, 0 },
2526   { X86_64_TABLE (X86_64_0D) },
2527   { Bad_Opcode },       /* 0x0f extended opcode escape */
2528   /* 10 */
2529   { "adcB",             { Ebh1, Gb }, 0 },
2530   { "adcS",             { Evh1, Gv }, 0 },
2531   { "adcB",             { Gb, EbS }, 0 },
2532   { "adcS",             { Gv, EvS }, 0 },
2533   { "adcB",             { AL, Ib }, 0 },
2534   { "adcS",             { eAX, Iv }, 0 },
2535   { X86_64_TABLE (X86_64_16) },
2536   { X86_64_TABLE (X86_64_17) },
2537   /* 18 */
2538   { "sbbB",             { Ebh1, Gb }, 0 },
2539   { "sbbS",             { Evh1, Gv }, 0 },
2540   { "sbbB",             { Gb, EbS }, 0 },
2541   { "sbbS",             { Gv, EvS }, 0 },
2542   { "sbbB",             { AL, Ib }, 0 },
2543   { "sbbS",             { eAX, Iv }, 0 },
2544   { X86_64_TABLE (X86_64_1E) },
2545   { X86_64_TABLE (X86_64_1F) },
2546   /* 20 */
2547   { "andB",             { Ebh1, Gb }, 0 },
2548   { "andS",             { Evh1, Gv }, 0 },
2549   { "andB",             { Gb, EbS }, 0 },
2550   { "andS",             { Gv, EvS }, 0 },
2551   { "andB",             { AL, Ib }, 0 },
2552   { "andS",             { eAX, Iv }, 0 },
2553   { Bad_Opcode },       /* SEG ES prefix */
2554   { X86_64_TABLE (X86_64_27) },
2555   /* 28 */
2556   { "subB",             { Ebh1, Gb }, 0 },
2557   { "subS",             { Evh1, Gv }, 0 },
2558   { "subB",             { Gb, EbS }, 0 },
2559   { "subS",             { Gv, EvS }, 0 },
2560   { "subB",             { AL, Ib }, 0 },
2561   { "subS",             { eAX, Iv }, 0 },
2562   { Bad_Opcode },       /* SEG CS prefix */
2563   { X86_64_TABLE (X86_64_2F) },
2564   /* 30 */
2565   { "xorB",             { Ebh1, Gb }, 0 },
2566   { "xorS",             { Evh1, Gv }, 0 },
2567   { "xorB",             { Gb, EbS }, 0 },
2568   { "xorS",             { Gv, EvS }, 0 },
2569   { "xorB",             { AL, Ib }, 0 },
2570   { "xorS",             { eAX, Iv }, 0 },
2571   { Bad_Opcode },       /* SEG SS prefix */
2572   { X86_64_TABLE (X86_64_37) },
2573   /* 38 */
2574   { "cmpB",             { Eb, Gb }, 0 },
2575   { "cmpS",             { Ev, Gv }, 0 },
2576   { "cmpB",             { Gb, EbS }, 0 },
2577   { "cmpS",             { Gv, EvS }, 0 },
2578   { "cmpB",             { AL, Ib }, 0 },
2579   { "cmpS",             { eAX, Iv }, 0 },
2580   { Bad_Opcode },       /* SEG DS prefix */
2581   { X86_64_TABLE (X86_64_3F) },
2582   /* 40 */
2583   { "inc{S|}",          { RMeAX }, 0 },
2584   { "inc{S|}",          { RMeCX }, 0 },
2585   { "inc{S|}",          { RMeDX }, 0 },
2586   { "inc{S|}",          { RMeBX }, 0 },
2587   { "inc{S|}",          { RMeSP }, 0 },
2588   { "inc{S|}",          { RMeBP }, 0 },
2589   { "inc{S|}",          { RMeSI }, 0 },
2590   { "inc{S|}",          { RMeDI }, 0 },
2591   /* 48 */
2592   { "dec{S|}",          { RMeAX }, 0 },
2593   { "dec{S|}",          { RMeCX }, 0 },
2594   { "dec{S|}",          { RMeDX }, 0 },
2595   { "dec{S|}",          { RMeBX }, 0 },
2596   { "dec{S|}",          { RMeSP }, 0 },
2597   { "dec{S|}",          { RMeBP }, 0 },
2598   { "dec{S|}",          { RMeSI }, 0 },
2599   { "dec{S|}",          { RMeDI }, 0 },
2600   /* 50 */
2601   { "pushV",            { RMrAX }, 0 },
2602   { "pushV",            { RMrCX }, 0 },
2603   { "pushV",            { RMrDX }, 0 },
2604   { "pushV",            { RMrBX }, 0 },
2605   { "pushV",            { RMrSP }, 0 },
2606   { "pushV",            { RMrBP }, 0 },
2607   { "pushV",            { RMrSI }, 0 },
2608   { "pushV",            { RMrDI }, 0 },
2609   /* 58 */
2610   { "popV",             { RMrAX }, 0 },
2611   { "popV",             { RMrCX }, 0 },
2612   { "popV",             { RMrDX }, 0 },
2613   { "popV",             { RMrBX }, 0 },
2614   { "popV",             { RMrSP }, 0 },
2615   { "popV",             { RMrBP }, 0 },
2616   { "popV",             { RMrSI }, 0 },
2617   { "popV",             { RMrDI }, 0 },
2618   /* 60 */
2619   { X86_64_TABLE (X86_64_60) },
2620   { X86_64_TABLE (X86_64_61) },
2621   { X86_64_TABLE (X86_64_62) },
2622   { X86_64_TABLE (X86_64_63) },
2623   { Bad_Opcode },       /* seg fs */
2624   { Bad_Opcode },       /* seg gs */
2625   { Bad_Opcode },       /* op size prefix */
2626   { Bad_Opcode },       /* adr size prefix */
2627   /* 68 */
2628   { "pushT",            { sIv }, 0 },
2629   { "imulS",            { Gv, Ev, Iv }, 0 },
2630   { "pushT",            { sIbT }, 0 },
2631   { "imulS",            { Gv, Ev, sIb }, 0 },
2632   { "ins{b|}",          { Ybr, indirDX }, 0 },
2633   { X86_64_TABLE (X86_64_6D) },
2634   { "outs{b|}",         { indirDXr, Xb }, 0 },
2635   { X86_64_TABLE (X86_64_6F) },
2636   /* 70 */
2637   { "joH",              { Jb, BND, cond_jump_flag }, 0 },
2638   { "jnoH",             { Jb, BND, cond_jump_flag }, 0 },
2639   { "jbH",              { Jb, BND, cond_jump_flag }, 0 },
2640   { "jaeH",             { Jb, BND, cond_jump_flag }, 0 },
2641   { "jeH",              { Jb, BND, cond_jump_flag }, 0 },
2642   { "jneH",             { Jb, BND, cond_jump_flag }, 0 },
2643   { "jbeH",             { Jb, BND, cond_jump_flag }, 0 },
2644   { "jaH",              { Jb, BND, cond_jump_flag }, 0 },
2645   /* 78 */
2646   { "jsH",              { Jb, BND, cond_jump_flag }, 0 },
2647   { "jnsH",             { Jb, BND, cond_jump_flag }, 0 },
2648   { "jpH",              { Jb, BND, cond_jump_flag }, 0 },
2649   { "jnpH",             { Jb, BND, cond_jump_flag }, 0 },
2650   { "jlH",              { Jb, BND, cond_jump_flag }, 0 },
2651   { "jgeH",             { Jb, BND, cond_jump_flag }, 0 },
2652   { "jleH",             { Jb, BND, cond_jump_flag }, 0 },
2653   { "jgH",              { Jb, BND, cond_jump_flag }, 0 },
2654   /* 80 */
2655   { REG_TABLE (REG_80) },
2656   { REG_TABLE (REG_81) },
2657   { Bad_Opcode },
2658   { REG_TABLE (REG_82) },
2659   { "testB",            { Eb, Gb }, 0 },
2660   { "testS",            { Ev, Gv }, 0 },
2661   { "xchgB",            { Ebh2, Gb }, 0 },
2662   { "xchgS",            { Evh2, Gv }, 0 },
2663   /* 88 */
2664   { "movB",             { Ebh3, Gb }, 0 },
2665   { "movS",             { Evh3, Gv }, 0 },
2666   { "movB",             { Gb, EbS }, 0 },
2667   { "movS",             { Gv, EvS }, 0 },
2668   { "movD",             { Sv, Sw }, 0 },
2669   { MOD_TABLE (MOD_8D) },
2670   { "movD",             { Sw, Sv }, 0 },
2671   { REG_TABLE (REG_8F) },
2672   /* 90 */
2673   { PREFIX_TABLE (PREFIX_90) },
2674   { "xchgS",            { RMeCX, eAX }, 0 },
2675   { "xchgS",            { RMeDX, eAX }, 0 },
2676   { "xchgS",            { RMeBX, eAX }, 0 },
2677   { "xchgS",            { RMeSP, eAX }, 0 },
2678   { "xchgS",            { RMeBP, eAX }, 0 },
2679   { "xchgS",            { RMeSI, eAX }, 0 },
2680   { "xchgS",            { RMeDI, eAX }, 0 },
2681   /* 98 */
2682   { "cW{t|}R",          { XX }, 0 },
2683   { "cR{t|}O",          { XX }, 0 },
2684   { X86_64_TABLE (X86_64_9A) },
2685   { Bad_Opcode },       /* fwait */
2686   { "pushfT",           { XX }, 0 },
2687   { "popfT",            { XX }, 0 },
2688   { "sahf",             { XX }, 0 },
2689   { "lahf",             { XX }, 0 },
2690   /* a0 */
2691   { "mov%LB",           { AL, Ob }, 0 },
2692   { "mov%LS",           { eAX, Ov }, 0 },
2693   { "mov%LB",           { Ob, AL }, 0 },
2694   { "mov%LS",           { Ov, eAX }, 0 },
2695   { "movs{b|}",         { Ybr, Xb }, 0 },
2696   { "movs{R|}",         { Yvr, Xv }, 0 },
2697   { "cmps{b|}",         { Xb, Yb }, 0 },
2698   { "cmps{R|}",         { Xv, Yv }, 0 },
2699   /* a8 */
2700   { "testB",            { AL, Ib }, 0 },
2701   { "testS",            { eAX, Iv }, 0 },
2702   { "stosB",            { Ybr, AL }, 0 },
2703   { "stosS",            { Yvr, eAX }, 0 },
2704   { "lodsB",            { ALr, Xb }, 0 },
2705   { "lodsS",            { eAXr, Xv }, 0 },
2706   { "scasB",            { AL, Yb }, 0 },
2707   { "scasS",            { eAX, Yv }, 0 },
2708   /* b0 */
2709   { "movB",             { RMAL, Ib }, 0 },
2710   { "movB",             { RMCL, Ib }, 0 },
2711   { "movB",             { RMDL, Ib }, 0 },
2712   { "movB",             { RMBL, Ib }, 0 },
2713   { "movB",             { RMAH, Ib }, 0 },
2714   { "movB",             { RMCH, Ib }, 0 },
2715   { "movB",             { RMDH, Ib }, 0 },
2716   { "movB",             { RMBH, Ib }, 0 },
2717   /* b8 */
2718   { "mov%LV",           { RMeAX, Iv64 }, 0 },
2719   { "mov%LV",           { RMeCX, Iv64 }, 0 },
2720   { "mov%LV",           { RMeDX, Iv64 }, 0 },
2721   { "mov%LV",           { RMeBX, Iv64 }, 0 },
2722   { "mov%LV",           { RMeSP, Iv64 }, 0 },
2723   { "mov%LV",           { RMeBP, Iv64 }, 0 },
2724   { "mov%LV",           { RMeSI, Iv64 }, 0 },
2725   { "mov%LV",           { RMeDI, Iv64 }, 0 },
2726   /* c0 */
2727   { REG_TABLE (REG_C0) },
2728   { REG_TABLE (REG_C1) },
2729   { "retT",             { Iw, BND }, 0 },
2730   { "retT",             { BND }, 0 },
2731   { X86_64_TABLE (X86_64_C4) },
2732   { X86_64_TABLE (X86_64_C5) },
2733   { REG_TABLE (REG_C6) },
2734   { REG_TABLE (REG_C7) },
2735   /* c8 */
2736   { "enterT",           { Iw, Ib }, 0 },
2737   { "leaveT",           { XX }, 0 },
2738   { "Jret{|f}P",        { Iw }, 0 },
2739   { "Jret{|f}P",        { XX }, 0 },
2740   { "int3",             { XX }, 0 },
2741   { "int",              { Ib }, 0 },
2742   { X86_64_TABLE (X86_64_CE) },
2743   { "iret%LP",          { XX }, 0 },
2744   /* d0 */
2745   { REG_TABLE (REG_D0) },
2746   { REG_TABLE (REG_D1) },
2747   { REG_TABLE (REG_D2) },
2748   { REG_TABLE (REG_D3) },
2749   { X86_64_TABLE (X86_64_D4) },
2750   { X86_64_TABLE (X86_64_D5) },
2751   { Bad_Opcode },
2752   { "xlat",             { DSBX }, 0 },
2753   /* d8 */
2754   { FLOAT },
2755   { FLOAT },
2756   { FLOAT },
2757   { FLOAT },
2758   { FLOAT },
2759   { FLOAT },
2760   { FLOAT },
2761   { FLOAT },
2762   /* e0 */
2763   { "loopneFH",         { Jb, XX, loop_jcxz_flag }, 0 },
2764   { "loopeFH",          { Jb, XX, loop_jcxz_flag }, 0 },
2765   { "loopFH",           { Jb, XX, loop_jcxz_flag }, 0 },
2766   { "jEcxzH",           { Jb, XX, loop_jcxz_flag }, 0 },
2767   { "inB",              { AL, Ib }, 0 },
2768   { "inG",              { zAX, Ib }, 0 },
2769   { "outB",             { Ib, AL }, 0 },
2770   { "outG",             { Ib, zAX }, 0 },
2771   /* e8 */
2772   { X86_64_TABLE (X86_64_E8) },
2773   { X86_64_TABLE (X86_64_E9) },
2774   { X86_64_TABLE (X86_64_EA) },
2775   { "jmp",              { Jb, BND }, 0 },
2776   { "inB",              { AL, indirDX }, 0 },
2777   { "inG",              { zAX, indirDX }, 0 },
2778   { "outB",             { indirDX, AL }, 0 },
2779   { "outG",             { indirDX, zAX }, 0 },
2780   /* f0 */
2781   { Bad_Opcode },       /* lock prefix */
2782   { "icebp",            { XX }, 0 },
2783   { Bad_Opcode },       /* repne */
2784   { Bad_Opcode },       /* repz */
2785   { "hlt",              { XX }, 0 },
2786   { "cmc",              { XX }, 0 },
2787   { REG_TABLE (REG_F6) },
2788   { REG_TABLE (REG_F7) },
2789   /* f8 */
2790   { "clc",              { XX }, 0 },
2791   { "stc",              { XX }, 0 },
2792   { "cli",              { XX }, 0 },
2793   { "sti",              { XX }, 0 },
2794   { "cld",              { XX }, 0 },
2795   { "std",              { XX }, 0 },
2796   { REG_TABLE (REG_FE) },
2797   { REG_TABLE (REG_FF) },
2798 };
2799
2800 static const struct dis386 dis386_twobyte[] = {
2801   /* 00 */
2802   { REG_TABLE (REG_0F00 ) },
2803   { REG_TABLE (REG_0F01 ) },
2804   { "larS",             { Gv, Ew }, 0 },
2805   { "lslS",             { Gv, Ew }, 0 },
2806   { Bad_Opcode },
2807   { "syscall",          { XX }, 0 },
2808   { "clts",             { XX }, 0 },
2809   { "sysret%LP",                { XX }, 0 },
2810   /* 08 */
2811   { "invd",             { XX }, 0 },
2812   { "wbinvd",           { XX }, 0 },
2813   { Bad_Opcode },
2814   { "ud2",              { XX }, 0 },
2815   { Bad_Opcode },
2816   { REG_TABLE (REG_0F0D) },
2817   { "femms",            { XX }, 0 },
2818   { "",                 { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix.  */
2819   /* 10 */
2820   { PREFIX_TABLE (PREFIX_0F10) },
2821   { PREFIX_TABLE (PREFIX_0F11) },
2822   { PREFIX_TABLE (PREFIX_0F12) },
2823   { MOD_TABLE (MOD_0F13) },
2824   { "unpcklpX",         { XM, EXx }, PREFIX_OPCODE },
2825   { "unpckhpX",         { XM, EXx }, PREFIX_OPCODE },
2826   { PREFIX_TABLE (PREFIX_0F16) },
2827   { MOD_TABLE (MOD_0F17) },
2828   /* 18 */
2829   { REG_TABLE (REG_0F18) },
2830   { "nopQ",             { Ev }, 0 },
2831   { PREFIX_TABLE (PREFIX_0F1A) },
2832   { PREFIX_TABLE (PREFIX_0F1B) },
2833   { "nopQ",             { Ev }, 0 },
2834   { "nopQ",             { Ev }, 0 },
2835   { "nopQ",             { Ev }, 0 },
2836   { "nopQ",             { Ev }, 0 },
2837   /* 20 */
2838   { "movZ",             { Rm, Cm }, 0 },
2839   { "movZ",             { Rm, Dm }, 0 },
2840   { "movZ",             { Cm, Rm }, 0 },
2841   { "movZ",             { Dm, Rm }, 0 },
2842   { MOD_TABLE (MOD_0F24) },
2843   { Bad_Opcode },
2844   { MOD_TABLE (MOD_0F26) },
2845   { Bad_Opcode },
2846   /* 28 */
2847   { "movapX",           { XM, EXx }, PREFIX_OPCODE },
2848   { "movapX",           { EXxS, XM }, PREFIX_OPCODE },
2849   { PREFIX_TABLE (PREFIX_0F2A) },
2850   { PREFIX_TABLE (PREFIX_0F2B) },
2851   { PREFIX_TABLE (PREFIX_0F2C) },
2852   { PREFIX_TABLE (PREFIX_0F2D) },
2853   { PREFIX_TABLE (PREFIX_0F2E) },
2854   { PREFIX_TABLE (PREFIX_0F2F) },
2855   /* 30 */
2856   { "wrmsr",            { XX }, 0 },
2857   { "rdtsc",            { XX }, 0 },
2858   { "rdmsr",            { XX }, 0 },
2859   { "rdpmc",            { XX }, 0 },
2860   { "sysenter",         { XX }, 0 },
2861   { "sysexit",          { XX }, 0 },
2862   { Bad_Opcode },
2863   { "getsec",           { XX }, 0 },
2864   /* 38 */
2865   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2866   { Bad_Opcode },
2867   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2868   { Bad_Opcode },
2869   { Bad_Opcode },
2870   { Bad_Opcode },
2871   { Bad_Opcode },
2872   { Bad_Opcode },
2873   /* 40 */
2874   { "cmovoS",           { Gv, Ev }, 0 },
2875   { "cmovnoS",          { Gv, Ev }, 0 },
2876   { "cmovbS",           { Gv, Ev }, 0 },
2877   { "cmovaeS",          { Gv, Ev }, 0 },
2878   { "cmoveS",           { Gv, Ev }, 0 },
2879   { "cmovneS",          { Gv, Ev }, 0 },
2880   { "cmovbeS",          { Gv, Ev }, 0 },
2881   { "cmovaS",           { Gv, Ev }, 0 },
2882   /* 48 */
2883   { "cmovsS",           { Gv, Ev }, 0 },
2884   { "cmovnsS",          { Gv, Ev }, 0 },
2885   { "cmovpS",           { Gv, Ev }, 0 },
2886   { "cmovnpS",          { Gv, Ev }, 0 },
2887   { "cmovlS",           { Gv, Ev }, 0 },
2888   { "cmovgeS",          { Gv, Ev }, 0 },
2889   { "cmovleS",          { Gv, Ev }, 0 },
2890   { "cmovgS",           { Gv, Ev }, 0 },
2891   /* 50 */
2892   { MOD_TABLE (MOD_0F51) },
2893   { PREFIX_TABLE (PREFIX_0F51) },
2894   { PREFIX_TABLE (PREFIX_0F52) },
2895   { PREFIX_TABLE (PREFIX_0F53) },
2896   { "andpX",            { XM, EXx }, PREFIX_OPCODE },
2897   { "andnpX",           { XM, EXx }, PREFIX_OPCODE },
2898   { "orpX",             { XM, EXx }, PREFIX_OPCODE },
2899   { "xorpX",            { XM, EXx }, PREFIX_OPCODE },
2900   /* 58 */
2901   { PREFIX_TABLE (PREFIX_0F58) },
2902   { PREFIX_TABLE (PREFIX_0F59) },
2903   { PREFIX_TABLE (PREFIX_0F5A) },
2904   { PREFIX_TABLE (PREFIX_0F5B) },
2905   { PREFIX_TABLE (PREFIX_0F5C) },
2906   { PREFIX_TABLE (PREFIX_0F5D) },
2907   { PREFIX_TABLE (PREFIX_0F5E) },
2908   { PREFIX_TABLE (PREFIX_0F5F) },
2909   /* 60 */
2910   { PREFIX_TABLE (PREFIX_0F60) },
2911   { PREFIX_TABLE (PREFIX_0F61) },
2912   { PREFIX_TABLE (PREFIX_0F62) },
2913   { "packsswb",         { MX, EM }, PREFIX_OPCODE },
2914   { "pcmpgtb",          { MX, EM }, PREFIX_OPCODE },
2915   { "pcmpgtw",          { MX, EM }, PREFIX_OPCODE },
2916   { "pcmpgtd",          { MX, EM }, PREFIX_OPCODE },
2917   { "packuswb",         { MX, EM }, PREFIX_OPCODE },
2918   /* 68 */
2919   { "punpckhbw",        { MX, EM }, PREFIX_OPCODE },
2920   { "punpckhwd",        { MX, EM }, PREFIX_OPCODE },
2921   { "punpckhdq",        { MX, EM }, PREFIX_OPCODE },
2922   { "packssdw",         { MX, EM }, PREFIX_OPCODE },
2923   { PREFIX_TABLE (PREFIX_0F6C) },
2924   { PREFIX_TABLE (PREFIX_0F6D) },
2925   { "movK",             { MX, Edq }, PREFIX_OPCODE },
2926   { PREFIX_TABLE (PREFIX_0F6F) },
2927   /* 70 */
2928   { PREFIX_TABLE (PREFIX_0F70) },
2929   { REG_TABLE (REG_0F71) },
2930   { REG_TABLE (REG_0F72) },
2931   { REG_TABLE (REG_0F73) },
2932   { "pcmpeqb",          { MX, EM }, PREFIX_OPCODE },
2933   { "pcmpeqw",          { MX, EM }, PREFIX_OPCODE },
2934   { "pcmpeqd",          { MX, EM }, PREFIX_OPCODE },
2935   { "emms",             { XX }, PREFIX_OPCODE },
2936   /* 78 */
2937   { PREFIX_TABLE (PREFIX_0F78) },
2938   { PREFIX_TABLE (PREFIX_0F79) },
2939   { THREE_BYTE_TABLE (THREE_BYTE_0F7A) },
2940   { Bad_Opcode },
2941   { PREFIX_TABLE (PREFIX_0F7C) },
2942   { PREFIX_TABLE (PREFIX_0F7D) },
2943   { PREFIX_TABLE (PREFIX_0F7E) },
2944   { PREFIX_TABLE (PREFIX_0F7F) },
2945   /* 80 */
2946   { "joH",              { Jv, BND, cond_jump_flag }, 0 },
2947   { "jnoH",             { Jv, BND, cond_jump_flag }, 0 },
2948   { "jbH",              { Jv, BND, cond_jump_flag }, 0 },
2949   { "jaeH",             { Jv, BND, cond_jump_flag }, 0 },
2950   { "jeH",              { Jv, BND, cond_jump_flag }, 0 },
2951   { "jneH",             { Jv, BND, cond_jump_flag }, 0 },
2952   { "jbeH",             { Jv, BND, cond_jump_flag }, 0 },
2953   { "jaH",              { Jv, BND, cond_jump_flag }, 0 },
2954   /* 88 */
2955   { "jsH",              { Jv, BND, cond_jump_flag }, 0 },
2956   { "jnsH",             { Jv, BND, cond_jump_flag }, 0 },
2957   { "jpH",              { Jv, BND, cond_jump_flag }, 0 },
2958   { "jnpH",             { Jv, BND, cond_jump_flag }, 0 },
2959   { "jlH",              { Jv, BND, cond_jump_flag }, 0 },
2960   { "jgeH",             { Jv, BND, cond_jump_flag }, 0 },
2961   { "jleH",             { Jv, BND, cond_jump_flag }, 0 },
2962   { "jgH",              { Jv, BND, cond_jump_flag }, 0 },
2963   /* 90 */
2964   { "seto",             { Eb }, 0 },
2965   { "setno",            { Eb }, 0 },
2966   { "setb",             { Eb }, 0 },
2967   { "setae",            { Eb }, 0 },
2968   { "sete",             { Eb }, 0 },
2969   { "setne",            { Eb }, 0 },
2970   { "setbe",            { Eb }, 0 },
2971   { "seta",             { Eb }, 0 },
2972   /* 98 */
2973   { "sets",             { Eb }, 0 },
2974   { "setns",            { Eb }, 0 },
2975   { "setp",             { Eb }, 0 },
2976   { "setnp",            { Eb }, 0 },
2977   { "setl",             { Eb }, 0 },
2978   { "setge",            { Eb }, 0 },
2979   { "setle",            { Eb }, 0 },
2980   { "setg",             { Eb }, 0 },
2981   /* a0 */
2982   { "pushT",            { fs }, 0 },
2983   { "popT",             { fs }, 0 },
2984   { "cpuid",            { XX }, 0 },
2985   { "btS",              { Ev, Gv }, 0 },
2986   { "shldS",            { Ev, Gv, Ib }, 0 },
2987   { "shldS",            { Ev, Gv, CL }, 0 },
2988   { REG_TABLE (REG_0FA6) },
2989   { REG_TABLE (REG_0FA7) },
2990   /* a8 */
2991   { "pushT",            { gs }, 0 },
2992   { "popT",             { gs }, 0 },
2993   { "rsm",              { XX }, 0 },
2994   { "btsS",             { Evh1, Gv }, 0 },
2995   { "shrdS",            { Ev, Gv, Ib }, 0 },
2996   { "shrdS",            { Ev, Gv, CL }, 0 },
2997   { REG_TABLE (REG_0FAE) },
2998   { "imulS",            { Gv, Ev }, 0 },
2999   /* b0 */
3000   { "cmpxchgB",         { Ebh1, Gb }, 0 },
3001   { "cmpxchgS",         { Evh1, Gv }, 0 },
3002   { MOD_TABLE (MOD_0FB2) },
3003   { "btrS",             { Evh1, Gv }, 0 },
3004   { MOD_TABLE (MOD_0FB4) },
3005   { MOD_TABLE (MOD_0FB5) },
3006   { "movz{bR|x}",       { Gv, Eb }, 0 },
3007   { "movz{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
3008   /* b8 */
3009   { PREFIX_TABLE (PREFIX_0FB8) },
3010   { "ud1",              { XX }, 0 },
3011   { REG_TABLE (REG_0FBA) },
3012   { "btcS",             { Evh1, Gv }, 0 },
3013   { PREFIX_TABLE (PREFIX_0FBC) },
3014   { PREFIX_TABLE (PREFIX_0FBD) },
3015   { "movs{bR|x}",       { Gv, Eb }, 0 },
3016   { "movs{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
3017   /* c0 */
3018   { "xaddB",            { Ebh1, Gb }, 0 },
3019   { "xaddS",            { Evh1, Gv }, 0 },
3020   { PREFIX_TABLE (PREFIX_0FC2) },
3021   { MOD_TABLE (MOD_0FC3) },
3022   { "pinsrw",           { MX, Edqw, Ib }, PREFIX_OPCODE },
3023   { "pextrw",           { Gdq, MS, Ib }, PREFIX_OPCODE },
3024   { "shufpX",           { XM, EXx, Ib }, PREFIX_OPCODE },
3025   { REG_TABLE (REG_0FC7) },
3026   /* c8 */
3027   { "bswap",            { RMeAX }, 0 },
3028   { "bswap",            { RMeCX }, 0 },
3029   { "bswap",            { RMeDX }, 0 },
3030   { "bswap",            { RMeBX }, 0 },
3031   { "bswap",            { RMeSP }, 0 },
3032   { "bswap",            { RMeBP }, 0 },
3033   { "bswap",            { RMeSI }, 0 },
3034   { "bswap",            { RMeDI }, 0 },
3035   /* d0 */
3036   { PREFIX_TABLE (PREFIX_0FD0) },
3037   { "psrlw",            { MX, EM }, PREFIX_OPCODE },
3038   { "psrld",            { MX, EM }, PREFIX_OPCODE },
3039   { "psrlq",            { MX, EM }, PREFIX_OPCODE },
3040   { "paddq",            { MX, EM }, PREFIX_OPCODE },
3041   { "pmullw",           { MX, EM }, PREFIX_OPCODE },
3042   { PREFIX_TABLE (PREFIX_0FD6) },
3043   { MOD_TABLE (MOD_0FD7) },
3044   /* d8 */
3045   { "psubusb",          { MX, EM }, PREFIX_OPCODE },
3046   { "psubusw",          { MX, EM }, PREFIX_OPCODE },
3047   { "pminub",           { MX, EM }, PREFIX_OPCODE },
3048   { "pand",             { MX, EM }, PREFIX_OPCODE },
3049   { "paddusb",          { MX, EM }, PREFIX_OPCODE },
3050   { "paddusw",          { MX, EM }, PREFIX_OPCODE },
3051   { "pmaxub",           { MX, EM }, PREFIX_OPCODE },
3052   { "pandn",            { MX, EM }, PREFIX_OPCODE },
3053   /* e0 */
3054   { "pavgb",            { MX, EM }, PREFIX_OPCODE },
3055   { "psraw",            { MX, EM }, PREFIX_OPCODE },
3056   { "psrad",            { MX, EM }, PREFIX_OPCODE },
3057   { "pavgw",            { MX, EM }, PREFIX_OPCODE },
3058   { "pmulhuw",          { MX, EM }, PREFIX_OPCODE },
3059   { "pmulhw",           { MX, EM }, PREFIX_OPCODE },
3060   { PREFIX_TABLE (PREFIX_0FE6) },
3061   { PREFIX_TABLE (PREFIX_0FE7) },
3062   /* e8 */
3063   { "psubsb",           { MX, EM }, PREFIX_OPCODE },
3064   { "psubsw",           { MX, EM }, PREFIX_OPCODE },
3065   { "pminsw",           { MX, EM }, PREFIX_OPCODE },
3066   { "por",              { MX, EM }, PREFIX_OPCODE },
3067   { "paddsb",           { MX, EM }, PREFIX_OPCODE },
3068   { "paddsw",           { MX, EM }, PREFIX_OPCODE },
3069   { "pmaxsw",           { MX, EM }, PREFIX_OPCODE },
3070   { "pxor",             { MX, EM }, PREFIX_OPCODE },
3071   /* f0 */
3072   { PREFIX_TABLE (PREFIX_0FF0) },
3073   { "psllw",            { MX, EM }, PREFIX_OPCODE },
3074   { "pslld",            { MX, EM }, PREFIX_OPCODE },
3075   { "psllq",            { MX, EM }, PREFIX_OPCODE },
3076   { "pmuludq",          { MX, EM }, PREFIX_OPCODE },
3077   { "pmaddwd",          { MX, EM }, PREFIX_OPCODE },
3078   { "psadbw",           { MX, EM }, PREFIX_OPCODE },
3079   { PREFIX_TABLE (PREFIX_0FF7) },
3080   /* f8 */
3081   { "psubb",            { MX, EM }, PREFIX_OPCODE },
3082   { "psubw",            { MX, EM }, PREFIX_OPCODE },
3083   { "psubd",            { MX, EM }, PREFIX_OPCODE },
3084   { "psubq",            { MX, EM }, PREFIX_OPCODE },
3085   { "paddb",            { MX, EM }, PREFIX_OPCODE },
3086   { "paddw",            { MX, EM }, PREFIX_OPCODE },
3087   { "paddd",            { MX, EM }, PREFIX_OPCODE },
3088   { Bad_Opcode },
3089 };
3090
3091 static const unsigned char onebyte_has_modrm[256] = {
3092   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3093   /*       -------------------------------        */
3094   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
3095   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
3096   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
3097   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
3098   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
3099   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
3100   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
3101   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
3102   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
3103   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
3104   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
3105   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
3106   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
3107   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
3108   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
3109   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
3110   /*       -------------------------------        */
3111   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3112 };
3113
3114 static const unsigned char twobyte_has_modrm[256] = {
3115   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3116   /*       -------------------------------        */
3117   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
3118   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
3119   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
3120   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
3121   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
3122   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
3123   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
3124   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
3125   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
3126   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
3127   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
3128   /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
3129   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
3130   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
3131   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
3132   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0  /* ff */
3133   /*       -------------------------------        */
3134   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3135 };
3136
3137 static char obuf[100];
3138 static char *obufp;
3139 static char *mnemonicendp;
3140 static char scratchbuf[100];
3141 static unsigned char *start_codep;
3142 static unsigned char *insn_codep;
3143 static unsigned char *codep;
3144 static unsigned char *end_codep;
3145 static int last_lock_prefix;
3146 static int last_repz_prefix;
3147 static int last_repnz_prefix;
3148 static int last_data_prefix;
3149 static int last_addr_prefix;
3150 static int last_rex_prefix;
3151 static int last_seg_prefix;
3152 static int fwait_prefix;
3153 /* The active segment register prefix.  */
3154 static int active_seg_prefix;
3155 #define MAX_CODE_LENGTH 15
3156 /* We can up to 14 prefixes since the maximum instruction length is
3157    15bytes.  */
3158 static int all_prefixes[MAX_CODE_LENGTH - 1];
3159 static disassemble_info *the_info;
3160 static struct
3161   {
3162     int mod;
3163     int reg;
3164     int rm;
3165   }
3166 modrm;
3167 static unsigned char need_modrm;
3168 static struct
3169   {
3170     int scale;
3171     int index;
3172     int base;
3173   }
3174 sib;
3175 static struct
3176   {
3177     int register_specifier;
3178     int length;
3179     int prefix;
3180     int w;
3181     int evex;
3182     int r;
3183     int v;
3184     int mask_register_specifier;
3185     int zeroing;
3186     int ll;
3187     int b;
3188   }
3189 vex;
3190 static unsigned char need_vex;
3191 static unsigned char need_vex_reg;
3192 static unsigned char vex_w_done;
3193
3194 struct op
3195   {
3196     const char *name;
3197     unsigned int len;
3198   };
3199
3200 /* If we are accessing mod/rm/reg without need_modrm set, then the
3201    values are stale.  Hitting this abort likely indicates that you
3202    need to update onebyte_has_modrm or twobyte_has_modrm.  */
3203 #define MODRM_CHECK  if (!need_modrm) abort ()
3204
3205 static const char **names64;
3206 static const char **names32;
3207 static const char **names16;
3208 static const char **names8;
3209 static const char **names8rex;
3210 static const char **names_seg;
3211 static const char *index64;
3212 static const char *index32;
3213 static const char **index16;
3214 static const char **names_bnd;
3215
3216 static const char *intel_names64[] = {
3217   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3218   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3219 };
3220 static const char *intel_names32[] = {
3221   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3222   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3223 };
3224 static const char *intel_names16[] = {
3225   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3226   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3227 };
3228 static const char *intel_names8[] = {
3229   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3230 };
3231 static const char *intel_names8rex[] = {
3232   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3233   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3234 };
3235 static const char *intel_names_seg[] = {
3236   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3237 };
3238 static const char *intel_index64 = "riz";
3239 static const char *intel_index32 = "eiz";
3240 static const char *intel_index16[] = {
3241   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3242 };
3243
3244 static const char *att_names64[] = {
3245   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3246   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3247 };
3248 static const char *att_names32[] = {
3249   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3250   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3251 };
3252 static const char *att_names16[] = {
3253   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3254   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3255 };
3256 static const char *att_names8[] = {
3257   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3258 };
3259 static const char *att_names8rex[] = {
3260   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3261   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3262 };
3263 static const char *att_names_seg[] = {
3264   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3265 };
3266 static const char *att_index64 = "%riz";
3267 static const char *att_index32 = "%eiz";
3268 static const char *att_index16[] = {
3269   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3270 };
3271
3272 static const char **names_mm;
3273 static const char *intel_names_mm[] = {
3274   "mm0", "mm1", "mm2", "mm3",
3275   "mm4", "mm5", "mm6", "mm7"
3276 };
3277 static const char *att_names_mm[] = {
3278   "%mm0", "%mm1", "%mm2", "%mm3",
3279   "%mm4", "%mm5", "%mm6", "%mm7"
3280 };
3281
3282 static const char *intel_names_bnd[] = {
3283   "bnd0", "bnd1", "bnd2", "bnd3"
3284 };
3285
3286 static const char *att_names_bnd[] = {
3287   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3288 };
3289
3290 static const char **names_xmm;
3291 static const char *intel_names_xmm[] = {
3292   "xmm0", "xmm1", "xmm2", "xmm3",
3293   "xmm4", "xmm5", "xmm6", "xmm7",
3294   "xmm8", "xmm9", "xmm10", "xmm11",
3295   "xmm12", "xmm13", "xmm14", "xmm15",
3296   "xmm16", "xmm17", "xmm18", "xmm19",
3297   "xmm20", "xmm21", "xmm22", "xmm23",
3298   "xmm24", "xmm25", "xmm26", "xmm27",
3299   "xmm28", "xmm29", "xmm30", "xmm31"
3300 };
3301 static const char *att_names_xmm[] = {
3302   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3303   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3304   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3305   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3306   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3307   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3308   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3309   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3310 };
3311
3312 static const char **names_ymm;
3313 static const char *intel_names_ymm[] = {
3314   "ymm0", "ymm1", "ymm2", "ymm3",
3315   "ymm4", "ymm5", "ymm6", "ymm7",
3316   "ymm8", "ymm9", "ymm10", "ymm11",
3317   "ymm12", "ymm13", "ymm14", "ymm15",
3318   "ymm16", "ymm17", "ymm18", "ymm19",
3319   "ymm20", "ymm21", "ymm22", "ymm23",
3320   "ymm24", "ymm25", "ymm26", "ymm27",
3321   "ymm28", "ymm29", "ymm30", "ymm31"
3322 };
3323 static const char *att_names_ymm[] = {
3324   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3325   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3326   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3327   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3328   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3329   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3330   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3331   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3332 };
3333
3334 static const char **names_zmm;
3335 static const char *intel_names_zmm[] = {
3336   "zmm0", "zmm1", "zmm2", "zmm3",
3337   "zmm4", "zmm5", "zmm6", "zmm7",
3338   "zmm8", "zmm9", "zmm10", "zmm11",
3339   "zmm12", "zmm13", "zmm14", "zmm15",
3340   "zmm16", "zmm17", "zmm18", "zmm19",
3341   "zmm20", "zmm21", "zmm22", "zmm23",
3342   "zmm24", "zmm25", "zmm26", "zmm27",
3343   "zmm28", "zmm29", "zmm30", "zmm31"
3344 };
3345 static const char *att_names_zmm[] = {
3346   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3347   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3348   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3349   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3350   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3351   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3352   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3353   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3354 };
3355
3356 static const char **names_mask;
3357 static const char *intel_names_mask[] = {
3358   "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3359 };
3360 static const char *att_names_mask[] = {
3361   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3362 };
3363
3364 static const char *names_rounding[] =
3365 {
3366   "{rn-sae}",
3367   "{rd-sae}",
3368   "{ru-sae}",
3369   "{rz-sae}"
3370 };
3371
3372 static const struct dis386 reg_table[][8] = {
3373   /* REG_80 */
3374   {
3375     { "addA",   { Ebh1, Ib }, 0 },
3376     { "orA",    { Ebh1, Ib }, 0 },
3377     { "adcA",   { Ebh1, Ib }, 0 },
3378     { "sbbA",   { Ebh1, Ib }, 0 },
3379     { "andA",   { Ebh1, Ib }, 0 },
3380     { "subA",   { Ebh1, Ib }, 0 },
3381     { "xorA",   { Ebh1, Ib }, 0 },
3382     { "cmpA",   { Eb, Ib }, 0 },
3383   },
3384   /* REG_81 */
3385   {
3386     { "addQ",   { Evh1, Iv }, 0 },
3387     { "orQ",    { Evh1, Iv }, 0 },
3388     { "adcQ",   { Evh1, Iv }, 0 },
3389     { "sbbQ",   { Evh1, Iv }, 0 },
3390     { "andQ",   { Evh1, Iv }, 0 },
3391     { "subQ",   { Evh1, Iv }, 0 },
3392     { "xorQ",   { Evh1, Iv }, 0 },
3393     { "cmpQ",   { Ev, Iv }, 0 },
3394   },
3395   /* REG_82 */
3396   {
3397     { "addQ",   { Evh1, sIb }, 0 },
3398     { "orQ",    { Evh1, sIb }, 0 },
3399     { "adcQ",   { Evh1, sIb }, 0 },
3400     { "sbbQ",   { Evh1, sIb }, 0 },
3401     { "andQ",   { Evh1, sIb }, 0 },
3402     { "subQ",   { Evh1, sIb }, 0 },
3403     { "xorQ",   { Evh1, sIb }, 0 },
3404     { "cmpQ",   { Ev, sIb }, 0 },
3405   },
3406   /* REG_8F */
3407   {
3408     { "popU",   { stackEv }, 0 },
3409     { XOP_8F_TABLE (XOP_09) },
3410     { Bad_Opcode },
3411     { Bad_Opcode },
3412     { Bad_Opcode },
3413     { XOP_8F_TABLE (XOP_09) },
3414   },
3415   /* REG_C0 */
3416   {
3417     { "rolA",   { Eb, Ib }, 0 },
3418     { "rorA",   { Eb, Ib }, 0 },
3419     { "rclA",   { Eb, Ib }, 0 },
3420     { "rcrA",   { Eb, Ib }, 0 },
3421     { "shlA",   { Eb, Ib }, 0 },
3422     { "shrA",   { Eb, Ib }, 0 },
3423     { Bad_Opcode },
3424     { "sarA",   { Eb, Ib }, 0 },
3425   },
3426   /* REG_C1 */
3427   {
3428     { "rolQ",   { Ev, Ib }, 0 },
3429     { "rorQ",   { Ev, Ib }, 0 },
3430     { "rclQ",   { Ev, Ib }, 0 },
3431     { "rcrQ",   { Ev, Ib }, 0 },
3432     { "shlQ",   { Ev, Ib }, 0 },
3433     { "shrQ",   { Ev, Ib }, 0 },
3434     { Bad_Opcode },
3435     { "sarQ",   { Ev, Ib }, 0 },
3436   },
3437   /* REG_C6 */
3438   {
3439     { "movA",   { Ebh3, Ib }, 0 },
3440     { Bad_Opcode },
3441     { Bad_Opcode },
3442     { Bad_Opcode },
3443     { Bad_Opcode },
3444     { Bad_Opcode },
3445     { Bad_Opcode },
3446     { MOD_TABLE (MOD_C6_REG_7) },
3447   },
3448   /* REG_C7 */
3449   {
3450     { "movQ",   { Evh3, Iv }, 0 },
3451     { Bad_Opcode },
3452     { Bad_Opcode },
3453     { Bad_Opcode },
3454     { Bad_Opcode },
3455     { Bad_Opcode },
3456     { Bad_Opcode },
3457     { MOD_TABLE (MOD_C7_REG_7) },
3458   },
3459   /* REG_D0 */
3460   {
3461     { "rolA",   { Eb, I1 }, 0 },
3462     { "rorA",   { Eb, I1 }, 0 },
3463     { "rclA",   { Eb, I1 }, 0 },
3464     { "rcrA",   { Eb, I1 }, 0 },
3465     { "shlA",   { Eb, I1 }, 0 },
3466     { "shrA",   { Eb, I1 }, 0 },
3467     { Bad_Opcode },
3468     { "sarA",   { Eb, I1 }, 0 },
3469   },
3470   /* REG_D1 */
3471   {
3472     { "rolQ",   { Ev, I1 }, 0 },
3473     { "rorQ",   { Ev, I1 }, 0 },
3474     { "rclQ",   { Ev, I1 }, 0 },
3475     { "rcrQ",   { Ev, I1 }, 0 },
3476     { "shlQ",   { Ev, I1 }, 0 },
3477     { "shrQ",   { Ev, I1 }, 0 },
3478     { Bad_Opcode },
3479     { "sarQ",   { Ev, I1 }, 0 },
3480   },
3481   /* REG_D2 */
3482   {
3483     { "rolA",   { Eb, CL }, 0 },
3484     { "rorA",   { Eb, CL }, 0 },
3485     { "rclA",   { Eb, CL }, 0 },
3486     { "rcrA",   { Eb, CL }, 0 },
3487     { "shlA",   { Eb, CL }, 0 },
3488     { "shrA",   { Eb, CL }, 0 },
3489     { Bad_Opcode },
3490     { "sarA",   { Eb, CL }, 0 },
3491   },
3492   /* REG_D3 */
3493   {
3494     { "rolQ",   { Ev, CL }, 0 },
3495     { "rorQ",   { Ev, CL }, 0 },
3496     { "rclQ",   { Ev, CL }, 0 },
3497     { "rcrQ",   { Ev, CL }, 0 },
3498     { "shlQ",   { Ev, CL }, 0 },
3499     { "shrQ",   { Ev, CL }, 0 },
3500     { Bad_Opcode },
3501     { "sarQ",   { Ev, CL }, 0 },
3502   },
3503   /* REG_F6 */
3504   {
3505     { "testA",  { Eb, Ib }, 0 },
3506     { Bad_Opcode },
3507     { "notA",   { Ebh1 }, 0 },
3508     { "negA",   { Ebh1 }, 0 },
3509     { "mulA",   { Eb }, 0 },    /* Don't print the implicit %al register,  */
3510     { "imulA",  { Eb }, 0 },    /* to distinguish these opcodes from other */
3511     { "divA",   { Eb }, 0 },    /* mul/imul opcodes.  Do the same for div  */
3512     { "idivA",  { Eb }, 0 },    /* and idiv for consistency.               */
3513   },
3514   /* REG_F7 */
3515   {
3516     { "testQ",  { Ev, Iv }, 0 },
3517     { Bad_Opcode },
3518     { "notQ",   { Evh1 }, 0 },
3519     { "negQ",   { Evh1 }, 0 },
3520     { "mulQ",   { Ev }, 0 },    /* Don't print the implicit register.  */
3521     { "imulQ",  { Ev }, 0 },
3522     { "divQ",   { Ev }, 0 },
3523     { "idivQ",  { Ev }, 0 },
3524   },
3525   /* REG_FE */
3526   {
3527     { "incA",   { Ebh1 }, 0 },
3528     { "decA",   { Ebh1 }, 0 },
3529   },
3530   /* REG_FF */
3531   {
3532     { "incQ",   { Evh1 }, 0 },
3533     { "decQ",   { Evh1 }, 0 },
3534     { "call{T|}", { indirEv, BND }, 0 },
3535     { MOD_TABLE (MOD_FF_REG_3) },
3536     { "jmp{T|}", { indirEv, BND }, 0 },
3537     { MOD_TABLE (MOD_FF_REG_5) },
3538     { "pushU",  { stackEv }, 0 },
3539     { Bad_Opcode },
3540   },
3541   /* REG_0F00 */
3542   {
3543     { "sldtD",  { Sv }, 0 },
3544     { "strD",   { Sv }, 0 },
3545     { "lldt",   { Ew }, 0 },
3546     { "ltr",    { Ew }, 0 },
3547     { "verr",   { Ew }, 0 },
3548     { "verw",   { Ew }, 0 },
3549     { Bad_Opcode },
3550     { Bad_Opcode },
3551   },
3552   /* REG_0F01 */
3553   {
3554     { MOD_TABLE (MOD_0F01_REG_0) },
3555     { MOD_TABLE (MOD_0F01_REG_1) },
3556     { MOD_TABLE (MOD_0F01_REG_2) },
3557     { MOD_TABLE (MOD_0F01_REG_3) },
3558     { "smswD",  { Sv }, 0 },
3559     { MOD_TABLE (MOD_0F01_REG_5) },
3560     { "lmsw",   { Ew }, 0 },
3561     { MOD_TABLE (MOD_0F01_REG_7) },
3562   },
3563   /* REG_0F0D */
3564   {
3565     { "prefetch",       { Mb }, 0 },
3566     { "prefetchw",      { Mb }, 0 },
3567     { "prefetchwt1",    { Mb }, 0 },
3568     { "prefetch",       { Mb }, 0 },
3569     { "prefetch",       { Mb }, 0 },
3570     { "prefetch",       { Mb }, 0 },
3571     { "prefetch",       { Mb }, 0 },
3572     { "prefetch",       { Mb }, 0 },
3573   },
3574   /* REG_0F18 */
3575   {
3576     { MOD_TABLE (MOD_0F18_REG_0) },
3577     { MOD_TABLE (MOD_0F18_REG_1) },
3578     { MOD_TABLE (MOD_0F18_REG_2) },
3579     { MOD_TABLE (MOD_0F18_REG_3) },
3580     { MOD_TABLE (MOD_0F18_REG_4) },
3581     { MOD_TABLE (MOD_0F18_REG_5) },
3582     { MOD_TABLE (MOD_0F18_REG_6) },
3583     { MOD_TABLE (MOD_0F18_REG_7) },
3584   },
3585   /* REG_0F71 */
3586   {
3587     { Bad_Opcode },
3588     { Bad_Opcode },
3589     { MOD_TABLE (MOD_0F71_REG_2) },
3590     { Bad_Opcode },
3591     { MOD_TABLE (MOD_0F71_REG_4) },
3592     { Bad_Opcode },
3593     { MOD_TABLE (MOD_0F71_REG_6) },
3594   },
3595   /* REG_0F72 */
3596   {
3597     { Bad_Opcode },
3598     { Bad_Opcode },
3599     { MOD_TABLE (MOD_0F72_REG_2) },
3600     { Bad_Opcode },
3601     { MOD_TABLE (MOD_0F72_REG_4) },
3602     { Bad_Opcode },
3603     { MOD_TABLE (MOD_0F72_REG_6) },
3604   },
3605   /* REG_0F73 */
3606   {
3607     { Bad_Opcode },
3608     { Bad_Opcode },
3609     { MOD_TABLE (MOD_0F73_REG_2) },
3610     { MOD_TABLE (MOD_0F73_REG_3) },
3611     { Bad_Opcode },
3612     { Bad_Opcode },
3613     { MOD_TABLE (MOD_0F73_REG_6) },
3614     { MOD_TABLE (MOD_0F73_REG_7) },
3615   },
3616   /* REG_0FA6 */
3617   {
3618     { "montmul",        { { OP_0f07, 0 } }, 0 },
3619     { "xsha1",          { { OP_0f07, 0 } }, 0 },
3620     { "xsha256",        { { OP_0f07, 0 } }, 0 },
3621   },
3622   /* REG_0FA7 */
3623   {
3624     { "xstore-rng",     { { OP_0f07, 0 } }, 0 },
3625     { "xcrypt-ecb",     { { OP_0f07, 0 } }, 0 },
3626     { "xcrypt-cbc",     { { OP_0f07, 0 } }, 0 },
3627     { "xcrypt-ctr",     { { OP_0f07, 0 } }, 0 },
3628     { "xcrypt-cfb",     { { OP_0f07, 0 } }, 0 },
3629     { "xcrypt-ofb",     { { OP_0f07, 0 } }, 0 },
3630   },
3631   /* REG_0FAE */
3632   {
3633     { MOD_TABLE (MOD_0FAE_REG_0) },
3634     { MOD_TABLE (MOD_0FAE_REG_1) },
3635     { MOD_TABLE (MOD_0FAE_REG_2) },
3636     { MOD_TABLE (MOD_0FAE_REG_3) },
3637     { MOD_TABLE (MOD_0FAE_REG_4) },
3638     { MOD_TABLE (MOD_0FAE_REG_5) },
3639     { MOD_TABLE (MOD_0FAE_REG_6) },
3640     { MOD_TABLE (MOD_0FAE_REG_7) },
3641   },
3642   /* REG_0FBA */
3643   {
3644     { Bad_Opcode },
3645     { Bad_Opcode },
3646     { Bad_Opcode },
3647     { Bad_Opcode },
3648     { "btQ",    { Ev, Ib }, 0 },
3649     { "btsQ",   { Evh1, Ib }, 0 },
3650     { "btrQ",   { Evh1, Ib }, 0 },
3651     { "btcQ",   { Evh1, Ib }, 0 },
3652   },
3653   /* REG_0FC7 */
3654   {
3655     { Bad_Opcode },
3656     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
3657     { Bad_Opcode },
3658     { MOD_TABLE (MOD_0FC7_REG_3) },
3659     { MOD_TABLE (MOD_0FC7_REG_4) },
3660     { MOD_TABLE (MOD_0FC7_REG_5) },
3661     { MOD_TABLE (MOD_0FC7_REG_6) },
3662     { MOD_TABLE (MOD_0FC7_REG_7) },
3663   },
3664   /* REG_VEX_0F71 */
3665   {
3666     { Bad_Opcode },
3667     { Bad_Opcode },
3668     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3669     { Bad_Opcode },
3670     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3671     { Bad_Opcode },
3672     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3673   },
3674   /* REG_VEX_0F72 */
3675   {
3676     { Bad_Opcode },
3677     { Bad_Opcode },
3678     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3679     { Bad_Opcode },
3680     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3681     { Bad_Opcode },
3682     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3683   },
3684   /* REG_VEX_0F73 */
3685   {
3686     { Bad_Opcode },
3687     { Bad_Opcode },
3688     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3689     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3690     { Bad_Opcode },
3691     { Bad_Opcode },
3692     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3693     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3694   },
3695   /* REG_VEX_0FAE */
3696   {
3697     { Bad_Opcode },
3698     { Bad_Opcode },
3699     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3700     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3701   },
3702   /* REG_VEX_0F38F3 */
3703   {
3704     { Bad_Opcode },
3705     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3706     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3707     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3708   },
3709   /* REG_XOP_LWPCB */
3710   {
3711     { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3712     { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3713   },
3714   /* REG_XOP_LWP */
3715   {
3716     { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3717     { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3718   },
3719   /* REG_XOP_TBM_01 */
3720   {
3721     { Bad_Opcode },
3722     { "blcfill",        { { OP_LWP_E, 0 }, Ev }, 0 },
3723     { "blsfill",        { { OP_LWP_E, 0 }, Ev }, 0 },
3724     { "blcs",   { { OP_LWP_E, 0 }, Ev }, 0 },
3725     { "tzmsk",  { { OP_LWP_E, 0 }, Ev }, 0 },
3726     { "blcic",  { { OP_LWP_E, 0 }, Ev }, 0 },
3727     { "blsic",  { { OP_LWP_E, 0 }, Ev }, 0 },
3728     { "t1mskc", { { OP_LWP_E, 0 }, Ev }, 0 },
3729   },
3730   /* REG_XOP_TBM_02 */
3731   {
3732     { Bad_Opcode },
3733     { "blcmsk", { { OP_LWP_E, 0 }, Ev }, 0 },
3734     { Bad_Opcode },
3735     { Bad_Opcode },
3736     { Bad_Opcode },
3737     { Bad_Opcode },
3738     { "blci",   { { OP_LWP_E, 0 }, Ev }, 0 },
3739   },
3740 #define NEED_REG_TABLE
3741 #include "i386-dis-evex.h"
3742 #undef NEED_REG_TABLE
3743 };
3744
3745 static const struct dis386 prefix_table[][4] = {
3746   /* PREFIX_90 */
3747   {
3748     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3749     { "pause", { XX }, 0 },
3750     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3751     { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3752   },
3753
3754   /* PREFIX_0F10 */
3755   {
3756     { "movups", { XM, EXx }, PREFIX_OPCODE },
3757     { "movss",  { XM, EXd }, PREFIX_OPCODE },
3758     { "movupd", { XM, EXx }, PREFIX_OPCODE },
3759     { "movsd",  { XM, EXq }, PREFIX_OPCODE },
3760   },
3761
3762   /* PREFIX_0F11 */
3763   {
3764     { "movups", { EXxS, XM }, PREFIX_OPCODE },
3765     { "movss",  { EXdS, XM }, PREFIX_OPCODE },
3766     { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3767     { "movsd",  { EXqS, XM }, PREFIX_OPCODE },
3768   },
3769
3770   /* PREFIX_0F12 */
3771   {
3772     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3773     { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3774     { "movlpd", { XM, EXq }, PREFIX_OPCODE },
3775     { "movddup", { XM, EXq }, PREFIX_OPCODE },
3776   },
3777
3778   /* PREFIX_0F16 */
3779   {
3780     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3781     { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3782     { "movhpd", { XM, EXq }, PREFIX_OPCODE },
3783   },
3784
3785   /* PREFIX_0F1A */
3786   {
3787     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3788     { "bndcl",  { Gbnd, Ev_bnd }, 0 },
3789     { "bndmov", { Gbnd, Ebnd }, 0 },
3790     { "bndcu",  { Gbnd, Ev_bnd }, 0 },
3791   },
3792
3793   /* PREFIX_0F1B */
3794   {
3795     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3796     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3797     { "bndmov", { Ebnd, Gbnd }, 0 },
3798     { "bndcn",  { Gbnd, Ev_bnd }, 0 },
3799   },
3800
3801   /* PREFIX_0F2A */
3802   {
3803     { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3804     { "cvtsi2ss%LQ", { XM, Ev }, PREFIX_OPCODE },
3805     { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3806     { "cvtsi2sd%LQ", { XM, Ev }, 0 },
3807   },
3808
3809   /* PREFIX_0F2B */
3810   {
3811     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3812     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3813     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3814     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3815   },
3816
3817   /* PREFIX_0F2C */
3818   {
3819     { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3820     { "cvttss2siY", { Gv, EXd }, PREFIX_OPCODE },
3821     { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3822     { "cvttsd2siY", { Gv, EXq }, PREFIX_OPCODE },
3823   },
3824
3825   /* PREFIX_0F2D */
3826   {
3827     { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3828     { "cvtss2siY", { Gv, EXd }, PREFIX_OPCODE },
3829     { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3830     { "cvtsd2siY", { Gv, EXq }, PREFIX_OPCODE },
3831   },
3832
3833   /* PREFIX_0F2E */
3834   {
3835     { "ucomiss",{ XM, EXd }, 0 },
3836     { Bad_Opcode },
3837     { "ucomisd",{ XM, EXq }, 0 },
3838   },
3839
3840   /* PREFIX_0F2F */
3841   {
3842     { "comiss", { XM, EXd }, 0 },
3843     { Bad_Opcode },
3844     { "comisd", { XM, EXq }, 0 },
3845   },
3846
3847   /* PREFIX_0F51 */
3848   {
3849     { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3850     { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3851     { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3852     { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3853   },
3854
3855   /* PREFIX_0F52 */
3856   {
3857     { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3858     { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3859   },
3860
3861   /* PREFIX_0F53 */
3862   {
3863     { "rcpps",  { XM, EXx }, PREFIX_OPCODE },
3864     { "rcpss",  { XM, EXd }, PREFIX_OPCODE },
3865   },
3866
3867   /* PREFIX_0F58 */
3868   {
3869     { "addps", { XM, EXx }, PREFIX_OPCODE },
3870     { "addss", { XM, EXd }, PREFIX_OPCODE },
3871     { "addpd", { XM, EXx }, PREFIX_OPCODE },
3872     { "addsd", { XM, EXq }, PREFIX_OPCODE },
3873   },
3874
3875   /* PREFIX_0F59 */
3876   {
3877     { "mulps",  { XM, EXx }, PREFIX_OPCODE },
3878     { "mulss",  { XM, EXd }, PREFIX_OPCODE },
3879     { "mulpd",  { XM, EXx }, PREFIX_OPCODE },
3880     { "mulsd",  { XM, EXq }, PREFIX_OPCODE },
3881   },
3882
3883   /* PREFIX_0F5A */
3884   {
3885     { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3886     { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3887     { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3888     { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3889   },
3890
3891   /* PREFIX_0F5B */
3892   {
3893     { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3894     { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3895     { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3896   },
3897
3898   /* PREFIX_0F5C */
3899   {
3900     { "subps",  { XM, EXx }, PREFIX_OPCODE },
3901     { "subss",  { XM, EXd }, PREFIX_OPCODE },
3902     { "subpd",  { XM, EXx }, PREFIX_OPCODE },
3903     { "subsd",  { XM, EXq }, PREFIX_OPCODE },
3904   },
3905
3906   /* PREFIX_0F5D */
3907   {
3908     { "minps",  { XM, EXx }, PREFIX_OPCODE },
3909     { "minss",  { XM, EXd }, PREFIX_OPCODE },
3910     { "minpd",  { XM, EXx }, PREFIX_OPCODE },
3911     { "minsd",  { XM, EXq }, PREFIX_OPCODE },
3912   },
3913
3914   /* PREFIX_0F5E */
3915   {
3916     { "divps",  { XM, EXx }, PREFIX_OPCODE },
3917     { "divss",  { XM, EXd }, PREFIX_OPCODE },
3918     { "divpd",  { XM, EXx }, PREFIX_OPCODE },
3919     { "divsd",  { XM, EXq }, PREFIX_OPCODE },
3920   },
3921
3922   /* PREFIX_0F5F */
3923   {
3924     { "maxps",  { XM, EXx }, PREFIX_OPCODE },
3925     { "maxss",  { XM, EXd }, PREFIX_OPCODE },
3926     { "maxpd",  { XM, EXx }, PREFIX_OPCODE },
3927     { "maxsd",  { XM, EXq }, PREFIX_OPCODE },
3928   },
3929
3930   /* PREFIX_0F60 */
3931   {
3932     { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3933     { Bad_Opcode },
3934     { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3935   },
3936
3937   /* PREFIX_0F61 */
3938   {
3939     { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3940     { Bad_Opcode },
3941     { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3942   },
3943
3944   /* PREFIX_0F62 */
3945   {
3946     { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3947     { Bad_Opcode },
3948     { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3949   },
3950
3951   /* PREFIX_0F6C */
3952   {
3953     { Bad_Opcode },
3954     { Bad_Opcode },
3955     { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE },
3956   },
3957
3958   /* PREFIX_0F6D */
3959   {
3960     { Bad_Opcode },
3961     { Bad_Opcode },
3962     { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE },
3963   },
3964
3965   /* PREFIX_0F6F */
3966   {
3967     { "movq",   { MX, EM }, PREFIX_OPCODE },
3968     { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3969     { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3970   },
3971
3972   /* PREFIX_0F70 */
3973   {
3974     { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3975     { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3976     { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3977     { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3978   },
3979
3980   /* PREFIX_0F73_REG_3 */
3981   {
3982     { Bad_Opcode },
3983     { Bad_Opcode },
3984     { "psrldq", { XS, Ib }, 0 },
3985   },
3986
3987   /* PREFIX_0F73_REG_7 */
3988   {
3989     { Bad_Opcode },
3990     { Bad_Opcode },
3991     { "pslldq", { XS, Ib }, 0 },
3992   },
3993
3994   /* PREFIX_0F78 */
3995   {
3996     {"vmread",  { Em, Gm }, 0 },
3997     { Bad_Opcode },
3998     {"extrq",   { XS, Ib, Ib }, 0 },
3999     {"insertq", { XM, XS, Ib, Ib }, 0 },
4000   },
4001
4002   /* PREFIX_0F79 */
4003   {
4004     {"vmwrite", { Gm, Em }, 0 },
4005     { Bad_Opcode },
4006     {"extrq",   { XM, XS }, 0 },
4007     {"insertq", { XM, XS }, 0 },
4008   },
4009
4010   /* PREFIX_0F7C */
4011   {
4012     { Bad_Opcode },
4013     { Bad_Opcode },
4014     { "haddpd", { XM, EXx }, PREFIX_OPCODE },
4015     { "haddps", { XM, EXx }, PREFIX_OPCODE },
4016   },
4017
4018   /* PREFIX_0F7D */
4019   {
4020     { Bad_Opcode },
4021     { Bad_Opcode },
4022     { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
4023     { "hsubps", { XM, EXx }, PREFIX_OPCODE },
4024   },
4025
4026   /* PREFIX_0F7E */
4027   {
4028     { "movK",   { Edq, MX }, PREFIX_OPCODE },
4029     { "movq",   { XM, EXq }, PREFIX_OPCODE },
4030     { "movK",   { Edq, XM }, PREFIX_OPCODE },
4031   },
4032
4033   /* PREFIX_0F7F */
4034   {
4035     { "movq",   { EMS, MX }, PREFIX_OPCODE },
4036     { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
4037     { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
4038   },
4039
4040   /* PREFIX_0FAE_REG_0 */
4041   {
4042     { Bad_Opcode },
4043     { "rdfsbase", { Ev }, 0 },
4044   },
4045
4046   /* PREFIX_0FAE_REG_1 */
4047   {
4048     { Bad_Opcode },
4049     { "rdgsbase", { Ev }, 0 },
4050   },
4051
4052   /* PREFIX_0FAE_REG_2 */
4053   {
4054     { Bad_Opcode },
4055     { "wrfsbase", { Ev }, 0 },
4056   },
4057
4058   /* PREFIX_0FAE_REG_3 */
4059   {
4060     { Bad_Opcode },
4061     { "wrgsbase", { Ev }, 0 },
4062   },
4063
4064   /* PREFIX_0FAE_REG_6 */
4065   {
4066     { "xsaveopt",      { FXSAVE }, 0 },
4067     { Bad_Opcode },
4068     { "clwb",   { Mb }, 0 },
4069   },
4070
4071   /* PREFIX_0FAE_REG_7 */
4072   {
4073     { "clflush",        { Mb }, 0 },
4074     { Bad_Opcode },
4075     { "clflushopt",     { Mb }, 0 },
4076   },
4077
4078   /* PREFIX_RM_0_0FAE_REG_7 */
4079   {
4080     { "sfence",         { Skip_MODRM }, 0 },
4081     { Bad_Opcode },
4082     { "pcommit",                { Skip_MODRM }, 0 },
4083   },
4084
4085   /* PREFIX_0FB8 */
4086   {
4087     { Bad_Opcode },
4088     { "popcntS", { Gv, Ev }, 0 },
4089   },
4090
4091   /* PREFIX_0FBC */
4092   {
4093     { "bsfS",   { Gv, Ev }, 0 },
4094     { "tzcntS", { Gv, Ev }, 0 },
4095     { "bsfS",   { Gv, Ev }, 0 },
4096   },
4097
4098   /* PREFIX_0FBD */
4099   {
4100     { "bsrS",   { Gv, Ev }, 0 },
4101     { "lzcntS", { Gv, Ev }, 0 },
4102     { "bsrS",   { Gv, Ev }, 0 },
4103   },
4104
4105   /* PREFIX_0FC2 */
4106   {
4107     { "cmpps",  { XM, EXx, CMP }, PREFIX_OPCODE },
4108     { "cmpss",  { XM, EXd, CMP }, PREFIX_OPCODE },
4109     { "cmppd",  { XM, EXx, CMP }, PREFIX_OPCODE },
4110     { "cmpsd",  { XM, EXq, CMP }, PREFIX_OPCODE },
4111   },
4112
4113   /* PREFIX_MOD_0_0FC3 */
4114   {
4115     { "movntiS", { Ev, Gv }, PREFIX_OPCODE },
4116   },
4117
4118   /* PREFIX_MOD_0_0FC7_REG_6 */
4119   {
4120     { "vmptrld",{ Mq }, 0 },
4121     { "vmxon",  { Mq }, 0 },
4122     { "vmclear",{ Mq }, 0 },
4123   },
4124
4125   /* PREFIX_MOD_3_0FC7_REG_6 */
4126   {
4127     { "rdrand", { Ev }, 0 },
4128     { Bad_Opcode },
4129     { "rdrand", { Ev }, 0 }
4130   },
4131
4132   /* PREFIX_MOD_3_0FC7_REG_7 */
4133   {
4134     { "rdseed", { Ev }, 0 },
4135     { "rdpid",  { Em }, 0 },
4136     { "rdseed", { Ev }, 0 },
4137   },
4138
4139   /* PREFIX_0FD0 */
4140   {
4141     { Bad_Opcode },
4142     { Bad_Opcode },
4143     { "addsubpd", { XM, EXx }, 0 },
4144     { "addsubps", { XM, EXx }, 0 },
4145   },
4146
4147   /* PREFIX_0FD6 */
4148   {
4149     { Bad_Opcode },
4150     { "movq2dq",{ XM, MS }, 0 },
4151     { "movq",   { EXqS, XM }, 0 },
4152     { "movdq2q",{ MX, XS }, 0 },
4153   },
4154
4155   /* PREFIX_0FE6 */
4156   {
4157     { Bad_Opcode },
4158     { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
4159     { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
4160     { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
4161   },
4162
4163   /* PREFIX_0FE7 */
4164   {
4165     { "movntq", { Mq, MX }, PREFIX_OPCODE },
4166     { Bad_Opcode },
4167     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
4168   },
4169
4170   /* PREFIX_0FF0 */
4171   {
4172     { Bad_Opcode },
4173     { Bad_Opcode },
4174     { Bad_Opcode },
4175     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4176   },
4177
4178   /* PREFIX_0FF7 */
4179   {
4180     { "maskmovq", { MX, MS }, PREFIX_OPCODE },
4181     { Bad_Opcode },
4182     { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
4183   },
4184
4185   /* PREFIX_0F3810 */
4186   {
4187     { Bad_Opcode },
4188     { Bad_Opcode },
4189     { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4190   },
4191
4192   /* PREFIX_0F3814 */
4193   {
4194     { Bad_Opcode },
4195     { Bad_Opcode },
4196     { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4197   },
4198
4199   /* PREFIX_0F3815 */
4200   {
4201     { Bad_Opcode },
4202     { Bad_Opcode },
4203     { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4204   },
4205
4206   /* PREFIX_0F3817 */
4207   {
4208     { Bad_Opcode },
4209     { Bad_Opcode },
4210     { "ptest",  { XM, EXx }, PREFIX_OPCODE },
4211   },
4212
4213   /* PREFIX_0F3820 */
4214   {
4215     { Bad_Opcode },
4216     { Bad_Opcode },
4217     { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE },
4218   },
4219
4220   /* PREFIX_0F3821 */
4221   {
4222     { Bad_Opcode },
4223     { Bad_Opcode },
4224     { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE },
4225   },
4226
4227   /* PREFIX_0F3822 */
4228   {
4229     { Bad_Opcode },
4230     { Bad_Opcode },
4231     { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE },
4232   },
4233
4234   /* PREFIX_0F3823 */
4235   {
4236     { Bad_Opcode },
4237     { Bad_Opcode },
4238     { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE },
4239   },
4240
4241   /* PREFIX_0F3824 */
4242   {
4243     { Bad_Opcode },
4244     { Bad_Opcode },
4245     { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE },
4246   },
4247
4248   /* PREFIX_0F3825 */
4249   {
4250     { Bad_Opcode },
4251     { Bad_Opcode },
4252     { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE },
4253   },
4254
4255   /* PREFIX_0F3828 */
4256   {
4257     { Bad_Opcode },
4258     { Bad_Opcode },
4259     { "pmuldq", { XM, EXx }, PREFIX_OPCODE },
4260   },
4261
4262   /* PREFIX_0F3829 */
4263   {
4264     { Bad_Opcode },
4265     { Bad_Opcode },
4266     { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE },
4267   },
4268
4269   /* PREFIX_0F382A */
4270   {
4271     { Bad_Opcode },
4272     { Bad_Opcode },
4273     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4274   },
4275
4276   /* PREFIX_0F382B */
4277   {
4278     { Bad_Opcode },
4279     { Bad_Opcode },
4280     { "packusdw", { XM, EXx }, PREFIX_OPCODE },
4281   },
4282
4283   /* PREFIX_0F3830 */
4284   {
4285     { Bad_Opcode },
4286     { Bad_Opcode },
4287     { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE },
4288   },
4289
4290   /* PREFIX_0F3831 */
4291   {
4292     { Bad_Opcode },
4293     { Bad_Opcode },
4294     { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE },
4295   },
4296
4297   /* PREFIX_0F3832 */
4298   {
4299     { Bad_Opcode },
4300     { Bad_Opcode },
4301     { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE },
4302   },
4303
4304   /* PREFIX_0F3833 */
4305   {
4306     { Bad_Opcode },
4307     { Bad_Opcode },
4308     { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE },
4309   },
4310
4311   /* PREFIX_0F3834 */
4312   {
4313     { Bad_Opcode },
4314     { Bad_Opcode },
4315     { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE },
4316   },
4317
4318   /* PREFIX_0F3835 */
4319   {
4320     { Bad_Opcode },
4321     { Bad_Opcode },
4322     { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE },
4323   },
4324
4325   /* PREFIX_0F3837 */
4326   {
4327     { Bad_Opcode },
4328     { Bad_Opcode },
4329     { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE },
4330   },
4331
4332   /* PREFIX_0F3838 */
4333   {
4334     { Bad_Opcode },
4335     { Bad_Opcode },
4336     { "pminsb", { XM, EXx }, PREFIX_OPCODE },
4337   },
4338
4339   /* PREFIX_0F3839 */
4340   {
4341     { Bad_Opcode },
4342     { Bad_Opcode },
4343     { "pminsd", { XM, EXx }, PREFIX_OPCODE },
4344   },
4345
4346   /* PREFIX_0F383A */
4347   {
4348     { Bad_Opcode },
4349     { Bad_Opcode },
4350     { "pminuw", { XM, EXx }, PREFIX_OPCODE },
4351   },
4352
4353   /* PREFIX_0F383B */
4354   {
4355     { Bad_Opcode },
4356     { Bad_Opcode },
4357     { "pminud", { XM, EXx }, PREFIX_OPCODE },
4358   },
4359
4360   /* PREFIX_0F383C */
4361   {
4362     { Bad_Opcode },
4363     { Bad_Opcode },
4364     { "pmaxsb", { XM, EXx }, PREFIX_OPCODE },
4365   },
4366
4367   /* PREFIX_0F383D */
4368   {
4369     { Bad_Opcode },
4370     { Bad_Opcode },
4371     { "pmaxsd", { XM, EXx }, PREFIX_OPCODE },
4372   },
4373
4374   /* PREFIX_0F383E */
4375   {
4376     { Bad_Opcode },
4377     { Bad_Opcode },
4378     { "pmaxuw", { XM, EXx }, PREFIX_OPCODE },
4379   },
4380
4381   /* PREFIX_0F383F */
4382   {
4383     { Bad_Opcode },
4384     { Bad_Opcode },
4385     { "pmaxud", { XM, EXx }, PREFIX_OPCODE },
4386   },
4387
4388   /* PREFIX_0F3840 */
4389   {
4390     { Bad_Opcode },
4391     { Bad_Opcode },
4392     { "pmulld", { XM, EXx }, PREFIX_OPCODE },
4393   },
4394
4395   /* PREFIX_0F3841 */
4396   {
4397     { Bad_Opcode },
4398     { Bad_Opcode },
4399     { "phminposuw", { XM, EXx }, PREFIX_OPCODE },
4400   },
4401
4402   /* PREFIX_0F3880 */
4403   {
4404     { Bad_Opcode },
4405     { Bad_Opcode },
4406     { "invept", { Gm, Mo }, PREFIX_OPCODE },
4407   },
4408
4409   /* PREFIX_0F3881 */
4410   {
4411     { Bad_Opcode },
4412     { Bad_Opcode },
4413     { "invvpid", { Gm, Mo }, PREFIX_OPCODE },
4414   },
4415
4416   /* PREFIX_0F3882 */
4417   {
4418     { Bad_Opcode },
4419     { Bad_Opcode },
4420     { "invpcid", { Gm, M }, PREFIX_OPCODE },
4421   },
4422
4423   /* PREFIX_0F38C8 */
4424   {
4425     { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4426   },
4427
4428   /* PREFIX_0F38C9 */
4429   {
4430     { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4431   },
4432
4433   /* PREFIX_0F38CA */
4434   {
4435     { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4436   },
4437
4438   /* PREFIX_0F38CB */
4439   {
4440     { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4441   },
4442
4443   /* PREFIX_0F38CC */
4444   {
4445     { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4446   },
4447
4448   /* PREFIX_0F38CD */
4449   {
4450     { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4451   },
4452
4453   /* PREFIX_0F38DB */
4454   {
4455     { Bad_Opcode },
4456     { Bad_Opcode },
4457     { "aesimc", { XM, EXx }, PREFIX_OPCODE },
4458   },
4459
4460   /* PREFIX_0F38DC */
4461   {
4462     { Bad_Opcode },
4463     { Bad_Opcode },
4464     { "aesenc", { XM, EXx }, PREFIX_OPCODE },
4465   },
4466
4467   /* PREFIX_0F38DD */
4468   {
4469     { Bad_Opcode },
4470     { Bad_Opcode },
4471     { "aesenclast", { XM, EXx }, PREFIX_OPCODE },
4472   },
4473
4474   /* PREFIX_0F38DE */
4475   {
4476     { Bad_Opcode },
4477     { Bad_Opcode },
4478     { "aesdec", { XM, EXx }, PREFIX_OPCODE },
4479   },
4480
4481   /* PREFIX_0F38DF */
4482   {
4483     { Bad_Opcode },
4484     { Bad_Opcode },
4485     { "aesdeclast", { XM, EXx }, PREFIX_OPCODE },
4486   },
4487
4488   /* PREFIX_0F38F0 */
4489   {
4490     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4491     { Bad_Opcode },
4492     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4493     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE },
4494   },
4495
4496   /* PREFIX_0F38F1 */
4497   {
4498     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4499     { Bad_Opcode },
4500     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4501     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE },
4502   },
4503
4504   /* PREFIX_0F38F6 */
4505   {
4506     { Bad_Opcode },
4507     { "adoxS",  { Gdq, Edq}, PREFIX_OPCODE },
4508     { "adcxS",  { Gdq, Edq}, PREFIX_OPCODE },
4509     { Bad_Opcode },
4510   },
4511
4512   /* PREFIX_0F3A08 */
4513   {
4514     { Bad_Opcode },
4515     { Bad_Opcode },
4516     { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE },
4517   },
4518
4519   /* PREFIX_0F3A09 */
4520   {
4521     { Bad_Opcode },
4522     { Bad_Opcode },
4523     { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4524   },
4525
4526   /* PREFIX_0F3A0A */
4527   {
4528     { Bad_Opcode },
4529     { Bad_Opcode },
4530     { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE },
4531   },
4532
4533   /* PREFIX_0F3A0B */
4534   {
4535     { Bad_Opcode },
4536     { Bad_Opcode },
4537     { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE },
4538   },
4539
4540   /* PREFIX_0F3A0C */
4541   {
4542     { Bad_Opcode },
4543     { Bad_Opcode },
4544     { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE },
4545   },
4546
4547   /* PREFIX_0F3A0D */
4548   {
4549     { Bad_Opcode },
4550     { Bad_Opcode },
4551     { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4552   },
4553
4554   /* PREFIX_0F3A0E */
4555   {
4556     { Bad_Opcode },
4557     { Bad_Opcode },
4558     { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE },
4559   },
4560
4561   /* PREFIX_0F3A14 */
4562   {
4563     { Bad_Opcode },
4564     { Bad_Opcode },
4565     { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE },
4566   },
4567
4568   /* PREFIX_0F3A15 */
4569   {
4570     { Bad_Opcode },
4571     { Bad_Opcode },
4572     { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE },
4573   },
4574
4575   /* PREFIX_0F3A16 */
4576   {
4577     { Bad_Opcode },
4578     { Bad_Opcode },
4579     { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE },
4580   },
4581
4582   /* PREFIX_0F3A17 */
4583   {
4584     { Bad_Opcode },
4585     { Bad_Opcode },
4586     { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE },
4587   },
4588
4589   /* PREFIX_0F3A20 */
4590   {
4591     { Bad_Opcode },
4592     { Bad_Opcode },
4593     { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE },
4594   },
4595
4596   /* PREFIX_0F3A21 */
4597   {
4598     { Bad_Opcode },
4599     { Bad_Opcode },
4600     { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE },
4601   },
4602
4603   /* PREFIX_0F3A22 */
4604   {
4605     { Bad_Opcode },
4606     { Bad_Opcode },
4607     { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE },
4608   },
4609
4610   /* PREFIX_0F3A40 */
4611   {
4612     { Bad_Opcode },
4613     { Bad_Opcode },
4614     { "dpps",   { XM, EXx, Ib }, PREFIX_OPCODE },
4615   },
4616
4617   /* PREFIX_0F3A41 */
4618   {
4619     { Bad_Opcode },
4620     { Bad_Opcode },
4621     { "dppd",   { XM, EXx, Ib }, PREFIX_OPCODE },
4622   },
4623
4624   /* PREFIX_0F3A42 */
4625   {
4626     { Bad_Opcode },
4627     { Bad_Opcode },
4628     { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE },
4629   },
4630
4631   /* PREFIX_0F3A44 */
4632   {
4633     { Bad_Opcode },
4634     { Bad_Opcode },
4635     { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE },
4636   },
4637
4638   /* PREFIX_0F3A60 */
4639   {
4640     { Bad_Opcode },
4641     { Bad_Opcode },
4642     { "pcmpestrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4643   },
4644
4645   /* PREFIX_0F3A61 */
4646   {
4647     { Bad_Opcode },
4648     { Bad_Opcode },
4649     { "pcmpestri", { XM, EXx, Ib }, PREFIX_OPCODE },
4650   },
4651
4652   /* PREFIX_0F3A62 */
4653   {
4654     { Bad_Opcode },
4655     { Bad_Opcode },
4656     { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4657   },
4658
4659   /* PREFIX_0F3A63 */
4660   {
4661     { Bad_Opcode },
4662     { Bad_Opcode },
4663     { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE },
4664   },
4665
4666   /* PREFIX_0F3ACC */
4667   {
4668     { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4669   },
4670
4671   /* PREFIX_0F3ADF */
4672   {
4673     { Bad_Opcode },
4674     { Bad_Opcode },
4675     { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE },
4676   },
4677
4678   /* PREFIX_VEX_0F10 */
4679   {
4680     { VEX_W_TABLE (VEX_W_0F10_P_0) },
4681     { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) },
4682     { VEX_W_TABLE (VEX_W_0F10_P_2) },
4683     { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) },
4684   },
4685
4686   /* PREFIX_VEX_0F11 */
4687   {
4688     { VEX_W_TABLE (VEX_W_0F11_P_0) },
4689     { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) },
4690     { VEX_W_TABLE (VEX_W_0F11_P_2) },
4691     { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) },
4692   },
4693
4694   /* PREFIX_VEX_0F12 */
4695   {
4696     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4697     { VEX_W_TABLE (VEX_W_0F12_P_1) },
4698     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
4699     { VEX_W_TABLE (VEX_W_0F12_P_3) },
4700   },
4701
4702   /* PREFIX_VEX_0F16 */
4703   {
4704     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4705     { VEX_W_TABLE (VEX_W_0F16_P_1) },
4706     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
4707   },
4708
4709   /* PREFIX_VEX_0F2A */
4710   {
4711     { Bad_Opcode },
4712     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) },
4713     { Bad_Opcode },
4714     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) },
4715   },
4716
4717   /* PREFIX_VEX_0F2C */
4718   {
4719     { Bad_Opcode },
4720     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) },
4721     { Bad_Opcode },
4722     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) },
4723   },
4724
4725   /* PREFIX_VEX_0F2D */
4726   {
4727     { Bad_Opcode },
4728     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) },
4729     { Bad_Opcode },
4730     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) },
4731   },
4732
4733   /* PREFIX_VEX_0F2E */
4734   {
4735     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) },
4736     { Bad_Opcode },
4737     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) },
4738   },
4739
4740   /* PREFIX_VEX_0F2F */
4741   {
4742     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) },
4743     { Bad_Opcode },
4744     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) },
4745   },
4746
4747   /* PREFIX_VEX_0F41 */
4748   {
4749     { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4750     { Bad_Opcode },
4751     { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4752   },
4753
4754   /* PREFIX_VEX_0F42 */
4755   {
4756     { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4757     { Bad_Opcode },
4758     { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4759   },
4760
4761   /* PREFIX_VEX_0F44 */
4762   {
4763     { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4764     { Bad_Opcode },
4765     { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4766   },
4767
4768   /* PREFIX_VEX_0F45 */
4769   {
4770     { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4771     { Bad_Opcode },
4772     { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4773   },
4774
4775   /* PREFIX_VEX_0F46 */
4776   {
4777     { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4778     { Bad_Opcode },
4779     { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4780   },
4781
4782   /* PREFIX_VEX_0F47 */
4783   {
4784     { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4785     { Bad_Opcode },
4786     { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
4787   },
4788
4789   /* PREFIX_VEX_0F4A */
4790   {
4791     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
4792     { Bad_Opcode },
4793     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
4794   },
4795
4796   /* PREFIX_VEX_0F4B */
4797   {
4798     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
4799     { Bad_Opcode },
4800     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4801   },
4802
4803   /* PREFIX_VEX_0F51 */
4804   {
4805     { VEX_W_TABLE (VEX_W_0F51_P_0) },
4806     { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) },
4807     { VEX_W_TABLE (VEX_W_0F51_P_2) },
4808     { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) },
4809   },
4810
4811   /* PREFIX_VEX_0F52 */
4812   {
4813     { VEX_W_TABLE (VEX_W_0F52_P_0) },
4814     { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) },
4815   },
4816
4817   /* PREFIX_VEX_0F53 */
4818   {
4819     { VEX_W_TABLE (VEX_W_0F53_P_0) },
4820     { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) },
4821   },
4822
4823   /* PREFIX_VEX_0F58 */
4824   {
4825     { VEX_W_TABLE (VEX_W_0F58_P_0) },
4826     { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) },
4827     { VEX_W_TABLE (VEX_W_0F58_P_2) },
4828     { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) },
4829   },
4830
4831   /* PREFIX_VEX_0F59 */
4832   {
4833     { VEX_W_TABLE (VEX_W_0F59_P_0) },
4834     { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) },
4835     { VEX_W_TABLE (VEX_W_0F59_P_2) },
4836     { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) },
4837   },
4838
4839   /* PREFIX_VEX_0F5A */
4840   {
4841     { VEX_W_TABLE (VEX_W_0F5A_P_0) },
4842     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) },
4843     { "vcvtpd2ps%XY", { XMM, EXx }, 0 },
4844     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) },
4845   },
4846
4847   /* PREFIX_VEX_0F5B */
4848   {
4849     { VEX_W_TABLE (VEX_W_0F5B_P_0) },
4850     { VEX_W_TABLE (VEX_W_0F5B_P_1) },
4851     { VEX_W_TABLE (VEX_W_0F5B_P_2) },
4852   },
4853
4854   /* PREFIX_VEX_0F5C */
4855   {
4856     { VEX_W_TABLE (VEX_W_0F5C_P_0) },
4857     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) },
4858     { VEX_W_TABLE (VEX_W_0F5C_P_2) },
4859     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) },
4860   },
4861
4862   /* PREFIX_VEX_0F5D */
4863   {
4864     { VEX_W_TABLE (VEX_W_0F5D_P_0) },
4865     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) },
4866     { VEX_W_TABLE (VEX_W_0F5D_P_2) },
4867     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) },
4868   },
4869
4870   /* PREFIX_VEX_0F5E */
4871   {
4872     { VEX_W_TABLE (VEX_W_0F5E_P_0) },
4873     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) },
4874     { VEX_W_TABLE (VEX_W_0F5E_P_2) },
4875     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) },
4876   },
4877
4878   /* PREFIX_VEX_0F5F */
4879   {
4880     { VEX_W_TABLE (VEX_W_0F5F_P_0) },
4881     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) },
4882     { VEX_W_TABLE (VEX_W_0F5F_P_2) },
4883     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) },
4884   },
4885
4886   /* PREFIX_VEX_0F60 */
4887   {
4888     { Bad_Opcode },
4889     { Bad_Opcode },
4890     { VEX_W_TABLE (VEX_W_0F60_P_2) },
4891   },
4892
4893   /* PREFIX_VEX_0F61 */
4894   {
4895     { Bad_Opcode },
4896     { Bad_Opcode },
4897     { VEX_W_TABLE (VEX_W_0F61_P_2) },
4898   },
4899
4900   /* PREFIX_VEX_0F62 */
4901   {
4902     { Bad_Opcode },
4903     { Bad_Opcode },
4904     { VEX_W_TABLE (VEX_W_0F62_P_2) },
4905   },
4906
4907   /* PREFIX_VEX_0F63 */
4908   {
4909     { Bad_Opcode },
4910     { Bad_Opcode },
4911     { VEX_W_TABLE (VEX_W_0F63_P_2) },
4912   },
4913
4914   /* PREFIX_VEX_0F64 */
4915   {
4916     { Bad_Opcode },
4917     { Bad_Opcode },
4918     { VEX_W_TABLE (VEX_W_0F64_P_2) },
4919   },
4920
4921   /* PREFIX_VEX_0F65 */
4922   {
4923     { Bad_Opcode },
4924     { Bad_Opcode },
4925     { VEX_W_TABLE (VEX_W_0F65_P_2) },
4926   },
4927
4928   /* PREFIX_VEX_0F66 */
4929   {
4930     { Bad_Opcode },
4931     { Bad_Opcode },
4932     { VEX_W_TABLE (VEX_W_0F66_P_2) },
4933   },
4934
4935   /* PREFIX_VEX_0F67 */
4936   {
4937     { Bad_Opcode },
4938     { Bad_Opcode },
4939     { VEX_W_TABLE (VEX_W_0F67_P_2) },
4940   },
4941
4942   /* PREFIX_VEX_0F68 */
4943   {
4944     { Bad_Opcode },
4945     { Bad_Opcode },
4946     { VEX_W_TABLE (VEX_W_0F68_P_2) },
4947   },
4948
4949   /* PREFIX_VEX_0F69 */
4950   {
4951     { Bad_Opcode },
4952     { Bad_Opcode },
4953     { VEX_W_TABLE (VEX_W_0F69_P_2) },
4954   },
4955
4956   /* PREFIX_VEX_0F6A */
4957   {
4958     { Bad_Opcode },
4959     { Bad_Opcode },
4960     { VEX_W_TABLE (VEX_W_0F6A_P_2) },
4961   },
4962
4963   /* PREFIX_VEX_0F6B */
4964   {
4965     { Bad_Opcode },
4966     { Bad_Opcode },
4967     { VEX_W_TABLE (VEX_W_0F6B_P_2) },
4968   },
4969
4970   /* PREFIX_VEX_0F6C */
4971   {
4972     { Bad_Opcode },
4973     { Bad_Opcode },
4974     { VEX_W_TABLE (VEX_W_0F6C_P_2) },
4975   },
4976
4977   /* PREFIX_VEX_0F6D */
4978   {
4979     { Bad_Opcode },
4980     { Bad_Opcode },
4981     { VEX_W_TABLE (VEX_W_0F6D_P_2) },
4982   },
4983
4984   /* PREFIX_VEX_0F6E */
4985   {
4986     { Bad_Opcode },
4987     { Bad_Opcode },
4988     { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
4989   },
4990
4991   /* PREFIX_VEX_0F6F */
4992   {
4993     { Bad_Opcode },
4994     { VEX_W_TABLE (VEX_W_0F6F_P_1) },
4995     { VEX_W_TABLE (VEX_W_0F6F_P_2) },
4996   },
4997
4998   /* PREFIX_VEX_0F70 */
4999   {
5000     { Bad_Opcode },
5001     { VEX_W_TABLE (VEX_W_0F70_P_1) },
5002     { VEX_W_TABLE (VEX_W_0F70_P_2) },
5003     { VEX_W_TABLE (VEX_W_0F70_P_3) },
5004   },
5005
5006   /* PREFIX_VEX_0F71_REG_2 */
5007   {
5008     { Bad_Opcode },
5009     { Bad_Opcode },
5010     { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) },
5011   },
5012
5013   /* PREFIX_VEX_0F71_REG_4 */
5014   {
5015     { Bad_Opcode },
5016     { Bad_Opcode },
5017     { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) },
5018   },
5019
5020   /* PREFIX_VEX_0F71_REG_6 */
5021   {
5022     { Bad_Opcode },
5023     { Bad_Opcode },
5024     { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) },
5025   },
5026
5027   /* PREFIX_VEX_0F72_REG_2 */
5028   {
5029     { Bad_Opcode },
5030     { Bad_Opcode },
5031     { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) },
5032   },
5033
5034   /* PREFIX_VEX_0F72_REG_4 */
5035   {
5036     { Bad_Opcode },
5037     { Bad_Opcode },
5038     { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) },
5039   },
5040
5041   /* PREFIX_VEX_0F72_REG_6 */
5042   {
5043     { Bad_Opcode },
5044     { Bad_Opcode },
5045     { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) },
5046   },
5047
5048   /* PREFIX_VEX_0F73_REG_2 */
5049   {
5050     { Bad_Opcode },
5051     { Bad_Opcode },
5052     { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) },
5053   },
5054
5055   /* PREFIX_VEX_0F73_REG_3 */
5056   {
5057     { Bad_Opcode },
5058     { Bad_Opcode },
5059     { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) },
5060   },
5061
5062   /* PREFIX_VEX_0F73_REG_6 */
5063   {
5064     { Bad_Opcode },
5065     { Bad_Opcode },
5066     { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) },
5067   },
5068
5069   /* PREFIX_VEX_0F73_REG_7 */
5070   {
5071     { Bad_Opcode },
5072     { Bad_Opcode },
5073     { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) },
5074   },
5075
5076   /* PREFIX_VEX_0F74 */
5077   {
5078     { Bad_Opcode },
5079     { Bad_Opcode },
5080     { VEX_W_TABLE (VEX_W_0F74_P_2) },
5081   },
5082
5083   /* PREFIX_VEX_0F75 */
5084   {
5085     { Bad_Opcode },
5086     { Bad_Opcode },
5087     { VEX_W_TABLE (VEX_W_0F75_P_2) },
5088   },
5089
5090   /* PREFIX_VEX_0F76 */
5091   {
5092     { Bad_Opcode },
5093     { Bad_Opcode },
5094     { VEX_W_TABLE (VEX_W_0F76_P_2) },
5095   },
5096
5097   /* PREFIX_VEX_0F77 */
5098   {
5099     { VEX_W_TABLE (VEX_W_0F77_P_0) },
5100   },
5101
5102   /* PREFIX_VEX_0F7C */
5103   {
5104     { Bad_Opcode },
5105     { Bad_Opcode },
5106     { VEX_W_TABLE (VEX_W_0F7C_P_2) },
5107     { VEX_W_TABLE (VEX_W_0F7C_P_3) },
5108   },
5109
5110   /* PREFIX_VEX_0F7D */
5111   {
5112     { Bad_Opcode },
5113     { Bad_Opcode },
5114     { VEX_W_TABLE (VEX_W_0F7D_P_2) },
5115     { VEX_W_TABLE (VEX_W_0F7D_P_3) },
5116   },
5117
5118   /* PREFIX_VEX_0F7E */
5119   {
5120     { Bad_Opcode },
5121     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
5122     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
5123   },
5124
5125   /* PREFIX_VEX_0F7F */
5126   {
5127     { Bad_Opcode },
5128     { VEX_W_TABLE (VEX_W_0F7F_P_1) },
5129     { VEX_W_TABLE (VEX_W_0F7F_P_2) },
5130   },
5131
5132   /* PREFIX_VEX_0F90 */
5133   {
5134     { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
5135     { Bad_Opcode },
5136     { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
5137   },
5138
5139   /* PREFIX_VEX_0F91 */
5140   {
5141     { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
5142     { Bad_Opcode },
5143     { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
5144   },
5145
5146   /* PREFIX_VEX_0F92 */
5147   {
5148     { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
5149     { Bad_Opcode },
5150     { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
5151     { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
5152   },
5153
5154   /* PREFIX_VEX_0F93 */
5155   {
5156     { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
5157     { Bad_Opcode },
5158     { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
5159     { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
5160   },
5161
5162   /* PREFIX_VEX_0F98 */
5163   {
5164     { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
5165     { Bad_Opcode },
5166     { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
5167   },
5168
5169   /* PREFIX_VEX_0F99 */
5170   {
5171     { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5172     { Bad_Opcode },
5173     { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5174   },
5175
5176   /* PREFIX_VEX_0FC2 */
5177   {
5178     { VEX_W_TABLE (VEX_W_0FC2_P_0) },
5179     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) },
5180     { VEX_W_TABLE (VEX_W_0FC2_P_2) },
5181     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) },
5182   },
5183
5184   /* PREFIX_VEX_0FC4 */
5185   {
5186     { Bad_Opcode },
5187     { Bad_Opcode },
5188     { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5189   },
5190
5191   /* PREFIX_VEX_0FC5 */
5192   {
5193     { Bad_Opcode },
5194     { Bad_Opcode },
5195     { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5196   },
5197
5198   /* PREFIX_VEX_0FD0 */
5199   {
5200     { Bad_Opcode },
5201     { Bad_Opcode },
5202     { VEX_W_TABLE (VEX_W_0FD0_P_2) },
5203     { VEX_W_TABLE (VEX_W_0FD0_P_3) },
5204   },
5205
5206   /* PREFIX_VEX_0FD1 */
5207   {
5208     { Bad_Opcode },
5209     { Bad_Opcode },
5210     { VEX_W_TABLE (VEX_W_0FD1_P_2) },
5211   },
5212
5213   /* PREFIX_VEX_0FD2 */
5214   {
5215     { Bad_Opcode },
5216     { Bad_Opcode },
5217     { VEX_W_TABLE (VEX_W_0FD2_P_2) },
5218   },
5219
5220   /* PREFIX_VEX_0FD3 */
5221   {
5222     { Bad_Opcode },
5223     { Bad_Opcode },
5224     { VEX_W_TABLE (VEX_W_0FD3_P_2) },
5225   },
5226
5227   /* PREFIX_VEX_0FD4 */
5228   {
5229     { Bad_Opcode },
5230     { Bad_Opcode },
5231     { VEX_W_TABLE (VEX_W_0FD4_P_2) },
5232   },
5233
5234   /* PREFIX_VEX_0FD5 */
5235   {
5236     { Bad_Opcode },
5237     { Bad_Opcode },
5238     { VEX_W_TABLE (VEX_W_0FD5_P_2) },
5239   },
5240
5241   /* PREFIX_VEX_0FD6 */
5242   {
5243     { Bad_Opcode },
5244     { Bad_Opcode },
5245     { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5246   },
5247
5248   /* PREFIX_VEX_0FD7 */
5249   {
5250     { Bad_Opcode },
5251     { Bad_Opcode },
5252     { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5253   },
5254
5255   /* PREFIX_VEX_0FD8 */
5256   {
5257     { Bad_Opcode },
5258     { Bad_Opcode },
5259     { VEX_W_TABLE (VEX_W_0FD8_P_2) },
5260   },
5261
5262   /* PREFIX_VEX_0FD9 */
5263   {
5264     { Bad_Opcode },
5265     { Bad_Opcode },
5266     { VEX_W_TABLE (VEX_W_0FD9_P_2) },
5267   },
5268
5269   /* PREFIX_VEX_0FDA */
5270   {
5271     { Bad_Opcode },
5272     { Bad_Opcode },
5273     { VEX_W_TABLE (VEX_W_0FDA_P_2) },
5274   },
5275
5276   /* PREFIX_VEX_0FDB */
5277   {
5278     { Bad_Opcode },
5279     { Bad_Opcode },
5280     { VEX_W_TABLE (VEX_W_0FDB_P_2) },
5281   },
5282
5283   /* PREFIX_VEX_0FDC */
5284   {
5285     { Bad_Opcode },
5286     { Bad_Opcode },
5287     { VEX_W_TABLE (VEX_W_0FDC_P_2) },
5288   },
5289
5290   /* PREFIX_VEX_0FDD */
5291   {
5292     { Bad_Opcode },
5293     { Bad_Opcode },
5294     { VEX_W_TABLE (VEX_W_0FDD_P_2) },
5295   },
5296
5297   /* PREFIX_VEX_0FDE */
5298   {
5299     { Bad_Opcode },
5300     { Bad_Opcode },
5301     { VEX_W_TABLE (VEX_W_0FDE_P_2) },
5302   },
5303
5304   /* PREFIX_VEX_0FDF */
5305   {
5306     { Bad_Opcode },
5307     { Bad_Opcode },
5308     { VEX_W_TABLE (VEX_W_0FDF_P_2) },
5309   },
5310
5311   /* PREFIX_VEX_0FE0 */
5312   {
5313     { Bad_Opcode },
5314     { Bad_Opcode },
5315     { VEX_W_TABLE (VEX_W_0FE0_P_2) },
5316   },
5317
5318   /* PREFIX_VEX_0FE1 */
5319   {
5320     { Bad_Opcode },
5321     { Bad_Opcode },
5322     { VEX_W_TABLE (VEX_W_0FE1_P_2) },
5323   },
5324
5325   /* PREFIX_VEX_0FE2 */
5326   {
5327     { Bad_Opcode },
5328     { Bad_Opcode },
5329     { VEX_W_TABLE (VEX_W_0FE2_P_2) },
5330   },
5331
5332   /* PREFIX_VEX_0FE3 */
5333   {
5334     { Bad_Opcode },
5335     { Bad_Opcode },
5336     { VEX_W_TABLE (VEX_W_0FE3_P_2) },
5337   },
5338
5339   /* PREFIX_VEX_0FE4 */
5340   {
5341     { Bad_Opcode },
5342     { Bad_Opcode },
5343     { VEX_W_TABLE (VEX_W_0FE4_P_2) },
5344   },
5345
5346   /* PREFIX_VEX_0FE5 */
5347   {
5348     { Bad_Opcode },
5349     { Bad_Opcode },
5350     { VEX_W_TABLE (VEX_W_0FE5_P_2) },
5351   },
5352
5353   /* PREFIX_VEX_0FE6 */
5354   {
5355     { Bad_Opcode },
5356     { VEX_W_TABLE (VEX_W_0FE6_P_1) },
5357     { VEX_W_TABLE (VEX_W_0FE6_P_2) },
5358     { VEX_W_TABLE (VEX_W_0FE6_P_3) },
5359   },
5360
5361   /* PREFIX_VEX_0FE7 */
5362   {
5363     { Bad_Opcode },
5364     { Bad_Opcode },
5365     { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5366   },
5367
5368   /* PREFIX_VEX_0FE8 */
5369   {
5370     { Bad_Opcode },
5371     { Bad_Opcode },
5372     { VEX_W_TABLE (VEX_W_0FE8_P_2) },
5373   },
5374
5375   /* PREFIX_VEX_0FE9 */
5376   {
5377     { Bad_Opcode },
5378     { Bad_Opcode },
5379     { VEX_W_TABLE (VEX_W_0FE9_P_2) },
5380   },
5381
5382   /* PREFIX_VEX_0FEA */
5383   {
5384     { Bad_Opcode },
5385     { Bad_Opcode },
5386     { VEX_W_TABLE (VEX_W_0FEA_P_2) },
5387   },
5388
5389   /* PREFIX_VEX_0FEB */
5390   {
5391     { Bad_Opcode },
5392     { Bad_Opcode },
5393     { VEX_W_TABLE (VEX_W_0FEB_P_2) },
5394   },
5395
5396   /* PREFIX_VEX_0FEC */
5397   {
5398     { Bad_Opcode },
5399     { Bad_Opcode },
5400     { VEX_W_TABLE (VEX_W_0FEC_P_2) },
5401   },
5402
5403   /* PREFIX_VEX_0FED */
5404   {
5405     { Bad_Opcode },
5406     { Bad_Opcode },
5407     { VEX_W_TABLE (VEX_W_0FED_P_2) },
5408   },
5409
5410   /* PREFIX_VEX_0FEE */
5411   {
5412     { Bad_Opcode },
5413     { Bad_Opcode },
5414     { VEX_W_TABLE (VEX_W_0FEE_P_2) },
5415   },
5416
5417   /* PREFIX_VEX_0FEF */
5418   {
5419     { Bad_Opcode },
5420     { Bad_Opcode },
5421     { VEX_W_TABLE (VEX_W_0FEF_P_2) },
5422   },
5423
5424   /* PREFIX_VEX_0FF0 */
5425   {
5426     { Bad_Opcode },
5427     { Bad_Opcode },
5428     { Bad_Opcode },
5429     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5430   },
5431
5432   /* PREFIX_VEX_0FF1 */
5433   {
5434     { Bad_Opcode },
5435     { Bad_Opcode },
5436     { VEX_W_TABLE (VEX_W_0FF1_P_2) },
5437   },
5438
5439   /* PREFIX_VEX_0FF2 */
5440   {
5441     { Bad_Opcode },
5442     { Bad_Opcode },
5443     { VEX_W_TABLE (VEX_W_0FF2_P_2) },
5444   },
5445
5446   /* PREFIX_VEX_0FF3 */
5447   {
5448     { Bad_Opcode },
5449     { Bad_Opcode },
5450     { VEX_W_TABLE (VEX_W_0FF3_P_2) },
5451   },
5452
5453   /* PREFIX_VEX_0FF4 */
5454   {
5455     { Bad_Opcode },
5456     { Bad_Opcode },
5457     { VEX_W_TABLE (VEX_W_0FF4_P_2) },
5458   },
5459
5460   /* PREFIX_VEX_0FF5 */
5461   {
5462     { Bad_Opcode },
5463     { Bad_Opcode },
5464     { VEX_W_TABLE (VEX_W_0FF5_P_2) },
5465   },
5466
5467   /* PREFIX_VEX_0FF6 */
5468   {
5469     { Bad_Opcode },
5470     { Bad_Opcode },
5471     { VEX_W_TABLE (VEX_W_0FF6_P_2) },
5472   },
5473
5474   /* PREFIX_VEX_0FF7 */
5475   {
5476     { Bad_Opcode },
5477     { Bad_Opcode },
5478     { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5479   },
5480
5481   /* PREFIX_VEX_0FF8 */
5482   {
5483     { Bad_Opcode },
5484     { Bad_Opcode },
5485     { VEX_W_TABLE (VEX_W_0FF8_P_2) },
5486   },
5487
5488   /* PREFIX_VEX_0FF9 */
5489   {
5490     { Bad_Opcode },
5491     { Bad_Opcode },
5492     { VEX_W_TABLE (VEX_W_0FF9_P_2) },
5493   },
5494
5495   /* PREFIX_VEX_0FFA */
5496   {
5497     { Bad_Opcode },
5498     { Bad_Opcode },
5499     { VEX_W_TABLE (VEX_W_0FFA_P_2) },
5500   },
5501
5502   /* PREFIX_VEX_0FFB */
5503   {
5504     { Bad_Opcode },
5505     { Bad_Opcode },
5506     { VEX_W_TABLE (VEX_W_0FFB_P_2) },
5507   },
5508
5509   /* PREFIX_VEX_0FFC */
5510   {
5511     { Bad_Opcode },
5512     { Bad_Opcode },
5513     { VEX_W_TABLE (VEX_W_0FFC_P_2) },
5514   },
5515
5516   /* PREFIX_VEX_0FFD */
5517   {
5518     { Bad_Opcode },
5519     { Bad_Opcode },
5520     { VEX_W_TABLE (VEX_W_0FFD_P_2) },
5521   },
5522
5523   /* PREFIX_VEX_0FFE */
5524   {
5525     { Bad_Opcode },
5526     { Bad_Opcode },
5527     { VEX_W_TABLE (VEX_W_0FFE_P_2) },
5528   },
5529
5530   /* PREFIX_VEX_0F3800 */
5531   {
5532     { Bad_Opcode },
5533     { Bad_Opcode },
5534     { VEX_W_TABLE (VEX_W_0F3800_P_2) },
5535   },
5536
5537   /* PREFIX_VEX_0F3801 */
5538   {
5539     { Bad_Opcode },
5540     { Bad_Opcode },
5541     { VEX_W_TABLE (VEX_W_0F3801_P_2) },
5542   },
5543
5544   /* PREFIX_VEX_0F3802 */
5545   {
5546     { Bad_Opcode },
5547     { Bad_Opcode },
5548     { VEX_W_TABLE (VEX_W_0F3802_P_2) },
5549   },
5550
5551   /* PREFIX_VEX_0F3803 */
5552   {
5553     { Bad_Opcode },
5554     { Bad_Opcode },
5555     { VEX_W_TABLE (VEX_W_0F3803_P_2) },
5556   },
5557
5558   /* PREFIX_VEX_0F3804 */
5559   {
5560     { Bad_Opcode },
5561     { Bad_Opcode },
5562     { VEX_W_TABLE (VEX_W_0F3804_P_2) },
5563   },
5564
5565   /* PREFIX_VEX_0F3805 */
5566   {
5567     { Bad_Opcode },
5568     { Bad_Opcode },
5569     { VEX_W_TABLE (VEX_W_0F3805_P_2) },
5570   },
5571
5572   /* PREFIX_VEX_0F3806 */
5573   {
5574     { Bad_Opcode },
5575     { Bad_Opcode },
5576     { VEX_W_TABLE (VEX_W_0F3806_P_2) },
5577   },
5578
5579   /* PREFIX_VEX_0F3807 */
5580   {
5581     { Bad_Opcode },
5582     { Bad_Opcode },
5583     { VEX_W_TABLE (VEX_W_0F3807_P_2) },
5584   },
5585
5586   /* PREFIX_VEX_0F3808 */
5587   {
5588     { Bad_Opcode },
5589     { Bad_Opcode },
5590     { VEX_W_TABLE (VEX_W_0F3808_P_2) },
5591   },
5592
5593   /* PREFIX_VEX_0F3809 */
5594   {
5595     { Bad_Opcode },
5596     { Bad_Opcode },
5597     { VEX_W_TABLE (VEX_W_0F3809_P_2) },
5598   },
5599
5600   /* PREFIX_VEX_0F380A */
5601   {
5602     { Bad_Opcode },
5603     { Bad_Opcode },
5604     { VEX_W_TABLE (VEX_W_0F380A_P_2) },
5605   },
5606
5607   /* PREFIX_VEX_0F380B */
5608   {
5609     { Bad_Opcode },
5610     { Bad_Opcode },
5611     { VEX_W_TABLE (VEX_W_0F380B_P_2) },
5612   },
5613
5614   /* PREFIX_VEX_0F380C */
5615   {
5616     { Bad_Opcode },
5617     { Bad_Opcode },
5618     { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5619   },
5620
5621   /* PREFIX_VEX_0F380D */
5622   {
5623     { Bad_Opcode },
5624     { Bad_Opcode },
5625     { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5626   },
5627
5628   /* PREFIX_VEX_0F380E */
5629   {
5630     { Bad_Opcode },
5631     { Bad_Opcode },
5632     { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5633   },
5634
5635   /* PREFIX_VEX_0F380F */
5636   {
5637     { Bad_Opcode },
5638     { Bad_Opcode },
5639     { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5640   },
5641
5642   /* PREFIX_VEX_0F3813 */
5643   {
5644     { Bad_Opcode },
5645     { Bad_Opcode },
5646     { "vcvtph2ps", { XM, EXxmmq }, 0 },
5647   },
5648
5649   /* PREFIX_VEX_0F3816 */
5650   {
5651     { Bad_Opcode },
5652     { Bad_Opcode },
5653     { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5654   },
5655
5656   /* PREFIX_VEX_0F3817 */
5657   {
5658     { Bad_Opcode },
5659     { Bad_Opcode },
5660     { VEX_W_TABLE (VEX_W_0F3817_P_2) },
5661   },
5662
5663   /* PREFIX_VEX_0F3818 */
5664   {
5665     { Bad_Opcode },
5666     { Bad_Opcode },
5667     { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5668   },
5669
5670   /* PREFIX_VEX_0F3819 */
5671   {
5672     { Bad_Opcode },
5673     { Bad_Opcode },
5674     { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5675   },
5676
5677   /* PREFIX_VEX_0F381A */
5678   {
5679     { Bad_Opcode },
5680     { Bad_Opcode },
5681     { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5682   },
5683
5684   /* PREFIX_VEX_0F381C */
5685   {
5686     { Bad_Opcode },
5687     { Bad_Opcode },
5688     { VEX_W_TABLE (VEX_W_0F381C_P_2) },
5689   },
5690
5691   /* PREFIX_VEX_0F381D */
5692   {
5693     { Bad_Opcode },
5694     { Bad_Opcode },
5695     { VEX_W_TABLE (VEX_W_0F381D_P_2) },
5696   },
5697
5698   /* PREFIX_VEX_0F381E */
5699   {
5700     { Bad_Opcode },
5701     { Bad_Opcode },
5702     { VEX_W_TABLE (VEX_W_0F381E_P_2) },
5703   },
5704
5705   /* PREFIX_VEX_0F3820 */
5706   {
5707     { Bad_Opcode },
5708     { Bad_Opcode },
5709     { VEX_W_TABLE (VEX_W_0F3820_P_2) },
5710   },
5711
5712   /* PREFIX_VEX_0F3821 */
5713   {
5714     { Bad_Opcode },
5715     { Bad_Opcode },
5716     { VEX_W_TABLE (VEX_W_0F3821_P_2) },
5717   },
5718
5719   /* PREFIX_VEX_0F3822 */
5720   {
5721     { Bad_Opcode },
5722     { Bad_Opcode },
5723     { VEX_W_TABLE (VEX_W_0F3822_P_2) },
5724   },
5725
5726   /* PREFIX_VEX_0F3823 */
5727   {
5728     { Bad_Opcode },
5729     { Bad_Opcode },
5730     { VEX_W_TABLE (VEX_W_0F3823_P_2) },
5731   },
5732
5733   /* PREFIX_VEX_0F3824 */
5734   {
5735     { Bad_Opcode },
5736     { Bad_Opcode },
5737     { VEX_W_TABLE (VEX_W_0F3824_P_2) },
5738   },
5739
5740   /* PREFIX_VEX_0F3825 */
5741   {
5742     { Bad_Opcode },
5743     { Bad_Opcode },
5744     { VEX_W_TABLE (VEX_W_0F3825_P_2) },
5745   },
5746
5747   /* PREFIX_VEX_0F3828 */
5748   {
5749     { Bad_Opcode },
5750     { Bad_Opcode },
5751     { VEX_W_TABLE (VEX_W_0F3828_P_2) },
5752   },
5753
5754   /* PREFIX_VEX_0F3829 */
5755   {
5756     { Bad_Opcode },
5757     { Bad_Opcode },
5758     { VEX_W_TABLE (VEX_W_0F3829_P_2) },
5759   },
5760
5761   /* PREFIX_VEX_0F382A */
5762   {
5763     { Bad_Opcode },
5764     { Bad_Opcode },
5765     { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5766   },
5767
5768   /* PREFIX_VEX_0F382B */
5769   {
5770     { Bad_Opcode },
5771     { Bad_Opcode },
5772     { VEX_W_TABLE (VEX_W_0F382B_P_2) },
5773   },
5774
5775   /* PREFIX_VEX_0F382C */
5776   {
5777     { Bad_Opcode },
5778     { Bad_Opcode },
5779      { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5780   },
5781
5782   /* PREFIX_VEX_0F382D */
5783   {
5784     { Bad_Opcode },
5785     { Bad_Opcode },
5786      { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5787   },
5788
5789   /* PREFIX_VEX_0F382E */
5790   {
5791     { Bad_Opcode },
5792     { Bad_Opcode },
5793      { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5794   },
5795
5796   /* PREFIX_VEX_0F382F */
5797   {
5798     { Bad_Opcode },
5799     { Bad_Opcode },
5800      { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5801   },
5802
5803   /* PREFIX_VEX_0F3830 */
5804   {
5805     { Bad_Opcode },
5806     { Bad_Opcode },
5807     { VEX_W_TABLE (VEX_W_0F3830_P_2) },
5808   },
5809
5810   /* PREFIX_VEX_0F3831 */
5811   {
5812     { Bad_Opcode },
5813     { Bad_Opcode },
5814     { VEX_W_TABLE (VEX_W_0F3831_P_2) },
5815   },
5816
5817   /* PREFIX_VEX_0F3832 */
5818   {
5819     { Bad_Opcode },
5820     { Bad_Opcode },
5821     { VEX_W_TABLE (VEX_W_0F3832_P_2) },
5822   },
5823
5824   /* PREFIX_VEX_0F3833 */
5825   {
5826     { Bad_Opcode },
5827     { Bad_Opcode },
5828     { VEX_W_TABLE (VEX_W_0F3833_P_2) },
5829   },
5830
5831   /* PREFIX_VEX_0F3834 */
5832   {
5833     { Bad_Opcode },
5834     { Bad_Opcode },
5835     { VEX_W_TABLE (VEX_W_0F3834_P_2) },
5836   },
5837
5838   /* PREFIX_VEX_0F3835 */
5839   {
5840     { Bad_Opcode },
5841     { Bad_Opcode },
5842     { VEX_W_TABLE (VEX_W_0F3835_P_2) },
5843   },
5844
5845   /* PREFIX_VEX_0F3836 */
5846   {
5847     { Bad_Opcode },
5848     { Bad_Opcode },
5849     { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5850   },
5851
5852   /* PREFIX_VEX_0F3837 */
5853   {
5854     { Bad_Opcode },
5855     { Bad_Opcode },
5856     { VEX_W_TABLE (VEX_W_0F3837_P_2) },
5857   },
5858
5859   /* PREFIX_VEX_0F3838 */
5860   {
5861     { Bad_Opcode },
5862     { Bad_Opcode },
5863     { VEX_W_TABLE (VEX_W_0F3838_P_2) },
5864   },
5865
5866   /* PREFIX_VEX_0F3839 */
5867   {
5868     { Bad_Opcode },
5869     { Bad_Opcode },
5870     { VEX_W_TABLE (VEX_W_0F3839_P_2) },
5871   },
5872
5873   /* PREFIX_VEX_0F383A */
5874   {
5875     { Bad_Opcode },
5876     { Bad_Opcode },
5877     { VEX_W_TABLE (VEX_W_0F383A_P_2) },
5878   },
5879
5880   /* PREFIX_VEX_0F383B */
5881   {
5882     { Bad_Opcode },
5883     { Bad_Opcode },
5884     { VEX_W_TABLE (VEX_W_0F383B_P_2) },
5885   },
5886
5887   /* PREFIX_VEX_0F383C */
5888   {
5889     { Bad_Opcode },
5890     { Bad_Opcode },
5891     { VEX_W_TABLE (VEX_W_0F383C_P_2) },
5892   },
5893
5894   /* PREFIX_VEX_0F383D */
5895   {
5896     { Bad_Opcode },
5897     { Bad_Opcode },
5898     { VEX_W_TABLE (VEX_W_0F383D_P_2) },
5899   },
5900
5901   /* PREFIX_VEX_0F383E */
5902   {
5903     { Bad_Opcode },
5904     { Bad_Opcode },
5905     { VEX_W_TABLE (VEX_W_0F383E_P_2) },
5906   },
5907
5908   /* PREFIX_VEX_0F383F */
5909   {
5910     { Bad_Opcode },
5911     { Bad_Opcode },
5912     { VEX_W_TABLE (VEX_W_0F383F_P_2) },
5913   },
5914
5915   /* PREFIX_VEX_0F3840 */
5916   {
5917     { Bad_Opcode },
5918     { Bad_Opcode },
5919     { VEX_W_TABLE (VEX_W_0F3840_P_2) },
5920   },
5921
5922   /* PREFIX_VEX_0F3841 */
5923   {
5924     { Bad_Opcode },
5925     { Bad_Opcode },
5926     { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
5927   },
5928
5929   /* PREFIX_VEX_0F3845 */
5930   {
5931     { Bad_Opcode },
5932     { Bad_Opcode },
5933     { "vpsrlv%LW", { XM, Vex, EXx }, 0 },
5934   },
5935
5936   /* PREFIX_VEX_0F3846 */
5937   {
5938     { Bad_Opcode },
5939     { Bad_Opcode },
5940     { VEX_W_TABLE (VEX_W_0F3846_P_2) },
5941   },
5942
5943   /* PREFIX_VEX_0F3847 */
5944   {
5945     { Bad_Opcode },
5946     { Bad_Opcode },
5947     { "vpsllv%LW", { XM, Vex, EXx }, 0 },
5948   },
5949
5950   /* PREFIX_VEX_0F3858 */
5951   {
5952     { Bad_Opcode },
5953     { Bad_Opcode },
5954     { VEX_W_TABLE (VEX_W_0F3858_P_2) },
5955   },
5956
5957   /* PREFIX_VEX_0F3859 */
5958   {
5959     { Bad_Opcode },
5960     { Bad_Opcode },
5961     { VEX_W_TABLE (VEX_W_0F3859_P_2) },
5962   },
5963
5964   /* PREFIX_VEX_0F385A */
5965   {
5966     { Bad_Opcode },
5967     { Bad_Opcode },
5968     { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
5969   },
5970
5971   /* PREFIX_VEX_0F3878 */
5972   {
5973     { Bad_Opcode },
5974     { Bad_Opcode },
5975     { VEX_W_TABLE (VEX_W_0F3878_P_2) },
5976   },
5977
5978   /* PREFIX_VEX_0F3879 */
5979   {
5980     { Bad_Opcode },
5981     { Bad_Opcode },
5982     { VEX_W_TABLE (VEX_W_0F3879_P_2) },
5983   },
5984
5985   /* PREFIX_VEX_0F388C */
5986   {
5987     { Bad_Opcode },
5988     { Bad_Opcode },
5989     { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
5990   },
5991
5992   /* PREFIX_VEX_0F388E */
5993   {
5994     { Bad_Opcode },
5995     { Bad_Opcode },
5996     { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
5997   },
5998
5999   /* PREFIX_VEX_0F3890 */
6000   {
6001     { Bad_Opcode },
6002     { Bad_Opcode },
6003     { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 },
6004   },
6005
6006   /* PREFIX_VEX_0F3891 */
6007   {
6008     { Bad_Opcode },
6009     { Bad_Opcode },
6010     { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6011   },
6012
6013   /* PREFIX_VEX_0F3892 */
6014   {
6015     { Bad_Opcode },
6016     { Bad_Opcode },
6017     { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 },
6018   },
6019
6020   /* PREFIX_VEX_0F3893 */
6021   {
6022     { Bad_Opcode },
6023     { Bad_Opcode },
6024     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6025   },
6026
6027   /* PREFIX_VEX_0F3896 */
6028   {
6029     { Bad_Opcode },
6030     { Bad_Opcode },
6031     { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 },
6032   },
6033
6034   /* PREFIX_VEX_0F3897 */
6035   {
6036     { Bad_Opcode },
6037     { Bad_Opcode },
6038     { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 },
6039   },
6040
6041   /* PREFIX_VEX_0F3898 */
6042   {
6043     { Bad_Opcode },
6044     { Bad_Opcode },
6045     { "vfmadd132p%XW", { XM, Vex, EXx }, 0 },
6046   },
6047
6048   /* PREFIX_VEX_0F3899 */
6049   {
6050     { Bad_Opcode },
6051     { Bad_Opcode },
6052     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6053   },
6054
6055   /* PREFIX_VEX_0F389A */
6056   {
6057     { Bad_Opcode },
6058     { Bad_Opcode },
6059     { "vfmsub132p%XW", { XM, Vex, EXx }, 0 },
6060   },
6061
6062   /* PREFIX_VEX_0F389B */
6063   {
6064     { Bad_Opcode },
6065     { Bad_Opcode },
6066     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6067   },
6068
6069   /* PREFIX_VEX_0F389C */
6070   {
6071     { Bad_Opcode },
6072     { Bad_Opcode },
6073     { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 },
6074   },
6075
6076   /* PREFIX_VEX_0F389D */
6077   {
6078     { Bad_Opcode },
6079     { Bad_Opcode },
6080     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6081   },
6082
6083   /* PREFIX_VEX_0F389E */
6084   {
6085     { Bad_Opcode },
6086     { Bad_Opcode },
6087     { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 },
6088   },
6089
6090   /* PREFIX_VEX_0F389F */
6091   {
6092     { Bad_Opcode },
6093     { Bad_Opcode },
6094     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6095   },
6096
6097   /* PREFIX_VEX_0F38A6 */
6098   {
6099     { Bad_Opcode },
6100     { Bad_Opcode },
6101     { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 },
6102     { Bad_Opcode },
6103   },
6104
6105   /* PREFIX_VEX_0F38A7 */
6106   {
6107     { Bad_Opcode },
6108     { Bad_Opcode },
6109     { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 },
6110   },
6111
6112   /* PREFIX_VEX_0F38A8 */
6113   {
6114     { Bad_Opcode },
6115     { Bad_Opcode },
6116     { "vfmadd213p%XW", { XM, Vex, EXx }, 0 },
6117   },
6118
6119   /* PREFIX_VEX_0F38A9 */
6120   {
6121     { Bad_Opcode },
6122     { Bad_Opcode },
6123     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6124   },
6125
6126   /* PREFIX_VEX_0F38AA */
6127   {
6128     { Bad_Opcode },
6129     { Bad_Opcode },
6130     { "vfmsub213p%XW", { XM, Vex, EXx }, 0 },
6131   },
6132
6133   /* PREFIX_VEX_0F38AB */
6134   {
6135     { Bad_Opcode },
6136     { Bad_Opcode },
6137     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6138   },
6139
6140   /* PREFIX_VEX_0F38AC */
6141   {
6142     { Bad_Opcode },
6143     { Bad_Opcode },
6144     { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 },
6145   },
6146
6147   /* PREFIX_VEX_0F38AD */
6148   {
6149     { Bad_Opcode },
6150     { Bad_Opcode },
6151     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6152   },
6153
6154   /* PREFIX_VEX_0F38AE */
6155   {
6156     { Bad_Opcode },
6157     { Bad_Opcode },
6158     { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 },
6159   },
6160
6161   /* PREFIX_VEX_0F38AF */
6162   {
6163     { Bad_Opcode },
6164     { Bad_Opcode },
6165     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6166   },
6167
6168   /* PREFIX_VEX_0F38B6 */
6169   {
6170     { Bad_Opcode },
6171     { Bad_Opcode },
6172     { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 },
6173   },
6174
6175   /* PREFIX_VEX_0F38B7 */
6176   {
6177     { Bad_Opcode },
6178     { Bad_Opcode },
6179     { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 },
6180   },
6181
6182   /* PREFIX_VEX_0F38B8 */
6183   {
6184     { Bad_Opcode },
6185     { Bad_Opcode },
6186     { "vfmadd231p%XW", { XM, Vex, EXx }, 0 },
6187   },
6188
6189   /* PREFIX_VEX_0F38B9 */
6190   {
6191     { Bad_Opcode },
6192     { Bad_Opcode },
6193     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6194   },
6195
6196   /* PREFIX_VEX_0F38BA */
6197   {
6198     { Bad_Opcode },
6199     { Bad_Opcode },
6200     { "vfmsub231p%XW", { XM, Vex, EXx }, 0 },
6201   },
6202
6203   /* PREFIX_VEX_0F38BB */
6204   {
6205     { Bad_Opcode },
6206     { Bad_Opcode },
6207     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6208   },
6209
6210   /* PREFIX_VEX_0F38BC */
6211   {
6212     { Bad_Opcode },
6213     { Bad_Opcode },
6214     { "vfnmadd231p%XW", { XM, Vex, EXx }, 0 },
6215   },
6216
6217   /* PREFIX_VEX_0F38BD */
6218   {
6219     { Bad_Opcode },
6220     { Bad_Opcode },
6221     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6222   },
6223
6224   /* PREFIX_VEX_0F38BE */
6225   {
6226     { Bad_Opcode },
6227     { Bad_Opcode },
6228     { "vfnmsub231p%XW", { XM, Vex, EXx }, 0 },
6229   },
6230
6231   /* PREFIX_VEX_0F38BF */
6232   {
6233     { Bad_Opcode },
6234     { Bad_Opcode },
6235     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6236   },
6237
6238   /* PREFIX_VEX_0F38DB */
6239   {
6240     { Bad_Opcode },
6241     { Bad_Opcode },
6242     { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6243   },
6244
6245   /* PREFIX_VEX_0F38DC */
6246   {
6247     { Bad_Opcode },
6248     { Bad_Opcode },
6249     { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2) },
6250   },
6251
6252   /* PREFIX_VEX_0F38DD */
6253   {
6254     { Bad_Opcode },
6255     { Bad_Opcode },
6256     { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2) },
6257   },
6258
6259   /* PREFIX_VEX_0F38DE */
6260   {
6261     { Bad_Opcode },
6262     { Bad_Opcode },
6263     { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2) },
6264   },
6265
6266   /* PREFIX_VEX_0F38DF */
6267   {
6268     { Bad_Opcode },
6269     { Bad_Opcode },
6270     { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2) },
6271   },
6272
6273   /* PREFIX_VEX_0F38F2 */
6274   {
6275     { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6276   },
6277
6278   /* PREFIX_VEX_0F38F3_REG_1 */
6279   {
6280     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6281   },
6282
6283   /* PREFIX_VEX_0F38F3_REG_2 */
6284   {
6285     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6286   },
6287
6288   /* PREFIX_VEX_0F38F3_REG_3 */
6289   {
6290     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6291   },
6292
6293   /* PREFIX_VEX_0F38F5 */
6294   {
6295     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6296     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6297     { Bad_Opcode },
6298     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6299   },
6300
6301   /* PREFIX_VEX_0F38F6 */
6302   {
6303     { Bad_Opcode },
6304     { Bad_Opcode },
6305     { Bad_Opcode },
6306     { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6307   },
6308
6309   /* PREFIX_VEX_0F38F7 */
6310   {
6311     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6312     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6313     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6314     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6315   },
6316
6317   /* PREFIX_VEX_0F3A00 */
6318   {
6319     { Bad_Opcode },
6320     { Bad_Opcode },
6321     { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6322   },
6323
6324   /* PREFIX_VEX_0F3A01 */
6325   {
6326     { Bad_Opcode },
6327     { Bad_Opcode },
6328     { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6329   },
6330
6331   /* PREFIX_VEX_0F3A02 */
6332   {
6333     { Bad_Opcode },
6334     { Bad_Opcode },
6335     { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6336   },
6337
6338   /* PREFIX_VEX_0F3A04 */
6339   {
6340     { Bad_Opcode },
6341     { Bad_Opcode },
6342     { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6343   },
6344
6345   /* PREFIX_VEX_0F3A05 */
6346   {
6347     { Bad_Opcode },
6348     { Bad_Opcode },
6349     { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6350   },
6351
6352   /* PREFIX_VEX_0F3A06 */
6353   {
6354     { Bad_Opcode },
6355     { Bad_Opcode },
6356     { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6357   },
6358
6359   /* PREFIX_VEX_0F3A08 */
6360   {
6361     { Bad_Opcode },
6362     { Bad_Opcode },
6363     { VEX_W_TABLE (VEX_W_0F3A08_P_2) },
6364   },
6365
6366   /* PREFIX_VEX_0F3A09 */
6367   {
6368     { Bad_Opcode },
6369     { Bad_Opcode },
6370     { VEX_W_TABLE (VEX_W_0F3A09_P_2) },
6371   },
6372
6373   /* PREFIX_VEX_0F3A0A */
6374   {
6375     { Bad_Opcode },
6376     { Bad_Opcode },
6377     { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) },
6378   },
6379
6380   /* PREFIX_VEX_0F3A0B */
6381   {
6382     { Bad_Opcode },
6383     { Bad_Opcode },
6384     { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) },
6385   },
6386
6387   /* PREFIX_VEX_0F3A0C */
6388   {
6389     { Bad_Opcode },
6390     { Bad_Opcode },
6391     { VEX_W_TABLE (VEX_W_0F3A0C_P_2) },
6392   },
6393
6394   /* PREFIX_VEX_0F3A0D */
6395   {
6396     { Bad_Opcode },
6397     { Bad_Opcode },
6398     { VEX_W_TABLE (VEX_W_0F3A0D_P_2) },
6399   },
6400
6401   /* PREFIX_VEX_0F3A0E */
6402   {
6403     { Bad_Opcode },
6404     { Bad_Opcode },
6405     { VEX_W_TABLE (VEX_W_0F3A0E_P_2) },
6406   },
6407
6408   /* PREFIX_VEX_0F3A0F */
6409   {
6410     { Bad_Opcode },
6411     { Bad_Opcode },
6412     { VEX_W_TABLE (VEX_W_0F3A0F_P_2) },
6413   },
6414
6415   /* PREFIX_VEX_0F3A14 */
6416   {
6417     { Bad_Opcode },
6418     { Bad_Opcode },
6419     { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6420   },
6421
6422   /* PREFIX_VEX_0F3A15 */
6423   {
6424     { Bad_Opcode },
6425     { Bad_Opcode },
6426     { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6427   },
6428
6429   /* PREFIX_VEX_0F3A16 */
6430   {
6431     { Bad_Opcode },
6432     { Bad_Opcode },
6433     { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6434   },
6435
6436   /* PREFIX_VEX_0F3A17 */
6437   {
6438     { Bad_Opcode },
6439     { Bad_Opcode },
6440     { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6441   },
6442
6443   /* PREFIX_VEX_0F3A18 */
6444   {
6445     { Bad_Opcode },
6446     { Bad_Opcode },
6447     { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6448   },
6449
6450   /* PREFIX_VEX_0F3A19 */
6451   {
6452     { Bad_Opcode },
6453     { Bad_Opcode },
6454     { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6455   },
6456
6457   /* PREFIX_VEX_0F3A1D */
6458   {
6459     { Bad_Opcode },
6460     { Bad_Opcode },
6461     { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 },
6462   },
6463
6464   /* PREFIX_VEX_0F3A20 */
6465   {
6466     { Bad_Opcode },
6467     { Bad_Opcode },
6468     { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6469   },
6470
6471   /* PREFIX_VEX_0F3A21 */
6472   {
6473     { Bad_Opcode },
6474     { Bad_Opcode },
6475     { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6476   },
6477
6478   /* PREFIX_VEX_0F3A22 */
6479   {
6480     { Bad_Opcode },
6481     { Bad_Opcode },
6482     { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6483   },
6484
6485   /* PREFIX_VEX_0F3A30 */
6486   {
6487     { Bad_Opcode },
6488     { Bad_Opcode },
6489     { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6490   },
6491
6492   /* PREFIX_VEX_0F3A31 */
6493   {
6494     { Bad_Opcode },
6495     { Bad_Opcode },
6496     { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6497   },
6498
6499   /* PREFIX_VEX_0F3A32 */
6500   {
6501     { Bad_Opcode },
6502     { Bad_Opcode },
6503     { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6504   },
6505
6506   /* PREFIX_VEX_0F3A33 */
6507   {
6508     { Bad_Opcode },
6509     { Bad_Opcode },
6510     { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6511   },
6512
6513   /* PREFIX_VEX_0F3A38 */
6514   {
6515     { Bad_Opcode },
6516     { Bad_Opcode },
6517     { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6518   },
6519
6520   /* PREFIX_VEX_0F3A39 */
6521   {
6522     { Bad_Opcode },
6523     { Bad_Opcode },
6524     { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6525   },
6526
6527   /* PREFIX_VEX_0F3A40 */
6528   {
6529     { Bad_Opcode },
6530     { Bad_Opcode },
6531     { VEX_W_TABLE (VEX_W_0F3A40_P_2) },
6532   },
6533
6534   /* PREFIX_VEX_0F3A41 */
6535   {
6536     { Bad_Opcode },
6537     { Bad_Opcode },
6538     { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6539   },
6540
6541   /* PREFIX_VEX_0F3A42 */
6542   {
6543     { Bad_Opcode },
6544     { Bad_Opcode },
6545     { VEX_W_TABLE (VEX_W_0F3A42_P_2) },
6546   },
6547
6548   /* PREFIX_VEX_0F3A44 */
6549   {
6550     { Bad_Opcode },
6551     { Bad_Opcode },
6552     { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2) },
6553   },
6554
6555   /* PREFIX_VEX_0F3A46 */
6556   {
6557     { Bad_Opcode },
6558     { Bad_Opcode },
6559     { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6560   },
6561
6562   /* PREFIX_VEX_0F3A48 */
6563   {
6564     { Bad_Opcode },
6565     { Bad_Opcode },
6566     { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6567   },
6568
6569   /* PREFIX_VEX_0F3A49 */
6570   {
6571     { Bad_Opcode },
6572     { Bad_Opcode },
6573     { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6574   },
6575
6576   /* PREFIX_VEX_0F3A4A */
6577   {
6578     { Bad_Opcode },
6579     { Bad_Opcode },
6580     { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6581   },
6582
6583   /* PREFIX_VEX_0F3A4B */
6584   {
6585     { Bad_Opcode },
6586     { Bad_Opcode },
6587     { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6588   },
6589
6590   /* PREFIX_VEX_0F3A4C */
6591   {
6592     { Bad_Opcode },
6593     { Bad_Opcode },
6594     { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6595   },
6596
6597   /* PREFIX_VEX_0F3A5C */
6598   {
6599     { Bad_Opcode },
6600     { Bad_Opcode },
6601     { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6602   },
6603
6604   /* PREFIX_VEX_0F3A5D */
6605   {
6606     { Bad_Opcode },
6607     { Bad_Opcode },
6608     { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6609   },
6610
6611   /* PREFIX_VEX_0F3A5E */
6612   {
6613     { Bad_Opcode },
6614     { Bad_Opcode },
6615     { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6616   },
6617
6618   /* PREFIX_VEX_0F3A5F */
6619   {
6620     { Bad_Opcode },
6621     { Bad_Opcode },
6622     { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6623   },
6624
6625   /* PREFIX_VEX_0F3A60 */
6626   {
6627     { Bad_Opcode },
6628     { Bad_Opcode },
6629     { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6630     { Bad_Opcode },
6631   },
6632
6633   /* PREFIX_VEX_0F3A61 */
6634   {
6635     { Bad_Opcode },
6636     { Bad_Opcode },
6637     { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6638   },
6639
6640   /* PREFIX_VEX_0F3A62 */
6641   {
6642     { Bad_Opcode },
6643     { Bad_Opcode },
6644     { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6645   },
6646
6647   /* PREFIX_VEX_0F3A63 */
6648   {
6649     { Bad_Opcode },
6650     { Bad_Opcode },
6651     { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6652   },
6653
6654   /* PREFIX_VEX_0F3A68 */
6655   {
6656     { Bad_Opcode },
6657     { Bad_Opcode },
6658     { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6659   },
6660
6661   /* PREFIX_VEX_0F3A69 */
6662   {
6663     { Bad_Opcode },
6664     { Bad_Opcode },
6665     { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6666   },
6667
6668   /* PREFIX_VEX_0F3A6A */
6669   {
6670     { Bad_Opcode },
6671     { Bad_Opcode },
6672     { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6673   },
6674
6675   /* PREFIX_VEX_0F3A6B */
6676   {
6677     { Bad_Opcode },
6678     { Bad_Opcode },
6679     { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6680   },
6681
6682   /* PREFIX_VEX_0F3A6C */
6683   {
6684     { Bad_Opcode },
6685     { Bad_Opcode },
6686     { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6687   },
6688
6689   /* PREFIX_VEX_0F3A6D */
6690   {
6691     { Bad_Opcode },
6692     { Bad_Opcode },
6693     { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6694   },
6695
6696   /* PREFIX_VEX_0F3A6E */
6697   {
6698     { Bad_Opcode },
6699     { Bad_Opcode },
6700     { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6701   },
6702
6703   /* PREFIX_VEX_0F3A6F */
6704   {
6705     { Bad_Opcode },
6706     { Bad_Opcode },
6707     { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6708   },
6709
6710   /* PREFIX_VEX_0F3A78 */
6711   {
6712     { Bad_Opcode },
6713     { Bad_Opcode },
6714     { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6715   },
6716
6717   /* PREFIX_VEX_0F3A79 */
6718   {
6719     { Bad_Opcode },
6720     { Bad_Opcode },
6721     { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6722   },
6723
6724   /* PREFIX_VEX_0F3A7A */
6725   {
6726     { Bad_Opcode },
6727     { Bad_Opcode },
6728     { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6729   },
6730
6731   /* PREFIX_VEX_0F3A7B */
6732   {
6733     { Bad_Opcode },
6734     { Bad_Opcode },
6735     { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6736   },
6737
6738   /* PREFIX_VEX_0F3A7C */
6739   {
6740     { Bad_Opcode },
6741     { Bad_Opcode },
6742     { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6743     { Bad_Opcode },
6744   },
6745
6746   /* PREFIX_VEX_0F3A7D */
6747   {
6748     { Bad_Opcode },
6749     { Bad_Opcode },
6750     { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6751   },
6752
6753   /* PREFIX_VEX_0F3A7E */
6754   {
6755     { Bad_Opcode },
6756     { Bad_Opcode },
6757     { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6758   },
6759
6760   /* PREFIX_VEX_0F3A7F */
6761   {
6762     { Bad_Opcode },
6763     { Bad_Opcode },
6764     { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6765   },
6766
6767   /* PREFIX_VEX_0F3ADF */
6768   {
6769     { Bad_Opcode },
6770     { Bad_Opcode },
6771     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6772   },
6773
6774   /* PREFIX_VEX_0F3AF0 */
6775   {
6776     { Bad_Opcode },
6777     { Bad_Opcode },
6778     { Bad_Opcode },
6779     { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6780   },
6781
6782 #define NEED_PREFIX_TABLE
6783 #include "i386-dis-evex.h"
6784 #undef NEED_PREFIX_TABLE
6785 };
6786
6787 static const struct dis386 x86_64_table[][2] = {
6788   /* X86_64_06 */
6789   {
6790     { "pushP", { es }, 0 },
6791   },
6792
6793   /* X86_64_07 */
6794   {
6795     { "popP", { es }, 0 },
6796   },
6797
6798   /* X86_64_0D */
6799   {
6800     { "pushP", { cs }, 0 },
6801   },
6802
6803   /* X86_64_16 */
6804   {
6805     { "pushP", { ss }, 0 },
6806   },
6807
6808   /* X86_64_17 */
6809   {
6810     { "popP", { ss }, 0 },
6811   },
6812
6813   /* X86_64_1E */
6814   {
6815     { "pushP", { ds }, 0 },
6816   },
6817
6818   /* X86_64_1F */
6819   {
6820     { "popP", { ds }, 0 },
6821   },
6822
6823   /* X86_64_27 */
6824   {
6825     { "daa", { XX }, 0 },
6826   },
6827
6828   /* X86_64_2F */
6829   {
6830     { "das", { XX }, 0 },
6831   },
6832
6833   /* X86_64_37 */
6834   {
6835     { "aaa", { XX }, 0 },
6836   },
6837
6838   /* X86_64_3F */
6839   {
6840     { "aas", { XX }, 0 },
6841   },
6842
6843   /* X86_64_60 */
6844   {
6845     { "pushaP", { XX }, 0 },
6846   },
6847
6848   /* X86_64_61 */
6849   {
6850     { "popaP", { XX }, 0 },
6851   },
6852
6853   /* X86_64_62 */
6854   {
6855     { MOD_TABLE (MOD_62_32BIT) },
6856     { EVEX_TABLE (EVEX_0F) },
6857   },
6858
6859   /* X86_64_63 */
6860   {
6861     { "arpl", { Ew, Gw }, 0 },
6862     { "movs{lq|xd}", { Gv, Ed }, 0 },
6863   },
6864
6865   /* X86_64_6D */
6866   {
6867     { "ins{R|}", { Yzr, indirDX }, 0 },
6868     { "ins{G|}", { Yzr, indirDX }, 0 },
6869   },
6870
6871   /* X86_64_6F */
6872   {
6873     { "outs{R|}", { indirDXr, Xz }, 0 },
6874     { "outs{G|}", { indirDXr, Xz }, 0 },
6875   },
6876
6877   /* X86_64_9A */
6878   {
6879     { "Jcall{T|}", { Ap }, 0 },
6880   },
6881
6882   /* X86_64_C4 */
6883   {
6884     { MOD_TABLE (MOD_C4_32BIT) },
6885     { VEX_C4_TABLE (VEX_0F) },
6886   },
6887
6888   /* X86_64_C5 */
6889   {
6890     { MOD_TABLE (MOD_C5_32BIT) },
6891     { VEX_C5_TABLE (VEX_0F) },
6892   },
6893
6894   /* X86_64_CE */
6895   {
6896     { "into", { XX }, 0 },
6897   },
6898
6899   /* X86_64_D4 */
6900   {
6901     { "aam", { Ib }, 0 },
6902   },
6903
6904   /* X86_64_D5 */
6905   {
6906     { "aad", { Ib }, 0 },
6907   },
6908
6909   /* X86_64_E8 */
6910   {
6911     { "callP",          { Jv, BND }, 0 },
6912     { "call@",          { Jv, BND }, 0 }
6913   },
6914
6915   /* X86_64_E9 */
6916   {
6917     { "jmpP",           { Jv, BND }, 0 },
6918     { "jmp@",           { Jv, BND }, 0 }
6919   },
6920
6921   /* X86_64_EA */
6922   {
6923     { "Jjmp{T|}", { Ap }, 0 },
6924   },
6925
6926   /* X86_64_0F01_REG_0 */
6927   {
6928     { "sgdt{Q|IQ}", { M }, 0 },
6929     { "sgdt", { M }, 0 },
6930   },
6931
6932   /* X86_64_0F01_REG_1 */
6933   {
6934     { "sidt{Q|IQ}", { M }, 0 },
6935     { "sidt", { M }, 0 },
6936   },
6937
6938   /* X86_64_0F01_REG_2 */
6939   {
6940     { "lgdt{Q|Q}", { M }, 0 },
6941     { "lgdt", { M }, 0 },
6942   },
6943
6944   /* X86_64_0F01_REG_3 */
6945   {
6946     { "lidt{Q|Q}", { M }, 0 },
6947     { "lidt", { M }, 0 },
6948   },
6949 };
6950
6951 static const struct dis386 three_byte_table[][256] = {
6952
6953   /* THREE_BYTE_0F38 */
6954   {
6955     /* 00 */
6956     { "pshufb",         { MX, EM }, PREFIX_OPCODE },
6957     { "phaddw",         { MX, EM }, PREFIX_OPCODE },
6958     { "phaddd",         { MX, EM }, PREFIX_OPCODE },
6959     { "phaddsw",        { MX, EM }, PREFIX_OPCODE },
6960     { "pmaddubsw",      { MX, EM }, PREFIX_OPCODE },
6961     { "phsubw",         { MX, EM }, PREFIX_OPCODE },
6962     { "phsubd",         { MX, EM }, PREFIX_OPCODE },
6963     { "phsubsw",        { MX, EM }, PREFIX_OPCODE },
6964     /* 08 */
6965     { "psignb",         { MX, EM }, PREFIX_OPCODE },
6966     { "psignw",         { MX, EM }, PREFIX_OPCODE },
6967     { "psignd",         { MX, EM }, PREFIX_OPCODE },
6968     { "pmulhrsw",       { MX, EM }, PREFIX_OPCODE },
6969     { Bad_Opcode },
6970     { Bad_Opcode },
6971     { Bad_Opcode },
6972     { Bad_Opcode },
6973     /* 10 */
6974     { PREFIX_TABLE (PREFIX_0F3810) },
6975     { Bad_Opcode },
6976     { Bad_Opcode },
6977     { Bad_Opcode },
6978     { PREFIX_TABLE (PREFIX_0F3814) },
6979     { PREFIX_TABLE (PREFIX_0F3815) },
6980     { Bad_Opcode },
6981     { PREFIX_TABLE (PREFIX_0F3817) },
6982     /* 18 */
6983     { Bad_Opcode },
6984     { Bad_Opcode },
6985     { Bad_Opcode },
6986     { Bad_Opcode },
6987     { "pabsb",          { MX, EM }, PREFIX_OPCODE },
6988     { "pabsw",          { MX, EM }, PREFIX_OPCODE },
6989     { "pabsd",          { MX, EM }, PREFIX_OPCODE },
6990     { Bad_Opcode },
6991     /* 20 */
6992     { PREFIX_TABLE (PREFIX_0F3820) },
6993     { PREFIX_TABLE (PREFIX_0F3821) },
6994     { PREFIX_TABLE (PREFIX_0F3822) },
6995     { PREFIX_TABLE (PREFIX_0F3823) },
6996     { PREFIX_TABLE (PREFIX_0F3824) },
6997     { PREFIX_TABLE (PREFIX_0F3825) },
6998     { Bad_Opcode },
6999     { Bad_Opcode },
7000     /* 28 */
7001     { PREFIX_TABLE (PREFIX_0F3828) },
7002     { PREFIX_TABLE (PREFIX_0F3829) },
7003     { PREFIX_TABLE (PREFIX_0F382A) },
7004     { PREFIX_TABLE (PREFIX_0F382B) },
7005     { Bad_Opcode },
7006     { Bad_Opcode },
7007     { Bad_Opcode },
7008     { Bad_Opcode },
7009     /* 30 */
7010     { PREFIX_TABLE (PREFIX_0F3830) },
7011     { PREFIX_TABLE (PREFIX_0F3831) },
7012     { PREFIX_TABLE (PREFIX_0F3832) },
7013     { PREFIX_TABLE (PREFIX_0F3833) },
7014     { PREFIX_TABLE (PREFIX_0F3834) },
7015     { PREFIX_TABLE (PREFIX_0F3835) },
7016     { Bad_Opcode },
7017     { PREFIX_TABLE (PREFIX_0F3837) },
7018     /* 38 */
7019     { PREFIX_TABLE (PREFIX_0F3838) },
7020     { PREFIX_TABLE (PREFIX_0F3839) },
7021     { PREFIX_TABLE (PREFIX_0F383A) },
7022     { PREFIX_TABLE (PREFIX_0F383B) },
7023     { PREFIX_TABLE (PREFIX_0F383C) },
7024     { PREFIX_TABLE (PREFIX_0F383D) },
7025     { PREFIX_TABLE (PREFIX_0F383E) },
7026     { PREFIX_TABLE (PREFIX_0F383F) },
7027     /* 40 */
7028     { PREFIX_TABLE (PREFIX_0F3840) },
7029     { PREFIX_TABLE (PREFIX_0F3841) },
7030     { Bad_Opcode },
7031     { Bad_Opcode },
7032     { Bad_Opcode },
7033     { Bad_Opcode },
7034     { Bad_Opcode },
7035     { Bad_Opcode },
7036     /* 48 */
7037     { Bad_Opcode },
7038     { Bad_Opcode },
7039     { Bad_Opcode },
7040     { Bad_Opcode },
7041     { Bad_Opcode },
7042     { Bad_Opcode },
7043     { Bad_Opcode },
7044     { Bad_Opcode },
7045     /* 50 */
7046     { Bad_Opcode },
7047     { Bad_Opcode },
7048     { Bad_Opcode },
7049     { Bad_Opcode },
7050     { Bad_Opcode },
7051     { Bad_Opcode },
7052     { Bad_Opcode },
7053     { Bad_Opcode },
7054     /* 58 */
7055     { Bad_Opcode },
7056     { Bad_Opcode },
7057     { Bad_Opcode },
7058     { Bad_Opcode },
7059     { Bad_Opcode },
7060     { Bad_Opcode },
7061     { Bad_Opcode },
7062     { Bad_Opcode },
7063     /* 60 */
7064     { Bad_Opcode },
7065     { Bad_Opcode },
7066     { Bad_Opcode },
7067     { Bad_Opcode },
7068     { Bad_Opcode },
7069     { Bad_Opcode },
7070     { Bad_Opcode },
7071     { Bad_Opcode },
7072     /* 68 */
7073     { Bad_Opcode },
7074     { Bad_Opcode },
7075     { Bad_Opcode },
7076     { Bad_Opcode },
7077     { Bad_Opcode },
7078     { Bad_Opcode },
7079     { Bad_Opcode },
7080     { Bad_Opcode },
7081     /* 70 */
7082     { Bad_Opcode },
7083     { Bad_Opcode },
7084     { Bad_Opcode },
7085     { Bad_Opcode },
7086     { Bad_Opcode },
7087     { Bad_Opcode },
7088     { Bad_Opcode },
7089     { Bad_Opcode },
7090     /* 78 */
7091     { Bad_Opcode },
7092     { Bad_Opcode },
7093     { Bad_Opcode },
7094     { Bad_Opcode },
7095     { Bad_Opcode },
7096     { Bad_Opcode },
7097     { Bad_Opcode },
7098     { Bad_Opcode },
7099     /* 80 */
7100     { PREFIX_TABLE (PREFIX_0F3880) },
7101     { PREFIX_TABLE (PREFIX_0F3881) },
7102     { PREFIX_TABLE (PREFIX_0F3882) },
7103     { Bad_Opcode },
7104     { Bad_Opcode },
7105     { Bad_Opcode },
7106     { Bad_Opcode },
7107     { Bad_Opcode },
7108     /* 88 */
7109     { Bad_Opcode },
7110     { Bad_Opcode },
7111     { Bad_Opcode },
7112     { Bad_Opcode },
7113     { Bad_Opcode },
7114     { Bad_Opcode },
7115     { Bad_Opcode },
7116     { Bad_Opcode },
7117     /* 90 */
7118     { Bad_Opcode },
7119     { Bad_Opcode },
7120     { Bad_Opcode },
7121     { Bad_Opcode },
7122     { Bad_Opcode },
7123     { Bad_Opcode },
7124     { Bad_Opcode },
7125     { Bad_Opcode },
7126     /* 98 */
7127     { Bad_Opcode },
7128     { Bad_Opcode },
7129     { Bad_Opcode },
7130     { Bad_Opcode },
7131     { Bad_Opcode },
7132     { Bad_Opcode },
7133     { Bad_Opcode },
7134     { Bad_Opcode },
7135     /* a0 */
7136     { Bad_Opcode },
7137     { Bad_Opcode },
7138     { Bad_Opcode },
7139     { Bad_Opcode },
7140     { Bad_Opcode },
7141     { Bad_Opcode },
7142     { Bad_Opcode },
7143     { Bad_Opcode },
7144     /* a8 */
7145     { Bad_Opcode },
7146     { Bad_Opcode },
7147     { Bad_Opcode },
7148     { Bad_Opcode },
7149     { Bad_Opcode },
7150     { Bad_Opcode },
7151     { Bad_Opcode },
7152     { Bad_Opcode },
7153     /* b0 */
7154     { Bad_Opcode },
7155     { Bad_Opcode },
7156     { Bad_Opcode },
7157     { Bad_Opcode },
7158     { Bad_Opcode },
7159     { Bad_Opcode },
7160     { Bad_Opcode },
7161     { Bad_Opcode },
7162     /* b8 */
7163     { Bad_Opcode },
7164     { Bad_Opcode },
7165     { Bad_Opcode },
7166     { Bad_Opcode },
7167     { Bad_Opcode },
7168     { Bad_Opcode },
7169     { Bad_Opcode },
7170     { Bad_Opcode },
7171     /* c0 */
7172     { Bad_Opcode },
7173     { Bad_Opcode },
7174     { Bad_Opcode },
7175     { Bad_Opcode },
7176     { Bad_Opcode },
7177     { Bad_Opcode },
7178     { Bad_Opcode },
7179     { Bad_Opcode },
7180     /* c8 */
7181     { PREFIX_TABLE (PREFIX_0F38C8) },
7182     { PREFIX_TABLE (PREFIX_0F38C9) },
7183     { PREFIX_TABLE (PREFIX_0F38CA) },
7184     { PREFIX_TABLE (PREFIX_0F38CB) },
7185     { PREFIX_TABLE (PREFIX_0F38CC) },
7186     { PREFIX_TABLE (PREFIX_0F38CD) },
7187     { Bad_Opcode },
7188     { Bad_Opcode },
7189     /* d0 */
7190     { Bad_Opcode },
7191     { Bad_Opcode },
7192     { Bad_Opcode },
7193     { Bad_Opcode },
7194     { Bad_Opcode },
7195     { Bad_Opcode },
7196     { Bad_Opcode },
7197     { Bad_Opcode },
7198     /* d8 */
7199     { Bad_Opcode },
7200     { Bad_Opcode },
7201     { Bad_Opcode },
7202     { PREFIX_TABLE (PREFIX_0F38DB) },
7203     { PREFIX_TABLE (PREFIX_0F38DC) },
7204     { PREFIX_TABLE (PREFIX_0F38DD) },
7205     { PREFIX_TABLE (PREFIX_0F38DE) },
7206     { PREFIX_TABLE (PREFIX_0F38DF) },
7207     /* e0 */
7208     { Bad_Opcode },
7209     { Bad_Opcode },
7210     { Bad_Opcode },
7211     { Bad_Opcode },
7212     { Bad_Opcode },
7213     { Bad_Opcode },
7214     { Bad_Opcode },
7215     { Bad_Opcode },
7216     /* e8 */
7217     { Bad_Opcode },
7218     { Bad_Opcode },
7219     { Bad_Opcode },
7220     { Bad_Opcode },
7221     { Bad_Opcode },
7222     { Bad_Opcode },
7223     { Bad_Opcode },
7224     { Bad_Opcode },
7225     /* f0 */
7226     { PREFIX_TABLE (PREFIX_0F38F0) },
7227     { PREFIX_TABLE (PREFIX_0F38F1) },
7228     { Bad_Opcode },
7229     { Bad_Opcode },
7230     { Bad_Opcode },
7231     { Bad_Opcode },
7232     { PREFIX_TABLE (PREFIX_0F38F6) },
7233     { Bad_Opcode },
7234     /* f8 */
7235     { Bad_Opcode },
7236     { Bad_Opcode },
7237     { Bad_Opcode },
7238     { Bad_Opcode },
7239     { Bad_Opcode },
7240     { Bad_Opcode },
7241     { Bad_Opcode },
7242     { Bad_Opcode },
7243   },
7244   /* THREE_BYTE_0F3A */
7245   {
7246     /* 00 */
7247     { Bad_Opcode },
7248     { Bad_Opcode },
7249     { Bad_Opcode },
7250     { Bad_Opcode },
7251     { Bad_Opcode },
7252     { Bad_Opcode },
7253     { Bad_Opcode },
7254     { Bad_Opcode },
7255     /* 08 */
7256     { PREFIX_TABLE (PREFIX_0F3A08) },
7257     { PREFIX_TABLE (PREFIX_0F3A09) },
7258     { PREFIX_TABLE (PREFIX_0F3A0A) },
7259     { PREFIX_TABLE (PREFIX_0F3A0B) },
7260     { PREFIX_TABLE (PREFIX_0F3A0C) },
7261     { PREFIX_TABLE (PREFIX_0F3A0D) },
7262     { PREFIX_TABLE (PREFIX_0F3A0E) },
7263     { "palignr",        { MX, EM, Ib }, PREFIX_OPCODE },
7264     /* 10 */
7265     { Bad_Opcode },
7266     { Bad_Opcode },
7267     { Bad_Opcode },
7268     { Bad_Opcode },
7269     { PREFIX_TABLE (PREFIX_0F3A14) },
7270     { PREFIX_TABLE (PREFIX_0F3A15) },
7271     { PREFIX_TABLE (PREFIX_0F3A16) },
7272     { PREFIX_TABLE (PREFIX_0F3A17) },
7273     /* 18 */
7274     { Bad_Opcode },
7275     { Bad_Opcode },
7276     { Bad_Opcode },
7277     { Bad_Opcode },
7278     { Bad_Opcode },
7279     { Bad_Opcode },
7280     { Bad_Opcode },
7281     { Bad_Opcode },
7282     /* 20 */
7283     { PREFIX_TABLE (PREFIX_0F3A20) },
7284     { PREFIX_TABLE (PREFIX_0F3A21) },
7285     { PREFIX_TABLE (PREFIX_0F3A22) },
7286     { Bad_Opcode },
7287     { Bad_Opcode },
7288     { Bad_Opcode },
7289     { Bad_Opcode },
7290     { Bad_Opcode },
7291     /* 28 */
7292     { Bad_Opcode },
7293     { Bad_Opcode },
7294     { Bad_Opcode },
7295     { Bad_Opcode },
7296     { Bad_Opcode },
7297     { Bad_Opcode },
7298     { Bad_Opcode },
7299     { Bad_Opcode },
7300     /* 30 */
7301     { Bad_Opcode },
7302     { Bad_Opcode },
7303     { Bad_Opcode },
7304     { Bad_Opcode },
7305     { Bad_Opcode },
7306     { Bad_Opcode },
7307     { Bad_Opcode },
7308     { Bad_Opcode },
7309     /* 38 */
7310     { Bad_Opcode },
7311     { Bad_Opcode },
7312     { Bad_Opcode },
7313     { Bad_Opcode },
7314     { Bad_Opcode },
7315     { Bad_Opcode },
7316     { Bad_Opcode },
7317     { Bad_Opcode },
7318     /* 40 */
7319     { PREFIX_TABLE (PREFIX_0F3A40) },
7320     { PREFIX_TABLE (PREFIX_0F3A41) },
7321     { PREFIX_TABLE (PREFIX_0F3A42) },
7322     { Bad_Opcode },
7323     { PREFIX_TABLE (PREFIX_0F3A44) },
7324     { Bad_Opcode },
7325     { Bad_Opcode },
7326     { Bad_Opcode },
7327     /* 48 */
7328     { Bad_Opcode },
7329     { Bad_Opcode },
7330     { Bad_Opcode },
7331     { Bad_Opcode },
7332     { Bad_Opcode },
7333     { Bad_Opcode },
7334     { Bad_Opcode },
7335     { Bad_Opcode },
7336     /* 50 */
7337     { Bad_Opcode },
7338     { Bad_Opcode },
7339     { Bad_Opcode },
7340     { Bad_Opcode },
7341     { Bad_Opcode },
7342     { Bad_Opcode },
7343     { Bad_Opcode },
7344     { Bad_Opcode },
7345     /* 58 */
7346     { Bad_Opcode },
7347     { Bad_Opcode },
7348     { Bad_Opcode },
7349     { Bad_Opcode },
7350     { Bad_Opcode },
7351     { Bad_Opcode },
7352     { Bad_Opcode },
7353     { Bad_Opcode },
7354     /* 60 */
7355     { PREFIX_TABLE (PREFIX_0F3A60) },
7356     { PREFIX_TABLE (PREFIX_0F3A61) },
7357     { PREFIX_TABLE (PREFIX_0F3A62) },
7358     { PREFIX_TABLE (PREFIX_0F3A63) },
7359     { Bad_Opcode },
7360     { Bad_Opcode },
7361     { Bad_Opcode },
7362     { Bad_Opcode },
7363     /* 68 */
7364     { Bad_Opcode },
7365     { Bad_Opcode },
7366     { Bad_Opcode },
7367     { Bad_Opcode },
7368     { Bad_Opcode },
7369     { Bad_Opcode },
7370     { Bad_Opcode },
7371     { Bad_Opcode },
7372     /* 70 */
7373     { Bad_Opcode },
7374     { Bad_Opcode },
7375     { Bad_Opcode },
7376     { Bad_Opcode },
7377     { Bad_Opcode },
7378     { Bad_Opcode },
7379     { Bad_Opcode },
7380     { Bad_Opcode },
7381     /* 78 */
7382     { Bad_Opcode },
7383     { Bad_Opcode },
7384     { Bad_Opcode },
7385     { Bad_Opcode },
7386     { Bad_Opcode },
7387     { Bad_Opcode },
7388     { Bad_Opcode },
7389     { Bad_Opcode },
7390     /* 80 */
7391     { Bad_Opcode },
7392     { Bad_Opcode },
7393     { Bad_Opcode },
7394     { Bad_Opcode },
7395     { Bad_Opcode },
7396     { Bad_Opcode },
7397     { Bad_Opcode },
7398     { Bad_Opcode },
7399     /* 88 */
7400     { Bad_Opcode },
7401     { Bad_Opcode },
7402     { Bad_Opcode },
7403     { Bad_Opcode },
7404     { Bad_Opcode },
7405     { Bad_Opcode },
7406     { Bad_Opcode },
7407     { Bad_Opcode },
7408     /* 90 */
7409     { Bad_Opcode },
7410     { Bad_Opcode },
7411     { Bad_Opcode },
7412     { Bad_Opcode },
7413     { Bad_Opcode },
7414     { Bad_Opcode },
7415     { Bad_Opcode },
7416     { Bad_Opcode },
7417     /* 98 */
7418     { Bad_Opcode },
7419     { Bad_Opcode },
7420     { Bad_Opcode },
7421     { Bad_Opcode },
7422     { Bad_Opcode },
7423     { Bad_Opcode },
7424     { Bad_Opcode },
7425     { Bad_Opcode },
7426     /* a0 */
7427     { Bad_Opcode },
7428     { Bad_Opcode },
7429     { Bad_Opcode },
7430     { Bad_Opcode },
7431     { Bad_Opcode },
7432     { Bad_Opcode },
7433     { Bad_Opcode },
7434     { Bad_Opcode },
7435     /* a8 */
7436     { Bad_Opcode },
7437     { Bad_Opcode },
7438     { Bad_Opcode },
7439     { Bad_Opcode },
7440     { Bad_Opcode },
7441     { Bad_Opcode },
7442     { Bad_Opcode },
7443     { Bad_Opcode },
7444     /* b0 */
7445     { Bad_Opcode },
7446     { Bad_Opcode },
7447     { Bad_Opcode },
7448     { Bad_Opcode },
7449     { Bad_Opcode },
7450     { Bad_Opcode },
7451     { Bad_Opcode },
7452     { Bad_Opcode },
7453     /* b8 */
7454     { Bad_Opcode },
7455     { Bad_Opcode },
7456     { Bad_Opcode },
7457     { Bad_Opcode },
7458     { Bad_Opcode },
7459     { Bad_Opcode },
7460     { Bad_Opcode },
7461     { Bad_Opcode },
7462     /* c0 */
7463     { Bad_Opcode },
7464     { Bad_Opcode },
7465     { Bad_Opcode },
7466     { Bad_Opcode },
7467     { Bad_Opcode },
7468     { Bad_Opcode },
7469     { Bad_Opcode },
7470     { Bad_Opcode },
7471     /* c8 */
7472     { Bad_Opcode },
7473     { Bad_Opcode },
7474     { Bad_Opcode },
7475     { Bad_Opcode },
7476     { PREFIX_TABLE (PREFIX_0F3ACC) },
7477     { Bad_Opcode },
7478     { Bad_Opcode },
7479     { Bad_Opcode },
7480     /* d0 */
7481     { Bad_Opcode },
7482     { Bad_Opcode },
7483     { Bad_Opcode },
7484     { Bad_Opcode },
7485     { Bad_Opcode },
7486     { Bad_Opcode },
7487     { Bad_Opcode },
7488     { Bad_Opcode },
7489     /* d8 */
7490     { Bad_Opcode },
7491     { Bad_Opcode },
7492     { Bad_Opcode },
7493     { Bad_Opcode },
7494     { Bad_Opcode },
7495     { Bad_Opcode },
7496     { Bad_Opcode },
7497     { PREFIX_TABLE (PREFIX_0F3ADF) },
7498     /* e0 */
7499     { Bad_Opcode },
7500     { Bad_Opcode },
7501     { Bad_Opcode },
7502     { Bad_Opcode },
7503     { Bad_Opcode },
7504     { Bad_Opcode },
7505     { Bad_Opcode },
7506     { Bad_Opcode },
7507     /* e8 */
7508     { Bad_Opcode },
7509     { Bad_Opcode },
7510     { Bad_Opcode },
7511     { Bad_Opcode },
7512     { Bad_Opcode },
7513     { Bad_Opcode },
7514     { Bad_Opcode },
7515     { Bad_Opcode },
7516     /* f0 */
7517     { Bad_Opcode },
7518     { Bad_Opcode },
7519     { Bad_Opcode },
7520     { Bad_Opcode },
7521     { Bad_Opcode },
7522     { Bad_Opcode },
7523     { Bad_Opcode },
7524     { Bad_Opcode },
7525     /* f8 */
7526     { Bad_Opcode },
7527     { Bad_Opcode },
7528     { Bad_Opcode },
7529     { Bad_Opcode },
7530     { Bad_Opcode },
7531     { Bad_Opcode },
7532     { Bad_Opcode },
7533     { Bad_Opcode },
7534   },
7535
7536   /* THREE_BYTE_0F7A */
7537   {
7538     /* 00 */
7539     { Bad_Opcode },
7540     { Bad_Opcode },
7541     { Bad_Opcode },
7542     { Bad_Opcode },
7543     { Bad_Opcode },
7544     { Bad_Opcode },
7545     { Bad_Opcode },
7546     { Bad_Opcode },
7547     /* 08 */
7548     { Bad_Opcode },
7549     { Bad_Opcode },
7550     { Bad_Opcode },
7551     { Bad_Opcode },
7552     { Bad_Opcode },
7553     { Bad_Opcode },
7554     { Bad_Opcode },
7555     { Bad_Opcode },
7556     /* 10 */
7557     { Bad_Opcode },
7558     { Bad_Opcode },
7559     { Bad_Opcode },
7560     { Bad_Opcode },
7561     { Bad_Opcode },
7562     { Bad_Opcode },
7563     { Bad_Opcode },
7564     { Bad_Opcode },
7565     /* 18 */
7566     { Bad_Opcode },
7567     { Bad_Opcode },
7568     { Bad_Opcode },
7569     { Bad_Opcode },
7570     { Bad_Opcode },
7571     { Bad_Opcode },
7572     { Bad_Opcode },
7573     { Bad_Opcode },
7574     /* 20 */
7575     { "ptest",          { XX }, PREFIX_OPCODE },
7576     { Bad_Opcode },
7577     { Bad_Opcode },
7578     { Bad_Opcode },
7579     { Bad_Opcode },
7580     { Bad_Opcode },
7581     { Bad_Opcode },
7582     { Bad_Opcode },
7583     /* 28 */
7584     { Bad_Opcode },
7585     { Bad_Opcode },
7586     { Bad_Opcode },
7587     { Bad_Opcode },
7588     { Bad_Opcode },
7589     { Bad_Opcode },
7590     { Bad_Opcode },
7591     { Bad_Opcode },
7592     /* 30 */
7593     { Bad_Opcode },
7594     { Bad_Opcode },
7595     { Bad_Opcode },
7596     { Bad_Opcode },
7597     { Bad_Opcode },
7598     { Bad_Opcode },
7599     { Bad_Opcode },
7600     { Bad_Opcode },
7601     /* 38 */
7602     { Bad_Opcode },
7603     { Bad_Opcode },
7604     { Bad_Opcode },
7605     { Bad_Opcode },
7606     { Bad_Opcode },
7607     { Bad_Opcode },
7608     { Bad_Opcode },
7609     { Bad_Opcode },
7610     /* 40 */
7611     { Bad_Opcode },
7612     { "phaddbw",        { XM, EXq }, PREFIX_OPCODE },
7613     { "phaddbd",        { XM, EXq }, PREFIX_OPCODE },
7614     { "phaddbq",        { XM, EXq }, PREFIX_OPCODE },
7615     { Bad_Opcode },
7616     { Bad_Opcode },
7617     { "phaddwd",        { XM, EXq }, PREFIX_OPCODE },
7618     { "phaddwq",        { XM, EXq }, PREFIX_OPCODE },
7619     /* 48 */
7620     { Bad_Opcode },
7621     { Bad_Opcode },
7622     { Bad_Opcode },
7623     { "phadddq",        { XM, EXq }, PREFIX_OPCODE },
7624     { Bad_Opcode },
7625     { Bad_Opcode },
7626     { Bad_Opcode },
7627     { Bad_Opcode },
7628     /* 50 */
7629     { Bad_Opcode },
7630     { "phaddubw",       { XM, EXq }, PREFIX_OPCODE },
7631     { "phaddubd",       { XM, EXq }, PREFIX_OPCODE },
7632     { "phaddubq",       { XM, EXq }, PREFIX_OPCODE },
7633     { Bad_Opcode },
7634     { Bad_Opcode },
7635     { "phadduwd",       { XM, EXq }, PREFIX_OPCODE },
7636     { "phadduwq",       { XM, EXq }, PREFIX_OPCODE },
7637     /* 58 */
7638     { Bad_Opcode },
7639     { Bad_Opcode },
7640     { Bad_Opcode },
7641     { "phaddudq",       { XM, EXq }, PREFIX_OPCODE },
7642     { Bad_Opcode },
7643     { Bad_Opcode },
7644     { Bad_Opcode },
7645     { Bad_Opcode },
7646     /* 60 */
7647     { Bad_Opcode },
7648     { "phsubbw",        { XM, EXq }, PREFIX_OPCODE },
7649     { "phsubbd",        { XM, EXq }, PREFIX_OPCODE },
7650     { "phsubbq",        { XM, EXq }, PREFIX_OPCODE },
7651     { Bad_Opcode },
7652     { Bad_Opcode },
7653     { Bad_Opcode },
7654     { Bad_Opcode },
7655     /* 68 */
7656     { Bad_Opcode },
7657     { Bad_Opcode },
7658     { Bad_Opcode },
7659     { Bad_Opcode },
7660     { Bad_Opcode },
7661     { Bad_Opcode },
7662     { Bad_Opcode },
7663     { Bad_Opcode },
7664     /* 70 */
7665     { Bad_Opcode },
7666     { Bad_Opcode },
7667     { Bad_Opcode },
7668     { Bad_Opcode },
7669     { Bad_Opcode },
7670     { Bad_Opcode },
7671     { Bad_Opcode },
7672     { Bad_Opcode },
7673     /* 78 */
7674     { Bad_Opcode },
7675     { Bad_Opcode },
7676     { Bad_Opcode },
7677     { Bad_Opcode },
7678     { Bad_Opcode },
7679     { Bad_Opcode },
7680     { Bad_Opcode },
7681     { Bad_Opcode },
7682     /* 80 */
7683     { Bad_Opcode },
7684     { Bad_Opcode },
7685     { Bad_Opcode },
7686     { Bad_Opcode },
7687     { Bad_Opcode },
7688     { Bad_Opcode },
7689     { Bad_Opcode },
7690     { Bad_Opcode },
7691     /* 88 */
7692     { Bad_Opcode },
7693     { Bad_Opcode },
7694     { Bad_Opcode },
7695     { Bad_Opcode },
7696     { Bad_Opcode },
7697     { Bad_Opcode },
7698     { Bad_Opcode },
7699     { Bad_Opcode },
7700     /* 90 */
7701     { Bad_Opcode },
7702     { Bad_Opcode },
7703     { Bad_Opcode },
7704     { Bad_Opcode },
7705     { Bad_Opcode },
7706     { Bad_Opcode },
7707     { Bad_Opcode },
7708     { Bad_Opcode },
7709     /* 98 */
7710     { Bad_Opcode },
7711     { Bad_Opcode },
7712     { Bad_Opcode },
7713     { Bad_Opcode },
7714     { Bad_Opcode },
7715     { Bad_Opcode },
7716     { Bad_Opcode },
7717     { Bad_Opcode },
7718     /* a0 */
7719     { Bad_Opcode },
7720     { Bad_Opcode },
7721     { Bad_Opcode },
7722     { Bad_Opcode },
7723     { Bad_Opcode },
7724     { Bad_Opcode },
7725     { Bad_Opcode },
7726     { Bad_Opcode },
7727     /* a8 */
7728     { Bad_Opcode },
7729     { Bad_Opcode },
7730     { Bad_Opcode },
7731     { Bad_Opcode },
7732     { Bad_Opcode },
7733     { Bad_Opcode },
7734     { Bad_Opcode },
7735     { Bad_Opcode },
7736     /* b0 */
7737     { Bad_Opcode },
7738     { Bad_Opcode },
7739     { Bad_Opcode },
7740     { Bad_Opcode },
7741     { Bad_Opcode },
7742     { Bad_Opcode },
7743     { Bad_Opcode },
7744     { Bad_Opcode },
7745     /* b8 */
7746     { Bad_Opcode },
7747     { Bad_Opcode },
7748     { Bad_Opcode },
7749     { Bad_Opcode },
7750     { Bad_Opcode },
7751     { Bad_Opcode },
7752     { Bad_Opcode },
7753     { Bad_Opcode },
7754     /* c0 */
7755     { Bad_Opcode },
7756     { Bad_Opcode },
7757     { Bad_Opcode },
7758     { Bad_Opcode },
7759     { Bad_Opcode },
7760     { Bad_Opcode },
7761     { Bad_Opcode },
7762     { Bad_Opcode },
7763     /* c8 */
7764     { Bad_Opcode },
7765     { Bad_Opcode },
7766     { Bad_Opcode },
7767     { Bad_Opcode },
7768     { Bad_Opcode },
7769     { Bad_Opcode },
7770     { Bad_Opcode },
7771     { Bad_Opcode },
7772     /* d0 */
7773     { Bad_Opcode },
7774     { Bad_Opcode },
7775     { Bad_Opcode },
7776     { Bad_Opcode },
7777     { Bad_Opcode },
7778     { Bad_Opcode },
7779     { Bad_Opcode },
7780     { Bad_Opcode },
7781     /* d8 */
7782     { Bad_Opcode },
7783     { Bad_Opcode },
7784     { Bad_Opcode },
7785     { Bad_Opcode },
7786     { Bad_Opcode },
7787     { Bad_Opcode },
7788     { Bad_Opcode },
7789     { Bad_Opcode },
7790     /* e0 */
7791     { Bad_Opcode },
7792     { Bad_Opcode },
7793     { Bad_Opcode },
7794     { Bad_Opcode },
7795     { Bad_Opcode },
7796     { Bad_Opcode },
7797     { Bad_Opcode },
7798     { Bad_Opcode },
7799     /* e8 */
7800     { Bad_Opcode },
7801     { Bad_Opcode },
7802     { Bad_Opcode },
7803     { Bad_Opcode },
7804     { Bad_Opcode },
7805     { Bad_Opcode },
7806     { Bad_Opcode },
7807     { Bad_Opcode },
7808     /* f0 */
7809     { Bad_Opcode },
7810     { Bad_Opcode },
7811     { Bad_Opcode },
7812     { Bad_Opcode },
7813     { Bad_Opcode },
7814     { Bad_Opcode },
7815     { Bad_Opcode },
7816     { Bad_Opcode },
7817     /* f8 */
7818     { Bad_Opcode },
7819     { Bad_Opcode },
7820     { Bad_Opcode },
7821     { Bad_Opcode },
7822     { Bad_Opcode },
7823     { Bad_Opcode },
7824     { Bad_Opcode },
7825     { Bad_Opcode },
7826   },
7827 };
7828
7829 static const struct dis386 xop_table[][256] = {
7830   /* XOP_08 */
7831   {
7832     /* 00 */
7833     { Bad_Opcode },
7834     { Bad_Opcode },
7835     { Bad_Opcode },
7836     { Bad_Opcode },
7837     { Bad_Opcode },
7838     { Bad_Opcode },
7839     { Bad_Opcode },
7840     { Bad_Opcode },
7841     /* 08 */
7842     { Bad_Opcode },
7843     { Bad_Opcode },
7844     { Bad_Opcode },
7845     { Bad_Opcode },
7846     { Bad_Opcode },
7847     { Bad_Opcode },
7848     { Bad_Opcode },
7849     { Bad_Opcode },
7850     /* 10 */
7851     { Bad_Opcode },
7852     { Bad_Opcode },
7853     { Bad_Opcode },
7854     { Bad_Opcode },
7855     { Bad_Opcode },
7856     { Bad_Opcode },
7857     { Bad_Opcode },
7858     { Bad_Opcode },
7859     /* 18 */
7860     { Bad_Opcode },
7861     { Bad_Opcode },
7862     { Bad_Opcode },
7863     { Bad_Opcode },
7864     { Bad_Opcode },
7865     { Bad_Opcode },
7866     { Bad_Opcode },
7867     { Bad_Opcode },
7868     /* 20 */
7869     { Bad_Opcode },
7870     { Bad_Opcode },
7871     { Bad_Opcode },
7872     { Bad_Opcode },
7873     { Bad_Opcode },
7874     { Bad_Opcode },
7875     { Bad_Opcode },
7876     { Bad_Opcode },
7877     /* 28 */
7878     { Bad_Opcode },
7879     { Bad_Opcode },
7880     { Bad_Opcode },
7881     { Bad_Opcode },
7882     { Bad_Opcode },
7883     { Bad_Opcode },
7884     { Bad_Opcode },
7885     { Bad_Opcode },
7886     /* 30 */
7887     { Bad_Opcode },
7888     { Bad_Opcode },
7889     { Bad_Opcode },
7890     { Bad_Opcode },
7891     { Bad_Opcode },
7892     { Bad_Opcode },
7893     { Bad_Opcode },
7894     { Bad_Opcode },
7895     /* 38 */
7896     { Bad_Opcode },
7897     { Bad_Opcode },
7898     { Bad_Opcode },
7899     { Bad_Opcode },
7900     { Bad_Opcode },
7901     { Bad_Opcode },
7902     { Bad_Opcode },
7903     { Bad_Opcode },
7904     /* 40 */
7905     { Bad_Opcode },
7906     { Bad_Opcode },
7907     { Bad_Opcode },
7908     { Bad_Opcode },
7909     { Bad_Opcode },
7910     { Bad_Opcode },
7911     { Bad_Opcode },
7912     { Bad_Opcode },
7913     /* 48 */
7914     { Bad_Opcode },
7915     { Bad_Opcode },
7916     { Bad_Opcode },
7917     { Bad_Opcode },
7918     { Bad_Opcode },
7919     { Bad_Opcode },
7920     { Bad_Opcode },
7921     { Bad_Opcode },
7922     /* 50 */
7923     { Bad_Opcode },
7924     { Bad_Opcode },
7925     { Bad_Opcode },
7926     { Bad_Opcode },
7927     { Bad_Opcode },
7928     { Bad_Opcode },
7929     { Bad_Opcode },
7930     { Bad_Opcode },
7931     /* 58 */
7932     { Bad_Opcode },
7933     { Bad_Opcode },
7934     { Bad_Opcode },
7935     { Bad_Opcode },
7936     { Bad_Opcode },
7937     { Bad_Opcode },
7938     { Bad_Opcode },
7939     { Bad_Opcode },
7940     /* 60 */
7941     { Bad_Opcode },
7942     { Bad_Opcode },
7943     { Bad_Opcode },
7944     { Bad_Opcode },
7945     { Bad_Opcode },
7946     { Bad_Opcode },
7947     { Bad_Opcode },
7948     { Bad_Opcode },
7949     /* 68 */
7950     { Bad_Opcode },
7951     { Bad_Opcode },
7952     { Bad_Opcode },
7953     { Bad_Opcode },
7954     { Bad_Opcode },
7955     { Bad_Opcode },
7956     { Bad_Opcode },
7957     { Bad_Opcode },
7958     /* 70 */
7959     { Bad_Opcode },
7960     { Bad_Opcode },
7961     { Bad_Opcode },
7962     { Bad_Opcode },
7963     { Bad_Opcode },
7964     { Bad_Opcode },
7965     { Bad_Opcode },
7966     { Bad_Opcode },
7967     /* 78 */
7968     { Bad_Opcode },
7969     { Bad_Opcode },
7970     { Bad_Opcode },
7971     { Bad_Opcode },
7972     { Bad_Opcode },
7973     { Bad_Opcode },
7974     { Bad_Opcode },
7975     { Bad_Opcode },
7976     /* 80 */
7977     { Bad_Opcode },
7978     { Bad_Opcode },
7979     { Bad_Opcode },
7980     { Bad_Opcode },
7981     { Bad_Opcode },
7982     { "vpmacssww",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7983     { "vpmacsswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7984     { "vpmacssdql",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7985     /* 88 */
7986     { Bad_Opcode },
7987     { Bad_Opcode },
7988     { Bad_Opcode },
7989     { Bad_Opcode },
7990     { Bad_Opcode },
7991     { Bad_Opcode },
7992     { "vpmacssdd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7993     { "vpmacssdqh",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7994     /* 90 */
7995     { Bad_Opcode },
7996     { Bad_Opcode },
7997     { Bad_Opcode },
7998     { Bad_Opcode },
7999     { Bad_Opcode },
8000     { "vpmacsww",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
8001     { "vpmacswd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
8002     { "vpmacsdql",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
8003     /* 98 */
8004     { Bad_Opcode },
8005     { Bad_Opcode },
8006     { Bad_Opcode },
8007     { Bad_Opcode },
8008     { Bad_Opcode },
8009     { Bad_Opcode },
8010     { "vpmacsdd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
8011     { "vpmacsdqh",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
8012     /* a0 */
8013     { Bad_Opcode },
8014     { Bad_Opcode },
8015     { "vpcmov",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
8016     { "vpperm",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
8017     { Bad_Opcode },
8018     { Bad_Opcode },
8019     { "vpmadcsswd",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
8020     { Bad_Opcode },
8021     /* a8 */
8022     { Bad_Opcode },
8023     { Bad_Opcode },
8024     { Bad_Opcode },
8025     { Bad_Opcode },
8026     { Bad_Opcode },
8027     { Bad_Opcode },
8028     { Bad_Opcode },
8029     { Bad_Opcode },
8030     /* b0 */
8031     { Bad_Opcode },
8032     { Bad_Opcode },
8033     { Bad_Opcode },
8034     { Bad_Opcode },
8035     { Bad_Opcode },
8036     { Bad_Opcode },
8037     { "vpmadcswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
8038     { Bad_Opcode },
8039     /* b8 */
8040     { Bad_Opcode },
8041     { Bad_Opcode },
8042     { Bad_Opcode },
8043     { Bad_Opcode },
8044     { Bad_Opcode },
8045     { Bad_Opcode },
8046     { Bad_Opcode },
8047     { Bad_Opcode },
8048     /* c0 */
8049     { "vprotb",         { XM, Vex_2src_1, Ib }, 0 },
8050     { "vprotw",         { XM, Vex_2src_1, Ib }, 0 },
8051     { "vprotd",         { XM, Vex_2src_1, Ib }, 0 },
8052     { "vprotq",         { XM, Vex_2src_1, Ib }, 0 },
8053     { Bad_Opcode },
8054     { Bad_Opcode },
8055     { Bad_Opcode },
8056     { Bad_Opcode },
8057     /* c8 */
8058     { Bad_Opcode },
8059     { Bad_Opcode },
8060     { Bad_Opcode },
8061     { Bad_Opcode },
8062     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
8063     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
8064     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
8065     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
8066     /* d0 */
8067     { Bad_Opcode },
8068     { Bad_Opcode },
8069     { Bad_Opcode },
8070     { Bad_Opcode },
8071     { Bad_Opcode },
8072     { Bad_Opcode },
8073     { Bad_Opcode },
8074     { Bad_Opcode },
8075     /* d8 */
8076     { Bad_Opcode },
8077     { Bad_Opcode },
8078     { Bad_Opcode },
8079     { Bad_Opcode },
8080     { Bad_Opcode },
8081     { Bad_Opcode },
8082     { Bad_Opcode },
8083     { Bad_Opcode },
8084     /* e0 */
8085     { Bad_Opcode },
8086     { Bad_Opcode },
8087     { Bad_Opcode },
8088     { Bad_Opcode },
8089     { Bad_Opcode },
8090     { Bad_Opcode },
8091     { Bad_Opcode },
8092     { Bad_Opcode },
8093     /* e8 */
8094     { Bad_Opcode },
8095     { Bad_Opcode },
8096     { Bad_Opcode },
8097     { Bad_Opcode },
8098     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
8099     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
8100     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
8101     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
8102     /* f0 */
8103     { Bad_Opcode },
8104     { Bad_Opcode },
8105     { Bad_Opcode },
8106     { Bad_Opcode },
8107     { Bad_Opcode },
8108     { Bad_Opcode },
8109     { Bad_Opcode },
8110     { Bad_Opcode },
8111     /* f8 */
8112     { Bad_Opcode },
8113     { Bad_Opcode },
8114     { Bad_Opcode },
8115     { Bad_Opcode },
8116     { Bad_Opcode },
8117     { Bad_Opcode },
8118     { Bad_Opcode },
8119     { Bad_Opcode },
8120   },
8121   /* XOP_09 */
8122   {
8123     /* 00 */
8124     { Bad_Opcode },
8125     { REG_TABLE (REG_XOP_TBM_01) },
8126     { REG_TABLE (REG_XOP_TBM_02) },
8127     { Bad_Opcode },
8128     { Bad_Opcode },
8129     { Bad_Opcode },
8130     { Bad_Opcode },
8131     { Bad_Opcode },
8132     /* 08 */
8133     { Bad_Opcode },
8134     { Bad_Opcode },
8135     { Bad_Opcode },
8136     { Bad_Opcode },
8137     { Bad_Opcode },
8138     { Bad_Opcode },
8139     { Bad_Opcode },
8140     { Bad_Opcode },
8141     /* 10 */
8142     { Bad_Opcode },
8143     { Bad_Opcode },
8144     { REG_TABLE (REG_XOP_LWPCB) },
8145     { Bad_Opcode },
8146     { Bad_Opcode },
8147     { Bad_Opcode },
8148     { Bad_Opcode },
8149     { Bad_Opcode },
8150     /* 18 */
8151     { Bad_Opcode },
8152     { Bad_Opcode },
8153     { Bad_Opcode },
8154     { Bad_Opcode },
8155     { Bad_Opcode },
8156     { Bad_Opcode },
8157     { Bad_Opcode },
8158     { Bad_Opcode },
8159     /* 20 */
8160     { Bad_Opcode },
8161     { Bad_Opcode },
8162     { Bad_Opcode },
8163     { Bad_Opcode },
8164     { Bad_Opcode },
8165     { Bad_Opcode },
8166     { Bad_Opcode },
8167     { Bad_Opcode },
8168     /* 28 */
8169     { Bad_Opcode },
8170     { Bad_Opcode },
8171     { Bad_Opcode },
8172     { Bad_Opcode },
8173     { Bad_Opcode },
8174     { Bad_Opcode },
8175     { Bad_Opcode },
8176     { Bad_Opcode },
8177     /* 30 */
8178     { Bad_Opcode },
8179     { Bad_Opcode },
8180     { Bad_Opcode },
8181     { Bad_Opcode },
8182     { Bad_Opcode },
8183     { Bad_Opcode },
8184     { Bad_Opcode },
8185     { Bad_Opcode },
8186     /* 38 */
8187     { Bad_Opcode },
8188     { Bad_Opcode },
8189     { Bad_Opcode },
8190     { Bad_Opcode },
8191     { Bad_Opcode },
8192     { Bad_Opcode },
8193     { Bad_Opcode },
8194     { Bad_Opcode },
8195     /* 40 */
8196     { Bad_Opcode },
8197     { Bad_Opcode },
8198     { Bad_Opcode },
8199     { Bad_Opcode },
8200     { Bad_Opcode },
8201     { Bad_Opcode },
8202     { Bad_Opcode },
8203     { Bad_Opcode },
8204     /* 48 */
8205     { Bad_Opcode },
8206     { Bad_Opcode },
8207     { Bad_Opcode },
8208     { Bad_Opcode },
8209     { Bad_Opcode },
8210     { Bad_Opcode },
8211     { Bad_Opcode },
8212     { Bad_Opcode },
8213     /* 50 */
8214     { Bad_Opcode },
8215     { Bad_Opcode },
8216     { Bad_Opcode },
8217     { Bad_Opcode },
8218     { Bad_Opcode },
8219     { Bad_Opcode },
8220     { Bad_Opcode },
8221     { Bad_Opcode },
8222     /* 58 */
8223     { Bad_Opcode },
8224     { Bad_Opcode },
8225     { Bad_Opcode },
8226     { Bad_Opcode },
8227     { Bad_Opcode },
8228     { Bad_Opcode },
8229     { Bad_Opcode },
8230     { Bad_Opcode },
8231     /* 60 */
8232     { Bad_Opcode },
8233     { Bad_Opcode },
8234     { Bad_Opcode },
8235     { Bad_Opcode },
8236     { Bad_Opcode },
8237     { Bad_Opcode },
8238     { Bad_Opcode },
8239     { Bad_Opcode },
8240     /* 68 */
8241     { Bad_Opcode },
8242     { Bad_Opcode },
8243     { Bad_Opcode },
8244     { Bad_Opcode },
8245     { Bad_Opcode },
8246     { Bad_Opcode },
8247     { Bad_Opcode },
8248     { Bad_Opcode },
8249     /* 70 */
8250     { Bad_Opcode },
8251     { Bad_Opcode },
8252     { Bad_Opcode },
8253     { Bad_Opcode },
8254     { Bad_Opcode },
8255     { Bad_Opcode },
8256     { Bad_Opcode },
8257     { Bad_Opcode },
8258     /* 78 */
8259     { Bad_Opcode },
8260     { Bad_Opcode },
8261     { Bad_Opcode },
8262     { Bad_Opcode },
8263     { Bad_Opcode },
8264     { Bad_Opcode },
8265     { Bad_Opcode },
8266     { Bad_Opcode },
8267     /* 80 */
8268     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
8269     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
8270     { "vfrczss",        { XM, EXd }, 0 },
8271     { "vfrczsd",        { XM, EXq }, 0 },
8272     { Bad_Opcode },
8273     { Bad_Opcode },
8274     { Bad_Opcode },
8275     { Bad_Opcode },
8276     /* 88 */
8277     { Bad_Opcode },
8278     { Bad_Opcode },
8279     { Bad_Opcode },
8280     { Bad_Opcode },
8281     { Bad_Opcode },
8282     { Bad_Opcode },
8283     { Bad_Opcode },
8284     { Bad_Opcode },
8285     /* 90 */
8286     { "vprotb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8287     { "vprotw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8288     { "vprotd",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8289     { "vprotq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8290     { "vpshlb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8291     { "vpshlw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8292     { "vpshld",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8293     { "vpshlq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8294     /* 98 */
8295     { "vpshab",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8296     { "vpshaw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8297     { "vpshad",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8298     { "vpshaq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8299     { Bad_Opcode },
8300     { Bad_Opcode },
8301     { Bad_Opcode },
8302     { Bad_Opcode },
8303     /* a0 */
8304     { Bad_Opcode },
8305     { Bad_Opcode },
8306     { Bad_Opcode },
8307     { Bad_Opcode },
8308     { Bad_Opcode },
8309     { Bad_Opcode },
8310     { Bad_Opcode },
8311     { Bad_Opcode },
8312     /* a8 */
8313     { Bad_Opcode },
8314     { Bad_Opcode },
8315     { Bad_Opcode },
8316     { Bad_Opcode },
8317     { Bad_Opcode },
8318     { Bad_Opcode },
8319     { Bad_Opcode },
8320     { Bad_Opcode },
8321     /* b0 */
8322     { Bad_Opcode },
8323     { Bad_Opcode },
8324     { Bad_Opcode },
8325     { Bad_Opcode },
8326     { Bad_Opcode },
8327     { Bad_Opcode },
8328     { Bad_Opcode },
8329     { Bad_Opcode },
8330     /* b8 */
8331     { Bad_Opcode },
8332     { Bad_Opcode },
8333     { Bad_Opcode },
8334     { Bad_Opcode },
8335     { Bad_Opcode },
8336     { Bad_Opcode },
8337     { Bad_Opcode },
8338     { Bad_Opcode },
8339     /* c0 */
8340     { Bad_Opcode },
8341     { "vphaddbw",       { XM, EXxmm }, 0 },
8342     { "vphaddbd",       { XM, EXxmm }, 0 },
8343     { "vphaddbq",       { XM, EXxmm }, 0 },
8344     { Bad_Opcode },
8345     { Bad_Opcode },
8346     { "vphaddwd",       { XM, EXxmm }, 0 },
8347     { "vphaddwq",       { XM, EXxmm }, 0 },
8348     /* c8 */
8349     { Bad_Opcode },
8350     { Bad_Opcode },
8351     { Bad_Opcode },
8352     { "vphadddq",       { XM, EXxmm }, 0 },
8353     { Bad_Opcode },
8354     { Bad_Opcode },
8355     { Bad_Opcode },
8356     { Bad_Opcode },
8357     /* d0 */
8358     { Bad_Opcode },
8359     { "vphaddubw",      { XM, EXxmm }, 0 },
8360     { "vphaddubd",      { XM, EXxmm }, 0 },
8361     { "vphaddubq",      { XM, EXxmm }, 0 },
8362     { Bad_Opcode },
8363     { Bad_Opcode },
8364     { "vphadduwd",      { XM, EXxmm }, 0 },
8365     { "vphadduwq",      { XM, EXxmm }, 0 },
8366     /* d8 */
8367     { Bad_Opcode },
8368     { Bad_Opcode },
8369     { Bad_Opcode },
8370     { "vphaddudq",      { XM, EXxmm }, 0 },
8371     { Bad_Opcode },
8372     { Bad_Opcode },
8373     { Bad_Opcode },
8374     { Bad_Opcode },
8375     /* e0 */
8376     { Bad_Opcode },
8377     { "vphsubbw",       { XM, EXxmm }, 0 },
8378     { "vphsubwd",       { XM, EXxmm }, 0 },
8379     { "vphsubdq",       { XM, EXxmm }, 0 },
8380     { Bad_Opcode },
8381     { Bad_Opcode },
8382     { Bad_Opcode },
8383     { Bad_Opcode },
8384     /* e8 */
8385     { Bad_Opcode },
8386     { Bad_Opcode },
8387     { Bad_Opcode },
8388     { Bad_Opcode },
8389     { Bad_Opcode },
8390     { Bad_Opcode },
8391     { Bad_Opcode },
8392     { Bad_Opcode },
8393     /* f0 */
8394     { Bad_Opcode },
8395     { Bad_Opcode },
8396     { Bad_Opcode },
8397     { Bad_Opcode },
8398     { Bad_Opcode },
8399     { Bad_Opcode },
8400     { Bad_Opcode },
8401     { Bad_Opcode },
8402     /* f8 */
8403     { Bad_Opcode },
8404     { Bad_Opcode },
8405     { Bad_Opcode },
8406     { Bad_Opcode },
8407     { Bad_Opcode },
8408     { Bad_Opcode },
8409     { Bad_Opcode },
8410     { Bad_Opcode },
8411   },
8412   /* XOP_0A */
8413   {
8414     /* 00 */
8415     { Bad_Opcode },
8416     { Bad_Opcode },
8417     { Bad_Opcode },
8418     { Bad_Opcode },
8419     { Bad_Opcode },
8420     { Bad_Opcode },
8421     { Bad_Opcode },
8422     { Bad_Opcode },
8423     /* 08 */
8424     { Bad_Opcode },
8425     { Bad_Opcode },
8426     { Bad_Opcode },
8427     { Bad_Opcode },
8428     { Bad_Opcode },
8429     { Bad_Opcode },
8430     { Bad_Opcode },
8431     { Bad_Opcode },
8432     /* 10 */
8433     { "bextr",  { Gv, Ev, Iq }, 0 },
8434     { Bad_Opcode },
8435     { REG_TABLE (REG_XOP_LWP) },
8436     { Bad_Opcode },
8437     { Bad_Opcode },
8438     { Bad_Opcode },
8439     { Bad_Opcode },
8440     { Bad_Opcode },
8441     /* 18 */
8442     { Bad_Opcode },
8443     { Bad_Opcode },
8444     { Bad_Opcode },
8445     { Bad_Opcode },
8446     { Bad_Opcode },
8447     { Bad_Opcode },
8448     { Bad_Opcode },
8449     { Bad_Opcode },
8450     /* 20 */
8451     { Bad_Opcode },
8452     { Bad_Opcode },
8453     { Bad_Opcode },
8454     { Bad_Opcode },
8455     { Bad_Opcode },
8456     { Bad_Opcode },
8457     { Bad_Opcode },
8458     { Bad_Opcode },
8459     /* 28 */
8460     { Bad_Opcode },
8461     { Bad_Opcode },
8462     { Bad_Opcode },
8463     { Bad_Opcode },
8464     { Bad_Opcode },
8465     { Bad_Opcode },
8466     { Bad_Opcode },
8467     { Bad_Opcode },
8468     /* 30 */
8469     { Bad_Opcode },
8470     { Bad_Opcode },
8471     { Bad_Opcode },
8472     { Bad_Opcode },
8473     { Bad_Opcode },
8474     { Bad_Opcode },
8475     { Bad_Opcode },
8476     { Bad_Opcode },
8477     /* 38 */
8478     { Bad_Opcode },
8479     { Bad_Opcode },
8480     { Bad_Opcode },
8481     { Bad_Opcode },
8482     { Bad_Opcode },
8483     { Bad_Opcode },
8484     { Bad_Opcode },
8485     { Bad_Opcode },
8486     /* 40 */
8487     { Bad_Opcode },
8488     { Bad_Opcode },
8489     { Bad_Opcode },
8490     { Bad_Opcode },
8491     { Bad_Opcode },
8492     { Bad_Opcode },
8493     { Bad_Opcode },
8494     { Bad_Opcode },
8495     /* 48 */
8496     { Bad_Opcode },
8497     { Bad_Opcode },
8498     { Bad_Opcode },
8499     { Bad_Opcode },
8500     { Bad_Opcode },
8501     { Bad_Opcode },
8502     { Bad_Opcode },
8503     { Bad_Opcode },
8504     /* 50 */
8505     { Bad_Opcode },
8506     { Bad_Opcode },
8507     { Bad_Opcode },
8508     { Bad_Opcode },
8509     { Bad_Opcode },
8510     { Bad_Opcode },
8511     { Bad_Opcode },
8512     { Bad_Opcode },
8513     /* 58 */
8514     { Bad_Opcode },
8515     { Bad_Opcode },
8516     { Bad_Opcode },
8517     { Bad_Opcode },
8518     { Bad_Opcode },
8519     { Bad_Opcode },
8520     { Bad_Opcode },
8521     { Bad_Opcode },
8522     /* 60 */
8523     { Bad_Opcode },
8524     { Bad_Opcode },
8525     { Bad_Opcode },
8526     { Bad_Opcode },
8527     { Bad_Opcode },
8528     { Bad_Opcode },
8529     { Bad_Opcode },
8530     { Bad_Opcode },
8531     /* 68 */
8532     { Bad_Opcode },
8533     { Bad_Opcode },
8534     { Bad_Opcode },
8535     { Bad_Opcode },
8536     { Bad_Opcode },
8537     { Bad_Opcode },
8538     { Bad_Opcode },
8539     { Bad_Opcode },
8540     /* 70 */
8541     { Bad_Opcode },
8542     { Bad_Opcode },
8543     { Bad_Opcode },
8544     { Bad_Opcode },
8545     { Bad_Opcode },
8546     { Bad_Opcode },
8547     { Bad_Opcode },
8548     { Bad_Opcode },
8549     /* 78 */
8550     { Bad_Opcode },
8551     { Bad_Opcode },
8552     { Bad_Opcode },
8553     { Bad_Opcode },
8554     { Bad_Opcode },
8555     { Bad_Opcode },
8556     { Bad_Opcode },
8557     { Bad_Opcode },
8558     /* 80 */
8559     { Bad_Opcode },
8560     { Bad_Opcode },
8561     { Bad_Opcode },
8562     { Bad_Opcode },
8563     { Bad_Opcode },
8564     { Bad_Opcode },
8565     { Bad_Opcode },
8566     { Bad_Opcode },
8567     /* 88 */
8568     { Bad_Opcode },
8569     { Bad_Opcode },
8570     { Bad_Opcode },
8571     { Bad_Opcode },
8572     { Bad_Opcode },
8573     { Bad_Opcode },
8574     { Bad_Opcode },
8575     { Bad_Opcode },
8576     /* 90 */
8577     { Bad_Opcode },
8578     { Bad_Opcode },
8579     { Bad_Opcode },
8580     { Bad_Opcode },
8581     { Bad_Opcode },
8582     { Bad_Opcode },
8583     { Bad_Opcode },
8584     { Bad_Opcode },
8585     /* 98 */
8586     { Bad_Opcode },
8587     { Bad_Opcode },
8588     { Bad_Opcode },
8589     { Bad_Opcode },
8590     { Bad_Opcode },
8591     { Bad_Opcode },
8592     { Bad_Opcode },
8593     { Bad_Opcode },
8594     /* a0 */
8595     { Bad_Opcode },
8596     { Bad_Opcode },
8597     { Bad_Opcode },
8598     { Bad_Opcode },
8599     { Bad_Opcode },
8600     { Bad_Opcode },
8601     { Bad_Opcode },
8602     { Bad_Opcode },
8603     /* a8 */
8604     { Bad_Opcode },
8605     { Bad_Opcode },
8606     { Bad_Opcode },
8607     { Bad_Opcode },
8608     { Bad_Opcode },
8609     { Bad_Opcode },
8610     { Bad_Opcode },
8611     { Bad_Opcode },
8612     /* b0 */
8613     { Bad_Opcode },
8614     { Bad_Opcode },
8615     { Bad_Opcode },
8616     { Bad_Opcode },
8617     { Bad_Opcode },
8618     { Bad_Opcode },
8619     { Bad_Opcode },
8620     { Bad_Opcode },
8621     /* b8 */
8622     { Bad_Opcode },
8623     { Bad_Opcode },
8624     { Bad_Opcode },
8625     { Bad_Opcode },
8626     { Bad_Opcode },
8627     { Bad_Opcode },
8628     { Bad_Opcode },
8629     { Bad_Opcode },
8630     /* c0 */
8631     { Bad_Opcode },
8632     { Bad_Opcode },
8633     { Bad_Opcode },
8634     { Bad_Opcode },
8635     { Bad_Opcode },
8636     { Bad_Opcode },
8637     { Bad_Opcode },
8638     { Bad_Opcode },
8639     /* c8 */
8640     { Bad_Opcode },
8641     { Bad_Opcode },
8642     { Bad_Opcode },
8643     { Bad_Opcode },
8644     { Bad_Opcode },
8645     { Bad_Opcode },
8646     { Bad_Opcode },
8647     { Bad_Opcode },
8648     /* d0 */
8649     { Bad_Opcode },
8650     { Bad_Opcode },
8651     { Bad_Opcode },
8652     { Bad_Opcode },
8653     { Bad_Opcode },
8654     { Bad_Opcode },
8655     { Bad_Opcode },
8656     { Bad_Opcode },
8657     /* d8 */
8658     { Bad_Opcode },
8659     { Bad_Opcode },
8660     { Bad_Opcode },
8661     { Bad_Opcode },
8662     { Bad_Opcode },
8663     { Bad_Opcode },
8664     { Bad_Opcode },
8665     { Bad_Opcode },
8666     /* e0 */
8667     { Bad_Opcode },
8668     { Bad_Opcode },
8669     { Bad_Opcode },
8670     { Bad_Opcode },
8671     { Bad_Opcode },
8672     { Bad_Opcode },
8673     { Bad_Opcode },
8674     { Bad_Opcode },
8675     /* e8 */
8676     { Bad_Opcode },
8677     { Bad_Opcode },
8678     { Bad_Opcode },
8679     { Bad_Opcode },
8680     { Bad_Opcode },
8681     { Bad_Opcode },
8682     { Bad_Opcode },
8683     { Bad_Opcode },
8684     /* f0 */
8685     { Bad_Opcode },
8686     { Bad_Opcode },
8687     { Bad_Opcode },
8688     { Bad_Opcode },
8689     { Bad_Opcode },
8690     { Bad_Opcode },
8691     { Bad_Opcode },
8692     { Bad_Opcode },
8693     /* f8 */
8694     { Bad_Opcode },
8695     { Bad_Opcode },
8696     { Bad_Opcode },
8697     { Bad_Opcode },
8698     { Bad_Opcode },
8699     { Bad_Opcode },
8700     { Bad_Opcode },
8701     { Bad_Opcode },
8702   },
8703 };
8704
8705 static const struct dis386 vex_table[][256] = {
8706   /* VEX_0F */
8707   {
8708     /* 00 */
8709     { Bad_Opcode },
8710     { Bad_Opcode },
8711     { Bad_Opcode },
8712     { Bad_Opcode },
8713     { Bad_Opcode },
8714     { Bad_Opcode },
8715     { Bad_Opcode },
8716     { Bad_Opcode },
8717     /* 08 */
8718     { Bad_Opcode },
8719     { Bad_Opcode },
8720     { Bad_Opcode },
8721     { Bad_Opcode },
8722     { Bad_Opcode },
8723     { Bad_Opcode },
8724     { Bad_Opcode },
8725     { Bad_Opcode },
8726     /* 10 */
8727     { PREFIX_TABLE (PREFIX_VEX_0F10) },
8728     { PREFIX_TABLE (PREFIX_VEX_0F11) },
8729     { PREFIX_TABLE (PREFIX_VEX_0F12) },
8730     { MOD_TABLE (MOD_VEX_0F13) },
8731     { VEX_W_TABLE (VEX_W_0F14) },
8732     { VEX_W_TABLE (VEX_W_0F15) },
8733     { PREFIX_TABLE (PREFIX_VEX_0F16) },
8734     { MOD_TABLE (MOD_VEX_0F17) },
8735     /* 18 */
8736     { Bad_Opcode },
8737     { Bad_Opcode },
8738     { Bad_Opcode },
8739     { Bad_Opcode },
8740     { Bad_Opcode },
8741     { Bad_Opcode },
8742     { Bad_Opcode },
8743     { Bad_Opcode },
8744     /* 20 */
8745     { Bad_Opcode },
8746     { Bad_Opcode },
8747     { Bad_Opcode },
8748     { Bad_Opcode },
8749     { Bad_Opcode },
8750     { Bad_Opcode },
8751     { Bad_Opcode },
8752     { Bad_Opcode },
8753     /* 28 */
8754     { VEX_W_TABLE (VEX_W_0F28) },
8755     { VEX_W_TABLE (VEX_W_0F29) },
8756     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8757     { MOD_TABLE (MOD_VEX_0F2B) },
8758     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8759     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8760     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8761     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8762     /* 30 */
8763     { Bad_Opcode },
8764     { Bad_Opcode },
8765     { Bad_Opcode },
8766     { Bad_Opcode },
8767     { Bad_Opcode },
8768     { Bad_Opcode },
8769     { Bad_Opcode },
8770     { Bad_Opcode },
8771     /* 38 */
8772     { Bad_Opcode },
8773     { Bad_Opcode },
8774     { Bad_Opcode },
8775     { Bad_Opcode },
8776     { Bad_Opcode },
8777     { Bad_Opcode },
8778     { Bad_Opcode },
8779     { Bad_Opcode },
8780     /* 40 */
8781     { Bad_Opcode },
8782     { PREFIX_TABLE (PREFIX_VEX_0F41) },
8783     { PREFIX_TABLE (PREFIX_VEX_0F42) },
8784     { Bad_Opcode },
8785     { PREFIX_TABLE (PREFIX_VEX_0F44) },
8786     { PREFIX_TABLE (PREFIX_VEX_0F45) },
8787     { PREFIX_TABLE (PREFIX_VEX_0F46) },
8788     { PREFIX_TABLE (PREFIX_VEX_0F47) },
8789     /* 48 */
8790     { Bad_Opcode },
8791     { Bad_Opcode },
8792     { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8793     { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8794     { Bad_Opcode },
8795     { Bad_Opcode },
8796     { Bad_Opcode },
8797     { Bad_Opcode },
8798     /* 50 */
8799     { MOD_TABLE (MOD_VEX_0F50) },
8800     { PREFIX_TABLE (PREFIX_VEX_0F51) },
8801     { PREFIX_TABLE (PREFIX_VEX_0F52) },
8802     { PREFIX_TABLE (PREFIX_VEX_0F53) },
8803     { "vandpX",         { XM, Vex, EXx }, 0 },
8804     { "vandnpX",        { XM, Vex, EXx }, 0 },
8805     { "vorpX",          { XM, Vex, EXx }, 0 },
8806     { "vxorpX",         { XM, Vex, EXx }, 0 },
8807     /* 58 */
8808     { PREFIX_TABLE (PREFIX_VEX_0F58) },
8809     { PREFIX_TABLE (PREFIX_VEX_0F59) },
8810     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8811     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8812     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8813     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8814     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8815     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8816     /* 60 */
8817     { PREFIX_TABLE (PREFIX_VEX_0F60) },
8818     { PREFIX_TABLE (PREFIX_VEX_0F61) },
8819     { PREFIX_TABLE (PREFIX_VEX_0F62) },
8820     { PREFIX_TABLE (PREFIX_VEX_0F63) },
8821     { PREFIX_TABLE (PREFIX_VEX_0F64) },
8822     { PREFIX_TABLE (PREFIX_VEX_0F65) },
8823     { PREFIX_TABLE (PREFIX_VEX_0F66) },
8824     { PREFIX_TABLE (PREFIX_VEX_0F67) },
8825     /* 68 */
8826     { PREFIX_TABLE (PREFIX_VEX_0F68) },
8827     { PREFIX_TABLE (PREFIX_VEX_0F69) },
8828     { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8829     { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8830     { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8831     { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8832     { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8833     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8834     /* 70 */
8835     { PREFIX_TABLE (PREFIX_VEX_0F70) },
8836     { REG_TABLE (REG_VEX_0F71) },
8837     { REG_TABLE (REG_VEX_0F72) },
8838     { REG_TABLE (REG_VEX_0F73) },
8839     { PREFIX_TABLE (PREFIX_VEX_0F74) },
8840     { PREFIX_TABLE (PREFIX_VEX_0F75) },
8841     { PREFIX_TABLE (PREFIX_VEX_0F76) },
8842     { PREFIX_TABLE (PREFIX_VEX_0F77) },
8843     /* 78 */
8844     { Bad_Opcode },
8845     { Bad_Opcode },
8846     { Bad_Opcode },
8847     { Bad_Opcode },
8848     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8849     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8850     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8851     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8852     /* 80 */
8853     { Bad_Opcode },
8854     { Bad_Opcode },
8855     { Bad_Opcode },
8856     { Bad_Opcode },
8857     { Bad_Opcode },
8858     { Bad_Opcode },
8859     { Bad_Opcode },
8860     { Bad_Opcode },
8861     /* 88 */
8862     { Bad_Opcode },
8863     { Bad_Opcode },
8864     { Bad_Opcode },
8865     { Bad_Opcode },
8866     { Bad_Opcode },
8867     { Bad_Opcode },
8868     { Bad_Opcode },
8869     { Bad_Opcode },
8870     /* 90 */
8871     { PREFIX_TABLE (PREFIX_VEX_0F90) },
8872     { PREFIX_TABLE (PREFIX_VEX_0F91) },
8873     { PREFIX_TABLE (PREFIX_VEX_0F92) },
8874     { PREFIX_TABLE (PREFIX_VEX_0F93) },
8875     { Bad_Opcode },
8876     { Bad_Opcode },
8877     { Bad_Opcode },
8878     { Bad_Opcode },
8879     /* 98 */
8880     { PREFIX_TABLE (PREFIX_VEX_0F98) },
8881     { PREFIX_TABLE (PREFIX_VEX_0F99) },
8882     { Bad_Opcode },
8883     { Bad_Opcode },
8884     { Bad_Opcode },
8885     { Bad_Opcode },
8886     { Bad_Opcode },
8887     { Bad_Opcode },
8888     /* a0 */
8889     { Bad_Opcode },
8890     { Bad_Opcode },
8891     { Bad_Opcode },
8892     { Bad_Opcode },
8893     { Bad_Opcode },
8894     { Bad_Opcode },
8895     { Bad_Opcode },
8896     { Bad_Opcode },
8897     /* a8 */
8898     { Bad_Opcode },
8899     { Bad_Opcode },
8900     { Bad_Opcode },
8901     { Bad_Opcode },
8902     { Bad_Opcode },
8903     { Bad_Opcode },
8904     { REG_TABLE (REG_VEX_0FAE) },
8905     { Bad_Opcode },
8906     /* b0 */
8907     { Bad_Opcode },
8908     { Bad_Opcode },
8909     { Bad_Opcode },
8910     { Bad_Opcode },
8911     { Bad_Opcode },
8912     { Bad_Opcode },
8913     { Bad_Opcode },
8914     { Bad_Opcode },
8915     /* b8 */
8916     { Bad_Opcode },
8917     { Bad_Opcode },
8918     { Bad_Opcode },
8919     { Bad_Opcode },
8920     { Bad_Opcode },
8921     { Bad_Opcode },
8922     { Bad_Opcode },
8923     { Bad_Opcode },
8924     /* c0 */
8925     { Bad_Opcode },
8926     { Bad_Opcode },
8927     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8928     { Bad_Opcode },
8929     { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8930     { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8931     { "vshufpX",        { XM, Vex, EXx, Ib }, 0 },
8932     { Bad_Opcode },
8933     /* c8 */
8934     { Bad_Opcode },
8935     { Bad_Opcode },
8936     { Bad_Opcode },
8937     { Bad_Opcode },
8938     { Bad_Opcode },
8939     { Bad_Opcode },
8940     { Bad_Opcode },
8941     { Bad_Opcode },
8942     /* d0 */
8943     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8944     { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8945     { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8946     { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8947     { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8948     { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8949     { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8950     { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8951     /* d8 */
8952     { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8953     { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8954     { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8955     { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8956     { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8957     { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8958     { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8959     { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8960     /* e0 */
8961     { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8962     { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8963     { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8964     { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8965     { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8966     { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8967     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8968     { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8969     /* e8 */
8970     { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8971     { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8972     { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8973     { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8974     { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8975     { PREFIX_TABLE (PREFIX_VEX_0FED) },
8976     { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8977     { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8978     /* f0 */
8979     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8980     { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8981     { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8982     { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8983     { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8984     { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8985     { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8986     { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8987     /* f8 */
8988     { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8989     { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8990     { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8991     { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8992     { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8993     { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8994     { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8995     { Bad_Opcode },
8996   },
8997   /* VEX_0F38 */
8998   {
8999     /* 00 */
9000     { PREFIX_TABLE (PREFIX_VEX_0F3800) },
9001     { PREFIX_TABLE (PREFIX_VEX_0F3801) },
9002     { PREFIX_TABLE (PREFIX_VEX_0F3802) },
9003     { PREFIX_TABLE (PREFIX_VEX_0F3803) },
9004     { PREFIX_TABLE (PREFIX_VEX_0F3804) },
9005     { PREFIX_TABLE (PREFIX_VEX_0F3805) },
9006     { PREFIX_TABLE (PREFIX_VEX_0F3806) },
9007     { PREFIX_TABLE (PREFIX_VEX_0F3807) },
9008     /* 08 */
9009     { PREFIX_TABLE (PREFIX_VEX_0F3808) },
9010     { PREFIX_TABLE (PREFIX_VEX_0F3809) },
9011     { PREFIX_TABLE (PREFIX_VEX_0F380A) },
9012     { PREFIX_TABLE (PREFIX_VEX_0F380B) },
9013     { PREFIX_TABLE (PREFIX_VEX_0F380C) },
9014     { PREFIX_TABLE (PREFIX_VEX_0F380D) },
9015     { PREFIX_TABLE (PREFIX_VEX_0F380E) },
9016     { PREFIX_TABLE (PREFIX_VEX_0F380F) },
9017     /* 10 */
9018     { Bad_Opcode },
9019     { Bad_Opcode },
9020     { Bad_Opcode },
9021     { PREFIX_TABLE (PREFIX_VEX_0F3813) },
9022     { Bad_Opcode },
9023     { Bad_Opcode },
9024     { PREFIX_TABLE (PREFIX_VEX_0F3816) },
9025     { PREFIX_TABLE (PREFIX_VEX_0F3817) },
9026     /* 18 */
9027     { PREFIX_TABLE (PREFIX_VEX_0F3818) },
9028     { PREFIX_TABLE (PREFIX_VEX_0F3819) },
9029     { PREFIX_TABLE (PREFIX_VEX_0F381A) },
9030     { Bad_Opcode },
9031     { PREFIX_TABLE (PREFIX_VEX_0F381C) },
9032     { PREFIX_TABLE (PREFIX_VEX_0F381D) },
9033     { PREFIX_TABLE (PREFIX_VEX_0F381E) },
9034     { Bad_Opcode },
9035     /* 20 */
9036     { PREFIX_TABLE (PREFIX_VEX_0F3820) },
9037     { PREFIX_TABLE (PREFIX_VEX_0F3821) },
9038     { PREFIX_TABLE (PREFIX_VEX_0F3822) },
9039     { PREFIX_TABLE (PREFIX_VEX_0F3823) },
9040     { PREFIX_TABLE (PREFIX_VEX_0F3824) },
9041     { PREFIX_TABLE (PREFIX_VEX_0F3825) },
9042     { Bad_Opcode },
9043     { Bad_Opcode },
9044     /* 28 */
9045     { PREFIX_TABLE (PREFIX_VEX_0F3828) },
9046     { PREFIX_TABLE (PREFIX_VEX_0F3829) },
9047     { PREFIX_TABLE (PREFIX_VEX_0F382A) },
9048     { PREFIX_TABLE (PREFIX_VEX_0F382B) },
9049     { PREFIX_TABLE (PREFIX_VEX_0F382C) },
9050     { PREFIX_TABLE (PREFIX_VEX_0F382D) },
9051     { PREFIX_TABLE (PREFIX_VEX_0F382E) },
9052     { PREFIX_TABLE (PREFIX_VEX_0F382F) },
9053     /* 30 */
9054     { PREFIX_TABLE (PREFIX_VEX_0F3830) },
9055     { PREFIX_TABLE (PREFIX_VEX_0F3831) },
9056     { PREFIX_TABLE (PREFIX_VEX_0F3832) },
9057     { PREFIX_TABLE (PREFIX_VEX_0F3833) },
9058     { PREFIX_TABLE (PREFIX_VEX_0F3834) },
9059     { PREFIX_TABLE (PREFIX_VEX_0F3835) },
9060     { PREFIX_TABLE (PREFIX_VEX_0F3836) },
9061     { PREFIX_TABLE (PREFIX_VEX_0F3837) },
9062     /* 38 */
9063     { PREFIX_TABLE (PREFIX_VEX_0F3838) },
9064     { PREFIX_TABLE (PREFIX_VEX_0F3839) },
9065     { PREFIX_TABLE (PREFIX_VEX_0F383A) },
9066     { PREFIX_TABLE (PREFIX_VEX_0F383B) },
9067     { PREFIX_TABLE (PREFIX_VEX_0F383C) },
9068     { PREFIX_TABLE (PREFIX_VEX_0F383D) },
9069     { PREFIX_TABLE (PREFIX_VEX_0F383E) },
9070     { PREFIX_TABLE (PREFIX_VEX_0F383F) },
9071     /* 40 */
9072     { PREFIX_TABLE (PREFIX_VEX_0F3840) },
9073     { PREFIX_TABLE (PREFIX_VEX_0F3841) },
9074     { Bad_Opcode },
9075     { Bad_Opcode },
9076     { Bad_Opcode },
9077     { PREFIX_TABLE (PREFIX_VEX_0F3845) },
9078     { PREFIX_TABLE (PREFIX_VEX_0F3846) },
9079     { PREFIX_TABLE (PREFIX_VEX_0F3847) },
9080     /* 48 */
9081     { Bad_Opcode },
9082     { Bad_Opcode },
9083     { Bad_Opcode },
9084     { Bad_Opcode },
9085     { Bad_Opcode },
9086     { Bad_Opcode },
9087     { Bad_Opcode },
9088     { Bad_Opcode },
9089     /* 50 */
9090     { Bad_Opcode },
9091     { Bad_Opcode },
9092     { Bad_Opcode },
9093     { Bad_Opcode },
9094     { Bad_Opcode },
9095     { Bad_Opcode },
9096     { Bad_Opcode },
9097     { Bad_Opcode },
9098     /* 58 */
9099     { PREFIX_TABLE (PREFIX_VEX_0F3858) },
9100     { PREFIX_TABLE (PREFIX_VEX_0F3859) },
9101     { PREFIX_TABLE (PREFIX_VEX_0F385A) },
9102     { Bad_Opcode },
9103     { Bad_Opcode },
9104     { Bad_Opcode },
9105     { Bad_Opcode },
9106     { Bad_Opcode },
9107     /* 60 */
9108     { Bad_Opcode },
9109     { Bad_Opcode },
9110     { Bad_Opcode },
9111     { Bad_Opcode },
9112     { Bad_Opcode },
9113     { Bad_Opcode },
9114     { Bad_Opcode },
9115     { Bad_Opcode },
9116     /* 68 */
9117     { Bad_Opcode },
9118     { Bad_Opcode },
9119     { Bad_Opcode },
9120     { Bad_Opcode },
9121     { Bad_Opcode },
9122     { Bad_Opcode },
9123     { Bad_Opcode },
9124     { Bad_Opcode },
9125     /* 70 */
9126     { Bad_Opcode },
9127     { Bad_Opcode },
9128     { Bad_Opcode },
9129     { Bad_Opcode },
9130     { Bad_Opcode },
9131     { Bad_Opcode },
9132     { Bad_Opcode },
9133     { Bad_Opcode },
9134     /* 78 */
9135     { PREFIX_TABLE (PREFIX_VEX_0F3878) },
9136     { PREFIX_TABLE (PREFIX_VEX_0F3879) },
9137     { Bad_Opcode },
9138     { Bad_Opcode },
9139     { Bad_Opcode },
9140     { Bad_Opcode },
9141     { Bad_Opcode },
9142     { Bad_Opcode },
9143     /* 80 */
9144     { Bad_Opcode },
9145     { Bad_Opcode },
9146     { Bad_Opcode },
9147     { Bad_Opcode },
9148     { Bad_Opcode },
9149     { Bad_Opcode },
9150     { Bad_Opcode },
9151     { Bad_Opcode },
9152     /* 88 */
9153     { Bad_Opcode },
9154     { Bad_Opcode },
9155     { Bad_Opcode },
9156     { Bad_Opcode },
9157     { PREFIX_TABLE (PREFIX_VEX_0F388C) },
9158     { Bad_Opcode },
9159     { PREFIX_TABLE (PREFIX_VEX_0F388E) },
9160     { Bad_Opcode },
9161     /* 90 */
9162     { PREFIX_TABLE (PREFIX_VEX_0F3890) },
9163     { PREFIX_TABLE (PREFIX_VEX_0F3891) },
9164     { PREFIX_TABLE (PREFIX_VEX_0F3892) },
9165     { PREFIX_TABLE (PREFIX_VEX_0F3893) },
9166     { Bad_Opcode },
9167     { Bad_Opcode },
9168     { PREFIX_TABLE (PREFIX_VEX_0F3896) },
9169     { PREFIX_TABLE (PREFIX_VEX_0F3897) },
9170     /* 98 */
9171     { PREFIX_TABLE (PREFIX_VEX_0F3898) },
9172     { PREFIX_TABLE (PREFIX_VEX_0F3899) },
9173     { PREFIX_TABLE (PREFIX_VEX_0F389A) },
9174     { PREFIX_TABLE (PREFIX_VEX_0F389B) },
9175     { PREFIX_TABLE (PREFIX_VEX_0F389C) },
9176     { PREFIX_TABLE (PREFIX_VEX_0F389D) },
9177     { PREFIX_TABLE (PREFIX_VEX_0F389E) },
9178     { PREFIX_TABLE (PREFIX_VEX_0F389F) },
9179     /* a0 */
9180     { Bad_Opcode },
9181     { Bad_Opcode },
9182     { Bad_Opcode },
9183     { Bad_Opcode },
9184     { Bad_Opcode },
9185     { Bad_Opcode },
9186     { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
9187     { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
9188     /* a8 */
9189     { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
9190     { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
9191     { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
9192     { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
9193     { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
9194     { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
9195     { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
9196     { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
9197     /* b0 */
9198     { Bad_Opcode },
9199     { Bad_Opcode },
9200     { Bad_Opcode },
9201     { Bad_Opcode },
9202     { Bad_Opcode },
9203     { Bad_Opcode },
9204     { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
9205     { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
9206     /* b8 */
9207     { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
9208     { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
9209     { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
9210     { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
9211     { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
9212     { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
9213     { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
9214     { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
9215     /* c0 */
9216     { Bad_Opcode },
9217     { Bad_Opcode },
9218     { Bad_Opcode },
9219     { Bad_Opcode },
9220     { Bad_Opcode },
9221     { Bad_Opcode },
9222     { Bad_Opcode },
9223     { Bad_Opcode },
9224     /* c8 */
9225     { Bad_Opcode },
9226     { Bad_Opcode },
9227     { Bad_Opcode },
9228     { Bad_Opcode },
9229     { Bad_Opcode },
9230     { Bad_Opcode },
9231     { Bad_Opcode },
9232     { Bad_Opcode },
9233     /* d0 */
9234     { Bad_Opcode },
9235     { Bad_Opcode },
9236     { Bad_Opcode },
9237     { Bad_Opcode },
9238     { Bad_Opcode },
9239     { Bad_Opcode },
9240     { Bad_Opcode },
9241     { Bad_Opcode },
9242     /* d8 */
9243     { Bad_Opcode },
9244     { Bad_Opcode },
9245     { Bad_Opcode },
9246     { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
9247     { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
9248     { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
9249     { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
9250     { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
9251     /* e0 */
9252     { Bad_Opcode },
9253     { Bad_Opcode },
9254     { Bad_Opcode },
9255     { Bad_Opcode },
9256     { Bad_Opcode },
9257     { Bad_Opcode },
9258     { Bad_Opcode },
9259     { Bad_Opcode },
9260     /* e8 */
9261     { Bad_Opcode },
9262     { Bad_Opcode },
9263     { Bad_Opcode },
9264     { Bad_Opcode },
9265     { Bad_Opcode },
9266     { Bad_Opcode },
9267     { Bad_Opcode },
9268     { Bad_Opcode },
9269     /* f0 */
9270     { Bad_Opcode },
9271     { Bad_Opcode },
9272     { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
9273     { REG_TABLE (REG_VEX_0F38F3) },
9274     { Bad_Opcode },
9275     { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
9276     { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
9277     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
9278     /* f8 */
9279     { Bad_Opcode },
9280     { Bad_Opcode },
9281     { Bad_Opcode },
9282     { Bad_Opcode },
9283     { Bad_Opcode },
9284     { Bad_Opcode },
9285     { Bad_Opcode },
9286     { Bad_Opcode },
9287   },
9288   /* VEX_0F3A */
9289   {
9290     /* 00 */
9291     { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
9292     { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
9293     { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
9294     { Bad_Opcode },
9295     { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
9296     { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
9297     { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
9298     { Bad_Opcode },
9299     /* 08 */
9300     { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
9301     { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
9302     { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
9303     { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
9304     { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
9305     { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
9306     { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
9307     { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
9308     /* 10 */
9309     { Bad_Opcode },
9310     { Bad_Opcode },
9311     { Bad_Opcode },
9312     { Bad_Opcode },
9313     { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
9314     { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
9315     { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
9316     { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
9317     /* 18 */
9318     { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
9319     { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
9320     { Bad_Opcode },
9321     { Bad_Opcode },
9322     { Bad_Opcode },
9323     { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
9324     { Bad_Opcode },
9325     { Bad_Opcode },
9326     /* 20 */
9327     { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
9328     { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
9329     { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
9330     { Bad_Opcode },
9331     { Bad_Opcode },
9332     { Bad_Opcode },
9333     { Bad_Opcode },
9334     { Bad_Opcode },
9335     /* 28 */
9336     { Bad_Opcode },
9337     { Bad_Opcode },
9338     { Bad_Opcode },
9339     { Bad_Opcode },
9340     { Bad_Opcode },
9341     { Bad_Opcode },
9342     { Bad_Opcode },
9343     { Bad_Opcode },
9344     /* 30 */
9345     { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
9346     { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
9347     { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
9348     { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
9349     { Bad_Opcode },
9350     { Bad_Opcode },
9351     { Bad_Opcode },
9352     { Bad_Opcode },
9353     /* 38 */
9354     { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
9355     { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
9356     { Bad_Opcode },
9357     { Bad_Opcode },
9358     { Bad_Opcode },
9359     { Bad_Opcode },
9360     { Bad_Opcode },
9361     { Bad_Opcode },
9362     /* 40 */
9363     { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
9364     { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
9365     { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
9366     { Bad_Opcode },
9367     { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
9368     { Bad_Opcode },
9369     { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
9370     { Bad_Opcode },
9371     /* 48 */
9372     { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
9373     { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
9374     { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
9375     { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
9376     { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
9377     { Bad_Opcode },
9378     { Bad_Opcode },
9379     { Bad_Opcode },
9380     /* 50 */
9381     { Bad_Opcode },
9382     { Bad_Opcode },
9383     { Bad_Opcode },
9384     { Bad_Opcode },
9385     { Bad_Opcode },
9386     { Bad_Opcode },
9387     { Bad_Opcode },
9388     { Bad_Opcode },
9389     /* 58 */
9390     { Bad_Opcode },
9391     { Bad_Opcode },
9392     { Bad_Opcode },
9393     { Bad_Opcode },
9394     { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9395     { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9396     { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9397     { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9398     /* 60 */
9399     { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9400     { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9401     { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9402     { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9403     { Bad_Opcode },
9404     { Bad_Opcode },
9405     { Bad_Opcode },
9406     { Bad_Opcode },
9407     /* 68 */
9408     { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9409     { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9410     { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9411     { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9412     { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9413     { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9414     { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9415     { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9416     /* 70 */
9417     { Bad_Opcode },
9418     { Bad_Opcode },
9419     { Bad_Opcode },
9420     { Bad_Opcode },
9421     { Bad_Opcode },
9422     { Bad_Opcode },
9423     { Bad_Opcode },
9424     { Bad_Opcode },
9425     /* 78 */
9426     { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9427     { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9428     { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9429     { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9430     { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9431     { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9432     { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9433     { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9434     /* 80 */
9435     { Bad_Opcode },
9436     { Bad_Opcode },
9437     { Bad_Opcode },
9438     { Bad_Opcode },
9439     { Bad_Opcode },
9440     { Bad_Opcode },
9441     { Bad_Opcode },
9442     { Bad_Opcode },
9443     /* 88 */
9444     { Bad_Opcode },
9445     { Bad_Opcode },
9446     { Bad_Opcode },
9447     { Bad_Opcode },
9448     { Bad_Opcode },
9449     { Bad_Opcode },
9450     { Bad_Opcode },
9451     { Bad_Opcode },
9452     /* 90 */
9453     { Bad_Opcode },
9454     { Bad_Opcode },
9455     { Bad_Opcode },
9456     { Bad_Opcode },
9457     { Bad_Opcode },
9458     { Bad_Opcode },
9459     { Bad_Opcode },
9460     { Bad_Opcode },
9461     /* 98 */
9462     { Bad_Opcode },
9463     { Bad_Opcode },
9464     { Bad_Opcode },
9465     { Bad_Opcode },
9466     { Bad_Opcode },
9467     { Bad_Opcode },
9468     { Bad_Opcode },
9469     { Bad_Opcode },
9470     /* a0 */
9471     { Bad_Opcode },
9472     { Bad_Opcode },
9473     { Bad_Opcode },
9474     { Bad_Opcode },
9475     { Bad_Opcode },
9476     { Bad_Opcode },
9477     { Bad_Opcode },
9478     { Bad_Opcode },
9479     /* a8 */
9480     { Bad_Opcode },
9481     { Bad_Opcode },
9482     { Bad_Opcode },
9483     { Bad_Opcode },
9484     { Bad_Opcode },
9485     { Bad_Opcode },
9486     { Bad_Opcode },
9487     { Bad_Opcode },
9488     /* b0 */
9489     { Bad_Opcode },
9490     { Bad_Opcode },
9491     { Bad_Opcode },
9492     { Bad_Opcode },
9493     { Bad_Opcode },
9494     { Bad_Opcode },
9495     { Bad_Opcode },
9496     { Bad_Opcode },
9497     /* b8 */
9498     { Bad_Opcode },
9499     { Bad_Opcode },
9500     { Bad_Opcode },
9501     { Bad_Opcode },
9502     { Bad_Opcode },
9503     { Bad_Opcode },
9504     { Bad_Opcode },
9505     { Bad_Opcode },
9506     /* c0 */
9507     { Bad_Opcode },
9508     { Bad_Opcode },
9509     { Bad_Opcode },
9510     { Bad_Opcode },
9511     { Bad_Opcode },
9512     { Bad_Opcode },
9513     { Bad_Opcode },
9514     { Bad_Opcode },
9515     /* c8 */
9516     { Bad_Opcode },
9517     { Bad_Opcode },
9518     { Bad_Opcode },
9519     { Bad_Opcode },
9520     { Bad_Opcode },
9521     { Bad_Opcode },
9522     { Bad_Opcode },
9523     { Bad_Opcode },
9524     /* d0 */
9525     { Bad_Opcode },
9526     { Bad_Opcode },
9527     { Bad_Opcode },
9528     { Bad_Opcode },
9529     { Bad_Opcode },
9530     { Bad_Opcode },
9531     { Bad_Opcode },
9532     { Bad_Opcode },
9533     /* d8 */
9534     { Bad_Opcode },
9535     { Bad_Opcode },
9536     { Bad_Opcode },
9537     { Bad_Opcode },
9538     { Bad_Opcode },
9539     { Bad_Opcode },
9540     { Bad_Opcode },
9541     { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9542     /* e0 */
9543     { Bad_Opcode },
9544     { Bad_Opcode },
9545     { Bad_Opcode },
9546     { Bad_Opcode },
9547     { Bad_Opcode },
9548     { Bad_Opcode },
9549     { Bad_Opcode },
9550     { Bad_Opcode },
9551     /* e8 */
9552     { Bad_Opcode },
9553     { Bad_Opcode },
9554     { Bad_Opcode },
9555     { Bad_Opcode },
9556     { Bad_Opcode },
9557     { Bad_Opcode },
9558     { Bad_Opcode },
9559     { Bad_Opcode },
9560     /* f0 */
9561     { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9562     { Bad_Opcode },
9563     { Bad_Opcode },
9564     { Bad_Opcode },
9565     { Bad_Opcode },
9566     { Bad_Opcode },
9567     { Bad_Opcode },
9568     { Bad_Opcode },
9569     /* f8 */
9570     { Bad_Opcode },
9571     { Bad_Opcode },
9572     { Bad_Opcode },
9573     { Bad_Opcode },
9574     { Bad_Opcode },
9575     { Bad_Opcode },
9576     { Bad_Opcode },
9577     { Bad_Opcode },
9578   },
9579 };
9580
9581 #define NEED_OPCODE_TABLE
9582 #include "i386-dis-evex.h"
9583 #undef NEED_OPCODE_TABLE
9584 static const struct dis386 vex_len_table[][2] = {
9585   /* VEX_LEN_0F10_P_1 */
9586   {
9587     { VEX_W_TABLE (VEX_W_0F10_P_1) },
9588     { VEX_W_TABLE (VEX_W_0F10_P_1) },
9589   },
9590
9591   /* VEX_LEN_0F10_P_3 */
9592   {
9593     { VEX_W_TABLE (VEX_W_0F10_P_3) },
9594     { VEX_W_TABLE (VEX_W_0F10_P_3) },
9595   },
9596
9597   /* VEX_LEN_0F11_P_1 */
9598   {
9599     { VEX_W_TABLE (VEX_W_0F11_P_1) },
9600     { VEX_W_TABLE (VEX_W_0F11_P_1) },
9601   },
9602
9603   /* VEX_LEN_0F11_P_3 */
9604   {
9605     { VEX_W_TABLE (VEX_W_0F11_P_3) },
9606     { VEX_W_TABLE (VEX_W_0F11_P_3) },
9607   },
9608
9609   /* VEX_LEN_0F12_P_0_M_0 */
9610   {
9611     { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) },
9612   },
9613
9614   /* VEX_LEN_0F12_P_0_M_1 */
9615   {
9616     { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) },
9617   },
9618
9619   /* VEX_LEN_0F12_P_2 */
9620   {
9621     { VEX_W_TABLE (VEX_W_0F12_P_2) },
9622   },
9623
9624   /* VEX_LEN_0F13_M_0 */
9625   {
9626     { VEX_W_TABLE (VEX_W_0F13_M_0) },
9627   },
9628
9629   /* VEX_LEN_0F16_P_0_M_0 */
9630   {
9631     { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) },
9632   },
9633
9634   /* VEX_LEN_0F16_P_0_M_1 */
9635   {
9636     { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) },
9637   },
9638
9639   /* VEX_LEN_0F16_P_2 */
9640   {
9641     { VEX_W_TABLE (VEX_W_0F16_P_2) },
9642   },
9643
9644   /* VEX_LEN_0F17_M_0 */
9645   {
9646     { VEX_W_TABLE (VEX_W_0F17_M_0) },
9647   },
9648
9649   /* VEX_LEN_0F2A_P_1 */
9650   {
9651     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9652     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9653   },
9654
9655   /* VEX_LEN_0F2A_P_3 */
9656   {
9657     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9658     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9659   },
9660
9661   /* VEX_LEN_0F2C_P_1 */
9662   {
9663     { "vcvttss2siY",    { Gv, EXdScalar }, 0 },
9664     { "vcvttss2siY",    { Gv, EXdScalar }, 0 },
9665   },
9666
9667   /* VEX_LEN_0F2C_P_3 */
9668   {
9669     { "vcvttsd2siY",    { Gv, EXqScalar }, 0 },
9670     { "vcvttsd2siY",    { Gv, EXqScalar }, 0 },
9671   },
9672
9673   /* VEX_LEN_0F2D_P_1 */
9674   {
9675     { "vcvtss2siY",     { Gv, EXdScalar }, 0 },
9676     { "vcvtss2siY",     { Gv, EXdScalar }, 0 },
9677   },
9678
9679   /* VEX_LEN_0F2D_P_3 */
9680   {
9681     { "vcvtsd2siY",     { Gv, EXqScalar }, 0 },
9682     { "vcvtsd2siY",     { Gv, EXqScalar }, 0 },
9683   },
9684
9685   /* VEX_LEN_0F2E_P_0 */
9686   {
9687     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9688     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9689   },
9690
9691   /* VEX_LEN_0F2E_P_2 */
9692   {
9693     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9694     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9695   },
9696
9697   /* VEX_LEN_0F2F_P_0 */
9698   {
9699     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9700     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9701   },
9702
9703   /* VEX_LEN_0F2F_P_2 */
9704   {
9705     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9706     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9707   },
9708
9709   /* VEX_LEN_0F41_P_0 */
9710   {
9711     { Bad_Opcode },
9712     { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9713   },
9714   /* VEX_LEN_0F41_P_2 */
9715   {
9716     { Bad_Opcode },
9717     { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9718   },
9719   /* VEX_LEN_0F42_P_0 */
9720   {
9721     { Bad_Opcode },
9722     { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9723   },
9724   /* VEX_LEN_0F42_P_2 */
9725   {
9726     { Bad_Opcode },
9727     { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9728   },
9729   /* VEX_LEN_0F44_P_0 */
9730   {
9731     { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9732   },
9733   /* VEX_LEN_0F44_P_2 */
9734   {
9735     { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9736   },
9737   /* VEX_LEN_0F45_P_0 */
9738   {
9739     { Bad_Opcode },
9740     { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9741   },
9742   /* VEX_LEN_0F45_P_2 */
9743   {
9744     { Bad_Opcode },
9745     { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9746   },
9747   /* VEX_LEN_0F46_P_0 */
9748   {
9749     { Bad_Opcode },
9750     { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9751   },
9752   /* VEX_LEN_0F46_P_2 */
9753   {
9754     { Bad_Opcode },
9755     { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9756   },
9757   /* VEX_LEN_0F47_P_0 */
9758   {
9759     { Bad_Opcode },
9760     { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9761   },
9762   /* VEX_LEN_0F47_P_2 */
9763   {
9764     { Bad_Opcode },
9765     { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9766   },
9767   /* VEX_LEN_0F4A_P_0 */
9768   {
9769     { Bad_Opcode },
9770     { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9771   },
9772   /* VEX_LEN_0F4A_P_2 */
9773   {
9774     { Bad_Opcode },
9775     { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9776   },
9777   /* VEX_LEN_0F4B_P_0 */
9778   {
9779     { Bad_Opcode },
9780     { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9781   },
9782   /* VEX_LEN_0F4B_P_2 */
9783   {
9784     { Bad_Opcode },
9785     { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9786   },
9787
9788   /* VEX_LEN_0F51_P_1 */
9789   {
9790     { VEX_W_TABLE (VEX_W_0F51_P_1) },
9791     { VEX_W_TABLE (VEX_W_0F51_P_1) },
9792   },
9793
9794   /* VEX_LEN_0F51_P_3 */
9795   {
9796     { VEX_W_TABLE (VEX_W_0F51_P_3) },
9797     { VEX_W_TABLE (VEX_W_0F51_P_3) },
9798   },
9799
9800   /* VEX_LEN_0F52_P_1 */
9801   {
9802     { VEX_W_TABLE (VEX_W_0F52_P_1) },
9803     { VEX_W_TABLE (VEX_W_0F52_P_1) },
9804   },
9805
9806   /* VEX_LEN_0F53_P_1 */
9807   {
9808     { VEX_W_TABLE (VEX_W_0F53_P_1) },
9809     { VEX_W_TABLE (VEX_W_0F53_P_1) },
9810   },
9811
9812   /* VEX_LEN_0F58_P_1 */
9813   {
9814     { VEX_W_TABLE (VEX_W_0F58_P_1) },
9815     { VEX_W_TABLE (VEX_W_0F58_P_1) },
9816   },
9817
9818   /* VEX_LEN_0F58_P_3 */
9819   {
9820     { VEX_W_TABLE (VEX_W_0F58_P_3) },
9821     { VEX_W_TABLE (VEX_W_0F58_P_3) },
9822   },
9823
9824   /* VEX_LEN_0F59_P_1 */
9825   {
9826     { VEX_W_TABLE (VEX_W_0F59_P_1) },
9827     { VEX_W_TABLE (VEX_W_0F59_P_1) },
9828   },
9829
9830   /* VEX_LEN_0F59_P_3 */
9831   {
9832     { VEX_W_TABLE (VEX_W_0F59_P_3) },
9833     { VEX_W_TABLE (VEX_W_0F59_P_3) },
9834   },
9835
9836   /* VEX_LEN_0F5A_P_1 */
9837   {
9838     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9839     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9840   },
9841
9842   /* VEX_LEN_0F5A_P_3 */
9843   {
9844     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9845     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9846   },
9847
9848   /* VEX_LEN_0F5C_P_1 */
9849   {
9850     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9851     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9852   },
9853
9854   /* VEX_LEN_0F5C_P_3 */
9855   {
9856     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9857     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9858   },
9859
9860   /* VEX_LEN_0F5D_P_1 */
9861   {
9862     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9863     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9864   },
9865
9866   /* VEX_LEN_0F5D_P_3 */
9867   {
9868     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9869     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9870   },
9871
9872   /* VEX_LEN_0F5E_P_1 */
9873   {
9874     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9875     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9876   },
9877
9878   /* VEX_LEN_0F5E_P_3 */
9879   {
9880     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9881     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9882   },
9883
9884   /* VEX_LEN_0F5F_P_1 */
9885   {
9886     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9887     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9888   },
9889
9890   /* VEX_LEN_0F5F_P_3 */
9891   {
9892     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9893     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9894   },
9895
9896   /* VEX_LEN_0F6E_P_2 */
9897   {
9898     { "vmovK",          { XMScalar, Edq }, 0 },
9899     { "vmovK",          { XMScalar, Edq }, 0 },
9900   },
9901
9902   /* VEX_LEN_0F7E_P_1 */
9903   {
9904     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9905     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9906   },
9907
9908   /* VEX_LEN_0F7E_P_2 */
9909   {
9910     { "vmovK",          { Edq, XMScalar }, 0 },
9911     { "vmovK",          { Edq, XMScalar }, 0 },
9912   },
9913
9914   /* VEX_LEN_0F90_P_0 */
9915   {
9916     { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9917   },
9918
9919   /* VEX_LEN_0F90_P_2 */
9920   {
9921     { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9922   },
9923
9924   /* VEX_LEN_0F91_P_0 */
9925   {
9926     { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9927   },
9928
9929   /* VEX_LEN_0F91_P_2 */
9930   {
9931     { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
9932   },
9933
9934   /* VEX_LEN_0F92_P_0 */
9935   {
9936     { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9937   },
9938
9939   /* VEX_LEN_0F92_P_2 */
9940   {
9941     { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
9942   },
9943
9944   /* VEX_LEN_0F92_P_3 */
9945   {
9946     { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0) },
9947   },
9948
9949   /* VEX_LEN_0F93_P_0 */
9950   {
9951     { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9952   },
9953
9954   /* VEX_LEN_0F93_P_2 */
9955   {
9956     { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
9957   },
9958
9959   /* VEX_LEN_0F93_P_3 */
9960   {
9961     { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0) },
9962   },
9963
9964   /* VEX_LEN_0F98_P_0 */
9965   {
9966     { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9967   },
9968
9969   /* VEX_LEN_0F98_P_2 */
9970   {
9971     { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
9972   },
9973
9974   /* VEX_LEN_0F99_P_0 */
9975   {
9976     { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
9977   },
9978
9979   /* VEX_LEN_0F99_P_2 */
9980   {
9981     { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
9982   },
9983
9984   /* VEX_LEN_0FAE_R_2_M_0 */
9985   {
9986     { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) },
9987   },
9988
9989   /* VEX_LEN_0FAE_R_3_M_0 */
9990   {
9991     { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) },
9992   },
9993
9994   /* VEX_LEN_0FC2_P_1 */
9995   {
9996     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9997     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9998   },
9999
10000   /* VEX_LEN_0FC2_P_3 */
10001   {
10002     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
10003     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
10004   },
10005
10006   /* VEX_LEN_0FC4_P_2 */
10007   {
10008     { VEX_W_TABLE (VEX_W_0FC4_P_2) },
10009   },
10010
10011   /* VEX_LEN_0FC5_P_2 */
10012   {
10013     { VEX_W_TABLE (VEX_W_0FC5_P_2) },
10014   },
10015
10016   /* VEX_LEN_0FD6_P_2 */
10017   {
10018     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
10019     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
10020   },
10021
10022   /* VEX_LEN_0FF7_P_2 */
10023   {
10024     { VEX_W_TABLE (VEX_W_0FF7_P_2) },
10025   },
10026
10027   /* VEX_LEN_0F3816_P_2 */
10028   {
10029     { Bad_Opcode },
10030     { VEX_W_TABLE (VEX_W_0F3816_P_2) },
10031   },
10032
10033   /* VEX_LEN_0F3819_P_2 */
10034   {
10035     { Bad_Opcode },
10036     { VEX_W_TABLE (VEX_W_0F3819_P_2) },
10037   },
10038
10039   /* VEX_LEN_0F381A_P_2_M_0 */
10040   {
10041     { Bad_Opcode },
10042     { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
10043   },
10044
10045   /* VEX_LEN_0F3836_P_2 */
10046   {
10047     { Bad_Opcode },
10048     { VEX_W_TABLE (VEX_W_0F3836_P_2) },
10049   },
10050
10051   /* VEX_LEN_0F3841_P_2 */
10052   {
10053     { VEX_W_TABLE (VEX_W_0F3841_P_2) },
10054   },
10055
10056   /* VEX_LEN_0F385A_P_2_M_0 */
10057   {
10058     { Bad_Opcode },
10059     { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
10060   },
10061
10062   /* VEX_LEN_0F38DB_P_2 */
10063   {
10064     { VEX_W_TABLE (VEX_W_0F38DB_P_2) },
10065   },
10066
10067   /* VEX_LEN_0F38DC_P_2 */
10068   {
10069     { VEX_W_TABLE (VEX_W_0F38DC_P_2) },
10070   },
10071
10072   /* VEX_LEN_0F38DD_P_2 */
10073   {
10074     { VEX_W_TABLE (VEX_W_0F38DD_P_2) },
10075   },
10076
10077   /* VEX_LEN_0F38DE_P_2 */
10078   {
10079     { VEX_W_TABLE (VEX_W_0F38DE_P_2) },
10080   },
10081
10082   /* VEX_LEN_0F38DF_P_2 */
10083   {
10084     { VEX_W_TABLE (VEX_W_0F38DF_P_2) },
10085   },
10086
10087   /* VEX_LEN_0F38F2_P_0 */
10088   {
10089     { "andnS",          { Gdq, VexGdq, Edq }, 0 },
10090   },
10091
10092   /* VEX_LEN_0F38F3_R_1_P_0 */
10093   {
10094     { "blsrS",          { VexGdq, Edq }, 0 },
10095   },
10096
10097   /* VEX_LEN_0F38F3_R_2_P_0 */
10098   {
10099     { "blsmskS",        { VexGdq, Edq }, 0 },
10100   },
10101
10102   /* VEX_LEN_0F38F3_R_3_P_0 */
10103   {
10104     { "blsiS",          { VexGdq, Edq }, 0 },
10105   },
10106
10107   /* VEX_LEN_0F38F5_P_0 */
10108   {
10109     { "bzhiS",          { Gdq, Edq, VexGdq }, 0 },
10110   },
10111
10112   /* VEX_LEN_0F38F5_P_1 */
10113   {
10114     { "pextS",          { Gdq, VexGdq, Edq }, 0 },
10115   },
10116
10117   /* VEX_LEN_0F38F5_P_3 */
10118   {
10119     { "pdepS",          { Gdq, VexGdq, Edq }, 0 },
10120   },
10121
10122   /* VEX_LEN_0F38F6_P_3 */
10123   {
10124     { "mulxS",          { Gdq, VexGdq, Edq }, 0 },
10125   },
10126
10127   /* VEX_LEN_0F38F7_P_0 */
10128   {
10129     { "bextrS",         { Gdq, Edq, VexGdq }, 0 },
10130   },
10131
10132   /* VEX_LEN_0F38F7_P_1 */
10133   {
10134     { "sarxS",          { Gdq, Edq, VexGdq }, 0 },
10135   },
10136
10137   /* VEX_LEN_0F38F7_P_2 */
10138   {
10139     { "shlxS",          { Gdq, Edq, VexGdq }, 0 },
10140   },
10141
10142   /* VEX_LEN_0F38F7_P_3 */
10143   {
10144     { "shrxS",          { Gdq, Edq, VexGdq }, 0 },
10145   },
10146
10147   /* VEX_LEN_0F3A00_P_2 */
10148   {
10149     { Bad_Opcode },
10150     { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
10151   },
10152
10153   /* VEX_LEN_0F3A01_P_2 */
10154   {
10155     { Bad_Opcode },
10156     { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
10157   },
10158
10159   /* VEX_LEN_0F3A06_P_2 */
10160   {
10161     { Bad_Opcode },
10162     { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
10163   },
10164
10165   /* VEX_LEN_0F3A0A_P_2 */
10166   {
10167     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
10168     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
10169   },
10170
10171   /* VEX_LEN_0F3A0B_P_2 */
10172   {
10173     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
10174     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
10175   },
10176
10177   /* VEX_LEN_0F3A14_P_2 */
10178   {
10179     { VEX_W_TABLE (VEX_W_0F3A14_P_2) },
10180   },
10181
10182   /* VEX_LEN_0F3A15_P_2 */
10183   {
10184     { VEX_W_TABLE (VEX_W_0F3A15_P_2) },
10185   },
10186
10187   /* VEX_LEN_0F3A16_P_2  */
10188   {
10189     { "vpextrK",        { Edq, XM, Ib }, 0 },
10190   },
10191
10192   /* VEX_LEN_0F3A17_P_2 */
10193   {
10194     { "vextractps",     { Edqd, XM, Ib }, 0 },
10195   },
10196
10197   /* VEX_LEN_0F3A18_P_2 */
10198   {
10199     { Bad_Opcode },
10200     { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
10201   },
10202
10203   /* VEX_LEN_0F3A19_P_2 */
10204   {
10205     { Bad_Opcode },
10206     { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
10207   },
10208
10209   /* VEX_LEN_0F3A20_P_2 */
10210   {
10211     { VEX_W_TABLE (VEX_W_0F3A20_P_2) },
10212   },
10213
10214   /* VEX_LEN_0F3A21_P_2 */
10215   {
10216     { VEX_W_TABLE (VEX_W_0F3A21_P_2) },
10217   },
10218
10219   /* VEX_LEN_0F3A22_P_2 */
10220   {
10221     { "vpinsrK",        { XM, Vex128, Edq, Ib }, 0 },
10222   },
10223
10224   /* VEX_LEN_0F3A30_P_2 */
10225   {
10226     { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
10227   },
10228
10229   /* VEX_LEN_0F3A31_P_2 */
10230   {
10231     { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
10232   },
10233
10234   /* VEX_LEN_0F3A32_P_2 */
10235   {
10236     { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
10237   },
10238
10239   /* VEX_LEN_0F3A33_P_2 */
10240   {
10241     { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
10242   },
10243
10244   /* VEX_LEN_0F3A38_P_2 */
10245   {
10246     { Bad_Opcode },
10247     { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
10248   },
10249
10250   /* VEX_LEN_0F3A39_P_2 */
10251   {
10252     { Bad_Opcode },
10253     { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
10254   },
10255
10256   /* VEX_LEN_0F3A41_P_2 */
10257   {
10258     { VEX_W_TABLE (VEX_W_0F3A41_P_2) },
10259   },
10260
10261   /* VEX_LEN_0F3A44_P_2 */
10262   {
10263     { VEX_W_TABLE (VEX_W_0F3A44_P_2) },
10264   },
10265
10266   /* VEX_LEN_0F3A46_P_2 */
10267   {
10268     { Bad_Opcode },
10269     { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
10270   },
10271
10272   /* VEX_LEN_0F3A60_P_2 */
10273   {
10274     { VEX_W_TABLE (VEX_W_0F3A60_P_2) },
10275   },
10276
10277   /* VEX_LEN_0F3A61_P_2 */
10278   {
10279     { VEX_W_TABLE (VEX_W_0F3A61_P_2) },
10280   },
10281
10282   /* VEX_LEN_0F3A62_P_2 */
10283   {
10284     { VEX_W_TABLE (VEX_W_0F3A62_P_2) },
10285   },
10286
10287   /* VEX_LEN_0F3A63_P_2 */
10288   {
10289     { VEX_W_TABLE (VEX_W_0F3A63_P_2) },
10290   },
10291
10292   /* VEX_LEN_0F3A6A_P_2 */
10293   {
10294     { "vfmaddss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10295   },
10296
10297   /* VEX_LEN_0F3A6B_P_2 */
10298   {
10299     { "vfmaddsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10300   },
10301
10302   /* VEX_LEN_0F3A6E_P_2 */
10303   {
10304     { "vfmsubss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10305   },
10306
10307   /* VEX_LEN_0F3A6F_P_2 */
10308   {
10309     { "vfmsubsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10310   },
10311
10312   /* VEX_LEN_0F3A7A_P_2 */
10313   {
10314     { "vfnmaddss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10315   },
10316
10317   /* VEX_LEN_0F3A7B_P_2 */
10318   {
10319     { "vfnmaddsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10320   },
10321
10322   /* VEX_LEN_0F3A7E_P_2 */
10323   {
10324     { "vfnmsubss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10325   },
10326
10327   /* VEX_LEN_0F3A7F_P_2 */
10328   {
10329     { "vfnmsubsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10330   },
10331
10332   /* VEX_LEN_0F3ADF_P_2 */
10333   {
10334     { VEX_W_TABLE (VEX_W_0F3ADF_P_2) },
10335   },
10336
10337   /* VEX_LEN_0F3AF0_P_3 */
10338   {
10339     { "rorxS",          { Gdq, Edq, Ib }, 0 },
10340   },
10341
10342   /* VEX_LEN_0FXOP_08_CC */
10343   {
10344      { "vpcomb",        { XM, Vex128, EXx, Ib }, 0 },
10345   },
10346
10347   /* VEX_LEN_0FXOP_08_CD */
10348   {
10349      { "vpcomw",        { XM, Vex128, EXx, Ib }, 0 },
10350   },
10351
10352   /* VEX_LEN_0FXOP_08_CE */
10353   {
10354      { "vpcomd",        { XM, Vex128, EXx, Ib }, 0 },
10355   },
10356
10357   /* VEX_LEN_0FXOP_08_CF */
10358   {
10359      { "vpcomq",        { XM, Vex128, EXx, Ib }, 0 },
10360   },
10361
10362   /* VEX_LEN_0FXOP_08_EC */
10363   {
10364      { "vpcomub",       { XM, Vex128, EXx, Ib }, 0 },
10365   },
10366
10367   /* VEX_LEN_0FXOP_08_ED */
10368   {
10369      { "vpcomuw",       { XM, Vex128, EXx, Ib }, 0 },
10370   },
10371
10372   /* VEX_LEN_0FXOP_08_EE */
10373   {
10374      { "vpcomud",       { XM, Vex128, EXx, Ib }, 0 },
10375   },
10376
10377   /* VEX_LEN_0FXOP_08_EF */
10378   {
10379      { "vpcomuq",       { XM, Vex128, EXx, Ib }, 0 },
10380   },
10381
10382   /* VEX_LEN_0FXOP_09_80 */
10383   {
10384     { "vfrczps",        { XM, EXxmm }, 0 },
10385     { "vfrczps",        { XM, EXymmq }, 0 },
10386   },
10387
10388   /* VEX_LEN_0FXOP_09_81 */
10389   {
10390     { "vfrczpd",        { XM, EXxmm }, 0 },
10391     { "vfrczpd",        { XM, EXymmq }, 0 },
10392   },
10393 };
10394
10395 static const struct dis386 vex_w_table[][2] = {
10396   {
10397     /* VEX_W_0F10_P_0 */
10398     { "vmovups",        { XM, EXx }, 0 },
10399   },
10400   {
10401     /* VEX_W_0F10_P_1 */
10402     { "vmovss",         { XMVexScalar, VexScalar, EXdScalar }, 0 },
10403   },
10404   {
10405     /* VEX_W_0F10_P_2 */
10406     { "vmovupd",        { XM, EXx }, 0 },
10407   },
10408   {
10409     /* VEX_W_0F10_P_3 */
10410     { "vmovsd",         { XMVexScalar, VexScalar, EXqScalar }, 0 },
10411   },
10412   {
10413     /* VEX_W_0F11_P_0 */
10414     { "vmovups",        { EXxS, XM }, 0 },
10415   },
10416   {
10417     /* VEX_W_0F11_P_1 */
10418     { "vmovss",         { EXdVexScalarS, VexScalar, XMScalar }, 0 },
10419   },
10420   {
10421     /* VEX_W_0F11_P_2 */
10422     { "vmovupd",        { EXxS, XM }, 0 },
10423   },
10424   {
10425     /* VEX_W_0F11_P_3 */
10426     { "vmovsd",         { EXqVexScalarS, VexScalar, XMScalar }, 0 },
10427   },
10428   {
10429     /* VEX_W_0F12_P_0_M_0 */
10430     { "vmovlps",        { XM, Vex128, EXq }, 0 },
10431   },
10432   {
10433     /* VEX_W_0F12_P_0_M_1 */
10434     { "vmovhlps",       { XM, Vex128, EXq }, 0 },
10435   },
10436   {
10437     /* VEX_W_0F12_P_1 */
10438     { "vmovsldup",      { XM, EXx }, 0 },
10439   },
10440   {
10441     /* VEX_W_0F12_P_2 */
10442     { "vmovlpd",        { XM, Vex128, EXq }, 0 },
10443   },
10444   {
10445     /* VEX_W_0F12_P_3 */
10446     { "vmovddup",       { XM, EXymmq }, 0 },
10447   },
10448   {
10449     /* VEX_W_0F13_M_0 */
10450     { "vmovlpX",        { EXq, XM }, 0 },
10451   },
10452   {
10453     /* VEX_W_0F14 */
10454     { "vunpcklpX",      { XM, Vex, EXx }, 0 },
10455   },
10456   {
10457     /* VEX_W_0F15 */
10458     { "vunpckhpX",      { XM, Vex, EXx }, 0 },
10459   },
10460   {
10461     /* VEX_W_0F16_P_0_M_0 */
10462     { "vmovhps",        { XM, Vex128, EXq }, 0 },
10463   },
10464   {
10465     /* VEX_W_0F16_P_0_M_1 */
10466     { "vmovlhps",       { XM, Vex128, EXq }, 0 },
10467   },
10468   {
10469     /* VEX_W_0F16_P_1 */
10470     { "vmovshdup",      { XM, EXx }, 0 },
10471   },
10472   {
10473     /* VEX_W_0F16_P_2 */
10474     { "vmovhpd",        { XM, Vex128, EXq }, 0 },
10475   },
10476   {
10477     /* VEX_W_0F17_M_0 */
10478     { "vmovhpX",        { EXq, XM }, 0 },
10479   },
10480   {
10481     /* VEX_W_0F28 */
10482     { "vmovapX",        { XM, EXx }, 0 },
10483   },
10484   {
10485     /* VEX_W_0F29 */
10486     { "vmovapX",        { EXxS, XM }, 0 },
10487   },
10488   {
10489     /* VEX_W_0F2B_M_0 */
10490     { "vmovntpX",       { Mx, XM }, 0 },
10491   },
10492   {
10493     /* VEX_W_0F2E_P_0 */
10494     { "vucomiss",       { XMScalar, EXdScalar }, 0 },
10495   },
10496   {
10497     /* VEX_W_0F2E_P_2 */
10498     { "vucomisd",       { XMScalar, EXqScalar }, 0 },
10499   },
10500   {
10501     /* VEX_W_0F2F_P_0 */
10502     { "vcomiss",        { XMScalar, EXdScalar }, 0 },
10503   },
10504   {
10505     /* VEX_W_0F2F_P_2 */
10506     { "vcomisd",        { XMScalar, EXqScalar }, 0 },
10507   },
10508   {
10509     /* VEX_W_0F41_P_0_LEN_1 */
10510     { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
10511     { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) },
10512   },
10513   {
10514     /* VEX_W_0F41_P_2_LEN_1 */
10515     { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) },
10516     { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) }
10517   },
10518   {
10519     /* VEX_W_0F42_P_0_LEN_1 */
10520     { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) },
10521     { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) },
10522   },
10523   {
10524     /* VEX_W_0F42_P_2_LEN_1 */
10525     { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) },
10526     { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) },
10527   },
10528   {
10529     /* VEX_W_0F44_P_0_LEN_0 */
10530     { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) },
10531     { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) },
10532   },
10533   {
10534     /* VEX_W_0F44_P_2_LEN_0 */
10535     { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) },
10536     { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) },
10537   },
10538   {
10539     /* VEX_W_0F45_P_0_LEN_1 */
10540     { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) },
10541     { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) },
10542   },
10543   {
10544     /* VEX_W_0F45_P_2_LEN_1 */
10545     { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) },
10546     { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) },
10547   },
10548   {
10549     /* VEX_W_0F46_P_0_LEN_1 */
10550     { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) },
10551     { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) },
10552   },
10553   {
10554     /* VEX_W_0F46_P_2_LEN_1 */
10555     { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) },
10556     { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) },
10557   },
10558   {
10559     /* VEX_W_0F47_P_0_LEN_1 */
10560     { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) },
10561     { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) },
10562   },
10563   {
10564     /* VEX_W_0F47_P_2_LEN_1 */
10565     { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) },
10566     { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) },
10567   },
10568   {
10569     /* VEX_W_0F4A_P_0_LEN_1 */
10570     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) },
10571     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) },
10572   },
10573   {
10574     /* VEX_W_0F4A_P_2_LEN_1 */
10575     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) },
10576     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) },
10577   },
10578   {
10579     /* VEX_W_0F4B_P_0_LEN_1 */
10580     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) },
10581     { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) },
10582   },
10583   {
10584     /* VEX_W_0F4B_P_2_LEN_1 */
10585     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
10586   },
10587   {
10588     /* VEX_W_0F50_M_0 */
10589     { "vmovmskpX",      { Gdq, XS }, 0 },
10590   },
10591   {
10592     /* VEX_W_0F51_P_0 */
10593     { "vsqrtps",        { XM, EXx }, 0 },
10594   },
10595   {
10596     /* VEX_W_0F51_P_1 */
10597     { "vsqrtss",        { XMScalar, VexScalar, EXdScalar }, 0 },
10598   },
10599   {
10600     /* VEX_W_0F51_P_2  */
10601     { "vsqrtpd",        { XM, EXx }, 0 },
10602   },
10603   {
10604     /* VEX_W_0F51_P_3 */
10605     { "vsqrtsd",        { XMScalar, VexScalar, EXqScalar }, 0 },
10606   },
10607   {
10608     /* VEX_W_0F52_P_0 */
10609     { "vrsqrtps",       { XM, EXx }, 0 },
10610   },
10611   {
10612     /* VEX_W_0F52_P_1 */
10613     { "vrsqrtss",       { XMScalar, VexScalar, EXdScalar }, 0 },
10614   },
10615   {
10616     /* VEX_W_0F53_P_0  */
10617     { "vrcpps",         { XM, EXx }, 0 },
10618   },
10619   {
10620     /* VEX_W_0F53_P_1  */
10621     { "vrcpss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10622   },
10623   {
10624     /* VEX_W_0F58_P_0  */
10625     { "vaddps",         { XM, Vex, EXx }, 0 },
10626   },
10627   {
10628     /* VEX_W_0F58_P_1  */
10629     { "vaddss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10630   },
10631   {
10632     /* VEX_W_0F58_P_2  */
10633     { "vaddpd",         { XM, Vex, EXx }, 0 },
10634   },
10635   {
10636     /* VEX_W_0F58_P_3  */
10637     { "vaddsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10638   },
10639   {
10640     /* VEX_W_0F59_P_0  */
10641     { "vmulps",         { XM, Vex, EXx }, 0 },
10642   },
10643   {
10644     /* VEX_W_0F59_P_1  */
10645     { "vmulss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10646   },
10647   {
10648     /* VEX_W_0F59_P_2  */
10649     { "vmulpd",         { XM, Vex, EXx }, 0 },
10650   },
10651   {
10652     /* VEX_W_0F59_P_3  */
10653     { "vmulsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10654   },
10655   {
10656     /* VEX_W_0F5A_P_0  */
10657     { "vcvtps2pd",      { XM, EXxmmq }, 0 },
10658   },
10659   {
10660     /* VEX_W_0F5A_P_1  */
10661     { "vcvtss2sd",      { XMScalar, VexScalar, EXdScalar }, 0 },
10662   },
10663   {
10664     /* VEX_W_0F5A_P_3  */
10665     { "vcvtsd2ss",      { XMScalar, VexScalar, EXqScalar }, 0 },
10666   },
10667   {
10668     /* VEX_W_0F5B_P_0  */
10669     { "vcvtdq2ps",      { XM, EXx }, 0 },
10670   },
10671   {
10672     /* VEX_W_0F5B_P_1  */
10673     { "vcvttps2dq",     { XM, EXx }, 0 },
10674   },
10675   {
10676     /* VEX_W_0F5B_P_2  */
10677     { "vcvtps2dq",      { XM, EXx }, 0 },
10678   },
10679   {
10680     /* VEX_W_0F5C_P_0  */
10681     { "vsubps",         { XM, Vex, EXx }, 0 },
10682   },
10683   {
10684     /* VEX_W_0F5C_P_1  */
10685     { "vsubss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10686   },
10687   {
10688     /* VEX_W_0F5C_P_2  */
10689     { "vsubpd",         { XM, Vex, EXx }, 0 },
10690   },
10691   {
10692     /* VEX_W_0F5C_P_3  */
10693     { "vsubsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10694   },
10695   {
10696     /* VEX_W_0F5D_P_0  */
10697     { "vminps",         { XM, Vex, EXx }, 0 },
10698   },
10699   {
10700     /* VEX_W_0F5D_P_1  */
10701     { "vminss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10702   },
10703   {
10704     /* VEX_W_0F5D_P_2  */
10705     { "vminpd",         { XM, Vex, EXx }, 0 },
10706   },
10707   {
10708     /* VEX_W_0F5D_P_3  */
10709     { "vminsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10710   },
10711   {
10712     /* VEX_W_0F5E_P_0  */
10713     { "vdivps",         { XM, Vex, EXx }, 0 },
10714   },
10715   {
10716     /* VEX_W_0F5E_P_1  */
10717     { "vdivss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10718   },
10719   {
10720     /* VEX_W_0F5E_P_2  */
10721     { "vdivpd",         { XM, Vex, EXx }, 0 },
10722   },
10723   {
10724     /* VEX_W_0F5E_P_3  */
10725     { "vdivsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10726   },
10727   {
10728     /* VEX_W_0F5F_P_0  */
10729     { "vmaxps",         { XM, Vex, EXx }, 0 },
10730   },
10731   {
10732     /* VEX_W_0F5F_P_1  */
10733     { "vmaxss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10734   },
10735   {
10736     /* VEX_W_0F5F_P_2  */
10737     { "vmaxpd",         { XM, Vex, EXx }, 0 },
10738   },
10739   {
10740     /* VEX_W_0F5F_P_3  */
10741     { "vmaxsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10742   },
10743   {
10744     /* VEX_W_0F60_P_2  */
10745     { "vpunpcklbw",     { XM, Vex, EXx }, 0 },
10746   },
10747   {
10748     /* VEX_W_0F61_P_2  */
10749     { "vpunpcklwd",     { XM, Vex, EXx }, 0 },
10750   },
10751   {
10752     /* VEX_W_0F62_P_2  */
10753     { "vpunpckldq",     { XM, Vex, EXx }, 0 },
10754   },
10755   {
10756     /* VEX_W_0F63_P_2  */
10757     { "vpacksswb",      { XM, Vex, EXx }, 0 },
10758   },
10759   {
10760     /* VEX_W_0F64_P_2  */
10761     { "vpcmpgtb",       { XM, Vex, EXx }, 0 },
10762   },
10763   {
10764     /* VEX_W_0F65_P_2  */
10765     { "vpcmpgtw",       { XM, Vex, EXx }, 0 },
10766   },
10767   {
10768     /* VEX_W_0F66_P_2  */
10769     { "vpcmpgtd",       { XM, Vex, EXx }, 0 },
10770   },
10771   {
10772     /* VEX_W_0F67_P_2  */
10773     { "vpackuswb",      { XM, Vex, EXx }, 0 },
10774   },
10775   {
10776     /* VEX_W_0F68_P_2  */
10777     { "vpunpckhbw",     { XM, Vex, EXx }, 0 },
10778   },
10779   {
10780     /* VEX_W_0F69_P_2  */
10781     { "vpunpckhwd",     { XM, Vex, EXx }, 0 },
10782   },
10783   {
10784     /* VEX_W_0F6A_P_2  */
10785     { "vpunpckhdq",     { XM, Vex, EXx }, 0 },
10786   },
10787   {
10788     /* VEX_W_0F6B_P_2  */
10789     { "vpackssdw",      { XM, Vex, EXx }, 0 },
10790   },
10791   {
10792     /* VEX_W_0F6C_P_2  */
10793     { "vpunpcklqdq",    { XM, Vex, EXx }, 0 },
10794   },
10795   {
10796     /* VEX_W_0F6D_P_2  */
10797     { "vpunpckhqdq",    { XM, Vex, EXx }, 0 },
10798   },
10799   {
10800     /* VEX_W_0F6F_P_1  */
10801     { "vmovdqu",        { XM, EXx }, 0 },
10802   },
10803   {
10804     /* VEX_W_0F6F_P_2  */
10805     { "vmovdqa",        { XM, EXx }, 0 },
10806   },
10807   {
10808     /* VEX_W_0F70_P_1 */
10809     { "vpshufhw",       { XM, EXx, Ib }, 0 },
10810   },
10811   {
10812     /* VEX_W_0F70_P_2 */
10813     { "vpshufd",        { XM, EXx, Ib }, 0 },
10814   },
10815   {
10816     /* VEX_W_0F70_P_3 */
10817     { "vpshuflw",       { XM, EXx, Ib }, 0 },
10818   },
10819   {
10820     /* VEX_W_0F71_R_2_P_2  */
10821     { "vpsrlw",         { Vex, XS, Ib }, 0 },
10822   },
10823   {
10824     /* VEX_W_0F71_R_4_P_2  */
10825     { "vpsraw",         { Vex, XS, Ib }, 0 },
10826   },
10827   {
10828     /* VEX_W_0F71_R_6_P_2  */
10829     { "vpsllw",         { Vex, XS, Ib }, 0 },
10830   },
10831   {
10832     /* VEX_W_0F72_R_2_P_2  */
10833     { "vpsrld",         { Vex, XS, Ib }, 0 },
10834   },
10835   {
10836     /* VEX_W_0F72_R_4_P_2  */
10837     { "vpsrad",         { Vex, XS, Ib }, 0 },
10838   },
10839   {
10840     /* VEX_W_0F72_R_6_P_2  */
10841     { "vpslld",         { Vex, XS, Ib }, 0 },
10842   },
10843   {
10844     /* VEX_W_0F73_R_2_P_2  */
10845     { "vpsrlq",         { Vex, XS, Ib }, 0 },
10846   },
10847   {
10848     /* VEX_W_0F73_R_3_P_2  */
10849     { "vpsrldq",        { Vex, XS, Ib }, 0 },
10850   },
10851   {
10852     /* VEX_W_0F73_R_6_P_2  */
10853     { "vpsllq",         { Vex, XS, Ib }, 0 },
10854   },
10855   {
10856     /* VEX_W_0F73_R_7_P_2  */
10857     { "vpslldq",        { Vex, XS, Ib }, 0 },
10858   },
10859   {
10860     /* VEX_W_0F74_P_2 */
10861     { "vpcmpeqb",       { XM, Vex, EXx }, 0 },
10862   },
10863   {
10864     /* VEX_W_0F75_P_2 */
10865     { "vpcmpeqw",       { XM, Vex, EXx }, 0 },
10866   },
10867   {
10868     /* VEX_W_0F76_P_2 */
10869     { "vpcmpeqd",       { XM, Vex, EXx }, 0 },
10870   },
10871   {
10872     /* VEX_W_0F77_P_0 */
10873     { "",               { VZERO }, 0 },
10874   },
10875   {
10876     /* VEX_W_0F7C_P_2 */
10877     { "vhaddpd",        { XM, Vex, EXx }, 0 },
10878   },
10879   {
10880     /* VEX_W_0F7C_P_3 */
10881     { "vhaddps",        { XM, Vex, EXx }, 0 },
10882   },
10883   {
10884     /* VEX_W_0F7D_P_2 */
10885     { "vhsubpd",        { XM, Vex, EXx }, 0 },
10886   },
10887   {
10888     /* VEX_W_0F7D_P_3 */
10889     { "vhsubps",        { XM, Vex, EXx }, 0 },
10890   },
10891   {
10892     /* VEX_W_0F7E_P_1 */
10893     { "vmovq",          { XMScalar, EXqScalar }, 0 },
10894   },
10895   {
10896     /* VEX_W_0F7F_P_1 */
10897     { "vmovdqu",        { EXxS, XM }, 0 },
10898   },
10899   {
10900     /* VEX_W_0F7F_P_2 */
10901     { "vmovdqa",        { EXxS, XM }, 0 },
10902   },
10903   {
10904     /* VEX_W_0F90_P_0_LEN_0 */
10905     { "kmovw",          { MaskG, MaskE }, 0 },
10906     { "kmovq",          { MaskG, MaskE }, 0 },
10907   },
10908   {
10909     /* VEX_W_0F90_P_2_LEN_0 */
10910     { "kmovb",          { MaskG, MaskBDE }, 0 },
10911     { "kmovd",          { MaskG, MaskBDE }, 0 },
10912   },
10913   {
10914     /* VEX_W_0F91_P_0_LEN_0 */
10915     { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
10916     { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
10917   },
10918   {
10919     /* VEX_W_0F91_P_2_LEN_0 */
10920     { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
10921     { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
10922   },
10923   {
10924     /* VEX_W_0F92_P_0_LEN_0 */
10925     { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
10926   },
10927   {
10928     /* VEX_W_0F92_P_2_LEN_0 */
10929     { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
10930   },
10931   {
10932     /* VEX_W_0F92_P_3_LEN_0 */
10933     { MOD_TABLE (MOD_VEX_W_0_0F92_P_3_LEN_0) },
10934     { MOD_TABLE (MOD_VEX_W_1_0F92_P_3_LEN_0) },
10935   },
10936   {
10937     /* VEX_W_0F93_P_0_LEN_0 */
10938     { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
10939   },
10940   {
10941     /* VEX_W_0F93_P_2_LEN_0 */
10942     { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
10943   },
10944   {
10945     /* VEX_W_0F93_P_3_LEN_0 */
10946     { MOD_TABLE (MOD_VEX_W_0_0F93_P_3_LEN_0) },
10947     { MOD_TABLE (MOD_VEX_W_1_0F93_P_3_LEN_0) },
10948   },
10949   {
10950     /* VEX_W_0F98_P_0_LEN_0 */
10951     { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
10952     { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
10953   },
10954   {
10955     /* VEX_W_0F98_P_2_LEN_0 */
10956     { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
10957     { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
10958   },
10959   {
10960     /* VEX_W_0F99_P_0_LEN_0 */
10961     { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
10962     { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
10963   },
10964   {
10965     /* VEX_W_0F99_P_2_LEN_0 */
10966     { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
10967     { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
10968   },
10969   {
10970     /* VEX_W_0FAE_R_2_M_0 */
10971     { "vldmxcsr",       { Md }, 0 },
10972   },
10973   {
10974     /* VEX_W_0FAE_R_3_M_0 */
10975     { "vstmxcsr",       { Md }, 0 },
10976   },
10977   {
10978     /* VEX_W_0FC2_P_0 */
10979     { "vcmpps",         { XM, Vex, EXx, VCMP }, 0 },
10980   },
10981   {
10982     /* VEX_W_0FC2_P_1 */
10983     { "vcmpss",         { XMScalar, VexScalar, EXdScalar, VCMP }, 0 },
10984   },
10985   {
10986     /* VEX_W_0FC2_P_2 */
10987     { "vcmppd",         { XM, Vex, EXx, VCMP }, 0 },
10988   },
10989   {
10990     /* VEX_W_0FC2_P_3 */
10991     { "vcmpsd",         { XMScalar, VexScalar, EXqScalar, VCMP }, 0 },
10992   },
10993   {
10994     /* VEX_W_0FC4_P_2 */
10995     { "vpinsrw",        { XM, Vex128, Edqw, Ib }, 0 },
10996   },
10997   {
10998     /* VEX_W_0FC5_P_2 */
10999     { "vpextrw",        { Gdq, XS, Ib }, 0 },
11000   },
11001   {
11002     /* VEX_W_0FD0_P_2 */
11003     { "vaddsubpd",      { XM, Vex, EXx }, 0 },
11004   },
11005   {
11006     /* VEX_W_0FD0_P_3 */
11007     { "vaddsubps",      { XM, Vex, EXx }, 0 },
11008   },
11009   {
11010     /* VEX_W_0FD1_P_2 */
11011     { "vpsrlw",         { XM, Vex, EXxmm }, 0 },
11012   },
11013   {
11014     /* VEX_W_0FD2_P_2 */
11015     { "vpsrld",         { XM, Vex, EXxmm }, 0 },
11016   },
11017   {
11018     /* VEX_W_0FD3_P_2 */
11019     { "vpsrlq",         { XM, Vex, EXxmm }, 0 },
11020   },
11021   {
11022     /* VEX_W_0FD4_P_2 */
11023     { "vpaddq",         { XM, Vex, EXx }, 0 },
11024   },
11025   {
11026     /* VEX_W_0FD5_P_2 */
11027     { "vpmullw",        { XM, Vex, EXx }, 0 },
11028   },
11029   {
11030     /* VEX_W_0FD6_P_2 */
11031     { "vmovq",          { EXqScalarS, XMScalar }, 0 },
11032   },
11033   {
11034     /* VEX_W_0FD7_P_2_M_1 */
11035     { "vpmovmskb",      { Gdq, XS }, 0 },
11036   },
11037   {
11038     /* VEX_W_0FD8_P_2 */
11039     { "vpsubusb",       { XM, Vex, EXx }, 0 },
11040   },
11041   {
11042     /* VEX_W_0FD9_P_2 */
11043     { "vpsubusw",       { XM, Vex, EXx }, 0 },
11044   },
11045   {
11046     /* VEX_W_0FDA_P_2 */
11047     { "vpminub",        { XM, Vex, EXx }, 0 },
11048   },
11049   {
11050     /* VEX_W_0FDB_P_2 */
11051     { "vpand",          { XM, Vex, EXx }, 0 },
11052   },
11053   {
11054     /* VEX_W_0FDC_P_2 */
11055     { "vpaddusb",       { XM, Vex, EXx }, 0 },
11056   },
11057   {
11058     /* VEX_W_0FDD_P_2 */
11059     { "vpaddusw",       { XM, Vex, EXx }, 0 },
11060   },
11061   {
11062     /* VEX_W_0FDE_P_2 */
11063     { "vpmaxub",        { XM, Vex, EXx }, 0 },
11064   },
11065   {
11066     /* VEX_W_0FDF_P_2 */
11067     { "vpandn",         { XM, Vex, EXx }, 0 },
11068   },
11069   {
11070     /* VEX_W_0FE0_P_2  */
11071     { "vpavgb",         { XM, Vex, EXx }, 0 },
11072   },
11073   {
11074     /* VEX_W_0FE1_P_2  */
11075     { "vpsraw",         { XM, Vex, EXxmm }, 0 },
11076   },
11077   {
11078     /* VEX_W_0FE2_P_2  */
11079     { "vpsrad",         { XM, Vex, EXxmm }, 0 },
11080   },
11081   {
11082     /* VEX_W_0FE3_P_2  */
11083     { "vpavgw",         { XM, Vex, EXx }, 0 },
11084   },
11085   {
11086     /* VEX_W_0FE4_P_2  */
11087     { "vpmulhuw",       { XM, Vex, EXx }, 0 },
11088   },
11089   {
11090     /* VEX_W_0FE5_P_2  */
11091     { "vpmulhw",        { XM, Vex, EXx }, 0 },
11092   },
11093   {
11094     /* VEX_W_0FE6_P_1  */
11095     { "vcvtdq2pd",      { XM, EXxmmq }, 0 },
11096   },
11097   {
11098     /* VEX_W_0FE6_P_2  */
11099     { "vcvttpd2dq%XY",  { XMM, EXx }, 0 },
11100   },
11101   {
11102     /* VEX_W_0FE6_P_3  */
11103     { "vcvtpd2dq%XY",   { XMM, EXx }, 0 },
11104   },
11105   {
11106     /* VEX_W_0FE7_P_2_M_0 */
11107     { "vmovntdq",       { Mx, XM }, 0 },
11108   },
11109   {
11110     /* VEX_W_0FE8_P_2  */
11111     { "vpsubsb",        { XM, Vex, EXx }, 0 },
11112   },
11113   {
11114     /* VEX_W_0FE9_P_2  */
11115     { "vpsubsw",        { XM, Vex, EXx }, 0 },
11116   },
11117   {
11118     /* VEX_W_0FEA_P_2  */
11119     { "vpminsw",        { XM, Vex, EXx }, 0 },
11120   },
11121   {
11122     /* VEX_W_0FEB_P_2  */
11123     { "vpor",           { XM, Vex, EXx }, 0 },
11124   },
11125   {
11126     /* VEX_W_0FEC_P_2  */
11127     { "vpaddsb",        { XM, Vex, EXx }, 0 },
11128   },
11129   {
11130     /* VEX_W_0FED_P_2  */
11131     { "vpaddsw",        { XM, Vex, EXx }, 0 },
11132   },
11133   {
11134     /* VEX_W_0FEE_P_2  */
11135     { "vpmaxsw",        { XM, Vex, EXx }, 0 },
11136   },
11137   {
11138     /* VEX_W_0FEF_P_2  */
11139     { "vpxor",          { XM, Vex, EXx }, 0 },
11140   },
11141   {
11142     /* VEX_W_0FF0_P_3_M_0 */
11143     { "vlddqu",         { XM, M }, 0 },
11144   },
11145   {
11146     /* VEX_W_0FF1_P_2 */
11147     { "vpsllw",         { XM, Vex, EXxmm }, 0 },
11148   },
11149   {
11150     /* VEX_W_0FF2_P_2 */
11151     { "vpslld",         { XM, Vex, EXxmm }, 0 },
11152   },
11153   {
11154     /* VEX_W_0FF3_P_2 */
11155     { "vpsllq",         { XM, Vex, EXxmm }, 0 },
11156   },
11157   {
11158     /* VEX_W_0FF4_P_2 */
11159     { "vpmuludq",       { XM, Vex, EXx }, 0 },
11160   },
11161   {
11162     /* VEX_W_0FF5_P_2 */
11163     { "vpmaddwd",       { XM, Vex, EXx }, 0 },
11164   },
11165   {
11166     /* VEX_W_0FF6_P_2 */
11167     { "vpsadbw",        { XM, Vex, EXx }, 0 },
11168   },
11169   {
11170     /* VEX_W_0FF7_P_2 */
11171     { "vmaskmovdqu",    { XM, XS }, 0 },
11172   },
11173   {
11174     /* VEX_W_0FF8_P_2 */
11175     { "vpsubb",         { XM, Vex, EXx }, 0 },
11176   },
11177   {
11178     /* VEX_W_0FF9_P_2 */
11179     { "vpsubw",         { XM, Vex, EXx }, 0 },
11180   },
11181   {
11182     /* VEX_W_0FFA_P_2 */
11183     { "vpsubd",         { XM, Vex, EXx }, 0 },
11184   },
11185   {
11186     /* VEX_W_0FFB_P_2 */
11187     { "vpsubq",         { XM, Vex, EXx }, 0 },
11188   },
11189   {
11190     /* VEX_W_0FFC_P_2 */
11191     { "vpaddb",         { XM, Vex, EXx }, 0 },
11192   },
11193   {
11194     /* VEX_W_0FFD_P_2 */
11195     { "vpaddw",         { XM, Vex, EXx }, 0 },
11196   },
11197   {
11198     /* VEX_W_0FFE_P_2 */
11199     { "vpaddd",         { XM, Vex, EXx }, 0 },
11200   },
11201   {
11202     /* VEX_W_0F3800_P_2  */
11203     { "vpshufb",        { XM, Vex, EXx }, 0 },
11204   },
11205   {
11206     /* VEX_W_0F3801_P_2  */
11207     { "vphaddw",        { XM, Vex, EXx }, 0 },
11208   },
11209   {
11210     /* VEX_W_0F3802_P_2  */
11211     { "vphaddd",        { XM, Vex, EXx }, 0 },
11212   },
11213   {
11214     /* VEX_W_0F3803_P_2  */
11215     { "vphaddsw",       { XM, Vex, EXx }, 0 },
11216   },
11217   {
11218     /* VEX_W_0F3804_P_2  */
11219     { "vpmaddubsw",     { XM, Vex, EXx }, 0 },
11220   },
11221   {
11222     /* VEX_W_0F3805_P_2  */
11223     { "vphsubw",        { XM, Vex, EXx }, 0 },
11224   },
11225   {
11226     /* VEX_W_0F3806_P_2  */
11227     { "vphsubd",        { XM, Vex, EXx }, 0 },
11228   },
11229   {
11230     /* VEX_W_0F3807_P_2  */
11231     { "vphsubsw",       { XM, Vex, EXx }, 0 },
11232   },
11233   {
11234     /* VEX_W_0F3808_P_2  */
11235     { "vpsignb",        { XM, Vex, EXx }, 0 },
11236   },
11237   {
11238     /* VEX_W_0F3809_P_2  */
11239     { "vpsignw",        { XM, Vex, EXx }, 0 },
11240   },
11241   {
11242     /* VEX_W_0F380A_P_2  */
11243     { "vpsignd",        { XM, Vex, EXx }, 0 },
11244   },
11245   {
11246     /* VEX_W_0F380B_P_2  */
11247     { "vpmulhrsw",      { XM, Vex, EXx }, 0 },
11248   },
11249   {
11250     /* VEX_W_0F380C_P_2  */
11251     { "vpermilps",      { XM, Vex, EXx }, 0 },
11252   },
11253   {
11254     /* VEX_W_0F380D_P_2  */
11255     { "vpermilpd",      { XM, Vex, EXx }, 0 },
11256   },
11257   {
11258     /* VEX_W_0F380E_P_2  */
11259     { "vtestps",        { XM, EXx }, 0 },
11260   },
11261   {
11262     /* VEX_W_0F380F_P_2  */
11263     { "vtestpd",        { XM, EXx }, 0 },
11264   },
11265   {
11266     /* VEX_W_0F3816_P_2  */
11267     { "vpermps",        { XM, Vex, EXx }, 0 },
11268   },
11269   {
11270     /* VEX_W_0F3817_P_2 */
11271     { "vptest",         { XM, EXx }, 0 },
11272   },
11273   {
11274     /* VEX_W_0F3818_P_2 */
11275     { "vbroadcastss",   { XM, EXxmm_md }, 0 },
11276   },
11277   {
11278     /* VEX_W_0F3819_P_2 */
11279     { "vbroadcastsd",   { XM, EXxmm_mq }, 0 },
11280   },
11281   {
11282     /* VEX_W_0F381A_P_2_M_0 */
11283     { "vbroadcastf128", { XM, Mxmm }, 0 },
11284   },
11285   {
11286     /* VEX_W_0F381C_P_2 */
11287     { "vpabsb",         { XM, EXx }, 0 },
11288   },
11289   {
11290     /* VEX_W_0F381D_P_2 */
11291     { "vpabsw",         { XM, EXx }, 0 },
11292   },
11293   {
11294     /* VEX_W_0F381E_P_2 */
11295     { "vpabsd",         { XM, EXx }, 0 },
11296   },
11297   {
11298     /* VEX_W_0F3820_P_2 */
11299     { "vpmovsxbw",      { XM, EXxmmq }, 0 },
11300   },
11301   {
11302     /* VEX_W_0F3821_P_2 */
11303     { "vpmovsxbd",      { XM, EXxmmqd }, 0 },
11304   },
11305   {
11306     /* VEX_W_0F3822_P_2 */
11307     { "vpmovsxbq",      { XM, EXxmmdw }, 0 },
11308   },
11309   {
11310     /* VEX_W_0F3823_P_2 */
11311     { "vpmovsxwd",      { XM, EXxmmq }, 0 },
11312   },
11313   {
11314     /* VEX_W_0F3824_P_2 */
11315     { "vpmovsxwq",      { XM, EXxmmqd }, 0 },
11316   },
11317   {
11318     /* VEX_W_0F3825_P_2 */
11319     { "vpmovsxdq",      { XM, EXxmmq }, 0 },
11320   },
11321   {
11322     /* VEX_W_0F3828_P_2 */
11323     { "vpmuldq",        { XM, Vex, EXx }, 0 },
11324   },
11325   {
11326     /* VEX_W_0F3829_P_2 */
11327     { "vpcmpeqq",       { XM, Vex, EXx }, 0 },
11328   },
11329   {
11330     /* VEX_W_0F382A_P_2_M_0 */
11331     { "vmovntdqa",      { XM, Mx }, 0 },
11332   },
11333   {
11334     /* VEX_W_0F382B_P_2 */
11335     { "vpackusdw",      { XM, Vex, EXx }, 0 },
11336   },
11337   {
11338     /* VEX_W_0F382C_P_2_M_0 */
11339     { "vmaskmovps",     { XM, Vex, Mx }, 0 },
11340   },
11341   {
11342     /* VEX_W_0F382D_P_2_M_0 */
11343     { "vmaskmovpd",     { XM, Vex, Mx }, 0 },
11344   },
11345   {
11346     /* VEX_W_0F382E_P_2_M_0 */
11347     { "vmaskmovps",     { Mx, Vex, XM }, 0 },
11348   },
11349   {
11350     /* VEX_W_0F382F_P_2_M_0 */
11351     { "vmaskmovpd",     { Mx, Vex, XM }, 0 },
11352   },
11353   {
11354     /* VEX_W_0F3830_P_2 */
11355     { "vpmovzxbw",      { XM, EXxmmq }, 0 },
11356   },
11357   {
11358     /* VEX_W_0F3831_P_2 */
11359     { "vpmovzxbd",      { XM, EXxmmqd }, 0 },
11360   },
11361   {
11362     /* VEX_W_0F3832_P_2 */
11363     { "vpmovzxbq",      { XM, EXxmmdw }, 0 },
11364   },
11365   {
11366     /* VEX_W_0F3833_P_2 */
11367     { "vpmovzxwd",      { XM, EXxmmq }, 0 },
11368   },
11369   {
11370     /* VEX_W_0F3834_P_2 */
11371     { "vpmovzxwq",      { XM, EXxmmqd }, 0 },
11372   },
11373   {
11374     /* VEX_W_0F3835_P_2 */
11375     { "vpmovzxdq",      { XM, EXxmmq }, 0 },
11376   },
11377   {
11378     /* VEX_W_0F3836_P_2  */
11379     { "vpermd",         { XM, Vex, EXx }, 0 },
11380   },
11381   {
11382     /* VEX_W_0F3837_P_2 */
11383     { "vpcmpgtq",       { XM, Vex, EXx }, 0 },
11384   },
11385   {
11386     /* VEX_W_0F3838_P_2 */
11387     { "vpminsb",        { XM, Vex, EXx }, 0 },
11388   },
11389   {
11390     /* VEX_W_0F3839_P_2 */
11391     { "vpminsd",        { XM, Vex, EXx }, 0 },
11392   },
11393   {
11394     /* VEX_W_0F383A_P_2 */
11395     { "vpminuw",        { XM, Vex, EXx }, 0 },
11396   },
11397   {
11398     /* VEX_W_0F383B_P_2 */
11399     { "vpminud",        { XM, Vex, EXx }, 0 },
11400   },
11401   {
11402     /* VEX_W_0F383C_P_2 */
11403     { "vpmaxsb",        { XM, Vex, EXx }, 0 },
11404   },
11405   {
11406     /* VEX_W_0F383D_P_2 */
11407     { "vpmaxsd",        { XM, Vex, EXx }, 0 },
11408   },
11409   {
11410     /* VEX_W_0F383E_P_2 */
11411     { "vpmaxuw",        { XM, Vex, EXx }, 0 },
11412   },
11413   {
11414     /* VEX_W_0F383F_P_2 */
11415     { "vpmaxud",        { XM, Vex, EXx }, 0 },
11416   },
11417   {
11418     /* VEX_W_0F3840_P_2 */
11419     { "vpmulld",        { XM, Vex, EXx }, 0 },
11420   },
11421   {
11422     /* VEX_W_0F3841_P_2 */
11423     { "vphminposuw",    { XM, EXx }, 0 },
11424   },
11425   {
11426     /* VEX_W_0F3846_P_2 */
11427     { "vpsravd",        { XM, Vex, EXx }, 0 },
11428   },
11429   {
11430     /* VEX_W_0F3858_P_2 */
11431     { "vpbroadcastd", { XM, EXxmm_md }, 0 },
11432   },
11433   {
11434     /* VEX_W_0F3859_P_2 */
11435     { "vpbroadcastq",   { XM, EXxmm_mq }, 0 },
11436   },
11437   {
11438     /* VEX_W_0F385A_P_2_M_0 */
11439     { "vbroadcasti128", { XM, Mxmm }, 0 },
11440   },
11441   {
11442     /* VEX_W_0F3878_P_2 */
11443     { "vpbroadcastb",   { XM, EXxmm_mb }, 0 },
11444   },
11445   {
11446     /* VEX_W_0F3879_P_2 */
11447     { "vpbroadcastw",   { XM, EXxmm_mw }, 0 },
11448   },
11449   {
11450     /* VEX_W_0F38DB_P_2 */
11451     { "vaesimc",        { XM, EXx }, 0 },
11452   },
11453   {
11454     /* VEX_W_0F38DC_P_2 */
11455     { "vaesenc",        { XM, Vex128, EXx }, 0 },
11456   },
11457   {
11458     /* VEX_W_0F38DD_P_2 */
11459     { "vaesenclast",    { XM, Vex128, EXx }, 0 },
11460   },
11461   {
11462     /* VEX_W_0F38DE_P_2 */
11463     { "vaesdec",        { XM, Vex128, EXx }, 0 },
11464   },
11465   {
11466     /* VEX_W_0F38DF_P_2 */
11467     { "vaesdeclast",    { XM, Vex128, EXx }, 0 },
11468   },
11469   {
11470     /* VEX_W_0F3A00_P_2 */
11471     { Bad_Opcode },
11472     { "vpermq",         { XM, EXx, Ib }, 0 },
11473   },
11474   {
11475     /* VEX_W_0F3A01_P_2 */
11476     { Bad_Opcode },
11477     { "vpermpd",        { XM, EXx, Ib }, 0 },
11478   },
11479   {
11480     /* VEX_W_0F3A02_P_2 */
11481     { "vpblendd",       { XM, Vex, EXx, Ib }, 0 },
11482   },
11483   {
11484     /* VEX_W_0F3A04_P_2 */
11485     { "vpermilps",      { XM, EXx, Ib }, 0 },
11486   },
11487   {
11488     /* VEX_W_0F3A05_P_2 */
11489     { "vpermilpd",      { XM, EXx, Ib }, 0 },
11490   },
11491   {
11492     /* VEX_W_0F3A06_P_2 */
11493     { "vperm2f128",     { XM, Vex256, EXx, Ib }, 0 },
11494   },
11495   {
11496     /* VEX_W_0F3A08_P_2 */
11497     { "vroundps",       { XM, EXx, Ib }, 0 },
11498   },
11499   {
11500     /* VEX_W_0F3A09_P_2 */
11501     { "vroundpd",       { XM, EXx, Ib }, 0 },
11502   },
11503   {
11504     /* VEX_W_0F3A0A_P_2 */
11505     { "vroundss",       { XMScalar, VexScalar, EXdScalar, Ib }, 0 },
11506   },
11507   {
11508     /* VEX_W_0F3A0B_P_2 */
11509     { "vroundsd",       { XMScalar, VexScalar, EXqScalar, Ib }, 0 },
11510   },
11511   {
11512     /* VEX_W_0F3A0C_P_2 */
11513     { "vblendps",       { XM, Vex, EXx, Ib }, 0 },
11514   },
11515   {
11516     /* VEX_W_0F3A0D_P_2 */
11517     { "vblendpd",       { XM, Vex, EXx, Ib }, 0 },
11518   },
11519   {
11520     /* VEX_W_0F3A0E_P_2 */
11521     { "vpblendw",       { XM, Vex, EXx, Ib }, 0 },
11522   },
11523   {
11524     /* VEX_W_0F3A0F_P_2 */
11525     { "vpalignr",       { XM, Vex, EXx, Ib }, 0 },
11526   },
11527   {
11528     /* VEX_W_0F3A14_P_2 */
11529     { "vpextrb",        { Edqb, XM, Ib }, 0 },
11530   },
11531   {
11532     /* VEX_W_0F3A15_P_2 */
11533     { "vpextrw",        { Edqw, XM, Ib }, 0 },
11534   },
11535   {
11536     /* VEX_W_0F3A18_P_2 */
11537     { "vinsertf128",    { XM, Vex256, EXxmm, Ib }, 0 },
11538   },
11539   {
11540     /* VEX_W_0F3A19_P_2 */
11541     { "vextractf128",   { EXxmm, XM, Ib }, 0 },
11542   },
11543   {
11544     /* VEX_W_0F3A20_P_2 */
11545     { "vpinsrb",        { XM, Vex128, Edqb, Ib }, 0 },
11546   },
11547   {
11548     /* VEX_W_0F3A21_P_2 */
11549     { "vinsertps",      { XM, Vex128, EXd, Ib }, 0 },
11550   },
11551   {
11552     /* VEX_W_0F3A30_P_2_LEN_0 */
11553     { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) },
11554     { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) },
11555   },
11556   {
11557     /* VEX_W_0F3A31_P_2_LEN_0 */
11558     { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) },
11559     { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) },
11560   },
11561   {
11562     /* VEX_W_0F3A32_P_2_LEN_0 */
11563     { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) },
11564     { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) },
11565   },
11566   {
11567     /* VEX_W_0F3A33_P_2_LEN_0 */
11568     { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) },
11569     { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) },
11570   },
11571   {
11572     /* VEX_W_0F3A38_P_2 */
11573     { "vinserti128",    { XM, Vex256, EXxmm, Ib }, 0 },
11574   },
11575   {
11576     /* VEX_W_0F3A39_P_2 */
11577     { "vextracti128",   { EXxmm, XM, Ib }, 0 },
11578   },
11579   {
11580     /* VEX_W_0F3A40_P_2 */
11581     { "vdpps",          { XM, Vex, EXx, Ib }, 0 },
11582   },
11583   {
11584     /* VEX_W_0F3A41_P_2 */
11585     { "vdppd",          { XM, Vex128, EXx, Ib }, 0 },
11586   },
11587   {
11588     /* VEX_W_0F3A42_P_2 */
11589     { "vmpsadbw",       { XM, Vex, EXx, Ib }, 0 },
11590   },
11591   {
11592     /* VEX_W_0F3A44_P_2 */
11593     { "vpclmulqdq",     { XM, Vex128, EXx, PCLMUL }, 0 },
11594   },
11595   {
11596     /* VEX_W_0F3A46_P_2 */
11597     { "vperm2i128",     { XM, Vex256, EXx, Ib }, 0 },
11598   },
11599   {
11600     /* VEX_W_0F3A48_P_2 */
11601     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11602     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11603   },
11604   {
11605     /* VEX_W_0F3A49_P_2 */
11606     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11607     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11608   },
11609   {
11610     /* VEX_W_0F3A4A_P_2 */
11611     { "vblendvps",      { XM, Vex, EXx, XMVexI4 }, 0 },
11612   },
11613   {
11614     /* VEX_W_0F3A4B_P_2 */
11615     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 }, 0 },
11616   },
11617   {
11618     /* VEX_W_0F3A4C_P_2 */
11619     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 }, 0 },
11620   },
11621   {
11622     /* VEX_W_0F3A60_P_2 */
11623     { "vpcmpestrm",     { XM, EXx, Ib }, 0 },
11624   },
11625   {
11626     /* VEX_W_0F3A61_P_2 */
11627     { "vpcmpestri",     { XM, EXx, Ib }, 0 },
11628   },
11629   {
11630     /* VEX_W_0F3A62_P_2 */
11631     { "vpcmpistrm",     { XM, EXx, Ib }, 0 },
11632   },
11633   {
11634     /* VEX_W_0F3A63_P_2 */
11635     { "vpcmpistri",     { XM, EXx, Ib }, 0 },
11636   },
11637   {
11638     /* VEX_W_0F3ADF_P_2 */
11639     { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
11640   },
11641 #define NEED_VEX_W_TABLE
11642 #include "i386-dis-evex.h"
11643 #undef NEED_VEX_W_TABLE
11644 };
11645
11646 static const struct dis386 mod_table[][2] = {
11647   {
11648     /* MOD_8D */
11649     { "leaS",           { Gv, M }, 0 },
11650   },
11651   {
11652     /* MOD_C6_REG_7 */
11653     { Bad_Opcode },
11654     { RM_TABLE (RM_C6_REG_7) },
11655   },
11656   {
11657     /* MOD_C7_REG_7 */
11658     { Bad_Opcode },
11659     { RM_TABLE (RM_C7_REG_7) },
11660   },
11661   {
11662     /* MOD_FF_REG_3 */
11663     { "Jcall^", { indirEp }, 0 },
11664   },
11665   {
11666     /* MOD_FF_REG_5 */
11667     { "Jjmp^", { indirEp }, 0 },
11668   },
11669   {
11670     /* MOD_0F01_REG_0 */
11671     { X86_64_TABLE (X86_64_0F01_REG_0) },
11672     { RM_TABLE (RM_0F01_REG_0) },
11673   },
11674   {
11675     /* MOD_0F01_REG_1 */
11676     { X86_64_TABLE (X86_64_0F01_REG_1) },
11677     { RM_TABLE (RM_0F01_REG_1) },
11678   },
11679   {
11680     /* MOD_0F01_REG_2 */
11681     { X86_64_TABLE (X86_64_0F01_REG_2) },
11682     { RM_TABLE (RM_0F01_REG_2) },
11683   },
11684   {
11685     /* MOD_0F01_REG_3 */
11686     { X86_64_TABLE (X86_64_0F01_REG_3) },
11687     { RM_TABLE (RM_0F01_REG_3) },
11688   },
11689   {
11690     /* MOD_0F01_REG_5 */
11691     { Bad_Opcode },
11692     { RM_TABLE (RM_0F01_REG_5) },
11693   },
11694   {
11695     /* MOD_0F01_REG_7 */
11696     { "invlpg",         { Mb }, 0 },
11697     { RM_TABLE (RM_0F01_REG_7) },
11698   },
11699   {
11700     /* MOD_0F12_PREFIX_0 */
11701     { "movlps",         { XM, EXq }, PREFIX_OPCODE },
11702     { "movhlps",        { XM, EXq }, PREFIX_OPCODE },
11703   },
11704   {
11705     /* MOD_0F13 */
11706     { "movlpX",         { EXq, XM }, PREFIX_OPCODE },
11707   },
11708   {
11709     /* MOD_0F16_PREFIX_0 */
11710     { "movhps",         { XM, EXq }, 0 },
11711     { "movlhps",        { XM, EXq }, 0 },
11712   },
11713   {
11714     /* MOD_0F17 */
11715     { "movhpX",         { EXq, XM }, PREFIX_OPCODE },
11716   },
11717   {
11718     /* MOD_0F18_REG_0 */
11719     { "prefetchnta",    { Mb }, 0 },
11720   },
11721   {
11722     /* MOD_0F18_REG_1 */
11723     { "prefetcht0",     { Mb }, 0 },
11724   },
11725   {
11726     /* MOD_0F18_REG_2 */
11727     { "prefetcht1",     { Mb }, 0 },
11728   },
11729   {
11730     /* MOD_0F18_REG_3 */
11731     { "prefetcht2",     { Mb }, 0 },
11732   },
11733   {
11734     /* MOD_0F18_REG_4 */
11735     { "nop/reserved",   { Mb }, 0 },
11736   },
11737   {
11738     /* MOD_0F18_REG_5 */
11739     { "nop/reserved",   { Mb }, 0 },
11740   },
11741   {
11742     /* MOD_0F18_REG_6 */
11743     { "nop/reserved",   { Mb }, 0 },
11744   },
11745   {
11746     /* MOD_0F18_REG_7 */
11747     { "nop/reserved",   { Mb }, 0 },
11748   },
11749   {
11750     /* MOD_0F1A_PREFIX_0 */
11751     { "bndldx",         { Gbnd, Ev_bnd }, 0 },
11752     { "nopQ",           { Ev }, 0 },
11753   },
11754   {
11755     /* MOD_0F1B_PREFIX_0 */
11756     { "bndstx",         { Ev_bnd, Gbnd }, 0 },
11757     { "nopQ",           { Ev }, 0 },
11758   },
11759   {
11760     /* MOD_0F1B_PREFIX_1 */
11761     { "bndmk",          { Gbnd, Ev_bnd }, 0 },
11762     { "nopQ",           { Ev }, 0 },
11763   },
11764   {
11765     /* MOD_0F24 */
11766     { Bad_Opcode },
11767     { "movL",           { Rd, Td }, 0 },
11768   },
11769   {
11770     /* MOD_0F26 */
11771     { Bad_Opcode },
11772     { "movL",           { Td, Rd }, 0 },
11773   },
11774   {
11775     /* MOD_0F2B_PREFIX_0 */
11776     {"movntps",         { Mx, XM }, PREFIX_OPCODE },
11777   },
11778   {
11779     /* MOD_0F2B_PREFIX_1 */
11780     {"movntss",         { Md, XM }, PREFIX_OPCODE },
11781   },
11782   {
11783     /* MOD_0F2B_PREFIX_2 */
11784     {"movntpd",         { Mx, XM }, PREFIX_OPCODE },
11785   },
11786   {
11787     /* MOD_0F2B_PREFIX_3 */
11788     {"movntsd",         { Mq, XM }, PREFIX_OPCODE },
11789   },
11790   {
11791     /* MOD_0F51 */
11792     { Bad_Opcode },
11793     { "movmskpX",       { Gdq, XS }, PREFIX_OPCODE },
11794   },
11795   {
11796     /* MOD_0F71_REG_2 */
11797     { Bad_Opcode },
11798     { "psrlw",          { MS, Ib }, 0 },
11799   },
11800   {
11801     /* MOD_0F71_REG_4 */
11802     { Bad_Opcode },
11803     { "psraw",          { MS, Ib }, 0 },
11804   },
11805   {
11806     /* MOD_0F71_REG_6 */
11807     { Bad_Opcode },
11808     { "psllw",          { MS, Ib }, 0 },
11809   },
11810   {
11811     /* MOD_0F72_REG_2 */
11812     { Bad_Opcode },
11813     { "psrld",          { MS, Ib }, 0 },
11814   },
11815   {
11816     /* MOD_0F72_REG_4 */
11817     { Bad_Opcode },
11818     { "psrad",          { MS, Ib }, 0 },
11819   },
11820   {
11821     /* MOD_0F72_REG_6 */
11822     { Bad_Opcode },
11823     { "pslld",          { MS, Ib }, 0 },
11824   },
11825   {
11826     /* MOD_0F73_REG_2 */
11827     { Bad_Opcode },
11828     { "psrlq",          { MS, Ib }, 0 },
11829   },
11830   {
11831     /* MOD_0F73_REG_3 */
11832     { Bad_Opcode },
11833     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
11834   },
11835   {
11836     /* MOD_0F73_REG_6 */
11837     { Bad_Opcode },
11838     { "psllq",          { MS, Ib }, 0 },
11839   },
11840   {
11841     /* MOD_0F73_REG_7 */
11842     { Bad_Opcode },
11843     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
11844   },
11845   {
11846     /* MOD_0FAE_REG_0 */
11847     { "fxsave",         { FXSAVE }, 0 },
11848     { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
11849   },
11850   {
11851     /* MOD_0FAE_REG_1 */
11852     { "fxrstor",        { FXSAVE }, 0 },
11853     { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
11854   },
11855   {
11856     /* MOD_0FAE_REG_2 */
11857     { "ldmxcsr",        { Md }, 0 },
11858     { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
11859   },
11860   {
11861     /* MOD_0FAE_REG_3 */
11862     { "stmxcsr",        { Md }, 0 },
11863     { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
11864   },
11865   {
11866     /* MOD_0FAE_REG_4 */
11867     { "xsave",          { FXSAVE }, 0 },
11868   },
11869   {
11870     /* MOD_0FAE_REG_5 */
11871     { "xrstor",         { FXSAVE }, 0 },
11872     { RM_TABLE (RM_0FAE_REG_5) },
11873   },
11874   {
11875     /* MOD_0FAE_REG_6 */
11876     { PREFIX_TABLE (PREFIX_0FAE_REG_6) },
11877     { RM_TABLE (RM_0FAE_REG_6) },
11878   },
11879   {
11880     /* MOD_0FAE_REG_7 */
11881     { PREFIX_TABLE (PREFIX_0FAE_REG_7) },
11882     { RM_TABLE (RM_0FAE_REG_7) },
11883   },
11884   {
11885     /* MOD_0FB2 */
11886     { "lssS",           { Gv, Mp }, 0 },
11887   },
11888   {
11889     /* MOD_0FB4 */
11890     { "lfsS",           { Gv, Mp }, 0 },
11891   },
11892   {
11893     /* MOD_0FB5 */
11894     { "lgsS",           { Gv, Mp }, 0 },
11895   },
11896   {
11897     /* MOD_0FC3 */
11898     { PREFIX_TABLE (PREFIX_MOD_0_0FC3) },
11899   },
11900   {
11901     /* MOD_0FC7_REG_3 */
11902     { "xrstors",        { FXSAVE }, 0 },
11903   },
11904   {
11905     /* MOD_0FC7_REG_4 */
11906     { "xsavec",         { FXSAVE }, 0 },
11907   },
11908   {
11909     /* MOD_0FC7_REG_5 */
11910     { "xsaves",         { FXSAVE }, 0 },
11911   },
11912   {
11913     /* MOD_0FC7_REG_6 */
11914     { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6) },
11915     { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6) }
11916   },
11917   {
11918     /* MOD_0FC7_REG_7 */
11919     { "vmptrst",        { Mq }, 0 },
11920     { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7) }
11921   },
11922   {
11923     /* MOD_0FD7 */
11924     { Bad_Opcode },
11925     { "pmovmskb",       { Gdq, MS }, 0 },
11926   },
11927   {
11928     /* MOD_0FE7_PREFIX_2 */
11929     { "movntdq",        { Mx, XM }, 0 },
11930   },
11931   {
11932     /* MOD_0FF0_PREFIX_3 */
11933     { "lddqu",          { XM, M }, 0 },
11934   },
11935   {
11936     /* MOD_0F382A_PREFIX_2 */
11937     { "movntdqa",       { XM, Mx }, 0 },
11938   },
11939   {
11940     /* MOD_62_32BIT */
11941     { "bound{S|}",      { Gv, Ma }, 0 },
11942     { EVEX_TABLE (EVEX_0F) },
11943   },
11944   {
11945     /* MOD_C4_32BIT */
11946     { "lesS",           { Gv, Mp }, 0 },
11947     { VEX_C4_TABLE (VEX_0F) },
11948   },
11949   {
11950     /* MOD_C5_32BIT */
11951     { "ldsS",           { Gv, Mp }, 0 },
11952     { VEX_C5_TABLE (VEX_0F) },
11953   },
11954   {
11955     /* MOD_VEX_0F12_PREFIX_0 */
11956     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
11957     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
11958   },
11959   {
11960     /* MOD_VEX_0F13 */
11961     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
11962   },
11963   {
11964     /* MOD_VEX_0F16_PREFIX_0 */
11965     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
11966     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
11967   },
11968   {
11969     /* MOD_VEX_0F17 */
11970     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
11971   },
11972   {
11973     /* MOD_VEX_0F2B */
11974     { VEX_W_TABLE (VEX_W_0F2B_M_0) },
11975   },
11976   {
11977     /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
11978     { Bad_Opcode },
11979     { "kandw",          { MaskG, MaskVex, MaskR }, 0 },
11980   },
11981   {
11982     /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
11983     { Bad_Opcode },
11984     { "kandq",          { MaskG, MaskVex, MaskR }, 0 },
11985   },
11986   {
11987     /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
11988     { Bad_Opcode },
11989     { "kandb",          { MaskG, MaskVex, MaskR }, 0 },
11990   },
11991   {
11992     /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
11993     { Bad_Opcode },
11994     { "kandd",          { MaskG, MaskVex, MaskR }, 0 },
11995   },
11996   {
11997     /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
11998     { Bad_Opcode },
11999     { "kandnw",         { MaskG, MaskVex, MaskR }, 0 },
12000   },
12001   {
12002     /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
12003     { Bad_Opcode },
12004     { "kandnq",         { MaskG, MaskVex, MaskR }, 0 },
12005   },
12006   {
12007     /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
12008     { Bad_Opcode },
12009     { "kandnb",         { MaskG, MaskVex, MaskR }, 0 },
12010   },
12011   {
12012     /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
12013     { Bad_Opcode },
12014     { "kandnd",         { MaskG, MaskVex, MaskR }, 0 },
12015   },
12016   {
12017     /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
12018     { Bad_Opcode },
12019     { "knotw",          { MaskG, MaskR }, 0 },
12020   },
12021   {
12022     /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
12023     { Bad_Opcode },
12024     { "knotq",          { MaskG, MaskR }, 0 },
12025   },
12026   {
12027     /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
12028     { Bad_Opcode },
12029     { "knotb",          { MaskG, MaskR }, 0 },
12030   },
12031   {
12032     /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
12033     { Bad_Opcode },
12034     { "knotd",          { MaskG, MaskR }, 0 },
12035   },
12036   {
12037     /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
12038     { Bad_Opcode },
12039     { "korw",       { MaskG, MaskVex, MaskR }, 0 },
12040   },
12041   {
12042     /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
12043     { Bad_Opcode },
12044     { "korq",       { MaskG, MaskVex, MaskR }, 0 },
12045   },
12046   {
12047     /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
12048     { Bad_Opcode },
12049     { "korb",       { MaskG, MaskVex, MaskR }, 0 },
12050   },
12051   {
12052     /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
12053     { Bad_Opcode },
12054     { "kord",       { MaskG, MaskVex, MaskR }, 0 },
12055   },
12056  {
12057     /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
12058     { Bad_Opcode },
12059     { "kxnorw",     { MaskG, MaskVex, MaskR }, 0 },
12060   },
12061   {
12062     /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
12063     { Bad_Opcode },
12064     { "kxnorq",     { MaskG, MaskVex, MaskR }, 0 },
12065   },
12066   {
12067     /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
12068     { Bad_Opcode },
12069     { "kxnorb",     { MaskG, MaskVex, MaskR }, 0 },
12070   },
12071   {
12072     /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
12073     { Bad_Opcode },
12074     { "kxnord",     { MaskG, MaskVex, MaskR }, 0 },
12075   },
12076   {
12077     /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
12078     { Bad_Opcode },
12079     { "kxorw",      { MaskG, MaskVex, MaskR }, 0 },
12080   },
12081   {
12082     /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
12083     { Bad_Opcode },
12084     { "kxorq",      { MaskG, MaskVex, MaskR }, 0 },
12085   },
12086   {
12087     /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
12088     { Bad_Opcode },
12089     { "kxorb",      { MaskG, MaskVex, MaskR }, 0 },
12090   },
12091   {
12092     /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
12093     { Bad_Opcode },
12094     { "kxord",      { MaskG, MaskVex, MaskR }, 0 },
12095   },
12096   {
12097     /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
12098     { Bad_Opcode },
12099     { "kaddw",          { MaskG, MaskVex, MaskR }, 0 },
12100   },
12101   {
12102     /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
12103     { Bad_Opcode },
12104     { "kaddq",          { MaskG, MaskVex, MaskR }, 0 },
12105   },
12106   {
12107     /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
12108     { Bad_Opcode },
12109     { "kaddb",          { MaskG, MaskVex, MaskR }, 0 },
12110   },
12111   {
12112     /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
12113     { Bad_Opcode },
12114     { "kaddd",          { MaskG, MaskVex, MaskR }, 0 },
12115   },
12116   {
12117     /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
12118     { Bad_Opcode },
12119     { "kunpckwd",   { MaskG, MaskVex, MaskR }, 0 },
12120   },
12121   {
12122     /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
12123     { Bad_Opcode },
12124     { "kunpckdq",   { MaskG, MaskVex, MaskR }, 0 },
12125   },
12126   {
12127     /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
12128     { Bad_Opcode },
12129     { "kunpckbw",   { MaskG, MaskVex, MaskR }, 0 },
12130   },
12131   {
12132     /* MOD_VEX_0F50 */
12133     { Bad_Opcode },
12134     { VEX_W_TABLE (VEX_W_0F50_M_0) },
12135   },
12136   {
12137     /* MOD_VEX_0F71_REG_2 */
12138     { Bad_Opcode },
12139     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
12140   },
12141   {
12142     /* MOD_VEX_0F71_REG_4 */
12143     { Bad_Opcode },
12144     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
12145   },
12146   {
12147     /* MOD_VEX_0F71_REG_6 */
12148     { Bad_Opcode },
12149     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
12150   },
12151   {
12152     /* MOD_VEX_0F72_REG_2 */
12153     { Bad_Opcode },
12154     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
12155   },
12156   {
12157     /* MOD_VEX_0F72_REG_4 */
12158     { Bad_Opcode },
12159     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
12160   },
12161   {
12162     /* MOD_VEX_0F72_REG_6 */
12163     { Bad_Opcode },
12164     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
12165   },
12166   {
12167     /* MOD_VEX_0F73_REG_2 */
12168     { Bad_Opcode },
12169     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
12170   },
12171   {
12172     /* MOD_VEX_0F73_REG_3 */
12173     { Bad_Opcode },
12174     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
12175   },
12176   {
12177     /* MOD_VEX_0F73_REG_6 */
12178     { Bad_Opcode },
12179     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
12180   },
12181   {
12182     /* MOD_VEX_0F73_REG_7 */
12183     { Bad_Opcode },
12184     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
12185   },
12186   {
12187     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
12188     { "kmovw",          { Ew, MaskG }, 0 },
12189     { Bad_Opcode },
12190   },
12191   {
12192     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
12193     { "kmovq",          { Eq, MaskG }, 0 },
12194     { Bad_Opcode },
12195   },
12196   {
12197     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
12198     { "kmovb",          { Eb, MaskG }, 0 },
12199     { Bad_Opcode },
12200   },
12201   {
12202     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
12203     { "kmovd",          { Ed, MaskG }, 0 },
12204     { Bad_Opcode },
12205   },
12206   {
12207     /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
12208     { Bad_Opcode },
12209     { "kmovw",          { MaskG, Rdq }, 0 },
12210   },
12211   {
12212     /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
12213     { Bad_Opcode },
12214     { "kmovb",          { MaskG, Rdq }, 0 },
12215   },
12216   {
12217     /* MOD_VEX_W_0_0F92_P_3_LEN_0 */
12218     { Bad_Opcode },
12219     { "kmovd",          { MaskG, Rdq }, 0 },
12220   },
12221   {
12222     /* MOD_VEX_W_1_0F92_P_3_LEN_0 */
12223     { Bad_Opcode },
12224     { "kmovq",          { MaskG, Rdq }, 0 },
12225   },
12226   {
12227     /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
12228     { Bad_Opcode },
12229     { "kmovw",          { Gdq, MaskR }, 0 },
12230   },
12231   {
12232     /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
12233     { Bad_Opcode },
12234     { "kmovb",          { Gdq, MaskR }, 0 },
12235   },
12236   {
12237     /* MOD_VEX_W_0_0F93_P_3_LEN_0 */
12238     { Bad_Opcode },
12239     { "kmovd",          { Gdq, MaskR }, 0 },
12240   },
12241   {
12242     /* MOD_VEX_W_1_0F93_P_3_LEN_0 */
12243     { Bad_Opcode },
12244     { "kmovq",          { Gdq, MaskR }, 0 },
12245   },
12246   {
12247     /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
12248     { Bad_Opcode },
12249     { "kortestw", { MaskG, MaskR }, 0 },
12250   },
12251   {
12252     /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
12253     { Bad_Opcode },
12254     { "kortestq", { MaskG, MaskR }, 0 },
12255   },
12256   {
12257     /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
12258     { Bad_Opcode },
12259     { "kortestb", { MaskG, MaskR }, 0 },
12260   },
12261   {
12262     /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
12263     { Bad_Opcode },
12264     { "kortestd", { MaskG, MaskR }, 0 },
12265   },
12266   {
12267     /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
12268     { Bad_Opcode },
12269     { "ktestw", { MaskG, MaskR }, 0 },
12270   },
12271   {
12272     /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
12273     { Bad_Opcode },
12274     { "ktestq", { MaskG, MaskR }, 0 },
12275   },
12276   {
12277     /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
12278     { Bad_Opcode },
12279     { "ktestb", { MaskG, MaskR }, 0 },
12280   },
12281   {
12282     /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
12283     { Bad_Opcode },
12284     { "ktestd", { MaskG, MaskR }, 0 },
12285   },
12286   {
12287     /* MOD_VEX_0FAE_REG_2 */
12288     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
12289   },
12290   {
12291     /* MOD_VEX_0FAE_REG_3 */
12292     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
12293   },
12294   {
12295     /* MOD_VEX_0FD7_PREFIX_2 */
12296     { Bad_Opcode },
12297     { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) },
12298   },
12299   {
12300     /* MOD_VEX_0FE7_PREFIX_2 */
12301     { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) },
12302   },
12303   {
12304     /* MOD_VEX_0FF0_PREFIX_3 */
12305     { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) },
12306   },
12307   {
12308     /* MOD_VEX_0F381A_PREFIX_2 */
12309     { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
12310   },
12311   {
12312     /* MOD_VEX_0F382A_PREFIX_2 */
12313     { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) },
12314   },
12315   {
12316     /* MOD_VEX_0F382C_PREFIX_2 */
12317     { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
12318   },
12319   {
12320     /* MOD_VEX_0F382D_PREFIX_2 */
12321     { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
12322   },
12323   {
12324     /* MOD_VEX_0F382E_PREFIX_2 */
12325     { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
12326   },
12327   {
12328     /* MOD_VEX_0F382F_PREFIX_2 */
12329     { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
12330   },
12331   {
12332     /* MOD_VEX_0F385A_PREFIX_2 */
12333     { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
12334   },
12335   {
12336     /* MOD_VEX_0F388C_PREFIX_2 */
12337     { "vpmaskmov%LW",   { XM, Vex, Mx }, 0 },
12338   },
12339   {
12340     /* MOD_VEX_0F388E_PREFIX_2 */
12341     { "vpmaskmov%LW",   { Mx, Vex, XM }, 0 },
12342   },
12343   {
12344     /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
12345     { Bad_Opcode },
12346     { "kshiftrb",       { MaskG, MaskR, Ib }, 0 },
12347   },
12348   {
12349     /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
12350     { Bad_Opcode },
12351     { "kshiftrw",       { MaskG, MaskR, Ib }, 0 },
12352   },
12353   {
12354     /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
12355     { Bad_Opcode },
12356     { "kshiftrd",       { MaskG, MaskR, Ib }, 0 },
12357   },
12358   {
12359     /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
12360     { Bad_Opcode },
12361     { "kshiftrq",       { MaskG, MaskR, Ib }, 0 },
12362   },
12363   {
12364     /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
12365     { Bad_Opcode },
12366     { "kshiftlb",       { MaskG, MaskR, Ib }, 0 },
12367   },
12368   {
12369     /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
12370     { Bad_Opcode },
12371     { "kshiftlw",       { MaskG, MaskR, Ib }, 0 },
12372   },
12373   {
12374     /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
12375     { Bad_Opcode },
12376     { "kshiftld",       { MaskG, MaskR, Ib }, 0 },
12377   },
12378   {
12379     /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
12380     { Bad_Opcode },
12381     { "kshiftlq",       { MaskG, MaskR, Ib }, 0 },
12382   },
12383 #define NEED_MOD_TABLE
12384 #include "i386-dis-evex.h"
12385 #undef NEED_MOD_TABLE
12386 };
12387
12388 static const struct dis386 rm_table[][8] = {
12389   {
12390     /* RM_C6_REG_7 */
12391     { "xabort",         { Skip_MODRM, Ib }, 0 },
12392   },
12393   {
12394     /* RM_C7_REG_7 */
12395     { "xbeginT",        { Skip_MODRM, Jv }, 0 },
12396   },
12397   {
12398     /* RM_0F01_REG_0 */
12399     { Bad_Opcode },
12400     { "vmcall",         { Skip_MODRM }, 0 },
12401     { "vmlaunch",       { Skip_MODRM }, 0 },
12402     { "vmresume",       { Skip_MODRM }, 0 },
12403     { "vmxoff",         { Skip_MODRM }, 0 },
12404   },
12405   {
12406     /* RM_0F01_REG_1 */
12407     { "monitor",        { { OP_Monitor, 0 } }, 0 },
12408     { "mwait",          { { OP_Mwait, 0 } }, 0 },
12409     { "clac",           { Skip_MODRM }, 0 },
12410     { "stac",           { Skip_MODRM }, 0 },
12411     { Bad_Opcode },
12412     { Bad_Opcode },
12413     { Bad_Opcode },
12414     { "encls",          { Skip_MODRM }, 0 },
12415   },
12416   {
12417     /* RM_0F01_REG_2 */
12418     { "xgetbv",         { Skip_MODRM }, 0 },
12419     { "xsetbv",         { Skip_MODRM }, 0 },
12420     { Bad_Opcode },
12421     { Bad_Opcode },
12422     { "vmfunc",         { Skip_MODRM }, 0 },
12423     { "xend",           { Skip_MODRM }, 0 },
12424     { "xtest",          { Skip_MODRM }, 0 },
12425     { "enclu",          { Skip_MODRM }, 0 },
12426   },
12427   {
12428     /* RM_0F01_REG_3 */
12429     { "vmrun",          { Skip_MODRM }, 0 },
12430     { "vmmcall",        { Skip_MODRM }, 0 },
12431     { "vmload",         { Skip_MODRM }, 0 },
12432     { "vmsave",         { Skip_MODRM }, 0 },
12433     { "stgi",           { Skip_MODRM }, 0 },
12434     { "clgi",           { Skip_MODRM }, 0 },
12435     { "skinit",         { Skip_MODRM }, 0 },
12436     { "invlpga",        { Skip_MODRM }, 0 },
12437   },
12438   {
12439     /* RM_0F01_REG_5 */
12440     { Bad_Opcode },
12441     { Bad_Opcode },
12442     { Bad_Opcode },
12443     { Bad_Opcode },
12444     { Bad_Opcode },
12445     { Bad_Opcode },
12446     { "rdpkru",         { Skip_MODRM }, 0 },
12447     { "wrpkru",         { Skip_MODRM }, 0 },
12448   },
12449   {
12450     /* RM_0F01_REG_7 */
12451     { "swapgs",         { Skip_MODRM }, 0  },
12452     { "rdtscp",         { Skip_MODRM }, 0  },
12453     { "monitorx",       { { OP_Monitor, 0 } }, 0  },
12454     { "mwaitx",         { { OP_Mwaitx,  0 } }, 0  },
12455     { "clzero",         { Skip_MODRM }, 0  },
12456   },
12457   {
12458     /* RM_0FAE_REG_5 */
12459     { "lfence",         { Skip_MODRM }, 0 },
12460   },
12461   {
12462     /* RM_0FAE_REG_6 */
12463     { "mfence",         { Skip_MODRM }, 0 },
12464   },
12465   {
12466     /* RM_0FAE_REG_7 */
12467     { PREFIX_TABLE (PREFIX_RM_0_0FAE_REG_7) },
12468   },
12469 };
12470
12471 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
12472
12473 /* We use the high bit to indicate different name for the same
12474    prefix.  */
12475 #define REP_PREFIX      (0xf3 | 0x100)
12476 #define XACQUIRE_PREFIX (0xf2 | 0x200)
12477 #define XRELEASE_PREFIX (0xf3 | 0x400)
12478 #define BND_PREFIX      (0xf2 | 0x400)
12479
12480 static int
12481 ckprefix (void)
12482 {
12483   int newrex, i, length;
12484   rex = 0;
12485   rex_ignored = 0;
12486   prefixes = 0;
12487   used_prefixes = 0;
12488   rex_used = 0;
12489   last_lock_prefix = -1;
12490   last_repz_prefix = -1;
12491   last_repnz_prefix = -1;
12492   last_data_prefix = -1;
12493   last_addr_prefix = -1;
12494   last_rex_prefix = -1;
12495   last_seg_prefix = -1;
12496   fwait_prefix = -1;
12497   active_seg_prefix = 0;
12498   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12499     all_prefixes[i] = 0;
12500   i = 0;
12501   length = 0;
12502   /* The maximum instruction length is 15bytes.  */
12503   while (length < MAX_CODE_LENGTH - 1)
12504     {
12505       FETCH_DATA (the_info, codep + 1);
12506       newrex = 0;
12507       switch (*codep)
12508         {
12509         /* REX prefixes family.  */
12510         case 0x40:
12511         case 0x41:
12512         case 0x42:
12513         case 0x43:
12514         case 0x44:
12515         case 0x45:
12516         case 0x46:
12517         case 0x47:
12518         case 0x48:
12519         case 0x49:
12520         case 0x4a:
12521         case 0x4b:
12522         case 0x4c:
12523         case 0x4d:
12524         case 0x4e:
12525         case 0x4f:
12526           if (address_mode == mode_64bit)
12527             newrex = *codep;
12528           else
12529             return 1;
12530           last_rex_prefix = i;
12531           break;
12532         case 0xf3:
12533           prefixes |= PREFIX_REPZ;
12534           last_repz_prefix = i;
12535           break;
12536         case 0xf2:
12537           prefixes |= PREFIX_REPNZ;
12538           last_repnz_prefix = i;
12539           break;
12540         case 0xf0:
12541           prefixes |= PREFIX_LOCK;
12542           last_lock_prefix = i;
12543           break;
12544         case 0x2e:
12545           prefixes |= PREFIX_CS;
12546           last_seg_prefix = i;
12547           active_seg_prefix = PREFIX_CS;
12548           break;
12549         case 0x36:
12550           prefixes |= PREFIX_SS;
12551           last_seg_prefix = i;
12552           active_seg_prefix = PREFIX_SS;
12553           break;
12554         case 0x3e:
12555           prefixes |= PREFIX_DS;
12556           last_seg_prefix = i;
12557           active_seg_prefix = PREFIX_DS;
12558           break;
12559         case 0x26:
12560           prefixes |= PREFIX_ES;
12561           last_seg_prefix = i;
12562           active_seg_prefix = PREFIX_ES;
12563           break;
12564         case 0x64:
12565           prefixes |= PREFIX_FS;
12566           last_seg_prefix = i;
12567           active_seg_prefix = PREFIX_FS;
12568           break;
12569         case 0x65:
12570           prefixes |= PREFIX_GS;
12571           last_seg_prefix = i;
12572           active_seg_prefix = PREFIX_GS;
12573           break;
12574         case 0x66:
12575           prefixes |= PREFIX_DATA;
12576           last_data_prefix = i;
12577           break;
12578         case 0x67:
12579           prefixes |= PREFIX_ADDR;
12580           last_addr_prefix = i;
12581           break;
12582         case FWAIT_OPCODE:
12583           /* fwait is really an instruction.  If there are prefixes
12584              before the fwait, they belong to the fwait, *not* to the
12585              following instruction.  */
12586           fwait_prefix = i;
12587           if (prefixes || rex)
12588             {
12589               prefixes |= PREFIX_FWAIT;
12590               codep++;
12591               /* This ensures that the previous REX prefixes are noticed
12592                  as unused prefixes, as in the return case below.  */
12593               rex_used = rex;
12594               return 1;
12595             }
12596           prefixes = PREFIX_FWAIT;
12597           break;
12598         default:
12599           return 1;
12600         }
12601       /* Rex is ignored when followed by another prefix.  */
12602       if (rex)
12603         {
12604           rex_used = rex;
12605           return 1;
12606         }
12607       if (*codep != FWAIT_OPCODE)
12608         all_prefixes[i++] = *codep;
12609       rex = newrex;
12610       codep++;
12611       length++;
12612     }
12613   return 0;
12614 }
12615
12616 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
12617    prefix byte.  */
12618
12619 static const char *
12620 prefix_name (int pref, int sizeflag)
12621 {
12622   static const char *rexes [16] =
12623     {
12624       "rex",            /* 0x40 */
12625       "rex.B",          /* 0x41 */
12626       "rex.X",          /* 0x42 */
12627       "rex.XB",         /* 0x43 */
12628       "rex.R",          /* 0x44 */
12629       "rex.RB",         /* 0x45 */
12630       "rex.RX",         /* 0x46 */
12631       "rex.RXB",        /* 0x47 */
12632       "rex.W",          /* 0x48 */
12633       "rex.WB",         /* 0x49 */
12634       "rex.WX",         /* 0x4a */
12635       "rex.WXB",        /* 0x4b */
12636       "rex.WR",         /* 0x4c */
12637       "rex.WRB",        /* 0x4d */
12638       "rex.WRX",        /* 0x4e */
12639       "rex.WRXB",       /* 0x4f */
12640     };
12641
12642   switch (pref)
12643     {
12644     /* REX prefixes family.  */
12645     case 0x40:
12646     case 0x41:
12647     case 0x42:
12648     case 0x43:
12649     case 0x44:
12650     case 0x45:
12651     case 0x46:
12652     case 0x47:
12653     case 0x48:
12654     case 0x49:
12655     case 0x4a:
12656     case 0x4b:
12657     case 0x4c:
12658     case 0x4d:
12659     case 0x4e:
12660     case 0x4f:
12661       return rexes [pref - 0x40];
12662     case 0xf3:
12663       return "repz";
12664     case 0xf2:
12665       return "repnz";
12666     case 0xf0:
12667       return "lock";
12668     case 0x2e:
12669       return "cs";
12670     case 0x36:
12671       return "ss";
12672     case 0x3e:
12673       return "ds";
12674     case 0x26:
12675       return "es";
12676     case 0x64:
12677       return "fs";
12678     case 0x65:
12679       return "gs";
12680     case 0x66:
12681       return (sizeflag & DFLAG) ? "data16" : "data32";
12682     case 0x67:
12683       if (address_mode == mode_64bit)
12684         return (sizeflag & AFLAG) ? "addr32" : "addr64";
12685       else
12686         return (sizeflag & AFLAG) ? "addr16" : "addr32";
12687     case FWAIT_OPCODE:
12688       return "fwait";
12689     case REP_PREFIX:
12690       return "rep";
12691     case XACQUIRE_PREFIX:
12692       return "xacquire";
12693     case XRELEASE_PREFIX:
12694       return "xrelease";
12695     case BND_PREFIX:
12696       return "bnd";
12697     default:
12698       return NULL;
12699     }
12700 }
12701
12702 static char op_out[MAX_OPERANDS][100];
12703 static int op_ad, op_index[MAX_OPERANDS];
12704 static int two_source_ops;
12705 static bfd_vma op_address[MAX_OPERANDS];
12706 static bfd_vma op_riprel[MAX_OPERANDS];
12707 static bfd_vma start_pc;
12708
12709 /*
12710  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
12711  *   (see topic "Redundant prefixes" in the "Differences from 8086"
12712  *   section of the "Virtual 8086 Mode" chapter.)
12713  * 'pc' should be the address of this instruction, it will
12714  *   be used to print the target address if this is a relative jump or call
12715  * The function returns the length of this instruction in bytes.
12716  */
12717
12718 static char intel_syntax;
12719 static char intel_mnemonic = !SYSV386_COMPAT;
12720 static char open_char;
12721 static char close_char;
12722 static char separator_char;
12723 static char scale_char;
12724
12725 enum x86_64_isa
12726 {
12727   amd64 = 0,
12728   intel64
12729 };
12730
12731 static enum x86_64_isa isa64;
12732
12733 /* Here for backwards compatibility.  When gdb stops using
12734    print_insn_i386_att and print_insn_i386_intel these functions can
12735    disappear, and print_insn_i386 be merged into print_insn.  */
12736 int
12737 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
12738 {
12739   intel_syntax = 0;
12740
12741   return print_insn (pc, info);
12742 }
12743
12744 int
12745 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
12746 {
12747   intel_syntax = 1;
12748
12749   return print_insn (pc, info);
12750 }
12751
12752 int
12753 print_insn_i386 (bfd_vma pc, disassemble_info *info)
12754 {
12755   intel_syntax = -1;
12756
12757   return print_insn (pc, info);
12758 }
12759
12760 void
12761 print_i386_disassembler_options (FILE *stream)
12762 {
12763   fprintf (stream, _("\n\
12764 The following i386/x86-64 specific disassembler options are supported for use\n\
12765 with the -M switch (multiple options should be separated by commas):\n"));
12766
12767   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
12768   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
12769   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
12770   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
12771   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
12772   fprintf (stream, _("  att-mnemonic\n"
12773                      "              Display instruction in AT&T mnemonic\n"));
12774   fprintf (stream, _("  intel-mnemonic\n"
12775                      "              Display instruction in Intel mnemonic\n"));
12776   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
12777   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
12778   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
12779   fprintf (stream, _("  data32      Assume 32bit data size\n"));
12780   fprintf (stream, _("  data16      Assume 16bit data size\n"));
12781   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
12782   fprintf (stream, _("  amd64       Display instruction in AMD64 ISA\n"));
12783   fprintf (stream, _("  intel64     Display instruction in Intel64 ISA\n"));
12784 }
12785
12786 /* Bad opcode.  */
12787 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
12788
12789 /* Get a pointer to struct dis386 with a valid name.  */
12790
12791 static const struct dis386 *
12792 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
12793 {
12794   int vindex, vex_table_index;
12795
12796   if (dp->name != NULL)
12797     return dp;
12798
12799   switch (dp->op[0].bytemode)
12800     {
12801     case USE_REG_TABLE:
12802       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
12803       break;
12804
12805     case USE_MOD_TABLE:
12806       vindex = modrm.mod == 0x3 ? 1 : 0;
12807       dp = &mod_table[dp->op[1].bytemode][vindex];
12808       break;
12809
12810     case USE_RM_TABLE:
12811       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
12812       break;
12813
12814     case USE_PREFIX_TABLE:
12815       if (need_vex)
12816         {
12817           /* The prefix in VEX is implicit.  */
12818           switch (vex.prefix)
12819             {
12820             case 0:
12821               vindex = 0;
12822               break;
12823             case REPE_PREFIX_OPCODE:
12824               vindex = 1;
12825               break;
12826             case DATA_PREFIX_OPCODE:
12827               vindex = 2;
12828               break;
12829             case REPNE_PREFIX_OPCODE:
12830               vindex = 3;
12831               break;
12832             default:
12833               abort ();
12834               break;
12835             }
12836         }
12837       else
12838         {
12839           int last_prefix = -1;
12840           int prefix = 0;
12841           vindex = 0;
12842           /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
12843              When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
12844              last one wins.  */
12845           if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
12846             {
12847               if (last_repz_prefix > last_repnz_prefix)
12848                 {
12849                   vindex = 1;
12850                   prefix = PREFIX_REPZ;
12851                   last_prefix = last_repz_prefix;
12852                 }
12853               else
12854                 {
12855                   vindex = 3;
12856                   prefix = PREFIX_REPNZ;
12857                   last_prefix = last_repnz_prefix;
12858                 }
12859
12860               /* Check if prefix should be ignored.  */
12861               if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
12862                      & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
12863                    & prefix) != 0)
12864                 vindex = 0;
12865             }
12866
12867           if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
12868             {
12869               vindex = 2;
12870               prefix = PREFIX_DATA;
12871               last_prefix = last_data_prefix;
12872             }
12873
12874           if (vindex != 0)
12875             {
12876               used_prefixes |= prefix;
12877               all_prefixes[last_prefix] = 0;
12878             }
12879         }
12880       dp = &prefix_table[dp->op[1].bytemode][vindex];
12881       break;
12882
12883     case USE_X86_64_TABLE:
12884       vindex = address_mode == mode_64bit ? 1 : 0;
12885       dp = &x86_64_table[dp->op[1].bytemode][vindex];
12886       break;
12887
12888     case USE_3BYTE_TABLE:
12889       FETCH_DATA (info, codep + 2);
12890       vindex = *codep++;
12891       dp = &three_byte_table[dp->op[1].bytemode][vindex];
12892       end_codep = codep;
12893       modrm.mod = (*codep >> 6) & 3;
12894       modrm.reg = (*codep >> 3) & 7;
12895       modrm.rm = *codep & 7;
12896       break;
12897
12898     case USE_VEX_LEN_TABLE:
12899       if (!need_vex)
12900         abort ();
12901
12902       switch (vex.length)
12903         {
12904         case 128:
12905           vindex = 0;
12906           break;
12907         case 256:
12908           vindex = 1;
12909           break;
12910         default:
12911           abort ();
12912           break;
12913         }
12914
12915       dp = &vex_len_table[dp->op[1].bytemode][vindex];
12916       break;
12917
12918     case USE_XOP_8F_TABLE:
12919       FETCH_DATA (info, codep + 3);
12920       /* All bits in the REX prefix are ignored.  */
12921       rex_ignored = rex;
12922       rex = ~(*codep >> 5) & 0x7;
12923
12924       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
12925       switch ((*codep & 0x1f))
12926         {
12927         default:
12928           dp = &bad_opcode;
12929           return dp;
12930         case 0x8:
12931           vex_table_index = XOP_08;
12932           break;
12933         case 0x9:
12934           vex_table_index = XOP_09;
12935           break;
12936         case 0xa:
12937           vex_table_index = XOP_0A;
12938           break;
12939         }
12940       codep++;
12941       vex.w = *codep & 0x80;
12942       if (vex.w && address_mode == mode_64bit)
12943         rex |= REX_W;
12944
12945       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12946       if (address_mode != mode_64bit
12947           && vex.register_specifier > 0x7)
12948         {
12949           dp = &bad_opcode;
12950           return dp;
12951         }
12952
12953       vex.length = (*codep & 0x4) ? 256 : 128;
12954       switch ((*codep & 0x3))
12955         {
12956         case 0:
12957           vex.prefix = 0;
12958           break;
12959         case 1:
12960           vex.prefix = DATA_PREFIX_OPCODE;
12961           break;
12962         case 2:
12963           vex.prefix = REPE_PREFIX_OPCODE;
12964           break;
12965         case 3:
12966           vex.prefix = REPNE_PREFIX_OPCODE;
12967           break;
12968         }
12969       need_vex = 1;
12970       need_vex_reg = 1;
12971       codep++;
12972       vindex = *codep++;
12973       dp = &xop_table[vex_table_index][vindex];
12974
12975       end_codep = codep;
12976       FETCH_DATA (info, codep + 1);
12977       modrm.mod = (*codep >> 6) & 3;
12978       modrm.reg = (*codep >> 3) & 7;
12979       modrm.rm = *codep & 7;
12980       break;
12981
12982     case USE_VEX_C4_TABLE:
12983       /* VEX prefix.  */
12984       FETCH_DATA (info, codep + 3);
12985       /* All bits in the REX prefix are ignored.  */
12986       rex_ignored = rex;
12987       rex = ~(*codep >> 5) & 0x7;
12988       switch ((*codep & 0x1f))
12989         {
12990         default:
12991           dp = &bad_opcode;
12992           return dp;
12993         case 0x1:
12994           vex_table_index = VEX_0F;
12995           break;
12996         case 0x2:
12997           vex_table_index = VEX_0F38;
12998           break;
12999         case 0x3:
13000           vex_table_index = VEX_0F3A;
13001           break;
13002         }
13003       codep++;
13004       vex.w = *codep & 0x80;
13005       if (vex.w && address_mode == mode_64bit)
13006         rex |= REX_W;
13007
13008       vex.register_specifier = (~(*codep >> 3)) & 0xf;
13009       if (address_mode != mode_64bit
13010           && vex.register_specifier > 0x7)
13011         {
13012           dp = &bad_opcode;
13013           return dp;
13014         }
13015
13016       vex.length = (*codep & 0x4) ? 256 : 128;
13017       switch ((*codep & 0x3))
13018         {
13019         case 0:
13020           vex.prefix = 0;
13021           break;
13022         case 1:
13023           vex.prefix = DATA_PREFIX_OPCODE;
13024           break;
13025         case 2:
13026           vex.prefix = REPE_PREFIX_OPCODE;
13027           break;
13028         case 3:
13029           vex.prefix = REPNE_PREFIX_OPCODE;
13030           break;
13031         }
13032       need_vex = 1;
13033       need_vex_reg = 1;
13034       codep++;
13035       vindex = *codep++;
13036       dp = &vex_table[vex_table_index][vindex];
13037       end_codep = codep;
13038       /* There is no MODRM byte for VEX [82|77].  */
13039       if (vindex != 0x77 && vindex != 0x82)
13040         {
13041           FETCH_DATA (info, codep + 1);
13042           modrm.mod = (*codep >> 6) & 3;
13043           modrm.reg = (*codep >> 3) & 7;
13044           modrm.rm = *codep & 7;
13045         }
13046       break;
13047
13048     case USE_VEX_C5_TABLE:
13049       /* VEX prefix.  */
13050       FETCH_DATA (info, codep + 2);
13051       /* All bits in the REX prefix are ignored.  */
13052       rex_ignored = rex;
13053       rex = (*codep & 0x80) ? 0 : REX_R;
13054
13055       vex.register_specifier = (~(*codep >> 3)) & 0xf;
13056       if (address_mode != mode_64bit
13057           && vex.register_specifier > 0x7)
13058         {
13059           dp = &bad_opcode;
13060           return dp;
13061         }
13062
13063       vex.w = 0;
13064
13065       vex.length = (*codep & 0x4) ? 256 : 128;
13066       switch ((*codep & 0x3))
13067         {
13068         case 0:
13069           vex.prefix = 0;
13070           break;
13071         case 1:
13072           vex.prefix = DATA_PREFIX_OPCODE;
13073           break;
13074         case 2:
13075           vex.prefix = REPE_PREFIX_OPCODE;
13076           break;
13077         case 3:
13078           vex.prefix = REPNE_PREFIX_OPCODE;
13079           break;
13080         }
13081       need_vex = 1;
13082       need_vex_reg = 1;
13083       codep++;
13084       vindex = *codep++;
13085       dp = &vex_table[dp->op[1].bytemode][vindex];
13086       end_codep = codep;
13087       /* There is no MODRM byte for VEX [82|77].  */
13088       if (vindex != 0x77 && vindex != 0x82)
13089         {
13090           FETCH_DATA (info, codep + 1);
13091           modrm.mod = (*codep >> 6) & 3;
13092           modrm.reg = (*codep >> 3) & 7;
13093           modrm.rm = *codep & 7;
13094         }
13095       break;
13096
13097     case USE_VEX_W_TABLE:
13098       if (!need_vex)
13099         abort ();
13100
13101       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
13102       break;
13103
13104     case USE_EVEX_TABLE:
13105       two_source_ops = 0;
13106       /* EVEX prefix.  */
13107       vex.evex = 1;
13108       FETCH_DATA (info, codep + 4);
13109       /* All bits in the REX prefix are ignored.  */
13110       rex_ignored = rex;
13111       /* The first byte after 0x62.  */
13112       rex = ~(*codep >> 5) & 0x7;
13113       vex.r = *codep & 0x10;
13114       switch ((*codep & 0xf))
13115         {
13116         default:
13117           return &bad_opcode;
13118         case 0x1:
13119           vex_table_index = EVEX_0F;
13120           break;
13121         case 0x2:
13122           vex_table_index = EVEX_0F38;
13123           break;
13124         case 0x3:
13125           vex_table_index = EVEX_0F3A;
13126           break;
13127         }
13128
13129       /* The second byte after 0x62.  */
13130       codep++;
13131       vex.w = *codep & 0x80;
13132       if (vex.w && address_mode == mode_64bit)
13133         rex |= REX_W;
13134
13135       vex.register_specifier = (~(*codep >> 3)) & 0xf;
13136       if (address_mode != mode_64bit)
13137         {
13138           /* In 16/32-bit mode silently ignore following bits.  */
13139           rex &= ~REX_B;
13140           vex.r = 1;
13141           vex.v = 1;
13142           vex.register_specifier &= 0x7;
13143         }
13144
13145       /* The U bit.  */
13146       if (!(*codep & 0x4))
13147         return &bad_opcode;
13148
13149       switch ((*codep & 0x3))
13150         {
13151         case 0:
13152           vex.prefix = 0;
13153           break;
13154         case 1:
13155           vex.prefix = DATA_PREFIX_OPCODE;
13156           break;
13157         case 2:
13158           vex.prefix = REPE_PREFIX_OPCODE;
13159           break;
13160         case 3:
13161           vex.prefix = REPNE_PREFIX_OPCODE;
13162           break;
13163         }
13164
13165       /* The third byte after 0x62.  */
13166       codep++;
13167
13168       /* Remember the static rounding bits.  */
13169       vex.ll = (*codep >> 5) & 3;
13170       vex.b = (*codep & 0x10) != 0;
13171
13172       vex.v = *codep & 0x8;
13173       vex.mask_register_specifier = *codep & 0x7;
13174       vex.zeroing = *codep & 0x80;
13175
13176       need_vex = 1;
13177       need_vex_reg = 1;
13178       codep++;
13179       vindex = *codep++;
13180       dp = &evex_table[vex_table_index][vindex];
13181       end_codep = codep;
13182       FETCH_DATA (info, codep + 1);
13183       modrm.mod = (*codep >> 6) & 3;
13184       modrm.reg = (*codep >> 3) & 7;
13185       modrm.rm = *codep & 7;
13186
13187       /* Set vector length.  */
13188       if (modrm.mod == 3 && vex.b)
13189         vex.length = 512;
13190       else
13191         {
13192           switch (vex.ll)
13193             {
13194             case 0x0:
13195               vex.length = 128;
13196               break;
13197             case 0x1:
13198               vex.length = 256;
13199               break;
13200             case 0x2:
13201               vex.length = 512;
13202               break;
13203             default:
13204               return &bad_opcode;
13205             }
13206         }
13207       break;
13208
13209     case 0:
13210       dp = &bad_opcode;
13211       break;
13212
13213     default:
13214       abort ();
13215     }
13216
13217   if (dp->name != NULL)
13218     return dp;
13219   else
13220     return get_valid_dis386 (dp, info);
13221 }
13222
13223 static void
13224 get_sib (disassemble_info *info, int sizeflag)
13225 {
13226   /* If modrm.mod == 3, operand must be register.  */
13227   if (need_modrm
13228       && ((sizeflag & AFLAG) || address_mode == mode_64bit)
13229       && modrm.mod != 3
13230       && modrm.rm == 4)
13231     {
13232       FETCH_DATA (info, codep + 2);
13233       sib.index = (codep [1] >> 3) & 7;
13234       sib.scale = (codep [1] >> 6) & 3;
13235       sib.base = codep [1] & 7;
13236     }
13237 }
13238
13239 static int
13240 print_insn (bfd_vma pc, disassemble_info *info)
13241 {
13242   const struct dis386 *dp;
13243   int i;
13244   char *op_txt[MAX_OPERANDS];
13245   int needcomma;
13246   int sizeflag, orig_sizeflag;
13247   const char *p;
13248   struct dis_private priv;
13249   int prefix_length;
13250
13251   priv.orig_sizeflag = AFLAG | DFLAG;
13252   if ((info->mach & bfd_mach_i386_i386) != 0)
13253     address_mode = mode_32bit;
13254   else if (info->mach == bfd_mach_i386_i8086)
13255     {
13256       address_mode = mode_16bit;
13257       priv.orig_sizeflag = 0;
13258     }
13259   else
13260     address_mode = mode_64bit;
13261
13262   if (intel_syntax == (char) -1)
13263     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
13264
13265   for (p = info->disassembler_options; p != NULL; )
13266     {
13267       if (CONST_STRNEQ (p, "amd64"))
13268         isa64 = amd64;
13269       else if (CONST_STRNEQ (p, "intel64"))
13270         isa64 = intel64;
13271       else if (CONST_STRNEQ (p, "x86-64"))
13272         {
13273           address_mode = mode_64bit;
13274           priv.orig_sizeflag = AFLAG | DFLAG;
13275         }
13276       else if (CONST_STRNEQ (p, "i386"))
13277         {
13278           address_mode = mode_32bit;
13279           priv.orig_sizeflag = AFLAG | DFLAG;
13280         }
13281       else if (CONST_STRNEQ (p, "i8086"))
13282         {
13283           address_mode = mode_16bit;
13284           priv.orig_sizeflag = 0;
13285         }
13286       else if (CONST_STRNEQ (p, "intel"))
13287         {
13288           intel_syntax = 1;
13289           if (CONST_STRNEQ (p + 5, "-mnemonic"))
13290             intel_mnemonic = 1;
13291         }
13292       else if (CONST_STRNEQ (p, "att"))
13293         {
13294           intel_syntax = 0;
13295           if (CONST_STRNEQ (p + 3, "-mnemonic"))
13296             intel_mnemonic = 0;
13297         }
13298       else if (CONST_STRNEQ (p, "addr"))
13299         {
13300           if (address_mode == mode_64bit)
13301             {
13302               if (p[4] == '3' && p[5] == '2')
13303                 priv.orig_sizeflag &= ~AFLAG;
13304               else if (p[4] == '6' && p[5] == '4')
13305                 priv.orig_sizeflag |= AFLAG;
13306             }
13307           else
13308             {
13309               if (p[4] == '1' && p[5] == '6')
13310                 priv.orig_sizeflag &= ~AFLAG;
13311               else if (p[4] == '3' && p[5] == '2')
13312                 priv.orig_sizeflag |= AFLAG;
13313             }
13314         }
13315       else if (CONST_STRNEQ (p, "data"))
13316         {
13317           if (p[4] == '1' && p[5] == '6')
13318             priv.orig_sizeflag &= ~DFLAG;
13319           else if (p[4] == '3' && p[5] == '2')
13320             priv.orig_sizeflag |= DFLAG;
13321         }
13322       else if (CONST_STRNEQ (p, "suffix"))
13323         priv.orig_sizeflag |= SUFFIX_ALWAYS;
13324
13325       p = strchr (p, ',');
13326       if (p != NULL)
13327         p++;
13328     }
13329
13330   if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
13331     {
13332       (*info->fprintf_func) (info->stream,
13333                              _("64-bit address is disabled"));
13334       return -1;
13335     }
13336
13337   if (intel_syntax)
13338     {
13339       names64 = intel_names64;
13340       names32 = intel_names32;
13341       names16 = intel_names16;
13342       names8 = intel_names8;
13343       names8rex = intel_names8rex;
13344       names_seg = intel_names_seg;
13345       names_mm = intel_names_mm;
13346       names_bnd = intel_names_bnd;
13347       names_xmm = intel_names_xmm;
13348       names_ymm = intel_names_ymm;
13349       names_zmm = intel_names_zmm;
13350       index64 = intel_index64;
13351       index32 = intel_index32;
13352       names_mask = intel_names_mask;
13353       index16 = intel_index16;
13354       open_char = '[';
13355       close_char = ']';
13356       separator_char = '+';
13357       scale_char = '*';
13358     }
13359   else
13360     {
13361       names64 = att_names64;
13362       names32 = att_names32;
13363       names16 = att_names16;
13364       names8 = att_names8;
13365       names8rex = att_names8rex;
13366       names_seg = att_names_seg;
13367       names_mm = att_names_mm;
13368       names_bnd = att_names_bnd;
13369       names_xmm = att_names_xmm;
13370       names_ymm = att_names_ymm;
13371       names_zmm = att_names_zmm;
13372       index64 = att_index64;
13373       index32 = att_index32;
13374       names_mask = att_names_mask;
13375       index16 = att_index16;
13376       open_char = '(';
13377       close_char =  ')';
13378       separator_char = ',';
13379       scale_char = ',';
13380     }
13381
13382   /* The output looks better if we put 7 bytes on a line, since that
13383      puts most long word instructions on a single line.  Use 8 bytes
13384      for Intel L1OM.  */
13385   if ((info->mach & bfd_mach_l1om) != 0)
13386     info->bytes_per_line = 8;
13387   else
13388     info->bytes_per_line = 7;
13389
13390   info->private_data = &priv;
13391   priv.max_fetched = priv.the_buffer;
13392   priv.insn_start = pc;
13393
13394   obuf[0] = 0;
13395   for (i = 0; i < MAX_OPERANDS; ++i)
13396     {
13397       op_out[i][0] = 0;
13398       op_index[i] = -1;
13399     }
13400
13401   the_info = info;
13402   start_pc = pc;
13403   start_codep = priv.the_buffer;
13404   codep = priv.the_buffer;
13405
13406   if (OPCODES_SIGSETJMP (priv.bailout) != 0)
13407     {
13408       const char *name;
13409
13410       /* Getting here means we tried for data but didn't get it.  That
13411          means we have an incomplete instruction of some sort.  Just
13412          print the first byte as a prefix or a .byte pseudo-op.  */
13413       if (codep > priv.the_buffer)
13414         {
13415           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
13416           if (name != NULL)
13417             (*info->fprintf_func) (info->stream, "%s", name);
13418           else
13419             {
13420               /* Just print the first byte as a .byte instruction.  */
13421               (*info->fprintf_func) (info->stream, ".byte 0x%x",
13422                                      (unsigned int) priv.the_buffer[0]);
13423             }
13424
13425           return 1;
13426         }
13427
13428       return -1;
13429     }
13430
13431   obufp = obuf;
13432   sizeflag = priv.orig_sizeflag;
13433
13434   if (!ckprefix () || rex_used)
13435     {
13436       /* Too many prefixes or unused REX prefixes.  */
13437       for (i = 0;
13438            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
13439            i++)
13440         (*info->fprintf_func) (info->stream, "%s%s",
13441                                i == 0 ? "" : " ",
13442                                prefix_name (all_prefixes[i], sizeflag));
13443       return i;
13444     }
13445
13446   insn_codep = codep;
13447
13448   FETCH_DATA (info, codep + 1);
13449   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
13450
13451   if (((prefixes & PREFIX_FWAIT)
13452        && ((*codep < 0xd8) || (*codep > 0xdf))))
13453     {
13454       /* Handle prefixes before fwait.  */
13455       for (i = 0; i < fwait_prefix && all_prefixes[i];
13456            i++)
13457         (*info->fprintf_func) (info->stream, "%s ",
13458                                prefix_name (all_prefixes[i], sizeflag));
13459       (*info->fprintf_func) (info->stream, "fwait");
13460       return i + 1;
13461     }
13462
13463   if (*codep == 0x0f)
13464     {
13465       unsigned char threebyte;
13466
13467       codep++;
13468       FETCH_DATA (info, codep + 1);
13469       threebyte = *codep;
13470       dp = &dis386_twobyte[threebyte];
13471       need_modrm = twobyte_has_modrm[*codep];
13472       codep++;
13473     }
13474   else
13475     {
13476       dp = &dis386[*codep];
13477       need_modrm = onebyte_has_modrm[*codep];
13478       codep++;
13479     }
13480
13481   /* Save sizeflag for printing the extra prefixes later before updating
13482      it for mnemonic and operand processing.  The prefix names depend
13483      only on the address mode.  */
13484   orig_sizeflag = sizeflag;
13485   if (prefixes & PREFIX_ADDR)
13486     sizeflag ^= AFLAG;
13487   if ((prefixes & PREFIX_DATA))
13488     sizeflag ^= DFLAG;
13489
13490   end_codep = codep;
13491   if (need_modrm)
13492     {
13493       FETCH_DATA (info, codep + 1);
13494       modrm.mod = (*codep >> 6) & 3;
13495       modrm.reg = (*codep >> 3) & 7;
13496       modrm.rm = *codep & 7;
13497     }
13498
13499   need_vex = 0;
13500   need_vex_reg = 0;
13501   vex_w_done = 0;
13502   vex.evex = 0;
13503
13504   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
13505     {
13506       get_sib (info, sizeflag);
13507       dofloat (sizeflag);
13508     }
13509   else
13510     {
13511       dp = get_valid_dis386 (dp, info);
13512       if (dp != NULL && putop (dp->name, sizeflag) == 0)
13513         {
13514           get_sib (info, sizeflag);
13515           for (i = 0; i < MAX_OPERANDS; ++i)
13516             {
13517               obufp = op_out[i];
13518               op_ad = MAX_OPERANDS - 1 - i;
13519               if (dp->op[i].rtn)
13520                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
13521               /* For EVEX instruction after the last operand masking
13522                  should be printed.  */
13523               if (i == 0 && vex.evex)
13524                 {
13525                   /* Don't print {%k0}.  */
13526                   if (vex.mask_register_specifier)
13527                     {
13528                       oappend ("{");
13529                       oappend (names_mask[vex.mask_register_specifier]);
13530                       oappend ("}");
13531                     }
13532                   if (vex.zeroing)
13533                     oappend ("{z}");
13534                 }
13535             }
13536         }
13537     }
13538
13539   /* Check if the REX prefix is used.  */
13540   if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)
13541     all_prefixes[last_rex_prefix] = 0;
13542
13543   /* Check if the SEG prefix is used.  */
13544   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
13545                    | PREFIX_FS | PREFIX_GS)) != 0
13546       && (used_prefixes & active_seg_prefix) != 0)
13547     all_prefixes[last_seg_prefix] = 0;
13548
13549   /* Check if the ADDR prefix is used.  */
13550   if ((prefixes & PREFIX_ADDR) != 0
13551       && (used_prefixes & PREFIX_ADDR) != 0)
13552     all_prefixes[last_addr_prefix] = 0;
13553
13554   /* Check if the DATA prefix is used.  */
13555   if ((prefixes & PREFIX_DATA) != 0
13556       && (used_prefixes & PREFIX_DATA) != 0)
13557     all_prefixes[last_data_prefix] = 0;
13558
13559   /* Print the extra prefixes.  */
13560   prefix_length = 0;
13561   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
13562     if (all_prefixes[i])
13563       {
13564         const char *name;
13565         name = prefix_name (all_prefixes[i], orig_sizeflag);
13566         if (name == NULL)
13567           abort ();
13568         prefix_length += strlen (name) + 1;
13569         (*info->fprintf_func) (info->stream, "%s ", name);
13570       }
13571
13572   /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
13573      unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
13574      used by putop and MMX/SSE operand and may be overriden by the
13575      PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
13576      separately.  */
13577   if (dp->prefix_requirement == PREFIX_OPCODE
13578       && dp != &bad_opcode
13579       && (((prefixes
13580             & (PREFIX_REPZ | PREFIX_REPNZ)) != 0
13581            && (used_prefixes
13582                & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
13583           || ((((prefixes
13584                  & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
13585                 == PREFIX_DATA)
13586                && (used_prefixes & PREFIX_DATA) == 0))))
13587     {
13588       (*info->fprintf_func) (info->stream, "(bad)");
13589       return end_codep - priv.the_buffer;
13590     }
13591
13592   /* Check maximum code length.  */
13593   if ((codep - start_codep) > MAX_CODE_LENGTH)
13594     {
13595       (*info->fprintf_func) (info->stream, "(bad)");
13596       return MAX_CODE_LENGTH;
13597     }
13598
13599   obufp = mnemonicendp;
13600   for (i = strlen (obuf) + prefix_length; i < 6; i++)
13601     oappend (" ");
13602   oappend (" ");
13603   (*info->fprintf_func) (info->stream, "%s", obuf);
13604
13605   /* The enter and bound instructions are printed with operands in the same
13606      order as the intel book; everything else is printed in reverse order.  */
13607   if (intel_syntax || two_source_ops)
13608     {
13609       bfd_vma riprel;
13610
13611       for (i = 0; i < MAX_OPERANDS; ++i)
13612         op_txt[i] = op_out[i];
13613
13614       if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
13615           && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
13616         {
13617           op_txt[2] = op_out[3];
13618           op_txt[3] = op_out[2];
13619         }
13620
13621       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
13622         {
13623           op_ad = op_index[i];
13624           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
13625           op_index[MAX_OPERANDS - 1 - i] = op_ad;
13626           riprel = op_riprel[i];
13627           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
13628           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
13629         }
13630     }
13631   else
13632     {
13633       for (i = 0; i < MAX_OPERANDS; ++i)
13634         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
13635     }
13636
13637   needcomma = 0;
13638   for (i = 0; i < MAX_OPERANDS; ++i)
13639     if (*op_txt[i])
13640       {
13641         if (needcomma)
13642           (*info->fprintf_func) (info->stream, ",");
13643         if (op_index[i] != -1 && !op_riprel[i])
13644           (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
13645         else
13646           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
13647         needcomma = 1;
13648       }
13649
13650   for (i = 0; i < MAX_OPERANDS; i++)
13651     if (op_index[i] != -1 && op_riprel[i])
13652       {
13653         (*info->fprintf_func) (info->stream, "        # ");
13654         (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
13655                                                 + op_address[op_index[i]]), info);
13656         break;
13657       }
13658   return codep - priv.the_buffer;
13659 }
13660
13661 static const char *float_mem[] = {
13662   /* d8 */
13663   "fadd{s|}",
13664   "fmul{s|}",
13665   "fcom{s|}",
13666   "fcomp{s|}",
13667   "fsub{s|}",
13668   "fsubr{s|}",
13669   "fdiv{s|}",
13670   "fdivr{s|}",
13671   /* d9 */
13672   "fld{s|}",
13673   "(bad)",
13674   "fst{s|}",
13675   "fstp{s|}",
13676   "fldenvIC",
13677   "fldcw",
13678   "fNstenvIC",
13679   "fNstcw",
13680   /* da */
13681   "fiadd{l|}",
13682   "fimul{l|}",
13683   "ficom{l|}",
13684   "ficomp{l|}",
13685   "fisub{l|}",
13686   "fisubr{l|}",
13687   "fidiv{l|}",
13688   "fidivr{l|}",
13689   /* db */
13690   "fild{l|}",
13691   "fisttp{l|}",
13692   "fist{l|}",
13693   "fistp{l|}",
13694   "(bad)",
13695   "fld{t||t|}",
13696   "(bad)",
13697   "fstp{t||t|}",
13698   /* dc */
13699   "fadd{l|}",
13700   "fmul{l|}",
13701   "fcom{l|}",
13702   "fcomp{l|}",
13703   "fsub{l|}",
13704   "fsubr{l|}",
13705   "fdiv{l|}",
13706   "fdivr{l|}",
13707   /* dd */
13708   "fld{l|}",
13709   "fisttp{ll|}",
13710   "fst{l||}",
13711   "fstp{l|}",
13712   "frstorIC",
13713   "(bad)",
13714   "fNsaveIC",
13715   "fNstsw",
13716   /* de */
13717   "fiadd",
13718   "fimul",
13719   "ficom",
13720   "ficomp",
13721   "fisub",
13722   "fisubr",
13723   "fidiv",
13724   "fidivr",
13725   /* df */
13726   "fild",
13727   "fisttp",
13728   "fist",
13729   "fistp",
13730   "fbld",
13731   "fild{ll|}",
13732   "fbstp",
13733   "fistp{ll|}",
13734 };
13735
13736 static const unsigned char float_mem_mode[] = {
13737   /* d8 */
13738   d_mode,
13739   d_mode,
13740   d_mode,
13741   d_mode,
13742   d_mode,
13743   d_mode,
13744   d_mode,
13745   d_mode,
13746   /* d9 */
13747   d_mode,
13748   0,
13749   d_mode,
13750   d_mode,
13751   0,
13752   w_mode,
13753   0,
13754   w_mode,
13755   /* da */
13756   d_mode,
13757   d_mode,
13758   d_mode,
13759   d_mode,
13760   d_mode,
13761   d_mode,
13762   d_mode,
13763   d_mode,
13764   /* db */
13765   d_mode,
13766   d_mode,
13767   d_mode,
13768   d_mode,
13769   0,
13770   t_mode,
13771   0,
13772   t_mode,
13773   /* dc */
13774   q_mode,
13775   q_mode,
13776   q_mode,
13777   q_mode,
13778   q_mode,
13779   q_mode,
13780   q_mode,
13781   q_mode,
13782   /* dd */
13783   q_mode,
13784   q_mode,
13785   q_mode,
13786   q_mode,
13787   0,
13788   0,
13789   0,
13790   w_mode,
13791   /* de */
13792   w_mode,
13793   w_mode,
13794   w_mode,
13795   w_mode,
13796   w_mode,
13797   w_mode,
13798   w_mode,
13799   w_mode,
13800   /* df */
13801   w_mode,
13802   w_mode,
13803   w_mode,
13804   w_mode,
13805   t_mode,
13806   q_mode,
13807   t_mode,
13808   q_mode
13809 };
13810
13811 #define ST { OP_ST, 0 }
13812 #define STi { OP_STi, 0 }
13813
13814 #define FGRPd9_2 NULL, { { NULL, 0 } }, 0
13815 #define FGRPd9_4 NULL, { { NULL, 1 } }, 0
13816 #define FGRPd9_5 NULL, { { NULL, 2 } }, 0
13817 #define FGRPd9_6 NULL, { { NULL, 3 } }, 0
13818 #define FGRPd9_7 NULL, { { NULL, 4 } }, 0
13819 #define FGRPda_5 NULL, { { NULL, 5 } }, 0
13820 #define FGRPdb_4 NULL, { { NULL, 6 } }, 0
13821 #define FGRPde_3 NULL, { { NULL, 7 } }, 0
13822 #define FGRPdf_4 NULL, { { NULL, 8 } }, 0
13823
13824 static const struct dis386 float_reg[][8] = {
13825   /* d8 */
13826   {
13827     { "fadd",   { ST, STi }, 0 },
13828     { "fmul",   { ST, STi }, 0 },
13829     { "fcom",   { STi }, 0 },
13830     { "fcomp",  { STi }, 0 },
13831     { "fsub",   { ST, STi }, 0 },
13832     { "fsubr",  { ST, STi }, 0 },
13833     { "fdiv",   { ST, STi }, 0 },
13834     { "fdivr",  { ST, STi }, 0 },
13835   },
13836   /* d9 */
13837   {
13838     { "fld",    { STi }, 0 },
13839     { "fxch",   { STi }, 0 },
13840     { FGRPd9_2 },
13841     { Bad_Opcode },
13842     { FGRPd9_4 },
13843     { FGRPd9_5 },
13844     { FGRPd9_6 },
13845     { FGRPd9_7 },
13846   },
13847   /* da */
13848   {
13849     { "fcmovb", { ST, STi }, 0 },
13850     { "fcmove", { ST, STi }, 0 },
13851     { "fcmovbe",{ ST, STi }, 0 },
13852     { "fcmovu", { ST, STi }, 0 },
13853     { Bad_Opcode },
13854     { FGRPda_5 },
13855     { Bad_Opcode },
13856     { Bad_Opcode },
13857   },
13858   /* db */
13859   {
13860     { "fcmovnb",{ ST, STi }, 0 },
13861     { "fcmovne",{ ST, STi }, 0 },
13862     { "fcmovnbe",{ ST, STi }, 0 },
13863     { "fcmovnu",{ ST, STi }, 0 },
13864     { FGRPdb_4 },
13865     { "fucomi", { ST, STi }, 0 },
13866     { "fcomi",  { ST, STi }, 0 },
13867     { Bad_Opcode },
13868   },
13869   /* dc */
13870   {
13871     { "fadd",   { STi, ST }, 0 },
13872     { "fmul",   { STi, ST }, 0 },
13873     { Bad_Opcode },
13874     { Bad_Opcode },
13875     { "fsub!M", { STi, ST }, 0 },
13876     { "fsubM",  { STi, ST }, 0 },
13877     { "fdiv!M", { STi, ST }, 0 },
13878     { "fdivM",  { STi, ST }, 0 },
13879   },
13880   /* dd */
13881   {
13882     { "ffree",  { STi }, 0 },
13883     { Bad_Opcode },
13884     { "fst",    { STi }, 0 },
13885     { "fstp",   { STi }, 0 },
13886     { "fucom",  { STi }, 0 },
13887     { "fucomp", { STi }, 0 },
13888     { Bad_Opcode },
13889     { Bad_Opcode },
13890   },
13891   /* de */
13892   {
13893     { "faddp",  { STi, ST }, 0 },
13894     { "fmulp",  { STi, ST }, 0 },
13895     { Bad_Opcode },
13896     { FGRPde_3 },
13897     { "fsub!Mp", { STi, ST }, 0 },
13898     { "fsubMp", { STi, ST }, 0 },
13899     { "fdiv!Mp", { STi, ST }, 0 },
13900     { "fdivMp", { STi, ST }, 0 },
13901   },
13902   /* df */
13903   {
13904     { "ffreep", { STi }, 0 },
13905     { Bad_Opcode },
13906     { Bad_Opcode },
13907     { Bad_Opcode },
13908     { FGRPdf_4 },
13909     { "fucomip", { ST, STi }, 0 },
13910     { "fcomip", { ST, STi }, 0 },
13911     { Bad_Opcode },
13912   },
13913 };
13914
13915 static char *fgrps[][8] = {
13916   /* d9_2  0 */
13917   {
13918     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13919   },
13920
13921   /* d9_4  1 */
13922   {
13923     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
13924   },
13925
13926   /* d9_5  2 */
13927   {
13928     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
13929   },
13930
13931   /* d9_6  3 */
13932   {
13933     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
13934   },
13935
13936   /* d9_7  4 */
13937   {
13938     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
13939   },
13940
13941   /* da_5  5 */
13942   {
13943     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13944   },
13945
13946   /* db_4  6 */
13947   {
13948     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
13949     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
13950   },
13951
13952   /* de_3  7 */
13953   {
13954     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13955   },
13956
13957   /* df_4  8 */
13958   {
13959     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13960   },
13961 };
13962
13963 static void
13964 swap_operand (void)
13965 {
13966   mnemonicendp[0] = '.';
13967   mnemonicendp[1] = 's';
13968   mnemonicendp += 2;
13969 }
13970
13971 static void
13972 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
13973                int sizeflag ATTRIBUTE_UNUSED)
13974 {
13975   /* Skip mod/rm byte.  */
13976   MODRM_CHECK;
13977   codep++;
13978 }
13979
13980 static void
13981 dofloat (int sizeflag)
13982 {
13983   const struct dis386 *dp;
13984   unsigned char floatop;
13985
13986   floatop = codep[-1];
13987
13988   if (modrm.mod != 3)
13989     {
13990       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
13991
13992       putop (float_mem[fp_indx], sizeflag);
13993       obufp = op_out[0];
13994       op_ad = 2;
13995       OP_E (float_mem_mode[fp_indx], sizeflag);
13996       return;
13997     }
13998   /* Skip mod/rm byte.  */
13999   MODRM_CHECK;
14000   codep++;
14001
14002   dp = &float_reg[floatop - 0xd8][modrm.reg];
14003   if (dp->name == NULL)
14004     {
14005       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
14006
14007       /* Instruction fnstsw is only one with strange arg.  */
14008       if (floatop == 0xdf && codep[-1] == 0xe0)
14009         strcpy (op_out[0], names16[0]);
14010     }
14011   else
14012     {
14013       putop (dp->name, sizeflag);
14014
14015       obufp = op_out[0];
14016       op_ad = 2;
14017       if (dp->op[0].rtn)
14018         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
14019
14020       obufp = op_out[1];
14021       op_ad = 1;
14022       if (dp->op[1].rtn)
14023         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
14024     }
14025 }
14026
14027 /* Like oappend (below), but S is a string starting with '%'.
14028    In Intel syntax, the '%' is elided.  */
14029 static void
14030 oappend_maybe_intel (const char *s)
14031 {
14032   oappend (s + intel_syntax);
14033 }
14034
14035 static void
14036 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14037 {
14038   oappend_maybe_intel ("%st");
14039 }
14040
14041 static void
14042 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14043 {
14044   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
14045   oappend_maybe_intel (scratchbuf);
14046 }
14047
14048 /* Capital letters in template are macros.  */
14049 static int
14050 putop (const char *in_template, int sizeflag)
14051 {
14052   const char *p;
14053   int alt = 0;
14054   int cond = 1;
14055   unsigned int l = 0, len = 1;
14056   char last[4];
14057
14058 #define SAVE_LAST(c)                    \
14059   if (l < len && l < sizeof (last))     \
14060     last[l++] = c;                      \
14061   else                                  \
14062     abort ();
14063
14064   for (p = in_template; *p; p++)
14065     {
14066       switch (*p)
14067         {
14068         default:
14069           *obufp++ = *p;
14070           break;
14071         case '%':
14072           len++;
14073           break;
14074         case '!':
14075           cond = 0;
14076           break;
14077         case '{':
14078           alt = 0;
14079           if (intel_syntax)
14080             {
14081               while (*++p != '|')
14082                 if (*p == '}' || *p == '\0')
14083                   abort ();
14084             }
14085           /* Fall through.  */
14086         case 'I':
14087           alt = 1;
14088           continue;
14089         case '|':
14090           while (*++p != '}')
14091             {
14092               if (*p == '\0')
14093                 abort ();
14094             }
14095           break;
14096         case '}':
14097           break;
14098         case 'A':
14099           if (intel_syntax)
14100             break;
14101           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
14102             *obufp++ = 'b';
14103           break;
14104         case 'B':
14105           if (l == 0 && len == 1)
14106             {
14107 case_B:
14108               if (intel_syntax)
14109                 break;
14110               if (sizeflag & SUFFIX_ALWAYS)
14111                 *obufp++ = 'b';
14112             }
14113           else
14114             {
14115               if (l != 1
14116                   || len != 2
14117                   || last[0] != 'L')
14118                 {
14119                   SAVE_LAST (*p);
14120                   break;
14121                 }
14122
14123               if (address_mode == mode_64bit
14124                   && !(prefixes & PREFIX_ADDR))
14125                 {
14126                   *obufp++ = 'a';
14127                   *obufp++ = 'b';
14128                   *obufp++ = 's';
14129                 }
14130
14131               goto case_B;
14132             }
14133           break;
14134         case 'C':
14135           if (intel_syntax && !alt)
14136             break;
14137           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
14138             {
14139               if (sizeflag & DFLAG)
14140                 *obufp++ = intel_syntax ? 'd' : 'l';
14141               else
14142                 *obufp++ = intel_syntax ? 'w' : 's';
14143               used_prefixes |= (prefixes & PREFIX_DATA);
14144             }
14145           break;
14146         case 'D':
14147           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
14148             break;
14149           USED_REX (REX_W);
14150           if (modrm.mod == 3)
14151             {
14152               if (rex & REX_W)
14153                 *obufp++ = 'q';
14154               else
14155                 {
14156                   if (sizeflag & DFLAG)
14157                     *obufp++ = intel_syntax ? 'd' : 'l';
14158                   else
14159                     *obufp++ = 'w';
14160                   used_prefixes |= (prefixes & PREFIX_DATA);
14161                 }
14162             }
14163           else
14164             *obufp++ = 'w';
14165           break;
14166         case 'E':               /* For jcxz/jecxz */
14167           if (address_mode == mode_64bit)
14168             {
14169               if (sizeflag & AFLAG)
14170                 *obufp++ = 'r';
14171               else
14172                 *obufp++ = 'e';
14173             }
14174           else
14175             if (sizeflag & AFLAG)
14176               *obufp++ = 'e';
14177           used_prefixes |= (prefixes & PREFIX_ADDR);
14178           break;
14179         case 'F':
14180           if (intel_syntax)
14181             break;
14182           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
14183             {
14184               if (sizeflag & AFLAG)
14185                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
14186               else
14187                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
14188               used_prefixes |= (prefixes & PREFIX_ADDR);
14189             }
14190           break;
14191         case 'G':
14192           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
14193             break;
14194           if ((rex & REX_W) || (sizeflag & DFLAG))
14195             *obufp++ = 'l';
14196           else
14197             *obufp++ = 'w';
14198           if (!(rex & REX_W))
14199             used_prefixes |= (prefixes & PREFIX_DATA);
14200           break;
14201         case 'H':
14202           if (intel_syntax)
14203             break;
14204           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
14205               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
14206             {
14207               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
14208               *obufp++ = ',';
14209               *obufp++ = 'p';
14210               if (prefixes & PREFIX_DS)
14211                 *obufp++ = 't';
14212               else
14213                 *obufp++ = 'n';
14214             }
14215           break;
14216         case 'J':
14217           if (intel_syntax)
14218             break;
14219           *obufp++ = 'l';
14220           break;
14221         case 'K':
14222           USED_REX (REX_W);
14223           if (rex & REX_W)
14224             *obufp++ = 'q';
14225           else
14226             *obufp++ = 'd';
14227           break;
14228         case 'Z':
14229           if (l != 0 || len != 1)
14230             {
14231               if (l != 1 || len != 2 || last[0] != 'X')
14232                 {
14233                   SAVE_LAST (*p);
14234                   break;
14235                 }
14236               if (!need_vex || !vex.evex)
14237                 abort ();
14238               if (intel_syntax
14239                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
14240                 break;
14241               switch (vex.length)
14242                 {
14243                 case 128:
14244                   *obufp++ = 'x';
14245                   break;
14246                 case 256:
14247                   *obufp++ = 'y';
14248                   break;
14249                 case 512:
14250                   *obufp++ = 'z';
14251                   break;
14252                 default:
14253                   abort ();
14254                 }
14255               break;
14256             }
14257           if (intel_syntax)
14258             break;
14259           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
14260             {
14261               *obufp++ = 'q';
14262               break;
14263             }
14264           /* Fall through.  */
14265           goto case_L;
14266         case 'L':
14267           if (l != 0 || len != 1)
14268             {
14269               SAVE_LAST (*p);
14270               break;
14271             }
14272 case_L:
14273           if (intel_syntax)
14274             break;
14275           if (sizeflag & SUFFIX_ALWAYS)
14276             *obufp++ = 'l';
14277           break;
14278         case 'M':
14279           if (intel_mnemonic != cond)
14280             *obufp++ = 'r';
14281           break;
14282         case 'N':
14283           if ((prefixes & PREFIX_FWAIT) == 0)
14284             *obufp++ = 'n';
14285           else
14286             used_prefixes |= PREFIX_FWAIT;
14287           break;
14288         case 'O':
14289           USED_REX (REX_W);
14290           if (rex & REX_W)
14291             *obufp++ = 'o';
14292           else if (intel_syntax && (sizeflag & DFLAG))
14293             *obufp++ = 'q';
14294           else
14295             *obufp++ = 'd';
14296           if (!(rex & REX_W))
14297             used_prefixes |= (prefixes & PREFIX_DATA);
14298           break;
14299         case 'T':
14300           if (!intel_syntax
14301               && address_mode == mode_64bit
14302               && ((sizeflag & DFLAG) || (rex & REX_W)))
14303             {
14304               *obufp++ = 'q';
14305               break;
14306             }
14307           /* Fall through.  */
14308           goto case_P;
14309         case 'P':
14310           if (l == 0 && len == 1)
14311             {
14312 case_P:
14313               if (intel_syntax)
14314                 {
14315                   if ((rex & REX_W) == 0
14316                       && (prefixes & PREFIX_DATA))
14317                     {
14318                       if ((sizeflag & DFLAG) == 0)
14319                         *obufp++ = 'w';
14320                       used_prefixes |= (prefixes & PREFIX_DATA);
14321                     }
14322                   break;
14323                 }
14324               if ((prefixes & PREFIX_DATA)
14325                   || (rex & REX_W)
14326                   || (sizeflag & SUFFIX_ALWAYS))
14327                 {
14328                   USED_REX (REX_W);
14329                   if (rex & REX_W)
14330                     *obufp++ = 'q';
14331                   else
14332                     {
14333                       if (sizeflag & DFLAG)
14334                         *obufp++ = 'l';
14335                       else
14336                         *obufp++ = 'w';
14337                       used_prefixes |= (prefixes & PREFIX_DATA);
14338                     }
14339                 }
14340             }
14341           else
14342             {
14343               if (l != 1 || len != 2 || last[0] != 'L')
14344                 {
14345                   SAVE_LAST (*p);
14346                   break;
14347                 }
14348
14349               if ((prefixes & PREFIX_DATA)
14350                   || (rex & REX_W)
14351                   || (sizeflag & SUFFIX_ALWAYS))
14352                 {
14353                   USED_REX (REX_W);
14354                   if (rex & REX_W)
14355                     *obufp++ = 'q';
14356                   else
14357                     {
14358                       if (sizeflag & DFLAG)
14359                         *obufp++ = intel_syntax ? 'd' : 'l';
14360                       else
14361                         *obufp++ = 'w';
14362                       used_prefixes |= (prefixes & PREFIX_DATA);
14363                     }
14364                 }
14365             }
14366           break;
14367         case 'U':
14368           if (intel_syntax)
14369             break;
14370           if (address_mode == mode_64bit
14371               && ((sizeflag & DFLAG) || (rex & REX_W)))
14372             {
14373               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
14374                 *obufp++ = 'q';
14375               break;
14376             }
14377           /* Fall through.  */
14378           goto case_Q;
14379         case 'Q':
14380           if (l == 0 && len == 1)
14381             {
14382 case_Q:
14383               if (intel_syntax && !alt)
14384                 break;
14385               USED_REX (REX_W);
14386               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
14387                 {
14388                   if (rex & REX_W)
14389                     *obufp++ = 'q';
14390                   else
14391                     {
14392                       if (sizeflag & DFLAG)
14393                         *obufp++ = intel_syntax ? 'd' : 'l';
14394                       else
14395                         *obufp++ = 'w';
14396                       used_prefixes |= (prefixes & PREFIX_DATA);
14397                     }
14398                 }
14399             }
14400           else
14401             {
14402               if (l != 1 || len != 2 || last[0] != 'L')
14403                 {
14404                   SAVE_LAST (*p);
14405                   break;
14406                 }
14407               if (intel_syntax
14408                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
14409                 break;
14410               if ((rex & REX_W))
14411                 {
14412                   USED_REX (REX_W);
14413                   *obufp++ = 'q';
14414                 }
14415               else
14416                 *obufp++ = 'l';
14417             }
14418           break;
14419         case 'R':
14420           USED_REX (REX_W);
14421           if (rex & REX_W)
14422             *obufp++ = 'q';
14423           else if (sizeflag & DFLAG)
14424             {
14425               if (intel_syntax)
14426                   *obufp++ = 'd';
14427               else
14428                   *obufp++ = 'l';
14429             }
14430           else
14431             *obufp++ = 'w';
14432           if (intel_syntax && !p[1]
14433               && ((rex & REX_W) || (sizeflag & DFLAG)))
14434             *obufp++ = 'e';
14435           if (!(rex & REX_W))
14436             used_prefixes |= (prefixes & PREFIX_DATA);
14437           break;
14438         case 'V':
14439           if (l == 0 && len == 1)
14440             {
14441               if (intel_syntax)
14442                 break;
14443               if (address_mode == mode_64bit
14444                   && ((sizeflag & DFLAG) || (rex & REX_W)))
14445                 {
14446                   if (sizeflag & SUFFIX_ALWAYS)
14447                     *obufp++ = 'q';
14448                   break;
14449                 }
14450             }
14451           else
14452             {
14453               if (l != 1
14454                   || len != 2
14455                   || last[0] != 'L')
14456                 {
14457                   SAVE_LAST (*p);
14458                   break;
14459                 }
14460
14461               if (rex & REX_W)
14462                 {
14463                   *obufp++ = 'a';
14464                   *obufp++ = 'b';
14465                   *obufp++ = 's';
14466                 }
14467             }
14468           /* Fall through.  */
14469           goto case_S;
14470         case 'S':
14471           if (l == 0 && len == 1)
14472             {
14473 case_S:
14474               if (intel_syntax)
14475                 break;
14476               if (sizeflag & SUFFIX_ALWAYS)
14477                 {
14478                   if (rex & REX_W)
14479                     *obufp++ = 'q';
14480                   else
14481                     {
14482                       if (sizeflag & DFLAG)
14483                         *obufp++ = 'l';
14484                       else
14485                         *obufp++ = 'w';
14486                       used_prefixes |= (prefixes & PREFIX_DATA);
14487                     }
14488                 }
14489             }
14490           else
14491             {
14492               if (l != 1
14493                   || len != 2
14494                   || last[0] != 'L')
14495                 {
14496                   SAVE_LAST (*p);
14497                   break;
14498                 }
14499
14500               if (address_mode == mode_64bit
14501                   && !(prefixes & PREFIX_ADDR))
14502                 {
14503                   *obufp++ = 'a';
14504                   *obufp++ = 'b';
14505                   *obufp++ = 's';
14506                 }
14507
14508               goto case_S;
14509             }
14510           break;
14511         case 'X':
14512           if (l != 0 || len != 1)
14513             {
14514               SAVE_LAST (*p);
14515               break;
14516             }
14517           if (need_vex && vex.prefix)
14518             {
14519               if (vex.prefix == DATA_PREFIX_OPCODE)
14520                 *obufp++ = 'd';
14521               else
14522                 *obufp++ = 's';
14523             }
14524           else
14525             {
14526               if (prefixes & PREFIX_DATA)
14527                 *obufp++ = 'd';
14528               else
14529                 *obufp++ = 's';
14530               used_prefixes |= (prefixes & PREFIX_DATA);
14531             }
14532           break;
14533         case 'Y':
14534           if (l == 0 && len == 1)
14535             {
14536               if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
14537                 break;
14538               if (rex & REX_W)
14539                 {
14540                   USED_REX (REX_W);
14541                   *obufp++ = 'q';
14542                 }
14543               break;
14544             }
14545           else
14546             {
14547               if (l != 1 || len != 2 || last[0] != 'X')
14548                 {
14549                   SAVE_LAST (*p);
14550                   break;
14551                 }
14552               if (!need_vex)
14553                 abort ();
14554               if (intel_syntax
14555                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
14556                 break;
14557               switch (vex.length)
14558                 {
14559                 case 128:
14560                   *obufp++ = 'x';
14561                   break;
14562                 case 256:
14563                   *obufp++ = 'y';
14564                   break;
14565                 case 512:
14566                   if (!vex.evex)
14567                 default:
14568                     abort ();
14569                 }
14570             }
14571           break;
14572         case 'W':
14573           if (l == 0 && len == 1)
14574             {
14575               /* operand size flag for cwtl, cbtw */
14576               USED_REX (REX_W);
14577               if (rex & REX_W)
14578                 {
14579                   if (intel_syntax)
14580                     *obufp++ = 'd';
14581                   else
14582                     *obufp++ = 'l';
14583                 }
14584               else if (sizeflag & DFLAG)
14585                 *obufp++ = 'w';
14586               else
14587                 *obufp++ = 'b';
14588               if (!(rex & REX_W))
14589                 used_prefixes |= (prefixes & PREFIX_DATA);
14590             }
14591           else
14592             {
14593               if (l != 1
14594                   || len != 2
14595                   || (last[0] != 'X'
14596                       && last[0] != 'L'))
14597                 {
14598                   SAVE_LAST (*p);
14599                   break;
14600                 }
14601               if (!need_vex)
14602                 abort ();
14603               if (last[0] == 'X')
14604                 *obufp++ = vex.w ? 'd': 's';
14605               else
14606                 *obufp++ = vex.w ? 'q': 'd';
14607             }
14608           break;
14609         case '^':
14610           if (intel_syntax)
14611             break;
14612           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
14613             {
14614               if (sizeflag & DFLAG)
14615                 *obufp++ = 'l';
14616               else
14617                 *obufp++ = 'w';
14618               used_prefixes |= (prefixes & PREFIX_DATA);
14619             }
14620           break;
14621         case '@':
14622           if (intel_syntax)
14623             break;
14624           if (address_mode == mode_64bit
14625               && (isa64 == intel64
14626                   || ((sizeflag & DFLAG) || (rex & REX_W))))
14627               *obufp++ = 'q';
14628           else if ((prefixes & PREFIX_DATA))
14629             {
14630               if (!(sizeflag & DFLAG))
14631                 *obufp++ = 'w';
14632               used_prefixes |= (prefixes & PREFIX_DATA);
14633             }
14634           break;
14635         }
14636       alt = 0;
14637     }
14638   *obufp = 0;
14639   mnemonicendp = obufp;
14640   return 0;
14641 }
14642
14643 static void
14644 oappend (const char *s)
14645 {
14646   obufp = stpcpy (obufp, s);
14647 }
14648
14649 static void
14650 append_seg (void)
14651 {
14652   /* Only print the active segment register.  */
14653   if (!active_seg_prefix)
14654     return;
14655
14656   used_prefixes |= active_seg_prefix;
14657   switch (active_seg_prefix)
14658     {
14659     case PREFIX_CS:
14660       oappend_maybe_intel ("%cs:");
14661       break;
14662     case PREFIX_DS:
14663       oappend_maybe_intel ("%ds:");
14664       break;
14665     case PREFIX_SS:
14666       oappend_maybe_intel ("%ss:");
14667       break;
14668     case PREFIX_ES:
14669       oappend_maybe_intel ("%es:");
14670       break;
14671     case PREFIX_FS:
14672       oappend_maybe_intel ("%fs:");
14673       break;
14674     case PREFIX_GS:
14675       oappend_maybe_intel ("%gs:");
14676       break;
14677     default:
14678       break;
14679     }
14680 }
14681
14682 static void
14683 OP_indirE (int bytemode, int sizeflag)
14684 {
14685   if (!intel_syntax)
14686     oappend ("*");
14687   OP_E (bytemode, sizeflag);
14688 }
14689
14690 static void
14691 print_operand_value (char *buf, int hex, bfd_vma disp)
14692 {
14693   if (address_mode == mode_64bit)
14694     {
14695       if (hex)
14696         {
14697           char tmp[30];
14698           int i;
14699           buf[0] = '0';
14700           buf[1] = 'x';
14701           sprintf_vma (tmp, disp);
14702           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
14703           strcpy (buf + 2, tmp + i);
14704         }
14705       else
14706         {
14707           bfd_signed_vma v = disp;
14708           char tmp[30];
14709           int i;
14710           if (v < 0)
14711             {
14712               *(buf++) = '-';
14713               v = -disp;
14714               /* Check for possible overflow on 0x8000000000000000.  */
14715               if (v < 0)
14716                 {
14717                   strcpy (buf, "9223372036854775808");
14718                   return;
14719                 }
14720             }
14721           if (!v)
14722             {
14723               strcpy (buf, "0");
14724               return;
14725             }
14726
14727           i = 0;
14728           tmp[29] = 0;
14729           while (v)
14730             {
14731               tmp[28 - i] = (v % 10) + '0';
14732               v /= 10;
14733               i++;
14734             }
14735           strcpy (buf, tmp + 29 - i);
14736         }
14737     }
14738   else
14739     {
14740       if (hex)
14741         sprintf (buf, "0x%x", (unsigned int) disp);
14742       else
14743         sprintf (buf, "%d", (int) disp);
14744     }
14745 }
14746
14747 /* Put DISP in BUF as signed hex number.  */
14748
14749 static void
14750 print_displacement (char *buf, bfd_vma disp)
14751 {
14752   bfd_signed_vma val = disp;
14753   char tmp[30];
14754   int i, j = 0;
14755
14756   if (val < 0)
14757     {
14758       buf[j++] = '-';
14759       val = -disp;
14760
14761       /* Check for possible overflow.  */
14762       if (val < 0)
14763         {
14764           switch (address_mode)
14765             {
14766             case mode_64bit:
14767               strcpy (buf + j, "0x8000000000000000");
14768               break;
14769             case mode_32bit:
14770               strcpy (buf + j, "0x80000000");
14771               break;
14772             case mode_16bit:
14773               strcpy (buf + j, "0x8000");
14774               break;
14775             }
14776           return;
14777         }
14778     }
14779
14780   buf[j++] = '0';
14781   buf[j++] = 'x';
14782
14783   sprintf_vma (tmp, (bfd_vma) val);
14784   for (i = 0; tmp[i] == '0'; i++)
14785     continue;
14786   if (tmp[i] == '\0')
14787     i--;
14788   strcpy (buf + j, tmp + i);
14789 }
14790
14791 static void
14792 intel_operand_size (int bytemode, int sizeflag)
14793 {
14794   if (vex.evex
14795       && vex.b
14796       && (bytemode == x_mode
14797           || bytemode == evex_half_bcst_xmmq_mode))
14798     {
14799       if (vex.w)
14800         oappend ("QWORD PTR ");
14801       else
14802         oappend ("DWORD PTR ");
14803       return;
14804     }
14805   switch (bytemode)
14806     {
14807     case b_mode:
14808     case b_swap_mode:
14809     case dqb_mode:
14810     case db_mode:
14811       oappend ("BYTE PTR ");
14812       break;
14813     case w_mode:
14814     case dw_mode:
14815     case dqw_mode:
14816     case dqw_swap_mode:
14817       oappend ("WORD PTR ");
14818       break;
14819     case stack_v_mode:
14820       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14821         {
14822           oappend ("QWORD PTR ");
14823           break;
14824         }
14825       /* FALLTHRU */
14826     case v_mode:
14827     case v_swap_mode:
14828     case dq_mode:
14829       USED_REX (REX_W);
14830       if (rex & REX_W)
14831         oappend ("QWORD PTR ");
14832       else
14833         {
14834           if ((sizeflag & DFLAG) || bytemode == dq_mode)
14835             oappend ("DWORD PTR ");
14836           else
14837             oappend ("WORD PTR ");
14838           used_prefixes |= (prefixes & PREFIX_DATA);
14839         }
14840       break;
14841     case z_mode:
14842       if ((rex & REX_W) || (sizeflag & DFLAG))
14843         *obufp++ = 'D';
14844       oappend ("WORD PTR ");
14845       if (!(rex & REX_W))
14846         used_prefixes |= (prefixes & PREFIX_DATA);
14847       break;
14848     case a_mode:
14849       if (sizeflag & DFLAG)
14850         oappend ("QWORD PTR ");
14851       else
14852         oappend ("DWORD PTR ");
14853       used_prefixes |= (prefixes & PREFIX_DATA);
14854       break;
14855     case d_mode:
14856     case d_scalar_mode:
14857     case d_scalar_swap_mode:
14858     case d_swap_mode:
14859     case dqd_mode:
14860       oappend ("DWORD PTR ");
14861       break;
14862     case q_mode:
14863     case q_scalar_mode:
14864     case q_scalar_swap_mode:
14865     case q_swap_mode:
14866       oappend ("QWORD PTR ");
14867       break;
14868     case m_mode:
14869       if (address_mode == mode_64bit)
14870         oappend ("QWORD PTR ");
14871       else
14872         oappend ("DWORD PTR ");
14873       break;
14874     case f_mode:
14875       if (sizeflag & DFLAG)
14876         oappend ("FWORD PTR ");
14877       else
14878         oappend ("DWORD PTR ");
14879       used_prefixes |= (prefixes & PREFIX_DATA);
14880       break;
14881     case t_mode:
14882       oappend ("TBYTE PTR ");
14883       break;
14884     case x_mode:
14885     case x_swap_mode:
14886     case evex_x_gscat_mode:
14887     case evex_x_nobcst_mode:
14888       if (need_vex)
14889         {
14890           switch (vex.length)
14891             {
14892             case 128:
14893               oappend ("XMMWORD PTR ");
14894               break;
14895             case 256:
14896               oappend ("YMMWORD PTR ");
14897               break;
14898             case 512:
14899               oappend ("ZMMWORD PTR ");
14900               break;
14901             default:
14902               abort ();
14903             }
14904         }
14905       else
14906         oappend ("XMMWORD PTR ");
14907       break;
14908     case xmm_mode:
14909       oappend ("XMMWORD PTR ");
14910       break;
14911     case ymm_mode:
14912       oappend ("YMMWORD PTR ");
14913       break;
14914     case xmmq_mode:
14915     case evex_half_bcst_xmmq_mode:
14916       if (!need_vex)
14917         abort ();
14918
14919       switch (vex.length)
14920         {
14921         case 128:
14922           oappend ("QWORD PTR ");
14923           break;
14924         case 256:
14925           oappend ("XMMWORD PTR ");
14926           break;
14927         case 512:
14928           oappend ("YMMWORD PTR ");
14929           break;
14930         default:
14931           abort ();
14932         }
14933       break;
14934     case xmm_mb_mode:
14935       if (!need_vex)
14936         abort ();
14937
14938       switch (vex.length)
14939         {
14940         case 128:
14941         case 256:
14942         case 512:
14943           oappend ("BYTE PTR ");
14944           break;
14945         default:
14946           abort ();
14947         }
14948       break;
14949     case xmm_mw_mode:
14950       if (!need_vex)
14951         abort ();
14952
14953       switch (vex.length)
14954         {
14955         case 128:
14956         case 256:
14957         case 512:
14958           oappend ("WORD PTR ");
14959           break;
14960         default:
14961           abort ();
14962         }
14963       break;
14964     case xmm_md_mode:
14965       if (!need_vex)
14966         abort ();
14967
14968       switch (vex.length)
14969         {
14970         case 128:
14971         case 256:
14972         case 512:
14973           oappend ("DWORD PTR ");
14974           break;
14975         default:
14976           abort ();
14977         }
14978       break;
14979     case xmm_mq_mode:
14980       if (!need_vex)
14981         abort ();
14982
14983       switch (vex.length)
14984         {
14985         case 128:
14986         case 256:
14987         case 512:
14988           oappend ("QWORD PTR ");
14989           break;
14990         default:
14991           abort ();
14992         }
14993       break;
14994     case xmmdw_mode:
14995       if (!need_vex)
14996         abort ();
14997
14998       switch (vex.length)
14999         {
15000         case 128:
15001           oappend ("WORD PTR ");
15002           break;
15003         case 256:
15004           oappend ("DWORD PTR ");
15005           break;
15006         case 512:
15007           oappend ("QWORD PTR ");
15008           break;
15009         default:
15010           abort ();
15011         }
15012       break;
15013     case xmmqd_mode:
15014       if (!need_vex)
15015         abort ();
15016
15017       switch (vex.length)
15018         {
15019         case 128:
15020           oappend ("DWORD PTR ");
15021           break;
15022         case 256:
15023           oappend ("QWORD PTR ");
15024           break;
15025         case 512:
15026           oappend ("XMMWORD PTR ");
15027           break;
15028         default:
15029           abort ();
15030         }
15031       break;
15032     case ymmq_mode:
15033       if (!need_vex)
15034         abort ();
15035
15036       switch (vex.length)
15037         {
15038         case 128:
15039           oappend ("QWORD PTR ");
15040           break;
15041         case 256:
15042           oappend ("YMMWORD PTR ");
15043           break;
15044         case 512:
15045           oappend ("ZMMWORD PTR ");
15046           break;
15047         default:
15048           abort ();
15049         }
15050       break;
15051     case ymmxmm_mode:
15052       if (!need_vex)
15053         abort ();
15054
15055       switch (vex.length)
15056         {
15057         case 128:
15058         case 256:
15059           oappend ("XMMWORD PTR ");
15060           break;
15061         default:
15062           abort ();
15063         }
15064       break;
15065     case o_mode:
15066       oappend ("OWORD PTR ");
15067       break;
15068     case xmm_mdq_mode:
15069     case vex_w_dq_mode:
15070     case vex_scalar_w_dq_mode:
15071       if (!need_vex)
15072         abort ();
15073
15074       if (vex.w)
15075         oappend ("QWORD PTR ");
15076       else
15077         oappend ("DWORD PTR ");
15078       break;
15079     case vex_vsib_d_w_dq_mode:
15080     case vex_vsib_q_w_dq_mode:
15081       if (!need_vex)
15082         abort ();
15083
15084       if (!vex.evex)
15085         {
15086           if (vex.w)
15087             oappend ("QWORD PTR ");
15088           else
15089             oappend ("DWORD PTR ");
15090         }
15091       else
15092         {
15093           switch (vex.length)
15094             {
15095             case 128:
15096               oappend ("XMMWORD PTR ");
15097               break;
15098             case 256:
15099               oappend ("YMMWORD PTR ");
15100               break;
15101             case 512:
15102               oappend ("ZMMWORD PTR ");
15103               break;
15104             default:
15105               abort ();
15106             }
15107         }
15108       break;
15109     case vex_vsib_q_w_d_mode:
15110     case vex_vsib_d_w_d_mode:
15111       if (!need_vex || !vex.evex)
15112         abort ();
15113
15114       switch (vex.length)
15115         {
15116         case 128:
15117           oappend ("QWORD PTR ");
15118           break;
15119         case 256:
15120           oappend ("XMMWORD PTR ");
15121           break;
15122         case 512:
15123           oappend ("YMMWORD PTR ");
15124           break;
15125         default:
15126           abort ();
15127         }
15128
15129       break;
15130     case mask_bd_mode:
15131       if (!need_vex || vex.length != 128)
15132         abort ();
15133       if (vex.w)
15134         oappend ("DWORD PTR ");
15135       else
15136         oappend ("BYTE PTR ");
15137       break;
15138     case mask_mode:
15139       if (!need_vex)
15140         abort ();
15141       if (vex.w)
15142         oappend ("QWORD PTR ");
15143       else
15144         oappend ("WORD PTR ");
15145       break;
15146     case v_bnd_mode:
15147     default:
15148       break;
15149     }
15150 }
15151
15152 static void
15153 OP_E_register (int bytemode, int sizeflag)
15154 {
15155   int reg = modrm.rm;
15156   const char **names;
15157
15158   USED_REX (REX_B);
15159   if ((rex & REX_B))
15160     reg += 8;
15161
15162   if ((sizeflag & SUFFIX_ALWAYS)
15163       && (bytemode == b_swap_mode
15164           || bytemode == v_swap_mode
15165           || bytemode == dqw_swap_mode))
15166     swap_operand ();
15167
15168   switch (bytemode)
15169     {
15170     case b_mode:
15171     case b_swap_mode:
15172       USED_REX (0);
15173       if (rex)
15174         names = names8rex;
15175       else
15176         names = names8;
15177       break;
15178     case w_mode:
15179       names = names16;
15180       break;
15181     case d_mode:
15182     case dw_mode:
15183     case db_mode:
15184       names = names32;
15185       break;
15186     case q_mode:
15187       names = names64;
15188       break;
15189     case m_mode:
15190     case v_bnd_mode:
15191       names = address_mode == mode_64bit ? names64 : names32;
15192       break;
15193     case bnd_mode:
15194       names = names_bnd;
15195       break;
15196     case stack_v_mode:
15197       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
15198         {
15199           names = names64;
15200           break;
15201         }
15202       bytemode = v_mode;
15203       /* FALLTHRU */
15204     case v_mode:
15205     case v_swap_mode:
15206     case dq_mode:
15207     case dqb_mode:
15208     case dqd_mode:
15209     case dqw_mode:
15210     case dqw_swap_mode:
15211       USED_REX (REX_W);
15212       if (rex & REX_W)
15213         names = names64;
15214       else
15215         {
15216           if ((sizeflag & DFLAG)
15217               || (bytemode != v_mode
15218                   && bytemode != v_swap_mode))
15219             names = names32;
15220           else
15221             names = names16;
15222           used_prefixes |= (prefixes & PREFIX_DATA);
15223         }
15224       break;
15225     case mask_bd_mode:
15226     case mask_mode:
15227       names = names_mask;
15228       break;
15229     case 0:
15230       return;
15231     default:
15232       oappend (INTERNAL_DISASSEMBLER_ERROR);
15233       return;
15234     }
15235   oappend (names[reg]);
15236 }
15237
15238 static void
15239 OP_E_memory (int bytemode, int sizeflag)
15240 {
15241   bfd_vma disp = 0;
15242   int add = (rex & REX_B) ? 8 : 0;
15243   int riprel = 0;
15244   int shift;
15245
15246   if (vex.evex)
15247     {
15248       /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0.  */
15249       if (vex.b
15250           && bytemode != x_mode
15251           && bytemode != xmmq_mode
15252           && bytemode != evex_half_bcst_xmmq_mode)
15253         {
15254           BadOp ();
15255           return;
15256         }
15257       switch (bytemode)
15258         {
15259         case dqw_mode:
15260         case dw_mode:
15261         case dqw_swap_mode:
15262           shift = 1;
15263           break;
15264         case dqb_mode:
15265         case db_mode:
15266           shift = 0;
15267           break;
15268         case vex_vsib_d_w_dq_mode:
15269         case vex_vsib_d_w_d_mode:
15270         case vex_vsib_q_w_dq_mode:
15271         case vex_vsib_q_w_d_mode:
15272         case evex_x_gscat_mode:
15273         case xmm_mdq_mode:
15274           shift = vex.w ? 3 : 2;
15275           break;
15276         case x_mode:
15277         case evex_half_bcst_xmmq_mode:
15278         case xmmq_mode:
15279           if (vex.b)
15280             {
15281               shift = vex.w ? 3 : 2;
15282               break;
15283             }
15284           /* Fall through if vex.b == 0.  */
15285         case xmmqd_mode:
15286         case xmmdw_mode:
15287         case ymmq_mode:
15288         case evex_x_nobcst_mode:
15289         case x_swap_mode:
15290           switch (vex.length)
15291             {
15292             case 128:
15293               shift = 4;
15294               break;
15295             case 256:
15296               shift = 5;
15297               break;
15298             case 512:
15299               shift = 6;
15300               break;
15301             default:
15302               abort ();
15303             }
15304           break;
15305         case ymm_mode:
15306           shift = 5;
15307           break;
15308         case xmm_mode:
15309           shift = 4;
15310           break;
15311         case xmm_mq_mode:
15312         case q_mode:
15313         case q_scalar_mode:
15314         case q_swap_mode:
15315         case q_scalar_swap_mode:
15316           shift = 3;
15317           break;
15318         case dqd_mode:
15319         case xmm_md_mode:
15320         case d_mode:
15321         case d_scalar_mode:
15322         case d_swap_mode:
15323         case d_scalar_swap_mode:
15324           shift = 2;
15325           break;
15326         case xmm_mw_mode:
15327           shift = 1;
15328           break;
15329         case xmm_mb_mode:
15330           shift = 0;
15331           break;
15332         default:
15333           abort ();
15334         }
15335       /* Make necessary corrections to shift for modes that need it.
15336          For these modes we currently have shift 4, 5 or 6 depending on
15337          vex.length (it corresponds to xmmword, ymmword or zmmword
15338          operand).  We might want to make it 3, 4 or 5 (e.g. for
15339          xmmq_mode).  In case of broadcast enabled the corrections
15340          aren't needed, as element size is always 32 or 64 bits.  */
15341       if (!vex.b
15342           && (bytemode == xmmq_mode
15343               || bytemode == evex_half_bcst_xmmq_mode))
15344         shift -= 1;
15345       else if (bytemode == xmmqd_mode)
15346         shift -= 2;
15347       else if (bytemode == xmmdw_mode)
15348         shift -= 3;
15349       else if (bytemode == ymmq_mode && vex.length == 128)
15350         shift -= 1;
15351     }
15352   else
15353     shift = 0;
15354
15355   USED_REX (REX_B);
15356   if (intel_syntax)
15357     intel_operand_size (bytemode, sizeflag);
15358   append_seg ();
15359
15360   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
15361     {
15362       /* 32/64 bit address mode */
15363       int havedisp;
15364       int havesib;
15365       int havebase;
15366       int haveindex;
15367       int needindex;
15368       int base, rbase;
15369       int vindex = 0;
15370       int scale = 0;
15371       int addr32flag = !((sizeflag & AFLAG)
15372                          || bytemode == v_bnd_mode
15373                          || bytemode == bnd_mode);
15374       const char **indexes64 = names64;
15375       const char **indexes32 = names32;
15376
15377       havesib = 0;
15378       havebase = 1;
15379       haveindex = 0;
15380       base = modrm.rm;
15381
15382       if (base == 4)
15383         {
15384           havesib = 1;
15385           vindex = sib.index;
15386           USED_REX (REX_X);
15387           if (rex & REX_X)
15388             vindex += 8;
15389           switch (bytemode)
15390             {
15391             case vex_vsib_d_w_dq_mode:
15392             case vex_vsib_d_w_d_mode:
15393             case vex_vsib_q_w_dq_mode:
15394             case vex_vsib_q_w_d_mode:
15395               if (!need_vex)
15396                 abort ();
15397               if (vex.evex)
15398                 {
15399                   if (!vex.v)
15400                     vindex += 16;
15401                 }
15402
15403               haveindex = 1;
15404               switch (vex.length)
15405                 {
15406                 case 128:
15407                   indexes64 = indexes32 = names_xmm;
15408                   break;
15409                 case 256:
15410                   if (!vex.w
15411                       || bytemode == vex_vsib_q_w_dq_mode
15412                       || bytemode == vex_vsib_q_w_d_mode)
15413                     indexes64 = indexes32 = names_ymm;
15414                   else
15415                     indexes64 = indexes32 = names_xmm;
15416                   break;
15417                 case 512:
15418                   if (!vex.w
15419                       || bytemode == vex_vsib_q_w_dq_mode
15420                       || bytemode == vex_vsib_q_w_d_mode)
15421                     indexes64 = indexes32 = names_zmm;
15422                   else
15423                     indexes64 = indexes32 = names_ymm;
15424                   break;
15425                 default:
15426                   abort ();
15427                 }
15428               break;
15429             default:
15430               haveindex = vindex != 4;
15431               break;
15432             }
15433           scale = sib.scale;
15434           base = sib.base;
15435           codep++;
15436         }
15437       rbase = base + add;
15438
15439       switch (modrm.mod)
15440         {
15441         case 0:
15442           if (base == 5)
15443             {
15444               havebase = 0;
15445               if (address_mode == mode_64bit && !havesib)
15446                 riprel = 1;
15447               disp = get32s ();
15448             }
15449           break;
15450         case 1:
15451           FETCH_DATA (the_info, codep + 1);
15452           disp = *codep++;
15453           if ((disp & 0x80) != 0)
15454             disp -= 0x100;
15455           if (vex.evex && shift > 0)
15456             disp <<= shift;
15457           break;
15458         case 2:
15459           disp = get32s ();
15460           break;
15461         }
15462
15463       /* In 32bit mode, we need index register to tell [offset] from
15464          [eiz*1 + offset].  */
15465       needindex = (havesib
15466                    && !havebase
15467                    && !haveindex
15468                    && address_mode == mode_32bit);
15469       havedisp = (havebase
15470                   || needindex
15471                   || (havesib && (haveindex || scale != 0)));
15472
15473       if (!intel_syntax)
15474         if (modrm.mod != 0 || base == 5)
15475           {
15476             if (havedisp || riprel)
15477               print_displacement (scratchbuf, disp);
15478             else
15479               print_operand_value (scratchbuf, 1, disp);
15480             oappend (scratchbuf);
15481             if (riprel)
15482               {
15483                 set_op (disp, 1);
15484                 oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)");
15485               }
15486           }
15487
15488       if ((havebase || haveindex || riprel)
15489           && (bytemode != v_bnd_mode)
15490           && (bytemode != bnd_mode))
15491         used_prefixes |= PREFIX_ADDR;
15492
15493       if (havedisp || (intel_syntax && riprel))
15494         {
15495           *obufp++ = open_char;
15496           if (intel_syntax && riprel)
15497             {
15498               set_op (disp, 1);
15499               oappend (sizeflag & AFLAG ? "rip" : "eip");
15500             }
15501           *obufp = '\0';
15502           if (havebase)
15503             oappend (address_mode == mode_64bit && !addr32flag
15504                      ? names64[rbase] : names32[rbase]);
15505           if (havesib)
15506             {
15507               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
15508                  print index to tell base + index from base.  */
15509               if (scale != 0
15510                   || needindex
15511                   || haveindex
15512                   || (havebase && base != ESP_REG_NUM))
15513                 {
15514                   if (!intel_syntax || havebase)
15515                     {
15516                       *obufp++ = separator_char;
15517                       *obufp = '\0';
15518                     }
15519                   if (haveindex)
15520                     oappend (address_mode == mode_64bit && !addr32flag
15521                              ? indexes64[vindex] : indexes32[vindex]);
15522                   else
15523                     oappend (address_mode == mode_64bit && !addr32flag
15524                              ? index64 : index32);
15525
15526                   *obufp++ = scale_char;
15527                   *obufp = '\0';
15528                   sprintf (scratchbuf, "%d", 1 << scale);
15529                   oappend (scratchbuf);
15530                 }
15531             }
15532           if (intel_syntax
15533               && (disp || modrm.mod != 0 || base == 5))
15534             {
15535               if (!havedisp || (bfd_signed_vma) disp >= 0)
15536                 {
15537                   *obufp++ = '+';
15538                   *obufp = '\0';
15539                 }
15540               else if (modrm.mod != 1 && disp != -disp)
15541                 {
15542                   *obufp++ = '-';
15543                   *obufp = '\0';
15544                   disp = - (bfd_signed_vma) disp;
15545                 }
15546
15547               if (havedisp)
15548                 print_displacement (scratchbuf, disp);
15549               else
15550                 print_operand_value (scratchbuf, 1, disp);
15551               oappend (scratchbuf);
15552             }
15553
15554           *obufp++ = close_char;
15555           *obufp = '\0';
15556         }
15557       else if (intel_syntax)
15558         {
15559           if (modrm.mod != 0 || base == 5)
15560             {
15561               if (!active_seg_prefix)
15562                 {
15563                   oappend (names_seg[ds_reg - es_reg]);
15564                   oappend (":");
15565                 }
15566               print_operand_value (scratchbuf, 1, disp);
15567               oappend (scratchbuf);
15568             }
15569         }
15570     }
15571   else
15572     {
15573       /* 16 bit address mode */
15574       used_prefixes |= prefixes & PREFIX_ADDR;
15575       switch (modrm.mod)
15576         {
15577         case 0:
15578           if (modrm.rm == 6)
15579             {
15580               disp = get16 ();
15581               if ((disp & 0x8000) != 0)
15582                 disp -= 0x10000;
15583             }
15584           break;
15585         case 1:
15586           FETCH_DATA (the_info, codep + 1);
15587           disp = *codep++;
15588           if ((disp & 0x80) != 0)
15589             disp -= 0x100;
15590           break;
15591         case 2:
15592           disp = get16 ();
15593           if ((disp & 0x8000) != 0)
15594             disp -= 0x10000;
15595           break;
15596         }
15597
15598       if (!intel_syntax)
15599         if (modrm.mod != 0 || modrm.rm == 6)
15600           {
15601             print_displacement (scratchbuf, disp);
15602             oappend (scratchbuf);
15603           }
15604
15605       if (modrm.mod != 0 || modrm.rm != 6)
15606         {
15607           *obufp++ = open_char;
15608           *obufp = '\0';
15609           oappend (index16[modrm.rm]);
15610           if (intel_syntax
15611               && (disp || modrm.mod != 0 || modrm.rm == 6))
15612             {
15613               if ((bfd_signed_vma) disp >= 0)
15614                 {
15615                   *obufp++ = '+';
15616                   *obufp = '\0';
15617                 }
15618               else if (modrm.mod != 1)
15619                 {
15620                   *obufp++ = '-';
15621                   *obufp = '\0';
15622                   disp = - (bfd_signed_vma) disp;
15623                 }
15624
15625               print_displacement (scratchbuf, disp);
15626               oappend (scratchbuf);
15627             }
15628
15629           *obufp++ = close_char;
15630           *obufp = '\0';
15631         }
15632       else if (intel_syntax)
15633         {
15634           if (!active_seg_prefix)
15635             {
15636               oappend (names_seg[ds_reg - es_reg]);
15637               oappend (":");
15638             }
15639           print_operand_value (scratchbuf, 1, disp & 0xffff);
15640           oappend (scratchbuf);
15641         }
15642     }
15643   if (vex.evex && vex.b
15644       && (bytemode == x_mode
15645           || bytemode == xmmq_mode
15646           || bytemode == evex_half_bcst_xmmq_mode))
15647     {
15648       if (vex.w
15649           || bytemode == xmmq_mode
15650           || bytemode == evex_half_bcst_xmmq_mode)
15651         {
15652           switch (vex.length)
15653             {
15654             case 128:
15655               oappend ("{1to2}");
15656               break;
15657             case 256:
15658               oappend ("{1to4}");
15659               break;
15660             case 512:
15661               oappend ("{1to8}");
15662               break;
15663             default:
15664               abort ();
15665             }
15666         }
15667       else
15668         {
15669           switch (vex.length)
15670             {
15671             case 128:
15672               oappend ("{1to4}");
15673               break;
15674             case 256:
15675               oappend ("{1to8}");
15676               break;
15677             case 512:
15678               oappend ("{1to16}");
15679               break;
15680             default:
15681               abort ();
15682             }
15683         }
15684     }
15685 }
15686
15687 static void
15688 OP_E (int bytemode, int sizeflag)
15689 {
15690   /* Skip mod/rm byte.  */
15691   MODRM_CHECK;
15692   codep++;
15693
15694   if (modrm.mod == 3)
15695     OP_E_register (bytemode, sizeflag);
15696   else
15697     OP_E_memory (bytemode, sizeflag);
15698 }
15699
15700 static void
15701 OP_G (int bytemode, int sizeflag)
15702 {
15703   int add = 0;
15704   USED_REX (REX_R);
15705   if (rex & REX_R)
15706     add += 8;
15707   switch (bytemode)
15708     {
15709     case b_mode:
15710       USED_REX (0);
15711       if (rex)
15712         oappend (names8rex[modrm.reg + add]);
15713       else
15714         oappend (names8[modrm.reg + add]);
15715       break;
15716     case w_mode:
15717       oappend (names16[modrm.reg + add]);
15718       break;
15719     case d_mode:
15720     case db_mode:
15721     case dw_mode:
15722       oappend (names32[modrm.reg + add]);
15723       break;
15724     case q_mode:
15725       oappend (names64[modrm.reg + add]);
15726       break;
15727     case bnd_mode:
15728       oappend (names_bnd[modrm.reg]);
15729       break;
15730     case v_mode:
15731     case dq_mode:
15732     case dqb_mode:
15733     case dqd_mode:
15734     case dqw_mode:
15735     case dqw_swap_mode:
15736       USED_REX (REX_W);
15737       if (rex & REX_W)
15738         oappend (names64[modrm.reg + add]);
15739       else
15740         {
15741           if ((sizeflag & DFLAG) || bytemode != v_mode)
15742             oappend (names32[modrm.reg + add]);
15743           else
15744             oappend (names16[modrm.reg + add]);
15745           used_prefixes |= (prefixes & PREFIX_DATA);
15746         }
15747       break;
15748     case m_mode:
15749       if (address_mode == mode_64bit)
15750         oappend (names64[modrm.reg + add]);
15751       else
15752         oappend (names32[modrm.reg + add]);
15753       break;
15754     case mask_bd_mode:
15755     case mask_mode:
15756       oappend (names_mask[modrm.reg + add]);
15757       break;
15758     default:
15759       oappend (INTERNAL_DISASSEMBLER_ERROR);
15760       break;
15761     }
15762 }
15763
15764 static bfd_vma
15765 get64 (void)
15766 {
15767   bfd_vma x;
15768 #ifdef BFD64
15769   unsigned int a;
15770   unsigned int b;
15771
15772   FETCH_DATA (the_info, codep + 8);
15773   a = *codep++ & 0xff;
15774   a |= (*codep++ & 0xff) << 8;
15775   a |= (*codep++ & 0xff) << 16;
15776   a |= (*codep++ & 0xffu) << 24;
15777   b = *codep++ & 0xff;
15778   b |= (*codep++ & 0xff) << 8;
15779   b |= (*codep++ & 0xff) << 16;
15780   b |= (*codep++ & 0xffu) << 24;
15781   x = a + ((bfd_vma) b << 32);
15782 #else
15783   abort ();
15784   x = 0;
15785 #endif
15786   return x;
15787 }
15788
15789 static bfd_signed_vma
15790 get32 (void)
15791 {
15792   bfd_signed_vma x = 0;
15793
15794   FETCH_DATA (the_info, codep + 4);
15795   x = *codep++ & (bfd_signed_vma) 0xff;
15796   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15797   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15798   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15799   return x;
15800 }
15801
15802 static bfd_signed_vma
15803 get32s (void)
15804 {
15805   bfd_signed_vma x = 0;
15806
15807   FETCH_DATA (the_info, codep + 4);
15808   x = *codep++ & (bfd_signed_vma) 0xff;
15809   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15810   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15811   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15812
15813   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
15814
15815   return x;
15816 }
15817
15818 static int
15819 get16 (void)
15820 {
15821   int x = 0;
15822
15823   FETCH_DATA (the_info, codep + 2);
15824   x = *codep++ & 0xff;
15825   x |= (*codep++ & 0xff) << 8;
15826   return x;
15827 }
15828
15829 static void
15830 set_op (bfd_vma op, int riprel)
15831 {
15832   op_index[op_ad] = op_ad;
15833   if (address_mode == mode_64bit)
15834     {
15835       op_address[op_ad] = op;
15836       op_riprel[op_ad] = riprel;
15837     }
15838   else
15839     {
15840       /* Mask to get a 32-bit address.  */
15841       op_address[op_ad] = op & 0xffffffff;
15842       op_riprel[op_ad] = riprel & 0xffffffff;
15843     }
15844 }
15845
15846 static void
15847 OP_REG (int code, int sizeflag)
15848 {
15849   const char *s;
15850   int add;
15851
15852   switch (code)
15853     {
15854     case es_reg: case ss_reg: case cs_reg:
15855     case ds_reg: case fs_reg: case gs_reg:
15856       oappend (names_seg[code - es_reg]);
15857       return;
15858     }
15859
15860   USED_REX (REX_B);
15861   if (rex & REX_B)
15862     add = 8;
15863   else
15864     add = 0;
15865
15866   switch (code)
15867     {
15868     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15869     case sp_reg: case bp_reg: case si_reg: case di_reg:
15870       s = names16[code - ax_reg + add];
15871       break;
15872     case al_reg: case ah_reg: case cl_reg: case ch_reg:
15873     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15874       USED_REX (0);
15875       if (rex)
15876         s = names8rex[code - al_reg + add];
15877       else
15878         s = names8[code - al_reg];
15879       break;
15880     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
15881     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
15882       if (address_mode == mode_64bit
15883           && ((sizeflag & DFLAG) || (rex & REX_W)))
15884         {
15885           s = names64[code - rAX_reg + add];
15886           break;
15887         }
15888       code += eAX_reg - rAX_reg;
15889       /* Fall through.  */
15890     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15891     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15892       USED_REX (REX_W);
15893       if (rex & REX_W)
15894         s = names64[code - eAX_reg + add];
15895       else
15896         {
15897           if (sizeflag & DFLAG)
15898             s = names32[code - eAX_reg + add];
15899           else
15900             s = names16[code - eAX_reg + add];
15901           used_prefixes |= (prefixes & PREFIX_DATA);
15902         }
15903       break;
15904     default:
15905       s = INTERNAL_DISASSEMBLER_ERROR;
15906       break;
15907     }
15908   oappend (s);
15909 }
15910
15911 static void
15912 OP_IMREG (int code, int sizeflag)
15913 {
15914   const char *s;
15915
15916   switch (code)
15917     {
15918     case indir_dx_reg:
15919       if (intel_syntax)
15920         s = "dx";
15921       else
15922         s = "(%dx)";
15923       break;
15924     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15925     case sp_reg: case bp_reg: case si_reg: case di_reg:
15926       s = names16[code - ax_reg];
15927       break;
15928     case es_reg: case ss_reg: case cs_reg:
15929     case ds_reg: case fs_reg: case gs_reg:
15930       s = names_seg[code - es_reg];
15931       break;
15932     case al_reg: case ah_reg: case cl_reg: case ch_reg:
15933     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15934       USED_REX (0);
15935       if (rex)
15936         s = names8rex[code - al_reg];
15937       else
15938         s = names8[code - al_reg];
15939       break;
15940     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15941     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15942       USED_REX (REX_W);
15943       if (rex & REX_W)
15944         s = names64[code - eAX_reg];
15945       else
15946         {
15947           if (sizeflag & DFLAG)
15948             s = names32[code - eAX_reg];
15949           else
15950             s = names16[code - eAX_reg];
15951           used_prefixes |= (prefixes & PREFIX_DATA);
15952         }
15953       break;
15954     case z_mode_ax_reg:
15955       if ((rex & REX_W) || (sizeflag & DFLAG))
15956         s = *names32;
15957       else
15958         s = *names16;
15959       if (!(rex & REX_W))
15960         used_prefixes |= (prefixes & PREFIX_DATA);
15961       break;
15962     default:
15963       s = INTERNAL_DISASSEMBLER_ERROR;
15964       break;
15965     }
15966   oappend (s);
15967 }
15968
15969 static void
15970 OP_I (int bytemode, int sizeflag)
15971 {
15972   bfd_signed_vma op;
15973   bfd_signed_vma mask = -1;
15974
15975   switch (bytemode)
15976     {
15977     case b_mode:
15978       FETCH_DATA (the_info, codep + 1);
15979       op = *codep++;
15980       mask = 0xff;
15981       break;
15982     case q_mode:
15983       if (address_mode == mode_64bit)
15984         {
15985           op = get32s ();
15986           break;
15987         }
15988       /* Fall through.  */
15989     case v_mode:
15990       USED_REX (REX_W);
15991       if (rex & REX_W)
15992         op = get32s ();
15993       else
15994         {
15995           if (sizeflag & DFLAG)
15996             {
15997               op = get32 ();
15998               mask = 0xffffffff;
15999             }
16000           else
16001             {
16002               op = get16 ();
16003               mask = 0xfffff;
16004             }
16005           used_prefixes |= (prefixes & PREFIX_DATA);
16006         }
16007       break;
16008     case w_mode:
16009       mask = 0xfffff;
16010       op = get16 ();
16011       break;
16012     case const_1_mode:
16013       if (intel_syntax)
16014         oappend ("1");
16015       return;
16016     default:
16017       oappend (INTERNAL_DISASSEMBLER_ERROR);
16018       return;
16019     }
16020
16021   op &= mask;
16022   scratchbuf[0] = '$';
16023   print_operand_value (scratchbuf + 1, 1, op);
16024   oappend_maybe_intel (scratchbuf);
16025   scratchbuf[0] = '\0';
16026 }
16027
16028 static void
16029 OP_I64 (int bytemode, int sizeflag)
16030 {
16031   bfd_signed_vma op;
16032   bfd_signed_vma mask = -1;
16033
16034   if (address_mode != mode_64bit)
16035     {
16036       OP_I (bytemode, sizeflag);
16037       return;
16038     }
16039
16040   switch (bytemode)
16041     {
16042     case b_mode:
16043       FETCH_DATA (the_info, codep + 1);
16044       op = *codep++;
16045       mask = 0xff;
16046       break;
16047     case v_mode:
16048       USED_REX (REX_W);
16049       if (rex & REX_W)
16050         op = get64 ();
16051       else
16052         {
16053           if (sizeflag & DFLAG)
16054             {
16055               op = get32 ();
16056               mask = 0xffffffff;
16057             }
16058           else
16059             {
16060               op = get16 ();
16061               mask = 0xfffff;
16062             }
16063           used_prefixes |= (prefixes & PREFIX_DATA);
16064         }
16065       break;
16066     case w_mode:
16067       mask = 0xfffff;
16068       op = get16 ();
16069       break;
16070     default:
16071       oappend (INTERNAL_DISASSEMBLER_ERROR);
16072       return;
16073     }
16074
16075   op &= mask;
16076   scratchbuf[0] = '$';
16077   print_operand_value (scratchbuf + 1, 1, op);
16078   oappend_maybe_intel (scratchbuf);
16079   scratchbuf[0] = '\0';
16080 }
16081
16082 static void
16083 OP_sI (int bytemode, int sizeflag)
16084 {
16085   bfd_signed_vma op;
16086
16087   switch (bytemode)
16088     {
16089     case b_mode:
16090     case b_T_mode:
16091       FETCH_DATA (the_info, codep + 1);
16092       op = *codep++;
16093       if ((op & 0x80) != 0)
16094         op -= 0x100;
16095       if (bytemode == b_T_mode)
16096         {
16097           if (address_mode != mode_64bit
16098               || !((sizeflag & DFLAG) || (rex & REX_W)))
16099             {
16100               /* The operand-size prefix is overridden by a REX prefix.  */
16101               if ((sizeflag & DFLAG) || (rex & REX_W))
16102                 op &= 0xffffffff;
16103               else
16104                 op &= 0xffff;
16105           }
16106         }
16107       else
16108         {
16109           if (!(rex & REX_W))
16110             {
16111               if (sizeflag & DFLAG)
16112                 op &= 0xffffffff;
16113               else
16114                 op &= 0xffff;
16115             }
16116         }
16117       break;
16118     case v_mode:
16119       /* The operand-size prefix is overridden by a REX prefix.  */
16120       if ((sizeflag & DFLAG) || (rex & REX_W))
16121         op = get32s ();
16122       else
16123         op = get16 ();
16124       break;
16125     default:
16126       oappend (INTERNAL_DISASSEMBLER_ERROR);
16127       return;
16128     }
16129
16130   scratchbuf[0] = '$';
16131   print_operand_value (scratchbuf + 1, 1, op);
16132   oappend_maybe_intel (scratchbuf);
16133 }
16134
16135 static void
16136 OP_J (int bytemode, int sizeflag)
16137 {
16138   bfd_vma disp;
16139   bfd_vma mask = -1;
16140   bfd_vma segment = 0;
16141
16142   switch (bytemode)
16143     {
16144     case b_mode:
16145       FETCH_DATA (the_info, codep + 1);
16146       disp = *codep++;
16147       if ((disp & 0x80) != 0)
16148         disp -= 0x100;
16149       break;
16150     case v_mode:
16151       if (isa64 == amd64)
16152         USED_REX (REX_W);
16153       if ((sizeflag & DFLAG)
16154           || (address_mode == mode_64bit
16155               && (isa64 != amd64 || (rex & REX_W))))
16156         disp = get32s ();
16157       else
16158         {
16159           disp = get16 ();
16160           if ((disp & 0x8000) != 0)
16161             disp -= 0x10000;
16162           /* In 16bit mode, address is wrapped around at 64k within
16163              the same segment.  Otherwise, a data16 prefix on a jump
16164              instruction means that the pc is masked to 16 bits after
16165              the displacement is added!  */
16166           mask = 0xffff;
16167           if ((prefixes & PREFIX_DATA) == 0)
16168             segment = ((start_pc + (codep - start_codep))
16169                        & ~((bfd_vma) 0xffff));
16170         }
16171       if (address_mode != mode_64bit
16172           || (isa64 == amd64 && !(rex & REX_W)))
16173         used_prefixes |= (prefixes & PREFIX_DATA);
16174       break;
16175     default:
16176       oappend (INTERNAL_DISASSEMBLER_ERROR);
16177       return;
16178     }
16179   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
16180   set_op (disp, 0);
16181   print_operand_value (scratchbuf, 1, disp);
16182   oappend (scratchbuf);
16183 }
16184
16185 static void
16186 OP_SEG (int bytemode, int sizeflag)
16187 {
16188   if (bytemode == w_mode)
16189     oappend (names_seg[modrm.reg]);
16190   else
16191     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
16192 }
16193
16194 static void
16195 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
16196 {
16197   int seg, offset;
16198
16199   if (sizeflag & DFLAG)
16200     {
16201       offset = get32 ();
16202       seg = get16 ();
16203     }
16204   else
16205     {
16206       offset = get16 ();
16207       seg = get16 ();
16208     }
16209   used_prefixes |= (prefixes & PREFIX_DATA);
16210   if (intel_syntax)
16211     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
16212   else
16213     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
16214   oappend (scratchbuf);
16215 }
16216
16217 static void
16218 OP_OFF (int bytemode, int sizeflag)
16219 {
16220   bfd_vma off;
16221
16222   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
16223     intel_operand_size (bytemode, sizeflag);
16224   append_seg ();
16225
16226   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
16227     off = get32 ();
16228   else
16229     off = get16 ();
16230
16231   if (intel_syntax)
16232     {
16233       if (!active_seg_prefix)
16234         {
16235           oappend (names_seg[ds_reg - es_reg]);
16236           oappend (":");
16237         }
16238     }
16239   print_operand_value (scratchbuf, 1, off);
16240   oappend (scratchbuf);
16241 }
16242
16243 static void
16244 OP_OFF64 (int bytemode, int sizeflag)
16245 {
16246   bfd_vma off;
16247
16248   if (address_mode != mode_64bit
16249       || (prefixes & PREFIX_ADDR))
16250     {
16251       OP_OFF (bytemode, sizeflag);
16252       return;
16253     }
16254
16255   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
16256     intel_operand_size (bytemode, sizeflag);
16257   append_seg ();
16258
16259   off = get64 ();
16260
16261   if (intel_syntax)
16262     {
16263       if (!active_seg_prefix)
16264         {
16265           oappend (names_seg[ds_reg - es_reg]);
16266           oappend (":");
16267         }
16268     }
16269   print_operand_value (scratchbuf, 1, off);
16270   oappend (scratchbuf);
16271 }
16272
16273 static void
16274 ptr_reg (int code, int sizeflag)
16275 {
16276   const char *s;
16277
16278   *obufp++ = open_char;
16279   used_prefixes |= (prefixes & PREFIX_ADDR);
16280   if (address_mode == mode_64bit)
16281     {
16282       if (!(sizeflag & AFLAG))
16283         s = names32[code - eAX_reg];
16284       else
16285         s = names64[code - eAX_reg];
16286     }
16287   else if (sizeflag & AFLAG)
16288     s = names32[code - eAX_reg];
16289   else
16290     s = names16[code - eAX_reg];
16291   oappend (s);
16292   *obufp++ = close_char;
16293   *obufp = 0;
16294 }
16295
16296 static void
16297 OP_ESreg (int code, int sizeflag)
16298 {
16299   if (intel_syntax)
16300     {
16301       switch (codep[-1])
16302         {
16303         case 0x6d:      /* insw/insl */
16304           intel_operand_size (z_mode, sizeflag);
16305           break;
16306         case 0xa5:      /* movsw/movsl/movsq */
16307         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
16308         case 0xab:      /* stosw/stosl */
16309         case 0xaf:      /* scasw/scasl */
16310           intel_operand_size (v_mode, sizeflag);
16311           break;
16312         default:
16313           intel_operand_size (b_mode, sizeflag);
16314         }
16315     }
16316   oappend_maybe_intel ("%es:");
16317   ptr_reg (code, sizeflag);
16318 }
16319
16320 static void
16321 OP_DSreg (int code, int sizeflag)
16322 {
16323   if (intel_syntax)
16324     {
16325       switch (codep[-1])
16326         {
16327         case 0x6f:      /* outsw/outsl */
16328           intel_operand_size (z_mode, sizeflag);
16329           break;
16330         case 0xa5:      /* movsw/movsl/movsq */
16331         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
16332         case 0xad:      /* lodsw/lodsl/lodsq */
16333           intel_operand_size (v_mode, sizeflag);
16334           break;
16335         default:
16336           intel_operand_size (b_mode, sizeflag);
16337         }
16338     }
16339   /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
16340      default segment register DS is printed.  */
16341   if (!active_seg_prefix)
16342     active_seg_prefix = PREFIX_DS;
16343   append_seg ();
16344   ptr_reg (code, sizeflag);
16345 }
16346
16347 static void
16348 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16349 {
16350   int add;
16351   if (rex & REX_R)
16352     {
16353       USED_REX (REX_R);
16354       add = 8;
16355     }
16356   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
16357     {
16358       all_prefixes[last_lock_prefix] = 0;
16359       used_prefixes |= PREFIX_LOCK;
16360       add = 8;
16361     }
16362   else
16363     add = 0;
16364   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
16365   oappend_maybe_intel (scratchbuf);
16366 }
16367
16368 static void
16369 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16370 {
16371   int add;
16372   USED_REX (REX_R);
16373   if (rex & REX_R)
16374     add = 8;
16375   else
16376     add = 0;
16377   if (intel_syntax)
16378     sprintf (scratchbuf, "db%d", modrm.reg + add);
16379   else
16380     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
16381   oappend (scratchbuf);
16382 }
16383
16384 static void
16385 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16386 {
16387   sprintf (scratchbuf, "%%tr%d", modrm.reg);
16388   oappend_maybe_intel (scratchbuf);
16389 }
16390
16391 static void
16392 OP_R (int bytemode, int sizeflag)
16393 {
16394   /* Skip mod/rm byte.  */
16395   MODRM_CHECK;
16396   codep++;
16397   OP_E_register (bytemode, sizeflag);
16398 }
16399
16400 static void
16401 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16402 {
16403   int reg = modrm.reg;
16404   const char **names;
16405
16406   used_prefixes |= (prefixes & PREFIX_DATA);
16407   if (prefixes & PREFIX_DATA)
16408     {
16409       names = names_xmm;
16410       USED_REX (REX_R);
16411       if (rex & REX_R)
16412         reg += 8;
16413     }
16414   else
16415     names = names_mm;
16416   oappend (names[reg]);
16417 }
16418
16419 static void
16420 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16421 {
16422   int reg = modrm.reg;
16423   const char **names;
16424
16425   USED_REX (REX_R);
16426   if (rex & REX_R)
16427     reg += 8;
16428   if (vex.evex)
16429     {
16430       if (!vex.r)
16431         reg += 16;
16432     }
16433
16434   if (need_vex
16435       && bytemode != xmm_mode
16436       && bytemode != xmmq_mode
16437       && bytemode != evex_half_bcst_xmmq_mode
16438       && bytemode != ymm_mode
16439       && bytemode != scalar_mode)
16440     {
16441       switch (vex.length)
16442         {
16443         case 128:
16444           names = names_xmm;
16445           break;
16446         case 256:
16447           if (vex.w
16448               || (bytemode != vex_vsib_q_w_dq_mode
16449                   && bytemode != vex_vsib_q_w_d_mode))
16450             names = names_ymm;
16451           else
16452             names = names_xmm;
16453           break;
16454         case 512:
16455           names = names_zmm;
16456           break;
16457         default:
16458           abort ();
16459         }
16460     }
16461   else if (bytemode == xmmq_mode
16462            || bytemode == evex_half_bcst_xmmq_mode)
16463     {
16464       switch (vex.length)
16465         {
16466         case 128:
16467         case 256:
16468           names = names_xmm;
16469           break;
16470         case 512:
16471           names = names_ymm;
16472           break;
16473         default:
16474           abort ();
16475         }
16476     }
16477   else if (bytemode == ymm_mode)
16478     names = names_ymm;
16479   else
16480     names = names_xmm;
16481   oappend (names[reg]);
16482 }
16483
16484 static void
16485 OP_EM (int bytemode, int sizeflag)
16486 {
16487   int reg;
16488   const char **names;
16489
16490   if (modrm.mod != 3)
16491     {
16492       if (intel_syntax
16493           && (bytemode == v_mode || bytemode == v_swap_mode))
16494         {
16495           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16496           used_prefixes |= (prefixes & PREFIX_DATA);
16497         }
16498       OP_E (bytemode, sizeflag);
16499       return;
16500     }
16501
16502   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
16503     swap_operand ();
16504
16505   /* Skip mod/rm byte.  */
16506   MODRM_CHECK;
16507   codep++;
16508   used_prefixes |= (prefixes & PREFIX_DATA);
16509   reg = modrm.rm;
16510   if (prefixes & PREFIX_DATA)
16511     {
16512       names = names_xmm;
16513       USED_REX (REX_B);
16514       if (rex & REX_B)
16515         reg += 8;
16516     }
16517   else
16518     names = names_mm;
16519   oappend (names[reg]);
16520 }
16521
16522 /* cvt* are the only instructions in sse2 which have
16523    both SSE and MMX operands and also have 0x66 prefix
16524    in their opcode. 0x66 was originally used to differentiate
16525    between SSE and MMX instruction(operands). So we have to handle the
16526    cvt* separately using OP_EMC and OP_MXC */
16527 static void
16528 OP_EMC (int bytemode, int sizeflag)
16529 {
16530   if (modrm.mod != 3)
16531     {
16532       if (intel_syntax && bytemode == v_mode)
16533         {
16534           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16535           used_prefixes |= (prefixes & PREFIX_DATA);
16536         }
16537       OP_E (bytemode, sizeflag);
16538       return;
16539     }
16540
16541   /* Skip mod/rm byte.  */
16542   MODRM_CHECK;
16543   codep++;
16544   used_prefixes |= (prefixes & PREFIX_DATA);
16545   oappend (names_mm[modrm.rm]);
16546 }
16547
16548 static void
16549 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16550 {
16551   used_prefixes |= (prefixes & PREFIX_DATA);
16552   oappend (names_mm[modrm.reg]);
16553 }
16554
16555 static void
16556 OP_EX (int bytemode, int sizeflag)
16557 {
16558   int reg;
16559   const char **names;
16560
16561   /* Skip mod/rm byte.  */
16562   MODRM_CHECK;
16563   codep++;
16564
16565   if (modrm.mod != 3)
16566     {
16567       OP_E_memory (bytemode, sizeflag);
16568       return;
16569     }
16570
16571   reg = modrm.rm;
16572   USED_REX (REX_B);
16573   if (rex & REX_B)
16574     reg += 8;
16575   if (vex.evex)
16576     {
16577       USED_REX (REX_X);
16578       if ((rex & REX_X))
16579         reg += 16;
16580     }
16581
16582   if ((sizeflag & SUFFIX_ALWAYS)
16583       && (bytemode == x_swap_mode
16584           || bytemode == d_swap_mode
16585           || bytemode == dqw_swap_mode
16586           || bytemode == d_scalar_swap_mode
16587           || bytemode == q_swap_mode
16588           || bytemode == q_scalar_swap_mode))
16589     swap_operand ();
16590
16591   if (need_vex
16592       && bytemode != xmm_mode
16593       && bytemode != xmmdw_mode
16594       && bytemode != xmmqd_mode
16595       && bytemode != xmm_mb_mode
16596       && bytemode != xmm_mw_mode
16597       && bytemode != xmm_md_mode
16598       && bytemode != xmm_mq_mode
16599       && bytemode != xmm_mdq_mode
16600       && bytemode != xmmq_mode
16601       && bytemode != evex_half_bcst_xmmq_mode
16602       && bytemode != ymm_mode
16603       && bytemode != d_scalar_mode
16604       && bytemode != d_scalar_swap_mode
16605       && bytemode != q_scalar_mode
16606       && bytemode != q_scalar_swap_mode
16607       && bytemode != vex_scalar_w_dq_mode)
16608     {
16609       switch (vex.length)
16610         {
16611         case 128:
16612           names = names_xmm;
16613           break;
16614         case 256:
16615           names = names_ymm;
16616           break;
16617         case 512:
16618           names = names_zmm;
16619           break;
16620         default:
16621           abort ();
16622         }
16623     }
16624   else if (bytemode == xmmq_mode
16625            || bytemode == evex_half_bcst_xmmq_mode)
16626     {
16627       switch (vex.length)
16628         {
16629         case 128:
16630         case 256:
16631           names = names_xmm;
16632           break;
16633         case 512:
16634           names = names_ymm;
16635           break;
16636         default:
16637           abort ();
16638         }
16639     }
16640   else if (bytemode == ymm_mode)
16641     names = names_ymm;
16642   else
16643     names = names_xmm;
16644   oappend (names[reg]);
16645 }
16646
16647 static void
16648 OP_MS (int bytemode, int sizeflag)
16649 {
16650   if (modrm.mod == 3)
16651     OP_EM (bytemode, sizeflag);
16652   else
16653     BadOp ();
16654 }
16655
16656 static void
16657 OP_XS (int bytemode, int sizeflag)
16658 {
16659   if (modrm.mod == 3)
16660     OP_EX (bytemode, sizeflag);
16661   else
16662     BadOp ();
16663 }
16664
16665 static void
16666 OP_M (int bytemode, int sizeflag)
16667 {
16668   if (modrm.mod == 3)
16669     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
16670     BadOp ();
16671   else
16672     OP_E (bytemode, sizeflag);
16673 }
16674
16675 static void
16676 OP_0f07 (int bytemode, int sizeflag)
16677 {
16678   if (modrm.mod != 3 || modrm.rm != 0)
16679     BadOp ();
16680   else
16681     OP_E (bytemode, sizeflag);
16682 }
16683
16684 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
16685    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
16686
16687 static void
16688 NOP_Fixup1 (int bytemode, int sizeflag)
16689 {
16690   if ((prefixes & PREFIX_DATA) != 0
16691       || (rex != 0
16692           && rex != 0x48
16693           && address_mode == mode_64bit))
16694     OP_REG (bytemode, sizeflag);
16695   else
16696     strcpy (obuf, "nop");
16697 }
16698
16699 static void
16700 NOP_Fixup2 (int bytemode, int sizeflag)
16701 {
16702   if ((prefixes & PREFIX_DATA) != 0
16703       || (rex != 0
16704           && rex != 0x48
16705           && address_mode == mode_64bit))
16706     OP_IMREG (bytemode, sizeflag);
16707 }
16708
16709 static const char *const Suffix3DNow[] = {
16710 /* 00 */        NULL,           NULL,           NULL,           NULL,
16711 /* 04 */        NULL,           NULL,           NULL,           NULL,
16712 /* 08 */        NULL,           NULL,           NULL,           NULL,
16713 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
16714 /* 10 */        NULL,           NULL,           NULL,           NULL,
16715 /* 14 */        NULL,           NULL,           NULL,           NULL,
16716 /* 18 */        NULL,           NULL,           NULL,           NULL,
16717 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
16718 /* 20 */        NULL,           NULL,           NULL,           NULL,
16719 /* 24 */        NULL,           NULL,           NULL,           NULL,
16720 /* 28 */        NULL,           NULL,           NULL,           NULL,
16721 /* 2C */        NULL,           NULL,           NULL,           NULL,
16722 /* 30 */        NULL,           NULL,           NULL,           NULL,
16723 /* 34 */        NULL,           NULL,           NULL,           NULL,
16724 /* 38 */        NULL,           NULL,           NULL,           NULL,
16725 /* 3C */        NULL,           NULL,           NULL,           NULL,
16726 /* 40 */        NULL,           NULL,           NULL,           NULL,
16727 /* 44 */        NULL,           NULL,           NULL,           NULL,
16728 /* 48 */        NULL,           NULL,           NULL,           NULL,
16729 /* 4C */        NULL,           NULL,           NULL,           NULL,
16730 /* 50 */        NULL,           NULL,           NULL,           NULL,
16731 /* 54 */        NULL,           NULL,           NULL,           NULL,
16732 /* 58 */        NULL,           NULL,           NULL,           NULL,
16733 /* 5C */        NULL,           NULL,           NULL,           NULL,
16734 /* 60 */        NULL,           NULL,           NULL,           NULL,
16735 /* 64 */        NULL,           NULL,           NULL,           NULL,
16736 /* 68 */        NULL,           NULL,           NULL,           NULL,
16737 /* 6C */        NULL,           NULL,           NULL,           NULL,
16738 /* 70 */        NULL,           NULL,           NULL,           NULL,
16739 /* 74 */        NULL,           NULL,           NULL,           NULL,
16740 /* 78 */        NULL,           NULL,           NULL,           NULL,
16741 /* 7C */        NULL,           NULL,           NULL,           NULL,
16742 /* 80 */        NULL,           NULL,           NULL,           NULL,
16743 /* 84 */        NULL,           NULL,           NULL,           NULL,
16744 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
16745 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
16746 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
16747 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
16748 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
16749 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
16750 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
16751 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
16752 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
16753 /* AC */        NULL,           NULL,           "pfacc",        NULL,
16754 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
16755 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
16756 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
16757 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
16758 /* C0 */        NULL,           NULL,           NULL,           NULL,
16759 /* C4 */        NULL,           NULL,           NULL,           NULL,
16760 /* C8 */        NULL,           NULL,           NULL,           NULL,
16761 /* CC */        NULL,           NULL,           NULL,           NULL,
16762 /* D0 */        NULL,           NULL,           NULL,           NULL,
16763 /* D4 */        NULL,           NULL,           NULL,           NULL,
16764 /* D8 */        NULL,           NULL,           NULL,           NULL,
16765 /* DC */        NULL,           NULL,           NULL,           NULL,
16766 /* E0 */        NULL,           NULL,           NULL,           NULL,
16767 /* E4 */        NULL,           NULL,           NULL,           NULL,
16768 /* E8 */        NULL,           NULL,           NULL,           NULL,
16769 /* EC */        NULL,           NULL,           NULL,           NULL,
16770 /* F0 */        NULL,           NULL,           NULL,           NULL,
16771 /* F4 */        NULL,           NULL,           NULL,           NULL,
16772 /* F8 */        NULL,           NULL,           NULL,           NULL,
16773 /* FC */        NULL,           NULL,           NULL,           NULL,
16774 };
16775
16776 static void
16777 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16778 {
16779   const char *mnemonic;
16780
16781   FETCH_DATA (the_info, codep + 1);
16782   /* AMD 3DNow! instructions are specified by an opcode suffix in the
16783      place where an 8-bit immediate would normally go.  ie. the last
16784      byte of the instruction.  */
16785   obufp = mnemonicendp;
16786   mnemonic = Suffix3DNow[*codep++ & 0xff];
16787   if (mnemonic)
16788     oappend (mnemonic);
16789   else
16790     {
16791       /* Since a variable sized modrm/sib chunk is between the start
16792          of the opcode (0x0f0f) and the opcode suffix, we need to do
16793          all the modrm processing first, and don't know until now that
16794          we have a bad opcode.  This necessitates some cleaning up.  */
16795       op_out[0][0] = '\0';
16796       op_out[1][0] = '\0';
16797       BadOp ();
16798     }
16799   mnemonicendp = obufp;
16800 }
16801
16802 static struct op simd_cmp_op[] =
16803 {
16804   { STRING_COMMA_LEN ("eq") },
16805   { STRING_COMMA_LEN ("lt") },
16806   { STRING_COMMA_LEN ("le") },
16807   { STRING_COMMA_LEN ("unord") },
16808   { STRING_COMMA_LEN ("neq") },
16809   { STRING_COMMA_LEN ("nlt") },
16810   { STRING_COMMA_LEN ("nle") },
16811   { STRING_COMMA_LEN ("ord") }
16812 };
16813
16814 static void
16815 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16816 {
16817   unsigned int cmp_type;
16818
16819   FETCH_DATA (the_info, codep + 1);
16820   cmp_type = *codep++ & 0xff;
16821   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
16822     {
16823       char suffix [3];
16824       char *p = mnemonicendp - 2;
16825       suffix[0] = p[0];
16826       suffix[1] = p[1];
16827       suffix[2] = '\0';
16828       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16829       mnemonicendp += simd_cmp_op[cmp_type].len;
16830     }
16831   else
16832     {
16833       /* We have a reserved extension byte.  Output it directly.  */
16834       scratchbuf[0] = '$';
16835       print_operand_value (scratchbuf + 1, 1, cmp_type);
16836       oappend_maybe_intel (scratchbuf);
16837       scratchbuf[0] = '\0';
16838     }
16839 }
16840
16841 static void
16842 OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED,
16843           int sizeflag ATTRIBUTE_UNUSED)
16844 {
16845   /* mwaitx %eax,%ecx,%ebx */
16846   if (!intel_syntax)
16847     {
16848       const char **names = (address_mode == mode_64bit
16849                             ? names64 : names32);
16850       strcpy (op_out[0], names[0]);
16851       strcpy (op_out[1], names[1]);
16852       strcpy (op_out[2], names[3]);
16853       two_source_ops = 1;
16854     }
16855   /* Skip mod/rm byte.  */
16856   MODRM_CHECK;
16857   codep++;
16858 }
16859
16860 static void
16861 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
16862           int sizeflag ATTRIBUTE_UNUSED)
16863 {
16864   /* mwait %eax,%ecx  */
16865   if (!intel_syntax)
16866     {
16867       const char **names = (address_mode == mode_64bit
16868                             ? names64 : names32);
16869       strcpy (op_out[0], names[0]);
16870       strcpy (op_out[1], names[1]);
16871       two_source_ops = 1;
16872     }
16873   /* Skip mod/rm byte.  */
16874   MODRM_CHECK;
16875   codep++;
16876 }
16877
16878 static void
16879 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
16880             int sizeflag ATTRIBUTE_UNUSED)
16881 {
16882   /* monitor %eax,%ecx,%edx"  */
16883   if (!intel_syntax)
16884     {
16885       const char **op1_names;
16886       const char **names = (address_mode == mode_64bit
16887                             ? names64 : names32);
16888
16889       if (!(prefixes & PREFIX_ADDR))
16890         op1_names = (address_mode == mode_16bit
16891                      ? names16 : names);
16892       else
16893         {
16894           /* Remove "addr16/addr32".  */
16895           all_prefixes[last_addr_prefix] = 0;
16896           op1_names = (address_mode != mode_32bit
16897                        ? names32 : names16);
16898           used_prefixes |= PREFIX_ADDR;
16899         }
16900       strcpy (op_out[0], op1_names[0]);
16901       strcpy (op_out[1], names[1]);
16902       strcpy (op_out[2], names[2]);
16903       two_source_ops = 1;
16904     }
16905   /* Skip mod/rm byte.  */
16906   MODRM_CHECK;
16907   codep++;
16908 }
16909
16910 static void
16911 BadOp (void)
16912 {
16913   /* Throw away prefixes and 1st. opcode byte.  */
16914   codep = insn_codep + 1;
16915   oappend ("(bad)");
16916 }
16917
16918 static void
16919 REP_Fixup (int bytemode, int sizeflag)
16920 {
16921   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
16922      lods and stos.  */
16923   if (prefixes & PREFIX_REPZ)
16924     all_prefixes[last_repz_prefix] = REP_PREFIX;
16925
16926   switch (bytemode)
16927     {
16928     case al_reg:
16929     case eAX_reg:
16930     case indir_dx_reg:
16931       OP_IMREG (bytemode, sizeflag);
16932       break;
16933     case eDI_reg:
16934       OP_ESreg (bytemode, sizeflag);
16935       break;
16936     case eSI_reg:
16937       OP_DSreg (bytemode, sizeflag);
16938       break;
16939     default:
16940       abort ();
16941       break;
16942     }
16943 }
16944
16945 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
16946    "bnd".  */
16947
16948 static void
16949 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16950 {
16951   if (prefixes & PREFIX_REPNZ)
16952     all_prefixes[last_repnz_prefix] = BND_PREFIX;
16953 }
16954
16955 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
16956    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
16957  */
16958
16959 static void
16960 HLE_Fixup1 (int bytemode, int sizeflag)
16961 {
16962   if (modrm.mod != 3
16963       && (prefixes & PREFIX_LOCK) != 0)
16964     {
16965       if (prefixes & PREFIX_REPZ)
16966         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16967       if (prefixes & PREFIX_REPNZ)
16968         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16969     }
16970
16971   OP_E (bytemode, sizeflag);
16972 }
16973
16974 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
16975    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
16976  */
16977
16978 static void
16979 HLE_Fixup2 (int bytemode, int sizeflag)
16980 {
16981   if (modrm.mod != 3)
16982     {
16983       if (prefixes & PREFIX_REPZ)
16984         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16985       if (prefixes & PREFIX_REPNZ)
16986         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16987     }
16988
16989   OP_E (bytemode, sizeflag);
16990 }
16991
16992 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
16993    "xrelease" for memory operand.  No check for LOCK prefix.   */
16994
16995 static void
16996 HLE_Fixup3 (int bytemode, int sizeflag)
16997 {
16998   if (modrm.mod != 3
16999       && last_repz_prefix > last_repnz_prefix
17000       && (prefixes & PREFIX_REPZ) != 0)
17001     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
17002
17003   OP_E (bytemode, sizeflag);
17004 }
17005
17006 static void
17007 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
17008 {
17009   USED_REX (REX_W);
17010   if (rex & REX_W)
17011     {
17012       /* Change cmpxchg8b to cmpxchg16b.  */
17013       char *p = mnemonicendp - 2;
17014       mnemonicendp = stpcpy (p, "16b");
17015       bytemode = o_mode;
17016     }
17017   else if ((prefixes & PREFIX_LOCK) != 0)
17018     {
17019       if (prefixes & PREFIX_REPZ)
17020         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
17021       if (prefixes & PREFIX_REPNZ)
17022         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
17023     }
17024
17025   OP_M (bytemode, sizeflag);
17026 }
17027
17028 static void
17029 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
17030 {
17031   const char **names;
17032
17033   if (need_vex)
17034     {
17035       switch (vex.length)
17036         {
17037         case 128:
17038           names = names_xmm;
17039           break;
17040         case 256:
17041           names = names_ymm;
17042           break;
17043         default:
17044           abort ();
17045         }
17046     }
17047   else
17048     names = names_xmm;
17049   oappend (names[reg]);
17050 }
17051
17052 static void
17053 CRC32_Fixup (int bytemode, int sizeflag)
17054 {
17055   /* Add proper suffix to "crc32".  */
17056   char *p = mnemonicendp;
17057
17058   switch (bytemode)
17059     {
17060     case b_mode:
17061       if (intel_syntax)
17062         goto skip;
17063
17064       *p++ = 'b';
17065       break;
17066     case v_mode:
17067       if (intel_syntax)
17068         goto skip;
17069
17070       USED_REX (REX_W);
17071       if (rex & REX_W)
17072         *p++ = 'q';
17073       else
17074         {
17075           if (sizeflag & DFLAG)
17076             *p++ = 'l';
17077           else
17078             *p++ = 'w';
17079           used_prefixes |= (prefixes & PREFIX_DATA);
17080         }
17081       break;
17082     default:
17083       oappend (INTERNAL_DISASSEMBLER_ERROR);
17084       break;
17085     }
17086   mnemonicendp = p;
17087   *p = '\0';
17088
17089 skip:
17090   if (modrm.mod == 3)
17091     {
17092       int add;
17093
17094       /* Skip mod/rm byte.  */
17095       MODRM_CHECK;
17096       codep++;
17097
17098       USED_REX (REX_B);
17099       add = (rex & REX_B) ? 8 : 0;
17100       if (bytemode == b_mode)
17101         {
17102           USED_REX (0);
17103           if (rex)
17104             oappend (names8rex[modrm.rm + add]);
17105           else
17106             oappend (names8[modrm.rm + add]);
17107         }
17108       else
17109         {
17110           USED_REX (REX_W);
17111           if (rex & REX_W)
17112             oappend (names64[modrm.rm + add]);
17113           else if ((prefixes & PREFIX_DATA))
17114             oappend (names16[modrm.rm + add]);
17115           else
17116             oappend (names32[modrm.rm + add]);
17117         }
17118     }
17119   else
17120     OP_E (bytemode, sizeflag);
17121 }
17122
17123 static void
17124 FXSAVE_Fixup (int bytemode, int sizeflag)
17125 {
17126   /* Add proper suffix to "fxsave" and "fxrstor".  */
17127   USED_REX (REX_W);
17128   if (rex & REX_W)
17129     {
17130       char *p = mnemonicendp;
17131       *p++ = '6';
17132       *p++ = '4';
17133       *p = '\0';
17134       mnemonicendp = p;
17135     }
17136   OP_M (bytemode, sizeflag);
17137 }
17138
17139 /* Display the destination register operand for instructions with
17140    VEX. */
17141
17142 static void
17143 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17144 {
17145   int reg;
17146   const char **names;
17147
17148   if (!need_vex)
17149     abort ();
17150
17151   if (!need_vex_reg)
17152     return;
17153
17154   reg = vex.register_specifier;
17155   if (vex.evex)
17156     {
17157       if (!vex.v)
17158         reg += 16;
17159     }
17160
17161   if (bytemode == vex_scalar_mode)
17162     {
17163       oappend (names_xmm[reg]);
17164       return;
17165     }
17166
17167   switch (vex.length)
17168     {
17169     case 128:
17170       switch (bytemode)
17171         {
17172         case vex_mode:
17173         case vex128_mode:
17174         case vex_vsib_q_w_dq_mode:
17175         case vex_vsib_q_w_d_mode:
17176           names = names_xmm;
17177           break;
17178         case dq_mode:
17179           if (vex.w)
17180             names = names64;
17181           else
17182             names = names32;
17183           break;
17184         case mask_bd_mode:
17185         case mask_mode:
17186           names = names_mask;
17187           break;
17188         default:
17189           abort ();
17190           return;
17191         }
17192       break;
17193     case 256:
17194       switch (bytemode)
17195         {
17196         case vex_mode:
17197         case vex256_mode:
17198           names = names_ymm;
17199           break;
17200         case vex_vsib_q_w_dq_mode:
17201         case vex_vsib_q_w_d_mode:
17202           names = vex.w ? names_ymm : names_xmm;
17203           break;
17204         case mask_bd_mode:
17205         case mask_mode:
17206           names = names_mask;
17207           break;
17208         default:
17209           abort ();
17210           return;
17211         }
17212       break;
17213     case 512:
17214       names = names_zmm;
17215       break;
17216     default:
17217       abort ();
17218       break;
17219     }
17220   oappend (names[reg]);
17221 }
17222
17223 /* Get the VEX immediate byte without moving codep.  */
17224
17225 static unsigned char
17226 get_vex_imm8 (int sizeflag, int opnum)
17227 {
17228   int bytes_before_imm = 0;
17229
17230   if (modrm.mod != 3)
17231     {
17232       /* There are SIB/displacement bytes.  */
17233       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
17234         {
17235           /* 32/64 bit address mode */
17236           int base = modrm.rm;
17237
17238           /* Check SIB byte.  */
17239           if (base == 4)
17240             {
17241               FETCH_DATA (the_info, codep + 1);
17242               base = *codep & 7;
17243               /* When decoding the third source, don't increase
17244                  bytes_before_imm as this has already been incremented
17245                  by one in OP_E_memory while decoding the second
17246                  source operand.  */
17247               if (opnum == 0)
17248                 bytes_before_imm++;
17249             }
17250
17251           /* Don't increase bytes_before_imm when decoding the third source,
17252              it has already been incremented by OP_E_memory while decoding
17253              the second source operand.  */
17254           if (opnum == 0)
17255             {
17256               switch (modrm.mod)
17257                 {
17258                   case 0:
17259                     /* When modrm.rm == 5 or modrm.rm == 4 and base in
17260                        SIB == 5, there is a 4 byte displacement.  */
17261                     if (base != 5)
17262                       /* No displacement. */
17263                       break;
17264                   case 2:
17265                     /* 4 byte displacement.  */
17266                     bytes_before_imm += 4;
17267                     break;
17268                   case 1:
17269                     /* 1 byte displacement.  */
17270                     bytes_before_imm++;
17271                     break;
17272                 }
17273             }
17274         }
17275       else
17276         {
17277           /* 16 bit address mode */
17278           /* Don't increase bytes_before_imm when decoding the third source,
17279              it has already been incremented by OP_E_memory while decoding
17280              the second source operand.  */
17281           if (opnum == 0)
17282             {
17283               switch (modrm.mod)
17284                 {
17285                 case 0:
17286                   /* When modrm.rm == 6, there is a 2 byte displacement.  */
17287                   if (modrm.rm != 6)
17288                     /* No displacement. */
17289                     break;
17290                 case 2:
17291                   /* 2 byte displacement.  */
17292                   bytes_before_imm += 2;
17293                   break;
17294                 case 1:
17295                   /* 1 byte displacement: when decoding the third source,
17296                      don't increase bytes_before_imm as this has already
17297                      been incremented by one in OP_E_memory while decoding
17298                      the second source operand.  */
17299                   if (opnum == 0)
17300                     bytes_before_imm++;
17301
17302                   break;
17303                 }
17304             }
17305         }
17306     }
17307
17308   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
17309   return codep [bytes_before_imm];
17310 }
17311
17312 static void
17313 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
17314 {
17315   const char **names;
17316
17317   if (reg == -1 && modrm.mod != 3)
17318     {
17319       OP_E_memory (bytemode, sizeflag);
17320       return;
17321     }
17322   else
17323     {
17324       if (reg == -1)
17325         {
17326           reg = modrm.rm;
17327           USED_REX (REX_B);
17328           if (rex & REX_B)
17329             reg += 8;
17330         }
17331       else if (reg > 7 && address_mode != mode_64bit)
17332         BadOp ();
17333     }
17334
17335   switch (vex.length)
17336     {
17337     case 128:
17338       names = names_xmm;
17339       break;
17340     case 256:
17341       names = names_ymm;
17342       break;
17343     default:
17344       abort ();
17345     }
17346   oappend (names[reg]);
17347 }
17348
17349 static void
17350 OP_EX_VexImmW (int bytemode, int sizeflag)
17351 {
17352   int reg = -1;
17353   static unsigned char vex_imm8;
17354
17355   if (vex_w_done == 0)
17356     {
17357       vex_w_done = 1;
17358
17359       /* Skip mod/rm byte.  */
17360       MODRM_CHECK;
17361       codep++;
17362
17363       vex_imm8 = get_vex_imm8 (sizeflag, 0);
17364
17365       if (vex.w)
17366           reg = vex_imm8 >> 4;
17367
17368       OP_EX_VexReg (bytemode, sizeflag, reg);
17369     }
17370   else if (vex_w_done == 1)
17371     {
17372       vex_w_done = 2;
17373
17374       if (!vex.w)
17375           reg = vex_imm8 >> 4;
17376
17377       OP_EX_VexReg (bytemode, sizeflag, reg);
17378     }
17379   else
17380     {
17381       /* Output the imm8 directly.  */
17382       scratchbuf[0] = '$';
17383       print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
17384       oappend_maybe_intel (scratchbuf);
17385       scratchbuf[0] = '\0';
17386       codep++;
17387     }
17388 }
17389
17390 static void
17391 OP_Vex_2src (int bytemode, int sizeflag)
17392 {
17393   if (modrm.mod == 3)
17394     {
17395       int reg = modrm.rm;
17396       USED_REX (REX_B);
17397       if (rex & REX_B)
17398         reg += 8;
17399       oappend (names_xmm[reg]);
17400     }
17401   else
17402     {
17403       if (intel_syntax
17404           && (bytemode == v_mode || bytemode == v_swap_mode))
17405         {
17406           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
17407           used_prefixes |= (prefixes & PREFIX_DATA);
17408         }
17409       OP_E (bytemode, sizeflag);
17410     }
17411 }
17412
17413 static void
17414 OP_Vex_2src_1 (int bytemode, int sizeflag)
17415 {
17416   if (modrm.mod == 3)
17417     {
17418       /* Skip mod/rm byte.   */
17419       MODRM_CHECK;
17420       codep++;
17421     }
17422
17423   if (vex.w)
17424     oappend (names_xmm[vex.register_specifier]);
17425   else
17426     OP_Vex_2src (bytemode, sizeflag);
17427 }
17428
17429 static void
17430 OP_Vex_2src_2 (int bytemode, int sizeflag)
17431 {
17432   if (vex.w)
17433     OP_Vex_2src (bytemode, sizeflag);
17434   else
17435     oappend (names_xmm[vex.register_specifier]);
17436 }
17437
17438 static void
17439 OP_EX_VexW (int bytemode, int sizeflag)
17440 {
17441   int reg = -1;
17442
17443   if (!vex_w_done)
17444     {
17445       vex_w_done = 1;
17446
17447       /* Skip mod/rm byte.  */
17448       MODRM_CHECK;
17449       codep++;
17450
17451       if (vex.w)
17452         reg = get_vex_imm8 (sizeflag, 0) >> 4;
17453     }
17454   else
17455     {
17456       if (!vex.w)
17457         reg = get_vex_imm8 (sizeflag, 1) >> 4;
17458     }
17459
17460   OP_EX_VexReg (bytemode, sizeflag, reg);
17461 }
17462
17463 static void
17464 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,
17465              int sizeflag ATTRIBUTE_UNUSED)
17466 {
17467   /* Skip the immediate byte and check for invalid bits.  */
17468   FETCH_DATA (the_info, codep + 1);
17469   if (*codep++ & 0xf)
17470     BadOp ();
17471 }
17472
17473 static void
17474 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17475 {
17476   int reg;
17477   const char **names;
17478
17479   FETCH_DATA (the_info, codep + 1);
17480   reg = *codep++;
17481
17482   if (bytemode != x_mode)
17483     abort ();
17484
17485   if (reg & 0xf)
17486       BadOp ();
17487
17488   reg >>= 4;
17489   if (reg > 7 && address_mode != mode_64bit)
17490     BadOp ();
17491
17492   switch (vex.length)
17493     {
17494     case 128:
17495       names = names_xmm;
17496       break;
17497     case 256:
17498       names = names_ymm;
17499       break;
17500     default:
17501       abort ();
17502     }
17503   oappend (names[reg]);
17504 }
17505
17506 static void
17507 OP_XMM_VexW (int bytemode, int sizeflag)
17508 {
17509   /* Turn off the REX.W bit since it is used for swapping operands
17510      now.  */
17511   rex &= ~REX_W;
17512   OP_XMM (bytemode, sizeflag);
17513 }
17514
17515 static void
17516 OP_EX_Vex (int bytemode, int sizeflag)
17517 {
17518   if (modrm.mod != 3)
17519     {
17520       if (vex.register_specifier != 0)
17521         BadOp ();
17522       need_vex_reg = 0;
17523     }
17524   OP_EX (bytemode, sizeflag);
17525 }
17526
17527 static void
17528 OP_XMM_Vex (int bytemode, int sizeflag)
17529 {
17530   if (modrm.mod != 3)
17531     {
17532       if (vex.register_specifier != 0)
17533         BadOp ();
17534       need_vex_reg = 0;
17535     }
17536   OP_XMM (bytemode, sizeflag);
17537 }
17538
17539 static void
17540 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17541 {
17542   switch (vex.length)
17543     {
17544     case 128:
17545       mnemonicendp = stpcpy (obuf, "vzeroupper");
17546       break;
17547     case 256:
17548       mnemonicendp = stpcpy (obuf, "vzeroall");
17549       break;
17550     default:
17551       abort ();
17552     }
17553 }
17554
17555 static struct op vex_cmp_op[] =
17556 {
17557   { STRING_COMMA_LEN ("eq") },
17558   { STRING_COMMA_LEN ("lt") },
17559   { STRING_COMMA_LEN ("le") },
17560   { STRING_COMMA_LEN ("unord") },
17561   { STRING_COMMA_LEN ("neq") },
17562   { STRING_COMMA_LEN ("nlt") },
17563   { STRING_COMMA_LEN ("nle") },
17564   { STRING_COMMA_LEN ("ord") },
17565   { STRING_COMMA_LEN ("eq_uq") },
17566   { STRING_COMMA_LEN ("nge") },
17567   { STRING_COMMA_LEN ("ngt") },
17568   { STRING_COMMA_LEN ("false") },
17569   { STRING_COMMA_LEN ("neq_oq") },
17570   { STRING_COMMA_LEN ("ge") },
17571   { STRING_COMMA_LEN ("gt") },
17572   { STRING_COMMA_LEN ("true") },
17573   { STRING_COMMA_LEN ("eq_os") },
17574   { STRING_COMMA_LEN ("lt_oq") },
17575   { STRING_COMMA_LEN ("le_oq") },
17576   { STRING_COMMA_LEN ("unord_s") },
17577   { STRING_COMMA_LEN ("neq_us") },
17578   { STRING_COMMA_LEN ("nlt_uq") },
17579   { STRING_COMMA_LEN ("nle_uq") },
17580   { STRING_COMMA_LEN ("ord_s") },
17581   { STRING_COMMA_LEN ("eq_us") },
17582   { STRING_COMMA_LEN ("nge_uq") },
17583   { STRING_COMMA_LEN ("ngt_uq") },
17584   { STRING_COMMA_LEN ("false_os") },
17585   { STRING_COMMA_LEN ("neq_os") },
17586   { STRING_COMMA_LEN ("ge_oq") },
17587   { STRING_COMMA_LEN ("gt_oq") },
17588   { STRING_COMMA_LEN ("true_us") },
17589 };
17590
17591 static void
17592 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17593 {
17594   unsigned int cmp_type;
17595
17596   FETCH_DATA (the_info, codep + 1);
17597   cmp_type = *codep++ & 0xff;
17598   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
17599     {
17600       char suffix [3];
17601       char *p = mnemonicendp - 2;
17602       suffix[0] = p[0];
17603       suffix[1] = p[1];
17604       suffix[2] = '\0';
17605       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
17606       mnemonicendp += vex_cmp_op[cmp_type].len;
17607     }
17608   else
17609     {
17610       /* We have a reserved extension byte.  Output it directly.  */
17611       scratchbuf[0] = '$';
17612       print_operand_value (scratchbuf + 1, 1, cmp_type);
17613       oappend_maybe_intel (scratchbuf);
17614       scratchbuf[0] = '\0';
17615     }
17616 }
17617
17618 static void
17619 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
17620              int sizeflag ATTRIBUTE_UNUSED)
17621 {
17622   unsigned int cmp_type;
17623
17624   if (!vex.evex)
17625     abort ();
17626
17627   FETCH_DATA (the_info, codep + 1);
17628   cmp_type = *codep++ & 0xff;
17629   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
17630      If it's the case, print suffix, otherwise - print the immediate.  */
17631   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
17632       && cmp_type != 3
17633       && cmp_type != 7)
17634     {
17635       char suffix [3];
17636       char *p = mnemonicendp - 2;
17637
17638       /* vpcmp* can have both one- and two-lettered suffix.  */
17639       if (p[0] == 'p')
17640         {
17641           p++;
17642           suffix[0] = p[0];
17643           suffix[1] = '\0';
17644         }
17645       else
17646         {
17647           suffix[0] = p[0];
17648           suffix[1] = p[1];
17649           suffix[2] = '\0';
17650         }
17651
17652       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
17653       mnemonicendp += simd_cmp_op[cmp_type].len;
17654     }
17655   else
17656     {
17657       /* We have a reserved extension byte.  Output it directly.  */
17658       scratchbuf[0] = '$';
17659       print_operand_value (scratchbuf + 1, 1, cmp_type);
17660       oappend_maybe_intel (scratchbuf);
17661       scratchbuf[0] = '\0';
17662     }
17663 }
17664
17665 static const struct op pclmul_op[] =
17666 {
17667   { STRING_COMMA_LEN ("lql") },
17668   { STRING_COMMA_LEN ("hql") },
17669   { STRING_COMMA_LEN ("lqh") },
17670   { STRING_COMMA_LEN ("hqh") }
17671 };
17672
17673 static void
17674 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
17675               int sizeflag ATTRIBUTE_UNUSED)
17676 {
17677   unsigned int pclmul_type;
17678
17679   FETCH_DATA (the_info, codep + 1);
17680   pclmul_type = *codep++ & 0xff;
17681   switch (pclmul_type)
17682     {
17683     case 0x10:
17684       pclmul_type = 2;
17685       break;
17686     case 0x11:
17687       pclmul_type = 3;
17688       break;
17689     default:
17690       break;
17691     }
17692   if (pclmul_type < ARRAY_SIZE (pclmul_op))
17693     {
17694       char suffix [4];
17695       char *p = mnemonicendp - 3;
17696       suffix[0] = p[0];
17697       suffix[1] = p[1];
17698       suffix[2] = p[2];
17699       suffix[3] = '\0';
17700       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
17701       mnemonicendp += pclmul_op[pclmul_type].len;
17702     }
17703   else
17704     {
17705       /* We have a reserved extension byte.  Output it directly.  */
17706       scratchbuf[0] = '$';
17707       print_operand_value (scratchbuf + 1, 1, pclmul_type);
17708       oappend_maybe_intel (scratchbuf);
17709       scratchbuf[0] = '\0';
17710     }
17711 }
17712
17713 static void
17714 MOVBE_Fixup (int bytemode, int sizeflag)
17715 {
17716   /* Add proper suffix to "movbe".  */
17717   char *p = mnemonicendp;
17718
17719   switch (bytemode)
17720     {
17721     case v_mode:
17722       if (intel_syntax)
17723         goto skip;
17724
17725       USED_REX (REX_W);
17726       if (sizeflag & SUFFIX_ALWAYS)
17727         {
17728           if (rex & REX_W)
17729             *p++ = 'q';
17730           else
17731             {
17732               if (sizeflag & DFLAG)
17733                 *p++ = 'l';
17734               else
17735                 *p++ = 'w';
17736               used_prefixes |= (prefixes & PREFIX_DATA);
17737             }
17738         }
17739       break;
17740     default:
17741       oappend (INTERNAL_DISASSEMBLER_ERROR);
17742       break;
17743     }
17744   mnemonicendp = p;
17745   *p = '\0';
17746
17747 skip:
17748   OP_M (bytemode, sizeflag);
17749 }
17750
17751 static void
17752 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17753 {
17754   int reg;
17755   const char **names;
17756
17757   /* Skip mod/rm byte.  */
17758   MODRM_CHECK;
17759   codep++;
17760
17761   if (vex.w)
17762     names = names64;
17763   else
17764     names = names32;
17765
17766   reg = modrm.rm;
17767   USED_REX (REX_B);
17768   if (rex & REX_B)
17769     reg += 8;
17770
17771   oappend (names[reg]);
17772 }
17773
17774 static void
17775 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17776 {
17777   const char **names;
17778
17779   if (vex.w)
17780     names = names64;
17781   else
17782     names = names32;
17783
17784   oappend (names[vex.register_specifier]);
17785 }
17786
17787 static void
17788 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17789 {
17790   if (!vex.evex
17791       || (bytemode != mask_mode && bytemode != mask_bd_mode))
17792     abort ();
17793
17794   USED_REX (REX_R);
17795   if ((rex & REX_R) != 0 || !vex.r)
17796     {
17797       BadOp ();
17798       return;
17799     }
17800
17801   oappend (names_mask [modrm.reg]);
17802 }
17803
17804 static void
17805 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17806 {
17807   if (!vex.evex
17808       || (bytemode != evex_rounding_mode
17809           && bytemode != evex_sae_mode))
17810     abort ();
17811   if (modrm.mod == 3 && vex.b)
17812     switch (bytemode)
17813       {
17814       case evex_rounding_mode:
17815         oappend (names_rounding[vex.ll]);
17816         break;
17817       case evex_sae_mode:
17818         oappend ("{sae}");
17819         break;
17820       default:
17821         break;
17822       }
17823 }