opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2014 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "dis-asm.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40
  41 #include <setjmp.h>
  42
  43 static int print_insn (bfd_vma, disassemble_info *);
  44 static void dofloat (int);
  45 static void OP_ST (int, int);
  46 static void OP_STi (int, int);
  47 static int putop (const char *, int);
  48 static void oappend (const char *);
  49 static void append_seg (void);
  50 static void OP_indirE (int, int);
  51 static void print_operand_value (char *, int, bfd_vma);
  52 static void OP_E_register (int, int);
  53 static void OP_E_memory (int, int);
  54 static void print_displacement (char *, bfd_vma);
  55 static void OP_E (int, int);
  56 static void OP_G (int, int);
  57 static bfd_vma get64 (void);
  58 static bfd_signed_vma get32 (void);
  59 static bfd_signed_vma get32s (void);
  60 static int get16 (void);
  61 static void set_op (bfd_vma, int);
  62 static void OP_Skip_MODRM (int, int);
  63 static void OP_REG (int, int);
  64 static void OP_IMREG (int, int);
  65 static void OP_I (int, int);
  66 static void OP_I64 (int, int);
  67 static void OP_sI (int, int);
  68 static void OP_J (int, int);
  69 static void OP_SEG (int, int);
  70 static void OP_DIR (int, int);
  71 static void OP_OFF (int, int);
  72 static void OP_OFF64 (int, int);
  73 static void ptr_reg (int, int);
  74 static void OP_ESreg (int, int);
  75 static void OP_DSreg (int, int);
  76 static void OP_C (int, int);
  77 static void OP_D (int, int);
  78 static void OP_T (int, int);
  79 static void OP_R (int, int);
  80 static void OP_MMX (int, int);
  81 static void OP_XMM (int, int);
  82 static void OP_EM (int, int);
  83 static void OP_EX (int, int);
  84 static void OP_EMC (int,int);
  85 static void OP_MXC (int,int);
  86 static void OP_MS (int, int);
  87 static void OP_XS (int, int);
  88 static void OP_M (int, int);
  89 static void OP_VEX (int, int);
  90 static void OP_EX_Vex (int, int);
  91 static void OP_EX_VexW (int, int);
  92 static void OP_EX_VexImmW (int, int);
  93 static void OP_XMM_Vex (int, int);
  94 static void OP_XMM_VexW (int, int);
  95 static void OP_Rounding (int, int);
  96 static void OP_REG_VexI4 (int, int);
  97 static void PCLMUL_Fixup (int, int);
  98 static void VEXI4_Fixup (int, int);
  99 static void VZERO_Fixup (int, int);
 100 static void VCMP_Fixup (int, int);
 101 static void VPCMP_Fixup (int, int);
 102 static void OP_0f07 (int, int);
 103 static void OP_Monitor (int, int);
 104 static void OP_Mwait (int, int);
 105 static void NOP_Fixup1 (int, int);
 106 static void NOP_Fixup2 (int, int);
 107 static void OP_3DNowSuffix (int, int);
 108 static void CMP_Fixup (int, int);
 109 static void BadOp (void);
 110 static void REP_Fixup (int, int);
 111 static void BND_Fixup (int, int);
 112 static void HLE_Fixup1 (int, int);
 113 static void HLE_Fixup2 (int, int);
 114 static void HLE_Fixup3 (int, int);
 115 static void CMPXCHG8B_Fixup (int, int);
 116 static void XMM_Fixup (int, int);
 117 static void CRC32_Fixup (int, int);
 118 static void FXSAVE_Fixup (int, int);
 119 static void OP_LWPCB_E (int, int);
 120 static void OP_LWP_E (int, int);
 121 static void OP_Vex_2src_1 (int, int);
 122 static void OP_Vex_2src_2 (int, int);
 123
 124 static void MOVBE_Fixup (int, int);
 125
 126 static void OP_Mask (int, int);
 127
 128 struct dis_private {
 129   /* Points to first byte not fetched.  */
 130   bfd_byte *max_fetched;
 131   bfd_byte the_buffer[MAX_MNEM_SIZE];
 132   bfd_vma insn_start;
 133   int orig_sizeflag;
 134   OPCODES_SIGJMP_BUF bailout;
 135 };
 136
 137 enum address_mode
 138 {
 139   mode_16bit,
 140   mode_32bit,
 141   mode_64bit
 142 };
 143
 144 enum address_mode address_mode;
 145
 146 /* Flags for the prefixes for the current instruction.  See below.  */
 147 static int prefixes;
 148
 149 /* REX prefix the current instruction.  See below.  */
 150 static int rex;
 151 /* Bits of REX we've already used.  */
 152 static int rex_used;
 153 /* REX bits in original REX prefix ignored.  */
 154 static int rex_ignored;
 155 /* Mark parts used in the REX prefix.  When we are testing for
 156    empty prefix (for 8bit register REX extension), just mask it
 157    out.  Otherwise test for REX bit is excuse for existence of REX
 158    only in case value is nonzero.  */
 159 #define USED_REX(value)                                 \
 160   {                                                     \
 161     if (value)                                          \
 162       {                                                 \
 163         if ((rex & value))                              \
 164           rex_used |= (value) | REX_OPCODE;             \
 165       }                                                 \
 166     else                                                \
 167       rex_used |= REX_OPCODE;                           \
 168   }
 169
 170 /* Flags for prefixes which we somehow handled when printing the
 171    current instruction.  */
 172 static int used_prefixes;
 173
 174 /* Flags stored in PREFIXES.  */
 175 #define PREFIX_REPZ 1
 176 #define PREFIX_REPNZ 2
 177 #define PREFIX_LOCK 4
 178 #define PREFIX_CS 8
 179 #define PREFIX_SS 0x10
 180 #define PREFIX_DS 0x20
 181 #define PREFIX_ES 0x40
 182 #define PREFIX_FS 0x80
 183 #define PREFIX_GS 0x100
 184 #define PREFIX_DATA 0x200
 185 #define PREFIX_ADDR 0x400
 186 #define PREFIX_FWAIT 0x800
 187
 188 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 189    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 190    on error.  */
 191 #define FETCH_DATA(info, addr) \
 192   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 193    ? 1 : fetch_data ((info), (addr)))
 194
 195 static int
 196 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 197 {
 198   int status;
 199   struct dis_private *priv = (struct dis_private *) info->private_data;
 200   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 201
 202   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 203     status = (*info->read_memory_func) (start,
 204                                         priv->max_fetched,
 205                                         addr - priv->max_fetched,
 206                                         info);
 207   else
 208     status = -1;
 209   if (status != 0)
 210     {
 211       /* If we did manage to read at least one byte, then
 212          print_insn_i386 will do something sensible.  Otherwise, print
 213          an error.  We do that here because this is where we know
 214          STATUS.  */
 215       if (priv->max_fetched == priv->the_buffer)
 216         (*info->memory_error_func) (status, start, info);
 217       OPCODES_SIGLONGJMP (priv->bailout, 1);
 218     }
 219   else
 220     priv->max_fetched = addr;
 221   return 1;
 222 }
 223
 224 #define XX { NULL, 0 }
 225 #define Bad_Opcode NULL, { { NULL, 0 } }
 226
 227 #define Eb { OP_E, b_mode }
 228 #define Ebnd { OP_E, bnd_mode }
 229 #define EbS { OP_E, b_swap_mode }
 230 #define Ev { OP_E, v_mode }
 231 #define Ev_bnd { OP_E, v_bnd_mode }
 232 #define EvS { OP_E, v_swap_mode }
 233 #define Ed { OP_E, d_mode }
 234 #define Edq { OP_E, dq_mode }
 235 #define Edqw { OP_E, dqw_mode }
 236 #define EdqwS { OP_E, dqw_swap_mode }
 237 #define Edqb { OP_E, dqb_mode }
 238 #define Edb { OP_E, db_mode }
 239 #define Edw { OP_E, dw_mode }
 240 #define Edqd { OP_E, dqd_mode }
 241 #define Eq { OP_E, q_mode }
 242 #define indirEv { OP_indirE, stack_v_mode }
 243 #define indirEp { OP_indirE, f_mode }
 244 #define stackEv { OP_E, stack_v_mode }
 245 #define Em { OP_E, m_mode }
 246 #define Ew { OP_E, w_mode }
 247 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 248 #define Ma { OP_M, a_mode }
 249 #define Mb { OP_M, b_mode }
 250 #define Md { OP_M, d_mode }
 251 #define Mo { OP_M, o_mode }
 252 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 253 #define Mq { OP_M, q_mode }
 254 #define Mx { OP_M, x_mode }
 255 #define Mxmm { OP_M, xmm_mode }
 256 #define Gb { OP_G, b_mode }
 257 #define Gbnd { OP_G, bnd_mode }
 258 #define Gv { OP_G, v_mode }
 259 #define Gd { OP_G, d_mode }
 260 #define Gdq { OP_G, dq_mode }
 261 #define Gm { OP_G, m_mode }
 262 #define Gw { OP_G, w_mode }
 263 #define Rd { OP_R, d_mode }
 264 #define Rdq { OP_R, dq_mode }
 265 #define Rm { OP_R, m_mode }
 266 #define Ib { OP_I, b_mode }
 267 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 268 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 269 #define Iv { OP_I, v_mode }
 270 #define sIv { OP_sI, v_mode }
 271 #define Iq { OP_I, q_mode }
 272 #define Iv64 { OP_I64, v_mode }
 273 #define Iw { OP_I, w_mode }
 274 #define I1 { OP_I, const_1_mode }
 275 #define Jb { OP_J, b_mode }
 276 #define Jv { OP_J, v_mode }
 277 #define Cm { OP_C, m_mode }
 278 #define Dm { OP_D, m_mode }
 279 #define Td { OP_T, d_mode }
 280 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 281
 282 #define RMeAX { OP_REG, eAX_reg }
 283 #define RMeBX { OP_REG, eBX_reg }
 284 #define RMeCX { OP_REG, eCX_reg }
 285 #define RMeDX { OP_REG, eDX_reg }
 286 #define RMeSP { OP_REG, eSP_reg }
 287 #define RMeBP { OP_REG, eBP_reg }
 288 #define RMeSI { OP_REG, eSI_reg }
 289 #define RMeDI { OP_REG, eDI_reg }
 290 #define RMrAX { OP_REG, rAX_reg }
 291 #define RMrBX { OP_REG, rBX_reg }
 292 #define RMrCX { OP_REG, rCX_reg }
 293 #define RMrDX { OP_REG, rDX_reg }
 294 #define RMrSP { OP_REG, rSP_reg }
 295 #define RMrBP { OP_REG, rBP_reg }
 296 #define RMrSI { OP_REG, rSI_reg }
 297 #define RMrDI { OP_REG, rDI_reg }
 298 #define RMAL { OP_REG, al_reg }
 299 #define RMCL { OP_REG, cl_reg }
 300 #define RMDL { OP_REG, dl_reg }
 301 #define RMBL { OP_REG, bl_reg }
 302 #define RMAH { OP_REG, ah_reg }
 303 #define RMCH { OP_REG, ch_reg }
 304 #define RMDH { OP_REG, dh_reg }
 305 #define RMBH { OP_REG, bh_reg }
 306 #define RMAX { OP_REG, ax_reg }
 307 #define RMDX { OP_REG, dx_reg }
 308
 309 #define eAX { OP_IMREG, eAX_reg }
 310 #define eBX { OP_IMREG, eBX_reg }
 311 #define eCX { OP_IMREG, eCX_reg }
 312 #define eDX { OP_IMREG, eDX_reg }
 313 #define eSP { OP_IMREG, eSP_reg }
 314 #define eBP { OP_IMREG, eBP_reg }
 315 #define eSI { OP_IMREG, eSI_reg }
 316 #define eDI { OP_IMREG, eDI_reg }
 317 #define AL { OP_IMREG, al_reg }
 318 #define CL { OP_IMREG, cl_reg }
 319 #define DL { OP_IMREG, dl_reg }
 320 #define BL { OP_IMREG, bl_reg }
 321 #define AH { OP_IMREG, ah_reg }
 322 #define CH { OP_IMREG, ch_reg }
 323 #define DH { OP_IMREG, dh_reg }
 324 #define BH { OP_IMREG, bh_reg }
 325 #define AX { OP_IMREG, ax_reg }
 326 #define DX { OP_IMREG, dx_reg }
 327 #define zAX { OP_IMREG, z_mode_ax_reg }
 328 #define indirDX { OP_IMREG, indir_dx_reg }
 329
 330 #define Sw { OP_SEG, w_mode }
 331 #define Sv { OP_SEG, v_mode }
 332 #define Ap { OP_DIR, 0 }
 333 #define Ob { OP_OFF64, b_mode }
 334 #define Ov { OP_OFF64, v_mode }
 335 #define Xb { OP_DSreg, eSI_reg }
 336 #define Xv { OP_DSreg, eSI_reg }
 337 #define Xz { OP_DSreg, eSI_reg }
 338 #define Yb { OP_ESreg, eDI_reg }
 339 #define Yv { OP_ESreg, eDI_reg }
 340 #define DSBX { OP_DSreg, eBX_reg }
 341
 342 #define es { OP_REG, es_reg }
 343 #define ss { OP_REG, ss_reg }
 344 #define cs { OP_REG, cs_reg }
 345 #define ds { OP_REG, ds_reg }
 346 #define fs { OP_REG, fs_reg }
 347 #define gs { OP_REG, gs_reg }
 348
 349 #define MX { OP_MMX, 0 }
 350 #define XM { OP_XMM, 0 }
 351 #define XMScalar { OP_XMM, scalar_mode }
 352 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 353 #define XMM { OP_XMM, xmm_mode }
 354 #define XMxmmq { OP_XMM, xmmq_mode }
 355 #define EM { OP_EM, v_mode }
 356 #define EMS { OP_EM, v_swap_mode }
 357 #define EMd { OP_EM, d_mode }
 358 #define EMx { OP_EM, x_mode }
 359 #define EXw { OP_EX, w_mode }
 360 #define EXd { OP_EX, d_mode }
 361 #define EXdScalar { OP_EX, d_scalar_mode }
 362 #define EXdS { OP_EX, d_swap_mode }
 363 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
 364 #define EXq { OP_EX, q_mode }
 365 #define EXqScalar { OP_EX, q_scalar_mode }
 366 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
 367 #define EXqS { OP_EX, q_swap_mode }
 368 #define EXx { OP_EX, x_mode }
 369 #define EXxS { OP_EX, x_swap_mode }
 370 #define EXxmm { OP_EX, xmm_mode }
 371 #define EXymm { OP_EX, ymm_mode }
 372 #define EXxmmq { OP_EX, xmmq_mode }
 373 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 374 #define EXxmm_mb { OP_EX, xmm_mb_mode }
 375 #define EXxmm_mw { OP_EX, xmm_mw_mode }
 376 #define EXxmm_md { OP_EX, xmm_md_mode }
 377 #define EXxmm_mq { OP_EX, xmm_mq_mode }
 378 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
 379 #define EXxmmdw { OP_EX, xmmdw_mode }
 380 #define EXxmmqd { OP_EX, xmmqd_mode }
 381 #define EXymmq { OP_EX, ymmq_mode }
 382 #define EXVexWdq { OP_EX, vex_w_dq_mode }
 383 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 384 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 385 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 386 #define MS { OP_MS, v_mode }
 387 #define XS { OP_XS, v_mode }
 388 #define EMCq { OP_EMC, q_mode }
 389 #define MXC { OP_MXC, 0 }
 390 #define OPSUF { OP_3DNowSuffix, 0 }
 391 #define CMP { CMP_Fixup, 0 }
 392 #define XMM0 { XMM_Fixup, 0 }
 393 #define FXSAVE { FXSAVE_Fixup, 0 }
 394 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
 395 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
 396
 397 #define Vex { OP_VEX, vex_mode }
 398 #define VexScalar { OP_VEX, vex_scalar_mode }
 399 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 400 #define Vex128 { OP_VEX, vex128_mode }
 401 #define Vex256 { OP_VEX, vex256_mode }
 402 #define VexGdq { OP_VEX, dq_mode }
 403 #define VexI4 { VEXI4_Fixup, 0}
 404 #define EXdVex { OP_EX_Vex, d_mode }
 405 #define EXdVexS { OP_EX_Vex, d_swap_mode }
 406 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
 407 #define EXqVex { OP_EX_Vex, q_mode }
 408 #define EXqVexS { OP_EX_Vex, q_swap_mode }
 409 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
 410 #define EXVexW { OP_EX_VexW, x_mode }
 411 #define EXdVexW { OP_EX_VexW, d_mode }
 412 #define EXqVexW { OP_EX_VexW, q_mode }
 413 #define EXVexImmW { OP_EX_VexImmW, x_mode }
 414 #define XMVex { OP_XMM_Vex, 0 }
 415 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
 416 #define XMVexW { OP_XMM_VexW, 0 }
 417 #define XMVexI4 { OP_REG_VexI4, x_mode }
 418 #define PCLMUL { PCLMUL_Fixup, 0 }
 419 #define VZERO { VZERO_Fixup, 0 }
 420 #define VCMP { VCMP_Fixup, 0 }
 421 #define VPCMP { VPCMP_Fixup, 0 }
 422
 423 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 424 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 425
 426 #define XMask { OP_Mask, mask_mode }
 427 #define MaskG { OP_G, mask_mode }
 428 #define MaskE { OP_E, mask_mode }
 429 #define MaskBDE { OP_E, mask_bd_mode }
 430 #define MaskR { OP_R, mask_mode }
 431 #define MaskVex { OP_VEX, mask_mode }
 432
 433 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 434 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
 435 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 436 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
 437
 438 /* Used handle "rep" prefix for string instructions.  */
 439 #define Xbr { REP_Fixup, eSI_reg }
 440 #define Xvr { REP_Fixup, eSI_reg }
 441 #define Ybr { REP_Fixup, eDI_reg }
 442 #define Yvr { REP_Fixup, eDI_reg }
 443 #define Yzr { REP_Fixup, eDI_reg }
 444 #define indirDXr { REP_Fixup, indir_dx_reg }
 445 #define ALr { REP_Fixup, al_reg }
 446 #define eAXr { REP_Fixup, eAX_reg }
 447
 448 /* Used handle HLE prefix for lockable instructions.  */
 449 #define Ebh1 { HLE_Fixup1, b_mode }
 450 #define Evh1 { HLE_Fixup1, v_mode }
 451 #define Ebh2 { HLE_Fixup2, b_mode }
 452 #define Evh2 { HLE_Fixup2, v_mode }
 453 #define Ebh3 { HLE_Fixup3, b_mode }
 454 #define Evh3 { HLE_Fixup3, v_mode }
 455
 456 #define BND { BND_Fixup, 0 }
 457
 458 #define cond_jump_flag { NULL, cond_jump_mode }
 459 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 460
 461 /* bits in sizeflag */
 462 #define SUFFIX_ALWAYS 4
 463 #define AFLAG 2
 464 #define DFLAG 1
 465
 466 enum
 467 {
 468   /* byte operand */
 469   b_mode = 1,
 470   /* byte operand with operand swapped */
 471   b_swap_mode,
 472   /* byte operand, sign extend like 'T' suffix */
 473   b_T_mode,
 474   /* operand size depends on prefixes */
 475   v_mode,
 476   /* operand size depends on prefixes with operand swapped */
 477   v_swap_mode,
 478   /* word operand */
 479   w_mode,
 480   /* double word operand  */
 481   d_mode,
 482   /* double word operand with operand swapped */
 483   d_swap_mode,
 484   /* quad word operand */
 485   q_mode,
 486   /* quad word operand with operand swapped */
 487   q_swap_mode,
 488   /* ten-byte operand */
 489   t_mode,
 490   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 491      broadcast enabled.  */
 492   x_mode,
 493   /* Similar to x_mode, but with different EVEX mem shifts.  */
 494   evex_x_gscat_mode,
 495   /* Similar to x_mode, but with disabled broadcast.  */
 496   evex_x_nobcst_mode,
 497   /* Similar to x_mode, but with operands swapped and disabled broadcast
 498      in EVEX.  */
 499   x_swap_mode,
 500   /* 16-byte XMM operand */
 501   xmm_mode,
 502   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 503      memory operand (depending on vector length).  Broadcast isn't
 504      allowed.  */
 505   xmmq_mode,
 506   /* Same as xmmq_mode, but broadcast is allowed.  */
 507   evex_half_bcst_xmmq_mode,
 508   /* XMM register or byte memory operand */
 509   xmm_mb_mode,
 510   /* XMM register or word memory operand */
 511   xmm_mw_mode,
 512   /* XMM register or double word memory operand */
 513   xmm_md_mode,
 514   /* XMM register or quad word memory operand */
 515   xmm_mq_mode,
 516   /* XMM register or double/quad word memory operand, depending on
 517      VEX.W.  */
 518   xmm_mdq_mode,
 519   /* 16-byte XMM, word, double word or quad word operand.  */
 520   xmmdw_mode,
 521   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 522   xmmqd_mode,
 523   /* 32-byte YMM operand */
 524   ymm_mode,
 525   /* quad word, ymmword or zmmword memory operand.  */
 526   ymmq_mode,
 527   /* 32-byte YMM or 16-byte word operand */
 528   ymmxmm_mode,
 529   /* d_mode in 32bit, q_mode in 64bit mode.  */
 530   m_mode,
 531   /* pair of v_mode operands */
 532   a_mode,
 533   cond_jump_mode,
 534   loop_jcxz_mode,
 535   v_bnd_mode,
 536   /* operand size depends on REX prefixes.  */
 537   dq_mode,
 538   /* registers like dq_mode, memory like w_mode.  */
 539   dqw_mode,
 540   dqw_swap_mode,
 541   bnd_mode,
 542   /* 4- or 6-byte pointer operand */
 543   f_mode,
 544   const_1_mode,
 545   /* v_mode for stack-related opcodes.  */
 546   stack_v_mode,
 547   /* non-quad operand size depends on prefixes */
 548   z_mode,
 549   /* 16-byte operand */
 550   o_mode,
 551   /* registers like dq_mode, memory like b_mode.  */
 552   dqb_mode,
 553   /* registers like d_mode, memory like b_mode.  */
 554   db_mode,
 555   /* registers like d_mode, memory like w_mode.  */
 556   dw_mode,
 557   /* registers like dq_mode, memory like d_mode.  */
 558   dqd_mode,
 559   /* normal vex mode */
 560   vex_mode,
 561   /* 128bit vex mode */
 562   vex128_mode,
 563   /* 256bit vex mode */
 564   vex256_mode,
 565   /* operand size depends on the VEX.W bit.  */
 566   vex_w_dq_mode,
 567
 568   /* Similar to vex_w_dq_mode, with VSIB dword indices.  */
 569   vex_vsib_d_w_dq_mode,
 570   /* Similar to vex_vsib_d_w_dq_mode, with smaller memory.  */
 571   vex_vsib_d_w_d_mode,
 572   /* Similar to vex_w_dq_mode, with VSIB qword indices.  */
 573   vex_vsib_q_w_dq_mode,
 574   /* Similar to vex_vsib_q_w_dq_mode, with smaller memory.  */
 575   vex_vsib_q_w_d_mode,
 576
 577   /* scalar, ignore vector length.  */
 578   scalar_mode,
 579   /* like d_mode, ignore vector length.  */
 580   d_scalar_mode,
 581   /* like d_swap_mode, ignore vector length.  */
 582   d_scalar_swap_mode,
 583   /* like q_mode, ignore vector length.  */
 584   q_scalar_mode,
 585   /* like q_swap_mode, ignore vector length.  */
 586   q_scalar_swap_mode,
 587   /* like vex_mode, ignore vector length.  */
 588   vex_scalar_mode,
 589   /* like vex_w_dq_mode, ignore vector length.  */
 590   vex_scalar_w_dq_mode,
 591
 592   /* Static rounding.  */
 593   evex_rounding_mode,
 594   /* Supress all exceptions.  */
 595   evex_sae_mode,
 596
 597   /* Mask register operand.  */
 598   mask_mode,
 599   /* Mask register operand.  */
 600   mask_bd_mode,
 601
 602   es_reg,
 603   cs_reg,
 604   ss_reg,
 605   ds_reg,
 606   fs_reg,
 607   gs_reg,
 608
 609   eAX_reg,
 610   eCX_reg,
 611   eDX_reg,
 612   eBX_reg,
 613   eSP_reg,
 614   eBP_reg,
 615   eSI_reg,
 616   eDI_reg,
 617
 618   al_reg,
 619   cl_reg,
 620   dl_reg,
 621   bl_reg,
 622   ah_reg,
 623   ch_reg,
 624   dh_reg,
 625   bh_reg,
 626
 627   ax_reg,
 628   cx_reg,
 629   dx_reg,
 630   bx_reg,
 631   sp_reg,
 632   bp_reg,
 633   si_reg,
 634   di_reg,
 635
 636   rAX_reg,
 637   rCX_reg,
 638   rDX_reg,
 639   rBX_reg,
 640   rSP_reg,
 641   rBP_reg,
 642   rSI_reg,
 643   rDI_reg,
 644
 645   z_mode_ax_reg,
 646   indir_dx_reg
 647 };
 648
 649 enum
 650 {
 651   FLOATCODE = 1,
 652   USE_REG_TABLE,
 653   USE_MOD_TABLE,
 654   USE_RM_TABLE,
 655   USE_PREFIX_TABLE,
 656   USE_X86_64_TABLE,
 657   USE_3BYTE_TABLE,
 658   USE_XOP_8F_TABLE,
 659   USE_VEX_C4_TABLE,
 660   USE_VEX_C5_TABLE,
 661   USE_VEX_LEN_TABLE,
 662   USE_VEX_W_TABLE,
 663   USE_EVEX_TABLE
 664 };
 665
 666 #define FLOAT                   NULL, { { NULL, FLOATCODE } }
 667
 668 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }
 669 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 670 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 671 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 672 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 673 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 674 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 675 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 676 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 677 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 678 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 679 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 680 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 681
 682 enum
 683 {
 684   REG_80 = 0,
 685   REG_81,
 686   REG_82,
 687   REG_8F,
 688   REG_C0,
 689   REG_C1,
 690   REG_C6,
 691   REG_C7,
 692   REG_D0,
 693   REG_D1,
 694   REG_D2,
 695   REG_D3,
 696   REG_F6,
 697   REG_F7,
 698   REG_FE,
 699   REG_FF,
 700   REG_0F00,
 701   REG_0F01,
 702   REG_0F0D,
 703   REG_0F18,
 704   REG_0F71,
 705   REG_0F72,
 706   REG_0F73,
 707   REG_0FA6,
 708   REG_0FA7,
 709   REG_0FAE,
 710   REG_0FBA,
 711   REG_0FC7,
 712   REG_VEX_0F71,
 713   REG_VEX_0F72,
 714   REG_VEX_0F73,
 715   REG_VEX_0FAE,
 716   REG_VEX_0F38F3,
 717   REG_XOP_LWPCB,
 718   REG_XOP_LWP,
 719   REG_XOP_TBM_01,
 720   REG_XOP_TBM_02,
 721
 722   REG_EVEX_0F71,
 723   REG_EVEX_0F72,
 724   REG_EVEX_0F73,
 725   REG_EVEX_0F38C6,
 726   REG_EVEX_0F38C7
 727 };
 728
 729 enum
 730 {
 731   MOD_8D = 0,
 732   MOD_C6_REG_7,
 733   MOD_C7_REG_7,
 734   MOD_FF_REG_3,
 735   MOD_FF_REG_5,
 736   MOD_0F01_REG_0,
 737   MOD_0F01_REG_1,
 738   MOD_0F01_REG_2,
 739   MOD_0F01_REG_3,
 740   MOD_0F01_REG_7,
 741   MOD_0F12_PREFIX_0,
 742   MOD_0F13,
 743   MOD_0F16_PREFIX_0,
 744   MOD_0F17,
 745   MOD_0F18_REG_0,
 746   MOD_0F18_REG_1,
 747   MOD_0F18_REG_2,
 748   MOD_0F18_REG_3,
 749   MOD_0F18_REG_4,
 750   MOD_0F18_REG_5,
 751   MOD_0F18_REG_6,
 752   MOD_0F18_REG_7,
 753   MOD_0F1A_PREFIX_0,
 754   MOD_0F1B_PREFIX_0,
 755   MOD_0F1B_PREFIX_1,
 756   MOD_0F24,
 757   MOD_0F26,
 758   MOD_0F2B_PREFIX_0,
 759   MOD_0F2B_PREFIX_1,
 760   MOD_0F2B_PREFIX_2,
 761   MOD_0F2B_PREFIX_3,
 762   MOD_0F51,
 763   MOD_0F71_REG_2,
 764   MOD_0F71_REG_4,
 765   MOD_0F71_REG_6,
 766   MOD_0F72_REG_2,
 767   MOD_0F72_REG_4,
 768   MOD_0F72_REG_6,
 769   MOD_0F73_REG_2,
 770   MOD_0F73_REG_3,
 771   MOD_0F73_REG_6,
 772   MOD_0F73_REG_7,
 773   MOD_0FAE_REG_0,
 774   MOD_0FAE_REG_1,
 775   MOD_0FAE_REG_2,
 776   MOD_0FAE_REG_3,
 777   MOD_0FAE_REG_4,
 778   MOD_0FAE_REG_5,
 779   MOD_0FAE_REG_6,
 780   MOD_0FAE_REG_7,
 781   MOD_0FB2,
 782   MOD_0FB4,
 783   MOD_0FB5,
 784   MOD_0FC7_REG_3,
 785   MOD_0FC7_REG_4,
 786   MOD_0FC7_REG_5,
 787   MOD_0FC7_REG_6,
 788   MOD_0FC7_REG_7,
 789   MOD_0FD7,
 790   MOD_0FE7_PREFIX_2,
 791   MOD_0FF0_PREFIX_3,
 792   MOD_0F382A_PREFIX_2,
 793   MOD_62_32BIT,
 794   MOD_C4_32BIT,
 795   MOD_C5_32BIT,
 796   MOD_VEX_0F12_PREFIX_0,
 797   MOD_VEX_0F13,
 798   MOD_VEX_0F16_PREFIX_0,
 799   MOD_VEX_0F17,
 800   MOD_VEX_0F2B,
 801   MOD_VEX_0F50,
 802   MOD_VEX_0F71_REG_2,
 803   MOD_VEX_0F71_REG_4,
 804   MOD_VEX_0F71_REG_6,
 805   MOD_VEX_0F72_REG_2,
 806   MOD_VEX_0F72_REG_4,
 807   MOD_VEX_0F72_REG_6,
 808   MOD_VEX_0F73_REG_2,
 809   MOD_VEX_0F73_REG_3,
 810   MOD_VEX_0F73_REG_6,
 811   MOD_VEX_0F73_REG_7,
 812   MOD_VEX_0FAE_REG_2,
 813   MOD_VEX_0FAE_REG_3,
 814   MOD_VEX_0FD7_PREFIX_2,
 815   MOD_VEX_0FE7_PREFIX_2,
 816   MOD_VEX_0FF0_PREFIX_3,
 817   MOD_VEX_0F381A_PREFIX_2,
 818   MOD_VEX_0F382A_PREFIX_2,
 819   MOD_VEX_0F382C_PREFIX_2,
 820   MOD_VEX_0F382D_PREFIX_2,
 821   MOD_VEX_0F382E_PREFIX_2,
 822   MOD_VEX_0F382F_PREFIX_2,
 823   MOD_VEX_0F385A_PREFIX_2,
 824   MOD_VEX_0F388C_PREFIX_2,
 825   MOD_VEX_0F388E_PREFIX_2,
 826
 827   MOD_EVEX_0F10_PREFIX_1,
 828   MOD_EVEX_0F10_PREFIX_3,
 829   MOD_EVEX_0F11_PREFIX_1,
 830   MOD_EVEX_0F11_PREFIX_3,
 831   MOD_EVEX_0F12_PREFIX_0,
 832   MOD_EVEX_0F16_PREFIX_0,
 833   MOD_EVEX_0F38C6_REG_1,
 834   MOD_EVEX_0F38C6_REG_2,
 835   MOD_EVEX_0F38C6_REG_5,
 836   MOD_EVEX_0F38C6_REG_6,
 837   MOD_EVEX_0F38C7_REG_1,
 838   MOD_EVEX_0F38C7_REG_2,
 839   MOD_EVEX_0F38C7_REG_5,
 840   MOD_EVEX_0F38C7_REG_6
 841 };
 842
 843 enum
 844 {
 845   RM_C6_REG_7 = 0,
 846   RM_C7_REG_7,
 847   RM_0F01_REG_0,
 848   RM_0F01_REG_1,
 849   RM_0F01_REG_2,
 850   RM_0F01_REG_3,
 851   RM_0F01_REG_7,
 852   RM_0FAE_REG_5,
 853   RM_0FAE_REG_6,
 854   RM_0FAE_REG_7
 855 };
 856
 857 enum
 858 {
 859   PREFIX_90 = 0,
 860   PREFIX_0F10,
 861   PREFIX_0F11,
 862   PREFIX_0F12,
 863   PREFIX_0F16,
 864   PREFIX_0F1A,
 865   PREFIX_0F1B,
 866   PREFIX_0F2A,
 867   PREFIX_0F2B,
 868   PREFIX_0F2C,
 869   PREFIX_0F2D,
 870   PREFIX_0F2E,
 871   PREFIX_0F2F,
 872   PREFIX_0F51,
 873   PREFIX_0F52,
 874   PREFIX_0F53,
 875   PREFIX_0F58,
 876   PREFIX_0F59,
 877   PREFIX_0F5A,
 878   PREFIX_0F5B,
 879   PREFIX_0F5C,
 880   PREFIX_0F5D,
 881   PREFIX_0F5E,
 882   PREFIX_0F5F,
 883   PREFIX_0F60,
 884   PREFIX_0F61,
 885   PREFIX_0F62,
 886   PREFIX_0F6C,
 887   PREFIX_0F6D,
 888   PREFIX_0F6F,
 889   PREFIX_0F70,
 890   PREFIX_0F73_REG_3,
 891   PREFIX_0F73_REG_7,
 892   PREFIX_0F78,
 893   PREFIX_0F79,
 894   PREFIX_0F7C,
 895   PREFIX_0F7D,
 896   PREFIX_0F7E,
 897   PREFIX_0F7F,
 898   PREFIX_0FAE_REG_0,
 899   PREFIX_0FAE_REG_1,
 900   PREFIX_0FAE_REG_2,
 901   PREFIX_0FAE_REG_3,
 902   PREFIX_0FAE_REG_6,
 903   PREFIX_0FAE_REG_7,
 904   PREFIX_RM_0_0FAE_REG_7,
 905   PREFIX_0FB8,
 906   PREFIX_0FBC,
 907   PREFIX_0FBD,
 908   PREFIX_0FC2,
 909   PREFIX_0FC3,
 910   PREFIX_0FC7_REG_6,
 911   PREFIX_0FD0,
 912   PREFIX_0FD6,
 913   PREFIX_0FE6,
 914   PREFIX_0FE7,
 915   PREFIX_0FF0,
 916   PREFIX_0FF7,
 917   PREFIX_0F3810,
 918   PREFIX_0F3814,
 919   PREFIX_0F3815,
 920   PREFIX_0F3817,
 921   PREFIX_0F3820,
 922   PREFIX_0F3821,
 923   PREFIX_0F3822,
 924   PREFIX_0F3823,
 925   PREFIX_0F3824,
 926   PREFIX_0F3825,
 927   PREFIX_0F3828,
 928   PREFIX_0F3829,
 929   PREFIX_0F382A,
 930   PREFIX_0F382B,
 931   PREFIX_0F3830,
 932   PREFIX_0F3831,
 933   PREFIX_0F3832,
 934   PREFIX_0F3833,
 935   PREFIX_0F3834,
 936   PREFIX_0F3835,
 937   PREFIX_0F3837,
 938   PREFIX_0F3838,
 939   PREFIX_0F3839,
 940   PREFIX_0F383A,
 941   PREFIX_0F383B,
 942   PREFIX_0F383C,
 943   PREFIX_0F383D,
 944   PREFIX_0F383E,
 945   PREFIX_0F383F,
 946   PREFIX_0F3840,
 947   PREFIX_0F3841,
 948   PREFIX_0F3880,
 949   PREFIX_0F3881,
 950   PREFIX_0F3882,
 951   PREFIX_0F38C8,
 952   PREFIX_0F38C9,
 953   PREFIX_0F38CA,
 954   PREFIX_0F38CB,
 955   PREFIX_0F38CC,
 956   PREFIX_0F38CD,
 957   PREFIX_0F38DB,
 958   PREFIX_0F38DC,
 959   PREFIX_0F38DD,
 960   PREFIX_0F38DE,
 961   PREFIX_0F38DF,
 962   PREFIX_0F38F0,
 963   PREFIX_0F38F1,
 964   PREFIX_0F38F6,
 965   PREFIX_0F3A08,
 966   PREFIX_0F3A09,
 967   PREFIX_0F3A0A,
 968   PREFIX_0F3A0B,
 969   PREFIX_0F3A0C,
 970   PREFIX_0F3A0D,
 971   PREFIX_0F3A0E,
 972   PREFIX_0F3A14,
 973   PREFIX_0F3A15,
 974   PREFIX_0F3A16,
 975   PREFIX_0F3A17,
 976   PREFIX_0F3A20,
 977   PREFIX_0F3A21,
 978   PREFIX_0F3A22,
 979   PREFIX_0F3A40,
 980   PREFIX_0F3A41,
 981   PREFIX_0F3A42,
 982   PREFIX_0F3A44,
 983   PREFIX_0F3A60,
 984   PREFIX_0F3A61,
 985   PREFIX_0F3A62,
 986   PREFIX_0F3A63,
 987   PREFIX_0F3ACC,
 988   PREFIX_0F3ADF,
 989   PREFIX_VEX_0F10,
 990   PREFIX_VEX_0F11,
 991   PREFIX_VEX_0F12,
 992   PREFIX_VEX_0F16,
 993   PREFIX_VEX_0F2A,
 994   PREFIX_VEX_0F2C,
 995   PREFIX_VEX_0F2D,
 996   PREFIX_VEX_0F2E,
 997   PREFIX_VEX_0F2F,
 998   PREFIX_VEX_0F41,
 999   PREFIX_VEX_0F42,
1000   PREFIX_VEX_0F44,
1001   PREFIX_VEX_0F45,
1002   PREFIX_VEX_0F46,
1003   PREFIX_VEX_0F47,
1004   PREFIX_VEX_0F4A,
1005   PREFIX_VEX_0F4B,
1006   PREFIX_VEX_0F51,
1007   PREFIX_VEX_0F52,
1008   PREFIX_VEX_0F53,
1009   PREFIX_VEX_0F58,
1010   PREFIX_VEX_0F59,
1011   PREFIX_VEX_0F5A,
1012   PREFIX_VEX_0F5B,
1013   PREFIX_VEX_0F5C,
1014   PREFIX_VEX_0F5D,
1015   PREFIX_VEX_0F5E,
1016   PREFIX_VEX_0F5F,
1017   PREFIX_VEX_0F60,
1018   PREFIX_VEX_0F61,
1019   PREFIX_VEX_0F62,
1020   PREFIX_VEX_0F63,
1021   PREFIX_VEX_0F64,
1022   PREFIX_VEX_0F65,
1023   PREFIX_VEX_0F66,
1024   PREFIX_VEX_0F67,
1025   PREFIX_VEX_0F68,
1026   PREFIX_VEX_0F69,
1027   PREFIX_VEX_0F6A,
1028   PREFIX_VEX_0F6B,
1029   PREFIX_VEX_0F6C,
1030   PREFIX_VEX_0F6D,
1031   PREFIX_VEX_0F6E,
1032   PREFIX_VEX_0F6F,
1033   PREFIX_VEX_0F70,
1034   PREFIX_VEX_0F71_REG_2,
1035   PREFIX_VEX_0F71_REG_4,
1036   PREFIX_VEX_0F71_REG_6,
1037   PREFIX_VEX_0F72_REG_2,
1038   PREFIX_VEX_0F72_REG_4,
1039   PREFIX_VEX_0F72_REG_6,
1040   PREFIX_VEX_0F73_REG_2,
1041   PREFIX_VEX_0F73_REG_3,
1042   PREFIX_VEX_0F73_REG_6,
1043   PREFIX_VEX_0F73_REG_7,
1044   PREFIX_VEX_0F74,
1045   PREFIX_VEX_0F75,
1046   PREFIX_VEX_0F76,
1047   PREFIX_VEX_0F77,
1048   PREFIX_VEX_0F7C,
1049   PREFIX_VEX_0F7D,
1050   PREFIX_VEX_0F7E,
1051   PREFIX_VEX_0F7F,
1052   PREFIX_VEX_0F90,
1053   PREFIX_VEX_0F91,
1054   PREFIX_VEX_0F92,
1055   PREFIX_VEX_0F93,
1056   PREFIX_VEX_0F98,
1057   PREFIX_VEX_0F99,
1058   PREFIX_VEX_0FC2,
1059   PREFIX_VEX_0FC4,
1060   PREFIX_VEX_0FC5,
1061   PREFIX_VEX_0FD0,
1062   PREFIX_VEX_0FD1,
1063   PREFIX_VEX_0FD2,
1064   PREFIX_VEX_0FD3,
1065   PREFIX_VEX_0FD4,
1066   PREFIX_VEX_0FD5,
1067   PREFIX_VEX_0FD6,
1068   PREFIX_VEX_0FD7,
1069   PREFIX_VEX_0FD8,
1070   PREFIX_VEX_0FD9,
1071   PREFIX_VEX_0FDA,
1072   PREFIX_VEX_0FDB,
1073   PREFIX_VEX_0FDC,
1074   PREFIX_VEX_0FDD,
1075   PREFIX_VEX_0FDE,
1076   PREFIX_VEX_0FDF,
1077   PREFIX_VEX_0FE0,
1078   PREFIX_VEX_0FE1,
1079   PREFIX_VEX_0FE2,
1080   PREFIX_VEX_0FE3,
1081   PREFIX_VEX_0FE4,
1082   PREFIX_VEX_0FE5,
1083   PREFIX_VEX_0FE6,
1084   PREFIX_VEX_0FE7,
1085   PREFIX_VEX_0FE8,
1086   PREFIX_VEX_0FE9,
1087   PREFIX_VEX_0FEA,
1088   PREFIX_VEX_0FEB,
1089   PREFIX_VEX_0FEC,
1090   PREFIX_VEX_0FED,
1091   PREFIX_VEX_0FEE,
1092   PREFIX_VEX_0FEF,
1093   PREFIX_VEX_0FF0,
1094   PREFIX_VEX_0FF1,
1095   PREFIX_VEX_0FF2,
1096   PREFIX_VEX_0FF3,
1097   PREFIX_VEX_0FF4,
1098   PREFIX_VEX_0FF5,
1099   PREFIX_VEX_0FF6,
1100   PREFIX_VEX_0FF7,
1101   PREFIX_VEX_0FF8,
1102   PREFIX_VEX_0FF9,
1103   PREFIX_VEX_0FFA,
1104   PREFIX_VEX_0FFB,
1105   PREFIX_VEX_0FFC,
1106   PREFIX_VEX_0FFD,
1107   PREFIX_VEX_0FFE,
1108   PREFIX_VEX_0F3800,
1109   PREFIX_VEX_0F3801,
1110   PREFIX_VEX_0F3802,
1111   PREFIX_VEX_0F3803,
1112   PREFIX_VEX_0F3804,
1113   PREFIX_VEX_0F3805,
1114   PREFIX_VEX_0F3806,
1115   PREFIX_VEX_0F3807,
1116   PREFIX_VEX_0F3808,
1117   PREFIX_VEX_0F3809,
1118   PREFIX_VEX_0F380A,
1119   PREFIX_VEX_0F380B,
1120   PREFIX_VEX_0F380C,
1121   PREFIX_VEX_0F380D,
1122   PREFIX_VEX_0F380E,
1123   PREFIX_VEX_0F380F,
1124   PREFIX_VEX_0F3813,
1125   PREFIX_VEX_0F3816,
1126   PREFIX_VEX_0F3817,
1127   PREFIX_VEX_0F3818,
1128   PREFIX_VEX_0F3819,
1129   PREFIX_VEX_0F381A,
1130   PREFIX_VEX_0F381C,
1131   PREFIX_VEX_0F381D,
1132   PREFIX_VEX_0F381E,
1133   PREFIX_VEX_0F3820,
1134   PREFIX_VEX_0F3821,
1135   PREFIX_VEX_0F3822,
1136   PREFIX_VEX_0F3823,
1137   PREFIX_VEX_0F3824,
1138   PREFIX_VEX_0F3825,
1139   PREFIX_VEX_0F3828,
1140   PREFIX_VEX_0F3829,
1141   PREFIX_VEX_0F382A,
1142   PREFIX_VEX_0F382B,
1143   PREFIX_VEX_0F382C,
1144   PREFIX_VEX_0F382D,
1145   PREFIX_VEX_0F382E,
1146   PREFIX_VEX_0F382F,
1147   PREFIX_VEX_0F3830,
1148   PREFIX_VEX_0F3831,
1149   PREFIX_VEX_0F3832,
1150   PREFIX_VEX_0F3833,
1151   PREFIX_VEX_0F3834,
1152   PREFIX_VEX_0F3835,
1153   PREFIX_VEX_0F3836,
1154   PREFIX_VEX_0F3837,
1155   PREFIX_VEX_0F3838,
1156   PREFIX_VEX_0F3839,
1157   PREFIX_VEX_0F383A,
1158   PREFIX_VEX_0F383B,
1159   PREFIX_VEX_0F383C,
1160   PREFIX_VEX_0F383D,
1161   PREFIX_VEX_0F383E,
1162   PREFIX_VEX_0F383F,
1163   PREFIX_VEX_0F3840,
1164   PREFIX_VEX_0F3841,
1165   PREFIX_VEX_0F3845,
1166   PREFIX_VEX_0F3846,
1167   PREFIX_VEX_0F3847,
1168   PREFIX_VEX_0F3858,
1169   PREFIX_VEX_0F3859,
1170   PREFIX_VEX_0F385A,
1171   PREFIX_VEX_0F3878,
1172   PREFIX_VEX_0F3879,
1173   PREFIX_VEX_0F388C,
1174   PREFIX_VEX_0F388E,
1175   PREFIX_VEX_0F3890,
1176   PREFIX_VEX_0F3891,
1177   PREFIX_VEX_0F3892,
1178   PREFIX_VEX_0F3893,
1179   PREFIX_VEX_0F3896,
1180   PREFIX_VEX_0F3897,
1181   PREFIX_VEX_0F3898,
1182   PREFIX_VEX_0F3899,
1183   PREFIX_VEX_0F389A,
1184   PREFIX_VEX_0F389B,
1185   PREFIX_VEX_0F389C,
1186   PREFIX_VEX_0F389D,
1187   PREFIX_VEX_0F389E,
1188   PREFIX_VEX_0F389F,
1189   PREFIX_VEX_0F38A6,
1190   PREFIX_VEX_0F38A7,
1191   PREFIX_VEX_0F38A8,
1192   PREFIX_VEX_0F38A9,
1193   PREFIX_VEX_0F38AA,
1194   PREFIX_VEX_0F38AB,
1195   PREFIX_VEX_0F38AC,
1196   PREFIX_VEX_0F38AD,
1197   PREFIX_VEX_0F38AE,
1198   PREFIX_VEX_0F38AF,
1199   PREFIX_VEX_0F38B6,
1200   PREFIX_VEX_0F38B7,
1201   PREFIX_VEX_0F38B8,
1202   PREFIX_VEX_0F38B9,
1203   PREFIX_VEX_0F38BA,
1204   PREFIX_VEX_0F38BB,
1205   PREFIX_VEX_0F38BC,
1206   PREFIX_VEX_0F38BD,
1207   PREFIX_VEX_0F38BE,
1208   PREFIX_VEX_0F38BF,
1209   PREFIX_VEX_0F38DB,
1210   PREFIX_VEX_0F38DC,
1211   PREFIX_VEX_0F38DD,
1212   PREFIX_VEX_0F38DE,
1213   PREFIX_VEX_0F38DF,
1214   PREFIX_VEX_0F38F2,
1215   PREFIX_VEX_0F38F3_REG_1,
1216   PREFIX_VEX_0F38F3_REG_2,
1217   PREFIX_VEX_0F38F3_REG_3,
1218   PREFIX_VEX_0F38F5,
1219   PREFIX_VEX_0F38F6,
1220   PREFIX_VEX_0F38F7,
1221   PREFIX_VEX_0F3A00,
1222   PREFIX_VEX_0F3A01,
1223   PREFIX_VEX_0F3A02,
1224   PREFIX_VEX_0F3A04,
1225   PREFIX_VEX_0F3A05,
1226   PREFIX_VEX_0F3A06,
1227   PREFIX_VEX_0F3A08,
1228   PREFIX_VEX_0F3A09,
1229   PREFIX_VEX_0F3A0A,
1230   PREFIX_VEX_0F3A0B,
1231   PREFIX_VEX_0F3A0C,
1232   PREFIX_VEX_0F3A0D,
1233   PREFIX_VEX_0F3A0E,
1234   PREFIX_VEX_0F3A0F,
1235   PREFIX_VEX_0F3A14,
1236   PREFIX_VEX_0F3A15,
1237   PREFIX_VEX_0F3A16,
1238   PREFIX_VEX_0F3A17,
1239   PREFIX_VEX_0F3A18,
1240   PREFIX_VEX_0F3A19,
1241   PREFIX_VEX_0F3A1D,
1242   PREFIX_VEX_0F3A20,
1243   PREFIX_VEX_0F3A21,
1244   PREFIX_VEX_0F3A22,
1245   PREFIX_VEX_0F3A30,
1246   PREFIX_VEX_0F3A31,
1247   PREFIX_VEX_0F3A32,
1248   PREFIX_VEX_0F3A33,
1249   PREFIX_VEX_0F3A38,
1250   PREFIX_VEX_0F3A39,
1251   PREFIX_VEX_0F3A40,
1252   PREFIX_VEX_0F3A41,
1253   PREFIX_VEX_0F3A42,
1254   PREFIX_VEX_0F3A44,
1255   PREFIX_VEX_0F3A46,
1256   PREFIX_VEX_0F3A48,
1257   PREFIX_VEX_0F3A49,
1258   PREFIX_VEX_0F3A4A,
1259   PREFIX_VEX_0F3A4B,
1260   PREFIX_VEX_0F3A4C,
1261   PREFIX_VEX_0F3A5C,
1262   PREFIX_VEX_0F3A5D,
1263   PREFIX_VEX_0F3A5E,
1264   PREFIX_VEX_0F3A5F,
1265   PREFIX_VEX_0F3A60,
1266   PREFIX_VEX_0F3A61,
1267   PREFIX_VEX_0F3A62,
1268   PREFIX_VEX_0F3A63,
1269   PREFIX_VEX_0F3A68,
1270   PREFIX_VEX_0F3A69,
1271   PREFIX_VEX_0F3A6A,
1272   PREFIX_VEX_0F3A6B,
1273   PREFIX_VEX_0F3A6C,
1274   PREFIX_VEX_0F3A6D,
1275   PREFIX_VEX_0F3A6E,
1276   PREFIX_VEX_0F3A6F,
1277   PREFIX_VEX_0F3A78,
1278   PREFIX_VEX_0F3A79,
1279   PREFIX_VEX_0F3A7A,
1280   PREFIX_VEX_0F3A7B,
1281   PREFIX_VEX_0F3A7C,
1282   PREFIX_VEX_0F3A7D,
1283   PREFIX_VEX_0F3A7E,
1284   PREFIX_VEX_0F3A7F,
1285   PREFIX_VEX_0F3ADF,
1286   PREFIX_VEX_0F3AF0,
1287
1288   PREFIX_EVEX_0F10,
1289   PREFIX_EVEX_0F11,
1290   PREFIX_EVEX_0F12,
1291   PREFIX_EVEX_0F13,
1292   PREFIX_EVEX_0F14,
1293   PREFIX_EVEX_0F15,
1294   PREFIX_EVEX_0F16,
1295   PREFIX_EVEX_0F17,
1296   PREFIX_EVEX_0F28,
1297   PREFIX_EVEX_0F29,
1298   PREFIX_EVEX_0F2A,
1299   PREFIX_EVEX_0F2B,
1300   PREFIX_EVEX_0F2C,
1301   PREFIX_EVEX_0F2D,
1302   PREFIX_EVEX_0F2E,
1303   PREFIX_EVEX_0F2F,
1304   PREFIX_EVEX_0F51,
1305   PREFIX_EVEX_0F54,
1306   PREFIX_EVEX_0F55,
1307   PREFIX_EVEX_0F56,
1308   PREFIX_EVEX_0F57,
1309   PREFIX_EVEX_0F58,
1310   PREFIX_EVEX_0F59,
1311   PREFIX_EVEX_0F5A,
1312   PREFIX_EVEX_0F5B,
1313   PREFIX_EVEX_0F5C,
1314   PREFIX_EVEX_0F5D,
1315   PREFIX_EVEX_0F5E,
1316   PREFIX_EVEX_0F5F,
1317   PREFIX_EVEX_0F60,
1318   PREFIX_EVEX_0F61,
1319   PREFIX_EVEX_0F62,
1320   PREFIX_EVEX_0F63,
1321   PREFIX_EVEX_0F64,
1322   PREFIX_EVEX_0F65,
1323   PREFIX_EVEX_0F66,
1324   PREFIX_EVEX_0F67,
1325   PREFIX_EVEX_0F68,
1326   PREFIX_EVEX_0F69,
1327   PREFIX_EVEX_0F6A,
1328   PREFIX_EVEX_0F6B,
1329   PREFIX_EVEX_0F6C,
1330   PREFIX_EVEX_0F6D,
1331   PREFIX_EVEX_0F6E,
1332   PREFIX_EVEX_0F6F,
1333   PREFIX_EVEX_0F70,
1334   PREFIX_EVEX_0F71_REG_2,
1335   PREFIX_EVEX_0F71_REG_4,
1336   PREFIX_EVEX_0F71_REG_6,
1337   PREFIX_EVEX_0F72_REG_0,
1338   PREFIX_EVEX_0F72_REG_1,
1339   PREFIX_EVEX_0F72_REG_2,
1340   PREFIX_EVEX_0F72_REG_4,
1341   PREFIX_EVEX_0F72_REG_6,
1342   PREFIX_EVEX_0F73_REG_2,
1343   PREFIX_EVEX_0F73_REG_3,
1344   PREFIX_EVEX_0F73_REG_6,
1345   PREFIX_EVEX_0F73_REG_7,
1346   PREFIX_EVEX_0F74,
1347   PREFIX_EVEX_0F75,
1348   PREFIX_EVEX_0F76,
1349   PREFIX_EVEX_0F78,
1350   PREFIX_EVEX_0F79,
1351   PREFIX_EVEX_0F7A,
1352   PREFIX_EVEX_0F7B,
1353   PREFIX_EVEX_0F7E,
1354   PREFIX_EVEX_0F7F,
1355   PREFIX_EVEX_0FC2,
1356   PREFIX_EVEX_0FC4,
1357   PREFIX_EVEX_0FC5,
1358   PREFIX_EVEX_0FC6,
1359   PREFIX_EVEX_0FD1,
1360   PREFIX_EVEX_0FD2,
1361   PREFIX_EVEX_0FD3,
1362   PREFIX_EVEX_0FD4,
1363   PREFIX_EVEX_0FD5,
1364   PREFIX_EVEX_0FD6,
1365   PREFIX_EVEX_0FD8,
1366   PREFIX_EVEX_0FD9,
1367   PREFIX_EVEX_0FDA,
1368   PREFIX_EVEX_0FDB,
1369   PREFIX_EVEX_0FDC,
1370   PREFIX_EVEX_0FDD,
1371   PREFIX_EVEX_0FDE,
1372   PREFIX_EVEX_0FDF,
1373   PREFIX_EVEX_0FE0,
1374   PREFIX_EVEX_0FE1,
1375   PREFIX_EVEX_0FE2,
1376   PREFIX_EVEX_0FE3,
1377   PREFIX_EVEX_0FE4,
1378   PREFIX_EVEX_0FE5,
1379   PREFIX_EVEX_0FE6,
1380   PREFIX_EVEX_0FE7,
1381   PREFIX_EVEX_0FE8,
1382   PREFIX_EVEX_0FE9,
1383   PREFIX_EVEX_0FEA,
1384   PREFIX_EVEX_0FEB,
1385   PREFIX_EVEX_0FEC,
1386   PREFIX_EVEX_0FED,
1387   PREFIX_EVEX_0FEE,
1388   PREFIX_EVEX_0FEF,
1389   PREFIX_EVEX_0FF1,
1390   PREFIX_EVEX_0FF2,
1391   PREFIX_EVEX_0FF3,
1392   PREFIX_EVEX_0FF4,
1393   PREFIX_EVEX_0FF5,
1394   PREFIX_EVEX_0FF6,
1395   PREFIX_EVEX_0FF8,
1396   PREFIX_EVEX_0FF9,
1397   PREFIX_EVEX_0FFA,
1398   PREFIX_EVEX_0FFB,
1399   PREFIX_EVEX_0FFC,
1400   PREFIX_EVEX_0FFD,
1401   PREFIX_EVEX_0FFE,
1402   PREFIX_EVEX_0F3800,
1403   PREFIX_EVEX_0F3804,
1404   PREFIX_EVEX_0F380B,
1405   PREFIX_EVEX_0F380C,
1406   PREFIX_EVEX_0F380D,
1407   PREFIX_EVEX_0F3810,
1408   PREFIX_EVEX_0F3811,
1409   PREFIX_EVEX_0F3812,
1410   PREFIX_EVEX_0F3813,
1411   PREFIX_EVEX_0F3814,
1412   PREFIX_EVEX_0F3815,
1413   PREFIX_EVEX_0F3816,
1414   PREFIX_EVEX_0F3818,
1415   PREFIX_EVEX_0F3819,
1416   PREFIX_EVEX_0F381A,
1417   PREFIX_EVEX_0F381B,
1418   PREFIX_EVEX_0F381C,
1419   PREFIX_EVEX_0F381D,
1420   PREFIX_EVEX_0F381E,
1421   PREFIX_EVEX_0F381F,
1422   PREFIX_EVEX_0F3820,
1423   PREFIX_EVEX_0F3821,
1424   PREFIX_EVEX_0F3822,
1425   PREFIX_EVEX_0F3823,
1426   PREFIX_EVEX_0F3824,
1427   PREFIX_EVEX_0F3825,
1428   PREFIX_EVEX_0F3826,
1429   PREFIX_EVEX_0F3827,
1430   PREFIX_EVEX_0F3828,
1431   PREFIX_EVEX_0F3829,
1432   PREFIX_EVEX_0F382A,
1433   PREFIX_EVEX_0F382B,
1434   PREFIX_EVEX_0F382C,
1435   PREFIX_EVEX_0F382D,
1436   PREFIX_EVEX_0F3830,
1437   PREFIX_EVEX_0F3831,
1438   PREFIX_EVEX_0F3832,
1439   PREFIX_EVEX_0F3833,
1440   PREFIX_EVEX_0F3834,
1441   PREFIX_EVEX_0F3835,
1442   PREFIX_EVEX_0F3836,
1443   PREFIX_EVEX_0F3837,
1444   PREFIX_EVEX_0F3838,
1445   PREFIX_EVEX_0F3839,
1446   PREFIX_EVEX_0F383A,
1447   PREFIX_EVEX_0F383B,
1448   PREFIX_EVEX_0F383C,
1449   PREFIX_EVEX_0F383D,
1450   PREFIX_EVEX_0F383E,
1451   PREFIX_EVEX_0F383F,
1452   PREFIX_EVEX_0F3840,
1453   PREFIX_EVEX_0F3842,
1454   PREFIX_EVEX_0F3843,
1455   PREFIX_EVEX_0F3844,
1456   PREFIX_EVEX_0F3845,
1457   PREFIX_EVEX_0F3846,
1458   PREFIX_EVEX_0F3847,
1459   PREFIX_EVEX_0F384C,
1460   PREFIX_EVEX_0F384D,
1461   PREFIX_EVEX_0F384E,
1462   PREFIX_EVEX_0F384F,
1463   PREFIX_EVEX_0F3858,
1464   PREFIX_EVEX_0F3859,
1465   PREFIX_EVEX_0F385A,
1466   PREFIX_EVEX_0F385B,
1467   PREFIX_EVEX_0F3864,
1468   PREFIX_EVEX_0F3865,
1469   PREFIX_EVEX_0F3866,
1470   PREFIX_EVEX_0F3875,
1471   PREFIX_EVEX_0F3876,
1472   PREFIX_EVEX_0F3877,
1473   PREFIX_EVEX_0F3878,
1474   PREFIX_EVEX_0F3879,
1475   PREFIX_EVEX_0F387A,
1476   PREFIX_EVEX_0F387B,
1477   PREFIX_EVEX_0F387C,
1478   PREFIX_EVEX_0F387D,
1479   PREFIX_EVEX_0F387E,
1480   PREFIX_EVEX_0F387F,
1481   PREFIX_EVEX_0F3888,
1482   PREFIX_EVEX_0F3889,
1483   PREFIX_EVEX_0F388A,
1484   PREFIX_EVEX_0F388B,
1485   PREFIX_EVEX_0F388D,
1486   PREFIX_EVEX_0F3890,
1487   PREFIX_EVEX_0F3891,
1488   PREFIX_EVEX_0F3892,
1489   PREFIX_EVEX_0F3893,
1490   PREFIX_EVEX_0F3896,
1491   PREFIX_EVEX_0F3897,
1492   PREFIX_EVEX_0F3898,
1493   PREFIX_EVEX_0F3899,
1494   PREFIX_EVEX_0F389A,
1495   PREFIX_EVEX_0F389B,
1496   PREFIX_EVEX_0F389C,
1497   PREFIX_EVEX_0F389D,
1498   PREFIX_EVEX_0F389E,
1499   PREFIX_EVEX_0F389F,
1500   PREFIX_EVEX_0F38A0,
1501   PREFIX_EVEX_0F38A1,
1502   PREFIX_EVEX_0F38A2,
1503   PREFIX_EVEX_0F38A3,
1504   PREFIX_EVEX_0F38A6,
1505   PREFIX_EVEX_0F38A7,
1506   PREFIX_EVEX_0F38A8,
1507   PREFIX_EVEX_0F38A9,
1508   PREFIX_EVEX_0F38AA,
1509   PREFIX_EVEX_0F38AB,
1510   PREFIX_EVEX_0F38AC,
1511   PREFIX_EVEX_0F38AD,
1512   PREFIX_EVEX_0F38AE,
1513   PREFIX_EVEX_0F38AF,
1514   PREFIX_EVEX_0F38B4,
1515   PREFIX_EVEX_0F38B5,
1516   PREFIX_EVEX_0F38B6,
1517   PREFIX_EVEX_0F38B7,
1518   PREFIX_EVEX_0F38B8,
1519   PREFIX_EVEX_0F38B9,
1520   PREFIX_EVEX_0F38BA,
1521   PREFIX_EVEX_0F38BB,
1522   PREFIX_EVEX_0F38BC,
1523   PREFIX_EVEX_0F38BD,
1524   PREFIX_EVEX_0F38BE,
1525   PREFIX_EVEX_0F38BF,
1526   PREFIX_EVEX_0F38C4,
1527   PREFIX_EVEX_0F38C6_REG_1,
1528   PREFIX_EVEX_0F38C6_REG_2,
1529   PREFIX_EVEX_0F38C6_REG_5,
1530   PREFIX_EVEX_0F38C6_REG_6,
1531   PREFIX_EVEX_0F38C7_REG_1,
1532   PREFIX_EVEX_0F38C7_REG_2,
1533   PREFIX_EVEX_0F38C7_REG_5,
1534   PREFIX_EVEX_0F38C7_REG_6,
1535   PREFIX_EVEX_0F38C8,
1536   PREFIX_EVEX_0F38CA,
1537   PREFIX_EVEX_0F38CB,
1538   PREFIX_EVEX_0F38CC,
1539   PREFIX_EVEX_0F38CD,
1540
1541   PREFIX_EVEX_0F3A00,
1542   PREFIX_EVEX_0F3A01,
1543   PREFIX_EVEX_0F3A03,
1544   PREFIX_EVEX_0F3A04,
1545   PREFIX_EVEX_0F3A05,
1546   PREFIX_EVEX_0F3A08,
1547   PREFIX_EVEX_0F3A09,
1548   PREFIX_EVEX_0F3A0A,
1549   PREFIX_EVEX_0F3A0B,
1550   PREFIX_EVEX_0F3A0F,
1551   PREFIX_EVEX_0F3A14,
1552   PREFIX_EVEX_0F3A15,
1553   PREFIX_EVEX_0F3A16,
1554   PREFIX_EVEX_0F3A17,
1555   PREFIX_EVEX_0F3A18,
1556   PREFIX_EVEX_0F3A19,
1557   PREFIX_EVEX_0F3A1A,
1558   PREFIX_EVEX_0F3A1B,
1559   PREFIX_EVEX_0F3A1D,
1560   PREFIX_EVEX_0F3A1E,
1561   PREFIX_EVEX_0F3A1F,
1562   PREFIX_EVEX_0F3A20,
1563   PREFIX_EVEX_0F3A21,
1564   PREFIX_EVEX_0F3A22,
1565   PREFIX_EVEX_0F3A23,
1566   PREFIX_EVEX_0F3A25,
1567   PREFIX_EVEX_0F3A26,
1568   PREFIX_EVEX_0F3A27,
1569   PREFIX_EVEX_0F3A38,
1570   PREFIX_EVEX_0F3A39,
1571   PREFIX_EVEX_0F3A3A,
1572   PREFIX_EVEX_0F3A3B,
1573   PREFIX_EVEX_0F3A3E,
1574   PREFIX_EVEX_0F3A3F,
1575   PREFIX_EVEX_0F3A42,
1576   PREFIX_EVEX_0F3A43,
1577   PREFIX_EVEX_0F3A50,
1578   PREFIX_EVEX_0F3A51,
1579   PREFIX_EVEX_0F3A54,
1580   PREFIX_EVEX_0F3A55,
1581   PREFIX_EVEX_0F3A56,
1582   PREFIX_EVEX_0F3A57,
1583   PREFIX_EVEX_0F3A66,
1584   PREFIX_EVEX_0F3A67
1585 };
1586
1587 enum
1588 {
1589   X86_64_06 = 0,
1590   X86_64_07,
1591   X86_64_0D,
1592   X86_64_16,
1593   X86_64_17,
1594   X86_64_1E,
1595   X86_64_1F,
1596   X86_64_27,
1597   X86_64_2F,
1598   X86_64_37,
1599   X86_64_3F,
1600   X86_64_60,
1601   X86_64_61,
1602   X86_64_62,
1603   X86_64_63,
1604   X86_64_6D,
1605   X86_64_6F,
1606   X86_64_9A,
1607   X86_64_C4,
1608   X86_64_C5,
1609   X86_64_CE,
1610   X86_64_D4,
1611   X86_64_D5,
1612   X86_64_EA,
1613   X86_64_0F01_REG_0,
1614   X86_64_0F01_REG_1,
1615   X86_64_0F01_REG_2,
1616   X86_64_0F01_REG_3
1617 };
1618
1619 enum
1620 {
1621   THREE_BYTE_0F38 = 0,
1622   THREE_BYTE_0F3A,
1623   THREE_BYTE_0F7A
1624 };
1625
1626 enum
1627 {
1628   XOP_08 = 0,
1629   XOP_09,
1630   XOP_0A
1631 };
1632
1633 enum
1634 {
1635   VEX_0F = 0,
1636   VEX_0F38,
1637   VEX_0F3A
1638 };
1639
1640 enum
1641 {
1642   EVEX_0F = 0,
1643   EVEX_0F38,
1644   EVEX_0F3A
1645 };
1646
1647 enum
1648 {
1649   VEX_LEN_0F10_P_1 = 0,
1650   VEX_LEN_0F10_P_3,
1651   VEX_LEN_0F11_P_1,
1652   VEX_LEN_0F11_P_3,
1653   VEX_LEN_0F12_P_0_M_0,
1654   VEX_LEN_0F12_P_0_M_1,
1655   VEX_LEN_0F12_P_2,
1656   VEX_LEN_0F13_M_0,
1657   VEX_LEN_0F16_P_0_M_0,
1658   VEX_LEN_0F16_P_0_M_1,
1659   VEX_LEN_0F16_P_2,
1660   VEX_LEN_0F17_M_0,
1661   VEX_LEN_0F2A_P_1,
1662   VEX_LEN_0F2A_P_3,
1663   VEX_LEN_0F2C_P_1,
1664   VEX_LEN_0F2C_P_3,
1665   VEX_LEN_0F2D_P_1,
1666   VEX_LEN_0F2D_P_3,
1667   VEX_LEN_0F2E_P_0,
1668   VEX_LEN_0F2E_P_2,
1669   VEX_LEN_0F2F_P_0,
1670   VEX_LEN_0F2F_P_2,
1671   VEX_LEN_0F41_P_0,
1672   VEX_LEN_0F41_P_2,
1673   VEX_LEN_0F42_P_0,
1674   VEX_LEN_0F42_P_2,
1675   VEX_LEN_0F44_P_0,
1676   VEX_LEN_0F44_P_2,
1677   VEX_LEN_0F45_P_0,
1678   VEX_LEN_0F45_P_2,
1679   VEX_LEN_0F46_P_0,
1680   VEX_LEN_0F46_P_2,
1681   VEX_LEN_0F47_P_0,
1682   VEX_LEN_0F47_P_2,
1683   VEX_LEN_0F4A_P_0,
1684   VEX_LEN_0F4A_P_2,
1685   VEX_LEN_0F4B_P_0,
1686   VEX_LEN_0F4B_P_2,
1687   VEX_LEN_0F51_P_1,
1688   VEX_LEN_0F51_P_3,
1689   VEX_LEN_0F52_P_1,
1690   VEX_LEN_0F53_P_1,
1691   VEX_LEN_0F58_P_1,
1692   VEX_LEN_0F58_P_3,
1693   VEX_LEN_0F59_P_1,
1694   VEX_LEN_0F59_P_3,
1695   VEX_LEN_0F5A_P_1,
1696   VEX_LEN_0F5A_P_3,
1697   VEX_LEN_0F5C_P_1,
1698   VEX_LEN_0F5C_P_3,
1699   VEX_LEN_0F5D_P_1,
1700   VEX_LEN_0F5D_P_3,
1701   VEX_LEN_0F5E_P_1,
1702   VEX_LEN_0F5E_P_3,
1703   VEX_LEN_0F5F_P_1,
1704   VEX_LEN_0F5F_P_3,
1705   VEX_LEN_0F6E_P_2,
1706   VEX_LEN_0F7E_P_1,
1707   VEX_LEN_0F7E_P_2,
1708   VEX_LEN_0F90_P_0,
1709   VEX_LEN_0F90_P_2,
1710   VEX_LEN_0F91_P_0,
1711   VEX_LEN_0F91_P_2,
1712   VEX_LEN_0F92_P_0,
1713   VEX_LEN_0F92_P_2,
1714   VEX_LEN_0F92_P_3,
1715   VEX_LEN_0F93_P_0,
1716   VEX_LEN_0F93_P_2,
1717   VEX_LEN_0F93_P_3,
1718   VEX_LEN_0F98_P_0,
1719   VEX_LEN_0F98_P_2,
1720   VEX_LEN_0F99_P_0,
1721   VEX_LEN_0F99_P_2,
1722   VEX_LEN_0FAE_R_2_M_0,
1723   VEX_LEN_0FAE_R_3_M_0,
1724   VEX_LEN_0FC2_P_1,
1725   VEX_LEN_0FC2_P_3,
1726   VEX_LEN_0FC4_P_2,
1727   VEX_LEN_0FC5_P_2,
1728   VEX_LEN_0FD6_P_2,
1729   VEX_LEN_0FF7_P_2,
1730   VEX_LEN_0F3816_P_2,
1731   VEX_LEN_0F3819_P_2,
1732   VEX_LEN_0F381A_P_2_M_0,
1733   VEX_LEN_0F3836_P_2,
1734   VEX_LEN_0F3841_P_2,
1735   VEX_LEN_0F385A_P_2_M_0,
1736   VEX_LEN_0F38DB_P_2,
1737   VEX_LEN_0F38DC_P_2,
1738   VEX_LEN_0F38DD_P_2,
1739   VEX_LEN_0F38DE_P_2,
1740   VEX_LEN_0F38DF_P_2,
1741   VEX_LEN_0F38F2_P_0,
1742   VEX_LEN_0F38F3_R_1_P_0,
1743   VEX_LEN_0F38F3_R_2_P_0,
1744   VEX_LEN_0F38F3_R_3_P_0,
1745   VEX_LEN_0F38F5_P_0,
1746   VEX_LEN_0F38F5_P_1,
1747   VEX_LEN_0F38F5_P_3,
1748   VEX_LEN_0F38F6_P_3,
1749   VEX_LEN_0F38F7_P_0,
1750   VEX_LEN_0F38F7_P_1,
1751   VEX_LEN_0F38F7_P_2,
1752   VEX_LEN_0F38F7_P_3,
1753   VEX_LEN_0F3A00_P_2,
1754   VEX_LEN_0F3A01_P_2,
1755   VEX_LEN_0F3A06_P_2,
1756   VEX_LEN_0F3A0A_P_2,
1757   VEX_LEN_0F3A0B_P_2,
1758   VEX_LEN_0F3A14_P_2,
1759   VEX_LEN_0F3A15_P_2,
1760   VEX_LEN_0F3A16_P_2,
1761   VEX_LEN_0F3A17_P_2,
1762   VEX_LEN_0F3A18_P_2,
1763   VEX_LEN_0F3A19_P_2,
1764   VEX_LEN_0F3A20_P_2,
1765   VEX_LEN_0F3A21_P_2,
1766   VEX_LEN_0F3A22_P_2,
1767   VEX_LEN_0F3A30_P_2,
1768   VEX_LEN_0F3A31_P_2,
1769   VEX_LEN_0F3A32_P_2,
1770   VEX_LEN_0F3A33_P_2,
1771   VEX_LEN_0F3A38_P_2,
1772   VEX_LEN_0F3A39_P_2,
1773   VEX_LEN_0F3A41_P_2,
1774   VEX_LEN_0F3A44_P_2,
1775   VEX_LEN_0F3A46_P_2,
1776   VEX_LEN_0F3A60_P_2,
1777   VEX_LEN_0F3A61_P_2,
1778   VEX_LEN_0F3A62_P_2,
1779   VEX_LEN_0F3A63_P_2,
1780   VEX_LEN_0F3A6A_P_2,
1781   VEX_LEN_0F3A6B_P_2,
1782   VEX_LEN_0F3A6E_P_2,
1783   VEX_LEN_0F3A6F_P_2,
1784   VEX_LEN_0F3A7A_P_2,
1785   VEX_LEN_0F3A7B_P_2,
1786   VEX_LEN_0F3A7E_P_2,
1787   VEX_LEN_0F3A7F_P_2,
1788   VEX_LEN_0F3ADF_P_2,
1789   VEX_LEN_0F3AF0_P_3,
1790   VEX_LEN_0FXOP_08_CC,
1791   VEX_LEN_0FXOP_08_CD,
1792   VEX_LEN_0FXOP_08_CE,
1793   VEX_LEN_0FXOP_08_CF,
1794   VEX_LEN_0FXOP_08_EC,
1795   VEX_LEN_0FXOP_08_ED,
1796   VEX_LEN_0FXOP_08_EE,
1797   VEX_LEN_0FXOP_08_EF,
1798   VEX_LEN_0FXOP_09_80,
1799   VEX_LEN_0FXOP_09_81
1800 };
1801
1802 enum
1803 {
1804   VEX_W_0F10_P_0 = 0,
1805   VEX_W_0F10_P_1,
1806   VEX_W_0F10_P_2,
1807   VEX_W_0F10_P_3,
1808   VEX_W_0F11_P_0,
1809   VEX_W_0F11_P_1,
1810   VEX_W_0F11_P_2,
1811   VEX_W_0F11_P_3,
1812   VEX_W_0F12_P_0_M_0,
1813   VEX_W_0F12_P_0_M_1,
1814   VEX_W_0F12_P_1,
1815   VEX_W_0F12_P_2,
1816   VEX_W_0F12_P_3,
1817   VEX_W_0F13_M_0,
1818   VEX_W_0F14,
1819   VEX_W_0F15,
1820   VEX_W_0F16_P_0_M_0,
1821   VEX_W_0F16_P_0_M_1,
1822   VEX_W_0F16_P_1,
1823   VEX_W_0F16_P_2,
1824   VEX_W_0F17_M_0,
1825   VEX_W_0F28,
1826   VEX_W_0F29,
1827   VEX_W_0F2B_M_0,
1828   VEX_W_0F2E_P_0,
1829   VEX_W_0F2E_P_2,
1830   VEX_W_0F2F_P_0,
1831   VEX_W_0F2F_P_2,
1832   VEX_W_0F41_P_0_LEN_1,
1833   VEX_W_0F41_P_2_LEN_1,
1834   VEX_W_0F42_P_0_LEN_1,
1835   VEX_W_0F42_P_2_LEN_1,
1836   VEX_W_0F44_P_0_LEN_0,
1837   VEX_W_0F44_P_2_LEN_0,
1838   VEX_W_0F45_P_0_LEN_1,
1839   VEX_W_0F45_P_2_LEN_1,
1840   VEX_W_0F46_P_0_LEN_1,
1841   VEX_W_0F46_P_2_LEN_1,
1842   VEX_W_0F47_P_0_LEN_1,
1843   VEX_W_0F47_P_2_LEN_1,
1844   VEX_W_0F4A_P_0_LEN_1,
1845   VEX_W_0F4A_P_2_LEN_1,
1846   VEX_W_0F4B_P_0_LEN_1,
1847   VEX_W_0F4B_P_2_LEN_1,
1848   VEX_W_0F50_M_0,
1849   VEX_W_0F51_P_0,
1850   VEX_W_0F51_P_1,
1851   VEX_W_0F51_P_2,
1852   VEX_W_0F51_P_3,
1853   VEX_W_0F52_P_0,
1854   VEX_W_0F52_P_1,
1855   VEX_W_0F53_P_0,
1856   VEX_W_0F53_P_1,
1857   VEX_W_0F58_P_0,
1858   VEX_W_0F58_P_1,
1859   VEX_W_0F58_P_2,
1860   VEX_W_0F58_P_3,
1861   VEX_W_0F59_P_0,
1862   VEX_W_0F59_P_1,
1863   VEX_W_0F59_P_2,
1864   VEX_W_0F59_P_3,
1865   VEX_W_0F5A_P_0,
1866   VEX_W_0F5A_P_1,
1867   VEX_W_0F5A_P_3,
1868   VEX_W_0F5B_P_0,
1869   VEX_W_0F5B_P_1,
1870   VEX_W_0F5B_P_2,
1871   VEX_W_0F5C_P_0,
1872   VEX_W_0F5C_P_1,
1873   VEX_W_0F5C_P_2,
1874   VEX_W_0F5C_P_3,
1875   VEX_W_0F5D_P_0,
1876   VEX_W_0F5D_P_1,
1877   VEX_W_0F5D_P_2,
1878   VEX_W_0F5D_P_3,
1879   VEX_W_0F5E_P_0,
1880   VEX_W_0F5E_P_1,
1881   VEX_W_0F5E_P_2,
1882   VEX_W_0F5E_P_3,
1883   VEX_W_0F5F_P_0,
1884   VEX_W_0F5F_P_1,
1885   VEX_W_0F5F_P_2,
1886   VEX_W_0F5F_P_3,
1887   VEX_W_0F60_P_2,
1888   VEX_W_0F61_P_2,
1889   VEX_W_0F62_P_2,
1890   VEX_W_0F63_P_2,
1891   VEX_W_0F64_P_2,
1892   VEX_W_0F65_P_2,
1893   VEX_W_0F66_P_2,
1894   VEX_W_0F67_P_2,
1895   VEX_W_0F68_P_2,
1896   VEX_W_0F69_P_2,
1897   VEX_W_0F6A_P_2,
1898   VEX_W_0F6B_P_2,
1899   VEX_W_0F6C_P_2,
1900   VEX_W_0F6D_P_2,
1901   VEX_W_0F6F_P_1,
1902   VEX_W_0F6F_P_2,
1903   VEX_W_0F70_P_1,
1904   VEX_W_0F70_P_2,
1905   VEX_W_0F70_P_3,
1906   VEX_W_0F71_R_2_P_2,
1907   VEX_W_0F71_R_4_P_2,
1908   VEX_W_0F71_R_6_P_2,
1909   VEX_W_0F72_R_2_P_2,
1910   VEX_W_0F72_R_4_P_2,
1911   VEX_W_0F72_R_6_P_2,
1912   VEX_W_0F73_R_2_P_2,
1913   VEX_W_0F73_R_3_P_2,
1914   VEX_W_0F73_R_6_P_2,
1915   VEX_W_0F73_R_7_P_2,
1916   VEX_W_0F74_P_2,
1917   VEX_W_0F75_P_2,
1918   VEX_W_0F76_P_2,
1919   VEX_W_0F77_P_0,
1920   VEX_W_0F7C_P_2,
1921   VEX_W_0F7C_P_3,
1922   VEX_W_0F7D_P_2,
1923   VEX_W_0F7D_P_3,
1924   VEX_W_0F7E_P_1,
1925   VEX_W_0F7F_P_1,
1926   VEX_W_0F7F_P_2,
1927   VEX_W_0F90_P_0_LEN_0,
1928   VEX_W_0F90_P_2_LEN_0,
1929   VEX_W_0F91_P_0_LEN_0,
1930   VEX_W_0F91_P_2_LEN_0,
1931   VEX_W_0F92_P_0_LEN_0,
1932   VEX_W_0F92_P_2_LEN_0,
1933   VEX_W_0F92_P_3_LEN_0,
1934   VEX_W_0F93_P_0_LEN_0,
1935   VEX_W_0F93_P_2_LEN_0,
1936   VEX_W_0F93_P_3_LEN_0,
1937   VEX_W_0F98_P_0_LEN_0,
1938   VEX_W_0F98_P_2_LEN_0,
1939   VEX_W_0F99_P_0_LEN_0,
1940   VEX_W_0F99_P_2_LEN_0,
1941   VEX_W_0FAE_R_2_M_0,
1942   VEX_W_0FAE_R_3_M_0,
1943   VEX_W_0FC2_P_0,
1944   VEX_W_0FC2_P_1,
1945   VEX_W_0FC2_P_2,
1946   VEX_W_0FC2_P_3,
1947   VEX_W_0FC4_P_2,
1948   VEX_W_0FC5_P_2,
1949   VEX_W_0FD0_P_2,
1950   VEX_W_0FD0_P_3,
1951   VEX_W_0FD1_P_2,
1952   VEX_W_0FD2_P_2,
1953   VEX_W_0FD3_P_2,
1954   VEX_W_0FD4_P_2,
1955   VEX_W_0FD5_P_2,
1956   VEX_W_0FD6_P_2,
1957   VEX_W_0FD7_P_2_M_1,
1958   VEX_W_0FD8_P_2,
1959   VEX_W_0FD9_P_2,
1960   VEX_W_0FDA_P_2,
1961   VEX_W_0FDB_P_2,
1962   VEX_W_0FDC_P_2,
1963   VEX_W_0FDD_P_2,
1964   VEX_W_0FDE_P_2,
1965   VEX_W_0FDF_P_2,
1966   VEX_W_0FE0_P_2,
1967   VEX_W_0FE1_P_2,
1968   VEX_W_0FE2_P_2,
1969   VEX_W_0FE3_P_2,
1970   VEX_W_0FE4_P_2,
1971   VEX_W_0FE5_P_2,
1972   VEX_W_0FE6_P_1,
1973   VEX_W_0FE6_P_2,
1974   VEX_W_0FE6_P_3,
1975   VEX_W_0FE7_P_2_M_0,
1976   VEX_W_0FE8_P_2,
1977   VEX_W_0FE9_P_2,
1978   VEX_W_0FEA_P_2,
1979   VEX_W_0FEB_P_2,
1980   VEX_W_0FEC_P_2,
1981   VEX_W_0FED_P_2,
1982   VEX_W_0FEE_P_2,
1983   VEX_W_0FEF_P_2,
1984   VEX_W_0FF0_P_3_M_0,
1985   VEX_W_0FF1_P_2,
1986   VEX_W_0FF2_P_2,
1987   VEX_W_0FF3_P_2,
1988   VEX_W_0FF4_P_2,
1989   VEX_W_0FF5_P_2,
1990   VEX_W_0FF6_P_2,
1991   VEX_W_0FF7_P_2,
1992   VEX_W_0FF8_P_2,
1993   VEX_W_0FF9_P_2,
1994   VEX_W_0FFA_P_2,
1995   VEX_W_0FFB_P_2,
1996   VEX_W_0FFC_P_2,
1997   VEX_W_0FFD_P_2,
1998   VEX_W_0FFE_P_2,
1999   VEX_W_0F3800_P_2,
2000   VEX_W_0F3801_P_2,
2001   VEX_W_0F3802_P_2,
2002   VEX_W_0F3803_P_2,
2003   VEX_W_0F3804_P_2,
2004   VEX_W_0F3805_P_2,
2005   VEX_W_0F3806_P_2,
2006   VEX_W_0F3807_P_2,
2007   VEX_W_0F3808_P_2,
2008   VEX_W_0F3809_P_2,
2009   VEX_W_0F380A_P_2,
2010   VEX_W_0F380B_P_2,
2011   VEX_W_0F380C_P_2,
2012   VEX_W_0F380D_P_2,
2013   VEX_W_0F380E_P_2,
2014   VEX_W_0F380F_P_2,
2015   VEX_W_0F3816_P_2,
2016   VEX_W_0F3817_P_2,
2017   VEX_W_0F3818_P_2,
2018   VEX_W_0F3819_P_2,
2019   VEX_W_0F381A_P_2_M_0,
2020   VEX_W_0F381C_P_2,
2021   VEX_W_0F381D_P_2,
2022   VEX_W_0F381E_P_2,
2023   VEX_W_0F3820_P_2,
2024   VEX_W_0F3821_P_2,
2025   VEX_W_0F3822_P_2,
2026   VEX_W_0F3823_P_2,
2027   VEX_W_0F3824_P_2,
2028   VEX_W_0F3825_P_2,
2029   VEX_W_0F3828_P_2,
2030   VEX_W_0F3829_P_2,
2031   VEX_W_0F382A_P_2_M_0,
2032   VEX_W_0F382B_P_2,
2033   VEX_W_0F382C_P_2_M_0,
2034   VEX_W_0F382D_P_2_M_0,
2035   VEX_W_0F382E_P_2_M_0,
2036   VEX_W_0F382F_P_2_M_0,
2037   VEX_W_0F3830_P_2,
2038   VEX_W_0F3831_P_2,
2039   VEX_W_0F3832_P_2,
2040   VEX_W_0F3833_P_2,
2041   VEX_W_0F3834_P_2,
2042   VEX_W_0F3835_P_2,
2043   VEX_W_0F3836_P_2,
2044   VEX_W_0F3837_P_2,
2045   VEX_W_0F3838_P_2,
2046   VEX_W_0F3839_P_2,
2047   VEX_W_0F383A_P_2,
2048   VEX_W_0F383B_P_2,
2049   VEX_W_0F383C_P_2,
2050   VEX_W_0F383D_P_2,
2051   VEX_W_0F383E_P_2,
2052   VEX_W_0F383F_P_2,
2053   VEX_W_0F3840_P_2,
2054   VEX_W_0F3841_P_2,
2055   VEX_W_0F3846_P_2,
2056   VEX_W_0F3858_P_2,
2057   VEX_W_0F3859_P_2,
2058   VEX_W_0F385A_P_2_M_0,
2059   VEX_W_0F3878_P_2,
2060   VEX_W_0F3879_P_2,
2061   VEX_W_0F38DB_P_2,
2062   VEX_W_0F38DC_P_2,
2063   VEX_W_0F38DD_P_2,
2064   VEX_W_0F38DE_P_2,
2065   VEX_W_0F38DF_P_2,
2066   VEX_W_0F3A00_P_2,
2067   VEX_W_0F3A01_P_2,
2068   VEX_W_0F3A02_P_2,
2069   VEX_W_0F3A04_P_2,
2070   VEX_W_0F3A05_P_2,
2071   VEX_W_0F3A06_P_2,
2072   VEX_W_0F3A08_P_2,
2073   VEX_W_0F3A09_P_2,
2074   VEX_W_0F3A0A_P_2,
2075   VEX_W_0F3A0B_P_2,
2076   VEX_W_0F3A0C_P_2,
2077   VEX_W_0F3A0D_P_2,
2078   VEX_W_0F3A0E_P_2,
2079   VEX_W_0F3A0F_P_2,
2080   VEX_W_0F3A14_P_2,
2081   VEX_W_0F3A15_P_2,
2082   VEX_W_0F3A18_P_2,
2083   VEX_W_0F3A19_P_2,
2084   VEX_W_0F3A20_P_2,
2085   VEX_W_0F3A21_P_2,
2086   VEX_W_0F3A30_P_2_LEN_0,
2087   VEX_W_0F3A31_P_2_LEN_0,
2088   VEX_W_0F3A32_P_2_LEN_0,
2089   VEX_W_0F3A33_P_2_LEN_0,
2090   VEX_W_0F3A38_P_2,
2091   VEX_W_0F3A39_P_2,
2092   VEX_W_0F3A40_P_2,
2093   VEX_W_0F3A41_P_2,
2094   VEX_W_0F3A42_P_2,
2095   VEX_W_0F3A44_P_2,
2096   VEX_W_0F3A46_P_2,
2097   VEX_W_0F3A48_P_2,
2098   VEX_W_0F3A49_P_2,
2099   VEX_W_0F3A4A_P_2,
2100   VEX_W_0F3A4B_P_2,
2101   VEX_W_0F3A4C_P_2,
2102   VEX_W_0F3A60_P_2,
2103   VEX_W_0F3A61_P_2,
2104   VEX_W_0F3A62_P_2,
2105   VEX_W_0F3A63_P_2,
2106   VEX_W_0F3ADF_P_2,
2107
2108   EVEX_W_0F10_P_0,
2109   EVEX_W_0F10_P_1_M_0,
2110   EVEX_W_0F10_P_1_M_1,
2111   EVEX_W_0F10_P_2,
2112   EVEX_W_0F10_P_3_M_0,
2113   EVEX_W_0F10_P_3_M_1,
2114   EVEX_W_0F11_P_0,
2115   EVEX_W_0F11_P_1_M_0,
2116   EVEX_W_0F11_P_1_M_1,
2117   EVEX_W_0F11_P_2,
2118   EVEX_W_0F11_P_3_M_0,
2119   EVEX_W_0F11_P_3_M_1,
2120   EVEX_W_0F12_P_0_M_0,
2121   EVEX_W_0F12_P_0_M_1,
2122   EVEX_W_0F12_P_1,
2123   EVEX_W_0F12_P_2,
2124   EVEX_W_0F12_P_3,
2125   EVEX_W_0F13_P_0,
2126   EVEX_W_0F13_P_2,
2127   EVEX_W_0F14_P_0,
2128   EVEX_W_0F14_P_2,
2129   EVEX_W_0F15_P_0,
2130   EVEX_W_0F15_P_2,
2131   EVEX_W_0F16_P_0_M_0,
2132   EVEX_W_0F16_P_0_M_1,
2133   EVEX_W_0F16_P_1,
2134   EVEX_W_0F16_P_2,
2135   EVEX_W_0F17_P_0,
2136   EVEX_W_0F17_P_2,
2137   EVEX_W_0F28_P_0,
2138   EVEX_W_0F28_P_2,
2139   EVEX_W_0F29_P_0,
2140   EVEX_W_0F29_P_2,
2141   EVEX_W_0F2A_P_1,
2142   EVEX_W_0F2A_P_3,
2143   EVEX_W_0F2B_P_0,
2144   EVEX_W_0F2B_P_2,
2145   EVEX_W_0F2E_P_0,
2146   EVEX_W_0F2E_P_2,
2147   EVEX_W_0F2F_P_0,
2148   EVEX_W_0F2F_P_2,
2149   EVEX_W_0F51_P_0,
2150   EVEX_W_0F51_P_1,
2151   EVEX_W_0F51_P_2,
2152   EVEX_W_0F51_P_3,
2153   EVEX_W_0F54_P_0,
2154   EVEX_W_0F54_P_2,
2155   EVEX_W_0F55_P_0,
2156   EVEX_W_0F55_P_2,
2157   EVEX_W_0F56_P_0,
2158   EVEX_W_0F56_P_2,
2159   EVEX_W_0F57_P_0,
2160   EVEX_W_0F57_P_2,
2161   EVEX_W_0F58_P_0,
2162   EVEX_W_0F58_P_1,
2163   EVEX_W_0F58_P_2,
2164   EVEX_W_0F58_P_3,
2165   EVEX_W_0F59_P_0,
2166   EVEX_W_0F59_P_1,
2167   EVEX_W_0F59_P_2,
2168   EVEX_W_0F59_P_3,
2169   EVEX_W_0F5A_P_0,
2170   EVEX_W_0F5A_P_1,
2171   EVEX_W_0F5A_P_2,
2172   EVEX_W_0F5A_P_3,
2173   EVEX_W_0F5B_P_0,
2174   EVEX_W_0F5B_P_1,
2175   EVEX_W_0F5B_P_2,
2176   EVEX_W_0F5C_P_0,
2177   EVEX_W_0F5C_P_1,
2178   EVEX_W_0F5C_P_2,
2179   EVEX_W_0F5C_P_3,
2180   EVEX_W_0F5D_P_0,
2181   EVEX_W_0F5D_P_1,
2182   EVEX_W_0F5D_P_2,
2183   EVEX_W_0F5D_P_3,
2184   EVEX_W_0F5E_P_0,
2185   EVEX_W_0F5E_P_1,
2186   EVEX_W_0F5E_P_2,
2187   EVEX_W_0F5E_P_3,
2188   EVEX_W_0F5F_P_0,
2189   EVEX_W_0F5F_P_1,
2190   EVEX_W_0F5F_P_2,
2191   EVEX_W_0F5F_P_3,
2192   EVEX_W_0F62_P_2,
2193   EVEX_W_0F66_P_2,
2194   EVEX_W_0F6A_P_2,
2195   EVEX_W_0F6B_P_2,
2196   EVEX_W_0F6C_P_2,
2197   EVEX_W_0F6D_P_2,
2198   EVEX_W_0F6E_P_2,
2199   EVEX_W_0F6F_P_1,
2200   EVEX_W_0F6F_P_2,
2201   EVEX_W_0F6F_P_3,
2202   EVEX_W_0F70_P_2,
2203   EVEX_W_0F72_R_2_P_2,
2204   EVEX_W_0F72_R_6_P_2,
2205   EVEX_W_0F73_R_2_P_2,
2206   EVEX_W_0F73_R_6_P_2,
2207   EVEX_W_0F76_P_2,
2208   EVEX_W_0F78_P_0,
2209   EVEX_W_0F78_P_2,
2210   EVEX_W_0F79_P_0,
2211   EVEX_W_0F79_P_2,
2212   EVEX_W_0F7A_P_1,
2213   EVEX_W_0F7A_P_2,
2214   EVEX_W_0F7A_P_3,
2215   EVEX_W_0F7B_P_1,
2216   EVEX_W_0F7B_P_2,
2217   EVEX_W_0F7B_P_3,
2218   EVEX_W_0F7E_P_1,
2219   EVEX_W_0F7E_P_2,
2220   EVEX_W_0F7F_P_1,
2221   EVEX_W_0F7F_P_2,
2222   EVEX_W_0F7F_P_3,
2223   EVEX_W_0FC2_P_0,
2224   EVEX_W_0FC2_P_1,
2225   EVEX_W_0FC2_P_2,
2226   EVEX_W_0FC2_P_3,
2227   EVEX_W_0FC6_P_0,
2228   EVEX_W_0FC6_P_2,
2229   EVEX_W_0FD2_P_2,
2230   EVEX_W_0FD3_P_2,
2231   EVEX_W_0FD4_P_2,
2232   EVEX_W_0FD6_P_2,
2233   EVEX_W_0FE6_P_1,
2234   EVEX_W_0FE6_P_2,
2235   EVEX_W_0FE6_P_3,
2236   EVEX_W_0FE7_P_2,
2237   EVEX_W_0FF2_P_2,
2238   EVEX_W_0FF3_P_2,
2239   EVEX_W_0FF4_P_2,
2240   EVEX_W_0FFA_P_2,
2241   EVEX_W_0FFB_P_2,
2242   EVEX_W_0FFE_P_2,
2243   EVEX_W_0F380C_P_2,
2244   EVEX_W_0F380D_P_2,
2245   EVEX_W_0F3810_P_1,
2246   EVEX_W_0F3810_P_2,
2247   EVEX_W_0F3811_P_1,
2248   EVEX_W_0F3811_P_2,
2249   EVEX_W_0F3812_P_1,
2250   EVEX_W_0F3812_P_2,
2251   EVEX_W_0F3813_P_1,
2252   EVEX_W_0F3813_P_2,
2253   EVEX_W_0F3814_P_1,
2254   EVEX_W_0F3815_P_1,
2255   EVEX_W_0F3818_P_2,
2256   EVEX_W_0F3819_P_2,
2257   EVEX_W_0F381A_P_2,
2258   EVEX_W_0F381B_P_2,
2259   EVEX_W_0F381E_P_2,
2260   EVEX_W_0F381F_P_2,
2261   EVEX_W_0F3820_P_1,
2262   EVEX_W_0F3821_P_1,
2263   EVEX_W_0F3822_P_1,
2264   EVEX_W_0F3823_P_1,
2265   EVEX_W_0F3824_P_1,
2266   EVEX_W_0F3825_P_1,
2267   EVEX_W_0F3825_P_2,
2268   EVEX_W_0F3826_P_1,
2269   EVEX_W_0F3826_P_2,
2270   EVEX_W_0F3828_P_1,
2271   EVEX_W_0F3828_P_2,
2272   EVEX_W_0F3829_P_1,
2273   EVEX_W_0F3829_P_2,
2274   EVEX_W_0F382A_P_1,
2275   EVEX_W_0F382A_P_2,
2276   EVEX_W_0F382B_P_2,
2277   EVEX_W_0F3830_P_1,
2278   EVEX_W_0F3831_P_1,
2279   EVEX_W_0F3832_P_1,
2280   EVEX_W_0F3833_P_1,
2281   EVEX_W_0F3834_P_1,
2282   EVEX_W_0F3835_P_1,
2283   EVEX_W_0F3835_P_2,
2284   EVEX_W_0F3837_P_2,
2285   EVEX_W_0F3838_P_1,
2286   EVEX_W_0F3839_P_1,
2287   EVEX_W_0F383A_P_1,
2288   EVEX_W_0F3840_P_2,
2289   EVEX_W_0F3858_P_2,
2290   EVEX_W_0F3859_P_2,
2291   EVEX_W_0F385A_P_2,
2292   EVEX_W_0F385B_P_2,
2293   EVEX_W_0F3866_P_2,
2294   EVEX_W_0F3875_P_2,
2295   EVEX_W_0F3878_P_2,
2296   EVEX_W_0F3879_P_2,
2297   EVEX_W_0F387A_P_2,
2298   EVEX_W_0F387B_P_2,
2299   EVEX_W_0F387D_P_2,
2300   EVEX_W_0F388D_P_2,
2301   EVEX_W_0F3891_P_2,
2302   EVEX_W_0F3893_P_2,
2303   EVEX_W_0F38A1_P_2,
2304   EVEX_W_0F38A3_P_2,
2305   EVEX_W_0F38C7_R_1_P_2,
2306   EVEX_W_0F38C7_R_2_P_2,
2307   EVEX_W_0F38C7_R_5_P_2,
2308   EVEX_W_0F38C7_R_6_P_2,
2309
2310   EVEX_W_0F3A00_P_2,
2311   EVEX_W_0F3A01_P_2,
2312   EVEX_W_0F3A04_P_2,
2313   EVEX_W_0F3A05_P_2,
2314   EVEX_W_0F3A08_P_2,
2315   EVEX_W_0F3A09_P_2,
2316   EVEX_W_0F3A0A_P_2,
2317   EVEX_W_0F3A0B_P_2,
2318   EVEX_W_0F3A16_P_2,
2319   EVEX_W_0F3A18_P_2,
2320   EVEX_W_0F3A19_P_2,
2321   EVEX_W_0F3A1A_P_2,
2322   EVEX_W_0F3A1B_P_2,
2323   EVEX_W_0F3A1D_P_2,
2324   EVEX_W_0F3A21_P_2,
2325   EVEX_W_0F3A22_P_2,
2326   EVEX_W_0F3A23_P_2,
2327   EVEX_W_0F3A38_P_2,
2328   EVEX_W_0F3A39_P_2,
2329   EVEX_W_0F3A3A_P_2,
2330   EVEX_W_0F3A3B_P_2,
2331   EVEX_W_0F3A3E_P_2,
2332   EVEX_W_0F3A3F_P_2,
2333   EVEX_W_0F3A42_P_2,
2334   EVEX_W_0F3A43_P_2,
2335   EVEX_W_0F3A50_P_2,
2336   EVEX_W_0F3A51_P_2,
2337   EVEX_W_0F3A56_P_2,
2338   EVEX_W_0F3A57_P_2,
2339   EVEX_W_0F3A66_P_2,
2340   EVEX_W_0F3A67_P_2
2341 };
2342
2343 typedef void (*op_rtn) (int bytemode, int sizeflag);
2344
2345 struct dis386 {
2346   const char *name;
2347   struct
2348     {
2349       op_rtn rtn;
2350       int bytemode;
2351     } op[MAX_OPERANDS];
2352 };
2353
2354 /* Upper case letters in the instruction names here are macros.
2355    'A' => print 'b' if no register operands or suffix_always is true
2356    'B' => print 'b' if suffix_always is true
2357    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2358           size prefix
2359    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2360           suffix_always is true
2361    'E' => print 'e' if 32-bit form of jcxz
2362    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2363    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2364    'H' => print ",pt" or ",pn" branch hint
2365    'I' => honor following macro letter even in Intel mode (implemented only
2366           for some of the macro letters)
2367    'J' => print 'l'
2368    'K' => print 'd' or 'q' if rex prefix is present.
2369    'L' => print 'l' if suffix_always is true
2370    'M' => print 'r' if intel_mnemonic is false.
2371    'N' => print 'n' if instruction has no wait "prefix"
2372    'O' => print 'd' or 'o' (or 'q' in Intel mode)
2373    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2374           or suffix_always is true.  print 'q' if rex prefix is present.
2375    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2376           is true
2377    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2378    'S' => print 'w', 'l' or 'q' if suffix_always is true
2379    'T' => print 'q' in 64bit mode and behave as 'P' otherwise
2380    'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
2381    'V' => print 'q' in 64bit mode and behave as 'S' otherwise
2382    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2383    'X' => print 's', 'd' depending on data16 prefix (for XMM)
2384    'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
2385           suffix_always is true.
2386    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2387    '!' => change condition from true to false or from false to true.
2388    '%' => add 1 upper case letter to the macro.
2389
2390    2 upper case letter macros:
2391    "XY" => print 'x' or 'y' if no register operands or suffix_always
2392            is true.
2393    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2394    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2395            or suffix_always is true
2396    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2397    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2398    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2399    "LW" => print 'd', 'q' depending on the VEX.W bit
2400    "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2401            an operand size prefix, or suffix_always is true.  print
2402            'q' if rex prefix is present.
2403
2404    Many of the above letters print nothing in Intel mode.  See "putop"
2405    for the details.
2406
2407    Braces '{' and '}', and vertical bars '|', indicate alternative
2408    mnemonic strings for AT&T and Intel.  */
2409
2410 static const struct dis386 dis386[] = {
2411   /* 00 */
2412   { "addB",             { Ebh1, Gb } },
2413   { "addS",             { Evh1, Gv } },
2414   { "addB",             { Gb, EbS } },
2415   { "addS",             { Gv, EvS } },
2416   { "addB",             { AL, Ib } },
2417   { "addS",             { eAX, Iv } },
2418   { X86_64_TABLE (X86_64_06) },
2419   { X86_64_TABLE (X86_64_07) },
2420   /* 08 */
2421   { "orB",              { Ebh1, Gb } },
2422   { "orS",              { Evh1, Gv } },
2423   { "orB",              { Gb, EbS } },
2424   { "orS",              { Gv, EvS } },
2425   { "orB",              { AL, Ib } },
2426   { "orS",              { eAX, Iv } },
2427   { X86_64_TABLE (X86_64_0D) },
2428   { Bad_Opcode },       /* 0x0f extended opcode escape */
2429   /* 10 */
2430   { "adcB",             { Ebh1, Gb } },
2431   { "adcS",             { Evh1, Gv } },
2432   { "adcB",             { Gb, EbS } },
2433   { "adcS",             { Gv, EvS } },
2434   { "adcB",             { AL, Ib } },
2435   { "adcS",             { eAX, Iv } },
2436   { X86_64_TABLE (X86_64_16) },
2437   { X86_64_TABLE (X86_64_17) },
2438   /* 18 */
2439   { "sbbB",             { Ebh1, Gb } },
2440   { "sbbS",             { Evh1, Gv } },
2441   { "sbbB",             { Gb, EbS } },
2442   { "sbbS",             { Gv, EvS } },
2443   { "sbbB",             { AL, Ib } },
2444   { "sbbS",             { eAX, Iv } },
2445   { X86_64_TABLE (X86_64_1E) },
2446   { X86_64_TABLE (X86_64_1F) },
2447   /* 20 */
2448   { "andB",             { Ebh1, Gb } },
2449   { "andS",             { Evh1, Gv } },
2450   { "andB",             { Gb, EbS } },
2451   { "andS",             { Gv, EvS } },
2452   { "andB",             { AL, Ib } },
2453   { "andS",             { eAX, Iv } },
2454   { Bad_Opcode },       /* SEG ES prefix */
2455   { X86_64_TABLE (X86_64_27) },
2456   /* 28 */
2457   { "subB",             { Ebh1, Gb } },
2458   { "subS",             { Evh1, Gv } },
2459   { "subB",             { Gb, EbS } },
2460   { "subS",             { Gv, EvS } },
2461   { "subB",             { AL, Ib } },
2462   { "subS",             { eAX, Iv } },
2463   { Bad_Opcode },       /* SEG CS prefix */
2464   { X86_64_TABLE (X86_64_2F) },
2465   /* 30 */
2466   { "xorB",             { Ebh1, Gb } },
2467   { "xorS",             { Evh1, Gv } },
2468   { "xorB",             { Gb, EbS } },
2469   { "xorS",             { Gv, EvS } },
2470   { "xorB",             { AL, Ib } },
2471   { "xorS",             { eAX, Iv } },
2472   { Bad_Opcode },       /* SEG SS prefix */
2473   { X86_64_TABLE (X86_64_37) },
2474   /* 38 */
2475   { "cmpB",             { Eb, Gb } },
2476   { "cmpS",             { Ev, Gv } },
2477   { "cmpB",             { Gb, EbS } },
2478   { "cmpS",             { Gv, EvS } },
2479   { "cmpB",             { AL, Ib } },
2480   { "cmpS",             { eAX, Iv } },
2481   { Bad_Opcode },       /* SEG DS prefix */
2482   { X86_64_TABLE (X86_64_3F) },
2483   /* 40 */
2484   { "inc{S|}",          { RMeAX } },
2485   { "inc{S|}",          { RMeCX } },
2486   { "inc{S|}",          { RMeDX } },
2487   { "inc{S|}",          { RMeBX } },
2488   { "inc{S|}",          { RMeSP } },
2489   { "inc{S|}",          { RMeBP } },
2490   { "inc{S|}",          { RMeSI } },
2491   { "inc{S|}",          { RMeDI } },
2492   /* 48 */
2493   { "dec{S|}",          { RMeAX } },
2494   { "dec{S|}",          { RMeCX } },
2495   { "dec{S|}",          { RMeDX } },
2496   { "dec{S|}",          { RMeBX } },
2497   { "dec{S|}",          { RMeSP } },
2498   { "dec{S|}",          { RMeBP } },
2499   { "dec{S|}",          { RMeSI } },
2500   { "dec{S|}",          { RMeDI } },
2501   /* 50 */
2502   { "pushV",            { RMrAX } },
2503   { "pushV",            { RMrCX } },
2504   { "pushV",            { RMrDX } },
2505   { "pushV",            { RMrBX } },
2506   { "pushV",            { RMrSP } },
2507   { "pushV",            { RMrBP } },
2508   { "pushV",            { RMrSI } },
2509   { "pushV",            { RMrDI } },
2510   /* 58 */
2511   { "popV",             { RMrAX } },
2512   { "popV",             { RMrCX } },
2513   { "popV",             { RMrDX } },
2514   { "popV",             { RMrBX } },
2515   { "popV",             { RMrSP } },
2516   { "popV",             { RMrBP } },
2517   { "popV",             { RMrSI } },
2518   { "popV",             { RMrDI } },
2519   /* 60 */
2520   { X86_64_TABLE (X86_64_60) },
2521   { X86_64_TABLE (X86_64_61) },
2522   { X86_64_TABLE (X86_64_62) },
2523   { X86_64_TABLE (X86_64_63) },
2524   { Bad_Opcode },       /* seg fs */
2525   { Bad_Opcode },       /* seg gs */
2526   { Bad_Opcode },       /* op size prefix */
2527   { Bad_Opcode },       /* adr size prefix */
2528   /* 68 */
2529   { "pushT",            { sIv } },
2530   { "imulS",            { Gv, Ev, Iv } },
2531   { "pushT",            { sIbT } },
2532   { "imulS",            { Gv, Ev, sIb } },
2533   { "ins{b|}",          { Ybr, indirDX } },
2534   { X86_64_TABLE (X86_64_6D) },
2535   { "outs{b|}",         { indirDXr, Xb } },
2536   { X86_64_TABLE (X86_64_6F) },
2537   /* 70 */
2538   { "joH",              { Jb, BND, cond_jump_flag } },
2539   { "jnoH",             { Jb, BND, cond_jump_flag } },
2540   { "jbH",              { Jb, BND, cond_jump_flag } },
2541   { "jaeH",             { Jb, BND, cond_jump_flag } },
2542   { "jeH",              { Jb, BND, cond_jump_flag } },
2543   { "jneH",             { Jb, BND, cond_jump_flag } },
2544   { "jbeH",             { Jb, BND, cond_jump_flag } },
2545   { "jaH",              { Jb, BND, cond_jump_flag } },
2546   /* 78 */
2547   { "jsH",              { Jb, BND, cond_jump_flag } },
2548   { "jnsH",             { Jb, BND, cond_jump_flag } },
2549   { "jpH",              { Jb, BND, cond_jump_flag } },
2550   { "jnpH",             { Jb, BND, cond_jump_flag } },
2551   { "jlH",              { Jb, BND, cond_jump_flag } },
2552   { "jgeH",             { Jb, BND, cond_jump_flag } },
2553   { "jleH",             { Jb, BND, cond_jump_flag } },
2554   { "jgH",              { Jb, BND, cond_jump_flag } },
2555   /* 80 */
2556   { REG_TABLE (REG_80) },
2557   { REG_TABLE (REG_81) },
2558   { Bad_Opcode },
2559   { REG_TABLE (REG_82) },
2560   { "testB",            { Eb, Gb } },
2561   { "testS",            { Ev, Gv } },
2562   { "xchgB",            { Ebh2, Gb } },
2563   { "xchgS",            { Evh2, Gv } },
2564   /* 88 */
2565   { "movB",             { Ebh3, Gb } },
2566   { "movS",             { Evh3, Gv } },
2567   { "movB",             { Gb, EbS } },
2568   { "movS",             { Gv, EvS } },
2569   { "movD",             { Sv, Sw } },
2570   { MOD_TABLE (MOD_8D) },
2571   { "movD",             { Sw, Sv } },
2572   { REG_TABLE (REG_8F) },
2573   /* 90 */
2574   { PREFIX_TABLE (PREFIX_90) },
2575   { "xchgS",            { RMeCX, eAX } },
2576   { "xchgS",            { RMeDX, eAX } },
2577   { "xchgS",            { RMeBX, eAX } },
2578   { "xchgS",            { RMeSP, eAX } },
2579   { "xchgS",            { RMeBP, eAX } },
2580   { "xchgS",            { RMeSI, eAX } },
2581   { "xchgS",            { RMeDI, eAX } },
2582   /* 98 */
2583   { "cW{t|}R",          { XX } },
2584   { "cR{t|}O",          { XX } },
2585   { X86_64_TABLE (X86_64_9A) },
2586   { Bad_Opcode },       /* fwait */
2587   { "pushfT",           { XX } },
2588   { "popfT",            { XX } },
2589   { "sahf",             { XX } },
2590   { "lahf",             { XX } },
2591   /* a0 */
2592   { "mov%LB",           { AL, Ob } },
2593   { "mov%LS",           { eAX, Ov } },
2594   { "mov%LB",           { Ob, AL } },
2595   { "mov%LS",           { Ov, eAX } },
2596   { "movs{b|}",         { Ybr, Xb } },
2597   { "movs{R|}",         { Yvr, Xv } },
2598   { "cmps{b|}",         { Xb, Yb } },
2599   { "cmps{R|}",         { Xv, Yv } },
2600   /* a8 */
2601   { "testB",            { AL, Ib } },
2602   { "testS",            { eAX, Iv } },
2603   { "stosB",            { Ybr, AL } },
2604   { "stosS",            { Yvr, eAX } },
2605   { "lodsB",            { ALr, Xb } },
2606   { "lodsS",            { eAXr, Xv } },
2607   { "scasB",            { AL, Yb } },
2608   { "scasS",            { eAX, Yv } },
2609   /* b0 */
2610   { "movB",             { RMAL, Ib } },
2611   { "movB",             { RMCL, Ib } },
2612   { "movB",             { RMDL, Ib } },
2613   { "movB",             { RMBL, Ib } },
2614   { "movB",             { RMAH, Ib } },
2615   { "movB",             { RMCH, Ib } },
2616   { "movB",             { RMDH, Ib } },
2617   { "movB",             { RMBH, Ib } },
2618   /* b8 */
2619   { "mov%LV",           { RMeAX, Iv64 } },
2620   { "mov%LV",           { RMeCX, Iv64 } },
2621   { "mov%LV",           { RMeDX, Iv64 } },
2622   { "mov%LV",           { RMeBX, Iv64 } },
2623   { "mov%LV",           { RMeSP, Iv64 } },
2624   { "mov%LV",           { RMeBP, Iv64 } },
2625   { "mov%LV",           { RMeSI, Iv64 } },
2626   { "mov%LV",           { RMeDI, Iv64 } },
2627   /* c0 */
2628   { REG_TABLE (REG_C0) },
2629   { REG_TABLE (REG_C1) },
2630   { "retT",             { Iw, BND } },
2631   { "retT",             { BND } },
2632   { X86_64_TABLE (X86_64_C4) },
2633   { X86_64_TABLE (X86_64_C5) },
2634   { REG_TABLE (REG_C6) },
2635   { REG_TABLE (REG_C7) },
2636   /* c8 */
2637   { "enterT",           { Iw, Ib } },
2638   { "leaveT",           { XX } },
2639   { "Jret{|f}P",        { Iw } },
2640   { "Jret{|f}P",        { XX } },
2641   { "int3",             { XX } },
2642   { "int",              { Ib } },
2643   { X86_64_TABLE (X86_64_CE) },
2644   { "iret%LP",          { XX } },
2645   /* d0 */
2646   { REG_TABLE (REG_D0) },
2647   { REG_TABLE (REG_D1) },
2648   { REG_TABLE (REG_D2) },
2649   { REG_TABLE (REG_D3) },
2650   { X86_64_TABLE (X86_64_D4) },
2651   { X86_64_TABLE (X86_64_D5) },
2652   { Bad_Opcode },
2653   { "xlat",             { DSBX } },
2654   /* d8 */
2655   { FLOAT },
2656   { FLOAT },
2657   { FLOAT },
2658   { FLOAT },
2659   { FLOAT },
2660   { FLOAT },
2661   { FLOAT },
2662   { FLOAT },
2663   /* e0 */
2664   { "loopneFH",         { Jb, XX, loop_jcxz_flag } },
2665   { "loopeFH",          { Jb, XX, loop_jcxz_flag } },
2666   { "loopFH",           { Jb, XX, loop_jcxz_flag } },
2667   { "jEcxzH",           { Jb, XX, loop_jcxz_flag } },
2668   { "inB",              { AL, Ib } },
2669   { "inG",              { zAX, Ib } },
2670   { "outB",             { Ib, AL } },
2671   { "outG",             { Ib, zAX } },
2672   /* e8 */
2673   { "callT",            { Jv, BND } },
2674   { "jmpT",             { Jv, BND } },
2675   { X86_64_TABLE (X86_64_EA) },
2676   { "jmp",              { Jb, BND } },
2677   { "inB",              { AL, indirDX } },
2678   { "inG",              { zAX, indirDX } },
2679   { "outB",             { indirDX, AL } },
2680   { "outG",             { indirDX, zAX } },
2681   /* f0 */
2682   { Bad_Opcode },       /* lock prefix */
2683   { "icebp",            { XX } },
2684   { Bad_Opcode },       /* repne */
2685   { Bad_Opcode },       /* repz */
2686   { "hlt",              { XX } },
2687   { "cmc",              { XX } },
2688   { REG_TABLE (REG_F6) },
2689   { REG_TABLE (REG_F7) },
2690   /* f8 */
2691   { "clc",              { XX } },
2692   { "stc",              { XX } },
2693   { "cli",              { XX } },
2694   { "sti",              { XX } },
2695   { "cld",              { XX } },
2696   { "std",              { XX } },
2697   { REG_TABLE (REG_FE) },
2698   { REG_TABLE (REG_FF) },
2699 };
2700
2701 static const struct dis386 dis386_twobyte[] = {
2702   /* 00 */
2703   { REG_TABLE (REG_0F00 ) },
2704   { REG_TABLE (REG_0F01 ) },
2705   { "larS",             { Gv, Ew } },
2706   { "lslS",             { Gv, Ew } },
2707   { Bad_Opcode },
2708   { "syscall",          { XX } },
2709   { "clts",             { XX } },
2710   { "sysret%LP",                { XX } },
2711   /* 08 */
2712   { "invd",             { XX } },
2713   { "wbinvd",           { XX } },
2714   { Bad_Opcode },
2715   { "ud2",              { XX } },
2716   { Bad_Opcode },
2717   { REG_TABLE (REG_0F0D) },
2718   { "femms",            { XX } },
2719   { "",                 { MX, EM, OPSUF } }, /* See OP_3DNowSuffix.  */
2720   /* 10 */
2721   { PREFIX_TABLE (PREFIX_0F10) },
2722   { PREFIX_TABLE (PREFIX_0F11) },
2723   { PREFIX_TABLE (PREFIX_0F12) },
2724   { MOD_TABLE (MOD_0F13) },
2725   { "unpcklpX",         { XM, EXx } },
2726   { "unpckhpX",         { XM, EXx } },
2727   { PREFIX_TABLE (PREFIX_0F16) },
2728   { MOD_TABLE (MOD_0F17) },
2729   /* 18 */
2730   { REG_TABLE (REG_0F18) },
2731   { "nopQ",             { Ev } },
2732   { PREFIX_TABLE (PREFIX_0F1A) },
2733   { PREFIX_TABLE (PREFIX_0F1B) },
2734   { "nopQ",             { Ev } },
2735   { "nopQ",             { Ev } },
2736   { "nopQ",             { Ev } },
2737   { "nopQ",             { Ev } },
2738   /* 20 */
2739   { "movZ",             { Rm, Cm } },
2740   { "movZ",             { Rm, Dm } },
2741   { "movZ",             { Cm, Rm } },
2742   { "movZ",             { Dm, Rm } },
2743   { MOD_TABLE (MOD_0F24) },
2744   { Bad_Opcode },
2745   { MOD_TABLE (MOD_0F26) },
2746   { Bad_Opcode },
2747   /* 28 */
2748   { "movapX",           { XM, EXx } },
2749   { "movapX",           { EXxS, XM } },
2750   { PREFIX_TABLE (PREFIX_0F2A) },
2751   { PREFIX_TABLE (PREFIX_0F2B) },
2752   { PREFIX_TABLE (PREFIX_0F2C) },
2753   { PREFIX_TABLE (PREFIX_0F2D) },
2754   { PREFIX_TABLE (PREFIX_0F2E) },
2755   { PREFIX_TABLE (PREFIX_0F2F) },
2756   /* 30 */
2757   { "wrmsr",            { XX } },
2758   { "rdtsc",            { XX } },
2759   { "rdmsr",            { XX } },
2760   { "rdpmc",            { XX } },
2761   { "sysenter",         { XX } },
2762   { "sysexit",          { XX } },
2763   { Bad_Opcode },
2764   { "getsec",           { XX } },
2765   /* 38 */
2766   { THREE_BYTE_TABLE (THREE_BYTE_0F38) },
2767   { Bad_Opcode },
2768   { THREE_BYTE_TABLE (THREE_BYTE_0F3A) },
2769   { Bad_Opcode },
2770   { Bad_Opcode },
2771   { Bad_Opcode },
2772   { Bad_Opcode },
2773   { Bad_Opcode },
2774   /* 40 */
2775   { "cmovoS",           { Gv, Ev } },
2776   { "cmovnoS",          { Gv, Ev } },
2777   { "cmovbS",           { Gv, Ev } },
2778   { "cmovaeS",          { Gv, Ev } },
2779   { "cmoveS",           { Gv, Ev } },
2780   { "cmovneS",          { Gv, Ev } },
2781   { "cmovbeS",          { Gv, Ev } },
2782   { "cmovaS",           { Gv, Ev } },
2783   /* 48 */
2784   { "cmovsS",           { Gv, Ev } },
2785   { "cmovnsS",          { Gv, Ev } },
2786   { "cmovpS",           { Gv, Ev } },
2787   { "cmovnpS",          { Gv, Ev } },
2788   { "cmovlS",           { Gv, Ev } },
2789   { "cmovgeS",          { Gv, Ev } },
2790   { "cmovleS",          { Gv, Ev } },
2791   { "cmovgS",           { Gv, Ev } },
2792   /* 50 */
2793   { MOD_TABLE (MOD_0F51) },
2794   { PREFIX_TABLE (PREFIX_0F51) },
2795   { PREFIX_TABLE (PREFIX_0F52) },
2796   { PREFIX_TABLE (PREFIX_0F53) },
2797   { "andpX",            { XM, EXx } },
2798   { "andnpX",           { XM, EXx } },
2799   { "orpX",             { XM, EXx } },
2800   { "xorpX",            { XM, EXx } },
2801   /* 58 */
2802   { PREFIX_TABLE (PREFIX_0F58) },
2803   { PREFIX_TABLE (PREFIX_0F59) },
2804   { PREFIX_TABLE (PREFIX_0F5A) },
2805   { PREFIX_TABLE (PREFIX_0F5B) },
2806   { PREFIX_TABLE (PREFIX_0F5C) },
2807   { PREFIX_TABLE (PREFIX_0F5D) },
2808   { PREFIX_TABLE (PREFIX_0F5E) },
2809   { PREFIX_TABLE (PREFIX_0F5F) },
2810   /* 60 */
2811   { PREFIX_TABLE (PREFIX_0F60) },
2812   { PREFIX_TABLE (PREFIX_0F61) },
2813   { PREFIX_TABLE (PREFIX_0F62) },
2814   { "packsswb",         { MX, EM } },
2815   { "pcmpgtb",          { MX, EM } },
2816   { "pcmpgtw",          { MX, EM } },
2817   { "pcmpgtd",          { MX, EM } },
2818   { "packuswb",         { MX, EM } },
2819   /* 68 */
2820   { "punpckhbw",        { MX, EM } },
2821   { "punpckhwd",        { MX, EM } },
2822   { "punpckhdq",        { MX, EM } },
2823   { "packssdw",         { MX, EM } },
2824   { PREFIX_TABLE (PREFIX_0F6C) },
2825   { PREFIX_TABLE (PREFIX_0F6D) },
2826   { "movK",             { MX, Edq } },
2827   { PREFIX_TABLE (PREFIX_0F6F) },
2828   /* 70 */
2829   { PREFIX_TABLE (PREFIX_0F70) },
2830   { REG_TABLE (REG_0F71) },
2831   { REG_TABLE (REG_0F72) },
2832   { REG_TABLE (REG_0F73) },
2833   { "pcmpeqb",          { MX, EM } },
2834   { "pcmpeqw",          { MX, EM } },
2835   { "pcmpeqd",          { MX, EM } },
2836   { "emms",             { XX } },
2837   /* 78 */
2838   { PREFIX_TABLE (PREFIX_0F78) },
2839   { PREFIX_TABLE (PREFIX_0F79) },
2840   { THREE_BYTE_TABLE (THREE_BYTE_0F7A) },
2841   { Bad_Opcode },
2842   { PREFIX_TABLE (PREFIX_0F7C) },
2843   { PREFIX_TABLE (PREFIX_0F7D) },
2844   { PREFIX_TABLE (PREFIX_0F7E) },
2845   { PREFIX_TABLE (PREFIX_0F7F) },
2846   /* 80 */
2847   { "joH",              { Jv, BND, cond_jump_flag } },
2848   { "jnoH",             { Jv, BND, cond_jump_flag } },
2849   { "jbH",              { Jv, BND, cond_jump_flag } },
2850   { "jaeH",             { Jv, BND, cond_jump_flag } },
2851   { "jeH",              { Jv, BND, cond_jump_flag } },
2852   { "jneH",             { Jv, BND, cond_jump_flag } },
2853   { "jbeH",             { Jv, BND, cond_jump_flag } },
2854   { "jaH",              { Jv, BND, cond_jump_flag } },
2855   /* 88 */
2856   { "jsH",              { Jv, BND, cond_jump_flag } },
2857   { "jnsH",             { Jv, BND, cond_jump_flag } },
2858   { "jpH",              { Jv, BND, cond_jump_flag } },
2859   { "jnpH",             { Jv, BND, cond_jump_flag } },
2860   { "jlH",              { Jv, BND, cond_jump_flag } },
2861   { "jgeH",             { Jv, BND, cond_jump_flag } },
2862   { "jleH",             { Jv, BND, cond_jump_flag } },
2863   { "jgH",              { Jv, BND, cond_jump_flag } },
2864   /* 90 */
2865   { "seto",             { Eb } },
2866   { "setno",            { Eb } },
2867   { "setb",             { Eb } },
2868   { "setae",            { Eb } },
2869   { "sete",             { Eb } },
2870   { "setne",            { Eb } },
2871   { "setbe",            { Eb } },
2872   { "seta",             { Eb } },
2873   /* 98 */
2874   { "sets",             { Eb } },
2875   { "setns",            { Eb } },
2876   { "setp",             { Eb } },
2877   { "setnp",            { Eb } },
2878   { "setl",             { Eb } },
2879   { "setge",            { Eb } },
2880   { "setle",            { Eb } },
2881   { "setg",             { Eb } },
2882   /* a0 */
2883   { "pushT",            { fs } },
2884   { "popT",             { fs } },
2885   { "cpuid",            { XX } },
2886   { "btS",              { Ev, Gv } },
2887   { "shldS",            { Ev, Gv, Ib } },
2888   { "shldS",            { Ev, Gv, CL } },
2889   { REG_TABLE (REG_0FA6) },
2890   { REG_TABLE (REG_0FA7) },
2891   /* a8 */
2892   { "pushT",            { gs } },
2893   { "popT",             { gs } },
2894   { "rsm",              { XX } },
2895   { "btsS",             { Evh1, Gv } },
2896   { "shrdS",            { Ev, Gv, Ib } },
2897   { "shrdS",            { Ev, Gv, CL } },
2898   { REG_TABLE (REG_0FAE) },
2899   { "imulS",            { Gv, Ev } },
2900   /* b0 */
2901   { "cmpxchgB",         { Ebh1, Gb } },
2902   { "cmpxchgS",         { Evh1, Gv } },
2903   { MOD_TABLE (MOD_0FB2) },
2904   { "btrS",             { Evh1, Gv } },
2905   { MOD_TABLE (MOD_0FB4) },
2906   { MOD_TABLE (MOD_0FB5) },
2907   { "movz{bR|x}",       { Gv, Eb } },
2908   { "movz{wR|x}",       { Gv, Ew } }, /* yes, there really is movzww ! */
2909   /* b8 */
2910   { PREFIX_TABLE (PREFIX_0FB8) },
2911   { "ud1",              { XX } },
2912   { REG_TABLE (REG_0FBA) },
2913   { "btcS",             { Evh1, Gv } },
2914   { PREFIX_TABLE (PREFIX_0FBC) },
2915   { PREFIX_TABLE (PREFIX_0FBD) },
2916   { "movs{bR|x}",       { Gv, Eb } },
2917   { "movs{wR|x}",       { Gv, Ew } }, /* yes, there really is movsww ! */
2918   /* c0 */
2919   { "xaddB",            { Ebh1, Gb } },
2920   { "xaddS",            { Evh1, Gv } },
2921   { PREFIX_TABLE (PREFIX_0FC2) },
2922   { PREFIX_TABLE (PREFIX_0FC3) },
2923   { "pinsrw",           { MX, Edqw, Ib } },
2924   { "pextrw",           { Gdq, MS, Ib } },
2925   { "shufpX",           { XM, EXx, Ib } },
2926   { REG_TABLE (REG_0FC7) },
2927   /* c8 */
2928   { "bswap",            { RMeAX } },
2929   { "bswap",            { RMeCX } },
2930   { "bswap",            { RMeDX } },
2931   { "bswap",            { RMeBX } },
2932   { "bswap",            { RMeSP } },
2933   { "bswap",            { RMeBP } },
2934   { "bswap",            { RMeSI } },
2935   { "bswap",            { RMeDI } },
2936   /* d0 */
2937   { PREFIX_TABLE (PREFIX_0FD0) },
2938   { "psrlw",            { MX, EM } },
2939   { "psrld",            { MX, EM } },
2940   { "psrlq",            { MX, EM } },
2941   { "paddq",            { MX, EM } },
2942   { "pmullw",           { MX, EM } },
2943   { PREFIX_TABLE (PREFIX_0FD6) },
2944   { MOD_TABLE (MOD_0FD7) },
2945   /* d8 */
2946   { "psubusb",          { MX, EM } },
2947   { "psubusw",          { MX, EM } },
2948   { "pminub",           { MX, EM } },
2949   { "pand",             { MX, EM } },
2950   { "paddusb",          { MX, EM } },
2951   { "paddusw",          { MX, EM } },
2952   { "pmaxub",           { MX, EM } },
2953   { "pandn",            { MX, EM } },
2954   /* e0 */
2955   { "pavgb",            { MX, EM } },
2956   { "psraw",            { MX, EM } },
2957   { "psrad",            { MX, EM } },
2958   { "pavgw",            { MX, EM } },
2959   { "pmulhuw",          { MX, EM } },
2960   { "pmulhw",           { MX, EM } },
2961   { PREFIX_TABLE (PREFIX_0FE6) },
2962   { PREFIX_TABLE (PREFIX_0FE7) },
2963   /* e8 */
2964   { "psubsb",           { MX, EM } },
2965   { "psubsw",           { MX, EM } },
2966   { "pminsw",           { MX, EM } },
2967   { "por",              { MX, EM } },
2968   { "paddsb",           { MX, EM } },
2969   { "paddsw",           { MX, EM } },
2970   { "pmaxsw",           { MX, EM } },
2971   { "pxor",             { MX, EM } },
2972   /* f0 */
2973   { PREFIX_TABLE (PREFIX_0FF0) },
2974   { "psllw",            { MX, EM } },
2975   { "pslld",            { MX, EM } },
2976   { "psllq",            { MX, EM } },
2977   { "pmuludq",          { MX, EM } },
2978   { "pmaddwd",          { MX, EM } },
2979   { "psadbw",           { MX, EM } },
2980   { PREFIX_TABLE (PREFIX_0FF7) },
2981   /* f8 */
2982   { "psubb",            { MX, EM } },
2983   { "psubw",            { MX, EM } },
2984   { "psubd",            { MX, EM } },
2985   { "psubq",            { MX, EM } },
2986   { "paddb",            { MX, EM } },
2987   { "paddw",            { MX, EM } },
2988   { "paddd",            { MX, EM } },
2989   { Bad_Opcode },
2990 };
2991
2992 static const unsigned char onebyte_has_modrm[256] = {
2993   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2994   /*       -------------------------------        */
2995   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2996   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2997   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2998   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2999   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
3000   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
3001   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
3002   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
3003   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
3004   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
3005   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
3006   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
3007   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
3008   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
3009   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
3010   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
3011   /*       -------------------------------        */
3012   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3013 };
3014
3015 static const unsigned char twobyte_has_modrm[256] = {
3016   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3017   /*       -------------------------------        */
3018   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
3019   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
3020   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
3021   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
3022   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
3023   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
3024   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
3025   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
3026   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
3027   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
3028   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
3029   /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
3030   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
3031   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
3032   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
3033   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0  /* ff */
3034   /*       -------------------------------        */
3035   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3036 };
3037
3038 static const unsigned char twobyte_has_mandatory_prefix[256] = {
3039   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3040   /*       -------------------------------        */
3041   /* 00 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 0f */
3042   /* 10 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* 1f */
3043   /* 20 */ 0,0,0,0,0,0,0,0,1,1,1,1,1,1,0,0, /* 2f */
3044   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
3045   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 4f */
3046   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
3047   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
3048   /* 70 */ 1,0,0,0,1,1,1,1,0,0,1,1,1,1,1,1, /* 7f */
3049   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
3050   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 9f */
3051   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* af */
3052   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* bf */
3053   /* c0 */ 0,0,1,1,1,1,1,0,0,0,0,0,0,0,0,0, /* cf */
3054   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
3055   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
3056   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0  /* ff */
3057   /*       -------------------------------        */
3058   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3059 };
3060
3061 static char obuf[100];
3062 static char *obufp;
3063 static char *mnemonicendp;
3064 static char scratchbuf[100];
3065 static unsigned char *start_codep;
3066 static unsigned char *insn_codep;
3067 static unsigned char *codep;
3068 static unsigned char *end_codep;
3069 static int last_lock_prefix;
3070 static int last_repz_prefix;
3071 static int last_repnz_prefix;
3072 static int last_data_prefix;
3073 static int last_addr_prefix;
3074 static int last_rex_prefix;
3075 static int last_seg_prefix;
3076 static int fwait_prefix;
3077 /* The PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is mandatory.  */
3078 static int mandatory_prefix;
3079 /* The active segment register prefix.  */
3080 static int active_seg_prefix;
3081 #define MAX_CODE_LENGTH 15
3082 /* We can up to 14 prefixes since the maximum instruction length is
3083    15bytes.  */
3084 static int all_prefixes[MAX_CODE_LENGTH - 1];
3085 static disassemble_info *the_info;
3086 static struct
3087   {
3088     int mod;
3089     int reg;
3090     int rm;
3091   }
3092 modrm;
3093 static unsigned char need_modrm;
3094 static struct
3095   {
3096     int scale;
3097     int index;
3098     int base;
3099   }
3100 sib;
3101 static struct
3102   {
3103     int register_specifier;
3104     int length;
3105     int prefix;
3106     int w;
3107     int evex;
3108     int r;
3109     int v;
3110     int mask_register_specifier;
3111     int zeroing;
3112     int ll;
3113     int b;
3114   }
3115 vex;
3116 static unsigned char need_vex;
3117 static unsigned char need_vex_reg;
3118 static unsigned char vex_w_done;
3119
3120 struct op
3121   {
3122     const char *name;
3123     unsigned int len;
3124   };
3125
3126 /* If we are accessing mod/rm/reg without need_modrm set, then the
3127    values are stale.  Hitting this abort likely indicates that you
3128    need to update onebyte_has_modrm or twobyte_has_modrm.  */
3129 #define MODRM_CHECK  if (!need_modrm) abort ()
3130
3131 static const char **names64;
3132 static const char **names32;
3133 static const char **names16;
3134 static const char **names8;
3135 static const char **names8rex;
3136 static const char **names_seg;
3137 static const char *index64;
3138 static const char *index32;
3139 static const char **index16;
3140 static const char **names_bnd;
3141
3142 static const char *intel_names64[] = {
3143   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3144   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3145 };
3146 static const char *intel_names32[] = {
3147   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3148   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3149 };
3150 static const char *intel_names16[] = {
3151   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3152   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3153 };
3154 static const char *intel_names8[] = {
3155   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3156 };
3157 static const char *intel_names8rex[] = {
3158   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3159   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3160 };
3161 static const char *intel_names_seg[] = {
3162   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3163 };
3164 static const char *intel_index64 = "riz";
3165 static const char *intel_index32 = "eiz";
3166 static const char *intel_index16[] = {
3167   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3168 };
3169
3170 static const char *att_names64[] = {
3171   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3172   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3173 };
3174 static const char *att_names32[] = {
3175   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3176   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3177 };
3178 static const char *att_names16[] = {
3179   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3180   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3181 };
3182 static const char *att_names8[] = {
3183   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3184 };
3185 static const char *att_names8rex[] = {
3186   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3187   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3188 };
3189 static const char *att_names_seg[] = {
3190   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3191 };
3192 static const char *att_index64 = "%riz";
3193 static const char *att_index32 = "%eiz";
3194 static const char *att_index16[] = {
3195   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3196 };
3197
3198 static const char **names_mm;
3199 static const char *intel_names_mm[] = {
3200   "mm0", "mm1", "mm2", "mm3",
3201   "mm4", "mm5", "mm6", "mm7"
3202 };
3203 static const char *att_names_mm[] = {
3204   "%mm0", "%mm1", "%mm2", "%mm3",
3205   "%mm4", "%mm5", "%mm6", "%mm7"
3206 };
3207
3208 static const char *intel_names_bnd[] = {
3209   "bnd0", "bnd1", "bnd2", "bnd3"
3210 };
3211
3212 static const char *att_names_bnd[] = {
3213   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3214 };
3215
3216 static const char **names_xmm;
3217 static const char *intel_names_xmm[] = {
3218   "xmm0", "xmm1", "xmm2", "xmm3",
3219   "xmm4", "xmm5", "xmm6", "xmm7",
3220   "xmm8", "xmm9", "xmm10", "xmm11",
3221   "xmm12", "xmm13", "xmm14", "xmm15",
3222   "xmm16", "xmm17", "xmm18", "xmm19",
3223   "xmm20", "xmm21", "xmm22", "xmm23",
3224   "xmm24", "xmm25", "xmm26", "xmm27",
3225   "xmm28", "xmm29", "xmm30", "xmm31"
3226 };
3227 static const char *att_names_xmm[] = {
3228   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3229   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3230   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3231   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3232   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3233   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3234   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3235   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3236 };
3237
3238 static const char **names_ymm;
3239 static const char *intel_names_ymm[] = {
3240   "ymm0", "ymm1", "ymm2", "ymm3",
3241   "ymm4", "ymm5", "ymm6", "ymm7",
3242   "ymm8", "ymm9", "ymm10", "ymm11",
3243   "ymm12", "ymm13", "ymm14", "ymm15",
3244   "ymm16", "ymm17", "ymm18", "ymm19",
3245   "ymm20", "ymm21", "ymm22", "ymm23",
3246   "ymm24", "ymm25", "ymm26", "ymm27",
3247   "ymm28", "ymm29", "ymm30", "ymm31"
3248 };
3249 static const char *att_names_ymm[] = {
3250   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3251   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3252   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3253   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3254   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3255   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3256   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3257   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3258 };
3259
3260 static const char **names_zmm;
3261 static const char *intel_names_zmm[] = {
3262   "zmm0", "zmm1", "zmm2", "zmm3",
3263   "zmm4", "zmm5", "zmm6", "zmm7",
3264   "zmm8", "zmm9", "zmm10", "zmm11",
3265   "zmm12", "zmm13", "zmm14", "zmm15",
3266   "zmm16", "zmm17", "zmm18", "zmm19",
3267   "zmm20", "zmm21", "zmm22", "zmm23",
3268   "zmm24", "zmm25", "zmm26", "zmm27",
3269   "zmm28", "zmm29", "zmm30", "zmm31"
3270 };
3271 static const char *att_names_zmm[] = {
3272   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3273   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3274   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3275   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3276   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3277   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3278   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3279   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3280 };
3281
3282 static const char **names_mask;
3283 static const char *intel_names_mask[] = {
3284   "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3285 };
3286 static const char *att_names_mask[] = {
3287   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3288 };
3289
3290 static const char *names_rounding[] =
3291 {
3292   "{rn-sae}",
3293   "{rd-sae}",
3294   "{ru-sae}",
3295   "{rz-sae}"
3296 };
3297
3298 static const struct dis386 reg_table[][8] = {
3299   /* REG_80 */
3300   {
3301     { "addA",   { Ebh1, Ib } },
3302     { "orA",    { Ebh1, Ib } },
3303     { "adcA",   { Ebh1, Ib } },
3304     { "sbbA",   { Ebh1, Ib } },
3305     { "andA",   { Ebh1, Ib } },
3306     { "subA",   { Ebh1, Ib } },
3307     { "xorA",   { Ebh1, Ib } },
3308     { "cmpA",   { Eb, Ib } },
3309   },
3310   /* REG_81 */
3311   {
3312     { "addQ",   { Evh1, Iv } },
3313     { "orQ",    { Evh1, Iv } },
3314     { "adcQ",   { Evh1, Iv } },
3315     { "sbbQ",   { Evh1, Iv } },
3316     { "andQ",   { Evh1, Iv } },
3317     { "subQ",   { Evh1, Iv } },
3318     { "xorQ",   { Evh1, Iv } },
3319     { "cmpQ",   { Ev, Iv } },
3320   },
3321   /* REG_82 */
3322   {
3323     { "addQ",   { Evh1, sIb } },
3324     { "orQ",    { Evh1, sIb } },
3325     { "adcQ",   { Evh1, sIb } },
3326     { "sbbQ",   { Evh1, sIb } },
3327     { "andQ",   { Evh1, sIb } },
3328     { "subQ",   { Evh1, sIb } },
3329     { "xorQ",   { Evh1, sIb } },
3330     { "cmpQ",   { Ev, sIb } },
3331   },
3332   /* REG_8F */
3333   {
3334     { "popU",   { stackEv } },
3335     { XOP_8F_TABLE (XOP_09) },
3336     { Bad_Opcode },
3337     { Bad_Opcode },
3338     { Bad_Opcode },
3339     { XOP_8F_TABLE (XOP_09) },
3340   },
3341   /* REG_C0 */
3342   {
3343     { "rolA",   { Eb, Ib } },
3344     { "rorA",   { Eb, Ib } },
3345     { "rclA",   { Eb, Ib } },
3346     { "rcrA",   { Eb, Ib } },
3347     { "shlA",   { Eb, Ib } },
3348     { "shrA",   { Eb, Ib } },
3349     { Bad_Opcode },
3350     { "sarA",   { Eb, Ib } },
3351   },
3352   /* REG_C1 */
3353   {
3354     { "rolQ",   { Ev, Ib } },
3355     { "rorQ",   { Ev, Ib } },
3356     { "rclQ",   { Ev, Ib } },
3357     { "rcrQ",   { Ev, Ib } },
3358     { "shlQ",   { Ev, Ib } },
3359     { "shrQ",   { Ev, Ib } },
3360     { Bad_Opcode },
3361     { "sarQ",   { Ev, Ib } },
3362   },
3363   /* REG_C6 */
3364   {
3365     { "movA",   { Ebh3, Ib } },
3366     { Bad_Opcode },
3367     { Bad_Opcode },
3368     { Bad_Opcode },
3369     { Bad_Opcode },
3370     { Bad_Opcode },
3371     { Bad_Opcode },
3372     { MOD_TABLE (MOD_C6_REG_7) },
3373   },
3374   /* REG_C7 */
3375   {
3376     { "movQ",   { Evh3, Iv } },
3377     { Bad_Opcode },
3378     { Bad_Opcode },
3379     { Bad_Opcode },
3380     { Bad_Opcode },
3381     { Bad_Opcode },
3382     { Bad_Opcode },
3383     { MOD_TABLE (MOD_C7_REG_7) },
3384   },
3385   /* REG_D0 */
3386   {
3387     { "rolA",   { Eb, I1 } },
3388     { "rorA",   { Eb, I1 } },
3389     { "rclA",   { Eb, I1 } },
3390     { "rcrA",   { Eb, I1 } },
3391     { "shlA",   { Eb, I1 } },
3392     { "shrA",   { Eb, I1 } },
3393     { Bad_Opcode },
3394     { "sarA",   { Eb, I1 } },
3395   },
3396   /* REG_D1 */
3397   {
3398     { "rolQ",   { Ev, I1 } },
3399     { "rorQ",   { Ev, I1 } },
3400     { "rclQ",   { Ev, I1 } },
3401     { "rcrQ",   { Ev, I1 } },
3402     { "shlQ",   { Ev, I1 } },
3403     { "shrQ",   { Ev, I1 } },
3404     { Bad_Opcode },
3405     { "sarQ",   { Ev, I1 } },
3406   },
3407   /* REG_D2 */
3408   {
3409     { "rolA",   { Eb, CL } },
3410     { "rorA",   { Eb, CL } },
3411     { "rclA",   { Eb, CL } },
3412     { "rcrA",   { Eb, CL } },
3413     { "shlA",   { Eb, CL } },
3414     { "shrA",   { Eb, CL } },
3415     { Bad_Opcode },
3416     { "sarA",   { Eb, CL } },
3417   },
3418   /* REG_D3 */
3419   {
3420     { "rolQ",   { Ev, CL } },
3421     { "rorQ",   { Ev, CL } },
3422     { "rclQ",   { Ev, CL } },
3423     { "rcrQ",   { Ev, CL } },
3424     { "shlQ",   { Ev, CL } },
3425     { "shrQ",   { Ev, CL } },
3426     { Bad_Opcode },
3427     { "sarQ",   { Ev, CL } },
3428   },
3429   /* REG_F6 */
3430   {
3431     { "testA",  { Eb, Ib } },
3432     { Bad_Opcode },
3433     { "notA",   { Ebh1 } },
3434     { "negA",   { Ebh1 } },
3435     { "mulA",   { Eb } },       /* Don't print the implicit %al register,  */
3436     { "imulA",  { Eb } },       /* to distinguish these opcodes from other */
3437     { "divA",   { Eb } },       /* mul/imul opcodes.  Do the same for div  */
3438     { "idivA",  { Eb } },       /* and idiv for consistency.               */
3439   },
3440   /* REG_F7 */
3441   {
3442     { "testQ",  { Ev, Iv } },
3443     { Bad_Opcode },
3444     { "notQ",   { Evh1 } },
3445     { "negQ",   { Evh1 } },
3446     { "mulQ",   { Ev } },       /* Don't print the implicit register.  */
3447     { "imulQ",  { Ev } },
3448     { "divQ",   { Ev } },
3449     { "idivQ",  { Ev } },
3450   },
3451   /* REG_FE */
3452   {
3453     { "incA",   { Ebh1 } },
3454     { "decA",   { Ebh1 } },
3455   },
3456   /* REG_FF */
3457   {
3458     { "incQ",   { Evh1 } },
3459     { "decQ",   { Evh1 } },
3460     { "call{T|}", { indirEv, BND } },
3461     { MOD_TABLE (MOD_FF_REG_3) },
3462     { "jmp{T|}", { indirEv, BND } },
3463     { MOD_TABLE (MOD_FF_REG_5) },
3464     { "pushU",  { stackEv } },
3465     { Bad_Opcode },
3466   },
3467   /* REG_0F00 */
3468   {
3469     { "sldtD",  { Sv } },
3470     { "strD",   { Sv } },
3471     { "lldt",   { Ew } },
3472     { "ltr",    { Ew } },
3473     { "verr",   { Ew } },
3474     { "verw",   { Ew } },
3475     { Bad_Opcode },
3476     { Bad_Opcode },
3477   },
3478   /* REG_0F01 */
3479   {
3480     { MOD_TABLE (MOD_0F01_REG_0) },
3481     { MOD_TABLE (MOD_0F01_REG_1) },
3482     { MOD_TABLE (MOD_0F01_REG_2) },
3483     { MOD_TABLE (MOD_0F01_REG_3) },
3484     { "smswD",  { Sv } },
3485     { Bad_Opcode },
3486     { "lmsw",   { Ew } },
3487     { MOD_TABLE (MOD_0F01_REG_7) },
3488   },
3489   /* REG_0F0D */
3490   {
3491     { "prefetch",       { Mb } },
3492     { "prefetchw",      { Mb } },
3493     { "prefetchwt1",    { Mb } },
3494     { "prefetch",       { Mb } },
3495     { "prefetch",       { Mb } },
3496     { "prefetch",       { Mb } },
3497     { "prefetch",       { Mb } },
3498     { "prefetch",       { Mb } },
3499   },
3500   /* REG_0F18 */
3501   {
3502     { MOD_TABLE (MOD_0F18_REG_0) },
3503     { MOD_TABLE (MOD_0F18_REG_1) },
3504     { MOD_TABLE (MOD_0F18_REG_2) },
3505     { MOD_TABLE (MOD_0F18_REG_3) },
3506     { MOD_TABLE (MOD_0F18_REG_4) },
3507     { MOD_TABLE (MOD_0F18_REG_5) },
3508     { MOD_TABLE (MOD_0F18_REG_6) },
3509     { MOD_TABLE (MOD_0F18_REG_7) },
3510   },
3511   /* REG_0F71 */
3512   {
3513     { Bad_Opcode },
3514     { Bad_Opcode },
3515     { MOD_TABLE (MOD_0F71_REG_2) },
3516     { Bad_Opcode },
3517     { MOD_TABLE (MOD_0F71_REG_4) },
3518     { Bad_Opcode },
3519     { MOD_TABLE (MOD_0F71_REG_6) },
3520   },
3521   /* REG_0F72 */
3522   {
3523     { Bad_Opcode },
3524     { Bad_Opcode },
3525     { MOD_TABLE (MOD_0F72_REG_2) },
3526     { Bad_Opcode },
3527     { MOD_TABLE (MOD_0F72_REG_4) },
3528     { Bad_Opcode },
3529     { MOD_TABLE (MOD_0F72_REG_6) },
3530   },
3531   /* REG_0F73 */
3532   {
3533     { Bad_Opcode },
3534     { Bad_Opcode },
3535     { MOD_TABLE (MOD_0F73_REG_2) },
3536     { MOD_TABLE (MOD_0F73_REG_3) },
3537     { Bad_Opcode },
3538     { Bad_Opcode },
3539     { MOD_TABLE (MOD_0F73_REG_6) },
3540     { MOD_TABLE (MOD_0F73_REG_7) },
3541   },
3542   /* REG_0FA6 */
3543   {
3544     { "montmul",        { { OP_0f07, 0 } } },
3545     { "xsha1",          { { OP_0f07, 0 } } },
3546     { "xsha256",        { { OP_0f07, 0 } } },
3547   },
3548   /* REG_0FA7 */
3549   {
3550     { "xstore-rng",     { { OP_0f07, 0 } } },
3551     { "xcrypt-ecb",     { { OP_0f07, 0 } } },
3552     { "xcrypt-cbc",     { { OP_0f07, 0 } } },
3553     { "xcrypt-ctr",     { { OP_0f07, 0 } } },
3554     { "xcrypt-cfb",     { { OP_0f07, 0 } } },
3555     { "xcrypt-ofb",     { { OP_0f07, 0 } } },
3556   },
3557   /* REG_0FAE */
3558   {
3559     { MOD_TABLE (MOD_0FAE_REG_0) },
3560     { MOD_TABLE (MOD_0FAE_REG_1) },
3561     { MOD_TABLE (MOD_0FAE_REG_2) },
3562     { MOD_TABLE (MOD_0FAE_REG_3) },
3563     { MOD_TABLE (MOD_0FAE_REG_4) },
3564     { MOD_TABLE (MOD_0FAE_REG_5) },
3565     { MOD_TABLE (MOD_0FAE_REG_6) },
3566     { MOD_TABLE (MOD_0FAE_REG_7) },
3567   },
3568   /* REG_0FBA */
3569   {
3570     { Bad_Opcode },
3571     { Bad_Opcode },
3572     { Bad_Opcode },
3573     { Bad_Opcode },
3574     { "btQ",    { Ev, Ib } },
3575     { "btsQ",   { Evh1, Ib } },
3576     { "btrQ",   { Evh1, Ib } },
3577     { "btcQ",   { Evh1, Ib } },
3578   },
3579   /* REG_0FC7 */
3580   {
3581     { Bad_Opcode },
3582     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } },
3583     { Bad_Opcode },
3584     { MOD_TABLE (MOD_0FC7_REG_3) },
3585     { MOD_TABLE (MOD_0FC7_REG_4) },
3586     { MOD_TABLE (MOD_0FC7_REG_5) },
3587     { MOD_TABLE (MOD_0FC7_REG_6) },
3588     { MOD_TABLE (MOD_0FC7_REG_7) },
3589   },
3590   /* REG_VEX_0F71 */
3591   {
3592     { Bad_Opcode },
3593     { Bad_Opcode },
3594     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3595     { Bad_Opcode },
3596     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3597     { Bad_Opcode },
3598     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3599   },
3600   /* REG_VEX_0F72 */
3601   {
3602     { Bad_Opcode },
3603     { Bad_Opcode },
3604     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3605     { Bad_Opcode },
3606     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3607     { Bad_Opcode },
3608     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3609   },
3610   /* REG_VEX_0F73 */
3611   {
3612     { Bad_Opcode },
3613     { Bad_Opcode },
3614     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3615     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3616     { Bad_Opcode },
3617     { Bad_Opcode },
3618     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3619     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3620   },
3621   /* REG_VEX_0FAE */
3622   {
3623     { Bad_Opcode },
3624     { Bad_Opcode },
3625     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3626     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3627   },
3628   /* REG_VEX_0F38F3 */
3629   {
3630     { Bad_Opcode },
3631     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3632     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3633     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3634   },
3635   /* REG_XOP_LWPCB */
3636   {
3637     { "llwpcb", { { OP_LWPCB_E, 0 } } },
3638     { "slwpcb", { { OP_LWPCB_E, 0 } } },
3639   },
3640   /* REG_XOP_LWP */
3641   {
3642     { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq } },
3643     { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq } },
3644   },
3645   /* REG_XOP_TBM_01 */
3646   {
3647     { Bad_Opcode },
3648     { "blcfill",        { { OP_LWP_E, 0 }, Ev } },
3649     { "blsfill",        { { OP_LWP_E, 0 }, Ev } },
3650     { "blcs",   { { OP_LWP_E, 0 }, Ev } },
3651     { "tzmsk",  { { OP_LWP_E, 0 }, Ev } },
3652     { "blcic",  { { OP_LWP_E, 0 }, Ev } },
3653     { "blsic",  { { OP_LWP_E, 0 }, Ev } },
3654     { "t1mskc", { { OP_LWP_E, 0 }, Ev } },
3655   },
3656   /* REG_XOP_TBM_02 */
3657   {
3658     { Bad_Opcode },
3659     { "blcmsk", { { OP_LWP_E, 0 }, Ev } },
3660     { Bad_Opcode },
3661     { Bad_Opcode },
3662     { Bad_Opcode },
3663     { Bad_Opcode },
3664     { "blci",   { { OP_LWP_E, 0 }, Ev } },
3665   },
3666 #define NEED_REG_TABLE
3667 #include "i386-dis-evex.h"
3668 #undef NEED_REG_TABLE
3669 };
3670
3671 static const struct dis386 prefix_table[][4] = {
3672   /* PREFIX_90 */
3673   {
3674     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
3675     { "pause", { XX } },
3676     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
3677   },
3678
3679   /* PREFIX_0F10 */
3680   {
3681     { "movups", { XM, EXx } },
3682     { "movss",  { XM, EXd } },
3683     { "movupd", { XM, EXx } },
3684     { "movsd",  { XM, EXq } },
3685   },
3686
3687   /* PREFIX_0F11 */
3688   {
3689     { "movups", { EXxS, XM } },
3690     { "movss",  { EXdS, XM } },
3691     { "movupd", { EXxS, XM } },
3692     { "movsd",  { EXqS, XM } },
3693   },
3694
3695   /* PREFIX_0F12 */
3696   {
3697     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3698     { "movsldup", { XM, EXx } },
3699     { "movlpd", { XM, EXq } },
3700     { "movddup", { XM, EXq } },
3701   },
3702
3703   /* PREFIX_0F16 */
3704   {
3705     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3706     { "movshdup", { XM, EXx } },
3707     { "movhpd", { XM, EXq } },
3708   },
3709
3710   /* PREFIX_0F1A */
3711   {
3712     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3713     { "bndcl",  { Gbnd, Ev_bnd } },
3714     { "bndmov", { Gbnd, Ebnd } },
3715     { "bndcu",  { Gbnd, Ev_bnd } },
3716   },
3717
3718   /* PREFIX_0F1B */
3719   {
3720     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3721     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3722     { "bndmov", { Ebnd, Gbnd } },
3723     { "bndcn",  { Gbnd, Ev_bnd } },
3724   },
3725
3726   /* PREFIX_0F2A */
3727   {
3728     { "cvtpi2ps", { XM, EMCq } },
3729     { "cvtsi2ss%LQ", { XM, Ev } },
3730     { "cvtpi2pd", { XM, EMCq } },
3731     { "cvtsi2sd%LQ", { XM, Ev } },
3732   },
3733
3734   /* PREFIX_0F2B */
3735   {
3736     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3737     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3738     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3739     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3740   },
3741
3742   /* PREFIX_0F2C */
3743   {
3744     { "cvttps2pi", { MXC, EXq } },
3745     { "cvttss2siY", { Gv, EXd } },
3746     { "cvttpd2pi", { MXC, EXx } },
3747     { "cvttsd2siY", { Gv, EXq } },
3748   },
3749
3750   /* PREFIX_0F2D */
3751   {
3752     { "cvtps2pi", { MXC, EXq } },
3753     { "cvtss2siY", { Gv, EXd } },
3754     { "cvtpd2pi", { MXC, EXx } },
3755     { "cvtsd2siY", { Gv, EXq } },
3756   },
3757
3758   /* PREFIX_0F2E */
3759   {
3760     { "ucomiss",{ XM, EXd } },
3761     { Bad_Opcode },
3762     { "ucomisd",{ XM, EXq } },
3763   },
3764
3765   /* PREFIX_0F2F */
3766   {
3767     { "comiss", { XM, EXd } },
3768     { Bad_Opcode },
3769     { "comisd", { XM, EXq } },
3770   },
3771
3772   /* PREFIX_0F51 */
3773   {
3774     { "sqrtps", { XM, EXx } },
3775     { "sqrtss", { XM, EXd } },
3776     { "sqrtpd", { XM, EXx } },
3777     { "sqrtsd", { XM, EXq } },
3778   },
3779
3780   /* PREFIX_0F52 */
3781   {
3782     { "rsqrtps",{ XM, EXx } },
3783     { "rsqrtss",{ XM, EXd } },
3784   },
3785
3786   /* PREFIX_0F53 */
3787   {
3788     { "rcpps",  { XM, EXx } },
3789     { "rcpss",  { XM, EXd } },
3790   },
3791
3792   /* PREFIX_0F58 */
3793   {
3794     { "addps", { XM, EXx } },
3795     { "addss", { XM, EXd } },
3796     { "addpd", { XM, EXx } },
3797     { "addsd", { XM, EXq } },
3798   },
3799
3800   /* PREFIX_0F59 */
3801   {
3802     { "mulps",  { XM, EXx } },
3803     { "mulss",  { XM, EXd } },
3804     { "mulpd",  { XM, EXx } },
3805     { "mulsd",  { XM, EXq } },
3806   },
3807
3808   /* PREFIX_0F5A */
3809   {
3810     { "cvtps2pd", { XM, EXq } },
3811     { "cvtss2sd", { XM, EXd } },
3812     { "cvtpd2ps", { XM, EXx } },
3813     { "cvtsd2ss", { XM, EXq } },
3814   },
3815
3816   /* PREFIX_0F5B */
3817   {
3818     { "cvtdq2ps", { XM, EXx } },
3819     { "cvttps2dq", { XM, EXx } },
3820     { "cvtps2dq", { XM, EXx } },
3821   },
3822
3823   /* PREFIX_0F5C */
3824   {
3825     { "subps",  { XM, EXx } },
3826     { "subss",  { XM, EXd } },
3827     { "subpd",  { XM, EXx } },
3828     { "subsd",  { XM, EXq } },
3829   },
3830
3831   /* PREFIX_0F5D */
3832   {
3833     { "minps",  { XM, EXx } },
3834     { "minss",  { XM, EXd } },
3835     { "minpd",  { XM, EXx } },
3836     { "minsd",  { XM, EXq } },
3837   },
3838
3839   /* PREFIX_0F5E */
3840   {
3841     { "divps",  { XM, EXx } },
3842     { "divss",  { XM, EXd } },
3843     { "divpd",  { XM, EXx } },
3844     { "divsd",  { XM, EXq } },
3845   },
3846
3847   /* PREFIX_0F5F */
3848   {
3849     { "maxps",  { XM, EXx } },
3850     { "maxss",  { XM, EXd } },
3851     { "maxpd",  { XM, EXx } },
3852     { "maxsd",  { XM, EXq } },
3853   },
3854
3855   /* PREFIX_0F60 */
3856   {
3857     { "punpcklbw",{ MX, EMd } },
3858     { Bad_Opcode },
3859     { "punpcklbw",{ MX, EMx } },
3860   },
3861
3862   /* PREFIX_0F61 */
3863   {
3864     { "punpcklwd",{ MX, EMd } },
3865     { Bad_Opcode },
3866     { "punpcklwd",{ MX, EMx } },
3867   },
3868
3869   /* PREFIX_0F62 */
3870   {
3871     { "punpckldq",{ MX, EMd } },
3872     { Bad_Opcode },
3873     { "punpckldq",{ MX, EMx } },
3874   },
3875
3876   /* PREFIX_0F6C */
3877   {
3878     { Bad_Opcode },
3879     { Bad_Opcode },
3880     { "punpcklqdq", { XM, EXx } },
3881   },
3882
3883   /* PREFIX_0F6D */
3884   {
3885     { Bad_Opcode },
3886     { Bad_Opcode },
3887     { "punpckhqdq", { XM, EXx } },
3888   },
3889
3890   /* PREFIX_0F6F */
3891   {
3892     { "movq",   { MX, EM } },
3893     { "movdqu", { XM, EXx } },
3894     { "movdqa", { XM, EXx } },
3895   },
3896
3897   /* PREFIX_0F70 */
3898   {
3899     { "pshufw", { MX, EM, Ib } },
3900     { "pshufhw",{ XM, EXx, Ib } },
3901     { "pshufd", { XM, EXx, Ib } },
3902     { "pshuflw",{ XM, EXx, Ib } },
3903   },
3904
3905   /* PREFIX_0F73_REG_3 */
3906   {
3907     { Bad_Opcode },
3908     { Bad_Opcode },
3909     { "psrldq", { XS, Ib } },
3910   },
3911
3912   /* PREFIX_0F73_REG_7 */
3913   {
3914     { Bad_Opcode },
3915     { Bad_Opcode },
3916     { "pslldq", { XS, Ib } },
3917   },
3918
3919   /* PREFIX_0F78 */
3920   {
3921     {"vmread",  { Em, Gm } },
3922     { Bad_Opcode },
3923     {"extrq",   { XS, Ib, Ib } },
3924     {"insertq", { XM, XS, Ib, Ib } },
3925   },
3926
3927   /* PREFIX_0F79 */
3928   {
3929     {"vmwrite", { Gm, Em } },
3930     { Bad_Opcode },
3931     {"extrq",   { XM, XS } },
3932     {"insertq", { XM, XS } },
3933   },
3934
3935   /* PREFIX_0F7C */
3936   {
3937     { Bad_Opcode },
3938     { Bad_Opcode },
3939     { "haddpd", { XM, EXx } },
3940     { "haddps", { XM, EXx } },
3941   },
3942
3943   /* PREFIX_0F7D */
3944   {
3945     { Bad_Opcode },
3946     { Bad_Opcode },
3947     { "hsubpd", { XM, EXx } },
3948     { "hsubps", { XM, EXx } },
3949   },
3950
3951   /* PREFIX_0F7E */
3952   {
3953     { "movK",   { Edq, MX } },
3954     { "movq",   { XM, EXq } },
3955     { "movK",   { Edq, XM } },
3956   },
3957
3958   /* PREFIX_0F7F */
3959   {
3960     { "movq",   { EMS, MX } },
3961     { "movdqu", { EXxS, XM } },
3962     { "movdqa", { EXxS, XM } },
3963   },
3964
3965   /* PREFIX_0FAE_REG_0 */
3966   {
3967     { Bad_Opcode },
3968     { "rdfsbase", { Ev } },
3969   },
3970
3971   /* PREFIX_0FAE_REG_1 */
3972   {
3973     { Bad_Opcode },
3974     { "rdgsbase", { Ev } },
3975   },
3976
3977   /* PREFIX_0FAE_REG_2 */
3978   {
3979     { Bad_Opcode },
3980     { "wrfsbase", { Ev } },
3981   },
3982
3983   /* PREFIX_0FAE_REG_3 */
3984   {
3985     { Bad_Opcode },
3986     { "wrgsbase", { Ev } },
3987   },
3988
3989   /* PREFIX_0FAE_REG_6 */
3990   {
3991     { "xsaveopt",      { FXSAVE } },
3992     { Bad_Opcode },
3993     { "clwb",   { Mb } },
3994   },
3995
3996   /* PREFIX_0FAE_REG_7 */
3997   {
3998     { "clflush",        { Mb } },
3999     { Bad_Opcode },
4000     { "clflushopt",     { Mb } },
4001   },
4002
4003   /* PREFIX_RM_0_0FAE_REG_7 */
4004   {
4005     { "sfence",         { Skip_MODRM } },
4006     { Bad_Opcode },
4007     { "pcommit",                { Skip_MODRM } },
4008   },
4009
4010   /* PREFIX_0FB8 */
4011   {
4012     { Bad_Opcode },
4013     { "popcntS", { Gv, Ev } },
4014   },
4015
4016   /* PREFIX_0FBC */
4017   {
4018     { "bsfS",   { Gv, Ev } },
4019     { "tzcntS", { Gv, Ev } },
4020     { "bsfS",   { Gv, Ev } },
4021   },
4022
4023   /* PREFIX_0FBD */
4024   {
4025     { "bsrS",   { Gv, Ev } },
4026     { "lzcntS", { Gv, Ev } },
4027     { "bsrS",   { Gv, Ev } },
4028   },
4029
4030   /* PREFIX_0FC2 */
4031   {
4032     { "cmpps",  { XM, EXx, CMP } },
4033     { "cmpss",  { XM, EXd, CMP } },
4034     { "cmppd",  { XM, EXx, CMP } },
4035     { "cmpsd",  { XM, EXq, CMP } },
4036   },
4037
4038   /* PREFIX_0FC3 */
4039   {
4040     { "movntiS", { Ma, Gv } },
4041   },
4042
4043   /* PREFIX_0FC7_REG_6 */
4044   {
4045     { "vmptrld",{ Mq } },
4046     { "vmxon",  { Mq } },
4047     { "vmclear",{ Mq } },
4048   },
4049
4050   /* PREFIX_0FD0 */
4051   {
4052     { Bad_Opcode },
4053     { Bad_Opcode },
4054     { "addsubpd", { XM, EXx } },
4055     { "addsubps", { XM, EXx } },
4056   },
4057
4058   /* PREFIX_0FD6 */
4059   {
4060     { Bad_Opcode },
4061     { "movq2dq",{ XM, MS } },
4062     { "movq",   { EXqS, XM } },
4063     { "movdq2q",{ MX, XS } },
4064   },
4065
4066   /* PREFIX_0FE6 */
4067   {
4068     { Bad_Opcode },
4069     { "cvtdq2pd", { XM, EXq } },
4070     { "cvttpd2dq", { XM, EXx } },
4071     { "cvtpd2dq", { XM, EXx } },
4072   },
4073
4074   /* PREFIX_0FE7 */
4075   {
4076     { "movntq", { Mq, MX } },
4077     { Bad_Opcode },
4078     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
4079   },
4080
4081   /* PREFIX_0FF0 */
4082   {
4083     { Bad_Opcode },
4084     { Bad_Opcode },
4085     { Bad_Opcode },
4086     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4087   },
4088
4089   /* PREFIX_0FF7 */
4090   {
4091     { "maskmovq", { MX, MS } },
4092     { Bad_Opcode },
4093     { "maskmovdqu", { XM, XS } },
4094   },
4095
4096   /* PREFIX_0F3810 */
4097   {
4098     { Bad_Opcode },
4099     { Bad_Opcode },
4100     { "pblendvb", { XM, EXx, XMM0 } },
4101   },
4102
4103   /* PREFIX_0F3814 */
4104   {
4105     { Bad_Opcode },
4106     { Bad_Opcode },
4107     { "blendvps", { XM, EXx, XMM0 } },
4108   },
4109
4110   /* PREFIX_0F3815 */
4111   {
4112     { Bad_Opcode },
4113     { Bad_Opcode },
4114     { "blendvpd", { XM, EXx, XMM0 } },
4115   },
4116
4117   /* PREFIX_0F3817 */
4118   {
4119     { Bad_Opcode },
4120     { Bad_Opcode },
4121     { "ptest",  { XM, EXx } },
4122   },
4123
4124   /* PREFIX_0F3820 */
4125   {
4126     { Bad_Opcode },
4127     { Bad_Opcode },
4128     { "pmovsxbw", { XM, EXq } },
4129   },
4130
4131   /* PREFIX_0F3821 */
4132   {
4133     { Bad_Opcode },
4134     { Bad_Opcode },
4135     { "pmovsxbd", { XM, EXd } },
4136   },
4137
4138   /* PREFIX_0F3822 */
4139   {
4140     { Bad_Opcode },
4141     { Bad_Opcode },
4142     { "pmovsxbq", { XM, EXw } },
4143   },
4144
4145   /* PREFIX_0F3823 */
4146   {
4147     { Bad_Opcode },
4148     { Bad_Opcode },
4149     { "pmovsxwd", { XM, EXq } },
4150   },
4151
4152   /* PREFIX_0F3824 */
4153   {
4154     { Bad_Opcode },
4155     { Bad_Opcode },
4156     { "pmovsxwq", { XM, EXd } },
4157   },
4158
4159   /* PREFIX_0F3825 */
4160   {
4161     { Bad_Opcode },
4162     { Bad_Opcode },
4163     { "pmovsxdq", { XM, EXq } },
4164   },
4165
4166   /* PREFIX_0F3828 */
4167   {
4168     { Bad_Opcode },
4169     { Bad_Opcode },
4170     { "pmuldq", { XM, EXx } },
4171   },
4172
4173   /* PREFIX_0F3829 */
4174   {
4175     { Bad_Opcode },
4176     { Bad_Opcode },
4177     { "pcmpeqq", { XM, EXx } },
4178   },
4179
4180   /* PREFIX_0F382A */
4181   {
4182     { Bad_Opcode },
4183     { Bad_Opcode },
4184     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4185   },
4186
4187   /* PREFIX_0F382B */
4188   {
4189     { Bad_Opcode },
4190     { Bad_Opcode },
4191     { "packusdw", { XM, EXx } },
4192   },
4193
4194   /* PREFIX_0F3830 */
4195   {
4196     { Bad_Opcode },
4197     { Bad_Opcode },
4198     { "pmovzxbw", { XM, EXq } },
4199   },
4200
4201   /* PREFIX_0F3831 */
4202   {
4203     { Bad_Opcode },
4204     { Bad_Opcode },
4205     { "pmovzxbd", { XM, EXd } },
4206   },
4207
4208   /* PREFIX_0F3832 */
4209   {
4210     { Bad_Opcode },
4211     { Bad_Opcode },
4212     { "pmovzxbq", { XM, EXw } },
4213   },
4214
4215   /* PREFIX_0F3833 */
4216   {
4217     { Bad_Opcode },
4218     { Bad_Opcode },
4219     { "pmovzxwd", { XM, EXq } },
4220   },
4221
4222   /* PREFIX_0F3834 */
4223   {
4224     { Bad_Opcode },
4225     { Bad_Opcode },
4226     { "pmovzxwq", { XM, EXd } },
4227   },
4228
4229   /* PREFIX_0F3835 */
4230   {
4231     { Bad_Opcode },
4232     { Bad_Opcode },
4233     { "pmovzxdq", { XM, EXq } },
4234   },
4235
4236   /* PREFIX_0F3837 */
4237   {
4238     { Bad_Opcode },
4239     { Bad_Opcode },
4240     { "pcmpgtq", { XM, EXx } },
4241   },
4242
4243   /* PREFIX_0F3838 */
4244   {
4245     { Bad_Opcode },
4246     { Bad_Opcode },
4247     { "pminsb", { XM, EXx } },
4248   },
4249
4250   /* PREFIX_0F3839 */
4251   {
4252     { Bad_Opcode },
4253     { Bad_Opcode },
4254     { "pminsd", { XM, EXx } },
4255   },
4256
4257   /* PREFIX_0F383A */
4258   {
4259     { Bad_Opcode },
4260     { Bad_Opcode },
4261     { "pminuw", { XM, EXx } },
4262   },
4263
4264   /* PREFIX_0F383B */
4265   {
4266     { Bad_Opcode },
4267     { Bad_Opcode },
4268     { "pminud", { XM, EXx } },
4269   },
4270
4271   /* PREFIX_0F383C */
4272   {
4273     { Bad_Opcode },
4274     { Bad_Opcode },
4275     { "pmaxsb", { XM, EXx } },
4276   },
4277
4278   /* PREFIX_0F383D */
4279   {
4280     { Bad_Opcode },
4281     { Bad_Opcode },
4282     { "pmaxsd", { XM, EXx } },
4283   },
4284
4285   /* PREFIX_0F383E */
4286   {
4287     { Bad_Opcode },
4288     { Bad_Opcode },
4289     { "pmaxuw", { XM, EXx } },
4290   },
4291
4292   /* PREFIX_0F383F */
4293   {
4294     { Bad_Opcode },
4295     { Bad_Opcode },
4296     { "pmaxud", { XM, EXx } },
4297   },
4298
4299   /* PREFIX_0F3840 */
4300   {
4301     { Bad_Opcode },
4302     { Bad_Opcode },
4303     { "pmulld", { XM, EXx } },
4304   },
4305
4306   /* PREFIX_0F3841 */
4307   {
4308     { Bad_Opcode },
4309     { Bad_Opcode },
4310     { "phminposuw", { XM, EXx } },
4311   },
4312
4313   /* PREFIX_0F3880 */
4314   {
4315     { Bad_Opcode },
4316     { Bad_Opcode },
4317     { "invept", { Gm, Mo } },
4318   },
4319
4320   /* PREFIX_0F3881 */
4321   {
4322     { Bad_Opcode },
4323     { Bad_Opcode },
4324     { "invvpid", { Gm, Mo } },
4325   },
4326
4327   /* PREFIX_0F3882 */
4328   {
4329     { Bad_Opcode },
4330     { Bad_Opcode },
4331     { "invpcid", { Gm, M } },
4332   },
4333
4334   /* PREFIX_0F38C8 */
4335   {
4336     { "sha1nexte", { XM, EXxmm } },
4337   },
4338
4339   /* PREFIX_0F38C9 */
4340   {
4341     { "sha1msg1", { XM, EXxmm } },
4342   },
4343
4344   /* PREFIX_0F38CA */
4345   {
4346     { "sha1msg2", { XM, EXxmm } },
4347   },
4348
4349   /* PREFIX_0F38CB */
4350   {
4351     { "sha256rnds2", { XM, EXxmm, XMM0 } },
4352   },
4353
4354   /* PREFIX_0F38CC */
4355   {
4356     { "sha256msg1", { XM, EXxmm } },
4357   },
4358
4359   /* PREFIX_0F38CD */
4360   {
4361     { "sha256msg2", { XM, EXxmm } },
4362   },
4363
4364   /* PREFIX_0F38DB */
4365   {
4366     { Bad_Opcode },
4367     { Bad_Opcode },
4368     { "aesimc", { XM, EXx } },
4369   },
4370
4371   /* PREFIX_0F38DC */
4372   {
4373     { Bad_Opcode },
4374     { Bad_Opcode },
4375     { "aesenc", { XM, EXx } },
4376   },
4377
4378   /* PREFIX_0F38DD */
4379   {
4380     { Bad_Opcode },
4381     { Bad_Opcode },
4382     { "aesenclast", { XM, EXx } },
4383   },
4384
4385   /* PREFIX_0F38DE */
4386   {
4387     { Bad_Opcode },
4388     { Bad_Opcode },
4389     { "aesdec", { XM, EXx } },
4390   },
4391
4392   /* PREFIX_0F38DF */
4393   {
4394     { Bad_Opcode },
4395     { Bad_Opcode },
4396     { "aesdeclast", { XM, EXx } },
4397   },
4398
4399   /* PREFIX_0F38F0 */
4400   {
4401     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
4402     { Bad_Opcode },
4403     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
4404     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } } },
4405   },
4406
4407   /* PREFIX_0F38F1 */
4408   {
4409     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
4410     { Bad_Opcode },
4411     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
4412     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } } },
4413   },
4414
4415   /* PREFIX_0F38F6 */
4416   {
4417     { Bad_Opcode },
4418     { "adoxS",  { Gdq, Edq} },
4419     { "adcxS",  { Gdq, Edq} },
4420     { Bad_Opcode },
4421   },
4422
4423   /* PREFIX_0F3A08 */
4424   {
4425     { Bad_Opcode },
4426     { Bad_Opcode },
4427     { "roundps", { XM, EXx, Ib } },
4428   },
4429
4430   /* PREFIX_0F3A09 */
4431   {
4432     { Bad_Opcode },
4433     { Bad_Opcode },
4434     { "roundpd", { XM, EXx, Ib } },
4435   },
4436
4437   /* PREFIX_0F3A0A */
4438   {
4439     { Bad_Opcode },
4440     { Bad_Opcode },
4441     { "roundss", { XM, EXd, Ib } },
4442   },
4443
4444   /* PREFIX_0F3A0B */
4445   {
4446     { Bad_Opcode },
4447     { Bad_Opcode },
4448     { "roundsd", { XM, EXq, Ib } },
4449   },
4450
4451   /* PREFIX_0F3A0C */
4452   {
4453     { Bad_Opcode },
4454     { Bad_Opcode },
4455     { "blendps", { XM, EXx, Ib } },
4456   },
4457
4458   /* PREFIX_0F3A0D */
4459   {
4460     { Bad_Opcode },
4461     { Bad_Opcode },
4462     { "blendpd", { XM, EXx, Ib } },
4463   },
4464
4465   /* PREFIX_0F3A0E */
4466   {
4467     { Bad_Opcode },
4468     { Bad_Opcode },
4469     { "pblendw", { XM, EXx, Ib } },
4470   },
4471
4472   /* PREFIX_0F3A14 */
4473   {
4474     { Bad_Opcode },
4475     { Bad_Opcode },
4476     { "pextrb", { Edqb, XM, Ib } },
4477   },
4478
4479   /* PREFIX_0F3A15 */
4480   {
4481     { Bad_Opcode },
4482     { Bad_Opcode },
4483     { "pextrw", { Edqw, XM, Ib } },
4484   },
4485
4486   /* PREFIX_0F3A16 */
4487   {
4488     { Bad_Opcode },
4489     { Bad_Opcode },
4490     { "pextrK", { Edq, XM, Ib } },
4491   },
4492
4493   /* PREFIX_0F3A17 */
4494   {
4495     { Bad_Opcode },
4496     { Bad_Opcode },
4497     { "extractps", { Edqd, XM, Ib } },
4498   },
4499
4500   /* PREFIX_0F3A20 */
4501   {
4502     { Bad_Opcode },
4503     { Bad_Opcode },
4504     { "pinsrb", { XM, Edqb, Ib } },
4505   },
4506
4507   /* PREFIX_0F3A21 */
4508   {
4509     { Bad_Opcode },
4510     { Bad_Opcode },
4511     { "insertps", { XM, EXd, Ib } },
4512   },
4513
4514   /* PREFIX_0F3A22 */
4515   {
4516     { Bad_Opcode },
4517     { Bad_Opcode },
4518     { "pinsrK", { XM, Edq, Ib } },
4519   },
4520
4521   /* PREFIX_0F3A40 */
4522   {
4523     { Bad_Opcode },
4524     { Bad_Opcode },
4525     { "dpps",   { XM, EXx, Ib } },
4526   },
4527
4528   /* PREFIX_0F3A41 */
4529   {
4530     { Bad_Opcode },
4531     { Bad_Opcode },
4532     { "dppd",   { XM, EXx, Ib } },
4533   },
4534
4535   /* PREFIX_0F3A42 */
4536   {
4537     { Bad_Opcode },
4538     { Bad_Opcode },
4539     { "mpsadbw", { XM, EXx, Ib } },
4540   },
4541
4542   /* PREFIX_0F3A44 */
4543   {
4544     { Bad_Opcode },
4545     { Bad_Opcode },
4546     { "pclmulqdq", { XM, EXx, PCLMUL } },
4547   },
4548
4549   /* PREFIX_0F3A60 */
4550   {
4551     { Bad_Opcode },
4552     { Bad_Opcode },
4553     { "pcmpestrm", { XM, EXx, Ib } },
4554   },
4555
4556   /* PREFIX_0F3A61 */
4557   {
4558     { Bad_Opcode },
4559     { Bad_Opcode },
4560     { "pcmpestri", { XM, EXx, Ib } },
4561   },
4562
4563   /* PREFIX_0F3A62 */
4564   {
4565     { Bad_Opcode },
4566     { Bad_Opcode },
4567     { "pcmpistrm", { XM, EXx, Ib } },
4568   },
4569
4570   /* PREFIX_0F3A63 */
4571   {
4572     { Bad_Opcode },
4573     { Bad_Opcode },
4574     { "pcmpistri", { XM, EXx, Ib } },
4575   },
4576
4577   /* PREFIX_0F3ACC */
4578   {
4579     { "sha1rnds4", { XM, EXxmm, Ib } },
4580   },
4581
4582   /* PREFIX_0F3ADF */
4583   {
4584     { Bad_Opcode },
4585     { Bad_Opcode },
4586     { "aeskeygenassist", { XM, EXx, Ib } },
4587   },
4588
4589   /* PREFIX_VEX_0F10 */
4590   {
4591     { VEX_W_TABLE (VEX_W_0F10_P_0) },
4592     { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) },
4593     { VEX_W_TABLE (VEX_W_0F10_P_2) },
4594     { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) },
4595   },
4596
4597   /* PREFIX_VEX_0F11 */
4598   {
4599     { VEX_W_TABLE (VEX_W_0F11_P_0) },
4600     { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) },
4601     { VEX_W_TABLE (VEX_W_0F11_P_2) },
4602     { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) },
4603   },
4604
4605   /* PREFIX_VEX_0F12 */
4606   {
4607     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4608     { VEX_W_TABLE (VEX_W_0F12_P_1) },
4609     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
4610     { VEX_W_TABLE (VEX_W_0F12_P_3) },
4611   },
4612
4613   /* PREFIX_VEX_0F16 */
4614   {
4615     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4616     { VEX_W_TABLE (VEX_W_0F16_P_1) },
4617     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
4618   },
4619
4620   /* PREFIX_VEX_0F2A */
4621   {
4622     { Bad_Opcode },
4623     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) },
4624     { Bad_Opcode },
4625     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) },
4626   },
4627
4628   /* PREFIX_VEX_0F2C */
4629   {
4630     { Bad_Opcode },
4631     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) },
4632     { Bad_Opcode },
4633     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) },
4634   },
4635
4636   /* PREFIX_VEX_0F2D */
4637   {
4638     { Bad_Opcode },
4639     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) },
4640     { Bad_Opcode },
4641     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) },
4642   },
4643
4644   /* PREFIX_VEX_0F2E */
4645   {
4646     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) },
4647     { Bad_Opcode },
4648     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) },
4649   },
4650
4651   /* PREFIX_VEX_0F2F */
4652   {
4653     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) },
4654     { Bad_Opcode },
4655     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) },
4656   },
4657
4658   /* PREFIX_VEX_0F41 */
4659   {
4660     { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4661     { Bad_Opcode },
4662     { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4663   },
4664
4665   /* PREFIX_VEX_0F42 */
4666   {
4667     { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4668     { Bad_Opcode },
4669     { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4670   },
4671
4672   /* PREFIX_VEX_0F44 */
4673   {
4674     { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4675     { Bad_Opcode },
4676     { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4677   },
4678
4679   /* PREFIX_VEX_0F45 */
4680   {
4681     { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4682     { Bad_Opcode },
4683     { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4684   },
4685
4686   /* PREFIX_VEX_0F46 */
4687   {
4688     { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4689     { Bad_Opcode },
4690     { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4691   },
4692
4693   /* PREFIX_VEX_0F47 */
4694   {
4695     { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4696     { Bad_Opcode },
4697     { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
4698   },
4699
4700   /* PREFIX_VEX_0F4A */
4701   {
4702     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
4703     { Bad_Opcode },
4704     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
4705   },
4706
4707   /* PREFIX_VEX_0F4B */
4708   {
4709     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
4710     { Bad_Opcode },
4711     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4712   },
4713
4714   /* PREFIX_VEX_0F51 */
4715   {
4716     { VEX_W_TABLE (VEX_W_0F51_P_0) },
4717     { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) },
4718     { VEX_W_TABLE (VEX_W_0F51_P_2) },
4719     { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) },
4720   },
4721
4722   /* PREFIX_VEX_0F52 */
4723   {
4724     { VEX_W_TABLE (VEX_W_0F52_P_0) },
4725     { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) },
4726   },
4727
4728   /* PREFIX_VEX_0F53 */
4729   {
4730     { VEX_W_TABLE (VEX_W_0F53_P_0) },
4731     { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) },
4732   },
4733
4734   /* PREFIX_VEX_0F58 */
4735   {
4736     { VEX_W_TABLE (VEX_W_0F58_P_0) },
4737     { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) },
4738     { VEX_W_TABLE (VEX_W_0F58_P_2) },
4739     { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) },
4740   },
4741
4742   /* PREFIX_VEX_0F59 */
4743   {
4744     { VEX_W_TABLE (VEX_W_0F59_P_0) },
4745     { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) },
4746     { VEX_W_TABLE (VEX_W_0F59_P_2) },
4747     { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) },
4748   },
4749
4750   /* PREFIX_VEX_0F5A */
4751   {
4752     { VEX_W_TABLE (VEX_W_0F5A_P_0) },
4753     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) },
4754     { "vcvtpd2ps%XY", { XMM, EXx } },
4755     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) },
4756   },
4757
4758   /* PREFIX_VEX_0F5B */
4759   {
4760     { VEX_W_TABLE (VEX_W_0F5B_P_0) },
4761     { VEX_W_TABLE (VEX_W_0F5B_P_1) },
4762     { VEX_W_TABLE (VEX_W_0F5B_P_2) },
4763   },
4764
4765   /* PREFIX_VEX_0F5C */
4766   {
4767     { VEX_W_TABLE (VEX_W_0F5C_P_0) },
4768     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) },
4769     { VEX_W_TABLE (VEX_W_0F5C_P_2) },
4770     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) },
4771   },
4772
4773   /* PREFIX_VEX_0F5D */
4774   {
4775     { VEX_W_TABLE (VEX_W_0F5D_P_0) },
4776     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) },
4777     { VEX_W_TABLE (VEX_W_0F5D_P_2) },
4778     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) },
4779   },
4780
4781   /* PREFIX_VEX_0F5E */
4782   {
4783     { VEX_W_TABLE (VEX_W_0F5E_P_0) },
4784     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) },
4785     { VEX_W_TABLE (VEX_W_0F5E_P_2) },
4786     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) },
4787   },
4788
4789   /* PREFIX_VEX_0F5F */
4790   {
4791     { VEX_W_TABLE (VEX_W_0F5F_P_0) },
4792     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) },
4793     { VEX_W_TABLE (VEX_W_0F5F_P_2) },
4794     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) },
4795   },
4796
4797   /* PREFIX_VEX_0F60 */
4798   {
4799     { Bad_Opcode },
4800     { Bad_Opcode },
4801     { VEX_W_TABLE (VEX_W_0F60_P_2) },
4802   },
4803
4804   /* PREFIX_VEX_0F61 */
4805   {
4806     { Bad_Opcode },
4807     { Bad_Opcode },
4808     { VEX_W_TABLE (VEX_W_0F61_P_2) },
4809   },
4810
4811   /* PREFIX_VEX_0F62 */
4812   {
4813     { Bad_Opcode },
4814     { Bad_Opcode },
4815     { VEX_W_TABLE (VEX_W_0F62_P_2) },
4816   },
4817
4818   /* PREFIX_VEX_0F63 */
4819   {
4820     { Bad_Opcode },
4821     { Bad_Opcode },
4822     { VEX_W_TABLE (VEX_W_0F63_P_2) },
4823   },
4824
4825   /* PREFIX_VEX_0F64 */
4826   {
4827     { Bad_Opcode },
4828     { Bad_Opcode },
4829     { VEX_W_TABLE (VEX_W_0F64_P_2) },
4830   },
4831
4832   /* PREFIX_VEX_0F65 */
4833   {
4834     { Bad_Opcode },
4835     { Bad_Opcode },
4836     { VEX_W_TABLE (VEX_W_0F65_P_2) },
4837   },
4838
4839   /* PREFIX_VEX_0F66 */
4840   {
4841     { Bad_Opcode },
4842     { Bad_Opcode },
4843     { VEX_W_TABLE (VEX_W_0F66_P_2) },
4844   },
4845
4846   /* PREFIX_VEX_0F67 */
4847   {
4848     { Bad_Opcode },
4849     { Bad_Opcode },
4850     { VEX_W_TABLE (VEX_W_0F67_P_2) },
4851   },
4852
4853   /* PREFIX_VEX_0F68 */
4854   {
4855     { Bad_Opcode },
4856     { Bad_Opcode },
4857     { VEX_W_TABLE (VEX_W_0F68_P_2) },
4858   },
4859
4860   /* PREFIX_VEX_0F69 */
4861   {
4862     { Bad_Opcode },
4863     { Bad_Opcode },
4864     { VEX_W_TABLE (VEX_W_0F69_P_2) },
4865   },
4866
4867   /* PREFIX_VEX_0F6A */
4868   {
4869     { Bad_Opcode },
4870     { Bad_Opcode },
4871     { VEX_W_TABLE (VEX_W_0F6A_P_2) },
4872   },
4873
4874   /* PREFIX_VEX_0F6B */
4875   {
4876     { Bad_Opcode },
4877     { Bad_Opcode },
4878     { VEX_W_TABLE (VEX_W_0F6B_P_2) },
4879   },
4880
4881   /* PREFIX_VEX_0F6C */
4882   {
4883     { Bad_Opcode },
4884     { Bad_Opcode },
4885     { VEX_W_TABLE (VEX_W_0F6C_P_2) },
4886   },
4887
4888   /* PREFIX_VEX_0F6D */
4889   {
4890     { Bad_Opcode },
4891     { Bad_Opcode },
4892     { VEX_W_TABLE (VEX_W_0F6D_P_2) },
4893   },
4894
4895   /* PREFIX_VEX_0F6E */
4896   {
4897     { Bad_Opcode },
4898     { Bad_Opcode },
4899     { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
4900   },
4901
4902   /* PREFIX_VEX_0F6F */
4903   {
4904     { Bad_Opcode },
4905     { VEX_W_TABLE (VEX_W_0F6F_P_1) },
4906     { VEX_W_TABLE (VEX_W_0F6F_P_2) },
4907   },
4908
4909   /* PREFIX_VEX_0F70 */
4910   {
4911     { Bad_Opcode },
4912     { VEX_W_TABLE (VEX_W_0F70_P_1) },
4913     { VEX_W_TABLE (VEX_W_0F70_P_2) },
4914     { VEX_W_TABLE (VEX_W_0F70_P_3) },
4915   },
4916
4917   /* PREFIX_VEX_0F71_REG_2 */
4918   {
4919     { Bad_Opcode },
4920     { Bad_Opcode },
4921     { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) },
4922   },
4923
4924   /* PREFIX_VEX_0F71_REG_4 */
4925   {
4926     { Bad_Opcode },
4927     { Bad_Opcode },
4928     { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) },
4929   },
4930
4931   /* PREFIX_VEX_0F71_REG_6 */
4932   {
4933     { Bad_Opcode },
4934     { Bad_Opcode },
4935     { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) },
4936   },
4937
4938   /* PREFIX_VEX_0F72_REG_2 */
4939   {
4940     { Bad_Opcode },
4941     { Bad_Opcode },
4942     { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) },
4943   },
4944
4945   /* PREFIX_VEX_0F72_REG_4 */
4946   {
4947     { Bad_Opcode },
4948     { Bad_Opcode },
4949     { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) },
4950   },
4951
4952   /* PREFIX_VEX_0F72_REG_6 */
4953   {
4954     { Bad_Opcode },
4955     { Bad_Opcode },
4956     { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) },
4957   },
4958
4959   /* PREFIX_VEX_0F73_REG_2 */
4960   {
4961     { Bad_Opcode },
4962     { Bad_Opcode },
4963     { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) },
4964   },
4965
4966   /* PREFIX_VEX_0F73_REG_3 */
4967   {
4968     { Bad_Opcode },
4969     { Bad_Opcode },
4970     { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) },
4971   },
4972
4973   /* PREFIX_VEX_0F73_REG_6 */
4974   {
4975     { Bad_Opcode },
4976     { Bad_Opcode },
4977     { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) },
4978   },
4979
4980   /* PREFIX_VEX_0F73_REG_7 */
4981   {
4982     { Bad_Opcode },
4983     { Bad_Opcode },
4984     { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) },
4985   },
4986
4987   /* PREFIX_VEX_0F74 */
4988   {
4989     { Bad_Opcode },
4990     { Bad_Opcode },
4991     { VEX_W_TABLE (VEX_W_0F74_P_2) },
4992   },
4993
4994   /* PREFIX_VEX_0F75 */
4995   {
4996     { Bad_Opcode },
4997     { Bad_Opcode },
4998     { VEX_W_TABLE (VEX_W_0F75_P_2) },
4999   },
5000
5001   /* PREFIX_VEX_0F76 */
5002   {
5003     { Bad_Opcode },
5004     { Bad_Opcode },
5005     { VEX_W_TABLE (VEX_W_0F76_P_2) },
5006   },
5007
5008   /* PREFIX_VEX_0F77 */
5009   {
5010     { VEX_W_TABLE (VEX_W_0F77_P_0) },
5011   },
5012
5013   /* PREFIX_VEX_0F7C */
5014   {
5015     { Bad_Opcode },
5016     { Bad_Opcode },
5017     { VEX_W_TABLE (VEX_W_0F7C_P_2) },
5018     { VEX_W_TABLE (VEX_W_0F7C_P_3) },
5019   },
5020
5021   /* PREFIX_VEX_0F7D */
5022   {
5023     { Bad_Opcode },
5024     { Bad_Opcode },
5025     { VEX_W_TABLE (VEX_W_0F7D_P_2) },
5026     { VEX_W_TABLE (VEX_W_0F7D_P_3) },
5027   },
5028
5029   /* PREFIX_VEX_0F7E */
5030   {
5031     { Bad_Opcode },
5032     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
5033     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
5034   },
5035
5036   /* PREFIX_VEX_0F7F */
5037   {
5038     { Bad_Opcode },
5039     { VEX_W_TABLE (VEX_W_0F7F_P_1) },
5040     { VEX_W_TABLE (VEX_W_0F7F_P_2) },
5041   },
5042
5043   /* PREFIX_VEX_0F90 */
5044   {
5045     { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
5046     { Bad_Opcode },
5047     { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
5048   },
5049
5050   /* PREFIX_VEX_0F91 */
5051   {
5052     { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
5053     { Bad_Opcode },
5054     { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
5055   },
5056
5057   /* PREFIX_VEX_0F92 */
5058   {
5059     { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
5060     { Bad_Opcode },
5061     { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
5062     { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
5063   },
5064
5065   /* PREFIX_VEX_0F93 */
5066   {
5067     { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
5068     { Bad_Opcode },
5069     { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
5070     { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
5071   },
5072
5073   /* PREFIX_VEX_0F98 */
5074   {
5075     { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
5076     { Bad_Opcode },
5077     { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
5078   },
5079
5080   /* PREFIX_VEX_0F99 */
5081   {
5082     { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5083     { Bad_Opcode },
5084     { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5085   },
5086
5087   /* PREFIX_VEX_0FC2 */
5088   {
5089     { VEX_W_TABLE (VEX_W_0FC2_P_0) },
5090     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) },
5091     { VEX_W_TABLE (VEX_W_0FC2_P_2) },
5092     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) },
5093   },
5094
5095   /* PREFIX_VEX_0FC4 */
5096   {
5097     { Bad_Opcode },
5098     { Bad_Opcode },
5099     { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5100   },
5101
5102   /* PREFIX_VEX_0FC5 */
5103   {
5104     { Bad_Opcode },
5105     { Bad_Opcode },
5106     { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5107   },
5108
5109   /* PREFIX_VEX_0FD0 */
5110   {
5111     { Bad_Opcode },
5112     { Bad_Opcode },
5113     { VEX_W_TABLE (VEX_W_0FD0_P_2) },
5114     { VEX_W_TABLE (VEX_W_0FD0_P_3) },
5115   },
5116
5117   /* PREFIX_VEX_0FD1 */
5118   {
5119     { Bad_Opcode },
5120     { Bad_Opcode },
5121     { VEX_W_TABLE (VEX_W_0FD1_P_2) },
5122   },
5123
5124   /* PREFIX_VEX_0FD2 */
5125   {
5126     { Bad_Opcode },
5127     { Bad_Opcode },
5128     { VEX_W_TABLE (VEX_W_0FD2_P_2) },
5129   },
5130
5131   /* PREFIX_VEX_0FD3 */
5132   {
5133     { Bad_Opcode },
5134     { Bad_Opcode },
5135     { VEX_W_TABLE (VEX_W_0FD3_P_2) },
5136   },
5137
5138   /* PREFIX_VEX_0FD4 */
5139   {
5140     { Bad_Opcode },
5141     { Bad_Opcode },
5142     { VEX_W_TABLE (VEX_W_0FD4_P_2) },
5143   },
5144
5145   /* PREFIX_VEX_0FD5 */
5146   {
5147     { Bad_Opcode },
5148     { Bad_Opcode },
5149     { VEX_W_TABLE (VEX_W_0FD5_P_2) },
5150   },
5151
5152   /* PREFIX_VEX_0FD6 */
5153   {
5154     { Bad_Opcode },
5155     { Bad_Opcode },
5156     { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5157   },
5158
5159   /* PREFIX_VEX_0FD7 */
5160   {
5161     { Bad_Opcode },
5162     { Bad_Opcode },
5163     { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5164   },
5165
5166   /* PREFIX_VEX_0FD8 */
5167   {
5168     { Bad_Opcode },
5169     { Bad_Opcode },
5170     { VEX_W_TABLE (VEX_W_0FD8_P_2) },
5171   },
5172
5173   /* PREFIX_VEX_0FD9 */
5174   {
5175     { Bad_Opcode },
5176     { Bad_Opcode },
5177     { VEX_W_TABLE (VEX_W_0FD9_P_2) },
5178   },
5179
5180   /* PREFIX_VEX_0FDA */
5181   {
5182     { Bad_Opcode },
5183     { Bad_Opcode },
5184     { VEX_W_TABLE (VEX_W_0FDA_P_2) },
5185   },
5186
5187   /* PREFIX_VEX_0FDB */
5188   {
5189     { Bad_Opcode },
5190     { Bad_Opcode },
5191     { VEX_W_TABLE (VEX_W_0FDB_P_2) },
5192   },
5193
5194   /* PREFIX_VEX_0FDC */
5195   {
5196     { Bad_Opcode },
5197     { Bad_Opcode },
5198     { VEX_W_TABLE (VEX_W_0FDC_P_2) },
5199   },
5200
5201   /* PREFIX_VEX_0FDD */
5202   {
5203     { Bad_Opcode },
5204     { Bad_Opcode },
5205     { VEX_W_TABLE (VEX_W_0FDD_P_2) },
5206   },
5207
5208   /* PREFIX_VEX_0FDE */
5209   {
5210     { Bad_Opcode },
5211     { Bad_Opcode },
5212     { VEX_W_TABLE (VEX_W_0FDE_P_2) },
5213   },
5214
5215   /* PREFIX_VEX_0FDF */
5216   {
5217     { Bad_Opcode },
5218     { Bad_Opcode },
5219     { VEX_W_TABLE (VEX_W_0FDF_P_2) },
5220   },
5221
5222   /* PREFIX_VEX_0FE0 */
5223   {
5224     { Bad_Opcode },
5225     { Bad_Opcode },
5226     { VEX_W_TABLE (VEX_W_0FE0_P_2) },
5227   },
5228
5229   /* PREFIX_VEX_0FE1 */
5230   {
5231     { Bad_Opcode },
5232     { Bad_Opcode },
5233     { VEX_W_TABLE (VEX_W_0FE1_P_2) },
5234   },
5235
5236   /* PREFIX_VEX_0FE2 */
5237   {
5238     { Bad_Opcode },
5239     { Bad_Opcode },
5240     { VEX_W_TABLE (VEX_W_0FE2_P_2) },
5241   },
5242
5243   /* PREFIX_VEX_0FE3 */
5244   {
5245     { Bad_Opcode },
5246     { Bad_Opcode },
5247     { VEX_W_TABLE (VEX_W_0FE3_P_2) },
5248   },
5249
5250   /* PREFIX_VEX_0FE4 */
5251   {
5252     { Bad_Opcode },
5253     { Bad_Opcode },
5254     { VEX_W_TABLE (VEX_W_0FE4_P_2) },
5255   },
5256
5257   /* PREFIX_VEX_0FE5 */
5258   {
5259     { Bad_Opcode },
5260     { Bad_Opcode },
5261     { VEX_W_TABLE (VEX_W_0FE5_P_2) },
5262   },
5263
5264   /* PREFIX_VEX_0FE6 */
5265   {
5266     { Bad_Opcode },
5267     { VEX_W_TABLE (VEX_W_0FE6_P_1) },
5268     { VEX_W_TABLE (VEX_W_0FE6_P_2) },
5269     { VEX_W_TABLE (VEX_W_0FE6_P_3) },
5270   },
5271
5272   /* PREFIX_VEX_0FE7 */
5273   {
5274     { Bad_Opcode },
5275     { Bad_Opcode },
5276     { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5277   },
5278
5279   /* PREFIX_VEX_0FE8 */
5280   {
5281     { Bad_Opcode },
5282     { Bad_Opcode },
5283     { VEX_W_TABLE (VEX_W_0FE8_P_2) },
5284   },
5285
5286   /* PREFIX_VEX_0FE9 */
5287   {
5288     { Bad_Opcode },
5289     { Bad_Opcode },
5290     { VEX_W_TABLE (VEX_W_0FE9_P_2) },
5291   },
5292
5293   /* PREFIX_VEX_0FEA */
5294   {
5295     { Bad_Opcode },
5296     { Bad_Opcode },
5297     { VEX_W_TABLE (VEX_W_0FEA_P_2) },
5298   },
5299
5300   /* PREFIX_VEX_0FEB */
5301   {
5302     { Bad_Opcode },
5303     { Bad_Opcode },
5304     { VEX_W_TABLE (VEX_W_0FEB_P_2) },
5305   },
5306
5307   /* PREFIX_VEX_0FEC */
5308   {
5309     { Bad_Opcode },
5310     { Bad_Opcode },
5311     { VEX_W_TABLE (VEX_W_0FEC_P_2) },
5312   },
5313
5314   /* PREFIX_VEX_0FED */
5315   {
5316     { Bad_Opcode },
5317     { Bad_Opcode },
5318     { VEX_W_TABLE (VEX_W_0FED_P_2) },
5319   },
5320
5321   /* PREFIX_VEX_0FEE */
5322   {
5323     { Bad_Opcode },
5324     { Bad_Opcode },
5325     { VEX_W_TABLE (VEX_W_0FEE_P_2) },
5326   },
5327
5328   /* PREFIX_VEX_0FEF */
5329   {
5330     { Bad_Opcode },
5331     { Bad_Opcode },
5332     { VEX_W_TABLE (VEX_W_0FEF_P_2) },
5333   },
5334
5335   /* PREFIX_VEX_0FF0 */
5336   {
5337     { Bad_Opcode },
5338     { Bad_Opcode },
5339     { Bad_Opcode },
5340     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5341   },
5342
5343   /* PREFIX_VEX_0FF1 */
5344   {
5345     { Bad_Opcode },
5346     { Bad_Opcode },
5347     { VEX_W_TABLE (VEX_W_0FF1_P_2) },
5348   },
5349
5350   /* PREFIX_VEX_0FF2 */
5351   {
5352     { Bad_Opcode },
5353     { Bad_Opcode },
5354     { VEX_W_TABLE (VEX_W_0FF2_P_2) },
5355   },
5356
5357   /* PREFIX_VEX_0FF3 */
5358   {
5359     { Bad_Opcode },
5360     { Bad_Opcode },
5361     { VEX_W_TABLE (VEX_W_0FF3_P_2) },
5362   },
5363
5364   /* PREFIX_VEX_0FF4 */
5365   {
5366     { Bad_Opcode },
5367     { Bad_Opcode },
5368     { VEX_W_TABLE (VEX_W_0FF4_P_2) },
5369   },
5370
5371   /* PREFIX_VEX_0FF5 */
5372   {
5373     { Bad_Opcode },
5374     { Bad_Opcode },
5375     { VEX_W_TABLE (VEX_W_0FF5_P_2) },
5376   },
5377
5378   /* PREFIX_VEX_0FF6 */
5379   {
5380     { Bad_Opcode },
5381     { Bad_Opcode },
5382     { VEX_W_TABLE (VEX_W_0FF6_P_2) },
5383   },
5384
5385   /* PREFIX_VEX_0FF7 */
5386   {
5387     { Bad_Opcode },
5388     { Bad_Opcode },
5389     { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5390   },
5391
5392   /* PREFIX_VEX_0FF8 */
5393   {
5394     { Bad_Opcode },
5395     { Bad_Opcode },
5396     { VEX_W_TABLE (VEX_W_0FF8_P_2) },
5397   },
5398
5399   /* PREFIX_VEX_0FF9 */
5400   {
5401     { Bad_Opcode },
5402     { Bad_Opcode },
5403     { VEX_W_TABLE (VEX_W_0FF9_P_2) },
5404   },
5405
5406   /* PREFIX_VEX_0FFA */
5407   {
5408     { Bad_Opcode },
5409     { Bad_Opcode },
5410     { VEX_W_TABLE (VEX_W_0FFA_P_2) },
5411   },
5412
5413   /* PREFIX_VEX_0FFB */
5414   {
5415     { Bad_Opcode },
5416     { Bad_Opcode },
5417     { VEX_W_TABLE (VEX_W_0FFB_P_2) },
5418   },
5419
5420   /* PREFIX_VEX_0FFC */
5421   {
5422     { Bad_Opcode },
5423     { Bad_Opcode },
5424     { VEX_W_TABLE (VEX_W_0FFC_P_2) },
5425   },
5426
5427   /* PREFIX_VEX_0FFD */
5428   {
5429     { Bad_Opcode },
5430     { Bad_Opcode },
5431     { VEX_W_TABLE (VEX_W_0FFD_P_2) },
5432   },
5433
5434   /* PREFIX_VEX_0FFE */
5435   {
5436     { Bad_Opcode },
5437     { Bad_Opcode },
5438     { VEX_W_TABLE (VEX_W_0FFE_P_2) },
5439   },
5440
5441   /* PREFIX_VEX_0F3800 */
5442   {
5443     { Bad_Opcode },
5444     { Bad_Opcode },
5445     { VEX_W_TABLE (VEX_W_0F3800_P_2) },
5446   },
5447
5448   /* PREFIX_VEX_0F3801 */
5449   {
5450     { Bad_Opcode },
5451     { Bad_Opcode },
5452     { VEX_W_TABLE (VEX_W_0F3801_P_2) },
5453   },
5454
5455   /* PREFIX_VEX_0F3802 */
5456   {
5457     { Bad_Opcode },
5458     { Bad_Opcode },
5459     { VEX_W_TABLE (VEX_W_0F3802_P_2) },
5460   },
5461
5462   /* PREFIX_VEX_0F3803 */
5463   {
5464     { Bad_Opcode },
5465     { Bad_Opcode },
5466     { VEX_W_TABLE (VEX_W_0F3803_P_2) },
5467   },
5468
5469   /* PREFIX_VEX_0F3804 */
5470   {
5471     { Bad_Opcode },
5472     { Bad_Opcode },
5473     { VEX_W_TABLE (VEX_W_0F3804_P_2) },
5474   },
5475
5476   /* PREFIX_VEX_0F3805 */
5477   {
5478     { Bad_Opcode },
5479     { Bad_Opcode },
5480     { VEX_W_TABLE (VEX_W_0F3805_P_2) },
5481   },
5482
5483   /* PREFIX_VEX_0F3806 */
5484   {
5485     { Bad_Opcode },
5486     { Bad_Opcode },
5487     { VEX_W_TABLE (VEX_W_0F3806_P_2) },
5488   },
5489
5490   /* PREFIX_VEX_0F3807 */
5491   {
5492     { Bad_Opcode },
5493     { Bad_Opcode },
5494     { VEX_W_TABLE (VEX_W_0F3807_P_2) },
5495   },
5496
5497   /* PREFIX_VEX_0F3808 */
5498   {
5499     { Bad_Opcode },
5500     { Bad_Opcode },
5501     { VEX_W_TABLE (VEX_W_0F3808_P_2) },
5502   },
5503
5504   /* PREFIX_VEX_0F3809 */
5505   {
5506     { Bad_Opcode },
5507     { Bad_Opcode },
5508     { VEX_W_TABLE (VEX_W_0F3809_P_2) },
5509   },
5510
5511   /* PREFIX_VEX_0F380A */
5512   {
5513     { Bad_Opcode },
5514     { Bad_Opcode },
5515     { VEX_W_TABLE (VEX_W_0F380A_P_2) },
5516   },
5517
5518   /* PREFIX_VEX_0F380B */
5519   {
5520     { Bad_Opcode },
5521     { Bad_Opcode },
5522     { VEX_W_TABLE (VEX_W_0F380B_P_2) },
5523   },
5524
5525   /* PREFIX_VEX_0F380C */
5526   {
5527     { Bad_Opcode },
5528     { Bad_Opcode },
5529     { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5530   },
5531
5532   /* PREFIX_VEX_0F380D */
5533   {
5534     { Bad_Opcode },
5535     { Bad_Opcode },
5536     { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5537   },
5538
5539   /* PREFIX_VEX_0F380E */
5540   {
5541     { Bad_Opcode },
5542     { Bad_Opcode },
5543     { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5544   },
5545
5546   /* PREFIX_VEX_0F380F */
5547   {
5548     { Bad_Opcode },
5549     { Bad_Opcode },
5550     { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5551   },
5552
5553   /* PREFIX_VEX_0F3813 */
5554   {
5555     { Bad_Opcode },
5556     { Bad_Opcode },
5557     { "vcvtph2ps", { XM, EXxmmq } },
5558   },
5559
5560   /* PREFIX_VEX_0F3816 */
5561   {
5562     { Bad_Opcode },
5563     { Bad_Opcode },
5564     { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5565   },
5566
5567   /* PREFIX_VEX_0F3817 */
5568   {
5569     { Bad_Opcode },
5570     { Bad_Opcode },
5571     { VEX_W_TABLE (VEX_W_0F3817_P_2) },
5572   },
5573
5574   /* PREFIX_VEX_0F3818 */
5575   {
5576     { Bad_Opcode },
5577     { Bad_Opcode },
5578     { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5579   },
5580
5581   /* PREFIX_VEX_0F3819 */
5582   {
5583     { Bad_Opcode },
5584     { Bad_Opcode },
5585     { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5586   },
5587
5588   /* PREFIX_VEX_0F381A */
5589   {
5590     { Bad_Opcode },
5591     { Bad_Opcode },
5592     { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5593   },
5594
5595   /* PREFIX_VEX_0F381C */
5596   {
5597     { Bad_Opcode },
5598     { Bad_Opcode },
5599     { VEX_W_TABLE (VEX_W_0F381C_P_2) },
5600   },
5601
5602   /* PREFIX_VEX_0F381D */
5603   {
5604     { Bad_Opcode },
5605     { Bad_Opcode },
5606     { VEX_W_TABLE (VEX_W_0F381D_P_2) },
5607   },
5608
5609   /* PREFIX_VEX_0F381E */
5610   {
5611     { Bad_Opcode },
5612     { Bad_Opcode },
5613     { VEX_W_TABLE (VEX_W_0F381E_P_2) },
5614   },
5615
5616   /* PREFIX_VEX_0F3820 */
5617   {
5618     { Bad_Opcode },
5619     { Bad_Opcode },
5620     { VEX_W_TABLE (VEX_W_0F3820_P_2) },
5621   },
5622
5623   /* PREFIX_VEX_0F3821 */
5624   {
5625     { Bad_Opcode },
5626     { Bad_Opcode },
5627     { VEX_W_TABLE (VEX_W_0F3821_P_2) },
5628   },
5629
5630   /* PREFIX_VEX_0F3822 */
5631   {
5632     { Bad_Opcode },
5633     { Bad_Opcode },
5634     { VEX_W_TABLE (VEX_W_0F3822_P_2) },
5635   },
5636
5637   /* PREFIX_VEX_0F3823 */
5638   {
5639     { Bad_Opcode },
5640     { Bad_Opcode },
5641     { VEX_W_TABLE (VEX_W_0F3823_P_2) },
5642   },
5643
5644   /* PREFIX_VEX_0F3824 */
5645   {
5646     { Bad_Opcode },
5647     { Bad_Opcode },
5648     { VEX_W_TABLE (VEX_W_0F3824_P_2) },
5649   },
5650
5651   /* PREFIX_VEX_0F3825 */
5652   {
5653     { Bad_Opcode },
5654     { Bad_Opcode },
5655     { VEX_W_TABLE (VEX_W_0F3825_P_2) },
5656   },
5657
5658   /* PREFIX_VEX_0F3828 */
5659   {
5660     { Bad_Opcode },
5661     { Bad_Opcode },
5662     { VEX_W_TABLE (VEX_W_0F3828_P_2) },
5663   },
5664
5665   /* PREFIX_VEX_0F3829 */
5666   {
5667     { Bad_Opcode },
5668     { Bad_Opcode },
5669     { VEX_W_TABLE (VEX_W_0F3829_P_2) },
5670   },
5671
5672   /* PREFIX_VEX_0F382A */
5673   {
5674     { Bad_Opcode },
5675     { Bad_Opcode },
5676     { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5677   },
5678
5679   /* PREFIX_VEX_0F382B */
5680   {
5681     { Bad_Opcode },
5682     { Bad_Opcode },
5683     { VEX_W_TABLE (VEX_W_0F382B_P_2) },
5684   },
5685
5686   /* PREFIX_VEX_0F382C */
5687   {
5688     { Bad_Opcode },
5689     { Bad_Opcode },
5690      { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5691   },
5692
5693   /* PREFIX_VEX_0F382D */
5694   {
5695     { Bad_Opcode },
5696     { Bad_Opcode },
5697      { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5698   },
5699
5700   /* PREFIX_VEX_0F382E */
5701   {
5702     { Bad_Opcode },
5703     { Bad_Opcode },
5704      { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5705   },
5706
5707   /* PREFIX_VEX_0F382F */
5708   {
5709     { Bad_Opcode },
5710     { Bad_Opcode },
5711      { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5712   },
5713
5714   /* PREFIX_VEX_0F3830 */
5715   {
5716     { Bad_Opcode },
5717     { Bad_Opcode },
5718     { VEX_W_TABLE (VEX_W_0F3830_P_2) },
5719   },
5720
5721   /* PREFIX_VEX_0F3831 */
5722   {
5723     { Bad_Opcode },
5724     { Bad_Opcode },
5725     { VEX_W_TABLE (VEX_W_0F3831_P_2) },
5726   },
5727
5728   /* PREFIX_VEX_0F3832 */
5729   {
5730     { Bad_Opcode },
5731     { Bad_Opcode },
5732     { VEX_W_TABLE (VEX_W_0F3832_P_2) },
5733   },
5734
5735   /* PREFIX_VEX_0F3833 */
5736   {
5737     { Bad_Opcode },
5738     { Bad_Opcode },
5739     { VEX_W_TABLE (VEX_W_0F3833_P_2) },
5740   },
5741
5742   /* PREFIX_VEX_0F3834 */
5743   {
5744     { Bad_Opcode },
5745     { Bad_Opcode },
5746     { VEX_W_TABLE (VEX_W_0F3834_P_2) },
5747   },
5748
5749   /* PREFIX_VEX_0F3835 */
5750   {
5751     { Bad_Opcode },
5752     { Bad_Opcode },
5753     { VEX_W_TABLE (VEX_W_0F3835_P_2) },
5754   },
5755
5756   /* PREFIX_VEX_0F3836 */
5757   {
5758     { Bad_Opcode },
5759     { Bad_Opcode },
5760     { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5761   },
5762
5763   /* PREFIX_VEX_0F3837 */
5764   {
5765     { Bad_Opcode },
5766     { Bad_Opcode },
5767     { VEX_W_TABLE (VEX_W_0F3837_P_2) },
5768   },
5769
5770   /* PREFIX_VEX_0F3838 */
5771   {
5772     { Bad_Opcode },
5773     { Bad_Opcode },
5774     { VEX_W_TABLE (VEX_W_0F3838_P_2) },
5775   },
5776
5777   /* PREFIX_VEX_0F3839 */
5778   {
5779     { Bad_Opcode },
5780     { Bad_Opcode },
5781     { VEX_W_TABLE (VEX_W_0F3839_P_2) },
5782   },
5783
5784   /* PREFIX_VEX_0F383A */
5785   {
5786     { Bad_Opcode },
5787     { Bad_Opcode },
5788     { VEX_W_TABLE (VEX_W_0F383A_P_2) },
5789   },
5790
5791   /* PREFIX_VEX_0F383B */
5792   {
5793     { Bad_Opcode },
5794     { Bad_Opcode },
5795     { VEX_W_TABLE (VEX_W_0F383B_P_2) },
5796   },
5797
5798   /* PREFIX_VEX_0F383C */
5799   {
5800     { Bad_Opcode },
5801     { Bad_Opcode },
5802     { VEX_W_TABLE (VEX_W_0F383C_P_2) },
5803   },
5804
5805   /* PREFIX_VEX_0F383D */
5806   {
5807     { Bad_Opcode },
5808     { Bad_Opcode },
5809     { VEX_W_TABLE (VEX_W_0F383D_P_2) },
5810   },
5811
5812   /* PREFIX_VEX_0F383E */
5813   {
5814     { Bad_Opcode },
5815     { Bad_Opcode },
5816     { VEX_W_TABLE (VEX_W_0F383E_P_2) },
5817   },
5818
5819   /* PREFIX_VEX_0F383F */
5820   {
5821     { Bad_Opcode },
5822     { Bad_Opcode },
5823     { VEX_W_TABLE (VEX_W_0F383F_P_2) },
5824   },
5825
5826   /* PREFIX_VEX_0F3840 */
5827   {
5828     { Bad_Opcode },
5829     { Bad_Opcode },
5830     { VEX_W_TABLE (VEX_W_0F3840_P_2) },
5831   },
5832
5833   /* PREFIX_VEX_0F3841 */
5834   {
5835     { Bad_Opcode },
5836     { Bad_Opcode },
5837     { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
5838   },
5839
5840   /* PREFIX_VEX_0F3845 */
5841   {
5842     { Bad_Opcode },
5843     { Bad_Opcode },
5844     { "vpsrlv%LW", { XM, Vex, EXx } },
5845   },
5846
5847   /* PREFIX_VEX_0F3846 */
5848   {
5849     { Bad_Opcode },
5850     { Bad_Opcode },
5851     { VEX_W_TABLE (VEX_W_0F3846_P_2) },
5852   },
5853
5854   /* PREFIX_VEX_0F3847 */
5855   {
5856     { Bad_Opcode },
5857     { Bad_Opcode },
5858     { "vpsllv%LW", { XM, Vex, EXx } },
5859   },
5860
5861   /* PREFIX_VEX_0F3858 */
5862   {
5863     { Bad_Opcode },
5864     { Bad_Opcode },
5865     { VEX_W_TABLE (VEX_W_0F3858_P_2) },
5866   },
5867
5868   /* PREFIX_VEX_0F3859 */
5869   {
5870     { Bad_Opcode },
5871     { Bad_Opcode },
5872     { VEX_W_TABLE (VEX_W_0F3859_P_2) },
5873   },
5874
5875   /* PREFIX_VEX_0F385A */
5876   {
5877     { Bad_Opcode },
5878     { Bad_Opcode },
5879     { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
5880   },
5881
5882   /* PREFIX_VEX_0F3878 */
5883   {
5884     { Bad_Opcode },
5885     { Bad_Opcode },
5886     { VEX_W_TABLE (VEX_W_0F3878_P_2) },
5887   },
5888
5889   /* PREFIX_VEX_0F3879 */
5890   {
5891     { Bad_Opcode },
5892     { Bad_Opcode },
5893     { VEX_W_TABLE (VEX_W_0F3879_P_2) },
5894   },
5895
5896   /* PREFIX_VEX_0F388C */
5897   {
5898     { Bad_Opcode },
5899     { Bad_Opcode },
5900     { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
5901   },
5902
5903   /* PREFIX_VEX_0F388E */
5904   {
5905     { Bad_Opcode },
5906     { Bad_Opcode },
5907     { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
5908   },
5909
5910   /* PREFIX_VEX_0F3890 */
5911   {
5912     { Bad_Opcode },
5913     { Bad_Opcode },
5914     { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex } },
5915   },
5916
5917   /* PREFIX_VEX_0F3891 */
5918   {
5919     { Bad_Opcode },
5920     { Bad_Opcode },
5921     { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ } },
5922   },
5923
5924   /* PREFIX_VEX_0F3892 */
5925   {
5926     { Bad_Opcode },
5927     { Bad_Opcode },
5928     { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex } },
5929   },
5930
5931   /* PREFIX_VEX_0F3893 */
5932   {
5933     { Bad_Opcode },
5934     { Bad_Opcode },
5935     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ } },
5936   },
5937
5938   /* PREFIX_VEX_0F3896 */
5939   {
5940     { Bad_Opcode },
5941     { Bad_Opcode },
5942     { "vfmaddsub132p%XW", { XM, Vex, EXx } },
5943   },
5944
5945   /* PREFIX_VEX_0F3897 */
5946   {
5947     { Bad_Opcode },
5948     { Bad_Opcode },
5949     { "vfmsubadd132p%XW", { XM, Vex, EXx } },
5950   },
5951
5952   /* PREFIX_VEX_0F3898 */
5953   {
5954     { Bad_Opcode },
5955     { Bad_Opcode },
5956     { "vfmadd132p%XW", { XM, Vex, EXx } },
5957   },
5958
5959   /* PREFIX_VEX_0F3899 */
5960   {
5961     { Bad_Opcode },
5962     { Bad_Opcode },
5963     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5964   },
5965
5966   /* PREFIX_VEX_0F389A */
5967   {
5968     { Bad_Opcode },
5969     { Bad_Opcode },
5970     { "vfmsub132p%XW", { XM, Vex, EXx } },
5971   },
5972
5973   /* PREFIX_VEX_0F389B */
5974   {
5975     { Bad_Opcode },
5976     { Bad_Opcode },
5977     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5978   },
5979
5980   /* PREFIX_VEX_0F389C */
5981   {
5982     { Bad_Opcode },
5983     { Bad_Opcode },
5984     { "vfnmadd132p%XW", { XM, Vex, EXx } },
5985   },
5986
5987   /* PREFIX_VEX_0F389D */
5988   {
5989     { Bad_Opcode },
5990     { Bad_Opcode },
5991     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5992   },
5993
5994   /* PREFIX_VEX_0F389E */
5995   {
5996     { Bad_Opcode },
5997     { Bad_Opcode },
5998     { "vfnmsub132p%XW", { XM, Vex, EXx } },
5999   },
6000
6001   /* PREFIX_VEX_0F389F */
6002   {
6003     { Bad_Opcode },
6004     { Bad_Opcode },
6005     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
6006   },
6007
6008   /* PREFIX_VEX_0F38A6 */
6009   {
6010     { Bad_Opcode },
6011     { Bad_Opcode },
6012     { "vfmaddsub213p%XW", { XM, Vex, EXx } },
6013     { Bad_Opcode },
6014   },
6015
6016   /* PREFIX_VEX_0F38A7 */
6017   {
6018     { Bad_Opcode },
6019     { Bad_Opcode },
6020     { "vfmsubadd213p%XW", { XM, Vex, EXx } },
6021   },
6022
6023   /* PREFIX_VEX_0F38A8 */
6024   {
6025     { Bad_Opcode },
6026     { Bad_Opcode },
6027     { "vfmadd213p%XW", { XM, Vex, EXx } },
6028   },
6029
6030   /* PREFIX_VEX_0F38A9 */
6031   {
6032     { Bad_Opcode },
6033     { Bad_Opcode },
6034     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
6035   },
6036
6037   /* PREFIX_VEX_0F38AA */
6038   {
6039     { Bad_Opcode },
6040     { Bad_Opcode },
6041     { "vfmsub213p%XW", { XM, Vex, EXx } },
6042   },
6043
6044   /* PREFIX_VEX_0F38AB */
6045   {
6046     { Bad_Opcode },
6047     { Bad_Opcode },
6048     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
6049   },
6050
6051   /* PREFIX_VEX_0F38AC */
6052   {
6053     { Bad_Opcode },
6054     { Bad_Opcode },
6055     { "vfnmadd213p%XW", { XM, Vex, EXx } },
6056   },
6057
6058   /* PREFIX_VEX_0F38AD */
6059   {
6060     { Bad_Opcode },
6061     { Bad_Opcode },
6062     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
6063   },
6064
6065   /* PREFIX_VEX_0F38AE */
6066   {
6067     { Bad_Opcode },
6068     { Bad_Opcode },
6069     { "vfnmsub213p%XW", { XM, Vex, EXx } },
6070   },
6071
6072   /* PREFIX_VEX_0F38AF */
6073   {
6074     { Bad_Opcode },
6075     { Bad_Opcode },
6076     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
6077   },
6078
6079   /* PREFIX_VEX_0F38B6 */
6080   {
6081     { Bad_Opcode },
6082     { Bad_Opcode },
6083     { "vfmaddsub231p%XW", { XM, Vex, EXx } },
6084   },
6085
6086   /* PREFIX_VEX_0F38B7 */
6087   {
6088     { Bad_Opcode },
6089     { Bad_Opcode },
6090     { "vfmsubadd231p%XW", { XM, Vex, EXx } },
6091   },
6092
6093   /* PREFIX_VEX_0F38B8 */
6094   {
6095     { Bad_Opcode },
6096     { Bad_Opcode },
6097     { "vfmadd231p%XW", { XM, Vex, EXx } },
6098   },
6099
6100   /* PREFIX_VEX_0F38B9 */
6101   {
6102     { Bad_Opcode },
6103     { Bad_Opcode },
6104     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
6105   },
6106
6107   /* PREFIX_VEX_0F38BA */
6108   {
6109     { Bad_Opcode },
6110     { Bad_Opcode },
6111     { "vfmsub231p%XW", { XM, Vex, EXx } },
6112   },
6113
6114   /* PREFIX_VEX_0F38BB */
6115   {
6116     { Bad_Opcode },
6117     { Bad_Opcode },
6118     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
6119   },
6120
6121   /* PREFIX_VEX_0F38BC */
6122   {
6123     { Bad_Opcode },
6124     { Bad_Opcode },
6125     { "vfnmadd231p%XW", { XM, Vex, EXx } },
6126   },
6127
6128   /* PREFIX_VEX_0F38BD */
6129   {
6130     { Bad_Opcode },
6131     { Bad_Opcode },
6132     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
6133   },
6134
6135   /* PREFIX_VEX_0F38BE */
6136   {
6137     { Bad_Opcode },
6138     { Bad_Opcode },
6139     { "vfnmsub231p%XW", { XM, Vex, EXx } },
6140   },
6141
6142   /* PREFIX_VEX_0F38BF */
6143   {
6144     { Bad_Opcode },
6145     { Bad_Opcode },
6146     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
6147   },
6148
6149   /* PREFIX_VEX_0F38DB */
6150   {
6151     { Bad_Opcode },
6152     { Bad_Opcode },
6153     { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6154   },
6155
6156   /* PREFIX_VEX_0F38DC */
6157   {
6158     { Bad_Opcode },
6159     { Bad_Opcode },
6160     { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2) },
6161   },
6162
6163   /* PREFIX_VEX_0F38DD */
6164   {
6165     { Bad_Opcode },
6166     { Bad_Opcode },
6167     { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2) },
6168   },
6169
6170   /* PREFIX_VEX_0F38DE */
6171   {
6172     { Bad_Opcode },
6173     { Bad_Opcode },
6174     { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2) },
6175   },
6176
6177   /* PREFIX_VEX_0F38DF */
6178   {
6179     { Bad_Opcode },
6180     { Bad_Opcode },
6181     { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2) },
6182   },
6183
6184   /* PREFIX_VEX_0F38F2 */
6185   {
6186     { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6187   },
6188
6189   /* PREFIX_VEX_0F38F3_REG_1 */
6190   {
6191     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6192   },
6193
6194   /* PREFIX_VEX_0F38F3_REG_2 */
6195   {
6196     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6197   },
6198
6199   /* PREFIX_VEX_0F38F3_REG_3 */
6200   {
6201     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6202   },
6203
6204   /* PREFIX_VEX_0F38F5 */
6205   {
6206     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6207     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6208     { Bad_Opcode },
6209     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6210   },
6211
6212   /* PREFIX_VEX_0F38F6 */
6213   {
6214     { Bad_Opcode },
6215     { Bad_Opcode },
6216     { Bad_Opcode },
6217     { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6218   },
6219
6220   /* PREFIX_VEX_0F38F7 */
6221   {
6222     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6223     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6224     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6225     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6226   },
6227
6228   /* PREFIX_VEX_0F3A00 */
6229   {
6230     { Bad_Opcode },
6231     { Bad_Opcode },
6232     { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6233   },
6234
6235   /* PREFIX_VEX_0F3A01 */
6236   {
6237     { Bad_Opcode },
6238     { Bad_Opcode },
6239     { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6240   },
6241
6242   /* PREFIX_VEX_0F3A02 */
6243   {
6244     { Bad_Opcode },
6245     { Bad_Opcode },
6246     { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6247   },
6248
6249   /* PREFIX_VEX_0F3A04 */
6250   {
6251     { Bad_Opcode },
6252     { Bad_Opcode },
6253     { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6254   },
6255
6256   /* PREFIX_VEX_0F3A05 */
6257   {
6258     { Bad_Opcode },
6259     { Bad_Opcode },
6260     { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6261   },
6262
6263   /* PREFIX_VEX_0F3A06 */
6264   {
6265     { Bad_Opcode },
6266     { Bad_Opcode },
6267     { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6268   },
6269
6270   /* PREFIX_VEX_0F3A08 */
6271   {
6272     { Bad_Opcode },
6273     { Bad_Opcode },
6274     { VEX_W_TABLE (VEX_W_0F3A08_P_2) },
6275   },
6276
6277   /* PREFIX_VEX_0F3A09 */
6278   {
6279     { Bad_Opcode },
6280     { Bad_Opcode },
6281     { VEX_W_TABLE (VEX_W_0F3A09_P_2) },
6282   },
6283
6284   /* PREFIX_VEX_0F3A0A */
6285   {
6286     { Bad_Opcode },
6287     { Bad_Opcode },
6288     { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) },
6289   },
6290
6291   /* PREFIX_VEX_0F3A0B */
6292   {
6293     { Bad_Opcode },
6294     { Bad_Opcode },
6295     { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) },
6296   },
6297
6298   /* PREFIX_VEX_0F3A0C */
6299   {
6300     { Bad_Opcode },
6301     { Bad_Opcode },
6302     { VEX_W_TABLE (VEX_W_0F3A0C_P_2) },
6303   },
6304
6305   /* PREFIX_VEX_0F3A0D */
6306   {
6307     { Bad_Opcode },
6308     { Bad_Opcode },
6309     { VEX_W_TABLE (VEX_W_0F3A0D_P_2) },
6310   },
6311
6312   /* PREFIX_VEX_0F3A0E */
6313   {
6314     { Bad_Opcode },
6315     { Bad_Opcode },
6316     { VEX_W_TABLE (VEX_W_0F3A0E_P_2) },
6317   },
6318
6319   /* PREFIX_VEX_0F3A0F */
6320   {
6321     { Bad_Opcode },
6322     { Bad_Opcode },
6323     { VEX_W_TABLE (VEX_W_0F3A0F_P_2) },
6324   },
6325
6326   /* PREFIX_VEX_0F3A14 */
6327   {
6328     { Bad_Opcode },
6329     { Bad_Opcode },
6330     { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6331   },
6332
6333   /* PREFIX_VEX_0F3A15 */
6334   {
6335     { Bad_Opcode },
6336     { Bad_Opcode },
6337     { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6338   },
6339
6340   /* PREFIX_VEX_0F3A16 */
6341   {
6342     { Bad_Opcode },
6343     { Bad_Opcode },
6344     { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6345   },
6346
6347   /* PREFIX_VEX_0F3A17 */
6348   {
6349     { Bad_Opcode },
6350     { Bad_Opcode },
6351     { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6352   },
6353
6354   /* PREFIX_VEX_0F3A18 */
6355   {
6356     { Bad_Opcode },
6357     { Bad_Opcode },
6358     { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6359   },
6360
6361   /* PREFIX_VEX_0F3A19 */
6362   {
6363     { Bad_Opcode },
6364     { Bad_Opcode },
6365     { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6366   },
6367
6368   /* PREFIX_VEX_0F3A1D */
6369   {
6370     { Bad_Opcode },
6371     { Bad_Opcode },
6372     { "vcvtps2ph", { EXxmmq, XM, Ib } },
6373   },
6374
6375   /* PREFIX_VEX_0F3A20 */
6376   {
6377     { Bad_Opcode },
6378     { Bad_Opcode },
6379     { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6380   },
6381
6382   /* PREFIX_VEX_0F3A21 */
6383   {
6384     { Bad_Opcode },
6385     { Bad_Opcode },
6386     { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6387   },
6388
6389   /* PREFIX_VEX_0F3A22 */
6390   {
6391     { Bad_Opcode },
6392     { Bad_Opcode },
6393     { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6394   },
6395
6396   /* PREFIX_VEX_0F3A30 */
6397   {
6398     { Bad_Opcode },
6399     { Bad_Opcode },
6400     { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6401   },
6402
6403   /* PREFIX_VEX_0F3A31 */
6404   {
6405     { Bad_Opcode },
6406     { Bad_Opcode },
6407     { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6408   },
6409
6410   /* PREFIX_VEX_0F3A32 */
6411   {
6412     { Bad_Opcode },
6413     { Bad_Opcode },
6414     { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6415   },
6416
6417   /* PREFIX_VEX_0F3A33 */
6418   {
6419     { Bad_Opcode },
6420     { Bad_Opcode },
6421     { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6422   },
6423
6424   /* PREFIX_VEX_0F3A38 */
6425   {
6426     { Bad_Opcode },
6427     { Bad_Opcode },
6428     { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6429   },
6430
6431   /* PREFIX_VEX_0F3A39 */
6432   {
6433     { Bad_Opcode },
6434     { Bad_Opcode },
6435     { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6436   },
6437
6438   /* PREFIX_VEX_0F3A40 */
6439   {
6440     { Bad_Opcode },
6441     { Bad_Opcode },
6442     { VEX_W_TABLE (VEX_W_0F3A40_P_2) },
6443   },
6444
6445   /* PREFIX_VEX_0F3A41 */
6446   {
6447     { Bad_Opcode },
6448     { Bad_Opcode },
6449     { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6450   },
6451
6452   /* PREFIX_VEX_0F3A42 */
6453   {
6454     { Bad_Opcode },
6455     { Bad_Opcode },
6456     { VEX_W_TABLE (VEX_W_0F3A42_P_2) },
6457   },
6458
6459   /* PREFIX_VEX_0F3A44 */
6460   {
6461     { Bad_Opcode },
6462     { Bad_Opcode },
6463     { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2) },
6464   },
6465
6466   /* PREFIX_VEX_0F3A46 */
6467   {
6468     { Bad_Opcode },
6469     { Bad_Opcode },
6470     { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6471   },
6472
6473   /* PREFIX_VEX_0F3A48 */
6474   {
6475     { Bad_Opcode },
6476     { Bad_Opcode },
6477     { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6478   },
6479
6480   /* PREFIX_VEX_0F3A49 */
6481   {
6482     { Bad_Opcode },
6483     { Bad_Opcode },
6484     { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6485   },
6486
6487   /* PREFIX_VEX_0F3A4A */
6488   {
6489     { Bad_Opcode },
6490     { Bad_Opcode },
6491     { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6492   },
6493
6494   /* PREFIX_VEX_0F3A4B */
6495   {
6496     { Bad_Opcode },
6497     { Bad_Opcode },
6498     { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6499   },
6500
6501   /* PREFIX_VEX_0F3A4C */
6502   {
6503     { Bad_Opcode },
6504     { Bad_Opcode },
6505     { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6506   },
6507
6508   /* PREFIX_VEX_0F3A5C */
6509   {
6510     { Bad_Opcode },
6511     { Bad_Opcode },
6512     { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6513   },
6514
6515   /* PREFIX_VEX_0F3A5D */
6516   {
6517     { Bad_Opcode },
6518     { Bad_Opcode },
6519     { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6520   },
6521
6522   /* PREFIX_VEX_0F3A5E */
6523   {
6524     { Bad_Opcode },
6525     { Bad_Opcode },
6526     { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6527   },
6528
6529   /* PREFIX_VEX_0F3A5F */
6530   {
6531     { Bad_Opcode },
6532     { Bad_Opcode },
6533     { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6534   },
6535
6536   /* PREFIX_VEX_0F3A60 */
6537   {
6538     { Bad_Opcode },
6539     { Bad_Opcode },
6540     { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6541     { Bad_Opcode },
6542   },
6543
6544   /* PREFIX_VEX_0F3A61 */
6545   {
6546     { Bad_Opcode },
6547     { Bad_Opcode },
6548     { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6549   },
6550
6551   /* PREFIX_VEX_0F3A62 */
6552   {
6553     { Bad_Opcode },
6554     { Bad_Opcode },
6555     { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6556   },
6557
6558   /* PREFIX_VEX_0F3A63 */
6559   {
6560     { Bad_Opcode },
6561     { Bad_Opcode },
6562     { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6563   },
6564
6565   /* PREFIX_VEX_0F3A68 */
6566   {
6567     { Bad_Opcode },
6568     { Bad_Opcode },
6569     { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6570   },
6571
6572   /* PREFIX_VEX_0F3A69 */
6573   {
6574     { Bad_Opcode },
6575     { Bad_Opcode },
6576     { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6577   },
6578
6579   /* PREFIX_VEX_0F3A6A */
6580   {
6581     { Bad_Opcode },
6582     { Bad_Opcode },
6583     { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6584   },
6585
6586   /* PREFIX_VEX_0F3A6B */
6587   {
6588     { Bad_Opcode },
6589     { Bad_Opcode },
6590     { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6591   },
6592
6593   /* PREFIX_VEX_0F3A6C */
6594   {
6595     { Bad_Opcode },
6596     { Bad_Opcode },
6597     { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6598   },
6599
6600   /* PREFIX_VEX_0F3A6D */
6601   {
6602     { Bad_Opcode },
6603     { Bad_Opcode },
6604     { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6605   },
6606
6607   /* PREFIX_VEX_0F3A6E */
6608   {
6609     { Bad_Opcode },
6610     { Bad_Opcode },
6611     { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6612   },
6613
6614   /* PREFIX_VEX_0F3A6F */
6615   {
6616     { Bad_Opcode },
6617     { Bad_Opcode },
6618     { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6619   },
6620
6621   /* PREFIX_VEX_0F3A78 */
6622   {
6623     { Bad_Opcode },
6624     { Bad_Opcode },
6625     { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6626   },
6627
6628   /* PREFIX_VEX_0F3A79 */
6629   {
6630     { Bad_Opcode },
6631     { Bad_Opcode },
6632     { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6633   },
6634
6635   /* PREFIX_VEX_0F3A7A */
6636   {
6637     { Bad_Opcode },
6638     { Bad_Opcode },
6639     { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6640   },
6641
6642   /* PREFIX_VEX_0F3A7B */
6643   {
6644     { Bad_Opcode },
6645     { Bad_Opcode },
6646     { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6647   },
6648
6649   /* PREFIX_VEX_0F3A7C */
6650   {
6651     { Bad_Opcode },
6652     { Bad_Opcode },
6653     { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6654     { Bad_Opcode },
6655   },
6656
6657   /* PREFIX_VEX_0F3A7D */
6658   {
6659     { Bad_Opcode },
6660     { Bad_Opcode },
6661     { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6662   },
6663
6664   /* PREFIX_VEX_0F3A7E */
6665   {
6666     { Bad_Opcode },
6667     { Bad_Opcode },
6668     { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6669   },
6670
6671   /* PREFIX_VEX_0F3A7F */
6672   {
6673     { Bad_Opcode },
6674     { Bad_Opcode },
6675     { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6676   },
6677
6678   /* PREFIX_VEX_0F3ADF */
6679   {
6680     { Bad_Opcode },
6681     { Bad_Opcode },
6682     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6683   },
6684
6685   /* PREFIX_VEX_0F3AF0 */
6686   {
6687     { Bad_Opcode },
6688     { Bad_Opcode },
6689     { Bad_Opcode },
6690     { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6691   },
6692
6693 #define NEED_PREFIX_TABLE
6694 #include "i386-dis-evex.h"
6695 #undef NEED_PREFIX_TABLE
6696 };
6697
6698 static const struct dis386 x86_64_table[][2] = {
6699   /* X86_64_06 */
6700   {
6701     { "pushP", { es } },
6702   },
6703
6704   /* X86_64_07 */
6705   {
6706     { "popP", { es } },
6707   },
6708
6709   /* X86_64_0D */
6710   {
6711     { "pushP", { cs } },
6712   },
6713
6714   /* X86_64_16 */
6715   {
6716     { "pushP", { ss } },
6717   },
6718
6719   /* X86_64_17 */
6720   {
6721     { "popP", { ss } },
6722   },
6723
6724   /* X86_64_1E */
6725   {
6726     { "pushP", { ds } },
6727   },
6728
6729   /* X86_64_1F */
6730   {
6731     { "popP", { ds } },
6732   },
6733
6734   /* X86_64_27 */
6735   {
6736     { "daa", { XX } },
6737   },
6738
6739   /* X86_64_2F */
6740   {
6741     { "das", { XX } },
6742   },
6743
6744   /* X86_64_37 */
6745   {
6746     { "aaa", { XX } },
6747   },
6748
6749   /* X86_64_3F */
6750   {
6751     { "aas", { XX } },
6752   },
6753
6754   /* X86_64_60 */
6755   {
6756     { "pushaP", { XX } },
6757   },
6758
6759   /* X86_64_61 */
6760   {
6761     { "popaP", { XX } },
6762   },
6763
6764   /* X86_64_62 */
6765   {
6766     { MOD_TABLE (MOD_62_32BIT) },
6767     { EVEX_TABLE (EVEX_0F) },
6768   },
6769
6770   /* X86_64_63 */
6771   {
6772     { "arpl", { Ew, Gw } },
6773     { "movs{lq|xd}", { Gv, Ed } },
6774   },
6775
6776   /* X86_64_6D */
6777   {
6778     { "ins{R|}", { Yzr, indirDX } },
6779     { "ins{G|}", { Yzr, indirDX } },
6780   },
6781
6782   /* X86_64_6F */
6783   {
6784     { "outs{R|}", { indirDXr, Xz } },
6785     { "outs{G|}", { indirDXr, Xz } },
6786   },
6787
6788   /* X86_64_9A */
6789   {
6790     { "Jcall{T|}", { Ap } },
6791   },
6792
6793   /* X86_64_C4 */
6794   {
6795     { MOD_TABLE (MOD_C4_32BIT) },
6796     { VEX_C4_TABLE (VEX_0F) },
6797   },
6798
6799   /* X86_64_C5 */
6800   {
6801     { MOD_TABLE (MOD_C5_32BIT) },
6802     { VEX_C5_TABLE (VEX_0F) },
6803   },
6804
6805   /* X86_64_CE */
6806   {
6807     { "into", { XX } },
6808   },
6809
6810   /* X86_64_D4 */
6811   {
6812     { "aam", { Ib } },
6813   },
6814
6815   /* X86_64_D5 */
6816   {
6817     { "aad", { Ib } },
6818   },
6819
6820   /* X86_64_EA */
6821   {
6822     { "Jjmp{T|}", { Ap } },
6823   },
6824
6825   /* X86_64_0F01_REG_0 */
6826   {
6827     { "sgdt{Q|IQ}", { M } },
6828     { "sgdt", { M } },
6829   },
6830
6831   /* X86_64_0F01_REG_1 */
6832   {
6833     { "sidt{Q|IQ}", { M } },
6834     { "sidt", { M } },
6835   },
6836
6837   /* X86_64_0F01_REG_2 */
6838   {
6839     { "lgdt{Q|Q}", { M } },
6840     { "lgdt", { M } },
6841   },
6842
6843   /* X86_64_0F01_REG_3 */
6844   {
6845     { "lidt{Q|Q}", { M } },
6846     { "lidt", { M } },
6847   },
6848 };
6849
6850 static const struct dis386 three_byte_table[][256] = {
6851
6852   /* THREE_BYTE_0F38 */
6853   {
6854     /* 00 */
6855     { "pshufb",         { MX, EM } },
6856     { "phaddw",         { MX, EM } },
6857     { "phaddd",         { MX, EM } },
6858     { "phaddsw",        { MX, EM } },
6859     { "pmaddubsw",      { MX, EM } },
6860     { "phsubw",         { MX, EM } },
6861     { "phsubd",         { MX, EM } },
6862     { "phsubsw",        { MX, EM } },
6863     /* 08 */
6864     { "psignb",         { MX, EM } },
6865     { "psignw",         { MX, EM } },
6866     { "psignd",         { MX, EM } },
6867     { "pmulhrsw",       { MX, EM } },
6868     { Bad_Opcode },
6869     { Bad_Opcode },
6870     { Bad_Opcode },
6871     { Bad_Opcode },
6872     /* 10 */
6873     { PREFIX_TABLE (PREFIX_0F3810) },
6874     { Bad_Opcode },
6875     { Bad_Opcode },
6876     { Bad_Opcode },
6877     { PREFIX_TABLE (PREFIX_0F3814) },
6878     { PREFIX_TABLE (PREFIX_0F3815) },
6879     { Bad_Opcode },
6880     { PREFIX_TABLE (PREFIX_0F3817) },
6881     /* 18 */
6882     { Bad_Opcode },
6883     { Bad_Opcode },
6884     { Bad_Opcode },
6885     { Bad_Opcode },
6886     { "pabsb",          { MX, EM } },
6887     { "pabsw",          { MX, EM } },
6888     { "pabsd",          { MX, EM } },
6889     { Bad_Opcode },
6890     /* 20 */
6891     { PREFIX_TABLE (PREFIX_0F3820) },
6892     { PREFIX_TABLE (PREFIX_0F3821) },
6893     { PREFIX_TABLE (PREFIX_0F3822) },
6894     { PREFIX_TABLE (PREFIX_0F3823) },
6895     { PREFIX_TABLE (PREFIX_0F3824) },
6896     { PREFIX_TABLE (PREFIX_0F3825) },
6897     { Bad_Opcode },
6898     { Bad_Opcode },
6899     /* 28 */
6900     { PREFIX_TABLE (PREFIX_0F3828) },
6901     { PREFIX_TABLE (PREFIX_0F3829) },
6902     { PREFIX_TABLE (PREFIX_0F382A) },
6903     { PREFIX_TABLE (PREFIX_0F382B) },
6904     { Bad_Opcode },
6905     { Bad_Opcode },
6906     { Bad_Opcode },
6907     { Bad_Opcode },
6908     /* 30 */
6909     { PREFIX_TABLE (PREFIX_0F3830) },
6910     { PREFIX_TABLE (PREFIX_0F3831) },
6911     { PREFIX_TABLE (PREFIX_0F3832) },
6912     { PREFIX_TABLE (PREFIX_0F3833) },
6913     { PREFIX_TABLE (PREFIX_0F3834) },
6914     { PREFIX_TABLE (PREFIX_0F3835) },
6915     { Bad_Opcode },
6916     { PREFIX_TABLE (PREFIX_0F3837) },
6917     /* 38 */
6918     { PREFIX_TABLE (PREFIX_0F3838) },
6919     { PREFIX_TABLE (PREFIX_0F3839) },
6920     { PREFIX_TABLE (PREFIX_0F383A) },
6921     { PREFIX_TABLE (PREFIX_0F383B) },
6922     { PREFIX_TABLE (PREFIX_0F383C) },
6923     { PREFIX_TABLE (PREFIX_0F383D) },
6924     { PREFIX_TABLE (PREFIX_0F383E) },
6925     { PREFIX_TABLE (PREFIX_0F383F) },
6926     /* 40 */
6927     { PREFIX_TABLE (PREFIX_0F3840) },
6928     { PREFIX_TABLE (PREFIX_0F3841) },
6929     { Bad_Opcode },
6930     { Bad_Opcode },
6931     { Bad_Opcode },
6932     { Bad_Opcode },
6933     { Bad_Opcode },
6934     { Bad_Opcode },
6935     /* 48 */
6936     { Bad_Opcode },
6937     { Bad_Opcode },
6938     { Bad_Opcode },
6939     { Bad_Opcode },
6940     { Bad_Opcode },
6941     { Bad_Opcode },
6942     { Bad_Opcode },
6943     { Bad_Opcode },
6944     /* 50 */
6945     { Bad_Opcode },
6946     { Bad_Opcode },
6947     { Bad_Opcode },
6948     { Bad_Opcode },
6949     { Bad_Opcode },
6950     { Bad_Opcode },
6951     { Bad_Opcode },
6952     { Bad_Opcode },
6953     /* 58 */
6954     { Bad_Opcode },
6955     { Bad_Opcode },
6956     { Bad_Opcode },
6957     { Bad_Opcode },
6958     { Bad_Opcode },
6959     { Bad_Opcode },
6960     { Bad_Opcode },
6961     { Bad_Opcode },
6962     /* 60 */
6963     { Bad_Opcode },
6964     { Bad_Opcode },
6965     { Bad_Opcode },
6966     { Bad_Opcode },
6967     { Bad_Opcode },
6968     { Bad_Opcode },
6969     { Bad_Opcode },
6970     { Bad_Opcode },
6971     /* 68 */
6972     { Bad_Opcode },
6973     { Bad_Opcode },
6974     { Bad_Opcode },
6975     { Bad_Opcode },
6976     { Bad_Opcode },
6977     { Bad_Opcode },
6978     { Bad_Opcode },
6979     { Bad_Opcode },
6980     /* 70 */
6981     { Bad_Opcode },
6982     { Bad_Opcode },
6983     { Bad_Opcode },
6984     { Bad_Opcode },
6985     { Bad_Opcode },
6986     { Bad_Opcode },
6987     { Bad_Opcode },
6988     { Bad_Opcode },
6989     /* 78 */
6990     { Bad_Opcode },
6991     { Bad_Opcode },
6992     { Bad_Opcode },
6993     { Bad_Opcode },
6994     { Bad_Opcode },
6995     { Bad_Opcode },
6996     { Bad_Opcode },
6997     { Bad_Opcode },
6998     /* 80 */
6999     { PREFIX_TABLE (PREFIX_0F3880) },
7000     { PREFIX_TABLE (PREFIX_0F3881) },
7001     { PREFIX_TABLE (PREFIX_0F3882) },
7002     { Bad_Opcode },
7003     { Bad_Opcode },
7004     { Bad_Opcode },
7005     { Bad_Opcode },
7006     { Bad_Opcode },
7007     /* 88 */
7008     { Bad_Opcode },
7009     { Bad_Opcode },
7010     { Bad_Opcode },
7011     { Bad_Opcode },
7012     { Bad_Opcode },
7013     { Bad_Opcode },
7014     { Bad_Opcode },
7015     { Bad_Opcode },
7016     /* 90 */
7017     { Bad_Opcode },
7018     { Bad_Opcode },
7019     { Bad_Opcode },
7020     { Bad_Opcode },
7021     { Bad_Opcode },
7022     { Bad_Opcode },
7023     { Bad_Opcode },
7024     { Bad_Opcode },
7025     /* 98 */
7026     { Bad_Opcode },
7027     { Bad_Opcode },
7028     { Bad_Opcode },
7029     { Bad_Opcode },
7030     { Bad_Opcode },
7031     { Bad_Opcode },
7032     { Bad_Opcode },
7033     { Bad_Opcode },
7034     /* a0 */
7035     { Bad_Opcode },
7036     { Bad_Opcode },
7037     { Bad_Opcode },
7038     { Bad_Opcode },
7039     { Bad_Opcode },
7040     { Bad_Opcode },
7041     { Bad_Opcode },
7042     { Bad_Opcode },
7043     /* a8 */
7044     { Bad_Opcode },
7045     { Bad_Opcode },
7046     { Bad_Opcode },
7047     { Bad_Opcode },
7048     { Bad_Opcode },
7049     { Bad_Opcode },
7050     { Bad_Opcode },
7051     { Bad_Opcode },
7052     /* b0 */
7053     { Bad_Opcode },
7054     { Bad_Opcode },
7055     { Bad_Opcode },
7056     { Bad_Opcode },
7057     { Bad_Opcode },
7058     { Bad_Opcode },
7059     { Bad_Opcode },
7060     { Bad_Opcode },
7061     /* b8 */
7062     { Bad_Opcode },
7063     { Bad_Opcode },
7064     { Bad_Opcode },
7065     { Bad_Opcode },
7066     { Bad_Opcode },
7067     { Bad_Opcode },
7068     { Bad_Opcode },
7069     { Bad_Opcode },
7070     /* c0 */
7071     { Bad_Opcode },
7072     { Bad_Opcode },
7073     { Bad_Opcode },
7074     { Bad_Opcode },
7075     { Bad_Opcode },
7076     { Bad_Opcode },
7077     { Bad_Opcode },
7078     { Bad_Opcode },
7079     /* c8 */
7080     { PREFIX_TABLE (PREFIX_0F38C8) },
7081     { PREFIX_TABLE (PREFIX_0F38C9) },
7082     { PREFIX_TABLE (PREFIX_0F38CA) },
7083     { PREFIX_TABLE (PREFIX_0F38CB) },
7084     { PREFIX_TABLE (PREFIX_0F38CC) },
7085     { PREFIX_TABLE (PREFIX_0F38CD) },
7086     { Bad_Opcode },
7087     { Bad_Opcode },
7088     /* d0 */
7089     { Bad_Opcode },
7090     { Bad_Opcode },
7091     { Bad_Opcode },
7092     { Bad_Opcode },
7093     { Bad_Opcode },
7094     { Bad_Opcode },
7095     { Bad_Opcode },
7096     { Bad_Opcode },
7097     /* d8 */
7098     { Bad_Opcode },
7099     { Bad_Opcode },
7100     { Bad_Opcode },
7101     { PREFIX_TABLE (PREFIX_0F38DB) },
7102     { PREFIX_TABLE (PREFIX_0F38DC) },
7103     { PREFIX_TABLE (PREFIX_0F38DD) },
7104     { PREFIX_TABLE (PREFIX_0F38DE) },
7105     { PREFIX_TABLE (PREFIX_0F38DF) },
7106     /* e0 */
7107     { Bad_Opcode },
7108     { Bad_Opcode },
7109     { Bad_Opcode },
7110     { Bad_Opcode },
7111     { Bad_Opcode },
7112     { Bad_Opcode },
7113     { Bad_Opcode },
7114     { Bad_Opcode },
7115     /* e8 */
7116     { Bad_Opcode },
7117     { Bad_Opcode },
7118     { Bad_Opcode },
7119     { Bad_Opcode },
7120     { Bad_Opcode },
7121     { Bad_Opcode },
7122     { Bad_Opcode },
7123     { Bad_Opcode },
7124     /* f0 */
7125     { PREFIX_TABLE (PREFIX_0F38F0) },
7126     { PREFIX_TABLE (PREFIX_0F38F1) },
7127     { Bad_Opcode },
7128     { Bad_Opcode },
7129     { Bad_Opcode },
7130     { Bad_Opcode },
7131     { PREFIX_TABLE (PREFIX_0F38F6) },
7132     { Bad_Opcode },
7133     /* f8 */
7134     { Bad_Opcode },
7135     { Bad_Opcode },
7136     { Bad_Opcode },
7137     { Bad_Opcode },
7138     { Bad_Opcode },
7139     { Bad_Opcode },
7140     { Bad_Opcode },
7141     { Bad_Opcode },
7142   },
7143   /* THREE_BYTE_0F3A */
7144   {
7145     /* 00 */
7146     { Bad_Opcode },
7147     { Bad_Opcode },
7148     { Bad_Opcode },
7149     { Bad_Opcode },
7150     { Bad_Opcode },
7151     { Bad_Opcode },
7152     { Bad_Opcode },
7153     { Bad_Opcode },
7154     /* 08 */
7155     { PREFIX_TABLE (PREFIX_0F3A08) },
7156     { PREFIX_TABLE (PREFIX_0F3A09) },
7157     { PREFIX_TABLE (PREFIX_0F3A0A) },
7158     { PREFIX_TABLE (PREFIX_0F3A0B) },
7159     { PREFIX_TABLE (PREFIX_0F3A0C) },
7160     { PREFIX_TABLE (PREFIX_0F3A0D) },
7161     { PREFIX_TABLE (PREFIX_0F3A0E) },
7162     { "palignr",        { MX, EM, Ib } },
7163     /* 10 */
7164     { Bad_Opcode },
7165     { Bad_Opcode },
7166     { Bad_Opcode },
7167     { Bad_Opcode },
7168     { PREFIX_TABLE (PREFIX_0F3A14) },
7169     { PREFIX_TABLE (PREFIX_0F3A15) },
7170     { PREFIX_TABLE (PREFIX_0F3A16) },
7171     { PREFIX_TABLE (PREFIX_0F3A17) },
7172     /* 18 */
7173     { Bad_Opcode },
7174     { Bad_Opcode },
7175     { Bad_Opcode },
7176     { Bad_Opcode },
7177     { Bad_Opcode },
7178     { Bad_Opcode },
7179     { Bad_Opcode },
7180     { Bad_Opcode },
7181     /* 20 */
7182     { PREFIX_TABLE (PREFIX_0F3A20) },
7183     { PREFIX_TABLE (PREFIX_0F3A21) },
7184     { PREFIX_TABLE (PREFIX_0F3A22) },
7185     { Bad_Opcode },
7186     { Bad_Opcode },
7187     { Bad_Opcode },
7188     { Bad_Opcode },
7189     { Bad_Opcode },
7190     /* 28 */
7191     { Bad_Opcode },
7192     { Bad_Opcode },
7193     { Bad_Opcode },
7194     { Bad_Opcode },
7195     { Bad_Opcode },
7196     { Bad_Opcode },
7197     { Bad_Opcode },
7198     { Bad_Opcode },
7199     /* 30 */
7200     { Bad_Opcode },
7201     { Bad_Opcode },
7202     { Bad_Opcode },
7203     { Bad_Opcode },
7204     { Bad_Opcode },
7205     { Bad_Opcode },
7206     { Bad_Opcode },
7207     { Bad_Opcode },
7208     /* 38 */
7209     { Bad_Opcode },
7210     { Bad_Opcode },
7211     { Bad_Opcode },
7212     { Bad_Opcode },
7213     { Bad_Opcode },
7214     { Bad_Opcode },
7215     { Bad_Opcode },
7216     { Bad_Opcode },
7217     /* 40 */
7218     { PREFIX_TABLE (PREFIX_0F3A40) },
7219     { PREFIX_TABLE (PREFIX_0F3A41) },
7220     { PREFIX_TABLE (PREFIX_0F3A42) },
7221     { Bad_Opcode },
7222     { PREFIX_TABLE (PREFIX_0F3A44) },
7223     { Bad_Opcode },
7224     { Bad_Opcode },
7225     { Bad_Opcode },
7226     /* 48 */
7227     { Bad_Opcode },
7228     { Bad_Opcode },
7229     { Bad_Opcode },
7230     { Bad_Opcode },
7231     { Bad_Opcode },
7232     { Bad_Opcode },
7233     { Bad_Opcode },
7234     { Bad_Opcode },
7235     /* 50 */
7236     { Bad_Opcode },
7237     { Bad_Opcode },
7238     { Bad_Opcode },
7239     { Bad_Opcode },
7240     { Bad_Opcode },
7241     { Bad_Opcode },
7242     { Bad_Opcode },
7243     { Bad_Opcode },
7244     /* 58 */
7245     { Bad_Opcode },
7246     { Bad_Opcode },
7247     { Bad_Opcode },
7248     { Bad_Opcode },
7249     { Bad_Opcode },
7250     { Bad_Opcode },
7251     { Bad_Opcode },
7252     { Bad_Opcode },
7253     /* 60 */
7254     { PREFIX_TABLE (PREFIX_0F3A60) },
7255     { PREFIX_TABLE (PREFIX_0F3A61) },
7256     { PREFIX_TABLE (PREFIX_0F3A62) },
7257     { PREFIX_TABLE (PREFIX_0F3A63) },
7258     { Bad_Opcode },
7259     { Bad_Opcode },
7260     { Bad_Opcode },
7261     { Bad_Opcode },
7262     /* 68 */
7263     { Bad_Opcode },
7264     { Bad_Opcode },
7265     { Bad_Opcode },
7266     { Bad_Opcode },
7267     { Bad_Opcode },
7268     { Bad_Opcode },
7269     { Bad_Opcode },
7270     { Bad_Opcode },
7271     /* 70 */
7272     { Bad_Opcode },
7273     { Bad_Opcode },
7274     { Bad_Opcode },
7275     { Bad_Opcode },
7276     { Bad_Opcode },
7277     { Bad_Opcode },
7278     { Bad_Opcode },
7279     { Bad_Opcode },
7280     /* 78 */
7281     { Bad_Opcode },
7282     { Bad_Opcode },
7283     { Bad_Opcode },
7284     { Bad_Opcode },
7285     { Bad_Opcode },
7286     { Bad_Opcode },
7287     { Bad_Opcode },
7288     { Bad_Opcode },
7289     /* 80 */
7290     { Bad_Opcode },
7291     { Bad_Opcode },
7292     { Bad_Opcode },
7293     { Bad_Opcode },
7294     { Bad_Opcode },
7295     { Bad_Opcode },
7296     { Bad_Opcode },
7297     { Bad_Opcode },
7298     /* 88 */
7299     { Bad_Opcode },
7300     { Bad_Opcode },
7301     { Bad_Opcode },
7302     { Bad_Opcode },
7303     { Bad_Opcode },
7304     { Bad_Opcode },
7305     { Bad_Opcode },
7306     { Bad_Opcode },
7307     /* 90 */
7308     { Bad_Opcode },
7309     { Bad_Opcode },
7310     { Bad_Opcode },
7311     { Bad_Opcode },
7312     { Bad_Opcode },
7313     { Bad_Opcode },
7314     { Bad_Opcode },
7315     { Bad_Opcode },
7316     /* 98 */
7317     { Bad_Opcode },
7318     { Bad_Opcode },
7319     { Bad_Opcode },
7320     { Bad_Opcode },
7321     { Bad_Opcode },
7322     { Bad_Opcode },
7323     { Bad_Opcode },
7324     { Bad_Opcode },
7325     /* a0 */
7326     { Bad_Opcode },
7327     { Bad_Opcode },
7328     { Bad_Opcode },
7329     { Bad_Opcode },
7330     { Bad_Opcode },
7331     { Bad_Opcode },
7332     { Bad_Opcode },
7333     { Bad_Opcode },
7334     /* a8 */
7335     { Bad_Opcode },
7336     { Bad_Opcode },
7337     { Bad_Opcode },
7338     { Bad_Opcode },
7339     { Bad_Opcode },
7340     { Bad_Opcode },
7341     { Bad_Opcode },
7342     { Bad_Opcode },
7343     /* b0 */
7344     { Bad_Opcode },
7345     { Bad_Opcode },
7346     { Bad_Opcode },
7347     { Bad_Opcode },
7348     { Bad_Opcode },
7349     { Bad_Opcode },
7350     { Bad_Opcode },
7351     { Bad_Opcode },
7352     /* b8 */
7353     { Bad_Opcode },
7354     { Bad_Opcode },
7355     { Bad_Opcode },
7356     { Bad_Opcode },
7357     { Bad_Opcode },
7358     { Bad_Opcode },
7359     { Bad_Opcode },
7360     { Bad_Opcode },
7361     /* c0 */
7362     { Bad_Opcode },
7363     { Bad_Opcode },
7364     { Bad_Opcode },
7365     { Bad_Opcode },
7366     { Bad_Opcode },
7367     { Bad_Opcode },
7368     { Bad_Opcode },
7369     { Bad_Opcode },
7370     /* c8 */
7371     { Bad_Opcode },
7372     { Bad_Opcode },
7373     { Bad_Opcode },
7374     { Bad_Opcode },
7375     { PREFIX_TABLE (PREFIX_0F3ACC) },
7376     { Bad_Opcode },
7377     { Bad_Opcode },
7378     { Bad_Opcode },
7379     /* d0 */
7380     { Bad_Opcode },
7381     { Bad_Opcode },
7382     { Bad_Opcode },
7383     { Bad_Opcode },
7384     { Bad_Opcode },
7385     { Bad_Opcode },
7386     { Bad_Opcode },
7387     { Bad_Opcode },
7388     /* d8 */
7389     { Bad_Opcode },
7390     { Bad_Opcode },
7391     { Bad_Opcode },
7392     { Bad_Opcode },
7393     { Bad_Opcode },
7394     { Bad_Opcode },
7395     { Bad_Opcode },
7396     { PREFIX_TABLE (PREFIX_0F3ADF) },
7397     /* e0 */
7398     { Bad_Opcode },
7399     { Bad_Opcode },
7400     { Bad_Opcode },
7401     { Bad_Opcode },
7402     { Bad_Opcode },
7403     { Bad_Opcode },
7404     { Bad_Opcode },
7405     { Bad_Opcode },
7406     /* e8 */
7407     { Bad_Opcode },
7408     { Bad_Opcode },
7409     { Bad_Opcode },
7410     { Bad_Opcode },
7411     { Bad_Opcode },
7412     { Bad_Opcode },
7413     { Bad_Opcode },
7414     { Bad_Opcode },
7415     /* f0 */
7416     { Bad_Opcode },
7417     { Bad_Opcode },
7418     { Bad_Opcode },
7419     { Bad_Opcode },
7420     { Bad_Opcode },
7421     { Bad_Opcode },
7422     { Bad_Opcode },
7423     { Bad_Opcode },
7424     /* f8 */
7425     { Bad_Opcode },
7426     { Bad_Opcode },
7427     { Bad_Opcode },
7428     { Bad_Opcode },
7429     { Bad_Opcode },
7430     { Bad_Opcode },
7431     { Bad_Opcode },
7432     { Bad_Opcode },
7433   },
7434
7435   /* THREE_BYTE_0F7A */
7436   {
7437     /* 00 */
7438     { Bad_Opcode },
7439     { Bad_Opcode },
7440     { Bad_Opcode },
7441     { Bad_Opcode },
7442     { Bad_Opcode },
7443     { Bad_Opcode },
7444     { Bad_Opcode },
7445     { Bad_Opcode },
7446     /* 08 */
7447     { Bad_Opcode },
7448     { Bad_Opcode },
7449     { Bad_Opcode },
7450     { Bad_Opcode },
7451     { Bad_Opcode },
7452     { Bad_Opcode },
7453     { Bad_Opcode },
7454     { Bad_Opcode },
7455     /* 10 */
7456     { Bad_Opcode },
7457     { Bad_Opcode },
7458     { Bad_Opcode },
7459     { Bad_Opcode },
7460     { Bad_Opcode },
7461     { Bad_Opcode },
7462     { Bad_Opcode },
7463     { Bad_Opcode },
7464     /* 18 */
7465     { Bad_Opcode },
7466     { Bad_Opcode },
7467     { Bad_Opcode },
7468     { Bad_Opcode },
7469     { Bad_Opcode },
7470     { Bad_Opcode },
7471     { Bad_Opcode },
7472     { Bad_Opcode },
7473     /* 20 */
7474     { "ptest",          { XX } },
7475     { Bad_Opcode },
7476     { Bad_Opcode },
7477     { Bad_Opcode },
7478     { Bad_Opcode },
7479     { Bad_Opcode },
7480     { Bad_Opcode },
7481     { Bad_Opcode },
7482     /* 28 */
7483     { Bad_Opcode },
7484     { Bad_Opcode },
7485     { Bad_Opcode },
7486     { Bad_Opcode },
7487     { Bad_Opcode },
7488     { Bad_Opcode },
7489     { Bad_Opcode },
7490     { Bad_Opcode },
7491     /* 30 */
7492     { Bad_Opcode },
7493     { Bad_Opcode },
7494     { Bad_Opcode },
7495     { Bad_Opcode },
7496     { Bad_Opcode },
7497     { Bad_Opcode },
7498     { Bad_Opcode },
7499     { Bad_Opcode },
7500     /* 38 */
7501     { Bad_Opcode },
7502     { Bad_Opcode },
7503     { Bad_Opcode },
7504     { Bad_Opcode },
7505     { Bad_Opcode },
7506     { Bad_Opcode },
7507     { Bad_Opcode },
7508     { Bad_Opcode },
7509     /* 40 */
7510     { Bad_Opcode },
7511     { "phaddbw",        { XM, EXq } },
7512     { "phaddbd",        { XM, EXq } },
7513     { "phaddbq",        { XM, EXq } },
7514     { Bad_Opcode },
7515     { Bad_Opcode },
7516     { "phaddwd",        { XM, EXq } },
7517     { "phaddwq",        { XM, EXq } },
7518     /* 48 */
7519     { Bad_Opcode },
7520     { Bad_Opcode },
7521     { Bad_Opcode },
7522     { "phadddq",        { XM, EXq } },
7523     { Bad_Opcode },
7524     { Bad_Opcode },
7525     { Bad_Opcode },
7526     { Bad_Opcode },
7527     /* 50 */
7528     { Bad_Opcode },
7529     { "phaddubw",       { XM, EXq } },
7530     { "phaddubd",       { XM, EXq } },
7531     { "phaddubq",       { XM, EXq } },
7532     { Bad_Opcode },
7533     { Bad_Opcode },
7534     { "phadduwd",       { XM, EXq } },
7535     { "phadduwq",       { XM, EXq } },
7536     /* 58 */
7537     { Bad_Opcode },
7538     { Bad_Opcode },
7539     { Bad_Opcode },
7540     { "phaddudq",       { XM, EXq } },
7541     { Bad_Opcode },
7542     { Bad_Opcode },
7543     { Bad_Opcode },
7544     { Bad_Opcode },
7545     /* 60 */
7546     { Bad_Opcode },
7547     { "phsubbw",        { XM, EXq } },
7548     { "phsubbd",        { XM, EXq } },
7549     { "phsubbq",        { XM, EXq } },
7550     { Bad_Opcode },
7551     { Bad_Opcode },
7552     { Bad_Opcode },
7553     { Bad_Opcode },
7554     /* 68 */
7555     { Bad_Opcode },
7556     { Bad_Opcode },
7557     { Bad_Opcode },
7558     { Bad_Opcode },
7559     { Bad_Opcode },
7560     { Bad_Opcode },
7561     { Bad_Opcode },
7562     { Bad_Opcode },
7563     /* 70 */
7564     { Bad_Opcode },
7565     { Bad_Opcode },
7566     { Bad_Opcode },
7567     { Bad_Opcode },
7568     { Bad_Opcode },
7569     { Bad_Opcode },
7570     { Bad_Opcode },
7571     { Bad_Opcode },
7572     /* 78 */
7573     { Bad_Opcode },
7574     { Bad_Opcode },
7575     { Bad_Opcode },
7576     { Bad_Opcode },
7577     { Bad_Opcode },
7578     { Bad_Opcode },
7579     { Bad_Opcode },
7580     { Bad_Opcode },
7581     /* 80 */
7582     { Bad_Opcode },
7583     { Bad_Opcode },
7584     { Bad_Opcode },
7585     { Bad_Opcode },
7586     { Bad_Opcode },
7587     { Bad_Opcode },
7588     { Bad_Opcode },
7589     { Bad_Opcode },
7590     /* 88 */
7591     { Bad_Opcode },
7592     { Bad_Opcode },
7593     { Bad_Opcode },
7594     { Bad_Opcode },
7595     { Bad_Opcode },
7596     { Bad_Opcode },
7597     { Bad_Opcode },
7598     { Bad_Opcode },
7599     /* 90 */
7600     { Bad_Opcode },
7601     { Bad_Opcode },
7602     { Bad_Opcode },
7603     { Bad_Opcode },
7604     { Bad_Opcode },
7605     { Bad_Opcode },
7606     { Bad_Opcode },
7607     { Bad_Opcode },
7608     /* 98 */
7609     { Bad_Opcode },
7610     { Bad_Opcode },
7611     { Bad_Opcode },
7612     { Bad_Opcode },
7613     { Bad_Opcode },
7614     { Bad_Opcode },
7615     { Bad_Opcode },
7616     { Bad_Opcode },
7617     /* a0 */
7618     { Bad_Opcode },
7619     { Bad_Opcode },
7620     { Bad_Opcode },
7621     { Bad_Opcode },
7622     { Bad_Opcode },
7623     { Bad_Opcode },
7624     { Bad_Opcode },
7625     { Bad_Opcode },
7626     /* a8 */
7627     { Bad_Opcode },
7628     { Bad_Opcode },
7629     { Bad_Opcode },
7630     { Bad_Opcode },
7631     { Bad_Opcode },
7632     { Bad_Opcode },
7633     { Bad_Opcode },
7634     { Bad_Opcode },
7635     /* b0 */
7636     { Bad_Opcode },
7637     { Bad_Opcode },
7638     { Bad_Opcode },
7639     { Bad_Opcode },
7640     { Bad_Opcode },
7641     { Bad_Opcode },
7642     { Bad_Opcode },
7643     { Bad_Opcode },
7644     /* b8 */
7645     { Bad_Opcode },
7646     { Bad_Opcode },
7647     { Bad_Opcode },
7648     { Bad_Opcode },
7649     { Bad_Opcode },
7650     { Bad_Opcode },
7651     { Bad_Opcode },
7652     { Bad_Opcode },
7653     /* c0 */
7654     { Bad_Opcode },
7655     { Bad_Opcode },
7656     { Bad_Opcode },
7657     { Bad_Opcode },
7658     { Bad_Opcode },
7659     { Bad_Opcode },
7660     { Bad_Opcode },
7661     { Bad_Opcode },
7662     /* c8 */
7663     { Bad_Opcode },
7664     { Bad_Opcode },
7665     { Bad_Opcode },
7666     { Bad_Opcode },
7667     { Bad_Opcode },
7668     { Bad_Opcode },
7669     { Bad_Opcode },
7670     { Bad_Opcode },
7671     /* d0 */
7672     { Bad_Opcode },
7673     { Bad_Opcode },
7674     { Bad_Opcode },
7675     { Bad_Opcode },
7676     { Bad_Opcode },
7677     { Bad_Opcode },
7678     { Bad_Opcode },
7679     { Bad_Opcode },
7680     /* d8 */
7681     { Bad_Opcode },
7682     { Bad_Opcode },
7683     { Bad_Opcode },
7684     { Bad_Opcode },
7685     { Bad_Opcode },
7686     { Bad_Opcode },
7687     { Bad_Opcode },
7688     { Bad_Opcode },
7689     /* e0 */
7690     { Bad_Opcode },
7691     { Bad_Opcode },
7692     { Bad_Opcode },
7693     { Bad_Opcode },
7694     { Bad_Opcode },
7695     { Bad_Opcode },
7696     { Bad_Opcode },
7697     { Bad_Opcode },
7698     /* e8 */
7699     { Bad_Opcode },
7700     { Bad_Opcode },
7701     { Bad_Opcode },
7702     { Bad_Opcode },
7703     { Bad_Opcode },
7704     { Bad_Opcode },
7705     { Bad_Opcode },
7706     { Bad_Opcode },
7707     /* f0 */
7708     { Bad_Opcode },
7709     { Bad_Opcode },
7710     { Bad_Opcode },
7711     { Bad_Opcode },
7712     { Bad_Opcode },
7713     { Bad_Opcode },
7714     { Bad_Opcode },
7715     { Bad_Opcode },
7716     /* f8 */
7717     { Bad_Opcode },
7718     { Bad_Opcode },
7719     { Bad_Opcode },
7720     { Bad_Opcode },
7721     { Bad_Opcode },
7722     { Bad_Opcode },
7723     { Bad_Opcode },
7724     { Bad_Opcode },
7725   },
7726 };
7727
7728 static const struct dis386 xop_table[][256] = {
7729   /* XOP_08 */
7730   {
7731     /* 00 */
7732     { Bad_Opcode },
7733     { Bad_Opcode },
7734     { Bad_Opcode },
7735     { Bad_Opcode },
7736     { Bad_Opcode },
7737     { Bad_Opcode },
7738     { Bad_Opcode },
7739     { Bad_Opcode },
7740     /* 08 */
7741     { Bad_Opcode },
7742     { Bad_Opcode },
7743     { Bad_Opcode },
7744     { Bad_Opcode },
7745     { Bad_Opcode },
7746     { Bad_Opcode },
7747     { Bad_Opcode },
7748     { Bad_Opcode },
7749     /* 10 */
7750     { Bad_Opcode },
7751     { Bad_Opcode },
7752     { Bad_Opcode },
7753     { Bad_Opcode },
7754     { Bad_Opcode },
7755     { Bad_Opcode },
7756     { Bad_Opcode },
7757     { Bad_Opcode },
7758     /* 18 */
7759     { Bad_Opcode },
7760     { Bad_Opcode },
7761     { Bad_Opcode },
7762     { Bad_Opcode },
7763     { Bad_Opcode },
7764     { Bad_Opcode },
7765     { Bad_Opcode },
7766     { Bad_Opcode },
7767     /* 20 */
7768     { Bad_Opcode },
7769     { Bad_Opcode },
7770     { Bad_Opcode },
7771     { Bad_Opcode },
7772     { Bad_Opcode },
7773     { Bad_Opcode },
7774     { Bad_Opcode },
7775     { Bad_Opcode },
7776     /* 28 */
7777     { Bad_Opcode },
7778     { Bad_Opcode },
7779     { Bad_Opcode },
7780     { Bad_Opcode },
7781     { Bad_Opcode },
7782     { Bad_Opcode },
7783     { Bad_Opcode },
7784     { Bad_Opcode },
7785     /* 30 */
7786     { Bad_Opcode },
7787     { Bad_Opcode },
7788     { Bad_Opcode },
7789     { Bad_Opcode },
7790     { Bad_Opcode },
7791     { Bad_Opcode },
7792     { Bad_Opcode },
7793     { Bad_Opcode },
7794     /* 38 */
7795     { Bad_Opcode },
7796     { Bad_Opcode },
7797     { Bad_Opcode },
7798     { Bad_Opcode },
7799     { Bad_Opcode },
7800     { Bad_Opcode },
7801     { Bad_Opcode },
7802     { Bad_Opcode },
7803     /* 40 */
7804     { Bad_Opcode },
7805     { Bad_Opcode },
7806     { Bad_Opcode },
7807     { Bad_Opcode },
7808     { Bad_Opcode },
7809     { Bad_Opcode },
7810     { Bad_Opcode },
7811     { Bad_Opcode },
7812     /* 48 */
7813     { Bad_Opcode },
7814     { Bad_Opcode },
7815     { Bad_Opcode },
7816     { Bad_Opcode },
7817     { Bad_Opcode },
7818     { Bad_Opcode },
7819     { Bad_Opcode },
7820     { Bad_Opcode },
7821     /* 50 */
7822     { Bad_Opcode },
7823     { Bad_Opcode },
7824     { Bad_Opcode },
7825     { Bad_Opcode },
7826     { Bad_Opcode },
7827     { Bad_Opcode },
7828     { Bad_Opcode },
7829     { Bad_Opcode },
7830     /* 58 */
7831     { Bad_Opcode },
7832     { Bad_Opcode },
7833     { Bad_Opcode },
7834     { Bad_Opcode },
7835     { Bad_Opcode },
7836     { Bad_Opcode },
7837     { Bad_Opcode },
7838     { Bad_Opcode },
7839     /* 60 */
7840     { Bad_Opcode },
7841     { Bad_Opcode },
7842     { Bad_Opcode },
7843     { Bad_Opcode },
7844     { Bad_Opcode },
7845     { Bad_Opcode },
7846     { Bad_Opcode },
7847     { Bad_Opcode },
7848     /* 68 */
7849     { Bad_Opcode },
7850     { Bad_Opcode },
7851     { Bad_Opcode },
7852     { Bad_Opcode },
7853     { Bad_Opcode },
7854     { Bad_Opcode },
7855     { Bad_Opcode },
7856     { Bad_Opcode },
7857     /* 70 */
7858     { Bad_Opcode },
7859     { Bad_Opcode },
7860     { Bad_Opcode },
7861     { Bad_Opcode },
7862     { Bad_Opcode },
7863     { Bad_Opcode },
7864     { Bad_Opcode },
7865     { Bad_Opcode },
7866     /* 78 */
7867     { Bad_Opcode },
7868     { Bad_Opcode },
7869     { Bad_Opcode },
7870     { Bad_Opcode },
7871     { Bad_Opcode },
7872     { Bad_Opcode },
7873     { Bad_Opcode },
7874     { Bad_Opcode },
7875     /* 80 */
7876     { Bad_Opcode },
7877     { Bad_Opcode },
7878     { Bad_Opcode },
7879     { Bad_Opcode },
7880     { Bad_Opcode },
7881     { "vpmacssww",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7882     { "vpmacsswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7883     { "vpmacssdql",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7884     /* 88 */
7885     { Bad_Opcode },
7886     { Bad_Opcode },
7887     { Bad_Opcode },
7888     { Bad_Opcode },
7889     { Bad_Opcode },
7890     { Bad_Opcode },
7891     { "vpmacssdd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7892     { "vpmacssdqh",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7893     /* 90 */
7894     { Bad_Opcode },
7895     { Bad_Opcode },
7896     { Bad_Opcode },
7897     { Bad_Opcode },
7898     { Bad_Opcode },
7899     { "vpmacsww",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7900     { "vpmacswd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7901     { "vpmacsdql",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7902     /* 98 */
7903     { Bad_Opcode },
7904     { Bad_Opcode },
7905     { Bad_Opcode },
7906     { Bad_Opcode },
7907     { Bad_Opcode },
7908     { Bad_Opcode },
7909     { "vpmacsdd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7910     { "vpmacsdqh",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7911     /* a0 */
7912     { Bad_Opcode },
7913     { Bad_Opcode },
7914     { "vpcmov",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7915     { "vpperm",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7916     { Bad_Opcode },
7917     { Bad_Opcode },
7918     { "vpmadcsswd",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7919     { Bad_Opcode },
7920     /* a8 */
7921     { Bad_Opcode },
7922     { Bad_Opcode },
7923     { Bad_Opcode },
7924     { Bad_Opcode },
7925     { Bad_Opcode },
7926     { Bad_Opcode },
7927     { Bad_Opcode },
7928     { Bad_Opcode },
7929     /* b0 */
7930     { Bad_Opcode },
7931     { Bad_Opcode },
7932     { Bad_Opcode },
7933     { Bad_Opcode },
7934     { Bad_Opcode },
7935     { Bad_Opcode },
7936     { "vpmadcswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7937     { Bad_Opcode },
7938     /* b8 */
7939     { Bad_Opcode },
7940     { Bad_Opcode },
7941     { Bad_Opcode },
7942     { Bad_Opcode },
7943     { Bad_Opcode },
7944     { Bad_Opcode },
7945     { Bad_Opcode },
7946     { Bad_Opcode },
7947     /* c0 */
7948     { "vprotb",         { XM, Vex_2src_1, Ib } },
7949     { "vprotw",         { XM, Vex_2src_1, Ib } },
7950     { "vprotd",         { XM, Vex_2src_1, Ib } },
7951     { "vprotq",         { XM, Vex_2src_1, Ib } },
7952     { Bad_Opcode },
7953     { Bad_Opcode },
7954     { Bad_Opcode },
7955     { Bad_Opcode },
7956     /* c8 */
7957     { Bad_Opcode },
7958     { Bad_Opcode },
7959     { Bad_Opcode },
7960     { Bad_Opcode },
7961     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
7962     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
7963     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
7964     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
7965     /* d0 */
7966     { Bad_Opcode },
7967     { Bad_Opcode },
7968     { Bad_Opcode },
7969     { Bad_Opcode },
7970     { Bad_Opcode },
7971     { Bad_Opcode },
7972     { Bad_Opcode },
7973     { Bad_Opcode },
7974     /* d8 */
7975     { Bad_Opcode },
7976     { Bad_Opcode },
7977     { Bad_Opcode },
7978     { Bad_Opcode },
7979     { Bad_Opcode },
7980     { Bad_Opcode },
7981     { Bad_Opcode },
7982     { Bad_Opcode },
7983     /* e0 */
7984     { Bad_Opcode },
7985     { Bad_Opcode },
7986     { Bad_Opcode },
7987     { Bad_Opcode },
7988     { Bad_Opcode },
7989     { Bad_Opcode },
7990     { Bad_Opcode },
7991     { Bad_Opcode },
7992     /* e8 */
7993     { Bad_Opcode },
7994     { Bad_Opcode },
7995     { Bad_Opcode },
7996     { Bad_Opcode },
7997     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
7998     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
7999     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
8000     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
8001     /* f0 */
8002     { Bad_Opcode },
8003     { Bad_Opcode },
8004     { Bad_Opcode },
8005     { Bad_Opcode },
8006     { Bad_Opcode },
8007     { Bad_Opcode },
8008     { Bad_Opcode },
8009     { Bad_Opcode },
8010     /* f8 */
8011     { Bad_Opcode },
8012     { Bad_Opcode },
8013     { Bad_Opcode },
8014     { Bad_Opcode },
8015     { Bad_Opcode },
8016     { Bad_Opcode },
8017     { Bad_Opcode },
8018     { Bad_Opcode },
8019   },
8020   /* XOP_09 */
8021   {
8022     /* 00 */
8023     { Bad_Opcode },
8024     { REG_TABLE (REG_XOP_TBM_01) },
8025     { REG_TABLE (REG_XOP_TBM_02) },
8026     { Bad_Opcode },
8027     { Bad_Opcode },
8028     { Bad_Opcode },
8029     { Bad_Opcode },
8030     { Bad_Opcode },
8031     /* 08 */
8032     { Bad_Opcode },
8033     { Bad_Opcode },
8034     { Bad_Opcode },
8035     { Bad_Opcode },
8036     { Bad_Opcode },
8037     { Bad_Opcode },
8038     { Bad_Opcode },
8039     { Bad_Opcode },
8040     /* 10 */
8041     { Bad_Opcode },
8042     { Bad_Opcode },
8043     { REG_TABLE (REG_XOP_LWPCB) },
8044     { Bad_Opcode },
8045     { Bad_Opcode },
8046     { Bad_Opcode },
8047     { Bad_Opcode },
8048     { Bad_Opcode },
8049     /* 18 */
8050     { Bad_Opcode },
8051     { Bad_Opcode },
8052     { Bad_Opcode },
8053     { Bad_Opcode },
8054     { Bad_Opcode },
8055     { Bad_Opcode },
8056     { Bad_Opcode },
8057     { Bad_Opcode },
8058     /* 20 */
8059     { Bad_Opcode },
8060     { Bad_Opcode },
8061     { Bad_Opcode },
8062     { Bad_Opcode },
8063     { Bad_Opcode },
8064     { Bad_Opcode },
8065     { Bad_Opcode },
8066     { Bad_Opcode },
8067     /* 28 */
8068     { Bad_Opcode },
8069     { Bad_Opcode },
8070     { Bad_Opcode },
8071     { Bad_Opcode },
8072     { Bad_Opcode },
8073     { Bad_Opcode },
8074     { Bad_Opcode },
8075     { Bad_Opcode },
8076     /* 30 */
8077     { Bad_Opcode },
8078     { Bad_Opcode },
8079     { Bad_Opcode },
8080     { Bad_Opcode },
8081     { Bad_Opcode },
8082     { Bad_Opcode },
8083     { Bad_Opcode },
8084     { Bad_Opcode },
8085     /* 38 */
8086     { Bad_Opcode },
8087     { Bad_Opcode },
8088     { Bad_Opcode },
8089     { Bad_Opcode },
8090     { Bad_Opcode },
8091     { Bad_Opcode },
8092     { Bad_Opcode },
8093     { Bad_Opcode },
8094     /* 40 */
8095     { Bad_Opcode },
8096     { Bad_Opcode },
8097     { Bad_Opcode },
8098     { Bad_Opcode },
8099     { Bad_Opcode },
8100     { Bad_Opcode },
8101     { Bad_Opcode },
8102     { Bad_Opcode },
8103     /* 48 */
8104     { Bad_Opcode },
8105     { Bad_Opcode },
8106     { Bad_Opcode },
8107     { Bad_Opcode },
8108     { Bad_Opcode },
8109     { Bad_Opcode },
8110     { Bad_Opcode },
8111     { Bad_Opcode },
8112     /* 50 */
8113     { Bad_Opcode },
8114     { Bad_Opcode },
8115     { Bad_Opcode },
8116     { Bad_Opcode },
8117     { Bad_Opcode },
8118     { Bad_Opcode },
8119     { Bad_Opcode },
8120     { Bad_Opcode },
8121     /* 58 */
8122     { Bad_Opcode },
8123     { Bad_Opcode },
8124     { Bad_Opcode },
8125     { Bad_Opcode },
8126     { Bad_Opcode },
8127     { Bad_Opcode },
8128     { Bad_Opcode },
8129     { Bad_Opcode },
8130     /* 60 */
8131     { Bad_Opcode },
8132     { Bad_Opcode },
8133     { Bad_Opcode },
8134     { Bad_Opcode },
8135     { Bad_Opcode },
8136     { Bad_Opcode },
8137     { Bad_Opcode },
8138     { Bad_Opcode },
8139     /* 68 */
8140     { Bad_Opcode },
8141     { Bad_Opcode },
8142     { Bad_Opcode },
8143     { Bad_Opcode },
8144     { Bad_Opcode },
8145     { Bad_Opcode },
8146     { Bad_Opcode },
8147     { Bad_Opcode },
8148     /* 70 */
8149     { Bad_Opcode },
8150     { Bad_Opcode },
8151     { Bad_Opcode },
8152     { Bad_Opcode },
8153     { Bad_Opcode },
8154     { Bad_Opcode },
8155     { Bad_Opcode },
8156     { Bad_Opcode },
8157     /* 78 */
8158     { Bad_Opcode },
8159     { Bad_Opcode },
8160     { Bad_Opcode },
8161     { Bad_Opcode },
8162     { Bad_Opcode },
8163     { Bad_Opcode },
8164     { Bad_Opcode },
8165     { Bad_Opcode },
8166     /* 80 */
8167     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
8168     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
8169     { "vfrczss",        { XM, EXd } },
8170     { "vfrczsd",        { XM, EXq } },
8171     { Bad_Opcode },
8172     { Bad_Opcode },
8173     { Bad_Opcode },
8174     { Bad_Opcode },
8175     /* 88 */
8176     { Bad_Opcode },
8177     { Bad_Opcode },
8178     { Bad_Opcode },
8179     { Bad_Opcode },
8180     { Bad_Opcode },
8181     { Bad_Opcode },
8182     { Bad_Opcode },
8183     { Bad_Opcode },
8184     /* 90 */
8185     { "vprotb",         { XM, Vex_2src_1, Vex_2src_2 } },
8186     { "vprotw",         { XM, Vex_2src_1, Vex_2src_2 } },
8187     { "vprotd",         { XM, Vex_2src_1, Vex_2src_2 } },
8188     { "vprotq",         { XM, Vex_2src_1, Vex_2src_2 } },
8189     { "vpshlb",         { XM, Vex_2src_1, Vex_2src_2 } },
8190     { "vpshlw",         { XM, Vex_2src_1, Vex_2src_2 } },
8191     { "vpshld",         { XM, Vex_2src_1, Vex_2src_2 } },
8192     { "vpshlq",         { XM, Vex_2src_1, Vex_2src_2 } },
8193     /* 98 */
8194     { "vpshab",         { XM, Vex_2src_1, Vex_2src_2 } },
8195     { "vpshaw",         { XM, Vex_2src_1, Vex_2src_2 } },
8196     { "vpshad",         { XM, Vex_2src_1, Vex_2src_2 } },
8197     { "vpshaq",         { XM, Vex_2src_1, Vex_2src_2 } },
8198     { Bad_Opcode },
8199     { Bad_Opcode },
8200     { Bad_Opcode },
8201     { Bad_Opcode },
8202     /* a0 */
8203     { Bad_Opcode },
8204     { Bad_Opcode },
8205     { Bad_Opcode },
8206     { Bad_Opcode },
8207     { Bad_Opcode },
8208     { Bad_Opcode },
8209     { Bad_Opcode },
8210     { Bad_Opcode },
8211     /* a8 */
8212     { Bad_Opcode },
8213     { Bad_Opcode },
8214     { Bad_Opcode },
8215     { Bad_Opcode },
8216     { Bad_Opcode },
8217     { Bad_Opcode },
8218     { Bad_Opcode },
8219     { Bad_Opcode },
8220     /* b0 */
8221     { Bad_Opcode },
8222     { Bad_Opcode },
8223     { Bad_Opcode },
8224     { Bad_Opcode },
8225     { Bad_Opcode },
8226     { Bad_Opcode },
8227     { Bad_Opcode },
8228     { Bad_Opcode },
8229     /* b8 */
8230     { Bad_Opcode },
8231     { Bad_Opcode },
8232     { Bad_Opcode },
8233     { Bad_Opcode },
8234     { Bad_Opcode },
8235     { Bad_Opcode },
8236     { Bad_Opcode },
8237     { Bad_Opcode },
8238     /* c0 */
8239     { Bad_Opcode },
8240     { "vphaddbw",       { XM, EXxmm } },
8241     { "vphaddbd",       { XM, EXxmm } },
8242     { "vphaddbq",       { XM, EXxmm } },
8243     { Bad_Opcode },
8244     { Bad_Opcode },
8245     { "vphaddwd",       { XM, EXxmm } },
8246     { "vphaddwq",       { XM, EXxmm } },
8247     /* c8 */
8248     { Bad_Opcode },
8249     { Bad_Opcode },
8250     { Bad_Opcode },
8251     { "vphadddq",       { XM, EXxmm } },
8252     { Bad_Opcode },
8253     { Bad_Opcode },
8254     { Bad_Opcode },
8255     { Bad_Opcode },
8256     /* d0 */
8257     { Bad_Opcode },
8258     { "vphaddubw",      { XM, EXxmm } },
8259     { "vphaddubd",      { XM, EXxmm } },
8260     { "vphaddubq",      { XM, EXxmm } },
8261     { Bad_Opcode },
8262     { Bad_Opcode },
8263     { "vphadduwd",      { XM, EXxmm } },
8264     { "vphadduwq",      { XM, EXxmm } },
8265     /* d8 */
8266     { Bad_Opcode },
8267     { Bad_Opcode },
8268     { Bad_Opcode },
8269     { "vphaddudq",      { XM, EXxmm } },
8270     { Bad_Opcode },
8271     { Bad_Opcode },
8272     { Bad_Opcode },
8273     { Bad_Opcode },
8274     /* e0 */
8275     { Bad_Opcode },
8276     { "vphsubbw",       { XM, EXxmm } },
8277     { "vphsubwd",       { XM, EXxmm } },
8278     { "vphsubdq",       { XM, EXxmm } },
8279     { Bad_Opcode },
8280     { Bad_Opcode },
8281     { Bad_Opcode },
8282     { Bad_Opcode },
8283     /* e8 */
8284     { Bad_Opcode },
8285     { Bad_Opcode },
8286     { Bad_Opcode },
8287     { Bad_Opcode },
8288     { Bad_Opcode },
8289     { Bad_Opcode },
8290     { Bad_Opcode },
8291     { Bad_Opcode },
8292     /* f0 */
8293     { Bad_Opcode },
8294     { Bad_Opcode },
8295     { Bad_Opcode },
8296     { Bad_Opcode },
8297     { Bad_Opcode },
8298     { Bad_Opcode },
8299     { Bad_Opcode },
8300     { Bad_Opcode },
8301     /* f8 */
8302     { Bad_Opcode },
8303     { Bad_Opcode },
8304     { Bad_Opcode },
8305     { Bad_Opcode },
8306     { Bad_Opcode },
8307     { Bad_Opcode },
8308     { Bad_Opcode },
8309     { Bad_Opcode },
8310   },
8311   /* XOP_0A */
8312   {
8313     /* 00 */
8314     { Bad_Opcode },
8315     { Bad_Opcode },
8316     { Bad_Opcode },
8317     { Bad_Opcode },
8318     { Bad_Opcode },
8319     { Bad_Opcode },
8320     { Bad_Opcode },
8321     { Bad_Opcode },
8322     /* 08 */
8323     { Bad_Opcode },
8324     { Bad_Opcode },
8325     { Bad_Opcode },
8326     { Bad_Opcode },
8327     { Bad_Opcode },
8328     { Bad_Opcode },
8329     { Bad_Opcode },
8330     { Bad_Opcode },
8331     /* 10 */
8332     { "bextr",  { Gv, Ev, Iq } },
8333     { Bad_Opcode },
8334     { REG_TABLE (REG_XOP_LWP) },
8335     { Bad_Opcode },
8336     { Bad_Opcode },
8337     { Bad_Opcode },
8338     { Bad_Opcode },
8339     { Bad_Opcode },
8340     /* 18 */
8341     { Bad_Opcode },
8342     { Bad_Opcode },
8343     { Bad_Opcode },
8344     { Bad_Opcode },
8345     { Bad_Opcode },
8346     { Bad_Opcode },
8347     { Bad_Opcode },
8348     { Bad_Opcode },
8349     /* 20 */
8350     { Bad_Opcode },
8351     { Bad_Opcode },
8352     { Bad_Opcode },
8353     { Bad_Opcode },
8354     { Bad_Opcode },
8355     { Bad_Opcode },
8356     { Bad_Opcode },
8357     { Bad_Opcode },
8358     /* 28 */
8359     { Bad_Opcode },
8360     { Bad_Opcode },
8361     { Bad_Opcode },
8362     { Bad_Opcode },
8363     { Bad_Opcode },
8364     { Bad_Opcode },
8365     { Bad_Opcode },
8366     { Bad_Opcode },
8367     /* 30 */
8368     { Bad_Opcode },
8369     { Bad_Opcode },
8370     { Bad_Opcode },
8371     { Bad_Opcode },
8372     { Bad_Opcode },
8373     { Bad_Opcode },
8374     { Bad_Opcode },
8375     { Bad_Opcode },
8376     /* 38 */
8377     { Bad_Opcode },
8378     { Bad_Opcode },
8379     { Bad_Opcode },
8380     { Bad_Opcode },
8381     { Bad_Opcode },
8382     { Bad_Opcode },
8383     { Bad_Opcode },
8384     { Bad_Opcode },
8385     /* 40 */
8386     { Bad_Opcode },
8387     { Bad_Opcode },
8388     { Bad_Opcode },
8389     { Bad_Opcode },
8390     { Bad_Opcode },
8391     { Bad_Opcode },
8392     { Bad_Opcode },
8393     { Bad_Opcode },
8394     /* 48 */
8395     { Bad_Opcode },
8396     { Bad_Opcode },
8397     { Bad_Opcode },
8398     { Bad_Opcode },
8399     { Bad_Opcode },
8400     { Bad_Opcode },
8401     { Bad_Opcode },
8402     { Bad_Opcode },
8403     /* 50 */
8404     { Bad_Opcode },
8405     { Bad_Opcode },
8406     { Bad_Opcode },
8407     { Bad_Opcode },
8408     { Bad_Opcode },
8409     { Bad_Opcode },
8410     { Bad_Opcode },
8411     { Bad_Opcode },
8412     /* 58 */
8413     { Bad_Opcode },
8414     { Bad_Opcode },
8415     { Bad_Opcode },
8416     { Bad_Opcode },
8417     { Bad_Opcode },
8418     { Bad_Opcode },
8419     { Bad_Opcode },
8420     { Bad_Opcode },
8421     /* 60 */
8422     { Bad_Opcode },
8423     { Bad_Opcode },
8424     { Bad_Opcode },
8425     { Bad_Opcode },
8426     { Bad_Opcode },
8427     { Bad_Opcode },
8428     { Bad_Opcode },
8429     { Bad_Opcode },
8430     /* 68 */
8431     { Bad_Opcode },
8432     { Bad_Opcode },
8433     { Bad_Opcode },
8434     { Bad_Opcode },
8435     { Bad_Opcode },
8436     { Bad_Opcode },
8437     { Bad_Opcode },
8438     { Bad_Opcode },
8439     /* 70 */
8440     { Bad_Opcode },
8441     { Bad_Opcode },
8442     { Bad_Opcode },
8443     { Bad_Opcode },
8444     { Bad_Opcode },
8445     { Bad_Opcode },
8446     { Bad_Opcode },
8447     { Bad_Opcode },
8448     /* 78 */
8449     { Bad_Opcode },
8450     { Bad_Opcode },
8451     { Bad_Opcode },
8452     { Bad_Opcode },
8453     { Bad_Opcode },
8454     { Bad_Opcode },
8455     { Bad_Opcode },
8456     { Bad_Opcode },
8457     /* 80 */
8458     { Bad_Opcode },
8459     { Bad_Opcode },
8460     { Bad_Opcode },
8461     { Bad_Opcode },
8462     { Bad_Opcode },
8463     { Bad_Opcode },
8464     { Bad_Opcode },
8465     { Bad_Opcode },
8466     /* 88 */
8467     { Bad_Opcode },
8468     { Bad_Opcode },
8469     { Bad_Opcode },
8470     { Bad_Opcode },
8471     { Bad_Opcode },
8472     { Bad_Opcode },
8473     { Bad_Opcode },
8474     { Bad_Opcode },
8475     /* 90 */
8476     { Bad_Opcode },
8477     { Bad_Opcode },
8478     { Bad_Opcode },
8479     { Bad_Opcode },
8480     { Bad_Opcode },
8481     { Bad_Opcode },
8482     { Bad_Opcode },
8483     { Bad_Opcode },
8484     /* 98 */
8485     { Bad_Opcode },
8486     { Bad_Opcode },
8487     { Bad_Opcode },
8488     { Bad_Opcode },
8489     { Bad_Opcode },
8490     { Bad_Opcode },
8491     { Bad_Opcode },
8492     { Bad_Opcode },
8493     /* a0 */
8494     { Bad_Opcode },
8495     { Bad_Opcode },
8496     { Bad_Opcode },
8497     { Bad_Opcode },
8498     { Bad_Opcode },
8499     { Bad_Opcode },
8500     { Bad_Opcode },
8501     { Bad_Opcode },
8502     /* a8 */
8503     { Bad_Opcode },
8504     { Bad_Opcode },
8505     { Bad_Opcode },
8506     { Bad_Opcode },
8507     { Bad_Opcode },
8508     { Bad_Opcode },
8509     { Bad_Opcode },
8510     { Bad_Opcode },
8511     /* b0 */
8512     { Bad_Opcode },
8513     { Bad_Opcode },
8514     { Bad_Opcode },
8515     { Bad_Opcode },
8516     { Bad_Opcode },
8517     { Bad_Opcode },
8518     { Bad_Opcode },
8519     { Bad_Opcode },
8520     /* b8 */
8521     { Bad_Opcode },
8522     { Bad_Opcode },
8523     { Bad_Opcode },
8524     { Bad_Opcode },
8525     { Bad_Opcode },
8526     { Bad_Opcode },
8527     { Bad_Opcode },
8528     { Bad_Opcode },
8529     /* c0 */
8530     { Bad_Opcode },
8531     { Bad_Opcode },
8532     { Bad_Opcode },
8533     { Bad_Opcode },
8534     { Bad_Opcode },
8535     { Bad_Opcode },
8536     { Bad_Opcode },
8537     { Bad_Opcode },
8538     /* c8 */
8539     { Bad_Opcode },
8540     { Bad_Opcode },
8541     { Bad_Opcode },
8542     { Bad_Opcode },
8543     { Bad_Opcode },
8544     { Bad_Opcode },
8545     { Bad_Opcode },
8546     { Bad_Opcode },
8547     /* d0 */
8548     { Bad_Opcode },
8549     { Bad_Opcode },
8550     { Bad_Opcode },
8551     { Bad_Opcode },
8552     { Bad_Opcode },
8553     { Bad_Opcode },
8554     { Bad_Opcode },
8555     { Bad_Opcode },
8556     /* d8 */
8557     { Bad_Opcode },
8558     { Bad_Opcode },
8559     { Bad_Opcode },
8560     { Bad_Opcode },
8561     { Bad_Opcode },
8562     { Bad_Opcode },
8563     { Bad_Opcode },
8564     { Bad_Opcode },
8565     /* e0 */
8566     { Bad_Opcode },
8567     { Bad_Opcode },
8568     { Bad_Opcode },
8569     { Bad_Opcode },
8570     { Bad_Opcode },
8571     { Bad_Opcode },
8572     { Bad_Opcode },
8573     { Bad_Opcode },
8574     /* e8 */
8575     { Bad_Opcode },
8576     { Bad_Opcode },
8577     { Bad_Opcode },
8578     { Bad_Opcode },
8579     { Bad_Opcode },
8580     { Bad_Opcode },
8581     { Bad_Opcode },
8582     { Bad_Opcode },
8583     /* f0 */
8584     { Bad_Opcode },
8585     { Bad_Opcode },
8586     { Bad_Opcode },
8587     { Bad_Opcode },
8588     { Bad_Opcode },
8589     { Bad_Opcode },
8590     { Bad_Opcode },
8591     { Bad_Opcode },
8592     /* f8 */
8593     { Bad_Opcode },
8594     { Bad_Opcode },
8595     { Bad_Opcode },
8596     { Bad_Opcode },
8597     { Bad_Opcode },
8598     { Bad_Opcode },
8599     { Bad_Opcode },
8600     { Bad_Opcode },
8601   },
8602 };
8603
8604 static const struct dis386 vex_table[][256] = {
8605   /* VEX_0F */
8606   {
8607     /* 00 */
8608     { Bad_Opcode },
8609     { Bad_Opcode },
8610     { Bad_Opcode },
8611     { Bad_Opcode },
8612     { Bad_Opcode },
8613     { Bad_Opcode },
8614     { Bad_Opcode },
8615     { Bad_Opcode },
8616     /* 08 */
8617     { Bad_Opcode },
8618     { Bad_Opcode },
8619     { Bad_Opcode },
8620     { Bad_Opcode },
8621     { Bad_Opcode },
8622     { Bad_Opcode },
8623     { Bad_Opcode },
8624     { Bad_Opcode },
8625     /* 10 */
8626     { PREFIX_TABLE (PREFIX_VEX_0F10) },
8627     { PREFIX_TABLE (PREFIX_VEX_0F11) },
8628     { PREFIX_TABLE (PREFIX_VEX_0F12) },
8629     { MOD_TABLE (MOD_VEX_0F13) },
8630     { VEX_W_TABLE (VEX_W_0F14) },
8631     { VEX_W_TABLE (VEX_W_0F15) },
8632     { PREFIX_TABLE (PREFIX_VEX_0F16) },
8633     { MOD_TABLE (MOD_VEX_0F17) },
8634     /* 18 */
8635     { Bad_Opcode },
8636     { Bad_Opcode },
8637     { Bad_Opcode },
8638     { Bad_Opcode },
8639     { Bad_Opcode },
8640     { Bad_Opcode },
8641     { Bad_Opcode },
8642     { Bad_Opcode },
8643     /* 20 */
8644     { Bad_Opcode },
8645     { Bad_Opcode },
8646     { Bad_Opcode },
8647     { Bad_Opcode },
8648     { Bad_Opcode },
8649     { Bad_Opcode },
8650     { Bad_Opcode },
8651     { Bad_Opcode },
8652     /* 28 */
8653     { VEX_W_TABLE (VEX_W_0F28) },
8654     { VEX_W_TABLE (VEX_W_0F29) },
8655     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8656     { MOD_TABLE (MOD_VEX_0F2B) },
8657     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8658     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8659     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8660     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8661     /* 30 */
8662     { Bad_Opcode },
8663     { Bad_Opcode },
8664     { Bad_Opcode },
8665     { Bad_Opcode },
8666     { Bad_Opcode },
8667     { Bad_Opcode },
8668     { Bad_Opcode },
8669     { Bad_Opcode },
8670     /* 38 */
8671     { Bad_Opcode },
8672     { Bad_Opcode },
8673     { Bad_Opcode },
8674     { Bad_Opcode },
8675     { Bad_Opcode },
8676     { Bad_Opcode },
8677     { Bad_Opcode },
8678     { Bad_Opcode },
8679     /* 40 */
8680     { Bad_Opcode },
8681     { PREFIX_TABLE (PREFIX_VEX_0F41) },
8682     { PREFIX_TABLE (PREFIX_VEX_0F42) },
8683     { Bad_Opcode },
8684     { PREFIX_TABLE (PREFIX_VEX_0F44) },
8685     { PREFIX_TABLE (PREFIX_VEX_0F45) },
8686     { PREFIX_TABLE (PREFIX_VEX_0F46) },
8687     { PREFIX_TABLE (PREFIX_VEX_0F47) },
8688     /* 48 */
8689     { Bad_Opcode },
8690     { Bad_Opcode },
8691     { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8692     { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8693     { Bad_Opcode },
8694     { Bad_Opcode },
8695     { Bad_Opcode },
8696     { Bad_Opcode },
8697     /* 50 */
8698     { MOD_TABLE (MOD_VEX_0F50) },
8699     { PREFIX_TABLE (PREFIX_VEX_0F51) },
8700     { PREFIX_TABLE (PREFIX_VEX_0F52) },
8701     { PREFIX_TABLE (PREFIX_VEX_0F53) },
8702     { "vandpX",         { XM, Vex, EXx } },
8703     { "vandnpX",        { XM, Vex, EXx } },
8704     { "vorpX",          { XM, Vex, EXx } },
8705     { "vxorpX",         { XM, Vex, EXx } },
8706     /* 58 */
8707     { PREFIX_TABLE (PREFIX_VEX_0F58) },
8708     { PREFIX_TABLE (PREFIX_VEX_0F59) },
8709     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8710     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8711     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8712     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8713     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8714     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8715     /* 60 */
8716     { PREFIX_TABLE (PREFIX_VEX_0F60) },
8717     { PREFIX_TABLE (PREFIX_VEX_0F61) },
8718     { PREFIX_TABLE (PREFIX_VEX_0F62) },
8719     { PREFIX_TABLE (PREFIX_VEX_0F63) },
8720     { PREFIX_TABLE (PREFIX_VEX_0F64) },
8721     { PREFIX_TABLE (PREFIX_VEX_0F65) },
8722     { PREFIX_TABLE (PREFIX_VEX_0F66) },
8723     { PREFIX_TABLE (PREFIX_VEX_0F67) },
8724     /* 68 */
8725     { PREFIX_TABLE (PREFIX_VEX_0F68) },
8726     { PREFIX_TABLE (PREFIX_VEX_0F69) },
8727     { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8728     { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8729     { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8730     { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8731     { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8732     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8733     /* 70 */
8734     { PREFIX_TABLE (PREFIX_VEX_0F70) },
8735     { REG_TABLE (REG_VEX_0F71) },
8736     { REG_TABLE (REG_VEX_0F72) },
8737     { REG_TABLE (REG_VEX_0F73) },
8738     { PREFIX_TABLE (PREFIX_VEX_0F74) },
8739     { PREFIX_TABLE (PREFIX_VEX_0F75) },
8740     { PREFIX_TABLE (PREFIX_VEX_0F76) },
8741     { PREFIX_TABLE (PREFIX_VEX_0F77) },
8742     /* 78 */
8743     { Bad_Opcode },
8744     { Bad_Opcode },
8745     { Bad_Opcode },
8746     { Bad_Opcode },
8747     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8748     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8749     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8750     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8751     /* 80 */
8752     { Bad_Opcode },
8753     { Bad_Opcode },
8754     { Bad_Opcode },
8755     { Bad_Opcode },
8756     { Bad_Opcode },
8757     { Bad_Opcode },
8758     { Bad_Opcode },
8759     { Bad_Opcode },
8760     /* 88 */
8761     { Bad_Opcode },
8762     { Bad_Opcode },
8763     { Bad_Opcode },
8764     { Bad_Opcode },
8765     { Bad_Opcode },
8766     { Bad_Opcode },
8767     { Bad_Opcode },
8768     { Bad_Opcode },
8769     /* 90 */
8770     { PREFIX_TABLE (PREFIX_VEX_0F90) },
8771     { PREFIX_TABLE (PREFIX_VEX_0F91) },
8772     { PREFIX_TABLE (PREFIX_VEX_0F92) },
8773     { PREFIX_TABLE (PREFIX_VEX_0F93) },
8774     { Bad_Opcode },
8775     { Bad_Opcode },
8776     { Bad_Opcode },
8777     { Bad_Opcode },
8778     /* 98 */
8779     { PREFIX_TABLE (PREFIX_VEX_0F98) },
8780     { PREFIX_TABLE (PREFIX_VEX_0F99) },
8781     { Bad_Opcode },
8782     { Bad_Opcode },
8783     { Bad_Opcode },
8784     { Bad_Opcode },
8785     { Bad_Opcode },
8786     { Bad_Opcode },
8787     /* a0 */
8788     { Bad_Opcode },
8789     { Bad_Opcode },
8790     { Bad_Opcode },
8791     { Bad_Opcode },
8792     { Bad_Opcode },
8793     { Bad_Opcode },
8794     { Bad_Opcode },
8795     { Bad_Opcode },
8796     /* a8 */
8797     { Bad_Opcode },
8798     { Bad_Opcode },
8799     { Bad_Opcode },
8800     { Bad_Opcode },
8801     { Bad_Opcode },
8802     { Bad_Opcode },
8803     { REG_TABLE (REG_VEX_0FAE) },
8804     { Bad_Opcode },
8805     /* b0 */
8806     { Bad_Opcode },
8807     { Bad_Opcode },
8808     { Bad_Opcode },
8809     { Bad_Opcode },
8810     { Bad_Opcode },
8811     { Bad_Opcode },
8812     { Bad_Opcode },
8813     { Bad_Opcode },
8814     /* b8 */
8815     { Bad_Opcode },
8816     { Bad_Opcode },
8817     { Bad_Opcode },
8818     { Bad_Opcode },
8819     { Bad_Opcode },
8820     { Bad_Opcode },
8821     { Bad_Opcode },
8822     { Bad_Opcode },
8823     /* c0 */
8824     { Bad_Opcode },
8825     { Bad_Opcode },
8826     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8827     { Bad_Opcode },
8828     { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8829     { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8830     { "vshufpX",        { XM, Vex, EXx, Ib } },
8831     { Bad_Opcode },
8832     /* c8 */
8833     { Bad_Opcode },
8834     { Bad_Opcode },
8835     { Bad_Opcode },
8836     { Bad_Opcode },
8837     { Bad_Opcode },
8838     { Bad_Opcode },
8839     { Bad_Opcode },
8840     { Bad_Opcode },
8841     /* d0 */
8842     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8843     { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8844     { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8845     { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8846     { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8847     { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8848     { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8849     { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8850     /* d8 */
8851     { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8852     { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8853     { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8854     { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8855     { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8856     { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8857     { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8858     { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8859     /* e0 */
8860     { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8861     { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8862     { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8863     { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8864     { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8865     { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8866     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8867     { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8868     /* e8 */
8869     { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8870     { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8871     { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8872     { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8873     { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8874     { PREFIX_TABLE (PREFIX_VEX_0FED) },
8875     { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8876     { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8877     /* f0 */
8878     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8879     { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8880     { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8881     { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8882     { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8883     { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8884     { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8885     { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8886     /* f8 */
8887     { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8888     { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8889     { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8890     { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8891     { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8892     { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8893     { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8894     { Bad_Opcode },
8895   },
8896   /* VEX_0F38 */
8897   {
8898     /* 00 */
8899     { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8900     { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8901     { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8902     { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8903     { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8904     { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8905     { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8906     { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8907     /* 08 */
8908     { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8909     { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8910     { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8911     { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8912     { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8913     { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8914     { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8915     { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8916     /* 10 */
8917     { Bad_Opcode },
8918     { Bad_Opcode },
8919     { Bad_Opcode },
8920     { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8921     { Bad_Opcode },
8922     { Bad_Opcode },
8923     { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8924     { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8925     /* 18 */
8926     { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8927     { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8928     { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8929     { Bad_Opcode },
8930     { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8931     { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8932     { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8933     { Bad_Opcode },
8934     /* 20 */
8935     { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8936     { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8937     { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8938     { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8939     { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8940     { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8941     { Bad_Opcode },
8942     { Bad_Opcode },
8943     /* 28 */
8944     { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8945     { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8946     { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8947     { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8948     { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8949     { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8950     { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8951     { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8952     /* 30 */
8953     { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8954     { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8955     { PREFIX_TABLE (PREFIX_VEX_0F3832) },
8956     { PREFIX_TABLE (PREFIX_VEX_0F3833) },
8957     { PREFIX_TABLE (PREFIX_VEX_0F3834) },
8958     { PREFIX_TABLE (PREFIX_VEX_0F3835) },
8959     { PREFIX_TABLE (PREFIX_VEX_0F3836) },
8960     { PREFIX_TABLE (PREFIX_VEX_0F3837) },
8961     /* 38 */
8962     { PREFIX_TABLE (PREFIX_VEX_0F3838) },
8963     { PREFIX_TABLE (PREFIX_VEX_0F3839) },
8964     { PREFIX_TABLE (PREFIX_VEX_0F383A) },
8965     { PREFIX_TABLE (PREFIX_VEX_0F383B) },
8966     { PREFIX_TABLE (PREFIX_VEX_0F383C) },
8967     { PREFIX_TABLE (PREFIX_VEX_0F383D) },
8968     { PREFIX_TABLE (PREFIX_VEX_0F383E) },
8969     { PREFIX_TABLE (PREFIX_VEX_0F383F) },
8970     /* 40 */
8971     { PREFIX_TABLE (PREFIX_VEX_0F3840) },
8972     { PREFIX_TABLE (PREFIX_VEX_0F3841) },
8973     { Bad_Opcode },
8974     { Bad_Opcode },
8975     { Bad_Opcode },
8976     { PREFIX_TABLE (PREFIX_VEX_0F3845) },
8977     { PREFIX_TABLE (PREFIX_VEX_0F3846) },
8978     { PREFIX_TABLE (PREFIX_VEX_0F3847) },
8979     /* 48 */
8980     { Bad_Opcode },
8981     { Bad_Opcode },
8982     { Bad_Opcode },
8983     { Bad_Opcode },
8984     { Bad_Opcode },
8985     { Bad_Opcode },
8986     { Bad_Opcode },
8987     { Bad_Opcode },
8988     /* 50 */
8989     { Bad_Opcode },
8990     { Bad_Opcode },
8991     { Bad_Opcode },
8992     { Bad_Opcode },
8993     { Bad_Opcode },
8994     { Bad_Opcode },
8995     { Bad_Opcode },
8996     { Bad_Opcode },
8997     /* 58 */
8998     { PREFIX_TABLE (PREFIX_VEX_0F3858) },
8999     { PREFIX_TABLE (PREFIX_VEX_0F3859) },
9000     { PREFIX_TABLE (PREFIX_VEX_0F385A) },
9001     { Bad_Opcode },
9002     { Bad_Opcode },
9003     { Bad_Opcode },
9004     { Bad_Opcode },
9005     { Bad_Opcode },
9006     /* 60 */
9007     { Bad_Opcode },
9008     { Bad_Opcode },
9009     { Bad_Opcode },
9010     { Bad_Opcode },
9011     { Bad_Opcode },
9012     { Bad_Opcode },
9013     { Bad_Opcode },
9014     { Bad_Opcode },
9015     /* 68 */
9016     { Bad_Opcode },
9017     { Bad_Opcode },
9018     { Bad_Opcode },
9019     { Bad_Opcode },
9020     { Bad_Opcode },
9021     { Bad_Opcode },
9022     { Bad_Opcode },
9023     { Bad_Opcode },
9024     /* 70 */
9025     { Bad_Opcode },
9026     { Bad_Opcode },
9027     { Bad_Opcode },
9028     { Bad_Opcode },
9029     { Bad_Opcode },
9030     { Bad_Opcode },
9031     { Bad_Opcode },
9032     { Bad_Opcode },
9033     /* 78 */
9034     { PREFIX_TABLE (PREFIX_VEX_0F3878) },
9035     { PREFIX_TABLE (PREFIX_VEX_0F3879) },
9036     { Bad_Opcode },
9037     { Bad_Opcode },
9038     { Bad_Opcode },
9039     { Bad_Opcode },
9040     { Bad_Opcode },
9041     { Bad_Opcode },
9042     /* 80 */
9043     { Bad_Opcode },
9044     { Bad_Opcode },
9045     { Bad_Opcode },
9046     { Bad_Opcode },
9047     { Bad_Opcode },
9048     { Bad_Opcode },
9049     { Bad_Opcode },
9050     { Bad_Opcode },
9051     /* 88 */
9052     { Bad_Opcode },
9053     { Bad_Opcode },
9054     { Bad_Opcode },
9055     { Bad_Opcode },
9056     { PREFIX_TABLE (PREFIX_VEX_0F388C) },
9057     { Bad_Opcode },
9058     { PREFIX_TABLE (PREFIX_VEX_0F388E) },
9059     { Bad_Opcode },
9060     /* 90 */
9061     { PREFIX_TABLE (PREFIX_VEX_0F3890) },
9062     { PREFIX_TABLE (PREFIX_VEX_0F3891) },
9063     { PREFIX_TABLE (PREFIX_VEX_0F3892) },
9064     { PREFIX_TABLE (PREFIX_VEX_0F3893) },
9065     { Bad_Opcode },
9066     { Bad_Opcode },
9067     { PREFIX_TABLE (PREFIX_VEX_0F3896) },
9068     { PREFIX_TABLE (PREFIX_VEX_0F3897) },
9069     /* 98 */
9070     { PREFIX_TABLE (PREFIX_VEX_0F3898) },
9071     { PREFIX_TABLE (PREFIX_VEX_0F3899) },
9072     { PREFIX_TABLE (PREFIX_VEX_0F389A) },
9073     { PREFIX_TABLE (PREFIX_VEX_0F389B) },
9074     { PREFIX_TABLE (PREFIX_VEX_0F389C) },
9075     { PREFIX_TABLE (PREFIX_VEX_0F389D) },
9076     { PREFIX_TABLE (PREFIX_VEX_0F389E) },
9077     { PREFIX_TABLE (PREFIX_VEX_0F389F) },
9078     /* a0 */
9079     { Bad_Opcode },
9080     { Bad_Opcode },
9081     { Bad_Opcode },
9082     { Bad_Opcode },
9083     { Bad_Opcode },
9084     { Bad_Opcode },
9085     { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
9086     { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
9087     /* a8 */
9088     { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
9089     { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
9090     { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
9091     { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
9092     { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
9093     { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
9094     { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
9095     { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
9096     /* b0 */
9097     { Bad_Opcode },
9098     { Bad_Opcode },
9099     { Bad_Opcode },
9100     { Bad_Opcode },
9101     { Bad_Opcode },
9102     { Bad_Opcode },
9103     { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
9104     { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
9105     /* b8 */
9106     { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
9107     { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
9108     { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
9109     { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
9110     { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
9111     { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
9112     { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
9113     { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
9114     /* c0 */
9115     { Bad_Opcode },
9116     { Bad_Opcode },
9117     { Bad_Opcode },
9118     { Bad_Opcode },
9119     { Bad_Opcode },
9120     { Bad_Opcode },
9121     { Bad_Opcode },
9122     { Bad_Opcode },
9123     /* c8 */
9124     { Bad_Opcode },
9125     { Bad_Opcode },
9126     { Bad_Opcode },
9127     { Bad_Opcode },
9128     { Bad_Opcode },
9129     { Bad_Opcode },
9130     { Bad_Opcode },
9131     { Bad_Opcode },
9132     /* d0 */
9133     { Bad_Opcode },
9134     { Bad_Opcode },
9135     { Bad_Opcode },
9136     { Bad_Opcode },
9137     { Bad_Opcode },
9138     { Bad_Opcode },
9139     { Bad_Opcode },
9140     { Bad_Opcode },
9141     /* d8 */
9142     { Bad_Opcode },
9143     { Bad_Opcode },
9144     { Bad_Opcode },
9145     { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
9146     { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
9147     { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
9148     { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
9149     { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
9150     /* e0 */
9151     { Bad_Opcode },
9152     { Bad_Opcode },
9153     { Bad_Opcode },
9154     { Bad_Opcode },
9155     { Bad_Opcode },
9156     { Bad_Opcode },
9157     { Bad_Opcode },
9158     { Bad_Opcode },
9159     /* e8 */
9160     { Bad_Opcode },
9161     { Bad_Opcode },
9162     { Bad_Opcode },
9163     { Bad_Opcode },
9164     { Bad_Opcode },
9165     { Bad_Opcode },
9166     { Bad_Opcode },
9167     { Bad_Opcode },
9168     /* f0 */
9169     { Bad_Opcode },
9170     { Bad_Opcode },
9171     { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
9172     { REG_TABLE (REG_VEX_0F38F3) },
9173     { Bad_Opcode },
9174     { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
9175     { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
9176     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
9177     /* f8 */
9178     { Bad_Opcode },
9179     { Bad_Opcode },
9180     { Bad_Opcode },
9181     { Bad_Opcode },
9182     { Bad_Opcode },
9183     { Bad_Opcode },
9184     { Bad_Opcode },
9185     { Bad_Opcode },
9186   },
9187   /* VEX_0F3A */
9188   {
9189     /* 00 */
9190     { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
9191     { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
9192     { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
9193     { Bad_Opcode },
9194     { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
9195     { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
9196     { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
9197     { Bad_Opcode },
9198     /* 08 */
9199     { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
9200     { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
9201     { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
9202     { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
9203     { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
9204     { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
9205     { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
9206     { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
9207     /* 10 */
9208     { Bad_Opcode },
9209     { Bad_Opcode },
9210     { Bad_Opcode },
9211     { Bad_Opcode },
9212     { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
9213     { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
9214     { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
9215     { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
9216     /* 18 */
9217     { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
9218     { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
9219     { Bad_Opcode },
9220     { Bad_Opcode },
9221     { Bad_Opcode },
9222     { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
9223     { Bad_Opcode },
9224     { Bad_Opcode },
9225     /* 20 */
9226     { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
9227     { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
9228     { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
9229     { Bad_Opcode },
9230     { Bad_Opcode },
9231     { Bad_Opcode },
9232     { Bad_Opcode },
9233     { Bad_Opcode },
9234     /* 28 */
9235     { Bad_Opcode },
9236     { Bad_Opcode },
9237     { Bad_Opcode },
9238     { Bad_Opcode },
9239     { Bad_Opcode },
9240     { Bad_Opcode },
9241     { Bad_Opcode },
9242     { Bad_Opcode },
9243     /* 30 */
9244     { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
9245     { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
9246     { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
9247     { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
9248     { Bad_Opcode },
9249     { Bad_Opcode },
9250     { Bad_Opcode },
9251     { Bad_Opcode },
9252     /* 38 */
9253     { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
9254     { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
9255     { Bad_Opcode },
9256     { Bad_Opcode },
9257     { Bad_Opcode },
9258     { Bad_Opcode },
9259     { Bad_Opcode },
9260     { Bad_Opcode },
9261     /* 40 */
9262     { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
9263     { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
9264     { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
9265     { Bad_Opcode },
9266     { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
9267     { Bad_Opcode },
9268     { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
9269     { Bad_Opcode },
9270     /* 48 */
9271     { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
9272     { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
9273     { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
9274     { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
9275     { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
9276     { Bad_Opcode },
9277     { Bad_Opcode },
9278     { Bad_Opcode },
9279     /* 50 */
9280     { Bad_Opcode },
9281     { Bad_Opcode },
9282     { Bad_Opcode },
9283     { Bad_Opcode },
9284     { Bad_Opcode },
9285     { Bad_Opcode },
9286     { Bad_Opcode },
9287     { Bad_Opcode },
9288     /* 58 */
9289     { Bad_Opcode },
9290     { Bad_Opcode },
9291     { Bad_Opcode },
9292     { Bad_Opcode },
9293     { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9294     { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9295     { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9296     { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9297     /* 60 */
9298     { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9299     { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9300     { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9301     { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9302     { Bad_Opcode },
9303     { Bad_Opcode },
9304     { Bad_Opcode },
9305     { Bad_Opcode },
9306     /* 68 */
9307     { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9308     { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9309     { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9310     { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9311     { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9312     { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9313     { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9314     { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9315     /* 70 */
9316     { Bad_Opcode },
9317     { Bad_Opcode },
9318     { Bad_Opcode },
9319     { Bad_Opcode },
9320     { Bad_Opcode },
9321     { Bad_Opcode },
9322     { Bad_Opcode },
9323     { Bad_Opcode },
9324     /* 78 */
9325     { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9326     { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9327     { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9328     { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9329     { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9330     { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9331     { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9332     { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9333     /* 80 */
9334     { Bad_Opcode },
9335     { Bad_Opcode },
9336     { Bad_Opcode },
9337     { Bad_Opcode },
9338     { Bad_Opcode },
9339     { Bad_Opcode },
9340     { Bad_Opcode },
9341     { Bad_Opcode },
9342     /* 88 */
9343     { Bad_Opcode },
9344     { Bad_Opcode },
9345     { Bad_Opcode },
9346     { Bad_Opcode },
9347     { Bad_Opcode },
9348     { Bad_Opcode },
9349     { Bad_Opcode },
9350     { Bad_Opcode },
9351     /* 90 */
9352     { Bad_Opcode },
9353     { Bad_Opcode },
9354     { Bad_Opcode },
9355     { Bad_Opcode },
9356     { Bad_Opcode },
9357     { Bad_Opcode },
9358     { Bad_Opcode },
9359     { Bad_Opcode },
9360     /* 98 */
9361     { Bad_Opcode },
9362     { Bad_Opcode },
9363     { Bad_Opcode },
9364     { Bad_Opcode },
9365     { Bad_Opcode },
9366     { Bad_Opcode },
9367     { Bad_Opcode },
9368     { Bad_Opcode },
9369     /* a0 */
9370     { Bad_Opcode },
9371     { Bad_Opcode },
9372     { Bad_Opcode },
9373     { Bad_Opcode },
9374     { Bad_Opcode },
9375     { Bad_Opcode },
9376     { Bad_Opcode },
9377     { Bad_Opcode },
9378     /* a8 */
9379     { Bad_Opcode },
9380     { Bad_Opcode },
9381     { Bad_Opcode },
9382     { Bad_Opcode },
9383     { Bad_Opcode },
9384     { Bad_Opcode },
9385     { Bad_Opcode },
9386     { Bad_Opcode },
9387     /* b0 */
9388     { Bad_Opcode },
9389     { Bad_Opcode },
9390     { Bad_Opcode },
9391     { Bad_Opcode },
9392     { Bad_Opcode },
9393     { Bad_Opcode },
9394     { Bad_Opcode },
9395     { Bad_Opcode },
9396     /* b8 */
9397     { Bad_Opcode },
9398     { Bad_Opcode },
9399     { Bad_Opcode },
9400     { Bad_Opcode },
9401     { Bad_Opcode },
9402     { Bad_Opcode },
9403     { Bad_Opcode },
9404     { Bad_Opcode },
9405     /* c0 */
9406     { Bad_Opcode },
9407     { Bad_Opcode },
9408     { Bad_Opcode },
9409     { Bad_Opcode },
9410     { Bad_Opcode },
9411     { Bad_Opcode },
9412     { Bad_Opcode },
9413     { Bad_Opcode },
9414     /* c8 */
9415     { Bad_Opcode },
9416     { Bad_Opcode },
9417     { Bad_Opcode },
9418     { Bad_Opcode },
9419     { Bad_Opcode },
9420     { Bad_Opcode },
9421     { Bad_Opcode },
9422     { Bad_Opcode },
9423     /* d0 */
9424     { Bad_Opcode },
9425     { Bad_Opcode },
9426     { Bad_Opcode },
9427     { Bad_Opcode },
9428     { Bad_Opcode },
9429     { Bad_Opcode },
9430     { Bad_Opcode },
9431     { Bad_Opcode },
9432     /* d8 */
9433     { Bad_Opcode },
9434     { Bad_Opcode },
9435     { Bad_Opcode },
9436     { Bad_Opcode },
9437     { Bad_Opcode },
9438     { Bad_Opcode },
9439     { Bad_Opcode },
9440     { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9441     /* e0 */
9442     { Bad_Opcode },
9443     { Bad_Opcode },
9444     { Bad_Opcode },
9445     { Bad_Opcode },
9446     { Bad_Opcode },
9447     { Bad_Opcode },
9448     { Bad_Opcode },
9449     { Bad_Opcode },
9450     /* e8 */
9451     { Bad_Opcode },
9452     { Bad_Opcode },
9453     { Bad_Opcode },
9454     { Bad_Opcode },
9455     { Bad_Opcode },
9456     { Bad_Opcode },
9457     { Bad_Opcode },
9458     { Bad_Opcode },
9459     /* f0 */
9460     { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9461     { Bad_Opcode },
9462     { Bad_Opcode },
9463     { Bad_Opcode },
9464     { Bad_Opcode },
9465     { Bad_Opcode },
9466     { Bad_Opcode },
9467     { Bad_Opcode },
9468     /* f8 */
9469     { Bad_Opcode },
9470     { Bad_Opcode },
9471     { Bad_Opcode },
9472     { Bad_Opcode },
9473     { Bad_Opcode },
9474     { Bad_Opcode },
9475     { Bad_Opcode },
9476     { Bad_Opcode },
9477   },
9478 };
9479
9480 #define NEED_OPCODE_TABLE
9481 #include "i386-dis-evex.h"
9482 #undef NEED_OPCODE_TABLE
9483 static const struct dis386 vex_len_table[][2] = {
9484   /* VEX_LEN_0F10_P_1 */
9485   {
9486     { VEX_W_TABLE (VEX_W_0F10_P_1) },
9487     { VEX_W_TABLE (VEX_W_0F10_P_1) },
9488   },
9489
9490   /* VEX_LEN_0F10_P_3 */
9491   {
9492     { VEX_W_TABLE (VEX_W_0F10_P_3) },
9493     { VEX_W_TABLE (VEX_W_0F10_P_3) },
9494   },
9495
9496   /* VEX_LEN_0F11_P_1 */
9497   {
9498     { VEX_W_TABLE (VEX_W_0F11_P_1) },
9499     { VEX_W_TABLE (VEX_W_0F11_P_1) },
9500   },
9501
9502   /* VEX_LEN_0F11_P_3 */
9503   {
9504     { VEX_W_TABLE (VEX_W_0F11_P_3) },
9505     { VEX_W_TABLE (VEX_W_0F11_P_3) },
9506   },
9507
9508   /* VEX_LEN_0F12_P_0_M_0 */
9509   {
9510     { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) },
9511   },
9512
9513   /* VEX_LEN_0F12_P_0_M_1 */
9514   {
9515     { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) },
9516   },
9517
9518   /* VEX_LEN_0F12_P_2 */
9519   {
9520     { VEX_W_TABLE (VEX_W_0F12_P_2) },
9521   },
9522
9523   /* VEX_LEN_0F13_M_0 */
9524   {
9525     { VEX_W_TABLE (VEX_W_0F13_M_0) },
9526   },
9527
9528   /* VEX_LEN_0F16_P_0_M_0 */
9529   {
9530     { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) },
9531   },
9532
9533   /* VEX_LEN_0F16_P_0_M_1 */
9534   {
9535     { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) },
9536   },
9537
9538   /* VEX_LEN_0F16_P_2 */
9539   {
9540     { VEX_W_TABLE (VEX_W_0F16_P_2) },
9541   },
9542
9543   /* VEX_LEN_0F17_M_0 */
9544   {
9545     { VEX_W_TABLE (VEX_W_0F17_M_0) },
9546   },
9547
9548   /* VEX_LEN_0F2A_P_1 */
9549   {
9550     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev } },
9551     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev } },
9552   },
9553
9554   /* VEX_LEN_0F2A_P_3 */
9555   {
9556     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev } },
9557     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev } },
9558   },
9559
9560   /* VEX_LEN_0F2C_P_1 */
9561   {
9562     { "vcvttss2siY",    { Gv, EXdScalar } },
9563     { "vcvttss2siY",    { Gv, EXdScalar } },
9564   },
9565
9566   /* VEX_LEN_0F2C_P_3 */
9567   {
9568     { "vcvttsd2siY",    { Gv, EXqScalar } },
9569     { "vcvttsd2siY",    { Gv, EXqScalar } },
9570   },
9571
9572   /* VEX_LEN_0F2D_P_1 */
9573   {
9574     { "vcvtss2siY",     { Gv, EXdScalar } },
9575     { "vcvtss2siY",     { Gv, EXdScalar } },
9576   },
9577
9578   /* VEX_LEN_0F2D_P_3 */
9579   {
9580     { "vcvtsd2siY",     { Gv, EXqScalar } },
9581     { "vcvtsd2siY",     { Gv, EXqScalar } },
9582   },
9583
9584   /* VEX_LEN_0F2E_P_0 */
9585   {
9586     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9587     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9588   },
9589
9590   /* VEX_LEN_0F2E_P_2 */
9591   {
9592     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9593     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9594   },
9595
9596   /* VEX_LEN_0F2F_P_0 */
9597   {
9598     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9599     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9600   },
9601
9602   /* VEX_LEN_0F2F_P_2 */
9603   {
9604     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9605     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9606   },
9607
9608   /* VEX_LEN_0F41_P_0 */
9609   {
9610     { Bad_Opcode },
9611     { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9612   },
9613   /* VEX_LEN_0F41_P_2 */
9614   {
9615     { Bad_Opcode },
9616     { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9617   },
9618   /* VEX_LEN_0F42_P_0 */
9619   {
9620     { Bad_Opcode },
9621     { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9622   },
9623   /* VEX_LEN_0F42_P_2 */
9624   {
9625     { Bad_Opcode },
9626     { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9627   },
9628   /* VEX_LEN_0F44_P_0 */
9629   {
9630     { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9631   },
9632   /* VEX_LEN_0F44_P_2 */
9633   {
9634     { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9635   },
9636   /* VEX_LEN_0F45_P_0 */
9637   {
9638     { Bad_Opcode },
9639     { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9640   },
9641   /* VEX_LEN_0F45_P_2 */
9642   {
9643     { Bad_Opcode },
9644     { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9645   },
9646   /* VEX_LEN_0F46_P_0 */
9647   {
9648     { Bad_Opcode },
9649     { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9650   },
9651   /* VEX_LEN_0F46_P_2 */
9652   {
9653     { Bad_Opcode },
9654     { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9655   },
9656   /* VEX_LEN_0F47_P_0 */
9657   {
9658     { Bad_Opcode },
9659     { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9660   },
9661   /* VEX_LEN_0F47_P_2 */
9662   {
9663     { Bad_Opcode },
9664     { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9665   },
9666   /* VEX_LEN_0F4A_P_0 */
9667   {
9668     { Bad_Opcode },
9669     { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9670   },
9671   /* VEX_LEN_0F4A_P_2 */
9672   {
9673     { Bad_Opcode },
9674     { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9675   },
9676   /* VEX_LEN_0F4B_P_0 */
9677   {
9678     { Bad_Opcode },
9679     { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9680   },
9681   /* VEX_LEN_0F4B_P_2 */
9682   {
9683     { Bad_Opcode },
9684     { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9685   },
9686
9687   /* VEX_LEN_0F51_P_1 */
9688   {
9689     { VEX_W_TABLE (VEX_W_0F51_P_1) },
9690     { VEX_W_TABLE (VEX_W_0F51_P_1) },
9691   },
9692
9693   /* VEX_LEN_0F51_P_3 */
9694   {
9695     { VEX_W_TABLE (VEX_W_0F51_P_3) },
9696     { VEX_W_TABLE (VEX_W_0F51_P_3) },
9697   },
9698
9699   /* VEX_LEN_0F52_P_1 */
9700   {
9701     { VEX_W_TABLE (VEX_W_0F52_P_1) },
9702     { VEX_W_TABLE (VEX_W_0F52_P_1) },
9703   },
9704
9705   /* VEX_LEN_0F53_P_1 */
9706   {
9707     { VEX_W_TABLE (VEX_W_0F53_P_1) },
9708     { VEX_W_TABLE (VEX_W_0F53_P_1) },
9709   },
9710
9711   /* VEX_LEN_0F58_P_1 */
9712   {
9713     { VEX_W_TABLE (VEX_W_0F58_P_1) },
9714     { VEX_W_TABLE (VEX_W_0F58_P_1) },
9715   },
9716
9717   /* VEX_LEN_0F58_P_3 */
9718   {
9719     { VEX_W_TABLE (VEX_W_0F58_P_3) },
9720     { VEX_W_TABLE (VEX_W_0F58_P_3) },
9721   },
9722
9723   /* VEX_LEN_0F59_P_1 */
9724   {
9725     { VEX_W_TABLE (VEX_W_0F59_P_1) },
9726     { VEX_W_TABLE (VEX_W_0F59_P_1) },
9727   },
9728
9729   /* VEX_LEN_0F59_P_3 */
9730   {
9731     { VEX_W_TABLE (VEX_W_0F59_P_3) },
9732     { VEX_W_TABLE (VEX_W_0F59_P_3) },
9733   },
9734
9735   /* VEX_LEN_0F5A_P_1 */
9736   {
9737     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9738     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9739   },
9740
9741   /* VEX_LEN_0F5A_P_3 */
9742   {
9743     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9744     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9745   },
9746
9747   /* VEX_LEN_0F5C_P_1 */
9748   {
9749     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9750     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9751   },
9752
9753   /* VEX_LEN_0F5C_P_3 */
9754   {
9755     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9756     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9757   },
9758
9759   /* VEX_LEN_0F5D_P_1 */
9760   {
9761     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9762     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9763   },
9764
9765   /* VEX_LEN_0F5D_P_3 */
9766   {
9767     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9768     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9769   },
9770
9771   /* VEX_LEN_0F5E_P_1 */
9772   {
9773     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9774     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9775   },
9776
9777   /* VEX_LEN_0F5E_P_3 */
9778   {
9779     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9780     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9781   },
9782
9783   /* VEX_LEN_0F5F_P_1 */
9784   {
9785     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9786     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9787   },
9788
9789   /* VEX_LEN_0F5F_P_3 */
9790   {
9791     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9792     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9793   },
9794
9795   /* VEX_LEN_0F6E_P_2 */
9796   {
9797     { "vmovK",          { XMScalar, Edq } },
9798     { "vmovK",          { XMScalar, Edq } },
9799   },
9800
9801   /* VEX_LEN_0F7E_P_1 */
9802   {
9803     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9804     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9805   },
9806
9807   /* VEX_LEN_0F7E_P_2 */
9808   {
9809     { "vmovK",          { Edq, XMScalar } },
9810     { "vmovK",          { Edq, XMScalar } },
9811   },
9812
9813   /* VEX_LEN_0F90_P_0 */
9814   {
9815     { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9816   },
9817
9818   /* VEX_LEN_0F90_P_2 */
9819   {
9820     { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9821   },
9822
9823   /* VEX_LEN_0F91_P_0 */
9824   {
9825     { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9826   },
9827
9828   /* VEX_LEN_0F91_P_2 */
9829   {
9830     { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
9831   },
9832
9833   /* VEX_LEN_0F92_P_0 */
9834   {
9835     { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9836   },
9837
9838   /* VEX_LEN_0F92_P_2 */
9839   {
9840     { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
9841   },
9842
9843   /* VEX_LEN_0F92_P_3 */
9844   {
9845     { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0) },
9846   },
9847
9848   /* VEX_LEN_0F93_P_0 */
9849   {
9850     { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9851   },
9852
9853   /* VEX_LEN_0F93_P_2 */
9854   {
9855     { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
9856   },
9857
9858   /* VEX_LEN_0F93_P_3 */
9859   {
9860     { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0) },
9861   },
9862
9863   /* VEX_LEN_0F98_P_0 */
9864   {
9865     { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9866   },
9867
9868   /* VEX_LEN_0F98_P_2 */
9869   {
9870     { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
9871   },
9872
9873   /* VEX_LEN_0F99_P_0 */
9874   {
9875     { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
9876   },
9877
9878   /* VEX_LEN_0F99_P_2 */
9879   {
9880     { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
9881   },
9882
9883   /* VEX_LEN_0FAE_R_2_M_0 */
9884   {
9885     { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) },
9886   },
9887
9888   /* VEX_LEN_0FAE_R_3_M_0 */
9889   {
9890     { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) },
9891   },
9892
9893   /* VEX_LEN_0FC2_P_1 */
9894   {
9895     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9896     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9897   },
9898
9899   /* VEX_LEN_0FC2_P_3 */
9900   {
9901     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9902     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9903   },
9904
9905   /* VEX_LEN_0FC4_P_2 */
9906   {
9907     { VEX_W_TABLE (VEX_W_0FC4_P_2) },
9908   },
9909
9910   /* VEX_LEN_0FC5_P_2 */
9911   {
9912     { VEX_W_TABLE (VEX_W_0FC5_P_2) },
9913   },
9914
9915   /* VEX_LEN_0FD6_P_2 */
9916   {
9917     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9918     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9919   },
9920
9921   /* VEX_LEN_0FF7_P_2 */
9922   {
9923     { VEX_W_TABLE (VEX_W_0FF7_P_2) },
9924   },
9925
9926   /* VEX_LEN_0F3816_P_2 */
9927   {
9928     { Bad_Opcode },
9929     { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9930   },
9931
9932   /* VEX_LEN_0F3819_P_2 */
9933   {
9934     { Bad_Opcode },
9935     { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9936   },
9937
9938   /* VEX_LEN_0F381A_P_2_M_0 */
9939   {
9940     { Bad_Opcode },
9941     { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9942   },
9943
9944   /* VEX_LEN_0F3836_P_2 */
9945   {
9946     { Bad_Opcode },
9947     { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9948   },
9949
9950   /* VEX_LEN_0F3841_P_2 */
9951   {
9952     { VEX_W_TABLE (VEX_W_0F3841_P_2) },
9953   },
9954
9955   /* VEX_LEN_0F385A_P_2_M_0 */
9956   {
9957     { Bad_Opcode },
9958     { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
9959   },
9960
9961   /* VEX_LEN_0F38DB_P_2 */
9962   {
9963     { VEX_W_TABLE (VEX_W_0F38DB_P_2) },
9964   },
9965
9966   /* VEX_LEN_0F38DC_P_2 */
9967   {
9968     { VEX_W_TABLE (VEX_W_0F38DC_P_2) },
9969   },
9970
9971   /* VEX_LEN_0F38DD_P_2 */
9972   {
9973     { VEX_W_TABLE (VEX_W_0F38DD_P_2) },
9974   },
9975
9976   /* VEX_LEN_0F38DE_P_2 */
9977   {
9978     { VEX_W_TABLE (VEX_W_0F38DE_P_2) },
9979   },
9980
9981   /* VEX_LEN_0F38DF_P_2 */
9982   {
9983     { VEX_W_TABLE (VEX_W_0F38DF_P_2) },
9984   },
9985
9986   /* VEX_LEN_0F38F2_P_0 */
9987   {
9988     { "andnS",          { Gdq, VexGdq, Edq } },
9989   },
9990
9991   /* VEX_LEN_0F38F3_R_1_P_0 */
9992   {
9993     { "blsrS",          { VexGdq, Edq } },
9994   },
9995
9996   /* VEX_LEN_0F38F3_R_2_P_0 */
9997   {
9998     { "blsmskS",        { VexGdq, Edq } },
9999   },
10000
10001   /* VEX_LEN_0F38F3_R_3_P_0 */
10002   {
10003     { "blsiS",          { VexGdq, Edq } },
10004   },
10005
10006   /* VEX_LEN_0F38F5_P_0 */
10007   {
10008     { "bzhiS",          { Gdq, Edq, VexGdq } },
10009   },
10010
10011   /* VEX_LEN_0F38F5_P_1 */
10012   {
10013     { "pextS",          { Gdq, VexGdq, Edq } },
10014   },
10015
10016   /* VEX_LEN_0F38F5_P_3 */
10017   {
10018     { "pdepS",          { Gdq, VexGdq, Edq } },
10019   },
10020
10021   /* VEX_LEN_0F38F6_P_3 */
10022   {
10023     { "mulxS",          { Gdq, VexGdq, Edq } },
10024   },
10025
10026   /* VEX_LEN_0F38F7_P_0 */
10027   {
10028     { "bextrS",         { Gdq, Edq, VexGdq } },
10029   },
10030
10031   /* VEX_LEN_0F38F7_P_1 */
10032   {
10033     { "sarxS",          { Gdq, Edq, VexGdq } },
10034   },
10035
10036   /* VEX_LEN_0F38F7_P_2 */
10037   {
10038     { "shlxS",          { Gdq, Edq, VexGdq } },
10039   },
10040
10041   /* VEX_LEN_0F38F7_P_3 */
10042   {
10043     { "shrxS",          { Gdq, Edq, VexGdq } },
10044   },
10045
10046   /* VEX_LEN_0F3A00_P_2 */
10047   {
10048     { Bad_Opcode },
10049     { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
10050   },
10051
10052   /* VEX_LEN_0F3A01_P_2 */
10053   {
10054     { Bad_Opcode },
10055     { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
10056   },
10057
10058   /* VEX_LEN_0F3A06_P_2 */
10059   {
10060     { Bad_Opcode },
10061     { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
10062   },
10063
10064   /* VEX_LEN_0F3A0A_P_2 */
10065   {
10066     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
10067     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
10068   },
10069
10070   /* VEX_LEN_0F3A0B_P_2 */
10071   {
10072     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
10073     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
10074   },
10075
10076   /* VEX_LEN_0F3A14_P_2 */
10077   {
10078     { VEX_W_TABLE (VEX_W_0F3A14_P_2) },
10079   },
10080
10081   /* VEX_LEN_0F3A15_P_2 */
10082   {
10083     { VEX_W_TABLE (VEX_W_0F3A15_P_2) },
10084   },
10085
10086   /* VEX_LEN_0F3A16_P_2  */
10087   {
10088     { "vpextrK",        { Edq, XM, Ib } },
10089   },
10090
10091   /* VEX_LEN_0F3A17_P_2 */
10092   {
10093     { "vextractps",     { Edqd, XM, Ib } },
10094   },
10095
10096   /* VEX_LEN_0F3A18_P_2 */
10097   {
10098     { Bad_Opcode },
10099     { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
10100   },
10101
10102   /* VEX_LEN_0F3A19_P_2 */
10103   {
10104     { Bad_Opcode },
10105     { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
10106   },
10107
10108   /* VEX_LEN_0F3A20_P_2 */
10109   {
10110     { VEX_W_TABLE (VEX_W_0F3A20_P_2) },
10111   },
10112
10113   /* VEX_LEN_0F3A21_P_2 */
10114   {
10115     { VEX_W_TABLE (VEX_W_0F3A21_P_2) },
10116   },
10117
10118   /* VEX_LEN_0F3A22_P_2 */
10119   {
10120     { "vpinsrK",        { XM, Vex128, Edq, Ib } },
10121   },
10122
10123   /* VEX_LEN_0F3A30_P_2 */
10124   {
10125     { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
10126   },
10127
10128   /* VEX_LEN_0F3A31_P_2 */
10129   {
10130     { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
10131   },
10132
10133   /* VEX_LEN_0F3A32_P_2 */
10134   {
10135     { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
10136   },
10137
10138   /* VEX_LEN_0F3A33_P_2 */
10139   {
10140     { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
10141   },
10142
10143   /* VEX_LEN_0F3A38_P_2 */
10144   {
10145     { Bad_Opcode },
10146     { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
10147   },
10148
10149   /* VEX_LEN_0F3A39_P_2 */
10150   {
10151     { Bad_Opcode },
10152     { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
10153   },
10154
10155   /* VEX_LEN_0F3A41_P_2 */
10156   {
10157     { VEX_W_TABLE (VEX_W_0F3A41_P_2) },
10158   },
10159
10160   /* VEX_LEN_0F3A44_P_2 */
10161   {
10162     { VEX_W_TABLE (VEX_W_0F3A44_P_2) },
10163   },
10164
10165   /* VEX_LEN_0F3A46_P_2 */
10166   {
10167     { Bad_Opcode },
10168     { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
10169   },
10170
10171   /* VEX_LEN_0F3A60_P_2 */
10172   {
10173     { VEX_W_TABLE (VEX_W_0F3A60_P_2) },
10174   },
10175
10176   /* VEX_LEN_0F3A61_P_2 */
10177   {
10178     { VEX_W_TABLE (VEX_W_0F3A61_P_2) },
10179   },
10180
10181   /* VEX_LEN_0F3A62_P_2 */
10182   {
10183     { VEX_W_TABLE (VEX_W_0F3A62_P_2) },
10184   },
10185
10186   /* VEX_LEN_0F3A63_P_2 */
10187   {
10188     { VEX_W_TABLE (VEX_W_0F3A63_P_2) },
10189   },
10190
10191   /* VEX_LEN_0F3A6A_P_2 */
10192   {
10193     { "vfmaddss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
10194   },
10195
10196   /* VEX_LEN_0F3A6B_P_2 */
10197   {
10198     { "vfmaddsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
10199   },
10200
10201   /* VEX_LEN_0F3A6E_P_2 */
10202   {
10203     { "vfmsubss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
10204   },
10205
10206   /* VEX_LEN_0F3A6F_P_2 */
10207   {
10208     { "vfmsubsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
10209   },
10210
10211   /* VEX_LEN_0F3A7A_P_2 */
10212   {
10213     { "vfnmaddss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
10214   },
10215
10216   /* VEX_LEN_0F3A7B_P_2 */
10217   {
10218     { "vfnmaddsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
10219   },
10220
10221   /* VEX_LEN_0F3A7E_P_2 */
10222   {
10223     { "vfnmsubss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
10224   },
10225
10226   /* VEX_LEN_0F3A7F_P_2 */
10227   {
10228     { "vfnmsubsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
10229   },
10230
10231   /* VEX_LEN_0F3ADF_P_2 */
10232   {
10233     { VEX_W_TABLE (VEX_W_0F3ADF_P_2) },
10234   },
10235
10236   /* VEX_LEN_0F3AF0_P_3 */
10237   {
10238     { "rorxS",          { Gdq, Edq, Ib } },
10239   },
10240
10241   /* VEX_LEN_0FXOP_08_CC */
10242   {
10243      { "vpcomb",        { XM, Vex128, EXx, Ib } },
10244   },
10245
10246   /* VEX_LEN_0FXOP_08_CD */
10247   {
10248      { "vpcomw",        { XM, Vex128, EXx, Ib } },
10249   },
10250
10251   /* VEX_LEN_0FXOP_08_CE */
10252   {
10253      { "vpcomd",        { XM, Vex128, EXx, Ib } },
10254   },
10255
10256   /* VEX_LEN_0FXOP_08_CF */
10257   {
10258      { "vpcomq",        { XM, Vex128, EXx, Ib } },
10259   },
10260
10261   /* VEX_LEN_0FXOP_08_EC */
10262   {
10263      { "vpcomub",       { XM, Vex128, EXx, Ib } },
10264   },
10265
10266   /* VEX_LEN_0FXOP_08_ED */
10267   {
10268      { "vpcomuw",       { XM, Vex128, EXx, Ib } },
10269   },
10270
10271   /* VEX_LEN_0FXOP_08_EE */
10272   {
10273      { "vpcomud",       { XM, Vex128, EXx, Ib } },
10274   },
10275
10276   /* VEX_LEN_0FXOP_08_EF */
10277   {
10278      { "vpcomuq",       { XM, Vex128, EXx, Ib } },
10279   },
10280
10281   /* VEX_LEN_0FXOP_09_80 */
10282   {
10283     { "vfrczps",        { XM, EXxmm } },
10284     { "vfrczps",        { XM, EXymmq } },
10285   },
10286
10287   /* VEX_LEN_0FXOP_09_81 */
10288   {
10289     { "vfrczpd",        { XM, EXxmm } },
10290     { "vfrczpd",        { XM, EXymmq } },
10291   },
10292 };
10293
10294 static const struct dis386 vex_w_table[][2] = {
10295   {
10296     /* VEX_W_0F10_P_0 */
10297     { "vmovups",        { XM, EXx } },
10298   },
10299   {
10300     /* VEX_W_0F10_P_1 */
10301     { "vmovss",         { XMVexScalar, VexScalar, EXdScalar } },
10302   },
10303   {
10304     /* VEX_W_0F10_P_2 */
10305     { "vmovupd",        { XM, EXx } },
10306   },
10307   {
10308     /* VEX_W_0F10_P_3 */
10309     { "vmovsd",         { XMVexScalar, VexScalar, EXqScalar } },
10310   },
10311   {
10312     /* VEX_W_0F11_P_0 */
10313     { "vmovups",        { EXxS, XM } },
10314   },
10315   {
10316     /* VEX_W_0F11_P_1 */
10317     { "vmovss",         { EXdVexScalarS, VexScalar, XMScalar } },
10318   },
10319   {
10320     /* VEX_W_0F11_P_2 */
10321     { "vmovupd",        { EXxS, XM } },
10322   },
10323   {
10324     /* VEX_W_0F11_P_3 */
10325     { "vmovsd",         { EXqVexScalarS, VexScalar, XMScalar } },
10326   },
10327   {
10328     /* VEX_W_0F12_P_0_M_0 */
10329     { "vmovlps",        { XM, Vex128, EXq } },
10330   },
10331   {
10332     /* VEX_W_0F12_P_0_M_1 */
10333     { "vmovhlps",       { XM, Vex128, EXq } },
10334   },
10335   {
10336     /* VEX_W_0F12_P_1 */
10337     { "vmovsldup",      { XM, EXx } },
10338   },
10339   {
10340     /* VEX_W_0F12_P_2 */
10341     { "vmovlpd",        { XM, Vex128, EXq } },
10342   },
10343   {
10344     /* VEX_W_0F12_P_3 */
10345     { "vmovddup",       { XM, EXymmq } },
10346   },
10347   {
10348     /* VEX_W_0F13_M_0 */
10349     { "vmovlpX",        { EXq, XM } },
10350   },
10351   {
10352     /* VEX_W_0F14 */
10353     { "vunpcklpX",      { XM, Vex, EXx } },
10354   },
10355   {
10356     /* VEX_W_0F15 */
10357     { "vunpckhpX",      { XM, Vex, EXx } },
10358   },
10359   {
10360     /* VEX_W_0F16_P_0_M_0 */
10361     { "vmovhps",        { XM, Vex128, EXq } },
10362   },
10363   {
10364     /* VEX_W_0F16_P_0_M_1 */
10365     { "vmovlhps",       { XM, Vex128, EXq } },
10366   },
10367   {
10368     /* VEX_W_0F16_P_1 */
10369     { "vmovshdup",      { XM, EXx } },
10370   },
10371   {
10372     /* VEX_W_0F16_P_2 */
10373     { "vmovhpd",        { XM, Vex128, EXq } },
10374   },
10375   {
10376     /* VEX_W_0F17_M_0 */
10377     { "vmovhpX",        { EXq, XM } },
10378   },
10379   {
10380     /* VEX_W_0F28 */
10381     { "vmovapX",        { XM, EXx } },
10382   },
10383   {
10384     /* VEX_W_0F29 */
10385     { "vmovapX",        { EXxS, XM } },
10386   },
10387   {
10388     /* VEX_W_0F2B_M_0 */
10389     { "vmovntpX",       { Mx, XM } },
10390   },
10391   {
10392     /* VEX_W_0F2E_P_0 */
10393     { "vucomiss",       { XMScalar, EXdScalar } },
10394   },
10395   {
10396     /* VEX_W_0F2E_P_2 */
10397     { "vucomisd",       { XMScalar, EXqScalar } },
10398   },
10399   {
10400     /* VEX_W_0F2F_P_0 */
10401     { "vcomiss",        { XMScalar, EXdScalar } },
10402   },
10403   {
10404     /* VEX_W_0F2F_P_2 */
10405     { "vcomisd",        { XMScalar, EXqScalar } },
10406   },
10407   {
10408     /* VEX_W_0F41_P_0_LEN_1 */
10409     { "kandw",          { MaskG, MaskVex, MaskR } },
10410     { "kandq",          { MaskG, MaskVex, MaskR } },
10411   },
10412   {
10413     /* VEX_W_0F41_P_2_LEN_1 */
10414     { "kandb",          { MaskG, MaskVex, MaskR } },
10415     { "kandd",          { MaskG, MaskVex, MaskR } },
10416   },
10417   {
10418     /* VEX_W_0F42_P_0_LEN_1 */
10419     { "kandnw",         { MaskG, MaskVex, MaskR } },
10420     { "kandnq",         { MaskG, MaskVex, MaskR } },
10421   },
10422   {
10423     /* VEX_W_0F42_P_2_LEN_1 */
10424     { "kandnb",         { MaskG, MaskVex, MaskR } },
10425     { "kandnd",         { MaskG, MaskVex, MaskR } },
10426   },
10427   {
10428     /* VEX_W_0F44_P_0_LEN_0 */
10429     { "knotw",          { MaskG, MaskR } },
10430     { "knotq",          { MaskG, MaskR } },
10431   },
10432   {
10433     /* VEX_W_0F44_P_2_LEN_0 */
10434     { "knotb",          { MaskG, MaskR } },
10435     { "knotd",          { MaskG, MaskR } },
10436   },
10437   {
10438     /* VEX_W_0F45_P_0_LEN_1 */
10439     { "korw",           { MaskG, MaskVex, MaskR } },
10440     { "korq",           { MaskG, MaskVex, MaskR } },
10441   },
10442   {
10443     /* VEX_W_0F45_P_2_LEN_1 */
10444     { "korb",           { MaskG, MaskVex, MaskR } },
10445     { "kord",           { MaskG, MaskVex, MaskR } },
10446   },
10447   {
10448     /* VEX_W_0F46_P_0_LEN_1 */
10449     { "kxnorw",         { MaskG, MaskVex, MaskR } },
10450     { "kxnorq",         { MaskG, MaskVex, MaskR } },
10451   },
10452   {
10453     /* VEX_W_0F46_P_2_LEN_1 */
10454     { "kxnorb",         { MaskG, MaskVex, MaskR } },
10455     { "kxnord",         { MaskG, MaskVex, MaskR } },
10456   },
10457   {
10458     /* VEX_W_0F47_P_0_LEN_1 */
10459     { "kxorw",          { MaskG, MaskVex, MaskR } },
10460     { "kxorq",          { MaskG, MaskVex, MaskR } },
10461   },
10462   {
10463     /* VEX_W_0F47_P_2_LEN_1 */
10464     { "kxorb",          { MaskG, MaskVex, MaskR } },
10465     { "kxord",          { MaskG, MaskVex, MaskR } },
10466   },
10467   {
10468     /* VEX_W_0F4A_P_0_LEN_1 */
10469     { "kaddw",          { MaskG, MaskVex, MaskR } },
10470     { "kaddq",          { MaskG, MaskVex, MaskR } },
10471   },
10472   {
10473     /* VEX_W_0F4A_P_2_LEN_1 */
10474     { "kaddb",          { MaskG, MaskVex, MaskR } },
10475     { "kaddd",          { MaskG, MaskVex, MaskR } },
10476   },
10477   {
10478     /* VEX_W_0F4B_P_0_LEN_1 */
10479     { "kunpckwd",       { MaskG, MaskVex, MaskR } },
10480     { "kunpckdq",       { MaskG, MaskVex, MaskR } },
10481   },
10482   {
10483     /* VEX_W_0F4B_P_2_LEN_1 */
10484     { "kunpckbw",       { MaskG, MaskVex, MaskR } },
10485   },
10486   {
10487     /* VEX_W_0F50_M_0 */
10488     { "vmovmskpX",      { Gdq, XS } },
10489   },
10490   {
10491     /* VEX_W_0F51_P_0 */
10492     { "vsqrtps",        { XM, EXx } },
10493   },
10494   {
10495     /* VEX_W_0F51_P_1 */
10496     { "vsqrtss",        { XMScalar, VexScalar, EXdScalar } },
10497   },
10498   {
10499     /* VEX_W_0F51_P_2  */
10500     { "vsqrtpd",        { XM, EXx } },
10501   },
10502   {
10503     /* VEX_W_0F51_P_3 */
10504     { "vsqrtsd",        { XMScalar, VexScalar, EXqScalar } },
10505   },
10506   {
10507     /* VEX_W_0F52_P_0 */
10508     { "vrsqrtps",       { XM, EXx } },
10509   },
10510   {
10511     /* VEX_W_0F52_P_1 */
10512     { "vrsqrtss",       { XMScalar, VexScalar, EXdScalar } },
10513   },
10514   {
10515     /* VEX_W_0F53_P_0  */
10516     { "vrcpps",         { XM, EXx } },
10517   },
10518   {
10519     /* VEX_W_0F53_P_1  */
10520     { "vrcpss",         { XMScalar, VexScalar, EXdScalar } },
10521   },
10522   {
10523     /* VEX_W_0F58_P_0  */
10524     { "vaddps",         { XM, Vex, EXx } },
10525   },
10526   {
10527     /* VEX_W_0F58_P_1  */
10528     { "vaddss",         { XMScalar, VexScalar, EXdScalar } },
10529   },
10530   {
10531     /* VEX_W_0F58_P_2  */
10532     { "vaddpd",         { XM, Vex, EXx } },
10533   },
10534   {
10535     /* VEX_W_0F58_P_3  */
10536     { "vaddsd",         { XMScalar, VexScalar, EXqScalar } },
10537   },
10538   {
10539     /* VEX_W_0F59_P_0  */
10540     { "vmulps",         { XM, Vex, EXx } },
10541   },
10542   {
10543     /* VEX_W_0F59_P_1  */
10544     { "vmulss",         { XMScalar, VexScalar, EXdScalar } },
10545   },
10546   {
10547     /* VEX_W_0F59_P_2  */
10548     { "vmulpd",         { XM, Vex, EXx } },
10549   },
10550   {
10551     /* VEX_W_0F59_P_3  */
10552     { "vmulsd",         { XMScalar, VexScalar, EXqScalar } },
10553   },
10554   {
10555     /* VEX_W_0F5A_P_0  */
10556     { "vcvtps2pd",      { XM, EXxmmq } },
10557   },
10558   {
10559     /* VEX_W_0F5A_P_1  */
10560     { "vcvtss2sd",      { XMScalar, VexScalar, EXdScalar } },
10561   },
10562   {
10563     /* VEX_W_0F5A_P_3  */
10564     { "vcvtsd2ss",      { XMScalar, VexScalar, EXqScalar } },
10565   },
10566   {
10567     /* VEX_W_0F5B_P_0  */
10568     { "vcvtdq2ps",      { XM, EXx } },
10569   },
10570   {
10571     /* VEX_W_0F5B_P_1  */
10572     { "vcvttps2dq",     { XM, EXx } },
10573   },
10574   {
10575     /* VEX_W_0F5B_P_2  */
10576     { "vcvtps2dq",      { XM, EXx } },
10577   },
10578   {
10579     /* VEX_W_0F5C_P_0  */
10580     { "vsubps",         { XM, Vex, EXx } },
10581   },
10582   {
10583     /* VEX_W_0F5C_P_1  */
10584     { "vsubss",         { XMScalar, VexScalar, EXdScalar } },
10585   },
10586   {
10587     /* VEX_W_0F5C_P_2  */
10588     { "vsubpd",         { XM, Vex, EXx } },
10589   },
10590   {
10591     /* VEX_W_0F5C_P_3  */
10592     { "vsubsd",         { XMScalar, VexScalar, EXqScalar } },
10593   },
10594   {
10595     /* VEX_W_0F5D_P_0  */
10596     { "vminps",         { XM, Vex, EXx } },
10597   },
10598   {
10599     /* VEX_W_0F5D_P_1  */
10600     { "vminss",         { XMScalar, VexScalar, EXdScalar } },
10601   },
10602   {
10603     /* VEX_W_0F5D_P_2  */
10604     { "vminpd",         { XM, Vex, EXx } },
10605   },
10606   {
10607     /* VEX_W_0F5D_P_3  */
10608     { "vminsd",         { XMScalar, VexScalar, EXqScalar } },
10609   },
10610   {
10611     /* VEX_W_0F5E_P_0  */
10612     { "vdivps",         { XM, Vex, EXx } },
10613   },
10614   {
10615     /* VEX_W_0F5E_P_1  */
10616     { "vdivss",         { XMScalar, VexScalar, EXdScalar } },
10617   },
10618   {
10619     /* VEX_W_0F5E_P_2  */
10620     { "vdivpd",         { XM, Vex, EXx } },
10621   },
10622   {
10623     /* VEX_W_0F5E_P_3  */
10624     { "vdivsd",         { XMScalar, VexScalar, EXqScalar } },
10625   },
10626   {
10627     /* VEX_W_0F5F_P_0  */
10628     { "vmaxps",         { XM, Vex, EXx } },
10629   },
10630   {
10631     /* VEX_W_0F5F_P_1  */
10632     { "vmaxss",         { XMScalar, VexScalar, EXdScalar } },
10633   },
10634   {
10635     /* VEX_W_0F5F_P_2  */
10636     { "vmaxpd",         { XM, Vex, EXx } },
10637   },
10638   {
10639     /* VEX_W_0F5F_P_3  */
10640     { "vmaxsd",         { XMScalar, VexScalar, EXqScalar } },
10641   },
10642   {
10643     /* VEX_W_0F60_P_2  */
10644     { "vpunpcklbw",     { XM, Vex, EXx } },
10645   },
10646   {
10647     /* VEX_W_0F61_P_2  */
10648     { "vpunpcklwd",     { XM, Vex, EXx } },
10649   },
10650   {
10651     /* VEX_W_0F62_P_2  */
10652     { "vpunpckldq",     { XM, Vex, EXx } },
10653   },
10654   {
10655     /* VEX_W_0F63_P_2  */
10656     { "vpacksswb",      { XM, Vex, EXx } },
10657   },
10658   {
10659     /* VEX_W_0F64_P_2  */
10660     { "vpcmpgtb",       { XM, Vex, EXx } },
10661   },
10662   {
10663     /* VEX_W_0F65_P_2  */
10664     { "vpcmpgtw",       { XM, Vex, EXx } },
10665   },
10666   {
10667     /* VEX_W_0F66_P_2  */
10668     { "vpcmpgtd",       { XM, Vex, EXx } },
10669   },
10670   {
10671     /* VEX_W_0F67_P_2  */
10672     { "vpackuswb",      { XM, Vex, EXx } },
10673   },
10674   {
10675     /* VEX_W_0F68_P_2  */
10676     { "vpunpckhbw",     { XM, Vex, EXx } },
10677   },
10678   {
10679     /* VEX_W_0F69_P_2  */
10680     { "vpunpckhwd",     { XM, Vex, EXx } },
10681   },
10682   {
10683     /* VEX_W_0F6A_P_2  */
10684     { "vpunpckhdq",     { XM, Vex, EXx } },
10685   },
10686   {
10687     /* VEX_W_0F6B_P_2  */
10688     { "vpackssdw",      { XM, Vex, EXx } },
10689   },
10690   {
10691     /* VEX_W_0F6C_P_2  */
10692     { "vpunpcklqdq",    { XM, Vex, EXx } },
10693   },
10694   {
10695     /* VEX_W_0F6D_P_2  */
10696     { "vpunpckhqdq",    { XM, Vex, EXx } },
10697   },
10698   {
10699     /* VEX_W_0F6F_P_1  */
10700     { "vmovdqu",        { XM, EXx } },
10701   },
10702   {
10703     /* VEX_W_0F6F_P_2  */
10704     { "vmovdqa",        { XM, EXx } },
10705   },
10706   {
10707     /* VEX_W_0F70_P_1 */
10708     { "vpshufhw",       { XM, EXx, Ib } },
10709   },
10710   {
10711     /* VEX_W_0F70_P_2 */
10712     { "vpshufd",        { XM, EXx, Ib } },
10713   },
10714   {
10715     /* VEX_W_0F70_P_3 */
10716     { "vpshuflw",       { XM, EXx, Ib } },
10717   },
10718   {
10719     /* VEX_W_0F71_R_2_P_2  */
10720     { "vpsrlw",         { Vex, XS, Ib } },
10721   },
10722   {
10723     /* VEX_W_0F71_R_4_P_2  */
10724     { "vpsraw",         { Vex, XS, Ib } },
10725   },
10726   {
10727     /* VEX_W_0F71_R_6_P_2  */
10728     { "vpsllw",         { Vex, XS, Ib } },
10729   },
10730   {
10731     /* VEX_W_0F72_R_2_P_2  */
10732     { "vpsrld",         { Vex, XS, Ib } },
10733   },
10734   {
10735     /* VEX_W_0F72_R_4_P_2  */
10736     { "vpsrad",         { Vex, XS, Ib } },
10737   },
10738   {
10739     /* VEX_W_0F72_R_6_P_2  */
10740     { "vpslld",         { Vex, XS, Ib } },
10741   },
10742   {
10743     /* VEX_W_0F73_R_2_P_2  */
10744     { "vpsrlq",         { Vex, XS, Ib } },
10745   },
10746   {
10747     /* VEX_W_0F73_R_3_P_2  */
10748     { "vpsrldq",        { Vex, XS, Ib } },
10749   },
10750   {
10751     /* VEX_W_0F73_R_6_P_2  */
10752     { "vpsllq",         { Vex, XS, Ib } },
10753   },
10754   {
10755     /* VEX_W_0F73_R_7_P_2  */
10756     { "vpslldq",        { Vex, XS, Ib } },
10757   },
10758   {
10759     /* VEX_W_0F74_P_2 */
10760     { "vpcmpeqb",       { XM, Vex, EXx } },
10761   },
10762   {
10763     /* VEX_W_0F75_P_2 */
10764     { "vpcmpeqw",       { XM, Vex, EXx } },
10765   },
10766   {
10767     /* VEX_W_0F76_P_2 */
10768     { "vpcmpeqd",       { XM, Vex, EXx } },
10769   },
10770   {
10771     /* VEX_W_0F77_P_0 */
10772     { "",               { VZERO } },
10773   },
10774   {
10775     /* VEX_W_0F7C_P_2 */
10776     { "vhaddpd",        { XM, Vex, EXx } },
10777   },
10778   {
10779     /* VEX_W_0F7C_P_3 */
10780     { "vhaddps",        { XM, Vex, EXx } },
10781   },
10782   {
10783     /* VEX_W_0F7D_P_2 */
10784     { "vhsubpd",        { XM, Vex, EXx } },
10785   },
10786   {
10787     /* VEX_W_0F7D_P_3 */
10788     { "vhsubps",        { XM, Vex, EXx } },
10789   },
10790   {
10791     /* VEX_W_0F7E_P_1 */
10792     { "vmovq",          { XMScalar, EXqScalar } },
10793   },
10794   {
10795     /* VEX_W_0F7F_P_1 */
10796     { "vmovdqu",        { EXxS, XM } },
10797   },
10798   {
10799     /* VEX_W_0F7F_P_2 */
10800     { "vmovdqa",        { EXxS, XM } },
10801   },
10802   {
10803     /* VEX_W_0F90_P_0_LEN_0 */
10804     { "kmovw",          { MaskG, MaskE } },
10805     { "kmovq",          { MaskG, MaskE } },
10806   },
10807   {
10808     /* VEX_W_0F90_P_2_LEN_0 */
10809     { "kmovb",          { MaskG, MaskBDE } },
10810     { "kmovd",          { MaskG, MaskBDE } },
10811   },
10812   {
10813     /* VEX_W_0F91_P_0_LEN_0 */
10814     { "kmovw",          { Ew, MaskG } },
10815     { "kmovq",          { Eq, MaskG } },
10816   },
10817   {
10818     /* VEX_W_0F91_P_2_LEN_0 */
10819     { "kmovb",          { Eb, MaskG } },
10820     { "kmovd",          { Ed, MaskG } },
10821   },
10822   {
10823     /* VEX_W_0F92_P_0_LEN_0 */
10824     { "kmovw",          { MaskG, Rdq } },
10825   },
10826   {
10827     /* VEX_W_0F92_P_2_LEN_0 */
10828     { "kmovb",          { MaskG, Rdq } },
10829   },
10830   {
10831     /* VEX_W_0F92_P_3_LEN_0 */
10832     { "kmovd",          { MaskG, Rdq } },
10833     { "kmovq",          { MaskG, Rdq } },
10834   },
10835   {
10836     /* VEX_W_0F93_P_0_LEN_0 */
10837     { "kmovw",          { Gdq, MaskR } },
10838   },
10839   {
10840     /* VEX_W_0F93_P_2_LEN_0 */
10841     { "kmovb",          { Gdq, MaskR } },
10842   },
10843   {
10844     /* VEX_W_0F93_P_3_LEN_0 */
10845     { "kmovd",          { Gdq, MaskR } },
10846     { "kmovq",          { Gdq, MaskR } },
10847   },
10848   {
10849     /* VEX_W_0F98_P_0_LEN_0 */
10850     { "kortestw",       { MaskG, MaskR } },
10851     { "kortestq",       { MaskG, MaskR } },
10852   },
10853   {
10854     /* VEX_W_0F98_P_2_LEN_0 */
10855     { "kortestb",       { MaskG, MaskR } },
10856     { "kortestd",       { MaskG, MaskR } },
10857   },
10858   {
10859     /* VEX_W_0F99_P_0_LEN_0 */
10860     { "ktestw", { MaskG, MaskR } },
10861     { "ktestq", { MaskG, MaskR } },
10862   },
10863   {
10864     /* VEX_W_0F99_P_2_LEN_0 */
10865     { "ktestb", { MaskG, MaskR } },
10866     { "ktestd", { MaskG, MaskR } },
10867   },
10868   {
10869     /* VEX_W_0FAE_R_2_M_0 */
10870     { "vldmxcsr",       { Md } },
10871   },
10872   {
10873     /* VEX_W_0FAE_R_3_M_0 */
10874     { "vstmxcsr",       { Md } },
10875   },
10876   {
10877     /* VEX_W_0FC2_P_0 */
10878     { "vcmpps",         { XM, Vex, EXx, VCMP } },
10879   },
10880   {
10881     /* VEX_W_0FC2_P_1 */
10882     { "vcmpss",         { XMScalar, VexScalar, EXdScalar, VCMP } },
10883   },
10884   {
10885     /* VEX_W_0FC2_P_2 */
10886     { "vcmppd",         { XM, Vex, EXx, VCMP } },
10887   },
10888   {
10889     /* VEX_W_0FC2_P_3 */
10890     { "vcmpsd",         { XMScalar, VexScalar, EXqScalar, VCMP } },
10891   },
10892   {
10893     /* VEX_W_0FC4_P_2 */
10894     { "vpinsrw",        { XM, Vex128, Edqw, Ib } },
10895   },
10896   {
10897     /* VEX_W_0FC5_P_2 */
10898     { "vpextrw",        { Gdq, XS, Ib } },
10899   },
10900   {
10901     /* VEX_W_0FD0_P_2 */
10902     { "vaddsubpd",      { XM, Vex, EXx } },
10903   },
10904   {
10905     /* VEX_W_0FD0_P_3 */
10906     { "vaddsubps",      { XM, Vex, EXx } },
10907   },
10908   {
10909     /* VEX_W_0FD1_P_2 */
10910     { "vpsrlw",         { XM, Vex, EXxmm } },
10911   },
10912   {
10913     /* VEX_W_0FD2_P_2 */
10914     { "vpsrld",         { XM, Vex, EXxmm } },
10915   },
10916   {
10917     /* VEX_W_0FD3_P_2 */
10918     { "vpsrlq",         { XM, Vex, EXxmm } },
10919   },
10920   {
10921     /* VEX_W_0FD4_P_2 */
10922     { "vpaddq",         { XM, Vex, EXx } },
10923   },
10924   {
10925     /* VEX_W_0FD5_P_2 */
10926     { "vpmullw",        { XM, Vex, EXx } },
10927   },
10928   {
10929     /* VEX_W_0FD6_P_2 */
10930     { "vmovq",          { EXqScalarS, XMScalar } },
10931   },
10932   {
10933     /* VEX_W_0FD7_P_2_M_1 */
10934     { "vpmovmskb",      { Gdq, XS } },
10935   },
10936   {
10937     /* VEX_W_0FD8_P_2 */
10938     { "vpsubusb",       { XM, Vex, EXx } },
10939   },
10940   {
10941     /* VEX_W_0FD9_P_2 */
10942     { "vpsubusw",       { XM, Vex, EXx } },
10943   },
10944   {
10945     /* VEX_W_0FDA_P_2 */
10946     { "vpminub",        { XM, Vex, EXx } },
10947   },
10948   {
10949     /* VEX_W_0FDB_P_2 */
10950     { "vpand",          { XM, Vex, EXx } },
10951   },
10952   {
10953     /* VEX_W_0FDC_P_2 */
10954     { "vpaddusb",       { XM, Vex, EXx } },
10955   },
10956   {
10957     /* VEX_W_0FDD_P_2 */
10958     { "vpaddusw",       { XM, Vex, EXx } },
10959   },
10960   {
10961     /* VEX_W_0FDE_P_2 */
10962     { "vpmaxub",        { XM, Vex, EXx } },
10963   },
10964   {
10965     /* VEX_W_0FDF_P_2 */
10966     { "vpandn",         { XM, Vex, EXx } },
10967   },
10968   {
10969     /* VEX_W_0FE0_P_2  */
10970     { "vpavgb",         { XM, Vex, EXx } },
10971   },
10972   {
10973     /* VEX_W_0FE1_P_2  */
10974     { "vpsraw",         { XM, Vex, EXxmm } },
10975   },
10976   {
10977     /* VEX_W_0FE2_P_2  */
10978     { "vpsrad",         { XM, Vex, EXxmm } },
10979   },
10980   {
10981     /* VEX_W_0FE3_P_2  */
10982     { "vpavgw",         { XM, Vex, EXx } },
10983   },
10984   {
10985     /* VEX_W_0FE4_P_2  */
10986     { "vpmulhuw",       { XM, Vex, EXx } },
10987   },
10988   {
10989     /* VEX_W_0FE5_P_2  */
10990     { "vpmulhw",        { XM, Vex, EXx } },
10991   },
10992   {
10993     /* VEX_W_0FE6_P_1  */
10994     { "vcvtdq2pd",      { XM, EXxmmq } },
10995   },
10996   {
10997     /* VEX_W_0FE6_P_2  */
10998     { "vcvttpd2dq%XY",  { XMM, EXx } },
10999   },
11000   {
11001     /* VEX_W_0FE6_P_3  */
11002     { "vcvtpd2dq%XY",   { XMM, EXx } },
11003   },
11004   {
11005     /* VEX_W_0FE7_P_2_M_0 */
11006     { "vmovntdq",       { Mx, XM } },
11007   },
11008   {
11009     /* VEX_W_0FE8_P_2  */
11010     { "vpsubsb",        { XM, Vex, EXx } },
11011   },
11012   {
11013     /* VEX_W_0FE9_P_2  */
11014     { "vpsubsw",        { XM, Vex, EXx } },
11015   },
11016   {
11017     /* VEX_W_0FEA_P_2  */
11018     { "vpminsw",        { XM, Vex, EXx } },
11019   },
11020   {
11021     /* VEX_W_0FEB_P_2  */
11022     { "vpor",           { XM, Vex, EXx } },
11023   },
11024   {
11025     /* VEX_W_0FEC_P_2  */
11026     { "vpaddsb",        { XM, Vex, EXx } },
11027   },
11028   {
11029     /* VEX_W_0FED_P_2  */
11030     { "vpaddsw",        { XM, Vex, EXx } },
11031   },
11032   {
11033     /* VEX_W_0FEE_P_2  */
11034     { "vpmaxsw",        { XM, Vex, EXx } },
11035   },
11036   {
11037     /* VEX_W_0FEF_P_2  */
11038     { "vpxor",          { XM, Vex, EXx } },
11039   },
11040   {
11041     /* VEX_W_0FF0_P_3_M_0 */
11042     { "vlddqu",         { XM, M } },
11043   },
11044   {
11045     /* VEX_W_0FF1_P_2 */
11046     { "vpsllw",         { XM, Vex, EXxmm } },
11047   },
11048   {
11049     /* VEX_W_0FF2_P_2 */
11050     { "vpslld",         { XM, Vex, EXxmm } },
11051   },
11052   {
11053     /* VEX_W_0FF3_P_2 */
11054     { "vpsllq",         { XM, Vex, EXxmm } },
11055   },
11056   {
11057     /* VEX_W_0FF4_P_2 */
11058     { "vpmuludq",       { XM, Vex, EXx } },
11059   },
11060   {
11061     /* VEX_W_0FF5_P_2 */
11062     { "vpmaddwd",       { XM, Vex, EXx } },
11063   },
11064   {
11065     /* VEX_W_0FF6_P_2 */
11066     { "vpsadbw",        { XM, Vex, EXx } },
11067   },
11068   {
11069     /* VEX_W_0FF7_P_2 */
11070     { "vmaskmovdqu",    { XM, XS } },
11071   },
11072   {
11073     /* VEX_W_0FF8_P_2 */
11074     { "vpsubb",         { XM, Vex, EXx } },
11075   },
11076   {
11077     /* VEX_W_0FF9_P_2 */
11078     { "vpsubw",         { XM, Vex, EXx } },
11079   },
11080   {
11081     /* VEX_W_0FFA_P_2 */
11082     { "vpsubd",         { XM, Vex, EXx } },
11083   },
11084   {
11085     /* VEX_W_0FFB_P_2 */
11086     { "vpsubq",         { XM, Vex, EXx } },
11087   },
11088   {
11089     /* VEX_W_0FFC_P_2 */
11090     { "vpaddb",         { XM, Vex, EXx } },
11091   },
11092   {
11093     /* VEX_W_0FFD_P_2 */
11094     { "vpaddw",         { XM, Vex, EXx } },
11095   },
11096   {
11097     /* VEX_W_0FFE_P_2 */
11098     { "vpaddd",         { XM, Vex, EXx } },
11099   },
11100   {
11101     /* VEX_W_0F3800_P_2  */
11102     { "vpshufb",        { XM, Vex, EXx } },
11103   },
11104   {
11105     /* VEX_W_0F3801_P_2  */
11106     { "vphaddw",        { XM, Vex, EXx } },
11107   },
11108   {
11109     /* VEX_W_0F3802_P_2  */
11110     { "vphaddd",        { XM, Vex, EXx } },
11111   },
11112   {
11113     /* VEX_W_0F3803_P_2  */
11114     { "vphaddsw",       { XM, Vex, EXx } },
11115   },
11116   {
11117     /* VEX_W_0F3804_P_2  */
11118     { "vpmaddubsw",     { XM, Vex, EXx } },
11119   },
11120   {
11121     /* VEX_W_0F3805_P_2  */
11122     { "vphsubw",        { XM, Vex, EXx } },
11123   },
11124   {
11125     /* VEX_W_0F3806_P_2  */
11126     { "vphsubd",        { XM, Vex, EXx } },
11127   },
11128   {
11129     /* VEX_W_0F3807_P_2  */
11130     { "vphsubsw",       { XM, Vex, EXx } },
11131   },
11132   {
11133     /* VEX_W_0F3808_P_2  */
11134     { "vpsignb",        { XM, Vex, EXx } },
11135   },
11136   {
11137     /* VEX_W_0F3809_P_2  */
11138     { "vpsignw",        { XM, Vex, EXx } },
11139   },
11140   {
11141     /* VEX_W_0F380A_P_2  */
11142     { "vpsignd",        { XM, Vex, EXx } },
11143   },
11144   {
11145     /* VEX_W_0F380B_P_2  */
11146     { "vpmulhrsw",      { XM, Vex, EXx } },
11147   },
11148   {
11149     /* VEX_W_0F380C_P_2  */
11150     { "vpermilps",      { XM, Vex, EXx } },
11151   },
11152   {
11153     /* VEX_W_0F380D_P_2  */
11154     { "vpermilpd",      { XM, Vex, EXx } },
11155   },
11156   {
11157     /* VEX_W_0F380E_P_2  */
11158     { "vtestps",        { XM, EXx } },
11159   },
11160   {
11161     /* VEX_W_0F380F_P_2  */
11162     { "vtestpd",        { XM, EXx } },
11163   },
11164   {
11165     /* VEX_W_0F3816_P_2  */
11166     { "vpermps",        { XM, Vex, EXx } },
11167   },
11168   {
11169     /* VEX_W_0F3817_P_2 */
11170     { "vptest",         { XM, EXx } },
11171   },
11172   {
11173     /* VEX_W_0F3818_P_2 */
11174     { "vbroadcastss",   { XM, EXxmm_md } },
11175   },
11176   {
11177     /* VEX_W_0F3819_P_2 */
11178     { "vbroadcastsd",   { XM, EXxmm_mq } },
11179   },
11180   {
11181     /* VEX_W_0F381A_P_2_M_0 */
11182     { "vbroadcastf128", { XM, Mxmm } },
11183   },
11184   {
11185     /* VEX_W_0F381C_P_2 */
11186     { "vpabsb",         { XM, EXx } },
11187   },
11188   {
11189     /* VEX_W_0F381D_P_2 */
11190     { "vpabsw",         { XM, EXx } },
11191   },
11192   {
11193     /* VEX_W_0F381E_P_2 */
11194     { "vpabsd",         { XM, EXx } },
11195   },
11196   {
11197     /* VEX_W_0F3820_P_2 */
11198     { "vpmovsxbw",      { XM, EXxmmq } },
11199   },
11200   {
11201     /* VEX_W_0F3821_P_2 */
11202     { "vpmovsxbd",      { XM, EXxmmqd } },
11203   },
11204   {
11205     /* VEX_W_0F3822_P_2 */
11206     { "vpmovsxbq",      { XM, EXxmmdw } },
11207   },
11208   {
11209     /* VEX_W_0F3823_P_2 */
11210     { "vpmovsxwd",      { XM, EXxmmq } },
11211   },
11212   {
11213     /* VEX_W_0F3824_P_2 */
11214     { "vpmovsxwq",      { XM, EXxmmqd } },
11215   },
11216   {
11217     /* VEX_W_0F3825_P_2 */
11218     { "vpmovsxdq",      { XM, EXxmmq } },
11219   },
11220   {
11221     /* VEX_W_0F3828_P_2 */
11222     { "vpmuldq",        { XM, Vex, EXx } },
11223   },
11224   {
11225     /* VEX_W_0F3829_P_2 */
11226     { "vpcmpeqq",       { XM, Vex, EXx } },
11227   },
11228   {
11229     /* VEX_W_0F382A_P_2_M_0 */
11230     { "vmovntdqa",      { XM, Mx } },
11231   },
11232   {
11233     /* VEX_W_0F382B_P_2 */
11234     { "vpackusdw",      { XM, Vex, EXx } },
11235   },
11236   {
11237     /* VEX_W_0F382C_P_2_M_0 */
11238     { "vmaskmovps",     { XM, Vex, Mx } },
11239   },
11240   {
11241     /* VEX_W_0F382D_P_2_M_0 */
11242     { "vmaskmovpd",     { XM, Vex, Mx } },
11243   },
11244   {
11245     /* VEX_W_0F382E_P_2_M_0 */
11246     { "vmaskmovps",     { Mx, Vex, XM } },
11247   },
11248   {
11249     /* VEX_W_0F382F_P_2_M_0 */
11250     { "vmaskmovpd",     { Mx, Vex, XM } },
11251   },
11252   {
11253     /* VEX_W_0F3830_P_2 */
11254     { "vpmovzxbw",      { XM, EXxmmq } },
11255   },
11256   {
11257     /* VEX_W_0F3831_P_2 */
11258     { "vpmovzxbd",      { XM, EXxmmqd } },
11259   },
11260   {
11261     /* VEX_W_0F3832_P_2 */
11262     { "vpmovzxbq",      { XM, EXxmmdw } },
11263   },
11264   {
11265     /* VEX_W_0F3833_P_2 */
11266     { "vpmovzxwd",      { XM, EXxmmq } },
11267   },
11268   {
11269     /* VEX_W_0F3834_P_2 */
11270     { "vpmovzxwq",      { XM, EXxmmqd } },
11271   },
11272   {
11273     /* VEX_W_0F3835_P_2 */
11274     { "vpmovzxdq",      { XM, EXxmmq } },
11275   },
11276   {
11277     /* VEX_W_0F3836_P_2  */
11278     { "vpermd",         { XM, Vex, EXx } },
11279   },
11280   {
11281     /* VEX_W_0F3837_P_2 */
11282     { "vpcmpgtq",       { XM, Vex, EXx } },
11283   },
11284   {
11285     /* VEX_W_0F3838_P_2 */
11286     { "vpminsb",        { XM, Vex, EXx } },
11287   },
11288   {
11289     /* VEX_W_0F3839_P_2 */
11290     { "vpminsd",        { XM, Vex, EXx } },
11291   },
11292   {
11293     /* VEX_W_0F383A_P_2 */
11294     { "vpminuw",        { XM, Vex, EXx } },
11295   },
11296   {
11297     /* VEX_W_0F383B_P_2 */
11298     { "vpminud",        { XM, Vex, EXx } },
11299   },
11300   {
11301     /* VEX_W_0F383C_P_2 */
11302     { "vpmaxsb",        { XM, Vex, EXx } },
11303   },
11304   {
11305     /* VEX_W_0F383D_P_2 */
11306     { "vpmaxsd",        { XM, Vex, EXx } },
11307   },
11308   {
11309     /* VEX_W_0F383E_P_2 */
11310     { "vpmaxuw",        { XM, Vex, EXx } },
11311   },
11312   {
11313     /* VEX_W_0F383F_P_2 */
11314     { "vpmaxud",        { XM, Vex, EXx } },
11315   },
11316   {
11317     /* VEX_W_0F3840_P_2 */
11318     { "vpmulld",        { XM, Vex, EXx } },
11319   },
11320   {
11321     /* VEX_W_0F3841_P_2 */
11322     { "vphminposuw",    { XM, EXx } },
11323   },
11324   {
11325     /* VEX_W_0F3846_P_2 */
11326     { "vpsravd",        { XM, Vex, EXx } },
11327   },
11328   {
11329     /* VEX_W_0F3858_P_2 */
11330     { "vpbroadcastd", { XM, EXxmm_md } },
11331   },
11332   {
11333     /* VEX_W_0F3859_P_2 */
11334     { "vpbroadcastq",   { XM, EXxmm_mq } },
11335   },
11336   {
11337     /* VEX_W_0F385A_P_2_M_0 */
11338     { "vbroadcasti128", { XM, Mxmm } },
11339   },
11340   {
11341     /* VEX_W_0F3878_P_2 */
11342     { "vpbroadcastb",   { XM, EXxmm_mb } },
11343   },
11344   {
11345     /* VEX_W_0F3879_P_2 */
11346     { "vpbroadcastw",   { XM, EXxmm_mw } },
11347   },
11348   {
11349     /* VEX_W_0F38DB_P_2 */
11350     { "vaesimc",        { XM, EXx } },
11351   },
11352   {
11353     /* VEX_W_0F38DC_P_2 */
11354     { "vaesenc",        { XM, Vex128, EXx } },
11355   },
11356   {
11357     /* VEX_W_0F38DD_P_2 */
11358     { "vaesenclast",    { XM, Vex128, EXx } },
11359   },
11360   {
11361     /* VEX_W_0F38DE_P_2 */
11362     { "vaesdec",        { XM, Vex128, EXx } },
11363   },
11364   {
11365     /* VEX_W_0F38DF_P_2 */
11366     { "vaesdeclast",    { XM, Vex128, EXx } },
11367   },
11368   {
11369     /* VEX_W_0F3A00_P_2 */
11370     { Bad_Opcode },
11371     { "vpermq",         { XM, EXx, Ib } },
11372   },
11373   {
11374     /* VEX_W_0F3A01_P_2 */
11375     { Bad_Opcode },
11376     { "vpermpd",        { XM, EXx, Ib } },
11377   },
11378   {
11379     /* VEX_W_0F3A02_P_2 */
11380     { "vpblendd",       { XM, Vex, EXx, Ib } },
11381   },
11382   {
11383     /* VEX_W_0F3A04_P_2 */
11384     { "vpermilps",      { XM, EXx, Ib } },
11385   },
11386   {
11387     /* VEX_W_0F3A05_P_2 */
11388     { "vpermilpd",      { XM, EXx, Ib } },
11389   },
11390   {
11391     /* VEX_W_0F3A06_P_2 */
11392     { "vperm2f128",     { XM, Vex256, EXx, Ib } },
11393   },
11394   {
11395     /* VEX_W_0F3A08_P_2 */
11396     { "vroundps",       { XM, EXx, Ib } },
11397   },
11398   {
11399     /* VEX_W_0F3A09_P_2 */
11400     { "vroundpd",       { XM, EXx, Ib } },
11401   },
11402   {
11403     /* VEX_W_0F3A0A_P_2 */
11404     { "vroundss",       { XMScalar, VexScalar, EXdScalar, Ib } },
11405   },
11406   {
11407     /* VEX_W_0F3A0B_P_2 */
11408     { "vroundsd",       { XMScalar, VexScalar, EXqScalar, Ib } },
11409   },
11410   {
11411     /* VEX_W_0F3A0C_P_2 */
11412     { "vblendps",       { XM, Vex, EXx, Ib } },
11413   },
11414   {
11415     /* VEX_W_0F3A0D_P_2 */
11416     { "vblendpd",       { XM, Vex, EXx, Ib } },
11417   },
11418   {
11419     /* VEX_W_0F3A0E_P_2 */
11420     { "vpblendw",       { XM, Vex, EXx, Ib } },
11421   },
11422   {
11423     /* VEX_W_0F3A0F_P_2 */
11424     { "vpalignr",       { XM, Vex, EXx, Ib } },
11425   },
11426   {
11427     /* VEX_W_0F3A14_P_2 */
11428     { "vpextrb",        { Edqb, XM, Ib } },
11429   },
11430   {
11431     /* VEX_W_0F3A15_P_2 */
11432     { "vpextrw",        { Edqw, XM, Ib } },
11433   },
11434   {
11435     /* VEX_W_0F3A18_P_2 */
11436     { "vinsertf128",    { XM, Vex256, EXxmm, Ib } },
11437   },
11438   {
11439     /* VEX_W_0F3A19_P_2 */
11440     { "vextractf128",   { EXxmm, XM, Ib } },
11441   },
11442   {
11443     /* VEX_W_0F3A20_P_2 */
11444     { "vpinsrb",        { XM, Vex128, Edqb, Ib } },
11445   },
11446   {
11447     /* VEX_W_0F3A21_P_2 */
11448     { "vinsertps",      { XM, Vex128, EXd, Ib } },
11449   },
11450   {
11451     /* VEX_W_0F3A30_P_2_LEN_0 */
11452     { "kshiftrb",       { MaskG, MaskR, Ib } },
11453     { "kshiftrw",       { MaskG, MaskR, Ib } },
11454   },
11455   {
11456     /* VEX_W_0F3A31_P_2_LEN_0 */
11457     { "kshiftrd",       { MaskG, MaskR, Ib } },
11458     { "kshiftrq",       { MaskG, MaskR, Ib } },
11459   },
11460   {
11461     /* VEX_W_0F3A32_P_2_LEN_0 */
11462     { "kshiftlb",       { MaskG, MaskR, Ib } },
11463     { "kshiftlw",       { MaskG, MaskR, Ib } },
11464   },
11465   {
11466     /* VEX_W_0F3A33_P_2_LEN_0 */
11467     { "kshiftld",       { MaskG, MaskR, Ib } },
11468     { "kshiftlq",       { MaskG, MaskR, Ib } },
11469   },
11470   {
11471     /* VEX_W_0F3A38_P_2 */
11472     { "vinserti128",    { XM, Vex256, EXxmm, Ib } },
11473   },
11474   {
11475     /* VEX_W_0F3A39_P_2 */
11476     { "vextracti128",   { EXxmm, XM, Ib } },
11477   },
11478   {
11479     /* VEX_W_0F3A40_P_2 */
11480     { "vdpps",          { XM, Vex, EXx, Ib } },
11481   },
11482   {
11483     /* VEX_W_0F3A41_P_2 */
11484     { "vdppd",          { XM, Vex128, EXx, Ib } },
11485   },
11486   {
11487     /* VEX_W_0F3A42_P_2 */
11488     { "vmpsadbw",       { XM, Vex, EXx, Ib } },
11489   },
11490   {
11491     /* VEX_W_0F3A44_P_2 */
11492     { "vpclmulqdq",     { XM, Vex128, EXx, PCLMUL } },
11493   },
11494   {
11495     /* VEX_W_0F3A46_P_2 */
11496     { "vperm2i128",     { XM, Vex256, EXx, Ib } },
11497   },
11498   {
11499     /* VEX_W_0F3A48_P_2 */
11500     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
11501     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
11502   },
11503   {
11504     /* VEX_W_0F3A49_P_2 */
11505     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
11506     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
11507   },
11508   {
11509     /* VEX_W_0F3A4A_P_2 */
11510     { "vblendvps",      { XM, Vex, EXx, XMVexI4 } },
11511   },
11512   {
11513     /* VEX_W_0F3A4B_P_2 */
11514     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 } },
11515   },
11516   {
11517     /* VEX_W_0F3A4C_P_2 */
11518     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 } },
11519   },
11520   {
11521     /* VEX_W_0F3A60_P_2 */
11522     { "vpcmpestrm",     { XM, EXx, Ib } },
11523   },
11524   {
11525     /* VEX_W_0F3A61_P_2 */
11526     { "vpcmpestri",     { XM, EXx, Ib } },
11527   },
11528   {
11529     /* VEX_W_0F3A62_P_2 */
11530     { "vpcmpistrm",     { XM, EXx, Ib } },
11531   },
11532   {
11533     /* VEX_W_0F3A63_P_2 */
11534     { "vpcmpistri",     { XM, EXx, Ib } },
11535   },
11536   {
11537     /* VEX_W_0F3ADF_P_2 */
11538     { "vaeskeygenassist", { XM, EXx, Ib } },
11539   },
11540 #define NEED_VEX_W_TABLE
11541 #include "i386-dis-evex.h"
11542 #undef NEED_VEX_W_TABLE
11543 };
11544
11545 static const struct dis386 mod_table[][2] = {
11546   {
11547     /* MOD_8D */
11548     { "leaS",           { Gv, M } },
11549   },
11550   {
11551     /* MOD_C6_REG_7 */
11552     { Bad_Opcode },
11553     { RM_TABLE (RM_C6_REG_7) },
11554   },
11555   {
11556     /* MOD_C7_REG_7 */
11557     { Bad_Opcode },
11558     { RM_TABLE (RM_C7_REG_7) },
11559   },
11560   {
11561     /* MOD_FF_REG_3 */
11562     { "Jcall{T|}", { indirEp } },
11563   },
11564   {
11565     /* MOD_FF_REG_5 */
11566     { "Jjmp{T|}", { indirEp } },
11567   },
11568   {
11569     /* MOD_0F01_REG_0 */
11570     { X86_64_TABLE (X86_64_0F01_REG_0) },
11571     { RM_TABLE (RM_0F01_REG_0) },
11572   },
11573   {
11574     /* MOD_0F01_REG_1 */
11575     { X86_64_TABLE (X86_64_0F01_REG_1) },
11576     { RM_TABLE (RM_0F01_REG_1) },
11577   },
11578   {
11579     /* MOD_0F01_REG_2 */
11580     { X86_64_TABLE (X86_64_0F01_REG_2) },
11581     { RM_TABLE (RM_0F01_REG_2) },
11582   },
11583   {
11584     /* MOD_0F01_REG_3 */
11585     { X86_64_TABLE (X86_64_0F01_REG_3) },
11586     { RM_TABLE (RM_0F01_REG_3) },
11587   },
11588   {
11589     /* MOD_0F01_REG_7 */
11590     { "invlpg",         { Mb } },
11591     { RM_TABLE (RM_0F01_REG_7) },
11592   },
11593   {
11594     /* MOD_0F12_PREFIX_0 */
11595     { "movlps",         { XM, EXq } },
11596     { "movhlps",        { XM, EXq } },
11597   },
11598   {
11599     /* MOD_0F13 */
11600     { "movlpX",         { EXq, XM } },
11601   },
11602   {
11603     /* MOD_0F16_PREFIX_0 */
11604     { "movhps",         { XM, EXq } },
11605     { "movlhps",        { XM, EXq } },
11606   },
11607   {
11608     /* MOD_0F17 */
11609     { "movhpX",         { EXq, XM } },
11610   },
11611   {
11612     /* MOD_0F18_REG_0 */
11613     { "prefetchnta",    { Mb } },
11614   },
11615   {
11616     /* MOD_0F18_REG_1 */
11617     { "prefetcht0",     { Mb } },
11618   },
11619   {
11620     /* MOD_0F18_REG_2 */
11621     { "prefetcht1",     { Mb } },
11622   },
11623   {
11624     /* MOD_0F18_REG_3 */
11625     { "prefetcht2",     { Mb } },
11626   },
11627   {
11628     /* MOD_0F18_REG_4 */
11629     { "nop/reserved",   { Mb } },
11630   },
11631   {
11632     /* MOD_0F18_REG_5 */
11633     { "nop/reserved",   { Mb } },
11634   },
11635   {
11636     /* MOD_0F18_REG_6 */
11637     { "nop/reserved",   { Mb } },
11638   },
11639   {
11640     /* MOD_0F18_REG_7 */
11641     { "nop/reserved",   { Mb } },
11642   },
11643   {
11644     /* MOD_0F1A_PREFIX_0 */
11645     { "bndldx",         { Gbnd, Ev_bnd } },
11646     { "nopQ",           { Ev } },
11647   },
11648   {
11649     /* MOD_0F1B_PREFIX_0 */
11650     { "bndstx",         { Ev_bnd, Gbnd } },
11651     { "nopQ",           { Ev } },
11652   },
11653   {
11654     /* MOD_0F1B_PREFIX_1 */
11655     { "bndmk",          { Gbnd, Ev_bnd } },
11656     { "nopQ",           { Ev } },
11657   },
11658   {
11659     /* MOD_0F24 */
11660     { Bad_Opcode },
11661     { "movL",           { Rd, Td } },
11662   },
11663   {
11664     /* MOD_0F26 */
11665     { Bad_Opcode },
11666     { "movL",           { Td, Rd } },
11667   },
11668   {
11669     /* MOD_0F2B_PREFIX_0 */
11670     {"movntps",         { Mx, XM } },
11671   },
11672   {
11673     /* MOD_0F2B_PREFIX_1 */
11674     {"movntss",         { Md, XM } },
11675   },
11676   {
11677     /* MOD_0F2B_PREFIX_2 */
11678     {"movntpd",         { Mx, XM } },
11679   },
11680   {
11681     /* MOD_0F2B_PREFIX_3 */
11682     {"movntsd",         { Mq, XM } },
11683   },
11684   {
11685     /* MOD_0F51 */
11686     { Bad_Opcode },
11687     { "movmskpX",       { Gdq, XS } },
11688   },
11689   {
11690     /* MOD_0F71_REG_2 */
11691     { Bad_Opcode },
11692     { "psrlw",          { MS, Ib } },
11693   },
11694   {
11695     /* MOD_0F71_REG_4 */
11696     { Bad_Opcode },
11697     { "psraw",          { MS, Ib } },
11698   },
11699   {
11700     /* MOD_0F71_REG_6 */
11701     { Bad_Opcode },
11702     { "psllw",          { MS, Ib } },
11703   },
11704   {
11705     /* MOD_0F72_REG_2 */
11706     { Bad_Opcode },
11707     { "psrld",          { MS, Ib } },
11708   },
11709   {
11710     /* MOD_0F72_REG_4 */
11711     { Bad_Opcode },
11712     { "psrad",          { MS, Ib } },
11713   },
11714   {
11715     /* MOD_0F72_REG_6 */
11716     { Bad_Opcode },
11717     { "pslld",          { MS, Ib } },
11718   },
11719   {
11720     /* MOD_0F73_REG_2 */
11721     { Bad_Opcode },
11722     { "psrlq",          { MS, Ib } },
11723   },
11724   {
11725     /* MOD_0F73_REG_3 */
11726     { Bad_Opcode },
11727     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
11728   },
11729   {
11730     /* MOD_0F73_REG_6 */
11731     { Bad_Opcode },
11732     { "psllq",          { MS, Ib } },
11733   },
11734   {
11735     /* MOD_0F73_REG_7 */
11736     { Bad_Opcode },
11737     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
11738   },
11739   {
11740     /* MOD_0FAE_REG_0 */
11741     { "fxsave",         { FXSAVE } },
11742     { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
11743   },
11744   {
11745     /* MOD_0FAE_REG_1 */
11746     { "fxrstor",        { FXSAVE } },
11747     { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
11748   },
11749   {
11750     /* MOD_0FAE_REG_2 */
11751     { "ldmxcsr",        { Md } },
11752     { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
11753   },
11754   {
11755     /* MOD_0FAE_REG_3 */
11756     { "stmxcsr",        { Md } },
11757     { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
11758   },
11759   {
11760     /* MOD_0FAE_REG_4 */
11761     { "xsave",          { FXSAVE } },
11762   },
11763   {
11764     /* MOD_0FAE_REG_5 */
11765     { "xrstor",         { FXSAVE } },
11766     { RM_TABLE (RM_0FAE_REG_5) },
11767   },
11768   {
11769     /* MOD_0FAE_REG_6 */
11770     { PREFIX_TABLE (PREFIX_0FAE_REG_6) },
11771     { RM_TABLE (RM_0FAE_REG_6) },
11772   },
11773   {
11774     /* MOD_0FAE_REG_7 */
11775     { PREFIX_TABLE (PREFIX_0FAE_REG_7) },
11776     { RM_TABLE (RM_0FAE_REG_7) },
11777   },
11778   {
11779     /* MOD_0FB2 */
11780     { "lssS",           { Gv, Mp } },
11781   },
11782   {
11783     /* MOD_0FB4 */
11784     { "lfsS",           { Gv, Mp } },
11785   },
11786   {
11787     /* MOD_0FB5 */
11788     { "lgsS",           { Gv, Mp } },
11789   },
11790   {
11791     /* MOD_0FC7_REG_3 */
11792     { "xrstors",                { FXSAVE } },
11793   },
11794   {
11795     /* MOD_0FC7_REG_4 */
11796     { "xsavec",         { FXSAVE } },
11797   },
11798   {
11799     /* MOD_0FC7_REG_5 */
11800     { "xsaves",         { FXSAVE } },
11801   },
11802   {
11803     /* MOD_0FC7_REG_6 */
11804     { PREFIX_TABLE (PREFIX_0FC7_REG_6) },
11805     { "rdrand",         { Ev } },
11806   },
11807   {
11808     /* MOD_0FC7_REG_7 */
11809     { "vmptrst",        { Mq } },
11810     { "rdseed",         { Ev } },
11811   },
11812   {
11813     /* MOD_0FD7 */
11814     { Bad_Opcode },
11815     { "pmovmskb",       { Gdq, MS } },
11816   },
11817   {
11818     /* MOD_0FE7_PREFIX_2 */
11819     { "movntdq",        { Mx, XM } },
11820   },
11821   {
11822     /* MOD_0FF0_PREFIX_3 */
11823     { "lddqu",          { XM, M } },
11824   },
11825   {
11826     /* MOD_0F382A_PREFIX_2 */
11827     { "movntdqa",       { XM, Mx } },
11828   },
11829   {
11830     /* MOD_62_32BIT */
11831     { "bound{S|}",      { Gv, Ma } },
11832     { EVEX_TABLE (EVEX_0F) },
11833   },
11834   {
11835     /* MOD_C4_32BIT */
11836     { "lesS",           { Gv, Mp } },
11837     { VEX_C4_TABLE (VEX_0F) },
11838   },
11839   {
11840     /* MOD_C5_32BIT */
11841     { "ldsS",           { Gv, Mp } },
11842     { VEX_C5_TABLE (VEX_0F) },
11843   },
11844   {
11845     /* MOD_VEX_0F12_PREFIX_0 */
11846     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
11847     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
11848   },
11849   {
11850     /* MOD_VEX_0F13 */
11851     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
11852   },
11853   {
11854     /* MOD_VEX_0F16_PREFIX_0 */
11855     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
11856     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
11857   },
11858   {
11859     /* MOD_VEX_0F17 */
11860     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
11861   },
11862   {
11863     /* MOD_VEX_0F2B */
11864     { VEX_W_TABLE (VEX_W_0F2B_M_0) },
11865   },
11866   {
11867     /* MOD_VEX_0F50 */
11868     { Bad_Opcode },
11869     { VEX_W_TABLE (VEX_W_0F50_M_0) },
11870   },
11871   {
11872     /* MOD_VEX_0F71_REG_2 */
11873     { Bad_Opcode },
11874     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
11875   },
11876   {
11877     /* MOD_VEX_0F71_REG_4 */
11878     { Bad_Opcode },
11879     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
11880   },
11881   {
11882     /* MOD_VEX_0F71_REG_6 */
11883     { Bad_Opcode },
11884     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
11885   },
11886   {
11887     /* MOD_VEX_0F72_REG_2 */
11888     { Bad_Opcode },
11889     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
11890   },
11891   {
11892     /* MOD_VEX_0F72_REG_4 */
11893     { Bad_Opcode },
11894     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
11895   },
11896   {
11897     /* MOD_VEX_0F72_REG_6 */
11898     { Bad_Opcode },
11899     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
11900   },
11901   {
11902     /* MOD_VEX_0F73_REG_2 */
11903     { Bad_Opcode },
11904     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
11905   },
11906   {
11907     /* MOD_VEX_0F73_REG_3 */
11908     { Bad_Opcode },
11909     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
11910   },
11911   {
11912     /* MOD_VEX_0F73_REG_6 */
11913     { Bad_Opcode },
11914     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
11915   },
11916   {
11917     /* MOD_VEX_0F73_REG_7 */
11918     { Bad_Opcode },
11919     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
11920   },
11921   {
11922     /* MOD_VEX_0FAE_REG_2 */
11923     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
11924   },
11925   {
11926     /* MOD_VEX_0FAE_REG_3 */
11927     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
11928   },
11929   {
11930     /* MOD_VEX_0FD7_PREFIX_2 */
11931     { Bad_Opcode },
11932     { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) },
11933   },
11934   {
11935     /* MOD_VEX_0FE7_PREFIX_2 */
11936     { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) },
11937   },
11938   {
11939     /* MOD_VEX_0FF0_PREFIX_3 */
11940     { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) },
11941   },
11942   {
11943     /* MOD_VEX_0F381A_PREFIX_2 */
11944     { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
11945   },
11946   {
11947     /* MOD_VEX_0F382A_PREFIX_2 */
11948     { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) },
11949   },
11950   {
11951     /* MOD_VEX_0F382C_PREFIX_2 */
11952     { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
11953   },
11954   {
11955     /* MOD_VEX_0F382D_PREFIX_2 */
11956     { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
11957   },
11958   {
11959     /* MOD_VEX_0F382E_PREFIX_2 */
11960     { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
11961   },
11962   {
11963     /* MOD_VEX_0F382F_PREFIX_2 */
11964     { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
11965   },
11966   {
11967     /* MOD_VEX_0F385A_PREFIX_2 */
11968     { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
11969   },
11970   {
11971     /* MOD_VEX_0F388C_PREFIX_2 */
11972     { "vpmaskmov%LW",   { XM, Vex, Mx } },
11973   },
11974   {
11975     /* MOD_VEX_0F388E_PREFIX_2 */
11976     { "vpmaskmov%LW",   { Mx, Vex, XM } },
11977   },
11978 #define NEED_MOD_TABLE
11979 #include "i386-dis-evex.h"
11980 #undef NEED_MOD_TABLE
11981 };
11982
11983 static const struct dis386 rm_table[][8] = {
11984   {
11985     /* RM_C6_REG_7 */
11986     { "xabort",         { Skip_MODRM, Ib } },
11987   },
11988   {
11989     /* RM_C7_REG_7 */
11990     { "xbeginT",        { Skip_MODRM, Jv } },
11991   },
11992   {
11993     /* RM_0F01_REG_0 */
11994     { Bad_Opcode },
11995     { "vmcall",         { Skip_MODRM } },
11996     { "vmlaunch",       { Skip_MODRM } },
11997     { "vmresume",       { Skip_MODRM } },
11998     { "vmxoff",         { Skip_MODRM } },
11999   },
12000   {
12001     /* RM_0F01_REG_1 */
12002     { "monitor",        { { OP_Monitor, 0 } } },
12003     { "mwait",          { { OP_Mwait, 0 } } },
12004     { "clac",           { Skip_MODRM } },
12005     { "stac",           { Skip_MODRM } },
12006     { Bad_Opcode },
12007     { Bad_Opcode },
12008     { Bad_Opcode },
12009     { "encls",          { Skip_MODRM } },
12010   },
12011   {
12012     /* RM_0F01_REG_2 */
12013     { "xgetbv",         { Skip_MODRM } },
12014     { "xsetbv",         { Skip_MODRM } },
12015     { Bad_Opcode },
12016     { Bad_Opcode },
12017     { "vmfunc",         { Skip_MODRM } },
12018     { "xend",           { Skip_MODRM } },
12019     { "xtest",          { Skip_MODRM } },
12020     { "enclu",          { Skip_MODRM } },
12021   },
12022   {
12023     /* RM_0F01_REG_3 */
12024     { "vmrun",          { Skip_MODRM } },
12025     { "vmmcall",        { Skip_MODRM } },
12026     { "vmload",         { Skip_MODRM } },
12027     { "vmsave",         { Skip_MODRM } },
12028     { "stgi",           { Skip_MODRM } },
12029     { "clgi",           { Skip_MODRM } },
12030     { "skinit",         { Skip_MODRM } },
12031     { "invlpga",        { Skip_MODRM } },
12032   },
12033   {
12034     /* RM_0F01_REG_7 */
12035     { "swapgs",         { Skip_MODRM } },
12036     { "rdtscp",         { Skip_MODRM } },
12037   },
12038   {
12039     /* RM_0FAE_REG_5 */
12040     { "lfence",         { Skip_MODRM } },
12041   },
12042   {
12043     /* RM_0FAE_REG_6 */
12044     { "mfence",         { Skip_MODRM } },
12045   },
12046   {
12047     /* RM_0FAE_REG_7 */
12048     { PREFIX_TABLE (PREFIX_RM_0_0FAE_REG_7) },
12049   },
12050 };
12051
12052 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
12053
12054 /* We use the high bit to indicate different name for the same
12055    prefix.  */
12056 #define REP_PREFIX      (0xf3 | 0x100)
12057 #define XACQUIRE_PREFIX (0xf2 | 0x200)
12058 #define XRELEASE_PREFIX (0xf3 | 0x400)
12059 #define BND_PREFIX      (0xf2 | 0x400)
12060
12061 static int
12062 ckprefix (void)
12063 {
12064   int newrex, i, length;
12065   rex = 0;
12066   rex_ignored = 0;
12067   prefixes = 0;
12068   used_prefixes = 0;
12069   rex_used = 0;
12070   last_lock_prefix = -1;
12071   last_repz_prefix = -1;
12072   last_repnz_prefix = -1;
12073   last_data_prefix = -1;
12074   last_addr_prefix = -1;
12075   last_rex_prefix = -1;
12076   last_seg_prefix = -1;
12077   fwait_prefix = -1;
12078   active_seg_prefix = 0;
12079   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12080     all_prefixes[i] = 0;
12081   i = 0;
12082   length = 0;
12083   /* The maximum instruction length is 15bytes.  */
12084   while (length < MAX_CODE_LENGTH - 1)
12085     {
12086       FETCH_DATA (the_info, codep + 1);
12087       newrex = 0;
12088       switch (*codep)
12089         {
12090         /* REX prefixes family.  */
12091         case 0x40:
12092         case 0x41:
12093         case 0x42:
12094         case 0x43:
12095         case 0x44:
12096         case 0x45:
12097         case 0x46:
12098         case 0x47:
12099         case 0x48:
12100         case 0x49:
12101         case 0x4a:
12102         case 0x4b:
12103         case 0x4c:
12104         case 0x4d:
12105         case 0x4e:
12106         case 0x4f:
12107           if (address_mode == mode_64bit)
12108             newrex = *codep;
12109           else
12110             return 1;
12111           last_rex_prefix = i;
12112           break;
12113         case 0xf3:
12114           prefixes |= PREFIX_REPZ;
12115           last_repz_prefix = i;
12116           break;
12117         case 0xf2:
12118           prefixes |= PREFIX_REPNZ;
12119           last_repnz_prefix = i;
12120           break;
12121         case 0xf0:
12122           prefixes |= PREFIX_LOCK;
12123           last_lock_prefix = i;
12124           break;
12125         case 0x2e:
12126           prefixes |= PREFIX_CS;
12127           last_seg_prefix = i;
12128           active_seg_prefix = PREFIX_CS;
12129           break;
12130         case 0x36:
12131           prefixes |= PREFIX_SS;
12132           last_seg_prefix = i;
12133           active_seg_prefix = PREFIX_SS;
12134           break;
12135         case 0x3e:
12136           prefixes |= PREFIX_DS;
12137           last_seg_prefix = i;
12138           active_seg_prefix = PREFIX_DS;
12139           break;
12140         case 0x26:
12141           prefixes |= PREFIX_ES;
12142           last_seg_prefix = i;
12143           active_seg_prefix = PREFIX_ES;
12144           break;
12145         case 0x64:
12146           prefixes |= PREFIX_FS;
12147           last_seg_prefix = i;
12148           active_seg_prefix = PREFIX_FS;
12149           break;
12150         case 0x65:
12151           prefixes |= PREFIX_GS;
12152           last_seg_prefix = i;
12153           active_seg_prefix = PREFIX_GS;
12154           break;
12155         case 0x66:
12156           prefixes |= PREFIX_DATA;
12157           last_data_prefix = i;
12158           break;
12159         case 0x67:
12160           prefixes |= PREFIX_ADDR;
12161           last_addr_prefix = i;
12162           break;
12163         case FWAIT_OPCODE:
12164           /* fwait is really an instruction.  If there are prefixes
12165              before the fwait, they belong to the fwait, *not* to the
12166              following instruction.  */
12167           fwait_prefix = i;
12168           if (prefixes || rex)
12169             {
12170               prefixes |= PREFIX_FWAIT;
12171               codep++;
12172               /* This ensures that the previous REX prefixes are noticed
12173                  as unused prefixes, as in the return case below.  */
12174               rex_used = rex;
12175               return 1;
12176             }
12177           prefixes = PREFIX_FWAIT;
12178           break;
12179         default:
12180           return 1;
12181         }
12182       /* Rex is ignored when followed by another prefix.  */
12183       if (rex)
12184         {
12185           rex_used = rex;
12186           return 1;
12187         }
12188       if (*codep != FWAIT_OPCODE)
12189         all_prefixes[i++] = *codep;
12190       rex = newrex;
12191       codep++;
12192       length++;
12193     }
12194   return 0;
12195 }
12196
12197 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
12198    prefix byte.  */
12199
12200 static const char *
12201 prefix_name (int pref, int sizeflag)
12202 {
12203   static const char *rexes [16] =
12204     {
12205       "rex",            /* 0x40 */
12206       "rex.B",          /* 0x41 */
12207       "rex.X",          /* 0x42 */
12208       "rex.XB",         /* 0x43 */
12209       "rex.R",          /* 0x44 */
12210       "rex.RB",         /* 0x45 */
12211       "rex.RX",         /* 0x46 */
12212       "rex.RXB",        /* 0x47 */
12213       "rex.W",          /* 0x48 */
12214       "rex.WB",         /* 0x49 */
12215       "rex.WX",         /* 0x4a */
12216       "rex.WXB",        /* 0x4b */
12217       "rex.WR",         /* 0x4c */
12218       "rex.WRB",        /* 0x4d */
12219       "rex.WRX",        /* 0x4e */
12220       "rex.WRXB",       /* 0x4f */
12221     };
12222
12223   switch (pref)
12224     {
12225     /* REX prefixes family.  */
12226     case 0x40:
12227     case 0x41:
12228     case 0x42:
12229     case 0x43:
12230     case 0x44:
12231     case 0x45:
12232     case 0x46:
12233     case 0x47:
12234     case 0x48:
12235     case 0x49:
12236     case 0x4a:
12237     case 0x4b:
12238     case 0x4c:
12239     case 0x4d:
12240     case 0x4e:
12241     case 0x4f:
12242       return rexes [pref - 0x40];
12243     case 0xf3:
12244       return "repz";
12245     case 0xf2:
12246       return "repnz";
12247     case 0xf0:
12248       return "lock";
12249     case 0x2e:
12250       return "cs";
12251     case 0x36:
12252       return "ss";
12253     case 0x3e:
12254       return "ds";
12255     case 0x26:
12256       return "es";
12257     case 0x64:
12258       return "fs";
12259     case 0x65:
12260       return "gs";
12261     case 0x66:
12262       return (sizeflag & DFLAG) ? "data16" : "data32";
12263     case 0x67:
12264       if (address_mode == mode_64bit)
12265         return (sizeflag & AFLAG) ? "addr32" : "addr64";
12266       else
12267         return (sizeflag & AFLAG) ? "addr16" : "addr32";
12268     case FWAIT_OPCODE:
12269       return "fwait";
12270     case REP_PREFIX:
12271       return "rep";
12272     case XACQUIRE_PREFIX:
12273       return "xacquire";
12274     case XRELEASE_PREFIX:
12275       return "xrelease";
12276     case BND_PREFIX:
12277       return "bnd";
12278     default:
12279       return NULL;
12280     }
12281 }
12282
12283 static char op_out[MAX_OPERANDS][100];
12284 static int op_ad, op_index[MAX_OPERANDS];
12285 static int two_source_ops;
12286 static bfd_vma op_address[MAX_OPERANDS];
12287 static bfd_vma op_riprel[MAX_OPERANDS];
12288 static bfd_vma start_pc;
12289
12290 /*
12291  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
12292  *   (see topic "Redundant prefixes" in the "Differences from 8086"
12293  *   section of the "Virtual 8086 Mode" chapter.)
12294  * 'pc' should be the address of this instruction, it will
12295  *   be used to print the target address if this is a relative jump or call
12296  * The function returns the length of this instruction in bytes.
12297  */
12298
12299 static char intel_syntax;
12300 static char intel_mnemonic = !SYSV386_COMPAT;
12301 static char open_char;
12302 static char close_char;
12303 static char separator_char;
12304 static char scale_char;
12305
12306 /* Here for backwards compatibility.  When gdb stops using
12307    print_insn_i386_att and print_insn_i386_intel these functions can
12308    disappear, and print_insn_i386 be merged into print_insn.  */
12309 int
12310 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
12311 {
12312   intel_syntax = 0;
12313
12314   return print_insn (pc, info);
12315 }
12316
12317 int
12318 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
12319 {
12320   intel_syntax = 1;
12321
12322   return print_insn (pc, info);
12323 }
12324
12325 int
12326 print_insn_i386 (bfd_vma pc, disassemble_info *info)
12327 {
12328   intel_syntax = -1;
12329
12330   return print_insn (pc, info);
12331 }
12332
12333 void
12334 print_i386_disassembler_options (FILE *stream)
12335 {
12336   fprintf (stream, _("\n\
12337 The following i386/x86-64 specific disassembler options are supported for use\n\
12338 with the -M switch (multiple options should be separated by commas):\n"));
12339
12340   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
12341   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
12342   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
12343   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
12344   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
12345   fprintf (stream, _("  att-mnemonic\n"
12346                      "              Display instruction in AT&T mnemonic\n"));
12347   fprintf (stream, _("  intel-mnemonic\n"
12348                      "              Display instruction in Intel mnemonic\n"));
12349   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
12350   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
12351   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
12352   fprintf (stream, _("  data32      Assume 32bit data size\n"));
12353   fprintf (stream, _("  data16      Assume 16bit data size\n"));
12354   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
12355 }
12356
12357 /* Bad opcode.  */
12358 static const struct dis386 bad_opcode = { "(bad)", { XX } };
12359
12360 /* Get a pointer to struct dis386 with a valid name.  */
12361
12362 static const struct dis386 *
12363 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
12364 {
12365   int vindex, vex_table_index;
12366
12367   if (dp->name != NULL)
12368     return dp;
12369
12370   switch (dp->op[0].bytemode)
12371     {
12372     case USE_REG_TABLE:
12373       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
12374       break;
12375
12376     case USE_MOD_TABLE:
12377       vindex = modrm.mod == 0x3 ? 1 : 0;
12378       dp = &mod_table[dp->op[1].bytemode][vindex];
12379       break;
12380
12381     case USE_RM_TABLE:
12382       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
12383       break;
12384
12385     case USE_PREFIX_TABLE:
12386       if (need_vex)
12387         {
12388           /* The prefix in VEX is implicit.  */
12389           switch (vex.prefix)
12390             {
12391             case 0:
12392               vindex = 0;
12393               break;
12394             case REPE_PREFIX_OPCODE:
12395               vindex = 1;
12396               break;
12397             case DATA_PREFIX_OPCODE:
12398               vindex = 2;
12399               break;
12400             case REPNE_PREFIX_OPCODE:
12401               vindex = 3;
12402               break;
12403             default:
12404               abort ();
12405               break;
12406             }
12407         }
12408       else
12409         {
12410           int last_prefix = -1;
12411           int prefix = 0;
12412           vindex = 0;
12413           /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
12414              When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
12415              last one wins.  */
12416           if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
12417             {
12418               if (last_repz_prefix > last_repnz_prefix)
12419                 {
12420                   vindex = 1;
12421                   prefix = PREFIX_REPZ;
12422                   last_prefix = last_repz_prefix;
12423                 }
12424               else
12425                 {
12426                   vindex = 3;
12427                   prefix = PREFIX_REPNZ;
12428                   last_prefix = last_repnz_prefix;
12429                 }
12430
12431               /* Ignore the invalid index if it isn't mandatory.  */
12432               if (!mandatory_prefix
12433                   && (prefix_table[dp->op[1].bytemode][vindex].name
12434                       == NULL)
12435                   && (prefix_table[dp->op[1].bytemode][vindex].op[0].bytemode
12436                       == 0))
12437                 vindex = 0;
12438             }
12439
12440           if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
12441             {
12442               vindex = 2;
12443               prefix = PREFIX_DATA;
12444               last_prefix = last_data_prefix;
12445             }
12446
12447           if (vindex != 0)
12448             {
12449               used_prefixes |= prefix;
12450               all_prefixes[last_prefix] = 0;
12451             }
12452         }
12453       dp = &prefix_table[dp->op[1].bytemode][vindex];
12454       break;
12455
12456     case USE_X86_64_TABLE:
12457       vindex = address_mode == mode_64bit ? 1 : 0;
12458       dp = &x86_64_table[dp->op[1].bytemode][vindex];
12459       break;
12460
12461     case USE_3BYTE_TABLE:
12462       FETCH_DATA (info, codep + 2);
12463       vindex = *codep++;
12464       dp = &three_byte_table[dp->op[1].bytemode][vindex];
12465       end_codep = codep;
12466       modrm.mod = (*codep >> 6) & 3;
12467       modrm.reg = (*codep >> 3) & 7;
12468       modrm.rm = *codep & 7;
12469       break;
12470
12471     case USE_VEX_LEN_TABLE:
12472       if (!need_vex)
12473         abort ();
12474
12475       switch (vex.length)
12476         {
12477         case 128:
12478           vindex = 0;
12479           break;
12480         case 256:
12481           vindex = 1;
12482           break;
12483         default:
12484           abort ();
12485           break;
12486         }
12487
12488       dp = &vex_len_table[dp->op[1].bytemode][vindex];
12489       break;
12490
12491     case USE_XOP_8F_TABLE:
12492       FETCH_DATA (info, codep + 3);
12493       /* All bits in the REX prefix are ignored.  */
12494       rex_ignored = rex;
12495       rex = ~(*codep >> 5) & 0x7;
12496
12497       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
12498       switch ((*codep & 0x1f))
12499         {
12500         default:
12501           dp = &bad_opcode;
12502           return dp;
12503         case 0x8:
12504           vex_table_index = XOP_08;
12505           break;
12506         case 0x9:
12507           vex_table_index = XOP_09;
12508           break;
12509         case 0xa:
12510           vex_table_index = XOP_0A;
12511           break;
12512         }
12513       codep++;
12514       vex.w = *codep & 0x80;
12515       if (vex.w && address_mode == mode_64bit)
12516         rex |= REX_W;
12517
12518       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12519       if (address_mode != mode_64bit
12520           && vex.register_specifier > 0x7)
12521         {
12522           dp = &bad_opcode;
12523           return dp;
12524         }
12525
12526       vex.length = (*codep & 0x4) ? 256 : 128;
12527       switch ((*codep & 0x3))
12528         {
12529         case 0:
12530           vex.prefix = 0;
12531           break;
12532         case 1:
12533           vex.prefix = DATA_PREFIX_OPCODE;
12534           break;
12535         case 2:
12536           vex.prefix = REPE_PREFIX_OPCODE;
12537           break;
12538         case 3:
12539           vex.prefix = REPNE_PREFIX_OPCODE;
12540           break;
12541         }
12542       need_vex = 1;
12543       need_vex_reg = 1;
12544       codep++;
12545       vindex = *codep++;
12546       dp = &xop_table[vex_table_index][vindex];
12547
12548       end_codep = codep;
12549       FETCH_DATA (info, codep + 1);
12550       modrm.mod = (*codep >> 6) & 3;
12551       modrm.reg = (*codep >> 3) & 7;
12552       modrm.rm = *codep & 7;
12553       break;
12554
12555     case USE_VEX_C4_TABLE:
12556       /* VEX prefix.  */
12557       FETCH_DATA (info, codep + 3);
12558       /* All bits in the REX prefix are ignored.  */
12559       rex_ignored = rex;
12560       rex = ~(*codep >> 5) & 0x7;
12561       switch ((*codep & 0x1f))
12562         {
12563         default:
12564           dp = &bad_opcode;
12565           return dp;
12566         case 0x1:
12567           vex_table_index = VEX_0F;
12568           break;
12569         case 0x2:
12570           vex_table_index = VEX_0F38;
12571           break;
12572         case 0x3:
12573           vex_table_index = VEX_0F3A;
12574           break;
12575         }
12576       codep++;
12577       vex.w = *codep & 0x80;
12578       if (vex.w && address_mode == mode_64bit)
12579         rex |= REX_W;
12580
12581       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12582       if (address_mode != mode_64bit
12583           && vex.register_specifier > 0x7)
12584         {
12585           dp = &bad_opcode;
12586           return dp;
12587         }
12588
12589       vex.length = (*codep & 0x4) ? 256 : 128;
12590       switch ((*codep & 0x3))
12591         {
12592         case 0:
12593           vex.prefix = 0;
12594           break;
12595         case 1:
12596           vex.prefix = DATA_PREFIX_OPCODE;
12597           break;
12598         case 2:
12599           vex.prefix = REPE_PREFIX_OPCODE;
12600           break;
12601         case 3:
12602           vex.prefix = REPNE_PREFIX_OPCODE;
12603           break;
12604         }
12605       need_vex = 1;
12606       need_vex_reg = 1;
12607       codep++;
12608       vindex = *codep++;
12609       dp = &vex_table[vex_table_index][vindex];
12610       end_codep = codep;
12611       /* There is no MODRM byte for VEX [82|77].  */
12612       if (vindex != 0x77 && vindex != 0x82)
12613         {
12614           FETCH_DATA (info, codep + 1);
12615           modrm.mod = (*codep >> 6) & 3;
12616           modrm.reg = (*codep >> 3) & 7;
12617           modrm.rm = *codep & 7;
12618         }
12619       break;
12620
12621     case USE_VEX_C5_TABLE:
12622       /* VEX prefix.  */
12623       FETCH_DATA (info, codep + 2);
12624       /* All bits in the REX prefix are ignored.  */
12625       rex_ignored = rex;
12626       rex = (*codep & 0x80) ? 0 : REX_R;
12627
12628       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12629       if (address_mode != mode_64bit
12630           && vex.register_specifier > 0x7)
12631         {
12632           dp = &bad_opcode;
12633           return dp;
12634         }
12635
12636       vex.w = 0;
12637
12638       vex.length = (*codep & 0x4) ? 256 : 128;
12639       switch ((*codep & 0x3))
12640         {
12641         case 0:
12642           vex.prefix = 0;
12643           break;
12644         case 1:
12645           vex.prefix = DATA_PREFIX_OPCODE;
12646           break;
12647         case 2:
12648           vex.prefix = REPE_PREFIX_OPCODE;
12649           break;
12650         case 3:
12651           vex.prefix = REPNE_PREFIX_OPCODE;
12652           break;
12653         }
12654       need_vex = 1;
12655       need_vex_reg = 1;
12656       codep++;
12657       vindex = *codep++;
12658       dp = &vex_table[dp->op[1].bytemode][vindex];
12659       end_codep = codep;
12660       /* There is no MODRM byte for VEX [82|77].  */
12661       if (vindex != 0x77 && vindex != 0x82)
12662         {
12663           FETCH_DATA (info, codep + 1);
12664           modrm.mod = (*codep >> 6) & 3;
12665           modrm.reg = (*codep >> 3) & 7;
12666           modrm.rm = *codep & 7;
12667         }
12668       break;
12669
12670     case USE_VEX_W_TABLE:
12671       if (!need_vex)
12672         abort ();
12673
12674       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
12675       break;
12676
12677     case USE_EVEX_TABLE:
12678       two_source_ops = 0;
12679       /* EVEX prefix.  */
12680       vex.evex = 1;
12681       FETCH_DATA (info, codep + 4);
12682       /* All bits in the REX prefix are ignored.  */
12683       rex_ignored = rex;
12684       /* The first byte after 0x62.  */
12685       rex = ~(*codep >> 5) & 0x7;
12686       vex.r = *codep & 0x10;
12687       switch ((*codep & 0xf))
12688         {
12689         default:
12690           return &bad_opcode;
12691         case 0x1:
12692           vex_table_index = EVEX_0F;
12693           break;
12694         case 0x2:
12695           vex_table_index = EVEX_0F38;
12696           break;
12697         case 0x3:
12698           vex_table_index = EVEX_0F3A;
12699           break;
12700         }
12701
12702       /* The second byte after 0x62.  */
12703       codep++;
12704       vex.w = *codep & 0x80;
12705       if (vex.w && address_mode == mode_64bit)
12706         rex |= REX_W;
12707
12708       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12709       if (address_mode != mode_64bit)
12710         {
12711           /* In 16/32-bit mode silently ignore following bits.  */
12712           rex &= ~REX_B;
12713           vex.r = 1;
12714           vex.v = 1;
12715           vex.register_specifier &= 0x7;
12716         }
12717
12718       /* The U bit.  */
12719       if (!(*codep & 0x4))
12720         return &bad_opcode;
12721
12722       switch ((*codep & 0x3))
12723         {
12724         case 0:
12725           vex.prefix = 0;
12726           break;
12727         case 1:
12728           vex.prefix = DATA_PREFIX_OPCODE;
12729           break;
12730         case 2:
12731           vex.prefix = REPE_PREFIX_OPCODE;
12732           break;
12733         case 3:
12734           vex.prefix = REPNE_PREFIX_OPCODE;
12735           break;
12736         }
12737
12738       /* The third byte after 0x62.  */
12739       codep++;
12740
12741       /* Remember the static rounding bits.  */
12742       vex.ll = (*codep >> 5) & 3;
12743       vex.b = (*codep & 0x10) != 0;
12744
12745       vex.v = *codep & 0x8;
12746       vex.mask_register_specifier = *codep & 0x7;
12747       vex.zeroing = *codep & 0x80;
12748
12749       need_vex = 1;
12750       need_vex_reg = 1;
12751       codep++;
12752       vindex = *codep++;
12753       dp = &evex_table[vex_table_index][vindex];
12754       end_codep = codep;
12755       FETCH_DATA (info, codep + 1);
12756       modrm.mod = (*codep >> 6) & 3;
12757       modrm.reg = (*codep >> 3) & 7;
12758       modrm.rm = *codep & 7;
12759
12760       /* Set vector length.  */
12761       if (modrm.mod == 3 && vex.b)
12762         vex.length = 512;
12763       else
12764         {
12765           switch (vex.ll)
12766             {
12767             case 0x0:
12768               vex.length = 128;
12769               break;
12770             case 0x1:
12771               vex.length = 256;
12772               break;
12773             case 0x2:
12774               vex.length = 512;
12775               break;
12776             default:
12777               return &bad_opcode;
12778             }
12779         }
12780       break;
12781
12782     case 0:
12783       dp = &bad_opcode;
12784       break;
12785
12786     default:
12787       abort ();
12788     }
12789
12790   if (dp->name != NULL)
12791     return dp;
12792   else
12793     return get_valid_dis386 (dp, info);
12794 }
12795
12796 static void
12797 get_sib (disassemble_info *info, int sizeflag)
12798 {
12799   /* If modrm.mod == 3, operand must be register.  */
12800   if (need_modrm
12801       && ((sizeflag & AFLAG) || address_mode == mode_64bit)
12802       && modrm.mod != 3
12803       && modrm.rm == 4)
12804     {
12805       FETCH_DATA (info, codep + 2);
12806       sib.index = (codep [1] >> 3) & 7;
12807       sib.scale = (codep [1] >> 6) & 3;
12808       sib.base = codep [1] & 7;
12809     }
12810 }
12811
12812 static int
12813 print_insn (bfd_vma pc, disassemble_info *info)
12814 {
12815   const struct dis386 *dp;
12816   int i;
12817   char *op_txt[MAX_OPERANDS];
12818   int needcomma;
12819   int sizeflag, orig_sizeflag;
12820   const char *p;
12821   struct dis_private priv;
12822   int prefix_length;
12823
12824   priv.orig_sizeflag = AFLAG | DFLAG;
12825   if ((info->mach & bfd_mach_i386_i386) != 0)
12826     address_mode = mode_32bit;
12827   else if (info->mach == bfd_mach_i386_i8086)
12828     {
12829       address_mode = mode_16bit;
12830       priv.orig_sizeflag = 0;
12831     }
12832   else
12833     address_mode = mode_64bit;
12834
12835   if (intel_syntax == (char) -1)
12836     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
12837
12838   for (p = info->disassembler_options; p != NULL; )
12839     {
12840       if (CONST_STRNEQ (p, "x86-64"))
12841         {
12842           address_mode = mode_64bit;
12843           priv.orig_sizeflag = AFLAG | DFLAG;
12844         }
12845       else if (CONST_STRNEQ (p, "i386"))
12846         {
12847           address_mode = mode_32bit;
12848           priv.orig_sizeflag = AFLAG | DFLAG;
12849         }
12850       else if (CONST_STRNEQ (p, "i8086"))
12851         {
12852           address_mode = mode_16bit;
12853           priv.orig_sizeflag = 0;
12854         }
12855       else if (CONST_STRNEQ (p, "intel"))
12856         {
12857           intel_syntax = 1;
12858           if (CONST_STRNEQ (p + 5, "-mnemonic"))
12859             intel_mnemonic = 1;
12860         }
12861       else if (CONST_STRNEQ (p, "att"))
12862         {
12863           intel_syntax = 0;
12864           if (CONST_STRNEQ (p + 3, "-mnemonic"))
12865             intel_mnemonic = 0;
12866         }
12867       else if (CONST_STRNEQ (p, "addr"))
12868         {
12869           if (address_mode == mode_64bit)
12870             {
12871               if (p[4] == '3' && p[5] == '2')
12872                 priv.orig_sizeflag &= ~AFLAG;
12873               else if (p[4] == '6' && p[5] == '4')
12874                 priv.orig_sizeflag |= AFLAG;
12875             }
12876           else
12877             {
12878               if (p[4] == '1' && p[5] == '6')
12879                 priv.orig_sizeflag &= ~AFLAG;
12880               else if (p[4] == '3' && p[5] == '2')
12881                 priv.orig_sizeflag |= AFLAG;
12882             }
12883         }
12884       else if (CONST_STRNEQ (p, "data"))
12885         {
12886           if (p[4] == '1' && p[5] == '6')
12887             priv.orig_sizeflag &= ~DFLAG;
12888           else if (p[4] == '3' && p[5] == '2')
12889             priv.orig_sizeflag |= DFLAG;
12890         }
12891       else if (CONST_STRNEQ (p, "suffix"))
12892         priv.orig_sizeflag |= SUFFIX_ALWAYS;
12893
12894       p = strchr (p, ',');
12895       if (p != NULL)
12896         p++;
12897     }
12898
12899   if (intel_syntax)
12900     {
12901       names64 = intel_names64;
12902       names32 = intel_names32;
12903       names16 = intel_names16;
12904       names8 = intel_names8;
12905       names8rex = intel_names8rex;
12906       names_seg = intel_names_seg;
12907       names_mm = intel_names_mm;
12908       names_bnd = intel_names_bnd;
12909       names_xmm = intel_names_xmm;
12910       names_ymm = intel_names_ymm;
12911       names_zmm = intel_names_zmm;
12912       index64 = intel_index64;
12913       index32 = intel_index32;
12914       names_mask = intel_names_mask;
12915       index16 = intel_index16;
12916       open_char = '[';
12917       close_char = ']';
12918       separator_char = '+';
12919       scale_char = '*';
12920     }
12921   else
12922     {
12923       names64 = att_names64;
12924       names32 = att_names32;
12925       names16 = att_names16;
12926       names8 = att_names8;
12927       names8rex = att_names8rex;
12928       names_seg = att_names_seg;
12929       names_mm = att_names_mm;
12930       names_bnd = att_names_bnd;
12931       names_xmm = att_names_xmm;
12932       names_ymm = att_names_ymm;
12933       names_zmm = att_names_zmm;
12934       index64 = att_index64;
12935       index32 = att_index32;
12936       names_mask = att_names_mask;
12937       index16 = att_index16;
12938       open_char = '(';
12939       close_char =  ')';
12940       separator_char = ',';
12941       scale_char = ',';
12942     }
12943
12944   /* The output looks better if we put 7 bytes on a line, since that
12945      puts most long word instructions on a single line.  Use 8 bytes
12946      for Intel L1OM.  */
12947   if ((info->mach & bfd_mach_l1om) != 0)
12948     info->bytes_per_line = 8;
12949   else
12950     info->bytes_per_line = 7;
12951
12952   info->private_data = &priv;
12953   priv.max_fetched = priv.the_buffer;
12954   priv.insn_start = pc;
12955
12956   obuf[0] = 0;
12957   for (i = 0; i < MAX_OPERANDS; ++i)
12958     {
12959       op_out[i][0] = 0;
12960       op_index[i] = -1;
12961     }
12962
12963   the_info = info;
12964   start_pc = pc;
12965   start_codep = priv.the_buffer;
12966   codep = priv.the_buffer;
12967
12968   if (OPCODES_SIGSETJMP (priv.bailout) != 0)
12969     {
12970       const char *name;
12971
12972       /* Getting here means we tried for data but didn't get it.  That
12973          means we have an incomplete instruction of some sort.  Just
12974          print the first byte as a prefix or a .byte pseudo-op.  */
12975       if (codep > priv.the_buffer)
12976         {
12977           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
12978           if (name != NULL)
12979             (*info->fprintf_func) (info->stream, "%s", name);
12980           else
12981             {
12982               /* Just print the first byte as a .byte instruction.  */
12983               (*info->fprintf_func) (info->stream, ".byte 0x%x",
12984                                      (unsigned int) priv.the_buffer[0]);
12985             }
12986
12987           return 1;
12988         }
12989
12990       return -1;
12991     }
12992
12993   obufp = obuf;
12994   sizeflag = priv.orig_sizeflag;
12995
12996   if (!ckprefix () || rex_used)
12997     {
12998       /* Too many prefixes or unused REX prefixes.  */
12999       for (i = 0;
13000            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
13001            i++)
13002         (*info->fprintf_func) (info->stream, "%s%s",
13003                                i == 0 ? "" : " ",
13004                                prefix_name (all_prefixes[i], sizeflag));
13005       return i;
13006     }
13007
13008   insn_codep = codep;
13009
13010   FETCH_DATA (info, codep + 1);
13011   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
13012
13013   if (((prefixes & PREFIX_FWAIT)
13014        && ((*codep < 0xd8) || (*codep > 0xdf))))
13015     {
13016       /* Handle prefixes before fwait.  */
13017       for (i = 0; i < fwait_prefix && all_prefixes[i];
13018            i++)
13019         (*info->fprintf_func) (info->stream, "%s ",
13020                                prefix_name (all_prefixes[i], sizeflag));
13021       (*info->fprintf_func) (info->stream, "fwait");
13022       return i + 1;
13023     }
13024
13025   if (*codep == 0x0f)
13026     {
13027       unsigned char threebyte;
13028       FETCH_DATA (info, codep + 2);
13029       threebyte = *++codep;
13030       dp = &dis386_twobyte[threebyte];
13031       need_modrm = twobyte_has_modrm[*codep];
13032       mandatory_prefix = twobyte_has_mandatory_prefix[*codep];
13033       codep++;
13034     }
13035   else
13036     {
13037       dp = &dis386[*codep];
13038       need_modrm = onebyte_has_modrm[*codep];
13039       mandatory_prefix = 0;
13040       codep++;
13041     }
13042
13043   /* Save sizeflag for printing the extra prefixes later before updating
13044      it for mnemonic and operand processing.  The prefix names depend
13045      only on the address mode.  */
13046   orig_sizeflag = sizeflag;
13047   if (prefixes & PREFIX_ADDR)
13048     sizeflag ^= AFLAG;
13049   if ((prefixes & PREFIX_DATA))
13050     sizeflag ^= DFLAG;
13051
13052   end_codep = codep;
13053   if (need_modrm)
13054     {
13055       FETCH_DATA (info, codep + 1);
13056       modrm.mod = (*codep >> 6) & 3;
13057       modrm.reg = (*codep >> 3) & 7;
13058       modrm.rm = *codep & 7;
13059     }
13060
13061   need_vex = 0;
13062   need_vex_reg = 0;
13063   vex_w_done = 0;
13064   vex.evex = 0;
13065
13066   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
13067     {
13068       get_sib (info, sizeflag);
13069       dofloat (sizeflag);
13070     }
13071   else
13072     {
13073       dp = get_valid_dis386 (dp, info);
13074       if (dp != NULL && putop (dp->name, sizeflag) == 0)
13075         {
13076           get_sib (info, sizeflag);
13077           for (i = 0; i < MAX_OPERANDS; ++i)
13078             {
13079               obufp = op_out[i];
13080               op_ad = MAX_OPERANDS - 1 - i;
13081               if (dp->op[i].rtn)
13082                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
13083               /* For EVEX instruction after the last operand masking
13084                  should be printed.  */
13085               if (i == 0 && vex.evex)
13086                 {
13087                   /* Don't print {%k0}.  */
13088                   if (vex.mask_register_specifier)
13089                     {
13090                       oappend ("{");
13091                       oappend (names_mask[vex.mask_register_specifier]);
13092                       oappend ("}");
13093                     }
13094                   if (vex.zeroing)
13095                     oappend ("{z}");
13096                 }
13097             }
13098         }
13099     }
13100
13101   /* Check if the REX prefix is used.  */
13102   if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)
13103     all_prefixes[last_rex_prefix] = 0;
13104
13105   /* Check if the SEG prefix is used.  */
13106   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
13107                    | PREFIX_FS | PREFIX_GS)) != 0
13108       && (used_prefixes & active_seg_prefix) != 0)
13109     all_prefixes[last_seg_prefix] = 0;
13110
13111   /* Check if the ADDR prefix is used.  */
13112   if ((prefixes & PREFIX_ADDR) != 0
13113       && (used_prefixes & PREFIX_ADDR) != 0)
13114     all_prefixes[last_addr_prefix] = 0;
13115
13116   /* Check if the DATA prefix is used.  */
13117   if ((prefixes & PREFIX_DATA) != 0
13118       && (used_prefixes & PREFIX_DATA) != 0)
13119     all_prefixes[last_data_prefix] = 0;
13120
13121   /* Print the extra prefixes.  */
13122   prefix_length = 0;
13123   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
13124     if (all_prefixes[i])
13125       {
13126         const char *name;
13127         name = prefix_name (all_prefixes[i], orig_sizeflag);
13128         if (name == NULL)
13129           abort ();
13130         prefix_length += strlen (name) + 1;
13131         (*info->fprintf_func) (info->stream, "%s ", name);
13132       }
13133
13134   /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
13135      unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
13136      used by putop and MMX/SSE operand and may be overriden by the
13137      PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
13138      separately.  */
13139   if (mandatory_prefix
13140       && dp != &bad_opcode
13141       && (((prefixes
13142             & (PREFIX_REPZ | PREFIX_REPNZ)) != 0
13143            && (used_prefixes
13144                & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
13145           || ((((prefixes
13146                  & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
13147                 == PREFIX_DATA)
13148                && (used_prefixes & PREFIX_DATA) == 0))))
13149     {
13150       (*info->fprintf_func) (info->stream, "(bad)");
13151       return end_codep - priv.the_buffer;
13152     }
13153
13154   /* Check maximum code length.  */
13155   if ((codep - start_codep) > MAX_CODE_LENGTH)
13156     {
13157       (*info->fprintf_func) (info->stream, "(bad)");
13158       return MAX_CODE_LENGTH;
13159     }
13160
13161   obufp = mnemonicendp;
13162   for (i = strlen (obuf) + prefix_length; i < 6; i++)
13163     oappend (" ");
13164   oappend (" ");
13165   (*info->fprintf_func) (info->stream, "%s", obuf);
13166
13167   /* The enter and bound instructions are printed with operands in the same
13168      order as the intel book; everything else is printed in reverse order.  */
13169   if (intel_syntax || two_source_ops)
13170     {
13171       bfd_vma riprel;
13172
13173       for (i = 0; i < MAX_OPERANDS; ++i)
13174         op_txt[i] = op_out[i];
13175
13176       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
13177         {
13178           op_ad = op_index[i];
13179           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
13180           op_index[MAX_OPERANDS - 1 - i] = op_ad;
13181           riprel = op_riprel[i];
13182           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
13183           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
13184         }
13185     }
13186   else
13187     {
13188       for (i = 0; i < MAX_OPERANDS; ++i)
13189         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
13190     }
13191
13192   needcomma = 0;
13193   for (i = 0; i < MAX_OPERANDS; ++i)
13194     if (*op_txt[i])
13195       {
13196         if (needcomma)
13197           (*info->fprintf_func) (info->stream, ",");
13198         if (op_index[i] != -1 && !op_riprel[i])
13199           (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
13200         else
13201           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
13202         needcomma = 1;
13203       }
13204
13205   for (i = 0; i < MAX_OPERANDS; i++)
13206     if (op_index[i] != -1 && op_riprel[i])
13207       {
13208         (*info->fprintf_func) (info->stream, "        # ");
13209         (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep
13210                                                 + op_address[op_index[i]]), info);
13211         break;
13212       }
13213   return codep - priv.the_buffer;
13214 }
13215
13216 static const char *float_mem[] = {
13217   /* d8 */
13218   "fadd{s|}",
13219   "fmul{s|}",
13220   "fcom{s|}",
13221   "fcomp{s|}",
13222   "fsub{s|}",
13223   "fsubr{s|}",
13224   "fdiv{s|}",
13225   "fdivr{s|}",
13226   /* d9 */
13227   "fld{s|}",
13228   "(bad)",
13229   "fst{s|}",
13230   "fstp{s|}",
13231   "fldenvIC",
13232   "fldcw",
13233   "fNstenvIC",
13234   "fNstcw",
13235   /* da */
13236   "fiadd{l|}",
13237   "fimul{l|}",
13238   "ficom{l|}",
13239   "ficomp{l|}",
13240   "fisub{l|}",
13241   "fisubr{l|}",
13242   "fidiv{l|}",
13243   "fidivr{l|}",
13244   /* db */
13245   "fild{l|}",
13246   "fisttp{l|}",
13247   "fist{l|}",
13248   "fistp{l|}",
13249   "(bad)",
13250   "fld{t||t|}",
13251   "(bad)",
13252   "fstp{t||t|}",
13253   /* dc */
13254   "fadd{l|}",
13255   "fmul{l|}",
13256   "fcom{l|}",
13257   "fcomp{l|}",
13258   "fsub{l|}",
13259   "fsubr{l|}",
13260   "fdiv{l|}",
13261   "fdivr{l|}",
13262   /* dd */
13263   "fld{l|}",
13264   "fisttp{ll|}",
13265   "fst{l||}",
13266   "fstp{l|}",
13267   "frstorIC",
13268   "(bad)",
13269   "fNsaveIC",
13270   "fNstsw",
13271   /* de */
13272   "fiadd",
13273   "fimul",
13274   "ficom",
13275   "ficomp",
13276   "fisub",
13277   "fisubr",
13278   "fidiv",
13279   "fidivr",
13280   /* df */
13281   "fild",
13282   "fisttp",
13283   "fist",
13284   "fistp",
13285   "fbld",
13286   "fild{ll|}",
13287   "fbstp",
13288   "fistp{ll|}",
13289 };
13290
13291 static const unsigned char float_mem_mode[] = {
13292   /* d8 */
13293   d_mode,
13294   d_mode,
13295   d_mode,
13296   d_mode,
13297   d_mode,
13298   d_mode,
13299   d_mode,
13300   d_mode,
13301   /* d9 */
13302   d_mode,
13303   0,
13304   d_mode,
13305   d_mode,
13306   0,
13307   w_mode,
13308   0,
13309   w_mode,
13310   /* da */
13311   d_mode,
13312   d_mode,
13313   d_mode,
13314   d_mode,
13315   d_mode,
13316   d_mode,
13317   d_mode,
13318   d_mode,
13319   /* db */
13320   d_mode,
13321   d_mode,
13322   d_mode,
13323   d_mode,
13324   0,
13325   t_mode,
13326   0,
13327   t_mode,
13328   /* dc */
13329   q_mode,
13330   q_mode,
13331   q_mode,
13332   q_mode,
13333   q_mode,
13334   q_mode,
13335   q_mode,
13336   q_mode,
13337   /* dd */
13338   q_mode,
13339   q_mode,
13340   q_mode,
13341   q_mode,
13342   0,
13343   0,
13344   0,
13345   w_mode,
13346   /* de */
13347   w_mode,
13348   w_mode,
13349   w_mode,
13350   w_mode,
13351   w_mode,
13352   w_mode,
13353   w_mode,
13354   w_mode,
13355   /* df */
13356   w_mode,
13357   w_mode,
13358   w_mode,
13359   w_mode,
13360   t_mode,
13361   q_mode,
13362   t_mode,
13363   q_mode
13364 };
13365
13366 #define ST { OP_ST, 0 }
13367 #define STi { OP_STi, 0 }
13368
13369 #define FGRPd9_2 NULL, { { NULL, 0 } }
13370 #define FGRPd9_4 NULL, { { NULL, 1 } }
13371 #define FGRPd9_5 NULL, { { NULL, 2 } }
13372 #define FGRPd9_6 NULL, { { NULL, 3 } }
13373 #define FGRPd9_7 NULL, { { NULL, 4 } }
13374 #define FGRPda_5 NULL, { { NULL, 5 } }
13375 #define FGRPdb_4 NULL, { { NULL, 6 } }
13376 #define FGRPde_3 NULL, { { NULL, 7 } }
13377 #define FGRPdf_4 NULL, { { NULL, 8 } }
13378
13379 static const struct dis386 float_reg[][8] = {
13380   /* d8 */
13381   {
13382     { "fadd",   { ST, STi } },
13383     { "fmul",   { ST, STi } },
13384     { "fcom",   { STi } },
13385     { "fcomp",  { STi } },
13386     { "fsub",   { ST, STi } },
13387     { "fsubr",  { ST, STi } },
13388     { "fdiv",   { ST, STi } },
13389     { "fdivr",  { ST, STi } },
13390   },
13391   /* d9 */
13392   {
13393     { "fld",    { STi } },
13394     { "fxch",   { STi } },
13395     { FGRPd9_2 },
13396     { Bad_Opcode },
13397     { FGRPd9_4 },
13398     { FGRPd9_5 },
13399     { FGRPd9_6 },
13400     { FGRPd9_7 },
13401   },
13402   /* da */
13403   {
13404     { "fcmovb", { ST, STi } },
13405     { "fcmove", { ST, STi } },
13406     { "fcmovbe",{ ST, STi } },
13407     { "fcmovu", { ST, STi } },
13408     { Bad_Opcode },
13409     { FGRPda_5 },
13410     { Bad_Opcode },
13411     { Bad_Opcode },
13412   },
13413   /* db */
13414   {
13415     { "fcmovnb",{ ST, STi } },
13416     { "fcmovne",{ ST, STi } },
13417     { "fcmovnbe",{ ST, STi } },
13418     { "fcmovnu",{ ST, STi } },
13419     { FGRPdb_4 },
13420     { "fucomi", { ST, STi } },
13421     { "fcomi",  { ST, STi } },
13422     { Bad_Opcode },
13423   },
13424   /* dc */
13425   {
13426     { "fadd",   { STi, ST } },
13427     { "fmul",   { STi, ST } },
13428     { Bad_Opcode },
13429     { Bad_Opcode },
13430     { "fsub!M", { STi, ST } },
13431     { "fsubM",  { STi, ST } },
13432     { "fdiv!M", { STi, ST } },
13433     { "fdivM",  { STi, ST } },
13434   },
13435   /* dd */
13436   {
13437     { "ffree",  { STi } },
13438     { Bad_Opcode },
13439     { "fst",    { STi } },
13440     { "fstp",   { STi } },
13441     { "fucom",  { STi } },
13442     { "fucomp", { STi } },
13443     { Bad_Opcode },
13444     { Bad_Opcode },
13445   },
13446   /* de */
13447   {
13448     { "faddp",  { STi, ST } },
13449     { "fmulp",  { STi, ST } },
13450     { Bad_Opcode },
13451     { FGRPde_3 },
13452     { "fsub!Mp", { STi, ST } },
13453     { "fsubMp", { STi, ST } },
13454     { "fdiv!Mp", { STi, ST } },
13455     { "fdivMp", { STi, ST } },
13456   },
13457   /* df */
13458   {
13459     { "ffreep", { STi } },
13460     { Bad_Opcode },
13461     { Bad_Opcode },
13462     { Bad_Opcode },
13463     { FGRPdf_4 },
13464     { "fucomip", { ST, STi } },
13465     { "fcomip", { ST, STi } },
13466     { Bad_Opcode },
13467   },
13468 };
13469
13470 static char *fgrps[][8] = {
13471   /* d9_2  0 */
13472   {
13473     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13474   },
13475
13476   /* d9_4  1 */
13477   {
13478     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
13479   },
13480
13481   /* d9_5  2 */
13482   {
13483     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
13484   },
13485
13486   /* d9_6  3 */
13487   {
13488     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
13489   },
13490
13491   /* d9_7  4 */
13492   {
13493     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
13494   },
13495
13496   /* da_5  5 */
13497   {
13498     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13499   },
13500
13501   /* db_4  6 */
13502   {
13503     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
13504     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
13505   },
13506
13507   /* de_3  7 */
13508   {
13509     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13510   },
13511
13512   /* df_4  8 */
13513   {
13514     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13515   },
13516 };
13517
13518 static void
13519 swap_operand (void)
13520 {
13521   mnemonicendp[0] = '.';
13522   mnemonicendp[1] = 's';
13523   mnemonicendp += 2;
13524 }
13525
13526 static void
13527 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
13528                int sizeflag ATTRIBUTE_UNUSED)
13529 {
13530   /* Skip mod/rm byte.  */
13531   MODRM_CHECK;
13532   codep++;
13533 }
13534
13535 static void
13536 dofloat (int sizeflag)
13537 {
13538   const struct dis386 *dp;
13539   unsigned char floatop;
13540
13541   floatop = codep[-1];
13542
13543   if (modrm.mod != 3)
13544     {
13545       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
13546
13547       putop (float_mem[fp_indx], sizeflag);
13548       obufp = op_out[0];
13549       op_ad = 2;
13550       OP_E (float_mem_mode[fp_indx], sizeflag);
13551       return;
13552     }
13553   /* Skip mod/rm byte.  */
13554   MODRM_CHECK;
13555   codep++;
13556
13557   dp = &float_reg[floatop - 0xd8][modrm.reg];
13558   if (dp->name == NULL)
13559     {
13560       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
13561
13562       /* Instruction fnstsw is only one with strange arg.  */
13563       if (floatop == 0xdf && codep[-1] == 0xe0)
13564         strcpy (op_out[0], names16[0]);
13565     }
13566   else
13567     {
13568       putop (dp->name, sizeflag);
13569
13570       obufp = op_out[0];
13571       op_ad = 2;
13572       if (dp->op[0].rtn)
13573         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
13574
13575       obufp = op_out[1];
13576       op_ad = 1;
13577       if (dp->op[1].rtn)
13578         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
13579     }
13580 }
13581
13582 /* Like oappend (below), but S is a string starting with '%'.
13583    In Intel syntax, the '%' is elided.  */
13584 static void
13585 oappend_maybe_intel (const char *s)
13586 {
13587   oappend (s + intel_syntax);
13588 }
13589
13590 static void
13591 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13592 {
13593   oappend_maybe_intel ("%st");
13594 }
13595
13596 static void
13597 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13598 {
13599   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
13600   oappend_maybe_intel (scratchbuf);
13601 }
13602
13603 /* Capital letters in template are macros.  */
13604 static int
13605 putop (const char *in_template, int sizeflag)
13606 {
13607   const char *p;
13608   int alt = 0;
13609   int cond = 1;
13610   unsigned int l = 0, len = 1;
13611   char last[4];
13612
13613 #define SAVE_LAST(c)                    \
13614   if (l < len && l < sizeof (last))     \
13615     last[l++] = c;                      \
13616   else                                  \
13617     abort ();
13618
13619   for (p = in_template; *p; p++)
13620     {
13621       switch (*p)
13622         {
13623         default:
13624           *obufp++ = *p;
13625           break;
13626         case '%':
13627           len++;
13628           break;
13629         case '!':
13630           cond = 0;
13631           break;
13632         case '{':
13633           alt = 0;
13634           if (intel_syntax)
13635             {
13636               while (*++p != '|')
13637                 if (*p == '}' || *p == '\0')
13638                   abort ();
13639             }
13640           /* Fall through.  */
13641         case 'I':
13642           alt = 1;
13643           continue;
13644         case '|':
13645           while (*++p != '}')
13646             {
13647               if (*p == '\0')
13648                 abort ();
13649             }
13650           break;
13651         case '}':
13652           break;
13653         case 'A':
13654           if (intel_syntax)
13655             break;
13656           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13657             *obufp++ = 'b';
13658           break;
13659         case 'B':
13660           if (l == 0 && len == 1)
13661             {
13662 case_B:
13663               if (intel_syntax)
13664                 break;
13665               if (sizeflag & SUFFIX_ALWAYS)
13666                 *obufp++ = 'b';
13667             }
13668           else
13669             {
13670               if (l != 1
13671                   || len != 2
13672                   || last[0] != 'L')
13673                 {
13674                   SAVE_LAST (*p);
13675                   break;
13676                 }
13677
13678               if (address_mode == mode_64bit
13679                   && !(prefixes & PREFIX_ADDR))
13680                 {
13681                   *obufp++ = 'a';
13682                   *obufp++ = 'b';
13683                   *obufp++ = 's';
13684                 }
13685
13686               goto case_B;
13687             }
13688           break;
13689         case 'C':
13690           if (intel_syntax && !alt)
13691             break;
13692           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
13693             {
13694               if (sizeflag & DFLAG)
13695                 *obufp++ = intel_syntax ? 'd' : 'l';
13696               else
13697                 *obufp++ = intel_syntax ? 'w' : 's';
13698               used_prefixes |= (prefixes & PREFIX_DATA);
13699             }
13700           break;
13701         case 'D':
13702           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
13703             break;
13704           USED_REX (REX_W);
13705           if (modrm.mod == 3)
13706             {
13707               if (rex & REX_W)
13708                 *obufp++ = 'q';
13709               else
13710                 {
13711                   if (sizeflag & DFLAG)
13712                     *obufp++ = intel_syntax ? 'd' : 'l';
13713                   else
13714                     *obufp++ = 'w';
13715                   used_prefixes |= (prefixes & PREFIX_DATA);
13716                 }
13717             }
13718           else
13719             *obufp++ = 'w';
13720           break;
13721         case 'E':               /* For jcxz/jecxz */
13722           if (address_mode == mode_64bit)
13723             {
13724               if (sizeflag & AFLAG)
13725                 *obufp++ = 'r';
13726               else
13727                 *obufp++ = 'e';
13728             }
13729           else
13730             if (sizeflag & AFLAG)
13731               *obufp++ = 'e';
13732           used_prefixes |= (prefixes & PREFIX_ADDR);
13733           break;
13734         case 'F':
13735           if (intel_syntax)
13736             break;
13737           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
13738             {
13739               if (sizeflag & AFLAG)
13740                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
13741               else
13742                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
13743               used_prefixes |= (prefixes & PREFIX_ADDR);
13744             }
13745           break;
13746         case 'G':
13747           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
13748             break;
13749           if ((rex & REX_W) || (sizeflag & DFLAG))
13750             *obufp++ = 'l';
13751           else
13752             *obufp++ = 'w';
13753           if (!(rex & REX_W))
13754             used_prefixes |= (prefixes & PREFIX_DATA);
13755           break;
13756         case 'H':
13757           if (intel_syntax)
13758             break;
13759           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
13760               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
13761             {
13762               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
13763               *obufp++ = ',';
13764               *obufp++ = 'p';
13765               if (prefixes & PREFIX_DS)
13766                 *obufp++ = 't';
13767               else
13768                 *obufp++ = 'n';
13769             }
13770           break;
13771         case 'J':
13772           if (intel_syntax)
13773             break;
13774           *obufp++ = 'l';
13775           break;
13776         case 'K':
13777           USED_REX (REX_W);
13778           if (rex & REX_W)
13779             *obufp++ = 'q';
13780           else
13781             *obufp++ = 'd';
13782           break;
13783         case 'Z':
13784           if (intel_syntax)
13785             break;
13786           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
13787             {
13788               *obufp++ = 'q';
13789               break;
13790             }
13791           /* Fall through.  */
13792           goto case_L;
13793         case 'L':
13794           if (l != 0 || len != 1)
13795             {
13796               SAVE_LAST (*p);
13797               break;
13798             }
13799 case_L:
13800           if (intel_syntax)
13801             break;
13802           if (sizeflag & SUFFIX_ALWAYS)
13803             *obufp++ = 'l';
13804           break;
13805         case 'M':
13806           if (intel_mnemonic != cond)
13807             *obufp++ = 'r';
13808           break;
13809         case 'N':
13810           if ((prefixes & PREFIX_FWAIT) == 0)
13811             *obufp++ = 'n';
13812           else
13813             used_prefixes |= PREFIX_FWAIT;
13814           break;
13815         case 'O':
13816           USED_REX (REX_W);
13817           if (rex & REX_W)
13818             *obufp++ = 'o';
13819           else if (intel_syntax && (sizeflag & DFLAG))
13820             *obufp++ = 'q';
13821           else
13822             *obufp++ = 'd';
13823           if (!(rex & REX_W))
13824             used_prefixes |= (prefixes & PREFIX_DATA);
13825           break;
13826         case 'T':
13827           if (!intel_syntax
13828               && address_mode == mode_64bit
13829               && ((sizeflag & DFLAG) || (rex & REX_W)))
13830             {
13831               *obufp++ = 'q';
13832               break;
13833             }
13834           /* Fall through.  */
13835           goto case_P;
13836         case 'P':
13837           if (l == 0 && len == 1)
13838             {
13839 case_P:
13840               if (intel_syntax)
13841                 {
13842                   if ((rex & REX_W) == 0
13843                       && (prefixes & PREFIX_DATA))
13844                     {
13845                       if ((sizeflag & DFLAG) == 0)
13846                         *obufp++ = 'w';
13847                       used_prefixes |= (prefixes & PREFIX_DATA);
13848                     }
13849                   break;
13850                 }
13851               if ((prefixes & PREFIX_DATA)
13852                   || (rex & REX_W)
13853                   || (sizeflag & SUFFIX_ALWAYS))
13854                 {
13855                   USED_REX (REX_W);
13856                   if (rex & REX_W)
13857                     *obufp++ = 'q';
13858                   else
13859                     {
13860                       if (sizeflag & DFLAG)
13861                         *obufp++ = 'l';
13862                       else
13863                         *obufp++ = 'w';
13864                       used_prefixes |= (prefixes & PREFIX_DATA);
13865                     }
13866                 }
13867             }
13868           else
13869             {
13870               if (l != 1 || len != 2 || last[0] != 'L')
13871                 {
13872                   SAVE_LAST (*p);
13873                   break;
13874                 }
13875
13876               if ((prefixes & PREFIX_DATA)
13877                   || (rex & REX_W)
13878                   || (sizeflag & SUFFIX_ALWAYS))
13879                 {
13880                   USED_REX (REX_W);
13881                   if (rex & REX_W)
13882                     *obufp++ = 'q';
13883                   else
13884                     {
13885                       if (sizeflag & DFLAG)
13886                         *obufp++ = intel_syntax ? 'd' : 'l';
13887                       else
13888                         *obufp++ = 'w';
13889                       used_prefixes |= (prefixes & PREFIX_DATA);
13890                     }
13891                 }
13892             }
13893           break;
13894         case 'U':
13895           if (intel_syntax)
13896             break;
13897           if (address_mode == mode_64bit
13898               && ((sizeflag & DFLAG) || (rex & REX_W)))
13899             {
13900               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13901                 *obufp++ = 'q';
13902               break;
13903             }
13904           /* Fall through.  */
13905           goto case_Q;
13906         case 'Q':
13907           if (l == 0 && len == 1)
13908             {
13909 case_Q:
13910               if (intel_syntax && !alt)
13911                 break;
13912               USED_REX (REX_W);
13913               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13914                 {
13915                   if (rex & REX_W)
13916                     *obufp++ = 'q';
13917                   else
13918                     {
13919                       if (sizeflag & DFLAG)
13920                         *obufp++ = intel_syntax ? 'd' : 'l';
13921                       else
13922                         *obufp++ = 'w';
13923                       used_prefixes |= (prefixes & PREFIX_DATA);
13924                     }
13925                 }
13926             }
13927           else
13928             {
13929               if (l != 1 || len != 2 || last[0] != 'L')
13930                 {
13931                   SAVE_LAST (*p);
13932                   break;
13933                 }
13934               if (intel_syntax
13935                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
13936                 break;
13937               if ((rex & REX_W))
13938                 {
13939                   USED_REX (REX_W);
13940                   *obufp++ = 'q';
13941                 }
13942               else
13943                 *obufp++ = 'l';
13944             }
13945           break;
13946         case 'R':
13947           USED_REX (REX_W);
13948           if (rex & REX_W)
13949             *obufp++ = 'q';
13950           else if (sizeflag & DFLAG)
13951             {
13952               if (intel_syntax)
13953                   *obufp++ = 'd';
13954               else
13955                   *obufp++ = 'l';
13956             }
13957           else
13958             *obufp++ = 'w';
13959           if (intel_syntax && !p[1]
13960               && ((rex & REX_W) || (sizeflag & DFLAG)))
13961             *obufp++ = 'e';
13962           if (!(rex & REX_W))
13963             used_prefixes |= (prefixes & PREFIX_DATA);
13964           break;
13965         case 'V':
13966           if (l == 0 && len == 1)
13967             {
13968               if (intel_syntax)
13969                 break;
13970               if (address_mode == mode_64bit
13971                   && ((sizeflag & DFLAG) || (rex & REX_W)))
13972                 {
13973                   if (sizeflag & SUFFIX_ALWAYS)
13974                     *obufp++ = 'q';
13975                   break;
13976                 }
13977             }
13978           else
13979             {
13980               if (l != 1
13981                   || len != 2
13982                   || last[0] != 'L')
13983                 {
13984                   SAVE_LAST (*p);
13985                   break;
13986                 }
13987
13988               if (rex & REX_W)
13989                 {
13990                   *obufp++ = 'a';
13991                   *obufp++ = 'b';
13992                   *obufp++ = 's';
13993                 }
13994             }
13995           /* Fall through.  */
13996           goto case_S;
13997         case 'S':
13998           if (l == 0 && len == 1)
13999             {
14000 case_S:
14001               if (intel_syntax)
14002                 break;
14003               if (sizeflag & SUFFIX_ALWAYS)
14004                 {
14005                   if (rex & REX_W)
14006                     *obufp++ = 'q';
14007                   else
14008                     {
14009                       if (sizeflag & DFLAG)
14010                         *obufp++ = 'l';
14011                       else
14012                         *obufp++ = 'w';
14013                       used_prefixes |= (prefixes & PREFIX_DATA);
14014                     }
14015                 }
14016             }
14017           else
14018             {
14019               if (l != 1
14020                   || len != 2
14021                   || last[0] != 'L')
14022                 {
14023                   SAVE_LAST (*p);
14024                   break;
14025                 }
14026
14027               if (address_mode == mode_64bit
14028                   && !(prefixes & PREFIX_ADDR))
14029                 {
14030                   *obufp++ = 'a';
14031                   *obufp++ = 'b';
14032                   *obufp++ = 's';
14033                 }
14034
14035               goto case_S;
14036             }
14037           break;
14038         case 'X':
14039           if (l != 0 || len != 1)
14040             {
14041               SAVE_LAST (*p);
14042               break;
14043             }
14044           if (need_vex && vex.prefix)
14045             {
14046               if (vex.prefix == DATA_PREFIX_OPCODE)
14047                 *obufp++ = 'd';
14048               else
14049                 *obufp++ = 's';
14050             }
14051           else
14052             {
14053               if (prefixes & PREFIX_DATA)
14054                 *obufp++ = 'd';
14055               else
14056                 *obufp++ = 's';
14057               used_prefixes |= (prefixes & PREFIX_DATA);
14058             }
14059           break;
14060         case 'Y':
14061           if (l == 0 && len == 1)
14062             {
14063               if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
14064                 break;
14065               if (rex & REX_W)
14066                 {
14067                   USED_REX (REX_W);
14068                   *obufp++ = 'q';
14069                 }
14070               break;
14071             }
14072           else
14073             {
14074               if (l != 1 || len != 2 || last[0] != 'X')
14075                 {
14076                   SAVE_LAST (*p);
14077                   break;
14078                 }
14079               if (!need_vex)
14080                 abort ();
14081               if (intel_syntax
14082                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
14083                 break;
14084               switch (vex.length)
14085                 {
14086                 case 128:
14087                   *obufp++ = 'x';
14088                   break;
14089                 case 256:
14090                   *obufp++ = 'y';
14091                   break;
14092                 default:
14093                   abort ();
14094                 }
14095             }
14096           break;
14097         case 'W':
14098           if (l == 0 && len == 1)
14099             {
14100               /* operand size flag for cwtl, cbtw */
14101               USED_REX (REX_W);
14102               if (rex & REX_W)
14103                 {
14104                   if (intel_syntax)
14105                     *obufp++ = 'd';
14106                   else
14107                     *obufp++ = 'l';
14108                 }
14109               else if (sizeflag & DFLAG)
14110                 *obufp++ = 'w';
14111               else
14112                 *obufp++ = 'b';
14113               if (!(rex & REX_W))
14114                 used_prefixes |= (prefixes & PREFIX_DATA);
14115             }
14116           else
14117             {
14118               if (l != 1
14119                   || len != 2
14120                   || (last[0] != 'X'
14121                       && last[0] != 'L'))
14122                 {
14123                   SAVE_LAST (*p);
14124                   break;
14125                 }
14126               if (!need_vex)
14127                 abort ();
14128               if (last[0] == 'X')
14129                 *obufp++ = vex.w ? 'd': 's';
14130               else
14131                 *obufp++ = vex.w ? 'q': 'd';
14132             }
14133           break;
14134         }
14135       alt = 0;
14136     }
14137   *obufp = 0;
14138   mnemonicendp = obufp;
14139   return 0;
14140 }
14141
14142 static void
14143 oappend (const char *s)
14144 {
14145   obufp = stpcpy (obufp, s);
14146 }
14147
14148 static void
14149 append_seg (void)
14150 {
14151   /* Only print the active segment register.  */
14152   if (!active_seg_prefix)
14153     return;
14154
14155   used_prefixes |= active_seg_prefix;
14156   switch (active_seg_prefix)
14157     {
14158     case PREFIX_CS:
14159       oappend_maybe_intel ("%cs:");
14160       break;
14161     case PREFIX_DS:
14162       oappend_maybe_intel ("%ds:");
14163       break;
14164     case PREFIX_SS:
14165       oappend_maybe_intel ("%ss:");
14166       break;
14167     case PREFIX_ES:
14168       oappend_maybe_intel ("%es:");
14169       break;
14170     case PREFIX_FS:
14171       oappend_maybe_intel ("%fs:");
14172       break;
14173     case PREFIX_GS:
14174       oappend_maybe_intel ("%gs:");
14175       break;
14176     default:
14177       break;
14178     }
14179 }
14180
14181 static void
14182 OP_indirE (int bytemode, int sizeflag)
14183 {
14184   if (!intel_syntax)
14185     oappend ("*");
14186   OP_E (bytemode, sizeflag);
14187 }
14188
14189 static void
14190 print_operand_value (char *buf, int hex, bfd_vma disp)
14191 {
14192   if (address_mode == mode_64bit)
14193     {
14194       if (hex)
14195         {
14196           char tmp[30];
14197           int i;
14198           buf[0] = '0';
14199           buf[1] = 'x';
14200           sprintf_vma (tmp, disp);
14201           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
14202           strcpy (buf + 2, tmp + i);
14203         }
14204       else
14205         {
14206           bfd_signed_vma v = disp;
14207           char tmp[30];
14208           int i;
14209           if (v < 0)
14210             {
14211               *(buf++) = '-';
14212               v = -disp;
14213               /* Check for possible overflow on 0x8000000000000000.  */
14214               if (v < 0)
14215                 {
14216                   strcpy (buf, "9223372036854775808");
14217                   return;
14218                 }
14219             }
14220           if (!v)
14221             {
14222               strcpy (buf, "0");
14223               return;
14224             }
14225
14226           i = 0;
14227           tmp[29] = 0;
14228           while (v)
14229             {
14230               tmp[28 - i] = (v % 10) + '0';
14231               v /= 10;
14232               i++;
14233             }
14234           strcpy (buf, tmp + 29 - i);
14235         }
14236     }
14237   else
14238     {
14239       if (hex)
14240         sprintf (buf, "0x%x", (unsigned int) disp);
14241       else
14242         sprintf (buf, "%d", (int) disp);
14243     }
14244 }
14245
14246 /* Put DISP in BUF as signed hex number.  */
14247
14248 static void
14249 print_displacement (char *buf, bfd_vma disp)
14250 {
14251   bfd_signed_vma val = disp;
14252   char tmp[30];
14253   int i, j = 0;
14254
14255   if (val < 0)
14256     {
14257       buf[j++] = '-';
14258       val = -disp;
14259
14260       /* Check for possible overflow.  */
14261       if (val < 0)
14262         {
14263           switch (address_mode)
14264             {
14265             case mode_64bit:
14266               strcpy (buf + j, "0x8000000000000000");
14267               break;
14268             case mode_32bit:
14269               strcpy (buf + j, "0x80000000");
14270               break;
14271             case mode_16bit:
14272               strcpy (buf + j, "0x8000");
14273               break;
14274             }
14275           return;
14276         }
14277     }
14278
14279   buf[j++] = '0';
14280   buf[j++] = 'x';
14281
14282   sprintf_vma (tmp, (bfd_vma) val);
14283   for (i = 0; tmp[i] == '0'; i++)
14284     continue;
14285   if (tmp[i] == '\0')
14286     i--;
14287   strcpy (buf + j, tmp + i);
14288 }
14289
14290 static void
14291 intel_operand_size (int bytemode, int sizeflag)
14292 {
14293   if (vex.evex
14294       && vex.b
14295       && (bytemode == x_mode
14296           || bytemode == evex_half_bcst_xmmq_mode))
14297     {
14298       if (vex.w)
14299         oappend ("QWORD PTR ");
14300       else
14301         oappend ("DWORD PTR ");
14302       return;
14303     }
14304   switch (bytemode)
14305     {
14306     case b_mode:
14307     case b_swap_mode:
14308     case dqb_mode:
14309     case db_mode:
14310       oappend ("BYTE PTR ");
14311       break;
14312     case w_mode:
14313     case dw_mode:
14314     case dqw_mode:
14315     case dqw_swap_mode:
14316       oappend ("WORD PTR ");
14317       break;
14318     case stack_v_mode:
14319       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14320         {
14321           oappend ("QWORD PTR ");
14322           break;
14323         }
14324       /* FALLTHRU */
14325     case v_mode:
14326     case v_swap_mode:
14327     case dq_mode:
14328       USED_REX (REX_W);
14329       if (rex & REX_W)
14330         oappend ("QWORD PTR ");
14331       else
14332         {
14333           if ((sizeflag & DFLAG) || bytemode == dq_mode)
14334             oappend ("DWORD PTR ");
14335           else
14336             oappend ("WORD PTR ");
14337           used_prefixes |= (prefixes & PREFIX_DATA);
14338         }
14339       break;
14340     case z_mode:
14341       if ((rex & REX_W) || (sizeflag & DFLAG))
14342         *obufp++ = 'D';
14343       oappend ("WORD PTR ");
14344       if (!(rex & REX_W))
14345         used_prefixes |= (prefixes & PREFIX_DATA);
14346       break;
14347     case a_mode:
14348       if (sizeflag & DFLAG)
14349         oappend ("QWORD PTR ");
14350       else
14351         oappend ("DWORD PTR ");
14352       used_prefixes |= (prefixes & PREFIX_DATA);
14353       break;
14354     case d_mode:
14355     case d_scalar_mode:
14356     case d_scalar_swap_mode:
14357     case d_swap_mode:
14358     case dqd_mode:
14359       oappend ("DWORD PTR ");
14360       break;
14361     case q_mode:
14362     case q_scalar_mode:
14363     case q_scalar_swap_mode:
14364     case q_swap_mode:
14365       oappend ("QWORD PTR ");
14366       break;
14367     case m_mode:
14368       if (address_mode == mode_64bit)
14369         oappend ("QWORD PTR ");
14370       else
14371         oappend ("DWORD PTR ");
14372       break;
14373     case f_mode:
14374       if (sizeflag & DFLAG)
14375         oappend ("FWORD PTR ");
14376       else
14377         oappend ("DWORD PTR ");
14378       used_prefixes |= (prefixes & PREFIX_DATA);
14379       break;
14380     case t_mode:
14381       oappend ("TBYTE PTR ");
14382       break;
14383     case x_mode:
14384     case x_swap_mode:
14385     case evex_x_gscat_mode:
14386     case evex_x_nobcst_mode:
14387       if (need_vex)
14388         {
14389           switch (vex.length)
14390             {
14391             case 128:
14392               oappend ("XMMWORD PTR ");
14393               break;
14394             case 256:
14395               oappend ("YMMWORD PTR ");
14396               break;
14397             case 512:
14398               oappend ("ZMMWORD PTR ");
14399               break;
14400             default:
14401               abort ();
14402             }
14403         }
14404       else
14405         oappend ("XMMWORD PTR ");
14406       break;
14407     case xmm_mode:
14408       oappend ("XMMWORD PTR ");
14409       break;
14410     case ymm_mode:
14411       oappend ("YMMWORD PTR ");
14412       break;
14413     case xmmq_mode:
14414     case evex_half_bcst_xmmq_mode:
14415       if (!need_vex)
14416         abort ();
14417
14418       switch (vex.length)
14419         {
14420         case 128:
14421           oappend ("QWORD PTR ");
14422           break;
14423         case 256:
14424           oappend ("XMMWORD PTR ");
14425           break;
14426         case 512:
14427           oappend ("YMMWORD PTR ");
14428           break;
14429         default:
14430           abort ();
14431         }
14432       break;
14433     case xmm_mb_mode:
14434       if (!need_vex)
14435         abort ();
14436
14437       switch (vex.length)
14438         {
14439         case 128:
14440         case 256:
14441         case 512:
14442           oappend ("BYTE PTR ");
14443           break;
14444         default:
14445           abort ();
14446         }
14447       break;
14448     case xmm_mw_mode:
14449       if (!need_vex)
14450         abort ();
14451
14452       switch (vex.length)
14453         {
14454         case 128:
14455         case 256:
14456         case 512:
14457           oappend ("WORD PTR ");
14458           break;
14459         default:
14460           abort ();
14461         }
14462       break;
14463     case xmm_md_mode:
14464       if (!need_vex)
14465         abort ();
14466
14467       switch (vex.length)
14468         {
14469         case 128:
14470         case 256:
14471         case 512:
14472           oappend ("DWORD PTR ");
14473           break;
14474         default:
14475           abort ();
14476         }
14477       break;
14478     case xmm_mq_mode:
14479       if (!need_vex)
14480         abort ();
14481
14482       switch (vex.length)
14483         {
14484         case 128:
14485         case 256:
14486         case 512:
14487           oappend ("QWORD PTR ");
14488           break;
14489         default:
14490           abort ();
14491         }
14492       break;
14493     case xmmdw_mode:
14494       if (!need_vex)
14495         abort ();
14496
14497       switch (vex.length)
14498         {
14499         case 128:
14500           oappend ("WORD PTR ");
14501           break;
14502         case 256:
14503           oappend ("DWORD PTR ");
14504           break;
14505         case 512:
14506           oappend ("QWORD PTR ");
14507           break;
14508         default:
14509           abort ();
14510         }
14511       break;
14512     case xmmqd_mode:
14513       if (!need_vex)
14514         abort ();
14515
14516       switch (vex.length)
14517         {
14518         case 128:
14519           oappend ("DWORD PTR ");
14520           break;
14521         case 256:
14522           oappend ("QWORD PTR ");
14523           break;
14524         case 512:
14525           oappend ("XMMWORD PTR ");
14526           break;
14527         default:
14528           abort ();
14529         }
14530       break;
14531     case ymmq_mode:
14532       if (!need_vex)
14533         abort ();
14534
14535       switch (vex.length)
14536         {
14537         case 128:
14538           oappend ("QWORD PTR ");
14539           break;
14540         case 256:
14541           oappend ("YMMWORD PTR ");
14542           break;
14543         case 512:
14544           oappend ("ZMMWORD PTR ");
14545           break;
14546         default:
14547           abort ();
14548         }
14549       break;
14550     case ymmxmm_mode:
14551       if (!need_vex)
14552         abort ();
14553
14554       switch (vex.length)
14555         {
14556         case 128:
14557         case 256:
14558           oappend ("XMMWORD PTR ");
14559           break;
14560         default:
14561           abort ();
14562         }
14563       break;
14564     case o_mode:
14565       oappend ("OWORD PTR ");
14566       break;
14567     case xmm_mdq_mode:
14568     case vex_w_dq_mode:
14569     case vex_scalar_w_dq_mode:
14570       if (!need_vex)
14571         abort ();
14572
14573       if (vex.w)
14574         oappend ("QWORD PTR ");
14575       else
14576         oappend ("DWORD PTR ");
14577       break;
14578     case vex_vsib_d_w_dq_mode:
14579     case vex_vsib_q_w_dq_mode:
14580       if (!need_vex)
14581         abort ();
14582
14583       if (!vex.evex)
14584         {
14585           if (vex.w)
14586             oappend ("QWORD PTR ");
14587           else
14588             oappend ("DWORD PTR ");
14589         }
14590       else
14591         {
14592           switch (vex.length)
14593             {
14594             case 128:
14595               oappend ("XMMWORD PTR ");
14596               break;
14597             case 256:
14598               oappend ("YMMWORD PTR ");
14599               break;
14600             case 512:
14601               oappend ("ZMMWORD PTR ");
14602               break;
14603             default:
14604               abort ();
14605             }
14606         }
14607       break;
14608     case vex_vsib_q_w_d_mode:
14609     case vex_vsib_d_w_d_mode:
14610       if (!need_vex || !vex.evex)
14611         abort ();
14612
14613       switch (vex.length)
14614         {
14615         case 128:
14616           oappend ("QWORD PTR ");
14617           break;
14618         case 256:
14619           oappend ("XMMWORD PTR ");
14620           break;
14621         case 512:
14622           oappend ("YMMWORD PTR ");
14623           break;
14624         default:
14625           abort ();
14626         }
14627
14628       break;
14629     case mask_bd_mode:
14630       if (!need_vex || vex.length != 128)
14631         abort ();
14632       if (vex.w)
14633         oappend ("DWORD PTR ");
14634       else
14635         oappend ("BYTE PTR ");
14636       break;
14637     case mask_mode:
14638       if (!need_vex)
14639         abort ();
14640       if (vex.w)
14641         oappend ("QWORD PTR ");
14642       else
14643         oappend ("WORD PTR ");
14644       break;
14645     case v_bnd_mode:
14646     default:
14647       break;
14648     }
14649 }
14650
14651 static void
14652 OP_E_register (int bytemode, int sizeflag)
14653 {
14654   int reg = modrm.rm;
14655   const char **names;
14656
14657   USED_REX (REX_B);
14658   if ((rex & REX_B))
14659     reg += 8;
14660
14661   if ((sizeflag & SUFFIX_ALWAYS)
14662       && (bytemode == b_swap_mode
14663           || bytemode == v_swap_mode
14664           || bytemode == dqw_swap_mode))
14665     swap_operand ();
14666
14667   switch (bytemode)
14668     {
14669     case b_mode:
14670     case b_swap_mode:
14671       USED_REX (0);
14672       if (rex)
14673         names = names8rex;
14674       else
14675         names = names8;
14676       break;
14677     case w_mode:
14678       names = names16;
14679       break;
14680     case d_mode:
14681     case dw_mode:
14682     case db_mode:
14683       names = names32;
14684       break;
14685     case q_mode:
14686       names = names64;
14687       break;
14688     case m_mode:
14689     case v_bnd_mode:
14690       names = address_mode == mode_64bit ? names64 : names32;
14691       break;
14692     case bnd_mode:
14693       names = names_bnd;
14694       break;
14695     case stack_v_mode:
14696       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14697         {
14698           names = names64;
14699           break;
14700         }
14701       bytemode = v_mode;
14702       /* FALLTHRU */
14703     case v_mode:
14704     case v_swap_mode:
14705     case dq_mode:
14706     case dqb_mode:
14707     case dqd_mode:
14708     case dqw_mode:
14709     case dqw_swap_mode:
14710       USED_REX (REX_W);
14711       if (rex & REX_W)
14712         names = names64;
14713       else
14714         {
14715           if ((sizeflag & DFLAG)
14716               || (bytemode != v_mode
14717                   && bytemode != v_swap_mode))
14718             names = names32;
14719           else
14720             names = names16;
14721           used_prefixes |= (prefixes & PREFIX_DATA);
14722         }
14723       break;
14724     case mask_bd_mode:
14725     case mask_mode:
14726       names = names_mask;
14727       break;
14728     case 0:
14729       return;
14730     default:
14731       oappend (INTERNAL_DISASSEMBLER_ERROR);
14732       return;
14733     }
14734   oappend (names[reg]);
14735 }
14736
14737 static void
14738 OP_E_memory (int bytemode, int sizeflag)
14739 {
14740   bfd_vma disp = 0;
14741   int add = (rex & REX_B) ? 8 : 0;
14742   int riprel = 0;
14743   int shift;
14744
14745   if (vex.evex)
14746     {
14747       /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0.  */
14748       if (vex.b
14749           && bytemode != x_mode
14750           && bytemode != xmmq_mode
14751           && bytemode != evex_half_bcst_xmmq_mode)
14752         {
14753           BadOp ();
14754           return;
14755         }
14756       switch (bytemode)
14757         {
14758         case dqw_mode:
14759         case dw_mode:
14760         case dqw_swap_mode:
14761           shift = 1;
14762           break;
14763         case dqb_mode:
14764         case db_mode:
14765           shift = 0;
14766           break;
14767         case vex_vsib_d_w_dq_mode:
14768         case vex_vsib_d_w_d_mode:
14769         case vex_vsib_q_w_dq_mode:
14770         case vex_vsib_q_w_d_mode:
14771         case evex_x_gscat_mode:
14772         case xmm_mdq_mode:
14773           shift = vex.w ? 3 : 2;
14774           break;
14775         case x_mode:
14776         case evex_half_bcst_xmmq_mode:
14777         case xmmq_mode:
14778           if (vex.b)
14779             {
14780               shift = vex.w ? 3 : 2;
14781               break;
14782             }
14783           /* Fall through if vex.b == 0.  */
14784         case xmmqd_mode:
14785         case xmmdw_mode:
14786         case ymmq_mode:
14787         case evex_x_nobcst_mode:
14788         case x_swap_mode:
14789           switch (vex.length)
14790             {
14791             case 128:
14792               shift = 4;
14793               break;
14794             case 256:
14795               shift = 5;
14796               break;
14797             case 512:
14798               shift = 6;
14799               break;
14800             default:
14801               abort ();
14802             }
14803           break;
14804         case ymm_mode:
14805           shift = 5;
14806           break;
14807         case xmm_mode:
14808           shift = 4;
14809           break;
14810         case xmm_mq_mode:
14811         case q_mode:
14812         case q_scalar_mode:
14813         case q_swap_mode:
14814         case q_scalar_swap_mode:
14815           shift = 3;
14816           break;
14817         case dqd_mode:
14818         case xmm_md_mode:
14819         case d_mode:
14820         case d_scalar_mode:
14821         case d_swap_mode:
14822         case d_scalar_swap_mode:
14823           shift = 2;
14824           break;
14825         case xmm_mw_mode:
14826           shift = 1;
14827           break;
14828         case xmm_mb_mode:
14829           shift = 0;
14830           break;
14831         default:
14832           abort ();
14833         }
14834       /* Make necessary corrections to shift for modes that need it.
14835          For these modes we currently have shift 4, 5 or 6 depending on
14836          vex.length (it corresponds to xmmword, ymmword or zmmword
14837          operand).  We might want to make it 3, 4 or 5 (e.g. for
14838          xmmq_mode).  In case of broadcast enabled the corrections
14839          aren't needed, as element size is always 32 or 64 bits.  */
14840       if (!vex.b
14841           && (bytemode == xmmq_mode
14842               || bytemode == evex_half_bcst_xmmq_mode))
14843         shift -= 1;
14844       else if (bytemode == xmmqd_mode)
14845         shift -= 2;
14846       else if (bytemode == xmmdw_mode)
14847         shift -= 3;
14848       else if (bytemode == ymmq_mode && vex.length == 128)
14849         shift -= 1;
14850     }
14851   else
14852     shift = 0;
14853
14854   USED_REX (REX_B);
14855   if (intel_syntax)
14856     intel_operand_size (bytemode, sizeflag);
14857   append_seg ();
14858
14859   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14860     {
14861       /* 32/64 bit address mode */
14862       int havedisp;
14863       int havesib;
14864       int havebase;
14865       int haveindex;
14866       int needindex;
14867       int base, rbase;
14868       int vindex = 0;
14869       int scale = 0;
14870       int addr32flag = !((sizeflag & AFLAG)
14871                          || bytemode == v_bnd_mode
14872                          || bytemode == bnd_mode);
14873       const char **indexes64 = names64;
14874       const char **indexes32 = names32;
14875
14876       havesib = 0;
14877       havebase = 1;
14878       haveindex = 0;
14879       base = modrm.rm;
14880
14881       if (base == 4)
14882         {
14883           havesib = 1;
14884           vindex = sib.index;
14885           USED_REX (REX_X);
14886           if (rex & REX_X)
14887             vindex += 8;
14888           switch (bytemode)
14889             {
14890             case vex_vsib_d_w_dq_mode:
14891             case vex_vsib_d_w_d_mode:
14892             case vex_vsib_q_w_dq_mode:
14893             case vex_vsib_q_w_d_mode:
14894               if (!need_vex)
14895                 abort ();
14896               if (vex.evex)
14897                 {
14898                   if (!vex.v)
14899                     vindex += 16;
14900                 }
14901
14902               haveindex = 1;
14903               switch (vex.length)
14904                 {
14905                 case 128:
14906                   indexes64 = indexes32 = names_xmm;
14907                   break;
14908                 case 256:
14909                   if (!vex.w
14910                       || bytemode == vex_vsib_q_w_dq_mode
14911                       || bytemode == vex_vsib_q_w_d_mode)
14912                     indexes64 = indexes32 = names_ymm;
14913                   else
14914                     indexes64 = indexes32 = names_xmm;
14915                   break;
14916                 case 512:
14917                   if (!vex.w
14918                       || bytemode == vex_vsib_q_w_dq_mode
14919                       || bytemode == vex_vsib_q_w_d_mode)
14920                     indexes64 = indexes32 = names_zmm;
14921                   else
14922                     indexes64 = indexes32 = names_ymm;
14923                   break;
14924                 default:
14925                   abort ();
14926                 }
14927               break;
14928             default:
14929               haveindex = vindex != 4;
14930               break;
14931             }
14932           scale = sib.scale;
14933           base = sib.base;
14934           codep++;
14935         }
14936       rbase = base + add;
14937
14938       switch (modrm.mod)
14939         {
14940         case 0:
14941           if (base == 5)
14942             {
14943               havebase = 0;
14944               if (address_mode == mode_64bit && !havesib)
14945                 riprel = 1;
14946               disp = get32s ();
14947             }
14948           break;
14949         case 1:
14950           FETCH_DATA (the_info, codep + 1);
14951           disp = *codep++;
14952           if ((disp & 0x80) != 0)
14953             disp -= 0x100;
14954           if (vex.evex && shift > 0)
14955             disp <<= shift;
14956           break;
14957         case 2:
14958           disp = get32s ();
14959           break;
14960         }
14961
14962       /* In 32bit mode, we need index register to tell [offset] from
14963          [eiz*1 + offset].  */
14964       needindex = (havesib
14965                    && !havebase
14966                    && !haveindex
14967                    && address_mode == mode_32bit);
14968       havedisp = (havebase
14969                   || needindex
14970                   || (havesib && (haveindex || scale != 0)));
14971
14972       if (!intel_syntax)
14973         if (modrm.mod != 0 || base == 5)
14974           {
14975             if (havedisp || riprel)
14976               print_displacement (scratchbuf, disp);
14977             else
14978               print_operand_value (scratchbuf, 1, disp);
14979             oappend (scratchbuf);
14980             if (riprel)
14981               {
14982                 set_op (disp, 1);
14983                 oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)");
14984               }
14985           }
14986
14987       if ((havebase || haveindex || riprel)
14988           && (bytemode != v_bnd_mode)
14989           && (bytemode != bnd_mode))
14990         used_prefixes |= PREFIX_ADDR;
14991
14992       if (havedisp || (intel_syntax && riprel))
14993         {
14994           *obufp++ = open_char;
14995           if (intel_syntax && riprel)
14996             {
14997               set_op (disp, 1);
14998               oappend (sizeflag & AFLAG ? "rip" : "eip");
14999             }
15000           *obufp = '\0';
15001           if (havebase)
15002             oappend (address_mode == mode_64bit && !addr32flag
15003                      ? names64[rbase] : names32[rbase]);
15004           if (havesib)
15005             {
15006               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
15007                  print index to tell base + index from base.  */
15008               if (scale != 0
15009                   || needindex
15010                   || haveindex
15011                   || (havebase && base != ESP_REG_NUM))
15012                 {
15013                   if (!intel_syntax || havebase)
15014                     {
15015                       *obufp++ = separator_char;
15016                       *obufp = '\0';
15017                     }
15018                   if (haveindex)
15019                     oappend (address_mode == mode_64bit && !addr32flag
15020                              ? indexes64[vindex] : indexes32[vindex]);
15021                   else
15022                     oappend (address_mode == mode_64bit && !addr32flag
15023                              ? index64 : index32);
15024
15025                   *obufp++ = scale_char;
15026                   *obufp = '\0';
15027                   sprintf (scratchbuf, "%d", 1 << scale);
15028                   oappend (scratchbuf);
15029                 }
15030             }
15031           if (intel_syntax
15032               && (disp || modrm.mod != 0 || base == 5))
15033             {
15034               if (!havedisp || (bfd_signed_vma) disp >= 0)
15035                 {
15036                   *obufp++ = '+';
15037                   *obufp = '\0';
15038                 }
15039               else if (modrm.mod != 1 && disp != -disp)
15040                 {
15041                   *obufp++ = '-';
15042                   *obufp = '\0';
15043                   disp = - (bfd_signed_vma) disp;
15044                 }
15045
15046               if (havedisp)
15047                 print_displacement (scratchbuf, disp);
15048               else
15049                 print_operand_value (scratchbuf, 1, disp);
15050               oappend (scratchbuf);
15051             }
15052
15053           *obufp++ = close_char;
15054           *obufp = '\0';
15055         }
15056       else if (intel_syntax)
15057         {
15058           if (modrm.mod != 0 || base == 5)
15059             {
15060               if (!active_seg_prefix)
15061                 {
15062                   oappend (names_seg[ds_reg - es_reg]);
15063                   oappend (":");
15064                 }
15065               print_operand_value (scratchbuf, 1, disp);
15066               oappend (scratchbuf);
15067             }
15068         }
15069     }
15070   else
15071     {
15072       /* 16 bit address mode */
15073       used_prefixes |= prefixes & PREFIX_ADDR;
15074       switch (modrm.mod)
15075         {
15076         case 0:
15077           if (modrm.rm == 6)
15078             {
15079               disp = get16 ();
15080               if ((disp & 0x8000) != 0)
15081                 disp -= 0x10000;
15082             }
15083           break;
15084         case 1:
15085           FETCH_DATA (the_info, codep + 1);
15086           disp = *codep++;
15087           if ((disp & 0x80) != 0)
15088             disp -= 0x100;
15089           break;
15090         case 2:
15091           disp = get16 ();
15092           if ((disp & 0x8000) != 0)
15093             disp -= 0x10000;
15094           break;
15095         }
15096
15097       if (!intel_syntax)
15098         if (modrm.mod != 0 || modrm.rm == 6)
15099           {
15100             print_displacement (scratchbuf, disp);
15101             oappend (scratchbuf);
15102           }
15103
15104       if (modrm.mod != 0 || modrm.rm != 6)
15105         {
15106           *obufp++ = open_char;
15107           *obufp = '\0';
15108           oappend (index16[modrm.rm]);
15109           if (intel_syntax
15110               && (disp || modrm.mod != 0 || modrm.rm == 6))
15111             {
15112               if ((bfd_signed_vma) disp >= 0)
15113                 {
15114                   *obufp++ = '+';
15115                   *obufp = '\0';
15116                 }
15117               else if (modrm.mod != 1)
15118                 {
15119                   *obufp++ = '-';
15120                   *obufp = '\0';
15121                   disp = - (bfd_signed_vma) disp;
15122                 }
15123
15124               print_displacement (scratchbuf, disp);
15125               oappend (scratchbuf);
15126             }
15127
15128           *obufp++ = close_char;
15129           *obufp = '\0';
15130         }
15131       else if (intel_syntax)
15132         {
15133           if (!active_seg_prefix)
15134             {
15135               oappend (names_seg[ds_reg - es_reg]);
15136               oappend (":");
15137             }
15138           print_operand_value (scratchbuf, 1, disp & 0xffff);
15139           oappend (scratchbuf);
15140         }
15141     }
15142   if (vex.evex && vex.b
15143       && (bytemode == x_mode
15144           || bytemode == xmmq_mode
15145           || bytemode == evex_half_bcst_xmmq_mode))
15146     {
15147       if (vex.w
15148           || bytemode == xmmq_mode
15149           || bytemode == evex_half_bcst_xmmq_mode)
15150         {
15151           switch (vex.length)
15152             {
15153             case 128:
15154               oappend ("{1to2}");
15155               break;
15156             case 256:
15157               oappend ("{1to4}");
15158               break;
15159             case 512:
15160               oappend ("{1to8}");
15161               break;
15162             default:
15163               abort ();
15164             }
15165         }
15166       else
15167         {
15168           switch (vex.length)
15169             {
15170             case 128:
15171               oappend ("{1to4}");
15172               break;
15173             case 256:
15174               oappend ("{1to8}");
15175               break;
15176             case 512:
15177               oappend ("{1to16}");
15178               break;
15179             default:
15180               abort ();
15181             }
15182         }
15183     }
15184 }
15185
15186 static void
15187 OP_E (int bytemode, int sizeflag)
15188 {
15189   /* Skip mod/rm byte.  */
15190   MODRM_CHECK;
15191   codep++;
15192
15193   if (modrm.mod == 3)
15194     OP_E_register (bytemode, sizeflag);
15195   else
15196     OP_E_memory (bytemode, sizeflag);
15197 }
15198
15199 static void
15200 OP_G (int bytemode, int sizeflag)
15201 {
15202   int add = 0;
15203   USED_REX (REX_R);
15204   if (rex & REX_R)
15205     add += 8;
15206   switch (bytemode)
15207     {
15208     case b_mode:
15209       USED_REX (0);
15210       if (rex)
15211         oappend (names8rex[modrm.reg + add]);
15212       else
15213         oappend (names8[modrm.reg + add]);
15214       break;
15215     case w_mode:
15216       oappend (names16[modrm.reg + add]);
15217       break;
15218     case d_mode:
15219     case db_mode:
15220     case dw_mode:
15221       oappend (names32[modrm.reg + add]);
15222       break;
15223     case q_mode:
15224       oappend (names64[modrm.reg + add]);
15225       break;
15226     case bnd_mode:
15227       oappend (names_bnd[modrm.reg]);
15228       break;
15229     case v_mode:
15230     case dq_mode:
15231     case dqb_mode:
15232     case dqd_mode:
15233     case dqw_mode:
15234     case dqw_swap_mode:
15235       USED_REX (REX_W);
15236       if (rex & REX_W)
15237         oappend (names64[modrm.reg + add]);
15238       else
15239         {
15240           if ((sizeflag & DFLAG) || bytemode != v_mode)
15241             oappend (names32[modrm.reg + add]);
15242           else
15243             oappend (names16[modrm.reg + add]);
15244           used_prefixes |= (prefixes & PREFIX_DATA);
15245         }
15246       break;
15247     case m_mode:
15248       if (address_mode == mode_64bit)
15249         oappend (names64[modrm.reg + add]);
15250       else
15251         oappend (names32[modrm.reg + add]);
15252       break;
15253     case mask_bd_mode:
15254     case mask_mode:
15255       oappend (names_mask[modrm.reg + add]);
15256       break;
15257     default:
15258       oappend (INTERNAL_DISASSEMBLER_ERROR);
15259       break;
15260     }
15261 }
15262
15263 static bfd_vma
15264 get64 (void)
15265 {
15266   bfd_vma x;
15267 #ifdef BFD64
15268   unsigned int a;
15269   unsigned int b;
15270
15271   FETCH_DATA (the_info, codep + 8);
15272   a = *codep++ & 0xff;
15273   a |= (*codep++ & 0xff) << 8;
15274   a |= (*codep++ & 0xff) << 16;
15275   a |= (*codep++ & 0xff) << 24;
15276   b = *codep++ & 0xff;
15277   b |= (*codep++ & 0xff) << 8;
15278   b |= (*codep++ & 0xff) << 16;
15279   b |= (*codep++ & 0xff) << 24;
15280   x = a + ((bfd_vma) b << 32);
15281 #else
15282   abort ();
15283   x = 0;
15284 #endif
15285   return x;
15286 }
15287
15288 static bfd_signed_vma
15289 get32 (void)
15290 {
15291   bfd_signed_vma x = 0;
15292
15293   FETCH_DATA (the_info, codep + 4);
15294   x = *codep++ & (bfd_signed_vma) 0xff;
15295   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15296   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15297   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15298   return x;
15299 }
15300
15301 static bfd_signed_vma
15302 get32s (void)
15303 {
15304   bfd_signed_vma x = 0;
15305
15306   FETCH_DATA (the_info, codep + 4);
15307   x = *codep++ & (bfd_signed_vma) 0xff;
15308   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15309   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15310   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15311
15312   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
15313
15314   return x;
15315 }
15316
15317 static int
15318 get16 (void)
15319 {
15320   int x = 0;
15321
15322   FETCH_DATA (the_info, codep + 2);
15323   x = *codep++ & 0xff;
15324   x |= (*codep++ & 0xff) << 8;
15325   return x;
15326 }
15327
15328 static void
15329 set_op (bfd_vma op, int riprel)
15330 {
15331   op_index[op_ad] = op_ad;
15332   if (address_mode == mode_64bit)
15333     {
15334       op_address[op_ad] = op;
15335       op_riprel[op_ad] = riprel;
15336     }
15337   else
15338     {
15339       /* Mask to get a 32-bit address.  */
15340       op_address[op_ad] = op & 0xffffffff;
15341       op_riprel[op_ad] = riprel & 0xffffffff;
15342     }
15343 }
15344
15345 static void
15346 OP_REG (int code, int sizeflag)
15347 {
15348   const char *s;
15349   int add;
15350
15351   switch (code)
15352     {
15353     case es_reg: case ss_reg: case cs_reg:
15354     case ds_reg: case fs_reg: case gs_reg:
15355       oappend (names_seg[code - es_reg]);
15356       return;
15357     }
15358
15359   USED_REX (REX_B);
15360   if (rex & REX_B)
15361     add = 8;
15362   else
15363     add = 0;
15364
15365   switch (code)
15366     {
15367     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15368     case sp_reg: case bp_reg: case si_reg: case di_reg:
15369       s = names16[code - ax_reg + add];
15370       break;
15371     case al_reg: case ah_reg: case cl_reg: case ch_reg:
15372     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15373       USED_REX (0);
15374       if (rex)
15375         s = names8rex[code - al_reg + add];
15376       else
15377         s = names8[code - al_reg];
15378       break;
15379     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
15380     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
15381       if (address_mode == mode_64bit
15382           && ((sizeflag & DFLAG) || (rex & REX_W)))
15383         {
15384           s = names64[code - rAX_reg + add];
15385           break;
15386         }
15387       code += eAX_reg - rAX_reg;
15388       /* Fall through.  */
15389     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15390     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15391       USED_REX (REX_W);
15392       if (rex & REX_W)
15393         s = names64[code - eAX_reg + add];
15394       else
15395         {
15396           if (sizeflag & DFLAG)
15397             s = names32[code - eAX_reg + add];
15398           else
15399             s = names16[code - eAX_reg + add];
15400           used_prefixes |= (prefixes & PREFIX_DATA);
15401         }
15402       break;
15403     default:
15404       s = INTERNAL_DISASSEMBLER_ERROR;
15405       break;
15406     }
15407   oappend (s);
15408 }
15409
15410 static void
15411 OP_IMREG (int code, int sizeflag)
15412 {
15413   const char *s;
15414
15415   switch (code)
15416     {
15417     case indir_dx_reg:
15418       if (intel_syntax)
15419         s = "dx";
15420       else
15421         s = "(%dx)";
15422       break;
15423     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15424     case sp_reg: case bp_reg: case si_reg: case di_reg:
15425       s = names16[code - ax_reg];
15426       break;
15427     case es_reg: case ss_reg: case cs_reg:
15428     case ds_reg: case fs_reg: case gs_reg:
15429       s = names_seg[code - es_reg];
15430       break;
15431     case al_reg: case ah_reg: case cl_reg: case ch_reg:
15432     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15433       USED_REX (0);
15434       if (rex)
15435         s = names8rex[code - al_reg];
15436       else
15437         s = names8[code - al_reg];
15438       break;
15439     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15440     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15441       USED_REX (REX_W);
15442       if (rex & REX_W)
15443         s = names64[code - eAX_reg];
15444       else
15445         {
15446           if (sizeflag & DFLAG)
15447             s = names32[code - eAX_reg];
15448           else
15449             s = names16[code - eAX_reg];
15450           used_prefixes |= (prefixes & PREFIX_DATA);
15451         }
15452       break;
15453     case z_mode_ax_reg:
15454       if ((rex & REX_W) || (sizeflag & DFLAG))
15455         s = *names32;
15456       else
15457         s = *names16;
15458       if (!(rex & REX_W))
15459         used_prefixes |= (prefixes & PREFIX_DATA);
15460       break;
15461     default:
15462       s = INTERNAL_DISASSEMBLER_ERROR;
15463       break;
15464     }
15465   oappend (s);
15466 }
15467
15468 static void
15469 OP_I (int bytemode, int sizeflag)
15470 {
15471   bfd_signed_vma op;
15472   bfd_signed_vma mask = -1;
15473
15474   switch (bytemode)
15475     {
15476     case b_mode:
15477       FETCH_DATA (the_info, codep + 1);
15478       op = *codep++;
15479       mask = 0xff;
15480       break;
15481     case q_mode:
15482       if (address_mode == mode_64bit)
15483         {
15484           op = get32s ();
15485           break;
15486         }
15487       /* Fall through.  */
15488     case v_mode:
15489       USED_REX (REX_W);
15490       if (rex & REX_W)
15491         op = get32s ();
15492       else
15493         {
15494           if (sizeflag & DFLAG)
15495             {
15496               op = get32 ();
15497               mask = 0xffffffff;
15498             }
15499           else
15500             {
15501               op = get16 ();
15502               mask = 0xfffff;
15503             }
15504           used_prefixes |= (prefixes & PREFIX_DATA);
15505         }
15506       break;
15507     case w_mode:
15508       mask = 0xfffff;
15509       op = get16 ();
15510       break;
15511     case const_1_mode:
15512       if (intel_syntax)
15513         oappend ("1");
15514       return;
15515     default:
15516       oappend (INTERNAL_DISASSEMBLER_ERROR);
15517       return;
15518     }
15519
15520   op &= mask;
15521   scratchbuf[0] = '$';
15522   print_operand_value (scratchbuf + 1, 1, op);
15523   oappend_maybe_intel (scratchbuf);
15524   scratchbuf[0] = '\0';
15525 }
15526
15527 static void
15528 OP_I64 (int bytemode, int sizeflag)
15529 {
15530   bfd_signed_vma op;
15531   bfd_signed_vma mask = -1;
15532
15533   if (address_mode != mode_64bit)
15534     {
15535       OP_I (bytemode, sizeflag);
15536       return;
15537     }
15538
15539   switch (bytemode)
15540     {
15541     case b_mode:
15542       FETCH_DATA (the_info, codep + 1);
15543       op = *codep++;
15544       mask = 0xff;
15545       break;
15546     case v_mode:
15547       USED_REX (REX_W);
15548       if (rex & REX_W)
15549         op = get64 ();
15550       else
15551         {
15552           if (sizeflag & DFLAG)
15553             {
15554               op = get32 ();
15555               mask = 0xffffffff;
15556             }
15557           else
15558             {
15559               op = get16 ();
15560               mask = 0xfffff;
15561             }
15562           used_prefixes |= (prefixes & PREFIX_DATA);
15563         }
15564       break;
15565     case w_mode:
15566       mask = 0xfffff;
15567       op = get16 ();
15568       break;
15569     default:
15570       oappend (INTERNAL_DISASSEMBLER_ERROR);
15571       return;
15572     }
15573
15574   op &= mask;
15575   scratchbuf[0] = '$';
15576   print_operand_value (scratchbuf + 1, 1, op);
15577   oappend_maybe_intel (scratchbuf);
15578   scratchbuf[0] = '\0';
15579 }
15580
15581 static void
15582 OP_sI (int bytemode, int sizeflag)
15583 {
15584   bfd_signed_vma op;
15585
15586   switch (bytemode)
15587     {
15588     case b_mode:
15589     case b_T_mode:
15590       FETCH_DATA (the_info, codep + 1);
15591       op = *codep++;
15592       if ((op & 0x80) != 0)
15593         op -= 0x100;
15594       if (bytemode == b_T_mode)
15595         {
15596           if (address_mode != mode_64bit
15597               || !((sizeflag & DFLAG) || (rex & REX_W)))
15598             {
15599               /* The operand-size prefix is overridden by a REX prefix.  */
15600               if ((sizeflag & DFLAG) || (rex & REX_W))
15601                 op &= 0xffffffff;
15602               else
15603                 op &= 0xffff;
15604           }
15605         }
15606       else
15607         {
15608           if (!(rex & REX_W))
15609             {
15610               if (sizeflag & DFLAG)
15611                 op &= 0xffffffff;
15612               else
15613                 op &= 0xffff;
15614             }
15615         }
15616       break;
15617     case v_mode:
15618       /* The operand-size prefix is overridden by a REX prefix.  */
15619       if ((sizeflag & DFLAG) || (rex & REX_W))
15620         op = get32s ();
15621       else
15622         op = get16 ();
15623       break;
15624     default:
15625       oappend (INTERNAL_DISASSEMBLER_ERROR);
15626       return;
15627     }
15628
15629   scratchbuf[0] = '$';
15630   print_operand_value (scratchbuf + 1, 1, op);
15631   oappend_maybe_intel (scratchbuf);
15632 }
15633
15634 static void
15635 OP_J (int bytemode, int sizeflag)
15636 {
15637   bfd_vma disp;
15638   bfd_vma mask = -1;
15639   bfd_vma segment = 0;
15640
15641   switch (bytemode)
15642     {
15643     case b_mode:
15644       FETCH_DATA (the_info, codep + 1);
15645       disp = *codep++;
15646       if ((disp & 0x80) != 0)
15647         disp -= 0x100;
15648       break;
15649     case v_mode:
15650       USED_REX (REX_W);
15651       if ((sizeflag & DFLAG) || (rex & REX_W))
15652         disp = get32s ();
15653       else
15654         {
15655           disp = get16 ();
15656           if ((disp & 0x8000) != 0)
15657             disp -= 0x10000;
15658           /* In 16bit mode, address is wrapped around at 64k within
15659              the same segment.  Otherwise, a data16 prefix on a jump
15660              instruction means that the pc is masked to 16 bits after
15661              the displacement is added!  */
15662           mask = 0xffff;
15663           if ((prefixes & PREFIX_DATA) == 0)
15664             segment = ((start_pc + codep - start_codep)
15665                        & ~((bfd_vma) 0xffff));
15666         }
15667       if (!(rex & REX_W))
15668         used_prefixes |= (prefixes & PREFIX_DATA);
15669       break;
15670     default:
15671       oappend (INTERNAL_DISASSEMBLER_ERROR);
15672       return;
15673     }
15674   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
15675   set_op (disp, 0);
15676   print_operand_value (scratchbuf, 1, disp);
15677   oappend (scratchbuf);
15678 }
15679
15680 static void
15681 OP_SEG (int bytemode, int sizeflag)
15682 {
15683   if (bytemode == w_mode)
15684     oappend (names_seg[modrm.reg]);
15685   else
15686     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
15687 }
15688
15689 static void
15690 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
15691 {
15692   int seg, offset;
15693
15694   if (sizeflag & DFLAG)
15695     {
15696       offset = get32 ();
15697       seg = get16 ();
15698     }
15699   else
15700     {
15701       offset = get16 ();
15702       seg = get16 ();
15703     }
15704   used_prefixes |= (prefixes & PREFIX_DATA);
15705   if (intel_syntax)
15706     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
15707   else
15708     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
15709   oappend (scratchbuf);
15710 }
15711
15712 static void
15713 OP_OFF (int bytemode, int sizeflag)
15714 {
15715   bfd_vma off;
15716
15717   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
15718     intel_operand_size (bytemode, sizeflag);
15719   append_seg ();
15720
15721   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
15722     off = get32 ();
15723   else
15724     off = get16 ();
15725
15726   if (intel_syntax)
15727     {
15728       if (!active_seg_prefix)
15729         {
15730           oappend (names_seg[ds_reg - es_reg]);
15731           oappend (":");
15732         }
15733     }
15734   print_operand_value (scratchbuf, 1, off);
15735   oappend (scratchbuf);
15736 }
15737
15738 static void
15739 OP_OFF64 (int bytemode, int sizeflag)
15740 {
15741   bfd_vma off;
15742
15743   if (address_mode != mode_64bit
15744       || (prefixes & PREFIX_ADDR))
15745     {
15746       OP_OFF (bytemode, sizeflag);
15747       return;
15748     }
15749
15750   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
15751     intel_operand_size (bytemode, sizeflag);
15752   append_seg ();
15753
15754   off = get64 ();
15755
15756   if (intel_syntax)
15757     {
15758       if (!active_seg_prefix)
15759         {
15760           oappend (names_seg[ds_reg - es_reg]);
15761           oappend (":");
15762         }
15763     }
15764   print_operand_value (scratchbuf, 1, off);
15765   oappend (scratchbuf);
15766 }
15767
15768 static void
15769 ptr_reg (int code, int sizeflag)
15770 {
15771   const char *s;
15772
15773   *obufp++ = open_char;
15774   used_prefixes |= (prefixes & PREFIX_ADDR);
15775   if (address_mode == mode_64bit)
15776     {
15777       if (!(sizeflag & AFLAG))
15778         s = names32[code - eAX_reg];
15779       else
15780         s = names64[code - eAX_reg];
15781     }
15782   else if (sizeflag & AFLAG)
15783     s = names32[code - eAX_reg];
15784   else
15785     s = names16[code - eAX_reg];
15786   oappend (s);
15787   *obufp++ = close_char;
15788   *obufp = 0;
15789 }
15790
15791 static void
15792 OP_ESreg (int code, int sizeflag)
15793 {
15794   if (intel_syntax)
15795     {
15796       switch (codep[-1])
15797         {
15798         case 0x6d:      /* insw/insl */
15799           intel_operand_size (z_mode, sizeflag);
15800           break;
15801         case 0xa5:      /* movsw/movsl/movsq */
15802         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15803         case 0xab:      /* stosw/stosl */
15804         case 0xaf:      /* scasw/scasl */
15805           intel_operand_size (v_mode, sizeflag);
15806           break;
15807         default:
15808           intel_operand_size (b_mode, sizeflag);
15809         }
15810     }
15811   oappend_maybe_intel ("%es:");
15812   ptr_reg (code, sizeflag);
15813 }
15814
15815 static void
15816 OP_DSreg (int code, int sizeflag)
15817 {
15818   if (intel_syntax)
15819     {
15820       switch (codep[-1])
15821         {
15822         case 0x6f:      /* outsw/outsl */
15823           intel_operand_size (z_mode, sizeflag);
15824           break;
15825         case 0xa5:      /* movsw/movsl/movsq */
15826         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15827         case 0xad:      /* lodsw/lodsl/lodsq */
15828           intel_operand_size (v_mode, sizeflag);
15829           break;
15830         default:
15831           intel_operand_size (b_mode, sizeflag);
15832         }
15833     }
15834   /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
15835      default segment register DS is printed.  */
15836   if (!active_seg_prefix)
15837     active_seg_prefix = PREFIX_DS;
15838   append_seg ();
15839   ptr_reg (code, sizeflag);
15840 }
15841
15842 static void
15843 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15844 {
15845   int add;
15846   if (rex & REX_R)
15847     {
15848       USED_REX (REX_R);
15849       add = 8;
15850     }
15851   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
15852     {
15853       all_prefixes[last_lock_prefix] = 0;
15854       used_prefixes |= PREFIX_LOCK;
15855       add = 8;
15856     }
15857   else
15858     add = 0;
15859   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
15860   oappend_maybe_intel (scratchbuf);
15861 }
15862
15863 static void
15864 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15865 {
15866   int add;
15867   USED_REX (REX_R);
15868   if (rex & REX_R)
15869     add = 8;
15870   else
15871     add = 0;
15872   if (intel_syntax)
15873     sprintf (scratchbuf, "db%d", modrm.reg + add);
15874   else
15875     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
15876   oappend (scratchbuf);
15877 }
15878
15879 static void
15880 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15881 {
15882   sprintf (scratchbuf, "%%tr%d", modrm.reg);
15883   oappend_maybe_intel (scratchbuf);
15884 }
15885
15886 static void
15887 OP_R (int bytemode, int sizeflag)
15888 {
15889   /* Skip mod/rm byte.  */
15890   MODRM_CHECK;
15891   codep++;
15892   OP_E_register (bytemode, sizeflag);
15893 }
15894
15895 static void
15896 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15897 {
15898   int reg = modrm.reg;
15899   const char **names;
15900
15901   used_prefixes |= (prefixes & PREFIX_DATA);
15902   if (prefixes & PREFIX_DATA)
15903     {
15904       names = names_xmm;
15905       USED_REX (REX_R);
15906       if (rex & REX_R)
15907         reg += 8;
15908     }
15909   else
15910     names = names_mm;
15911   oappend (names[reg]);
15912 }
15913
15914 static void
15915 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15916 {
15917   int reg = modrm.reg;
15918   const char **names;
15919
15920   USED_REX (REX_R);
15921   if (rex & REX_R)
15922     reg += 8;
15923   if (vex.evex)
15924     {
15925       if (!vex.r)
15926         reg += 16;
15927     }
15928
15929   if (need_vex
15930       && bytemode != xmm_mode
15931       && bytemode != xmmq_mode
15932       && bytemode != evex_half_bcst_xmmq_mode
15933       && bytemode != ymm_mode
15934       && bytemode != scalar_mode)
15935     {
15936       switch (vex.length)
15937         {
15938         case 128:
15939           names = names_xmm;
15940           break;
15941         case 256:
15942           if (vex.w
15943               || (bytemode != vex_vsib_q_w_dq_mode
15944                   && bytemode != vex_vsib_q_w_d_mode))
15945             names = names_ymm;
15946           else
15947             names = names_xmm;
15948           break;
15949         case 512:
15950           names = names_zmm;
15951           break;
15952         default:
15953           abort ();
15954         }
15955     }
15956   else if (bytemode == xmmq_mode
15957            || bytemode == evex_half_bcst_xmmq_mode)
15958     {
15959       switch (vex.length)
15960         {
15961         case 128:
15962         case 256:
15963           names = names_xmm;
15964           break;
15965         case 512:
15966           names = names_ymm;
15967           break;
15968         default:
15969           abort ();
15970         }
15971     }
15972   else if (bytemode == ymm_mode)
15973     names = names_ymm;
15974   else
15975     names = names_xmm;
15976   oappend (names[reg]);
15977 }
15978
15979 static void
15980 OP_EM (int bytemode, int sizeflag)
15981 {
15982   int reg;
15983   const char **names;
15984
15985   if (modrm.mod != 3)
15986     {
15987       if (intel_syntax
15988           && (bytemode == v_mode || bytemode == v_swap_mode))
15989         {
15990           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15991           used_prefixes |= (prefixes & PREFIX_DATA);
15992         }
15993       OP_E (bytemode, sizeflag);
15994       return;
15995     }
15996
15997   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
15998     swap_operand ();
15999
16000   /* Skip mod/rm byte.  */
16001   MODRM_CHECK;
16002   codep++;
16003   used_prefixes |= (prefixes & PREFIX_DATA);
16004   reg = modrm.rm;
16005   if (prefixes & PREFIX_DATA)
16006     {
16007       names = names_xmm;
16008       USED_REX (REX_B);
16009       if (rex & REX_B)
16010         reg += 8;
16011     }
16012   else
16013     names = names_mm;
16014   oappend (names[reg]);
16015 }
16016
16017 /* cvt* are the only instructions in sse2 which have
16018    both SSE and MMX operands and also have 0x66 prefix
16019    in their opcode. 0x66 was originally used to differentiate
16020    between SSE and MMX instruction(operands). So we have to handle the
16021    cvt* separately using OP_EMC and OP_MXC */
16022 static void
16023 OP_EMC (int bytemode, int sizeflag)
16024 {
16025   if (modrm.mod != 3)
16026     {
16027       if (intel_syntax && bytemode == v_mode)
16028         {
16029           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16030           used_prefixes |= (prefixes & PREFIX_DATA);
16031         }
16032       OP_E (bytemode, sizeflag);
16033       return;
16034     }
16035
16036   /* Skip mod/rm byte.  */
16037   MODRM_CHECK;
16038   codep++;
16039   used_prefixes |= (prefixes & PREFIX_DATA);
16040   oappend (names_mm[modrm.rm]);
16041 }
16042
16043 static void
16044 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16045 {
16046   used_prefixes |= (prefixes & PREFIX_DATA);
16047   oappend (names_mm[modrm.reg]);
16048 }
16049
16050 static void
16051 OP_EX (int bytemode, int sizeflag)
16052 {
16053   int reg;
16054   const char **names;
16055
16056   /* Skip mod/rm byte.  */
16057   MODRM_CHECK;
16058   codep++;
16059
16060   if (modrm.mod != 3)
16061     {
16062       OP_E_memory (bytemode, sizeflag);
16063       return;
16064     }
16065
16066   reg = modrm.rm;
16067   USED_REX (REX_B);
16068   if (rex & REX_B)
16069     reg += 8;
16070   if (vex.evex)
16071     {
16072       USED_REX (REX_X);
16073       if ((rex & REX_X))
16074         reg += 16;
16075     }
16076
16077   if ((sizeflag & SUFFIX_ALWAYS)
16078       && (bytemode == x_swap_mode
16079           || bytemode == d_swap_mode
16080           || bytemode == dqw_swap_mode
16081           || bytemode == d_scalar_swap_mode
16082           || bytemode == q_swap_mode
16083           || bytemode == q_scalar_swap_mode))
16084     swap_operand ();
16085
16086   if (need_vex
16087       && bytemode != xmm_mode
16088       && bytemode != xmmdw_mode
16089       && bytemode != xmmqd_mode
16090       && bytemode != xmm_mb_mode
16091       && bytemode != xmm_mw_mode
16092       && bytemode != xmm_md_mode
16093       && bytemode != xmm_mq_mode
16094       && bytemode != xmm_mdq_mode
16095       && bytemode != xmmq_mode
16096       && bytemode != evex_half_bcst_xmmq_mode
16097       && bytemode != ymm_mode
16098       && bytemode != d_scalar_mode
16099       && bytemode != d_scalar_swap_mode
16100       && bytemode != q_scalar_mode
16101       && bytemode != q_scalar_swap_mode
16102       && bytemode != vex_scalar_w_dq_mode)
16103     {
16104       switch (vex.length)
16105         {
16106         case 128:
16107           names = names_xmm;
16108           break;
16109         case 256:
16110           names = names_ymm;
16111           break;
16112         case 512:
16113           names = names_zmm;
16114           break;
16115         default:
16116           abort ();
16117         }
16118     }
16119   else if (bytemode == xmmq_mode
16120            || bytemode == evex_half_bcst_xmmq_mode)
16121     {
16122       switch (vex.length)
16123         {
16124         case 128:
16125         case 256:
16126           names = names_xmm;
16127           break;
16128         case 512:
16129           names = names_ymm;
16130           break;
16131         default:
16132           abort ();
16133         }
16134     }
16135   else if (bytemode == ymm_mode)
16136     names = names_ymm;
16137   else
16138     names = names_xmm;
16139   oappend (names[reg]);
16140 }
16141
16142 static void
16143 OP_MS (int bytemode, int sizeflag)
16144 {
16145   if (modrm.mod == 3)
16146     OP_EM (bytemode, sizeflag);
16147   else
16148     BadOp ();
16149 }
16150
16151 static void
16152 OP_XS (int bytemode, int sizeflag)
16153 {
16154   if (modrm.mod == 3)
16155     OP_EX (bytemode, sizeflag);
16156   else
16157     BadOp ();
16158 }
16159
16160 static void
16161 OP_M (int bytemode, int sizeflag)
16162 {
16163   if (modrm.mod == 3)
16164     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
16165     BadOp ();
16166   else
16167     OP_E (bytemode, sizeflag);
16168 }
16169
16170 static void
16171 OP_0f07 (int bytemode, int sizeflag)
16172 {
16173   if (modrm.mod != 3 || modrm.rm != 0)
16174     BadOp ();
16175   else
16176     OP_E (bytemode, sizeflag);
16177 }
16178
16179 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
16180    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
16181
16182 static void
16183 NOP_Fixup1 (int bytemode, int sizeflag)
16184 {
16185   if ((prefixes & PREFIX_DATA) != 0
16186       || (rex != 0
16187           && rex != 0x48
16188           && address_mode == mode_64bit))
16189     OP_REG (bytemode, sizeflag);
16190   else
16191     strcpy (obuf, "nop");
16192 }
16193
16194 static void
16195 NOP_Fixup2 (int bytemode, int sizeflag)
16196 {
16197   if ((prefixes & PREFIX_DATA) != 0
16198       || (rex != 0
16199           && rex != 0x48
16200           && address_mode == mode_64bit))
16201     OP_IMREG (bytemode, sizeflag);
16202 }
16203
16204 static const char *const Suffix3DNow[] = {
16205 /* 00 */        NULL,           NULL,           NULL,           NULL,
16206 /* 04 */        NULL,           NULL,           NULL,           NULL,
16207 /* 08 */        NULL,           NULL,           NULL,           NULL,
16208 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
16209 /* 10 */        NULL,           NULL,           NULL,           NULL,
16210 /* 14 */        NULL,           NULL,           NULL,           NULL,
16211 /* 18 */        NULL,           NULL,           NULL,           NULL,
16212 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
16213 /* 20 */        NULL,           NULL,           NULL,           NULL,
16214 /* 24 */        NULL,           NULL,           NULL,           NULL,
16215 /* 28 */        NULL,           NULL,           NULL,           NULL,
16216 /* 2C */        NULL,           NULL,           NULL,           NULL,
16217 /* 30 */        NULL,           NULL,           NULL,           NULL,
16218 /* 34 */        NULL,           NULL,           NULL,           NULL,
16219 /* 38 */        NULL,           NULL,           NULL,           NULL,
16220 /* 3C */        NULL,           NULL,           NULL,           NULL,
16221 /* 40 */        NULL,           NULL,           NULL,           NULL,
16222 /* 44 */        NULL,           NULL,           NULL,           NULL,
16223 /* 48 */        NULL,           NULL,           NULL,           NULL,
16224 /* 4C */        NULL,           NULL,           NULL,           NULL,
16225 /* 50 */        NULL,           NULL,           NULL,           NULL,
16226 /* 54 */        NULL,           NULL,           NULL,           NULL,
16227 /* 58 */        NULL,           NULL,           NULL,           NULL,
16228 /* 5C */        NULL,           NULL,           NULL,           NULL,
16229 /* 60 */        NULL,           NULL,           NULL,           NULL,
16230 /* 64 */        NULL,           NULL,           NULL,           NULL,
16231 /* 68 */        NULL,           NULL,           NULL,           NULL,
16232 /* 6C */        NULL,           NULL,           NULL,           NULL,
16233 /* 70 */        NULL,           NULL,           NULL,           NULL,
16234 /* 74 */        NULL,           NULL,           NULL,           NULL,
16235 /* 78 */        NULL,           NULL,           NULL,           NULL,
16236 /* 7C */        NULL,           NULL,           NULL,           NULL,
16237 /* 80 */        NULL,           NULL,           NULL,           NULL,
16238 /* 84 */        NULL,           NULL,           NULL,           NULL,
16239 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
16240 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
16241 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
16242 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
16243 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
16244 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
16245 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
16246 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
16247 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
16248 /* AC */        NULL,           NULL,           "pfacc",        NULL,
16249 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
16250 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
16251 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
16252 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
16253 /* C0 */        NULL,           NULL,           NULL,           NULL,
16254 /* C4 */        NULL,           NULL,           NULL,           NULL,
16255 /* C8 */        NULL,           NULL,           NULL,           NULL,
16256 /* CC */        NULL,           NULL,           NULL,           NULL,
16257 /* D0 */        NULL,           NULL,           NULL,           NULL,
16258 /* D4 */        NULL,           NULL,           NULL,           NULL,
16259 /* D8 */        NULL,           NULL,           NULL,           NULL,
16260 /* DC */        NULL,           NULL,           NULL,           NULL,
16261 /* E0 */        NULL,           NULL,           NULL,           NULL,
16262 /* E4 */        NULL,           NULL,           NULL,           NULL,
16263 /* E8 */        NULL,           NULL,           NULL,           NULL,
16264 /* EC */        NULL,           NULL,           NULL,           NULL,
16265 /* F0 */        NULL,           NULL,           NULL,           NULL,
16266 /* F4 */        NULL,           NULL,           NULL,           NULL,
16267 /* F8 */        NULL,           NULL,           NULL,           NULL,
16268 /* FC */        NULL,           NULL,           NULL,           NULL,
16269 };
16270
16271 static void
16272 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16273 {
16274   const char *mnemonic;
16275
16276   FETCH_DATA (the_info, codep + 1);
16277   /* AMD 3DNow! instructions are specified by an opcode suffix in the
16278      place where an 8-bit immediate would normally go.  ie. the last
16279      byte of the instruction.  */
16280   obufp = mnemonicendp;
16281   mnemonic = Suffix3DNow[*codep++ & 0xff];
16282   if (mnemonic)
16283     oappend (mnemonic);
16284   else
16285     {
16286       /* Since a variable sized modrm/sib chunk is between the start
16287          of the opcode (0x0f0f) and the opcode suffix, we need to do
16288          all the modrm processing first, and don't know until now that
16289          we have a bad opcode.  This necessitates some cleaning up.  */
16290       op_out[0][0] = '\0';
16291       op_out[1][0] = '\0';
16292       BadOp ();
16293     }
16294   mnemonicendp = obufp;
16295 }
16296
16297 static struct op simd_cmp_op[] =
16298 {
16299   { STRING_COMMA_LEN ("eq") },
16300   { STRING_COMMA_LEN ("lt") },
16301   { STRING_COMMA_LEN ("le") },
16302   { STRING_COMMA_LEN ("unord") },
16303   { STRING_COMMA_LEN ("neq") },
16304   { STRING_COMMA_LEN ("nlt") },
16305   { STRING_COMMA_LEN ("nle") },
16306   { STRING_COMMA_LEN ("ord") }
16307 };
16308
16309 static void
16310 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16311 {
16312   unsigned int cmp_type;
16313
16314   FETCH_DATA (the_info, codep + 1);
16315   cmp_type = *codep++ & 0xff;
16316   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
16317     {
16318       char suffix [3];
16319       char *p = mnemonicendp - 2;
16320       suffix[0] = p[0];
16321       suffix[1] = p[1];
16322       suffix[2] = '\0';
16323       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16324       mnemonicendp += simd_cmp_op[cmp_type].len;
16325     }
16326   else
16327     {
16328       /* We have a reserved extension byte.  Output it directly.  */
16329       scratchbuf[0] = '$';
16330       print_operand_value (scratchbuf + 1, 1, cmp_type);
16331       oappend_maybe_intel (scratchbuf);
16332       scratchbuf[0] = '\0';
16333     }
16334 }
16335
16336 static void
16337 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
16338           int sizeflag ATTRIBUTE_UNUSED)
16339 {
16340   /* mwait %eax,%ecx  */
16341   if (!intel_syntax)
16342     {
16343       const char **names = (address_mode == mode_64bit
16344                             ? names64 : names32);
16345       strcpy (op_out[0], names[0]);
16346       strcpy (op_out[1], names[1]);
16347       two_source_ops = 1;
16348     }
16349   /* Skip mod/rm byte.  */
16350   MODRM_CHECK;
16351   codep++;
16352 }
16353
16354 static void
16355 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
16356             int sizeflag ATTRIBUTE_UNUSED)
16357 {
16358   /* monitor %eax,%ecx,%edx"  */
16359   if (!intel_syntax)
16360     {
16361       const char **op1_names;
16362       const char **names = (address_mode == mode_64bit
16363                             ? names64 : names32);
16364
16365       if (!(prefixes & PREFIX_ADDR))
16366         op1_names = (address_mode == mode_16bit
16367                      ? names16 : names);
16368       else
16369         {
16370           /* Remove "addr16/addr32".  */
16371           all_prefixes[last_addr_prefix] = 0;
16372           op1_names = (address_mode != mode_32bit
16373                        ? names32 : names16);
16374           used_prefixes |= PREFIX_ADDR;
16375         }
16376       strcpy (op_out[0], op1_names[0]);
16377       strcpy (op_out[1], names[1]);
16378       strcpy (op_out[2], names[2]);
16379       two_source_ops = 1;
16380     }
16381   /* Skip mod/rm byte.  */
16382   MODRM_CHECK;
16383   codep++;
16384 }
16385
16386 static void
16387 BadOp (void)
16388 {
16389   /* Throw away prefixes and 1st. opcode byte.  */
16390   codep = insn_codep + 1;
16391   oappend ("(bad)");
16392 }
16393
16394 static void
16395 REP_Fixup (int bytemode, int sizeflag)
16396 {
16397   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
16398      lods and stos.  */
16399   if (prefixes & PREFIX_REPZ)
16400     all_prefixes[last_repz_prefix] = REP_PREFIX;
16401
16402   switch (bytemode)
16403     {
16404     case al_reg:
16405     case eAX_reg:
16406     case indir_dx_reg:
16407       OP_IMREG (bytemode, sizeflag);
16408       break;
16409     case eDI_reg:
16410       OP_ESreg (bytemode, sizeflag);
16411       break;
16412     case eSI_reg:
16413       OP_DSreg (bytemode, sizeflag);
16414       break;
16415     default:
16416       abort ();
16417       break;
16418     }
16419 }
16420
16421 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
16422    "bnd".  */
16423
16424 static void
16425 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16426 {
16427   if (prefixes & PREFIX_REPNZ)
16428     all_prefixes[last_repnz_prefix] = BND_PREFIX;
16429 }
16430
16431 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
16432    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
16433  */
16434
16435 static void
16436 HLE_Fixup1 (int bytemode, int sizeflag)
16437 {
16438   if (modrm.mod != 3
16439       && (prefixes & PREFIX_LOCK) != 0)
16440     {
16441       if (prefixes & PREFIX_REPZ)
16442         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16443       if (prefixes & PREFIX_REPNZ)
16444         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16445     }
16446
16447   OP_E (bytemode, sizeflag);
16448 }
16449
16450 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
16451    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
16452  */
16453
16454 static void
16455 HLE_Fixup2 (int bytemode, int sizeflag)
16456 {
16457   if (modrm.mod != 3)
16458     {
16459       if (prefixes & PREFIX_REPZ)
16460         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16461       if (prefixes & PREFIX_REPNZ)
16462         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16463     }
16464
16465   OP_E (bytemode, sizeflag);
16466 }
16467
16468 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
16469    "xrelease" for memory operand.  No check for LOCK prefix.   */
16470
16471 static void
16472 HLE_Fixup3 (int bytemode, int sizeflag)
16473 {
16474   if (modrm.mod != 3
16475       && last_repz_prefix > last_repnz_prefix
16476       && (prefixes & PREFIX_REPZ) != 0)
16477     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16478
16479   OP_E (bytemode, sizeflag);
16480 }
16481
16482 static void
16483 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
16484 {
16485   USED_REX (REX_W);
16486   if (rex & REX_W)
16487     {
16488       /* Change cmpxchg8b to cmpxchg16b.  */
16489       char *p = mnemonicendp - 2;
16490       mnemonicendp = stpcpy (p, "16b");
16491       bytemode = o_mode;
16492     }
16493   else if ((prefixes & PREFIX_LOCK) != 0)
16494     {
16495       if (prefixes & PREFIX_REPZ)
16496         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16497       if (prefixes & PREFIX_REPNZ)
16498         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16499     }
16500
16501   OP_M (bytemode, sizeflag);
16502 }
16503
16504 static void
16505 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
16506 {
16507   const char **names;
16508
16509   if (need_vex)
16510     {
16511       switch (vex.length)
16512         {
16513         case 128:
16514           names = names_xmm;
16515           break;
16516         case 256:
16517           names = names_ymm;
16518           break;
16519         default:
16520           abort ();
16521         }
16522     }
16523   else
16524     names = names_xmm;
16525   oappend (names[reg]);
16526 }
16527
16528 static void
16529 CRC32_Fixup (int bytemode, int sizeflag)
16530 {
16531   /* Add proper suffix to "crc32".  */
16532   char *p = mnemonicendp;
16533
16534   switch (bytemode)
16535     {
16536     case b_mode:
16537       if (intel_syntax)
16538         goto skip;
16539
16540       *p++ = 'b';
16541       break;
16542     case v_mode:
16543       if (intel_syntax)
16544         goto skip;
16545
16546       USED_REX (REX_W);
16547       if (rex & REX_W)
16548         *p++ = 'q';
16549       else
16550         {
16551           if (sizeflag & DFLAG)
16552             *p++ = 'l';
16553           else
16554             *p++ = 'w';
16555           used_prefixes |= (prefixes & PREFIX_DATA);
16556         }
16557       break;
16558     default:
16559       oappend (INTERNAL_DISASSEMBLER_ERROR);
16560       break;
16561     }
16562   mnemonicendp = p;
16563   *p = '\0';
16564
16565 skip:
16566   if (modrm.mod == 3)
16567     {
16568       int add;
16569
16570       /* Skip mod/rm byte.  */
16571       MODRM_CHECK;
16572       codep++;
16573
16574       USED_REX (REX_B);
16575       add = (rex & REX_B) ? 8 : 0;
16576       if (bytemode == b_mode)
16577         {
16578           USED_REX (0);
16579           if (rex)
16580             oappend (names8rex[modrm.rm + add]);
16581           else
16582             oappend (names8[modrm.rm + add]);
16583         }
16584       else
16585         {
16586           USED_REX (REX_W);
16587           if (rex & REX_W)
16588             oappend (names64[modrm.rm + add]);
16589           else if ((prefixes & PREFIX_DATA))
16590             oappend (names16[modrm.rm + add]);
16591           else
16592             oappend (names32[modrm.rm + add]);
16593         }
16594     }
16595   else
16596     OP_E (bytemode, sizeflag);
16597 }
16598
16599 static void
16600 FXSAVE_Fixup (int bytemode, int sizeflag)
16601 {
16602   /* Add proper suffix to "fxsave" and "fxrstor".  */
16603   USED_REX (REX_W);
16604   if (rex & REX_W)
16605     {
16606       char *p = mnemonicendp;
16607       *p++ = '6';
16608       *p++ = '4';
16609       *p = '\0';
16610       mnemonicendp = p;
16611     }
16612   OP_M (bytemode, sizeflag);
16613 }
16614
16615 /* Display the destination register operand for instructions with
16616    VEX. */
16617
16618 static void
16619 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16620 {
16621   int reg;
16622   const char **names;
16623
16624   if (!need_vex)
16625     abort ();
16626
16627   if (!need_vex_reg)
16628     return;
16629
16630   reg = vex.register_specifier;
16631   if (vex.evex)
16632     {
16633       if (!vex.v)
16634         reg += 16;
16635     }
16636
16637   if (bytemode == vex_scalar_mode)
16638     {
16639       oappend (names_xmm[reg]);
16640       return;
16641     }
16642
16643   switch (vex.length)
16644     {
16645     case 128:
16646       switch (bytemode)
16647         {
16648         case vex_mode:
16649         case vex128_mode:
16650         case vex_vsib_q_w_dq_mode:
16651         case vex_vsib_q_w_d_mode:
16652           names = names_xmm;
16653           break;
16654         case dq_mode:
16655           if (vex.w)
16656             names = names64;
16657           else
16658             names = names32;
16659           break;
16660         case mask_bd_mode:
16661         case mask_mode:
16662           names = names_mask;
16663           break;
16664         default:
16665           abort ();
16666           return;
16667         }
16668       break;
16669     case 256:
16670       switch (bytemode)
16671         {
16672         case vex_mode:
16673         case vex256_mode:
16674           names = names_ymm;
16675           break;
16676         case vex_vsib_q_w_dq_mode:
16677         case vex_vsib_q_w_d_mode:
16678           names = vex.w ? names_ymm : names_xmm;
16679           break;
16680         case mask_bd_mode:
16681         case mask_mode:
16682           names = names_mask;
16683           break;
16684         default:
16685           abort ();
16686           return;
16687         }
16688       break;
16689     case 512:
16690       names = names_zmm;
16691       break;
16692     default:
16693       abort ();
16694       break;
16695     }
16696   oappend (names[reg]);
16697 }
16698
16699 /* Get the VEX immediate byte without moving codep.  */
16700
16701 static unsigned char
16702 get_vex_imm8 (int sizeflag, int opnum)
16703 {
16704   int bytes_before_imm = 0;
16705
16706   if (modrm.mod != 3)
16707     {
16708       /* There are SIB/displacement bytes.  */
16709       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
16710         {
16711           /* 32/64 bit address mode */
16712           int base = modrm.rm;
16713
16714           /* Check SIB byte.  */
16715           if (base == 4)
16716             {
16717               FETCH_DATA (the_info, codep + 1);
16718               base = *codep & 7;
16719               /* When decoding the third source, don't increase
16720                  bytes_before_imm as this has already been incremented
16721                  by one in OP_E_memory while decoding the second
16722                  source operand.  */
16723               if (opnum == 0)
16724                 bytes_before_imm++;
16725             }
16726
16727           /* Don't increase bytes_before_imm when decoding the third source,
16728              it has already been incremented by OP_E_memory while decoding
16729              the second source operand.  */
16730           if (opnum == 0)
16731             {
16732               switch (modrm.mod)
16733                 {
16734                   case 0:
16735                     /* When modrm.rm == 5 or modrm.rm == 4 and base in
16736                        SIB == 5, there is a 4 byte displacement.  */
16737                     if (base != 5)
16738                       /* No displacement. */
16739                       break;
16740                   case 2:
16741                     /* 4 byte displacement.  */
16742                     bytes_before_imm += 4;
16743                     break;
16744                   case 1:
16745                     /* 1 byte displacement.  */
16746                     bytes_before_imm++;
16747                     break;
16748                 }
16749             }
16750         }
16751       else
16752         {
16753           /* 16 bit address mode */
16754           /* Don't increase bytes_before_imm when decoding the third source,
16755              it has already been incremented by OP_E_memory while decoding
16756              the second source operand.  */
16757           if (opnum == 0)
16758             {
16759               switch (modrm.mod)
16760                 {
16761                 case 0:
16762                   /* When modrm.rm == 6, there is a 2 byte displacement.  */
16763                   if (modrm.rm != 6)
16764                     /* No displacement. */
16765                     break;
16766                 case 2:
16767                   /* 2 byte displacement.  */
16768                   bytes_before_imm += 2;
16769                   break;
16770                 case 1:
16771                   /* 1 byte displacement: when decoding the third source,
16772                      don't increase bytes_before_imm as this has already
16773                      been incremented by one in OP_E_memory while decoding
16774                      the second source operand.  */
16775                   if (opnum == 0)
16776                     bytes_before_imm++;
16777
16778                   break;
16779                 }
16780             }
16781         }
16782     }
16783
16784   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
16785   return codep [bytes_before_imm];
16786 }
16787
16788 static void
16789 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
16790 {
16791   const char **names;
16792
16793   if (reg == -1 && modrm.mod != 3)
16794     {
16795       OP_E_memory (bytemode, sizeflag);
16796       return;
16797     }
16798   else
16799     {
16800       if (reg == -1)
16801         {
16802           reg = modrm.rm;
16803           USED_REX (REX_B);
16804           if (rex & REX_B)
16805             reg += 8;
16806         }
16807       else if (reg > 7 && address_mode != mode_64bit)
16808         BadOp ();
16809     }
16810
16811   switch (vex.length)
16812     {
16813     case 128:
16814       names = names_xmm;
16815       break;
16816     case 256:
16817       names = names_ymm;
16818       break;
16819     default:
16820       abort ();
16821     }
16822   oappend (names[reg]);
16823 }
16824
16825 static void
16826 OP_EX_VexImmW (int bytemode, int sizeflag)
16827 {
16828   int reg = -1;
16829   static unsigned char vex_imm8;
16830
16831   if (vex_w_done == 0)
16832     {
16833       vex_w_done = 1;
16834
16835       /* Skip mod/rm byte.  */
16836       MODRM_CHECK;
16837       codep++;
16838
16839       vex_imm8 = get_vex_imm8 (sizeflag, 0);
16840
16841       if (vex.w)
16842           reg = vex_imm8 >> 4;
16843
16844       OP_EX_VexReg (bytemode, sizeflag, reg);
16845     }
16846   else if (vex_w_done == 1)
16847     {
16848       vex_w_done = 2;
16849
16850       if (!vex.w)
16851           reg = vex_imm8 >> 4;
16852
16853       OP_EX_VexReg (bytemode, sizeflag, reg);
16854     }
16855   else
16856     {
16857       /* Output the imm8 directly.  */
16858       scratchbuf[0] = '$';
16859       print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
16860       oappend_maybe_intel (scratchbuf);
16861       scratchbuf[0] = '\0';
16862       codep++;
16863     }
16864 }
16865
16866 static void
16867 OP_Vex_2src (int bytemode, int sizeflag)
16868 {
16869   if (modrm.mod == 3)
16870     {
16871       int reg = modrm.rm;
16872       USED_REX (REX_B);
16873       if (rex & REX_B)
16874         reg += 8;
16875       oappend (names_xmm[reg]);
16876     }
16877   else
16878     {
16879       if (intel_syntax
16880           && (bytemode == v_mode || bytemode == v_swap_mode))
16881         {
16882           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16883           used_prefixes |= (prefixes & PREFIX_DATA);
16884         }
16885       OP_E (bytemode, sizeflag);
16886     }
16887 }
16888
16889 static void
16890 OP_Vex_2src_1 (int bytemode, int sizeflag)
16891 {
16892   if (modrm.mod == 3)
16893     {
16894       /* Skip mod/rm byte.   */
16895       MODRM_CHECK;
16896       codep++;
16897     }
16898
16899   if (vex.w)
16900     oappend (names_xmm[vex.register_specifier]);
16901   else
16902     OP_Vex_2src (bytemode, sizeflag);
16903 }
16904
16905 static void
16906 OP_Vex_2src_2 (int bytemode, int sizeflag)
16907 {
16908   if (vex.w)
16909     OP_Vex_2src (bytemode, sizeflag);
16910   else
16911     oappend (names_xmm[vex.register_specifier]);
16912 }
16913
16914 static void
16915 OP_EX_VexW (int bytemode, int sizeflag)
16916 {
16917   int reg = -1;
16918
16919   if (!vex_w_done)
16920     {
16921       vex_w_done = 1;
16922
16923       /* Skip mod/rm byte.  */
16924       MODRM_CHECK;
16925       codep++;
16926
16927       if (vex.w)
16928         reg = get_vex_imm8 (sizeflag, 0) >> 4;
16929     }
16930   else
16931     {
16932       if (!vex.w)
16933         reg = get_vex_imm8 (sizeflag, 1) >> 4;
16934     }
16935
16936   OP_EX_VexReg (bytemode, sizeflag, reg);
16937 }
16938
16939 static void
16940 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,
16941              int sizeflag ATTRIBUTE_UNUSED)
16942 {
16943   /* Skip the immediate byte and check for invalid bits.  */
16944   FETCH_DATA (the_info, codep + 1);
16945   if (*codep++ & 0xf)
16946     BadOp ();
16947 }
16948
16949 static void
16950 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16951 {
16952   int reg;
16953   const char **names;
16954
16955   FETCH_DATA (the_info, codep + 1);
16956   reg = *codep++;
16957
16958   if (bytemode != x_mode)
16959     abort ();
16960
16961   if (reg & 0xf)
16962       BadOp ();
16963
16964   reg >>= 4;
16965   if (reg > 7 && address_mode != mode_64bit)
16966     BadOp ();
16967
16968   switch (vex.length)
16969     {
16970     case 128:
16971       names = names_xmm;
16972       break;
16973     case 256:
16974       names = names_ymm;
16975       break;
16976     default:
16977       abort ();
16978     }
16979   oappend (names[reg]);
16980 }
16981
16982 static void
16983 OP_XMM_VexW (int bytemode, int sizeflag)
16984 {
16985   /* Turn off the REX.W bit since it is used for swapping operands
16986      now.  */
16987   rex &= ~REX_W;
16988   OP_XMM (bytemode, sizeflag);
16989 }
16990
16991 static void
16992 OP_EX_Vex (int bytemode, int sizeflag)
16993 {
16994   if (modrm.mod != 3)
16995     {
16996       if (vex.register_specifier != 0)
16997         BadOp ();
16998       need_vex_reg = 0;
16999     }
17000   OP_EX (bytemode, sizeflag);
17001 }
17002
17003 static void
17004 OP_XMM_Vex (int bytemode, int sizeflag)
17005 {
17006   if (modrm.mod != 3)
17007     {
17008       if (vex.register_specifier != 0)
17009         BadOp ();
17010       need_vex_reg = 0;
17011     }
17012   OP_XMM (bytemode, sizeflag);
17013 }
17014
17015 static void
17016 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17017 {
17018   switch (vex.length)
17019     {
17020     case 128:
17021       mnemonicendp = stpcpy (obuf, "vzeroupper");
17022       break;
17023     case 256:
17024       mnemonicendp = stpcpy (obuf, "vzeroall");
17025       break;
17026     default:
17027       abort ();
17028     }
17029 }
17030
17031 static struct op vex_cmp_op[] =
17032 {
17033   { STRING_COMMA_LEN ("eq") },
17034   { STRING_COMMA_LEN ("lt") },
17035   { STRING_COMMA_LEN ("le") },
17036   { STRING_COMMA_LEN ("unord") },
17037   { STRING_COMMA_LEN ("neq") },
17038   { STRING_COMMA_LEN ("nlt") },
17039   { STRING_COMMA_LEN ("nle") },
17040   { STRING_COMMA_LEN ("ord") },
17041   { STRING_COMMA_LEN ("eq_uq") },
17042   { STRING_COMMA_LEN ("nge") },
17043   { STRING_COMMA_LEN ("ngt") },
17044   { STRING_COMMA_LEN ("false") },
17045   { STRING_COMMA_LEN ("neq_oq") },
17046   { STRING_COMMA_LEN ("ge") },
17047   { STRING_COMMA_LEN ("gt") },
17048   { STRING_COMMA_LEN ("true") },
17049   { STRING_COMMA_LEN ("eq_os") },
17050   { STRING_COMMA_LEN ("lt_oq") },
17051   { STRING_COMMA_LEN ("le_oq") },
17052   { STRING_COMMA_LEN ("unord_s") },
17053   { STRING_COMMA_LEN ("neq_us") },
17054   { STRING_COMMA_LEN ("nlt_uq") },
17055   { STRING_COMMA_LEN ("nle_uq") },
17056   { STRING_COMMA_LEN ("ord_s") },
17057   { STRING_COMMA_LEN ("eq_us") },
17058   { STRING_COMMA_LEN ("nge_uq") },
17059   { STRING_COMMA_LEN ("ngt_uq") },
17060   { STRING_COMMA_LEN ("false_os") },
17061   { STRING_COMMA_LEN ("neq_os") },
17062   { STRING_COMMA_LEN ("ge_oq") },
17063   { STRING_COMMA_LEN ("gt_oq") },
17064   { STRING_COMMA_LEN ("true_us") },
17065 };
17066
17067 static void
17068 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17069 {
17070   unsigned int cmp_type;
17071
17072   FETCH_DATA (the_info, codep + 1);
17073   cmp_type = *codep++ & 0xff;
17074   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
17075     {
17076       char suffix [3];
17077       char *p = mnemonicendp - 2;
17078       suffix[0] = p[0];
17079       suffix[1] = p[1];
17080       suffix[2] = '\0';
17081       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
17082       mnemonicendp += vex_cmp_op[cmp_type].len;
17083     }
17084   else
17085     {
17086       /* We have a reserved extension byte.  Output it directly.  */
17087       scratchbuf[0] = '$';
17088       print_operand_value (scratchbuf + 1, 1, cmp_type);
17089       oappend_maybe_intel (scratchbuf);
17090       scratchbuf[0] = '\0';
17091     }
17092 }
17093
17094 static void
17095 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
17096              int sizeflag ATTRIBUTE_UNUSED)
17097 {
17098   unsigned int cmp_type;
17099
17100   if (!vex.evex)
17101     abort ();
17102
17103   FETCH_DATA (the_info, codep + 1);
17104   cmp_type = *codep++ & 0xff;
17105   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
17106      If it's the case, print suffix, otherwise - print the immediate.  */
17107   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
17108       && cmp_type != 3
17109       && cmp_type != 7)
17110     {
17111       char suffix [3];
17112       char *p = mnemonicendp - 2;
17113
17114       /* vpcmp* can have both one- and two-lettered suffix.  */
17115       if (p[0] == 'p')
17116         {
17117           p++;
17118           suffix[0] = p[0];
17119           suffix[1] = '\0';
17120         }
17121       else
17122         {
17123           suffix[0] = p[0];
17124           suffix[1] = p[1];
17125           suffix[2] = '\0';
17126         }
17127
17128       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
17129       mnemonicendp += simd_cmp_op[cmp_type].len;
17130     }
17131   else
17132     {
17133       /* We have a reserved extension byte.  Output it directly.  */
17134       scratchbuf[0] = '$';
17135       print_operand_value (scratchbuf + 1, 1, cmp_type);
17136       oappend_maybe_intel (scratchbuf);
17137       scratchbuf[0] = '\0';
17138     }
17139 }
17140
17141 static const struct op pclmul_op[] =
17142 {
17143   { STRING_COMMA_LEN ("lql") },
17144   { STRING_COMMA_LEN ("hql") },
17145   { STRING_COMMA_LEN ("lqh") },
17146   { STRING_COMMA_LEN ("hqh") }
17147 };
17148
17149 static void
17150 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
17151               int sizeflag ATTRIBUTE_UNUSED)
17152 {
17153   unsigned int pclmul_type;
17154
17155   FETCH_DATA (the_info, codep + 1);
17156   pclmul_type = *codep++ & 0xff;
17157   switch (pclmul_type)
17158     {
17159     case 0x10:
17160       pclmul_type = 2;
17161       break;
17162     case 0x11:
17163       pclmul_type = 3;
17164       break;
17165     default:
17166       break;
17167     }
17168   if (pclmul_type < ARRAY_SIZE (pclmul_op))
17169     {
17170       char suffix [4];
17171       char *p = mnemonicendp - 3;
17172       suffix[0] = p[0];
17173       suffix[1] = p[1];
17174       suffix[2] = p[2];
17175       suffix[3] = '\0';
17176       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
17177       mnemonicendp += pclmul_op[pclmul_type].len;
17178     }
17179   else
17180     {
17181       /* We have a reserved extension byte.  Output it directly.  */
17182       scratchbuf[0] = '$';
17183       print_operand_value (scratchbuf + 1, 1, pclmul_type);
17184       oappend_maybe_intel (scratchbuf);
17185       scratchbuf[0] = '\0';
17186     }
17187 }
17188
17189 static void
17190 MOVBE_Fixup (int bytemode, int sizeflag)
17191 {
17192   /* Add proper suffix to "movbe".  */
17193   char *p = mnemonicendp;
17194
17195   switch (bytemode)
17196     {
17197     case v_mode:
17198       if (intel_syntax)
17199         goto skip;
17200
17201       USED_REX (REX_W);
17202       if (sizeflag & SUFFIX_ALWAYS)
17203         {
17204           if (rex & REX_W)
17205             *p++ = 'q';
17206           else
17207             {
17208               if (sizeflag & DFLAG)
17209                 *p++ = 'l';
17210               else
17211                 *p++ = 'w';
17212               used_prefixes |= (prefixes & PREFIX_DATA);
17213             }
17214         }
17215       break;
17216     default:
17217       oappend (INTERNAL_DISASSEMBLER_ERROR);
17218       break;
17219     }
17220   mnemonicendp = p;
17221   *p = '\0';
17222
17223 skip:
17224   OP_M (bytemode, sizeflag);
17225 }
17226
17227 static void
17228 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17229 {
17230   int reg;
17231   const char **names;
17232
17233   /* Skip mod/rm byte.  */
17234   MODRM_CHECK;
17235   codep++;
17236
17237   if (vex.w)
17238     names = names64;
17239   else
17240     names = names32;
17241
17242   reg = modrm.rm;
17243   USED_REX (REX_B);
17244   if (rex & REX_B)
17245     reg += 8;
17246
17247   oappend (names[reg]);
17248 }
17249
17250 static void
17251 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17252 {
17253   const char **names;
17254
17255   if (vex.w)
17256     names = names64;
17257   else
17258     names = names32;
17259
17260   oappend (names[vex.register_specifier]);
17261 }
17262
17263 static void
17264 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17265 {
17266   if (!vex.evex
17267       || (bytemode != mask_mode && bytemode != mask_bd_mode))
17268     abort ();
17269
17270   USED_REX (REX_R);
17271   if ((rex & REX_R) != 0 || !vex.r)
17272     {
17273       BadOp ();
17274       return;
17275     }
17276
17277   oappend (names_mask [modrm.reg]);
17278 }
17279
17280 static void
17281 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17282 {
17283   if (!vex.evex
17284       || (bytemode != evex_rounding_mode
17285           && bytemode != evex_sae_mode))
17286     abort ();
17287   if (modrm.mod == 3 && vex.b)
17288     switch (bytemode)
17289       {
17290       case evex_rounding_mode:
17291         oappend (names_rounding[vex.ll]);
17292         break;
17293       case evex_sae_mode:
17294         oappend ("{sae}");
17295         break;
17296       default:
17297         break;
17298       }
17299 }