opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2018 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "disassemble.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40
  41 #include <setjmp.h>
  42
  43 static int print_insn (bfd_vma, disassemble_info *);
  44 static void dofloat (int);
  45 static void OP_ST (int, int);
  46 static void OP_STi (int, int);
  47 static int putop (const char *, int);
  48 static void oappend (const char *);
  49 static void append_seg (void);
  50 static void OP_indirE (int, int);
  51 static void print_operand_value (char *, int, bfd_vma);
  52 static void OP_E_register (int, int);
  53 static void OP_E_memory (int, int);
  54 static void print_displacement (char *, bfd_vma);
  55 static void OP_E (int, int);
  56 static void OP_G (int, int);
  57 static bfd_vma get64 (void);
  58 static bfd_signed_vma get32 (void);
  59 static bfd_signed_vma get32s (void);
  60 static int get16 (void);
  61 static void set_op (bfd_vma, int);
  62 static void OP_Skip_MODRM (int, int);
  63 static void OP_REG (int, int);
  64 static void OP_IMREG (int, int);
  65 static void OP_I (int, int);
  66 static void OP_I64 (int, int);
  67 static void OP_sI (int, int);
  68 static void OP_J (int, int);
  69 static void OP_SEG (int, int);
  70 static void OP_DIR (int, int);
  71 static void OP_OFF (int, int);
  72 static void OP_OFF64 (int, int);
  73 static void ptr_reg (int, int);
  74 static void OP_ESreg (int, int);
  75 static void OP_DSreg (int, int);
  76 static void OP_C (int, int);
  77 static void OP_D (int, int);
  78 static void OP_T (int, int);
  79 static void OP_R (int, int);
  80 static void OP_MMX (int, int);
  81 static void OP_XMM (int, int);
  82 static void OP_EM (int, int);
  83 static void OP_EX (int, int);
  84 static void OP_EMC (int,int);
  85 static void OP_MXC (int,int);
  86 static void OP_MS (int, int);
  87 static void OP_XS (int, int);
  88 static void OP_M (int, int);
  89 static void OP_VEX (int, int);
  90 static void OP_EX_Vex (int, int);
  91 static void OP_EX_VexW (int, int);
  92 static void OP_EX_VexImmW (int, int);
  93 static void OP_XMM_Vex (int, int);
  94 static void OP_XMM_VexW (int, int);
  95 static void OP_Rounding (int, int);
  96 static void OP_REG_VexI4 (int, int);
  97 static void PCLMUL_Fixup (int, int);
  98 static void VCMP_Fixup (int, int);
  99 static void VPCMP_Fixup (int, int);
 100 static void VPCOM_Fixup (int, int);
 101 static void OP_0f07 (int, int);
 102 static void OP_Monitor (int, int);
 103 static void OP_Mwait (int, int);
 104 static void OP_Mwaitx (int, int);
 105 static void NOP_Fixup1 (int, int);
 106 static void NOP_Fixup2 (int, int);
 107 static void OP_3DNowSuffix (int, int);
 108 static void CMP_Fixup (int, int);
 109 static void BadOp (void);
 110 static void REP_Fixup (int, int);
 111 static void BND_Fixup (int, int);
 112 static void NOTRACK_Fixup (int, int);
 113 static void HLE_Fixup1 (int, int);
 114 static void HLE_Fixup2 (int, int);
 115 static void HLE_Fixup3 (int, int);
 116 static void CMPXCHG8B_Fixup (int, int);
 117 static void XMM_Fixup (int, int);
 118 static void CRC32_Fixup (int, int);
 119 static void FXSAVE_Fixup (int, int);
 120 static void PCMPESTR_Fixup (int, int);
 121 static void OP_LWPCB_E (int, int);
 122 static void OP_LWP_E (int, int);
 123 static void OP_Vex_2src_1 (int, int);
 124 static void OP_Vex_2src_2 (int, int);
 125
 126 static void MOVBE_Fixup (int, int);
 127
 128 static void OP_Mask (int, int);
 129
 130 struct dis_private {
 131   /* Points to first byte not fetched.  */
 132   bfd_byte *max_fetched;
 133   bfd_byte the_buffer[MAX_MNEM_SIZE];
 134   bfd_vma insn_start;
 135   int orig_sizeflag;
 136   OPCODES_SIGJMP_BUF bailout;
 137 };
 138
 139 enum address_mode
 140 {
 141   mode_16bit,
 142   mode_32bit,
 143   mode_64bit
 144 };
 145
 146 enum address_mode address_mode;
 147
 148 /* Flags for the prefixes for the current instruction.  See below.  */
 149 static int prefixes;
 150
 151 /* REX prefix the current instruction.  See below.  */
 152 static int rex;
 153 /* Bits of REX we've already used.  */
 154 static int rex_used;
 155 /* REX bits in original REX prefix ignored.  */
 156 static int rex_ignored;
 157 /* Mark parts used in the REX prefix.  When we are testing for
 158    empty prefix (for 8bit register REX extension), just mask it
 159    out.  Otherwise test for REX bit is excuse for existence of REX
 160    only in case value is nonzero.  */
 161 #define USED_REX(value)                                 \
 162   {                                                     \
 163     if (value)                                          \
 164       {                                                 \
 165         if ((rex & value))                              \
 166           rex_used |= (value) | REX_OPCODE;             \
 167       }                                                 \
 168     else                                                \
 169       rex_used |= REX_OPCODE;                           \
 170   }
 171
 172 /* Flags for prefixes which we somehow handled when printing the
 173    current instruction.  */
 174 static int used_prefixes;
 175
 176 /* Flags stored in PREFIXES.  */
 177 #define PREFIX_REPZ 1
 178 #define PREFIX_REPNZ 2
 179 #define PREFIX_LOCK 4
 180 #define PREFIX_CS 8
 181 #define PREFIX_SS 0x10
 182 #define PREFIX_DS 0x20
 183 #define PREFIX_ES 0x40
 184 #define PREFIX_FS 0x80
 185 #define PREFIX_GS 0x100
 186 #define PREFIX_DATA 0x200
 187 #define PREFIX_ADDR 0x400
 188 #define PREFIX_FWAIT 0x800
 189
 190 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 191    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 192    on error.  */
 193 #define FETCH_DATA(info, addr) \
 194   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 195    ? 1 : fetch_data ((info), (addr)))
 196
 197 static int
 198 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 199 {
 200   int status;
 201   struct dis_private *priv = (struct dis_private *) info->private_data;
 202   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 203
 204   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 205     status = (*info->read_memory_func) (start,
 206                                         priv->max_fetched,
 207                                         addr - priv->max_fetched,
 208                                         info);
 209   else
 210     status = -1;
 211   if (status != 0)
 212     {
 213       /* If we did manage to read at least one byte, then
 214          print_insn_i386 will do something sensible.  Otherwise, print
 215          an error.  We do that here because this is where we know
 216          STATUS.  */
 217       if (priv->max_fetched == priv->the_buffer)
 218         (*info->memory_error_func) (status, start, info);
 219       OPCODES_SIGLONGJMP (priv->bailout, 1);
 220     }
 221   else
 222     priv->max_fetched = addr;
 223   return 1;
 224 }
 225
 226 /* Possible values for prefix requirement.  */
 227 #define PREFIX_IGNORED_SHIFT    16
 228 #define PREFIX_IGNORED_REPZ     (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
 229 #define PREFIX_IGNORED_REPNZ    (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
 230 #define PREFIX_IGNORED_DATA     (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
 231 #define PREFIX_IGNORED_ADDR     (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
 232 #define PREFIX_IGNORED_LOCK     (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
 233
 234 /* Opcode prefixes.  */
 235 #define PREFIX_OPCODE           (PREFIX_REPZ \
 236                                  | PREFIX_REPNZ \
 237                                  | PREFIX_DATA)
 238
 239 /* Prefixes ignored.  */
 240 #define PREFIX_IGNORED          (PREFIX_IGNORED_REPZ \
 241                                  | PREFIX_IGNORED_REPNZ \
 242                                  | PREFIX_IGNORED_DATA)
 243
 244 #define XX { NULL, 0 }
 245 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
 246
 247 #define Eb { OP_E, b_mode }
 248 #define Ebnd { OP_E, bnd_mode }
 249 #define EbS { OP_E, b_swap_mode }
 250 #define EbndS { OP_E, bnd_swap_mode }
 251 #define Ev { OP_E, v_mode }
 252 #define Eva { OP_E, va_mode }
 253 #define Ev_bnd { OP_E, v_bnd_mode }
 254 #define EvS { OP_E, v_swap_mode }
 255 #define Ed { OP_E, d_mode }
 256 #define Edq { OP_E, dq_mode }
 257 #define Edqw { OP_E, dqw_mode }
 258 #define Edqb { OP_E, dqb_mode }
 259 #define Edb { OP_E, db_mode }
 260 #define Edw { OP_E, dw_mode }
 261 #define Edqd { OP_E, dqd_mode }
 262 #define Edqa { OP_E, dqa_mode }
 263 #define Eq { OP_E, q_mode }
 264 #define indirEv { OP_indirE, indir_v_mode }
 265 #define indirEp { OP_indirE, f_mode }
 266 #define stackEv { OP_E, stack_v_mode }
 267 #define Em { OP_E, m_mode }
 268 #define Ew { OP_E, w_mode }
 269 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 270 #define Ma { OP_M, a_mode }
 271 #define Mb { OP_M, b_mode }
 272 #define Md { OP_M, d_mode }
 273 #define Mo { OP_M, o_mode }
 274 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 275 #define Mq { OP_M, q_mode }
 276 #define Mv_bnd { OP_M, v_bndmk_mode }
 277 #define Mx { OP_M, x_mode }
 278 #define Mxmm { OP_M, xmm_mode }
 279 #define Gb { OP_G, b_mode }
 280 #define Gbnd { OP_G, bnd_mode }
 281 #define Gv { OP_G, v_mode }
 282 #define Gd { OP_G, d_mode }
 283 #define Gdq { OP_G, dq_mode }
 284 #define Gm { OP_G, m_mode }
 285 #define Gva { OP_G, va_mode }
 286 #define Gw { OP_G, w_mode }
 287 #define Rd { OP_R, d_mode }
 288 #define Rdq { OP_R, dq_mode }
 289 #define Rm { OP_R, m_mode }
 290 #define Ib { OP_I, b_mode }
 291 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 292 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 293 #define Iv { OP_I, v_mode }
 294 #define sIv { OP_sI, v_mode }
 295 #define Iq { OP_I, q_mode }
 296 #define Iv64 { OP_I64, v_mode }
 297 #define Iw { OP_I, w_mode }
 298 #define I1 { OP_I, const_1_mode }
 299 #define Jb { OP_J, b_mode }
 300 #define Jv { OP_J, v_mode }
 301 #define Cm { OP_C, m_mode }
 302 #define Dm { OP_D, m_mode }
 303 #define Td { OP_T, d_mode }
 304 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 305
 306 #define RMeAX { OP_REG, eAX_reg }
 307 #define RMeBX { OP_REG, eBX_reg }
 308 #define RMeCX { OP_REG, eCX_reg }
 309 #define RMeDX { OP_REG, eDX_reg }
 310 #define RMeSP { OP_REG, eSP_reg }
 311 #define RMeBP { OP_REG, eBP_reg }
 312 #define RMeSI { OP_REG, eSI_reg }
 313 #define RMeDI { OP_REG, eDI_reg }
 314 #define RMrAX { OP_REG, rAX_reg }
 315 #define RMrBX { OP_REG, rBX_reg }
 316 #define RMrCX { OP_REG, rCX_reg }
 317 #define RMrDX { OP_REG, rDX_reg }
 318 #define RMrSP { OP_REG, rSP_reg }
 319 #define RMrBP { OP_REG, rBP_reg }
 320 #define RMrSI { OP_REG, rSI_reg }
 321 #define RMrDI { OP_REG, rDI_reg }
 322 #define RMAL { OP_REG, al_reg }
 323 #define RMCL { OP_REG, cl_reg }
 324 #define RMDL { OP_REG, dl_reg }
 325 #define RMBL { OP_REG, bl_reg }
 326 #define RMAH { OP_REG, ah_reg }
 327 #define RMCH { OP_REG, ch_reg }
 328 #define RMDH { OP_REG, dh_reg }
 329 #define RMBH { OP_REG, bh_reg }
 330 #define RMAX { OP_REG, ax_reg }
 331 #define RMDX { OP_REG, dx_reg }
 332
 333 #define eAX { OP_IMREG, eAX_reg }
 334 #define eBX { OP_IMREG, eBX_reg }
 335 #define eCX { OP_IMREG, eCX_reg }
 336 #define eDX { OP_IMREG, eDX_reg }
 337 #define eSP { OP_IMREG, eSP_reg }
 338 #define eBP { OP_IMREG, eBP_reg }
 339 #define eSI { OP_IMREG, eSI_reg }
 340 #define eDI { OP_IMREG, eDI_reg }
 341 #define AL { OP_IMREG, al_reg }
 342 #define CL { OP_IMREG, cl_reg }
 343 #define DL { OP_IMREG, dl_reg }
 344 #define BL { OP_IMREG, bl_reg }
 345 #define AH { OP_IMREG, ah_reg }
 346 #define CH { OP_IMREG, ch_reg }
 347 #define DH { OP_IMREG, dh_reg }
 348 #define BH { OP_IMREG, bh_reg }
 349 #define AX { OP_IMREG, ax_reg }
 350 #define DX { OP_IMREG, dx_reg }
 351 #define zAX { OP_IMREG, z_mode_ax_reg }
 352 #define indirDX { OP_IMREG, indir_dx_reg }
 353
 354 #define Sw { OP_SEG, w_mode }
 355 #define Sv { OP_SEG, v_mode }
 356 #define Ap { OP_DIR, 0 }
 357 #define Ob { OP_OFF64, b_mode }
 358 #define Ov { OP_OFF64, v_mode }
 359 #define Xb { OP_DSreg, eSI_reg }
 360 #define Xv { OP_DSreg, eSI_reg }
 361 #define Xz { OP_DSreg, eSI_reg }
 362 #define Yb { OP_ESreg, eDI_reg }
 363 #define Yv { OP_ESreg, eDI_reg }
 364 #define DSBX { OP_DSreg, eBX_reg }
 365
 366 #define es { OP_REG, es_reg }
 367 #define ss { OP_REG, ss_reg }
 368 #define cs { OP_REG, cs_reg }
 369 #define ds { OP_REG, ds_reg }
 370 #define fs { OP_REG, fs_reg }
 371 #define gs { OP_REG, gs_reg }
 372
 373 #define MX { OP_MMX, 0 }
 374 #define XM { OP_XMM, 0 }
 375 #define XMScalar { OP_XMM, scalar_mode }
 376 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 377 #define XMM { OP_XMM, xmm_mode }
 378 #define XMxmmq { OP_XMM, xmmq_mode }
 379 #define EM { OP_EM, v_mode }
 380 #define EMS { OP_EM, v_swap_mode }
 381 #define EMd { OP_EM, d_mode }
 382 #define EMx { OP_EM, x_mode }
 383 #define EXbScalar { OP_EX, b_scalar_mode }
 384 #define EXw { OP_EX, w_mode }
 385 #define EXwScalar { OP_EX, w_scalar_mode }
 386 #define EXd { OP_EX, d_mode }
 387 #define EXdScalar { OP_EX, d_scalar_mode }
 388 #define EXdS { OP_EX, d_swap_mode }
 389 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
 390 #define EXq { OP_EX, q_mode }
 391 #define EXqScalar { OP_EX, q_scalar_mode }
 392 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
 393 #define EXqS { OP_EX, q_swap_mode }
 394 #define EXx { OP_EX, x_mode }
 395 #define EXxS { OP_EX, x_swap_mode }
 396 #define EXxmm { OP_EX, xmm_mode }
 397 #define EXymm { OP_EX, ymm_mode }
 398 #define EXxmmq { OP_EX, xmmq_mode }
 399 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 400 #define EXxmm_mb { OP_EX, xmm_mb_mode }
 401 #define EXxmm_mw { OP_EX, xmm_mw_mode }
 402 #define EXxmm_md { OP_EX, xmm_md_mode }
 403 #define EXxmm_mq { OP_EX, xmm_mq_mode }
 404 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
 405 #define EXxmmdw { OP_EX, xmmdw_mode }
 406 #define EXxmmqd { OP_EX, xmmqd_mode }
 407 #define EXymmq { OP_EX, ymmq_mode }
 408 #define EXVexWdq { OP_EX, vex_w_dq_mode }
 409 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 410 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 411 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 412 #define MS { OP_MS, v_mode }
 413 #define XS { OP_XS, v_mode }
 414 #define EMCq { OP_EMC, q_mode }
 415 #define MXC { OP_MXC, 0 }
 416 #define OPSUF { OP_3DNowSuffix, 0 }
 417 #define CMP { CMP_Fixup, 0 }
 418 #define XMM0 { XMM_Fixup, 0 }
 419 #define FXSAVE { FXSAVE_Fixup, 0 }
 420 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
 421 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
 422
 423 #define Vex { OP_VEX, vex_mode }
 424 #define VexScalar { OP_VEX, vex_scalar_mode }
 425 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 426 #define Vex128 { OP_VEX, vex128_mode }
 427 #define Vex256 { OP_VEX, vex256_mode }
 428 #define VexGdq { OP_VEX, dq_mode }
 429 #define EXdVex { OP_EX_Vex, d_mode }
 430 #define EXdVexS { OP_EX_Vex, d_swap_mode }
 431 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
 432 #define EXqVex { OP_EX_Vex, q_mode }
 433 #define EXqVexS { OP_EX_Vex, q_swap_mode }
 434 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
 435 #define EXVexW { OP_EX_VexW, x_mode }
 436 #define EXdVexW { OP_EX_VexW, d_mode }
 437 #define EXqVexW { OP_EX_VexW, q_mode }
 438 #define EXVexImmW { OP_EX_VexImmW, x_mode }
 439 #define XMVex { OP_XMM_Vex, 0 }
 440 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
 441 #define XMVexW { OP_XMM_VexW, 0 }
 442 #define XMVexI4 { OP_REG_VexI4, x_mode }
 443 #define PCLMUL { PCLMUL_Fixup, 0 }
 444 #define VCMP { VCMP_Fixup, 0 }
 445 #define VPCMP { VPCMP_Fixup, 0 }
 446 #define VPCOM { VPCOM_Fixup, 0 }
 447
 448 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 449 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
 450 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 451
 452 #define XMask { OP_Mask, mask_mode }
 453 #define MaskG { OP_G, mask_mode }
 454 #define MaskE { OP_E, mask_mode }
 455 #define MaskBDE { OP_E, mask_bd_mode }
 456 #define MaskR { OP_R, mask_mode }
 457 #define MaskVex { OP_VEX, mask_mode }
 458
 459 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 460 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
 461 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 462 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
 463
 464 /* Used handle "rep" prefix for string instructions.  */
 465 #define Xbr { REP_Fixup, eSI_reg }
 466 #define Xvr { REP_Fixup, eSI_reg }
 467 #define Ybr { REP_Fixup, eDI_reg }
 468 #define Yvr { REP_Fixup, eDI_reg }
 469 #define Yzr { REP_Fixup, eDI_reg }
 470 #define indirDXr { REP_Fixup, indir_dx_reg }
 471 #define ALr { REP_Fixup, al_reg }
 472 #define eAXr { REP_Fixup, eAX_reg }
 473
 474 /* Used handle HLE prefix for lockable instructions.  */
 475 #define Ebh1 { HLE_Fixup1, b_mode }
 476 #define Evh1 { HLE_Fixup1, v_mode }
 477 #define Ebh2 { HLE_Fixup2, b_mode }
 478 #define Evh2 { HLE_Fixup2, v_mode }
 479 #define Ebh3 { HLE_Fixup3, b_mode }
 480 #define Evh3 { HLE_Fixup3, v_mode }
 481
 482 #define BND { BND_Fixup, 0 }
 483 #define NOTRACK { NOTRACK_Fixup, 0 }
 484
 485 #define cond_jump_flag { NULL, cond_jump_mode }
 486 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 487
 488 /* bits in sizeflag */
 489 #define SUFFIX_ALWAYS 4
 490 #define AFLAG 2
 491 #define DFLAG 1
 492
 493 enum
 494 {
 495   /* byte operand */
 496   b_mode = 1,
 497   /* byte operand with operand swapped */
 498   b_swap_mode,
 499   /* byte operand, sign extend like 'T' suffix */
 500   b_T_mode,
 501   /* operand size depends on prefixes */
 502   v_mode,
 503   /* operand size depends on prefixes with operand swapped */
 504   v_swap_mode,
 505   /* operand size depends on address prefix */
 506   va_mode,
 507   /* word operand */
 508   w_mode,
 509   /* double word operand  */
 510   d_mode,
 511   /* double word operand with operand swapped */
 512   d_swap_mode,
 513   /* quad word operand */
 514   q_mode,
 515   /* quad word operand with operand swapped */
 516   q_swap_mode,
 517   /* ten-byte operand */
 518   t_mode,
 519   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 520      broadcast enabled.  */
 521   x_mode,
 522   /* Similar to x_mode, but with different EVEX mem shifts.  */
 523   evex_x_gscat_mode,
 524   /* Similar to x_mode, but with disabled broadcast.  */
 525   evex_x_nobcst_mode,
 526   /* Similar to x_mode, but with operands swapped and disabled broadcast
 527      in EVEX.  */
 528   x_swap_mode,
 529   /* 16-byte XMM operand */
 530   xmm_mode,
 531   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 532      memory operand (depending on vector length).  Broadcast isn't
 533      allowed.  */
 534   xmmq_mode,
 535   /* Same as xmmq_mode, but broadcast is allowed.  */
 536   evex_half_bcst_xmmq_mode,
 537   /* XMM register or byte memory operand */
 538   xmm_mb_mode,
 539   /* XMM register or word memory operand */
 540   xmm_mw_mode,
 541   /* XMM register or double word memory operand */
 542   xmm_md_mode,
 543   /* XMM register or quad word memory operand */
 544   xmm_mq_mode,
 545   /* XMM register or double/quad word memory operand, depending on
 546      VEX.W.  */
 547   xmm_mdq_mode,
 548   /* 16-byte XMM, word, double word or quad word operand.  */
 549   xmmdw_mode,
 550   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 551   xmmqd_mode,
 552   /* 32-byte YMM operand */
 553   ymm_mode,
 554   /* quad word, ymmword or zmmword memory operand.  */
 555   ymmq_mode,
 556   /* 32-byte YMM or 16-byte word operand */
 557   ymmxmm_mode,
 558   /* d_mode in 32bit, q_mode in 64bit mode.  */
 559   m_mode,
 560   /* pair of v_mode operands */
 561   a_mode,
 562   cond_jump_mode,
 563   loop_jcxz_mode,
 564   v_bnd_mode,
 565   /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode.  */
 566   v_bndmk_mode,
 567   /* operand size depends on REX prefixes.  */
 568   dq_mode,
 569   /* registers like dq_mode, memory like w_mode.  */
 570   dqw_mode,
 571   /* bounds operand */
 572   bnd_mode,
 573   /* bounds operand with operand swapped */
 574   bnd_swap_mode,
 575   /* 4- or 6-byte pointer operand */
 576   f_mode,
 577   const_1_mode,
 578   /* v_mode for indirect branch opcodes.  */
 579   indir_v_mode,
 580   /* v_mode for stack-related opcodes.  */
 581   stack_v_mode,
 582   /* non-quad operand size depends on prefixes */
 583   z_mode,
 584   /* 16-byte operand */
 585   o_mode,
 586   /* registers like dq_mode, memory like b_mode.  */
 587   dqb_mode,
 588   /* registers like d_mode, memory like b_mode.  */
 589   db_mode,
 590   /* registers like d_mode, memory like w_mode.  */
 591   dw_mode,
 592   /* registers like dq_mode, memory like d_mode.  */
 593   dqd_mode,
 594   /* operand size depends on the W bit as well as address mode.  */
 595   dqa_mode,
 596   /* normal vex mode */
 597   vex_mode,
 598   /* 128bit vex mode */
 599   vex128_mode,
 600   /* 256bit vex mode */
 601   vex256_mode,
 602   /* operand size depends on the VEX.W bit.  */
 603   vex_w_dq_mode,
 604
 605   /* Similar to vex_w_dq_mode, with VSIB dword indices.  */
 606   vex_vsib_d_w_dq_mode,
 607   /* Similar to vex_vsib_d_w_dq_mode, with smaller memory.  */
 608   vex_vsib_d_w_d_mode,
 609   /* Similar to vex_w_dq_mode, with VSIB qword indices.  */
 610   vex_vsib_q_w_dq_mode,
 611   /* Similar to vex_vsib_q_w_dq_mode, with smaller memory.  */
 612   vex_vsib_q_w_d_mode,
 613
 614   /* scalar, ignore vector length.  */
 615   scalar_mode,
 616   /* like b_mode, ignore vector length.  */
 617   b_scalar_mode,
 618   /* like w_mode, ignore vector length.  */
 619   w_scalar_mode,
 620   /* like d_mode, ignore vector length.  */
 621   d_scalar_mode,
 622   /* like d_swap_mode, ignore vector length.  */
 623   d_scalar_swap_mode,
 624   /* like q_mode, ignore vector length.  */
 625   q_scalar_mode,
 626   /* like q_swap_mode, ignore vector length.  */
 627   q_scalar_swap_mode,
 628   /* like vex_mode, ignore vector length.  */
 629   vex_scalar_mode,
 630   /* like vex_w_dq_mode, ignore vector length.  */
 631   vex_scalar_w_dq_mode,
 632
 633   /* Static rounding.  */
 634   evex_rounding_mode,
 635   /* Static rounding, 64-bit mode only.  */
 636   evex_rounding_64_mode,
 637   /* Supress all exceptions.  */
 638   evex_sae_mode,
 639
 640   /* Mask register operand.  */
 641   mask_mode,
 642   /* Mask register operand.  */
 643   mask_bd_mode,
 644
 645   es_reg,
 646   cs_reg,
 647   ss_reg,
 648   ds_reg,
 649   fs_reg,
 650   gs_reg,
 651
 652   eAX_reg,
 653   eCX_reg,
 654   eDX_reg,
 655   eBX_reg,
 656   eSP_reg,
 657   eBP_reg,
 658   eSI_reg,
 659   eDI_reg,
 660
 661   al_reg,
 662   cl_reg,
 663   dl_reg,
 664   bl_reg,
 665   ah_reg,
 666   ch_reg,
 667   dh_reg,
 668   bh_reg,
 669
 670   ax_reg,
 671   cx_reg,
 672   dx_reg,
 673   bx_reg,
 674   sp_reg,
 675   bp_reg,
 676   si_reg,
 677   di_reg,
 678
 679   rAX_reg,
 680   rCX_reg,
 681   rDX_reg,
 682   rBX_reg,
 683   rSP_reg,
 684   rBP_reg,
 685   rSI_reg,
 686   rDI_reg,
 687
 688   z_mode_ax_reg,
 689   indir_dx_reg
 690 };
 691
 692 enum
 693 {
 694   FLOATCODE = 1,
 695   USE_REG_TABLE,
 696   USE_MOD_TABLE,
 697   USE_RM_TABLE,
 698   USE_PREFIX_TABLE,
 699   USE_X86_64_TABLE,
 700   USE_3BYTE_TABLE,
 701   USE_XOP_8F_TABLE,
 702   USE_VEX_C4_TABLE,
 703   USE_VEX_C5_TABLE,
 704   USE_VEX_LEN_TABLE,
 705   USE_VEX_W_TABLE,
 706   USE_EVEX_TABLE,
 707   USE_EVEX_LEN_TABLE
 708 };
 709
 710 #define FLOAT                   NULL, { { NULL, FLOATCODE } }, 0
 711
 712 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }, 0
 713 #define DIS386_PREFIX(T, I, P)          NULL, { { NULL, (T)}, { NULL,  (I) } }, P
 714 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 715 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 716 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 717 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 718 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 719 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 720 #define THREE_BYTE_TABLE_PREFIX(I, P)   DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
 721 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 722 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 723 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 724 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 725 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 726 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 727 #define EVEX_LEN_TABLE(I)       DIS386 (USE_EVEX_LEN_TABLE, (I))
 728
 729 enum
 730 {
 731   REG_80 = 0,
 732   REG_81,
 733   REG_83,
 734   REG_8F,
 735   REG_C0,
 736   REG_C1,
 737   REG_C6,
 738   REG_C7,
 739   REG_D0,
 740   REG_D1,
 741   REG_D2,
 742   REG_D3,
 743   REG_F6,
 744   REG_F7,
 745   REG_FE,
 746   REG_FF,
 747   REG_0F00,
 748   REG_0F01,
 749   REG_0F0D,
 750   REG_0F18,
 751   REG_0F1C_MOD_0,
 752   REG_0F1E_MOD_3,
 753   REG_0F71,
 754   REG_0F72,
 755   REG_0F73,
 756   REG_0FA6,
 757   REG_0FA7,
 758   REG_0FAE,
 759   REG_0FBA,
 760   REG_0FC7,
 761   REG_VEX_0F71,
 762   REG_VEX_0F72,
 763   REG_VEX_0F73,
 764   REG_VEX_0FAE,
 765   REG_VEX_0F38F3,
 766   REG_XOP_LWPCB,
 767   REG_XOP_LWP,
 768   REG_XOP_TBM_01,
 769   REG_XOP_TBM_02,
 770
 771   REG_EVEX_0F71,
 772   REG_EVEX_0F72,
 773   REG_EVEX_0F73,
 774   REG_EVEX_0F38C6,
 775   REG_EVEX_0F38C7
 776 };
 777
 778 enum
 779 {
 780   MOD_8D = 0,
 781   MOD_C6_REG_7,
 782   MOD_C7_REG_7,
 783   MOD_FF_REG_3,
 784   MOD_FF_REG_5,
 785   MOD_0F01_REG_0,
 786   MOD_0F01_REG_1,
 787   MOD_0F01_REG_2,
 788   MOD_0F01_REG_3,
 789   MOD_0F01_REG_5,
 790   MOD_0F01_REG_7,
 791   MOD_0F12_PREFIX_0,
 792   MOD_0F13,
 793   MOD_0F16_PREFIX_0,
 794   MOD_0F17,
 795   MOD_0F18_REG_0,
 796   MOD_0F18_REG_1,
 797   MOD_0F18_REG_2,
 798   MOD_0F18_REG_3,
 799   MOD_0F18_REG_4,
 800   MOD_0F18_REG_5,
 801   MOD_0F18_REG_6,
 802   MOD_0F18_REG_7,
 803   MOD_0F1A_PREFIX_0,
 804   MOD_0F1B_PREFIX_0,
 805   MOD_0F1B_PREFIX_1,
 806   MOD_0F1C_PREFIX_0,
 807   MOD_0F1E_PREFIX_1,
 808   MOD_0F24,
 809   MOD_0F26,
 810   MOD_0F2B_PREFIX_0,
 811   MOD_0F2B_PREFIX_1,
 812   MOD_0F2B_PREFIX_2,
 813   MOD_0F2B_PREFIX_3,
 814   MOD_0F51,
 815   MOD_0F71_REG_2,
 816   MOD_0F71_REG_4,
 817   MOD_0F71_REG_6,
 818   MOD_0F72_REG_2,
 819   MOD_0F72_REG_4,
 820   MOD_0F72_REG_6,
 821   MOD_0F73_REG_2,
 822   MOD_0F73_REG_3,
 823   MOD_0F73_REG_6,
 824   MOD_0F73_REG_7,
 825   MOD_0FAE_REG_0,
 826   MOD_0FAE_REG_1,
 827   MOD_0FAE_REG_2,
 828   MOD_0FAE_REG_3,
 829   MOD_0FAE_REG_4,
 830   MOD_0FAE_REG_5,
 831   MOD_0FAE_REG_6,
 832   MOD_0FAE_REG_7,
 833   MOD_0FB2,
 834   MOD_0FB4,
 835   MOD_0FB5,
 836   MOD_0FC3,
 837   MOD_0FC7_REG_3,
 838   MOD_0FC7_REG_4,
 839   MOD_0FC7_REG_5,
 840   MOD_0FC7_REG_6,
 841   MOD_0FC7_REG_7,
 842   MOD_0FD7,
 843   MOD_0FE7_PREFIX_2,
 844   MOD_0FF0_PREFIX_3,
 845   MOD_0F382A_PREFIX_2,
 846   MOD_0F38F5_PREFIX_2,
 847   MOD_0F38F6_PREFIX_0,
 848   MOD_0F38F8_PREFIX_2,
 849   MOD_0F38F9_PREFIX_0,
 850   MOD_62_32BIT,
 851   MOD_C4_32BIT,
 852   MOD_C5_32BIT,
 853   MOD_VEX_0F12_PREFIX_0,
 854   MOD_VEX_0F13,
 855   MOD_VEX_0F16_PREFIX_0,
 856   MOD_VEX_0F17,
 857   MOD_VEX_0F2B,
 858   MOD_VEX_W_0_0F41_P_0_LEN_1,
 859   MOD_VEX_W_1_0F41_P_0_LEN_1,
 860   MOD_VEX_W_0_0F41_P_2_LEN_1,
 861   MOD_VEX_W_1_0F41_P_2_LEN_1,
 862   MOD_VEX_W_0_0F42_P_0_LEN_1,
 863   MOD_VEX_W_1_0F42_P_0_LEN_1,
 864   MOD_VEX_W_0_0F42_P_2_LEN_1,
 865   MOD_VEX_W_1_0F42_P_2_LEN_1,
 866   MOD_VEX_W_0_0F44_P_0_LEN_1,
 867   MOD_VEX_W_1_0F44_P_0_LEN_1,
 868   MOD_VEX_W_0_0F44_P_2_LEN_1,
 869   MOD_VEX_W_1_0F44_P_2_LEN_1,
 870   MOD_VEX_W_0_0F45_P_0_LEN_1,
 871   MOD_VEX_W_1_0F45_P_0_LEN_1,
 872   MOD_VEX_W_0_0F45_P_2_LEN_1,
 873   MOD_VEX_W_1_0F45_P_2_LEN_1,
 874   MOD_VEX_W_0_0F46_P_0_LEN_1,
 875   MOD_VEX_W_1_0F46_P_0_LEN_1,
 876   MOD_VEX_W_0_0F46_P_2_LEN_1,
 877   MOD_VEX_W_1_0F46_P_2_LEN_1,
 878   MOD_VEX_W_0_0F47_P_0_LEN_1,
 879   MOD_VEX_W_1_0F47_P_0_LEN_1,
 880   MOD_VEX_W_0_0F47_P_2_LEN_1,
 881   MOD_VEX_W_1_0F47_P_2_LEN_1,
 882   MOD_VEX_W_0_0F4A_P_0_LEN_1,
 883   MOD_VEX_W_1_0F4A_P_0_LEN_1,
 884   MOD_VEX_W_0_0F4A_P_2_LEN_1,
 885   MOD_VEX_W_1_0F4A_P_2_LEN_1,
 886   MOD_VEX_W_0_0F4B_P_0_LEN_1,
 887   MOD_VEX_W_1_0F4B_P_0_LEN_1,
 888   MOD_VEX_W_0_0F4B_P_2_LEN_1,
 889   MOD_VEX_0F50,
 890   MOD_VEX_0F71_REG_2,
 891   MOD_VEX_0F71_REG_4,
 892   MOD_VEX_0F71_REG_6,
 893   MOD_VEX_0F72_REG_2,
 894   MOD_VEX_0F72_REG_4,
 895   MOD_VEX_0F72_REG_6,
 896   MOD_VEX_0F73_REG_2,
 897   MOD_VEX_0F73_REG_3,
 898   MOD_VEX_0F73_REG_6,
 899   MOD_VEX_0F73_REG_7,
 900   MOD_VEX_W_0_0F91_P_0_LEN_0,
 901   MOD_VEX_W_1_0F91_P_0_LEN_0,
 902   MOD_VEX_W_0_0F91_P_2_LEN_0,
 903   MOD_VEX_W_1_0F91_P_2_LEN_0,
 904   MOD_VEX_W_0_0F92_P_0_LEN_0,
 905   MOD_VEX_W_0_0F92_P_2_LEN_0,
 906   MOD_VEX_W_0_0F92_P_3_LEN_0,
 907   MOD_VEX_W_1_0F92_P_3_LEN_0,
 908   MOD_VEX_W_0_0F93_P_0_LEN_0,
 909   MOD_VEX_W_0_0F93_P_2_LEN_0,
 910   MOD_VEX_W_0_0F93_P_3_LEN_0,
 911   MOD_VEX_W_1_0F93_P_3_LEN_0,
 912   MOD_VEX_W_0_0F98_P_0_LEN_0,
 913   MOD_VEX_W_1_0F98_P_0_LEN_0,
 914   MOD_VEX_W_0_0F98_P_2_LEN_0,
 915   MOD_VEX_W_1_0F98_P_2_LEN_0,
 916   MOD_VEX_W_0_0F99_P_0_LEN_0,
 917   MOD_VEX_W_1_0F99_P_0_LEN_0,
 918   MOD_VEX_W_0_0F99_P_2_LEN_0,
 919   MOD_VEX_W_1_0F99_P_2_LEN_0,
 920   MOD_VEX_0FAE_REG_2,
 921   MOD_VEX_0FAE_REG_3,
 922   MOD_VEX_0FD7_PREFIX_2,
 923   MOD_VEX_0FE7_PREFIX_2,
 924   MOD_VEX_0FF0_PREFIX_3,
 925   MOD_VEX_0F381A_PREFIX_2,
 926   MOD_VEX_0F382A_PREFIX_2,
 927   MOD_VEX_0F382C_PREFIX_2,
 928   MOD_VEX_0F382D_PREFIX_2,
 929   MOD_VEX_0F382E_PREFIX_2,
 930   MOD_VEX_0F382F_PREFIX_2,
 931   MOD_VEX_0F385A_PREFIX_2,
 932   MOD_VEX_0F388C_PREFIX_2,
 933   MOD_VEX_0F388E_PREFIX_2,
 934   MOD_VEX_W_0_0F3A30_P_2_LEN_0,
 935   MOD_VEX_W_1_0F3A30_P_2_LEN_0,
 936   MOD_VEX_W_0_0F3A31_P_2_LEN_0,
 937   MOD_VEX_W_1_0F3A31_P_2_LEN_0,
 938   MOD_VEX_W_0_0F3A32_P_2_LEN_0,
 939   MOD_VEX_W_1_0F3A32_P_2_LEN_0,
 940   MOD_VEX_W_0_0F3A33_P_2_LEN_0,
 941   MOD_VEX_W_1_0F3A33_P_2_LEN_0,
 942
 943   MOD_EVEX_0F10_PREFIX_1,
 944   MOD_EVEX_0F10_PREFIX_3,
 945   MOD_EVEX_0F11_PREFIX_1,
 946   MOD_EVEX_0F11_PREFIX_3,
 947   MOD_EVEX_0F12_PREFIX_0,
 948   MOD_EVEX_0F16_PREFIX_0,
 949   MOD_EVEX_0F38C6_REG_1,
 950   MOD_EVEX_0F38C6_REG_2,
 951   MOD_EVEX_0F38C6_REG_5,
 952   MOD_EVEX_0F38C6_REG_6,
 953   MOD_EVEX_0F38C7_REG_1,
 954   MOD_EVEX_0F38C7_REG_2,
 955   MOD_EVEX_0F38C7_REG_5,
 956   MOD_EVEX_0F38C7_REG_6
 957 };
 958
 959 enum
 960 {
 961   RM_C6_REG_7 = 0,
 962   RM_C7_REG_7,
 963   RM_0F01_REG_0,
 964   RM_0F01_REG_1,
 965   RM_0F01_REG_2,
 966   RM_0F01_REG_3,
 967   RM_0F01_REG_5,
 968   RM_0F01_REG_7,
 969   RM_0F1E_MOD_3_REG_7,
 970   RM_0FAE_REG_6,
 971   RM_0FAE_REG_7
 972 };
 973
 974 enum
 975 {
 976   PREFIX_90 = 0,
 977   PREFIX_MOD_0_0F01_REG_5,
 978   PREFIX_MOD_3_0F01_REG_5_RM_0,
 979   PREFIX_MOD_3_0F01_REG_5_RM_2,
 980   PREFIX_0F09,
 981   PREFIX_0F10,
 982   PREFIX_0F11,
 983   PREFIX_0F12,
 984   PREFIX_0F16,
 985   PREFIX_0F1A,
 986   PREFIX_0F1B,
 987   PREFIX_0F1C,
 988   PREFIX_0F1E,
 989   PREFIX_0F2A,
 990   PREFIX_0F2B,
 991   PREFIX_0F2C,
 992   PREFIX_0F2D,
 993   PREFIX_0F2E,
 994   PREFIX_0F2F,
 995   PREFIX_0F51,
 996   PREFIX_0F52,
 997   PREFIX_0F53,
 998   PREFIX_0F58,
 999   PREFIX_0F59,
1000   PREFIX_0F5A,
1001   PREFIX_0F5B,
1002   PREFIX_0F5C,
1003   PREFIX_0F5D,
1004   PREFIX_0F5E,
1005   PREFIX_0F5F,
1006   PREFIX_0F60,
1007   PREFIX_0F61,
1008   PREFIX_0F62,
1009   PREFIX_0F6C,
1010   PREFIX_0F6D,
1011   PREFIX_0F6F,
1012   PREFIX_0F70,
1013   PREFIX_0F73_REG_3,
1014   PREFIX_0F73_REG_7,
1015   PREFIX_0F78,
1016   PREFIX_0F79,
1017   PREFIX_0F7C,
1018   PREFIX_0F7D,
1019   PREFIX_0F7E,
1020   PREFIX_0F7F,
1021   PREFIX_0FAE_REG_0,
1022   PREFIX_0FAE_REG_1,
1023   PREFIX_0FAE_REG_2,
1024   PREFIX_0FAE_REG_3,
1025   PREFIX_MOD_0_0FAE_REG_4,
1026   PREFIX_MOD_3_0FAE_REG_4,
1027   PREFIX_MOD_0_0FAE_REG_5,
1028   PREFIX_MOD_3_0FAE_REG_5,
1029   PREFIX_MOD_0_0FAE_REG_6,
1030   PREFIX_MOD_1_0FAE_REG_6,
1031   PREFIX_0FAE_REG_7,
1032   PREFIX_0FB8,
1033   PREFIX_0FBC,
1034   PREFIX_0FBD,
1035   PREFIX_0FC2,
1036   PREFIX_MOD_0_0FC3,
1037   PREFIX_MOD_0_0FC7_REG_6,
1038   PREFIX_MOD_3_0FC7_REG_6,
1039   PREFIX_MOD_3_0FC7_REG_7,
1040   PREFIX_0FD0,
1041   PREFIX_0FD6,
1042   PREFIX_0FE6,
1043   PREFIX_0FE7,
1044   PREFIX_0FF0,
1045   PREFIX_0FF7,
1046   PREFIX_0F3810,
1047   PREFIX_0F3814,
1048   PREFIX_0F3815,
1049   PREFIX_0F3817,
1050   PREFIX_0F3820,
1051   PREFIX_0F3821,
1052   PREFIX_0F3822,
1053   PREFIX_0F3823,
1054   PREFIX_0F3824,
1055   PREFIX_0F3825,
1056   PREFIX_0F3828,
1057   PREFIX_0F3829,
1058   PREFIX_0F382A,
1059   PREFIX_0F382B,
1060   PREFIX_0F3830,
1061   PREFIX_0F3831,
1062   PREFIX_0F3832,
1063   PREFIX_0F3833,
1064   PREFIX_0F3834,
1065   PREFIX_0F3835,
1066   PREFIX_0F3837,
1067   PREFIX_0F3838,
1068   PREFIX_0F3839,
1069   PREFIX_0F383A,
1070   PREFIX_0F383B,
1071   PREFIX_0F383C,
1072   PREFIX_0F383D,
1073   PREFIX_0F383E,
1074   PREFIX_0F383F,
1075   PREFIX_0F3840,
1076   PREFIX_0F3841,
1077   PREFIX_0F3880,
1078   PREFIX_0F3881,
1079   PREFIX_0F3882,
1080   PREFIX_0F38C8,
1081   PREFIX_0F38C9,
1082   PREFIX_0F38CA,
1083   PREFIX_0F38CB,
1084   PREFIX_0F38CC,
1085   PREFIX_0F38CD,
1086   PREFIX_0F38CF,
1087   PREFIX_0F38DB,
1088   PREFIX_0F38DC,
1089   PREFIX_0F38DD,
1090   PREFIX_0F38DE,
1091   PREFIX_0F38DF,
1092   PREFIX_0F38F0,
1093   PREFIX_0F38F1,
1094   PREFIX_0F38F5,
1095   PREFIX_0F38F6,
1096   PREFIX_0F38F8,
1097   PREFIX_0F38F9,
1098   PREFIX_0F3A08,
1099   PREFIX_0F3A09,
1100   PREFIX_0F3A0A,
1101   PREFIX_0F3A0B,
1102   PREFIX_0F3A0C,
1103   PREFIX_0F3A0D,
1104   PREFIX_0F3A0E,
1105   PREFIX_0F3A14,
1106   PREFIX_0F3A15,
1107   PREFIX_0F3A16,
1108   PREFIX_0F3A17,
1109   PREFIX_0F3A20,
1110   PREFIX_0F3A21,
1111   PREFIX_0F3A22,
1112   PREFIX_0F3A40,
1113   PREFIX_0F3A41,
1114   PREFIX_0F3A42,
1115   PREFIX_0F3A44,
1116   PREFIX_0F3A60,
1117   PREFIX_0F3A61,
1118   PREFIX_0F3A62,
1119   PREFIX_0F3A63,
1120   PREFIX_0F3ACC,
1121   PREFIX_0F3ACE,
1122   PREFIX_0F3ACF,
1123   PREFIX_0F3ADF,
1124   PREFIX_VEX_0F10,
1125   PREFIX_VEX_0F11,
1126   PREFIX_VEX_0F12,
1127   PREFIX_VEX_0F16,
1128   PREFIX_VEX_0F2A,
1129   PREFIX_VEX_0F2C,
1130   PREFIX_VEX_0F2D,
1131   PREFIX_VEX_0F2E,
1132   PREFIX_VEX_0F2F,
1133   PREFIX_VEX_0F41,
1134   PREFIX_VEX_0F42,
1135   PREFIX_VEX_0F44,
1136   PREFIX_VEX_0F45,
1137   PREFIX_VEX_0F46,
1138   PREFIX_VEX_0F47,
1139   PREFIX_VEX_0F4A,
1140   PREFIX_VEX_0F4B,
1141   PREFIX_VEX_0F51,
1142   PREFIX_VEX_0F52,
1143   PREFIX_VEX_0F53,
1144   PREFIX_VEX_0F58,
1145   PREFIX_VEX_0F59,
1146   PREFIX_VEX_0F5A,
1147   PREFIX_VEX_0F5B,
1148   PREFIX_VEX_0F5C,
1149   PREFIX_VEX_0F5D,
1150   PREFIX_VEX_0F5E,
1151   PREFIX_VEX_0F5F,
1152   PREFIX_VEX_0F60,
1153   PREFIX_VEX_0F61,
1154   PREFIX_VEX_0F62,
1155   PREFIX_VEX_0F63,
1156   PREFIX_VEX_0F64,
1157   PREFIX_VEX_0F65,
1158   PREFIX_VEX_0F66,
1159   PREFIX_VEX_0F67,
1160   PREFIX_VEX_0F68,
1161   PREFIX_VEX_0F69,
1162   PREFIX_VEX_0F6A,
1163   PREFIX_VEX_0F6B,
1164   PREFIX_VEX_0F6C,
1165   PREFIX_VEX_0F6D,
1166   PREFIX_VEX_0F6E,
1167   PREFIX_VEX_0F6F,
1168   PREFIX_VEX_0F70,
1169   PREFIX_VEX_0F71_REG_2,
1170   PREFIX_VEX_0F71_REG_4,
1171   PREFIX_VEX_0F71_REG_6,
1172   PREFIX_VEX_0F72_REG_2,
1173   PREFIX_VEX_0F72_REG_4,
1174   PREFIX_VEX_0F72_REG_6,
1175   PREFIX_VEX_0F73_REG_2,
1176   PREFIX_VEX_0F73_REG_3,
1177   PREFIX_VEX_0F73_REG_6,
1178   PREFIX_VEX_0F73_REG_7,
1179   PREFIX_VEX_0F74,
1180   PREFIX_VEX_0F75,
1181   PREFIX_VEX_0F76,
1182   PREFIX_VEX_0F77,
1183   PREFIX_VEX_0F7C,
1184   PREFIX_VEX_0F7D,
1185   PREFIX_VEX_0F7E,
1186   PREFIX_VEX_0F7F,
1187   PREFIX_VEX_0F90,
1188   PREFIX_VEX_0F91,
1189   PREFIX_VEX_0F92,
1190   PREFIX_VEX_0F93,
1191   PREFIX_VEX_0F98,
1192   PREFIX_VEX_0F99,
1193   PREFIX_VEX_0FC2,
1194   PREFIX_VEX_0FC4,
1195   PREFIX_VEX_0FC5,
1196   PREFIX_VEX_0FD0,
1197   PREFIX_VEX_0FD1,
1198   PREFIX_VEX_0FD2,
1199   PREFIX_VEX_0FD3,
1200   PREFIX_VEX_0FD4,
1201   PREFIX_VEX_0FD5,
1202   PREFIX_VEX_0FD6,
1203   PREFIX_VEX_0FD7,
1204   PREFIX_VEX_0FD8,
1205   PREFIX_VEX_0FD9,
1206   PREFIX_VEX_0FDA,
1207   PREFIX_VEX_0FDB,
1208   PREFIX_VEX_0FDC,
1209   PREFIX_VEX_0FDD,
1210   PREFIX_VEX_0FDE,
1211   PREFIX_VEX_0FDF,
1212   PREFIX_VEX_0FE0,
1213   PREFIX_VEX_0FE1,
1214   PREFIX_VEX_0FE2,
1215   PREFIX_VEX_0FE3,
1216   PREFIX_VEX_0FE4,
1217   PREFIX_VEX_0FE5,
1218   PREFIX_VEX_0FE6,
1219   PREFIX_VEX_0FE7,
1220   PREFIX_VEX_0FE8,
1221   PREFIX_VEX_0FE9,
1222   PREFIX_VEX_0FEA,
1223   PREFIX_VEX_0FEB,
1224   PREFIX_VEX_0FEC,
1225   PREFIX_VEX_0FED,
1226   PREFIX_VEX_0FEE,
1227   PREFIX_VEX_0FEF,
1228   PREFIX_VEX_0FF0,
1229   PREFIX_VEX_0FF1,
1230   PREFIX_VEX_0FF2,
1231   PREFIX_VEX_0FF3,
1232   PREFIX_VEX_0FF4,
1233   PREFIX_VEX_0FF5,
1234   PREFIX_VEX_0FF6,
1235   PREFIX_VEX_0FF7,
1236   PREFIX_VEX_0FF8,
1237   PREFIX_VEX_0FF9,
1238   PREFIX_VEX_0FFA,
1239   PREFIX_VEX_0FFB,
1240   PREFIX_VEX_0FFC,
1241   PREFIX_VEX_0FFD,
1242   PREFIX_VEX_0FFE,
1243   PREFIX_VEX_0F3800,
1244   PREFIX_VEX_0F3801,
1245   PREFIX_VEX_0F3802,
1246   PREFIX_VEX_0F3803,
1247   PREFIX_VEX_0F3804,
1248   PREFIX_VEX_0F3805,
1249   PREFIX_VEX_0F3806,
1250   PREFIX_VEX_0F3807,
1251   PREFIX_VEX_0F3808,
1252   PREFIX_VEX_0F3809,
1253   PREFIX_VEX_0F380A,
1254   PREFIX_VEX_0F380B,
1255   PREFIX_VEX_0F380C,
1256   PREFIX_VEX_0F380D,
1257   PREFIX_VEX_0F380E,
1258   PREFIX_VEX_0F380F,
1259   PREFIX_VEX_0F3813,
1260   PREFIX_VEX_0F3816,
1261   PREFIX_VEX_0F3817,
1262   PREFIX_VEX_0F3818,
1263   PREFIX_VEX_0F3819,
1264   PREFIX_VEX_0F381A,
1265   PREFIX_VEX_0F381C,
1266   PREFIX_VEX_0F381D,
1267   PREFIX_VEX_0F381E,
1268   PREFIX_VEX_0F3820,
1269   PREFIX_VEX_0F3821,
1270   PREFIX_VEX_0F3822,
1271   PREFIX_VEX_0F3823,
1272   PREFIX_VEX_0F3824,
1273   PREFIX_VEX_0F3825,
1274   PREFIX_VEX_0F3828,
1275   PREFIX_VEX_0F3829,
1276   PREFIX_VEX_0F382A,
1277   PREFIX_VEX_0F382B,
1278   PREFIX_VEX_0F382C,
1279   PREFIX_VEX_0F382D,
1280   PREFIX_VEX_0F382E,
1281   PREFIX_VEX_0F382F,
1282   PREFIX_VEX_0F3830,
1283   PREFIX_VEX_0F3831,
1284   PREFIX_VEX_0F3832,
1285   PREFIX_VEX_0F3833,
1286   PREFIX_VEX_0F3834,
1287   PREFIX_VEX_0F3835,
1288   PREFIX_VEX_0F3836,
1289   PREFIX_VEX_0F3837,
1290   PREFIX_VEX_0F3838,
1291   PREFIX_VEX_0F3839,
1292   PREFIX_VEX_0F383A,
1293   PREFIX_VEX_0F383B,
1294   PREFIX_VEX_0F383C,
1295   PREFIX_VEX_0F383D,
1296   PREFIX_VEX_0F383E,
1297   PREFIX_VEX_0F383F,
1298   PREFIX_VEX_0F3840,
1299   PREFIX_VEX_0F3841,
1300   PREFIX_VEX_0F3845,
1301   PREFIX_VEX_0F3846,
1302   PREFIX_VEX_0F3847,
1303   PREFIX_VEX_0F3858,
1304   PREFIX_VEX_0F3859,
1305   PREFIX_VEX_0F385A,
1306   PREFIX_VEX_0F3878,
1307   PREFIX_VEX_0F3879,
1308   PREFIX_VEX_0F388C,
1309   PREFIX_VEX_0F388E,
1310   PREFIX_VEX_0F3890,
1311   PREFIX_VEX_0F3891,
1312   PREFIX_VEX_0F3892,
1313   PREFIX_VEX_0F3893,
1314   PREFIX_VEX_0F3896,
1315   PREFIX_VEX_0F3897,
1316   PREFIX_VEX_0F3898,
1317   PREFIX_VEX_0F3899,
1318   PREFIX_VEX_0F389A,
1319   PREFIX_VEX_0F389B,
1320   PREFIX_VEX_0F389C,
1321   PREFIX_VEX_0F389D,
1322   PREFIX_VEX_0F389E,
1323   PREFIX_VEX_0F389F,
1324   PREFIX_VEX_0F38A6,
1325   PREFIX_VEX_0F38A7,
1326   PREFIX_VEX_0F38A8,
1327   PREFIX_VEX_0F38A9,
1328   PREFIX_VEX_0F38AA,
1329   PREFIX_VEX_0F38AB,
1330   PREFIX_VEX_0F38AC,
1331   PREFIX_VEX_0F38AD,
1332   PREFIX_VEX_0F38AE,
1333   PREFIX_VEX_0F38AF,
1334   PREFIX_VEX_0F38B6,
1335   PREFIX_VEX_0F38B7,
1336   PREFIX_VEX_0F38B8,
1337   PREFIX_VEX_0F38B9,
1338   PREFIX_VEX_0F38BA,
1339   PREFIX_VEX_0F38BB,
1340   PREFIX_VEX_0F38BC,
1341   PREFIX_VEX_0F38BD,
1342   PREFIX_VEX_0F38BE,
1343   PREFIX_VEX_0F38BF,
1344   PREFIX_VEX_0F38CF,
1345   PREFIX_VEX_0F38DB,
1346   PREFIX_VEX_0F38DC,
1347   PREFIX_VEX_0F38DD,
1348   PREFIX_VEX_0F38DE,
1349   PREFIX_VEX_0F38DF,
1350   PREFIX_VEX_0F38F2,
1351   PREFIX_VEX_0F38F3_REG_1,
1352   PREFIX_VEX_0F38F3_REG_2,
1353   PREFIX_VEX_0F38F3_REG_3,
1354   PREFIX_VEX_0F38F5,
1355   PREFIX_VEX_0F38F6,
1356   PREFIX_VEX_0F38F7,
1357   PREFIX_VEX_0F3A00,
1358   PREFIX_VEX_0F3A01,
1359   PREFIX_VEX_0F3A02,
1360   PREFIX_VEX_0F3A04,
1361   PREFIX_VEX_0F3A05,
1362   PREFIX_VEX_0F3A06,
1363   PREFIX_VEX_0F3A08,
1364   PREFIX_VEX_0F3A09,
1365   PREFIX_VEX_0F3A0A,
1366   PREFIX_VEX_0F3A0B,
1367   PREFIX_VEX_0F3A0C,
1368   PREFIX_VEX_0F3A0D,
1369   PREFIX_VEX_0F3A0E,
1370   PREFIX_VEX_0F3A0F,
1371   PREFIX_VEX_0F3A14,
1372   PREFIX_VEX_0F3A15,
1373   PREFIX_VEX_0F3A16,
1374   PREFIX_VEX_0F3A17,
1375   PREFIX_VEX_0F3A18,
1376   PREFIX_VEX_0F3A19,
1377   PREFIX_VEX_0F3A1D,
1378   PREFIX_VEX_0F3A20,
1379   PREFIX_VEX_0F3A21,
1380   PREFIX_VEX_0F3A22,
1381   PREFIX_VEX_0F3A30,
1382   PREFIX_VEX_0F3A31,
1383   PREFIX_VEX_0F3A32,
1384   PREFIX_VEX_0F3A33,
1385   PREFIX_VEX_0F3A38,
1386   PREFIX_VEX_0F3A39,
1387   PREFIX_VEX_0F3A40,
1388   PREFIX_VEX_0F3A41,
1389   PREFIX_VEX_0F3A42,
1390   PREFIX_VEX_0F3A44,
1391   PREFIX_VEX_0F3A46,
1392   PREFIX_VEX_0F3A48,
1393   PREFIX_VEX_0F3A49,
1394   PREFIX_VEX_0F3A4A,
1395   PREFIX_VEX_0F3A4B,
1396   PREFIX_VEX_0F3A4C,
1397   PREFIX_VEX_0F3A5C,
1398   PREFIX_VEX_0F3A5D,
1399   PREFIX_VEX_0F3A5E,
1400   PREFIX_VEX_0F3A5F,
1401   PREFIX_VEX_0F3A60,
1402   PREFIX_VEX_0F3A61,
1403   PREFIX_VEX_0F3A62,
1404   PREFIX_VEX_0F3A63,
1405   PREFIX_VEX_0F3A68,
1406   PREFIX_VEX_0F3A69,
1407   PREFIX_VEX_0F3A6A,
1408   PREFIX_VEX_0F3A6B,
1409   PREFIX_VEX_0F3A6C,
1410   PREFIX_VEX_0F3A6D,
1411   PREFIX_VEX_0F3A6E,
1412   PREFIX_VEX_0F3A6F,
1413   PREFIX_VEX_0F3A78,
1414   PREFIX_VEX_0F3A79,
1415   PREFIX_VEX_0F3A7A,
1416   PREFIX_VEX_0F3A7B,
1417   PREFIX_VEX_0F3A7C,
1418   PREFIX_VEX_0F3A7D,
1419   PREFIX_VEX_0F3A7E,
1420   PREFIX_VEX_0F3A7F,
1421   PREFIX_VEX_0F3ACE,
1422   PREFIX_VEX_0F3ACF,
1423   PREFIX_VEX_0F3ADF,
1424   PREFIX_VEX_0F3AF0,
1425
1426   PREFIX_EVEX_0F10,
1427   PREFIX_EVEX_0F11,
1428   PREFIX_EVEX_0F12,
1429   PREFIX_EVEX_0F13,
1430   PREFIX_EVEX_0F14,
1431   PREFIX_EVEX_0F15,
1432   PREFIX_EVEX_0F16,
1433   PREFIX_EVEX_0F17,
1434   PREFIX_EVEX_0F28,
1435   PREFIX_EVEX_0F29,
1436   PREFIX_EVEX_0F2A,
1437   PREFIX_EVEX_0F2B,
1438   PREFIX_EVEX_0F2C,
1439   PREFIX_EVEX_0F2D,
1440   PREFIX_EVEX_0F2E,
1441   PREFIX_EVEX_0F2F,
1442   PREFIX_EVEX_0F51,
1443   PREFIX_EVEX_0F54,
1444   PREFIX_EVEX_0F55,
1445   PREFIX_EVEX_0F56,
1446   PREFIX_EVEX_0F57,
1447   PREFIX_EVEX_0F58,
1448   PREFIX_EVEX_0F59,
1449   PREFIX_EVEX_0F5A,
1450   PREFIX_EVEX_0F5B,
1451   PREFIX_EVEX_0F5C,
1452   PREFIX_EVEX_0F5D,
1453   PREFIX_EVEX_0F5E,
1454   PREFIX_EVEX_0F5F,
1455   PREFIX_EVEX_0F60,
1456   PREFIX_EVEX_0F61,
1457   PREFIX_EVEX_0F62,
1458   PREFIX_EVEX_0F63,
1459   PREFIX_EVEX_0F64,
1460   PREFIX_EVEX_0F65,
1461   PREFIX_EVEX_0F66,
1462   PREFIX_EVEX_0F67,
1463   PREFIX_EVEX_0F68,
1464   PREFIX_EVEX_0F69,
1465   PREFIX_EVEX_0F6A,
1466   PREFIX_EVEX_0F6B,
1467   PREFIX_EVEX_0F6C,
1468   PREFIX_EVEX_0F6D,
1469   PREFIX_EVEX_0F6E,
1470   PREFIX_EVEX_0F6F,
1471   PREFIX_EVEX_0F70,
1472   PREFIX_EVEX_0F71_REG_2,
1473   PREFIX_EVEX_0F71_REG_4,
1474   PREFIX_EVEX_0F71_REG_6,
1475   PREFIX_EVEX_0F72_REG_0,
1476   PREFIX_EVEX_0F72_REG_1,
1477   PREFIX_EVEX_0F72_REG_2,
1478   PREFIX_EVEX_0F72_REG_4,
1479   PREFIX_EVEX_0F72_REG_6,
1480   PREFIX_EVEX_0F73_REG_2,
1481   PREFIX_EVEX_0F73_REG_3,
1482   PREFIX_EVEX_0F73_REG_6,
1483   PREFIX_EVEX_0F73_REG_7,
1484   PREFIX_EVEX_0F74,
1485   PREFIX_EVEX_0F75,
1486   PREFIX_EVEX_0F76,
1487   PREFIX_EVEX_0F78,
1488   PREFIX_EVEX_0F79,
1489   PREFIX_EVEX_0F7A,
1490   PREFIX_EVEX_0F7B,
1491   PREFIX_EVEX_0F7E,
1492   PREFIX_EVEX_0F7F,
1493   PREFIX_EVEX_0FC2,
1494   PREFIX_EVEX_0FC4,
1495   PREFIX_EVEX_0FC5,
1496   PREFIX_EVEX_0FC6,
1497   PREFIX_EVEX_0FD1,
1498   PREFIX_EVEX_0FD2,
1499   PREFIX_EVEX_0FD3,
1500   PREFIX_EVEX_0FD4,
1501   PREFIX_EVEX_0FD5,
1502   PREFIX_EVEX_0FD6,
1503   PREFIX_EVEX_0FD8,
1504   PREFIX_EVEX_0FD9,
1505   PREFIX_EVEX_0FDA,
1506   PREFIX_EVEX_0FDB,
1507   PREFIX_EVEX_0FDC,
1508   PREFIX_EVEX_0FDD,
1509   PREFIX_EVEX_0FDE,
1510   PREFIX_EVEX_0FDF,
1511   PREFIX_EVEX_0FE0,
1512   PREFIX_EVEX_0FE1,
1513   PREFIX_EVEX_0FE2,
1514   PREFIX_EVEX_0FE3,
1515   PREFIX_EVEX_0FE4,
1516   PREFIX_EVEX_0FE5,
1517   PREFIX_EVEX_0FE6,
1518   PREFIX_EVEX_0FE7,
1519   PREFIX_EVEX_0FE8,
1520   PREFIX_EVEX_0FE9,
1521   PREFIX_EVEX_0FEA,
1522   PREFIX_EVEX_0FEB,
1523   PREFIX_EVEX_0FEC,
1524   PREFIX_EVEX_0FED,
1525   PREFIX_EVEX_0FEE,
1526   PREFIX_EVEX_0FEF,
1527   PREFIX_EVEX_0FF1,
1528   PREFIX_EVEX_0FF2,
1529   PREFIX_EVEX_0FF3,
1530   PREFIX_EVEX_0FF4,
1531   PREFIX_EVEX_0FF5,
1532   PREFIX_EVEX_0FF6,
1533   PREFIX_EVEX_0FF8,
1534   PREFIX_EVEX_0FF9,
1535   PREFIX_EVEX_0FFA,
1536   PREFIX_EVEX_0FFB,
1537   PREFIX_EVEX_0FFC,
1538   PREFIX_EVEX_0FFD,
1539   PREFIX_EVEX_0FFE,
1540   PREFIX_EVEX_0F3800,
1541   PREFIX_EVEX_0F3804,
1542   PREFIX_EVEX_0F380B,
1543   PREFIX_EVEX_0F380C,
1544   PREFIX_EVEX_0F380D,
1545   PREFIX_EVEX_0F3810,
1546   PREFIX_EVEX_0F3811,
1547   PREFIX_EVEX_0F3812,
1548   PREFIX_EVEX_0F3813,
1549   PREFIX_EVEX_0F3814,
1550   PREFIX_EVEX_0F3815,
1551   PREFIX_EVEX_0F3816,
1552   PREFIX_EVEX_0F3818,
1553   PREFIX_EVEX_0F3819,
1554   PREFIX_EVEX_0F381A,
1555   PREFIX_EVEX_0F381B,
1556   PREFIX_EVEX_0F381C,
1557   PREFIX_EVEX_0F381D,
1558   PREFIX_EVEX_0F381E,
1559   PREFIX_EVEX_0F381F,
1560   PREFIX_EVEX_0F3820,
1561   PREFIX_EVEX_0F3821,
1562   PREFIX_EVEX_0F3822,
1563   PREFIX_EVEX_0F3823,
1564   PREFIX_EVEX_0F3824,
1565   PREFIX_EVEX_0F3825,
1566   PREFIX_EVEX_0F3826,
1567   PREFIX_EVEX_0F3827,
1568   PREFIX_EVEX_0F3828,
1569   PREFIX_EVEX_0F3829,
1570   PREFIX_EVEX_0F382A,
1571   PREFIX_EVEX_0F382B,
1572   PREFIX_EVEX_0F382C,
1573   PREFIX_EVEX_0F382D,
1574   PREFIX_EVEX_0F3830,
1575   PREFIX_EVEX_0F3831,
1576   PREFIX_EVEX_0F3832,
1577   PREFIX_EVEX_0F3833,
1578   PREFIX_EVEX_0F3834,
1579   PREFIX_EVEX_0F3835,
1580   PREFIX_EVEX_0F3836,
1581   PREFIX_EVEX_0F3837,
1582   PREFIX_EVEX_0F3838,
1583   PREFIX_EVEX_0F3839,
1584   PREFIX_EVEX_0F383A,
1585   PREFIX_EVEX_0F383B,
1586   PREFIX_EVEX_0F383C,
1587   PREFIX_EVEX_0F383D,
1588   PREFIX_EVEX_0F383E,
1589   PREFIX_EVEX_0F383F,
1590   PREFIX_EVEX_0F3840,
1591   PREFIX_EVEX_0F3842,
1592   PREFIX_EVEX_0F3843,
1593   PREFIX_EVEX_0F3844,
1594   PREFIX_EVEX_0F3845,
1595   PREFIX_EVEX_0F3846,
1596   PREFIX_EVEX_0F3847,
1597   PREFIX_EVEX_0F384C,
1598   PREFIX_EVEX_0F384D,
1599   PREFIX_EVEX_0F384E,
1600   PREFIX_EVEX_0F384F,
1601   PREFIX_EVEX_0F3850,
1602   PREFIX_EVEX_0F3851,
1603   PREFIX_EVEX_0F3852,
1604   PREFIX_EVEX_0F3853,
1605   PREFIX_EVEX_0F3854,
1606   PREFIX_EVEX_0F3855,
1607   PREFIX_EVEX_0F3858,
1608   PREFIX_EVEX_0F3859,
1609   PREFIX_EVEX_0F385A,
1610   PREFIX_EVEX_0F385B,
1611   PREFIX_EVEX_0F3862,
1612   PREFIX_EVEX_0F3863,
1613   PREFIX_EVEX_0F3864,
1614   PREFIX_EVEX_0F3865,
1615   PREFIX_EVEX_0F3866,
1616   PREFIX_EVEX_0F3870,
1617   PREFIX_EVEX_0F3871,
1618   PREFIX_EVEX_0F3872,
1619   PREFIX_EVEX_0F3873,
1620   PREFIX_EVEX_0F3875,
1621   PREFIX_EVEX_0F3876,
1622   PREFIX_EVEX_0F3877,
1623   PREFIX_EVEX_0F3878,
1624   PREFIX_EVEX_0F3879,
1625   PREFIX_EVEX_0F387A,
1626   PREFIX_EVEX_0F387B,
1627   PREFIX_EVEX_0F387C,
1628   PREFIX_EVEX_0F387D,
1629   PREFIX_EVEX_0F387E,
1630   PREFIX_EVEX_0F387F,
1631   PREFIX_EVEX_0F3883,
1632   PREFIX_EVEX_0F3888,
1633   PREFIX_EVEX_0F3889,
1634   PREFIX_EVEX_0F388A,
1635   PREFIX_EVEX_0F388B,
1636   PREFIX_EVEX_0F388D,
1637   PREFIX_EVEX_0F388F,
1638   PREFIX_EVEX_0F3890,
1639   PREFIX_EVEX_0F3891,
1640   PREFIX_EVEX_0F3892,
1641   PREFIX_EVEX_0F3893,
1642   PREFIX_EVEX_0F3896,
1643   PREFIX_EVEX_0F3897,
1644   PREFIX_EVEX_0F3898,
1645   PREFIX_EVEX_0F3899,
1646   PREFIX_EVEX_0F389A,
1647   PREFIX_EVEX_0F389B,
1648   PREFIX_EVEX_0F389C,
1649   PREFIX_EVEX_0F389D,
1650   PREFIX_EVEX_0F389E,
1651   PREFIX_EVEX_0F389F,
1652   PREFIX_EVEX_0F38A0,
1653   PREFIX_EVEX_0F38A1,
1654   PREFIX_EVEX_0F38A2,
1655   PREFIX_EVEX_0F38A3,
1656   PREFIX_EVEX_0F38A6,
1657   PREFIX_EVEX_0F38A7,
1658   PREFIX_EVEX_0F38A8,
1659   PREFIX_EVEX_0F38A9,
1660   PREFIX_EVEX_0F38AA,
1661   PREFIX_EVEX_0F38AB,
1662   PREFIX_EVEX_0F38AC,
1663   PREFIX_EVEX_0F38AD,
1664   PREFIX_EVEX_0F38AE,
1665   PREFIX_EVEX_0F38AF,
1666   PREFIX_EVEX_0F38B4,
1667   PREFIX_EVEX_0F38B5,
1668   PREFIX_EVEX_0F38B6,
1669   PREFIX_EVEX_0F38B7,
1670   PREFIX_EVEX_0F38B8,
1671   PREFIX_EVEX_0F38B9,
1672   PREFIX_EVEX_0F38BA,
1673   PREFIX_EVEX_0F38BB,
1674   PREFIX_EVEX_0F38BC,
1675   PREFIX_EVEX_0F38BD,
1676   PREFIX_EVEX_0F38BE,
1677   PREFIX_EVEX_0F38BF,
1678   PREFIX_EVEX_0F38C4,
1679   PREFIX_EVEX_0F38C6_REG_1,
1680   PREFIX_EVEX_0F38C6_REG_2,
1681   PREFIX_EVEX_0F38C6_REG_5,
1682   PREFIX_EVEX_0F38C6_REG_6,
1683   PREFIX_EVEX_0F38C7_REG_1,
1684   PREFIX_EVEX_0F38C7_REG_2,
1685   PREFIX_EVEX_0F38C7_REG_5,
1686   PREFIX_EVEX_0F38C7_REG_6,
1687   PREFIX_EVEX_0F38C8,
1688   PREFIX_EVEX_0F38CA,
1689   PREFIX_EVEX_0F38CB,
1690   PREFIX_EVEX_0F38CC,
1691   PREFIX_EVEX_0F38CD,
1692   PREFIX_EVEX_0F38CF,
1693   PREFIX_EVEX_0F38DC,
1694   PREFIX_EVEX_0F38DD,
1695   PREFIX_EVEX_0F38DE,
1696   PREFIX_EVEX_0F38DF,
1697
1698   PREFIX_EVEX_0F3A00,
1699   PREFIX_EVEX_0F3A01,
1700   PREFIX_EVEX_0F3A03,
1701   PREFIX_EVEX_0F3A04,
1702   PREFIX_EVEX_0F3A05,
1703   PREFIX_EVEX_0F3A08,
1704   PREFIX_EVEX_0F3A09,
1705   PREFIX_EVEX_0F3A0A,
1706   PREFIX_EVEX_0F3A0B,
1707   PREFIX_EVEX_0F3A0F,
1708   PREFIX_EVEX_0F3A14,
1709   PREFIX_EVEX_0F3A15,
1710   PREFIX_EVEX_0F3A16,
1711   PREFIX_EVEX_0F3A17,
1712   PREFIX_EVEX_0F3A18,
1713   PREFIX_EVEX_0F3A19,
1714   PREFIX_EVEX_0F3A1A,
1715   PREFIX_EVEX_0F3A1B,
1716   PREFIX_EVEX_0F3A1D,
1717   PREFIX_EVEX_0F3A1E,
1718   PREFIX_EVEX_0F3A1F,
1719   PREFIX_EVEX_0F3A20,
1720   PREFIX_EVEX_0F3A21,
1721   PREFIX_EVEX_0F3A22,
1722   PREFIX_EVEX_0F3A23,
1723   PREFIX_EVEX_0F3A25,
1724   PREFIX_EVEX_0F3A26,
1725   PREFIX_EVEX_0F3A27,
1726   PREFIX_EVEX_0F3A38,
1727   PREFIX_EVEX_0F3A39,
1728   PREFIX_EVEX_0F3A3A,
1729   PREFIX_EVEX_0F3A3B,
1730   PREFIX_EVEX_0F3A3E,
1731   PREFIX_EVEX_0F3A3F,
1732   PREFIX_EVEX_0F3A42,
1733   PREFIX_EVEX_0F3A43,
1734   PREFIX_EVEX_0F3A44,
1735   PREFIX_EVEX_0F3A50,
1736   PREFIX_EVEX_0F3A51,
1737   PREFIX_EVEX_0F3A54,
1738   PREFIX_EVEX_0F3A55,
1739   PREFIX_EVEX_0F3A56,
1740   PREFIX_EVEX_0F3A57,
1741   PREFIX_EVEX_0F3A66,
1742   PREFIX_EVEX_0F3A67,
1743   PREFIX_EVEX_0F3A70,
1744   PREFIX_EVEX_0F3A71,
1745   PREFIX_EVEX_0F3A72,
1746   PREFIX_EVEX_0F3A73,
1747   PREFIX_EVEX_0F3ACE,
1748   PREFIX_EVEX_0F3ACF
1749 };
1750
1751 enum
1752 {
1753   X86_64_06 = 0,
1754   X86_64_07,
1755   X86_64_0D,
1756   X86_64_16,
1757   X86_64_17,
1758   X86_64_1E,
1759   X86_64_1F,
1760   X86_64_27,
1761   X86_64_2F,
1762   X86_64_37,
1763   X86_64_3F,
1764   X86_64_60,
1765   X86_64_61,
1766   X86_64_62,
1767   X86_64_63,
1768   X86_64_6D,
1769   X86_64_6F,
1770   X86_64_82,
1771   X86_64_9A,
1772   X86_64_C4,
1773   X86_64_C5,
1774   X86_64_CE,
1775   X86_64_D4,
1776   X86_64_D5,
1777   X86_64_E8,
1778   X86_64_E9,
1779   X86_64_EA,
1780   X86_64_0F01_REG_0,
1781   X86_64_0F01_REG_1,
1782   X86_64_0F01_REG_2,
1783   X86_64_0F01_REG_3
1784 };
1785
1786 enum
1787 {
1788   THREE_BYTE_0F38 = 0,
1789   THREE_BYTE_0F3A
1790 };
1791
1792 enum
1793 {
1794   XOP_08 = 0,
1795   XOP_09,
1796   XOP_0A
1797 };
1798
1799 enum
1800 {
1801   VEX_0F = 0,
1802   VEX_0F38,
1803   VEX_0F3A
1804 };
1805
1806 enum
1807 {
1808   EVEX_0F = 0,
1809   EVEX_0F38,
1810   EVEX_0F3A
1811 };
1812
1813 enum
1814 {
1815   VEX_LEN_0F12_P_0_M_0 = 0,
1816   VEX_LEN_0F12_P_0_M_1,
1817   VEX_LEN_0F12_P_2,
1818   VEX_LEN_0F13_M_0,
1819   VEX_LEN_0F16_P_0_M_0,
1820   VEX_LEN_0F16_P_0_M_1,
1821   VEX_LEN_0F16_P_2,
1822   VEX_LEN_0F17_M_0,
1823   VEX_LEN_0F2A_P_1,
1824   VEX_LEN_0F2A_P_3,
1825   VEX_LEN_0F2C_P_1,
1826   VEX_LEN_0F2C_P_3,
1827   VEX_LEN_0F2D_P_1,
1828   VEX_LEN_0F2D_P_3,
1829   VEX_LEN_0F41_P_0,
1830   VEX_LEN_0F41_P_2,
1831   VEX_LEN_0F42_P_0,
1832   VEX_LEN_0F42_P_2,
1833   VEX_LEN_0F44_P_0,
1834   VEX_LEN_0F44_P_2,
1835   VEX_LEN_0F45_P_0,
1836   VEX_LEN_0F45_P_2,
1837   VEX_LEN_0F46_P_0,
1838   VEX_LEN_0F46_P_2,
1839   VEX_LEN_0F47_P_0,
1840   VEX_LEN_0F47_P_2,
1841   VEX_LEN_0F4A_P_0,
1842   VEX_LEN_0F4A_P_2,
1843   VEX_LEN_0F4B_P_0,
1844   VEX_LEN_0F4B_P_2,
1845   VEX_LEN_0F6E_P_2,
1846   VEX_LEN_0F77_P_0,
1847   VEX_LEN_0F7E_P_1,
1848   VEX_LEN_0F7E_P_2,
1849   VEX_LEN_0F90_P_0,
1850   VEX_LEN_0F90_P_2,
1851   VEX_LEN_0F91_P_0,
1852   VEX_LEN_0F91_P_2,
1853   VEX_LEN_0F92_P_0,
1854   VEX_LEN_0F92_P_2,
1855   VEX_LEN_0F92_P_3,
1856   VEX_LEN_0F93_P_0,
1857   VEX_LEN_0F93_P_2,
1858   VEX_LEN_0F93_P_3,
1859   VEX_LEN_0F98_P_0,
1860   VEX_LEN_0F98_P_2,
1861   VEX_LEN_0F99_P_0,
1862   VEX_LEN_0F99_P_2,
1863   VEX_LEN_0FAE_R_2_M_0,
1864   VEX_LEN_0FAE_R_3_M_0,
1865   VEX_LEN_0FC4_P_2,
1866   VEX_LEN_0FC5_P_2,
1867   VEX_LEN_0FD6_P_2,
1868   VEX_LEN_0FF7_P_2,
1869   VEX_LEN_0F3816_P_2,
1870   VEX_LEN_0F3819_P_2,
1871   VEX_LEN_0F381A_P_2_M_0,
1872   VEX_LEN_0F3836_P_2,
1873   VEX_LEN_0F3841_P_2,
1874   VEX_LEN_0F385A_P_2_M_0,
1875   VEX_LEN_0F38DB_P_2,
1876   VEX_LEN_0F38F2_P_0,
1877   VEX_LEN_0F38F3_R_1_P_0,
1878   VEX_LEN_0F38F3_R_2_P_0,
1879   VEX_LEN_0F38F3_R_3_P_0,
1880   VEX_LEN_0F38F5_P_0,
1881   VEX_LEN_0F38F5_P_1,
1882   VEX_LEN_0F38F5_P_3,
1883   VEX_LEN_0F38F6_P_3,
1884   VEX_LEN_0F38F7_P_0,
1885   VEX_LEN_0F38F7_P_1,
1886   VEX_LEN_0F38F7_P_2,
1887   VEX_LEN_0F38F7_P_3,
1888   VEX_LEN_0F3A00_P_2,
1889   VEX_LEN_0F3A01_P_2,
1890   VEX_LEN_0F3A06_P_2,
1891   VEX_LEN_0F3A14_P_2,
1892   VEX_LEN_0F3A15_P_2,
1893   VEX_LEN_0F3A16_P_2,
1894   VEX_LEN_0F3A17_P_2,
1895   VEX_LEN_0F3A18_P_2,
1896   VEX_LEN_0F3A19_P_2,
1897   VEX_LEN_0F3A20_P_2,
1898   VEX_LEN_0F3A21_P_2,
1899   VEX_LEN_0F3A22_P_2,
1900   VEX_LEN_0F3A30_P_2,
1901   VEX_LEN_0F3A31_P_2,
1902   VEX_LEN_0F3A32_P_2,
1903   VEX_LEN_0F3A33_P_2,
1904   VEX_LEN_0F3A38_P_2,
1905   VEX_LEN_0F3A39_P_2,
1906   VEX_LEN_0F3A41_P_2,
1907   VEX_LEN_0F3A46_P_2,
1908   VEX_LEN_0F3A60_P_2,
1909   VEX_LEN_0F3A61_P_2,
1910   VEX_LEN_0F3A62_P_2,
1911   VEX_LEN_0F3A63_P_2,
1912   VEX_LEN_0F3A6A_P_2,
1913   VEX_LEN_0F3A6B_P_2,
1914   VEX_LEN_0F3A6E_P_2,
1915   VEX_LEN_0F3A6F_P_2,
1916   VEX_LEN_0F3A7A_P_2,
1917   VEX_LEN_0F3A7B_P_2,
1918   VEX_LEN_0F3A7E_P_2,
1919   VEX_LEN_0F3A7F_P_2,
1920   VEX_LEN_0F3ADF_P_2,
1921   VEX_LEN_0F3AF0_P_3,
1922   VEX_LEN_0FXOP_08_CC,
1923   VEX_LEN_0FXOP_08_CD,
1924   VEX_LEN_0FXOP_08_CE,
1925   VEX_LEN_0FXOP_08_CF,
1926   VEX_LEN_0FXOP_08_EC,
1927   VEX_LEN_0FXOP_08_ED,
1928   VEX_LEN_0FXOP_08_EE,
1929   VEX_LEN_0FXOP_08_EF,
1930   VEX_LEN_0FXOP_09_80,
1931   VEX_LEN_0FXOP_09_81
1932 };
1933
1934 enum
1935 {
1936   EVEX_LEN_0F6E_P_2 = 0,
1937   EVEX_LEN_0F7E_P_1,
1938   EVEX_LEN_0F7E_P_2,
1939   EVEX_LEN_0FD6_P_2
1940 };
1941
1942 enum
1943 {
1944   VEX_W_0F41_P_0_LEN_1 = 0,
1945   VEX_W_0F41_P_2_LEN_1,
1946   VEX_W_0F42_P_0_LEN_1,
1947   VEX_W_0F42_P_2_LEN_1,
1948   VEX_W_0F44_P_0_LEN_0,
1949   VEX_W_0F44_P_2_LEN_0,
1950   VEX_W_0F45_P_0_LEN_1,
1951   VEX_W_0F45_P_2_LEN_1,
1952   VEX_W_0F46_P_0_LEN_1,
1953   VEX_W_0F46_P_2_LEN_1,
1954   VEX_W_0F47_P_0_LEN_1,
1955   VEX_W_0F47_P_2_LEN_1,
1956   VEX_W_0F4A_P_0_LEN_1,
1957   VEX_W_0F4A_P_2_LEN_1,
1958   VEX_W_0F4B_P_0_LEN_1,
1959   VEX_W_0F4B_P_2_LEN_1,
1960   VEX_W_0F90_P_0_LEN_0,
1961   VEX_W_0F90_P_2_LEN_0,
1962   VEX_W_0F91_P_0_LEN_0,
1963   VEX_W_0F91_P_2_LEN_0,
1964   VEX_W_0F92_P_0_LEN_0,
1965   VEX_W_0F92_P_2_LEN_0,
1966   VEX_W_0F92_P_3_LEN_0,
1967   VEX_W_0F93_P_0_LEN_0,
1968   VEX_W_0F93_P_2_LEN_0,
1969   VEX_W_0F93_P_3_LEN_0,
1970   VEX_W_0F98_P_0_LEN_0,
1971   VEX_W_0F98_P_2_LEN_0,
1972   VEX_W_0F99_P_0_LEN_0,
1973   VEX_W_0F99_P_2_LEN_0,
1974   VEX_W_0FC4_P_2,
1975   VEX_W_0FC5_P_2,
1976   VEX_W_0F380C_P_2,
1977   VEX_W_0F380D_P_2,
1978   VEX_W_0F380E_P_2,
1979   VEX_W_0F380F_P_2,
1980   VEX_W_0F3816_P_2,
1981   VEX_W_0F3818_P_2,
1982   VEX_W_0F3819_P_2,
1983   VEX_W_0F381A_P_2_M_0,
1984   VEX_W_0F382C_P_2_M_0,
1985   VEX_W_0F382D_P_2_M_0,
1986   VEX_W_0F382E_P_2_M_0,
1987   VEX_W_0F382F_P_2_M_0,
1988   VEX_W_0F3836_P_2,
1989   VEX_W_0F3846_P_2,
1990   VEX_W_0F3858_P_2,
1991   VEX_W_0F3859_P_2,
1992   VEX_W_0F385A_P_2_M_0,
1993   VEX_W_0F3878_P_2,
1994   VEX_W_0F3879_P_2,
1995   VEX_W_0F38CF_P_2,
1996   VEX_W_0F3A00_P_2,
1997   VEX_W_0F3A01_P_2,
1998   VEX_W_0F3A02_P_2,
1999   VEX_W_0F3A04_P_2,
2000   VEX_W_0F3A05_P_2,
2001   VEX_W_0F3A06_P_2,
2002   VEX_W_0F3A14_P_2,
2003   VEX_W_0F3A15_P_2,
2004   VEX_W_0F3A18_P_2,
2005   VEX_W_0F3A19_P_2,
2006   VEX_W_0F3A20_P_2,
2007   VEX_W_0F3A30_P_2_LEN_0,
2008   VEX_W_0F3A31_P_2_LEN_0,
2009   VEX_W_0F3A32_P_2_LEN_0,
2010   VEX_W_0F3A33_P_2_LEN_0,
2011   VEX_W_0F3A38_P_2,
2012   VEX_W_0F3A39_P_2,
2013   VEX_W_0F3A46_P_2,
2014   VEX_W_0F3A48_P_2,
2015   VEX_W_0F3A49_P_2,
2016   VEX_W_0F3A4A_P_2,
2017   VEX_W_0F3A4B_P_2,
2018   VEX_W_0F3A4C_P_2,
2019   VEX_W_0F3ACE_P_2,
2020   VEX_W_0F3ACF_P_2,
2021
2022   EVEX_W_0F10_P_0,
2023   EVEX_W_0F10_P_1_M_0,
2024   EVEX_W_0F10_P_1_M_1,
2025   EVEX_W_0F10_P_2,
2026   EVEX_W_0F10_P_3_M_0,
2027   EVEX_W_0F10_P_3_M_1,
2028   EVEX_W_0F11_P_0,
2029   EVEX_W_0F11_P_1_M_0,
2030   EVEX_W_0F11_P_1_M_1,
2031   EVEX_W_0F11_P_2,
2032   EVEX_W_0F11_P_3_M_0,
2033   EVEX_W_0F11_P_3_M_1,
2034   EVEX_W_0F12_P_0_M_0,
2035   EVEX_W_0F12_P_0_M_1,
2036   EVEX_W_0F12_P_1,
2037   EVEX_W_0F12_P_2,
2038   EVEX_W_0F12_P_3,
2039   EVEX_W_0F13_P_0,
2040   EVEX_W_0F13_P_2,
2041   EVEX_W_0F14_P_0,
2042   EVEX_W_0F14_P_2,
2043   EVEX_W_0F15_P_0,
2044   EVEX_W_0F15_P_2,
2045   EVEX_W_0F16_P_0_M_0,
2046   EVEX_W_0F16_P_0_M_1,
2047   EVEX_W_0F16_P_1,
2048   EVEX_W_0F16_P_2,
2049   EVEX_W_0F17_P_0,
2050   EVEX_W_0F17_P_2,
2051   EVEX_W_0F28_P_0,
2052   EVEX_W_0F28_P_2,
2053   EVEX_W_0F29_P_0,
2054   EVEX_W_0F29_P_2,
2055   EVEX_W_0F2A_P_1,
2056   EVEX_W_0F2A_P_3,
2057   EVEX_W_0F2B_P_0,
2058   EVEX_W_0F2B_P_2,
2059   EVEX_W_0F2E_P_0,
2060   EVEX_W_0F2E_P_2,
2061   EVEX_W_0F2F_P_0,
2062   EVEX_W_0F2F_P_2,
2063   EVEX_W_0F51_P_0,
2064   EVEX_W_0F51_P_1,
2065   EVEX_W_0F51_P_2,
2066   EVEX_W_0F51_P_3,
2067   EVEX_W_0F54_P_0,
2068   EVEX_W_0F54_P_2,
2069   EVEX_W_0F55_P_0,
2070   EVEX_W_0F55_P_2,
2071   EVEX_W_0F56_P_0,
2072   EVEX_W_0F56_P_2,
2073   EVEX_W_0F57_P_0,
2074   EVEX_W_0F57_P_2,
2075   EVEX_W_0F58_P_0,
2076   EVEX_W_0F58_P_1,
2077   EVEX_W_0F58_P_2,
2078   EVEX_W_0F58_P_3,
2079   EVEX_W_0F59_P_0,
2080   EVEX_W_0F59_P_1,
2081   EVEX_W_0F59_P_2,
2082   EVEX_W_0F59_P_3,
2083   EVEX_W_0F5A_P_0,
2084   EVEX_W_0F5A_P_1,
2085   EVEX_W_0F5A_P_2,
2086   EVEX_W_0F5A_P_3,
2087   EVEX_W_0F5B_P_0,
2088   EVEX_W_0F5B_P_1,
2089   EVEX_W_0F5B_P_2,
2090   EVEX_W_0F5C_P_0,
2091   EVEX_W_0F5C_P_1,
2092   EVEX_W_0F5C_P_2,
2093   EVEX_W_0F5C_P_3,
2094   EVEX_W_0F5D_P_0,
2095   EVEX_W_0F5D_P_1,
2096   EVEX_W_0F5D_P_2,
2097   EVEX_W_0F5D_P_3,
2098   EVEX_W_0F5E_P_0,
2099   EVEX_W_0F5E_P_1,
2100   EVEX_W_0F5E_P_2,
2101   EVEX_W_0F5E_P_3,
2102   EVEX_W_0F5F_P_0,
2103   EVEX_W_0F5F_P_1,
2104   EVEX_W_0F5F_P_2,
2105   EVEX_W_0F5F_P_3,
2106   EVEX_W_0F62_P_2,
2107   EVEX_W_0F66_P_2,
2108   EVEX_W_0F6A_P_2,
2109   EVEX_W_0F6B_P_2,
2110   EVEX_W_0F6C_P_2,
2111   EVEX_W_0F6D_P_2,
2112   EVEX_W_0F6E_P_2,
2113   EVEX_W_0F6F_P_1,
2114   EVEX_W_0F6F_P_2,
2115   EVEX_W_0F6F_P_3,
2116   EVEX_W_0F70_P_2,
2117   EVEX_W_0F72_R_2_P_2,
2118   EVEX_W_0F72_R_6_P_2,
2119   EVEX_W_0F73_R_2_P_2,
2120   EVEX_W_0F73_R_6_P_2,
2121   EVEX_W_0F76_P_2,
2122   EVEX_W_0F78_P_0,
2123   EVEX_W_0F78_P_2,
2124   EVEX_W_0F79_P_0,
2125   EVEX_W_0F79_P_2,
2126   EVEX_W_0F7A_P_1,
2127   EVEX_W_0F7A_P_2,
2128   EVEX_W_0F7A_P_3,
2129   EVEX_W_0F7B_P_1,
2130   EVEX_W_0F7B_P_2,
2131   EVEX_W_0F7B_P_3,
2132   EVEX_W_0F7E_P_1,
2133   EVEX_W_0F7E_P_2,
2134   EVEX_W_0F7F_P_1,
2135   EVEX_W_0F7F_P_2,
2136   EVEX_W_0F7F_P_3,
2137   EVEX_W_0FC2_P_0,
2138   EVEX_W_0FC2_P_1,
2139   EVEX_W_0FC2_P_2,
2140   EVEX_W_0FC2_P_3,
2141   EVEX_W_0FC6_P_0,
2142   EVEX_W_0FC6_P_2,
2143   EVEX_W_0FD2_P_2,
2144   EVEX_W_0FD3_P_2,
2145   EVEX_W_0FD4_P_2,
2146   EVEX_W_0FD6_P_2,
2147   EVEX_W_0FE6_P_1,
2148   EVEX_W_0FE6_P_2,
2149   EVEX_W_0FE6_P_3,
2150   EVEX_W_0FE7_P_2,
2151   EVEX_W_0FF2_P_2,
2152   EVEX_W_0FF3_P_2,
2153   EVEX_W_0FF4_P_2,
2154   EVEX_W_0FFA_P_2,
2155   EVEX_W_0FFB_P_2,
2156   EVEX_W_0FFE_P_2,
2157   EVEX_W_0F380C_P_2,
2158   EVEX_W_0F380D_P_2,
2159   EVEX_W_0F3810_P_1,
2160   EVEX_W_0F3810_P_2,
2161   EVEX_W_0F3811_P_1,
2162   EVEX_W_0F3811_P_2,
2163   EVEX_W_0F3812_P_1,
2164   EVEX_W_0F3812_P_2,
2165   EVEX_W_0F3813_P_1,
2166   EVEX_W_0F3813_P_2,
2167   EVEX_W_0F3814_P_1,
2168   EVEX_W_0F3815_P_1,
2169   EVEX_W_0F3818_P_2,
2170   EVEX_W_0F3819_P_2,
2171   EVEX_W_0F381A_P_2,
2172   EVEX_W_0F381B_P_2,
2173   EVEX_W_0F381E_P_2,
2174   EVEX_W_0F381F_P_2,
2175   EVEX_W_0F3820_P_1,
2176   EVEX_W_0F3821_P_1,
2177   EVEX_W_0F3822_P_1,
2178   EVEX_W_0F3823_P_1,
2179   EVEX_W_0F3824_P_1,
2180   EVEX_W_0F3825_P_1,
2181   EVEX_W_0F3825_P_2,
2182   EVEX_W_0F3826_P_1,
2183   EVEX_W_0F3826_P_2,
2184   EVEX_W_0F3828_P_1,
2185   EVEX_W_0F3828_P_2,
2186   EVEX_W_0F3829_P_1,
2187   EVEX_W_0F3829_P_2,
2188   EVEX_W_0F382A_P_1,
2189   EVEX_W_0F382A_P_2,
2190   EVEX_W_0F382B_P_2,
2191   EVEX_W_0F3830_P_1,
2192   EVEX_W_0F3831_P_1,
2193   EVEX_W_0F3832_P_1,
2194   EVEX_W_0F3833_P_1,
2195   EVEX_W_0F3834_P_1,
2196   EVEX_W_0F3835_P_1,
2197   EVEX_W_0F3835_P_2,
2198   EVEX_W_0F3837_P_2,
2199   EVEX_W_0F3838_P_1,
2200   EVEX_W_0F3839_P_1,
2201   EVEX_W_0F383A_P_1,
2202   EVEX_W_0F3840_P_2,
2203   EVEX_W_0F3854_P_2,
2204   EVEX_W_0F3855_P_2,
2205   EVEX_W_0F3858_P_2,
2206   EVEX_W_0F3859_P_2,
2207   EVEX_W_0F385A_P_2,
2208   EVEX_W_0F385B_P_2,
2209   EVEX_W_0F3862_P_2,
2210   EVEX_W_0F3863_P_2,
2211   EVEX_W_0F3866_P_2,
2212   EVEX_W_0F3870_P_2,
2213   EVEX_W_0F3871_P_2,
2214   EVEX_W_0F3872_P_2,
2215   EVEX_W_0F3873_P_2,
2216   EVEX_W_0F3875_P_2,
2217   EVEX_W_0F3878_P_2,
2218   EVEX_W_0F3879_P_2,
2219   EVEX_W_0F387A_P_2,
2220   EVEX_W_0F387B_P_2,
2221   EVEX_W_0F387D_P_2,
2222   EVEX_W_0F3883_P_2,
2223   EVEX_W_0F388D_P_2,
2224   EVEX_W_0F3891_P_2,
2225   EVEX_W_0F3893_P_2,
2226   EVEX_W_0F38A1_P_2,
2227   EVEX_W_0F38A3_P_2,
2228   EVEX_W_0F38C7_R_1_P_2,
2229   EVEX_W_0F38C7_R_2_P_2,
2230   EVEX_W_0F38C7_R_5_P_2,
2231   EVEX_W_0F38C7_R_6_P_2,
2232
2233   EVEX_W_0F3A00_P_2,
2234   EVEX_W_0F3A01_P_2,
2235   EVEX_W_0F3A04_P_2,
2236   EVEX_W_0F3A05_P_2,
2237   EVEX_W_0F3A08_P_2,
2238   EVEX_W_0F3A09_P_2,
2239   EVEX_W_0F3A0A_P_2,
2240   EVEX_W_0F3A0B_P_2,
2241   EVEX_W_0F3A16_P_2,
2242   EVEX_W_0F3A18_P_2,
2243   EVEX_W_0F3A19_P_2,
2244   EVEX_W_0F3A1A_P_2,
2245   EVEX_W_0F3A1B_P_2,
2246   EVEX_W_0F3A1D_P_2,
2247   EVEX_W_0F3A21_P_2,
2248   EVEX_W_0F3A22_P_2,
2249   EVEX_W_0F3A23_P_2,
2250   EVEX_W_0F3A38_P_2,
2251   EVEX_W_0F3A39_P_2,
2252   EVEX_W_0F3A3A_P_2,
2253   EVEX_W_0F3A3B_P_2,
2254   EVEX_W_0F3A3E_P_2,
2255   EVEX_W_0F3A3F_P_2,
2256   EVEX_W_0F3A42_P_2,
2257   EVEX_W_0F3A43_P_2,
2258   EVEX_W_0F3A50_P_2,
2259   EVEX_W_0F3A51_P_2,
2260   EVEX_W_0F3A56_P_2,
2261   EVEX_W_0F3A57_P_2,
2262   EVEX_W_0F3A66_P_2,
2263   EVEX_W_0F3A67_P_2,
2264   EVEX_W_0F3A70_P_2,
2265   EVEX_W_0F3A71_P_2,
2266   EVEX_W_0F3A72_P_2,
2267   EVEX_W_0F3A73_P_2,
2268   EVEX_W_0F3ACE_P_2,
2269   EVEX_W_0F3ACF_P_2
2270 };
2271
2272 typedef void (*op_rtn) (int bytemode, int sizeflag);
2273
2274 struct dis386 {
2275   const char *name;
2276   struct
2277     {
2278       op_rtn rtn;
2279       int bytemode;
2280     } op[MAX_OPERANDS];
2281   unsigned int prefix_requirement;
2282 };
2283
2284 /* Upper case letters in the instruction names here are macros.
2285    'A' => print 'b' if no register operands or suffix_always is true
2286    'B' => print 'b' if suffix_always is true
2287    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2288           size prefix
2289    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2290           suffix_always is true
2291    'E' => print 'e' if 32-bit form of jcxz
2292    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2293    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2294    'H' => print ",pt" or ",pn" branch hint
2295    'I' => honor following macro letter even in Intel mode (implemented only
2296           for some of the macro letters)
2297    'J' => print 'l'
2298    'K' => print 'd' or 'q' if rex prefix is present.
2299    'L' => print 'l' if suffix_always is true
2300    'M' => print 'r' if intel_mnemonic is false.
2301    'N' => print 'n' if instruction has no wait "prefix"
2302    'O' => print 'd' or 'o' (or 'q' in Intel mode)
2303    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2304           or suffix_always is true.  print 'q' if rex prefix is present.
2305    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2306           is true
2307    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2308    'S' => print 'w', 'l' or 'q' if suffix_always is true
2309    'T' => print 'q' in 64bit mode if instruction has no operand size
2310           prefix and behave as 'P' otherwise
2311    'U' => print 'q' in 64bit mode if instruction has no operand size
2312           prefix and behave as 'Q' otherwise
2313    'V' => print 'q' in 64bit mode if instruction has no operand size
2314           prefix and behave as 'S' otherwise
2315    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2316    'X' => print 's', 'd' depending on data16 prefix (for XMM)
2317    'Y' unused.
2318    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2319    '!' => change condition from true to false or from false to true.
2320    '%' => add 1 upper case letter to the macro.
2321    '^' => print 'w' or 'l' depending on operand size prefix or
2322           suffix_always is true (lcall/ljmp).
2323    '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2324           on operand size prefix.
2325    '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2326           has no operand size prefix for AMD64 ISA, behave as 'P'
2327           otherwise
2328
2329    2 upper case letter macros:
2330    "XY" => print 'x' or 'y' if suffix_always is true or no register
2331            operands and no broadcast.
2332    "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2333            register operands and no broadcast.
2334    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2335    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2336            or suffix_always is true
2337    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2338    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2339    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2340    "LW" => print 'd', 'q' depending on the VEX.W bit
2341    "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2342            an operand size prefix, or suffix_always is true.  print
2343            'q' if rex prefix is present.
2344
2345    Many of the above letters print nothing in Intel mode.  See "putop"
2346    for the details.
2347
2348    Braces '{' and '}', and vertical bars '|', indicate alternative
2349    mnemonic strings for AT&T and Intel.  */
2350
2351 static const struct dis386 dis386[] = {
2352   /* 00 */
2353   { "addB",             { Ebh1, Gb }, 0 },
2354   { "addS",             { Evh1, Gv }, 0 },
2355   { "addB",             { Gb, EbS }, 0 },
2356   { "addS",             { Gv, EvS }, 0 },
2357   { "addB",             { AL, Ib }, 0 },
2358   { "addS",             { eAX, Iv }, 0 },
2359   { X86_64_TABLE (X86_64_06) },
2360   { X86_64_TABLE (X86_64_07) },
2361   /* 08 */
2362   { "orB",              { Ebh1, Gb }, 0 },
2363   { "orS",              { Evh1, Gv }, 0 },
2364   { "orB",              { Gb, EbS }, 0 },
2365   { "orS",              { Gv, EvS }, 0 },
2366   { "orB",              { AL, Ib }, 0 },
2367   { "orS",              { eAX, Iv }, 0 },
2368   { X86_64_TABLE (X86_64_0D) },
2369   { Bad_Opcode },       /* 0x0f extended opcode escape */
2370   /* 10 */
2371   { "adcB",             { Ebh1, Gb }, 0 },
2372   { "adcS",             { Evh1, Gv }, 0 },
2373   { "adcB",             { Gb, EbS }, 0 },
2374   { "adcS",             { Gv, EvS }, 0 },
2375   { "adcB",             { AL, Ib }, 0 },
2376   { "adcS",             { eAX, Iv }, 0 },
2377   { X86_64_TABLE (X86_64_16) },
2378   { X86_64_TABLE (X86_64_17) },
2379   /* 18 */
2380   { "sbbB",             { Ebh1, Gb }, 0 },
2381   { "sbbS",             { Evh1, Gv }, 0 },
2382   { "sbbB",             { Gb, EbS }, 0 },
2383   { "sbbS",             { Gv, EvS }, 0 },
2384   { "sbbB",             { AL, Ib }, 0 },
2385   { "sbbS",             { eAX, Iv }, 0 },
2386   { X86_64_TABLE (X86_64_1E) },
2387   { X86_64_TABLE (X86_64_1F) },
2388   /* 20 */
2389   { "andB",             { Ebh1, Gb }, 0 },
2390   { "andS",             { Evh1, Gv }, 0 },
2391   { "andB",             { Gb, EbS }, 0 },
2392   { "andS",             { Gv, EvS }, 0 },
2393   { "andB",             { AL, Ib }, 0 },
2394   { "andS",             { eAX, Iv }, 0 },
2395   { Bad_Opcode },       /* SEG ES prefix */
2396   { X86_64_TABLE (X86_64_27) },
2397   /* 28 */
2398   { "subB",             { Ebh1, Gb }, 0 },
2399   { "subS",             { Evh1, Gv }, 0 },
2400   { "subB",             { Gb, EbS }, 0 },
2401   { "subS",             { Gv, EvS }, 0 },
2402   { "subB",             { AL, Ib }, 0 },
2403   { "subS",             { eAX, Iv }, 0 },
2404   { Bad_Opcode },       /* SEG CS prefix */
2405   { X86_64_TABLE (X86_64_2F) },
2406   /* 30 */
2407   { "xorB",             { Ebh1, Gb }, 0 },
2408   { "xorS",             { Evh1, Gv }, 0 },
2409   { "xorB",             { Gb, EbS }, 0 },
2410   { "xorS",             { Gv, EvS }, 0 },
2411   { "xorB",             { AL, Ib }, 0 },
2412   { "xorS",             { eAX, Iv }, 0 },
2413   { Bad_Opcode },       /* SEG SS prefix */
2414   { X86_64_TABLE (X86_64_37) },
2415   /* 38 */
2416   { "cmpB",             { Eb, Gb }, 0 },
2417   { "cmpS",             { Ev, Gv }, 0 },
2418   { "cmpB",             { Gb, EbS }, 0 },
2419   { "cmpS",             { Gv, EvS }, 0 },
2420   { "cmpB",             { AL, Ib }, 0 },
2421   { "cmpS",             { eAX, Iv }, 0 },
2422   { Bad_Opcode },       /* SEG DS prefix */
2423   { X86_64_TABLE (X86_64_3F) },
2424   /* 40 */
2425   { "inc{S|}",          { RMeAX }, 0 },
2426   { "inc{S|}",          { RMeCX }, 0 },
2427   { "inc{S|}",          { RMeDX }, 0 },
2428   { "inc{S|}",          { RMeBX }, 0 },
2429   { "inc{S|}",          { RMeSP }, 0 },
2430   { "inc{S|}",          { RMeBP }, 0 },
2431   { "inc{S|}",          { RMeSI }, 0 },
2432   { "inc{S|}",          { RMeDI }, 0 },
2433   /* 48 */
2434   { "dec{S|}",          { RMeAX }, 0 },
2435   { "dec{S|}",          { RMeCX }, 0 },
2436   { "dec{S|}",          { RMeDX }, 0 },
2437   { "dec{S|}",          { RMeBX }, 0 },
2438   { "dec{S|}",          { RMeSP }, 0 },
2439   { "dec{S|}",          { RMeBP }, 0 },
2440   { "dec{S|}",          { RMeSI }, 0 },
2441   { "dec{S|}",          { RMeDI }, 0 },
2442   /* 50 */
2443   { "pushV",            { RMrAX }, 0 },
2444   { "pushV",            { RMrCX }, 0 },
2445   { "pushV",            { RMrDX }, 0 },
2446   { "pushV",            { RMrBX }, 0 },
2447   { "pushV",            { RMrSP }, 0 },
2448   { "pushV",            { RMrBP }, 0 },
2449   { "pushV",            { RMrSI }, 0 },
2450   { "pushV",            { RMrDI }, 0 },
2451   /* 58 */
2452   { "popV",             { RMrAX }, 0 },
2453   { "popV",             { RMrCX }, 0 },
2454   { "popV",             { RMrDX }, 0 },
2455   { "popV",             { RMrBX }, 0 },
2456   { "popV",             { RMrSP }, 0 },
2457   { "popV",             { RMrBP }, 0 },
2458   { "popV",             { RMrSI }, 0 },
2459   { "popV",             { RMrDI }, 0 },
2460   /* 60 */
2461   { X86_64_TABLE (X86_64_60) },
2462   { X86_64_TABLE (X86_64_61) },
2463   { X86_64_TABLE (X86_64_62) },
2464   { X86_64_TABLE (X86_64_63) },
2465   { Bad_Opcode },       /* seg fs */
2466   { Bad_Opcode },       /* seg gs */
2467   { Bad_Opcode },       /* op size prefix */
2468   { Bad_Opcode },       /* adr size prefix */
2469   /* 68 */
2470   { "pushT",            { sIv }, 0 },
2471   { "imulS",            { Gv, Ev, Iv }, 0 },
2472   { "pushT",            { sIbT }, 0 },
2473   { "imulS",            { Gv, Ev, sIb }, 0 },
2474   { "ins{b|}",          { Ybr, indirDX }, 0 },
2475   { X86_64_TABLE (X86_64_6D) },
2476   { "outs{b|}",         { indirDXr, Xb }, 0 },
2477   { X86_64_TABLE (X86_64_6F) },
2478   /* 70 */
2479   { "joH",              { Jb, BND, cond_jump_flag }, 0 },
2480   { "jnoH",             { Jb, BND, cond_jump_flag }, 0 },
2481   { "jbH",              { Jb, BND, cond_jump_flag }, 0 },
2482   { "jaeH",             { Jb, BND, cond_jump_flag }, 0 },
2483   { "jeH",              { Jb, BND, cond_jump_flag }, 0 },
2484   { "jneH",             { Jb, BND, cond_jump_flag }, 0 },
2485   { "jbeH",             { Jb, BND, cond_jump_flag }, 0 },
2486   { "jaH",              { Jb, BND, cond_jump_flag }, 0 },
2487   /* 78 */
2488   { "jsH",              { Jb, BND, cond_jump_flag }, 0 },
2489   { "jnsH",             { Jb, BND, cond_jump_flag }, 0 },
2490   { "jpH",              { Jb, BND, cond_jump_flag }, 0 },
2491   { "jnpH",             { Jb, BND, cond_jump_flag }, 0 },
2492   { "jlH",              { Jb, BND, cond_jump_flag }, 0 },
2493   { "jgeH",             { Jb, BND, cond_jump_flag }, 0 },
2494   { "jleH",             { Jb, BND, cond_jump_flag }, 0 },
2495   { "jgH",              { Jb, BND, cond_jump_flag }, 0 },
2496   /* 80 */
2497   { REG_TABLE (REG_80) },
2498   { REG_TABLE (REG_81) },
2499   { X86_64_TABLE (X86_64_82) },
2500   { REG_TABLE (REG_83) },
2501   { "testB",            { Eb, Gb }, 0 },
2502   { "testS",            { Ev, Gv }, 0 },
2503   { "xchgB",            { Ebh2, Gb }, 0 },
2504   { "xchgS",            { Evh2, Gv }, 0 },
2505   /* 88 */
2506   { "movB",             { Ebh3, Gb }, 0 },
2507   { "movS",             { Evh3, Gv }, 0 },
2508   { "movB",             { Gb, EbS }, 0 },
2509   { "movS",             { Gv, EvS }, 0 },
2510   { "movD",             { Sv, Sw }, 0 },
2511   { MOD_TABLE (MOD_8D) },
2512   { "movD",             { Sw, Sv }, 0 },
2513   { REG_TABLE (REG_8F) },
2514   /* 90 */
2515   { PREFIX_TABLE (PREFIX_90) },
2516   { "xchgS",            { RMeCX, eAX }, 0 },
2517   { "xchgS",            { RMeDX, eAX }, 0 },
2518   { "xchgS",            { RMeBX, eAX }, 0 },
2519   { "xchgS",            { RMeSP, eAX }, 0 },
2520   { "xchgS",            { RMeBP, eAX }, 0 },
2521   { "xchgS",            { RMeSI, eAX }, 0 },
2522   { "xchgS",            { RMeDI, eAX }, 0 },
2523   /* 98 */
2524   { "cW{t|}R",          { XX }, 0 },
2525   { "cR{t|}O",          { XX }, 0 },
2526   { X86_64_TABLE (X86_64_9A) },
2527   { Bad_Opcode },       /* fwait */
2528   { "pushfT",           { XX }, 0 },
2529   { "popfT",            { XX }, 0 },
2530   { "sahf",             { XX }, 0 },
2531   { "lahf",             { XX }, 0 },
2532   /* a0 */
2533   { "mov%LB",           { AL, Ob }, 0 },
2534   { "mov%LS",           { eAX, Ov }, 0 },
2535   { "mov%LB",           { Ob, AL }, 0 },
2536   { "mov%LS",           { Ov, eAX }, 0 },
2537   { "movs{b|}",         { Ybr, Xb }, 0 },
2538   { "movs{R|}",         { Yvr, Xv }, 0 },
2539   { "cmps{b|}",         { Xb, Yb }, 0 },
2540   { "cmps{R|}",         { Xv, Yv }, 0 },
2541   /* a8 */
2542   { "testB",            { AL, Ib }, 0 },
2543   { "testS",            { eAX, Iv }, 0 },
2544   { "stosB",            { Ybr, AL }, 0 },
2545   { "stosS",            { Yvr, eAX }, 0 },
2546   { "lodsB",            { ALr, Xb }, 0 },
2547   { "lodsS",            { eAXr, Xv }, 0 },
2548   { "scasB",            { AL, Yb }, 0 },
2549   { "scasS",            { eAX, Yv }, 0 },
2550   /* b0 */
2551   { "movB",             { RMAL, Ib }, 0 },
2552   { "movB",             { RMCL, Ib }, 0 },
2553   { "movB",             { RMDL, Ib }, 0 },
2554   { "movB",             { RMBL, Ib }, 0 },
2555   { "movB",             { RMAH, Ib }, 0 },
2556   { "movB",             { RMCH, Ib }, 0 },
2557   { "movB",             { RMDH, Ib }, 0 },
2558   { "movB",             { RMBH, Ib }, 0 },
2559   /* b8 */
2560   { "mov%LV",           { RMeAX, Iv64 }, 0 },
2561   { "mov%LV",           { RMeCX, Iv64 }, 0 },
2562   { "mov%LV",           { RMeDX, Iv64 }, 0 },
2563   { "mov%LV",           { RMeBX, Iv64 }, 0 },
2564   { "mov%LV",           { RMeSP, Iv64 }, 0 },
2565   { "mov%LV",           { RMeBP, Iv64 }, 0 },
2566   { "mov%LV",           { RMeSI, Iv64 }, 0 },
2567   { "mov%LV",           { RMeDI, Iv64 }, 0 },
2568   /* c0 */
2569   { REG_TABLE (REG_C0) },
2570   { REG_TABLE (REG_C1) },
2571   { "retT",             { Iw, BND }, 0 },
2572   { "retT",             { BND }, 0 },
2573   { X86_64_TABLE (X86_64_C4) },
2574   { X86_64_TABLE (X86_64_C5) },
2575   { REG_TABLE (REG_C6) },
2576   { REG_TABLE (REG_C7) },
2577   /* c8 */
2578   { "enterT",           { Iw, Ib }, 0 },
2579   { "leaveT",           { XX }, 0 },
2580   { "Jret{|f}P",        { Iw }, 0 },
2581   { "Jret{|f}P",        { XX }, 0 },
2582   { "int3",             { XX }, 0 },
2583   { "int",              { Ib }, 0 },
2584   { X86_64_TABLE (X86_64_CE) },
2585   { "iret%LP",          { XX }, 0 },
2586   /* d0 */
2587   { REG_TABLE (REG_D0) },
2588   { REG_TABLE (REG_D1) },
2589   { REG_TABLE (REG_D2) },
2590   { REG_TABLE (REG_D3) },
2591   { X86_64_TABLE (X86_64_D4) },
2592   { X86_64_TABLE (X86_64_D5) },
2593   { Bad_Opcode },
2594   { "xlat",             { DSBX }, 0 },
2595   /* d8 */
2596   { FLOAT },
2597   { FLOAT },
2598   { FLOAT },
2599   { FLOAT },
2600   { FLOAT },
2601   { FLOAT },
2602   { FLOAT },
2603   { FLOAT },
2604   /* e0 */
2605   { "loopneFH",         { Jb, XX, loop_jcxz_flag }, 0 },
2606   { "loopeFH",          { Jb, XX, loop_jcxz_flag }, 0 },
2607   { "loopFH",           { Jb, XX, loop_jcxz_flag }, 0 },
2608   { "jEcxzH",           { Jb, XX, loop_jcxz_flag }, 0 },
2609   { "inB",              { AL, Ib }, 0 },
2610   { "inG",              { zAX, Ib }, 0 },
2611   { "outB",             { Ib, AL }, 0 },
2612   { "outG",             { Ib, zAX }, 0 },
2613   /* e8 */
2614   { X86_64_TABLE (X86_64_E8) },
2615   { X86_64_TABLE (X86_64_E9) },
2616   { X86_64_TABLE (X86_64_EA) },
2617   { "jmp",              { Jb, BND }, 0 },
2618   { "inB",              { AL, indirDX }, 0 },
2619   { "inG",              { zAX, indirDX }, 0 },
2620   { "outB",             { indirDX, AL }, 0 },
2621   { "outG",             { indirDX, zAX }, 0 },
2622   /* f0 */
2623   { Bad_Opcode },       /* lock prefix */
2624   { "icebp",            { XX }, 0 },
2625   { Bad_Opcode },       /* repne */
2626   { Bad_Opcode },       /* repz */
2627   { "hlt",              { XX }, 0 },
2628   { "cmc",              { XX }, 0 },
2629   { REG_TABLE (REG_F6) },
2630   { REG_TABLE (REG_F7) },
2631   /* f8 */
2632   { "clc",              { XX }, 0 },
2633   { "stc",              { XX }, 0 },
2634   { "cli",              { XX }, 0 },
2635   { "sti",              { XX }, 0 },
2636   { "cld",              { XX }, 0 },
2637   { "std",              { XX }, 0 },
2638   { REG_TABLE (REG_FE) },
2639   { REG_TABLE (REG_FF) },
2640 };
2641
2642 static const struct dis386 dis386_twobyte[] = {
2643   /* 00 */
2644   { REG_TABLE (REG_0F00 ) },
2645   { REG_TABLE (REG_0F01 ) },
2646   { "larS",             { Gv, Ew }, 0 },
2647   { "lslS",             { Gv, Ew }, 0 },
2648   { Bad_Opcode },
2649   { "syscall",          { XX }, 0 },
2650   { "clts",             { XX }, 0 },
2651   { "sysret%LP",                { XX }, 0 },
2652   /* 08 */
2653   { "invd",             { XX }, 0 },
2654   { PREFIX_TABLE (PREFIX_0F09) },
2655   { Bad_Opcode },
2656   { "ud2",              { XX }, 0 },
2657   { Bad_Opcode },
2658   { REG_TABLE (REG_0F0D) },
2659   { "femms",            { XX }, 0 },
2660   { "",                 { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix.  */
2661   /* 10 */
2662   { PREFIX_TABLE (PREFIX_0F10) },
2663   { PREFIX_TABLE (PREFIX_0F11) },
2664   { PREFIX_TABLE (PREFIX_0F12) },
2665   { MOD_TABLE (MOD_0F13) },
2666   { "unpcklpX",         { XM, EXx }, PREFIX_OPCODE },
2667   { "unpckhpX",         { XM, EXx }, PREFIX_OPCODE },
2668   { PREFIX_TABLE (PREFIX_0F16) },
2669   { MOD_TABLE (MOD_0F17) },
2670   /* 18 */
2671   { REG_TABLE (REG_0F18) },
2672   { "nopQ",             { Ev }, 0 },
2673   { PREFIX_TABLE (PREFIX_0F1A) },
2674   { PREFIX_TABLE (PREFIX_0F1B) },
2675   { PREFIX_TABLE (PREFIX_0F1C) },
2676   { "nopQ",             { Ev }, 0 },
2677   { PREFIX_TABLE (PREFIX_0F1E) },
2678   { "nopQ",             { Ev }, 0 },
2679   /* 20 */
2680   { "movZ",             { Rm, Cm }, 0 },
2681   { "movZ",             { Rm, Dm }, 0 },
2682   { "movZ",             { Cm, Rm }, 0 },
2683   { "movZ",             { Dm, Rm }, 0 },
2684   { MOD_TABLE (MOD_0F24) },
2685   { Bad_Opcode },
2686   { MOD_TABLE (MOD_0F26) },
2687   { Bad_Opcode },
2688   /* 28 */
2689   { "movapX",           { XM, EXx }, PREFIX_OPCODE },
2690   { "movapX",           { EXxS, XM }, PREFIX_OPCODE },
2691   { PREFIX_TABLE (PREFIX_0F2A) },
2692   { PREFIX_TABLE (PREFIX_0F2B) },
2693   { PREFIX_TABLE (PREFIX_0F2C) },
2694   { PREFIX_TABLE (PREFIX_0F2D) },
2695   { PREFIX_TABLE (PREFIX_0F2E) },
2696   { PREFIX_TABLE (PREFIX_0F2F) },
2697   /* 30 */
2698   { "wrmsr",            { XX }, 0 },
2699   { "rdtsc",            { XX }, 0 },
2700   { "rdmsr",            { XX }, 0 },
2701   { "rdpmc",            { XX }, 0 },
2702   { "sysenter",         { XX }, 0 },
2703   { "sysexit",          { XX }, 0 },
2704   { Bad_Opcode },
2705   { "getsec",           { XX }, 0 },
2706   /* 38 */
2707   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2708   { Bad_Opcode },
2709   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2710   { Bad_Opcode },
2711   { Bad_Opcode },
2712   { Bad_Opcode },
2713   { Bad_Opcode },
2714   { Bad_Opcode },
2715   /* 40 */
2716   { "cmovoS",           { Gv, Ev }, 0 },
2717   { "cmovnoS",          { Gv, Ev }, 0 },
2718   { "cmovbS",           { Gv, Ev }, 0 },
2719   { "cmovaeS",          { Gv, Ev }, 0 },
2720   { "cmoveS",           { Gv, Ev }, 0 },
2721   { "cmovneS",          { Gv, Ev }, 0 },
2722   { "cmovbeS",          { Gv, Ev }, 0 },
2723   { "cmovaS",           { Gv, Ev }, 0 },
2724   /* 48 */
2725   { "cmovsS",           { Gv, Ev }, 0 },
2726   { "cmovnsS",          { Gv, Ev }, 0 },
2727   { "cmovpS",           { Gv, Ev }, 0 },
2728   { "cmovnpS",          { Gv, Ev }, 0 },
2729   { "cmovlS",           { Gv, Ev }, 0 },
2730   { "cmovgeS",          { Gv, Ev }, 0 },
2731   { "cmovleS",          { Gv, Ev }, 0 },
2732   { "cmovgS",           { Gv, Ev }, 0 },
2733   /* 50 */
2734   { MOD_TABLE (MOD_0F51) },
2735   { PREFIX_TABLE (PREFIX_0F51) },
2736   { PREFIX_TABLE (PREFIX_0F52) },
2737   { PREFIX_TABLE (PREFIX_0F53) },
2738   { "andpX",            { XM, EXx }, PREFIX_OPCODE },
2739   { "andnpX",           { XM, EXx }, PREFIX_OPCODE },
2740   { "orpX",             { XM, EXx }, PREFIX_OPCODE },
2741   { "xorpX",            { XM, EXx }, PREFIX_OPCODE },
2742   /* 58 */
2743   { PREFIX_TABLE (PREFIX_0F58) },
2744   { PREFIX_TABLE (PREFIX_0F59) },
2745   { PREFIX_TABLE (PREFIX_0F5A) },
2746   { PREFIX_TABLE (PREFIX_0F5B) },
2747   { PREFIX_TABLE (PREFIX_0F5C) },
2748   { PREFIX_TABLE (PREFIX_0F5D) },
2749   { PREFIX_TABLE (PREFIX_0F5E) },
2750   { PREFIX_TABLE (PREFIX_0F5F) },
2751   /* 60 */
2752   { PREFIX_TABLE (PREFIX_0F60) },
2753   { PREFIX_TABLE (PREFIX_0F61) },
2754   { PREFIX_TABLE (PREFIX_0F62) },
2755   { "packsswb",         { MX, EM }, PREFIX_OPCODE },
2756   { "pcmpgtb",          { MX, EM }, PREFIX_OPCODE },
2757   { "pcmpgtw",          { MX, EM }, PREFIX_OPCODE },
2758   { "pcmpgtd",          { MX, EM }, PREFIX_OPCODE },
2759   { "packuswb",         { MX, EM }, PREFIX_OPCODE },
2760   /* 68 */
2761   { "punpckhbw",        { MX, EM }, PREFIX_OPCODE },
2762   { "punpckhwd",        { MX, EM }, PREFIX_OPCODE },
2763   { "punpckhdq",        { MX, EM }, PREFIX_OPCODE },
2764   { "packssdw",         { MX, EM }, PREFIX_OPCODE },
2765   { PREFIX_TABLE (PREFIX_0F6C) },
2766   { PREFIX_TABLE (PREFIX_0F6D) },
2767   { "movK",             { MX, Edq }, PREFIX_OPCODE },
2768   { PREFIX_TABLE (PREFIX_0F6F) },
2769   /* 70 */
2770   { PREFIX_TABLE (PREFIX_0F70) },
2771   { REG_TABLE (REG_0F71) },
2772   { REG_TABLE (REG_0F72) },
2773   { REG_TABLE (REG_0F73) },
2774   { "pcmpeqb",          { MX, EM }, PREFIX_OPCODE },
2775   { "pcmpeqw",          { MX, EM }, PREFIX_OPCODE },
2776   { "pcmpeqd",          { MX, EM }, PREFIX_OPCODE },
2777   { "emms",             { XX }, PREFIX_OPCODE },
2778   /* 78 */
2779   { PREFIX_TABLE (PREFIX_0F78) },
2780   { PREFIX_TABLE (PREFIX_0F79) },
2781   { Bad_Opcode },
2782   { Bad_Opcode },
2783   { PREFIX_TABLE (PREFIX_0F7C) },
2784   { PREFIX_TABLE (PREFIX_0F7D) },
2785   { PREFIX_TABLE (PREFIX_0F7E) },
2786   { PREFIX_TABLE (PREFIX_0F7F) },
2787   /* 80 */
2788   { "joH",              { Jv, BND, cond_jump_flag }, 0 },
2789   { "jnoH",             { Jv, BND, cond_jump_flag }, 0 },
2790   { "jbH",              { Jv, BND, cond_jump_flag }, 0 },
2791   { "jaeH",             { Jv, BND, cond_jump_flag }, 0 },
2792   { "jeH",              { Jv, BND, cond_jump_flag }, 0 },
2793   { "jneH",             { Jv, BND, cond_jump_flag }, 0 },
2794   { "jbeH",             { Jv, BND, cond_jump_flag }, 0 },
2795   { "jaH",              { Jv, BND, cond_jump_flag }, 0 },
2796   /* 88 */
2797   { "jsH",              { Jv, BND, cond_jump_flag }, 0 },
2798   { "jnsH",             { Jv, BND, cond_jump_flag }, 0 },
2799   { "jpH",              { Jv, BND, cond_jump_flag }, 0 },
2800   { "jnpH",             { Jv, BND, cond_jump_flag }, 0 },
2801   { "jlH",              { Jv, BND, cond_jump_flag }, 0 },
2802   { "jgeH",             { Jv, BND, cond_jump_flag }, 0 },
2803   { "jleH",             { Jv, BND, cond_jump_flag }, 0 },
2804   { "jgH",              { Jv, BND, cond_jump_flag }, 0 },
2805   /* 90 */
2806   { "seto",             { Eb }, 0 },
2807   { "setno",            { Eb }, 0 },
2808   { "setb",             { Eb }, 0 },
2809   { "setae",            { Eb }, 0 },
2810   { "sete",             { Eb }, 0 },
2811   { "setne",            { Eb }, 0 },
2812   { "setbe",            { Eb }, 0 },
2813   { "seta",             { Eb }, 0 },
2814   /* 98 */
2815   { "sets",             { Eb }, 0 },
2816   { "setns",            { Eb }, 0 },
2817   { "setp",             { Eb }, 0 },
2818   { "setnp",            { Eb }, 0 },
2819   { "setl",             { Eb }, 0 },
2820   { "setge",            { Eb }, 0 },
2821   { "setle",            { Eb }, 0 },
2822   { "setg",             { Eb }, 0 },
2823   /* a0 */
2824   { "pushT",            { fs }, 0 },
2825   { "popT",             { fs }, 0 },
2826   { "cpuid",            { XX }, 0 },
2827   { "btS",              { Ev, Gv }, 0 },
2828   { "shldS",            { Ev, Gv, Ib }, 0 },
2829   { "shldS",            { Ev, Gv, CL }, 0 },
2830   { REG_TABLE (REG_0FA6) },
2831   { REG_TABLE (REG_0FA7) },
2832   /* a8 */
2833   { "pushT",            { gs }, 0 },
2834   { "popT",             { gs }, 0 },
2835   { "rsm",              { XX }, 0 },
2836   { "btsS",             { Evh1, Gv }, 0 },
2837   { "shrdS",            { Ev, Gv, Ib }, 0 },
2838   { "shrdS",            { Ev, Gv, CL }, 0 },
2839   { REG_TABLE (REG_0FAE) },
2840   { "imulS",            { Gv, Ev }, 0 },
2841   /* b0 */
2842   { "cmpxchgB",         { Ebh1, Gb }, 0 },
2843   { "cmpxchgS",         { Evh1, Gv }, 0 },
2844   { MOD_TABLE (MOD_0FB2) },
2845   { "btrS",             { Evh1, Gv }, 0 },
2846   { MOD_TABLE (MOD_0FB4) },
2847   { MOD_TABLE (MOD_0FB5) },
2848   { "movz{bR|x}",       { Gv, Eb }, 0 },
2849   { "movz{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
2850   /* b8 */
2851   { PREFIX_TABLE (PREFIX_0FB8) },
2852   { "ud1S",             { Gv, Ev }, 0 },
2853   { REG_TABLE (REG_0FBA) },
2854   { "btcS",             { Evh1, Gv }, 0 },
2855   { PREFIX_TABLE (PREFIX_0FBC) },
2856   { PREFIX_TABLE (PREFIX_0FBD) },
2857   { "movs{bR|x}",       { Gv, Eb }, 0 },
2858   { "movs{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
2859   /* c0 */
2860   { "xaddB",            { Ebh1, Gb }, 0 },
2861   { "xaddS",            { Evh1, Gv }, 0 },
2862   { PREFIX_TABLE (PREFIX_0FC2) },
2863   { MOD_TABLE (MOD_0FC3) },
2864   { "pinsrw",           { MX, Edqw, Ib }, PREFIX_OPCODE },
2865   { "pextrw",           { Gdq, MS, Ib }, PREFIX_OPCODE },
2866   { "shufpX",           { XM, EXx, Ib }, PREFIX_OPCODE },
2867   { REG_TABLE (REG_0FC7) },
2868   /* c8 */
2869   { "bswap",            { RMeAX }, 0 },
2870   { "bswap",            { RMeCX }, 0 },
2871   { "bswap",            { RMeDX }, 0 },
2872   { "bswap",            { RMeBX }, 0 },
2873   { "bswap",            { RMeSP }, 0 },
2874   { "bswap",            { RMeBP }, 0 },
2875   { "bswap",            { RMeSI }, 0 },
2876   { "bswap",            { RMeDI }, 0 },
2877   /* d0 */
2878   { PREFIX_TABLE (PREFIX_0FD0) },
2879   { "psrlw",            { MX, EM }, PREFIX_OPCODE },
2880   { "psrld",            { MX, EM }, PREFIX_OPCODE },
2881   { "psrlq",            { MX, EM }, PREFIX_OPCODE },
2882   { "paddq",            { MX, EM }, PREFIX_OPCODE },
2883   { "pmullw",           { MX, EM }, PREFIX_OPCODE },
2884   { PREFIX_TABLE (PREFIX_0FD6) },
2885   { MOD_TABLE (MOD_0FD7) },
2886   /* d8 */
2887   { "psubusb",          { MX, EM }, PREFIX_OPCODE },
2888   { "psubusw",          { MX, EM }, PREFIX_OPCODE },
2889   { "pminub",           { MX, EM }, PREFIX_OPCODE },
2890   { "pand",             { MX, EM }, PREFIX_OPCODE },
2891   { "paddusb",          { MX, EM }, PREFIX_OPCODE },
2892   { "paddusw",          { MX, EM }, PREFIX_OPCODE },
2893   { "pmaxub",           { MX, EM }, PREFIX_OPCODE },
2894   { "pandn",            { MX, EM }, PREFIX_OPCODE },
2895   /* e0 */
2896   { "pavgb",            { MX, EM }, PREFIX_OPCODE },
2897   { "psraw",            { MX, EM }, PREFIX_OPCODE },
2898   { "psrad",            { MX, EM }, PREFIX_OPCODE },
2899   { "pavgw",            { MX, EM }, PREFIX_OPCODE },
2900   { "pmulhuw",          { MX, EM }, PREFIX_OPCODE },
2901   { "pmulhw",           { MX, EM }, PREFIX_OPCODE },
2902   { PREFIX_TABLE (PREFIX_0FE6) },
2903   { PREFIX_TABLE (PREFIX_0FE7) },
2904   /* e8 */
2905   { "psubsb",           { MX, EM }, PREFIX_OPCODE },
2906   { "psubsw",           { MX, EM }, PREFIX_OPCODE },
2907   { "pminsw",           { MX, EM }, PREFIX_OPCODE },
2908   { "por",              { MX, EM }, PREFIX_OPCODE },
2909   { "paddsb",           { MX, EM }, PREFIX_OPCODE },
2910   { "paddsw",           { MX, EM }, PREFIX_OPCODE },
2911   { "pmaxsw",           { MX, EM }, PREFIX_OPCODE },
2912   { "pxor",             { MX, EM }, PREFIX_OPCODE },
2913   /* f0 */
2914   { PREFIX_TABLE (PREFIX_0FF0) },
2915   { "psllw",            { MX, EM }, PREFIX_OPCODE },
2916   { "pslld",            { MX, EM }, PREFIX_OPCODE },
2917   { "psllq",            { MX, EM }, PREFIX_OPCODE },
2918   { "pmuludq",          { MX, EM }, PREFIX_OPCODE },
2919   { "pmaddwd",          { MX, EM }, PREFIX_OPCODE },
2920   { "psadbw",           { MX, EM }, PREFIX_OPCODE },
2921   { PREFIX_TABLE (PREFIX_0FF7) },
2922   /* f8 */
2923   { "psubb",            { MX, EM }, PREFIX_OPCODE },
2924   { "psubw",            { MX, EM }, PREFIX_OPCODE },
2925   { "psubd",            { MX, EM }, PREFIX_OPCODE },
2926   { "psubq",            { MX, EM }, PREFIX_OPCODE },
2927   { "paddb",            { MX, EM }, PREFIX_OPCODE },
2928   { "paddw",            { MX, EM }, PREFIX_OPCODE },
2929   { "paddd",            { MX, EM }, PREFIX_OPCODE },
2930   { "ud0S",             { Gv, Ev }, 0 },
2931 };
2932
2933 static const unsigned char onebyte_has_modrm[256] = {
2934   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2935   /*       -------------------------------        */
2936   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2937   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2938   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2939   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2940   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2941   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2942   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2943   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2944   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2945   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2946   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2947   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2948   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2949   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2950   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2951   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
2952   /*       -------------------------------        */
2953   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2954 };
2955
2956 static const unsigned char twobyte_has_modrm[256] = {
2957   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2958   /*       -------------------------------        */
2959   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2960   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2961   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2962   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2963   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2964   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2965   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2966   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2967   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2968   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2969   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2970   /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2971   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2972   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2973   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2974   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1  /* ff */
2975   /*       -------------------------------        */
2976   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2977 };
2978
2979 static char obuf[100];
2980 static char *obufp;
2981 static char *mnemonicendp;
2982 static char scratchbuf[100];
2983 static unsigned char *start_codep;
2984 static unsigned char *insn_codep;
2985 static unsigned char *codep;
2986 static unsigned char *end_codep;
2987 static int last_lock_prefix;
2988 static int last_repz_prefix;
2989 static int last_repnz_prefix;
2990 static int last_data_prefix;
2991 static int last_addr_prefix;
2992 static int last_rex_prefix;
2993 static int last_seg_prefix;
2994 static int fwait_prefix;
2995 /* The active segment register prefix.  */
2996 static int active_seg_prefix;
2997 #define MAX_CODE_LENGTH 15
2998 /* We can up to 14 prefixes since the maximum instruction length is
2999    15bytes.  */
3000 static int all_prefixes[MAX_CODE_LENGTH - 1];
3001 static disassemble_info *the_info;
3002 static struct
3003   {
3004     int mod;
3005     int reg;
3006     int rm;
3007   }
3008 modrm;
3009 static unsigned char need_modrm;
3010 static struct
3011   {
3012     int scale;
3013     int index;
3014     int base;
3015   }
3016 sib;
3017 static struct
3018   {
3019     int register_specifier;
3020     int length;
3021     int prefix;
3022     int w;
3023     int evex;
3024     int r;
3025     int v;
3026     int mask_register_specifier;
3027     int zeroing;
3028     int ll;
3029     int b;
3030   }
3031 vex;
3032 static unsigned char need_vex;
3033 static unsigned char need_vex_reg;
3034 static unsigned char vex_w_done;
3035
3036 struct op
3037   {
3038     const char *name;
3039     unsigned int len;
3040   };
3041
3042 /* If we are accessing mod/rm/reg without need_modrm set, then the
3043    values are stale.  Hitting this abort likely indicates that you
3044    need to update onebyte_has_modrm or twobyte_has_modrm.  */
3045 #define MODRM_CHECK  if (!need_modrm) abort ()
3046
3047 static const char **names64;
3048 static const char **names32;
3049 static const char **names16;
3050 static const char **names8;
3051 static const char **names8rex;
3052 static const char **names_seg;
3053 static const char *index64;
3054 static const char *index32;
3055 static const char **index16;
3056 static const char **names_bnd;
3057
3058 static const char *intel_names64[] = {
3059   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3060   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3061 };
3062 static const char *intel_names32[] = {
3063   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3064   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3065 };
3066 static const char *intel_names16[] = {
3067   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3068   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3069 };
3070 static const char *intel_names8[] = {
3071   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3072 };
3073 static const char *intel_names8rex[] = {
3074   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3075   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3076 };
3077 static const char *intel_names_seg[] = {
3078   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3079 };
3080 static const char *intel_index64 = "riz";
3081 static const char *intel_index32 = "eiz";
3082 static const char *intel_index16[] = {
3083   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3084 };
3085
3086 static const char *att_names64[] = {
3087   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3088   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3089 };
3090 static const char *att_names32[] = {
3091   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3092   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3093 };
3094 static const char *att_names16[] = {
3095   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3096   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3097 };
3098 static const char *att_names8[] = {
3099   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3100 };
3101 static const char *att_names8rex[] = {
3102   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3103   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3104 };
3105 static const char *att_names_seg[] = {
3106   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3107 };
3108 static const char *att_index64 = "%riz";
3109 static const char *att_index32 = "%eiz";
3110 static const char *att_index16[] = {
3111   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3112 };
3113
3114 static const char **names_mm;
3115 static const char *intel_names_mm[] = {
3116   "mm0", "mm1", "mm2", "mm3",
3117   "mm4", "mm5", "mm6", "mm7"
3118 };
3119 static const char *att_names_mm[] = {
3120   "%mm0", "%mm1", "%mm2", "%mm3",
3121   "%mm4", "%mm5", "%mm6", "%mm7"
3122 };
3123
3124 static const char *intel_names_bnd[] = {
3125   "bnd0", "bnd1", "bnd2", "bnd3"
3126 };
3127
3128 static const char *att_names_bnd[] = {
3129   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3130 };
3131
3132 static const char **names_xmm;
3133 static const char *intel_names_xmm[] = {
3134   "xmm0", "xmm1", "xmm2", "xmm3",
3135   "xmm4", "xmm5", "xmm6", "xmm7",
3136   "xmm8", "xmm9", "xmm10", "xmm11",
3137   "xmm12", "xmm13", "xmm14", "xmm15",
3138   "xmm16", "xmm17", "xmm18", "xmm19",
3139   "xmm20", "xmm21", "xmm22", "xmm23",
3140   "xmm24", "xmm25", "xmm26", "xmm27",
3141   "xmm28", "xmm29", "xmm30", "xmm31"
3142 };
3143 static const char *att_names_xmm[] = {
3144   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3145   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3146   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3147   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3148   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3149   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3150   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3151   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3152 };
3153
3154 static const char **names_ymm;
3155 static const char *intel_names_ymm[] = {
3156   "ymm0", "ymm1", "ymm2", "ymm3",
3157   "ymm4", "ymm5", "ymm6", "ymm7",
3158   "ymm8", "ymm9", "ymm10", "ymm11",
3159   "ymm12", "ymm13", "ymm14", "ymm15",
3160   "ymm16", "ymm17", "ymm18", "ymm19",
3161   "ymm20", "ymm21", "ymm22", "ymm23",
3162   "ymm24", "ymm25", "ymm26", "ymm27",
3163   "ymm28", "ymm29", "ymm30", "ymm31"
3164 };
3165 static const char *att_names_ymm[] = {
3166   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3167   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3168   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3169   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3170   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3171   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3172   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3173   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3174 };
3175
3176 static const char **names_zmm;
3177 static const char *intel_names_zmm[] = {
3178   "zmm0", "zmm1", "zmm2", "zmm3",
3179   "zmm4", "zmm5", "zmm6", "zmm7",
3180   "zmm8", "zmm9", "zmm10", "zmm11",
3181   "zmm12", "zmm13", "zmm14", "zmm15",
3182   "zmm16", "zmm17", "zmm18", "zmm19",
3183   "zmm20", "zmm21", "zmm22", "zmm23",
3184   "zmm24", "zmm25", "zmm26", "zmm27",
3185   "zmm28", "zmm29", "zmm30", "zmm31"
3186 };
3187 static const char *att_names_zmm[] = {
3188   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3189   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3190   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3191   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3192   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3193   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3194   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3195   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3196 };
3197
3198 static const char **names_mask;
3199 static const char *intel_names_mask[] = {
3200   "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3201 };
3202 static const char *att_names_mask[] = {
3203   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3204 };
3205
3206 static const char *names_rounding[] =
3207 {
3208   "{rn-sae}",
3209   "{rd-sae}",
3210   "{ru-sae}",
3211   "{rz-sae}"
3212 };
3213
3214 static const struct dis386 reg_table[][8] = {
3215   /* REG_80 */
3216   {
3217     { "addA",   { Ebh1, Ib }, 0 },
3218     { "orA",    { Ebh1, Ib }, 0 },
3219     { "adcA",   { Ebh1, Ib }, 0 },
3220     { "sbbA",   { Ebh1, Ib }, 0 },
3221     { "andA",   { Ebh1, Ib }, 0 },
3222     { "subA",   { Ebh1, Ib }, 0 },
3223     { "xorA",   { Ebh1, Ib }, 0 },
3224     { "cmpA",   { Eb, Ib }, 0 },
3225   },
3226   /* REG_81 */
3227   {
3228     { "addQ",   { Evh1, Iv }, 0 },
3229     { "orQ",    { Evh1, Iv }, 0 },
3230     { "adcQ",   { Evh1, Iv }, 0 },
3231     { "sbbQ",   { Evh1, Iv }, 0 },
3232     { "andQ",   { Evh1, Iv }, 0 },
3233     { "subQ",   { Evh1, Iv }, 0 },
3234     { "xorQ",   { Evh1, Iv }, 0 },
3235     { "cmpQ",   { Ev, Iv }, 0 },
3236   },
3237   /* REG_83 */
3238   {
3239     { "addQ",   { Evh1, sIb }, 0 },
3240     { "orQ",    { Evh1, sIb }, 0 },
3241     { "adcQ",   { Evh1, sIb }, 0 },
3242     { "sbbQ",   { Evh1, sIb }, 0 },
3243     { "andQ",   { Evh1, sIb }, 0 },
3244     { "subQ",   { Evh1, sIb }, 0 },
3245     { "xorQ",   { Evh1, sIb }, 0 },
3246     { "cmpQ",   { Ev, sIb }, 0 },
3247   },
3248   /* REG_8F */
3249   {
3250     { "popU",   { stackEv }, 0 },
3251     { XOP_8F_TABLE (XOP_09) },
3252     { Bad_Opcode },
3253     { Bad_Opcode },
3254     { Bad_Opcode },
3255     { XOP_8F_TABLE (XOP_09) },
3256   },
3257   /* REG_C0 */
3258   {
3259     { "rolA",   { Eb, Ib }, 0 },
3260     { "rorA",   { Eb, Ib }, 0 },
3261     { "rclA",   { Eb, Ib }, 0 },
3262     { "rcrA",   { Eb, Ib }, 0 },
3263     { "shlA",   { Eb, Ib }, 0 },
3264     { "shrA",   { Eb, Ib }, 0 },
3265     { "shlA",   { Eb, Ib }, 0 },
3266     { "sarA",   { Eb, Ib }, 0 },
3267   },
3268   /* REG_C1 */
3269   {
3270     { "rolQ",   { Ev, Ib }, 0 },
3271     { "rorQ",   { Ev, Ib }, 0 },
3272     { "rclQ",   { Ev, Ib }, 0 },
3273     { "rcrQ",   { Ev, Ib }, 0 },
3274     { "shlQ",   { Ev, Ib }, 0 },
3275     { "shrQ",   { Ev, Ib }, 0 },
3276     { "shlQ",   { Ev, Ib }, 0 },
3277     { "sarQ",   { Ev, Ib }, 0 },
3278   },
3279   /* REG_C6 */
3280   {
3281     { "movA",   { Ebh3, Ib }, 0 },
3282     { Bad_Opcode },
3283     { Bad_Opcode },
3284     { Bad_Opcode },
3285     { Bad_Opcode },
3286     { Bad_Opcode },
3287     { Bad_Opcode },
3288     { MOD_TABLE (MOD_C6_REG_7) },
3289   },
3290   /* REG_C7 */
3291   {
3292     { "movQ",   { Evh3, Iv }, 0 },
3293     { Bad_Opcode },
3294     { Bad_Opcode },
3295     { Bad_Opcode },
3296     { Bad_Opcode },
3297     { Bad_Opcode },
3298     { Bad_Opcode },
3299     { MOD_TABLE (MOD_C7_REG_7) },
3300   },
3301   /* REG_D0 */
3302   {
3303     { "rolA",   { Eb, I1 }, 0 },
3304     { "rorA",   { Eb, I1 }, 0 },
3305     { "rclA",   { Eb, I1 }, 0 },
3306     { "rcrA",   { Eb, I1 }, 0 },
3307     { "shlA",   { Eb, I1 }, 0 },
3308     { "shrA",   { Eb, I1 }, 0 },
3309     { "shlA",   { Eb, I1 }, 0 },
3310     { "sarA",   { Eb, I1 }, 0 },
3311   },
3312   /* REG_D1 */
3313   {
3314     { "rolQ",   { Ev, I1 }, 0 },
3315     { "rorQ",   { Ev, I1 }, 0 },
3316     { "rclQ",   { Ev, I1 }, 0 },
3317     { "rcrQ",   { Ev, I1 }, 0 },
3318     { "shlQ",   { Ev, I1 }, 0 },
3319     { "shrQ",   { Ev, I1 }, 0 },
3320     { "shlQ",   { Ev, I1 }, 0 },
3321     { "sarQ",   { Ev, I1 }, 0 },
3322   },
3323   /* REG_D2 */
3324   {
3325     { "rolA",   { Eb, CL }, 0 },
3326     { "rorA",   { Eb, CL }, 0 },
3327     { "rclA",   { Eb, CL }, 0 },
3328     { "rcrA",   { Eb, CL }, 0 },
3329     { "shlA",   { Eb, CL }, 0 },
3330     { "shrA",   { Eb, CL }, 0 },
3331     { "shlA",   { Eb, CL }, 0 },
3332     { "sarA",   { Eb, CL }, 0 },
3333   },
3334   /* REG_D3 */
3335   {
3336     { "rolQ",   { Ev, CL }, 0 },
3337     { "rorQ",   { Ev, CL }, 0 },
3338     { "rclQ",   { Ev, CL }, 0 },
3339     { "rcrQ",   { Ev, CL }, 0 },
3340     { "shlQ",   { Ev, CL }, 0 },
3341     { "shrQ",   { Ev, CL }, 0 },
3342     { "shlQ",   { Ev, CL }, 0 },
3343     { "sarQ",   { Ev, CL }, 0 },
3344   },
3345   /* REG_F6 */
3346   {
3347     { "testA",  { Eb, Ib }, 0 },
3348     { "testA",  { Eb, Ib }, 0 },
3349     { "notA",   { Ebh1 }, 0 },
3350     { "negA",   { Ebh1 }, 0 },
3351     { "mulA",   { Eb }, 0 },    /* Don't print the implicit %al register,  */
3352     { "imulA",  { Eb }, 0 },    /* to distinguish these opcodes from other */
3353     { "divA",   { Eb }, 0 },    /* mul/imul opcodes.  Do the same for div  */
3354     { "idivA",  { Eb }, 0 },    /* and idiv for consistency.               */
3355   },
3356   /* REG_F7 */
3357   {
3358     { "testQ",  { Ev, Iv }, 0 },
3359     { "testQ",  { Ev, Iv }, 0 },
3360     { "notQ",   { Evh1 }, 0 },
3361     { "negQ",   { Evh1 }, 0 },
3362     { "mulQ",   { Ev }, 0 },    /* Don't print the implicit register.  */
3363     { "imulQ",  { Ev }, 0 },
3364     { "divQ",   { Ev }, 0 },
3365     { "idivQ",  { Ev }, 0 },
3366   },
3367   /* REG_FE */
3368   {
3369     { "incA",   { Ebh1 }, 0 },
3370     { "decA",   { Ebh1 }, 0 },
3371   },
3372   /* REG_FF */
3373   {
3374     { "incQ",   { Evh1 }, 0 },
3375     { "decQ",   { Evh1 }, 0 },
3376     { "call{&|}", { NOTRACK, indirEv, BND }, 0 },
3377     { MOD_TABLE (MOD_FF_REG_3) },
3378     { "jmp{&|}", { NOTRACK, indirEv, BND }, 0 },
3379     { MOD_TABLE (MOD_FF_REG_5) },
3380     { "pushU",  { stackEv }, 0 },
3381     { Bad_Opcode },
3382   },
3383   /* REG_0F00 */
3384   {
3385     { "sldtD",  { Sv }, 0 },
3386     { "strD",   { Sv }, 0 },
3387     { "lldt",   { Ew }, 0 },
3388     { "ltr",    { Ew }, 0 },
3389     { "verr",   { Ew }, 0 },
3390     { "verw",   { Ew }, 0 },
3391     { Bad_Opcode },
3392     { Bad_Opcode },
3393   },
3394   /* REG_0F01 */
3395   {
3396     { MOD_TABLE (MOD_0F01_REG_0) },
3397     { MOD_TABLE (MOD_0F01_REG_1) },
3398     { MOD_TABLE (MOD_0F01_REG_2) },
3399     { MOD_TABLE (MOD_0F01_REG_3) },
3400     { "smswD",  { Sv }, 0 },
3401     { MOD_TABLE (MOD_0F01_REG_5) },
3402     { "lmsw",   { Ew }, 0 },
3403     { MOD_TABLE (MOD_0F01_REG_7) },
3404   },
3405   /* REG_0F0D */
3406   {
3407     { "prefetch",       { Mb }, 0 },
3408     { "prefetchw",      { Mb }, 0 },
3409     { "prefetchwt1",    { Mb }, 0 },
3410     { "prefetch",       { Mb }, 0 },
3411     { "prefetch",       { Mb }, 0 },
3412     { "prefetch",       { Mb }, 0 },
3413     { "prefetch",       { Mb }, 0 },
3414     { "prefetch",       { Mb }, 0 },
3415   },
3416   /* REG_0F18 */
3417   {
3418     { MOD_TABLE (MOD_0F18_REG_0) },
3419     { MOD_TABLE (MOD_0F18_REG_1) },
3420     { MOD_TABLE (MOD_0F18_REG_2) },
3421     { MOD_TABLE (MOD_0F18_REG_3) },
3422     { MOD_TABLE (MOD_0F18_REG_4) },
3423     { MOD_TABLE (MOD_0F18_REG_5) },
3424     { MOD_TABLE (MOD_0F18_REG_6) },
3425     { MOD_TABLE (MOD_0F18_REG_7) },
3426   },
3427   /* REG_0F1C_MOD_0 */
3428   {
3429     { "cldemote",       { Mb }, 0 },
3430     { "nopQ",           { Ev }, 0 },
3431     { "nopQ",           { Ev }, 0 },
3432     { "nopQ",           { Ev }, 0 },
3433     { "nopQ",           { Ev }, 0 },
3434     { "nopQ",           { Ev }, 0 },
3435     { "nopQ",           { Ev }, 0 },
3436     { "nopQ",           { Ev }, 0 },
3437   },
3438   /* REG_0F1E_MOD_3 */
3439   {
3440     { "nopQ",           { Ev }, 0 },
3441     { "rdsspK",         { Rdq }, PREFIX_OPCODE },
3442     { "nopQ",           { Ev }, 0 },
3443     { "nopQ",           { Ev }, 0 },
3444     { "nopQ",           { Ev }, 0 },
3445     { "nopQ",           { Ev }, 0 },
3446     { "nopQ",           { Ev }, 0 },
3447     { RM_TABLE (RM_0F1E_MOD_3_REG_7) },
3448   },
3449   /* REG_0F71 */
3450   {
3451     { Bad_Opcode },
3452     { Bad_Opcode },
3453     { MOD_TABLE (MOD_0F71_REG_2) },
3454     { Bad_Opcode },
3455     { MOD_TABLE (MOD_0F71_REG_4) },
3456     { Bad_Opcode },
3457     { MOD_TABLE (MOD_0F71_REG_6) },
3458   },
3459   /* REG_0F72 */
3460   {
3461     { Bad_Opcode },
3462     { Bad_Opcode },
3463     { MOD_TABLE (MOD_0F72_REG_2) },
3464     { Bad_Opcode },
3465     { MOD_TABLE (MOD_0F72_REG_4) },
3466     { Bad_Opcode },
3467     { MOD_TABLE (MOD_0F72_REG_6) },
3468   },
3469   /* REG_0F73 */
3470   {
3471     { Bad_Opcode },
3472     { Bad_Opcode },
3473     { MOD_TABLE (MOD_0F73_REG_2) },
3474     { MOD_TABLE (MOD_0F73_REG_3) },
3475     { Bad_Opcode },
3476     { Bad_Opcode },
3477     { MOD_TABLE (MOD_0F73_REG_6) },
3478     { MOD_TABLE (MOD_0F73_REG_7) },
3479   },
3480   /* REG_0FA6 */
3481   {
3482     { "montmul",        { { OP_0f07, 0 } }, 0 },
3483     { "xsha1",          { { OP_0f07, 0 } }, 0 },
3484     { "xsha256",        { { OP_0f07, 0 } }, 0 },
3485   },
3486   /* REG_0FA7 */
3487   {
3488     { "xstore-rng",     { { OP_0f07, 0 } }, 0 },
3489     { "xcrypt-ecb",     { { OP_0f07, 0 } }, 0 },
3490     { "xcrypt-cbc",     { { OP_0f07, 0 } }, 0 },
3491     { "xcrypt-ctr",     { { OP_0f07, 0 } }, 0 },
3492     { "xcrypt-cfb",     { { OP_0f07, 0 } }, 0 },
3493     { "xcrypt-ofb",     { { OP_0f07, 0 } }, 0 },
3494   },
3495   /* REG_0FAE */
3496   {
3497     { MOD_TABLE (MOD_0FAE_REG_0) },
3498     { MOD_TABLE (MOD_0FAE_REG_1) },
3499     { MOD_TABLE (MOD_0FAE_REG_2) },
3500     { MOD_TABLE (MOD_0FAE_REG_3) },
3501     { MOD_TABLE (MOD_0FAE_REG_4) },
3502     { MOD_TABLE (MOD_0FAE_REG_5) },
3503     { MOD_TABLE (MOD_0FAE_REG_6) },
3504     { MOD_TABLE (MOD_0FAE_REG_7) },
3505   },
3506   /* REG_0FBA */
3507   {
3508     { Bad_Opcode },
3509     { Bad_Opcode },
3510     { Bad_Opcode },
3511     { Bad_Opcode },
3512     { "btQ",    { Ev, Ib }, 0 },
3513     { "btsQ",   { Evh1, Ib }, 0 },
3514     { "btrQ",   { Evh1, Ib }, 0 },
3515     { "btcQ",   { Evh1, Ib }, 0 },
3516   },
3517   /* REG_0FC7 */
3518   {
3519     { Bad_Opcode },
3520     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
3521     { Bad_Opcode },
3522     { MOD_TABLE (MOD_0FC7_REG_3) },
3523     { MOD_TABLE (MOD_0FC7_REG_4) },
3524     { MOD_TABLE (MOD_0FC7_REG_5) },
3525     { MOD_TABLE (MOD_0FC7_REG_6) },
3526     { MOD_TABLE (MOD_0FC7_REG_7) },
3527   },
3528   /* REG_VEX_0F71 */
3529   {
3530     { Bad_Opcode },
3531     { Bad_Opcode },
3532     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3533     { Bad_Opcode },
3534     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3535     { Bad_Opcode },
3536     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3537   },
3538   /* REG_VEX_0F72 */
3539   {
3540     { Bad_Opcode },
3541     { Bad_Opcode },
3542     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3543     { Bad_Opcode },
3544     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3545     { Bad_Opcode },
3546     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3547   },
3548   /* REG_VEX_0F73 */
3549   {
3550     { Bad_Opcode },
3551     { Bad_Opcode },
3552     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3553     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3554     { Bad_Opcode },
3555     { Bad_Opcode },
3556     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3557     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3558   },
3559   /* REG_VEX_0FAE */
3560   {
3561     { Bad_Opcode },
3562     { Bad_Opcode },
3563     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3564     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3565   },
3566   /* REG_VEX_0F38F3 */
3567   {
3568     { Bad_Opcode },
3569     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3570     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3571     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3572   },
3573   /* REG_XOP_LWPCB */
3574   {
3575     { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3576     { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3577   },
3578   /* REG_XOP_LWP */
3579   {
3580     { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3581     { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3582   },
3583   /* REG_XOP_TBM_01 */
3584   {
3585     { Bad_Opcode },
3586     { "blcfill",        { { OP_LWP_E, 0 }, Ev }, 0 },
3587     { "blsfill",        { { OP_LWP_E, 0 }, Ev }, 0 },
3588     { "blcs",   { { OP_LWP_E, 0 }, Ev }, 0 },
3589     { "tzmsk",  { { OP_LWP_E, 0 }, Ev }, 0 },
3590     { "blcic",  { { OP_LWP_E, 0 }, Ev }, 0 },
3591     { "blsic",  { { OP_LWP_E, 0 }, Ev }, 0 },
3592     { "t1mskc", { { OP_LWP_E, 0 }, Ev }, 0 },
3593   },
3594   /* REG_XOP_TBM_02 */
3595   {
3596     { Bad_Opcode },
3597     { "blcmsk", { { OP_LWP_E, 0 }, Ev }, 0 },
3598     { Bad_Opcode },
3599     { Bad_Opcode },
3600     { Bad_Opcode },
3601     { Bad_Opcode },
3602     { "blci",   { { OP_LWP_E, 0 }, Ev }, 0 },
3603   },
3604 #define NEED_REG_TABLE
3605 #include "i386-dis-evex.h"
3606 #undef NEED_REG_TABLE
3607 };
3608
3609 static const struct dis386 prefix_table[][4] = {
3610   /* PREFIX_90 */
3611   {
3612     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3613     { "pause", { XX }, 0 },
3614     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3615     { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3616   },
3617
3618   /* PREFIX_MOD_0_0F01_REG_5 */
3619   {
3620     { Bad_Opcode },
3621     { "rstorssp",       { Mq }, PREFIX_OPCODE },
3622   },
3623
3624   /* PREFIX_MOD_3_0F01_REG_5_RM_0 */
3625   {
3626     { Bad_Opcode },
3627     { "setssbsy",       { Skip_MODRM }, PREFIX_OPCODE },
3628   },
3629
3630   /* PREFIX_MOD_3_0F01_REG_5_RM_2 */
3631   {
3632     { Bad_Opcode },
3633     { "saveprevssp",    { Skip_MODRM }, PREFIX_OPCODE },
3634   },
3635
3636   /* PREFIX_0F09 */
3637   {
3638     { "wbinvd",   { XX }, 0 },
3639     { "wbnoinvd", { XX }, 0 },
3640   },
3641
3642   /* PREFIX_0F10 */
3643   {
3644     { "movups", { XM, EXx }, PREFIX_OPCODE },
3645     { "movss",  { XM, EXd }, PREFIX_OPCODE },
3646     { "movupd", { XM, EXx }, PREFIX_OPCODE },
3647     { "movsd",  { XM, EXq }, PREFIX_OPCODE },
3648   },
3649
3650   /* PREFIX_0F11 */
3651   {
3652     { "movups", { EXxS, XM }, PREFIX_OPCODE },
3653     { "movss",  { EXdS, XM }, PREFIX_OPCODE },
3654     { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3655     { "movsd",  { EXqS, XM }, PREFIX_OPCODE },
3656   },
3657
3658   /* PREFIX_0F12 */
3659   {
3660     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3661     { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3662     { "movlpd", { XM, EXq }, PREFIX_OPCODE },
3663     { "movddup", { XM, EXq }, PREFIX_OPCODE },
3664   },
3665
3666   /* PREFIX_0F16 */
3667   {
3668     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3669     { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3670     { "movhpd", { XM, EXq }, PREFIX_OPCODE },
3671   },
3672
3673   /* PREFIX_0F1A */
3674   {
3675     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3676     { "bndcl",  { Gbnd, Ev_bnd }, 0 },
3677     { "bndmov", { Gbnd, Ebnd }, 0 },
3678     { "bndcu",  { Gbnd, Ev_bnd }, 0 },
3679   },
3680
3681   /* PREFIX_0F1B */
3682   {
3683     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3684     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3685     { "bndmov", { EbndS, Gbnd }, 0 },
3686     { "bndcn",  { Gbnd, Ev_bnd }, 0 },
3687   },
3688
3689   /* PREFIX_0F1C */
3690   {
3691     { MOD_TABLE (MOD_0F1C_PREFIX_0) },
3692     { "nopQ",   { Ev }, PREFIX_OPCODE },
3693     { "nopQ",   { Ev }, PREFIX_OPCODE },
3694     { "nopQ",   { Ev }, PREFIX_OPCODE },
3695   },
3696
3697   /* PREFIX_0F1E */
3698   {
3699     { "nopQ",   { Ev }, PREFIX_OPCODE },
3700     { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3701     { "nopQ",   { Ev }, PREFIX_OPCODE },
3702     { "nopQ",   { Ev }, PREFIX_OPCODE },
3703   },
3704
3705   /* PREFIX_0F2A */
3706   {
3707     { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3708     { "cvtsi2ss%LQ", { XM, Ev }, PREFIX_OPCODE },
3709     { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3710     { "cvtsi2sd%LQ", { XM, Ev }, 0 },
3711   },
3712
3713   /* PREFIX_0F2B */
3714   {
3715     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3716     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3717     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3718     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3719   },
3720
3721   /* PREFIX_0F2C */
3722   {
3723     { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3724     { "cvttss2si", { Gv, EXd }, PREFIX_OPCODE },
3725     { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3726     { "cvttsd2si", { Gv, EXq }, PREFIX_OPCODE },
3727   },
3728
3729   /* PREFIX_0F2D */
3730   {
3731     { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3732     { "cvtss2si", { Gv, EXd }, PREFIX_OPCODE },
3733     { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3734     { "cvtsd2si", { Gv, EXq }, PREFIX_OPCODE },
3735   },
3736
3737   /* PREFIX_0F2E */
3738   {
3739     { "ucomiss",{ XM, EXd }, 0 },
3740     { Bad_Opcode },
3741     { "ucomisd",{ XM, EXq }, 0 },
3742   },
3743
3744   /* PREFIX_0F2F */
3745   {
3746     { "comiss", { XM, EXd }, 0 },
3747     { Bad_Opcode },
3748     { "comisd", { XM, EXq }, 0 },
3749   },
3750
3751   /* PREFIX_0F51 */
3752   {
3753     { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3754     { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3755     { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3756     { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3757   },
3758
3759   /* PREFIX_0F52 */
3760   {
3761     { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3762     { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3763   },
3764
3765   /* PREFIX_0F53 */
3766   {
3767     { "rcpps",  { XM, EXx }, PREFIX_OPCODE },
3768     { "rcpss",  { XM, EXd }, PREFIX_OPCODE },
3769   },
3770
3771   /* PREFIX_0F58 */
3772   {
3773     { "addps", { XM, EXx }, PREFIX_OPCODE },
3774     { "addss", { XM, EXd }, PREFIX_OPCODE },
3775     { "addpd", { XM, EXx }, PREFIX_OPCODE },
3776     { "addsd", { XM, EXq }, PREFIX_OPCODE },
3777   },
3778
3779   /* PREFIX_0F59 */
3780   {
3781     { "mulps",  { XM, EXx }, PREFIX_OPCODE },
3782     { "mulss",  { XM, EXd }, PREFIX_OPCODE },
3783     { "mulpd",  { XM, EXx }, PREFIX_OPCODE },
3784     { "mulsd",  { XM, EXq }, PREFIX_OPCODE },
3785   },
3786
3787   /* PREFIX_0F5A */
3788   {
3789     { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3790     { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3791     { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3792     { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3793   },
3794
3795   /* PREFIX_0F5B */
3796   {
3797     { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3798     { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3799     { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3800   },
3801
3802   /* PREFIX_0F5C */
3803   {
3804     { "subps",  { XM, EXx }, PREFIX_OPCODE },
3805     { "subss",  { XM, EXd }, PREFIX_OPCODE },
3806     { "subpd",  { XM, EXx }, PREFIX_OPCODE },
3807     { "subsd",  { XM, EXq }, PREFIX_OPCODE },
3808   },
3809
3810   /* PREFIX_0F5D */
3811   {
3812     { "minps",  { XM, EXx }, PREFIX_OPCODE },
3813     { "minss",  { XM, EXd }, PREFIX_OPCODE },
3814     { "minpd",  { XM, EXx }, PREFIX_OPCODE },
3815     { "minsd",  { XM, EXq }, PREFIX_OPCODE },
3816   },
3817
3818   /* PREFIX_0F5E */
3819   {
3820     { "divps",  { XM, EXx }, PREFIX_OPCODE },
3821     { "divss",  { XM, EXd }, PREFIX_OPCODE },
3822     { "divpd",  { XM, EXx }, PREFIX_OPCODE },
3823     { "divsd",  { XM, EXq }, PREFIX_OPCODE },
3824   },
3825
3826   /* PREFIX_0F5F */
3827   {
3828     { "maxps",  { XM, EXx }, PREFIX_OPCODE },
3829     { "maxss",  { XM, EXd }, PREFIX_OPCODE },
3830     { "maxpd",  { XM, EXx }, PREFIX_OPCODE },
3831     { "maxsd",  { XM, EXq }, PREFIX_OPCODE },
3832   },
3833
3834   /* PREFIX_0F60 */
3835   {
3836     { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3837     { Bad_Opcode },
3838     { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3839   },
3840
3841   /* PREFIX_0F61 */
3842   {
3843     { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3844     { Bad_Opcode },
3845     { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3846   },
3847
3848   /* PREFIX_0F62 */
3849   {
3850     { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3851     { Bad_Opcode },
3852     { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3853   },
3854
3855   /* PREFIX_0F6C */
3856   {
3857     { Bad_Opcode },
3858     { Bad_Opcode },
3859     { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE },
3860   },
3861
3862   /* PREFIX_0F6D */
3863   {
3864     { Bad_Opcode },
3865     { Bad_Opcode },
3866     { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE },
3867   },
3868
3869   /* PREFIX_0F6F */
3870   {
3871     { "movq",   { MX, EM }, PREFIX_OPCODE },
3872     { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3873     { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3874   },
3875
3876   /* PREFIX_0F70 */
3877   {
3878     { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3879     { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3880     { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3881     { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3882   },
3883
3884   /* PREFIX_0F73_REG_3 */
3885   {
3886     { Bad_Opcode },
3887     { Bad_Opcode },
3888     { "psrldq", { XS, Ib }, 0 },
3889   },
3890
3891   /* PREFIX_0F73_REG_7 */
3892   {
3893     { Bad_Opcode },
3894     { Bad_Opcode },
3895     { "pslldq", { XS, Ib }, 0 },
3896   },
3897
3898   /* PREFIX_0F78 */
3899   {
3900     {"vmread",  { Em, Gm }, 0 },
3901     { Bad_Opcode },
3902     {"extrq",   { XS, Ib, Ib }, 0 },
3903     {"insertq", { XM, XS, Ib, Ib }, 0 },
3904   },
3905
3906   /* PREFIX_0F79 */
3907   {
3908     {"vmwrite", { Gm, Em }, 0 },
3909     { Bad_Opcode },
3910     {"extrq",   { XM, XS }, 0 },
3911     {"insertq", { XM, XS }, 0 },
3912   },
3913
3914   /* PREFIX_0F7C */
3915   {
3916     { Bad_Opcode },
3917     { Bad_Opcode },
3918     { "haddpd", { XM, EXx }, PREFIX_OPCODE },
3919     { "haddps", { XM, EXx }, PREFIX_OPCODE },
3920   },
3921
3922   /* PREFIX_0F7D */
3923   {
3924     { Bad_Opcode },
3925     { Bad_Opcode },
3926     { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
3927     { "hsubps", { XM, EXx }, PREFIX_OPCODE },
3928   },
3929
3930   /* PREFIX_0F7E */
3931   {
3932     { "movK",   { Edq, MX }, PREFIX_OPCODE },
3933     { "movq",   { XM, EXq }, PREFIX_OPCODE },
3934     { "movK",   { Edq, XM }, PREFIX_OPCODE },
3935   },
3936
3937   /* PREFIX_0F7F */
3938   {
3939     { "movq",   { EMS, MX }, PREFIX_OPCODE },
3940     { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
3941     { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
3942   },
3943
3944   /* PREFIX_0FAE_REG_0 */
3945   {
3946     { Bad_Opcode },
3947     { "rdfsbase", { Ev }, 0 },
3948   },
3949
3950   /* PREFIX_0FAE_REG_1 */
3951   {
3952     { Bad_Opcode },
3953     { "rdgsbase", { Ev }, 0 },
3954   },
3955
3956   /* PREFIX_0FAE_REG_2 */
3957   {
3958     { Bad_Opcode },
3959     { "wrfsbase", { Ev }, 0 },
3960   },
3961
3962   /* PREFIX_0FAE_REG_3 */
3963   {
3964     { Bad_Opcode },
3965     { "wrgsbase", { Ev }, 0 },
3966   },
3967
3968   /* PREFIX_MOD_0_0FAE_REG_4 */
3969   {
3970     { "xsave",  { FXSAVE }, 0 },
3971     { "ptwrite%LQ", { Edq }, 0 },
3972   },
3973
3974   /* PREFIX_MOD_3_0FAE_REG_4 */
3975   {
3976     { Bad_Opcode },
3977     { "ptwrite%LQ", { Edq }, 0 },
3978   },
3979
3980   /* PREFIX_MOD_0_0FAE_REG_5 */
3981   {
3982     { "xrstor",         { FXSAVE }, PREFIX_OPCODE },
3983   },
3984
3985   /* PREFIX_MOD_3_0FAE_REG_5 */
3986   {
3987     { "lfence",         { Skip_MODRM }, 0 },
3988     { "incsspK",        { Rdq }, PREFIX_OPCODE },
3989   },
3990
3991   /* PREFIX_MOD_0_0FAE_REG_6 */
3992   {
3993     { "xsaveopt",       { FXSAVE }, PREFIX_OPCODE },
3994     { "clrssbsy",       { Mq }, PREFIX_OPCODE },
3995     { "clwb",   { Mb }, PREFIX_OPCODE },
3996   },
3997
3998   /* PREFIX_MOD_1_0FAE_REG_6 */
3999   {
4000     { RM_TABLE (RM_0FAE_REG_6) },
4001     { "umonitor",       { Eva }, PREFIX_OPCODE },
4002     { "tpause", { Edq }, PREFIX_OPCODE },
4003     { "umwait", { Edq }, PREFIX_OPCODE },
4004   },
4005
4006   /* PREFIX_0FAE_REG_7 */
4007   {
4008     { "clflush",        { Mb }, 0 },
4009     { Bad_Opcode },
4010     { "clflushopt",     { Mb }, 0 },
4011   },
4012
4013   /* PREFIX_0FB8 */
4014   {
4015     { Bad_Opcode },
4016     { "popcntS", { Gv, Ev }, 0 },
4017   },
4018
4019   /* PREFIX_0FBC */
4020   {
4021     { "bsfS",   { Gv, Ev }, 0 },
4022     { "tzcntS", { Gv, Ev }, 0 },
4023     { "bsfS",   { Gv, Ev }, 0 },
4024   },
4025
4026   /* PREFIX_0FBD */
4027   {
4028     { "bsrS",   { Gv, Ev }, 0 },
4029     { "lzcntS", { Gv, Ev }, 0 },
4030     { "bsrS",   { Gv, Ev }, 0 },
4031   },
4032
4033   /* PREFIX_0FC2 */
4034   {
4035     { "cmpps",  { XM, EXx, CMP }, PREFIX_OPCODE },
4036     { "cmpss",  { XM, EXd, CMP }, PREFIX_OPCODE },
4037     { "cmppd",  { XM, EXx, CMP }, PREFIX_OPCODE },
4038     { "cmpsd",  { XM, EXq, CMP }, PREFIX_OPCODE },
4039   },
4040
4041   /* PREFIX_MOD_0_0FC3 */
4042   {
4043     { "movntiS", { Ev, Gv }, PREFIX_OPCODE },
4044   },
4045
4046   /* PREFIX_MOD_0_0FC7_REG_6 */
4047   {
4048     { "vmptrld",{ Mq }, 0 },
4049     { "vmxon",  { Mq }, 0 },
4050     { "vmclear",{ Mq }, 0 },
4051   },
4052
4053   /* PREFIX_MOD_3_0FC7_REG_6 */
4054   {
4055     { "rdrand", { Ev }, 0 },
4056     { Bad_Opcode },
4057     { "rdrand", { Ev }, 0 }
4058   },
4059
4060   /* PREFIX_MOD_3_0FC7_REG_7 */
4061   {
4062     { "rdseed", { Ev }, 0 },
4063     { "rdpid",  { Em }, 0 },
4064     { "rdseed", { Ev }, 0 },
4065   },
4066
4067   /* PREFIX_0FD0 */
4068   {
4069     { Bad_Opcode },
4070     { Bad_Opcode },
4071     { "addsubpd", { XM, EXx }, 0 },
4072     { "addsubps", { XM, EXx }, 0 },
4073   },
4074
4075   /* PREFIX_0FD6 */
4076   {
4077     { Bad_Opcode },
4078     { "movq2dq",{ XM, MS }, 0 },
4079     { "movq",   { EXqS, XM }, 0 },
4080     { "movdq2q",{ MX, XS }, 0 },
4081   },
4082
4083   /* PREFIX_0FE6 */
4084   {
4085     { Bad_Opcode },
4086     { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
4087     { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
4088     { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
4089   },
4090
4091   /* PREFIX_0FE7 */
4092   {
4093     { "movntq", { Mq, MX }, PREFIX_OPCODE },
4094     { Bad_Opcode },
4095     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
4096   },
4097
4098   /* PREFIX_0FF0 */
4099   {
4100     { Bad_Opcode },
4101     { Bad_Opcode },
4102     { Bad_Opcode },
4103     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4104   },
4105
4106   /* PREFIX_0FF7 */
4107   {
4108     { "maskmovq", { MX, MS }, PREFIX_OPCODE },
4109     { Bad_Opcode },
4110     { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
4111   },
4112
4113   /* PREFIX_0F3810 */
4114   {
4115     { Bad_Opcode },
4116     { Bad_Opcode },
4117     { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4118   },
4119
4120   /* PREFIX_0F3814 */
4121   {
4122     { Bad_Opcode },
4123     { Bad_Opcode },
4124     { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4125   },
4126
4127   /* PREFIX_0F3815 */
4128   {
4129     { Bad_Opcode },
4130     { Bad_Opcode },
4131     { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4132   },
4133
4134   /* PREFIX_0F3817 */
4135   {
4136     { Bad_Opcode },
4137     { Bad_Opcode },
4138     { "ptest",  { XM, EXx }, PREFIX_OPCODE },
4139   },
4140
4141   /* PREFIX_0F3820 */
4142   {
4143     { Bad_Opcode },
4144     { Bad_Opcode },
4145     { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE },
4146   },
4147
4148   /* PREFIX_0F3821 */
4149   {
4150     { Bad_Opcode },
4151     { Bad_Opcode },
4152     { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE },
4153   },
4154
4155   /* PREFIX_0F3822 */
4156   {
4157     { Bad_Opcode },
4158     { Bad_Opcode },
4159     { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE },
4160   },
4161
4162   /* PREFIX_0F3823 */
4163   {
4164     { Bad_Opcode },
4165     { Bad_Opcode },
4166     { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE },
4167   },
4168
4169   /* PREFIX_0F3824 */
4170   {
4171     { Bad_Opcode },
4172     { Bad_Opcode },
4173     { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE },
4174   },
4175
4176   /* PREFIX_0F3825 */
4177   {
4178     { Bad_Opcode },
4179     { Bad_Opcode },
4180     { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE },
4181   },
4182
4183   /* PREFIX_0F3828 */
4184   {
4185     { Bad_Opcode },
4186     { Bad_Opcode },
4187     { "pmuldq", { XM, EXx }, PREFIX_OPCODE },
4188   },
4189
4190   /* PREFIX_0F3829 */
4191   {
4192     { Bad_Opcode },
4193     { Bad_Opcode },
4194     { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE },
4195   },
4196
4197   /* PREFIX_0F382A */
4198   {
4199     { Bad_Opcode },
4200     { Bad_Opcode },
4201     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4202   },
4203
4204   /* PREFIX_0F382B */
4205   {
4206     { Bad_Opcode },
4207     { Bad_Opcode },
4208     { "packusdw", { XM, EXx }, PREFIX_OPCODE },
4209   },
4210
4211   /* PREFIX_0F3830 */
4212   {
4213     { Bad_Opcode },
4214     { Bad_Opcode },
4215     { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE },
4216   },
4217
4218   /* PREFIX_0F3831 */
4219   {
4220     { Bad_Opcode },
4221     { Bad_Opcode },
4222     { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE },
4223   },
4224
4225   /* PREFIX_0F3832 */
4226   {
4227     { Bad_Opcode },
4228     { Bad_Opcode },
4229     { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE },
4230   },
4231
4232   /* PREFIX_0F3833 */
4233   {
4234     { Bad_Opcode },
4235     { Bad_Opcode },
4236     { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE },
4237   },
4238
4239   /* PREFIX_0F3834 */
4240   {
4241     { Bad_Opcode },
4242     { Bad_Opcode },
4243     { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE },
4244   },
4245
4246   /* PREFIX_0F3835 */
4247   {
4248     { Bad_Opcode },
4249     { Bad_Opcode },
4250     { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE },
4251   },
4252
4253   /* PREFIX_0F3837 */
4254   {
4255     { Bad_Opcode },
4256     { Bad_Opcode },
4257     { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE },
4258   },
4259
4260   /* PREFIX_0F3838 */
4261   {
4262     { Bad_Opcode },
4263     { Bad_Opcode },
4264     { "pminsb", { XM, EXx }, PREFIX_OPCODE },
4265   },
4266
4267   /* PREFIX_0F3839 */
4268   {
4269     { Bad_Opcode },
4270     { Bad_Opcode },
4271     { "pminsd", { XM, EXx }, PREFIX_OPCODE },
4272   },
4273
4274   /* PREFIX_0F383A */
4275   {
4276     { Bad_Opcode },
4277     { Bad_Opcode },
4278     { "pminuw", { XM, EXx }, PREFIX_OPCODE },
4279   },
4280
4281   /* PREFIX_0F383B */
4282   {
4283     { Bad_Opcode },
4284     { Bad_Opcode },
4285     { "pminud", { XM, EXx }, PREFIX_OPCODE },
4286   },
4287
4288   /* PREFIX_0F383C */
4289   {
4290     { Bad_Opcode },
4291     { Bad_Opcode },
4292     { "pmaxsb", { XM, EXx }, PREFIX_OPCODE },
4293   },
4294
4295   /* PREFIX_0F383D */
4296   {
4297     { Bad_Opcode },
4298     { Bad_Opcode },
4299     { "pmaxsd", { XM, EXx }, PREFIX_OPCODE },
4300   },
4301
4302   /* PREFIX_0F383E */
4303   {
4304     { Bad_Opcode },
4305     { Bad_Opcode },
4306     { "pmaxuw", { XM, EXx }, PREFIX_OPCODE },
4307   },
4308
4309   /* PREFIX_0F383F */
4310   {
4311     { Bad_Opcode },
4312     { Bad_Opcode },
4313     { "pmaxud", { XM, EXx }, PREFIX_OPCODE },
4314   },
4315
4316   /* PREFIX_0F3840 */
4317   {
4318     { Bad_Opcode },
4319     { Bad_Opcode },
4320     { "pmulld", { XM, EXx }, PREFIX_OPCODE },
4321   },
4322
4323   /* PREFIX_0F3841 */
4324   {
4325     { Bad_Opcode },
4326     { Bad_Opcode },
4327     { "phminposuw", { XM, EXx }, PREFIX_OPCODE },
4328   },
4329
4330   /* PREFIX_0F3880 */
4331   {
4332     { Bad_Opcode },
4333     { Bad_Opcode },
4334     { "invept", { Gm, Mo }, PREFIX_OPCODE },
4335   },
4336
4337   /* PREFIX_0F3881 */
4338   {
4339     { Bad_Opcode },
4340     { Bad_Opcode },
4341     { "invvpid", { Gm, Mo }, PREFIX_OPCODE },
4342   },
4343
4344   /* PREFIX_0F3882 */
4345   {
4346     { Bad_Opcode },
4347     { Bad_Opcode },
4348     { "invpcid", { Gm, M }, PREFIX_OPCODE },
4349   },
4350
4351   /* PREFIX_0F38C8 */
4352   {
4353     { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4354   },
4355
4356   /* PREFIX_0F38C9 */
4357   {
4358     { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4359   },
4360
4361   /* PREFIX_0F38CA */
4362   {
4363     { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4364   },
4365
4366   /* PREFIX_0F38CB */
4367   {
4368     { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4369   },
4370
4371   /* PREFIX_0F38CC */
4372   {
4373     { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4374   },
4375
4376   /* PREFIX_0F38CD */
4377   {
4378     { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4379   },
4380
4381   /* PREFIX_0F38CF */
4382   {
4383     { Bad_Opcode },
4384     { Bad_Opcode },
4385     { "gf2p8mulb", { XM, EXxmm }, PREFIX_OPCODE },
4386   },
4387
4388   /* PREFIX_0F38DB */
4389   {
4390     { Bad_Opcode },
4391     { Bad_Opcode },
4392     { "aesimc", { XM, EXx }, PREFIX_OPCODE },
4393   },
4394
4395   /* PREFIX_0F38DC */
4396   {
4397     { Bad_Opcode },
4398     { Bad_Opcode },
4399     { "aesenc", { XM, EXx }, PREFIX_OPCODE },
4400   },
4401
4402   /* PREFIX_0F38DD */
4403   {
4404     { Bad_Opcode },
4405     { Bad_Opcode },
4406     { "aesenclast", { XM, EXx }, PREFIX_OPCODE },
4407   },
4408
4409   /* PREFIX_0F38DE */
4410   {
4411     { Bad_Opcode },
4412     { Bad_Opcode },
4413     { "aesdec", { XM, EXx }, PREFIX_OPCODE },
4414   },
4415
4416   /* PREFIX_0F38DF */
4417   {
4418     { Bad_Opcode },
4419     { Bad_Opcode },
4420     { "aesdeclast", { XM, EXx }, PREFIX_OPCODE },
4421   },
4422
4423   /* PREFIX_0F38F0 */
4424   {
4425     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4426     { Bad_Opcode },
4427     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4428     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE },
4429   },
4430
4431   /* PREFIX_0F38F1 */
4432   {
4433     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4434     { Bad_Opcode },
4435     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4436     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE },
4437   },
4438
4439   /* PREFIX_0F38F5 */
4440   {
4441     { Bad_Opcode },
4442     { Bad_Opcode },
4443     { MOD_TABLE (MOD_0F38F5_PREFIX_2) },
4444   },
4445
4446   /* PREFIX_0F38F6 */
4447   {
4448     { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
4449     { "adoxS",  { Gdq, Edq}, PREFIX_OPCODE },
4450     { "adcxS",  { Gdq, Edq}, PREFIX_OPCODE },
4451     { Bad_Opcode },
4452   },
4453
4454   /* PREFIX_0F38F8 */
4455   {
4456     { Bad_Opcode },
4457     { Bad_Opcode },
4458     { MOD_TABLE (MOD_0F38F8_PREFIX_2) },
4459   },
4460
4461   /* PREFIX_0F38F9 */
4462   {
4463     { MOD_TABLE (MOD_0F38F9_PREFIX_0) },
4464   },
4465
4466   /* PREFIX_0F3A08 */
4467   {
4468     { Bad_Opcode },
4469     { Bad_Opcode },
4470     { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE },
4471   },
4472
4473   /* PREFIX_0F3A09 */
4474   {
4475     { Bad_Opcode },
4476     { Bad_Opcode },
4477     { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4478   },
4479
4480   /* PREFIX_0F3A0A */
4481   {
4482     { Bad_Opcode },
4483     { Bad_Opcode },
4484     { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE },
4485   },
4486
4487   /* PREFIX_0F3A0B */
4488   {
4489     { Bad_Opcode },
4490     { Bad_Opcode },
4491     { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE },
4492   },
4493
4494   /* PREFIX_0F3A0C */
4495   {
4496     { Bad_Opcode },
4497     { Bad_Opcode },
4498     { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE },
4499   },
4500
4501   /* PREFIX_0F3A0D */
4502   {
4503     { Bad_Opcode },
4504     { Bad_Opcode },
4505     { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4506   },
4507
4508   /* PREFIX_0F3A0E */
4509   {
4510     { Bad_Opcode },
4511     { Bad_Opcode },
4512     { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE },
4513   },
4514
4515   /* PREFIX_0F3A14 */
4516   {
4517     { Bad_Opcode },
4518     { Bad_Opcode },
4519     { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE },
4520   },
4521
4522   /* PREFIX_0F3A15 */
4523   {
4524     { Bad_Opcode },
4525     { Bad_Opcode },
4526     { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE },
4527   },
4528
4529   /* PREFIX_0F3A16 */
4530   {
4531     { Bad_Opcode },
4532     { Bad_Opcode },
4533     { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE },
4534   },
4535
4536   /* PREFIX_0F3A17 */
4537   {
4538     { Bad_Opcode },
4539     { Bad_Opcode },
4540     { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE },
4541   },
4542
4543   /* PREFIX_0F3A20 */
4544   {
4545     { Bad_Opcode },
4546     { Bad_Opcode },
4547     { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE },
4548   },
4549
4550   /* PREFIX_0F3A21 */
4551   {
4552     { Bad_Opcode },
4553     { Bad_Opcode },
4554     { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE },
4555   },
4556
4557   /* PREFIX_0F3A22 */
4558   {
4559     { Bad_Opcode },
4560     { Bad_Opcode },
4561     { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE },
4562   },
4563
4564   /* PREFIX_0F3A40 */
4565   {
4566     { Bad_Opcode },
4567     { Bad_Opcode },
4568     { "dpps",   { XM, EXx, Ib }, PREFIX_OPCODE },
4569   },
4570
4571   /* PREFIX_0F3A41 */
4572   {
4573     { Bad_Opcode },
4574     { Bad_Opcode },
4575     { "dppd",   { XM, EXx, Ib }, PREFIX_OPCODE },
4576   },
4577
4578   /* PREFIX_0F3A42 */
4579   {
4580     { Bad_Opcode },
4581     { Bad_Opcode },
4582     { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE },
4583   },
4584
4585   /* PREFIX_0F3A44 */
4586   {
4587     { Bad_Opcode },
4588     { Bad_Opcode },
4589     { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE },
4590   },
4591
4592   /* PREFIX_0F3A60 */
4593   {
4594     { Bad_Opcode },
4595     { Bad_Opcode },
4596     { "pcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4597   },
4598
4599   /* PREFIX_0F3A61 */
4600   {
4601     { Bad_Opcode },
4602     { Bad_Opcode },
4603     { "pcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4604   },
4605
4606   /* PREFIX_0F3A62 */
4607   {
4608     { Bad_Opcode },
4609     { Bad_Opcode },
4610     { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4611   },
4612
4613   /* PREFIX_0F3A63 */
4614   {
4615     { Bad_Opcode },
4616     { Bad_Opcode },
4617     { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE },
4618   },
4619
4620   /* PREFIX_0F3ACC */
4621   {
4622     { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4623   },
4624
4625   /* PREFIX_0F3ACE */
4626   {
4627     { Bad_Opcode },
4628     { Bad_Opcode },
4629     { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4630   },
4631
4632   /* PREFIX_0F3ACF */
4633   {
4634     { Bad_Opcode },
4635     { Bad_Opcode },
4636     { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4637   },
4638
4639   /* PREFIX_0F3ADF */
4640   {
4641     { Bad_Opcode },
4642     { Bad_Opcode },
4643     { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE },
4644   },
4645
4646   /* PREFIX_VEX_0F10 */
4647   {
4648     { "vmovups",        { XM, EXx }, 0 },
4649     { "vmovss",         { XMVexScalar, VexScalar, EXdScalar }, 0 },
4650     { "vmovupd",        { XM, EXx }, 0 },
4651     { "vmovsd",         { XMVexScalar, VexScalar, EXqScalar }, 0 },
4652   },
4653
4654   /* PREFIX_VEX_0F11 */
4655   {
4656     { "vmovups",        { EXxS, XM }, 0 },
4657     { "vmovss",         { EXdVexScalarS, VexScalar, XMScalar }, 0 },
4658     { "vmovupd",        { EXxS, XM }, 0 },
4659     { "vmovsd",         { EXqVexScalarS, VexScalar, XMScalar }, 0 },
4660   },
4661
4662   /* PREFIX_VEX_0F12 */
4663   {
4664     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4665     { "vmovsldup",      { XM, EXx }, 0 },
4666     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
4667     { "vmovddup",       { XM, EXymmq }, 0 },
4668   },
4669
4670   /* PREFIX_VEX_0F16 */
4671   {
4672     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4673     { "vmovshdup",      { XM, EXx }, 0 },
4674     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
4675   },
4676
4677   /* PREFIX_VEX_0F2A */
4678   {
4679     { Bad_Opcode },
4680     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) },
4681     { Bad_Opcode },
4682     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) },
4683   },
4684
4685   /* PREFIX_VEX_0F2C */
4686   {
4687     { Bad_Opcode },
4688     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) },
4689     { Bad_Opcode },
4690     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) },
4691   },
4692
4693   /* PREFIX_VEX_0F2D */
4694   {
4695     { Bad_Opcode },
4696     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) },
4697     { Bad_Opcode },
4698     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) },
4699   },
4700
4701   /* PREFIX_VEX_0F2E */
4702   {
4703     { "vucomiss",       { XMScalar, EXdScalar }, 0 },
4704     { Bad_Opcode },
4705     { "vucomisd",       { XMScalar, EXqScalar }, 0 },
4706   },
4707
4708   /* PREFIX_VEX_0F2F */
4709   {
4710     { "vcomiss",        { XMScalar, EXdScalar }, 0 },
4711     { Bad_Opcode },
4712     { "vcomisd",        { XMScalar, EXqScalar }, 0 },
4713   },
4714
4715   /* PREFIX_VEX_0F41 */
4716   {
4717     { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4718     { Bad_Opcode },
4719     { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4720   },
4721
4722   /* PREFIX_VEX_0F42 */
4723   {
4724     { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4725     { Bad_Opcode },
4726     { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4727   },
4728
4729   /* PREFIX_VEX_0F44 */
4730   {
4731     { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4732     { Bad_Opcode },
4733     { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4734   },
4735
4736   /* PREFIX_VEX_0F45 */
4737   {
4738     { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4739     { Bad_Opcode },
4740     { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4741   },
4742
4743   /* PREFIX_VEX_0F46 */
4744   {
4745     { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4746     { Bad_Opcode },
4747     { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4748   },
4749
4750   /* PREFIX_VEX_0F47 */
4751   {
4752     { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4753     { Bad_Opcode },
4754     { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
4755   },
4756
4757   /* PREFIX_VEX_0F4A */
4758   {
4759     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
4760     { Bad_Opcode },
4761     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
4762   },
4763
4764   /* PREFIX_VEX_0F4B */
4765   {
4766     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
4767     { Bad_Opcode },
4768     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4769   },
4770
4771   /* PREFIX_VEX_0F51 */
4772   {
4773     { "vsqrtps",        { XM, EXx }, 0 },
4774     { "vsqrtss",        { XMScalar, VexScalar, EXdScalar }, 0 },
4775     { "vsqrtpd",        { XM, EXx }, 0 },
4776     { "vsqrtsd",        { XMScalar, VexScalar, EXqScalar }, 0 },
4777   },
4778
4779   /* PREFIX_VEX_0F52 */
4780   {
4781     { "vrsqrtps",       { XM, EXx }, 0 },
4782     { "vrsqrtss",       { XMScalar, VexScalar, EXdScalar }, 0 },
4783   },
4784
4785   /* PREFIX_VEX_0F53 */
4786   {
4787     { "vrcpps",         { XM, EXx }, 0 },
4788     { "vrcpss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4789   },
4790
4791   /* PREFIX_VEX_0F58 */
4792   {
4793     { "vaddps",         { XM, Vex, EXx }, 0 },
4794     { "vaddss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4795     { "vaddpd",         { XM, Vex, EXx }, 0 },
4796     { "vaddsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4797   },
4798
4799   /* PREFIX_VEX_0F59 */
4800   {
4801     { "vmulps",         { XM, Vex, EXx }, 0 },
4802     { "vmulss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4803     { "vmulpd",         { XM, Vex, EXx }, 0 },
4804     { "vmulsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4805   },
4806
4807   /* PREFIX_VEX_0F5A */
4808   {
4809     { "vcvtps2pd",      { XM, EXxmmq }, 0 },
4810     { "vcvtss2sd",      { XMScalar, VexScalar, EXdScalar }, 0 },
4811     { "vcvtpd2ps%XY",{ XMM, EXx }, 0 },
4812     { "vcvtsd2ss",      { XMScalar, VexScalar, EXqScalar }, 0 },
4813   },
4814
4815   /* PREFIX_VEX_0F5B */
4816   {
4817     { "vcvtdq2ps",      { XM, EXx }, 0 },
4818     { "vcvttps2dq",     { XM, EXx }, 0 },
4819     { "vcvtps2dq",      { XM, EXx }, 0 },
4820   },
4821
4822   /* PREFIX_VEX_0F5C */
4823   {
4824     { "vsubps",         { XM, Vex, EXx }, 0 },
4825     { "vsubss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4826     { "vsubpd",         { XM, Vex, EXx }, 0 },
4827     { "vsubsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4828   },
4829
4830   /* PREFIX_VEX_0F5D */
4831   {
4832     { "vminps",         { XM, Vex, EXx }, 0 },
4833     { "vminss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4834     { "vminpd",         { XM, Vex, EXx }, 0 },
4835     { "vminsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4836   },
4837
4838   /* PREFIX_VEX_0F5E */
4839   {
4840     { "vdivps",         { XM, Vex, EXx }, 0 },
4841     { "vdivss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4842     { "vdivpd",         { XM, Vex, EXx }, 0 },
4843     { "vdivsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4844   },
4845
4846   /* PREFIX_VEX_0F5F */
4847   {
4848     { "vmaxps",         { XM, Vex, EXx }, 0 },
4849     { "vmaxss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4850     { "vmaxpd",         { XM, Vex, EXx }, 0 },
4851     { "vmaxsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4852   },
4853
4854   /* PREFIX_VEX_0F60 */
4855   {
4856     { Bad_Opcode },
4857     { Bad_Opcode },
4858     { "vpunpcklbw",     { XM, Vex, EXx }, 0 },
4859   },
4860
4861   /* PREFIX_VEX_0F61 */
4862   {
4863     { Bad_Opcode },
4864     { Bad_Opcode },
4865     { "vpunpcklwd",     { XM, Vex, EXx }, 0 },
4866   },
4867
4868   /* PREFIX_VEX_0F62 */
4869   {
4870     { Bad_Opcode },
4871     { Bad_Opcode },
4872     { "vpunpckldq",     { XM, Vex, EXx }, 0 },
4873   },
4874
4875   /* PREFIX_VEX_0F63 */
4876   {
4877     { Bad_Opcode },
4878     { Bad_Opcode },
4879     { "vpacksswb",      { XM, Vex, EXx }, 0 },
4880   },
4881
4882   /* PREFIX_VEX_0F64 */
4883   {
4884     { Bad_Opcode },
4885     { Bad_Opcode },
4886     { "vpcmpgtb",       { XM, Vex, EXx }, 0 },
4887   },
4888
4889   /* PREFIX_VEX_0F65 */
4890   {
4891     { Bad_Opcode },
4892     { Bad_Opcode },
4893     { "vpcmpgtw",       { XM, Vex, EXx }, 0 },
4894   },
4895
4896   /* PREFIX_VEX_0F66 */
4897   {
4898     { Bad_Opcode },
4899     { Bad_Opcode },
4900     { "vpcmpgtd",       { XM, Vex, EXx }, 0 },
4901   },
4902
4903   /* PREFIX_VEX_0F67 */
4904   {
4905     { Bad_Opcode },
4906     { Bad_Opcode },
4907     { "vpackuswb",      { XM, Vex, EXx }, 0 },
4908   },
4909
4910   /* PREFIX_VEX_0F68 */
4911   {
4912     { Bad_Opcode },
4913     { Bad_Opcode },
4914     { "vpunpckhbw",     { XM, Vex, EXx }, 0 },
4915   },
4916
4917   /* PREFIX_VEX_0F69 */
4918   {
4919     { Bad_Opcode },
4920     { Bad_Opcode },
4921     { "vpunpckhwd",     { XM, Vex, EXx }, 0 },
4922   },
4923
4924   /* PREFIX_VEX_0F6A */
4925   {
4926     { Bad_Opcode },
4927     { Bad_Opcode },
4928     { "vpunpckhdq",     { XM, Vex, EXx }, 0 },
4929   },
4930
4931   /* PREFIX_VEX_0F6B */
4932   {
4933     { Bad_Opcode },
4934     { Bad_Opcode },
4935     { "vpackssdw",      { XM, Vex, EXx }, 0 },
4936   },
4937
4938   /* PREFIX_VEX_0F6C */
4939   {
4940     { Bad_Opcode },
4941     { Bad_Opcode },
4942     { "vpunpcklqdq",    { XM, Vex, EXx }, 0 },
4943   },
4944
4945   /* PREFIX_VEX_0F6D */
4946   {
4947     { Bad_Opcode },
4948     { Bad_Opcode },
4949     { "vpunpckhqdq",    { XM, Vex, EXx }, 0 },
4950   },
4951
4952   /* PREFIX_VEX_0F6E */
4953   {
4954     { Bad_Opcode },
4955     { Bad_Opcode },
4956     { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
4957   },
4958
4959   /* PREFIX_VEX_0F6F */
4960   {
4961     { Bad_Opcode },
4962     { "vmovdqu",        { XM, EXx }, 0 },
4963     { "vmovdqa",        { XM, EXx }, 0 },
4964   },
4965
4966   /* PREFIX_VEX_0F70 */
4967   {
4968     { Bad_Opcode },
4969     { "vpshufhw",       { XM, EXx, Ib }, 0 },
4970     { "vpshufd",        { XM, EXx, Ib }, 0 },
4971     { "vpshuflw",       { XM, EXx, Ib }, 0 },
4972   },
4973
4974   /* PREFIX_VEX_0F71_REG_2 */
4975   {
4976     { Bad_Opcode },
4977     { Bad_Opcode },
4978     { "vpsrlw",         { Vex, XS, Ib }, 0 },
4979   },
4980
4981   /* PREFIX_VEX_0F71_REG_4 */
4982   {
4983     { Bad_Opcode },
4984     { Bad_Opcode },
4985     { "vpsraw",         { Vex, XS, Ib }, 0 },
4986   },
4987
4988   /* PREFIX_VEX_0F71_REG_6 */
4989   {
4990     { Bad_Opcode },
4991     { Bad_Opcode },
4992     { "vpsllw",         { Vex, XS, Ib }, 0 },
4993   },
4994
4995   /* PREFIX_VEX_0F72_REG_2 */
4996   {
4997     { Bad_Opcode },
4998     { Bad_Opcode },
4999     { "vpsrld",         { Vex, XS, Ib }, 0 },
5000   },
5001
5002   /* PREFIX_VEX_0F72_REG_4 */
5003   {
5004     { Bad_Opcode },
5005     { Bad_Opcode },
5006     { "vpsrad",         { Vex, XS, Ib }, 0 },
5007   },
5008
5009   /* PREFIX_VEX_0F72_REG_6 */
5010   {
5011     { Bad_Opcode },
5012     { Bad_Opcode },
5013     { "vpslld",         { Vex, XS, Ib }, 0 },
5014   },
5015
5016   /* PREFIX_VEX_0F73_REG_2 */
5017   {
5018     { Bad_Opcode },
5019     { Bad_Opcode },
5020     { "vpsrlq",         { Vex, XS, Ib }, 0 },
5021   },
5022
5023   /* PREFIX_VEX_0F73_REG_3 */
5024   {
5025     { Bad_Opcode },
5026     { Bad_Opcode },
5027     { "vpsrldq",        { Vex, XS, Ib }, 0 },
5028   },
5029
5030   /* PREFIX_VEX_0F73_REG_6 */
5031   {
5032     { Bad_Opcode },
5033     { Bad_Opcode },
5034     { "vpsllq",         { Vex, XS, Ib }, 0 },
5035   },
5036
5037   /* PREFIX_VEX_0F73_REG_7 */
5038   {
5039     { Bad_Opcode },
5040     { Bad_Opcode },
5041     { "vpslldq",        { Vex, XS, Ib }, 0 },
5042   },
5043
5044   /* PREFIX_VEX_0F74 */
5045   {
5046     { Bad_Opcode },
5047     { Bad_Opcode },
5048     { "vpcmpeqb",       { XM, Vex, EXx }, 0 },
5049   },
5050
5051   /* PREFIX_VEX_0F75 */
5052   {
5053     { Bad_Opcode },
5054     { Bad_Opcode },
5055     { "vpcmpeqw",       { XM, Vex, EXx }, 0 },
5056   },
5057
5058   /* PREFIX_VEX_0F76 */
5059   {
5060     { Bad_Opcode },
5061     { Bad_Opcode },
5062     { "vpcmpeqd",       { XM, Vex, EXx }, 0 },
5063   },
5064
5065   /* PREFIX_VEX_0F77 */
5066   {
5067     { VEX_LEN_TABLE (VEX_LEN_0F77_P_0) },
5068   },
5069
5070   /* PREFIX_VEX_0F7C */
5071   {
5072     { Bad_Opcode },
5073     { Bad_Opcode },
5074     { "vhaddpd",        { XM, Vex, EXx }, 0 },
5075     { "vhaddps",        { XM, Vex, EXx }, 0 },
5076   },
5077
5078   /* PREFIX_VEX_0F7D */
5079   {
5080     { Bad_Opcode },
5081     { Bad_Opcode },
5082     { "vhsubpd",        { XM, Vex, EXx }, 0 },
5083     { "vhsubps",        { XM, Vex, EXx }, 0 },
5084   },
5085
5086   /* PREFIX_VEX_0F7E */
5087   {
5088     { Bad_Opcode },
5089     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
5090     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
5091   },
5092
5093   /* PREFIX_VEX_0F7F */
5094   {
5095     { Bad_Opcode },
5096     { "vmovdqu",        { EXxS, XM }, 0 },
5097     { "vmovdqa",        { EXxS, XM }, 0 },
5098   },
5099
5100   /* PREFIX_VEX_0F90 */
5101   {
5102     { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
5103     { Bad_Opcode },
5104     { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
5105   },
5106
5107   /* PREFIX_VEX_0F91 */
5108   {
5109     { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
5110     { Bad_Opcode },
5111     { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
5112   },
5113
5114   /* PREFIX_VEX_0F92 */
5115   {
5116     { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
5117     { Bad_Opcode },
5118     { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
5119     { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
5120   },
5121
5122   /* PREFIX_VEX_0F93 */
5123   {
5124     { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
5125     { Bad_Opcode },
5126     { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
5127     { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
5128   },
5129
5130   /* PREFIX_VEX_0F98 */
5131   {
5132     { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
5133     { Bad_Opcode },
5134     { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
5135   },
5136
5137   /* PREFIX_VEX_0F99 */
5138   {
5139     { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5140     { Bad_Opcode },
5141     { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5142   },
5143
5144   /* PREFIX_VEX_0FC2 */
5145   {
5146     { "vcmpps",         { XM, Vex, EXx, VCMP }, 0 },
5147     { "vcmpss",         { XMScalar, VexScalar, EXdScalar, VCMP }, 0 },
5148     { "vcmppd",         { XM, Vex, EXx, VCMP }, 0 },
5149     { "vcmpsd",         { XMScalar, VexScalar, EXqScalar, VCMP }, 0 },
5150   },
5151
5152   /* PREFIX_VEX_0FC4 */
5153   {
5154     { Bad_Opcode },
5155     { Bad_Opcode },
5156     { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5157   },
5158
5159   /* PREFIX_VEX_0FC5 */
5160   {
5161     { Bad_Opcode },
5162     { Bad_Opcode },
5163     { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5164   },
5165
5166   /* PREFIX_VEX_0FD0 */
5167   {
5168     { Bad_Opcode },
5169     { Bad_Opcode },
5170     { "vaddsubpd",      { XM, Vex, EXx }, 0 },
5171     { "vaddsubps",      { XM, Vex, EXx }, 0 },
5172   },
5173
5174   /* PREFIX_VEX_0FD1 */
5175   {
5176     { Bad_Opcode },
5177     { Bad_Opcode },
5178     { "vpsrlw",         { XM, Vex, EXxmm }, 0 },
5179   },
5180
5181   /* PREFIX_VEX_0FD2 */
5182   {
5183     { Bad_Opcode },
5184     { Bad_Opcode },
5185     { "vpsrld",         { XM, Vex, EXxmm }, 0 },
5186   },
5187
5188   /* PREFIX_VEX_0FD3 */
5189   {
5190     { Bad_Opcode },
5191     { Bad_Opcode },
5192     { "vpsrlq",         { XM, Vex, EXxmm }, 0 },
5193   },
5194
5195   /* PREFIX_VEX_0FD4 */
5196   {
5197     { Bad_Opcode },
5198     { Bad_Opcode },
5199     { "vpaddq",         { XM, Vex, EXx }, 0 },
5200   },
5201
5202   /* PREFIX_VEX_0FD5 */
5203   {
5204     { Bad_Opcode },
5205     { Bad_Opcode },
5206     { "vpmullw",        { XM, Vex, EXx }, 0 },
5207   },
5208
5209   /* PREFIX_VEX_0FD6 */
5210   {
5211     { Bad_Opcode },
5212     { Bad_Opcode },
5213     { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5214   },
5215
5216   /* PREFIX_VEX_0FD7 */
5217   {
5218     { Bad_Opcode },
5219     { Bad_Opcode },
5220     { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5221   },
5222
5223   /* PREFIX_VEX_0FD8 */
5224   {
5225     { Bad_Opcode },
5226     { Bad_Opcode },
5227     { "vpsubusb",       { XM, Vex, EXx }, 0 },
5228   },
5229
5230   /* PREFIX_VEX_0FD9 */
5231   {
5232     { Bad_Opcode },
5233     { Bad_Opcode },
5234     { "vpsubusw",       { XM, Vex, EXx }, 0 },
5235   },
5236
5237   /* PREFIX_VEX_0FDA */
5238   {
5239     { Bad_Opcode },
5240     { Bad_Opcode },
5241     { "vpminub",        { XM, Vex, EXx }, 0 },
5242   },
5243
5244   /* PREFIX_VEX_0FDB */
5245   {
5246     { Bad_Opcode },
5247     { Bad_Opcode },
5248     { "vpand",          { XM, Vex, EXx }, 0 },
5249   },
5250
5251   /* PREFIX_VEX_0FDC */
5252   {
5253     { Bad_Opcode },
5254     { Bad_Opcode },
5255     { "vpaddusb",       { XM, Vex, EXx }, 0 },
5256   },
5257
5258   /* PREFIX_VEX_0FDD */
5259   {
5260     { Bad_Opcode },
5261     { Bad_Opcode },
5262     { "vpaddusw",       { XM, Vex, EXx }, 0 },
5263   },
5264
5265   /* PREFIX_VEX_0FDE */
5266   {
5267     { Bad_Opcode },
5268     { Bad_Opcode },
5269     { "vpmaxub",        { XM, Vex, EXx }, 0 },
5270   },
5271
5272   /* PREFIX_VEX_0FDF */
5273   {
5274     { Bad_Opcode },
5275     { Bad_Opcode },
5276     { "vpandn",         { XM, Vex, EXx }, 0 },
5277   },
5278
5279   /* PREFIX_VEX_0FE0 */
5280   {
5281     { Bad_Opcode },
5282     { Bad_Opcode },
5283     { "vpavgb",         { XM, Vex, EXx }, 0 },
5284   },
5285
5286   /* PREFIX_VEX_0FE1 */
5287   {
5288     { Bad_Opcode },
5289     { Bad_Opcode },
5290     { "vpsraw",         { XM, Vex, EXxmm }, 0 },
5291   },
5292
5293   /* PREFIX_VEX_0FE2 */
5294   {
5295     { Bad_Opcode },
5296     { Bad_Opcode },
5297     { "vpsrad",         { XM, Vex, EXxmm }, 0 },
5298   },
5299
5300   /* PREFIX_VEX_0FE3 */
5301   {
5302     { Bad_Opcode },
5303     { Bad_Opcode },
5304     { "vpavgw",         { XM, Vex, EXx }, 0 },
5305   },
5306
5307   /* PREFIX_VEX_0FE4 */
5308   {
5309     { Bad_Opcode },
5310     { Bad_Opcode },
5311     { "vpmulhuw",       { XM, Vex, EXx }, 0 },
5312   },
5313
5314   /* PREFIX_VEX_0FE5 */
5315   {
5316     { Bad_Opcode },
5317     { Bad_Opcode },
5318     { "vpmulhw",        { XM, Vex, EXx }, 0 },
5319   },
5320
5321   /* PREFIX_VEX_0FE6 */
5322   {
5323     { Bad_Opcode },
5324     { "vcvtdq2pd",      { XM, EXxmmq }, 0 },
5325     { "vcvttpd2dq%XY",  { XMM, EXx }, 0 },
5326     { "vcvtpd2dq%XY",   { XMM, EXx }, 0 },
5327   },
5328
5329   /* PREFIX_VEX_0FE7 */
5330   {
5331     { Bad_Opcode },
5332     { Bad_Opcode },
5333     { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5334   },
5335
5336   /* PREFIX_VEX_0FE8 */
5337   {
5338     { Bad_Opcode },
5339     { Bad_Opcode },
5340     { "vpsubsb",        { XM, Vex, EXx }, 0 },
5341   },
5342
5343   /* PREFIX_VEX_0FE9 */
5344   {
5345     { Bad_Opcode },
5346     { Bad_Opcode },
5347     { "vpsubsw",        { XM, Vex, EXx }, 0 },
5348   },
5349
5350   /* PREFIX_VEX_0FEA */
5351   {
5352     { Bad_Opcode },
5353     { Bad_Opcode },
5354     { "vpminsw",        { XM, Vex, EXx }, 0 },
5355   },
5356
5357   /* PREFIX_VEX_0FEB */
5358   {
5359     { Bad_Opcode },
5360     { Bad_Opcode },
5361     { "vpor",           { XM, Vex, EXx }, 0 },
5362   },
5363
5364   /* PREFIX_VEX_0FEC */
5365   {
5366     { Bad_Opcode },
5367     { Bad_Opcode },
5368     { "vpaddsb",        { XM, Vex, EXx }, 0 },
5369   },
5370
5371   /* PREFIX_VEX_0FED */
5372   {
5373     { Bad_Opcode },
5374     { Bad_Opcode },
5375     { "vpaddsw",        { XM, Vex, EXx }, 0 },
5376   },
5377
5378   /* PREFIX_VEX_0FEE */
5379   {
5380     { Bad_Opcode },
5381     { Bad_Opcode },
5382     { "vpmaxsw",        { XM, Vex, EXx }, 0 },
5383   },
5384
5385   /* PREFIX_VEX_0FEF */
5386   {
5387     { Bad_Opcode },
5388     { Bad_Opcode },
5389     { "vpxor",          { XM, Vex, EXx }, 0 },
5390   },
5391
5392   /* PREFIX_VEX_0FF0 */
5393   {
5394     { Bad_Opcode },
5395     { Bad_Opcode },
5396     { Bad_Opcode },
5397     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5398   },
5399
5400   /* PREFIX_VEX_0FF1 */
5401   {
5402     { Bad_Opcode },
5403     { Bad_Opcode },
5404     { "vpsllw",         { XM, Vex, EXxmm }, 0 },
5405   },
5406
5407   /* PREFIX_VEX_0FF2 */
5408   {
5409     { Bad_Opcode },
5410     { Bad_Opcode },
5411     { "vpslld",         { XM, Vex, EXxmm }, 0 },
5412   },
5413
5414   /* PREFIX_VEX_0FF3 */
5415   {
5416     { Bad_Opcode },
5417     { Bad_Opcode },
5418     { "vpsllq",         { XM, Vex, EXxmm }, 0 },
5419   },
5420
5421   /* PREFIX_VEX_0FF4 */
5422   {
5423     { Bad_Opcode },
5424     { Bad_Opcode },
5425     { "vpmuludq",       { XM, Vex, EXx }, 0 },
5426   },
5427
5428   /* PREFIX_VEX_0FF5 */
5429   {
5430     { Bad_Opcode },
5431     { Bad_Opcode },
5432     { "vpmaddwd",       { XM, Vex, EXx }, 0 },
5433   },
5434
5435   /* PREFIX_VEX_0FF6 */
5436   {
5437     { Bad_Opcode },
5438     { Bad_Opcode },
5439     { "vpsadbw",        { XM, Vex, EXx }, 0 },
5440   },
5441
5442   /* PREFIX_VEX_0FF7 */
5443   {
5444     { Bad_Opcode },
5445     { Bad_Opcode },
5446     { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5447   },
5448
5449   /* PREFIX_VEX_0FF8 */
5450   {
5451     { Bad_Opcode },
5452     { Bad_Opcode },
5453     { "vpsubb",         { XM, Vex, EXx }, 0 },
5454   },
5455
5456   /* PREFIX_VEX_0FF9 */
5457   {
5458     { Bad_Opcode },
5459     { Bad_Opcode },
5460     { "vpsubw",         { XM, Vex, EXx }, 0 },
5461   },
5462
5463   /* PREFIX_VEX_0FFA */
5464   {
5465     { Bad_Opcode },
5466     { Bad_Opcode },
5467     { "vpsubd",         { XM, Vex, EXx }, 0 },
5468   },
5469
5470   /* PREFIX_VEX_0FFB */
5471   {
5472     { Bad_Opcode },
5473     { Bad_Opcode },
5474     { "vpsubq",         { XM, Vex, EXx }, 0 },
5475   },
5476
5477   /* PREFIX_VEX_0FFC */
5478   {
5479     { Bad_Opcode },
5480     { Bad_Opcode },
5481     { "vpaddb",         { XM, Vex, EXx }, 0 },
5482   },
5483
5484   /* PREFIX_VEX_0FFD */
5485   {
5486     { Bad_Opcode },
5487     { Bad_Opcode },
5488     { "vpaddw",         { XM, Vex, EXx }, 0 },
5489   },
5490
5491   /* PREFIX_VEX_0FFE */
5492   {
5493     { Bad_Opcode },
5494     { Bad_Opcode },
5495     { "vpaddd",         { XM, Vex, EXx }, 0 },
5496   },
5497
5498   /* PREFIX_VEX_0F3800 */
5499   {
5500     { Bad_Opcode },
5501     { Bad_Opcode },
5502     { "vpshufb",        { XM, Vex, EXx }, 0 },
5503   },
5504
5505   /* PREFIX_VEX_0F3801 */
5506   {
5507     { Bad_Opcode },
5508     { Bad_Opcode },
5509     { "vphaddw",        { XM, Vex, EXx }, 0 },
5510   },
5511
5512   /* PREFIX_VEX_0F3802 */
5513   {
5514     { Bad_Opcode },
5515     { Bad_Opcode },
5516     { "vphaddd",        { XM, Vex, EXx }, 0 },
5517   },
5518
5519   /* PREFIX_VEX_0F3803 */
5520   {
5521     { Bad_Opcode },
5522     { Bad_Opcode },
5523     { "vphaddsw",       { XM, Vex, EXx }, 0 },
5524   },
5525
5526   /* PREFIX_VEX_0F3804 */
5527   {
5528     { Bad_Opcode },
5529     { Bad_Opcode },
5530     { "vpmaddubsw",     { XM, Vex, EXx }, 0 },
5531   },
5532
5533   /* PREFIX_VEX_0F3805 */
5534   {
5535     { Bad_Opcode },
5536     { Bad_Opcode },
5537     { "vphsubw",        { XM, Vex, EXx }, 0 },
5538   },
5539
5540   /* PREFIX_VEX_0F3806 */
5541   {
5542     { Bad_Opcode },
5543     { Bad_Opcode },
5544     { "vphsubd",        { XM, Vex, EXx }, 0 },
5545   },
5546
5547   /* PREFIX_VEX_0F3807 */
5548   {
5549     { Bad_Opcode },
5550     { Bad_Opcode },
5551     { "vphsubsw",       { XM, Vex, EXx }, 0 },
5552   },
5553
5554   /* PREFIX_VEX_0F3808 */
5555   {
5556     { Bad_Opcode },
5557     { Bad_Opcode },
5558     { "vpsignb",        { XM, Vex, EXx }, 0 },
5559   },
5560
5561   /* PREFIX_VEX_0F3809 */
5562   {
5563     { Bad_Opcode },
5564     { Bad_Opcode },
5565     { "vpsignw",        { XM, Vex, EXx }, 0 },
5566   },
5567
5568   /* PREFIX_VEX_0F380A */
5569   {
5570     { Bad_Opcode },
5571     { Bad_Opcode },
5572     { "vpsignd",        { XM, Vex, EXx }, 0 },
5573   },
5574
5575   /* PREFIX_VEX_0F380B */
5576   {
5577     { Bad_Opcode },
5578     { Bad_Opcode },
5579     { "vpmulhrsw",      { XM, Vex, EXx }, 0 },
5580   },
5581
5582   /* PREFIX_VEX_0F380C */
5583   {
5584     { Bad_Opcode },
5585     { Bad_Opcode },
5586     { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5587   },
5588
5589   /* PREFIX_VEX_0F380D */
5590   {
5591     { Bad_Opcode },
5592     { Bad_Opcode },
5593     { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5594   },
5595
5596   /* PREFIX_VEX_0F380E */
5597   {
5598     { Bad_Opcode },
5599     { Bad_Opcode },
5600     { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5601   },
5602
5603   /* PREFIX_VEX_0F380F */
5604   {
5605     { Bad_Opcode },
5606     { Bad_Opcode },
5607     { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5608   },
5609
5610   /* PREFIX_VEX_0F3813 */
5611   {
5612     { Bad_Opcode },
5613     { Bad_Opcode },
5614     { "vcvtph2ps", { XM, EXxmmq }, 0 },
5615   },
5616
5617   /* PREFIX_VEX_0F3816 */
5618   {
5619     { Bad_Opcode },
5620     { Bad_Opcode },
5621     { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5622   },
5623
5624   /* PREFIX_VEX_0F3817 */
5625   {
5626     { Bad_Opcode },
5627     { Bad_Opcode },
5628     { "vptest",         { XM, EXx }, 0 },
5629   },
5630
5631   /* PREFIX_VEX_0F3818 */
5632   {
5633     { Bad_Opcode },
5634     { Bad_Opcode },
5635     { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5636   },
5637
5638   /* PREFIX_VEX_0F3819 */
5639   {
5640     { Bad_Opcode },
5641     { Bad_Opcode },
5642     { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5643   },
5644
5645   /* PREFIX_VEX_0F381A */
5646   {
5647     { Bad_Opcode },
5648     { Bad_Opcode },
5649     { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5650   },
5651
5652   /* PREFIX_VEX_0F381C */
5653   {
5654     { Bad_Opcode },
5655     { Bad_Opcode },
5656     { "vpabsb",         { XM, EXx }, 0 },
5657   },
5658
5659   /* PREFIX_VEX_0F381D */
5660   {
5661     { Bad_Opcode },
5662     { Bad_Opcode },
5663     { "vpabsw",         { XM, EXx }, 0 },
5664   },
5665
5666   /* PREFIX_VEX_0F381E */
5667   {
5668     { Bad_Opcode },
5669     { Bad_Opcode },
5670     { "vpabsd",         { XM, EXx }, 0 },
5671   },
5672
5673   /* PREFIX_VEX_0F3820 */
5674   {
5675     { Bad_Opcode },
5676     { Bad_Opcode },
5677     { "vpmovsxbw",      { XM, EXxmmq }, 0 },
5678   },
5679
5680   /* PREFIX_VEX_0F3821 */
5681   {
5682     { Bad_Opcode },
5683     { Bad_Opcode },
5684     { "vpmovsxbd",      { XM, EXxmmqd }, 0 },
5685   },
5686
5687   /* PREFIX_VEX_0F3822 */
5688   {
5689     { Bad_Opcode },
5690     { Bad_Opcode },
5691     { "vpmovsxbq",      { XM, EXxmmdw }, 0 },
5692   },
5693
5694   /* PREFIX_VEX_0F3823 */
5695   {
5696     { Bad_Opcode },
5697     { Bad_Opcode },
5698     { "vpmovsxwd",      { XM, EXxmmq }, 0 },
5699   },
5700
5701   /* PREFIX_VEX_0F3824 */
5702   {
5703     { Bad_Opcode },
5704     { Bad_Opcode },
5705     { "vpmovsxwq",      { XM, EXxmmqd }, 0 },
5706   },
5707
5708   /* PREFIX_VEX_0F3825 */
5709   {
5710     { Bad_Opcode },
5711     { Bad_Opcode },
5712     { "vpmovsxdq",      { XM, EXxmmq }, 0 },
5713   },
5714
5715   /* PREFIX_VEX_0F3828 */
5716   {
5717     { Bad_Opcode },
5718     { Bad_Opcode },
5719     { "vpmuldq",        { XM, Vex, EXx }, 0 },
5720   },
5721
5722   /* PREFIX_VEX_0F3829 */
5723   {
5724     { Bad_Opcode },
5725     { Bad_Opcode },
5726     { "vpcmpeqq",       { XM, Vex, EXx }, 0 },
5727   },
5728
5729   /* PREFIX_VEX_0F382A */
5730   {
5731     { Bad_Opcode },
5732     { Bad_Opcode },
5733     { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5734   },
5735
5736   /* PREFIX_VEX_0F382B */
5737   {
5738     { Bad_Opcode },
5739     { Bad_Opcode },
5740     { "vpackusdw",      { XM, Vex, EXx }, 0 },
5741   },
5742
5743   /* PREFIX_VEX_0F382C */
5744   {
5745     { Bad_Opcode },
5746     { Bad_Opcode },
5747      { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5748   },
5749
5750   /* PREFIX_VEX_0F382D */
5751   {
5752     { Bad_Opcode },
5753     { Bad_Opcode },
5754      { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5755   },
5756
5757   /* PREFIX_VEX_0F382E */
5758   {
5759     { Bad_Opcode },
5760     { Bad_Opcode },
5761      { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5762   },
5763
5764   /* PREFIX_VEX_0F382F */
5765   {
5766     { Bad_Opcode },
5767     { Bad_Opcode },
5768      { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5769   },
5770
5771   /* PREFIX_VEX_0F3830 */
5772   {
5773     { Bad_Opcode },
5774     { Bad_Opcode },
5775     { "vpmovzxbw",      { XM, EXxmmq }, 0 },
5776   },
5777
5778   /* PREFIX_VEX_0F3831 */
5779   {
5780     { Bad_Opcode },
5781     { Bad_Opcode },
5782     { "vpmovzxbd",      { XM, EXxmmqd }, 0 },
5783   },
5784
5785   /* PREFIX_VEX_0F3832 */
5786   {
5787     { Bad_Opcode },
5788     { Bad_Opcode },
5789     { "vpmovzxbq",      { XM, EXxmmdw }, 0 },
5790   },
5791
5792   /* PREFIX_VEX_0F3833 */
5793   {
5794     { Bad_Opcode },
5795     { Bad_Opcode },
5796     { "vpmovzxwd",      { XM, EXxmmq }, 0 },
5797   },
5798
5799   /* PREFIX_VEX_0F3834 */
5800   {
5801     { Bad_Opcode },
5802     { Bad_Opcode },
5803     { "vpmovzxwq",      { XM, EXxmmqd }, 0 },
5804   },
5805
5806   /* PREFIX_VEX_0F3835 */
5807   {
5808     { Bad_Opcode },
5809     { Bad_Opcode },
5810     { "vpmovzxdq",      { XM, EXxmmq }, 0 },
5811   },
5812
5813   /* PREFIX_VEX_0F3836 */
5814   {
5815     { Bad_Opcode },
5816     { Bad_Opcode },
5817     { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5818   },
5819
5820   /* PREFIX_VEX_0F3837 */
5821   {
5822     { Bad_Opcode },
5823     { Bad_Opcode },
5824     { "vpcmpgtq",       { XM, Vex, EXx }, 0 },
5825   },
5826
5827   /* PREFIX_VEX_0F3838 */
5828   {
5829     { Bad_Opcode },
5830     { Bad_Opcode },
5831     { "vpminsb",        { XM, Vex, EXx }, 0 },
5832   },
5833
5834   /* PREFIX_VEX_0F3839 */
5835   {
5836     { Bad_Opcode },
5837     { Bad_Opcode },
5838     { "vpminsd",        { XM, Vex, EXx }, 0 },
5839   },
5840
5841   /* PREFIX_VEX_0F383A */
5842   {
5843     { Bad_Opcode },
5844     { Bad_Opcode },
5845     { "vpminuw",        { XM, Vex, EXx }, 0 },
5846   },
5847
5848   /* PREFIX_VEX_0F383B */
5849   {
5850     { Bad_Opcode },
5851     { Bad_Opcode },
5852     { "vpminud",        { XM, Vex, EXx }, 0 },
5853   },
5854
5855   /* PREFIX_VEX_0F383C */
5856   {
5857     { Bad_Opcode },
5858     { Bad_Opcode },
5859     { "vpmaxsb",        { XM, Vex, EXx }, 0 },
5860   },
5861
5862   /* PREFIX_VEX_0F383D */
5863   {
5864     { Bad_Opcode },
5865     { Bad_Opcode },
5866     { "vpmaxsd",        { XM, Vex, EXx }, 0 },
5867   },
5868
5869   /* PREFIX_VEX_0F383E */
5870   {
5871     { Bad_Opcode },
5872     { Bad_Opcode },
5873     { "vpmaxuw",        { XM, Vex, EXx }, 0 },
5874   },
5875
5876   /* PREFIX_VEX_0F383F */
5877   {
5878     { Bad_Opcode },
5879     { Bad_Opcode },
5880     { "vpmaxud",        { XM, Vex, EXx }, 0 },
5881   },
5882
5883   /* PREFIX_VEX_0F3840 */
5884   {
5885     { Bad_Opcode },
5886     { Bad_Opcode },
5887     { "vpmulld",        { XM, Vex, EXx }, 0 },
5888   },
5889
5890   /* PREFIX_VEX_0F3841 */
5891   {
5892     { Bad_Opcode },
5893     { Bad_Opcode },
5894     { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
5895   },
5896
5897   /* PREFIX_VEX_0F3845 */
5898   {
5899     { Bad_Opcode },
5900     { Bad_Opcode },
5901     { "vpsrlv%LW", { XM, Vex, EXx }, 0 },
5902   },
5903
5904   /* PREFIX_VEX_0F3846 */
5905   {
5906     { Bad_Opcode },
5907     { Bad_Opcode },
5908     { VEX_W_TABLE (VEX_W_0F3846_P_2) },
5909   },
5910
5911   /* PREFIX_VEX_0F3847 */
5912   {
5913     { Bad_Opcode },
5914     { Bad_Opcode },
5915     { "vpsllv%LW", { XM, Vex, EXx }, 0 },
5916   },
5917
5918   /* PREFIX_VEX_0F3858 */
5919   {
5920     { Bad_Opcode },
5921     { Bad_Opcode },
5922     { VEX_W_TABLE (VEX_W_0F3858_P_2) },
5923   },
5924
5925   /* PREFIX_VEX_0F3859 */
5926   {
5927     { Bad_Opcode },
5928     { Bad_Opcode },
5929     { VEX_W_TABLE (VEX_W_0F3859_P_2) },
5930   },
5931
5932   /* PREFIX_VEX_0F385A */
5933   {
5934     { Bad_Opcode },
5935     { Bad_Opcode },
5936     { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
5937   },
5938
5939   /* PREFIX_VEX_0F3878 */
5940   {
5941     { Bad_Opcode },
5942     { Bad_Opcode },
5943     { VEX_W_TABLE (VEX_W_0F3878_P_2) },
5944   },
5945
5946   /* PREFIX_VEX_0F3879 */
5947   {
5948     { Bad_Opcode },
5949     { Bad_Opcode },
5950     { VEX_W_TABLE (VEX_W_0F3879_P_2) },
5951   },
5952
5953   /* PREFIX_VEX_0F388C */
5954   {
5955     { Bad_Opcode },
5956     { Bad_Opcode },
5957     { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
5958   },
5959
5960   /* PREFIX_VEX_0F388E */
5961   {
5962     { Bad_Opcode },
5963     { Bad_Opcode },
5964     { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
5965   },
5966
5967   /* PREFIX_VEX_0F3890 */
5968   {
5969     { Bad_Opcode },
5970     { Bad_Opcode },
5971     { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 },
5972   },
5973
5974   /* PREFIX_VEX_0F3891 */
5975   {
5976     { Bad_Opcode },
5977     { Bad_Opcode },
5978     { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
5979   },
5980
5981   /* PREFIX_VEX_0F3892 */
5982   {
5983     { Bad_Opcode },
5984     { Bad_Opcode },
5985     { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 },
5986   },
5987
5988   /* PREFIX_VEX_0F3893 */
5989   {
5990     { Bad_Opcode },
5991     { Bad_Opcode },
5992     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
5993   },
5994
5995   /* PREFIX_VEX_0F3896 */
5996   {
5997     { Bad_Opcode },
5998     { Bad_Opcode },
5999     { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 },
6000   },
6001
6002   /* PREFIX_VEX_0F3897 */
6003   {
6004     { Bad_Opcode },
6005     { Bad_Opcode },
6006     { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 },
6007   },
6008
6009   /* PREFIX_VEX_0F3898 */
6010   {
6011     { Bad_Opcode },
6012     { Bad_Opcode },
6013     { "vfmadd132p%XW", { XM, Vex, EXx }, 0 },
6014   },
6015
6016   /* PREFIX_VEX_0F3899 */
6017   {
6018     { Bad_Opcode },
6019     { Bad_Opcode },
6020     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6021   },
6022
6023   /* PREFIX_VEX_0F389A */
6024   {
6025     { Bad_Opcode },
6026     { Bad_Opcode },
6027     { "vfmsub132p%XW", { XM, Vex, EXx }, 0 },
6028   },
6029
6030   /* PREFIX_VEX_0F389B */
6031   {
6032     { Bad_Opcode },
6033     { Bad_Opcode },
6034     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6035   },
6036
6037   /* PREFIX_VEX_0F389C */
6038   {
6039     { Bad_Opcode },
6040     { Bad_Opcode },
6041     { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 },
6042   },
6043
6044   /* PREFIX_VEX_0F389D */
6045   {
6046     { Bad_Opcode },
6047     { Bad_Opcode },
6048     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6049   },
6050
6051   /* PREFIX_VEX_0F389E */
6052   {
6053     { Bad_Opcode },
6054     { Bad_Opcode },
6055     { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 },
6056   },
6057
6058   /* PREFIX_VEX_0F389F */
6059   {
6060     { Bad_Opcode },
6061     { Bad_Opcode },
6062     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6063   },
6064
6065   /* PREFIX_VEX_0F38A6 */
6066   {
6067     { Bad_Opcode },
6068     { Bad_Opcode },
6069     { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 },
6070     { Bad_Opcode },
6071   },
6072
6073   /* PREFIX_VEX_0F38A7 */
6074   {
6075     { Bad_Opcode },
6076     { Bad_Opcode },
6077     { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 },
6078   },
6079
6080   /* PREFIX_VEX_0F38A8 */
6081   {
6082     { Bad_Opcode },
6083     { Bad_Opcode },
6084     { "vfmadd213p%XW", { XM, Vex, EXx }, 0 },
6085   },
6086
6087   /* PREFIX_VEX_0F38A9 */
6088   {
6089     { Bad_Opcode },
6090     { Bad_Opcode },
6091     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6092   },
6093
6094   /* PREFIX_VEX_0F38AA */
6095   {
6096     { Bad_Opcode },
6097     { Bad_Opcode },
6098     { "vfmsub213p%XW", { XM, Vex, EXx }, 0 },
6099   },
6100
6101   /* PREFIX_VEX_0F38AB */
6102   {
6103     { Bad_Opcode },
6104     { Bad_Opcode },
6105     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6106   },
6107
6108   /* PREFIX_VEX_0F38AC */
6109   {
6110     { Bad_Opcode },
6111     { Bad_Opcode },
6112     { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 },
6113   },
6114
6115   /* PREFIX_VEX_0F38AD */
6116   {
6117     { Bad_Opcode },
6118     { Bad_Opcode },
6119     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6120   },
6121
6122   /* PREFIX_VEX_0F38AE */
6123   {
6124     { Bad_Opcode },
6125     { Bad_Opcode },
6126     { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 },
6127   },
6128
6129   /* PREFIX_VEX_0F38AF */
6130   {
6131     { Bad_Opcode },
6132     { Bad_Opcode },
6133     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6134   },
6135
6136   /* PREFIX_VEX_0F38B6 */
6137   {
6138     { Bad_Opcode },
6139     { Bad_Opcode },
6140     { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 },
6141   },
6142
6143   /* PREFIX_VEX_0F38B7 */
6144   {
6145     { Bad_Opcode },
6146     { Bad_Opcode },
6147     { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 },
6148   },
6149
6150   /* PREFIX_VEX_0F38B8 */
6151   {
6152     { Bad_Opcode },
6153     { Bad_Opcode },
6154     { "vfmadd231p%XW", { XM, Vex, EXx }, 0 },
6155   },
6156
6157   /* PREFIX_VEX_0F38B9 */
6158   {
6159     { Bad_Opcode },
6160     { Bad_Opcode },
6161     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6162   },
6163
6164   /* PREFIX_VEX_0F38BA */
6165   {
6166     { Bad_Opcode },
6167     { Bad_Opcode },
6168     { "vfmsub231p%XW", { XM, Vex, EXx }, 0 },
6169   },
6170
6171   /* PREFIX_VEX_0F38BB */
6172   {
6173     { Bad_Opcode },
6174     { Bad_Opcode },
6175     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6176   },
6177
6178   /* PREFIX_VEX_0F38BC */
6179   {
6180     { Bad_Opcode },
6181     { Bad_Opcode },
6182     { "vfnmadd231p%XW", { XM, Vex, EXx }, 0 },
6183   },
6184
6185   /* PREFIX_VEX_0F38BD */
6186   {
6187     { Bad_Opcode },
6188     { Bad_Opcode },
6189     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6190   },
6191
6192   /* PREFIX_VEX_0F38BE */
6193   {
6194     { Bad_Opcode },
6195     { Bad_Opcode },
6196     { "vfnmsub231p%XW", { XM, Vex, EXx }, 0 },
6197   },
6198
6199   /* PREFIX_VEX_0F38BF */
6200   {
6201     { Bad_Opcode },
6202     { Bad_Opcode },
6203     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6204   },
6205
6206   /* PREFIX_VEX_0F38CF */
6207   {
6208     { Bad_Opcode },
6209     { Bad_Opcode },
6210     { VEX_W_TABLE (VEX_W_0F38CF_P_2) },
6211   },
6212
6213   /* PREFIX_VEX_0F38DB */
6214   {
6215     { Bad_Opcode },
6216     { Bad_Opcode },
6217     { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6218   },
6219
6220   /* PREFIX_VEX_0F38DC */
6221   {
6222     { Bad_Opcode },
6223     { Bad_Opcode },
6224     { "vaesenc",        { XM, Vex, EXx }, 0 },
6225   },
6226
6227   /* PREFIX_VEX_0F38DD */
6228   {
6229     { Bad_Opcode },
6230     { Bad_Opcode },
6231     { "vaesenclast",    { XM, Vex, EXx }, 0 },
6232   },
6233
6234   /* PREFIX_VEX_0F38DE */
6235   {
6236     { Bad_Opcode },
6237     { Bad_Opcode },
6238     { "vaesdec",        { XM, Vex, EXx }, 0 },
6239   },
6240
6241   /* PREFIX_VEX_0F38DF */
6242   {
6243     { Bad_Opcode },
6244     { Bad_Opcode },
6245     { "vaesdeclast",    { XM, Vex, EXx }, 0 },
6246   },
6247
6248   /* PREFIX_VEX_0F38F2 */
6249   {
6250     { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6251   },
6252
6253   /* PREFIX_VEX_0F38F3_REG_1 */
6254   {
6255     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6256   },
6257
6258   /* PREFIX_VEX_0F38F3_REG_2 */
6259   {
6260     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6261   },
6262
6263   /* PREFIX_VEX_0F38F3_REG_3 */
6264   {
6265     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6266   },
6267
6268   /* PREFIX_VEX_0F38F5 */
6269   {
6270     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6271     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6272     { Bad_Opcode },
6273     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6274   },
6275
6276   /* PREFIX_VEX_0F38F6 */
6277   {
6278     { Bad_Opcode },
6279     { Bad_Opcode },
6280     { Bad_Opcode },
6281     { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6282   },
6283
6284   /* PREFIX_VEX_0F38F7 */
6285   {
6286     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6287     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6288     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6289     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6290   },
6291
6292   /* PREFIX_VEX_0F3A00 */
6293   {
6294     { Bad_Opcode },
6295     { Bad_Opcode },
6296     { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6297   },
6298
6299   /* PREFIX_VEX_0F3A01 */
6300   {
6301     { Bad_Opcode },
6302     { Bad_Opcode },
6303     { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6304   },
6305
6306   /* PREFIX_VEX_0F3A02 */
6307   {
6308     { Bad_Opcode },
6309     { Bad_Opcode },
6310     { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6311   },
6312
6313   /* PREFIX_VEX_0F3A04 */
6314   {
6315     { Bad_Opcode },
6316     { Bad_Opcode },
6317     { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6318   },
6319
6320   /* PREFIX_VEX_0F3A05 */
6321   {
6322     { Bad_Opcode },
6323     { Bad_Opcode },
6324     { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6325   },
6326
6327   /* PREFIX_VEX_0F3A06 */
6328   {
6329     { Bad_Opcode },
6330     { Bad_Opcode },
6331     { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6332   },
6333
6334   /* PREFIX_VEX_0F3A08 */
6335   {
6336     { Bad_Opcode },
6337     { Bad_Opcode },
6338     { "vroundps",       { XM, EXx, Ib }, 0 },
6339   },
6340
6341   /* PREFIX_VEX_0F3A09 */
6342   {
6343     { Bad_Opcode },
6344     { Bad_Opcode },
6345     { "vroundpd",       { XM, EXx, Ib }, 0 },
6346   },
6347
6348   /* PREFIX_VEX_0F3A0A */
6349   {
6350     { Bad_Opcode },
6351     { Bad_Opcode },
6352     { "vroundss",       { XMScalar, VexScalar, EXdScalar, Ib }, 0 },
6353   },
6354
6355   /* PREFIX_VEX_0F3A0B */
6356   {
6357     { Bad_Opcode },
6358     { Bad_Opcode },
6359     { "vroundsd",       { XMScalar, VexScalar, EXqScalar, Ib }, 0 },
6360   },
6361
6362   /* PREFIX_VEX_0F3A0C */
6363   {
6364     { Bad_Opcode },
6365     { Bad_Opcode },
6366     { "vblendps",       { XM, Vex, EXx, Ib }, 0 },
6367   },
6368
6369   /* PREFIX_VEX_0F3A0D */
6370   {
6371     { Bad_Opcode },
6372     { Bad_Opcode },
6373     { "vblendpd",       { XM, Vex, EXx, Ib }, 0 },
6374   },
6375
6376   /* PREFIX_VEX_0F3A0E */
6377   {
6378     { Bad_Opcode },
6379     { Bad_Opcode },
6380     { "vpblendw",       { XM, Vex, EXx, Ib }, 0 },
6381   },
6382
6383   /* PREFIX_VEX_0F3A0F */
6384   {
6385     { Bad_Opcode },
6386     { Bad_Opcode },
6387     { "vpalignr",       { XM, Vex, EXx, Ib }, 0 },
6388   },
6389
6390   /* PREFIX_VEX_0F3A14 */
6391   {
6392     { Bad_Opcode },
6393     { Bad_Opcode },
6394     { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6395   },
6396
6397   /* PREFIX_VEX_0F3A15 */
6398   {
6399     { Bad_Opcode },
6400     { Bad_Opcode },
6401     { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6402   },
6403
6404   /* PREFIX_VEX_0F3A16 */
6405   {
6406     { Bad_Opcode },
6407     { Bad_Opcode },
6408     { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6409   },
6410
6411   /* PREFIX_VEX_0F3A17 */
6412   {
6413     { Bad_Opcode },
6414     { Bad_Opcode },
6415     { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6416   },
6417
6418   /* PREFIX_VEX_0F3A18 */
6419   {
6420     { Bad_Opcode },
6421     { Bad_Opcode },
6422     { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6423   },
6424
6425   /* PREFIX_VEX_0F3A19 */
6426   {
6427     { Bad_Opcode },
6428     { Bad_Opcode },
6429     { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6430   },
6431
6432   /* PREFIX_VEX_0F3A1D */
6433   {
6434     { Bad_Opcode },
6435     { Bad_Opcode },
6436     { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 },
6437   },
6438
6439   /* PREFIX_VEX_0F3A20 */
6440   {
6441     { Bad_Opcode },
6442     { Bad_Opcode },
6443     { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6444   },
6445
6446   /* PREFIX_VEX_0F3A21 */
6447   {
6448     { Bad_Opcode },
6449     { Bad_Opcode },
6450     { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6451   },
6452
6453   /* PREFIX_VEX_0F3A22 */
6454   {
6455     { Bad_Opcode },
6456     { Bad_Opcode },
6457     { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6458   },
6459
6460   /* PREFIX_VEX_0F3A30 */
6461   {
6462     { Bad_Opcode },
6463     { Bad_Opcode },
6464     { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6465   },
6466
6467   /* PREFIX_VEX_0F3A31 */
6468   {
6469     { Bad_Opcode },
6470     { Bad_Opcode },
6471     { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6472   },
6473
6474   /* PREFIX_VEX_0F3A32 */
6475   {
6476     { Bad_Opcode },
6477     { Bad_Opcode },
6478     { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6479   },
6480
6481   /* PREFIX_VEX_0F3A33 */
6482   {
6483     { Bad_Opcode },
6484     { Bad_Opcode },
6485     { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6486   },
6487
6488   /* PREFIX_VEX_0F3A38 */
6489   {
6490     { Bad_Opcode },
6491     { Bad_Opcode },
6492     { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6493   },
6494
6495   /* PREFIX_VEX_0F3A39 */
6496   {
6497     { Bad_Opcode },
6498     { Bad_Opcode },
6499     { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6500   },
6501
6502   /* PREFIX_VEX_0F3A40 */
6503   {
6504     { Bad_Opcode },
6505     { Bad_Opcode },
6506     { "vdpps",          { XM, Vex, EXx, Ib }, 0 },
6507   },
6508
6509   /* PREFIX_VEX_0F3A41 */
6510   {
6511     { Bad_Opcode },
6512     { Bad_Opcode },
6513     { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6514   },
6515
6516   /* PREFIX_VEX_0F3A42 */
6517   {
6518     { Bad_Opcode },
6519     { Bad_Opcode },
6520     { "vmpsadbw",       { XM, Vex, EXx, Ib }, 0 },
6521   },
6522
6523   /* PREFIX_VEX_0F3A44 */
6524   {
6525     { Bad_Opcode },
6526     { Bad_Opcode },
6527     { "vpclmulqdq",     { XM, Vex, EXx, PCLMUL }, 0 },
6528   },
6529
6530   /* PREFIX_VEX_0F3A46 */
6531   {
6532     { Bad_Opcode },
6533     { Bad_Opcode },
6534     { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6535   },
6536
6537   /* PREFIX_VEX_0F3A48 */
6538   {
6539     { Bad_Opcode },
6540     { Bad_Opcode },
6541     { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6542   },
6543
6544   /* PREFIX_VEX_0F3A49 */
6545   {
6546     { Bad_Opcode },
6547     { Bad_Opcode },
6548     { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6549   },
6550
6551   /* PREFIX_VEX_0F3A4A */
6552   {
6553     { Bad_Opcode },
6554     { Bad_Opcode },
6555     { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6556   },
6557
6558   /* PREFIX_VEX_0F3A4B */
6559   {
6560     { Bad_Opcode },
6561     { Bad_Opcode },
6562     { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6563   },
6564
6565   /* PREFIX_VEX_0F3A4C */
6566   {
6567     { Bad_Opcode },
6568     { Bad_Opcode },
6569     { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6570   },
6571
6572   /* PREFIX_VEX_0F3A5C */
6573   {
6574     { Bad_Opcode },
6575     { Bad_Opcode },
6576     { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6577   },
6578
6579   /* PREFIX_VEX_0F3A5D */
6580   {
6581     { Bad_Opcode },
6582     { Bad_Opcode },
6583     { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6584   },
6585
6586   /* PREFIX_VEX_0F3A5E */
6587   {
6588     { Bad_Opcode },
6589     { Bad_Opcode },
6590     { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6591   },
6592
6593   /* PREFIX_VEX_0F3A5F */
6594   {
6595     { Bad_Opcode },
6596     { Bad_Opcode },
6597     { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6598   },
6599
6600   /* PREFIX_VEX_0F3A60 */
6601   {
6602     { Bad_Opcode },
6603     { Bad_Opcode },
6604     { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6605     { Bad_Opcode },
6606   },
6607
6608   /* PREFIX_VEX_0F3A61 */
6609   {
6610     { Bad_Opcode },
6611     { Bad_Opcode },
6612     { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6613   },
6614
6615   /* PREFIX_VEX_0F3A62 */
6616   {
6617     { Bad_Opcode },
6618     { Bad_Opcode },
6619     { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6620   },
6621
6622   /* PREFIX_VEX_0F3A63 */
6623   {
6624     { Bad_Opcode },
6625     { Bad_Opcode },
6626     { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6627   },
6628
6629   /* PREFIX_VEX_0F3A68 */
6630   {
6631     { Bad_Opcode },
6632     { Bad_Opcode },
6633     { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6634   },
6635
6636   /* PREFIX_VEX_0F3A69 */
6637   {
6638     { Bad_Opcode },
6639     { Bad_Opcode },
6640     { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6641   },
6642
6643   /* PREFIX_VEX_0F3A6A */
6644   {
6645     { Bad_Opcode },
6646     { Bad_Opcode },
6647     { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6648   },
6649
6650   /* PREFIX_VEX_0F3A6B */
6651   {
6652     { Bad_Opcode },
6653     { Bad_Opcode },
6654     { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6655   },
6656
6657   /* PREFIX_VEX_0F3A6C */
6658   {
6659     { Bad_Opcode },
6660     { Bad_Opcode },
6661     { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6662   },
6663
6664   /* PREFIX_VEX_0F3A6D */
6665   {
6666     { Bad_Opcode },
6667     { Bad_Opcode },
6668     { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6669   },
6670
6671   /* PREFIX_VEX_0F3A6E */
6672   {
6673     { Bad_Opcode },
6674     { Bad_Opcode },
6675     { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6676   },
6677
6678   /* PREFIX_VEX_0F3A6F */
6679   {
6680     { Bad_Opcode },
6681     { Bad_Opcode },
6682     { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6683   },
6684
6685   /* PREFIX_VEX_0F3A78 */
6686   {
6687     { Bad_Opcode },
6688     { Bad_Opcode },
6689     { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6690   },
6691
6692   /* PREFIX_VEX_0F3A79 */
6693   {
6694     { Bad_Opcode },
6695     { Bad_Opcode },
6696     { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6697   },
6698
6699   /* PREFIX_VEX_0F3A7A */
6700   {
6701     { Bad_Opcode },
6702     { Bad_Opcode },
6703     { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6704   },
6705
6706   /* PREFIX_VEX_0F3A7B */
6707   {
6708     { Bad_Opcode },
6709     { Bad_Opcode },
6710     { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6711   },
6712
6713   /* PREFIX_VEX_0F3A7C */
6714   {
6715     { Bad_Opcode },
6716     { Bad_Opcode },
6717     { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6718     { Bad_Opcode },
6719   },
6720
6721   /* PREFIX_VEX_0F3A7D */
6722   {
6723     { Bad_Opcode },
6724     { Bad_Opcode },
6725     { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6726   },
6727
6728   /* PREFIX_VEX_0F3A7E */
6729   {
6730     { Bad_Opcode },
6731     { Bad_Opcode },
6732     { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6733   },
6734
6735   /* PREFIX_VEX_0F3A7F */
6736   {
6737     { Bad_Opcode },
6738     { Bad_Opcode },
6739     { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6740   },
6741
6742   /* PREFIX_VEX_0F3ACE */
6743   {
6744     { Bad_Opcode },
6745     { Bad_Opcode },
6746     { VEX_W_TABLE (VEX_W_0F3ACE_P_2) },
6747   },
6748
6749   /* PREFIX_VEX_0F3ACF */
6750   {
6751     { Bad_Opcode },
6752     { Bad_Opcode },
6753     { VEX_W_TABLE (VEX_W_0F3ACF_P_2) },
6754   },
6755
6756   /* PREFIX_VEX_0F3ADF */
6757   {
6758     { Bad_Opcode },
6759     { Bad_Opcode },
6760     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6761   },
6762
6763   /* PREFIX_VEX_0F3AF0 */
6764   {
6765     { Bad_Opcode },
6766     { Bad_Opcode },
6767     { Bad_Opcode },
6768     { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6769   },
6770
6771 #define NEED_PREFIX_TABLE
6772 #include "i386-dis-evex.h"
6773 #undef NEED_PREFIX_TABLE
6774 };
6775
6776 static const struct dis386 x86_64_table[][2] = {
6777   /* X86_64_06 */
6778   {
6779     { "pushP", { es }, 0 },
6780   },
6781
6782   /* X86_64_07 */
6783   {
6784     { "popP", { es }, 0 },
6785   },
6786
6787   /* X86_64_0D */
6788   {
6789     { "pushP", { cs }, 0 },
6790   },
6791
6792   /* X86_64_16 */
6793   {
6794     { "pushP", { ss }, 0 },
6795   },
6796
6797   /* X86_64_17 */
6798   {
6799     { "popP", { ss }, 0 },
6800   },
6801
6802   /* X86_64_1E */
6803   {
6804     { "pushP", { ds }, 0 },
6805   },
6806
6807   /* X86_64_1F */
6808   {
6809     { "popP", { ds }, 0 },
6810   },
6811
6812   /* X86_64_27 */
6813   {
6814     { "daa", { XX }, 0 },
6815   },
6816
6817   /* X86_64_2F */
6818   {
6819     { "das", { XX }, 0 },
6820   },
6821
6822   /* X86_64_37 */
6823   {
6824     { "aaa", { XX }, 0 },
6825   },
6826
6827   /* X86_64_3F */
6828   {
6829     { "aas", { XX }, 0 },
6830   },
6831
6832   /* X86_64_60 */
6833   {
6834     { "pushaP", { XX }, 0 },
6835   },
6836
6837   /* X86_64_61 */
6838   {
6839     { "popaP", { XX }, 0 },
6840   },
6841
6842   /* X86_64_62 */
6843   {
6844     { MOD_TABLE (MOD_62_32BIT) },
6845     { EVEX_TABLE (EVEX_0F) },
6846   },
6847
6848   /* X86_64_63 */
6849   {
6850     { "arpl", { Ew, Gw }, 0 },
6851     { "movs{lq|xd}", { Gv, Ed }, 0 },
6852   },
6853
6854   /* X86_64_6D */
6855   {
6856     { "ins{R|}", { Yzr, indirDX }, 0 },
6857     { "ins{G|}", { Yzr, indirDX }, 0 },
6858   },
6859
6860   /* X86_64_6F */
6861   {
6862     { "outs{R|}", { indirDXr, Xz }, 0 },
6863     { "outs{G|}", { indirDXr, Xz }, 0 },
6864   },
6865
6866   /* X86_64_82 */
6867   {
6868     /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode.  */
6869     { REG_TABLE (REG_80) },
6870   },
6871
6872   /* X86_64_9A */
6873   {
6874     { "Jcall{T|}", { Ap }, 0 },
6875   },
6876
6877   /* X86_64_C4 */
6878   {
6879     { MOD_TABLE (MOD_C4_32BIT) },
6880     { VEX_C4_TABLE (VEX_0F) },
6881   },
6882
6883   /* X86_64_C5 */
6884   {
6885     { MOD_TABLE (MOD_C5_32BIT) },
6886     { VEX_C5_TABLE (VEX_0F) },
6887   },
6888
6889   /* X86_64_CE */
6890   {
6891     { "into", { XX }, 0 },
6892   },
6893
6894   /* X86_64_D4 */
6895   {
6896     { "aam", { Ib }, 0 },
6897   },
6898
6899   /* X86_64_D5 */
6900   {
6901     { "aad", { Ib }, 0 },
6902   },
6903
6904   /* X86_64_E8 */
6905   {
6906     { "callP",          { Jv, BND }, 0 },
6907     { "call@",          { Jv, BND }, 0 }
6908   },
6909
6910   /* X86_64_E9 */
6911   {
6912     { "jmpP",           { Jv, BND }, 0 },
6913     { "jmp@",           { Jv, BND }, 0 }
6914   },
6915
6916   /* X86_64_EA */
6917   {
6918     { "Jjmp{T|}", { Ap }, 0 },
6919   },
6920
6921   /* X86_64_0F01_REG_0 */
6922   {
6923     { "sgdt{Q|IQ}", { M }, 0 },
6924     { "sgdt", { M }, 0 },
6925   },
6926
6927   /* X86_64_0F01_REG_1 */
6928   {
6929     { "sidt{Q|IQ}", { M }, 0 },
6930     { "sidt", { M }, 0 },
6931   },
6932
6933   /* X86_64_0F01_REG_2 */
6934   {
6935     { "lgdt{Q|Q}", { M }, 0 },
6936     { "lgdt", { M }, 0 },
6937   },
6938
6939   /* X86_64_0F01_REG_3 */
6940   {
6941     { "lidt{Q|Q}", { M }, 0 },
6942     { "lidt", { M }, 0 },
6943   },
6944 };
6945
6946 static const struct dis386 three_byte_table[][256] = {
6947
6948   /* THREE_BYTE_0F38 */
6949   {
6950     /* 00 */
6951     { "pshufb",         { MX, EM }, PREFIX_OPCODE },
6952     { "phaddw",         { MX, EM }, PREFIX_OPCODE },
6953     { "phaddd",         { MX, EM }, PREFIX_OPCODE },
6954     { "phaddsw",        { MX, EM }, PREFIX_OPCODE },
6955     { "pmaddubsw",      { MX, EM }, PREFIX_OPCODE },
6956     { "phsubw",         { MX, EM }, PREFIX_OPCODE },
6957     { "phsubd",         { MX, EM }, PREFIX_OPCODE },
6958     { "phsubsw",        { MX, EM }, PREFIX_OPCODE },
6959     /* 08 */
6960     { "psignb",         { MX, EM }, PREFIX_OPCODE },
6961     { "psignw",         { MX, EM }, PREFIX_OPCODE },
6962     { "psignd",         { MX, EM }, PREFIX_OPCODE },
6963     { "pmulhrsw",       { MX, EM }, PREFIX_OPCODE },
6964     { Bad_Opcode },
6965     { Bad_Opcode },
6966     { Bad_Opcode },
6967     { Bad_Opcode },
6968     /* 10 */
6969     { PREFIX_TABLE (PREFIX_0F3810) },
6970     { Bad_Opcode },
6971     { Bad_Opcode },
6972     { Bad_Opcode },
6973     { PREFIX_TABLE (PREFIX_0F3814) },
6974     { PREFIX_TABLE (PREFIX_0F3815) },
6975     { Bad_Opcode },
6976     { PREFIX_TABLE (PREFIX_0F3817) },
6977     /* 18 */
6978     { Bad_Opcode },
6979     { Bad_Opcode },
6980     { Bad_Opcode },
6981     { Bad_Opcode },
6982     { "pabsb",          { MX, EM }, PREFIX_OPCODE },
6983     { "pabsw",          { MX, EM }, PREFIX_OPCODE },
6984     { "pabsd",          { MX, EM }, PREFIX_OPCODE },
6985     { Bad_Opcode },
6986     /* 20 */
6987     { PREFIX_TABLE (PREFIX_0F3820) },
6988     { PREFIX_TABLE (PREFIX_0F3821) },
6989     { PREFIX_TABLE (PREFIX_0F3822) },
6990     { PREFIX_TABLE (PREFIX_0F3823) },
6991     { PREFIX_TABLE (PREFIX_0F3824) },
6992     { PREFIX_TABLE (PREFIX_0F3825) },
6993     { Bad_Opcode },
6994     { Bad_Opcode },
6995     /* 28 */
6996     { PREFIX_TABLE (PREFIX_0F3828) },
6997     { PREFIX_TABLE (PREFIX_0F3829) },
6998     { PREFIX_TABLE (PREFIX_0F382A) },
6999     { PREFIX_TABLE (PREFIX_0F382B) },
7000     { Bad_Opcode },
7001     { Bad_Opcode },
7002     { Bad_Opcode },
7003     { Bad_Opcode },
7004     /* 30 */
7005     { PREFIX_TABLE (PREFIX_0F3830) },
7006     { PREFIX_TABLE (PREFIX_0F3831) },
7007     { PREFIX_TABLE (PREFIX_0F3832) },
7008     { PREFIX_TABLE (PREFIX_0F3833) },
7009     { PREFIX_TABLE (PREFIX_0F3834) },
7010     { PREFIX_TABLE (PREFIX_0F3835) },
7011     { Bad_Opcode },
7012     { PREFIX_TABLE (PREFIX_0F3837) },
7013     /* 38 */
7014     { PREFIX_TABLE (PREFIX_0F3838) },
7015     { PREFIX_TABLE (PREFIX_0F3839) },
7016     { PREFIX_TABLE (PREFIX_0F383A) },
7017     { PREFIX_TABLE (PREFIX_0F383B) },
7018     { PREFIX_TABLE (PREFIX_0F383C) },
7019     { PREFIX_TABLE (PREFIX_0F383D) },
7020     { PREFIX_TABLE (PREFIX_0F383E) },
7021     { PREFIX_TABLE (PREFIX_0F383F) },
7022     /* 40 */
7023     { PREFIX_TABLE (PREFIX_0F3840) },
7024     { PREFIX_TABLE (PREFIX_0F3841) },
7025     { Bad_Opcode },
7026     { Bad_Opcode },
7027     { Bad_Opcode },
7028     { Bad_Opcode },
7029     { Bad_Opcode },
7030     { Bad_Opcode },
7031     /* 48 */
7032     { Bad_Opcode },
7033     { Bad_Opcode },
7034     { Bad_Opcode },
7035     { Bad_Opcode },
7036     { Bad_Opcode },
7037     { Bad_Opcode },
7038     { Bad_Opcode },
7039     { Bad_Opcode },
7040     /* 50 */
7041     { Bad_Opcode },
7042     { Bad_Opcode },
7043     { Bad_Opcode },
7044     { Bad_Opcode },
7045     { Bad_Opcode },
7046     { Bad_Opcode },
7047     { Bad_Opcode },
7048     { Bad_Opcode },
7049     /* 58 */
7050     { Bad_Opcode },
7051     { Bad_Opcode },
7052     { Bad_Opcode },
7053     { Bad_Opcode },
7054     { Bad_Opcode },
7055     { Bad_Opcode },
7056     { Bad_Opcode },
7057     { Bad_Opcode },
7058     /* 60 */
7059     { Bad_Opcode },
7060     { Bad_Opcode },
7061     { Bad_Opcode },
7062     { Bad_Opcode },
7063     { Bad_Opcode },
7064     { Bad_Opcode },
7065     { Bad_Opcode },
7066     { Bad_Opcode },
7067     /* 68 */
7068     { Bad_Opcode },
7069     { Bad_Opcode },
7070     { Bad_Opcode },
7071     { Bad_Opcode },
7072     { Bad_Opcode },
7073     { Bad_Opcode },
7074     { Bad_Opcode },
7075     { Bad_Opcode },
7076     /* 70 */
7077     { Bad_Opcode },
7078     { Bad_Opcode },
7079     { Bad_Opcode },
7080     { Bad_Opcode },
7081     { Bad_Opcode },
7082     { Bad_Opcode },
7083     { Bad_Opcode },
7084     { Bad_Opcode },
7085     /* 78 */
7086     { Bad_Opcode },
7087     { Bad_Opcode },
7088     { Bad_Opcode },
7089     { Bad_Opcode },
7090     { Bad_Opcode },
7091     { Bad_Opcode },
7092     { Bad_Opcode },
7093     { Bad_Opcode },
7094     /* 80 */
7095     { PREFIX_TABLE (PREFIX_0F3880) },
7096     { PREFIX_TABLE (PREFIX_0F3881) },
7097     { PREFIX_TABLE (PREFIX_0F3882) },
7098     { Bad_Opcode },
7099     { Bad_Opcode },
7100     { Bad_Opcode },
7101     { Bad_Opcode },
7102     { Bad_Opcode },
7103     /* 88 */
7104     { Bad_Opcode },
7105     { Bad_Opcode },
7106     { Bad_Opcode },
7107     { Bad_Opcode },
7108     { Bad_Opcode },
7109     { Bad_Opcode },
7110     { Bad_Opcode },
7111     { Bad_Opcode },
7112     /* 90 */
7113     { Bad_Opcode },
7114     { Bad_Opcode },
7115     { Bad_Opcode },
7116     { Bad_Opcode },
7117     { Bad_Opcode },
7118     { Bad_Opcode },
7119     { Bad_Opcode },
7120     { Bad_Opcode },
7121     /* 98 */
7122     { Bad_Opcode },
7123     { Bad_Opcode },
7124     { Bad_Opcode },
7125     { Bad_Opcode },
7126     { Bad_Opcode },
7127     { Bad_Opcode },
7128     { Bad_Opcode },
7129     { Bad_Opcode },
7130     /* a0 */
7131     { Bad_Opcode },
7132     { Bad_Opcode },
7133     { Bad_Opcode },
7134     { Bad_Opcode },
7135     { Bad_Opcode },
7136     { Bad_Opcode },
7137     { Bad_Opcode },
7138     { Bad_Opcode },
7139     /* a8 */
7140     { Bad_Opcode },
7141     { Bad_Opcode },
7142     { Bad_Opcode },
7143     { Bad_Opcode },
7144     { Bad_Opcode },
7145     { Bad_Opcode },
7146     { Bad_Opcode },
7147     { Bad_Opcode },
7148     /* b0 */
7149     { Bad_Opcode },
7150     { Bad_Opcode },
7151     { Bad_Opcode },
7152     { Bad_Opcode },
7153     { Bad_Opcode },
7154     { Bad_Opcode },
7155     { Bad_Opcode },
7156     { Bad_Opcode },
7157     /* b8 */
7158     { Bad_Opcode },
7159     { Bad_Opcode },
7160     { Bad_Opcode },
7161     { Bad_Opcode },
7162     { Bad_Opcode },
7163     { Bad_Opcode },
7164     { Bad_Opcode },
7165     { Bad_Opcode },
7166     /* c0 */
7167     { Bad_Opcode },
7168     { Bad_Opcode },
7169     { Bad_Opcode },
7170     { Bad_Opcode },
7171     { Bad_Opcode },
7172     { Bad_Opcode },
7173     { Bad_Opcode },
7174     { Bad_Opcode },
7175     /* c8 */
7176     { PREFIX_TABLE (PREFIX_0F38C8) },
7177     { PREFIX_TABLE (PREFIX_0F38C9) },
7178     { PREFIX_TABLE (PREFIX_0F38CA) },
7179     { PREFIX_TABLE (PREFIX_0F38CB) },
7180     { PREFIX_TABLE (PREFIX_0F38CC) },
7181     { PREFIX_TABLE (PREFIX_0F38CD) },
7182     { Bad_Opcode },
7183     { PREFIX_TABLE (PREFIX_0F38CF) },
7184     /* d0 */
7185     { Bad_Opcode },
7186     { Bad_Opcode },
7187     { Bad_Opcode },
7188     { Bad_Opcode },
7189     { Bad_Opcode },
7190     { Bad_Opcode },
7191     { Bad_Opcode },
7192     { Bad_Opcode },
7193     /* d8 */
7194     { Bad_Opcode },
7195     { Bad_Opcode },
7196     { Bad_Opcode },
7197     { PREFIX_TABLE (PREFIX_0F38DB) },
7198     { PREFIX_TABLE (PREFIX_0F38DC) },
7199     { PREFIX_TABLE (PREFIX_0F38DD) },
7200     { PREFIX_TABLE (PREFIX_0F38DE) },
7201     { PREFIX_TABLE (PREFIX_0F38DF) },
7202     /* e0 */
7203     { Bad_Opcode },
7204     { Bad_Opcode },
7205     { Bad_Opcode },
7206     { Bad_Opcode },
7207     { Bad_Opcode },
7208     { Bad_Opcode },
7209     { Bad_Opcode },
7210     { Bad_Opcode },
7211     /* e8 */
7212     { Bad_Opcode },
7213     { Bad_Opcode },
7214     { Bad_Opcode },
7215     { Bad_Opcode },
7216     { Bad_Opcode },
7217     { Bad_Opcode },
7218     { Bad_Opcode },
7219     { Bad_Opcode },
7220     /* f0 */
7221     { PREFIX_TABLE (PREFIX_0F38F0) },
7222     { PREFIX_TABLE (PREFIX_0F38F1) },
7223     { Bad_Opcode },
7224     { Bad_Opcode },
7225     { Bad_Opcode },
7226     { PREFIX_TABLE (PREFIX_0F38F5) },
7227     { PREFIX_TABLE (PREFIX_0F38F6) },
7228     { Bad_Opcode },
7229     /* f8 */
7230     { PREFIX_TABLE (PREFIX_0F38F8) },
7231     { PREFIX_TABLE (PREFIX_0F38F9) },
7232     { Bad_Opcode },
7233     { Bad_Opcode },
7234     { Bad_Opcode },
7235     { Bad_Opcode },
7236     { Bad_Opcode },
7237     { Bad_Opcode },
7238   },
7239   /* THREE_BYTE_0F3A */
7240   {
7241     /* 00 */
7242     { Bad_Opcode },
7243     { Bad_Opcode },
7244     { Bad_Opcode },
7245     { Bad_Opcode },
7246     { Bad_Opcode },
7247     { Bad_Opcode },
7248     { Bad_Opcode },
7249     { Bad_Opcode },
7250     /* 08 */
7251     { PREFIX_TABLE (PREFIX_0F3A08) },
7252     { PREFIX_TABLE (PREFIX_0F3A09) },
7253     { PREFIX_TABLE (PREFIX_0F3A0A) },
7254     { PREFIX_TABLE (PREFIX_0F3A0B) },
7255     { PREFIX_TABLE (PREFIX_0F3A0C) },
7256     { PREFIX_TABLE (PREFIX_0F3A0D) },
7257     { PREFIX_TABLE (PREFIX_0F3A0E) },
7258     { "palignr",        { MX, EM, Ib }, PREFIX_OPCODE },
7259     /* 10 */
7260     { Bad_Opcode },
7261     { Bad_Opcode },
7262     { Bad_Opcode },
7263     { Bad_Opcode },
7264     { PREFIX_TABLE (PREFIX_0F3A14) },
7265     { PREFIX_TABLE (PREFIX_0F3A15) },
7266     { PREFIX_TABLE (PREFIX_0F3A16) },
7267     { PREFIX_TABLE (PREFIX_0F3A17) },
7268     /* 18 */
7269     { Bad_Opcode },
7270     { Bad_Opcode },
7271     { Bad_Opcode },
7272     { Bad_Opcode },
7273     { Bad_Opcode },
7274     { Bad_Opcode },
7275     { Bad_Opcode },
7276     { Bad_Opcode },
7277     /* 20 */
7278     { PREFIX_TABLE (PREFIX_0F3A20) },
7279     { PREFIX_TABLE (PREFIX_0F3A21) },
7280     { PREFIX_TABLE (PREFIX_0F3A22) },
7281     { Bad_Opcode },
7282     { Bad_Opcode },
7283     { Bad_Opcode },
7284     { Bad_Opcode },
7285     { Bad_Opcode },
7286     /* 28 */
7287     { Bad_Opcode },
7288     { Bad_Opcode },
7289     { Bad_Opcode },
7290     { Bad_Opcode },
7291     { Bad_Opcode },
7292     { Bad_Opcode },
7293     { Bad_Opcode },
7294     { Bad_Opcode },
7295     /* 30 */
7296     { Bad_Opcode },
7297     { Bad_Opcode },
7298     { Bad_Opcode },
7299     { Bad_Opcode },
7300     { Bad_Opcode },
7301     { Bad_Opcode },
7302     { Bad_Opcode },
7303     { Bad_Opcode },
7304     /* 38 */
7305     { Bad_Opcode },
7306     { Bad_Opcode },
7307     { Bad_Opcode },
7308     { Bad_Opcode },
7309     { Bad_Opcode },
7310     { Bad_Opcode },
7311     { Bad_Opcode },
7312     { Bad_Opcode },
7313     /* 40 */
7314     { PREFIX_TABLE (PREFIX_0F3A40) },
7315     { PREFIX_TABLE (PREFIX_0F3A41) },
7316     { PREFIX_TABLE (PREFIX_0F3A42) },
7317     { Bad_Opcode },
7318     { PREFIX_TABLE (PREFIX_0F3A44) },
7319     { Bad_Opcode },
7320     { Bad_Opcode },
7321     { Bad_Opcode },
7322     /* 48 */
7323     { Bad_Opcode },
7324     { Bad_Opcode },
7325     { Bad_Opcode },
7326     { Bad_Opcode },
7327     { Bad_Opcode },
7328     { Bad_Opcode },
7329     { Bad_Opcode },
7330     { Bad_Opcode },
7331     /* 50 */
7332     { Bad_Opcode },
7333     { Bad_Opcode },
7334     { Bad_Opcode },
7335     { Bad_Opcode },
7336     { Bad_Opcode },
7337     { Bad_Opcode },
7338     { Bad_Opcode },
7339     { Bad_Opcode },
7340     /* 58 */
7341     { Bad_Opcode },
7342     { Bad_Opcode },
7343     { Bad_Opcode },
7344     { Bad_Opcode },
7345     { Bad_Opcode },
7346     { Bad_Opcode },
7347     { Bad_Opcode },
7348     { Bad_Opcode },
7349     /* 60 */
7350     { PREFIX_TABLE (PREFIX_0F3A60) },
7351     { PREFIX_TABLE (PREFIX_0F3A61) },
7352     { PREFIX_TABLE (PREFIX_0F3A62) },
7353     { PREFIX_TABLE (PREFIX_0F3A63) },
7354     { Bad_Opcode },
7355     { Bad_Opcode },
7356     { Bad_Opcode },
7357     { Bad_Opcode },
7358     /* 68 */
7359     { Bad_Opcode },
7360     { Bad_Opcode },
7361     { Bad_Opcode },
7362     { Bad_Opcode },
7363     { Bad_Opcode },
7364     { Bad_Opcode },
7365     { Bad_Opcode },
7366     { Bad_Opcode },
7367     /* 70 */
7368     { Bad_Opcode },
7369     { Bad_Opcode },
7370     { Bad_Opcode },
7371     { Bad_Opcode },
7372     { Bad_Opcode },
7373     { Bad_Opcode },
7374     { Bad_Opcode },
7375     { Bad_Opcode },
7376     /* 78 */
7377     { Bad_Opcode },
7378     { Bad_Opcode },
7379     { Bad_Opcode },
7380     { Bad_Opcode },
7381     { Bad_Opcode },
7382     { Bad_Opcode },
7383     { Bad_Opcode },
7384     { Bad_Opcode },
7385     /* 80 */
7386     { Bad_Opcode },
7387     { Bad_Opcode },
7388     { Bad_Opcode },
7389     { Bad_Opcode },
7390     { Bad_Opcode },
7391     { Bad_Opcode },
7392     { Bad_Opcode },
7393     { Bad_Opcode },
7394     /* 88 */
7395     { Bad_Opcode },
7396     { Bad_Opcode },
7397     { Bad_Opcode },
7398     { Bad_Opcode },
7399     { Bad_Opcode },
7400     { Bad_Opcode },
7401     { Bad_Opcode },
7402     { Bad_Opcode },
7403     /* 90 */
7404     { Bad_Opcode },
7405     { Bad_Opcode },
7406     { Bad_Opcode },
7407     { Bad_Opcode },
7408     { Bad_Opcode },
7409     { Bad_Opcode },
7410     { Bad_Opcode },
7411     { Bad_Opcode },
7412     /* 98 */
7413     { Bad_Opcode },
7414     { Bad_Opcode },
7415     { Bad_Opcode },
7416     { Bad_Opcode },
7417     { Bad_Opcode },
7418     { Bad_Opcode },
7419     { Bad_Opcode },
7420     { Bad_Opcode },
7421     /* a0 */
7422     { Bad_Opcode },
7423     { Bad_Opcode },
7424     { Bad_Opcode },
7425     { Bad_Opcode },
7426     { Bad_Opcode },
7427     { Bad_Opcode },
7428     { Bad_Opcode },
7429     { Bad_Opcode },
7430     /* a8 */
7431     { Bad_Opcode },
7432     { Bad_Opcode },
7433     { Bad_Opcode },
7434     { Bad_Opcode },
7435     { Bad_Opcode },
7436     { Bad_Opcode },
7437     { Bad_Opcode },
7438     { Bad_Opcode },
7439     /* b0 */
7440     { Bad_Opcode },
7441     { Bad_Opcode },
7442     { Bad_Opcode },
7443     { Bad_Opcode },
7444     { Bad_Opcode },
7445     { Bad_Opcode },
7446     { Bad_Opcode },
7447     { Bad_Opcode },
7448     /* b8 */
7449     { Bad_Opcode },
7450     { Bad_Opcode },
7451     { Bad_Opcode },
7452     { Bad_Opcode },
7453     { Bad_Opcode },
7454     { Bad_Opcode },
7455     { Bad_Opcode },
7456     { Bad_Opcode },
7457     /* c0 */
7458     { Bad_Opcode },
7459     { Bad_Opcode },
7460     { Bad_Opcode },
7461     { Bad_Opcode },
7462     { Bad_Opcode },
7463     { Bad_Opcode },
7464     { Bad_Opcode },
7465     { Bad_Opcode },
7466     /* c8 */
7467     { Bad_Opcode },
7468     { Bad_Opcode },
7469     { Bad_Opcode },
7470     { Bad_Opcode },
7471     { PREFIX_TABLE (PREFIX_0F3ACC) },
7472     { Bad_Opcode },
7473     { PREFIX_TABLE (PREFIX_0F3ACE) },
7474     { PREFIX_TABLE (PREFIX_0F3ACF) },
7475     /* d0 */
7476     { Bad_Opcode },
7477     { Bad_Opcode },
7478     { Bad_Opcode },
7479     { Bad_Opcode },
7480     { Bad_Opcode },
7481     { Bad_Opcode },
7482     { Bad_Opcode },
7483     { Bad_Opcode },
7484     /* d8 */
7485     { Bad_Opcode },
7486     { Bad_Opcode },
7487     { Bad_Opcode },
7488     { Bad_Opcode },
7489     { Bad_Opcode },
7490     { Bad_Opcode },
7491     { Bad_Opcode },
7492     { PREFIX_TABLE (PREFIX_0F3ADF) },
7493     /* e0 */
7494     { Bad_Opcode },
7495     { Bad_Opcode },
7496     { Bad_Opcode },
7497     { Bad_Opcode },
7498     { Bad_Opcode },
7499     { Bad_Opcode },
7500     { Bad_Opcode },
7501     { Bad_Opcode },
7502     /* e8 */
7503     { Bad_Opcode },
7504     { Bad_Opcode },
7505     { Bad_Opcode },
7506     { Bad_Opcode },
7507     { Bad_Opcode },
7508     { Bad_Opcode },
7509     { Bad_Opcode },
7510     { Bad_Opcode },
7511     /* f0 */
7512     { Bad_Opcode },
7513     { Bad_Opcode },
7514     { Bad_Opcode },
7515     { Bad_Opcode },
7516     { Bad_Opcode },
7517     { Bad_Opcode },
7518     { Bad_Opcode },
7519     { Bad_Opcode },
7520     /* f8 */
7521     { Bad_Opcode },
7522     { Bad_Opcode },
7523     { Bad_Opcode },
7524     { Bad_Opcode },
7525     { Bad_Opcode },
7526     { Bad_Opcode },
7527     { Bad_Opcode },
7528     { Bad_Opcode },
7529   },
7530 };
7531
7532 static const struct dis386 xop_table[][256] = {
7533   /* XOP_08 */
7534   {
7535     /* 00 */
7536     { Bad_Opcode },
7537     { Bad_Opcode },
7538     { Bad_Opcode },
7539     { Bad_Opcode },
7540     { Bad_Opcode },
7541     { Bad_Opcode },
7542     { Bad_Opcode },
7543     { Bad_Opcode },
7544     /* 08 */
7545     { Bad_Opcode },
7546     { Bad_Opcode },
7547     { Bad_Opcode },
7548     { Bad_Opcode },
7549     { Bad_Opcode },
7550     { Bad_Opcode },
7551     { Bad_Opcode },
7552     { Bad_Opcode },
7553     /* 10 */
7554     { Bad_Opcode },
7555     { Bad_Opcode },
7556     { Bad_Opcode },
7557     { Bad_Opcode },
7558     { Bad_Opcode },
7559     { Bad_Opcode },
7560     { Bad_Opcode },
7561     { Bad_Opcode },
7562     /* 18 */
7563     { Bad_Opcode },
7564     { Bad_Opcode },
7565     { Bad_Opcode },
7566     { Bad_Opcode },
7567     { Bad_Opcode },
7568     { Bad_Opcode },
7569     { Bad_Opcode },
7570     { Bad_Opcode },
7571     /* 20 */
7572     { Bad_Opcode },
7573     { Bad_Opcode },
7574     { Bad_Opcode },
7575     { Bad_Opcode },
7576     { Bad_Opcode },
7577     { Bad_Opcode },
7578     { Bad_Opcode },
7579     { Bad_Opcode },
7580     /* 28 */
7581     { Bad_Opcode },
7582     { Bad_Opcode },
7583     { Bad_Opcode },
7584     { Bad_Opcode },
7585     { Bad_Opcode },
7586     { Bad_Opcode },
7587     { Bad_Opcode },
7588     { Bad_Opcode },
7589     /* 30 */
7590     { Bad_Opcode },
7591     { Bad_Opcode },
7592     { Bad_Opcode },
7593     { Bad_Opcode },
7594     { Bad_Opcode },
7595     { Bad_Opcode },
7596     { Bad_Opcode },
7597     { Bad_Opcode },
7598     /* 38 */
7599     { Bad_Opcode },
7600     { Bad_Opcode },
7601     { Bad_Opcode },
7602     { Bad_Opcode },
7603     { Bad_Opcode },
7604     { Bad_Opcode },
7605     { Bad_Opcode },
7606     { Bad_Opcode },
7607     /* 40 */
7608     { Bad_Opcode },
7609     { Bad_Opcode },
7610     { Bad_Opcode },
7611     { Bad_Opcode },
7612     { Bad_Opcode },
7613     { Bad_Opcode },
7614     { Bad_Opcode },
7615     { Bad_Opcode },
7616     /* 48 */
7617     { Bad_Opcode },
7618     { Bad_Opcode },
7619     { Bad_Opcode },
7620     { Bad_Opcode },
7621     { Bad_Opcode },
7622     { Bad_Opcode },
7623     { Bad_Opcode },
7624     { Bad_Opcode },
7625     /* 50 */
7626     { Bad_Opcode },
7627     { Bad_Opcode },
7628     { Bad_Opcode },
7629     { Bad_Opcode },
7630     { Bad_Opcode },
7631     { Bad_Opcode },
7632     { Bad_Opcode },
7633     { Bad_Opcode },
7634     /* 58 */
7635     { Bad_Opcode },
7636     { Bad_Opcode },
7637     { Bad_Opcode },
7638     { Bad_Opcode },
7639     { Bad_Opcode },
7640     { Bad_Opcode },
7641     { Bad_Opcode },
7642     { Bad_Opcode },
7643     /* 60 */
7644     { Bad_Opcode },
7645     { Bad_Opcode },
7646     { Bad_Opcode },
7647     { Bad_Opcode },
7648     { Bad_Opcode },
7649     { Bad_Opcode },
7650     { Bad_Opcode },
7651     { Bad_Opcode },
7652     /* 68 */
7653     { Bad_Opcode },
7654     { Bad_Opcode },
7655     { Bad_Opcode },
7656     { Bad_Opcode },
7657     { Bad_Opcode },
7658     { Bad_Opcode },
7659     { Bad_Opcode },
7660     { Bad_Opcode },
7661     /* 70 */
7662     { Bad_Opcode },
7663     { Bad_Opcode },
7664     { Bad_Opcode },
7665     { Bad_Opcode },
7666     { Bad_Opcode },
7667     { Bad_Opcode },
7668     { Bad_Opcode },
7669     { Bad_Opcode },
7670     /* 78 */
7671     { Bad_Opcode },
7672     { Bad_Opcode },
7673     { Bad_Opcode },
7674     { Bad_Opcode },
7675     { Bad_Opcode },
7676     { Bad_Opcode },
7677     { Bad_Opcode },
7678     { Bad_Opcode },
7679     /* 80 */
7680     { Bad_Opcode },
7681     { Bad_Opcode },
7682     { Bad_Opcode },
7683     { Bad_Opcode },
7684     { Bad_Opcode },
7685     { "vpmacssww",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7686     { "vpmacsswd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7687     { "vpmacssdql",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7688     /* 88 */
7689     { Bad_Opcode },
7690     { Bad_Opcode },
7691     { Bad_Opcode },
7692     { Bad_Opcode },
7693     { Bad_Opcode },
7694     { Bad_Opcode },
7695     { "vpmacssdd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7696     { "vpmacssdqh",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7697     /* 90 */
7698     { Bad_Opcode },
7699     { Bad_Opcode },
7700     { Bad_Opcode },
7701     { Bad_Opcode },
7702     { Bad_Opcode },
7703     { "vpmacsww",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7704     { "vpmacswd",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7705     { "vpmacsdql",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7706     /* 98 */
7707     { Bad_Opcode },
7708     { Bad_Opcode },
7709     { Bad_Opcode },
7710     { Bad_Opcode },
7711     { Bad_Opcode },
7712     { Bad_Opcode },
7713     { "vpmacsdd",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7714     { "vpmacsdqh",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7715     /* a0 */
7716     { Bad_Opcode },
7717     { Bad_Opcode },
7718     { "vpcmov",         { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7719     { "vpperm",         { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7720     { Bad_Opcode },
7721     { Bad_Opcode },
7722     { "vpmadcsswd",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7723     { Bad_Opcode },
7724     /* a8 */
7725     { Bad_Opcode },
7726     { Bad_Opcode },
7727     { Bad_Opcode },
7728     { Bad_Opcode },
7729     { Bad_Opcode },
7730     { Bad_Opcode },
7731     { Bad_Opcode },
7732     { Bad_Opcode },
7733     /* b0 */
7734     { Bad_Opcode },
7735     { Bad_Opcode },
7736     { Bad_Opcode },
7737     { Bad_Opcode },
7738     { Bad_Opcode },
7739     { Bad_Opcode },
7740     { "vpmadcswd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7741     { Bad_Opcode },
7742     /* b8 */
7743     { Bad_Opcode },
7744     { Bad_Opcode },
7745     { Bad_Opcode },
7746     { Bad_Opcode },
7747     { Bad_Opcode },
7748     { Bad_Opcode },
7749     { Bad_Opcode },
7750     { Bad_Opcode },
7751     /* c0 */
7752     { "vprotb",         { XM, Vex_2src_1, Ib }, 0 },
7753     { "vprotw",         { XM, Vex_2src_1, Ib }, 0 },
7754     { "vprotd",         { XM, Vex_2src_1, Ib }, 0 },
7755     { "vprotq",         { XM, Vex_2src_1, Ib }, 0 },
7756     { Bad_Opcode },
7757     { Bad_Opcode },
7758     { Bad_Opcode },
7759     { Bad_Opcode },
7760     /* c8 */
7761     { Bad_Opcode },
7762     { Bad_Opcode },
7763     { Bad_Opcode },
7764     { Bad_Opcode },
7765     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
7766     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
7767     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
7768     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
7769     /* d0 */
7770     { Bad_Opcode },
7771     { Bad_Opcode },
7772     { Bad_Opcode },
7773     { Bad_Opcode },
7774     { Bad_Opcode },
7775     { Bad_Opcode },
7776     { Bad_Opcode },
7777     { Bad_Opcode },
7778     /* d8 */
7779     { Bad_Opcode },
7780     { Bad_Opcode },
7781     { Bad_Opcode },
7782     { Bad_Opcode },
7783     { Bad_Opcode },
7784     { Bad_Opcode },
7785     { Bad_Opcode },
7786     { Bad_Opcode },
7787     /* e0 */
7788     { Bad_Opcode },
7789     { Bad_Opcode },
7790     { Bad_Opcode },
7791     { Bad_Opcode },
7792     { Bad_Opcode },
7793     { Bad_Opcode },
7794     { Bad_Opcode },
7795     { Bad_Opcode },
7796     /* e8 */
7797     { Bad_Opcode },
7798     { Bad_Opcode },
7799     { Bad_Opcode },
7800     { Bad_Opcode },
7801     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
7802     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
7803     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
7804     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
7805     /* f0 */
7806     { Bad_Opcode },
7807     { Bad_Opcode },
7808     { Bad_Opcode },
7809     { Bad_Opcode },
7810     { Bad_Opcode },
7811     { Bad_Opcode },
7812     { Bad_Opcode },
7813     { Bad_Opcode },
7814     /* f8 */
7815     { Bad_Opcode },
7816     { Bad_Opcode },
7817     { Bad_Opcode },
7818     { Bad_Opcode },
7819     { Bad_Opcode },
7820     { Bad_Opcode },
7821     { Bad_Opcode },
7822     { Bad_Opcode },
7823   },
7824   /* XOP_09 */
7825   {
7826     /* 00 */
7827     { Bad_Opcode },
7828     { REG_TABLE (REG_XOP_TBM_01) },
7829     { REG_TABLE (REG_XOP_TBM_02) },
7830     { Bad_Opcode },
7831     { Bad_Opcode },
7832     { Bad_Opcode },
7833     { Bad_Opcode },
7834     { Bad_Opcode },
7835     /* 08 */
7836     { Bad_Opcode },
7837     { Bad_Opcode },
7838     { Bad_Opcode },
7839     { Bad_Opcode },
7840     { Bad_Opcode },
7841     { Bad_Opcode },
7842     { Bad_Opcode },
7843     { Bad_Opcode },
7844     /* 10 */
7845     { Bad_Opcode },
7846     { Bad_Opcode },
7847     { REG_TABLE (REG_XOP_LWPCB) },
7848     { Bad_Opcode },
7849     { Bad_Opcode },
7850     { Bad_Opcode },
7851     { Bad_Opcode },
7852     { Bad_Opcode },
7853     /* 18 */
7854     { Bad_Opcode },
7855     { Bad_Opcode },
7856     { Bad_Opcode },
7857     { Bad_Opcode },
7858     { Bad_Opcode },
7859     { Bad_Opcode },
7860     { Bad_Opcode },
7861     { Bad_Opcode },
7862     /* 20 */
7863     { Bad_Opcode },
7864     { Bad_Opcode },
7865     { Bad_Opcode },
7866     { Bad_Opcode },
7867     { Bad_Opcode },
7868     { Bad_Opcode },
7869     { Bad_Opcode },
7870     { Bad_Opcode },
7871     /* 28 */
7872     { Bad_Opcode },
7873     { Bad_Opcode },
7874     { Bad_Opcode },
7875     { Bad_Opcode },
7876     { Bad_Opcode },
7877     { Bad_Opcode },
7878     { Bad_Opcode },
7879     { Bad_Opcode },
7880     /* 30 */
7881     { Bad_Opcode },
7882     { Bad_Opcode },
7883     { Bad_Opcode },
7884     { Bad_Opcode },
7885     { Bad_Opcode },
7886     { Bad_Opcode },
7887     { Bad_Opcode },
7888     { Bad_Opcode },
7889     /* 38 */
7890     { Bad_Opcode },
7891     { Bad_Opcode },
7892     { Bad_Opcode },
7893     { Bad_Opcode },
7894     { Bad_Opcode },
7895     { Bad_Opcode },
7896     { Bad_Opcode },
7897     { Bad_Opcode },
7898     /* 40 */
7899     { Bad_Opcode },
7900     { Bad_Opcode },
7901     { Bad_Opcode },
7902     { Bad_Opcode },
7903     { Bad_Opcode },
7904     { Bad_Opcode },
7905     { Bad_Opcode },
7906     { Bad_Opcode },
7907     /* 48 */
7908     { Bad_Opcode },
7909     { Bad_Opcode },
7910     { Bad_Opcode },
7911     { Bad_Opcode },
7912     { Bad_Opcode },
7913     { Bad_Opcode },
7914     { Bad_Opcode },
7915     { Bad_Opcode },
7916     /* 50 */
7917     { Bad_Opcode },
7918     { Bad_Opcode },
7919     { Bad_Opcode },
7920     { Bad_Opcode },
7921     { Bad_Opcode },
7922     { Bad_Opcode },
7923     { Bad_Opcode },
7924     { Bad_Opcode },
7925     /* 58 */
7926     { Bad_Opcode },
7927     { Bad_Opcode },
7928     { Bad_Opcode },
7929     { Bad_Opcode },
7930     { Bad_Opcode },
7931     { Bad_Opcode },
7932     { Bad_Opcode },
7933     { Bad_Opcode },
7934     /* 60 */
7935     { Bad_Opcode },
7936     { Bad_Opcode },
7937     { Bad_Opcode },
7938     { Bad_Opcode },
7939     { Bad_Opcode },
7940     { Bad_Opcode },
7941     { Bad_Opcode },
7942     { Bad_Opcode },
7943     /* 68 */
7944     { Bad_Opcode },
7945     { Bad_Opcode },
7946     { Bad_Opcode },
7947     { Bad_Opcode },
7948     { Bad_Opcode },
7949     { Bad_Opcode },
7950     { Bad_Opcode },
7951     { Bad_Opcode },
7952     /* 70 */
7953     { Bad_Opcode },
7954     { Bad_Opcode },
7955     { Bad_Opcode },
7956     { Bad_Opcode },
7957     { Bad_Opcode },
7958     { Bad_Opcode },
7959     { Bad_Opcode },
7960     { Bad_Opcode },
7961     /* 78 */
7962     { Bad_Opcode },
7963     { Bad_Opcode },
7964     { Bad_Opcode },
7965     { Bad_Opcode },
7966     { Bad_Opcode },
7967     { Bad_Opcode },
7968     { Bad_Opcode },
7969     { Bad_Opcode },
7970     /* 80 */
7971     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
7972     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
7973     { "vfrczss",        { XM, EXd }, 0 },
7974     { "vfrczsd",        { XM, EXq }, 0 },
7975     { Bad_Opcode },
7976     { Bad_Opcode },
7977     { Bad_Opcode },
7978     { Bad_Opcode },
7979     /* 88 */
7980     { Bad_Opcode },
7981     { Bad_Opcode },
7982     { Bad_Opcode },
7983     { Bad_Opcode },
7984     { Bad_Opcode },
7985     { Bad_Opcode },
7986     { Bad_Opcode },
7987     { Bad_Opcode },
7988     /* 90 */
7989     { "vprotb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7990     { "vprotw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7991     { "vprotd",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7992     { "vprotq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7993     { "vpshlb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7994     { "vpshlw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7995     { "vpshld",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7996     { "vpshlq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7997     /* 98 */
7998     { "vpshab",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7999     { "vpshaw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8000     { "vpshad",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8001     { "vpshaq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8002     { Bad_Opcode },
8003     { Bad_Opcode },
8004     { Bad_Opcode },
8005     { Bad_Opcode },
8006     /* a0 */
8007     { Bad_Opcode },
8008     { Bad_Opcode },
8009     { Bad_Opcode },
8010     { Bad_Opcode },
8011     { Bad_Opcode },
8012     { Bad_Opcode },
8013     { Bad_Opcode },
8014     { Bad_Opcode },
8015     /* a8 */
8016     { Bad_Opcode },
8017     { Bad_Opcode },
8018     { Bad_Opcode },
8019     { Bad_Opcode },
8020     { Bad_Opcode },
8021     { Bad_Opcode },
8022     { Bad_Opcode },
8023     { Bad_Opcode },
8024     /* b0 */
8025     { Bad_Opcode },
8026     { Bad_Opcode },
8027     { Bad_Opcode },
8028     { Bad_Opcode },
8029     { Bad_Opcode },
8030     { Bad_Opcode },
8031     { Bad_Opcode },
8032     { Bad_Opcode },
8033     /* b8 */
8034     { Bad_Opcode },
8035     { Bad_Opcode },
8036     { Bad_Opcode },
8037     { Bad_Opcode },
8038     { Bad_Opcode },
8039     { Bad_Opcode },
8040     { Bad_Opcode },
8041     { Bad_Opcode },
8042     /* c0 */
8043     { Bad_Opcode },
8044     { "vphaddbw",       { XM, EXxmm }, 0 },
8045     { "vphaddbd",       { XM, EXxmm }, 0 },
8046     { "vphaddbq",       { XM, EXxmm }, 0 },
8047     { Bad_Opcode },
8048     { Bad_Opcode },
8049     { "vphaddwd",       { XM, EXxmm }, 0 },
8050     { "vphaddwq",       { XM, EXxmm }, 0 },
8051     /* c8 */
8052     { Bad_Opcode },
8053     { Bad_Opcode },
8054     { Bad_Opcode },
8055     { "vphadddq",       { XM, EXxmm }, 0 },
8056     { Bad_Opcode },
8057     { Bad_Opcode },
8058     { Bad_Opcode },
8059     { Bad_Opcode },
8060     /* d0 */
8061     { Bad_Opcode },
8062     { "vphaddubw",      { XM, EXxmm }, 0 },
8063     { "vphaddubd",      { XM, EXxmm }, 0 },
8064     { "vphaddubq",      { XM, EXxmm }, 0 },
8065     { Bad_Opcode },
8066     { Bad_Opcode },
8067     { "vphadduwd",      { XM, EXxmm }, 0 },
8068     { "vphadduwq",      { XM, EXxmm }, 0 },
8069     /* d8 */
8070     { Bad_Opcode },
8071     { Bad_Opcode },
8072     { Bad_Opcode },
8073     { "vphaddudq",      { XM, EXxmm }, 0 },
8074     { Bad_Opcode },
8075     { Bad_Opcode },
8076     { Bad_Opcode },
8077     { Bad_Opcode },
8078     /* e0 */
8079     { Bad_Opcode },
8080     { "vphsubbw",       { XM, EXxmm }, 0 },
8081     { "vphsubwd",       { XM, EXxmm }, 0 },
8082     { "vphsubdq",       { XM, EXxmm }, 0 },
8083     { Bad_Opcode },
8084     { Bad_Opcode },
8085     { Bad_Opcode },
8086     { Bad_Opcode },
8087     /* e8 */
8088     { Bad_Opcode },
8089     { Bad_Opcode },
8090     { Bad_Opcode },
8091     { Bad_Opcode },
8092     { Bad_Opcode },
8093     { Bad_Opcode },
8094     { Bad_Opcode },
8095     { Bad_Opcode },
8096     /* f0 */
8097     { Bad_Opcode },
8098     { Bad_Opcode },
8099     { Bad_Opcode },
8100     { Bad_Opcode },
8101     { Bad_Opcode },
8102     { Bad_Opcode },
8103     { Bad_Opcode },
8104     { Bad_Opcode },
8105     /* f8 */
8106     { Bad_Opcode },
8107     { Bad_Opcode },
8108     { Bad_Opcode },
8109     { Bad_Opcode },
8110     { Bad_Opcode },
8111     { Bad_Opcode },
8112     { Bad_Opcode },
8113     { Bad_Opcode },
8114   },
8115   /* XOP_0A */
8116   {
8117     /* 00 */
8118     { Bad_Opcode },
8119     { Bad_Opcode },
8120     { Bad_Opcode },
8121     { Bad_Opcode },
8122     { Bad_Opcode },
8123     { Bad_Opcode },
8124     { Bad_Opcode },
8125     { Bad_Opcode },
8126     /* 08 */
8127     { Bad_Opcode },
8128     { Bad_Opcode },
8129     { Bad_Opcode },
8130     { Bad_Opcode },
8131     { Bad_Opcode },
8132     { Bad_Opcode },
8133     { Bad_Opcode },
8134     { Bad_Opcode },
8135     /* 10 */
8136     { "bextr",  { Gv, Ev, Iq }, 0 },
8137     { Bad_Opcode },
8138     { REG_TABLE (REG_XOP_LWP) },
8139     { Bad_Opcode },
8140     { Bad_Opcode },
8141     { Bad_Opcode },
8142     { Bad_Opcode },
8143     { Bad_Opcode },
8144     /* 18 */
8145     { Bad_Opcode },
8146     { Bad_Opcode },
8147     { Bad_Opcode },
8148     { Bad_Opcode },
8149     { Bad_Opcode },
8150     { Bad_Opcode },
8151     { Bad_Opcode },
8152     { Bad_Opcode },
8153     /* 20 */
8154     { Bad_Opcode },
8155     { Bad_Opcode },
8156     { Bad_Opcode },
8157     { Bad_Opcode },
8158     { Bad_Opcode },
8159     { Bad_Opcode },
8160     { Bad_Opcode },
8161     { Bad_Opcode },
8162     /* 28 */
8163     { Bad_Opcode },
8164     { Bad_Opcode },
8165     { Bad_Opcode },
8166     { Bad_Opcode },
8167     { Bad_Opcode },
8168     { Bad_Opcode },
8169     { Bad_Opcode },
8170     { Bad_Opcode },
8171     /* 30 */
8172     { Bad_Opcode },
8173     { Bad_Opcode },
8174     { Bad_Opcode },
8175     { Bad_Opcode },
8176     { Bad_Opcode },
8177     { Bad_Opcode },
8178     { Bad_Opcode },
8179     { Bad_Opcode },
8180     /* 38 */
8181     { Bad_Opcode },
8182     { Bad_Opcode },
8183     { Bad_Opcode },
8184     { Bad_Opcode },
8185     { Bad_Opcode },
8186     { Bad_Opcode },
8187     { Bad_Opcode },
8188     { Bad_Opcode },
8189     /* 40 */
8190     { Bad_Opcode },
8191     { Bad_Opcode },
8192     { Bad_Opcode },
8193     { Bad_Opcode },
8194     { Bad_Opcode },
8195     { Bad_Opcode },
8196     { Bad_Opcode },
8197     { Bad_Opcode },
8198     /* 48 */
8199     { Bad_Opcode },
8200     { Bad_Opcode },
8201     { Bad_Opcode },
8202     { Bad_Opcode },
8203     { Bad_Opcode },
8204     { Bad_Opcode },
8205     { Bad_Opcode },
8206     { Bad_Opcode },
8207     /* 50 */
8208     { Bad_Opcode },
8209     { Bad_Opcode },
8210     { Bad_Opcode },
8211     { Bad_Opcode },
8212     { Bad_Opcode },
8213     { Bad_Opcode },
8214     { Bad_Opcode },
8215     { Bad_Opcode },
8216     /* 58 */
8217     { Bad_Opcode },
8218     { Bad_Opcode },
8219     { Bad_Opcode },
8220     { Bad_Opcode },
8221     { Bad_Opcode },
8222     { Bad_Opcode },
8223     { Bad_Opcode },
8224     { Bad_Opcode },
8225     /* 60 */
8226     { Bad_Opcode },
8227     { Bad_Opcode },
8228     { Bad_Opcode },
8229     { Bad_Opcode },
8230     { Bad_Opcode },
8231     { Bad_Opcode },
8232     { Bad_Opcode },
8233     { Bad_Opcode },
8234     /* 68 */
8235     { Bad_Opcode },
8236     { Bad_Opcode },
8237     { Bad_Opcode },
8238     { Bad_Opcode },
8239     { Bad_Opcode },
8240     { Bad_Opcode },
8241     { Bad_Opcode },
8242     { Bad_Opcode },
8243     /* 70 */
8244     { Bad_Opcode },
8245     { Bad_Opcode },
8246     { Bad_Opcode },
8247     { Bad_Opcode },
8248     { Bad_Opcode },
8249     { Bad_Opcode },
8250     { Bad_Opcode },
8251     { Bad_Opcode },
8252     /* 78 */
8253     { Bad_Opcode },
8254     { Bad_Opcode },
8255     { Bad_Opcode },
8256     { Bad_Opcode },
8257     { Bad_Opcode },
8258     { Bad_Opcode },
8259     { Bad_Opcode },
8260     { Bad_Opcode },
8261     /* 80 */
8262     { Bad_Opcode },
8263     { Bad_Opcode },
8264     { Bad_Opcode },
8265     { Bad_Opcode },
8266     { Bad_Opcode },
8267     { Bad_Opcode },
8268     { Bad_Opcode },
8269     { Bad_Opcode },
8270     /* 88 */
8271     { Bad_Opcode },
8272     { Bad_Opcode },
8273     { Bad_Opcode },
8274     { Bad_Opcode },
8275     { Bad_Opcode },
8276     { Bad_Opcode },
8277     { Bad_Opcode },
8278     { Bad_Opcode },
8279     /* 90 */
8280     { Bad_Opcode },
8281     { Bad_Opcode },
8282     { Bad_Opcode },
8283     { Bad_Opcode },
8284     { Bad_Opcode },
8285     { Bad_Opcode },
8286     { Bad_Opcode },
8287     { Bad_Opcode },
8288     /* 98 */
8289     { Bad_Opcode },
8290     { Bad_Opcode },
8291     { Bad_Opcode },
8292     { Bad_Opcode },
8293     { Bad_Opcode },
8294     { Bad_Opcode },
8295     { Bad_Opcode },
8296     { Bad_Opcode },
8297     /* a0 */
8298     { Bad_Opcode },
8299     { Bad_Opcode },
8300     { Bad_Opcode },
8301     { Bad_Opcode },
8302     { Bad_Opcode },
8303     { Bad_Opcode },
8304     { Bad_Opcode },
8305     { Bad_Opcode },
8306     /* a8 */
8307     { Bad_Opcode },
8308     { Bad_Opcode },
8309     { Bad_Opcode },
8310     { Bad_Opcode },
8311     { Bad_Opcode },
8312     { Bad_Opcode },
8313     { Bad_Opcode },
8314     { Bad_Opcode },
8315     /* b0 */
8316     { Bad_Opcode },
8317     { Bad_Opcode },
8318     { Bad_Opcode },
8319     { Bad_Opcode },
8320     { Bad_Opcode },
8321     { Bad_Opcode },
8322     { Bad_Opcode },
8323     { Bad_Opcode },
8324     /* b8 */
8325     { Bad_Opcode },
8326     { Bad_Opcode },
8327     { Bad_Opcode },
8328     { Bad_Opcode },
8329     { Bad_Opcode },
8330     { Bad_Opcode },
8331     { Bad_Opcode },
8332     { Bad_Opcode },
8333     /* c0 */
8334     { Bad_Opcode },
8335     { Bad_Opcode },
8336     { Bad_Opcode },
8337     { Bad_Opcode },
8338     { Bad_Opcode },
8339     { Bad_Opcode },
8340     { Bad_Opcode },
8341     { Bad_Opcode },
8342     /* c8 */
8343     { Bad_Opcode },
8344     { Bad_Opcode },
8345     { Bad_Opcode },
8346     { Bad_Opcode },
8347     { Bad_Opcode },
8348     { Bad_Opcode },
8349     { Bad_Opcode },
8350     { Bad_Opcode },
8351     /* d0 */
8352     { Bad_Opcode },
8353     { Bad_Opcode },
8354     { Bad_Opcode },
8355     { Bad_Opcode },
8356     { Bad_Opcode },
8357     { Bad_Opcode },
8358     { Bad_Opcode },
8359     { Bad_Opcode },
8360     /* d8 */
8361     { Bad_Opcode },
8362     { Bad_Opcode },
8363     { Bad_Opcode },
8364     { Bad_Opcode },
8365     { Bad_Opcode },
8366     { Bad_Opcode },
8367     { Bad_Opcode },
8368     { Bad_Opcode },
8369     /* e0 */
8370     { Bad_Opcode },
8371     { Bad_Opcode },
8372     { Bad_Opcode },
8373     { Bad_Opcode },
8374     { Bad_Opcode },
8375     { Bad_Opcode },
8376     { Bad_Opcode },
8377     { Bad_Opcode },
8378     /* e8 */
8379     { Bad_Opcode },
8380     { Bad_Opcode },
8381     { Bad_Opcode },
8382     { Bad_Opcode },
8383     { Bad_Opcode },
8384     { Bad_Opcode },
8385     { Bad_Opcode },
8386     { Bad_Opcode },
8387     /* f0 */
8388     { Bad_Opcode },
8389     { Bad_Opcode },
8390     { Bad_Opcode },
8391     { Bad_Opcode },
8392     { Bad_Opcode },
8393     { Bad_Opcode },
8394     { Bad_Opcode },
8395     { Bad_Opcode },
8396     /* f8 */
8397     { Bad_Opcode },
8398     { Bad_Opcode },
8399     { Bad_Opcode },
8400     { Bad_Opcode },
8401     { Bad_Opcode },
8402     { Bad_Opcode },
8403     { Bad_Opcode },
8404     { Bad_Opcode },
8405   },
8406 };
8407
8408 static const struct dis386 vex_table[][256] = {
8409   /* VEX_0F */
8410   {
8411     /* 00 */
8412     { Bad_Opcode },
8413     { Bad_Opcode },
8414     { Bad_Opcode },
8415     { Bad_Opcode },
8416     { Bad_Opcode },
8417     { Bad_Opcode },
8418     { Bad_Opcode },
8419     { Bad_Opcode },
8420     /* 08 */
8421     { Bad_Opcode },
8422     { Bad_Opcode },
8423     { Bad_Opcode },
8424     { Bad_Opcode },
8425     { Bad_Opcode },
8426     { Bad_Opcode },
8427     { Bad_Opcode },
8428     { Bad_Opcode },
8429     /* 10 */
8430     { PREFIX_TABLE (PREFIX_VEX_0F10) },
8431     { PREFIX_TABLE (PREFIX_VEX_0F11) },
8432     { PREFIX_TABLE (PREFIX_VEX_0F12) },
8433     { MOD_TABLE (MOD_VEX_0F13) },
8434     { "vunpcklpX",      { XM, Vex, EXx }, 0 },
8435     { "vunpckhpX",      { XM, Vex, EXx }, 0 },
8436     { PREFIX_TABLE (PREFIX_VEX_0F16) },
8437     { MOD_TABLE (MOD_VEX_0F17) },
8438     /* 18 */
8439     { Bad_Opcode },
8440     { Bad_Opcode },
8441     { Bad_Opcode },
8442     { Bad_Opcode },
8443     { Bad_Opcode },
8444     { Bad_Opcode },
8445     { Bad_Opcode },
8446     { Bad_Opcode },
8447     /* 20 */
8448     { Bad_Opcode },
8449     { Bad_Opcode },
8450     { Bad_Opcode },
8451     { Bad_Opcode },
8452     { Bad_Opcode },
8453     { Bad_Opcode },
8454     { Bad_Opcode },
8455     { Bad_Opcode },
8456     /* 28 */
8457     { "vmovapX",        { XM, EXx }, 0 },
8458     { "vmovapX",        { EXxS, XM }, 0 },
8459     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8460     { MOD_TABLE (MOD_VEX_0F2B) },
8461     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8462     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8463     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8464     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8465     /* 30 */
8466     { Bad_Opcode },
8467     { Bad_Opcode },
8468     { Bad_Opcode },
8469     { Bad_Opcode },
8470     { Bad_Opcode },
8471     { Bad_Opcode },
8472     { Bad_Opcode },
8473     { Bad_Opcode },
8474     /* 38 */
8475     { Bad_Opcode },
8476     { Bad_Opcode },
8477     { Bad_Opcode },
8478     { Bad_Opcode },
8479     { Bad_Opcode },
8480     { Bad_Opcode },
8481     { Bad_Opcode },
8482     { Bad_Opcode },
8483     /* 40 */
8484     { Bad_Opcode },
8485     { PREFIX_TABLE (PREFIX_VEX_0F41) },
8486     { PREFIX_TABLE (PREFIX_VEX_0F42) },
8487     { Bad_Opcode },
8488     { PREFIX_TABLE (PREFIX_VEX_0F44) },
8489     { PREFIX_TABLE (PREFIX_VEX_0F45) },
8490     { PREFIX_TABLE (PREFIX_VEX_0F46) },
8491     { PREFIX_TABLE (PREFIX_VEX_0F47) },
8492     /* 48 */
8493     { Bad_Opcode },
8494     { Bad_Opcode },
8495     { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8496     { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8497     { Bad_Opcode },
8498     { Bad_Opcode },
8499     { Bad_Opcode },
8500     { Bad_Opcode },
8501     /* 50 */
8502     { MOD_TABLE (MOD_VEX_0F50) },
8503     { PREFIX_TABLE (PREFIX_VEX_0F51) },
8504     { PREFIX_TABLE (PREFIX_VEX_0F52) },
8505     { PREFIX_TABLE (PREFIX_VEX_0F53) },
8506     { "vandpX",         { XM, Vex, EXx }, 0 },
8507     { "vandnpX",        { XM, Vex, EXx }, 0 },
8508     { "vorpX",          { XM, Vex, EXx }, 0 },
8509     { "vxorpX",         { XM, Vex, EXx }, 0 },
8510     /* 58 */
8511     { PREFIX_TABLE (PREFIX_VEX_0F58) },
8512     { PREFIX_TABLE (PREFIX_VEX_0F59) },
8513     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8514     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8515     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8516     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8517     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8518     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8519     /* 60 */
8520     { PREFIX_TABLE (PREFIX_VEX_0F60) },
8521     { PREFIX_TABLE (PREFIX_VEX_0F61) },
8522     { PREFIX_TABLE (PREFIX_VEX_0F62) },
8523     { PREFIX_TABLE (PREFIX_VEX_0F63) },
8524     { PREFIX_TABLE (PREFIX_VEX_0F64) },
8525     { PREFIX_TABLE (PREFIX_VEX_0F65) },
8526     { PREFIX_TABLE (PREFIX_VEX_0F66) },
8527     { PREFIX_TABLE (PREFIX_VEX_0F67) },
8528     /* 68 */
8529     { PREFIX_TABLE (PREFIX_VEX_0F68) },
8530     { PREFIX_TABLE (PREFIX_VEX_0F69) },
8531     { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8532     { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8533     { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8534     { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8535     { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8536     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8537     /* 70 */
8538     { PREFIX_TABLE (PREFIX_VEX_0F70) },
8539     { REG_TABLE (REG_VEX_0F71) },
8540     { REG_TABLE (REG_VEX_0F72) },
8541     { REG_TABLE (REG_VEX_0F73) },
8542     { PREFIX_TABLE (PREFIX_VEX_0F74) },
8543     { PREFIX_TABLE (PREFIX_VEX_0F75) },
8544     { PREFIX_TABLE (PREFIX_VEX_0F76) },
8545     { PREFIX_TABLE (PREFIX_VEX_0F77) },
8546     /* 78 */
8547     { Bad_Opcode },
8548     { Bad_Opcode },
8549     { Bad_Opcode },
8550     { Bad_Opcode },
8551     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8552     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8553     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8554     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8555     /* 80 */
8556     { Bad_Opcode },
8557     { Bad_Opcode },
8558     { Bad_Opcode },
8559     { Bad_Opcode },
8560     { Bad_Opcode },
8561     { Bad_Opcode },
8562     { Bad_Opcode },
8563     { Bad_Opcode },
8564     /* 88 */
8565     { Bad_Opcode },
8566     { Bad_Opcode },
8567     { Bad_Opcode },
8568     { Bad_Opcode },
8569     { Bad_Opcode },
8570     { Bad_Opcode },
8571     { Bad_Opcode },
8572     { Bad_Opcode },
8573     /* 90 */
8574     { PREFIX_TABLE (PREFIX_VEX_0F90) },
8575     { PREFIX_TABLE (PREFIX_VEX_0F91) },
8576     { PREFIX_TABLE (PREFIX_VEX_0F92) },
8577     { PREFIX_TABLE (PREFIX_VEX_0F93) },
8578     { Bad_Opcode },
8579     { Bad_Opcode },
8580     { Bad_Opcode },
8581     { Bad_Opcode },
8582     /* 98 */
8583     { PREFIX_TABLE (PREFIX_VEX_0F98) },
8584     { PREFIX_TABLE (PREFIX_VEX_0F99) },
8585     { Bad_Opcode },
8586     { Bad_Opcode },
8587     { Bad_Opcode },
8588     { Bad_Opcode },
8589     { Bad_Opcode },
8590     { Bad_Opcode },
8591     /* a0 */
8592     { Bad_Opcode },
8593     { Bad_Opcode },
8594     { Bad_Opcode },
8595     { Bad_Opcode },
8596     { Bad_Opcode },
8597     { Bad_Opcode },
8598     { Bad_Opcode },
8599     { Bad_Opcode },
8600     /* a8 */
8601     { Bad_Opcode },
8602     { Bad_Opcode },
8603     { Bad_Opcode },
8604     { Bad_Opcode },
8605     { Bad_Opcode },
8606     { Bad_Opcode },
8607     { REG_TABLE (REG_VEX_0FAE) },
8608     { Bad_Opcode },
8609     /* b0 */
8610     { Bad_Opcode },
8611     { Bad_Opcode },
8612     { Bad_Opcode },
8613     { Bad_Opcode },
8614     { Bad_Opcode },
8615     { Bad_Opcode },
8616     { Bad_Opcode },
8617     { Bad_Opcode },
8618     /* b8 */
8619     { Bad_Opcode },
8620     { Bad_Opcode },
8621     { Bad_Opcode },
8622     { Bad_Opcode },
8623     { Bad_Opcode },
8624     { Bad_Opcode },
8625     { Bad_Opcode },
8626     { Bad_Opcode },
8627     /* c0 */
8628     { Bad_Opcode },
8629     { Bad_Opcode },
8630     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8631     { Bad_Opcode },
8632     { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8633     { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8634     { "vshufpX",        { XM, Vex, EXx, Ib }, 0 },
8635     { Bad_Opcode },
8636     /* c8 */
8637     { Bad_Opcode },
8638     { Bad_Opcode },
8639     { Bad_Opcode },
8640     { Bad_Opcode },
8641     { Bad_Opcode },
8642     { Bad_Opcode },
8643     { Bad_Opcode },
8644     { Bad_Opcode },
8645     /* d0 */
8646     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8647     { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8648     { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8649     { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8650     { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8651     { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8652     { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8653     { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8654     /* d8 */
8655     { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8656     { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8657     { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8658     { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8659     { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8660     { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8661     { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8662     { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8663     /* e0 */
8664     { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8665     { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8666     { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8667     { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8668     { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8669     { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8670     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8671     { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8672     /* e8 */
8673     { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8674     { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8675     { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8676     { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8677     { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8678     { PREFIX_TABLE (PREFIX_VEX_0FED) },
8679     { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8680     { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8681     /* f0 */
8682     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8683     { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8684     { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8685     { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8686     { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8687     { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8688     { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8689     { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8690     /* f8 */
8691     { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8692     { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8693     { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8694     { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8695     { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8696     { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8697     { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8698     { Bad_Opcode },
8699   },
8700   /* VEX_0F38 */
8701   {
8702     /* 00 */
8703     { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8704     { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8705     { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8706     { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8707     { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8708     { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8709     { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8710     { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8711     /* 08 */
8712     { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8713     { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8714     { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8715     { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8716     { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8717     { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8718     { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8719     { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8720     /* 10 */
8721     { Bad_Opcode },
8722     { Bad_Opcode },
8723     { Bad_Opcode },
8724     { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8725     { Bad_Opcode },
8726     { Bad_Opcode },
8727     { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8728     { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8729     /* 18 */
8730     { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8731     { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8732     { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8733     { Bad_Opcode },
8734     { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8735     { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8736     { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8737     { Bad_Opcode },
8738     /* 20 */
8739     { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8740     { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8741     { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8742     { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8743     { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8744     { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8745     { Bad_Opcode },
8746     { Bad_Opcode },
8747     /* 28 */
8748     { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8749     { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8750     { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8751     { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8752     { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8753     { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8754     { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8755     { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8756     /* 30 */
8757     { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8758     { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8759     { PREFIX_TABLE (PREFIX_VEX_0F3832) },
8760     { PREFIX_TABLE (PREFIX_VEX_0F3833) },
8761     { PREFIX_TABLE (PREFIX_VEX_0F3834) },
8762     { PREFIX_TABLE (PREFIX_VEX_0F3835) },
8763     { PREFIX_TABLE (PREFIX_VEX_0F3836) },
8764     { PREFIX_TABLE (PREFIX_VEX_0F3837) },
8765     /* 38 */
8766     { PREFIX_TABLE (PREFIX_VEX_0F3838) },
8767     { PREFIX_TABLE (PREFIX_VEX_0F3839) },
8768     { PREFIX_TABLE (PREFIX_VEX_0F383A) },
8769     { PREFIX_TABLE (PREFIX_VEX_0F383B) },
8770     { PREFIX_TABLE (PREFIX_VEX_0F383C) },
8771     { PREFIX_TABLE (PREFIX_VEX_0F383D) },
8772     { PREFIX_TABLE (PREFIX_VEX_0F383E) },
8773     { PREFIX_TABLE (PREFIX_VEX_0F383F) },
8774     /* 40 */
8775     { PREFIX_TABLE (PREFIX_VEX_0F3840) },
8776     { PREFIX_TABLE (PREFIX_VEX_0F3841) },
8777     { Bad_Opcode },
8778     { Bad_Opcode },
8779     { Bad_Opcode },
8780     { PREFIX_TABLE (PREFIX_VEX_0F3845) },
8781     { PREFIX_TABLE (PREFIX_VEX_0F3846) },
8782     { PREFIX_TABLE (PREFIX_VEX_0F3847) },
8783     /* 48 */
8784     { Bad_Opcode },
8785     { Bad_Opcode },
8786     { Bad_Opcode },
8787     { Bad_Opcode },
8788     { Bad_Opcode },
8789     { Bad_Opcode },
8790     { Bad_Opcode },
8791     { Bad_Opcode },
8792     /* 50 */
8793     { Bad_Opcode },
8794     { Bad_Opcode },
8795     { Bad_Opcode },
8796     { Bad_Opcode },
8797     { Bad_Opcode },
8798     { Bad_Opcode },
8799     { Bad_Opcode },
8800     { Bad_Opcode },
8801     /* 58 */
8802     { PREFIX_TABLE (PREFIX_VEX_0F3858) },
8803     { PREFIX_TABLE (PREFIX_VEX_0F3859) },
8804     { PREFIX_TABLE (PREFIX_VEX_0F385A) },
8805     { Bad_Opcode },
8806     { Bad_Opcode },
8807     { Bad_Opcode },
8808     { Bad_Opcode },
8809     { Bad_Opcode },
8810     /* 60 */
8811     { Bad_Opcode },
8812     { Bad_Opcode },
8813     { Bad_Opcode },
8814     { Bad_Opcode },
8815     { Bad_Opcode },
8816     { Bad_Opcode },
8817     { Bad_Opcode },
8818     { Bad_Opcode },
8819     /* 68 */
8820     { Bad_Opcode },
8821     { Bad_Opcode },
8822     { Bad_Opcode },
8823     { Bad_Opcode },
8824     { Bad_Opcode },
8825     { Bad_Opcode },
8826     { Bad_Opcode },
8827     { Bad_Opcode },
8828     /* 70 */
8829     { Bad_Opcode },
8830     { Bad_Opcode },
8831     { Bad_Opcode },
8832     { Bad_Opcode },
8833     { Bad_Opcode },
8834     { Bad_Opcode },
8835     { Bad_Opcode },
8836     { Bad_Opcode },
8837     /* 78 */
8838     { PREFIX_TABLE (PREFIX_VEX_0F3878) },
8839     { PREFIX_TABLE (PREFIX_VEX_0F3879) },
8840     { Bad_Opcode },
8841     { Bad_Opcode },
8842     { Bad_Opcode },
8843     { Bad_Opcode },
8844     { Bad_Opcode },
8845     { Bad_Opcode },
8846     /* 80 */
8847     { Bad_Opcode },
8848     { Bad_Opcode },
8849     { Bad_Opcode },
8850     { Bad_Opcode },
8851     { Bad_Opcode },
8852     { Bad_Opcode },
8853     { Bad_Opcode },
8854     { Bad_Opcode },
8855     /* 88 */
8856     { Bad_Opcode },
8857     { Bad_Opcode },
8858     { Bad_Opcode },
8859     { Bad_Opcode },
8860     { PREFIX_TABLE (PREFIX_VEX_0F388C) },
8861     { Bad_Opcode },
8862     { PREFIX_TABLE (PREFIX_VEX_0F388E) },
8863     { Bad_Opcode },
8864     /* 90 */
8865     { PREFIX_TABLE (PREFIX_VEX_0F3890) },
8866     { PREFIX_TABLE (PREFIX_VEX_0F3891) },
8867     { PREFIX_TABLE (PREFIX_VEX_0F3892) },
8868     { PREFIX_TABLE (PREFIX_VEX_0F3893) },
8869     { Bad_Opcode },
8870     { Bad_Opcode },
8871     { PREFIX_TABLE (PREFIX_VEX_0F3896) },
8872     { PREFIX_TABLE (PREFIX_VEX_0F3897) },
8873     /* 98 */
8874     { PREFIX_TABLE (PREFIX_VEX_0F3898) },
8875     { PREFIX_TABLE (PREFIX_VEX_0F3899) },
8876     { PREFIX_TABLE (PREFIX_VEX_0F389A) },
8877     { PREFIX_TABLE (PREFIX_VEX_0F389B) },
8878     { PREFIX_TABLE (PREFIX_VEX_0F389C) },
8879     { PREFIX_TABLE (PREFIX_VEX_0F389D) },
8880     { PREFIX_TABLE (PREFIX_VEX_0F389E) },
8881     { PREFIX_TABLE (PREFIX_VEX_0F389F) },
8882     /* a0 */
8883     { Bad_Opcode },
8884     { Bad_Opcode },
8885     { Bad_Opcode },
8886     { Bad_Opcode },
8887     { Bad_Opcode },
8888     { Bad_Opcode },
8889     { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
8890     { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
8891     /* a8 */
8892     { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
8893     { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
8894     { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
8895     { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
8896     { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
8897     { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
8898     { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
8899     { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
8900     /* b0 */
8901     { Bad_Opcode },
8902     { Bad_Opcode },
8903     { Bad_Opcode },
8904     { Bad_Opcode },
8905     { Bad_Opcode },
8906     { Bad_Opcode },
8907     { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
8908     { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
8909     /* b8 */
8910     { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
8911     { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
8912     { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
8913     { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
8914     { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
8915     { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
8916     { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
8917     { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
8918     /* c0 */
8919     { Bad_Opcode },
8920     { Bad_Opcode },
8921     { Bad_Opcode },
8922     { Bad_Opcode },
8923     { Bad_Opcode },
8924     { Bad_Opcode },
8925     { Bad_Opcode },
8926     { Bad_Opcode },
8927     /* c8 */
8928     { Bad_Opcode },
8929     { Bad_Opcode },
8930     { Bad_Opcode },
8931     { Bad_Opcode },
8932     { Bad_Opcode },
8933     { Bad_Opcode },
8934     { Bad_Opcode },
8935     { PREFIX_TABLE (PREFIX_VEX_0F38CF) },
8936     /* d0 */
8937     { Bad_Opcode },
8938     { Bad_Opcode },
8939     { Bad_Opcode },
8940     { Bad_Opcode },
8941     { Bad_Opcode },
8942     { Bad_Opcode },
8943     { Bad_Opcode },
8944     { Bad_Opcode },
8945     /* d8 */
8946     { Bad_Opcode },
8947     { Bad_Opcode },
8948     { Bad_Opcode },
8949     { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
8950     { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
8951     { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
8952     { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
8953     { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
8954     /* e0 */
8955     { Bad_Opcode },
8956     { Bad_Opcode },
8957     { Bad_Opcode },
8958     { Bad_Opcode },
8959     { Bad_Opcode },
8960     { Bad_Opcode },
8961     { Bad_Opcode },
8962     { Bad_Opcode },
8963     /* e8 */
8964     { Bad_Opcode },
8965     { Bad_Opcode },
8966     { Bad_Opcode },
8967     { Bad_Opcode },
8968     { Bad_Opcode },
8969     { Bad_Opcode },
8970     { Bad_Opcode },
8971     { Bad_Opcode },
8972     /* f0 */
8973     { Bad_Opcode },
8974     { Bad_Opcode },
8975     { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
8976     { REG_TABLE (REG_VEX_0F38F3) },
8977     { Bad_Opcode },
8978     { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
8979     { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
8980     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
8981     /* f8 */
8982     { Bad_Opcode },
8983     { Bad_Opcode },
8984     { Bad_Opcode },
8985     { Bad_Opcode },
8986     { Bad_Opcode },
8987     { Bad_Opcode },
8988     { Bad_Opcode },
8989     { Bad_Opcode },
8990   },
8991   /* VEX_0F3A */
8992   {
8993     /* 00 */
8994     { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
8995     { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
8996     { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
8997     { Bad_Opcode },
8998     { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
8999     { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
9000     { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
9001     { Bad_Opcode },
9002     /* 08 */
9003     { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
9004     { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
9005     { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
9006     { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
9007     { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
9008     { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
9009     { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
9010     { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
9011     /* 10 */
9012     { Bad_Opcode },
9013     { Bad_Opcode },
9014     { Bad_Opcode },
9015     { Bad_Opcode },
9016     { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
9017     { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
9018     { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
9019     { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
9020     /* 18 */
9021     { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
9022     { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
9023     { Bad_Opcode },
9024     { Bad_Opcode },
9025     { Bad_Opcode },
9026     { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
9027     { Bad_Opcode },
9028     { Bad_Opcode },
9029     /* 20 */
9030     { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
9031     { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
9032     { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
9033     { Bad_Opcode },
9034     { Bad_Opcode },
9035     { Bad_Opcode },
9036     { Bad_Opcode },
9037     { Bad_Opcode },
9038     /* 28 */
9039     { Bad_Opcode },
9040     { Bad_Opcode },
9041     { Bad_Opcode },
9042     { Bad_Opcode },
9043     { Bad_Opcode },
9044     { Bad_Opcode },
9045     { Bad_Opcode },
9046     { Bad_Opcode },
9047     /* 30 */
9048     { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
9049     { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
9050     { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
9051     { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
9052     { Bad_Opcode },
9053     { Bad_Opcode },
9054     { Bad_Opcode },
9055     { Bad_Opcode },
9056     /* 38 */
9057     { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
9058     { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
9059     { Bad_Opcode },
9060     { Bad_Opcode },
9061     { Bad_Opcode },
9062     { Bad_Opcode },
9063     { Bad_Opcode },
9064     { Bad_Opcode },
9065     /* 40 */
9066     { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
9067     { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
9068     { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
9069     { Bad_Opcode },
9070     { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
9071     { Bad_Opcode },
9072     { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
9073     { Bad_Opcode },
9074     /* 48 */
9075     { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
9076     { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
9077     { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
9078     { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
9079     { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
9080     { Bad_Opcode },
9081     { Bad_Opcode },
9082     { Bad_Opcode },
9083     /* 50 */
9084     { Bad_Opcode },
9085     { Bad_Opcode },
9086     { Bad_Opcode },
9087     { Bad_Opcode },
9088     { Bad_Opcode },
9089     { Bad_Opcode },
9090     { Bad_Opcode },
9091     { Bad_Opcode },
9092     /* 58 */
9093     { Bad_Opcode },
9094     { Bad_Opcode },
9095     { Bad_Opcode },
9096     { Bad_Opcode },
9097     { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9098     { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9099     { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9100     { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9101     /* 60 */
9102     { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9103     { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9104     { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9105     { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9106     { Bad_Opcode },
9107     { Bad_Opcode },
9108     { Bad_Opcode },
9109     { Bad_Opcode },
9110     /* 68 */
9111     { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9112     { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9113     { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9114     { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9115     { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9116     { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9117     { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9118     { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9119     /* 70 */
9120     { Bad_Opcode },
9121     { Bad_Opcode },
9122     { Bad_Opcode },
9123     { Bad_Opcode },
9124     { Bad_Opcode },
9125     { Bad_Opcode },
9126     { Bad_Opcode },
9127     { Bad_Opcode },
9128     /* 78 */
9129     { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9130     { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9131     { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9132     { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9133     { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9134     { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9135     { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9136     { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9137     /* 80 */
9138     { Bad_Opcode },
9139     { Bad_Opcode },
9140     { Bad_Opcode },
9141     { Bad_Opcode },
9142     { Bad_Opcode },
9143     { Bad_Opcode },
9144     { Bad_Opcode },
9145     { Bad_Opcode },
9146     /* 88 */
9147     { Bad_Opcode },
9148     { Bad_Opcode },
9149     { Bad_Opcode },
9150     { Bad_Opcode },
9151     { Bad_Opcode },
9152     { Bad_Opcode },
9153     { Bad_Opcode },
9154     { Bad_Opcode },
9155     /* 90 */
9156     { Bad_Opcode },
9157     { Bad_Opcode },
9158     { Bad_Opcode },
9159     { Bad_Opcode },
9160     { Bad_Opcode },
9161     { Bad_Opcode },
9162     { Bad_Opcode },
9163     { Bad_Opcode },
9164     /* 98 */
9165     { Bad_Opcode },
9166     { Bad_Opcode },
9167     { Bad_Opcode },
9168     { Bad_Opcode },
9169     { Bad_Opcode },
9170     { Bad_Opcode },
9171     { Bad_Opcode },
9172     { Bad_Opcode },
9173     /* a0 */
9174     { Bad_Opcode },
9175     { Bad_Opcode },
9176     { Bad_Opcode },
9177     { Bad_Opcode },
9178     { Bad_Opcode },
9179     { Bad_Opcode },
9180     { Bad_Opcode },
9181     { Bad_Opcode },
9182     /* a8 */
9183     { Bad_Opcode },
9184     { Bad_Opcode },
9185     { Bad_Opcode },
9186     { Bad_Opcode },
9187     { Bad_Opcode },
9188     { Bad_Opcode },
9189     { Bad_Opcode },
9190     { Bad_Opcode },
9191     /* b0 */
9192     { Bad_Opcode },
9193     { Bad_Opcode },
9194     { Bad_Opcode },
9195     { Bad_Opcode },
9196     { Bad_Opcode },
9197     { Bad_Opcode },
9198     { Bad_Opcode },
9199     { Bad_Opcode },
9200     /* b8 */
9201     { Bad_Opcode },
9202     { Bad_Opcode },
9203     { Bad_Opcode },
9204     { Bad_Opcode },
9205     { Bad_Opcode },
9206     { Bad_Opcode },
9207     { Bad_Opcode },
9208     { Bad_Opcode },
9209     /* c0 */
9210     { Bad_Opcode },
9211     { Bad_Opcode },
9212     { Bad_Opcode },
9213     { Bad_Opcode },
9214     { Bad_Opcode },
9215     { Bad_Opcode },
9216     { Bad_Opcode },
9217     { Bad_Opcode },
9218     /* c8 */
9219     { Bad_Opcode },
9220     { Bad_Opcode },
9221     { Bad_Opcode },
9222     { Bad_Opcode },
9223     { Bad_Opcode },
9224     { Bad_Opcode },
9225     { PREFIX_TABLE(PREFIX_VEX_0F3ACE) },
9226     { PREFIX_TABLE(PREFIX_VEX_0F3ACF) },
9227     /* d0 */
9228     { Bad_Opcode },
9229     { Bad_Opcode },
9230     { Bad_Opcode },
9231     { Bad_Opcode },
9232     { Bad_Opcode },
9233     { Bad_Opcode },
9234     { Bad_Opcode },
9235     { Bad_Opcode },
9236     /* d8 */
9237     { Bad_Opcode },
9238     { Bad_Opcode },
9239     { Bad_Opcode },
9240     { Bad_Opcode },
9241     { Bad_Opcode },
9242     { Bad_Opcode },
9243     { Bad_Opcode },
9244     { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9245     /* e0 */
9246     { Bad_Opcode },
9247     { Bad_Opcode },
9248     { Bad_Opcode },
9249     { Bad_Opcode },
9250     { Bad_Opcode },
9251     { Bad_Opcode },
9252     { Bad_Opcode },
9253     { Bad_Opcode },
9254     /* e8 */
9255     { Bad_Opcode },
9256     { Bad_Opcode },
9257     { Bad_Opcode },
9258     { Bad_Opcode },
9259     { Bad_Opcode },
9260     { Bad_Opcode },
9261     { Bad_Opcode },
9262     { Bad_Opcode },
9263     /* f0 */
9264     { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9265     { Bad_Opcode },
9266     { Bad_Opcode },
9267     { Bad_Opcode },
9268     { Bad_Opcode },
9269     { Bad_Opcode },
9270     { Bad_Opcode },
9271     { Bad_Opcode },
9272     /* f8 */
9273     { Bad_Opcode },
9274     { Bad_Opcode },
9275     { Bad_Opcode },
9276     { Bad_Opcode },
9277     { Bad_Opcode },
9278     { Bad_Opcode },
9279     { Bad_Opcode },
9280     { Bad_Opcode },
9281   },
9282 };
9283
9284 #define NEED_OPCODE_TABLE
9285 #include "i386-dis-evex.h"
9286 #undef NEED_OPCODE_TABLE
9287 static const struct dis386 vex_len_table[][2] = {
9288   /* VEX_LEN_0F12_P_0_M_0 */
9289   {
9290     { "vmovlps",        { XM, Vex128, EXq }, 0 },
9291   },
9292
9293   /* VEX_LEN_0F12_P_0_M_1 */
9294   {
9295     { "vmovhlps",       { XM, Vex128, EXq }, 0 },
9296   },
9297
9298   /* VEX_LEN_0F12_P_2 */
9299   {
9300     { "vmovlpd",        { XM, Vex128, EXq }, 0 },
9301   },
9302
9303   /* VEX_LEN_0F13_M_0 */
9304   {
9305     { "vmovlpX",        { EXq, XM }, 0 },
9306   },
9307
9308   /* VEX_LEN_0F16_P_0_M_0 */
9309   {
9310     { "vmovhps",        { XM, Vex128, EXq }, 0 },
9311   },
9312
9313   /* VEX_LEN_0F16_P_0_M_1 */
9314   {
9315     { "vmovlhps",       { XM, Vex128, EXq }, 0 },
9316   },
9317
9318   /* VEX_LEN_0F16_P_2 */
9319   {
9320     { "vmovhpd",        { XM, Vex128, EXq }, 0 },
9321   },
9322
9323   /* VEX_LEN_0F17_M_0 */
9324   {
9325     { "vmovhpX",        { EXq, XM }, 0 },
9326   },
9327
9328   /* VEX_LEN_0F2A_P_1 */
9329   {
9330     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9331     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9332   },
9333
9334   /* VEX_LEN_0F2A_P_3 */
9335   {
9336     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9337     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9338   },
9339
9340   /* VEX_LEN_0F2C_P_1 */
9341   {
9342     { "vcvttss2si",     { Gv, EXdScalar }, 0 },
9343     { "vcvttss2si",     { Gv, EXdScalar }, 0 },
9344   },
9345
9346   /* VEX_LEN_0F2C_P_3 */
9347   {
9348     { "vcvttsd2si",     { Gv, EXqScalar }, 0 },
9349     { "vcvttsd2si",     { Gv, EXqScalar }, 0 },
9350   },
9351
9352   /* VEX_LEN_0F2D_P_1 */
9353   {
9354     { "vcvtss2si",      { Gv, EXdScalar }, 0 },
9355     { "vcvtss2si",      { Gv, EXdScalar }, 0 },
9356   },
9357
9358   /* VEX_LEN_0F2D_P_3 */
9359   {
9360     { "vcvtsd2si",      { Gv, EXqScalar }, 0 },
9361     { "vcvtsd2si",      { Gv, EXqScalar }, 0 },
9362   },
9363
9364   /* VEX_LEN_0F41_P_0 */
9365   {
9366     { Bad_Opcode },
9367     { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9368   },
9369   /* VEX_LEN_0F41_P_2 */
9370   {
9371     { Bad_Opcode },
9372     { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9373   },
9374   /* VEX_LEN_0F42_P_0 */
9375   {
9376     { Bad_Opcode },
9377     { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9378   },
9379   /* VEX_LEN_0F42_P_2 */
9380   {
9381     { Bad_Opcode },
9382     { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9383   },
9384   /* VEX_LEN_0F44_P_0 */
9385   {
9386     { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9387   },
9388   /* VEX_LEN_0F44_P_2 */
9389   {
9390     { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9391   },
9392   /* VEX_LEN_0F45_P_0 */
9393   {
9394     { Bad_Opcode },
9395     { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9396   },
9397   /* VEX_LEN_0F45_P_2 */
9398   {
9399     { Bad_Opcode },
9400     { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9401   },
9402   /* VEX_LEN_0F46_P_0 */
9403   {
9404     { Bad_Opcode },
9405     { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9406   },
9407   /* VEX_LEN_0F46_P_2 */
9408   {
9409     { Bad_Opcode },
9410     { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9411   },
9412   /* VEX_LEN_0F47_P_0 */
9413   {
9414     { Bad_Opcode },
9415     { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9416   },
9417   /* VEX_LEN_0F47_P_2 */
9418   {
9419     { Bad_Opcode },
9420     { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9421   },
9422   /* VEX_LEN_0F4A_P_0 */
9423   {
9424     { Bad_Opcode },
9425     { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9426   },
9427   /* VEX_LEN_0F4A_P_2 */
9428   {
9429     { Bad_Opcode },
9430     { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9431   },
9432   /* VEX_LEN_0F4B_P_0 */
9433   {
9434     { Bad_Opcode },
9435     { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9436   },
9437   /* VEX_LEN_0F4B_P_2 */
9438   {
9439     { Bad_Opcode },
9440     { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9441   },
9442
9443   /* VEX_LEN_0F6E_P_2 */
9444   {
9445     { "vmovK",          { XMScalar, Edq }, 0 },
9446   },
9447
9448   /* VEX_LEN_0F77_P_1 */
9449   {
9450     { "vzeroupper",     { XX }, 0 },
9451     { "vzeroall",       { XX }, 0 },
9452   },
9453
9454   /* VEX_LEN_0F7E_P_1 */
9455   {
9456     { "vmovq",          { XMScalar, EXqScalar }, 0 },
9457   },
9458
9459   /* VEX_LEN_0F7E_P_2 */
9460   {
9461     { "vmovK",          { Edq, XMScalar }, 0 },
9462   },
9463
9464   /* VEX_LEN_0F90_P_0 */
9465   {
9466     { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9467   },
9468
9469   /* VEX_LEN_0F90_P_2 */
9470   {
9471     { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9472   },
9473
9474   /* VEX_LEN_0F91_P_0 */
9475   {
9476     { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9477   },
9478
9479   /* VEX_LEN_0F91_P_2 */
9480   {
9481     { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
9482   },
9483
9484   /* VEX_LEN_0F92_P_0 */
9485   {
9486     { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9487   },
9488
9489   /* VEX_LEN_0F92_P_2 */
9490   {
9491     { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
9492   },
9493
9494   /* VEX_LEN_0F92_P_3 */
9495   {
9496     { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0) },
9497   },
9498
9499   /* VEX_LEN_0F93_P_0 */
9500   {
9501     { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9502   },
9503
9504   /* VEX_LEN_0F93_P_2 */
9505   {
9506     { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
9507   },
9508
9509   /* VEX_LEN_0F93_P_3 */
9510   {
9511     { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0) },
9512   },
9513
9514   /* VEX_LEN_0F98_P_0 */
9515   {
9516     { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9517   },
9518
9519   /* VEX_LEN_0F98_P_2 */
9520   {
9521     { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
9522   },
9523
9524   /* VEX_LEN_0F99_P_0 */
9525   {
9526     { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
9527   },
9528
9529   /* VEX_LEN_0F99_P_2 */
9530   {
9531     { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
9532   },
9533
9534   /* VEX_LEN_0FAE_R_2_M_0 */
9535   {
9536     { "vldmxcsr",       { Md }, 0 },
9537   },
9538
9539   /* VEX_LEN_0FAE_R_3_M_0 */
9540   {
9541     { "vstmxcsr",       { Md }, 0 },
9542   },
9543
9544   /* VEX_LEN_0FC4_P_2 */
9545   {
9546     { VEX_W_TABLE (VEX_W_0FC4_P_2) },
9547   },
9548
9549   /* VEX_LEN_0FC5_P_2 */
9550   {
9551     { VEX_W_TABLE (VEX_W_0FC5_P_2) },
9552   },
9553
9554   /* VEX_LEN_0FD6_P_2 */
9555   {
9556     { "vmovq",          { EXqScalarS, XMScalar }, 0 },
9557   },
9558
9559   /* VEX_LEN_0FF7_P_2 */
9560   {
9561     { "vmaskmovdqu",    { XM, XS }, 0 },
9562   },
9563
9564   /* VEX_LEN_0F3816_P_2 */
9565   {
9566     { Bad_Opcode },
9567     { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9568   },
9569
9570   /* VEX_LEN_0F3819_P_2 */
9571   {
9572     { Bad_Opcode },
9573     { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9574   },
9575
9576   /* VEX_LEN_0F381A_P_2_M_0 */
9577   {
9578     { Bad_Opcode },
9579     { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9580   },
9581
9582   /* VEX_LEN_0F3836_P_2 */
9583   {
9584     { Bad_Opcode },
9585     { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9586   },
9587
9588   /* VEX_LEN_0F3841_P_2 */
9589   {
9590     { "vphminposuw",    { XM, EXx }, 0 },
9591   },
9592
9593   /* VEX_LEN_0F385A_P_2_M_0 */
9594   {
9595     { Bad_Opcode },
9596     { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
9597   },
9598
9599   /* VEX_LEN_0F38DB_P_2 */
9600   {
9601     { "vaesimc",        { XM, EXx }, 0 },
9602   },
9603
9604   /* VEX_LEN_0F38F2_P_0 */
9605   {
9606     { "andnS",          { Gdq, VexGdq, Edq }, 0 },
9607   },
9608
9609   /* VEX_LEN_0F38F3_R_1_P_0 */
9610   {
9611     { "blsrS",          { VexGdq, Edq }, 0 },
9612   },
9613
9614   /* VEX_LEN_0F38F3_R_2_P_0 */
9615   {
9616     { "blsmskS",        { VexGdq, Edq }, 0 },
9617   },
9618
9619   /* VEX_LEN_0F38F3_R_3_P_0 */
9620   {
9621     { "blsiS",          { VexGdq, Edq }, 0 },
9622   },
9623
9624   /* VEX_LEN_0F38F5_P_0 */
9625   {
9626     { "bzhiS",          { Gdq, Edq, VexGdq }, 0 },
9627   },
9628
9629   /* VEX_LEN_0F38F5_P_1 */
9630   {
9631     { "pextS",          { Gdq, VexGdq, Edq }, 0 },
9632   },
9633
9634   /* VEX_LEN_0F38F5_P_3 */
9635   {
9636     { "pdepS",          { Gdq, VexGdq, Edq }, 0 },
9637   },
9638
9639   /* VEX_LEN_0F38F6_P_3 */
9640   {
9641     { "mulxS",          { Gdq, VexGdq, Edq }, 0 },
9642   },
9643
9644   /* VEX_LEN_0F38F7_P_0 */
9645   {
9646     { "bextrS",         { Gdq, Edq, VexGdq }, 0 },
9647   },
9648
9649   /* VEX_LEN_0F38F7_P_1 */
9650   {
9651     { "sarxS",          { Gdq, Edq, VexGdq }, 0 },
9652   },
9653
9654   /* VEX_LEN_0F38F7_P_2 */
9655   {
9656     { "shlxS",          { Gdq, Edq, VexGdq }, 0 },
9657   },
9658
9659   /* VEX_LEN_0F38F7_P_3 */
9660   {
9661     { "shrxS",          { Gdq, Edq, VexGdq }, 0 },
9662   },
9663
9664   /* VEX_LEN_0F3A00_P_2 */
9665   {
9666     { Bad_Opcode },
9667     { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
9668   },
9669
9670   /* VEX_LEN_0F3A01_P_2 */
9671   {
9672     { Bad_Opcode },
9673     { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
9674   },
9675
9676   /* VEX_LEN_0F3A06_P_2 */
9677   {
9678     { Bad_Opcode },
9679     { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
9680   },
9681
9682   /* VEX_LEN_0F3A14_P_2 */
9683   {
9684     { VEX_W_TABLE (VEX_W_0F3A14_P_2) },
9685   },
9686
9687   /* VEX_LEN_0F3A15_P_2 */
9688   {
9689     { VEX_W_TABLE (VEX_W_0F3A15_P_2) },
9690   },
9691
9692   /* VEX_LEN_0F3A16_P_2  */
9693   {
9694     { "vpextrK",        { Edq, XM, Ib }, 0 },
9695   },
9696
9697   /* VEX_LEN_0F3A17_P_2 */
9698   {
9699     { "vextractps",     { Edqd, XM, Ib }, 0 },
9700   },
9701
9702   /* VEX_LEN_0F3A18_P_2 */
9703   {
9704     { Bad_Opcode },
9705     { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
9706   },
9707
9708   /* VEX_LEN_0F3A19_P_2 */
9709   {
9710     { Bad_Opcode },
9711     { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
9712   },
9713
9714   /* VEX_LEN_0F3A20_P_2 */
9715   {
9716     { VEX_W_TABLE (VEX_W_0F3A20_P_2) },
9717   },
9718
9719   /* VEX_LEN_0F3A21_P_2 */
9720   {
9721     { "vinsertps",      { XM, Vex128, EXd, Ib }, 0 },
9722   },
9723
9724   /* VEX_LEN_0F3A22_P_2 */
9725   {
9726     { "vpinsrK",        { XM, Vex128, Edq, Ib }, 0 },
9727   },
9728
9729   /* VEX_LEN_0F3A30_P_2 */
9730   {
9731     { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
9732   },
9733
9734   /* VEX_LEN_0F3A31_P_2 */
9735   {
9736     { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
9737   },
9738
9739   /* VEX_LEN_0F3A32_P_2 */
9740   {
9741     { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
9742   },
9743
9744   /* VEX_LEN_0F3A33_P_2 */
9745   {
9746     { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
9747   },
9748
9749   /* VEX_LEN_0F3A38_P_2 */
9750   {
9751     { Bad_Opcode },
9752     { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
9753   },
9754
9755   /* VEX_LEN_0F3A39_P_2 */
9756   {
9757     { Bad_Opcode },
9758     { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
9759   },
9760
9761   /* VEX_LEN_0F3A41_P_2 */
9762   {
9763     { "vdppd",          { XM, Vex128, EXx, Ib }, 0 },
9764   },
9765
9766   /* VEX_LEN_0F3A46_P_2 */
9767   {
9768     { Bad_Opcode },
9769     { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
9770   },
9771
9772   /* VEX_LEN_0F3A60_P_2 */
9773   {
9774     { "vpcmpestrm",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
9775   },
9776
9777   /* VEX_LEN_0F3A61_P_2 */
9778   {
9779     { "vpcmpestri",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
9780   },
9781
9782   /* VEX_LEN_0F3A62_P_2 */
9783   {
9784     { "vpcmpistrm",     { XM, EXx, Ib }, 0 },
9785   },
9786
9787   /* VEX_LEN_0F3A63_P_2 */
9788   {
9789     { "vpcmpistri",     { XM, EXx, Ib }, 0 },
9790   },
9791
9792   /* VEX_LEN_0F3A6A_P_2 */
9793   {
9794     { "vfmaddss",       { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9795   },
9796
9797   /* VEX_LEN_0F3A6B_P_2 */
9798   {
9799     { "vfmaddsd",       { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9800   },
9801
9802   /* VEX_LEN_0F3A6E_P_2 */
9803   {
9804     { "vfmsubss",       { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9805   },
9806
9807   /* VEX_LEN_0F3A6F_P_2 */
9808   {
9809     { "vfmsubsd",       { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9810   },
9811
9812   /* VEX_LEN_0F3A7A_P_2 */
9813   {
9814     { "vfnmaddss",      { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9815   },
9816
9817   /* VEX_LEN_0F3A7B_P_2 */
9818   {
9819     { "vfnmaddsd",      { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9820   },
9821
9822   /* VEX_LEN_0F3A7E_P_2 */
9823   {
9824     { "vfnmsubss",      { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9825   },
9826
9827   /* VEX_LEN_0F3A7F_P_2 */
9828   {
9829     { "vfnmsubsd",      { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9830   },
9831
9832   /* VEX_LEN_0F3ADF_P_2 */
9833   {
9834     { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
9835   },
9836
9837   /* VEX_LEN_0F3AF0_P_3 */
9838   {
9839     { "rorxS",          { Gdq, Edq, Ib }, 0 },
9840   },
9841
9842   /* VEX_LEN_0FXOP_08_CC */
9843   {
9844      { "vpcomb",        { XM, Vex128, EXx, VPCOM }, 0 },
9845   },
9846
9847   /* VEX_LEN_0FXOP_08_CD */
9848   {
9849      { "vpcomw",        { XM, Vex128, EXx, VPCOM }, 0 },
9850   },
9851
9852   /* VEX_LEN_0FXOP_08_CE */
9853   {
9854      { "vpcomd",        { XM, Vex128, EXx, VPCOM }, 0 },
9855   },
9856
9857   /* VEX_LEN_0FXOP_08_CF */
9858   {
9859      { "vpcomq",        { XM, Vex128, EXx, VPCOM }, 0 },
9860   },
9861
9862   /* VEX_LEN_0FXOP_08_EC */
9863   {
9864      { "vpcomub",       { XM, Vex128, EXx, VPCOM }, 0 },
9865   },
9866
9867   /* VEX_LEN_0FXOP_08_ED */
9868   {
9869      { "vpcomuw",       { XM, Vex128, EXx, VPCOM }, 0 },
9870   },
9871
9872   /* VEX_LEN_0FXOP_08_EE */
9873   {
9874      { "vpcomud",       { XM, Vex128, EXx, VPCOM }, 0 },
9875   },
9876
9877   /* VEX_LEN_0FXOP_08_EF */
9878   {
9879      { "vpcomuq",       { XM, Vex128, EXx, VPCOM }, 0 },
9880   },
9881
9882   /* VEX_LEN_0FXOP_09_80 */
9883   {
9884     { "vfrczps",        { XM, EXxmm }, 0 },
9885     { "vfrczps",        { XM, EXymmq }, 0 },
9886   },
9887
9888   /* VEX_LEN_0FXOP_09_81 */
9889   {
9890     { "vfrczpd",        { XM, EXxmm }, 0 },
9891     { "vfrczpd",        { XM, EXymmq }, 0 },
9892   },
9893 };
9894
9895 static const struct dis386 evex_len_table[][3] = {
9896 #define NEED_EVEX_LEN_TABLE
9897 #include "i386-dis-evex.h"
9898 #undef NEED_EVEX_LEN_TABLE
9899 };
9900
9901 static const struct dis386 vex_w_table[][2] = {
9902   {
9903     /* VEX_W_0F41_P_0_LEN_1 */
9904     { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
9905     { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) },
9906   },
9907   {
9908     /* VEX_W_0F41_P_2_LEN_1 */
9909     { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) },
9910     { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) }
9911   },
9912   {
9913     /* VEX_W_0F42_P_0_LEN_1 */
9914     { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) },
9915     { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) },
9916   },
9917   {
9918     /* VEX_W_0F42_P_2_LEN_1 */
9919     { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) },
9920     { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) },
9921   },
9922   {
9923     /* VEX_W_0F44_P_0_LEN_0 */
9924     { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) },
9925     { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) },
9926   },
9927   {
9928     /* VEX_W_0F44_P_2_LEN_0 */
9929     { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) },
9930     { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) },
9931   },
9932   {
9933     /* VEX_W_0F45_P_0_LEN_1 */
9934     { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) },
9935     { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) },
9936   },
9937   {
9938     /* VEX_W_0F45_P_2_LEN_1 */
9939     { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) },
9940     { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) },
9941   },
9942   {
9943     /* VEX_W_0F46_P_0_LEN_1 */
9944     { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) },
9945     { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) },
9946   },
9947   {
9948     /* VEX_W_0F46_P_2_LEN_1 */
9949     { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) },
9950     { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) },
9951   },
9952   {
9953     /* VEX_W_0F47_P_0_LEN_1 */
9954     { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) },
9955     { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) },
9956   },
9957   {
9958     /* VEX_W_0F47_P_2_LEN_1 */
9959     { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) },
9960     { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) },
9961   },
9962   {
9963     /* VEX_W_0F4A_P_0_LEN_1 */
9964     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) },
9965     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) },
9966   },
9967   {
9968     /* VEX_W_0F4A_P_2_LEN_1 */
9969     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) },
9970     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) },
9971   },
9972   {
9973     /* VEX_W_0F4B_P_0_LEN_1 */
9974     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) },
9975     { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) },
9976   },
9977   {
9978     /* VEX_W_0F4B_P_2_LEN_1 */
9979     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
9980   },
9981   {
9982     /* VEX_W_0F90_P_0_LEN_0 */
9983     { "kmovw",          { MaskG, MaskE }, 0 },
9984     { "kmovq",          { MaskG, MaskE }, 0 },
9985   },
9986   {
9987     /* VEX_W_0F90_P_2_LEN_0 */
9988     { "kmovb",          { MaskG, MaskBDE }, 0 },
9989     { "kmovd",          { MaskG, MaskBDE }, 0 },
9990   },
9991   {
9992     /* VEX_W_0F91_P_0_LEN_0 */
9993     { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
9994     { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
9995   },
9996   {
9997     /* VEX_W_0F91_P_2_LEN_0 */
9998     { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
9999     { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
10000   },
10001   {
10002     /* VEX_W_0F92_P_0_LEN_0 */
10003     { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
10004   },
10005   {
10006     /* VEX_W_0F92_P_2_LEN_0 */
10007     { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
10008   },
10009   {
10010     /* VEX_W_0F92_P_3_LEN_0 */
10011     { MOD_TABLE (MOD_VEX_W_0_0F92_P_3_LEN_0) },
10012     { MOD_TABLE (MOD_VEX_W_1_0F92_P_3_LEN_0) },
10013   },
10014   {
10015     /* VEX_W_0F93_P_0_LEN_0 */
10016     { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
10017   },
10018   {
10019     /* VEX_W_0F93_P_2_LEN_0 */
10020     { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
10021   },
10022   {
10023     /* VEX_W_0F93_P_3_LEN_0 */
10024     { MOD_TABLE (MOD_VEX_W_0_0F93_P_3_LEN_0) },
10025     { MOD_TABLE (MOD_VEX_W_1_0F93_P_3_LEN_0) },
10026   },
10027   {
10028     /* VEX_W_0F98_P_0_LEN_0 */
10029     { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
10030     { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
10031   },
10032   {
10033     /* VEX_W_0F98_P_2_LEN_0 */
10034     { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
10035     { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
10036   },
10037   {
10038     /* VEX_W_0F99_P_0_LEN_0 */
10039     { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
10040     { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
10041   },
10042   {
10043     /* VEX_W_0F99_P_2_LEN_0 */
10044     { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
10045     { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
10046   },
10047   {
10048     /* VEX_W_0FC4_P_2 */
10049     { "vpinsrw",        { XM, Vex128, Edqw, Ib }, 0 },
10050   },
10051   {
10052     /* VEX_W_0FC5_P_2 */
10053     { "vpextrw",        { Gdq, XS, Ib }, 0 },
10054   },
10055   {
10056     /* VEX_W_0F380C_P_2  */
10057     { "vpermilps",      { XM, Vex, EXx }, 0 },
10058   },
10059   {
10060     /* VEX_W_0F380D_P_2  */
10061     { "vpermilpd",      { XM, Vex, EXx }, 0 },
10062   },
10063   {
10064     /* VEX_W_0F380E_P_2  */
10065     { "vtestps",        { XM, EXx }, 0 },
10066   },
10067   {
10068     /* VEX_W_0F380F_P_2  */
10069     { "vtestpd",        { XM, EXx }, 0 },
10070   },
10071   {
10072     /* VEX_W_0F3816_P_2  */
10073     { "vpermps",        { XM, Vex, EXx }, 0 },
10074   },
10075   {
10076     /* VEX_W_0F3818_P_2 */
10077     { "vbroadcastss",   { XM, EXxmm_md }, 0 },
10078   },
10079   {
10080     /* VEX_W_0F3819_P_2 */
10081     { "vbroadcastsd",   { XM, EXxmm_mq }, 0 },
10082   },
10083   {
10084     /* VEX_W_0F381A_P_2_M_0 */
10085     { "vbroadcastf128", { XM, Mxmm }, 0 },
10086   },
10087   {
10088     /* VEX_W_0F382C_P_2_M_0 */
10089     { "vmaskmovps",     { XM, Vex, Mx }, 0 },
10090   },
10091   {
10092     /* VEX_W_0F382D_P_2_M_0 */
10093     { "vmaskmovpd",     { XM, Vex, Mx }, 0 },
10094   },
10095   {
10096     /* VEX_W_0F382E_P_2_M_0 */
10097     { "vmaskmovps",     { Mx, Vex, XM }, 0 },
10098   },
10099   {
10100     /* VEX_W_0F382F_P_2_M_0 */
10101     { "vmaskmovpd",     { Mx, Vex, XM }, 0 },
10102   },
10103   {
10104     /* VEX_W_0F3836_P_2  */
10105     { "vpermd",         { XM, Vex, EXx }, 0 },
10106   },
10107   {
10108     /* VEX_W_0F3846_P_2 */
10109     { "vpsravd",        { XM, Vex, EXx }, 0 },
10110   },
10111   {
10112     /* VEX_W_0F3858_P_2 */
10113     { "vpbroadcastd", { XM, EXxmm_md }, 0 },
10114   },
10115   {
10116     /* VEX_W_0F3859_P_2 */
10117     { "vpbroadcastq",   { XM, EXxmm_mq }, 0 },
10118   },
10119   {
10120     /* VEX_W_0F385A_P_2_M_0 */
10121     { "vbroadcasti128", { XM, Mxmm }, 0 },
10122   },
10123   {
10124     /* VEX_W_0F3878_P_2 */
10125     { "vpbroadcastb",   { XM, EXxmm_mb }, 0 },
10126   },
10127   {
10128     /* VEX_W_0F3879_P_2 */
10129     { "vpbroadcastw",   { XM, EXxmm_mw }, 0 },
10130   },
10131   {
10132     /* VEX_W_0F38CF_P_2 */
10133     { "vgf2p8mulb", { XM, Vex, EXx }, 0 },
10134   },
10135   {
10136     /* VEX_W_0F3A00_P_2 */
10137     { Bad_Opcode },
10138     { "vpermq",         { XM, EXx, Ib }, 0 },
10139   },
10140   {
10141     /* VEX_W_0F3A01_P_2 */
10142     { Bad_Opcode },
10143     { "vpermpd",        { XM, EXx, Ib }, 0 },
10144   },
10145   {
10146     /* VEX_W_0F3A02_P_2 */
10147     { "vpblendd",       { XM, Vex, EXx, Ib }, 0 },
10148   },
10149   {
10150     /* VEX_W_0F3A04_P_2 */
10151     { "vpermilps",      { XM, EXx, Ib }, 0 },
10152   },
10153   {
10154     /* VEX_W_0F3A05_P_2 */
10155     { "vpermilpd",      { XM, EXx, Ib }, 0 },
10156   },
10157   {
10158     /* VEX_W_0F3A06_P_2 */
10159     { "vperm2f128",     { XM, Vex256, EXx, Ib }, 0 },
10160   },
10161   {
10162     /* VEX_W_0F3A14_P_2 */
10163     { "vpextrb",        { Edqb, XM, Ib }, 0 },
10164   },
10165   {
10166     /* VEX_W_0F3A15_P_2 */
10167     { "vpextrw",        { Edqw, XM, Ib }, 0 },
10168   },
10169   {
10170     /* VEX_W_0F3A18_P_2 */
10171     { "vinsertf128",    { XM, Vex256, EXxmm, Ib }, 0 },
10172   },
10173   {
10174     /* VEX_W_0F3A19_P_2 */
10175     { "vextractf128",   { EXxmm, XM, Ib }, 0 },
10176   },
10177   {
10178     /* VEX_W_0F3A20_P_2 */
10179     { "vpinsrb",        { XM, Vex128, Edqb, Ib }, 0 },
10180   },
10181   {
10182     /* VEX_W_0F3A30_P_2_LEN_0 */
10183     { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) },
10184     { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) },
10185   },
10186   {
10187     /* VEX_W_0F3A31_P_2_LEN_0 */
10188     { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) },
10189     { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) },
10190   },
10191   {
10192     /* VEX_W_0F3A32_P_2_LEN_0 */
10193     { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) },
10194     { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) },
10195   },
10196   {
10197     /* VEX_W_0F3A33_P_2_LEN_0 */
10198     { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) },
10199     { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) },
10200   },
10201   {
10202     /* VEX_W_0F3A38_P_2 */
10203     { "vinserti128",    { XM, Vex256, EXxmm, Ib }, 0 },
10204   },
10205   {
10206     /* VEX_W_0F3A39_P_2 */
10207     { "vextracti128",   { EXxmm, XM, Ib }, 0 },
10208   },
10209   {
10210     /* VEX_W_0F3A46_P_2 */
10211     { "vperm2i128",     { XM, Vex256, EXx, Ib }, 0 },
10212   },
10213   {
10214     /* VEX_W_0F3A48_P_2 */
10215     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10216     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10217   },
10218   {
10219     /* VEX_W_0F3A49_P_2 */
10220     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10221     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10222   },
10223   {
10224     /* VEX_W_0F3A4A_P_2 */
10225     { "vblendvps",      { XM, Vex, EXx, XMVexI4 }, 0 },
10226   },
10227   {
10228     /* VEX_W_0F3A4B_P_2 */
10229     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 }, 0 },
10230   },
10231   {
10232     /* VEX_W_0F3A4C_P_2 */
10233     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 }, 0 },
10234   },
10235   {
10236     /* VEX_W_0F3ACE_P_2 */
10237     { Bad_Opcode },
10238     { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, 0 },
10239   },
10240   {
10241     /* VEX_W_0F3ACF_P_2 */
10242     { Bad_Opcode },
10243     { "vgf2p8affineinvqb",  { XM, Vex, EXx, Ib }, 0 },
10244   },
10245 #define NEED_VEX_W_TABLE
10246 #include "i386-dis-evex.h"
10247 #undef NEED_VEX_W_TABLE
10248 };
10249
10250 static const struct dis386 mod_table[][2] = {
10251   {
10252     /* MOD_8D */
10253     { "leaS",           { Gv, M }, 0 },
10254   },
10255   {
10256     /* MOD_C6_REG_7 */
10257     { Bad_Opcode },
10258     { RM_TABLE (RM_C6_REG_7) },
10259   },
10260   {
10261     /* MOD_C7_REG_7 */
10262     { Bad_Opcode },
10263     { RM_TABLE (RM_C7_REG_7) },
10264   },
10265   {
10266     /* MOD_FF_REG_3 */
10267     { "Jcall^", { indirEp }, 0 },
10268   },
10269   {
10270     /* MOD_FF_REG_5 */
10271     { "Jjmp^", { indirEp }, 0 },
10272   },
10273   {
10274     /* MOD_0F01_REG_0 */
10275     { X86_64_TABLE (X86_64_0F01_REG_0) },
10276     { RM_TABLE (RM_0F01_REG_0) },
10277   },
10278   {
10279     /* MOD_0F01_REG_1 */
10280     { X86_64_TABLE (X86_64_0F01_REG_1) },
10281     { RM_TABLE (RM_0F01_REG_1) },
10282   },
10283   {
10284     /* MOD_0F01_REG_2 */
10285     { X86_64_TABLE (X86_64_0F01_REG_2) },
10286     { RM_TABLE (RM_0F01_REG_2) },
10287   },
10288   {
10289     /* MOD_0F01_REG_3 */
10290     { X86_64_TABLE (X86_64_0F01_REG_3) },
10291     { RM_TABLE (RM_0F01_REG_3) },
10292   },
10293   {
10294     /* MOD_0F01_REG_5 */
10295     { PREFIX_TABLE (PREFIX_MOD_0_0F01_REG_5) },
10296     { RM_TABLE (RM_0F01_REG_5) },
10297   },
10298   {
10299     /* MOD_0F01_REG_7 */
10300     { "invlpg",         { Mb }, 0 },
10301     { RM_TABLE (RM_0F01_REG_7) },
10302   },
10303   {
10304     /* MOD_0F12_PREFIX_0 */
10305     { "movlps",         { XM, EXq }, PREFIX_OPCODE },
10306     { "movhlps",        { XM, EXq }, PREFIX_OPCODE },
10307   },
10308   {
10309     /* MOD_0F13 */
10310     { "movlpX",         { EXq, XM }, PREFIX_OPCODE },
10311   },
10312   {
10313     /* MOD_0F16_PREFIX_0 */
10314     { "movhps",         { XM, EXq }, 0 },
10315     { "movlhps",        { XM, EXq }, 0 },
10316   },
10317   {
10318     /* MOD_0F17 */
10319     { "movhpX",         { EXq, XM }, PREFIX_OPCODE },
10320   },
10321   {
10322     /* MOD_0F18_REG_0 */
10323     { "prefetchnta",    { Mb }, 0 },
10324   },
10325   {
10326     /* MOD_0F18_REG_1 */
10327     { "prefetcht0",     { Mb }, 0 },
10328   },
10329   {
10330     /* MOD_0F18_REG_2 */
10331     { "prefetcht1",     { Mb }, 0 },
10332   },
10333   {
10334     /* MOD_0F18_REG_3 */
10335     { "prefetcht2",     { Mb }, 0 },
10336   },
10337   {
10338     /* MOD_0F18_REG_4 */
10339     { "nop/reserved",   { Mb }, 0 },
10340   },
10341   {
10342     /* MOD_0F18_REG_5 */
10343     { "nop/reserved",   { Mb }, 0 },
10344   },
10345   {
10346     /* MOD_0F18_REG_6 */
10347     { "nop/reserved",   { Mb }, 0 },
10348   },
10349   {
10350     /* MOD_0F18_REG_7 */
10351     { "nop/reserved",   { Mb }, 0 },
10352   },
10353   {
10354     /* MOD_0F1A_PREFIX_0 */
10355     { "bndldx",         { Gbnd, Mv_bnd }, 0 },
10356     { "nopQ",           { Ev }, 0 },
10357   },
10358   {
10359     /* MOD_0F1B_PREFIX_0 */
10360     { "bndstx",         { Mv_bnd, Gbnd }, 0 },
10361     { "nopQ",           { Ev }, 0 },
10362   },
10363   {
10364     /* MOD_0F1B_PREFIX_1 */
10365     { "bndmk",          { Gbnd, Mv_bnd }, 0 },
10366     { "nopQ",           { Ev }, 0 },
10367   },
10368   {
10369     /* MOD_0F1C_PREFIX_0 */
10370     { REG_TABLE (REG_0F1C_MOD_0) },
10371     { "nopQ",           { Ev }, 0 },
10372   },
10373   {
10374     /* MOD_0F1E_PREFIX_1 */
10375     { "nopQ",           { Ev }, 0 },
10376     { REG_TABLE (REG_0F1E_MOD_3) },
10377   },
10378   {
10379     /* MOD_0F24 */
10380     { Bad_Opcode },
10381     { "movL",           { Rd, Td }, 0 },
10382   },
10383   {
10384     /* MOD_0F26 */
10385     { Bad_Opcode },
10386     { "movL",           { Td, Rd }, 0 },
10387   },
10388   {
10389     /* MOD_0F2B_PREFIX_0 */
10390     {"movntps",         { Mx, XM }, PREFIX_OPCODE },
10391   },
10392   {
10393     /* MOD_0F2B_PREFIX_1 */
10394     {"movntss",         { Md, XM }, PREFIX_OPCODE },
10395   },
10396   {
10397     /* MOD_0F2B_PREFIX_2 */
10398     {"movntpd",         { Mx, XM }, PREFIX_OPCODE },
10399   },
10400   {
10401     /* MOD_0F2B_PREFIX_3 */
10402     {"movntsd",         { Mq, XM }, PREFIX_OPCODE },
10403   },
10404   {
10405     /* MOD_0F51 */
10406     { Bad_Opcode },
10407     { "movmskpX",       { Gdq, XS }, PREFIX_OPCODE },
10408   },
10409   {
10410     /* MOD_0F71_REG_2 */
10411     { Bad_Opcode },
10412     { "psrlw",          { MS, Ib }, 0 },
10413   },
10414   {
10415     /* MOD_0F71_REG_4 */
10416     { Bad_Opcode },
10417     { "psraw",          { MS, Ib }, 0 },
10418   },
10419   {
10420     /* MOD_0F71_REG_6 */
10421     { Bad_Opcode },
10422     { "psllw",          { MS, Ib }, 0 },
10423   },
10424   {
10425     /* MOD_0F72_REG_2 */
10426     { Bad_Opcode },
10427     { "psrld",          { MS, Ib }, 0 },
10428   },
10429   {
10430     /* MOD_0F72_REG_4 */
10431     { Bad_Opcode },
10432     { "psrad",          { MS, Ib }, 0 },
10433   },
10434   {
10435     /* MOD_0F72_REG_6 */
10436     { Bad_Opcode },
10437     { "pslld",          { MS, Ib }, 0 },
10438   },
10439   {
10440     /* MOD_0F73_REG_2 */
10441     { Bad_Opcode },
10442     { "psrlq",          { MS, Ib }, 0 },
10443   },
10444   {
10445     /* MOD_0F73_REG_3 */
10446     { Bad_Opcode },
10447     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
10448   },
10449   {
10450     /* MOD_0F73_REG_6 */
10451     { Bad_Opcode },
10452     { "psllq",          { MS, Ib }, 0 },
10453   },
10454   {
10455     /* MOD_0F73_REG_7 */
10456     { Bad_Opcode },
10457     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
10458   },
10459   {
10460     /* MOD_0FAE_REG_0 */
10461     { "fxsave",         { FXSAVE }, 0 },
10462     { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
10463   },
10464   {
10465     /* MOD_0FAE_REG_1 */
10466     { "fxrstor",        { FXSAVE }, 0 },
10467     { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
10468   },
10469   {
10470     /* MOD_0FAE_REG_2 */
10471     { "ldmxcsr",        { Md }, 0 },
10472     { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
10473   },
10474   {
10475     /* MOD_0FAE_REG_3 */
10476     { "stmxcsr",        { Md }, 0 },
10477     { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
10478   },
10479   {
10480     /* MOD_0FAE_REG_4 */
10481     { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_4) },
10482     { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_4) },
10483   },
10484   {
10485     /* MOD_0FAE_REG_5 */
10486     { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_5) },
10487     { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_5) },
10488   },
10489   {
10490     /* MOD_0FAE_REG_6 */
10491     { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_6) },
10492     { PREFIX_TABLE (PREFIX_MOD_1_0FAE_REG_6) },
10493   },
10494   {
10495     /* MOD_0FAE_REG_7 */
10496     { PREFIX_TABLE (PREFIX_0FAE_REG_7) },
10497     { RM_TABLE (RM_0FAE_REG_7) },
10498   },
10499   {
10500     /* MOD_0FB2 */
10501     { "lssS",           { Gv, Mp }, 0 },
10502   },
10503   {
10504     /* MOD_0FB4 */
10505     { "lfsS",           { Gv, Mp }, 0 },
10506   },
10507   {
10508     /* MOD_0FB5 */
10509     { "lgsS",           { Gv, Mp }, 0 },
10510   },
10511   {
10512     /* MOD_0FC3 */
10513     { PREFIX_TABLE (PREFIX_MOD_0_0FC3) },
10514   },
10515   {
10516     /* MOD_0FC7_REG_3 */
10517     { "xrstors",        { FXSAVE }, 0 },
10518   },
10519   {
10520     /* MOD_0FC7_REG_4 */
10521     { "xsavec",         { FXSAVE }, 0 },
10522   },
10523   {
10524     /* MOD_0FC7_REG_5 */
10525     { "xsaves",         { FXSAVE }, 0 },
10526   },
10527   {
10528     /* MOD_0FC7_REG_6 */
10529     { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6) },
10530     { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6) }
10531   },
10532   {
10533     /* MOD_0FC7_REG_7 */
10534     { "vmptrst",        { Mq }, 0 },
10535     { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7) }
10536   },
10537   {
10538     /* MOD_0FD7 */
10539     { Bad_Opcode },
10540     { "pmovmskb",       { Gdq, MS }, 0 },
10541   },
10542   {
10543     /* MOD_0FE7_PREFIX_2 */
10544     { "movntdq",        { Mx, XM }, 0 },
10545   },
10546   {
10547     /* MOD_0FF0_PREFIX_3 */
10548     { "lddqu",          { XM, M }, 0 },
10549   },
10550   {
10551     /* MOD_0F382A_PREFIX_2 */
10552     { "movntdqa",       { XM, Mx }, 0 },
10553   },
10554   {
10555     /* MOD_0F38F5_PREFIX_2 */
10556     { "wrussK",         { M, Gdq }, PREFIX_OPCODE },
10557   },
10558   {
10559     /* MOD_0F38F6_PREFIX_0 */
10560     { "wrssK",          { M, Gdq }, PREFIX_OPCODE },
10561   },
10562   {
10563     /* MOD_0F38F8_PREFIX_2 */
10564     { "movdir64b",      { Gva, M }, PREFIX_OPCODE },
10565   },
10566   {
10567     /* MOD_0F38F9_PREFIX_0 */
10568     { "movdiri",        { Em, Gv }, PREFIX_OPCODE },
10569   },
10570   {
10571     /* MOD_62_32BIT */
10572     { "bound{S|}",      { Gv, Ma }, 0 },
10573     { EVEX_TABLE (EVEX_0F) },
10574   },
10575   {
10576     /* MOD_C4_32BIT */
10577     { "lesS",           { Gv, Mp }, 0 },
10578     { VEX_C4_TABLE (VEX_0F) },
10579   },
10580   {
10581     /* MOD_C5_32BIT */
10582     { "ldsS",           { Gv, Mp }, 0 },
10583     { VEX_C5_TABLE (VEX_0F) },
10584   },
10585   {
10586     /* MOD_VEX_0F12_PREFIX_0 */
10587     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
10588     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
10589   },
10590   {
10591     /* MOD_VEX_0F13 */
10592     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
10593   },
10594   {
10595     /* MOD_VEX_0F16_PREFIX_0 */
10596     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
10597     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
10598   },
10599   {
10600     /* MOD_VEX_0F17 */
10601     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
10602   },
10603   {
10604     /* MOD_VEX_0F2B */
10605     { "vmovntpX",       { Mx, XM }, 0 },
10606   },
10607   {
10608     /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
10609     { Bad_Opcode },
10610     { "kandw",          { MaskG, MaskVex, MaskR }, 0 },
10611   },
10612   {
10613     /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
10614     { Bad_Opcode },
10615     { "kandq",          { MaskG, MaskVex, MaskR }, 0 },
10616   },
10617   {
10618     /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
10619     { Bad_Opcode },
10620     { "kandb",          { MaskG, MaskVex, MaskR }, 0 },
10621   },
10622   {
10623     /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
10624     { Bad_Opcode },
10625     { "kandd",          { MaskG, MaskVex, MaskR }, 0 },
10626   },
10627   {
10628     /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
10629     { Bad_Opcode },
10630     { "kandnw",         { MaskG, MaskVex, MaskR }, 0 },
10631   },
10632   {
10633     /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
10634     { Bad_Opcode },
10635     { "kandnq",         { MaskG, MaskVex, MaskR }, 0 },
10636   },
10637   {
10638     /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
10639     { Bad_Opcode },
10640     { "kandnb",         { MaskG, MaskVex, MaskR }, 0 },
10641   },
10642   {
10643     /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
10644     { Bad_Opcode },
10645     { "kandnd",         { MaskG, MaskVex, MaskR }, 0 },
10646   },
10647   {
10648     /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
10649     { Bad_Opcode },
10650     { "knotw",          { MaskG, MaskR }, 0 },
10651   },
10652   {
10653     /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
10654     { Bad_Opcode },
10655     { "knotq",          { MaskG, MaskR }, 0 },
10656   },
10657   {
10658     /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
10659     { Bad_Opcode },
10660     { "knotb",          { MaskG, MaskR }, 0 },
10661   },
10662   {
10663     /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
10664     { Bad_Opcode },
10665     { "knotd",          { MaskG, MaskR }, 0 },
10666   },
10667   {
10668     /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
10669     { Bad_Opcode },
10670     { "korw",       { MaskG, MaskVex, MaskR }, 0 },
10671   },
10672   {
10673     /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
10674     { Bad_Opcode },
10675     { "korq",       { MaskG, MaskVex, MaskR }, 0 },
10676   },
10677   {
10678     /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
10679     { Bad_Opcode },
10680     { "korb",       { MaskG, MaskVex, MaskR }, 0 },
10681   },
10682   {
10683     /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
10684     { Bad_Opcode },
10685     { "kord",       { MaskG, MaskVex, MaskR }, 0 },
10686   },
10687  {
10688     /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
10689     { Bad_Opcode },
10690     { "kxnorw",     { MaskG, MaskVex, MaskR }, 0 },
10691   },
10692   {
10693     /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
10694     { Bad_Opcode },
10695     { "kxnorq",     { MaskG, MaskVex, MaskR }, 0 },
10696   },
10697   {
10698     /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
10699     { Bad_Opcode },
10700     { "kxnorb",     { MaskG, MaskVex, MaskR }, 0 },
10701   },
10702   {
10703     /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
10704     { Bad_Opcode },
10705     { "kxnord",     { MaskG, MaskVex, MaskR }, 0 },
10706   },
10707   {
10708     /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
10709     { Bad_Opcode },
10710     { "kxorw",      { MaskG, MaskVex, MaskR }, 0 },
10711   },
10712   {
10713     /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
10714     { Bad_Opcode },
10715     { "kxorq",      { MaskG, MaskVex, MaskR }, 0 },
10716   },
10717   {
10718     /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
10719     { Bad_Opcode },
10720     { "kxorb",      { MaskG, MaskVex, MaskR }, 0 },
10721   },
10722   {
10723     /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
10724     { Bad_Opcode },
10725     { "kxord",      { MaskG, MaskVex, MaskR }, 0 },
10726   },
10727   {
10728     /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
10729     { Bad_Opcode },
10730     { "kaddw",          { MaskG, MaskVex, MaskR }, 0 },
10731   },
10732   {
10733     /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
10734     { Bad_Opcode },
10735     { "kaddq",          { MaskG, MaskVex, MaskR }, 0 },
10736   },
10737   {
10738     /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
10739     { Bad_Opcode },
10740     { "kaddb",          { MaskG, MaskVex, MaskR }, 0 },
10741   },
10742   {
10743     /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
10744     { Bad_Opcode },
10745     { "kaddd",          { MaskG, MaskVex, MaskR }, 0 },
10746   },
10747   {
10748     /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
10749     { Bad_Opcode },
10750     { "kunpckwd",   { MaskG, MaskVex, MaskR }, 0 },
10751   },
10752   {
10753     /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
10754     { Bad_Opcode },
10755     { "kunpckdq",   { MaskG, MaskVex, MaskR }, 0 },
10756   },
10757   {
10758     /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
10759     { Bad_Opcode },
10760     { "kunpckbw",   { MaskG, MaskVex, MaskR }, 0 },
10761   },
10762   {
10763     /* MOD_VEX_0F50 */
10764     { Bad_Opcode },
10765     { "vmovmskpX",      { Gdq, XS }, 0 },
10766   },
10767   {
10768     /* MOD_VEX_0F71_REG_2 */
10769     { Bad_Opcode },
10770     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
10771   },
10772   {
10773     /* MOD_VEX_0F71_REG_4 */
10774     { Bad_Opcode },
10775     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
10776   },
10777   {
10778     /* MOD_VEX_0F71_REG_6 */
10779     { Bad_Opcode },
10780     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
10781   },
10782   {
10783     /* MOD_VEX_0F72_REG_2 */
10784     { Bad_Opcode },
10785     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
10786   },
10787   {
10788     /* MOD_VEX_0F72_REG_4 */
10789     { Bad_Opcode },
10790     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
10791   },
10792   {
10793     /* MOD_VEX_0F72_REG_6 */
10794     { Bad_Opcode },
10795     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
10796   },
10797   {
10798     /* MOD_VEX_0F73_REG_2 */
10799     { Bad_Opcode },
10800     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
10801   },
10802   {
10803     /* MOD_VEX_0F73_REG_3 */
10804     { Bad_Opcode },
10805     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
10806   },
10807   {
10808     /* MOD_VEX_0F73_REG_6 */
10809     { Bad_Opcode },
10810     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
10811   },
10812   {
10813     /* MOD_VEX_0F73_REG_7 */
10814     { Bad_Opcode },
10815     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
10816   },
10817   {
10818     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10819     { "kmovw",          { Ew, MaskG }, 0 },
10820     { Bad_Opcode },
10821   },
10822   {
10823     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10824     { "kmovq",          { Eq, MaskG }, 0 },
10825     { Bad_Opcode },
10826   },
10827   {
10828     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10829     { "kmovb",          { Eb, MaskG }, 0 },
10830     { Bad_Opcode },
10831   },
10832   {
10833     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10834     { "kmovd",          { Ed, MaskG }, 0 },
10835     { Bad_Opcode },
10836   },
10837   {
10838     /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
10839     { Bad_Opcode },
10840     { "kmovw",          { MaskG, Rdq }, 0 },
10841   },
10842   {
10843     /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
10844     { Bad_Opcode },
10845     { "kmovb",          { MaskG, Rdq }, 0 },
10846   },
10847   {
10848     /* MOD_VEX_W_0_0F92_P_3_LEN_0 */
10849     { Bad_Opcode },
10850     { "kmovd",          { MaskG, Rdq }, 0 },
10851   },
10852   {
10853     /* MOD_VEX_W_1_0F92_P_3_LEN_0 */
10854     { Bad_Opcode },
10855     { "kmovq",          { MaskG, Rdq }, 0 },
10856   },
10857   {
10858     /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
10859     { Bad_Opcode },
10860     { "kmovw",          { Gdq, MaskR }, 0 },
10861   },
10862   {
10863     /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
10864     { Bad_Opcode },
10865     { "kmovb",          { Gdq, MaskR }, 0 },
10866   },
10867   {
10868     /* MOD_VEX_W_0_0F93_P_3_LEN_0 */
10869     { Bad_Opcode },
10870     { "kmovd",          { Gdq, MaskR }, 0 },
10871   },
10872   {
10873     /* MOD_VEX_W_1_0F93_P_3_LEN_0 */
10874     { Bad_Opcode },
10875     { "kmovq",          { Gdq, MaskR }, 0 },
10876   },
10877   {
10878     /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
10879     { Bad_Opcode },
10880     { "kortestw", { MaskG, MaskR }, 0 },
10881   },
10882   {
10883     /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
10884     { Bad_Opcode },
10885     { "kortestq", { MaskG, MaskR }, 0 },
10886   },
10887   {
10888     /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
10889     { Bad_Opcode },
10890     { "kortestb", { MaskG, MaskR }, 0 },
10891   },
10892   {
10893     /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
10894     { Bad_Opcode },
10895     { "kortestd", { MaskG, MaskR }, 0 },
10896   },
10897   {
10898     /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
10899     { Bad_Opcode },
10900     { "ktestw", { MaskG, MaskR }, 0 },
10901   },
10902   {
10903     /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
10904     { Bad_Opcode },
10905     { "ktestq", { MaskG, MaskR }, 0 },
10906   },
10907   {
10908     /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
10909     { Bad_Opcode },
10910     { "ktestb", { MaskG, MaskR }, 0 },
10911   },
10912   {
10913     /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
10914     { Bad_Opcode },
10915     { "ktestd", { MaskG, MaskR }, 0 },
10916   },
10917   {
10918     /* MOD_VEX_0FAE_REG_2 */
10919     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
10920   },
10921   {
10922     /* MOD_VEX_0FAE_REG_3 */
10923     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
10924   },
10925   {
10926     /* MOD_VEX_0FD7_PREFIX_2 */
10927     { Bad_Opcode },
10928     { "vpmovmskb",      { Gdq, XS }, 0 },
10929   },
10930   {
10931     /* MOD_VEX_0FE7_PREFIX_2 */
10932     { "vmovntdq",       { Mx, XM }, 0 },
10933   },
10934   {
10935     /* MOD_VEX_0FF0_PREFIX_3 */
10936     { "vlddqu",         { XM, M }, 0 },
10937   },
10938   {
10939     /* MOD_VEX_0F381A_PREFIX_2 */
10940     { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
10941   },
10942   {
10943     /* MOD_VEX_0F382A_PREFIX_2 */
10944     { "vmovntdqa",      { XM, Mx }, 0 },
10945   },
10946   {
10947     /* MOD_VEX_0F382C_PREFIX_2 */
10948     { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
10949   },
10950   {
10951     /* MOD_VEX_0F382D_PREFIX_2 */
10952     { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
10953   },
10954   {
10955     /* MOD_VEX_0F382E_PREFIX_2 */
10956     { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
10957   },
10958   {
10959     /* MOD_VEX_0F382F_PREFIX_2 */
10960     { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
10961   },
10962   {
10963     /* MOD_VEX_0F385A_PREFIX_2 */
10964     { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
10965   },
10966   {
10967     /* MOD_VEX_0F388C_PREFIX_2 */
10968     { "vpmaskmov%LW",   { XM, Vex, Mx }, 0 },
10969   },
10970   {
10971     /* MOD_VEX_0F388E_PREFIX_2 */
10972     { "vpmaskmov%LW",   { Mx, Vex, XM }, 0 },
10973   },
10974   {
10975     /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
10976     { Bad_Opcode },
10977     { "kshiftrb",       { MaskG, MaskR, Ib }, 0 },
10978   },
10979   {
10980     /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
10981     { Bad_Opcode },
10982     { "kshiftrw",       { MaskG, MaskR, Ib }, 0 },
10983   },
10984   {
10985     /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
10986     { Bad_Opcode },
10987     { "kshiftrd",       { MaskG, MaskR, Ib }, 0 },
10988   },
10989   {
10990     /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
10991     { Bad_Opcode },
10992     { "kshiftrq",       { MaskG, MaskR, Ib }, 0 },
10993   },
10994   {
10995     /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
10996     { Bad_Opcode },
10997     { "kshiftlb",       { MaskG, MaskR, Ib }, 0 },
10998   },
10999   {
11000     /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
11001     { Bad_Opcode },
11002     { "kshiftlw",       { MaskG, MaskR, Ib }, 0 },
11003   },
11004   {
11005     /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
11006     { Bad_Opcode },
11007     { "kshiftld",       { MaskG, MaskR, Ib }, 0 },
11008   },
11009   {
11010     /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
11011     { Bad_Opcode },
11012     { "kshiftlq",       { MaskG, MaskR, Ib }, 0 },
11013   },
11014 #define NEED_MOD_TABLE
11015 #include "i386-dis-evex.h"
11016 #undef NEED_MOD_TABLE
11017 };
11018
11019 static const struct dis386 rm_table[][8] = {
11020   {
11021     /* RM_C6_REG_7 */
11022     { "xabort",         { Skip_MODRM, Ib }, 0 },
11023   },
11024   {
11025     /* RM_C7_REG_7 */
11026     { "xbeginT",        { Skip_MODRM, Jv }, 0 },
11027   },
11028   {
11029     /* RM_0F01_REG_0 */
11030     { Bad_Opcode },
11031     { "vmcall",         { Skip_MODRM }, 0 },
11032     { "vmlaunch",       { Skip_MODRM }, 0 },
11033     { "vmresume",       { Skip_MODRM }, 0 },
11034     { "vmxoff",         { Skip_MODRM }, 0 },
11035     { "pconfig",        { Skip_MODRM }, 0 },
11036   },
11037   {
11038     /* RM_0F01_REG_1 */
11039     { "monitor",        { { OP_Monitor, 0 } }, 0 },
11040     { "mwait",          { { OP_Mwait, 0 } }, 0 },
11041     { "clac",           { Skip_MODRM }, 0 },
11042     { "stac",           { Skip_MODRM }, 0 },
11043     { Bad_Opcode },
11044     { Bad_Opcode },
11045     { Bad_Opcode },
11046     { "encls",          { Skip_MODRM }, 0 },
11047   },
11048   {
11049     /* RM_0F01_REG_2 */
11050     { "xgetbv",         { Skip_MODRM }, 0 },
11051     { "xsetbv",         { Skip_MODRM }, 0 },
11052     { Bad_Opcode },
11053     { Bad_Opcode },
11054     { "vmfunc",         { Skip_MODRM }, 0 },
11055     { "xend",           { Skip_MODRM }, 0 },
11056     { "xtest",          { Skip_MODRM }, 0 },
11057     { "enclu",          { Skip_MODRM }, 0 },
11058   },
11059   {
11060     /* RM_0F01_REG_3 */
11061     { "vmrun",          { Skip_MODRM }, 0 },
11062     { "vmmcall",        { Skip_MODRM }, 0 },
11063     { "vmload",         { Skip_MODRM }, 0 },
11064     { "vmsave",         { Skip_MODRM }, 0 },
11065     { "stgi",           { Skip_MODRM }, 0 },
11066     { "clgi",           { Skip_MODRM }, 0 },
11067     { "skinit",         { Skip_MODRM }, 0 },
11068     { "invlpga",        { Skip_MODRM }, 0 },
11069   },
11070   {
11071     /* RM_0F01_REG_5 */
11072     { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_0) },
11073     { Bad_Opcode },
11074     { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_2) },
11075     { Bad_Opcode },
11076     { Bad_Opcode },
11077     { Bad_Opcode },
11078     { "rdpkru",         { Skip_MODRM }, 0 },
11079     { "wrpkru",         { Skip_MODRM }, 0 },
11080   },
11081   {
11082     /* RM_0F01_REG_7 */
11083     { "swapgs",         { Skip_MODRM }, 0  },
11084     { "rdtscp",         { Skip_MODRM }, 0  },
11085     { "monitorx",       { { OP_Monitor, 0 } }, 0  },
11086     { "mwaitx",         { { OP_Mwaitx,  0 } }, 0  },
11087     { "clzero",         { Skip_MODRM }, 0  },
11088   },
11089   {
11090     /* RM_0F1E_MOD_3_REG_7 */
11091     { "nopQ",           { Ev }, 0 },
11092     { "nopQ",           { Ev }, 0 },
11093     { "endbr64",        { Skip_MODRM },  PREFIX_OPCODE },
11094     { "endbr32",        { Skip_MODRM },  PREFIX_OPCODE },
11095     { "nopQ",           { Ev }, 0 },
11096     { "nopQ",           { Ev }, 0 },
11097     { "nopQ",           { Ev }, 0 },
11098     { "nopQ",           { Ev }, 0 },
11099   },
11100   {
11101     /* RM_0FAE_REG_6 */
11102     { "mfence",         { Skip_MODRM }, 0 },
11103   },
11104   {
11105     /* RM_0FAE_REG_7 */
11106     { "sfence",         { Skip_MODRM }, 0 },
11107
11108   },
11109 };
11110
11111 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
11112
11113 /* We use the high bit to indicate different name for the same
11114    prefix.  */
11115 #define REP_PREFIX      (0xf3 | 0x100)
11116 #define XACQUIRE_PREFIX (0xf2 | 0x200)
11117 #define XRELEASE_PREFIX (0xf3 | 0x400)
11118 #define BND_PREFIX      (0xf2 | 0x400)
11119 #define NOTRACK_PREFIX  (0x3e | 0x100)
11120
11121 static int
11122 ckprefix (void)
11123 {
11124   int newrex, i, length;
11125   rex = 0;
11126   rex_ignored = 0;
11127   prefixes = 0;
11128   used_prefixes = 0;
11129   rex_used = 0;
11130   last_lock_prefix = -1;
11131   last_repz_prefix = -1;
11132   last_repnz_prefix = -1;
11133   last_data_prefix = -1;
11134   last_addr_prefix = -1;
11135   last_rex_prefix = -1;
11136   last_seg_prefix = -1;
11137   fwait_prefix = -1;
11138   active_seg_prefix = 0;
11139   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
11140     all_prefixes[i] = 0;
11141   i = 0;
11142   length = 0;
11143   /* The maximum instruction length is 15bytes.  */
11144   while (length < MAX_CODE_LENGTH - 1)
11145     {
11146       FETCH_DATA (the_info, codep + 1);
11147       newrex = 0;
11148       switch (*codep)
11149         {
11150         /* REX prefixes family.  */
11151         case 0x40:
11152         case 0x41:
11153         case 0x42:
11154         case 0x43:
11155         case 0x44:
11156         case 0x45:
11157         case 0x46:
11158         case 0x47:
11159         case 0x48:
11160         case 0x49:
11161         case 0x4a:
11162         case 0x4b:
11163         case 0x4c:
11164         case 0x4d:
11165         case 0x4e:
11166         case 0x4f:
11167           if (address_mode == mode_64bit)
11168             newrex = *codep;
11169           else
11170             return 1;
11171           last_rex_prefix = i;
11172           break;
11173         case 0xf3:
11174           prefixes |= PREFIX_REPZ;
11175           last_repz_prefix = i;
11176           break;
11177         case 0xf2:
11178           prefixes |= PREFIX_REPNZ;
11179           last_repnz_prefix = i;
11180           break;
11181         case 0xf0:
11182           prefixes |= PREFIX_LOCK;
11183           last_lock_prefix = i;
11184           break;
11185         case 0x2e:
11186           prefixes |= PREFIX_CS;
11187           last_seg_prefix = i;
11188           active_seg_prefix = PREFIX_CS;
11189           break;
11190         case 0x36:
11191           prefixes |= PREFIX_SS;
11192           last_seg_prefix = i;
11193           active_seg_prefix = PREFIX_SS;
11194           break;
11195         case 0x3e:
11196           prefixes |= PREFIX_DS;
11197           last_seg_prefix = i;
11198           active_seg_prefix = PREFIX_DS;
11199           break;
11200         case 0x26:
11201           prefixes |= PREFIX_ES;
11202           last_seg_prefix = i;
11203           active_seg_prefix = PREFIX_ES;
11204           break;
11205         case 0x64:
11206           prefixes |= PREFIX_FS;
11207           last_seg_prefix = i;
11208           active_seg_prefix = PREFIX_FS;
11209           break;
11210         case 0x65:
11211           prefixes |= PREFIX_GS;
11212           last_seg_prefix = i;
11213           active_seg_prefix = PREFIX_GS;
11214           break;
11215         case 0x66:
11216           prefixes |= PREFIX_DATA;
11217           last_data_prefix = i;
11218           break;
11219         case 0x67:
11220           prefixes |= PREFIX_ADDR;
11221           last_addr_prefix = i;
11222           break;
11223         case FWAIT_OPCODE:
11224           /* fwait is really an instruction.  If there are prefixes
11225              before the fwait, they belong to the fwait, *not* to the
11226              following instruction.  */
11227           fwait_prefix = i;
11228           if (prefixes || rex)
11229             {
11230               prefixes |= PREFIX_FWAIT;
11231               codep++;
11232               /* This ensures that the previous REX prefixes are noticed
11233                  as unused prefixes, as in the return case below.  */
11234               rex_used = rex;
11235               return 1;
11236             }
11237           prefixes = PREFIX_FWAIT;
11238           break;
11239         default:
11240           return 1;
11241         }
11242       /* Rex is ignored when followed by another prefix.  */
11243       if (rex)
11244         {
11245           rex_used = rex;
11246           return 1;
11247         }
11248       if (*codep != FWAIT_OPCODE)
11249         all_prefixes[i++] = *codep;
11250       rex = newrex;
11251       codep++;
11252       length++;
11253     }
11254   return 0;
11255 }
11256
11257 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
11258    prefix byte.  */
11259
11260 static const char *
11261 prefix_name (int pref, int sizeflag)
11262 {
11263   static const char *rexes [16] =
11264     {
11265       "rex",            /* 0x40 */
11266       "rex.B",          /* 0x41 */
11267       "rex.X",          /* 0x42 */
11268       "rex.XB",         /* 0x43 */
11269       "rex.R",          /* 0x44 */
11270       "rex.RB",         /* 0x45 */
11271       "rex.RX",         /* 0x46 */
11272       "rex.RXB",        /* 0x47 */
11273       "rex.W",          /* 0x48 */
11274       "rex.WB",         /* 0x49 */
11275       "rex.WX",         /* 0x4a */
11276       "rex.WXB",        /* 0x4b */
11277       "rex.WR",         /* 0x4c */
11278       "rex.WRB",        /* 0x4d */
11279       "rex.WRX",        /* 0x4e */
11280       "rex.WRXB",       /* 0x4f */
11281     };
11282
11283   switch (pref)
11284     {
11285     /* REX prefixes family.  */
11286     case 0x40:
11287     case 0x41:
11288     case 0x42:
11289     case 0x43:
11290     case 0x44:
11291     case 0x45:
11292     case 0x46:
11293     case 0x47:
11294     case 0x48:
11295     case 0x49:
11296     case 0x4a:
11297     case 0x4b:
11298     case 0x4c:
11299     case 0x4d:
11300     case 0x4e:
11301     case 0x4f:
11302       return rexes [pref - 0x40];
11303     case 0xf3:
11304       return "repz";
11305     case 0xf2:
11306       return "repnz";
11307     case 0xf0:
11308       return "lock";
11309     case 0x2e:
11310       return "cs";
11311     case 0x36:
11312       return "ss";
11313     case 0x3e:
11314       return "ds";
11315     case 0x26:
11316       return "es";
11317     case 0x64:
11318       return "fs";
11319     case 0x65:
11320       return "gs";
11321     case 0x66:
11322       return (sizeflag & DFLAG) ? "data16" : "data32";
11323     case 0x67:
11324       if (address_mode == mode_64bit)
11325         return (sizeflag & AFLAG) ? "addr32" : "addr64";
11326       else
11327         return (sizeflag & AFLAG) ? "addr16" : "addr32";
11328     case FWAIT_OPCODE:
11329       return "fwait";
11330     case REP_PREFIX:
11331       return "rep";
11332     case XACQUIRE_PREFIX:
11333       return "xacquire";
11334     case XRELEASE_PREFIX:
11335       return "xrelease";
11336     case BND_PREFIX:
11337       return "bnd";
11338     case NOTRACK_PREFIX:
11339       return "notrack";
11340     default:
11341       return NULL;
11342     }
11343 }
11344
11345 static char op_out[MAX_OPERANDS][100];
11346 static int op_ad, op_index[MAX_OPERANDS];
11347 static int two_source_ops;
11348 static bfd_vma op_address[MAX_OPERANDS];
11349 static bfd_vma op_riprel[MAX_OPERANDS];
11350 static bfd_vma start_pc;
11351
11352 /*
11353  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
11354  *   (see topic "Redundant prefixes" in the "Differences from 8086"
11355  *   section of the "Virtual 8086 Mode" chapter.)
11356  * 'pc' should be the address of this instruction, it will
11357  *   be used to print the target address if this is a relative jump or call
11358  * The function returns the length of this instruction in bytes.
11359  */
11360
11361 static char intel_syntax;
11362 static char intel_mnemonic = !SYSV386_COMPAT;
11363 static char open_char;
11364 static char close_char;
11365 static char separator_char;
11366 static char scale_char;
11367
11368 enum x86_64_isa
11369 {
11370   amd64 = 0,
11371   intel64
11372 };
11373
11374 static enum x86_64_isa isa64;
11375
11376 /* Here for backwards compatibility.  When gdb stops using
11377    print_insn_i386_att and print_insn_i386_intel these functions can
11378    disappear, and print_insn_i386 be merged into print_insn.  */
11379 int
11380 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
11381 {
11382   intel_syntax = 0;
11383
11384   return print_insn (pc, info);
11385 }
11386
11387 int
11388 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
11389 {
11390   intel_syntax = 1;
11391
11392   return print_insn (pc, info);
11393 }
11394
11395 int
11396 print_insn_i386 (bfd_vma pc, disassemble_info *info)
11397 {
11398   intel_syntax = -1;
11399
11400   return print_insn (pc, info);
11401 }
11402
11403 void
11404 print_i386_disassembler_options (FILE *stream)
11405 {
11406   fprintf (stream, _("\n\
11407 The following i386/x86-64 specific disassembler options are supported for use\n\
11408 with the -M switch (multiple options should be separated by commas):\n"));
11409
11410   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
11411   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
11412   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
11413   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
11414   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
11415   fprintf (stream, _("  att-mnemonic\n"
11416                      "              Display instruction in AT&T mnemonic\n"));
11417   fprintf (stream, _("  intel-mnemonic\n"
11418                      "              Display instruction in Intel mnemonic\n"));
11419   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
11420   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
11421   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
11422   fprintf (stream, _("  data32      Assume 32bit data size\n"));
11423   fprintf (stream, _("  data16      Assume 16bit data size\n"));
11424   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
11425   fprintf (stream, _("  amd64       Display instruction in AMD64 ISA\n"));
11426   fprintf (stream, _("  intel64     Display instruction in Intel64 ISA\n"));
11427 }
11428
11429 /* Bad opcode.  */
11430 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
11431
11432 /* Get a pointer to struct dis386 with a valid name.  */
11433
11434 static const struct dis386 *
11435 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
11436 {
11437   int vindex, vex_table_index;
11438
11439   if (dp->name != NULL)
11440     return dp;
11441
11442   switch (dp->op[0].bytemode)
11443     {
11444     case USE_REG_TABLE:
11445       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
11446       break;
11447
11448     case USE_MOD_TABLE:
11449       vindex = modrm.mod == 0x3 ? 1 : 0;
11450       dp = &mod_table[dp->op[1].bytemode][vindex];
11451       break;
11452
11453     case USE_RM_TABLE:
11454       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
11455       break;
11456
11457     case USE_PREFIX_TABLE:
11458       if (need_vex)
11459         {
11460           /* The prefix in VEX is implicit.  */
11461           switch (vex.prefix)
11462             {
11463             case 0:
11464               vindex = 0;
11465               break;
11466             case REPE_PREFIX_OPCODE:
11467               vindex = 1;
11468               break;
11469             case DATA_PREFIX_OPCODE:
11470               vindex = 2;
11471               break;
11472             case REPNE_PREFIX_OPCODE:
11473               vindex = 3;
11474               break;
11475             default:
11476               abort ();
11477               break;
11478             }
11479         }
11480       else
11481         {
11482           int last_prefix = -1;
11483           int prefix = 0;
11484           vindex = 0;
11485           /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
11486              When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
11487              last one wins.  */
11488           if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
11489             {
11490               if (last_repz_prefix > last_repnz_prefix)
11491                 {
11492                   vindex = 1;
11493                   prefix = PREFIX_REPZ;
11494                   last_prefix = last_repz_prefix;
11495                 }
11496               else
11497                 {
11498                   vindex = 3;
11499                   prefix = PREFIX_REPNZ;
11500                   last_prefix = last_repnz_prefix;
11501                 }
11502
11503               /* Check if prefix should be ignored.  */
11504               if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
11505                      & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
11506                    & prefix) != 0)
11507                 vindex = 0;
11508             }
11509
11510           if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
11511             {
11512               vindex = 2;
11513               prefix = PREFIX_DATA;
11514               last_prefix = last_data_prefix;
11515             }
11516
11517           if (vindex != 0)
11518             {
11519               used_prefixes |= prefix;
11520               all_prefixes[last_prefix] = 0;
11521             }
11522         }
11523       dp = &prefix_table[dp->op[1].bytemode][vindex];
11524       break;
11525
11526     case USE_X86_64_TABLE:
11527       vindex = address_mode == mode_64bit ? 1 : 0;
11528       dp = &x86_64_table[dp->op[1].bytemode][vindex];
11529       break;
11530
11531     case USE_3BYTE_TABLE:
11532       FETCH_DATA (info, codep + 2);
11533       vindex = *codep++;
11534       dp = &three_byte_table[dp->op[1].bytemode][vindex];
11535       end_codep = codep;
11536       modrm.mod = (*codep >> 6) & 3;
11537       modrm.reg = (*codep >> 3) & 7;
11538       modrm.rm = *codep & 7;
11539       break;
11540
11541     case USE_VEX_LEN_TABLE:
11542       if (!need_vex)
11543         abort ();
11544
11545       switch (vex.length)
11546         {
11547         case 128:
11548           vindex = 0;
11549           break;
11550         case 256:
11551           vindex = 1;
11552           break;
11553         default:
11554           abort ();
11555           break;
11556         }
11557
11558       dp = &vex_len_table[dp->op[1].bytemode][vindex];
11559       break;
11560
11561     case USE_EVEX_LEN_TABLE:
11562       if (!vex.evex)
11563         abort ();
11564
11565       switch (vex.length)
11566         {
11567         case 128:
11568           vindex = 0;
11569           break;
11570         case 256:
11571           vindex = 1;
11572           break;
11573         case 512:
11574           vindex = 2;
11575           break;
11576         default:
11577           abort ();
11578           break;
11579         }
11580
11581       dp = &evex_len_table[dp->op[1].bytemode][vindex];
11582       break;
11583
11584     case USE_XOP_8F_TABLE:
11585       FETCH_DATA (info, codep + 3);
11586       /* All bits in the REX prefix are ignored.  */
11587       rex_ignored = rex;
11588       rex = ~(*codep >> 5) & 0x7;
11589
11590       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
11591       switch ((*codep & 0x1f))
11592         {
11593         default:
11594           dp = &bad_opcode;
11595           return dp;
11596         case 0x8:
11597           vex_table_index = XOP_08;
11598           break;
11599         case 0x9:
11600           vex_table_index = XOP_09;
11601           break;
11602         case 0xa:
11603           vex_table_index = XOP_0A;
11604           break;
11605         }
11606       codep++;
11607       vex.w = *codep & 0x80;
11608       if (vex.w && address_mode == mode_64bit)
11609         rex |= REX_W;
11610
11611       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11612       if (address_mode != mode_64bit)
11613         {
11614           /* In 16/32-bit mode REX_B is silently ignored.  */
11615           rex &= ~REX_B;
11616         }
11617
11618       vex.length = (*codep & 0x4) ? 256 : 128;
11619       switch ((*codep & 0x3))
11620         {
11621         case 0:
11622           break;
11623         case 1:
11624           vex.prefix = DATA_PREFIX_OPCODE;
11625           break;
11626         case 2:
11627           vex.prefix = REPE_PREFIX_OPCODE;
11628           break;
11629         case 3:
11630           vex.prefix = REPNE_PREFIX_OPCODE;
11631           break;
11632         }
11633       need_vex = 1;
11634       need_vex_reg = 1;
11635       codep++;
11636       vindex = *codep++;
11637       dp = &xop_table[vex_table_index][vindex];
11638
11639       end_codep = codep;
11640       FETCH_DATA (info, codep + 1);
11641       modrm.mod = (*codep >> 6) & 3;
11642       modrm.reg = (*codep >> 3) & 7;
11643       modrm.rm = *codep & 7;
11644       break;
11645
11646     case USE_VEX_C4_TABLE:
11647       /* VEX prefix.  */
11648       FETCH_DATA (info, codep + 3);
11649       /* All bits in the REX prefix are ignored.  */
11650       rex_ignored = rex;
11651       rex = ~(*codep >> 5) & 0x7;
11652       switch ((*codep & 0x1f))
11653         {
11654         default:
11655           dp = &bad_opcode;
11656           return dp;
11657         case 0x1:
11658           vex_table_index = VEX_0F;
11659           break;
11660         case 0x2:
11661           vex_table_index = VEX_0F38;
11662           break;
11663         case 0x3:
11664           vex_table_index = VEX_0F3A;
11665           break;
11666         }
11667       codep++;
11668       vex.w = *codep & 0x80;
11669       if (address_mode == mode_64bit)
11670         {
11671           if (vex.w)
11672             rex |= REX_W;
11673         }
11674       else
11675         {
11676           /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
11677              is ignored, other REX bits are 0 and the highest bit in
11678              VEX.vvvv is also ignored (but we mustn't clear it here).  */
11679           rex = 0;
11680         }
11681       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11682       vex.length = (*codep & 0x4) ? 256 : 128;
11683       switch ((*codep & 0x3))
11684         {
11685         case 0:
11686           break;
11687         case 1:
11688           vex.prefix = DATA_PREFIX_OPCODE;
11689           break;
11690         case 2:
11691           vex.prefix = REPE_PREFIX_OPCODE;
11692           break;
11693         case 3:
11694           vex.prefix = REPNE_PREFIX_OPCODE;
11695           break;
11696         }
11697       need_vex = 1;
11698       need_vex_reg = 1;
11699       codep++;
11700       vindex = *codep++;
11701       dp = &vex_table[vex_table_index][vindex];
11702       end_codep = codep;
11703       /* There is no MODRM byte for VEX0F 77.  */
11704       if (vex_table_index != VEX_0F || vindex != 0x77)
11705         {
11706           FETCH_DATA (info, codep + 1);
11707           modrm.mod = (*codep >> 6) & 3;
11708           modrm.reg = (*codep >> 3) & 7;
11709           modrm.rm = *codep & 7;
11710         }
11711       break;
11712
11713     case USE_VEX_C5_TABLE:
11714       /* VEX prefix.  */
11715       FETCH_DATA (info, codep + 2);
11716       /* All bits in the REX prefix are ignored.  */
11717       rex_ignored = rex;
11718       rex = (*codep & 0x80) ? 0 : REX_R;
11719
11720       /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
11721          VEX.vvvv is 1.  */
11722       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11723       vex.length = (*codep & 0x4) ? 256 : 128;
11724       switch ((*codep & 0x3))
11725         {
11726         case 0:
11727           break;
11728         case 1:
11729           vex.prefix = DATA_PREFIX_OPCODE;
11730           break;
11731         case 2:
11732           vex.prefix = REPE_PREFIX_OPCODE;
11733           break;
11734         case 3:
11735           vex.prefix = REPNE_PREFIX_OPCODE;
11736           break;
11737         }
11738       need_vex = 1;
11739       need_vex_reg = 1;
11740       codep++;
11741       vindex = *codep++;
11742       dp = &vex_table[dp->op[1].bytemode][vindex];
11743       end_codep = codep;
11744       /* There is no MODRM byte for VEX 77.  */
11745       if (vindex != 0x77)
11746         {
11747           FETCH_DATA (info, codep + 1);
11748           modrm.mod = (*codep >> 6) & 3;
11749           modrm.reg = (*codep >> 3) & 7;
11750           modrm.rm = *codep & 7;
11751         }
11752       break;
11753
11754     case USE_VEX_W_TABLE:
11755       if (!need_vex)
11756         abort ();
11757
11758       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
11759       break;
11760
11761     case USE_EVEX_TABLE:
11762       two_source_ops = 0;
11763       /* EVEX prefix.  */
11764       vex.evex = 1;
11765       FETCH_DATA (info, codep + 4);
11766       /* All bits in the REX prefix are ignored.  */
11767       rex_ignored = rex;
11768       /* The first byte after 0x62.  */
11769       rex = ~(*codep >> 5) & 0x7;
11770       vex.r = *codep & 0x10;
11771       switch ((*codep & 0xf))
11772         {
11773         default:
11774           return &bad_opcode;
11775         case 0x1:
11776           vex_table_index = EVEX_0F;
11777           break;
11778         case 0x2:
11779           vex_table_index = EVEX_0F38;
11780           break;
11781         case 0x3:
11782           vex_table_index = EVEX_0F3A;
11783           break;
11784         }
11785
11786       /* The second byte after 0x62.  */
11787       codep++;
11788       vex.w = *codep & 0x80;
11789       if (vex.w && address_mode == mode_64bit)
11790         rex |= REX_W;
11791
11792       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11793
11794       /* The U bit.  */
11795       if (!(*codep & 0x4))
11796         return &bad_opcode;
11797
11798       switch ((*codep & 0x3))
11799         {
11800         case 0:
11801           break;
11802         case 1:
11803           vex.prefix = DATA_PREFIX_OPCODE;
11804           break;
11805         case 2:
11806           vex.prefix = REPE_PREFIX_OPCODE;
11807           break;
11808         case 3:
11809           vex.prefix = REPNE_PREFIX_OPCODE;
11810           break;
11811         }
11812
11813       /* The third byte after 0x62.  */
11814       codep++;
11815
11816       /* Remember the static rounding bits.  */
11817       vex.ll = (*codep >> 5) & 3;
11818       vex.b = (*codep & 0x10) != 0;
11819
11820       vex.v = *codep & 0x8;
11821       vex.mask_register_specifier = *codep & 0x7;
11822       vex.zeroing = *codep & 0x80;
11823
11824       if (address_mode != mode_64bit)
11825         {
11826           /* In 16/32-bit mode silently ignore following bits.  */
11827           rex &= ~REX_B;
11828           vex.r = 1;
11829           vex.v = 1;
11830         }
11831
11832       need_vex = 1;
11833       need_vex_reg = 1;
11834       codep++;
11835       vindex = *codep++;
11836       dp = &evex_table[vex_table_index][vindex];
11837       end_codep = codep;
11838       FETCH_DATA (info, codep + 1);
11839       modrm.mod = (*codep >> 6) & 3;
11840       modrm.reg = (*codep >> 3) & 7;
11841       modrm.rm = *codep & 7;
11842
11843       /* Set vector length.  */
11844       if (modrm.mod == 3 && vex.b)
11845         vex.length = 512;
11846       else
11847         {
11848           switch (vex.ll)
11849             {
11850             case 0x0:
11851               vex.length = 128;
11852               break;
11853             case 0x1:
11854               vex.length = 256;
11855               break;
11856             case 0x2:
11857               vex.length = 512;
11858               break;
11859             default:
11860               return &bad_opcode;
11861             }
11862         }
11863       break;
11864
11865     case 0:
11866       dp = &bad_opcode;
11867       break;
11868
11869     default:
11870       abort ();
11871     }
11872
11873   if (dp->name != NULL)
11874     return dp;
11875   else
11876     return get_valid_dis386 (dp, info);
11877 }
11878
11879 static void
11880 get_sib (disassemble_info *info, int sizeflag)
11881 {
11882   /* If modrm.mod == 3, operand must be register.  */
11883   if (need_modrm
11884       && ((sizeflag & AFLAG) || address_mode == mode_64bit)
11885       && modrm.mod != 3
11886       && modrm.rm == 4)
11887     {
11888       FETCH_DATA (info, codep + 2);
11889       sib.index = (codep [1] >> 3) & 7;
11890       sib.scale = (codep [1] >> 6) & 3;
11891       sib.base = codep [1] & 7;
11892     }
11893 }
11894
11895 static int
11896 print_insn (bfd_vma pc, disassemble_info *info)
11897 {
11898   const struct dis386 *dp;
11899   int i;
11900   char *op_txt[MAX_OPERANDS];
11901   int needcomma;
11902   int sizeflag, orig_sizeflag;
11903   const char *p;
11904   struct dis_private priv;
11905   int prefix_length;
11906
11907   priv.orig_sizeflag = AFLAG | DFLAG;
11908   if ((info->mach & bfd_mach_i386_i386) != 0)
11909     address_mode = mode_32bit;
11910   else if (info->mach == bfd_mach_i386_i8086)
11911     {
11912       address_mode = mode_16bit;
11913       priv.orig_sizeflag = 0;
11914     }
11915   else
11916     address_mode = mode_64bit;
11917
11918   if (intel_syntax == (char) -1)
11919     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
11920
11921   for (p = info->disassembler_options; p != NULL; )
11922     {
11923       if (CONST_STRNEQ (p, "amd64"))
11924         isa64 = amd64;
11925       else if (CONST_STRNEQ (p, "intel64"))
11926         isa64 = intel64;
11927       else if (CONST_STRNEQ (p, "x86-64"))
11928         {
11929           address_mode = mode_64bit;
11930           priv.orig_sizeflag = AFLAG | DFLAG;
11931         }
11932       else if (CONST_STRNEQ (p, "i386"))
11933         {
11934           address_mode = mode_32bit;
11935           priv.orig_sizeflag = AFLAG | DFLAG;
11936         }
11937       else if (CONST_STRNEQ (p, "i8086"))
11938         {
11939           address_mode = mode_16bit;
11940           priv.orig_sizeflag = 0;
11941         }
11942       else if (CONST_STRNEQ (p, "intel"))
11943         {
11944           intel_syntax = 1;
11945           if (CONST_STRNEQ (p + 5, "-mnemonic"))
11946             intel_mnemonic = 1;
11947         }
11948       else if (CONST_STRNEQ (p, "att"))
11949         {
11950           intel_syntax = 0;
11951           if (CONST_STRNEQ (p + 3, "-mnemonic"))
11952             intel_mnemonic = 0;
11953         }
11954       else if (CONST_STRNEQ (p, "addr"))
11955         {
11956           if (address_mode == mode_64bit)
11957             {
11958               if (p[4] == '3' && p[5] == '2')
11959                 priv.orig_sizeflag &= ~AFLAG;
11960               else if (p[4] == '6' && p[5] == '4')
11961                 priv.orig_sizeflag |= AFLAG;
11962             }
11963           else
11964             {
11965               if (p[4] == '1' && p[5] == '6')
11966                 priv.orig_sizeflag &= ~AFLAG;
11967               else if (p[4] == '3' && p[5] == '2')
11968                 priv.orig_sizeflag |= AFLAG;
11969             }
11970         }
11971       else if (CONST_STRNEQ (p, "data"))
11972         {
11973           if (p[4] == '1' && p[5] == '6')
11974             priv.orig_sizeflag &= ~DFLAG;
11975           else if (p[4] == '3' && p[5] == '2')
11976             priv.orig_sizeflag |= DFLAG;
11977         }
11978       else if (CONST_STRNEQ (p, "suffix"))
11979         priv.orig_sizeflag |= SUFFIX_ALWAYS;
11980
11981       p = strchr (p, ',');
11982       if (p != NULL)
11983         p++;
11984     }
11985
11986   if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
11987     {
11988       (*info->fprintf_func) (info->stream,
11989                              _("64-bit address is disabled"));
11990       return -1;
11991     }
11992
11993   if (intel_syntax)
11994     {
11995       names64 = intel_names64;
11996       names32 = intel_names32;
11997       names16 = intel_names16;
11998       names8 = intel_names8;
11999       names8rex = intel_names8rex;
12000       names_seg = intel_names_seg;
12001       names_mm = intel_names_mm;
12002       names_bnd = intel_names_bnd;
12003       names_xmm = intel_names_xmm;
12004       names_ymm = intel_names_ymm;
12005       names_zmm = intel_names_zmm;
12006       index64 = intel_index64;
12007       index32 = intel_index32;
12008       names_mask = intel_names_mask;
12009       index16 = intel_index16;
12010       open_char = '[';
12011       close_char = ']';
12012       separator_char = '+';
12013       scale_char = '*';
12014     }
12015   else
12016     {
12017       names64 = att_names64;
12018       names32 = att_names32;
12019       names16 = att_names16;
12020       names8 = att_names8;
12021       names8rex = att_names8rex;
12022       names_seg = att_names_seg;
12023       names_mm = att_names_mm;
12024       names_bnd = att_names_bnd;
12025       names_xmm = att_names_xmm;
12026       names_ymm = att_names_ymm;
12027       names_zmm = att_names_zmm;
12028       index64 = att_index64;
12029       index32 = att_index32;
12030       names_mask = att_names_mask;
12031       index16 = att_index16;
12032       open_char = '(';
12033       close_char =  ')';
12034       separator_char = ',';
12035       scale_char = ',';
12036     }
12037
12038   /* The output looks better if we put 7 bytes on a line, since that
12039      puts most long word instructions on a single line.  Use 8 bytes
12040      for Intel L1OM.  */
12041   if ((info->mach & bfd_mach_l1om) != 0)
12042     info->bytes_per_line = 8;
12043   else
12044     info->bytes_per_line = 7;
12045
12046   info->private_data = &priv;
12047   priv.max_fetched = priv.the_buffer;
12048   priv.insn_start = pc;
12049
12050   obuf[0] = 0;
12051   for (i = 0; i < MAX_OPERANDS; ++i)
12052     {
12053       op_out[i][0] = 0;
12054       op_index[i] = -1;
12055     }
12056
12057   the_info = info;
12058   start_pc = pc;
12059   start_codep = priv.the_buffer;
12060   codep = priv.the_buffer;
12061
12062   if (OPCODES_SIGSETJMP (priv.bailout) != 0)
12063     {
12064       const char *name;
12065
12066       /* Getting here means we tried for data but didn't get it.  That
12067          means we have an incomplete instruction of some sort.  Just
12068          print the first byte as a prefix or a .byte pseudo-op.  */
12069       if (codep > priv.the_buffer)
12070         {
12071           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
12072           if (name != NULL)
12073             (*info->fprintf_func) (info->stream, "%s", name);
12074           else
12075             {
12076               /* Just print the first byte as a .byte instruction.  */
12077               (*info->fprintf_func) (info->stream, ".byte 0x%x",
12078                                      (unsigned int) priv.the_buffer[0]);
12079             }
12080
12081           return 1;
12082         }
12083
12084       return -1;
12085     }
12086
12087   obufp = obuf;
12088   sizeflag = priv.orig_sizeflag;
12089
12090   if (!ckprefix () || rex_used)
12091     {
12092       /* Too many prefixes or unused REX prefixes.  */
12093       for (i = 0;
12094            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
12095            i++)
12096         (*info->fprintf_func) (info->stream, "%s%s",
12097                                i == 0 ? "" : " ",
12098                                prefix_name (all_prefixes[i], sizeflag));
12099       return i;
12100     }
12101
12102   insn_codep = codep;
12103
12104   FETCH_DATA (info, codep + 1);
12105   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
12106
12107   if (((prefixes & PREFIX_FWAIT)
12108        && ((*codep < 0xd8) || (*codep > 0xdf))))
12109     {
12110       /* Handle prefixes before fwait.  */
12111       for (i = 0; i < fwait_prefix && all_prefixes[i];
12112            i++)
12113         (*info->fprintf_func) (info->stream, "%s ",
12114                                prefix_name (all_prefixes[i], sizeflag));
12115       (*info->fprintf_func) (info->stream, "fwait");
12116       return i + 1;
12117     }
12118
12119   if (*codep == 0x0f)
12120     {
12121       unsigned char threebyte;
12122
12123       codep++;
12124       FETCH_DATA (info, codep + 1);
12125       threebyte = *codep;
12126       dp = &dis386_twobyte[threebyte];
12127       need_modrm = twobyte_has_modrm[*codep];
12128       codep++;
12129     }
12130   else
12131     {
12132       dp = &dis386[*codep];
12133       need_modrm = onebyte_has_modrm[*codep];
12134       codep++;
12135     }
12136
12137   /* Save sizeflag for printing the extra prefixes later before updating
12138      it for mnemonic and operand processing.  The prefix names depend
12139      only on the address mode.  */
12140   orig_sizeflag = sizeflag;
12141   if (prefixes & PREFIX_ADDR)
12142     sizeflag ^= AFLAG;
12143   if ((prefixes & PREFIX_DATA))
12144     sizeflag ^= DFLAG;
12145
12146   end_codep = codep;
12147   if (need_modrm)
12148     {
12149       FETCH_DATA (info, codep + 1);
12150       modrm.mod = (*codep >> 6) & 3;
12151       modrm.reg = (*codep >> 3) & 7;
12152       modrm.rm = *codep & 7;
12153     }
12154
12155   need_vex = 0;
12156   need_vex_reg = 0;
12157   vex_w_done = 0;
12158   memset (&vex, 0, sizeof (vex));
12159
12160   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
12161     {
12162       get_sib (info, sizeflag);
12163       dofloat (sizeflag);
12164     }
12165   else
12166     {
12167       dp = get_valid_dis386 (dp, info);
12168       if (dp != NULL && putop (dp->name, sizeflag) == 0)
12169         {
12170           get_sib (info, sizeflag);
12171           for (i = 0; i < MAX_OPERANDS; ++i)
12172             {
12173               obufp = op_out[i];
12174               op_ad = MAX_OPERANDS - 1 - i;
12175               if (dp->op[i].rtn)
12176                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
12177               /* For EVEX instruction after the last operand masking
12178                  should be printed.  */
12179               if (i == 0 && vex.evex)
12180                 {
12181                   /* Don't print {%k0}.  */
12182                   if (vex.mask_register_specifier)
12183                     {
12184                       oappend ("{");
12185                       oappend (names_mask[vex.mask_register_specifier]);
12186                       oappend ("}");
12187                     }
12188                   if (vex.zeroing)
12189                     oappend ("{z}");
12190                 }
12191             }
12192         }
12193     }
12194
12195   /* Check if the REX prefix is used.  */
12196   if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)
12197     all_prefixes[last_rex_prefix] = 0;
12198
12199   /* Check if the SEG prefix is used.  */
12200   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
12201                    | PREFIX_FS | PREFIX_GS)) != 0
12202       && (used_prefixes & active_seg_prefix) != 0)
12203     all_prefixes[last_seg_prefix] = 0;
12204
12205   /* Check if the ADDR prefix is used.  */
12206   if ((prefixes & PREFIX_ADDR) != 0
12207       && (used_prefixes & PREFIX_ADDR) != 0)
12208     all_prefixes[last_addr_prefix] = 0;
12209
12210   /* Check if the DATA prefix is used.  */
12211   if ((prefixes & PREFIX_DATA) != 0
12212       && (used_prefixes & PREFIX_DATA) != 0)
12213     all_prefixes[last_data_prefix] = 0;
12214
12215   /* Print the extra prefixes.  */
12216   prefix_length = 0;
12217   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12218     if (all_prefixes[i])
12219       {
12220         const char *name;
12221         name = prefix_name (all_prefixes[i], orig_sizeflag);
12222         if (name == NULL)
12223           abort ();
12224         prefix_length += strlen (name) + 1;
12225         (*info->fprintf_func) (info->stream, "%s ", name);
12226       }
12227
12228   /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
12229      unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
12230      used by putop and MMX/SSE operand and may be overriden by the
12231      PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
12232      separately.  */
12233   if (dp->prefix_requirement == PREFIX_OPCODE
12234       && dp != &bad_opcode
12235       && (((prefixes
12236             & (PREFIX_REPZ | PREFIX_REPNZ)) != 0
12237            && (used_prefixes
12238                & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
12239           || ((((prefixes
12240                  & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
12241                 == PREFIX_DATA)
12242                && (used_prefixes & PREFIX_DATA) == 0))))
12243     {
12244       (*info->fprintf_func) (info->stream, "(bad)");
12245       return end_codep - priv.the_buffer;
12246     }
12247
12248   /* Check maximum code length.  */
12249   if ((codep - start_codep) > MAX_CODE_LENGTH)
12250     {
12251       (*info->fprintf_func) (info->stream, "(bad)");
12252       return MAX_CODE_LENGTH;
12253     }
12254
12255   obufp = mnemonicendp;
12256   for (i = strlen (obuf) + prefix_length; i < 6; i++)
12257     oappend (" ");
12258   oappend (" ");
12259   (*info->fprintf_func) (info->stream, "%s", obuf);
12260
12261   /* The enter and bound instructions are printed with operands in the same
12262      order as the intel book; everything else is printed in reverse order.  */
12263   if (intel_syntax || two_source_ops)
12264     {
12265       bfd_vma riprel;
12266
12267       for (i = 0; i < MAX_OPERANDS; ++i)
12268         op_txt[i] = op_out[i];
12269
12270       if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
12271           && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
12272         {
12273           op_txt[2] = op_out[3];
12274           op_txt[3] = op_out[2];
12275         }
12276
12277       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
12278         {
12279           op_ad = op_index[i];
12280           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
12281           op_index[MAX_OPERANDS - 1 - i] = op_ad;
12282           riprel = op_riprel[i];
12283           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
12284           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
12285         }
12286     }
12287   else
12288     {
12289       for (i = 0; i < MAX_OPERANDS; ++i)
12290         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
12291     }
12292
12293   needcomma = 0;
12294   for (i = 0; i < MAX_OPERANDS; ++i)
12295     if (*op_txt[i])
12296       {
12297         if (needcomma)
12298           (*info->fprintf_func) (info->stream, ",");
12299         if (op_index[i] != -1 && !op_riprel[i])
12300           (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
12301         else
12302           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
12303         needcomma = 1;
12304       }
12305
12306   for (i = 0; i < MAX_OPERANDS; i++)
12307     if (op_index[i] != -1 && op_riprel[i])
12308       {
12309         (*info->fprintf_func) (info->stream, "        # ");
12310         (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
12311                                                 + op_address[op_index[i]]), info);
12312         break;
12313       }
12314   return codep - priv.the_buffer;
12315 }
12316
12317 static const char *float_mem[] = {
12318   /* d8 */
12319   "fadd{s|}",
12320   "fmul{s|}",
12321   "fcom{s|}",
12322   "fcomp{s|}",
12323   "fsub{s|}",
12324   "fsubr{s|}",
12325   "fdiv{s|}",
12326   "fdivr{s|}",
12327   /* d9 */
12328   "fld{s|}",
12329   "(bad)",
12330   "fst{s|}",
12331   "fstp{s|}",
12332   "fldenvIC",
12333   "fldcw",
12334   "fNstenvIC",
12335   "fNstcw",
12336   /* da */
12337   "fiadd{l|}",
12338   "fimul{l|}",
12339   "ficom{l|}",
12340   "ficomp{l|}",
12341   "fisub{l|}",
12342   "fisubr{l|}",
12343   "fidiv{l|}",
12344   "fidivr{l|}",
12345   /* db */
12346   "fild{l|}",
12347   "fisttp{l|}",
12348   "fist{l|}",
12349   "fistp{l|}",
12350   "(bad)",
12351   "fld{t||t|}",
12352   "(bad)",
12353   "fstp{t||t|}",
12354   /* dc */
12355   "fadd{l|}",
12356   "fmul{l|}",
12357   "fcom{l|}",
12358   "fcomp{l|}",
12359   "fsub{l|}",
12360   "fsubr{l|}",
12361   "fdiv{l|}",
12362   "fdivr{l|}",
12363   /* dd */
12364   "fld{l|}",
12365   "fisttp{ll|}",
12366   "fst{l||}",
12367   "fstp{l|}",
12368   "frstorIC",
12369   "(bad)",
12370   "fNsaveIC",
12371   "fNstsw",
12372   /* de */
12373   "fiadd{s|}",
12374   "fimul{s|}",
12375   "ficom{s|}",
12376   "ficomp{s|}",
12377   "fisub{s|}",
12378   "fisubr{s|}",
12379   "fidiv{s|}",
12380   "fidivr{s|}",
12381   /* df */
12382   "fild{s|}",
12383   "fisttp{s|}",
12384   "fist{s|}",
12385   "fistp{s|}",
12386   "fbld",
12387   "fild{ll|}",
12388   "fbstp",
12389   "fistp{ll|}",
12390 };
12391
12392 static const unsigned char float_mem_mode[] = {
12393   /* d8 */
12394   d_mode,
12395   d_mode,
12396   d_mode,
12397   d_mode,
12398   d_mode,
12399   d_mode,
12400   d_mode,
12401   d_mode,
12402   /* d9 */
12403   d_mode,
12404   0,
12405   d_mode,
12406   d_mode,
12407   0,
12408   w_mode,
12409   0,
12410   w_mode,
12411   /* da */
12412   d_mode,
12413   d_mode,
12414   d_mode,
12415   d_mode,
12416   d_mode,
12417   d_mode,
12418   d_mode,
12419   d_mode,
12420   /* db */
12421   d_mode,
12422   d_mode,
12423   d_mode,
12424   d_mode,
12425   0,
12426   t_mode,
12427   0,
12428   t_mode,
12429   /* dc */
12430   q_mode,
12431   q_mode,
12432   q_mode,
12433   q_mode,
12434   q_mode,
12435   q_mode,
12436   q_mode,
12437   q_mode,
12438   /* dd */
12439   q_mode,
12440   q_mode,
12441   q_mode,
12442   q_mode,
12443   0,
12444   0,
12445   0,
12446   w_mode,
12447   /* de */
12448   w_mode,
12449   w_mode,
12450   w_mode,
12451   w_mode,
12452   w_mode,
12453   w_mode,
12454   w_mode,
12455   w_mode,
12456   /* df */
12457   w_mode,
12458   w_mode,
12459   w_mode,
12460   w_mode,
12461   t_mode,
12462   q_mode,
12463   t_mode,
12464   q_mode
12465 };
12466
12467 #define ST { OP_ST, 0 }
12468 #define STi { OP_STi, 0 }
12469
12470 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
12471 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
12472 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
12473 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
12474 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
12475 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
12476 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
12477 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
12478 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
12479
12480 static const struct dis386 float_reg[][8] = {
12481   /* d8 */
12482   {
12483     { "fadd",   { ST, STi }, 0 },
12484     { "fmul",   { ST, STi }, 0 },
12485     { "fcom",   { STi }, 0 },
12486     { "fcomp",  { STi }, 0 },
12487     { "fsub",   { ST, STi }, 0 },
12488     { "fsubr",  { ST, STi }, 0 },
12489     { "fdiv",   { ST, STi }, 0 },
12490     { "fdivr",  { ST, STi }, 0 },
12491   },
12492   /* d9 */
12493   {
12494     { "fld",    { STi }, 0 },
12495     { "fxch",   { STi }, 0 },
12496     { FGRPd9_2 },
12497     { Bad_Opcode },
12498     { FGRPd9_4 },
12499     { FGRPd9_5 },
12500     { FGRPd9_6 },
12501     { FGRPd9_7 },
12502   },
12503   /* da */
12504   {
12505     { "fcmovb", { ST, STi }, 0 },
12506     { "fcmove", { ST, STi }, 0 },
12507     { "fcmovbe",{ ST, STi }, 0 },
12508     { "fcmovu", { ST, STi }, 0 },
12509     { Bad_Opcode },
12510     { FGRPda_5 },
12511     { Bad_Opcode },
12512     { Bad_Opcode },
12513   },
12514   /* db */
12515   {
12516     { "fcmovnb",{ ST, STi }, 0 },
12517     { "fcmovne",{ ST, STi }, 0 },
12518     { "fcmovnbe",{ ST, STi }, 0 },
12519     { "fcmovnu",{ ST, STi }, 0 },
12520     { FGRPdb_4 },
12521     { "fucomi", { ST, STi }, 0 },
12522     { "fcomi",  { ST, STi }, 0 },
12523     { Bad_Opcode },
12524   },
12525   /* dc */
12526   {
12527     { "fadd",   { STi, ST }, 0 },
12528     { "fmul",   { STi, ST }, 0 },
12529     { Bad_Opcode },
12530     { Bad_Opcode },
12531     { "fsub{!M|r}",     { STi, ST }, 0 },
12532     { "fsub{M|}",       { STi, ST }, 0 },
12533     { "fdiv{!M|r}",     { STi, ST }, 0 },
12534     { "fdiv{M|}",       { STi, ST }, 0 },
12535   },
12536   /* dd */
12537   {
12538     { "ffree",  { STi }, 0 },
12539     { Bad_Opcode },
12540     { "fst",    { STi }, 0 },
12541     { "fstp",   { STi }, 0 },
12542     { "fucom",  { STi }, 0 },
12543     { "fucomp", { STi }, 0 },
12544     { Bad_Opcode },
12545     { Bad_Opcode },
12546   },
12547   /* de */
12548   {
12549     { "faddp",  { STi, ST }, 0 },
12550     { "fmulp",  { STi, ST }, 0 },
12551     { Bad_Opcode },
12552     { FGRPde_3 },
12553     { "fsub{!M|r}p",    { STi, ST }, 0 },
12554     { "fsub{M|}p",      { STi, ST }, 0 },
12555     { "fdiv{!M|r}p",    { STi, ST }, 0 },
12556     { "fdiv{M|}p",      { STi, ST }, 0 },
12557   },
12558   /* df */
12559   {
12560     { "ffreep", { STi }, 0 },
12561     { Bad_Opcode },
12562     { Bad_Opcode },
12563     { Bad_Opcode },
12564     { FGRPdf_4 },
12565     { "fucomip", { ST, STi }, 0 },
12566     { "fcomip", { ST, STi }, 0 },
12567     { Bad_Opcode },
12568   },
12569 };
12570
12571 static char *fgrps[][8] = {
12572   /* Bad opcode 0 */
12573   {
12574     "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12575   },
12576
12577   /* d9_2  1 */
12578   {
12579     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12580   },
12581
12582   /* d9_4  2 */
12583   {
12584     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
12585   },
12586
12587   /* d9_5  3 */
12588   {
12589     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
12590   },
12591
12592   /* d9_6  4 */
12593   {
12594     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
12595   },
12596
12597   /* d9_7  5 */
12598   {
12599     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
12600   },
12601
12602   /* da_5  6 */
12603   {
12604     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12605   },
12606
12607   /* db_4  7 */
12608   {
12609     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
12610     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
12611   },
12612
12613   /* de_3  8 */
12614   {
12615     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12616   },
12617
12618   /* df_4  9 */
12619   {
12620     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12621   },
12622 };
12623
12624 static void
12625 swap_operand (void)
12626 {
12627   mnemonicendp[0] = '.';
12628   mnemonicendp[1] = 's';
12629   mnemonicendp += 2;
12630 }
12631
12632 static void
12633 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
12634                int sizeflag ATTRIBUTE_UNUSED)
12635 {
12636   /* Skip mod/rm byte.  */
12637   MODRM_CHECK;
12638   codep++;
12639 }
12640
12641 static void
12642 dofloat (int sizeflag)
12643 {
12644   const struct dis386 *dp;
12645   unsigned char floatop;
12646
12647   floatop = codep[-1];
12648
12649   if (modrm.mod != 3)
12650     {
12651       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
12652
12653       putop (float_mem[fp_indx], sizeflag);
12654       obufp = op_out[0];
12655       op_ad = 2;
12656       OP_E (float_mem_mode[fp_indx], sizeflag);
12657       return;
12658     }
12659   /* Skip mod/rm byte.  */
12660   MODRM_CHECK;
12661   codep++;
12662
12663   dp = &float_reg[floatop - 0xd8][modrm.reg];
12664   if (dp->name == NULL)
12665     {
12666       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
12667
12668       /* Instruction fnstsw is only one with strange arg.  */
12669       if (floatop == 0xdf && codep[-1] == 0xe0)
12670         strcpy (op_out[0], names16[0]);
12671     }
12672   else
12673     {
12674       putop (dp->name, sizeflag);
12675
12676       obufp = op_out[0];
12677       op_ad = 2;
12678       if (dp->op[0].rtn)
12679         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
12680
12681       obufp = op_out[1];
12682       op_ad = 1;
12683       if (dp->op[1].rtn)
12684         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
12685     }
12686 }
12687
12688 /* Like oappend (below), but S is a string starting with '%'.
12689    In Intel syntax, the '%' is elided.  */
12690 static void
12691 oappend_maybe_intel (const char *s)
12692 {
12693   oappend (s + intel_syntax);
12694 }
12695
12696 static void
12697 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12698 {
12699   oappend_maybe_intel ("%st");
12700 }
12701
12702 static void
12703 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12704 {
12705   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
12706   oappend_maybe_intel (scratchbuf);
12707 }
12708
12709 /* Capital letters in template are macros.  */
12710 static int
12711 putop (const char *in_template, int sizeflag)
12712 {
12713   const char *p;
12714   int alt = 0;
12715   int cond = 1;
12716   unsigned int l = 0, len = 1;
12717   char last[4];
12718
12719 #define SAVE_LAST(c)                    \
12720   if (l < len && l < sizeof (last))     \
12721     last[l++] = c;                      \
12722   else                                  \
12723     abort ();
12724
12725   for (p = in_template; *p; p++)
12726     {
12727       switch (*p)
12728         {
12729         default:
12730           *obufp++ = *p;
12731           break;
12732         case '%':
12733           len++;
12734           break;
12735         case '!':
12736           cond = 0;
12737           break;
12738         case '{':
12739           if (intel_syntax)
12740             {
12741               while (*++p != '|')
12742                 if (*p == '}' || *p == '\0')
12743                   abort ();
12744             }
12745           /* Fall through.  */
12746         case 'I':
12747           alt = 1;
12748           continue;
12749         case '|':
12750           while (*++p != '}')
12751             {
12752               if (*p == '\0')
12753                 abort ();
12754             }
12755           break;
12756         case '}':
12757           break;
12758         case 'A':
12759           if (intel_syntax)
12760             break;
12761           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12762             *obufp++ = 'b';
12763           break;
12764         case 'B':
12765           if (l == 0 && len == 1)
12766             {
12767 case_B:
12768               if (intel_syntax)
12769                 break;
12770               if (sizeflag & SUFFIX_ALWAYS)
12771                 *obufp++ = 'b';
12772             }
12773           else
12774             {
12775               if (l != 1
12776                   || len != 2
12777                   || last[0] != 'L')
12778                 {
12779                   SAVE_LAST (*p);
12780                   break;
12781                 }
12782
12783               if (address_mode == mode_64bit
12784                   && !(prefixes & PREFIX_ADDR))
12785                 {
12786                   *obufp++ = 'a';
12787                   *obufp++ = 'b';
12788                   *obufp++ = 's';
12789                 }
12790
12791               goto case_B;
12792             }
12793           break;
12794         case 'C':
12795           if (intel_syntax && !alt)
12796             break;
12797           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
12798             {
12799               if (sizeflag & DFLAG)
12800                 *obufp++ = intel_syntax ? 'd' : 'l';
12801               else
12802                 *obufp++ = intel_syntax ? 'w' : 's';
12803               used_prefixes |= (prefixes & PREFIX_DATA);
12804             }
12805           break;
12806         case 'D':
12807           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
12808             break;
12809           USED_REX (REX_W);
12810           if (modrm.mod == 3)
12811             {
12812               if (rex & REX_W)
12813                 *obufp++ = 'q';
12814               else
12815                 {
12816                   if (sizeflag & DFLAG)
12817                     *obufp++ = intel_syntax ? 'd' : 'l';
12818                   else
12819                     *obufp++ = 'w';
12820                   used_prefixes |= (prefixes & PREFIX_DATA);
12821                 }
12822             }
12823           else
12824             *obufp++ = 'w';
12825           break;
12826         case 'E':               /* For jcxz/jecxz */
12827           if (address_mode == mode_64bit)
12828             {
12829               if (sizeflag & AFLAG)
12830                 *obufp++ = 'r';
12831               else
12832                 *obufp++ = 'e';
12833             }
12834           else
12835             if (sizeflag & AFLAG)
12836               *obufp++ = 'e';
12837           used_prefixes |= (prefixes & PREFIX_ADDR);
12838           break;
12839         case 'F':
12840           if (intel_syntax)
12841             break;
12842           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
12843             {
12844               if (sizeflag & AFLAG)
12845                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
12846               else
12847                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
12848               used_prefixes |= (prefixes & PREFIX_ADDR);
12849             }
12850           break;
12851         case 'G':
12852           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
12853             break;
12854           if ((rex & REX_W) || (sizeflag & DFLAG))
12855             *obufp++ = 'l';
12856           else
12857             *obufp++ = 'w';
12858           if (!(rex & REX_W))
12859             used_prefixes |= (prefixes & PREFIX_DATA);
12860           break;
12861         case 'H':
12862           if (intel_syntax)
12863             break;
12864           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
12865               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
12866             {
12867               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
12868               *obufp++ = ',';
12869               *obufp++ = 'p';
12870               if (prefixes & PREFIX_DS)
12871                 *obufp++ = 't';
12872               else
12873                 *obufp++ = 'n';
12874             }
12875           break;
12876         case 'J':
12877           if (intel_syntax)
12878             break;
12879           *obufp++ = 'l';
12880           break;
12881         case 'K':
12882           USED_REX (REX_W);
12883           if (rex & REX_W)
12884             *obufp++ = 'q';
12885           else
12886             *obufp++ = 'd';
12887           break;
12888         case 'Z':
12889           if (l != 0 || len != 1)
12890             {
12891               if (l != 1 || len != 2 || last[0] != 'X')
12892                 {
12893                   SAVE_LAST (*p);
12894                   break;
12895                 }
12896               if (!need_vex || !vex.evex)
12897                 abort ();
12898               if (intel_syntax
12899                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
12900                 break;
12901               switch (vex.length)
12902                 {
12903                 case 128:
12904                   *obufp++ = 'x';
12905                   break;
12906                 case 256:
12907                   *obufp++ = 'y';
12908                   break;
12909                 case 512:
12910                   *obufp++ = 'z';
12911                   break;
12912                 default:
12913                   abort ();
12914                 }
12915               break;
12916             }
12917           if (intel_syntax)
12918             break;
12919           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
12920             {
12921               *obufp++ = 'q';
12922               break;
12923             }
12924           /* Fall through.  */
12925           goto case_L;
12926         case 'L':
12927           if (l != 0 || len != 1)
12928             {
12929               SAVE_LAST (*p);
12930               break;
12931             }
12932 case_L:
12933           if (intel_syntax)
12934             break;
12935           if (sizeflag & SUFFIX_ALWAYS)
12936             *obufp++ = 'l';
12937           break;
12938         case 'M':
12939           if (intel_mnemonic != cond)
12940             *obufp++ = 'r';
12941           break;
12942         case 'N':
12943           if ((prefixes & PREFIX_FWAIT) == 0)
12944             *obufp++ = 'n';
12945           else
12946             used_prefixes |= PREFIX_FWAIT;
12947           break;
12948         case 'O':
12949           USED_REX (REX_W);
12950           if (rex & REX_W)
12951             *obufp++ = 'o';
12952           else if (intel_syntax && (sizeflag & DFLAG))
12953             *obufp++ = 'q';
12954           else
12955             *obufp++ = 'd';
12956           if (!(rex & REX_W))
12957             used_prefixes |= (prefixes & PREFIX_DATA);
12958           break;
12959         case '&':
12960           if (!intel_syntax
12961               && address_mode == mode_64bit
12962               && isa64 == intel64)
12963             {
12964               *obufp++ = 'q';
12965               break;
12966             }
12967           /* Fall through.  */
12968         case 'T':
12969           if (!intel_syntax
12970               && address_mode == mode_64bit
12971               && ((sizeflag & DFLAG) || (rex & REX_W)))
12972             {
12973               *obufp++ = 'q';
12974               break;
12975             }
12976           /* Fall through.  */
12977           goto case_P;
12978         case 'P':
12979           if (l == 0 && len == 1)
12980             {
12981 case_P:
12982               if (intel_syntax)
12983                 {
12984                   if ((rex & REX_W) == 0
12985                       && (prefixes & PREFIX_DATA))
12986                     {
12987                       if ((sizeflag & DFLAG) == 0)
12988                         *obufp++ = 'w';
12989                       used_prefixes |= (prefixes & PREFIX_DATA);
12990                     }
12991                   break;
12992                 }
12993               if ((prefixes & PREFIX_DATA)
12994                   || (rex & REX_W)
12995                   || (sizeflag & SUFFIX_ALWAYS))
12996                 {
12997                   USED_REX (REX_W);
12998                   if (rex & REX_W)
12999                     *obufp++ = 'q';
13000                   else
13001                     {
13002                       if (sizeflag & DFLAG)
13003                         *obufp++ = 'l';
13004                       else
13005                         *obufp++ = 'w';
13006                       used_prefixes |= (prefixes & PREFIX_DATA);
13007                     }
13008                 }
13009             }
13010           else
13011             {
13012               if (l != 1 || len != 2 || last[0] != 'L')
13013                 {
13014                   SAVE_LAST (*p);
13015                   break;
13016                 }
13017
13018               if ((prefixes & PREFIX_DATA)
13019                   || (rex & REX_W)
13020                   || (sizeflag & SUFFIX_ALWAYS))
13021                 {
13022                   USED_REX (REX_W);
13023                   if (rex & REX_W)
13024                     *obufp++ = 'q';
13025                   else
13026                     {
13027                       if (sizeflag & DFLAG)
13028                         *obufp++ = intel_syntax ? 'd' : 'l';
13029                       else
13030                         *obufp++ = 'w';
13031                       used_prefixes |= (prefixes & PREFIX_DATA);
13032                     }
13033                 }
13034             }
13035           break;
13036         case 'U':
13037           if (intel_syntax)
13038             break;
13039           if (address_mode == mode_64bit
13040               && ((sizeflag & DFLAG) || (rex & REX_W)))
13041             {
13042               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13043                 *obufp++ = 'q';
13044               break;
13045             }
13046           /* Fall through.  */
13047           goto case_Q;
13048         case 'Q':
13049           if (l == 0 && len == 1)
13050             {
13051 case_Q:
13052               if (intel_syntax && !alt)
13053                 break;
13054               USED_REX (REX_W);
13055               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13056                 {
13057                   if (rex & REX_W)
13058                     *obufp++ = 'q';
13059                   else
13060                     {
13061                       if (sizeflag & DFLAG)
13062                         *obufp++ = intel_syntax ? 'd' : 'l';
13063                       else
13064                         *obufp++ = 'w';
13065                       used_prefixes |= (prefixes & PREFIX_DATA);
13066                     }
13067                 }
13068             }
13069           else
13070             {
13071               if (l != 1 || len != 2 || last[0] != 'L')
13072                 {
13073                   SAVE_LAST (*p);
13074                   break;
13075                 }
13076               if (intel_syntax
13077                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
13078                 break;
13079               if ((rex & REX_W))
13080                 {
13081                   USED_REX (REX_W);
13082                   *obufp++ = 'q';
13083                 }
13084               else
13085                 *obufp++ = 'l';
13086             }
13087           break;
13088         case 'R':
13089           USED_REX (REX_W);
13090           if (rex & REX_W)
13091             *obufp++ = 'q';
13092           else if (sizeflag & DFLAG)
13093             {
13094               if (intel_syntax)
13095                   *obufp++ = 'd';
13096               else
13097                   *obufp++ = 'l';
13098             }
13099           else
13100             *obufp++ = 'w';
13101           if (intel_syntax && !p[1]
13102               && ((rex & REX_W) || (sizeflag & DFLAG)))
13103             *obufp++ = 'e';
13104           if (!(rex & REX_W))
13105             used_prefixes |= (prefixes & PREFIX_DATA);
13106           break;
13107         case 'V':
13108           if (l == 0 && len == 1)
13109             {
13110               if (intel_syntax)
13111                 break;
13112               if (address_mode == mode_64bit
13113                   && ((sizeflag & DFLAG) || (rex & REX_W)))
13114                 {
13115                   if (sizeflag & SUFFIX_ALWAYS)
13116                     *obufp++ = 'q';
13117                   break;
13118                 }
13119             }
13120           else
13121             {
13122               if (l != 1
13123                   || len != 2
13124                   || last[0] != 'L')
13125                 {
13126                   SAVE_LAST (*p);
13127                   break;
13128                 }
13129
13130               if (rex & REX_W)
13131                 {
13132                   *obufp++ = 'a';
13133                   *obufp++ = 'b';
13134                   *obufp++ = 's';
13135                 }
13136             }
13137           /* Fall through.  */
13138           goto case_S;
13139         case 'S':
13140           if (l == 0 && len == 1)
13141             {
13142 case_S:
13143               if (intel_syntax)
13144                 break;
13145               if (sizeflag & SUFFIX_ALWAYS)
13146                 {
13147                   if (rex & REX_W)
13148                     *obufp++ = 'q';
13149                   else
13150                     {
13151                       if (sizeflag & DFLAG)
13152                         *obufp++ = 'l';
13153                       else
13154                         *obufp++ = 'w';
13155                       used_prefixes |= (prefixes & PREFIX_DATA);
13156                     }
13157                 }
13158             }
13159           else
13160             {
13161               if (l != 1
13162                   || len != 2
13163                   || last[0] != 'L')
13164                 {
13165                   SAVE_LAST (*p);
13166                   break;
13167                 }
13168
13169               if (address_mode == mode_64bit
13170                   && !(prefixes & PREFIX_ADDR))
13171                 {
13172                   *obufp++ = 'a';
13173                   *obufp++ = 'b';
13174                   *obufp++ = 's';
13175                 }
13176
13177               goto case_S;
13178             }
13179           break;
13180         case 'X':
13181           if (l != 0 || len != 1)
13182             {
13183               SAVE_LAST (*p);
13184               break;
13185             }
13186           if (need_vex && vex.prefix)
13187             {
13188               if (vex.prefix == DATA_PREFIX_OPCODE)
13189                 *obufp++ = 'd';
13190               else
13191                 *obufp++ = 's';
13192             }
13193           else
13194             {
13195               if (prefixes & PREFIX_DATA)
13196                 *obufp++ = 'd';
13197               else
13198                 *obufp++ = 's';
13199               used_prefixes |= (prefixes & PREFIX_DATA);
13200             }
13201           break;
13202         case 'Y':
13203           if (l == 0 && len == 1)
13204             abort ();
13205           else
13206             {
13207               if (l != 1 || len != 2 || last[0] != 'X')
13208                 {
13209                   SAVE_LAST (*p);
13210                   break;
13211                 }
13212               if (!need_vex)
13213                 abort ();
13214               if (intel_syntax
13215                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
13216                 break;
13217               switch (vex.length)
13218                 {
13219                 case 128:
13220                   *obufp++ = 'x';
13221                   break;
13222                 case 256:
13223                   *obufp++ = 'y';
13224                   break;
13225                 case 512:
13226                   if (!vex.evex)
13227                 default:
13228                     abort ();
13229                 }
13230             }
13231           break;
13232         case 'W':
13233           if (l == 0 && len == 1)
13234             {
13235               /* operand size flag for cwtl, cbtw */
13236               USED_REX (REX_W);
13237               if (rex & REX_W)
13238                 {
13239                   if (intel_syntax)
13240                     *obufp++ = 'd';
13241                   else
13242                     *obufp++ = 'l';
13243                 }
13244               else if (sizeflag & DFLAG)
13245                 *obufp++ = 'w';
13246               else
13247                 *obufp++ = 'b';
13248               if (!(rex & REX_W))
13249                 used_prefixes |= (prefixes & PREFIX_DATA);
13250             }
13251           else
13252             {
13253               if (l != 1
13254                   || len != 2
13255                   || (last[0] != 'X'
13256                       && last[0] != 'L'))
13257                 {
13258                   SAVE_LAST (*p);
13259                   break;
13260                 }
13261               if (!need_vex)
13262                 abort ();
13263               if (last[0] == 'X')
13264                 *obufp++ = vex.w ? 'd': 's';
13265               else
13266                 *obufp++ = vex.w ? 'q': 'd';
13267             }
13268           break;
13269         case '^':
13270           if (intel_syntax)
13271             break;
13272           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
13273             {
13274               if (sizeflag & DFLAG)
13275                 *obufp++ = 'l';
13276               else
13277                 *obufp++ = 'w';
13278               used_prefixes |= (prefixes & PREFIX_DATA);
13279             }
13280           break;
13281         case '@':
13282           if (intel_syntax)
13283             break;
13284           if (address_mode == mode_64bit
13285               && (isa64 == intel64
13286                   || ((sizeflag & DFLAG) || (rex & REX_W))))
13287               *obufp++ = 'q';
13288           else if ((prefixes & PREFIX_DATA))
13289             {
13290               if (!(sizeflag & DFLAG))
13291                 *obufp++ = 'w';
13292               used_prefixes |= (prefixes & PREFIX_DATA);
13293             }
13294           break;
13295         }
13296       alt = 0;
13297     }
13298   *obufp = 0;
13299   mnemonicendp = obufp;
13300   return 0;
13301 }
13302
13303 static void
13304 oappend (const char *s)
13305 {
13306   obufp = stpcpy (obufp, s);
13307 }
13308
13309 static void
13310 append_seg (void)
13311 {
13312   /* Only print the active segment register.  */
13313   if (!active_seg_prefix)
13314     return;
13315
13316   used_prefixes |= active_seg_prefix;
13317   switch (active_seg_prefix)
13318     {
13319     case PREFIX_CS:
13320       oappend_maybe_intel ("%cs:");
13321       break;
13322     case PREFIX_DS:
13323       oappend_maybe_intel ("%ds:");
13324       break;
13325     case PREFIX_SS:
13326       oappend_maybe_intel ("%ss:");
13327       break;
13328     case PREFIX_ES:
13329       oappend_maybe_intel ("%es:");
13330       break;
13331     case PREFIX_FS:
13332       oappend_maybe_intel ("%fs:");
13333       break;
13334     case PREFIX_GS:
13335       oappend_maybe_intel ("%gs:");
13336       break;
13337     default:
13338       break;
13339     }
13340 }
13341
13342 static void
13343 OP_indirE (int bytemode, int sizeflag)
13344 {
13345   if (!intel_syntax)
13346     oappend ("*");
13347   OP_E (bytemode, sizeflag);
13348 }
13349
13350 static void
13351 print_operand_value (char *buf, int hex, bfd_vma disp)
13352 {
13353   if (address_mode == mode_64bit)
13354     {
13355       if (hex)
13356         {
13357           char tmp[30];
13358           int i;
13359           buf[0] = '0';
13360           buf[1] = 'x';
13361           sprintf_vma (tmp, disp);
13362           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
13363           strcpy (buf + 2, tmp + i);
13364         }
13365       else
13366         {
13367           bfd_signed_vma v = disp;
13368           char tmp[30];
13369           int i;
13370           if (v < 0)
13371             {
13372               *(buf++) = '-';
13373               v = -disp;
13374               /* Check for possible overflow on 0x8000000000000000.  */
13375               if (v < 0)
13376                 {
13377                   strcpy (buf, "9223372036854775808");
13378                   return;
13379                 }
13380             }
13381           if (!v)
13382             {
13383               strcpy (buf, "0");
13384               return;
13385             }
13386
13387           i = 0;
13388           tmp[29] = 0;
13389           while (v)
13390             {
13391               tmp[28 - i] = (v % 10) + '0';
13392               v /= 10;
13393               i++;
13394             }
13395           strcpy (buf, tmp + 29 - i);
13396         }
13397     }
13398   else
13399     {
13400       if (hex)
13401         sprintf (buf, "0x%x", (unsigned int) disp);
13402       else
13403         sprintf (buf, "%d", (int) disp);
13404     }
13405 }
13406
13407 /* Put DISP in BUF as signed hex number.  */
13408
13409 static void
13410 print_displacement (char *buf, bfd_vma disp)
13411 {
13412   bfd_signed_vma val = disp;
13413   char tmp[30];
13414   int i, j = 0;
13415
13416   if (val < 0)
13417     {
13418       buf[j++] = '-';
13419       val = -disp;
13420
13421       /* Check for possible overflow.  */
13422       if (val < 0)
13423         {
13424           switch (address_mode)
13425             {
13426             case mode_64bit:
13427               strcpy (buf + j, "0x8000000000000000");
13428               break;
13429             case mode_32bit:
13430               strcpy (buf + j, "0x80000000");
13431               break;
13432             case mode_16bit:
13433               strcpy (buf + j, "0x8000");
13434               break;
13435             }
13436           return;
13437         }
13438     }
13439
13440   buf[j++] = '0';
13441   buf[j++] = 'x';
13442
13443   sprintf_vma (tmp, (bfd_vma) val);
13444   for (i = 0; tmp[i] == '0'; i++)
13445     continue;
13446   if (tmp[i] == '\0')
13447     i--;
13448   strcpy (buf + j, tmp + i);
13449 }
13450
13451 static void
13452 intel_operand_size (int bytemode, int sizeflag)
13453 {
13454   if (vex.evex
13455       && vex.b
13456       && (bytemode == x_mode
13457           || bytemode == evex_half_bcst_xmmq_mode))
13458     {
13459       if (vex.w)
13460         oappend ("QWORD PTR ");
13461       else
13462         oappend ("DWORD PTR ");
13463       return;
13464     }
13465   switch (bytemode)
13466     {
13467     case b_mode:
13468     case b_swap_mode:
13469     case dqb_mode:
13470     case db_mode:
13471       oappend ("BYTE PTR ");
13472       break;
13473     case w_mode:
13474     case dw_mode:
13475     case dqw_mode:
13476       oappend ("WORD PTR ");
13477       break;
13478     case indir_v_mode:
13479       if (address_mode == mode_64bit && isa64 == intel64)
13480         {
13481           oappend ("QWORD PTR ");
13482           break;
13483         }
13484       /* Fall through.  */
13485     case stack_v_mode:
13486       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
13487         {
13488           oappend ("QWORD PTR ");
13489           break;
13490         }
13491       /* Fall through.  */
13492     case v_mode:
13493     case v_swap_mode:
13494     case dq_mode:
13495       USED_REX (REX_W);
13496       if (rex & REX_W)
13497         oappend ("QWORD PTR ");
13498       else
13499         {
13500           if ((sizeflag & DFLAG) || bytemode == dq_mode)
13501             oappend ("DWORD PTR ");
13502           else
13503             oappend ("WORD PTR ");
13504           used_prefixes |= (prefixes & PREFIX_DATA);
13505         }
13506       break;
13507     case z_mode:
13508       if ((rex & REX_W) || (sizeflag & DFLAG))
13509         *obufp++ = 'D';
13510       oappend ("WORD PTR ");
13511       if (!(rex & REX_W))
13512         used_prefixes |= (prefixes & PREFIX_DATA);
13513       break;
13514     case a_mode:
13515       if (sizeflag & DFLAG)
13516         oappend ("QWORD PTR ");
13517       else
13518         oappend ("DWORD PTR ");
13519       used_prefixes |= (prefixes & PREFIX_DATA);
13520       break;
13521     case d_mode:
13522     case d_scalar_mode:
13523     case d_scalar_swap_mode:
13524     case d_swap_mode:
13525     case dqd_mode:
13526       oappend ("DWORD PTR ");
13527       break;
13528     case q_mode:
13529     case q_scalar_mode:
13530     case q_scalar_swap_mode:
13531     case q_swap_mode:
13532       oappend ("QWORD PTR ");
13533       break;
13534     case dqa_mode:
13535     case m_mode:
13536       if (address_mode == mode_64bit)
13537         oappend ("QWORD PTR ");
13538       else
13539         oappend ("DWORD PTR ");
13540       break;
13541     case f_mode:
13542       if (sizeflag & DFLAG)
13543         oappend ("FWORD PTR ");
13544       else
13545         oappend ("DWORD PTR ");
13546       used_prefixes |= (prefixes & PREFIX_DATA);
13547       break;
13548     case t_mode:
13549       oappend ("TBYTE PTR ");
13550       break;
13551     case x_mode:
13552     case x_swap_mode:
13553     case evex_x_gscat_mode:
13554     case evex_x_nobcst_mode:
13555     case b_scalar_mode:
13556     case w_scalar_mode:
13557       if (need_vex)
13558         {
13559           switch (vex.length)
13560             {
13561             case 128:
13562               oappend ("XMMWORD PTR ");
13563               break;
13564             case 256:
13565               oappend ("YMMWORD PTR ");
13566               break;
13567             case 512:
13568               oappend ("ZMMWORD PTR ");
13569               break;
13570             default:
13571               abort ();
13572             }
13573         }
13574       else
13575         oappend ("XMMWORD PTR ");
13576       break;
13577     case xmm_mode:
13578       oappend ("XMMWORD PTR ");
13579       break;
13580     case ymm_mode:
13581       oappend ("YMMWORD PTR ");
13582       break;
13583     case xmmq_mode:
13584     case evex_half_bcst_xmmq_mode:
13585       if (!need_vex)
13586         abort ();
13587
13588       switch (vex.length)
13589         {
13590         case 128:
13591           oappend ("QWORD PTR ");
13592           break;
13593         case 256:
13594           oappend ("XMMWORD PTR ");
13595           break;
13596         case 512:
13597           oappend ("YMMWORD PTR ");
13598           break;
13599         default:
13600           abort ();
13601         }
13602       break;
13603     case xmm_mb_mode:
13604       if (!need_vex)
13605         abort ();
13606
13607       switch (vex.length)
13608         {
13609         case 128:
13610         case 256:
13611         case 512:
13612           oappend ("BYTE PTR ");
13613           break;
13614         default:
13615           abort ();
13616         }
13617       break;
13618     case xmm_mw_mode:
13619       if (!need_vex)
13620         abort ();
13621
13622       switch (vex.length)
13623         {
13624         case 128:
13625         case 256:
13626         case 512:
13627           oappend ("WORD PTR ");
13628           break;
13629         default:
13630           abort ();
13631         }
13632       break;
13633     case xmm_md_mode:
13634       if (!need_vex)
13635         abort ();
13636
13637       switch (vex.length)
13638         {
13639         case 128:
13640         case 256:
13641         case 512:
13642           oappend ("DWORD PTR ");
13643           break;
13644         default:
13645           abort ();
13646         }
13647       break;
13648     case xmm_mq_mode:
13649       if (!need_vex)
13650         abort ();
13651
13652       switch (vex.length)
13653         {
13654         case 128:
13655         case 256:
13656         case 512:
13657           oappend ("QWORD PTR ");
13658           break;
13659         default:
13660           abort ();
13661         }
13662       break;
13663     case xmmdw_mode:
13664       if (!need_vex)
13665         abort ();
13666
13667       switch (vex.length)
13668         {
13669         case 128:
13670           oappend ("WORD PTR ");
13671           break;
13672         case 256:
13673           oappend ("DWORD PTR ");
13674           break;
13675         case 512:
13676           oappend ("QWORD PTR ");
13677           break;
13678         default:
13679           abort ();
13680         }
13681       break;
13682     case xmmqd_mode:
13683       if (!need_vex)
13684         abort ();
13685
13686       switch (vex.length)
13687         {
13688         case 128:
13689           oappend ("DWORD PTR ");
13690           break;
13691         case 256:
13692           oappend ("QWORD PTR ");
13693           break;
13694         case 512:
13695           oappend ("XMMWORD PTR ");
13696           break;
13697         default:
13698           abort ();
13699         }
13700       break;
13701     case ymmq_mode:
13702       if (!need_vex)
13703         abort ();
13704
13705       switch (vex.length)
13706         {
13707         case 128:
13708           oappend ("QWORD PTR ");
13709           break;
13710         case 256:
13711           oappend ("YMMWORD PTR ");
13712           break;
13713         case 512:
13714           oappend ("ZMMWORD PTR ");
13715           break;
13716         default:
13717           abort ();
13718         }
13719       break;
13720     case ymmxmm_mode:
13721       if (!need_vex)
13722         abort ();
13723
13724       switch (vex.length)
13725         {
13726         case 128:
13727         case 256:
13728           oappend ("XMMWORD PTR ");
13729           break;
13730         default:
13731           abort ();
13732         }
13733       break;
13734     case o_mode:
13735       oappend ("OWORD PTR ");
13736       break;
13737     case xmm_mdq_mode:
13738     case vex_w_dq_mode:
13739     case vex_scalar_w_dq_mode:
13740       if (!need_vex)
13741         abort ();
13742
13743       if (vex.w)
13744         oappend ("QWORD PTR ");
13745       else
13746         oappend ("DWORD PTR ");
13747       break;
13748     case vex_vsib_d_w_dq_mode:
13749     case vex_vsib_q_w_dq_mode:
13750       if (!need_vex)
13751         abort ();
13752
13753       if (!vex.evex)
13754         {
13755           if (vex.w)
13756             oappend ("QWORD PTR ");
13757           else
13758             oappend ("DWORD PTR ");
13759         }
13760       else
13761         {
13762           switch (vex.length)
13763             {
13764             case 128:
13765               oappend ("XMMWORD PTR ");
13766               break;
13767             case 256:
13768               oappend ("YMMWORD PTR ");
13769               break;
13770             case 512:
13771               oappend ("ZMMWORD PTR ");
13772               break;
13773             default:
13774               abort ();
13775             }
13776         }
13777       break;
13778     case vex_vsib_q_w_d_mode:
13779     case vex_vsib_d_w_d_mode:
13780       if (!need_vex || !vex.evex)
13781         abort ();
13782
13783       switch (vex.length)
13784         {
13785         case 128:
13786           oappend ("QWORD PTR ");
13787           break;
13788         case 256:
13789           oappend ("XMMWORD PTR ");
13790           break;
13791         case 512:
13792           oappend ("YMMWORD PTR ");
13793           break;
13794         default:
13795           abort ();
13796         }
13797
13798       break;
13799     case mask_bd_mode:
13800       if (!need_vex || vex.length != 128)
13801         abort ();
13802       if (vex.w)
13803         oappend ("DWORD PTR ");
13804       else
13805         oappend ("BYTE PTR ");
13806       break;
13807     case mask_mode:
13808       if (!need_vex)
13809         abort ();
13810       if (vex.w)
13811         oappend ("QWORD PTR ");
13812       else
13813         oappend ("WORD PTR ");
13814       break;
13815     case v_bnd_mode:
13816     case v_bndmk_mode:
13817     default:
13818       break;
13819     }
13820 }
13821
13822 static void
13823 OP_E_register (int bytemode, int sizeflag)
13824 {
13825   int reg = modrm.rm;
13826   const char **names;
13827
13828   USED_REX (REX_B);
13829   if ((rex & REX_B))
13830     reg += 8;
13831
13832   if ((sizeflag & SUFFIX_ALWAYS)
13833       && (bytemode == b_swap_mode
13834           || bytemode == bnd_swap_mode
13835           || bytemode == v_swap_mode))
13836     swap_operand ();
13837
13838   switch (bytemode)
13839     {
13840     case b_mode:
13841     case b_swap_mode:
13842       USED_REX (0);
13843       if (rex)
13844         names = names8rex;
13845       else
13846         names = names8;
13847       break;
13848     case w_mode:
13849       names = names16;
13850       break;
13851     case d_mode:
13852     case dw_mode:
13853     case db_mode:
13854       names = names32;
13855       break;
13856     case q_mode:
13857       names = names64;
13858       break;
13859     case m_mode:
13860     case v_bnd_mode:
13861       names = address_mode == mode_64bit ? names64 : names32;
13862       break;
13863     case bnd_mode:
13864     case bnd_swap_mode:
13865       if (reg > 0x3)
13866         {
13867           oappend ("(bad)");
13868           return;
13869         }
13870       names = names_bnd;
13871       break;
13872     case indir_v_mode:
13873       if (address_mode == mode_64bit && isa64 == intel64)
13874         {
13875           names = names64;
13876           break;
13877         }
13878       /* Fall through.  */
13879     case stack_v_mode:
13880       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
13881         {
13882           names = names64;
13883           break;
13884         }
13885       bytemode = v_mode;
13886       /* Fall through.  */
13887     case v_mode:
13888     case v_swap_mode:
13889     case dq_mode:
13890     case dqb_mode:
13891     case dqd_mode:
13892     case dqw_mode:
13893     case dqa_mode:
13894       USED_REX (REX_W);
13895       if (rex & REX_W)
13896         names = names64;
13897       else
13898         {
13899           if ((sizeflag & DFLAG)
13900               || (bytemode != v_mode
13901                   && bytemode != v_swap_mode))
13902             names = names32;
13903           else
13904             names = names16;
13905           used_prefixes |= (prefixes & PREFIX_DATA);
13906         }
13907       break;
13908     case va_mode:
13909       names = (address_mode == mode_64bit
13910                ? names64 : names32);
13911       if (!(prefixes & PREFIX_ADDR))
13912         names = (address_mode == mode_16bit
13913                      ? names16 : names);
13914       else
13915         {
13916           /* Remove "addr16/addr32".  */
13917           all_prefixes[last_addr_prefix] = 0;
13918           names = (address_mode != mode_32bit
13919                        ? names32 : names16);
13920           used_prefixes |= PREFIX_ADDR;
13921         }
13922       break;
13923     case mask_bd_mode:
13924     case mask_mode:
13925       if (reg > 0x7)
13926         {
13927           oappend ("(bad)");
13928           return;
13929         }
13930       names = names_mask;
13931       break;
13932     case 0:
13933       return;
13934     default:
13935       oappend (INTERNAL_DISASSEMBLER_ERROR);
13936       return;
13937     }
13938   oappend (names[reg]);
13939 }
13940
13941 static void
13942 OP_E_memory (int bytemode, int sizeflag)
13943 {
13944   bfd_vma disp = 0;
13945   int add = (rex & REX_B) ? 8 : 0;
13946   int riprel = 0;
13947   int shift;
13948
13949   if (vex.evex)
13950     {
13951       /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0.  */
13952       if (vex.b
13953           && bytemode != x_mode
13954           && bytemode != xmmq_mode
13955           && bytemode != evex_half_bcst_xmmq_mode)
13956         {
13957           BadOp ();
13958           return;
13959         }
13960       switch (bytemode)
13961         {
13962         case dqw_mode:
13963         case dw_mode:
13964           shift = 1;
13965           break;
13966         case dqb_mode:
13967         case db_mode:
13968           shift = 0;
13969           break;
13970         case vex_vsib_d_w_dq_mode:
13971         case vex_vsib_d_w_d_mode:
13972         case vex_vsib_q_w_dq_mode:
13973         case vex_vsib_q_w_d_mode:
13974         case evex_x_gscat_mode:
13975         case xmm_mdq_mode:
13976           shift = vex.w ? 3 : 2;
13977           break;
13978         case x_mode:
13979         case evex_half_bcst_xmmq_mode:
13980         case xmmq_mode:
13981           if (vex.b)
13982             {
13983               shift = vex.w ? 3 : 2;
13984               break;
13985             }
13986           /* Fall through.  */
13987         case xmmqd_mode:
13988         case xmmdw_mode:
13989         case ymmq_mode:
13990         case evex_x_nobcst_mode:
13991         case x_swap_mode:
13992           switch (vex.length)
13993             {
13994             case 128:
13995               shift = 4;
13996               break;
13997             case 256:
13998               shift = 5;
13999               break;
14000             case 512:
14001               shift = 6;
14002               break;
14003             default:
14004               abort ();
14005             }
14006           break;
14007         case ymm_mode:
14008           shift = 5;
14009           break;
14010         case xmm_mode:
14011           shift = 4;
14012           break;
14013         case xmm_mq_mode:
14014         case q_mode:
14015         case q_scalar_mode:
14016         case q_swap_mode:
14017         case q_scalar_swap_mode:
14018           shift = 3;
14019           break;
14020         case dqd_mode:
14021         case xmm_md_mode:
14022         case d_mode:
14023         case d_scalar_mode:
14024         case d_swap_mode:
14025         case d_scalar_swap_mode:
14026           shift = 2;
14027           break;
14028         case w_scalar_mode:
14029         case xmm_mw_mode:
14030           shift = 1;
14031           break;
14032         case b_scalar_mode:
14033         case xmm_mb_mode:
14034           shift = 0;
14035           break;
14036         case dqa_mode:
14037           shift = address_mode == mode_64bit ? 3 : 2;
14038           break;
14039         default:
14040           abort ();
14041         }
14042       /* Make necessary corrections to shift for modes that need it.
14043          For these modes we currently have shift 4, 5 or 6 depending on
14044          vex.length (it corresponds to xmmword, ymmword or zmmword
14045          operand).  We might want to make it 3, 4 or 5 (e.g. for
14046          xmmq_mode).  In case of broadcast enabled the corrections
14047          aren't needed, as element size is always 32 or 64 bits.  */
14048       if (!vex.b
14049           && (bytemode == xmmq_mode
14050               || bytemode == evex_half_bcst_xmmq_mode))
14051         shift -= 1;
14052       else if (bytemode == xmmqd_mode)
14053         shift -= 2;
14054       else if (bytemode == xmmdw_mode)
14055         shift -= 3;
14056       else if (bytemode == ymmq_mode && vex.length == 128)
14057         shift -= 1;
14058     }
14059   else
14060     shift = 0;
14061
14062   USED_REX (REX_B);
14063   if (intel_syntax)
14064     intel_operand_size (bytemode, sizeflag);
14065   append_seg ();
14066
14067   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14068     {
14069       /* 32/64 bit address mode */
14070       int havedisp;
14071       int havesib;
14072       int havebase;
14073       int haveindex;
14074       int needindex;
14075       int needaddr32;
14076       int base, rbase;
14077       int vindex = 0;
14078       int scale = 0;
14079       int addr32flag = !((sizeflag & AFLAG)
14080                          || bytemode == v_bnd_mode
14081                          || bytemode == v_bndmk_mode
14082                          || bytemode == bnd_mode
14083                          || bytemode == bnd_swap_mode);
14084       const char **indexes64 = names64;
14085       const char **indexes32 = names32;
14086
14087       havesib = 0;
14088       havebase = 1;
14089       haveindex = 0;
14090       base = modrm.rm;
14091
14092       if (base == 4)
14093         {
14094           havesib = 1;
14095           vindex = sib.index;
14096           USED_REX (REX_X);
14097           if (rex & REX_X)
14098             vindex += 8;
14099           switch (bytemode)
14100             {
14101             case vex_vsib_d_w_dq_mode:
14102             case vex_vsib_d_w_d_mode:
14103             case vex_vsib_q_w_dq_mode:
14104             case vex_vsib_q_w_d_mode:
14105               if (!need_vex)
14106                 abort ();
14107               if (vex.evex)
14108                 {
14109                   if (!vex.v)
14110                     vindex += 16;
14111                 }
14112
14113               haveindex = 1;
14114               switch (vex.length)
14115                 {
14116                 case 128:
14117                   indexes64 = indexes32 = names_xmm;
14118                   break;
14119                 case 256:
14120                   if (!vex.w
14121                       || bytemode == vex_vsib_q_w_dq_mode
14122                       || bytemode == vex_vsib_q_w_d_mode)
14123                     indexes64 = indexes32 = names_ymm;
14124                   else
14125                     indexes64 = indexes32 = names_xmm;
14126                   break;
14127                 case 512:
14128                   if (!vex.w
14129                       || bytemode == vex_vsib_q_w_dq_mode
14130                       || bytemode == vex_vsib_q_w_d_mode)
14131                     indexes64 = indexes32 = names_zmm;
14132                   else
14133                     indexes64 = indexes32 = names_ymm;
14134                   break;
14135                 default:
14136                   abort ();
14137                 }
14138               break;
14139             default:
14140               haveindex = vindex != 4;
14141               break;
14142             }
14143           scale = sib.scale;
14144           base = sib.base;
14145           codep++;
14146         }
14147       rbase = base + add;
14148
14149       switch (modrm.mod)
14150         {
14151         case 0:
14152           if (base == 5)
14153             {
14154               havebase = 0;
14155               if (address_mode == mode_64bit && !havesib)
14156                 riprel = 1;
14157               disp = get32s ();
14158               if (riprel && bytemode == v_bndmk_mode)
14159                 {
14160                   oappend ("(bad)");
14161                   return;
14162                 }
14163             }
14164           break;
14165         case 1:
14166           FETCH_DATA (the_info, codep + 1);
14167           disp = *codep++;
14168           if ((disp & 0x80) != 0)
14169             disp -= 0x100;
14170           if (vex.evex && shift > 0)
14171             disp <<= shift;
14172           break;
14173         case 2:
14174           disp = get32s ();
14175           break;
14176         }
14177
14178       needindex = 0;
14179       needaddr32 = 0;
14180       if (havesib
14181           && !havebase
14182           && !haveindex
14183           && address_mode != mode_16bit)
14184         {
14185           if (address_mode == mode_64bit)
14186             {
14187               /* Display eiz instead of addr32.  */
14188               needindex = addr32flag;
14189               needaddr32 = 1;
14190             }
14191           else
14192             {
14193               /* In 32-bit mode, we need index register to tell [offset]
14194                  from [eiz*1 + offset].  */
14195               needindex = 1;
14196             }
14197         }
14198
14199       havedisp = (havebase
14200                   || needindex
14201                   || (havesib && (haveindex || scale != 0)));
14202
14203       if (!intel_syntax)
14204         if (modrm.mod != 0 || base == 5)
14205           {
14206             if (havedisp || riprel)
14207               print_displacement (scratchbuf, disp);
14208             else
14209               print_operand_value (scratchbuf, 1, disp);
14210             oappend (scratchbuf);
14211             if (riprel)
14212               {
14213                 set_op (disp, 1);
14214                 oappend (!addr32flag ? "(%rip)" : "(%eip)");
14215               }
14216           }
14217
14218       if ((havebase || haveindex || needaddr32 || riprel)
14219           && (bytemode != v_bnd_mode)
14220           && (bytemode != v_bndmk_mode)
14221           && (bytemode != bnd_mode)
14222           && (bytemode != bnd_swap_mode))
14223         used_prefixes |= PREFIX_ADDR;
14224
14225       if (havedisp || (intel_syntax && riprel))
14226         {
14227           *obufp++ = open_char;
14228           if (intel_syntax && riprel)
14229             {
14230               set_op (disp, 1);
14231               oappend (!addr32flag ? "rip" : "eip");
14232             }
14233           *obufp = '\0';
14234           if (havebase)
14235             oappend (address_mode == mode_64bit && !addr32flag
14236                      ? names64[rbase] : names32[rbase]);
14237           if (havesib)
14238             {
14239               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
14240                  print index to tell base + index from base.  */
14241               if (scale != 0
14242                   || needindex
14243                   || haveindex
14244                   || (havebase && base != ESP_REG_NUM))
14245                 {
14246                   if (!intel_syntax || havebase)
14247                     {
14248                       *obufp++ = separator_char;
14249                       *obufp = '\0';
14250                     }
14251                   if (haveindex)
14252                     oappend (address_mode == mode_64bit && !addr32flag
14253                              ? indexes64[vindex] : indexes32[vindex]);
14254                   else
14255                     oappend (address_mode == mode_64bit && !addr32flag
14256                              ? index64 : index32);
14257
14258                   *obufp++ = scale_char;
14259                   *obufp = '\0';
14260                   sprintf (scratchbuf, "%d", 1 << scale);
14261                   oappend (scratchbuf);
14262                 }
14263             }
14264           if (intel_syntax
14265               && (disp || modrm.mod != 0 || base == 5))
14266             {
14267               if (!havedisp || (bfd_signed_vma) disp >= 0)
14268                 {
14269                   *obufp++ = '+';
14270                   *obufp = '\0';
14271                 }
14272               else if (modrm.mod != 1 && disp != -disp)
14273                 {
14274                   *obufp++ = '-';
14275                   *obufp = '\0';
14276                   disp = - (bfd_signed_vma) disp;
14277                 }
14278
14279               if (havedisp)
14280                 print_displacement (scratchbuf, disp);
14281               else
14282                 print_operand_value (scratchbuf, 1, disp);
14283               oappend (scratchbuf);
14284             }
14285
14286           *obufp++ = close_char;
14287           *obufp = '\0';
14288         }
14289       else if (intel_syntax)
14290         {
14291           if (modrm.mod != 0 || base == 5)
14292             {
14293               if (!active_seg_prefix)
14294                 {
14295                   oappend (names_seg[ds_reg - es_reg]);
14296                   oappend (":");
14297                 }
14298               print_operand_value (scratchbuf, 1, disp);
14299               oappend (scratchbuf);
14300             }
14301         }
14302     }
14303   else
14304     {
14305       /* 16 bit address mode */
14306       used_prefixes |= prefixes & PREFIX_ADDR;
14307       switch (modrm.mod)
14308         {
14309         case 0:
14310           if (modrm.rm == 6)
14311             {
14312               disp = get16 ();
14313               if ((disp & 0x8000) != 0)
14314                 disp -= 0x10000;
14315             }
14316           break;
14317         case 1:
14318           FETCH_DATA (the_info, codep + 1);
14319           disp = *codep++;
14320           if ((disp & 0x80) != 0)
14321             disp -= 0x100;
14322           if (vex.evex && shift > 0)
14323             disp <<= shift;
14324           break;
14325         case 2:
14326           disp = get16 ();
14327           if ((disp & 0x8000) != 0)
14328             disp -= 0x10000;
14329           break;
14330         }
14331
14332       if (!intel_syntax)
14333         if (modrm.mod != 0 || modrm.rm == 6)
14334           {
14335             print_displacement (scratchbuf, disp);
14336             oappend (scratchbuf);
14337           }
14338
14339       if (modrm.mod != 0 || modrm.rm != 6)
14340         {
14341           *obufp++ = open_char;
14342           *obufp = '\0';
14343           oappend (index16[modrm.rm]);
14344           if (intel_syntax
14345               && (disp || modrm.mod != 0 || modrm.rm == 6))
14346             {
14347               if ((bfd_signed_vma) disp >= 0)
14348                 {
14349                   *obufp++ = '+';
14350                   *obufp = '\0';
14351                 }
14352               else if (modrm.mod != 1)
14353                 {
14354                   *obufp++ = '-';
14355                   *obufp = '\0';
14356                   disp = - (bfd_signed_vma) disp;
14357                 }
14358
14359               print_displacement (scratchbuf, disp);
14360               oappend (scratchbuf);
14361             }
14362
14363           *obufp++ = close_char;
14364           *obufp = '\0';
14365         }
14366       else if (intel_syntax)
14367         {
14368           if (!active_seg_prefix)
14369             {
14370               oappend (names_seg[ds_reg - es_reg]);
14371               oappend (":");
14372             }
14373           print_operand_value (scratchbuf, 1, disp & 0xffff);
14374           oappend (scratchbuf);
14375         }
14376     }
14377   if (vex.evex && vex.b
14378       && (bytemode == x_mode
14379           || bytemode == xmmq_mode
14380           || bytemode == evex_half_bcst_xmmq_mode))
14381     {
14382       if (vex.w
14383           || bytemode == xmmq_mode
14384           || bytemode == evex_half_bcst_xmmq_mode)
14385         {
14386           switch (vex.length)
14387             {
14388             case 128:
14389               oappend ("{1to2}");
14390               break;
14391             case 256:
14392               oappend ("{1to4}");
14393               break;
14394             case 512:
14395               oappend ("{1to8}");
14396               break;
14397             default:
14398               abort ();
14399             }
14400         }
14401       else
14402         {
14403           switch (vex.length)
14404             {
14405             case 128:
14406               oappend ("{1to4}");
14407               break;
14408             case 256:
14409               oappend ("{1to8}");
14410               break;
14411             case 512:
14412               oappend ("{1to16}");
14413               break;
14414             default:
14415               abort ();
14416             }
14417         }
14418     }
14419 }
14420
14421 static void
14422 OP_E (int bytemode, int sizeflag)
14423 {
14424   /* Skip mod/rm byte.  */
14425   MODRM_CHECK;
14426   codep++;
14427
14428   if (modrm.mod == 3)
14429     OP_E_register (bytemode, sizeflag);
14430   else
14431     OP_E_memory (bytemode, sizeflag);
14432 }
14433
14434 static void
14435 OP_G (int bytemode, int sizeflag)
14436 {
14437   int add = 0;
14438   const char **names;
14439   USED_REX (REX_R);
14440   if (rex & REX_R)
14441     add += 8;
14442   switch (bytemode)
14443     {
14444     case b_mode:
14445       USED_REX (0);
14446       if (rex)
14447         oappend (names8rex[modrm.reg + add]);
14448       else
14449         oappend (names8[modrm.reg + add]);
14450       break;
14451     case w_mode:
14452       oappend (names16[modrm.reg + add]);
14453       break;
14454     case d_mode:
14455     case db_mode:
14456     case dw_mode:
14457       oappend (names32[modrm.reg + add]);
14458       break;
14459     case q_mode:
14460       oappend (names64[modrm.reg + add]);
14461       break;
14462     case bnd_mode:
14463       if (modrm.reg > 0x3)
14464         {
14465           oappend ("(bad)");
14466           return;
14467         }
14468       oappend (names_bnd[modrm.reg]);
14469       break;
14470     case v_mode:
14471     case dq_mode:
14472     case dqb_mode:
14473     case dqd_mode:
14474     case dqw_mode:
14475       USED_REX (REX_W);
14476       if (rex & REX_W)
14477         oappend (names64[modrm.reg + add]);
14478       else
14479         {
14480           if ((sizeflag & DFLAG) || bytemode != v_mode)
14481             oappend (names32[modrm.reg + add]);
14482           else
14483             oappend (names16[modrm.reg + add]);
14484           used_prefixes |= (prefixes & PREFIX_DATA);
14485         }
14486       break;
14487     case va_mode:
14488       names = (address_mode == mode_64bit
14489                ? names64 : names32);
14490       if (!(prefixes & PREFIX_ADDR))
14491         {
14492           if (address_mode == mode_16bit)
14493             names = names16;
14494         }
14495       else
14496         {
14497           /* Remove "addr16/addr32".  */
14498           all_prefixes[last_addr_prefix] = 0;
14499           names = (address_mode != mode_32bit
14500                        ? names32 : names16);
14501           used_prefixes |= PREFIX_ADDR;
14502         }
14503       oappend (names[modrm.reg + add]);
14504       break;
14505     case m_mode:
14506       if (address_mode == mode_64bit)
14507         oappend (names64[modrm.reg + add]);
14508       else
14509         oappend (names32[modrm.reg + add]);
14510       break;
14511     case mask_bd_mode:
14512     case mask_mode:
14513       if ((modrm.reg + add) > 0x7)
14514         {
14515           oappend ("(bad)");
14516           return;
14517         }
14518       oappend (names_mask[modrm.reg + add]);
14519       break;
14520     default:
14521       oappend (INTERNAL_DISASSEMBLER_ERROR);
14522       break;
14523     }
14524 }
14525
14526 static bfd_vma
14527 get64 (void)
14528 {
14529   bfd_vma x;
14530 #ifdef BFD64
14531   unsigned int a;
14532   unsigned int b;
14533
14534   FETCH_DATA (the_info, codep + 8);
14535   a = *codep++ & 0xff;
14536   a |= (*codep++ & 0xff) << 8;
14537   a |= (*codep++ & 0xff) << 16;
14538   a |= (*codep++ & 0xffu) << 24;
14539   b = *codep++ & 0xff;
14540   b |= (*codep++ & 0xff) << 8;
14541   b |= (*codep++ & 0xff) << 16;
14542   b |= (*codep++ & 0xffu) << 24;
14543   x = a + ((bfd_vma) b << 32);
14544 #else
14545   abort ();
14546   x = 0;
14547 #endif
14548   return x;
14549 }
14550
14551 static bfd_signed_vma
14552 get32 (void)
14553 {
14554   bfd_signed_vma x = 0;
14555
14556   FETCH_DATA (the_info, codep + 4);
14557   x = *codep++ & (bfd_signed_vma) 0xff;
14558   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14559   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14560   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14561   return x;
14562 }
14563
14564 static bfd_signed_vma
14565 get32s (void)
14566 {
14567   bfd_signed_vma x = 0;
14568
14569   FETCH_DATA (the_info, codep + 4);
14570   x = *codep++ & (bfd_signed_vma) 0xff;
14571   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14572   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14573   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14574
14575   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
14576
14577   return x;
14578 }
14579
14580 static int
14581 get16 (void)
14582 {
14583   int x = 0;
14584
14585   FETCH_DATA (the_info, codep + 2);
14586   x = *codep++ & 0xff;
14587   x |= (*codep++ & 0xff) << 8;
14588   return x;
14589 }
14590
14591 static void
14592 set_op (bfd_vma op, int riprel)
14593 {
14594   op_index[op_ad] = op_ad;
14595   if (address_mode == mode_64bit)
14596     {
14597       op_address[op_ad] = op;
14598       op_riprel[op_ad] = riprel;
14599     }
14600   else
14601     {
14602       /* Mask to get a 32-bit address.  */
14603       op_address[op_ad] = op & 0xffffffff;
14604       op_riprel[op_ad] = riprel & 0xffffffff;
14605     }
14606 }
14607
14608 static void
14609 OP_REG (int code, int sizeflag)
14610 {
14611   const char *s;
14612   int add;
14613
14614   switch (code)
14615     {
14616     case es_reg: case ss_reg: case cs_reg:
14617     case ds_reg: case fs_reg: case gs_reg:
14618       oappend (names_seg[code - es_reg]);
14619       return;
14620     }
14621
14622   USED_REX (REX_B);
14623   if (rex & REX_B)
14624     add = 8;
14625   else
14626     add = 0;
14627
14628   switch (code)
14629     {
14630     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14631     case sp_reg: case bp_reg: case si_reg: case di_reg:
14632       s = names16[code - ax_reg + add];
14633       break;
14634     case al_reg: case ah_reg: case cl_reg: case ch_reg:
14635     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14636       USED_REX (0);
14637       if (rex)
14638         s = names8rex[code - al_reg + add];
14639       else
14640         s = names8[code - al_reg];
14641       break;
14642     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
14643     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
14644       if (address_mode == mode_64bit
14645           && ((sizeflag & DFLAG) || (rex & REX_W)))
14646         {
14647           s = names64[code - rAX_reg + add];
14648           break;
14649         }
14650       code += eAX_reg - rAX_reg;
14651       /* Fall through.  */
14652     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14653     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14654       USED_REX (REX_W);
14655       if (rex & REX_W)
14656         s = names64[code - eAX_reg + add];
14657       else
14658         {
14659           if (sizeflag & DFLAG)
14660             s = names32[code - eAX_reg + add];
14661           else
14662             s = names16[code - eAX_reg + add];
14663           used_prefixes |= (prefixes & PREFIX_DATA);
14664         }
14665       break;
14666     default:
14667       s = INTERNAL_DISASSEMBLER_ERROR;
14668       break;
14669     }
14670   oappend (s);
14671 }
14672
14673 static void
14674 OP_IMREG (int code, int sizeflag)
14675 {
14676   const char *s;
14677
14678   switch (code)
14679     {
14680     case indir_dx_reg:
14681       if (intel_syntax)
14682         s = "dx";
14683       else
14684         s = "(%dx)";
14685       break;
14686     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14687     case sp_reg: case bp_reg: case si_reg: case di_reg:
14688       s = names16[code - ax_reg];
14689       break;
14690     case es_reg: case ss_reg: case cs_reg:
14691     case ds_reg: case fs_reg: case gs_reg:
14692       s = names_seg[code - es_reg];
14693       break;
14694     case al_reg: case ah_reg: case cl_reg: case ch_reg:
14695     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14696       USED_REX (0);
14697       if (rex)
14698         s = names8rex[code - al_reg];
14699       else
14700         s = names8[code - al_reg];
14701       break;
14702     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14703     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14704       USED_REX (REX_W);
14705       if (rex & REX_W)
14706         s = names64[code - eAX_reg];
14707       else
14708         {
14709           if (sizeflag & DFLAG)
14710             s = names32[code - eAX_reg];
14711           else
14712             s = names16[code - eAX_reg];
14713           used_prefixes |= (prefixes & PREFIX_DATA);
14714         }
14715       break;
14716     case z_mode_ax_reg:
14717       if ((rex & REX_W) || (sizeflag & DFLAG))
14718         s = *names32;
14719       else
14720         s = *names16;
14721       if (!(rex & REX_W))
14722         used_prefixes |= (prefixes & PREFIX_DATA);
14723       break;
14724     default:
14725       s = INTERNAL_DISASSEMBLER_ERROR;
14726       break;
14727     }
14728   oappend (s);
14729 }
14730
14731 static void
14732 OP_I (int bytemode, int sizeflag)
14733 {
14734   bfd_signed_vma op;
14735   bfd_signed_vma mask = -1;
14736
14737   switch (bytemode)
14738     {
14739     case b_mode:
14740       FETCH_DATA (the_info, codep + 1);
14741       op = *codep++;
14742       mask = 0xff;
14743       break;
14744     case q_mode:
14745       if (address_mode == mode_64bit)
14746         {
14747           op = get32s ();
14748           break;
14749         }
14750       /* Fall through.  */
14751     case v_mode:
14752       USED_REX (REX_W);
14753       if (rex & REX_W)
14754         op = get32s ();
14755       else
14756         {
14757           if (sizeflag & DFLAG)
14758             {
14759               op = get32 ();
14760               mask = 0xffffffff;
14761             }
14762           else
14763             {
14764               op = get16 ();
14765               mask = 0xfffff;
14766             }
14767           used_prefixes |= (prefixes & PREFIX_DATA);
14768         }
14769       break;
14770     case w_mode:
14771       mask = 0xfffff;
14772       op = get16 ();
14773       break;
14774     case const_1_mode:
14775       if (intel_syntax)
14776         oappend ("1");
14777       return;
14778     default:
14779       oappend (INTERNAL_DISASSEMBLER_ERROR);
14780       return;
14781     }
14782
14783   op &= mask;
14784   scratchbuf[0] = '$';
14785   print_operand_value (scratchbuf + 1, 1, op);
14786   oappend_maybe_intel (scratchbuf);
14787   scratchbuf[0] = '\0';
14788 }
14789
14790 static void
14791 OP_I64 (int bytemode, int sizeflag)
14792 {
14793   bfd_signed_vma op;
14794   bfd_signed_vma mask = -1;
14795
14796   if (address_mode != mode_64bit)
14797     {
14798       OP_I (bytemode, sizeflag);
14799       return;
14800     }
14801
14802   switch (bytemode)
14803     {
14804     case b_mode:
14805       FETCH_DATA (the_info, codep + 1);
14806       op = *codep++;
14807       mask = 0xff;
14808       break;
14809     case v_mode:
14810       USED_REX (REX_W);
14811       if (rex & REX_W)
14812         op = get64 ();
14813       else
14814         {
14815           if (sizeflag & DFLAG)
14816             {
14817               op = get32 ();
14818               mask = 0xffffffff;
14819             }
14820           else
14821             {
14822               op = get16 ();
14823               mask = 0xfffff;
14824             }
14825           used_prefixes |= (prefixes & PREFIX_DATA);
14826         }
14827       break;
14828     case w_mode:
14829       mask = 0xfffff;
14830       op = get16 ();
14831       break;
14832     default:
14833       oappend (INTERNAL_DISASSEMBLER_ERROR);
14834       return;
14835     }
14836
14837   op &= mask;
14838   scratchbuf[0] = '$';
14839   print_operand_value (scratchbuf + 1, 1, op);
14840   oappend_maybe_intel (scratchbuf);
14841   scratchbuf[0] = '\0';
14842 }
14843
14844 static void
14845 OP_sI (int bytemode, int sizeflag)
14846 {
14847   bfd_signed_vma op;
14848
14849   switch (bytemode)
14850     {
14851     case b_mode:
14852     case b_T_mode:
14853       FETCH_DATA (the_info, codep + 1);
14854       op = *codep++;
14855       if ((op & 0x80) != 0)
14856         op -= 0x100;
14857       if (bytemode == b_T_mode)
14858         {
14859           if (address_mode != mode_64bit
14860               || !((sizeflag & DFLAG) || (rex & REX_W)))
14861             {
14862               /* The operand-size prefix is overridden by a REX prefix.  */
14863               if ((sizeflag & DFLAG) || (rex & REX_W))
14864                 op &= 0xffffffff;
14865               else
14866                 op &= 0xffff;
14867           }
14868         }
14869       else
14870         {
14871           if (!(rex & REX_W))
14872             {
14873               if (sizeflag & DFLAG)
14874                 op &= 0xffffffff;
14875               else
14876                 op &= 0xffff;
14877             }
14878         }
14879       break;
14880     case v_mode:
14881       /* The operand-size prefix is overridden by a REX prefix.  */
14882       if ((sizeflag & DFLAG) || (rex & REX_W))
14883         op = get32s ();
14884       else
14885         op = get16 ();
14886       break;
14887     default:
14888       oappend (INTERNAL_DISASSEMBLER_ERROR);
14889       return;
14890     }
14891
14892   scratchbuf[0] = '$';
14893   print_operand_value (scratchbuf + 1, 1, op);
14894   oappend_maybe_intel (scratchbuf);
14895 }
14896
14897 static void
14898 OP_J (int bytemode, int sizeflag)
14899 {
14900   bfd_vma disp;
14901   bfd_vma mask = -1;
14902   bfd_vma segment = 0;
14903
14904   switch (bytemode)
14905     {
14906     case b_mode:
14907       FETCH_DATA (the_info, codep + 1);
14908       disp = *codep++;
14909       if ((disp & 0x80) != 0)
14910         disp -= 0x100;
14911       break;
14912     case v_mode:
14913       if (isa64 == amd64)
14914         USED_REX (REX_W);
14915       if ((sizeflag & DFLAG)
14916           || (address_mode == mode_64bit
14917               && (isa64 != amd64 || (rex & REX_W))))
14918         disp = get32s ();
14919       else
14920         {
14921           disp = get16 ();
14922           if ((disp & 0x8000) != 0)
14923             disp -= 0x10000;
14924           /* In 16bit mode, address is wrapped around at 64k within
14925              the same segment.  Otherwise, a data16 prefix on a jump
14926              instruction means that the pc is masked to 16 bits after
14927              the displacement is added!  */
14928           mask = 0xffff;
14929           if ((prefixes & PREFIX_DATA) == 0)
14930             segment = ((start_pc + (codep - start_codep))
14931                        & ~((bfd_vma) 0xffff));
14932         }
14933       if (address_mode != mode_64bit
14934           || (isa64 == amd64 && !(rex & REX_W)))
14935         used_prefixes |= (prefixes & PREFIX_DATA);
14936       break;
14937     default:
14938       oappend (INTERNAL_DISASSEMBLER_ERROR);
14939       return;
14940     }
14941   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
14942   set_op (disp, 0);
14943   print_operand_value (scratchbuf, 1, disp);
14944   oappend (scratchbuf);
14945 }
14946
14947 static void
14948 OP_SEG (int bytemode, int sizeflag)
14949 {
14950   if (bytemode == w_mode)
14951     oappend (names_seg[modrm.reg]);
14952   else
14953     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
14954 }
14955
14956 static void
14957 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
14958 {
14959   int seg, offset;
14960
14961   if (sizeflag & DFLAG)
14962     {
14963       offset = get32 ();
14964       seg = get16 ();
14965     }
14966   else
14967     {
14968       offset = get16 ();
14969       seg = get16 ();
14970     }
14971   used_prefixes |= (prefixes & PREFIX_DATA);
14972   if (intel_syntax)
14973     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
14974   else
14975     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
14976   oappend (scratchbuf);
14977 }
14978
14979 static void
14980 OP_OFF (int bytemode, int sizeflag)
14981 {
14982   bfd_vma off;
14983
14984   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
14985     intel_operand_size (bytemode, sizeflag);
14986   append_seg ();
14987
14988   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14989     off = get32 ();
14990   else
14991     off = get16 ();
14992
14993   if (intel_syntax)
14994     {
14995       if (!active_seg_prefix)
14996         {
14997           oappend (names_seg[ds_reg - es_reg]);
14998           oappend (":");
14999         }
15000     }
15001   print_operand_value (scratchbuf, 1, off);
15002   oappend (scratchbuf);
15003 }
15004
15005 static void
15006 OP_OFF64 (int bytemode, int sizeflag)
15007 {
15008   bfd_vma off;
15009
15010   if (address_mode != mode_64bit
15011       || (prefixes & PREFIX_ADDR))
15012     {
15013       OP_OFF (bytemode, sizeflag);
15014       return;
15015     }
15016
15017   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
15018     intel_operand_size (bytemode, sizeflag);
15019   append_seg ();
15020
15021   off = get64 ();
15022
15023   if (intel_syntax)
15024     {
15025       if (!active_seg_prefix)
15026         {
15027           oappend (names_seg[ds_reg - es_reg]);
15028           oappend (":");
15029         }
15030     }
15031   print_operand_value (scratchbuf, 1, off);
15032   oappend (scratchbuf);
15033 }
15034
15035 static void
15036 ptr_reg (int code, int sizeflag)
15037 {
15038   const char *s;
15039
15040   *obufp++ = open_char;
15041   used_prefixes |= (prefixes & PREFIX_ADDR);
15042   if (address_mode == mode_64bit)
15043     {
15044       if (!(sizeflag & AFLAG))
15045         s = names32[code - eAX_reg];
15046       else
15047         s = names64[code - eAX_reg];
15048     }
15049   else if (sizeflag & AFLAG)
15050     s = names32[code - eAX_reg];
15051   else
15052     s = names16[code - eAX_reg];
15053   oappend (s);
15054   *obufp++ = close_char;
15055   *obufp = 0;
15056 }
15057
15058 static void
15059 OP_ESreg (int code, int sizeflag)
15060 {
15061   if (intel_syntax)
15062     {
15063       switch (codep[-1])
15064         {
15065         case 0x6d:      /* insw/insl */
15066           intel_operand_size (z_mode, sizeflag);
15067           break;
15068         case 0xa5:      /* movsw/movsl/movsq */
15069         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15070         case 0xab:      /* stosw/stosl */
15071         case 0xaf:      /* scasw/scasl */
15072           intel_operand_size (v_mode, sizeflag);
15073           break;
15074         default:
15075           intel_operand_size (b_mode, sizeflag);
15076         }
15077     }
15078   oappend_maybe_intel ("%es:");
15079   ptr_reg (code, sizeflag);
15080 }
15081
15082 static void
15083 OP_DSreg (int code, int sizeflag)
15084 {
15085   if (intel_syntax)
15086     {
15087       switch (codep[-1])
15088         {
15089         case 0x6f:      /* outsw/outsl */
15090           intel_operand_size (z_mode, sizeflag);
15091           break;
15092         case 0xa5:      /* movsw/movsl/movsq */
15093         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15094         case 0xad:      /* lodsw/lodsl/lodsq */
15095           intel_operand_size (v_mode, sizeflag);
15096           break;
15097         default:
15098           intel_operand_size (b_mode, sizeflag);
15099         }
15100     }
15101   /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
15102      default segment register DS is printed.  */
15103   if (!active_seg_prefix)
15104     active_seg_prefix = PREFIX_DS;
15105   append_seg ();
15106   ptr_reg (code, sizeflag);
15107 }
15108
15109 static void
15110 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15111 {
15112   int add;
15113   if (rex & REX_R)
15114     {
15115       USED_REX (REX_R);
15116       add = 8;
15117     }
15118   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
15119     {
15120       all_prefixes[last_lock_prefix] = 0;
15121       used_prefixes |= PREFIX_LOCK;
15122       add = 8;
15123     }
15124   else
15125     add = 0;
15126   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
15127   oappend_maybe_intel (scratchbuf);
15128 }
15129
15130 static void
15131 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15132 {
15133   int add;
15134   USED_REX (REX_R);
15135   if (rex & REX_R)
15136     add = 8;
15137   else
15138     add = 0;
15139   if (intel_syntax)
15140     sprintf (scratchbuf, "db%d", modrm.reg + add);
15141   else
15142     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
15143   oappend (scratchbuf);
15144 }
15145
15146 static void
15147 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15148 {
15149   sprintf (scratchbuf, "%%tr%d", modrm.reg);
15150   oappend_maybe_intel (scratchbuf);
15151 }
15152
15153 static void
15154 OP_R (int bytemode, int sizeflag)
15155 {
15156   /* Skip mod/rm byte.  */
15157   MODRM_CHECK;
15158   codep++;
15159   OP_E_register (bytemode, sizeflag);
15160 }
15161
15162 static void
15163 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15164 {
15165   int reg = modrm.reg;
15166   const char **names;
15167
15168   used_prefixes |= (prefixes & PREFIX_DATA);
15169   if (prefixes & PREFIX_DATA)
15170     {
15171       names = names_xmm;
15172       USED_REX (REX_R);
15173       if (rex & REX_R)
15174         reg += 8;
15175     }
15176   else
15177     names = names_mm;
15178   oappend (names[reg]);
15179 }
15180
15181 static void
15182 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15183 {
15184   int reg = modrm.reg;
15185   const char **names;
15186
15187   USED_REX (REX_R);
15188   if (rex & REX_R)
15189     reg += 8;
15190   if (vex.evex)
15191     {
15192       if (!vex.r)
15193         reg += 16;
15194     }
15195
15196   if (need_vex
15197       && bytemode != xmm_mode
15198       && bytemode != xmmq_mode
15199       && bytemode != evex_half_bcst_xmmq_mode
15200       && bytemode != ymm_mode
15201       && bytemode != scalar_mode)
15202     {
15203       switch (vex.length)
15204         {
15205         case 128:
15206           names = names_xmm;
15207           break;
15208         case 256:
15209           if (vex.w
15210               || (bytemode != vex_vsib_q_w_dq_mode
15211                   && bytemode != vex_vsib_q_w_d_mode))
15212             names = names_ymm;
15213           else
15214             names = names_xmm;
15215           break;
15216         case 512:
15217           names = names_zmm;
15218           break;
15219         default:
15220           abort ();
15221         }
15222     }
15223   else if (bytemode == xmmq_mode
15224            || bytemode == evex_half_bcst_xmmq_mode)
15225     {
15226       switch (vex.length)
15227         {
15228         case 128:
15229         case 256:
15230           names = names_xmm;
15231           break;
15232         case 512:
15233           names = names_ymm;
15234           break;
15235         default:
15236           abort ();
15237         }
15238     }
15239   else if (bytemode == ymm_mode)
15240     names = names_ymm;
15241   else
15242     names = names_xmm;
15243   oappend (names[reg]);
15244 }
15245
15246 static void
15247 OP_EM (int bytemode, int sizeflag)
15248 {
15249   int reg;
15250   const char **names;
15251
15252   if (modrm.mod != 3)
15253     {
15254       if (intel_syntax
15255           && (bytemode == v_mode || bytemode == v_swap_mode))
15256         {
15257           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15258           used_prefixes |= (prefixes & PREFIX_DATA);
15259         }
15260       OP_E (bytemode, sizeflag);
15261       return;
15262     }
15263
15264   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
15265     swap_operand ();
15266
15267   /* Skip mod/rm byte.  */
15268   MODRM_CHECK;
15269   codep++;
15270   used_prefixes |= (prefixes & PREFIX_DATA);
15271   reg = modrm.rm;
15272   if (prefixes & PREFIX_DATA)
15273     {
15274       names = names_xmm;
15275       USED_REX (REX_B);
15276       if (rex & REX_B)
15277         reg += 8;
15278     }
15279   else
15280     names = names_mm;
15281   oappend (names[reg]);
15282 }
15283
15284 /* cvt* are the only instructions in sse2 which have
15285    both SSE and MMX operands and also have 0x66 prefix
15286    in their opcode. 0x66 was originally used to differentiate
15287    between SSE and MMX instruction(operands). So we have to handle the
15288    cvt* separately using OP_EMC and OP_MXC */
15289 static void
15290 OP_EMC (int bytemode, int sizeflag)
15291 {
15292   if (modrm.mod != 3)
15293     {
15294       if (intel_syntax && bytemode == v_mode)
15295         {
15296           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15297           used_prefixes |= (prefixes & PREFIX_DATA);
15298         }
15299       OP_E (bytemode, sizeflag);
15300       return;
15301     }
15302
15303   /* Skip mod/rm byte.  */
15304   MODRM_CHECK;
15305   codep++;
15306   used_prefixes |= (prefixes & PREFIX_DATA);
15307   oappend (names_mm[modrm.rm]);
15308 }
15309
15310 static void
15311 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15312 {
15313   used_prefixes |= (prefixes & PREFIX_DATA);
15314   oappend (names_mm[modrm.reg]);
15315 }
15316
15317 static void
15318 OP_EX (int bytemode, int sizeflag)
15319 {
15320   int reg;
15321   const char **names;
15322
15323   /* Skip mod/rm byte.  */
15324   MODRM_CHECK;
15325   codep++;
15326
15327   if (modrm.mod != 3)
15328     {
15329       OP_E_memory (bytemode, sizeflag);
15330       return;
15331     }
15332
15333   reg = modrm.rm;
15334   USED_REX (REX_B);
15335   if (rex & REX_B)
15336     reg += 8;
15337   if (vex.evex)
15338     {
15339       USED_REX (REX_X);
15340       if ((rex & REX_X))
15341         reg += 16;
15342     }
15343
15344   if ((sizeflag & SUFFIX_ALWAYS)
15345       && (bytemode == x_swap_mode
15346           || bytemode == d_swap_mode
15347           || bytemode == d_scalar_swap_mode
15348           || bytemode == q_swap_mode
15349           || bytemode == q_scalar_swap_mode))
15350     swap_operand ();
15351
15352   if (need_vex
15353       && bytemode != xmm_mode
15354       && bytemode != xmmdw_mode
15355       && bytemode != xmmqd_mode
15356       && bytemode != xmm_mb_mode
15357       && bytemode != xmm_mw_mode
15358       && bytemode != xmm_md_mode
15359       && bytemode != xmm_mq_mode
15360       && bytemode != xmm_mdq_mode
15361       && bytemode != xmmq_mode
15362       && bytemode != evex_half_bcst_xmmq_mode
15363       && bytemode != ymm_mode
15364       && bytemode != d_scalar_mode
15365       && bytemode != d_scalar_swap_mode
15366       && bytemode != q_scalar_mode
15367       && bytemode != q_scalar_swap_mode
15368       && bytemode != vex_scalar_w_dq_mode)
15369     {
15370       switch (vex.length)
15371         {
15372         case 128:
15373           names = names_xmm;
15374           break;
15375         case 256:
15376           names = names_ymm;
15377           break;
15378         case 512:
15379           names = names_zmm;
15380           break;
15381         default:
15382           abort ();
15383         }
15384     }
15385   else if (bytemode == xmmq_mode
15386            || bytemode == evex_half_bcst_xmmq_mode)
15387     {
15388       switch (vex.length)
15389         {
15390         case 128:
15391         case 256:
15392           names = names_xmm;
15393           break;
15394         case 512:
15395           names = names_ymm;
15396           break;
15397         default:
15398           abort ();
15399         }
15400     }
15401   else if (bytemode == ymm_mode)
15402     names = names_ymm;
15403   else
15404     names = names_xmm;
15405   oappend (names[reg]);
15406 }
15407
15408 static void
15409 OP_MS (int bytemode, int sizeflag)
15410 {
15411   if (modrm.mod == 3)
15412     OP_EM (bytemode, sizeflag);
15413   else
15414     BadOp ();
15415 }
15416
15417 static void
15418 OP_XS (int bytemode, int sizeflag)
15419 {
15420   if (modrm.mod == 3)
15421     OP_EX (bytemode, sizeflag);
15422   else
15423     BadOp ();
15424 }
15425
15426 static void
15427 OP_M (int bytemode, int sizeflag)
15428 {
15429   if (modrm.mod == 3)
15430     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
15431     BadOp ();
15432   else
15433     OP_E (bytemode, sizeflag);
15434 }
15435
15436 static void
15437 OP_0f07 (int bytemode, int sizeflag)
15438 {
15439   if (modrm.mod != 3 || modrm.rm != 0)
15440     BadOp ();
15441   else
15442     OP_E (bytemode, sizeflag);
15443 }
15444
15445 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
15446    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
15447
15448 static void
15449 NOP_Fixup1 (int bytemode, int sizeflag)
15450 {
15451   if ((prefixes & PREFIX_DATA) != 0
15452       || (rex != 0
15453           && rex != 0x48
15454           && address_mode == mode_64bit))
15455     OP_REG (bytemode, sizeflag);
15456   else
15457     strcpy (obuf, "nop");
15458 }
15459
15460 static void
15461 NOP_Fixup2 (int bytemode, int sizeflag)
15462 {
15463   if ((prefixes & PREFIX_DATA) != 0
15464       || (rex != 0
15465           && rex != 0x48
15466           && address_mode == mode_64bit))
15467     OP_IMREG (bytemode, sizeflag);
15468 }
15469
15470 static const char *const Suffix3DNow[] = {
15471 /* 00 */        NULL,           NULL,           NULL,           NULL,
15472 /* 04 */        NULL,           NULL,           NULL,           NULL,
15473 /* 08 */        NULL,           NULL,           NULL,           NULL,
15474 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
15475 /* 10 */        NULL,           NULL,           NULL,           NULL,
15476 /* 14 */        NULL,           NULL,           NULL,           NULL,
15477 /* 18 */        NULL,           NULL,           NULL,           NULL,
15478 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
15479 /* 20 */        NULL,           NULL,           NULL,           NULL,
15480 /* 24 */        NULL,           NULL,           NULL,           NULL,
15481 /* 28 */        NULL,           NULL,           NULL,           NULL,
15482 /* 2C */        NULL,           NULL,           NULL,           NULL,
15483 /* 30 */        NULL,           NULL,           NULL,           NULL,
15484 /* 34 */        NULL,           NULL,           NULL,           NULL,
15485 /* 38 */        NULL,           NULL,           NULL,           NULL,
15486 /* 3C */        NULL,           NULL,           NULL,           NULL,
15487 /* 40 */        NULL,           NULL,           NULL,           NULL,
15488 /* 44 */        NULL,           NULL,           NULL,           NULL,
15489 /* 48 */        NULL,           NULL,           NULL,           NULL,
15490 /* 4C */        NULL,           NULL,           NULL,           NULL,
15491 /* 50 */        NULL,           NULL,           NULL,           NULL,
15492 /* 54 */        NULL,           NULL,           NULL,           NULL,
15493 /* 58 */        NULL,           NULL,           NULL,           NULL,
15494 /* 5C */        NULL,           NULL,           NULL,           NULL,
15495 /* 60 */        NULL,           NULL,           NULL,           NULL,
15496 /* 64 */        NULL,           NULL,           NULL,           NULL,
15497 /* 68 */        NULL,           NULL,           NULL,           NULL,
15498 /* 6C */        NULL,           NULL,           NULL,           NULL,
15499 /* 70 */        NULL,           NULL,           NULL,           NULL,
15500 /* 74 */        NULL,           NULL,           NULL,           NULL,
15501 /* 78 */        NULL,           NULL,           NULL,           NULL,
15502 /* 7C */        NULL,           NULL,           NULL,           NULL,
15503 /* 80 */        NULL,           NULL,           NULL,           NULL,
15504 /* 84 */        NULL,           NULL,           NULL,           NULL,
15505 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
15506 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
15507 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
15508 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
15509 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
15510 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
15511 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
15512 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
15513 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
15514 /* AC */        NULL,           NULL,           "pfacc",        NULL,
15515 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
15516 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
15517 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
15518 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
15519 /* C0 */        NULL,           NULL,           NULL,           NULL,
15520 /* C4 */        NULL,           NULL,           NULL,           NULL,
15521 /* C8 */        NULL,           NULL,           NULL,           NULL,
15522 /* CC */        NULL,           NULL,           NULL,           NULL,
15523 /* D0 */        NULL,           NULL,           NULL,           NULL,
15524 /* D4 */        NULL,           NULL,           NULL,           NULL,
15525 /* D8 */        NULL,           NULL,           NULL,           NULL,
15526 /* DC */        NULL,           NULL,           NULL,           NULL,
15527 /* E0 */        NULL,           NULL,           NULL,           NULL,
15528 /* E4 */        NULL,           NULL,           NULL,           NULL,
15529 /* E8 */        NULL,           NULL,           NULL,           NULL,
15530 /* EC */        NULL,           NULL,           NULL,           NULL,
15531 /* F0 */        NULL,           NULL,           NULL,           NULL,
15532 /* F4 */        NULL,           NULL,           NULL,           NULL,
15533 /* F8 */        NULL,           NULL,           NULL,           NULL,
15534 /* FC */        NULL,           NULL,           NULL,           NULL,
15535 };
15536
15537 static void
15538 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15539 {
15540   const char *mnemonic;
15541
15542   FETCH_DATA (the_info, codep + 1);
15543   /* AMD 3DNow! instructions are specified by an opcode suffix in the
15544      place where an 8-bit immediate would normally go.  ie. the last
15545      byte of the instruction.  */
15546   obufp = mnemonicendp;
15547   mnemonic = Suffix3DNow[*codep++ & 0xff];
15548   if (mnemonic)
15549     oappend (mnemonic);
15550   else
15551     {
15552       /* Since a variable sized modrm/sib chunk is between the start
15553          of the opcode (0x0f0f) and the opcode suffix, we need to do
15554          all the modrm processing first, and don't know until now that
15555          we have a bad opcode.  This necessitates some cleaning up.  */
15556       op_out[0][0] = '\0';
15557       op_out[1][0] = '\0';
15558       BadOp ();
15559     }
15560   mnemonicendp = obufp;
15561 }
15562
15563 static struct op simd_cmp_op[] =
15564 {
15565   { STRING_COMMA_LEN ("eq") },
15566   { STRING_COMMA_LEN ("lt") },
15567   { STRING_COMMA_LEN ("le") },
15568   { STRING_COMMA_LEN ("unord") },
15569   { STRING_COMMA_LEN ("neq") },
15570   { STRING_COMMA_LEN ("nlt") },
15571   { STRING_COMMA_LEN ("nle") },
15572   { STRING_COMMA_LEN ("ord") }
15573 };
15574
15575 static void
15576 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15577 {
15578   unsigned int cmp_type;
15579
15580   FETCH_DATA (the_info, codep + 1);
15581   cmp_type = *codep++ & 0xff;
15582   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
15583     {
15584       char suffix [3];
15585       char *p = mnemonicendp - 2;
15586       suffix[0] = p[0];
15587       suffix[1] = p[1];
15588       suffix[2] = '\0';
15589       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
15590       mnemonicendp += simd_cmp_op[cmp_type].len;
15591     }
15592   else
15593     {
15594       /* We have a reserved extension byte.  Output it directly.  */
15595       scratchbuf[0] = '$';
15596       print_operand_value (scratchbuf + 1, 1, cmp_type);
15597       oappend_maybe_intel (scratchbuf);
15598       scratchbuf[0] = '\0';
15599     }
15600 }
15601
15602 static void
15603 OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED,
15604           int sizeflag ATTRIBUTE_UNUSED)
15605 {
15606   /* mwaitx %eax,%ecx,%ebx */
15607   if (!intel_syntax)
15608     {
15609       const char **names = (address_mode == mode_64bit
15610                             ? names64 : names32);
15611       strcpy (op_out[0], names[0]);
15612       strcpy (op_out[1], names[1]);
15613       strcpy (op_out[2], names[3]);
15614       two_source_ops = 1;
15615     }
15616   /* Skip mod/rm byte.  */
15617   MODRM_CHECK;
15618   codep++;
15619 }
15620
15621 static void
15622 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
15623           int sizeflag ATTRIBUTE_UNUSED)
15624 {
15625   /* mwait %eax,%ecx  */
15626   if (!intel_syntax)
15627     {
15628       const char **names = (address_mode == mode_64bit
15629                             ? names64 : names32);
15630       strcpy (op_out[0], names[0]);
15631       strcpy (op_out[1], names[1]);
15632       two_source_ops = 1;
15633     }
15634   /* Skip mod/rm byte.  */
15635   MODRM_CHECK;
15636   codep++;
15637 }
15638
15639 static void
15640 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
15641             int sizeflag ATTRIBUTE_UNUSED)
15642 {
15643   /* monitor %eax,%ecx,%edx"  */
15644   if (!intel_syntax)
15645     {
15646       const char **op1_names;
15647       const char **names = (address_mode == mode_64bit
15648                             ? names64 : names32);
15649
15650       if (!(prefixes & PREFIX_ADDR))
15651         op1_names = (address_mode == mode_16bit
15652                      ? names16 : names);
15653       else
15654         {
15655           /* Remove "addr16/addr32".  */
15656           all_prefixes[last_addr_prefix] = 0;
15657           op1_names = (address_mode != mode_32bit
15658                        ? names32 : names16);
15659           used_prefixes |= PREFIX_ADDR;
15660         }
15661       strcpy (op_out[0], op1_names[0]);
15662       strcpy (op_out[1], names[1]);
15663       strcpy (op_out[2], names[2]);
15664       two_source_ops = 1;
15665     }
15666   /* Skip mod/rm byte.  */
15667   MODRM_CHECK;
15668   codep++;
15669 }
15670
15671 static void
15672 BadOp (void)
15673 {
15674   /* Throw away prefixes and 1st. opcode byte.  */
15675   codep = insn_codep + 1;
15676   oappend ("(bad)");
15677 }
15678
15679 static void
15680 REP_Fixup (int bytemode, int sizeflag)
15681 {
15682   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
15683      lods and stos.  */
15684   if (prefixes & PREFIX_REPZ)
15685     all_prefixes[last_repz_prefix] = REP_PREFIX;
15686
15687   switch (bytemode)
15688     {
15689     case al_reg:
15690     case eAX_reg:
15691     case indir_dx_reg:
15692       OP_IMREG (bytemode, sizeflag);
15693       break;
15694     case eDI_reg:
15695       OP_ESreg (bytemode, sizeflag);
15696       break;
15697     case eSI_reg:
15698       OP_DSreg (bytemode, sizeflag);
15699       break;
15700     default:
15701       abort ();
15702       break;
15703     }
15704 }
15705
15706 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
15707    "bnd".  */
15708
15709 static void
15710 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15711 {
15712   if (prefixes & PREFIX_REPNZ)
15713     all_prefixes[last_repnz_prefix] = BND_PREFIX;
15714 }
15715
15716 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
15717    "notrack".  */
15718
15719 static void
15720 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED,
15721                int sizeflag ATTRIBUTE_UNUSED)
15722 {
15723   if (active_seg_prefix == PREFIX_DS
15724       && (address_mode != mode_64bit || last_data_prefix < 0))
15725     {
15726       /* NOTRACK prefix is only valid on indirect branch instructions.
15727          NB: DATA prefix is unsupported for Intel64.  */
15728       active_seg_prefix = 0;
15729       all_prefixes[last_seg_prefix] = NOTRACK_PREFIX;
15730     }
15731 }
15732
15733 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
15734    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
15735  */
15736
15737 static void
15738 HLE_Fixup1 (int bytemode, int sizeflag)
15739 {
15740   if (modrm.mod != 3
15741       && (prefixes & PREFIX_LOCK) != 0)
15742     {
15743       if (prefixes & PREFIX_REPZ)
15744         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15745       if (prefixes & PREFIX_REPNZ)
15746         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15747     }
15748
15749   OP_E (bytemode, sizeflag);
15750 }
15751
15752 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
15753    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
15754  */
15755
15756 static void
15757 HLE_Fixup2 (int bytemode, int sizeflag)
15758 {
15759   if (modrm.mod != 3)
15760     {
15761       if (prefixes & PREFIX_REPZ)
15762         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15763       if (prefixes & PREFIX_REPNZ)
15764         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15765     }
15766
15767   OP_E (bytemode, sizeflag);
15768 }
15769
15770 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
15771    "xrelease" for memory operand.  No check for LOCK prefix.   */
15772
15773 static void
15774 HLE_Fixup3 (int bytemode, int sizeflag)
15775 {
15776   if (modrm.mod != 3
15777       && last_repz_prefix > last_repnz_prefix
15778       && (prefixes & PREFIX_REPZ) != 0)
15779     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15780
15781   OP_E (bytemode, sizeflag);
15782 }
15783
15784 static void
15785 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
15786 {
15787   USED_REX (REX_W);
15788   if (rex & REX_W)
15789     {
15790       /* Change cmpxchg8b to cmpxchg16b.  */
15791       char *p = mnemonicendp - 2;
15792       mnemonicendp = stpcpy (p, "16b");
15793       bytemode = o_mode;
15794     }
15795   else if ((prefixes & PREFIX_LOCK) != 0)
15796     {
15797       if (prefixes & PREFIX_REPZ)
15798         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15799       if (prefixes & PREFIX_REPNZ)
15800         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15801     }
15802
15803   OP_M (bytemode, sizeflag);
15804 }
15805
15806 static void
15807 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
15808 {
15809   const char **names;
15810
15811   if (need_vex)
15812     {
15813       switch (vex.length)
15814         {
15815         case 128:
15816           names = names_xmm;
15817           break;
15818         case 256:
15819           names = names_ymm;
15820           break;
15821         default:
15822           abort ();
15823         }
15824     }
15825   else
15826     names = names_xmm;
15827   oappend (names[reg]);
15828 }
15829
15830 static void
15831 CRC32_Fixup (int bytemode, int sizeflag)
15832 {
15833   /* Add proper suffix to "crc32".  */
15834   char *p = mnemonicendp;
15835
15836   switch (bytemode)
15837     {
15838     case b_mode:
15839       if (intel_syntax)
15840         goto skip;
15841
15842       *p++ = 'b';
15843       break;
15844     case v_mode:
15845       if (intel_syntax)
15846         goto skip;
15847
15848       USED_REX (REX_W);
15849       if (rex & REX_W)
15850         *p++ = 'q';
15851       else
15852         {
15853           if (sizeflag & DFLAG)
15854             *p++ = 'l';
15855           else
15856             *p++ = 'w';
15857           used_prefixes |= (prefixes & PREFIX_DATA);
15858         }
15859       break;
15860     default:
15861       oappend (INTERNAL_DISASSEMBLER_ERROR);
15862       break;
15863     }
15864   mnemonicendp = p;
15865   *p = '\0';
15866
15867 skip:
15868   if (modrm.mod == 3)
15869     {
15870       int add;
15871
15872       /* Skip mod/rm byte.  */
15873       MODRM_CHECK;
15874       codep++;
15875
15876       USED_REX (REX_B);
15877       add = (rex & REX_B) ? 8 : 0;
15878       if (bytemode == b_mode)
15879         {
15880           USED_REX (0);
15881           if (rex)
15882             oappend (names8rex[modrm.rm + add]);
15883           else
15884             oappend (names8[modrm.rm + add]);
15885         }
15886       else
15887         {
15888           USED_REX (REX_W);
15889           if (rex & REX_W)
15890             oappend (names64[modrm.rm + add]);
15891           else if ((prefixes & PREFIX_DATA))
15892             oappend (names16[modrm.rm + add]);
15893           else
15894             oappend (names32[modrm.rm + add]);
15895         }
15896     }
15897   else
15898     OP_E (bytemode, sizeflag);
15899 }
15900
15901 static void
15902 FXSAVE_Fixup (int bytemode, int sizeflag)
15903 {
15904   /* Add proper suffix to "fxsave" and "fxrstor".  */
15905   USED_REX (REX_W);
15906   if (rex & REX_W)
15907     {
15908       char *p = mnemonicendp;
15909       *p++ = '6';
15910       *p++ = '4';
15911       *p = '\0';
15912       mnemonicendp = p;
15913     }
15914   OP_M (bytemode, sizeflag);
15915 }
15916
15917 static void
15918 PCMPESTR_Fixup (int bytemode, int sizeflag)
15919 {
15920   /* Add proper suffix to "{,v}pcmpestr{i,m}".  */
15921   if (!intel_syntax)
15922     {
15923       char *p = mnemonicendp;
15924
15925       USED_REX (REX_W);
15926       if (rex & REX_W)
15927         *p++ = 'q';
15928       else if (sizeflag & SUFFIX_ALWAYS)
15929         *p++ = 'l';
15930
15931       *p = '\0';
15932       mnemonicendp = p;
15933     }
15934
15935   OP_EX (bytemode, sizeflag);
15936 }
15937
15938 /* Display the destination register operand for instructions with
15939    VEX. */
15940
15941 static void
15942 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15943 {
15944   int reg;
15945   const char **names;
15946
15947   if (!need_vex)
15948     abort ();
15949
15950   if (!need_vex_reg)
15951     return;
15952
15953   reg = vex.register_specifier;
15954   if (address_mode != mode_64bit)
15955     reg &= 7;
15956   else if (vex.evex && !vex.v)
15957     reg += 16;
15958
15959   if (bytemode == vex_scalar_mode)
15960     {
15961       oappend (names_xmm[reg]);
15962       return;
15963     }
15964
15965   switch (vex.length)
15966     {
15967     case 128:
15968       switch (bytemode)
15969         {
15970         case vex_mode:
15971         case vex128_mode:
15972         case vex_vsib_q_w_dq_mode:
15973         case vex_vsib_q_w_d_mode:
15974           names = names_xmm;
15975           break;
15976         case dq_mode:
15977           if (rex & REX_W)
15978             names = names64;
15979           else
15980             names = names32;
15981           break;
15982         case mask_bd_mode:
15983         case mask_mode:
15984           if (reg > 0x7)
15985             {
15986               oappend ("(bad)");
15987               return;
15988             }
15989           names = names_mask;
15990           break;
15991         default:
15992           abort ();
15993           return;
15994         }
15995       break;
15996     case 256:
15997       switch (bytemode)
15998         {
15999         case vex_mode:
16000         case vex256_mode:
16001           names = names_ymm;
16002           break;
16003         case vex_vsib_q_w_dq_mode:
16004         case vex_vsib_q_w_d_mode:
16005           names = vex.w ? names_ymm : names_xmm;
16006           break;
16007         case mask_bd_mode:
16008         case mask_mode:
16009           if (reg > 0x7)
16010             {
16011               oappend ("(bad)");
16012               return;
16013             }
16014           names = names_mask;
16015           break;
16016         default:
16017           /* See PR binutils/20893 for a reproducer.  */
16018           oappend ("(bad)");
16019           return;
16020         }
16021       break;
16022     case 512:
16023       names = names_zmm;
16024       break;
16025     default:
16026       abort ();
16027       break;
16028     }
16029   oappend (names[reg]);
16030 }
16031
16032 /* Get the VEX immediate byte without moving codep.  */
16033
16034 static unsigned char
16035 get_vex_imm8 (int sizeflag, int opnum)
16036 {
16037   int bytes_before_imm = 0;
16038
16039   if (modrm.mod != 3)
16040     {
16041       /* There are SIB/displacement bytes.  */
16042       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
16043         {
16044           /* 32/64 bit address mode */
16045           int base = modrm.rm;
16046
16047           /* Check SIB byte.  */
16048           if (base == 4)
16049             {
16050               FETCH_DATA (the_info, codep + 1);
16051               base = *codep & 7;
16052               /* When decoding the third source, don't increase
16053                  bytes_before_imm as this has already been incremented
16054                  by one in OP_E_memory while decoding the second
16055                  source operand.  */
16056               if (opnum == 0)
16057                 bytes_before_imm++;
16058             }
16059
16060           /* Don't increase bytes_before_imm when decoding the third source,
16061              it has already been incremented by OP_E_memory while decoding
16062              the second source operand.  */
16063           if (opnum == 0)
16064             {
16065               switch (modrm.mod)
16066                 {
16067                   case 0:
16068                     /* When modrm.rm == 5 or modrm.rm == 4 and base in
16069                        SIB == 5, there is a 4 byte displacement.  */
16070                     if (base != 5)
16071                       /* No displacement. */
16072                       break;
16073                     /* Fall through.  */
16074                   case 2:
16075                     /* 4 byte displacement.  */
16076                     bytes_before_imm += 4;
16077                     break;
16078                   case 1:
16079                     /* 1 byte displacement.  */
16080                     bytes_before_imm++;
16081                     break;
16082                 }
16083             }
16084         }
16085       else
16086         {
16087           /* 16 bit address mode */
16088           /* Don't increase bytes_before_imm when decoding the third source,
16089              it has already been incremented by OP_E_memory while decoding
16090              the second source operand.  */
16091           if (opnum == 0)
16092             {
16093               switch (modrm.mod)
16094                 {
16095                 case 0:
16096                   /* When modrm.rm == 6, there is a 2 byte displacement.  */
16097                   if (modrm.rm != 6)
16098                     /* No displacement. */
16099                     break;
16100                   /* Fall through.  */
16101                 case 2:
16102                   /* 2 byte displacement.  */
16103                   bytes_before_imm += 2;
16104                   break;
16105                 case 1:
16106                   /* 1 byte displacement: when decoding the third source,
16107                      don't increase bytes_before_imm as this has already
16108                      been incremented by one in OP_E_memory while decoding
16109                      the second source operand.  */
16110                   if (opnum == 0)
16111                     bytes_before_imm++;
16112
16113                   break;
16114                 }
16115             }
16116         }
16117     }
16118
16119   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
16120   return codep [bytes_before_imm];
16121 }
16122
16123 static void
16124 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
16125 {
16126   const char **names;
16127
16128   if (reg == -1 && modrm.mod != 3)
16129     {
16130       OP_E_memory (bytemode, sizeflag);
16131       return;
16132     }
16133   else
16134     {
16135       if (reg == -1)
16136         {
16137           reg = modrm.rm;
16138           USED_REX (REX_B);
16139           if (rex & REX_B)
16140             reg += 8;
16141         }
16142       if (address_mode != mode_64bit)
16143         reg &= 7;
16144     }
16145
16146   switch (vex.length)
16147     {
16148     case 128:
16149       names = names_xmm;
16150       break;
16151     case 256:
16152       names = names_ymm;
16153       break;
16154     default:
16155       abort ();
16156     }
16157   oappend (names[reg]);
16158 }
16159
16160 static void
16161 OP_EX_VexImmW (int bytemode, int sizeflag)
16162 {
16163   int reg = -1;
16164   static unsigned char vex_imm8;
16165
16166   if (vex_w_done == 0)
16167     {
16168       vex_w_done = 1;
16169
16170       /* Skip mod/rm byte.  */
16171       MODRM_CHECK;
16172       codep++;
16173
16174       vex_imm8 = get_vex_imm8 (sizeflag, 0);
16175
16176       if (vex.w)
16177           reg = vex_imm8 >> 4;
16178
16179       OP_EX_VexReg (bytemode, sizeflag, reg);
16180     }
16181   else if (vex_w_done == 1)
16182     {
16183       vex_w_done = 2;
16184
16185       if (!vex.w)
16186           reg = vex_imm8 >> 4;
16187
16188       OP_EX_VexReg (bytemode, sizeflag, reg);
16189     }
16190   else
16191     {
16192       /* Output the imm8 directly.  */
16193       scratchbuf[0] = '$';
16194       print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
16195       oappend_maybe_intel (scratchbuf);
16196       scratchbuf[0] = '\0';
16197       codep++;
16198     }
16199 }
16200
16201 static void
16202 OP_Vex_2src (int bytemode, int sizeflag)
16203 {
16204   if (modrm.mod == 3)
16205     {
16206       int reg = modrm.rm;
16207       USED_REX (REX_B);
16208       if (rex & REX_B)
16209         reg += 8;
16210       oappend (names_xmm[reg]);
16211     }
16212   else
16213     {
16214       if (intel_syntax
16215           && (bytemode == v_mode || bytemode == v_swap_mode))
16216         {
16217           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16218           used_prefixes |= (prefixes & PREFIX_DATA);
16219         }
16220       OP_E (bytemode, sizeflag);
16221     }
16222 }
16223
16224 static void
16225 OP_Vex_2src_1 (int bytemode, int sizeflag)
16226 {
16227   if (modrm.mod == 3)
16228     {
16229       /* Skip mod/rm byte.   */
16230       MODRM_CHECK;
16231       codep++;
16232     }
16233
16234   if (vex.w)
16235     {
16236       unsigned int reg = vex.register_specifier;
16237
16238       if (address_mode != mode_64bit)
16239         reg &= 7;
16240       oappend (names_xmm[reg]);
16241     }
16242   else
16243     OP_Vex_2src (bytemode, sizeflag);
16244 }
16245
16246 static void
16247 OP_Vex_2src_2 (int bytemode, int sizeflag)
16248 {
16249   if (vex.w)
16250     OP_Vex_2src (bytemode, sizeflag);
16251   else
16252     {
16253       unsigned int reg = vex.register_specifier;
16254
16255       if (address_mode != mode_64bit)
16256         reg &= 7;
16257       oappend (names_xmm[reg]);
16258     }
16259 }
16260
16261 static void
16262 OP_EX_VexW (int bytemode, int sizeflag)
16263 {
16264   int reg = -1;
16265
16266   if (!vex_w_done)
16267     {
16268       /* Skip mod/rm byte.  */
16269       MODRM_CHECK;
16270       codep++;
16271
16272       if (vex.w)
16273         reg = get_vex_imm8 (sizeflag, 0) >> 4;
16274     }
16275   else
16276     {
16277       if (!vex.w)
16278         reg = get_vex_imm8 (sizeflag, 1) >> 4;
16279     }
16280
16281   OP_EX_VexReg (bytemode, sizeflag, reg);
16282
16283   if (vex_w_done)
16284     codep++;
16285   vex_w_done = 1;
16286 }
16287
16288 static void
16289 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16290 {
16291   int reg;
16292   const char **names;
16293
16294   FETCH_DATA (the_info, codep + 1);
16295   reg = *codep++;
16296
16297   if (bytemode != x_mode)
16298     abort ();
16299
16300   reg >>= 4;
16301   if (address_mode != mode_64bit)
16302     reg &= 7;
16303
16304   switch (vex.length)
16305     {
16306     case 128:
16307       names = names_xmm;
16308       break;
16309     case 256:
16310       names = names_ymm;
16311       break;
16312     default:
16313       abort ();
16314     }
16315   oappend (names[reg]);
16316 }
16317
16318 static void
16319 OP_XMM_VexW (int bytemode, int sizeflag)
16320 {
16321   /* Turn off the REX.W bit since it is used for swapping operands
16322      now.  */
16323   rex &= ~REX_W;
16324   OP_XMM (bytemode, sizeflag);
16325 }
16326
16327 static void
16328 OP_EX_Vex (int bytemode, int sizeflag)
16329 {
16330   if (modrm.mod != 3)
16331     {
16332       if (vex.register_specifier != 0)
16333         BadOp ();
16334       need_vex_reg = 0;
16335     }
16336   OP_EX (bytemode, sizeflag);
16337 }
16338
16339 static void
16340 OP_XMM_Vex (int bytemode, int sizeflag)
16341 {
16342   if (modrm.mod != 3)
16343     {
16344       if (vex.register_specifier != 0)
16345         BadOp ();
16346       need_vex_reg = 0;
16347     }
16348   OP_XMM (bytemode, sizeflag);
16349 }
16350
16351 static struct op vex_cmp_op[] =
16352 {
16353   { STRING_COMMA_LEN ("eq") },
16354   { STRING_COMMA_LEN ("lt") },
16355   { STRING_COMMA_LEN ("le") },
16356   { STRING_COMMA_LEN ("unord") },
16357   { STRING_COMMA_LEN ("neq") },
16358   { STRING_COMMA_LEN ("nlt") },
16359   { STRING_COMMA_LEN ("nle") },
16360   { STRING_COMMA_LEN ("ord") },
16361   { STRING_COMMA_LEN ("eq_uq") },
16362   { STRING_COMMA_LEN ("nge") },
16363   { STRING_COMMA_LEN ("ngt") },
16364   { STRING_COMMA_LEN ("false") },
16365   { STRING_COMMA_LEN ("neq_oq") },
16366   { STRING_COMMA_LEN ("ge") },
16367   { STRING_COMMA_LEN ("gt") },
16368   { STRING_COMMA_LEN ("true") },
16369   { STRING_COMMA_LEN ("eq_os") },
16370   { STRING_COMMA_LEN ("lt_oq") },
16371   { STRING_COMMA_LEN ("le_oq") },
16372   { STRING_COMMA_LEN ("unord_s") },
16373   { STRING_COMMA_LEN ("neq_us") },
16374   { STRING_COMMA_LEN ("nlt_uq") },
16375   { STRING_COMMA_LEN ("nle_uq") },
16376   { STRING_COMMA_LEN ("ord_s") },
16377   { STRING_COMMA_LEN ("eq_us") },
16378   { STRING_COMMA_LEN ("nge_uq") },
16379   { STRING_COMMA_LEN ("ngt_uq") },
16380   { STRING_COMMA_LEN ("false_os") },
16381   { STRING_COMMA_LEN ("neq_os") },
16382   { STRING_COMMA_LEN ("ge_oq") },
16383   { STRING_COMMA_LEN ("gt_oq") },
16384   { STRING_COMMA_LEN ("true_us") },
16385 };
16386
16387 static void
16388 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16389 {
16390   unsigned int cmp_type;
16391
16392   FETCH_DATA (the_info, codep + 1);
16393   cmp_type = *codep++ & 0xff;
16394   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
16395     {
16396       char suffix [3];
16397       char *p = mnemonicendp - 2;
16398       suffix[0] = p[0];
16399       suffix[1] = p[1];
16400       suffix[2] = '\0';
16401       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
16402       mnemonicendp += vex_cmp_op[cmp_type].len;
16403     }
16404   else
16405     {
16406       /* We have a reserved extension byte.  Output it directly.  */
16407       scratchbuf[0] = '$';
16408       print_operand_value (scratchbuf + 1, 1, cmp_type);
16409       oappend_maybe_intel (scratchbuf);
16410       scratchbuf[0] = '\0';
16411     }
16412 }
16413
16414 static void
16415 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
16416              int sizeflag ATTRIBUTE_UNUSED)
16417 {
16418   unsigned int cmp_type;
16419
16420   if (!vex.evex)
16421     abort ();
16422
16423   FETCH_DATA (the_info, codep + 1);
16424   cmp_type = *codep++ & 0xff;
16425   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
16426      If it's the case, print suffix, otherwise - print the immediate.  */
16427   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
16428       && cmp_type != 3
16429       && cmp_type != 7)
16430     {
16431       char suffix [3];
16432       char *p = mnemonicendp - 2;
16433
16434       /* vpcmp* can have both one- and two-lettered suffix.  */
16435       if (p[0] == 'p')
16436         {
16437           p++;
16438           suffix[0] = p[0];
16439           suffix[1] = '\0';
16440         }
16441       else
16442         {
16443           suffix[0] = p[0];
16444           suffix[1] = p[1];
16445           suffix[2] = '\0';
16446         }
16447
16448       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16449       mnemonicendp += simd_cmp_op[cmp_type].len;
16450     }
16451   else
16452     {
16453       /* We have a reserved extension byte.  Output it directly.  */
16454       scratchbuf[0] = '$';
16455       print_operand_value (scratchbuf + 1, 1, cmp_type);
16456       oappend_maybe_intel (scratchbuf);
16457       scratchbuf[0] = '\0';
16458     }
16459 }
16460
16461 static const struct op xop_cmp_op[] =
16462 {
16463   { STRING_COMMA_LEN ("lt") },
16464   { STRING_COMMA_LEN ("le") },
16465   { STRING_COMMA_LEN ("gt") },
16466   { STRING_COMMA_LEN ("ge") },
16467   { STRING_COMMA_LEN ("eq") },
16468   { STRING_COMMA_LEN ("neq") },
16469   { STRING_COMMA_LEN ("false") },
16470   { STRING_COMMA_LEN ("true") }
16471 };
16472
16473 static void
16474 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED,
16475              int sizeflag ATTRIBUTE_UNUSED)
16476 {
16477   unsigned int cmp_type;
16478
16479   FETCH_DATA (the_info, codep + 1);
16480   cmp_type = *codep++ & 0xff;
16481   if (cmp_type < ARRAY_SIZE (xop_cmp_op))
16482     {
16483       char suffix[3];
16484       char *p = mnemonicendp - 2;
16485
16486       /* vpcom* can have both one- and two-lettered suffix.  */
16487       if (p[0] == 'm')
16488         {
16489           p++;
16490           suffix[0] = p[0];
16491           suffix[1] = '\0';
16492         }
16493       else
16494         {
16495           suffix[0] = p[0];
16496           suffix[1] = p[1];
16497           suffix[2] = '\0';
16498         }
16499
16500       sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix);
16501       mnemonicendp += xop_cmp_op[cmp_type].len;
16502     }
16503   else
16504     {
16505       /* We have a reserved extension byte.  Output it directly.  */
16506       scratchbuf[0] = '$';
16507       print_operand_value (scratchbuf + 1, 1, cmp_type);
16508       oappend_maybe_intel (scratchbuf);
16509       scratchbuf[0] = '\0';
16510     }
16511 }
16512
16513 static const struct op pclmul_op[] =
16514 {
16515   { STRING_COMMA_LEN ("lql") },
16516   { STRING_COMMA_LEN ("hql") },
16517   { STRING_COMMA_LEN ("lqh") },
16518   { STRING_COMMA_LEN ("hqh") }
16519 };
16520
16521 static void
16522 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
16523               int sizeflag ATTRIBUTE_UNUSED)
16524 {
16525   unsigned int pclmul_type;
16526
16527   FETCH_DATA (the_info, codep + 1);
16528   pclmul_type = *codep++ & 0xff;
16529   switch (pclmul_type)
16530     {
16531     case 0x10:
16532       pclmul_type = 2;
16533       break;
16534     case 0x11:
16535       pclmul_type = 3;
16536       break;
16537     default:
16538       break;
16539     }
16540   if (pclmul_type < ARRAY_SIZE (pclmul_op))
16541     {
16542       char suffix [4];
16543       char *p = mnemonicendp - 3;
16544       suffix[0] = p[0];
16545       suffix[1] = p[1];
16546       suffix[2] = p[2];
16547       suffix[3] = '\0';
16548       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
16549       mnemonicendp += pclmul_op[pclmul_type].len;
16550     }
16551   else
16552     {
16553       /* We have a reserved extension byte.  Output it directly.  */
16554       scratchbuf[0] = '$';
16555       print_operand_value (scratchbuf + 1, 1, pclmul_type);
16556       oappend_maybe_intel (scratchbuf);
16557       scratchbuf[0] = '\0';
16558     }
16559 }
16560
16561 static void
16562 MOVBE_Fixup (int bytemode, int sizeflag)
16563 {
16564   /* Add proper suffix to "movbe".  */
16565   char *p = mnemonicendp;
16566
16567   switch (bytemode)
16568     {
16569     case v_mode:
16570       if (intel_syntax)
16571         goto skip;
16572
16573       USED_REX (REX_W);
16574       if (sizeflag & SUFFIX_ALWAYS)
16575         {
16576           if (rex & REX_W)
16577             *p++ = 'q';
16578           else
16579             {
16580               if (sizeflag & DFLAG)
16581                 *p++ = 'l';
16582               else
16583                 *p++ = 'w';
16584               used_prefixes |= (prefixes & PREFIX_DATA);
16585             }
16586         }
16587       break;
16588     default:
16589       oappend (INTERNAL_DISASSEMBLER_ERROR);
16590       break;
16591     }
16592   mnemonicendp = p;
16593   *p = '\0';
16594
16595 skip:
16596   OP_M (bytemode, sizeflag);
16597 }
16598
16599 static void
16600 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16601 {
16602   int reg;
16603   const char **names;
16604
16605   /* Skip mod/rm byte.  */
16606   MODRM_CHECK;
16607   codep++;
16608
16609   if (rex & REX_W)
16610     names = names64;
16611   else
16612     names = names32;
16613
16614   reg = modrm.rm;
16615   USED_REX (REX_B);
16616   if (rex & REX_B)
16617     reg += 8;
16618
16619   oappend (names[reg]);
16620 }
16621
16622 static void
16623 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16624 {
16625   const char **names;
16626   unsigned int reg = vex.register_specifier;
16627
16628   if (rex & REX_W)
16629     names = names64;
16630   else
16631     names = names32;
16632
16633   if (address_mode != mode_64bit)
16634     reg &= 7;
16635   oappend (names[reg]);
16636 }
16637
16638 static void
16639 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16640 {
16641   if (!vex.evex
16642       || (bytemode != mask_mode && bytemode != mask_bd_mode))
16643     abort ();
16644
16645   USED_REX (REX_R);
16646   if ((rex & REX_R) != 0 || !vex.r)
16647     {
16648       BadOp ();
16649       return;
16650     }
16651
16652   oappend (names_mask [modrm.reg]);
16653 }
16654
16655 static void
16656 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16657 {
16658   if (!vex.evex
16659       || (bytemode != evex_rounding_mode
16660           && bytemode != evex_rounding_64_mode
16661           && bytemode != evex_sae_mode))
16662     abort ();
16663   if (modrm.mod == 3 && vex.b)
16664     switch (bytemode)
16665       {
16666       case evex_rounding_64_mode:
16667         if (address_mode != mode_64bit)
16668           {
16669             oappend ("(bad)");
16670             break;
16671           }
16672         /* Fall through.  */
16673       case evex_rounding_mode:
16674         oappend (names_rounding[vex.ll]);
16675         break;
16676       case evex_sae_mode:
16677         oappend ("{sae}");
16678         break;
16679       default:
16680         break;
16681       }
16682 }