1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright (C) 1988-2020 Free Software Foundation, Inc.
4 This file is part of the GNU opcodes library.
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
24 modified by John Hassey (hassey@dg-rtp.dg.com)
25 x86-64 support added by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
28 /* The main tables describing the instructions is essentially a copy
29 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
30 Programmers Manual. Usually, there is a capital letter, followed
31 by a small letter. The capital letter tell the addressing mode,
32 and the small letter tells about the operand size. Refer to
33 the Intel manual for details. */
36 #include "disassemble.h"
38 #include "opcode/i386.h"
39 #include "libiberty.h"
43 static int print_insn (bfd_vma
, disassemble_info
*);
44 static void dofloat (int);
45 static void OP_ST (int, int);
46 static void OP_STi (int, int);
47 static int putop (const char *, int);
48 static void oappend (const char *);
49 static void append_seg (void);
50 static void OP_indirE (int, int);
51 static void print_operand_value (char *, int, bfd_vma
);
52 static void OP_E_register (int, int);
53 static void OP_E_memory (int, int);
54 static void print_displacement (char *, bfd_vma
);
55 static void OP_E (int, int);
56 static void OP_G (int, int);
57 static bfd_vma
get64 (void);
58 static bfd_signed_vma
get32 (void);
59 static bfd_signed_vma
get32s (void);
60 static int get16 (void);
61 static void set_op (bfd_vma
, int);
62 static void OP_Skip_MODRM (int, int);
63 static void OP_REG (int, int);
64 static void OP_IMREG (int, int);
65 static void OP_I (int, int);
66 static void OP_I64 (int, int);
67 static void OP_sI (int, int);
68 static void OP_J (int, int);
69 static void OP_SEG (int, int);
70 static void OP_DIR (int, int);
71 static void OP_OFF (int, int);
72 static void OP_OFF64 (int, int);
73 static void ptr_reg (int, int);
74 static void OP_ESreg (int, int);
75 static void OP_DSreg (int, int);
76 static void OP_C (int, int);
77 static void OP_D (int, int);
78 static void OP_T (int, int);
79 static void OP_R (int, int);
80 static void OP_MMX (int, int);
81 static void OP_XMM (int, int);
82 static void OP_EM (int, int);
83 static void OP_EX (int, int);
84 static void OP_EMC (int,int);
85 static void OP_MXC (int,int);
86 static void OP_MS (int, int);
87 static void OP_XS (int, int);
88 static void OP_M (int, int);
89 static void OP_VEX (int, int);
90 static void OP_EX_Vex (int, int);
91 static void OP_EX_VexW (int, int);
92 static void OP_EX_VexImmW (int, int);
93 static void OP_XMM_Vex (int, int);
94 static void OP_XMM_VexW (int, int);
95 static void OP_Rounding (int, int);
96 static void OP_REG_VexI4 (int, int);
97 static void PCLMUL_Fixup (int, int);
98 static void VCMP_Fixup (int, int);
99 static void VPCMP_Fixup (int, int);
100 static void VPCOM_Fixup (int, int);
101 static void OP_0f07 (int, int);
102 static void OP_Monitor (int, int);
103 static void OP_Mwait (int, int);
104 static void NOP_Fixup1 (int, int);
105 static void NOP_Fixup2 (int, int);
106 static void OP_3DNowSuffix (int, int);
107 static void CMP_Fixup (int, int);
108 static void BadOp (void);
109 static void REP_Fixup (int, int);
110 static void SEP_Fixup (int, int);
111 static void BND_Fixup (int, int);
112 static void NOTRACK_Fixup (int, int);
113 static void HLE_Fixup1 (int, int);
114 static void HLE_Fixup2 (int, int);
115 static void HLE_Fixup3 (int, int);
116 static void CMPXCHG8B_Fixup (int, int);
117 static void XMM_Fixup (int, int);
118 static void CRC32_Fixup (int, int);
119 static void FXSAVE_Fixup (int, int);
120 static void PCMPESTR_Fixup (int, int);
121 static void OP_LWPCB_E (int, int);
122 static void OP_LWP_E (int, int);
123 static void OP_Vex_2src_1 (int, int);
124 static void OP_Vex_2src_2 (int, int);
126 static void MOVBE_Fixup (int, int);
128 static void OP_Mask (int, int);
131 /* Points to first byte not fetched. */
132 bfd_byte
*max_fetched
;
133 bfd_byte the_buffer
[MAX_MNEM_SIZE
];
136 OPCODES_SIGJMP_BUF bailout
;
146 enum address_mode address_mode
;
148 /* Flags for the prefixes for the current instruction. See below. */
151 /* REX prefix the current instruction. See below. */
153 /* Bits of REX we've already used. */
155 /* REX bits in original REX prefix ignored. */
156 static int rex_ignored
;
157 /* Mark parts used in the REX prefix. When we are testing for
158 empty prefix (for 8bit register REX extension), just mask it
159 out. Otherwise test for REX bit is excuse for existence of REX
160 only in case value is nonzero. */
161 #define USED_REX(value) \
166 rex_used |= (value) | REX_OPCODE; \
169 rex_used |= REX_OPCODE; \
172 /* Flags for prefixes which we somehow handled when printing the
173 current instruction. */
174 static int used_prefixes
;
176 /* Flags stored in PREFIXES. */
177 #define PREFIX_REPZ 1
178 #define PREFIX_REPNZ 2
179 #define PREFIX_LOCK 4
181 #define PREFIX_SS 0x10
182 #define PREFIX_DS 0x20
183 #define PREFIX_ES 0x40
184 #define PREFIX_FS 0x80
185 #define PREFIX_GS 0x100
186 #define PREFIX_DATA 0x200
187 #define PREFIX_ADDR 0x400
188 #define PREFIX_FWAIT 0x800
190 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
191 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
193 #define FETCH_DATA(info, addr) \
194 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
195 ? 1 : fetch_data ((info), (addr)))
198 fetch_data (struct disassemble_info
*info
, bfd_byte
*addr
)
201 struct dis_private
*priv
= (struct dis_private
*) info
->private_data
;
202 bfd_vma start
= priv
->insn_start
+ (priv
->max_fetched
- priv
->the_buffer
);
204 if (addr
<= priv
->the_buffer
+ MAX_MNEM_SIZE
)
205 status
= (*info
->read_memory_func
) (start
,
207 addr
- priv
->max_fetched
,
213 /* If we did manage to read at least one byte, then
214 print_insn_i386 will do something sensible. Otherwise, print
215 an error. We do that here because this is where we know
217 if (priv
->max_fetched
== priv
->the_buffer
)
218 (*info
->memory_error_func
) (status
, start
, info
);
219 OPCODES_SIGLONGJMP (priv
->bailout
, 1);
222 priv
->max_fetched
= addr
;
226 /* Possible values for prefix requirement. */
227 #define PREFIX_IGNORED_SHIFT 16
228 #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
229 #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
230 #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
231 #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
232 #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
234 /* Opcode prefixes. */
235 #define PREFIX_OPCODE (PREFIX_REPZ \
239 /* Prefixes ignored. */
240 #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \
241 | PREFIX_IGNORED_REPNZ \
242 | PREFIX_IGNORED_DATA)
244 #define XX { NULL, 0 }
245 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
247 #define Eb { OP_E, b_mode }
248 #define Ebnd { OP_E, bnd_mode }
249 #define EbS { OP_E, b_swap_mode }
250 #define EbndS { OP_E, bnd_swap_mode }
251 #define Ev { OP_E, v_mode }
252 #define Eva { OP_E, va_mode }
253 #define Ev_bnd { OP_E, v_bnd_mode }
254 #define EvS { OP_E, v_swap_mode }
255 #define Ed { OP_E, d_mode }
256 #define Edq { OP_E, dq_mode }
257 #define Edqw { OP_E, dqw_mode }
258 #define Edqb { OP_E, dqb_mode }
259 #define Edb { OP_E, db_mode }
260 #define Edw { OP_E, dw_mode }
261 #define Edqd { OP_E, dqd_mode }
262 #define Eq { OP_E, q_mode }
263 #define indirEv { OP_indirE, indir_v_mode }
264 #define indirEp { OP_indirE, f_mode }
265 #define stackEv { OP_E, stack_v_mode }
266 #define Em { OP_E, m_mode }
267 #define Ew { OP_E, w_mode }
268 #define M { OP_M, 0 } /* lea, lgdt, etc. */
269 #define Ma { OP_M, a_mode }
270 #define Mb { OP_M, b_mode }
271 #define Md { OP_M, d_mode }
272 #define Mo { OP_M, o_mode }
273 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
274 #define Mq { OP_M, q_mode }
275 #define Mv_bnd { OP_M, v_bndmk_mode }
276 #define Mx { OP_M, x_mode }
277 #define Mxmm { OP_M, xmm_mode }
278 #define Gb { OP_G, b_mode }
279 #define Gbnd { OP_G, bnd_mode }
280 #define Gv { OP_G, v_mode }
281 #define Gd { OP_G, d_mode }
282 #define Gdq { OP_G, dq_mode }
283 #define Gm { OP_G, m_mode }
284 #define Gva { OP_G, va_mode }
285 #define Gw { OP_G, w_mode }
286 #define Rd { OP_R, d_mode }
287 #define Rdq { OP_R, dq_mode }
288 #define Rm { OP_R, m_mode }
289 #define Ib { OP_I, b_mode }
290 #define sIb { OP_sI, b_mode } /* sign extened byte */
291 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
292 #define Iv { OP_I, v_mode }
293 #define sIv { OP_sI, v_mode }
294 #define Iv64 { OP_I64, v_mode }
295 #define Id { OP_I, d_mode }
296 #define Iw { OP_I, w_mode }
297 #define I1 { OP_I, const_1_mode }
298 #define Jb { OP_J, b_mode }
299 #define Jv { OP_J, v_mode }
300 #define Jdqw { OP_J, dqw_mode }
301 #define Cm { OP_C, m_mode }
302 #define Dm { OP_D, m_mode }
303 #define Td { OP_T, d_mode }
304 #define Skip_MODRM { OP_Skip_MODRM, 0 }
306 #define RMeAX { OP_REG, eAX_reg }
307 #define RMeBX { OP_REG, eBX_reg }
308 #define RMeCX { OP_REG, eCX_reg }
309 #define RMeDX { OP_REG, eDX_reg }
310 #define RMeSP { OP_REG, eSP_reg }
311 #define RMeBP { OP_REG, eBP_reg }
312 #define RMeSI { OP_REG, eSI_reg }
313 #define RMeDI { OP_REG, eDI_reg }
314 #define RMrAX { OP_REG, rAX_reg }
315 #define RMrBX { OP_REG, rBX_reg }
316 #define RMrCX { OP_REG, rCX_reg }
317 #define RMrDX { OP_REG, rDX_reg }
318 #define RMrSP { OP_REG, rSP_reg }
319 #define RMrBP { OP_REG, rBP_reg }
320 #define RMrSI { OP_REG, rSI_reg }
321 #define RMrDI { OP_REG, rDI_reg }
322 #define RMAL { OP_REG, al_reg }
323 #define RMCL { OP_REG, cl_reg }
324 #define RMDL { OP_REG, dl_reg }
325 #define RMBL { OP_REG, bl_reg }
326 #define RMAH { OP_REG, ah_reg }
327 #define RMCH { OP_REG, ch_reg }
328 #define RMDH { OP_REG, dh_reg }
329 #define RMBH { OP_REG, bh_reg }
330 #define RMAX { OP_REG, ax_reg }
331 #define RMDX { OP_REG, dx_reg }
333 #define eAX { OP_IMREG, eAX_reg }
334 #define eBX { OP_IMREG, eBX_reg }
335 #define eCX { OP_IMREG, eCX_reg }
336 #define eDX { OP_IMREG, eDX_reg }
337 #define eSP { OP_IMREG, eSP_reg }
338 #define eBP { OP_IMREG, eBP_reg }
339 #define eSI { OP_IMREG, eSI_reg }
340 #define eDI { OP_IMREG, eDI_reg }
341 #define AL { OP_IMREG, al_reg }
342 #define CL { OP_IMREG, cl_reg }
343 #define DL { OP_IMREG, dl_reg }
344 #define BL { OP_IMREG, bl_reg }
345 #define AH { OP_IMREG, ah_reg }
346 #define CH { OP_IMREG, ch_reg }
347 #define DH { OP_IMREG, dh_reg }
348 #define BH { OP_IMREG, bh_reg }
349 #define AX { OP_IMREG, ax_reg }
350 #define DX { OP_IMREG, dx_reg }
351 #define zAX { OP_IMREG, z_mode_ax_reg }
352 #define indirDX { OP_IMREG, indir_dx_reg }
354 #define Sw { OP_SEG, w_mode }
355 #define Sv { OP_SEG, v_mode }
356 #define Ap { OP_DIR, 0 }
357 #define Ob { OP_OFF64, b_mode }
358 #define Ov { OP_OFF64, v_mode }
359 #define Xb { OP_DSreg, eSI_reg }
360 #define Xv { OP_DSreg, eSI_reg }
361 #define Xz { OP_DSreg, eSI_reg }
362 #define Yb { OP_ESreg, eDI_reg }
363 #define Yv { OP_ESreg, eDI_reg }
364 #define DSBX { OP_DSreg, eBX_reg }
366 #define es { OP_REG, es_reg }
367 #define ss { OP_REG, ss_reg }
368 #define cs { OP_REG, cs_reg }
369 #define ds { OP_REG, ds_reg }
370 #define fs { OP_REG, fs_reg }
371 #define gs { OP_REG, gs_reg }
373 #define MX { OP_MMX, 0 }
374 #define XM { OP_XMM, 0 }
375 #define XMScalar { OP_XMM, scalar_mode }
376 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
377 #define XMM { OP_XMM, xmm_mode }
378 #define XMxmmq { OP_XMM, xmmq_mode }
379 #define EM { OP_EM, v_mode }
380 #define EMS { OP_EM, v_swap_mode }
381 #define EMd { OP_EM, d_mode }
382 #define EMx { OP_EM, x_mode }
383 #define EXbScalar { OP_EX, b_scalar_mode }
384 #define EXw { OP_EX, w_mode }
385 #define EXwScalar { OP_EX, w_scalar_mode }
386 #define EXd { OP_EX, d_mode }
387 #define EXdScalar { OP_EX, d_scalar_mode }
388 #define EXdS { OP_EX, d_swap_mode }
389 #define EXq { OP_EX, q_mode }
390 #define EXqScalar { OP_EX, q_scalar_mode }
391 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
392 #define EXqS { OP_EX, q_swap_mode }
393 #define EXx { OP_EX, x_mode }
394 #define EXxS { OP_EX, x_swap_mode }
395 #define EXxmm { OP_EX, xmm_mode }
396 #define EXymm { OP_EX, ymm_mode }
397 #define EXxmmq { OP_EX, xmmq_mode }
398 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
399 #define EXxmm_mb { OP_EX, xmm_mb_mode }
400 #define EXxmm_mw { OP_EX, xmm_mw_mode }
401 #define EXxmm_md { OP_EX, xmm_md_mode }
402 #define EXxmm_mq { OP_EX, xmm_mq_mode }
403 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
404 #define EXxmmdw { OP_EX, xmmdw_mode }
405 #define EXxmmqd { OP_EX, xmmqd_mode }
406 #define EXymmq { OP_EX, ymmq_mode }
407 #define EXVexWdq { OP_EX, vex_w_dq_mode }
408 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
409 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
410 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
411 #define MS { OP_MS, v_mode }
412 #define XS { OP_XS, v_mode }
413 #define EMCq { OP_EMC, q_mode }
414 #define MXC { OP_MXC, 0 }
415 #define OPSUF { OP_3DNowSuffix, 0 }
416 #define SEP { SEP_Fixup, 0 }
417 #define CMP { CMP_Fixup, 0 }
418 #define XMM0 { XMM_Fixup, 0 }
419 #define FXSAVE { FXSAVE_Fixup, 0 }
420 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
421 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
423 #define Vex { OP_VEX, vex_mode }
424 #define VexScalar { OP_VEX, vex_scalar_mode }
425 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
426 #define Vex128 { OP_VEX, vex128_mode }
427 #define Vex256 { OP_VEX, vex256_mode }
428 #define VexGdq { OP_VEX, dq_mode }
429 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
430 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
431 #define EXVexW { OP_EX_VexW, x_mode }
432 #define EXdVexW { OP_EX_VexW, d_mode }
433 #define EXqVexW { OP_EX_VexW, q_mode }
434 #define EXVexImmW { OP_EX_VexImmW, x_mode }
435 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
436 #define XMVexW { OP_XMM_VexW, 0 }
437 #define XMVexI4 { OP_REG_VexI4, x_mode }
438 #define PCLMUL { PCLMUL_Fixup, 0 }
439 #define VCMP { VCMP_Fixup, 0 }
440 #define VPCMP { VPCMP_Fixup, 0 }
441 #define VPCOM { VPCOM_Fixup, 0 }
443 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
444 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
445 #define EXxEVexS { OP_Rounding, evex_sae_mode }
447 #define XMask { OP_Mask, mask_mode }
448 #define MaskG { OP_G, mask_mode }
449 #define MaskE { OP_E, mask_mode }
450 #define MaskBDE { OP_E, mask_bd_mode }
451 #define MaskR { OP_R, mask_mode }
452 #define MaskVex { OP_VEX, mask_mode }
454 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
455 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
456 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
457 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
459 /* Used handle "rep" prefix for string instructions. */
460 #define Xbr { REP_Fixup, eSI_reg }
461 #define Xvr { REP_Fixup, eSI_reg }
462 #define Ybr { REP_Fixup, eDI_reg }
463 #define Yvr { REP_Fixup, eDI_reg }
464 #define Yzr { REP_Fixup, eDI_reg }
465 #define indirDXr { REP_Fixup, indir_dx_reg }
466 #define ALr { REP_Fixup, al_reg }
467 #define eAXr { REP_Fixup, eAX_reg }
469 /* Used handle HLE prefix for lockable instructions. */
470 #define Ebh1 { HLE_Fixup1, b_mode }
471 #define Evh1 { HLE_Fixup1, v_mode }
472 #define Ebh2 { HLE_Fixup2, b_mode }
473 #define Evh2 { HLE_Fixup2, v_mode }
474 #define Ebh3 { HLE_Fixup3, b_mode }
475 #define Evh3 { HLE_Fixup3, v_mode }
477 #define BND { BND_Fixup, 0 }
478 #define NOTRACK { NOTRACK_Fixup, 0 }
480 #define cond_jump_flag { NULL, cond_jump_mode }
481 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
483 /* bits in sizeflag */
484 #define SUFFIX_ALWAYS 4
492 /* byte operand with operand swapped */
494 /* byte operand, sign extend like 'T' suffix */
496 /* operand size depends on prefixes */
498 /* operand size depends on prefixes with operand swapped */
500 /* operand size depends on address prefix */
504 /* double word operand */
506 /* double word operand with operand swapped */
508 /* quad word operand */
510 /* quad word operand with operand swapped */
512 /* ten-byte operand */
514 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
515 broadcast enabled. */
517 /* Similar to x_mode, but with different EVEX mem shifts. */
519 /* Similar to x_mode, but with disabled broadcast. */
521 /* Similar to x_mode, but with operands swapped and disabled broadcast
524 /* 16-byte XMM operand */
526 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
527 memory operand (depending on vector length). Broadcast isn't
530 /* Same as xmmq_mode, but broadcast is allowed. */
531 evex_half_bcst_xmmq_mode
,
532 /* XMM register or byte memory operand */
534 /* XMM register or word memory operand */
536 /* XMM register or double word memory operand */
538 /* XMM register or quad word memory operand */
540 /* XMM register or double/quad word memory operand, depending on
543 /* 16-byte XMM, word, double word or quad word operand. */
545 /* 16-byte XMM, double word, quad word operand or xmm word operand. */
547 /* 32-byte YMM operand */
549 /* quad word, ymmword or zmmword memory operand. */
551 /* 32-byte YMM or 16-byte word operand */
553 /* d_mode in 32bit, q_mode in 64bit mode. */
555 /* pair of v_mode operands */
560 /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode. */
562 /* operand size depends on REX prefixes. */
564 /* registers like dq_mode, memory like w_mode, displacements like
565 v_mode without considering Intel64 ISA. */
569 /* bounds operand with operand swapped */
571 /* 4- or 6-byte pointer operand */
574 /* v_mode for indirect branch opcodes. */
576 /* v_mode for stack-related opcodes. */
578 /* non-quad operand size depends on prefixes */
580 /* 16-byte operand */
582 /* registers like dq_mode, memory like b_mode. */
584 /* registers like d_mode, memory like b_mode. */
586 /* registers like d_mode, memory like w_mode. */
588 /* registers like dq_mode, memory like d_mode. */
590 /* normal vex mode */
592 /* 128bit vex mode */
594 /* 256bit vex mode */
596 /* operand size depends on the VEX.W bit. */
599 /* Similar to vex_w_dq_mode, with VSIB dword indices. */
600 vex_vsib_d_w_dq_mode
,
601 /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */
603 /* Similar to vex_w_dq_mode, with VSIB qword indices. */
604 vex_vsib_q_w_dq_mode
,
605 /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */
608 /* scalar, ignore vector length. */
610 /* like b_mode, ignore vector length. */
612 /* like w_mode, ignore vector length. */
614 /* like d_mode, ignore vector length. */
616 /* like d_swap_mode, ignore vector length. */
618 /* like q_mode, ignore vector length. */
620 /* like q_swap_mode, ignore vector length. */
622 /* like vex_mode, ignore vector length. */
624 /* like vex_w_dq_mode, ignore vector length. */
625 vex_scalar_w_dq_mode
,
627 /* Static rounding. */
629 /* Static rounding, 64-bit mode only. */
630 evex_rounding_64_mode
,
631 /* Supress all exceptions. */
634 /* Mask register operand. */
636 /* Mask register operand. */
704 #define FLOAT NULL, { { NULL, FLOATCODE } }, 0
706 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0
707 #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P
708 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
709 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
710 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
711 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
712 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
713 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
714 #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
715 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
716 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
717 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
718 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
719 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
720 #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I))
721 #define EVEX_LEN_TABLE(I) DIS386 (USE_EVEX_LEN_TABLE, (I))
849 MOD_VEX_0F12_PREFIX_0
,
851 MOD_VEX_0F16_PREFIX_0
,
854 MOD_VEX_W_0_0F41_P_0_LEN_1
,
855 MOD_VEX_W_1_0F41_P_0_LEN_1
,
856 MOD_VEX_W_0_0F41_P_2_LEN_1
,
857 MOD_VEX_W_1_0F41_P_2_LEN_1
,
858 MOD_VEX_W_0_0F42_P_0_LEN_1
,
859 MOD_VEX_W_1_0F42_P_0_LEN_1
,
860 MOD_VEX_W_0_0F42_P_2_LEN_1
,
861 MOD_VEX_W_1_0F42_P_2_LEN_1
,
862 MOD_VEX_W_0_0F44_P_0_LEN_1
,
863 MOD_VEX_W_1_0F44_P_0_LEN_1
,
864 MOD_VEX_W_0_0F44_P_2_LEN_1
,
865 MOD_VEX_W_1_0F44_P_2_LEN_1
,
866 MOD_VEX_W_0_0F45_P_0_LEN_1
,
867 MOD_VEX_W_1_0F45_P_0_LEN_1
,
868 MOD_VEX_W_0_0F45_P_2_LEN_1
,
869 MOD_VEX_W_1_0F45_P_2_LEN_1
,
870 MOD_VEX_W_0_0F46_P_0_LEN_1
,
871 MOD_VEX_W_1_0F46_P_0_LEN_1
,
872 MOD_VEX_W_0_0F46_P_2_LEN_1
,
873 MOD_VEX_W_1_0F46_P_2_LEN_1
,
874 MOD_VEX_W_0_0F47_P_0_LEN_1
,
875 MOD_VEX_W_1_0F47_P_0_LEN_1
,
876 MOD_VEX_W_0_0F47_P_2_LEN_1
,
877 MOD_VEX_W_1_0F47_P_2_LEN_1
,
878 MOD_VEX_W_0_0F4A_P_0_LEN_1
,
879 MOD_VEX_W_1_0F4A_P_0_LEN_1
,
880 MOD_VEX_W_0_0F4A_P_2_LEN_1
,
881 MOD_VEX_W_1_0F4A_P_2_LEN_1
,
882 MOD_VEX_W_0_0F4B_P_0_LEN_1
,
883 MOD_VEX_W_1_0F4B_P_0_LEN_1
,
884 MOD_VEX_W_0_0F4B_P_2_LEN_1
,
896 MOD_VEX_W_0_0F91_P_0_LEN_0
,
897 MOD_VEX_W_1_0F91_P_0_LEN_0
,
898 MOD_VEX_W_0_0F91_P_2_LEN_0
,
899 MOD_VEX_W_1_0F91_P_2_LEN_0
,
900 MOD_VEX_W_0_0F92_P_0_LEN_0
,
901 MOD_VEX_W_0_0F92_P_2_LEN_0
,
902 MOD_VEX_0F92_P_3_LEN_0
,
903 MOD_VEX_W_0_0F93_P_0_LEN_0
,
904 MOD_VEX_W_0_0F93_P_2_LEN_0
,
905 MOD_VEX_0F93_P_3_LEN_0
,
906 MOD_VEX_W_0_0F98_P_0_LEN_0
,
907 MOD_VEX_W_1_0F98_P_0_LEN_0
,
908 MOD_VEX_W_0_0F98_P_2_LEN_0
,
909 MOD_VEX_W_1_0F98_P_2_LEN_0
,
910 MOD_VEX_W_0_0F99_P_0_LEN_0
,
911 MOD_VEX_W_1_0F99_P_0_LEN_0
,
912 MOD_VEX_W_0_0F99_P_2_LEN_0
,
913 MOD_VEX_W_1_0F99_P_2_LEN_0
,
916 MOD_VEX_0FD7_PREFIX_2
,
917 MOD_VEX_0FE7_PREFIX_2
,
918 MOD_VEX_0FF0_PREFIX_3
,
919 MOD_VEX_0F381A_PREFIX_2
,
920 MOD_VEX_0F382A_PREFIX_2
,
921 MOD_VEX_0F382C_PREFIX_2
,
922 MOD_VEX_0F382D_PREFIX_2
,
923 MOD_VEX_0F382E_PREFIX_2
,
924 MOD_VEX_0F382F_PREFIX_2
,
925 MOD_VEX_0F385A_PREFIX_2
,
926 MOD_VEX_0F388C_PREFIX_2
,
927 MOD_VEX_0F388E_PREFIX_2
,
928 MOD_VEX_W_0_0F3A30_P_2_LEN_0
,
929 MOD_VEX_W_1_0F3A30_P_2_LEN_0
,
930 MOD_VEX_W_0_0F3A31_P_2_LEN_0
,
931 MOD_VEX_W_1_0F3A31_P_2_LEN_0
,
932 MOD_VEX_W_0_0F3A32_P_2_LEN_0
,
933 MOD_VEX_W_1_0F3A32_P_2_LEN_0
,
934 MOD_VEX_W_0_0F3A33_P_2_LEN_0
,
935 MOD_VEX_W_1_0F3A33_P_2_LEN_0
,
937 MOD_EVEX_0F12_PREFIX_0
,
938 MOD_EVEX_0F16_PREFIX_0
,
939 MOD_EVEX_0F38C6_REG_1
,
940 MOD_EVEX_0F38C6_REG_2
,
941 MOD_EVEX_0F38C6_REG_5
,
942 MOD_EVEX_0F38C6_REG_6
,
943 MOD_EVEX_0F38C7_REG_1
,
944 MOD_EVEX_0F38C7_REG_2
,
945 MOD_EVEX_0F38C7_REG_5
,
946 MOD_EVEX_0F38C7_REG_6
959 RM_0F1E_P_1_MOD_3_REG_7
,
960 RM_0FAE_REG_6_MOD_3_P_0
,
967 PREFIX_0F01_REG_5_MOD_0
,
968 PREFIX_0F01_REG_5_MOD_3_RM_0
,
969 PREFIX_0F01_REG_5_MOD_3_RM_2
,
970 PREFIX_0F01_REG_7_MOD_3_RM_2
,
971 PREFIX_0F01_REG_7_MOD_3_RM_3
,
1013 PREFIX_0FAE_REG_0_MOD_3
,
1014 PREFIX_0FAE_REG_1_MOD_3
,
1015 PREFIX_0FAE_REG_2_MOD_3
,
1016 PREFIX_0FAE_REG_3_MOD_3
,
1017 PREFIX_0FAE_REG_4_MOD_0
,
1018 PREFIX_0FAE_REG_4_MOD_3
,
1019 PREFIX_0FAE_REG_5_MOD_0
,
1020 PREFIX_0FAE_REG_5_MOD_3
,
1021 PREFIX_0FAE_REG_6_MOD_0
,
1022 PREFIX_0FAE_REG_6_MOD_3
,
1023 PREFIX_0FAE_REG_7_MOD_0
,
1029 PREFIX_0FC7_REG_6_MOD_0
,
1030 PREFIX_0FC7_REG_6_MOD_3
,
1031 PREFIX_0FC7_REG_7_MOD_3
,
1161 PREFIX_VEX_0F71_REG_2
,
1162 PREFIX_VEX_0F71_REG_4
,
1163 PREFIX_VEX_0F71_REG_6
,
1164 PREFIX_VEX_0F72_REG_2
,
1165 PREFIX_VEX_0F72_REG_4
,
1166 PREFIX_VEX_0F72_REG_6
,
1167 PREFIX_VEX_0F73_REG_2
,
1168 PREFIX_VEX_0F73_REG_3
,
1169 PREFIX_VEX_0F73_REG_6
,
1170 PREFIX_VEX_0F73_REG_7
,
1343 PREFIX_VEX_0F38F3_REG_1
,
1344 PREFIX_VEX_0F38F3_REG_2
,
1345 PREFIX_VEX_0F38F3_REG_3
,
1464 PREFIX_EVEX_0F71_REG_2
,
1465 PREFIX_EVEX_0F71_REG_4
,
1466 PREFIX_EVEX_0F71_REG_6
,
1467 PREFIX_EVEX_0F72_REG_0
,
1468 PREFIX_EVEX_0F72_REG_1
,
1469 PREFIX_EVEX_0F72_REG_2
,
1470 PREFIX_EVEX_0F72_REG_4
,
1471 PREFIX_EVEX_0F72_REG_6
,
1472 PREFIX_EVEX_0F73_REG_2
,
1473 PREFIX_EVEX_0F73_REG_3
,
1474 PREFIX_EVEX_0F73_REG_6
,
1475 PREFIX_EVEX_0F73_REG_7
,
1672 PREFIX_EVEX_0F38C6_REG_1
,
1673 PREFIX_EVEX_0F38C6_REG_2
,
1674 PREFIX_EVEX_0F38C6_REG_5
,
1675 PREFIX_EVEX_0F38C6_REG_6
,
1676 PREFIX_EVEX_0F38C7_REG_1
,
1677 PREFIX_EVEX_0F38C7_REG_2
,
1678 PREFIX_EVEX_0F38C7_REG_5
,
1679 PREFIX_EVEX_0F38C7_REG_6
,
1781 THREE_BYTE_0F38
= 0,
1808 VEX_LEN_0F12_P_0_M_0
= 0,
1809 VEX_LEN_0F12_P_0_M_1
,
1812 VEX_LEN_0F16_P_0_M_0
,
1813 VEX_LEN_0F16_P_0_M_1
,
1850 VEX_LEN_0FAE_R_2_M_0
,
1851 VEX_LEN_0FAE_R_3_M_0
,
1858 VEX_LEN_0F381A_P_2_M_0
,
1861 VEX_LEN_0F385A_P_2_M_0
,
1864 VEX_LEN_0F38F3_R_1_P_0
,
1865 VEX_LEN_0F38F3_R_2_P_0
,
1866 VEX_LEN_0F38F3_R_3_P_0
,
1909 VEX_LEN_0FXOP_08_CC
,
1910 VEX_LEN_0FXOP_08_CD
,
1911 VEX_LEN_0FXOP_08_CE
,
1912 VEX_LEN_0FXOP_08_CF
,
1913 VEX_LEN_0FXOP_08_EC
,
1914 VEX_LEN_0FXOP_08_ED
,
1915 VEX_LEN_0FXOP_08_EE
,
1916 VEX_LEN_0FXOP_08_EF
,
1917 VEX_LEN_0FXOP_09_80
,
1923 EVEX_LEN_0F6E_P_2
= 0,
1927 EVEX_LEN_0F3819_P_2_W_0
,
1928 EVEX_LEN_0F3819_P_2_W_1
,
1929 EVEX_LEN_0F381A_P_2_W_0
,
1930 EVEX_LEN_0F381A_P_2_W_1
,
1931 EVEX_LEN_0F381B_P_2_W_0
,
1932 EVEX_LEN_0F381B_P_2_W_1
,
1933 EVEX_LEN_0F385A_P_2_W_0
,
1934 EVEX_LEN_0F385A_P_2_W_1
,
1935 EVEX_LEN_0F385B_P_2_W_0
,
1936 EVEX_LEN_0F385B_P_2_W_1
,
1937 EVEX_LEN_0F38C6_REG_1_PREFIX_2
,
1938 EVEX_LEN_0F38C6_REG_2_PREFIX_2
,
1939 EVEX_LEN_0F38C6_REG_5_PREFIX_2
,
1940 EVEX_LEN_0F38C6_REG_6_PREFIX_2
,
1941 EVEX_LEN_0F38C7_R_1_P_2_W_0
,
1942 EVEX_LEN_0F38C7_R_1_P_2_W_1
,
1943 EVEX_LEN_0F38C7_R_2_P_2_W_0
,
1944 EVEX_LEN_0F38C7_R_2_P_2_W_1
,
1945 EVEX_LEN_0F38C7_R_5_P_2_W_0
,
1946 EVEX_LEN_0F38C7_R_5_P_2_W_1
,
1947 EVEX_LEN_0F38C7_R_6_P_2_W_0
,
1948 EVEX_LEN_0F38C7_R_6_P_2_W_1
,
1949 EVEX_LEN_0F3A18_P_2_W_0
,
1950 EVEX_LEN_0F3A18_P_2_W_1
,
1951 EVEX_LEN_0F3A19_P_2_W_0
,
1952 EVEX_LEN_0F3A19_P_2_W_1
,
1953 EVEX_LEN_0F3A1A_P_2_W_0
,
1954 EVEX_LEN_0F3A1A_P_2_W_1
,
1955 EVEX_LEN_0F3A1B_P_2_W_0
,
1956 EVEX_LEN_0F3A1B_P_2_W_1
,
1957 EVEX_LEN_0F3A23_P_2_W_0
,
1958 EVEX_LEN_0F3A23_P_2_W_1
,
1959 EVEX_LEN_0F3A38_P_2_W_0
,
1960 EVEX_LEN_0F3A38_P_2_W_1
,
1961 EVEX_LEN_0F3A39_P_2_W_0
,
1962 EVEX_LEN_0F3A39_P_2_W_1
,
1963 EVEX_LEN_0F3A3A_P_2_W_0
,
1964 EVEX_LEN_0F3A3A_P_2_W_1
,
1965 EVEX_LEN_0F3A3B_P_2_W_0
,
1966 EVEX_LEN_0F3A3B_P_2_W_1
,
1967 EVEX_LEN_0F3A43_P_2_W_0
,
1968 EVEX_LEN_0F3A43_P_2_W_1
1973 VEX_W_0F41_P_0_LEN_1
= 0,
1974 VEX_W_0F41_P_2_LEN_1
,
1975 VEX_W_0F42_P_0_LEN_1
,
1976 VEX_W_0F42_P_2_LEN_1
,
1977 VEX_W_0F44_P_0_LEN_0
,
1978 VEX_W_0F44_P_2_LEN_0
,
1979 VEX_W_0F45_P_0_LEN_1
,
1980 VEX_W_0F45_P_2_LEN_1
,
1981 VEX_W_0F46_P_0_LEN_1
,
1982 VEX_W_0F46_P_2_LEN_1
,
1983 VEX_W_0F47_P_0_LEN_1
,
1984 VEX_W_0F47_P_2_LEN_1
,
1985 VEX_W_0F4A_P_0_LEN_1
,
1986 VEX_W_0F4A_P_2_LEN_1
,
1987 VEX_W_0F4B_P_0_LEN_1
,
1988 VEX_W_0F4B_P_2_LEN_1
,
1989 VEX_W_0F90_P_0_LEN_0
,
1990 VEX_W_0F90_P_2_LEN_0
,
1991 VEX_W_0F91_P_0_LEN_0
,
1992 VEX_W_0F91_P_2_LEN_0
,
1993 VEX_W_0F92_P_0_LEN_0
,
1994 VEX_W_0F92_P_2_LEN_0
,
1995 VEX_W_0F93_P_0_LEN_0
,
1996 VEX_W_0F93_P_2_LEN_0
,
1997 VEX_W_0F98_P_0_LEN_0
,
1998 VEX_W_0F98_P_2_LEN_0
,
1999 VEX_W_0F99_P_0_LEN_0
,
2000 VEX_W_0F99_P_2_LEN_0
,
2008 VEX_W_0F381A_P_2_M_0
,
2009 VEX_W_0F382C_P_2_M_0
,
2010 VEX_W_0F382D_P_2_M_0
,
2011 VEX_W_0F382E_P_2_M_0
,
2012 VEX_W_0F382F_P_2_M_0
,
2017 VEX_W_0F385A_P_2_M_0
,
2029 VEX_W_0F3A30_P_2_LEN_0
,
2030 VEX_W_0F3A31_P_2_LEN_0
,
2031 VEX_W_0F3A32_P_2_LEN_0
,
2032 VEX_W_0F3A33_P_2_LEN_0
,
2052 EVEX_W_0F12_P_0_M_0
,
2053 EVEX_W_0F12_P_0_M_1
,
2063 EVEX_W_0F16_P_0_M_0
,
2064 EVEX_W_0F16_P_0_M_1
,
2133 EVEX_W_0F72_R_2_P_2
,
2134 EVEX_W_0F72_R_6_P_2
,
2135 EVEX_W_0F73_R_2_P_2
,
2136 EVEX_W_0F73_R_6_P_2
,
2246 EVEX_W_0F38C7_R_1_P_2
,
2247 EVEX_W_0F38C7_R_2_P_2
,
2248 EVEX_W_0F38C7_R_5_P_2
,
2249 EVEX_W_0F38C7_R_6_P_2
,
2288 typedef void (*op_rtn
) (int bytemode
, int sizeflag
);
2297 unsigned int prefix_requirement
;
2300 /* Upper case letters in the instruction names here are macros.
2301 'A' => print 'b' if no register operands or suffix_always is true
2302 'B' => print 'b' if suffix_always is true
2303 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2305 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2306 suffix_always is true
2307 'E' => print 'e' if 32-bit form of jcxz
2308 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2309 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2310 'H' => print ",pt" or ",pn" branch hint
2311 'I' => honor following macro letter even in Intel mode (implemented only
2312 for some of the macro letters)
2314 'K' => print 'd' or 'q' if rex prefix is present.
2315 'L' => print 'l' if suffix_always is true
2316 'M' => print 'r' if intel_mnemonic is false.
2317 'N' => print 'n' if instruction has no wait "prefix"
2318 'O' => print 'd' or 'o' (or 'q' in Intel mode)
2319 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2320 or suffix_always is true. print 'q' if rex prefix is present.
2321 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2323 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2324 'S' => print 'w', 'l' or 'q' if suffix_always is true
2325 'T' => print 'q' in 64bit mode if instruction has no operand size
2326 prefix and behave as 'P' otherwise
2327 'U' => print 'q' in 64bit mode if instruction has no operand size
2328 prefix and behave as 'Q' otherwise
2329 'V' => print 'q' in 64bit mode if instruction has no operand size
2330 prefix and behave as 'S' otherwise
2331 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2332 'X' => print 's', 'd' depending on data16 prefix (for XMM)
2334 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2335 '!' => change condition from true to false or from false to true.
2336 '%' => add 1 upper case letter to the macro.
2337 '^' => print 'w' or 'l' depending on operand size prefix or
2338 suffix_always is true (lcall/ljmp).
2339 '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2340 on operand size prefix.
2341 '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2342 has no operand size prefix for AMD64 ISA, behave as 'P'
2345 2 upper case letter macros:
2346 "XY" => print 'x' or 'y' if suffix_always is true or no register
2347 operands and no broadcast.
2348 "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2349 register operands and no broadcast.
2350 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2351 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2352 or suffix_always is true
2353 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2354 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2355 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2356 "LW" => print 'd', 'q' depending on the VEX.W bit
2357 "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2358 an operand size prefix, or suffix_always is true. print
2359 'q' if rex prefix is present.
2361 Many of the above letters print nothing in Intel mode. See "putop"
2364 Braces '{' and '}', and vertical bars '|', indicate alternative
2365 mnemonic strings for AT&T and Intel. */
2367 static const struct dis386 dis386
[] = {
2369 { "addB", { Ebh1
, Gb
}, 0 },
2370 { "addS", { Evh1
, Gv
}, 0 },
2371 { "addB", { Gb
, EbS
}, 0 },
2372 { "addS", { Gv
, EvS
}, 0 },
2373 { "addB", { AL
, Ib
}, 0 },
2374 { "addS", { eAX
, Iv
}, 0 },
2375 { X86_64_TABLE (X86_64_06
) },
2376 { X86_64_TABLE (X86_64_07
) },
2378 { "orB", { Ebh1
, Gb
}, 0 },
2379 { "orS", { Evh1
, Gv
}, 0 },
2380 { "orB", { Gb
, EbS
}, 0 },
2381 { "orS", { Gv
, EvS
}, 0 },
2382 { "orB", { AL
, Ib
}, 0 },
2383 { "orS", { eAX
, Iv
}, 0 },
2384 { X86_64_TABLE (X86_64_0D
) },
2385 { Bad_Opcode
}, /* 0x0f extended opcode escape */
2387 { "adcB", { Ebh1
, Gb
}, 0 },
2388 { "adcS", { Evh1
, Gv
}, 0 },
2389 { "adcB", { Gb
, EbS
}, 0 },
2390 { "adcS", { Gv
, EvS
}, 0 },
2391 { "adcB", { AL
, Ib
}, 0 },
2392 { "adcS", { eAX
, Iv
}, 0 },
2393 { X86_64_TABLE (X86_64_16
) },
2394 { X86_64_TABLE (X86_64_17
) },
2396 { "sbbB", { Ebh1
, Gb
}, 0 },
2397 { "sbbS", { Evh1
, Gv
}, 0 },
2398 { "sbbB", { Gb
, EbS
}, 0 },
2399 { "sbbS", { Gv
, EvS
}, 0 },
2400 { "sbbB", { AL
, Ib
}, 0 },
2401 { "sbbS", { eAX
, Iv
}, 0 },
2402 { X86_64_TABLE (X86_64_1E
) },
2403 { X86_64_TABLE (X86_64_1F
) },
2405 { "andB", { Ebh1
, Gb
}, 0 },
2406 { "andS", { Evh1
, Gv
}, 0 },
2407 { "andB", { Gb
, EbS
}, 0 },
2408 { "andS", { Gv
, EvS
}, 0 },
2409 { "andB", { AL
, Ib
}, 0 },
2410 { "andS", { eAX
, Iv
}, 0 },
2411 { Bad_Opcode
}, /* SEG ES prefix */
2412 { X86_64_TABLE (X86_64_27
) },
2414 { "subB", { Ebh1
, Gb
}, 0 },
2415 { "subS", { Evh1
, Gv
}, 0 },
2416 { "subB", { Gb
, EbS
}, 0 },
2417 { "subS", { Gv
, EvS
}, 0 },
2418 { "subB", { AL
, Ib
}, 0 },
2419 { "subS", { eAX
, Iv
}, 0 },
2420 { Bad_Opcode
}, /* SEG CS prefix */
2421 { X86_64_TABLE (X86_64_2F
) },
2423 { "xorB", { Ebh1
, Gb
}, 0 },
2424 { "xorS", { Evh1
, Gv
}, 0 },
2425 { "xorB", { Gb
, EbS
}, 0 },
2426 { "xorS", { Gv
, EvS
}, 0 },
2427 { "xorB", { AL
, Ib
}, 0 },
2428 { "xorS", { eAX
, Iv
}, 0 },
2429 { Bad_Opcode
}, /* SEG SS prefix */
2430 { X86_64_TABLE (X86_64_37
) },
2432 { "cmpB", { Eb
, Gb
}, 0 },
2433 { "cmpS", { Ev
, Gv
}, 0 },
2434 { "cmpB", { Gb
, EbS
}, 0 },
2435 { "cmpS", { Gv
, EvS
}, 0 },
2436 { "cmpB", { AL
, Ib
}, 0 },
2437 { "cmpS", { eAX
, Iv
}, 0 },
2438 { Bad_Opcode
}, /* SEG DS prefix */
2439 { X86_64_TABLE (X86_64_3F
) },
2441 { "inc{S|}", { RMeAX
}, 0 },
2442 { "inc{S|}", { RMeCX
}, 0 },
2443 { "inc{S|}", { RMeDX
}, 0 },
2444 { "inc{S|}", { RMeBX
}, 0 },
2445 { "inc{S|}", { RMeSP
}, 0 },
2446 { "inc{S|}", { RMeBP
}, 0 },
2447 { "inc{S|}", { RMeSI
}, 0 },
2448 { "inc{S|}", { RMeDI
}, 0 },
2450 { "dec{S|}", { RMeAX
}, 0 },
2451 { "dec{S|}", { RMeCX
}, 0 },
2452 { "dec{S|}", { RMeDX
}, 0 },
2453 { "dec{S|}", { RMeBX
}, 0 },
2454 { "dec{S|}", { RMeSP
}, 0 },
2455 { "dec{S|}", { RMeBP
}, 0 },
2456 { "dec{S|}", { RMeSI
}, 0 },
2457 { "dec{S|}", { RMeDI
}, 0 },
2459 { "pushV", { RMrAX
}, 0 },
2460 { "pushV", { RMrCX
}, 0 },
2461 { "pushV", { RMrDX
}, 0 },
2462 { "pushV", { RMrBX
}, 0 },
2463 { "pushV", { RMrSP
}, 0 },
2464 { "pushV", { RMrBP
}, 0 },
2465 { "pushV", { RMrSI
}, 0 },
2466 { "pushV", { RMrDI
}, 0 },
2468 { "popV", { RMrAX
}, 0 },
2469 { "popV", { RMrCX
}, 0 },
2470 { "popV", { RMrDX
}, 0 },
2471 { "popV", { RMrBX
}, 0 },
2472 { "popV", { RMrSP
}, 0 },
2473 { "popV", { RMrBP
}, 0 },
2474 { "popV", { RMrSI
}, 0 },
2475 { "popV", { RMrDI
}, 0 },
2477 { X86_64_TABLE (X86_64_60
) },
2478 { X86_64_TABLE (X86_64_61
) },
2479 { X86_64_TABLE (X86_64_62
) },
2480 { X86_64_TABLE (X86_64_63
) },
2481 { Bad_Opcode
}, /* seg fs */
2482 { Bad_Opcode
}, /* seg gs */
2483 { Bad_Opcode
}, /* op size prefix */
2484 { Bad_Opcode
}, /* adr size prefix */
2486 { "pushT", { sIv
}, 0 },
2487 { "imulS", { Gv
, Ev
, Iv
}, 0 },
2488 { "pushT", { sIbT
}, 0 },
2489 { "imulS", { Gv
, Ev
, sIb
}, 0 },
2490 { "ins{b|}", { Ybr
, indirDX
}, 0 },
2491 { X86_64_TABLE (X86_64_6D
) },
2492 { "outs{b|}", { indirDXr
, Xb
}, 0 },
2493 { X86_64_TABLE (X86_64_6F
) },
2495 { "joH", { Jb
, BND
, cond_jump_flag
}, 0 },
2496 { "jnoH", { Jb
, BND
, cond_jump_flag
}, 0 },
2497 { "jbH", { Jb
, BND
, cond_jump_flag
}, 0 },
2498 { "jaeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2499 { "jeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2500 { "jneH", { Jb
, BND
, cond_jump_flag
}, 0 },
2501 { "jbeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2502 { "jaH", { Jb
, BND
, cond_jump_flag
}, 0 },
2504 { "jsH", { Jb
, BND
, cond_jump_flag
}, 0 },
2505 { "jnsH", { Jb
, BND
, cond_jump_flag
}, 0 },
2506 { "jpH", { Jb
, BND
, cond_jump_flag
}, 0 },
2507 { "jnpH", { Jb
, BND
, cond_jump_flag
}, 0 },
2508 { "jlH", { Jb
, BND
, cond_jump_flag
}, 0 },
2509 { "jgeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2510 { "jleH", { Jb
, BND
, cond_jump_flag
}, 0 },
2511 { "jgH", { Jb
, BND
, cond_jump_flag
}, 0 },
2513 { REG_TABLE (REG_80
) },
2514 { REG_TABLE (REG_81
) },
2515 { X86_64_TABLE (X86_64_82
) },
2516 { REG_TABLE (REG_83
) },
2517 { "testB", { Eb
, Gb
}, 0 },
2518 { "testS", { Ev
, Gv
}, 0 },
2519 { "xchgB", { Ebh2
, Gb
}, 0 },
2520 { "xchgS", { Evh2
, Gv
}, 0 },
2522 { "movB", { Ebh3
, Gb
}, 0 },
2523 { "movS", { Evh3
, Gv
}, 0 },
2524 { "movB", { Gb
, EbS
}, 0 },
2525 { "movS", { Gv
, EvS
}, 0 },
2526 { "movD", { Sv
, Sw
}, 0 },
2527 { MOD_TABLE (MOD_8D
) },
2528 { "movD", { Sw
, Sv
}, 0 },
2529 { REG_TABLE (REG_8F
) },
2531 { PREFIX_TABLE (PREFIX_90
) },
2532 { "xchgS", { RMeCX
, eAX
}, 0 },
2533 { "xchgS", { RMeDX
, eAX
}, 0 },
2534 { "xchgS", { RMeBX
, eAX
}, 0 },
2535 { "xchgS", { RMeSP
, eAX
}, 0 },
2536 { "xchgS", { RMeBP
, eAX
}, 0 },
2537 { "xchgS", { RMeSI
, eAX
}, 0 },
2538 { "xchgS", { RMeDI
, eAX
}, 0 },
2540 { "cW{t|}R", { XX
}, 0 },
2541 { "cR{t|}O", { XX
}, 0 },
2542 { X86_64_TABLE (X86_64_9A
) },
2543 { Bad_Opcode
}, /* fwait */
2544 { "pushfT", { XX
}, 0 },
2545 { "popfT", { XX
}, 0 },
2546 { "sahf", { XX
}, 0 },
2547 { "lahf", { XX
}, 0 },
2549 { "mov%LB", { AL
, Ob
}, 0 },
2550 { "mov%LS", { eAX
, Ov
}, 0 },
2551 { "mov%LB", { Ob
, AL
}, 0 },
2552 { "mov%LS", { Ov
, eAX
}, 0 },
2553 { "movs{b|}", { Ybr
, Xb
}, 0 },
2554 { "movs{R|}", { Yvr
, Xv
}, 0 },
2555 { "cmps{b|}", { Xb
, Yb
}, 0 },
2556 { "cmps{R|}", { Xv
, Yv
}, 0 },
2558 { "testB", { AL
, Ib
}, 0 },
2559 { "testS", { eAX
, Iv
}, 0 },
2560 { "stosB", { Ybr
, AL
}, 0 },
2561 { "stosS", { Yvr
, eAX
}, 0 },
2562 { "lodsB", { ALr
, Xb
}, 0 },
2563 { "lodsS", { eAXr
, Xv
}, 0 },
2564 { "scasB", { AL
, Yb
}, 0 },
2565 { "scasS", { eAX
, Yv
}, 0 },
2567 { "movB", { RMAL
, Ib
}, 0 },
2568 { "movB", { RMCL
, Ib
}, 0 },
2569 { "movB", { RMDL
, Ib
}, 0 },
2570 { "movB", { RMBL
, Ib
}, 0 },
2571 { "movB", { RMAH
, Ib
}, 0 },
2572 { "movB", { RMCH
, Ib
}, 0 },
2573 { "movB", { RMDH
, Ib
}, 0 },
2574 { "movB", { RMBH
, Ib
}, 0 },
2576 { "mov%LV", { RMeAX
, Iv64
}, 0 },
2577 { "mov%LV", { RMeCX
, Iv64
}, 0 },
2578 { "mov%LV", { RMeDX
, Iv64
}, 0 },
2579 { "mov%LV", { RMeBX
, Iv64
}, 0 },
2580 { "mov%LV", { RMeSP
, Iv64
}, 0 },
2581 { "mov%LV", { RMeBP
, Iv64
}, 0 },
2582 { "mov%LV", { RMeSI
, Iv64
}, 0 },
2583 { "mov%LV", { RMeDI
, Iv64
}, 0 },
2585 { REG_TABLE (REG_C0
) },
2586 { REG_TABLE (REG_C1
) },
2587 { "retT", { Iw
, BND
}, 0 },
2588 { "retT", { BND
}, 0 },
2589 { X86_64_TABLE (X86_64_C4
) },
2590 { X86_64_TABLE (X86_64_C5
) },
2591 { REG_TABLE (REG_C6
) },
2592 { REG_TABLE (REG_C7
) },
2594 { "enterT", { Iw
, Ib
}, 0 },
2595 { "leaveT", { XX
}, 0 },
2596 { "Jret{|f}P", { Iw
}, 0 },
2597 { "Jret{|f}P", { XX
}, 0 },
2598 { "int3", { XX
}, 0 },
2599 { "int", { Ib
}, 0 },
2600 { X86_64_TABLE (X86_64_CE
) },
2601 { "iret%LP", { XX
}, 0 },
2603 { REG_TABLE (REG_D0
) },
2604 { REG_TABLE (REG_D1
) },
2605 { REG_TABLE (REG_D2
) },
2606 { REG_TABLE (REG_D3
) },
2607 { X86_64_TABLE (X86_64_D4
) },
2608 { X86_64_TABLE (X86_64_D5
) },
2610 { "xlat", { DSBX
}, 0 },
2621 { "loopneFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2622 { "loopeFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2623 { "loopFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2624 { "jEcxzH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2625 { "inB", { AL
, Ib
}, 0 },
2626 { "inG", { zAX
, Ib
}, 0 },
2627 { "outB", { Ib
, AL
}, 0 },
2628 { "outG", { Ib
, zAX
}, 0 },
2630 { X86_64_TABLE (X86_64_E8
) },
2631 { X86_64_TABLE (X86_64_E9
) },
2632 { X86_64_TABLE (X86_64_EA
) },
2633 { "jmp", { Jb
, BND
}, 0 },
2634 { "inB", { AL
, indirDX
}, 0 },
2635 { "inG", { zAX
, indirDX
}, 0 },
2636 { "outB", { indirDX
, AL
}, 0 },
2637 { "outG", { indirDX
, zAX
}, 0 },
2639 { Bad_Opcode
}, /* lock prefix */
2640 { "icebp", { XX
}, 0 },
2641 { Bad_Opcode
}, /* repne */
2642 { Bad_Opcode
}, /* repz */
2643 { "hlt", { XX
}, 0 },
2644 { "cmc", { XX
}, 0 },
2645 { REG_TABLE (REG_F6
) },
2646 { REG_TABLE (REG_F7
) },
2648 { "clc", { XX
}, 0 },
2649 { "stc", { XX
}, 0 },
2650 { "cli", { XX
}, 0 },
2651 { "sti", { XX
}, 0 },
2652 { "cld", { XX
}, 0 },
2653 { "std", { XX
}, 0 },
2654 { REG_TABLE (REG_FE
) },
2655 { REG_TABLE (REG_FF
) },
2658 static const struct dis386 dis386_twobyte
[] = {
2660 { REG_TABLE (REG_0F00
) },
2661 { REG_TABLE (REG_0F01
) },
2662 { "larS", { Gv
, Ew
}, 0 },
2663 { "lslS", { Gv
, Ew
}, 0 },
2665 { "syscall", { XX
}, 0 },
2666 { "clts", { XX
}, 0 },
2667 { "sysret%LP", { XX
}, 0 },
2669 { "invd", { XX
}, 0 },
2670 { PREFIX_TABLE (PREFIX_0F09
) },
2672 { "ud2", { XX
}, 0 },
2674 { REG_TABLE (REG_0F0D
) },
2675 { "femms", { XX
}, 0 },
2676 { "", { MX
, EM
, OPSUF
}, 0 }, /* See OP_3DNowSuffix. */
2678 { PREFIX_TABLE (PREFIX_0F10
) },
2679 { PREFIX_TABLE (PREFIX_0F11
) },
2680 { PREFIX_TABLE (PREFIX_0F12
) },
2681 { MOD_TABLE (MOD_0F13
) },
2682 { "unpcklpX", { XM
, EXx
}, PREFIX_OPCODE
},
2683 { "unpckhpX", { XM
, EXx
}, PREFIX_OPCODE
},
2684 { PREFIX_TABLE (PREFIX_0F16
) },
2685 { MOD_TABLE (MOD_0F17
) },
2687 { REG_TABLE (REG_0F18
) },
2688 { "nopQ", { Ev
}, 0 },
2689 { PREFIX_TABLE (PREFIX_0F1A
) },
2690 { PREFIX_TABLE (PREFIX_0F1B
) },
2691 { PREFIX_TABLE (PREFIX_0F1C
) },
2692 { "nopQ", { Ev
}, 0 },
2693 { PREFIX_TABLE (PREFIX_0F1E
) },
2694 { "nopQ", { Ev
}, 0 },
2696 { "movZ", { Rm
, Cm
}, 0 },
2697 { "movZ", { Rm
, Dm
}, 0 },
2698 { "movZ", { Cm
, Rm
}, 0 },
2699 { "movZ", { Dm
, Rm
}, 0 },
2700 { MOD_TABLE (MOD_0F24
) },
2702 { MOD_TABLE (MOD_0F26
) },
2705 { "movapX", { XM
, EXx
}, PREFIX_OPCODE
},
2706 { "movapX", { EXxS
, XM
}, PREFIX_OPCODE
},
2707 { PREFIX_TABLE (PREFIX_0F2A
) },
2708 { PREFIX_TABLE (PREFIX_0F2B
) },
2709 { PREFIX_TABLE (PREFIX_0F2C
) },
2710 { PREFIX_TABLE (PREFIX_0F2D
) },
2711 { PREFIX_TABLE (PREFIX_0F2E
) },
2712 { PREFIX_TABLE (PREFIX_0F2F
) },
2714 { "wrmsr", { XX
}, 0 },
2715 { "rdtsc", { XX
}, 0 },
2716 { "rdmsr", { XX
}, 0 },
2717 { "rdpmc", { XX
}, 0 },
2718 { "sysenter", { SEP
}, 0 },
2719 { "sysexit", { SEP
}, 0 },
2721 { "getsec", { XX
}, 0 },
2723 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38
, PREFIX_OPCODE
) },
2725 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A
, PREFIX_OPCODE
) },
2732 { "cmovoS", { Gv
, Ev
}, 0 },
2733 { "cmovnoS", { Gv
, Ev
}, 0 },
2734 { "cmovbS", { Gv
, Ev
}, 0 },
2735 { "cmovaeS", { Gv
, Ev
}, 0 },
2736 { "cmoveS", { Gv
, Ev
}, 0 },
2737 { "cmovneS", { Gv
, Ev
}, 0 },
2738 { "cmovbeS", { Gv
, Ev
}, 0 },
2739 { "cmovaS", { Gv
, Ev
}, 0 },
2741 { "cmovsS", { Gv
, Ev
}, 0 },
2742 { "cmovnsS", { Gv
, Ev
}, 0 },
2743 { "cmovpS", { Gv
, Ev
}, 0 },
2744 { "cmovnpS", { Gv
, Ev
}, 0 },
2745 { "cmovlS", { Gv
, Ev
}, 0 },
2746 { "cmovgeS", { Gv
, Ev
}, 0 },
2747 { "cmovleS", { Gv
, Ev
}, 0 },
2748 { "cmovgS", { Gv
, Ev
}, 0 },
2750 { MOD_TABLE (MOD_0F51
) },
2751 { PREFIX_TABLE (PREFIX_0F51
) },
2752 { PREFIX_TABLE (PREFIX_0F52
) },
2753 { PREFIX_TABLE (PREFIX_0F53
) },
2754 { "andpX", { XM
, EXx
}, PREFIX_OPCODE
},
2755 { "andnpX", { XM
, EXx
}, PREFIX_OPCODE
},
2756 { "orpX", { XM
, EXx
}, PREFIX_OPCODE
},
2757 { "xorpX", { XM
, EXx
}, PREFIX_OPCODE
},
2759 { PREFIX_TABLE (PREFIX_0F58
) },
2760 { PREFIX_TABLE (PREFIX_0F59
) },
2761 { PREFIX_TABLE (PREFIX_0F5A
) },
2762 { PREFIX_TABLE (PREFIX_0F5B
) },
2763 { PREFIX_TABLE (PREFIX_0F5C
) },
2764 { PREFIX_TABLE (PREFIX_0F5D
) },
2765 { PREFIX_TABLE (PREFIX_0F5E
) },
2766 { PREFIX_TABLE (PREFIX_0F5F
) },
2768 { PREFIX_TABLE (PREFIX_0F60
) },
2769 { PREFIX_TABLE (PREFIX_0F61
) },
2770 { PREFIX_TABLE (PREFIX_0F62
) },
2771 { "packsswb", { MX
, EM
}, PREFIX_OPCODE
},
2772 { "pcmpgtb", { MX
, EM
}, PREFIX_OPCODE
},
2773 { "pcmpgtw", { MX
, EM
}, PREFIX_OPCODE
},
2774 { "pcmpgtd", { MX
, EM
}, PREFIX_OPCODE
},
2775 { "packuswb", { MX
, EM
}, PREFIX_OPCODE
},
2777 { "punpckhbw", { MX
, EM
}, PREFIX_OPCODE
},
2778 { "punpckhwd", { MX
, EM
}, PREFIX_OPCODE
},
2779 { "punpckhdq", { MX
, EM
}, PREFIX_OPCODE
},
2780 { "packssdw", { MX
, EM
}, PREFIX_OPCODE
},
2781 { PREFIX_TABLE (PREFIX_0F6C
) },
2782 { PREFIX_TABLE (PREFIX_0F6D
) },
2783 { "movK", { MX
, Edq
}, PREFIX_OPCODE
},
2784 { PREFIX_TABLE (PREFIX_0F6F
) },
2786 { PREFIX_TABLE (PREFIX_0F70
) },
2787 { REG_TABLE (REG_0F71
) },
2788 { REG_TABLE (REG_0F72
) },
2789 { REG_TABLE (REG_0F73
) },
2790 { "pcmpeqb", { MX
, EM
}, PREFIX_OPCODE
},
2791 { "pcmpeqw", { MX
, EM
}, PREFIX_OPCODE
},
2792 { "pcmpeqd", { MX
, EM
}, PREFIX_OPCODE
},
2793 { "emms", { XX
}, PREFIX_OPCODE
},
2795 { PREFIX_TABLE (PREFIX_0F78
) },
2796 { PREFIX_TABLE (PREFIX_0F79
) },
2799 { PREFIX_TABLE (PREFIX_0F7C
) },
2800 { PREFIX_TABLE (PREFIX_0F7D
) },
2801 { PREFIX_TABLE (PREFIX_0F7E
) },
2802 { PREFIX_TABLE (PREFIX_0F7F
) },
2804 { "joH", { Jv
, BND
, cond_jump_flag
}, 0 },
2805 { "jnoH", { Jv
, BND
, cond_jump_flag
}, 0 },
2806 { "jbH", { Jv
, BND
, cond_jump_flag
}, 0 },
2807 { "jaeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2808 { "jeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2809 { "jneH", { Jv
, BND
, cond_jump_flag
}, 0 },
2810 { "jbeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2811 { "jaH", { Jv
, BND
, cond_jump_flag
}, 0 },
2813 { "jsH", { Jv
, BND
, cond_jump_flag
}, 0 },
2814 { "jnsH", { Jv
, BND
, cond_jump_flag
}, 0 },
2815 { "jpH", { Jv
, BND
, cond_jump_flag
}, 0 },
2816 { "jnpH", { Jv
, BND
, cond_jump_flag
}, 0 },
2817 { "jlH", { Jv
, BND
, cond_jump_flag
}, 0 },
2818 { "jgeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2819 { "jleH", { Jv
, BND
, cond_jump_flag
}, 0 },
2820 { "jgH", { Jv
, BND
, cond_jump_flag
}, 0 },
2822 { "seto", { Eb
}, 0 },
2823 { "setno", { Eb
}, 0 },
2824 { "setb", { Eb
}, 0 },
2825 { "setae", { Eb
}, 0 },
2826 { "sete", { Eb
}, 0 },
2827 { "setne", { Eb
}, 0 },
2828 { "setbe", { Eb
}, 0 },
2829 { "seta", { Eb
}, 0 },
2831 { "sets", { Eb
}, 0 },
2832 { "setns", { Eb
}, 0 },
2833 { "setp", { Eb
}, 0 },
2834 { "setnp", { Eb
}, 0 },
2835 { "setl", { Eb
}, 0 },
2836 { "setge", { Eb
}, 0 },
2837 { "setle", { Eb
}, 0 },
2838 { "setg", { Eb
}, 0 },
2840 { "pushT", { fs
}, 0 },
2841 { "popT", { fs
}, 0 },
2842 { "cpuid", { XX
}, 0 },
2843 { "btS", { Ev
, Gv
}, 0 },
2844 { "shldS", { Ev
, Gv
, Ib
}, 0 },
2845 { "shldS", { Ev
, Gv
, CL
}, 0 },
2846 { REG_TABLE (REG_0FA6
) },
2847 { REG_TABLE (REG_0FA7
) },
2849 { "pushT", { gs
}, 0 },
2850 { "popT", { gs
}, 0 },
2851 { "rsm", { XX
}, 0 },
2852 { "btsS", { Evh1
, Gv
}, 0 },
2853 { "shrdS", { Ev
, Gv
, Ib
}, 0 },
2854 { "shrdS", { Ev
, Gv
, CL
}, 0 },
2855 { REG_TABLE (REG_0FAE
) },
2856 { "imulS", { Gv
, Ev
}, 0 },
2858 { "cmpxchgB", { Ebh1
, Gb
}, 0 },
2859 { "cmpxchgS", { Evh1
, Gv
}, 0 },
2860 { MOD_TABLE (MOD_0FB2
) },
2861 { "btrS", { Evh1
, Gv
}, 0 },
2862 { MOD_TABLE (MOD_0FB4
) },
2863 { MOD_TABLE (MOD_0FB5
) },
2864 { "movz{bR|x}", { Gv
, Eb
}, 0 },
2865 { "movz{wR|x}", { Gv
, Ew
}, 0 }, /* yes, there really is movzww ! */
2867 { PREFIX_TABLE (PREFIX_0FB8
) },
2868 { "ud1S", { Gv
, Ev
}, 0 },
2869 { REG_TABLE (REG_0FBA
) },
2870 { "btcS", { Evh1
, Gv
}, 0 },
2871 { PREFIX_TABLE (PREFIX_0FBC
) },
2872 { PREFIX_TABLE (PREFIX_0FBD
) },
2873 { "movs{bR|x}", { Gv
, Eb
}, 0 },
2874 { "movs{wR|x}", { Gv
, Ew
}, 0 }, /* yes, there really is movsww ! */
2876 { "xaddB", { Ebh1
, Gb
}, 0 },
2877 { "xaddS", { Evh1
, Gv
}, 0 },
2878 { PREFIX_TABLE (PREFIX_0FC2
) },
2879 { MOD_TABLE (MOD_0FC3
) },
2880 { "pinsrw", { MX
, Edqw
, Ib
}, PREFIX_OPCODE
},
2881 { "pextrw", { Gdq
, MS
, Ib
}, PREFIX_OPCODE
},
2882 { "shufpX", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
2883 { REG_TABLE (REG_0FC7
) },
2885 { "bswap", { RMeAX
}, 0 },
2886 { "bswap", { RMeCX
}, 0 },
2887 { "bswap", { RMeDX
}, 0 },
2888 { "bswap", { RMeBX
}, 0 },
2889 { "bswap", { RMeSP
}, 0 },
2890 { "bswap", { RMeBP
}, 0 },
2891 { "bswap", { RMeSI
}, 0 },
2892 { "bswap", { RMeDI
}, 0 },
2894 { PREFIX_TABLE (PREFIX_0FD0
) },
2895 { "psrlw", { MX
, EM
}, PREFIX_OPCODE
},
2896 { "psrld", { MX
, EM
}, PREFIX_OPCODE
},
2897 { "psrlq", { MX
, EM
}, PREFIX_OPCODE
},
2898 { "paddq", { MX
, EM
}, PREFIX_OPCODE
},
2899 { "pmullw", { MX
, EM
}, PREFIX_OPCODE
},
2900 { PREFIX_TABLE (PREFIX_0FD6
) },
2901 { MOD_TABLE (MOD_0FD7
) },
2903 { "psubusb", { MX
, EM
}, PREFIX_OPCODE
},
2904 { "psubusw", { MX
, EM
}, PREFIX_OPCODE
},
2905 { "pminub", { MX
, EM
}, PREFIX_OPCODE
},
2906 { "pand", { MX
, EM
}, PREFIX_OPCODE
},
2907 { "paddusb", { MX
, EM
}, PREFIX_OPCODE
},
2908 { "paddusw", { MX
, EM
}, PREFIX_OPCODE
},
2909 { "pmaxub", { MX
, EM
}, PREFIX_OPCODE
},
2910 { "pandn", { MX
, EM
}, PREFIX_OPCODE
},
2912 { "pavgb", { MX
, EM
}, PREFIX_OPCODE
},
2913 { "psraw", { MX
, EM
}, PREFIX_OPCODE
},
2914 { "psrad", { MX
, EM
}, PREFIX_OPCODE
},
2915 { "pavgw", { MX
, EM
}, PREFIX_OPCODE
},
2916 { "pmulhuw", { MX
, EM
}, PREFIX_OPCODE
},
2917 { "pmulhw", { MX
, EM
}, PREFIX_OPCODE
},
2918 { PREFIX_TABLE (PREFIX_0FE6
) },
2919 { PREFIX_TABLE (PREFIX_0FE7
) },
2921 { "psubsb", { MX
, EM
}, PREFIX_OPCODE
},
2922 { "psubsw", { MX
, EM
}, PREFIX_OPCODE
},
2923 { "pminsw", { MX
, EM
}, PREFIX_OPCODE
},
2924 { "por", { MX
, EM
}, PREFIX_OPCODE
},
2925 { "paddsb", { MX
, EM
}, PREFIX_OPCODE
},
2926 { "paddsw", { MX
, EM
}, PREFIX_OPCODE
},
2927 { "pmaxsw", { MX
, EM
}, PREFIX_OPCODE
},
2928 { "pxor", { MX
, EM
}, PREFIX_OPCODE
},
2930 { PREFIX_TABLE (PREFIX_0FF0
) },
2931 { "psllw", { MX
, EM
}, PREFIX_OPCODE
},
2932 { "pslld", { MX
, EM
}, PREFIX_OPCODE
},
2933 { "psllq", { MX
, EM
}, PREFIX_OPCODE
},
2934 { "pmuludq", { MX
, EM
}, PREFIX_OPCODE
},
2935 { "pmaddwd", { MX
, EM
}, PREFIX_OPCODE
},
2936 { "psadbw", { MX
, EM
}, PREFIX_OPCODE
},
2937 { PREFIX_TABLE (PREFIX_0FF7
) },
2939 { "psubb", { MX
, EM
}, PREFIX_OPCODE
},
2940 { "psubw", { MX
, EM
}, PREFIX_OPCODE
},
2941 { "psubd", { MX
, EM
}, PREFIX_OPCODE
},
2942 { "psubq", { MX
, EM
}, PREFIX_OPCODE
},
2943 { "paddb", { MX
, EM
}, PREFIX_OPCODE
},
2944 { "paddw", { MX
, EM
}, PREFIX_OPCODE
},
2945 { "paddd", { MX
, EM
}, PREFIX_OPCODE
},
2946 { "ud0S", { Gv
, Ev
}, 0 },
2949 static const unsigned char onebyte_has_modrm
[256] = {
2950 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2951 /* ------------------------------- */
2952 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2953 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2954 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2955 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2956 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2957 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2958 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2959 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2960 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2961 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2962 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2963 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2964 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2965 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2966 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2967 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
2968 /* ------------------------------- */
2969 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2972 static const unsigned char twobyte_has_modrm
[256] = {
2973 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2974 /* ------------------------------- */
2975 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2976 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2977 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2978 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2979 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2980 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2981 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2982 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2983 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2984 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2985 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2986 /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2987 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2988 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2989 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2990 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 /* ff */
2991 /* ------------------------------- */
2992 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2995 static char obuf
[100];
2997 static char *mnemonicendp
;
2998 static char scratchbuf
[100];
2999 static unsigned char *start_codep
;
3000 static unsigned char *insn_codep
;
3001 static unsigned char *codep
;
3002 static unsigned char *end_codep
;
3003 static int last_lock_prefix
;
3004 static int last_repz_prefix
;
3005 static int last_repnz_prefix
;
3006 static int last_data_prefix
;
3007 static int last_addr_prefix
;
3008 static int last_rex_prefix
;
3009 static int last_seg_prefix
;
3010 static int fwait_prefix
;
3011 /* The active segment register prefix. */
3012 static int active_seg_prefix
;
3013 #define MAX_CODE_LENGTH 15
3014 /* We can up to 14 prefixes since the maximum instruction length is
3016 static int all_prefixes
[MAX_CODE_LENGTH
- 1];
3017 static disassemble_info
*the_info
;
3025 static unsigned char need_modrm
;
3035 int register_specifier
;
3042 int mask_register_specifier
;
3048 static unsigned char need_vex
;
3049 static unsigned char need_vex_reg
;
3050 static unsigned char vex_w_done
;
3058 /* If we are accessing mod/rm/reg without need_modrm set, then the
3059 values are stale. Hitting this abort likely indicates that you
3060 need to update onebyte_has_modrm or twobyte_has_modrm. */
3061 #define MODRM_CHECK if (!need_modrm) abort ()
3063 static const char **names64
;
3064 static const char **names32
;
3065 static const char **names16
;
3066 static const char **names8
;
3067 static const char **names8rex
;
3068 static const char **names_seg
;
3069 static const char *index64
;
3070 static const char *index32
;
3071 static const char **index16
;
3072 static const char **names_bnd
;
3074 static const char *intel_names64
[] = {
3075 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3076 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3078 static const char *intel_names32
[] = {
3079 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3080 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3082 static const char *intel_names16
[] = {
3083 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3084 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3086 static const char *intel_names8
[] = {
3087 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3089 static const char *intel_names8rex
[] = {
3090 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3091 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3093 static const char *intel_names_seg
[] = {
3094 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3096 static const char *intel_index64
= "riz";
3097 static const char *intel_index32
= "eiz";
3098 static const char *intel_index16
[] = {
3099 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3102 static const char *att_names64
[] = {
3103 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3104 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3106 static const char *att_names32
[] = {
3107 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3108 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3110 static const char *att_names16
[] = {
3111 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3112 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3114 static const char *att_names8
[] = {
3115 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3117 static const char *att_names8rex
[] = {
3118 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3119 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3121 static const char *att_names_seg
[] = {
3122 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3124 static const char *att_index64
= "%riz";
3125 static const char *att_index32
= "%eiz";
3126 static const char *att_index16
[] = {
3127 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3130 static const char **names_mm
;
3131 static const char *intel_names_mm
[] = {
3132 "mm0", "mm1", "mm2", "mm3",
3133 "mm4", "mm5", "mm6", "mm7"
3135 static const char *att_names_mm
[] = {
3136 "%mm0", "%mm1", "%mm2", "%mm3",
3137 "%mm4", "%mm5", "%mm6", "%mm7"
3140 static const char *intel_names_bnd
[] = {
3141 "bnd0", "bnd1", "bnd2", "bnd3"
3144 static const char *att_names_bnd
[] = {
3145 "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3148 static const char **names_xmm
;
3149 static const char *intel_names_xmm
[] = {
3150 "xmm0", "xmm1", "xmm2", "xmm3",
3151 "xmm4", "xmm5", "xmm6", "xmm7",
3152 "xmm8", "xmm9", "xmm10", "xmm11",
3153 "xmm12", "xmm13", "xmm14", "xmm15",
3154 "xmm16", "xmm17", "xmm18", "xmm19",
3155 "xmm20", "xmm21", "xmm22", "xmm23",
3156 "xmm24", "xmm25", "xmm26", "xmm27",
3157 "xmm28", "xmm29", "xmm30", "xmm31"
3159 static const char *att_names_xmm
[] = {
3160 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3161 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3162 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3163 "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3164 "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3165 "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3166 "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3167 "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3170 static const char **names_ymm
;
3171 static const char *intel_names_ymm
[] = {
3172 "ymm0", "ymm1", "ymm2", "ymm3",
3173 "ymm4", "ymm5", "ymm6", "ymm7",
3174 "ymm8", "ymm9", "ymm10", "ymm11",
3175 "ymm12", "ymm13", "ymm14", "ymm15",
3176 "ymm16", "ymm17", "ymm18", "ymm19",
3177 "ymm20", "ymm21", "ymm22", "ymm23",
3178 "ymm24", "ymm25", "ymm26", "ymm27",
3179 "ymm28", "ymm29", "ymm30", "ymm31"
3181 static const char *att_names_ymm
[] = {
3182 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3183 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3184 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3185 "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3186 "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3187 "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3188 "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3189 "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3192 static const char **names_zmm
;
3193 static const char *intel_names_zmm
[] = {
3194 "zmm0", "zmm1", "zmm2", "zmm3",
3195 "zmm4", "zmm5", "zmm6", "zmm7",
3196 "zmm8", "zmm9", "zmm10", "zmm11",
3197 "zmm12", "zmm13", "zmm14", "zmm15",
3198 "zmm16", "zmm17", "zmm18", "zmm19",
3199 "zmm20", "zmm21", "zmm22", "zmm23",
3200 "zmm24", "zmm25", "zmm26", "zmm27",
3201 "zmm28", "zmm29", "zmm30", "zmm31"
3203 static const char *att_names_zmm
[] = {
3204 "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3205 "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3206 "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3207 "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3208 "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3209 "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3210 "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3211 "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3214 static const char **names_mask
;
3215 static const char *intel_names_mask
[] = {
3216 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3218 static const char *att_names_mask
[] = {
3219 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3222 static const char *names_rounding
[] =
3230 static const struct dis386 reg_table
[][8] = {
3233 { "addA", { Ebh1
, Ib
}, 0 },
3234 { "orA", { Ebh1
, Ib
}, 0 },
3235 { "adcA", { Ebh1
, Ib
}, 0 },
3236 { "sbbA", { Ebh1
, Ib
}, 0 },
3237 { "andA", { Ebh1
, Ib
}, 0 },
3238 { "subA", { Ebh1
, Ib
}, 0 },
3239 { "xorA", { Ebh1
, Ib
}, 0 },
3240 { "cmpA", { Eb
, Ib
}, 0 },
3244 { "addQ", { Evh1
, Iv
}, 0 },
3245 { "orQ", { Evh1
, Iv
}, 0 },
3246 { "adcQ", { Evh1
, Iv
}, 0 },
3247 { "sbbQ", { Evh1
, Iv
}, 0 },
3248 { "andQ", { Evh1
, Iv
}, 0 },
3249 { "subQ", { Evh1
, Iv
}, 0 },
3250 { "xorQ", { Evh1
, Iv
}, 0 },
3251 { "cmpQ", { Ev
, Iv
}, 0 },
3255 { "addQ", { Evh1
, sIb
}, 0 },
3256 { "orQ", { Evh1
, sIb
}, 0 },
3257 { "adcQ", { Evh1
, sIb
}, 0 },
3258 { "sbbQ", { Evh1
, sIb
}, 0 },
3259 { "andQ", { Evh1
, sIb
}, 0 },
3260 { "subQ", { Evh1
, sIb
}, 0 },
3261 { "xorQ", { Evh1
, sIb
}, 0 },
3262 { "cmpQ", { Ev
, sIb
}, 0 },
3266 { "popU", { stackEv
}, 0 },
3267 { XOP_8F_TABLE (XOP_09
) },
3271 { XOP_8F_TABLE (XOP_09
) },
3275 { "rolA", { Eb
, Ib
}, 0 },
3276 { "rorA", { Eb
, Ib
}, 0 },
3277 { "rclA", { Eb
, Ib
}, 0 },
3278 { "rcrA", { Eb
, Ib
}, 0 },
3279 { "shlA", { Eb
, Ib
}, 0 },
3280 { "shrA", { Eb
, Ib
}, 0 },
3281 { "shlA", { Eb
, Ib
}, 0 },
3282 { "sarA", { Eb
, Ib
}, 0 },
3286 { "rolQ", { Ev
, Ib
}, 0 },
3287 { "rorQ", { Ev
, Ib
}, 0 },
3288 { "rclQ", { Ev
, Ib
}, 0 },
3289 { "rcrQ", { Ev
, Ib
}, 0 },
3290 { "shlQ", { Ev
, Ib
}, 0 },
3291 { "shrQ", { Ev
, Ib
}, 0 },
3292 { "shlQ", { Ev
, Ib
}, 0 },
3293 { "sarQ", { Ev
, Ib
}, 0 },
3297 { "movA", { Ebh3
, Ib
}, 0 },
3304 { MOD_TABLE (MOD_C6_REG_7
) },
3308 { "movQ", { Evh3
, Iv
}, 0 },
3315 { MOD_TABLE (MOD_C7_REG_7
) },
3319 { "rolA", { Eb
, I1
}, 0 },
3320 { "rorA", { Eb
, I1
}, 0 },
3321 { "rclA", { Eb
, I1
}, 0 },
3322 { "rcrA", { Eb
, I1
}, 0 },
3323 { "shlA", { Eb
, I1
}, 0 },
3324 { "shrA", { Eb
, I1
}, 0 },
3325 { "shlA", { Eb
, I1
}, 0 },
3326 { "sarA", { Eb
, I1
}, 0 },
3330 { "rolQ", { Ev
, I1
}, 0 },
3331 { "rorQ", { Ev
, I1
}, 0 },
3332 { "rclQ", { Ev
, I1
}, 0 },
3333 { "rcrQ", { Ev
, I1
}, 0 },
3334 { "shlQ", { Ev
, I1
}, 0 },
3335 { "shrQ", { Ev
, I1
}, 0 },
3336 { "shlQ", { Ev
, I1
}, 0 },
3337 { "sarQ", { Ev
, I1
}, 0 },
3341 { "rolA", { Eb
, CL
}, 0 },
3342 { "rorA", { Eb
, CL
}, 0 },
3343 { "rclA", { Eb
, CL
}, 0 },
3344 { "rcrA", { Eb
, CL
}, 0 },
3345 { "shlA", { Eb
, CL
}, 0 },
3346 { "shrA", { Eb
, CL
}, 0 },
3347 { "shlA", { Eb
, CL
}, 0 },
3348 { "sarA", { Eb
, CL
}, 0 },
3352 { "rolQ", { Ev
, CL
}, 0 },
3353 { "rorQ", { Ev
, CL
}, 0 },
3354 { "rclQ", { Ev
, CL
}, 0 },
3355 { "rcrQ", { Ev
, CL
}, 0 },
3356 { "shlQ", { Ev
, CL
}, 0 },
3357 { "shrQ", { Ev
, CL
}, 0 },
3358 { "shlQ", { Ev
, CL
}, 0 },
3359 { "sarQ", { Ev
, CL
}, 0 },
3363 { "testA", { Eb
, Ib
}, 0 },
3364 { "testA", { Eb
, Ib
}, 0 },
3365 { "notA", { Ebh1
}, 0 },
3366 { "negA", { Ebh1
}, 0 },
3367 { "mulA", { Eb
}, 0 }, /* Don't print the implicit %al register, */
3368 { "imulA", { Eb
}, 0 }, /* to distinguish these opcodes from other */
3369 { "divA", { Eb
}, 0 }, /* mul/imul opcodes. Do the same for div */
3370 { "idivA", { Eb
}, 0 }, /* and idiv for consistency. */
3374 { "testQ", { Ev
, Iv
}, 0 },
3375 { "testQ", { Ev
, Iv
}, 0 },
3376 { "notQ", { Evh1
}, 0 },
3377 { "negQ", { Evh1
}, 0 },
3378 { "mulQ", { Ev
}, 0 }, /* Don't print the implicit register. */
3379 { "imulQ", { Ev
}, 0 },
3380 { "divQ", { Ev
}, 0 },
3381 { "idivQ", { Ev
}, 0 },
3385 { "incA", { Ebh1
}, 0 },
3386 { "decA", { Ebh1
}, 0 },
3390 { "incQ", { Evh1
}, 0 },
3391 { "decQ", { Evh1
}, 0 },
3392 { "call{&|}", { NOTRACK
, indirEv
, BND
}, 0 },
3393 { MOD_TABLE (MOD_FF_REG_3
) },
3394 { "jmp{&|}", { NOTRACK
, indirEv
, BND
}, 0 },
3395 { MOD_TABLE (MOD_FF_REG_5
) },
3396 { "pushU", { stackEv
}, 0 },
3401 { "sldtD", { Sv
}, 0 },
3402 { "strD", { Sv
}, 0 },
3403 { "lldt", { Ew
}, 0 },
3404 { "ltr", { Ew
}, 0 },
3405 { "verr", { Ew
}, 0 },
3406 { "verw", { Ew
}, 0 },
3412 { MOD_TABLE (MOD_0F01_REG_0
) },
3413 { MOD_TABLE (MOD_0F01_REG_1
) },
3414 { MOD_TABLE (MOD_0F01_REG_2
) },
3415 { MOD_TABLE (MOD_0F01_REG_3
) },
3416 { "smswD", { Sv
}, 0 },
3417 { MOD_TABLE (MOD_0F01_REG_5
) },
3418 { "lmsw", { Ew
}, 0 },
3419 { MOD_TABLE (MOD_0F01_REG_7
) },
3423 { "prefetch", { Mb
}, 0 },
3424 { "prefetchw", { Mb
}, 0 },
3425 { "prefetchwt1", { Mb
}, 0 },
3426 { "prefetch", { Mb
}, 0 },
3427 { "prefetch", { Mb
}, 0 },
3428 { "prefetch", { Mb
}, 0 },
3429 { "prefetch", { Mb
}, 0 },
3430 { "prefetch", { Mb
}, 0 },
3434 { MOD_TABLE (MOD_0F18_REG_0
) },
3435 { MOD_TABLE (MOD_0F18_REG_1
) },
3436 { MOD_TABLE (MOD_0F18_REG_2
) },
3437 { MOD_TABLE (MOD_0F18_REG_3
) },
3438 { MOD_TABLE (MOD_0F18_REG_4
) },
3439 { MOD_TABLE (MOD_0F18_REG_5
) },
3440 { MOD_TABLE (MOD_0F18_REG_6
) },
3441 { MOD_TABLE (MOD_0F18_REG_7
) },
3443 /* REG_0F1C_P_0_MOD_0 */
3445 { "cldemote", { Mb
}, 0 },
3446 { "nopQ", { Ev
}, 0 },
3447 { "nopQ", { Ev
}, 0 },
3448 { "nopQ", { Ev
}, 0 },
3449 { "nopQ", { Ev
}, 0 },
3450 { "nopQ", { Ev
}, 0 },
3451 { "nopQ", { Ev
}, 0 },
3452 { "nopQ", { Ev
}, 0 },
3454 /* REG_0F1E_P_1_MOD_3 */
3456 { "nopQ", { Ev
}, 0 },
3457 { "rdsspK", { Rdq
}, PREFIX_OPCODE
},
3458 { "nopQ", { Ev
}, 0 },
3459 { "nopQ", { Ev
}, 0 },
3460 { "nopQ", { Ev
}, 0 },
3461 { "nopQ", { Ev
}, 0 },
3462 { "nopQ", { Ev
}, 0 },
3463 { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7
) },
3469 { MOD_TABLE (MOD_0F71_REG_2
) },
3471 { MOD_TABLE (MOD_0F71_REG_4
) },
3473 { MOD_TABLE (MOD_0F71_REG_6
) },
3479 { MOD_TABLE (MOD_0F72_REG_2
) },
3481 { MOD_TABLE (MOD_0F72_REG_4
) },
3483 { MOD_TABLE (MOD_0F72_REG_6
) },
3489 { MOD_TABLE (MOD_0F73_REG_2
) },
3490 { MOD_TABLE (MOD_0F73_REG_3
) },
3493 { MOD_TABLE (MOD_0F73_REG_6
) },
3494 { MOD_TABLE (MOD_0F73_REG_7
) },
3498 { "montmul", { { OP_0f07
, 0 } }, 0 },
3499 { "xsha1", { { OP_0f07
, 0 } }, 0 },
3500 { "xsha256", { { OP_0f07
, 0 } }, 0 },
3504 { "xstore-rng", { { OP_0f07
, 0 } }, 0 },
3505 { "xcrypt-ecb", { { OP_0f07
, 0 } }, 0 },
3506 { "xcrypt-cbc", { { OP_0f07
, 0 } }, 0 },
3507 { "xcrypt-ctr", { { OP_0f07
, 0 } }, 0 },
3508 { "xcrypt-cfb", { { OP_0f07
, 0 } }, 0 },
3509 { "xcrypt-ofb", { { OP_0f07
, 0 } }, 0 },
3513 { MOD_TABLE (MOD_0FAE_REG_0
) },
3514 { MOD_TABLE (MOD_0FAE_REG_1
) },
3515 { MOD_TABLE (MOD_0FAE_REG_2
) },
3516 { MOD_TABLE (MOD_0FAE_REG_3
) },
3517 { MOD_TABLE (MOD_0FAE_REG_4
) },
3518 { MOD_TABLE (MOD_0FAE_REG_5
) },
3519 { MOD_TABLE (MOD_0FAE_REG_6
) },
3520 { MOD_TABLE (MOD_0FAE_REG_7
) },
3528 { "btQ", { Ev
, Ib
}, 0 },
3529 { "btsQ", { Evh1
, Ib
}, 0 },
3530 { "btrQ", { Evh1
, Ib
}, 0 },
3531 { "btcQ", { Evh1
, Ib
}, 0 },
3536 { "cmpxchg8b", { { CMPXCHG8B_Fixup
, q_mode
} }, 0 },
3538 { MOD_TABLE (MOD_0FC7_REG_3
) },
3539 { MOD_TABLE (MOD_0FC7_REG_4
) },
3540 { MOD_TABLE (MOD_0FC7_REG_5
) },
3541 { MOD_TABLE (MOD_0FC7_REG_6
) },
3542 { MOD_TABLE (MOD_0FC7_REG_7
) },
3548 { MOD_TABLE (MOD_VEX_0F71_REG_2
) },
3550 { MOD_TABLE (MOD_VEX_0F71_REG_4
) },
3552 { MOD_TABLE (MOD_VEX_0F71_REG_6
) },
3558 { MOD_TABLE (MOD_VEX_0F72_REG_2
) },
3560 { MOD_TABLE (MOD_VEX_0F72_REG_4
) },
3562 { MOD_TABLE (MOD_VEX_0F72_REG_6
) },
3568 { MOD_TABLE (MOD_VEX_0F73_REG_2
) },
3569 { MOD_TABLE (MOD_VEX_0F73_REG_3
) },
3572 { MOD_TABLE (MOD_VEX_0F73_REG_6
) },
3573 { MOD_TABLE (MOD_VEX_0F73_REG_7
) },
3579 { MOD_TABLE (MOD_VEX_0FAE_REG_2
) },
3580 { MOD_TABLE (MOD_VEX_0FAE_REG_3
) },
3582 /* REG_VEX_0F38F3 */
3585 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1
) },
3586 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2
) },
3587 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3
) },
3591 { "llwpcb", { { OP_LWPCB_E
, 0 } }, 0 },
3592 { "slwpcb", { { OP_LWPCB_E
, 0 } }, 0 },
3596 { "lwpins", { { OP_LWP_E
, 0 }, Ed
, Id
}, 0 },
3597 { "lwpval", { { OP_LWP_E
, 0 }, Ed
, Id
}, 0 },
3599 /* REG_XOP_TBM_01 */
3602 { "blcfill", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3603 { "blsfill", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3604 { "blcs", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3605 { "tzmsk", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3606 { "blcic", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3607 { "blsic", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3608 { "t1mskc", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3610 /* REG_XOP_TBM_02 */
3613 { "blcmsk", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3618 { "blci", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3621 #include "i386-dis-evex-reg.h"
3624 static const struct dis386 prefix_table
[][4] = {
3627 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} }, 0 },
3628 { "pause", { XX
}, 0 },
3629 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} }, 0 },
3630 { NULL
, { { NULL
, 0 } }, PREFIX_IGNORED
}
3633 /* PREFIX_0F01_REG_5_MOD_0 */
3636 { "rstorssp", { Mq
}, PREFIX_OPCODE
},
3639 /* PREFIX_0F01_REG_5_MOD_3_RM_0 */
3642 { "setssbsy", { Skip_MODRM
}, PREFIX_OPCODE
},
3645 /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
3648 { "saveprevssp", { Skip_MODRM
}, PREFIX_OPCODE
},
3651 /* PREFIX_0F01_REG_7_MOD_3_RM_2 */
3653 { "monitorx", { { OP_Monitor
, 0 } }, 0 },
3654 { "mcommit", { Skip_MODRM
}, 0 },
3657 /* PREFIX_0F01_REG_7_MOD_3_RM_3 */
3659 { "mwaitx", { { OP_Mwait
, eBX_reg
} }, 0 },
3664 { "wbinvd", { XX
}, 0 },
3665 { "wbnoinvd", { XX
}, 0 },
3670 { "movups", { XM
, EXx
}, PREFIX_OPCODE
},
3671 { "movss", { XM
, EXd
}, PREFIX_OPCODE
},
3672 { "movupd", { XM
, EXx
}, PREFIX_OPCODE
},
3673 { "movsd", { XM
, EXq
}, PREFIX_OPCODE
},
3678 { "movups", { EXxS
, XM
}, PREFIX_OPCODE
},
3679 { "movss", { EXdS
, XM
}, PREFIX_OPCODE
},
3680 { "movupd", { EXxS
, XM
}, PREFIX_OPCODE
},
3681 { "movsd", { EXqS
, XM
}, PREFIX_OPCODE
},
3686 { MOD_TABLE (MOD_0F12_PREFIX_0
) },
3687 { "movsldup", { XM
, EXx
}, PREFIX_OPCODE
},
3688 { "movlpd", { XM
, EXq
}, PREFIX_OPCODE
},
3689 { "movddup", { XM
, EXq
}, PREFIX_OPCODE
},
3694 { MOD_TABLE (MOD_0F16_PREFIX_0
) },
3695 { "movshdup", { XM
, EXx
}, PREFIX_OPCODE
},
3696 { "movhpd", { XM
, EXq
}, PREFIX_OPCODE
},
3701 { MOD_TABLE (MOD_0F1A_PREFIX_0
) },
3702 { "bndcl", { Gbnd
, Ev_bnd
}, 0 },
3703 { "bndmov", { Gbnd
, Ebnd
}, 0 },
3704 { "bndcu", { Gbnd
, Ev_bnd
}, 0 },
3709 { MOD_TABLE (MOD_0F1B_PREFIX_0
) },
3710 { MOD_TABLE (MOD_0F1B_PREFIX_1
) },
3711 { "bndmov", { EbndS
, Gbnd
}, 0 },
3712 { "bndcn", { Gbnd
, Ev_bnd
}, 0 },
3717 { MOD_TABLE (MOD_0F1C_PREFIX_0
) },
3718 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3719 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3720 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3725 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3726 { MOD_TABLE (MOD_0F1E_PREFIX_1
) },
3727 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3728 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3733 { "cvtpi2ps", { XM
, EMCq
}, PREFIX_OPCODE
},
3734 { "cvtsi2ss%LQ", { XM
, Edq
}, PREFIX_OPCODE
},
3735 { "cvtpi2pd", { XM
, EMCq
}, PREFIX_OPCODE
},
3736 { "cvtsi2sd%LQ", { XM
, Edq
}, 0 },
3741 { MOD_TABLE (MOD_0F2B_PREFIX_0
) },
3742 { MOD_TABLE (MOD_0F2B_PREFIX_1
) },
3743 { MOD_TABLE (MOD_0F2B_PREFIX_2
) },
3744 { MOD_TABLE (MOD_0F2B_PREFIX_3
) },
3749 { "cvttps2pi", { MXC
, EXq
}, PREFIX_OPCODE
},
3750 { "cvttss2si", { Gdq
, EXd
}, PREFIX_OPCODE
},
3751 { "cvttpd2pi", { MXC
, EXx
}, PREFIX_OPCODE
},
3752 { "cvttsd2si", { Gdq
, EXq
}, PREFIX_OPCODE
},
3757 { "cvtps2pi", { MXC
, EXq
}, PREFIX_OPCODE
},
3758 { "cvtss2si", { Gdq
, EXd
}, PREFIX_OPCODE
},
3759 { "cvtpd2pi", { MXC
, EXx
}, PREFIX_OPCODE
},
3760 { "cvtsd2si", { Gdq
, EXq
}, PREFIX_OPCODE
},
3765 { "ucomiss",{ XM
, EXd
}, 0 },
3767 { "ucomisd",{ XM
, EXq
}, 0 },
3772 { "comiss", { XM
, EXd
}, 0 },
3774 { "comisd", { XM
, EXq
}, 0 },
3779 { "sqrtps", { XM
, EXx
}, PREFIX_OPCODE
},
3780 { "sqrtss", { XM
, EXd
}, PREFIX_OPCODE
},
3781 { "sqrtpd", { XM
, EXx
}, PREFIX_OPCODE
},
3782 { "sqrtsd", { XM
, EXq
}, PREFIX_OPCODE
},
3787 { "rsqrtps",{ XM
, EXx
}, PREFIX_OPCODE
},
3788 { "rsqrtss",{ XM
, EXd
}, PREFIX_OPCODE
},
3793 { "rcpps", { XM
, EXx
}, PREFIX_OPCODE
},
3794 { "rcpss", { XM
, EXd
}, PREFIX_OPCODE
},
3799 { "addps", { XM
, EXx
}, PREFIX_OPCODE
},
3800 { "addss", { XM
, EXd
}, PREFIX_OPCODE
},
3801 { "addpd", { XM
, EXx
}, PREFIX_OPCODE
},
3802 { "addsd", { XM
, EXq
}, PREFIX_OPCODE
},
3807 { "mulps", { XM
, EXx
}, PREFIX_OPCODE
},
3808 { "mulss", { XM
, EXd
}, PREFIX_OPCODE
},
3809 { "mulpd", { XM
, EXx
}, PREFIX_OPCODE
},
3810 { "mulsd", { XM
, EXq
}, PREFIX_OPCODE
},
3815 { "cvtps2pd", { XM
, EXq
}, PREFIX_OPCODE
},
3816 { "cvtss2sd", { XM
, EXd
}, PREFIX_OPCODE
},
3817 { "cvtpd2ps", { XM
, EXx
}, PREFIX_OPCODE
},
3818 { "cvtsd2ss", { XM
, EXq
}, PREFIX_OPCODE
},
3823 { "cvtdq2ps", { XM
, EXx
}, PREFIX_OPCODE
},
3824 { "cvttps2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3825 { "cvtps2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3830 { "subps", { XM
, EXx
}, PREFIX_OPCODE
},
3831 { "subss", { XM
, EXd
}, PREFIX_OPCODE
},
3832 { "subpd", { XM
, EXx
}, PREFIX_OPCODE
},
3833 { "subsd", { XM
, EXq
}, PREFIX_OPCODE
},
3838 { "minps", { XM
, EXx
}, PREFIX_OPCODE
},
3839 { "minss", { XM
, EXd
}, PREFIX_OPCODE
},
3840 { "minpd", { XM
, EXx
}, PREFIX_OPCODE
},
3841 { "minsd", { XM
, EXq
}, PREFIX_OPCODE
},
3846 { "divps", { XM
, EXx
}, PREFIX_OPCODE
},
3847 { "divss", { XM
, EXd
}, PREFIX_OPCODE
},
3848 { "divpd", { XM
, EXx
}, PREFIX_OPCODE
},
3849 { "divsd", { XM
, EXq
}, PREFIX_OPCODE
},
3854 { "maxps", { XM
, EXx
}, PREFIX_OPCODE
},
3855 { "maxss", { XM
, EXd
}, PREFIX_OPCODE
},
3856 { "maxpd", { XM
, EXx
}, PREFIX_OPCODE
},
3857 { "maxsd", { XM
, EXq
}, PREFIX_OPCODE
},
3862 { "punpcklbw",{ MX
, EMd
}, PREFIX_OPCODE
},
3864 { "punpcklbw",{ MX
, EMx
}, PREFIX_OPCODE
},
3869 { "punpcklwd",{ MX
, EMd
}, PREFIX_OPCODE
},
3871 { "punpcklwd",{ MX
, EMx
}, PREFIX_OPCODE
},
3876 { "punpckldq",{ MX
, EMd
}, PREFIX_OPCODE
},
3878 { "punpckldq",{ MX
, EMx
}, PREFIX_OPCODE
},
3885 { "punpcklqdq", { XM
, EXx
}, PREFIX_OPCODE
},
3892 { "punpckhqdq", { XM
, EXx
}, PREFIX_OPCODE
},
3897 { "movq", { MX
, EM
}, PREFIX_OPCODE
},
3898 { "movdqu", { XM
, EXx
}, PREFIX_OPCODE
},
3899 { "movdqa", { XM
, EXx
}, PREFIX_OPCODE
},
3904 { "pshufw", { MX
, EM
, Ib
}, PREFIX_OPCODE
},
3905 { "pshufhw",{ XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3906 { "pshufd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3907 { "pshuflw",{ XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3910 /* PREFIX_0F73_REG_3 */
3914 { "psrldq", { XS
, Ib
}, 0 },
3917 /* PREFIX_0F73_REG_7 */
3921 { "pslldq", { XS
, Ib
}, 0 },
3926 {"vmread", { Em
, Gm
}, 0 },
3928 {"extrq", { XS
, Ib
, Ib
}, 0 },
3929 {"insertq", { XM
, XS
, Ib
, Ib
}, 0 },
3934 {"vmwrite", { Gm
, Em
}, 0 },
3936 {"extrq", { XM
, XS
}, 0 },
3937 {"insertq", { XM
, XS
}, 0 },
3944 { "haddpd", { XM
, EXx
}, PREFIX_OPCODE
},
3945 { "haddps", { XM
, EXx
}, PREFIX_OPCODE
},
3952 { "hsubpd", { XM
, EXx
}, PREFIX_OPCODE
},
3953 { "hsubps", { XM
, EXx
}, PREFIX_OPCODE
},
3958 { "movK", { Edq
, MX
}, PREFIX_OPCODE
},
3959 { "movq", { XM
, EXq
}, PREFIX_OPCODE
},
3960 { "movK", { Edq
, XM
}, PREFIX_OPCODE
},
3965 { "movq", { EMS
, MX
}, PREFIX_OPCODE
},
3966 { "movdqu", { EXxS
, XM
}, PREFIX_OPCODE
},
3967 { "movdqa", { EXxS
, XM
}, PREFIX_OPCODE
},
3970 /* PREFIX_0FAE_REG_0_MOD_3 */
3973 { "rdfsbase", { Ev
}, 0 },
3976 /* PREFIX_0FAE_REG_1_MOD_3 */
3979 { "rdgsbase", { Ev
}, 0 },
3982 /* PREFIX_0FAE_REG_2_MOD_3 */
3985 { "wrfsbase", { Ev
}, 0 },
3988 /* PREFIX_0FAE_REG_3_MOD_3 */
3991 { "wrgsbase", { Ev
}, 0 },
3994 /* PREFIX_0FAE_REG_4_MOD_0 */
3996 { "xsave", { FXSAVE
}, 0 },
3997 { "ptwrite%LQ", { Edq
}, 0 },
4000 /* PREFIX_0FAE_REG_4_MOD_3 */
4003 { "ptwrite%LQ", { Edq
}, 0 },
4006 /* PREFIX_0FAE_REG_5_MOD_0 */
4008 { "xrstor", { FXSAVE
}, PREFIX_OPCODE
},
4011 /* PREFIX_0FAE_REG_5_MOD_3 */
4013 { "lfence", { Skip_MODRM
}, 0 },
4014 { "incsspK", { Rdq
}, PREFIX_OPCODE
},
4017 /* PREFIX_0FAE_REG_6_MOD_0 */
4019 { "xsaveopt", { FXSAVE
}, PREFIX_OPCODE
},
4020 { "clrssbsy", { Mq
}, PREFIX_OPCODE
},
4021 { "clwb", { Mb
}, PREFIX_OPCODE
},
4024 /* PREFIX_0FAE_REG_6_MOD_3 */
4026 { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0
) },
4027 { "umonitor", { Eva
}, PREFIX_OPCODE
},
4028 { "tpause", { Edq
}, PREFIX_OPCODE
},
4029 { "umwait", { Edq
}, PREFIX_OPCODE
},
4032 /* PREFIX_0FAE_REG_7_MOD_0 */
4034 { "clflush", { Mb
}, 0 },
4036 { "clflushopt", { Mb
}, 0 },
4042 { "popcntS", { Gv
, Ev
}, 0 },
4047 { "bsfS", { Gv
, Ev
}, 0 },
4048 { "tzcntS", { Gv
, Ev
}, 0 },
4049 { "bsfS", { Gv
, Ev
}, 0 },
4054 { "bsrS", { Gv
, Ev
}, 0 },
4055 { "lzcntS", { Gv
, Ev
}, 0 },
4056 { "bsrS", { Gv
, Ev
}, 0 },
4061 { "cmpps", { XM
, EXx
, CMP
}, PREFIX_OPCODE
},
4062 { "cmpss", { XM
, EXd
, CMP
}, PREFIX_OPCODE
},
4063 { "cmppd", { XM
, EXx
, CMP
}, PREFIX_OPCODE
},
4064 { "cmpsd", { XM
, EXq
, CMP
}, PREFIX_OPCODE
},
4067 /* PREFIX_0FC3_MOD_0 */
4069 { "movntiS", { Edq
, Gdq
}, PREFIX_OPCODE
},
4072 /* PREFIX_0FC7_REG_6_MOD_0 */
4074 { "vmptrld",{ Mq
}, 0 },
4075 { "vmxon", { Mq
}, 0 },
4076 { "vmclear",{ Mq
}, 0 },
4079 /* PREFIX_0FC7_REG_6_MOD_3 */
4081 { "rdrand", { Ev
}, 0 },
4083 { "rdrand", { Ev
}, 0 }
4086 /* PREFIX_0FC7_REG_7_MOD_3 */
4088 { "rdseed", { Ev
}, 0 },
4089 { "rdpid", { Em
}, 0 },
4090 { "rdseed", { Ev
}, 0 },
4097 { "addsubpd", { XM
, EXx
}, 0 },
4098 { "addsubps", { XM
, EXx
}, 0 },
4104 { "movq2dq",{ XM
, MS
}, 0 },
4105 { "movq", { EXqS
, XM
}, 0 },
4106 { "movdq2q",{ MX
, XS
}, 0 },
4112 { "cvtdq2pd", { XM
, EXq
}, PREFIX_OPCODE
},
4113 { "cvttpd2dq", { XM
, EXx
}, PREFIX_OPCODE
},
4114 { "cvtpd2dq", { XM
, EXx
}, PREFIX_OPCODE
},
4119 { "movntq", { Mq
, MX
}, PREFIX_OPCODE
},
4121 { MOD_TABLE (MOD_0FE7_PREFIX_2
) },
4129 { MOD_TABLE (MOD_0FF0_PREFIX_3
) },
4134 { "maskmovq", { MX
, MS
}, PREFIX_OPCODE
},
4136 { "maskmovdqu", { XM
, XS
}, PREFIX_OPCODE
},
4143 { "pblendvb", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4150 { "blendvps", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4157 { "blendvpd", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4164 { "ptest", { XM
, EXx
}, PREFIX_OPCODE
},
4171 { "pmovsxbw", { XM
, EXq
}, PREFIX_OPCODE
},
4178 { "pmovsxbd", { XM
, EXd
}, PREFIX_OPCODE
},
4185 { "pmovsxbq", { XM
, EXw
}, PREFIX_OPCODE
},
4192 { "pmovsxwd", { XM
, EXq
}, PREFIX_OPCODE
},
4199 { "pmovsxwq", { XM
, EXd
}, PREFIX_OPCODE
},
4206 { "pmovsxdq", { XM
, EXq
}, PREFIX_OPCODE
},
4213 { "pmuldq", { XM
, EXx
}, PREFIX_OPCODE
},
4220 { "pcmpeqq", { XM
, EXx
}, PREFIX_OPCODE
},
4227 { MOD_TABLE (MOD_0F382A_PREFIX_2
) },
4234 { "packusdw", { XM
, EXx
}, PREFIX_OPCODE
},
4241 { "pmovzxbw", { XM
, EXq
}, PREFIX_OPCODE
},
4248 { "pmovzxbd", { XM
, EXd
}, PREFIX_OPCODE
},
4255 { "pmovzxbq", { XM
, EXw
}, PREFIX_OPCODE
},
4262 { "pmovzxwd", { XM
, EXq
}, PREFIX_OPCODE
},
4269 { "pmovzxwq", { XM
, EXd
}, PREFIX_OPCODE
},
4276 { "pmovzxdq", { XM
, EXq
}, PREFIX_OPCODE
},
4283 { "pcmpgtq", { XM
, EXx
}, PREFIX_OPCODE
},
4290 { "pminsb", { XM
, EXx
}, PREFIX_OPCODE
},
4297 { "pminsd", { XM
, EXx
}, PREFIX_OPCODE
},
4304 { "pminuw", { XM
, EXx
}, PREFIX_OPCODE
},
4311 { "pminud", { XM
, EXx
}, PREFIX_OPCODE
},
4318 { "pmaxsb", { XM
, EXx
}, PREFIX_OPCODE
},
4325 { "pmaxsd", { XM
, EXx
}, PREFIX_OPCODE
},
4332 { "pmaxuw", { XM
, EXx
}, PREFIX_OPCODE
},
4339 { "pmaxud", { XM
, EXx
}, PREFIX_OPCODE
},
4346 { "pmulld", { XM
, EXx
}, PREFIX_OPCODE
},
4353 { "phminposuw", { XM
, EXx
}, PREFIX_OPCODE
},
4360 { "invept", { Gm
, Mo
}, PREFIX_OPCODE
},
4367 { "invvpid", { Gm
, Mo
}, PREFIX_OPCODE
},
4374 { "invpcid", { Gm
, M
}, PREFIX_OPCODE
},
4379 { "sha1nexte", { XM
, EXxmm
}, PREFIX_OPCODE
},
4384 { "sha1msg1", { XM
, EXxmm
}, PREFIX_OPCODE
},
4389 { "sha1msg2", { XM
, EXxmm
}, PREFIX_OPCODE
},
4394 { "sha256rnds2", { XM
, EXxmm
, XMM0
}, PREFIX_OPCODE
},
4399 { "sha256msg1", { XM
, EXxmm
}, PREFIX_OPCODE
},
4404 { "sha256msg2", { XM
, EXxmm
}, PREFIX_OPCODE
},
4411 { "gf2p8mulb", { XM
, EXxmm
}, PREFIX_OPCODE
},
4418 { "aesimc", { XM
, EXx
}, PREFIX_OPCODE
},
4425 { "aesenc", { XM
, EXx
}, PREFIX_OPCODE
},
4432 { "aesenclast", { XM
, EXx
}, PREFIX_OPCODE
},
4439 { "aesdec", { XM
, EXx
}, PREFIX_OPCODE
},
4446 { "aesdeclast", { XM
, EXx
}, PREFIX_OPCODE
},
4451 { "movbeS", { Gv
, { MOVBE_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4453 { "movbeS", { Gv
, { MOVBE_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4454 { "crc32", { Gdq
, { CRC32_Fixup
, b_mode
} }, PREFIX_OPCODE
},
4459 { "movbeS", { { MOVBE_Fixup
, v_mode
}, Gv
}, PREFIX_OPCODE
},
4461 { "movbeS", { { MOVBE_Fixup
, v_mode
}, Gv
}, PREFIX_OPCODE
},
4462 { "crc32", { Gdq
, { CRC32_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4469 { MOD_TABLE (MOD_0F38F5_PREFIX_2
) },
4474 { MOD_TABLE (MOD_0F38F6_PREFIX_0
) },
4475 { "adoxS", { Gdq
, Edq
}, PREFIX_OPCODE
},
4476 { "adcxS", { Gdq
, Edq
}, PREFIX_OPCODE
},
4483 { MOD_TABLE (MOD_0F38F8_PREFIX_1
) },
4484 { MOD_TABLE (MOD_0F38F8_PREFIX_2
) },
4485 { MOD_TABLE (MOD_0F38F8_PREFIX_3
) },
4490 { MOD_TABLE (MOD_0F38F9_PREFIX_0
) },
4497 { "roundps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4504 { "roundpd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4511 { "roundss", { XM
, EXd
, Ib
}, PREFIX_OPCODE
},
4518 { "roundsd", { XM
, EXq
, Ib
}, PREFIX_OPCODE
},
4525 { "blendps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4532 { "blendpd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4539 { "pblendw", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4546 { "pextrb", { Edqb
, XM
, Ib
}, PREFIX_OPCODE
},
4553 { "pextrw", { Edqw
, XM
, Ib
}, PREFIX_OPCODE
},
4560 { "pextrK", { Edq
, XM
, Ib
}, PREFIX_OPCODE
},
4567 { "extractps", { Edqd
, XM
, Ib
}, PREFIX_OPCODE
},
4574 { "pinsrb", { XM
, Edqb
, Ib
}, PREFIX_OPCODE
},
4581 { "insertps", { XM
, EXd
, Ib
}, PREFIX_OPCODE
},
4588 { "pinsrK", { XM
, Edq
, Ib
}, PREFIX_OPCODE
},
4595 { "dpps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4602 { "dppd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4609 { "mpsadbw", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4616 { "pclmulqdq", { XM
, EXx
, PCLMUL
}, PREFIX_OPCODE
},
4623 { "pcmpestrm", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, PREFIX_OPCODE
},
4630 { "pcmpestri", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, PREFIX_OPCODE
},
4637 { "pcmpistrm", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4644 { "pcmpistri", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4649 { "sha1rnds4", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4656 { "gf2p8affineqb", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4663 { "gf2p8affineinvqb", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4670 { "aeskeygenassist", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4673 /* PREFIX_VEX_0F10 */
4675 { "vmovups", { XM
, EXx
}, 0 },
4676 { "vmovss", { XMVexScalar
, VexScalar
, EXdScalar
}, 0 },
4677 { "vmovupd", { XM
, EXx
}, 0 },
4678 { "vmovsd", { XMVexScalar
, VexScalar
, EXqScalar
}, 0 },
4681 /* PREFIX_VEX_0F11 */
4683 { "vmovups", { EXxS
, XM
}, 0 },
4684 { "vmovss", { EXdVexScalarS
, VexScalar
, XMScalar
}, 0 },
4685 { "vmovupd", { EXxS
, XM
}, 0 },
4686 { "vmovsd", { EXqVexScalarS
, VexScalar
, XMScalar
}, 0 },
4689 /* PREFIX_VEX_0F12 */
4691 { MOD_TABLE (MOD_VEX_0F12_PREFIX_0
) },
4692 { "vmovsldup", { XM
, EXx
}, 0 },
4693 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2
) },
4694 { "vmovddup", { XM
, EXymmq
}, 0 },
4697 /* PREFIX_VEX_0F16 */
4699 { MOD_TABLE (MOD_VEX_0F16_PREFIX_0
) },
4700 { "vmovshdup", { XM
, EXx
}, 0 },
4701 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2
) },
4704 /* PREFIX_VEX_0F2A */
4707 { "vcvtsi2ss%LQ", { XMScalar
, VexScalar
, Edq
}, 0 },
4709 { "vcvtsi2sd%LQ", { XMScalar
, VexScalar
, Edq
}, 0 },
4712 /* PREFIX_VEX_0F2C */
4715 { "vcvttss2si", { Gdq
, EXdScalar
}, 0 },
4717 { "vcvttsd2si", { Gdq
, EXqScalar
}, 0 },
4720 /* PREFIX_VEX_0F2D */
4723 { "vcvtss2si", { Gdq
, EXdScalar
}, 0 },
4725 { "vcvtsd2si", { Gdq
, EXqScalar
}, 0 },
4728 /* PREFIX_VEX_0F2E */
4730 { "vucomiss", { XMScalar
, EXdScalar
}, 0 },
4732 { "vucomisd", { XMScalar
, EXqScalar
}, 0 },
4735 /* PREFIX_VEX_0F2F */
4737 { "vcomiss", { XMScalar
, EXdScalar
}, 0 },
4739 { "vcomisd", { XMScalar
, EXqScalar
}, 0 },
4742 /* PREFIX_VEX_0F41 */
4744 { VEX_LEN_TABLE (VEX_LEN_0F41_P_0
) },
4746 { VEX_LEN_TABLE (VEX_LEN_0F41_P_2
) },
4749 /* PREFIX_VEX_0F42 */
4751 { VEX_LEN_TABLE (VEX_LEN_0F42_P_0
) },
4753 { VEX_LEN_TABLE (VEX_LEN_0F42_P_2
) },
4756 /* PREFIX_VEX_0F44 */
4758 { VEX_LEN_TABLE (VEX_LEN_0F44_P_0
) },
4760 { VEX_LEN_TABLE (VEX_LEN_0F44_P_2
) },
4763 /* PREFIX_VEX_0F45 */
4765 { VEX_LEN_TABLE (VEX_LEN_0F45_P_0
) },
4767 { VEX_LEN_TABLE (VEX_LEN_0F45_P_2
) },
4770 /* PREFIX_VEX_0F46 */
4772 { VEX_LEN_TABLE (VEX_LEN_0F46_P_0
) },
4774 { VEX_LEN_TABLE (VEX_LEN_0F46_P_2
) },
4777 /* PREFIX_VEX_0F47 */
4779 { VEX_LEN_TABLE (VEX_LEN_0F47_P_0
) },
4781 { VEX_LEN_TABLE (VEX_LEN_0F47_P_2
) },
4784 /* PREFIX_VEX_0F4A */
4786 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0
) },
4788 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2
) },
4791 /* PREFIX_VEX_0F4B */
4793 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0
) },
4795 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2
) },
4798 /* PREFIX_VEX_0F51 */
4800 { "vsqrtps", { XM
, EXx
}, 0 },
4801 { "vsqrtss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4802 { "vsqrtpd", { XM
, EXx
}, 0 },
4803 { "vsqrtsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4806 /* PREFIX_VEX_0F52 */
4808 { "vrsqrtps", { XM
, EXx
}, 0 },
4809 { "vrsqrtss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4812 /* PREFIX_VEX_0F53 */
4814 { "vrcpps", { XM
, EXx
}, 0 },
4815 { "vrcpss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4818 /* PREFIX_VEX_0F58 */
4820 { "vaddps", { XM
, Vex
, EXx
}, 0 },
4821 { "vaddss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4822 { "vaddpd", { XM
, Vex
, EXx
}, 0 },
4823 { "vaddsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4826 /* PREFIX_VEX_0F59 */
4828 { "vmulps", { XM
, Vex
, EXx
}, 0 },
4829 { "vmulss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4830 { "vmulpd", { XM
, Vex
, EXx
}, 0 },
4831 { "vmulsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4834 /* PREFIX_VEX_0F5A */
4836 { "vcvtps2pd", { XM
, EXxmmq
}, 0 },
4837 { "vcvtss2sd", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4838 { "vcvtpd2ps%XY",{ XMM
, EXx
}, 0 },
4839 { "vcvtsd2ss", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4842 /* PREFIX_VEX_0F5B */
4844 { "vcvtdq2ps", { XM
, EXx
}, 0 },
4845 { "vcvttps2dq", { XM
, EXx
}, 0 },
4846 { "vcvtps2dq", { XM
, EXx
}, 0 },
4849 /* PREFIX_VEX_0F5C */
4851 { "vsubps", { XM
, Vex
, EXx
}, 0 },
4852 { "vsubss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4853 { "vsubpd", { XM
, Vex
, EXx
}, 0 },
4854 { "vsubsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4857 /* PREFIX_VEX_0F5D */
4859 { "vminps", { XM
, Vex
, EXx
}, 0 },
4860 { "vminss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4861 { "vminpd", { XM
, Vex
, EXx
}, 0 },
4862 { "vminsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4865 /* PREFIX_VEX_0F5E */
4867 { "vdivps", { XM
, Vex
, EXx
}, 0 },
4868 { "vdivss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4869 { "vdivpd", { XM
, Vex
, EXx
}, 0 },
4870 { "vdivsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4873 /* PREFIX_VEX_0F5F */
4875 { "vmaxps", { XM
, Vex
, EXx
}, 0 },
4876 { "vmaxss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4877 { "vmaxpd", { XM
, Vex
, EXx
}, 0 },
4878 { "vmaxsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4881 /* PREFIX_VEX_0F60 */
4885 { "vpunpcklbw", { XM
, Vex
, EXx
}, 0 },
4888 /* PREFIX_VEX_0F61 */
4892 { "vpunpcklwd", { XM
, Vex
, EXx
}, 0 },
4895 /* PREFIX_VEX_0F62 */
4899 { "vpunpckldq", { XM
, Vex
, EXx
}, 0 },
4902 /* PREFIX_VEX_0F63 */
4906 { "vpacksswb", { XM
, Vex
, EXx
}, 0 },
4909 /* PREFIX_VEX_0F64 */
4913 { "vpcmpgtb", { XM
, Vex
, EXx
}, 0 },
4916 /* PREFIX_VEX_0F65 */
4920 { "vpcmpgtw", { XM
, Vex
, EXx
}, 0 },
4923 /* PREFIX_VEX_0F66 */
4927 { "vpcmpgtd", { XM
, Vex
, EXx
}, 0 },
4930 /* PREFIX_VEX_0F67 */
4934 { "vpackuswb", { XM
, Vex
, EXx
}, 0 },
4937 /* PREFIX_VEX_0F68 */
4941 { "vpunpckhbw", { XM
, Vex
, EXx
}, 0 },
4944 /* PREFIX_VEX_0F69 */
4948 { "vpunpckhwd", { XM
, Vex
, EXx
}, 0 },
4951 /* PREFIX_VEX_0F6A */
4955 { "vpunpckhdq", { XM
, Vex
, EXx
}, 0 },
4958 /* PREFIX_VEX_0F6B */
4962 { "vpackssdw", { XM
, Vex
, EXx
}, 0 },
4965 /* PREFIX_VEX_0F6C */
4969 { "vpunpcklqdq", { XM
, Vex
, EXx
}, 0 },
4972 /* PREFIX_VEX_0F6D */
4976 { "vpunpckhqdq", { XM
, Vex
, EXx
}, 0 },
4979 /* PREFIX_VEX_0F6E */
4983 { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2
) },
4986 /* PREFIX_VEX_0F6F */
4989 { "vmovdqu", { XM
, EXx
}, 0 },
4990 { "vmovdqa", { XM
, EXx
}, 0 },
4993 /* PREFIX_VEX_0F70 */
4996 { "vpshufhw", { XM
, EXx
, Ib
}, 0 },
4997 { "vpshufd", { XM
, EXx
, Ib
}, 0 },
4998 { "vpshuflw", { XM
, EXx
, Ib
}, 0 },
5001 /* PREFIX_VEX_0F71_REG_2 */
5005 { "vpsrlw", { Vex
, XS
, Ib
}, 0 },
5008 /* PREFIX_VEX_0F71_REG_4 */
5012 { "vpsraw", { Vex
, XS
, Ib
}, 0 },
5015 /* PREFIX_VEX_0F71_REG_6 */
5019 { "vpsllw", { Vex
, XS
, Ib
}, 0 },
5022 /* PREFIX_VEX_0F72_REG_2 */
5026 { "vpsrld", { Vex
, XS
, Ib
}, 0 },
5029 /* PREFIX_VEX_0F72_REG_4 */
5033 { "vpsrad", { Vex
, XS
, Ib
}, 0 },
5036 /* PREFIX_VEX_0F72_REG_6 */
5040 { "vpslld", { Vex
, XS
, Ib
}, 0 },
5043 /* PREFIX_VEX_0F73_REG_2 */
5047 { "vpsrlq", { Vex
, XS
, Ib
}, 0 },
5050 /* PREFIX_VEX_0F73_REG_3 */
5054 { "vpsrldq", { Vex
, XS
, Ib
}, 0 },
5057 /* PREFIX_VEX_0F73_REG_6 */
5061 { "vpsllq", { Vex
, XS
, Ib
}, 0 },
5064 /* PREFIX_VEX_0F73_REG_7 */
5068 { "vpslldq", { Vex
, XS
, Ib
}, 0 },
5071 /* PREFIX_VEX_0F74 */
5075 { "vpcmpeqb", { XM
, Vex
, EXx
}, 0 },
5078 /* PREFIX_VEX_0F75 */
5082 { "vpcmpeqw", { XM
, Vex
, EXx
}, 0 },
5085 /* PREFIX_VEX_0F76 */
5089 { "vpcmpeqd", { XM
, Vex
, EXx
}, 0 },
5092 /* PREFIX_VEX_0F77 */
5094 { VEX_LEN_TABLE (VEX_LEN_0F77_P_0
) },
5097 /* PREFIX_VEX_0F7C */
5101 { "vhaddpd", { XM
, Vex
, EXx
}, 0 },
5102 { "vhaddps", { XM
, Vex
, EXx
}, 0 },
5105 /* PREFIX_VEX_0F7D */
5109 { "vhsubpd", { XM
, Vex
, EXx
}, 0 },
5110 { "vhsubps", { XM
, Vex
, EXx
}, 0 },
5113 /* PREFIX_VEX_0F7E */
5116 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1
) },
5117 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2
) },
5120 /* PREFIX_VEX_0F7F */
5123 { "vmovdqu", { EXxS
, XM
}, 0 },
5124 { "vmovdqa", { EXxS
, XM
}, 0 },
5127 /* PREFIX_VEX_0F90 */
5129 { VEX_LEN_TABLE (VEX_LEN_0F90_P_0
) },
5131 { VEX_LEN_TABLE (VEX_LEN_0F90_P_2
) },
5134 /* PREFIX_VEX_0F91 */
5136 { VEX_LEN_TABLE (VEX_LEN_0F91_P_0
) },
5138 { VEX_LEN_TABLE (VEX_LEN_0F91_P_2
) },
5141 /* PREFIX_VEX_0F92 */
5143 { VEX_LEN_TABLE (VEX_LEN_0F92_P_0
) },
5145 { VEX_LEN_TABLE (VEX_LEN_0F92_P_2
) },
5146 { VEX_LEN_TABLE (VEX_LEN_0F92_P_3
) },
5149 /* PREFIX_VEX_0F93 */
5151 { VEX_LEN_TABLE (VEX_LEN_0F93_P_0
) },
5153 { VEX_LEN_TABLE (VEX_LEN_0F93_P_2
) },
5154 { VEX_LEN_TABLE (VEX_LEN_0F93_P_3
) },
5157 /* PREFIX_VEX_0F98 */
5159 { VEX_LEN_TABLE (VEX_LEN_0F98_P_0
) },
5161 { VEX_LEN_TABLE (VEX_LEN_0F98_P_2
) },
5164 /* PREFIX_VEX_0F99 */
5166 { VEX_LEN_TABLE (VEX_LEN_0F99_P_0
) },
5168 { VEX_LEN_TABLE (VEX_LEN_0F99_P_2
) },
5171 /* PREFIX_VEX_0FC2 */
5173 { "vcmpps", { XM
, Vex
, EXx
, VCMP
}, 0 },
5174 { "vcmpss", { XMScalar
, VexScalar
, EXdScalar
, VCMP
}, 0 },
5175 { "vcmppd", { XM
, Vex
, EXx
, VCMP
}, 0 },
5176 { "vcmpsd", { XMScalar
, VexScalar
, EXqScalar
, VCMP
}, 0 },
5179 /* PREFIX_VEX_0FC4 */
5183 { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2
) },
5186 /* PREFIX_VEX_0FC5 */
5190 { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2
) },
5193 /* PREFIX_VEX_0FD0 */
5197 { "vaddsubpd", { XM
, Vex
, EXx
}, 0 },
5198 { "vaddsubps", { XM
, Vex
, EXx
}, 0 },
5201 /* PREFIX_VEX_0FD1 */
5205 { "vpsrlw", { XM
, Vex
, EXxmm
}, 0 },
5208 /* PREFIX_VEX_0FD2 */
5212 { "vpsrld", { XM
, Vex
, EXxmm
}, 0 },
5215 /* PREFIX_VEX_0FD3 */
5219 { "vpsrlq", { XM
, Vex
, EXxmm
}, 0 },
5222 /* PREFIX_VEX_0FD4 */
5226 { "vpaddq", { XM
, Vex
, EXx
}, 0 },
5229 /* PREFIX_VEX_0FD5 */
5233 { "vpmullw", { XM
, Vex
, EXx
}, 0 },
5236 /* PREFIX_VEX_0FD6 */
5240 { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2
) },
5243 /* PREFIX_VEX_0FD7 */
5247 { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2
) },
5250 /* PREFIX_VEX_0FD8 */
5254 { "vpsubusb", { XM
, Vex
, EXx
}, 0 },
5257 /* PREFIX_VEX_0FD9 */
5261 { "vpsubusw", { XM
, Vex
, EXx
}, 0 },
5264 /* PREFIX_VEX_0FDA */
5268 { "vpminub", { XM
, Vex
, EXx
}, 0 },
5271 /* PREFIX_VEX_0FDB */
5275 { "vpand", { XM
, Vex
, EXx
}, 0 },
5278 /* PREFIX_VEX_0FDC */
5282 { "vpaddusb", { XM
, Vex
, EXx
}, 0 },
5285 /* PREFIX_VEX_0FDD */
5289 { "vpaddusw", { XM
, Vex
, EXx
}, 0 },
5292 /* PREFIX_VEX_0FDE */
5296 { "vpmaxub", { XM
, Vex
, EXx
}, 0 },
5299 /* PREFIX_VEX_0FDF */
5303 { "vpandn", { XM
, Vex
, EXx
}, 0 },
5306 /* PREFIX_VEX_0FE0 */
5310 { "vpavgb", { XM
, Vex
, EXx
}, 0 },
5313 /* PREFIX_VEX_0FE1 */
5317 { "vpsraw", { XM
, Vex
, EXxmm
}, 0 },
5320 /* PREFIX_VEX_0FE2 */
5324 { "vpsrad", { XM
, Vex
, EXxmm
}, 0 },
5327 /* PREFIX_VEX_0FE3 */
5331 { "vpavgw", { XM
, Vex
, EXx
}, 0 },
5334 /* PREFIX_VEX_0FE4 */
5338 { "vpmulhuw", { XM
, Vex
, EXx
}, 0 },
5341 /* PREFIX_VEX_0FE5 */
5345 { "vpmulhw", { XM
, Vex
, EXx
}, 0 },
5348 /* PREFIX_VEX_0FE6 */
5351 { "vcvtdq2pd", { XM
, EXxmmq
}, 0 },
5352 { "vcvttpd2dq%XY", { XMM
, EXx
}, 0 },
5353 { "vcvtpd2dq%XY", { XMM
, EXx
}, 0 },
5356 /* PREFIX_VEX_0FE7 */
5360 { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2
) },
5363 /* PREFIX_VEX_0FE8 */
5367 { "vpsubsb", { XM
, Vex
, EXx
}, 0 },
5370 /* PREFIX_VEX_0FE9 */
5374 { "vpsubsw", { XM
, Vex
, EXx
}, 0 },
5377 /* PREFIX_VEX_0FEA */
5381 { "vpminsw", { XM
, Vex
, EXx
}, 0 },
5384 /* PREFIX_VEX_0FEB */
5388 { "vpor", { XM
, Vex
, EXx
}, 0 },
5391 /* PREFIX_VEX_0FEC */
5395 { "vpaddsb", { XM
, Vex
, EXx
}, 0 },
5398 /* PREFIX_VEX_0FED */
5402 { "vpaddsw", { XM
, Vex
, EXx
}, 0 },
5405 /* PREFIX_VEX_0FEE */
5409 { "vpmaxsw", { XM
, Vex
, EXx
}, 0 },
5412 /* PREFIX_VEX_0FEF */
5416 { "vpxor", { XM
, Vex
, EXx
}, 0 },
5419 /* PREFIX_VEX_0FF0 */
5424 { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3
) },
5427 /* PREFIX_VEX_0FF1 */
5431 { "vpsllw", { XM
, Vex
, EXxmm
}, 0 },
5434 /* PREFIX_VEX_0FF2 */
5438 { "vpslld", { XM
, Vex
, EXxmm
}, 0 },
5441 /* PREFIX_VEX_0FF3 */
5445 { "vpsllq", { XM
, Vex
, EXxmm
}, 0 },
5448 /* PREFIX_VEX_0FF4 */
5452 { "vpmuludq", { XM
, Vex
, EXx
}, 0 },
5455 /* PREFIX_VEX_0FF5 */
5459 { "vpmaddwd", { XM
, Vex
, EXx
}, 0 },
5462 /* PREFIX_VEX_0FF6 */
5466 { "vpsadbw", { XM
, Vex
, EXx
}, 0 },
5469 /* PREFIX_VEX_0FF7 */
5473 { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2
) },
5476 /* PREFIX_VEX_0FF8 */
5480 { "vpsubb", { XM
, Vex
, EXx
}, 0 },
5483 /* PREFIX_VEX_0FF9 */
5487 { "vpsubw", { XM
, Vex
, EXx
}, 0 },
5490 /* PREFIX_VEX_0FFA */
5494 { "vpsubd", { XM
, Vex
, EXx
}, 0 },
5497 /* PREFIX_VEX_0FFB */
5501 { "vpsubq", { XM
, Vex
, EXx
}, 0 },
5504 /* PREFIX_VEX_0FFC */
5508 { "vpaddb", { XM
, Vex
, EXx
}, 0 },
5511 /* PREFIX_VEX_0FFD */
5515 { "vpaddw", { XM
, Vex
, EXx
}, 0 },
5518 /* PREFIX_VEX_0FFE */
5522 { "vpaddd", { XM
, Vex
, EXx
}, 0 },
5525 /* PREFIX_VEX_0F3800 */
5529 { "vpshufb", { XM
, Vex
, EXx
}, 0 },
5532 /* PREFIX_VEX_0F3801 */
5536 { "vphaddw", { XM
, Vex
, EXx
}, 0 },
5539 /* PREFIX_VEX_0F3802 */
5543 { "vphaddd", { XM
, Vex
, EXx
}, 0 },
5546 /* PREFIX_VEX_0F3803 */
5550 { "vphaddsw", { XM
, Vex
, EXx
}, 0 },
5553 /* PREFIX_VEX_0F3804 */
5557 { "vpmaddubsw", { XM
, Vex
, EXx
}, 0 },
5560 /* PREFIX_VEX_0F3805 */
5564 { "vphsubw", { XM
, Vex
, EXx
}, 0 },
5567 /* PREFIX_VEX_0F3806 */
5571 { "vphsubd", { XM
, Vex
, EXx
}, 0 },
5574 /* PREFIX_VEX_0F3807 */
5578 { "vphsubsw", { XM
, Vex
, EXx
}, 0 },
5581 /* PREFIX_VEX_0F3808 */
5585 { "vpsignb", { XM
, Vex
, EXx
}, 0 },
5588 /* PREFIX_VEX_0F3809 */
5592 { "vpsignw", { XM
, Vex
, EXx
}, 0 },
5595 /* PREFIX_VEX_0F380A */
5599 { "vpsignd", { XM
, Vex
, EXx
}, 0 },
5602 /* PREFIX_VEX_0F380B */
5606 { "vpmulhrsw", { XM
, Vex
, EXx
}, 0 },
5609 /* PREFIX_VEX_0F380C */
5613 { VEX_W_TABLE (VEX_W_0F380C_P_2
) },
5616 /* PREFIX_VEX_0F380D */
5620 { VEX_W_TABLE (VEX_W_0F380D_P_2
) },
5623 /* PREFIX_VEX_0F380E */
5627 { VEX_W_TABLE (VEX_W_0F380E_P_2
) },
5630 /* PREFIX_VEX_0F380F */
5634 { VEX_W_TABLE (VEX_W_0F380F_P_2
) },
5637 /* PREFIX_VEX_0F3813 */
5641 { "vcvtph2ps", { XM
, EXxmmq
}, 0 },
5644 /* PREFIX_VEX_0F3816 */
5648 { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2
) },
5651 /* PREFIX_VEX_0F3817 */
5655 { "vptest", { XM
, EXx
}, 0 },
5658 /* PREFIX_VEX_0F3818 */
5662 { VEX_W_TABLE (VEX_W_0F3818_P_2
) },
5665 /* PREFIX_VEX_0F3819 */
5669 { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2
) },
5672 /* PREFIX_VEX_0F381A */
5676 { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2
) },
5679 /* PREFIX_VEX_0F381C */
5683 { "vpabsb", { XM
, EXx
}, 0 },
5686 /* PREFIX_VEX_0F381D */
5690 { "vpabsw", { XM
, EXx
}, 0 },
5693 /* PREFIX_VEX_0F381E */
5697 { "vpabsd", { XM
, EXx
}, 0 },
5700 /* PREFIX_VEX_0F3820 */
5704 { "vpmovsxbw", { XM
, EXxmmq
}, 0 },
5707 /* PREFIX_VEX_0F3821 */
5711 { "vpmovsxbd", { XM
, EXxmmqd
}, 0 },
5714 /* PREFIX_VEX_0F3822 */
5718 { "vpmovsxbq", { XM
, EXxmmdw
}, 0 },
5721 /* PREFIX_VEX_0F3823 */
5725 { "vpmovsxwd", { XM
, EXxmmq
}, 0 },
5728 /* PREFIX_VEX_0F3824 */
5732 { "vpmovsxwq", { XM
, EXxmmqd
}, 0 },
5735 /* PREFIX_VEX_0F3825 */
5739 { "vpmovsxdq", { XM
, EXxmmq
}, 0 },
5742 /* PREFIX_VEX_0F3828 */
5746 { "vpmuldq", { XM
, Vex
, EXx
}, 0 },
5749 /* PREFIX_VEX_0F3829 */
5753 { "vpcmpeqq", { XM
, Vex
, EXx
}, 0 },
5756 /* PREFIX_VEX_0F382A */
5760 { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2
) },
5763 /* PREFIX_VEX_0F382B */
5767 { "vpackusdw", { XM
, Vex
, EXx
}, 0 },
5770 /* PREFIX_VEX_0F382C */
5774 { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2
) },
5777 /* PREFIX_VEX_0F382D */
5781 { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2
) },
5784 /* PREFIX_VEX_0F382E */
5788 { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2
) },
5791 /* PREFIX_VEX_0F382F */
5795 { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2
) },
5798 /* PREFIX_VEX_0F3830 */
5802 { "vpmovzxbw", { XM
, EXxmmq
}, 0 },
5805 /* PREFIX_VEX_0F3831 */
5809 { "vpmovzxbd", { XM
, EXxmmqd
}, 0 },
5812 /* PREFIX_VEX_0F3832 */
5816 { "vpmovzxbq", { XM
, EXxmmdw
}, 0 },
5819 /* PREFIX_VEX_0F3833 */
5823 { "vpmovzxwd", { XM
, EXxmmq
}, 0 },
5826 /* PREFIX_VEX_0F3834 */
5830 { "vpmovzxwq", { XM
, EXxmmqd
}, 0 },
5833 /* PREFIX_VEX_0F3835 */
5837 { "vpmovzxdq", { XM
, EXxmmq
}, 0 },
5840 /* PREFIX_VEX_0F3836 */
5844 { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2
) },
5847 /* PREFIX_VEX_0F3837 */
5851 { "vpcmpgtq", { XM
, Vex
, EXx
}, 0 },
5854 /* PREFIX_VEX_0F3838 */
5858 { "vpminsb", { XM
, Vex
, EXx
}, 0 },
5861 /* PREFIX_VEX_0F3839 */
5865 { "vpminsd", { XM
, Vex
, EXx
}, 0 },
5868 /* PREFIX_VEX_0F383A */
5872 { "vpminuw", { XM
, Vex
, EXx
}, 0 },
5875 /* PREFIX_VEX_0F383B */
5879 { "vpminud", { XM
, Vex
, EXx
}, 0 },
5882 /* PREFIX_VEX_0F383C */
5886 { "vpmaxsb", { XM
, Vex
, EXx
}, 0 },
5889 /* PREFIX_VEX_0F383D */
5893 { "vpmaxsd", { XM
, Vex
, EXx
}, 0 },
5896 /* PREFIX_VEX_0F383E */
5900 { "vpmaxuw", { XM
, Vex
, EXx
}, 0 },
5903 /* PREFIX_VEX_0F383F */
5907 { "vpmaxud", { XM
, Vex
, EXx
}, 0 },
5910 /* PREFIX_VEX_0F3840 */
5914 { "vpmulld", { XM
, Vex
, EXx
}, 0 },
5917 /* PREFIX_VEX_0F3841 */
5921 { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2
) },
5924 /* PREFIX_VEX_0F3845 */
5928 { "vpsrlv%LW", { XM
, Vex
, EXx
}, 0 },
5931 /* PREFIX_VEX_0F3846 */
5935 { VEX_W_TABLE (VEX_W_0F3846_P_2
) },
5938 /* PREFIX_VEX_0F3847 */
5942 { "vpsllv%LW", { XM
, Vex
, EXx
}, 0 },
5945 /* PREFIX_VEX_0F3858 */
5949 { VEX_W_TABLE (VEX_W_0F3858_P_2
) },
5952 /* PREFIX_VEX_0F3859 */
5956 { VEX_W_TABLE (VEX_W_0F3859_P_2
) },
5959 /* PREFIX_VEX_0F385A */
5963 { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2
) },
5966 /* PREFIX_VEX_0F3878 */
5970 { VEX_W_TABLE (VEX_W_0F3878_P_2
) },
5973 /* PREFIX_VEX_0F3879 */
5977 { VEX_W_TABLE (VEX_W_0F3879_P_2
) },
5980 /* PREFIX_VEX_0F388C */
5984 { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2
) },
5987 /* PREFIX_VEX_0F388E */
5991 { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2
) },
5994 /* PREFIX_VEX_0F3890 */
5998 { "vpgatherd%LW", { XM
, MVexVSIBDWpX
, Vex
}, 0 },
6001 /* PREFIX_VEX_0F3891 */
6005 { "vpgatherq%LW", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
}, 0 },
6008 /* PREFIX_VEX_0F3892 */
6012 { "vgatherdp%XW", { XM
, MVexVSIBDWpX
, Vex
}, 0 },
6015 /* PREFIX_VEX_0F3893 */
6019 { "vgatherqp%XW", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
}, 0 },
6022 /* PREFIX_VEX_0F3896 */
6026 { "vfmaddsub132p%XW", { XM
, Vex
, EXx
}, 0 },
6029 /* PREFIX_VEX_0F3897 */
6033 { "vfmsubadd132p%XW", { XM
, Vex
, EXx
}, 0 },
6036 /* PREFIX_VEX_0F3898 */
6040 { "vfmadd132p%XW", { XM
, Vex
, EXx
}, 0 },
6043 /* PREFIX_VEX_0F3899 */
6047 { "vfmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6050 /* PREFIX_VEX_0F389A */
6054 { "vfmsub132p%XW", { XM
, Vex
, EXx
}, 0 },
6057 /* PREFIX_VEX_0F389B */
6061 { "vfmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6064 /* PREFIX_VEX_0F389C */
6068 { "vfnmadd132p%XW", { XM
, Vex
, EXx
}, 0 },
6071 /* PREFIX_VEX_0F389D */
6075 { "vfnmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6078 /* PREFIX_VEX_0F389E */
6082 { "vfnmsub132p%XW", { XM
, Vex
, EXx
}, 0 },
6085 /* PREFIX_VEX_0F389F */
6089 { "vfnmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6092 /* PREFIX_VEX_0F38A6 */
6096 { "vfmaddsub213p%XW", { XM
, Vex
, EXx
}, 0 },
6100 /* PREFIX_VEX_0F38A7 */
6104 { "vfmsubadd213p%XW", { XM
, Vex
, EXx
}, 0 },
6107 /* PREFIX_VEX_0F38A8 */
6111 { "vfmadd213p%XW", { XM
, Vex
, EXx
}, 0 },
6114 /* PREFIX_VEX_0F38A9 */
6118 { "vfmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6121 /* PREFIX_VEX_0F38AA */
6125 { "vfmsub213p%XW", { XM
, Vex
, EXx
}, 0 },
6128 /* PREFIX_VEX_0F38AB */
6132 { "vfmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6135 /* PREFIX_VEX_0F38AC */
6139 { "vfnmadd213p%XW", { XM
, Vex
, EXx
}, 0 },
6142 /* PREFIX_VEX_0F38AD */
6146 { "vfnmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6149 /* PREFIX_VEX_0F38AE */
6153 { "vfnmsub213p%XW", { XM
, Vex
, EXx
}, 0 },
6156 /* PREFIX_VEX_0F38AF */
6160 { "vfnmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6163 /* PREFIX_VEX_0F38B6 */
6167 { "vfmaddsub231p%XW", { XM
, Vex
, EXx
}, 0 },
6170 /* PREFIX_VEX_0F38B7 */
6174 { "vfmsubadd231p%XW", { XM
, Vex
, EXx
}, 0 },
6177 /* PREFIX_VEX_0F38B8 */
6181 { "vfmadd231p%XW", { XM
, Vex
, EXx
}, 0 },
6184 /* PREFIX_VEX_0F38B9 */
6188 { "vfmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6191 /* PREFIX_VEX_0F38BA */
6195 { "vfmsub231p%XW", { XM
, Vex
, EXx
}, 0 },
6198 /* PREFIX_VEX_0F38BB */
6202 { "vfmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6205 /* PREFIX_VEX_0F38BC */
6209 { "vfnmadd231p%XW", { XM
, Vex
, EXx
}, 0 },
6212 /* PREFIX_VEX_0F38BD */
6216 { "vfnmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6219 /* PREFIX_VEX_0F38BE */
6223 { "vfnmsub231p%XW", { XM
, Vex
, EXx
}, 0 },
6226 /* PREFIX_VEX_0F38BF */
6230 { "vfnmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6233 /* PREFIX_VEX_0F38CF */
6237 { VEX_W_TABLE (VEX_W_0F38CF_P_2
) },
6240 /* PREFIX_VEX_0F38DB */
6244 { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2
) },
6247 /* PREFIX_VEX_0F38DC */
6251 { "vaesenc", { XM
, Vex
, EXx
}, 0 },
6254 /* PREFIX_VEX_0F38DD */
6258 { "vaesenclast", { XM
, Vex
, EXx
}, 0 },
6261 /* PREFIX_VEX_0F38DE */
6265 { "vaesdec", { XM
, Vex
, EXx
}, 0 },
6268 /* PREFIX_VEX_0F38DF */
6272 { "vaesdeclast", { XM
, Vex
, EXx
}, 0 },
6275 /* PREFIX_VEX_0F38F2 */
6277 { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0
) },
6280 /* PREFIX_VEX_0F38F3_REG_1 */
6282 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0
) },
6285 /* PREFIX_VEX_0F38F3_REG_2 */
6287 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0
) },
6290 /* PREFIX_VEX_0F38F3_REG_3 */
6292 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0
) },
6295 /* PREFIX_VEX_0F38F5 */
6297 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0
) },
6298 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1
) },
6300 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3
) },
6303 /* PREFIX_VEX_0F38F6 */
6308 { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3
) },
6311 /* PREFIX_VEX_0F38F7 */
6313 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0
) },
6314 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1
) },
6315 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2
) },
6316 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3
) },
6319 /* PREFIX_VEX_0F3A00 */
6323 { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2
) },
6326 /* PREFIX_VEX_0F3A01 */
6330 { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2
) },
6333 /* PREFIX_VEX_0F3A02 */
6337 { VEX_W_TABLE (VEX_W_0F3A02_P_2
) },
6340 /* PREFIX_VEX_0F3A04 */
6344 { VEX_W_TABLE (VEX_W_0F3A04_P_2
) },
6347 /* PREFIX_VEX_0F3A05 */
6351 { VEX_W_TABLE (VEX_W_0F3A05_P_2
) },
6354 /* PREFIX_VEX_0F3A06 */
6358 { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2
) },
6361 /* PREFIX_VEX_0F3A08 */
6365 { "vroundps", { XM
, EXx
, Ib
}, 0 },
6368 /* PREFIX_VEX_0F3A09 */
6372 { "vroundpd", { XM
, EXx
, Ib
}, 0 },
6375 /* PREFIX_VEX_0F3A0A */
6379 { "vroundss", { XMScalar
, VexScalar
, EXdScalar
, Ib
}, 0 },
6382 /* PREFIX_VEX_0F3A0B */
6386 { "vroundsd", { XMScalar
, VexScalar
, EXqScalar
, Ib
}, 0 },
6389 /* PREFIX_VEX_0F3A0C */
6393 { "vblendps", { XM
, Vex
, EXx
, Ib
}, 0 },
6396 /* PREFIX_VEX_0F3A0D */
6400 { "vblendpd", { XM
, Vex
, EXx
, Ib
}, 0 },
6403 /* PREFIX_VEX_0F3A0E */
6407 { "vpblendw", { XM
, Vex
, EXx
, Ib
}, 0 },
6410 /* PREFIX_VEX_0F3A0F */
6414 { "vpalignr", { XM
, Vex
, EXx
, Ib
}, 0 },
6417 /* PREFIX_VEX_0F3A14 */
6421 { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2
) },
6424 /* PREFIX_VEX_0F3A15 */
6428 { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2
) },
6431 /* PREFIX_VEX_0F3A16 */
6435 { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2
) },
6438 /* PREFIX_VEX_0F3A17 */
6442 { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2
) },
6445 /* PREFIX_VEX_0F3A18 */
6449 { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2
) },
6452 /* PREFIX_VEX_0F3A19 */
6456 { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2
) },
6459 /* PREFIX_VEX_0F3A1D */
6463 { "vcvtps2ph", { EXxmmq
, XM
, Ib
}, 0 },
6466 /* PREFIX_VEX_0F3A20 */
6470 { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2
) },
6473 /* PREFIX_VEX_0F3A21 */
6477 { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2
) },
6480 /* PREFIX_VEX_0F3A22 */
6484 { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2
) },
6487 /* PREFIX_VEX_0F3A30 */
6491 { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2
) },
6494 /* PREFIX_VEX_0F3A31 */
6498 { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2
) },
6501 /* PREFIX_VEX_0F3A32 */
6505 { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2
) },
6508 /* PREFIX_VEX_0F3A33 */
6512 { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2
) },
6515 /* PREFIX_VEX_0F3A38 */
6519 { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2
) },
6522 /* PREFIX_VEX_0F3A39 */
6526 { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2
) },
6529 /* PREFIX_VEX_0F3A40 */
6533 { "vdpps", { XM
, Vex
, EXx
, Ib
}, 0 },
6536 /* PREFIX_VEX_0F3A41 */
6540 { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2
) },
6543 /* PREFIX_VEX_0F3A42 */
6547 { "vmpsadbw", { XM
, Vex
, EXx
, Ib
}, 0 },
6550 /* PREFIX_VEX_0F3A44 */
6554 { "vpclmulqdq", { XM
, Vex
, EXx
, PCLMUL
}, 0 },
6557 /* PREFIX_VEX_0F3A46 */
6561 { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2
) },
6564 /* PREFIX_VEX_0F3A48 */
6568 { VEX_W_TABLE (VEX_W_0F3A48_P_2
) },
6571 /* PREFIX_VEX_0F3A49 */
6575 { VEX_W_TABLE (VEX_W_0F3A49_P_2
) },
6578 /* PREFIX_VEX_0F3A4A */
6582 { VEX_W_TABLE (VEX_W_0F3A4A_P_2
) },
6585 /* PREFIX_VEX_0F3A4B */
6589 { VEX_W_TABLE (VEX_W_0F3A4B_P_2
) },
6592 /* PREFIX_VEX_0F3A4C */
6596 { VEX_W_TABLE (VEX_W_0F3A4C_P_2
) },
6599 /* PREFIX_VEX_0F3A5C */
6603 { "vfmaddsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6606 /* PREFIX_VEX_0F3A5D */
6610 { "vfmaddsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6613 /* PREFIX_VEX_0F3A5E */
6617 { "vfmsubaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6620 /* PREFIX_VEX_0F3A5F */
6624 { "vfmsubaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6627 /* PREFIX_VEX_0F3A60 */
6631 { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2
) },
6635 /* PREFIX_VEX_0F3A61 */
6639 { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2
) },
6642 /* PREFIX_VEX_0F3A62 */
6646 { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2
) },
6649 /* PREFIX_VEX_0F3A63 */
6653 { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2
) },
6656 /* PREFIX_VEX_0F3A68 */
6660 { "vfmaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6663 /* PREFIX_VEX_0F3A69 */
6667 { "vfmaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6670 /* PREFIX_VEX_0F3A6A */
6674 { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2
) },
6677 /* PREFIX_VEX_0F3A6B */
6681 { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2
) },
6684 /* PREFIX_VEX_0F3A6C */
6688 { "vfmsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6691 /* PREFIX_VEX_0F3A6D */
6695 { "vfmsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6698 /* PREFIX_VEX_0F3A6E */
6702 { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2
) },
6705 /* PREFIX_VEX_0F3A6F */
6709 { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2
) },
6712 /* PREFIX_VEX_0F3A78 */
6716 { "vfnmaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6719 /* PREFIX_VEX_0F3A79 */
6723 { "vfnmaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6726 /* PREFIX_VEX_0F3A7A */
6730 { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2
) },
6733 /* PREFIX_VEX_0F3A7B */
6737 { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2
) },
6740 /* PREFIX_VEX_0F3A7C */
6744 { "vfnmsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6748 /* PREFIX_VEX_0F3A7D */
6752 { "vfnmsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6755 /* PREFIX_VEX_0F3A7E */
6759 { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2
) },
6762 /* PREFIX_VEX_0F3A7F */
6766 { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2
) },
6769 /* PREFIX_VEX_0F3ACE */
6773 { VEX_W_TABLE (VEX_W_0F3ACE_P_2
) },
6776 /* PREFIX_VEX_0F3ACF */
6780 { VEX_W_TABLE (VEX_W_0F3ACF_P_2
) },
6783 /* PREFIX_VEX_0F3ADF */
6787 { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2
) },
6790 /* PREFIX_VEX_0F3AF0 */
6795 { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3
) },
6798 #include "i386-dis-evex-prefix.h"
6801 static const struct dis386 x86_64_table
[][2] = {
6804 { "pushP", { es
}, 0 },
6809 { "popP", { es
}, 0 },
6814 { "pushP", { cs
}, 0 },
6819 { "pushP", { ss
}, 0 },
6824 { "popP", { ss
}, 0 },
6829 { "pushP", { ds
}, 0 },
6834 { "popP", { ds
}, 0 },
6839 { "daa", { XX
}, 0 },
6844 { "das", { XX
}, 0 },
6849 { "aaa", { XX
}, 0 },
6854 { "aas", { XX
}, 0 },
6859 { "pushaP", { XX
}, 0 },
6864 { "popaP", { XX
}, 0 },
6869 { MOD_TABLE (MOD_62_32BIT
) },
6870 { EVEX_TABLE (EVEX_0F
) },
6875 { "arpl", { Ew
, Gw
}, 0 },
6876 { "movs{lq|xd}", { Gv
, Ed
}, 0 },
6881 { "ins{R|}", { Yzr
, indirDX
}, 0 },
6882 { "ins{G|}", { Yzr
, indirDX
}, 0 },
6887 { "outs{R|}", { indirDXr
, Xz
}, 0 },
6888 { "outs{G|}", { indirDXr
, Xz
}, 0 },
6893 /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode. */
6894 { REG_TABLE (REG_80
) },
6899 { "Jcall{T|}", { Ap
}, 0 },
6904 { MOD_TABLE (MOD_C4_32BIT
) },
6905 { VEX_C4_TABLE (VEX_0F
) },
6910 { MOD_TABLE (MOD_C5_32BIT
) },
6911 { VEX_C5_TABLE (VEX_0F
) },
6916 { "into", { XX
}, 0 },
6921 { "aam", { Ib
}, 0 },
6926 { "aad", { Ib
}, 0 },
6931 { "callP", { Jv
, BND
}, 0 },
6932 { "call@", { Jv
, BND
}, 0 }
6937 { "jmpP", { Jv
, BND
}, 0 },
6938 { "jmp@", { Jv
, BND
}, 0 }
6943 { "Jjmp{T|}", { Ap
}, 0 },
6946 /* X86_64_0F01_REG_0 */
6948 { "sgdt{Q|IQ}", { M
}, 0 },
6949 { "sgdt", { M
}, 0 },
6952 /* X86_64_0F01_REG_1 */
6954 { "sidt{Q|IQ}", { M
}, 0 },
6955 { "sidt", { M
}, 0 },
6958 /* X86_64_0F01_REG_2 */
6960 { "lgdt{Q|Q}", { M
}, 0 },
6961 { "lgdt", { M
}, 0 },
6964 /* X86_64_0F01_REG_3 */
6966 { "lidt{Q|Q}", { M
}, 0 },
6967 { "lidt", { M
}, 0 },
6971 static const struct dis386 three_byte_table
[][256] = {
6973 /* THREE_BYTE_0F38 */
6976 { "pshufb", { MX
, EM
}, PREFIX_OPCODE
},
6977 { "phaddw", { MX
, EM
}, PREFIX_OPCODE
},
6978 { "phaddd", { MX
, EM
}, PREFIX_OPCODE
},
6979 { "phaddsw", { MX
, EM
}, PREFIX_OPCODE
},
6980 { "pmaddubsw", { MX
, EM
}, PREFIX_OPCODE
},
6981 { "phsubw", { MX
, EM
}, PREFIX_OPCODE
},
6982 { "phsubd", { MX
, EM
}, PREFIX_OPCODE
},
6983 { "phsubsw", { MX
, EM
}, PREFIX_OPCODE
},
6985 { "psignb", { MX
, EM
}, PREFIX_OPCODE
},
6986 { "psignw", { MX
, EM
}, PREFIX_OPCODE
},
6987 { "psignd", { MX
, EM
}, PREFIX_OPCODE
},
6988 { "pmulhrsw", { MX
, EM
}, PREFIX_OPCODE
},
6994 { PREFIX_TABLE (PREFIX_0F3810
) },
6998 { PREFIX_TABLE (PREFIX_0F3814
) },
6999 { PREFIX_TABLE (PREFIX_0F3815
) },
7001 { PREFIX_TABLE (PREFIX_0F3817
) },
7007 { "pabsb", { MX
, EM
}, PREFIX_OPCODE
},
7008 { "pabsw", { MX
, EM
}, PREFIX_OPCODE
},
7009 { "pabsd", { MX
, EM
}, PREFIX_OPCODE
},
7012 { PREFIX_TABLE (PREFIX_0F3820
) },
7013 { PREFIX_TABLE (PREFIX_0F3821
) },
7014 { PREFIX_TABLE (PREFIX_0F3822
) },
7015 { PREFIX_TABLE (PREFIX_0F3823
) },
7016 { PREFIX_TABLE (PREFIX_0F3824
) },
7017 { PREFIX_TABLE (PREFIX_0F3825
) },
7021 { PREFIX_TABLE (PREFIX_0F3828
) },
7022 { PREFIX_TABLE (PREFIX_0F3829
) },
7023 { PREFIX_TABLE (PREFIX_0F382A
) },
7024 { PREFIX_TABLE (PREFIX_0F382B
) },
7030 { PREFIX_TABLE (PREFIX_0F3830
) },
7031 { PREFIX_TABLE (PREFIX_0F3831
) },
7032 { PREFIX_TABLE (PREFIX_0F3832
) },
7033 { PREFIX_TABLE (PREFIX_0F3833
) },
7034 { PREFIX_TABLE (PREFIX_0F3834
) },
7035 { PREFIX_TABLE (PREFIX_0F3835
) },
7037 { PREFIX_TABLE (PREFIX_0F3837
) },
7039 { PREFIX_TABLE (PREFIX_0F3838
) },
7040 { PREFIX_TABLE (PREFIX_0F3839
) },
7041 { PREFIX_TABLE (PREFIX_0F383A
) },
7042 { PREFIX_TABLE (PREFIX_0F383B
) },
7043 { PREFIX_TABLE (PREFIX_0F383C
) },
7044 { PREFIX_TABLE (PREFIX_0F383D
) },
7045 { PREFIX_TABLE (PREFIX_0F383E
) },
7046 { PREFIX_TABLE (PREFIX_0F383F
) },
7048 { PREFIX_TABLE (PREFIX_0F3840
) },
7049 { PREFIX_TABLE (PREFIX_0F3841
) },
7120 { PREFIX_TABLE (PREFIX_0F3880
) },
7121 { PREFIX_TABLE (PREFIX_0F3881
) },
7122 { PREFIX_TABLE (PREFIX_0F3882
) },
7201 { PREFIX_TABLE (PREFIX_0F38C8
) },
7202 { PREFIX_TABLE (PREFIX_0F38C9
) },
7203 { PREFIX_TABLE (PREFIX_0F38CA
) },
7204 { PREFIX_TABLE (PREFIX_0F38CB
) },
7205 { PREFIX_TABLE (PREFIX_0F38CC
) },
7206 { PREFIX_TABLE (PREFIX_0F38CD
) },
7208 { PREFIX_TABLE (PREFIX_0F38CF
) },
7222 { PREFIX_TABLE (PREFIX_0F38DB
) },
7223 { PREFIX_TABLE (PREFIX_0F38DC
) },
7224 { PREFIX_TABLE (PREFIX_0F38DD
) },
7225 { PREFIX_TABLE (PREFIX_0F38DE
) },
7226 { PREFIX_TABLE (PREFIX_0F38DF
) },
7246 { PREFIX_TABLE (PREFIX_0F38F0
) },
7247 { PREFIX_TABLE (PREFIX_0F38F1
) },
7251 { PREFIX_TABLE (PREFIX_0F38F5
) },
7252 { PREFIX_TABLE (PREFIX_0F38F6
) },
7255 { PREFIX_TABLE (PREFIX_0F38F8
) },
7256 { PREFIX_TABLE (PREFIX_0F38F9
) },
7264 /* THREE_BYTE_0F3A */
7276 { PREFIX_TABLE (PREFIX_0F3A08
) },
7277 { PREFIX_TABLE (PREFIX_0F3A09
) },
7278 { PREFIX_TABLE (PREFIX_0F3A0A
) },
7279 { PREFIX_TABLE (PREFIX_0F3A0B
) },
7280 { PREFIX_TABLE (PREFIX_0F3A0C
) },
7281 { PREFIX_TABLE (PREFIX_0F3A0D
) },
7282 { PREFIX_TABLE (PREFIX_0F3A0E
) },
7283 { "palignr", { MX
, EM
, Ib
}, PREFIX_OPCODE
},
7289 { PREFIX_TABLE (PREFIX_0F3A14
) },
7290 { PREFIX_TABLE (PREFIX_0F3A15
) },
7291 { PREFIX_TABLE (PREFIX_0F3A16
) },
7292 { PREFIX_TABLE (PREFIX_0F3A17
) },
7303 { PREFIX_TABLE (PREFIX_0F3A20
) },
7304 { PREFIX_TABLE (PREFIX_0F3A21
) },
7305 { PREFIX_TABLE (PREFIX_0F3A22
) },
7339 { PREFIX_TABLE (PREFIX_0F3A40
) },
7340 { PREFIX_TABLE (PREFIX_0F3A41
) },
7341 { PREFIX_TABLE (PREFIX_0F3A42
) },
7343 { PREFIX_TABLE (PREFIX_0F3A44
) },
7375 { PREFIX_TABLE (PREFIX_0F3A60
) },
7376 { PREFIX_TABLE (PREFIX_0F3A61
) },
7377 { PREFIX_TABLE (PREFIX_0F3A62
) },
7378 { PREFIX_TABLE (PREFIX_0F3A63
) },
7496 { PREFIX_TABLE (PREFIX_0F3ACC
) },
7498 { PREFIX_TABLE (PREFIX_0F3ACE
) },
7499 { PREFIX_TABLE (PREFIX_0F3ACF
) },
7517 { PREFIX_TABLE (PREFIX_0F3ADF
) },
7557 static const struct dis386 xop_table
[][256] = {
7710 { "vpmacssww", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7711 { "vpmacsswd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7712 { "vpmacssdql", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7720 { "vpmacssdd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7721 { "vpmacssdqh", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7728 { "vpmacsww", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7729 { "vpmacswd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7730 { "vpmacsdql", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7738 { "vpmacsdd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7739 { "vpmacsdqh", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7743 { "vpcmov", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7744 { "vpperm", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7747 { "vpmadcsswd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7765 { "vpmadcswd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7777 { "vprotb", { XM
, Vex_2src_1
, Ib
}, 0 },
7778 { "vprotw", { XM
, Vex_2src_1
, Ib
}, 0 },
7779 { "vprotd", { XM
, Vex_2src_1
, Ib
}, 0 },
7780 { "vprotq", { XM
, Vex_2src_1
, Ib
}, 0 },
7790 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC
) },
7791 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD
) },
7792 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE
) },
7793 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF
) },
7826 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC
) },
7827 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED
) },
7828 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE
) },
7829 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF
) },
7853 { REG_TABLE (REG_XOP_TBM_01
) },
7854 { REG_TABLE (REG_XOP_TBM_02
) },
7872 { REG_TABLE (REG_XOP_LWPCB
) },
7996 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80
) },
7997 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81
) },
7998 { "vfrczss", { XM
, EXd
}, 0 },
7999 { "vfrczsd", { XM
, EXq
}, 0 },
8014 { "vprotb", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8015 { "vprotw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8016 { "vprotd", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8017 { "vprotq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8018 { "vpshlb", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8019 { "vpshlw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8020 { "vpshld", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8021 { "vpshlq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8023 { "vpshab", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8024 { "vpshaw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8025 { "vpshad", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8026 { "vpshaq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8069 { "vphaddbw", { XM
, EXxmm
}, 0 },
8070 { "vphaddbd", { XM
, EXxmm
}, 0 },
8071 { "vphaddbq", { XM
, EXxmm
}, 0 },
8074 { "vphaddwd", { XM
, EXxmm
}, 0 },
8075 { "vphaddwq", { XM
, EXxmm
}, 0 },
8080 { "vphadddq", { XM
, EXxmm
}, 0 },
8087 { "vphaddubw", { XM
, EXxmm
}, 0 },
8088 { "vphaddubd", { XM
, EXxmm
}, 0 },
8089 { "vphaddubq", { XM
, EXxmm
}, 0 },
8092 { "vphadduwd", { XM
, EXxmm
}, 0 },
8093 { "vphadduwq", { XM
, EXxmm
}, 0 },
8098 { "vphaddudq", { XM
, EXxmm
}, 0 },
8105 { "vphsubbw", { XM
, EXxmm
}, 0 },
8106 { "vphsubwd", { XM
, EXxmm
}, 0 },
8107 { "vphsubdq", { XM
, EXxmm
}, 0 },
8161 { "bextrS", { Gdq
, Edq
, Id
}, 0 },
8163 { REG_TABLE (REG_XOP_LWP
) },
8433 static const struct dis386 vex_table
[][256] = {
8455 { PREFIX_TABLE (PREFIX_VEX_0F10
) },
8456 { PREFIX_TABLE (PREFIX_VEX_0F11
) },
8457 { PREFIX_TABLE (PREFIX_VEX_0F12
) },
8458 { MOD_TABLE (MOD_VEX_0F13
) },
8459 { "vunpcklpX", { XM
, Vex
, EXx
}, 0 },
8460 { "vunpckhpX", { XM
, Vex
, EXx
}, 0 },
8461 { PREFIX_TABLE (PREFIX_VEX_0F16
) },
8462 { MOD_TABLE (MOD_VEX_0F17
) },
8482 { "vmovapX", { XM
, EXx
}, 0 },
8483 { "vmovapX", { EXxS
, XM
}, 0 },
8484 { PREFIX_TABLE (PREFIX_VEX_0F2A
) },
8485 { MOD_TABLE (MOD_VEX_0F2B
) },
8486 { PREFIX_TABLE (PREFIX_VEX_0F2C
) },
8487 { PREFIX_TABLE (PREFIX_VEX_0F2D
) },
8488 { PREFIX_TABLE (PREFIX_VEX_0F2E
) },
8489 { PREFIX_TABLE (PREFIX_VEX_0F2F
) },
8510 { PREFIX_TABLE (PREFIX_VEX_0F41
) },
8511 { PREFIX_TABLE (PREFIX_VEX_0F42
) },
8513 { PREFIX_TABLE (PREFIX_VEX_0F44
) },
8514 { PREFIX_TABLE (PREFIX_VEX_0F45
) },
8515 { PREFIX_TABLE (PREFIX_VEX_0F46
) },
8516 { PREFIX_TABLE (PREFIX_VEX_0F47
) },
8520 { PREFIX_TABLE (PREFIX_VEX_0F4A
) },
8521 { PREFIX_TABLE (PREFIX_VEX_0F4B
) },
8527 { MOD_TABLE (MOD_VEX_0F50
) },
8528 { PREFIX_TABLE (PREFIX_VEX_0F51
) },
8529 { PREFIX_TABLE (PREFIX_VEX_0F52
) },
8530 { PREFIX_TABLE (PREFIX_VEX_0F53
) },
8531 { "vandpX", { XM
, Vex
, EXx
}, 0 },
8532 { "vandnpX", { XM
, Vex
, EXx
}, 0 },
8533 { "vorpX", { XM
, Vex
, EXx
}, 0 },
8534 { "vxorpX", { XM
, Vex
, EXx
}, 0 },
8536 { PREFIX_TABLE (PREFIX_VEX_0F58
) },
8537 { PREFIX_TABLE (PREFIX_VEX_0F59
) },
8538 { PREFIX_TABLE (PREFIX_VEX_0F5A
) },
8539 { PREFIX_TABLE (PREFIX_VEX_0F5B
) },
8540 { PREFIX_TABLE (PREFIX_VEX_0F5C
) },
8541 { PREFIX_TABLE (PREFIX_VEX_0F5D
) },
8542 { PREFIX_TABLE (PREFIX_VEX_0F5E
) },
8543 { PREFIX_TABLE (PREFIX_VEX_0F5F
) },
8545 { PREFIX_TABLE (PREFIX_VEX_0F60
) },
8546 { PREFIX_TABLE (PREFIX_VEX_0F61
) },
8547 { PREFIX_TABLE (PREFIX_VEX_0F62
) },
8548 { PREFIX_TABLE (PREFIX_VEX_0F63
) },
8549 { PREFIX_TABLE (PREFIX_VEX_0F64
) },
8550 { PREFIX_TABLE (PREFIX_VEX_0F65
) },
8551 { PREFIX_TABLE (PREFIX_VEX_0F66
) },
8552 { PREFIX_TABLE (PREFIX_VEX_0F67
) },
8554 { PREFIX_TABLE (PREFIX_VEX_0F68
) },
8555 { PREFIX_TABLE (PREFIX_VEX_0F69
) },
8556 { PREFIX_TABLE (PREFIX_VEX_0F6A
) },
8557 { PREFIX_TABLE (PREFIX_VEX_0F6B
) },
8558 { PREFIX_TABLE (PREFIX_VEX_0F6C
) },
8559 { PREFIX_TABLE (PREFIX_VEX_0F6D
) },
8560 { PREFIX_TABLE (PREFIX_VEX_0F6E
) },
8561 { PREFIX_TABLE (PREFIX_VEX_0F6F
) },
8563 { PREFIX_TABLE (PREFIX_VEX_0F70
) },
8564 { REG_TABLE (REG_VEX_0F71
) },
8565 { REG_TABLE (REG_VEX_0F72
) },
8566 { REG_TABLE (REG_VEX_0F73
) },
8567 { PREFIX_TABLE (PREFIX_VEX_0F74
) },
8568 { PREFIX_TABLE (PREFIX_VEX_0F75
) },
8569 { PREFIX_TABLE (PREFIX_VEX_0F76
) },
8570 { PREFIX_TABLE (PREFIX_VEX_0F77
) },
8576 { PREFIX_TABLE (PREFIX_VEX_0F7C
) },
8577 { PREFIX_TABLE (PREFIX_VEX_0F7D
) },
8578 { PREFIX_TABLE (PREFIX_VEX_0F7E
) },
8579 { PREFIX_TABLE (PREFIX_VEX_0F7F
) },
8599 { PREFIX_TABLE (PREFIX_VEX_0F90
) },
8600 { PREFIX_TABLE (PREFIX_VEX_0F91
) },
8601 { PREFIX_TABLE (PREFIX_VEX_0F92
) },
8602 { PREFIX_TABLE (PREFIX_VEX_0F93
) },
8608 { PREFIX_TABLE (PREFIX_VEX_0F98
) },
8609 { PREFIX_TABLE (PREFIX_VEX_0F99
) },
8632 { REG_TABLE (REG_VEX_0FAE
) },
8655 { PREFIX_TABLE (PREFIX_VEX_0FC2
) },
8657 { PREFIX_TABLE (PREFIX_VEX_0FC4
) },
8658 { PREFIX_TABLE (PREFIX_VEX_0FC5
) },
8659 { "vshufpX", { XM
, Vex
, EXx
, Ib
}, 0 },
8671 { PREFIX_TABLE (PREFIX_VEX_0FD0
) },
8672 { PREFIX_TABLE (PREFIX_VEX_0FD1
) },
8673 { PREFIX_TABLE (PREFIX_VEX_0FD2
) },
8674 { PREFIX_TABLE (PREFIX_VEX_0FD3
) },
8675 { PREFIX_TABLE (PREFIX_VEX_0FD4
) },
8676 { PREFIX_TABLE (PREFIX_VEX_0FD5
) },
8677 { PREFIX_TABLE (PREFIX_VEX_0FD6
) },
8678 { PREFIX_TABLE (PREFIX_VEX_0FD7
) },
8680 { PREFIX_TABLE (PREFIX_VEX_0FD8
) },
8681 { PREFIX_TABLE (PREFIX_VEX_0FD9
) },
8682 { PREFIX_TABLE (PREFIX_VEX_0FDA
) },
8683 { PREFIX_TABLE (PREFIX_VEX_0FDB
) },
8684 { PREFIX_TABLE (PREFIX_VEX_0FDC
) },
8685 { PREFIX_TABLE (PREFIX_VEX_0FDD
) },
8686 { PREFIX_TABLE (PREFIX_VEX_0FDE
) },
8687 { PREFIX_TABLE (PREFIX_VEX_0FDF
) },
8689 { PREFIX_TABLE (PREFIX_VEX_0FE0
) },
8690 { PREFIX_TABLE (PREFIX_VEX_0FE1
) },
8691 { PREFIX_TABLE (PREFIX_VEX_0FE2
) },
8692 { PREFIX_TABLE (PREFIX_VEX_0FE3
) },
8693 { PREFIX_TABLE (PREFIX_VEX_0FE4
) },
8694 { PREFIX_TABLE (PREFIX_VEX_0FE5
) },
8695 { PREFIX_TABLE (PREFIX_VEX_0FE6
) },
8696 { PREFIX_TABLE (PREFIX_VEX_0FE7
) },
8698 { PREFIX_TABLE (PREFIX_VEX_0FE8
) },
8699 { PREFIX_TABLE (PREFIX_VEX_0FE9
) },
8700 { PREFIX_TABLE (PREFIX_VEX_0FEA
) },
8701 { PREFIX_TABLE (PREFIX_VEX_0FEB
) },
8702 { PREFIX_TABLE (PREFIX_VEX_0FEC
) },
8703 { PREFIX_TABLE (PREFIX_VEX_0FED
) },
8704 { PREFIX_TABLE (PREFIX_VEX_0FEE
) },
8705 { PREFIX_TABLE (PREFIX_VEX_0FEF
) },
8707 { PREFIX_TABLE (PREFIX_VEX_0FF0
) },
8708 { PREFIX_TABLE (PREFIX_VEX_0FF1
) },
8709 { PREFIX_TABLE (PREFIX_VEX_0FF2
) },
8710 { PREFIX_TABLE (PREFIX_VEX_0FF3
) },
8711 { PREFIX_TABLE (PREFIX_VEX_0FF4
) },
8712 { PREFIX_TABLE (PREFIX_VEX_0FF5
) },
8713 { PREFIX_TABLE (PREFIX_VEX_0FF6
) },
8714 { PREFIX_TABLE (PREFIX_VEX_0FF7
) },
8716 { PREFIX_TABLE (PREFIX_VEX_0FF8
) },
8717 { PREFIX_TABLE (PREFIX_VEX_0FF9
) },
8718 { PREFIX_TABLE (PREFIX_VEX_0FFA
) },
8719 { PREFIX_TABLE (PREFIX_VEX_0FFB
) },
8720 { PREFIX_TABLE (PREFIX_VEX_0FFC
) },
8721 { PREFIX_TABLE (PREFIX_VEX_0FFD
) },
8722 { PREFIX_TABLE (PREFIX_VEX_0FFE
) },
8728 { PREFIX_TABLE (PREFIX_VEX_0F3800
) },
8729 { PREFIX_TABLE (PREFIX_VEX_0F3801
) },
8730 { PREFIX_TABLE (PREFIX_VEX_0F3802
) },
8731 { PREFIX_TABLE (PREFIX_VEX_0F3803
) },
8732 { PREFIX_TABLE (PREFIX_VEX_0F3804
) },
8733 { PREFIX_TABLE (PREFIX_VEX_0F3805
) },
8734 { PREFIX_TABLE (PREFIX_VEX_0F3806
) },
8735 { PREFIX_TABLE (PREFIX_VEX_0F3807
) },
8737 { PREFIX_TABLE (PREFIX_VEX_0F3808
) },
8738 { PREFIX_TABLE (PREFIX_VEX_0F3809
) },
8739 { PREFIX_TABLE (PREFIX_VEX_0F380A
) },
8740 { PREFIX_TABLE (PREFIX_VEX_0F380B
) },
8741 { PREFIX_TABLE (PREFIX_VEX_0F380C
) },
8742 { PREFIX_TABLE (PREFIX_VEX_0F380D
) },
8743 { PREFIX_TABLE (PREFIX_VEX_0F380E
) },
8744 { PREFIX_TABLE (PREFIX_VEX_0F380F
) },
8749 { PREFIX_TABLE (PREFIX_VEX_0F3813
) },
8752 { PREFIX_TABLE (PREFIX_VEX_0F3816
) },
8753 { PREFIX_TABLE (PREFIX_VEX_0F3817
) },
8755 { PREFIX_TABLE (PREFIX_VEX_0F3818
) },
8756 { PREFIX_TABLE (PREFIX_VEX_0F3819
) },
8757 { PREFIX_TABLE (PREFIX_VEX_0F381A
) },
8759 { PREFIX_TABLE (PREFIX_VEX_0F381C
) },
8760 { PREFIX_TABLE (PREFIX_VEX_0F381D
) },
8761 { PREFIX_TABLE (PREFIX_VEX_0F381E
) },
8764 { PREFIX_TABLE (PREFIX_VEX_0F3820
) },
8765 { PREFIX_TABLE (PREFIX_VEX_0F3821
) },
8766 { PREFIX_TABLE (PREFIX_VEX_0F3822
) },
8767 { PREFIX_TABLE (PREFIX_VEX_0F3823
) },
8768 { PREFIX_TABLE (PREFIX_VEX_0F3824
) },
8769 { PREFIX_TABLE (PREFIX_VEX_0F3825
) },
8773 { PREFIX_TABLE (PREFIX_VEX_0F3828
) },
8774 { PREFIX_TABLE (PREFIX_VEX_0F3829
) },
8775 { PREFIX_TABLE (PREFIX_VEX_0F382A
) },
8776 { PREFIX_TABLE (PREFIX_VEX_0F382B
) },
8777 { PREFIX_TABLE (PREFIX_VEX_0F382C
) },
8778 { PREFIX_TABLE (PREFIX_VEX_0F382D
) },
8779 { PREFIX_TABLE (PREFIX_VEX_0F382E
) },
8780 { PREFIX_TABLE (PREFIX_VEX_0F382F
) },
8782 { PREFIX_TABLE (PREFIX_VEX_0F3830
) },
8783 { PREFIX_TABLE (PREFIX_VEX_0F3831
) },
8784 { PREFIX_TABLE (PREFIX_VEX_0F3832
) },
8785 { PREFIX_TABLE (PREFIX_VEX_0F3833
) },
8786 { PREFIX_TABLE (PREFIX_VEX_0F3834
) },
8787 { PREFIX_TABLE (PREFIX_VEX_0F3835
) },
8788 { PREFIX_TABLE (PREFIX_VEX_0F3836
) },
8789 { PREFIX_TABLE (PREFIX_VEX_0F3837
) },
8791 { PREFIX_TABLE (PREFIX_VEX_0F3838
) },
8792 { PREFIX_TABLE (PREFIX_VEX_0F3839
) },
8793 { PREFIX_TABLE (PREFIX_VEX_0F383A
) },
8794 { PREFIX_TABLE (PREFIX_VEX_0F383B
) },
8795 { PREFIX_TABLE (PREFIX_VEX_0F383C
) },
8796 { PREFIX_TABLE (PREFIX_VEX_0F383D
) },
8797 { PREFIX_TABLE (PREFIX_VEX_0F383E
) },
8798 { PREFIX_TABLE (PREFIX_VEX_0F383F
) },
8800 { PREFIX_TABLE (PREFIX_VEX_0F3840
) },
8801 { PREFIX_TABLE (PREFIX_VEX_0F3841
) },
8805 { PREFIX_TABLE (PREFIX_VEX_0F3845
) },
8806 { PREFIX_TABLE (PREFIX_VEX_0F3846
) },
8807 { PREFIX_TABLE (PREFIX_VEX_0F3847
) },
8827 { PREFIX_TABLE (PREFIX_VEX_0F3858
) },
8828 { PREFIX_TABLE (PREFIX_VEX_0F3859
) },
8829 { PREFIX_TABLE (PREFIX_VEX_0F385A
) },
8863 { PREFIX_TABLE (PREFIX_VEX_0F3878
) },
8864 { PREFIX_TABLE (PREFIX_VEX_0F3879
) },
8885 { PREFIX_TABLE (PREFIX_VEX_0F388C
) },
8887 { PREFIX_TABLE (PREFIX_VEX_0F388E
) },
8890 { PREFIX_TABLE (PREFIX_VEX_0F3890
) },
8891 { PREFIX_TABLE (PREFIX_VEX_0F3891
) },
8892 { PREFIX_TABLE (PREFIX_VEX_0F3892
) },
8893 { PREFIX_TABLE (PREFIX_VEX_0F3893
) },
8896 { PREFIX_TABLE (PREFIX_VEX_0F3896
) },
8897 { PREFIX_TABLE (PREFIX_VEX_0F3897
) },
8899 { PREFIX_TABLE (PREFIX_VEX_0F3898
) },
8900 { PREFIX_TABLE (PREFIX_VEX_0F3899
) },
8901 { PREFIX_TABLE (PREFIX_VEX_0F389A
) },
8902 { PREFIX_TABLE (PREFIX_VEX_0F389B
) },
8903 { PREFIX_TABLE (PREFIX_VEX_0F389C
) },
8904 { PREFIX_TABLE (PREFIX_VEX_0F389D
) },
8905 { PREFIX_TABLE (PREFIX_VEX_0F389E
) },
8906 { PREFIX_TABLE (PREFIX_VEX_0F389F
) },
8914 { PREFIX_TABLE (PREFIX_VEX_0F38A6
) },
8915 { PREFIX_TABLE (PREFIX_VEX_0F38A7
) },
8917 { PREFIX_TABLE (PREFIX_VEX_0F38A8
) },
8918 { PREFIX_TABLE (PREFIX_VEX_0F38A9
) },
8919 { PREFIX_TABLE (PREFIX_VEX_0F38AA
) },
8920 { PREFIX_TABLE (PREFIX_VEX_0F38AB
) },
8921 { PREFIX_TABLE (PREFIX_VEX_0F38AC
) },
8922 { PREFIX_TABLE (PREFIX_VEX_0F38AD
) },
8923 { PREFIX_TABLE (PREFIX_VEX_0F38AE
) },
8924 { PREFIX_TABLE (PREFIX_VEX_0F38AF
) },
8932 { PREFIX_TABLE (PREFIX_VEX_0F38B6
) },
8933 { PREFIX_TABLE (PREFIX_VEX_0F38B7
) },
8935 { PREFIX_TABLE (PREFIX_VEX_0F38B8
) },
8936 { PREFIX_TABLE (PREFIX_VEX_0F38B9
) },
8937 { PREFIX_TABLE (PREFIX_VEX_0F38BA
) },
8938 { PREFIX_TABLE (PREFIX_VEX_0F38BB
) },
8939 { PREFIX_TABLE (PREFIX_VEX_0F38BC
) },
8940 { PREFIX_TABLE (PREFIX_VEX_0F38BD
) },
8941 { PREFIX_TABLE (PREFIX_VEX_0F38BE
) },
8942 { PREFIX_TABLE (PREFIX_VEX_0F38BF
) },
8960 { PREFIX_TABLE (PREFIX_VEX_0F38CF
) },
8974 { PREFIX_TABLE (PREFIX_VEX_0F38DB
) },
8975 { PREFIX_TABLE (PREFIX_VEX_0F38DC
) },
8976 { PREFIX_TABLE (PREFIX_VEX_0F38DD
) },
8977 { PREFIX_TABLE (PREFIX_VEX_0F38DE
) },
8978 { PREFIX_TABLE (PREFIX_VEX_0F38DF
) },
9000 { PREFIX_TABLE (PREFIX_VEX_0F38F2
) },
9001 { REG_TABLE (REG_VEX_0F38F3
) },
9003 { PREFIX_TABLE (PREFIX_VEX_0F38F5
) },
9004 { PREFIX_TABLE (PREFIX_VEX_0F38F6
) },
9005 { PREFIX_TABLE (PREFIX_VEX_0F38F7
) },
9019 { PREFIX_TABLE (PREFIX_VEX_0F3A00
) },
9020 { PREFIX_TABLE (PREFIX_VEX_0F3A01
) },
9021 { PREFIX_TABLE (PREFIX_VEX_0F3A02
) },
9023 { PREFIX_TABLE (PREFIX_VEX_0F3A04
) },
9024 { PREFIX_TABLE (PREFIX_VEX_0F3A05
) },
9025 { PREFIX_TABLE (PREFIX_VEX_0F3A06
) },
9028 { PREFIX_TABLE (PREFIX_VEX_0F3A08
) },
9029 { PREFIX_TABLE (PREFIX_VEX_0F3A09
) },
9030 { PREFIX_TABLE (PREFIX_VEX_0F3A0A
) },
9031 { PREFIX_TABLE (PREFIX_VEX_0F3A0B
) },
9032 { PREFIX_TABLE (PREFIX_VEX_0F3A0C
) },
9033 { PREFIX_TABLE (PREFIX_VEX_0F3A0D
) },
9034 { PREFIX_TABLE (PREFIX_VEX_0F3A0E
) },
9035 { PREFIX_TABLE (PREFIX_VEX_0F3A0F
) },
9041 { PREFIX_TABLE (PREFIX_VEX_0F3A14
) },
9042 { PREFIX_TABLE (PREFIX_VEX_0F3A15
) },
9043 { PREFIX_TABLE (PREFIX_VEX_0F3A16
) },
9044 { PREFIX_TABLE (PREFIX_VEX_0F3A17
) },
9046 { PREFIX_TABLE (PREFIX_VEX_0F3A18
) },
9047 { PREFIX_TABLE (PREFIX_VEX_0F3A19
) },
9051 { PREFIX_TABLE (PREFIX_VEX_0F3A1D
) },
9055 { PREFIX_TABLE (PREFIX_VEX_0F3A20
) },
9056 { PREFIX_TABLE (PREFIX_VEX_0F3A21
) },
9057 { PREFIX_TABLE (PREFIX_VEX_0F3A22
) },
9073 { PREFIX_TABLE (PREFIX_VEX_0F3A30
) },
9074 { PREFIX_TABLE (PREFIX_VEX_0F3A31
) },
9075 { PREFIX_TABLE (PREFIX_VEX_0F3A32
) },
9076 { PREFIX_TABLE (PREFIX_VEX_0F3A33
) },
9082 { PREFIX_TABLE (PREFIX_VEX_0F3A38
) },
9083 { PREFIX_TABLE (PREFIX_VEX_0F3A39
) },
9091 { PREFIX_TABLE (PREFIX_VEX_0F3A40
) },
9092 { PREFIX_TABLE (PREFIX_VEX_0F3A41
) },
9093 { PREFIX_TABLE (PREFIX_VEX_0F3A42
) },
9095 { PREFIX_TABLE (PREFIX_VEX_0F3A44
) },
9097 { PREFIX_TABLE (PREFIX_VEX_0F3A46
) },
9100 { PREFIX_TABLE (PREFIX_VEX_0F3A48
) },
9101 { PREFIX_TABLE (PREFIX_VEX_0F3A49
) },
9102 { PREFIX_TABLE (PREFIX_VEX_0F3A4A
) },
9103 { PREFIX_TABLE (PREFIX_VEX_0F3A4B
) },
9104 { PREFIX_TABLE (PREFIX_VEX_0F3A4C
) },
9122 { PREFIX_TABLE (PREFIX_VEX_0F3A5C
) },
9123 { PREFIX_TABLE (PREFIX_VEX_0F3A5D
) },
9124 { PREFIX_TABLE (PREFIX_VEX_0F3A5E
) },
9125 { PREFIX_TABLE (PREFIX_VEX_0F3A5F
) },
9127 { PREFIX_TABLE (PREFIX_VEX_0F3A60
) },
9128 { PREFIX_TABLE (PREFIX_VEX_0F3A61
) },
9129 { PREFIX_TABLE (PREFIX_VEX_0F3A62
) },
9130 { PREFIX_TABLE (PREFIX_VEX_0F3A63
) },
9136 { PREFIX_TABLE (PREFIX_VEX_0F3A68
) },
9137 { PREFIX_TABLE (PREFIX_VEX_0F3A69
) },
9138 { PREFIX_TABLE (PREFIX_VEX_0F3A6A
) },
9139 { PREFIX_TABLE (PREFIX_VEX_0F3A6B
) },
9140 { PREFIX_TABLE (PREFIX_VEX_0F3A6C
) },
9141 { PREFIX_TABLE (PREFIX_VEX_0F3A6D
) },
9142 { PREFIX_TABLE (PREFIX_VEX_0F3A6E
) },
9143 { PREFIX_TABLE (PREFIX_VEX_0F3A6F
) },
9154 { PREFIX_TABLE (PREFIX_VEX_0F3A78
) },
9155 { PREFIX_TABLE (PREFIX_VEX_0F3A79
) },
9156 { PREFIX_TABLE (PREFIX_VEX_0F3A7A
) },
9157 { PREFIX_TABLE (PREFIX_VEX_0F3A7B
) },
9158 { PREFIX_TABLE (PREFIX_VEX_0F3A7C
) },
9159 { PREFIX_TABLE (PREFIX_VEX_0F3A7D
) },
9160 { PREFIX_TABLE (PREFIX_VEX_0F3A7E
) },
9161 { PREFIX_TABLE (PREFIX_VEX_0F3A7F
) },
9250 { PREFIX_TABLE(PREFIX_VEX_0F3ACE
) },
9251 { PREFIX_TABLE(PREFIX_VEX_0F3ACF
) },
9269 { PREFIX_TABLE (PREFIX_VEX_0F3ADF
) },
9289 { PREFIX_TABLE (PREFIX_VEX_0F3AF0
) },
9309 #include "i386-dis-evex.h"
9311 static const struct dis386 vex_len_table
[][2] = {
9312 /* VEX_LEN_0F12_P_0_M_0 */
9314 { "vmovlps", { XM
, Vex128
, EXq
}, 0 },
9317 /* VEX_LEN_0F12_P_0_M_1 */
9319 { "vmovhlps", { XM
, Vex128
, EXq
}, 0 },
9322 /* VEX_LEN_0F12_P_2 */
9324 { "vmovlpd", { XM
, Vex128
, EXq
}, 0 },
9327 /* VEX_LEN_0F13_M_0 */
9329 { "vmovlpX", { EXq
, XM
}, 0 },
9332 /* VEX_LEN_0F16_P_0_M_0 */
9334 { "vmovhps", { XM
, Vex128
, EXq
}, 0 },
9337 /* VEX_LEN_0F16_P_0_M_1 */
9339 { "vmovlhps", { XM
, Vex128
, EXq
}, 0 },
9342 /* VEX_LEN_0F16_P_2 */
9344 { "vmovhpd", { XM
, Vex128
, EXq
}, 0 },
9347 /* VEX_LEN_0F17_M_0 */
9349 { "vmovhpX", { EXq
, XM
}, 0 },
9352 /* VEX_LEN_0F41_P_0 */
9355 { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1
) },
9357 /* VEX_LEN_0F41_P_2 */
9360 { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1
) },
9362 /* VEX_LEN_0F42_P_0 */
9365 { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1
) },
9367 /* VEX_LEN_0F42_P_2 */
9370 { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1
) },
9372 /* VEX_LEN_0F44_P_0 */
9374 { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0
) },
9376 /* VEX_LEN_0F44_P_2 */
9378 { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0
) },
9380 /* VEX_LEN_0F45_P_0 */
9383 { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1
) },
9385 /* VEX_LEN_0F45_P_2 */
9388 { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1
) },
9390 /* VEX_LEN_0F46_P_0 */
9393 { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1
) },
9395 /* VEX_LEN_0F46_P_2 */
9398 { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1
) },
9400 /* VEX_LEN_0F47_P_0 */
9403 { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1
) },
9405 /* VEX_LEN_0F47_P_2 */
9408 { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1
) },
9410 /* VEX_LEN_0F4A_P_0 */
9413 { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1
) },
9415 /* VEX_LEN_0F4A_P_2 */
9418 { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1
) },
9420 /* VEX_LEN_0F4B_P_0 */
9423 { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1
) },
9425 /* VEX_LEN_0F4B_P_2 */
9428 { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1
) },
9431 /* VEX_LEN_0F6E_P_2 */
9433 { "vmovK", { XMScalar
, Edq
}, 0 },
9436 /* VEX_LEN_0F77_P_1 */
9438 { "vzeroupper", { XX
}, 0 },
9439 { "vzeroall", { XX
}, 0 },
9442 /* VEX_LEN_0F7E_P_1 */
9444 { "vmovq", { XMScalar
, EXqScalar
}, 0 },
9447 /* VEX_LEN_0F7E_P_2 */
9449 { "vmovK", { Edq
, XMScalar
}, 0 },
9452 /* VEX_LEN_0F90_P_0 */
9454 { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0
) },
9457 /* VEX_LEN_0F90_P_2 */
9459 { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0
) },
9462 /* VEX_LEN_0F91_P_0 */
9464 { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0
) },
9467 /* VEX_LEN_0F91_P_2 */
9469 { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0
) },
9472 /* VEX_LEN_0F92_P_0 */
9474 { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0
) },
9477 /* VEX_LEN_0F92_P_2 */
9479 { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0
) },
9482 /* VEX_LEN_0F92_P_3 */
9484 { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0
) },
9487 /* VEX_LEN_0F93_P_0 */
9489 { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0
) },
9492 /* VEX_LEN_0F93_P_2 */
9494 { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0
) },
9497 /* VEX_LEN_0F93_P_3 */
9499 { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0
) },
9502 /* VEX_LEN_0F98_P_0 */
9504 { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0
) },
9507 /* VEX_LEN_0F98_P_2 */
9509 { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0
) },
9512 /* VEX_LEN_0F99_P_0 */
9514 { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0
) },
9517 /* VEX_LEN_0F99_P_2 */
9519 { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0
) },
9522 /* VEX_LEN_0FAE_R_2_M_0 */
9524 { "vldmxcsr", { Md
}, 0 },
9527 /* VEX_LEN_0FAE_R_3_M_0 */
9529 { "vstmxcsr", { Md
}, 0 },
9532 /* VEX_LEN_0FC4_P_2 */
9534 { "vpinsrw", { XM
, Vex128
, Edqw
, Ib
}, 0 },
9537 /* VEX_LEN_0FC5_P_2 */
9539 { "vpextrw", { Gdq
, XS
, Ib
}, 0 },
9542 /* VEX_LEN_0FD6_P_2 */
9544 { "vmovq", { EXqScalarS
, XMScalar
}, 0 },
9547 /* VEX_LEN_0FF7_P_2 */
9549 { "vmaskmovdqu", { XM
, XS
}, 0 },
9552 /* VEX_LEN_0F3816_P_2 */
9555 { VEX_W_TABLE (VEX_W_0F3816_P_2
) },
9558 /* VEX_LEN_0F3819_P_2 */
9561 { VEX_W_TABLE (VEX_W_0F3819_P_2
) },
9564 /* VEX_LEN_0F381A_P_2_M_0 */
9567 { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0
) },
9570 /* VEX_LEN_0F3836_P_2 */
9573 { VEX_W_TABLE (VEX_W_0F3836_P_2
) },
9576 /* VEX_LEN_0F3841_P_2 */
9578 { "vphminposuw", { XM
, EXx
}, 0 },
9581 /* VEX_LEN_0F385A_P_2_M_0 */
9584 { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0
) },
9587 /* VEX_LEN_0F38DB_P_2 */
9589 { "vaesimc", { XM
, EXx
}, 0 },
9592 /* VEX_LEN_0F38F2_P_0 */
9594 { "andnS", { Gdq
, VexGdq
, Edq
}, 0 },
9597 /* VEX_LEN_0F38F3_R_1_P_0 */
9599 { "blsrS", { VexGdq
, Edq
}, 0 },
9602 /* VEX_LEN_0F38F3_R_2_P_0 */
9604 { "blsmskS", { VexGdq
, Edq
}, 0 },
9607 /* VEX_LEN_0F38F3_R_3_P_0 */
9609 { "blsiS", { VexGdq
, Edq
}, 0 },
9612 /* VEX_LEN_0F38F5_P_0 */
9614 { "bzhiS", { Gdq
, Edq
, VexGdq
}, 0 },
9617 /* VEX_LEN_0F38F5_P_1 */
9619 { "pextS", { Gdq
, VexGdq
, Edq
}, 0 },
9622 /* VEX_LEN_0F38F5_P_3 */
9624 { "pdepS", { Gdq
, VexGdq
, Edq
}, 0 },
9627 /* VEX_LEN_0F38F6_P_3 */
9629 { "mulxS", { Gdq
, VexGdq
, Edq
}, 0 },
9632 /* VEX_LEN_0F38F7_P_0 */
9634 { "bextrS", { Gdq
, Edq
, VexGdq
}, 0 },
9637 /* VEX_LEN_0F38F7_P_1 */
9639 { "sarxS", { Gdq
, Edq
, VexGdq
}, 0 },
9642 /* VEX_LEN_0F38F7_P_2 */
9644 { "shlxS", { Gdq
, Edq
, VexGdq
}, 0 },
9647 /* VEX_LEN_0F38F7_P_3 */
9649 { "shrxS", { Gdq
, Edq
, VexGdq
}, 0 },
9652 /* VEX_LEN_0F3A00_P_2 */
9655 { VEX_W_TABLE (VEX_W_0F3A00_P_2
) },
9658 /* VEX_LEN_0F3A01_P_2 */
9661 { VEX_W_TABLE (VEX_W_0F3A01_P_2
) },
9664 /* VEX_LEN_0F3A06_P_2 */
9667 { VEX_W_TABLE (VEX_W_0F3A06_P_2
) },
9670 /* VEX_LEN_0F3A14_P_2 */
9672 { "vpextrb", { Edqb
, XM
, Ib
}, 0 },
9675 /* VEX_LEN_0F3A15_P_2 */
9677 { "vpextrw", { Edqw
, XM
, Ib
}, 0 },
9680 /* VEX_LEN_0F3A16_P_2 */
9682 { "vpextrK", { Edq
, XM
, Ib
}, 0 },
9685 /* VEX_LEN_0F3A17_P_2 */
9687 { "vextractps", { Edqd
, XM
, Ib
}, 0 },
9690 /* VEX_LEN_0F3A18_P_2 */
9693 { VEX_W_TABLE (VEX_W_0F3A18_P_2
) },
9696 /* VEX_LEN_0F3A19_P_2 */
9699 { VEX_W_TABLE (VEX_W_0F3A19_P_2
) },
9702 /* VEX_LEN_0F3A20_P_2 */
9704 { "vpinsrb", { XM
, Vex128
, Edqb
, Ib
}, 0 },
9707 /* VEX_LEN_0F3A21_P_2 */
9709 { "vinsertps", { XM
, Vex128
, EXd
, Ib
}, 0 },
9712 /* VEX_LEN_0F3A22_P_2 */
9714 { "vpinsrK", { XM
, Vex128
, Edq
, Ib
}, 0 },
9717 /* VEX_LEN_0F3A30_P_2 */
9719 { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0
) },
9722 /* VEX_LEN_0F3A31_P_2 */
9724 { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0
) },
9727 /* VEX_LEN_0F3A32_P_2 */
9729 { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0
) },
9732 /* VEX_LEN_0F3A33_P_2 */
9734 { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0
) },
9737 /* VEX_LEN_0F3A38_P_2 */
9740 { VEX_W_TABLE (VEX_W_0F3A38_P_2
) },
9743 /* VEX_LEN_0F3A39_P_2 */
9746 { VEX_W_TABLE (VEX_W_0F3A39_P_2
) },
9749 /* VEX_LEN_0F3A41_P_2 */
9751 { "vdppd", { XM
, Vex128
, EXx
, Ib
}, 0 },
9754 /* VEX_LEN_0F3A46_P_2 */
9757 { VEX_W_TABLE (VEX_W_0F3A46_P_2
) },
9760 /* VEX_LEN_0F3A60_P_2 */
9762 { "vpcmpestrm", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, 0 },
9765 /* VEX_LEN_0F3A61_P_2 */
9767 { "vpcmpestri", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, 0 },
9770 /* VEX_LEN_0F3A62_P_2 */
9772 { "vpcmpistrm", { XM
, EXx
, Ib
}, 0 },
9775 /* VEX_LEN_0F3A63_P_2 */
9777 { "vpcmpistri", { XM
, EXx
, Ib
}, 0 },
9780 /* VEX_LEN_0F3A6A_P_2 */
9782 { "vfmaddss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
}, 0 },
9785 /* VEX_LEN_0F3A6B_P_2 */
9787 { "vfmaddsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
}, 0 },
9790 /* VEX_LEN_0F3A6E_P_2 */
9792 { "vfmsubss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
}, 0 },
9795 /* VEX_LEN_0F3A6F_P_2 */
9797 { "vfmsubsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
}, 0 },
9800 /* VEX_LEN_0F3A7A_P_2 */
9802 { "vfnmaddss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
}, 0 },
9805 /* VEX_LEN_0F3A7B_P_2 */
9807 { "vfnmaddsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
}, 0 },
9810 /* VEX_LEN_0F3A7E_P_2 */
9812 { "vfnmsubss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
}, 0 },
9815 /* VEX_LEN_0F3A7F_P_2 */
9817 { "vfnmsubsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
}, 0 },
9820 /* VEX_LEN_0F3ADF_P_2 */
9822 { "vaeskeygenassist", { XM
, EXx
, Ib
}, 0 },
9825 /* VEX_LEN_0F3AF0_P_3 */
9827 { "rorxS", { Gdq
, Edq
, Ib
}, 0 },
9830 /* VEX_LEN_0FXOP_08_CC */
9832 { "vpcomb", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9835 /* VEX_LEN_0FXOP_08_CD */
9837 { "vpcomw", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9840 /* VEX_LEN_0FXOP_08_CE */
9842 { "vpcomd", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9845 /* VEX_LEN_0FXOP_08_CF */
9847 { "vpcomq", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9850 /* VEX_LEN_0FXOP_08_EC */
9852 { "vpcomub", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9855 /* VEX_LEN_0FXOP_08_ED */
9857 { "vpcomuw", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9860 /* VEX_LEN_0FXOP_08_EE */
9862 { "vpcomud", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9865 /* VEX_LEN_0FXOP_08_EF */
9867 { "vpcomuq", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9870 /* VEX_LEN_0FXOP_09_80 */
9872 { "vfrczps", { XM
, EXxmm
}, 0 },
9873 { "vfrczps", { XM
, EXymmq
}, 0 },
9876 /* VEX_LEN_0FXOP_09_81 */
9878 { "vfrczpd", { XM
, EXxmm
}, 0 },
9879 { "vfrczpd", { XM
, EXymmq
}, 0 },
9883 #include "i386-dis-evex-len.h"
9885 static const struct dis386 vex_w_table
[][2] = {
9887 /* VEX_W_0F41_P_0_LEN_1 */
9888 { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1
) },
9889 { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1
) },
9892 /* VEX_W_0F41_P_2_LEN_1 */
9893 { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1
) },
9894 { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1
) }
9897 /* VEX_W_0F42_P_0_LEN_1 */
9898 { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1
) },
9899 { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1
) },
9902 /* VEX_W_0F42_P_2_LEN_1 */
9903 { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1
) },
9904 { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1
) },
9907 /* VEX_W_0F44_P_0_LEN_0 */
9908 { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1
) },
9909 { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1
) },
9912 /* VEX_W_0F44_P_2_LEN_0 */
9913 { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1
) },
9914 { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1
) },
9917 /* VEX_W_0F45_P_0_LEN_1 */
9918 { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1
) },
9919 { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1
) },
9922 /* VEX_W_0F45_P_2_LEN_1 */
9923 { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1
) },
9924 { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1
) },
9927 /* VEX_W_0F46_P_0_LEN_1 */
9928 { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1
) },
9929 { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1
) },
9932 /* VEX_W_0F46_P_2_LEN_1 */
9933 { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1
) },
9934 { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1
) },
9937 /* VEX_W_0F47_P_0_LEN_1 */
9938 { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1
) },
9939 { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1
) },
9942 /* VEX_W_0F47_P_2_LEN_1 */
9943 { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1
) },
9944 { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1
) },
9947 /* VEX_W_0F4A_P_0_LEN_1 */
9948 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1
) },
9949 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1
) },
9952 /* VEX_W_0F4A_P_2_LEN_1 */
9953 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1
) },
9954 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1
) },
9957 /* VEX_W_0F4B_P_0_LEN_1 */
9958 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1
) },
9959 { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1
) },
9962 /* VEX_W_0F4B_P_2_LEN_1 */
9963 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1
) },
9966 /* VEX_W_0F90_P_0_LEN_0 */
9967 { "kmovw", { MaskG
, MaskE
}, 0 },
9968 { "kmovq", { MaskG
, MaskE
}, 0 },
9971 /* VEX_W_0F90_P_2_LEN_0 */
9972 { "kmovb", { MaskG
, MaskBDE
}, 0 },
9973 { "kmovd", { MaskG
, MaskBDE
}, 0 },
9976 /* VEX_W_0F91_P_0_LEN_0 */
9977 { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0
) },
9978 { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0
) },
9981 /* VEX_W_0F91_P_2_LEN_0 */
9982 { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0
) },
9983 { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0
) },
9986 /* VEX_W_0F92_P_0_LEN_0 */
9987 { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0
) },
9990 /* VEX_W_0F92_P_2_LEN_0 */
9991 { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0
) },
9994 /* VEX_W_0F93_P_0_LEN_0 */
9995 { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0
) },
9998 /* VEX_W_0F93_P_2_LEN_0 */
9999 { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0
) },
10002 /* VEX_W_0F98_P_0_LEN_0 */
10003 { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0
) },
10004 { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0
) },
10007 /* VEX_W_0F98_P_2_LEN_0 */
10008 { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0
) },
10009 { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0
) },
10012 /* VEX_W_0F99_P_0_LEN_0 */
10013 { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0
) },
10014 { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0
) },
10017 /* VEX_W_0F99_P_2_LEN_0 */
10018 { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0
) },
10019 { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0
) },
10022 /* VEX_W_0F380C_P_2 */
10023 { "vpermilps", { XM
, Vex
, EXx
}, 0 },
10026 /* VEX_W_0F380D_P_2 */
10027 { "vpermilpd", { XM
, Vex
, EXx
}, 0 },
10030 /* VEX_W_0F380E_P_2 */
10031 { "vtestps", { XM
, EXx
}, 0 },
10034 /* VEX_W_0F380F_P_2 */
10035 { "vtestpd", { XM
, EXx
}, 0 },
10038 /* VEX_W_0F3816_P_2 */
10039 { "vpermps", { XM
, Vex
, EXx
}, 0 },
10042 /* VEX_W_0F3818_P_2 */
10043 { "vbroadcastss", { XM
, EXxmm_md
}, 0 },
10046 /* VEX_W_0F3819_P_2 */
10047 { "vbroadcastsd", { XM
, EXxmm_mq
}, 0 },
10050 /* VEX_W_0F381A_P_2_M_0 */
10051 { "vbroadcastf128", { XM
, Mxmm
}, 0 },
10054 /* VEX_W_0F382C_P_2_M_0 */
10055 { "vmaskmovps", { XM
, Vex
, Mx
}, 0 },
10058 /* VEX_W_0F382D_P_2_M_0 */
10059 { "vmaskmovpd", { XM
, Vex
, Mx
}, 0 },
10062 /* VEX_W_0F382E_P_2_M_0 */
10063 { "vmaskmovps", { Mx
, Vex
, XM
}, 0 },
10066 /* VEX_W_0F382F_P_2_M_0 */
10067 { "vmaskmovpd", { Mx
, Vex
, XM
}, 0 },
10070 /* VEX_W_0F3836_P_2 */
10071 { "vpermd", { XM
, Vex
, EXx
}, 0 },
10074 /* VEX_W_0F3846_P_2 */
10075 { "vpsravd", { XM
, Vex
, EXx
}, 0 },
10078 /* VEX_W_0F3858_P_2 */
10079 { "vpbroadcastd", { XM
, EXxmm_md
}, 0 },
10082 /* VEX_W_0F3859_P_2 */
10083 { "vpbroadcastq", { XM
, EXxmm_mq
}, 0 },
10086 /* VEX_W_0F385A_P_2_M_0 */
10087 { "vbroadcasti128", { XM
, Mxmm
}, 0 },
10090 /* VEX_W_0F3878_P_2 */
10091 { "vpbroadcastb", { XM
, EXxmm_mb
}, 0 },
10094 /* VEX_W_0F3879_P_2 */
10095 { "vpbroadcastw", { XM
, EXxmm_mw
}, 0 },
10098 /* VEX_W_0F38CF_P_2 */
10099 { "vgf2p8mulb", { XM
, Vex
, EXx
}, 0 },
10102 /* VEX_W_0F3A00_P_2 */
10104 { "vpermq", { XM
, EXx
, Ib
}, 0 },
10107 /* VEX_W_0F3A01_P_2 */
10109 { "vpermpd", { XM
, EXx
, Ib
}, 0 },
10112 /* VEX_W_0F3A02_P_2 */
10113 { "vpblendd", { XM
, Vex
, EXx
, Ib
}, 0 },
10116 /* VEX_W_0F3A04_P_2 */
10117 { "vpermilps", { XM
, EXx
, Ib
}, 0 },
10120 /* VEX_W_0F3A05_P_2 */
10121 { "vpermilpd", { XM
, EXx
, Ib
}, 0 },
10124 /* VEX_W_0F3A06_P_2 */
10125 { "vperm2f128", { XM
, Vex256
, EXx
, Ib
}, 0 },
10128 /* VEX_W_0F3A18_P_2 */
10129 { "vinsertf128", { XM
, Vex256
, EXxmm
, Ib
}, 0 },
10132 /* VEX_W_0F3A19_P_2 */
10133 { "vextractf128", { EXxmm
, XM
, Ib
}, 0 },
10136 /* VEX_W_0F3A30_P_2_LEN_0 */
10137 { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0
) },
10138 { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0
) },
10141 /* VEX_W_0F3A31_P_2_LEN_0 */
10142 { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0
) },
10143 { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0
) },
10146 /* VEX_W_0F3A32_P_2_LEN_0 */
10147 { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0
) },
10148 { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0
) },
10151 /* VEX_W_0F3A33_P_2_LEN_0 */
10152 { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0
) },
10153 { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0
) },
10156 /* VEX_W_0F3A38_P_2 */
10157 { "vinserti128", { XM
, Vex256
, EXxmm
, Ib
}, 0 },
10160 /* VEX_W_0F3A39_P_2 */
10161 { "vextracti128", { EXxmm
, XM
, Ib
}, 0 },
10164 /* VEX_W_0F3A46_P_2 */
10165 { "vperm2i128", { XM
, Vex256
, EXx
, Ib
}, 0 },
10168 /* VEX_W_0F3A48_P_2 */
10169 { "vpermil2ps", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
10170 { "vpermil2ps", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
10173 /* VEX_W_0F3A49_P_2 */
10174 { "vpermil2pd", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
10175 { "vpermil2pd", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
10178 /* VEX_W_0F3A4A_P_2 */
10179 { "vblendvps", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10182 /* VEX_W_0F3A4B_P_2 */
10183 { "vblendvpd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10186 /* VEX_W_0F3A4C_P_2 */
10187 { "vpblendvb", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10190 /* VEX_W_0F3ACE_P_2 */
10192 { "vgf2p8affineqb", { XM
, Vex
, EXx
, Ib
}, 0 },
10195 /* VEX_W_0F3ACF_P_2 */
10197 { "vgf2p8affineinvqb", { XM
, Vex
, EXx
, Ib
}, 0 },
10200 #include "i386-dis-evex-w.h"
10203 static const struct dis386 mod_table
[][2] = {
10206 { "leaS", { Gv
, M
}, 0 },
10211 { RM_TABLE (RM_C6_REG_7
) },
10216 { RM_TABLE (RM_C7_REG_7
) },
10220 { "Jcall^", { indirEp
}, 0 },
10224 { "Jjmp^", { indirEp
}, 0 },
10227 /* MOD_0F01_REG_0 */
10228 { X86_64_TABLE (X86_64_0F01_REG_0
) },
10229 { RM_TABLE (RM_0F01_REG_0
) },
10232 /* MOD_0F01_REG_1 */
10233 { X86_64_TABLE (X86_64_0F01_REG_1
) },
10234 { RM_TABLE (RM_0F01_REG_1
) },
10237 /* MOD_0F01_REG_2 */
10238 { X86_64_TABLE (X86_64_0F01_REG_2
) },
10239 { RM_TABLE (RM_0F01_REG_2
) },
10242 /* MOD_0F01_REG_3 */
10243 { X86_64_TABLE (X86_64_0F01_REG_3
) },
10244 { RM_TABLE (RM_0F01_REG_3
) },
10247 /* MOD_0F01_REG_5 */
10248 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0
) },
10249 { RM_TABLE (RM_0F01_REG_5_MOD_3
) },
10252 /* MOD_0F01_REG_7 */
10253 { "invlpg", { Mb
}, 0 },
10254 { RM_TABLE (RM_0F01_REG_7_MOD_3
) },
10257 /* MOD_0F12_PREFIX_0 */
10258 { "movlps", { XM
, EXq
}, PREFIX_OPCODE
},
10259 { "movhlps", { XM
, EXq
}, PREFIX_OPCODE
},
10263 { "movlpX", { EXq
, XM
}, PREFIX_OPCODE
},
10266 /* MOD_0F16_PREFIX_0 */
10267 { "movhps", { XM
, EXq
}, 0 },
10268 { "movlhps", { XM
, EXq
}, 0 },
10272 { "movhpX", { EXq
, XM
}, PREFIX_OPCODE
},
10275 /* MOD_0F18_REG_0 */
10276 { "prefetchnta", { Mb
}, 0 },
10279 /* MOD_0F18_REG_1 */
10280 { "prefetcht0", { Mb
}, 0 },
10283 /* MOD_0F18_REG_2 */
10284 { "prefetcht1", { Mb
}, 0 },
10287 /* MOD_0F18_REG_3 */
10288 { "prefetcht2", { Mb
}, 0 },
10291 /* MOD_0F18_REG_4 */
10292 { "nop/reserved", { Mb
}, 0 },
10295 /* MOD_0F18_REG_5 */
10296 { "nop/reserved", { Mb
}, 0 },
10299 /* MOD_0F18_REG_6 */
10300 { "nop/reserved", { Mb
}, 0 },
10303 /* MOD_0F18_REG_7 */
10304 { "nop/reserved", { Mb
}, 0 },
10307 /* MOD_0F1A_PREFIX_0 */
10308 { "bndldx", { Gbnd
, Mv_bnd
}, 0 },
10309 { "nopQ", { Ev
}, 0 },
10312 /* MOD_0F1B_PREFIX_0 */
10313 { "bndstx", { Mv_bnd
, Gbnd
}, 0 },
10314 { "nopQ", { Ev
}, 0 },
10317 /* MOD_0F1B_PREFIX_1 */
10318 { "bndmk", { Gbnd
, Mv_bnd
}, 0 },
10319 { "nopQ", { Ev
}, 0 },
10322 /* MOD_0F1C_PREFIX_0 */
10323 { REG_TABLE (REG_0F1C_P_0_MOD_0
) },
10324 { "nopQ", { Ev
}, 0 },
10327 /* MOD_0F1E_PREFIX_1 */
10328 { "nopQ", { Ev
}, 0 },
10329 { REG_TABLE (REG_0F1E_P_1_MOD_3
) },
10334 { "movL", { Rd
, Td
}, 0 },
10339 { "movL", { Td
, Rd
}, 0 },
10342 /* MOD_0F2B_PREFIX_0 */
10343 {"movntps", { Mx
, XM
}, PREFIX_OPCODE
},
10346 /* MOD_0F2B_PREFIX_1 */
10347 {"movntss", { Md
, XM
}, PREFIX_OPCODE
},
10350 /* MOD_0F2B_PREFIX_2 */
10351 {"movntpd", { Mx
, XM
}, PREFIX_OPCODE
},
10354 /* MOD_0F2B_PREFIX_3 */
10355 {"movntsd", { Mq
, XM
}, PREFIX_OPCODE
},
10360 { "movmskpX", { Gdq
, XS
}, PREFIX_OPCODE
},
10363 /* MOD_0F71_REG_2 */
10365 { "psrlw", { MS
, Ib
}, 0 },
10368 /* MOD_0F71_REG_4 */
10370 { "psraw", { MS
, Ib
}, 0 },
10373 /* MOD_0F71_REG_6 */
10375 { "psllw", { MS
, Ib
}, 0 },
10378 /* MOD_0F72_REG_2 */
10380 { "psrld", { MS
, Ib
}, 0 },
10383 /* MOD_0F72_REG_4 */
10385 { "psrad", { MS
, Ib
}, 0 },
10388 /* MOD_0F72_REG_6 */
10390 { "pslld", { MS
, Ib
}, 0 },
10393 /* MOD_0F73_REG_2 */
10395 { "psrlq", { MS
, Ib
}, 0 },
10398 /* MOD_0F73_REG_3 */
10400 { PREFIX_TABLE (PREFIX_0F73_REG_3
) },
10403 /* MOD_0F73_REG_6 */
10405 { "psllq", { MS
, Ib
}, 0 },
10408 /* MOD_0F73_REG_7 */
10410 { PREFIX_TABLE (PREFIX_0F73_REG_7
) },
10413 /* MOD_0FAE_REG_0 */
10414 { "fxsave", { FXSAVE
}, 0 },
10415 { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3
) },
10418 /* MOD_0FAE_REG_1 */
10419 { "fxrstor", { FXSAVE
}, 0 },
10420 { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3
) },
10423 /* MOD_0FAE_REG_2 */
10424 { "ldmxcsr", { Md
}, 0 },
10425 { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3
) },
10428 /* MOD_0FAE_REG_3 */
10429 { "stmxcsr", { Md
}, 0 },
10430 { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3
) },
10433 /* MOD_0FAE_REG_4 */
10434 { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0
) },
10435 { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3
) },
10438 /* MOD_0FAE_REG_5 */
10439 { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_0
) },
10440 { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3
) },
10443 /* MOD_0FAE_REG_6 */
10444 { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0
) },
10445 { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3
) },
10448 /* MOD_0FAE_REG_7 */
10449 { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0
) },
10450 { RM_TABLE (RM_0FAE_REG_7_MOD_3
) },
10454 { "lssS", { Gv
, Mp
}, 0 },
10458 { "lfsS", { Gv
, Mp
}, 0 },
10462 { "lgsS", { Gv
, Mp
}, 0 },
10466 { PREFIX_TABLE (PREFIX_0FC3_MOD_0
) },
10469 /* MOD_0FC7_REG_3 */
10470 { "xrstors", { FXSAVE
}, 0 },
10473 /* MOD_0FC7_REG_4 */
10474 { "xsavec", { FXSAVE
}, 0 },
10477 /* MOD_0FC7_REG_5 */
10478 { "xsaves", { FXSAVE
}, 0 },
10481 /* MOD_0FC7_REG_6 */
10482 { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0
) },
10483 { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3
) }
10486 /* MOD_0FC7_REG_7 */
10487 { "vmptrst", { Mq
}, 0 },
10488 { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3
) }
10493 { "pmovmskb", { Gdq
, MS
}, 0 },
10496 /* MOD_0FE7_PREFIX_2 */
10497 { "movntdq", { Mx
, XM
}, 0 },
10500 /* MOD_0FF0_PREFIX_3 */
10501 { "lddqu", { XM
, M
}, 0 },
10504 /* MOD_0F382A_PREFIX_2 */
10505 { "movntdqa", { XM
, Mx
}, 0 },
10508 /* MOD_0F38F5_PREFIX_2 */
10509 { "wrussK", { M
, Gdq
}, PREFIX_OPCODE
},
10512 /* MOD_0F38F6_PREFIX_0 */
10513 { "wrssK", { M
, Gdq
}, PREFIX_OPCODE
},
10516 /* MOD_0F38F8_PREFIX_1 */
10517 { "enqcmds", { Gva
, M
}, PREFIX_OPCODE
},
10520 /* MOD_0F38F8_PREFIX_2 */
10521 { "movdir64b", { Gva
, M
}, PREFIX_OPCODE
},
10524 /* MOD_0F38F8_PREFIX_3 */
10525 { "enqcmd", { Gva
, M
}, PREFIX_OPCODE
},
10528 /* MOD_0F38F9_PREFIX_0 */
10529 { "movdiri", { Ev
, Gv
}, PREFIX_OPCODE
},
10533 { "bound{S|}", { Gv
, Ma
}, 0 },
10534 { EVEX_TABLE (EVEX_0F
) },
10538 { "lesS", { Gv
, Mp
}, 0 },
10539 { VEX_C4_TABLE (VEX_0F
) },
10543 { "ldsS", { Gv
, Mp
}, 0 },
10544 { VEX_C5_TABLE (VEX_0F
) },
10547 /* MOD_VEX_0F12_PREFIX_0 */
10548 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0
) },
10549 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1
) },
10553 { VEX_LEN_TABLE (VEX_LEN_0F13_M_0
) },
10556 /* MOD_VEX_0F16_PREFIX_0 */
10557 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0
) },
10558 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1
) },
10562 { VEX_LEN_TABLE (VEX_LEN_0F17_M_0
) },
10566 { "vmovntpX", { Mx
, XM
}, 0 },
10569 /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
10571 { "kandw", { MaskG
, MaskVex
, MaskR
}, 0 },
10574 /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
10576 { "kandq", { MaskG
, MaskVex
, MaskR
}, 0 },
10579 /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
10581 { "kandb", { MaskG
, MaskVex
, MaskR
}, 0 },
10584 /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
10586 { "kandd", { MaskG
, MaskVex
, MaskR
}, 0 },
10589 /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
10591 { "kandnw", { MaskG
, MaskVex
, MaskR
}, 0 },
10594 /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
10596 { "kandnq", { MaskG
, MaskVex
, MaskR
}, 0 },
10599 /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
10601 { "kandnb", { MaskG
, MaskVex
, MaskR
}, 0 },
10604 /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
10606 { "kandnd", { MaskG
, MaskVex
, MaskR
}, 0 },
10609 /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
10611 { "knotw", { MaskG
, MaskR
}, 0 },
10614 /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
10616 { "knotq", { MaskG
, MaskR
}, 0 },
10619 /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
10621 { "knotb", { MaskG
, MaskR
}, 0 },
10624 /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
10626 { "knotd", { MaskG
, MaskR
}, 0 },
10629 /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
10631 { "korw", { MaskG
, MaskVex
, MaskR
}, 0 },
10634 /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
10636 { "korq", { MaskG
, MaskVex
, MaskR
}, 0 },
10639 /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
10641 { "korb", { MaskG
, MaskVex
, MaskR
}, 0 },
10644 /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
10646 { "kord", { MaskG
, MaskVex
, MaskR
}, 0 },
10649 /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
10651 { "kxnorw", { MaskG
, MaskVex
, MaskR
}, 0 },
10654 /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
10656 { "kxnorq", { MaskG
, MaskVex
, MaskR
}, 0 },
10659 /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
10661 { "kxnorb", { MaskG
, MaskVex
, MaskR
}, 0 },
10664 /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
10666 { "kxnord", { MaskG
, MaskVex
, MaskR
}, 0 },
10669 /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
10671 { "kxorw", { MaskG
, MaskVex
, MaskR
}, 0 },
10674 /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
10676 { "kxorq", { MaskG
, MaskVex
, MaskR
}, 0 },
10679 /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
10681 { "kxorb", { MaskG
, MaskVex
, MaskR
}, 0 },
10684 /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
10686 { "kxord", { MaskG
, MaskVex
, MaskR
}, 0 },
10689 /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
10691 { "kaddw", { MaskG
, MaskVex
, MaskR
}, 0 },
10694 /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
10696 { "kaddq", { MaskG
, MaskVex
, MaskR
}, 0 },
10699 /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
10701 { "kaddb", { MaskG
, MaskVex
, MaskR
}, 0 },
10704 /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
10706 { "kaddd", { MaskG
, MaskVex
, MaskR
}, 0 },
10709 /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
10711 { "kunpckwd", { MaskG
, MaskVex
, MaskR
}, 0 },
10714 /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
10716 { "kunpckdq", { MaskG
, MaskVex
, MaskR
}, 0 },
10719 /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
10721 { "kunpckbw", { MaskG
, MaskVex
, MaskR
}, 0 },
10726 { "vmovmskpX", { Gdq
, XS
}, 0 },
10729 /* MOD_VEX_0F71_REG_2 */
10731 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2
) },
10734 /* MOD_VEX_0F71_REG_4 */
10736 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4
) },
10739 /* MOD_VEX_0F71_REG_6 */
10741 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6
) },
10744 /* MOD_VEX_0F72_REG_2 */
10746 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2
) },
10749 /* MOD_VEX_0F72_REG_4 */
10751 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4
) },
10754 /* MOD_VEX_0F72_REG_6 */
10756 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6
) },
10759 /* MOD_VEX_0F73_REG_2 */
10761 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2
) },
10764 /* MOD_VEX_0F73_REG_3 */
10766 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3
) },
10769 /* MOD_VEX_0F73_REG_6 */
10771 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6
) },
10774 /* MOD_VEX_0F73_REG_7 */
10776 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7
) },
10779 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10780 { "kmovw", { Ew
, MaskG
}, 0 },
10784 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10785 { "kmovq", { Eq
, MaskG
}, 0 },
10789 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10790 { "kmovb", { Eb
, MaskG
}, 0 },
10794 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10795 { "kmovd", { Ed
, MaskG
}, 0 },
10799 /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
10801 { "kmovw", { MaskG
, Rdq
}, 0 },
10804 /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
10806 { "kmovb", { MaskG
, Rdq
}, 0 },
10809 /* MOD_VEX_0F92_P_3_LEN_0 */
10811 { "kmovK", { MaskG
, Rdq
}, 0 },
10814 /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
10816 { "kmovw", { Gdq
, MaskR
}, 0 },
10819 /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
10821 { "kmovb", { Gdq
, MaskR
}, 0 },
10824 /* MOD_VEX_0F93_P_3_LEN_0 */
10826 { "kmovK", { Gdq
, MaskR
}, 0 },
10829 /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
10831 { "kortestw", { MaskG
, MaskR
}, 0 },
10834 /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
10836 { "kortestq", { MaskG
, MaskR
}, 0 },
10839 /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
10841 { "kortestb", { MaskG
, MaskR
}, 0 },
10844 /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
10846 { "kortestd", { MaskG
, MaskR
}, 0 },
10849 /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
10851 { "ktestw", { MaskG
, MaskR
}, 0 },
10854 /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
10856 { "ktestq", { MaskG
, MaskR
}, 0 },
10859 /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
10861 { "ktestb", { MaskG
, MaskR
}, 0 },
10864 /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
10866 { "ktestd", { MaskG
, MaskR
}, 0 },
10869 /* MOD_VEX_0FAE_REG_2 */
10870 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0
) },
10873 /* MOD_VEX_0FAE_REG_3 */
10874 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0
) },
10877 /* MOD_VEX_0FD7_PREFIX_2 */
10879 { "vpmovmskb", { Gdq
, XS
}, 0 },
10882 /* MOD_VEX_0FE7_PREFIX_2 */
10883 { "vmovntdq", { Mx
, XM
}, 0 },
10886 /* MOD_VEX_0FF0_PREFIX_3 */
10887 { "vlddqu", { XM
, M
}, 0 },
10890 /* MOD_VEX_0F381A_PREFIX_2 */
10891 { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0
) },
10894 /* MOD_VEX_0F382A_PREFIX_2 */
10895 { "vmovntdqa", { XM
, Mx
}, 0 },
10898 /* MOD_VEX_0F382C_PREFIX_2 */
10899 { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0
) },
10902 /* MOD_VEX_0F382D_PREFIX_2 */
10903 { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0
) },
10906 /* MOD_VEX_0F382E_PREFIX_2 */
10907 { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0
) },
10910 /* MOD_VEX_0F382F_PREFIX_2 */
10911 { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0
) },
10914 /* MOD_VEX_0F385A_PREFIX_2 */
10915 { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0
) },
10918 /* MOD_VEX_0F388C_PREFIX_2 */
10919 { "vpmaskmov%LW", { XM
, Vex
, Mx
}, 0 },
10922 /* MOD_VEX_0F388E_PREFIX_2 */
10923 { "vpmaskmov%LW", { Mx
, Vex
, XM
}, 0 },
10926 /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
10928 { "kshiftrb", { MaskG
, MaskR
, Ib
}, 0 },
10931 /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
10933 { "kshiftrw", { MaskG
, MaskR
, Ib
}, 0 },
10936 /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
10938 { "kshiftrd", { MaskG
, MaskR
, Ib
}, 0 },
10941 /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
10943 { "kshiftrq", { MaskG
, MaskR
, Ib
}, 0 },
10946 /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
10948 { "kshiftlb", { MaskG
, MaskR
, Ib
}, 0 },
10951 /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
10953 { "kshiftlw", { MaskG
, MaskR
, Ib
}, 0 },
10956 /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
10958 { "kshiftld", { MaskG
, MaskR
, Ib
}, 0 },
10961 /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
10963 { "kshiftlq", { MaskG
, MaskR
, Ib
}, 0 },
10966 #include "i386-dis-evex-mod.h"
10969 static const struct dis386 rm_table
[][8] = {
10972 { "xabort", { Skip_MODRM
, Ib
}, 0 },
10976 { "xbeginT", { Skip_MODRM
, Jdqw
}, 0 },
10979 /* RM_0F01_REG_0 */
10980 { "enclv", { Skip_MODRM
}, 0 },
10981 { "vmcall", { Skip_MODRM
}, 0 },
10982 { "vmlaunch", { Skip_MODRM
}, 0 },
10983 { "vmresume", { Skip_MODRM
}, 0 },
10984 { "vmxoff", { Skip_MODRM
}, 0 },
10985 { "pconfig", { Skip_MODRM
}, 0 },
10988 /* RM_0F01_REG_1 */
10989 { "monitor", { { OP_Monitor
, 0 } }, 0 },
10990 { "mwait", { { OP_Mwait
, 0 } }, 0 },
10991 { "clac", { Skip_MODRM
}, 0 },
10992 { "stac", { Skip_MODRM
}, 0 },
10996 { "encls", { Skip_MODRM
}, 0 },
10999 /* RM_0F01_REG_2 */
11000 { "xgetbv", { Skip_MODRM
}, 0 },
11001 { "xsetbv", { Skip_MODRM
}, 0 },
11004 { "vmfunc", { Skip_MODRM
}, 0 },
11005 { "xend", { Skip_MODRM
}, 0 },
11006 { "xtest", { Skip_MODRM
}, 0 },
11007 { "enclu", { Skip_MODRM
}, 0 },
11010 /* RM_0F01_REG_3 */
11011 { "vmrun", { Skip_MODRM
}, 0 },
11012 { "vmmcall", { Skip_MODRM
}, 0 },
11013 { "vmload", { Skip_MODRM
}, 0 },
11014 { "vmsave", { Skip_MODRM
}, 0 },
11015 { "stgi", { Skip_MODRM
}, 0 },
11016 { "clgi", { Skip_MODRM
}, 0 },
11017 { "skinit", { Skip_MODRM
}, 0 },
11018 { "invlpga", { Skip_MODRM
}, 0 },
11021 /* RM_0F01_REG_5_MOD_3 */
11022 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0
) },
11024 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2
) },
11028 { "rdpkru", { Skip_MODRM
}, 0 },
11029 { "wrpkru", { Skip_MODRM
}, 0 },
11032 /* RM_0F01_REG_7_MOD_3 */
11033 { "swapgs", { Skip_MODRM
}, 0 },
11034 { "rdtscp", { Skip_MODRM
}, 0 },
11035 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2
) },
11036 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_3
) },
11037 { "clzero", { Skip_MODRM
}, 0 },
11038 { "rdpru", { Skip_MODRM
}, 0 },
11041 /* RM_0F1E_P_1_MOD_3_REG_7 */
11042 { "nopQ", { Ev
}, 0 },
11043 { "nopQ", { Ev
}, 0 },
11044 { "endbr64", { Skip_MODRM
}, PREFIX_OPCODE
},
11045 { "endbr32", { Skip_MODRM
}, PREFIX_OPCODE
},
11046 { "nopQ", { Ev
}, 0 },
11047 { "nopQ", { Ev
}, 0 },
11048 { "nopQ", { Ev
}, 0 },
11049 { "nopQ", { Ev
}, 0 },
11052 /* RM_0FAE_REG_6_MOD_3 */
11053 { "mfence", { Skip_MODRM
}, 0 },
11056 /* RM_0FAE_REG_7_MOD_3 */
11057 { "sfence", { Skip_MODRM
}, 0 },
11062 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
11064 /* We use the high bit to indicate different name for the same
11066 #define REP_PREFIX (0xf3 | 0x100)
11067 #define XACQUIRE_PREFIX (0xf2 | 0x200)
11068 #define XRELEASE_PREFIX (0xf3 | 0x400)
11069 #define BND_PREFIX (0xf2 | 0x400)
11070 #define NOTRACK_PREFIX (0x3e | 0x100)
11072 /* Remember if the current op is a jump instruction. */
11073 static bfd_boolean op_is_jump
= FALSE
;
11078 int newrex
, i
, length
;
11084 last_lock_prefix
= -1;
11085 last_repz_prefix
= -1;
11086 last_repnz_prefix
= -1;
11087 last_data_prefix
= -1;
11088 last_addr_prefix
= -1;
11089 last_rex_prefix
= -1;
11090 last_seg_prefix
= -1;
11092 active_seg_prefix
= 0;
11093 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
11094 all_prefixes
[i
] = 0;
11097 /* The maximum instruction length is 15bytes. */
11098 while (length
< MAX_CODE_LENGTH
- 1)
11100 FETCH_DATA (the_info
, codep
+ 1);
11104 /* REX prefixes family. */
11121 if (address_mode
== mode_64bit
)
11125 last_rex_prefix
= i
;
11128 prefixes
|= PREFIX_REPZ
;
11129 last_repz_prefix
= i
;
11132 prefixes
|= PREFIX_REPNZ
;
11133 last_repnz_prefix
= i
;
11136 prefixes
|= PREFIX_LOCK
;
11137 last_lock_prefix
= i
;
11140 prefixes
|= PREFIX_CS
;
11141 last_seg_prefix
= i
;
11142 active_seg_prefix
= PREFIX_CS
;
11145 prefixes
|= PREFIX_SS
;
11146 last_seg_prefix
= i
;
11147 active_seg_prefix
= PREFIX_SS
;
11150 prefixes
|= PREFIX_DS
;
11151 last_seg_prefix
= i
;
11152 active_seg_prefix
= PREFIX_DS
;
11155 prefixes
|= PREFIX_ES
;
11156 last_seg_prefix
= i
;
11157 active_seg_prefix
= PREFIX_ES
;
11160 prefixes
|= PREFIX_FS
;
11161 last_seg_prefix
= i
;
11162 active_seg_prefix
= PREFIX_FS
;
11165 prefixes
|= PREFIX_GS
;
11166 last_seg_prefix
= i
;
11167 active_seg_prefix
= PREFIX_GS
;
11170 prefixes
|= PREFIX_DATA
;
11171 last_data_prefix
= i
;
11174 prefixes
|= PREFIX_ADDR
;
11175 last_addr_prefix
= i
;
11178 /* fwait is really an instruction. If there are prefixes
11179 before the fwait, they belong to the fwait, *not* to the
11180 following instruction. */
11182 if (prefixes
|| rex
)
11184 prefixes
|= PREFIX_FWAIT
;
11186 /* This ensures that the previous REX prefixes are noticed
11187 as unused prefixes, as in the return case below. */
11191 prefixes
= PREFIX_FWAIT
;
11196 /* Rex is ignored when followed by another prefix. */
11202 if (*codep
!= FWAIT_OPCODE
)
11203 all_prefixes
[i
++] = *codep
;
11211 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
11214 static const char *
11215 prefix_name (int pref
, int sizeflag
)
11217 static const char *rexes
[16] =
11220 "rex.B", /* 0x41 */
11221 "rex.X", /* 0x42 */
11222 "rex.XB", /* 0x43 */
11223 "rex.R", /* 0x44 */
11224 "rex.RB", /* 0x45 */
11225 "rex.RX", /* 0x46 */
11226 "rex.RXB", /* 0x47 */
11227 "rex.W", /* 0x48 */
11228 "rex.WB", /* 0x49 */
11229 "rex.WX", /* 0x4a */
11230 "rex.WXB", /* 0x4b */
11231 "rex.WR", /* 0x4c */
11232 "rex.WRB", /* 0x4d */
11233 "rex.WRX", /* 0x4e */
11234 "rex.WRXB", /* 0x4f */
11239 /* REX prefixes family. */
11256 return rexes
[pref
- 0x40];
11276 return (sizeflag
& DFLAG
) ? "data16" : "data32";
11278 if (address_mode
== mode_64bit
)
11279 return (sizeflag
& AFLAG
) ? "addr32" : "addr64";
11281 return (sizeflag
& AFLAG
) ? "addr16" : "addr32";
11286 case XACQUIRE_PREFIX
:
11288 case XRELEASE_PREFIX
:
11292 case NOTRACK_PREFIX
:
11299 static char op_out
[MAX_OPERANDS
][100];
11300 static int op_ad
, op_index
[MAX_OPERANDS
];
11301 static int two_source_ops
;
11302 static bfd_vma op_address
[MAX_OPERANDS
];
11303 static bfd_vma op_riprel
[MAX_OPERANDS
];
11304 static bfd_vma start_pc
;
11307 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
11308 * (see topic "Redundant prefixes" in the "Differences from 8086"
11309 * section of the "Virtual 8086 Mode" chapter.)
11310 * 'pc' should be the address of this instruction, it will
11311 * be used to print the target address if this is a relative jump or call
11312 * The function returns the length of this instruction in bytes.
11315 static char intel_syntax
;
11316 static char intel_mnemonic
= !SYSV386_COMPAT
;
11317 static char open_char
;
11318 static char close_char
;
11319 static char separator_char
;
11320 static char scale_char
;
11328 static enum x86_64_isa isa64
;
11330 /* Here for backwards compatibility. When gdb stops using
11331 print_insn_i386_att and print_insn_i386_intel these functions can
11332 disappear, and print_insn_i386 be merged into print_insn. */
11334 print_insn_i386_att (bfd_vma pc
, disassemble_info
*info
)
11338 return print_insn (pc
, info
);
11342 print_insn_i386_intel (bfd_vma pc
, disassemble_info
*info
)
11346 return print_insn (pc
, info
);
11350 print_insn_i386 (bfd_vma pc
, disassemble_info
*info
)
11354 return print_insn (pc
, info
);
11358 print_i386_disassembler_options (FILE *stream
)
11360 fprintf (stream
, _("\n\
11361 The following i386/x86-64 specific disassembler options are supported for use\n\
11362 with the -M switch (multiple options should be separated by commas):\n"));
11364 fprintf (stream
, _(" x86-64 Disassemble in 64bit mode\n"));
11365 fprintf (stream
, _(" i386 Disassemble in 32bit mode\n"));
11366 fprintf (stream
, _(" i8086 Disassemble in 16bit mode\n"));
11367 fprintf (stream
, _(" att Display instruction in AT&T syntax\n"));
11368 fprintf (stream
, _(" intel Display instruction in Intel syntax\n"));
11369 fprintf (stream
, _(" att-mnemonic\n"
11370 " Display instruction in AT&T mnemonic\n"));
11371 fprintf (stream
, _(" intel-mnemonic\n"
11372 " Display instruction in Intel mnemonic\n"));
11373 fprintf (stream
, _(" addr64 Assume 64bit address size\n"));
11374 fprintf (stream
, _(" addr32 Assume 32bit address size\n"));
11375 fprintf (stream
, _(" addr16 Assume 16bit address size\n"));
11376 fprintf (stream
, _(" data32 Assume 32bit data size\n"));
11377 fprintf (stream
, _(" data16 Assume 16bit data size\n"));
11378 fprintf (stream
, _(" suffix Always display instruction suffix in AT&T syntax\n"));
11379 fprintf (stream
, _(" amd64 Display instruction in AMD64 ISA\n"));
11380 fprintf (stream
, _(" intel64 Display instruction in Intel64 ISA\n"));
11384 static const struct dis386 bad_opcode
= { "(bad)", { XX
}, 0 };
11386 /* Get a pointer to struct dis386 with a valid name. */
11388 static const struct dis386
*
11389 get_valid_dis386 (const struct dis386
*dp
, disassemble_info
*info
)
11391 int vindex
, vex_table_index
;
11393 if (dp
->name
!= NULL
)
11396 switch (dp
->op
[0].bytemode
)
11398 case USE_REG_TABLE
:
11399 dp
= ®_table
[dp
->op
[1].bytemode
][modrm
.reg
];
11402 case USE_MOD_TABLE
:
11403 vindex
= modrm
.mod
== 0x3 ? 1 : 0;
11404 dp
= &mod_table
[dp
->op
[1].bytemode
][vindex
];
11408 dp
= &rm_table
[dp
->op
[1].bytemode
][modrm
.rm
];
11411 case USE_PREFIX_TABLE
:
11414 /* The prefix in VEX is implicit. */
11415 switch (vex
.prefix
)
11420 case REPE_PREFIX_OPCODE
:
11423 case DATA_PREFIX_OPCODE
:
11426 case REPNE_PREFIX_OPCODE
:
11436 int last_prefix
= -1;
11439 /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
11440 When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
11442 if ((prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0)
11444 if (last_repz_prefix
> last_repnz_prefix
)
11447 prefix
= PREFIX_REPZ
;
11448 last_prefix
= last_repz_prefix
;
11453 prefix
= PREFIX_REPNZ
;
11454 last_prefix
= last_repnz_prefix
;
11457 /* Check if prefix should be ignored. */
11458 if ((((prefix_table
[dp
->op
[1].bytemode
][vindex
].prefix_requirement
11459 & PREFIX_IGNORED
) >> PREFIX_IGNORED_SHIFT
)
11464 if (vindex
== 0 && (prefixes
& PREFIX_DATA
) != 0)
11467 prefix
= PREFIX_DATA
;
11468 last_prefix
= last_data_prefix
;
11473 used_prefixes
|= prefix
;
11474 all_prefixes
[last_prefix
] = 0;
11477 dp
= &prefix_table
[dp
->op
[1].bytemode
][vindex
];
11480 case USE_X86_64_TABLE
:
11481 vindex
= address_mode
== mode_64bit
? 1 : 0;
11482 dp
= &x86_64_table
[dp
->op
[1].bytemode
][vindex
];
11485 case USE_3BYTE_TABLE
:
11486 FETCH_DATA (info
, codep
+ 2);
11488 dp
= &three_byte_table
[dp
->op
[1].bytemode
][vindex
];
11490 modrm
.mod
= (*codep
>> 6) & 3;
11491 modrm
.reg
= (*codep
>> 3) & 7;
11492 modrm
.rm
= *codep
& 7;
11495 case USE_VEX_LEN_TABLE
:
11499 switch (vex
.length
)
11512 dp
= &vex_len_table
[dp
->op
[1].bytemode
][vindex
];
11515 case USE_EVEX_LEN_TABLE
:
11519 switch (vex
.length
)
11535 dp
= &evex_len_table
[dp
->op
[1].bytemode
][vindex
];
11538 case USE_XOP_8F_TABLE
:
11539 FETCH_DATA (info
, codep
+ 3);
11540 /* All bits in the REX prefix are ignored. */
11542 rex
= ~(*codep
>> 5) & 0x7;
11544 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
11545 switch ((*codep
& 0x1f))
11551 vex_table_index
= XOP_08
;
11554 vex_table_index
= XOP_09
;
11557 vex_table_index
= XOP_0A
;
11561 vex
.w
= *codep
& 0x80;
11562 if (vex
.w
&& address_mode
== mode_64bit
)
11565 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11566 if (address_mode
!= mode_64bit
)
11568 /* In 16/32-bit mode REX_B is silently ignored. */
11572 vex
.length
= (*codep
& 0x4) ? 256 : 128;
11573 switch ((*codep
& 0x3))
11578 vex
.prefix
= DATA_PREFIX_OPCODE
;
11581 vex
.prefix
= REPE_PREFIX_OPCODE
;
11584 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11591 dp
= &xop_table
[vex_table_index
][vindex
];
11594 FETCH_DATA (info
, codep
+ 1);
11595 modrm
.mod
= (*codep
>> 6) & 3;
11596 modrm
.reg
= (*codep
>> 3) & 7;
11597 modrm
.rm
= *codep
& 7;
11600 case USE_VEX_C4_TABLE
:
11602 FETCH_DATA (info
, codep
+ 3);
11603 /* All bits in the REX prefix are ignored. */
11605 rex
= ~(*codep
>> 5) & 0x7;
11606 switch ((*codep
& 0x1f))
11612 vex_table_index
= VEX_0F
;
11615 vex_table_index
= VEX_0F38
;
11618 vex_table_index
= VEX_0F3A
;
11622 vex
.w
= *codep
& 0x80;
11623 if (address_mode
== mode_64bit
)
11630 /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
11631 is ignored, other REX bits are 0 and the highest bit in
11632 VEX.vvvv is also ignored (but we mustn't clear it here). */
11635 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11636 vex
.length
= (*codep
& 0x4) ? 256 : 128;
11637 switch ((*codep
& 0x3))
11642 vex
.prefix
= DATA_PREFIX_OPCODE
;
11645 vex
.prefix
= REPE_PREFIX_OPCODE
;
11648 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11655 dp
= &vex_table
[vex_table_index
][vindex
];
11657 /* There is no MODRM byte for VEX0F 77. */
11658 if (vex_table_index
!= VEX_0F
|| vindex
!= 0x77)
11660 FETCH_DATA (info
, codep
+ 1);
11661 modrm
.mod
= (*codep
>> 6) & 3;
11662 modrm
.reg
= (*codep
>> 3) & 7;
11663 modrm
.rm
= *codep
& 7;
11667 case USE_VEX_C5_TABLE
:
11669 FETCH_DATA (info
, codep
+ 2);
11670 /* All bits in the REX prefix are ignored. */
11672 rex
= (*codep
& 0x80) ? 0 : REX_R
;
11674 /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
11676 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11677 vex
.length
= (*codep
& 0x4) ? 256 : 128;
11678 switch ((*codep
& 0x3))
11683 vex
.prefix
= DATA_PREFIX_OPCODE
;
11686 vex
.prefix
= REPE_PREFIX_OPCODE
;
11689 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11696 dp
= &vex_table
[dp
->op
[1].bytemode
][vindex
];
11698 /* There is no MODRM byte for VEX 77. */
11699 if (vindex
!= 0x77)
11701 FETCH_DATA (info
, codep
+ 1);
11702 modrm
.mod
= (*codep
>> 6) & 3;
11703 modrm
.reg
= (*codep
>> 3) & 7;
11704 modrm
.rm
= *codep
& 7;
11708 case USE_VEX_W_TABLE
:
11712 dp
= &vex_w_table
[dp
->op
[1].bytemode
][vex
.w
? 1 : 0];
11715 case USE_EVEX_TABLE
:
11716 two_source_ops
= 0;
11719 FETCH_DATA (info
, codep
+ 4);
11720 /* All bits in the REX prefix are ignored. */
11722 /* The first byte after 0x62. */
11723 rex
= ~(*codep
>> 5) & 0x7;
11724 vex
.r
= *codep
& 0x10;
11725 switch ((*codep
& 0xf))
11728 return &bad_opcode
;
11730 vex_table_index
= EVEX_0F
;
11733 vex_table_index
= EVEX_0F38
;
11736 vex_table_index
= EVEX_0F3A
;
11740 /* The second byte after 0x62. */
11742 vex
.w
= *codep
& 0x80;
11743 if (vex
.w
&& address_mode
== mode_64bit
)
11746 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11749 if (!(*codep
& 0x4))
11750 return &bad_opcode
;
11752 switch ((*codep
& 0x3))
11757 vex
.prefix
= DATA_PREFIX_OPCODE
;
11760 vex
.prefix
= REPE_PREFIX_OPCODE
;
11763 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11767 /* The third byte after 0x62. */
11770 /* Remember the static rounding bits. */
11771 vex
.ll
= (*codep
>> 5) & 3;
11772 vex
.b
= (*codep
& 0x10) != 0;
11774 vex
.v
= *codep
& 0x8;
11775 vex
.mask_register_specifier
= *codep
& 0x7;
11776 vex
.zeroing
= *codep
& 0x80;
11778 if (address_mode
!= mode_64bit
)
11780 /* In 16/32-bit mode silently ignore following bits. */
11790 dp
= &evex_table
[vex_table_index
][vindex
];
11792 FETCH_DATA (info
, codep
+ 1);
11793 modrm
.mod
= (*codep
>> 6) & 3;
11794 modrm
.reg
= (*codep
>> 3) & 7;
11795 modrm
.rm
= *codep
& 7;
11797 /* Set vector length. */
11798 if (modrm
.mod
== 3 && vex
.b
)
11814 return &bad_opcode
;
11827 if (dp
->name
!= NULL
)
11830 return get_valid_dis386 (dp
, info
);
11834 get_sib (disassemble_info
*info
, int sizeflag
)
11836 /* If modrm.mod == 3, operand must be register. */
11838 && ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
11842 FETCH_DATA (info
, codep
+ 2);
11843 sib
.index
= (codep
[1] >> 3) & 7;
11844 sib
.scale
= (codep
[1] >> 6) & 3;
11845 sib
.base
= codep
[1] & 7;
11850 print_insn (bfd_vma pc
, disassemble_info
*info
)
11852 const struct dis386
*dp
;
11854 char *op_txt
[MAX_OPERANDS
];
11856 int sizeflag
, orig_sizeflag
;
11858 struct dis_private priv
;
11861 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
11862 if ((info
->mach
& bfd_mach_i386_i386
) != 0)
11863 address_mode
= mode_32bit
;
11864 else if (info
->mach
== bfd_mach_i386_i8086
)
11866 address_mode
= mode_16bit
;
11867 priv
.orig_sizeflag
= 0;
11870 address_mode
= mode_64bit
;
11872 if (intel_syntax
== (char) -1)
11873 intel_syntax
= (info
->mach
& bfd_mach_i386_intel_syntax
) != 0;
11875 for (p
= info
->disassembler_options
; p
!= NULL
; )
11877 if (CONST_STRNEQ (p
, "amd64"))
11879 else if (CONST_STRNEQ (p
, "intel64"))
11881 else if (CONST_STRNEQ (p
, "x86-64"))
11883 address_mode
= mode_64bit
;
11884 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
11886 else if (CONST_STRNEQ (p
, "i386"))
11888 address_mode
= mode_32bit
;
11889 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
11891 else if (CONST_STRNEQ (p
, "i8086"))
11893 address_mode
= mode_16bit
;
11894 priv
.orig_sizeflag
= 0;
11896 else if (CONST_STRNEQ (p
, "intel"))
11899 if (CONST_STRNEQ (p
+ 5, "-mnemonic"))
11900 intel_mnemonic
= 1;
11902 else if (CONST_STRNEQ (p
, "att"))
11905 if (CONST_STRNEQ (p
+ 3, "-mnemonic"))
11906 intel_mnemonic
= 0;
11908 else if (CONST_STRNEQ (p
, "addr"))
11910 if (address_mode
== mode_64bit
)
11912 if (p
[4] == '3' && p
[5] == '2')
11913 priv
.orig_sizeflag
&= ~AFLAG
;
11914 else if (p
[4] == '6' && p
[5] == '4')
11915 priv
.orig_sizeflag
|= AFLAG
;
11919 if (p
[4] == '1' && p
[5] == '6')
11920 priv
.orig_sizeflag
&= ~AFLAG
;
11921 else if (p
[4] == '3' && p
[5] == '2')
11922 priv
.orig_sizeflag
|= AFLAG
;
11925 else if (CONST_STRNEQ (p
, "data"))
11927 if (p
[4] == '1' && p
[5] == '6')
11928 priv
.orig_sizeflag
&= ~DFLAG
;
11929 else if (p
[4] == '3' && p
[5] == '2')
11930 priv
.orig_sizeflag
|= DFLAG
;
11932 else if (CONST_STRNEQ (p
, "suffix"))
11933 priv
.orig_sizeflag
|= SUFFIX_ALWAYS
;
11935 p
= strchr (p
, ',');
11940 if (address_mode
== mode_64bit
&& sizeof (bfd_vma
) < 8)
11942 (*info
->fprintf_func
) (info
->stream
,
11943 _("64-bit address is disabled"));
11949 names64
= intel_names64
;
11950 names32
= intel_names32
;
11951 names16
= intel_names16
;
11952 names8
= intel_names8
;
11953 names8rex
= intel_names8rex
;
11954 names_seg
= intel_names_seg
;
11955 names_mm
= intel_names_mm
;
11956 names_bnd
= intel_names_bnd
;
11957 names_xmm
= intel_names_xmm
;
11958 names_ymm
= intel_names_ymm
;
11959 names_zmm
= intel_names_zmm
;
11960 index64
= intel_index64
;
11961 index32
= intel_index32
;
11962 names_mask
= intel_names_mask
;
11963 index16
= intel_index16
;
11966 separator_char
= '+';
11971 names64
= att_names64
;
11972 names32
= att_names32
;
11973 names16
= att_names16
;
11974 names8
= att_names8
;
11975 names8rex
= att_names8rex
;
11976 names_seg
= att_names_seg
;
11977 names_mm
= att_names_mm
;
11978 names_bnd
= att_names_bnd
;
11979 names_xmm
= att_names_xmm
;
11980 names_ymm
= att_names_ymm
;
11981 names_zmm
= att_names_zmm
;
11982 index64
= att_index64
;
11983 index32
= att_index32
;
11984 names_mask
= att_names_mask
;
11985 index16
= att_index16
;
11988 separator_char
= ',';
11992 /* The output looks better if we put 7 bytes on a line, since that
11993 puts most long word instructions on a single line. Use 8 bytes
11995 if ((info
->mach
& bfd_mach_l1om
) != 0)
11996 info
->bytes_per_line
= 8;
11998 info
->bytes_per_line
= 7;
12000 info
->private_data
= &priv
;
12001 priv
.max_fetched
= priv
.the_buffer
;
12002 priv
.insn_start
= pc
;
12005 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12013 start_codep
= priv
.the_buffer
;
12014 codep
= priv
.the_buffer
;
12016 if (OPCODES_SIGSETJMP (priv
.bailout
) != 0)
12020 /* Getting here means we tried for data but didn't get it. That
12021 means we have an incomplete instruction of some sort. Just
12022 print the first byte as a prefix or a .byte pseudo-op. */
12023 if (codep
> priv
.the_buffer
)
12025 name
= prefix_name (priv
.the_buffer
[0], priv
.orig_sizeflag
);
12027 (*info
->fprintf_func
) (info
->stream
, "%s", name
);
12030 /* Just print the first byte as a .byte instruction. */
12031 (*info
->fprintf_func
) (info
->stream
, ".byte 0x%x",
12032 (unsigned int) priv
.the_buffer
[0]);
12042 sizeflag
= priv
.orig_sizeflag
;
12044 if (!ckprefix () || rex_used
)
12046 /* Too many prefixes or unused REX prefixes. */
12048 i
< (int) ARRAY_SIZE (all_prefixes
) && all_prefixes
[i
];
12050 (*info
->fprintf_func
) (info
->stream
, "%s%s",
12052 prefix_name (all_prefixes
[i
], sizeflag
));
12056 insn_codep
= codep
;
12058 FETCH_DATA (info
, codep
+ 1);
12059 two_source_ops
= (*codep
== 0x62) || (*codep
== 0xc8);
12061 if (((prefixes
& PREFIX_FWAIT
)
12062 && ((*codep
< 0xd8) || (*codep
> 0xdf))))
12064 /* Handle prefixes before fwait. */
12065 for (i
= 0; i
< fwait_prefix
&& all_prefixes
[i
];
12067 (*info
->fprintf_func
) (info
->stream
, "%s ",
12068 prefix_name (all_prefixes
[i
], sizeflag
));
12069 (*info
->fprintf_func
) (info
->stream
, "fwait");
12073 if (*codep
== 0x0f)
12075 unsigned char threebyte
;
12078 FETCH_DATA (info
, codep
+ 1);
12079 threebyte
= *codep
;
12080 dp
= &dis386_twobyte
[threebyte
];
12081 need_modrm
= twobyte_has_modrm
[*codep
];
12086 dp
= &dis386
[*codep
];
12087 need_modrm
= onebyte_has_modrm
[*codep
];
12091 /* Save sizeflag for printing the extra prefixes later before updating
12092 it for mnemonic and operand processing. The prefix names depend
12093 only on the address mode. */
12094 orig_sizeflag
= sizeflag
;
12095 if (prefixes
& PREFIX_ADDR
)
12097 if ((prefixes
& PREFIX_DATA
))
12103 FETCH_DATA (info
, codep
+ 1);
12104 modrm
.mod
= (*codep
>> 6) & 3;
12105 modrm
.reg
= (*codep
>> 3) & 7;
12106 modrm
.rm
= *codep
& 7;
12112 memset (&vex
, 0, sizeof (vex
));
12114 if (dp
->name
== NULL
&& dp
->op
[0].bytemode
== FLOATCODE
)
12116 get_sib (info
, sizeflag
);
12117 dofloat (sizeflag
);
12121 dp
= get_valid_dis386 (dp
, info
);
12122 if (dp
!= NULL
&& putop (dp
->name
, sizeflag
) == 0)
12124 get_sib (info
, sizeflag
);
12125 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12128 op_ad
= MAX_OPERANDS
- 1 - i
;
12130 (*dp
->op
[i
].rtn
) (dp
->op
[i
].bytemode
, sizeflag
);
12131 /* For EVEX instruction after the last operand masking
12132 should be printed. */
12133 if (i
== 0 && vex
.evex
)
12135 /* Don't print {%k0}. */
12136 if (vex
.mask_register_specifier
)
12139 oappend (names_mask
[vex
.mask_register_specifier
]);
12149 /* Clear instruction information. */
12152 the_info
->insn_info_valid
= 0;
12153 the_info
->branch_delay_insns
= 0;
12154 the_info
->data_size
= 0;
12155 the_info
->insn_type
= dis_noninsn
;
12156 the_info
->target
= 0;
12157 the_info
->target2
= 0;
12160 /* Reset jump operation indicator. */
12161 op_is_jump
= FALSE
;
12164 int jump_detection
= 0;
12166 /* Extract flags. */
12167 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12169 if ((dp
->op
[i
].rtn
== OP_J
)
12170 || (dp
->op
[i
].rtn
== OP_indirE
))
12171 jump_detection
|= 1;
12172 else if ((dp
->op
[i
].rtn
== BND_Fixup
)
12173 || (!dp
->op
[i
].rtn
&& !dp
->op
[i
].bytemode
))
12174 jump_detection
|= 2;
12175 else if ((dp
->op
[i
].bytemode
== cond_jump_mode
)
12176 || (dp
->op
[i
].bytemode
== loop_jcxz_mode
))
12177 jump_detection
|= 4;
12180 /* Determine if this is a jump or branch. */
12181 if ((jump_detection
& 0x3) == 0x3)
12184 if (jump_detection
& 0x4)
12185 the_info
->insn_type
= dis_condbranch
;
12187 the_info
->insn_type
=
12188 (dp
->name
&& !strncmp(dp
->name
, "call", 4))
12189 ? dis_jsr
: dis_branch
;
12193 /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
12194 are all 0s in inverted form. */
12195 if (need_vex
&& vex
.register_specifier
!= 0)
12197 (*info
->fprintf_func
) (info
->stream
, "(bad)");
12198 return end_codep
- priv
.the_buffer
;
12201 /* Check if the REX prefix is used. */
12202 if (rex_ignored
== 0 && (rex
^ rex_used
) == 0 && last_rex_prefix
>= 0)
12203 all_prefixes
[last_rex_prefix
] = 0;
12205 /* Check if the SEG prefix is used. */
12206 if ((prefixes
& (PREFIX_CS
| PREFIX_SS
| PREFIX_DS
| PREFIX_ES
12207 | PREFIX_FS
| PREFIX_GS
)) != 0
12208 && (used_prefixes
& active_seg_prefix
) != 0)
12209 all_prefixes
[last_seg_prefix
] = 0;
12211 /* Check if the ADDR prefix is used. */
12212 if ((prefixes
& PREFIX_ADDR
) != 0
12213 && (used_prefixes
& PREFIX_ADDR
) != 0)
12214 all_prefixes
[last_addr_prefix
] = 0;
12216 /* Check if the DATA prefix is used. */
12217 if ((prefixes
& PREFIX_DATA
) != 0
12218 && (used_prefixes
& PREFIX_DATA
) != 0)
12219 all_prefixes
[last_data_prefix
] = 0;
12221 /* Print the extra prefixes. */
12223 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
12224 if (all_prefixes
[i
])
12227 name
= prefix_name (all_prefixes
[i
], orig_sizeflag
);
12230 prefix_length
+= strlen (name
) + 1;
12231 (*info
->fprintf_func
) (info
->stream
, "%s ", name
);
12234 /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
12235 unused, opcode is invalid. Since the PREFIX_DATA prefix may be
12236 used by putop and MMX/SSE operand and may be overriden by the
12237 PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
12239 if (dp
->prefix_requirement
== PREFIX_OPCODE
12240 && dp
!= &bad_opcode
12242 & (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0
12244 & (PREFIX_REPZ
| PREFIX_REPNZ
)) == 0)
12246 & (PREFIX_REPZ
| PREFIX_REPNZ
| PREFIX_DATA
))
12248 && (used_prefixes
& PREFIX_DATA
) == 0))))
12250 (*info
->fprintf_func
) (info
->stream
, "(bad)");
12251 return end_codep
- priv
.the_buffer
;
12254 /* Check maximum code length. */
12255 if ((codep
- start_codep
) > MAX_CODE_LENGTH
)
12257 (*info
->fprintf_func
) (info
->stream
, "(bad)");
12258 return MAX_CODE_LENGTH
;
12261 obufp
= mnemonicendp
;
12262 for (i
= strlen (obuf
) + prefix_length
; i
< 6; i
++)
12265 (*info
->fprintf_func
) (info
->stream
, "%s", obuf
);
12267 /* The enter and bound instructions are printed with operands in the same
12268 order as the intel book; everything else is printed in reverse order. */
12269 if (intel_syntax
|| two_source_ops
)
12273 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12274 op_txt
[i
] = op_out
[i
];
12276 if (intel_syntax
&& dp
&& dp
->op
[2].rtn
== OP_Rounding
12277 && dp
->op
[3].rtn
== OP_E
&& dp
->op
[4].rtn
== NULL
)
12279 op_txt
[2] = op_out
[3];
12280 op_txt
[3] = op_out
[2];
12283 for (i
= 0; i
< (MAX_OPERANDS
>> 1); ++i
)
12285 op_ad
= op_index
[i
];
12286 op_index
[i
] = op_index
[MAX_OPERANDS
- 1 - i
];
12287 op_index
[MAX_OPERANDS
- 1 - i
] = op_ad
;
12288 riprel
= op_riprel
[i
];
12289 op_riprel
[i
] = op_riprel
[MAX_OPERANDS
- 1 - i
];
12290 op_riprel
[MAX_OPERANDS
- 1 - i
] = riprel
;
12295 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12296 op_txt
[MAX_OPERANDS
- 1 - i
] = op_out
[i
];
12300 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12304 (*info
->fprintf_func
) (info
->stream
, ",");
12305 if (op_index
[i
] != -1 && !op_riprel
[i
])
12307 bfd_vma target
= (bfd_vma
) op_address
[op_index
[i
]];
12309 if (the_info
&& op_is_jump
)
12311 the_info
->insn_info_valid
= 1;
12312 the_info
->branch_delay_insns
= 0;
12313 the_info
->data_size
= 0;
12314 the_info
->target
= target
;
12315 the_info
->target2
= 0;
12317 (*info
->print_address_func
) (target
, info
);
12320 (*info
->fprintf_func
) (info
->stream
, "%s", op_txt
[i
]);
12324 for (i
= 0; i
< MAX_OPERANDS
; i
++)
12325 if (op_index
[i
] != -1 && op_riprel
[i
])
12327 (*info
->fprintf_func
) (info
->stream
, " # ");
12328 (*info
->print_address_func
) ((bfd_vma
) (start_pc
+ (codep
- start_codep
)
12329 + op_address
[op_index
[i
]]), info
);
12332 return codep
- priv
.the_buffer
;
12335 static const char *float_mem
[] = {
12410 static const unsigned char float_mem_mode
[] = {
12485 #define ST { OP_ST, 0 }
12486 #define STi { OP_STi, 0 }
12488 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
12489 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
12490 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
12491 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
12492 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
12493 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
12494 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
12495 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
12496 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
12498 static const struct dis386 float_reg
[][8] = {
12501 { "fadd", { ST
, STi
}, 0 },
12502 { "fmul", { ST
, STi
}, 0 },
12503 { "fcom", { STi
}, 0 },
12504 { "fcomp", { STi
}, 0 },
12505 { "fsub", { ST
, STi
}, 0 },
12506 { "fsubr", { ST
, STi
}, 0 },
12507 { "fdiv", { ST
, STi
}, 0 },
12508 { "fdivr", { ST
, STi
}, 0 },
12512 { "fld", { STi
}, 0 },
12513 { "fxch", { STi
}, 0 },
12523 { "fcmovb", { ST
, STi
}, 0 },
12524 { "fcmove", { ST
, STi
}, 0 },
12525 { "fcmovbe",{ ST
, STi
}, 0 },
12526 { "fcmovu", { ST
, STi
}, 0 },
12534 { "fcmovnb",{ ST
, STi
}, 0 },
12535 { "fcmovne",{ ST
, STi
}, 0 },
12536 { "fcmovnbe",{ ST
, STi
}, 0 },
12537 { "fcmovnu",{ ST
, STi
}, 0 },
12539 { "fucomi", { ST
, STi
}, 0 },
12540 { "fcomi", { ST
, STi
}, 0 },
12545 { "fadd", { STi
, ST
}, 0 },
12546 { "fmul", { STi
, ST
}, 0 },
12549 { "fsub{!M|r}", { STi
, ST
}, 0 },
12550 { "fsub{M|}", { STi
, ST
}, 0 },
12551 { "fdiv{!M|r}", { STi
, ST
}, 0 },
12552 { "fdiv{M|}", { STi
, ST
}, 0 },
12556 { "ffree", { STi
}, 0 },
12558 { "fst", { STi
}, 0 },
12559 { "fstp", { STi
}, 0 },
12560 { "fucom", { STi
}, 0 },
12561 { "fucomp", { STi
}, 0 },
12567 { "faddp", { STi
, ST
}, 0 },
12568 { "fmulp", { STi
, ST
}, 0 },
12571 { "fsub{!M|r}p", { STi
, ST
}, 0 },
12572 { "fsub{M|}p", { STi
, ST
}, 0 },
12573 { "fdiv{!M|r}p", { STi
, ST
}, 0 },
12574 { "fdiv{M|}p", { STi
, ST
}, 0 },
12578 { "ffreep", { STi
}, 0 },
12583 { "fucomip", { ST
, STi
}, 0 },
12584 { "fcomip", { ST
, STi
}, 0 },
12589 static char *fgrps
[][8] = {
12592 "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12597 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12602 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
12607 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
12612 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
12617 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
12622 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12627 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
12628 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
12633 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12638 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12643 swap_operand (void)
12645 mnemonicendp
[0] = '.';
12646 mnemonicendp
[1] = 's';
12651 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED
,
12652 int sizeflag ATTRIBUTE_UNUSED
)
12654 /* Skip mod/rm byte. */
12660 dofloat (int sizeflag
)
12662 const struct dis386
*dp
;
12663 unsigned char floatop
;
12665 floatop
= codep
[-1];
12667 if (modrm
.mod
!= 3)
12669 int fp_indx
= (floatop
- 0xd8) * 8 + modrm
.reg
;
12671 putop (float_mem
[fp_indx
], sizeflag
);
12674 OP_E (float_mem_mode
[fp_indx
], sizeflag
);
12677 /* Skip mod/rm byte. */
12681 dp
= &float_reg
[floatop
- 0xd8][modrm
.reg
];
12682 if (dp
->name
== NULL
)
12684 putop (fgrps
[dp
->op
[0].bytemode
][modrm
.rm
], sizeflag
);
12686 /* Instruction fnstsw is only one with strange arg. */
12687 if (floatop
== 0xdf && codep
[-1] == 0xe0)
12688 strcpy (op_out
[0], names16
[0]);
12692 putop (dp
->name
, sizeflag
);
12697 (*dp
->op
[0].rtn
) (dp
->op
[0].bytemode
, sizeflag
);
12702 (*dp
->op
[1].rtn
) (dp
->op
[1].bytemode
, sizeflag
);
12706 /* Like oappend (below), but S is a string starting with '%'.
12707 In Intel syntax, the '%' is elided. */
12709 oappend_maybe_intel (const char *s
)
12711 oappend (s
+ intel_syntax
);
12715 OP_ST (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
12717 oappend_maybe_intel ("%st");
12721 OP_STi (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
12723 sprintf (scratchbuf
, "%%st(%d)", modrm
.rm
);
12724 oappend_maybe_intel (scratchbuf
);
12727 /* Capital letters in template are macros. */
12729 putop (const char *in_template
, int sizeflag
)
12734 unsigned int l
= 0, len
= 1;
12737 #define SAVE_LAST(c) \
12738 if (l < len && l < sizeof (last)) \
12743 for (p
= in_template
; *p
; p
++)
12759 while (*++p
!= '|')
12760 if (*p
== '}' || *p
== '\0')
12763 /* Fall through. */
12768 while (*++p
!= '}')
12779 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
12783 if (l
== 0 && len
== 1)
12788 if (sizeflag
& SUFFIX_ALWAYS
)
12801 if (address_mode
== mode_64bit
12802 && !(prefixes
& PREFIX_ADDR
))
12813 if (intel_syntax
&& !alt
)
12815 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
12817 if (sizeflag
& DFLAG
)
12818 *obufp
++ = intel_syntax
? 'd' : 'l';
12820 *obufp
++ = intel_syntax
? 'w' : 's';
12821 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12825 if (intel_syntax
|| !(sizeflag
& SUFFIX_ALWAYS
))
12828 if (modrm
.mod
== 3)
12834 if (sizeflag
& DFLAG
)
12835 *obufp
++ = intel_syntax
? 'd' : 'l';
12838 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12844 case 'E': /* For jcxz/jecxz */
12845 if (address_mode
== mode_64bit
)
12847 if (sizeflag
& AFLAG
)
12853 if (sizeflag
& AFLAG
)
12855 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
12860 if ((prefixes
& PREFIX_ADDR
) || (sizeflag
& SUFFIX_ALWAYS
))
12862 if (sizeflag
& AFLAG
)
12863 *obufp
++ = address_mode
== mode_64bit
? 'q' : 'l';
12865 *obufp
++ = address_mode
== mode_64bit
? 'l' : 'w';
12866 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
12870 if (intel_syntax
|| (obufp
[-1] != 's' && !(sizeflag
& SUFFIX_ALWAYS
)))
12872 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
12876 if (!(rex
& REX_W
))
12877 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12882 if ((prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_CS
12883 || (prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_DS
)
12885 used_prefixes
|= prefixes
& (PREFIX_CS
| PREFIX_DS
);
12888 if (prefixes
& PREFIX_DS
)
12907 if (l
!= 0 || len
!= 1)
12909 if (l
!= 1 || len
!= 2 || last
[0] != 'X')
12914 if (!need_vex
|| !vex
.evex
)
12917 || ((modrm
.mod
== 3 || vex
.b
) && !(sizeflag
& SUFFIX_ALWAYS
)))
12919 switch (vex
.length
)
12937 if (address_mode
== mode_64bit
&& (sizeflag
& SUFFIX_ALWAYS
))
12942 /* Fall through. */
12945 if (l
!= 0 || len
!= 1)
12953 if (sizeflag
& SUFFIX_ALWAYS
)
12957 if (intel_mnemonic
!= cond
)
12961 if ((prefixes
& PREFIX_FWAIT
) == 0)
12964 used_prefixes
|= PREFIX_FWAIT
;
12970 else if (intel_syntax
&& (sizeflag
& DFLAG
))
12974 if (!(rex
& REX_W
))
12975 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12979 && address_mode
== mode_64bit
12980 && isa64
== intel64
)
12985 /* Fall through. */
12988 && address_mode
== mode_64bit
12989 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
12994 /* Fall through. */
12997 if (l
== 0 && len
== 1)
13002 if ((rex
& REX_W
) == 0
13003 && (prefixes
& PREFIX_DATA
))
13005 if ((sizeflag
& DFLAG
) == 0)
13007 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13011 if ((prefixes
& PREFIX_DATA
)
13013 || (sizeflag
& SUFFIX_ALWAYS
))
13020 if (sizeflag
& DFLAG
)
13024 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13030 if (l
!= 1 || len
!= 2 || last
[0] != 'L')
13036 if ((prefixes
& PREFIX_DATA
)
13038 || (sizeflag
& SUFFIX_ALWAYS
))
13045 if (sizeflag
& DFLAG
)
13046 *obufp
++ = intel_syntax
? 'd' : 'l';
13049 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13057 if (address_mode
== mode_64bit
13058 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13060 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
13064 /* Fall through. */
13067 if (l
== 0 && len
== 1)
13070 if (intel_syntax
&& !alt
)
13073 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
13079 if (sizeflag
& DFLAG
)
13080 *obufp
++ = intel_syntax
? 'd' : 'l';
13083 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13089 if (l
!= 1 || len
!= 2 || last
[0] != 'L')
13095 || (modrm
.mod
== 3 && !(sizeflag
& SUFFIX_ALWAYS
)))
13110 else if (sizeflag
& DFLAG
)
13119 if (intel_syntax
&& !p
[1]
13120 && ((rex
& REX_W
) || (sizeflag
& DFLAG
)))
13122 if (!(rex
& REX_W
))
13123 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13126 if (l
== 0 && len
== 1)
13130 if (address_mode
== mode_64bit
13131 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13133 if (sizeflag
& SUFFIX_ALWAYS
)
13155 /* Fall through. */
13158 if (l
== 0 && len
== 1)
13163 if (sizeflag
& SUFFIX_ALWAYS
)
13169 if (sizeflag
& DFLAG
)
13173 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13187 if (address_mode
== mode_64bit
13188 && !(prefixes
& PREFIX_ADDR
))
13199 if (l
!= 0 || len
!= 1)
13204 if (need_vex
&& vex
.prefix
)
13206 if (vex
.prefix
== DATA_PREFIX_OPCODE
)
13213 if (prefixes
& PREFIX_DATA
)
13217 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13221 if (l
== 0 && len
== 1)
13225 if (l
!= 1 || len
!= 2 || last
[0] != 'X')
13233 || ((modrm
.mod
== 3 || vex
.b
) && !(sizeflag
& SUFFIX_ALWAYS
)))
13235 switch (vex
.length
)
13251 if (l
== 0 && len
== 1)
13253 /* operand size flag for cwtl, cbtw */
13262 else if (sizeflag
& DFLAG
)
13266 if (!(rex
& REX_W
))
13267 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13274 && last
[0] != 'L'))
13281 if (last
[0] == 'X')
13282 *obufp
++ = vex
.w
? 'd': 's';
13284 *obufp
++ = vex
.w
? 'q': 'd';
13290 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
13292 if (sizeflag
& DFLAG
)
13296 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13302 if (address_mode
== mode_64bit
13303 && (isa64
== intel64
13304 || ((sizeflag
& DFLAG
) || (rex
& REX_W
))))
13306 else if ((prefixes
& PREFIX_DATA
))
13308 if (!(sizeflag
& DFLAG
))
13310 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13317 mnemonicendp
= obufp
;
13322 oappend (const char *s
)
13324 obufp
= stpcpy (obufp
, s
);
13330 /* Only print the active segment register. */
13331 if (!active_seg_prefix
)
13334 used_prefixes
|= active_seg_prefix
;
13335 switch (active_seg_prefix
)
13338 oappend_maybe_intel ("%cs:");
13341 oappend_maybe_intel ("%ds:");
13344 oappend_maybe_intel ("%ss:");
13347 oappend_maybe_intel ("%es:");
13350 oappend_maybe_intel ("%fs:");
13353 oappend_maybe_intel ("%gs:");
13361 OP_indirE (int bytemode
, int sizeflag
)
13365 OP_E (bytemode
, sizeflag
);
13369 print_operand_value (char *buf
, int hex
, bfd_vma disp
)
13371 if (address_mode
== mode_64bit
)
13379 sprintf_vma (tmp
, disp
);
13380 for (i
= 0; tmp
[i
] == '0' && tmp
[i
+ 1]; i
++);
13381 strcpy (buf
+ 2, tmp
+ i
);
13385 bfd_signed_vma v
= disp
;
13392 /* Check for possible overflow on 0x8000000000000000. */
13395 strcpy (buf
, "9223372036854775808");
13409 tmp
[28 - i
] = (v
% 10) + '0';
13413 strcpy (buf
, tmp
+ 29 - i
);
13419 sprintf (buf
, "0x%x", (unsigned int) disp
);
13421 sprintf (buf
, "%d", (int) disp
);
13425 /* Put DISP in BUF as signed hex number. */
13428 print_displacement (char *buf
, bfd_vma disp
)
13430 bfd_signed_vma val
= disp
;
13439 /* Check for possible overflow. */
13442 switch (address_mode
)
13445 strcpy (buf
+ j
, "0x8000000000000000");
13448 strcpy (buf
+ j
, "0x80000000");
13451 strcpy (buf
+ j
, "0x8000");
13461 sprintf_vma (tmp
, (bfd_vma
) val
);
13462 for (i
= 0; tmp
[i
] == '0'; i
++)
13464 if (tmp
[i
] == '\0')
13466 strcpy (buf
+ j
, tmp
+ i
);
13470 intel_operand_size (int bytemode
, int sizeflag
)
13474 && (bytemode
== x_mode
13475 || bytemode
== evex_half_bcst_xmmq_mode
))
13478 oappend ("QWORD PTR ");
13480 oappend ("DWORD PTR ");
13489 oappend ("BYTE PTR ");
13494 oappend ("WORD PTR ");
13497 if (address_mode
== mode_64bit
&& isa64
== intel64
)
13499 oappend ("QWORD PTR ");
13502 /* Fall through. */
13504 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13506 oappend ("QWORD PTR ");
13509 /* Fall through. */
13515 oappend ("QWORD PTR ");
13518 if ((sizeflag
& DFLAG
) || bytemode
== dq_mode
)
13519 oappend ("DWORD PTR ");
13521 oappend ("WORD PTR ");
13522 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13526 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
13528 oappend ("WORD PTR ");
13529 if (!(rex
& REX_W
))
13530 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13533 if (sizeflag
& DFLAG
)
13534 oappend ("QWORD PTR ");
13536 oappend ("DWORD PTR ");
13537 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13540 case d_scalar_mode
:
13541 case d_scalar_swap_mode
:
13544 oappend ("DWORD PTR ");
13547 case q_scalar_mode
:
13548 case q_scalar_swap_mode
:
13550 oappend ("QWORD PTR ");
13553 if (address_mode
== mode_64bit
)
13554 oappend ("QWORD PTR ");
13556 oappend ("DWORD PTR ");
13559 if (sizeflag
& DFLAG
)
13560 oappend ("FWORD PTR ");
13562 oappend ("DWORD PTR ");
13563 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13566 oappend ("TBYTE PTR ");
13570 case evex_x_gscat_mode
:
13571 case evex_x_nobcst_mode
:
13572 case b_scalar_mode
:
13573 case w_scalar_mode
:
13576 switch (vex
.length
)
13579 oappend ("XMMWORD PTR ");
13582 oappend ("YMMWORD PTR ");
13585 oappend ("ZMMWORD PTR ");
13592 oappend ("XMMWORD PTR ");
13595 oappend ("XMMWORD PTR ");
13598 oappend ("YMMWORD PTR ");
13601 case evex_half_bcst_xmmq_mode
:
13605 switch (vex
.length
)
13608 oappend ("QWORD PTR ");
13611 oappend ("XMMWORD PTR ");
13614 oappend ("YMMWORD PTR ");
13624 switch (vex
.length
)
13629 oappend ("BYTE PTR ");
13639 switch (vex
.length
)
13644 oappend ("WORD PTR ");
13654 switch (vex
.length
)
13659 oappend ("DWORD PTR ");
13669 switch (vex
.length
)
13674 oappend ("QWORD PTR ");
13684 switch (vex
.length
)
13687 oappend ("WORD PTR ");
13690 oappend ("DWORD PTR ");
13693 oappend ("QWORD PTR ");
13703 switch (vex
.length
)
13706 oappend ("DWORD PTR ");
13709 oappend ("QWORD PTR ");
13712 oappend ("XMMWORD PTR ");
13722 switch (vex
.length
)
13725 oappend ("QWORD PTR ");
13728 oappend ("YMMWORD PTR ");
13731 oappend ("ZMMWORD PTR ");
13741 switch (vex
.length
)
13745 oappend ("XMMWORD PTR ");
13752 oappend ("OWORD PTR ");
13755 case vex_w_dq_mode
:
13756 case vex_scalar_w_dq_mode
:
13761 oappend ("QWORD PTR ");
13763 oappend ("DWORD PTR ");
13765 case vex_vsib_d_w_dq_mode
:
13766 case vex_vsib_q_w_dq_mode
:
13773 oappend ("QWORD PTR ");
13775 oappend ("DWORD PTR ");
13779 switch (vex
.length
)
13782 oappend ("XMMWORD PTR ");
13785 oappend ("YMMWORD PTR ");
13788 oappend ("ZMMWORD PTR ");
13795 case vex_vsib_q_w_d_mode
:
13796 case vex_vsib_d_w_d_mode
:
13797 if (!need_vex
|| !vex
.evex
)
13800 switch (vex
.length
)
13803 oappend ("QWORD PTR ");
13806 oappend ("XMMWORD PTR ");
13809 oappend ("YMMWORD PTR ");
13817 if (!need_vex
|| vex
.length
!= 128)
13820 oappend ("DWORD PTR ");
13822 oappend ("BYTE PTR ");
13828 oappend ("QWORD PTR ");
13830 oappend ("WORD PTR ");
13840 OP_E_register (int bytemode
, int sizeflag
)
13842 int reg
= modrm
.rm
;
13843 const char **names
;
13849 if ((sizeflag
& SUFFIX_ALWAYS
)
13850 && (bytemode
== b_swap_mode
13851 || bytemode
== bnd_swap_mode
13852 || bytemode
== v_swap_mode
))
13878 names
= address_mode
== mode_64bit
? names64
: names32
;
13881 case bnd_swap_mode
:
13890 if (address_mode
== mode_64bit
&& isa64
== intel64
)
13895 /* Fall through. */
13897 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13903 /* Fall through. */
13915 if ((sizeflag
& DFLAG
)
13916 || (bytemode
!= v_mode
13917 && bytemode
!= v_swap_mode
))
13921 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13925 names
= (address_mode
== mode_64bit
13926 ? names64
: names32
);
13927 if (!(prefixes
& PREFIX_ADDR
))
13928 names
= (address_mode
== mode_16bit
13929 ? names16
: names
);
13932 /* Remove "addr16/addr32". */
13933 all_prefixes
[last_addr_prefix
] = 0;
13934 names
= (address_mode
!= mode_32bit
13935 ? names32
: names16
);
13936 used_prefixes
|= PREFIX_ADDR
;
13946 names
= names_mask
;
13951 oappend (INTERNAL_DISASSEMBLER_ERROR
);
13954 oappend (names
[reg
]);
13958 OP_E_memory (int bytemode
, int sizeflag
)
13961 int add
= (rex
& REX_B
) ? 8 : 0;
13967 /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */
13969 && bytemode
!= x_mode
13970 && bytemode
!= xmmq_mode
13971 && bytemode
!= evex_half_bcst_xmmq_mode
)
13987 if (address_mode
!= mode_64bit
)
13993 case vex_vsib_d_w_dq_mode
:
13994 case vex_vsib_d_w_d_mode
:
13995 case vex_vsib_q_w_dq_mode
:
13996 case vex_vsib_q_w_d_mode
:
13997 case evex_x_gscat_mode
:
13999 shift
= vex
.w
? 3 : 2;
14002 case evex_half_bcst_xmmq_mode
:
14006 shift
= vex
.w
? 3 : 2;
14009 /* Fall through. */
14013 case evex_x_nobcst_mode
:
14015 switch (vex
.length
)
14038 case q_scalar_mode
:
14040 case q_scalar_swap_mode
:
14046 case d_scalar_mode
:
14048 case d_scalar_swap_mode
:
14051 case w_scalar_mode
:
14055 case b_scalar_mode
:
14062 /* Make necessary corrections to shift for modes that need it.
14063 For these modes we currently have shift 4, 5 or 6 depending on
14064 vex.length (it corresponds to xmmword, ymmword or zmmword
14065 operand). We might want to make it 3, 4 or 5 (e.g. for
14066 xmmq_mode). In case of broadcast enabled the corrections
14067 aren't needed, as element size is always 32 or 64 bits. */
14069 && (bytemode
== xmmq_mode
14070 || bytemode
== evex_half_bcst_xmmq_mode
))
14072 else if (bytemode
== xmmqd_mode
)
14074 else if (bytemode
== xmmdw_mode
)
14076 else if (bytemode
== ymmq_mode
&& vex
.length
== 128)
14084 intel_operand_size (bytemode
, sizeflag
);
14087 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
14089 /* 32/64 bit address mode */
14099 int addr32flag
= !((sizeflag
& AFLAG
)
14100 || bytemode
== v_bnd_mode
14101 || bytemode
== v_bndmk_mode
14102 || bytemode
== bnd_mode
14103 || bytemode
== bnd_swap_mode
);
14104 const char **indexes64
= names64
;
14105 const char **indexes32
= names32
;
14115 vindex
= sib
.index
;
14121 case vex_vsib_d_w_dq_mode
:
14122 case vex_vsib_d_w_d_mode
:
14123 case vex_vsib_q_w_dq_mode
:
14124 case vex_vsib_q_w_d_mode
:
14134 switch (vex
.length
)
14137 indexes64
= indexes32
= names_xmm
;
14141 || bytemode
== vex_vsib_q_w_dq_mode
14142 || bytemode
== vex_vsib_q_w_d_mode
)
14143 indexes64
= indexes32
= names_ymm
;
14145 indexes64
= indexes32
= names_xmm
;
14149 || bytemode
== vex_vsib_q_w_dq_mode
14150 || bytemode
== vex_vsib_q_w_d_mode
)
14151 indexes64
= indexes32
= names_zmm
;
14153 indexes64
= indexes32
= names_ymm
;
14160 haveindex
= vindex
!= 4;
14167 rbase
= base
+ add
;
14175 if (address_mode
== mode_64bit
&& !havesib
)
14178 if (riprel
&& bytemode
== v_bndmk_mode
)
14186 FETCH_DATA (the_info
, codep
+ 1);
14188 if ((disp
& 0x80) != 0)
14190 if (vex
.evex
&& shift
> 0)
14203 && address_mode
!= mode_16bit
)
14205 if (address_mode
== mode_64bit
)
14207 /* Display eiz instead of addr32. */
14208 needindex
= addr32flag
;
14213 /* In 32-bit mode, we need index register to tell [offset]
14214 from [eiz*1 + offset]. */
14219 havedisp
= (havebase
14221 || (havesib
&& (haveindex
|| scale
!= 0)));
14224 if (modrm
.mod
!= 0 || base
== 5)
14226 if (havedisp
|| riprel
)
14227 print_displacement (scratchbuf
, disp
);
14229 print_operand_value (scratchbuf
, 1, disp
);
14230 oappend (scratchbuf
);
14234 oappend (!addr32flag
? "(%rip)" : "(%eip)");
14238 if ((havebase
|| haveindex
|| needindex
|| needaddr32
|| riprel
)
14239 && (bytemode
!= v_bnd_mode
)
14240 && (bytemode
!= v_bndmk_mode
)
14241 && (bytemode
!= bnd_mode
)
14242 && (bytemode
!= bnd_swap_mode
))
14243 used_prefixes
|= PREFIX_ADDR
;
14245 if (havedisp
|| (intel_syntax
&& riprel
))
14247 *obufp
++ = open_char
;
14248 if (intel_syntax
&& riprel
)
14251 oappend (!addr32flag
? "rip" : "eip");
14255 oappend (address_mode
== mode_64bit
&& !addr32flag
14256 ? names64
[rbase
] : names32
[rbase
]);
14259 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
14260 print index to tell base + index from base. */
14264 || (havebase
&& base
!= ESP_REG_NUM
))
14266 if (!intel_syntax
|| havebase
)
14268 *obufp
++ = separator_char
;
14272 oappend (address_mode
== mode_64bit
&& !addr32flag
14273 ? indexes64
[vindex
] : indexes32
[vindex
]);
14275 oappend (address_mode
== mode_64bit
&& !addr32flag
14276 ? index64
: index32
);
14278 *obufp
++ = scale_char
;
14280 sprintf (scratchbuf
, "%d", 1 << scale
);
14281 oappend (scratchbuf
);
14285 && (disp
|| modrm
.mod
!= 0 || base
== 5))
14287 if (!havedisp
|| (bfd_signed_vma
) disp
>= 0)
14292 else if (modrm
.mod
!= 1 && disp
!= -disp
)
14296 disp
= - (bfd_signed_vma
) disp
;
14300 print_displacement (scratchbuf
, disp
);
14302 print_operand_value (scratchbuf
, 1, disp
);
14303 oappend (scratchbuf
);
14306 *obufp
++ = close_char
;
14309 else if (intel_syntax
)
14311 if (modrm
.mod
!= 0 || base
== 5)
14313 if (!active_seg_prefix
)
14315 oappend (names_seg
[ds_reg
- es_reg
]);
14318 print_operand_value (scratchbuf
, 1, disp
);
14319 oappend (scratchbuf
);
14325 /* 16 bit address mode */
14326 used_prefixes
|= prefixes
& PREFIX_ADDR
;
14333 if ((disp
& 0x8000) != 0)
14338 FETCH_DATA (the_info
, codep
+ 1);
14340 if ((disp
& 0x80) != 0)
14342 if (vex
.evex
&& shift
> 0)
14347 if ((disp
& 0x8000) != 0)
14353 if (modrm
.mod
!= 0 || modrm
.rm
== 6)
14355 print_displacement (scratchbuf
, disp
);
14356 oappend (scratchbuf
);
14359 if (modrm
.mod
!= 0 || modrm
.rm
!= 6)
14361 *obufp
++ = open_char
;
14363 oappend (index16
[modrm
.rm
]);
14365 && (disp
|| modrm
.mod
!= 0 || modrm
.rm
== 6))
14367 if ((bfd_signed_vma
) disp
>= 0)
14372 else if (modrm
.mod
!= 1)
14376 disp
= - (bfd_signed_vma
) disp
;
14379 print_displacement (scratchbuf
, disp
);
14380 oappend (scratchbuf
);
14383 *obufp
++ = close_char
;
14386 else if (intel_syntax
)
14388 if (!active_seg_prefix
)
14390 oappend (names_seg
[ds_reg
- es_reg
]);
14393 print_operand_value (scratchbuf
, 1, disp
& 0xffff);
14394 oappend (scratchbuf
);
14397 if (vex
.evex
&& vex
.b
14398 && (bytemode
== x_mode
14399 || bytemode
== xmmq_mode
14400 || bytemode
== evex_half_bcst_xmmq_mode
))
14403 || bytemode
== xmmq_mode
14404 || bytemode
== evex_half_bcst_xmmq_mode
)
14406 switch (vex
.length
)
14409 oappend ("{1to2}");
14412 oappend ("{1to4}");
14415 oappend ("{1to8}");
14423 switch (vex
.length
)
14426 oappend ("{1to4}");
14429 oappend ("{1to8}");
14432 oappend ("{1to16}");
14442 OP_E (int bytemode
, int sizeflag
)
14444 /* Skip mod/rm byte. */
14448 if (modrm
.mod
== 3)
14449 OP_E_register (bytemode
, sizeflag
);
14451 OP_E_memory (bytemode
, sizeflag
);
14455 OP_G (int bytemode
, int sizeflag
)
14458 const char **names
;
14467 oappend (names8rex
[modrm
.reg
+ add
]);
14469 oappend (names8
[modrm
.reg
+ add
]);
14472 oappend (names16
[modrm
.reg
+ add
]);
14477 oappend (names32
[modrm
.reg
+ add
]);
14480 oappend (names64
[modrm
.reg
+ add
]);
14483 if (modrm
.reg
> 0x3)
14488 oappend (names_bnd
[modrm
.reg
]);
14497 oappend (names64
[modrm
.reg
+ add
]);
14500 if ((sizeflag
& DFLAG
) || bytemode
!= v_mode
)
14501 oappend (names32
[modrm
.reg
+ add
]);
14503 oappend (names16
[modrm
.reg
+ add
]);
14504 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14508 names
= (address_mode
== mode_64bit
14509 ? names64
: names32
);
14510 if (!(prefixes
& PREFIX_ADDR
))
14512 if (address_mode
== mode_16bit
)
14517 /* Remove "addr16/addr32". */
14518 all_prefixes
[last_addr_prefix
] = 0;
14519 names
= (address_mode
!= mode_32bit
14520 ? names32
: names16
);
14521 used_prefixes
|= PREFIX_ADDR
;
14523 oappend (names
[modrm
.reg
+ add
]);
14526 if (address_mode
== mode_64bit
)
14527 oappend (names64
[modrm
.reg
+ add
]);
14529 oappend (names32
[modrm
.reg
+ add
]);
14533 if ((modrm
.reg
+ add
) > 0x7)
14538 oappend (names_mask
[modrm
.reg
+ add
]);
14541 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14554 FETCH_DATA (the_info
, codep
+ 8);
14555 a
= *codep
++ & 0xff;
14556 a
|= (*codep
++ & 0xff) << 8;
14557 a
|= (*codep
++ & 0xff) << 16;
14558 a
|= (*codep
++ & 0xffu
) << 24;
14559 b
= *codep
++ & 0xff;
14560 b
|= (*codep
++ & 0xff) << 8;
14561 b
|= (*codep
++ & 0xff) << 16;
14562 b
|= (*codep
++ & 0xffu
) << 24;
14563 x
= a
+ ((bfd_vma
) b
<< 32);
14571 static bfd_signed_vma
14574 bfd_signed_vma x
= 0;
14576 FETCH_DATA (the_info
, codep
+ 4);
14577 x
= *codep
++ & (bfd_signed_vma
) 0xff;
14578 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
14579 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
14580 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
14584 static bfd_signed_vma
14587 bfd_signed_vma x
= 0;
14589 FETCH_DATA (the_info
, codep
+ 4);
14590 x
= *codep
++ & (bfd_signed_vma
) 0xff;
14591 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
14592 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
14593 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
14595 x
= (x
^ ((bfd_signed_vma
) 1 << 31)) - ((bfd_signed_vma
) 1 << 31);
14605 FETCH_DATA (the_info
, codep
+ 2);
14606 x
= *codep
++ & 0xff;
14607 x
|= (*codep
++ & 0xff) << 8;
14612 set_op (bfd_vma op
, int riprel
)
14614 op_index
[op_ad
] = op_ad
;
14615 if (address_mode
== mode_64bit
)
14617 op_address
[op_ad
] = op
;
14618 op_riprel
[op_ad
] = riprel
;
14622 /* Mask to get a 32-bit address. */
14623 op_address
[op_ad
] = op
& 0xffffffff;
14624 op_riprel
[op_ad
] = riprel
& 0xffffffff;
14629 OP_REG (int code
, int sizeflag
)
14636 case es_reg
: case ss_reg
: case cs_reg
:
14637 case ds_reg
: case fs_reg
: case gs_reg
:
14638 oappend (names_seg
[code
- es_reg
]);
14650 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
14651 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
14652 s
= names16
[code
- ax_reg
+ add
];
14654 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
14655 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
14658 s
= names8rex
[code
- al_reg
+ add
];
14660 s
= names8
[code
- al_reg
];
14662 case rAX_reg
: case rCX_reg
: case rDX_reg
: case rBX_reg
:
14663 case rSP_reg
: case rBP_reg
: case rSI_reg
: case rDI_reg
:
14664 if (address_mode
== mode_64bit
14665 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14667 s
= names64
[code
- rAX_reg
+ add
];
14670 code
+= eAX_reg
- rAX_reg
;
14671 /* Fall through. */
14672 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
14673 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
14676 s
= names64
[code
- eAX_reg
+ add
];
14679 if (sizeflag
& DFLAG
)
14680 s
= names32
[code
- eAX_reg
+ add
];
14682 s
= names16
[code
- eAX_reg
+ add
];
14683 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14687 s
= INTERNAL_DISASSEMBLER_ERROR
;
14694 OP_IMREG (int code
, int sizeflag
)
14706 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
14707 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
14708 s
= names16
[code
- ax_reg
];
14710 case es_reg
: case ss_reg
: case cs_reg
:
14711 case ds_reg
: case fs_reg
: case gs_reg
:
14712 s
= names_seg
[code
- es_reg
];
14714 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
14715 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
14718 s
= names8rex
[code
- al_reg
];
14720 s
= names8
[code
- al_reg
];
14722 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
14723 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
14726 s
= names64
[code
- eAX_reg
];
14729 if (sizeflag
& DFLAG
)
14730 s
= names32
[code
- eAX_reg
];
14732 s
= names16
[code
- eAX_reg
];
14733 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14736 case z_mode_ax_reg
:
14737 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
14741 if (!(rex
& REX_W
))
14742 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14745 s
= INTERNAL_DISASSEMBLER_ERROR
;
14752 OP_I (int bytemode
, int sizeflag
)
14755 bfd_signed_vma mask
= -1;
14760 FETCH_DATA (the_info
, codep
+ 1);
14770 if (sizeflag
& DFLAG
)
14780 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14796 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14801 scratchbuf
[0] = '$';
14802 print_operand_value (scratchbuf
+ 1, 1, op
);
14803 oappend_maybe_intel (scratchbuf
);
14804 scratchbuf
[0] = '\0';
14808 OP_I64 (int bytemode
, int sizeflag
)
14810 if (bytemode
!= v_mode
|| address_mode
!= mode_64bit
|| !(rex
& REX_W
))
14812 OP_I (bytemode
, sizeflag
);
14818 scratchbuf
[0] = '$';
14819 print_operand_value (scratchbuf
+ 1, 1, get64 ());
14820 oappend_maybe_intel (scratchbuf
);
14821 scratchbuf
[0] = '\0';
14825 OP_sI (int bytemode
, int sizeflag
)
14833 FETCH_DATA (the_info
, codep
+ 1);
14835 if ((op
& 0x80) != 0)
14837 if (bytemode
== b_T_mode
)
14839 if (address_mode
!= mode_64bit
14840 || !((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14842 /* The operand-size prefix is overridden by a REX prefix. */
14843 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
14851 if (!(rex
& REX_W
))
14853 if (sizeflag
& DFLAG
)
14861 /* The operand-size prefix is overridden by a REX prefix. */
14862 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
14868 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14872 scratchbuf
[0] = '$';
14873 print_operand_value (scratchbuf
+ 1, 1, op
);
14874 oappend_maybe_intel (scratchbuf
);
14878 OP_J (int bytemode
, int sizeflag
)
14882 bfd_vma segment
= 0;
14887 FETCH_DATA (the_info
, codep
+ 1);
14889 if ((disp
& 0x80) != 0)
14893 if (isa64
!= intel64
)
14896 if ((sizeflag
& DFLAG
)
14897 || (address_mode
== mode_64bit
14898 && ((isa64
== intel64
&& bytemode
!= dqw_mode
)
14899 || (rex
& REX_W
))))
14904 if ((disp
& 0x8000) != 0)
14906 /* In 16bit mode, address is wrapped around at 64k within
14907 the same segment. Otherwise, a data16 prefix on a jump
14908 instruction means that the pc is masked to 16 bits after
14909 the displacement is added! */
14911 if ((prefixes
& PREFIX_DATA
) == 0)
14912 segment
= ((start_pc
+ (codep
- start_codep
))
14913 & ~((bfd_vma
) 0xffff));
14915 if (address_mode
!= mode_64bit
14916 || (isa64
!= intel64
&& !(rex
& REX_W
)))
14917 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14920 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14923 disp
= ((start_pc
+ (codep
- start_codep
) + disp
) & mask
) | segment
;
14925 print_operand_value (scratchbuf
, 1, disp
);
14926 oappend (scratchbuf
);
14930 OP_SEG (int bytemode
, int sizeflag
)
14932 if (bytemode
== w_mode
)
14933 oappend (names_seg
[modrm
.reg
]);
14935 OP_E (modrm
.mod
== 3 ? bytemode
: w_mode
, sizeflag
);
14939 OP_DIR (int dummy ATTRIBUTE_UNUSED
, int sizeflag
)
14943 if (sizeflag
& DFLAG
)
14953 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14955 sprintf (scratchbuf
, "0x%x:0x%x", seg
, offset
);
14957 sprintf (scratchbuf
, "$0x%x,$0x%x", seg
, offset
);
14958 oappend (scratchbuf
);
14962 OP_OFF (int bytemode
, int sizeflag
)
14966 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
14967 intel_operand_size (bytemode
, sizeflag
);
14970 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
14977 if (!active_seg_prefix
)
14979 oappend (names_seg
[ds_reg
- es_reg
]);
14983 print_operand_value (scratchbuf
, 1, off
);
14984 oappend (scratchbuf
);
14988 OP_OFF64 (int bytemode
, int sizeflag
)
14992 if (address_mode
!= mode_64bit
14993 || (prefixes
& PREFIX_ADDR
))
14995 OP_OFF (bytemode
, sizeflag
);
14999 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
15000 intel_operand_size (bytemode
, sizeflag
);
15007 if (!active_seg_prefix
)
15009 oappend (names_seg
[ds_reg
- es_reg
]);
15013 print_operand_value (scratchbuf
, 1, off
);
15014 oappend (scratchbuf
);
15018 ptr_reg (int code
, int sizeflag
)
15022 *obufp
++ = open_char
;
15023 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
15024 if (address_mode
== mode_64bit
)
15026 if (!(sizeflag
& AFLAG
))
15027 s
= names32
[code
- eAX_reg
];
15029 s
= names64
[code
- eAX_reg
];
15031 else if (sizeflag
& AFLAG
)
15032 s
= names32
[code
- eAX_reg
];
15034 s
= names16
[code
- eAX_reg
];
15036 *obufp
++ = close_char
;
15041 OP_ESreg (int code
, int sizeflag
)
15047 case 0x6d: /* insw/insl */
15048 intel_operand_size (z_mode
, sizeflag
);
15050 case 0xa5: /* movsw/movsl/movsq */
15051 case 0xa7: /* cmpsw/cmpsl/cmpsq */
15052 case 0xab: /* stosw/stosl */
15053 case 0xaf: /* scasw/scasl */
15054 intel_operand_size (v_mode
, sizeflag
);
15057 intel_operand_size (b_mode
, sizeflag
);
15060 oappend_maybe_intel ("%es:");
15061 ptr_reg (code
, sizeflag
);
15065 OP_DSreg (int code
, int sizeflag
)
15071 case 0x6f: /* outsw/outsl */
15072 intel_operand_size (z_mode
, sizeflag
);
15074 case 0xa5: /* movsw/movsl/movsq */
15075 case 0xa7: /* cmpsw/cmpsl/cmpsq */
15076 case 0xad: /* lodsw/lodsl/lodsq */
15077 intel_operand_size (v_mode
, sizeflag
);
15080 intel_operand_size (b_mode
, sizeflag
);
15083 /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
15084 default segment register DS is printed. */
15085 if (!active_seg_prefix
)
15086 active_seg_prefix
= PREFIX_DS
;
15088 ptr_reg (code
, sizeflag
);
15092 OP_C (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15100 else if (address_mode
!= mode_64bit
&& (prefixes
& PREFIX_LOCK
))
15102 all_prefixes
[last_lock_prefix
] = 0;
15103 used_prefixes
|= PREFIX_LOCK
;
15108 sprintf (scratchbuf
, "%%cr%d", modrm
.reg
+ add
);
15109 oappend_maybe_intel (scratchbuf
);
15113 OP_D (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15122 sprintf (scratchbuf
, "db%d", modrm
.reg
+ add
);
15124 sprintf (scratchbuf
, "%%db%d", modrm
.reg
+ add
);
15125 oappend (scratchbuf
);
15129 OP_T (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15131 sprintf (scratchbuf
, "%%tr%d", modrm
.reg
);
15132 oappend_maybe_intel (scratchbuf
);
15136 OP_R (int bytemode
, int sizeflag
)
15138 /* Skip mod/rm byte. */
15141 OP_E_register (bytemode
, sizeflag
);
15145 OP_MMX (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15147 int reg
= modrm
.reg
;
15148 const char **names
;
15150 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15151 if (prefixes
& PREFIX_DATA
)
15160 oappend (names
[reg
]);
15164 OP_XMM (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
15166 int reg
= modrm
.reg
;
15167 const char **names
;
15179 && bytemode
!= xmm_mode
15180 && bytemode
!= xmmq_mode
15181 && bytemode
!= evex_half_bcst_xmmq_mode
15182 && bytemode
!= ymm_mode
15183 && bytemode
!= scalar_mode
)
15185 switch (vex
.length
)
15192 || (bytemode
!= vex_vsib_q_w_dq_mode
15193 && bytemode
!= vex_vsib_q_w_d_mode
))
15205 else if (bytemode
== xmmq_mode
15206 || bytemode
== evex_half_bcst_xmmq_mode
)
15208 switch (vex
.length
)
15221 else if (bytemode
== ymm_mode
)
15225 oappend (names
[reg
]);
15229 OP_EM (int bytemode
, int sizeflag
)
15232 const char **names
;
15234 if (modrm
.mod
!= 3)
15237 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
15239 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
15240 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15242 OP_E (bytemode
, sizeflag
);
15246 if ((sizeflag
& SUFFIX_ALWAYS
) && bytemode
== v_swap_mode
)
15249 /* Skip mod/rm byte. */
15252 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15254 if (prefixes
& PREFIX_DATA
)
15263 oappend (names
[reg
]);
15266 /* cvt* are the only instructions in sse2 which have
15267 both SSE and MMX operands and also have 0x66 prefix
15268 in their opcode. 0x66 was originally used to differentiate
15269 between SSE and MMX instruction(operands). So we have to handle the
15270 cvt* separately using OP_EMC and OP_MXC */
15272 OP_EMC (int bytemode
, int sizeflag
)
15274 if (modrm
.mod
!= 3)
15276 if (intel_syntax
&& bytemode
== v_mode
)
15278 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
15279 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15281 OP_E (bytemode
, sizeflag
);
15285 /* Skip mod/rm byte. */
15288 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15289 oappend (names_mm
[modrm
.rm
]);
15293 OP_MXC (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15295 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15296 oappend (names_mm
[modrm
.reg
]);
15300 OP_EX (int bytemode
, int sizeflag
)
15303 const char **names
;
15305 /* Skip mod/rm byte. */
15309 if (modrm
.mod
!= 3)
15311 OP_E_memory (bytemode
, sizeflag
);
15326 if ((sizeflag
& SUFFIX_ALWAYS
)
15327 && (bytemode
== x_swap_mode
15328 || bytemode
== d_swap_mode
15329 || bytemode
== d_scalar_swap_mode
15330 || bytemode
== q_swap_mode
15331 || bytemode
== q_scalar_swap_mode
))
15335 && bytemode
!= xmm_mode
15336 && bytemode
!= xmmdw_mode
15337 && bytemode
!= xmmqd_mode
15338 && bytemode
!= xmm_mb_mode
15339 && bytemode
!= xmm_mw_mode
15340 && bytemode
!= xmm_md_mode
15341 && bytemode
!= xmm_mq_mode
15342 && bytemode
!= xmm_mdq_mode
15343 && bytemode
!= xmmq_mode
15344 && bytemode
!= evex_half_bcst_xmmq_mode
15345 && bytemode
!= ymm_mode
15346 && bytemode
!= d_scalar_mode
15347 && bytemode
!= d_scalar_swap_mode
15348 && bytemode
!= q_scalar_mode
15349 && bytemode
!= q_scalar_swap_mode
15350 && bytemode
!= vex_scalar_w_dq_mode
)
15352 switch (vex
.length
)
15367 else if (bytemode
== xmmq_mode
15368 || bytemode
== evex_half_bcst_xmmq_mode
)
15370 switch (vex
.length
)
15383 else if (bytemode
== ymm_mode
)
15387 oappend (names
[reg
]);
15391 OP_MS (int bytemode
, int sizeflag
)
15393 if (modrm
.mod
== 3)
15394 OP_EM (bytemode
, sizeflag
);
15400 OP_XS (int bytemode
, int sizeflag
)
15402 if (modrm
.mod
== 3)
15403 OP_EX (bytemode
, sizeflag
);
15409 OP_M (int bytemode
, int sizeflag
)
15411 if (modrm
.mod
== 3)
15412 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
15415 OP_E (bytemode
, sizeflag
);
15419 OP_0f07 (int bytemode
, int sizeflag
)
15421 if (modrm
.mod
!= 3 || modrm
.rm
!= 0)
15424 OP_E (bytemode
, sizeflag
);
15427 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
15428 32bit mode and "xchg %rax,%rax" in 64bit mode. */
15431 NOP_Fixup1 (int bytemode
, int sizeflag
)
15433 if ((prefixes
& PREFIX_DATA
) != 0
15436 && address_mode
== mode_64bit
))
15437 OP_REG (bytemode
, sizeflag
);
15439 strcpy (obuf
, "nop");
15443 NOP_Fixup2 (int bytemode
, int sizeflag
)
15445 if ((prefixes
& PREFIX_DATA
) != 0
15448 && address_mode
== mode_64bit
))
15449 OP_IMREG (bytemode
, sizeflag
);
15452 static const char *const Suffix3DNow
[] = {
15453 /* 00 */ NULL
, NULL
, NULL
, NULL
,
15454 /* 04 */ NULL
, NULL
, NULL
, NULL
,
15455 /* 08 */ NULL
, NULL
, NULL
, NULL
,
15456 /* 0C */ "pi2fw", "pi2fd", NULL
, NULL
,
15457 /* 10 */ NULL
, NULL
, NULL
, NULL
,
15458 /* 14 */ NULL
, NULL
, NULL
, NULL
,
15459 /* 18 */ NULL
, NULL
, NULL
, NULL
,
15460 /* 1C */ "pf2iw", "pf2id", NULL
, NULL
,
15461 /* 20 */ NULL
, NULL
, NULL
, NULL
,
15462 /* 24 */ NULL
, NULL
, NULL
, NULL
,
15463 /* 28 */ NULL
, NULL
, NULL
, NULL
,
15464 /* 2C */ NULL
, NULL
, NULL
, NULL
,
15465 /* 30 */ NULL
, NULL
, NULL
, NULL
,
15466 /* 34 */ NULL
, NULL
, NULL
, NULL
,
15467 /* 38 */ NULL
, NULL
, NULL
, NULL
,
15468 /* 3C */ NULL
, NULL
, NULL
, NULL
,
15469 /* 40 */ NULL
, NULL
, NULL
, NULL
,
15470 /* 44 */ NULL
, NULL
, NULL
, NULL
,
15471 /* 48 */ NULL
, NULL
, NULL
, NULL
,
15472 /* 4C */ NULL
, NULL
, NULL
, NULL
,
15473 /* 50 */ NULL
, NULL
, NULL
, NULL
,
15474 /* 54 */ NULL
, NULL
, NULL
, NULL
,
15475 /* 58 */ NULL
, NULL
, NULL
, NULL
,
15476 /* 5C */ NULL
, NULL
, NULL
, NULL
,
15477 /* 60 */ NULL
, NULL
, NULL
, NULL
,
15478 /* 64 */ NULL
, NULL
, NULL
, NULL
,
15479 /* 68 */ NULL
, NULL
, NULL
, NULL
,
15480 /* 6C */ NULL
, NULL
, NULL
, NULL
,
15481 /* 70 */ NULL
, NULL
, NULL
, NULL
,
15482 /* 74 */ NULL
, NULL
, NULL
, NULL
,
15483 /* 78 */ NULL
, NULL
, NULL
, NULL
,
15484 /* 7C */ NULL
, NULL
, NULL
, NULL
,
15485 /* 80 */ NULL
, NULL
, NULL
, NULL
,
15486 /* 84 */ NULL
, NULL
, NULL
, NULL
,
15487 /* 88 */ NULL
, NULL
, "pfnacc", NULL
,
15488 /* 8C */ NULL
, NULL
, "pfpnacc", NULL
,
15489 /* 90 */ "pfcmpge", NULL
, NULL
, NULL
,
15490 /* 94 */ "pfmin", NULL
, "pfrcp", "pfrsqrt",
15491 /* 98 */ NULL
, NULL
, "pfsub", NULL
,
15492 /* 9C */ NULL
, NULL
, "pfadd", NULL
,
15493 /* A0 */ "pfcmpgt", NULL
, NULL
, NULL
,
15494 /* A4 */ "pfmax", NULL
, "pfrcpit1", "pfrsqit1",
15495 /* A8 */ NULL
, NULL
, "pfsubr", NULL
,
15496 /* AC */ NULL
, NULL
, "pfacc", NULL
,
15497 /* B0 */ "pfcmpeq", NULL
, NULL
, NULL
,
15498 /* B4 */ "pfmul", NULL
, "pfrcpit2", "pmulhrw",
15499 /* B8 */ NULL
, NULL
, NULL
, "pswapd",
15500 /* BC */ NULL
, NULL
, NULL
, "pavgusb",
15501 /* C0 */ NULL
, NULL
, NULL
, NULL
,
15502 /* C4 */ NULL
, NULL
, NULL
, NULL
,
15503 /* C8 */ NULL
, NULL
, NULL
, NULL
,
15504 /* CC */ NULL
, NULL
, NULL
, NULL
,
15505 /* D0 */ NULL
, NULL
, NULL
, NULL
,
15506 /* D4 */ NULL
, NULL
, NULL
, NULL
,
15507 /* D8 */ NULL
, NULL
, NULL
, NULL
,
15508 /* DC */ NULL
, NULL
, NULL
, NULL
,
15509 /* E0 */ NULL
, NULL
, NULL
, NULL
,
15510 /* E4 */ NULL
, NULL
, NULL
, NULL
,
15511 /* E8 */ NULL
, NULL
, NULL
, NULL
,
15512 /* EC */ NULL
, NULL
, NULL
, NULL
,
15513 /* F0 */ NULL
, NULL
, NULL
, NULL
,
15514 /* F4 */ NULL
, NULL
, NULL
, NULL
,
15515 /* F8 */ NULL
, NULL
, NULL
, NULL
,
15516 /* FC */ NULL
, NULL
, NULL
, NULL
,
15520 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15522 const char *mnemonic
;
15524 FETCH_DATA (the_info
, codep
+ 1);
15525 /* AMD 3DNow! instructions are specified by an opcode suffix in the
15526 place where an 8-bit immediate would normally go. ie. the last
15527 byte of the instruction. */
15528 obufp
= mnemonicendp
;
15529 mnemonic
= Suffix3DNow
[*codep
++ & 0xff];
15531 oappend (mnemonic
);
15534 /* Since a variable sized modrm/sib chunk is between the start
15535 of the opcode (0x0f0f) and the opcode suffix, we need to do
15536 all the modrm processing first, and don't know until now that
15537 we have a bad opcode. This necessitates some cleaning up. */
15538 op_out
[0][0] = '\0';
15539 op_out
[1][0] = '\0';
15542 mnemonicendp
= obufp
;
15545 static struct op simd_cmp_op
[] =
15547 { STRING_COMMA_LEN ("eq") },
15548 { STRING_COMMA_LEN ("lt") },
15549 { STRING_COMMA_LEN ("le") },
15550 { STRING_COMMA_LEN ("unord") },
15551 { STRING_COMMA_LEN ("neq") },
15552 { STRING_COMMA_LEN ("nlt") },
15553 { STRING_COMMA_LEN ("nle") },
15554 { STRING_COMMA_LEN ("ord") }
15558 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15560 unsigned int cmp_type
;
15562 FETCH_DATA (the_info
, codep
+ 1);
15563 cmp_type
= *codep
++ & 0xff;
15564 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
))
15567 char *p
= mnemonicendp
- 2;
15571 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
15572 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
15576 /* We have a reserved extension byte. Output it directly. */
15577 scratchbuf
[0] = '$';
15578 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
15579 oappend_maybe_intel (scratchbuf
);
15580 scratchbuf
[0] = '\0';
15585 OP_Mwait (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
15587 /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx */
15590 strcpy (op_out
[0], names32
[0]);
15591 strcpy (op_out
[1], names32
[1]);
15592 if (bytemode
== eBX_reg
)
15593 strcpy (op_out
[2], names32
[3]);
15594 two_source_ops
= 1;
15596 /* Skip mod/rm byte. */
15602 OP_Monitor (int bytemode ATTRIBUTE_UNUSED
,
15603 int sizeflag ATTRIBUTE_UNUSED
)
15605 /* monitor %{e,r,}ax,%ecx,%edx" */
15608 const char **names
= (address_mode
== mode_64bit
15609 ? names64
: names32
);
15611 if (prefixes
& PREFIX_ADDR
)
15613 /* Remove "addr16/addr32". */
15614 all_prefixes
[last_addr_prefix
] = 0;
15615 names
= (address_mode
!= mode_32bit
15616 ? names32
: names16
);
15617 used_prefixes
|= PREFIX_ADDR
;
15619 else if (address_mode
== mode_16bit
)
15621 strcpy (op_out
[0], names
[0]);
15622 strcpy (op_out
[1], names32
[1]);
15623 strcpy (op_out
[2], names32
[2]);
15624 two_source_ops
= 1;
15626 /* Skip mod/rm byte. */
15634 /* Throw away prefixes and 1st. opcode byte. */
15635 codep
= insn_codep
+ 1;
15640 REP_Fixup (int bytemode
, int sizeflag
)
15642 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
15644 if (prefixes
& PREFIX_REPZ
)
15645 all_prefixes
[last_repz_prefix
] = REP_PREFIX
;
15652 OP_IMREG (bytemode
, sizeflag
);
15655 OP_ESreg (bytemode
, sizeflag
);
15658 OP_DSreg (bytemode
, sizeflag
);
15667 SEP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15669 if ( isa64
!= amd64
)
15674 mnemonicendp
= obufp
;
15678 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
15682 BND_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15684 if (prefixes
& PREFIX_REPNZ
)
15685 all_prefixes
[last_repnz_prefix
] = BND_PREFIX
;
15688 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
15692 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED
,
15693 int sizeflag ATTRIBUTE_UNUSED
)
15695 if (active_seg_prefix
== PREFIX_DS
15696 && (address_mode
!= mode_64bit
|| last_data_prefix
< 0))
15698 /* NOTRACK prefix is only valid on indirect branch instructions.
15699 NB: DATA prefix is unsupported for Intel64. */
15700 active_seg_prefix
= 0;
15701 all_prefixes
[last_seg_prefix
] = NOTRACK_PREFIX
;
15705 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
15706 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
15710 HLE_Fixup1 (int bytemode
, int sizeflag
)
15713 && (prefixes
& PREFIX_LOCK
) != 0)
15715 if (prefixes
& PREFIX_REPZ
)
15716 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
15717 if (prefixes
& PREFIX_REPNZ
)
15718 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
15721 OP_E (bytemode
, sizeflag
);
15724 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
15725 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
15729 HLE_Fixup2 (int bytemode
, int sizeflag
)
15731 if (modrm
.mod
!= 3)
15733 if (prefixes
& PREFIX_REPZ
)
15734 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
15735 if (prefixes
& PREFIX_REPNZ
)
15736 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
15739 OP_E (bytemode
, sizeflag
);
15742 /* Similar to OP_E. But the 0xf3 prefixes should be displayed as
15743 "xrelease" for memory operand. No check for LOCK prefix. */
15746 HLE_Fixup3 (int bytemode
, int sizeflag
)
15749 && last_repz_prefix
> last_repnz_prefix
15750 && (prefixes
& PREFIX_REPZ
) != 0)
15751 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
15753 OP_E (bytemode
, sizeflag
);
15757 CMPXCHG8B_Fixup (int bytemode
, int sizeflag
)
15762 /* Change cmpxchg8b to cmpxchg16b. */
15763 char *p
= mnemonicendp
- 2;
15764 mnemonicendp
= stpcpy (p
, "16b");
15767 else if ((prefixes
& PREFIX_LOCK
) != 0)
15769 if (prefixes
& PREFIX_REPZ
)
15770 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
15771 if (prefixes
& PREFIX_REPNZ
)
15772 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
15775 OP_M (bytemode
, sizeflag
);
15779 XMM_Fixup (int reg
, int sizeflag ATTRIBUTE_UNUSED
)
15781 const char **names
;
15785 switch (vex
.length
)
15799 oappend (names
[reg
]);
15803 CRC32_Fixup (int bytemode
, int sizeflag
)
15805 /* Add proper suffix to "crc32". */
15806 char *p
= mnemonicendp
;
15825 if (sizeflag
& DFLAG
)
15829 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15833 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15840 if (modrm
.mod
== 3)
15844 /* Skip mod/rm byte. */
15849 add
= (rex
& REX_B
) ? 8 : 0;
15850 if (bytemode
== b_mode
)
15854 oappend (names8rex
[modrm
.rm
+ add
]);
15856 oappend (names8
[modrm
.rm
+ add
]);
15862 oappend (names64
[modrm
.rm
+ add
]);
15863 else if ((prefixes
& PREFIX_DATA
))
15864 oappend (names16
[modrm
.rm
+ add
]);
15866 oappend (names32
[modrm
.rm
+ add
]);
15870 OP_E (bytemode
, sizeflag
);
15874 FXSAVE_Fixup (int bytemode
, int sizeflag
)
15876 /* Add proper suffix to "fxsave" and "fxrstor". */
15880 char *p
= mnemonicendp
;
15886 OP_M (bytemode
, sizeflag
);
15890 PCMPESTR_Fixup (int bytemode
, int sizeflag
)
15892 /* Add proper suffix to "{,v}pcmpestr{i,m}". */
15895 char *p
= mnemonicendp
;
15900 else if (sizeflag
& SUFFIX_ALWAYS
)
15907 OP_EX (bytemode
, sizeflag
);
15910 /* Display the destination register operand for instructions with
15914 OP_VEX (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
15917 const char **names
;
15925 reg
= vex
.register_specifier
;
15926 vex
.register_specifier
= 0;
15927 if (address_mode
!= mode_64bit
)
15929 else if (vex
.evex
&& !vex
.v
)
15932 if (bytemode
== vex_scalar_mode
)
15934 oappend (names_xmm
[reg
]);
15938 switch (vex
.length
)
15945 case vex_vsib_q_w_dq_mode
:
15946 case vex_vsib_q_w_d_mode
:
15962 names
= names_mask
;
15976 case vex_vsib_q_w_dq_mode
:
15977 case vex_vsib_q_w_d_mode
:
15978 names
= vex
.w
? names_ymm
: names_xmm
;
15987 names
= names_mask
;
15990 /* See PR binutils/20893 for a reproducer. */
16002 oappend (names
[reg
]);
16005 /* Get the VEX immediate byte without moving codep. */
16007 static unsigned char
16008 get_vex_imm8 (int sizeflag
, int opnum
)
16010 int bytes_before_imm
= 0;
16012 if (modrm
.mod
!= 3)
16014 /* There are SIB/displacement bytes. */
16015 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
16017 /* 32/64 bit address mode */
16018 int base
= modrm
.rm
;
16020 /* Check SIB byte. */
16023 FETCH_DATA (the_info
, codep
+ 1);
16025 /* When decoding the third source, don't increase
16026 bytes_before_imm as this has already been incremented
16027 by one in OP_E_memory while decoding the second
16030 bytes_before_imm
++;
16033 /* Don't increase bytes_before_imm when decoding the third source,
16034 it has already been incremented by OP_E_memory while decoding
16035 the second source operand. */
16041 /* When modrm.rm == 5 or modrm.rm == 4 and base in
16042 SIB == 5, there is a 4 byte displacement. */
16044 /* No displacement. */
16046 /* Fall through. */
16048 /* 4 byte displacement. */
16049 bytes_before_imm
+= 4;
16052 /* 1 byte displacement. */
16053 bytes_before_imm
++;
16060 /* 16 bit address mode */
16061 /* Don't increase bytes_before_imm when decoding the third source,
16062 it has already been incremented by OP_E_memory while decoding
16063 the second source operand. */
16069 /* When modrm.rm == 6, there is a 2 byte displacement. */
16071 /* No displacement. */
16073 /* Fall through. */
16075 /* 2 byte displacement. */
16076 bytes_before_imm
+= 2;
16079 /* 1 byte displacement: when decoding the third source,
16080 don't increase bytes_before_imm as this has already
16081 been incremented by one in OP_E_memory while decoding
16082 the second source operand. */
16084 bytes_before_imm
++;
16092 FETCH_DATA (the_info
, codep
+ bytes_before_imm
+ 1);
16093 return codep
[bytes_before_imm
];
16097 OP_EX_VexReg (int bytemode
, int sizeflag
, int reg
)
16099 const char **names
;
16101 if (reg
== -1 && modrm
.mod
!= 3)
16103 OP_E_memory (bytemode
, sizeflag
);
16115 if (address_mode
!= mode_64bit
)
16119 switch (vex
.length
)
16130 oappend (names
[reg
]);
16134 OP_EX_VexImmW (int bytemode
, int sizeflag
)
16137 static unsigned char vex_imm8
;
16139 if (vex_w_done
== 0)
16143 /* Skip mod/rm byte. */
16147 vex_imm8
= get_vex_imm8 (sizeflag
, 0);
16150 reg
= vex_imm8
>> 4;
16152 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
16154 else if (vex_w_done
== 1)
16159 reg
= vex_imm8
>> 4;
16161 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
16165 /* Output the imm8 directly. */
16166 scratchbuf
[0] = '$';
16167 print_operand_value (scratchbuf
+ 1, 1, vex_imm8
& 0xf);
16168 oappend_maybe_intel (scratchbuf
);
16169 scratchbuf
[0] = '\0';
16175 OP_Vex_2src (int bytemode
, int sizeflag
)
16177 if (modrm
.mod
== 3)
16179 int reg
= modrm
.rm
;
16183 oappend (names_xmm
[reg
]);
16188 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
16190 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
16191 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16193 OP_E (bytemode
, sizeflag
);
16198 OP_Vex_2src_1 (int bytemode
, int sizeflag
)
16200 if (modrm
.mod
== 3)
16202 /* Skip mod/rm byte. */
16209 unsigned int reg
= vex
.register_specifier
;
16210 vex
.register_specifier
= 0;
16212 if (address_mode
!= mode_64bit
)
16214 oappend (names_xmm
[reg
]);
16217 OP_Vex_2src (bytemode
, sizeflag
);
16221 OP_Vex_2src_2 (int bytemode
, int sizeflag
)
16224 OP_Vex_2src (bytemode
, sizeflag
);
16227 unsigned int reg
= vex
.register_specifier
;
16228 vex
.register_specifier
= 0;
16230 if (address_mode
!= mode_64bit
)
16232 oappend (names_xmm
[reg
]);
16237 OP_EX_VexW (int bytemode
, int sizeflag
)
16243 /* Skip mod/rm byte. */
16248 reg
= get_vex_imm8 (sizeflag
, 0) >> 4;
16253 reg
= get_vex_imm8 (sizeflag
, 1) >> 4;
16256 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
16264 OP_REG_VexI4 (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16267 const char **names
;
16269 FETCH_DATA (the_info
, codep
+ 1);
16272 if (bytemode
!= x_mode
)
16276 if (address_mode
!= mode_64bit
)
16279 switch (vex
.length
)
16290 oappend (names
[reg
]);
16294 OP_XMM_VexW (int bytemode
, int sizeflag
)
16296 /* Turn off the REX.W bit since it is used for swapping operands
16299 OP_XMM (bytemode
, sizeflag
);
16303 OP_EX_Vex (int bytemode
, int sizeflag
)
16305 if (modrm
.mod
!= 3)
16307 OP_EX (bytemode
, sizeflag
);
16311 OP_XMM_Vex (int bytemode
, int sizeflag
)
16313 if (modrm
.mod
!= 3)
16315 OP_XMM (bytemode
, sizeflag
);
16318 static struct op vex_cmp_op
[] =
16320 { STRING_COMMA_LEN ("eq") },
16321 { STRING_COMMA_LEN ("lt") },
16322 { STRING_COMMA_LEN ("le") },
16323 { STRING_COMMA_LEN ("unord") },
16324 { STRING_COMMA_LEN ("neq") },
16325 { STRING_COMMA_LEN ("nlt") },
16326 { STRING_COMMA_LEN ("nle") },
16327 { STRING_COMMA_LEN ("ord") },
16328 { STRING_COMMA_LEN ("eq_uq") },
16329 { STRING_COMMA_LEN ("nge") },
16330 { STRING_COMMA_LEN ("ngt") },
16331 { STRING_COMMA_LEN ("false") },
16332 { STRING_COMMA_LEN ("neq_oq") },
16333 { STRING_COMMA_LEN ("ge") },
16334 { STRING_COMMA_LEN ("gt") },
16335 { STRING_COMMA_LEN ("true") },
16336 { STRING_COMMA_LEN ("eq_os") },
16337 { STRING_COMMA_LEN ("lt_oq") },
16338 { STRING_COMMA_LEN ("le_oq") },
16339 { STRING_COMMA_LEN ("unord_s") },
16340 { STRING_COMMA_LEN ("neq_us") },
16341 { STRING_COMMA_LEN ("nlt_uq") },
16342 { STRING_COMMA_LEN ("nle_uq") },
16343 { STRING_COMMA_LEN ("ord_s") },
16344 { STRING_COMMA_LEN ("eq_us") },
16345 { STRING_COMMA_LEN ("nge_uq") },
16346 { STRING_COMMA_LEN ("ngt_uq") },
16347 { STRING_COMMA_LEN ("false_os") },
16348 { STRING_COMMA_LEN ("neq_os") },
16349 { STRING_COMMA_LEN ("ge_oq") },
16350 { STRING_COMMA_LEN ("gt_oq") },
16351 { STRING_COMMA_LEN ("true_us") },
16355 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16357 unsigned int cmp_type
;
16359 FETCH_DATA (the_info
, codep
+ 1);
16360 cmp_type
= *codep
++ & 0xff;
16361 if (cmp_type
< ARRAY_SIZE (vex_cmp_op
))
16364 char *p
= mnemonicendp
- 2;
16368 sprintf (p
, "%s%s", vex_cmp_op
[cmp_type
].name
, suffix
);
16369 mnemonicendp
+= vex_cmp_op
[cmp_type
].len
;
16373 /* We have a reserved extension byte. Output it directly. */
16374 scratchbuf
[0] = '$';
16375 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
16376 oappend_maybe_intel (scratchbuf
);
16377 scratchbuf
[0] = '\0';
16382 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
,
16383 int sizeflag ATTRIBUTE_UNUSED
)
16385 unsigned int cmp_type
;
16390 FETCH_DATA (the_info
, codep
+ 1);
16391 cmp_type
= *codep
++ & 0xff;
16392 /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
16393 If it's the case, print suffix, otherwise - print the immediate. */
16394 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
)
16399 char *p
= mnemonicendp
- 2;
16401 /* vpcmp* can have both one- and two-lettered suffix. */
16415 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
16416 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
16420 /* We have a reserved extension byte. Output it directly. */
16421 scratchbuf
[0] = '$';
16422 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
16423 oappend_maybe_intel (scratchbuf
);
16424 scratchbuf
[0] = '\0';
16428 static const struct op xop_cmp_op
[] =
16430 { STRING_COMMA_LEN ("lt") },
16431 { STRING_COMMA_LEN ("le") },
16432 { STRING_COMMA_LEN ("gt") },
16433 { STRING_COMMA_LEN ("ge") },
16434 { STRING_COMMA_LEN ("eq") },
16435 { STRING_COMMA_LEN ("neq") },
16436 { STRING_COMMA_LEN ("false") },
16437 { STRING_COMMA_LEN ("true") }
16441 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED
,
16442 int sizeflag ATTRIBUTE_UNUSED
)
16444 unsigned int cmp_type
;
16446 FETCH_DATA (the_info
, codep
+ 1);
16447 cmp_type
= *codep
++ & 0xff;
16448 if (cmp_type
< ARRAY_SIZE (xop_cmp_op
))
16451 char *p
= mnemonicendp
- 2;
16453 /* vpcom* can have both one- and two-lettered suffix. */
16467 sprintf (p
, "%s%s", xop_cmp_op
[cmp_type
].name
, suffix
);
16468 mnemonicendp
+= xop_cmp_op
[cmp_type
].len
;
16472 /* We have a reserved extension byte. Output it directly. */
16473 scratchbuf
[0] = '$';
16474 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
16475 oappend_maybe_intel (scratchbuf
);
16476 scratchbuf
[0] = '\0';
16480 static const struct op pclmul_op
[] =
16482 { STRING_COMMA_LEN ("lql") },
16483 { STRING_COMMA_LEN ("hql") },
16484 { STRING_COMMA_LEN ("lqh") },
16485 { STRING_COMMA_LEN ("hqh") }
16489 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED
,
16490 int sizeflag ATTRIBUTE_UNUSED
)
16492 unsigned int pclmul_type
;
16494 FETCH_DATA (the_info
, codep
+ 1);
16495 pclmul_type
= *codep
++ & 0xff;
16496 switch (pclmul_type
)
16507 if (pclmul_type
< ARRAY_SIZE (pclmul_op
))
16510 char *p
= mnemonicendp
- 3;
16515 sprintf (p
, "%s%s", pclmul_op
[pclmul_type
].name
, suffix
);
16516 mnemonicendp
+= pclmul_op
[pclmul_type
].len
;
16520 /* We have a reserved extension byte. Output it directly. */
16521 scratchbuf
[0] = '$';
16522 print_operand_value (scratchbuf
+ 1, 1, pclmul_type
);
16523 oappend_maybe_intel (scratchbuf
);
16524 scratchbuf
[0] = '\0';
16529 MOVBE_Fixup (int bytemode
, int sizeflag
)
16531 /* Add proper suffix to "movbe". */
16532 char *p
= mnemonicendp
;
16541 if (sizeflag
& SUFFIX_ALWAYS
)
16547 if (sizeflag
& DFLAG
)
16551 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16556 oappend (INTERNAL_DISASSEMBLER_ERROR
);
16563 OP_M (bytemode
, sizeflag
);
16567 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16570 const char **names
;
16572 /* Skip mod/rm byte. */
16586 oappend (names
[reg
]);
16590 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16592 const char **names
;
16593 unsigned int reg
= vex
.register_specifier
;
16594 vex
.register_specifier
= 0;
16601 if (address_mode
!= mode_64bit
)
16603 oappend (names
[reg
]);
16607 OP_Mask (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16610 || (bytemode
!= mask_mode
&& bytemode
!= mask_bd_mode
))
16614 if ((rex
& REX_R
) != 0 || !vex
.r
)
16620 oappend (names_mask
[modrm
.reg
]);
16624 OP_Rounding (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16627 || (bytemode
!= evex_rounding_mode
16628 && bytemode
!= evex_rounding_64_mode
16629 && bytemode
!= evex_sae_mode
))
16631 if (modrm
.mod
== 3 && vex
.b
)
16634 case evex_rounding_64_mode
:
16635 if (address_mode
!= mode_64bit
)
16640 /* Fall through. */
16641 case evex_rounding_mode
:
16642 oappend (names_rounding
[vex
.ll
]);
16644 case evex_sae_mode
: