opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2020 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "disassemble.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40
  41 #include <setjmp.h>
  42
  43 static int print_insn (bfd_vma, disassemble_info *);
  44 static void dofloat (int);
  45 static void OP_ST (int, int);
  46 static void OP_STi (int, int);
  47 static int putop (const char *, int);
  48 static void oappend (const char *);
  49 static void append_seg (void);
  50 static void OP_indirE (int, int);
  51 static void print_operand_value (char *, int, bfd_vma);
  52 static void OP_E_register (int, int);
  53 static void OP_E_memory (int, int);
  54 static void print_displacement (char *, bfd_vma);
  55 static void OP_E (int, int);
  56 static void OP_G (int, int);
  57 static bfd_vma get64 (void);
  58 static bfd_signed_vma get32 (void);
  59 static bfd_signed_vma get32s (void);
  60 static int get16 (void);
  61 static void set_op (bfd_vma, int);
  62 static void OP_Skip_MODRM (int, int);
  63 static void OP_REG (int, int);
  64 static void OP_IMREG (int, int);
  65 static void OP_I (int, int);
  66 static void OP_I64 (int, int);
  67 static void OP_sI (int, int);
  68 static void OP_J (int, int);
  69 static void OP_SEG (int, int);
  70 static void OP_DIR (int, int);
  71 static void OP_OFF (int, int);
  72 static void OP_OFF64 (int, int);
  73 static void ptr_reg (int, int);
  74 static void OP_ESreg (int, int);
  75 static void OP_DSreg (int, int);
  76 static void OP_C (int, int);
  77 static void OP_D (int, int);
  78 static void OP_T (int, int);
  79 static void OP_R (int, int);
  80 static void OP_MMX (int, int);
  81 static void OP_XMM (int, int);
  82 static void OP_EM (int, int);
  83 static void OP_EX (int, int);
  84 static void OP_EMC (int,int);
  85 static void OP_MXC (int,int);
  86 static void OP_MS (int, int);
  87 static void OP_XS (int, int);
  88 static void OP_M (int, int);
  89 static void OP_VEX (int, int);
  90 static void OP_EX_Vex (int, int);
  91 static void OP_EX_VexW (int, int);
  92 static void OP_EX_VexImmW (int, int);
  93 static void OP_XMM_Vex (int, int);
  94 static void OP_XMM_VexW (int, int);
  95 static void OP_Rounding (int, int);
  96 static void OP_REG_VexI4 (int, int);
  97 static void PCLMUL_Fixup (int, int);
  98 static void VCMP_Fixup (int, int);
  99 static void VPCMP_Fixup (int, int);
 100 static void VPCOM_Fixup (int, int);
 101 static void OP_0f07 (int, int);
 102 static void OP_Monitor (int, int);
 103 static void OP_Mwait (int, int);
 104 static void NOP_Fixup1 (int, int);
 105 static void NOP_Fixup2 (int, int);
 106 static void OP_3DNowSuffix (int, int);
 107 static void CMP_Fixup (int, int);
 108 static void BadOp (void);
 109 static void REP_Fixup (int, int);
 110 static void SEP_Fixup (int, int);
 111 static void BND_Fixup (int, int);
 112 static void NOTRACK_Fixup (int, int);
 113 static void HLE_Fixup1 (int, int);
 114 static void HLE_Fixup2 (int, int);
 115 static void HLE_Fixup3 (int, int);
 116 static void CMPXCHG8B_Fixup (int, int);
 117 static void XMM_Fixup (int, int);
 118 static void CRC32_Fixup (int, int);
 119 static void FXSAVE_Fixup (int, int);
 120 static void PCMPESTR_Fixup (int, int);
 121 static void OP_LWPCB_E (int, int);
 122 static void OP_LWP_E (int, int);
 123 static void OP_Vex_2src_1 (int, int);
 124 static void OP_Vex_2src_2 (int, int);
 125
 126 static void MOVBE_Fixup (int, int);
 127
 128 static void OP_Mask (int, int);
 129
 130 struct dis_private {
 131   /* Points to first byte not fetched.  */
 132   bfd_byte *max_fetched;
 133   bfd_byte the_buffer[MAX_MNEM_SIZE];
 134   bfd_vma insn_start;
 135   int orig_sizeflag;
 136   OPCODES_SIGJMP_BUF bailout;
 137 };
 138
 139 enum address_mode
 140 {
 141   mode_16bit,
 142   mode_32bit,
 143   mode_64bit
 144 };
 145
 146 enum address_mode address_mode;
 147
 148 /* Flags for the prefixes for the current instruction.  See below.  */
 149 static int prefixes;
 150
 151 /* REX prefix the current instruction.  See below.  */
 152 static int rex;
 153 /* Bits of REX we've already used.  */
 154 static int rex_used;
 155 /* REX bits in original REX prefix ignored.  */
 156 static int rex_ignored;
 157 /* Mark parts used in the REX prefix.  When we are testing for
 158    empty prefix (for 8bit register REX extension), just mask it
 159    out.  Otherwise test for REX bit is excuse for existence of REX
 160    only in case value is nonzero.  */
 161 #define USED_REX(value)                                 \
 162   {                                                     \
 163     if (value)                                          \
 164       {                                                 \
 165         if ((rex & value))                              \
 166           rex_used |= (value) | REX_OPCODE;             \
 167       }                                                 \
 168     else                                                \
 169       rex_used |= REX_OPCODE;                           \
 170   }
 171
 172 /* Flags for prefixes which we somehow handled when printing the
 173    current instruction.  */
 174 static int used_prefixes;
 175
 176 /* Flags stored in PREFIXES.  */
 177 #define PREFIX_REPZ 1
 178 #define PREFIX_REPNZ 2
 179 #define PREFIX_LOCK 4
 180 #define PREFIX_CS 8
 181 #define PREFIX_SS 0x10
 182 #define PREFIX_DS 0x20
 183 #define PREFIX_ES 0x40
 184 #define PREFIX_FS 0x80
 185 #define PREFIX_GS 0x100
 186 #define PREFIX_DATA 0x200
 187 #define PREFIX_ADDR 0x400
 188 #define PREFIX_FWAIT 0x800
 189
 190 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 191    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 192    on error.  */
 193 #define FETCH_DATA(info, addr) \
 194   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 195    ? 1 : fetch_data ((info), (addr)))
 196
 197 static int
 198 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 199 {
 200   int status;
 201   struct dis_private *priv = (struct dis_private *) info->private_data;
 202   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 203
 204   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 205     status = (*info->read_memory_func) (start,
 206                                         priv->max_fetched,
 207                                         addr - priv->max_fetched,
 208                                         info);
 209   else
 210     status = -1;
 211   if (status != 0)
 212     {
 213       /* If we did manage to read at least one byte, then
 214          print_insn_i386 will do something sensible.  Otherwise, print
 215          an error.  We do that here because this is where we know
 216          STATUS.  */
 217       if (priv->max_fetched == priv->the_buffer)
 218         (*info->memory_error_func) (status, start, info);
 219       OPCODES_SIGLONGJMP (priv->bailout, 1);
 220     }
 221   else
 222     priv->max_fetched = addr;
 223   return 1;
 224 }
 225
 226 /* Possible values for prefix requirement.  */
 227 #define PREFIX_IGNORED_SHIFT    16
 228 #define PREFIX_IGNORED_REPZ     (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
 229 #define PREFIX_IGNORED_REPNZ    (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
 230 #define PREFIX_IGNORED_DATA     (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
 231 #define PREFIX_IGNORED_ADDR     (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
 232 #define PREFIX_IGNORED_LOCK     (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
 233
 234 /* Opcode prefixes.  */
 235 #define PREFIX_OPCODE           (PREFIX_REPZ \
 236                                  | PREFIX_REPNZ \
 237                                  | PREFIX_DATA)
 238
 239 /* Prefixes ignored.  */
 240 #define PREFIX_IGNORED          (PREFIX_IGNORED_REPZ \
 241                                  | PREFIX_IGNORED_REPNZ \
 242                                  | PREFIX_IGNORED_DATA)
 243
 244 #define XX { NULL, 0 }
 245 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
 246
 247 #define Eb { OP_E, b_mode }
 248 #define Ebnd { OP_E, bnd_mode }
 249 #define EbS { OP_E, b_swap_mode }
 250 #define EbndS { OP_E, bnd_swap_mode }
 251 #define Ev { OP_E, v_mode }
 252 #define Eva { OP_E, va_mode }
 253 #define Ev_bnd { OP_E, v_bnd_mode }
 254 #define EvS { OP_E, v_swap_mode }
 255 #define Ed { OP_E, d_mode }
 256 #define Edq { OP_E, dq_mode }
 257 #define Edqw { OP_E, dqw_mode }
 258 #define Edqb { OP_E, dqb_mode }
 259 #define Edb { OP_E, db_mode }
 260 #define Edw { OP_E, dw_mode }
 261 #define Edqd { OP_E, dqd_mode }
 262 #define Eq { OP_E, q_mode }
 263 #define indirEv { OP_indirE, indir_v_mode }
 264 #define indirEp { OP_indirE, f_mode }
 265 #define stackEv { OP_E, stack_v_mode }
 266 #define Em { OP_E, m_mode }
 267 #define Ew { OP_E, w_mode }
 268 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 269 #define Ma { OP_M, a_mode }
 270 #define Mb { OP_M, b_mode }
 271 #define Md { OP_M, d_mode }
 272 #define Mo { OP_M, o_mode }
 273 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 274 #define Mq { OP_M, q_mode }
 275 #define Mv_bnd { OP_M, v_bndmk_mode }
 276 #define Mx { OP_M, x_mode }
 277 #define Mxmm { OP_M, xmm_mode }
 278 #define Gb { OP_G, b_mode }
 279 #define Gbnd { OP_G, bnd_mode }
 280 #define Gv { OP_G, v_mode }
 281 #define Gd { OP_G, d_mode }
 282 #define Gdq { OP_G, dq_mode }
 283 #define Gm { OP_G, m_mode }
 284 #define Gva { OP_G, va_mode }
 285 #define Gw { OP_G, w_mode }
 286 #define Rd { OP_R, d_mode }
 287 #define Rdq { OP_R, dq_mode }
 288 #define Rm { OP_R, m_mode }
 289 #define Ib { OP_I, b_mode }
 290 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 291 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 292 #define Iv { OP_I, v_mode }
 293 #define sIv { OP_sI, v_mode }
 294 #define Iv64 { OP_I64, v_mode }
 295 #define Id { OP_I, d_mode }
 296 #define Iw { OP_I, w_mode }
 297 #define I1 { OP_I, const_1_mode }
 298 #define Jb { OP_J, b_mode }
 299 #define Jv { OP_J, v_mode }
 300 #define Jdqw { OP_J, dqw_mode }
 301 #define Cm { OP_C, m_mode }
 302 #define Dm { OP_D, m_mode }
 303 #define Td { OP_T, d_mode }
 304 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 305
 306 #define RMeAX { OP_REG, eAX_reg }
 307 #define RMeBX { OP_REG, eBX_reg }
 308 #define RMeCX { OP_REG, eCX_reg }
 309 #define RMeDX { OP_REG, eDX_reg }
 310 #define RMeSP { OP_REG, eSP_reg }
 311 #define RMeBP { OP_REG, eBP_reg }
 312 #define RMeSI { OP_REG, eSI_reg }
 313 #define RMeDI { OP_REG, eDI_reg }
 314 #define RMrAX { OP_REG, rAX_reg }
 315 #define RMrBX { OP_REG, rBX_reg }
 316 #define RMrCX { OP_REG, rCX_reg }
 317 #define RMrDX { OP_REG, rDX_reg }
 318 #define RMrSP { OP_REG, rSP_reg }
 319 #define RMrBP { OP_REG, rBP_reg }
 320 #define RMrSI { OP_REG, rSI_reg }
 321 #define RMrDI { OP_REG, rDI_reg }
 322 #define RMAL { OP_REG, al_reg }
 323 #define RMCL { OP_REG, cl_reg }
 324 #define RMDL { OP_REG, dl_reg }
 325 #define RMBL { OP_REG, bl_reg }
 326 #define RMAH { OP_REG, ah_reg }
 327 #define RMCH { OP_REG, ch_reg }
 328 #define RMDH { OP_REG, dh_reg }
 329 #define RMBH { OP_REG, bh_reg }
 330 #define RMAX { OP_REG, ax_reg }
 331 #define RMDX { OP_REG, dx_reg }
 332
 333 #define eAX { OP_IMREG, eAX_reg }
 334 #define eBX { OP_IMREG, eBX_reg }
 335 #define eCX { OP_IMREG, eCX_reg }
 336 #define eDX { OP_IMREG, eDX_reg }
 337 #define eSP { OP_IMREG, eSP_reg }
 338 #define eBP { OP_IMREG, eBP_reg }
 339 #define eSI { OP_IMREG, eSI_reg }
 340 #define eDI { OP_IMREG, eDI_reg }
 341 #define AL { OP_IMREG, al_reg }
 342 #define CL { OP_IMREG, cl_reg }
 343 #define DL { OP_IMREG, dl_reg }
 344 #define BL { OP_IMREG, bl_reg }
 345 #define AH { OP_IMREG, ah_reg }
 346 #define CH { OP_IMREG, ch_reg }
 347 #define DH { OP_IMREG, dh_reg }
 348 #define BH { OP_IMREG, bh_reg }
 349 #define AX { OP_IMREG, ax_reg }
 350 #define DX { OP_IMREG, dx_reg }
 351 #define zAX { OP_IMREG, z_mode_ax_reg }
 352 #define indirDX { OP_IMREG, indir_dx_reg }
 353
 354 #define Sw { OP_SEG, w_mode }
 355 #define Sv { OP_SEG, v_mode }
 356 #define Ap { OP_DIR, 0 }
 357 #define Ob { OP_OFF64, b_mode }
 358 #define Ov { OP_OFF64, v_mode }
 359 #define Xb { OP_DSreg, eSI_reg }
 360 #define Xv { OP_DSreg, eSI_reg }
 361 #define Xz { OP_DSreg, eSI_reg }
 362 #define Yb { OP_ESreg, eDI_reg }
 363 #define Yv { OP_ESreg, eDI_reg }
 364 #define DSBX { OP_DSreg, eBX_reg }
 365
 366 #define es { OP_REG, es_reg }
 367 #define ss { OP_REG, ss_reg }
 368 #define cs { OP_REG, cs_reg }
 369 #define ds { OP_REG, ds_reg }
 370 #define fs { OP_REG, fs_reg }
 371 #define gs { OP_REG, gs_reg }
 372
 373 #define MX { OP_MMX, 0 }
 374 #define XM { OP_XMM, 0 }
 375 #define XMScalar { OP_XMM, scalar_mode }
 376 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 377 #define XMM { OP_XMM, xmm_mode }
 378 #define XMxmmq { OP_XMM, xmmq_mode }
 379 #define EM { OP_EM, v_mode }
 380 #define EMS { OP_EM, v_swap_mode }
 381 #define EMd { OP_EM, d_mode }
 382 #define EMx { OP_EM, x_mode }
 383 #define EXbScalar { OP_EX, b_scalar_mode }
 384 #define EXw { OP_EX, w_mode }
 385 #define EXwScalar { OP_EX, w_scalar_mode }
 386 #define EXd { OP_EX, d_mode }
 387 #define EXdScalar { OP_EX, d_scalar_mode }
 388 #define EXdS { OP_EX, d_swap_mode }
 389 #define EXq { OP_EX, q_mode }
 390 #define EXqScalar { OP_EX, q_scalar_mode }
 391 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
 392 #define EXqS { OP_EX, q_swap_mode }
 393 #define EXx { OP_EX, x_mode }
 394 #define EXxS { OP_EX, x_swap_mode }
 395 #define EXxmm { OP_EX, xmm_mode }
 396 #define EXymm { OP_EX, ymm_mode }
 397 #define EXxmmq { OP_EX, xmmq_mode }
 398 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 399 #define EXxmm_mb { OP_EX, xmm_mb_mode }
 400 #define EXxmm_mw { OP_EX, xmm_mw_mode }
 401 #define EXxmm_md { OP_EX, xmm_md_mode }
 402 #define EXxmm_mq { OP_EX, xmm_mq_mode }
 403 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
 404 #define EXxmmdw { OP_EX, xmmdw_mode }
 405 #define EXxmmqd { OP_EX, xmmqd_mode }
 406 #define EXymmq { OP_EX, ymmq_mode }
 407 #define EXVexWdq { OP_EX, vex_w_dq_mode }
 408 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 409 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 410 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 411 #define MS { OP_MS, v_mode }
 412 #define XS { OP_XS, v_mode }
 413 #define EMCq { OP_EMC, q_mode }
 414 #define MXC { OP_MXC, 0 }
 415 #define OPSUF { OP_3DNowSuffix, 0 }
 416 #define SEP { SEP_Fixup, 0 }
 417 #define CMP { CMP_Fixup, 0 }
 418 #define XMM0 { XMM_Fixup, 0 }
 419 #define FXSAVE { FXSAVE_Fixup, 0 }
 420 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
 421 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
 422
 423 #define Vex { OP_VEX, vex_mode }
 424 #define VexScalar { OP_VEX, vex_scalar_mode }
 425 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 426 #define Vex128 { OP_VEX, vex128_mode }
 427 #define Vex256 { OP_VEX, vex256_mode }
 428 #define VexGdq { OP_VEX, dq_mode }
 429 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
 430 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
 431 #define EXVexW { OP_EX_VexW, x_mode }
 432 #define EXdVexW { OP_EX_VexW, d_mode }
 433 #define EXqVexW { OP_EX_VexW, q_mode }
 434 #define EXVexImmW { OP_EX_VexImmW, x_mode }
 435 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
 436 #define XMVexW { OP_XMM_VexW, 0 }
 437 #define XMVexI4 { OP_REG_VexI4, x_mode }
 438 #define PCLMUL { PCLMUL_Fixup, 0 }
 439 #define VCMP { VCMP_Fixup, 0 }
 440 #define VPCMP { VPCMP_Fixup, 0 }
 441 #define VPCOM { VPCOM_Fixup, 0 }
 442
 443 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 444 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
 445 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 446
 447 #define XMask { OP_Mask, mask_mode }
 448 #define MaskG { OP_G, mask_mode }
 449 #define MaskE { OP_E, mask_mode }
 450 #define MaskBDE { OP_E, mask_bd_mode }
 451 #define MaskR { OP_R, mask_mode }
 452 #define MaskVex { OP_VEX, mask_mode }
 453
 454 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 455 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
 456 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 457 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
 458
 459 /* Used handle "rep" prefix for string instructions.  */
 460 #define Xbr { REP_Fixup, eSI_reg }
 461 #define Xvr { REP_Fixup, eSI_reg }
 462 #define Ybr { REP_Fixup, eDI_reg }
 463 #define Yvr { REP_Fixup, eDI_reg }
 464 #define Yzr { REP_Fixup, eDI_reg }
 465 #define indirDXr { REP_Fixup, indir_dx_reg }
 466 #define ALr { REP_Fixup, al_reg }
 467 #define eAXr { REP_Fixup, eAX_reg }
 468
 469 /* Used handle HLE prefix for lockable instructions.  */
 470 #define Ebh1 { HLE_Fixup1, b_mode }
 471 #define Evh1 { HLE_Fixup1, v_mode }
 472 #define Ebh2 { HLE_Fixup2, b_mode }
 473 #define Evh2 { HLE_Fixup2, v_mode }
 474 #define Ebh3 { HLE_Fixup3, b_mode }
 475 #define Evh3 { HLE_Fixup3, v_mode }
 476
 477 #define BND { BND_Fixup, 0 }
 478 #define NOTRACK { NOTRACK_Fixup, 0 }
 479
 480 #define cond_jump_flag { NULL, cond_jump_mode }
 481 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 482
 483 /* bits in sizeflag */
 484 #define SUFFIX_ALWAYS 4
 485 #define AFLAG 2
 486 #define DFLAG 1
 487
 488 enum
 489 {
 490   /* byte operand */
 491   b_mode = 1,
 492   /* byte operand with operand swapped */
 493   b_swap_mode,
 494   /* byte operand, sign extend like 'T' suffix */
 495   b_T_mode,
 496   /* operand size depends on prefixes */
 497   v_mode,
 498   /* operand size depends on prefixes with operand swapped */
 499   v_swap_mode,
 500   /* operand size depends on address prefix */
 501   va_mode,
 502   /* word operand */
 503   w_mode,
 504   /* double word operand  */
 505   d_mode,
 506   /* double word operand with operand swapped */
 507   d_swap_mode,
 508   /* quad word operand */
 509   q_mode,
 510   /* quad word operand with operand swapped */
 511   q_swap_mode,
 512   /* ten-byte operand */
 513   t_mode,
 514   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 515      broadcast enabled.  */
 516   x_mode,
 517   /* Similar to x_mode, but with different EVEX mem shifts.  */
 518   evex_x_gscat_mode,
 519   /* Similar to x_mode, but with disabled broadcast.  */
 520   evex_x_nobcst_mode,
 521   /* Similar to x_mode, but with operands swapped and disabled broadcast
 522      in EVEX.  */
 523   x_swap_mode,
 524   /* 16-byte XMM operand */
 525   xmm_mode,
 526   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 527      memory operand (depending on vector length).  Broadcast isn't
 528      allowed.  */
 529   xmmq_mode,
 530   /* Same as xmmq_mode, but broadcast is allowed.  */
 531   evex_half_bcst_xmmq_mode,
 532   /* XMM register or byte memory operand */
 533   xmm_mb_mode,
 534   /* XMM register or word memory operand */
 535   xmm_mw_mode,
 536   /* XMM register or double word memory operand */
 537   xmm_md_mode,
 538   /* XMM register or quad word memory operand */
 539   xmm_mq_mode,
 540   /* XMM register or double/quad word memory operand, depending on
 541      VEX.W.  */
 542   xmm_mdq_mode,
 543   /* 16-byte XMM, word, double word or quad word operand.  */
 544   xmmdw_mode,
 545   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 546   xmmqd_mode,
 547   /* 32-byte YMM operand */
 548   ymm_mode,
 549   /* quad word, ymmword or zmmword memory operand.  */
 550   ymmq_mode,
 551   /* 32-byte YMM or 16-byte word operand */
 552   ymmxmm_mode,
 553   /* d_mode in 32bit, q_mode in 64bit mode.  */
 554   m_mode,
 555   /* pair of v_mode operands */
 556   a_mode,
 557   cond_jump_mode,
 558   loop_jcxz_mode,
 559   v_bnd_mode,
 560   /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode.  */
 561   v_bndmk_mode,
 562   /* operand size depends on REX prefixes.  */
 563   dq_mode,
 564   /* registers like dq_mode, memory like w_mode, displacements like
 565      v_mode without considering Intel64 ISA.  */
 566   dqw_mode,
 567   /* bounds operand */
 568   bnd_mode,
 569   /* bounds operand with operand swapped */
 570   bnd_swap_mode,
 571   /* 4- or 6-byte pointer operand */
 572   f_mode,
 573   const_1_mode,
 574   /* v_mode for indirect branch opcodes.  */
 575   indir_v_mode,
 576   /* v_mode for stack-related opcodes.  */
 577   stack_v_mode,
 578   /* non-quad operand size depends on prefixes */
 579   z_mode,
 580   /* 16-byte operand */
 581   o_mode,
 582   /* registers like dq_mode, memory like b_mode.  */
 583   dqb_mode,
 584   /* registers like d_mode, memory like b_mode.  */
 585   db_mode,
 586   /* registers like d_mode, memory like w_mode.  */
 587   dw_mode,
 588   /* registers like dq_mode, memory like d_mode.  */
 589   dqd_mode,
 590   /* normal vex mode */
 591   vex_mode,
 592   /* 128bit vex mode */
 593   vex128_mode,
 594   /* 256bit vex mode */
 595   vex256_mode,
 596   /* operand size depends on the VEX.W bit.  */
 597   vex_w_dq_mode,
 598
 599   /* Similar to vex_w_dq_mode, with VSIB dword indices.  */
 600   vex_vsib_d_w_dq_mode,
 601   /* Similar to vex_vsib_d_w_dq_mode, with smaller memory.  */
 602   vex_vsib_d_w_d_mode,
 603   /* Similar to vex_w_dq_mode, with VSIB qword indices.  */
 604   vex_vsib_q_w_dq_mode,
 605   /* Similar to vex_vsib_q_w_dq_mode, with smaller memory.  */
 606   vex_vsib_q_w_d_mode,
 607
 608   /* scalar, ignore vector length.  */
 609   scalar_mode,
 610   /* like b_mode, ignore vector length.  */
 611   b_scalar_mode,
 612   /* like w_mode, ignore vector length.  */
 613   w_scalar_mode,
 614   /* like d_mode, ignore vector length.  */
 615   d_scalar_mode,
 616   /* like d_swap_mode, ignore vector length.  */
 617   d_scalar_swap_mode,
 618   /* like q_mode, ignore vector length.  */
 619   q_scalar_mode,
 620   /* like q_swap_mode, ignore vector length.  */
 621   q_scalar_swap_mode,
 622   /* like vex_mode, ignore vector length.  */
 623   vex_scalar_mode,
 624   /* like vex_w_dq_mode, ignore vector length.  */
 625   vex_scalar_w_dq_mode,
 626
 627   /* Static rounding.  */
 628   evex_rounding_mode,
 629   /* Static rounding, 64-bit mode only.  */
 630   evex_rounding_64_mode,
 631   /* Supress all exceptions.  */
 632   evex_sae_mode,
 633
 634   /* Mask register operand.  */
 635   mask_mode,
 636   /* Mask register operand.  */
 637   mask_bd_mode,
 638
 639   es_reg,
 640   cs_reg,
 641   ss_reg,
 642   ds_reg,
 643   fs_reg,
 644   gs_reg,
 645
 646   eAX_reg,
 647   eCX_reg,
 648   eDX_reg,
 649   eBX_reg,
 650   eSP_reg,
 651   eBP_reg,
 652   eSI_reg,
 653   eDI_reg,
 654
 655   al_reg,
 656   cl_reg,
 657   dl_reg,
 658   bl_reg,
 659   ah_reg,
 660   ch_reg,
 661   dh_reg,
 662   bh_reg,
 663
 664   ax_reg,
 665   cx_reg,
 666   dx_reg,
 667   bx_reg,
 668   sp_reg,
 669   bp_reg,
 670   si_reg,
 671   di_reg,
 672
 673   rAX_reg,
 674   rCX_reg,
 675   rDX_reg,
 676   rBX_reg,
 677   rSP_reg,
 678   rBP_reg,
 679   rSI_reg,
 680   rDI_reg,
 681
 682   z_mode_ax_reg,
 683   indir_dx_reg
 684 };
 685
 686 enum
 687 {
 688   FLOATCODE = 1,
 689   USE_REG_TABLE,
 690   USE_MOD_TABLE,
 691   USE_RM_TABLE,
 692   USE_PREFIX_TABLE,
 693   USE_X86_64_TABLE,
 694   USE_3BYTE_TABLE,
 695   USE_XOP_8F_TABLE,
 696   USE_VEX_C4_TABLE,
 697   USE_VEX_C5_TABLE,
 698   USE_VEX_LEN_TABLE,
 699   USE_VEX_W_TABLE,
 700   USE_EVEX_TABLE,
 701   USE_EVEX_LEN_TABLE
 702 };
 703
 704 #define FLOAT                   NULL, { { NULL, FLOATCODE } }, 0
 705
 706 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }, 0
 707 #define DIS386_PREFIX(T, I, P)          NULL, { { NULL, (T)}, { NULL,  (I) } }, P
 708 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 709 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 710 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 711 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 712 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 713 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 714 #define THREE_BYTE_TABLE_PREFIX(I, P)   DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
 715 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 716 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 717 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 718 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 719 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 720 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 721 #define EVEX_LEN_TABLE(I)       DIS386 (USE_EVEX_LEN_TABLE, (I))
 722
 723 enum
 724 {
 725   REG_80 = 0,
 726   REG_81,
 727   REG_83,
 728   REG_8F,
 729   REG_C0,
 730   REG_C1,
 731   REG_C6,
 732   REG_C7,
 733   REG_D0,
 734   REG_D1,
 735   REG_D2,
 736   REG_D3,
 737   REG_F6,
 738   REG_F7,
 739   REG_FE,
 740   REG_FF,
 741   REG_0F00,
 742   REG_0F01,
 743   REG_0F0D,
 744   REG_0F18,
 745   REG_0F1C_P_0_MOD_0,
 746   REG_0F1E_P_1_MOD_3,
 747   REG_0F71,
 748   REG_0F72,
 749   REG_0F73,
 750   REG_0FA6,
 751   REG_0FA7,
 752   REG_0FAE,
 753   REG_0FBA,
 754   REG_0FC7,
 755   REG_VEX_0F71,
 756   REG_VEX_0F72,
 757   REG_VEX_0F73,
 758   REG_VEX_0FAE,
 759   REG_VEX_0F38F3,
 760   REG_XOP_LWPCB,
 761   REG_XOP_LWP,
 762   REG_XOP_TBM_01,
 763   REG_XOP_TBM_02,
 764
 765   REG_EVEX_0F71,
 766   REG_EVEX_0F72,
 767   REG_EVEX_0F73,
 768   REG_EVEX_0F38C6,
 769   REG_EVEX_0F38C7
 770 };
 771
 772 enum
 773 {
 774   MOD_8D = 0,
 775   MOD_C6_REG_7,
 776   MOD_C7_REG_7,
 777   MOD_FF_REG_3,
 778   MOD_FF_REG_5,
 779   MOD_0F01_REG_0,
 780   MOD_0F01_REG_1,
 781   MOD_0F01_REG_2,
 782   MOD_0F01_REG_3,
 783   MOD_0F01_REG_5,
 784   MOD_0F01_REG_7,
 785   MOD_0F12_PREFIX_0,
 786   MOD_0F13,
 787   MOD_0F16_PREFIX_0,
 788   MOD_0F17,
 789   MOD_0F18_REG_0,
 790   MOD_0F18_REG_1,
 791   MOD_0F18_REG_2,
 792   MOD_0F18_REG_3,
 793   MOD_0F18_REG_4,
 794   MOD_0F18_REG_5,
 795   MOD_0F18_REG_6,
 796   MOD_0F18_REG_7,
 797   MOD_0F1A_PREFIX_0,
 798   MOD_0F1B_PREFIX_0,
 799   MOD_0F1B_PREFIX_1,
 800   MOD_0F1C_PREFIX_0,
 801   MOD_0F1E_PREFIX_1,
 802   MOD_0F24,
 803   MOD_0F26,
 804   MOD_0F2B_PREFIX_0,
 805   MOD_0F2B_PREFIX_1,
 806   MOD_0F2B_PREFIX_2,
 807   MOD_0F2B_PREFIX_3,
 808   MOD_0F51,
 809   MOD_0F71_REG_2,
 810   MOD_0F71_REG_4,
 811   MOD_0F71_REG_6,
 812   MOD_0F72_REG_2,
 813   MOD_0F72_REG_4,
 814   MOD_0F72_REG_6,
 815   MOD_0F73_REG_2,
 816   MOD_0F73_REG_3,
 817   MOD_0F73_REG_6,
 818   MOD_0F73_REG_7,
 819   MOD_0FAE_REG_0,
 820   MOD_0FAE_REG_1,
 821   MOD_0FAE_REG_2,
 822   MOD_0FAE_REG_3,
 823   MOD_0FAE_REG_4,
 824   MOD_0FAE_REG_5,
 825   MOD_0FAE_REG_6,
 826   MOD_0FAE_REG_7,
 827   MOD_0FB2,
 828   MOD_0FB4,
 829   MOD_0FB5,
 830   MOD_0FC3,
 831   MOD_0FC7_REG_3,
 832   MOD_0FC7_REG_4,
 833   MOD_0FC7_REG_5,
 834   MOD_0FC7_REG_6,
 835   MOD_0FC7_REG_7,
 836   MOD_0FD7,
 837   MOD_0FE7_PREFIX_2,
 838   MOD_0FF0_PREFIX_3,
 839   MOD_0F382A_PREFIX_2,
 840   MOD_0F38F5_PREFIX_2,
 841   MOD_0F38F6_PREFIX_0,
 842   MOD_0F38F8_PREFIX_1,
 843   MOD_0F38F8_PREFIX_2,
 844   MOD_0F38F8_PREFIX_3,
 845   MOD_0F38F9_PREFIX_0,
 846   MOD_62_32BIT,
 847   MOD_C4_32BIT,
 848   MOD_C5_32BIT,
 849   MOD_VEX_0F12_PREFIX_0,
 850   MOD_VEX_0F13,
 851   MOD_VEX_0F16_PREFIX_0,
 852   MOD_VEX_0F17,
 853   MOD_VEX_0F2B,
 854   MOD_VEX_W_0_0F41_P_0_LEN_1,
 855   MOD_VEX_W_1_0F41_P_0_LEN_1,
 856   MOD_VEX_W_0_0F41_P_2_LEN_1,
 857   MOD_VEX_W_1_0F41_P_2_LEN_1,
 858   MOD_VEX_W_0_0F42_P_0_LEN_1,
 859   MOD_VEX_W_1_0F42_P_0_LEN_1,
 860   MOD_VEX_W_0_0F42_P_2_LEN_1,
 861   MOD_VEX_W_1_0F42_P_2_LEN_1,
 862   MOD_VEX_W_0_0F44_P_0_LEN_1,
 863   MOD_VEX_W_1_0F44_P_0_LEN_1,
 864   MOD_VEX_W_0_0F44_P_2_LEN_1,
 865   MOD_VEX_W_1_0F44_P_2_LEN_1,
 866   MOD_VEX_W_0_0F45_P_0_LEN_1,
 867   MOD_VEX_W_1_0F45_P_0_LEN_1,
 868   MOD_VEX_W_0_0F45_P_2_LEN_1,
 869   MOD_VEX_W_1_0F45_P_2_LEN_1,
 870   MOD_VEX_W_0_0F46_P_0_LEN_1,
 871   MOD_VEX_W_1_0F46_P_0_LEN_1,
 872   MOD_VEX_W_0_0F46_P_2_LEN_1,
 873   MOD_VEX_W_1_0F46_P_2_LEN_1,
 874   MOD_VEX_W_0_0F47_P_0_LEN_1,
 875   MOD_VEX_W_1_0F47_P_0_LEN_1,
 876   MOD_VEX_W_0_0F47_P_2_LEN_1,
 877   MOD_VEX_W_1_0F47_P_2_LEN_1,
 878   MOD_VEX_W_0_0F4A_P_0_LEN_1,
 879   MOD_VEX_W_1_0F4A_P_0_LEN_1,
 880   MOD_VEX_W_0_0F4A_P_2_LEN_1,
 881   MOD_VEX_W_1_0F4A_P_2_LEN_1,
 882   MOD_VEX_W_0_0F4B_P_0_LEN_1,
 883   MOD_VEX_W_1_0F4B_P_0_LEN_1,
 884   MOD_VEX_W_0_0F4B_P_2_LEN_1,
 885   MOD_VEX_0F50,
 886   MOD_VEX_0F71_REG_2,
 887   MOD_VEX_0F71_REG_4,
 888   MOD_VEX_0F71_REG_6,
 889   MOD_VEX_0F72_REG_2,
 890   MOD_VEX_0F72_REG_4,
 891   MOD_VEX_0F72_REG_6,
 892   MOD_VEX_0F73_REG_2,
 893   MOD_VEX_0F73_REG_3,
 894   MOD_VEX_0F73_REG_6,
 895   MOD_VEX_0F73_REG_7,
 896   MOD_VEX_W_0_0F91_P_0_LEN_0,
 897   MOD_VEX_W_1_0F91_P_0_LEN_0,
 898   MOD_VEX_W_0_0F91_P_2_LEN_0,
 899   MOD_VEX_W_1_0F91_P_2_LEN_0,
 900   MOD_VEX_W_0_0F92_P_0_LEN_0,
 901   MOD_VEX_W_0_0F92_P_2_LEN_0,
 902   MOD_VEX_0F92_P_3_LEN_0,
 903   MOD_VEX_W_0_0F93_P_0_LEN_0,
 904   MOD_VEX_W_0_0F93_P_2_LEN_0,
 905   MOD_VEX_0F93_P_3_LEN_0,
 906   MOD_VEX_W_0_0F98_P_0_LEN_0,
 907   MOD_VEX_W_1_0F98_P_0_LEN_0,
 908   MOD_VEX_W_0_0F98_P_2_LEN_0,
 909   MOD_VEX_W_1_0F98_P_2_LEN_0,
 910   MOD_VEX_W_0_0F99_P_0_LEN_0,
 911   MOD_VEX_W_1_0F99_P_0_LEN_0,
 912   MOD_VEX_W_0_0F99_P_2_LEN_0,
 913   MOD_VEX_W_1_0F99_P_2_LEN_0,
 914   MOD_VEX_0FAE_REG_2,
 915   MOD_VEX_0FAE_REG_3,
 916   MOD_VEX_0FD7_PREFIX_2,
 917   MOD_VEX_0FE7_PREFIX_2,
 918   MOD_VEX_0FF0_PREFIX_3,
 919   MOD_VEX_0F381A_PREFIX_2,
 920   MOD_VEX_0F382A_PREFIX_2,
 921   MOD_VEX_0F382C_PREFIX_2,
 922   MOD_VEX_0F382D_PREFIX_2,
 923   MOD_VEX_0F382E_PREFIX_2,
 924   MOD_VEX_0F382F_PREFIX_2,
 925   MOD_VEX_0F385A_PREFIX_2,
 926   MOD_VEX_0F388C_PREFIX_2,
 927   MOD_VEX_0F388E_PREFIX_2,
 928   MOD_VEX_W_0_0F3A30_P_2_LEN_0,
 929   MOD_VEX_W_1_0F3A30_P_2_LEN_0,
 930   MOD_VEX_W_0_0F3A31_P_2_LEN_0,
 931   MOD_VEX_W_1_0F3A31_P_2_LEN_0,
 932   MOD_VEX_W_0_0F3A32_P_2_LEN_0,
 933   MOD_VEX_W_1_0F3A32_P_2_LEN_0,
 934   MOD_VEX_W_0_0F3A33_P_2_LEN_0,
 935   MOD_VEX_W_1_0F3A33_P_2_LEN_0,
 936
 937   MOD_EVEX_0F12_PREFIX_0,
 938   MOD_EVEX_0F16_PREFIX_0,
 939   MOD_EVEX_0F38C6_REG_1,
 940   MOD_EVEX_0F38C6_REG_2,
 941   MOD_EVEX_0F38C6_REG_5,
 942   MOD_EVEX_0F38C6_REG_6,
 943   MOD_EVEX_0F38C7_REG_1,
 944   MOD_EVEX_0F38C7_REG_2,
 945   MOD_EVEX_0F38C7_REG_5,
 946   MOD_EVEX_0F38C7_REG_6
 947 };
 948
 949 enum
 950 {
 951   RM_C6_REG_7 = 0,
 952   RM_C7_REG_7,
 953   RM_0F01_REG_0,
 954   RM_0F01_REG_1,
 955   RM_0F01_REG_2,
 956   RM_0F01_REG_3,
 957   RM_0F01_REG_5_MOD_3,
 958   RM_0F01_REG_7_MOD_3,
 959   RM_0F1E_P_1_MOD_3_REG_7,
 960   RM_0FAE_REG_6_MOD_3_P_0,
 961   RM_0FAE_REG_7_MOD_3,
 962 };
 963
 964 enum
 965 {
 966   PREFIX_90 = 0,
 967   PREFIX_0F01_REG_5_MOD_0,
 968   PREFIX_0F01_REG_5_MOD_3_RM_0,
 969   PREFIX_0F01_REG_5_MOD_3_RM_2,
 970   PREFIX_0F01_REG_7_MOD_3_RM_2,
 971   PREFIX_0F01_REG_7_MOD_3_RM_3,
 972   PREFIX_0F09,
 973   PREFIX_0F10,
 974   PREFIX_0F11,
 975   PREFIX_0F12,
 976   PREFIX_0F16,
 977   PREFIX_0F1A,
 978   PREFIX_0F1B,
 979   PREFIX_0F1C,
 980   PREFIX_0F1E,
 981   PREFIX_0F2A,
 982   PREFIX_0F2B,
 983   PREFIX_0F2C,
 984   PREFIX_0F2D,
 985   PREFIX_0F2E,
 986   PREFIX_0F2F,
 987   PREFIX_0F51,
 988   PREFIX_0F52,
 989   PREFIX_0F53,
 990   PREFIX_0F58,
 991   PREFIX_0F59,
 992   PREFIX_0F5A,
 993   PREFIX_0F5B,
 994   PREFIX_0F5C,
 995   PREFIX_0F5D,
 996   PREFIX_0F5E,
 997   PREFIX_0F5F,
 998   PREFIX_0F60,
 999   PREFIX_0F61,
1000   PREFIX_0F62,
1001   PREFIX_0F6C,
1002   PREFIX_0F6D,
1003   PREFIX_0F6F,
1004   PREFIX_0F70,
1005   PREFIX_0F73_REG_3,
1006   PREFIX_0F73_REG_7,
1007   PREFIX_0F78,
1008   PREFIX_0F79,
1009   PREFIX_0F7C,
1010   PREFIX_0F7D,
1011   PREFIX_0F7E,
1012   PREFIX_0F7F,
1013   PREFIX_0FAE_REG_0_MOD_3,
1014   PREFIX_0FAE_REG_1_MOD_3,
1015   PREFIX_0FAE_REG_2_MOD_3,
1016   PREFIX_0FAE_REG_3_MOD_3,
1017   PREFIX_0FAE_REG_4_MOD_0,
1018   PREFIX_0FAE_REG_4_MOD_3,
1019   PREFIX_0FAE_REG_5_MOD_0,
1020   PREFIX_0FAE_REG_5_MOD_3,
1021   PREFIX_0FAE_REG_6_MOD_0,
1022   PREFIX_0FAE_REG_6_MOD_3,
1023   PREFIX_0FAE_REG_7_MOD_0,
1024   PREFIX_0FB8,
1025   PREFIX_0FBC,
1026   PREFIX_0FBD,
1027   PREFIX_0FC2,
1028   PREFIX_0FC3_MOD_0,
1029   PREFIX_0FC7_REG_6_MOD_0,
1030   PREFIX_0FC7_REG_6_MOD_3,
1031   PREFIX_0FC7_REG_7_MOD_3,
1032   PREFIX_0FD0,
1033   PREFIX_0FD6,
1034   PREFIX_0FE6,
1035   PREFIX_0FE7,
1036   PREFIX_0FF0,
1037   PREFIX_0FF7,
1038   PREFIX_0F3810,
1039   PREFIX_0F3814,
1040   PREFIX_0F3815,
1041   PREFIX_0F3817,
1042   PREFIX_0F3820,
1043   PREFIX_0F3821,
1044   PREFIX_0F3822,
1045   PREFIX_0F3823,
1046   PREFIX_0F3824,
1047   PREFIX_0F3825,
1048   PREFIX_0F3828,
1049   PREFIX_0F3829,
1050   PREFIX_0F382A,
1051   PREFIX_0F382B,
1052   PREFIX_0F3830,
1053   PREFIX_0F3831,
1054   PREFIX_0F3832,
1055   PREFIX_0F3833,
1056   PREFIX_0F3834,
1057   PREFIX_0F3835,
1058   PREFIX_0F3837,
1059   PREFIX_0F3838,
1060   PREFIX_0F3839,
1061   PREFIX_0F383A,
1062   PREFIX_0F383B,
1063   PREFIX_0F383C,
1064   PREFIX_0F383D,
1065   PREFIX_0F383E,
1066   PREFIX_0F383F,
1067   PREFIX_0F3840,
1068   PREFIX_0F3841,
1069   PREFIX_0F3880,
1070   PREFIX_0F3881,
1071   PREFIX_0F3882,
1072   PREFIX_0F38C8,
1073   PREFIX_0F38C9,
1074   PREFIX_0F38CA,
1075   PREFIX_0F38CB,
1076   PREFIX_0F38CC,
1077   PREFIX_0F38CD,
1078   PREFIX_0F38CF,
1079   PREFIX_0F38DB,
1080   PREFIX_0F38DC,
1081   PREFIX_0F38DD,
1082   PREFIX_0F38DE,
1083   PREFIX_0F38DF,
1084   PREFIX_0F38F0,
1085   PREFIX_0F38F1,
1086   PREFIX_0F38F5,
1087   PREFIX_0F38F6,
1088   PREFIX_0F38F8,
1089   PREFIX_0F38F9,
1090   PREFIX_0F3A08,
1091   PREFIX_0F3A09,
1092   PREFIX_0F3A0A,
1093   PREFIX_0F3A0B,
1094   PREFIX_0F3A0C,
1095   PREFIX_0F3A0D,
1096   PREFIX_0F3A0E,
1097   PREFIX_0F3A14,
1098   PREFIX_0F3A15,
1099   PREFIX_0F3A16,
1100   PREFIX_0F3A17,
1101   PREFIX_0F3A20,
1102   PREFIX_0F3A21,
1103   PREFIX_0F3A22,
1104   PREFIX_0F3A40,
1105   PREFIX_0F3A41,
1106   PREFIX_0F3A42,
1107   PREFIX_0F3A44,
1108   PREFIX_0F3A60,
1109   PREFIX_0F3A61,
1110   PREFIX_0F3A62,
1111   PREFIX_0F3A63,
1112   PREFIX_0F3ACC,
1113   PREFIX_0F3ACE,
1114   PREFIX_0F3ACF,
1115   PREFIX_0F3ADF,
1116   PREFIX_VEX_0F10,
1117   PREFIX_VEX_0F11,
1118   PREFIX_VEX_0F12,
1119   PREFIX_VEX_0F16,
1120   PREFIX_VEX_0F2A,
1121   PREFIX_VEX_0F2C,
1122   PREFIX_VEX_0F2D,
1123   PREFIX_VEX_0F2E,
1124   PREFIX_VEX_0F2F,
1125   PREFIX_VEX_0F41,
1126   PREFIX_VEX_0F42,
1127   PREFIX_VEX_0F44,
1128   PREFIX_VEX_0F45,
1129   PREFIX_VEX_0F46,
1130   PREFIX_VEX_0F47,
1131   PREFIX_VEX_0F4A,
1132   PREFIX_VEX_0F4B,
1133   PREFIX_VEX_0F51,
1134   PREFIX_VEX_0F52,
1135   PREFIX_VEX_0F53,
1136   PREFIX_VEX_0F58,
1137   PREFIX_VEX_0F59,
1138   PREFIX_VEX_0F5A,
1139   PREFIX_VEX_0F5B,
1140   PREFIX_VEX_0F5C,
1141   PREFIX_VEX_0F5D,
1142   PREFIX_VEX_0F5E,
1143   PREFIX_VEX_0F5F,
1144   PREFIX_VEX_0F60,
1145   PREFIX_VEX_0F61,
1146   PREFIX_VEX_0F62,
1147   PREFIX_VEX_0F63,
1148   PREFIX_VEX_0F64,
1149   PREFIX_VEX_0F65,
1150   PREFIX_VEX_0F66,
1151   PREFIX_VEX_0F67,
1152   PREFIX_VEX_0F68,
1153   PREFIX_VEX_0F69,
1154   PREFIX_VEX_0F6A,
1155   PREFIX_VEX_0F6B,
1156   PREFIX_VEX_0F6C,
1157   PREFIX_VEX_0F6D,
1158   PREFIX_VEX_0F6E,
1159   PREFIX_VEX_0F6F,
1160   PREFIX_VEX_0F70,
1161   PREFIX_VEX_0F71_REG_2,
1162   PREFIX_VEX_0F71_REG_4,
1163   PREFIX_VEX_0F71_REG_6,
1164   PREFIX_VEX_0F72_REG_2,
1165   PREFIX_VEX_0F72_REG_4,
1166   PREFIX_VEX_0F72_REG_6,
1167   PREFIX_VEX_0F73_REG_2,
1168   PREFIX_VEX_0F73_REG_3,
1169   PREFIX_VEX_0F73_REG_6,
1170   PREFIX_VEX_0F73_REG_7,
1171   PREFIX_VEX_0F74,
1172   PREFIX_VEX_0F75,
1173   PREFIX_VEX_0F76,
1174   PREFIX_VEX_0F77,
1175   PREFIX_VEX_0F7C,
1176   PREFIX_VEX_0F7D,
1177   PREFIX_VEX_0F7E,
1178   PREFIX_VEX_0F7F,
1179   PREFIX_VEX_0F90,
1180   PREFIX_VEX_0F91,
1181   PREFIX_VEX_0F92,
1182   PREFIX_VEX_0F93,
1183   PREFIX_VEX_0F98,
1184   PREFIX_VEX_0F99,
1185   PREFIX_VEX_0FC2,
1186   PREFIX_VEX_0FC4,
1187   PREFIX_VEX_0FC5,
1188   PREFIX_VEX_0FD0,
1189   PREFIX_VEX_0FD1,
1190   PREFIX_VEX_0FD2,
1191   PREFIX_VEX_0FD3,
1192   PREFIX_VEX_0FD4,
1193   PREFIX_VEX_0FD5,
1194   PREFIX_VEX_0FD6,
1195   PREFIX_VEX_0FD7,
1196   PREFIX_VEX_0FD8,
1197   PREFIX_VEX_0FD9,
1198   PREFIX_VEX_0FDA,
1199   PREFIX_VEX_0FDB,
1200   PREFIX_VEX_0FDC,
1201   PREFIX_VEX_0FDD,
1202   PREFIX_VEX_0FDE,
1203   PREFIX_VEX_0FDF,
1204   PREFIX_VEX_0FE0,
1205   PREFIX_VEX_0FE1,
1206   PREFIX_VEX_0FE2,
1207   PREFIX_VEX_0FE3,
1208   PREFIX_VEX_0FE4,
1209   PREFIX_VEX_0FE5,
1210   PREFIX_VEX_0FE6,
1211   PREFIX_VEX_0FE7,
1212   PREFIX_VEX_0FE8,
1213   PREFIX_VEX_0FE9,
1214   PREFIX_VEX_0FEA,
1215   PREFIX_VEX_0FEB,
1216   PREFIX_VEX_0FEC,
1217   PREFIX_VEX_0FED,
1218   PREFIX_VEX_0FEE,
1219   PREFIX_VEX_0FEF,
1220   PREFIX_VEX_0FF0,
1221   PREFIX_VEX_0FF1,
1222   PREFIX_VEX_0FF2,
1223   PREFIX_VEX_0FF3,
1224   PREFIX_VEX_0FF4,
1225   PREFIX_VEX_0FF5,
1226   PREFIX_VEX_0FF6,
1227   PREFIX_VEX_0FF7,
1228   PREFIX_VEX_0FF8,
1229   PREFIX_VEX_0FF9,
1230   PREFIX_VEX_0FFA,
1231   PREFIX_VEX_0FFB,
1232   PREFIX_VEX_0FFC,
1233   PREFIX_VEX_0FFD,
1234   PREFIX_VEX_0FFE,
1235   PREFIX_VEX_0F3800,
1236   PREFIX_VEX_0F3801,
1237   PREFIX_VEX_0F3802,
1238   PREFIX_VEX_0F3803,
1239   PREFIX_VEX_0F3804,
1240   PREFIX_VEX_0F3805,
1241   PREFIX_VEX_0F3806,
1242   PREFIX_VEX_0F3807,
1243   PREFIX_VEX_0F3808,
1244   PREFIX_VEX_0F3809,
1245   PREFIX_VEX_0F380A,
1246   PREFIX_VEX_0F380B,
1247   PREFIX_VEX_0F380C,
1248   PREFIX_VEX_0F380D,
1249   PREFIX_VEX_0F380E,
1250   PREFIX_VEX_0F380F,
1251   PREFIX_VEX_0F3813,
1252   PREFIX_VEX_0F3816,
1253   PREFIX_VEX_0F3817,
1254   PREFIX_VEX_0F3818,
1255   PREFIX_VEX_0F3819,
1256   PREFIX_VEX_0F381A,
1257   PREFIX_VEX_0F381C,
1258   PREFIX_VEX_0F381D,
1259   PREFIX_VEX_0F381E,
1260   PREFIX_VEX_0F3820,
1261   PREFIX_VEX_0F3821,
1262   PREFIX_VEX_0F3822,
1263   PREFIX_VEX_0F3823,
1264   PREFIX_VEX_0F3824,
1265   PREFIX_VEX_0F3825,
1266   PREFIX_VEX_0F3828,
1267   PREFIX_VEX_0F3829,
1268   PREFIX_VEX_0F382A,
1269   PREFIX_VEX_0F382B,
1270   PREFIX_VEX_0F382C,
1271   PREFIX_VEX_0F382D,
1272   PREFIX_VEX_0F382E,
1273   PREFIX_VEX_0F382F,
1274   PREFIX_VEX_0F3830,
1275   PREFIX_VEX_0F3831,
1276   PREFIX_VEX_0F3832,
1277   PREFIX_VEX_0F3833,
1278   PREFIX_VEX_0F3834,
1279   PREFIX_VEX_0F3835,
1280   PREFIX_VEX_0F3836,
1281   PREFIX_VEX_0F3837,
1282   PREFIX_VEX_0F3838,
1283   PREFIX_VEX_0F3839,
1284   PREFIX_VEX_0F383A,
1285   PREFIX_VEX_0F383B,
1286   PREFIX_VEX_0F383C,
1287   PREFIX_VEX_0F383D,
1288   PREFIX_VEX_0F383E,
1289   PREFIX_VEX_0F383F,
1290   PREFIX_VEX_0F3840,
1291   PREFIX_VEX_0F3841,
1292   PREFIX_VEX_0F3845,
1293   PREFIX_VEX_0F3846,
1294   PREFIX_VEX_0F3847,
1295   PREFIX_VEX_0F3858,
1296   PREFIX_VEX_0F3859,
1297   PREFIX_VEX_0F385A,
1298   PREFIX_VEX_0F3878,
1299   PREFIX_VEX_0F3879,
1300   PREFIX_VEX_0F388C,
1301   PREFIX_VEX_0F388E,
1302   PREFIX_VEX_0F3890,
1303   PREFIX_VEX_0F3891,
1304   PREFIX_VEX_0F3892,
1305   PREFIX_VEX_0F3893,
1306   PREFIX_VEX_0F3896,
1307   PREFIX_VEX_0F3897,
1308   PREFIX_VEX_0F3898,
1309   PREFIX_VEX_0F3899,
1310   PREFIX_VEX_0F389A,
1311   PREFIX_VEX_0F389B,
1312   PREFIX_VEX_0F389C,
1313   PREFIX_VEX_0F389D,
1314   PREFIX_VEX_0F389E,
1315   PREFIX_VEX_0F389F,
1316   PREFIX_VEX_0F38A6,
1317   PREFIX_VEX_0F38A7,
1318   PREFIX_VEX_0F38A8,
1319   PREFIX_VEX_0F38A9,
1320   PREFIX_VEX_0F38AA,
1321   PREFIX_VEX_0F38AB,
1322   PREFIX_VEX_0F38AC,
1323   PREFIX_VEX_0F38AD,
1324   PREFIX_VEX_0F38AE,
1325   PREFIX_VEX_0F38AF,
1326   PREFIX_VEX_0F38B6,
1327   PREFIX_VEX_0F38B7,
1328   PREFIX_VEX_0F38B8,
1329   PREFIX_VEX_0F38B9,
1330   PREFIX_VEX_0F38BA,
1331   PREFIX_VEX_0F38BB,
1332   PREFIX_VEX_0F38BC,
1333   PREFIX_VEX_0F38BD,
1334   PREFIX_VEX_0F38BE,
1335   PREFIX_VEX_0F38BF,
1336   PREFIX_VEX_0F38CF,
1337   PREFIX_VEX_0F38DB,
1338   PREFIX_VEX_0F38DC,
1339   PREFIX_VEX_0F38DD,
1340   PREFIX_VEX_0F38DE,
1341   PREFIX_VEX_0F38DF,
1342   PREFIX_VEX_0F38F2,
1343   PREFIX_VEX_0F38F3_REG_1,
1344   PREFIX_VEX_0F38F3_REG_2,
1345   PREFIX_VEX_0F38F3_REG_3,
1346   PREFIX_VEX_0F38F5,
1347   PREFIX_VEX_0F38F6,
1348   PREFIX_VEX_0F38F7,
1349   PREFIX_VEX_0F3A00,
1350   PREFIX_VEX_0F3A01,
1351   PREFIX_VEX_0F3A02,
1352   PREFIX_VEX_0F3A04,
1353   PREFIX_VEX_0F3A05,
1354   PREFIX_VEX_0F3A06,
1355   PREFIX_VEX_0F3A08,
1356   PREFIX_VEX_0F3A09,
1357   PREFIX_VEX_0F3A0A,
1358   PREFIX_VEX_0F3A0B,
1359   PREFIX_VEX_0F3A0C,
1360   PREFIX_VEX_0F3A0D,
1361   PREFIX_VEX_0F3A0E,
1362   PREFIX_VEX_0F3A0F,
1363   PREFIX_VEX_0F3A14,
1364   PREFIX_VEX_0F3A15,
1365   PREFIX_VEX_0F3A16,
1366   PREFIX_VEX_0F3A17,
1367   PREFIX_VEX_0F3A18,
1368   PREFIX_VEX_0F3A19,
1369   PREFIX_VEX_0F3A1D,
1370   PREFIX_VEX_0F3A20,
1371   PREFIX_VEX_0F3A21,
1372   PREFIX_VEX_0F3A22,
1373   PREFIX_VEX_0F3A30,
1374   PREFIX_VEX_0F3A31,
1375   PREFIX_VEX_0F3A32,
1376   PREFIX_VEX_0F3A33,
1377   PREFIX_VEX_0F3A38,
1378   PREFIX_VEX_0F3A39,
1379   PREFIX_VEX_0F3A40,
1380   PREFIX_VEX_0F3A41,
1381   PREFIX_VEX_0F3A42,
1382   PREFIX_VEX_0F3A44,
1383   PREFIX_VEX_0F3A46,
1384   PREFIX_VEX_0F3A48,
1385   PREFIX_VEX_0F3A49,
1386   PREFIX_VEX_0F3A4A,
1387   PREFIX_VEX_0F3A4B,
1388   PREFIX_VEX_0F3A4C,
1389   PREFIX_VEX_0F3A5C,
1390   PREFIX_VEX_0F3A5D,
1391   PREFIX_VEX_0F3A5E,
1392   PREFIX_VEX_0F3A5F,
1393   PREFIX_VEX_0F3A60,
1394   PREFIX_VEX_0F3A61,
1395   PREFIX_VEX_0F3A62,
1396   PREFIX_VEX_0F3A63,
1397   PREFIX_VEX_0F3A68,
1398   PREFIX_VEX_0F3A69,
1399   PREFIX_VEX_0F3A6A,
1400   PREFIX_VEX_0F3A6B,
1401   PREFIX_VEX_0F3A6C,
1402   PREFIX_VEX_0F3A6D,
1403   PREFIX_VEX_0F3A6E,
1404   PREFIX_VEX_0F3A6F,
1405   PREFIX_VEX_0F3A78,
1406   PREFIX_VEX_0F3A79,
1407   PREFIX_VEX_0F3A7A,
1408   PREFIX_VEX_0F3A7B,
1409   PREFIX_VEX_0F3A7C,
1410   PREFIX_VEX_0F3A7D,
1411   PREFIX_VEX_0F3A7E,
1412   PREFIX_VEX_0F3A7F,
1413   PREFIX_VEX_0F3ACE,
1414   PREFIX_VEX_0F3ACF,
1415   PREFIX_VEX_0F3ADF,
1416   PREFIX_VEX_0F3AF0,
1417
1418   PREFIX_EVEX_0F10,
1419   PREFIX_EVEX_0F11,
1420   PREFIX_EVEX_0F12,
1421   PREFIX_EVEX_0F13,
1422   PREFIX_EVEX_0F14,
1423   PREFIX_EVEX_0F15,
1424   PREFIX_EVEX_0F16,
1425   PREFIX_EVEX_0F17,
1426   PREFIX_EVEX_0F28,
1427   PREFIX_EVEX_0F29,
1428   PREFIX_EVEX_0F2A,
1429   PREFIX_EVEX_0F2B,
1430   PREFIX_EVEX_0F2C,
1431   PREFIX_EVEX_0F2D,
1432   PREFIX_EVEX_0F2E,
1433   PREFIX_EVEX_0F2F,
1434   PREFIX_EVEX_0F51,
1435   PREFIX_EVEX_0F54,
1436   PREFIX_EVEX_0F55,
1437   PREFIX_EVEX_0F56,
1438   PREFIX_EVEX_0F57,
1439   PREFIX_EVEX_0F58,
1440   PREFIX_EVEX_0F59,
1441   PREFIX_EVEX_0F5A,
1442   PREFIX_EVEX_0F5B,
1443   PREFIX_EVEX_0F5C,
1444   PREFIX_EVEX_0F5D,
1445   PREFIX_EVEX_0F5E,
1446   PREFIX_EVEX_0F5F,
1447   PREFIX_EVEX_0F60,
1448   PREFIX_EVEX_0F61,
1449   PREFIX_EVEX_0F62,
1450   PREFIX_EVEX_0F63,
1451   PREFIX_EVEX_0F64,
1452   PREFIX_EVEX_0F65,
1453   PREFIX_EVEX_0F66,
1454   PREFIX_EVEX_0F67,
1455   PREFIX_EVEX_0F68,
1456   PREFIX_EVEX_0F69,
1457   PREFIX_EVEX_0F6A,
1458   PREFIX_EVEX_0F6B,
1459   PREFIX_EVEX_0F6C,
1460   PREFIX_EVEX_0F6D,
1461   PREFIX_EVEX_0F6E,
1462   PREFIX_EVEX_0F6F,
1463   PREFIX_EVEX_0F70,
1464   PREFIX_EVEX_0F71_REG_2,
1465   PREFIX_EVEX_0F71_REG_4,
1466   PREFIX_EVEX_0F71_REG_6,
1467   PREFIX_EVEX_0F72_REG_0,
1468   PREFIX_EVEX_0F72_REG_1,
1469   PREFIX_EVEX_0F72_REG_2,
1470   PREFIX_EVEX_0F72_REG_4,
1471   PREFIX_EVEX_0F72_REG_6,
1472   PREFIX_EVEX_0F73_REG_2,
1473   PREFIX_EVEX_0F73_REG_3,
1474   PREFIX_EVEX_0F73_REG_6,
1475   PREFIX_EVEX_0F73_REG_7,
1476   PREFIX_EVEX_0F74,
1477   PREFIX_EVEX_0F75,
1478   PREFIX_EVEX_0F76,
1479   PREFIX_EVEX_0F78,
1480   PREFIX_EVEX_0F79,
1481   PREFIX_EVEX_0F7A,
1482   PREFIX_EVEX_0F7B,
1483   PREFIX_EVEX_0F7E,
1484   PREFIX_EVEX_0F7F,
1485   PREFIX_EVEX_0FC2,
1486   PREFIX_EVEX_0FC4,
1487   PREFIX_EVEX_0FC5,
1488   PREFIX_EVEX_0FC6,
1489   PREFIX_EVEX_0FD1,
1490   PREFIX_EVEX_0FD2,
1491   PREFIX_EVEX_0FD3,
1492   PREFIX_EVEX_0FD4,
1493   PREFIX_EVEX_0FD5,
1494   PREFIX_EVEX_0FD6,
1495   PREFIX_EVEX_0FD8,
1496   PREFIX_EVEX_0FD9,
1497   PREFIX_EVEX_0FDA,
1498   PREFIX_EVEX_0FDB,
1499   PREFIX_EVEX_0FDC,
1500   PREFIX_EVEX_0FDD,
1501   PREFIX_EVEX_0FDE,
1502   PREFIX_EVEX_0FDF,
1503   PREFIX_EVEX_0FE0,
1504   PREFIX_EVEX_0FE1,
1505   PREFIX_EVEX_0FE2,
1506   PREFIX_EVEX_0FE3,
1507   PREFIX_EVEX_0FE4,
1508   PREFIX_EVEX_0FE5,
1509   PREFIX_EVEX_0FE6,
1510   PREFIX_EVEX_0FE7,
1511   PREFIX_EVEX_0FE8,
1512   PREFIX_EVEX_0FE9,
1513   PREFIX_EVEX_0FEA,
1514   PREFIX_EVEX_0FEB,
1515   PREFIX_EVEX_0FEC,
1516   PREFIX_EVEX_0FED,
1517   PREFIX_EVEX_0FEE,
1518   PREFIX_EVEX_0FEF,
1519   PREFIX_EVEX_0FF1,
1520   PREFIX_EVEX_0FF2,
1521   PREFIX_EVEX_0FF3,
1522   PREFIX_EVEX_0FF4,
1523   PREFIX_EVEX_0FF5,
1524   PREFIX_EVEX_0FF6,
1525   PREFIX_EVEX_0FF8,
1526   PREFIX_EVEX_0FF9,
1527   PREFIX_EVEX_0FFA,
1528   PREFIX_EVEX_0FFB,
1529   PREFIX_EVEX_0FFC,
1530   PREFIX_EVEX_0FFD,
1531   PREFIX_EVEX_0FFE,
1532   PREFIX_EVEX_0F3800,
1533   PREFIX_EVEX_0F3804,
1534   PREFIX_EVEX_0F380B,
1535   PREFIX_EVEX_0F380C,
1536   PREFIX_EVEX_0F380D,
1537   PREFIX_EVEX_0F3810,
1538   PREFIX_EVEX_0F3811,
1539   PREFIX_EVEX_0F3812,
1540   PREFIX_EVEX_0F3813,
1541   PREFIX_EVEX_0F3814,
1542   PREFIX_EVEX_0F3815,
1543   PREFIX_EVEX_0F3816,
1544   PREFIX_EVEX_0F3818,
1545   PREFIX_EVEX_0F3819,
1546   PREFIX_EVEX_0F381A,
1547   PREFIX_EVEX_0F381B,
1548   PREFIX_EVEX_0F381C,
1549   PREFIX_EVEX_0F381D,
1550   PREFIX_EVEX_0F381E,
1551   PREFIX_EVEX_0F381F,
1552   PREFIX_EVEX_0F3820,
1553   PREFIX_EVEX_0F3821,
1554   PREFIX_EVEX_0F3822,
1555   PREFIX_EVEX_0F3823,
1556   PREFIX_EVEX_0F3824,
1557   PREFIX_EVEX_0F3825,
1558   PREFIX_EVEX_0F3826,
1559   PREFIX_EVEX_0F3827,
1560   PREFIX_EVEX_0F3828,
1561   PREFIX_EVEX_0F3829,
1562   PREFIX_EVEX_0F382A,
1563   PREFIX_EVEX_0F382B,
1564   PREFIX_EVEX_0F382C,
1565   PREFIX_EVEX_0F382D,
1566   PREFIX_EVEX_0F3830,
1567   PREFIX_EVEX_0F3831,
1568   PREFIX_EVEX_0F3832,
1569   PREFIX_EVEX_0F3833,
1570   PREFIX_EVEX_0F3834,
1571   PREFIX_EVEX_0F3835,
1572   PREFIX_EVEX_0F3836,
1573   PREFIX_EVEX_0F3837,
1574   PREFIX_EVEX_0F3838,
1575   PREFIX_EVEX_0F3839,
1576   PREFIX_EVEX_0F383A,
1577   PREFIX_EVEX_0F383B,
1578   PREFIX_EVEX_0F383C,
1579   PREFIX_EVEX_0F383D,
1580   PREFIX_EVEX_0F383E,
1581   PREFIX_EVEX_0F383F,
1582   PREFIX_EVEX_0F3840,
1583   PREFIX_EVEX_0F3842,
1584   PREFIX_EVEX_0F3843,
1585   PREFIX_EVEX_0F3844,
1586   PREFIX_EVEX_0F3845,
1587   PREFIX_EVEX_0F3846,
1588   PREFIX_EVEX_0F3847,
1589   PREFIX_EVEX_0F384C,
1590   PREFIX_EVEX_0F384D,
1591   PREFIX_EVEX_0F384E,
1592   PREFIX_EVEX_0F384F,
1593   PREFIX_EVEX_0F3850,
1594   PREFIX_EVEX_0F3851,
1595   PREFIX_EVEX_0F3852,
1596   PREFIX_EVEX_0F3853,
1597   PREFIX_EVEX_0F3854,
1598   PREFIX_EVEX_0F3855,
1599   PREFIX_EVEX_0F3858,
1600   PREFIX_EVEX_0F3859,
1601   PREFIX_EVEX_0F385A,
1602   PREFIX_EVEX_0F385B,
1603   PREFIX_EVEX_0F3862,
1604   PREFIX_EVEX_0F3863,
1605   PREFIX_EVEX_0F3864,
1606   PREFIX_EVEX_0F3865,
1607   PREFIX_EVEX_0F3866,
1608   PREFIX_EVEX_0F3868,
1609   PREFIX_EVEX_0F3870,
1610   PREFIX_EVEX_0F3871,
1611   PREFIX_EVEX_0F3872,
1612   PREFIX_EVEX_0F3873,
1613   PREFIX_EVEX_0F3875,
1614   PREFIX_EVEX_0F3876,
1615   PREFIX_EVEX_0F3877,
1616   PREFIX_EVEX_0F3878,
1617   PREFIX_EVEX_0F3879,
1618   PREFIX_EVEX_0F387A,
1619   PREFIX_EVEX_0F387B,
1620   PREFIX_EVEX_0F387C,
1621   PREFIX_EVEX_0F387D,
1622   PREFIX_EVEX_0F387E,
1623   PREFIX_EVEX_0F387F,
1624   PREFIX_EVEX_0F3883,
1625   PREFIX_EVEX_0F3888,
1626   PREFIX_EVEX_0F3889,
1627   PREFIX_EVEX_0F388A,
1628   PREFIX_EVEX_0F388B,
1629   PREFIX_EVEX_0F388D,
1630   PREFIX_EVEX_0F388F,
1631   PREFIX_EVEX_0F3890,
1632   PREFIX_EVEX_0F3891,
1633   PREFIX_EVEX_0F3892,
1634   PREFIX_EVEX_0F3893,
1635   PREFIX_EVEX_0F3896,
1636   PREFIX_EVEX_0F3897,
1637   PREFIX_EVEX_0F3898,
1638   PREFIX_EVEX_0F3899,
1639   PREFIX_EVEX_0F389A,
1640   PREFIX_EVEX_0F389B,
1641   PREFIX_EVEX_0F389C,
1642   PREFIX_EVEX_0F389D,
1643   PREFIX_EVEX_0F389E,
1644   PREFIX_EVEX_0F389F,
1645   PREFIX_EVEX_0F38A0,
1646   PREFIX_EVEX_0F38A1,
1647   PREFIX_EVEX_0F38A2,
1648   PREFIX_EVEX_0F38A3,
1649   PREFIX_EVEX_0F38A6,
1650   PREFIX_EVEX_0F38A7,
1651   PREFIX_EVEX_0F38A8,
1652   PREFIX_EVEX_0F38A9,
1653   PREFIX_EVEX_0F38AA,
1654   PREFIX_EVEX_0F38AB,
1655   PREFIX_EVEX_0F38AC,
1656   PREFIX_EVEX_0F38AD,
1657   PREFIX_EVEX_0F38AE,
1658   PREFIX_EVEX_0F38AF,
1659   PREFIX_EVEX_0F38B4,
1660   PREFIX_EVEX_0F38B5,
1661   PREFIX_EVEX_0F38B6,
1662   PREFIX_EVEX_0F38B7,
1663   PREFIX_EVEX_0F38B8,
1664   PREFIX_EVEX_0F38B9,
1665   PREFIX_EVEX_0F38BA,
1666   PREFIX_EVEX_0F38BB,
1667   PREFIX_EVEX_0F38BC,
1668   PREFIX_EVEX_0F38BD,
1669   PREFIX_EVEX_0F38BE,
1670   PREFIX_EVEX_0F38BF,
1671   PREFIX_EVEX_0F38C4,
1672   PREFIX_EVEX_0F38C6_REG_1,
1673   PREFIX_EVEX_0F38C6_REG_2,
1674   PREFIX_EVEX_0F38C6_REG_5,
1675   PREFIX_EVEX_0F38C6_REG_6,
1676   PREFIX_EVEX_0F38C7_REG_1,
1677   PREFIX_EVEX_0F38C7_REG_2,
1678   PREFIX_EVEX_0F38C7_REG_5,
1679   PREFIX_EVEX_0F38C7_REG_6,
1680   PREFIX_EVEX_0F38C8,
1681   PREFIX_EVEX_0F38CA,
1682   PREFIX_EVEX_0F38CB,
1683   PREFIX_EVEX_0F38CC,
1684   PREFIX_EVEX_0F38CD,
1685   PREFIX_EVEX_0F38CF,
1686   PREFIX_EVEX_0F38DC,
1687   PREFIX_EVEX_0F38DD,
1688   PREFIX_EVEX_0F38DE,
1689   PREFIX_EVEX_0F38DF,
1690
1691   PREFIX_EVEX_0F3A00,
1692   PREFIX_EVEX_0F3A01,
1693   PREFIX_EVEX_0F3A03,
1694   PREFIX_EVEX_0F3A04,
1695   PREFIX_EVEX_0F3A05,
1696   PREFIX_EVEX_0F3A08,
1697   PREFIX_EVEX_0F3A09,
1698   PREFIX_EVEX_0F3A0A,
1699   PREFIX_EVEX_0F3A0B,
1700   PREFIX_EVEX_0F3A0F,
1701   PREFIX_EVEX_0F3A14,
1702   PREFIX_EVEX_0F3A15,
1703   PREFIX_EVEX_0F3A16,
1704   PREFIX_EVEX_0F3A17,
1705   PREFIX_EVEX_0F3A18,
1706   PREFIX_EVEX_0F3A19,
1707   PREFIX_EVEX_0F3A1A,
1708   PREFIX_EVEX_0F3A1B,
1709   PREFIX_EVEX_0F3A1D,
1710   PREFIX_EVEX_0F3A1E,
1711   PREFIX_EVEX_0F3A1F,
1712   PREFIX_EVEX_0F3A20,
1713   PREFIX_EVEX_0F3A21,
1714   PREFIX_EVEX_0F3A22,
1715   PREFIX_EVEX_0F3A23,
1716   PREFIX_EVEX_0F3A25,
1717   PREFIX_EVEX_0F3A26,
1718   PREFIX_EVEX_0F3A27,
1719   PREFIX_EVEX_0F3A38,
1720   PREFIX_EVEX_0F3A39,
1721   PREFIX_EVEX_0F3A3A,
1722   PREFIX_EVEX_0F3A3B,
1723   PREFIX_EVEX_0F3A3E,
1724   PREFIX_EVEX_0F3A3F,
1725   PREFIX_EVEX_0F3A42,
1726   PREFIX_EVEX_0F3A43,
1727   PREFIX_EVEX_0F3A44,
1728   PREFIX_EVEX_0F3A50,
1729   PREFIX_EVEX_0F3A51,
1730   PREFIX_EVEX_0F3A54,
1731   PREFIX_EVEX_0F3A55,
1732   PREFIX_EVEX_0F3A56,
1733   PREFIX_EVEX_0F3A57,
1734   PREFIX_EVEX_0F3A66,
1735   PREFIX_EVEX_0F3A67,
1736   PREFIX_EVEX_0F3A70,
1737   PREFIX_EVEX_0F3A71,
1738   PREFIX_EVEX_0F3A72,
1739   PREFIX_EVEX_0F3A73,
1740   PREFIX_EVEX_0F3ACE,
1741   PREFIX_EVEX_0F3ACF
1742 };
1743
1744 enum
1745 {
1746   X86_64_06 = 0,
1747   X86_64_07,
1748   X86_64_0D,
1749   X86_64_16,
1750   X86_64_17,
1751   X86_64_1E,
1752   X86_64_1F,
1753   X86_64_27,
1754   X86_64_2F,
1755   X86_64_37,
1756   X86_64_3F,
1757   X86_64_60,
1758   X86_64_61,
1759   X86_64_62,
1760   X86_64_63,
1761   X86_64_6D,
1762   X86_64_6F,
1763   X86_64_82,
1764   X86_64_9A,
1765   X86_64_C4,
1766   X86_64_C5,
1767   X86_64_CE,
1768   X86_64_D4,
1769   X86_64_D5,
1770   X86_64_E8,
1771   X86_64_E9,
1772   X86_64_EA,
1773   X86_64_0F01_REG_0,
1774   X86_64_0F01_REG_1,
1775   X86_64_0F01_REG_2,
1776   X86_64_0F01_REG_3
1777 };
1778
1779 enum
1780 {
1781   THREE_BYTE_0F38 = 0,
1782   THREE_BYTE_0F3A
1783 };
1784
1785 enum
1786 {
1787   XOP_08 = 0,
1788   XOP_09,
1789   XOP_0A
1790 };
1791
1792 enum
1793 {
1794   VEX_0F = 0,
1795   VEX_0F38,
1796   VEX_0F3A
1797 };
1798
1799 enum
1800 {
1801   EVEX_0F = 0,
1802   EVEX_0F38,
1803   EVEX_0F3A
1804 };
1805
1806 enum
1807 {
1808   VEX_LEN_0F12_P_0_M_0 = 0,
1809   VEX_LEN_0F12_P_0_M_1,
1810   VEX_LEN_0F12_P_2,
1811   VEX_LEN_0F13_M_0,
1812   VEX_LEN_0F16_P_0_M_0,
1813   VEX_LEN_0F16_P_0_M_1,
1814   VEX_LEN_0F16_P_2,
1815   VEX_LEN_0F17_M_0,
1816   VEX_LEN_0F41_P_0,
1817   VEX_LEN_0F41_P_2,
1818   VEX_LEN_0F42_P_0,
1819   VEX_LEN_0F42_P_2,
1820   VEX_LEN_0F44_P_0,
1821   VEX_LEN_0F44_P_2,
1822   VEX_LEN_0F45_P_0,
1823   VEX_LEN_0F45_P_2,
1824   VEX_LEN_0F46_P_0,
1825   VEX_LEN_0F46_P_2,
1826   VEX_LEN_0F47_P_0,
1827   VEX_LEN_0F47_P_2,
1828   VEX_LEN_0F4A_P_0,
1829   VEX_LEN_0F4A_P_2,
1830   VEX_LEN_0F4B_P_0,
1831   VEX_LEN_0F4B_P_2,
1832   VEX_LEN_0F6E_P_2,
1833   VEX_LEN_0F77_P_0,
1834   VEX_LEN_0F7E_P_1,
1835   VEX_LEN_0F7E_P_2,
1836   VEX_LEN_0F90_P_0,
1837   VEX_LEN_0F90_P_2,
1838   VEX_LEN_0F91_P_0,
1839   VEX_LEN_0F91_P_2,
1840   VEX_LEN_0F92_P_0,
1841   VEX_LEN_0F92_P_2,
1842   VEX_LEN_0F92_P_3,
1843   VEX_LEN_0F93_P_0,
1844   VEX_LEN_0F93_P_2,
1845   VEX_LEN_0F93_P_3,
1846   VEX_LEN_0F98_P_0,
1847   VEX_LEN_0F98_P_2,
1848   VEX_LEN_0F99_P_0,
1849   VEX_LEN_0F99_P_2,
1850   VEX_LEN_0FAE_R_2_M_0,
1851   VEX_LEN_0FAE_R_3_M_0,
1852   VEX_LEN_0FC4_P_2,
1853   VEX_LEN_0FC5_P_2,
1854   VEX_LEN_0FD6_P_2,
1855   VEX_LEN_0FF7_P_2,
1856   VEX_LEN_0F3816_P_2,
1857   VEX_LEN_0F3819_P_2,
1858   VEX_LEN_0F381A_P_2_M_0,
1859   VEX_LEN_0F3836_P_2,
1860   VEX_LEN_0F3841_P_2,
1861   VEX_LEN_0F385A_P_2_M_0,
1862   VEX_LEN_0F38DB_P_2,
1863   VEX_LEN_0F38F2_P_0,
1864   VEX_LEN_0F38F3_R_1_P_0,
1865   VEX_LEN_0F38F3_R_2_P_0,
1866   VEX_LEN_0F38F3_R_3_P_0,
1867   VEX_LEN_0F38F5_P_0,
1868   VEX_LEN_0F38F5_P_1,
1869   VEX_LEN_0F38F5_P_3,
1870   VEX_LEN_0F38F6_P_3,
1871   VEX_LEN_0F38F7_P_0,
1872   VEX_LEN_0F38F7_P_1,
1873   VEX_LEN_0F38F7_P_2,
1874   VEX_LEN_0F38F7_P_3,
1875   VEX_LEN_0F3A00_P_2,
1876   VEX_LEN_0F3A01_P_2,
1877   VEX_LEN_0F3A06_P_2,
1878   VEX_LEN_0F3A14_P_2,
1879   VEX_LEN_0F3A15_P_2,
1880   VEX_LEN_0F3A16_P_2,
1881   VEX_LEN_0F3A17_P_2,
1882   VEX_LEN_0F3A18_P_2,
1883   VEX_LEN_0F3A19_P_2,
1884   VEX_LEN_0F3A20_P_2,
1885   VEX_LEN_0F3A21_P_2,
1886   VEX_LEN_0F3A22_P_2,
1887   VEX_LEN_0F3A30_P_2,
1888   VEX_LEN_0F3A31_P_2,
1889   VEX_LEN_0F3A32_P_2,
1890   VEX_LEN_0F3A33_P_2,
1891   VEX_LEN_0F3A38_P_2,
1892   VEX_LEN_0F3A39_P_2,
1893   VEX_LEN_0F3A41_P_2,
1894   VEX_LEN_0F3A46_P_2,
1895   VEX_LEN_0F3A60_P_2,
1896   VEX_LEN_0F3A61_P_2,
1897   VEX_LEN_0F3A62_P_2,
1898   VEX_LEN_0F3A63_P_2,
1899   VEX_LEN_0F3A6A_P_2,
1900   VEX_LEN_0F3A6B_P_2,
1901   VEX_LEN_0F3A6E_P_2,
1902   VEX_LEN_0F3A6F_P_2,
1903   VEX_LEN_0F3A7A_P_2,
1904   VEX_LEN_0F3A7B_P_2,
1905   VEX_LEN_0F3A7E_P_2,
1906   VEX_LEN_0F3A7F_P_2,
1907   VEX_LEN_0F3ADF_P_2,
1908   VEX_LEN_0F3AF0_P_3,
1909   VEX_LEN_0FXOP_08_CC,
1910   VEX_LEN_0FXOP_08_CD,
1911   VEX_LEN_0FXOP_08_CE,
1912   VEX_LEN_0FXOP_08_CF,
1913   VEX_LEN_0FXOP_08_EC,
1914   VEX_LEN_0FXOP_08_ED,
1915   VEX_LEN_0FXOP_08_EE,
1916   VEX_LEN_0FXOP_08_EF,
1917   VEX_LEN_0FXOP_09_80,
1918   VEX_LEN_0FXOP_09_81
1919 };
1920
1921 enum
1922 {
1923   EVEX_LEN_0F6E_P_2 = 0,
1924   EVEX_LEN_0F7E_P_1,
1925   EVEX_LEN_0F7E_P_2,
1926   EVEX_LEN_0FD6_P_2,
1927   EVEX_LEN_0F3819_P_2_W_0,
1928   EVEX_LEN_0F3819_P_2_W_1,
1929   EVEX_LEN_0F381A_P_2_W_0,
1930   EVEX_LEN_0F381A_P_2_W_1,
1931   EVEX_LEN_0F381B_P_2_W_0,
1932   EVEX_LEN_0F381B_P_2_W_1,
1933   EVEX_LEN_0F385A_P_2_W_0,
1934   EVEX_LEN_0F385A_P_2_W_1,
1935   EVEX_LEN_0F385B_P_2_W_0,
1936   EVEX_LEN_0F385B_P_2_W_1,
1937   EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1938   EVEX_LEN_0F38C6_REG_2_PREFIX_2,
1939   EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1940   EVEX_LEN_0F38C6_REG_6_PREFIX_2,
1941   EVEX_LEN_0F38C7_R_1_P_2_W_0,
1942   EVEX_LEN_0F38C7_R_1_P_2_W_1,
1943   EVEX_LEN_0F38C7_R_2_P_2_W_0,
1944   EVEX_LEN_0F38C7_R_2_P_2_W_1,
1945   EVEX_LEN_0F38C7_R_5_P_2_W_0,
1946   EVEX_LEN_0F38C7_R_5_P_2_W_1,
1947   EVEX_LEN_0F38C7_R_6_P_2_W_0,
1948   EVEX_LEN_0F38C7_R_6_P_2_W_1,
1949   EVEX_LEN_0F3A18_P_2_W_0,
1950   EVEX_LEN_0F3A18_P_2_W_1,
1951   EVEX_LEN_0F3A19_P_2_W_0,
1952   EVEX_LEN_0F3A19_P_2_W_1,
1953   EVEX_LEN_0F3A1A_P_2_W_0,
1954   EVEX_LEN_0F3A1A_P_2_W_1,
1955   EVEX_LEN_0F3A1B_P_2_W_0,
1956   EVEX_LEN_0F3A1B_P_2_W_1,
1957   EVEX_LEN_0F3A23_P_2_W_0,
1958   EVEX_LEN_0F3A23_P_2_W_1,
1959   EVEX_LEN_0F3A38_P_2_W_0,
1960   EVEX_LEN_0F3A38_P_2_W_1,
1961   EVEX_LEN_0F3A39_P_2_W_0,
1962   EVEX_LEN_0F3A39_P_2_W_1,
1963   EVEX_LEN_0F3A3A_P_2_W_0,
1964   EVEX_LEN_0F3A3A_P_2_W_1,
1965   EVEX_LEN_0F3A3B_P_2_W_0,
1966   EVEX_LEN_0F3A3B_P_2_W_1,
1967   EVEX_LEN_0F3A43_P_2_W_0,
1968   EVEX_LEN_0F3A43_P_2_W_1
1969 };
1970
1971 enum
1972 {
1973   VEX_W_0F41_P_0_LEN_1 = 0,
1974   VEX_W_0F41_P_2_LEN_1,
1975   VEX_W_0F42_P_0_LEN_1,
1976   VEX_W_0F42_P_2_LEN_1,
1977   VEX_W_0F44_P_0_LEN_0,
1978   VEX_W_0F44_P_2_LEN_0,
1979   VEX_W_0F45_P_0_LEN_1,
1980   VEX_W_0F45_P_2_LEN_1,
1981   VEX_W_0F46_P_0_LEN_1,
1982   VEX_W_0F46_P_2_LEN_1,
1983   VEX_W_0F47_P_0_LEN_1,
1984   VEX_W_0F47_P_2_LEN_1,
1985   VEX_W_0F4A_P_0_LEN_1,
1986   VEX_W_0F4A_P_2_LEN_1,
1987   VEX_W_0F4B_P_0_LEN_1,
1988   VEX_W_0F4B_P_2_LEN_1,
1989   VEX_W_0F90_P_0_LEN_0,
1990   VEX_W_0F90_P_2_LEN_0,
1991   VEX_W_0F91_P_0_LEN_0,
1992   VEX_W_0F91_P_2_LEN_0,
1993   VEX_W_0F92_P_0_LEN_0,
1994   VEX_W_0F92_P_2_LEN_0,
1995   VEX_W_0F93_P_0_LEN_0,
1996   VEX_W_0F93_P_2_LEN_0,
1997   VEX_W_0F98_P_0_LEN_0,
1998   VEX_W_0F98_P_2_LEN_0,
1999   VEX_W_0F99_P_0_LEN_0,
2000   VEX_W_0F99_P_2_LEN_0,
2001   VEX_W_0F380C_P_2,
2002   VEX_W_0F380D_P_2,
2003   VEX_W_0F380E_P_2,
2004   VEX_W_0F380F_P_2,
2005   VEX_W_0F3816_P_2,
2006   VEX_W_0F3818_P_2,
2007   VEX_W_0F3819_P_2,
2008   VEX_W_0F381A_P_2_M_0,
2009   VEX_W_0F382C_P_2_M_0,
2010   VEX_W_0F382D_P_2_M_0,
2011   VEX_W_0F382E_P_2_M_0,
2012   VEX_W_0F382F_P_2_M_0,
2013   VEX_W_0F3836_P_2,
2014   VEX_W_0F3846_P_2,
2015   VEX_W_0F3858_P_2,
2016   VEX_W_0F3859_P_2,
2017   VEX_W_0F385A_P_2_M_0,
2018   VEX_W_0F3878_P_2,
2019   VEX_W_0F3879_P_2,
2020   VEX_W_0F38CF_P_2,
2021   VEX_W_0F3A00_P_2,
2022   VEX_W_0F3A01_P_2,
2023   VEX_W_0F3A02_P_2,
2024   VEX_W_0F3A04_P_2,
2025   VEX_W_0F3A05_P_2,
2026   VEX_W_0F3A06_P_2,
2027   VEX_W_0F3A18_P_2,
2028   VEX_W_0F3A19_P_2,
2029   VEX_W_0F3A30_P_2_LEN_0,
2030   VEX_W_0F3A31_P_2_LEN_0,
2031   VEX_W_0F3A32_P_2_LEN_0,
2032   VEX_W_0F3A33_P_2_LEN_0,
2033   VEX_W_0F3A38_P_2,
2034   VEX_W_0F3A39_P_2,
2035   VEX_W_0F3A46_P_2,
2036   VEX_W_0F3A48_P_2,
2037   VEX_W_0F3A49_P_2,
2038   VEX_W_0F3A4A_P_2,
2039   VEX_W_0F3A4B_P_2,
2040   VEX_W_0F3A4C_P_2,
2041   VEX_W_0F3ACE_P_2,
2042   VEX_W_0F3ACF_P_2,
2043
2044   EVEX_W_0F10_P_0,
2045   EVEX_W_0F10_P_1,
2046   EVEX_W_0F10_P_2,
2047   EVEX_W_0F10_P_3,
2048   EVEX_W_0F11_P_0,
2049   EVEX_W_0F11_P_1,
2050   EVEX_W_0F11_P_2,
2051   EVEX_W_0F11_P_3,
2052   EVEX_W_0F12_P_0_M_0,
2053   EVEX_W_0F12_P_0_M_1,
2054   EVEX_W_0F12_P_1,
2055   EVEX_W_0F12_P_2,
2056   EVEX_W_0F12_P_3,
2057   EVEX_W_0F13_P_0,
2058   EVEX_W_0F13_P_2,
2059   EVEX_W_0F14_P_0,
2060   EVEX_W_0F14_P_2,
2061   EVEX_W_0F15_P_0,
2062   EVEX_W_0F15_P_2,
2063   EVEX_W_0F16_P_0_M_0,
2064   EVEX_W_0F16_P_0_M_1,
2065   EVEX_W_0F16_P_1,
2066   EVEX_W_0F16_P_2,
2067   EVEX_W_0F17_P_0,
2068   EVEX_W_0F17_P_2,
2069   EVEX_W_0F28_P_0,
2070   EVEX_W_0F28_P_2,
2071   EVEX_W_0F29_P_0,
2072   EVEX_W_0F29_P_2,
2073   EVEX_W_0F2A_P_3,
2074   EVEX_W_0F2B_P_0,
2075   EVEX_W_0F2B_P_2,
2076   EVEX_W_0F2E_P_0,
2077   EVEX_W_0F2E_P_2,
2078   EVEX_W_0F2F_P_0,
2079   EVEX_W_0F2F_P_2,
2080   EVEX_W_0F51_P_0,
2081   EVEX_W_0F51_P_1,
2082   EVEX_W_0F51_P_2,
2083   EVEX_W_0F51_P_3,
2084   EVEX_W_0F54_P_0,
2085   EVEX_W_0F54_P_2,
2086   EVEX_W_0F55_P_0,
2087   EVEX_W_0F55_P_2,
2088   EVEX_W_0F56_P_0,
2089   EVEX_W_0F56_P_2,
2090   EVEX_W_0F57_P_0,
2091   EVEX_W_0F57_P_2,
2092   EVEX_W_0F58_P_0,
2093   EVEX_W_0F58_P_1,
2094   EVEX_W_0F58_P_2,
2095   EVEX_W_0F58_P_3,
2096   EVEX_W_0F59_P_0,
2097   EVEX_W_0F59_P_1,
2098   EVEX_W_0F59_P_2,
2099   EVEX_W_0F59_P_3,
2100   EVEX_W_0F5A_P_0,
2101   EVEX_W_0F5A_P_1,
2102   EVEX_W_0F5A_P_2,
2103   EVEX_W_0F5A_P_3,
2104   EVEX_W_0F5B_P_0,
2105   EVEX_W_0F5B_P_1,
2106   EVEX_W_0F5B_P_2,
2107   EVEX_W_0F5C_P_0,
2108   EVEX_W_0F5C_P_1,
2109   EVEX_W_0F5C_P_2,
2110   EVEX_W_0F5C_P_3,
2111   EVEX_W_0F5D_P_0,
2112   EVEX_W_0F5D_P_1,
2113   EVEX_W_0F5D_P_2,
2114   EVEX_W_0F5D_P_3,
2115   EVEX_W_0F5E_P_0,
2116   EVEX_W_0F5E_P_1,
2117   EVEX_W_0F5E_P_2,
2118   EVEX_W_0F5E_P_3,
2119   EVEX_W_0F5F_P_0,
2120   EVEX_W_0F5F_P_1,
2121   EVEX_W_0F5F_P_2,
2122   EVEX_W_0F5F_P_3,
2123   EVEX_W_0F62_P_2,
2124   EVEX_W_0F66_P_2,
2125   EVEX_W_0F6A_P_2,
2126   EVEX_W_0F6B_P_2,
2127   EVEX_W_0F6C_P_2,
2128   EVEX_W_0F6D_P_2,
2129   EVEX_W_0F6F_P_1,
2130   EVEX_W_0F6F_P_2,
2131   EVEX_W_0F6F_P_3,
2132   EVEX_W_0F70_P_2,
2133   EVEX_W_0F72_R_2_P_2,
2134   EVEX_W_0F72_R_6_P_2,
2135   EVEX_W_0F73_R_2_P_2,
2136   EVEX_W_0F73_R_6_P_2,
2137   EVEX_W_0F76_P_2,
2138   EVEX_W_0F78_P_0,
2139   EVEX_W_0F78_P_2,
2140   EVEX_W_0F79_P_0,
2141   EVEX_W_0F79_P_2,
2142   EVEX_W_0F7A_P_1,
2143   EVEX_W_0F7A_P_2,
2144   EVEX_W_0F7A_P_3,
2145   EVEX_W_0F7B_P_2,
2146   EVEX_W_0F7B_P_3,
2147   EVEX_W_0F7E_P_1,
2148   EVEX_W_0F7F_P_1,
2149   EVEX_W_0F7F_P_2,
2150   EVEX_W_0F7F_P_3,
2151   EVEX_W_0FC2_P_0,
2152   EVEX_W_0FC2_P_1,
2153   EVEX_W_0FC2_P_2,
2154   EVEX_W_0FC2_P_3,
2155   EVEX_W_0FC6_P_0,
2156   EVEX_W_0FC6_P_2,
2157   EVEX_W_0FD2_P_2,
2158   EVEX_W_0FD3_P_2,
2159   EVEX_W_0FD4_P_2,
2160   EVEX_W_0FD6_P_2,
2161   EVEX_W_0FE6_P_1,
2162   EVEX_W_0FE6_P_2,
2163   EVEX_W_0FE6_P_3,
2164   EVEX_W_0FE7_P_2,
2165   EVEX_W_0FF2_P_2,
2166   EVEX_W_0FF3_P_2,
2167   EVEX_W_0FF4_P_2,
2168   EVEX_W_0FFA_P_2,
2169   EVEX_W_0FFB_P_2,
2170   EVEX_W_0FFE_P_2,
2171   EVEX_W_0F380C_P_2,
2172   EVEX_W_0F380D_P_2,
2173   EVEX_W_0F3810_P_1,
2174   EVEX_W_0F3810_P_2,
2175   EVEX_W_0F3811_P_1,
2176   EVEX_W_0F3811_P_2,
2177   EVEX_W_0F3812_P_1,
2178   EVEX_W_0F3812_P_2,
2179   EVEX_W_0F3813_P_1,
2180   EVEX_W_0F3813_P_2,
2181   EVEX_W_0F3814_P_1,
2182   EVEX_W_0F3815_P_1,
2183   EVEX_W_0F3818_P_2,
2184   EVEX_W_0F3819_P_2,
2185   EVEX_W_0F381A_P_2,
2186   EVEX_W_0F381B_P_2,
2187   EVEX_W_0F381E_P_2,
2188   EVEX_W_0F381F_P_2,
2189   EVEX_W_0F3820_P_1,
2190   EVEX_W_0F3821_P_1,
2191   EVEX_W_0F3822_P_1,
2192   EVEX_W_0F3823_P_1,
2193   EVEX_W_0F3824_P_1,
2194   EVEX_W_0F3825_P_1,
2195   EVEX_W_0F3825_P_2,
2196   EVEX_W_0F3826_P_1,
2197   EVEX_W_0F3826_P_2,
2198   EVEX_W_0F3828_P_1,
2199   EVEX_W_0F3828_P_2,
2200   EVEX_W_0F3829_P_1,
2201   EVEX_W_0F3829_P_2,
2202   EVEX_W_0F382A_P_1,
2203   EVEX_W_0F382A_P_2,
2204   EVEX_W_0F382B_P_2,
2205   EVEX_W_0F3830_P_1,
2206   EVEX_W_0F3831_P_1,
2207   EVEX_W_0F3832_P_1,
2208   EVEX_W_0F3833_P_1,
2209   EVEX_W_0F3834_P_1,
2210   EVEX_W_0F3835_P_1,
2211   EVEX_W_0F3835_P_2,
2212   EVEX_W_0F3837_P_2,
2213   EVEX_W_0F3838_P_1,
2214   EVEX_W_0F3839_P_1,
2215   EVEX_W_0F383A_P_1,
2216   EVEX_W_0F3840_P_2,
2217   EVEX_W_0F3852_P_1,
2218   EVEX_W_0F3854_P_2,
2219   EVEX_W_0F3855_P_2,
2220   EVEX_W_0F3858_P_2,
2221   EVEX_W_0F3859_P_2,
2222   EVEX_W_0F385A_P_2,
2223   EVEX_W_0F385B_P_2,
2224   EVEX_W_0F3862_P_2,
2225   EVEX_W_0F3863_P_2,
2226   EVEX_W_0F3866_P_2,
2227   EVEX_W_0F3868_P_3,
2228   EVEX_W_0F3870_P_2,
2229   EVEX_W_0F3871_P_2,
2230   EVEX_W_0F3872_P_1,
2231   EVEX_W_0F3872_P_2,
2232   EVEX_W_0F3872_P_3,
2233   EVEX_W_0F3873_P_2,
2234   EVEX_W_0F3875_P_2,
2235   EVEX_W_0F3878_P_2,
2236   EVEX_W_0F3879_P_2,
2237   EVEX_W_0F387A_P_2,
2238   EVEX_W_0F387B_P_2,
2239   EVEX_W_0F387D_P_2,
2240   EVEX_W_0F3883_P_2,
2241   EVEX_W_0F388D_P_2,
2242   EVEX_W_0F3891_P_2,
2243   EVEX_W_0F3893_P_2,
2244   EVEX_W_0F38A1_P_2,
2245   EVEX_W_0F38A3_P_2,
2246   EVEX_W_0F38C7_R_1_P_2,
2247   EVEX_W_0F38C7_R_2_P_2,
2248   EVEX_W_0F38C7_R_5_P_2,
2249   EVEX_W_0F38C7_R_6_P_2,
2250
2251   EVEX_W_0F3A00_P_2,
2252   EVEX_W_0F3A01_P_2,
2253   EVEX_W_0F3A04_P_2,
2254   EVEX_W_0F3A05_P_2,
2255   EVEX_W_0F3A08_P_2,
2256   EVEX_W_0F3A09_P_2,
2257   EVEX_W_0F3A0A_P_2,
2258   EVEX_W_0F3A0B_P_2,
2259   EVEX_W_0F3A18_P_2,
2260   EVEX_W_0F3A19_P_2,
2261   EVEX_W_0F3A1A_P_2,
2262   EVEX_W_0F3A1B_P_2,
2263   EVEX_W_0F3A1D_P_2,
2264   EVEX_W_0F3A21_P_2,
2265   EVEX_W_0F3A23_P_2,
2266   EVEX_W_0F3A38_P_2,
2267   EVEX_W_0F3A39_P_2,
2268   EVEX_W_0F3A3A_P_2,
2269   EVEX_W_0F3A3B_P_2,
2270   EVEX_W_0F3A3E_P_2,
2271   EVEX_W_0F3A3F_P_2,
2272   EVEX_W_0F3A42_P_2,
2273   EVEX_W_0F3A43_P_2,
2274   EVEX_W_0F3A50_P_2,
2275   EVEX_W_0F3A51_P_2,
2276   EVEX_W_0F3A56_P_2,
2277   EVEX_W_0F3A57_P_2,
2278   EVEX_W_0F3A66_P_2,
2279   EVEX_W_0F3A67_P_2,
2280   EVEX_W_0F3A70_P_2,
2281   EVEX_W_0F3A71_P_2,
2282   EVEX_W_0F3A72_P_2,
2283   EVEX_W_0F3A73_P_2,
2284   EVEX_W_0F3ACE_P_2,
2285   EVEX_W_0F3ACF_P_2
2286 };
2287
2288 typedef void (*op_rtn) (int bytemode, int sizeflag);
2289
2290 struct dis386 {
2291   const char *name;
2292   struct
2293     {
2294       op_rtn rtn;
2295       int bytemode;
2296     } op[MAX_OPERANDS];
2297   unsigned int prefix_requirement;
2298 };
2299
2300 /* Upper case letters in the instruction names here are macros.
2301    'A' => print 'b' if no register operands or suffix_always is true
2302    'B' => print 'b' if suffix_always is true
2303    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2304           size prefix
2305    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2306           suffix_always is true
2307    'E' => print 'e' if 32-bit form of jcxz
2308    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2309    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2310    'H' => print ",pt" or ",pn" branch hint
2311    'I' => honor following macro letter even in Intel mode (implemented only
2312           for some of the macro letters)
2313    'J' => print 'l'
2314    'K' => print 'd' or 'q' if rex prefix is present.
2315    'L' => print 'l' if suffix_always is true
2316    'M' => print 'r' if intel_mnemonic is false.
2317    'N' => print 'n' if instruction has no wait "prefix"
2318    'O' => print 'd' or 'o' (or 'q' in Intel mode)
2319    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2320           or suffix_always is true.  print 'q' if rex prefix is present.
2321    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2322           is true
2323    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2324    'S' => print 'w', 'l' or 'q' if suffix_always is true
2325    'T' => print 'q' in 64bit mode if instruction has no operand size
2326           prefix and behave as 'P' otherwise
2327    'U' => print 'q' in 64bit mode if instruction has no operand size
2328           prefix and behave as 'Q' otherwise
2329    'V' => print 'q' in 64bit mode if instruction has no operand size
2330           prefix and behave as 'S' otherwise
2331    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2332    'X' => print 's', 'd' depending on data16 prefix (for XMM)
2333    'Y' unused.
2334    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2335    '!' => change condition from true to false or from false to true.
2336    '%' => add 1 upper case letter to the macro.
2337    '^' => print 'w' or 'l' depending on operand size prefix or
2338           suffix_always is true (lcall/ljmp).
2339    '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2340           on operand size prefix.
2341    '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2342           has no operand size prefix for AMD64 ISA, behave as 'P'
2343           otherwise
2344
2345    2 upper case letter macros:
2346    "XY" => print 'x' or 'y' if suffix_always is true or no register
2347            operands and no broadcast.
2348    "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2349            register operands and no broadcast.
2350    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2351    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2352            or suffix_always is true
2353    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2354    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2355    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2356    "LW" => print 'd', 'q' depending on the VEX.W bit
2357    "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2358            an operand size prefix, or suffix_always is true.  print
2359            'q' if rex prefix is present.
2360
2361    Many of the above letters print nothing in Intel mode.  See "putop"
2362    for the details.
2363
2364    Braces '{' and '}', and vertical bars '|', indicate alternative
2365    mnemonic strings for AT&T and Intel.  */
2366
2367 static const struct dis386 dis386[] = {
2368   /* 00 */
2369   { "addB",             { Ebh1, Gb }, 0 },
2370   { "addS",             { Evh1, Gv }, 0 },
2371   { "addB",             { Gb, EbS }, 0 },
2372   { "addS",             { Gv, EvS }, 0 },
2373   { "addB",             { AL, Ib }, 0 },
2374   { "addS",             { eAX, Iv }, 0 },
2375   { X86_64_TABLE (X86_64_06) },
2376   { X86_64_TABLE (X86_64_07) },
2377   /* 08 */
2378   { "orB",              { Ebh1, Gb }, 0 },
2379   { "orS",              { Evh1, Gv }, 0 },
2380   { "orB",              { Gb, EbS }, 0 },
2381   { "orS",              { Gv, EvS }, 0 },
2382   { "orB",              { AL, Ib }, 0 },
2383   { "orS",              { eAX, Iv }, 0 },
2384   { X86_64_TABLE (X86_64_0D) },
2385   { Bad_Opcode },       /* 0x0f extended opcode escape */
2386   /* 10 */
2387   { "adcB",             { Ebh1, Gb }, 0 },
2388   { "adcS",             { Evh1, Gv }, 0 },
2389   { "adcB",             { Gb, EbS }, 0 },
2390   { "adcS",             { Gv, EvS }, 0 },
2391   { "adcB",             { AL, Ib }, 0 },
2392   { "adcS",             { eAX, Iv }, 0 },
2393   { X86_64_TABLE (X86_64_16) },
2394   { X86_64_TABLE (X86_64_17) },
2395   /* 18 */
2396   { "sbbB",             { Ebh1, Gb }, 0 },
2397   { "sbbS",             { Evh1, Gv }, 0 },
2398   { "sbbB",             { Gb, EbS }, 0 },
2399   { "sbbS",             { Gv, EvS }, 0 },
2400   { "sbbB",             { AL, Ib }, 0 },
2401   { "sbbS",             { eAX, Iv }, 0 },
2402   { X86_64_TABLE (X86_64_1E) },
2403   { X86_64_TABLE (X86_64_1F) },
2404   /* 20 */
2405   { "andB",             { Ebh1, Gb }, 0 },
2406   { "andS",             { Evh1, Gv }, 0 },
2407   { "andB",             { Gb, EbS }, 0 },
2408   { "andS",             { Gv, EvS }, 0 },
2409   { "andB",             { AL, Ib }, 0 },
2410   { "andS",             { eAX, Iv }, 0 },
2411   { Bad_Opcode },       /* SEG ES prefix */
2412   { X86_64_TABLE (X86_64_27) },
2413   /* 28 */
2414   { "subB",             { Ebh1, Gb }, 0 },
2415   { "subS",             { Evh1, Gv }, 0 },
2416   { "subB",             { Gb, EbS }, 0 },
2417   { "subS",             { Gv, EvS }, 0 },
2418   { "subB",             { AL, Ib }, 0 },
2419   { "subS",             { eAX, Iv }, 0 },
2420   { Bad_Opcode },       /* SEG CS prefix */
2421   { X86_64_TABLE (X86_64_2F) },
2422   /* 30 */
2423   { "xorB",             { Ebh1, Gb }, 0 },
2424   { "xorS",             { Evh1, Gv }, 0 },
2425   { "xorB",             { Gb, EbS }, 0 },
2426   { "xorS",             { Gv, EvS }, 0 },
2427   { "xorB",             { AL, Ib }, 0 },
2428   { "xorS",             { eAX, Iv }, 0 },
2429   { Bad_Opcode },       /* SEG SS prefix */
2430   { X86_64_TABLE (X86_64_37) },
2431   /* 38 */
2432   { "cmpB",             { Eb, Gb }, 0 },
2433   { "cmpS",             { Ev, Gv }, 0 },
2434   { "cmpB",             { Gb, EbS }, 0 },
2435   { "cmpS",             { Gv, EvS }, 0 },
2436   { "cmpB",             { AL, Ib }, 0 },
2437   { "cmpS",             { eAX, Iv }, 0 },
2438   { Bad_Opcode },       /* SEG DS prefix */
2439   { X86_64_TABLE (X86_64_3F) },
2440   /* 40 */
2441   { "inc{S|}",          { RMeAX }, 0 },
2442   { "inc{S|}",          { RMeCX }, 0 },
2443   { "inc{S|}",          { RMeDX }, 0 },
2444   { "inc{S|}",          { RMeBX }, 0 },
2445   { "inc{S|}",          { RMeSP }, 0 },
2446   { "inc{S|}",          { RMeBP }, 0 },
2447   { "inc{S|}",          { RMeSI }, 0 },
2448   { "inc{S|}",          { RMeDI }, 0 },
2449   /* 48 */
2450   { "dec{S|}",          { RMeAX }, 0 },
2451   { "dec{S|}",          { RMeCX }, 0 },
2452   { "dec{S|}",          { RMeDX }, 0 },
2453   { "dec{S|}",          { RMeBX }, 0 },
2454   { "dec{S|}",          { RMeSP }, 0 },
2455   { "dec{S|}",          { RMeBP }, 0 },
2456   { "dec{S|}",          { RMeSI }, 0 },
2457   { "dec{S|}",          { RMeDI }, 0 },
2458   /* 50 */
2459   { "pushV",            { RMrAX }, 0 },
2460   { "pushV",            { RMrCX }, 0 },
2461   { "pushV",            { RMrDX }, 0 },
2462   { "pushV",            { RMrBX }, 0 },
2463   { "pushV",            { RMrSP }, 0 },
2464   { "pushV",            { RMrBP }, 0 },
2465   { "pushV",            { RMrSI }, 0 },
2466   { "pushV",            { RMrDI }, 0 },
2467   /* 58 */
2468   { "popV",             { RMrAX }, 0 },
2469   { "popV",             { RMrCX }, 0 },
2470   { "popV",             { RMrDX }, 0 },
2471   { "popV",             { RMrBX }, 0 },
2472   { "popV",             { RMrSP }, 0 },
2473   { "popV",             { RMrBP }, 0 },
2474   { "popV",             { RMrSI }, 0 },
2475   { "popV",             { RMrDI }, 0 },
2476   /* 60 */
2477   { X86_64_TABLE (X86_64_60) },
2478   { X86_64_TABLE (X86_64_61) },
2479   { X86_64_TABLE (X86_64_62) },
2480   { X86_64_TABLE (X86_64_63) },
2481   { Bad_Opcode },       /* seg fs */
2482   { Bad_Opcode },       /* seg gs */
2483   { Bad_Opcode },       /* op size prefix */
2484   { Bad_Opcode },       /* adr size prefix */
2485   /* 68 */
2486   { "pushT",            { sIv }, 0 },
2487   { "imulS",            { Gv, Ev, Iv }, 0 },
2488   { "pushT",            { sIbT }, 0 },
2489   { "imulS",            { Gv, Ev, sIb }, 0 },
2490   { "ins{b|}",          { Ybr, indirDX }, 0 },
2491   { X86_64_TABLE (X86_64_6D) },
2492   { "outs{b|}",         { indirDXr, Xb }, 0 },
2493   { X86_64_TABLE (X86_64_6F) },
2494   /* 70 */
2495   { "joH",              { Jb, BND, cond_jump_flag }, 0 },
2496   { "jnoH",             { Jb, BND, cond_jump_flag }, 0 },
2497   { "jbH",              { Jb, BND, cond_jump_flag }, 0 },
2498   { "jaeH",             { Jb, BND, cond_jump_flag }, 0 },
2499   { "jeH",              { Jb, BND, cond_jump_flag }, 0 },
2500   { "jneH",             { Jb, BND, cond_jump_flag }, 0 },
2501   { "jbeH",             { Jb, BND, cond_jump_flag }, 0 },
2502   { "jaH",              { Jb, BND, cond_jump_flag }, 0 },
2503   /* 78 */
2504   { "jsH",              { Jb, BND, cond_jump_flag }, 0 },
2505   { "jnsH",             { Jb, BND, cond_jump_flag }, 0 },
2506   { "jpH",              { Jb, BND, cond_jump_flag }, 0 },
2507   { "jnpH",             { Jb, BND, cond_jump_flag }, 0 },
2508   { "jlH",              { Jb, BND, cond_jump_flag }, 0 },
2509   { "jgeH",             { Jb, BND, cond_jump_flag }, 0 },
2510   { "jleH",             { Jb, BND, cond_jump_flag }, 0 },
2511   { "jgH",              { Jb, BND, cond_jump_flag }, 0 },
2512   /* 80 */
2513   { REG_TABLE (REG_80) },
2514   { REG_TABLE (REG_81) },
2515   { X86_64_TABLE (X86_64_82) },
2516   { REG_TABLE (REG_83) },
2517   { "testB",            { Eb, Gb }, 0 },
2518   { "testS",            { Ev, Gv }, 0 },
2519   { "xchgB",            { Ebh2, Gb }, 0 },
2520   { "xchgS",            { Evh2, Gv }, 0 },
2521   /* 88 */
2522   { "movB",             { Ebh3, Gb }, 0 },
2523   { "movS",             { Evh3, Gv }, 0 },
2524   { "movB",             { Gb, EbS }, 0 },
2525   { "movS",             { Gv, EvS }, 0 },
2526   { "movD",             { Sv, Sw }, 0 },
2527   { MOD_TABLE (MOD_8D) },
2528   { "movD",             { Sw, Sv }, 0 },
2529   { REG_TABLE (REG_8F) },
2530   /* 90 */
2531   { PREFIX_TABLE (PREFIX_90) },
2532   { "xchgS",            { RMeCX, eAX }, 0 },
2533   { "xchgS",            { RMeDX, eAX }, 0 },
2534   { "xchgS",            { RMeBX, eAX }, 0 },
2535   { "xchgS",            { RMeSP, eAX }, 0 },
2536   { "xchgS",            { RMeBP, eAX }, 0 },
2537   { "xchgS",            { RMeSI, eAX }, 0 },
2538   { "xchgS",            { RMeDI, eAX }, 0 },
2539   /* 98 */
2540   { "cW{t|}R",          { XX }, 0 },
2541   { "cR{t|}O",          { XX }, 0 },
2542   { X86_64_TABLE (X86_64_9A) },
2543   { Bad_Opcode },       /* fwait */
2544   { "pushfT",           { XX }, 0 },
2545   { "popfT",            { XX }, 0 },
2546   { "sahf",             { XX }, 0 },
2547   { "lahf",             { XX }, 0 },
2548   /* a0 */
2549   { "mov%LB",           { AL, Ob }, 0 },
2550   { "mov%LS",           { eAX, Ov }, 0 },
2551   { "mov%LB",           { Ob, AL }, 0 },
2552   { "mov%LS",           { Ov, eAX }, 0 },
2553   { "movs{b|}",         { Ybr, Xb }, 0 },
2554   { "movs{R|}",         { Yvr, Xv }, 0 },
2555   { "cmps{b|}",         { Xb, Yb }, 0 },
2556   { "cmps{R|}",         { Xv, Yv }, 0 },
2557   /* a8 */
2558   { "testB",            { AL, Ib }, 0 },
2559   { "testS",            { eAX, Iv }, 0 },
2560   { "stosB",            { Ybr, AL }, 0 },
2561   { "stosS",            { Yvr, eAX }, 0 },
2562   { "lodsB",            { ALr, Xb }, 0 },
2563   { "lodsS",            { eAXr, Xv }, 0 },
2564   { "scasB",            { AL, Yb }, 0 },
2565   { "scasS",            { eAX, Yv }, 0 },
2566   /* b0 */
2567   { "movB",             { RMAL, Ib }, 0 },
2568   { "movB",             { RMCL, Ib }, 0 },
2569   { "movB",             { RMDL, Ib }, 0 },
2570   { "movB",             { RMBL, Ib }, 0 },
2571   { "movB",             { RMAH, Ib }, 0 },
2572   { "movB",             { RMCH, Ib }, 0 },
2573   { "movB",             { RMDH, Ib }, 0 },
2574   { "movB",             { RMBH, Ib }, 0 },
2575   /* b8 */
2576   { "mov%LV",           { RMeAX, Iv64 }, 0 },
2577   { "mov%LV",           { RMeCX, Iv64 }, 0 },
2578   { "mov%LV",           { RMeDX, Iv64 }, 0 },
2579   { "mov%LV",           { RMeBX, Iv64 }, 0 },
2580   { "mov%LV",           { RMeSP, Iv64 }, 0 },
2581   { "mov%LV",           { RMeBP, Iv64 }, 0 },
2582   { "mov%LV",           { RMeSI, Iv64 }, 0 },
2583   { "mov%LV",           { RMeDI, Iv64 }, 0 },
2584   /* c0 */
2585   { REG_TABLE (REG_C0) },
2586   { REG_TABLE (REG_C1) },
2587   { "retT",             { Iw, BND }, 0 },
2588   { "retT",             { BND }, 0 },
2589   { X86_64_TABLE (X86_64_C4) },
2590   { X86_64_TABLE (X86_64_C5) },
2591   { REG_TABLE (REG_C6) },
2592   { REG_TABLE (REG_C7) },
2593   /* c8 */
2594   { "enterT",           { Iw, Ib }, 0 },
2595   { "leaveT",           { XX }, 0 },
2596   { "Jret{|f}P",        { Iw }, 0 },
2597   { "Jret{|f}P",        { XX }, 0 },
2598   { "int3",             { XX }, 0 },
2599   { "int",              { Ib }, 0 },
2600   { X86_64_TABLE (X86_64_CE) },
2601   { "iret%LP",          { XX }, 0 },
2602   /* d0 */
2603   { REG_TABLE (REG_D0) },
2604   { REG_TABLE (REG_D1) },
2605   { REG_TABLE (REG_D2) },
2606   { REG_TABLE (REG_D3) },
2607   { X86_64_TABLE (X86_64_D4) },
2608   { X86_64_TABLE (X86_64_D5) },
2609   { Bad_Opcode },
2610   { "xlat",             { DSBX }, 0 },
2611   /* d8 */
2612   { FLOAT },
2613   { FLOAT },
2614   { FLOAT },
2615   { FLOAT },
2616   { FLOAT },
2617   { FLOAT },
2618   { FLOAT },
2619   { FLOAT },
2620   /* e0 */
2621   { "loopneFH",         { Jb, XX, loop_jcxz_flag }, 0 },
2622   { "loopeFH",          { Jb, XX, loop_jcxz_flag }, 0 },
2623   { "loopFH",           { Jb, XX, loop_jcxz_flag }, 0 },
2624   { "jEcxzH",           { Jb, XX, loop_jcxz_flag }, 0 },
2625   { "inB",              { AL, Ib }, 0 },
2626   { "inG",              { zAX, Ib }, 0 },
2627   { "outB",             { Ib, AL }, 0 },
2628   { "outG",             { Ib, zAX }, 0 },
2629   /* e8 */
2630   { X86_64_TABLE (X86_64_E8) },
2631   { X86_64_TABLE (X86_64_E9) },
2632   { X86_64_TABLE (X86_64_EA) },
2633   { "jmp",              { Jb, BND }, 0 },
2634   { "inB",              { AL, indirDX }, 0 },
2635   { "inG",              { zAX, indirDX }, 0 },
2636   { "outB",             { indirDX, AL }, 0 },
2637   { "outG",             { indirDX, zAX }, 0 },
2638   /* f0 */
2639   { Bad_Opcode },       /* lock prefix */
2640   { "icebp",            { XX }, 0 },
2641   { Bad_Opcode },       /* repne */
2642   { Bad_Opcode },       /* repz */
2643   { "hlt",              { XX }, 0 },
2644   { "cmc",              { XX }, 0 },
2645   { REG_TABLE (REG_F6) },
2646   { REG_TABLE (REG_F7) },
2647   /* f8 */
2648   { "clc",              { XX }, 0 },
2649   { "stc",              { XX }, 0 },
2650   { "cli",              { XX }, 0 },
2651   { "sti",              { XX }, 0 },
2652   { "cld",              { XX }, 0 },
2653   { "std",              { XX }, 0 },
2654   { REG_TABLE (REG_FE) },
2655   { REG_TABLE (REG_FF) },
2656 };
2657
2658 static const struct dis386 dis386_twobyte[] = {
2659   /* 00 */
2660   { REG_TABLE (REG_0F00 ) },
2661   { REG_TABLE (REG_0F01 ) },
2662   { "larS",             { Gv, Ew }, 0 },
2663   { "lslS",             { Gv, Ew }, 0 },
2664   { Bad_Opcode },
2665   { "syscall",          { XX }, 0 },
2666   { "clts",             { XX }, 0 },
2667   { "sysret%LP",                { XX }, 0 },
2668   /* 08 */
2669   { "invd",             { XX }, 0 },
2670   { PREFIX_TABLE (PREFIX_0F09) },
2671   { Bad_Opcode },
2672   { "ud2",              { XX }, 0 },
2673   { Bad_Opcode },
2674   { REG_TABLE (REG_0F0D) },
2675   { "femms",            { XX }, 0 },
2676   { "",                 { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix.  */
2677   /* 10 */
2678   { PREFIX_TABLE (PREFIX_0F10) },
2679   { PREFIX_TABLE (PREFIX_0F11) },
2680   { PREFIX_TABLE (PREFIX_0F12) },
2681   { MOD_TABLE (MOD_0F13) },
2682   { "unpcklpX",         { XM, EXx }, PREFIX_OPCODE },
2683   { "unpckhpX",         { XM, EXx }, PREFIX_OPCODE },
2684   { PREFIX_TABLE (PREFIX_0F16) },
2685   { MOD_TABLE (MOD_0F17) },
2686   /* 18 */
2687   { REG_TABLE (REG_0F18) },
2688   { "nopQ",             { Ev }, 0 },
2689   { PREFIX_TABLE (PREFIX_0F1A) },
2690   { PREFIX_TABLE (PREFIX_0F1B) },
2691   { PREFIX_TABLE (PREFIX_0F1C) },
2692   { "nopQ",             { Ev }, 0 },
2693   { PREFIX_TABLE (PREFIX_0F1E) },
2694   { "nopQ",             { Ev }, 0 },
2695   /* 20 */
2696   { "movZ",             { Rm, Cm }, 0 },
2697   { "movZ",             { Rm, Dm }, 0 },
2698   { "movZ",             { Cm, Rm }, 0 },
2699   { "movZ",             { Dm, Rm }, 0 },
2700   { MOD_TABLE (MOD_0F24) },
2701   { Bad_Opcode },
2702   { MOD_TABLE (MOD_0F26) },
2703   { Bad_Opcode },
2704   /* 28 */
2705   { "movapX",           { XM, EXx }, PREFIX_OPCODE },
2706   { "movapX",           { EXxS, XM }, PREFIX_OPCODE },
2707   { PREFIX_TABLE (PREFIX_0F2A) },
2708   { PREFIX_TABLE (PREFIX_0F2B) },
2709   { PREFIX_TABLE (PREFIX_0F2C) },
2710   { PREFIX_TABLE (PREFIX_0F2D) },
2711   { PREFIX_TABLE (PREFIX_0F2E) },
2712   { PREFIX_TABLE (PREFIX_0F2F) },
2713   /* 30 */
2714   { "wrmsr",            { XX }, 0 },
2715   { "rdtsc",            { XX }, 0 },
2716   { "rdmsr",            { XX }, 0 },
2717   { "rdpmc",            { XX }, 0 },
2718   { "sysenter",         { SEP }, 0 },
2719   { "sysexit",          { SEP }, 0 },
2720   { Bad_Opcode },
2721   { "getsec",           { XX }, 0 },
2722   /* 38 */
2723   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2724   { Bad_Opcode },
2725   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2726   { Bad_Opcode },
2727   { Bad_Opcode },
2728   { Bad_Opcode },
2729   { Bad_Opcode },
2730   { Bad_Opcode },
2731   /* 40 */
2732   { "cmovoS",           { Gv, Ev }, 0 },
2733   { "cmovnoS",          { Gv, Ev }, 0 },
2734   { "cmovbS",           { Gv, Ev }, 0 },
2735   { "cmovaeS",          { Gv, Ev }, 0 },
2736   { "cmoveS",           { Gv, Ev }, 0 },
2737   { "cmovneS",          { Gv, Ev }, 0 },
2738   { "cmovbeS",          { Gv, Ev }, 0 },
2739   { "cmovaS",           { Gv, Ev }, 0 },
2740   /* 48 */
2741   { "cmovsS",           { Gv, Ev }, 0 },
2742   { "cmovnsS",          { Gv, Ev }, 0 },
2743   { "cmovpS",           { Gv, Ev }, 0 },
2744   { "cmovnpS",          { Gv, Ev }, 0 },
2745   { "cmovlS",           { Gv, Ev }, 0 },
2746   { "cmovgeS",          { Gv, Ev }, 0 },
2747   { "cmovleS",          { Gv, Ev }, 0 },
2748   { "cmovgS",           { Gv, Ev }, 0 },
2749   /* 50 */
2750   { MOD_TABLE (MOD_0F51) },
2751   { PREFIX_TABLE (PREFIX_0F51) },
2752   { PREFIX_TABLE (PREFIX_0F52) },
2753   { PREFIX_TABLE (PREFIX_0F53) },
2754   { "andpX",            { XM, EXx }, PREFIX_OPCODE },
2755   { "andnpX",           { XM, EXx }, PREFIX_OPCODE },
2756   { "orpX",             { XM, EXx }, PREFIX_OPCODE },
2757   { "xorpX",            { XM, EXx }, PREFIX_OPCODE },
2758   /* 58 */
2759   { PREFIX_TABLE (PREFIX_0F58) },
2760   { PREFIX_TABLE (PREFIX_0F59) },
2761   { PREFIX_TABLE (PREFIX_0F5A) },
2762   { PREFIX_TABLE (PREFIX_0F5B) },
2763   { PREFIX_TABLE (PREFIX_0F5C) },
2764   { PREFIX_TABLE (PREFIX_0F5D) },
2765   { PREFIX_TABLE (PREFIX_0F5E) },
2766   { PREFIX_TABLE (PREFIX_0F5F) },
2767   /* 60 */
2768   { PREFIX_TABLE (PREFIX_0F60) },
2769   { PREFIX_TABLE (PREFIX_0F61) },
2770   { PREFIX_TABLE (PREFIX_0F62) },
2771   { "packsswb",         { MX, EM }, PREFIX_OPCODE },
2772   { "pcmpgtb",          { MX, EM }, PREFIX_OPCODE },
2773   { "pcmpgtw",          { MX, EM }, PREFIX_OPCODE },
2774   { "pcmpgtd",          { MX, EM }, PREFIX_OPCODE },
2775   { "packuswb",         { MX, EM }, PREFIX_OPCODE },
2776   /* 68 */
2777   { "punpckhbw",        { MX, EM }, PREFIX_OPCODE },
2778   { "punpckhwd",        { MX, EM }, PREFIX_OPCODE },
2779   { "punpckhdq",        { MX, EM }, PREFIX_OPCODE },
2780   { "packssdw",         { MX, EM }, PREFIX_OPCODE },
2781   { PREFIX_TABLE (PREFIX_0F6C) },
2782   { PREFIX_TABLE (PREFIX_0F6D) },
2783   { "movK",             { MX, Edq }, PREFIX_OPCODE },
2784   { PREFIX_TABLE (PREFIX_0F6F) },
2785   /* 70 */
2786   { PREFIX_TABLE (PREFIX_0F70) },
2787   { REG_TABLE (REG_0F71) },
2788   { REG_TABLE (REG_0F72) },
2789   { REG_TABLE (REG_0F73) },
2790   { "pcmpeqb",          { MX, EM }, PREFIX_OPCODE },
2791   { "pcmpeqw",          { MX, EM }, PREFIX_OPCODE },
2792   { "pcmpeqd",          { MX, EM }, PREFIX_OPCODE },
2793   { "emms",             { XX }, PREFIX_OPCODE },
2794   /* 78 */
2795   { PREFIX_TABLE (PREFIX_0F78) },
2796   { PREFIX_TABLE (PREFIX_0F79) },
2797   { Bad_Opcode },
2798   { Bad_Opcode },
2799   { PREFIX_TABLE (PREFIX_0F7C) },
2800   { PREFIX_TABLE (PREFIX_0F7D) },
2801   { PREFIX_TABLE (PREFIX_0F7E) },
2802   { PREFIX_TABLE (PREFIX_0F7F) },
2803   /* 80 */
2804   { "joH",              { Jv, BND, cond_jump_flag }, 0 },
2805   { "jnoH",             { Jv, BND, cond_jump_flag }, 0 },
2806   { "jbH",              { Jv, BND, cond_jump_flag }, 0 },
2807   { "jaeH",             { Jv, BND, cond_jump_flag }, 0 },
2808   { "jeH",              { Jv, BND, cond_jump_flag }, 0 },
2809   { "jneH",             { Jv, BND, cond_jump_flag }, 0 },
2810   { "jbeH",             { Jv, BND, cond_jump_flag }, 0 },
2811   { "jaH",              { Jv, BND, cond_jump_flag }, 0 },
2812   /* 88 */
2813   { "jsH",              { Jv, BND, cond_jump_flag }, 0 },
2814   { "jnsH",             { Jv, BND, cond_jump_flag }, 0 },
2815   { "jpH",              { Jv, BND, cond_jump_flag }, 0 },
2816   { "jnpH",             { Jv, BND, cond_jump_flag }, 0 },
2817   { "jlH",              { Jv, BND, cond_jump_flag }, 0 },
2818   { "jgeH",             { Jv, BND, cond_jump_flag }, 0 },
2819   { "jleH",             { Jv, BND, cond_jump_flag }, 0 },
2820   { "jgH",              { Jv, BND, cond_jump_flag }, 0 },
2821   /* 90 */
2822   { "seto",             { Eb }, 0 },
2823   { "setno",            { Eb }, 0 },
2824   { "setb",             { Eb }, 0 },
2825   { "setae",            { Eb }, 0 },
2826   { "sete",             { Eb }, 0 },
2827   { "setne",            { Eb }, 0 },
2828   { "setbe",            { Eb }, 0 },
2829   { "seta",             { Eb }, 0 },
2830   /* 98 */
2831   { "sets",             { Eb }, 0 },
2832   { "setns",            { Eb }, 0 },
2833   { "setp",             { Eb }, 0 },
2834   { "setnp",            { Eb }, 0 },
2835   { "setl",             { Eb }, 0 },
2836   { "setge",            { Eb }, 0 },
2837   { "setle",            { Eb }, 0 },
2838   { "setg",             { Eb }, 0 },
2839   /* a0 */
2840   { "pushT",            { fs }, 0 },
2841   { "popT",             { fs }, 0 },
2842   { "cpuid",            { XX }, 0 },
2843   { "btS",              { Ev, Gv }, 0 },
2844   { "shldS",            { Ev, Gv, Ib }, 0 },
2845   { "shldS",            { Ev, Gv, CL }, 0 },
2846   { REG_TABLE (REG_0FA6) },
2847   { REG_TABLE (REG_0FA7) },
2848   /* a8 */
2849   { "pushT",            { gs }, 0 },
2850   { "popT",             { gs }, 0 },
2851   { "rsm",              { XX }, 0 },
2852   { "btsS",             { Evh1, Gv }, 0 },
2853   { "shrdS",            { Ev, Gv, Ib }, 0 },
2854   { "shrdS",            { Ev, Gv, CL }, 0 },
2855   { REG_TABLE (REG_0FAE) },
2856   { "imulS",            { Gv, Ev }, 0 },
2857   /* b0 */
2858   { "cmpxchgB",         { Ebh1, Gb }, 0 },
2859   { "cmpxchgS",         { Evh1, Gv }, 0 },
2860   { MOD_TABLE (MOD_0FB2) },
2861   { "btrS",             { Evh1, Gv }, 0 },
2862   { MOD_TABLE (MOD_0FB4) },
2863   { MOD_TABLE (MOD_0FB5) },
2864   { "movz{bR|x}",       { Gv, Eb }, 0 },
2865   { "movz{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
2866   /* b8 */
2867   { PREFIX_TABLE (PREFIX_0FB8) },
2868   { "ud1S",             { Gv, Ev }, 0 },
2869   { REG_TABLE (REG_0FBA) },
2870   { "btcS",             { Evh1, Gv }, 0 },
2871   { PREFIX_TABLE (PREFIX_0FBC) },
2872   { PREFIX_TABLE (PREFIX_0FBD) },
2873   { "movs{bR|x}",       { Gv, Eb }, 0 },
2874   { "movs{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
2875   /* c0 */
2876   { "xaddB",            { Ebh1, Gb }, 0 },
2877   { "xaddS",            { Evh1, Gv }, 0 },
2878   { PREFIX_TABLE (PREFIX_0FC2) },
2879   { MOD_TABLE (MOD_0FC3) },
2880   { "pinsrw",           { MX, Edqw, Ib }, PREFIX_OPCODE },
2881   { "pextrw",           { Gdq, MS, Ib }, PREFIX_OPCODE },
2882   { "shufpX",           { XM, EXx, Ib }, PREFIX_OPCODE },
2883   { REG_TABLE (REG_0FC7) },
2884   /* c8 */
2885   { "bswap",            { RMeAX }, 0 },
2886   { "bswap",            { RMeCX }, 0 },
2887   { "bswap",            { RMeDX }, 0 },
2888   { "bswap",            { RMeBX }, 0 },
2889   { "bswap",            { RMeSP }, 0 },
2890   { "bswap",            { RMeBP }, 0 },
2891   { "bswap",            { RMeSI }, 0 },
2892   { "bswap",            { RMeDI }, 0 },
2893   /* d0 */
2894   { PREFIX_TABLE (PREFIX_0FD0) },
2895   { "psrlw",            { MX, EM }, PREFIX_OPCODE },
2896   { "psrld",            { MX, EM }, PREFIX_OPCODE },
2897   { "psrlq",            { MX, EM }, PREFIX_OPCODE },
2898   { "paddq",            { MX, EM }, PREFIX_OPCODE },
2899   { "pmullw",           { MX, EM }, PREFIX_OPCODE },
2900   { PREFIX_TABLE (PREFIX_0FD6) },
2901   { MOD_TABLE (MOD_0FD7) },
2902   /* d8 */
2903   { "psubusb",          { MX, EM }, PREFIX_OPCODE },
2904   { "psubusw",          { MX, EM }, PREFIX_OPCODE },
2905   { "pminub",           { MX, EM }, PREFIX_OPCODE },
2906   { "pand",             { MX, EM }, PREFIX_OPCODE },
2907   { "paddusb",          { MX, EM }, PREFIX_OPCODE },
2908   { "paddusw",          { MX, EM }, PREFIX_OPCODE },
2909   { "pmaxub",           { MX, EM }, PREFIX_OPCODE },
2910   { "pandn",            { MX, EM }, PREFIX_OPCODE },
2911   /* e0 */
2912   { "pavgb",            { MX, EM }, PREFIX_OPCODE },
2913   { "psraw",            { MX, EM }, PREFIX_OPCODE },
2914   { "psrad",            { MX, EM }, PREFIX_OPCODE },
2915   { "pavgw",            { MX, EM }, PREFIX_OPCODE },
2916   { "pmulhuw",          { MX, EM }, PREFIX_OPCODE },
2917   { "pmulhw",           { MX, EM }, PREFIX_OPCODE },
2918   { PREFIX_TABLE (PREFIX_0FE6) },
2919   { PREFIX_TABLE (PREFIX_0FE7) },
2920   /* e8 */
2921   { "psubsb",           { MX, EM }, PREFIX_OPCODE },
2922   { "psubsw",           { MX, EM }, PREFIX_OPCODE },
2923   { "pminsw",           { MX, EM }, PREFIX_OPCODE },
2924   { "por",              { MX, EM }, PREFIX_OPCODE },
2925   { "paddsb",           { MX, EM }, PREFIX_OPCODE },
2926   { "paddsw",           { MX, EM }, PREFIX_OPCODE },
2927   { "pmaxsw",           { MX, EM }, PREFIX_OPCODE },
2928   { "pxor",             { MX, EM }, PREFIX_OPCODE },
2929   /* f0 */
2930   { PREFIX_TABLE (PREFIX_0FF0) },
2931   { "psllw",            { MX, EM }, PREFIX_OPCODE },
2932   { "pslld",            { MX, EM }, PREFIX_OPCODE },
2933   { "psllq",            { MX, EM }, PREFIX_OPCODE },
2934   { "pmuludq",          { MX, EM }, PREFIX_OPCODE },
2935   { "pmaddwd",          { MX, EM }, PREFIX_OPCODE },
2936   { "psadbw",           { MX, EM }, PREFIX_OPCODE },
2937   { PREFIX_TABLE (PREFIX_0FF7) },
2938   /* f8 */
2939   { "psubb",            { MX, EM }, PREFIX_OPCODE },
2940   { "psubw",            { MX, EM }, PREFIX_OPCODE },
2941   { "psubd",            { MX, EM }, PREFIX_OPCODE },
2942   { "psubq",            { MX, EM }, PREFIX_OPCODE },
2943   { "paddb",            { MX, EM }, PREFIX_OPCODE },
2944   { "paddw",            { MX, EM }, PREFIX_OPCODE },
2945   { "paddd",            { MX, EM }, PREFIX_OPCODE },
2946   { "ud0S",             { Gv, Ev }, 0 },
2947 };
2948
2949 static const unsigned char onebyte_has_modrm[256] = {
2950   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2951   /*       -------------------------------        */
2952   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2953   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2954   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2955   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2956   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2957   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2958   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2959   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2960   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2961   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2962   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2963   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2964   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2965   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2966   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2967   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
2968   /*       -------------------------------        */
2969   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2970 };
2971
2972 static const unsigned char twobyte_has_modrm[256] = {
2973   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2974   /*       -------------------------------        */
2975   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2976   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2977   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2978   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2979   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2980   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2981   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2982   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2983   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2984   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2985   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2986   /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2987   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2988   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2989   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2990   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1  /* ff */
2991   /*       -------------------------------        */
2992   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2993 };
2994
2995 static char obuf[100];
2996 static char *obufp;
2997 static char *mnemonicendp;
2998 static char scratchbuf[100];
2999 static unsigned char *start_codep;
3000 static unsigned char *insn_codep;
3001 static unsigned char *codep;
3002 static unsigned char *end_codep;
3003 static int last_lock_prefix;
3004 static int last_repz_prefix;
3005 static int last_repnz_prefix;
3006 static int last_data_prefix;
3007 static int last_addr_prefix;
3008 static int last_rex_prefix;
3009 static int last_seg_prefix;
3010 static int fwait_prefix;
3011 /* The active segment register prefix.  */
3012 static int active_seg_prefix;
3013 #define MAX_CODE_LENGTH 15
3014 /* We can up to 14 prefixes since the maximum instruction length is
3015    15bytes.  */
3016 static int all_prefixes[MAX_CODE_LENGTH - 1];
3017 static disassemble_info *the_info;
3018 static struct
3019   {
3020     int mod;
3021     int reg;
3022     int rm;
3023   }
3024 modrm;
3025 static unsigned char need_modrm;
3026 static struct
3027   {
3028     int scale;
3029     int index;
3030     int base;
3031   }
3032 sib;
3033 static struct
3034   {
3035     int register_specifier;
3036     int length;
3037     int prefix;
3038     int w;
3039     int evex;
3040     int r;
3041     int v;
3042     int mask_register_specifier;
3043     int zeroing;
3044     int ll;
3045     int b;
3046   }
3047 vex;
3048 static unsigned char need_vex;
3049 static unsigned char need_vex_reg;
3050 static unsigned char vex_w_done;
3051
3052 struct op
3053   {
3054     const char *name;
3055     unsigned int len;
3056   };
3057
3058 /* If we are accessing mod/rm/reg without need_modrm set, then the
3059    values are stale.  Hitting this abort likely indicates that you
3060    need to update onebyte_has_modrm or twobyte_has_modrm.  */
3061 #define MODRM_CHECK  if (!need_modrm) abort ()
3062
3063 static const char **names64;
3064 static const char **names32;
3065 static const char **names16;
3066 static const char **names8;
3067 static const char **names8rex;
3068 static const char **names_seg;
3069 static const char *index64;
3070 static const char *index32;
3071 static const char **index16;
3072 static const char **names_bnd;
3073
3074 static const char *intel_names64[] = {
3075   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3076   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3077 };
3078 static const char *intel_names32[] = {
3079   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3080   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3081 };
3082 static const char *intel_names16[] = {
3083   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3084   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3085 };
3086 static const char *intel_names8[] = {
3087   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3088 };
3089 static const char *intel_names8rex[] = {
3090   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3091   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3092 };
3093 static const char *intel_names_seg[] = {
3094   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3095 };
3096 static const char *intel_index64 = "riz";
3097 static const char *intel_index32 = "eiz";
3098 static const char *intel_index16[] = {
3099   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3100 };
3101
3102 static const char *att_names64[] = {
3103   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3104   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3105 };
3106 static const char *att_names32[] = {
3107   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3108   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3109 };
3110 static const char *att_names16[] = {
3111   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3112   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3113 };
3114 static const char *att_names8[] = {
3115   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3116 };
3117 static const char *att_names8rex[] = {
3118   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3119   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3120 };
3121 static const char *att_names_seg[] = {
3122   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3123 };
3124 static const char *att_index64 = "%riz";
3125 static const char *att_index32 = "%eiz";
3126 static const char *att_index16[] = {
3127   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3128 };
3129
3130 static const char **names_mm;
3131 static const char *intel_names_mm[] = {
3132   "mm0", "mm1", "mm2", "mm3",
3133   "mm4", "mm5", "mm6", "mm7"
3134 };
3135 static const char *att_names_mm[] = {
3136   "%mm0", "%mm1", "%mm2", "%mm3",
3137   "%mm4", "%mm5", "%mm6", "%mm7"
3138 };
3139
3140 static const char *intel_names_bnd[] = {
3141   "bnd0", "bnd1", "bnd2", "bnd3"
3142 };
3143
3144 static const char *att_names_bnd[] = {
3145   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3146 };
3147
3148 static const char **names_xmm;
3149 static const char *intel_names_xmm[] = {
3150   "xmm0", "xmm1", "xmm2", "xmm3",
3151   "xmm4", "xmm5", "xmm6", "xmm7",
3152   "xmm8", "xmm9", "xmm10", "xmm11",
3153   "xmm12", "xmm13", "xmm14", "xmm15",
3154   "xmm16", "xmm17", "xmm18", "xmm19",
3155   "xmm20", "xmm21", "xmm22", "xmm23",
3156   "xmm24", "xmm25", "xmm26", "xmm27",
3157   "xmm28", "xmm29", "xmm30", "xmm31"
3158 };
3159 static const char *att_names_xmm[] = {
3160   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3161   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3162   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3163   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3164   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3165   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3166   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3167   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3168 };
3169
3170 static const char **names_ymm;
3171 static const char *intel_names_ymm[] = {
3172   "ymm0", "ymm1", "ymm2", "ymm3",
3173   "ymm4", "ymm5", "ymm6", "ymm7",
3174   "ymm8", "ymm9", "ymm10", "ymm11",
3175   "ymm12", "ymm13", "ymm14", "ymm15",
3176   "ymm16", "ymm17", "ymm18", "ymm19",
3177   "ymm20", "ymm21", "ymm22", "ymm23",
3178   "ymm24", "ymm25", "ymm26", "ymm27",
3179   "ymm28", "ymm29", "ymm30", "ymm31"
3180 };
3181 static const char *att_names_ymm[] = {
3182   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3183   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3184   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3185   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3186   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3187   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3188   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3189   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3190 };
3191
3192 static const char **names_zmm;
3193 static const char *intel_names_zmm[] = {
3194   "zmm0", "zmm1", "zmm2", "zmm3",
3195   "zmm4", "zmm5", "zmm6", "zmm7",
3196   "zmm8", "zmm9", "zmm10", "zmm11",
3197   "zmm12", "zmm13", "zmm14", "zmm15",
3198   "zmm16", "zmm17", "zmm18", "zmm19",
3199   "zmm20", "zmm21", "zmm22", "zmm23",
3200   "zmm24", "zmm25", "zmm26", "zmm27",
3201   "zmm28", "zmm29", "zmm30", "zmm31"
3202 };
3203 static const char *att_names_zmm[] = {
3204   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3205   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3206   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3207   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3208   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3209   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3210   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3211   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3212 };
3213
3214 static const char **names_mask;
3215 static const char *intel_names_mask[] = {
3216   "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3217 };
3218 static const char *att_names_mask[] = {
3219   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3220 };
3221
3222 static const char *names_rounding[] =
3223 {
3224   "{rn-sae}",
3225   "{rd-sae}",
3226   "{ru-sae}",
3227   "{rz-sae}"
3228 };
3229
3230 static const struct dis386 reg_table[][8] = {
3231   /* REG_80 */
3232   {
3233     { "addA",   { Ebh1, Ib }, 0 },
3234     { "orA",    { Ebh1, Ib }, 0 },
3235     { "adcA",   { Ebh1, Ib }, 0 },
3236     { "sbbA",   { Ebh1, Ib }, 0 },
3237     { "andA",   { Ebh1, Ib }, 0 },
3238     { "subA",   { Ebh1, Ib }, 0 },
3239     { "xorA",   { Ebh1, Ib }, 0 },
3240     { "cmpA",   { Eb, Ib }, 0 },
3241   },
3242   /* REG_81 */
3243   {
3244     { "addQ",   { Evh1, Iv }, 0 },
3245     { "orQ",    { Evh1, Iv }, 0 },
3246     { "adcQ",   { Evh1, Iv }, 0 },
3247     { "sbbQ",   { Evh1, Iv }, 0 },
3248     { "andQ",   { Evh1, Iv }, 0 },
3249     { "subQ",   { Evh1, Iv }, 0 },
3250     { "xorQ",   { Evh1, Iv }, 0 },
3251     { "cmpQ",   { Ev, Iv }, 0 },
3252   },
3253   /* REG_83 */
3254   {
3255     { "addQ",   { Evh1, sIb }, 0 },
3256     { "orQ",    { Evh1, sIb }, 0 },
3257     { "adcQ",   { Evh1, sIb }, 0 },
3258     { "sbbQ",   { Evh1, sIb }, 0 },
3259     { "andQ",   { Evh1, sIb }, 0 },
3260     { "subQ",   { Evh1, sIb }, 0 },
3261     { "xorQ",   { Evh1, sIb }, 0 },
3262     { "cmpQ",   { Ev, sIb }, 0 },
3263   },
3264   /* REG_8F */
3265   {
3266     { "popU",   { stackEv }, 0 },
3267     { XOP_8F_TABLE (XOP_09) },
3268     { Bad_Opcode },
3269     { Bad_Opcode },
3270     { Bad_Opcode },
3271     { XOP_8F_TABLE (XOP_09) },
3272   },
3273   /* REG_C0 */
3274   {
3275     { "rolA",   { Eb, Ib }, 0 },
3276     { "rorA",   { Eb, Ib }, 0 },
3277     { "rclA",   { Eb, Ib }, 0 },
3278     { "rcrA",   { Eb, Ib }, 0 },
3279     { "shlA",   { Eb, Ib }, 0 },
3280     { "shrA",   { Eb, Ib }, 0 },
3281     { "shlA",   { Eb, Ib }, 0 },
3282     { "sarA",   { Eb, Ib }, 0 },
3283   },
3284   /* REG_C1 */
3285   {
3286     { "rolQ",   { Ev, Ib }, 0 },
3287     { "rorQ",   { Ev, Ib }, 0 },
3288     { "rclQ",   { Ev, Ib }, 0 },
3289     { "rcrQ",   { Ev, Ib }, 0 },
3290     { "shlQ",   { Ev, Ib }, 0 },
3291     { "shrQ",   { Ev, Ib }, 0 },
3292     { "shlQ",   { Ev, Ib }, 0 },
3293     { "sarQ",   { Ev, Ib }, 0 },
3294   },
3295   /* REG_C6 */
3296   {
3297     { "movA",   { Ebh3, Ib }, 0 },
3298     { Bad_Opcode },
3299     { Bad_Opcode },
3300     { Bad_Opcode },
3301     { Bad_Opcode },
3302     { Bad_Opcode },
3303     { Bad_Opcode },
3304     { MOD_TABLE (MOD_C6_REG_7) },
3305   },
3306   /* REG_C7 */
3307   {
3308     { "movQ",   { Evh3, Iv }, 0 },
3309     { Bad_Opcode },
3310     { Bad_Opcode },
3311     { Bad_Opcode },
3312     { Bad_Opcode },
3313     { Bad_Opcode },
3314     { Bad_Opcode },
3315     { MOD_TABLE (MOD_C7_REG_7) },
3316   },
3317   /* REG_D0 */
3318   {
3319     { "rolA",   { Eb, I1 }, 0 },
3320     { "rorA",   { Eb, I1 }, 0 },
3321     { "rclA",   { Eb, I1 }, 0 },
3322     { "rcrA",   { Eb, I1 }, 0 },
3323     { "shlA",   { Eb, I1 }, 0 },
3324     { "shrA",   { Eb, I1 }, 0 },
3325     { "shlA",   { Eb, I1 }, 0 },
3326     { "sarA",   { Eb, I1 }, 0 },
3327   },
3328   /* REG_D1 */
3329   {
3330     { "rolQ",   { Ev, I1 }, 0 },
3331     { "rorQ",   { Ev, I1 }, 0 },
3332     { "rclQ",   { Ev, I1 }, 0 },
3333     { "rcrQ",   { Ev, I1 }, 0 },
3334     { "shlQ",   { Ev, I1 }, 0 },
3335     { "shrQ",   { Ev, I1 }, 0 },
3336     { "shlQ",   { Ev, I1 }, 0 },
3337     { "sarQ",   { Ev, I1 }, 0 },
3338   },
3339   /* REG_D2 */
3340   {
3341     { "rolA",   { Eb, CL }, 0 },
3342     { "rorA",   { Eb, CL }, 0 },
3343     { "rclA",   { Eb, CL }, 0 },
3344     { "rcrA",   { Eb, CL }, 0 },
3345     { "shlA",   { Eb, CL }, 0 },
3346     { "shrA",   { Eb, CL }, 0 },
3347     { "shlA",   { Eb, CL }, 0 },
3348     { "sarA",   { Eb, CL }, 0 },
3349   },
3350   /* REG_D3 */
3351   {
3352     { "rolQ",   { Ev, CL }, 0 },
3353     { "rorQ",   { Ev, CL }, 0 },
3354     { "rclQ",   { Ev, CL }, 0 },
3355     { "rcrQ",   { Ev, CL }, 0 },
3356     { "shlQ",   { Ev, CL }, 0 },
3357     { "shrQ",   { Ev, CL }, 0 },
3358     { "shlQ",   { Ev, CL }, 0 },
3359     { "sarQ",   { Ev, CL }, 0 },
3360   },
3361   /* REG_F6 */
3362   {
3363     { "testA",  { Eb, Ib }, 0 },
3364     { "testA",  { Eb, Ib }, 0 },
3365     { "notA",   { Ebh1 }, 0 },
3366     { "negA",   { Ebh1 }, 0 },
3367     { "mulA",   { Eb }, 0 },    /* Don't print the implicit %al register,  */
3368     { "imulA",  { Eb }, 0 },    /* to distinguish these opcodes from other */
3369     { "divA",   { Eb }, 0 },    /* mul/imul opcodes.  Do the same for div  */
3370     { "idivA",  { Eb }, 0 },    /* and idiv for consistency.               */
3371   },
3372   /* REG_F7 */
3373   {
3374     { "testQ",  { Ev, Iv }, 0 },
3375     { "testQ",  { Ev, Iv }, 0 },
3376     { "notQ",   { Evh1 }, 0 },
3377     { "negQ",   { Evh1 }, 0 },
3378     { "mulQ",   { Ev }, 0 },    /* Don't print the implicit register.  */
3379     { "imulQ",  { Ev }, 0 },
3380     { "divQ",   { Ev }, 0 },
3381     { "idivQ",  { Ev }, 0 },
3382   },
3383   /* REG_FE */
3384   {
3385     { "incA",   { Ebh1 }, 0 },
3386     { "decA",   { Ebh1 }, 0 },
3387   },
3388   /* REG_FF */
3389   {
3390     { "incQ",   { Evh1 }, 0 },
3391     { "decQ",   { Evh1 }, 0 },
3392     { "call{&|}", { NOTRACK, indirEv, BND }, 0 },
3393     { MOD_TABLE (MOD_FF_REG_3) },
3394     { "jmp{&|}", { NOTRACK, indirEv, BND }, 0 },
3395     { MOD_TABLE (MOD_FF_REG_5) },
3396     { "pushU",  { stackEv }, 0 },
3397     { Bad_Opcode },
3398   },
3399   /* REG_0F00 */
3400   {
3401     { "sldtD",  { Sv }, 0 },
3402     { "strD",   { Sv }, 0 },
3403     { "lldt",   { Ew }, 0 },
3404     { "ltr",    { Ew }, 0 },
3405     { "verr",   { Ew }, 0 },
3406     { "verw",   { Ew }, 0 },
3407     { Bad_Opcode },
3408     { Bad_Opcode },
3409   },
3410   /* REG_0F01 */
3411   {
3412     { MOD_TABLE (MOD_0F01_REG_0) },
3413     { MOD_TABLE (MOD_0F01_REG_1) },
3414     { MOD_TABLE (MOD_0F01_REG_2) },
3415     { MOD_TABLE (MOD_0F01_REG_3) },
3416     { "smswD",  { Sv }, 0 },
3417     { MOD_TABLE (MOD_0F01_REG_5) },
3418     { "lmsw",   { Ew }, 0 },
3419     { MOD_TABLE (MOD_0F01_REG_7) },
3420   },
3421   /* REG_0F0D */
3422   {
3423     { "prefetch",       { Mb }, 0 },
3424     { "prefetchw",      { Mb }, 0 },
3425     { "prefetchwt1",    { Mb }, 0 },
3426     { "prefetch",       { Mb }, 0 },
3427     { "prefetch",       { Mb }, 0 },
3428     { "prefetch",       { Mb }, 0 },
3429     { "prefetch",       { Mb }, 0 },
3430     { "prefetch",       { Mb }, 0 },
3431   },
3432   /* REG_0F18 */
3433   {
3434     { MOD_TABLE (MOD_0F18_REG_0) },
3435     { MOD_TABLE (MOD_0F18_REG_1) },
3436     { MOD_TABLE (MOD_0F18_REG_2) },
3437     { MOD_TABLE (MOD_0F18_REG_3) },
3438     { MOD_TABLE (MOD_0F18_REG_4) },
3439     { MOD_TABLE (MOD_0F18_REG_5) },
3440     { MOD_TABLE (MOD_0F18_REG_6) },
3441     { MOD_TABLE (MOD_0F18_REG_7) },
3442   },
3443   /* REG_0F1C_P_0_MOD_0 */
3444   {
3445     { "cldemote",       { Mb }, 0 },
3446     { "nopQ",           { Ev }, 0 },
3447     { "nopQ",           { Ev }, 0 },
3448     { "nopQ",           { Ev }, 0 },
3449     { "nopQ",           { Ev }, 0 },
3450     { "nopQ",           { Ev }, 0 },
3451     { "nopQ",           { Ev }, 0 },
3452     { "nopQ",           { Ev }, 0 },
3453   },
3454   /* REG_0F1E_P_1_MOD_3 */
3455   {
3456     { "nopQ",           { Ev }, 0 },
3457     { "rdsspK",         { Rdq }, PREFIX_OPCODE },
3458     { "nopQ",           { Ev }, 0 },
3459     { "nopQ",           { Ev }, 0 },
3460     { "nopQ",           { Ev }, 0 },
3461     { "nopQ",           { Ev }, 0 },
3462     { "nopQ",           { Ev }, 0 },
3463     { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7) },
3464   },
3465   /* REG_0F71 */
3466   {
3467     { Bad_Opcode },
3468     { Bad_Opcode },
3469     { MOD_TABLE (MOD_0F71_REG_2) },
3470     { Bad_Opcode },
3471     { MOD_TABLE (MOD_0F71_REG_4) },
3472     { Bad_Opcode },
3473     { MOD_TABLE (MOD_0F71_REG_6) },
3474   },
3475   /* REG_0F72 */
3476   {
3477     { Bad_Opcode },
3478     { Bad_Opcode },
3479     { MOD_TABLE (MOD_0F72_REG_2) },
3480     { Bad_Opcode },
3481     { MOD_TABLE (MOD_0F72_REG_4) },
3482     { Bad_Opcode },
3483     { MOD_TABLE (MOD_0F72_REG_6) },
3484   },
3485   /* REG_0F73 */
3486   {
3487     { Bad_Opcode },
3488     { Bad_Opcode },
3489     { MOD_TABLE (MOD_0F73_REG_2) },
3490     { MOD_TABLE (MOD_0F73_REG_3) },
3491     { Bad_Opcode },
3492     { Bad_Opcode },
3493     { MOD_TABLE (MOD_0F73_REG_6) },
3494     { MOD_TABLE (MOD_0F73_REG_7) },
3495   },
3496   /* REG_0FA6 */
3497   {
3498     { "montmul",        { { OP_0f07, 0 } }, 0 },
3499     { "xsha1",          { { OP_0f07, 0 } }, 0 },
3500     { "xsha256",        { { OP_0f07, 0 } }, 0 },
3501   },
3502   /* REG_0FA7 */
3503   {
3504     { "xstore-rng",     { { OP_0f07, 0 } }, 0 },
3505     { "xcrypt-ecb",     { { OP_0f07, 0 } }, 0 },
3506     { "xcrypt-cbc",     { { OP_0f07, 0 } }, 0 },
3507     { "xcrypt-ctr",     { { OP_0f07, 0 } }, 0 },
3508     { "xcrypt-cfb",     { { OP_0f07, 0 } }, 0 },
3509     { "xcrypt-ofb",     { { OP_0f07, 0 } }, 0 },
3510   },
3511   /* REG_0FAE */
3512   {
3513     { MOD_TABLE (MOD_0FAE_REG_0) },
3514     { MOD_TABLE (MOD_0FAE_REG_1) },
3515     { MOD_TABLE (MOD_0FAE_REG_2) },
3516     { MOD_TABLE (MOD_0FAE_REG_3) },
3517     { MOD_TABLE (MOD_0FAE_REG_4) },
3518     { MOD_TABLE (MOD_0FAE_REG_5) },
3519     { MOD_TABLE (MOD_0FAE_REG_6) },
3520     { MOD_TABLE (MOD_0FAE_REG_7) },
3521   },
3522   /* REG_0FBA */
3523   {
3524     { Bad_Opcode },
3525     { Bad_Opcode },
3526     { Bad_Opcode },
3527     { Bad_Opcode },
3528     { "btQ",    { Ev, Ib }, 0 },
3529     { "btsQ",   { Evh1, Ib }, 0 },
3530     { "btrQ",   { Evh1, Ib }, 0 },
3531     { "btcQ",   { Evh1, Ib }, 0 },
3532   },
3533   /* REG_0FC7 */
3534   {
3535     { Bad_Opcode },
3536     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
3537     { Bad_Opcode },
3538     { MOD_TABLE (MOD_0FC7_REG_3) },
3539     { MOD_TABLE (MOD_0FC7_REG_4) },
3540     { MOD_TABLE (MOD_0FC7_REG_5) },
3541     { MOD_TABLE (MOD_0FC7_REG_6) },
3542     { MOD_TABLE (MOD_0FC7_REG_7) },
3543   },
3544   /* REG_VEX_0F71 */
3545   {
3546     { Bad_Opcode },
3547     { Bad_Opcode },
3548     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3549     { Bad_Opcode },
3550     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3551     { Bad_Opcode },
3552     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3553   },
3554   /* REG_VEX_0F72 */
3555   {
3556     { Bad_Opcode },
3557     { Bad_Opcode },
3558     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3559     { Bad_Opcode },
3560     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3561     { Bad_Opcode },
3562     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3563   },
3564   /* REG_VEX_0F73 */
3565   {
3566     { Bad_Opcode },
3567     { Bad_Opcode },
3568     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3569     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3570     { Bad_Opcode },
3571     { Bad_Opcode },
3572     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3573     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3574   },
3575   /* REG_VEX_0FAE */
3576   {
3577     { Bad_Opcode },
3578     { Bad_Opcode },
3579     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3580     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3581   },
3582   /* REG_VEX_0F38F3 */
3583   {
3584     { Bad_Opcode },
3585     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3586     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3587     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3588   },
3589   /* REG_XOP_LWPCB */
3590   {
3591     { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3592     { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3593   },
3594   /* REG_XOP_LWP */
3595   {
3596     { "lwpins", { { OP_LWP_E, 0 }, Ed, Id }, 0 },
3597     { "lwpval", { { OP_LWP_E, 0 }, Ed, Id }, 0 },
3598   },
3599   /* REG_XOP_TBM_01 */
3600   {
3601     { Bad_Opcode },
3602     { "blcfill",        { { OP_LWP_E, 0 }, Edq }, 0 },
3603     { "blsfill",        { { OP_LWP_E, 0 }, Edq }, 0 },
3604     { "blcs",   { { OP_LWP_E, 0 }, Edq }, 0 },
3605     { "tzmsk",  { { OP_LWP_E, 0 }, Edq }, 0 },
3606     { "blcic",  { { OP_LWP_E, 0 }, Edq }, 0 },
3607     { "blsic",  { { OP_LWP_E, 0 }, Edq }, 0 },
3608     { "t1mskc", { { OP_LWP_E, 0 }, Edq }, 0 },
3609   },
3610   /* REG_XOP_TBM_02 */
3611   {
3612     { Bad_Opcode },
3613     { "blcmsk", { { OP_LWP_E, 0 }, Edq }, 0 },
3614     { Bad_Opcode },
3615     { Bad_Opcode },
3616     { Bad_Opcode },
3617     { Bad_Opcode },
3618     { "blci",   { { OP_LWP_E, 0 }, Edq }, 0 },
3619   },
3620
3621 #include "i386-dis-evex-reg.h"
3622 };
3623
3624 static const struct dis386 prefix_table[][4] = {
3625   /* PREFIX_90 */
3626   {
3627     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3628     { "pause", { XX }, 0 },
3629     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3630     { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3631   },
3632
3633   /* PREFIX_0F01_REG_5_MOD_0 */
3634   {
3635     { Bad_Opcode },
3636     { "rstorssp",       { Mq }, PREFIX_OPCODE },
3637   },
3638
3639   /* PREFIX_0F01_REG_5_MOD_3_RM_0 */
3640   {
3641     { Bad_Opcode },
3642     { "setssbsy",       { Skip_MODRM }, PREFIX_OPCODE },
3643   },
3644
3645   /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
3646   {
3647     { Bad_Opcode },
3648     { "saveprevssp",    { Skip_MODRM }, PREFIX_OPCODE },
3649   },
3650
3651   /* PREFIX_0F01_REG_7_MOD_3_RM_2 */
3652   {
3653     { "monitorx",       { { OP_Monitor, 0 } }, 0  },
3654     { "mcommit",        { Skip_MODRM }, 0 },
3655   },
3656
3657   /* PREFIX_0F01_REG_7_MOD_3_RM_3 */
3658   {
3659     { "mwaitx",         { { OP_Mwait, eBX_reg } }, 0  },
3660   },
3661
3662   /* PREFIX_0F09 */
3663   {
3664     { "wbinvd",   { XX }, 0 },
3665     { "wbnoinvd", { XX }, 0 },
3666   },
3667
3668   /* PREFIX_0F10 */
3669   {
3670     { "movups", { XM, EXx }, PREFIX_OPCODE },
3671     { "movss",  { XM, EXd }, PREFIX_OPCODE },
3672     { "movupd", { XM, EXx }, PREFIX_OPCODE },
3673     { "movsd",  { XM, EXq }, PREFIX_OPCODE },
3674   },
3675
3676   /* PREFIX_0F11 */
3677   {
3678     { "movups", { EXxS, XM }, PREFIX_OPCODE },
3679     { "movss",  { EXdS, XM }, PREFIX_OPCODE },
3680     { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3681     { "movsd",  { EXqS, XM }, PREFIX_OPCODE },
3682   },
3683
3684   /* PREFIX_0F12 */
3685   {
3686     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3687     { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3688     { "movlpd", { XM, EXq }, PREFIX_OPCODE },
3689     { "movddup", { XM, EXq }, PREFIX_OPCODE },
3690   },
3691
3692   /* PREFIX_0F16 */
3693   {
3694     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3695     { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3696     { "movhpd", { XM, EXq }, PREFIX_OPCODE },
3697   },
3698
3699   /* PREFIX_0F1A */
3700   {
3701     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3702     { "bndcl",  { Gbnd, Ev_bnd }, 0 },
3703     { "bndmov", { Gbnd, Ebnd }, 0 },
3704     { "bndcu",  { Gbnd, Ev_bnd }, 0 },
3705   },
3706
3707   /* PREFIX_0F1B */
3708   {
3709     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3710     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3711     { "bndmov", { EbndS, Gbnd }, 0 },
3712     { "bndcn",  { Gbnd, Ev_bnd }, 0 },
3713   },
3714
3715   /* PREFIX_0F1C */
3716   {
3717     { MOD_TABLE (MOD_0F1C_PREFIX_0) },
3718     { "nopQ",   { Ev }, PREFIX_OPCODE },
3719     { "nopQ",   { Ev }, PREFIX_OPCODE },
3720     { "nopQ",   { Ev }, PREFIX_OPCODE },
3721   },
3722
3723   /* PREFIX_0F1E */
3724   {
3725     { "nopQ",   { Ev }, PREFIX_OPCODE },
3726     { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3727     { "nopQ",   { Ev }, PREFIX_OPCODE },
3728     { "nopQ",   { Ev }, PREFIX_OPCODE },
3729   },
3730
3731   /* PREFIX_0F2A */
3732   {
3733     { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3734     { "cvtsi2ss%LQ", { XM, Edq }, PREFIX_OPCODE },
3735     { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3736     { "cvtsi2sd%LQ", { XM, Edq }, 0 },
3737   },
3738
3739   /* PREFIX_0F2B */
3740   {
3741     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3742     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3743     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3744     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3745   },
3746
3747   /* PREFIX_0F2C */
3748   {
3749     { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3750     { "cvttss2si", { Gdq, EXd }, PREFIX_OPCODE },
3751     { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3752     { "cvttsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3753   },
3754
3755   /* PREFIX_0F2D */
3756   {
3757     { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3758     { "cvtss2si", { Gdq, EXd }, PREFIX_OPCODE },
3759     { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3760     { "cvtsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3761   },
3762
3763   /* PREFIX_0F2E */
3764   {
3765     { "ucomiss",{ XM, EXd }, 0 },
3766     { Bad_Opcode },
3767     { "ucomisd",{ XM, EXq }, 0 },
3768   },
3769
3770   /* PREFIX_0F2F */
3771   {
3772     { "comiss", { XM, EXd }, 0 },
3773     { Bad_Opcode },
3774     { "comisd", { XM, EXq }, 0 },
3775   },
3776
3777   /* PREFIX_0F51 */
3778   {
3779     { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3780     { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3781     { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3782     { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3783   },
3784
3785   /* PREFIX_0F52 */
3786   {
3787     { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3788     { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3789   },
3790
3791   /* PREFIX_0F53 */
3792   {
3793     { "rcpps",  { XM, EXx }, PREFIX_OPCODE },
3794     { "rcpss",  { XM, EXd }, PREFIX_OPCODE },
3795   },
3796
3797   /* PREFIX_0F58 */
3798   {
3799     { "addps", { XM, EXx }, PREFIX_OPCODE },
3800     { "addss", { XM, EXd }, PREFIX_OPCODE },
3801     { "addpd", { XM, EXx }, PREFIX_OPCODE },
3802     { "addsd", { XM, EXq }, PREFIX_OPCODE },
3803   },
3804
3805   /* PREFIX_0F59 */
3806   {
3807     { "mulps",  { XM, EXx }, PREFIX_OPCODE },
3808     { "mulss",  { XM, EXd }, PREFIX_OPCODE },
3809     { "mulpd",  { XM, EXx }, PREFIX_OPCODE },
3810     { "mulsd",  { XM, EXq }, PREFIX_OPCODE },
3811   },
3812
3813   /* PREFIX_0F5A */
3814   {
3815     { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3816     { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3817     { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3818     { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3819   },
3820
3821   /* PREFIX_0F5B */
3822   {
3823     { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3824     { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3825     { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3826   },
3827
3828   /* PREFIX_0F5C */
3829   {
3830     { "subps",  { XM, EXx }, PREFIX_OPCODE },
3831     { "subss",  { XM, EXd }, PREFIX_OPCODE },
3832     { "subpd",  { XM, EXx }, PREFIX_OPCODE },
3833     { "subsd",  { XM, EXq }, PREFIX_OPCODE },
3834   },
3835
3836   /* PREFIX_0F5D */
3837   {
3838     { "minps",  { XM, EXx }, PREFIX_OPCODE },
3839     { "minss",  { XM, EXd }, PREFIX_OPCODE },
3840     { "minpd",  { XM, EXx }, PREFIX_OPCODE },
3841     { "minsd",  { XM, EXq }, PREFIX_OPCODE },
3842   },
3843
3844   /* PREFIX_0F5E */
3845   {
3846     { "divps",  { XM, EXx }, PREFIX_OPCODE },
3847     { "divss",  { XM, EXd }, PREFIX_OPCODE },
3848     { "divpd",  { XM, EXx }, PREFIX_OPCODE },
3849     { "divsd",  { XM, EXq }, PREFIX_OPCODE },
3850   },
3851
3852   /* PREFIX_0F5F */
3853   {
3854     { "maxps",  { XM, EXx }, PREFIX_OPCODE },
3855     { "maxss",  { XM, EXd }, PREFIX_OPCODE },
3856     { "maxpd",  { XM, EXx }, PREFIX_OPCODE },
3857     { "maxsd",  { XM, EXq }, PREFIX_OPCODE },
3858   },
3859
3860   /* PREFIX_0F60 */
3861   {
3862     { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3863     { Bad_Opcode },
3864     { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3865   },
3866
3867   /* PREFIX_0F61 */
3868   {
3869     { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3870     { Bad_Opcode },
3871     { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3872   },
3873
3874   /* PREFIX_0F62 */
3875   {
3876     { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3877     { Bad_Opcode },
3878     { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3879   },
3880
3881   /* PREFIX_0F6C */
3882   {
3883     { Bad_Opcode },
3884     { Bad_Opcode },
3885     { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE },
3886   },
3887
3888   /* PREFIX_0F6D */
3889   {
3890     { Bad_Opcode },
3891     { Bad_Opcode },
3892     { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE },
3893   },
3894
3895   /* PREFIX_0F6F */
3896   {
3897     { "movq",   { MX, EM }, PREFIX_OPCODE },
3898     { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3899     { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3900   },
3901
3902   /* PREFIX_0F70 */
3903   {
3904     { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3905     { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3906     { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3907     { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3908   },
3909
3910   /* PREFIX_0F73_REG_3 */
3911   {
3912     { Bad_Opcode },
3913     { Bad_Opcode },
3914     { "psrldq", { XS, Ib }, 0 },
3915   },
3916
3917   /* PREFIX_0F73_REG_7 */
3918   {
3919     { Bad_Opcode },
3920     { Bad_Opcode },
3921     { "pslldq", { XS, Ib }, 0 },
3922   },
3923
3924   /* PREFIX_0F78 */
3925   {
3926     {"vmread",  { Em, Gm }, 0 },
3927     { Bad_Opcode },
3928     {"extrq",   { XS, Ib, Ib }, 0 },
3929     {"insertq", { XM, XS, Ib, Ib }, 0 },
3930   },
3931
3932   /* PREFIX_0F79 */
3933   {
3934     {"vmwrite", { Gm, Em }, 0 },
3935     { Bad_Opcode },
3936     {"extrq",   { XM, XS }, 0 },
3937     {"insertq", { XM, XS }, 0 },
3938   },
3939
3940   /* PREFIX_0F7C */
3941   {
3942     { Bad_Opcode },
3943     { Bad_Opcode },
3944     { "haddpd", { XM, EXx }, PREFIX_OPCODE },
3945     { "haddps", { XM, EXx }, PREFIX_OPCODE },
3946   },
3947
3948   /* PREFIX_0F7D */
3949   {
3950     { Bad_Opcode },
3951     { Bad_Opcode },
3952     { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
3953     { "hsubps", { XM, EXx }, PREFIX_OPCODE },
3954   },
3955
3956   /* PREFIX_0F7E */
3957   {
3958     { "movK",   { Edq, MX }, PREFIX_OPCODE },
3959     { "movq",   { XM, EXq }, PREFIX_OPCODE },
3960     { "movK",   { Edq, XM }, PREFIX_OPCODE },
3961   },
3962
3963   /* PREFIX_0F7F */
3964   {
3965     { "movq",   { EMS, MX }, PREFIX_OPCODE },
3966     { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
3967     { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
3968   },
3969
3970   /* PREFIX_0FAE_REG_0_MOD_3 */
3971   {
3972     { Bad_Opcode },
3973     { "rdfsbase", { Ev }, 0 },
3974   },
3975
3976   /* PREFIX_0FAE_REG_1_MOD_3 */
3977   {
3978     { Bad_Opcode },
3979     { "rdgsbase", { Ev }, 0 },
3980   },
3981
3982   /* PREFIX_0FAE_REG_2_MOD_3 */
3983   {
3984     { Bad_Opcode },
3985     { "wrfsbase", { Ev }, 0 },
3986   },
3987
3988   /* PREFIX_0FAE_REG_3_MOD_3 */
3989   {
3990     { Bad_Opcode },
3991     { "wrgsbase", { Ev }, 0 },
3992   },
3993
3994   /* PREFIX_0FAE_REG_4_MOD_0 */
3995   {
3996     { "xsave",  { FXSAVE }, 0 },
3997     { "ptwrite%LQ", { Edq }, 0 },
3998   },
3999
4000   /* PREFIX_0FAE_REG_4_MOD_3 */
4001   {
4002     { Bad_Opcode },
4003     { "ptwrite%LQ", { Edq }, 0 },
4004   },
4005
4006   /* PREFIX_0FAE_REG_5_MOD_0 */
4007   {
4008     { "xrstor",         { FXSAVE }, PREFIX_OPCODE },
4009   },
4010
4011   /* PREFIX_0FAE_REG_5_MOD_3 */
4012   {
4013     { "lfence",         { Skip_MODRM }, 0 },
4014     { "incsspK",        { Rdq }, PREFIX_OPCODE },
4015   },
4016
4017   /* PREFIX_0FAE_REG_6_MOD_0 */
4018   {
4019     { "xsaveopt",       { FXSAVE }, PREFIX_OPCODE },
4020     { "clrssbsy",       { Mq }, PREFIX_OPCODE },
4021     { "clwb",   { Mb }, PREFIX_OPCODE },
4022   },
4023
4024   /* PREFIX_0FAE_REG_6_MOD_3 */
4025   {
4026     { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0) },
4027     { "umonitor",       { Eva }, PREFIX_OPCODE },
4028     { "tpause", { Edq }, PREFIX_OPCODE },
4029     { "umwait", { Edq }, PREFIX_OPCODE },
4030   },
4031
4032   /* PREFIX_0FAE_REG_7_MOD_0 */
4033   {
4034     { "clflush",        { Mb }, 0 },
4035     { Bad_Opcode },
4036     { "clflushopt",     { Mb }, 0 },
4037   },
4038
4039   /* PREFIX_0FB8 */
4040   {
4041     { Bad_Opcode },
4042     { "popcntS", { Gv, Ev }, 0 },
4043   },
4044
4045   /* PREFIX_0FBC */
4046   {
4047     { "bsfS",   { Gv, Ev }, 0 },
4048     { "tzcntS", { Gv, Ev }, 0 },
4049     { "bsfS",   { Gv, Ev }, 0 },
4050   },
4051
4052   /* PREFIX_0FBD */
4053   {
4054     { "bsrS",   { Gv, Ev }, 0 },
4055     { "lzcntS", { Gv, Ev }, 0 },
4056     { "bsrS",   { Gv, Ev }, 0 },
4057   },
4058
4059   /* PREFIX_0FC2 */
4060   {
4061     { "cmpps",  { XM, EXx, CMP }, PREFIX_OPCODE },
4062     { "cmpss",  { XM, EXd, CMP }, PREFIX_OPCODE },
4063     { "cmppd",  { XM, EXx, CMP }, PREFIX_OPCODE },
4064     { "cmpsd",  { XM, EXq, CMP }, PREFIX_OPCODE },
4065   },
4066
4067   /* PREFIX_0FC3_MOD_0 */
4068   {
4069     { "movntiS", { Edq, Gdq }, PREFIX_OPCODE },
4070   },
4071
4072   /* PREFIX_0FC7_REG_6_MOD_0 */
4073   {
4074     { "vmptrld",{ Mq }, 0 },
4075     { "vmxon",  { Mq }, 0 },
4076     { "vmclear",{ Mq }, 0 },
4077   },
4078
4079   /* PREFIX_0FC7_REG_6_MOD_3 */
4080   {
4081     { "rdrand", { Ev }, 0 },
4082     { Bad_Opcode },
4083     { "rdrand", { Ev }, 0 }
4084   },
4085
4086   /* PREFIX_0FC7_REG_7_MOD_3 */
4087   {
4088     { "rdseed", { Ev }, 0 },
4089     { "rdpid",  { Em }, 0 },
4090     { "rdseed", { Ev }, 0 },
4091   },
4092
4093   /* PREFIX_0FD0 */
4094   {
4095     { Bad_Opcode },
4096     { Bad_Opcode },
4097     { "addsubpd", { XM, EXx }, 0 },
4098     { "addsubps", { XM, EXx }, 0 },
4099   },
4100
4101   /* PREFIX_0FD6 */
4102   {
4103     { Bad_Opcode },
4104     { "movq2dq",{ XM, MS }, 0 },
4105     { "movq",   { EXqS, XM }, 0 },
4106     { "movdq2q",{ MX, XS }, 0 },
4107   },
4108
4109   /* PREFIX_0FE6 */
4110   {
4111     { Bad_Opcode },
4112     { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
4113     { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
4114     { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
4115   },
4116
4117   /* PREFIX_0FE7 */
4118   {
4119     { "movntq", { Mq, MX }, PREFIX_OPCODE },
4120     { Bad_Opcode },
4121     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
4122   },
4123
4124   /* PREFIX_0FF0 */
4125   {
4126     { Bad_Opcode },
4127     { Bad_Opcode },
4128     { Bad_Opcode },
4129     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4130   },
4131
4132   /* PREFIX_0FF7 */
4133   {
4134     { "maskmovq", { MX, MS }, PREFIX_OPCODE },
4135     { Bad_Opcode },
4136     { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
4137   },
4138
4139   /* PREFIX_0F3810 */
4140   {
4141     { Bad_Opcode },
4142     { Bad_Opcode },
4143     { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4144   },
4145
4146   /* PREFIX_0F3814 */
4147   {
4148     { Bad_Opcode },
4149     { Bad_Opcode },
4150     { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4151   },
4152
4153   /* PREFIX_0F3815 */
4154   {
4155     { Bad_Opcode },
4156     { Bad_Opcode },
4157     { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4158   },
4159
4160   /* PREFIX_0F3817 */
4161   {
4162     { Bad_Opcode },
4163     { Bad_Opcode },
4164     { "ptest",  { XM, EXx }, PREFIX_OPCODE },
4165   },
4166
4167   /* PREFIX_0F3820 */
4168   {
4169     { Bad_Opcode },
4170     { Bad_Opcode },
4171     { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE },
4172   },
4173
4174   /* PREFIX_0F3821 */
4175   {
4176     { Bad_Opcode },
4177     { Bad_Opcode },
4178     { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE },
4179   },
4180
4181   /* PREFIX_0F3822 */
4182   {
4183     { Bad_Opcode },
4184     { Bad_Opcode },
4185     { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE },
4186   },
4187
4188   /* PREFIX_0F3823 */
4189   {
4190     { Bad_Opcode },
4191     { Bad_Opcode },
4192     { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE },
4193   },
4194
4195   /* PREFIX_0F3824 */
4196   {
4197     { Bad_Opcode },
4198     { Bad_Opcode },
4199     { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE },
4200   },
4201
4202   /* PREFIX_0F3825 */
4203   {
4204     { Bad_Opcode },
4205     { Bad_Opcode },
4206     { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE },
4207   },
4208
4209   /* PREFIX_0F3828 */
4210   {
4211     { Bad_Opcode },
4212     { Bad_Opcode },
4213     { "pmuldq", { XM, EXx }, PREFIX_OPCODE },
4214   },
4215
4216   /* PREFIX_0F3829 */
4217   {
4218     { Bad_Opcode },
4219     { Bad_Opcode },
4220     { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE },
4221   },
4222
4223   /* PREFIX_0F382A */
4224   {
4225     { Bad_Opcode },
4226     { Bad_Opcode },
4227     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4228   },
4229
4230   /* PREFIX_0F382B */
4231   {
4232     { Bad_Opcode },
4233     { Bad_Opcode },
4234     { "packusdw", { XM, EXx }, PREFIX_OPCODE },
4235   },
4236
4237   /* PREFIX_0F3830 */
4238   {
4239     { Bad_Opcode },
4240     { Bad_Opcode },
4241     { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE },
4242   },
4243
4244   /* PREFIX_0F3831 */
4245   {
4246     { Bad_Opcode },
4247     { Bad_Opcode },
4248     { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE },
4249   },
4250
4251   /* PREFIX_0F3832 */
4252   {
4253     { Bad_Opcode },
4254     { Bad_Opcode },
4255     { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE },
4256   },
4257
4258   /* PREFIX_0F3833 */
4259   {
4260     { Bad_Opcode },
4261     { Bad_Opcode },
4262     { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE },
4263   },
4264
4265   /* PREFIX_0F3834 */
4266   {
4267     { Bad_Opcode },
4268     { Bad_Opcode },
4269     { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE },
4270   },
4271
4272   /* PREFIX_0F3835 */
4273   {
4274     { Bad_Opcode },
4275     { Bad_Opcode },
4276     { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE },
4277   },
4278
4279   /* PREFIX_0F3837 */
4280   {
4281     { Bad_Opcode },
4282     { Bad_Opcode },
4283     { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE },
4284   },
4285
4286   /* PREFIX_0F3838 */
4287   {
4288     { Bad_Opcode },
4289     { Bad_Opcode },
4290     { "pminsb", { XM, EXx }, PREFIX_OPCODE },
4291   },
4292
4293   /* PREFIX_0F3839 */
4294   {
4295     { Bad_Opcode },
4296     { Bad_Opcode },
4297     { "pminsd", { XM, EXx }, PREFIX_OPCODE },
4298   },
4299
4300   /* PREFIX_0F383A */
4301   {
4302     { Bad_Opcode },
4303     { Bad_Opcode },
4304     { "pminuw", { XM, EXx }, PREFIX_OPCODE },
4305   },
4306
4307   /* PREFIX_0F383B */
4308   {
4309     { Bad_Opcode },
4310     { Bad_Opcode },
4311     { "pminud", { XM, EXx }, PREFIX_OPCODE },
4312   },
4313
4314   /* PREFIX_0F383C */
4315   {
4316     { Bad_Opcode },
4317     { Bad_Opcode },
4318     { "pmaxsb", { XM, EXx }, PREFIX_OPCODE },
4319   },
4320
4321   /* PREFIX_0F383D */
4322   {
4323     { Bad_Opcode },
4324     { Bad_Opcode },
4325     { "pmaxsd", { XM, EXx }, PREFIX_OPCODE },
4326   },
4327
4328   /* PREFIX_0F383E */
4329   {
4330     { Bad_Opcode },
4331     { Bad_Opcode },
4332     { "pmaxuw", { XM, EXx }, PREFIX_OPCODE },
4333   },
4334
4335   /* PREFIX_0F383F */
4336   {
4337     { Bad_Opcode },
4338     { Bad_Opcode },
4339     { "pmaxud", { XM, EXx }, PREFIX_OPCODE },
4340   },
4341
4342   /* PREFIX_0F3840 */
4343   {
4344     { Bad_Opcode },
4345     { Bad_Opcode },
4346     { "pmulld", { XM, EXx }, PREFIX_OPCODE },
4347   },
4348
4349   /* PREFIX_0F3841 */
4350   {
4351     { Bad_Opcode },
4352     { Bad_Opcode },
4353     { "phminposuw", { XM, EXx }, PREFIX_OPCODE },
4354   },
4355
4356   /* PREFIX_0F3880 */
4357   {
4358     { Bad_Opcode },
4359     { Bad_Opcode },
4360     { "invept", { Gm, Mo }, PREFIX_OPCODE },
4361   },
4362
4363   /* PREFIX_0F3881 */
4364   {
4365     { Bad_Opcode },
4366     { Bad_Opcode },
4367     { "invvpid", { Gm, Mo }, PREFIX_OPCODE },
4368   },
4369
4370   /* PREFIX_0F3882 */
4371   {
4372     { Bad_Opcode },
4373     { Bad_Opcode },
4374     { "invpcid", { Gm, M }, PREFIX_OPCODE },
4375   },
4376
4377   /* PREFIX_0F38C8 */
4378   {
4379     { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4380   },
4381
4382   /* PREFIX_0F38C9 */
4383   {
4384     { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4385   },
4386
4387   /* PREFIX_0F38CA */
4388   {
4389     { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4390   },
4391
4392   /* PREFIX_0F38CB */
4393   {
4394     { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4395   },
4396
4397   /* PREFIX_0F38CC */
4398   {
4399     { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4400   },
4401
4402   /* PREFIX_0F38CD */
4403   {
4404     { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4405   },
4406
4407   /* PREFIX_0F38CF */
4408   {
4409     { Bad_Opcode },
4410     { Bad_Opcode },
4411     { "gf2p8mulb", { XM, EXxmm }, PREFIX_OPCODE },
4412   },
4413
4414   /* PREFIX_0F38DB */
4415   {
4416     { Bad_Opcode },
4417     { Bad_Opcode },
4418     { "aesimc", { XM, EXx }, PREFIX_OPCODE },
4419   },
4420
4421   /* PREFIX_0F38DC */
4422   {
4423     { Bad_Opcode },
4424     { Bad_Opcode },
4425     { "aesenc", { XM, EXx }, PREFIX_OPCODE },
4426   },
4427
4428   /* PREFIX_0F38DD */
4429   {
4430     { Bad_Opcode },
4431     { Bad_Opcode },
4432     { "aesenclast", { XM, EXx }, PREFIX_OPCODE },
4433   },
4434
4435   /* PREFIX_0F38DE */
4436   {
4437     { Bad_Opcode },
4438     { Bad_Opcode },
4439     { "aesdec", { XM, EXx }, PREFIX_OPCODE },
4440   },
4441
4442   /* PREFIX_0F38DF */
4443   {
4444     { Bad_Opcode },
4445     { Bad_Opcode },
4446     { "aesdeclast", { XM, EXx }, PREFIX_OPCODE },
4447   },
4448
4449   /* PREFIX_0F38F0 */
4450   {
4451     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4452     { Bad_Opcode },
4453     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4454     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE },
4455   },
4456
4457   /* PREFIX_0F38F1 */
4458   {
4459     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4460     { Bad_Opcode },
4461     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4462     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE },
4463   },
4464
4465   /* PREFIX_0F38F5 */
4466   {
4467     { Bad_Opcode },
4468     { Bad_Opcode },
4469     { MOD_TABLE (MOD_0F38F5_PREFIX_2) },
4470   },
4471
4472   /* PREFIX_0F38F6 */
4473   {
4474     { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
4475     { "adoxS",  { Gdq, Edq}, PREFIX_OPCODE },
4476     { "adcxS",  { Gdq, Edq}, PREFIX_OPCODE },
4477     { Bad_Opcode },
4478   },
4479
4480   /* PREFIX_0F38F8 */
4481   {
4482     { Bad_Opcode },
4483     { MOD_TABLE (MOD_0F38F8_PREFIX_1) },
4484     { MOD_TABLE (MOD_0F38F8_PREFIX_2) },
4485     { MOD_TABLE (MOD_0F38F8_PREFIX_3) },
4486   },
4487
4488   /* PREFIX_0F38F9 */
4489   {
4490     { MOD_TABLE (MOD_0F38F9_PREFIX_0) },
4491   },
4492
4493   /* PREFIX_0F3A08 */
4494   {
4495     { Bad_Opcode },
4496     { Bad_Opcode },
4497     { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE },
4498   },
4499
4500   /* PREFIX_0F3A09 */
4501   {
4502     { Bad_Opcode },
4503     { Bad_Opcode },
4504     { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4505   },
4506
4507   /* PREFIX_0F3A0A */
4508   {
4509     { Bad_Opcode },
4510     { Bad_Opcode },
4511     { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE },
4512   },
4513
4514   /* PREFIX_0F3A0B */
4515   {
4516     { Bad_Opcode },
4517     { Bad_Opcode },
4518     { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE },
4519   },
4520
4521   /* PREFIX_0F3A0C */
4522   {
4523     { Bad_Opcode },
4524     { Bad_Opcode },
4525     { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE },
4526   },
4527
4528   /* PREFIX_0F3A0D */
4529   {
4530     { Bad_Opcode },
4531     { Bad_Opcode },
4532     { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4533   },
4534
4535   /* PREFIX_0F3A0E */
4536   {
4537     { Bad_Opcode },
4538     { Bad_Opcode },
4539     { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE },
4540   },
4541
4542   /* PREFIX_0F3A14 */
4543   {
4544     { Bad_Opcode },
4545     { Bad_Opcode },
4546     { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE },
4547   },
4548
4549   /* PREFIX_0F3A15 */
4550   {
4551     { Bad_Opcode },
4552     { Bad_Opcode },
4553     { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE },
4554   },
4555
4556   /* PREFIX_0F3A16 */
4557   {
4558     { Bad_Opcode },
4559     { Bad_Opcode },
4560     { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE },
4561   },
4562
4563   /* PREFIX_0F3A17 */
4564   {
4565     { Bad_Opcode },
4566     { Bad_Opcode },
4567     { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE },
4568   },
4569
4570   /* PREFIX_0F3A20 */
4571   {
4572     { Bad_Opcode },
4573     { Bad_Opcode },
4574     { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE },
4575   },
4576
4577   /* PREFIX_0F3A21 */
4578   {
4579     { Bad_Opcode },
4580     { Bad_Opcode },
4581     { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE },
4582   },
4583
4584   /* PREFIX_0F3A22 */
4585   {
4586     { Bad_Opcode },
4587     { Bad_Opcode },
4588     { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE },
4589   },
4590
4591   /* PREFIX_0F3A40 */
4592   {
4593     { Bad_Opcode },
4594     { Bad_Opcode },
4595     { "dpps",   { XM, EXx, Ib }, PREFIX_OPCODE },
4596   },
4597
4598   /* PREFIX_0F3A41 */
4599   {
4600     { Bad_Opcode },
4601     { Bad_Opcode },
4602     { "dppd",   { XM, EXx, Ib }, PREFIX_OPCODE },
4603   },
4604
4605   /* PREFIX_0F3A42 */
4606   {
4607     { Bad_Opcode },
4608     { Bad_Opcode },
4609     { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE },
4610   },
4611
4612   /* PREFIX_0F3A44 */
4613   {
4614     { Bad_Opcode },
4615     { Bad_Opcode },
4616     { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE },
4617   },
4618
4619   /* PREFIX_0F3A60 */
4620   {
4621     { Bad_Opcode },
4622     { Bad_Opcode },
4623     { "pcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4624   },
4625
4626   /* PREFIX_0F3A61 */
4627   {
4628     { Bad_Opcode },
4629     { Bad_Opcode },
4630     { "pcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4631   },
4632
4633   /* PREFIX_0F3A62 */
4634   {
4635     { Bad_Opcode },
4636     { Bad_Opcode },
4637     { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4638   },
4639
4640   /* PREFIX_0F3A63 */
4641   {
4642     { Bad_Opcode },
4643     { Bad_Opcode },
4644     { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE },
4645   },
4646
4647   /* PREFIX_0F3ACC */
4648   {
4649     { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4650   },
4651
4652   /* PREFIX_0F3ACE */
4653   {
4654     { Bad_Opcode },
4655     { Bad_Opcode },
4656     { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4657   },
4658
4659   /* PREFIX_0F3ACF */
4660   {
4661     { Bad_Opcode },
4662     { Bad_Opcode },
4663     { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4664   },
4665
4666   /* PREFIX_0F3ADF */
4667   {
4668     { Bad_Opcode },
4669     { Bad_Opcode },
4670     { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE },
4671   },
4672
4673   /* PREFIX_VEX_0F10 */
4674   {
4675     { "vmovups",        { XM, EXx }, 0 },
4676     { "vmovss",         { XMVexScalar, VexScalar, EXdScalar }, 0 },
4677     { "vmovupd",        { XM, EXx }, 0 },
4678     { "vmovsd",         { XMVexScalar, VexScalar, EXqScalar }, 0 },
4679   },
4680
4681   /* PREFIX_VEX_0F11 */
4682   {
4683     { "vmovups",        { EXxS, XM }, 0 },
4684     { "vmovss",         { EXdVexScalarS, VexScalar, XMScalar }, 0 },
4685     { "vmovupd",        { EXxS, XM }, 0 },
4686     { "vmovsd",         { EXqVexScalarS, VexScalar, XMScalar }, 0 },
4687   },
4688
4689   /* PREFIX_VEX_0F12 */
4690   {
4691     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4692     { "vmovsldup",      { XM, EXx }, 0 },
4693     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
4694     { "vmovddup",       { XM, EXymmq }, 0 },
4695   },
4696
4697   /* PREFIX_VEX_0F16 */
4698   {
4699     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4700     { "vmovshdup",      { XM, EXx }, 0 },
4701     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
4702   },
4703
4704   /* PREFIX_VEX_0F2A */
4705   {
4706     { Bad_Opcode },
4707     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Edq }, 0 },
4708     { Bad_Opcode },
4709     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Edq }, 0 },
4710   },
4711
4712   /* PREFIX_VEX_0F2C */
4713   {
4714     { Bad_Opcode },
4715     { "vcvttss2si",     { Gdq, EXdScalar }, 0 },
4716     { Bad_Opcode },
4717     { "vcvttsd2si",     { Gdq, EXqScalar }, 0 },
4718   },
4719
4720   /* PREFIX_VEX_0F2D */
4721   {
4722     { Bad_Opcode },
4723     { "vcvtss2si",      { Gdq, EXdScalar }, 0 },
4724     { Bad_Opcode },
4725     { "vcvtsd2si",      { Gdq, EXqScalar }, 0 },
4726   },
4727
4728   /* PREFIX_VEX_0F2E */
4729   {
4730     { "vucomiss",       { XMScalar, EXdScalar }, 0 },
4731     { Bad_Opcode },
4732     { "vucomisd",       { XMScalar, EXqScalar }, 0 },
4733   },
4734
4735   /* PREFIX_VEX_0F2F */
4736   {
4737     { "vcomiss",        { XMScalar, EXdScalar }, 0 },
4738     { Bad_Opcode },
4739     { "vcomisd",        { XMScalar, EXqScalar }, 0 },
4740   },
4741
4742   /* PREFIX_VEX_0F41 */
4743   {
4744     { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4745     { Bad_Opcode },
4746     { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4747   },
4748
4749   /* PREFIX_VEX_0F42 */
4750   {
4751     { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4752     { Bad_Opcode },
4753     { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4754   },
4755
4756   /* PREFIX_VEX_0F44 */
4757   {
4758     { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4759     { Bad_Opcode },
4760     { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4761   },
4762
4763   /* PREFIX_VEX_0F45 */
4764   {
4765     { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4766     { Bad_Opcode },
4767     { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4768   },
4769
4770   /* PREFIX_VEX_0F46 */
4771   {
4772     { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4773     { Bad_Opcode },
4774     { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4775   },
4776
4777   /* PREFIX_VEX_0F47 */
4778   {
4779     { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4780     { Bad_Opcode },
4781     { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
4782   },
4783
4784   /* PREFIX_VEX_0F4A */
4785   {
4786     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
4787     { Bad_Opcode },
4788     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
4789   },
4790
4791   /* PREFIX_VEX_0F4B */
4792   {
4793     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
4794     { Bad_Opcode },
4795     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4796   },
4797
4798   /* PREFIX_VEX_0F51 */
4799   {
4800     { "vsqrtps",        { XM, EXx }, 0 },
4801     { "vsqrtss",        { XMScalar, VexScalar, EXdScalar }, 0 },
4802     { "vsqrtpd",        { XM, EXx }, 0 },
4803     { "vsqrtsd",        { XMScalar, VexScalar, EXqScalar }, 0 },
4804   },
4805
4806   /* PREFIX_VEX_0F52 */
4807   {
4808     { "vrsqrtps",       { XM, EXx }, 0 },
4809     { "vrsqrtss",       { XMScalar, VexScalar, EXdScalar }, 0 },
4810   },
4811
4812   /* PREFIX_VEX_0F53 */
4813   {
4814     { "vrcpps",         { XM, EXx }, 0 },
4815     { "vrcpss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4816   },
4817
4818   /* PREFIX_VEX_0F58 */
4819   {
4820     { "vaddps",         { XM, Vex, EXx }, 0 },
4821     { "vaddss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4822     { "vaddpd",         { XM, Vex, EXx }, 0 },
4823     { "vaddsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4824   },
4825
4826   /* PREFIX_VEX_0F59 */
4827   {
4828     { "vmulps",         { XM, Vex, EXx }, 0 },
4829     { "vmulss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4830     { "vmulpd",         { XM, Vex, EXx }, 0 },
4831     { "vmulsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4832   },
4833
4834   /* PREFIX_VEX_0F5A */
4835   {
4836     { "vcvtps2pd",      { XM, EXxmmq }, 0 },
4837     { "vcvtss2sd",      { XMScalar, VexScalar, EXdScalar }, 0 },
4838     { "vcvtpd2ps%XY",{ XMM, EXx }, 0 },
4839     { "vcvtsd2ss",      { XMScalar, VexScalar, EXqScalar }, 0 },
4840   },
4841
4842   /* PREFIX_VEX_0F5B */
4843   {
4844     { "vcvtdq2ps",      { XM, EXx }, 0 },
4845     { "vcvttps2dq",     { XM, EXx }, 0 },
4846     { "vcvtps2dq",      { XM, EXx }, 0 },
4847   },
4848
4849   /* PREFIX_VEX_0F5C */
4850   {
4851     { "vsubps",         { XM, Vex, EXx }, 0 },
4852     { "vsubss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4853     { "vsubpd",         { XM, Vex, EXx }, 0 },
4854     { "vsubsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4855   },
4856
4857   /* PREFIX_VEX_0F5D */
4858   {
4859     { "vminps",         { XM, Vex, EXx }, 0 },
4860     { "vminss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4861     { "vminpd",         { XM, Vex, EXx }, 0 },
4862     { "vminsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4863   },
4864
4865   /* PREFIX_VEX_0F5E */
4866   {
4867     { "vdivps",         { XM, Vex, EXx }, 0 },
4868     { "vdivss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4869     { "vdivpd",         { XM, Vex, EXx }, 0 },
4870     { "vdivsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4871   },
4872
4873   /* PREFIX_VEX_0F5F */
4874   {
4875     { "vmaxps",         { XM, Vex, EXx }, 0 },
4876     { "vmaxss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4877     { "vmaxpd",         { XM, Vex, EXx }, 0 },
4878     { "vmaxsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4879   },
4880
4881   /* PREFIX_VEX_0F60 */
4882   {
4883     { Bad_Opcode },
4884     { Bad_Opcode },
4885     { "vpunpcklbw",     { XM, Vex, EXx }, 0 },
4886   },
4887
4888   /* PREFIX_VEX_0F61 */
4889   {
4890     { Bad_Opcode },
4891     { Bad_Opcode },
4892     { "vpunpcklwd",     { XM, Vex, EXx }, 0 },
4893   },
4894
4895   /* PREFIX_VEX_0F62 */
4896   {
4897     { Bad_Opcode },
4898     { Bad_Opcode },
4899     { "vpunpckldq",     { XM, Vex, EXx }, 0 },
4900   },
4901
4902   /* PREFIX_VEX_0F63 */
4903   {
4904     { Bad_Opcode },
4905     { Bad_Opcode },
4906     { "vpacksswb",      { XM, Vex, EXx }, 0 },
4907   },
4908
4909   /* PREFIX_VEX_0F64 */
4910   {
4911     { Bad_Opcode },
4912     { Bad_Opcode },
4913     { "vpcmpgtb",       { XM, Vex, EXx }, 0 },
4914   },
4915
4916   /* PREFIX_VEX_0F65 */
4917   {
4918     { Bad_Opcode },
4919     { Bad_Opcode },
4920     { "vpcmpgtw",       { XM, Vex, EXx }, 0 },
4921   },
4922
4923   /* PREFIX_VEX_0F66 */
4924   {
4925     { Bad_Opcode },
4926     { Bad_Opcode },
4927     { "vpcmpgtd",       { XM, Vex, EXx }, 0 },
4928   },
4929
4930   /* PREFIX_VEX_0F67 */
4931   {
4932     { Bad_Opcode },
4933     { Bad_Opcode },
4934     { "vpackuswb",      { XM, Vex, EXx }, 0 },
4935   },
4936
4937   /* PREFIX_VEX_0F68 */
4938   {
4939     { Bad_Opcode },
4940     { Bad_Opcode },
4941     { "vpunpckhbw",     { XM, Vex, EXx }, 0 },
4942   },
4943
4944   /* PREFIX_VEX_0F69 */
4945   {
4946     { Bad_Opcode },
4947     { Bad_Opcode },
4948     { "vpunpckhwd",     { XM, Vex, EXx }, 0 },
4949   },
4950
4951   /* PREFIX_VEX_0F6A */
4952   {
4953     { Bad_Opcode },
4954     { Bad_Opcode },
4955     { "vpunpckhdq",     { XM, Vex, EXx }, 0 },
4956   },
4957
4958   /* PREFIX_VEX_0F6B */
4959   {
4960     { Bad_Opcode },
4961     { Bad_Opcode },
4962     { "vpackssdw",      { XM, Vex, EXx }, 0 },
4963   },
4964
4965   /* PREFIX_VEX_0F6C */
4966   {
4967     { Bad_Opcode },
4968     { Bad_Opcode },
4969     { "vpunpcklqdq",    { XM, Vex, EXx }, 0 },
4970   },
4971
4972   /* PREFIX_VEX_0F6D */
4973   {
4974     { Bad_Opcode },
4975     { Bad_Opcode },
4976     { "vpunpckhqdq",    { XM, Vex, EXx }, 0 },
4977   },
4978
4979   /* PREFIX_VEX_0F6E */
4980   {
4981     { Bad_Opcode },
4982     { Bad_Opcode },
4983     { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
4984   },
4985
4986   /* PREFIX_VEX_0F6F */
4987   {
4988     { Bad_Opcode },
4989     { "vmovdqu",        { XM, EXx }, 0 },
4990     { "vmovdqa",        { XM, EXx }, 0 },
4991   },
4992
4993   /* PREFIX_VEX_0F70 */
4994   {
4995     { Bad_Opcode },
4996     { "vpshufhw",       { XM, EXx, Ib }, 0 },
4997     { "vpshufd",        { XM, EXx, Ib }, 0 },
4998     { "vpshuflw",       { XM, EXx, Ib }, 0 },
4999   },
5000
5001   /* PREFIX_VEX_0F71_REG_2 */
5002   {
5003     { Bad_Opcode },
5004     { Bad_Opcode },
5005     { "vpsrlw",         { Vex, XS, Ib }, 0 },
5006   },
5007
5008   /* PREFIX_VEX_0F71_REG_4 */
5009   {
5010     { Bad_Opcode },
5011     { Bad_Opcode },
5012     { "vpsraw",         { Vex, XS, Ib }, 0 },
5013   },
5014
5015   /* PREFIX_VEX_0F71_REG_6 */
5016   {
5017     { Bad_Opcode },
5018     { Bad_Opcode },
5019     { "vpsllw",         { Vex, XS, Ib }, 0 },
5020   },
5021
5022   /* PREFIX_VEX_0F72_REG_2 */
5023   {
5024     { Bad_Opcode },
5025     { Bad_Opcode },
5026     { "vpsrld",         { Vex, XS, Ib }, 0 },
5027   },
5028
5029   /* PREFIX_VEX_0F72_REG_4 */
5030   {
5031     { Bad_Opcode },
5032     { Bad_Opcode },
5033     { "vpsrad",         { Vex, XS, Ib }, 0 },
5034   },
5035
5036   /* PREFIX_VEX_0F72_REG_6 */
5037   {
5038     { Bad_Opcode },
5039     { Bad_Opcode },
5040     { "vpslld",         { Vex, XS, Ib }, 0 },
5041   },
5042
5043   /* PREFIX_VEX_0F73_REG_2 */
5044   {
5045     { Bad_Opcode },
5046     { Bad_Opcode },
5047     { "vpsrlq",         { Vex, XS, Ib }, 0 },
5048   },
5049
5050   /* PREFIX_VEX_0F73_REG_3 */
5051   {
5052     { Bad_Opcode },
5053     { Bad_Opcode },
5054     { "vpsrldq",        { Vex, XS, Ib }, 0 },
5055   },
5056
5057   /* PREFIX_VEX_0F73_REG_6 */
5058   {
5059     { Bad_Opcode },
5060     { Bad_Opcode },
5061     { "vpsllq",         { Vex, XS, Ib }, 0 },
5062   },
5063
5064   /* PREFIX_VEX_0F73_REG_7 */
5065   {
5066     { Bad_Opcode },
5067     { Bad_Opcode },
5068     { "vpslldq",        { Vex, XS, Ib }, 0 },
5069   },
5070
5071   /* PREFIX_VEX_0F74 */
5072   {
5073     { Bad_Opcode },
5074     { Bad_Opcode },
5075     { "vpcmpeqb",       { XM, Vex, EXx }, 0 },
5076   },
5077
5078   /* PREFIX_VEX_0F75 */
5079   {
5080     { Bad_Opcode },
5081     { Bad_Opcode },
5082     { "vpcmpeqw",       { XM, Vex, EXx }, 0 },
5083   },
5084
5085   /* PREFIX_VEX_0F76 */
5086   {
5087     { Bad_Opcode },
5088     { Bad_Opcode },
5089     { "vpcmpeqd",       { XM, Vex, EXx }, 0 },
5090   },
5091
5092   /* PREFIX_VEX_0F77 */
5093   {
5094     { VEX_LEN_TABLE (VEX_LEN_0F77_P_0) },
5095   },
5096
5097   /* PREFIX_VEX_0F7C */
5098   {
5099     { Bad_Opcode },
5100     { Bad_Opcode },
5101     { "vhaddpd",        { XM, Vex, EXx }, 0 },
5102     { "vhaddps",        { XM, Vex, EXx }, 0 },
5103   },
5104
5105   /* PREFIX_VEX_0F7D */
5106   {
5107     { Bad_Opcode },
5108     { Bad_Opcode },
5109     { "vhsubpd",        { XM, Vex, EXx }, 0 },
5110     { "vhsubps",        { XM, Vex, EXx }, 0 },
5111   },
5112
5113   /* PREFIX_VEX_0F7E */
5114   {
5115     { Bad_Opcode },
5116     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
5117     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
5118   },
5119
5120   /* PREFIX_VEX_0F7F */
5121   {
5122     { Bad_Opcode },
5123     { "vmovdqu",        { EXxS, XM }, 0 },
5124     { "vmovdqa",        { EXxS, XM }, 0 },
5125   },
5126
5127   /* PREFIX_VEX_0F90 */
5128   {
5129     { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
5130     { Bad_Opcode },
5131     { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
5132   },
5133
5134   /* PREFIX_VEX_0F91 */
5135   {
5136     { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
5137     { Bad_Opcode },
5138     { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
5139   },
5140
5141   /* PREFIX_VEX_0F92 */
5142   {
5143     { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
5144     { Bad_Opcode },
5145     { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
5146     { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
5147   },
5148
5149   /* PREFIX_VEX_0F93 */
5150   {
5151     { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
5152     { Bad_Opcode },
5153     { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
5154     { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
5155   },
5156
5157   /* PREFIX_VEX_0F98 */
5158   {
5159     { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
5160     { Bad_Opcode },
5161     { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
5162   },
5163
5164   /* PREFIX_VEX_0F99 */
5165   {
5166     { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5167     { Bad_Opcode },
5168     { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5169   },
5170
5171   /* PREFIX_VEX_0FC2 */
5172   {
5173     { "vcmpps",         { XM, Vex, EXx, VCMP }, 0 },
5174     { "vcmpss",         { XMScalar, VexScalar, EXdScalar, VCMP }, 0 },
5175     { "vcmppd",         { XM, Vex, EXx, VCMP }, 0 },
5176     { "vcmpsd",         { XMScalar, VexScalar, EXqScalar, VCMP }, 0 },
5177   },
5178
5179   /* PREFIX_VEX_0FC4 */
5180   {
5181     { Bad_Opcode },
5182     { Bad_Opcode },
5183     { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5184   },
5185
5186   /* PREFIX_VEX_0FC5 */
5187   {
5188     { Bad_Opcode },
5189     { Bad_Opcode },
5190     { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5191   },
5192
5193   /* PREFIX_VEX_0FD0 */
5194   {
5195     { Bad_Opcode },
5196     { Bad_Opcode },
5197     { "vaddsubpd",      { XM, Vex, EXx }, 0 },
5198     { "vaddsubps",      { XM, Vex, EXx }, 0 },
5199   },
5200
5201   /* PREFIX_VEX_0FD1 */
5202   {
5203     { Bad_Opcode },
5204     { Bad_Opcode },
5205     { "vpsrlw",         { XM, Vex, EXxmm }, 0 },
5206   },
5207
5208   /* PREFIX_VEX_0FD2 */
5209   {
5210     { Bad_Opcode },
5211     { Bad_Opcode },
5212     { "vpsrld",         { XM, Vex, EXxmm }, 0 },
5213   },
5214
5215   /* PREFIX_VEX_0FD3 */
5216   {
5217     { Bad_Opcode },
5218     { Bad_Opcode },
5219     { "vpsrlq",         { XM, Vex, EXxmm }, 0 },
5220   },
5221
5222   /* PREFIX_VEX_0FD4 */
5223   {
5224     { Bad_Opcode },
5225     { Bad_Opcode },
5226     { "vpaddq",         { XM, Vex, EXx }, 0 },
5227   },
5228
5229   /* PREFIX_VEX_0FD5 */
5230   {
5231     { Bad_Opcode },
5232     { Bad_Opcode },
5233     { "vpmullw",        { XM, Vex, EXx }, 0 },
5234   },
5235
5236   /* PREFIX_VEX_0FD6 */
5237   {
5238     { Bad_Opcode },
5239     { Bad_Opcode },
5240     { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5241   },
5242
5243   /* PREFIX_VEX_0FD7 */
5244   {
5245     { Bad_Opcode },
5246     { Bad_Opcode },
5247     { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5248   },
5249
5250   /* PREFIX_VEX_0FD8 */
5251   {
5252     { Bad_Opcode },
5253     { Bad_Opcode },
5254     { "vpsubusb",       { XM, Vex, EXx }, 0 },
5255   },
5256
5257   /* PREFIX_VEX_0FD9 */
5258   {
5259     { Bad_Opcode },
5260     { Bad_Opcode },
5261     { "vpsubusw",       { XM, Vex, EXx }, 0 },
5262   },
5263
5264   /* PREFIX_VEX_0FDA */
5265   {
5266     { Bad_Opcode },
5267     { Bad_Opcode },
5268     { "vpminub",        { XM, Vex, EXx }, 0 },
5269   },
5270
5271   /* PREFIX_VEX_0FDB */
5272   {
5273     { Bad_Opcode },
5274     { Bad_Opcode },
5275     { "vpand",          { XM, Vex, EXx }, 0 },
5276   },
5277
5278   /* PREFIX_VEX_0FDC */
5279   {
5280     { Bad_Opcode },
5281     { Bad_Opcode },
5282     { "vpaddusb",       { XM, Vex, EXx }, 0 },
5283   },
5284
5285   /* PREFIX_VEX_0FDD */
5286   {
5287     { Bad_Opcode },
5288     { Bad_Opcode },
5289     { "vpaddusw",       { XM, Vex, EXx }, 0 },
5290   },
5291
5292   /* PREFIX_VEX_0FDE */
5293   {
5294     { Bad_Opcode },
5295     { Bad_Opcode },
5296     { "vpmaxub",        { XM, Vex, EXx }, 0 },
5297   },
5298
5299   /* PREFIX_VEX_0FDF */
5300   {
5301     { Bad_Opcode },
5302     { Bad_Opcode },
5303     { "vpandn",         { XM, Vex, EXx }, 0 },
5304   },
5305
5306   /* PREFIX_VEX_0FE0 */
5307   {
5308     { Bad_Opcode },
5309     { Bad_Opcode },
5310     { "vpavgb",         { XM, Vex, EXx }, 0 },
5311   },
5312
5313   /* PREFIX_VEX_0FE1 */
5314   {
5315     { Bad_Opcode },
5316     { Bad_Opcode },
5317     { "vpsraw",         { XM, Vex, EXxmm }, 0 },
5318   },
5319
5320   /* PREFIX_VEX_0FE2 */
5321   {
5322     { Bad_Opcode },
5323     { Bad_Opcode },
5324     { "vpsrad",         { XM, Vex, EXxmm }, 0 },
5325   },
5326
5327   /* PREFIX_VEX_0FE3 */
5328   {
5329     { Bad_Opcode },
5330     { Bad_Opcode },
5331     { "vpavgw",         { XM, Vex, EXx }, 0 },
5332   },
5333
5334   /* PREFIX_VEX_0FE4 */
5335   {
5336     { Bad_Opcode },
5337     { Bad_Opcode },
5338     { "vpmulhuw",       { XM, Vex, EXx }, 0 },
5339   },
5340
5341   /* PREFIX_VEX_0FE5 */
5342   {
5343     { Bad_Opcode },
5344     { Bad_Opcode },
5345     { "vpmulhw",        { XM, Vex, EXx }, 0 },
5346   },
5347
5348   /* PREFIX_VEX_0FE6 */
5349   {
5350     { Bad_Opcode },
5351     { "vcvtdq2pd",      { XM, EXxmmq }, 0 },
5352     { "vcvttpd2dq%XY",  { XMM, EXx }, 0 },
5353     { "vcvtpd2dq%XY",   { XMM, EXx }, 0 },
5354   },
5355
5356   /* PREFIX_VEX_0FE7 */
5357   {
5358     { Bad_Opcode },
5359     { Bad_Opcode },
5360     { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5361   },
5362
5363   /* PREFIX_VEX_0FE8 */
5364   {
5365     { Bad_Opcode },
5366     { Bad_Opcode },
5367     { "vpsubsb",        { XM, Vex, EXx }, 0 },
5368   },
5369
5370   /* PREFIX_VEX_0FE9 */
5371   {
5372     { Bad_Opcode },
5373     { Bad_Opcode },
5374     { "vpsubsw",        { XM, Vex, EXx }, 0 },
5375   },
5376
5377   /* PREFIX_VEX_0FEA */
5378   {
5379     { Bad_Opcode },
5380     { Bad_Opcode },
5381     { "vpminsw",        { XM, Vex, EXx }, 0 },
5382   },
5383
5384   /* PREFIX_VEX_0FEB */
5385   {
5386     { Bad_Opcode },
5387     { Bad_Opcode },
5388     { "vpor",           { XM, Vex, EXx }, 0 },
5389   },
5390
5391   /* PREFIX_VEX_0FEC */
5392   {
5393     { Bad_Opcode },
5394     { Bad_Opcode },
5395     { "vpaddsb",        { XM, Vex, EXx }, 0 },
5396   },
5397
5398   /* PREFIX_VEX_0FED */
5399   {
5400     { Bad_Opcode },
5401     { Bad_Opcode },
5402     { "vpaddsw",        { XM, Vex, EXx }, 0 },
5403   },
5404
5405   /* PREFIX_VEX_0FEE */
5406   {
5407     { Bad_Opcode },
5408     { Bad_Opcode },
5409     { "vpmaxsw",        { XM, Vex, EXx }, 0 },
5410   },
5411
5412   /* PREFIX_VEX_0FEF */
5413   {
5414     { Bad_Opcode },
5415     { Bad_Opcode },
5416     { "vpxor",          { XM, Vex, EXx }, 0 },
5417   },
5418
5419   /* PREFIX_VEX_0FF0 */
5420   {
5421     { Bad_Opcode },
5422     { Bad_Opcode },
5423     { Bad_Opcode },
5424     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5425   },
5426
5427   /* PREFIX_VEX_0FF1 */
5428   {
5429     { Bad_Opcode },
5430     { Bad_Opcode },
5431     { "vpsllw",         { XM, Vex, EXxmm }, 0 },
5432   },
5433
5434   /* PREFIX_VEX_0FF2 */
5435   {
5436     { Bad_Opcode },
5437     { Bad_Opcode },
5438     { "vpslld",         { XM, Vex, EXxmm }, 0 },
5439   },
5440
5441   /* PREFIX_VEX_0FF3 */
5442   {
5443     { Bad_Opcode },
5444     { Bad_Opcode },
5445     { "vpsllq",         { XM, Vex, EXxmm }, 0 },
5446   },
5447
5448   /* PREFIX_VEX_0FF4 */
5449   {
5450     { Bad_Opcode },
5451     { Bad_Opcode },
5452     { "vpmuludq",       { XM, Vex, EXx }, 0 },
5453   },
5454
5455   /* PREFIX_VEX_0FF5 */
5456   {
5457     { Bad_Opcode },
5458     { Bad_Opcode },
5459     { "vpmaddwd",       { XM, Vex, EXx }, 0 },
5460   },
5461
5462   /* PREFIX_VEX_0FF6 */
5463   {
5464     { Bad_Opcode },
5465     { Bad_Opcode },
5466     { "vpsadbw",        { XM, Vex, EXx }, 0 },
5467   },
5468
5469   /* PREFIX_VEX_0FF7 */
5470   {
5471     { Bad_Opcode },
5472     { Bad_Opcode },
5473     { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5474   },
5475
5476   /* PREFIX_VEX_0FF8 */
5477   {
5478     { Bad_Opcode },
5479     { Bad_Opcode },
5480     { "vpsubb",         { XM, Vex, EXx }, 0 },
5481   },
5482
5483   /* PREFIX_VEX_0FF9 */
5484   {
5485     { Bad_Opcode },
5486     { Bad_Opcode },
5487     { "vpsubw",         { XM, Vex, EXx }, 0 },
5488   },
5489
5490   /* PREFIX_VEX_0FFA */
5491   {
5492     { Bad_Opcode },
5493     { Bad_Opcode },
5494     { "vpsubd",         { XM, Vex, EXx }, 0 },
5495   },
5496
5497   /* PREFIX_VEX_0FFB */
5498   {
5499     { Bad_Opcode },
5500     { Bad_Opcode },
5501     { "vpsubq",         { XM, Vex, EXx }, 0 },
5502   },
5503
5504   /* PREFIX_VEX_0FFC */
5505   {
5506     { Bad_Opcode },
5507     { Bad_Opcode },
5508     { "vpaddb",         { XM, Vex, EXx }, 0 },
5509   },
5510
5511   /* PREFIX_VEX_0FFD */
5512   {
5513     { Bad_Opcode },
5514     { Bad_Opcode },
5515     { "vpaddw",         { XM, Vex, EXx }, 0 },
5516   },
5517
5518   /* PREFIX_VEX_0FFE */
5519   {
5520     { Bad_Opcode },
5521     { Bad_Opcode },
5522     { "vpaddd",         { XM, Vex, EXx }, 0 },
5523   },
5524
5525   /* PREFIX_VEX_0F3800 */
5526   {
5527     { Bad_Opcode },
5528     { Bad_Opcode },
5529     { "vpshufb",        { XM, Vex, EXx }, 0 },
5530   },
5531
5532   /* PREFIX_VEX_0F3801 */
5533   {
5534     { Bad_Opcode },
5535     { Bad_Opcode },
5536     { "vphaddw",        { XM, Vex, EXx }, 0 },
5537   },
5538
5539   /* PREFIX_VEX_0F3802 */
5540   {
5541     { Bad_Opcode },
5542     { Bad_Opcode },
5543     { "vphaddd",        { XM, Vex, EXx }, 0 },
5544   },
5545
5546   /* PREFIX_VEX_0F3803 */
5547   {
5548     { Bad_Opcode },
5549     { Bad_Opcode },
5550     { "vphaddsw",       { XM, Vex, EXx }, 0 },
5551   },
5552
5553   /* PREFIX_VEX_0F3804 */
5554   {
5555     { Bad_Opcode },
5556     { Bad_Opcode },
5557     { "vpmaddubsw",     { XM, Vex, EXx }, 0 },
5558   },
5559
5560   /* PREFIX_VEX_0F3805 */
5561   {
5562     { Bad_Opcode },
5563     { Bad_Opcode },
5564     { "vphsubw",        { XM, Vex, EXx }, 0 },
5565   },
5566
5567   /* PREFIX_VEX_0F3806 */
5568   {
5569     { Bad_Opcode },
5570     { Bad_Opcode },
5571     { "vphsubd",        { XM, Vex, EXx }, 0 },
5572   },
5573
5574   /* PREFIX_VEX_0F3807 */
5575   {
5576     { Bad_Opcode },
5577     { Bad_Opcode },
5578     { "vphsubsw",       { XM, Vex, EXx }, 0 },
5579   },
5580
5581   /* PREFIX_VEX_0F3808 */
5582   {
5583     { Bad_Opcode },
5584     { Bad_Opcode },
5585     { "vpsignb",        { XM, Vex, EXx }, 0 },
5586   },
5587
5588   /* PREFIX_VEX_0F3809 */
5589   {
5590     { Bad_Opcode },
5591     { Bad_Opcode },
5592     { "vpsignw",        { XM, Vex, EXx }, 0 },
5593   },
5594
5595   /* PREFIX_VEX_0F380A */
5596   {
5597     { Bad_Opcode },
5598     { Bad_Opcode },
5599     { "vpsignd",        { XM, Vex, EXx }, 0 },
5600   },
5601
5602   /* PREFIX_VEX_0F380B */
5603   {
5604     { Bad_Opcode },
5605     { Bad_Opcode },
5606     { "vpmulhrsw",      { XM, Vex, EXx }, 0 },
5607   },
5608
5609   /* PREFIX_VEX_0F380C */
5610   {
5611     { Bad_Opcode },
5612     { Bad_Opcode },
5613     { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5614   },
5615
5616   /* PREFIX_VEX_0F380D */
5617   {
5618     { Bad_Opcode },
5619     { Bad_Opcode },
5620     { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5621   },
5622
5623   /* PREFIX_VEX_0F380E */
5624   {
5625     { Bad_Opcode },
5626     { Bad_Opcode },
5627     { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5628   },
5629
5630   /* PREFIX_VEX_0F380F */
5631   {
5632     { Bad_Opcode },
5633     { Bad_Opcode },
5634     { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5635   },
5636
5637   /* PREFIX_VEX_0F3813 */
5638   {
5639     { Bad_Opcode },
5640     { Bad_Opcode },
5641     { "vcvtph2ps", { XM, EXxmmq }, 0 },
5642   },
5643
5644   /* PREFIX_VEX_0F3816 */
5645   {
5646     { Bad_Opcode },
5647     { Bad_Opcode },
5648     { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5649   },
5650
5651   /* PREFIX_VEX_0F3817 */
5652   {
5653     { Bad_Opcode },
5654     { Bad_Opcode },
5655     { "vptest",         { XM, EXx }, 0 },
5656   },
5657
5658   /* PREFIX_VEX_0F3818 */
5659   {
5660     { Bad_Opcode },
5661     { Bad_Opcode },
5662     { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5663   },
5664
5665   /* PREFIX_VEX_0F3819 */
5666   {
5667     { Bad_Opcode },
5668     { Bad_Opcode },
5669     { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5670   },
5671
5672   /* PREFIX_VEX_0F381A */
5673   {
5674     { Bad_Opcode },
5675     { Bad_Opcode },
5676     { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5677   },
5678
5679   /* PREFIX_VEX_0F381C */
5680   {
5681     { Bad_Opcode },
5682     { Bad_Opcode },
5683     { "vpabsb",         { XM, EXx }, 0 },
5684   },
5685
5686   /* PREFIX_VEX_0F381D */
5687   {
5688     { Bad_Opcode },
5689     { Bad_Opcode },
5690     { "vpabsw",         { XM, EXx }, 0 },
5691   },
5692
5693   /* PREFIX_VEX_0F381E */
5694   {
5695     { Bad_Opcode },
5696     { Bad_Opcode },
5697     { "vpabsd",         { XM, EXx }, 0 },
5698   },
5699
5700   /* PREFIX_VEX_0F3820 */
5701   {
5702     { Bad_Opcode },
5703     { Bad_Opcode },
5704     { "vpmovsxbw",      { XM, EXxmmq }, 0 },
5705   },
5706
5707   /* PREFIX_VEX_0F3821 */
5708   {
5709     { Bad_Opcode },
5710     { Bad_Opcode },
5711     { "vpmovsxbd",      { XM, EXxmmqd }, 0 },
5712   },
5713
5714   /* PREFIX_VEX_0F3822 */
5715   {
5716     { Bad_Opcode },
5717     { Bad_Opcode },
5718     { "vpmovsxbq",      { XM, EXxmmdw }, 0 },
5719   },
5720
5721   /* PREFIX_VEX_0F3823 */
5722   {
5723     { Bad_Opcode },
5724     { Bad_Opcode },
5725     { "vpmovsxwd",      { XM, EXxmmq }, 0 },
5726   },
5727
5728   /* PREFIX_VEX_0F3824 */
5729   {
5730     { Bad_Opcode },
5731     { Bad_Opcode },
5732     { "vpmovsxwq",      { XM, EXxmmqd }, 0 },
5733   },
5734
5735   /* PREFIX_VEX_0F3825 */
5736   {
5737     { Bad_Opcode },
5738     { Bad_Opcode },
5739     { "vpmovsxdq",      { XM, EXxmmq }, 0 },
5740   },
5741
5742   /* PREFIX_VEX_0F3828 */
5743   {
5744     { Bad_Opcode },
5745     { Bad_Opcode },
5746     { "vpmuldq",        { XM, Vex, EXx }, 0 },
5747   },
5748
5749   /* PREFIX_VEX_0F3829 */
5750   {
5751     { Bad_Opcode },
5752     { Bad_Opcode },
5753     { "vpcmpeqq",       { XM, Vex, EXx }, 0 },
5754   },
5755
5756   /* PREFIX_VEX_0F382A */
5757   {
5758     { Bad_Opcode },
5759     { Bad_Opcode },
5760     { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5761   },
5762
5763   /* PREFIX_VEX_0F382B */
5764   {
5765     { Bad_Opcode },
5766     { Bad_Opcode },
5767     { "vpackusdw",      { XM, Vex, EXx }, 0 },
5768   },
5769
5770   /* PREFIX_VEX_0F382C */
5771   {
5772     { Bad_Opcode },
5773     { Bad_Opcode },
5774      { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5775   },
5776
5777   /* PREFIX_VEX_0F382D */
5778   {
5779     { Bad_Opcode },
5780     { Bad_Opcode },
5781      { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5782   },
5783
5784   /* PREFIX_VEX_0F382E */
5785   {
5786     { Bad_Opcode },
5787     { Bad_Opcode },
5788      { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5789   },
5790
5791   /* PREFIX_VEX_0F382F */
5792   {
5793     { Bad_Opcode },
5794     { Bad_Opcode },
5795      { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5796   },
5797
5798   /* PREFIX_VEX_0F3830 */
5799   {
5800     { Bad_Opcode },
5801     { Bad_Opcode },
5802     { "vpmovzxbw",      { XM, EXxmmq }, 0 },
5803   },
5804
5805   /* PREFIX_VEX_0F3831 */
5806   {
5807     { Bad_Opcode },
5808     { Bad_Opcode },
5809     { "vpmovzxbd",      { XM, EXxmmqd }, 0 },
5810   },
5811
5812   /* PREFIX_VEX_0F3832 */
5813   {
5814     { Bad_Opcode },
5815     { Bad_Opcode },
5816     { "vpmovzxbq",      { XM, EXxmmdw }, 0 },
5817   },
5818
5819   /* PREFIX_VEX_0F3833 */
5820   {
5821     { Bad_Opcode },
5822     { Bad_Opcode },
5823     { "vpmovzxwd",      { XM, EXxmmq }, 0 },
5824   },
5825
5826   /* PREFIX_VEX_0F3834 */
5827   {
5828     { Bad_Opcode },
5829     { Bad_Opcode },
5830     { "vpmovzxwq",      { XM, EXxmmqd }, 0 },
5831   },
5832
5833   /* PREFIX_VEX_0F3835 */
5834   {
5835     { Bad_Opcode },
5836     { Bad_Opcode },
5837     { "vpmovzxdq",      { XM, EXxmmq }, 0 },
5838   },
5839
5840   /* PREFIX_VEX_0F3836 */
5841   {
5842     { Bad_Opcode },
5843     { Bad_Opcode },
5844     { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5845   },
5846
5847   /* PREFIX_VEX_0F3837 */
5848   {
5849     { Bad_Opcode },
5850     { Bad_Opcode },
5851     { "vpcmpgtq",       { XM, Vex, EXx }, 0 },
5852   },
5853
5854   /* PREFIX_VEX_0F3838 */
5855   {
5856     { Bad_Opcode },
5857     { Bad_Opcode },
5858     { "vpminsb",        { XM, Vex, EXx }, 0 },
5859   },
5860
5861   /* PREFIX_VEX_0F3839 */
5862   {
5863     { Bad_Opcode },
5864     { Bad_Opcode },
5865     { "vpminsd",        { XM, Vex, EXx }, 0 },
5866   },
5867
5868   /* PREFIX_VEX_0F383A */
5869   {
5870     { Bad_Opcode },
5871     { Bad_Opcode },
5872     { "vpminuw",        { XM, Vex, EXx }, 0 },
5873   },
5874
5875   /* PREFIX_VEX_0F383B */
5876   {
5877     { Bad_Opcode },
5878     { Bad_Opcode },
5879     { "vpminud",        { XM, Vex, EXx }, 0 },
5880   },
5881
5882   /* PREFIX_VEX_0F383C */
5883   {
5884     { Bad_Opcode },
5885     { Bad_Opcode },
5886     { "vpmaxsb",        { XM, Vex, EXx }, 0 },
5887   },
5888
5889   /* PREFIX_VEX_0F383D */
5890   {
5891     { Bad_Opcode },
5892     { Bad_Opcode },
5893     { "vpmaxsd",        { XM, Vex, EXx }, 0 },
5894   },
5895
5896   /* PREFIX_VEX_0F383E */
5897   {
5898     { Bad_Opcode },
5899     { Bad_Opcode },
5900     { "vpmaxuw",        { XM, Vex, EXx }, 0 },
5901   },
5902
5903   /* PREFIX_VEX_0F383F */
5904   {
5905     { Bad_Opcode },
5906     { Bad_Opcode },
5907     { "vpmaxud",        { XM, Vex, EXx }, 0 },
5908   },
5909
5910   /* PREFIX_VEX_0F3840 */
5911   {
5912     { Bad_Opcode },
5913     { Bad_Opcode },
5914     { "vpmulld",        { XM, Vex, EXx }, 0 },
5915   },
5916
5917   /* PREFIX_VEX_0F3841 */
5918   {
5919     { Bad_Opcode },
5920     { Bad_Opcode },
5921     { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
5922   },
5923
5924   /* PREFIX_VEX_0F3845 */
5925   {
5926     { Bad_Opcode },
5927     { Bad_Opcode },
5928     { "vpsrlv%LW", { XM, Vex, EXx }, 0 },
5929   },
5930
5931   /* PREFIX_VEX_0F3846 */
5932   {
5933     { Bad_Opcode },
5934     { Bad_Opcode },
5935     { VEX_W_TABLE (VEX_W_0F3846_P_2) },
5936   },
5937
5938   /* PREFIX_VEX_0F3847 */
5939   {
5940     { Bad_Opcode },
5941     { Bad_Opcode },
5942     { "vpsllv%LW", { XM, Vex, EXx }, 0 },
5943   },
5944
5945   /* PREFIX_VEX_0F3858 */
5946   {
5947     { Bad_Opcode },
5948     { Bad_Opcode },
5949     { VEX_W_TABLE (VEX_W_0F3858_P_2) },
5950   },
5951
5952   /* PREFIX_VEX_0F3859 */
5953   {
5954     { Bad_Opcode },
5955     { Bad_Opcode },
5956     { VEX_W_TABLE (VEX_W_0F3859_P_2) },
5957   },
5958
5959   /* PREFIX_VEX_0F385A */
5960   {
5961     { Bad_Opcode },
5962     { Bad_Opcode },
5963     { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
5964   },
5965
5966   /* PREFIX_VEX_0F3878 */
5967   {
5968     { Bad_Opcode },
5969     { Bad_Opcode },
5970     { VEX_W_TABLE (VEX_W_0F3878_P_2) },
5971   },
5972
5973   /* PREFIX_VEX_0F3879 */
5974   {
5975     { Bad_Opcode },
5976     { Bad_Opcode },
5977     { VEX_W_TABLE (VEX_W_0F3879_P_2) },
5978   },
5979
5980   /* PREFIX_VEX_0F388C */
5981   {
5982     { Bad_Opcode },
5983     { Bad_Opcode },
5984     { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
5985   },
5986
5987   /* PREFIX_VEX_0F388E */
5988   {
5989     { Bad_Opcode },
5990     { Bad_Opcode },
5991     { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
5992   },
5993
5994   /* PREFIX_VEX_0F3890 */
5995   {
5996     { Bad_Opcode },
5997     { Bad_Opcode },
5998     { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 },
5999   },
6000
6001   /* PREFIX_VEX_0F3891 */
6002   {
6003     { Bad_Opcode },
6004     { Bad_Opcode },
6005     { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6006   },
6007
6008   /* PREFIX_VEX_0F3892 */
6009   {
6010     { Bad_Opcode },
6011     { Bad_Opcode },
6012     { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 },
6013   },
6014
6015   /* PREFIX_VEX_0F3893 */
6016   {
6017     { Bad_Opcode },
6018     { Bad_Opcode },
6019     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6020   },
6021
6022   /* PREFIX_VEX_0F3896 */
6023   {
6024     { Bad_Opcode },
6025     { Bad_Opcode },
6026     { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 },
6027   },
6028
6029   /* PREFIX_VEX_0F3897 */
6030   {
6031     { Bad_Opcode },
6032     { Bad_Opcode },
6033     { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 },
6034   },
6035
6036   /* PREFIX_VEX_0F3898 */
6037   {
6038     { Bad_Opcode },
6039     { Bad_Opcode },
6040     { "vfmadd132p%XW", { XM, Vex, EXx }, 0 },
6041   },
6042
6043   /* PREFIX_VEX_0F3899 */
6044   {
6045     { Bad_Opcode },
6046     { Bad_Opcode },
6047     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6048   },
6049
6050   /* PREFIX_VEX_0F389A */
6051   {
6052     { Bad_Opcode },
6053     { Bad_Opcode },
6054     { "vfmsub132p%XW", { XM, Vex, EXx }, 0 },
6055   },
6056
6057   /* PREFIX_VEX_0F389B */
6058   {
6059     { Bad_Opcode },
6060     { Bad_Opcode },
6061     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6062   },
6063
6064   /* PREFIX_VEX_0F389C */
6065   {
6066     { Bad_Opcode },
6067     { Bad_Opcode },
6068     { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 },
6069   },
6070
6071   /* PREFIX_VEX_0F389D */
6072   {
6073     { Bad_Opcode },
6074     { Bad_Opcode },
6075     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6076   },
6077
6078   /* PREFIX_VEX_0F389E */
6079   {
6080     { Bad_Opcode },
6081     { Bad_Opcode },
6082     { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 },
6083   },
6084
6085   /* PREFIX_VEX_0F389F */
6086   {
6087     { Bad_Opcode },
6088     { Bad_Opcode },
6089     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6090   },
6091
6092   /* PREFIX_VEX_0F38A6 */
6093   {
6094     { Bad_Opcode },
6095     { Bad_Opcode },
6096     { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 },
6097     { Bad_Opcode },
6098   },
6099
6100   /* PREFIX_VEX_0F38A7 */
6101   {
6102     { Bad_Opcode },
6103     { Bad_Opcode },
6104     { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 },
6105   },
6106
6107   /* PREFIX_VEX_0F38A8 */
6108   {
6109     { Bad_Opcode },
6110     { Bad_Opcode },
6111     { "vfmadd213p%XW", { XM, Vex, EXx }, 0 },
6112   },
6113
6114   /* PREFIX_VEX_0F38A9 */
6115   {
6116     { Bad_Opcode },
6117     { Bad_Opcode },
6118     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6119   },
6120
6121   /* PREFIX_VEX_0F38AA */
6122   {
6123     { Bad_Opcode },
6124     { Bad_Opcode },
6125     { "vfmsub213p%XW", { XM, Vex, EXx }, 0 },
6126   },
6127
6128   /* PREFIX_VEX_0F38AB */
6129   {
6130     { Bad_Opcode },
6131     { Bad_Opcode },
6132     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6133   },
6134
6135   /* PREFIX_VEX_0F38AC */
6136   {
6137     { Bad_Opcode },
6138     { Bad_Opcode },
6139     { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 },
6140   },
6141
6142   /* PREFIX_VEX_0F38AD */
6143   {
6144     { Bad_Opcode },
6145     { Bad_Opcode },
6146     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6147   },
6148
6149   /* PREFIX_VEX_0F38AE */
6150   {
6151     { Bad_Opcode },
6152     { Bad_Opcode },
6153     { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 },
6154   },
6155
6156   /* PREFIX_VEX_0F38AF */
6157   {
6158     { Bad_Opcode },
6159     { Bad_Opcode },
6160     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6161   },
6162
6163   /* PREFIX_VEX_0F38B6 */
6164   {
6165     { Bad_Opcode },
6166     { Bad_Opcode },
6167     { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 },
6168   },
6169
6170   /* PREFIX_VEX_0F38B7 */
6171   {
6172     { Bad_Opcode },
6173     { Bad_Opcode },
6174     { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 },
6175   },
6176
6177   /* PREFIX_VEX_0F38B8 */
6178   {
6179     { Bad_Opcode },
6180     { Bad_Opcode },
6181     { "vfmadd231p%XW", { XM, Vex, EXx }, 0 },
6182   },
6183
6184   /* PREFIX_VEX_0F38B9 */
6185   {
6186     { Bad_Opcode },
6187     { Bad_Opcode },
6188     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6189   },
6190
6191   /* PREFIX_VEX_0F38BA */
6192   {
6193     { Bad_Opcode },
6194     { Bad_Opcode },
6195     { "vfmsub231p%XW", { XM, Vex, EXx }, 0 },
6196   },
6197
6198   /* PREFIX_VEX_0F38BB */
6199   {
6200     { Bad_Opcode },
6201     { Bad_Opcode },
6202     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6203   },
6204
6205   /* PREFIX_VEX_0F38BC */
6206   {
6207     { Bad_Opcode },
6208     { Bad_Opcode },
6209     { "vfnmadd231p%XW", { XM, Vex, EXx }, 0 },
6210   },
6211
6212   /* PREFIX_VEX_0F38BD */
6213   {
6214     { Bad_Opcode },
6215     { Bad_Opcode },
6216     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6217   },
6218
6219   /* PREFIX_VEX_0F38BE */
6220   {
6221     { Bad_Opcode },
6222     { Bad_Opcode },
6223     { "vfnmsub231p%XW", { XM, Vex, EXx }, 0 },
6224   },
6225
6226   /* PREFIX_VEX_0F38BF */
6227   {
6228     { Bad_Opcode },
6229     { Bad_Opcode },
6230     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6231   },
6232
6233   /* PREFIX_VEX_0F38CF */
6234   {
6235     { Bad_Opcode },
6236     { Bad_Opcode },
6237     { VEX_W_TABLE (VEX_W_0F38CF_P_2) },
6238   },
6239
6240   /* PREFIX_VEX_0F38DB */
6241   {
6242     { Bad_Opcode },
6243     { Bad_Opcode },
6244     { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6245   },
6246
6247   /* PREFIX_VEX_0F38DC */
6248   {
6249     { Bad_Opcode },
6250     { Bad_Opcode },
6251     { "vaesenc",        { XM, Vex, EXx }, 0 },
6252   },
6253
6254   /* PREFIX_VEX_0F38DD */
6255   {
6256     { Bad_Opcode },
6257     { Bad_Opcode },
6258     { "vaesenclast",    { XM, Vex, EXx }, 0 },
6259   },
6260
6261   /* PREFIX_VEX_0F38DE */
6262   {
6263     { Bad_Opcode },
6264     { Bad_Opcode },
6265     { "vaesdec",        { XM, Vex, EXx }, 0 },
6266   },
6267
6268   /* PREFIX_VEX_0F38DF */
6269   {
6270     { Bad_Opcode },
6271     { Bad_Opcode },
6272     { "vaesdeclast",    { XM, Vex, EXx }, 0 },
6273   },
6274
6275   /* PREFIX_VEX_0F38F2 */
6276   {
6277     { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6278   },
6279
6280   /* PREFIX_VEX_0F38F3_REG_1 */
6281   {
6282     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6283   },
6284
6285   /* PREFIX_VEX_0F38F3_REG_2 */
6286   {
6287     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6288   },
6289
6290   /* PREFIX_VEX_0F38F3_REG_3 */
6291   {
6292     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6293   },
6294
6295   /* PREFIX_VEX_0F38F5 */
6296   {
6297     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6298     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6299     { Bad_Opcode },
6300     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6301   },
6302
6303   /* PREFIX_VEX_0F38F6 */
6304   {
6305     { Bad_Opcode },
6306     { Bad_Opcode },
6307     { Bad_Opcode },
6308     { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6309   },
6310
6311   /* PREFIX_VEX_0F38F7 */
6312   {
6313     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6314     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6315     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6316     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6317   },
6318
6319   /* PREFIX_VEX_0F3A00 */
6320   {
6321     { Bad_Opcode },
6322     { Bad_Opcode },
6323     { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6324   },
6325
6326   /* PREFIX_VEX_0F3A01 */
6327   {
6328     { Bad_Opcode },
6329     { Bad_Opcode },
6330     { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6331   },
6332
6333   /* PREFIX_VEX_0F3A02 */
6334   {
6335     { Bad_Opcode },
6336     { Bad_Opcode },
6337     { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6338   },
6339
6340   /* PREFIX_VEX_0F3A04 */
6341   {
6342     { Bad_Opcode },
6343     { Bad_Opcode },
6344     { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6345   },
6346
6347   /* PREFIX_VEX_0F3A05 */
6348   {
6349     { Bad_Opcode },
6350     { Bad_Opcode },
6351     { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6352   },
6353
6354   /* PREFIX_VEX_0F3A06 */
6355   {
6356     { Bad_Opcode },
6357     { Bad_Opcode },
6358     { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6359   },
6360
6361   /* PREFIX_VEX_0F3A08 */
6362   {
6363     { Bad_Opcode },
6364     { Bad_Opcode },
6365     { "vroundps",       { XM, EXx, Ib }, 0 },
6366   },
6367
6368   /* PREFIX_VEX_0F3A09 */
6369   {
6370     { Bad_Opcode },
6371     { Bad_Opcode },
6372     { "vroundpd",       { XM, EXx, Ib }, 0 },
6373   },
6374
6375   /* PREFIX_VEX_0F3A0A */
6376   {
6377     { Bad_Opcode },
6378     { Bad_Opcode },
6379     { "vroundss",       { XMScalar, VexScalar, EXdScalar, Ib }, 0 },
6380   },
6381
6382   /* PREFIX_VEX_0F3A0B */
6383   {
6384     { Bad_Opcode },
6385     { Bad_Opcode },
6386     { "vroundsd",       { XMScalar, VexScalar, EXqScalar, Ib }, 0 },
6387   },
6388
6389   /* PREFIX_VEX_0F3A0C */
6390   {
6391     { Bad_Opcode },
6392     { Bad_Opcode },
6393     { "vblendps",       { XM, Vex, EXx, Ib }, 0 },
6394   },
6395
6396   /* PREFIX_VEX_0F3A0D */
6397   {
6398     { Bad_Opcode },
6399     { Bad_Opcode },
6400     { "vblendpd",       { XM, Vex, EXx, Ib }, 0 },
6401   },
6402
6403   /* PREFIX_VEX_0F3A0E */
6404   {
6405     { Bad_Opcode },
6406     { Bad_Opcode },
6407     { "vpblendw",       { XM, Vex, EXx, Ib }, 0 },
6408   },
6409
6410   /* PREFIX_VEX_0F3A0F */
6411   {
6412     { Bad_Opcode },
6413     { Bad_Opcode },
6414     { "vpalignr",       { XM, Vex, EXx, Ib }, 0 },
6415   },
6416
6417   /* PREFIX_VEX_0F3A14 */
6418   {
6419     { Bad_Opcode },
6420     { Bad_Opcode },
6421     { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6422   },
6423
6424   /* PREFIX_VEX_0F3A15 */
6425   {
6426     { Bad_Opcode },
6427     { Bad_Opcode },
6428     { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6429   },
6430
6431   /* PREFIX_VEX_0F3A16 */
6432   {
6433     { Bad_Opcode },
6434     { Bad_Opcode },
6435     { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6436   },
6437
6438   /* PREFIX_VEX_0F3A17 */
6439   {
6440     { Bad_Opcode },
6441     { Bad_Opcode },
6442     { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6443   },
6444
6445   /* PREFIX_VEX_0F3A18 */
6446   {
6447     { Bad_Opcode },
6448     { Bad_Opcode },
6449     { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6450   },
6451
6452   /* PREFIX_VEX_0F3A19 */
6453   {
6454     { Bad_Opcode },
6455     { Bad_Opcode },
6456     { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6457   },
6458
6459   /* PREFIX_VEX_0F3A1D */
6460   {
6461     { Bad_Opcode },
6462     { Bad_Opcode },
6463     { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 },
6464   },
6465
6466   /* PREFIX_VEX_0F3A20 */
6467   {
6468     { Bad_Opcode },
6469     { Bad_Opcode },
6470     { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6471   },
6472
6473   /* PREFIX_VEX_0F3A21 */
6474   {
6475     { Bad_Opcode },
6476     { Bad_Opcode },
6477     { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6478   },
6479
6480   /* PREFIX_VEX_0F3A22 */
6481   {
6482     { Bad_Opcode },
6483     { Bad_Opcode },
6484     { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6485   },
6486
6487   /* PREFIX_VEX_0F3A30 */
6488   {
6489     { Bad_Opcode },
6490     { Bad_Opcode },
6491     { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6492   },
6493
6494   /* PREFIX_VEX_0F3A31 */
6495   {
6496     { Bad_Opcode },
6497     { Bad_Opcode },
6498     { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6499   },
6500
6501   /* PREFIX_VEX_0F3A32 */
6502   {
6503     { Bad_Opcode },
6504     { Bad_Opcode },
6505     { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6506   },
6507
6508   /* PREFIX_VEX_0F3A33 */
6509   {
6510     { Bad_Opcode },
6511     { Bad_Opcode },
6512     { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6513   },
6514
6515   /* PREFIX_VEX_0F3A38 */
6516   {
6517     { Bad_Opcode },
6518     { Bad_Opcode },
6519     { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6520   },
6521
6522   /* PREFIX_VEX_0F3A39 */
6523   {
6524     { Bad_Opcode },
6525     { Bad_Opcode },
6526     { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6527   },
6528
6529   /* PREFIX_VEX_0F3A40 */
6530   {
6531     { Bad_Opcode },
6532     { Bad_Opcode },
6533     { "vdpps",          { XM, Vex, EXx, Ib }, 0 },
6534   },
6535
6536   /* PREFIX_VEX_0F3A41 */
6537   {
6538     { Bad_Opcode },
6539     { Bad_Opcode },
6540     { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6541   },
6542
6543   /* PREFIX_VEX_0F3A42 */
6544   {
6545     { Bad_Opcode },
6546     { Bad_Opcode },
6547     { "vmpsadbw",       { XM, Vex, EXx, Ib }, 0 },
6548   },
6549
6550   /* PREFIX_VEX_0F3A44 */
6551   {
6552     { Bad_Opcode },
6553     { Bad_Opcode },
6554     { "vpclmulqdq",     { XM, Vex, EXx, PCLMUL }, 0 },
6555   },
6556
6557   /* PREFIX_VEX_0F3A46 */
6558   {
6559     { Bad_Opcode },
6560     { Bad_Opcode },
6561     { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6562   },
6563
6564   /* PREFIX_VEX_0F3A48 */
6565   {
6566     { Bad_Opcode },
6567     { Bad_Opcode },
6568     { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6569   },
6570
6571   /* PREFIX_VEX_0F3A49 */
6572   {
6573     { Bad_Opcode },
6574     { Bad_Opcode },
6575     { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6576   },
6577
6578   /* PREFIX_VEX_0F3A4A */
6579   {
6580     { Bad_Opcode },
6581     { Bad_Opcode },
6582     { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6583   },
6584
6585   /* PREFIX_VEX_0F3A4B */
6586   {
6587     { Bad_Opcode },
6588     { Bad_Opcode },
6589     { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6590   },
6591
6592   /* PREFIX_VEX_0F3A4C */
6593   {
6594     { Bad_Opcode },
6595     { Bad_Opcode },
6596     { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6597   },
6598
6599   /* PREFIX_VEX_0F3A5C */
6600   {
6601     { Bad_Opcode },
6602     { Bad_Opcode },
6603     { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6604   },
6605
6606   /* PREFIX_VEX_0F3A5D */
6607   {
6608     { Bad_Opcode },
6609     { Bad_Opcode },
6610     { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6611   },
6612
6613   /* PREFIX_VEX_0F3A5E */
6614   {
6615     { Bad_Opcode },
6616     { Bad_Opcode },
6617     { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6618   },
6619
6620   /* PREFIX_VEX_0F3A5F */
6621   {
6622     { Bad_Opcode },
6623     { Bad_Opcode },
6624     { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6625   },
6626
6627   /* PREFIX_VEX_0F3A60 */
6628   {
6629     { Bad_Opcode },
6630     { Bad_Opcode },
6631     { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6632     { Bad_Opcode },
6633   },
6634
6635   /* PREFIX_VEX_0F3A61 */
6636   {
6637     { Bad_Opcode },
6638     { Bad_Opcode },
6639     { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6640   },
6641
6642   /* PREFIX_VEX_0F3A62 */
6643   {
6644     { Bad_Opcode },
6645     { Bad_Opcode },
6646     { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6647   },
6648
6649   /* PREFIX_VEX_0F3A63 */
6650   {
6651     { Bad_Opcode },
6652     { Bad_Opcode },
6653     { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6654   },
6655
6656   /* PREFIX_VEX_0F3A68 */
6657   {
6658     { Bad_Opcode },
6659     { Bad_Opcode },
6660     { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6661   },
6662
6663   /* PREFIX_VEX_0F3A69 */
6664   {
6665     { Bad_Opcode },
6666     { Bad_Opcode },
6667     { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6668   },
6669
6670   /* PREFIX_VEX_0F3A6A */
6671   {
6672     { Bad_Opcode },
6673     { Bad_Opcode },
6674     { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6675   },
6676
6677   /* PREFIX_VEX_0F3A6B */
6678   {
6679     { Bad_Opcode },
6680     { Bad_Opcode },
6681     { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6682   },
6683
6684   /* PREFIX_VEX_0F3A6C */
6685   {
6686     { Bad_Opcode },
6687     { Bad_Opcode },
6688     { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6689   },
6690
6691   /* PREFIX_VEX_0F3A6D */
6692   {
6693     { Bad_Opcode },
6694     { Bad_Opcode },
6695     { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6696   },
6697
6698   /* PREFIX_VEX_0F3A6E */
6699   {
6700     { Bad_Opcode },
6701     { Bad_Opcode },
6702     { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6703   },
6704
6705   /* PREFIX_VEX_0F3A6F */
6706   {
6707     { Bad_Opcode },
6708     { Bad_Opcode },
6709     { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6710   },
6711
6712   /* PREFIX_VEX_0F3A78 */
6713   {
6714     { Bad_Opcode },
6715     { Bad_Opcode },
6716     { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6717   },
6718
6719   /* PREFIX_VEX_0F3A79 */
6720   {
6721     { Bad_Opcode },
6722     { Bad_Opcode },
6723     { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6724   },
6725
6726   /* PREFIX_VEX_0F3A7A */
6727   {
6728     { Bad_Opcode },
6729     { Bad_Opcode },
6730     { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6731   },
6732
6733   /* PREFIX_VEX_0F3A7B */
6734   {
6735     { Bad_Opcode },
6736     { Bad_Opcode },
6737     { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6738   },
6739
6740   /* PREFIX_VEX_0F3A7C */
6741   {
6742     { Bad_Opcode },
6743     { Bad_Opcode },
6744     { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6745     { Bad_Opcode },
6746   },
6747
6748   /* PREFIX_VEX_0F3A7D */
6749   {
6750     { Bad_Opcode },
6751     { Bad_Opcode },
6752     { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6753   },
6754
6755   /* PREFIX_VEX_0F3A7E */
6756   {
6757     { Bad_Opcode },
6758     { Bad_Opcode },
6759     { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6760   },
6761
6762   /* PREFIX_VEX_0F3A7F */
6763   {
6764     { Bad_Opcode },
6765     { Bad_Opcode },
6766     { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6767   },
6768
6769   /* PREFIX_VEX_0F3ACE */
6770   {
6771     { Bad_Opcode },
6772     { Bad_Opcode },
6773     { VEX_W_TABLE (VEX_W_0F3ACE_P_2) },
6774   },
6775
6776   /* PREFIX_VEX_0F3ACF */
6777   {
6778     { Bad_Opcode },
6779     { Bad_Opcode },
6780     { VEX_W_TABLE (VEX_W_0F3ACF_P_2) },
6781   },
6782
6783   /* PREFIX_VEX_0F3ADF */
6784   {
6785     { Bad_Opcode },
6786     { Bad_Opcode },
6787     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6788   },
6789
6790   /* PREFIX_VEX_0F3AF0 */
6791   {
6792     { Bad_Opcode },
6793     { Bad_Opcode },
6794     { Bad_Opcode },
6795     { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6796   },
6797
6798 #include "i386-dis-evex-prefix.h"
6799 };
6800
6801 static const struct dis386 x86_64_table[][2] = {
6802   /* X86_64_06 */
6803   {
6804     { "pushP", { es }, 0 },
6805   },
6806
6807   /* X86_64_07 */
6808   {
6809     { "popP", { es }, 0 },
6810   },
6811
6812   /* X86_64_0D */
6813   {
6814     { "pushP", { cs }, 0 },
6815   },
6816
6817   /* X86_64_16 */
6818   {
6819     { "pushP", { ss }, 0 },
6820   },
6821
6822   /* X86_64_17 */
6823   {
6824     { "popP", { ss }, 0 },
6825   },
6826
6827   /* X86_64_1E */
6828   {
6829     { "pushP", { ds }, 0 },
6830   },
6831
6832   /* X86_64_1F */
6833   {
6834     { "popP", { ds }, 0 },
6835   },
6836
6837   /* X86_64_27 */
6838   {
6839     { "daa", { XX }, 0 },
6840   },
6841
6842   /* X86_64_2F */
6843   {
6844     { "das", { XX }, 0 },
6845   },
6846
6847   /* X86_64_37 */
6848   {
6849     { "aaa", { XX }, 0 },
6850   },
6851
6852   /* X86_64_3F */
6853   {
6854     { "aas", { XX }, 0 },
6855   },
6856
6857   /* X86_64_60 */
6858   {
6859     { "pushaP", { XX }, 0 },
6860   },
6861
6862   /* X86_64_61 */
6863   {
6864     { "popaP", { XX }, 0 },
6865   },
6866
6867   /* X86_64_62 */
6868   {
6869     { MOD_TABLE (MOD_62_32BIT) },
6870     { EVEX_TABLE (EVEX_0F) },
6871   },
6872
6873   /* X86_64_63 */
6874   {
6875     { "arpl", { Ew, Gw }, 0 },
6876     { "movs{lq|xd}", { Gv, Ed }, 0 },
6877   },
6878
6879   /* X86_64_6D */
6880   {
6881     { "ins{R|}", { Yzr, indirDX }, 0 },
6882     { "ins{G|}", { Yzr, indirDX }, 0 },
6883   },
6884
6885   /* X86_64_6F */
6886   {
6887     { "outs{R|}", { indirDXr, Xz }, 0 },
6888     { "outs{G|}", { indirDXr, Xz }, 0 },
6889   },
6890
6891   /* X86_64_82 */
6892   {
6893     /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode.  */
6894     { REG_TABLE (REG_80) },
6895   },
6896
6897   /* X86_64_9A */
6898   {
6899     { "Jcall{T|}", { Ap }, 0 },
6900   },
6901
6902   /* X86_64_C4 */
6903   {
6904     { MOD_TABLE (MOD_C4_32BIT) },
6905     { VEX_C4_TABLE (VEX_0F) },
6906   },
6907
6908   /* X86_64_C5 */
6909   {
6910     { MOD_TABLE (MOD_C5_32BIT) },
6911     { VEX_C5_TABLE (VEX_0F) },
6912   },
6913
6914   /* X86_64_CE */
6915   {
6916     { "into", { XX }, 0 },
6917   },
6918
6919   /* X86_64_D4 */
6920   {
6921     { "aam", { Ib }, 0 },
6922   },
6923
6924   /* X86_64_D5 */
6925   {
6926     { "aad", { Ib }, 0 },
6927   },
6928
6929   /* X86_64_E8 */
6930   {
6931     { "callP",          { Jv, BND }, 0 },
6932     { "call@",          { Jv, BND }, 0 }
6933   },
6934
6935   /* X86_64_E9 */
6936   {
6937     { "jmpP",           { Jv, BND }, 0 },
6938     { "jmp@",           { Jv, BND }, 0 }
6939   },
6940
6941   /* X86_64_EA */
6942   {
6943     { "Jjmp{T|}", { Ap }, 0 },
6944   },
6945
6946   /* X86_64_0F01_REG_0 */
6947   {
6948     { "sgdt{Q|IQ}", { M }, 0 },
6949     { "sgdt", { M }, 0 },
6950   },
6951
6952   /* X86_64_0F01_REG_1 */
6953   {
6954     { "sidt{Q|IQ}", { M }, 0 },
6955     { "sidt", { M }, 0 },
6956   },
6957
6958   /* X86_64_0F01_REG_2 */
6959   {
6960     { "lgdt{Q|Q}", { M }, 0 },
6961     { "lgdt", { M }, 0 },
6962   },
6963
6964   /* X86_64_0F01_REG_3 */
6965   {
6966     { "lidt{Q|Q}", { M }, 0 },
6967     { "lidt", { M }, 0 },
6968   },
6969 };
6970
6971 static const struct dis386 three_byte_table[][256] = {
6972
6973   /* THREE_BYTE_0F38 */
6974   {
6975     /* 00 */
6976     { "pshufb",         { MX, EM }, PREFIX_OPCODE },
6977     { "phaddw",         { MX, EM }, PREFIX_OPCODE },
6978     { "phaddd",         { MX, EM }, PREFIX_OPCODE },
6979     { "phaddsw",        { MX, EM }, PREFIX_OPCODE },
6980     { "pmaddubsw",      { MX, EM }, PREFIX_OPCODE },
6981     { "phsubw",         { MX, EM }, PREFIX_OPCODE },
6982     { "phsubd",         { MX, EM }, PREFIX_OPCODE },
6983     { "phsubsw",        { MX, EM }, PREFIX_OPCODE },
6984     /* 08 */
6985     { "psignb",         { MX, EM }, PREFIX_OPCODE },
6986     { "psignw",         { MX, EM }, PREFIX_OPCODE },
6987     { "psignd",         { MX, EM }, PREFIX_OPCODE },
6988     { "pmulhrsw",       { MX, EM }, PREFIX_OPCODE },
6989     { Bad_Opcode },
6990     { Bad_Opcode },
6991     { Bad_Opcode },
6992     { Bad_Opcode },
6993     /* 10 */
6994     { PREFIX_TABLE (PREFIX_0F3810) },
6995     { Bad_Opcode },
6996     { Bad_Opcode },
6997     { Bad_Opcode },
6998     { PREFIX_TABLE (PREFIX_0F3814) },
6999     { PREFIX_TABLE (PREFIX_0F3815) },
7000     { Bad_Opcode },
7001     { PREFIX_TABLE (PREFIX_0F3817) },
7002     /* 18 */
7003     { Bad_Opcode },
7004     { Bad_Opcode },
7005     { Bad_Opcode },
7006     { Bad_Opcode },
7007     { "pabsb",          { MX, EM }, PREFIX_OPCODE },
7008     { "pabsw",          { MX, EM }, PREFIX_OPCODE },
7009     { "pabsd",          { MX, EM }, PREFIX_OPCODE },
7010     { Bad_Opcode },
7011     /* 20 */
7012     { PREFIX_TABLE (PREFIX_0F3820) },
7013     { PREFIX_TABLE (PREFIX_0F3821) },
7014     { PREFIX_TABLE (PREFIX_0F3822) },
7015     { PREFIX_TABLE (PREFIX_0F3823) },
7016     { PREFIX_TABLE (PREFIX_0F3824) },
7017     { PREFIX_TABLE (PREFIX_0F3825) },
7018     { Bad_Opcode },
7019     { Bad_Opcode },
7020     /* 28 */
7021     { PREFIX_TABLE (PREFIX_0F3828) },
7022     { PREFIX_TABLE (PREFIX_0F3829) },
7023     { PREFIX_TABLE (PREFIX_0F382A) },
7024     { PREFIX_TABLE (PREFIX_0F382B) },
7025     { Bad_Opcode },
7026     { Bad_Opcode },
7027     { Bad_Opcode },
7028     { Bad_Opcode },
7029     /* 30 */
7030     { PREFIX_TABLE (PREFIX_0F3830) },
7031     { PREFIX_TABLE (PREFIX_0F3831) },
7032     { PREFIX_TABLE (PREFIX_0F3832) },
7033     { PREFIX_TABLE (PREFIX_0F3833) },
7034     { PREFIX_TABLE (PREFIX_0F3834) },
7035     { PREFIX_TABLE (PREFIX_0F3835) },
7036     { Bad_Opcode },
7037     { PREFIX_TABLE (PREFIX_0F3837) },
7038     /* 38 */
7039     { PREFIX_TABLE (PREFIX_0F3838) },
7040     { PREFIX_TABLE (PREFIX_0F3839) },
7041     { PREFIX_TABLE (PREFIX_0F383A) },
7042     { PREFIX_TABLE (PREFIX_0F383B) },
7043     { PREFIX_TABLE (PREFIX_0F383C) },
7044     { PREFIX_TABLE (PREFIX_0F383D) },
7045     { PREFIX_TABLE (PREFIX_0F383E) },
7046     { PREFIX_TABLE (PREFIX_0F383F) },
7047     /* 40 */
7048     { PREFIX_TABLE (PREFIX_0F3840) },
7049     { PREFIX_TABLE (PREFIX_0F3841) },
7050     { Bad_Opcode },
7051     { Bad_Opcode },
7052     { Bad_Opcode },
7053     { Bad_Opcode },
7054     { Bad_Opcode },
7055     { Bad_Opcode },
7056     /* 48 */
7057     { Bad_Opcode },
7058     { Bad_Opcode },
7059     { Bad_Opcode },
7060     { Bad_Opcode },
7061     { Bad_Opcode },
7062     { Bad_Opcode },
7063     { Bad_Opcode },
7064     { Bad_Opcode },
7065     /* 50 */
7066     { Bad_Opcode },
7067     { Bad_Opcode },
7068     { Bad_Opcode },
7069     { Bad_Opcode },
7070     { Bad_Opcode },
7071     { Bad_Opcode },
7072     { Bad_Opcode },
7073     { Bad_Opcode },
7074     /* 58 */
7075     { Bad_Opcode },
7076     { Bad_Opcode },
7077     { Bad_Opcode },
7078     { Bad_Opcode },
7079     { Bad_Opcode },
7080     { Bad_Opcode },
7081     { Bad_Opcode },
7082     { Bad_Opcode },
7083     /* 60 */
7084     { Bad_Opcode },
7085     { Bad_Opcode },
7086     { Bad_Opcode },
7087     { Bad_Opcode },
7088     { Bad_Opcode },
7089     { Bad_Opcode },
7090     { Bad_Opcode },
7091     { Bad_Opcode },
7092     /* 68 */
7093     { Bad_Opcode },
7094     { Bad_Opcode },
7095     { Bad_Opcode },
7096     { Bad_Opcode },
7097     { Bad_Opcode },
7098     { Bad_Opcode },
7099     { Bad_Opcode },
7100     { Bad_Opcode },
7101     /* 70 */
7102     { Bad_Opcode },
7103     { Bad_Opcode },
7104     { Bad_Opcode },
7105     { Bad_Opcode },
7106     { Bad_Opcode },
7107     { Bad_Opcode },
7108     { Bad_Opcode },
7109     { Bad_Opcode },
7110     /* 78 */
7111     { Bad_Opcode },
7112     { Bad_Opcode },
7113     { Bad_Opcode },
7114     { Bad_Opcode },
7115     { Bad_Opcode },
7116     { Bad_Opcode },
7117     { Bad_Opcode },
7118     { Bad_Opcode },
7119     /* 80 */
7120     { PREFIX_TABLE (PREFIX_0F3880) },
7121     { PREFIX_TABLE (PREFIX_0F3881) },
7122     { PREFIX_TABLE (PREFIX_0F3882) },
7123     { Bad_Opcode },
7124     { Bad_Opcode },
7125     { Bad_Opcode },
7126     { Bad_Opcode },
7127     { Bad_Opcode },
7128     /* 88 */
7129     { Bad_Opcode },
7130     { Bad_Opcode },
7131     { Bad_Opcode },
7132     { Bad_Opcode },
7133     { Bad_Opcode },
7134     { Bad_Opcode },
7135     { Bad_Opcode },
7136     { Bad_Opcode },
7137     /* 90 */
7138     { Bad_Opcode },
7139     { Bad_Opcode },
7140     { Bad_Opcode },
7141     { Bad_Opcode },
7142     { Bad_Opcode },
7143     { Bad_Opcode },
7144     { Bad_Opcode },
7145     { Bad_Opcode },
7146     /* 98 */
7147     { Bad_Opcode },
7148     { Bad_Opcode },
7149     { Bad_Opcode },
7150     { Bad_Opcode },
7151     { Bad_Opcode },
7152     { Bad_Opcode },
7153     { Bad_Opcode },
7154     { Bad_Opcode },
7155     /* a0 */
7156     { Bad_Opcode },
7157     { Bad_Opcode },
7158     { Bad_Opcode },
7159     { Bad_Opcode },
7160     { Bad_Opcode },
7161     { Bad_Opcode },
7162     { Bad_Opcode },
7163     { Bad_Opcode },
7164     /* a8 */
7165     { Bad_Opcode },
7166     { Bad_Opcode },
7167     { Bad_Opcode },
7168     { Bad_Opcode },
7169     { Bad_Opcode },
7170     { Bad_Opcode },
7171     { Bad_Opcode },
7172     { Bad_Opcode },
7173     /* b0 */
7174     { Bad_Opcode },
7175     { Bad_Opcode },
7176     { Bad_Opcode },
7177     { Bad_Opcode },
7178     { Bad_Opcode },
7179     { Bad_Opcode },
7180     { Bad_Opcode },
7181     { Bad_Opcode },
7182     /* b8 */
7183     { Bad_Opcode },
7184     { Bad_Opcode },
7185     { Bad_Opcode },
7186     { Bad_Opcode },
7187     { Bad_Opcode },
7188     { Bad_Opcode },
7189     { Bad_Opcode },
7190     { Bad_Opcode },
7191     /* c0 */
7192     { Bad_Opcode },
7193     { Bad_Opcode },
7194     { Bad_Opcode },
7195     { Bad_Opcode },
7196     { Bad_Opcode },
7197     { Bad_Opcode },
7198     { Bad_Opcode },
7199     { Bad_Opcode },
7200     /* c8 */
7201     { PREFIX_TABLE (PREFIX_0F38C8) },
7202     { PREFIX_TABLE (PREFIX_0F38C9) },
7203     { PREFIX_TABLE (PREFIX_0F38CA) },
7204     { PREFIX_TABLE (PREFIX_0F38CB) },
7205     { PREFIX_TABLE (PREFIX_0F38CC) },
7206     { PREFIX_TABLE (PREFIX_0F38CD) },
7207     { Bad_Opcode },
7208     { PREFIX_TABLE (PREFIX_0F38CF) },
7209     /* d0 */
7210     { Bad_Opcode },
7211     { Bad_Opcode },
7212     { Bad_Opcode },
7213     { Bad_Opcode },
7214     { Bad_Opcode },
7215     { Bad_Opcode },
7216     { Bad_Opcode },
7217     { Bad_Opcode },
7218     /* d8 */
7219     { Bad_Opcode },
7220     { Bad_Opcode },
7221     { Bad_Opcode },
7222     { PREFIX_TABLE (PREFIX_0F38DB) },
7223     { PREFIX_TABLE (PREFIX_0F38DC) },
7224     { PREFIX_TABLE (PREFIX_0F38DD) },
7225     { PREFIX_TABLE (PREFIX_0F38DE) },
7226     { PREFIX_TABLE (PREFIX_0F38DF) },
7227     /* e0 */
7228     { Bad_Opcode },
7229     { Bad_Opcode },
7230     { Bad_Opcode },
7231     { Bad_Opcode },
7232     { Bad_Opcode },
7233     { Bad_Opcode },
7234     { Bad_Opcode },
7235     { Bad_Opcode },
7236     /* e8 */
7237     { Bad_Opcode },
7238     { Bad_Opcode },
7239     { Bad_Opcode },
7240     { Bad_Opcode },
7241     { Bad_Opcode },
7242     { Bad_Opcode },
7243     { Bad_Opcode },
7244     { Bad_Opcode },
7245     /* f0 */
7246     { PREFIX_TABLE (PREFIX_0F38F0) },
7247     { PREFIX_TABLE (PREFIX_0F38F1) },
7248     { Bad_Opcode },
7249     { Bad_Opcode },
7250     { Bad_Opcode },
7251     { PREFIX_TABLE (PREFIX_0F38F5) },
7252     { PREFIX_TABLE (PREFIX_0F38F6) },
7253     { Bad_Opcode },
7254     /* f8 */
7255     { PREFIX_TABLE (PREFIX_0F38F8) },
7256     { PREFIX_TABLE (PREFIX_0F38F9) },
7257     { Bad_Opcode },
7258     { Bad_Opcode },
7259     { Bad_Opcode },
7260     { Bad_Opcode },
7261     { Bad_Opcode },
7262     { Bad_Opcode },
7263   },
7264   /* THREE_BYTE_0F3A */
7265   {
7266     /* 00 */
7267     { Bad_Opcode },
7268     { Bad_Opcode },
7269     { Bad_Opcode },
7270     { Bad_Opcode },
7271     { Bad_Opcode },
7272     { Bad_Opcode },
7273     { Bad_Opcode },
7274     { Bad_Opcode },
7275     /* 08 */
7276     { PREFIX_TABLE (PREFIX_0F3A08) },
7277     { PREFIX_TABLE (PREFIX_0F3A09) },
7278     { PREFIX_TABLE (PREFIX_0F3A0A) },
7279     { PREFIX_TABLE (PREFIX_0F3A0B) },
7280     { PREFIX_TABLE (PREFIX_0F3A0C) },
7281     { PREFIX_TABLE (PREFIX_0F3A0D) },
7282     { PREFIX_TABLE (PREFIX_0F3A0E) },
7283     { "palignr",        { MX, EM, Ib }, PREFIX_OPCODE },
7284     /* 10 */
7285     { Bad_Opcode },
7286     { Bad_Opcode },
7287     { Bad_Opcode },
7288     { Bad_Opcode },
7289     { PREFIX_TABLE (PREFIX_0F3A14) },
7290     { PREFIX_TABLE (PREFIX_0F3A15) },
7291     { PREFIX_TABLE (PREFIX_0F3A16) },
7292     { PREFIX_TABLE (PREFIX_0F3A17) },
7293     /* 18 */
7294     { Bad_Opcode },
7295     { Bad_Opcode },
7296     { Bad_Opcode },
7297     { Bad_Opcode },
7298     { Bad_Opcode },
7299     { Bad_Opcode },
7300     { Bad_Opcode },
7301     { Bad_Opcode },
7302     /* 20 */
7303     { PREFIX_TABLE (PREFIX_0F3A20) },
7304     { PREFIX_TABLE (PREFIX_0F3A21) },
7305     { PREFIX_TABLE (PREFIX_0F3A22) },
7306     { Bad_Opcode },
7307     { Bad_Opcode },
7308     { Bad_Opcode },
7309     { Bad_Opcode },
7310     { Bad_Opcode },
7311     /* 28 */
7312     { Bad_Opcode },
7313     { Bad_Opcode },
7314     { Bad_Opcode },
7315     { Bad_Opcode },
7316     { Bad_Opcode },
7317     { Bad_Opcode },
7318     { Bad_Opcode },
7319     { Bad_Opcode },
7320     /* 30 */
7321     { Bad_Opcode },
7322     { Bad_Opcode },
7323     { Bad_Opcode },
7324     { Bad_Opcode },
7325     { Bad_Opcode },
7326     { Bad_Opcode },
7327     { Bad_Opcode },
7328     { Bad_Opcode },
7329     /* 38 */
7330     { Bad_Opcode },
7331     { Bad_Opcode },
7332     { Bad_Opcode },
7333     { Bad_Opcode },
7334     { Bad_Opcode },
7335     { Bad_Opcode },
7336     { Bad_Opcode },
7337     { Bad_Opcode },
7338     /* 40 */
7339     { PREFIX_TABLE (PREFIX_0F3A40) },
7340     { PREFIX_TABLE (PREFIX_0F3A41) },
7341     { PREFIX_TABLE (PREFIX_0F3A42) },
7342     { Bad_Opcode },
7343     { PREFIX_TABLE (PREFIX_0F3A44) },
7344     { Bad_Opcode },
7345     { Bad_Opcode },
7346     { Bad_Opcode },
7347     /* 48 */
7348     { Bad_Opcode },
7349     { Bad_Opcode },
7350     { Bad_Opcode },
7351     { Bad_Opcode },
7352     { Bad_Opcode },
7353     { Bad_Opcode },
7354     { Bad_Opcode },
7355     { Bad_Opcode },
7356     /* 50 */
7357     { Bad_Opcode },
7358     { Bad_Opcode },
7359     { Bad_Opcode },
7360     { Bad_Opcode },
7361     { Bad_Opcode },
7362     { Bad_Opcode },
7363     { Bad_Opcode },
7364     { Bad_Opcode },
7365     /* 58 */
7366     { Bad_Opcode },
7367     { Bad_Opcode },
7368     { Bad_Opcode },
7369     { Bad_Opcode },
7370     { Bad_Opcode },
7371     { Bad_Opcode },
7372     { Bad_Opcode },
7373     { Bad_Opcode },
7374     /* 60 */
7375     { PREFIX_TABLE (PREFIX_0F3A60) },
7376     { PREFIX_TABLE (PREFIX_0F3A61) },
7377     { PREFIX_TABLE (PREFIX_0F3A62) },
7378     { PREFIX_TABLE (PREFIX_0F3A63) },
7379     { Bad_Opcode },
7380     { Bad_Opcode },
7381     { Bad_Opcode },
7382     { Bad_Opcode },
7383     /* 68 */
7384     { Bad_Opcode },
7385     { Bad_Opcode },
7386     { Bad_Opcode },
7387     { Bad_Opcode },
7388     { Bad_Opcode },
7389     { Bad_Opcode },
7390     { Bad_Opcode },
7391     { Bad_Opcode },
7392     /* 70 */
7393     { Bad_Opcode },
7394     { Bad_Opcode },
7395     { Bad_Opcode },
7396     { Bad_Opcode },
7397     { Bad_Opcode },
7398     { Bad_Opcode },
7399     { Bad_Opcode },
7400     { Bad_Opcode },
7401     /* 78 */
7402     { Bad_Opcode },
7403     { Bad_Opcode },
7404     { Bad_Opcode },
7405     { Bad_Opcode },
7406     { Bad_Opcode },
7407     { Bad_Opcode },
7408     { Bad_Opcode },
7409     { Bad_Opcode },
7410     /* 80 */
7411     { Bad_Opcode },
7412     { Bad_Opcode },
7413     { Bad_Opcode },
7414     { Bad_Opcode },
7415     { Bad_Opcode },
7416     { Bad_Opcode },
7417     { Bad_Opcode },
7418     { Bad_Opcode },
7419     /* 88 */
7420     { Bad_Opcode },
7421     { Bad_Opcode },
7422     { Bad_Opcode },
7423     { Bad_Opcode },
7424     { Bad_Opcode },
7425     { Bad_Opcode },
7426     { Bad_Opcode },
7427     { Bad_Opcode },
7428     /* 90 */
7429     { Bad_Opcode },
7430     { Bad_Opcode },
7431     { Bad_Opcode },
7432     { Bad_Opcode },
7433     { Bad_Opcode },
7434     { Bad_Opcode },
7435     { Bad_Opcode },
7436     { Bad_Opcode },
7437     /* 98 */
7438     { Bad_Opcode },
7439     { Bad_Opcode },
7440     { Bad_Opcode },
7441     { Bad_Opcode },
7442     { Bad_Opcode },
7443     { Bad_Opcode },
7444     { Bad_Opcode },
7445     { Bad_Opcode },
7446     /* a0 */
7447     { Bad_Opcode },
7448     { Bad_Opcode },
7449     { Bad_Opcode },
7450     { Bad_Opcode },
7451     { Bad_Opcode },
7452     { Bad_Opcode },
7453     { Bad_Opcode },
7454     { Bad_Opcode },
7455     /* a8 */
7456     { Bad_Opcode },
7457     { Bad_Opcode },
7458     { Bad_Opcode },
7459     { Bad_Opcode },
7460     { Bad_Opcode },
7461     { Bad_Opcode },
7462     { Bad_Opcode },
7463     { Bad_Opcode },
7464     /* b0 */
7465     { Bad_Opcode },
7466     { Bad_Opcode },
7467     { Bad_Opcode },
7468     { Bad_Opcode },
7469     { Bad_Opcode },
7470     { Bad_Opcode },
7471     { Bad_Opcode },
7472     { Bad_Opcode },
7473     /* b8 */
7474     { Bad_Opcode },
7475     { Bad_Opcode },
7476     { Bad_Opcode },
7477     { Bad_Opcode },
7478     { Bad_Opcode },
7479     { Bad_Opcode },
7480     { Bad_Opcode },
7481     { Bad_Opcode },
7482     /* c0 */
7483     { Bad_Opcode },
7484     { Bad_Opcode },
7485     { Bad_Opcode },
7486     { Bad_Opcode },
7487     { Bad_Opcode },
7488     { Bad_Opcode },
7489     { Bad_Opcode },
7490     { Bad_Opcode },
7491     /* c8 */
7492     { Bad_Opcode },
7493     { Bad_Opcode },
7494     { Bad_Opcode },
7495     { Bad_Opcode },
7496     { PREFIX_TABLE (PREFIX_0F3ACC) },
7497     { Bad_Opcode },
7498     { PREFIX_TABLE (PREFIX_0F3ACE) },
7499     { PREFIX_TABLE (PREFIX_0F3ACF) },
7500     /* d0 */
7501     { Bad_Opcode },
7502     { Bad_Opcode },
7503     { Bad_Opcode },
7504     { Bad_Opcode },
7505     { Bad_Opcode },
7506     { Bad_Opcode },
7507     { Bad_Opcode },
7508     { Bad_Opcode },
7509     /* d8 */
7510     { Bad_Opcode },
7511     { Bad_Opcode },
7512     { Bad_Opcode },
7513     { Bad_Opcode },
7514     { Bad_Opcode },
7515     { Bad_Opcode },
7516     { Bad_Opcode },
7517     { PREFIX_TABLE (PREFIX_0F3ADF) },
7518     /* e0 */
7519     { Bad_Opcode },
7520     { Bad_Opcode },
7521     { Bad_Opcode },
7522     { Bad_Opcode },
7523     { Bad_Opcode },
7524     { Bad_Opcode },
7525     { Bad_Opcode },
7526     { Bad_Opcode },
7527     /* e8 */
7528     { Bad_Opcode },
7529     { Bad_Opcode },
7530     { Bad_Opcode },
7531     { Bad_Opcode },
7532     { Bad_Opcode },
7533     { Bad_Opcode },
7534     { Bad_Opcode },
7535     { Bad_Opcode },
7536     /* f0 */
7537     { Bad_Opcode },
7538     { Bad_Opcode },
7539     { Bad_Opcode },
7540     { Bad_Opcode },
7541     { Bad_Opcode },
7542     { Bad_Opcode },
7543     { Bad_Opcode },
7544     { Bad_Opcode },
7545     /* f8 */
7546     { Bad_Opcode },
7547     { Bad_Opcode },
7548     { Bad_Opcode },
7549     { Bad_Opcode },
7550     { Bad_Opcode },
7551     { Bad_Opcode },
7552     { Bad_Opcode },
7553     { Bad_Opcode },
7554   },
7555 };
7556
7557 static const struct dis386 xop_table[][256] = {
7558   /* XOP_08 */
7559   {
7560     /* 00 */
7561     { Bad_Opcode },
7562     { Bad_Opcode },
7563     { Bad_Opcode },
7564     { Bad_Opcode },
7565     { Bad_Opcode },
7566     { Bad_Opcode },
7567     { Bad_Opcode },
7568     { Bad_Opcode },
7569     /* 08 */
7570     { Bad_Opcode },
7571     { Bad_Opcode },
7572     { Bad_Opcode },
7573     { Bad_Opcode },
7574     { Bad_Opcode },
7575     { Bad_Opcode },
7576     { Bad_Opcode },
7577     { Bad_Opcode },
7578     /* 10 */
7579     { Bad_Opcode },
7580     { Bad_Opcode },
7581     { Bad_Opcode },
7582     { Bad_Opcode },
7583     { Bad_Opcode },
7584     { Bad_Opcode },
7585     { Bad_Opcode },
7586     { Bad_Opcode },
7587     /* 18 */
7588     { Bad_Opcode },
7589     { Bad_Opcode },
7590     { Bad_Opcode },
7591     { Bad_Opcode },
7592     { Bad_Opcode },
7593     { Bad_Opcode },
7594     { Bad_Opcode },
7595     { Bad_Opcode },
7596     /* 20 */
7597     { Bad_Opcode },
7598     { Bad_Opcode },
7599     { Bad_Opcode },
7600     { Bad_Opcode },
7601     { Bad_Opcode },
7602     { Bad_Opcode },
7603     { Bad_Opcode },
7604     { Bad_Opcode },
7605     /* 28 */
7606     { Bad_Opcode },
7607     { Bad_Opcode },
7608     { Bad_Opcode },
7609     { Bad_Opcode },
7610     { Bad_Opcode },
7611     { Bad_Opcode },
7612     { Bad_Opcode },
7613     { Bad_Opcode },
7614     /* 30 */
7615     { Bad_Opcode },
7616     { Bad_Opcode },
7617     { Bad_Opcode },
7618     { Bad_Opcode },
7619     { Bad_Opcode },
7620     { Bad_Opcode },
7621     { Bad_Opcode },
7622     { Bad_Opcode },
7623     /* 38 */
7624     { Bad_Opcode },
7625     { Bad_Opcode },
7626     { Bad_Opcode },
7627     { Bad_Opcode },
7628     { Bad_Opcode },
7629     { Bad_Opcode },
7630     { Bad_Opcode },
7631     { Bad_Opcode },
7632     /* 40 */
7633     { Bad_Opcode },
7634     { Bad_Opcode },
7635     { Bad_Opcode },
7636     { Bad_Opcode },
7637     { Bad_Opcode },
7638     { Bad_Opcode },
7639     { Bad_Opcode },
7640     { Bad_Opcode },
7641     /* 48 */
7642     { Bad_Opcode },
7643     { Bad_Opcode },
7644     { Bad_Opcode },
7645     { Bad_Opcode },
7646     { Bad_Opcode },
7647     { Bad_Opcode },
7648     { Bad_Opcode },
7649     { Bad_Opcode },
7650     /* 50 */
7651     { Bad_Opcode },
7652     { Bad_Opcode },
7653     { Bad_Opcode },
7654     { Bad_Opcode },
7655     { Bad_Opcode },
7656     { Bad_Opcode },
7657     { Bad_Opcode },
7658     { Bad_Opcode },
7659     /* 58 */
7660     { Bad_Opcode },
7661     { Bad_Opcode },
7662     { Bad_Opcode },
7663     { Bad_Opcode },
7664     { Bad_Opcode },
7665     { Bad_Opcode },
7666     { Bad_Opcode },
7667     { Bad_Opcode },
7668     /* 60 */
7669     { Bad_Opcode },
7670     { Bad_Opcode },
7671     { Bad_Opcode },
7672     { Bad_Opcode },
7673     { Bad_Opcode },
7674     { Bad_Opcode },
7675     { Bad_Opcode },
7676     { Bad_Opcode },
7677     /* 68 */
7678     { Bad_Opcode },
7679     { Bad_Opcode },
7680     { Bad_Opcode },
7681     { Bad_Opcode },
7682     { Bad_Opcode },
7683     { Bad_Opcode },
7684     { Bad_Opcode },
7685     { Bad_Opcode },
7686     /* 70 */
7687     { Bad_Opcode },
7688     { Bad_Opcode },
7689     { Bad_Opcode },
7690     { Bad_Opcode },
7691     { Bad_Opcode },
7692     { Bad_Opcode },
7693     { Bad_Opcode },
7694     { Bad_Opcode },
7695     /* 78 */
7696     { Bad_Opcode },
7697     { Bad_Opcode },
7698     { Bad_Opcode },
7699     { Bad_Opcode },
7700     { Bad_Opcode },
7701     { Bad_Opcode },
7702     { Bad_Opcode },
7703     { Bad_Opcode },
7704     /* 80 */
7705     { Bad_Opcode },
7706     { Bad_Opcode },
7707     { Bad_Opcode },
7708     { Bad_Opcode },
7709     { Bad_Opcode },
7710     { "vpmacssww",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7711     { "vpmacsswd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7712     { "vpmacssdql",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7713     /* 88 */
7714     { Bad_Opcode },
7715     { Bad_Opcode },
7716     { Bad_Opcode },
7717     { Bad_Opcode },
7718     { Bad_Opcode },
7719     { Bad_Opcode },
7720     { "vpmacssdd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7721     { "vpmacssdqh",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7722     /* 90 */
7723     { Bad_Opcode },
7724     { Bad_Opcode },
7725     { Bad_Opcode },
7726     { Bad_Opcode },
7727     { Bad_Opcode },
7728     { "vpmacsww",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7729     { "vpmacswd",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7730     { "vpmacsdql",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7731     /* 98 */
7732     { Bad_Opcode },
7733     { Bad_Opcode },
7734     { Bad_Opcode },
7735     { Bad_Opcode },
7736     { Bad_Opcode },
7737     { Bad_Opcode },
7738     { "vpmacsdd",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7739     { "vpmacsdqh",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7740     /* a0 */
7741     { Bad_Opcode },
7742     { Bad_Opcode },
7743     { "vpcmov",         { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7744     { "vpperm",         { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7745     { Bad_Opcode },
7746     { Bad_Opcode },
7747     { "vpmadcsswd",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7748     { Bad_Opcode },
7749     /* a8 */
7750     { Bad_Opcode },
7751     { Bad_Opcode },
7752     { Bad_Opcode },
7753     { Bad_Opcode },
7754     { Bad_Opcode },
7755     { Bad_Opcode },
7756     { Bad_Opcode },
7757     { Bad_Opcode },
7758     /* b0 */
7759     { Bad_Opcode },
7760     { Bad_Opcode },
7761     { Bad_Opcode },
7762     { Bad_Opcode },
7763     { Bad_Opcode },
7764     { Bad_Opcode },
7765     { "vpmadcswd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7766     { Bad_Opcode },
7767     /* b8 */
7768     { Bad_Opcode },
7769     { Bad_Opcode },
7770     { Bad_Opcode },
7771     { Bad_Opcode },
7772     { Bad_Opcode },
7773     { Bad_Opcode },
7774     { Bad_Opcode },
7775     { Bad_Opcode },
7776     /* c0 */
7777     { "vprotb",         { XM, Vex_2src_1, Ib }, 0 },
7778     { "vprotw",         { XM, Vex_2src_1, Ib }, 0 },
7779     { "vprotd",         { XM, Vex_2src_1, Ib }, 0 },
7780     { "vprotq",         { XM, Vex_2src_1, Ib }, 0 },
7781     { Bad_Opcode },
7782     { Bad_Opcode },
7783     { Bad_Opcode },
7784     { Bad_Opcode },
7785     /* c8 */
7786     { Bad_Opcode },
7787     { Bad_Opcode },
7788     { Bad_Opcode },
7789     { Bad_Opcode },
7790     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
7791     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
7792     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
7793     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
7794     /* d0 */
7795     { Bad_Opcode },
7796     { Bad_Opcode },
7797     { Bad_Opcode },
7798     { Bad_Opcode },
7799     { Bad_Opcode },
7800     { Bad_Opcode },
7801     { Bad_Opcode },
7802     { Bad_Opcode },
7803     /* d8 */
7804     { Bad_Opcode },
7805     { Bad_Opcode },
7806     { Bad_Opcode },
7807     { Bad_Opcode },
7808     { Bad_Opcode },
7809     { Bad_Opcode },
7810     { Bad_Opcode },
7811     { Bad_Opcode },
7812     /* e0 */
7813     { Bad_Opcode },
7814     { Bad_Opcode },
7815     { Bad_Opcode },
7816     { Bad_Opcode },
7817     { Bad_Opcode },
7818     { Bad_Opcode },
7819     { Bad_Opcode },
7820     { Bad_Opcode },
7821     /* e8 */
7822     { Bad_Opcode },
7823     { Bad_Opcode },
7824     { Bad_Opcode },
7825     { Bad_Opcode },
7826     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
7827     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
7828     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
7829     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
7830     /* f0 */
7831     { Bad_Opcode },
7832     { Bad_Opcode },
7833     { Bad_Opcode },
7834     { Bad_Opcode },
7835     { Bad_Opcode },
7836     { Bad_Opcode },
7837     { Bad_Opcode },
7838     { Bad_Opcode },
7839     /* f8 */
7840     { Bad_Opcode },
7841     { Bad_Opcode },
7842     { Bad_Opcode },
7843     { Bad_Opcode },
7844     { Bad_Opcode },
7845     { Bad_Opcode },
7846     { Bad_Opcode },
7847     { Bad_Opcode },
7848   },
7849   /* XOP_09 */
7850   {
7851     /* 00 */
7852     { Bad_Opcode },
7853     { REG_TABLE (REG_XOP_TBM_01) },
7854     { REG_TABLE (REG_XOP_TBM_02) },
7855     { Bad_Opcode },
7856     { Bad_Opcode },
7857     { Bad_Opcode },
7858     { Bad_Opcode },
7859     { Bad_Opcode },
7860     /* 08 */
7861     { Bad_Opcode },
7862     { Bad_Opcode },
7863     { Bad_Opcode },
7864     { Bad_Opcode },
7865     { Bad_Opcode },
7866     { Bad_Opcode },
7867     { Bad_Opcode },
7868     { Bad_Opcode },
7869     /* 10 */
7870     { Bad_Opcode },
7871     { Bad_Opcode },
7872     { REG_TABLE (REG_XOP_LWPCB) },
7873     { Bad_Opcode },
7874     { Bad_Opcode },
7875     { Bad_Opcode },
7876     { Bad_Opcode },
7877     { Bad_Opcode },
7878     /* 18 */
7879     { Bad_Opcode },
7880     { Bad_Opcode },
7881     { Bad_Opcode },
7882     { Bad_Opcode },
7883     { Bad_Opcode },
7884     { Bad_Opcode },
7885     { Bad_Opcode },
7886     { Bad_Opcode },
7887     /* 20 */
7888     { Bad_Opcode },
7889     { Bad_Opcode },
7890     { Bad_Opcode },
7891     { Bad_Opcode },
7892     { Bad_Opcode },
7893     { Bad_Opcode },
7894     { Bad_Opcode },
7895     { Bad_Opcode },
7896     /* 28 */
7897     { Bad_Opcode },
7898     { Bad_Opcode },
7899     { Bad_Opcode },
7900     { Bad_Opcode },
7901     { Bad_Opcode },
7902     { Bad_Opcode },
7903     { Bad_Opcode },
7904     { Bad_Opcode },
7905     /* 30 */
7906     { Bad_Opcode },
7907     { Bad_Opcode },
7908     { Bad_Opcode },
7909     { Bad_Opcode },
7910     { Bad_Opcode },
7911     { Bad_Opcode },
7912     { Bad_Opcode },
7913     { Bad_Opcode },
7914     /* 38 */
7915     { Bad_Opcode },
7916     { Bad_Opcode },
7917     { Bad_Opcode },
7918     { Bad_Opcode },
7919     { Bad_Opcode },
7920     { Bad_Opcode },
7921     { Bad_Opcode },
7922     { Bad_Opcode },
7923     /* 40 */
7924     { Bad_Opcode },
7925     { Bad_Opcode },
7926     { Bad_Opcode },
7927     { Bad_Opcode },
7928     { Bad_Opcode },
7929     { Bad_Opcode },
7930     { Bad_Opcode },
7931     { Bad_Opcode },
7932     /* 48 */
7933     { Bad_Opcode },
7934     { Bad_Opcode },
7935     { Bad_Opcode },
7936     { Bad_Opcode },
7937     { Bad_Opcode },
7938     { Bad_Opcode },
7939     { Bad_Opcode },
7940     { Bad_Opcode },
7941     /* 50 */
7942     { Bad_Opcode },
7943     { Bad_Opcode },
7944     { Bad_Opcode },
7945     { Bad_Opcode },
7946     { Bad_Opcode },
7947     { Bad_Opcode },
7948     { Bad_Opcode },
7949     { Bad_Opcode },
7950     /* 58 */
7951     { Bad_Opcode },
7952     { Bad_Opcode },
7953     { Bad_Opcode },
7954     { Bad_Opcode },
7955     { Bad_Opcode },
7956     { Bad_Opcode },
7957     { Bad_Opcode },
7958     { Bad_Opcode },
7959     /* 60 */
7960     { Bad_Opcode },
7961     { Bad_Opcode },
7962     { Bad_Opcode },
7963     { Bad_Opcode },
7964     { Bad_Opcode },
7965     { Bad_Opcode },
7966     { Bad_Opcode },
7967     { Bad_Opcode },
7968     /* 68 */
7969     { Bad_Opcode },
7970     { Bad_Opcode },
7971     { Bad_Opcode },
7972     { Bad_Opcode },
7973     { Bad_Opcode },
7974     { Bad_Opcode },
7975     { Bad_Opcode },
7976     { Bad_Opcode },
7977     /* 70 */
7978     { Bad_Opcode },
7979     { Bad_Opcode },
7980     { Bad_Opcode },
7981     { Bad_Opcode },
7982     { Bad_Opcode },
7983     { Bad_Opcode },
7984     { Bad_Opcode },
7985     { Bad_Opcode },
7986     /* 78 */
7987     { Bad_Opcode },
7988     { Bad_Opcode },
7989     { Bad_Opcode },
7990     { Bad_Opcode },
7991     { Bad_Opcode },
7992     { Bad_Opcode },
7993     { Bad_Opcode },
7994     { Bad_Opcode },
7995     /* 80 */
7996     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
7997     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
7998     { "vfrczss",        { XM, EXd }, 0 },
7999     { "vfrczsd",        { XM, EXq }, 0 },
8000     { Bad_Opcode },
8001     { Bad_Opcode },
8002     { Bad_Opcode },
8003     { Bad_Opcode },
8004     /* 88 */
8005     { Bad_Opcode },
8006     { Bad_Opcode },
8007     { Bad_Opcode },
8008     { Bad_Opcode },
8009     { Bad_Opcode },
8010     { Bad_Opcode },
8011     { Bad_Opcode },
8012     { Bad_Opcode },
8013     /* 90 */
8014     { "vprotb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8015     { "vprotw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8016     { "vprotd",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8017     { "vprotq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8018     { "vpshlb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8019     { "vpshlw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8020     { "vpshld",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8021     { "vpshlq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8022     /* 98 */
8023     { "vpshab",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8024     { "vpshaw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8025     { "vpshad",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8026     { "vpshaq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8027     { Bad_Opcode },
8028     { Bad_Opcode },
8029     { Bad_Opcode },
8030     { Bad_Opcode },
8031     /* a0 */
8032     { Bad_Opcode },
8033     { Bad_Opcode },
8034     { Bad_Opcode },
8035     { Bad_Opcode },
8036     { Bad_Opcode },
8037     { Bad_Opcode },
8038     { Bad_Opcode },
8039     { Bad_Opcode },
8040     /* a8 */
8041     { Bad_Opcode },
8042     { Bad_Opcode },
8043     { Bad_Opcode },
8044     { Bad_Opcode },
8045     { Bad_Opcode },
8046     { Bad_Opcode },
8047     { Bad_Opcode },
8048     { Bad_Opcode },
8049     /* b0 */
8050     { Bad_Opcode },
8051     { Bad_Opcode },
8052     { Bad_Opcode },
8053     { Bad_Opcode },
8054     { Bad_Opcode },
8055     { Bad_Opcode },
8056     { Bad_Opcode },
8057     { Bad_Opcode },
8058     /* b8 */
8059     { Bad_Opcode },
8060     { Bad_Opcode },
8061     { Bad_Opcode },
8062     { Bad_Opcode },
8063     { Bad_Opcode },
8064     { Bad_Opcode },
8065     { Bad_Opcode },
8066     { Bad_Opcode },
8067     /* c0 */
8068     { Bad_Opcode },
8069     { "vphaddbw",       { XM, EXxmm }, 0 },
8070     { "vphaddbd",       { XM, EXxmm }, 0 },
8071     { "vphaddbq",       { XM, EXxmm }, 0 },
8072     { Bad_Opcode },
8073     { Bad_Opcode },
8074     { "vphaddwd",       { XM, EXxmm }, 0 },
8075     { "vphaddwq",       { XM, EXxmm }, 0 },
8076     /* c8 */
8077     { Bad_Opcode },
8078     { Bad_Opcode },
8079     { Bad_Opcode },
8080     { "vphadddq",       { XM, EXxmm }, 0 },
8081     { Bad_Opcode },
8082     { Bad_Opcode },
8083     { Bad_Opcode },
8084     { Bad_Opcode },
8085     /* d0 */
8086     { Bad_Opcode },
8087     { "vphaddubw",      { XM, EXxmm }, 0 },
8088     { "vphaddubd",      { XM, EXxmm }, 0 },
8089     { "vphaddubq",      { XM, EXxmm }, 0 },
8090     { Bad_Opcode },
8091     { Bad_Opcode },
8092     { "vphadduwd",      { XM, EXxmm }, 0 },
8093     { "vphadduwq",      { XM, EXxmm }, 0 },
8094     /* d8 */
8095     { Bad_Opcode },
8096     { Bad_Opcode },
8097     { Bad_Opcode },
8098     { "vphaddudq",      { XM, EXxmm }, 0 },
8099     { Bad_Opcode },
8100     { Bad_Opcode },
8101     { Bad_Opcode },
8102     { Bad_Opcode },
8103     /* e0 */
8104     { Bad_Opcode },
8105     { "vphsubbw",       { XM, EXxmm }, 0 },
8106     { "vphsubwd",       { XM, EXxmm }, 0 },
8107     { "vphsubdq",       { XM, EXxmm }, 0 },
8108     { Bad_Opcode },
8109     { Bad_Opcode },
8110     { Bad_Opcode },
8111     { Bad_Opcode },
8112     /* e8 */
8113     { Bad_Opcode },
8114     { Bad_Opcode },
8115     { Bad_Opcode },
8116     { Bad_Opcode },
8117     { Bad_Opcode },
8118     { Bad_Opcode },
8119     { Bad_Opcode },
8120     { Bad_Opcode },
8121     /* f0 */
8122     { Bad_Opcode },
8123     { Bad_Opcode },
8124     { Bad_Opcode },
8125     { Bad_Opcode },
8126     { Bad_Opcode },
8127     { Bad_Opcode },
8128     { Bad_Opcode },
8129     { Bad_Opcode },
8130     /* f8 */
8131     { Bad_Opcode },
8132     { Bad_Opcode },
8133     { Bad_Opcode },
8134     { Bad_Opcode },
8135     { Bad_Opcode },
8136     { Bad_Opcode },
8137     { Bad_Opcode },
8138     { Bad_Opcode },
8139   },
8140   /* XOP_0A */
8141   {
8142     /* 00 */
8143     { Bad_Opcode },
8144     { Bad_Opcode },
8145     { Bad_Opcode },
8146     { Bad_Opcode },
8147     { Bad_Opcode },
8148     { Bad_Opcode },
8149     { Bad_Opcode },
8150     { Bad_Opcode },
8151     /* 08 */
8152     { Bad_Opcode },
8153     { Bad_Opcode },
8154     { Bad_Opcode },
8155     { Bad_Opcode },
8156     { Bad_Opcode },
8157     { Bad_Opcode },
8158     { Bad_Opcode },
8159     { Bad_Opcode },
8160     /* 10 */
8161     { "bextrS", { Gdq, Edq, Id }, 0 },
8162     { Bad_Opcode },
8163     { REG_TABLE (REG_XOP_LWP) },
8164     { Bad_Opcode },
8165     { Bad_Opcode },
8166     { Bad_Opcode },
8167     { Bad_Opcode },
8168     { Bad_Opcode },
8169     /* 18 */
8170     { Bad_Opcode },
8171     { Bad_Opcode },
8172     { Bad_Opcode },
8173     { Bad_Opcode },
8174     { Bad_Opcode },
8175     { Bad_Opcode },
8176     { Bad_Opcode },
8177     { Bad_Opcode },
8178     /* 20 */
8179     { Bad_Opcode },
8180     { Bad_Opcode },
8181     { Bad_Opcode },
8182     { Bad_Opcode },
8183     { Bad_Opcode },
8184     { Bad_Opcode },
8185     { Bad_Opcode },
8186     { Bad_Opcode },
8187     /* 28 */
8188     { Bad_Opcode },
8189     { Bad_Opcode },
8190     { Bad_Opcode },
8191     { Bad_Opcode },
8192     { Bad_Opcode },
8193     { Bad_Opcode },
8194     { Bad_Opcode },
8195     { Bad_Opcode },
8196     /* 30 */
8197     { Bad_Opcode },
8198     { Bad_Opcode },
8199     { Bad_Opcode },
8200     { Bad_Opcode },
8201     { Bad_Opcode },
8202     { Bad_Opcode },
8203     { Bad_Opcode },
8204     { Bad_Opcode },
8205     /* 38 */
8206     { Bad_Opcode },
8207     { Bad_Opcode },
8208     { Bad_Opcode },
8209     { Bad_Opcode },
8210     { Bad_Opcode },
8211     { Bad_Opcode },
8212     { Bad_Opcode },
8213     { Bad_Opcode },
8214     /* 40 */
8215     { Bad_Opcode },
8216     { Bad_Opcode },
8217     { Bad_Opcode },
8218     { Bad_Opcode },
8219     { Bad_Opcode },
8220     { Bad_Opcode },
8221     { Bad_Opcode },
8222     { Bad_Opcode },
8223     /* 48 */
8224     { Bad_Opcode },
8225     { Bad_Opcode },
8226     { Bad_Opcode },
8227     { Bad_Opcode },
8228     { Bad_Opcode },
8229     { Bad_Opcode },
8230     { Bad_Opcode },
8231     { Bad_Opcode },
8232     /* 50 */
8233     { Bad_Opcode },
8234     { Bad_Opcode },
8235     { Bad_Opcode },
8236     { Bad_Opcode },
8237     { Bad_Opcode },
8238     { Bad_Opcode },
8239     { Bad_Opcode },
8240     { Bad_Opcode },
8241     /* 58 */
8242     { Bad_Opcode },
8243     { Bad_Opcode },
8244     { Bad_Opcode },
8245     { Bad_Opcode },
8246     { Bad_Opcode },
8247     { Bad_Opcode },
8248     { Bad_Opcode },
8249     { Bad_Opcode },
8250     /* 60 */
8251     { Bad_Opcode },
8252     { Bad_Opcode },
8253     { Bad_Opcode },
8254     { Bad_Opcode },
8255     { Bad_Opcode },
8256     { Bad_Opcode },
8257     { Bad_Opcode },
8258     { Bad_Opcode },
8259     /* 68 */
8260     { Bad_Opcode },
8261     { Bad_Opcode },
8262     { Bad_Opcode },
8263     { Bad_Opcode },
8264     { Bad_Opcode },
8265     { Bad_Opcode },
8266     { Bad_Opcode },
8267     { Bad_Opcode },
8268     /* 70 */
8269     { Bad_Opcode },
8270     { Bad_Opcode },
8271     { Bad_Opcode },
8272     { Bad_Opcode },
8273     { Bad_Opcode },
8274     { Bad_Opcode },
8275     { Bad_Opcode },
8276     { Bad_Opcode },
8277     /* 78 */
8278     { Bad_Opcode },
8279     { Bad_Opcode },
8280     { Bad_Opcode },
8281     { Bad_Opcode },
8282     { Bad_Opcode },
8283     { Bad_Opcode },
8284     { Bad_Opcode },
8285     { Bad_Opcode },
8286     /* 80 */
8287     { Bad_Opcode },
8288     { Bad_Opcode },
8289     { Bad_Opcode },
8290     { Bad_Opcode },
8291     { Bad_Opcode },
8292     { Bad_Opcode },
8293     { Bad_Opcode },
8294     { Bad_Opcode },
8295     /* 88 */
8296     { Bad_Opcode },
8297     { Bad_Opcode },
8298     { Bad_Opcode },
8299     { Bad_Opcode },
8300     { Bad_Opcode },
8301     { Bad_Opcode },
8302     { Bad_Opcode },
8303     { Bad_Opcode },
8304     /* 90 */
8305     { Bad_Opcode },
8306     { Bad_Opcode },
8307     { Bad_Opcode },
8308     { Bad_Opcode },
8309     { Bad_Opcode },
8310     { Bad_Opcode },
8311     { Bad_Opcode },
8312     { Bad_Opcode },
8313     /* 98 */
8314     { Bad_Opcode },
8315     { Bad_Opcode },
8316     { Bad_Opcode },
8317     { Bad_Opcode },
8318     { Bad_Opcode },
8319     { Bad_Opcode },
8320     { Bad_Opcode },
8321     { Bad_Opcode },
8322     /* a0 */
8323     { Bad_Opcode },
8324     { Bad_Opcode },
8325     { Bad_Opcode },
8326     { Bad_Opcode },
8327     { Bad_Opcode },
8328     { Bad_Opcode },
8329     { Bad_Opcode },
8330     { Bad_Opcode },
8331     /* a8 */
8332     { Bad_Opcode },
8333     { Bad_Opcode },
8334     { Bad_Opcode },
8335     { Bad_Opcode },
8336     { Bad_Opcode },
8337     { Bad_Opcode },
8338     { Bad_Opcode },
8339     { Bad_Opcode },
8340     /* b0 */
8341     { Bad_Opcode },
8342     { Bad_Opcode },
8343     { Bad_Opcode },
8344     { Bad_Opcode },
8345     { Bad_Opcode },
8346     { Bad_Opcode },
8347     { Bad_Opcode },
8348     { Bad_Opcode },
8349     /* b8 */
8350     { Bad_Opcode },
8351     { Bad_Opcode },
8352     { Bad_Opcode },
8353     { Bad_Opcode },
8354     { Bad_Opcode },
8355     { Bad_Opcode },
8356     { Bad_Opcode },
8357     { Bad_Opcode },
8358     /* c0 */
8359     { Bad_Opcode },
8360     { Bad_Opcode },
8361     { Bad_Opcode },
8362     { Bad_Opcode },
8363     { Bad_Opcode },
8364     { Bad_Opcode },
8365     { Bad_Opcode },
8366     { Bad_Opcode },
8367     /* c8 */
8368     { Bad_Opcode },
8369     { Bad_Opcode },
8370     { Bad_Opcode },
8371     { Bad_Opcode },
8372     { Bad_Opcode },
8373     { Bad_Opcode },
8374     { Bad_Opcode },
8375     { Bad_Opcode },
8376     /* d0 */
8377     { Bad_Opcode },
8378     { Bad_Opcode },
8379     { Bad_Opcode },
8380     { Bad_Opcode },
8381     { Bad_Opcode },
8382     { Bad_Opcode },
8383     { Bad_Opcode },
8384     { Bad_Opcode },
8385     /* d8 */
8386     { Bad_Opcode },
8387     { Bad_Opcode },
8388     { Bad_Opcode },
8389     { Bad_Opcode },
8390     { Bad_Opcode },
8391     { Bad_Opcode },
8392     { Bad_Opcode },
8393     { Bad_Opcode },
8394     /* e0 */
8395     { Bad_Opcode },
8396     { Bad_Opcode },
8397     { Bad_Opcode },
8398     { Bad_Opcode },
8399     { Bad_Opcode },
8400     { Bad_Opcode },
8401     { Bad_Opcode },
8402     { Bad_Opcode },
8403     /* e8 */
8404     { Bad_Opcode },
8405     { Bad_Opcode },
8406     { Bad_Opcode },
8407     { Bad_Opcode },
8408     { Bad_Opcode },
8409     { Bad_Opcode },
8410     { Bad_Opcode },
8411     { Bad_Opcode },
8412     /* f0 */
8413     { Bad_Opcode },
8414     { Bad_Opcode },
8415     { Bad_Opcode },
8416     { Bad_Opcode },
8417     { Bad_Opcode },
8418     { Bad_Opcode },
8419     { Bad_Opcode },
8420     { Bad_Opcode },
8421     /* f8 */
8422     { Bad_Opcode },
8423     { Bad_Opcode },
8424     { Bad_Opcode },
8425     { Bad_Opcode },
8426     { Bad_Opcode },
8427     { Bad_Opcode },
8428     { Bad_Opcode },
8429     { Bad_Opcode },
8430   },
8431 };
8432
8433 static const struct dis386 vex_table[][256] = {
8434   /* VEX_0F */
8435   {
8436     /* 00 */
8437     { Bad_Opcode },
8438     { Bad_Opcode },
8439     { Bad_Opcode },
8440     { Bad_Opcode },
8441     { Bad_Opcode },
8442     { Bad_Opcode },
8443     { Bad_Opcode },
8444     { Bad_Opcode },
8445     /* 08 */
8446     { Bad_Opcode },
8447     { Bad_Opcode },
8448     { Bad_Opcode },
8449     { Bad_Opcode },
8450     { Bad_Opcode },
8451     { Bad_Opcode },
8452     { Bad_Opcode },
8453     { Bad_Opcode },
8454     /* 10 */
8455     { PREFIX_TABLE (PREFIX_VEX_0F10) },
8456     { PREFIX_TABLE (PREFIX_VEX_0F11) },
8457     { PREFIX_TABLE (PREFIX_VEX_0F12) },
8458     { MOD_TABLE (MOD_VEX_0F13) },
8459     { "vunpcklpX",      { XM, Vex, EXx }, 0 },
8460     { "vunpckhpX",      { XM, Vex, EXx }, 0 },
8461     { PREFIX_TABLE (PREFIX_VEX_0F16) },
8462     { MOD_TABLE (MOD_VEX_0F17) },
8463     /* 18 */
8464     { Bad_Opcode },
8465     { Bad_Opcode },
8466     { Bad_Opcode },
8467     { Bad_Opcode },
8468     { Bad_Opcode },
8469     { Bad_Opcode },
8470     { Bad_Opcode },
8471     { Bad_Opcode },
8472     /* 20 */
8473     { Bad_Opcode },
8474     { Bad_Opcode },
8475     { Bad_Opcode },
8476     { Bad_Opcode },
8477     { Bad_Opcode },
8478     { Bad_Opcode },
8479     { Bad_Opcode },
8480     { Bad_Opcode },
8481     /* 28 */
8482     { "vmovapX",        { XM, EXx }, 0 },
8483     { "vmovapX",        { EXxS, XM }, 0 },
8484     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8485     { MOD_TABLE (MOD_VEX_0F2B) },
8486     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8487     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8488     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8489     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8490     /* 30 */
8491     { Bad_Opcode },
8492     { Bad_Opcode },
8493     { Bad_Opcode },
8494     { Bad_Opcode },
8495     { Bad_Opcode },
8496     { Bad_Opcode },
8497     { Bad_Opcode },
8498     { Bad_Opcode },
8499     /* 38 */
8500     { Bad_Opcode },
8501     { Bad_Opcode },
8502     { Bad_Opcode },
8503     { Bad_Opcode },
8504     { Bad_Opcode },
8505     { Bad_Opcode },
8506     { Bad_Opcode },
8507     { Bad_Opcode },
8508     /* 40 */
8509     { Bad_Opcode },
8510     { PREFIX_TABLE (PREFIX_VEX_0F41) },
8511     { PREFIX_TABLE (PREFIX_VEX_0F42) },
8512     { Bad_Opcode },
8513     { PREFIX_TABLE (PREFIX_VEX_0F44) },
8514     { PREFIX_TABLE (PREFIX_VEX_0F45) },
8515     { PREFIX_TABLE (PREFIX_VEX_0F46) },
8516     { PREFIX_TABLE (PREFIX_VEX_0F47) },
8517     /* 48 */
8518     { Bad_Opcode },
8519     { Bad_Opcode },
8520     { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8521     { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8522     { Bad_Opcode },
8523     { Bad_Opcode },
8524     { Bad_Opcode },
8525     { Bad_Opcode },
8526     /* 50 */
8527     { MOD_TABLE (MOD_VEX_0F50) },
8528     { PREFIX_TABLE (PREFIX_VEX_0F51) },
8529     { PREFIX_TABLE (PREFIX_VEX_0F52) },
8530     { PREFIX_TABLE (PREFIX_VEX_0F53) },
8531     { "vandpX",         { XM, Vex, EXx }, 0 },
8532     { "vandnpX",        { XM, Vex, EXx }, 0 },
8533     { "vorpX",          { XM, Vex, EXx }, 0 },
8534     { "vxorpX",         { XM, Vex, EXx }, 0 },
8535     /* 58 */
8536     { PREFIX_TABLE (PREFIX_VEX_0F58) },
8537     { PREFIX_TABLE (PREFIX_VEX_0F59) },
8538     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8539     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8540     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8541     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8542     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8543     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8544     /* 60 */
8545     { PREFIX_TABLE (PREFIX_VEX_0F60) },
8546     { PREFIX_TABLE (PREFIX_VEX_0F61) },
8547     { PREFIX_TABLE (PREFIX_VEX_0F62) },
8548     { PREFIX_TABLE (PREFIX_VEX_0F63) },
8549     { PREFIX_TABLE (PREFIX_VEX_0F64) },
8550     { PREFIX_TABLE (PREFIX_VEX_0F65) },
8551     { PREFIX_TABLE (PREFIX_VEX_0F66) },
8552     { PREFIX_TABLE (PREFIX_VEX_0F67) },
8553     /* 68 */
8554     { PREFIX_TABLE (PREFIX_VEX_0F68) },
8555     { PREFIX_TABLE (PREFIX_VEX_0F69) },
8556     { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8557     { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8558     { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8559     { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8560     { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8561     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8562     /* 70 */
8563     { PREFIX_TABLE (PREFIX_VEX_0F70) },
8564     { REG_TABLE (REG_VEX_0F71) },
8565     { REG_TABLE (REG_VEX_0F72) },
8566     { REG_TABLE (REG_VEX_0F73) },
8567     { PREFIX_TABLE (PREFIX_VEX_0F74) },
8568     { PREFIX_TABLE (PREFIX_VEX_0F75) },
8569     { PREFIX_TABLE (PREFIX_VEX_0F76) },
8570     { PREFIX_TABLE (PREFIX_VEX_0F77) },
8571     /* 78 */
8572     { Bad_Opcode },
8573     { Bad_Opcode },
8574     { Bad_Opcode },
8575     { Bad_Opcode },
8576     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8577     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8578     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8579     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8580     /* 80 */
8581     { Bad_Opcode },
8582     { Bad_Opcode },
8583     { Bad_Opcode },
8584     { Bad_Opcode },
8585     { Bad_Opcode },
8586     { Bad_Opcode },
8587     { Bad_Opcode },
8588     { Bad_Opcode },
8589     /* 88 */
8590     { Bad_Opcode },
8591     { Bad_Opcode },
8592     { Bad_Opcode },
8593     { Bad_Opcode },
8594     { Bad_Opcode },
8595     { Bad_Opcode },
8596     { Bad_Opcode },
8597     { Bad_Opcode },
8598     /* 90 */
8599     { PREFIX_TABLE (PREFIX_VEX_0F90) },
8600     { PREFIX_TABLE (PREFIX_VEX_0F91) },
8601     { PREFIX_TABLE (PREFIX_VEX_0F92) },
8602     { PREFIX_TABLE (PREFIX_VEX_0F93) },
8603     { Bad_Opcode },
8604     { Bad_Opcode },
8605     { Bad_Opcode },
8606     { Bad_Opcode },
8607     /* 98 */
8608     { PREFIX_TABLE (PREFIX_VEX_0F98) },
8609     { PREFIX_TABLE (PREFIX_VEX_0F99) },
8610     { Bad_Opcode },
8611     { Bad_Opcode },
8612     { Bad_Opcode },
8613     { Bad_Opcode },
8614     { Bad_Opcode },
8615     { Bad_Opcode },
8616     /* a0 */
8617     { Bad_Opcode },
8618     { Bad_Opcode },
8619     { Bad_Opcode },
8620     { Bad_Opcode },
8621     { Bad_Opcode },
8622     { Bad_Opcode },
8623     { Bad_Opcode },
8624     { Bad_Opcode },
8625     /* a8 */
8626     { Bad_Opcode },
8627     { Bad_Opcode },
8628     { Bad_Opcode },
8629     { Bad_Opcode },
8630     { Bad_Opcode },
8631     { Bad_Opcode },
8632     { REG_TABLE (REG_VEX_0FAE) },
8633     { Bad_Opcode },
8634     /* b0 */
8635     { Bad_Opcode },
8636     { Bad_Opcode },
8637     { Bad_Opcode },
8638     { Bad_Opcode },
8639     { Bad_Opcode },
8640     { Bad_Opcode },
8641     { Bad_Opcode },
8642     { Bad_Opcode },
8643     /* b8 */
8644     { Bad_Opcode },
8645     { Bad_Opcode },
8646     { Bad_Opcode },
8647     { Bad_Opcode },
8648     { Bad_Opcode },
8649     { Bad_Opcode },
8650     { Bad_Opcode },
8651     { Bad_Opcode },
8652     /* c0 */
8653     { Bad_Opcode },
8654     { Bad_Opcode },
8655     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8656     { Bad_Opcode },
8657     { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8658     { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8659     { "vshufpX",        { XM, Vex, EXx, Ib }, 0 },
8660     { Bad_Opcode },
8661     /* c8 */
8662     { Bad_Opcode },
8663     { Bad_Opcode },
8664     { Bad_Opcode },
8665     { Bad_Opcode },
8666     { Bad_Opcode },
8667     { Bad_Opcode },
8668     { Bad_Opcode },
8669     { Bad_Opcode },
8670     /* d0 */
8671     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8672     { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8673     { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8674     { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8675     { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8676     { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8677     { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8678     { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8679     /* d8 */
8680     { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8681     { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8682     { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8683     { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8684     { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8685     { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8686     { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8687     { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8688     /* e0 */
8689     { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8690     { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8691     { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8692     { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8693     { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8694     { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8695     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8696     { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8697     /* e8 */
8698     { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8699     { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8700     { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8701     { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8702     { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8703     { PREFIX_TABLE (PREFIX_VEX_0FED) },
8704     { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8705     { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8706     /* f0 */
8707     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8708     { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8709     { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8710     { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8711     { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8712     { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8713     { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8714     { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8715     /* f8 */
8716     { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8717     { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8718     { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8719     { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8720     { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8721     { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8722     { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8723     { Bad_Opcode },
8724   },
8725   /* VEX_0F38 */
8726   {
8727     /* 00 */
8728     { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8729     { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8730     { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8731     { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8732     { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8733     { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8734     { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8735     { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8736     /* 08 */
8737     { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8738     { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8739     { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8740     { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8741     { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8742     { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8743     { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8744     { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8745     /* 10 */
8746     { Bad_Opcode },
8747     { Bad_Opcode },
8748     { Bad_Opcode },
8749     { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8750     { Bad_Opcode },
8751     { Bad_Opcode },
8752     { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8753     { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8754     /* 18 */
8755     { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8756     { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8757     { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8758     { Bad_Opcode },
8759     { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8760     { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8761     { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8762     { Bad_Opcode },
8763     /* 20 */
8764     { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8765     { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8766     { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8767     { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8768     { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8769     { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8770     { Bad_Opcode },
8771     { Bad_Opcode },
8772     /* 28 */
8773     { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8774     { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8775     { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8776     { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8777     { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8778     { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8779     { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8780     { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8781     /* 30 */
8782     { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8783     { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8784     { PREFIX_TABLE (PREFIX_VEX_0F3832) },
8785     { PREFIX_TABLE (PREFIX_VEX_0F3833) },
8786     { PREFIX_TABLE (PREFIX_VEX_0F3834) },
8787     { PREFIX_TABLE (PREFIX_VEX_0F3835) },
8788     { PREFIX_TABLE (PREFIX_VEX_0F3836) },
8789     { PREFIX_TABLE (PREFIX_VEX_0F3837) },
8790     /* 38 */
8791     { PREFIX_TABLE (PREFIX_VEX_0F3838) },
8792     { PREFIX_TABLE (PREFIX_VEX_0F3839) },
8793     { PREFIX_TABLE (PREFIX_VEX_0F383A) },
8794     { PREFIX_TABLE (PREFIX_VEX_0F383B) },
8795     { PREFIX_TABLE (PREFIX_VEX_0F383C) },
8796     { PREFIX_TABLE (PREFIX_VEX_0F383D) },
8797     { PREFIX_TABLE (PREFIX_VEX_0F383E) },
8798     { PREFIX_TABLE (PREFIX_VEX_0F383F) },
8799     /* 40 */
8800     { PREFIX_TABLE (PREFIX_VEX_0F3840) },
8801     { PREFIX_TABLE (PREFIX_VEX_0F3841) },
8802     { Bad_Opcode },
8803     { Bad_Opcode },
8804     { Bad_Opcode },
8805     { PREFIX_TABLE (PREFIX_VEX_0F3845) },
8806     { PREFIX_TABLE (PREFIX_VEX_0F3846) },
8807     { PREFIX_TABLE (PREFIX_VEX_0F3847) },
8808     /* 48 */
8809     { Bad_Opcode },
8810     { Bad_Opcode },
8811     { Bad_Opcode },
8812     { Bad_Opcode },
8813     { Bad_Opcode },
8814     { Bad_Opcode },
8815     { Bad_Opcode },
8816     { Bad_Opcode },
8817     /* 50 */
8818     { Bad_Opcode },
8819     { Bad_Opcode },
8820     { Bad_Opcode },
8821     { Bad_Opcode },
8822     { Bad_Opcode },
8823     { Bad_Opcode },
8824     { Bad_Opcode },
8825     { Bad_Opcode },
8826     /* 58 */
8827     { PREFIX_TABLE (PREFIX_VEX_0F3858) },
8828     { PREFIX_TABLE (PREFIX_VEX_0F3859) },
8829     { PREFIX_TABLE (PREFIX_VEX_0F385A) },
8830     { Bad_Opcode },
8831     { Bad_Opcode },
8832     { Bad_Opcode },
8833     { Bad_Opcode },
8834     { Bad_Opcode },
8835     /* 60 */
8836     { Bad_Opcode },
8837     { Bad_Opcode },
8838     { Bad_Opcode },
8839     { Bad_Opcode },
8840     { Bad_Opcode },
8841     { Bad_Opcode },
8842     { Bad_Opcode },
8843     { Bad_Opcode },
8844     /* 68 */
8845     { Bad_Opcode },
8846     { Bad_Opcode },
8847     { Bad_Opcode },
8848     { Bad_Opcode },
8849     { Bad_Opcode },
8850     { Bad_Opcode },
8851     { Bad_Opcode },
8852     { Bad_Opcode },
8853     /* 70 */
8854     { Bad_Opcode },
8855     { Bad_Opcode },
8856     { Bad_Opcode },
8857     { Bad_Opcode },
8858     { Bad_Opcode },
8859     { Bad_Opcode },
8860     { Bad_Opcode },
8861     { Bad_Opcode },
8862     /* 78 */
8863     { PREFIX_TABLE (PREFIX_VEX_0F3878) },
8864     { PREFIX_TABLE (PREFIX_VEX_0F3879) },
8865     { Bad_Opcode },
8866     { Bad_Opcode },
8867     { Bad_Opcode },
8868     { Bad_Opcode },
8869     { Bad_Opcode },
8870     { Bad_Opcode },
8871     /* 80 */
8872     { Bad_Opcode },
8873     { Bad_Opcode },
8874     { Bad_Opcode },
8875     { Bad_Opcode },
8876     { Bad_Opcode },
8877     { Bad_Opcode },
8878     { Bad_Opcode },
8879     { Bad_Opcode },
8880     /* 88 */
8881     { Bad_Opcode },
8882     { Bad_Opcode },
8883     { Bad_Opcode },
8884     { Bad_Opcode },
8885     { PREFIX_TABLE (PREFIX_VEX_0F388C) },
8886     { Bad_Opcode },
8887     { PREFIX_TABLE (PREFIX_VEX_0F388E) },
8888     { Bad_Opcode },
8889     /* 90 */
8890     { PREFIX_TABLE (PREFIX_VEX_0F3890) },
8891     { PREFIX_TABLE (PREFIX_VEX_0F3891) },
8892     { PREFIX_TABLE (PREFIX_VEX_0F3892) },
8893     { PREFIX_TABLE (PREFIX_VEX_0F3893) },
8894     { Bad_Opcode },
8895     { Bad_Opcode },
8896     { PREFIX_TABLE (PREFIX_VEX_0F3896) },
8897     { PREFIX_TABLE (PREFIX_VEX_0F3897) },
8898     /* 98 */
8899     { PREFIX_TABLE (PREFIX_VEX_0F3898) },
8900     { PREFIX_TABLE (PREFIX_VEX_0F3899) },
8901     { PREFIX_TABLE (PREFIX_VEX_0F389A) },
8902     { PREFIX_TABLE (PREFIX_VEX_0F389B) },
8903     { PREFIX_TABLE (PREFIX_VEX_0F389C) },
8904     { PREFIX_TABLE (PREFIX_VEX_0F389D) },
8905     { PREFIX_TABLE (PREFIX_VEX_0F389E) },
8906     { PREFIX_TABLE (PREFIX_VEX_0F389F) },
8907     /* a0 */
8908     { Bad_Opcode },
8909     { Bad_Opcode },
8910     { Bad_Opcode },
8911     { Bad_Opcode },
8912     { Bad_Opcode },
8913     { Bad_Opcode },
8914     { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
8915     { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
8916     /* a8 */
8917     { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
8918     { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
8919     { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
8920     { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
8921     { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
8922     { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
8923     { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
8924     { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
8925     /* b0 */
8926     { Bad_Opcode },
8927     { Bad_Opcode },
8928     { Bad_Opcode },
8929     { Bad_Opcode },
8930     { Bad_Opcode },
8931     { Bad_Opcode },
8932     { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
8933     { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
8934     /* b8 */
8935     { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
8936     { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
8937     { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
8938     { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
8939     { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
8940     { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
8941     { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
8942     { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
8943     /* c0 */
8944     { Bad_Opcode },
8945     { Bad_Opcode },
8946     { Bad_Opcode },
8947     { Bad_Opcode },
8948     { Bad_Opcode },
8949     { Bad_Opcode },
8950     { Bad_Opcode },
8951     { Bad_Opcode },
8952     /* c8 */
8953     { Bad_Opcode },
8954     { Bad_Opcode },
8955     { Bad_Opcode },
8956     { Bad_Opcode },
8957     { Bad_Opcode },
8958     { Bad_Opcode },
8959     { Bad_Opcode },
8960     { PREFIX_TABLE (PREFIX_VEX_0F38CF) },
8961     /* d0 */
8962     { Bad_Opcode },
8963     { Bad_Opcode },
8964     { Bad_Opcode },
8965     { Bad_Opcode },
8966     { Bad_Opcode },
8967     { Bad_Opcode },
8968     { Bad_Opcode },
8969     { Bad_Opcode },
8970     /* d8 */
8971     { Bad_Opcode },
8972     { Bad_Opcode },
8973     { Bad_Opcode },
8974     { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
8975     { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
8976     { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
8977     { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
8978     { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
8979     /* e0 */
8980     { Bad_Opcode },
8981     { Bad_Opcode },
8982     { Bad_Opcode },
8983     { Bad_Opcode },
8984     { Bad_Opcode },
8985     { Bad_Opcode },
8986     { Bad_Opcode },
8987     { Bad_Opcode },
8988     /* e8 */
8989     { Bad_Opcode },
8990     { Bad_Opcode },
8991     { Bad_Opcode },
8992     { Bad_Opcode },
8993     { Bad_Opcode },
8994     { Bad_Opcode },
8995     { Bad_Opcode },
8996     { Bad_Opcode },
8997     /* f0 */
8998     { Bad_Opcode },
8999     { Bad_Opcode },
9000     { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
9001     { REG_TABLE (REG_VEX_0F38F3) },
9002     { Bad_Opcode },
9003     { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
9004     { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
9005     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
9006     /* f8 */
9007     { Bad_Opcode },
9008     { Bad_Opcode },
9009     { Bad_Opcode },
9010     { Bad_Opcode },
9011     { Bad_Opcode },
9012     { Bad_Opcode },
9013     { Bad_Opcode },
9014     { Bad_Opcode },
9015   },
9016   /* VEX_0F3A */
9017   {
9018     /* 00 */
9019     { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
9020     { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
9021     { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
9022     { Bad_Opcode },
9023     { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
9024     { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
9025     { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
9026     { Bad_Opcode },
9027     /* 08 */
9028     { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
9029     { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
9030     { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
9031     { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
9032     { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
9033     { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
9034     { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
9035     { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
9036     /* 10 */
9037     { Bad_Opcode },
9038     { Bad_Opcode },
9039     { Bad_Opcode },
9040     { Bad_Opcode },
9041     { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
9042     { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
9043     { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
9044     { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
9045     /* 18 */
9046     { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
9047     { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
9048     { Bad_Opcode },
9049     { Bad_Opcode },
9050     { Bad_Opcode },
9051     { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
9052     { Bad_Opcode },
9053     { Bad_Opcode },
9054     /* 20 */
9055     { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
9056     { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
9057     { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
9058     { Bad_Opcode },
9059     { Bad_Opcode },
9060     { Bad_Opcode },
9061     { Bad_Opcode },
9062     { Bad_Opcode },
9063     /* 28 */
9064     { Bad_Opcode },
9065     { Bad_Opcode },
9066     { Bad_Opcode },
9067     { Bad_Opcode },
9068     { Bad_Opcode },
9069     { Bad_Opcode },
9070     { Bad_Opcode },
9071     { Bad_Opcode },
9072     /* 30 */
9073     { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
9074     { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
9075     { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
9076     { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
9077     { Bad_Opcode },
9078     { Bad_Opcode },
9079     { Bad_Opcode },
9080     { Bad_Opcode },
9081     /* 38 */
9082     { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
9083     { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
9084     { Bad_Opcode },
9085     { Bad_Opcode },
9086     { Bad_Opcode },
9087     { Bad_Opcode },
9088     { Bad_Opcode },
9089     { Bad_Opcode },
9090     /* 40 */
9091     { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
9092     { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
9093     { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
9094     { Bad_Opcode },
9095     { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
9096     { Bad_Opcode },
9097     { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
9098     { Bad_Opcode },
9099     /* 48 */
9100     { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
9101     { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
9102     { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
9103     { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
9104     { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
9105     { Bad_Opcode },
9106     { Bad_Opcode },
9107     { Bad_Opcode },
9108     /* 50 */
9109     { Bad_Opcode },
9110     { Bad_Opcode },
9111     { Bad_Opcode },
9112     { Bad_Opcode },
9113     { Bad_Opcode },
9114     { Bad_Opcode },
9115     { Bad_Opcode },
9116     { Bad_Opcode },
9117     /* 58 */
9118     { Bad_Opcode },
9119     { Bad_Opcode },
9120     { Bad_Opcode },
9121     { Bad_Opcode },
9122     { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9123     { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9124     { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9125     { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9126     /* 60 */
9127     { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9128     { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9129     { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9130     { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9131     { Bad_Opcode },
9132     { Bad_Opcode },
9133     { Bad_Opcode },
9134     { Bad_Opcode },
9135     /* 68 */
9136     { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9137     { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9138     { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9139     { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9140     { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9141     { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9142     { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9143     { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9144     /* 70 */
9145     { Bad_Opcode },
9146     { Bad_Opcode },
9147     { Bad_Opcode },
9148     { Bad_Opcode },
9149     { Bad_Opcode },
9150     { Bad_Opcode },
9151     { Bad_Opcode },
9152     { Bad_Opcode },
9153     /* 78 */
9154     { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9155     { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9156     { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9157     { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9158     { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9159     { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9160     { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9161     { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9162     /* 80 */
9163     { Bad_Opcode },
9164     { Bad_Opcode },
9165     { Bad_Opcode },
9166     { Bad_Opcode },
9167     { Bad_Opcode },
9168     { Bad_Opcode },
9169     { Bad_Opcode },
9170     { Bad_Opcode },
9171     /* 88 */
9172     { Bad_Opcode },
9173     { Bad_Opcode },
9174     { Bad_Opcode },
9175     { Bad_Opcode },
9176     { Bad_Opcode },
9177     { Bad_Opcode },
9178     { Bad_Opcode },
9179     { Bad_Opcode },
9180     /* 90 */
9181     { Bad_Opcode },
9182     { Bad_Opcode },
9183     { Bad_Opcode },
9184     { Bad_Opcode },
9185     { Bad_Opcode },
9186     { Bad_Opcode },
9187     { Bad_Opcode },
9188     { Bad_Opcode },
9189     /* 98 */
9190     { Bad_Opcode },
9191     { Bad_Opcode },
9192     { Bad_Opcode },
9193     { Bad_Opcode },
9194     { Bad_Opcode },
9195     { Bad_Opcode },
9196     { Bad_Opcode },
9197     { Bad_Opcode },
9198     /* a0 */
9199     { Bad_Opcode },
9200     { Bad_Opcode },
9201     { Bad_Opcode },
9202     { Bad_Opcode },
9203     { Bad_Opcode },
9204     { Bad_Opcode },
9205     { Bad_Opcode },
9206     { Bad_Opcode },
9207     /* a8 */
9208     { Bad_Opcode },
9209     { Bad_Opcode },
9210     { Bad_Opcode },
9211     { Bad_Opcode },
9212     { Bad_Opcode },
9213     { Bad_Opcode },
9214     { Bad_Opcode },
9215     { Bad_Opcode },
9216     /* b0 */
9217     { Bad_Opcode },
9218     { Bad_Opcode },
9219     { Bad_Opcode },
9220     { Bad_Opcode },
9221     { Bad_Opcode },
9222     { Bad_Opcode },
9223     { Bad_Opcode },
9224     { Bad_Opcode },
9225     /* b8 */
9226     { Bad_Opcode },
9227     { Bad_Opcode },
9228     { Bad_Opcode },
9229     { Bad_Opcode },
9230     { Bad_Opcode },
9231     { Bad_Opcode },
9232     { Bad_Opcode },
9233     { Bad_Opcode },
9234     /* c0 */
9235     { Bad_Opcode },
9236     { Bad_Opcode },
9237     { Bad_Opcode },
9238     { Bad_Opcode },
9239     { Bad_Opcode },
9240     { Bad_Opcode },
9241     { Bad_Opcode },
9242     { Bad_Opcode },
9243     /* c8 */
9244     { Bad_Opcode },
9245     { Bad_Opcode },
9246     { Bad_Opcode },
9247     { Bad_Opcode },
9248     { Bad_Opcode },
9249     { Bad_Opcode },
9250     { PREFIX_TABLE(PREFIX_VEX_0F3ACE) },
9251     { PREFIX_TABLE(PREFIX_VEX_0F3ACF) },
9252     /* d0 */
9253     { Bad_Opcode },
9254     { Bad_Opcode },
9255     { Bad_Opcode },
9256     { Bad_Opcode },
9257     { Bad_Opcode },
9258     { Bad_Opcode },
9259     { Bad_Opcode },
9260     { Bad_Opcode },
9261     /* d8 */
9262     { Bad_Opcode },
9263     { Bad_Opcode },
9264     { Bad_Opcode },
9265     { Bad_Opcode },
9266     { Bad_Opcode },
9267     { Bad_Opcode },
9268     { Bad_Opcode },
9269     { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9270     /* e0 */
9271     { Bad_Opcode },
9272     { Bad_Opcode },
9273     { Bad_Opcode },
9274     { Bad_Opcode },
9275     { Bad_Opcode },
9276     { Bad_Opcode },
9277     { Bad_Opcode },
9278     { Bad_Opcode },
9279     /* e8 */
9280     { Bad_Opcode },
9281     { Bad_Opcode },
9282     { Bad_Opcode },
9283     { Bad_Opcode },
9284     { Bad_Opcode },
9285     { Bad_Opcode },
9286     { Bad_Opcode },
9287     { Bad_Opcode },
9288     /* f0 */
9289     { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9290     { Bad_Opcode },
9291     { Bad_Opcode },
9292     { Bad_Opcode },
9293     { Bad_Opcode },
9294     { Bad_Opcode },
9295     { Bad_Opcode },
9296     { Bad_Opcode },
9297     /* f8 */
9298     { Bad_Opcode },
9299     { Bad_Opcode },
9300     { Bad_Opcode },
9301     { Bad_Opcode },
9302     { Bad_Opcode },
9303     { Bad_Opcode },
9304     { Bad_Opcode },
9305     { Bad_Opcode },
9306   },
9307 };
9308
9309 #include "i386-dis-evex.h"
9310
9311 static const struct dis386 vex_len_table[][2] = {
9312   /* VEX_LEN_0F12_P_0_M_0 */
9313   {
9314     { "vmovlps",        { XM, Vex128, EXq }, 0 },
9315   },
9316
9317   /* VEX_LEN_0F12_P_0_M_1 */
9318   {
9319     { "vmovhlps",       { XM, Vex128, EXq }, 0 },
9320   },
9321
9322   /* VEX_LEN_0F12_P_2 */
9323   {
9324     { "vmovlpd",        { XM, Vex128, EXq }, 0 },
9325   },
9326
9327   /* VEX_LEN_0F13_M_0 */
9328   {
9329     { "vmovlpX",        { EXq, XM }, 0 },
9330   },
9331
9332   /* VEX_LEN_0F16_P_0_M_0 */
9333   {
9334     { "vmovhps",        { XM, Vex128, EXq }, 0 },
9335   },
9336
9337   /* VEX_LEN_0F16_P_0_M_1 */
9338   {
9339     { "vmovlhps",       { XM, Vex128, EXq }, 0 },
9340   },
9341
9342   /* VEX_LEN_0F16_P_2 */
9343   {
9344     { "vmovhpd",        { XM, Vex128, EXq }, 0 },
9345   },
9346
9347   /* VEX_LEN_0F17_M_0 */
9348   {
9349     { "vmovhpX",        { EXq, XM }, 0 },
9350   },
9351
9352   /* VEX_LEN_0F41_P_0 */
9353   {
9354     { Bad_Opcode },
9355     { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9356   },
9357   /* VEX_LEN_0F41_P_2 */
9358   {
9359     { Bad_Opcode },
9360     { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9361   },
9362   /* VEX_LEN_0F42_P_0 */
9363   {
9364     { Bad_Opcode },
9365     { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9366   },
9367   /* VEX_LEN_0F42_P_2 */
9368   {
9369     { Bad_Opcode },
9370     { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9371   },
9372   /* VEX_LEN_0F44_P_0 */
9373   {
9374     { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9375   },
9376   /* VEX_LEN_0F44_P_2 */
9377   {
9378     { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9379   },
9380   /* VEX_LEN_0F45_P_0 */
9381   {
9382     { Bad_Opcode },
9383     { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9384   },
9385   /* VEX_LEN_0F45_P_2 */
9386   {
9387     { Bad_Opcode },
9388     { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9389   },
9390   /* VEX_LEN_0F46_P_0 */
9391   {
9392     { Bad_Opcode },
9393     { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9394   },
9395   /* VEX_LEN_0F46_P_2 */
9396   {
9397     { Bad_Opcode },
9398     { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9399   },
9400   /* VEX_LEN_0F47_P_0 */
9401   {
9402     { Bad_Opcode },
9403     { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9404   },
9405   /* VEX_LEN_0F47_P_2 */
9406   {
9407     { Bad_Opcode },
9408     { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9409   },
9410   /* VEX_LEN_0F4A_P_0 */
9411   {
9412     { Bad_Opcode },
9413     { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9414   },
9415   /* VEX_LEN_0F4A_P_2 */
9416   {
9417     { Bad_Opcode },
9418     { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9419   },
9420   /* VEX_LEN_0F4B_P_0 */
9421   {
9422     { Bad_Opcode },
9423     { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9424   },
9425   /* VEX_LEN_0F4B_P_2 */
9426   {
9427     { Bad_Opcode },
9428     { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9429   },
9430
9431   /* VEX_LEN_0F6E_P_2 */
9432   {
9433     { "vmovK",          { XMScalar, Edq }, 0 },
9434   },
9435
9436   /* VEX_LEN_0F77_P_1 */
9437   {
9438     { "vzeroupper",     { XX }, 0 },
9439     { "vzeroall",       { XX }, 0 },
9440   },
9441
9442   /* VEX_LEN_0F7E_P_1 */
9443   {
9444     { "vmovq",          { XMScalar, EXqScalar }, 0 },
9445   },
9446
9447   /* VEX_LEN_0F7E_P_2 */
9448   {
9449     { "vmovK",          { Edq, XMScalar }, 0 },
9450   },
9451
9452   /* VEX_LEN_0F90_P_0 */
9453   {
9454     { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9455   },
9456
9457   /* VEX_LEN_0F90_P_2 */
9458   {
9459     { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9460   },
9461
9462   /* VEX_LEN_0F91_P_0 */
9463   {
9464     { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9465   },
9466
9467   /* VEX_LEN_0F91_P_2 */
9468   {
9469     { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
9470   },
9471
9472   /* VEX_LEN_0F92_P_0 */
9473   {
9474     { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9475   },
9476
9477   /* VEX_LEN_0F92_P_2 */
9478   {
9479     { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
9480   },
9481
9482   /* VEX_LEN_0F92_P_3 */
9483   {
9484     { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0) },
9485   },
9486
9487   /* VEX_LEN_0F93_P_0 */
9488   {
9489     { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9490   },
9491
9492   /* VEX_LEN_0F93_P_2 */
9493   {
9494     { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
9495   },
9496
9497   /* VEX_LEN_0F93_P_3 */
9498   {
9499     { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0) },
9500   },
9501
9502   /* VEX_LEN_0F98_P_0 */
9503   {
9504     { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9505   },
9506
9507   /* VEX_LEN_0F98_P_2 */
9508   {
9509     { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
9510   },
9511
9512   /* VEX_LEN_0F99_P_0 */
9513   {
9514     { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
9515   },
9516
9517   /* VEX_LEN_0F99_P_2 */
9518   {
9519     { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
9520   },
9521
9522   /* VEX_LEN_0FAE_R_2_M_0 */
9523   {
9524     { "vldmxcsr",       { Md }, 0 },
9525   },
9526
9527   /* VEX_LEN_0FAE_R_3_M_0 */
9528   {
9529     { "vstmxcsr",       { Md }, 0 },
9530   },
9531
9532   /* VEX_LEN_0FC4_P_2 */
9533   {
9534     { "vpinsrw",        { XM, Vex128, Edqw, Ib }, 0 },
9535   },
9536
9537   /* VEX_LEN_0FC5_P_2 */
9538   {
9539     { "vpextrw",        { Gdq, XS, Ib }, 0 },
9540   },
9541
9542   /* VEX_LEN_0FD6_P_2 */
9543   {
9544     { "vmovq",          { EXqScalarS, XMScalar }, 0 },
9545   },
9546
9547   /* VEX_LEN_0FF7_P_2 */
9548   {
9549     { "vmaskmovdqu",    { XM, XS }, 0 },
9550   },
9551
9552   /* VEX_LEN_0F3816_P_2 */
9553   {
9554     { Bad_Opcode },
9555     { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9556   },
9557
9558   /* VEX_LEN_0F3819_P_2 */
9559   {
9560     { Bad_Opcode },
9561     { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9562   },
9563
9564   /* VEX_LEN_0F381A_P_2_M_0 */
9565   {
9566     { Bad_Opcode },
9567     { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9568   },
9569
9570   /* VEX_LEN_0F3836_P_2 */
9571   {
9572     { Bad_Opcode },
9573     { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9574   },
9575
9576   /* VEX_LEN_0F3841_P_2 */
9577   {
9578     { "vphminposuw",    { XM, EXx }, 0 },
9579   },
9580
9581   /* VEX_LEN_0F385A_P_2_M_0 */
9582   {
9583     { Bad_Opcode },
9584     { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
9585   },
9586
9587   /* VEX_LEN_0F38DB_P_2 */
9588   {
9589     { "vaesimc",        { XM, EXx }, 0 },
9590   },
9591
9592   /* VEX_LEN_0F38F2_P_0 */
9593   {
9594     { "andnS",          { Gdq, VexGdq, Edq }, 0 },
9595   },
9596
9597   /* VEX_LEN_0F38F3_R_1_P_0 */
9598   {
9599     { "blsrS",          { VexGdq, Edq }, 0 },
9600   },
9601
9602   /* VEX_LEN_0F38F3_R_2_P_0 */
9603   {
9604     { "blsmskS",        { VexGdq, Edq }, 0 },
9605   },
9606
9607   /* VEX_LEN_0F38F3_R_3_P_0 */
9608   {
9609     { "blsiS",          { VexGdq, Edq }, 0 },
9610   },
9611
9612   /* VEX_LEN_0F38F5_P_0 */
9613   {
9614     { "bzhiS",          { Gdq, Edq, VexGdq }, 0 },
9615   },
9616
9617   /* VEX_LEN_0F38F5_P_1 */
9618   {
9619     { "pextS",          { Gdq, VexGdq, Edq }, 0 },
9620   },
9621
9622   /* VEX_LEN_0F38F5_P_3 */
9623   {
9624     { "pdepS",          { Gdq, VexGdq, Edq }, 0 },
9625   },
9626
9627   /* VEX_LEN_0F38F6_P_3 */
9628   {
9629     { "mulxS",          { Gdq, VexGdq, Edq }, 0 },
9630   },
9631
9632   /* VEX_LEN_0F38F7_P_0 */
9633   {
9634     { "bextrS",         { Gdq, Edq, VexGdq }, 0 },
9635   },
9636
9637   /* VEX_LEN_0F38F7_P_1 */
9638   {
9639     { "sarxS",          { Gdq, Edq, VexGdq }, 0 },
9640   },
9641
9642   /* VEX_LEN_0F38F7_P_2 */
9643   {
9644     { "shlxS",          { Gdq, Edq, VexGdq }, 0 },
9645   },
9646
9647   /* VEX_LEN_0F38F7_P_3 */
9648   {
9649     { "shrxS",          { Gdq, Edq, VexGdq }, 0 },
9650   },
9651
9652   /* VEX_LEN_0F3A00_P_2 */
9653   {
9654     { Bad_Opcode },
9655     { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
9656   },
9657
9658   /* VEX_LEN_0F3A01_P_2 */
9659   {
9660     { Bad_Opcode },
9661     { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
9662   },
9663
9664   /* VEX_LEN_0F3A06_P_2 */
9665   {
9666     { Bad_Opcode },
9667     { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
9668   },
9669
9670   /* VEX_LEN_0F3A14_P_2 */
9671   {
9672     { "vpextrb",        { Edqb, XM, Ib }, 0 },
9673   },
9674
9675   /* VEX_LEN_0F3A15_P_2 */
9676   {
9677     { "vpextrw",        { Edqw, XM, Ib }, 0 },
9678   },
9679
9680   /* VEX_LEN_0F3A16_P_2  */
9681   {
9682     { "vpextrK",        { Edq, XM, Ib }, 0 },
9683   },
9684
9685   /* VEX_LEN_0F3A17_P_2 */
9686   {
9687     { "vextractps",     { Edqd, XM, Ib }, 0 },
9688   },
9689
9690   /* VEX_LEN_0F3A18_P_2 */
9691   {
9692     { Bad_Opcode },
9693     { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
9694   },
9695
9696   /* VEX_LEN_0F3A19_P_2 */
9697   {
9698     { Bad_Opcode },
9699     { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
9700   },
9701
9702   /* VEX_LEN_0F3A20_P_2 */
9703   {
9704     { "vpinsrb",        { XM, Vex128, Edqb, Ib }, 0 },
9705   },
9706
9707   /* VEX_LEN_0F3A21_P_2 */
9708   {
9709     { "vinsertps",      { XM, Vex128, EXd, Ib }, 0 },
9710   },
9711
9712   /* VEX_LEN_0F3A22_P_2 */
9713   {
9714     { "vpinsrK",        { XM, Vex128, Edq, Ib }, 0 },
9715   },
9716
9717   /* VEX_LEN_0F3A30_P_2 */
9718   {
9719     { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
9720   },
9721
9722   /* VEX_LEN_0F3A31_P_2 */
9723   {
9724     { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
9725   },
9726
9727   /* VEX_LEN_0F3A32_P_2 */
9728   {
9729     { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
9730   },
9731
9732   /* VEX_LEN_0F3A33_P_2 */
9733   {
9734     { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
9735   },
9736
9737   /* VEX_LEN_0F3A38_P_2 */
9738   {
9739     { Bad_Opcode },
9740     { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
9741   },
9742
9743   /* VEX_LEN_0F3A39_P_2 */
9744   {
9745     { Bad_Opcode },
9746     { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
9747   },
9748
9749   /* VEX_LEN_0F3A41_P_2 */
9750   {
9751     { "vdppd",          { XM, Vex128, EXx, Ib }, 0 },
9752   },
9753
9754   /* VEX_LEN_0F3A46_P_2 */
9755   {
9756     { Bad_Opcode },
9757     { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
9758   },
9759
9760   /* VEX_LEN_0F3A60_P_2 */
9761   {
9762     { "vpcmpestrm",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
9763   },
9764
9765   /* VEX_LEN_0F3A61_P_2 */
9766   {
9767     { "vpcmpestri",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
9768   },
9769
9770   /* VEX_LEN_0F3A62_P_2 */
9771   {
9772     { "vpcmpistrm",     { XM, EXx, Ib }, 0 },
9773   },
9774
9775   /* VEX_LEN_0F3A63_P_2 */
9776   {
9777     { "vpcmpistri",     { XM, EXx, Ib }, 0 },
9778   },
9779
9780   /* VEX_LEN_0F3A6A_P_2 */
9781   {
9782     { "vfmaddss",       { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9783   },
9784
9785   /* VEX_LEN_0F3A6B_P_2 */
9786   {
9787     { "vfmaddsd",       { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9788   },
9789
9790   /* VEX_LEN_0F3A6E_P_2 */
9791   {
9792     { "vfmsubss",       { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9793   },
9794
9795   /* VEX_LEN_0F3A6F_P_2 */
9796   {
9797     { "vfmsubsd",       { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9798   },
9799
9800   /* VEX_LEN_0F3A7A_P_2 */
9801   {
9802     { "vfnmaddss",      { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9803   },
9804
9805   /* VEX_LEN_0F3A7B_P_2 */
9806   {
9807     { "vfnmaddsd",      { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9808   },
9809
9810   /* VEX_LEN_0F3A7E_P_2 */
9811   {
9812     { "vfnmsubss",      { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9813   },
9814
9815   /* VEX_LEN_0F3A7F_P_2 */
9816   {
9817     { "vfnmsubsd",      { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9818   },
9819
9820   /* VEX_LEN_0F3ADF_P_2 */
9821   {
9822     { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
9823   },
9824
9825   /* VEX_LEN_0F3AF0_P_3 */
9826   {
9827     { "rorxS",          { Gdq, Edq, Ib }, 0 },
9828   },
9829
9830   /* VEX_LEN_0FXOP_08_CC */
9831   {
9832      { "vpcomb",        { XM, Vex128, EXx, VPCOM }, 0 },
9833   },
9834
9835   /* VEX_LEN_0FXOP_08_CD */
9836   {
9837      { "vpcomw",        { XM, Vex128, EXx, VPCOM }, 0 },
9838   },
9839
9840   /* VEX_LEN_0FXOP_08_CE */
9841   {
9842      { "vpcomd",        { XM, Vex128, EXx, VPCOM }, 0 },
9843   },
9844
9845   /* VEX_LEN_0FXOP_08_CF */
9846   {
9847      { "vpcomq",        { XM, Vex128, EXx, VPCOM }, 0 },
9848   },
9849
9850   /* VEX_LEN_0FXOP_08_EC */
9851   {
9852      { "vpcomub",       { XM, Vex128, EXx, VPCOM }, 0 },
9853   },
9854
9855   /* VEX_LEN_0FXOP_08_ED */
9856   {
9857      { "vpcomuw",       { XM, Vex128, EXx, VPCOM }, 0 },
9858   },
9859
9860   /* VEX_LEN_0FXOP_08_EE */
9861   {
9862      { "vpcomud",       { XM, Vex128, EXx, VPCOM }, 0 },
9863   },
9864
9865   /* VEX_LEN_0FXOP_08_EF */
9866   {
9867      { "vpcomuq",       { XM, Vex128, EXx, VPCOM }, 0 },
9868   },
9869
9870   /* VEX_LEN_0FXOP_09_80 */
9871   {
9872     { "vfrczps",        { XM, EXxmm }, 0 },
9873     { "vfrczps",        { XM, EXymmq }, 0 },
9874   },
9875
9876   /* VEX_LEN_0FXOP_09_81 */
9877   {
9878     { "vfrczpd",        { XM, EXxmm }, 0 },
9879     { "vfrczpd",        { XM, EXymmq }, 0 },
9880   },
9881 };
9882
9883 #include "i386-dis-evex-len.h"
9884
9885 static const struct dis386 vex_w_table[][2] = {
9886   {
9887     /* VEX_W_0F41_P_0_LEN_1 */
9888     { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
9889     { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) },
9890   },
9891   {
9892     /* VEX_W_0F41_P_2_LEN_1 */
9893     { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) },
9894     { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) }
9895   },
9896   {
9897     /* VEX_W_0F42_P_0_LEN_1 */
9898     { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) },
9899     { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) },
9900   },
9901   {
9902     /* VEX_W_0F42_P_2_LEN_1 */
9903     { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) },
9904     { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) },
9905   },
9906   {
9907     /* VEX_W_0F44_P_0_LEN_0 */
9908     { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) },
9909     { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) },
9910   },
9911   {
9912     /* VEX_W_0F44_P_2_LEN_0 */
9913     { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) },
9914     { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) },
9915   },
9916   {
9917     /* VEX_W_0F45_P_0_LEN_1 */
9918     { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) },
9919     { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) },
9920   },
9921   {
9922     /* VEX_W_0F45_P_2_LEN_1 */
9923     { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) },
9924     { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) },
9925   },
9926   {
9927     /* VEX_W_0F46_P_0_LEN_1 */
9928     { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) },
9929     { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) },
9930   },
9931   {
9932     /* VEX_W_0F46_P_2_LEN_1 */
9933     { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) },
9934     { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) },
9935   },
9936   {
9937     /* VEX_W_0F47_P_0_LEN_1 */
9938     { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) },
9939     { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) },
9940   },
9941   {
9942     /* VEX_W_0F47_P_2_LEN_1 */
9943     { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) },
9944     { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) },
9945   },
9946   {
9947     /* VEX_W_0F4A_P_0_LEN_1 */
9948     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) },
9949     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) },
9950   },
9951   {
9952     /* VEX_W_0F4A_P_2_LEN_1 */
9953     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) },
9954     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) },
9955   },
9956   {
9957     /* VEX_W_0F4B_P_0_LEN_1 */
9958     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) },
9959     { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) },
9960   },
9961   {
9962     /* VEX_W_0F4B_P_2_LEN_1 */
9963     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
9964   },
9965   {
9966     /* VEX_W_0F90_P_0_LEN_0 */
9967     { "kmovw",          { MaskG, MaskE }, 0 },
9968     { "kmovq",          { MaskG, MaskE }, 0 },
9969   },
9970   {
9971     /* VEX_W_0F90_P_2_LEN_0 */
9972     { "kmovb",          { MaskG, MaskBDE }, 0 },
9973     { "kmovd",          { MaskG, MaskBDE }, 0 },
9974   },
9975   {
9976     /* VEX_W_0F91_P_0_LEN_0 */
9977     { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
9978     { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
9979   },
9980   {
9981     /* VEX_W_0F91_P_2_LEN_0 */
9982     { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
9983     { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
9984   },
9985   {
9986     /* VEX_W_0F92_P_0_LEN_0 */
9987     { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
9988   },
9989   {
9990     /* VEX_W_0F92_P_2_LEN_0 */
9991     { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
9992   },
9993   {
9994     /* VEX_W_0F93_P_0_LEN_0 */
9995     { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
9996   },
9997   {
9998     /* VEX_W_0F93_P_2_LEN_0 */
9999     { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
10000   },
10001   {
10002     /* VEX_W_0F98_P_0_LEN_0 */
10003     { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
10004     { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
10005   },
10006   {
10007     /* VEX_W_0F98_P_2_LEN_0 */
10008     { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
10009     { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
10010   },
10011   {
10012     /* VEX_W_0F99_P_0_LEN_0 */
10013     { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
10014     { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
10015   },
10016   {
10017     /* VEX_W_0F99_P_2_LEN_0 */
10018     { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
10019     { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
10020   },
10021   {
10022     /* VEX_W_0F380C_P_2  */
10023     { "vpermilps",      { XM, Vex, EXx }, 0 },
10024   },
10025   {
10026     /* VEX_W_0F380D_P_2  */
10027     { "vpermilpd",      { XM, Vex, EXx }, 0 },
10028   },
10029   {
10030     /* VEX_W_0F380E_P_2  */
10031     { "vtestps",        { XM, EXx }, 0 },
10032   },
10033   {
10034     /* VEX_W_0F380F_P_2  */
10035     { "vtestpd",        { XM, EXx }, 0 },
10036   },
10037   {
10038     /* VEX_W_0F3816_P_2  */
10039     { "vpermps",        { XM, Vex, EXx }, 0 },
10040   },
10041   {
10042     /* VEX_W_0F3818_P_2 */
10043     { "vbroadcastss",   { XM, EXxmm_md }, 0 },
10044   },
10045   {
10046     /* VEX_W_0F3819_P_2 */
10047     { "vbroadcastsd",   { XM, EXxmm_mq }, 0 },
10048   },
10049   {
10050     /* VEX_W_0F381A_P_2_M_0 */
10051     { "vbroadcastf128", { XM, Mxmm }, 0 },
10052   },
10053   {
10054     /* VEX_W_0F382C_P_2_M_0 */
10055     { "vmaskmovps",     { XM, Vex, Mx }, 0 },
10056   },
10057   {
10058     /* VEX_W_0F382D_P_2_M_0 */
10059     { "vmaskmovpd",     { XM, Vex, Mx }, 0 },
10060   },
10061   {
10062     /* VEX_W_0F382E_P_2_M_0 */
10063     { "vmaskmovps",     { Mx, Vex, XM }, 0 },
10064   },
10065   {
10066     /* VEX_W_0F382F_P_2_M_0 */
10067     { "vmaskmovpd",     { Mx, Vex, XM }, 0 },
10068   },
10069   {
10070     /* VEX_W_0F3836_P_2  */
10071     { "vpermd",         { XM, Vex, EXx }, 0 },
10072   },
10073   {
10074     /* VEX_W_0F3846_P_2 */
10075     { "vpsravd",        { XM, Vex, EXx }, 0 },
10076   },
10077   {
10078     /* VEX_W_0F3858_P_2 */
10079     { "vpbroadcastd", { XM, EXxmm_md }, 0 },
10080   },
10081   {
10082     /* VEX_W_0F3859_P_2 */
10083     { "vpbroadcastq",   { XM, EXxmm_mq }, 0 },
10084   },
10085   {
10086     /* VEX_W_0F385A_P_2_M_0 */
10087     { "vbroadcasti128", { XM, Mxmm }, 0 },
10088   },
10089   {
10090     /* VEX_W_0F3878_P_2 */
10091     { "vpbroadcastb",   { XM, EXxmm_mb }, 0 },
10092   },
10093   {
10094     /* VEX_W_0F3879_P_2 */
10095     { "vpbroadcastw",   { XM, EXxmm_mw }, 0 },
10096   },
10097   {
10098     /* VEX_W_0F38CF_P_2 */
10099     { "vgf2p8mulb", { XM, Vex, EXx }, 0 },
10100   },
10101   {
10102     /* VEX_W_0F3A00_P_2 */
10103     { Bad_Opcode },
10104     { "vpermq",         { XM, EXx, Ib }, 0 },
10105   },
10106   {
10107     /* VEX_W_0F3A01_P_2 */
10108     { Bad_Opcode },
10109     { "vpermpd",        { XM, EXx, Ib }, 0 },
10110   },
10111   {
10112     /* VEX_W_0F3A02_P_2 */
10113     { "vpblendd",       { XM, Vex, EXx, Ib }, 0 },
10114   },
10115   {
10116     /* VEX_W_0F3A04_P_2 */
10117     { "vpermilps",      { XM, EXx, Ib }, 0 },
10118   },
10119   {
10120     /* VEX_W_0F3A05_P_2 */
10121     { "vpermilpd",      { XM, EXx, Ib }, 0 },
10122   },
10123   {
10124     /* VEX_W_0F3A06_P_2 */
10125     { "vperm2f128",     { XM, Vex256, EXx, Ib }, 0 },
10126   },
10127   {
10128     /* VEX_W_0F3A18_P_2 */
10129     { "vinsertf128",    { XM, Vex256, EXxmm, Ib }, 0 },
10130   },
10131   {
10132     /* VEX_W_0F3A19_P_2 */
10133     { "vextractf128",   { EXxmm, XM, Ib }, 0 },
10134   },
10135   {
10136     /* VEX_W_0F3A30_P_2_LEN_0 */
10137     { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) },
10138     { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) },
10139   },
10140   {
10141     /* VEX_W_0F3A31_P_2_LEN_0 */
10142     { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) },
10143     { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) },
10144   },
10145   {
10146     /* VEX_W_0F3A32_P_2_LEN_0 */
10147     { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) },
10148     { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) },
10149   },
10150   {
10151     /* VEX_W_0F3A33_P_2_LEN_0 */
10152     { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) },
10153     { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) },
10154   },
10155   {
10156     /* VEX_W_0F3A38_P_2 */
10157     { "vinserti128",    { XM, Vex256, EXxmm, Ib }, 0 },
10158   },
10159   {
10160     /* VEX_W_0F3A39_P_2 */
10161     { "vextracti128",   { EXxmm, XM, Ib }, 0 },
10162   },
10163   {
10164     /* VEX_W_0F3A46_P_2 */
10165     { "vperm2i128",     { XM, Vex256, EXx, Ib }, 0 },
10166   },
10167   {
10168     /* VEX_W_0F3A48_P_2 */
10169     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10170     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10171   },
10172   {
10173     /* VEX_W_0F3A49_P_2 */
10174     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10175     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10176   },
10177   {
10178     /* VEX_W_0F3A4A_P_2 */
10179     { "vblendvps",      { XM, Vex, EXx, XMVexI4 }, 0 },
10180   },
10181   {
10182     /* VEX_W_0F3A4B_P_2 */
10183     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 }, 0 },
10184   },
10185   {
10186     /* VEX_W_0F3A4C_P_2 */
10187     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 }, 0 },
10188   },
10189   {
10190     /* VEX_W_0F3ACE_P_2 */
10191     { Bad_Opcode },
10192     { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, 0 },
10193   },
10194   {
10195     /* VEX_W_0F3ACF_P_2 */
10196     { Bad_Opcode },
10197     { "vgf2p8affineinvqb",  { XM, Vex, EXx, Ib }, 0 },
10198   },
10199
10200 #include "i386-dis-evex-w.h"
10201 };
10202
10203 static const struct dis386 mod_table[][2] = {
10204   {
10205     /* MOD_8D */
10206     { "leaS",           { Gv, M }, 0 },
10207   },
10208   {
10209     /* MOD_C6_REG_7 */
10210     { Bad_Opcode },
10211     { RM_TABLE (RM_C6_REG_7) },
10212   },
10213   {
10214     /* MOD_C7_REG_7 */
10215     { Bad_Opcode },
10216     { RM_TABLE (RM_C7_REG_7) },
10217   },
10218   {
10219     /* MOD_FF_REG_3 */
10220     { "Jcall^", { indirEp }, 0 },
10221   },
10222   {
10223     /* MOD_FF_REG_5 */
10224     { "Jjmp^", { indirEp }, 0 },
10225   },
10226   {
10227     /* MOD_0F01_REG_0 */
10228     { X86_64_TABLE (X86_64_0F01_REG_0) },
10229     { RM_TABLE (RM_0F01_REG_0) },
10230   },
10231   {
10232     /* MOD_0F01_REG_1 */
10233     { X86_64_TABLE (X86_64_0F01_REG_1) },
10234     { RM_TABLE (RM_0F01_REG_1) },
10235   },
10236   {
10237     /* MOD_0F01_REG_2 */
10238     { X86_64_TABLE (X86_64_0F01_REG_2) },
10239     { RM_TABLE (RM_0F01_REG_2) },
10240   },
10241   {
10242     /* MOD_0F01_REG_3 */
10243     { X86_64_TABLE (X86_64_0F01_REG_3) },
10244     { RM_TABLE (RM_0F01_REG_3) },
10245   },
10246   {
10247     /* MOD_0F01_REG_5 */
10248     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0) },
10249     { RM_TABLE (RM_0F01_REG_5_MOD_3) },
10250   },
10251   {
10252     /* MOD_0F01_REG_7 */
10253     { "invlpg",         { Mb }, 0 },
10254     { RM_TABLE (RM_0F01_REG_7_MOD_3) },
10255   },
10256   {
10257     /* MOD_0F12_PREFIX_0 */
10258     { "movlps",         { XM, EXq }, PREFIX_OPCODE },
10259     { "movhlps",        { XM, EXq }, PREFIX_OPCODE },
10260   },
10261   {
10262     /* MOD_0F13 */
10263     { "movlpX",         { EXq, XM }, PREFIX_OPCODE },
10264   },
10265   {
10266     /* MOD_0F16_PREFIX_0 */
10267     { "movhps",         { XM, EXq }, 0 },
10268     { "movlhps",        { XM, EXq }, 0 },
10269   },
10270   {
10271     /* MOD_0F17 */
10272     { "movhpX",         { EXq, XM }, PREFIX_OPCODE },
10273   },
10274   {
10275     /* MOD_0F18_REG_0 */
10276     { "prefetchnta",    { Mb }, 0 },
10277   },
10278   {
10279     /* MOD_0F18_REG_1 */
10280     { "prefetcht0",     { Mb }, 0 },
10281   },
10282   {
10283     /* MOD_0F18_REG_2 */
10284     { "prefetcht1",     { Mb }, 0 },
10285   },
10286   {
10287     /* MOD_0F18_REG_3 */
10288     { "prefetcht2",     { Mb }, 0 },
10289   },
10290   {
10291     /* MOD_0F18_REG_4 */
10292     { "nop/reserved",   { Mb }, 0 },
10293   },
10294   {
10295     /* MOD_0F18_REG_5 */
10296     { "nop/reserved",   { Mb }, 0 },
10297   },
10298   {
10299     /* MOD_0F18_REG_6 */
10300     { "nop/reserved",   { Mb }, 0 },
10301   },
10302   {
10303     /* MOD_0F18_REG_7 */
10304     { "nop/reserved",   { Mb }, 0 },
10305   },
10306   {
10307     /* MOD_0F1A_PREFIX_0 */
10308     { "bndldx",         { Gbnd, Mv_bnd }, 0 },
10309     { "nopQ",           { Ev }, 0 },
10310   },
10311   {
10312     /* MOD_0F1B_PREFIX_0 */
10313     { "bndstx",         { Mv_bnd, Gbnd }, 0 },
10314     { "nopQ",           { Ev }, 0 },
10315   },
10316   {
10317     /* MOD_0F1B_PREFIX_1 */
10318     { "bndmk",          { Gbnd, Mv_bnd }, 0 },
10319     { "nopQ",           { Ev }, 0 },
10320   },
10321   {
10322     /* MOD_0F1C_PREFIX_0 */
10323     { REG_TABLE (REG_0F1C_P_0_MOD_0) },
10324     { "nopQ",           { Ev }, 0 },
10325   },
10326   {
10327     /* MOD_0F1E_PREFIX_1 */
10328     { "nopQ",           { Ev }, 0 },
10329     { REG_TABLE (REG_0F1E_P_1_MOD_3) },
10330   },
10331   {
10332     /* MOD_0F24 */
10333     { Bad_Opcode },
10334     { "movL",           { Rd, Td }, 0 },
10335   },
10336   {
10337     /* MOD_0F26 */
10338     { Bad_Opcode },
10339     { "movL",           { Td, Rd }, 0 },
10340   },
10341   {
10342     /* MOD_0F2B_PREFIX_0 */
10343     {"movntps",         { Mx, XM }, PREFIX_OPCODE },
10344   },
10345   {
10346     /* MOD_0F2B_PREFIX_1 */
10347     {"movntss",         { Md, XM }, PREFIX_OPCODE },
10348   },
10349   {
10350     /* MOD_0F2B_PREFIX_2 */
10351     {"movntpd",         { Mx, XM }, PREFIX_OPCODE },
10352   },
10353   {
10354     /* MOD_0F2B_PREFIX_3 */
10355     {"movntsd",         { Mq, XM }, PREFIX_OPCODE },
10356   },
10357   {
10358     /* MOD_0F51 */
10359     { Bad_Opcode },
10360     { "movmskpX",       { Gdq, XS }, PREFIX_OPCODE },
10361   },
10362   {
10363     /* MOD_0F71_REG_2 */
10364     { Bad_Opcode },
10365     { "psrlw",          { MS, Ib }, 0 },
10366   },
10367   {
10368     /* MOD_0F71_REG_4 */
10369     { Bad_Opcode },
10370     { "psraw",          { MS, Ib }, 0 },
10371   },
10372   {
10373     /* MOD_0F71_REG_6 */
10374     { Bad_Opcode },
10375     { "psllw",          { MS, Ib }, 0 },
10376   },
10377   {
10378     /* MOD_0F72_REG_2 */
10379     { Bad_Opcode },
10380     { "psrld",          { MS, Ib }, 0 },
10381   },
10382   {
10383     /* MOD_0F72_REG_4 */
10384     { Bad_Opcode },
10385     { "psrad",          { MS, Ib }, 0 },
10386   },
10387   {
10388     /* MOD_0F72_REG_6 */
10389     { Bad_Opcode },
10390     { "pslld",          { MS, Ib }, 0 },
10391   },
10392   {
10393     /* MOD_0F73_REG_2 */
10394     { Bad_Opcode },
10395     { "psrlq",          { MS, Ib }, 0 },
10396   },
10397   {
10398     /* MOD_0F73_REG_3 */
10399     { Bad_Opcode },
10400     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
10401   },
10402   {
10403     /* MOD_0F73_REG_6 */
10404     { Bad_Opcode },
10405     { "psllq",          { MS, Ib }, 0 },
10406   },
10407   {
10408     /* MOD_0F73_REG_7 */
10409     { Bad_Opcode },
10410     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
10411   },
10412   {
10413     /* MOD_0FAE_REG_0 */
10414     { "fxsave",         { FXSAVE }, 0 },
10415     { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3) },
10416   },
10417   {
10418     /* MOD_0FAE_REG_1 */
10419     { "fxrstor",        { FXSAVE }, 0 },
10420     { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3) },
10421   },
10422   {
10423     /* MOD_0FAE_REG_2 */
10424     { "ldmxcsr",        { Md }, 0 },
10425     { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3) },
10426   },
10427   {
10428     /* MOD_0FAE_REG_3 */
10429     { "stmxcsr",        { Md }, 0 },
10430     { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3) },
10431   },
10432   {
10433     /* MOD_0FAE_REG_4 */
10434     { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0) },
10435     { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3) },
10436   },
10437   {
10438     /* MOD_0FAE_REG_5 */
10439     { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_0) },
10440     { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3) },
10441   },
10442   {
10443     /* MOD_0FAE_REG_6 */
10444     { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0) },
10445     { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3) },
10446   },
10447   {
10448     /* MOD_0FAE_REG_7 */
10449     { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0) },
10450     { RM_TABLE (RM_0FAE_REG_7_MOD_3) },
10451   },
10452   {
10453     /* MOD_0FB2 */
10454     { "lssS",           { Gv, Mp }, 0 },
10455   },
10456   {
10457     /* MOD_0FB4 */
10458     { "lfsS",           { Gv, Mp }, 0 },
10459   },
10460   {
10461     /* MOD_0FB5 */
10462     { "lgsS",           { Gv, Mp }, 0 },
10463   },
10464   {
10465     /* MOD_0FC3 */
10466     { PREFIX_TABLE (PREFIX_0FC3_MOD_0) },
10467   },
10468   {
10469     /* MOD_0FC7_REG_3 */
10470     { "xrstors",        { FXSAVE }, 0 },
10471   },
10472   {
10473     /* MOD_0FC7_REG_4 */
10474     { "xsavec",         { FXSAVE }, 0 },
10475   },
10476   {
10477     /* MOD_0FC7_REG_5 */
10478     { "xsaves",         { FXSAVE }, 0 },
10479   },
10480   {
10481     /* MOD_0FC7_REG_6 */
10482     { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0) },
10483     { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3) }
10484   },
10485   {
10486     /* MOD_0FC7_REG_7 */
10487     { "vmptrst",        { Mq }, 0 },
10488     { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3) }
10489   },
10490   {
10491     /* MOD_0FD7 */
10492     { Bad_Opcode },
10493     { "pmovmskb",       { Gdq, MS }, 0 },
10494   },
10495   {
10496     /* MOD_0FE7_PREFIX_2 */
10497     { "movntdq",        { Mx, XM }, 0 },
10498   },
10499   {
10500     /* MOD_0FF0_PREFIX_3 */
10501     { "lddqu",          { XM, M }, 0 },
10502   },
10503   {
10504     /* MOD_0F382A_PREFIX_2 */
10505     { "movntdqa",       { XM, Mx }, 0 },
10506   },
10507   {
10508     /* MOD_0F38F5_PREFIX_2 */
10509     { "wrussK",         { M, Gdq }, PREFIX_OPCODE },
10510   },
10511   {
10512     /* MOD_0F38F6_PREFIX_0 */
10513     { "wrssK",          { M, Gdq }, PREFIX_OPCODE },
10514   },
10515   {
10516     /* MOD_0F38F8_PREFIX_1 */
10517     { "enqcmds",        { Gva, M }, PREFIX_OPCODE },
10518   },
10519   {
10520     /* MOD_0F38F8_PREFIX_2 */
10521     { "movdir64b",      { Gva, M }, PREFIX_OPCODE },
10522   },
10523   {
10524     /* MOD_0F38F8_PREFIX_3 */
10525     { "enqcmd",         { Gva, M }, PREFIX_OPCODE },
10526   },
10527   {
10528     /* MOD_0F38F9_PREFIX_0 */
10529     { "movdiri",        { Ev, Gv }, PREFIX_OPCODE },
10530   },
10531   {
10532     /* MOD_62_32BIT */
10533     { "bound{S|}",      { Gv, Ma }, 0 },
10534     { EVEX_TABLE (EVEX_0F) },
10535   },
10536   {
10537     /* MOD_C4_32BIT */
10538     { "lesS",           { Gv, Mp }, 0 },
10539     { VEX_C4_TABLE (VEX_0F) },
10540   },
10541   {
10542     /* MOD_C5_32BIT */
10543     { "ldsS",           { Gv, Mp }, 0 },
10544     { VEX_C5_TABLE (VEX_0F) },
10545   },
10546   {
10547     /* MOD_VEX_0F12_PREFIX_0 */
10548     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
10549     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
10550   },
10551   {
10552     /* MOD_VEX_0F13 */
10553     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
10554   },
10555   {
10556     /* MOD_VEX_0F16_PREFIX_0 */
10557     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
10558     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
10559   },
10560   {
10561     /* MOD_VEX_0F17 */
10562     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
10563   },
10564   {
10565     /* MOD_VEX_0F2B */
10566     { "vmovntpX",       { Mx, XM }, 0 },
10567   },
10568   {
10569     /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
10570     { Bad_Opcode },
10571     { "kandw",          { MaskG, MaskVex, MaskR }, 0 },
10572   },
10573   {
10574     /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
10575     { Bad_Opcode },
10576     { "kandq",          { MaskG, MaskVex, MaskR }, 0 },
10577   },
10578   {
10579     /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
10580     { Bad_Opcode },
10581     { "kandb",          { MaskG, MaskVex, MaskR }, 0 },
10582   },
10583   {
10584     /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
10585     { Bad_Opcode },
10586     { "kandd",          { MaskG, MaskVex, MaskR }, 0 },
10587   },
10588   {
10589     /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
10590     { Bad_Opcode },
10591     { "kandnw",         { MaskG, MaskVex, MaskR }, 0 },
10592   },
10593   {
10594     /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
10595     { Bad_Opcode },
10596     { "kandnq",         { MaskG, MaskVex, MaskR }, 0 },
10597   },
10598   {
10599     /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
10600     { Bad_Opcode },
10601     { "kandnb",         { MaskG, MaskVex, MaskR }, 0 },
10602   },
10603   {
10604     /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
10605     { Bad_Opcode },
10606     { "kandnd",         { MaskG, MaskVex, MaskR }, 0 },
10607   },
10608   {
10609     /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
10610     { Bad_Opcode },
10611     { "knotw",          { MaskG, MaskR }, 0 },
10612   },
10613   {
10614     /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
10615     { Bad_Opcode },
10616     { "knotq",          { MaskG, MaskR }, 0 },
10617   },
10618   {
10619     /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
10620     { Bad_Opcode },
10621     { "knotb",          { MaskG, MaskR }, 0 },
10622   },
10623   {
10624     /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
10625     { Bad_Opcode },
10626     { "knotd",          { MaskG, MaskR }, 0 },
10627   },
10628   {
10629     /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
10630     { Bad_Opcode },
10631     { "korw",       { MaskG, MaskVex, MaskR }, 0 },
10632   },
10633   {
10634     /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
10635     { Bad_Opcode },
10636     { "korq",       { MaskG, MaskVex, MaskR }, 0 },
10637   },
10638   {
10639     /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
10640     { Bad_Opcode },
10641     { "korb",       { MaskG, MaskVex, MaskR }, 0 },
10642   },
10643   {
10644     /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
10645     { Bad_Opcode },
10646     { "kord",       { MaskG, MaskVex, MaskR }, 0 },
10647   },
10648  {
10649     /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
10650     { Bad_Opcode },
10651     { "kxnorw",     { MaskG, MaskVex, MaskR }, 0 },
10652   },
10653   {
10654     /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
10655     { Bad_Opcode },
10656     { "kxnorq",     { MaskG, MaskVex, MaskR }, 0 },
10657   },
10658   {
10659     /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
10660     { Bad_Opcode },
10661     { "kxnorb",     { MaskG, MaskVex, MaskR }, 0 },
10662   },
10663   {
10664     /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
10665     { Bad_Opcode },
10666     { "kxnord",     { MaskG, MaskVex, MaskR }, 0 },
10667   },
10668   {
10669     /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
10670     { Bad_Opcode },
10671     { "kxorw",      { MaskG, MaskVex, MaskR }, 0 },
10672   },
10673   {
10674     /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
10675     { Bad_Opcode },
10676     { "kxorq",      { MaskG, MaskVex, MaskR }, 0 },
10677   },
10678   {
10679     /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
10680     { Bad_Opcode },
10681     { "kxorb",      { MaskG, MaskVex, MaskR }, 0 },
10682   },
10683   {
10684     /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
10685     { Bad_Opcode },
10686     { "kxord",      { MaskG, MaskVex, MaskR }, 0 },
10687   },
10688   {
10689     /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
10690     { Bad_Opcode },
10691     { "kaddw",          { MaskG, MaskVex, MaskR }, 0 },
10692   },
10693   {
10694     /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
10695     { Bad_Opcode },
10696     { "kaddq",          { MaskG, MaskVex, MaskR }, 0 },
10697   },
10698   {
10699     /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
10700     { Bad_Opcode },
10701     { "kaddb",          { MaskG, MaskVex, MaskR }, 0 },
10702   },
10703   {
10704     /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
10705     { Bad_Opcode },
10706     { "kaddd",          { MaskG, MaskVex, MaskR }, 0 },
10707   },
10708   {
10709     /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
10710     { Bad_Opcode },
10711     { "kunpckwd",   { MaskG, MaskVex, MaskR }, 0 },
10712   },
10713   {
10714     /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
10715     { Bad_Opcode },
10716     { "kunpckdq",   { MaskG, MaskVex, MaskR }, 0 },
10717   },
10718   {
10719     /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
10720     { Bad_Opcode },
10721     { "kunpckbw",   { MaskG, MaskVex, MaskR }, 0 },
10722   },
10723   {
10724     /* MOD_VEX_0F50 */
10725     { Bad_Opcode },
10726     { "vmovmskpX",      { Gdq, XS }, 0 },
10727   },
10728   {
10729     /* MOD_VEX_0F71_REG_2 */
10730     { Bad_Opcode },
10731     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
10732   },
10733   {
10734     /* MOD_VEX_0F71_REG_4 */
10735     { Bad_Opcode },
10736     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
10737   },
10738   {
10739     /* MOD_VEX_0F71_REG_6 */
10740     { Bad_Opcode },
10741     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
10742   },
10743   {
10744     /* MOD_VEX_0F72_REG_2 */
10745     { Bad_Opcode },
10746     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
10747   },
10748   {
10749     /* MOD_VEX_0F72_REG_4 */
10750     { Bad_Opcode },
10751     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
10752   },
10753   {
10754     /* MOD_VEX_0F72_REG_6 */
10755     { Bad_Opcode },
10756     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
10757   },
10758   {
10759     /* MOD_VEX_0F73_REG_2 */
10760     { Bad_Opcode },
10761     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
10762   },
10763   {
10764     /* MOD_VEX_0F73_REG_3 */
10765     { Bad_Opcode },
10766     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
10767   },
10768   {
10769     /* MOD_VEX_0F73_REG_6 */
10770     { Bad_Opcode },
10771     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
10772   },
10773   {
10774     /* MOD_VEX_0F73_REG_7 */
10775     { Bad_Opcode },
10776     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
10777   },
10778   {
10779     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10780     { "kmovw",          { Ew, MaskG }, 0 },
10781     { Bad_Opcode },
10782   },
10783   {
10784     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10785     { "kmovq",          { Eq, MaskG }, 0 },
10786     { Bad_Opcode },
10787   },
10788   {
10789     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10790     { "kmovb",          { Eb, MaskG }, 0 },
10791     { Bad_Opcode },
10792   },
10793   {
10794     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10795     { "kmovd",          { Ed, MaskG }, 0 },
10796     { Bad_Opcode },
10797   },
10798   {
10799     /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
10800     { Bad_Opcode },
10801     { "kmovw",          { MaskG, Rdq }, 0 },
10802   },
10803   {
10804     /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
10805     { Bad_Opcode },
10806     { "kmovb",          { MaskG, Rdq }, 0 },
10807   },
10808   {
10809     /* MOD_VEX_0F92_P_3_LEN_0 */
10810     { Bad_Opcode },
10811     { "kmovK",          { MaskG, Rdq }, 0 },
10812   },
10813   {
10814     /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
10815     { Bad_Opcode },
10816     { "kmovw",          { Gdq, MaskR }, 0 },
10817   },
10818   {
10819     /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
10820     { Bad_Opcode },
10821     { "kmovb",          { Gdq, MaskR }, 0 },
10822   },
10823   {
10824     /* MOD_VEX_0F93_P_3_LEN_0 */
10825     { Bad_Opcode },
10826     { "kmovK",          { Gdq, MaskR }, 0 },
10827   },
10828   {
10829     /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
10830     { Bad_Opcode },
10831     { "kortestw", { MaskG, MaskR }, 0 },
10832   },
10833   {
10834     /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
10835     { Bad_Opcode },
10836     { "kortestq", { MaskG, MaskR }, 0 },
10837   },
10838   {
10839     /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
10840     { Bad_Opcode },
10841     { "kortestb", { MaskG, MaskR }, 0 },
10842   },
10843   {
10844     /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
10845     { Bad_Opcode },
10846     { "kortestd", { MaskG, MaskR }, 0 },
10847   },
10848   {
10849     /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
10850     { Bad_Opcode },
10851     { "ktestw", { MaskG, MaskR }, 0 },
10852   },
10853   {
10854     /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
10855     { Bad_Opcode },
10856     { "ktestq", { MaskG, MaskR }, 0 },
10857   },
10858   {
10859     /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
10860     { Bad_Opcode },
10861     { "ktestb", { MaskG, MaskR }, 0 },
10862   },
10863   {
10864     /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
10865     { Bad_Opcode },
10866     { "ktestd", { MaskG, MaskR }, 0 },
10867   },
10868   {
10869     /* MOD_VEX_0FAE_REG_2 */
10870     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
10871   },
10872   {
10873     /* MOD_VEX_0FAE_REG_3 */
10874     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
10875   },
10876   {
10877     /* MOD_VEX_0FD7_PREFIX_2 */
10878     { Bad_Opcode },
10879     { "vpmovmskb",      { Gdq, XS }, 0 },
10880   },
10881   {
10882     /* MOD_VEX_0FE7_PREFIX_2 */
10883     { "vmovntdq",       { Mx, XM }, 0 },
10884   },
10885   {
10886     /* MOD_VEX_0FF0_PREFIX_3 */
10887     { "vlddqu",         { XM, M }, 0 },
10888   },
10889   {
10890     /* MOD_VEX_0F381A_PREFIX_2 */
10891     { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
10892   },
10893   {
10894     /* MOD_VEX_0F382A_PREFIX_2 */
10895     { "vmovntdqa",      { XM, Mx }, 0 },
10896   },
10897   {
10898     /* MOD_VEX_0F382C_PREFIX_2 */
10899     { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
10900   },
10901   {
10902     /* MOD_VEX_0F382D_PREFIX_2 */
10903     { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
10904   },
10905   {
10906     /* MOD_VEX_0F382E_PREFIX_2 */
10907     { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
10908   },
10909   {
10910     /* MOD_VEX_0F382F_PREFIX_2 */
10911     { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
10912   },
10913   {
10914     /* MOD_VEX_0F385A_PREFIX_2 */
10915     { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
10916   },
10917   {
10918     /* MOD_VEX_0F388C_PREFIX_2 */
10919     { "vpmaskmov%LW",   { XM, Vex, Mx }, 0 },
10920   },
10921   {
10922     /* MOD_VEX_0F388E_PREFIX_2 */
10923     { "vpmaskmov%LW",   { Mx, Vex, XM }, 0 },
10924   },
10925   {
10926     /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
10927     { Bad_Opcode },
10928     { "kshiftrb",       { MaskG, MaskR, Ib }, 0 },
10929   },
10930   {
10931     /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
10932     { Bad_Opcode },
10933     { "kshiftrw",       { MaskG, MaskR, Ib }, 0 },
10934   },
10935   {
10936     /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
10937     { Bad_Opcode },
10938     { "kshiftrd",       { MaskG, MaskR, Ib }, 0 },
10939   },
10940   {
10941     /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
10942     { Bad_Opcode },
10943     { "kshiftrq",       { MaskG, MaskR, Ib }, 0 },
10944   },
10945   {
10946     /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
10947     { Bad_Opcode },
10948     { "kshiftlb",       { MaskG, MaskR, Ib }, 0 },
10949   },
10950   {
10951     /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
10952     { Bad_Opcode },
10953     { "kshiftlw",       { MaskG, MaskR, Ib }, 0 },
10954   },
10955   {
10956     /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
10957     { Bad_Opcode },
10958     { "kshiftld",       { MaskG, MaskR, Ib }, 0 },
10959   },
10960   {
10961     /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
10962     { Bad_Opcode },
10963     { "kshiftlq",       { MaskG, MaskR, Ib }, 0 },
10964   },
10965
10966 #include "i386-dis-evex-mod.h"
10967 };
10968
10969 static const struct dis386 rm_table[][8] = {
10970   {
10971     /* RM_C6_REG_7 */
10972     { "xabort",         { Skip_MODRM, Ib }, 0 },
10973   },
10974   {
10975     /* RM_C7_REG_7 */
10976     { "xbeginT",        { Skip_MODRM, Jdqw }, 0 },
10977   },
10978   {
10979     /* RM_0F01_REG_0 */
10980     { "enclv",          { Skip_MODRM }, 0 },
10981     { "vmcall",         { Skip_MODRM }, 0 },
10982     { "vmlaunch",       { Skip_MODRM }, 0 },
10983     { "vmresume",       { Skip_MODRM }, 0 },
10984     { "vmxoff",         { Skip_MODRM }, 0 },
10985     { "pconfig",        { Skip_MODRM }, 0 },
10986   },
10987   {
10988     /* RM_0F01_REG_1 */
10989     { "monitor",        { { OP_Monitor, 0 } }, 0 },
10990     { "mwait",          { { OP_Mwait, 0 } }, 0 },
10991     { "clac",           { Skip_MODRM }, 0 },
10992     { "stac",           { Skip_MODRM }, 0 },
10993     { Bad_Opcode },
10994     { Bad_Opcode },
10995     { Bad_Opcode },
10996     { "encls",          { Skip_MODRM }, 0 },
10997   },
10998   {
10999     /* RM_0F01_REG_2 */
11000     { "xgetbv",         { Skip_MODRM }, 0 },
11001     { "xsetbv",         { Skip_MODRM }, 0 },
11002     { Bad_Opcode },
11003     { Bad_Opcode },
11004     { "vmfunc",         { Skip_MODRM }, 0 },
11005     { "xend",           { Skip_MODRM }, 0 },
11006     { "xtest",          { Skip_MODRM }, 0 },
11007     { "enclu",          { Skip_MODRM }, 0 },
11008   },
11009   {
11010     /* RM_0F01_REG_3 */
11011     { "vmrun",          { Skip_MODRM }, 0 },
11012     { "vmmcall",        { Skip_MODRM }, 0 },
11013     { "vmload",         { Skip_MODRM }, 0 },
11014     { "vmsave",         { Skip_MODRM }, 0 },
11015     { "stgi",           { Skip_MODRM }, 0 },
11016     { "clgi",           { Skip_MODRM }, 0 },
11017     { "skinit",         { Skip_MODRM }, 0 },
11018     { "invlpga",        { Skip_MODRM }, 0 },
11019   },
11020   {
11021     /* RM_0F01_REG_5_MOD_3 */
11022     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0) },
11023     { Bad_Opcode },
11024     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2) },
11025     { Bad_Opcode },
11026     { Bad_Opcode },
11027     { Bad_Opcode },
11028     { "rdpkru",         { Skip_MODRM }, 0 },
11029     { "wrpkru",         { Skip_MODRM }, 0 },
11030   },
11031   {
11032     /* RM_0F01_REG_7_MOD_3 */
11033     { "swapgs",         { Skip_MODRM }, 0  },
11034     { "rdtscp",         { Skip_MODRM }, 0  },
11035     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2) },
11036     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_3) },
11037     { "clzero",         { Skip_MODRM }, 0  },
11038     { "rdpru",          { Skip_MODRM }, 0  },
11039   },
11040   {
11041     /* RM_0F1E_P_1_MOD_3_REG_7 */
11042     { "nopQ",           { Ev }, 0 },
11043     { "nopQ",           { Ev }, 0 },
11044     { "endbr64",        { Skip_MODRM },  PREFIX_OPCODE },
11045     { "endbr32",        { Skip_MODRM },  PREFIX_OPCODE },
11046     { "nopQ",           { Ev }, 0 },
11047     { "nopQ",           { Ev }, 0 },
11048     { "nopQ",           { Ev }, 0 },
11049     { "nopQ",           { Ev }, 0 },
11050   },
11051   {
11052     /* RM_0FAE_REG_6_MOD_3 */
11053     { "mfence",         { Skip_MODRM }, 0 },
11054   },
11055   {
11056     /* RM_0FAE_REG_7_MOD_3 */
11057     { "sfence",         { Skip_MODRM }, 0 },
11058
11059   },
11060 };
11061
11062 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
11063
11064 /* We use the high bit to indicate different name for the same
11065    prefix.  */
11066 #define REP_PREFIX      (0xf3 | 0x100)
11067 #define XACQUIRE_PREFIX (0xf2 | 0x200)
11068 #define XRELEASE_PREFIX (0xf3 | 0x400)
11069 #define BND_PREFIX      (0xf2 | 0x400)
11070 #define NOTRACK_PREFIX  (0x3e | 0x100)
11071
11072 /* Remember if the current op is a jump instruction.  */
11073 static bfd_boolean op_is_jump = FALSE;
11074
11075 static int
11076 ckprefix (void)
11077 {
11078   int newrex, i, length;
11079   rex = 0;
11080   rex_ignored = 0;
11081   prefixes = 0;
11082   used_prefixes = 0;
11083   rex_used = 0;
11084   last_lock_prefix = -1;
11085   last_repz_prefix = -1;
11086   last_repnz_prefix = -1;
11087   last_data_prefix = -1;
11088   last_addr_prefix = -1;
11089   last_rex_prefix = -1;
11090   last_seg_prefix = -1;
11091   fwait_prefix = -1;
11092   active_seg_prefix = 0;
11093   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
11094     all_prefixes[i] = 0;
11095   i = 0;
11096   length = 0;
11097   /* The maximum instruction length is 15bytes.  */
11098   while (length < MAX_CODE_LENGTH - 1)
11099     {
11100       FETCH_DATA (the_info, codep + 1);
11101       newrex = 0;
11102       switch (*codep)
11103         {
11104         /* REX prefixes family.  */
11105         case 0x40:
11106         case 0x41:
11107         case 0x42:
11108         case 0x43:
11109         case 0x44:
11110         case 0x45:
11111         case 0x46:
11112         case 0x47:
11113         case 0x48:
11114         case 0x49:
11115         case 0x4a:
11116         case 0x4b:
11117         case 0x4c:
11118         case 0x4d:
11119         case 0x4e:
11120         case 0x4f:
11121           if (address_mode == mode_64bit)
11122             newrex = *codep;
11123           else
11124             return 1;
11125           last_rex_prefix = i;
11126           break;
11127         case 0xf3:
11128           prefixes |= PREFIX_REPZ;
11129           last_repz_prefix = i;
11130           break;
11131         case 0xf2:
11132           prefixes |= PREFIX_REPNZ;
11133           last_repnz_prefix = i;
11134           break;
11135         case 0xf0:
11136           prefixes |= PREFIX_LOCK;
11137           last_lock_prefix = i;
11138           break;
11139         case 0x2e:
11140           prefixes |= PREFIX_CS;
11141           last_seg_prefix = i;
11142           active_seg_prefix = PREFIX_CS;
11143           break;
11144         case 0x36:
11145           prefixes |= PREFIX_SS;
11146           last_seg_prefix = i;
11147           active_seg_prefix = PREFIX_SS;
11148           break;
11149         case 0x3e:
11150           prefixes |= PREFIX_DS;
11151           last_seg_prefix = i;
11152           active_seg_prefix = PREFIX_DS;
11153           break;
11154         case 0x26:
11155           prefixes |= PREFIX_ES;
11156           last_seg_prefix = i;
11157           active_seg_prefix = PREFIX_ES;
11158           break;
11159         case 0x64:
11160           prefixes |= PREFIX_FS;
11161           last_seg_prefix = i;
11162           active_seg_prefix = PREFIX_FS;
11163           break;
11164         case 0x65:
11165           prefixes |= PREFIX_GS;
11166           last_seg_prefix = i;
11167           active_seg_prefix = PREFIX_GS;
11168           break;
11169         case 0x66:
11170           prefixes |= PREFIX_DATA;
11171           last_data_prefix = i;
11172           break;
11173         case 0x67:
11174           prefixes |= PREFIX_ADDR;
11175           last_addr_prefix = i;
11176           break;
11177         case FWAIT_OPCODE:
11178           /* fwait is really an instruction.  If there are prefixes
11179              before the fwait, they belong to the fwait, *not* to the
11180              following instruction.  */
11181           fwait_prefix = i;
11182           if (prefixes || rex)
11183             {
11184               prefixes |= PREFIX_FWAIT;
11185               codep++;
11186               /* This ensures that the previous REX prefixes are noticed
11187                  as unused prefixes, as in the return case below.  */
11188               rex_used = rex;
11189               return 1;
11190             }
11191           prefixes = PREFIX_FWAIT;
11192           break;
11193         default:
11194           return 1;
11195         }
11196       /* Rex is ignored when followed by another prefix.  */
11197       if (rex)
11198         {
11199           rex_used = rex;
11200           return 1;
11201         }
11202       if (*codep != FWAIT_OPCODE)
11203         all_prefixes[i++] = *codep;
11204       rex = newrex;
11205       codep++;
11206       length++;
11207     }
11208   return 0;
11209 }
11210
11211 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
11212    prefix byte.  */
11213
11214 static const char *
11215 prefix_name (int pref, int sizeflag)
11216 {
11217   static const char *rexes [16] =
11218     {
11219       "rex",            /* 0x40 */
11220       "rex.B",          /* 0x41 */
11221       "rex.X",          /* 0x42 */
11222       "rex.XB",         /* 0x43 */
11223       "rex.R",          /* 0x44 */
11224       "rex.RB",         /* 0x45 */
11225       "rex.RX",         /* 0x46 */
11226       "rex.RXB",        /* 0x47 */
11227       "rex.W",          /* 0x48 */
11228       "rex.WB",         /* 0x49 */
11229       "rex.WX",         /* 0x4a */
11230       "rex.WXB",        /* 0x4b */
11231       "rex.WR",         /* 0x4c */
11232       "rex.WRB",        /* 0x4d */
11233       "rex.WRX",        /* 0x4e */
11234       "rex.WRXB",       /* 0x4f */
11235     };
11236
11237   switch (pref)
11238     {
11239     /* REX prefixes family.  */
11240     case 0x40:
11241     case 0x41:
11242     case 0x42:
11243     case 0x43:
11244     case 0x44:
11245     case 0x45:
11246     case 0x46:
11247     case 0x47:
11248     case 0x48:
11249     case 0x49:
11250     case 0x4a:
11251     case 0x4b:
11252     case 0x4c:
11253     case 0x4d:
11254     case 0x4e:
11255     case 0x4f:
11256       return rexes [pref - 0x40];
11257     case 0xf3:
11258       return "repz";
11259     case 0xf2:
11260       return "repnz";
11261     case 0xf0:
11262       return "lock";
11263     case 0x2e:
11264       return "cs";
11265     case 0x36:
11266       return "ss";
11267     case 0x3e:
11268       return "ds";
11269     case 0x26:
11270       return "es";
11271     case 0x64:
11272       return "fs";
11273     case 0x65:
11274       return "gs";
11275     case 0x66:
11276       return (sizeflag & DFLAG) ? "data16" : "data32";
11277     case 0x67:
11278       if (address_mode == mode_64bit)
11279         return (sizeflag & AFLAG) ? "addr32" : "addr64";
11280       else
11281         return (sizeflag & AFLAG) ? "addr16" : "addr32";
11282     case FWAIT_OPCODE:
11283       return "fwait";
11284     case REP_PREFIX:
11285       return "rep";
11286     case XACQUIRE_PREFIX:
11287       return "xacquire";
11288     case XRELEASE_PREFIX:
11289       return "xrelease";
11290     case BND_PREFIX:
11291       return "bnd";
11292     case NOTRACK_PREFIX:
11293       return "notrack";
11294     default:
11295       return NULL;
11296     }
11297 }
11298
11299 static char op_out[MAX_OPERANDS][100];
11300 static int op_ad, op_index[MAX_OPERANDS];
11301 static int two_source_ops;
11302 static bfd_vma op_address[MAX_OPERANDS];
11303 static bfd_vma op_riprel[MAX_OPERANDS];
11304 static bfd_vma start_pc;
11305
11306 /*
11307  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
11308  *   (see topic "Redundant prefixes" in the "Differences from 8086"
11309  *   section of the "Virtual 8086 Mode" chapter.)
11310  * 'pc' should be the address of this instruction, it will
11311  *   be used to print the target address if this is a relative jump or call
11312  * The function returns the length of this instruction in bytes.
11313  */
11314
11315 static char intel_syntax;
11316 static char intel_mnemonic = !SYSV386_COMPAT;
11317 static char open_char;
11318 static char close_char;
11319 static char separator_char;
11320 static char scale_char;
11321
11322 enum x86_64_isa
11323 {
11324   amd64 = 1,
11325   intel64
11326 };
11327
11328 static enum x86_64_isa isa64;
11329
11330 /* Here for backwards compatibility.  When gdb stops using
11331    print_insn_i386_att and print_insn_i386_intel these functions can
11332    disappear, and print_insn_i386 be merged into print_insn.  */
11333 int
11334 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
11335 {
11336   intel_syntax = 0;
11337
11338   return print_insn (pc, info);
11339 }
11340
11341 int
11342 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
11343 {
11344   intel_syntax = 1;
11345
11346   return print_insn (pc, info);
11347 }
11348
11349 int
11350 print_insn_i386 (bfd_vma pc, disassemble_info *info)
11351 {
11352   intel_syntax = -1;
11353
11354   return print_insn (pc, info);
11355 }
11356
11357 void
11358 print_i386_disassembler_options (FILE *stream)
11359 {
11360   fprintf (stream, _("\n\
11361 The following i386/x86-64 specific disassembler options are supported for use\n\
11362 with the -M switch (multiple options should be separated by commas):\n"));
11363
11364   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
11365   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
11366   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
11367   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
11368   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
11369   fprintf (stream, _("  att-mnemonic\n"
11370                      "              Display instruction in AT&T mnemonic\n"));
11371   fprintf (stream, _("  intel-mnemonic\n"
11372                      "              Display instruction in Intel mnemonic\n"));
11373   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
11374   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
11375   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
11376   fprintf (stream, _("  data32      Assume 32bit data size\n"));
11377   fprintf (stream, _("  data16      Assume 16bit data size\n"));
11378   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
11379   fprintf (stream, _("  amd64       Display instruction in AMD64 ISA\n"));
11380   fprintf (stream, _("  intel64     Display instruction in Intel64 ISA\n"));
11381 }
11382
11383 /* Bad opcode.  */
11384 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
11385
11386 /* Get a pointer to struct dis386 with a valid name.  */
11387
11388 static const struct dis386 *
11389 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
11390 {
11391   int vindex, vex_table_index;
11392
11393   if (dp->name != NULL)
11394     return dp;
11395
11396   switch (dp->op[0].bytemode)
11397     {
11398     case USE_REG_TABLE:
11399       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
11400       break;
11401
11402     case USE_MOD_TABLE:
11403       vindex = modrm.mod == 0x3 ? 1 : 0;
11404       dp = &mod_table[dp->op[1].bytemode][vindex];
11405       break;
11406
11407     case USE_RM_TABLE:
11408       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
11409       break;
11410
11411     case USE_PREFIX_TABLE:
11412       if (need_vex)
11413         {
11414           /* The prefix in VEX is implicit.  */
11415           switch (vex.prefix)
11416             {
11417             case 0:
11418               vindex = 0;
11419               break;
11420             case REPE_PREFIX_OPCODE:
11421               vindex = 1;
11422               break;
11423             case DATA_PREFIX_OPCODE:
11424               vindex = 2;
11425               break;
11426             case REPNE_PREFIX_OPCODE:
11427               vindex = 3;
11428               break;
11429             default:
11430               abort ();
11431               break;
11432             }
11433         }
11434       else
11435         {
11436           int last_prefix = -1;
11437           int prefix = 0;
11438           vindex = 0;
11439           /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
11440              When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
11441              last one wins.  */
11442           if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
11443             {
11444               if (last_repz_prefix > last_repnz_prefix)
11445                 {
11446                   vindex = 1;
11447                   prefix = PREFIX_REPZ;
11448                   last_prefix = last_repz_prefix;
11449                 }
11450               else
11451                 {
11452                   vindex = 3;
11453                   prefix = PREFIX_REPNZ;
11454                   last_prefix = last_repnz_prefix;
11455                 }
11456
11457               /* Check if prefix should be ignored.  */
11458               if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
11459                      & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
11460                    & prefix) != 0)
11461                 vindex = 0;
11462             }
11463
11464           if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
11465             {
11466               vindex = 2;
11467               prefix = PREFIX_DATA;
11468               last_prefix = last_data_prefix;
11469             }
11470
11471           if (vindex != 0)
11472             {
11473               used_prefixes |= prefix;
11474               all_prefixes[last_prefix] = 0;
11475             }
11476         }
11477       dp = &prefix_table[dp->op[1].bytemode][vindex];
11478       break;
11479
11480     case USE_X86_64_TABLE:
11481       vindex = address_mode == mode_64bit ? 1 : 0;
11482       dp = &x86_64_table[dp->op[1].bytemode][vindex];
11483       break;
11484
11485     case USE_3BYTE_TABLE:
11486       FETCH_DATA (info, codep + 2);
11487       vindex = *codep++;
11488       dp = &three_byte_table[dp->op[1].bytemode][vindex];
11489       end_codep = codep;
11490       modrm.mod = (*codep >> 6) & 3;
11491       modrm.reg = (*codep >> 3) & 7;
11492       modrm.rm = *codep & 7;
11493       break;
11494
11495     case USE_VEX_LEN_TABLE:
11496       if (!need_vex)
11497         abort ();
11498
11499       switch (vex.length)
11500         {
11501         case 128:
11502           vindex = 0;
11503           break;
11504         case 256:
11505           vindex = 1;
11506           break;
11507         default:
11508           abort ();
11509           break;
11510         }
11511
11512       dp = &vex_len_table[dp->op[1].bytemode][vindex];
11513       break;
11514
11515     case USE_EVEX_LEN_TABLE:
11516       if (!vex.evex)
11517         abort ();
11518
11519       switch (vex.length)
11520         {
11521         case 128:
11522           vindex = 0;
11523           break;
11524         case 256:
11525           vindex = 1;
11526           break;
11527         case 512:
11528           vindex = 2;
11529           break;
11530         default:
11531           abort ();
11532           break;
11533         }
11534
11535       dp = &evex_len_table[dp->op[1].bytemode][vindex];
11536       break;
11537
11538     case USE_XOP_8F_TABLE:
11539       FETCH_DATA (info, codep + 3);
11540       /* All bits in the REX prefix are ignored.  */
11541       rex_ignored = rex;
11542       rex = ~(*codep >> 5) & 0x7;
11543
11544       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
11545       switch ((*codep & 0x1f))
11546         {
11547         default:
11548           dp = &bad_opcode;
11549           return dp;
11550         case 0x8:
11551           vex_table_index = XOP_08;
11552           break;
11553         case 0x9:
11554           vex_table_index = XOP_09;
11555           break;
11556         case 0xa:
11557           vex_table_index = XOP_0A;
11558           break;
11559         }
11560       codep++;
11561       vex.w = *codep & 0x80;
11562       if (vex.w && address_mode == mode_64bit)
11563         rex |= REX_W;
11564
11565       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11566       if (address_mode != mode_64bit)
11567         {
11568           /* In 16/32-bit mode REX_B is silently ignored.  */
11569           rex &= ~REX_B;
11570         }
11571
11572       vex.length = (*codep & 0x4) ? 256 : 128;
11573       switch ((*codep & 0x3))
11574         {
11575         case 0:
11576           break;
11577         case 1:
11578           vex.prefix = DATA_PREFIX_OPCODE;
11579           break;
11580         case 2:
11581           vex.prefix = REPE_PREFIX_OPCODE;
11582           break;
11583         case 3:
11584           vex.prefix = REPNE_PREFIX_OPCODE;
11585           break;
11586         }
11587       need_vex = 1;
11588       need_vex_reg = 1;
11589       codep++;
11590       vindex = *codep++;
11591       dp = &xop_table[vex_table_index][vindex];
11592
11593       end_codep = codep;
11594       FETCH_DATA (info, codep + 1);
11595       modrm.mod = (*codep >> 6) & 3;
11596       modrm.reg = (*codep >> 3) & 7;
11597       modrm.rm = *codep & 7;
11598       break;
11599
11600     case USE_VEX_C4_TABLE:
11601       /* VEX prefix.  */
11602       FETCH_DATA (info, codep + 3);
11603       /* All bits in the REX prefix are ignored.  */
11604       rex_ignored = rex;
11605       rex = ~(*codep >> 5) & 0x7;
11606       switch ((*codep & 0x1f))
11607         {
11608         default:
11609           dp = &bad_opcode;
11610           return dp;
11611         case 0x1:
11612           vex_table_index = VEX_0F;
11613           break;
11614         case 0x2:
11615           vex_table_index = VEX_0F38;
11616           break;
11617         case 0x3:
11618           vex_table_index = VEX_0F3A;
11619           break;
11620         }
11621       codep++;
11622       vex.w = *codep & 0x80;
11623       if (address_mode == mode_64bit)
11624         {
11625           if (vex.w)
11626             rex |= REX_W;
11627         }
11628       else
11629         {
11630           /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
11631              is ignored, other REX bits are 0 and the highest bit in
11632              VEX.vvvv is also ignored (but we mustn't clear it here).  */
11633           rex = 0;
11634         }
11635       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11636       vex.length = (*codep & 0x4) ? 256 : 128;
11637       switch ((*codep & 0x3))
11638         {
11639         case 0:
11640           break;
11641         case 1:
11642           vex.prefix = DATA_PREFIX_OPCODE;
11643           break;
11644         case 2:
11645           vex.prefix = REPE_PREFIX_OPCODE;
11646           break;
11647         case 3:
11648           vex.prefix = REPNE_PREFIX_OPCODE;
11649           break;
11650         }
11651       need_vex = 1;
11652       need_vex_reg = 1;
11653       codep++;
11654       vindex = *codep++;
11655       dp = &vex_table[vex_table_index][vindex];
11656       end_codep = codep;
11657       /* There is no MODRM byte for VEX0F 77.  */
11658       if (vex_table_index != VEX_0F || vindex != 0x77)
11659         {
11660           FETCH_DATA (info, codep + 1);
11661           modrm.mod = (*codep >> 6) & 3;
11662           modrm.reg = (*codep >> 3) & 7;
11663           modrm.rm = *codep & 7;
11664         }
11665       break;
11666
11667     case USE_VEX_C5_TABLE:
11668       /* VEX prefix.  */
11669       FETCH_DATA (info, codep + 2);
11670       /* All bits in the REX prefix are ignored.  */
11671       rex_ignored = rex;
11672       rex = (*codep & 0x80) ? 0 : REX_R;
11673
11674       /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
11675          VEX.vvvv is 1.  */
11676       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11677       vex.length = (*codep & 0x4) ? 256 : 128;
11678       switch ((*codep & 0x3))
11679         {
11680         case 0:
11681           break;
11682         case 1:
11683           vex.prefix = DATA_PREFIX_OPCODE;
11684           break;
11685         case 2:
11686           vex.prefix = REPE_PREFIX_OPCODE;
11687           break;
11688         case 3:
11689           vex.prefix = REPNE_PREFIX_OPCODE;
11690           break;
11691         }
11692       need_vex = 1;
11693       need_vex_reg = 1;
11694       codep++;
11695       vindex = *codep++;
11696       dp = &vex_table[dp->op[1].bytemode][vindex];
11697       end_codep = codep;
11698       /* There is no MODRM byte for VEX 77.  */
11699       if (vindex != 0x77)
11700         {
11701           FETCH_DATA (info, codep + 1);
11702           modrm.mod = (*codep >> 6) & 3;
11703           modrm.reg = (*codep >> 3) & 7;
11704           modrm.rm = *codep & 7;
11705         }
11706       break;
11707
11708     case USE_VEX_W_TABLE:
11709       if (!need_vex)
11710         abort ();
11711
11712       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
11713       break;
11714
11715     case USE_EVEX_TABLE:
11716       two_source_ops = 0;
11717       /* EVEX prefix.  */
11718       vex.evex = 1;
11719       FETCH_DATA (info, codep + 4);
11720       /* All bits in the REX prefix are ignored.  */
11721       rex_ignored = rex;
11722       /* The first byte after 0x62.  */
11723       rex = ~(*codep >> 5) & 0x7;
11724       vex.r = *codep & 0x10;
11725       switch ((*codep & 0xf))
11726         {
11727         default:
11728           return &bad_opcode;
11729         case 0x1:
11730           vex_table_index = EVEX_0F;
11731           break;
11732         case 0x2:
11733           vex_table_index = EVEX_0F38;
11734           break;
11735         case 0x3:
11736           vex_table_index = EVEX_0F3A;
11737           break;
11738         }
11739
11740       /* The second byte after 0x62.  */
11741       codep++;
11742       vex.w = *codep & 0x80;
11743       if (vex.w && address_mode == mode_64bit)
11744         rex |= REX_W;
11745
11746       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11747
11748       /* The U bit.  */
11749       if (!(*codep & 0x4))
11750         return &bad_opcode;
11751
11752       switch ((*codep & 0x3))
11753         {
11754         case 0:
11755           break;
11756         case 1:
11757           vex.prefix = DATA_PREFIX_OPCODE;
11758           break;
11759         case 2:
11760           vex.prefix = REPE_PREFIX_OPCODE;
11761           break;
11762         case 3:
11763           vex.prefix = REPNE_PREFIX_OPCODE;
11764           break;
11765         }
11766
11767       /* The third byte after 0x62.  */
11768       codep++;
11769
11770       /* Remember the static rounding bits.  */
11771       vex.ll = (*codep >> 5) & 3;
11772       vex.b = (*codep & 0x10) != 0;
11773
11774       vex.v = *codep & 0x8;
11775       vex.mask_register_specifier = *codep & 0x7;
11776       vex.zeroing = *codep & 0x80;
11777
11778       if (address_mode != mode_64bit)
11779         {
11780           /* In 16/32-bit mode silently ignore following bits.  */
11781           rex &= ~REX_B;
11782           vex.r = 1;
11783           vex.v = 1;
11784         }
11785
11786       need_vex = 1;
11787       need_vex_reg = 1;
11788       codep++;
11789       vindex = *codep++;
11790       dp = &evex_table[vex_table_index][vindex];
11791       end_codep = codep;
11792       FETCH_DATA (info, codep + 1);
11793       modrm.mod = (*codep >> 6) & 3;
11794       modrm.reg = (*codep >> 3) & 7;
11795       modrm.rm = *codep & 7;
11796
11797       /* Set vector length.  */
11798       if (modrm.mod == 3 && vex.b)
11799         vex.length = 512;
11800       else
11801         {
11802           switch (vex.ll)
11803             {
11804             case 0x0:
11805               vex.length = 128;
11806               break;
11807             case 0x1:
11808               vex.length = 256;
11809               break;
11810             case 0x2:
11811               vex.length = 512;
11812               break;
11813             default:
11814               return &bad_opcode;
11815             }
11816         }
11817       break;
11818
11819     case 0:
11820       dp = &bad_opcode;
11821       break;
11822
11823     default:
11824       abort ();
11825     }
11826
11827   if (dp->name != NULL)
11828     return dp;
11829   else
11830     return get_valid_dis386 (dp, info);
11831 }
11832
11833 static void
11834 get_sib (disassemble_info *info, int sizeflag)
11835 {
11836   /* If modrm.mod == 3, operand must be register.  */
11837   if (need_modrm
11838       && ((sizeflag & AFLAG) || address_mode == mode_64bit)
11839       && modrm.mod != 3
11840       && modrm.rm == 4)
11841     {
11842       FETCH_DATA (info, codep + 2);
11843       sib.index = (codep [1] >> 3) & 7;
11844       sib.scale = (codep [1] >> 6) & 3;
11845       sib.base = codep [1] & 7;
11846     }
11847 }
11848
11849 static int
11850 print_insn (bfd_vma pc, disassemble_info *info)
11851 {
11852   const struct dis386 *dp;
11853   int i;
11854   char *op_txt[MAX_OPERANDS];
11855   int needcomma;
11856   int sizeflag, orig_sizeflag;
11857   const char *p;
11858   struct dis_private priv;
11859   int prefix_length;
11860
11861   priv.orig_sizeflag = AFLAG | DFLAG;
11862   if ((info->mach & bfd_mach_i386_i386) != 0)
11863     address_mode = mode_32bit;
11864   else if (info->mach == bfd_mach_i386_i8086)
11865     {
11866       address_mode = mode_16bit;
11867       priv.orig_sizeflag = 0;
11868     }
11869   else
11870     address_mode = mode_64bit;
11871
11872   if (intel_syntax == (char) -1)
11873     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
11874
11875   for (p = info->disassembler_options; p != NULL; )
11876     {
11877       if (CONST_STRNEQ (p, "amd64"))
11878         isa64 = amd64;
11879       else if (CONST_STRNEQ (p, "intel64"))
11880         isa64 = intel64;
11881       else if (CONST_STRNEQ (p, "x86-64"))
11882         {
11883           address_mode = mode_64bit;
11884           priv.orig_sizeflag = AFLAG | DFLAG;
11885         }
11886       else if (CONST_STRNEQ (p, "i386"))
11887         {
11888           address_mode = mode_32bit;
11889           priv.orig_sizeflag = AFLAG | DFLAG;
11890         }
11891       else if (CONST_STRNEQ (p, "i8086"))
11892         {
11893           address_mode = mode_16bit;
11894           priv.orig_sizeflag = 0;
11895         }
11896       else if (CONST_STRNEQ (p, "intel"))
11897         {
11898           intel_syntax = 1;
11899           if (CONST_STRNEQ (p + 5, "-mnemonic"))
11900             intel_mnemonic = 1;
11901         }
11902       else if (CONST_STRNEQ (p, "att"))
11903         {
11904           intel_syntax = 0;
11905           if (CONST_STRNEQ (p + 3, "-mnemonic"))
11906             intel_mnemonic = 0;
11907         }
11908       else if (CONST_STRNEQ (p, "addr"))
11909         {
11910           if (address_mode == mode_64bit)
11911             {
11912               if (p[4] == '3' && p[5] == '2')
11913                 priv.orig_sizeflag &= ~AFLAG;
11914               else if (p[4] == '6' && p[5] == '4')
11915                 priv.orig_sizeflag |= AFLAG;
11916             }
11917           else
11918             {
11919               if (p[4] == '1' && p[5] == '6')
11920                 priv.orig_sizeflag &= ~AFLAG;
11921               else if (p[4] == '3' && p[5] == '2')
11922                 priv.orig_sizeflag |= AFLAG;
11923             }
11924         }
11925       else if (CONST_STRNEQ (p, "data"))
11926         {
11927           if (p[4] == '1' && p[5] == '6')
11928             priv.orig_sizeflag &= ~DFLAG;
11929           else if (p[4] == '3' && p[5] == '2')
11930             priv.orig_sizeflag |= DFLAG;
11931         }
11932       else if (CONST_STRNEQ (p, "suffix"))
11933         priv.orig_sizeflag |= SUFFIX_ALWAYS;
11934
11935       p = strchr (p, ',');
11936       if (p != NULL)
11937         p++;
11938     }
11939
11940   if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
11941     {
11942       (*info->fprintf_func) (info->stream,
11943                              _("64-bit address is disabled"));
11944       return -1;
11945     }
11946
11947   if (intel_syntax)
11948     {
11949       names64 = intel_names64;
11950       names32 = intel_names32;
11951       names16 = intel_names16;
11952       names8 = intel_names8;
11953       names8rex = intel_names8rex;
11954       names_seg = intel_names_seg;
11955       names_mm = intel_names_mm;
11956       names_bnd = intel_names_bnd;
11957       names_xmm = intel_names_xmm;
11958       names_ymm = intel_names_ymm;
11959       names_zmm = intel_names_zmm;
11960       index64 = intel_index64;
11961       index32 = intel_index32;
11962       names_mask = intel_names_mask;
11963       index16 = intel_index16;
11964       open_char = '[';
11965       close_char = ']';
11966       separator_char = '+';
11967       scale_char = '*';
11968     }
11969   else
11970     {
11971       names64 = att_names64;
11972       names32 = att_names32;
11973       names16 = att_names16;
11974       names8 = att_names8;
11975       names8rex = att_names8rex;
11976       names_seg = att_names_seg;
11977       names_mm = att_names_mm;
11978       names_bnd = att_names_bnd;
11979       names_xmm = att_names_xmm;
11980       names_ymm = att_names_ymm;
11981       names_zmm = att_names_zmm;
11982       index64 = att_index64;
11983       index32 = att_index32;
11984       names_mask = att_names_mask;
11985       index16 = att_index16;
11986       open_char = '(';
11987       close_char =  ')';
11988       separator_char = ',';
11989       scale_char = ',';
11990     }
11991
11992   /* The output looks better if we put 7 bytes on a line, since that
11993      puts most long word instructions on a single line.  Use 8 bytes
11994      for Intel L1OM.  */
11995   if ((info->mach & bfd_mach_l1om) != 0)
11996     info->bytes_per_line = 8;
11997   else
11998     info->bytes_per_line = 7;
11999
12000   info->private_data = &priv;
12001   priv.max_fetched = priv.the_buffer;
12002   priv.insn_start = pc;
12003
12004   obuf[0] = 0;
12005   for (i = 0; i < MAX_OPERANDS; ++i)
12006     {
12007       op_out[i][0] = 0;
12008       op_index[i] = -1;
12009     }
12010
12011   the_info = info;
12012   start_pc = pc;
12013   start_codep = priv.the_buffer;
12014   codep = priv.the_buffer;
12015
12016   if (OPCODES_SIGSETJMP (priv.bailout) != 0)
12017     {
12018       const char *name;
12019
12020       /* Getting here means we tried for data but didn't get it.  That
12021          means we have an incomplete instruction of some sort.  Just
12022          print the first byte as a prefix or a .byte pseudo-op.  */
12023       if (codep > priv.the_buffer)
12024         {
12025           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
12026           if (name != NULL)
12027             (*info->fprintf_func) (info->stream, "%s", name);
12028           else
12029             {
12030               /* Just print the first byte as a .byte instruction.  */
12031               (*info->fprintf_func) (info->stream, ".byte 0x%x",
12032                                      (unsigned int) priv.the_buffer[0]);
12033             }
12034
12035           return 1;
12036         }
12037
12038       return -1;
12039     }
12040
12041   obufp = obuf;
12042   sizeflag = priv.orig_sizeflag;
12043
12044   if (!ckprefix () || rex_used)
12045     {
12046       /* Too many prefixes or unused REX prefixes.  */
12047       for (i = 0;
12048            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
12049            i++)
12050         (*info->fprintf_func) (info->stream, "%s%s",
12051                                i == 0 ? "" : " ",
12052                                prefix_name (all_prefixes[i], sizeflag));
12053       return i;
12054     }
12055
12056   insn_codep = codep;
12057
12058   FETCH_DATA (info, codep + 1);
12059   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
12060
12061   if (((prefixes & PREFIX_FWAIT)
12062        && ((*codep < 0xd8) || (*codep > 0xdf))))
12063     {
12064       /* Handle prefixes before fwait.  */
12065       for (i = 0; i < fwait_prefix && all_prefixes[i];
12066            i++)
12067         (*info->fprintf_func) (info->stream, "%s ",
12068                                prefix_name (all_prefixes[i], sizeflag));
12069       (*info->fprintf_func) (info->stream, "fwait");
12070       return i + 1;
12071     }
12072
12073   if (*codep == 0x0f)
12074     {
12075       unsigned char threebyte;
12076
12077       codep++;
12078       FETCH_DATA (info, codep + 1);
12079       threebyte = *codep;
12080       dp = &dis386_twobyte[threebyte];
12081       need_modrm = twobyte_has_modrm[*codep];
12082       codep++;
12083     }
12084   else
12085     {
12086       dp = &dis386[*codep];
12087       need_modrm = onebyte_has_modrm[*codep];
12088       codep++;
12089     }
12090
12091   /* Save sizeflag for printing the extra prefixes later before updating
12092      it for mnemonic and operand processing.  The prefix names depend
12093      only on the address mode.  */
12094   orig_sizeflag = sizeflag;
12095   if (prefixes & PREFIX_ADDR)
12096     sizeflag ^= AFLAG;
12097   if ((prefixes & PREFIX_DATA))
12098     sizeflag ^= DFLAG;
12099
12100   end_codep = codep;
12101   if (need_modrm)
12102     {
12103       FETCH_DATA (info, codep + 1);
12104       modrm.mod = (*codep >> 6) & 3;
12105       modrm.reg = (*codep >> 3) & 7;
12106       modrm.rm = *codep & 7;
12107     }
12108
12109   need_vex = 0;
12110   need_vex_reg = 0;
12111   vex_w_done = 0;
12112   memset (&vex, 0, sizeof (vex));
12113
12114   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
12115     {
12116       get_sib (info, sizeflag);
12117       dofloat (sizeflag);
12118     }
12119   else
12120     {
12121       dp = get_valid_dis386 (dp, info);
12122       if (dp != NULL && putop (dp->name, sizeflag) == 0)
12123         {
12124           get_sib (info, sizeflag);
12125           for (i = 0; i < MAX_OPERANDS; ++i)
12126             {
12127               obufp = op_out[i];
12128               op_ad = MAX_OPERANDS - 1 - i;
12129               if (dp->op[i].rtn)
12130                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
12131               /* For EVEX instruction after the last operand masking
12132                  should be printed.  */
12133               if (i == 0 && vex.evex)
12134                 {
12135                   /* Don't print {%k0}.  */
12136                   if (vex.mask_register_specifier)
12137                     {
12138                       oappend ("{");
12139                       oappend (names_mask[vex.mask_register_specifier]);
12140                       oappend ("}");
12141                     }
12142                   if (vex.zeroing)
12143                     oappend ("{z}");
12144                 }
12145             }
12146         }
12147     }
12148
12149   /* Clear instruction information.  */
12150   if (the_info)
12151     {
12152       the_info->insn_info_valid = 0;
12153       the_info->branch_delay_insns = 0;
12154       the_info->data_size = 0;
12155       the_info->insn_type = dis_noninsn;
12156       the_info->target = 0;
12157       the_info->target2 = 0;
12158     }
12159
12160   /* Reset jump operation indicator.  */
12161   op_is_jump = FALSE;
12162
12163   {
12164     int jump_detection = 0;
12165
12166     /* Extract flags.  */
12167     for (i = 0; i < MAX_OPERANDS; ++i)
12168       {
12169         if ((dp->op[i].rtn == OP_J)
12170             || (dp->op[i].rtn == OP_indirE))
12171           jump_detection |= 1;
12172         else if ((dp->op[i].rtn == BND_Fixup)
12173                  || (!dp->op[i].rtn && !dp->op[i].bytemode))
12174           jump_detection |= 2;
12175         else if ((dp->op[i].bytemode == cond_jump_mode)
12176                  || (dp->op[i].bytemode == loop_jcxz_mode))
12177           jump_detection |= 4;
12178       }
12179
12180     /* Determine if this is a jump or branch.  */
12181     if ((jump_detection & 0x3) == 0x3)
12182       {
12183         op_is_jump = TRUE;
12184         if (jump_detection & 0x4)
12185           the_info->insn_type = dis_condbranch;
12186         else
12187           the_info->insn_type =
12188             (dp->name && !strncmp(dp->name, "call", 4))
12189             ? dis_jsr : dis_branch;
12190       }
12191   }
12192
12193   /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
12194      are all 0s in inverted form.  */
12195   if (need_vex && vex.register_specifier != 0)
12196     {
12197       (*info->fprintf_func) (info->stream, "(bad)");
12198       return end_codep - priv.the_buffer;
12199     }
12200
12201   /* Check if the REX prefix is used.  */
12202   if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)
12203     all_prefixes[last_rex_prefix] = 0;
12204
12205   /* Check if the SEG prefix is used.  */
12206   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
12207                    | PREFIX_FS | PREFIX_GS)) != 0
12208       && (used_prefixes & active_seg_prefix) != 0)
12209     all_prefixes[last_seg_prefix] = 0;
12210
12211   /* Check if the ADDR prefix is used.  */
12212   if ((prefixes & PREFIX_ADDR) != 0
12213       && (used_prefixes & PREFIX_ADDR) != 0)
12214     all_prefixes[last_addr_prefix] = 0;
12215
12216   /* Check if the DATA prefix is used.  */
12217   if ((prefixes & PREFIX_DATA) != 0
12218       && (used_prefixes & PREFIX_DATA) != 0)
12219     all_prefixes[last_data_prefix] = 0;
12220
12221   /* Print the extra prefixes.  */
12222   prefix_length = 0;
12223   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12224     if (all_prefixes[i])
12225       {
12226         const char *name;
12227         name = prefix_name (all_prefixes[i], orig_sizeflag);
12228         if (name == NULL)
12229           abort ();
12230         prefix_length += strlen (name) + 1;
12231         (*info->fprintf_func) (info->stream, "%s ", name);
12232       }
12233
12234   /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
12235      unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
12236      used by putop and MMX/SSE operand and may be overriden by the
12237      PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
12238      separately.  */
12239   if (dp->prefix_requirement == PREFIX_OPCODE
12240       && dp != &bad_opcode
12241       && (((prefixes
12242             & (PREFIX_REPZ | PREFIX_REPNZ)) != 0
12243            && (used_prefixes
12244                & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
12245           || ((((prefixes
12246                  & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
12247                 == PREFIX_DATA)
12248                && (used_prefixes & PREFIX_DATA) == 0))))
12249     {
12250       (*info->fprintf_func) (info->stream, "(bad)");
12251       return end_codep - priv.the_buffer;
12252     }
12253
12254   /* Check maximum code length.  */
12255   if ((codep - start_codep) > MAX_CODE_LENGTH)
12256     {
12257       (*info->fprintf_func) (info->stream, "(bad)");
12258       return MAX_CODE_LENGTH;
12259     }
12260
12261   obufp = mnemonicendp;
12262   for (i = strlen (obuf) + prefix_length; i < 6; i++)
12263     oappend (" ");
12264   oappend (" ");
12265   (*info->fprintf_func) (info->stream, "%s", obuf);
12266
12267   /* The enter and bound instructions are printed with operands in the same
12268      order as the intel book; everything else is printed in reverse order.  */
12269   if (intel_syntax || two_source_ops)
12270     {
12271       bfd_vma riprel;
12272
12273       for (i = 0; i < MAX_OPERANDS; ++i)
12274         op_txt[i] = op_out[i];
12275
12276       if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
12277           && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
12278         {
12279           op_txt[2] = op_out[3];
12280           op_txt[3] = op_out[2];
12281         }
12282
12283       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
12284         {
12285           op_ad = op_index[i];
12286           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
12287           op_index[MAX_OPERANDS - 1 - i] = op_ad;
12288           riprel = op_riprel[i];
12289           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
12290           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
12291         }
12292     }
12293   else
12294     {
12295       for (i = 0; i < MAX_OPERANDS; ++i)
12296         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
12297     }
12298
12299   needcomma = 0;
12300   for (i = 0; i < MAX_OPERANDS; ++i)
12301     if (*op_txt[i])
12302       {
12303         if (needcomma)
12304           (*info->fprintf_func) (info->stream, ",");
12305         if (op_index[i] != -1 && !op_riprel[i])
12306           {
12307             bfd_vma target = (bfd_vma) op_address[op_index[i]];
12308
12309             if (the_info && op_is_jump)
12310               {
12311                 the_info->insn_info_valid = 1;
12312                 the_info->branch_delay_insns = 0;
12313                 the_info->data_size = 0;
12314                 the_info->target = target;
12315                 the_info->target2 = 0;
12316               }
12317             (*info->print_address_func) (target, info);
12318           }
12319         else
12320           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
12321         needcomma = 1;
12322       }
12323
12324   for (i = 0; i < MAX_OPERANDS; i++)
12325     if (op_index[i] != -1 && op_riprel[i])
12326       {
12327         (*info->fprintf_func) (info->stream, "        # ");
12328         (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
12329                                                 + op_address[op_index[i]]), info);
12330         break;
12331       }
12332   return codep - priv.the_buffer;
12333 }
12334
12335 static const char *float_mem[] = {
12336   /* d8 */
12337   "fadd{s|}",
12338   "fmul{s|}",
12339   "fcom{s|}",
12340   "fcomp{s|}",
12341   "fsub{s|}",
12342   "fsubr{s|}",
12343   "fdiv{s|}",
12344   "fdivr{s|}",
12345   /* d9 */
12346   "fld{s|}",
12347   "(bad)",
12348   "fst{s|}",
12349   "fstp{s|}",
12350   "fldenvIC",
12351   "fldcw",
12352   "fNstenvIC",
12353   "fNstcw",
12354   /* da */
12355   "fiadd{l|}",
12356   "fimul{l|}",
12357   "ficom{l|}",
12358   "ficomp{l|}",
12359   "fisub{l|}",
12360   "fisubr{l|}",
12361   "fidiv{l|}",
12362   "fidivr{l|}",
12363   /* db */
12364   "fild{l|}",
12365   "fisttp{l|}",
12366   "fist{l|}",
12367   "fistp{l|}",
12368   "(bad)",
12369   "fld{t||t|}",
12370   "(bad)",
12371   "fstp{t||t|}",
12372   /* dc */
12373   "fadd{l|}",
12374   "fmul{l|}",
12375   "fcom{l|}",
12376   "fcomp{l|}",
12377   "fsub{l|}",
12378   "fsubr{l|}",
12379   "fdiv{l|}",
12380   "fdivr{l|}",
12381   /* dd */
12382   "fld{l|}",
12383   "fisttp{ll|}",
12384   "fst{l||}",
12385   "fstp{l|}",
12386   "frstorIC",
12387   "(bad)",
12388   "fNsaveIC",
12389   "fNstsw",
12390   /* de */
12391   "fiadd{s|}",
12392   "fimul{s|}",
12393   "ficom{s|}",
12394   "ficomp{s|}",
12395   "fisub{s|}",
12396   "fisubr{s|}",
12397   "fidiv{s|}",
12398   "fidivr{s|}",
12399   /* df */
12400   "fild{s|}",
12401   "fisttp{s|}",
12402   "fist{s|}",
12403   "fistp{s|}",
12404   "fbld",
12405   "fild{ll|}",
12406   "fbstp",
12407   "fistp{ll|}",
12408 };
12409
12410 static const unsigned char float_mem_mode[] = {
12411   /* d8 */
12412   d_mode,
12413   d_mode,
12414   d_mode,
12415   d_mode,
12416   d_mode,
12417   d_mode,
12418   d_mode,
12419   d_mode,
12420   /* d9 */
12421   d_mode,
12422   0,
12423   d_mode,
12424   d_mode,
12425   0,
12426   w_mode,
12427   0,
12428   w_mode,
12429   /* da */
12430   d_mode,
12431   d_mode,
12432   d_mode,
12433   d_mode,
12434   d_mode,
12435   d_mode,
12436   d_mode,
12437   d_mode,
12438   /* db */
12439   d_mode,
12440   d_mode,
12441   d_mode,
12442   d_mode,
12443   0,
12444   t_mode,
12445   0,
12446   t_mode,
12447   /* dc */
12448   q_mode,
12449   q_mode,
12450   q_mode,
12451   q_mode,
12452   q_mode,
12453   q_mode,
12454   q_mode,
12455   q_mode,
12456   /* dd */
12457   q_mode,
12458   q_mode,
12459   q_mode,
12460   q_mode,
12461   0,
12462   0,
12463   0,
12464   w_mode,
12465   /* de */
12466   w_mode,
12467   w_mode,
12468   w_mode,
12469   w_mode,
12470   w_mode,
12471   w_mode,
12472   w_mode,
12473   w_mode,
12474   /* df */
12475   w_mode,
12476   w_mode,
12477   w_mode,
12478   w_mode,
12479   t_mode,
12480   q_mode,
12481   t_mode,
12482   q_mode
12483 };
12484
12485 #define ST { OP_ST, 0 }
12486 #define STi { OP_STi, 0 }
12487
12488 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
12489 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
12490 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
12491 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
12492 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
12493 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
12494 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
12495 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
12496 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
12497
12498 static const struct dis386 float_reg[][8] = {
12499   /* d8 */
12500   {
12501     { "fadd",   { ST, STi }, 0 },
12502     { "fmul",   { ST, STi }, 0 },
12503     { "fcom",   { STi }, 0 },
12504     { "fcomp",  { STi }, 0 },
12505     { "fsub",   { ST, STi }, 0 },
12506     { "fsubr",  { ST, STi }, 0 },
12507     { "fdiv",   { ST, STi }, 0 },
12508     { "fdivr",  { ST, STi }, 0 },
12509   },
12510   /* d9 */
12511   {
12512     { "fld",    { STi }, 0 },
12513     { "fxch",   { STi }, 0 },
12514     { FGRPd9_2 },
12515     { Bad_Opcode },
12516     { FGRPd9_4 },
12517     { FGRPd9_5 },
12518     { FGRPd9_6 },
12519     { FGRPd9_7 },
12520   },
12521   /* da */
12522   {
12523     { "fcmovb", { ST, STi }, 0 },
12524     { "fcmove", { ST, STi }, 0 },
12525     { "fcmovbe",{ ST, STi }, 0 },
12526     { "fcmovu", { ST, STi }, 0 },
12527     { Bad_Opcode },
12528     { FGRPda_5 },
12529     { Bad_Opcode },
12530     { Bad_Opcode },
12531   },
12532   /* db */
12533   {
12534     { "fcmovnb",{ ST, STi }, 0 },
12535     { "fcmovne",{ ST, STi }, 0 },
12536     { "fcmovnbe",{ ST, STi }, 0 },
12537     { "fcmovnu",{ ST, STi }, 0 },
12538     { FGRPdb_4 },
12539     { "fucomi", { ST, STi }, 0 },
12540     { "fcomi",  { ST, STi }, 0 },
12541     { Bad_Opcode },
12542   },
12543   /* dc */
12544   {
12545     { "fadd",   { STi, ST }, 0 },
12546     { "fmul",   { STi, ST }, 0 },
12547     { Bad_Opcode },
12548     { Bad_Opcode },
12549     { "fsub{!M|r}",     { STi, ST }, 0 },
12550     { "fsub{M|}",       { STi, ST }, 0 },
12551     { "fdiv{!M|r}",     { STi, ST }, 0 },
12552     { "fdiv{M|}",       { STi, ST }, 0 },
12553   },
12554   /* dd */
12555   {
12556     { "ffree",  { STi }, 0 },
12557     { Bad_Opcode },
12558     { "fst",    { STi }, 0 },
12559     { "fstp",   { STi }, 0 },
12560     { "fucom",  { STi }, 0 },
12561     { "fucomp", { STi }, 0 },
12562     { Bad_Opcode },
12563     { Bad_Opcode },
12564   },
12565   /* de */
12566   {
12567     { "faddp",  { STi, ST }, 0 },
12568     { "fmulp",  { STi, ST }, 0 },
12569     { Bad_Opcode },
12570     { FGRPde_3 },
12571     { "fsub{!M|r}p",    { STi, ST }, 0 },
12572     { "fsub{M|}p",      { STi, ST }, 0 },
12573     { "fdiv{!M|r}p",    { STi, ST }, 0 },
12574     { "fdiv{M|}p",      { STi, ST }, 0 },
12575   },
12576   /* df */
12577   {
12578     { "ffreep", { STi }, 0 },
12579     { Bad_Opcode },
12580     { Bad_Opcode },
12581     { Bad_Opcode },
12582     { FGRPdf_4 },
12583     { "fucomip", { ST, STi }, 0 },
12584     { "fcomip", { ST, STi }, 0 },
12585     { Bad_Opcode },
12586   },
12587 };
12588
12589 static char *fgrps[][8] = {
12590   /* Bad opcode 0 */
12591   {
12592     "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12593   },
12594
12595   /* d9_2  1 */
12596   {
12597     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12598   },
12599
12600   /* d9_4  2 */
12601   {
12602     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
12603   },
12604
12605   /* d9_5  3 */
12606   {
12607     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
12608   },
12609
12610   /* d9_6  4 */
12611   {
12612     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
12613   },
12614
12615   /* d9_7  5 */
12616   {
12617     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
12618   },
12619
12620   /* da_5  6 */
12621   {
12622     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12623   },
12624
12625   /* db_4  7 */
12626   {
12627     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
12628     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
12629   },
12630
12631   /* de_3  8 */
12632   {
12633     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12634   },
12635
12636   /* df_4  9 */
12637   {
12638     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12639   },
12640 };
12641
12642 static void
12643 swap_operand (void)
12644 {
12645   mnemonicendp[0] = '.';
12646   mnemonicendp[1] = 's';
12647   mnemonicendp += 2;
12648 }
12649
12650 static void
12651 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
12652                int sizeflag ATTRIBUTE_UNUSED)
12653 {
12654   /* Skip mod/rm byte.  */
12655   MODRM_CHECK;
12656   codep++;
12657 }
12658
12659 static void
12660 dofloat (int sizeflag)
12661 {
12662   const struct dis386 *dp;
12663   unsigned char floatop;
12664
12665   floatop = codep[-1];
12666
12667   if (modrm.mod != 3)
12668     {
12669       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
12670
12671       putop (float_mem[fp_indx], sizeflag);
12672       obufp = op_out[0];
12673       op_ad = 2;
12674       OP_E (float_mem_mode[fp_indx], sizeflag);
12675       return;
12676     }
12677   /* Skip mod/rm byte.  */
12678   MODRM_CHECK;
12679   codep++;
12680
12681   dp = &float_reg[floatop - 0xd8][modrm.reg];
12682   if (dp->name == NULL)
12683     {
12684       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
12685
12686       /* Instruction fnstsw is only one with strange arg.  */
12687       if (floatop == 0xdf && codep[-1] == 0xe0)
12688         strcpy (op_out[0], names16[0]);
12689     }
12690   else
12691     {
12692       putop (dp->name, sizeflag);
12693
12694       obufp = op_out[0];
12695       op_ad = 2;
12696       if (dp->op[0].rtn)
12697         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
12698
12699       obufp = op_out[1];
12700       op_ad = 1;
12701       if (dp->op[1].rtn)
12702         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
12703     }
12704 }
12705
12706 /* Like oappend (below), but S is a string starting with '%'.
12707    In Intel syntax, the '%' is elided.  */
12708 static void
12709 oappend_maybe_intel (const char *s)
12710 {
12711   oappend (s + intel_syntax);
12712 }
12713
12714 static void
12715 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12716 {
12717   oappend_maybe_intel ("%st");
12718 }
12719
12720 static void
12721 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12722 {
12723   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
12724   oappend_maybe_intel (scratchbuf);
12725 }
12726
12727 /* Capital letters in template are macros.  */
12728 static int
12729 putop (const char *in_template, int sizeflag)
12730 {
12731   const char *p;
12732   int alt = 0;
12733   int cond = 1;
12734   unsigned int l = 0, len = 1;
12735   char last[4];
12736
12737 #define SAVE_LAST(c)                    \
12738   if (l < len && l < sizeof (last))     \
12739     last[l++] = c;                      \
12740   else                                  \
12741     abort ();
12742
12743   for (p = in_template; *p; p++)
12744     {
12745       switch (*p)
12746         {
12747         default:
12748           *obufp++ = *p;
12749           break;
12750         case '%':
12751           len++;
12752           break;
12753         case '!':
12754           cond = 0;
12755           break;
12756         case '{':
12757           if (intel_syntax)
12758             {
12759               while (*++p != '|')
12760                 if (*p == '}' || *p == '\0')
12761                   abort ();
12762             }
12763           /* Fall through.  */
12764         case 'I':
12765           alt = 1;
12766           continue;
12767         case '|':
12768           while (*++p != '}')
12769             {
12770               if (*p == '\0')
12771                 abort ();
12772             }
12773           break;
12774         case '}':
12775           break;
12776         case 'A':
12777           if (intel_syntax)
12778             break;
12779           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12780             *obufp++ = 'b';
12781           break;
12782         case 'B':
12783           if (l == 0 && len == 1)
12784             {
12785 case_B:
12786               if (intel_syntax)
12787                 break;
12788               if (sizeflag & SUFFIX_ALWAYS)
12789                 *obufp++ = 'b';
12790             }
12791           else
12792             {
12793               if (l != 1
12794                   || len != 2
12795                   || last[0] != 'L')
12796                 {
12797                   SAVE_LAST (*p);
12798                   break;
12799                 }
12800
12801               if (address_mode == mode_64bit
12802                   && !(prefixes & PREFIX_ADDR))
12803                 {
12804                   *obufp++ = 'a';
12805                   *obufp++ = 'b';
12806                   *obufp++ = 's';
12807                 }
12808
12809               goto case_B;
12810             }
12811           break;
12812         case 'C':
12813           if (intel_syntax && !alt)
12814             break;
12815           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
12816             {
12817               if (sizeflag & DFLAG)
12818                 *obufp++ = intel_syntax ? 'd' : 'l';
12819               else
12820                 *obufp++ = intel_syntax ? 'w' : 's';
12821               used_prefixes |= (prefixes & PREFIX_DATA);
12822             }
12823           break;
12824         case 'D':
12825           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
12826             break;
12827           USED_REX (REX_W);
12828           if (modrm.mod == 3)
12829             {
12830               if (rex & REX_W)
12831                 *obufp++ = 'q';
12832               else
12833                 {
12834                   if (sizeflag & DFLAG)
12835                     *obufp++ = intel_syntax ? 'd' : 'l';
12836                   else
12837                     *obufp++ = 'w';
12838                   used_prefixes |= (prefixes & PREFIX_DATA);
12839                 }
12840             }
12841           else
12842             *obufp++ = 'w';
12843           break;
12844         case 'E':               /* For jcxz/jecxz */
12845           if (address_mode == mode_64bit)
12846             {
12847               if (sizeflag & AFLAG)
12848                 *obufp++ = 'r';
12849               else
12850                 *obufp++ = 'e';
12851             }
12852           else
12853             if (sizeflag & AFLAG)
12854               *obufp++ = 'e';
12855           used_prefixes |= (prefixes & PREFIX_ADDR);
12856           break;
12857         case 'F':
12858           if (intel_syntax)
12859             break;
12860           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
12861             {
12862               if (sizeflag & AFLAG)
12863                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
12864               else
12865                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
12866               used_prefixes |= (prefixes & PREFIX_ADDR);
12867             }
12868           break;
12869         case 'G':
12870           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
12871             break;
12872           if ((rex & REX_W) || (sizeflag & DFLAG))
12873             *obufp++ = 'l';
12874           else
12875             *obufp++ = 'w';
12876           if (!(rex & REX_W))
12877             used_prefixes |= (prefixes & PREFIX_DATA);
12878           break;
12879         case 'H':
12880           if (intel_syntax)
12881             break;
12882           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
12883               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
12884             {
12885               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
12886               *obufp++ = ',';
12887               *obufp++ = 'p';
12888               if (prefixes & PREFIX_DS)
12889                 *obufp++ = 't';
12890               else
12891                 *obufp++ = 'n';
12892             }
12893           break;
12894         case 'J':
12895           if (intel_syntax)
12896             break;
12897           *obufp++ = 'l';
12898           break;
12899         case 'K':
12900           USED_REX (REX_W);
12901           if (rex & REX_W)
12902             *obufp++ = 'q';
12903           else
12904             *obufp++ = 'd';
12905           break;
12906         case 'Z':
12907           if (l != 0 || len != 1)
12908             {
12909               if (l != 1 || len != 2 || last[0] != 'X')
12910                 {
12911                   SAVE_LAST (*p);
12912                   break;
12913                 }
12914               if (!need_vex || !vex.evex)
12915                 abort ();
12916               if (intel_syntax
12917                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
12918                 break;
12919               switch (vex.length)
12920                 {
12921                 case 128:
12922                   *obufp++ = 'x';
12923                   break;
12924                 case 256:
12925                   *obufp++ = 'y';
12926                   break;
12927                 case 512:
12928                   *obufp++ = 'z';
12929                   break;
12930                 default:
12931                   abort ();
12932                 }
12933               break;
12934             }
12935           if (intel_syntax)
12936             break;
12937           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
12938             {
12939               *obufp++ = 'q';
12940               break;
12941             }
12942           /* Fall through.  */
12943           goto case_L;
12944         case 'L':
12945           if (l != 0 || len != 1)
12946             {
12947               SAVE_LAST (*p);
12948               break;
12949             }
12950 case_L:
12951           if (intel_syntax)
12952             break;
12953           if (sizeflag & SUFFIX_ALWAYS)
12954             *obufp++ = 'l';
12955           break;
12956         case 'M':
12957           if (intel_mnemonic != cond)
12958             *obufp++ = 'r';
12959           break;
12960         case 'N':
12961           if ((prefixes & PREFIX_FWAIT) == 0)
12962             *obufp++ = 'n';
12963           else
12964             used_prefixes |= PREFIX_FWAIT;
12965           break;
12966         case 'O':
12967           USED_REX (REX_W);
12968           if (rex & REX_W)
12969             *obufp++ = 'o';
12970           else if (intel_syntax && (sizeflag & DFLAG))
12971             *obufp++ = 'q';
12972           else
12973             *obufp++ = 'd';
12974           if (!(rex & REX_W))
12975             used_prefixes |= (prefixes & PREFIX_DATA);
12976           break;
12977         case '&':
12978           if (!intel_syntax
12979               && address_mode == mode_64bit
12980               && isa64 == intel64)
12981             {
12982               *obufp++ = 'q';
12983               break;
12984             }
12985           /* Fall through.  */
12986         case 'T':
12987           if (!intel_syntax
12988               && address_mode == mode_64bit
12989               && ((sizeflag & DFLAG) || (rex & REX_W)))
12990             {
12991               *obufp++ = 'q';
12992               break;
12993             }
12994           /* Fall through.  */
12995           goto case_P;
12996         case 'P':
12997           if (l == 0 && len == 1)
12998             {
12999 case_P:
13000               if (intel_syntax)
13001                 {
13002                   if ((rex & REX_W) == 0
13003                       && (prefixes & PREFIX_DATA))
13004                     {
13005                       if ((sizeflag & DFLAG) == 0)
13006                         *obufp++ = 'w';
13007                       used_prefixes |= (prefixes & PREFIX_DATA);
13008                     }
13009                   break;
13010                 }
13011               if ((prefixes & PREFIX_DATA)
13012                   || (rex & REX_W)
13013                   || (sizeflag & SUFFIX_ALWAYS))
13014                 {
13015                   USED_REX (REX_W);
13016                   if (rex & REX_W)
13017                     *obufp++ = 'q';
13018                   else
13019                     {
13020                       if (sizeflag & DFLAG)
13021                         *obufp++ = 'l';
13022                       else
13023                         *obufp++ = 'w';
13024                       used_prefixes |= (prefixes & PREFIX_DATA);
13025                     }
13026                 }
13027             }
13028           else
13029             {
13030               if (l != 1 || len != 2 || last[0] != 'L')
13031                 {
13032                   SAVE_LAST (*p);
13033                   break;
13034                 }
13035
13036               if ((prefixes & PREFIX_DATA)
13037                   || (rex & REX_W)
13038                   || (sizeflag & SUFFIX_ALWAYS))
13039                 {
13040                   USED_REX (REX_W);
13041                   if (rex & REX_W)
13042                     *obufp++ = 'q';
13043                   else
13044                     {
13045                       if (sizeflag & DFLAG)
13046                         *obufp++ = intel_syntax ? 'd' : 'l';
13047                       else
13048                         *obufp++ = 'w';
13049                       used_prefixes |= (prefixes & PREFIX_DATA);
13050                     }
13051                 }
13052             }
13053           break;
13054         case 'U':
13055           if (intel_syntax)
13056             break;
13057           if (address_mode == mode_64bit
13058               && ((sizeflag & DFLAG) || (rex & REX_W)))
13059             {
13060               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13061                 *obufp++ = 'q';
13062               break;
13063             }
13064           /* Fall through.  */
13065           goto case_Q;
13066         case 'Q':
13067           if (l == 0 && len == 1)
13068             {
13069 case_Q:
13070               if (intel_syntax && !alt)
13071                 break;
13072               USED_REX (REX_W);
13073               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13074                 {
13075                   if (rex & REX_W)
13076                     *obufp++ = 'q';
13077                   else
13078                     {
13079                       if (sizeflag & DFLAG)
13080                         *obufp++ = intel_syntax ? 'd' : 'l';
13081                       else
13082                         *obufp++ = 'w';
13083                       used_prefixes |= (prefixes & PREFIX_DATA);
13084                     }
13085                 }
13086             }
13087           else
13088             {
13089               if (l != 1 || len != 2 || last[0] != 'L')
13090                 {
13091                   SAVE_LAST (*p);
13092                   break;
13093                 }
13094               if (intel_syntax
13095                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
13096                 break;
13097               if ((rex & REX_W))
13098                 {
13099                   USED_REX (REX_W);
13100                   *obufp++ = 'q';
13101                 }
13102               else
13103                 *obufp++ = 'l';
13104             }
13105           break;
13106         case 'R':
13107           USED_REX (REX_W);
13108           if (rex & REX_W)
13109             *obufp++ = 'q';
13110           else if (sizeflag & DFLAG)
13111             {
13112               if (intel_syntax)
13113                   *obufp++ = 'd';
13114               else
13115                   *obufp++ = 'l';
13116             }
13117           else
13118             *obufp++ = 'w';
13119           if (intel_syntax && !p[1]
13120               && ((rex & REX_W) || (sizeflag & DFLAG)))
13121             *obufp++ = 'e';
13122           if (!(rex & REX_W))
13123             used_prefixes |= (prefixes & PREFIX_DATA);
13124           break;
13125         case 'V':
13126           if (l == 0 && len == 1)
13127             {
13128               if (intel_syntax)
13129                 break;
13130               if (address_mode == mode_64bit
13131                   && ((sizeflag & DFLAG) || (rex & REX_W)))
13132                 {
13133                   if (sizeflag & SUFFIX_ALWAYS)
13134                     *obufp++ = 'q';
13135                   break;
13136                 }
13137             }
13138           else
13139             {
13140               if (l != 1
13141                   || len != 2
13142                   || last[0] != 'L')
13143                 {
13144                   SAVE_LAST (*p);
13145                   break;
13146                 }
13147
13148               if (rex & REX_W)
13149                 {
13150                   *obufp++ = 'a';
13151                   *obufp++ = 'b';
13152                   *obufp++ = 's';
13153                 }
13154             }
13155           /* Fall through.  */
13156           goto case_S;
13157         case 'S':
13158           if (l == 0 && len == 1)
13159             {
13160 case_S:
13161               if (intel_syntax)
13162                 break;
13163               if (sizeflag & SUFFIX_ALWAYS)
13164                 {
13165                   if (rex & REX_W)
13166                     *obufp++ = 'q';
13167                   else
13168                     {
13169                       if (sizeflag & DFLAG)
13170                         *obufp++ = 'l';
13171                       else
13172                         *obufp++ = 'w';
13173                       used_prefixes |= (prefixes & PREFIX_DATA);
13174                     }
13175                 }
13176             }
13177           else
13178             {
13179               if (l != 1
13180                   || len != 2
13181                   || last[0] != 'L')
13182                 {
13183                   SAVE_LAST (*p);
13184                   break;
13185                 }
13186
13187               if (address_mode == mode_64bit
13188                   && !(prefixes & PREFIX_ADDR))
13189                 {
13190                   *obufp++ = 'a';
13191                   *obufp++ = 'b';
13192                   *obufp++ = 's';
13193                 }
13194
13195               goto case_S;
13196             }
13197           break;
13198         case 'X':
13199           if (l != 0 || len != 1)
13200             {
13201               SAVE_LAST (*p);
13202               break;
13203             }
13204           if (need_vex && vex.prefix)
13205             {
13206               if (vex.prefix == DATA_PREFIX_OPCODE)
13207                 *obufp++ = 'd';
13208               else
13209                 *obufp++ = 's';
13210             }
13211           else
13212             {
13213               if (prefixes & PREFIX_DATA)
13214                 *obufp++ = 'd';
13215               else
13216                 *obufp++ = 's';
13217               used_prefixes |= (prefixes & PREFIX_DATA);
13218             }
13219           break;
13220         case 'Y':
13221           if (l == 0 && len == 1)
13222             abort ();
13223           else
13224             {
13225               if (l != 1 || len != 2 || last[0] != 'X')
13226                 {
13227                   SAVE_LAST (*p);
13228                   break;
13229                 }
13230               if (!need_vex)
13231                 abort ();
13232               if (intel_syntax
13233                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
13234                 break;
13235               switch (vex.length)
13236                 {
13237                 case 128:
13238                   *obufp++ = 'x';
13239                   break;
13240                 case 256:
13241                   *obufp++ = 'y';
13242                   break;
13243                 case 512:
13244                   if (!vex.evex)
13245                 default:
13246                     abort ();
13247                 }
13248             }
13249           break;
13250         case 'W':
13251           if (l == 0 && len == 1)
13252             {
13253               /* operand size flag for cwtl, cbtw */
13254               USED_REX (REX_W);
13255               if (rex & REX_W)
13256                 {
13257                   if (intel_syntax)
13258                     *obufp++ = 'd';
13259                   else
13260                     *obufp++ = 'l';
13261                 }
13262               else if (sizeflag & DFLAG)
13263                 *obufp++ = 'w';
13264               else
13265                 *obufp++ = 'b';
13266               if (!(rex & REX_W))
13267                 used_prefixes |= (prefixes & PREFIX_DATA);
13268             }
13269           else
13270             {
13271               if (l != 1
13272                   || len != 2
13273                   || (last[0] != 'X'
13274                       && last[0] != 'L'))
13275                 {
13276                   SAVE_LAST (*p);
13277                   break;
13278                 }
13279               if (!need_vex)
13280                 abort ();
13281               if (last[0] == 'X')
13282                 *obufp++ = vex.w ? 'd': 's';
13283               else
13284                 *obufp++ = vex.w ? 'q': 'd';
13285             }
13286           break;
13287         case '^':
13288           if (intel_syntax)
13289             break;
13290           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
13291             {
13292               if (sizeflag & DFLAG)
13293                 *obufp++ = 'l';
13294               else
13295                 *obufp++ = 'w';
13296               used_prefixes |= (prefixes & PREFIX_DATA);
13297             }
13298           break;
13299         case '@':
13300           if (intel_syntax)
13301             break;
13302           if (address_mode == mode_64bit
13303               && (isa64 == intel64
13304                   || ((sizeflag & DFLAG) || (rex & REX_W))))
13305               *obufp++ = 'q';
13306           else if ((prefixes & PREFIX_DATA))
13307             {
13308               if (!(sizeflag & DFLAG))
13309                 *obufp++ = 'w';
13310               used_prefixes |= (prefixes & PREFIX_DATA);
13311             }
13312           break;
13313         }
13314       alt = 0;
13315     }
13316   *obufp = 0;
13317   mnemonicendp = obufp;
13318   return 0;
13319 }
13320
13321 static void
13322 oappend (const char *s)
13323 {
13324   obufp = stpcpy (obufp, s);
13325 }
13326
13327 static void
13328 append_seg (void)
13329 {
13330   /* Only print the active segment register.  */
13331   if (!active_seg_prefix)
13332     return;
13333
13334   used_prefixes |= active_seg_prefix;
13335   switch (active_seg_prefix)
13336     {
13337     case PREFIX_CS:
13338       oappend_maybe_intel ("%cs:");
13339       break;
13340     case PREFIX_DS:
13341       oappend_maybe_intel ("%ds:");
13342       break;
13343     case PREFIX_SS:
13344       oappend_maybe_intel ("%ss:");
13345       break;
13346     case PREFIX_ES:
13347       oappend_maybe_intel ("%es:");
13348       break;
13349     case PREFIX_FS:
13350       oappend_maybe_intel ("%fs:");
13351       break;
13352     case PREFIX_GS:
13353       oappend_maybe_intel ("%gs:");
13354       break;
13355     default:
13356       break;
13357     }
13358 }
13359
13360 static void
13361 OP_indirE (int bytemode, int sizeflag)
13362 {
13363   if (!intel_syntax)
13364     oappend ("*");
13365   OP_E (bytemode, sizeflag);
13366 }
13367
13368 static void
13369 print_operand_value (char *buf, int hex, bfd_vma disp)
13370 {
13371   if (address_mode == mode_64bit)
13372     {
13373       if (hex)
13374         {
13375           char tmp[30];
13376           int i;
13377           buf[0] = '0';
13378           buf[1] = 'x';
13379           sprintf_vma (tmp, disp);
13380           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
13381           strcpy (buf + 2, tmp + i);
13382         }
13383       else
13384         {
13385           bfd_signed_vma v = disp;
13386           char tmp[30];
13387           int i;
13388           if (v < 0)
13389             {
13390               *(buf++) = '-';
13391               v = -disp;
13392               /* Check for possible overflow on 0x8000000000000000.  */
13393               if (v < 0)
13394                 {
13395                   strcpy (buf, "9223372036854775808");
13396                   return;
13397                 }
13398             }
13399           if (!v)
13400             {
13401               strcpy (buf, "0");
13402               return;
13403             }
13404
13405           i = 0;
13406           tmp[29] = 0;
13407           while (v)
13408             {
13409               tmp[28 - i] = (v % 10) + '0';
13410               v /= 10;
13411               i++;
13412             }
13413           strcpy (buf, tmp + 29 - i);
13414         }
13415     }
13416   else
13417     {
13418       if (hex)
13419         sprintf (buf, "0x%x", (unsigned int) disp);
13420       else
13421         sprintf (buf, "%d", (int) disp);
13422     }
13423 }
13424
13425 /* Put DISP in BUF as signed hex number.  */
13426
13427 static void
13428 print_displacement (char *buf, bfd_vma disp)
13429 {
13430   bfd_signed_vma val = disp;
13431   char tmp[30];
13432   int i, j = 0;
13433
13434   if (val < 0)
13435     {
13436       buf[j++] = '-';
13437       val = -disp;
13438
13439       /* Check for possible overflow.  */
13440       if (val < 0)
13441         {
13442           switch (address_mode)
13443             {
13444             case mode_64bit:
13445               strcpy (buf + j, "0x8000000000000000");
13446               break;
13447             case mode_32bit:
13448               strcpy (buf + j, "0x80000000");
13449               break;
13450             case mode_16bit:
13451               strcpy (buf + j, "0x8000");
13452               break;
13453             }
13454           return;
13455         }
13456     }
13457
13458   buf[j++] = '0';
13459   buf[j++] = 'x';
13460
13461   sprintf_vma (tmp, (bfd_vma) val);
13462   for (i = 0; tmp[i] == '0'; i++)
13463     continue;
13464   if (tmp[i] == '\0')
13465     i--;
13466   strcpy (buf + j, tmp + i);
13467 }
13468
13469 static void
13470 intel_operand_size (int bytemode, int sizeflag)
13471 {
13472   if (vex.evex
13473       && vex.b
13474       && (bytemode == x_mode
13475           || bytemode == evex_half_bcst_xmmq_mode))
13476     {
13477       if (vex.w)
13478         oappend ("QWORD PTR ");
13479       else
13480         oappend ("DWORD PTR ");
13481       return;
13482     }
13483   switch (bytemode)
13484     {
13485     case b_mode:
13486     case b_swap_mode:
13487     case dqb_mode:
13488     case db_mode:
13489       oappend ("BYTE PTR ");
13490       break;
13491     case w_mode:
13492     case dw_mode:
13493     case dqw_mode:
13494       oappend ("WORD PTR ");
13495       break;
13496     case indir_v_mode:
13497       if (address_mode == mode_64bit && isa64 == intel64)
13498         {
13499           oappend ("QWORD PTR ");
13500           break;
13501         }
13502       /* Fall through.  */
13503     case stack_v_mode:
13504       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
13505         {
13506           oappend ("QWORD PTR ");
13507           break;
13508         }
13509       /* Fall through.  */
13510     case v_mode:
13511     case v_swap_mode:
13512     case dq_mode:
13513       USED_REX (REX_W);
13514       if (rex & REX_W)
13515         oappend ("QWORD PTR ");
13516       else
13517         {
13518           if ((sizeflag & DFLAG) || bytemode == dq_mode)
13519             oappend ("DWORD PTR ");
13520           else
13521             oappend ("WORD PTR ");
13522           used_prefixes |= (prefixes & PREFIX_DATA);
13523         }
13524       break;
13525     case z_mode:
13526       if ((rex & REX_W) || (sizeflag & DFLAG))
13527         *obufp++ = 'D';
13528       oappend ("WORD PTR ");
13529       if (!(rex & REX_W))
13530         used_prefixes |= (prefixes & PREFIX_DATA);
13531       break;
13532     case a_mode:
13533       if (sizeflag & DFLAG)
13534         oappend ("QWORD PTR ");
13535       else
13536         oappend ("DWORD PTR ");
13537       used_prefixes |= (prefixes & PREFIX_DATA);
13538       break;
13539     case d_mode:
13540     case d_scalar_mode:
13541     case d_scalar_swap_mode:
13542     case d_swap_mode:
13543     case dqd_mode:
13544       oappend ("DWORD PTR ");
13545       break;
13546     case q_mode:
13547     case q_scalar_mode:
13548     case q_scalar_swap_mode:
13549     case q_swap_mode:
13550       oappend ("QWORD PTR ");
13551       break;
13552     case m_mode:
13553       if (address_mode == mode_64bit)
13554         oappend ("QWORD PTR ");
13555       else
13556         oappend ("DWORD PTR ");
13557       break;
13558     case f_mode:
13559       if (sizeflag & DFLAG)
13560         oappend ("FWORD PTR ");
13561       else
13562         oappend ("DWORD PTR ");
13563       used_prefixes |= (prefixes & PREFIX_DATA);
13564       break;
13565     case t_mode:
13566       oappend ("TBYTE PTR ");
13567       break;
13568     case x_mode:
13569     case x_swap_mode:
13570     case evex_x_gscat_mode:
13571     case evex_x_nobcst_mode:
13572     case b_scalar_mode:
13573     case w_scalar_mode:
13574       if (need_vex)
13575         {
13576           switch (vex.length)
13577             {
13578             case 128:
13579               oappend ("XMMWORD PTR ");
13580               break;
13581             case 256:
13582               oappend ("YMMWORD PTR ");
13583               break;
13584             case 512:
13585               oappend ("ZMMWORD PTR ");
13586               break;
13587             default:
13588               abort ();
13589             }
13590         }
13591       else
13592         oappend ("XMMWORD PTR ");
13593       break;
13594     case xmm_mode:
13595       oappend ("XMMWORD PTR ");
13596       break;
13597     case ymm_mode:
13598       oappend ("YMMWORD PTR ");
13599       break;
13600     case xmmq_mode:
13601     case evex_half_bcst_xmmq_mode:
13602       if (!need_vex)
13603         abort ();
13604
13605       switch (vex.length)
13606         {
13607         case 128:
13608           oappend ("QWORD PTR ");
13609           break;
13610         case 256:
13611           oappend ("XMMWORD PTR ");
13612           break;
13613         case 512:
13614           oappend ("YMMWORD PTR ");
13615           break;
13616         default:
13617           abort ();
13618         }
13619       break;
13620     case xmm_mb_mode:
13621       if (!need_vex)
13622         abort ();
13623
13624       switch (vex.length)
13625         {
13626         case 128:
13627         case 256:
13628         case 512:
13629           oappend ("BYTE PTR ");
13630           break;
13631         default:
13632           abort ();
13633         }
13634       break;
13635     case xmm_mw_mode:
13636       if (!need_vex)
13637         abort ();
13638
13639       switch (vex.length)
13640         {
13641         case 128:
13642         case 256:
13643         case 512:
13644           oappend ("WORD PTR ");
13645           break;
13646         default:
13647           abort ();
13648         }
13649       break;
13650     case xmm_md_mode:
13651       if (!need_vex)
13652         abort ();
13653
13654       switch (vex.length)
13655         {
13656         case 128:
13657         case 256:
13658         case 512:
13659           oappend ("DWORD PTR ");
13660           break;
13661         default:
13662           abort ();
13663         }
13664       break;
13665     case xmm_mq_mode:
13666       if (!need_vex)
13667         abort ();
13668
13669       switch (vex.length)
13670         {
13671         case 128:
13672         case 256:
13673         case 512:
13674           oappend ("QWORD PTR ");
13675           break;
13676         default:
13677           abort ();
13678         }
13679       break;
13680     case xmmdw_mode:
13681       if (!need_vex)
13682         abort ();
13683
13684       switch (vex.length)
13685         {
13686         case 128:
13687           oappend ("WORD PTR ");
13688           break;
13689         case 256:
13690           oappend ("DWORD PTR ");
13691           break;
13692         case 512:
13693           oappend ("QWORD PTR ");
13694           break;
13695         default:
13696           abort ();
13697         }
13698       break;
13699     case xmmqd_mode:
13700       if (!need_vex)
13701         abort ();
13702
13703       switch (vex.length)
13704         {
13705         case 128:
13706           oappend ("DWORD PTR ");
13707           break;
13708         case 256:
13709           oappend ("QWORD PTR ");
13710           break;
13711         case 512:
13712           oappend ("XMMWORD PTR ");
13713           break;
13714         default:
13715           abort ();
13716         }
13717       break;
13718     case ymmq_mode:
13719       if (!need_vex)
13720         abort ();
13721
13722       switch (vex.length)
13723         {
13724         case 128:
13725           oappend ("QWORD PTR ");
13726           break;
13727         case 256:
13728           oappend ("YMMWORD PTR ");
13729           break;
13730         case 512:
13731           oappend ("ZMMWORD PTR ");
13732           break;
13733         default:
13734           abort ();
13735         }
13736       break;
13737     case ymmxmm_mode:
13738       if (!need_vex)
13739         abort ();
13740
13741       switch (vex.length)
13742         {
13743         case 128:
13744         case 256:
13745           oappend ("XMMWORD PTR ");
13746           break;
13747         default:
13748           abort ();
13749         }
13750       break;
13751     case o_mode:
13752       oappend ("OWORD PTR ");
13753       break;
13754     case xmm_mdq_mode:
13755     case vex_w_dq_mode:
13756     case vex_scalar_w_dq_mode:
13757       if (!need_vex)
13758         abort ();
13759
13760       if (vex.w)
13761         oappend ("QWORD PTR ");
13762       else
13763         oappend ("DWORD PTR ");
13764       break;
13765     case vex_vsib_d_w_dq_mode:
13766     case vex_vsib_q_w_dq_mode:
13767       if (!need_vex)
13768         abort ();
13769
13770       if (!vex.evex)
13771         {
13772           if (vex.w)
13773             oappend ("QWORD PTR ");
13774           else
13775             oappend ("DWORD PTR ");
13776         }
13777       else
13778         {
13779           switch (vex.length)
13780             {
13781             case 128:
13782               oappend ("XMMWORD PTR ");
13783               break;
13784             case 256:
13785               oappend ("YMMWORD PTR ");
13786               break;
13787             case 512:
13788               oappend ("ZMMWORD PTR ");
13789               break;
13790             default:
13791               abort ();
13792             }
13793         }
13794       break;
13795     case vex_vsib_q_w_d_mode:
13796     case vex_vsib_d_w_d_mode:
13797       if (!need_vex || !vex.evex)
13798         abort ();
13799
13800       switch (vex.length)
13801         {
13802         case 128:
13803           oappend ("QWORD PTR ");
13804           break;
13805         case 256:
13806           oappend ("XMMWORD PTR ");
13807           break;
13808         case 512:
13809           oappend ("YMMWORD PTR ");
13810           break;
13811         default:
13812           abort ();
13813         }
13814
13815       break;
13816     case mask_bd_mode:
13817       if (!need_vex || vex.length != 128)
13818         abort ();
13819       if (vex.w)
13820         oappend ("DWORD PTR ");
13821       else
13822         oappend ("BYTE PTR ");
13823       break;
13824     case mask_mode:
13825       if (!need_vex)
13826         abort ();
13827       if (vex.w)
13828         oappend ("QWORD PTR ");
13829       else
13830         oappend ("WORD PTR ");
13831       break;
13832     case v_bnd_mode:
13833     case v_bndmk_mode:
13834     default:
13835       break;
13836     }
13837 }
13838
13839 static void
13840 OP_E_register (int bytemode, int sizeflag)
13841 {
13842   int reg = modrm.rm;
13843   const char **names;
13844
13845   USED_REX (REX_B);
13846   if ((rex & REX_B))
13847     reg += 8;
13848
13849   if ((sizeflag & SUFFIX_ALWAYS)
13850       && (bytemode == b_swap_mode
13851           || bytemode == bnd_swap_mode
13852           || bytemode == v_swap_mode))
13853     swap_operand ();
13854
13855   switch (bytemode)
13856     {
13857     case b_mode:
13858     case b_swap_mode:
13859       USED_REX (0);
13860       if (rex)
13861         names = names8rex;
13862       else
13863         names = names8;
13864       break;
13865     case w_mode:
13866       names = names16;
13867       break;
13868     case d_mode:
13869     case dw_mode:
13870     case db_mode:
13871       names = names32;
13872       break;
13873     case q_mode:
13874       names = names64;
13875       break;
13876     case m_mode:
13877     case v_bnd_mode:
13878       names = address_mode == mode_64bit ? names64 : names32;
13879       break;
13880     case bnd_mode:
13881     case bnd_swap_mode:
13882       if (reg > 0x3)
13883         {
13884           oappend ("(bad)");
13885           return;
13886         }
13887       names = names_bnd;
13888       break;
13889     case indir_v_mode:
13890       if (address_mode == mode_64bit && isa64 == intel64)
13891         {
13892           names = names64;
13893           break;
13894         }
13895       /* Fall through.  */
13896     case stack_v_mode:
13897       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
13898         {
13899           names = names64;
13900           break;
13901         }
13902       bytemode = v_mode;
13903       /* Fall through.  */
13904     case v_mode:
13905     case v_swap_mode:
13906     case dq_mode:
13907     case dqb_mode:
13908     case dqd_mode:
13909     case dqw_mode:
13910       USED_REX (REX_W);
13911       if (rex & REX_W)
13912         names = names64;
13913       else
13914         {
13915           if ((sizeflag & DFLAG)
13916               || (bytemode != v_mode
13917                   && bytemode != v_swap_mode))
13918             names = names32;
13919           else
13920             names = names16;
13921           used_prefixes |= (prefixes & PREFIX_DATA);
13922         }
13923       break;
13924     case va_mode:
13925       names = (address_mode == mode_64bit
13926                ? names64 : names32);
13927       if (!(prefixes & PREFIX_ADDR))
13928         names = (address_mode == mode_16bit
13929                      ? names16 : names);
13930       else
13931         {
13932           /* Remove "addr16/addr32".  */
13933           all_prefixes[last_addr_prefix] = 0;
13934           names = (address_mode != mode_32bit
13935                        ? names32 : names16);
13936           used_prefixes |= PREFIX_ADDR;
13937         }
13938       break;
13939     case mask_bd_mode:
13940     case mask_mode:
13941       if (reg > 0x7)
13942         {
13943           oappend ("(bad)");
13944           return;
13945         }
13946       names = names_mask;
13947       break;
13948     case 0:
13949       return;
13950     default:
13951       oappend (INTERNAL_DISASSEMBLER_ERROR);
13952       return;
13953     }
13954   oappend (names[reg]);
13955 }
13956
13957 static void
13958 OP_E_memory (int bytemode, int sizeflag)
13959 {
13960   bfd_vma disp = 0;
13961   int add = (rex & REX_B) ? 8 : 0;
13962   int riprel = 0;
13963   int shift;
13964
13965   if (vex.evex)
13966     {
13967       /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0.  */
13968       if (vex.b
13969           && bytemode != x_mode
13970           && bytemode != xmmq_mode
13971           && bytemode != evex_half_bcst_xmmq_mode)
13972         {
13973           BadOp ();
13974           return;
13975         }
13976       switch (bytemode)
13977         {
13978         case dqw_mode:
13979         case dw_mode:
13980           shift = 1;
13981           break;
13982         case dqb_mode:
13983         case db_mode:
13984           shift = 0;
13985           break;
13986         case dq_mode:
13987           if (address_mode != mode_64bit)
13988             {
13989               shift = 2;
13990               break;
13991             }
13992             /* fall through */
13993         case vex_vsib_d_w_dq_mode:
13994         case vex_vsib_d_w_d_mode:
13995         case vex_vsib_q_w_dq_mode:
13996         case vex_vsib_q_w_d_mode:
13997         case evex_x_gscat_mode:
13998         case xmm_mdq_mode:
13999           shift = vex.w ? 3 : 2;
14000           break;
14001         case x_mode:
14002         case evex_half_bcst_xmmq_mode:
14003         case xmmq_mode:
14004           if (vex.b)
14005             {
14006               shift = vex.w ? 3 : 2;
14007               break;
14008             }
14009           /* Fall through.  */
14010         case xmmqd_mode:
14011         case xmmdw_mode:
14012         case ymmq_mode:
14013         case evex_x_nobcst_mode:
14014         case x_swap_mode:
14015           switch (vex.length)
14016             {
14017             case 128:
14018               shift = 4;
14019               break;
14020             case 256:
14021               shift = 5;
14022               break;
14023             case 512:
14024               shift = 6;
14025               break;
14026             default:
14027               abort ();
14028             }
14029           break;
14030         case ymm_mode:
14031           shift = 5;
14032           break;
14033         case xmm_mode:
14034           shift = 4;
14035           break;
14036         case xmm_mq_mode:
14037         case q_mode:
14038         case q_scalar_mode:
14039         case q_swap_mode:
14040         case q_scalar_swap_mode:
14041           shift = 3;
14042           break;
14043         case dqd_mode:
14044         case xmm_md_mode:
14045         case d_mode:
14046         case d_scalar_mode:
14047         case d_swap_mode:
14048         case d_scalar_swap_mode:
14049           shift = 2;
14050           break;
14051         case w_scalar_mode:
14052         case xmm_mw_mode:
14053           shift = 1;
14054           break;
14055         case b_scalar_mode:
14056         case xmm_mb_mode:
14057           shift = 0;
14058           break;
14059         default:
14060           abort ();
14061         }
14062       /* Make necessary corrections to shift for modes that need it.
14063          For these modes we currently have shift 4, 5 or 6 depending on
14064          vex.length (it corresponds to xmmword, ymmword or zmmword
14065          operand).  We might want to make it 3, 4 or 5 (e.g. for
14066          xmmq_mode).  In case of broadcast enabled the corrections
14067          aren't needed, as element size is always 32 or 64 bits.  */
14068       if (!vex.b
14069           && (bytemode == xmmq_mode
14070               || bytemode == evex_half_bcst_xmmq_mode))
14071         shift -= 1;
14072       else if (bytemode == xmmqd_mode)
14073         shift -= 2;
14074       else if (bytemode == xmmdw_mode)
14075         shift -= 3;
14076       else if (bytemode == ymmq_mode && vex.length == 128)
14077         shift -= 1;
14078     }
14079   else
14080     shift = 0;
14081
14082   USED_REX (REX_B);
14083   if (intel_syntax)
14084     intel_operand_size (bytemode, sizeflag);
14085   append_seg ();
14086
14087   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14088     {
14089       /* 32/64 bit address mode */
14090       int havedisp;
14091       int havesib;
14092       int havebase;
14093       int haveindex;
14094       int needindex;
14095       int needaddr32;
14096       int base, rbase;
14097       int vindex = 0;
14098       int scale = 0;
14099       int addr32flag = !((sizeflag & AFLAG)
14100                          || bytemode == v_bnd_mode
14101                          || bytemode == v_bndmk_mode
14102                          || bytemode == bnd_mode
14103                          || bytemode == bnd_swap_mode);
14104       const char **indexes64 = names64;
14105       const char **indexes32 = names32;
14106
14107       havesib = 0;
14108       havebase = 1;
14109       haveindex = 0;
14110       base = modrm.rm;
14111
14112       if (base == 4)
14113         {
14114           havesib = 1;
14115           vindex = sib.index;
14116           USED_REX (REX_X);
14117           if (rex & REX_X)
14118             vindex += 8;
14119           switch (bytemode)
14120             {
14121             case vex_vsib_d_w_dq_mode:
14122             case vex_vsib_d_w_d_mode:
14123             case vex_vsib_q_w_dq_mode:
14124             case vex_vsib_q_w_d_mode:
14125               if (!need_vex)
14126                 abort ();
14127               if (vex.evex)
14128                 {
14129                   if (!vex.v)
14130                     vindex += 16;
14131                 }
14132
14133               haveindex = 1;
14134               switch (vex.length)
14135                 {
14136                 case 128:
14137                   indexes64 = indexes32 = names_xmm;
14138                   break;
14139                 case 256:
14140                   if (!vex.w
14141                       || bytemode == vex_vsib_q_w_dq_mode
14142                       || bytemode == vex_vsib_q_w_d_mode)
14143                     indexes64 = indexes32 = names_ymm;
14144                   else
14145                     indexes64 = indexes32 = names_xmm;
14146                   break;
14147                 case 512:
14148                   if (!vex.w
14149                       || bytemode == vex_vsib_q_w_dq_mode
14150                       || bytemode == vex_vsib_q_w_d_mode)
14151                     indexes64 = indexes32 = names_zmm;
14152                   else
14153                     indexes64 = indexes32 = names_ymm;
14154                   break;
14155                 default:
14156                   abort ();
14157                 }
14158               break;
14159             default:
14160               haveindex = vindex != 4;
14161               break;
14162             }
14163           scale = sib.scale;
14164           base = sib.base;
14165           codep++;
14166         }
14167       rbase = base + add;
14168
14169       switch (modrm.mod)
14170         {
14171         case 0:
14172           if (base == 5)
14173             {
14174               havebase = 0;
14175               if (address_mode == mode_64bit && !havesib)
14176                 riprel = 1;
14177               disp = get32s ();
14178               if (riprel && bytemode == v_bndmk_mode)
14179                 {
14180                   oappend ("(bad)");
14181                   return;
14182                 }
14183             }
14184           break;
14185         case 1:
14186           FETCH_DATA (the_info, codep + 1);
14187           disp = *codep++;
14188           if ((disp & 0x80) != 0)
14189             disp -= 0x100;
14190           if (vex.evex && shift > 0)
14191             disp <<= shift;
14192           break;
14193         case 2:
14194           disp = get32s ();
14195           break;
14196         }
14197
14198       needindex = 0;
14199       needaddr32 = 0;
14200       if (havesib
14201           && !havebase
14202           && !haveindex
14203           && address_mode != mode_16bit)
14204         {
14205           if (address_mode == mode_64bit)
14206             {
14207               /* Display eiz instead of addr32.  */
14208               needindex = addr32flag;
14209               needaddr32 = 1;
14210             }
14211           else
14212             {
14213               /* In 32-bit mode, we need index register to tell [offset]
14214                  from [eiz*1 + offset].  */
14215               needindex = 1;
14216             }
14217         }
14218
14219       havedisp = (havebase
14220                   || needindex
14221                   || (havesib && (haveindex || scale != 0)));
14222
14223       if (!intel_syntax)
14224         if (modrm.mod != 0 || base == 5)
14225           {
14226             if (havedisp || riprel)
14227               print_displacement (scratchbuf, disp);
14228             else
14229               print_operand_value (scratchbuf, 1, disp);
14230             oappend (scratchbuf);
14231             if (riprel)
14232               {
14233                 set_op (disp, 1);
14234                 oappend (!addr32flag ? "(%rip)" : "(%eip)");
14235               }
14236           }
14237
14238       if ((havebase || haveindex || needindex || needaddr32 || riprel)
14239           && (bytemode != v_bnd_mode)
14240           && (bytemode != v_bndmk_mode)
14241           && (bytemode != bnd_mode)
14242           && (bytemode != bnd_swap_mode))
14243         used_prefixes |= PREFIX_ADDR;
14244
14245       if (havedisp || (intel_syntax && riprel))
14246         {
14247           *obufp++ = open_char;
14248           if (intel_syntax && riprel)
14249             {
14250               set_op (disp, 1);
14251               oappend (!addr32flag ? "rip" : "eip");
14252             }
14253           *obufp = '\0';
14254           if (havebase)
14255             oappend (address_mode == mode_64bit && !addr32flag
14256                      ? names64[rbase] : names32[rbase]);
14257           if (havesib)
14258             {
14259               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
14260                  print index to tell base + index from base.  */
14261               if (scale != 0
14262                   || needindex
14263                   || haveindex
14264                   || (havebase && base != ESP_REG_NUM))
14265                 {
14266                   if (!intel_syntax || havebase)
14267                     {
14268                       *obufp++ = separator_char;
14269                       *obufp = '\0';
14270                     }
14271                   if (haveindex)
14272                     oappend (address_mode == mode_64bit && !addr32flag
14273                              ? indexes64[vindex] : indexes32[vindex]);
14274                   else
14275                     oappend (address_mode == mode_64bit && !addr32flag
14276                              ? index64 : index32);
14277
14278                   *obufp++ = scale_char;
14279                   *obufp = '\0';
14280                   sprintf (scratchbuf, "%d", 1 << scale);
14281                   oappend (scratchbuf);
14282                 }
14283             }
14284           if (intel_syntax
14285               && (disp || modrm.mod != 0 || base == 5))
14286             {
14287               if (!havedisp || (bfd_signed_vma) disp >= 0)
14288                 {
14289                   *obufp++ = '+';
14290                   *obufp = '\0';
14291                 }
14292               else if (modrm.mod != 1 && disp != -disp)
14293                 {
14294                   *obufp++ = '-';
14295                   *obufp = '\0';
14296                   disp = - (bfd_signed_vma) disp;
14297                 }
14298
14299               if (havedisp)
14300                 print_displacement (scratchbuf, disp);
14301               else
14302                 print_operand_value (scratchbuf, 1, disp);
14303               oappend (scratchbuf);
14304             }
14305
14306           *obufp++ = close_char;
14307           *obufp = '\0';
14308         }
14309       else if (intel_syntax)
14310         {
14311           if (modrm.mod != 0 || base == 5)
14312             {
14313               if (!active_seg_prefix)
14314                 {
14315                   oappend (names_seg[ds_reg - es_reg]);
14316                   oappend (":");
14317                 }
14318               print_operand_value (scratchbuf, 1, disp);
14319               oappend (scratchbuf);
14320             }
14321         }
14322     }
14323   else
14324     {
14325       /* 16 bit address mode */
14326       used_prefixes |= prefixes & PREFIX_ADDR;
14327       switch (modrm.mod)
14328         {
14329         case 0:
14330           if (modrm.rm == 6)
14331             {
14332               disp = get16 ();
14333               if ((disp & 0x8000) != 0)
14334                 disp -= 0x10000;
14335             }
14336           break;
14337         case 1:
14338           FETCH_DATA (the_info, codep + 1);
14339           disp = *codep++;
14340           if ((disp & 0x80) != 0)
14341             disp -= 0x100;
14342           if (vex.evex && shift > 0)
14343             disp <<= shift;
14344           break;
14345         case 2:
14346           disp = get16 ();
14347           if ((disp & 0x8000) != 0)
14348             disp -= 0x10000;
14349           break;
14350         }
14351
14352       if (!intel_syntax)
14353         if (modrm.mod != 0 || modrm.rm == 6)
14354           {
14355             print_displacement (scratchbuf, disp);
14356             oappend (scratchbuf);
14357           }
14358
14359       if (modrm.mod != 0 || modrm.rm != 6)
14360         {
14361           *obufp++ = open_char;
14362           *obufp = '\0';
14363           oappend (index16[modrm.rm]);
14364           if (intel_syntax
14365               && (disp || modrm.mod != 0 || modrm.rm == 6))
14366             {
14367               if ((bfd_signed_vma) disp >= 0)
14368                 {
14369                   *obufp++ = '+';
14370                   *obufp = '\0';
14371                 }
14372               else if (modrm.mod != 1)
14373                 {
14374                   *obufp++ = '-';
14375                   *obufp = '\0';
14376                   disp = - (bfd_signed_vma) disp;
14377                 }
14378
14379               print_displacement (scratchbuf, disp);
14380               oappend (scratchbuf);
14381             }
14382
14383           *obufp++ = close_char;
14384           *obufp = '\0';
14385         }
14386       else if (intel_syntax)
14387         {
14388           if (!active_seg_prefix)
14389             {
14390               oappend (names_seg[ds_reg - es_reg]);
14391               oappend (":");
14392             }
14393           print_operand_value (scratchbuf, 1, disp & 0xffff);
14394           oappend (scratchbuf);
14395         }
14396     }
14397   if (vex.evex && vex.b
14398       && (bytemode == x_mode
14399           || bytemode == xmmq_mode
14400           || bytemode == evex_half_bcst_xmmq_mode))
14401     {
14402       if (vex.w
14403           || bytemode == xmmq_mode
14404           || bytemode == evex_half_bcst_xmmq_mode)
14405         {
14406           switch (vex.length)
14407             {
14408             case 128:
14409               oappend ("{1to2}");
14410               break;
14411             case 256:
14412               oappend ("{1to4}");
14413               break;
14414             case 512:
14415               oappend ("{1to8}");
14416               break;
14417             default:
14418               abort ();
14419             }
14420         }
14421       else
14422         {
14423           switch (vex.length)
14424             {
14425             case 128:
14426               oappend ("{1to4}");
14427               break;
14428             case 256:
14429               oappend ("{1to8}");
14430               break;
14431             case 512:
14432               oappend ("{1to16}");
14433               break;
14434             default:
14435               abort ();
14436             }
14437         }
14438     }
14439 }
14440
14441 static void
14442 OP_E (int bytemode, int sizeflag)
14443 {
14444   /* Skip mod/rm byte.  */
14445   MODRM_CHECK;
14446   codep++;
14447
14448   if (modrm.mod == 3)
14449     OP_E_register (bytemode, sizeflag);
14450   else
14451     OP_E_memory (bytemode, sizeflag);
14452 }
14453
14454 static void
14455 OP_G (int bytemode, int sizeflag)
14456 {
14457   int add = 0;
14458   const char **names;
14459   USED_REX (REX_R);
14460   if (rex & REX_R)
14461     add += 8;
14462   switch (bytemode)
14463     {
14464     case b_mode:
14465       USED_REX (0);
14466       if (rex)
14467         oappend (names8rex[modrm.reg + add]);
14468       else
14469         oappend (names8[modrm.reg + add]);
14470       break;
14471     case w_mode:
14472       oappend (names16[modrm.reg + add]);
14473       break;
14474     case d_mode:
14475     case db_mode:
14476     case dw_mode:
14477       oappend (names32[modrm.reg + add]);
14478       break;
14479     case q_mode:
14480       oappend (names64[modrm.reg + add]);
14481       break;
14482     case bnd_mode:
14483       if (modrm.reg > 0x3)
14484         {
14485           oappend ("(bad)");
14486           return;
14487         }
14488       oappend (names_bnd[modrm.reg]);
14489       break;
14490     case v_mode:
14491     case dq_mode:
14492     case dqb_mode:
14493     case dqd_mode:
14494     case dqw_mode:
14495       USED_REX (REX_W);
14496       if (rex & REX_W)
14497         oappend (names64[modrm.reg + add]);
14498       else
14499         {
14500           if ((sizeflag & DFLAG) || bytemode != v_mode)
14501             oappend (names32[modrm.reg + add]);
14502           else
14503             oappend (names16[modrm.reg + add]);
14504           used_prefixes |= (prefixes & PREFIX_DATA);
14505         }
14506       break;
14507     case va_mode:
14508       names = (address_mode == mode_64bit
14509                ? names64 : names32);
14510       if (!(prefixes & PREFIX_ADDR))
14511         {
14512           if (address_mode == mode_16bit)
14513             names = names16;
14514         }
14515       else
14516         {
14517           /* Remove "addr16/addr32".  */
14518           all_prefixes[last_addr_prefix] = 0;
14519           names = (address_mode != mode_32bit
14520                        ? names32 : names16);
14521           used_prefixes |= PREFIX_ADDR;
14522         }
14523       oappend (names[modrm.reg + add]);
14524       break;
14525     case m_mode:
14526       if (address_mode == mode_64bit)
14527         oappend (names64[modrm.reg + add]);
14528       else
14529         oappend (names32[modrm.reg + add]);
14530       break;
14531     case mask_bd_mode:
14532     case mask_mode:
14533       if ((modrm.reg + add) > 0x7)
14534         {
14535           oappend ("(bad)");
14536           return;
14537         }
14538       oappend (names_mask[modrm.reg + add]);
14539       break;
14540     default:
14541       oappend (INTERNAL_DISASSEMBLER_ERROR);
14542       break;
14543     }
14544 }
14545
14546 static bfd_vma
14547 get64 (void)
14548 {
14549   bfd_vma x;
14550 #ifdef BFD64
14551   unsigned int a;
14552   unsigned int b;
14553
14554   FETCH_DATA (the_info, codep + 8);
14555   a = *codep++ & 0xff;
14556   a |= (*codep++ & 0xff) << 8;
14557   a |= (*codep++ & 0xff) << 16;
14558   a |= (*codep++ & 0xffu) << 24;
14559   b = *codep++ & 0xff;
14560   b |= (*codep++ & 0xff) << 8;
14561   b |= (*codep++ & 0xff) << 16;
14562   b |= (*codep++ & 0xffu) << 24;
14563   x = a + ((bfd_vma) b << 32);
14564 #else
14565   abort ();
14566   x = 0;
14567 #endif
14568   return x;
14569 }
14570
14571 static bfd_signed_vma
14572 get32 (void)
14573 {
14574   bfd_signed_vma x = 0;
14575
14576   FETCH_DATA (the_info, codep + 4);
14577   x = *codep++ & (bfd_signed_vma) 0xff;
14578   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14579   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14580   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14581   return x;
14582 }
14583
14584 static bfd_signed_vma
14585 get32s (void)
14586 {
14587   bfd_signed_vma x = 0;
14588
14589   FETCH_DATA (the_info, codep + 4);
14590   x = *codep++ & (bfd_signed_vma) 0xff;
14591   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14592   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14593   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14594
14595   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
14596
14597   return x;
14598 }
14599
14600 static int
14601 get16 (void)
14602 {
14603   int x = 0;
14604
14605   FETCH_DATA (the_info, codep + 2);
14606   x = *codep++ & 0xff;
14607   x |= (*codep++ & 0xff) << 8;
14608   return x;
14609 }
14610
14611 static void
14612 set_op (bfd_vma op, int riprel)
14613 {
14614   op_index[op_ad] = op_ad;
14615   if (address_mode == mode_64bit)
14616     {
14617       op_address[op_ad] = op;
14618       op_riprel[op_ad] = riprel;
14619     }
14620   else
14621     {
14622       /* Mask to get a 32-bit address.  */
14623       op_address[op_ad] = op & 0xffffffff;
14624       op_riprel[op_ad] = riprel & 0xffffffff;
14625     }
14626 }
14627
14628 static void
14629 OP_REG (int code, int sizeflag)
14630 {
14631   const char *s;
14632   int add;
14633
14634   switch (code)
14635     {
14636     case es_reg: case ss_reg: case cs_reg:
14637     case ds_reg: case fs_reg: case gs_reg:
14638       oappend (names_seg[code - es_reg]);
14639       return;
14640     }
14641
14642   USED_REX (REX_B);
14643   if (rex & REX_B)
14644     add = 8;
14645   else
14646     add = 0;
14647
14648   switch (code)
14649     {
14650     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14651     case sp_reg: case bp_reg: case si_reg: case di_reg:
14652       s = names16[code - ax_reg + add];
14653       break;
14654     case al_reg: case ah_reg: case cl_reg: case ch_reg:
14655     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14656       USED_REX (0);
14657       if (rex)
14658         s = names8rex[code - al_reg + add];
14659       else
14660         s = names8[code - al_reg];
14661       break;
14662     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
14663     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
14664       if (address_mode == mode_64bit
14665           && ((sizeflag & DFLAG) || (rex & REX_W)))
14666         {
14667           s = names64[code - rAX_reg + add];
14668           break;
14669         }
14670       code += eAX_reg - rAX_reg;
14671       /* Fall through.  */
14672     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14673     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14674       USED_REX (REX_W);
14675       if (rex & REX_W)
14676         s = names64[code - eAX_reg + add];
14677       else
14678         {
14679           if (sizeflag & DFLAG)
14680             s = names32[code - eAX_reg + add];
14681           else
14682             s = names16[code - eAX_reg + add];
14683           used_prefixes |= (prefixes & PREFIX_DATA);
14684         }
14685       break;
14686     default:
14687       s = INTERNAL_DISASSEMBLER_ERROR;
14688       break;
14689     }
14690   oappend (s);
14691 }
14692
14693 static void
14694 OP_IMREG (int code, int sizeflag)
14695 {
14696   const char *s;
14697
14698   switch (code)
14699     {
14700     case indir_dx_reg:
14701       if (intel_syntax)
14702         s = "dx";
14703       else
14704         s = "(%dx)";
14705       break;
14706     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14707     case sp_reg: case bp_reg: case si_reg: case di_reg:
14708       s = names16[code - ax_reg];
14709       break;
14710     case es_reg: case ss_reg: case cs_reg:
14711     case ds_reg: case fs_reg: case gs_reg:
14712       s = names_seg[code - es_reg];
14713       break;
14714     case al_reg: case ah_reg: case cl_reg: case ch_reg:
14715     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14716       USED_REX (0);
14717       if (rex)
14718         s = names8rex[code - al_reg];
14719       else
14720         s = names8[code - al_reg];
14721       break;
14722     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14723     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14724       USED_REX (REX_W);
14725       if (rex & REX_W)
14726         s = names64[code - eAX_reg];
14727       else
14728         {
14729           if (sizeflag & DFLAG)
14730             s = names32[code - eAX_reg];
14731           else
14732             s = names16[code - eAX_reg];
14733           used_prefixes |= (prefixes & PREFIX_DATA);
14734         }
14735       break;
14736     case z_mode_ax_reg:
14737       if ((rex & REX_W) || (sizeflag & DFLAG))
14738         s = *names32;
14739       else
14740         s = *names16;
14741       if (!(rex & REX_W))
14742         used_prefixes |= (prefixes & PREFIX_DATA);
14743       break;
14744     default:
14745       s = INTERNAL_DISASSEMBLER_ERROR;
14746       break;
14747     }
14748   oappend (s);
14749 }
14750
14751 static void
14752 OP_I (int bytemode, int sizeflag)
14753 {
14754   bfd_signed_vma op;
14755   bfd_signed_vma mask = -1;
14756
14757   switch (bytemode)
14758     {
14759     case b_mode:
14760       FETCH_DATA (the_info, codep + 1);
14761       op = *codep++;
14762       mask = 0xff;
14763       break;
14764     case v_mode:
14765       USED_REX (REX_W);
14766       if (rex & REX_W)
14767         op = get32s ();
14768       else
14769         {
14770           if (sizeflag & DFLAG)
14771             {
14772               op = get32 ();
14773               mask = 0xffffffff;
14774             }
14775           else
14776             {
14777               op = get16 ();
14778               mask = 0xfffff;
14779             }
14780           used_prefixes |= (prefixes & PREFIX_DATA);
14781         }
14782       break;
14783     case d_mode:
14784       mask = 0xffffffff;
14785       op = get32 ();
14786       break;
14787     case w_mode:
14788       mask = 0xfffff;
14789       op = get16 ();
14790       break;
14791     case const_1_mode:
14792       if (intel_syntax)
14793         oappend ("1");
14794       return;
14795     default:
14796       oappend (INTERNAL_DISASSEMBLER_ERROR);
14797       return;
14798     }
14799
14800   op &= mask;
14801   scratchbuf[0] = '$';
14802   print_operand_value (scratchbuf + 1, 1, op);
14803   oappend_maybe_intel (scratchbuf);
14804   scratchbuf[0] = '\0';
14805 }
14806
14807 static void
14808 OP_I64 (int bytemode, int sizeflag)
14809 {
14810   if (bytemode != v_mode || address_mode != mode_64bit || !(rex & REX_W))
14811     {
14812       OP_I (bytemode, sizeflag);
14813       return;
14814     }
14815
14816   USED_REX (REX_W);
14817
14818   scratchbuf[0] = '$';
14819   print_operand_value (scratchbuf + 1, 1, get64 ());
14820   oappend_maybe_intel (scratchbuf);
14821   scratchbuf[0] = '\0';
14822 }
14823
14824 static void
14825 OP_sI (int bytemode, int sizeflag)
14826 {
14827   bfd_signed_vma op;
14828
14829   switch (bytemode)
14830     {
14831     case b_mode:
14832     case b_T_mode:
14833       FETCH_DATA (the_info, codep + 1);
14834       op = *codep++;
14835       if ((op & 0x80) != 0)
14836         op -= 0x100;
14837       if (bytemode == b_T_mode)
14838         {
14839           if (address_mode != mode_64bit
14840               || !((sizeflag & DFLAG) || (rex & REX_W)))
14841             {
14842               /* The operand-size prefix is overridden by a REX prefix.  */
14843               if ((sizeflag & DFLAG) || (rex & REX_W))
14844                 op &= 0xffffffff;
14845               else
14846                 op &= 0xffff;
14847           }
14848         }
14849       else
14850         {
14851           if (!(rex & REX_W))
14852             {
14853               if (sizeflag & DFLAG)
14854                 op &= 0xffffffff;
14855               else
14856                 op &= 0xffff;
14857             }
14858         }
14859       break;
14860     case v_mode:
14861       /* The operand-size prefix is overridden by a REX prefix.  */
14862       if ((sizeflag & DFLAG) || (rex & REX_W))
14863         op = get32s ();
14864       else
14865         op = get16 ();
14866       break;
14867     default:
14868       oappend (INTERNAL_DISASSEMBLER_ERROR);
14869       return;
14870     }
14871
14872   scratchbuf[0] = '$';
14873   print_operand_value (scratchbuf + 1, 1, op);
14874   oappend_maybe_intel (scratchbuf);
14875 }
14876
14877 static void
14878 OP_J (int bytemode, int sizeflag)
14879 {
14880   bfd_vma disp;
14881   bfd_vma mask = -1;
14882   bfd_vma segment = 0;
14883
14884   switch (bytemode)
14885     {
14886     case b_mode:
14887       FETCH_DATA (the_info, codep + 1);
14888       disp = *codep++;
14889       if ((disp & 0x80) != 0)
14890         disp -= 0x100;
14891       break;
14892     case v_mode:
14893       if (isa64 != intel64)
14894     case dqw_mode:
14895         USED_REX (REX_W);
14896       if ((sizeflag & DFLAG)
14897           || (address_mode == mode_64bit
14898               && ((isa64 == intel64 && bytemode != dqw_mode)
14899                   || (rex & REX_W))))
14900         disp = get32s ();
14901       else
14902         {
14903           disp = get16 ();
14904           if ((disp & 0x8000) != 0)
14905             disp -= 0x10000;
14906           /* In 16bit mode, address is wrapped around at 64k within
14907              the same segment.  Otherwise, a data16 prefix on a jump
14908              instruction means that the pc is masked to 16 bits after
14909              the displacement is added!  */
14910           mask = 0xffff;
14911           if ((prefixes & PREFIX_DATA) == 0)
14912             segment = ((start_pc + (codep - start_codep))
14913                        & ~((bfd_vma) 0xffff));
14914         }
14915       if (address_mode != mode_64bit
14916           || (isa64 != intel64 && !(rex & REX_W)))
14917         used_prefixes |= (prefixes & PREFIX_DATA);
14918       break;
14919     default:
14920       oappend (INTERNAL_DISASSEMBLER_ERROR);
14921       return;
14922     }
14923   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
14924   set_op (disp, 0);
14925   print_operand_value (scratchbuf, 1, disp);
14926   oappend (scratchbuf);
14927 }
14928
14929 static void
14930 OP_SEG (int bytemode, int sizeflag)
14931 {
14932   if (bytemode == w_mode)
14933     oappend (names_seg[modrm.reg]);
14934   else
14935     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
14936 }
14937
14938 static void
14939 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
14940 {
14941   int seg, offset;
14942
14943   if (sizeflag & DFLAG)
14944     {
14945       offset = get32 ();
14946       seg = get16 ();
14947     }
14948   else
14949     {
14950       offset = get16 ();
14951       seg = get16 ();
14952     }
14953   used_prefixes |= (prefixes & PREFIX_DATA);
14954   if (intel_syntax)
14955     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
14956   else
14957     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
14958   oappend (scratchbuf);
14959 }
14960
14961 static void
14962 OP_OFF (int bytemode, int sizeflag)
14963 {
14964   bfd_vma off;
14965
14966   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
14967     intel_operand_size (bytemode, sizeflag);
14968   append_seg ();
14969
14970   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14971     off = get32 ();
14972   else
14973     off = get16 ();
14974
14975   if (intel_syntax)
14976     {
14977       if (!active_seg_prefix)
14978         {
14979           oappend (names_seg[ds_reg - es_reg]);
14980           oappend (":");
14981         }
14982     }
14983   print_operand_value (scratchbuf, 1, off);
14984   oappend (scratchbuf);
14985 }
14986
14987 static void
14988 OP_OFF64 (int bytemode, int sizeflag)
14989 {
14990   bfd_vma off;
14991
14992   if (address_mode != mode_64bit
14993       || (prefixes & PREFIX_ADDR))
14994     {
14995       OP_OFF (bytemode, sizeflag);
14996       return;
14997     }
14998
14999   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
15000     intel_operand_size (bytemode, sizeflag);
15001   append_seg ();
15002
15003   off = get64 ();
15004
15005   if (intel_syntax)
15006     {
15007       if (!active_seg_prefix)
15008         {
15009           oappend (names_seg[ds_reg - es_reg]);
15010           oappend (":");
15011         }
15012     }
15013   print_operand_value (scratchbuf, 1, off);
15014   oappend (scratchbuf);
15015 }
15016
15017 static void
15018 ptr_reg (int code, int sizeflag)
15019 {
15020   const char *s;
15021
15022   *obufp++ = open_char;
15023   used_prefixes |= (prefixes & PREFIX_ADDR);
15024   if (address_mode == mode_64bit)
15025     {
15026       if (!(sizeflag & AFLAG))
15027         s = names32[code - eAX_reg];
15028       else
15029         s = names64[code - eAX_reg];
15030     }
15031   else if (sizeflag & AFLAG)
15032     s = names32[code - eAX_reg];
15033   else
15034     s = names16[code - eAX_reg];
15035   oappend (s);
15036   *obufp++ = close_char;
15037   *obufp = 0;
15038 }
15039
15040 static void
15041 OP_ESreg (int code, int sizeflag)
15042 {
15043   if (intel_syntax)
15044     {
15045       switch (codep[-1])
15046         {
15047         case 0x6d:      /* insw/insl */
15048           intel_operand_size (z_mode, sizeflag);
15049           break;
15050         case 0xa5:      /* movsw/movsl/movsq */
15051         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15052         case 0xab:      /* stosw/stosl */
15053         case 0xaf:      /* scasw/scasl */
15054           intel_operand_size (v_mode, sizeflag);
15055           break;
15056         default:
15057           intel_operand_size (b_mode, sizeflag);
15058         }
15059     }
15060   oappend_maybe_intel ("%es:");
15061   ptr_reg (code, sizeflag);
15062 }
15063
15064 static void
15065 OP_DSreg (int code, int sizeflag)
15066 {
15067   if (intel_syntax)
15068     {
15069       switch (codep[-1])
15070         {
15071         case 0x6f:      /* outsw/outsl */
15072           intel_operand_size (z_mode, sizeflag);
15073           break;
15074         case 0xa5:      /* movsw/movsl/movsq */
15075         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15076         case 0xad:      /* lodsw/lodsl/lodsq */
15077           intel_operand_size (v_mode, sizeflag);
15078           break;
15079         default:
15080           intel_operand_size (b_mode, sizeflag);
15081         }
15082     }
15083   /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
15084      default segment register DS is printed.  */
15085   if (!active_seg_prefix)
15086     active_seg_prefix = PREFIX_DS;
15087   append_seg ();
15088   ptr_reg (code, sizeflag);
15089 }
15090
15091 static void
15092 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15093 {
15094   int add;
15095   if (rex & REX_R)
15096     {
15097       USED_REX (REX_R);
15098       add = 8;
15099     }
15100   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
15101     {
15102       all_prefixes[last_lock_prefix] = 0;
15103       used_prefixes |= PREFIX_LOCK;
15104       add = 8;
15105     }
15106   else
15107     add = 0;
15108   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
15109   oappend_maybe_intel (scratchbuf);
15110 }
15111
15112 static void
15113 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15114 {
15115   int add;
15116   USED_REX (REX_R);
15117   if (rex & REX_R)
15118     add = 8;
15119   else
15120     add = 0;
15121   if (intel_syntax)
15122     sprintf (scratchbuf, "db%d", modrm.reg + add);
15123   else
15124     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
15125   oappend (scratchbuf);
15126 }
15127
15128 static void
15129 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15130 {
15131   sprintf (scratchbuf, "%%tr%d", modrm.reg);
15132   oappend_maybe_intel (scratchbuf);
15133 }
15134
15135 static void
15136 OP_R (int bytemode, int sizeflag)
15137 {
15138   /* Skip mod/rm byte.  */
15139   MODRM_CHECK;
15140   codep++;
15141   OP_E_register (bytemode, sizeflag);
15142 }
15143
15144 static void
15145 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15146 {
15147   int reg = modrm.reg;
15148   const char **names;
15149
15150   used_prefixes |= (prefixes & PREFIX_DATA);
15151   if (prefixes & PREFIX_DATA)
15152     {
15153       names = names_xmm;
15154       USED_REX (REX_R);
15155       if (rex & REX_R)
15156         reg += 8;
15157     }
15158   else
15159     names = names_mm;
15160   oappend (names[reg]);
15161 }
15162
15163 static void
15164 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15165 {
15166   int reg = modrm.reg;
15167   const char **names;
15168
15169   USED_REX (REX_R);
15170   if (rex & REX_R)
15171     reg += 8;
15172   if (vex.evex)
15173     {
15174       if (!vex.r)
15175         reg += 16;
15176     }
15177
15178   if (need_vex
15179       && bytemode != xmm_mode
15180       && bytemode != xmmq_mode
15181       && bytemode != evex_half_bcst_xmmq_mode
15182       && bytemode != ymm_mode
15183       && bytemode != scalar_mode)
15184     {
15185       switch (vex.length)
15186         {
15187         case 128:
15188           names = names_xmm;
15189           break;
15190         case 256:
15191           if (vex.w
15192               || (bytemode != vex_vsib_q_w_dq_mode
15193                   && bytemode != vex_vsib_q_w_d_mode))
15194             names = names_ymm;
15195           else
15196             names = names_xmm;
15197           break;
15198         case 512:
15199           names = names_zmm;
15200           break;
15201         default:
15202           abort ();
15203         }
15204     }
15205   else if (bytemode == xmmq_mode
15206            || bytemode == evex_half_bcst_xmmq_mode)
15207     {
15208       switch (vex.length)
15209         {
15210         case 128:
15211         case 256:
15212           names = names_xmm;
15213           break;
15214         case 512:
15215           names = names_ymm;
15216           break;
15217         default:
15218           abort ();
15219         }
15220     }
15221   else if (bytemode == ymm_mode)
15222     names = names_ymm;
15223   else
15224     names = names_xmm;
15225   oappend (names[reg]);
15226 }
15227
15228 static void
15229 OP_EM (int bytemode, int sizeflag)
15230 {
15231   int reg;
15232   const char **names;
15233
15234   if (modrm.mod != 3)
15235     {
15236       if (intel_syntax
15237           && (bytemode == v_mode || bytemode == v_swap_mode))
15238         {
15239           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15240           used_prefixes |= (prefixes & PREFIX_DATA);
15241         }
15242       OP_E (bytemode, sizeflag);
15243       return;
15244     }
15245
15246   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
15247     swap_operand ();
15248
15249   /* Skip mod/rm byte.  */
15250   MODRM_CHECK;
15251   codep++;
15252   used_prefixes |= (prefixes & PREFIX_DATA);
15253   reg = modrm.rm;
15254   if (prefixes & PREFIX_DATA)
15255     {
15256       names = names_xmm;
15257       USED_REX (REX_B);
15258       if (rex & REX_B)
15259         reg += 8;
15260     }
15261   else
15262     names = names_mm;
15263   oappend (names[reg]);
15264 }
15265
15266 /* cvt* are the only instructions in sse2 which have
15267    both SSE and MMX operands and also have 0x66 prefix
15268    in their opcode. 0x66 was originally used to differentiate
15269    between SSE and MMX instruction(operands). So we have to handle the
15270    cvt* separately using OP_EMC and OP_MXC */
15271 static void
15272 OP_EMC (int bytemode, int sizeflag)
15273 {
15274   if (modrm.mod != 3)
15275     {
15276       if (intel_syntax && bytemode == v_mode)
15277         {
15278           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15279           used_prefixes |= (prefixes & PREFIX_DATA);
15280         }
15281       OP_E (bytemode, sizeflag);
15282       return;
15283     }
15284
15285   /* Skip mod/rm byte.  */
15286   MODRM_CHECK;
15287   codep++;
15288   used_prefixes |= (prefixes & PREFIX_DATA);
15289   oappend (names_mm[modrm.rm]);
15290 }
15291
15292 static void
15293 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15294 {
15295   used_prefixes |= (prefixes & PREFIX_DATA);
15296   oappend (names_mm[modrm.reg]);
15297 }
15298
15299 static void
15300 OP_EX (int bytemode, int sizeflag)
15301 {
15302   int reg;
15303   const char **names;
15304
15305   /* Skip mod/rm byte.  */
15306   MODRM_CHECK;
15307   codep++;
15308
15309   if (modrm.mod != 3)
15310     {
15311       OP_E_memory (bytemode, sizeflag);
15312       return;
15313     }
15314
15315   reg = modrm.rm;
15316   USED_REX (REX_B);
15317   if (rex & REX_B)
15318     reg += 8;
15319   if (vex.evex)
15320     {
15321       USED_REX (REX_X);
15322       if ((rex & REX_X))
15323         reg += 16;
15324     }
15325
15326   if ((sizeflag & SUFFIX_ALWAYS)
15327       && (bytemode == x_swap_mode
15328           || bytemode == d_swap_mode
15329           || bytemode == d_scalar_swap_mode
15330           || bytemode == q_swap_mode
15331           || bytemode == q_scalar_swap_mode))
15332     swap_operand ();
15333
15334   if (need_vex
15335       && bytemode != xmm_mode
15336       && bytemode != xmmdw_mode
15337       && bytemode != xmmqd_mode
15338       && bytemode != xmm_mb_mode
15339       && bytemode != xmm_mw_mode
15340       && bytemode != xmm_md_mode
15341       && bytemode != xmm_mq_mode
15342       && bytemode != xmm_mdq_mode
15343       && bytemode != xmmq_mode
15344       && bytemode != evex_half_bcst_xmmq_mode
15345       && bytemode != ymm_mode
15346       && bytemode != d_scalar_mode
15347       && bytemode != d_scalar_swap_mode
15348       && bytemode != q_scalar_mode
15349       && bytemode != q_scalar_swap_mode
15350       && bytemode != vex_scalar_w_dq_mode)
15351     {
15352       switch (vex.length)
15353         {
15354         case 128:
15355           names = names_xmm;
15356           break;
15357         case 256:
15358           names = names_ymm;
15359           break;
15360         case 512:
15361           names = names_zmm;
15362           break;
15363         default:
15364           abort ();
15365         }
15366     }
15367   else if (bytemode == xmmq_mode
15368            || bytemode == evex_half_bcst_xmmq_mode)
15369     {
15370       switch (vex.length)
15371         {
15372         case 128:
15373         case 256:
15374           names = names_xmm;
15375           break;
15376         case 512:
15377           names = names_ymm;
15378           break;
15379         default:
15380           abort ();
15381         }
15382     }
15383   else if (bytemode == ymm_mode)
15384     names = names_ymm;
15385   else
15386     names = names_xmm;
15387   oappend (names[reg]);
15388 }
15389
15390 static void
15391 OP_MS (int bytemode, int sizeflag)
15392 {
15393   if (modrm.mod == 3)
15394     OP_EM (bytemode, sizeflag);
15395   else
15396     BadOp ();
15397 }
15398
15399 static void
15400 OP_XS (int bytemode, int sizeflag)
15401 {
15402   if (modrm.mod == 3)
15403     OP_EX (bytemode, sizeflag);
15404   else
15405     BadOp ();
15406 }
15407
15408 static void
15409 OP_M (int bytemode, int sizeflag)
15410 {
15411   if (modrm.mod == 3)
15412     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
15413     BadOp ();
15414   else
15415     OP_E (bytemode, sizeflag);
15416 }
15417
15418 static void
15419 OP_0f07 (int bytemode, int sizeflag)
15420 {
15421   if (modrm.mod != 3 || modrm.rm != 0)
15422     BadOp ();
15423   else
15424     OP_E (bytemode, sizeflag);
15425 }
15426
15427 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
15428    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
15429
15430 static void
15431 NOP_Fixup1 (int bytemode, int sizeflag)
15432 {
15433   if ((prefixes & PREFIX_DATA) != 0
15434       || (rex != 0
15435           && rex != 0x48
15436           && address_mode == mode_64bit))
15437     OP_REG (bytemode, sizeflag);
15438   else
15439     strcpy (obuf, "nop");
15440 }
15441
15442 static void
15443 NOP_Fixup2 (int bytemode, int sizeflag)
15444 {
15445   if ((prefixes & PREFIX_DATA) != 0
15446       || (rex != 0
15447           && rex != 0x48
15448           && address_mode == mode_64bit))
15449     OP_IMREG (bytemode, sizeflag);
15450 }
15451
15452 static const char *const Suffix3DNow[] = {
15453 /* 00 */        NULL,           NULL,           NULL,           NULL,
15454 /* 04 */        NULL,           NULL,           NULL,           NULL,
15455 /* 08 */        NULL,           NULL,           NULL,           NULL,
15456 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
15457 /* 10 */        NULL,           NULL,           NULL,           NULL,
15458 /* 14 */        NULL,           NULL,           NULL,           NULL,
15459 /* 18 */        NULL,           NULL,           NULL,           NULL,
15460 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
15461 /* 20 */        NULL,           NULL,           NULL,           NULL,
15462 /* 24 */        NULL,           NULL,           NULL,           NULL,
15463 /* 28 */        NULL,           NULL,           NULL,           NULL,
15464 /* 2C */        NULL,           NULL,           NULL,           NULL,
15465 /* 30 */        NULL,           NULL,           NULL,           NULL,
15466 /* 34 */        NULL,           NULL,           NULL,           NULL,
15467 /* 38 */        NULL,           NULL,           NULL,           NULL,
15468 /* 3C */        NULL,           NULL,           NULL,           NULL,
15469 /* 40 */        NULL,           NULL,           NULL,           NULL,
15470 /* 44 */        NULL,           NULL,           NULL,           NULL,
15471 /* 48 */        NULL,           NULL,           NULL,           NULL,
15472 /* 4C */        NULL,           NULL,           NULL,           NULL,
15473 /* 50 */        NULL,           NULL,           NULL,           NULL,
15474 /* 54 */        NULL,           NULL,           NULL,           NULL,
15475 /* 58 */        NULL,           NULL,           NULL,           NULL,
15476 /* 5C */        NULL,           NULL,           NULL,           NULL,
15477 /* 60 */        NULL,           NULL,           NULL,           NULL,
15478 /* 64 */        NULL,           NULL,           NULL,           NULL,
15479 /* 68 */        NULL,           NULL,           NULL,           NULL,
15480 /* 6C */        NULL,           NULL,           NULL,           NULL,
15481 /* 70 */        NULL,           NULL,           NULL,           NULL,
15482 /* 74 */        NULL,           NULL,           NULL,           NULL,
15483 /* 78 */        NULL,           NULL,           NULL,           NULL,
15484 /* 7C */        NULL,           NULL,           NULL,           NULL,
15485 /* 80 */        NULL,           NULL,           NULL,           NULL,
15486 /* 84 */        NULL,           NULL,           NULL,           NULL,
15487 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
15488 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
15489 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
15490 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
15491 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
15492 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
15493 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
15494 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
15495 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
15496 /* AC */        NULL,           NULL,           "pfacc",        NULL,
15497 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
15498 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
15499 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
15500 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
15501 /* C0 */        NULL,           NULL,           NULL,           NULL,
15502 /* C4 */        NULL,           NULL,           NULL,           NULL,
15503 /* C8 */        NULL,           NULL,           NULL,           NULL,
15504 /* CC */        NULL,           NULL,           NULL,           NULL,
15505 /* D0 */        NULL,           NULL,           NULL,           NULL,
15506 /* D4 */        NULL,           NULL,           NULL,           NULL,
15507 /* D8 */        NULL,           NULL,           NULL,           NULL,
15508 /* DC */        NULL,           NULL,           NULL,           NULL,
15509 /* E0 */        NULL,           NULL,           NULL,           NULL,
15510 /* E4 */        NULL,           NULL,           NULL,           NULL,
15511 /* E8 */        NULL,           NULL,           NULL,           NULL,
15512 /* EC */        NULL,           NULL,           NULL,           NULL,
15513 /* F0 */        NULL,           NULL,           NULL,           NULL,
15514 /* F4 */        NULL,           NULL,           NULL,           NULL,
15515 /* F8 */        NULL,           NULL,           NULL,           NULL,
15516 /* FC */        NULL,           NULL,           NULL,           NULL,
15517 };
15518
15519 static void
15520 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15521 {
15522   const char *mnemonic;
15523
15524   FETCH_DATA (the_info, codep + 1);
15525   /* AMD 3DNow! instructions are specified by an opcode suffix in the
15526      place where an 8-bit immediate would normally go.  ie. the last
15527      byte of the instruction.  */
15528   obufp = mnemonicendp;
15529   mnemonic = Suffix3DNow[*codep++ & 0xff];
15530   if (mnemonic)
15531     oappend (mnemonic);
15532   else
15533     {
15534       /* Since a variable sized modrm/sib chunk is between the start
15535          of the opcode (0x0f0f) and the opcode suffix, we need to do
15536          all the modrm processing first, and don't know until now that
15537          we have a bad opcode.  This necessitates some cleaning up.  */
15538       op_out[0][0] = '\0';
15539       op_out[1][0] = '\0';
15540       BadOp ();
15541     }
15542   mnemonicendp = obufp;
15543 }
15544
15545 static struct op simd_cmp_op[] =
15546 {
15547   { STRING_COMMA_LEN ("eq") },
15548   { STRING_COMMA_LEN ("lt") },
15549   { STRING_COMMA_LEN ("le") },
15550   { STRING_COMMA_LEN ("unord") },
15551   { STRING_COMMA_LEN ("neq") },
15552   { STRING_COMMA_LEN ("nlt") },
15553   { STRING_COMMA_LEN ("nle") },
15554   { STRING_COMMA_LEN ("ord") }
15555 };
15556
15557 static void
15558 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15559 {
15560   unsigned int cmp_type;
15561
15562   FETCH_DATA (the_info, codep + 1);
15563   cmp_type = *codep++ & 0xff;
15564   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
15565     {
15566       char suffix [3];
15567       char *p = mnemonicendp - 2;
15568       suffix[0] = p[0];
15569       suffix[1] = p[1];
15570       suffix[2] = '\0';
15571       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
15572       mnemonicendp += simd_cmp_op[cmp_type].len;
15573     }
15574   else
15575     {
15576       /* We have a reserved extension byte.  Output it directly.  */
15577       scratchbuf[0] = '$';
15578       print_operand_value (scratchbuf + 1, 1, cmp_type);
15579       oappend_maybe_intel (scratchbuf);
15580       scratchbuf[0] = '\0';
15581     }
15582 }
15583
15584 static void
15585 OP_Mwait (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15586 {
15587   /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx  */
15588   if (!intel_syntax)
15589     {
15590       strcpy (op_out[0], names32[0]);
15591       strcpy (op_out[1], names32[1]);
15592       if (bytemode == eBX_reg)
15593         strcpy (op_out[2], names32[3]);
15594       two_source_ops = 1;
15595     }
15596   /* Skip mod/rm byte.  */
15597   MODRM_CHECK;
15598   codep++;
15599 }
15600
15601 static void
15602 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
15603             int sizeflag ATTRIBUTE_UNUSED)
15604 {
15605   /* monitor %{e,r,}ax,%ecx,%edx"  */
15606   if (!intel_syntax)
15607     {
15608       const char **names = (address_mode == mode_64bit
15609                             ? names64 : names32);
15610
15611       if (prefixes & PREFIX_ADDR)
15612         {
15613           /* Remove "addr16/addr32".  */
15614           all_prefixes[last_addr_prefix] = 0;
15615           names = (address_mode != mode_32bit
15616                    ? names32 : names16);
15617           used_prefixes |= PREFIX_ADDR;
15618         }
15619       else if (address_mode == mode_16bit)
15620         names = names16;
15621       strcpy (op_out[0], names[0]);
15622       strcpy (op_out[1], names32[1]);
15623       strcpy (op_out[2], names32[2]);
15624       two_source_ops = 1;
15625     }
15626   /* Skip mod/rm byte.  */
15627   MODRM_CHECK;
15628   codep++;
15629 }
15630
15631 static void
15632 BadOp (void)
15633 {
15634   /* Throw away prefixes and 1st. opcode byte.  */
15635   codep = insn_codep + 1;
15636   oappend ("(bad)");
15637 }
15638
15639 static void
15640 REP_Fixup (int bytemode, int sizeflag)
15641 {
15642   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
15643      lods and stos.  */
15644   if (prefixes & PREFIX_REPZ)
15645     all_prefixes[last_repz_prefix] = REP_PREFIX;
15646
15647   switch (bytemode)
15648     {
15649     case al_reg:
15650     case eAX_reg:
15651     case indir_dx_reg:
15652       OP_IMREG (bytemode, sizeflag);
15653       break;
15654     case eDI_reg:
15655       OP_ESreg (bytemode, sizeflag);
15656       break;
15657     case eSI_reg:
15658       OP_DSreg (bytemode, sizeflag);
15659       break;
15660     default:
15661       abort ();
15662       break;
15663     }
15664 }
15665
15666 static void
15667 SEP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15668 {
15669   if ( isa64 != amd64 )
15670     return;
15671
15672   obufp = obuf;
15673   BadOp ();
15674   mnemonicendp = obufp;
15675   ++codep;
15676 }
15677
15678 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
15679    "bnd".  */
15680
15681 static void
15682 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15683 {
15684   if (prefixes & PREFIX_REPNZ)
15685     all_prefixes[last_repnz_prefix] = BND_PREFIX;
15686 }
15687
15688 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
15689    "notrack".  */
15690
15691 static void
15692 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED,
15693                int sizeflag ATTRIBUTE_UNUSED)
15694 {
15695   if (active_seg_prefix == PREFIX_DS
15696       && (address_mode != mode_64bit || last_data_prefix < 0))
15697     {
15698       /* NOTRACK prefix is only valid on indirect branch instructions.
15699          NB: DATA prefix is unsupported for Intel64.  */
15700       active_seg_prefix = 0;
15701       all_prefixes[last_seg_prefix] = NOTRACK_PREFIX;
15702     }
15703 }
15704
15705 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
15706    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
15707  */
15708
15709 static void
15710 HLE_Fixup1 (int bytemode, int sizeflag)
15711 {
15712   if (modrm.mod != 3
15713       && (prefixes & PREFIX_LOCK) != 0)
15714     {
15715       if (prefixes & PREFIX_REPZ)
15716         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15717       if (prefixes & PREFIX_REPNZ)
15718         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15719     }
15720
15721   OP_E (bytemode, sizeflag);
15722 }
15723
15724 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
15725    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
15726  */
15727
15728 static void
15729 HLE_Fixup2 (int bytemode, int sizeflag)
15730 {
15731   if (modrm.mod != 3)
15732     {
15733       if (prefixes & PREFIX_REPZ)
15734         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15735       if (prefixes & PREFIX_REPNZ)
15736         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15737     }
15738
15739   OP_E (bytemode, sizeflag);
15740 }
15741
15742 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
15743    "xrelease" for memory operand.  No check for LOCK prefix.   */
15744
15745 static void
15746 HLE_Fixup3 (int bytemode, int sizeflag)
15747 {
15748   if (modrm.mod != 3
15749       && last_repz_prefix > last_repnz_prefix
15750       && (prefixes & PREFIX_REPZ) != 0)
15751     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15752
15753   OP_E (bytemode, sizeflag);
15754 }
15755
15756 static void
15757 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
15758 {
15759   USED_REX (REX_W);
15760   if (rex & REX_W)
15761     {
15762       /* Change cmpxchg8b to cmpxchg16b.  */
15763       char *p = mnemonicendp - 2;
15764       mnemonicendp = stpcpy (p, "16b");
15765       bytemode = o_mode;
15766     }
15767   else if ((prefixes & PREFIX_LOCK) != 0)
15768     {
15769       if (prefixes & PREFIX_REPZ)
15770         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15771       if (prefixes & PREFIX_REPNZ)
15772         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15773     }
15774
15775   OP_M (bytemode, sizeflag);
15776 }
15777
15778 static void
15779 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
15780 {
15781   const char **names;
15782
15783   if (need_vex)
15784     {
15785       switch (vex.length)
15786         {
15787         case 128:
15788           names = names_xmm;
15789           break;
15790         case 256:
15791           names = names_ymm;
15792           break;
15793         default:
15794           abort ();
15795         }
15796     }
15797   else
15798     names = names_xmm;
15799   oappend (names[reg]);
15800 }
15801
15802 static void
15803 CRC32_Fixup (int bytemode, int sizeflag)
15804 {
15805   /* Add proper suffix to "crc32".  */
15806   char *p = mnemonicendp;
15807
15808   switch (bytemode)
15809     {
15810     case b_mode:
15811       if (intel_syntax)
15812         goto skip;
15813
15814       *p++ = 'b';
15815       break;
15816     case v_mode:
15817       if (intel_syntax)
15818         goto skip;
15819
15820       USED_REX (REX_W);
15821       if (rex & REX_W)
15822         *p++ = 'q';
15823       else
15824         {
15825           if (sizeflag & DFLAG)
15826             *p++ = 'l';
15827           else
15828             *p++ = 'w';
15829           used_prefixes |= (prefixes & PREFIX_DATA);
15830         }
15831       break;
15832     default:
15833       oappend (INTERNAL_DISASSEMBLER_ERROR);
15834       break;
15835     }
15836   mnemonicendp = p;
15837   *p = '\0';
15838
15839 skip:
15840   if (modrm.mod == 3)
15841     {
15842       int add;
15843
15844       /* Skip mod/rm byte.  */
15845       MODRM_CHECK;
15846       codep++;
15847
15848       USED_REX (REX_B);
15849       add = (rex & REX_B) ? 8 : 0;
15850       if (bytemode == b_mode)
15851         {
15852           USED_REX (0);
15853           if (rex)
15854             oappend (names8rex[modrm.rm + add]);
15855           else
15856             oappend (names8[modrm.rm + add]);
15857         }
15858       else
15859         {
15860           USED_REX (REX_W);
15861           if (rex & REX_W)
15862             oappend (names64[modrm.rm + add]);
15863           else if ((prefixes & PREFIX_DATA))
15864             oappend (names16[modrm.rm + add]);
15865           else
15866             oappend (names32[modrm.rm + add]);
15867         }
15868     }
15869   else
15870     OP_E (bytemode, sizeflag);
15871 }
15872
15873 static void
15874 FXSAVE_Fixup (int bytemode, int sizeflag)
15875 {
15876   /* Add proper suffix to "fxsave" and "fxrstor".  */
15877   USED_REX (REX_W);
15878   if (rex & REX_W)
15879     {
15880       char *p = mnemonicendp;
15881       *p++ = '6';
15882       *p++ = '4';
15883       *p = '\0';
15884       mnemonicendp = p;
15885     }
15886   OP_M (bytemode, sizeflag);
15887 }
15888
15889 static void
15890 PCMPESTR_Fixup (int bytemode, int sizeflag)
15891 {
15892   /* Add proper suffix to "{,v}pcmpestr{i,m}".  */
15893   if (!intel_syntax)
15894     {
15895       char *p = mnemonicendp;
15896
15897       USED_REX (REX_W);
15898       if (rex & REX_W)
15899         *p++ = 'q';
15900       else if (sizeflag & SUFFIX_ALWAYS)
15901         *p++ = 'l';
15902
15903       *p = '\0';
15904       mnemonicendp = p;
15905     }
15906
15907   OP_EX (bytemode, sizeflag);
15908 }
15909
15910 /* Display the destination register operand for instructions with
15911    VEX. */
15912
15913 static void
15914 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15915 {
15916   int reg;
15917   const char **names;
15918
15919   if (!need_vex)
15920     abort ();
15921
15922   if (!need_vex_reg)
15923     return;
15924
15925   reg = vex.register_specifier;
15926   vex.register_specifier = 0;
15927   if (address_mode != mode_64bit)
15928     reg &= 7;
15929   else if (vex.evex && !vex.v)
15930     reg += 16;
15931
15932   if (bytemode == vex_scalar_mode)
15933     {
15934       oappend (names_xmm[reg]);
15935       return;
15936     }
15937
15938   switch (vex.length)
15939     {
15940     case 128:
15941       switch (bytemode)
15942         {
15943         case vex_mode:
15944         case vex128_mode:
15945         case vex_vsib_q_w_dq_mode:
15946         case vex_vsib_q_w_d_mode:
15947           names = names_xmm;
15948           break;
15949         case dq_mode:
15950           if (rex & REX_W)
15951             names = names64;
15952           else
15953             names = names32;
15954           break;
15955         case mask_bd_mode:
15956         case mask_mode:
15957           if (reg > 0x7)
15958             {
15959               oappend ("(bad)");
15960               return;
15961             }
15962           names = names_mask;
15963           break;
15964         default:
15965           abort ();
15966           return;
15967         }
15968       break;
15969     case 256:
15970       switch (bytemode)
15971         {
15972         case vex_mode:
15973         case vex256_mode:
15974           names = names_ymm;
15975           break;
15976         case vex_vsib_q_w_dq_mode:
15977         case vex_vsib_q_w_d_mode:
15978           names = vex.w ? names_ymm : names_xmm;
15979           break;
15980         case mask_bd_mode:
15981         case mask_mode:
15982           if (reg > 0x7)
15983             {
15984               oappend ("(bad)");
15985               return;
15986             }
15987           names = names_mask;
15988           break;
15989         default:
15990           /* See PR binutils/20893 for a reproducer.  */
15991           oappend ("(bad)");
15992           return;
15993         }
15994       break;
15995     case 512:
15996       names = names_zmm;
15997       break;
15998     default:
15999       abort ();
16000       break;
16001     }
16002   oappend (names[reg]);
16003 }
16004
16005 /* Get the VEX immediate byte without moving codep.  */
16006
16007 static unsigned char
16008 get_vex_imm8 (int sizeflag, int opnum)
16009 {
16010   int bytes_before_imm = 0;
16011
16012   if (modrm.mod != 3)
16013     {
16014       /* There are SIB/displacement bytes.  */
16015       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
16016         {
16017           /* 32/64 bit address mode */
16018           int base = modrm.rm;
16019
16020           /* Check SIB byte.  */
16021           if (base == 4)
16022             {
16023               FETCH_DATA (the_info, codep + 1);
16024               base = *codep & 7;
16025               /* When decoding the third source, don't increase
16026                  bytes_before_imm as this has already been incremented
16027                  by one in OP_E_memory while decoding the second
16028                  source operand.  */
16029               if (opnum == 0)
16030                 bytes_before_imm++;
16031             }
16032
16033           /* Don't increase bytes_before_imm when decoding the third source,
16034              it has already been incremented by OP_E_memory while decoding
16035              the second source operand.  */
16036           if (opnum == 0)
16037             {
16038               switch (modrm.mod)
16039                 {
16040                   case 0:
16041                     /* When modrm.rm == 5 or modrm.rm == 4 and base in
16042                        SIB == 5, there is a 4 byte displacement.  */
16043                     if (base != 5)
16044                       /* No displacement. */
16045                       break;
16046                     /* Fall through.  */
16047                   case 2:
16048                     /* 4 byte displacement.  */
16049                     bytes_before_imm += 4;
16050                     break;
16051                   case 1:
16052                     /* 1 byte displacement.  */
16053                     bytes_before_imm++;
16054                     break;
16055                 }
16056             }
16057         }
16058       else
16059         {
16060           /* 16 bit address mode */
16061           /* Don't increase bytes_before_imm when decoding the third source,
16062              it has already been incremented by OP_E_memory while decoding
16063              the second source operand.  */
16064           if (opnum == 0)
16065             {
16066               switch (modrm.mod)
16067                 {
16068                 case 0:
16069                   /* When modrm.rm == 6, there is a 2 byte displacement.  */
16070                   if (modrm.rm != 6)
16071                     /* No displacement. */
16072                     break;
16073                   /* Fall through.  */
16074                 case 2:
16075                   /* 2 byte displacement.  */
16076                   bytes_before_imm += 2;
16077                   break;
16078                 case 1:
16079                   /* 1 byte displacement: when decoding the third source,
16080                      don't increase bytes_before_imm as this has already
16081                      been incremented by one in OP_E_memory while decoding
16082                      the second source operand.  */
16083                   if (opnum == 0)
16084                     bytes_before_imm++;
16085
16086                   break;
16087                 }
16088             }
16089         }
16090     }
16091
16092   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
16093   return codep [bytes_before_imm];
16094 }
16095
16096 static void
16097 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
16098 {
16099   const char **names;
16100
16101   if (reg == -1 && modrm.mod != 3)
16102     {
16103       OP_E_memory (bytemode, sizeflag);
16104       return;
16105     }
16106   else
16107     {
16108       if (reg == -1)
16109         {
16110           reg = modrm.rm;
16111           USED_REX (REX_B);
16112           if (rex & REX_B)
16113             reg += 8;
16114         }
16115       if (address_mode != mode_64bit)
16116         reg &= 7;
16117     }
16118
16119   switch (vex.length)
16120     {
16121     case 128:
16122       names = names_xmm;
16123       break;
16124     case 256:
16125       names = names_ymm;
16126       break;
16127     default:
16128       abort ();
16129     }
16130   oappend (names[reg]);
16131 }
16132
16133 static void
16134 OP_EX_VexImmW (int bytemode, int sizeflag)
16135 {
16136   int reg = -1;
16137   static unsigned char vex_imm8;
16138
16139   if (vex_w_done == 0)
16140     {
16141       vex_w_done = 1;
16142
16143       /* Skip mod/rm byte.  */
16144       MODRM_CHECK;
16145       codep++;
16146
16147       vex_imm8 = get_vex_imm8 (sizeflag, 0);
16148
16149       if (vex.w)
16150           reg = vex_imm8 >> 4;
16151
16152       OP_EX_VexReg (bytemode, sizeflag, reg);
16153     }
16154   else if (vex_w_done == 1)
16155     {
16156       vex_w_done = 2;
16157
16158       if (!vex.w)
16159           reg = vex_imm8 >> 4;
16160
16161       OP_EX_VexReg (bytemode, sizeflag, reg);
16162     }
16163   else
16164     {
16165       /* Output the imm8 directly.  */
16166       scratchbuf[0] = '$';
16167       print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
16168       oappend_maybe_intel (scratchbuf);
16169       scratchbuf[0] = '\0';
16170       codep++;
16171     }
16172 }
16173
16174 static void
16175 OP_Vex_2src (int bytemode, int sizeflag)
16176 {
16177   if (modrm.mod == 3)
16178     {
16179       int reg = modrm.rm;
16180       USED_REX (REX_B);
16181       if (rex & REX_B)
16182         reg += 8;
16183       oappend (names_xmm[reg]);
16184     }
16185   else
16186     {
16187       if (intel_syntax
16188           && (bytemode == v_mode || bytemode == v_swap_mode))
16189         {
16190           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16191           used_prefixes |= (prefixes & PREFIX_DATA);
16192         }
16193       OP_E (bytemode, sizeflag);
16194     }
16195 }
16196
16197 static void
16198 OP_Vex_2src_1 (int bytemode, int sizeflag)
16199 {
16200   if (modrm.mod == 3)
16201     {
16202       /* Skip mod/rm byte.   */
16203       MODRM_CHECK;
16204       codep++;
16205     }
16206
16207   if (vex.w)
16208     {
16209       unsigned int reg = vex.register_specifier;
16210       vex.register_specifier = 0;
16211
16212       if (address_mode != mode_64bit)
16213         reg &= 7;
16214       oappend (names_xmm[reg]);
16215     }
16216   else
16217     OP_Vex_2src (bytemode, sizeflag);
16218 }
16219
16220 static void
16221 OP_Vex_2src_2 (int bytemode, int sizeflag)
16222 {
16223   if (vex.w)
16224     OP_Vex_2src (bytemode, sizeflag);
16225   else
16226     {
16227       unsigned int reg = vex.register_specifier;
16228       vex.register_specifier = 0;
16229
16230       if (address_mode != mode_64bit)
16231         reg &= 7;
16232       oappend (names_xmm[reg]);
16233     }
16234 }
16235
16236 static void
16237 OP_EX_VexW (int bytemode, int sizeflag)
16238 {
16239   int reg = -1;
16240
16241   if (!vex_w_done)
16242     {
16243       /* Skip mod/rm byte.  */
16244       MODRM_CHECK;
16245       codep++;
16246
16247       if (vex.w)
16248         reg = get_vex_imm8 (sizeflag, 0) >> 4;
16249     }
16250   else
16251     {
16252       if (!vex.w)
16253         reg = get_vex_imm8 (sizeflag, 1) >> 4;
16254     }
16255
16256   OP_EX_VexReg (bytemode, sizeflag, reg);
16257
16258   if (vex_w_done)
16259     codep++;
16260   vex_w_done = 1;
16261 }
16262
16263 static void
16264 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16265 {
16266   int reg;
16267   const char **names;
16268
16269   FETCH_DATA (the_info, codep + 1);
16270   reg = *codep++;
16271
16272   if (bytemode != x_mode)
16273     abort ();
16274
16275   reg >>= 4;
16276   if (address_mode != mode_64bit)
16277     reg &= 7;
16278
16279   switch (vex.length)
16280     {
16281     case 128:
16282       names = names_xmm;
16283       break;
16284     case 256:
16285       names = names_ymm;
16286       break;
16287     default:
16288       abort ();
16289     }
16290   oappend (names[reg]);
16291 }
16292
16293 static void
16294 OP_XMM_VexW (int bytemode, int sizeflag)
16295 {
16296   /* Turn off the REX.W bit since it is used for swapping operands
16297      now.  */
16298   rex &= ~REX_W;
16299   OP_XMM (bytemode, sizeflag);
16300 }
16301
16302 static void
16303 OP_EX_Vex (int bytemode, int sizeflag)
16304 {
16305   if (modrm.mod != 3)
16306     need_vex_reg = 0;
16307   OP_EX (bytemode, sizeflag);
16308 }
16309
16310 static void
16311 OP_XMM_Vex (int bytemode, int sizeflag)
16312 {
16313   if (modrm.mod != 3)
16314     need_vex_reg = 0;
16315   OP_XMM (bytemode, sizeflag);
16316 }
16317
16318 static struct op vex_cmp_op[] =
16319 {
16320   { STRING_COMMA_LEN ("eq") },
16321   { STRING_COMMA_LEN ("lt") },
16322   { STRING_COMMA_LEN ("le") },
16323   { STRING_COMMA_LEN ("unord") },
16324   { STRING_COMMA_LEN ("neq") },
16325   { STRING_COMMA_LEN ("nlt") },
16326   { STRING_COMMA_LEN ("nle") },
16327   { STRING_COMMA_LEN ("ord") },
16328   { STRING_COMMA_LEN ("eq_uq") },
16329   { STRING_COMMA_LEN ("nge") },
16330   { STRING_COMMA_LEN ("ngt") },
16331   { STRING_COMMA_LEN ("false") },
16332   { STRING_COMMA_LEN ("neq_oq") },
16333   { STRING_COMMA_LEN ("ge") },
16334   { STRING_COMMA_LEN ("gt") },
16335   { STRING_COMMA_LEN ("true") },
16336   { STRING_COMMA_LEN ("eq_os") },
16337   { STRING_COMMA_LEN ("lt_oq") },
16338   { STRING_COMMA_LEN ("le_oq") },
16339   { STRING_COMMA_LEN ("unord_s") },
16340   { STRING_COMMA_LEN ("neq_us") },
16341   { STRING_COMMA_LEN ("nlt_uq") },
16342   { STRING_COMMA_LEN ("nle_uq") },
16343   { STRING_COMMA_LEN ("ord_s") },
16344   { STRING_COMMA_LEN ("eq_us") },
16345   { STRING_COMMA_LEN ("nge_uq") },
16346   { STRING_COMMA_LEN ("ngt_uq") },
16347   { STRING_COMMA_LEN ("false_os") },
16348   { STRING_COMMA_LEN ("neq_os") },
16349   { STRING_COMMA_LEN ("ge_oq") },
16350   { STRING_COMMA_LEN ("gt_oq") },
16351   { STRING_COMMA_LEN ("true_us") },
16352 };
16353
16354 static void
16355 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16356 {
16357   unsigned int cmp_type;
16358
16359   FETCH_DATA (the_info, codep + 1);
16360   cmp_type = *codep++ & 0xff;
16361   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
16362     {
16363       char suffix [3];
16364       char *p = mnemonicendp - 2;
16365       suffix[0] = p[0];
16366       suffix[1] = p[1];
16367       suffix[2] = '\0';
16368       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
16369       mnemonicendp += vex_cmp_op[cmp_type].len;
16370     }
16371   else
16372     {
16373       /* We have a reserved extension byte.  Output it directly.  */
16374       scratchbuf[0] = '$';
16375       print_operand_value (scratchbuf + 1, 1, cmp_type);
16376       oappend_maybe_intel (scratchbuf);
16377       scratchbuf[0] = '\0';
16378     }
16379 }
16380
16381 static void
16382 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
16383              int sizeflag ATTRIBUTE_UNUSED)
16384 {
16385   unsigned int cmp_type;
16386
16387   if (!vex.evex)
16388     abort ();
16389
16390   FETCH_DATA (the_info, codep + 1);
16391   cmp_type = *codep++ & 0xff;
16392   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
16393      If it's the case, print suffix, otherwise - print the immediate.  */
16394   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
16395       && cmp_type != 3
16396       && cmp_type != 7)
16397     {
16398       char suffix [3];
16399       char *p = mnemonicendp - 2;
16400
16401       /* vpcmp* can have both one- and two-lettered suffix.  */
16402       if (p[0] == 'p')
16403         {
16404           p++;
16405           suffix[0] = p[0];
16406           suffix[1] = '\0';
16407         }
16408       else
16409         {
16410           suffix[0] = p[0];
16411           suffix[1] = p[1];
16412           suffix[2] = '\0';
16413         }
16414
16415       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16416       mnemonicendp += simd_cmp_op[cmp_type].len;
16417     }
16418   else
16419     {
16420       /* We have a reserved extension byte.  Output it directly.  */
16421       scratchbuf[0] = '$';
16422       print_operand_value (scratchbuf + 1, 1, cmp_type);
16423       oappend_maybe_intel (scratchbuf);
16424       scratchbuf[0] = '\0';
16425     }
16426 }
16427
16428 static const struct op xop_cmp_op[] =
16429 {
16430   { STRING_COMMA_LEN ("lt") },
16431   { STRING_COMMA_LEN ("le") },
16432   { STRING_COMMA_LEN ("gt") },
16433   { STRING_COMMA_LEN ("ge") },
16434   { STRING_COMMA_LEN ("eq") },
16435   { STRING_COMMA_LEN ("neq") },
16436   { STRING_COMMA_LEN ("false") },
16437   { STRING_COMMA_LEN ("true") }
16438 };
16439
16440 static void
16441 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED,
16442              int sizeflag ATTRIBUTE_UNUSED)
16443 {
16444   unsigned int cmp_type;
16445
16446   FETCH_DATA (the_info, codep + 1);
16447   cmp_type = *codep++ & 0xff;
16448   if (cmp_type < ARRAY_SIZE (xop_cmp_op))
16449     {
16450       char suffix[3];
16451       char *p = mnemonicendp - 2;
16452
16453       /* vpcom* can have both one- and two-lettered suffix.  */
16454       if (p[0] == 'm')
16455         {
16456           p++;
16457           suffix[0] = p[0];
16458           suffix[1] = '\0';
16459         }
16460       else
16461         {
16462           suffix[0] = p[0];
16463           suffix[1] = p[1];
16464           suffix[2] = '\0';
16465         }
16466
16467       sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix);
16468       mnemonicendp += xop_cmp_op[cmp_type].len;
16469     }
16470   else
16471     {
16472       /* We have a reserved extension byte.  Output it directly.  */
16473       scratchbuf[0] = '$';
16474       print_operand_value (scratchbuf + 1, 1, cmp_type);
16475       oappend_maybe_intel (scratchbuf);
16476       scratchbuf[0] = '\0';
16477     }
16478 }
16479
16480 static const struct op pclmul_op[] =
16481 {
16482   { STRING_COMMA_LEN ("lql") },
16483   { STRING_COMMA_LEN ("hql") },
16484   { STRING_COMMA_LEN ("lqh") },
16485   { STRING_COMMA_LEN ("hqh") }
16486 };
16487
16488 static void
16489 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
16490               int sizeflag ATTRIBUTE_UNUSED)
16491 {
16492   unsigned int pclmul_type;
16493
16494   FETCH_DATA (the_info, codep + 1);
16495   pclmul_type = *codep++ & 0xff;
16496   switch (pclmul_type)
16497     {
16498     case 0x10:
16499       pclmul_type = 2;
16500       break;
16501     case 0x11:
16502       pclmul_type = 3;
16503       break;
16504     default:
16505       break;
16506     }
16507   if (pclmul_type < ARRAY_SIZE (pclmul_op))
16508     {
16509       char suffix [4];
16510       char *p = mnemonicendp - 3;
16511       suffix[0] = p[0];
16512       suffix[1] = p[1];
16513       suffix[2] = p[2];
16514       suffix[3] = '\0';
16515       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
16516       mnemonicendp += pclmul_op[pclmul_type].len;
16517     }
16518   else
16519     {
16520       /* We have a reserved extension byte.  Output it directly.  */
16521       scratchbuf[0] = '$';
16522       print_operand_value (scratchbuf + 1, 1, pclmul_type);
16523       oappend_maybe_intel (scratchbuf);
16524       scratchbuf[0] = '\0';
16525     }
16526 }
16527
16528 static void
16529 MOVBE_Fixup (int bytemode, int sizeflag)
16530 {
16531   /* Add proper suffix to "movbe".  */
16532   char *p = mnemonicendp;
16533
16534   switch (bytemode)
16535     {
16536     case v_mode:
16537       if (intel_syntax)
16538         goto skip;
16539
16540       USED_REX (REX_W);
16541       if (sizeflag & SUFFIX_ALWAYS)
16542         {
16543           if (rex & REX_W)
16544             *p++ = 'q';
16545           else
16546             {
16547               if (sizeflag & DFLAG)
16548                 *p++ = 'l';
16549               else
16550                 *p++ = 'w';
16551               used_prefixes |= (prefixes & PREFIX_DATA);
16552             }
16553         }
16554       break;
16555     default:
16556       oappend (INTERNAL_DISASSEMBLER_ERROR);
16557       break;
16558     }
16559   mnemonicendp = p;
16560   *p = '\0';
16561
16562 skip:
16563   OP_M (bytemode, sizeflag);
16564 }
16565
16566 static void
16567 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16568 {
16569   int reg;
16570   const char **names;
16571
16572   /* Skip mod/rm byte.  */
16573   MODRM_CHECK;
16574   codep++;
16575
16576   if (rex & REX_W)
16577     names = names64;
16578   else
16579     names = names32;
16580
16581   reg = modrm.rm;
16582   USED_REX (REX_B);
16583   if (rex & REX_B)
16584     reg += 8;
16585
16586   oappend (names[reg]);
16587 }
16588
16589 static void
16590 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16591 {
16592   const char **names;
16593   unsigned int reg = vex.register_specifier;
16594   vex.register_specifier = 0;
16595
16596   if (rex & REX_W)
16597     names = names64;
16598   else
16599     names = names32;
16600
16601   if (address_mode != mode_64bit)
16602     reg &= 7;
16603   oappend (names[reg]);
16604 }
16605
16606 static void
16607 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16608 {
16609   if (!vex.evex
16610       || (bytemode != mask_mode && bytemode != mask_bd_mode))
16611     abort ();
16612
16613   USED_REX (REX_R);
16614   if ((rex & REX_R) != 0 || !vex.r)
16615     {
16616       BadOp ();
16617       return;
16618     }
16619
16620   oappend (names_mask [modrm.reg]);
16621 }
16622
16623 static void
16624 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16625 {
16626   if (!vex.evex
16627       || (bytemode != evex_rounding_mode
16628           && bytemode != evex_rounding_64_mode
16629           && bytemode != evex_sae_mode))
16630     abort ();
16631   if (modrm.mod == 3 && vex.b)
16632     switch (bytemode)
16633       {
16634       case evex_rounding_64_mode:
16635         if (address_mode != mode_64bit)
16636           {
16637             oappend ("(bad)");
16638             break;
16639           }
16640         /* Fall through.  */
16641       case evex_rounding_mode:
16642         oappend (names_rounding[vex.ll]);
16643         break;
16644       case evex_sae_mode:
16645         oappend ("{sae}");
16646         break;
16647       default:
16648         break;
16649       }
16650 }