opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2015 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "dis-asm.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40
  41 #include <setjmp.h>
  42
  43 static int print_insn (bfd_vma, disassemble_info *);
  44 static void dofloat (int);
  45 static void OP_ST (int, int);
  46 static void OP_STi (int, int);
  47 static int putop (const char *, int);
  48 static void oappend (const char *);
  49 static void append_seg (void);
  50 static void OP_indirE (int, int);
  51 static void print_operand_value (char *, int, bfd_vma);
  52 static void OP_E_register (int, int);
  53 static void OP_E_memory (int, int);
  54 static void print_displacement (char *, bfd_vma);
  55 static void OP_E (int, int);
  56 static void OP_G (int, int);
  57 static bfd_vma get64 (void);
  58 static bfd_signed_vma get32 (void);
  59 static bfd_signed_vma get32s (void);
  60 static int get16 (void);
  61 static void set_op (bfd_vma, int);
  62 static void OP_Skip_MODRM (int, int);
  63 static void OP_REG (int, int);
  64 static void OP_IMREG (int, int);
  65 static void OP_I (int, int);
  66 static void OP_I64 (int, int);
  67 static void OP_sI (int, int);
  68 static void OP_J (int, int);
  69 static void OP_SEG (int, int);
  70 static void OP_DIR (int, int);
  71 static void OP_OFF (int, int);
  72 static void OP_OFF64 (int, int);
  73 static void ptr_reg (int, int);
  74 static void OP_ESreg (int, int);
  75 static void OP_DSreg (int, int);
  76 static void OP_C (int, int);
  77 static void OP_D (int, int);
  78 static void OP_T (int, int);
  79 static void OP_R (int, int);
  80 static void OP_MMX (int, int);
  81 static void OP_XMM (int, int);
  82 static void OP_EM (int, int);
  83 static void OP_EX (int, int);
  84 static void OP_EMC (int,int);
  85 static void OP_MXC (int,int);
  86 static void OP_MS (int, int);
  87 static void OP_XS (int, int);
  88 static void OP_M (int, int);
  89 static void OP_VEX (int, int);
  90 static void OP_EX_Vex (int, int);
  91 static void OP_EX_VexW (int, int);
  92 static void OP_EX_VexImmW (int, int);
  93 static void OP_XMM_Vex (int, int);
  94 static void OP_XMM_VexW (int, int);
  95 static void OP_Rounding (int, int);
  96 static void OP_REG_VexI4 (int, int);
  97 static void PCLMUL_Fixup (int, int);
  98 static void VEXI4_Fixup (int, int);
  99 static void VZERO_Fixup (int, int);
 100 static void VCMP_Fixup (int, int);
 101 static void VPCMP_Fixup (int, int);
 102 static void OP_0f07 (int, int);
 103 static void OP_Monitor (int, int);
 104 static void OP_Mwait (int, int);
 105 static void NOP_Fixup1 (int, int);
 106 static void NOP_Fixup2 (int, int);
 107 static void OP_3DNowSuffix (int, int);
 108 static void CMP_Fixup (int, int);
 109 static void BadOp (void);
 110 static void REP_Fixup (int, int);
 111 static void BND_Fixup (int, int);
 112 static void HLE_Fixup1 (int, int);
 113 static void HLE_Fixup2 (int, int);
 114 static void HLE_Fixup3 (int, int);
 115 static void CMPXCHG8B_Fixup (int, int);
 116 static void XMM_Fixup (int, int);
 117 static void CRC32_Fixup (int, int);
 118 static void FXSAVE_Fixup (int, int);
 119 static void OP_LWPCB_E (int, int);
 120 static void OP_LWP_E (int, int);
 121 static void OP_Vex_2src_1 (int, int);
 122 static void OP_Vex_2src_2 (int, int);
 123
 124 static void MOVBE_Fixup (int, int);
 125
 126 static void OP_Mask (int, int);
 127
 128 struct dis_private {
 129   /* Points to first byte not fetched.  */
 130   bfd_byte *max_fetched;
 131   bfd_byte the_buffer[MAX_MNEM_SIZE];
 132   bfd_vma insn_start;
 133   int orig_sizeflag;
 134   OPCODES_SIGJMP_BUF bailout;
 135 };
 136
 137 enum address_mode
 138 {
 139   mode_16bit,
 140   mode_32bit,
 141   mode_64bit
 142 };
 143
 144 enum address_mode address_mode;
 145
 146 /* Flags for the prefixes for the current instruction.  See below.  */
 147 static int prefixes;
 148
 149 /* REX prefix the current instruction.  See below.  */
 150 static int rex;
 151 /* Bits of REX we've already used.  */
 152 static int rex_used;
 153 /* REX bits in original REX prefix ignored.  */
 154 static int rex_ignored;
 155 /* Mark parts used in the REX prefix.  When we are testing for
 156    empty prefix (for 8bit register REX extension), just mask it
 157    out.  Otherwise test for REX bit is excuse for existence of REX
 158    only in case value is nonzero.  */
 159 #define USED_REX(value)                                 \
 160   {                                                     \
 161     if (value)                                          \
 162       {                                                 \
 163         if ((rex & value))                              \
 164           rex_used |= (value) | REX_OPCODE;             \
 165       }                                                 \
 166     else                                                \
 167       rex_used |= REX_OPCODE;                           \
 168   }
 169
 170 /* Flags for prefixes which we somehow handled when printing the
 171    current instruction.  */
 172 static int used_prefixes;
 173
 174 /* Flags stored in PREFIXES.  */
 175 #define PREFIX_REPZ 1
 176 #define PREFIX_REPNZ 2
 177 #define PREFIX_LOCK 4
 178 #define PREFIX_CS 8
 179 #define PREFIX_SS 0x10
 180 #define PREFIX_DS 0x20
 181 #define PREFIX_ES 0x40
 182 #define PREFIX_FS 0x80
 183 #define PREFIX_GS 0x100
 184 #define PREFIX_DATA 0x200
 185 #define PREFIX_ADDR 0x400
 186 #define PREFIX_FWAIT 0x800
 187
 188 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 189    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 190    on error.  */
 191 #define FETCH_DATA(info, addr) \
 192   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 193    ? 1 : fetch_data ((info), (addr)))
 194
 195 static int
 196 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 197 {
 198   int status;
 199   struct dis_private *priv = (struct dis_private *) info->private_data;
 200   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 201
 202   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 203     status = (*info->read_memory_func) (start,
 204                                         priv->max_fetched,
 205                                         addr - priv->max_fetched,
 206                                         info);
 207   else
 208     status = -1;
 209   if (status != 0)
 210     {
 211       /* If we did manage to read at least one byte, then
 212          print_insn_i386 will do something sensible.  Otherwise, print
 213          an error.  We do that here because this is where we know
 214          STATUS.  */
 215       if (priv->max_fetched == priv->the_buffer)
 216         (*info->memory_error_func) (status, start, info);
 217       OPCODES_SIGLONGJMP (priv->bailout, 1);
 218     }
 219   else
 220     priv->max_fetched = addr;
 221   return 1;
 222 }
 223
 224 /* Possible values for prefix requirement.  */
 225 #define PREFIX_UD_SHIFT         8
 226 #define PREFIX_UD_REPZ          (PREFIX_REPZ << PREFIX_UD_SHIFT)
 227 #define PREFIX_UD_REPNZ         (PREFIX_REPNZ << PREFIX_UD_SHIFT)
 228 #define PREFIX_UD_DATA          (PREFIX_DATA << PREFIX_UD_SHIFT)
 229 #define PREFIX_UD_ADDR          (PREFIX_ADDR << PREFIX_UD_SHIFT)
 230 #define PREFIX_UD_LOCK          (PREFIX_LOCK << PREFIX_UD_SHIFT)
 231 #define PREFIX_IGNORED_SHIFT    16
 232 #define PREFIX_IGNORED_REPZ     (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
 233 #define PREFIX_IGNORED_REPNZ    (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
 234 #define PREFIX_IGNORED_DATA     (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
 235 #define PREFIX_IGNORED_ADDR     (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
 236 #define PREFIX_IGNORED_LOCK     (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
 237
 238 /* Opcode prefixes.  */
 239 #define PREFIX_OPCODE           (PREFIX_REPZ \
 240                                  | PREFIX_REPNZ \
 241                                  | PREFIX_DATA)
 242
 243 /* Prefixes ignored.  */
 244 #define PREFIX_IGNORED          (PREFIX_IGNORED_REPZ \
 245                                  | PREFIX_IGNORED_REPNZ \
 246                                  | PREFIX_IGNORED_DATA)
 247
 248 #define XX { NULL, 0 }
 249 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
 250
 251 #define Eb { OP_E, b_mode }
 252 #define Ebnd { OP_E, bnd_mode }
 253 #define EbS { OP_E, b_swap_mode }
 254 #define Ev { OP_E, v_mode }
 255 #define Ev_bnd { OP_E, v_bnd_mode }
 256 #define EvS { OP_E, v_swap_mode }
 257 #define Ed { OP_E, d_mode }
 258 #define Edq { OP_E, dq_mode }
 259 #define Edqw { OP_E, dqw_mode }
 260 #define EdqwS { OP_E, dqw_swap_mode }
 261 #define Edqb { OP_E, dqb_mode }
 262 #define Edb { OP_E, db_mode }
 263 #define Edw { OP_E, dw_mode }
 264 #define Edqd { OP_E, dqd_mode }
 265 #define Eq { OP_E, q_mode }
 266 #define indirEv { OP_indirE, stack_v_mode }
 267 #define indirEp { OP_indirE, f_mode }
 268 #define stackEv { OP_E, stack_v_mode }
 269 #define Em { OP_E, m_mode }
 270 #define Ew { OP_E, w_mode }
 271 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 272 #define Ma { OP_M, a_mode }
 273 #define Mb { OP_M, b_mode }
 274 #define Md { OP_M, d_mode }
 275 #define Mo { OP_M, o_mode }
 276 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 277 #define Mq { OP_M, q_mode }
 278 #define Mx { OP_M, x_mode }
 279 #define Mxmm { OP_M, xmm_mode }
 280 #define Gb { OP_G, b_mode }
 281 #define Gbnd { OP_G, bnd_mode }
 282 #define Gv { OP_G, v_mode }
 283 #define Gd { OP_G, d_mode }
 284 #define Gdq { OP_G, dq_mode }
 285 #define Gm { OP_G, m_mode }
 286 #define Gw { OP_G, w_mode }
 287 #define Rd { OP_R, d_mode }
 288 #define Rdq { OP_R, dq_mode }
 289 #define Rm { OP_R, m_mode }
 290 #define Ib { OP_I, b_mode }
 291 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 292 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 293 #define Iv { OP_I, v_mode }
 294 #define sIv { OP_sI, v_mode }
 295 #define Iq { OP_I, q_mode }
 296 #define Iv64 { OP_I64, v_mode }
 297 #define Iw { OP_I, w_mode }
 298 #define I1 { OP_I, const_1_mode }
 299 #define Jb { OP_J, b_mode }
 300 #define Jv { OP_J, v_mode }
 301 #define Cm { OP_C, m_mode }
 302 #define Dm { OP_D, m_mode }
 303 #define Td { OP_T, d_mode }
 304 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 305
 306 #define RMeAX { OP_REG, eAX_reg }
 307 #define RMeBX { OP_REG, eBX_reg }
 308 #define RMeCX { OP_REG, eCX_reg }
 309 #define RMeDX { OP_REG, eDX_reg }
 310 #define RMeSP { OP_REG, eSP_reg }
 311 #define RMeBP { OP_REG, eBP_reg }
 312 #define RMeSI { OP_REG, eSI_reg }
 313 #define RMeDI { OP_REG, eDI_reg }
 314 #define RMrAX { OP_REG, rAX_reg }
 315 #define RMrBX { OP_REG, rBX_reg }
 316 #define RMrCX { OP_REG, rCX_reg }
 317 #define RMrDX { OP_REG, rDX_reg }
 318 #define RMrSP { OP_REG, rSP_reg }
 319 #define RMrBP { OP_REG, rBP_reg }
 320 #define RMrSI { OP_REG, rSI_reg }
 321 #define RMrDI { OP_REG, rDI_reg }
 322 #define RMAL { OP_REG, al_reg }
 323 #define RMCL { OP_REG, cl_reg }
 324 #define RMDL { OP_REG, dl_reg }
 325 #define RMBL { OP_REG, bl_reg }
 326 #define RMAH { OP_REG, ah_reg }
 327 #define RMCH { OP_REG, ch_reg }
 328 #define RMDH { OP_REG, dh_reg }
 329 #define RMBH { OP_REG, bh_reg }
 330 #define RMAX { OP_REG, ax_reg }
 331 #define RMDX { OP_REG, dx_reg }
 332
 333 #define eAX { OP_IMREG, eAX_reg }
 334 #define eBX { OP_IMREG, eBX_reg }
 335 #define eCX { OP_IMREG, eCX_reg }
 336 #define eDX { OP_IMREG, eDX_reg }
 337 #define eSP { OP_IMREG, eSP_reg }
 338 #define eBP { OP_IMREG, eBP_reg }
 339 #define eSI { OP_IMREG, eSI_reg }
 340 #define eDI { OP_IMREG, eDI_reg }
 341 #define AL { OP_IMREG, al_reg }
 342 #define CL { OP_IMREG, cl_reg }
 343 #define DL { OP_IMREG, dl_reg }
 344 #define BL { OP_IMREG, bl_reg }
 345 #define AH { OP_IMREG, ah_reg }
 346 #define CH { OP_IMREG, ch_reg }
 347 #define DH { OP_IMREG, dh_reg }
 348 #define BH { OP_IMREG, bh_reg }
 349 #define AX { OP_IMREG, ax_reg }
 350 #define DX { OP_IMREG, dx_reg }
 351 #define zAX { OP_IMREG, z_mode_ax_reg }
 352 #define indirDX { OP_IMREG, indir_dx_reg }
 353
 354 #define Sw { OP_SEG, w_mode }
 355 #define Sv { OP_SEG, v_mode }
 356 #define Ap { OP_DIR, 0 }
 357 #define Ob { OP_OFF64, b_mode }
 358 #define Ov { OP_OFF64, v_mode }
 359 #define Xb { OP_DSreg, eSI_reg }
 360 #define Xv { OP_DSreg, eSI_reg }
 361 #define Xz { OP_DSreg, eSI_reg }
 362 #define Yb { OP_ESreg, eDI_reg }
 363 #define Yv { OP_ESreg, eDI_reg }
 364 #define DSBX { OP_DSreg, eBX_reg }
 365
 366 #define es { OP_REG, es_reg }
 367 #define ss { OP_REG, ss_reg }
 368 #define cs { OP_REG, cs_reg }
 369 #define ds { OP_REG, ds_reg }
 370 #define fs { OP_REG, fs_reg }
 371 #define gs { OP_REG, gs_reg }
 372
 373 #define MX { OP_MMX, 0 }
 374 #define XM { OP_XMM, 0 }
 375 #define XMScalar { OP_XMM, scalar_mode }
 376 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 377 #define XMM { OP_XMM, xmm_mode }
 378 #define XMxmmq { OP_XMM, xmmq_mode }
 379 #define EM { OP_EM, v_mode }
 380 #define EMS { OP_EM, v_swap_mode }
 381 #define EMd { OP_EM, d_mode }
 382 #define EMx { OP_EM, x_mode }
 383 #define EXw { OP_EX, w_mode }
 384 #define EXd { OP_EX, d_mode }
 385 #define EXdScalar { OP_EX, d_scalar_mode }
 386 #define EXdS { OP_EX, d_swap_mode }
 387 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
 388 #define EXq { OP_EX, q_mode }
 389 #define EXqScalar { OP_EX, q_scalar_mode }
 390 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
 391 #define EXqS { OP_EX, q_swap_mode }
 392 #define EXx { OP_EX, x_mode }
 393 #define EXxS { OP_EX, x_swap_mode }
 394 #define EXxmm { OP_EX, xmm_mode }
 395 #define EXymm { OP_EX, ymm_mode }
 396 #define EXxmmq { OP_EX, xmmq_mode }
 397 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 398 #define EXxmm_mb { OP_EX, xmm_mb_mode }
 399 #define EXxmm_mw { OP_EX, xmm_mw_mode }
 400 #define EXxmm_md { OP_EX, xmm_md_mode }
 401 #define EXxmm_mq { OP_EX, xmm_mq_mode }
 402 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
 403 #define EXxmmdw { OP_EX, xmmdw_mode }
 404 #define EXxmmqd { OP_EX, xmmqd_mode }
 405 #define EXymmq { OP_EX, ymmq_mode }
 406 #define EXVexWdq { OP_EX, vex_w_dq_mode }
 407 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 408 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 409 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 410 #define MS { OP_MS, v_mode }
 411 #define XS { OP_XS, v_mode }
 412 #define EMCq { OP_EMC, q_mode }
 413 #define MXC { OP_MXC, 0 }
 414 #define OPSUF { OP_3DNowSuffix, 0 }
 415 #define CMP { CMP_Fixup, 0 }
 416 #define XMM0 { XMM_Fixup, 0 }
 417 #define FXSAVE { FXSAVE_Fixup, 0 }
 418 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
 419 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
 420
 421 #define Vex { OP_VEX, vex_mode }
 422 #define VexScalar { OP_VEX, vex_scalar_mode }
 423 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 424 #define Vex128 { OP_VEX, vex128_mode }
 425 #define Vex256 { OP_VEX, vex256_mode }
 426 #define VexGdq { OP_VEX, dq_mode }
 427 #define VexI4 { VEXI4_Fixup, 0}
 428 #define EXdVex { OP_EX_Vex, d_mode }
 429 #define EXdVexS { OP_EX_Vex, d_swap_mode }
 430 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
 431 #define EXqVex { OP_EX_Vex, q_mode }
 432 #define EXqVexS { OP_EX_Vex, q_swap_mode }
 433 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
 434 #define EXVexW { OP_EX_VexW, x_mode }
 435 #define EXdVexW { OP_EX_VexW, d_mode }
 436 #define EXqVexW { OP_EX_VexW, q_mode }
 437 #define EXVexImmW { OP_EX_VexImmW, x_mode }
 438 #define XMVex { OP_XMM_Vex, 0 }
 439 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
 440 #define XMVexW { OP_XMM_VexW, 0 }
 441 #define XMVexI4 { OP_REG_VexI4, x_mode }
 442 #define PCLMUL { PCLMUL_Fixup, 0 }
 443 #define VZERO { VZERO_Fixup, 0 }
 444 #define VCMP { VCMP_Fixup, 0 }
 445 #define VPCMP { VPCMP_Fixup, 0 }
 446
 447 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 448 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 449
 450 #define XMask { OP_Mask, mask_mode }
 451 #define MaskG { OP_G, mask_mode }
 452 #define MaskE { OP_E, mask_mode }
 453 #define MaskBDE { OP_E, mask_bd_mode }
 454 #define MaskR { OP_R, mask_mode }
 455 #define MaskVex { OP_VEX, mask_mode }
 456
 457 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 458 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
 459 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 460 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
 461
 462 /* Used handle "rep" prefix for string instructions.  */
 463 #define Xbr { REP_Fixup, eSI_reg }
 464 #define Xvr { REP_Fixup, eSI_reg }
 465 #define Ybr { REP_Fixup, eDI_reg }
 466 #define Yvr { REP_Fixup, eDI_reg }
 467 #define Yzr { REP_Fixup, eDI_reg }
 468 #define indirDXr { REP_Fixup, indir_dx_reg }
 469 #define ALr { REP_Fixup, al_reg }
 470 #define eAXr { REP_Fixup, eAX_reg }
 471
 472 /* Used handle HLE prefix for lockable instructions.  */
 473 #define Ebh1 { HLE_Fixup1, b_mode }
 474 #define Evh1 { HLE_Fixup1, v_mode }
 475 #define Ebh2 { HLE_Fixup2, b_mode }
 476 #define Evh2 { HLE_Fixup2, v_mode }
 477 #define Ebh3 { HLE_Fixup3, b_mode }
 478 #define Evh3 { HLE_Fixup3, v_mode }
 479
 480 #define BND { BND_Fixup, 0 }
 481
 482 #define cond_jump_flag { NULL, cond_jump_mode }
 483 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 484
 485 /* bits in sizeflag */
 486 #define SUFFIX_ALWAYS 4
 487 #define AFLAG 2
 488 #define DFLAG 1
 489
 490 enum
 491 {
 492   /* byte operand */
 493   b_mode = 1,
 494   /* byte operand with operand swapped */
 495   b_swap_mode,
 496   /* byte operand, sign extend like 'T' suffix */
 497   b_T_mode,
 498   /* operand size depends on prefixes */
 499   v_mode,
 500   /* operand size depends on prefixes with operand swapped */
 501   v_swap_mode,
 502   /* word operand */
 503   w_mode,
 504   /* double word operand  */
 505   d_mode,
 506   /* double word operand with operand swapped */
 507   d_swap_mode,
 508   /* quad word operand */
 509   q_mode,
 510   /* quad word operand with operand swapped */
 511   q_swap_mode,
 512   /* ten-byte operand */
 513   t_mode,
 514   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 515      broadcast enabled.  */
 516   x_mode,
 517   /* Similar to x_mode, but with different EVEX mem shifts.  */
 518   evex_x_gscat_mode,
 519   /* Similar to x_mode, but with disabled broadcast.  */
 520   evex_x_nobcst_mode,
 521   /* Similar to x_mode, but with operands swapped and disabled broadcast
 522      in EVEX.  */
 523   x_swap_mode,
 524   /* 16-byte XMM operand */
 525   xmm_mode,
 526   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 527      memory operand (depending on vector length).  Broadcast isn't
 528      allowed.  */
 529   xmmq_mode,
 530   /* Same as xmmq_mode, but broadcast is allowed.  */
 531   evex_half_bcst_xmmq_mode,
 532   /* XMM register or byte memory operand */
 533   xmm_mb_mode,
 534   /* XMM register or word memory operand */
 535   xmm_mw_mode,
 536   /* XMM register or double word memory operand */
 537   xmm_md_mode,
 538   /* XMM register or quad word memory operand */
 539   xmm_mq_mode,
 540   /* XMM register or double/quad word memory operand, depending on
 541      VEX.W.  */
 542   xmm_mdq_mode,
 543   /* 16-byte XMM, word, double word or quad word operand.  */
 544   xmmdw_mode,
 545   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 546   xmmqd_mode,
 547   /* 32-byte YMM operand */
 548   ymm_mode,
 549   /* quad word, ymmword or zmmword memory operand.  */
 550   ymmq_mode,
 551   /* 32-byte YMM or 16-byte word operand */
 552   ymmxmm_mode,
 553   /* d_mode in 32bit, q_mode in 64bit mode.  */
 554   m_mode,
 555   /* pair of v_mode operands */
 556   a_mode,
 557   cond_jump_mode,
 558   loop_jcxz_mode,
 559   v_bnd_mode,
 560   /* operand size depends on REX prefixes.  */
 561   dq_mode,
 562   /* registers like dq_mode, memory like w_mode.  */
 563   dqw_mode,
 564   dqw_swap_mode,
 565   bnd_mode,
 566   /* 4- or 6-byte pointer operand */
 567   f_mode,
 568   const_1_mode,
 569   /* v_mode for stack-related opcodes.  */
 570   stack_v_mode,
 571   /* non-quad operand size depends on prefixes */
 572   z_mode,
 573   /* 16-byte operand */
 574   o_mode,
 575   /* registers like dq_mode, memory like b_mode.  */
 576   dqb_mode,
 577   /* registers like d_mode, memory like b_mode.  */
 578   db_mode,
 579   /* registers like d_mode, memory like w_mode.  */
 580   dw_mode,
 581   /* registers like dq_mode, memory like d_mode.  */
 582   dqd_mode,
 583   /* normal vex mode */
 584   vex_mode,
 585   /* 128bit vex mode */
 586   vex128_mode,
 587   /* 256bit vex mode */
 588   vex256_mode,
 589   /* operand size depends on the VEX.W bit.  */
 590   vex_w_dq_mode,
 591
 592   /* Similar to vex_w_dq_mode, with VSIB dword indices.  */
 593   vex_vsib_d_w_dq_mode,
 594   /* Similar to vex_vsib_d_w_dq_mode, with smaller memory.  */
 595   vex_vsib_d_w_d_mode,
 596   /* Similar to vex_w_dq_mode, with VSIB qword indices.  */
 597   vex_vsib_q_w_dq_mode,
 598   /* Similar to vex_vsib_q_w_dq_mode, with smaller memory.  */
 599   vex_vsib_q_w_d_mode,
 600
 601   /* scalar, ignore vector length.  */
 602   scalar_mode,
 603   /* like d_mode, ignore vector length.  */
 604   d_scalar_mode,
 605   /* like d_swap_mode, ignore vector length.  */
 606   d_scalar_swap_mode,
 607   /* like q_mode, ignore vector length.  */
 608   q_scalar_mode,
 609   /* like q_swap_mode, ignore vector length.  */
 610   q_scalar_swap_mode,
 611   /* like vex_mode, ignore vector length.  */
 612   vex_scalar_mode,
 613   /* like vex_w_dq_mode, ignore vector length.  */
 614   vex_scalar_w_dq_mode,
 615
 616   /* Static rounding.  */
 617   evex_rounding_mode,
 618   /* Supress all exceptions.  */
 619   evex_sae_mode,
 620
 621   /* Mask register operand.  */
 622   mask_mode,
 623   /* Mask register operand.  */
 624   mask_bd_mode,
 625
 626   es_reg,
 627   cs_reg,
 628   ss_reg,
 629   ds_reg,
 630   fs_reg,
 631   gs_reg,
 632
 633   eAX_reg,
 634   eCX_reg,
 635   eDX_reg,
 636   eBX_reg,
 637   eSP_reg,
 638   eBP_reg,
 639   eSI_reg,
 640   eDI_reg,
 641
 642   al_reg,
 643   cl_reg,
 644   dl_reg,
 645   bl_reg,
 646   ah_reg,
 647   ch_reg,
 648   dh_reg,
 649   bh_reg,
 650
 651   ax_reg,
 652   cx_reg,
 653   dx_reg,
 654   bx_reg,
 655   sp_reg,
 656   bp_reg,
 657   si_reg,
 658   di_reg,
 659
 660   rAX_reg,
 661   rCX_reg,
 662   rDX_reg,
 663   rBX_reg,
 664   rSP_reg,
 665   rBP_reg,
 666   rSI_reg,
 667   rDI_reg,
 668
 669   z_mode_ax_reg,
 670   indir_dx_reg
 671 };
 672
 673 enum
 674 {
 675   FLOATCODE = 1,
 676   USE_REG_TABLE,
 677   USE_MOD_TABLE,
 678   USE_RM_TABLE,
 679   USE_PREFIX_TABLE,
 680   USE_X86_64_TABLE,
 681   USE_3BYTE_TABLE,
 682   USE_XOP_8F_TABLE,
 683   USE_VEX_C4_TABLE,
 684   USE_VEX_C5_TABLE,
 685   USE_VEX_LEN_TABLE,
 686   USE_VEX_W_TABLE,
 687   USE_EVEX_TABLE
 688 };
 689
 690 #define FLOAT                   NULL, { { NULL, FLOATCODE } }, 0
 691
 692 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }, 0
 693 #define DIS386_PREFIX(T, I, P)          NULL, { { NULL, (T)}, { NULL,  (I) } }, P
 694 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 695 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 696 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 697 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 698 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 699 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 700 #define THREE_BYTE_TABLE_PREFIX(I, P)   DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
 701 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 702 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 703 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 704 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 705 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 706 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 707
 708 enum
 709 {
 710   REG_80 = 0,
 711   REG_81,
 712   REG_82,
 713   REG_8F,
 714   REG_C0,
 715   REG_C1,
 716   REG_C6,
 717   REG_C7,
 718   REG_D0,
 719   REG_D1,
 720   REG_D2,
 721   REG_D3,
 722   REG_F6,
 723   REG_F7,
 724   REG_FE,
 725   REG_FF,
 726   REG_0F00,
 727   REG_0F01,
 728   REG_0F0D,
 729   REG_0F18,
 730   REG_0F71,
 731   REG_0F72,
 732   REG_0F73,
 733   REG_0FA6,
 734   REG_0FA7,
 735   REG_0FAE,
 736   REG_0FBA,
 737   REG_0FC7,
 738   REG_VEX_0F71,
 739   REG_VEX_0F72,
 740   REG_VEX_0F73,
 741   REG_VEX_0FAE,
 742   REG_VEX_0F38F3,
 743   REG_XOP_LWPCB,
 744   REG_XOP_LWP,
 745   REG_XOP_TBM_01,
 746   REG_XOP_TBM_02,
 747
 748   REG_EVEX_0F71,
 749   REG_EVEX_0F72,
 750   REG_EVEX_0F73,
 751   REG_EVEX_0F38C6,
 752   REG_EVEX_0F38C7
 753 };
 754
 755 enum
 756 {
 757   MOD_8D = 0,
 758   MOD_C6_REG_7,
 759   MOD_C7_REG_7,
 760   MOD_FF_REG_3,
 761   MOD_FF_REG_5,
 762   MOD_0F01_REG_0,
 763   MOD_0F01_REG_1,
 764   MOD_0F01_REG_2,
 765   MOD_0F01_REG_3,
 766   MOD_0F01_REG_7,
 767   MOD_0F12_PREFIX_0,
 768   MOD_0F13,
 769   MOD_0F16_PREFIX_0,
 770   MOD_0F17,
 771   MOD_0F18_REG_0,
 772   MOD_0F18_REG_1,
 773   MOD_0F18_REG_2,
 774   MOD_0F18_REG_3,
 775   MOD_0F18_REG_4,
 776   MOD_0F18_REG_5,
 777   MOD_0F18_REG_6,
 778   MOD_0F18_REG_7,
 779   MOD_0F1A_PREFIX_0,
 780   MOD_0F1B_PREFIX_0,
 781   MOD_0F1B_PREFIX_1,
 782   MOD_0F24,
 783   MOD_0F26,
 784   MOD_0F2B_PREFIX_0,
 785   MOD_0F2B_PREFIX_1,
 786   MOD_0F2B_PREFIX_2,
 787   MOD_0F2B_PREFIX_3,
 788   MOD_0F51,
 789   MOD_0F71_REG_2,
 790   MOD_0F71_REG_4,
 791   MOD_0F71_REG_6,
 792   MOD_0F72_REG_2,
 793   MOD_0F72_REG_4,
 794   MOD_0F72_REG_6,
 795   MOD_0F73_REG_2,
 796   MOD_0F73_REG_3,
 797   MOD_0F73_REG_6,
 798   MOD_0F73_REG_7,
 799   MOD_0FAE_REG_0,
 800   MOD_0FAE_REG_1,
 801   MOD_0FAE_REG_2,
 802   MOD_0FAE_REG_3,
 803   MOD_0FAE_REG_4,
 804   MOD_0FAE_REG_5,
 805   MOD_0FAE_REG_6,
 806   MOD_0FAE_REG_7,
 807   MOD_0FB2,
 808   MOD_0FB4,
 809   MOD_0FB5,
 810   MOD_0FC7_REG_3,
 811   MOD_0FC7_REG_4,
 812   MOD_0FC7_REG_5,
 813   MOD_0FC7_REG_6,
 814   MOD_0FC7_REG_7,
 815   MOD_0FD7,
 816   MOD_0FE7_PREFIX_2,
 817   MOD_0FF0_PREFIX_3,
 818   MOD_0F382A_PREFIX_2,
 819   MOD_62_32BIT,
 820   MOD_C4_32BIT,
 821   MOD_C5_32BIT,
 822   MOD_VEX_0F12_PREFIX_0,
 823   MOD_VEX_0F13,
 824   MOD_VEX_0F16_PREFIX_0,
 825   MOD_VEX_0F17,
 826   MOD_VEX_0F2B,
 827   MOD_VEX_0F50,
 828   MOD_VEX_0F71_REG_2,
 829   MOD_VEX_0F71_REG_4,
 830   MOD_VEX_0F71_REG_6,
 831   MOD_VEX_0F72_REG_2,
 832   MOD_VEX_0F72_REG_4,
 833   MOD_VEX_0F72_REG_6,
 834   MOD_VEX_0F73_REG_2,
 835   MOD_VEX_0F73_REG_3,
 836   MOD_VEX_0F73_REG_6,
 837   MOD_VEX_0F73_REG_7,
 838   MOD_VEX_0FAE_REG_2,
 839   MOD_VEX_0FAE_REG_3,
 840   MOD_VEX_0FD7_PREFIX_2,
 841   MOD_VEX_0FE7_PREFIX_2,
 842   MOD_VEX_0FF0_PREFIX_3,
 843   MOD_VEX_0F381A_PREFIX_2,
 844   MOD_VEX_0F382A_PREFIX_2,
 845   MOD_VEX_0F382C_PREFIX_2,
 846   MOD_VEX_0F382D_PREFIX_2,
 847   MOD_VEX_0F382E_PREFIX_2,
 848   MOD_VEX_0F382F_PREFIX_2,
 849   MOD_VEX_0F385A_PREFIX_2,
 850   MOD_VEX_0F388C_PREFIX_2,
 851   MOD_VEX_0F388E_PREFIX_2,
 852
 853   MOD_EVEX_0F10_PREFIX_1,
 854   MOD_EVEX_0F10_PREFIX_3,
 855   MOD_EVEX_0F11_PREFIX_1,
 856   MOD_EVEX_0F11_PREFIX_3,
 857   MOD_EVEX_0F12_PREFIX_0,
 858   MOD_EVEX_0F16_PREFIX_0,
 859   MOD_EVEX_0F38C6_REG_1,
 860   MOD_EVEX_0F38C6_REG_2,
 861   MOD_EVEX_0F38C6_REG_5,
 862   MOD_EVEX_0F38C6_REG_6,
 863   MOD_EVEX_0F38C7_REG_1,
 864   MOD_EVEX_0F38C7_REG_2,
 865   MOD_EVEX_0F38C7_REG_5,
 866   MOD_EVEX_0F38C7_REG_6
 867 };
 868
 869 enum
 870 {
 871   RM_C6_REG_7 = 0,
 872   RM_C7_REG_7,
 873   RM_0F01_REG_0,
 874   RM_0F01_REG_1,
 875   RM_0F01_REG_2,
 876   RM_0F01_REG_3,
 877   RM_0F01_REG_7,
 878   RM_0FAE_REG_5,
 879   RM_0FAE_REG_6,
 880   RM_0FAE_REG_7
 881 };
 882
 883 enum
 884 {
 885   PREFIX_90 = 0,
 886   PREFIX_0F10,
 887   PREFIX_0F11,
 888   PREFIX_0F12,
 889   PREFIX_0F16,
 890   PREFIX_0F1A,
 891   PREFIX_0F1B,
 892   PREFIX_0F2A,
 893   PREFIX_0F2B,
 894   PREFIX_0F2C,
 895   PREFIX_0F2D,
 896   PREFIX_0F2E,
 897   PREFIX_0F2F,
 898   PREFIX_0F51,
 899   PREFIX_0F52,
 900   PREFIX_0F53,
 901   PREFIX_0F58,
 902   PREFIX_0F59,
 903   PREFIX_0F5A,
 904   PREFIX_0F5B,
 905   PREFIX_0F5C,
 906   PREFIX_0F5D,
 907   PREFIX_0F5E,
 908   PREFIX_0F5F,
 909   PREFIX_0F60,
 910   PREFIX_0F61,
 911   PREFIX_0F62,
 912   PREFIX_0F6C,
 913   PREFIX_0F6D,
 914   PREFIX_0F6F,
 915   PREFIX_0F70,
 916   PREFIX_0F73_REG_3,
 917   PREFIX_0F73_REG_7,
 918   PREFIX_0F78,
 919   PREFIX_0F79,
 920   PREFIX_0F7C,
 921   PREFIX_0F7D,
 922   PREFIX_0F7E,
 923   PREFIX_0F7F,
 924   PREFIX_0FAE_REG_0,
 925   PREFIX_0FAE_REG_1,
 926   PREFIX_0FAE_REG_2,
 927   PREFIX_0FAE_REG_3,
 928   PREFIX_0FAE_REG_6,
 929   PREFIX_0FAE_REG_7,
 930   PREFIX_RM_0_0FAE_REG_7,
 931   PREFIX_0FB8,
 932   PREFIX_0FBC,
 933   PREFIX_0FBD,
 934   PREFIX_0FC2,
 935   PREFIX_0FC3,
 936   PREFIX_MOD_0_0FC7_REG_6,
 937   PREFIX_MOD_3_0FC7_REG_6,
 938   PREFIX_MOD_3_0FC7_REG_7,
 939   PREFIX_0FD0,
 940   PREFIX_0FD6,
 941   PREFIX_0FE6,
 942   PREFIX_0FE7,
 943   PREFIX_0FF0,
 944   PREFIX_0FF7,
 945   PREFIX_0F3810,
 946   PREFIX_0F3814,
 947   PREFIX_0F3815,
 948   PREFIX_0F3817,
 949   PREFIX_0F3820,
 950   PREFIX_0F3821,
 951   PREFIX_0F3822,
 952   PREFIX_0F3823,
 953   PREFIX_0F3824,
 954   PREFIX_0F3825,
 955   PREFIX_0F3828,
 956   PREFIX_0F3829,
 957   PREFIX_0F382A,
 958   PREFIX_0F382B,
 959   PREFIX_0F3830,
 960   PREFIX_0F3831,
 961   PREFIX_0F3832,
 962   PREFIX_0F3833,
 963   PREFIX_0F3834,
 964   PREFIX_0F3835,
 965   PREFIX_0F3837,
 966   PREFIX_0F3838,
 967   PREFIX_0F3839,
 968   PREFIX_0F383A,
 969   PREFIX_0F383B,
 970   PREFIX_0F383C,
 971   PREFIX_0F383D,
 972   PREFIX_0F383E,
 973   PREFIX_0F383F,
 974   PREFIX_0F3840,
 975   PREFIX_0F3841,
 976   PREFIX_0F3880,
 977   PREFIX_0F3881,
 978   PREFIX_0F3882,
 979   PREFIX_0F38C8,
 980   PREFIX_0F38C9,
 981   PREFIX_0F38CA,
 982   PREFIX_0F38CB,
 983   PREFIX_0F38CC,
 984   PREFIX_0F38CD,
 985   PREFIX_0F38DB,
 986   PREFIX_0F38DC,
 987   PREFIX_0F38DD,
 988   PREFIX_0F38DE,
 989   PREFIX_0F38DF,
 990   PREFIX_0F38F0,
 991   PREFIX_0F38F1,
 992   PREFIX_0F38F6,
 993   PREFIX_0F3A08,
 994   PREFIX_0F3A09,
 995   PREFIX_0F3A0A,
 996   PREFIX_0F3A0B,
 997   PREFIX_0F3A0C,
 998   PREFIX_0F3A0D,
 999   PREFIX_0F3A0E,
1000   PREFIX_0F3A14,
1001   PREFIX_0F3A15,
1002   PREFIX_0F3A16,
1003   PREFIX_0F3A17,
1004   PREFIX_0F3A20,
1005   PREFIX_0F3A21,
1006   PREFIX_0F3A22,
1007   PREFIX_0F3A40,
1008   PREFIX_0F3A41,
1009   PREFIX_0F3A42,
1010   PREFIX_0F3A44,
1011   PREFIX_0F3A60,
1012   PREFIX_0F3A61,
1013   PREFIX_0F3A62,
1014   PREFIX_0F3A63,
1015   PREFIX_0F3ACC,
1016   PREFIX_0F3ADF,
1017   PREFIX_VEX_0F10,
1018   PREFIX_VEX_0F11,
1019   PREFIX_VEX_0F12,
1020   PREFIX_VEX_0F16,
1021   PREFIX_VEX_0F2A,
1022   PREFIX_VEX_0F2C,
1023   PREFIX_VEX_0F2D,
1024   PREFIX_VEX_0F2E,
1025   PREFIX_VEX_0F2F,
1026   PREFIX_VEX_0F41,
1027   PREFIX_VEX_0F42,
1028   PREFIX_VEX_0F44,
1029   PREFIX_VEX_0F45,
1030   PREFIX_VEX_0F46,
1031   PREFIX_VEX_0F47,
1032   PREFIX_VEX_0F4A,
1033   PREFIX_VEX_0F4B,
1034   PREFIX_VEX_0F51,
1035   PREFIX_VEX_0F52,
1036   PREFIX_VEX_0F53,
1037   PREFIX_VEX_0F58,
1038   PREFIX_VEX_0F59,
1039   PREFIX_VEX_0F5A,
1040   PREFIX_VEX_0F5B,
1041   PREFIX_VEX_0F5C,
1042   PREFIX_VEX_0F5D,
1043   PREFIX_VEX_0F5E,
1044   PREFIX_VEX_0F5F,
1045   PREFIX_VEX_0F60,
1046   PREFIX_VEX_0F61,
1047   PREFIX_VEX_0F62,
1048   PREFIX_VEX_0F63,
1049   PREFIX_VEX_0F64,
1050   PREFIX_VEX_0F65,
1051   PREFIX_VEX_0F66,
1052   PREFIX_VEX_0F67,
1053   PREFIX_VEX_0F68,
1054   PREFIX_VEX_0F69,
1055   PREFIX_VEX_0F6A,
1056   PREFIX_VEX_0F6B,
1057   PREFIX_VEX_0F6C,
1058   PREFIX_VEX_0F6D,
1059   PREFIX_VEX_0F6E,
1060   PREFIX_VEX_0F6F,
1061   PREFIX_VEX_0F70,
1062   PREFIX_VEX_0F71_REG_2,
1063   PREFIX_VEX_0F71_REG_4,
1064   PREFIX_VEX_0F71_REG_6,
1065   PREFIX_VEX_0F72_REG_2,
1066   PREFIX_VEX_0F72_REG_4,
1067   PREFIX_VEX_0F72_REG_6,
1068   PREFIX_VEX_0F73_REG_2,
1069   PREFIX_VEX_0F73_REG_3,
1070   PREFIX_VEX_0F73_REG_6,
1071   PREFIX_VEX_0F73_REG_7,
1072   PREFIX_VEX_0F74,
1073   PREFIX_VEX_0F75,
1074   PREFIX_VEX_0F76,
1075   PREFIX_VEX_0F77,
1076   PREFIX_VEX_0F7C,
1077   PREFIX_VEX_0F7D,
1078   PREFIX_VEX_0F7E,
1079   PREFIX_VEX_0F7F,
1080   PREFIX_VEX_0F90,
1081   PREFIX_VEX_0F91,
1082   PREFIX_VEX_0F92,
1083   PREFIX_VEX_0F93,
1084   PREFIX_VEX_0F98,
1085   PREFIX_VEX_0F99,
1086   PREFIX_VEX_0FC2,
1087   PREFIX_VEX_0FC4,
1088   PREFIX_VEX_0FC5,
1089   PREFIX_VEX_0FD0,
1090   PREFIX_VEX_0FD1,
1091   PREFIX_VEX_0FD2,
1092   PREFIX_VEX_0FD3,
1093   PREFIX_VEX_0FD4,
1094   PREFIX_VEX_0FD5,
1095   PREFIX_VEX_0FD6,
1096   PREFIX_VEX_0FD7,
1097   PREFIX_VEX_0FD8,
1098   PREFIX_VEX_0FD9,
1099   PREFIX_VEX_0FDA,
1100   PREFIX_VEX_0FDB,
1101   PREFIX_VEX_0FDC,
1102   PREFIX_VEX_0FDD,
1103   PREFIX_VEX_0FDE,
1104   PREFIX_VEX_0FDF,
1105   PREFIX_VEX_0FE0,
1106   PREFIX_VEX_0FE1,
1107   PREFIX_VEX_0FE2,
1108   PREFIX_VEX_0FE3,
1109   PREFIX_VEX_0FE4,
1110   PREFIX_VEX_0FE5,
1111   PREFIX_VEX_0FE6,
1112   PREFIX_VEX_0FE7,
1113   PREFIX_VEX_0FE8,
1114   PREFIX_VEX_0FE9,
1115   PREFIX_VEX_0FEA,
1116   PREFIX_VEX_0FEB,
1117   PREFIX_VEX_0FEC,
1118   PREFIX_VEX_0FED,
1119   PREFIX_VEX_0FEE,
1120   PREFIX_VEX_0FEF,
1121   PREFIX_VEX_0FF0,
1122   PREFIX_VEX_0FF1,
1123   PREFIX_VEX_0FF2,
1124   PREFIX_VEX_0FF3,
1125   PREFIX_VEX_0FF4,
1126   PREFIX_VEX_0FF5,
1127   PREFIX_VEX_0FF6,
1128   PREFIX_VEX_0FF7,
1129   PREFIX_VEX_0FF8,
1130   PREFIX_VEX_0FF9,
1131   PREFIX_VEX_0FFA,
1132   PREFIX_VEX_0FFB,
1133   PREFIX_VEX_0FFC,
1134   PREFIX_VEX_0FFD,
1135   PREFIX_VEX_0FFE,
1136   PREFIX_VEX_0F3800,
1137   PREFIX_VEX_0F3801,
1138   PREFIX_VEX_0F3802,
1139   PREFIX_VEX_0F3803,
1140   PREFIX_VEX_0F3804,
1141   PREFIX_VEX_0F3805,
1142   PREFIX_VEX_0F3806,
1143   PREFIX_VEX_0F3807,
1144   PREFIX_VEX_0F3808,
1145   PREFIX_VEX_0F3809,
1146   PREFIX_VEX_0F380A,
1147   PREFIX_VEX_0F380B,
1148   PREFIX_VEX_0F380C,
1149   PREFIX_VEX_0F380D,
1150   PREFIX_VEX_0F380E,
1151   PREFIX_VEX_0F380F,
1152   PREFIX_VEX_0F3813,
1153   PREFIX_VEX_0F3816,
1154   PREFIX_VEX_0F3817,
1155   PREFIX_VEX_0F3818,
1156   PREFIX_VEX_0F3819,
1157   PREFIX_VEX_0F381A,
1158   PREFIX_VEX_0F381C,
1159   PREFIX_VEX_0F381D,
1160   PREFIX_VEX_0F381E,
1161   PREFIX_VEX_0F3820,
1162   PREFIX_VEX_0F3821,
1163   PREFIX_VEX_0F3822,
1164   PREFIX_VEX_0F3823,
1165   PREFIX_VEX_0F3824,
1166   PREFIX_VEX_0F3825,
1167   PREFIX_VEX_0F3828,
1168   PREFIX_VEX_0F3829,
1169   PREFIX_VEX_0F382A,
1170   PREFIX_VEX_0F382B,
1171   PREFIX_VEX_0F382C,
1172   PREFIX_VEX_0F382D,
1173   PREFIX_VEX_0F382E,
1174   PREFIX_VEX_0F382F,
1175   PREFIX_VEX_0F3830,
1176   PREFIX_VEX_0F3831,
1177   PREFIX_VEX_0F3832,
1178   PREFIX_VEX_0F3833,
1179   PREFIX_VEX_0F3834,
1180   PREFIX_VEX_0F3835,
1181   PREFIX_VEX_0F3836,
1182   PREFIX_VEX_0F3837,
1183   PREFIX_VEX_0F3838,
1184   PREFIX_VEX_0F3839,
1185   PREFIX_VEX_0F383A,
1186   PREFIX_VEX_0F383B,
1187   PREFIX_VEX_0F383C,
1188   PREFIX_VEX_0F383D,
1189   PREFIX_VEX_0F383E,
1190   PREFIX_VEX_0F383F,
1191   PREFIX_VEX_0F3840,
1192   PREFIX_VEX_0F3841,
1193   PREFIX_VEX_0F3845,
1194   PREFIX_VEX_0F3846,
1195   PREFIX_VEX_0F3847,
1196   PREFIX_VEX_0F3858,
1197   PREFIX_VEX_0F3859,
1198   PREFIX_VEX_0F385A,
1199   PREFIX_VEX_0F3878,
1200   PREFIX_VEX_0F3879,
1201   PREFIX_VEX_0F388C,
1202   PREFIX_VEX_0F388E,
1203   PREFIX_VEX_0F3890,
1204   PREFIX_VEX_0F3891,
1205   PREFIX_VEX_0F3892,
1206   PREFIX_VEX_0F3893,
1207   PREFIX_VEX_0F3896,
1208   PREFIX_VEX_0F3897,
1209   PREFIX_VEX_0F3898,
1210   PREFIX_VEX_0F3899,
1211   PREFIX_VEX_0F389A,
1212   PREFIX_VEX_0F389B,
1213   PREFIX_VEX_0F389C,
1214   PREFIX_VEX_0F389D,
1215   PREFIX_VEX_0F389E,
1216   PREFIX_VEX_0F389F,
1217   PREFIX_VEX_0F38A6,
1218   PREFIX_VEX_0F38A7,
1219   PREFIX_VEX_0F38A8,
1220   PREFIX_VEX_0F38A9,
1221   PREFIX_VEX_0F38AA,
1222   PREFIX_VEX_0F38AB,
1223   PREFIX_VEX_0F38AC,
1224   PREFIX_VEX_0F38AD,
1225   PREFIX_VEX_0F38AE,
1226   PREFIX_VEX_0F38AF,
1227   PREFIX_VEX_0F38B6,
1228   PREFIX_VEX_0F38B7,
1229   PREFIX_VEX_0F38B8,
1230   PREFIX_VEX_0F38B9,
1231   PREFIX_VEX_0F38BA,
1232   PREFIX_VEX_0F38BB,
1233   PREFIX_VEX_0F38BC,
1234   PREFIX_VEX_0F38BD,
1235   PREFIX_VEX_0F38BE,
1236   PREFIX_VEX_0F38BF,
1237   PREFIX_VEX_0F38DB,
1238   PREFIX_VEX_0F38DC,
1239   PREFIX_VEX_0F38DD,
1240   PREFIX_VEX_0F38DE,
1241   PREFIX_VEX_0F38DF,
1242   PREFIX_VEX_0F38F2,
1243   PREFIX_VEX_0F38F3_REG_1,
1244   PREFIX_VEX_0F38F3_REG_2,
1245   PREFIX_VEX_0F38F3_REG_3,
1246   PREFIX_VEX_0F38F5,
1247   PREFIX_VEX_0F38F6,
1248   PREFIX_VEX_0F38F7,
1249   PREFIX_VEX_0F3A00,
1250   PREFIX_VEX_0F3A01,
1251   PREFIX_VEX_0F3A02,
1252   PREFIX_VEX_0F3A04,
1253   PREFIX_VEX_0F3A05,
1254   PREFIX_VEX_0F3A06,
1255   PREFIX_VEX_0F3A08,
1256   PREFIX_VEX_0F3A09,
1257   PREFIX_VEX_0F3A0A,
1258   PREFIX_VEX_0F3A0B,
1259   PREFIX_VEX_0F3A0C,
1260   PREFIX_VEX_0F3A0D,
1261   PREFIX_VEX_0F3A0E,
1262   PREFIX_VEX_0F3A0F,
1263   PREFIX_VEX_0F3A14,
1264   PREFIX_VEX_0F3A15,
1265   PREFIX_VEX_0F3A16,
1266   PREFIX_VEX_0F3A17,
1267   PREFIX_VEX_0F3A18,
1268   PREFIX_VEX_0F3A19,
1269   PREFIX_VEX_0F3A1D,
1270   PREFIX_VEX_0F3A20,
1271   PREFIX_VEX_0F3A21,
1272   PREFIX_VEX_0F3A22,
1273   PREFIX_VEX_0F3A30,
1274   PREFIX_VEX_0F3A31,
1275   PREFIX_VEX_0F3A32,
1276   PREFIX_VEX_0F3A33,
1277   PREFIX_VEX_0F3A38,
1278   PREFIX_VEX_0F3A39,
1279   PREFIX_VEX_0F3A40,
1280   PREFIX_VEX_0F3A41,
1281   PREFIX_VEX_0F3A42,
1282   PREFIX_VEX_0F3A44,
1283   PREFIX_VEX_0F3A46,
1284   PREFIX_VEX_0F3A48,
1285   PREFIX_VEX_0F3A49,
1286   PREFIX_VEX_0F3A4A,
1287   PREFIX_VEX_0F3A4B,
1288   PREFIX_VEX_0F3A4C,
1289   PREFIX_VEX_0F3A5C,
1290   PREFIX_VEX_0F3A5D,
1291   PREFIX_VEX_0F3A5E,
1292   PREFIX_VEX_0F3A5F,
1293   PREFIX_VEX_0F3A60,
1294   PREFIX_VEX_0F3A61,
1295   PREFIX_VEX_0F3A62,
1296   PREFIX_VEX_0F3A63,
1297   PREFIX_VEX_0F3A68,
1298   PREFIX_VEX_0F3A69,
1299   PREFIX_VEX_0F3A6A,
1300   PREFIX_VEX_0F3A6B,
1301   PREFIX_VEX_0F3A6C,
1302   PREFIX_VEX_0F3A6D,
1303   PREFIX_VEX_0F3A6E,
1304   PREFIX_VEX_0F3A6F,
1305   PREFIX_VEX_0F3A78,
1306   PREFIX_VEX_0F3A79,
1307   PREFIX_VEX_0F3A7A,
1308   PREFIX_VEX_0F3A7B,
1309   PREFIX_VEX_0F3A7C,
1310   PREFIX_VEX_0F3A7D,
1311   PREFIX_VEX_0F3A7E,
1312   PREFIX_VEX_0F3A7F,
1313   PREFIX_VEX_0F3ADF,
1314   PREFIX_VEX_0F3AF0,
1315
1316   PREFIX_EVEX_0F10,
1317   PREFIX_EVEX_0F11,
1318   PREFIX_EVEX_0F12,
1319   PREFIX_EVEX_0F13,
1320   PREFIX_EVEX_0F14,
1321   PREFIX_EVEX_0F15,
1322   PREFIX_EVEX_0F16,
1323   PREFIX_EVEX_0F17,
1324   PREFIX_EVEX_0F28,
1325   PREFIX_EVEX_0F29,
1326   PREFIX_EVEX_0F2A,
1327   PREFIX_EVEX_0F2B,
1328   PREFIX_EVEX_0F2C,
1329   PREFIX_EVEX_0F2D,
1330   PREFIX_EVEX_0F2E,
1331   PREFIX_EVEX_0F2F,
1332   PREFIX_EVEX_0F51,
1333   PREFIX_EVEX_0F54,
1334   PREFIX_EVEX_0F55,
1335   PREFIX_EVEX_0F56,
1336   PREFIX_EVEX_0F57,
1337   PREFIX_EVEX_0F58,
1338   PREFIX_EVEX_0F59,
1339   PREFIX_EVEX_0F5A,
1340   PREFIX_EVEX_0F5B,
1341   PREFIX_EVEX_0F5C,
1342   PREFIX_EVEX_0F5D,
1343   PREFIX_EVEX_0F5E,
1344   PREFIX_EVEX_0F5F,
1345   PREFIX_EVEX_0F60,
1346   PREFIX_EVEX_0F61,
1347   PREFIX_EVEX_0F62,
1348   PREFIX_EVEX_0F63,
1349   PREFIX_EVEX_0F64,
1350   PREFIX_EVEX_0F65,
1351   PREFIX_EVEX_0F66,
1352   PREFIX_EVEX_0F67,
1353   PREFIX_EVEX_0F68,
1354   PREFIX_EVEX_0F69,
1355   PREFIX_EVEX_0F6A,
1356   PREFIX_EVEX_0F6B,
1357   PREFIX_EVEX_0F6C,
1358   PREFIX_EVEX_0F6D,
1359   PREFIX_EVEX_0F6E,
1360   PREFIX_EVEX_0F6F,
1361   PREFIX_EVEX_0F70,
1362   PREFIX_EVEX_0F71_REG_2,
1363   PREFIX_EVEX_0F71_REG_4,
1364   PREFIX_EVEX_0F71_REG_6,
1365   PREFIX_EVEX_0F72_REG_0,
1366   PREFIX_EVEX_0F72_REG_1,
1367   PREFIX_EVEX_0F72_REG_2,
1368   PREFIX_EVEX_0F72_REG_4,
1369   PREFIX_EVEX_0F72_REG_6,
1370   PREFIX_EVEX_0F73_REG_2,
1371   PREFIX_EVEX_0F73_REG_3,
1372   PREFIX_EVEX_0F73_REG_6,
1373   PREFIX_EVEX_0F73_REG_7,
1374   PREFIX_EVEX_0F74,
1375   PREFIX_EVEX_0F75,
1376   PREFIX_EVEX_0F76,
1377   PREFIX_EVEX_0F78,
1378   PREFIX_EVEX_0F79,
1379   PREFIX_EVEX_0F7A,
1380   PREFIX_EVEX_0F7B,
1381   PREFIX_EVEX_0F7E,
1382   PREFIX_EVEX_0F7F,
1383   PREFIX_EVEX_0FC2,
1384   PREFIX_EVEX_0FC4,
1385   PREFIX_EVEX_0FC5,
1386   PREFIX_EVEX_0FC6,
1387   PREFIX_EVEX_0FD1,
1388   PREFIX_EVEX_0FD2,
1389   PREFIX_EVEX_0FD3,
1390   PREFIX_EVEX_0FD4,
1391   PREFIX_EVEX_0FD5,
1392   PREFIX_EVEX_0FD6,
1393   PREFIX_EVEX_0FD8,
1394   PREFIX_EVEX_0FD9,
1395   PREFIX_EVEX_0FDA,
1396   PREFIX_EVEX_0FDB,
1397   PREFIX_EVEX_0FDC,
1398   PREFIX_EVEX_0FDD,
1399   PREFIX_EVEX_0FDE,
1400   PREFIX_EVEX_0FDF,
1401   PREFIX_EVEX_0FE0,
1402   PREFIX_EVEX_0FE1,
1403   PREFIX_EVEX_0FE2,
1404   PREFIX_EVEX_0FE3,
1405   PREFIX_EVEX_0FE4,
1406   PREFIX_EVEX_0FE5,
1407   PREFIX_EVEX_0FE6,
1408   PREFIX_EVEX_0FE7,
1409   PREFIX_EVEX_0FE8,
1410   PREFIX_EVEX_0FE9,
1411   PREFIX_EVEX_0FEA,
1412   PREFIX_EVEX_0FEB,
1413   PREFIX_EVEX_0FEC,
1414   PREFIX_EVEX_0FED,
1415   PREFIX_EVEX_0FEE,
1416   PREFIX_EVEX_0FEF,
1417   PREFIX_EVEX_0FF1,
1418   PREFIX_EVEX_0FF2,
1419   PREFIX_EVEX_0FF3,
1420   PREFIX_EVEX_0FF4,
1421   PREFIX_EVEX_0FF5,
1422   PREFIX_EVEX_0FF6,
1423   PREFIX_EVEX_0FF8,
1424   PREFIX_EVEX_0FF9,
1425   PREFIX_EVEX_0FFA,
1426   PREFIX_EVEX_0FFB,
1427   PREFIX_EVEX_0FFC,
1428   PREFIX_EVEX_0FFD,
1429   PREFIX_EVEX_0FFE,
1430   PREFIX_EVEX_0F3800,
1431   PREFIX_EVEX_0F3804,
1432   PREFIX_EVEX_0F380B,
1433   PREFIX_EVEX_0F380C,
1434   PREFIX_EVEX_0F380D,
1435   PREFIX_EVEX_0F3810,
1436   PREFIX_EVEX_0F3811,
1437   PREFIX_EVEX_0F3812,
1438   PREFIX_EVEX_0F3813,
1439   PREFIX_EVEX_0F3814,
1440   PREFIX_EVEX_0F3815,
1441   PREFIX_EVEX_0F3816,
1442   PREFIX_EVEX_0F3818,
1443   PREFIX_EVEX_0F3819,
1444   PREFIX_EVEX_0F381A,
1445   PREFIX_EVEX_0F381B,
1446   PREFIX_EVEX_0F381C,
1447   PREFIX_EVEX_0F381D,
1448   PREFIX_EVEX_0F381E,
1449   PREFIX_EVEX_0F381F,
1450   PREFIX_EVEX_0F3820,
1451   PREFIX_EVEX_0F3821,
1452   PREFIX_EVEX_0F3822,
1453   PREFIX_EVEX_0F3823,
1454   PREFIX_EVEX_0F3824,
1455   PREFIX_EVEX_0F3825,
1456   PREFIX_EVEX_0F3826,
1457   PREFIX_EVEX_0F3827,
1458   PREFIX_EVEX_0F3828,
1459   PREFIX_EVEX_0F3829,
1460   PREFIX_EVEX_0F382A,
1461   PREFIX_EVEX_0F382B,
1462   PREFIX_EVEX_0F382C,
1463   PREFIX_EVEX_0F382D,
1464   PREFIX_EVEX_0F3830,
1465   PREFIX_EVEX_0F3831,
1466   PREFIX_EVEX_0F3832,
1467   PREFIX_EVEX_0F3833,
1468   PREFIX_EVEX_0F3834,
1469   PREFIX_EVEX_0F3835,
1470   PREFIX_EVEX_0F3836,
1471   PREFIX_EVEX_0F3837,
1472   PREFIX_EVEX_0F3838,
1473   PREFIX_EVEX_0F3839,
1474   PREFIX_EVEX_0F383A,
1475   PREFIX_EVEX_0F383B,
1476   PREFIX_EVEX_0F383C,
1477   PREFIX_EVEX_0F383D,
1478   PREFIX_EVEX_0F383E,
1479   PREFIX_EVEX_0F383F,
1480   PREFIX_EVEX_0F3840,
1481   PREFIX_EVEX_0F3842,
1482   PREFIX_EVEX_0F3843,
1483   PREFIX_EVEX_0F3844,
1484   PREFIX_EVEX_0F3845,
1485   PREFIX_EVEX_0F3846,
1486   PREFIX_EVEX_0F3847,
1487   PREFIX_EVEX_0F384C,
1488   PREFIX_EVEX_0F384D,
1489   PREFIX_EVEX_0F384E,
1490   PREFIX_EVEX_0F384F,
1491   PREFIX_EVEX_0F3858,
1492   PREFIX_EVEX_0F3859,
1493   PREFIX_EVEX_0F385A,
1494   PREFIX_EVEX_0F385B,
1495   PREFIX_EVEX_0F3864,
1496   PREFIX_EVEX_0F3865,
1497   PREFIX_EVEX_0F3866,
1498   PREFIX_EVEX_0F3875,
1499   PREFIX_EVEX_0F3876,
1500   PREFIX_EVEX_0F3877,
1501   PREFIX_EVEX_0F3878,
1502   PREFIX_EVEX_0F3879,
1503   PREFIX_EVEX_0F387A,
1504   PREFIX_EVEX_0F387B,
1505   PREFIX_EVEX_0F387C,
1506   PREFIX_EVEX_0F387D,
1507   PREFIX_EVEX_0F387E,
1508   PREFIX_EVEX_0F387F,
1509   PREFIX_EVEX_0F3883,
1510   PREFIX_EVEX_0F3888,
1511   PREFIX_EVEX_0F3889,
1512   PREFIX_EVEX_0F388A,
1513   PREFIX_EVEX_0F388B,
1514   PREFIX_EVEX_0F388D,
1515   PREFIX_EVEX_0F3890,
1516   PREFIX_EVEX_0F3891,
1517   PREFIX_EVEX_0F3892,
1518   PREFIX_EVEX_0F3893,
1519   PREFIX_EVEX_0F3896,
1520   PREFIX_EVEX_0F3897,
1521   PREFIX_EVEX_0F3898,
1522   PREFIX_EVEX_0F3899,
1523   PREFIX_EVEX_0F389A,
1524   PREFIX_EVEX_0F389B,
1525   PREFIX_EVEX_0F389C,
1526   PREFIX_EVEX_0F389D,
1527   PREFIX_EVEX_0F389E,
1528   PREFIX_EVEX_0F389F,
1529   PREFIX_EVEX_0F38A0,
1530   PREFIX_EVEX_0F38A1,
1531   PREFIX_EVEX_0F38A2,
1532   PREFIX_EVEX_0F38A3,
1533   PREFIX_EVEX_0F38A6,
1534   PREFIX_EVEX_0F38A7,
1535   PREFIX_EVEX_0F38A8,
1536   PREFIX_EVEX_0F38A9,
1537   PREFIX_EVEX_0F38AA,
1538   PREFIX_EVEX_0F38AB,
1539   PREFIX_EVEX_0F38AC,
1540   PREFIX_EVEX_0F38AD,
1541   PREFIX_EVEX_0F38AE,
1542   PREFIX_EVEX_0F38AF,
1543   PREFIX_EVEX_0F38B4,
1544   PREFIX_EVEX_0F38B5,
1545   PREFIX_EVEX_0F38B6,
1546   PREFIX_EVEX_0F38B7,
1547   PREFIX_EVEX_0F38B8,
1548   PREFIX_EVEX_0F38B9,
1549   PREFIX_EVEX_0F38BA,
1550   PREFIX_EVEX_0F38BB,
1551   PREFIX_EVEX_0F38BC,
1552   PREFIX_EVEX_0F38BD,
1553   PREFIX_EVEX_0F38BE,
1554   PREFIX_EVEX_0F38BF,
1555   PREFIX_EVEX_0F38C4,
1556   PREFIX_EVEX_0F38C6_REG_1,
1557   PREFIX_EVEX_0F38C6_REG_2,
1558   PREFIX_EVEX_0F38C6_REG_5,
1559   PREFIX_EVEX_0F38C6_REG_6,
1560   PREFIX_EVEX_0F38C7_REG_1,
1561   PREFIX_EVEX_0F38C7_REG_2,
1562   PREFIX_EVEX_0F38C7_REG_5,
1563   PREFIX_EVEX_0F38C7_REG_6,
1564   PREFIX_EVEX_0F38C8,
1565   PREFIX_EVEX_0F38CA,
1566   PREFIX_EVEX_0F38CB,
1567   PREFIX_EVEX_0F38CC,
1568   PREFIX_EVEX_0F38CD,
1569
1570   PREFIX_EVEX_0F3A00,
1571   PREFIX_EVEX_0F3A01,
1572   PREFIX_EVEX_0F3A03,
1573   PREFIX_EVEX_0F3A04,
1574   PREFIX_EVEX_0F3A05,
1575   PREFIX_EVEX_0F3A08,
1576   PREFIX_EVEX_0F3A09,
1577   PREFIX_EVEX_0F3A0A,
1578   PREFIX_EVEX_0F3A0B,
1579   PREFIX_EVEX_0F3A0F,
1580   PREFIX_EVEX_0F3A14,
1581   PREFIX_EVEX_0F3A15,
1582   PREFIX_EVEX_0F3A16,
1583   PREFIX_EVEX_0F3A17,
1584   PREFIX_EVEX_0F3A18,
1585   PREFIX_EVEX_0F3A19,
1586   PREFIX_EVEX_0F3A1A,
1587   PREFIX_EVEX_0F3A1B,
1588   PREFIX_EVEX_0F3A1D,
1589   PREFIX_EVEX_0F3A1E,
1590   PREFIX_EVEX_0F3A1F,
1591   PREFIX_EVEX_0F3A20,
1592   PREFIX_EVEX_0F3A21,
1593   PREFIX_EVEX_0F3A22,
1594   PREFIX_EVEX_0F3A23,
1595   PREFIX_EVEX_0F3A25,
1596   PREFIX_EVEX_0F3A26,
1597   PREFIX_EVEX_0F3A27,
1598   PREFIX_EVEX_0F3A38,
1599   PREFIX_EVEX_0F3A39,
1600   PREFIX_EVEX_0F3A3A,
1601   PREFIX_EVEX_0F3A3B,
1602   PREFIX_EVEX_0F3A3E,
1603   PREFIX_EVEX_0F3A3F,
1604   PREFIX_EVEX_0F3A42,
1605   PREFIX_EVEX_0F3A43,
1606   PREFIX_EVEX_0F3A50,
1607   PREFIX_EVEX_0F3A51,
1608   PREFIX_EVEX_0F3A54,
1609   PREFIX_EVEX_0F3A55,
1610   PREFIX_EVEX_0F3A56,
1611   PREFIX_EVEX_0F3A57,
1612   PREFIX_EVEX_0F3A66,
1613   PREFIX_EVEX_0F3A67
1614 };
1615
1616 enum
1617 {
1618   X86_64_06 = 0,
1619   X86_64_07,
1620   X86_64_0D,
1621   X86_64_16,
1622   X86_64_17,
1623   X86_64_1E,
1624   X86_64_1F,
1625   X86_64_27,
1626   X86_64_2F,
1627   X86_64_37,
1628   X86_64_3F,
1629   X86_64_60,
1630   X86_64_61,
1631   X86_64_62,
1632   X86_64_63,
1633   X86_64_6D,
1634   X86_64_6F,
1635   X86_64_9A,
1636   X86_64_C4,
1637   X86_64_C5,
1638   X86_64_CE,
1639   X86_64_D4,
1640   X86_64_D5,
1641   X86_64_EA,
1642   X86_64_0F01_REG_0,
1643   X86_64_0F01_REG_1,
1644   X86_64_0F01_REG_2,
1645   X86_64_0F01_REG_3
1646 };
1647
1648 enum
1649 {
1650   THREE_BYTE_0F38 = 0,
1651   THREE_BYTE_0F3A,
1652   THREE_BYTE_0F7A
1653 };
1654
1655 enum
1656 {
1657   XOP_08 = 0,
1658   XOP_09,
1659   XOP_0A
1660 };
1661
1662 enum
1663 {
1664   VEX_0F = 0,
1665   VEX_0F38,
1666   VEX_0F3A
1667 };
1668
1669 enum
1670 {
1671   EVEX_0F = 0,
1672   EVEX_0F38,
1673   EVEX_0F3A
1674 };
1675
1676 enum
1677 {
1678   VEX_LEN_0F10_P_1 = 0,
1679   VEX_LEN_0F10_P_3,
1680   VEX_LEN_0F11_P_1,
1681   VEX_LEN_0F11_P_3,
1682   VEX_LEN_0F12_P_0_M_0,
1683   VEX_LEN_0F12_P_0_M_1,
1684   VEX_LEN_0F12_P_2,
1685   VEX_LEN_0F13_M_0,
1686   VEX_LEN_0F16_P_0_M_0,
1687   VEX_LEN_0F16_P_0_M_1,
1688   VEX_LEN_0F16_P_2,
1689   VEX_LEN_0F17_M_0,
1690   VEX_LEN_0F2A_P_1,
1691   VEX_LEN_0F2A_P_3,
1692   VEX_LEN_0F2C_P_1,
1693   VEX_LEN_0F2C_P_3,
1694   VEX_LEN_0F2D_P_1,
1695   VEX_LEN_0F2D_P_3,
1696   VEX_LEN_0F2E_P_0,
1697   VEX_LEN_0F2E_P_2,
1698   VEX_LEN_0F2F_P_0,
1699   VEX_LEN_0F2F_P_2,
1700   VEX_LEN_0F41_P_0,
1701   VEX_LEN_0F41_P_2,
1702   VEX_LEN_0F42_P_0,
1703   VEX_LEN_0F42_P_2,
1704   VEX_LEN_0F44_P_0,
1705   VEX_LEN_0F44_P_2,
1706   VEX_LEN_0F45_P_0,
1707   VEX_LEN_0F45_P_2,
1708   VEX_LEN_0F46_P_0,
1709   VEX_LEN_0F46_P_2,
1710   VEX_LEN_0F47_P_0,
1711   VEX_LEN_0F47_P_2,
1712   VEX_LEN_0F4A_P_0,
1713   VEX_LEN_0F4A_P_2,
1714   VEX_LEN_0F4B_P_0,
1715   VEX_LEN_0F4B_P_2,
1716   VEX_LEN_0F51_P_1,
1717   VEX_LEN_0F51_P_3,
1718   VEX_LEN_0F52_P_1,
1719   VEX_LEN_0F53_P_1,
1720   VEX_LEN_0F58_P_1,
1721   VEX_LEN_0F58_P_3,
1722   VEX_LEN_0F59_P_1,
1723   VEX_LEN_0F59_P_3,
1724   VEX_LEN_0F5A_P_1,
1725   VEX_LEN_0F5A_P_3,
1726   VEX_LEN_0F5C_P_1,
1727   VEX_LEN_0F5C_P_3,
1728   VEX_LEN_0F5D_P_1,
1729   VEX_LEN_0F5D_P_3,
1730   VEX_LEN_0F5E_P_1,
1731   VEX_LEN_0F5E_P_3,
1732   VEX_LEN_0F5F_P_1,
1733   VEX_LEN_0F5F_P_3,
1734   VEX_LEN_0F6E_P_2,
1735   VEX_LEN_0F7E_P_1,
1736   VEX_LEN_0F7E_P_2,
1737   VEX_LEN_0F90_P_0,
1738   VEX_LEN_0F90_P_2,
1739   VEX_LEN_0F91_P_0,
1740   VEX_LEN_0F91_P_2,
1741   VEX_LEN_0F92_P_0,
1742   VEX_LEN_0F92_P_2,
1743   VEX_LEN_0F92_P_3,
1744   VEX_LEN_0F93_P_0,
1745   VEX_LEN_0F93_P_2,
1746   VEX_LEN_0F93_P_3,
1747   VEX_LEN_0F98_P_0,
1748   VEX_LEN_0F98_P_2,
1749   VEX_LEN_0F99_P_0,
1750   VEX_LEN_0F99_P_2,
1751   VEX_LEN_0FAE_R_2_M_0,
1752   VEX_LEN_0FAE_R_3_M_0,
1753   VEX_LEN_0FC2_P_1,
1754   VEX_LEN_0FC2_P_3,
1755   VEX_LEN_0FC4_P_2,
1756   VEX_LEN_0FC5_P_2,
1757   VEX_LEN_0FD6_P_2,
1758   VEX_LEN_0FF7_P_2,
1759   VEX_LEN_0F3816_P_2,
1760   VEX_LEN_0F3819_P_2,
1761   VEX_LEN_0F381A_P_2_M_0,
1762   VEX_LEN_0F3836_P_2,
1763   VEX_LEN_0F3841_P_2,
1764   VEX_LEN_0F385A_P_2_M_0,
1765   VEX_LEN_0F38DB_P_2,
1766   VEX_LEN_0F38DC_P_2,
1767   VEX_LEN_0F38DD_P_2,
1768   VEX_LEN_0F38DE_P_2,
1769   VEX_LEN_0F38DF_P_2,
1770   VEX_LEN_0F38F2_P_0,
1771   VEX_LEN_0F38F3_R_1_P_0,
1772   VEX_LEN_0F38F3_R_2_P_0,
1773   VEX_LEN_0F38F3_R_3_P_0,
1774   VEX_LEN_0F38F5_P_0,
1775   VEX_LEN_0F38F5_P_1,
1776   VEX_LEN_0F38F5_P_3,
1777   VEX_LEN_0F38F6_P_3,
1778   VEX_LEN_0F38F7_P_0,
1779   VEX_LEN_0F38F7_P_1,
1780   VEX_LEN_0F38F7_P_2,
1781   VEX_LEN_0F38F7_P_3,
1782   VEX_LEN_0F3A00_P_2,
1783   VEX_LEN_0F3A01_P_2,
1784   VEX_LEN_0F3A06_P_2,
1785   VEX_LEN_0F3A0A_P_2,
1786   VEX_LEN_0F3A0B_P_2,
1787   VEX_LEN_0F3A14_P_2,
1788   VEX_LEN_0F3A15_P_2,
1789   VEX_LEN_0F3A16_P_2,
1790   VEX_LEN_0F3A17_P_2,
1791   VEX_LEN_0F3A18_P_2,
1792   VEX_LEN_0F3A19_P_2,
1793   VEX_LEN_0F3A20_P_2,
1794   VEX_LEN_0F3A21_P_2,
1795   VEX_LEN_0F3A22_P_2,
1796   VEX_LEN_0F3A30_P_2,
1797   VEX_LEN_0F3A31_P_2,
1798   VEX_LEN_0F3A32_P_2,
1799   VEX_LEN_0F3A33_P_2,
1800   VEX_LEN_0F3A38_P_2,
1801   VEX_LEN_0F3A39_P_2,
1802   VEX_LEN_0F3A41_P_2,
1803   VEX_LEN_0F3A44_P_2,
1804   VEX_LEN_0F3A46_P_2,
1805   VEX_LEN_0F3A60_P_2,
1806   VEX_LEN_0F3A61_P_2,
1807   VEX_LEN_0F3A62_P_2,
1808   VEX_LEN_0F3A63_P_2,
1809   VEX_LEN_0F3A6A_P_2,
1810   VEX_LEN_0F3A6B_P_2,
1811   VEX_LEN_0F3A6E_P_2,
1812   VEX_LEN_0F3A6F_P_2,
1813   VEX_LEN_0F3A7A_P_2,
1814   VEX_LEN_0F3A7B_P_2,
1815   VEX_LEN_0F3A7E_P_2,
1816   VEX_LEN_0F3A7F_P_2,
1817   VEX_LEN_0F3ADF_P_2,
1818   VEX_LEN_0F3AF0_P_3,
1819   VEX_LEN_0FXOP_08_CC,
1820   VEX_LEN_0FXOP_08_CD,
1821   VEX_LEN_0FXOP_08_CE,
1822   VEX_LEN_0FXOP_08_CF,
1823   VEX_LEN_0FXOP_08_EC,
1824   VEX_LEN_0FXOP_08_ED,
1825   VEX_LEN_0FXOP_08_EE,
1826   VEX_LEN_0FXOP_08_EF,
1827   VEX_LEN_0FXOP_09_80,
1828   VEX_LEN_0FXOP_09_81
1829 };
1830
1831 enum
1832 {
1833   VEX_W_0F10_P_0 = 0,
1834   VEX_W_0F10_P_1,
1835   VEX_W_0F10_P_2,
1836   VEX_W_0F10_P_3,
1837   VEX_W_0F11_P_0,
1838   VEX_W_0F11_P_1,
1839   VEX_W_0F11_P_2,
1840   VEX_W_0F11_P_3,
1841   VEX_W_0F12_P_0_M_0,
1842   VEX_W_0F12_P_0_M_1,
1843   VEX_W_0F12_P_1,
1844   VEX_W_0F12_P_2,
1845   VEX_W_0F12_P_3,
1846   VEX_W_0F13_M_0,
1847   VEX_W_0F14,
1848   VEX_W_0F15,
1849   VEX_W_0F16_P_0_M_0,
1850   VEX_W_0F16_P_0_M_1,
1851   VEX_W_0F16_P_1,
1852   VEX_W_0F16_P_2,
1853   VEX_W_0F17_M_0,
1854   VEX_W_0F28,
1855   VEX_W_0F29,
1856   VEX_W_0F2B_M_0,
1857   VEX_W_0F2E_P_0,
1858   VEX_W_0F2E_P_2,
1859   VEX_W_0F2F_P_0,
1860   VEX_W_0F2F_P_2,
1861   VEX_W_0F41_P_0_LEN_1,
1862   VEX_W_0F41_P_2_LEN_1,
1863   VEX_W_0F42_P_0_LEN_1,
1864   VEX_W_0F42_P_2_LEN_1,
1865   VEX_W_0F44_P_0_LEN_0,
1866   VEX_W_0F44_P_2_LEN_0,
1867   VEX_W_0F45_P_0_LEN_1,
1868   VEX_W_0F45_P_2_LEN_1,
1869   VEX_W_0F46_P_0_LEN_1,
1870   VEX_W_0F46_P_2_LEN_1,
1871   VEX_W_0F47_P_0_LEN_1,
1872   VEX_W_0F47_P_2_LEN_1,
1873   VEX_W_0F4A_P_0_LEN_1,
1874   VEX_W_0F4A_P_2_LEN_1,
1875   VEX_W_0F4B_P_0_LEN_1,
1876   VEX_W_0F4B_P_2_LEN_1,
1877   VEX_W_0F50_M_0,
1878   VEX_W_0F51_P_0,
1879   VEX_W_0F51_P_1,
1880   VEX_W_0F51_P_2,
1881   VEX_W_0F51_P_3,
1882   VEX_W_0F52_P_0,
1883   VEX_W_0F52_P_1,
1884   VEX_W_0F53_P_0,
1885   VEX_W_0F53_P_1,
1886   VEX_W_0F58_P_0,
1887   VEX_W_0F58_P_1,
1888   VEX_W_0F58_P_2,
1889   VEX_W_0F58_P_3,
1890   VEX_W_0F59_P_0,
1891   VEX_W_0F59_P_1,
1892   VEX_W_0F59_P_2,
1893   VEX_W_0F59_P_3,
1894   VEX_W_0F5A_P_0,
1895   VEX_W_0F5A_P_1,
1896   VEX_W_0F5A_P_3,
1897   VEX_W_0F5B_P_0,
1898   VEX_W_0F5B_P_1,
1899   VEX_W_0F5B_P_2,
1900   VEX_W_0F5C_P_0,
1901   VEX_W_0F5C_P_1,
1902   VEX_W_0F5C_P_2,
1903   VEX_W_0F5C_P_3,
1904   VEX_W_0F5D_P_0,
1905   VEX_W_0F5D_P_1,
1906   VEX_W_0F5D_P_2,
1907   VEX_W_0F5D_P_3,
1908   VEX_W_0F5E_P_0,
1909   VEX_W_0F5E_P_1,
1910   VEX_W_0F5E_P_2,
1911   VEX_W_0F5E_P_3,
1912   VEX_W_0F5F_P_0,
1913   VEX_W_0F5F_P_1,
1914   VEX_W_0F5F_P_2,
1915   VEX_W_0F5F_P_3,
1916   VEX_W_0F60_P_2,
1917   VEX_W_0F61_P_2,
1918   VEX_W_0F62_P_2,
1919   VEX_W_0F63_P_2,
1920   VEX_W_0F64_P_2,
1921   VEX_W_0F65_P_2,
1922   VEX_W_0F66_P_2,
1923   VEX_W_0F67_P_2,
1924   VEX_W_0F68_P_2,
1925   VEX_W_0F69_P_2,
1926   VEX_W_0F6A_P_2,
1927   VEX_W_0F6B_P_2,
1928   VEX_W_0F6C_P_2,
1929   VEX_W_0F6D_P_2,
1930   VEX_W_0F6F_P_1,
1931   VEX_W_0F6F_P_2,
1932   VEX_W_0F70_P_1,
1933   VEX_W_0F70_P_2,
1934   VEX_W_0F70_P_3,
1935   VEX_W_0F71_R_2_P_2,
1936   VEX_W_0F71_R_4_P_2,
1937   VEX_W_0F71_R_6_P_2,
1938   VEX_W_0F72_R_2_P_2,
1939   VEX_W_0F72_R_4_P_2,
1940   VEX_W_0F72_R_6_P_2,
1941   VEX_W_0F73_R_2_P_2,
1942   VEX_W_0F73_R_3_P_2,
1943   VEX_W_0F73_R_6_P_2,
1944   VEX_W_0F73_R_7_P_2,
1945   VEX_W_0F74_P_2,
1946   VEX_W_0F75_P_2,
1947   VEX_W_0F76_P_2,
1948   VEX_W_0F77_P_0,
1949   VEX_W_0F7C_P_2,
1950   VEX_W_0F7C_P_3,
1951   VEX_W_0F7D_P_2,
1952   VEX_W_0F7D_P_3,
1953   VEX_W_0F7E_P_1,
1954   VEX_W_0F7F_P_1,
1955   VEX_W_0F7F_P_2,
1956   VEX_W_0F90_P_0_LEN_0,
1957   VEX_W_0F90_P_2_LEN_0,
1958   VEX_W_0F91_P_0_LEN_0,
1959   VEX_W_0F91_P_2_LEN_0,
1960   VEX_W_0F92_P_0_LEN_0,
1961   VEX_W_0F92_P_2_LEN_0,
1962   VEX_W_0F92_P_3_LEN_0,
1963   VEX_W_0F93_P_0_LEN_0,
1964   VEX_W_0F93_P_2_LEN_0,
1965   VEX_W_0F93_P_3_LEN_0,
1966   VEX_W_0F98_P_0_LEN_0,
1967   VEX_W_0F98_P_2_LEN_0,
1968   VEX_W_0F99_P_0_LEN_0,
1969   VEX_W_0F99_P_2_LEN_0,
1970   VEX_W_0FAE_R_2_M_0,
1971   VEX_W_0FAE_R_3_M_0,
1972   VEX_W_0FC2_P_0,
1973   VEX_W_0FC2_P_1,
1974   VEX_W_0FC2_P_2,
1975   VEX_W_0FC2_P_3,
1976   VEX_W_0FC4_P_2,
1977   VEX_W_0FC5_P_2,
1978   VEX_W_0FD0_P_2,
1979   VEX_W_0FD0_P_3,
1980   VEX_W_0FD1_P_2,
1981   VEX_W_0FD2_P_2,
1982   VEX_W_0FD3_P_2,
1983   VEX_W_0FD4_P_2,
1984   VEX_W_0FD5_P_2,
1985   VEX_W_0FD6_P_2,
1986   VEX_W_0FD7_P_2_M_1,
1987   VEX_W_0FD8_P_2,
1988   VEX_W_0FD9_P_2,
1989   VEX_W_0FDA_P_2,
1990   VEX_W_0FDB_P_2,
1991   VEX_W_0FDC_P_2,
1992   VEX_W_0FDD_P_2,
1993   VEX_W_0FDE_P_2,
1994   VEX_W_0FDF_P_2,
1995   VEX_W_0FE0_P_2,
1996   VEX_W_0FE1_P_2,
1997   VEX_W_0FE2_P_2,
1998   VEX_W_0FE3_P_2,
1999   VEX_W_0FE4_P_2,
2000   VEX_W_0FE5_P_2,
2001   VEX_W_0FE6_P_1,
2002   VEX_W_0FE6_P_2,
2003   VEX_W_0FE6_P_3,
2004   VEX_W_0FE7_P_2_M_0,
2005   VEX_W_0FE8_P_2,
2006   VEX_W_0FE9_P_2,
2007   VEX_W_0FEA_P_2,
2008   VEX_W_0FEB_P_2,
2009   VEX_W_0FEC_P_2,
2010   VEX_W_0FED_P_2,
2011   VEX_W_0FEE_P_2,
2012   VEX_W_0FEF_P_2,
2013   VEX_W_0FF0_P_3_M_0,
2014   VEX_W_0FF1_P_2,
2015   VEX_W_0FF2_P_2,
2016   VEX_W_0FF3_P_2,
2017   VEX_W_0FF4_P_2,
2018   VEX_W_0FF5_P_2,
2019   VEX_W_0FF6_P_2,
2020   VEX_W_0FF7_P_2,
2021   VEX_W_0FF8_P_2,
2022   VEX_W_0FF9_P_2,
2023   VEX_W_0FFA_P_2,
2024   VEX_W_0FFB_P_2,
2025   VEX_W_0FFC_P_2,
2026   VEX_W_0FFD_P_2,
2027   VEX_W_0FFE_P_2,
2028   VEX_W_0F3800_P_2,
2029   VEX_W_0F3801_P_2,
2030   VEX_W_0F3802_P_2,
2031   VEX_W_0F3803_P_2,
2032   VEX_W_0F3804_P_2,
2033   VEX_W_0F3805_P_2,
2034   VEX_W_0F3806_P_2,
2035   VEX_W_0F3807_P_2,
2036   VEX_W_0F3808_P_2,
2037   VEX_W_0F3809_P_2,
2038   VEX_W_0F380A_P_2,
2039   VEX_W_0F380B_P_2,
2040   VEX_W_0F380C_P_2,
2041   VEX_W_0F380D_P_2,
2042   VEX_W_0F380E_P_2,
2043   VEX_W_0F380F_P_2,
2044   VEX_W_0F3816_P_2,
2045   VEX_W_0F3817_P_2,
2046   VEX_W_0F3818_P_2,
2047   VEX_W_0F3819_P_2,
2048   VEX_W_0F381A_P_2_M_0,
2049   VEX_W_0F381C_P_2,
2050   VEX_W_0F381D_P_2,
2051   VEX_W_0F381E_P_2,
2052   VEX_W_0F3820_P_2,
2053   VEX_W_0F3821_P_2,
2054   VEX_W_0F3822_P_2,
2055   VEX_W_0F3823_P_2,
2056   VEX_W_0F3824_P_2,
2057   VEX_W_0F3825_P_2,
2058   VEX_W_0F3828_P_2,
2059   VEX_W_0F3829_P_2,
2060   VEX_W_0F382A_P_2_M_0,
2061   VEX_W_0F382B_P_2,
2062   VEX_W_0F382C_P_2_M_0,
2063   VEX_W_0F382D_P_2_M_0,
2064   VEX_W_0F382E_P_2_M_0,
2065   VEX_W_0F382F_P_2_M_0,
2066   VEX_W_0F3830_P_2,
2067   VEX_W_0F3831_P_2,
2068   VEX_W_0F3832_P_2,
2069   VEX_W_0F3833_P_2,
2070   VEX_W_0F3834_P_2,
2071   VEX_W_0F3835_P_2,
2072   VEX_W_0F3836_P_2,
2073   VEX_W_0F3837_P_2,
2074   VEX_W_0F3838_P_2,
2075   VEX_W_0F3839_P_2,
2076   VEX_W_0F383A_P_2,
2077   VEX_W_0F383B_P_2,
2078   VEX_W_0F383C_P_2,
2079   VEX_W_0F383D_P_2,
2080   VEX_W_0F383E_P_2,
2081   VEX_W_0F383F_P_2,
2082   VEX_W_0F3840_P_2,
2083   VEX_W_0F3841_P_2,
2084   VEX_W_0F3846_P_2,
2085   VEX_W_0F3858_P_2,
2086   VEX_W_0F3859_P_2,
2087   VEX_W_0F385A_P_2_M_0,
2088   VEX_W_0F3878_P_2,
2089   VEX_W_0F3879_P_2,
2090   VEX_W_0F38DB_P_2,
2091   VEX_W_0F38DC_P_2,
2092   VEX_W_0F38DD_P_2,
2093   VEX_W_0F38DE_P_2,
2094   VEX_W_0F38DF_P_2,
2095   VEX_W_0F3A00_P_2,
2096   VEX_W_0F3A01_P_2,
2097   VEX_W_0F3A02_P_2,
2098   VEX_W_0F3A04_P_2,
2099   VEX_W_0F3A05_P_2,
2100   VEX_W_0F3A06_P_2,
2101   VEX_W_0F3A08_P_2,
2102   VEX_W_0F3A09_P_2,
2103   VEX_W_0F3A0A_P_2,
2104   VEX_W_0F3A0B_P_2,
2105   VEX_W_0F3A0C_P_2,
2106   VEX_W_0F3A0D_P_2,
2107   VEX_W_0F3A0E_P_2,
2108   VEX_W_0F3A0F_P_2,
2109   VEX_W_0F3A14_P_2,
2110   VEX_W_0F3A15_P_2,
2111   VEX_W_0F3A18_P_2,
2112   VEX_W_0F3A19_P_2,
2113   VEX_W_0F3A20_P_2,
2114   VEX_W_0F3A21_P_2,
2115   VEX_W_0F3A30_P_2_LEN_0,
2116   VEX_W_0F3A31_P_2_LEN_0,
2117   VEX_W_0F3A32_P_2_LEN_0,
2118   VEX_W_0F3A33_P_2_LEN_0,
2119   VEX_W_0F3A38_P_2,
2120   VEX_W_0F3A39_P_2,
2121   VEX_W_0F3A40_P_2,
2122   VEX_W_0F3A41_P_2,
2123   VEX_W_0F3A42_P_2,
2124   VEX_W_0F3A44_P_2,
2125   VEX_W_0F3A46_P_2,
2126   VEX_W_0F3A48_P_2,
2127   VEX_W_0F3A49_P_2,
2128   VEX_W_0F3A4A_P_2,
2129   VEX_W_0F3A4B_P_2,
2130   VEX_W_0F3A4C_P_2,
2131   VEX_W_0F3A60_P_2,
2132   VEX_W_0F3A61_P_2,
2133   VEX_W_0F3A62_P_2,
2134   VEX_W_0F3A63_P_2,
2135   VEX_W_0F3ADF_P_2,
2136
2137   EVEX_W_0F10_P_0,
2138   EVEX_W_0F10_P_1_M_0,
2139   EVEX_W_0F10_P_1_M_1,
2140   EVEX_W_0F10_P_2,
2141   EVEX_W_0F10_P_3_M_0,
2142   EVEX_W_0F10_P_3_M_1,
2143   EVEX_W_0F11_P_0,
2144   EVEX_W_0F11_P_1_M_0,
2145   EVEX_W_0F11_P_1_M_1,
2146   EVEX_W_0F11_P_2,
2147   EVEX_W_0F11_P_3_M_0,
2148   EVEX_W_0F11_P_3_M_1,
2149   EVEX_W_0F12_P_0_M_0,
2150   EVEX_W_0F12_P_0_M_1,
2151   EVEX_W_0F12_P_1,
2152   EVEX_W_0F12_P_2,
2153   EVEX_W_0F12_P_3,
2154   EVEX_W_0F13_P_0,
2155   EVEX_W_0F13_P_2,
2156   EVEX_W_0F14_P_0,
2157   EVEX_W_0F14_P_2,
2158   EVEX_W_0F15_P_0,
2159   EVEX_W_0F15_P_2,
2160   EVEX_W_0F16_P_0_M_0,
2161   EVEX_W_0F16_P_0_M_1,
2162   EVEX_W_0F16_P_1,
2163   EVEX_W_0F16_P_2,
2164   EVEX_W_0F17_P_0,
2165   EVEX_W_0F17_P_2,
2166   EVEX_W_0F28_P_0,
2167   EVEX_W_0F28_P_2,
2168   EVEX_W_0F29_P_0,
2169   EVEX_W_0F29_P_2,
2170   EVEX_W_0F2A_P_1,
2171   EVEX_W_0F2A_P_3,
2172   EVEX_W_0F2B_P_0,
2173   EVEX_W_0F2B_P_2,
2174   EVEX_W_0F2E_P_0,
2175   EVEX_W_0F2E_P_2,
2176   EVEX_W_0F2F_P_0,
2177   EVEX_W_0F2F_P_2,
2178   EVEX_W_0F51_P_0,
2179   EVEX_W_0F51_P_1,
2180   EVEX_W_0F51_P_2,
2181   EVEX_W_0F51_P_3,
2182   EVEX_W_0F54_P_0,
2183   EVEX_W_0F54_P_2,
2184   EVEX_W_0F55_P_0,
2185   EVEX_W_0F55_P_2,
2186   EVEX_W_0F56_P_0,
2187   EVEX_W_0F56_P_2,
2188   EVEX_W_0F57_P_0,
2189   EVEX_W_0F57_P_2,
2190   EVEX_W_0F58_P_0,
2191   EVEX_W_0F58_P_1,
2192   EVEX_W_0F58_P_2,
2193   EVEX_W_0F58_P_3,
2194   EVEX_W_0F59_P_0,
2195   EVEX_W_0F59_P_1,
2196   EVEX_W_0F59_P_2,
2197   EVEX_W_0F59_P_3,
2198   EVEX_W_0F5A_P_0,
2199   EVEX_W_0F5A_P_1,
2200   EVEX_W_0F5A_P_2,
2201   EVEX_W_0F5A_P_3,
2202   EVEX_W_0F5B_P_0,
2203   EVEX_W_0F5B_P_1,
2204   EVEX_W_0F5B_P_2,
2205   EVEX_W_0F5C_P_0,
2206   EVEX_W_0F5C_P_1,
2207   EVEX_W_0F5C_P_2,
2208   EVEX_W_0F5C_P_3,
2209   EVEX_W_0F5D_P_0,
2210   EVEX_W_0F5D_P_1,
2211   EVEX_W_0F5D_P_2,
2212   EVEX_W_0F5D_P_3,
2213   EVEX_W_0F5E_P_0,
2214   EVEX_W_0F5E_P_1,
2215   EVEX_W_0F5E_P_2,
2216   EVEX_W_0F5E_P_3,
2217   EVEX_W_0F5F_P_0,
2218   EVEX_W_0F5F_P_1,
2219   EVEX_W_0F5F_P_2,
2220   EVEX_W_0F5F_P_3,
2221   EVEX_W_0F62_P_2,
2222   EVEX_W_0F66_P_2,
2223   EVEX_W_0F6A_P_2,
2224   EVEX_W_0F6B_P_2,
2225   EVEX_W_0F6C_P_2,
2226   EVEX_W_0F6D_P_2,
2227   EVEX_W_0F6E_P_2,
2228   EVEX_W_0F6F_P_1,
2229   EVEX_W_0F6F_P_2,
2230   EVEX_W_0F6F_P_3,
2231   EVEX_W_0F70_P_2,
2232   EVEX_W_0F72_R_2_P_2,
2233   EVEX_W_0F72_R_6_P_2,
2234   EVEX_W_0F73_R_2_P_2,
2235   EVEX_W_0F73_R_6_P_2,
2236   EVEX_W_0F76_P_2,
2237   EVEX_W_0F78_P_0,
2238   EVEX_W_0F78_P_2,
2239   EVEX_W_0F79_P_0,
2240   EVEX_W_0F79_P_2,
2241   EVEX_W_0F7A_P_1,
2242   EVEX_W_0F7A_P_2,
2243   EVEX_W_0F7A_P_3,
2244   EVEX_W_0F7B_P_1,
2245   EVEX_W_0F7B_P_2,
2246   EVEX_W_0F7B_P_3,
2247   EVEX_W_0F7E_P_1,
2248   EVEX_W_0F7E_P_2,
2249   EVEX_W_0F7F_P_1,
2250   EVEX_W_0F7F_P_2,
2251   EVEX_W_0F7F_P_3,
2252   EVEX_W_0FC2_P_0,
2253   EVEX_W_0FC2_P_1,
2254   EVEX_W_0FC2_P_2,
2255   EVEX_W_0FC2_P_3,
2256   EVEX_W_0FC6_P_0,
2257   EVEX_W_0FC6_P_2,
2258   EVEX_W_0FD2_P_2,
2259   EVEX_W_0FD3_P_2,
2260   EVEX_W_0FD4_P_2,
2261   EVEX_W_0FD6_P_2,
2262   EVEX_W_0FE6_P_1,
2263   EVEX_W_0FE6_P_2,
2264   EVEX_W_0FE6_P_3,
2265   EVEX_W_0FE7_P_2,
2266   EVEX_W_0FF2_P_2,
2267   EVEX_W_0FF3_P_2,
2268   EVEX_W_0FF4_P_2,
2269   EVEX_W_0FFA_P_2,
2270   EVEX_W_0FFB_P_2,
2271   EVEX_W_0FFE_P_2,
2272   EVEX_W_0F380C_P_2,
2273   EVEX_W_0F380D_P_2,
2274   EVEX_W_0F3810_P_1,
2275   EVEX_W_0F3810_P_2,
2276   EVEX_W_0F3811_P_1,
2277   EVEX_W_0F3811_P_2,
2278   EVEX_W_0F3812_P_1,
2279   EVEX_W_0F3812_P_2,
2280   EVEX_W_0F3813_P_1,
2281   EVEX_W_0F3813_P_2,
2282   EVEX_W_0F3814_P_1,
2283   EVEX_W_0F3815_P_1,
2284   EVEX_W_0F3818_P_2,
2285   EVEX_W_0F3819_P_2,
2286   EVEX_W_0F381A_P_2,
2287   EVEX_W_0F381B_P_2,
2288   EVEX_W_0F381E_P_2,
2289   EVEX_W_0F381F_P_2,
2290   EVEX_W_0F3820_P_1,
2291   EVEX_W_0F3821_P_1,
2292   EVEX_W_0F3822_P_1,
2293   EVEX_W_0F3823_P_1,
2294   EVEX_W_0F3824_P_1,
2295   EVEX_W_0F3825_P_1,
2296   EVEX_W_0F3825_P_2,
2297   EVEX_W_0F3826_P_1,
2298   EVEX_W_0F3826_P_2,
2299   EVEX_W_0F3828_P_1,
2300   EVEX_W_0F3828_P_2,
2301   EVEX_W_0F3829_P_1,
2302   EVEX_W_0F3829_P_2,
2303   EVEX_W_0F382A_P_1,
2304   EVEX_W_0F382A_P_2,
2305   EVEX_W_0F382B_P_2,
2306   EVEX_W_0F3830_P_1,
2307   EVEX_W_0F3831_P_1,
2308   EVEX_W_0F3832_P_1,
2309   EVEX_W_0F3833_P_1,
2310   EVEX_W_0F3834_P_1,
2311   EVEX_W_0F3835_P_1,
2312   EVEX_W_0F3835_P_2,
2313   EVEX_W_0F3837_P_2,
2314   EVEX_W_0F3838_P_1,
2315   EVEX_W_0F3839_P_1,
2316   EVEX_W_0F383A_P_1,
2317   EVEX_W_0F3840_P_2,
2318   EVEX_W_0F3858_P_2,
2319   EVEX_W_0F3859_P_2,
2320   EVEX_W_0F385A_P_2,
2321   EVEX_W_0F385B_P_2,
2322   EVEX_W_0F3866_P_2,
2323   EVEX_W_0F3875_P_2,
2324   EVEX_W_0F3878_P_2,
2325   EVEX_W_0F3879_P_2,
2326   EVEX_W_0F387A_P_2,
2327   EVEX_W_0F387B_P_2,
2328   EVEX_W_0F387D_P_2,
2329   EVEX_W_0F3883_P_2,
2330   EVEX_W_0F388D_P_2,
2331   EVEX_W_0F3891_P_2,
2332   EVEX_W_0F3893_P_2,
2333   EVEX_W_0F38A1_P_2,
2334   EVEX_W_0F38A3_P_2,
2335   EVEX_W_0F38C7_R_1_P_2,
2336   EVEX_W_0F38C7_R_2_P_2,
2337   EVEX_W_0F38C7_R_5_P_2,
2338   EVEX_W_0F38C7_R_6_P_2,
2339
2340   EVEX_W_0F3A00_P_2,
2341   EVEX_W_0F3A01_P_2,
2342   EVEX_W_0F3A04_P_2,
2343   EVEX_W_0F3A05_P_2,
2344   EVEX_W_0F3A08_P_2,
2345   EVEX_W_0F3A09_P_2,
2346   EVEX_W_0F3A0A_P_2,
2347   EVEX_W_0F3A0B_P_2,
2348   EVEX_W_0F3A16_P_2,
2349   EVEX_W_0F3A18_P_2,
2350   EVEX_W_0F3A19_P_2,
2351   EVEX_W_0F3A1A_P_2,
2352   EVEX_W_0F3A1B_P_2,
2353   EVEX_W_0F3A1D_P_2,
2354   EVEX_W_0F3A21_P_2,
2355   EVEX_W_0F3A22_P_2,
2356   EVEX_W_0F3A23_P_2,
2357   EVEX_W_0F3A38_P_2,
2358   EVEX_W_0F3A39_P_2,
2359   EVEX_W_0F3A3A_P_2,
2360   EVEX_W_0F3A3B_P_2,
2361   EVEX_W_0F3A3E_P_2,
2362   EVEX_W_0F3A3F_P_2,
2363   EVEX_W_0F3A42_P_2,
2364   EVEX_W_0F3A43_P_2,
2365   EVEX_W_0F3A50_P_2,
2366   EVEX_W_0F3A51_P_2,
2367   EVEX_W_0F3A56_P_2,
2368   EVEX_W_0F3A57_P_2,
2369   EVEX_W_0F3A66_P_2,
2370   EVEX_W_0F3A67_P_2
2371 };
2372
2373 typedef void (*op_rtn) (int bytemode, int sizeflag);
2374
2375 struct dis386 {
2376   const char *name;
2377   struct
2378     {
2379       op_rtn rtn;
2380       int bytemode;
2381     } op[MAX_OPERANDS];
2382   unsigned int prefix_requirement;
2383 };
2384
2385 /* Upper case letters in the instruction names here are macros.
2386    'A' => print 'b' if no register operands or suffix_always is true
2387    'B' => print 'b' if suffix_always is true
2388    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2389           size prefix
2390    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2391           suffix_always is true
2392    'E' => print 'e' if 32-bit form of jcxz
2393    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2394    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2395    'H' => print ",pt" or ",pn" branch hint
2396    'I' => honor following macro letter even in Intel mode (implemented only
2397           for some of the macro letters)
2398    'J' => print 'l'
2399    'K' => print 'd' or 'q' if rex prefix is present.
2400    'L' => print 'l' if suffix_always is true
2401    'M' => print 'r' if intel_mnemonic is false.
2402    'N' => print 'n' if instruction has no wait "prefix"
2403    'O' => print 'd' or 'o' (or 'q' in Intel mode)
2404    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2405           or suffix_always is true.  print 'q' if rex prefix is present.
2406    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2407           is true
2408    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2409    'S' => print 'w', 'l' or 'q' if suffix_always is true
2410    'T' => print 'q' in 64bit mode and behave as 'P' otherwise
2411    'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
2412    'V' => print 'q' in 64bit mode and behave as 'S' otherwise
2413    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2414    'X' => print 's', 'd' depending on data16 prefix (for XMM)
2415    'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
2416           suffix_always is true.
2417    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2418    '!' => change condition from true to false or from false to true.
2419    '%' => add 1 upper case letter to the macro.
2420
2421    2 upper case letter macros:
2422    "XY" => print 'x' or 'y' if no register operands or suffix_always
2423            is true.
2424    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2425    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2426            or suffix_always is true
2427    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2428    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2429    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2430    "LW" => print 'd', 'q' depending on the VEX.W bit
2431    "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2432            an operand size prefix, or suffix_always is true.  print
2433            'q' if rex prefix is present.
2434
2435    Many of the above letters print nothing in Intel mode.  See "putop"
2436    for the details.
2437
2438    Braces '{' and '}', and vertical bars '|', indicate alternative
2439    mnemonic strings for AT&T and Intel.  */
2440
2441 static const struct dis386 dis386[] = {
2442   /* 00 */
2443   { "addB",             { Ebh1, Gb }, 0 },
2444   { "addS",             { Evh1, Gv }, 0 },
2445   { "addB",             { Gb, EbS }, 0 },
2446   { "addS",             { Gv, EvS }, 0 },
2447   { "addB",             { AL, Ib }, 0 },
2448   { "addS",             { eAX, Iv }, 0 },
2449   { X86_64_TABLE (X86_64_06) },
2450   { X86_64_TABLE (X86_64_07) },
2451   /* 08 */
2452   { "orB",              { Ebh1, Gb }, 0 },
2453   { "orS",              { Evh1, Gv }, 0 },
2454   { "orB",              { Gb, EbS }, 0 },
2455   { "orS",              { Gv, EvS }, 0 },
2456   { "orB",              { AL, Ib }, 0 },
2457   { "orS",              { eAX, Iv }, 0 },
2458   { X86_64_TABLE (X86_64_0D) },
2459   { Bad_Opcode },       /* 0x0f extended opcode escape */
2460   /* 10 */
2461   { "adcB",             { Ebh1, Gb }, 0 },
2462   { "adcS",             { Evh1, Gv }, 0 },
2463   { "adcB",             { Gb, EbS }, 0 },
2464   { "adcS",             { Gv, EvS }, 0 },
2465   { "adcB",             { AL, Ib }, 0 },
2466   { "adcS",             { eAX, Iv }, 0 },
2467   { X86_64_TABLE (X86_64_16) },
2468   { X86_64_TABLE (X86_64_17) },
2469   /* 18 */
2470   { "sbbB",             { Ebh1, Gb }, 0 },
2471   { "sbbS",             { Evh1, Gv }, 0 },
2472   { "sbbB",             { Gb, EbS }, 0 },
2473   { "sbbS",             { Gv, EvS }, 0 },
2474   { "sbbB",             { AL, Ib }, 0 },
2475   { "sbbS",             { eAX, Iv }, 0 },
2476   { X86_64_TABLE (X86_64_1E) },
2477   { X86_64_TABLE (X86_64_1F) },
2478   /* 20 */
2479   { "andB",             { Ebh1, Gb }, 0 },
2480   { "andS",             { Evh1, Gv }, 0 },
2481   { "andB",             { Gb, EbS }, 0 },
2482   { "andS",             { Gv, EvS }, 0 },
2483   { "andB",             { AL, Ib }, 0 },
2484   { "andS",             { eAX, Iv }, 0 },
2485   { Bad_Opcode },       /* SEG ES prefix */
2486   { X86_64_TABLE (X86_64_27) },
2487   /* 28 */
2488   { "subB",             { Ebh1, Gb }, 0 },
2489   { "subS",             { Evh1, Gv }, 0 },
2490   { "subB",             { Gb, EbS }, 0 },
2491   { "subS",             { Gv, EvS }, 0 },
2492   { "subB",             { AL, Ib }, 0 },
2493   { "subS",             { eAX, Iv }, 0 },
2494   { Bad_Opcode },       /* SEG CS prefix */
2495   { X86_64_TABLE (X86_64_2F) },
2496   /* 30 */
2497   { "xorB",             { Ebh1, Gb }, 0 },
2498   { "xorS",             { Evh1, Gv }, 0 },
2499   { "xorB",             { Gb, EbS }, 0 },
2500   { "xorS",             { Gv, EvS }, 0 },
2501   { "xorB",             { AL, Ib }, 0 },
2502   { "xorS",             { eAX, Iv }, 0 },
2503   { Bad_Opcode },       /* SEG SS prefix */
2504   { X86_64_TABLE (X86_64_37) },
2505   /* 38 */
2506   { "cmpB",             { Eb, Gb }, 0 },
2507   { "cmpS",             { Ev, Gv }, 0 },
2508   { "cmpB",             { Gb, EbS }, 0 },
2509   { "cmpS",             { Gv, EvS }, 0 },
2510   { "cmpB",             { AL, Ib }, 0 },
2511   { "cmpS",             { eAX, Iv }, 0 },
2512   { Bad_Opcode },       /* SEG DS prefix */
2513   { X86_64_TABLE (X86_64_3F) },
2514   /* 40 */
2515   { "inc{S|}",          { RMeAX }, 0 },
2516   { "inc{S|}",          { RMeCX }, 0 },
2517   { "inc{S|}",          { RMeDX }, 0 },
2518   { "inc{S|}",          { RMeBX }, 0 },
2519   { "inc{S|}",          { RMeSP }, 0 },
2520   { "inc{S|}",          { RMeBP }, 0 },
2521   { "inc{S|}",          { RMeSI }, 0 },
2522   { "inc{S|}",          { RMeDI }, 0 },
2523   /* 48 */
2524   { "dec{S|}",          { RMeAX }, 0 },
2525   { "dec{S|}",          { RMeCX }, 0 },
2526   { "dec{S|}",          { RMeDX }, 0 },
2527   { "dec{S|}",          { RMeBX }, 0 },
2528   { "dec{S|}",          { RMeSP }, 0 },
2529   { "dec{S|}",          { RMeBP }, 0 },
2530   { "dec{S|}",          { RMeSI }, 0 },
2531   { "dec{S|}",          { RMeDI }, 0 },
2532   /* 50 */
2533   { "pushV",            { RMrAX }, 0 },
2534   { "pushV",            { RMrCX }, 0 },
2535   { "pushV",            { RMrDX }, 0 },
2536   { "pushV",            { RMrBX }, 0 },
2537   { "pushV",            { RMrSP }, 0 },
2538   { "pushV",            { RMrBP }, 0 },
2539   { "pushV",            { RMrSI }, 0 },
2540   { "pushV",            { RMrDI }, 0 },
2541   /* 58 */
2542   { "popV",             { RMrAX }, 0 },
2543   { "popV",             { RMrCX }, 0 },
2544   { "popV",             { RMrDX }, 0 },
2545   { "popV",             { RMrBX }, 0 },
2546   { "popV",             { RMrSP }, 0 },
2547   { "popV",             { RMrBP }, 0 },
2548   { "popV",             { RMrSI }, 0 },
2549   { "popV",             { RMrDI }, 0 },
2550   /* 60 */
2551   { X86_64_TABLE (X86_64_60) },
2552   { X86_64_TABLE (X86_64_61) },
2553   { X86_64_TABLE (X86_64_62) },
2554   { X86_64_TABLE (X86_64_63) },
2555   { Bad_Opcode },       /* seg fs */
2556   { Bad_Opcode },       /* seg gs */
2557   { Bad_Opcode },       /* op size prefix */
2558   { Bad_Opcode },       /* adr size prefix */
2559   /* 68 */
2560   { "pushT",            { sIv }, 0 },
2561   { "imulS",            { Gv, Ev, Iv }, 0 },
2562   { "pushT",            { sIbT }, 0 },
2563   { "imulS",            { Gv, Ev, sIb }, 0 },
2564   { "ins{b|}",          { Ybr, indirDX }, 0 },
2565   { X86_64_TABLE (X86_64_6D) },
2566   { "outs{b|}",         { indirDXr, Xb }, 0 },
2567   { X86_64_TABLE (X86_64_6F) },
2568   /* 70 */
2569   { "joH",              { Jb, BND, cond_jump_flag }, 0 },
2570   { "jnoH",             { Jb, BND, cond_jump_flag }, 0 },
2571   { "jbH",              { Jb, BND, cond_jump_flag }, 0 },
2572   { "jaeH",             { Jb, BND, cond_jump_flag }, 0 },
2573   { "jeH",              { Jb, BND, cond_jump_flag }, 0 },
2574   { "jneH",             { Jb, BND, cond_jump_flag }, 0 },
2575   { "jbeH",             { Jb, BND, cond_jump_flag }, 0 },
2576   { "jaH",              { Jb, BND, cond_jump_flag }, 0 },
2577   /* 78 */
2578   { "jsH",              { Jb, BND, cond_jump_flag }, 0 },
2579   { "jnsH",             { Jb, BND, cond_jump_flag }, 0 },
2580   { "jpH",              { Jb, BND, cond_jump_flag }, 0 },
2581   { "jnpH",             { Jb, BND, cond_jump_flag }, 0 },
2582   { "jlH",              { Jb, BND, cond_jump_flag }, 0 },
2583   { "jgeH",             { Jb, BND, cond_jump_flag }, 0 },
2584   { "jleH",             { Jb, BND, cond_jump_flag }, 0 },
2585   { "jgH",              { Jb, BND, cond_jump_flag }, 0 },
2586   /* 80 */
2587   { REG_TABLE (REG_80) },
2588   { REG_TABLE (REG_81) },
2589   { Bad_Opcode },
2590   { REG_TABLE (REG_82) },
2591   { "testB",            { Eb, Gb }, 0 },
2592   { "testS",            { Ev, Gv }, 0 },
2593   { "xchgB",            { Ebh2, Gb }, 0 },
2594   { "xchgS",            { Evh2, Gv }, 0 },
2595   /* 88 */
2596   { "movB",             { Ebh3, Gb }, 0 },
2597   { "movS",             { Evh3, Gv }, 0 },
2598   { "movB",             { Gb, EbS }, 0 },
2599   { "movS",             { Gv, EvS }, 0 },
2600   { "movD",             { Sv, Sw }, 0 },
2601   { MOD_TABLE (MOD_8D) },
2602   { "movD",             { Sw, Sv }, 0 },
2603   { REG_TABLE (REG_8F) },
2604   /* 90 */
2605   { PREFIX_TABLE (PREFIX_90) },
2606   { "xchgS",            { RMeCX, eAX }, 0 },
2607   { "xchgS",            { RMeDX, eAX }, 0 },
2608   { "xchgS",            { RMeBX, eAX }, 0 },
2609   { "xchgS",            { RMeSP, eAX }, 0 },
2610   { "xchgS",            { RMeBP, eAX }, 0 },
2611   { "xchgS",            { RMeSI, eAX }, 0 },
2612   { "xchgS",            { RMeDI, eAX }, 0 },
2613   /* 98 */
2614   { "cW{t|}R",          { XX }, 0 },
2615   { "cR{t|}O",          { XX }, 0 },
2616   { X86_64_TABLE (X86_64_9A) },
2617   { Bad_Opcode },       /* fwait */
2618   { "pushfT",           { XX }, 0 },
2619   { "popfT",            { XX }, 0 },
2620   { "sahf",             { XX }, 0 },
2621   { "lahf",             { XX }, 0 },
2622   /* a0 */
2623   { "mov%LB",           { AL, Ob }, 0 },
2624   { "mov%LS",           { eAX, Ov }, 0 },
2625   { "mov%LB",           { Ob, AL }, 0 },
2626   { "mov%LS",           { Ov, eAX }, 0 },
2627   { "movs{b|}",         { Ybr, Xb }, 0 },
2628   { "movs{R|}",         { Yvr, Xv }, 0 },
2629   { "cmps{b|}",         { Xb, Yb }, 0 },
2630   { "cmps{R|}",         { Xv, Yv }, 0 },
2631   /* a8 */
2632   { "testB",            { AL, Ib }, 0 },
2633   { "testS",            { eAX, Iv }, 0 },
2634   { "stosB",            { Ybr, AL }, 0 },
2635   { "stosS",            { Yvr, eAX }, 0 },
2636   { "lodsB",            { ALr, Xb }, 0 },
2637   { "lodsS",            { eAXr, Xv }, 0 },
2638   { "scasB",            { AL, Yb }, 0 },
2639   { "scasS",            { eAX, Yv }, 0 },
2640   /* b0 */
2641   { "movB",             { RMAL, Ib }, 0 },
2642   { "movB",             { RMCL, Ib }, 0 },
2643   { "movB",             { RMDL, Ib }, 0 },
2644   { "movB",             { RMBL, Ib }, 0 },
2645   { "movB",             { RMAH, Ib }, 0 },
2646   { "movB",             { RMCH, Ib }, 0 },
2647   { "movB",             { RMDH, Ib }, 0 },
2648   { "movB",             { RMBH, Ib }, 0 },
2649   /* b8 */
2650   { "mov%LV",           { RMeAX, Iv64 }, 0 },
2651   { "mov%LV",           { RMeCX, Iv64 }, 0 },
2652   { "mov%LV",           { RMeDX, Iv64 }, 0 },
2653   { "mov%LV",           { RMeBX, Iv64 }, 0 },
2654   { "mov%LV",           { RMeSP, Iv64 }, 0 },
2655   { "mov%LV",           { RMeBP, Iv64 }, 0 },
2656   { "mov%LV",           { RMeSI, Iv64 }, 0 },
2657   { "mov%LV",           { RMeDI, Iv64 }, 0 },
2658   /* c0 */
2659   { REG_TABLE (REG_C0) },
2660   { REG_TABLE (REG_C1) },
2661   { "retT",             { Iw, BND }, 0 },
2662   { "retT",             { BND }, 0 },
2663   { X86_64_TABLE (X86_64_C4) },
2664   { X86_64_TABLE (X86_64_C5) },
2665   { REG_TABLE (REG_C6) },
2666   { REG_TABLE (REG_C7) },
2667   /* c8 */
2668   { "enterT",           { Iw, Ib }, 0 },
2669   { "leaveT",           { XX }, 0 },
2670   { "Jret{|f}P",        { Iw }, 0 },
2671   { "Jret{|f}P",        { XX }, 0 },
2672   { "int3",             { XX }, 0 },
2673   { "int",              { Ib }, 0 },
2674   { X86_64_TABLE (X86_64_CE) },
2675   { "iret%LP",          { XX }, 0 },
2676   /* d0 */
2677   { REG_TABLE (REG_D0) },
2678   { REG_TABLE (REG_D1) },
2679   { REG_TABLE (REG_D2) },
2680   { REG_TABLE (REG_D3) },
2681   { X86_64_TABLE (X86_64_D4) },
2682   { X86_64_TABLE (X86_64_D5) },
2683   { Bad_Opcode },
2684   { "xlat",             { DSBX }, 0 },
2685   /* d8 */
2686   { FLOAT },
2687   { FLOAT },
2688   { FLOAT },
2689   { FLOAT },
2690   { FLOAT },
2691   { FLOAT },
2692   { FLOAT },
2693   { FLOAT },
2694   /* e0 */
2695   { "loopneFH",         { Jb, XX, loop_jcxz_flag }, 0 },
2696   { "loopeFH",          { Jb, XX, loop_jcxz_flag }, 0 },
2697   { "loopFH",           { Jb, XX, loop_jcxz_flag }, 0 },
2698   { "jEcxzH",           { Jb, XX, loop_jcxz_flag }, 0 },
2699   { "inB",              { AL, Ib }, 0 },
2700   { "inG",              { zAX, Ib }, 0 },
2701   { "outB",             { Ib, AL }, 0 },
2702   { "outG",             { Ib, zAX }, 0 },
2703   /* e8 */
2704   { "callT",            { Jv, BND }, 0 },
2705   { "jmpT",             { Jv, BND }, 0 },
2706   { X86_64_TABLE (X86_64_EA) },
2707   { "jmp",              { Jb, BND }, 0 },
2708   { "inB",              { AL, indirDX }, 0 },
2709   { "inG",              { zAX, indirDX }, 0 },
2710   { "outB",             { indirDX, AL }, 0 },
2711   { "outG",             { indirDX, zAX }, 0 },
2712   /* f0 */
2713   { Bad_Opcode },       /* lock prefix */
2714   { "icebp",            { XX }, 0 },
2715   { Bad_Opcode },       /* repne */
2716   { Bad_Opcode },       /* repz */
2717   { "hlt",              { XX }, 0 },
2718   { "cmc",              { XX }, 0 },
2719   { REG_TABLE (REG_F6) },
2720   { REG_TABLE (REG_F7) },
2721   /* f8 */
2722   { "clc",              { XX }, 0 },
2723   { "stc",              { XX }, 0 },
2724   { "cli",              { XX }, 0 },
2725   { "sti",              { XX }, 0 },
2726   { "cld",              { XX }, 0 },
2727   { "std",              { XX }, 0 },
2728   { REG_TABLE (REG_FE) },
2729   { REG_TABLE (REG_FF) },
2730 };
2731
2732 static const struct dis386 dis386_twobyte[] = {
2733   /* 00 */
2734   { REG_TABLE (REG_0F00 ) },
2735   { REG_TABLE (REG_0F01 ) },
2736   { "larS",             { Gv, Ew }, 0 },
2737   { "lslS",             { Gv, Ew }, 0 },
2738   { Bad_Opcode },
2739   { "syscall",          { XX }, 0 },
2740   { "clts",             { XX }, 0 },
2741   { "sysret%LP",                { XX }, 0 },
2742   /* 08 */
2743   { "invd",             { XX }, 0 },
2744   { "wbinvd",           { XX }, 0 },
2745   { Bad_Opcode },
2746   { "ud2",              { XX }, 0 },
2747   { Bad_Opcode },
2748   { REG_TABLE (REG_0F0D) },
2749   { "femms",            { XX }, 0 },
2750   { "",                 { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix.  */
2751   /* 10 */
2752   { PREFIX_TABLE (PREFIX_0F10) },
2753   { PREFIX_TABLE (PREFIX_0F11) },
2754   { PREFIX_TABLE (PREFIX_0F12) },
2755   { MOD_TABLE (MOD_0F13) },
2756   { "unpcklpX",         { XM, EXx }, PREFIX_OPCODE },
2757   { "unpckhpX",         { XM, EXx }, PREFIX_OPCODE },
2758   { PREFIX_TABLE (PREFIX_0F16) },
2759   { MOD_TABLE (MOD_0F17) },
2760   /* 18 */
2761   { REG_TABLE (REG_0F18) },
2762   { "nopQ",             { Ev }, 0 },
2763   { PREFIX_TABLE (PREFIX_0F1A) },
2764   { PREFIX_TABLE (PREFIX_0F1B) },
2765   { "nopQ",             { Ev }, 0 },
2766   { "nopQ",             { Ev }, 0 },
2767   { "nopQ",             { Ev }, 0 },
2768   { "nopQ",             { Ev }, 0 },
2769   /* 20 */
2770   { "movZ",             { Rm, Cm }, 0 },
2771   { "movZ",             { Rm, Dm }, 0 },
2772   { "movZ",             { Cm, Rm }, 0 },
2773   { "movZ",             { Dm, Rm }, 0 },
2774   { MOD_TABLE (MOD_0F24) },
2775   { Bad_Opcode },
2776   { MOD_TABLE (MOD_0F26) },
2777   { Bad_Opcode },
2778   /* 28 */
2779   { "movapX",           { XM, EXx }, PREFIX_OPCODE },
2780   { "movapX",           { EXxS, XM }, PREFIX_OPCODE },
2781   { PREFIX_TABLE (PREFIX_0F2A) },
2782   { PREFIX_TABLE (PREFIX_0F2B) },
2783   { PREFIX_TABLE (PREFIX_0F2C) },
2784   { PREFIX_TABLE (PREFIX_0F2D) },
2785   { PREFIX_TABLE (PREFIX_0F2E) },
2786   { PREFIX_TABLE (PREFIX_0F2F) },
2787   /* 30 */
2788   { "wrmsr",            { XX }, 0 },
2789   { "rdtsc",            { XX }, 0 },
2790   { "rdmsr",            { XX }, 0 },
2791   { "rdpmc",            { XX }, 0 },
2792   { "sysenter",         { XX }, 0 },
2793   { "sysexit",          { XX }, 0 },
2794   { Bad_Opcode },
2795   { "getsec",           { XX }, 0 },
2796   /* 38 */
2797   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2798   { Bad_Opcode },
2799   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2800   { Bad_Opcode },
2801   { Bad_Opcode },
2802   { Bad_Opcode },
2803   { Bad_Opcode },
2804   { Bad_Opcode },
2805   /* 40 */
2806   { "cmovoS",           { Gv, Ev }, 0 },
2807   { "cmovnoS",          { Gv, Ev }, 0 },
2808   { "cmovbS",           { Gv, Ev }, 0 },
2809   { "cmovaeS",          { Gv, Ev }, 0 },
2810   { "cmoveS",           { Gv, Ev }, 0 },
2811   { "cmovneS",          { Gv, Ev }, 0 },
2812   { "cmovbeS",          { Gv, Ev }, 0 },
2813   { "cmovaS",           { Gv, Ev }, 0 },
2814   /* 48 */
2815   { "cmovsS",           { Gv, Ev }, 0 },
2816   { "cmovnsS",          { Gv, Ev }, 0 },
2817   { "cmovpS",           { Gv, Ev }, 0 },
2818   { "cmovnpS",          { Gv, Ev }, 0 },
2819   { "cmovlS",           { Gv, Ev }, 0 },
2820   { "cmovgeS",          { Gv, Ev }, 0 },
2821   { "cmovleS",          { Gv, Ev }, 0 },
2822   { "cmovgS",           { Gv, Ev }, 0 },
2823   /* 50 */
2824   { MOD_TABLE (MOD_0F51) },
2825   { PREFIX_TABLE (PREFIX_0F51) },
2826   { PREFIX_TABLE (PREFIX_0F52) },
2827   { PREFIX_TABLE (PREFIX_0F53) },
2828   { "andpX",            { XM, EXx }, PREFIX_OPCODE },
2829   { "andnpX",           { XM, EXx }, PREFIX_OPCODE },
2830   { "orpX",             { XM, EXx }, PREFIX_OPCODE },
2831   { "xorpX",            { XM, EXx }, PREFIX_OPCODE },
2832   /* 58 */
2833   { PREFIX_TABLE (PREFIX_0F58) },
2834   { PREFIX_TABLE (PREFIX_0F59) },
2835   { PREFIX_TABLE (PREFIX_0F5A) },
2836   { PREFIX_TABLE (PREFIX_0F5B) },
2837   { PREFIX_TABLE (PREFIX_0F5C) },
2838   { PREFIX_TABLE (PREFIX_0F5D) },
2839   { PREFIX_TABLE (PREFIX_0F5E) },
2840   { PREFIX_TABLE (PREFIX_0F5F) },
2841   /* 60 */
2842   { PREFIX_TABLE (PREFIX_0F60) },
2843   { PREFIX_TABLE (PREFIX_0F61) },
2844   { PREFIX_TABLE (PREFIX_0F62) },
2845   { "packsswb",         { MX, EM }, PREFIX_OPCODE },
2846   { "pcmpgtb",          { MX, EM }, PREFIX_OPCODE },
2847   { "pcmpgtw",          { MX, EM }, PREFIX_OPCODE },
2848   { "pcmpgtd",          { MX, EM }, PREFIX_OPCODE },
2849   { "packuswb",         { MX, EM }, PREFIX_OPCODE },
2850   /* 68 */
2851   { "punpckhbw",        { MX, EM }, PREFIX_OPCODE },
2852   { "punpckhwd",        { MX, EM }, PREFIX_OPCODE },
2853   { "punpckhdq",        { MX, EM }, PREFIX_OPCODE },
2854   { "packssdw",         { MX, EM }, PREFIX_OPCODE },
2855   { PREFIX_TABLE (PREFIX_0F6C) },
2856   { PREFIX_TABLE (PREFIX_0F6D) },
2857   { "movK",             { MX, Edq }, PREFIX_OPCODE },
2858   { PREFIX_TABLE (PREFIX_0F6F) },
2859   /* 70 */
2860   { PREFIX_TABLE (PREFIX_0F70) },
2861   { REG_TABLE (REG_0F71) },
2862   { REG_TABLE (REG_0F72) },
2863   { REG_TABLE (REG_0F73) },
2864   { "pcmpeqb",          { MX, EM }, PREFIX_OPCODE },
2865   { "pcmpeqw",          { MX, EM }, PREFIX_OPCODE },
2866   { "pcmpeqd",          { MX, EM }, PREFIX_OPCODE },
2867   { "emms",             { XX }, PREFIX_OPCODE },
2868   /* 78 */
2869   { PREFIX_TABLE (PREFIX_0F78) },
2870   { PREFIX_TABLE (PREFIX_0F79) },
2871   { THREE_BYTE_TABLE (THREE_BYTE_0F7A) },
2872   { Bad_Opcode },
2873   { PREFIX_TABLE (PREFIX_0F7C) },
2874   { PREFIX_TABLE (PREFIX_0F7D) },
2875   { PREFIX_TABLE (PREFIX_0F7E) },
2876   { PREFIX_TABLE (PREFIX_0F7F) },
2877   /* 80 */
2878   { "joH",              { Jv, BND, cond_jump_flag }, 0 },
2879   { "jnoH",             { Jv, BND, cond_jump_flag }, 0 },
2880   { "jbH",              { Jv, BND, cond_jump_flag }, 0 },
2881   { "jaeH",             { Jv, BND, cond_jump_flag }, 0 },
2882   { "jeH",              { Jv, BND, cond_jump_flag }, 0 },
2883   { "jneH",             { Jv, BND, cond_jump_flag }, 0 },
2884   { "jbeH",             { Jv, BND, cond_jump_flag }, 0 },
2885   { "jaH",              { Jv, BND, cond_jump_flag }, 0 },
2886   /* 88 */
2887   { "jsH",              { Jv, BND, cond_jump_flag }, 0 },
2888   { "jnsH",             { Jv, BND, cond_jump_flag }, 0 },
2889   { "jpH",              { Jv, BND, cond_jump_flag }, 0 },
2890   { "jnpH",             { Jv, BND, cond_jump_flag }, 0 },
2891   { "jlH",              { Jv, BND, cond_jump_flag }, 0 },
2892   { "jgeH",             { Jv, BND, cond_jump_flag }, 0 },
2893   { "jleH",             { Jv, BND, cond_jump_flag }, 0 },
2894   { "jgH",              { Jv, BND, cond_jump_flag }, 0 },
2895   /* 90 */
2896   { "seto",             { Eb }, 0 },
2897   { "setno",            { Eb }, 0 },
2898   { "setb",             { Eb }, 0 },
2899   { "setae",            { Eb }, 0 },
2900   { "sete",             { Eb }, 0 },
2901   { "setne",            { Eb }, 0 },
2902   { "setbe",            { Eb }, 0 },
2903   { "seta",             { Eb }, 0 },
2904   /* 98 */
2905   { "sets",             { Eb }, 0 },
2906   { "setns",            { Eb }, 0 },
2907   { "setp",             { Eb }, 0 },
2908   { "setnp",            { Eb }, 0 },
2909   { "setl",             { Eb }, 0 },
2910   { "setge",            { Eb }, 0 },
2911   { "setle",            { Eb }, 0 },
2912   { "setg",             { Eb }, 0 },
2913   /* a0 */
2914   { "pushT",            { fs }, 0 },
2915   { "popT",             { fs }, 0 },
2916   { "cpuid",            { XX }, 0 },
2917   { "btS",              { Ev, Gv }, 0 },
2918   { "shldS",            { Ev, Gv, Ib }, 0 },
2919   { "shldS",            { Ev, Gv, CL }, 0 },
2920   { REG_TABLE (REG_0FA6) },
2921   { REG_TABLE (REG_0FA7) },
2922   /* a8 */
2923   { "pushT",            { gs }, 0 },
2924   { "popT",             { gs }, 0 },
2925   { "rsm",              { XX }, 0 },
2926   { "btsS",             { Evh1, Gv }, 0 },
2927   { "shrdS",            { Ev, Gv, Ib }, 0 },
2928   { "shrdS",            { Ev, Gv, CL }, 0 },
2929   { REG_TABLE (REG_0FAE) },
2930   { "imulS",            { Gv, Ev }, 0 },
2931   /* b0 */
2932   { "cmpxchgB",         { Ebh1, Gb }, 0 },
2933   { "cmpxchgS",         { Evh1, Gv }, 0 },
2934   { MOD_TABLE (MOD_0FB2) },
2935   { "btrS",             { Evh1, Gv }, 0 },
2936   { MOD_TABLE (MOD_0FB4) },
2937   { MOD_TABLE (MOD_0FB5) },
2938   { "movz{bR|x}",       { Gv, Eb }, 0 },
2939   { "movz{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
2940   /* b8 */
2941   { PREFIX_TABLE (PREFIX_0FB8) },
2942   { "ud1",              { XX }, 0 },
2943   { REG_TABLE (REG_0FBA) },
2944   { "btcS",             { Evh1, Gv }, 0 },
2945   { PREFIX_TABLE (PREFIX_0FBC) },
2946   { PREFIX_TABLE (PREFIX_0FBD) },
2947   { "movs{bR|x}",       { Gv, Eb }, 0 },
2948   { "movs{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
2949   /* c0 */
2950   { "xaddB",            { Ebh1, Gb }, 0 },
2951   { "xaddS",            { Evh1, Gv }, 0 },
2952   { PREFIX_TABLE (PREFIX_0FC2) },
2953   { PREFIX_TABLE (PREFIX_0FC3) },
2954   { "pinsrw",           { MX, Edqw, Ib }, PREFIX_OPCODE },
2955   { "pextrw",           { Gdq, MS, Ib }, PREFIX_OPCODE },
2956   { "shufpX",           { XM, EXx, Ib }, PREFIX_OPCODE },
2957   { REG_TABLE (REG_0FC7) },
2958   /* c8 */
2959   { "bswap",            { RMeAX }, 0 },
2960   { "bswap",            { RMeCX }, 0 },
2961   { "bswap",            { RMeDX }, 0 },
2962   { "bswap",            { RMeBX }, 0 },
2963   { "bswap",            { RMeSP }, 0 },
2964   { "bswap",            { RMeBP }, 0 },
2965   { "bswap",            { RMeSI }, 0 },
2966   { "bswap",            { RMeDI }, 0 },
2967   /* d0 */
2968   { PREFIX_TABLE (PREFIX_0FD0) },
2969   { "psrlw",            { MX, EM }, PREFIX_OPCODE },
2970   { "psrld",            { MX, EM }, PREFIX_OPCODE },
2971   { "psrlq",            { MX, EM }, PREFIX_OPCODE },
2972   { "paddq",            { MX, EM }, PREFIX_OPCODE },
2973   { "pmullw",           { MX, EM }, PREFIX_OPCODE },
2974   { PREFIX_TABLE (PREFIX_0FD6) },
2975   { MOD_TABLE (MOD_0FD7) },
2976   /* d8 */
2977   { "psubusb",          { MX, EM }, PREFIX_OPCODE },
2978   { "psubusw",          { MX, EM }, PREFIX_OPCODE },
2979   { "pminub",           { MX, EM }, PREFIX_OPCODE },
2980   { "pand",             { MX, EM }, PREFIX_OPCODE },
2981   { "paddusb",          { MX, EM }, PREFIX_OPCODE },
2982   { "paddusw",          { MX, EM }, PREFIX_OPCODE },
2983   { "pmaxub",           { MX, EM }, PREFIX_OPCODE },
2984   { "pandn",            { MX, EM }, PREFIX_OPCODE },
2985   /* e0 */
2986   { "pavgb",            { MX, EM }, PREFIX_OPCODE },
2987   { "psraw",            { MX, EM }, PREFIX_OPCODE },
2988   { "psrad",            { MX, EM }, PREFIX_OPCODE },
2989   { "pavgw",            { MX, EM }, PREFIX_OPCODE },
2990   { "pmulhuw",          { MX, EM }, PREFIX_OPCODE },
2991   { "pmulhw",           { MX, EM }, PREFIX_OPCODE },
2992   { PREFIX_TABLE (PREFIX_0FE6) },
2993   { PREFIX_TABLE (PREFIX_0FE7) },
2994   /* e8 */
2995   { "psubsb",           { MX, EM }, PREFIX_OPCODE },
2996   { "psubsw",           { MX, EM }, PREFIX_OPCODE },
2997   { "pminsw",           { MX, EM }, PREFIX_OPCODE },
2998   { "por",              { MX, EM }, PREFIX_OPCODE },
2999   { "paddsb",           { MX, EM }, PREFIX_OPCODE },
3000   { "paddsw",           { MX, EM }, PREFIX_OPCODE },
3001   { "pmaxsw",           { MX, EM }, PREFIX_OPCODE },
3002   { "pxor",             { MX, EM }, PREFIX_OPCODE },
3003   /* f0 */
3004   { PREFIX_TABLE (PREFIX_0FF0) },
3005   { "psllw",            { MX, EM }, PREFIX_OPCODE },
3006   { "pslld",            { MX, EM }, PREFIX_OPCODE },
3007   { "psllq",            { MX, EM }, PREFIX_OPCODE },
3008   { "pmuludq",          { MX, EM }, PREFIX_OPCODE },
3009   { "pmaddwd",          { MX, EM }, PREFIX_OPCODE },
3010   { "psadbw",           { MX, EM }, PREFIX_OPCODE },
3011   { PREFIX_TABLE (PREFIX_0FF7) },
3012   /* f8 */
3013   { "psubb",            { MX, EM }, PREFIX_OPCODE },
3014   { "psubw",            { MX, EM }, PREFIX_OPCODE },
3015   { "psubd",            { MX, EM }, PREFIX_OPCODE },
3016   { "psubq",            { MX, EM }, PREFIX_OPCODE },
3017   { "paddb",            { MX, EM }, PREFIX_OPCODE },
3018   { "paddw",            { MX, EM }, PREFIX_OPCODE },
3019   { "paddd",            { MX, EM }, PREFIX_OPCODE },
3020   { Bad_Opcode },
3021 };
3022
3023 static const unsigned char onebyte_has_modrm[256] = {
3024   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3025   /*       -------------------------------        */
3026   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
3027   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
3028   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
3029   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
3030   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
3031   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
3032   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
3033   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
3034   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
3035   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
3036   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
3037   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
3038   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
3039   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
3040   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
3041   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
3042   /*       -------------------------------        */
3043   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3044 };
3045
3046 static const unsigned char twobyte_has_modrm[256] = {
3047   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3048   /*       -------------------------------        */
3049   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
3050   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
3051   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
3052   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
3053   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
3054   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
3055   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
3056   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
3057   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
3058   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
3059   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
3060   /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
3061   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
3062   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
3063   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
3064   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0  /* ff */
3065   /*       -------------------------------        */
3066   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3067 };
3068
3069 static char obuf[100];
3070 static char *obufp;
3071 static char *mnemonicendp;
3072 static char scratchbuf[100];
3073 static unsigned char *start_codep;
3074 static unsigned char *insn_codep;
3075 static unsigned char *codep;
3076 static unsigned char *end_codep;
3077 static int last_lock_prefix;
3078 static int last_repz_prefix;
3079 static int last_repnz_prefix;
3080 static int last_data_prefix;
3081 static int last_addr_prefix;
3082 static int last_rex_prefix;
3083 static int last_seg_prefix;
3084 static int fwait_prefix;
3085 /* The active segment register prefix.  */
3086 static int active_seg_prefix;
3087 #define MAX_CODE_LENGTH 15
3088 /* We can up to 14 prefixes since the maximum instruction length is
3089    15bytes.  */
3090 static int all_prefixes[MAX_CODE_LENGTH - 1];
3091 static disassemble_info *the_info;
3092 static struct
3093   {
3094     int mod;
3095     int reg;
3096     int rm;
3097   }
3098 modrm;
3099 static unsigned char need_modrm;
3100 static struct
3101   {
3102     int scale;
3103     int index;
3104     int base;
3105   }
3106 sib;
3107 static struct
3108   {
3109     int register_specifier;
3110     int length;
3111     int prefix;
3112     int w;
3113     int evex;
3114     int r;
3115     int v;
3116     int mask_register_specifier;
3117     int zeroing;
3118     int ll;
3119     int b;
3120   }
3121 vex;
3122 static unsigned char need_vex;
3123 static unsigned char need_vex_reg;
3124 static unsigned char vex_w_done;
3125
3126 struct op
3127   {
3128     const char *name;
3129     unsigned int len;
3130   };
3131
3132 /* If we are accessing mod/rm/reg without need_modrm set, then the
3133    values are stale.  Hitting this abort likely indicates that you
3134    need to update onebyte_has_modrm or twobyte_has_modrm.  */
3135 #define MODRM_CHECK  if (!need_modrm) abort ()
3136
3137 static const char **names64;
3138 static const char **names32;
3139 static const char **names16;
3140 static const char **names8;
3141 static const char **names8rex;
3142 static const char **names_seg;
3143 static const char *index64;
3144 static const char *index32;
3145 static const char **index16;
3146 static const char **names_bnd;
3147
3148 static const char *intel_names64[] = {
3149   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3150   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3151 };
3152 static const char *intel_names32[] = {
3153   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3154   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3155 };
3156 static const char *intel_names16[] = {
3157   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3158   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3159 };
3160 static const char *intel_names8[] = {
3161   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3162 };
3163 static const char *intel_names8rex[] = {
3164   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3165   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3166 };
3167 static const char *intel_names_seg[] = {
3168   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3169 };
3170 static const char *intel_index64 = "riz";
3171 static const char *intel_index32 = "eiz";
3172 static const char *intel_index16[] = {
3173   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3174 };
3175
3176 static const char *att_names64[] = {
3177   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3178   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3179 };
3180 static const char *att_names32[] = {
3181   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3182   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3183 };
3184 static const char *att_names16[] = {
3185   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3186   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3187 };
3188 static const char *att_names8[] = {
3189   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3190 };
3191 static const char *att_names8rex[] = {
3192   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3193   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3194 };
3195 static const char *att_names_seg[] = {
3196   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3197 };
3198 static const char *att_index64 = "%riz";
3199 static const char *att_index32 = "%eiz";
3200 static const char *att_index16[] = {
3201   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3202 };
3203
3204 static const char **names_mm;
3205 static const char *intel_names_mm[] = {
3206   "mm0", "mm1", "mm2", "mm3",
3207   "mm4", "mm5", "mm6", "mm7"
3208 };
3209 static const char *att_names_mm[] = {
3210   "%mm0", "%mm1", "%mm2", "%mm3",
3211   "%mm4", "%mm5", "%mm6", "%mm7"
3212 };
3213
3214 static const char *intel_names_bnd[] = {
3215   "bnd0", "bnd1", "bnd2", "bnd3"
3216 };
3217
3218 static const char *att_names_bnd[] = {
3219   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3220 };
3221
3222 static const char **names_xmm;
3223 static const char *intel_names_xmm[] = {
3224   "xmm0", "xmm1", "xmm2", "xmm3",
3225   "xmm4", "xmm5", "xmm6", "xmm7",
3226   "xmm8", "xmm9", "xmm10", "xmm11",
3227   "xmm12", "xmm13", "xmm14", "xmm15",
3228   "xmm16", "xmm17", "xmm18", "xmm19",
3229   "xmm20", "xmm21", "xmm22", "xmm23",
3230   "xmm24", "xmm25", "xmm26", "xmm27",
3231   "xmm28", "xmm29", "xmm30", "xmm31"
3232 };
3233 static const char *att_names_xmm[] = {
3234   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3235   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3236   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3237   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3238   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3239   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3240   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3241   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3242 };
3243
3244 static const char **names_ymm;
3245 static const char *intel_names_ymm[] = {
3246   "ymm0", "ymm1", "ymm2", "ymm3",
3247   "ymm4", "ymm5", "ymm6", "ymm7",
3248   "ymm8", "ymm9", "ymm10", "ymm11",
3249   "ymm12", "ymm13", "ymm14", "ymm15",
3250   "ymm16", "ymm17", "ymm18", "ymm19",
3251   "ymm20", "ymm21", "ymm22", "ymm23",
3252   "ymm24", "ymm25", "ymm26", "ymm27",
3253   "ymm28", "ymm29", "ymm30", "ymm31"
3254 };
3255 static const char *att_names_ymm[] = {
3256   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3257   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3258   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3259   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3260   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3261   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3262   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3263   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3264 };
3265
3266 static const char **names_zmm;
3267 static const char *intel_names_zmm[] = {
3268   "zmm0", "zmm1", "zmm2", "zmm3",
3269   "zmm4", "zmm5", "zmm6", "zmm7",
3270   "zmm8", "zmm9", "zmm10", "zmm11",
3271   "zmm12", "zmm13", "zmm14", "zmm15",
3272   "zmm16", "zmm17", "zmm18", "zmm19",
3273   "zmm20", "zmm21", "zmm22", "zmm23",
3274   "zmm24", "zmm25", "zmm26", "zmm27",
3275   "zmm28", "zmm29", "zmm30", "zmm31"
3276 };
3277 static const char *att_names_zmm[] = {
3278   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3279   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3280   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3281   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3282   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3283   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3284   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3285   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3286 };
3287
3288 static const char **names_mask;
3289 static const char *intel_names_mask[] = {
3290   "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3291 };
3292 static const char *att_names_mask[] = {
3293   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3294 };
3295
3296 static const char *names_rounding[] =
3297 {
3298   "{rn-sae}",
3299   "{rd-sae}",
3300   "{ru-sae}",
3301   "{rz-sae}"
3302 };
3303
3304 static const struct dis386 reg_table[][8] = {
3305   /* REG_80 */
3306   {
3307     { "addA",   { Ebh1, Ib }, 0 },
3308     { "orA",    { Ebh1, Ib }, 0 },
3309     { "adcA",   { Ebh1, Ib }, 0 },
3310     { "sbbA",   { Ebh1, Ib }, 0 },
3311     { "andA",   { Ebh1, Ib }, 0 },
3312     { "subA",   { Ebh1, Ib }, 0 },
3313     { "xorA",   { Ebh1, Ib }, 0 },
3314     { "cmpA",   { Eb, Ib }, 0 },
3315   },
3316   /* REG_81 */
3317   {
3318     { "addQ",   { Evh1, Iv }, 0 },
3319     { "orQ",    { Evh1, Iv }, 0 },
3320     { "adcQ",   { Evh1, Iv }, 0 },
3321     { "sbbQ",   { Evh1, Iv }, 0 },
3322     { "andQ",   { Evh1, Iv }, 0 },
3323     { "subQ",   { Evh1, Iv }, 0 },
3324     { "xorQ",   { Evh1, Iv }, 0 },
3325     { "cmpQ",   { Ev, Iv }, 0 },
3326   },
3327   /* REG_82 */
3328   {
3329     { "addQ",   { Evh1, sIb }, 0 },
3330     { "orQ",    { Evh1, sIb }, 0 },
3331     { "adcQ",   { Evh1, sIb }, 0 },
3332     { "sbbQ",   { Evh1, sIb }, 0 },
3333     { "andQ",   { Evh1, sIb }, 0 },
3334     { "subQ",   { Evh1, sIb }, 0 },
3335     { "xorQ",   { Evh1, sIb }, 0 },
3336     { "cmpQ",   { Ev, sIb }, 0 },
3337   },
3338   /* REG_8F */
3339   {
3340     { "popU",   { stackEv }, 0 },
3341     { XOP_8F_TABLE (XOP_09) },
3342     { Bad_Opcode },
3343     { Bad_Opcode },
3344     { Bad_Opcode },
3345     { XOP_8F_TABLE (XOP_09) },
3346   },
3347   /* REG_C0 */
3348   {
3349     { "rolA",   { Eb, Ib }, 0 },
3350     { "rorA",   { Eb, Ib }, 0 },
3351     { "rclA",   { Eb, Ib }, 0 },
3352     { "rcrA",   { Eb, Ib }, 0 },
3353     { "shlA",   { Eb, Ib }, 0 },
3354     { "shrA",   { Eb, Ib }, 0 },
3355     { Bad_Opcode },
3356     { "sarA",   { Eb, Ib }, 0 },
3357   },
3358   /* REG_C1 */
3359   {
3360     { "rolQ",   { Ev, Ib }, 0 },
3361     { "rorQ",   { Ev, Ib }, 0 },
3362     { "rclQ",   { Ev, Ib }, 0 },
3363     { "rcrQ",   { Ev, Ib }, 0 },
3364     { "shlQ",   { Ev, Ib }, 0 },
3365     { "shrQ",   { Ev, Ib }, 0 },
3366     { Bad_Opcode },
3367     { "sarQ",   { Ev, Ib }, 0 },
3368   },
3369   /* REG_C6 */
3370   {
3371     { "movA",   { Ebh3, Ib }, 0 },
3372     { Bad_Opcode },
3373     { Bad_Opcode },
3374     { Bad_Opcode },
3375     { Bad_Opcode },
3376     { Bad_Opcode },
3377     { Bad_Opcode },
3378     { MOD_TABLE (MOD_C6_REG_7) },
3379   },
3380   /* REG_C7 */
3381   {
3382     { "movQ",   { Evh3, Iv }, 0 },
3383     { Bad_Opcode },
3384     { Bad_Opcode },
3385     { Bad_Opcode },
3386     { Bad_Opcode },
3387     { Bad_Opcode },
3388     { Bad_Opcode },
3389     { MOD_TABLE (MOD_C7_REG_7) },
3390   },
3391   /* REG_D0 */
3392   {
3393     { "rolA",   { Eb, I1 }, 0 },
3394     { "rorA",   { Eb, I1 }, 0 },
3395     { "rclA",   { Eb, I1 }, 0 },
3396     { "rcrA",   { Eb, I1 }, 0 },
3397     { "shlA",   { Eb, I1 }, 0 },
3398     { "shrA",   { Eb, I1 }, 0 },
3399     { Bad_Opcode },
3400     { "sarA",   { Eb, I1 }, 0 },
3401   },
3402   /* REG_D1 */
3403   {
3404     { "rolQ",   { Ev, I1 }, 0 },
3405     { "rorQ",   { Ev, I1 }, 0 },
3406     { "rclQ",   { Ev, I1 }, 0 },
3407     { "rcrQ",   { Ev, I1 }, 0 },
3408     { "shlQ",   { Ev, I1 }, 0 },
3409     { "shrQ",   { Ev, I1 }, 0 },
3410     { Bad_Opcode },
3411     { "sarQ",   { Ev, I1 }, 0 },
3412   },
3413   /* REG_D2 */
3414   {
3415     { "rolA",   { Eb, CL }, 0 },
3416     { "rorA",   { Eb, CL }, 0 },
3417     { "rclA",   { Eb, CL }, 0 },
3418     { "rcrA",   { Eb, CL }, 0 },
3419     { "shlA",   { Eb, CL }, 0 },
3420     { "shrA",   { Eb, CL }, 0 },
3421     { Bad_Opcode },
3422     { "sarA",   { Eb, CL }, 0 },
3423   },
3424   /* REG_D3 */
3425   {
3426     { "rolQ",   { Ev, CL }, 0 },
3427     { "rorQ",   { Ev, CL }, 0 },
3428     { "rclQ",   { Ev, CL }, 0 },
3429     { "rcrQ",   { Ev, CL }, 0 },
3430     { "shlQ",   { Ev, CL }, 0 },
3431     { "shrQ",   { Ev, CL }, 0 },
3432     { Bad_Opcode },
3433     { "sarQ",   { Ev, CL }, 0 },
3434   },
3435   /* REG_F6 */
3436   {
3437     { "testA",  { Eb, Ib }, 0 },
3438     { Bad_Opcode },
3439     { "notA",   { Ebh1 }, 0 },
3440     { "negA",   { Ebh1 }, 0 },
3441     { "mulA",   { Eb }, 0 },    /* Don't print the implicit %al register,  */
3442     { "imulA",  { Eb }, 0 },    /* to distinguish these opcodes from other */
3443     { "divA",   { Eb }, 0 },    /* mul/imul opcodes.  Do the same for div  */
3444     { "idivA",  { Eb }, 0 },    /* and idiv for consistency.               */
3445   },
3446   /* REG_F7 */
3447   {
3448     { "testQ",  { Ev, Iv }, 0 },
3449     { Bad_Opcode },
3450     { "notQ",   { Evh1 }, 0 },
3451     { "negQ",   { Evh1 }, 0 },
3452     { "mulQ",   { Ev }, 0 },    /* Don't print the implicit register.  */
3453     { "imulQ",  { Ev }, 0 },
3454     { "divQ",   { Ev }, 0 },
3455     { "idivQ",  { Ev }, 0 },
3456   },
3457   /* REG_FE */
3458   {
3459     { "incA",   { Ebh1 }, 0 },
3460     { "decA",   { Ebh1 }, 0 },
3461   },
3462   /* REG_FF */
3463   {
3464     { "incQ",   { Evh1 }, 0 },
3465     { "decQ",   { Evh1 }, 0 },
3466     { "call{T|}", { indirEv, BND }, 0 },
3467     { MOD_TABLE (MOD_FF_REG_3) },
3468     { "jmp{T|}", { indirEv, BND }, 0 },
3469     { MOD_TABLE (MOD_FF_REG_5) },
3470     { "pushU",  { stackEv }, 0 },
3471     { Bad_Opcode },
3472   },
3473   /* REG_0F00 */
3474   {
3475     { "sldtD",  { Sv }, 0 },
3476     { "strD",   { Sv }, 0 },
3477     { "lldt",   { Ew }, 0 },
3478     { "ltr",    { Ew }, 0 },
3479     { "verr",   { Ew }, 0 },
3480     { "verw",   { Ew }, 0 },
3481     { Bad_Opcode },
3482     { Bad_Opcode },
3483   },
3484   /* REG_0F01 */
3485   {
3486     { MOD_TABLE (MOD_0F01_REG_0) },
3487     { MOD_TABLE (MOD_0F01_REG_1) },
3488     { MOD_TABLE (MOD_0F01_REG_2) },
3489     { MOD_TABLE (MOD_0F01_REG_3) },
3490     { "smswD",  { Sv }, 0 },
3491     { Bad_Opcode },
3492     { "lmsw",   { Ew }, 0 },
3493     { MOD_TABLE (MOD_0F01_REG_7) },
3494   },
3495   /* REG_0F0D */
3496   {
3497     { "prefetch",       { Mb }, 0 },
3498     { "prefetchw",      { Mb }, 0 },
3499     { "prefetchwt1",    { Mb }, 0 },
3500     { "prefetch",       { Mb }, 0 },
3501     { "prefetch",       { Mb }, 0 },
3502     { "prefetch",       { Mb }, 0 },
3503     { "prefetch",       { Mb }, 0 },
3504     { "prefetch",       { Mb }, 0 },
3505   },
3506   /* REG_0F18 */
3507   {
3508     { MOD_TABLE (MOD_0F18_REG_0) },
3509     { MOD_TABLE (MOD_0F18_REG_1) },
3510     { MOD_TABLE (MOD_0F18_REG_2) },
3511     { MOD_TABLE (MOD_0F18_REG_3) },
3512     { MOD_TABLE (MOD_0F18_REG_4) },
3513     { MOD_TABLE (MOD_0F18_REG_5) },
3514     { MOD_TABLE (MOD_0F18_REG_6) },
3515     { MOD_TABLE (MOD_0F18_REG_7) },
3516   },
3517   /* REG_0F71 */
3518   {
3519     { Bad_Opcode },
3520     { Bad_Opcode },
3521     { MOD_TABLE (MOD_0F71_REG_2) },
3522     { Bad_Opcode },
3523     { MOD_TABLE (MOD_0F71_REG_4) },
3524     { Bad_Opcode },
3525     { MOD_TABLE (MOD_0F71_REG_6) },
3526   },
3527   /* REG_0F72 */
3528   {
3529     { Bad_Opcode },
3530     { Bad_Opcode },
3531     { MOD_TABLE (MOD_0F72_REG_2) },
3532     { Bad_Opcode },
3533     { MOD_TABLE (MOD_0F72_REG_4) },
3534     { Bad_Opcode },
3535     { MOD_TABLE (MOD_0F72_REG_6) },
3536   },
3537   /* REG_0F73 */
3538   {
3539     { Bad_Opcode },
3540     { Bad_Opcode },
3541     { MOD_TABLE (MOD_0F73_REG_2) },
3542     { MOD_TABLE (MOD_0F73_REG_3) },
3543     { Bad_Opcode },
3544     { Bad_Opcode },
3545     { MOD_TABLE (MOD_0F73_REG_6) },
3546     { MOD_TABLE (MOD_0F73_REG_7) },
3547   },
3548   /* REG_0FA6 */
3549   {
3550     { "montmul",        { { OP_0f07, 0 } }, 0 },
3551     { "xsha1",          { { OP_0f07, 0 } }, 0 },
3552     { "xsha256",        { { OP_0f07, 0 } }, 0 },
3553   },
3554   /* REG_0FA7 */
3555   {
3556     { "xstore-rng",     { { OP_0f07, 0 } }, 0 },
3557     { "xcrypt-ecb",     { { OP_0f07, 0 } }, 0 },
3558     { "xcrypt-cbc",     { { OP_0f07, 0 } }, 0 },
3559     { "xcrypt-ctr",     { { OP_0f07, 0 } }, 0 },
3560     { "xcrypt-cfb",     { { OP_0f07, 0 } }, 0 },
3561     { "xcrypt-ofb",     { { OP_0f07, 0 } }, 0 },
3562   },
3563   /* REG_0FAE */
3564   {
3565     { MOD_TABLE (MOD_0FAE_REG_0) },
3566     { MOD_TABLE (MOD_0FAE_REG_1) },
3567     { MOD_TABLE (MOD_0FAE_REG_2) },
3568     { MOD_TABLE (MOD_0FAE_REG_3) },
3569     { MOD_TABLE (MOD_0FAE_REG_4) },
3570     { MOD_TABLE (MOD_0FAE_REG_5) },
3571     { MOD_TABLE (MOD_0FAE_REG_6) },
3572     { MOD_TABLE (MOD_0FAE_REG_7) },
3573   },
3574   /* REG_0FBA */
3575   {
3576     { Bad_Opcode },
3577     { Bad_Opcode },
3578     { Bad_Opcode },
3579     { Bad_Opcode },
3580     { "btQ",    { Ev, Ib }, 0 },
3581     { "btsQ",   { Evh1, Ib }, 0 },
3582     { "btrQ",   { Evh1, Ib }, 0 },
3583     { "btcQ",   { Evh1, Ib }, 0 },
3584   },
3585   /* REG_0FC7 */
3586   {
3587     { Bad_Opcode },
3588     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
3589     { Bad_Opcode },
3590     { MOD_TABLE (MOD_0FC7_REG_3) },
3591     { MOD_TABLE (MOD_0FC7_REG_4) },
3592     { MOD_TABLE (MOD_0FC7_REG_5) },
3593     { MOD_TABLE (MOD_0FC7_REG_6) },
3594     { MOD_TABLE (MOD_0FC7_REG_7) },
3595   },
3596   /* REG_VEX_0F71 */
3597   {
3598     { Bad_Opcode },
3599     { Bad_Opcode },
3600     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3601     { Bad_Opcode },
3602     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3603     { Bad_Opcode },
3604     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3605   },
3606   /* REG_VEX_0F72 */
3607   {
3608     { Bad_Opcode },
3609     { Bad_Opcode },
3610     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3611     { Bad_Opcode },
3612     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3613     { Bad_Opcode },
3614     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3615   },
3616   /* REG_VEX_0F73 */
3617   {
3618     { Bad_Opcode },
3619     { Bad_Opcode },
3620     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3621     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3622     { Bad_Opcode },
3623     { Bad_Opcode },
3624     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3625     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3626   },
3627   /* REG_VEX_0FAE */
3628   {
3629     { Bad_Opcode },
3630     { Bad_Opcode },
3631     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3632     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3633   },
3634   /* REG_VEX_0F38F3 */
3635   {
3636     { Bad_Opcode },
3637     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3638     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3639     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3640   },
3641   /* REG_XOP_LWPCB */
3642   {
3643     { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3644     { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3645   },
3646   /* REG_XOP_LWP */
3647   {
3648     { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3649     { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3650   },
3651   /* REG_XOP_TBM_01 */
3652   {
3653     { Bad_Opcode },
3654     { "blcfill",        { { OP_LWP_E, 0 }, Ev }, 0 },
3655     { "blsfill",        { { OP_LWP_E, 0 }, Ev }, 0 },
3656     { "blcs",   { { OP_LWP_E, 0 }, Ev }, 0 },
3657     { "tzmsk",  { { OP_LWP_E, 0 }, Ev }, 0 },
3658     { "blcic",  { { OP_LWP_E, 0 }, Ev }, 0 },
3659     { "blsic",  { { OP_LWP_E, 0 }, Ev }, 0 },
3660     { "t1mskc", { { OP_LWP_E, 0 }, Ev }, 0 },
3661   },
3662   /* REG_XOP_TBM_02 */
3663   {
3664     { Bad_Opcode },
3665     { "blcmsk", { { OP_LWP_E, 0 }, Ev }, 0 },
3666     { Bad_Opcode },
3667     { Bad_Opcode },
3668     { Bad_Opcode },
3669     { Bad_Opcode },
3670     { "blci",   { { OP_LWP_E, 0 }, Ev }, 0 },
3671   },
3672 #define NEED_REG_TABLE
3673 #include "i386-dis-evex.h"
3674 #undef NEED_REG_TABLE
3675 };
3676
3677 static const struct dis386 prefix_table[][4] = {
3678   /* PREFIX_90 */
3679   {
3680     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3681     { "pause", { XX }, 0 },
3682     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3683     { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3684   },
3685
3686   /* PREFIX_0F10 */
3687   {
3688     { "movups", { XM, EXx }, PREFIX_OPCODE },
3689     { "movss",  { XM, EXd }, PREFIX_OPCODE },
3690     { "movupd", { XM, EXx }, PREFIX_OPCODE },
3691     { "movsd",  { XM, EXq }, PREFIX_OPCODE },
3692   },
3693
3694   /* PREFIX_0F11 */
3695   {
3696     { "movups", { EXxS, XM }, PREFIX_OPCODE },
3697     { "movss",  { EXdS, XM }, PREFIX_OPCODE },
3698     { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3699     { "movsd",  { EXqS, XM }, PREFIX_OPCODE },
3700   },
3701
3702   /* PREFIX_0F12 */
3703   {
3704     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3705     { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3706     { "movlpd", { XM, EXq }, PREFIX_OPCODE },
3707     { "movddup", { XM, EXq }, PREFIX_OPCODE },
3708   },
3709
3710   /* PREFIX_0F16 */
3711   {
3712     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3713     { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3714     { "movhpd", { XM, EXq }, PREFIX_OPCODE },
3715   },
3716
3717   /* PREFIX_0F1A */
3718   {
3719     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3720     { "bndcl",  { Gbnd, Ev_bnd }, 0 },
3721     { "bndmov", { Gbnd, Ebnd }, 0 },
3722     { "bndcu",  { Gbnd, Ev_bnd }, 0 },
3723   },
3724
3725   /* PREFIX_0F1B */
3726   {
3727     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3728     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3729     { "bndmov", { Ebnd, Gbnd }, 0 },
3730     { "bndcn",  { Gbnd, Ev_bnd }, 0 },
3731   },
3732
3733   /* PREFIX_0F2A */
3734   {
3735     { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3736     { "cvtsi2ss%LQ", { XM, Ev }, PREFIX_OPCODE },
3737     { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3738     { "cvtsi2sd%LQ", { XM, Ev }, 0 },
3739   },
3740
3741   /* PREFIX_0F2B */
3742   {
3743     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3744     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3745     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3746     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3747   },
3748
3749   /* PREFIX_0F2C */
3750   {
3751     { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3752     { "cvttss2siY", { Gv, EXd }, PREFIX_OPCODE },
3753     { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3754     { "cvttsd2siY", { Gv, EXq }, PREFIX_OPCODE },
3755   },
3756
3757   /* PREFIX_0F2D */
3758   {
3759     { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3760     { "cvtss2siY", { Gv, EXd }, PREFIX_OPCODE },
3761     { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3762     { "cvtsd2siY", { Gv, EXq }, PREFIX_OPCODE },
3763   },
3764
3765   /* PREFIX_0F2E */
3766   {
3767     { "ucomiss",{ XM, EXd }, 0 },
3768     { Bad_Opcode },
3769     { "ucomisd",{ XM, EXq }, 0 },
3770   },
3771
3772   /* PREFIX_0F2F */
3773   {
3774     { "comiss", { XM, EXd }, 0 },
3775     { Bad_Opcode },
3776     { "comisd", { XM, EXq }, 0 },
3777   },
3778
3779   /* PREFIX_0F51 */
3780   {
3781     { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3782     { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3783     { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3784     { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3785   },
3786
3787   /* PREFIX_0F52 */
3788   {
3789     { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3790     { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3791   },
3792
3793   /* PREFIX_0F53 */
3794   {
3795     { "rcpps",  { XM, EXx }, PREFIX_OPCODE },
3796     { "rcpss",  { XM, EXd }, PREFIX_OPCODE },
3797   },
3798
3799   /* PREFIX_0F58 */
3800   {
3801     { "addps", { XM, EXx }, PREFIX_OPCODE },
3802     { "addss", { XM, EXd }, PREFIX_OPCODE },
3803     { "addpd", { XM, EXx }, PREFIX_OPCODE },
3804     { "addsd", { XM, EXq }, PREFIX_OPCODE },
3805   },
3806
3807   /* PREFIX_0F59 */
3808   {
3809     { "mulps",  { XM, EXx }, PREFIX_OPCODE },
3810     { "mulss",  { XM, EXd }, PREFIX_OPCODE },
3811     { "mulpd",  { XM, EXx }, PREFIX_OPCODE },
3812     { "mulsd",  { XM, EXq }, PREFIX_OPCODE },
3813   },
3814
3815   /* PREFIX_0F5A */
3816   {
3817     { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3818     { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3819     { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3820     { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3821   },
3822
3823   /* PREFIX_0F5B */
3824   {
3825     { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3826     { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3827     { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3828   },
3829
3830   /* PREFIX_0F5C */
3831   {
3832     { "subps",  { XM, EXx }, PREFIX_OPCODE },
3833     { "subss",  { XM, EXd }, PREFIX_OPCODE },
3834     { "subpd",  { XM, EXx }, PREFIX_OPCODE },
3835     { "subsd",  { XM, EXq }, PREFIX_OPCODE },
3836   },
3837
3838   /* PREFIX_0F5D */
3839   {
3840     { "minps",  { XM, EXx }, PREFIX_OPCODE },
3841     { "minss",  { XM, EXd }, PREFIX_OPCODE },
3842     { "minpd",  { XM, EXx }, PREFIX_OPCODE },
3843     { "minsd",  { XM, EXq }, PREFIX_OPCODE },
3844   },
3845
3846   /* PREFIX_0F5E */
3847   {
3848     { "divps",  { XM, EXx }, PREFIX_OPCODE },
3849     { "divss",  { XM, EXd }, PREFIX_OPCODE },
3850     { "divpd",  { XM, EXx }, PREFIX_OPCODE },
3851     { "divsd",  { XM, EXq }, PREFIX_OPCODE },
3852   },
3853
3854   /* PREFIX_0F5F */
3855   {
3856     { "maxps",  { XM, EXx }, PREFIX_OPCODE },
3857     { "maxss",  { XM, EXd }, PREFIX_OPCODE },
3858     { "maxpd",  { XM, EXx }, PREFIX_OPCODE },
3859     { "maxsd",  { XM, EXq }, PREFIX_OPCODE },
3860   },
3861
3862   /* PREFIX_0F60 */
3863   {
3864     { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3865     { Bad_Opcode },
3866     { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3867   },
3868
3869   /* PREFIX_0F61 */
3870   {
3871     { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3872     { Bad_Opcode },
3873     { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3874   },
3875
3876   /* PREFIX_0F62 */
3877   {
3878     { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3879     { Bad_Opcode },
3880     { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3881   },
3882
3883   /* PREFIX_0F6C */
3884   {
3885     { Bad_Opcode },
3886     { Bad_Opcode },
3887     { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE },
3888   },
3889
3890   /* PREFIX_0F6D */
3891   {
3892     { Bad_Opcode },
3893     { Bad_Opcode },
3894     { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE },
3895   },
3896
3897   /* PREFIX_0F6F */
3898   {
3899     { "movq",   { MX, EM }, PREFIX_OPCODE },
3900     { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3901     { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3902   },
3903
3904   /* PREFIX_0F70 */
3905   {
3906     { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3907     { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3908     { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3909     { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3910   },
3911
3912   /* PREFIX_0F73_REG_3 */
3913   {
3914     { Bad_Opcode },
3915     { Bad_Opcode },
3916     { "psrldq", { XS, Ib }, 0 },
3917   },
3918
3919   /* PREFIX_0F73_REG_7 */
3920   {
3921     { Bad_Opcode },
3922     { Bad_Opcode },
3923     { "pslldq", { XS, Ib }, 0 },
3924   },
3925
3926   /* PREFIX_0F78 */
3927   {
3928     {"vmread",  { Em, Gm }, 0 },
3929     { Bad_Opcode },
3930     {"extrq",   { XS, Ib, Ib }, 0 },
3931     {"insertq", { XM, XS, Ib, Ib }, 0 },
3932   },
3933
3934   /* PREFIX_0F79 */
3935   {
3936     {"vmwrite", { Gm, Em }, 0 },
3937     { Bad_Opcode },
3938     {"extrq",   { XM, XS }, 0 },
3939     {"insertq", { XM, XS }, 0 },
3940   },
3941
3942   /* PREFIX_0F7C */
3943   {
3944     { Bad_Opcode },
3945     { Bad_Opcode },
3946     { "haddpd", { XM, EXx }, PREFIX_OPCODE },
3947     { "haddps", { XM, EXx }, PREFIX_OPCODE },
3948   },
3949
3950   /* PREFIX_0F7D */
3951   {
3952     { Bad_Opcode },
3953     { Bad_Opcode },
3954     { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
3955     { "hsubps", { XM, EXx }, PREFIX_OPCODE },
3956   },
3957
3958   /* PREFIX_0F7E */
3959   {
3960     { "movK",   { Edq, MX }, PREFIX_OPCODE },
3961     { "movq",   { XM, EXq }, PREFIX_OPCODE },
3962     { "movK",   { Edq, XM }, PREFIX_OPCODE },
3963   },
3964
3965   /* PREFIX_0F7F */
3966   {
3967     { "movq",   { EMS, MX }, PREFIX_OPCODE },
3968     { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
3969     { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
3970   },
3971
3972   /* PREFIX_0FAE_REG_0 */
3973   {
3974     { Bad_Opcode },
3975     { "rdfsbase", { Ev }, 0 },
3976   },
3977
3978   /* PREFIX_0FAE_REG_1 */
3979   {
3980     { Bad_Opcode },
3981     { "rdgsbase", { Ev }, 0 },
3982   },
3983
3984   /* PREFIX_0FAE_REG_2 */
3985   {
3986     { Bad_Opcode },
3987     { "wrfsbase", { Ev }, 0 },
3988   },
3989
3990   /* PREFIX_0FAE_REG_3 */
3991   {
3992     { Bad_Opcode },
3993     { "wrgsbase", { Ev }, 0 },
3994   },
3995
3996   /* PREFIX_0FAE_REG_6 */
3997   {
3998     { "xsaveopt",      { FXSAVE }, 0 },
3999     { Bad_Opcode },
4000     { "clwb",   { Mb }, 0 },
4001   },
4002
4003   /* PREFIX_0FAE_REG_7 */
4004   {
4005     { "clflush",        { Mb }, 0 },
4006     { Bad_Opcode },
4007     { "clflushopt",     { Mb }, 0 },
4008   },
4009
4010   /* PREFIX_RM_0_0FAE_REG_7 */
4011   {
4012     { "sfence",         { Skip_MODRM }, 0 },
4013     { Bad_Opcode },
4014     { "pcommit",                { Skip_MODRM }, 0 },
4015   },
4016
4017   /* PREFIX_0FB8 */
4018   {
4019     { Bad_Opcode },
4020     { "popcntS", { Gv, Ev }, 0 },
4021   },
4022
4023   /* PREFIX_0FBC */
4024   {
4025     { "bsfS",   { Gv, Ev }, 0 },
4026     { "tzcntS", { Gv, Ev }, 0 },
4027     { "bsfS",   { Gv, Ev }, 0 },
4028   },
4029
4030   /* PREFIX_0FBD */
4031   {
4032     { "bsrS",   { Gv, Ev }, 0 },
4033     { "lzcntS", { Gv, Ev }, 0 },
4034     { "bsrS",   { Gv, Ev }, 0 },
4035   },
4036
4037   /* PREFIX_0FC2 */
4038   {
4039     { "cmpps",  { XM, EXx, CMP }, PREFIX_OPCODE },
4040     { "cmpss",  { XM, EXd, CMP }, PREFIX_OPCODE },
4041     { "cmppd",  { XM, EXx, CMP }, PREFIX_OPCODE },
4042     { "cmpsd",  { XM, EXq, CMP }, PREFIX_OPCODE },
4043   },
4044
4045   /* PREFIX_0FC3 */
4046   {
4047     { "movntiS", { Ma, Gv }, PREFIX_OPCODE },
4048   },
4049
4050   /* PREFIX_MOD_0_0FC7_REG_6 */
4051   {
4052     { "vmptrld",{ Mq }, 0 },
4053     { "vmxon",  { Mq }, 0 },
4054     { "vmclear",{ Mq }, 0 },
4055   },
4056
4057   /* PREFIX_MOD_3_0FC7_REG_6 */
4058   {
4059     { "rdrand", { Ev }, 0 },
4060     { Bad_Opcode },
4061     { "rdrand", { Ev }, 0 }
4062   },
4063
4064   /* PREFIX_MOD_3_0FC7_REG_7 */
4065   {
4066     { "rdseed", { Ev }, 0 },
4067     { Bad_Opcode },
4068     { "rdseed", { Ev }, 0 },
4069   },
4070
4071   /* PREFIX_0FD0 */
4072   {
4073     { Bad_Opcode },
4074     { Bad_Opcode },
4075     { "addsubpd", { XM, EXx }, 0 },
4076     { "addsubps", { XM, EXx }, 0 },
4077   },
4078
4079   /* PREFIX_0FD6 */
4080   {
4081     { Bad_Opcode },
4082     { "movq2dq",{ XM, MS }, 0 },
4083     { "movq",   { EXqS, XM }, 0 },
4084     { "movdq2q",{ MX, XS }, 0 },
4085   },
4086
4087   /* PREFIX_0FE6 */
4088   {
4089     { Bad_Opcode },
4090     { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
4091     { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
4092     { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
4093   },
4094
4095   /* PREFIX_0FE7 */
4096   {
4097     { "movntq", { Mq, MX }, PREFIX_OPCODE },
4098     { Bad_Opcode },
4099     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
4100   },
4101
4102   /* PREFIX_0FF0 */
4103   {
4104     { Bad_Opcode },
4105     { Bad_Opcode },
4106     { Bad_Opcode },
4107     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4108   },
4109
4110   /* PREFIX_0FF7 */
4111   {
4112     { "maskmovq", { MX, MS }, PREFIX_OPCODE },
4113     { Bad_Opcode },
4114     { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
4115   },
4116
4117   /* PREFIX_0F3810 */
4118   {
4119     { Bad_Opcode },
4120     { Bad_Opcode },
4121     { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4122   },
4123
4124   /* PREFIX_0F3814 */
4125   {
4126     { Bad_Opcode },
4127     { Bad_Opcode },
4128     { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4129   },
4130
4131   /* PREFIX_0F3815 */
4132   {
4133     { Bad_Opcode },
4134     { Bad_Opcode },
4135     { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4136   },
4137
4138   /* PREFIX_0F3817 */
4139   {
4140     { Bad_Opcode },
4141     { Bad_Opcode },
4142     { "ptest",  { XM, EXx }, PREFIX_OPCODE },
4143   },
4144
4145   /* PREFIX_0F3820 */
4146   {
4147     { Bad_Opcode },
4148     { Bad_Opcode },
4149     { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE },
4150   },
4151
4152   /* PREFIX_0F3821 */
4153   {
4154     { Bad_Opcode },
4155     { Bad_Opcode },
4156     { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE },
4157   },
4158
4159   /* PREFIX_0F3822 */
4160   {
4161     { Bad_Opcode },
4162     { Bad_Opcode },
4163     { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE },
4164   },
4165
4166   /* PREFIX_0F3823 */
4167   {
4168     { Bad_Opcode },
4169     { Bad_Opcode },
4170     { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE },
4171   },
4172
4173   /* PREFIX_0F3824 */
4174   {
4175     { Bad_Opcode },
4176     { Bad_Opcode },
4177     { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE },
4178   },
4179
4180   /* PREFIX_0F3825 */
4181   {
4182     { Bad_Opcode },
4183     { Bad_Opcode },
4184     { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE },
4185   },
4186
4187   /* PREFIX_0F3828 */
4188   {
4189     { Bad_Opcode },
4190     { Bad_Opcode },
4191     { "pmuldq", { XM, EXx }, PREFIX_OPCODE },
4192   },
4193
4194   /* PREFIX_0F3829 */
4195   {
4196     { Bad_Opcode },
4197     { Bad_Opcode },
4198     { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE },
4199   },
4200
4201   /* PREFIX_0F382A */
4202   {
4203     { Bad_Opcode },
4204     { Bad_Opcode },
4205     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4206   },
4207
4208   /* PREFIX_0F382B */
4209   {
4210     { Bad_Opcode },
4211     { Bad_Opcode },
4212     { "packusdw", { XM, EXx }, PREFIX_OPCODE },
4213   },
4214
4215   /* PREFIX_0F3830 */
4216   {
4217     { Bad_Opcode },
4218     { Bad_Opcode },
4219     { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE },
4220   },
4221
4222   /* PREFIX_0F3831 */
4223   {
4224     { Bad_Opcode },
4225     { Bad_Opcode },
4226     { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE },
4227   },
4228
4229   /* PREFIX_0F3832 */
4230   {
4231     { Bad_Opcode },
4232     { Bad_Opcode },
4233     { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE },
4234   },
4235
4236   /* PREFIX_0F3833 */
4237   {
4238     { Bad_Opcode },
4239     { Bad_Opcode },
4240     { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE },
4241   },
4242
4243   /* PREFIX_0F3834 */
4244   {
4245     { Bad_Opcode },
4246     { Bad_Opcode },
4247     { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE },
4248   },
4249
4250   /* PREFIX_0F3835 */
4251   {
4252     { Bad_Opcode },
4253     { Bad_Opcode },
4254     { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE },
4255   },
4256
4257   /* PREFIX_0F3837 */
4258   {
4259     { Bad_Opcode },
4260     { Bad_Opcode },
4261     { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE },
4262   },
4263
4264   /* PREFIX_0F3838 */
4265   {
4266     { Bad_Opcode },
4267     { Bad_Opcode },
4268     { "pminsb", { XM, EXx }, PREFIX_OPCODE },
4269   },
4270
4271   /* PREFIX_0F3839 */
4272   {
4273     { Bad_Opcode },
4274     { Bad_Opcode },
4275     { "pminsd", { XM, EXx }, PREFIX_OPCODE },
4276   },
4277
4278   /* PREFIX_0F383A */
4279   {
4280     { Bad_Opcode },
4281     { Bad_Opcode },
4282     { "pminuw", { XM, EXx }, PREFIX_OPCODE },
4283   },
4284
4285   /* PREFIX_0F383B */
4286   {
4287     { Bad_Opcode },
4288     { Bad_Opcode },
4289     { "pminud", { XM, EXx }, PREFIX_OPCODE },
4290   },
4291
4292   /* PREFIX_0F383C */
4293   {
4294     { Bad_Opcode },
4295     { Bad_Opcode },
4296     { "pmaxsb", { XM, EXx }, PREFIX_OPCODE },
4297   },
4298
4299   /* PREFIX_0F383D */
4300   {
4301     { Bad_Opcode },
4302     { Bad_Opcode },
4303     { "pmaxsd", { XM, EXx }, PREFIX_OPCODE },
4304   },
4305
4306   /* PREFIX_0F383E */
4307   {
4308     { Bad_Opcode },
4309     { Bad_Opcode },
4310     { "pmaxuw", { XM, EXx }, PREFIX_OPCODE },
4311   },
4312
4313   /* PREFIX_0F383F */
4314   {
4315     { Bad_Opcode },
4316     { Bad_Opcode },
4317     { "pmaxud", { XM, EXx }, PREFIX_OPCODE },
4318   },
4319
4320   /* PREFIX_0F3840 */
4321   {
4322     { Bad_Opcode },
4323     { Bad_Opcode },
4324     { "pmulld", { XM, EXx }, PREFIX_OPCODE },
4325   },
4326
4327   /* PREFIX_0F3841 */
4328   {
4329     { Bad_Opcode },
4330     { Bad_Opcode },
4331     { "phminposuw", { XM, EXx }, PREFIX_OPCODE },
4332   },
4333
4334   /* PREFIX_0F3880 */
4335   {
4336     { Bad_Opcode },
4337     { Bad_Opcode },
4338     { "invept", { Gm, Mo }, PREFIX_OPCODE },
4339   },
4340
4341   /* PREFIX_0F3881 */
4342   {
4343     { Bad_Opcode },
4344     { Bad_Opcode },
4345     { "invvpid", { Gm, Mo }, PREFIX_OPCODE },
4346   },
4347
4348   /* PREFIX_0F3882 */
4349   {
4350     { Bad_Opcode },
4351     { Bad_Opcode },
4352     { "invpcid", { Gm, M }, PREFIX_OPCODE },
4353   },
4354
4355   /* PREFIX_0F38C8 */
4356   {
4357     { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4358   },
4359
4360   /* PREFIX_0F38C9 */
4361   {
4362     { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4363   },
4364
4365   /* PREFIX_0F38CA */
4366   {
4367     { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4368   },
4369
4370   /* PREFIX_0F38CB */
4371   {
4372     { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4373   },
4374
4375   /* PREFIX_0F38CC */
4376   {
4377     { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4378   },
4379
4380   /* PREFIX_0F38CD */
4381   {
4382     { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4383   },
4384
4385   /* PREFIX_0F38DB */
4386   {
4387     { Bad_Opcode },
4388     { Bad_Opcode },
4389     { "aesimc", { XM, EXx }, PREFIX_OPCODE },
4390   },
4391
4392   /* PREFIX_0F38DC */
4393   {
4394     { Bad_Opcode },
4395     { Bad_Opcode },
4396     { "aesenc", { XM, EXx }, PREFIX_OPCODE },
4397   },
4398
4399   /* PREFIX_0F38DD */
4400   {
4401     { Bad_Opcode },
4402     { Bad_Opcode },
4403     { "aesenclast", { XM, EXx }, PREFIX_OPCODE },
4404   },
4405
4406   /* PREFIX_0F38DE */
4407   {
4408     { Bad_Opcode },
4409     { Bad_Opcode },
4410     { "aesdec", { XM, EXx }, PREFIX_OPCODE },
4411   },
4412
4413   /* PREFIX_0F38DF */
4414   {
4415     { Bad_Opcode },
4416     { Bad_Opcode },
4417     { "aesdeclast", { XM, EXx }, PREFIX_OPCODE },
4418   },
4419
4420   /* PREFIX_0F38F0 */
4421   {
4422     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4423     { Bad_Opcode },
4424     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4425     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE },
4426   },
4427
4428   /* PREFIX_0F38F1 */
4429   {
4430     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4431     { Bad_Opcode },
4432     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4433     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE },
4434   },
4435
4436   /* PREFIX_0F38F6 */
4437   {
4438     { Bad_Opcode },
4439     { "adoxS",  { Gdq, Edq}, PREFIX_OPCODE },
4440     { "adcxS",  { Gdq, Edq}, PREFIX_OPCODE },
4441     { Bad_Opcode },
4442   },
4443
4444   /* PREFIX_0F3A08 */
4445   {
4446     { Bad_Opcode },
4447     { Bad_Opcode },
4448     { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE },
4449   },
4450
4451   /* PREFIX_0F3A09 */
4452   {
4453     { Bad_Opcode },
4454     { Bad_Opcode },
4455     { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4456   },
4457
4458   /* PREFIX_0F3A0A */
4459   {
4460     { Bad_Opcode },
4461     { Bad_Opcode },
4462     { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE },
4463   },
4464
4465   /* PREFIX_0F3A0B */
4466   {
4467     { Bad_Opcode },
4468     { Bad_Opcode },
4469     { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE },
4470   },
4471
4472   /* PREFIX_0F3A0C */
4473   {
4474     { Bad_Opcode },
4475     { Bad_Opcode },
4476     { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE },
4477   },
4478
4479   /* PREFIX_0F3A0D */
4480   {
4481     { Bad_Opcode },
4482     { Bad_Opcode },
4483     { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4484   },
4485
4486   /* PREFIX_0F3A0E */
4487   {
4488     { Bad_Opcode },
4489     { Bad_Opcode },
4490     { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE },
4491   },
4492
4493   /* PREFIX_0F3A14 */
4494   {
4495     { Bad_Opcode },
4496     { Bad_Opcode },
4497     { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE },
4498   },
4499
4500   /* PREFIX_0F3A15 */
4501   {
4502     { Bad_Opcode },
4503     { Bad_Opcode },
4504     { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE },
4505   },
4506
4507   /* PREFIX_0F3A16 */
4508   {
4509     { Bad_Opcode },
4510     { Bad_Opcode },
4511     { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE },
4512   },
4513
4514   /* PREFIX_0F3A17 */
4515   {
4516     { Bad_Opcode },
4517     { Bad_Opcode },
4518     { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE },
4519   },
4520
4521   /* PREFIX_0F3A20 */
4522   {
4523     { Bad_Opcode },
4524     { Bad_Opcode },
4525     { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE },
4526   },
4527
4528   /* PREFIX_0F3A21 */
4529   {
4530     { Bad_Opcode },
4531     { Bad_Opcode },
4532     { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE },
4533   },
4534
4535   /* PREFIX_0F3A22 */
4536   {
4537     { Bad_Opcode },
4538     { Bad_Opcode },
4539     { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE },
4540   },
4541
4542   /* PREFIX_0F3A40 */
4543   {
4544     { Bad_Opcode },
4545     { Bad_Opcode },
4546     { "dpps",   { XM, EXx, Ib }, PREFIX_OPCODE },
4547   },
4548
4549   /* PREFIX_0F3A41 */
4550   {
4551     { Bad_Opcode },
4552     { Bad_Opcode },
4553     { "dppd",   { XM, EXx, Ib }, PREFIX_OPCODE },
4554   },
4555
4556   /* PREFIX_0F3A42 */
4557   {
4558     { Bad_Opcode },
4559     { Bad_Opcode },
4560     { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE },
4561   },
4562
4563   /* PREFIX_0F3A44 */
4564   {
4565     { Bad_Opcode },
4566     { Bad_Opcode },
4567     { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE },
4568   },
4569
4570   /* PREFIX_0F3A60 */
4571   {
4572     { Bad_Opcode },
4573     { Bad_Opcode },
4574     { "pcmpestrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4575   },
4576
4577   /* PREFIX_0F3A61 */
4578   {
4579     { Bad_Opcode },
4580     { Bad_Opcode },
4581     { "pcmpestri", { XM, EXx, Ib }, PREFIX_OPCODE },
4582   },
4583
4584   /* PREFIX_0F3A62 */
4585   {
4586     { Bad_Opcode },
4587     { Bad_Opcode },
4588     { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4589   },
4590
4591   /* PREFIX_0F3A63 */
4592   {
4593     { Bad_Opcode },
4594     { Bad_Opcode },
4595     { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE },
4596   },
4597
4598   /* PREFIX_0F3ACC */
4599   {
4600     { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4601   },
4602
4603   /* PREFIX_0F3ADF */
4604   {
4605     { Bad_Opcode },
4606     { Bad_Opcode },
4607     { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE },
4608   },
4609
4610   /* PREFIX_VEX_0F10 */
4611   {
4612     { VEX_W_TABLE (VEX_W_0F10_P_0) },
4613     { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) },
4614     { VEX_W_TABLE (VEX_W_0F10_P_2) },
4615     { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) },
4616   },
4617
4618   /* PREFIX_VEX_0F11 */
4619   {
4620     { VEX_W_TABLE (VEX_W_0F11_P_0) },
4621     { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) },
4622     { VEX_W_TABLE (VEX_W_0F11_P_2) },
4623     { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) },
4624   },
4625
4626   /* PREFIX_VEX_0F12 */
4627   {
4628     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4629     { VEX_W_TABLE (VEX_W_0F12_P_1) },
4630     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
4631     { VEX_W_TABLE (VEX_W_0F12_P_3) },
4632   },
4633
4634   /* PREFIX_VEX_0F16 */
4635   {
4636     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4637     { VEX_W_TABLE (VEX_W_0F16_P_1) },
4638     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
4639   },
4640
4641   /* PREFIX_VEX_0F2A */
4642   {
4643     { Bad_Opcode },
4644     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) },
4645     { Bad_Opcode },
4646     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) },
4647   },
4648
4649   /* PREFIX_VEX_0F2C */
4650   {
4651     { Bad_Opcode },
4652     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) },
4653     { Bad_Opcode },
4654     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) },
4655   },
4656
4657   /* PREFIX_VEX_0F2D */
4658   {
4659     { Bad_Opcode },
4660     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) },
4661     { Bad_Opcode },
4662     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) },
4663   },
4664
4665   /* PREFIX_VEX_0F2E */
4666   {
4667     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) },
4668     { Bad_Opcode },
4669     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) },
4670   },
4671
4672   /* PREFIX_VEX_0F2F */
4673   {
4674     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) },
4675     { Bad_Opcode },
4676     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) },
4677   },
4678
4679   /* PREFIX_VEX_0F41 */
4680   {
4681     { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4682     { Bad_Opcode },
4683     { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4684   },
4685
4686   /* PREFIX_VEX_0F42 */
4687   {
4688     { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4689     { Bad_Opcode },
4690     { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4691   },
4692
4693   /* PREFIX_VEX_0F44 */
4694   {
4695     { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4696     { Bad_Opcode },
4697     { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4698   },
4699
4700   /* PREFIX_VEX_0F45 */
4701   {
4702     { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4703     { Bad_Opcode },
4704     { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4705   },
4706
4707   /* PREFIX_VEX_0F46 */
4708   {
4709     { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4710     { Bad_Opcode },
4711     { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4712   },
4713
4714   /* PREFIX_VEX_0F47 */
4715   {
4716     { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4717     { Bad_Opcode },
4718     { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
4719   },
4720
4721   /* PREFIX_VEX_0F4A */
4722   {
4723     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
4724     { Bad_Opcode },
4725     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
4726   },
4727
4728   /* PREFIX_VEX_0F4B */
4729   {
4730     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
4731     { Bad_Opcode },
4732     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4733   },
4734
4735   /* PREFIX_VEX_0F51 */
4736   {
4737     { VEX_W_TABLE (VEX_W_0F51_P_0) },
4738     { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) },
4739     { VEX_W_TABLE (VEX_W_0F51_P_2) },
4740     { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) },
4741   },
4742
4743   /* PREFIX_VEX_0F52 */
4744   {
4745     { VEX_W_TABLE (VEX_W_0F52_P_0) },
4746     { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) },
4747   },
4748
4749   /* PREFIX_VEX_0F53 */
4750   {
4751     { VEX_W_TABLE (VEX_W_0F53_P_0) },
4752     { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) },
4753   },
4754
4755   /* PREFIX_VEX_0F58 */
4756   {
4757     { VEX_W_TABLE (VEX_W_0F58_P_0) },
4758     { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) },
4759     { VEX_W_TABLE (VEX_W_0F58_P_2) },
4760     { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) },
4761   },
4762
4763   /* PREFIX_VEX_0F59 */
4764   {
4765     { VEX_W_TABLE (VEX_W_0F59_P_0) },
4766     { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) },
4767     { VEX_W_TABLE (VEX_W_0F59_P_2) },
4768     { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) },
4769   },
4770
4771   /* PREFIX_VEX_0F5A */
4772   {
4773     { VEX_W_TABLE (VEX_W_0F5A_P_0) },
4774     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) },
4775     { "vcvtpd2ps%XY", { XMM, EXx }, 0 },
4776     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) },
4777   },
4778
4779   /* PREFIX_VEX_0F5B */
4780   {
4781     { VEX_W_TABLE (VEX_W_0F5B_P_0) },
4782     { VEX_W_TABLE (VEX_W_0F5B_P_1) },
4783     { VEX_W_TABLE (VEX_W_0F5B_P_2) },
4784   },
4785
4786   /* PREFIX_VEX_0F5C */
4787   {
4788     { VEX_W_TABLE (VEX_W_0F5C_P_0) },
4789     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) },
4790     { VEX_W_TABLE (VEX_W_0F5C_P_2) },
4791     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) },
4792   },
4793
4794   /* PREFIX_VEX_0F5D */
4795   {
4796     { VEX_W_TABLE (VEX_W_0F5D_P_0) },
4797     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) },
4798     { VEX_W_TABLE (VEX_W_0F5D_P_2) },
4799     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) },
4800   },
4801
4802   /* PREFIX_VEX_0F5E */
4803   {
4804     { VEX_W_TABLE (VEX_W_0F5E_P_0) },
4805     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) },
4806     { VEX_W_TABLE (VEX_W_0F5E_P_2) },
4807     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) },
4808   },
4809
4810   /* PREFIX_VEX_0F5F */
4811   {
4812     { VEX_W_TABLE (VEX_W_0F5F_P_0) },
4813     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) },
4814     { VEX_W_TABLE (VEX_W_0F5F_P_2) },
4815     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) },
4816   },
4817
4818   /* PREFIX_VEX_0F60 */
4819   {
4820     { Bad_Opcode },
4821     { Bad_Opcode },
4822     { VEX_W_TABLE (VEX_W_0F60_P_2) },
4823   },
4824
4825   /* PREFIX_VEX_0F61 */
4826   {
4827     { Bad_Opcode },
4828     { Bad_Opcode },
4829     { VEX_W_TABLE (VEX_W_0F61_P_2) },
4830   },
4831
4832   /* PREFIX_VEX_0F62 */
4833   {
4834     { Bad_Opcode },
4835     { Bad_Opcode },
4836     { VEX_W_TABLE (VEX_W_0F62_P_2) },
4837   },
4838
4839   /* PREFIX_VEX_0F63 */
4840   {
4841     { Bad_Opcode },
4842     { Bad_Opcode },
4843     { VEX_W_TABLE (VEX_W_0F63_P_2) },
4844   },
4845
4846   /* PREFIX_VEX_0F64 */
4847   {
4848     { Bad_Opcode },
4849     { Bad_Opcode },
4850     { VEX_W_TABLE (VEX_W_0F64_P_2) },
4851   },
4852
4853   /* PREFIX_VEX_0F65 */
4854   {
4855     { Bad_Opcode },
4856     { Bad_Opcode },
4857     { VEX_W_TABLE (VEX_W_0F65_P_2) },
4858   },
4859
4860   /* PREFIX_VEX_0F66 */
4861   {
4862     { Bad_Opcode },
4863     { Bad_Opcode },
4864     { VEX_W_TABLE (VEX_W_0F66_P_2) },
4865   },
4866
4867   /* PREFIX_VEX_0F67 */
4868   {
4869     { Bad_Opcode },
4870     { Bad_Opcode },
4871     { VEX_W_TABLE (VEX_W_0F67_P_2) },
4872   },
4873
4874   /* PREFIX_VEX_0F68 */
4875   {
4876     { Bad_Opcode },
4877     { Bad_Opcode },
4878     { VEX_W_TABLE (VEX_W_0F68_P_2) },
4879   },
4880
4881   /* PREFIX_VEX_0F69 */
4882   {
4883     { Bad_Opcode },
4884     { Bad_Opcode },
4885     { VEX_W_TABLE (VEX_W_0F69_P_2) },
4886   },
4887
4888   /* PREFIX_VEX_0F6A */
4889   {
4890     { Bad_Opcode },
4891     { Bad_Opcode },
4892     { VEX_W_TABLE (VEX_W_0F6A_P_2) },
4893   },
4894
4895   /* PREFIX_VEX_0F6B */
4896   {
4897     { Bad_Opcode },
4898     { Bad_Opcode },
4899     { VEX_W_TABLE (VEX_W_0F6B_P_2) },
4900   },
4901
4902   /* PREFIX_VEX_0F6C */
4903   {
4904     { Bad_Opcode },
4905     { Bad_Opcode },
4906     { VEX_W_TABLE (VEX_W_0F6C_P_2) },
4907   },
4908
4909   /* PREFIX_VEX_0F6D */
4910   {
4911     { Bad_Opcode },
4912     { Bad_Opcode },
4913     { VEX_W_TABLE (VEX_W_0F6D_P_2) },
4914   },
4915
4916   /* PREFIX_VEX_0F6E */
4917   {
4918     { Bad_Opcode },
4919     { Bad_Opcode },
4920     { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
4921   },
4922
4923   /* PREFIX_VEX_0F6F */
4924   {
4925     { Bad_Opcode },
4926     { VEX_W_TABLE (VEX_W_0F6F_P_1) },
4927     { VEX_W_TABLE (VEX_W_0F6F_P_2) },
4928   },
4929
4930   /* PREFIX_VEX_0F70 */
4931   {
4932     { Bad_Opcode },
4933     { VEX_W_TABLE (VEX_W_0F70_P_1) },
4934     { VEX_W_TABLE (VEX_W_0F70_P_2) },
4935     { VEX_W_TABLE (VEX_W_0F70_P_3) },
4936   },
4937
4938   /* PREFIX_VEX_0F71_REG_2 */
4939   {
4940     { Bad_Opcode },
4941     { Bad_Opcode },
4942     { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) },
4943   },
4944
4945   /* PREFIX_VEX_0F71_REG_4 */
4946   {
4947     { Bad_Opcode },
4948     { Bad_Opcode },
4949     { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) },
4950   },
4951
4952   /* PREFIX_VEX_0F71_REG_6 */
4953   {
4954     { Bad_Opcode },
4955     { Bad_Opcode },
4956     { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) },
4957   },
4958
4959   /* PREFIX_VEX_0F72_REG_2 */
4960   {
4961     { Bad_Opcode },
4962     { Bad_Opcode },
4963     { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) },
4964   },
4965
4966   /* PREFIX_VEX_0F72_REG_4 */
4967   {
4968     { Bad_Opcode },
4969     { Bad_Opcode },
4970     { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) },
4971   },
4972
4973   /* PREFIX_VEX_0F72_REG_6 */
4974   {
4975     { Bad_Opcode },
4976     { Bad_Opcode },
4977     { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) },
4978   },
4979
4980   /* PREFIX_VEX_0F73_REG_2 */
4981   {
4982     { Bad_Opcode },
4983     { Bad_Opcode },
4984     { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) },
4985   },
4986
4987   /* PREFIX_VEX_0F73_REG_3 */
4988   {
4989     { Bad_Opcode },
4990     { Bad_Opcode },
4991     { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) },
4992   },
4993
4994   /* PREFIX_VEX_0F73_REG_6 */
4995   {
4996     { Bad_Opcode },
4997     { Bad_Opcode },
4998     { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) },
4999   },
5000
5001   /* PREFIX_VEX_0F73_REG_7 */
5002   {
5003     { Bad_Opcode },
5004     { Bad_Opcode },
5005     { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) },
5006   },
5007
5008   /* PREFIX_VEX_0F74 */
5009   {
5010     { Bad_Opcode },
5011     { Bad_Opcode },
5012     { VEX_W_TABLE (VEX_W_0F74_P_2) },
5013   },
5014
5015   /* PREFIX_VEX_0F75 */
5016   {
5017     { Bad_Opcode },
5018     { Bad_Opcode },
5019     { VEX_W_TABLE (VEX_W_0F75_P_2) },
5020   },
5021
5022   /* PREFIX_VEX_0F76 */
5023   {
5024     { Bad_Opcode },
5025     { Bad_Opcode },
5026     { VEX_W_TABLE (VEX_W_0F76_P_2) },
5027   },
5028
5029   /* PREFIX_VEX_0F77 */
5030   {
5031     { VEX_W_TABLE (VEX_W_0F77_P_0) },
5032   },
5033
5034   /* PREFIX_VEX_0F7C */
5035   {
5036     { Bad_Opcode },
5037     { Bad_Opcode },
5038     { VEX_W_TABLE (VEX_W_0F7C_P_2) },
5039     { VEX_W_TABLE (VEX_W_0F7C_P_3) },
5040   },
5041
5042   /* PREFIX_VEX_0F7D */
5043   {
5044     { Bad_Opcode },
5045     { Bad_Opcode },
5046     { VEX_W_TABLE (VEX_W_0F7D_P_2) },
5047     { VEX_W_TABLE (VEX_W_0F7D_P_3) },
5048   },
5049
5050   /* PREFIX_VEX_0F7E */
5051   {
5052     { Bad_Opcode },
5053     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
5054     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
5055   },
5056
5057   /* PREFIX_VEX_0F7F */
5058   {
5059     { Bad_Opcode },
5060     { VEX_W_TABLE (VEX_W_0F7F_P_1) },
5061     { VEX_W_TABLE (VEX_W_0F7F_P_2) },
5062   },
5063
5064   /* PREFIX_VEX_0F90 */
5065   {
5066     { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
5067     { Bad_Opcode },
5068     { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
5069   },
5070
5071   /* PREFIX_VEX_0F91 */
5072   {
5073     { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
5074     { Bad_Opcode },
5075     { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
5076   },
5077
5078   /* PREFIX_VEX_0F92 */
5079   {
5080     { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
5081     { Bad_Opcode },
5082     { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
5083     { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
5084   },
5085
5086   /* PREFIX_VEX_0F93 */
5087   {
5088     { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
5089     { Bad_Opcode },
5090     { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
5091     { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
5092   },
5093
5094   /* PREFIX_VEX_0F98 */
5095   {
5096     { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
5097     { Bad_Opcode },
5098     { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
5099   },
5100
5101   /* PREFIX_VEX_0F99 */
5102   {
5103     { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5104     { Bad_Opcode },
5105     { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5106   },
5107
5108   /* PREFIX_VEX_0FC2 */
5109   {
5110     { VEX_W_TABLE (VEX_W_0FC2_P_0) },
5111     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) },
5112     { VEX_W_TABLE (VEX_W_0FC2_P_2) },
5113     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) },
5114   },
5115
5116   /* PREFIX_VEX_0FC4 */
5117   {
5118     { Bad_Opcode },
5119     { Bad_Opcode },
5120     { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5121   },
5122
5123   /* PREFIX_VEX_0FC5 */
5124   {
5125     { Bad_Opcode },
5126     { Bad_Opcode },
5127     { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5128   },
5129
5130   /* PREFIX_VEX_0FD0 */
5131   {
5132     { Bad_Opcode },
5133     { Bad_Opcode },
5134     { VEX_W_TABLE (VEX_W_0FD0_P_2) },
5135     { VEX_W_TABLE (VEX_W_0FD0_P_3) },
5136   },
5137
5138   /* PREFIX_VEX_0FD1 */
5139   {
5140     { Bad_Opcode },
5141     { Bad_Opcode },
5142     { VEX_W_TABLE (VEX_W_0FD1_P_2) },
5143   },
5144
5145   /* PREFIX_VEX_0FD2 */
5146   {
5147     { Bad_Opcode },
5148     { Bad_Opcode },
5149     { VEX_W_TABLE (VEX_W_0FD2_P_2) },
5150   },
5151
5152   /* PREFIX_VEX_0FD3 */
5153   {
5154     { Bad_Opcode },
5155     { Bad_Opcode },
5156     { VEX_W_TABLE (VEX_W_0FD3_P_2) },
5157   },
5158
5159   /* PREFIX_VEX_0FD4 */
5160   {
5161     { Bad_Opcode },
5162     { Bad_Opcode },
5163     { VEX_W_TABLE (VEX_W_0FD4_P_2) },
5164   },
5165
5166   /* PREFIX_VEX_0FD5 */
5167   {
5168     { Bad_Opcode },
5169     { Bad_Opcode },
5170     { VEX_W_TABLE (VEX_W_0FD5_P_2) },
5171   },
5172
5173   /* PREFIX_VEX_0FD6 */
5174   {
5175     { Bad_Opcode },
5176     { Bad_Opcode },
5177     { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5178   },
5179
5180   /* PREFIX_VEX_0FD7 */
5181   {
5182     { Bad_Opcode },
5183     { Bad_Opcode },
5184     { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5185   },
5186
5187   /* PREFIX_VEX_0FD8 */
5188   {
5189     { Bad_Opcode },
5190     { Bad_Opcode },
5191     { VEX_W_TABLE (VEX_W_0FD8_P_2) },
5192   },
5193
5194   /* PREFIX_VEX_0FD9 */
5195   {
5196     { Bad_Opcode },
5197     { Bad_Opcode },
5198     { VEX_W_TABLE (VEX_W_0FD9_P_2) },
5199   },
5200
5201   /* PREFIX_VEX_0FDA */
5202   {
5203     { Bad_Opcode },
5204     { Bad_Opcode },
5205     { VEX_W_TABLE (VEX_W_0FDA_P_2) },
5206   },
5207
5208   /* PREFIX_VEX_0FDB */
5209   {
5210     { Bad_Opcode },
5211     { Bad_Opcode },
5212     { VEX_W_TABLE (VEX_W_0FDB_P_2) },
5213   },
5214
5215   /* PREFIX_VEX_0FDC */
5216   {
5217     { Bad_Opcode },
5218     { Bad_Opcode },
5219     { VEX_W_TABLE (VEX_W_0FDC_P_2) },
5220   },
5221
5222   /* PREFIX_VEX_0FDD */
5223   {
5224     { Bad_Opcode },
5225     { Bad_Opcode },
5226     { VEX_W_TABLE (VEX_W_0FDD_P_2) },
5227   },
5228
5229   /* PREFIX_VEX_0FDE */
5230   {
5231     { Bad_Opcode },
5232     { Bad_Opcode },
5233     { VEX_W_TABLE (VEX_W_0FDE_P_2) },
5234   },
5235
5236   /* PREFIX_VEX_0FDF */
5237   {
5238     { Bad_Opcode },
5239     { Bad_Opcode },
5240     { VEX_W_TABLE (VEX_W_0FDF_P_2) },
5241   },
5242
5243   /* PREFIX_VEX_0FE0 */
5244   {
5245     { Bad_Opcode },
5246     { Bad_Opcode },
5247     { VEX_W_TABLE (VEX_W_0FE0_P_2) },
5248   },
5249
5250   /* PREFIX_VEX_0FE1 */
5251   {
5252     { Bad_Opcode },
5253     { Bad_Opcode },
5254     { VEX_W_TABLE (VEX_W_0FE1_P_2) },
5255   },
5256
5257   /* PREFIX_VEX_0FE2 */
5258   {
5259     { Bad_Opcode },
5260     { Bad_Opcode },
5261     { VEX_W_TABLE (VEX_W_0FE2_P_2) },
5262   },
5263
5264   /* PREFIX_VEX_0FE3 */
5265   {
5266     { Bad_Opcode },
5267     { Bad_Opcode },
5268     { VEX_W_TABLE (VEX_W_0FE3_P_2) },
5269   },
5270
5271   /* PREFIX_VEX_0FE4 */
5272   {
5273     { Bad_Opcode },
5274     { Bad_Opcode },
5275     { VEX_W_TABLE (VEX_W_0FE4_P_2) },
5276   },
5277
5278   /* PREFIX_VEX_0FE5 */
5279   {
5280     { Bad_Opcode },
5281     { Bad_Opcode },
5282     { VEX_W_TABLE (VEX_W_0FE5_P_2) },
5283   },
5284
5285   /* PREFIX_VEX_0FE6 */
5286   {
5287     { Bad_Opcode },
5288     { VEX_W_TABLE (VEX_W_0FE6_P_1) },
5289     { VEX_W_TABLE (VEX_W_0FE6_P_2) },
5290     { VEX_W_TABLE (VEX_W_0FE6_P_3) },
5291   },
5292
5293   /* PREFIX_VEX_0FE7 */
5294   {
5295     { Bad_Opcode },
5296     { Bad_Opcode },
5297     { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5298   },
5299
5300   /* PREFIX_VEX_0FE8 */
5301   {
5302     { Bad_Opcode },
5303     { Bad_Opcode },
5304     { VEX_W_TABLE (VEX_W_0FE8_P_2) },
5305   },
5306
5307   /* PREFIX_VEX_0FE9 */
5308   {
5309     { Bad_Opcode },
5310     { Bad_Opcode },
5311     { VEX_W_TABLE (VEX_W_0FE9_P_2) },
5312   },
5313
5314   /* PREFIX_VEX_0FEA */
5315   {
5316     { Bad_Opcode },
5317     { Bad_Opcode },
5318     { VEX_W_TABLE (VEX_W_0FEA_P_2) },
5319   },
5320
5321   /* PREFIX_VEX_0FEB */
5322   {
5323     { Bad_Opcode },
5324     { Bad_Opcode },
5325     { VEX_W_TABLE (VEX_W_0FEB_P_2) },
5326   },
5327
5328   /* PREFIX_VEX_0FEC */
5329   {
5330     { Bad_Opcode },
5331     { Bad_Opcode },
5332     { VEX_W_TABLE (VEX_W_0FEC_P_2) },
5333   },
5334
5335   /* PREFIX_VEX_0FED */
5336   {
5337     { Bad_Opcode },
5338     { Bad_Opcode },
5339     { VEX_W_TABLE (VEX_W_0FED_P_2) },
5340   },
5341
5342   /* PREFIX_VEX_0FEE */
5343   {
5344     { Bad_Opcode },
5345     { Bad_Opcode },
5346     { VEX_W_TABLE (VEX_W_0FEE_P_2) },
5347   },
5348
5349   /* PREFIX_VEX_0FEF */
5350   {
5351     { Bad_Opcode },
5352     { Bad_Opcode },
5353     { VEX_W_TABLE (VEX_W_0FEF_P_2) },
5354   },
5355
5356   /* PREFIX_VEX_0FF0 */
5357   {
5358     { Bad_Opcode },
5359     { Bad_Opcode },
5360     { Bad_Opcode },
5361     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5362   },
5363
5364   /* PREFIX_VEX_0FF1 */
5365   {
5366     { Bad_Opcode },
5367     { Bad_Opcode },
5368     { VEX_W_TABLE (VEX_W_0FF1_P_2) },
5369   },
5370
5371   /* PREFIX_VEX_0FF2 */
5372   {
5373     { Bad_Opcode },
5374     { Bad_Opcode },
5375     { VEX_W_TABLE (VEX_W_0FF2_P_2) },
5376   },
5377
5378   /* PREFIX_VEX_0FF3 */
5379   {
5380     { Bad_Opcode },
5381     { Bad_Opcode },
5382     { VEX_W_TABLE (VEX_W_0FF3_P_2) },
5383   },
5384
5385   /* PREFIX_VEX_0FF4 */
5386   {
5387     { Bad_Opcode },
5388     { Bad_Opcode },
5389     { VEX_W_TABLE (VEX_W_0FF4_P_2) },
5390   },
5391
5392   /* PREFIX_VEX_0FF5 */
5393   {
5394     { Bad_Opcode },
5395     { Bad_Opcode },
5396     { VEX_W_TABLE (VEX_W_0FF5_P_2) },
5397   },
5398
5399   /* PREFIX_VEX_0FF6 */
5400   {
5401     { Bad_Opcode },
5402     { Bad_Opcode },
5403     { VEX_W_TABLE (VEX_W_0FF6_P_2) },
5404   },
5405
5406   /* PREFIX_VEX_0FF7 */
5407   {
5408     { Bad_Opcode },
5409     { Bad_Opcode },
5410     { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5411   },
5412
5413   /* PREFIX_VEX_0FF8 */
5414   {
5415     { Bad_Opcode },
5416     { Bad_Opcode },
5417     { VEX_W_TABLE (VEX_W_0FF8_P_2) },
5418   },
5419
5420   /* PREFIX_VEX_0FF9 */
5421   {
5422     { Bad_Opcode },
5423     { Bad_Opcode },
5424     { VEX_W_TABLE (VEX_W_0FF9_P_2) },
5425   },
5426
5427   /* PREFIX_VEX_0FFA */
5428   {
5429     { Bad_Opcode },
5430     { Bad_Opcode },
5431     { VEX_W_TABLE (VEX_W_0FFA_P_2) },
5432   },
5433
5434   /* PREFIX_VEX_0FFB */
5435   {
5436     { Bad_Opcode },
5437     { Bad_Opcode },
5438     { VEX_W_TABLE (VEX_W_0FFB_P_2) },
5439   },
5440
5441   /* PREFIX_VEX_0FFC */
5442   {
5443     { Bad_Opcode },
5444     { Bad_Opcode },
5445     { VEX_W_TABLE (VEX_W_0FFC_P_2) },
5446   },
5447
5448   /* PREFIX_VEX_0FFD */
5449   {
5450     { Bad_Opcode },
5451     { Bad_Opcode },
5452     { VEX_W_TABLE (VEX_W_0FFD_P_2) },
5453   },
5454
5455   /* PREFIX_VEX_0FFE */
5456   {
5457     { Bad_Opcode },
5458     { Bad_Opcode },
5459     { VEX_W_TABLE (VEX_W_0FFE_P_2) },
5460   },
5461
5462   /* PREFIX_VEX_0F3800 */
5463   {
5464     { Bad_Opcode },
5465     { Bad_Opcode },
5466     { VEX_W_TABLE (VEX_W_0F3800_P_2) },
5467   },
5468
5469   /* PREFIX_VEX_0F3801 */
5470   {
5471     { Bad_Opcode },
5472     { Bad_Opcode },
5473     { VEX_W_TABLE (VEX_W_0F3801_P_2) },
5474   },
5475
5476   /* PREFIX_VEX_0F3802 */
5477   {
5478     { Bad_Opcode },
5479     { Bad_Opcode },
5480     { VEX_W_TABLE (VEX_W_0F3802_P_2) },
5481   },
5482
5483   /* PREFIX_VEX_0F3803 */
5484   {
5485     { Bad_Opcode },
5486     { Bad_Opcode },
5487     { VEX_W_TABLE (VEX_W_0F3803_P_2) },
5488   },
5489
5490   /* PREFIX_VEX_0F3804 */
5491   {
5492     { Bad_Opcode },
5493     { Bad_Opcode },
5494     { VEX_W_TABLE (VEX_W_0F3804_P_2) },
5495   },
5496
5497   /* PREFIX_VEX_0F3805 */
5498   {
5499     { Bad_Opcode },
5500     { Bad_Opcode },
5501     { VEX_W_TABLE (VEX_W_0F3805_P_2) },
5502   },
5503
5504   /* PREFIX_VEX_0F3806 */
5505   {
5506     { Bad_Opcode },
5507     { Bad_Opcode },
5508     { VEX_W_TABLE (VEX_W_0F3806_P_2) },
5509   },
5510
5511   /* PREFIX_VEX_0F3807 */
5512   {
5513     { Bad_Opcode },
5514     { Bad_Opcode },
5515     { VEX_W_TABLE (VEX_W_0F3807_P_2) },
5516   },
5517
5518   /* PREFIX_VEX_0F3808 */
5519   {
5520     { Bad_Opcode },
5521     { Bad_Opcode },
5522     { VEX_W_TABLE (VEX_W_0F3808_P_2) },
5523   },
5524
5525   /* PREFIX_VEX_0F3809 */
5526   {
5527     { Bad_Opcode },
5528     { Bad_Opcode },
5529     { VEX_W_TABLE (VEX_W_0F3809_P_2) },
5530   },
5531
5532   /* PREFIX_VEX_0F380A */
5533   {
5534     { Bad_Opcode },
5535     { Bad_Opcode },
5536     { VEX_W_TABLE (VEX_W_0F380A_P_2) },
5537   },
5538
5539   /* PREFIX_VEX_0F380B */
5540   {
5541     { Bad_Opcode },
5542     { Bad_Opcode },
5543     { VEX_W_TABLE (VEX_W_0F380B_P_2) },
5544   },
5545
5546   /* PREFIX_VEX_0F380C */
5547   {
5548     { Bad_Opcode },
5549     { Bad_Opcode },
5550     { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5551   },
5552
5553   /* PREFIX_VEX_0F380D */
5554   {
5555     { Bad_Opcode },
5556     { Bad_Opcode },
5557     { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5558   },
5559
5560   /* PREFIX_VEX_0F380E */
5561   {
5562     { Bad_Opcode },
5563     { Bad_Opcode },
5564     { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5565   },
5566
5567   /* PREFIX_VEX_0F380F */
5568   {
5569     { Bad_Opcode },
5570     { Bad_Opcode },
5571     { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5572   },
5573
5574   /* PREFIX_VEX_0F3813 */
5575   {
5576     { Bad_Opcode },
5577     { Bad_Opcode },
5578     { "vcvtph2ps", { XM, EXxmmq }, 0 },
5579   },
5580
5581   /* PREFIX_VEX_0F3816 */
5582   {
5583     { Bad_Opcode },
5584     { Bad_Opcode },
5585     { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5586   },
5587
5588   /* PREFIX_VEX_0F3817 */
5589   {
5590     { Bad_Opcode },
5591     { Bad_Opcode },
5592     { VEX_W_TABLE (VEX_W_0F3817_P_2) },
5593   },
5594
5595   /* PREFIX_VEX_0F3818 */
5596   {
5597     { Bad_Opcode },
5598     { Bad_Opcode },
5599     { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5600   },
5601
5602   /* PREFIX_VEX_0F3819 */
5603   {
5604     { Bad_Opcode },
5605     { Bad_Opcode },
5606     { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5607   },
5608
5609   /* PREFIX_VEX_0F381A */
5610   {
5611     { Bad_Opcode },
5612     { Bad_Opcode },
5613     { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5614   },
5615
5616   /* PREFIX_VEX_0F381C */
5617   {
5618     { Bad_Opcode },
5619     { Bad_Opcode },
5620     { VEX_W_TABLE (VEX_W_0F381C_P_2) },
5621   },
5622
5623   /* PREFIX_VEX_0F381D */
5624   {
5625     { Bad_Opcode },
5626     { Bad_Opcode },
5627     { VEX_W_TABLE (VEX_W_0F381D_P_2) },
5628   },
5629
5630   /* PREFIX_VEX_0F381E */
5631   {
5632     { Bad_Opcode },
5633     { Bad_Opcode },
5634     { VEX_W_TABLE (VEX_W_0F381E_P_2) },
5635   },
5636
5637   /* PREFIX_VEX_0F3820 */
5638   {
5639     { Bad_Opcode },
5640     { Bad_Opcode },
5641     { VEX_W_TABLE (VEX_W_0F3820_P_2) },
5642   },
5643
5644   /* PREFIX_VEX_0F3821 */
5645   {
5646     { Bad_Opcode },
5647     { Bad_Opcode },
5648     { VEX_W_TABLE (VEX_W_0F3821_P_2) },
5649   },
5650
5651   /* PREFIX_VEX_0F3822 */
5652   {
5653     { Bad_Opcode },
5654     { Bad_Opcode },
5655     { VEX_W_TABLE (VEX_W_0F3822_P_2) },
5656   },
5657
5658   /* PREFIX_VEX_0F3823 */
5659   {
5660     { Bad_Opcode },
5661     { Bad_Opcode },
5662     { VEX_W_TABLE (VEX_W_0F3823_P_2) },
5663   },
5664
5665   /* PREFIX_VEX_0F3824 */
5666   {
5667     { Bad_Opcode },
5668     { Bad_Opcode },
5669     { VEX_W_TABLE (VEX_W_0F3824_P_2) },
5670   },
5671
5672   /* PREFIX_VEX_0F3825 */
5673   {
5674     { Bad_Opcode },
5675     { Bad_Opcode },
5676     { VEX_W_TABLE (VEX_W_0F3825_P_2) },
5677   },
5678
5679   /* PREFIX_VEX_0F3828 */
5680   {
5681     { Bad_Opcode },
5682     { Bad_Opcode },
5683     { VEX_W_TABLE (VEX_W_0F3828_P_2) },
5684   },
5685
5686   /* PREFIX_VEX_0F3829 */
5687   {
5688     { Bad_Opcode },
5689     { Bad_Opcode },
5690     { VEX_W_TABLE (VEX_W_0F3829_P_2) },
5691   },
5692
5693   /* PREFIX_VEX_0F382A */
5694   {
5695     { Bad_Opcode },
5696     { Bad_Opcode },
5697     { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5698   },
5699
5700   /* PREFIX_VEX_0F382B */
5701   {
5702     { Bad_Opcode },
5703     { Bad_Opcode },
5704     { VEX_W_TABLE (VEX_W_0F382B_P_2) },
5705   },
5706
5707   /* PREFIX_VEX_0F382C */
5708   {
5709     { Bad_Opcode },
5710     { Bad_Opcode },
5711      { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5712   },
5713
5714   /* PREFIX_VEX_0F382D */
5715   {
5716     { Bad_Opcode },
5717     { Bad_Opcode },
5718      { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5719   },
5720
5721   /* PREFIX_VEX_0F382E */
5722   {
5723     { Bad_Opcode },
5724     { Bad_Opcode },
5725      { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5726   },
5727
5728   /* PREFIX_VEX_0F382F */
5729   {
5730     { Bad_Opcode },
5731     { Bad_Opcode },
5732      { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5733   },
5734
5735   /* PREFIX_VEX_0F3830 */
5736   {
5737     { Bad_Opcode },
5738     { Bad_Opcode },
5739     { VEX_W_TABLE (VEX_W_0F3830_P_2) },
5740   },
5741
5742   /* PREFIX_VEX_0F3831 */
5743   {
5744     { Bad_Opcode },
5745     { Bad_Opcode },
5746     { VEX_W_TABLE (VEX_W_0F3831_P_2) },
5747   },
5748
5749   /* PREFIX_VEX_0F3832 */
5750   {
5751     { Bad_Opcode },
5752     { Bad_Opcode },
5753     { VEX_W_TABLE (VEX_W_0F3832_P_2) },
5754   },
5755
5756   /* PREFIX_VEX_0F3833 */
5757   {
5758     { Bad_Opcode },
5759     { Bad_Opcode },
5760     { VEX_W_TABLE (VEX_W_0F3833_P_2) },
5761   },
5762
5763   /* PREFIX_VEX_0F3834 */
5764   {
5765     { Bad_Opcode },
5766     { Bad_Opcode },
5767     { VEX_W_TABLE (VEX_W_0F3834_P_2) },
5768   },
5769
5770   /* PREFIX_VEX_0F3835 */
5771   {
5772     { Bad_Opcode },
5773     { Bad_Opcode },
5774     { VEX_W_TABLE (VEX_W_0F3835_P_2) },
5775   },
5776
5777   /* PREFIX_VEX_0F3836 */
5778   {
5779     { Bad_Opcode },
5780     { Bad_Opcode },
5781     { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5782   },
5783
5784   /* PREFIX_VEX_0F3837 */
5785   {
5786     { Bad_Opcode },
5787     { Bad_Opcode },
5788     { VEX_W_TABLE (VEX_W_0F3837_P_2) },
5789   },
5790
5791   /* PREFIX_VEX_0F3838 */
5792   {
5793     { Bad_Opcode },
5794     { Bad_Opcode },
5795     { VEX_W_TABLE (VEX_W_0F3838_P_2) },
5796   },
5797
5798   /* PREFIX_VEX_0F3839 */
5799   {
5800     { Bad_Opcode },
5801     { Bad_Opcode },
5802     { VEX_W_TABLE (VEX_W_0F3839_P_2) },
5803   },
5804
5805   /* PREFIX_VEX_0F383A */
5806   {
5807     { Bad_Opcode },
5808     { Bad_Opcode },
5809     { VEX_W_TABLE (VEX_W_0F383A_P_2) },
5810   },
5811
5812   /* PREFIX_VEX_0F383B */
5813   {
5814     { Bad_Opcode },
5815     { Bad_Opcode },
5816     { VEX_W_TABLE (VEX_W_0F383B_P_2) },
5817   },
5818
5819   /* PREFIX_VEX_0F383C */
5820   {
5821     { Bad_Opcode },
5822     { Bad_Opcode },
5823     { VEX_W_TABLE (VEX_W_0F383C_P_2) },
5824   },
5825
5826   /* PREFIX_VEX_0F383D */
5827   {
5828     { Bad_Opcode },
5829     { Bad_Opcode },
5830     { VEX_W_TABLE (VEX_W_0F383D_P_2) },
5831   },
5832
5833   /* PREFIX_VEX_0F383E */
5834   {
5835     { Bad_Opcode },
5836     { Bad_Opcode },
5837     { VEX_W_TABLE (VEX_W_0F383E_P_2) },
5838   },
5839
5840   /* PREFIX_VEX_0F383F */
5841   {
5842     { Bad_Opcode },
5843     { Bad_Opcode },
5844     { VEX_W_TABLE (VEX_W_0F383F_P_2) },
5845   },
5846
5847   /* PREFIX_VEX_0F3840 */
5848   {
5849     { Bad_Opcode },
5850     { Bad_Opcode },
5851     { VEX_W_TABLE (VEX_W_0F3840_P_2) },
5852   },
5853
5854   /* PREFIX_VEX_0F3841 */
5855   {
5856     { Bad_Opcode },
5857     { Bad_Opcode },
5858     { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
5859   },
5860
5861   /* PREFIX_VEX_0F3845 */
5862   {
5863     { Bad_Opcode },
5864     { Bad_Opcode },
5865     { "vpsrlv%LW", { XM, Vex, EXx }, 0 },
5866   },
5867
5868   /* PREFIX_VEX_0F3846 */
5869   {
5870     { Bad_Opcode },
5871     { Bad_Opcode },
5872     { VEX_W_TABLE (VEX_W_0F3846_P_2) },
5873   },
5874
5875   /* PREFIX_VEX_0F3847 */
5876   {
5877     { Bad_Opcode },
5878     { Bad_Opcode },
5879     { "vpsllv%LW", { XM, Vex, EXx }, 0 },
5880   },
5881
5882   /* PREFIX_VEX_0F3858 */
5883   {
5884     { Bad_Opcode },
5885     { Bad_Opcode },
5886     { VEX_W_TABLE (VEX_W_0F3858_P_2) },
5887   },
5888
5889   /* PREFIX_VEX_0F3859 */
5890   {
5891     { Bad_Opcode },
5892     { Bad_Opcode },
5893     { VEX_W_TABLE (VEX_W_0F3859_P_2) },
5894   },
5895
5896   /* PREFIX_VEX_0F385A */
5897   {
5898     { Bad_Opcode },
5899     { Bad_Opcode },
5900     { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
5901   },
5902
5903   /* PREFIX_VEX_0F3878 */
5904   {
5905     { Bad_Opcode },
5906     { Bad_Opcode },
5907     { VEX_W_TABLE (VEX_W_0F3878_P_2) },
5908   },
5909
5910   /* PREFIX_VEX_0F3879 */
5911   {
5912     { Bad_Opcode },
5913     { Bad_Opcode },
5914     { VEX_W_TABLE (VEX_W_0F3879_P_2) },
5915   },
5916
5917   /* PREFIX_VEX_0F388C */
5918   {
5919     { Bad_Opcode },
5920     { Bad_Opcode },
5921     { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
5922   },
5923
5924   /* PREFIX_VEX_0F388E */
5925   {
5926     { Bad_Opcode },
5927     { Bad_Opcode },
5928     { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
5929   },
5930
5931   /* PREFIX_VEX_0F3890 */
5932   {
5933     { Bad_Opcode },
5934     { Bad_Opcode },
5935     { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 },
5936   },
5937
5938   /* PREFIX_VEX_0F3891 */
5939   {
5940     { Bad_Opcode },
5941     { Bad_Opcode },
5942     { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
5943   },
5944
5945   /* PREFIX_VEX_0F3892 */
5946   {
5947     { Bad_Opcode },
5948     { Bad_Opcode },
5949     { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 },
5950   },
5951
5952   /* PREFIX_VEX_0F3893 */
5953   {
5954     { Bad_Opcode },
5955     { Bad_Opcode },
5956     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
5957   },
5958
5959   /* PREFIX_VEX_0F3896 */
5960   {
5961     { Bad_Opcode },
5962     { Bad_Opcode },
5963     { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 },
5964   },
5965
5966   /* PREFIX_VEX_0F3897 */
5967   {
5968     { Bad_Opcode },
5969     { Bad_Opcode },
5970     { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 },
5971   },
5972
5973   /* PREFIX_VEX_0F3898 */
5974   {
5975     { Bad_Opcode },
5976     { Bad_Opcode },
5977     { "vfmadd132p%XW", { XM, Vex, EXx }, 0 },
5978   },
5979
5980   /* PREFIX_VEX_0F3899 */
5981   {
5982     { Bad_Opcode },
5983     { Bad_Opcode },
5984     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
5985   },
5986
5987   /* PREFIX_VEX_0F389A */
5988   {
5989     { Bad_Opcode },
5990     { Bad_Opcode },
5991     { "vfmsub132p%XW", { XM, Vex, EXx }, 0 },
5992   },
5993
5994   /* PREFIX_VEX_0F389B */
5995   {
5996     { Bad_Opcode },
5997     { Bad_Opcode },
5998     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
5999   },
6000
6001   /* PREFIX_VEX_0F389C */
6002   {
6003     { Bad_Opcode },
6004     { Bad_Opcode },
6005     { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 },
6006   },
6007
6008   /* PREFIX_VEX_0F389D */
6009   {
6010     { Bad_Opcode },
6011     { Bad_Opcode },
6012     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6013   },
6014
6015   /* PREFIX_VEX_0F389E */
6016   {
6017     { Bad_Opcode },
6018     { Bad_Opcode },
6019     { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 },
6020   },
6021
6022   /* PREFIX_VEX_0F389F */
6023   {
6024     { Bad_Opcode },
6025     { Bad_Opcode },
6026     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6027   },
6028
6029   /* PREFIX_VEX_0F38A6 */
6030   {
6031     { Bad_Opcode },
6032     { Bad_Opcode },
6033     { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 },
6034     { Bad_Opcode },
6035   },
6036
6037   /* PREFIX_VEX_0F38A7 */
6038   {
6039     { Bad_Opcode },
6040     { Bad_Opcode },
6041     { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 },
6042   },
6043
6044   /* PREFIX_VEX_0F38A8 */
6045   {
6046     { Bad_Opcode },
6047     { Bad_Opcode },
6048     { "vfmadd213p%XW", { XM, Vex, EXx }, 0 },
6049   },
6050
6051   /* PREFIX_VEX_0F38A9 */
6052   {
6053     { Bad_Opcode },
6054     { Bad_Opcode },
6055     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6056   },
6057
6058   /* PREFIX_VEX_0F38AA */
6059   {
6060     { Bad_Opcode },
6061     { Bad_Opcode },
6062     { "vfmsub213p%XW", { XM, Vex, EXx }, 0 },
6063   },
6064
6065   /* PREFIX_VEX_0F38AB */
6066   {
6067     { Bad_Opcode },
6068     { Bad_Opcode },
6069     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6070   },
6071
6072   /* PREFIX_VEX_0F38AC */
6073   {
6074     { Bad_Opcode },
6075     { Bad_Opcode },
6076     { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 },
6077   },
6078
6079   /* PREFIX_VEX_0F38AD */
6080   {
6081     { Bad_Opcode },
6082     { Bad_Opcode },
6083     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6084   },
6085
6086   /* PREFIX_VEX_0F38AE */
6087   {
6088     { Bad_Opcode },
6089     { Bad_Opcode },
6090     { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 },
6091   },
6092
6093   /* PREFIX_VEX_0F38AF */
6094   {
6095     { Bad_Opcode },
6096     { Bad_Opcode },
6097     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6098   },
6099
6100   /* PREFIX_VEX_0F38B6 */
6101   {
6102     { Bad_Opcode },
6103     { Bad_Opcode },
6104     { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 },
6105   },
6106
6107   /* PREFIX_VEX_0F38B7 */
6108   {
6109     { Bad_Opcode },
6110     { Bad_Opcode },
6111     { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 },
6112   },
6113
6114   /* PREFIX_VEX_0F38B8 */
6115   {
6116     { Bad_Opcode },
6117     { Bad_Opcode },
6118     { "vfmadd231p%XW", { XM, Vex, EXx }, 0 },
6119   },
6120
6121   /* PREFIX_VEX_0F38B9 */
6122   {
6123     { Bad_Opcode },
6124     { Bad_Opcode },
6125     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6126   },
6127
6128   /* PREFIX_VEX_0F38BA */
6129   {
6130     { Bad_Opcode },
6131     { Bad_Opcode },
6132     { "vfmsub231p%XW", { XM, Vex, EXx }, 0 },
6133   },
6134
6135   /* PREFIX_VEX_0F38BB */
6136   {
6137     { Bad_Opcode },
6138     { Bad_Opcode },
6139     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6140   },
6141
6142   /* PREFIX_VEX_0F38BC */
6143   {
6144     { Bad_Opcode },
6145     { Bad_Opcode },
6146     { "vfnmadd231p%XW", { XM, Vex, EXx }, 0 },
6147   },
6148
6149   /* PREFIX_VEX_0F38BD */
6150   {
6151     { Bad_Opcode },
6152     { Bad_Opcode },
6153     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6154   },
6155
6156   /* PREFIX_VEX_0F38BE */
6157   {
6158     { Bad_Opcode },
6159     { Bad_Opcode },
6160     { "vfnmsub231p%XW", { XM, Vex, EXx }, 0 },
6161   },
6162
6163   /* PREFIX_VEX_0F38BF */
6164   {
6165     { Bad_Opcode },
6166     { Bad_Opcode },
6167     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6168   },
6169
6170   /* PREFIX_VEX_0F38DB */
6171   {
6172     { Bad_Opcode },
6173     { Bad_Opcode },
6174     { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6175   },
6176
6177   /* PREFIX_VEX_0F38DC */
6178   {
6179     { Bad_Opcode },
6180     { Bad_Opcode },
6181     { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2) },
6182   },
6183
6184   /* PREFIX_VEX_0F38DD */
6185   {
6186     { Bad_Opcode },
6187     { Bad_Opcode },
6188     { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2) },
6189   },
6190
6191   /* PREFIX_VEX_0F38DE */
6192   {
6193     { Bad_Opcode },
6194     { Bad_Opcode },
6195     { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2) },
6196   },
6197
6198   /* PREFIX_VEX_0F38DF */
6199   {
6200     { Bad_Opcode },
6201     { Bad_Opcode },
6202     { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2) },
6203   },
6204
6205   /* PREFIX_VEX_0F38F2 */
6206   {
6207     { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6208   },
6209
6210   /* PREFIX_VEX_0F38F3_REG_1 */
6211   {
6212     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6213   },
6214
6215   /* PREFIX_VEX_0F38F3_REG_2 */
6216   {
6217     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6218   },
6219
6220   /* PREFIX_VEX_0F38F3_REG_3 */
6221   {
6222     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6223   },
6224
6225   /* PREFIX_VEX_0F38F5 */
6226   {
6227     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6228     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6229     { Bad_Opcode },
6230     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6231   },
6232
6233   /* PREFIX_VEX_0F38F6 */
6234   {
6235     { Bad_Opcode },
6236     { Bad_Opcode },
6237     { Bad_Opcode },
6238     { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6239   },
6240
6241   /* PREFIX_VEX_0F38F7 */
6242   {
6243     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6244     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6245     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6246     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6247   },
6248
6249   /* PREFIX_VEX_0F3A00 */
6250   {
6251     { Bad_Opcode },
6252     { Bad_Opcode },
6253     { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6254   },
6255
6256   /* PREFIX_VEX_0F3A01 */
6257   {
6258     { Bad_Opcode },
6259     { Bad_Opcode },
6260     { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6261   },
6262
6263   /* PREFIX_VEX_0F3A02 */
6264   {
6265     { Bad_Opcode },
6266     { Bad_Opcode },
6267     { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6268   },
6269
6270   /* PREFIX_VEX_0F3A04 */
6271   {
6272     { Bad_Opcode },
6273     { Bad_Opcode },
6274     { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6275   },
6276
6277   /* PREFIX_VEX_0F3A05 */
6278   {
6279     { Bad_Opcode },
6280     { Bad_Opcode },
6281     { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6282   },
6283
6284   /* PREFIX_VEX_0F3A06 */
6285   {
6286     { Bad_Opcode },
6287     { Bad_Opcode },
6288     { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6289   },
6290
6291   /* PREFIX_VEX_0F3A08 */
6292   {
6293     { Bad_Opcode },
6294     { Bad_Opcode },
6295     { VEX_W_TABLE (VEX_W_0F3A08_P_2) },
6296   },
6297
6298   /* PREFIX_VEX_0F3A09 */
6299   {
6300     { Bad_Opcode },
6301     { Bad_Opcode },
6302     { VEX_W_TABLE (VEX_W_0F3A09_P_2) },
6303   },
6304
6305   /* PREFIX_VEX_0F3A0A */
6306   {
6307     { Bad_Opcode },
6308     { Bad_Opcode },
6309     { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) },
6310   },
6311
6312   /* PREFIX_VEX_0F3A0B */
6313   {
6314     { Bad_Opcode },
6315     { Bad_Opcode },
6316     { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) },
6317   },
6318
6319   /* PREFIX_VEX_0F3A0C */
6320   {
6321     { Bad_Opcode },
6322     { Bad_Opcode },
6323     { VEX_W_TABLE (VEX_W_0F3A0C_P_2) },
6324   },
6325
6326   /* PREFIX_VEX_0F3A0D */
6327   {
6328     { Bad_Opcode },
6329     { Bad_Opcode },
6330     { VEX_W_TABLE (VEX_W_0F3A0D_P_2) },
6331   },
6332
6333   /* PREFIX_VEX_0F3A0E */
6334   {
6335     { Bad_Opcode },
6336     { Bad_Opcode },
6337     { VEX_W_TABLE (VEX_W_0F3A0E_P_2) },
6338   },
6339
6340   /* PREFIX_VEX_0F3A0F */
6341   {
6342     { Bad_Opcode },
6343     { Bad_Opcode },
6344     { VEX_W_TABLE (VEX_W_0F3A0F_P_2) },
6345   },
6346
6347   /* PREFIX_VEX_0F3A14 */
6348   {
6349     { Bad_Opcode },
6350     { Bad_Opcode },
6351     { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6352   },
6353
6354   /* PREFIX_VEX_0F3A15 */
6355   {
6356     { Bad_Opcode },
6357     { Bad_Opcode },
6358     { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6359   },
6360
6361   /* PREFIX_VEX_0F3A16 */
6362   {
6363     { Bad_Opcode },
6364     { Bad_Opcode },
6365     { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6366   },
6367
6368   /* PREFIX_VEX_0F3A17 */
6369   {
6370     { Bad_Opcode },
6371     { Bad_Opcode },
6372     { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6373   },
6374
6375   /* PREFIX_VEX_0F3A18 */
6376   {
6377     { Bad_Opcode },
6378     { Bad_Opcode },
6379     { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6380   },
6381
6382   /* PREFIX_VEX_0F3A19 */
6383   {
6384     { Bad_Opcode },
6385     { Bad_Opcode },
6386     { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6387   },
6388
6389   /* PREFIX_VEX_0F3A1D */
6390   {
6391     { Bad_Opcode },
6392     { Bad_Opcode },
6393     { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 },
6394   },
6395
6396   /* PREFIX_VEX_0F3A20 */
6397   {
6398     { Bad_Opcode },
6399     { Bad_Opcode },
6400     { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6401   },
6402
6403   /* PREFIX_VEX_0F3A21 */
6404   {
6405     { Bad_Opcode },
6406     { Bad_Opcode },
6407     { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6408   },
6409
6410   /* PREFIX_VEX_0F3A22 */
6411   {
6412     { Bad_Opcode },
6413     { Bad_Opcode },
6414     { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6415   },
6416
6417   /* PREFIX_VEX_0F3A30 */
6418   {
6419     { Bad_Opcode },
6420     { Bad_Opcode },
6421     { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6422   },
6423
6424   /* PREFIX_VEX_0F3A31 */
6425   {
6426     { Bad_Opcode },
6427     { Bad_Opcode },
6428     { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6429   },
6430
6431   /* PREFIX_VEX_0F3A32 */
6432   {
6433     { Bad_Opcode },
6434     { Bad_Opcode },
6435     { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6436   },
6437
6438   /* PREFIX_VEX_0F3A33 */
6439   {
6440     { Bad_Opcode },
6441     { Bad_Opcode },
6442     { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6443   },
6444
6445   /* PREFIX_VEX_0F3A38 */
6446   {
6447     { Bad_Opcode },
6448     { Bad_Opcode },
6449     { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6450   },
6451
6452   /* PREFIX_VEX_0F3A39 */
6453   {
6454     { Bad_Opcode },
6455     { Bad_Opcode },
6456     { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6457   },
6458
6459   /* PREFIX_VEX_0F3A40 */
6460   {
6461     { Bad_Opcode },
6462     { Bad_Opcode },
6463     { VEX_W_TABLE (VEX_W_0F3A40_P_2) },
6464   },
6465
6466   /* PREFIX_VEX_0F3A41 */
6467   {
6468     { Bad_Opcode },
6469     { Bad_Opcode },
6470     { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6471   },
6472
6473   /* PREFIX_VEX_0F3A42 */
6474   {
6475     { Bad_Opcode },
6476     { Bad_Opcode },
6477     { VEX_W_TABLE (VEX_W_0F3A42_P_2) },
6478   },
6479
6480   /* PREFIX_VEX_0F3A44 */
6481   {
6482     { Bad_Opcode },
6483     { Bad_Opcode },
6484     { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2) },
6485   },
6486
6487   /* PREFIX_VEX_0F3A46 */
6488   {
6489     { Bad_Opcode },
6490     { Bad_Opcode },
6491     { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6492   },
6493
6494   /* PREFIX_VEX_0F3A48 */
6495   {
6496     { Bad_Opcode },
6497     { Bad_Opcode },
6498     { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6499   },
6500
6501   /* PREFIX_VEX_0F3A49 */
6502   {
6503     { Bad_Opcode },
6504     { Bad_Opcode },
6505     { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6506   },
6507
6508   /* PREFIX_VEX_0F3A4A */
6509   {
6510     { Bad_Opcode },
6511     { Bad_Opcode },
6512     { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6513   },
6514
6515   /* PREFIX_VEX_0F3A4B */
6516   {
6517     { Bad_Opcode },
6518     { Bad_Opcode },
6519     { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6520   },
6521
6522   /* PREFIX_VEX_0F3A4C */
6523   {
6524     { Bad_Opcode },
6525     { Bad_Opcode },
6526     { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6527   },
6528
6529   /* PREFIX_VEX_0F3A5C */
6530   {
6531     { Bad_Opcode },
6532     { Bad_Opcode },
6533     { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6534   },
6535
6536   /* PREFIX_VEX_0F3A5D */
6537   {
6538     { Bad_Opcode },
6539     { Bad_Opcode },
6540     { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6541   },
6542
6543   /* PREFIX_VEX_0F3A5E */
6544   {
6545     { Bad_Opcode },
6546     { Bad_Opcode },
6547     { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6548   },
6549
6550   /* PREFIX_VEX_0F3A5F */
6551   {
6552     { Bad_Opcode },
6553     { Bad_Opcode },
6554     { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6555   },
6556
6557   /* PREFIX_VEX_0F3A60 */
6558   {
6559     { Bad_Opcode },
6560     { Bad_Opcode },
6561     { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6562     { Bad_Opcode },
6563   },
6564
6565   /* PREFIX_VEX_0F3A61 */
6566   {
6567     { Bad_Opcode },
6568     { Bad_Opcode },
6569     { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6570   },
6571
6572   /* PREFIX_VEX_0F3A62 */
6573   {
6574     { Bad_Opcode },
6575     { Bad_Opcode },
6576     { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6577   },
6578
6579   /* PREFIX_VEX_0F3A63 */
6580   {
6581     { Bad_Opcode },
6582     { Bad_Opcode },
6583     { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6584   },
6585
6586   /* PREFIX_VEX_0F3A68 */
6587   {
6588     { Bad_Opcode },
6589     { Bad_Opcode },
6590     { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6591   },
6592
6593   /* PREFIX_VEX_0F3A69 */
6594   {
6595     { Bad_Opcode },
6596     { Bad_Opcode },
6597     { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6598   },
6599
6600   /* PREFIX_VEX_0F3A6A */
6601   {
6602     { Bad_Opcode },
6603     { Bad_Opcode },
6604     { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6605   },
6606
6607   /* PREFIX_VEX_0F3A6B */
6608   {
6609     { Bad_Opcode },
6610     { Bad_Opcode },
6611     { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6612   },
6613
6614   /* PREFIX_VEX_0F3A6C */
6615   {
6616     { Bad_Opcode },
6617     { Bad_Opcode },
6618     { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6619   },
6620
6621   /* PREFIX_VEX_0F3A6D */
6622   {
6623     { Bad_Opcode },
6624     { Bad_Opcode },
6625     { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6626   },
6627
6628   /* PREFIX_VEX_0F3A6E */
6629   {
6630     { Bad_Opcode },
6631     { Bad_Opcode },
6632     { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6633   },
6634
6635   /* PREFIX_VEX_0F3A6F */
6636   {
6637     { Bad_Opcode },
6638     { Bad_Opcode },
6639     { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6640   },
6641
6642   /* PREFIX_VEX_0F3A78 */
6643   {
6644     { Bad_Opcode },
6645     { Bad_Opcode },
6646     { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6647   },
6648
6649   /* PREFIX_VEX_0F3A79 */
6650   {
6651     { Bad_Opcode },
6652     { Bad_Opcode },
6653     { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6654   },
6655
6656   /* PREFIX_VEX_0F3A7A */
6657   {
6658     { Bad_Opcode },
6659     { Bad_Opcode },
6660     { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6661   },
6662
6663   /* PREFIX_VEX_0F3A7B */
6664   {
6665     { Bad_Opcode },
6666     { Bad_Opcode },
6667     { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6668   },
6669
6670   /* PREFIX_VEX_0F3A7C */
6671   {
6672     { Bad_Opcode },
6673     { Bad_Opcode },
6674     { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6675     { Bad_Opcode },
6676   },
6677
6678   /* PREFIX_VEX_0F3A7D */
6679   {
6680     { Bad_Opcode },
6681     { Bad_Opcode },
6682     { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6683   },
6684
6685   /* PREFIX_VEX_0F3A7E */
6686   {
6687     { Bad_Opcode },
6688     { Bad_Opcode },
6689     { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6690   },
6691
6692   /* PREFIX_VEX_0F3A7F */
6693   {
6694     { Bad_Opcode },
6695     { Bad_Opcode },
6696     { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6697   },
6698
6699   /* PREFIX_VEX_0F3ADF */
6700   {
6701     { Bad_Opcode },
6702     { Bad_Opcode },
6703     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6704   },
6705
6706   /* PREFIX_VEX_0F3AF0 */
6707   {
6708     { Bad_Opcode },
6709     { Bad_Opcode },
6710     { Bad_Opcode },
6711     { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6712   },
6713
6714 #define NEED_PREFIX_TABLE
6715 #include "i386-dis-evex.h"
6716 #undef NEED_PREFIX_TABLE
6717 };
6718
6719 static const struct dis386 x86_64_table[][2] = {
6720   /* X86_64_06 */
6721   {
6722     { "pushP", { es }, 0 },
6723   },
6724
6725   /* X86_64_07 */
6726   {
6727     { "popP", { es }, 0 },
6728   },
6729
6730   /* X86_64_0D */
6731   {
6732     { "pushP", { cs }, 0 },
6733   },
6734
6735   /* X86_64_16 */
6736   {
6737     { "pushP", { ss }, 0 },
6738   },
6739
6740   /* X86_64_17 */
6741   {
6742     { "popP", { ss }, 0 },
6743   },
6744
6745   /* X86_64_1E */
6746   {
6747     { "pushP", { ds }, 0 },
6748   },
6749
6750   /* X86_64_1F */
6751   {
6752     { "popP", { ds }, 0 },
6753   },
6754
6755   /* X86_64_27 */
6756   {
6757     { "daa", { XX }, 0 },
6758   },
6759
6760   /* X86_64_2F */
6761   {
6762     { "das", { XX }, 0 },
6763   },
6764
6765   /* X86_64_37 */
6766   {
6767     { "aaa", { XX }, 0 },
6768   },
6769
6770   /* X86_64_3F */
6771   {
6772     { "aas", { XX }, 0 },
6773   },
6774
6775   /* X86_64_60 */
6776   {
6777     { "pushaP", { XX }, 0 },
6778   },
6779
6780   /* X86_64_61 */
6781   {
6782     { "popaP", { XX }, 0 },
6783   },
6784
6785   /* X86_64_62 */
6786   {
6787     { MOD_TABLE (MOD_62_32BIT) },
6788     { EVEX_TABLE (EVEX_0F) },
6789   },
6790
6791   /* X86_64_63 */
6792   {
6793     { "arpl", { Ew, Gw }, 0 },
6794     { "movs{lq|xd}", { Gv, Ed }, 0 },
6795   },
6796
6797   /* X86_64_6D */
6798   {
6799     { "ins{R|}", { Yzr, indirDX }, 0 },
6800     { "ins{G|}", { Yzr, indirDX }, 0 },
6801   },
6802
6803   /* X86_64_6F */
6804   {
6805     { "outs{R|}", { indirDXr, Xz }, 0 },
6806     { "outs{G|}", { indirDXr, Xz }, 0 },
6807   },
6808
6809   /* X86_64_9A */
6810   {
6811     { "Jcall{T|}", { Ap }, 0 },
6812   },
6813
6814   /* X86_64_C4 */
6815   {
6816     { MOD_TABLE (MOD_C4_32BIT) },
6817     { VEX_C4_TABLE (VEX_0F) },
6818   },
6819
6820   /* X86_64_C5 */
6821   {
6822     { MOD_TABLE (MOD_C5_32BIT) },
6823     { VEX_C5_TABLE (VEX_0F) },
6824   },
6825
6826   /* X86_64_CE */
6827   {
6828     { "into", { XX }, 0 },
6829   },
6830
6831   /* X86_64_D4 */
6832   {
6833     { "aam", { Ib }, 0 },
6834   },
6835
6836   /* X86_64_D5 */
6837   {
6838     { "aad", { Ib }, 0 },
6839   },
6840
6841   /* X86_64_EA */
6842   {
6843     { "Jjmp{T|}", { Ap }, 0 },
6844   },
6845
6846   /* X86_64_0F01_REG_0 */
6847   {
6848     { "sgdt{Q|IQ}", { M }, 0 },
6849     { "sgdt", { M }, 0 },
6850   },
6851
6852   /* X86_64_0F01_REG_1 */
6853   {
6854     { "sidt{Q|IQ}", { M }, 0 },
6855     { "sidt", { M }, 0 },
6856   },
6857
6858   /* X86_64_0F01_REG_2 */
6859   {
6860     { "lgdt{Q|Q}", { M }, 0 },
6861     { "lgdt", { M }, 0 },
6862   },
6863
6864   /* X86_64_0F01_REG_3 */
6865   {
6866     { "lidt{Q|Q}", { M }, 0 },
6867     { "lidt", { M }, 0 },
6868   },
6869 };
6870
6871 static const struct dis386 three_byte_table[][256] = {
6872
6873   /* THREE_BYTE_0F38 */
6874   {
6875     /* 00 */
6876     { "pshufb",         { MX, EM }, PREFIX_OPCODE },
6877     { "phaddw",         { MX, EM }, PREFIX_OPCODE },
6878     { "phaddd",         { MX, EM }, PREFIX_OPCODE },
6879     { "phaddsw",        { MX, EM }, PREFIX_OPCODE },
6880     { "pmaddubsw",      { MX, EM }, PREFIX_OPCODE },
6881     { "phsubw",         { MX, EM }, PREFIX_OPCODE },
6882     { "phsubd",         { MX, EM }, PREFIX_OPCODE },
6883     { "phsubsw",        { MX, EM }, PREFIX_OPCODE },
6884     /* 08 */
6885     { "psignb",         { MX, EM }, PREFIX_OPCODE },
6886     { "psignw",         { MX, EM }, PREFIX_OPCODE },
6887     { "psignd",         { MX, EM }, PREFIX_OPCODE },
6888     { "pmulhrsw",       { MX, EM }, PREFIX_OPCODE },
6889     { Bad_Opcode },
6890     { Bad_Opcode },
6891     { Bad_Opcode },
6892     { Bad_Opcode },
6893     /* 10 */
6894     { PREFIX_TABLE (PREFIX_0F3810) },
6895     { Bad_Opcode },
6896     { Bad_Opcode },
6897     { Bad_Opcode },
6898     { PREFIX_TABLE (PREFIX_0F3814) },
6899     { PREFIX_TABLE (PREFIX_0F3815) },
6900     { Bad_Opcode },
6901     { PREFIX_TABLE (PREFIX_0F3817) },
6902     /* 18 */
6903     { Bad_Opcode },
6904     { Bad_Opcode },
6905     { Bad_Opcode },
6906     { Bad_Opcode },
6907     { "pabsb",          { MX, EM }, PREFIX_OPCODE },
6908     { "pabsw",          { MX, EM }, PREFIX_OPCODE },
6909     { "pabsd",          { MX, EM }, PREFIX_OPCODE },
6910     { Bad_Opcode },
6911     /* 20 */
6912     { PREFIX_TABLE (PREFIX_0F3820) },
6913     { PREFIX_TABLE (PREFIX_0F3821) },
6914     { PREFIX_TABLE (PREFIX_0F3822) },
6915     { PREFIX_TABLE (PREFIX_0F3823) },
6916     { PREFIX_TABLE (PREFIX_0F3824) },
6917     { PREFIX_TABLE (PREFIX_0F3825) },
6918     { Bad_Opcode },
6919     { Bad_Opcode },
6920     /* 28 */
6921     { PREFIX_TABLE (PREFIX_0F3828) },
6922     { PREFIX_TABLE (PREFIX_0F3829) },
6923     { PREFIX_TABLE (PREFIX_0F382A) },
6924     { PREFIX_TABLE (PREFIX_0F382B) },
6925     { Bad_Opcode },
6926     { Bad_Opcode },
6927     { Bad_Opcode },
6928     { Bad_Opcode },
6929     /* 30 */
6930     { PREFIX_TABLE (PREFIX_0F3830) },
6931     { PREFIX_TABLE (PREFIX_0F3831) },
6932     { PREFIX_TABLE (PREFIX_0F3832) },
6933     { PREFIX_TABLE (PREFIX_0F3833) },
6934     { PREFIX_TABLE (PREFIX_0F3834) },
6935     { PREFIX_TABLE (PREFIX_0F3835) },
6936     { Bad_Opcode },
6937     { PREFIX_TABLE (PREFIX_0F3837) },
6938     /* 38 */
6939     { PREFIX_TABLE (PREFIX_0F3838) },
6940     { PREFIX_TABLE (PREFIX_0F3839) },
6941     { PREFIX_TABLE (PREFIX_0F383A) },
6942     { PREFIX_TABLE (PREFIX_0F383B) },
6943     { PREFIX_TABLE (PREFIX_0F383C) },
6944     { PREFIX_TABLE (PREFIX_0F383D) },
6945     { PREFIX_TABLE (PREFIX_0F383E) },
6946     { PREFIX_TABLE (PREFIX_0F383F) },
6947     /* 40 */
6948     { PREFIX_TABLE (PREFIX_0F3840) },
6949     { PREFIX_TABLE (PREFIX_0F3841) },
6950     { Bad_Opcode },
6951     { Bad_Opcode },
6952     { Bad_Opcode },
6953     { Bad_Opcode },
6954     { Bad_Opcode },
6955     { Bad_Opcode },
6956     /* 48 */
6957     { Bad_Opcode },
6958     { Bad_Opcode },
6959     { Bad_Opcode },
6960     { Bad_Opcode },
6961     { Bad_Opcode },
6962     { Bad_Opcode },
6963     { Bad_Opcode },
6964     { Bad_Opcode },
6965     /* 50 */
6966     { Bad_Opcode },
6967     { Bad_Opcode },
6968     { Bad_Opcode },
6969     { Bad_Opcode },
6970     { Bad_Opcode },
6971     { Bad_Opcode },
6972     { Bad_Opcode },
6973     { Bad_Opcode },
6974     /* 58 */
6975     { Bad_Opcode },
6976     { Bad_Opcode },
6977     { Bad_Opcode },
6978     { Bad_Opcode },
6979     { Bad_Opcode },
6980     { Bad_Opcode },
6981     { Bad_Opcode },
6982     { Bad_Opcode },
6983     /* 60 */
6984     { Bad_Opcode },
6985     { Bad_Opcode },
6986     { Bad_Opcode },
6987     { Bad_Opcode },
6988     { Bad_Opcode },
6989     { Bad_Opcode },
6990     { Bad_Opcode },
6991     { Bad_Opcode },
6992     /* 68 */
6993     { Bad_Opcode },
6994     { Bad_Opcode },
6995     { Bad_Opcode },
6996     { Bad_Opcode },
6997     { Bad_Opcode },
6998     { Bad_Opcode },
6999     { Bad_Opcode },
7000     { Bad_Opcode },
7001     /* 70 */
7002     { Bad_Opcode },
7003     { Bad_Opcode },
7004     { Bad_Opcode },
7005     { Bad_Opcode },
7006     { Bad_Opcode },
7007     { Bad_Opcode },
7008     { Bad_Opcode },
7009     { Bad_Opcode },
7010     /* 78 */
7011     { Bad_Opcode },
7012     { Bad_Opcode },
7013     { Bad_Opcode },
7014     { Bad_Opcode },
7015     { Bad_Opcode },
7016     { Bad_Opcode },
7017     { Bad_Opcode },
7018     { Bad_Opcode },
7019     /* 80 */
7020     { PREFIX_TABLE (PREFIX_0F3880) },
7021     { PREFIX_TABLE (PREFIX_0F3881) },
7022     { PREFIX_TABLE (PREFIX_0F3882) },
7023     { Bad_Opcode },
7024     { Bad_Opcode },
7025     { Bad_Opcode },
7026     { Bad_Opcode },
7027     { Bad_Opcode },
7028     /* 88 */
7029     { Bad_Opcode },
7030     { Bad_Opcode },
7031     { Bad_Opcode },
7032     { Bad_Opcode },
7033     { Bad_Opcode },
7034     { Bad_Opcode },
7035     { Bad_Opcode },
7036     { Bad_Opcode },
7037     /* 90 */
7038     { Bad_Opcode },
7039     { Bad_Opcode },
7040     { Bad_Opcode },
7041     { Bad_Opcode },
7042     { Bad_Opcode },
7043     { Bad_Opcode },
7044     { Bad_Opcode },
7045     { Bad_Opcode },
7046     /* 98 */
7047     { Bad_Opcode },
7048     { Bad_Opcode },
7049     { Bad_Opcode },
7050     { Bad_Opcode },
7051     { Bad_Opcode },
7052     { Bad_Opcode },
7053     { Bad_Opcode },
7054     { Bad_Opcode },
7055     /* a0 */
7056     { Bad_Opcode },
7057     { Bad_Opcode },
7058     { Bad_Opcode },
7059     { Bad_Opcode },
7060     { Bad_Opcode },
7061     { Bad_Opcode },
7062     { Bad_Opcode },
7063     { Bad_Opcode },
7064     /* a8 */
7065     { Bad_Opcode },
7066     { Bad_Opcode },
7067     { Bad_Opcode },
7068     { Bad_Opcode },
7069     { Bad_Opcode },
7070     { Bad_Opcode },
7071     { Bad_Opcode },
7072     { Bad_Opcode },
7073     /* b0 */
7074     { Bad_Opcode },
7075     { Bad_Opcode },
7076     { Bad_Opcode },
7077     { Bad_Opcode },
7078     { Bad_Opcode },
7079     { Bad_Opcode },
7080     { Bad_Opcode },
7081     { Bad_Opcode },
7082     /* b8 */
7083     { Bad_Opcode },
7084     { Bad_Opcode },
7085     { Bad_Opcode },
7086     { Bad_Opcode },
7087     { Bad_Opcode },
7088     { Bad_Opcode },
7089     { Bad_Opcode },
7090     { Bad_Opcode },
7091     /* c0 */
7092     { Bad_Opcode },
7093     { Bad_Opcode },
7094     { Bad_Opcode },
7095     { Bad_Opcode },
7096     { Bad_Opcode },
7097     { Bad_Opcode },
7098     { Bad_Opcode },
7099     { Bad_Opcode },
7100     /* c8 */
7101     { PREFIX_TABLE (PREFIX_0F38C8) },
7102     { PREFIX_TABLE (PREFIX_0F38C9) },
7103     { PREFIX_TABLE (PREFIX_0F38CA) },
7104     { PREFIX_TABLE (PREFIX_0F38CB) },
7105     { PREFIX_TABLE (PREFIX_0F38CC) },
7106     { PREFIX_TABLE (PREFIX_0F38CD) },
7107     { Bad_Opcode },
7108     { Bad_Opcode },
7109     /* d0 */
7110     { Bad_Opcode },
7111     { Bad_Opcode },
7112     { Bad_Opcode },
7113     { Bad_Opcode },
7114     { Bad_Opcode },
7115     { Bad_Opcode },
7116     { Bad_Opcode },
7117     { Bad_Opcode },
7118     /* d8 */
7119     { Bad_Opcode },
7120     { Bad_Opcode },
7121     { Bad_Opcode },
7122     { PREFIX_TABLE (PREFIX_0F38DB) },
7123     { PREFIX_TABLE (PREFIX_0F38DC) },
7124     { PREFIX_TABLE (PREFIX_0F38DD) },
7125     { PREFIX_TABLE (PREFIX_0F38DE) },
7126     { PREFIX_TABLE (PREFIX_0F38DF) },
7127     /* e0 */
7128     { Bad_Opcode },
7129     { Bad_Opcode },
7130     { Bad_Opcode },
7131     { Bad_Opcode },
7132     { Bad_Opcode },
7133     { Bad_Opcode },
7134     { Bad_Opcode },
7135     { Bad_Opcode },
7136     /* e8 */
7137     { Bad_Opcode },
7138     { Bad_Opcode },
7139     { Bad_Opcode },
7140     { Bad_Opcode },
7141     { Bad_Opcode },
7142     { Bad_Opcode },
7143     { Bad_Opcode },
7144     { Bad_Opcode },
7145     /* f0 */
7146     { PREFIX_TABLE (PREFIX_0F38F0) },
7147     { PREFIX_TABLE (PREFIX_0F38F1) },
7148     { Bad_Opcode },
7149     { Bad_Opcode },
7150     { Bad_Opcode },
7151     { Bad_Opcode },
7152     { PREFIX_TABLE (PREFIX_0F38F6) },
7153     { Bad_Opcode },
7154     /* f8 */
7155     { Bad_Opcode },
7156     { Bad_Opcode },
7157     { Bad_Opcode },
7158     { Bad_Opcode },
7159     { Bad_Opcode },
7160     { Bad_Opcode },
7161     { Bad_Opcode },
7162     { Bad_Opcode },
7163   },
7164   /* THREE_BYTE_0F3A */
7165   {
7166     /* 00 */
7167     { Bad_Opcode },
7168     { Bad_Opcode },
7169     { Bad_Opcode },
7170     { Bad_Opcode },
7171     { Bad_Opcode },
7172     { Bad_Opcode },
7173     { Bad_Opcode },
7174     { Bad_Opcode },
7175     /* 08 */
7176     { PREFIX_TABLE (PREFIX_0F3A08) },
7177     { PREFIX_TABLE (PREFIX_0F3A09) },
7178     { PREFIX_TABLE (PREFIX_0F3A0A) },
7179     { PREFIX_TABLE (PREFIX_0F3A0B) },
7180     { PREFIX_TABLE (PREFIX_0F3A0C) },
7181     { PREFIX_TABLE (PREFIX_0F3A0D) },
7182     { PREFIX_TABLE (PREFIX_0F3A0E) },
7183     { "palignr",        { MX, EM, Ib }, PREFIX_OPCODE },
7184     /* 10 */
7185     { Bad_Opcode },
7186     { Bad_Opcode },
7187     { Bad_Opcode },
7188     { Bad_Opcode },
7189     { PREFIX_TABLE (PREFIX_0F3A14) },
7190     { PREFIX_TABLE (PREFIX_0F3A15) },
7191     { PREFIX_TABLE (PREFIX_0F3A16) },
7192     { PREFIX_TABLE (PREFIX_0F3A17) },
7193     /* 18 */
7194     { Bad_Opcode },
7195     { Bad_Opcode },
7196     { Bad_Opcode },
7197     { Bad_Opcode },
7198     { Bad_Opcode },
7199     { Bad_Opcode },
7200     { Bad_Opcode },
7201     { Bad_Opcode },
7202     /* 20 */
7203     { PREFIX_TABLE (PREFIX_0F3A20) },
7204     { PREFIX_TABLE (PREFIX_0F3A21) },
7205     { PREFIX_TABLE (PREFIX_0F3A22) },
7206     { Bad_Opcode },
7207     { Bad_Opcode },
7208     { Bad_Opcode },
7209     { Bad_Opcode },
7210     { Bad_Opcode },
7211     /* 28 */
7212     { Bad_Opcode },
7213     { Bad_Opcode },
7214     { Bad_Opcode },
7215     { Bad_Opcode },
7216     { Bad_Opcode },
7217     { Bad_Opcode },
7218     { Bad_Opcode },
7219     { Bad_Opcode },
7220     /* 30 */
7221     { Bad_Opcode },
7222     { Bad_Opcode },
7223     { Bad_Opcode },
7224     { Bad_Opcode },
7225     { Bad_Opcode },
7226     { Bad_Opcode },
7227     { Bad_Opcode },
7228     { Bad_Opcode },
7229     /* 38 */
7230     { Bad_Opcode },
7231     { Bad_Opcode },
7232     { Bad_Opcode },
7233     { Bad_Opcode },
7234     { Bad_Opcode },
7235     { Bad_Opcode },
7236     { Bad_Opcode },
7237     { Bad_Opcode },
7238     /* 40 */
7239     { PREFIX_TABLE (PREFIX_0F3A40) },
7240     { PREFIX_TABLE (PREFIX_0F3A41) },
7241     { PREFIX_TABLE (PREFIX_0F3A42) },
7242     { Bad_Opcode },
7243     { PREFIX_TABLE (PREFIX_0F3A44) },
7244     { Bad_Opcode },
7245     { Bad_Opcode },
7246     { Bad_Opcode },
7247     /* 48 */
7248     { Bad_Opcode },
7249     { Bad_Opcode },
7250     { Bad_Opcode },
7251     { Bad_Opcode },
7252     { Bad_Opcode },
7253     { Bad_Opcode },
7254     { Bad_Opcode },
7255     { Bad_Opcode },
7256     /* 50 */
7257     { Bad_Opcode },
7258     { Bad_Opcode },
7259     { Bad_Opcode },
7260     { Bad_Opcode },
7261     { Bad_Opcode },
7262     { Bad_Opcode },
7263     { Bad_Opcode },
7264     { Bad_Opcode },
7265     /* 58 */
7266     { Bad_Opcode },
7267     { Bad_Opcode },
7268     { Bad_Opcode },
7269     { Bad_Opcode },
7270     { Bad_Opcode },
7271     { Bad_Opcode },
7272     { Bad_Opcode },
7273     { Bad_Opcode },
7274     /* 60 */
7275     { PREFIX_TABLE (PREFIX_0F3A60) },
7276     { PREFIX_TABLE (PREFIX_0F3A61) },
7277     { PREFIX_TABLE (PREFIX_0F3A62) },
7278     { PREFIX_TABLE (PREFIX_0F3A63) },
7279     { Bad_Opcode },
7280     { Bad_Opcode },
7281     { Bad_Opcode },
7282     { Bad_Opcode },
7283     /* 68 */
7284     { Bad_Opcode },
7285     { Bad_Opcode },
7286     { Bad_Opcode },
7287     { Bad_Opcode },
7288     { Bad_Opcode },
7289     { Bad_Opcode },
7290     { Bad_Opcode },
7291     { Bad_Opcode },
7292     /* 70 */
7293     { Bad_Opcode },
7294     { Bad_Opcode },
7295     { Bad_Opcode },
7296     { Bad_Opcode },
7297     { Bad_Opcode },
7298     { Bad_Opcode },
7299     { Bad_Opcode },
7300     { Bad_Opcode },
7301     /* 78 */
7302     { Bad_Opcode },
7303     { Bad_Opcode },
7304     { Bad_Opcode },
7305     { Bad_Opcode },
7306     { Bad_Opcode },
7307     { Bad_Opcode },
7308     { Bad_Opcode },
7309     { Bad_Opcode },
7310     /* 80 */
7311     { Bad_Opcode },
7312     { Bad_Opcode },
7313     { Bad_Opcode },
7314     { Bad_Opcode },
7315     { Bad_Opcode },
7316     { Bad_Opcode },
7317     { Bad_Opcode },
7318     { Bad_Opcode },
7319     /* 88 */
7320     { Bad_Opcode },
7321     { Bad_Opcode },
7322     { Bad_Opcode },
7323     { Bad_Opcode },
7324     { Bad_Opcode },
7325     { Bad_Opcode },
7326     { Bad_Opcode },
7327     { Bad_Opcode },
7328     /* 90 */
7329     { Bad_Opcode },
7330     { Bad_Opcode },
7331     { Bad_Opcode },
7332     { Bad_Opcode },
7333     { Bad_Opcode },
7334     { Bad_Opcode },
7335     { Bad_Opcode },
7336     { Bad_Opcode },
7337     /* 98 */
7338     { Bad_Opcode },
7339     { Bad_Opcode },
7340     { Bad_Opcode },
7341     { Bad_Opcode },
7342     { Bad_Opcode },
7343     { Bad_Opcode },
7344     { Bad_Opcode },
7345     { Bad_Opcode },
7346     /* a0 */
7347     { Bad_Opcode },
7348     { Bad_Opcode },
7349     { Bad_Opcode },
7350     { Bad_Opcode },
7351     { Bad_Opcode },
7352     { Bad_Opcode },
7353     { Bad_Opcode },
7354     { Bad_Opcode },
7355     /* a8 */
7356     { Bad_Opcode },
7357     { Bad_Opcode },
7358     { Bad_Opcode },
7359     { Bad_Opcode },
7360     { Bad_Opcode },
7361     { Bad_Opcode },
7362     { Bad_Opcode },
7363     { Bad_Opcode },
7364     /* b0 */
7365     { Bad_Opcode },
7366     { Bad_Opcode },
7367     { Bad_Opcode },
7368     { Bad_Opcode },
7369     { Bad_Opcode },
7370     { Bad_Opcode },
7371     { Bad_Opcode },
7372     { Bad_Opcode },
7373     /* b8 */
7374     { Bad_Opcode },
7375     { Bad_Opcode },
7376     { Bad_Opcode },
7377     { Bad_Opcode },
7378     { Bad_Opcode },
7379     { Bad_Opcode },
7380     { Bad_Opcode },
7381     { Bad_Opcode },
7382     /* c0 */
7383     { Bad_Opcode },
7384     { Bad_Opcode },
7385     { Bad_Opcode },
7386     { Bad_Opcode },
7387     { Bad_Opcode },
7388     { Bad_Opcode },
7389     { Bad_Opcode },
7390     { Bad_Opcode },
7391     /* c8 */
7392     { Bad_Opcode },
7393     { Bad_Opcode },
7394     { Bad_Opcode },
7395     { Bad_Opcode },
7396     { PREFIX_TABLE (PREFIX_0F3ACC) },
7397     { Bad_Opcode },
7398     { Bad_Opcode },
7399     { Bad_Opcode },
7400     /* d0 */
7401     { Bad_Opcode },
7402     { Bad_Opcode },
7403     { Bad_Opcode },
7404     { Bad_Opcode },
7405     { Bad_Opcode },
7406     { Bad_Opcode },
7407     { Bad_Opcode },
7408     { Bad_Opcode },
7409     /* d8 */
7410     { Bad_Opcode },
7411     { Bad_Opcode },
7412     { Bad_Opcode },
7413     { Bad_Opcode },
7414     { Bad_Opcode },
7415     { Bad_Opcode },
7416     { Bad_Opcode },
7417     { PREFIX_TABLE (PREFIX_0F3ADF) },
7418     /* e0 */
7419     { Bad_Opcode },
7420     { Bad_Opcode },
7421     { Bad_Opcode },
7422     { Bad_Opcode },
7423     { Bad_Opcode },
7424     { Bad_Opcode },
7425     { Bad_Opcode },
7426     { Bad_Opcode },
7427     /* e8 */
7428     { Bad_Opcode },
7429     { Bad_Opcode },
7430     { Bad_Opcode },
7431     { Bad_Opcode },
7432     { Bad_Opcode },
7433     { Bad_Opcode },
7434     { Bad_Opcode },
7435     { Bad_Opcode },
7436     /* f0 */
7437     { Bad_Opcode },
7438     { Bad_Opcode },
7439     { Bad_Opcode },
7440     { Bad_Opcode },
7441     { Bad_Opcode },
7442     { Bad_Opcode },
7443     { Bad_Opcode },
7444     { Bad_Opcode },
7445     /* f8 */
7446     { Bad_Opcode },
7447     { Bad_Opcode },
7448     { Bad_Opcode },
7449     { Bad_Opcode },
7450     { Bad_Opcode },
7451     { Bad_Opcode },
7452     { Bad_Opcode },
7453     { Bad_Opcode },
7454   },
7455
7456   /* THREE_BYTE_0F7A */
7457   {
7458     /* 00 */
7459     { Bad_Opcode },
7460     { Bad_Opcode },
7461     { Bad_Opcode },
7462     { Bad_Opcode },
7463     { Bad_Opcode },
7464     { Bad_Opcode },
7465     { Bad_Opcode },
7466     { Bad_Opcode },
7467     /* 08 */
7468     { Bad_Opcode },
7469     { Bad_Opcode },
7470     { Bad_Opcode },
7471     { Bad_Opcode },
7472     { Bad_Opcode },
7473     { Bad_Opcode },
7474     { Bad_Opcode },
7475     { Bad_Opcode },
7476     /* 10 */
7477     { Bad_Opcode },
7478     { Bad_Opcode },
7479     { Bad_Opcode },
7480     { Bad_Opcode },
7481     { Bad_Opcode },
7482     { Bad_Opcode },
7483     { Bad_Opcode },
7484     { Bad_Opcode },
7485     /* 18 */
7486     { Bad_Opcode },
7487     { Bad_Opcode },
7488     { Bad_Opcode },
7489     { Bad_Opcode },
7490     { Bad_Opcode },
7491     { Bad_Opcode },
7492     { Bad_Opcode },
7493     { Bad_Opcode },
7494     /* 20 */
7495     { "ptest",          { XX }, PREFIX_OPCODE },
7496     { Bad_Opcode },
7497     { Bad_Opcode },
7498     { Bad_Opcode },
7499     { Bad_Opcode },
7500     { Bad_Opcode },
7501     { Bad_Opcode },
7502     { Bad_Opcode },
7503     /* 28 */
7504     { Bad_Opcode },
7505     { Bad_Opcode },
7506     { Bad_Opcode },
7507     { Bad_Opcode },
7508     { Bad_Opcode },
7509     { Bad_Opcode },
7510     { Bad_Opcode },
7511     { Bad_Opcode },
7512     /* 30 */
7513     { Bad_Opcode },
7514     { Bad_Opcode },
7515     { Bad_Opcode },
7516     { Bad_Opcode },
7517     { Bad_Opcode },
7518     { Bad_Opcode },
7519     { Bad_Opcode },
7520     { Bad_Opcode },
7521     /* 38 */
7522     { Bad_Opcode },
7523     { Bad_Opcode },
7524     { Bad_Opcode },
7525     { Bad_Opcode },
7526     { Bad_Opcode },
7527     { Bad_Opcode },
7528     { Bad_Opcode },
7529     { Bad_Opcode },
7530     /* 40 */
7531     { Bad_Opcode },
7532     { "phaddbw",        { XM, EXq }, PREFIX_OPCODE },
7533     { "phaddbd",        { XM, EXq }, PREFIX_OPCODE },
7534     { "phaddbq",        { XM, EXq }, PREFIX_OPCODE },
7535     { Bad_Opcode },
7536     { Bad_Opcode },
7537     { "phaddwd",        { XM, EXq }, PREFIX_OPCODE },
7538     { "phaddwq",        { XM, EXq }, PREFIX_OPCODE },
7539     /* 48 */
7540     { Bad_Opcode },
7541     { Bad_Opcode },
7542     { Bad_Opcode },
7543     { "phadddq",        { XM, EXq }, PREFIX_OPCODE },
7544     { Bad_Opcode },
7545     { Bad_Opcode },
7546     { Bad_Opcode },
7547     { Bad_Opcode },
7548     /* 50 */
7549     { Bad_Opcode },
7550     { "phaddubw",       { XM, EXq }, PREFIX_OPCODE },
7551     { "phaddubd",       { XM, EXq }, PREFIX_OPCODE },
7552     { "phaddubq",       { XM, EXq }, PREFIX_OPCODE },
7553     { Bad_Opcode },
7554     { Bad_Opcode },
7555     { "phadduwd",       { XM, EXq }, PREFIX_OPCODE },
7556     { "phadduwq",       { XM, EXq }, PREFIX_OPCODE },
7557     /* 58 */
7558     { Bad_Opcode },
7559     { Bad_Opcode },
7560     { Bad_Opcode },
7561     { "phaddudq",       { XM, EXq }, PREFIX_OPCODE },
7562     { Bad_Opcode },
7563     { Bad_Opcode },
7564     { Bad_Opcode },
7565     { Bad_Opcode },
7566     /* 60 */
7567     { Bad_Opcode },
7568     { "phsubbw",        { XM, EXq }, PREFIX_OPCODE },
7569     { "phsubbd",        { XM, EXq }, PREFIX_OPCODE },
7570     { "phsubbq",        { XM, EXq }, PREFIX_OPCODE },
7571     { Bad_Opcode },
7572     { Bad_Opcode },
7573     { Bad_Opcode },
7574     { Bad_Opcode },
7575     /* 68 */
7576     { Bad_Opcode },
7577     { Bad_Opcode },
7578     { Bad_Opcode },
7579     { Bad_Opcode },
7580     { Bad_Opcode },
7581     { Bad_Opcode },
7582     { Bad_Opcode },
7583     { Bad_Opcode },
7584     /* 70 */
7585     { Bad_Opcode },
7586     { Bad_Opcode },
7587     { Bad_Opcode },
7588     { Bad_Opcode },
7589     { Bad_Opcode },
7590     { Bad_Opcode },
7591     { Bad_Opcode },
7592     { Bad_Opcode },
7593     /* 78 */
7594     { Bad_Opcode },
7595     { Bad_Opcode },
7596     { Bad_Opcode },
7597     { Bad_Opcode },
7598     { Bad_Opcode },
7599     { Bad_Opcode },
7600     { Bad_Opcode },
7601     { Bad_Opcode },
7602     /* 80 */
7603     { Bad_Opcode },
7604     { Bad_Opcode },
7605     { Bad_Opcode },
7606     { Bad_Opcode },
7607     { Bad_Opcode },
7608     { Bad_Opcode },
7609     { Bad_Opcode },
7610     { Bad_Opcode },
7611     /* 88 */
7612     { Bad_Opcode },
7613     { Bad_Opcode },
7614     { Bad_Opcode },
7615     { Bad_Opcode },
7616     { Bad_Opcode },
7617     { Bad_Opcode },
7618     { Bad_Opcode },
7619     { Bad_Opcode },
7620     /* 90 */
7621     { Bad_Opcode },
7622     { Bad_Opcode },
7623     { Bad_Opcode },
7624     { Bad_Opcode },
7625     { Bad_Opcode },
7626     { Bad_Opcode },
7627     { Bad_Opcode },
7628     { Bad_Opcode },
7629     /* 98 */
7630     { Bad_Opcode },
7631     { Bad_Opcode },
7632     { Bad_Opcode },
7633     { Bad_Opcode },
7634     { Bad_Opcode },
7635     { Bad_Opcode },
7636     { Bad_Opcode },
7637     { Bad_Opcode },
7638     /* a0 */
7639     { Bad_Opcode },
7640     { Bad_Opcode },
7641     { Bad_Opcode },
7642     { Bad_Opcode },
7643     { Bad_Opcode },
7644     { Bad_Opcode },
7645     { Bad_Opcode },
7646     { Bad_Opcode },
7647     /* a8 */
7648     { Bad_Opcode },
7649     { Bad_Opcode },
7650     { Bad_Opcode },
7651     { Bad_Opcode },
7652     { Bad_Opcode },
7653     { Bad_Opcode },
7654     { Bad_Opcode },
7655     { Bad_Opcode },
7656     /* b0 */
7657     { Bad_Opcode },
7658     { Bad_Opcode },
7659     { Bad_Opcode },
7660     { Bad_Opcode },
7661     { Bad_Opcode },
7662     { Bad_Opcode },
7663     { Bad_Opcode },
7664     { Bad_Opcode },
7665     /* b8 */
7666     { Bad_Opcode },
7667     { Bad_Opcode },
7668     { Bad_Opcode },
7669     { Bad_Opcode },
7670     { Bad_Opcode },
7671     { Bad_Opcode },
7672     { Bad_Opcode },
7673     { Bad_Opcode },
7674     /* c0 */
7675     { Bad_Opcode },
7676     { Bad_Opcode },
7677     { Bad_Opcode },
7678     { Bad_Opcode },
7679     { Bad_Opcode },
7680     { Bad_Opcode },
7681     { Bad_Opcode },
7682     { Bad_Opcode },
7683     /* c8 */
7684     { Bad_Opcode },
7685     { Bad_Opcode },
7686     { Bad_Opcode },
7687     { Bad_Opcode },
7688     { Bad_Opcode },
7689     { Bad_Opcode },
7690     { Bad_Opcode },
7691     { Bad_Opcode },
7692     /* d0 */
7693     { Bad_Opcode },
7694     { Bad_Opcode },
7695     { Bad_Opcode },
7696     { Bad_Opcode },
7697     { Bad_Opcode },
7698     { Bad_Opcode },
7699     { Bad_Opcode },
7700     { Bad_Opcode },
7701     /* d8 */
7702     { Bad_Opcode },
7703     { Bad_Opcode },
7704     { Bad_Opcode },
7705     { Bad_Opcode },
7706     { Bad_Opcode },
7707     { Bad_Opcode },
7708     { Bad_Opcode },
7709     { Bad_Opcode },
7710     /* e0 */
7711     { Bad_Opcode },
7712     { Bad_Opcode },
7713     { Bad_Opcode },
7714     { Bad_Opcode },
7715     { Bad_Opcode },
7716     { Bad_Opcode },
7717     { Bad_Opcode },
7718     { Bad_Opcode },
7719     /* e8 */
7720     { Bad_Opcode },
7721     { Bad_Opcode },
7722     { Bad_Opcode },
7723     { Bad_Opcode },
7724     { Bad_Opcode },
7725     { Bad_Opcode },
7726     { Bad_Opcode },
7727     { Bad_Opcode },
7728     /* f0 */
7729     { Bad_Opcode },
7730     { Bad_Opcode },
7731     { Bad_Opcode },
7732     { Bad_Opcode },
7733     { Bad_Opcode },
7734     { Bad_Opcode },
7735     { Bad_Opcode },
7736     { Bad_Opcode },
7737     /* f8 */
7738     { Bad_Opcode },
7739     { Bad_Opcode },
7740     { Bad_Opcode },
7741     { Bad_Opcode },
7742     { Bad_Opcode },
7743     { Bad_Opcode },
7744     { Bad_Opcode },
7745     { Bad_Opcode },
7746   },
7747 };
7748
7749 static const struct dis386 xop_table[][256] = {
7750   /* XOP_08 */
7751   {
7752     /* 00 */
7753     { Bad_Opcode },
7754     { Bad_Opcode },
7755     { Bad_Opcode },
7756     { Bad_Opcode },
7757     { Bad_Opcode },
7758     { Bad_Opcode },
7759     { Bad_Opcode },
7760     { Bad_Opcode },
7761     /* 08 */
7762     { Bad_Opcode },
7763     { Bad_Opcode },
7764     { Bad_Opcode },
7765     { Bad_Opcode },
7766     { Bad_Opcode },
7767     { Bad_Opcode },
7768     { Bad_Opcode },
7769     { Bad_Opcode },
7770     /* 10 */
7771     { Bad_Opcode },
7772     { Bad_Opcode },
7773     { Bad_Opcode },
7774     { Bad_Opcode },
7775     { Bad_Opcode },
7776     { Bad_Opcode },
7777     { Bad_Opcode },
7778     { Bad_Opcode },
7779     /* 18 */
7780     { Bad_Opcode },
7781     { Bad_Opcode },
7782     { Bad_Opcode },
7783     { Bad_Opcode },
7784     { Bad_Opcode },
7785     { Bad_Opcode },
7786     { Bad_Opcode },
7787     { Bad_Opcode },
7788     /* 20 */
7789     { Bad_Opcode },
7790     { Bad_Opcode },
7791     { Bad_Opcode },
7792     { Bad_Opcode },
7793     { Bad_Opcode },
7794     { Bad_Opcode },
7795     { Bad_Opcode },
7796     { Bad_Opcode },
7797     /* 28 */
7798     { Bad_Opcode },
7799     { Bad_Opcode },
7800     { Bad_Opcode },
7801     { Bad_Opcode },
7802     { Bad_Opcode },
7803     { Bad_Opcode },
7804     { Bad_Opcode },
7805     { Bad_Opcode },
7806     /* 30 */
7807     { Bad_Opcode },
7808     { Bad_Opcode },
7809     { Bad_Opcode },
7810     { Bad_Opcode },
7811     { Bad_Opcode },
7812     { Bad_Opcode },
7813     { Bad_Opcode },
7814     { Bad_Opcode },
7815     /* 38 */
7816     { Bad_Opcode },
7817     { Bad_Opcode },
7818     { Bad_Opcode },
7819     { Bad_Opcode },
7820     { Bad_Opcode },
7821     { Bad_Opcode },
7822     { Bad_Opcode },
7823     { Bad_Opcode },
7824     /* 40 */
7825     { Bad_Opcode },
7826     { Bad_Opcode },
7827     { Bad_Opcode },
7828     { Bad_Opcode },
7829     { Bad_Opcode },
7830     { Bad_Opcode },
7831     { Bad_Opcode },
7832     { Bad_Opcode },
7833     /* 48 */
7834     { Bad_Opcode },
7835     { Bad_Opcode },
7836     { Bad_Opcode },
7837     { Bad_Opcode },
7838     { Bad_Opcode },
7839     { Bad_Opcode },
7840     { Bad_Opcode },
7841     { Bad_Opcode },
7842     /* 50 */
7843     { Bad_Opcode },
7844     { Bad_Opcode },
7845     { Bad_Opcode },
7846     { Bad_Opcode },
7847     { Bad_Opcode },
7848     { Bad_Opcode },
7849     { Bad_Opcode },
7850     { Bad_Opcode },
7851     /* 58 */
7852     { Bad_Opcode },
7853     { Bad_Opcode },
7854     { Bad_Opcode },
7855     { Bad_Opcode },
7856     { Bad_Opcode },
7857     { Bad_Opcode },
7858     { Bad_Opcode },
7859     { Bad_Opcode },
7860     /* 60 */
7861     { Bad_Opcode },
7862     { Bad_Opcode },
7863     { Bad_Opcode },
7864     { Bad_Opcode },
7865     { Bad_Opcode },
7866     { Bad_Opcode },
7867     { Bad_Opcode },
7868     { Bad_Opcode },
7869     /* 68 */
7870     { Bad_Opcode },
7871     { Bad_Opcode },
7872     { Bad_Opcode },
7873     { Bad_Opcode },
7874     { Bad_Opcode },
7875     { Bad_Opcode },
7876     { Bad_Opcode },
7877     { Bad_Opcode },
7878     /* 70 */
7879     { Bad_Opcode },
7880     { Bad_Opcode },
7881     { Bad_Opcode },
7882     { Bad_Opcode },
7883     { Bad_Opcode },
7884     { Bad_Opcode },
7885     { Bad_Opcode },
7886     { Bad_Opcode },
7887     /* 78 */
7888     { Bad_Opcode },
7889     { Bad_Opcode },
7890     { Bad_Opcode },
7891     { Bad_Opcode },
7892     { Bad_Opcode },
7893     { Bad_Opcode },
7894     { Bad_Opcode },
7895     { Bad_Opcode },
7896     /* 80 */
7897     { Bad_Opcode },
7898     { Bad_Opcode },
7899     { Bad_Opcode },
7900     { Bad_Opcode },
7901     { Bad_Opcode },
7902     { "vpmacssww",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7903     { "vpmacsswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7904     { "vpmacssdql",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7905     /* 88 */
7906     { Bad_Opcode },
7907     { Bad_Opcode },
7908     { Bad_Opcode },
7909     { Bad_Opcode },
7910     { Bad_Opcode },
7911     { Bad_Opcode },
7912     { "vpmacssdd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7913     { "vpmacssdqh",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7914     /* 90 */
7915     { Bad_Opcode },
7916     { Bad_Opcode },
7917     { Bad_Opcode },
7918     { Bad_Opcode },
7919     { Bad_Opcode },
7920     { "vpmacsww",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7921     { "vpmacswd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7922     { "vpmacsdql",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7923     /* 98 */
7924     { Bad_Opcode },
7925     { Bad_Opcode },
7926     { Bad_Opcode },
7927     { Bad_Opcode },
7928     { Bad_Opcode },
7929     { Bad_Opcode },
7930     { "vpmacsdd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7931     { "vpmacsdqh",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7932     /* a0 */
7933     { Bad_Opcode },
7934     { Bad_Opcode },
7935     { "vpcmov",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7936     { "vpperm",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7937     { Bad_Opcode },
7938     { Bad_Opcode },
7939     { "vpmadcsswd",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7940     { Bad_Opcode },
7941     /* a8 */
7942     { Bad_Opcode },
7943     { Bad_Opcode },
7944     { Bad_Opcode },
7945     { Bad_Opcode },
7946     { Bad_Opcode },
7947     { Bad_Opcode },
7948     { Bad_Opcode },
7949     { Bad_Opcode },
7950     /* b0 */
7951     { Bad_Opcode },
7952     { Bad_Opcode },
7953     { Bad_Opcode },
7954     { Bad_Opcode },
7955     { Bad_Opcode },
7956     { Bad_Opcode },
7957     { "vpmadcswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7958     { Bad_Opcode },
7959     /* b8 */
7960     { Bad_Opcode },
7961     { Bad_Opcode },
7962     { Bad_Opcode },
7963     { Bad_Opcode },
7964     { Bad_Opcode },
7965     { Bad_Opcode },
7966     { Bad_Opcode },
7967     { Bad_Opcode },
7968     /* c0 */
7969     { "vprotb",         { XM, Vex_2src_1, Ib }, 0 },
7970     { "vprotw",         { XM, Vex_2src_1, Ib }, 0 },
7971     { "vprotd",         { XM, Vex_2src_1, Ib }, 0 },
7972     { "vprotq",         { XM, Vex_2src_1, Ib }, 0 },
7973     { Bad_Opcode },
7974     { Bad_Opcode },
7975     { Bad_Opcode },
7976     { Bad_Opcode },
7977     /* c8 */
7978     { Bad_Opcode },
7979     { Bad_Opcode },
7980     { Bad_Opcode },
7981     { Bad_Opcode },
7982     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
7983     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
7984     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
7985     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
7986     /* d0 */
7987     { Bad_Opcode },
7988     { Bad_Opcode },
7989     { Bad_Opcode },
7990     { Bad_Opcode },
7991     { Bad_Opcode },
7992     { Bad_Opcode },
7993     { Bad_Opcode },
7994     { Bad_Opcode },
7995     /* d8 */
7996     { Bad_Opcode },
7997     { Bad_Opcode },
7998     { Bad_Opcode },
7999     { Bad_Opcode },
8000     { Bad_Opcode },
8001     { Bad_Opcode },
8002     { Bad_Opcode },
8003     { Bad_Opcode },
8004     /* e0 */
8005     { Bad_Opcode },
8006     { Bad_Opcode },
8007     { Bad_Opcode },
8008     { Bad_Opcode },
8009     { Bad_Opcode },
8010     { Bad_Opcode },
8011     { Bad_Opcode },
8012     { Bad_Opcode },
8013     /* e8 */
8014     { Bad_Opcode },
8015     { Bad_Opcode },
8016     { Bad_Opcode },
8017     { Bad_Opcode },
8018     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
8019     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
8020     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
8021     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
8022     /* f0 */
8023     { Bad_Opcode },
8024     { Bad_Opcode },
8025     { Bad_Opcode },
8026     { Bad_Opcode },
8027     { Bad_Opcode },
8028     { Bad_Opcode },
8029     { Bad_Opcode },
8030     { Bad_Opcode },
8031     /* f8 */
8032     { Bad_Opcode },
8033     { Bad_Opcode },
8034     { Bad_Opcode },
8035     { Bad_Opcode },
8036     { Bad_Opcode },
8037     { Bad_Opcode },
8038     { Bad_Opcode },
8039     { Bad_Opcode },
8040   },
8041   /* XOP_09 */
8042   {
8043     /* 00 */
8044     { Bad_Opcode },
8045     { REG_TABLE (REG_XOP_TBM_01) },
8046     { REG_TABLE (REG_XOP_TBM_02) },
8047     { Bad_Opcode },
8048     { Bad_Opcode },
8049     { Bad_Opcode },
8050     { Bad_Opcode },
8051     { Bad_Opcode },
8052     /* 08 */
8053     { Bad_Opcode },
8054     { Bad_Opcode },
8055     { Bad_Opcode },
8056     { Bad_Opcode },
8057     { Bad_Opcode },
8058     { Bad_Opcode },
8059     { Bad_Opcode },
8060     { Bad_Opcode },
8061     /* 10 */
8062     { Bad_Opcode },
8063     { Bad_Opcode },
8064     { REG_TABLE (REG_XOP_LWPCB) },
8065     { Bad_Opcode },
8066     { Bad_Opcode },
8067     { Bad_Opcode },
8068     { Bad_Opcode },
8069     { Bad_Opcode },
8070     /* 18 */
8071     { Bad_Opcode },
8072     { Bad_Opcode },
8073     { Bad_Opcode },
8074     { Bad_Opcode },
8075     { Bad_Opcode },
8076     { Bad_Opcode },
8077     { Bad_Opcode },
8078     { Bad_Opcode },
8079     /* 20 */
8080     { Bad_Opcode },
8081     { Bad_Opcode },
8082     { Bad_Opcode },
8083     { Bad_Opcode },
8084     { Bad_Opcode },
8085     { Bad_Opcode },
8086     { Bad_Opcode },
8087     { Bad_Opcode },
8088     /* 28 */
8089     { Bad_Opcode },
8090     { Bad_Opcode },
8091     { Bad_Opcode },
8092     { Bad_Opcode },
8093     { Bad_Opcode },
8094     { Bad_Opcode },
8095     { Bad_Opcode },
8096     { Bad_Opcode },
8097     /* 30 */
8098     { Bad_Opcode },
8099     { Bad_Opcode },
8100     { Bad_Opcode },
8101     { Bad_Opcode },
8102     { Bad_Opcode },
8103     { Bad_Opcode },
8104     { Bad_Opcode },
8105     { Bad_Opcode },
8106     /* 38 */
8107     { Bad_Opcode },
8108     { Bad_Opcode },
8109     { Bad_Opcode },
8110     { Bad_Opcode },
8111     { Bad_Opcode },
8112     { Bad_Opcode },
8113     { Bad_Opcode },
8114     { Bad_Opcode },
8115     /* 40 */
8116     { Bad_Opcode },
8117     { Bad_Opcode },
8118     { Bad_Opcode },
8119     { Bad_Opcode },
8120     { Bad_Opcode },
8121     { Bad_Opcode },
8122     { Bad_Opcode },
8123     { Bad_Opcode },
8124     /* 48 */
8125     { Bad_Opcode },
8126     { Bad_Opcode },
8127     { Bad_Opcode },
8128     { Bad_Opcode },
8129     { Bad_Opcode },
8130     { Bad_Opcode },
8131     { Bad_Opcode },
8132     { Bad_Opcode },
8133     /* 50 */
8134     { Bad_Opcode },
8135     { Bad_Opcode },
8136     { Bad_Opcode },
8137     { Bad_Opcode },
8138     { Bad_Opcode },
8139     { Bad_Opcode },
8140     { Bad_Opcode },
8141     { Bad_Opcode },
8142     /* 58 */
8143     { Bad_Opcode },
8144     { Bad_Opcode },
8145     { Bad_Opcode },
8146     { Bad_Opcode },
8147     { Bad_Opcode },
8148     { Bad_Opcode },
8149     { Bad_Opcode },
8150     { Bad_Opcode },
8151     /* 60 */
8152     { Bad_Opcode },
8153     { Bad_Opcode },
8154     { Bad_Opcode },
8155     { Bad_Opcode },
8156     { Bad_Opcode },
8157     { Bad_Opcode },
8158     { Bad_Opcode },
8159     { Bad_Opcode },
8160     /* 68 */
8161     { Bad_Opcode },
8162     { Bad_Opcode },
8163     { Bad_Opcode },
8164     { Bad_Opcode },
8165     { Bad_Opcode },
8166     { Bad_Opcode },
8167     { Bad_Opcode },
8168     { Bad_Opcode },
8169     /* 70 */
8170     { Bad_Opcode },
8171     { Bad_Opcode },
8172     { Bad_Opcode },
8173     { Bad_Opcode },
8174     { Bad_Opcode },
8175     { Bad_Opcode },
8176     { Bad_Opcode },
8177     { Bad_Opcode },
8178     /* 78 */
8179     { Bad_Opcode },
8180     { Bad_Opcode },
8181     { Bad_Opcode },
8182     { Bad_Opcode },
8183     { Bad_Opcode },
8184     { Bad_Opcode },
8185     { Bad_Opcode },
8186     { Bad_Opcode },
8187     /* 80 */
8188     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
8189     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
8190     { "vfrczss",        { XM, EXd }, 0 },
8191     { "vfrczsd",        { XM, EXq }, 0 },
8192     { Bad_Opcode },
8193     { Bad_Opcode },
8194     { Bad_Opcode },
8195     { Bad_Opcode },
8196     /* 88 */
8197     { Bad_Opcode },
8198     { Bad_Opcode },
8199     { Bad_Opcode },
8200     { Bad_Opcode },
8201     { Bad_Opcode },
8202     { Bad_Opcode },
8203     { Bad_Opcode },
8204     { Bad_Opcode },
8205     /* 90 */
8206     { "vprotb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8207     { "vprotw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8208     { "vprotd",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8209     { "vprotq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8210     { "vpshlb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8211     { "vpshlw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8212     { "vpshld",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8213     { "vpshlq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8214     /* 98 */
8215     { "vpshab",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8216     { "vpshaw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8217     { "vpshad",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8218     { "vpshaq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8219     { Bad_Opcode },
8220     { Bad_Opcode },
8221     { Bad_Opcode },
8222     { Bad_Opcode },
8223     /* a0 */
8224     { Bad_Opcode },
8225     { Bad_Opcode },
8226     { Bad_Opcode },
8227     { Bad_Opcode },
8228     { Bad_Opcode },
8229     { Bad_Opcode },
8230     { Bad_Opcode },
8231     { Bad_Opcode },
8232     /* a8 */
8233     { Bad_Opcode },
8234     { Bad_Opcode },
8235     { Bad_Opcode },
8236     { Bad_Opcode },
8237     { Bad_Opcode },
8238     { Bad_Opcode },
8239     { Bad_Opcode },
8240     { Bad_Opcode },
8241     /* b0 */
8242     { Bad_Opcode },
8243     { Bad_Opcode },
8244     { Bad_Opcode },
8245     { Bad_Opcode },
8246     { Bad_Opcode },
8247     { Bad_Opcode },
8248     { Bad_Opcode },
8249     { Bad_Opcode },
8250     /* b8 */
8251     { Bad_Opcode },
8252     { Bad_Opcode },
8253     { Bad_Opcode },
8254     { Bad_Opcode },
8255     { Bad_Opcode },
8256     { Bad_Opcode },
8257     { Bad_Opcode },
8258     { Bad_Opcode },
8259     /* c0 */
8260     { Bad_Opcode },
8261     { "vphaddbw",       { XM, EXxmm }, 0 },
8262     { "vphaddbd",       { XM, EXxmm }, 0 },
8263     { "vphaddbq",       { XM, EXxmm }, 0 },
8264     { Bad_Opcode },
8265     { Bad_Opcode },
8266     { "vphaddwd",       { XM, EXxmm }, 0 },
8267     { "vphaddwq",       { XM, EXxmm }, 0 },
8268     /* c8 */
8269     { Bad_Opcode },
8270     { Bad_Opcode },
8271     { Bad_Opcode },
8272     { "vphadddq",       { XM, EXxmm }, 0 },
8273     { Bad_Opcode },
8274     { Bad_Opcode },
8275     { Bad_Opcode },
8276     { Bad_Opcode },
8277     /* d0 */
8278     { Bad_Opcode },
8279     { "vphaddubw",      { XM, EXxmm }, 0 },
8280     { "vphaddubd",      { XM, EXxmm }, 0 },
8281     { "vphaddubq",      { XM, EXxmm }, 0 },
8282     { Bad_Opcode },
8283     { Bad_Opcode },
8284     { "vphadduwd",      { XM, EXxmm }, 0 },
8285     { "vphadduwq",      { XM, EXxmm }, 0 },
8286     /* d8 */
8287     { Bad_Opcode },
8288     { Bad_Opcode },
8289     { Bad_Opcode },
8290     { "vphaddudq",      { XM, EXxmm }, 0 },
8291     { Bad_Opcode },
8292     { Bad_Opcode },
8293     { Bad_Opcode },
8294     { Bad_Opcode },
8295     /* e0 */
8296     { Bad_Opcode },
8297     { "vphsubbw",       { XM, EXxmm }, 0 },
8298     { "vphsubwd",       { XM, EXxmm }, 0 },
8299     { "vphsubdq",       { XM, EXxmm }, 0 },
8300     { Bad_Opcode },
8301     { Bad_Opcode },
8302     { Bad_Opcode },
8303     { Bad_Opcode },
8304     /* e8 */
8305     { Bad_Opcode },
8306     { Bad_Opcode },
8307     { Bad_Opcode },
8308     { Bad_Opcode },
8309     { Bad_Opcode },
8310     { Bad_Opcode },
8311     { Bad_Opcode },
8312     { Bad_Opcode },
8313     /* f0 */
8314     { Bad_Opcode },
8315     { Bad_Opcode },
8316     { Bad_Opcode },
8317     { Bad_Opcode },
8318     { Bad_Opcode },
8319     { Bad_Opcode },
8320     { Bad_Opcode },
8321     { Bad_Opcode },
8322     /* f8 */
8323     { Bad_Opcode },
8324     { Bad_Opcode },
8325     { Bad_Opcode },
8326     { Bad_Opcode },
8327     { Bad_Opcode },
8328     { Bad_Opcode },
8329     { Bad_Opcode },
8330     { Bad_Opcode },
8331   },
8332   /* XOP_0A */
8333   {
8334     /* 00 */
8335     { Bad_Opcode },
8336     { Bad_Opcode },
8337     { Bad_Opcode },
8338     { Bad_Opcode },
8339     { Bad_Opcode },
8340     { Bad_Opcode },
8341     { Bad_Opcode },
8342     { Bad_Opcode },
8343     /* 08 */
8344     { Bad_Opcode },
8345     { Bad_Opcode },
8346     { Bad_Opcode },
8347     { Bad_Opcode },
8348     { Bad_Opcode },
8349     { Bad_Opcode },
8350     { Bad_Opcode },
8351     { Bad_Opcode },
8352     /* 10 */
8353     { "bextr",  { Gv, Ev, Iq }, 0 },
8354     { Bad_Opcode },
8355     { REG_TABLE (REG_XOP_LWP) },
8356     { Bad_Opcode },
8357     { Bad_Opcode },
8358     { Bad_Opcode },
8359     { Bad_Opcode },
8360     { Bad_Opcode },
8361     /* 18 */
8362     { Bad_Opcode },
8363     { Bad_Opcode },
8364     { Bad_Opcode },
8365     { Bad_Opcode },
8366     { Bad_Opcode },
8367     { Bad_Opcode },
8368     { Bad_Opcode },
8369     { Bad_Opcode },
8370     /* 20 */
8371     { Bad_Opcode },
8372     { Bad_Opcode },
8373     { Bad_Opcode },
8374     { Bad_Opcode },
8375     { Bad_Opcode },
8376     { Bad_Opcode },
8377     { Bad_Opcode },
8378     { Bad_Opcode },
8379     /* 28 */
8380     { Bad_Opcode },
8381     { Bad_Opcode },
8382     { Bad_Opcode },
8383     { Bad_Opcode },
8384     { Bad_Opcode },
8385     { Bad_Opcode },
8386     { Bad_Opcode },
8387     { Bad_Opcode },
8388     /* 30 */
8389     { Bad_Opcode },
8390     { Bad_Opcode },
8391     { Bad_Opcode },
8392     { Bad_Opcode },
8393     { Bad_Opcode },
8394     { Bad_Opcode },
8395     { Bad_Opcode },
8396     { Bad_Opcode },
8397     /* 38 */
8398     { Bad_Opcode },
8399     { Bad_Opcode },
8400     { Bad_Opcode },
8401     { Bad_Opcode },
8402     { Bad_Opcode },
8403     { Bad_Opcode },
8404     { Bad_Opcode },
8405     { Bad_Opcode },
8406     /* 40 */
8407     { Bad_Opcode },
8408     { Bad_Opcode },
8409     { Bad_Opcode },
8410     { Bad_Opcode },
8411     { Bad_Opcode },
8412     { Bad_Opcode },
8413     { Bad_Opcode },
8414     { Bad_Opcode },
8415     /* 48 */
8416     { Bad_Opcode },
8417     { Bad_Opcode },
8418     { Bad_Opcode },
8419     { Bad_Opcode },
8420     { Bad_Opcode },
8421     { Bad_Opcode },
8422     { Bad_Opcode },
8423     { Bad_Opcode },
8424     /* 50 */
8425     { Bad_Opcode },
8426     { Bad_Opcode },
8427     { Bad_Opcode },
8428     { Bad_Opcode },
8429     { Bad_Opcode },
8430     { Bad_Opcode },
8431     { Bad_Opcode },
8432     { Bad_Opcode },
8433     /* 58 */
8434     { Bad_Opcode },
8435     { Bad_Opcode },
8436     { Bad_Opcode },
8437     { Bad_Opcode },
8438     { Bad_Opcode },
8439     { Bad_Opcode },
8440     { Bad_Opcode },
8441     { Bad_Opcode },
8442     /* 60 */
8443     { Bad_Opcode },
8444     { Bad_Opcode },
8445     { Bad_Opcode },
8446     { Bad_Opcode },
8447     { Bad_Opcode },
8448     { Bad_Opcode },
8449     { Bad_Opcode },
8450     { Bad_Opcode },
8451     /* 68 */
8452     { Bad_Opcode },
8453     { Bad_Opcode },
8454     { Bad_Opcode },
8455     { Bad_Opcode },
8456     { Bad_Opcode },
8457     { Bad_Opcode },
8458     { Bad_Opcode },
8459     { Bad_Opcode },
8460     /* 70 */
8461     { Bad_Opcode },
8462     { Bad_Opcode },
8463     { Bad_Opcode },
8464     { Bad_Opcode },
8465     { Bad_Opcode },
8466     { Bad_Opcode },
8467     { Bad_Opcode },
8468     { Bad_Opcode },
8469     /* 78 */
8470     { Bad_Opcode },
8471     { Bad_Opcode },
8472     { Bad_Opcode },
8473     { Bad_Opcode },
8474     { Bad_Opcode },
8475     { Bad_Opcode },
8476     { Bad_Opcode },
8477     { Bad_Opcode },
8478     /* 80 */
8479     { Bad_Opcode },
8480     { Bad_Opcode },
8481     { Bad_Opcode },
8482     { Bad_Opcode },
8483     { Bad_Opcode },
8484     { Bad_Opcode },
8485     { Bad_Opcode },
8486     { Bad_Opcode },
8487     /* 88 */
8488     { Bad_Opcode },
8489     { Bad_Opcode },
8490     { Bad_Opcode },
8491     { Bad_Opcode },
8492     { Bad_Opcode },
8493     { Bad_Opcode },
8494     { Bad_Opcode },
8495     { Bad_Opcode },
8496     /* 90 */
8497     { Bad_Opcode },
8498     { Bad_Opcode },
8499     { Bad_Opcode },
8500     { Bad_Opcode },
8501     { Bad_Opcode },
8502     { Bad_Opcode },
8503     { Bad_Opcode },
8504     { Bad_Opcode },
8505     /* 98 */
8506     { Bad_Opcode },
8507     { Bad_Opcode },
8508     { Bad_Opcode },
8509     { Bad_Opcode },
8510     { Bad_Opcode },
8511     { Bad_Opcode },
8512     { Bad_Opcode },
8513     { Bad_Opcode },
8514     /* a0 */
8515     { Bad_Opcode },
8516     { Bad_Opcode },
8517     { Bad_Opcode },
8518     { Bad_Opcode },
8519     { Bad_Opcode },
8520     { Bad_Opcode },
8521     { Bad_Opcode },
8522     { Bad_Opcode },
8523     /* a8 */
8524     { Bad_Opcode },
8525     { Bad_Opcode },
8526     { Bad_Opcode },
8527     { Bad_Opcode },
8528     { Bad_Opcode },
8529     { Bad_Opcode },
8530     { Bad_Opcode },
8531     { Bad_Opcode },
8532     /* b0 */
8533     { Bad_Opcode },
8534     { Bad_Opcode },
8535     { Bad_Opcode },
8536     { Bad_Opcode },
8537     { Bad_Opcode },
8538     { Bad_Opcode },
8539     { Bad_Opcode },
8540     { Bad_Opcode },
8541     /* b8 */
8542     { Bad_Opcode },
8543     { Bad_Opcode },
8544     { Bad_Opcode },
8545     { Bad_Opcode },
8546     { Bad_Opcode },
8547     { Bad_Opcode },
8548     { Bad_Opcode },
8549     { Bad_Opcode },
8550     /* c0 */
8551     { Bad_Opcode },
8552     { Bad_Opcode },
8553     { Bad_Opcode },
8554     { Bad_Opcode },
8555     { Bad_Opcode },
8556     { Bad_Opcode },
8557     { Bad_Opcode },
8558     { Bad_Opcode },
8559     /* c8 */
8560     { Bad_Opcode },
8561     { Bad_Opcode },
8562     { Bad_Opcode },
8563     { Bad_Opcode },
8564     { Bad_Opcode },
8565     { Bad_Opcode },
8566     { Bad_Opcode },
8567     { Bad_Opcode },
8568     /* d0 */
8569     { Bad_Opcode },
8570     { Bad_Opcode },
8571     { Bad_Opcode },
8572     { Bad_Opcode },
8573     { Bad_Opcode },
8574     { Bad_Opcode },
8575     { Bad_Opcode },
8576     { Bad_Opcode },
8577     /* d8 */
8578     { Bad_Opcode },
8579     { Bad_Opcode },
8580     { Bad_Opcode },
8581     { Bad_Opcode },
8582     { Bad_Opcode },
8583     { Bad_Opcode },
8584     { Bad_Opcode },
8585     { Bad_Opcode },
8586     /* e0 */
8587     { Bad_Opcode },
8588     { Bad_Opcode },
8589     { Bad_Opcode },
8590     { Bad_Opcode },
8591     { Bad_Opcode },
8592     { Bad_Opcode },
8593     { Bad_Opcode },
8594     { Bad_Opcode },
8595     /* e8 */
8596     { Bad_Opcode },
8597     { Bad_Opcode },
8598     { Bad_Opcode },
8599     { Bad_Opcode },
8600     { Bad_Opcode },
8601     { Bad_Opcode },
8602     { Bad_Opcode },
8603     { Bad_Opcode },
8604     /* f0 */
8605     { Bad_Opcode },
8606     { Bad_Opcode },
8607     { Bad_Opcode },
8608     { Bad_Opcode },
8609     { Bad_Opcode },
8610     { Bad_Opcode },
8611     { Bad_Opcode },
8612     { Bad_Opcode },
8613     /* f8 */
8614     { Bad_Opcode },
8615     { Bad_Opcode },
8616     { Bad_Opcode },
8617     { Bad_Opcode },
8618     { Bad_Opcode },
8619     { Bad_Opcode },
8620     { Bad_Opcode },
8621     { Bad_Opcode },
8622   },
8623 };
8624
8625 static const struct dis386 vex_table[][256] = {
8626   /* VEX_0F */
8627   {
8628     /* 00 */
8629     { Bad_Opcode },
8630     { Bad_Opcode },
8631     { Bad_Opcode },
8632     { Bad_Opcode },
8633     { Bad_Opcode },
8634     { Bad_Opcode },
8635     { Bad_Opcode },
8636     { Bad_Opcode },
8637     /* 08 */
8638     { Bad_Opcode },
8639     { Bad_Opcode },
8640     { Bad_Opcode },
8641     { Bad_Opcode },
8642     { Bad_Opcode },
8643     { Bad_Opcode },
8644     { Bad_Opcode },
8645     { Bad_Opcode },
8646     /* 10 */
8647     { PREFIX_TABLE (PREFIX_VEX_0F10) },
8648     { PREFIX_TABLE (PREFIX_VEX_0F11) },
8649     { PREFIX_TABLE (PREFIX_VEX_0F12) },
8650     { MOD_TABLE (MOD_VEX_0F13) },
8651     { VEX_W_TABLE (VEX_W_0F14) },
8652     { VEX_W_TABLE (VEX_W_0F15) },
8653     { PREFIX_TABLE (PREFIX_VEX_0F16) },
8654     { MOD_TABLE (MOD_VEX_0F17) },
8655     /* 18 */
8656     { Bad_Opcode },
8657     { Bad_Opcode },
8658     { Bad_Opcode },
8659     { Bad_Opcode },
8660     { Bad_Opcode },
8661     { Bad_Opcode },
8662     { Bad_Opcode },
8663     { Bad_Opcode },
8664     /* 20 */
8665     { Bad_Opcode },
8666     { Bad_Opcode },
8667     { Bad_Opcode },
8668     { Bad_Opcode },
8669     { Bad_Opcode },
8670     { Bad_Opcode },
8671     { Bad_Opcode },
8672     { Bad_Opcode },
8673     /* 28 */
8674     { VEX_W_TABLE (VEX_W_0F28) },
8675     { VEX_W_TABLE (VEX_W_0F29) },
8676     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8677     { MOD_TABLE (MOD_VEX_0F2B) },
8678     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8679     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8680     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8681     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8682     /* 30 */
8683     { Bad_Opcode },
8684     { Bad_Opcode },
8685     { Bad_Opcode },
8686     { Bad_Opcode },
8687     { Bad_Opcode },
8688     { Bad_Opcode },
8689     { Bad_Opcode },
8690     { Bad_Opcode },
8691     /* 38 */
8692     { Bad_Opcode },
8693     { Bad_Opcode },
8694     { Bad_Opcode },
8695     { Bad_Opcode },
8696     { Bad_Opcode },
8697     { Bad_Opcode },
8698     { Bad_Opcode },
8699     { Bad_Opcode },
8700     /* 40 */
8701     { Bad_Opcode },
8702     { PREFIX_TABLE (PREFIX_VEX_0F41) },
8703     { PREFIX_TABLE (PREFIX_VEX_0F42) },
8704     { Bad_Opcode },
8705     { PREFIX_TABLE (PREFIX_VEX_0F44) },
8706     { PREFIX_TABLE (PREFIX_VEX_0F45) },
8707     { PREFIX_TABLE (PREFIX_VEX_0F46) },
8708     { PREFIX_TABLE (PREFIX_VEX_0F47) },
8709     /* 48 */
8710     { Bad_Opcode },
8711     { Bad_Opcode },
8712     { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8713     { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8714     { Bad_Opcode },
8715     { Bad_Opcode },
8716     { Bad_Opcode },
8717     { Bad_Opcode },
8718     /* 50 */
8719     { MOD_TABLE (MOD_VEX_0F50) },
8720     { PREFIX_TABLE (PREFIX_VEX_0F51) },
8721     { PREFIX_TABLE (PREFIX_VEX_0F52) },
8722     { PREFIX_TABLE (PREFIX_VEX_0F53) },
8723     { "vandpX",         { XM, Vex, EXx }, 0 },
8724     { "vandnpX",        { XM, Vex, EXx }, 0 },
8725     { "vorpX",          { XM, Vex, EXx }, 0 },
8726     { "vxorpX",         { XM, Vex, EXx }, 0 },
8727     /* 58 */
8728     { PREFIX_TABLE (PREFIX_VEX_0F58) },
8729     { PREFIX_TABLE (PREFIX_VEX_0F59) },
8730     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8731     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8732     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8733     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8734     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8735     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8736     /* 60 */
8737     { PREFIX_TABLE (PREFIX_VEX_0F60) },
8738     { PREFIX_TABLE (PREFIX_VEX_0F61) },
8739     { PREFIX_TABLE (PREFIX_VEX_0F62) },
8740     { PREFIX_TABLE (PREFIX_VEX_0F63) },
8741     { PREFIX_TABLE (PREFIX_VEX_0F64) },
8742     { PREFIX_TABLE (PREFIX_VEX_0F65) },
8743     { PREFIX_TABLE (PREFIX_VEX_0F66) },
8744     { PREFIX_TABLE (PREFIX_VEX_0F67) },
8745     /* 68 */
8746     { PREFIX_TABLE (PREFIX_VEX_0F68) },
8747     { PREFIX_TABLE (PREFIX_VEX_0F69) },
8748     { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8749     { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8750     { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8751     { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8752     { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8753     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8754     /* 70 */
8755     { PREFIX_TABLE (PREFIX_VEX_0F70) },
8756     { REG_TABLE (REG_VEX_0F71) },
8757     { REG_TABLE (REG_VEX_0F72) },
8758     { REG_TABLE (REG_VEX_0F73) },
8759     { PREFIX_TABLE (PREFIX_VEX_0F74) },
8760     { PREFIX_TABLE (PREFIX_VEX_0F75) },
8761     { PREFIX_TABLE (PREFIX_VEX_0F76) },
8762     { PREFIX_TABLE (PREFIX_VEX_0F77) },
8763     /* 78 */
8764     { Bad_Opcode },
8765     { Bad_Opcode },
8766     { Bad_Opcode },
8767     { Bad_Opcode },
8768     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8769     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8770     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8771     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8772     /* 80 */
8773     { Bad_Opcode },
8774     { Bad_Opcode },
8775     { Bad_Opcode },
8776     { Bad_Opcode },
8777     { Bad_Opcode },
8778     { Bad_Opcode },
8779     { Bad_Opcode },
8780     { Bad_Opcode },
8781     /* 88 */
8782     { Bad_Opcode },
8783     { Bad_Opcode },
8784     { Bad_Opcode },
8785     { Bad_Opcode },
8786     { Bad_Opcode },
8787     { Bad_Opcode },
8788     { Bad_Opcode },
8789     { Bad_Opcode },
8790     /* 90 */
8791     { PREFIX_TABLE (PREFIX_VEX_0F90) },
8792     { PREFIX_TABLE (PREFIX_VEX_0F91) },
8793     { PREFIX_TABLE (PREFIX_VEX_0F92) },
8794     { PREFIX_TABLE (PREFIX_VEX_0F93) },
8795     { Bad_Opcode },
8796     { Bad_Opcode },
8797     { Bad_Opcode },
8798     { Bad_Opcode },
8799     /* 98 */
8800     { PREFIX_TABLE (PREFIX_VEX_0F98) },
8801     { PREFIX_TABLE (PREFIX_VEX_0F99) },
8802     { Bad_Opcode },
8803     { Bad_Opcode },
8804     { Bad_Opcode },
8805     { Bad_Opcode },
8806     { Bad_Opcode },
8807     { Bad_Opcode },
8808     /* a0 */
8809     { Bad_Opcode },
8810     { Bad_Opcode },
8811     { Bad_Opcode },
8812     { Bad_Opcode },
8813     { Bad_Opcode },
8814     { Bad_Opcode },
8815     { Bad_Opcode },
8816     { Bad_Opcode },
8817     /* a8 */
8818     { Bad_Opcode },
8819     { Bad_Opcode },
8820     { Bad_Opcode },
8821     { Bad_Opcode },
8822     { Bad_Opcode },
8823     { Bad_Opcode },
8824     { REG_TABLE (REG_VEX_0FAE) },
8825     { Bad_Opcode },
8826     /* b0 */
8827     { Bad_Opcode },
8828     { Bad_Opcode },
8829     { Bad_Opcode },
8830     { Bad_Opcode },
8831     { Bad_Opcode },
8832     { Bad_Opcode },
8833     { Bad_Opcode },
8834     { Bad_Opcode },
8835     /* b8 */
8836     { Bad_Opcode },
8837     { Bad_Opcode },
8838     { Bad_Opcode },
8839     { Bad_Opcode },
8840     { Bad_Opcode },
8841     { Bad_Opcode },
8842     { Bad_Opcode },
8843     { Bad_Opcode },
8844     /* c0 */
8845     { Bad_Opcode },
8846     { Bad_Opcode },
8847     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8848     { Bad_Opcode },
8849     { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8850     { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8851     { "vshufpX",        { XM, Vex, EXx, Ib }, 0 },
8852     { Bad_Opcode },
8853     /* c8 */
8854     { Bad_Opcode },
8855     { Bad_Opcode },
8856     { Bad_Opcode },
8857     { Bad_Opcode },
8858     { Bad_Opcode },
8859     { Bad_Opcode },
8860     { Bad_Opcode },
8861     { Bad_Opcode },
8862     /* d0 */
8863     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8864     { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8865     { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8866     { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8867     { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8868     { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8869     { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8870     { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8871     /* d8 */
8872     { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8873     { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8874     { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8875     { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8876     { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8877     { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8878     { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8879     { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8880     /* e0 */
8881     { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8882     { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8883     { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8884     { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8885     { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8886     { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8887     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8888     { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8889     /* e8 */
8890     { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8891     { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8892     { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8893     { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8894     { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8895     { PREFIX_TABLE (PREFIX_VEX_0FED) },
8896     { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8897     { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8898     /* f0 */
8899     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8900     { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8901     { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8902     { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8903     { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8904     { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8905     { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8906     { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8907     /* f8 */
8908     { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8909     { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8910     { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8911     { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8912     { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8913     { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8914     { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8915     { Bad_Opcode },
8916   },
8917   /* VEX_0F38 */
8918   {
8919     /* 00 */
8920     { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8921     { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8922     { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8923     { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8924     { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8925     { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8926     { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8927     { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8928     /* 08 */
8929     { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8930     { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8931     { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8932     { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8933     { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8934     { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8935     { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8936     { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8937     /* 10 */
8938     { Bad_Opcode },
8939     { Bad_Opcode },
8940     { Bad_Opcode },
8941     { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8942     { Bad_Opcode },
8943     { Bad_Opcode },
8944     { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8945     { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8946     /* 18 */
8947     { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8948     { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8949     { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8950     { Bad_Opcode },
8951     { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8952     { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8953     { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8954     { Bad_Opcode },
8955     /* 20 */
8956     { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8957     { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8958     { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8959     { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8960     { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8961     { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8962     { Bad_Opcode },
8963     { Bad_Opcode },
8964     /* 28 */
8965     { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8966     { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8967     { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8968     { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8969     { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8970     { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8971     { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8972     { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8973     /* 30 */
8974     { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8975     { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8976     { PREFIX_TABLE (PREFIX_VEX_0F3832) },
8977     { PREFIX_TABLE (PREFIX_VEX_0F3833) },
8978     { PREFIX_TABLE (PREFIX_VEX_0F3834) },
8979     { PREFIX_TABLE (PREFIX_VEX_0F3835) },
8980     { PREFIX_TABLE (PREFIX_VEX_0F3836) },
8981     { PREFIX_TABLE (PREFIX_VEX_0F3837) },
8982     /* 38 */
8983     { PREFIX_TABLE (PREFIX_VEX_0F3838) },
8984     { PREFIX_TABLE (PREFIX_VEX_0F3839) },
8985     { PREFIX_TABLE (PREFIX_VEX_0F383A) },
8986     { PREFIX_TABLE (PREFIX_VEX_0F383B) },
8987     { PREFIX_TABLE (PREFIX_VEX_0F383C) },
8988     { PREFIX_TABLE (PREFIX_VEX_0F383D) },
8989     { PREFIX_TABLE (PREFIX_VEX_0F383E) },
8990     { PREFIX_TABLE (PREFIX_VEX_0F383F) },
8991     /* 40 */
8992     { PREFIX_TABLE (PREFIX_VEX_0F3840) },
8993     { PREFIX_TABLE (PREFIX_VEX_0F3841) },
8994     { Bad_Opcode },
8995     { Bad_Opcode },
8996     { Bad_Opcode },
8997     { PREFIX_TABLE (PREFIX_VEX_0F3845) },
8998     { PREFIX_TABLE (PREFIX_VEX_0F3846) },
8999     { PREFIX_TABLE (PREFIX_VEX_0F3847) },
9000     /* 48 */
9001     { Bad_Opcode },
9002     { Bad_Opcode },
9003     { Bad_Opcode },
9004     { Bad_Opcode },
9005     { Bad_Opcode },
9006     { Bad_Opcode },
9007     { Bad_Opcode },
9008     { Bad_Opcode },
9009     /* 50 */
9010     { Bad_Opcode },
9011     { Bad_Opcode },
9012     { Bad_Opcode },
9013     { Bad_Opcode },
9014     { Bad_Opcode },
9015     { Bad_Opcode },
9016     { Bad_Opcode },
9017     { Bad_Opcode },
9018     /* 58 */
9019     { PREFIX_TABLE (PREFIX_VEX_0F3858) },
9020     { PREFIX_TABLE (PREFIX_VEX_0F3859) },
9021     { PREFIX_TABLE (PREFIX_VEX_0F385A) },
9022     { Bad_Opcode },
9023     { Bad_Opcode },
9024     { Bad_Opcode },
9025     { Bad_Opcode },
9026     { Bad_Opcode },
9027     /* 60 */
9028     { Bad_Opcode },
9029     { Bad_Opcode },
9030     { Bad_Opcode },
9031     { Bad_Opcode },
9032     { Bad_Opcode },
9033     { Bad_Opcode },
9034     { Bad_Opcode },
9035     { Bad_Opcode },
9036     /* 68 */
9037     { Bad_Opcode },
9038     { Bad_Opcode },
9039     { Bad_Opcode },
9040     { Bad_Opcode },
9041     { Bad_Opcode },
9042     { Bad_Opcode },
9043     { Bad_Opcode },
9044     { Bad_Opcode },
9045     /* 70 */
9046     { Bad_Opcode },
9047     { Bad_Opcode },
9048     { Bad_Opcode },
9049     { Bad_Opcode },
9050     { Bad_Opcode },
9051     { Bad_Opcode },
9052     { Bad_Opcode },
9053     { Bad_Opcode },
9054     /* 78 */
9055     { PREFIX_TABLE (PREFIX_VEX_0F3878) },
9056     { PREFIX_TABLE (PREFIX_VEX_0F3879) },
9057     { Bad_Opcode },
9058     { Bad_Opcode },
9059     { Bad_Opcode },
9060     { Bad_Opcode },
9061     { Bad_Opcode },
9062     { Bad_Opcode },
9063     /* 80 */
9064     { Bad_Opcode },
9065     { Bad_Opcode },
9066     { Bad_Opcode },
9067     { Bad_Opcode },
9068     { Bad_Opcode },
9069     { Bad_Opcode },
9070     { Bad_Opcode },
9071     { Bad_Opcode },
9072     /* 88 */
9073     { Bad_Opcode },
9074     { Bad_Opcode },
9075     { Bad_Opcode },
9076     { Bad_Opcode },
9077     { PREFIX_TABLE (PREFIX_VEX_0F388C) },
9078     { Bad_Opcode },
9079     { PREFIX_TABLE (PREFIX_VEX_0F388E) },
9080     { Bad_Opcode },
9081     /* 90 */
9082     { PREFIX_TABLE (PREFIX_VEX_0F3890) },
9083     { PREFIX_TABLE (PREFIX_VEX_0F3891) },
9084     { PREFIX_TABLE (PREFIX_VEX_0F3892) },
9085     { PREFIX_TABLE (PREFIX_VEX_0F3893) },
9086     { Bad_Opcode },
9087     { Bad_Opcode },
9088     { PREFIX_TABLE (PREFIX_VEX_0F3896) },
9089     { PREFIX_TABLE (PREFIX_VEX_0F3897) },
9090     /* 98 */
9091     { PREFIX_TABLE (PREFIX_VEX_0F3898) },
9092     { PREFIX_TABLE (PREFIX_VEX_0F3899) },
9093     { PREFIX_TABLE (PREFIX_VEX_0F389A) },
9094     { PREFIX_TABLE (PREFIX_VEX_0F389B) },
9095     { PREFIX_TABLE (PREFIX_VEX_0F389C) },
9096     { PREFIX_TABLE (PREFIX_VEX_0F389D) },
9097     { PREFIX_TABLE (PREFIX_VEX_0F389E) },
9098     { PREFIX_TABLE (PREFIX_VEX_0F389F) },
9099     /* a0 */
9100     { Bad_Opcode },
9101     { Bad_Opcode },
9102     { Bad_Opcode },
9103     { Bad_Opcode },
9104     { Bad_Opcode },
9105     { Bad_Opcode },
9106     { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
9107     { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
9108     /* a8 */
9109     { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
9110     { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
9111     { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
9112     { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
9113     { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
9114     { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
9115     { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
9116     { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
9117     /* b0 */
9118     { Bad_Opcode },
9119     { Bad_Opcode },
9120     { Bad_Opcode },
9121     { Bad_Opcode },
9122     { Bad_Opcode },
9123     { Bad_Opcode },
9124     { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
9125     { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
9126     /* b8 */
9127     { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
9128     { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
9129     { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
9130     { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
9131     { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
9132     { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
9133     { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
9134     { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
9135     /* c0 */
9136     { Bad_Opcode },
9137     { Bad_Opcode },
9138     { Bad_Opcode },
9139     { Bad_Opcode },
9140     { Bad_Opcode },
9141     { Bad_Opcode },
9142     { Bad_Opcode },
9143     { Bad_Opcode },
9144     /* c8 */
9145     { Bad_Opcode },
9146     { Bad_Opcode },
9147     { Bad_Opcode },
9148     { Bad_Opcode },
9149     { Bad_Opcode },
9150     { Bad_Opcode },
9151     { Bad_Opcode },
9152     { Bad_Opcode },
9153     /* d0 */
9154     { Bad_Opcode },
9155     { Bad_Opcode },
9156     { Bad_Opcode },
9157     { Bad_Opcode },
9158     { Bad_Opcode },
9159     { Bad_Opcode },
9160     { Bad_Opcode },
9161     { Bad_Opcode },
9162     /* d8 */
9163     { Bad_Opcode },
9164     { Bad_Opcode },
9165     { Bad_Opcode },
9166     { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
9167     { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
9168     { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
9169     { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
9170     { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
9171     /* e0 */
9172     { Bad_Opcode },
9173     { Bad_Opcode },
9174     { Bad_Opcode },
9175     { Bad_Opcode },
9176     { Bad_Opcode },
9177     { Bad_Opcode },
9178     { Bad_Opcode },
9179     { Bad_Opcode },
9180     /* e8 */
9181     { Bad_Opcode },
9182     { Bad_Opcode },
9183     { Bad_Opcode },
9184     { Bad_Opcode },
9185     { Bad_Opcode },
9186     { Bad_Opcode },
9187     { Bad_Opcode },
9188     { Bad_Opcode },
9189     /* f0 */
9190     { Bad_Opcode },
9191     { Bad_Opcode },
9192     { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
9193     { REG_TABLE (REG_VEX_0F38F3) },
9194     { Bad_Opcode },
9195     { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
9196     { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
9197     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
9198     /* f8 */
9199     { Bad_Opcode },
9200     { Bad_Opcode },
9201     { Bad_Opcode },
9202     { Bad_Opcode },
9203     { Bad_Opcode },
9204     { Bad_Opcode },
9205     { Bad_Opcode },
9206     { Bad_Opcode },
9207   },
9208   /* VEX_0F3A */
9209   {
9210     /* 00 */
9211     { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
9212     { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
9213     { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
9214     { Bad_Opcode },
9215     { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
9216     { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
9217     { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
9218     { Bad_Opcode },
9219     /* 08 */
9220     { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
9221     { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
9222     { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
9223     { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
9224     { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
9225     { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
9226     { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
9227     { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
9228     /* 10 */
9229     { Bad_Opcode },
9230     { Bad_Opcode },
9231     { Bad_Opcode },
9232     { Bad_Opcode },
9233     { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
9234     { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
9235     { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
9236     { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
9237     /* 18 */
9238     { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
9239     { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
9240     { Bad_Opcode },
9241     { Bad_Opcode },
9242     { Bad_Opcode },
9243     { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
9244     { Bad_Opcode },
9245     { Bad_Opcode },
9246     /* 20 */
9247     { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
9248     { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
9249     { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
9250     { Bad_Opcode },
9251     { Bad_Opcode },
9252     { Bad_Opcode },
9253     { Bad_Opcode },
9254     { Bad_Opcode },
9255     /* 28 */
9256     { Bad_Opcode },
9257     { Bad_Opcode },
9258     { Bad_Opcode },
9259     { Bad_Opcode },
9260     { Bad_Opcode },
9261     { Bad_Opcode },
9262     { Bad_Opcode },
9263     { Bad_Opcode },
9264     /* 30 */
9265     { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
9266     { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
9267     { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
9268     { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
9269     { Bad_Opcode },
9270     { Bad_Opcode },
9271     { Bad_Opcode },
9272     { Bad_Opcode },
9273     /* 38 */
9274     { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
9275     { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
9276     { Bad_Opcode },
9277     { Bad_Opcode },
9278     { Bad_Opcode },
9279     { Bad_Opcode },
9280     { Bad_Opcode },
9281     { Bad_Opcode },
9282     /* 40 */
9283     { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
9284     { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
9285     { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
9286     { Bad_Opcode },
9287     { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
9288     { Bad_Opcode },
9289     { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
9290     { Bad_Opcode },
9291     /* 48 */
9292     { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
9293     { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
9294     { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
9295     { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
9296     { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
9297     { Bad_Opcode },
9298     { Bad_Opcode },
9299     { Bad_Opcode },
9300     /* 50 */
9301     { Bad_Opcode },
9302     { Bad_Opcode },
9303     { Bad_Opcode },
9304     { Bad_Opcode },
9305     { Bad_Opcode },
9306     { Bad_Opcode },
9307     { Bad_Opcode },
9308     { Bad_Opcode },
9309     /* 58 */
9310     { Bad_Opcode },
9311     { Bad_Opcode },
9312     { Bad_Opcode },
9313     { Bad_Opcode },
9314     { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9315     { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9316     { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9317     { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9318     /* 60 */
9319     { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9320     { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9321     { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9322     { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9323     { Bad_Opcode },
9324     { Bad_Opcode },
9325     { Bad_Opcode },
9326     { Bad_Opcode },
9327     /* 68 */
9328     { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9329     { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9330     { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9331     { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9332     { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9333     { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9334     { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9335     { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9336     /* 70 */
9337     { Bad_Opcode },
9338     { Bad_Opcode },
9339     { Bad_Opcode },
9340     { Bad_Opcode },
9341     { Bad_Opcode },
9342     { Bad_Opcode },
9343     { Bad_Opcode },
9344     { Bad_Opcode },
9345     /* 78 */
9346     { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9347     { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9348     { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9349     { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9350     { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9351     { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9352     { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9353     { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9354     /* 80 */
9355     { Bad_Opcode },
9356     { Bad_Opcode },
9357     { Bad_Opcode },
9358     { Bad_Opcode },
9359     { Bad_Opcode },
9360     { Bad_Opcode },
9361     { Bad_Opcode },
9362     { Bad_Opcode },
9363     /* 88 */
9364     { Bad_Opcode },
9365     { Bad_Opcode },
9366     { Bad_Opcode },
9367     { Bad_Opcode },
9368     { Bad_Opcode },
9369     { Bad_Opcode },
9370     { Bad_Opcode },
9371     { Bad_Opcode },
9372     /* 90 */
9373     { Bad_Opcode },
9374     { Bad_Opcode },
9375     { Bad_Opcode },
9376     { Bad_Opcode },
9377     { Bad_Opcode },
9378     { Bad_Opcode },
9379     { Bad_Opcode },
9380     { Bad_Opcode },
9381     /* 98 */
9382     { Bad_Opcode },
9383     { Bad_Opcode },
9384     { Bad_Opcode },
9385     { Bad_Opcode },
9386     { Bad_Opcode },
9387     { Bad_Opcode },
9388     { Bad_Opcode },
9389     { Bad_Opcode },
9390     /* a0 */
9391     { Bad_Opcode },
9392     { Bad_Opcode },
9393     { Bad_Opcode },
9394     { Bad_Opcode },
9395     { Bad_Opcode },
9396     { Bad_Opcode },
9397     { Bad_Opcode },
9398     { Bad_Opcode },
9399     /* a8 */
9400     { Bad_Opcode },
9401     { Bad_Opcode },
9402     { Bad_Opcode },
9403     { Bad_Opcode },
9404     { Bad_Opcode },
9405     { Bad_Opcode },
9406     { Bad_Opcode },
9407     { Bad_Opcode },
9408     /* b0 */
9409     { Bad_Opcode },
9410     { Bad_Opcode },
9411     { Bad_Opcode },
9412     { Bad_Opcode },
9413     { Bad_Opcode },
9414     { Bad_Opcode },
9415     { Bad_Opcode },
9416     { Bad_Opcode },
9417     /* b8 */
9418     { Bad_Opcode },
9419     { Bad_Opcode },
9420     { Bad_Opcode },
9421     { Bad_Opcode },
9422     { Bad_Opcode },
9423     { Bad_Opcode },
9424     { Bad_Opcode },
9425     { Bad_Opcode },
9426     /* c0 */
9427     { Bad_Opcode },
9428     { Bad_Opcode },
9429     { Bad_Opcode },
9430     { Bad_Opcode },
9431     { Bad_Opcode },
9432     { Bad_Opcode },
9433     { Bad_Opcode },
9434     { Bad_Opcode },
9435     /* c8 */
9436     { Bad_Opcode },
9437     { Bad_Opcode },
9438     { Bad_Opcode },
9439     { Bad_Opcode },
9440     { Bad_Opcode },
9441     { Bad_Opcode },
9442     { Bad_Opcode },
9443     { Bad_Opcode },
9444     /* d0 */
9445     { Bad_Opcode },
9446     { Bad_Opcode },
9447     { Bad_Opcode },
9448     { Bad_Opcode },
9449     { Bad_Opcode },
9450     { Bad_Opcode },
9451     { Bad_Opcode },
9452     { Bad_Opcode },
9453     /* d8 */
9454     { Bad_Opcode },
9455     { Bad_Opcode },
9456     { Bad_Opcode },
9457     { Bad_Opcode },
9458     { Bad_Opcode },
9459     { Bad_Opcode },
9460     { Bad_Opcode },
9461     { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9462     /* e0 */
9463     { Bad_Opcode },
9464     { Bad_Opcode },
9465     { Bad_Opcode },
9466     { Bad_Opcode },
9467     { Bad_Opcode },
9468     { Bad_Opcode },
9469     { Bad_Opcode },
9470     { Bad_Opcode },
9471     /* e8 */
9472     { Bad_Opcode },
9473     { Bad_Opcode },
9474     { Bad_Opcode },
9475     { Bad_Opcode },
9476     { Bad_Opcode },
9477     { Bad_Opcode },
9478     { Bad_Opcode },
9479     { Bad_Opcode },
9480     /* f0 */
9481     { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9482     { Bad_Opcode },
9483     { Bad_Opcode },
9484     { Bad_Opcode },
9485     { Bad_Opcode },
9486     { Bad_Opcode },
9487     { Bad_Opcode },
9488     { Bad_Opcode },
9489     /* f8 */
9490     { Bad_Opcode },
9491     { Bad_Opcode },
9492     { Bad_Opcode },
9493     { Bad_Opcode },
9494     { Bad_Opcode },
9495     { Bad_Opcode },
9496     { Bad_Opcode },
9497     { Bad_Opcode },
9498   },
9499 };
9500
9501 #define NEED_OPCODE_TABLE
9502 #include "i386-dis-evex.h"
9503 #undef NEED_OPCODE_TABLE
9504 static const struct dis386 vex_len_table[][2] = {
9505   /* VEX_LEN_0F10_P_1 */
9506   {
9507     { VEX_W_TABLE (VEX_W_0F10_P_1) },
9508     { VEX_W_TABLE (VEX_W_0F10_P_1) },
9509   },
9510
9511   /* VEX_LEN_0F10_P_3 */
9512   {
9513     { VEX_W_TABLE (VEX_W_0F10_P_3) },
9514     { VEX_W_TABLE (VEX_W_0F10_P_3) },
9515   },
9516
9517   /* VEX_LEN_0F11_P_1 */
9518   {
9519     { VEX_W_TABLE (VEX_W_0F11_P_1) },
9520     { VEX_W_TABLE (VEX_W_0F11_P_1) },
9521   },
9522
9523   /* VEX_LEN_0F11_P_3 */
9524   {
9525     { VEX_W_TABLE (VEX_W_0F11_P_3) },
9526     { VEX_W_TABLE (VEX_W_0F11_P_3) },
9527   },
9528
9529   /* VEX_LEN_0F12_P_0_M_0 */
9530   {
9531     { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) },
9532   },
9533
9534   /* VEX_LEN_0F12_P_0_M_1 */
9535   {
9536     { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) },
9537   },
9538
9539   /* VEX_LEN_0F12_P_2 */
9540   {
9541     { VEX_W_TABLE (VEX_W_0F12_P_2) },
9542   },
9543
9544   /* VEX_LEN_0F13_M_0 */
9545   {
9546     { VEX_W_TABLE (VEX_W_0F13_M_0) },
9547   },
9548
9549   /* VEX_LEN_0F16_P_0_M_0 */
9550   {
9551     { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) },
9552   },
9553
9554   /* VEX_LEN_0F16_P_0_M_1 */
9555   {
9556     { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) },
9557   },
9558
9559   /* VEX_LEN_0F16_P_2 */
9560   {
9561     { VEX_W_TABLE (VEX_W_0F16_P_2) },
9562   },
9563
9564   /* VEX_LEN_0F17_M_0 */
9565   {
9566     { VEX_W_TABLE (VEX_W_0F17_M_0) },
9567   },
9568
9569   /* VEX_LEN_0F2A_P_1 */
9570   {
9571     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9572     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9573   },
9574
9575   /* VEX_LEN_0F2A_P_3 */
9576   {
9577     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9578     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9579   },
9580
9581   /* VEX_LEN_0F2C_P_1 */
9582   {
9583     { "vcvttss2siY",    { Gv, EXdScalar }, 0 },
9584     { "vcvttss2siY",    { Gv, EXdScalar }, 0 },
9585   },
9586
9587   /* VEX_LEN_0F2C_P_3 */
9588   {
9589     { "vcvttsd2siY",    { Gv, EXqScalar }, 0 },
9590     { "vcvttsd2siY",    { Gv, EXqScalar }, 0 },
9591   },
9592
9593   /* VEX_LEN_0F2D_P_1 */
9594   {
9595     { "vcvtss2siY",     { Gv, EXdScalar }, 0 },
9596     { "vcvtss2siY",     { Gv, EXdScalar }, 0 },
9597   },
9598
9599   /* VEX_LEN_0F2D_P_3 */
9600   {
9601     { "vcvtsd2siY",     { Gv, EXqScalar }, 0 },
9602     { "vcvtsd2siY",     { Gv, EXqScalar }, 0 },
9603   },
9604
9605   /* VEX_LEN_0F2E_P_0 */
9606   {
9607     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9608     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9609   },
9610
9611   /* VEX_LEN_0F2E_P_2 */
9612   {
9613     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9614     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9615   },
9616
9617   /* VEX_LEN_0F2F_P_0 */
9618   {
9619     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9620     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9621   },
9622
9623   /* VEX_LEN_0F2F_P_2 */
9624   {
9625     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9626     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9627   },
9628
9629   /* VEX_LEN_0F41_P_0 */
9630   {
9631     { Bad_Opcode },
9632     { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9633   },
9634   /* VEX_LEN_0F41_P_2 */
9635   {
9636     { Bad_Opcode },
9637     { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9638   },
9639   /* VEX_LEN_0F42_P_0 */
9640   {
9641     { Bad_Opcode },
9642     { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9643   },
9644   /* VEX_LEN_0F42_P_2 */
9645   {
9646     { Bad_Opcode },
9647     { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9648   },
9649   /* VEX_LEN_0F44_P_0 */
9650   {
9651     { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9652   },
9653   /* VEX_LEN_0F44_P_2 */
9654   {
9655     { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9656   },
9657   /* VEX_LEN_0F45_P_0 */
9658   {
9659     { Bad_Opcode },
9660     { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9661   },
9662   /* VEX_LEN_0F45_P_2 */
9663   {
9664     { Bad_Opcode },
9665     { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9666   },
9667   /* VEX_LEN_0F46_P_0 */
9668   {
9669     { Bad_Opcode },
9670     { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9671   },
9672   /* VEX_LEN_0F46_P_2 */
9673   {
9674     { Bad_Opcode },
9675     { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9676   },
9677   /* VEX_LEN_0F47_P_0 */
9678   {
9679     { Bad_Opcode },
9680     { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9681   },
9682   /* VEX_LEN_0F47_P_2 */
9683   {
9684     { Bad_Opcode },
9685     { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9686   },
9687   /* VEX_LEN_0F4A_P_0 */
9688   {
9689     { Bad_Opcode },
9690     { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9691   },
9692   /* VEX_LEN_0F4A_P_2 */
9693   {
9694     { Bad_Opcode },
9695     { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9696   },
9697   /* VEX_LEN_0F4B_P_0 */
9698   {
9699     { Bad_Opcode },
9700     { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9701   },
9702   /* VEX_LEN_0F4B_P_2 */
9703   {
9704     { Bad_Opcode },
9705     { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9706   },
9707
9708   /* VEX_LEN_0F51_P_1 */
9709   {
9710     { VEX_W_TABLE (VEX_W_0F51_P_1) },
9711     { VEX_W_TABLE (VEX_W_0F51_P_1) },
9712   },
9713
9714   /* VEX_LEN_0F51_P_3 */
9715   {
9716     { VEX_W_TABLE (VEX_W_0F51_P_3) },
9717     { VEX_W_TABLE (VEX_W_0F51_P_3) },
9718   },
9719
9720   /* VEX_LEN_0F52_P_1 */
9721   {
9722     { VEX_W_TABLE (VEX_W_0F52_P_1) },
9723     { VEX_W_TABLE (VEX_W_0F52_P_1) },
9724   },
9725
9726   /* VEX_LEN_0F53_P_1 */
9727   {
9728     { VEX_W_TABLE (VEX_W_0F53_P_1) },
9729     { VEX_W_TABLE (VEX_W_0F53_P_1) },
9730   },
9731
9732   /* VEX_LEN_0F58_P_1 */
9733   {
9734     { VEX_W_TABLE (VEX_W_0F58_P_1) },
9735     { VEX_W_TABLE (VEX_W_0F58_P_1) },
9736   },
9737
9738   /* VEX_LEN_0F58_P_3 */
9739   {
9740     { VEX_W_TABLE (VEX_W_0F58_P_3) },
9741     { VEX_W_TABLE (VEX_W_0F58_P_3) },
9742   },
9743
9744   /* VEX_LEN_0F59_P_1 */
9745   {
9746     { VEX_W_TABLE (VEX_W_0F59_P_1) },
9747     { VEX_W_TABLE (VEX_W_0F59_P_1) },
9748   },
9749
9750   /* VEX_LEN_0F59_P_3 */
9751   {
9752     { VEX_W_TABLE (VEX_W_0F59_P_3) },
9753     { VEX_W_TABLE (VEX_W_0F59_P_3) },
9754   },
9755
9756   /* VEX_LEN_0F5A_P_1 */
9757   {
9758     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9759     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9760   },
9761
9762   /* VEX_LEN_0F5A_P_3 */
9763   {
9764     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9765     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9766   },
9767
9768   /* VEX_LEN_0F5C_P_1 */
9769   {
9770     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9771     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9772   },
9773
9774   /* VEX_LEN_0F5C_P_3 */
9775   {
9776     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9777     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9778   },
9779
9780   /* VEX_LEN_0F5D_P_1 */
9781   {
9782     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9783     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9784   },
9785
9786   /* VEX_LEN_0F5D_P_3 */
9787   {
9788     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9789     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9790   },
9791
9792   /* VEX_LEN_0F5E_P_1 */
9793   {
9794     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9795     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9796   },
9797
9798   /* VEX_LEN_0F5E_P_3 */
9799   {
9800     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9801     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9802   },
9803
9804   /* VEX_LEN_0F5F_P_1 */
9805   {
9806     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9807     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9808   },
9809
9810   /* VEX_LEN_0F5F_P_3 */
9811   {
9812     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9813     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9814   },
9815
9816   /* VEX_LEN_0F6E_P_2 */
9817   {
9818     { "vmovK",          { XMScalar, Edq }, 0 },
9819     { "vmovK",          { XMScalar, Edq }, 0 },
9820   },
9821
9822   /* VEX_LEN_0F7E_P_1 */
9823   {
9824     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9825     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9826   },
9827
9828   /* VEX_LEN_0F7E_P_2 */
9829   {
9830     { "vmovK",          { Edq, XMScalar }, 0 },
9831     { "vmovK",          { Edq, XMScalar }, 0 },
9832   },
9833
9834   /* VEX_LEN_0F90_P_0 */
9835   {
9836     { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9837   },
9838
9839   /* VEX_LEN_0F90_P_2 */
9840   {
9841     { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9842   },
9843
9844   /* VEX_LEN_0F91_P_0 */
9845   {
9846     { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9847   },
9848
9849   /* VEX_LEN_0F91_P_2 */
9850   {
9851     { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
9852   },
9853
9854   /* VEX_LEN_0F92_P_0 */
9855   {
9856     { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9857   },
9858
9859   /* VEX_LEN_0F92_P_2 */
9860   {
9861     { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
9862   },
9863
9864   /* VEX_LEN_0F92_P_3 */
9865   {
9866     { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0) },
9867   },
9868
9869   /* VEX_LEN_0F93_P_0 */
9870   {
9871     { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9872   },
9873
9874   /* VEX_LEN_0F93_P_2 */
9875   {
9876     { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
9877   },
9878
9879   /* VEX_LEN_0F93_P_3 */
9880   {
9881     { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0) },
9882   },
9883
9884   /* VEX_LEN_0F98_P_0 */
9885   {
9886     { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9887   },
9888
9889   /* VEX_LEN_0F98_P_2 */
9890   {
9891     { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
9892   },
9893
9894   /* VEX_LEN_0F99_P_0 */
9895   {
9896     { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
9897   },
9898
9899   /* VEX_LEN_0F99_P_2 */
9900   {
9901     { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
9902   },
9903
9904   /* VEX_LEN_0FAE_R_2_M_0 */
9905   {
9906     { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) },
9907   },
9908
9909   /* VEX_LEN_0FAE_R_3_M_0 */
9910   {
9911     { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) },
9912   },
9913
9914   /* VEX_LEN_0FC2_P_1 */
9915   {
9916     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9917     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9918   },
9919
9920   /* VEX_LEN_0FC2_P_3 */
9921   {
9922     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9923     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9924   },
9925
9926   /* VEX_LEN_0FC4_P_2 */
9927   {
9928     { VEX_W_TABLE (VEX_W_0FC4_P_2) },
9929   },
9930
9931   /* VEX_LEN_0FC5_P_2 */
9932   {
9933     { VEX_W_TABLE (VEX_W_0FC5_P_2) },
9934   },
9935
9936   /* VEX_LEN_0FD6_P_2 */
9937   {
9938     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9939     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9940   },
9941
9942   /* VEX_LEN_0FF7_P_2 */
9943   {
9944     { VEX_W_TABLE (VEX_W_0FF7_P_2) },
9945   },
9946
9947   /* VEX_LEN_0F3816_P_2 */
9948   {
9949     { Bad_Opcode },
9950     { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9951   },
9952
9953   /* VEX_LEN_0F3819_P_2 */
9954   {
9955     { Bad_Opcode },
9956     { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9957   },
9958
9959   /* VEX_LEN_0F381A_P_2_M_0 */
9960   {
9961     { Bad_Opcode },
9962     { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9963   },
9964
9965   /* VEX_LEN_0F3836_P_2 */
9966   {
9967     { Bad_Opcode },
9968     { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9969   },
9970
9971   /* VEX_LEN_0F3841_P_2 */
9972   {
9973     { VEX_W_TABLE (VEX_W_0F3841_P_2) },
9974   },
9975
9976   /* VEX_LEN_0F385A_P_2_M_0 */
9977   {
9978     { Bad_Opcode },
9979     { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
9980   },
9981
9982   /* VEX_LEN_0F38DB_P_2 */
9983   {
9984     { VEX_W_TABLE (VEX_W_0F38DB_P_2) },
9985   },
9986
9987   /* VEX_LEN_0F38DC_P_2 */
9988   {
9989     { VEX_W_TABLE (VEX_W_0F38DC_P_2) },
9990   },
9991
9992   /* VEX_LEN_0F38DD_P_2 */
9993   {
9994     { VEX_W_TABLE (VEX_W_0F38DD_P_2) },
9995   },
9996
9997   /* VEX_LEN_0F38DE_P_2 */
9998   {
9999     { VEX_W_TABLE (VEX_W_0F38DE_P_2) },
10000   },
10001
10002   /* VEX_LEN_0F38DF_P_2 */
10003   {
10004     { VEX_W_TABLE (VEX_W_0F38DF_P_2) },
10005   },
10006
10007   /* VEX_LEN_0F38F2_P_0 */
10008   {
10009     { "andnS",          { Gdq, VexGdq, Edq }, 0 },
10010   },
10011
10012   /* VEX_LEN_0F38F3_R_1_P_0 */
10013   {
10014     { "blsrS",          { VexGdq, Edq }, 0 },
10015   },
10016
10017   /* VEX_LEN_0F38F3_R_2_P_0 */
10018   {
10019     { "blsmskS",        { VexGdq, Edq }, 0 },
10020   },
10021
10022   /* VEX_LEN_0F38F3_R_3_P_0 */
10023   {
10024     { "blsiS",          { VexGdq, Edq }, 0 },
10025   },
10026
10027   /* VEX_LEN_0F38F5_P_0 */
10028   {
10029     { "bzhiS",          { Gdq, Edq, VexGdq }, 0 },
10030   },
10031
10032   /* VEX_LEN_0F38F5_P_1 */
10033   {
10034     { "pextS",          { Gdq, VexGdq, Edq }, 0 },
10035   },
10036
10037   /* VEX_LEN_0F38F5_P_3 */
10038   {
10039     { "pdepS",          { Gdq, VexGdq, Edq }, 0 },
10040   },
10041
10042   /* VEX_LEN_0F38F6_P_3 */
10043   {
10044     { "mulxS",          { Gdq, VexGdq, Edq }, 0 },
10045   },
10046
10047   /* VEX_LEN_0F38F7_P_0 */
10048   {
10049     { "bextrS",         { Gdq, Edq, VexGdq }, 0 },
10050   },
10051
10052   /* VEX_LEN_0F38F7_P_1 */
10053   {
10054     { "sarxS",          { Gdq, Edq, VexGdq }, 0 },
10055   },
10056
10057   /* VEX_LEN_0F38F7_P_2 */
10058   {
10059     { "shlxS",          { Gdq, Edq, VexGdq }, 0 },
10060   },
10061
10062   /* VEX_LEN_0F38F7_P_3 */
10063   {
10064     { "shrxS",          { Gdq, Edq, VexGdq }, 0 },
10065   },
10066
10067   /* VEX_LEN_0F3A00_P_2 */
10068   {
10069     { Bad_Opcode },
10070     { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
10071   },
10072
10073   /* VEX_LEN_0F3A01_P_2 */
10074   {
10075     { Bad_Opcode },
10076     { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
10077   },
10078
10079   /* VEX_LEN_0F3A06_P_2 */
10080   {
10081     { Bad_Opcode },
10082     { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
10083   },
10084
10085   /* VEX_LEN_0F3A0A_P_2 */
10086   {
10087     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
10088     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
10089   },
10090
10091   /* VEX_LEN_0F3A0B_P_2 */
10092   {
10093     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
10094     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
10095   },
10096
10097   /* VEX_LEN_0F3A14_P_2 */
10098   {
10099     { VEX_W_TABLE (VEX_W_0F3A14_P_2) },
10100   },
10101
10102   /* VEX_LEN_0F3A15_P_2 */
10103   {
10104     { VEX_W_TABLE (VEX_W_0F3A15_P_2) },
10105   },
10106
10107   /* VEX_LEN_0F3A16_P_2  */
10108   {
10109     { "vpextrK",        { Edq, XM, Ib }, 0 },
10110   },
10111
10112   /* VEX_LEN_0F3A17_P_2 */
10113   {
10114     { "vextractps",     { Edqd, XM, Ib }, 0 },
10115   },
10116
10117   /* VEX_LEN_0F3A18_P_2 */
10118   {
10119     { Bad_Opcode },
10120     { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
10121   },
10122
10123   /* VEX_LEN_0F3A19_P_2 */
10124   {
10125     { Bad_Opcode },
10126     { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
10127   },
10128
10129   /* VEX_LEN_0F3A20_P_2 */
10130   {
10131     { VEX_W_TABLE (VEX_W_0F3A20_P_2) },
10132   },
10133
10134   /* VEX_LEN_0F3A21_P_2 */
10135   {
10136     { VEX_W_TABLE (VEX_W_0F3A21_P_2) },
10137   },
10138
10139   /* VEX_LEN_0F3A22_P_2 */
10140   {
10141     { "vpinsrK",        { XM, Vex128, Edq, Ib }, 0 },
10142   },
10143
10144   /* VEX_LEN_0F3A30_P_2 */
10145   {
10146     { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
10147   },
10148
10149   /* VEX_LEN_0F3A31_P_2 */
10150   {
10151     { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
10152   },
10153
10154   /* VEX_LEN_0F3A32_P_2 */
10155   {
10156     { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
10157   },
10158
10159   /* VEX_LEN_0F3A33_P_2 */
10160   {
10161     { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
10162   },
10163
10164   /* VEX_LEN_0F3A38_P_2 */
10165   {
10166     { Bad_Opcode },
10167     { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
10168   },
10169
10170   /* VEX_LEN_0F3A39_P_2 */
10171   {
10172     { Bad_Opcode },
10173     { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
10174   },
10175
10176   /* VEX_LEN_0F3A41_P_2 */
10177   {
10178     { VEX_W_TABLE (VEX_W_0F3A41_P_2) },
10179   },
10180
10181   /* VEX_LEN_0F3A44_P_2 */
10182   {
10183     { VEX_W_TABLE (VEX_W_0F3A44_P_2) },
10184   },
10185
10186   /* VEX_LEN_0F3A46_P_2 */
10187   {
10188     { Bad_Opcode },
10189     { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
10190   },
10191
10192   /* VEX_LEN_0F3A60_P_2 */
10193   {
10194     { VEX_W_TABLE (VEX_W_0F3A60_P_2) },
10195   },
10196
10197   /* VEX_LEN_0F3A61_P_2 */
10198   {
10199     { VEX_W_TABLE (VEX_W_0F3A61_P_2) },
10200   },
10201
10202   /* VEX_LEN_0F3A62_P_2 */
10203   {
10204     { VEX_W_TABLE (VEX_W_0F3A62_P_2) },
10205   },
10206
10207   /* VEX_LEN_0F3A63_P_2 */
10208   {
10209     { VEX_W_TABLE (VEX_W_0F3A63_P_2) },
10210   },
10211
10212   /* VEX_LEN_0F3A6A_P_2 */
10213   {
10214     { "vfmaddss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10215   },
10216
10217   /* VEX_LEN_0F3A6B_P_2 */
10218   {
10219     { "vfmaddsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10220   },
10221
10222   /* VEX_LEN_0F3A6E_P_2 */
10223   {
10224     { "vfmsubss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10225   },
10226
10227   /* VEX_LEN_0F3A6F_P_2 */
10228   {
10229     { "vfmsubsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10230   },
10231
10232   /* VEX_LEN_0F3A7A_P_2 */
10233   {
10234     { "vfnmaddss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10235   },
10236
10237   /* VEX_LEN_0F3A7B_P_2 */
10238   {
10239     { "vfnmaddsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10240   },
10241
10242   /* VEX_LEN_0F3A7E_P_2 */
10243   {
10244     { "vfnmsubss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10245   },
10246
10247   /* VEX_LEN_0F3A7F_P_2 */
10248   {
10249     { "vfnmsubsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10250   },
10251
10252   /* VEX_LEN_0F3ADF_P_2 */
10253   {
10254     { VEX_W_TABLE (VEX_W_0F3ADF_P_2) },
10255   },
10256
10257   /* VEX_LEN_0F3AF0_P_3 */
10258   {
10259     { "rorxS",          { Gdq, Edq, Ib }, 0 },
10260   },
10261
10262   /* VEX_LEN_0FXOP_08_CC */
10263   {
10264      { "vpcomb",        { XM, Vex128, EXx, Ib }, 0 },
10265   },
10266
10267   /* VEX_LEN_0FXOP_08_CD */
10268   {
10269      { "vpcomw",        { XM, Vex128, EXx, Ib }, 0 },
10270   },
10271
10272   /* VEX_LEN_0FXOP_08_CE */
10273   {
10274      { "vpcomd",        { XM, Vex128, EXx, Ib }, 0 },
10275   },
10276
10277   /* VEX_LEN_0FXOP_08_CF */
10278   {
10279      { "vpcomq",        { XM, Vex128, EXx, Ib }, 0 },
10280   },
10281
10282   /* VEX_LEN_0FXOP_08_EC */
10283   {
10284      { "vpcomub",       { XM, Vex128, EXx, Ib }, 0 },
10285   },
10286
10287   /* VEX_LEN_0FXOP_08_ED */
10288   {
10289      { "vpcomuw",       { XM, Vex128, EXx, Ib }, 0 },
10290   },
10291
10292   /* VEX_LEN_0FXOP_08_EE */
10293   {
10294      { "vpcomud",       { XM, Vex128, EXx, Ib }, 0 },
10295   },
10296
10297   /* VEX_LEN_0FXOP_08_EF */
10298   {
10299      { "vpcomuq",       { XM, Vex128, EXx, Ib }, 0 },
10300   },
10301
10302   /* VEX_LEN_0FXOP_09_80 */
10303   {
10304     { "vfrczps",        { XM, EXxmm }, 0 },
10305     { "vfrczps",        { XM, EXymmq }, 0 },
10306   },
10307
10308   /* VEX_LEN_0FXOP_09_81 */
10309   {
10310     { "vfrczpd",        { XM, EXxmm }, 0 },
10311     { "vfrczpd",        { XM, EXymmq }, 0 },
10312   },
10313 };
10314
10315 static const struct dis386 vex_w_table[][2] = {
10316   {
10317     /* VEX_W_0F10_P_0 */
10318     { "vmovups",        { XM, EXx }, 0 },
10319   },
10320   {
10321     /* VEX_W_0F10_P_1 */
10322     { "vmovss",         { XMVexScalar, VexScalar, EXdScalar }, 0 },
10323   },
10324   {
10325     /* VEX_W_0F10_P_2 */
10326     { "vmovupd",        { XM, EXx }, 0 },
10327   },
10328   {
10329     /* VEX_W_0F10_P_3 */
10330     { "vmovsd",         { XMVexScalar, VexScalar, EXqScalar }, 0 },
10331   },
10332   {
10333     /* VEX_W_0F11_P_0 */
10334     { "vmovups",        { EXxS, XM }, 0 },
10335   },
10336   {
10337     /* VEX_W_0F11_P_1 */
10338     { "vmovss",         { EXdVexScalarS, VexScalar, XMScalar }, 0 },
10339   },
10340   {
10341     /* VEX_W_0F11_P_2 */
10342     { "vmovupd",        { EXxS, XM }, 0 },
10343   },
10344   {
10345     /* VEX_W_0F11_P_3 */
10346     { "vmovsd",         { EXqVexScalarS, VexScalar, XMScalar }, 0 },
10347   },
10348   {
10349     /* VEX_W_0F12_P_0_M_0 */
10350     { "vmovlps",        { XM, Vex128, EXq }, 0 },
10351   },
10352   {
10353     /* VEX_W_0F12_P_0_M_1 */
10354     { "vmovhlps",       { XM, Vex128, EXq }, 0 },
10355   },
10356   {
10357     /* VEX_W_0F12_P_1 */
10358     { "vmovsldup",      { XM, EXx }, 0 },
10359   },
10360   {
10361     /* VEX_W_0F12_P_2 */
10362     { "vmovlpd",        { XM, Vex128, EXq }, 0 },
10363   },
10364   {
10365     /* VEX_W_0F12_P_3 */
10366     { "vmovddup",       { XM, EXymmq }, 0 },
10367   },
10368   {
10369     /* VEX_W_0F13_M_0 */
10370     { "vmovlpX",        { EXq, XM }, 0 },
10371   },
10372   {
10373     /* VEX_W_0F14 */
10374     { "vunpcklpX",      { XM, Vex, EXx }, 0 },
10375   },
10376   {
10377     /* VEX_W_0F15 */
10378     { "vunpckhpX",      { XM, Vex, EXx }, 0 },
10379   },
10380   {
10381     /* VEX_W_0F16_P_0_M_0 */
10382     { "vmovhps",        { XM, Vex128, EXq }, 0 },
10383   },
10384   {
10385     /* VEX_W_0F16_P_0_M_1 */
10386     { "vmovlhps",       { XM, Vex128, EXq }, 0 },
10387   },
10388   {
10389     /* VEX_W_0F16_P_1 */
10390     { "vmovshdup",      { XM, EXx }, 0 },
10391   },
10392   {
10393     /* VEX_W_0F16_P_2 */
10394     { "vmovhpd",        { XM, Vex128, EXq }, 0 },
10395   },
10396   {
10397     /* VEX_W_0F17_M_0 */
10398     { "vmovhpX",        { EXq, XM }, 0 },
10399   },
10400   {
10401     /* VEX_W_0F28 */
10402     { "vmovapX",        { XM, EXx }, 0 },
10403   },
10404   {
10405     /* VEX_W_0F29 */
10406     { "vmovapX",        { EXxS, XM }, 0 },
10407   },
10408   {
10409     /* VEX_W_0F2B_M_0 */
10410     { "vmovntpX",       { Mx, XM }, 0 },
10411   },
10412   {
10413     /* VEX_W_0F2E_P_0 */
10414     { "vucomiss",       { XMScalar, EXdScalar }, 0 },
10415   },
10416   {
10417     /* VEX_W_0F2E_P_2 */
10418     { "vucomisd",       { XMScalar, EXqScalar }, 0 },
10419   },
10420   {
10421     /* VEX_W_0F2F_P_0 */
10422     { "vcomiss",        { XMScalar, EXdScalar }, 0 },
10423   },
10424   {
10425     /* VEX_W_0F2F_P_2 */
10426     { "vcomisd",        { XMScalar, EXqScalar }, 0 },
10427   },
10428   {
10429     /* VEX_W_0F41_P_0_LEN_1 */
10430     { "kandw",          { MaskG, MaskVex, MaskR }, 0 },
10431     { "kandq",          { MaskG, MaskVex, MaskR }, 0 },
10432   },
10433   {
10434     /* VEX_W_0F41_P_2_LEN_1 */
10435     { "kandb",          { MaskG, MaskVex, MaskR }, 0 },
10436     { "kandd",          { MaskG, MaskVex, MaskR }, 0 },
10437   },
10438   {
10439     /* VEX_W_0F42_P_0_LEN_1 */
10440     { "kandnw",         { MaskG, MaskVex, MaskR }, 0 },
10441     { "kandnq",         { MaskG, MaskVex, MaskR }, 0 },
10442   },
10443   {
10444     /* VEX_W_0F42_P_2_LEN_1 */
10445     { "kandnb",         { MaskG, MaskVex, MaskR }, 0 },
10446     { "kandnd",         { MaskG, MaskVex, MaskR }, 0 },
10447   },
10448   {
10449     /* VEX_W_0F44_P_0_LEN_0 */
10450     { "knotw",          { MaskG, MaskR }, 0 },
10451     { "knotq",          { MaskG, MaskR }, 0 },
10452   },
10453   {
10454     /* VEX_W_0F44_P_2_LEN_0 */
10455     { "knotb",          { MaskG, MaskR }, 0 },
10456     { "knotd",          { MaskG, MaskR }, 0 },
10457   },
10458   {
10459     /* VEX_W_0F45_P_0_LEN_1 */
10460     { "korw",           { MaskG, MaskVex, MaskR }, 0 },
10461     { "korq",           { MaskG, MaskVex, MaskR }, 0 },
10462   },
10463   {
10464     /* VEX_W_0F45_P_2_LEN_1 */
10465     { "korb",           { MaskG, MaskVex, MaskR }, 0 },
10466     { "kord",           { MaskG, MaskVex, MaskR }, 0 },
10467   },
10468   {
10469     /* VEX_W_0F46_P_0_LEN_1 */
10470     { "kxnorw",         { MaskG, MaskVex, MaskR }, 0 },
10471     { "kxnorq",         { MaskG, MaskVex, MaskR }, 0 },
10472   },
10473   {
10474     /* VEX_W_0F46_P_2_LEN_1 */
10475     { "kxnorb",         { MaskG, MaskVex, MaskR }, 0 },
10476     { "kxnord",         { MaskG, MaskVex, MaskR }, 0 },
10477   },
10478   {
10479     /* VEX_W_0F47_P_0_LEN_1 */
10480     { "kxorw",          { MaskG, MaskVex, MaskR }, 0 },
10481     { "kxorq",          { MaskG, MaskVex, MaskR }, 0 },
10482   },
10483   {
10484     /* VEX_W_0F47_P_2_LEN_1 */
10485     { "kxorb",          { MaskG, MaskVex, MaskR }, 0 },
10486     { "kxord",          { MaskG, MaskVex, MaskR }, 0 },
10487   },
10488   {
10489     /* VEX_W_0F4A_P_0_LEN_1 */
10490     { "kaddw",          { MaskG, MaskVex, MaskR }, 0 },
10491     { "kaddq",          { MaskG, MaskVex, MaskR }, 0 },
10492   },
10493   {
10494     /* VEX_W_0F4A_P_2_LEN_1 */
10495     { "kaddb",          { MaskG, MaskVex, MaskR }, 0 },
10496     { "kaddd",          { MaskG, MaskVex, MaskR }, 0 },
10497   },
10498   {
10499     /* VEX_W_0F4B_P_0_LEN_1 */
10500     { "kunpckwd",       { MaskG, MaskVex, MaskR }, 0 },
10501     { "kunpckdq",       { MaskG, MaskVex, MaskR }, 0 },
10502   },
10503   {
10504     /* VEX_W_0F4B_P_2_LEN_1 */
10505     { "kunpckbw",       { MaskG, MaskVex, MaskR }, 0 },
10506   },
10507   {
10508     /* VEX_W_0F50_M_0 */
10509     { "vmovmskpX",      { Gdq, XS }, 0 },
10510   },
10511   {
10512     /* VEX_W_0F51_P_0 */
10513     { "vsqrtps",        { XM, EXx }, 0 },
10514   },
10515   {
10516     /* VEX_W_0F51_P_1 */
10517     { "vsqrtss",        { XMScalar, VexScalar, EXdScalar }, 0 },
10518   },
10519   {
10520     /* VEX_W_0F51_P_2  */
10521     { "vsqrtpd",        { XM, EXx }, 0 },
10522   },
10523   {
10524     /* VEX_W_0F51_P_3 */
10525     { "vsqrtsd",        { XMScalar, VexScalar, EXqScalar }, 0 },
10526   },
10527   {
10528     /* VEX_W_0F52_P_0 */
10529     { "vrsqrtps",       { XM, EXx }, 0 },
10530   },
10531   {
10532     /* VEX_W_0F52_P_1 */
10533     { "vrsqrtss",       { XMScalar, VexScalar, EXdScalar }, 0 },
10534   },
10535   {
10536     /* VEX_W_0F53_P_0  */
10537     { "vrcpps",         { XM, EXx }, 0 },
10538   },
10539   {
10540     /* VEX_W_0F53_P_1  */
10541     { "vrcpss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10542   },
10543   {
10544     /* VEX_W_0F58_P_0  */
10545     { "vaddps",         { XM, Vex, EXx }, 0 },
10546   },
10547   {
10548     /* VEX_W_0F58_P_1  */
10549     { "vaddss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10550   },
10551   {
10552     /* VEX_W_0F58_P_2  */
10553     { "vaddpd",         { XM, Vex, EXx }, 0 },
10554   },
10555   {
10556     /* VEX_W_0F58_P_3  */
10557     { "vaddsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10558   },
10559   {
10560     /* VEX_W_0F59_P_0  */
10561     { "vmulps",         { XM, Vex, EXx }, 0 },
10562   },
10563   {
10564     /* VEX_W_0F59_P_1  */
10565     { "vmulss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10566   },
10567   {
10568     /* VEX_W_0F59_P_2  */
10569     { "vmulpd",         { XM, Vex, EXx }, 0 },
10570   },
10571   {
10572     /* VEX_W_0F59_P_3  */
10573     { "vmulsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10574   },
10575   {
10576     /* VEX_W_0F5A_P_0  */
10577     { "vcvtps2pd",      { XM, EXxmmq }, 0 },
10578   },
10579   {
10580     /* VEX_W_0F5A_P_1  */
10581     { "vcvtss2sd",      { XMScalar, VexScalar, EXdScalar }, 0 },
10582   },
10583   {
10584     /* VEX_W_0F5A_P_3  */
10585     { "vcvtsd2ss",      { XMScalar, VexScalar, EXqScalar }, 0 },
10586   },
10587   {
10588     /* VEX_W_0F5B_P_0  */
10589     { "vcvtdq2ps",      { XM, EXx }, 0 },
10590   },
10591   {
10592     /* VEX_W_0F5B_P_1  */
10593     { "vcvttps2dq",     { XM, EXx }, 0 },
10594   },
10595   {
10596     /* VEX_W_0F5B_P_2  */
10597     { "vcvtps2dq",      { XM, EXx }, 0 },
10598   },
10599   {
10600     /* VEX_W_0F5C_P_0  */
10601     { "vsubps",         { XM, Vex, EXx }, 0 },
10602   },
10603   {
10604     /* VEX_W_0F5C_P_1  */
10605     { "vsubss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10606   },
10607   {
10608     /* VEX_W_0F5C_P_2  */
10609     { "vsubpd",         { XM, Vex, EXx }, 0 },
10610   },
10611   {
10612     /* VEX_W_0F5C_P_3  */
10613     { "vsubsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10614   },
10615   {
10616     /* VEX_W_0F5D_P_0  */
10617     { "vminps",         { XM, Vex, EXx }, 0 },
10618   },
10619   {
10620     /* VEX_W_0F5D_P_1  */
10621     { "vminss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10622   },
10623   {
10624     /* VEX_W_0F5D_P_2  */
10625     { "vminpd",         { XM, Vex, EXx }, 0 },
10626   },
10627   {
10628     /* VEX_W_0F5D_P_3  */
10629     { "vminsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10630   },
10631   {
10632     /* VEX_W_0F5E_P_0  */
10633     { "vdivps",         { XM, Vex, EXx }, 0 },
10634   },
10635   {
10636     /* VEX_W_0F5E_P_1  */
10637     { "vdivss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10638   },
10639   {
10640     /* VEX_W_0F5E_P_2  */
10641     { "vdivpd",         { XM, Vex, EXx }, 0 },
10642   },
10643   {
10644     /* VEX_W_0F5E_P_3  */
10645     { "vdivsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10646   },
10647   {
10648     /* VEX_W_0F5F_P_0  */
10649     { "vmaxps",         { XM, Vex, EXx }, 0 },
10650   },
10651   {
10652     /* VEX_W_0F5F_P_1  */
10653     { "vmaxss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10654   },
10655   {
10656     /* VEX_W_0F5F_P_2  */
10657     { "vmaxpd",         { XM, Vex, EXx }, 0 },
10658   },
10659   {
10660     /* VEX_W_0F5F_P_3  */
10661     { "vmaxsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10662   },
10663   {
10664     /* VEX_W_0F60_P_2  */
10665     { "vpunpcklbw",     { XM, Vex, EXx }, 0 },
10666   },
10667   {
10668     /* VEX_W_0F61_P_2  */
10669     { "vpunpcklwd",     { XM, Vex, EXx }, 0 },
10670   },
10671   {
10672     /* VEX_W_0F62_P_2  */
10673     { "vpunpckldq",     { XM, Vex, EXx }, 0 },
10674   },
10675   {
10676     /* VEX_W_0F63_P_2  */
10677     { "vpacksswb",      { XM, Vex, EXx }, 0 },
10678   },
10679   {
10680     /* VEX_W_0F64_P_2  */
10681     { "vpcmpgtb",       { XM, Vex, EXx }, 0 },
10682   },
10683   {
10684     /* VEX_W_0F65_P_2  */
10685     { "vpcmpgtw",       { XM, Vex, EXx }, 0 },
10686   },
10687   {
10688     /* VEX_W_0F66_P_2  */
10689     { "vpcmpgtd",       { XM, Vex, EXx }, 0 },
10690   },
10691   {
10692     /* VEX_W_0F67_P_2  */
10693     { "vpackuswb",      { XM, Vex, EXx }, 0 },
10694   },
10695   {
10696     /* VEX_W_0F68_P_2  */
10697     { "vpunpckhbw",     { XM, Vex, EXx }, 0 },
10698   },
10699   {
10700     /* VEX_W_0F69_P_2  */
10701     { "vpunpckhwd",     { XM, Vex, EXx }, 0 },
10702   },
10703   {
10704     /* VEX_W_0F6A_P_2  */
10705     { "vpunpckhdq",     { XM, Vex, EXx }, 0 },
10706   },
10707   {
10708     /* VEX_W_0F6B_P_2  */
10709     { "vpackssdw",      { XM, Vex, EXx }, 0 },
10710   },
10711   {
10712     /* VEX_W_0F6C_P_2  */
10713     { "vpunpcklqdq",    { XM, Vex, EXx }, 0 },
10714   },
10715   {
10716     /* VEX_W_0F6D_P_2  */
10717     { "vpunpckhqdq",    { XM, Vex, EXx }, 0 },
10718   },
10719   {
10720     /* VEX_W_0F6F_P_1  */
10721     { "vmovdqu",        { XM, EXx }, 0 },
10722   },
10723   {
10724     /* VEX_W_0F6F_P_2  */
10725     { "vmovdqa",        { XM, EXx }, 0 },
10726   },
10727   {
10728     /* VEX_W_0F70_P_1 */
10729     { "vpshufhw",       { XM, EXx, Ib }, 0 },
10730   },
10731   {
10732     /* VEX_W_0F70_P_2 */
10733     { "vpshufd",        { XM, EXx, Ib }, 0 },
10734   },
10735   {
10736     /* VEX_W_0F70_P_3 */
10737     { "vpshuflw",       { XM, EXx, Ib }, 0 },
10738   },
10739   {
10740     /* VEX_W_0F71_R_2_P_2  */
10741     { "vpsrlw",         { Vex, XS, Ib }, 0 },
10742   },
10743   {
10744     /* VEX_W_0F71_R_4_P_2  */
10745     { "vpsraw",         { Vex, XS, Ib }, 0 },
10746   },
10747   {
10748     /* VEX_W_0F71_R_6_P_2  */
10749     { "vpsllw",         { Vex, XS, Ib }, 0 },
10750   },
10751   {
10752     /* VEX_W_0F72_R_2_P_2  */
10753     { "vpsrld",         { Vex, XS, Ib }, 0 },
10754   },
10755   {
10756     /* VEX_W_0F72_R_4_P_2  */
10757     { "vpsrad",         { Vex, XS, Ib }, 0 },
10758   },
10759   {
10760     /* VEX_W_0F72_R_6_P_2  */
10761     { "vpslld",         { Vex, XS, Ib }, 0 },
10762   },
10763   {
10764     /* VEX_W_0F73_R_2_P_2  */
10765     { "vpsrlq",         { Vex, XS, Ib }, 0 },
10766   },
10767   {
10768     /* VEX_W_0F73_R_3_P_2  */
10769     { "vpsrldq",        { Vex, XS, Ib }, 0 },
10770   },
10771   {
10772     /* VEX_W_0F73_R_6_P_2  */
10773     { "vpsllq",         { Vex, XS, Ib }, 0 },
10774   },
10775   {
10776     /* VEX_W_0F73_R_7_P_2  */
10777     { "vpslldq",        { Vex, XS, Ib }, 0 },
10778   },
10779   {
10780     /* VEX_W_0F74_P_2 */
10781     { "vpcmpeqb",       { XM, Vex, EXx }, 0 },
10782   },
10783   {
10784     /* VEX_W_0F75_P_2 */
10785     { "vpcmpeqw",       { XM, Vex, EXx }, 0 },
10786   },
10787   {
10788     /* VEX_W_0F76_P_2 */
10789     { "vpcmpeqd",       { XM, Vex, EXx }, 0 },
10790   },
10791   {
10792     /* VEX_W_0F77_P_0 */
10793     { "",               { VZERO }, 0 },
10794   },
10795   {
10796     /* VEX_W_0F7C_P_2 */
10797     { "vhaddpd",        { XM, Vex, EXx }, 0 },
10798   },
10799   {
10800     /* VEX_W_0F7C_P_3 */
10801     { "vhaddps",        { XM, Vex, EXx }, 0 },
10802   },
10803   {
10804     /* VEX_W_0F7D_P_2 */
10805     { "vhsubpd",        { XM, Vex, EXx }, 0 },
10806   },
10807   {
10808     /* VEX_W_0F7D_P_3 */
10809     { "vhsubps",        { XM, Vex, EXx }, 0 },
10810   },
10811   {
10812     /* VEX_W_0F7E_P_1 */
10813     { "vmovq",          { XMScalar, EXqScalar }, 0 },
10814   },
10815   {
10816     /* VEX_W_0F7F_P_1 */
10817     { "vmovdqu",        { EXxS, XM }, 0 },
10818   },
10819   {
10820     /* VEX_W_0F7F_P_2 */
10821     { "vmovdqa",        { EXxS, XM }, 0 },
10822   },
10823   {
10824     /* VEX_W_0F90_P_0_LEN_0 */
10825     { "kmovw",          { MaskG, MaskE }, 0 },
10826     { "kmovq",          { MaskG, MaskE }, 0 },
10827   },
10828   {
10829     /* VEX_W_0F90_P_2_LEN_0 */
10830     { "kmovb",          { MaskG, MaskBDE }, 0 },
10831     { "kmovd",          { MaskG, MaskBDE }, 0 },
10832   },
10833   {
10834     /* VEX_W_0F91_P_0_LEN_0 */
10835     { "kmovw",          { Ew, MaskG }, 0 },
10836     { "kmovq",          { Eq, MaskG }, 0 },
10837   },
10838   {
10839     /* VEX_W_0F91_P_2_LEN_0 */
10840     { "kmovb",          { Eb, MaskG }, 0 },
10841     { "kmovd",          { Ed, MaskG }, 0 },
10842   },
10843   {
10844     /* VEX_W_0F92_P_0_LEN_0 */
10845     { "kmovw",          { MaskG, Rdq }, 0 },
10846   },
10847   {
10848     /* VEX_W_0F92_P_2_LEN_0 */
10849     { "kmovb",          { MaskG, Rdq }, 0 },
10850   },
10851   {
10852     /* VEX_W_0F92_P_3_LEN_0 */
10853     { "kmovd",          { MaskG, Rdq }, 0 },
10854     { "kmovq",          { MaskG, Rdq }, 0 },
10855   },
10856   {
10857     /* VEX_W_0F93_P_0_LEN_0 */
10858     { "kmovw",          { Gdq, MaskR }, 0 },
10859   },
10860   {
10861     /* VEX_W_0F93_P_2_LEN_0 */
10862     { "kmovb",          { Gdq, MaskR }, 0 },
10863   },
10864   {
10865     /* VEX_W_0F93_P_3_LEN_0 */
10866     { "kmovd",          { Gdq, MaskR }, 0 },
10867     { "kmovq",          { Gdq, MaskR }, 0 },
10868   },
10869   {
10870     /* VEX_W_0F98_P_0_LEN_0 */
10871     { "kortestw",       { MaskG, MaskR }, 0 },
10872     { "kortestq",       { MaskG, MaskR }, 0 },
10873   },
10874   {
10875     /* VEX_W_0F98_P_2_LEN_0 */
10876     { "kortestb",       { MaskG, MaskR }, 0 },
10877     { "kortestd",       { MaskG, MaskR }, 0 },
10878   },
10879   {
10880     /* VEX_W_0F99_P_0_LEN_0 */
10881     { "ktestw", { MaskG, MaskR }, 0 },
10882     { "ktestq", { MaskG, MaskR }, 0 },
10883   },
10884   {
10885     /* VEX_W_0F99_P_2_LEN_0 */
10886     { "ktestb", { MaskG, MaskR }, 0 },
10887     { "ktestd", { MaskG, MaskR }, 0 },
10888   },
10889   {
10890     /* VEX_W_0FAE_R_2_M_0 */
10891     { "vldmxcsr",       { Md }, 0 },
10892   },
10893   {
10894     /* VEX_W_0FAE_R_3_M_0 */
10895     { "vstmxcsr",       { Md }, 0 },
10896   },
10897   {
10898     /* VEX_W_0FC2_P_0 */
10899     { "vcmpps",         { XM, Vex, EXx, VCMP }, 0 },
10900   },
10901   {
10902     /* VEX_W_0FC2_P_1 */
10903     { "vcmpss",         { XMScalar, VexScalar, EXdScalar, VCMP }, 0 },
10904   },
10905   {
10906     /* VEX_W_0FC2_P_2 */
10907     { "vcmppd",         { XM, Vex, EXx, VCMP }, 0 },
10908   },
10909   {
10910     /* VEX_W_0FC2_P_3 */
10911     { "vcmpsd",         { XMScalar, VexScalar, EXqScalar, VCMP }, 0 },
10912   },
10913   {
10914     /* VEX_W_0FC4_P_2 */
10915     { "vpinsrw",        { XM, Vex128, Edqw, Ib }, 0 },
10916   },
10917   {
10918     /* VEX_W_0FC5_P_2 */
10919     { "vpextrw",        { Gdq, XS, Ib }, 0 },
10920   },
10921   {
10922     /* VEX_W_0FD0_P_2 */
10923     { "vaddsubpd",      { XM, Vex, EXx }, 0 },
10924   },
10925   {
10926     /* VEX_W_0FD0_P_3 */
10927     { "vaddsubps",      { XM, Vex, EXx }, 0 },
10928   },
10929   {
10930     /* VEX_W_0FD1_P_2 */
10931     { "vpsrlw",         { XM, Vex, EXxmm }, 0 },
10932   },
10933   {
10934     /* VEX_W_0FD2_P_2 */
10935     { "vpsrld",         { XM, Vex, EXxmm }, 0 },
10936   },
10937   {
10938     /* VEX_W_0FD3_P_2 */
10939     { "vpsrlq",         { XM, Vex, EXxmm }, 0 },
10940   },
10941   {
10942     /* VEX_W_0FD4_P_2 */
10943     { "vpaddq",         { XM, Vex, EXx }, 0 },
10944   },
10945   {
10946     /* VEX_W_0FD5_P_2 */
10947     { "vpmullw",        { XM, Vex, EXx }, 0 },
10948   },
10949   {
10950     /* VEX_W_0FD6_P_2 */
10951     { "vmovq",          { EXqScalarS, XMScalar }, 0 },
10952   },
10953   {
10954     /* VEX_W_0FD7_P_2_M_1 */
10955     { "vpmovmskb",      { Gdq, XS }, 0 },
10956   },
10957   {
10958     /* VEX_W_0FD8_P_2 */
10959     { "vpsubusb",       { XM, Vex, EXx }, 0 },
10960   },
10961   {
10962     /* VEX_W_0FD9_P_2 */
10963     { "vpsubusw",       { XM, Vex, EXx }, 0 },
10964   },
10965   {
10966     /* VEX_W_0FDA_P_2 */
10967     { "vpminub",        { XM, Vex, EXx }, 0 },
10968   },
10969   {
10970     /* VEX_W_0FDB_P_2 */
10971     { "vpand",          { XM, Vex, EXx }, 0 },
10972   },
10973   {
10974     /* VEX_W_0FDC_P_2 */
10975     { "vpaddusb",       { XM, Vex, EXx }, 0 },
10976   },
10977   {
10978     /* VEX_W_0FDD_P_2 */
10979     { "vpaddusw",       { XM, Vex, EXx }, 0 },
10980   },
10981   {
10982     /* VEX_W_0FDE_P_2 */
10983     { "vpmaxub",        { XM, Vex, EXx }, 0 },
10984   },
10985   {
10986     /* VEX_W_0FDF_P_2 */
10987     { "vpandn",         { XM, Vex, EXx }, 0 },
10988   },
10989   {
10990     /* VEX_W_0FE0_P_2  */
10991     { "vpavgb",         { XM, Vex, EXx }, 0 },
10992   },
10993   {
10994     /* VEX_W_0FE1_P_2  */
10995     { "vpsraw",         { XM, Vex, EXxmm }, 0 },
10996   },
10997   {
10998     /* VEX_W_0FE2_P_2  */
10999     { "vpsrad",         { XM, Vex, EXxmm }, 0 },
11000   },
11001   {
11002     /* VEX_W_0FE3_P_2  */
11003     { "vpavgw",         { XM, Vex, EXx }, 0 },
11004   },
11005   {
11006     /* VEX_W_0FE4_P_2  */
11007     { "vpmulhuw",       { XM, Vex, EXx }, 0 },
11008   },
11009   {
11010     /* VEX_W_0FE5_P_2  */
11011     { "vpmulhw",        { XM, Vex, EXx }, 0 },
11012   },
11013   {
11014     /* VEX_W_0FE6_P_1  */
11015     { "vcvtdq2pd",      { XM, EXxmmq }, 0 },
11016   },
11017   {
11018     /* VEX_W_0FE6_P_2  */
11019     { "vcvttpd2dq%XY",  { XMM, EXx }, 0 },
11020   },
11021   {
11022     /* VEX_W_0FE6_P_3  */
11023     { "vcvtpd2dq%XY",   { XMM, EXx }, 0 },
11024   },
11025   {
11026     /* VEX_W_0FE7_P_2_M_0 */
11027     { "vmovntdq",       { Mx, XM }, 0 },
11028   },
11029   {
11030     /* VEX_W_0FE8_P_2  */
11031     { "vpsubsb",        { XM, Vex, EXx }, 0 },
11032   },
11033   {
11034     /* VEX_W_0FE9_P_2  */
11035     { "vpsubsw",        { XM, Vex, EXx }, 0 },
11036   },
11037   {
11038     /* VEX_W_0FEA_P_2  */
11039     { "vpminsw",        { XM, Vex, EXx }, 0 },
11040   },
11041   {
11042     /* VEX_W_0FEB_P_2  */
11043     { "vpor",           { XM, Vex, EXx }, 0 },
11044   },
11045   {
11046     /* VEX_W_0FEC_P_2  */
11047     { "vpaddsb",        { XM, Vex, EXx }, 0 },
11048   },
11049   {
11050     /* VEX_W_0FED_P_2  */
11051     { "vpaddsw",        { XM, Vex, EXx }, 0 },
11052   },
11053   {
11054     /* VEX_W_0FEE_P_2  */
11055     { "vpmaxsw",        { XM, Vex, EXx }, 0 },
11056   },
11057   {
11058     /* VEX_W_0FEF_P_2  */
11059     { "vpxor",          { XM, Vex, EXx }, 0 },
11060   },
11061   {
11062     /* VEX_W_0FF0_P_3_M_0 */
11063     { "vlddqu",         { XM, M }, 0 },
11064   },
11065   {
11066     /* VEX_W_0FF1_P_2 */
11067     { "vpsllw",         { XM, Vex, EXxmm }, 0 },
11068   },
11069   {
11070     /* VEX_W_0FF2_P_2 */
11071     { "vpslld",         { XM, Vex, EXxmm }, 0 },
11072   },
11073   {
11074     /* VEX_W_0FF3_P_2 */
11075     { "vpsllq",         { XM, Vex, EXxmm }, 0 },
11076   },
11077   {
11078     /* VEX_W_0FF4_P_2 */
11079     { "vpmuludq",       { XM, Vex, EXx }, 0 },
11080   },
11081   {
11082     /* VEX_W_0FF5_P_2 */
11083     { "vpmaddwd",       { XM, Vex, EXx }, 0 },
11084   },
11085   {
11086     /* VEX_W_0FF6_P_2 */
11087     { "vpsadbw",        { XM, Vex, EXx }, 0 },
11088   },
11089   {
11090     /* VEX_W_0FF7_P_2 */
11091     { "vmaskmovdqu",    { XM, XS }, 0 },
11092   },
11093   {
11094     /* VEX_W_0FF8_P_2 */
11095     { "vpsubb",         { XM, Vex, EXx }, 0 },
11096   },
11097   {
11098     /* VEX_W_0FF9_P_2 */
11099     { "vpsubw",         { XM, Vex, EXx }, 0 },
11100   },
11101   {
11102     /* VEX_W_0FFA_P_2 */
11103     { "vpsubd",         { XM, Vex, EXx }, 0 },
11104   },
11105   {
11106     /* VEX_W_0FFB_P_2 */
11107     { "vpsubq",         { XM, Vex, EXx }, 0 },
11108   },
11109   {
11110     /* VEX_W_0FFC_P_2 */
11111     { "vpaddb",         { XM, Vex, EXx }, 0 },
11112   },
11113   {
11114     /* VEX_W_0FFD_P_2 */
11115     { "vpaddw",         { XM, Vex, EXx }, 0 },
11116   },
11117   {
11118     /* VEX_W_0FFE_P_2 */
11119     { "vpaddd",         { XM, Vex, EXx }, 0 },
11120   },
11121   {
11122     /* VEX_W_0F3800_P_2  */
11123     { "vpshufb",        { XM, Vex, EXx }, 0 },
11124   },
11125   {
11126     /* VEX_W_0F3801_P_2  */
11127     { "vphaddw",        { XM, Vex, EXx }, 0 },
11128   },
11129   {
11130     /* VEX_W_0F3802_P_2  */
11131     { "vphaddd",        { XM, Vex, EXx }, 0 },
11132   },
11133   {
11134     /* VEX_W_0F3803_P_2  */
11135     { "vphaddsw",       { XM, Vex, EXx }, 0 },
11136   },
11137   {
11138     /* VEX_W_0F3804_P_2  */
11139     { "vpmaddubsw",     { XM, Vex, EXx }, 0 },
11140   },
11141   {
11142     /* VEX_W_0F3805_P_2  */
11143     { "vphsubw",        { XM, Vex, EXx }, 0 },
11144   },
11145   {
11146     /* VEX_W_0F3806_P_2  */
11147     { "vphsubd",        { XM, Vex, EXx }, 0 },
11148   },
11149   {
11150     /* VEX_W_0F3807_P_2  */
11151     { "vphsubsw",       { XM, Vex, EXx }, 0 },
11152   },
11153   {
11154     /* VEX_W_0F3808_P_2  */
11155     { "vpsignb",        { XM, Vex, EXx }, 0 },
11156   },
11157   {
11158     /* VEX_W_0F3809_P_2  */
11159     { "vpsignw",        { XM, Vex, EXx }, 0 },
11160   },
11161   {
11162     /* VEX_W_0F380A_P_2  */
11163     { "vpsignd",        { XM, Vex, EXx }, 0 },
11164   },
11165   {
11166     /* VEX_W_0F380B_P_2  */
11167     { "vpmulhrsw",      { XM, Vex, EXx }, 0 },
11168   },
11169   {
11170     /* VEX_W_0F380C_P_2  */
11171     { "vpermilps",      { XM, Vex, EXx }, 0 },
11172   },
11173   {
11174     /* VEX_W_0F380D_P_2  */
11175     { "vpermilpd",      { XM, Vex, EXx }, 0 },
11176   },
11177   {
11178     /* VEX_W_0F380E_P_2  */
11179     { "vtestps",        { XM, EXx }, 0 },
11180   },
11181   {
11182     /* VEX_W_0F380F_P_2  */
11183     { "vtestpd",        { XM, EXx }, 0 },
11184   },
11185   {
11186     /* VEX_W_0F3816_P_2  */
11187     { "vpermps",        { XM, Vex, EXx }, 0 },
11188   },
11189   {
11190     /* VEX_W_0F3817_P_2 */
11191     { "vptest",         { XM, EXx }, 0 },
11192   },
11193   {
11194     /* VEX_W_0F3818_P_2 */
11195     { "vbroadcastss",   { XM, EXxmm_md }, 0 },
11196   },
11197   {
11198     /* VEX_W_0F3819_P_2 */
11199     { "vbroadcastsd",   { XM, EXxmm_mq }, 0 },
11200   },
11201   {
11202     /* VEX_W_0F381A_P_2_M_0 */
11203     { "vbroadcastf128", { XM, Mxmm }, 0 },
11204   },
11205   {
11206     /* VEX_W_0F381C_P_2 */
11207     { "vpabsb",         { XM, EXx }, 0 },
11208   },
11209   {
11210     /* VEX_W_0F381D_P_2 */
11211     { "vpabsw",         { XM, EXx }, 0 },
11212   },
11213   {
11214     /* VEX_W_0F381E_P_2 */
11215     { "vpabsd",         { XM, EXx }, 0 },
11216   },
11217   {
11218     /* VEX_W_0F3820_P_2 */
11219     { "vpmovsxbw",      { XM, EXxmmq }, 0 },
11220   },
11221   {
11222     /* VEX_W_0F3821_P_2 */
11223     { "vpmovsxbd",      { XM, EXxmmqd }, 0 },
11224   },
11225   {
11226     /* VEX_W_0F3822_P_2 */
11227     { "vpmovsxbq",      { XM, EXxmmdw }, 0 },
11228   },
11229   {
11230     /* VEX_W_0F3823_P_2 */
11231     { "vpmovsxwd",      { XM, EXxmmq }, 0 },
11232   },
11233   {
11234     /* VEX_W_0F3824_P_2 */
11235     { "vpmovsxwq",      { XM, EXxmmqd }, 0 },
11236   },
11237   {
11238     /* VEX_W_0F3825_P_2 */
11239     { "vpmovsxdq",      { XM, EXxmmq }, 0 },
11240   },
11241   {
11242     /* VEX_W_0F3828_P_2 */
11243     { "vpmuldq",        { XM, Vex, EXx }, 0 },
11244   },
11245   {
11246     /* VEX_W_0F3829_P_2 */
11247     { "vpcmpeqq",       { XM, Vex, EXx }, 0 },
11248   },
11249   {
11250     /* VEX_W_0F382A_P_2_M_0 */
11251     { "vmovntdqa",      { XM, Mx }, 0 },
11252   },
11253   {
11254     /* VEX_W_0F382B_P_2 */
11255     { "vpackusdw",      { XM, Vex, EXx }, 0 },
11256   },
11257   {
11258     /* VEX_W_0F382C_P_2_M_0 */
11259     { "vmaskmovps",     { XM, Vex, Mx }, 0 },
11260   },
11261   {
11262     /* VEX_W_0F382D_P_2_M_0 */
11263     { "vmaskmovpd",     { XM, Vex, Mx }, 0 },
11264   },
11265   {
11266     /* VEX_W_0F382E_P_2_M_0 */
11267     { "vmaskmovps",     { Mx, Vex, XM }, 0 },
11268   },
11269   {
11270     /* VEX_W_0F382F_P_2_M_0 */
11271     { "vmaskmovpd",     { Mx, Vex, XM }, 0 },
11272   },
11273   {
11274     /* VEX_W_0F3830_P_2 */
11275     { "vpmovzxbw",      { XM, EXxmmq }, 0 },
11276   },
11277   {
11278     /* VEX_W_0F3831_P_2 */
11279     { "vpmovzxbd",      { XM, EXxmmqd }, 0 },
11280   },
11281   {
11282     /* VEX_W_0F3832_P_2 */
11283     { "vpmovzxbq",      { XM, EXxmmdw }, 0 },
11284   },
11285   {
11286     /* VEX_W_0F3833_P_2 */
11287     { "vpmovzxwd",      { XM, EXxmmq }, 0 },
11288   },
11289   {
11290     /* VEX_W_0F3834_P_2 */
11291     { "vpmovzxwq",      { XM, EXxmmqd }, 0 },
11292   },
11293   {
11294     /* VEX_W_0F3835_P_2 */
11295     { "vpmovzxdq",      { XM, EXxmmq }, 0 },
11296   },
11297   {
11298     /* VEX_W_0F3836_P_2  */
11299     { "vpermd",         { XM, Vex, EXx }, 0 },
11300   },
11301   {
11302     /* VEX_W_0F3837_P_2 */
11303     { "vpcmpgtq",       { XM, Vex, EXx }, 0 },
11304   },
11305   {
11306     /* VEX_W_0F3838_P_2 */
11307     { "vpminsb",        { XM, Vex, EXx }, 0 },
11308   },
11309   {
11310     /* VEX_W_0F3839_P_2 */
11311     { "vpminsd",        { XM, Vex, EXx }, 0 },
11312   },
11313   {
11314     /* VEX_W_0F383A_P_2 */
11315     { "vpminuw",        { XM, Vex, EXx }, 0 },
11316   },
11317   {
11318     /* VEX_W_0F383B_P_2 */
11319     { "vpminud",        { XM, Vex, EXx }, 0 },
11320   },
11321   {
11322     /* VEX_W_0F383C_P_2 */
11323     { "vpmaxsb",        { XM, Vex, EXx }, 0 },
11324   },
11325   {
11326     /* VEX_W_0F383D_P_2 */
11327     { "vpmaxsd",        { XM, Vex, EXx }, 0 },
11328   },
11329   {
11330     /* VEX_W_0F383E_P_2 */
11331     { "vpmaxuw",        { XM, Vex, EXx }, 0 },
11332   },
11333   {
11334     /* VEX_W_0F383F_P_2 */
11335     { "vpmaxud",        { XM, Vex, EXx }, 0 },
11336   },
11337   {
11338     /* VEX_W_0F3840_P_2 */
11339     { "vpmulld",        { XM, Vex, EXx }, 0 },
11340   },
11341   {
11342     /* VEX_W_0F3841_P_2 */
11343     { "vphminposuw",    { XM, EXx }, 0 },
11344   },
11345   {
11346     /* VEX_W_0F3846_P_2 */
11347     { "vpsravd",        { XM, Vex, EXx }, 0 },
11348   },
11349   {
11350     /* VEX_W_0F3858_P_2 */
11351     { "vpbroadcastd", { XM, EXxmm_md }, 0 },
11352   },
11353   {
11354     /* VEX_W_0F3859_P_2 */
11355     { "vpbroadcastq",   { XM, EXxmm_mq }, 0 },
11356   },
11357   {
11358     /* VEX_W_0F385A_P_2_M_0 */
11359     { "vbroadcasti128", { XM, Mxmm }, 0 },
11360   },
11361   {
11362     /* VEX_W_0F3878_P_2 */
11363     { "vpbroadcastb",   { XM, EXxmm_mb }, 0 },
11364   },
11365   {
11366     /* VEX_W_0F3879_P_2 */
11367     { "vpbroadcastw",   { XM, EXxmm_mw }, 0 },
11368   },
11369   {
11370     /* VEX_W_0F38DB_P_2 */
11371     { "vaesimc",        { XM, EXx }, 0 },
11372   },
11373   {
11374     /* VEX_W_0F38DC_P_2 */
11375     { "vaesenc",        { XM, Vex128, EXx }, 0 },
11376   },
11377   {
11378     /* VEX_W_0F38DD_P_2 */
11379     { "vaesenclast",    { XM, Vex128, EXx }, 0 },
11380   },
11381   {
11382     /* VEX_W_0F38DE_P_2 */
11383     { "vaesdec",        { XM, Vex128, EXx }, 0 },
11384   },
11385   {
11386     /* VEX_W_0F38DF_P_2 */
11387     { "vaesdeclast",    { XM, Vex128, EXx }, 0 },
11388   },
11389   {
11390     /* VEX_W_0F3A00_P_2 */
11391     { Bad_Opcode },
11392     { "vpermq",         { XM, EXx, Ib }, 0 },
11393   },
11394   {
11395     /* VEX_W_0F3A01_P_2 */
11396     { Bad_Opcode },
11397     { "vpermpd",        { XM, EXx, Ib }, 0 },
11398   },
11399   {
11400     /* VEX_W_0F3A02_P_2 */
11401     { "vpblendd",       { XM, Vex, EXx, Ib }, 0 },
11402   },
11403   {
11404     /* VEX_W_0F3A04_P_2 */
11405     { "vpermilps",      { XM, EXx, Ib }, 0 },
11406   },
11407   {
11408     /* VEX_W_0F3A05_P_2 */
11409     { "vpermilpd",      { XM, EXx, Ib }, 0 },
11410   },
11411   {
11412     /* VEX_W_0F3A06_P_2 */
11413     { "vperm2f128",     { XM, Vex256, EXx, Ib }, 0 },
11414   },
11415   {
11416     /* VEX_W_0F3A08_P_2 */
11417     { "vroundps",       { XM, EXx, Ib }, 0 },
11418   },
11419   {
11420     /* VEX_W_0F3A09_P_2 */
11421     { "vroundpd",       { XM, EXx, Ib }, 0 },
11422   },
11423   {
11424     /* VEX_W_0F3A0A_P_2 */
11425     { "vroundss",       { XMScalar, VexScalar, EXdScalar, Ib }, 0 },
11426   },
11427   {
11428     /* VEX_W_0F3A0B_P_2 */
11429     { "vroundsd",       { XMScalar, VexScalar, EXqScalar, Ib }, 0 },
11430   },
11431   {
11432     /* VEX_W_0F3A0C_P_2 */
11433     { "vblendps",       { XM, Vex, EXx, Ib }, 0 },
11434   },
11435   {
11436     /* VEX_W_0F3A0D_P_2 */
11437     { "vblendpd",       { XM, Vex, EXx, Ib }, 0 },
11438   },
11439   {
11440     /* VEX_W_0F3A0E_P_2 */
11441     { "vpblendw",       { XM, Vex, EXx, Ib }, 0 },
11442   },
11443   {
11444     /* VEX_W_0F3A0F_P_2 */
11445     { "vpalignr",       { XM, Vex, EXx, Ib }, 0 },
11446   },
11447   {
11448     /* VEX_W_0F3A14_P_2 */
11449     { "vpextrb",        { Edqb, XM, Ib }, 0 },
11450   },
11451   {
11452     /* VEX_W_0F3A15_P_2 */
11453     { "vpextrw",        { Edqw, XM, Ib }, 0 },
11454   },
11455   {
11456     /* VEX_W_0F3A18_P_2 */
11457     { "vinsertf128",    { XM, Vex256, EXxmm, Ib }, 0 },
11458   },
11459   {
11460     /* VEX_W_0F3A19_P_2 */
11461     { "vextractf128",   { EXxmm, XM, Ib }, 0 },
11462   },
11463   {
11464     /* VEX_W_0F3A20_P_2 */
11465     { "vpinsrb",        { XM, Vex128, Edqb, Ib }, 0 },
11466   },
11467   {
11468     /* VEX_W_0F3A21_P_2 */
11469     { "vinsertps",      { XM, Vex128, EXd, Ib }, 0 },
11470   },
11471   {
11472     /* VEX_W_0F3A30_P_2_LEN_0 */
11473     { "kshiftrb",       { MaskG, MaskR, Ib }, 0 },
11474     { "kshiftrw",       { MaskG, MaskR, Ib }, 0 },
11475   },
11476   {
11477     /* VEX_W_0F3A31_P_2_LEN_0 */
11478     { "kshiftrd",       { MaskG, MaskR, Ib }, 0 },
11479     { "kshiftrq",       { MaskG, MaskR, Ib }, 0 },
11480   },
11481   {
11482     /* VEX_W_0F3A32_P_2_LEN_0 */
11483     { "kshiftlb",       { MaskG, MaskR, Ib }, 0 },
11484     { "kshiftlw",       { MaskG, MaskR, Ib }, 0 },
11485   },
11486   {
11487     /* VEX_W_0F3A33_P_2_LEN_0 */
11488     { "kshiftld",       { MaskG, MaskR, Ib }, 0 },
11489     { "kshiftlq",       { MaskG, MaskR, Ib }, 0 },
11490   },
11491   {
11492     /* VEX_W_0F3A38_P_2 */
11493     { "vinserti128",    { XM, Vex256, EXxmm, Ib }, 0 },
11494   },
11495   {
11496     /* VEX_W_0F3A39_P_2 */
11497     { "vextracti128",   { EXxmm, XM, Ib }, 0 },
11498   },
11499   {
11500     /* VEX_W_0F3A40_P_2 */
11501     { "vdpps",          { XM, Vex, EXx, Ib }, 0 },
11502   },
11503   {
11504     /* VEX_W_0F3A41_P_2 */
11505     { "vdppd",          { XM, Vex128, EXx, Ib }, 0 },
11506   },
11507   {
11508     /* VEX_W_0F3A42_P_2 */
11509     { "vmpsadbw",       { XM, Vex, EXx, Ib }, 0 },
11510   },
11511   {
11512     /* VEX_W_0F3A44_P_2 */
11513     { "vpclmulqdq",     { XM, Vex128, EXx, PCLMUL }, 0 },
11514   },
11515   {
11516     /* VEX_W_0F3A46_P_2 */
11517     { "vperm2i128",     { XM, Vex256, EXx, Ib }, 0 },
11518   },
11519   {
11520     /* VEX_W_0F3A48_P_2 */
11521     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11522     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11523   },
11524   {
11525     /* VEX_W_0F3A49_P_2 */
11526     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11527     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11528   },
11529   {
11530     /* VEX_W_0F3A4A_P_2 */
11531     { "vblendvps",      { XM, Vex, EXx, XMVexI4 }, 0 },
11532   },
11533   {
11534     /* VEX_W_0F3A4B_P_2 */
11535     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 }, 0 },
11536   },
11537   {
11538     /* VEX_W_0F3A4C_P_2 */
11539     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 }, 0 },
11540   },
11541   {
11542     /* VEX_W_0F3A60_P_2 */
11543     { "vpcmpestrm",     { XM, EXx, Ib }, 0 },
11544   },
11545   {
11546     /* VEX_W_0F3A61_P_2 */
11547     { "vpcmpestri",     { XM, EXx, Ib }, 0 },
11548   },
11549   {
11550     /* VEX_W_0F3A62_P_2 */
11551     { "vpcmpistrm",     { XM, EXx, Ib }, 0 },
11552   },
11553   {
11554     /* VEX_W_0F3A63_P_2 */
11555     { "vpcmpistri",     { XM, EXx, Ib }, 0 },
11556   },
11557   {
11558     /* VEX_W_0F3ADF_P_2 */
11559     { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
11560   },
11561 #define NEED_VEX_W_TABLE
11562 #include "i386-dis-evex.h"
11563 #undef NEED_VEX_W_TABLE
11564 };
11565
11566 static const struct dis386 mod_table[][2] = {
11567   {
11568     /* MOD_8D */
11569     { "leaS",           { Gv, M }, 0 },
11570   },
11571   {
11572     /* MOD_C6_REG_7 */
11573     { Bad_Opcode },
11574     { RM_TABLE (RM_C6_REG_7) },
11575   },
11576   {
11577     /* MOD_C7_REG_7 */
11578     { Bad_Opcode },
11579     { RM_TABLE (RM_C7_REG_7) },
11580   },
11581   {
11582     /* MOD_FF_REG_3 */
11583     { "Jcall{T|}", { indirEp }, 0 },
11584   },
11585   {
11586     /* MOD_FF_REG_5 */
11587     { "Jjmp{T|}", { indirEp }, 0 },
11588   },
11589   {
11590     /* MOD_0F01_REG_0 */
11591     { X86_64_TABLE (X86_64_0F01_REG_0) },
11592     { RM_TABLE (RM_0F01_REG_0) },
11593   },
11594   {
11595     /* MOD_0F01_REG_1 */
11596     { X86_64_TABLE (X86_64_0F01_REG_1) },
11597     { RM_TABLE (RM_0F01_REG_1) },
11598   },
11599   {
11600     /* MOD_0F01_REG_2 */
11601     { X86_64_TABLE (X86_64_0F01_REG_2) },
11602     { RM_TABLE (RM_0F01_REG_2) },
11603   },
11604   {
11605     /* MOD_0F01_REG_3 */
11606     { X86_64_TABLE (X86_64_0F01_REG_3) },
11607     { RM_TABLE (RM_0F01_REG_3) },
11608   },
11609   {
11610     /* MOD_0F01_REG_7 */
11611     { "invlpg",         { Mb }, 0 },
11612     { RM_TABLE (RM_0F01_REG_7) },
11613   },
11614   {
11615     /* MOD_0F12_PREFIX_0 */
11616     { "movlps",         { XM, EXq }, PREFIX_OPCODE },
11617     { "movhlps",        { XM, EXq }, PREFIX_OPCODE },
11618   },
11619   {
11620     /* MOD_0F13 */
11621     { "movlpX",         { EXq, XM }, PREFIX_OPCODE },
11622   },
11623   {
11624     /* MOD_0F16_PREFIX_0 */
11625     { "movhps",         { XM, EXq }, 0 },
11626     { "movlhps",        { XM, EXq }, 0 },
11627   },
11628   {
11629     /* MOD_0F17 */
11630     { "movhpX",         { EXq, XM }, PREFIX_OPCODE },
11631   },
11632   {
11633     /* MOD_0F18_REG_0 */
11634     { "prefetchnta",    { Mb }, 0 },
11635   },
11636   {
11637     /* MOD_0F18_REG_1 */
11638     { "prefetcht0",     { Mb }, 0 },
11639   },
11640   {
11641     /* MOD_0F18_REG_2 */
11642     { "prefetcht1",     { Mb }, 0 },
11643   },
11644   {
11645     /* MOD_0F18_REG_3 */
11646     { "prefetcht2",     { Mb }, 0 },
11647   },
11648   {
11649     /* MOD_0F18_REG_4 */
11650     { "nop/reserved",   { Mb }, 0 },
11651   },
11652   {
11653     /* MOD_0F18_REG_5 */
11654     { "nop/reserved",   { Mb }, 0 },
11655   },
11656   {
11657     /* MOD_0F18_REG_6 */
11658     { "nop/reserved",   { Mb }, 0 },
11659   },
11660   {
11661     /* MOD_0F18_REG_7 */
11662     { "nop/reserved",   { Mb }, 0 },
11663   },
11664   {
11665     /* MOD_0F1A_PREFIX_0 */
11666     { "bndldx",         { Gbnd, Ev_bnd }, 0 },
11667     { "nopQ",           { Ev }, 0 },
11668   },
11669   {
11670     /* MOD_0F1B_PREFIX_0 */
11671     { "bndstx",         { Ev_bnd, Gbnd }, 0 },
11672     { "nopQ",           { Ev }, 0 },
11673   },
11674   {
11675     /* MOD_0F1B_PREFIX_1 */
11676     { "bndmk",          { Gbnd, Ev_bnd }, 0 },
11677     { "nopQ",           { Ev }, 0 },
11678   },
11679   {
11680     /* MOD_0F24 */
11681     { Bad_Opcode },
11682     { "movL",           { Rd, Td }, 0 },
11683   },
11684   {
11685     /* MOD_0F26 */
11686     { Bad_Opcode },
11687     { "movL",           { Td, Rd }, 0 },
11688   },
11689   {
11690     /* MOD_0F2B_PREFIX_0 */
11691     {"movntps",         { Mx, XM }, PREFIX_OPCODE },
11692   },
11693   {
11694     /* MOD_0F2B_PREFIX_1 */
11695     {"movntss",         { Md, XM }, PREFIX_OPCODE },
11696   },
11697   {
11698     /* MOD_0F2B_PREFIX_2 */
11699     {"movntpd",         { Mx, XM }, PREFIX_OPCODE },
11700   },
11701   {
11702     /* MOD_0F2B_PREFIX_3 */
11703     {"movntsd",         { Mq, XM }, PREFIX_OPCODE },
11704   },
11705   {
11706     /* MOD_0F51 */
11707     { Bad_Opcode },
11708     { "movmskpX",       { Gdq, XS }, PREFIX_OPCODE },
11709   },
11710   {
11711     /* MOD_0F71_REG_2 */
11712     { Bad_Opcode },
11713     { "psrlw",          { MS, Ib }, 0 },
11714   },
11715   {
11716     /* MOD_0F71_REG_4 */
11717     { Bad_Opcode },
11718     { "psraw",          { MS, Ib }, 0 },
11719   },
11720   {
11721     /* MOD_0F71_REG_6 */
11722     { Bad_Opcode },
11723     { "psllw",          { MS, Ib }, 0 },
11724   },
11725   {
11726     /* MOD_0F72_REG_2 */
11727     { Bad_Opcode },
11728     { "psrld",          { MS, Ib }, 0 },
11729   },
11730   {
11731     /* MOD_0F72_REG_4 */
11732     { Bad_Opcode },
11733     { "psrad",          { MS, Ib }, 0 },
11734   },
11735   {
11736     /* MOD_0F72_REG_6 */
11737     { Bad_Opcode },
11738     { "pslld",          { MS, Ib }, 0 },
11739   },
11740   {
11741     /* MOD_0F73_REG_2 */
11742     { Bad_Opcode },
11743     { "psrlq",          { MS, Ib }, 0 },
11744   },
11745   {
11746     /* MOD_0F73_REG_3 */
11747     { Bad_Opcode },
11748     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
11749   },
11750   {
11751     /* MOD_0F73_REG_6 */
11752     { Bad_Opcode },
11753     { "psllq",          { MS, Ib }, 0 },
11754   },
11755   {
11756     /* MOD_0F73_REG_7 */
11757     { Bad_Opcode },
11758     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
11759   },
11760   {
11761     /* MOD_0FAE_REG_0 */
11762     { "fxsave",         { FXSAVE }, 0 },
11763     { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
11764   },
11765   {
11766     /* MOD_0FAE_REG_1 */
11767     { "fxrstor",        { FXSAVE }, 0 },
11768     { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
11769   },
11770   {
11771     /* MOD_0FAE_REG_2 */
11772     { "ldmxcsr",        { Md }, 0 },
11773     { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
11774   },
11775   {
11776     /* MOD_0FAE_REG_3 */
11777     { "stmxcsr",        { Md }, 0 },
11778     { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
11779   },
11780   {
11781     /* MOD_0FAE_REG_4 */
11782     { "xsave",          { FXSAVE }, 0 },
11783   },
11784   {
11785     /* MOD_0FAE_REG_5 */
11786     { "xrstor",         { FXSAVE }, 0 },
11787     { RM_TABLE (RM_0FAE_REG_5) },
11788   },
11789   {
11790     /* MOD_0FAE_REG_6 */
11791     { PREFIX_TABLE (PREFIX_0FAE_REG_6) },
11792     { RM_TABLE (RM_0FAE_REG_6) },
11793   },
11794   {
11795     /* MOD_0FAE_REG_7 */
11796     { PREFIX_TABLE (PREFIX_0FAE_REG_7) },
11797     { RM_TABLE (RM_0FAE_REG_7) },
11798   },
11799   {
11800     /* MOD_0FB2 */
11801     { "lssS",           { Gv, Mp }, 0 },
11802   },
11803   {
11804     /* MOD_0FB4 */
11805     { "lfsS",           { Gv, Mp }, 0 },
11806   },
11807   {
11808     /* MOD_0FB5 */
11809     { "lgsS",           { Gv, Mp }, 0 },
11810   },
11811   {
11812     /* MOD_0FC7_REG_3 */
11813     { "xrstors",                { FXSAVE }, 0 },
11814   },
11815   {
11816     /* MOD_0FC7_REG_4 */
11817     { "xsavec",         { FXSAVE }, 0 },
11818   },
11819   {
11820     /* MOD_0FC7_REG_5 */
11821     { "xsaves",         { FXSAVE }, 0 },
11822   },
11823   {
11824     /* MOD_0FC7_REG_6 */
11825     { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6) },
11826     { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6) }
11827   },
11828   {
11829     /* MOD_0FC7_REG_7 */
11830     { "vmptrst",        { Mq }, 0 },
11831     { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7) }
11832   },
11833   {
11834     /* MOD_0FD7 */
11835     { Bad_Opcode },
11836     { "pmovmskb",       { Gdq, MS }, 0 },
11837   },
11838   {
11839     /* MOD_0FE7_PREFIX_2 */
11840     { "movntdq",        { Mx, XM }, 0 },
11841   },
11842   {
11843     /* MOD_0FF0_PREFIX_3 */
11844     { "lddqu",          { XM, M }, 0 },
11845   },
11846   {
11847     /* MOD_0F382A_PREFIX_2 */
11848     { "movntdqa",       { XM, Mx }, 0 },
11849   },
11850   {
11851     /* MOD_62_32BIT */
11852     { "bound{S|}",      { Gv, Ma }, 0 },
11853     { EVEX_TABLE (EVEX_0F) },
11854   },
11855   {
11856     /* MOD_C4_32BIT */
11857     { "lesS",           { Gv, Mp }, 0 },
11858     { VEX_C4_TABLE (VEX_0F) },
11859   },
11860   {
11861     /* MOD_C5_32BIT */
11862     { "ldsS",           { Gv, Mp }, 0 },
11863     { VEX_C5_TABLE (VEX_0F) },
11864   },
11865   {
11866     /* MOD_VEX_0F12_PREFIX_0 */
11867     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
11868     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
11869   },
11870   {
11871     /* MOD_VEX_0F13 */
11872     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
11873   },
11874   {
11875     /* MOD_VEX_0F16_PREFIX_0 */
11876     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
11877     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
11878   },
11879   {
11880     /* MOD_VEX_0F17 */
11881     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
11882   },
11883   {
11884     /* MOD_VEX_0F2B */
11885     { VEX_W_TABLE (VEX_W_0F2B_M_0) },
11886   },
11887   {
11888     /* MOD_VEX_0F50 */
11889     { Bad_Opcode },
11890     { VEX_W_TABLE (VEX_W_0F50_M_0) },
11891   },
11892   {
11893     /* MOD_VEX_0F71_REG_2 */
11894     { Bad_Opcode },
11895     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
11896   },
11897   {
11898     /* MOD_VEX_0F71_REG_4 */
11899     { Bad_Opcode },
11900     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
11901   },
11902   {
11903     /* MOD_VEX_0F71_REG_6 */
11904     { Bad_Opcode },
11905     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
11906   },
11907   {
11908     /* MOD_VEX_0F72_REG_2 */
11909     { Bad_Opcode },
11910     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
11911   },
11912   {
11913     /* MOD_VEX_0F72_REG_4 */
11914     { Bad_Opcode },
11915     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
11916   },
11917   {
11918     /* MOD_VEX_0F72_REG_6 */
11919     { Bad_Opcode },
11920     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
11921   },
11922   {
11923     /* MOD_VEX_0F73_REG_2 */
11924     { Bad_Opcode },
11925     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
11926   },
11927   {
11928     /* MOD_VEX_0F73_REG_3 */
11929     { Bad_Opcode },
11930     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
11931   },
11932   {
11933     /* MOD_VEX_0F73_REG_6 */
11934     { Bad_Opcode },
11935     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
11936   },
11937   {
11938     /* MOD_VEX_0F73_REG_7 */
11939     { Bad_Opcode },
11940     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
11941   },
11942   {
11943     /* MOD_VEX_0FAE_REG_2 */
11944     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
11945   },
11946   {
11947     /* MOD_VEX_0FAE_REG_3 */
11948     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
11949   },
11950   {
11951     /* MOD_VEX_0FD7_PREFIX_2 */
11952     { Bad_Opcode },
11953     { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) },
11954   },
11955   {
11956     /* MOD_VEX_0FE7_PREFIX_2 */
11957     { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) },
11958   },
11959   {
11960     /* MOD_VEX_0FF0_PREFIX_3 */
11961     { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) },
11962   },
11963   {
11964     /* MOD_VEX_0F381A_PREFIX_2 */
11965     { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
11966   },
11967   {
11968     /* MOD_VEX_0F382A_PREFIX_2 */
11969     { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) },
11970   },
11971   {
11972     /* MOD_VEX_0F382C_PREFIX_2 */
11973     { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
11974   },
11975   {
11976     /* MOD_VEX_0F382D_PREFIX_2 */
11977     { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
11978   },
11979   {
11980     /* MOD_VEX_0F382E_PREFIX_2 */
11981     { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
11982   },
11983   {
11984     /* MOD_VEX_0F382F_PREFIX_2 */
11985     { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
11986   },
11987   {
11988     /* MOD_VEX_0F385A_PREFIX_2 */
11989     { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
11990   },
11991   {
11992     /* MOD_VEX_0F388C_PREFIX_2 */
11993     { "vpmaskmov%LW",   { XM, Vex, Mx }, 0 },
11994   },
11995   {
11996     /* MOD_VEX_0F388E_PREFIX_2 */
11997     { "vpmaskmov%LW",   { Mx, Vex, XM }, 0 },
11998   },
11999 #define NEED_MOD_TABLE
12000 #include "i386-dis-evex.h"
12001 #undef NEED_MOD_TABLE
12002 };
12003
12004 static const struct dis386 rm_table[][8] = {
12005   {
12006     /* RM_C6_REG_7 */
12007     { "xabort",         { Skip_MODRM, Ib }, 0 },
12008   },
12009   {
12010     /* RM_C7_REG_7 */
12011     { "xbeginT",        { Skip_MODRM, Jv }, 0 },
12012   },
12013   {
12014     /* RM_0F01_REG_0 */
12015     { Bad_Opcode },
12016     { "vmcall",         { Skip_MODRM }, 0 },
12017     { "vmlaunch",       { Skip_MODRM }, 0 },
12018     { "vmresume",       { Skip_MODRM }, 0 },
12019     { "vmxoff",         { Skip_MODRM }, 0 },
12020   },
12021   {
12022     /* RM_0F01_REG_1 */
12023     { "monitor",        { { OP_Monitor, 0 } }, 0 },
12024     { "mwait",          { { OP_Mwait, 0 } }, 0 },
12025     { "clac",           { Skip_MODRM }, 0 },
12026     { "stac",           { Skip_MODRM }, 0 },
12027     { Bad_Opcode },
12028     { Bad_Opcode },
12029     { Bad_Opcode },
12030     { "encls",          { Skip_MODRM }, 0 },
12031   },
12032   {
12033     /* RM_0F01_REG_2 */
12034     { "xgetbv",         { Skip_MODRM }, 0 },
12035     { "xsetbv",         { Skip_MODRM }, 0 },
12036     { Bad_Opcode },
12037     { Bad_Opcode },
12038     { "vmfunc",         { Skip_MODRM }, 0 },
12039     { "xend",           { Skip_MODRM }, 0 },
12040     { "xtest",          { Skip_MODRM }, 0 },
12041     { "enclu",          { Skip_MODRM }, 0 },
12042   },
12043   {
12044     /* RM_0F01_REG_3 */
12045     { "vmrun",          { Skip_MODRM }, 0 },
12046     { "vmmcall",        { Skip_MODRM }, 0 },
12047     { "vmload",         { Skip_MODRM }, 0 },
12048     { "vmsave",         { Skip_MODRM }, 0 },
12049     { "stgi",           { Skip_MODRM }, 0 },
12050     { "clgi",           { Skip_MODRM }, 0 },
12051     { "skinit",         { Skip_MODRM }, 0 },
12052     { "invlpga",        { Skip_MODRM }, 0 },
12053   },
12054   {
12055     /* RM_0F01_REG_7 */
12056     { "swapgs",         { Skip_MODRM }, 0  },
12057     { "rdtscp",         { Skip_MODRM }, 0  },
12058     { Bad_Opcode },
12059     { Bad_Opcode },
12060     { "clzero",         { Skip_MODRM }, 0  },
12061   },
12062   {
12063     /* RM_0FAE_REG_5 */
12064     { "lfence",         { Skip_MODRM }, 0 },
12065   },
12066   {
12067     /* RM_0FAE_REG_6 */
12068     { "mfence",         { Skip_MODRM }, 0 },
12069   },
12070   {
12071     /* RM_0FAE_REG_7 */
12072     { PREFIX_TABLE (PREFIX_RM_0_0FAE_REG_7) },
12073   },
12074 };
12075
12076 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
12077
12078 /* We use the high bit to indicate different name for the same
12079    prefix.  */
12080 #define REP_PREFIX      (0xf3 | 0x100)
12081 #define XACQUIRE_PREFIX (0xf2 | 0x200)
12082 #define XRELEASE_PREFIX (0xf3 | 0x400)
12083 #define BND_PREFIX      (0xf2 | 0x400)
12084
12085 static int
12086 ckprefix (void)
12087 {
12088   int newrex, i, length;
12089   rex = 0;
12090   rex_ignored = 0;
12091   prefixes = 0;
12092   used_prefixes = 0;
12093   rex_used = 0;
12094   last_lock_prefix = -1;
12095   last_repz_prefix = -1;
12096   last_repnz_prefix = -1;
12097   last_data_prefix = -1;
12098   last_addr_prefix = -1;
12099   last_rex_prefix = -1;
12100   last_seg_prefix = -1;
12101   fwait_prefix = -1;
12102   active_seg_prefix = 0;
12103   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12104     all_prefixes[i] = 0;
12105   i = 0;
12106   length = 0;
12107   /* The maximum instruction length is 15bytes.  */
12108   while (length < MAX_CODE_LENGTH - 1)
12109     {
12110       FETCH_DATA (the_info, codep + 1);
12111       newrex = 0;
12112       switch (*codep)
12113         {
12114         /* REX prefixes family.  */
12115         case 0x40:
12116         case 0x41:
12117         case 0x42:
12118         case 0x43:
12119         case 0x44:
12120         case 0x45:
12121         case 0x46:
12122         case 0x47:
12123         case 0x48:
12124         case 0x49:
12125         case 0x4a:
12126         case 0x4b:
12127         case 0x4c:
12128         case 0x4d:
12129         case 0x4e:
12130         case 0x4f:
12131           if (address_mode == mode_64bit)
12132             newrex = *codep;
12133           else
12134             return 1;
12135           last_rex_prefix = i;
12136           break;
12137         case 0xf3:
12138           prefixes |= PREFIX_REPZ;
12139           last_repz_prefix = i;
12140           break;
12141         case 0xf2:
12142           prefixes |= PREFIX_REPNZ;
12143           last_repnz_prefix = i;
12144           break;
12145         case 0xf0:
12146           prefixes |= PREFIX_LOCK;
12147           last_lock_prefix = i;
12148           break;
12149         case 0x2e:
12150           prefixes |= PREFIX_CS;
12151           last_seg_prefix = i;
12152           active_seg_prefix = PREFIX_CS;
12153           break;
12154         case 0x36:
12155           prefixes |= PREFIX_SS;
12156           last_seg_prefix = i;
12157           active_seg_prefix = PREFIX_SS;
12158           break;
12159         case 0x3e:
12160           prefixes |= PREFIX_DS;
12161           last_seg_prefix = i;
12162           active_seg_prefix = PREFIX_DS;
12163           break;
12164         case 0x26:
12165           prefixes |= PREFIX_ES;
12166           last_seg_prefix = i;
12167           active_seg_prefix = PREFIX_ES;
12168           break;
12169         case 0x64:
12170           prefixes |= PREFIX_FS;
12171           last_seg_prefix = i;
12172           active_seg_prefix = PREFIX_FS;
12173           break;
12174         case 0x65:
12175           prefixes |= PREFIX_GS;
12176           last_seg_prefix = i;
12177           active_seg_prefix = PREFIX_GS;
12178           break;
12179         case 0x66:
12180           prefixes |= PREFIX_DATA;
12181           last_data_prefix = i;
12182           break;
12183         case 0x67:
12184           prefixes |= PREFIX_ADDR;
12185           last_addr_prefix = i;
12186           break;
12187         case FWAIT_OPCODE:
12188           /* fwait is really an instruction.  If there are prefixes
12189              before the fwait, they belong to the fwait, *not* to the
12190              following instruction.  */
12191           fwait_prefix = i;
12192           if (prefixes || rex)
12193             {
12194               prefixes |= PREFIX_FWAIT;
12195               codep++;
12196               /* This ensures that the previous REX prefixes are noticed
12197                  as unused prefixes, as in the return case below.  */
12198               rex_used = rex;
12199               return 1;
12200             }
12201           prefixes = PREFIX_FWAIT;
12202           break;
12203         default:
12204           return 1;
12205         }
12206       /* Rex is ignored when followed by another prefix.  */
12207       if (rex)
12208         {
12209           rex_used = rex;
12210           return 1;
12211         }
12212       if (*codep != FWAIT_OPCODE)
12213         all_prefixes[i++] = *codep;
12214       rex = newrex;
12215       codep++;
12216       length++;
12217     }
12218   return 0;
12219 }
12220
12221 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
12222    prefix byte.  */
12223
12224 static const char *
12225 prefix_name (int pref, int sizeflag)
12226 {
12227   static const char *rexes [16] =
12228     {
12229       "rex",            /* 0x40 */
12230       "rex.B",          /* 0x41 */
12231       "rex.X",          /* 0x42 */
12232       "rex.XB",         /* 0x43 */
12233       "rex.R",          /* 0x44 */
12234       "rex.RB",         /* 0x45 */
12235       "rex.RX",         /* 0x46 */
12236       "rex.RXB",        /* 0x47 */
12237       "rex.W",          /* 0x48 */
12238       "rex.WB",         /* 0x49 */
12239       "rex.WX",         /* 0x4a */
12240       "rex.WXB",        /* 0x4b */
12241       "rex.WR",         /* 0x4c */
12242       "rex.WRB",        /* 0x4d */
12243       "rex.WRX",        /* 0x4e */
12244       "rex.WRXB",       /* 0x4f */
12245     };
12246
12247   switch (pref)
12248     {
12249     /* REX prefixes family.  */
12250     case 0x40:
12251     case 0x41:
12252     case 0x42:
12253     case 0x43:
12254     case 0x44:
12255     case 0x45:
12256     case 0x46:
12257     case 0x47:
12258     case 0x48:
12259     case 0x49:
12260     case 0x4a:
12261     case 0x4b:
12262     case 0x4c:
12263     case 0x4d:
12264     case 0x4e:
12265     case 0x4f:
12266       return rexes [pref - 0x40];
12267     case 0xf3:
12268       return "repz";
12269     case 0xf2:
12270       return "repnz";
12271     case 0xf0:
12272       return "lock";
12273     case 0x2e:
12274       return "cs";
12275     case 0x36:
12276       return "ss";
12277     case 0x3e:
12278       return "ds";
12279     case 0x26:
12280       return "es";
12281     case 0x64:
12282       return "fs";
12283     case 0x65:
12284       return "gs";
12285     case 0x66:
12286       return (sizeflag & DFLAG) ? "data16" : "data32";
12287     case 0x67:
12288       if (address_mode == mode_64bit)
12289         return (sizeflag & AFLAG) ? "addr32" : "addr64";
12290       else
12291         return (sizeflag & AFLAG) ? "addr16" : "addr32";
12292     case FWAIT_OPCODE:
12293       return "fwait";
12294     case REP_PREFIX:
12295       return "rep";
12296     case XACQUIRE_PREFIX:
12297       return "xacquire";
12298     case XRELEASE_PREFIX:
12299       return "xrelease";
12300     case BND_PREFIX:
12301       return "bnd";
12302     default:
12303       return NULL;
12304     }
12305 }
12306
12307 static char op_out[MAX_OPERANDS][100];
12308 static int op_ad, op_index[MAX_OPERANDS];
12309 static int two_source_ops;
12310 static bfd_vma op_address[MAX_OPERANDS];
12311 static bfd_vma op_riprel[MAX_OPERANDS];
12312 static bfd_vma start_pc;
12313
12314 /*
12315  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
12316  *   (see topic "Redundant prefixes" in the "Differences from 8086"
12317  *   section of the "Virtual 8086 Mode" chapter.)
12318  * 'pc' should be the address of this instruction, it will
12319  *   be used to print the target address if this is a relative jump or call
12320  * The function returns the length of this instruction in bytes.
12321  */
12322
12323 static char intel_syntax;
12324 static char intel_mnemonic = !SYSV386_COMPAT;
12325 static char open_char;
12326 static char close_char;
12327 static char separator_char;
12328 static char scale_char;
12329
12330 /* Here for backwards compatibility.  When gdb stops using
12331    print_insn_i386_att and print_insn_i386_intel these functions can
12332    disappear, and print_insn_i386 be merged into print_insn.  */
12333 int
12334 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
12335 {
12336   intel_syntax = 0;
12337
12338   return print_insn (pc, info);
12339 }
12340
12341 int
12342 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
12343 {
12344   intel_syntax = 1;
12345
12346   return print_insn (pc, info);
12347 }
12348
12349 int
12350 print_insn_i386 (bfd_vma pc, disassemble_info *info)
12351 {
12352   intel_syntax = -1;
12353
12354   return print_insn (pc, info);
12355 }
12356
12357 void
12358 print_i386_disassembler_options (FILE *stream)
12359 {
12360   fprintf (stream, _("\n\
12361 The following i386/x86-64 specific disassembler options are supported for use\n\
12362 with the -M switch (multiple options should be separated by commas):\n"));
12363
12364   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
12365   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
12366   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
12367   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
12368   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
12369   fprintf (stream, _("  att-mnemonic\n"
12370                      "              Display instruction in AT&T mnemonic\n"));
12371   fprintf (stream, _("  intel-mnemonic\n"
12372                      "              Display instruction in Intel mnemonic\n"));
12373   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
12374   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
12375   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
12376   fprintf (stream, _("  data32      Assume 32bit data size\n"));
12377   fprintf (stream, _("  data16      Assume 16bit data size\n"));
12378   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
12379 }
12380
12381 /* Bad opcode.  */
12382 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
12383
12384 /* Get a pointer to struct dis386 with a valid name.  */
12385
12386 static const struct dis386 *
12387 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
12388 {
12389   int vindex, vex_table_index;
12390
12391   if (dp->name != NULL)
12392     return dp;
12393
12394   switch (dp->op[0].bytemode)
12395     {
12396     case USE_REG_TABLE:
12397       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
12398       break;
12399
12400     case USE_MOD_TABLE:
12401       vindex = modrm.mod == 0x3 ? 1 : 0;
12402       dp = &mod_table[dp->op[1].bytemode][vindex];
12403       break;
12404
12405     case USE_RM_TABLE:
12406       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
12407       break;
12408
12409     case USE_PREFIX_TABLE:
12410       if (need_vex)
12411         {
12412           /* The prefix in VEX is implicit.  */
12413           switch (vex.prefix)
12414             {
12415             case 0:
12416               vindex = 0;
12417               break;
12418             case REPE_PREFIX_OPCODE:
12419               vindex = 1;
12420               break;
12421             case DATA_PREFIX_OPCODE:
12422               vindex = 2;
12423               break;
12424             case REPNE_PREFIX_OPCODE:
12425               vindex = 3;
12426               break;
12427             default:
12428               abort ();
12429               break;
12430             }
12431         }
12432       else
12433         {
12434           int last_prefix = -1;
12435           int prefix = 0;
12436           vindex = 0;
12437           /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
12438              When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
12439              last one wins.  */
12440           if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
12441             {
12442               if (last_repz_prefix > last_repnz_prefix)
12443                 {
12444                   vindex = 1;
12445                   prefix = PREFIX_REPZ;
12446                   last_prefix = last_repz_prefix;
12447                 }
12448               else
12449                 {
12450                   vindex = 3;
12451                   prefix = PREFIX_REPNZ;
12452                   last_prefix = last_repnz_prefix;
12453                 }
12454
12455               /* Check if prefix should be ignored.  */
12456               if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
12457                      & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
12458                    & prefix) != 0)
12459                 vindex = 0;
12460             }
12461
12462           if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
12463             {
12464               vindex = 2;
12465               prefix = PREFIX_DATA;
12466               last_prefix = last_data_prefix;
12467             }
12468
12469           if (vindex != 0)
12470             {
12471               used_prefixes |= prefix;
12472               all_prefixes[last_prefix] = 0;
12473             }
12474         }
12475       dp = &prefix_table[dp->op[1].bytemode][vindex];
12476       break;
12477
12478     case USE_X86_64_TABLE:
12479       vindex = address_mode == mode_64bit ? 1 : 0;
12480       dp = &x86_64_table[dp->op[1].bytemode][vindex];
12481       break;
12482
12483     case USE_3BYTE_TABLE:
12484       FETCH_DATA (info, codep + 2);
12485       vindex = *codep++;
12486       dp = &three_byte_table[dp->op[1].bytemode][vindex];
12487       end_codep = codep;
12488       modrm.mod = (*codep >> 6) & 3;
12489       modrm.reg = (*codep >> 3) & 7;
12490       modrm.rm = *codep & 7;
12491       break;
12492
12493     case USE_VEX_LEN_TABLE:
12494       if (!need_vex)
12495         abort ();
12496
12497       switch (vex.length)
12498         {
12499         case 128:
12500           vindex = 0;
12501           break;
12502         case 256:
12503           vindex = 1;
12504           break;
12505         default:
12506           abort ();
12507           break;
12508         }
12509
12510       dp = &vex_len_table[dp->op[1].bytemode][vindex];
12511       break;
12512
12513     case USE_XOP_8F_TABLE:
12514       FETCH_DATA (info, codep + 3);
12515       /* All bits in the REX prefix are ignored.  */
12516       rex_ignored = rex;
12517       rex = ~(*codep >> 5) & 0x7;
12518
12519       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
12520       switch ((*codep & 0x1f))
12521         {
12522         default:
12523           dp = &bad_opcode;
12524           return dp;
12525         case 0x8:
12526           vex_table_index = XOP_08;
12527           break;
12528         case 0x9:
12529           vex_table_index = XOP_09;
12530           break;
12531         case 0xa:
12532           vex_table_index = XOP_0A;
12533           break;
12534         }
12535       codep++;
12536       vex.w = *codep & 0x80;
12537       if (vex.w && address_mode == mode_64bit)
12538         rex |= REX_W;
12539
12540       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12541       if (address_mode != mode_64bit
12542           && vex.register_specifier > 0x7)
12543         {
12544           dp = &bad_opcode;
12545           return dp;
12546         }
12547
12548       vex.length = (*codep & 0x4) ? 256 : 128;
12549       switch ((*codep & 0x3))
12550         {
12551         case 0:
12552           vex.prefix = 0;
12553           break;
12554         case 1:
12555           vex.prefix = DATA_PREFIX_OPCODE;
12556           break;
12557         case 2:
12558           vex.prefix = REPE_PREFIX_OPCODE;
12559           break;
12560         case 3:
12561           vex.prefix = REPNE_PREFIX_OPCODE;
12562           break;
12563         }
12564       need_vex = 1;
12565       need_vex_reg = 1;
12566       codep++;
12567       vindex = *codep++;
12568       dp = &xop_table[vex_table_index][vindex];
12569
12570       end_codep = codep;
12571       FETCH_DATA (info, codep + 1);
12572       modrm.mod = (*codep >> 6) & 3;
12573       modrm.reg = (*codep >> 3) & 7;
12574       modrm.rm = *codep & 7;
12575       break;
12576
12577     case USE_VEX_C4_TABLE:
12578       /* VEX prefix.  */
12579       FETCH_DATA (info, codep + 3);
12580       /* All bits in the REX prefix are ignored.  */
12581       rex_ignored = rex;
12582       rex = ~(*codep >> 5) & 0x7;
12583       switch ((*codep & 0x1f))
12584         {
12585         default:
12586           dp = &bad_opcode;
12587           return dp;
12588         case 0x1:
12589           vex_table_index = VEX_0F;
12590           break;
12591         case 0x2:
12592           vex_table_index = VEX_0F38;
12593           break;
12594         case 0x3:
12595           vex_table_index = VEX_0F3A;
12596           break;
12597         }
12598       codep++;
12599       vex.w = *codep & 0x80;
12600       if (vex.w && address_mode == mode_64bit)
12601         rex |= REX_W;
12602
12603       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12604       if (address_mode != mode_64bit
12605           && vex.register_specifier > 0x7)
12606         {
12607           dp = &bad_opcode;
12608           return dp;
12609         }
12610
12611       vex.length = (*codep & 0x4) ? 256 : 128;
12612       switch ((*codep & 0x3))
12613         {
12614         case 0:
12615           vex.prefix = 0;
12616           break;
12617         case 1:
12618           vex.prefix = DATA_PREFIX_OPCODE;
12619           break;
12620         case 2:
12621           vex.prefix = REPE_PREFIX_OPCODE;
12622           break;
12623         case 3:
12624           vex.prefix = REPNE_PREFIX_OPCODE;
12625           break;
12626         }
12627       need_vex = 1;
12628       need_vex_reg = 1;
12629       codep++;
12630       vindex = *codep++;
12631       dp = &vex_table[vex_table_index][vindex];
12632       end_codep = codep;
12633       /* There is no MODRM byte for VEX [82|77].  */
12634       if (vindex != 0x77 && vindex != 0x82)
12635         {
12636           FETCH_DATA (info, codep + 1);
12637           modrm.mod = (*codep >> 6) & 3;
12638           modrm.reg = (*codep >> 3) & 7;
12639           modrm.rm = *codep & 7;
12640         }
12641       break;
12642
12643     case USE_VEX_C5_TABLE:
12644       /* VEX prefix.  */
12645       FETCH_DATA (info, codep + 2);
12646       /* All bits in the REX prefix are ignored.  */
12647       rex_ignored = rex;
12648       rex = (*codep & 0x80) ? 0 : REX_R;
12649
12650       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12651       if (address_mode != mode_64bit
12652           && vex.register_specifier > 0x7)
12653         {
12654           dp = &bad_opcode;
12655           return dp;
12656         }
12657
12658       vex.w = 0;
12659
12660       vex.length = (*codep & 0x4) ? 256 : 128;
12661       switch ((*codep & 0x3))
12662         {
12663         case 0:
12664           vex.prefix = 0;
12665           break;
12666         case 1:
12667           vex.prefix = DATA_PREFIX_OPCODE;
12668           break;
12669         case 2:
12670           vex.prefix = REPE_PREFIX_OPCODE;
12671           break;
12672         case 3:
12673           vex.prefix = REPNE_PREFIX_OPCODE;
12674           break;
12675         }
12676       need_vex = 1;
12677       need_vex_reg = 1;
12678       codep++;
12679       vindex = *codep++;
12680       dp = &vex_table[dp->op[1].bytemode][vindex];
12681       end_codep = codep;
12682       /* There is no MODRM byte for VEX [82|77].  */
12683       if (vindex != 0x77 && vindex != 0x82)
12684         {
12685           FETCH_DATA (info, codep + 1);
12686           modrm.mod = (*codep >> 6) & 3;
12687           modrm.reg = (*codep >> 3) & 7;
12688           modrm.rm = *codep & 7;
12689         }
12690       break;
12691
12692     case USE_VEX_W_TABLE:
12693       if (!need_vex)
12694         abort ();
12695
12696       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
12697       break;
12698
12699     case USE_EVEX_TABLE:
12700       two_source_ops = 0;
12701       /* EVEX prefix.  */
12702       vex.evex = 1;
12703       FETCH_DATA (info, codep + 4);
12704       /* All bits in the REX prefix are ignored.  */
12705       rex_ignored = rex;
12706       /* The first byte after 0x62.  */
12707       rex = ~(*codep >> 5) & 0x7;
12708       vex.r = *codep & 0x10;
12709       switch ((*codep & 0xf))
12710         {
12711         default:
12712           return &bad_opcode;
12713         case 0x1:
12714           vex_table_index = EVEX_0F;
12715           break;
12716         case 0x2:
12717           vex_table_index = EVEX_0F38;
12718           break;
12719         case 0x3:
12720           vex_table_index = EVEX_0F3A;
12721           break;
12722         }
12723
12724       /* The second byte after 0x62.  */
12725       codep++;
12726       vex.w = *codep & 0x80;
12727       if (vex.w && address_mode == mode_64bit)
12728         rex |= REX_W;
12729
12730       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12731       if (address_mode != mode_64bit)
12732         {
12733           /* In 16/32-bit mode silently ignore following bits.  */
12734           rex &= ~REX_B;
12735           vex.r = 1;
12736           vex.v = 1;
12737           vex.register_specifier &= 0x7;
12738         }
12739
12740       /* The U bit.  */
12741       if (!(*codep & 0x4))
12742         return &bad_opcode;
12743
12744       switch ((*codep & 0x3))
12745         {
12746         case 0:
12747           vex.prefix = 0;
12748           break;
12749         case 1:
12750           vex.prefix = DATA_PREFIX_OPCODE;
12751           break;
12752         case 2:
12753           vex.prefix = REPE_PREFIX_OPCODE;
12754           break;
12755         case 3:
12756           vex.prefix = REPNE_PREFIX_OPCODE;
12757           break;
12758         }
12759
12760       /* The third byte after 0x62.  */
12761       codep++;
12762
12763       /* Remember the static rounding bits.  */
12764       vex.ll = (*codep >> 5) & 3;
12765       vex.b = (*codep & 0x10) != 0;
12766
12767       vex.v = *codep & 0x8;
12768       vex.mask_register_specifier = *codep & 0x7;
12769       vex.zeroing = *codep & 0x80;
12770
12771       need_vex = 1;
12772       need_vex_reg = 1;
12773       codep++;
12774       vindex = *codep++;
12775       dp = &evex_table[vex_table_index][vindex];
12776       end_codep = codep;
12777       FETCH_DATA (info, codep + 1);
12778       modrm.mod = (*codep >> 6) & 3;
12779       modrm.reg = (*codep >> 3) & 7;
12780       modrm.rm = *codep & 7;
12781
12782       /* Set vector length.  */
12783       if (modrm.mod == 3 && vex.b)
12784         vex.length = 512;
12785       else
12786         {
12787           switch (vex.ll)
12788             {
12789             case 0x0:
12790               vex.length = 128;
12791               break;
12792             case 0x1:
12793               vex.length = 256;
12794               break;
12795             case 0x2:
12796               vex.length = 512;
12797               break;
12798             default:
12799               return &bad_opcode;
12800             }
12801         }
12802       break;
12803
12804     case 0:
12805       dp = &bad_opcode;
12806       break;
12807
12808     default:
12809       abort ();
12810     }
12811
12812   if (dp->name != NULL)
12813     return dp;
12814   else
12815     return get_valid_dis386 (dp, info);
12816 }
12817
12818 static void
12819 get_sib (disassemble_info *info, int sizeflag)
12820 {
12821   /* If modrm.mod == 3, operand must be register.  */
12822   if (need_modrm
12823       && ((sizeflag & AFLAG) || address_mode == mode_64bit)
12824       && modrm.mod != 3
12825       && modrm.rm == 4)
12826     {
12827       FETCH_DATA (info, codep + 2);
12828       sib.index = (codep [1] >> 3) & 7;
12829       sib.scale = (codep [1] >> 6) & 3;
12830       sib.base = codep [1] & 7;
12831     }
12832 }
12833
12834 static int
12835 print_insn (bfd_vma pc, disassemble_info *info)
12836 {
12837   const struct dis386 *dp;
12838   int i;
12839   char *op_txt[MAX_OPERANDS];
12840   int needcomma;
12841   int sizeflag, orig_sizeflag;
12842   const char *p;
12843   struct dis_private priv;
12844   int prefix_length;
12845
12846   priv.orig_sizeflag = AFLAG | DFLAG;
12847   if ((info->mach & bfd_mach_i386_i386) != 0)
12848     address_mode = mode_32bit;
12849   else if (info->mach == bfd_mach_i386_i8086)
12850     {
12851       address_mode = mode_16bit;
12852       priv.orig_sizeflag = 0;
12853     }
12854   else
12855     address_mode = mode_64bit;
12856
12857   if (intel_syntax == (char) -1)
12858     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
12859
12860   for (p = info->disassembler_options; p != NULL; )
12861     {
12862       if (CONST_STRNEQ (p, "x86-64"))
12863         {
12864           address_mode = mode_64bit;
12865           priv.orig_sizeflag = AFLAG | DFLAG;
12866         }
12867       else if (CONST_STRNEQ (p, "i386"))
12868         {
12869           address_mode = mode_32bit;
12870           priv.orig_sizeflag = AFLAG | DFLAG;
12871         }
12872       else if (CONST_STRNEQ (p, "i8086"))
12873         {
12874           address_mode = mode_16bit;
12875           priv.orig_sizeflag = 0;
12876         }
12877       else if (CONST_STRNEQ (p, "intel"))
12878         {
12879           intel_syntax = 1;
12880           if (CONST_STRNEQ (p + 5, "-mnemonic"))
12881             intel_mnemonic = 1;
12882         }
12883       else if (CONST_STRNEQ (p, "att"))
12884         {
12885           intel_syntax = 0;
12886           if (CONST_STRNEQ (p + 3, "-mnemonic"))
12887             intel_mnemonic = 0;
12888         }
12889       else if (CONST_STRNEQ (p, "addr"))
12890         {
12891           if (address_mode == mode_64bit)
12892             {
12893               if (p[4] == '3' && p[5] == '2')
12894                 priv.orig_sizeflag &= ~AFLAG;
12895               else if (p[4] == '6' && p[5] == '4')
12896                 priv.orig_sizeflag |= AFLAG;
12897             }
12898           else
12899             {
12900               if (p[4] == '1' && p[5] == '6')
12901                 priv.orig_sizeflag &= ~AFLAG;
12902               else if (p[4] == '3' && p[5] == '2')
12903                 priv.orig_sizeflag |= AFLAG;
12904             }
12905         }
12906       else if (CONST_STRNEQ (p, "data"))
12907         {
12908           if (p[4] == '1' && p[5] == '6')
12909             priv.orig_sizeflag &= ~DFLAG;
12910           else if (p[4] == '3' && p[5] == '2')
12911             priv.orig_sizeflag |= DFLAG;
12912         }
12913       else if (CONST_STRNEQ (p, "suffix"))
12914         priv.orig_sizeflag |= SUFFIX_ALWAYS;
12915
12916       p = strchr (p, ',');
12917       if (p != NULL)
12918         p++;
12919     }
12920
12921   if (intel_syntax)
12922     {
12923       names64 = intel_names64;
12924       names32 = intel_names32;
12925       names16 = intel_names16;
12926       names8 = intel_names8;
12927       names8rex = intel_names8rex;
12928       names_seg = intel_names_seg;
12929       names_mm = intel_names_mm;
12930       names_bnd = intel_names_bnd;
12931       names_xmm = intel_names_xmm;
12932       names_ymm = intel_names_ymm;
12933       names_zmm = intel_names_zmm;
12934       index64 = intel_index64;
12935       index32 = intel_index32;
12936       names_mask = intel_names_mask;
12937       index16 = intel_index16;
12938       open_char = '[';
12939       close_char = ']';
12940       separator_char = '+';
12941       scale_char = '*';
12942     }
12943   else
12944     {
12945       names64 = att_names64;
12946       names32 = att_names32;
12947       names16 = att_names16;
12948       names8 = att_names8;
12949       names8rex = att_names8rex;
12950       names_seg = att_names_seg;
12951       names_mm = att_names_mm;
12952       names_bnd = att_names_bnd;
12953       names_xmm = att_names_xmm;
12954       names_ymm = att_names_ymm;
12955       names_zmm = att_names_zmm;
12956       index64 = att_index64;
12957       index32 = att_index32;
12958       names_mask = att_names_mask;
12959       index16 = att_index16;
12960       open_char = '(';
12961       close_char =  ')';
12962       separator_char = ',';
12963       scale_char = ',';
12964     }
12965
12966   /* The output looks better if we put 7 bytes on a line, since that
12967      puts most long word instructions on a single line.  Use 8 bytes
12968      for Intel L1OM.  */
12969   if ((info->mach & bfd_mach_l1om) != 0)
12970     info->bytes_per_line = 8;
12971   else
12972     info->bytes_per_line = 7;
12973
12974   info->private_data = &priv;
12975   priv.max_fetched = priv.the_buffer;
12976   priv.insn_start = pc;
12977
12978   obuf[0] = 0;
12979   for (i = 0; i < MAX_OPERANDS; ++i)
12980     {
12981       op_out[i][0] = 0;
12982       op_index[i] = -1;
12983     }
12984
12985   the_info = info;
12986   start_pc = pc;
12987   start_codep = priv.the_buffer;
12988   codep = priv.the_buffer;
12989
12990   if (OPCODES_SIGSETJMP (priv.bailout) != 0)
12991     {
12992       const char *name;
12993
12994       /* Getting here means we tried for data but didn't get it.  That
12995          means we have an incomplete instruction of some sort.  Just
12996          print the first byte as a prefix or a .byte pseudo-op.  */
12997       if (codep > priv.the_buffer)
12998         {
12999           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
13000           if (name != NULL)
13001             (*info->fprintf_func) (info->stream, "%s", name);
13002           else
13003             {
13004               /* Just print the first byte as a .byte instruction.  */
13005               (*info->fprintf_func) (info->stream, ".byte 0x%x",
13006                                      (unsigned int) priv.the_buffer[0]);
13007             }
13008
13009           return 1;
13010         }
13011
13012       return -1;
13013     }
13014
13015   obufp = obuf;
13016   sizeflag = priv.orig_sizeflag;
13017
13018   if (!ckprefix () || rex_used)
13019     {
13020       /* Too many prefixes or unused REX prefixes.  */
13021       for (i = 0;
13022            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
13023            i++)
13024         (*info->fprintf_func) (info->stream, "%s%s",
13025                                i == 0 ? "" : " ",
13026                                prefix_name (all_prefixes[i], sizeflag));
13027       return i;
13028     }
13029
13030   insn_codep = codep;
13031
13032   FETCH_DATA (info, codep + 1);
13033   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
13034
13035   if (((prefixes & PREFIX_FWAIT)
13036        && ((*codep < 0xd8) || (*codep > 0xdf))))
13037     {
13038       /* Handle prefixes before fwait.  */
13039       for (i = 0; i < fwait_prefix && all_prefixes[i];
13040            i++)
13041         (*info->fprintf_func) (info->stream, "%s ",
13042                                prefix_name (all_prefixes[i], sizeflag));
13043       (*info->fprintf_func) (info->stream, "fwait");
13044       return i + 1;
13045     }
13046
13047   if (*codep == 0x0f)
13048     {
13049       unsigned char threebyte;
13050       FETCH_DATA (info, codep + 2);
13051       threebyte = *++codep;
13052       dp = &dis386_twobyte[threebyte];
13053       need_modrm = twobyte_has_modrm[*codep];
13054       codep++;
13055     }
13056   else
13057     {
13058       dp = &dis386[*codep];
13059       need_modrm = onebyte_has_modrm[*codep];
13060       codep++;
13061     }
13062
13063   /* Save sizeflag for printing the extra prefixes later before updating
13064      it for mnemonic and operand processing.  The prefix names depend
13065      only on the address mode.  */
13066   orig_sizeflag = sizeflag;
13067   if (prefixes & PREFIX_ADDR)
13068     sizeflag ^= AFLAG;
13069   if ((prefixes & PREFIX_DATA))
13070     sizeflag ^= DFLAG;
13071
13072   end_codep = codep;
13073   if (need_modrm)
13074     {
13075       FETCH_DATA (info, codep + 1);
13076       modrm.mod = (*codep >> 6) & 3;
13077       modrm.reg = (*codep >> 3) & 7;
13078       modrm.rm = *codep & 7;
13079     }
13080
13081   need_vex = 0;
13082   need_vex_reg = 0;
13083   vex_w_done = 0;
13084   vex.evex = 0;
13085
13086   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
13087     {
13088       get_sib (info, sizeflag);
13089       dofloat (sizeflag);
13090     }
13091   else
13092     {
13093       dp = get_valid_dis386 (dp, info);
13094       if (dp != NULL && putop (dp->name, sizeflag) == 0)
13095         {
13096           get_sib (info, sizeflag);
13097           for (i = 0; i < MAX_OPERANDS; ++i)
13098             {
13099               obufp = op_out[i];
13100               op_ad = MAX_OPERANDS - 1 - i;
13101               if (dp->op[i].rtn)
13102                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
13103               /* For EVEX instruction after the last operand masking
13104                  should be printed.  */
13105               if (i == 0 && vex.evex)
13106                 {
13107                   /* Don't print {%k0}.  */
13108                   if (vex.mask_register_specifier)
13109                     {
13110                       oappend ("{");
13111                       oappend (names_mask[vex.mask_register_specifier]);
13112                       oappend ("}");
13113                     }
13114                   if (vex.zeroing)
13115                     oappend ("{z}");
13116                 }
13117             }
13118         }
13119     }
13120
13121   /* Check if the REX prefix is used.  */
13122   if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)
13123     all_prefixes[last_rex_prefix] = 0;
13124
13125   /* Check if the SEG prefix is used.  */
13126   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
13127                    | PREFIX_FS | PREFIX_GS)) != 0
13128       && (used_prefixes & active_seg_prefix) != 0)
13129     all_prefixes[last_seg_prefix] = 0;
13130
13131   /* Check if the ADDR prefix is used.  */
13132   if ((prefixes & PREFIX_ADDR) != 0
13133       && (used_prefixes & PREFIX_ADDR) != 0)
13134     all_prefixes[last_addr_prefix] = 0;
13135
13136   /* Check if the DATA prefix is used.  */
13137   if ((prefixes & PREFIX_DATA) != 0
13138       && (used_prefixes & PREFIX_DATA) != 0)
13139     all_prefixes[last_data_prefix] = 0;
13140
13141   /* Print the extra prefixes.  */
13142   prefix_length = 0;
13143   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
13144     if (all_prefixes[i])
13145       {
13146         const char *name;
13147         name = prefix_name (all_prefixes[i], orig_sizeflag);
13148         if (name == NULL)
13149           abort ();
13150         prefix_length += strlen (name) + 1;
13151         (*info->fprintf_func) (info->stream, "%s ", name);
13152       }
13153
13154   /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
13155      unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
13156      used by putop and MMX/SSE operand and may be overriden by the
13157      PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
13158      separately.  */
13159   if (dp->prefix_requirement == PREFIX_OPCODE
13160       && dp != &bad_opcode
13161       && (((prefixes
13162             & (PREFIX_REPZ | PREFIX_REPNZ)) != 0
13163            && (used_prefixes
13164                & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
13165           || ((((prefixes
13166                  & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
13167                 == PREFIX_DATA)
13168                && (used_prefixes & PREFIX_DATA) == 0))))
13169     {
13170       (*info->fprintf_func) (info->stream, "(bad)");
13171       return end_codep - priv.the_buffer;
13172     }
13173
13174   /* Check maximum code length.  */
13175   if ((codep - start_codep) > MAX_CODE_LENGTH)
13176     {
13177       (*info->fprintf_func) (info->stream, "(bad)");
13178       return MAX_CODE_LENGTH;
13179     }
13180
13181   obufp = mnemonicendp;
13182   for (i = strlen (obuf) + prefix_length; i < 6; i++)
13183     oappend (" ");
13184   oappend (" ");
13185   (*info->fprintf_func) (info->stream, "%s", obuf);
13186
13187   /* The enter and bound instructions are printed with operands in the same
13188      order as the intel book; everything else is printed in reverse order.  */
13189   if (intel_syntax || two_source_ops)
13190     {
13191       bfd_vma riprel;
13192
13193       for (i = 0; i < MAX_OPERANDS; ++i)
13194         op_txt[i] = op_out[i];
13195
13196       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
13197         {
13198           op_ad = op_index[i];
13199           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
13200           op_index[MAX_OPERANDS - 1 - i] = op_ad;
13201           riprel = op_riprel[i];
13202           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
13203           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
13204         }
13205     }
13206   else
13207     {
13208       for (i = 0; i < MAX_OPERANDS; ++i)
13209         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
13210     }
13211
13212   needcomma = 0;
13213   for (i = 0; i < MAX_OPERANDS; ++i)
13214     if (*op_txt[i])
13215       {
13216         if (needcomma)
13217           (*info->fprintf_func) (info->stream, ",");
13218         if (op_index[i] != -1 && !op_riprel[i])
13219           (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
13220         else
13221           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
13222         needcomma = 1;
13223       }
13224
13225   for (i = 0; i < MAX_OPERANDS; i++)
13226     if (op_index[i] != -1 && op_riprel[i])
13227       {
13228         (*info->fprintf_func) (info->stream, "        # ");
13229         (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep
13230                                                 + op_address[op_index[i]]), info);
13231         break;
13232       }
13233   return codep - priv.the_buffer;
13234 }
13235
13236 static const char *float_mem[] = {
13237   /* d8 */
13238   "fadd{s|}",
13239   "fmul{s|}",
13240   "fcom{s|}",
13241   "fcomp{s|}",
13242   "fsub{s|}",
13243   "fsubr{s|}",
13244   "fdiv{s|}",
13245   "fdivr{s|}",
13246   /* d9 */
13247   "fld{s|}",
13248   "(bad)",
13249   "fst{s|}",
13250   "fstp{s|}",
13251   "fldenvIC",
13252   "fldcw",
13253   "fNstenvIC",
13254   "fNstcw",
13255   /* da */
13256   "fiadd{l|}",
13257   "fimul{l|}",
13258   "ficom{l|}",
13259   "ficomp{l|}",
13260   "fisub{l|}",
13261   "fisubr{l|}",
13262   "fidiv{l|}",
13263   "fidivr{l|}",
13264   /* db */
13265   "fild{l|}",
13266   "fisttp{l|}",
13267   "fist{l|}",
13268   "fistp{l|}",
13269   "(bad)",
13270   "fld{t||t|}",
13271   "(bad)",
13272   "fstp{t||t|}",
13273   /* dc */
13274   "fadd{l|}",
13275   "fmul{l|}",
13276   "fcom{l|}",
13277   "fcomp{l|}",
13278   "fsub{l|}",
13279   "fsubr{l|}",
13280   "fdiv{l|}",
13281   "fdivr{l|}",
13282   /* dd */
13283   "fld{l|}",
13284   "fisttp{ll|}",
13285   "fst{l||}",
13286   "fstp{l|}",
13287   "frstorIC",
13288   "(bad)",
13289   "fNsaveIC",
13290   "fNstsw",
13291   /* de */
13292   "fiadd",
13293   "fimul",
13294   "ficom",
13295   "ficomp",
13296   "fisub",
13297   "fisubr",
13298   "fidiv",
13299   "fidivr",
13300   /* df */
13301   "fild",
13302   "fisttp",
13303   "fist",
13304   "fistp",
13305   "fbld",
13306   "fild{ll|}",
13307   "fbstp",
13308   "fistp{ll|}",
13309 };
13310
13311 static const unsigned char float_mem_mode[] = {
13312   /* d8 */
13313   d_mode,
13314   d_mode,
13315   d_mode,
13316   d_mode,
13317   d_mode,
13318   d_mode,
13319   d_mode,
13320   d_mode,
13321   /* d9 */
13322   d_mode,
13323   0,
13324   d_mode,
13325   d_mode,
13326   0,
13327   w_mode,
13328   0,
13329   w_mode,
13330   /* da */
13331   d_mode,
13332   d_mode,
13333   d_mode,
13334   d_mode,
13335   d_mode,
13336   d_mode,
13337   d_mode,
13338   d_mode,
13339   /* db */
13340   d_mode,
13341   d_mode,
13342   d_mode,
13343   d_mode,
13344   0,
13345   t_mode,
13346   0,
13347   t_mode,
13348   /* dc */
13349   q_mode,
13350   q_mode,
13351   q_mode,
13352   q_mode,
13353   q_mode,
13354   q_mode,
13355   q_mode,
13356   q_mode,
13357   /* dd */
13358   q_mode,
13359   q_mode,
13360   q_mode,
13361   q_mode,
13362   0,
13363   0,
13364   0,
13365   w_mode,
13366   /* de */
13367   w_mode,
13368   w_mode,
13369   w_mode,
13370   w_mode,
13371   w_mode,
13372   w_mode,
13373   w_mode,
13374   w_mode,
13375   /* df */
13376   w_mode,
13377   w_mode,
13378   w_mode,
13379   w_mode,
13380   t_mode,
13381   q_mode,
13382   t_mode,
13383   q_mode
13384 };
13385
13386 #define ST { OP_ST, 0 }
13387 #define STi { OP_STi, 0 }
13388
13389 #define FGRPd9_2 NULL, { { NULL, 0 } }, 0
13390 #define FGRPd9_4 NULL, { { NULL, 1 } }, 0
13391 #define FGRPd9_5 NULL, { { NULL, 2 } }, 0
13392 #define FGRPd9_6 NULL, { { NULL, 3 } }, 0
13393 #define FGRPd9_7 NULL, { { NULL, 4 } }, 0
13394 #define FGRPda_5 NULL, { { NULL, 5 } }, 0
13395 #define FGRPdb_4 NULL, { { NULL, 6 } }, 0
13396 #define FGRPde_3 NULL, { { NULL, 7 } }, 0
13397 #define FGRPdf_4 NULL, { { NULL, 8 } }, 0
13398
13399 static const struct dis386 float_reg[][8] = {
13400   /* d8 */
13401   {
13402     { "fadd",   { ST, STi }, 0 },
13403     { "fmul",   { ST, STi }, 0 },
13404     { "fcom",   { STi }, 0 },
13405     { "fcomp",  { STi }, 0 },
13406     { "fsub",   { ST, STi }, 0 },
13407     { "fsubr",  { ST, STi }, 0 },
13408     { "fdiv",   { ST, STi }, 0 },
13409     { "fdivr",  { ST, STi }, 0 },
13410   },
13411   /* d9 */
13412   {
13413     { "fld",    { STi }, 0 },
13414     { "fxch",   { STi }, 0 },
13415     { FGRPd9_2 },
13416     { Bad_Opcode },
13417     { FGRPd9_4 },
13418     { FGRPd9_5 },
13419     { FGRPd9_6 },
13420     { FGRPd9_7 },
13421   },
13422   /* da */
13423   {
13424     { "fcmovb", { ST, STi }, 0 },
13425     { "fcmove", { ST, STi }, 0 },
13426     { "fcmovbe",{ ST, STi }, 0 },
13427     { "fcmovu", { ST, STi }, 0 },
13428     { Bad_Opcode },
13429     { FGRPda_5 },
13430     { Bad_Opcode },
13431     { Bad_Opcode },
13432   },
13433   /* db */
13434   {
13435     { "fcmovnb",{ ST, STi }, 0 },
13436     { "fcmovne",{ ST, STi }, 0 },
13437     { "fcmovnbe",{ ST, STi }, 0 },
13438     { "fcmovnu",{ ST, STi }, 0 },
13439     { FGRPdb_4 },
13440     { "fucomi", { ST, STi }, 0 },
13441     { "fcomi",  { ST, STi }, 0 },
13442     { Bad_Opcode },
13443   },
13444   /* dc */
13445   {
13446     { "fadd",   { STi, ST }, 0 },
13447     { "fmul",   { STi, ST }, 0 },
13448     { Bad_Opcode },
13449     { Bad_Opcode },
13450     { "fsub!M", { STi, ST }, 0 },
13451     { "fsubM",  { STi, ST }, 0 },
13452     { "fdiv!M", { STi, ST }, 0 },
13453     { "fdivM",  { STi, ST }, 0 },
13454   },
13455   /* dd */
13456   {
13457     { "ffree",  { STi }, 0 },
13458     { Bad_Opcode },
13459     { "fst",    { STi }, 0 },
13460     { "fstp",   { STi }, 0 },
13461     { "fucom",  { STi }, 0 },
13462     { "fucomp", { STi }, 0 },
13463     { Bad_Opcode },
13464     { Bad_Opcode },
13465   },
13466   /* de */
13467   {
13468     { "faddp",  { STi, ST }, 0 },
13469     { "fmulp",  { STi, ST }, 0 },
13470     { Bad_Opcode },
13471     { FGRPde_3 },
13472     { "fsub!Mp", { STi, ST }, 0 },
13473     { "fsubMp", { STi, ST }, 0 },
13474     { "fdiv!Mp", { STi, ST }, 0 },
13475     { "fdivMp", { STi, ST }, 0 },
13476   },
13477   /* df */
13478   {
13479     { "ffreep", { STi }, 0 },
13480     { Bad_Opcode },
13481     { Bad_Opcode },
13482     { Bad_Opcode },
13483     { FGRPdf_4 },
13484     { "fucomip", { ST, STi }, 0 },
13485     { "fcomip", { ST, STi }, 0 },
13486     { Bad_Opcode },
13487   },
13488 };
13489
13490 static char *fgrps[][8] = {
13491   /* d9_2  0 */
13492   {
13493     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13494   },
13495
13496   /* d9_4  1 */
13497   {
13498     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
13499   },
13500
13501   /* d9_5  2 */
13502   {
13503     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
13504   },
13505
13506   /* d9_6  3 */
13507   {
13508     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
13509   },
13510
13511   /* d9_7  4 */
13512   {
13513     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
13514   },
13515
13516   /* da_5  5 */
13517   {
13518     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13519   },
13520
13521   /* db_4  6 */
13522   {
13523     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
13524     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
13525   },
13526
13527   /* de_3  7 */
13528   {
13529     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13530   },
13531
13532   /* df_4  8 */
13533   {
13534     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13535   },
13536 };
13537
13538 static void
13539 swap_operand (void)
13540 {
13541   mnemonicendp[0] = '.';
13542   mnemonicendp[1] = 's';
13543   mnemonicendp += 2;
13544 }
13545
13546 static void
13547 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
13548                int sizeflag ATTRIBUTE_UNUSED)
13549 {
13550   /* Skip mod/rm byte.  */
13551   MODRM_CHECK;
13552   codep++;
13553 }
13554
13555 static void
13556 dofloat (int sizeflag)
13557 {
13558   const struct dis386 *dp;
13559   unsigned char floatop;
13560
13561   floatop = codep[-1];
13562
13563   if (modrm.mod != 3)
13564     {
13565       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
13566
13567       putop (float_mem[fp_indx], sizeflag);
13568       obufp = op_out[0];
13569       op_ad = 2;
13570       OP_E (float_mem_mode[fp_indx], sizeflag);
13571       return;
13572     }
13573   /* Skip mod/rm byte.  */
13574   MODRM_CHECK;
13575   codep++;
13576
13577   dp = &float_reg[floatop - 0xd8][modrm.reg];
13578   if (dp->name == NULL)
13579     {
13580       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
13581
13582       /* Instruction fnstsw is only one with strange arg.  */
13583       if (floatop == 0xdf && codep[-1] == 0xe0)
13584         strcpy (op_out[0], names16[0]);
13585     }
13586   else
13587     {
13588       putop (dp->name, sizeflag);
13589
13590       obufp = op_out[0];
13591       op_ad = 2;
13592       if (dp->op[0].rtn)
13593         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
13594
13595       obufp = op_out[1];
13596       op_ad = 1;
13597       if (dp->op[1].rtn)
13598         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
13599     }
13600 }
13601
13602 /* Like oappend (below), but S is a string starting with '%'.
13603    In Intel syntax, the '%' is elided.  */
13604 static void
13605 oappend_maybe_intel (const char *s)
13606 {
13607   oappend (s + intel_syntax);
13608 }
13609
13610 static void
13611 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13612 {
13613   oappend_maybe_intel ("%st");
13614 }
13615
13616 static void
13617 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13618 {
13619   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
13620   oappend_maybe_intel (scratchbuf);
13621 }
13622
13623 /* Capital letters in template are macros.  */
13624 static int
13625 putop (const char *in_template, int sizeflag)
13626 {
13627   const char *p;
13628   int alt = 0;
13629   int cond = 1;
13630   unsigned int l = 0, len = 1;
13631   char last[4];
13632
13633 #define SAVE_LAST(c)                    \
13634   if (l < len && l < sizeof (last))     \
13635     last[l++] = c;                      \
13636   else                                  \
13637     abort ();
13638
13639   for (p = in_template; *p; p++)
13640     {
13641       switch (*p)
13642         {
13643         default:
13644           *obufp++ = *p;
13645           break;
13646         case '%':
13647           len++;
13648           break;
13649         case '!':
13650           cond = 0;
13651           break;
13652         case '{':
13653           alt = 0;
13654           if (intel_syntax)
13655             {
13656               while (*++p != '|')
13657                 if (*p == '}' || *p == '\0')
13658                   abort ();
13659             }
13660           /* Fall through.  */
13661         case 'I':
13662           alt = 1;
13663           continue;
13664         case '|':
13665           while (*++p != '}')
13666             {
13667               if (*p == '\0')
13668                 abort ();
13669             }
13670           break;
13671         case '}':
13672           break;
13673         case 'A':
13674           if (intel_syntax)
13675             break;
13676           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13677             *obufp++ = 'b';
13678           break;
13679         case 'B':
13680           if (l == 0 && len == 1)
13681             {
13682 case_B:
13683               if (intel_syntax)
13684                 break;
13685               if (sizeflag & SUFFIX_ALWAYS)
13686                 *obufp++ = 'b';
13687             }
13688           else
13689             {
13690               if (l != 1
13691                   || len != 2
13692                   || last[0] != 'L')
13693                 {
13694                   SAVE_LAST (*p);
13695                   break;
13696                 }
13697
13698               if (address_mode == mode_64bit
13699                   && !(prefixes & PREFIX_ADDR))
13700                 {
13701                   *obufp++ = 'a';
13702                   *obufp++ = 'b';
13703                   *obufp++ = 's';
13704                 }
13705
13706               goto case_B;
13707             }
13708           break;
13709         case 'C':
13710           if (intel_syntax && !alt)
13711             break;
13712           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
13713             {
13714               if (sizeflag & DFLAG)
13715                 *obufp++ = intel_syntax ? 'd' : 'l';
13716               else
13717                 *obufp++ = intel_syntax ? 'w' : 's';
13718               used_prefixes |= (prefixes & PREFIX_DATA);
13719             }
13720           break;
13721         case 'D':
13722           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
13723             break;
13724           USED_REX (REX_W);
13725           if (modrm.mod == 3)
13726             {
13727               if (rex & REX_W)
13728                 *obufp++ = 'q';
13729               else
13730                 {
13731                   if (sizeflag & DFLAG)
13732                     *obufp++ = intel_syntax ? 'd' : 'l';
13733                   else
13734                     *obufp++ = 'w';
13735                   used_prefixes |= (prefixes & PREFIX_DATA);
13736                 }
13737             }
13738           else
13739             *obufp++ = 'w';
13740           break;
13741         case 'E':               /* For jcxz/jecxz */
13742           if (address_mode == mode_64bit)
13743             {
13744               if (sizeflag & AFLAG)
13745                 *obufp++ = 'r';
13746               else
13747                 *obufp++ = 'e';
13748             }
13749           else
13750             if (sizeflag & AFLAG)
13751               *obufp++ = 'e';
13752           used_prefixes |= (prefixes & PREFIX_ADDR);
13753           break;
13754         case 'F':
13755           if (intel_syntax)
13756             break;
13757           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
13758             {
13759               if (sizeflag & AFLAG)
13760                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
13761               else
13762                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
13763               used_prefixes |= (prefixes & PREFIX_ADDR);
13764             }
13765           break;
13766         case 'G':
13767           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
13768             break;
13769           if ((rex & REX_W) || (sizeflag & DFLAG))
13770             *obufp++ = 'l';
13771           else
13772             *obufp++ = 'w';
13773           if (!(rex & REX_W))
13774             used_prefixes |= (prefixes & PREFIX_DATA);
13775           break;
13776         case 'H':
13777           if (intel_syntax)
13778             break;
13779           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
13780               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
13781             {
13782               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
13783               *obufp++ = ',';
13784               *obufp++ = 'p';
13785               if (prefixes & PREFIX_DS)
13786                 *obufp++ = 't';
13787               else
13788                 *obufp++ = 'n';
13789             }
13790           break;
13791         case 'J':
13792           if (intel_syntax)
13793             break;
13794           *obufp++ = 'l';
13795           break;
13796         case 'K':
13797           USED_REX (REX_W);
13798           if (rex & REX_W)
13799             *obufp++ = 'q';
13800           else
13801             *obufp++ = 'd';
13802           break;
13803         case 'Z':
13804           if (intel_syntax)
13805             break;
13806           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
13807             {
13808               *obufp++ = 'q';
13809               break;
13810             }
13811           /* Fall through.  */
13812           goto case_L;
13813         case 'L':
13814           if (l != 0 || len != 1)
13815             {
13816               SAVE_LAST (*p);
13817               break;
13818             }
13819 case_L:
13820           if (intel_syntax)
13821             break;
13822           if (sizeflag & SUFFIX_ALWAYS)
13823             *obufp++ = 'l';
13824           break;
13825         case 'M':
13826           if (intel_mnemonic != cond)
13827             *obufp++ = 'r';
13828           break;
13829         case 'N':
13830           if ((prefixes & PREFIX_FWAIT) == 0)
13831             *obufp++ = 'n';
13832           else
13833             used_prefixes |= PREFIX_FWAIT;
13834           break;
13835         case 'O':
13836           USED_REX (REX_W);
13837           if (rex & REX_W)
13838             *obufp++ = 'o';
13839           else if (intel_syntax && (sizeflag & DFLAG))
13840             *obufp++ = 'q';
13841           else
13842             *obufp++ = 'd';
13843           if (!(rex & REX_W))
13844             used_prefixes |= (prefixes & PREFIX_DATA);
13845           break;
13846         case 'T':
13847           if (!intel_syntax
13848               && address_mode == mode_64bit
13849               && ((sizeflag & DFLAG) || (rex & REX_W)))
13850             {
13851               *obufp++ = 'q';
13852               break;
13853             }
13854           /* Fall through.  */
13855           goto case_P;
13856         case 'P':
13857           if (l == 0 && len == 1)
13858             {
13859 case_P:
13860               if (intel_syntax)
13861                 {
13862                   if ((rex & REX_W) == 0
13863                       && (prefixes & PREFIX_DATA))
13864                     {
13865                       if ((sizeflag & DFLAG) == 0)
13866                         *obufp++ = 'w';
13867                       used_prefixes |= (prefixes & PREFIX_DATA);
13868                     }
13869                   break;
13870                 }
13871               if ((prefixes & PREFIX_DATA)
13872                   || (rex & REX_W)
13873                   || (sizeflag & SUFFIX_ALWAYS))
13874                 {
13875                   USED_REX (REX_W);
13876                   if (rex & REX_W)
13877                     *obufp++ = 'q';
13878                   else
13879                     {
13880                       if (sizeflag & DFLAG)
13881                         *obufp++ = 'l';
13882                       else
13883                         *obufp++ = 'w';
13884                       used_prefixes |= (prefixes & PREFIX_DATA);
13885                     }
13886                 }
13887             }
13888           else
13889             {
13890               if (l != 1 || len != 2 || last[0] != 'L')
13891                 {
13892                   SAVE_LAST (*p);
13893                   break;
13894                 }
13895
13896               if ((prefixes & PREFIX_DATA)
13897                   || (rex & REX_W)
13898                   || (sizeflag & SUFFIX_ALWAYS))
13899                 {
13900                   USED_REX (REX_W);
13901                   if (rex & REX_W)
13902                     *obufp++ = 'q';
13903                   else
13904                     {
13905                       if (sizeflag & DFLAG)
13906                         *obufp++ = intel_syntax ? 'd' : 'l';
13907                       else
13908                         *obufp++ = 'w';
13909                       used_prefixes |= (prefixes & PREFIX_DATA);
13910                     }
13911                 }
13912             }
13913           break;
13914         case 'U':
13915           if (intel_syntax)
13916             break;
13917           if (address_mode == mode_64bit
13918               && ((sizeflag & DFLAG) || (rex & REX_W)))
13919             {
13920               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13921                 *obufp++ = 'q';
13922               break;
13923             }
13924           /* Fall through.  */
13925           goto case_Q;
13926         case 'Q':
13927           if (l == 0 && len == 1)
13928             {
13929 case_Q:
13930               if (intel_syntax && !alt)
13931                 break;
13932               USED_REX (REX_W);
13933               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13934                 {
13935                   if (rex & REX_W)
13936                     *obufp++ = 'q';
13937                   else
13938                     {
13939                       if (sizeflag & DFLAG)
13940                         *obufp++ = intel_syntax ? 'd' : 'l';
13941                       else
13942                         *obufp++ = 'w';
13943                       used_prefixes |= (prefixes & PREFIX_DATA);
13944                     }
13945                 }
13946             }
13947           else
13948             {
13949               if (l != 1 || len != 2 || last[0] != 'L')
13950                 {
13951                   SAVE_LAST (*p);
13952                   break;
13953                 }
13954               if (intel_syntax
13955                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
13956                 break;
13957               if ((rex & REX_W))
13958                 {
13959                   USED_REX (REX_W);
13960                   *obufp++ = 'q';
13961                 }
13962               else
13963                 *obufp++ = 'l';
13964             }
13965           break;
13966         case 'R':
13967           USED_REX (REX_W);
13968           if (rex & REX_W)
13969             *obufp++ = 'q';
13970           else if (sizeflag & DFLAG)
13971             {
13972               if (intel_syntax)
13973                   *obufp++ = 'd';
13974               else
13975                   *obufp++ = 'l';
13976             }
13977           else
13978             *obufp++ = 'w';
13979           if (intel_syntax && !p[1]
13980               && ((rex & REX_W) || (sizeflag & DFLAG)))
13981             *obufp++ = 'e';
13982           if (!(rex & REX_W))
13983             used_prefixes |= (prefixes & PREFIX_DATA);
13984           break;
13985         case 'V':
13986           if (l == 0 && len == 1)
13987             {
13988               if (intel_syntax)
13989                 break;
13990               if (address_mode == mode_64bit
13991                   && ((sizeflag & DFLAG) || (rex & REX_W)))
13992                 {
13993                   if (sizeflag & SUFFIX_ALWAYS)
13994                     *obufp++ = 'q';
13995                   break;
13996                 }
13997             }
13998           else
13999             {
14000               if (l != 1
14001                   || len != 2
14002                   || last[0] != 'L')
14003                 {
14004                   SAVE_LAST (*p);
14005                   break;
14006                 }
14007
14008               if (rex & REX_W)
14009                 {
14010                   *obufp++ = 'a';
14011                   *obufp++ = 'b';
14012                   *obufp++ = 's';
14013                 }
14014             }
14015           /* Fall through.  */
14016           goto case_S;
14017         case 'S':
14018           if (l == 0 && len == 1)
14019             {
14020 case_S:
14021               if (intel_syntax)
14022                 break;
14023               if (sizeflag & SUFFIX_ALWAYS)
14024                 {
14025                   if (rex & REX_W)
14026                     *obufp++ = 'q';
14027                   else
14028                     {
14029                       if (sizeflag & DFLAG)
14030                         *obufp++ = 'l';
14031                       else
14032                         *obufp++ = 'w';
14033                       used_prefixes |= (prefixes & PREFIX_DATA);
14034                     }
14035                 }
14036             }
14037           else
14038             {
14039               if (l != 1
14040                   || len != 2
14041                   || last[0] != 'L')
14042                 {
14043                   SAVE_LAST (*p);
14044                   break;
14045                 }
14046
14047               if (address_mode == mode_64bit
14048                   && !(prefixes & PREFIX_ADDR))
14049                 {
14050                   *obufp++ = 'a';
14051                   *obufp++ = 'b';
14052                   *obufp++ = 's';
14053                 }
14054
14055               goto case_S;
14056             }
14057           break;
14058         case 'X':
14059           if (l != 0 || len != 1)
14060             {
14061               SAVE_LAST (*p);
14062               break;
14063             }
14064           if (need_vex && vex.prefix)
14065             {
14066               if (vex.prefix == DATA_PREFIX_OPCODE)
14067                 *obufp++ = 'd';
14068               else
14069                 *obufp++ = 's';
14070             }
14071           else
14072             {
14073               if (prefixes & PREFIX_DATA)
14074                 *obufp++ = 'd';
14075               else
14076                 *obufp++ = 's';
14077               used_prefixes |= (prefixes & PREFIX_DATA);
14078             }
14079           break;
14080         case 'Y':
14081           if (l == 0 && len == 1)
14082             {
14083               if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
14084                 break;
14085               if (rex & REX_W)
14086                 {
14087                   USED_REX (REX_W);
14088                   *obufp++ = 'q';
14089                 }
14090               break;
14091             }
14092           else
14093             {
14094               if (l != 1 || len != 2 || last[0] != 'X')
14095                 {
14096                   SAVE_LAST (*p);
14097                   break;
14098                 }
14099               if (!need_vex)
14100                 abort ();
14101               if (intel_syntax
14102                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
14103                 break;
14104               switch (vex.length)
14105                 {
14106                 case 128:
14107                   *obufp++ = 'x';
14108                   break;
14109                 case 256:
14110                   *obufp++ = 'y';
14111                   break;
14112                 default:
14113                   abort ();
14114                 }
14115             }
14116           break;
14117         case 'W':
14118           if (l == 0 && len == 1)
14119             {
14120               /* operand size flag for cwtl, cbtw */
14121               USED_REX (REX_W);
14122               if (rex & REX_W)
14123                 {
14124                   if (intel_syntax)
14125                     *obufp++ = 'd';
14126                   else
14127                     *obufp++ = 'l';
14128                 }
14129               else if (sizeflag & DFLAG)
14130                 *obufp++ = 'w';
14131               else
14132                 *obufp++ = 'b';
14133               if (!(rex & REX_W))
14134                 used_prefixes |= (prefixes & PREFIX_DATA);
14135             }
14136           else
14137             {
14138               if (l != 1
14139                   || len != 2
14140                   || (last[0] != 'X'
14141                       && last[0] != 'L'))
14142                 {
14143                   SAVE_LAST (*p);
14144                   break;
14145                 }
14146               if (!need_vex)
14147                 abort ();
14148               if (last[0] == 'X')
14149                 *obufp++ = vex.w ? 'd': 's';
14150               else
14151                 *obufp++ = vex.w ? 'q': 'd';
14152             }
14153           break;
14154         }
14155       alt = 0;
14156     }
14157   *obufp = 0;
14158   mnemonicendp = obufp;
14159   return 0;
14160 }
14161
14162 static void
14163 oappend (const char *s)
14164 {
14165   obufp = stpcpy (obufp, s);
14166 }
14167
14168 static void
14169 append_seg (void)
14170 {
14171   /* Only print the active segment register.  */
14172   if (!active_seg_prefix)
14173     return;
14174
14175   used_prefixes |= active_seg_prefix;
14176   switch (active_seg_prefix)
14177     {
14178     case PREFIX_CS:
14179       oappend_maybe_intel ("%cs:");
14180       break;
14181     case PREFIX_DS:
14182       oappend_maybe_intel ("%ds:");
14183       break;
14184     case PREFIX_SS:
14185       oappend_maybe_intel ("%ss:");
14186       break;
14187     case PREFIX_ES:
14188       oappend_maybe_intel ("%es:");
14189       break;
14190     case PREFIX_FS:
14191       oappend_maybe_intel ("%fs:");
14192       break;
14193     case PREFIX_GS:
14194       oappend_maybe_intel ("%gs:");
14195       break;
14196     default:
14197       break;
14198     }
14199 }
14200
14201 static void
14202 OP_indirE (int bytemode, int sizeflag)
14203 {
14204   if (!intel_syntax)
14205     oappend ("*");
14206   OP_E (bytemode, sizeflag);
14207 }
14208
14209 static void
14210 print_operand_value (char *buf, int hex, bfd_vma disp)
14211 {
14212   if (address_mode == mode_64bit)
14213     {
14214       if (hex)
14215         {
14216           char tmp[30];
14217           int i;
14218           buf[0] = '0';
14219           buf[1] = 'x';
14220           sprintf_vma (tmp, disp);
14221           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
14222           strcpy (buf + 2, tmp + i);
14223         }
14224       else
14225         {
14226           bfd_signed_vma v = disp;
14227           char tmp[30];
14228           int i;
14229           if (v < 0)
14230             {
14231               *(buf++) = '-';
14232               v = -disp;
14233               /* Check for possible overflow on 0x8000000000000000.  */
14234               if (v < 0)
14235                 {
14236                   strcpy (buf, "9223372036854775808");
14237                   return;
14238                 }
14239             }
14240           if (!v)
14241             {
14242               strcpy (buf, "0");
14243               return;
14244             }
14245
14246           i = 0;
14247           tmp[29] = 0;
14248           while (v)
14249             {
14250               tmp[28 - i] = (v % 10) + '0';
14251               v /= 10;
14252               i++;
14253             }
14254           strcpy (buf, tmp + 29 - i);
14255         }
14256     }
14257   else
14258     {
14259       if (hex)
14260         sprintf (buf, "0x%x", (unsigned int) disp);
14261       else
14262         sprintf (buf, "%d", (int) disp);
14263     }
14264 }
14265
14266 /* Put DISP in BUF as signed hex number.  */
14267
14268 static void
14269 print_displacement (char *buf, bfd_vma disp)
14270 {
14271   bfd_signed_vma val = disp;
14272   char tmp[30];
14273   int i, j = 0;
14274
14275   if (val < 0)
14276     {
14277       buf[j++] = '-';
14278       val = -disp;
14279
14280       /* Check for possible overflow.  */
14281       if (val < 0)
14282         {
14283           switch (address_mode)
14284             {
14285             case mode_64bit:
14286               strcpy (buf + j, "0x8000000000000000");
14287               break;
14288             case mode_32bit:
14289               strcpy (buf + j, "0x80000000");
14290               break;
14291             case mode_16bit:
14292               strcpy (buf + j, "0x8000");
14293               break;
14294             }
14295           return;
14296         }
14297     }
14298
14299   buf[j++] = '0';
14300   buf[j++] = 'x';
14301
14302   sprintf_vma (tmp, (bfd_vma) val);
14303   for (i = 0; tmp[i] == '0'; i++)
14304     continue;
14305   if (tmp[i] == '\0')
14306     i--;
14307   strcpy (buf + j, tmp + i);
14308 }
14309
14310 static void
14311 intel_operand_size (int bytemode, int sizeflag)
14312 {
14313   if (vex.evex
14314       && vex.b
14315       && (bytemode == x_mode
14316           || bytemode == evex_half_bcst_xmmq_mode))
14317     {
14318       if (vex.w)
14319         oappend ("QWORD PTR ");
14320       else
14321         oappend ("DWORD PTR ");
14322       return;
14323     }
14324   switch (bytemode)
14325     {
14326     case b_mode:
14327     case b_swap_mode:
14328     case dqb_mode:
14329     case db_mode:
14330       oappend ("BYTE PTR ");
14331       break;
14332     case w_mode:
14333     case dw_mode:
14334     case dqw_mode:
14335     case dqw_swap_mode:
14336       oappend ("WORD PTR ");
14337       break;
14338     case stack_v_mode:
14339       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14340         {
14341           oappend ("QWORD PTR ");
14342           break;
14343         }
14344       /* FALLTHRU */
14345     case v_mode:
14346     case v_swap_mode:
14347     case dq_mode:
14348       USED_REX (REX_W);
14349       if (rex & REX_W)
14350         oappend ("QWORD PTR ");
14351       else
14352         {
14353           if ((sizeflag & DFLAG) || bytemode == dq_mode)
14354             oappend ("DWORD PTR ");
14355           else
14356             oappend ("WORD PTR ");
14357           used_prefixes |= (prefixes & PREFIX_DATA);
14358         }
14359       break;
14360     case z_mode:
14361       if ((rex & REX_W) || (sizeflag & DFLAG))
14362         *obufp++ = 'D';
14363       oappend ("WORD PTR ");
14364       if (!(rex & REX_W))
14365         used_prefixes |= (prefixes & PREFIX_DATA);
14366       break;
14367     case a_mode:
14368       if (sizeflag & DFLAG)
14369         oappend ("QWORD PTR ");
14370       else
14371         oappend ("DWORD PTR ");
14372       used_prefixes |= (prefixes & PREFIX_DATA);
14373       break;
14374     case d_mode:
14375     case d_scalar_mode:
14376     case d_scalar_swap_mode:
14377     case d_swap_mode:
14378     case dqd_mode:
14379       oappend ("DWORD PTR ");
14380       break;
14381     case q_mode:
14382     case q_scalar_mode:
14383     case q_scalar_swap_mode:
14384     case q_swap_mode:
14385       oappend ("QWORD PTR ");
14386       break;
14387     case m_mode:
14388       if (address_mode == mode_64bit)
14389         oappend ("QWORD PTR ");
14390       else
14391         oappend ("DWORD PTR ");
14392       break;
14393     case f_mode:
14394       if (sizeflag & DFLAG)
14395         oappend ("FWORD PTR ");
14396       else
14397         oappend ("DWORD PTR ");
14398       used_prefixes |= (prefixes & PREFIX_DATA);
14399       break;
14400     case t_mode:
14401       oappend ("TBYTE PTR ");
14402       break;
14403     case x_mode:
14404     case x_swap_mode:
14405     case evex_x_gscat_mode:
14406     case evex_x_nobcst_mode:
14407       if (need_vex)
14408         {
14409           switch (vex.length)
14410             {
14411             case 128:
14412               oappend ("XMMWORD PTR ");
14413               break;
14414             case 256:
14415               oappend ("YMMWORD PTR ");
14416               break;
14417             case 512:
14418               oappend ("ZMMWORD PTR ");
14419               break;
14420             default:
14421               abort ();
14422             }
14423         }
14424       else
14425         oappend ("XMMWORD PTR ");
14426       break;
14427     case xmm_mode:
14428       oappend ("XMMWORD PTR ");
14429       break;
14430     case ymm_mode:
14431       oappend ("YMMWORD PTR ");
14432       break;
14433     case xmmq_mode:
14434     case evex_half_bcst_xmmq_mode:
14435       if (!need_vex)
14436         abort ();
14437
14438       switch (vex.length)
14439         {
14440         case 128:
14441           oappend ("QWORD PTR ");
14442           break;
14443         case 256:
14444           oappend ("XMMWORD PTR ");
14445           break;
14446         case 512:
14447           oappend ("YMMWORD PTR ");
14448           break;
14449         default:
14450           abort ();
14451         }
14452       break;
14453     case xmm_mb_mode:
14454       if (!need_vex)
14455         abort ();
14456
14457       switch (vex.length)
14458         {
14459         case 128:
14460         case 256:
14461         case 512:
14462           oappend ("BYTE PTR ");
14463           break;
14464         default:
14465           abort ();
14466         }
14467       break;
14468     case xmm_mw_mode:
14469       if (!need_vex)
14470         abort ();
14471
14472       switch (vex.length)
14473         {
14474         case 128:
14475         case 256:
14476         case 512:
14477           oappend ("WORD PTR ");
14478           break;
14479         default:
14480           abort ();
14481         }
14482       break;
14483     case xmm_md_mode:
14484       if (!need_vex)
14485         abort ();
14486
14487       switch (vex.length)
14488         {
14489         case 128:
14490         case 256:
14491         case 512:
14492           oappend ("DWORD PTR ");
14493           break;
14494         default:
14495           abort ();
14496         }
14497       break;
14498     case xmm_mq_mode:
14499       if (!need_vex)
14500         abort ();
14501
14502       switch (vex.length)
14503         {
14504         case 128:
14505         case 256:
14506         case 512:
14507           oappend ("QWORD PTR ");
14508           break;
14509         default:
14510           abort ();
14511         }
14512       break;
14513     case xmmdw_mode:
14514       if (!need_vex)
14515         abort ();
14516
14517       switch (vex.length)
14518         {
14519         case 128:
14520           oappend ("WORD PTR ");
14521           break;
14522         case 256:
14523           oappend ("DWORD PTR ");
14524           break;
14525         case 512:
14526           oappend ("QWORD PTR ");
14527           break;
14528         default:
14529           abort ();
14530         }
14531       break;
14532     case xmmqd_mode:
14533       if (!need_vex)
14534         abort ();
14535
14536       switch (vex.length)
14537         {
14538         case 128:
14539           oappend ("DWORD PTR ");
14540           break;
14541         case 256:
14542           oappend ("QWORD PTR ");
14543           break;
14544         case 512:
14545           oappend ("XMMWORD PTR ");
14546           break;
14547         default:
14548           abort ();
14549         }
14550       break;
14551     case ymmq_mode:
14552       if (!need_vex)
14553         abort ();
14554
14555       switch (vex.length)
14556         {
14557         case 128:
14558           oappend ("QWORD PTR ");
14559           break;
14560         case 256:
14561           oappend ("YMMWORD PTR ");
14562           break;
14563         case 512:
14564           oappend ("ZMMWORD PTR ");
14565           break;
14566         default:
14567           abort ();
14568         }
14569       break;
14570     case ymmxmm_mode:
14571       if (!need_vex)
14572         abort ();
14573
14574       switch (vex.length)
14575         {
14576         case 128:
14577         case 256:
14578           oappend ("XMMWORD PTR ");
14579           break;
14580         default:
14581           abort ();
14582         }
14583       break;
14584     case o_mode:
14585       oappend ("OWORD PTR ");
14586       break;
14587     case xmm_mdq_mode:
14588     case vex_w_dq_mode:
14589     case vex_scalar_w_dq_mode:
14590       if (!need_vex)
14591         abort ();
14592
14593       if (vex.w)
14594         oappend ("QWORD PTR ");
14595       else
14596         oappend ("DWORD PTR ");
14597       break;
14598     case vex_vsib_d_w_dq_mode:
14599     case vex_vsib_q_w_dq_mode:
14600       if (!need_vex)
14601         abort ();
14602
14603       if (!vex.evex)
14604         {
14605           if (vex.w)
14606             oappend ("QWORD PTR ");
14607           else
14608             oappend ("DWORD PTR ");
14609         }
14610       else
14611         {
14612           switch (vex.length)
14613             {
14614             case 128:
14615               oappend ("XMMWORD PTR ");
14616               break;
14617             case 256:
14618               oappend ("YMMWORD PTR ");
14619               break;
14620             case 512:
14621               oappend ("ZMMWORD PTR ");
14622               break;
14623             default:
14624               abort ();
14625             }
14626         }
14627       break;
14628     case vex_vsib_q_w_d_mode:
14629     case vex_vsib_d_w_d_mode:
14630       if (!need_vex || !vex.evex)
14631         abort ();
14632
14633       switch (vex.length)
14634         {
14635         case 128:
14636           oappend ("QWORD PTR ");
14637           break;
14638         case 256:
14639           oappend ("XMMWORD PTR ");
14640           break;
14641         case 512:
14642           oappend ("YMMWORD PTR ");
14643           break;
14644         default:
14645           abort ();
14646         }
14647
14648       break;
14649     case mask_bd_mode:
14650       if (!need_vex || vex.length != 128)
14651         abort ();
14652       if (vex.w)
14653         oappend ("DWORD PTR ");
14654       else
14655         oappend ("BYTE PTR ");
14656       break;
14657     case mask_mode:
14658       if (!need_vex)
14659         abort ();
14660       if (vex.w)
14661         oappend ("QWORD PTR ");
14662       else
14663         oappend ("WORD PTR ");
14664       break;
14665     case v_bnd_mode:
14666     default:
14667       break;
14668     }
14669 }
14670
14671 static void
14672 OP_E_register (int bytemode, int sizeflag)
14673 {
14674   int reg = modrm.rm;
14675   const char **names;
14676
14677   USED_REX (REX_B);
14678   if ((rex & REX_B))
14679     reg += 8;
14680
14681   if ((sizeflag & SUFFIX_ALWAYS)
14682       && (bytemode == b_swap_mode
14683           || bytemode == v_swap_mode
14684           || bytemode == dqw_swap_mode))
14685     swap_operand ();
14686
14687   switch (bytemode)
14688     {
14689     case b_mode:
14690     case b_swap_mode:
14691       USED_REX (0);
14692       if (rex)
14693         names = names8rex;
14694       else
14695         names = names8;
14696       break;
14697     case w_mode:
14698       names = names16;
14699       break;
14700     case d_mode:
14701     case dw_mode:
14702     case db_mode:
14703       names = names32;
14704       break;
14705     case q_mode:
14706       names = names64;
14707       break;
14708     case m_mode:
14709     case v_bnd_mode:
14710       names = address_mode == mode_64bit ? names64 : names32;
14711       break;
14712     case bnd_mode:
14713       names = names_bnd;
14714       break;
14715     case stack_v_mode:
14716       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14717         {
14718           names = names64;
14719           break;
14720         }
14721       bytemode = v_mode;
14722       /* FALLTHRU */
14723     case v_mode:
14724     case v_swap_mode:
14725     case dq_mode:
14726     case dqb_mode:
14727     case dqd_mode:
14728     case dqw_mode:
14729     case dqw_swap_mode:
14730       USED_REX (REX_W);
14731       if (rex & REX_W)
14732         names = names64;
14733       else
14734         {
14735           if ((sizeflag & DFLAG)
14736               || (bytemode != v_mode
14737                   && bytemode != v_swap_mode))
14738             names = names32;
14739           else
14740             names = names16;
14741           used_prefixes |= (prefixes & PREFIX_DATA);
14742         }
14743       break;
14744     case mask_bd_mode:
14745     case mask_mode:
14746       names = names_mask;
14747       break;
14748     case 0:
14749       return;
14750     default:
14751       oappend (INTERNAL_DISASSEMBLER_ERROR);
14752       return;
14753     }
14754   oappend (names[reg]);
14755 }
14756
14757 static void
14758 OP_E_memory (int bytemode, int sizeflag)
14759 {
14760   bfd_vma disp = 0;
14761   int add = (rex & REX_B) ? 8 : 0;
14762   int riprel = 0;
14763   int shift;
14764
14765   if (vex.evex)
14766     {
14767       /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0.  */
14768       if (vex.b
14769           && bytemode != x_mode
14770           && bytemode != xmmq_mode
14771           && bytemode != evex_half_bcst_xmmq_mode)
14772         {
14773           BadOp ();
14774           return;
14775         }
14776       switch (bytemode)
14777         {
14778         case dqw_mode:
14779         case dw_mode:
14780         case dqw_swap_mode:
14781           shift = 1;
14782           break;
14783         case dqb_mode:
14784         case db_mode:
14785           shift = 0;
14786           break;
14787         case vex_vsib_d_w_dq_mode:
14788         case vex_vsib_d_w_d_mode:
14789         case vex_vsib_q_w_dq_mode:
14790         case vex_vsib_q_w_d_mode:
14791         case evex_x_gscat_mode:
14792         case xmm_mdq_mode:
14793           shift = vex.w ? 3 : 2;
14794           break;
14795         case x_mode:
14796         case evex_half_bcst_xmmq_mode:
14797         case xmmq_mode:
14798           if (vex.b)
14799             {
14800               shift = vex.w ? 3 : 2;
14801               break;
14802             }
14803           /* Fall through if vex.b == 0.  */
14804         case xmmqd_mode:
14805         case xmmdw_mode:
14806         case ymmq_mode:
14807         case evex_x_nobcst_mode:
14808         case x_swap_mode:
14809           switch (vex.length)
14810             {
14811             case 128:
14812               shift = 4;
14813               break;
14814             case 256:
14815               shift = 5;
14816               break;
14817             case 512:
14818               shift = 6;
14819               break;
14820             default:
14821               abort ();
14822             }
14823           break;
14824         case ymm_mode:
14825           shift = 5;
14826           break;
14827         case xmm_mode:
14828           shift = 4;
14829           break;
14830         case xmm_mq_mode:
14831         case q_mode:
14832         case q_scalar_mode:
14833         case q_swap_mode:
14834         case q_scalar_swap_mode:
14835           shift = 3;
14836           break;
14837         case dqd_mode:
14838         case xmm_md_mode:
14839         case d_mode:
14840         case d_scalar_mode:
14841         case d_swap_mode:
14842         case d_scalar_swap_mode:
14843           shift = 2;
14844           break;
14845         case xmm_mw_mode:
14846           shift = 1;
14847           break;
14848         case xmm_mb_mode:
14849           shift = 0;
14850           break;
14851         default:
14852           abort ();
14853         }
14854       /* Make necessary corrections to shift for modes that need it.
14855          For these modes we currently have shift 4, 5 or 6 depending on
14856          vex.length (it corresponds to xmmword, ymmword or zmmword
14857          operand).  We might want to make it 3, 4 or 5 (e.g. for
14858          xmmq_mode).  In case of broadcast enabled the corrections
14859          aren't needed, as element size is always 32 or 64 bits.  */
14860       if (!vex.b
14861           && (bytemode == xmmq_mode
14862               || bytemode == evex_half_bcst_xmmq_mode))
14863         shift -= 1;
14864       else if (bytemode == xmmqd_mode)
14865         shift -= 2;
14866       else if (bytemode == xmmdw_mode)
14867         shift -= 3;
14868       else if (bytemode == ymmq_mode && vex.length == 128)
14869         shift -= 1;
14870     }
14871   else
14872     shift = 0;
14873
14874   USED_REX (REX_B);
14875   if (intel_syntax)
14876     intel_operand_size (bytemode, sizeflag);
14877   append_seg ();
14878
14879   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14880     {
14881       /* 32/64 bit address mode */
14882       int havedisp;
14883       int havesib;
14884       int havebase;
14885       int haveindex;
14886       int needindex;
14887       int base, rbase;
14888       int vindex = 0;
14889       int scale = 0;
14890       int addr32flag = !((sizeflag & AFLAG)
14891                          || bytemode == v_bnd_mode
14892                          || bytemode == bnd_mode);
14893       const char **indexes64 = names64;
14894       const char **indexes32 = names32;
14895
14896       havesib = 0;
14897       havebase = 1;
14898       haveindex = 0;
14899       base = modrm.rm;
14900
14901       if (base == 4)
14902         {
14903           havesib = 1;
14904           vindex = sib.index;
14905           USED_REX (REX_X);
14906           if (rex & REX_X)
14907             vindex += 8;
14908           switch (bytemode)
14909             {
14910             case vex_vsib_d_w_dq_mode:
14911             case vex_vsib_d_w_d_mode:
14912             case vex_vsib_q_w_dq_mode:
14913             case vex_vsib_q_w_d_mode:
14914               if (!need_vex)
14915                 abort ();
14916               if (vex.evex)
14917                 {
14918                   if (!vex.v)
14919                     vindex += 16;
14920                 }
14921
14922               haveindex = 1;
14923               switch (vex.length)
14924                 {
14925                 case 128:
14926                   indexes64 = indexes32 = names_xmm;
14927                   break;
14928                 case 256:
14929                   if (!vex.w
14930                       || bytemode == vex_vsib_q_w_dq_mode
14931                       || bytemode == vex_vsib_q_w_d_mode)
14932                     indexes64 = indexes32 = names_ymm;
14933                   else
14934                     indexes64 = indexes32 = names_xmm;
14935                   break;
14936                 case 512:
14937                   if (!vex.w
14938                       || bytemode == vex_vsib_q_w_dq_mode
14939                       || bytemode == vex_vsib_q_w_d_mode)
14940                     indexes64 = indexes32 = names_zmm;
14941                   else
14942                     indexes64 = indexes32 = names_ymm;
14943                   break;
14944                 default:
14945                   abort ();
14946                 }
14947               break;
14948             default:
14949               haveindex = vindex != 4;
14950               break;
14951             }
14952           scale = sib.scale;
14953           base = sib.base;
14954           codep++;
14955         }
14956       rbase = base + add;
14957
14958       switch (modrm.mod)
14959         {
14960         case 0:
14961           if (base == 5)
14962             {
14963               havebase = 0;
14964               if (address_mode == mode_64bit && !havesib)
14965                 riprel = 1;
14966               disp = get32s ();
14967             }
14968           break;
14969         case 1:
14970           FETCH_DATA (the_info, codep + 1);
14971           disp = *codep++;
14972           if ((disp & 0x80) != 0)
14973             disp -= 0x100;
14974           if (vex.evex && shift > 0)
14975             disp <<= shift;
14976           break;
14977         case 2:
14978           disp = get32s ();
14979           break;
14980         }
14981
14982       /* In 32bit mode, we need index register to tell [offset] from
14983          [eiz*1 + offset].  */
14984       needindex = (havesib
14985                    && !havebase
14986                    && !haveindex
14987                    && address_mode == mode_32bit);
14988       havedisp = (havebase
14989                   || needindex
14990                   || (havesib && (haveindex || scale != 0)));
14991
14992       if (!intel_syntax)
14993         if (modrm.mod != 0 || base == 5)
14994           {
14995             if (havedisp || riprel)
14996               print_displacement (scratchbuf, disp);
14997             else
14998               print_operand_value (scratchbuf, 1, disp);
14999             oappend (scratchbuf);
15000             if (riprel)
15001               {
15002                 set_op (disp, 1);
15003                 oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)");
15004               }
15005           }
15006
15007       if ((havebase || haveindex || riprel)
15008           && (bytemode != v_bnd_mode)
15009           && (bytemode != bnd_mode))
15010         used_prefixes |= PREFIX_ADDR;
15011
15012       if (havedisp || (intel_syntax && riprel))
15013         {
15014           *obufp++ = open_char;
15015           if (intel_syntax && riprel)
15016             {
15017               set_op (disp, 1);
15018               oappend (sizeflag & AFLAG ? "rip" : "eip");
15019             }
15020           *obufp = '\0';
15021           if (havebase)
15022             oappend (address_mode == mode_64bit && !addr32flag
15023                      ? names64[rbase] : names32[rbase]);
15024           if (havesib)
15025             {
15026               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
15027                  print index to tell base + index from base.  */
15028               if (scale != 0
15029                   || needindex
15030                   || haveindex
15031                   || (havebase && base != ESP_REG_NUM))
15032                 {
15033                   if (!intel_syntax || havebase)
15034                     {
15035                       *obufp++ = separator_char;
15036                       *obufp = '\0';
15037                     }
15038                   if (haveindex)
15039                     oappend (address_mode == mode_64bit && !addr32flag
15040                              ? indexes64[vindex] : indexes32[vindex]);
15041                   else
15042                     oappend (address_mode == mode_64bit && !addr32flag
15043                              ? index64 : index32);
15044
15045                   *obufp++ = scale_char;
15046                   *obufp = '\0';
15047                   sprintf (scratchbuf, "%d", 1 << scale);
15048                   oappend (scratchbuf);
15049                 }
15050             }
15051           if (intel_syntax
15052               && (disp || modrm.mod != 0 || base == 5))
15053             {
15054               if (!havedisp || (bfd_signed_vma) disp >= 0)
15055                 {
15056                   *obufp++ = '+';
15057                   *obufp = '\0';
15058                 }
15059               else if (modrm.mod != 1 && disp != -disp)
15060                 {
15061                   *obufp++ = '-';
15062                   *obufp = '\0';
15063                   disp = - (bfd_signed_vma) disp;
15064                 }
15065
15066               if (havedisp)
15067                 print_displacement (scratchbuf, disp);
15068               else
15069                 print_operand_value (scratchbuf, 1, disp);
15070               oappend (scratchbuf);
15071             }
15072
15073           *obufp++ = close_char;
15074           *obufp = '\0';
15075         }
15076       else if (intel_syntax)
15077         {
15078           if (modrm.mod != 0 || base == 5)
15079             {
15080               if (!active_seg_prefix)
15081                 {
15082                   oappend (names_seg[ds_reg - es_reg]);
15083                   oappend (":");
15084                 }
15085               print_operand_value (scratchbuf, 1, disp);
15086               oappend (scratchbuf);
15087             }
15088         }
15089     }
15090   else
15091     {
15092       /* 16 bit address mode */
15093       used_prefixes |= prefixes & PREFIX_ADDR;
15094       switch (modrm.mod)
15095         {
15096         case 0:
15097           if (modrm.rm == 6)
15098             {
15099               disp = get16 ();
15100               if ((disp & 0x8000) != 0)
15101                 disp -= 0x10000;
15102             }
15103           break;
15104         case 1:
15105           FETCH_DATA (the_info, codep + 1);
15106           disp = *codep++;
15107           if ((disp & 0x80) != 0)
15108             disp -= 0x100;
15109           break;
15110         case 2:
15111           disp = get16 ();
15112           if ((disp & 0x8000) != 0)
15113             disp -= 0x10000;
15114           break;
15115         }
15116
15117       if (!intel_syntax)
15118         if (modrm.mod != 0 || modrm.rm == 6)
15119           {
15120             print_displacement (scratchbuf, disp);
15121             oappend (scratchbuf);
15122           }
15123
15124       if (modrm.mod != 0 || modrm.rm != 6)
15125         {
15126           *obufp++ = open_char;
15127           *obufp = '\0';
15128           oappend (index16[modrm.rm]);
15129           if (intel_syntax
15130               && (disp || modrm.mod != 0 || modrm.rm == 6))
15131             {
15132               if ((bfd_signed_vma) disp >= 0)
15133                 {
15134                   *obufp++ = '+';
15135                   *obufp = '\0';
15136                 }
15137               else if (modrm.mod != 1)
15138                 {
15139                   *obufp++ = '-';
15140                   *obufp = '\0';
15141                   disp = - (bfd_signed_vma) disp;
15142                 }
15143
15144               print_displacement (scratchbuf, disp);
15145               oappend (scratchbuf);
15146             }
15147
15148           *obufp++ = close_char;
15149           *obufp = '\0';
15150         }
15151       else if (intel_syntax)
15152         {
15153           if (!active_seg_prefix)
15154             {
15155               oappend (names_seg[ds_reg - es_reg]);
15156               oappend (":");
15157             }
15158           print_operand_value (scratchbuf, 1, disp & 0xffff);
15159           oappend (scratchbuf);
15160         }
15161     }
15162   if (vex.evex && vex.b
15163       && (bytemode == x_mode
15164           || bytemode == xmmq_mode
15165           || bytemode == evex_half_bcst_xmmq_mode))
15166     {
15167       if (vex.w
15168           || bytemode == xmmq_mode
15169           || bytemode == evex_half_bcst_xmmq_mode)
15170         {
15171           switch (vex.length)
15172             {
15173             case 128:
15174               oappend ("{1to2}");
15175               break;
15176             case 256:
15177               oappend ("{1to4}");
15178               break;
15179             case 512:
15180               oappend ("{1to8}");
15181               break;
15182             default:
15183               abort ();
15184             }
15185         }
15186       else
15187         {
15188           switch (vex.length)
15189             {
15190             case 128:
15191               oappend ("{1to4}");
15192               break;
15193             case 256:
15194               oappend ("{1to8}");
15195               break;
15196             case 512:
15197               oappend ("{1to16}");
15198               break;
15199             default:
15200               abort ();
15201             }
15202         }
15203     }
15204 }
15205
15206 static void
15207 OP_E (int bytemode, int sizeflag)
15208 {
15209   /* Skip mod/rm byte.  */
15210   MODRM_CHECK;
15211   codep++;
15212
15213   if (modrm.mod == 3)
15214     OP_E_register (bytemode, sizeflag);
15215   else
15216     OP_E_memory (bytemode, sizeflag);
15217 }
15218
15219 static void
15220 OP_G (int bytemode, int sizeflag)
15221 {
15222   int add = 0;
15223   USED_REX (REX_R);
15224   if (rex & REX_R)
15225     add += 8;
15226   switch (bytemode)
15227     {
15228     case b_mode:
15229       USED_REX (0);
15230       if (rex)
15231         oappend (names8rex[modrm.reg + add]);
15232       else
15233         oappend (names8[modrm.reg + add]);
15234       break;
15235     case w_mode:
15236       oappend (names16[modrm.reg + add]);
15237       break;
15238     case d_mode:
15239     case db_mode:
15240     case dw_mode:
15241       oappend (names32[modrm.reg + add]);
15242       break;
15243     case q_mode:
15244       oappend (names64[modrm.reg + add]);
15245       break;
15246     case bnd_mode:
15247       oappend (names_bnd[modrm.reg]);
15248       break;
15249     case v_mode:
15250     case dq_mode:
15251     case dqb_mode:
15252     case dqd_mode:
15253     case dqw_mode:
15254     case dqw_swap_mode:
15255       USED_REX (REX_W);
15256       if (rex & REX_W)
15257         oappend (names64[modrm.reg + add]);
15258       else
15259         {
15260           if ((sizeflag & DFLAG) || bytemode != v_mode)
15261             oappend (names32[modrm.reg + add]);
15262           else
15263             oappend (names16[modrm.reg + add]);
15264           used_prefixes |= (prefixes & PREFIX_DATA);
15265         }
15266       break;
15267     case m_mode:
15268       if (address_mode == mode_64bit)
15269         oappend (names64[modrm.reg + add]);
15270       else
15271         oappend (names32[modrm.reg + add]);
15272       break;
15273     case mask_bd_mode:
15274     case mask_mode:
15275       oappend (names_mask[modrm.reg + add]);
15276       break;
15277     default:
15278       oappend (INTERNAL_DISASSEMBLER_ERROR);
15279       break;
15280     }
15281 }
15282
15283 static bfd_vma
15284 get64 (void)
15285 {
15286   bfd_vma x;
15287 #ifdef BFD64
15288   unsigned int a;
15289   unsigned int b;
15290
15291   FETCH_DATA (the_info, codep + 8);
15292   a = *codep++ & 0xff;
15293   a |= (*codep++ & 0xff) << 8;
15294   a |= (*codep++ & 0xff) << 16;
15295   a |= (*codep++ & 0xff) << 24;
15296   b = *codep++ & 0xff;
15297   b |= (*codep++ & 0xff) << 8;
15298   b |= (*codep++ & 0xff) << 16;
15299   b |= (*codep++ & 0xff) << 24;
15300   x = a + ((bfd_vma) b << 32);
15301 #else
15302   abort ();
15303   x = 0;
15304 #endif
15305   return x;
15306 }
15307
15308 static bfd_signed_vma
15309 get32 (void)
15310 {
15311   bfd_signed_vma x = 0;
15312
15313   FETCH_DATA (the_info, codep + 4);
15314   x = *codep++ & (bfd_signed_vma) 0xff;
15315   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15316   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15317   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15318   return x;
15319 }
15320
15321 static bfd_signed_vma
15322 get32s (void)
15323 {
15324   bfd_signed_vma x = 0;
15325
15326   FETCH_DATA (the_info, codep + 4);
15327   x = *codep++ & (bfd_signed_vma) 0xff;
15328   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15329   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15330   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15331
15332   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
15333
15334   return x;
15335 }
15336
15337 static int
15338 get16 (void)
15339 {
15340   int x = 0;
15341
15342   FETCH_DATA (the_info, codep + 2);
15343   x = *codep++ & 0xff;
15344   x |= (*codep++ & 0xff) << 8;
15345   return x;
15346 }
15347
15348 static void
15349 set_op (bfd_vma op, int riprel)
15350 {
15351   op_index[op_ad] = op_ad;
15352   if (address_mode == mode_64bit)
15353     {
15354       op_address[op_ad] = op;
15355       op_riprel[op_ad] = riprel;
15356     }
15357   else
15358     {
15359       /* Mask to get a 32-bit address.  */
15360       op_address[op_ad] = op & 0xffffffff;
15361       op_riprel[op_ad] = riprel & 0xffffffff;
15362     }
15363 }
15364
15365 static void
15366 OP_REG (int code, int sizeflag)
15367 {
15368   const char *s;
15369   int add;
15370
15371   switch (code)
15372     {
15373     case es_reg: case ss_reg: case cs_reg:
15374     case ds_reg: case fs_reg: case gs_reg:
15375       oappend (names_seg[code - es_reg]);
15376       return;
15377     }
15378
15379   USED_REX (REX_B);
15380   if (rex & REX_B)
15381     add = 8;
15382   else
15383     add = 0;
15384
15385   switch (code)
15386     {
15387     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15388     case sp_reg: case bp_reg: case si_reg: case di_reg:
15389       s = names16[code - ax_reg + add];
15390       break;
15391     case al_reg: case ah_reg: case cl_reg: case ch_reg:
15392     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15393       USED_REX (0);
15394       if (rex)
15395         s = names8rex[code - al_reg + add];
15396       else
15397         s = names8[code - al_reg];
15398       break;
15399     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
15400     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
15401       if (address_mode == mode_64bit
15402           && ((sizeflag & DFLAG) || (rex & REX_W)))
15403         {
15404           s = names64[code - rAX_reg + add];
15405           break;
15406         }
15407       code += eAX_reg - rAX_reg;
15408       /* Fall through.  */
15409     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15410     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15411       USED_REX (REX_W);
15412       if (rex & REX_W)
15413         s = names64[code - eAX_reg + add];
15414       else
15415         {
15416           if (sizeflag & DFLAG)
15417             s = names32[code - eAX_reg + add];
15418           else
15419             s = names16[code - eAX_reg + add];
15420           used_prefixes |= (prefixes & PREFIX_DATA);
15421         }
15422       break;
15423     default:
15424       s = INTERNAL_DISASSEMBLER_ERROR;
15425       break;
15426     }
15427   oappend (s);
15428 }
15429
15430 static void
15431 OP_IMREG (int code, int sizeflag)
15432 {
15433   const char *s;
15434
15435   switch (code)
15436     {
15437     case indir_dx_reg:
15438       if (intel_syntax)
15439         s = "dx";
15440       else
15441         s = "(%dx)";
15442       break;
15443     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15444     case sp_reg: case bp_reg: case si_reg: case di_reg:
15445       s = names16[code - ax_reg];
15446       break;
15447     case es_reg: case ss_reg: case cs_reg:
15448     case ds_reg: case fs_reg: case gs_reg:
15449       s = names_seg[code - es_reg];
15450       break;
15451     case al_reg: case ah_reg: case cl_reg: case ch_reg:
15452     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15453       USED_REX (0);
15454       if (rex)
15455         s = names8rex[code - al_reg];
15456       else
15457         s = names8[code - al_reg];
15458       break;
15459     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15460     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15461       USED_REX (REX_W);
15462       if (rex & REX_W)
15463         s = names64[code - eAX_reg];
15464       else
15465         {
15466           if (sizeflag & DFLAG)
15467             s = names32[code - eAX_reg];
15468           else
15469             s = names16[code - eAX_reg];
15470           used_prefixes |= (prefixes & PREFIX_DATA);
15471         }
15472       break;
15473     case z_mode_ax_reg:
15474       if ((rex & REX_W) || (sizeflag & DFLAG))
15475         s = *names32;
15476       else
15477         s = *names16;
15478       if (!(rex & REX_W))
15479         used_prefixes |= (prefixes & PREFIX_DATA);
15480       break;
15481     default:
15482       s = INTERNAL_DISASSEMBLER_ERROR;
15483       break;
15484     }
15485   oappend (s);
15486 }
15487
15488 static void
15489 OP_I (int bytemode, int sizeflag)
15490 {
15491   bfd_signed_vma op;
15492   bfd_signed_vma mask = -1;
15493
15494   switch (bytemode)
15495     {
15496     case b_mode:
15497       FETCH_DATA (the_info, codep + 1);
15498       op = *codep++;
15499       mask = 0xff;
15500       break;
15501     case q_mode:
15502       if (address_mode == mode_64bit)
15503         {
15504           op = get32s ();
15505           break;
15506         }
15507       /* Fall through.  */
15508     case v_mode:
15509       USED_REX (REX_W);
15510       if (rex & REX_W)
15511         op = get32s ();
15512       else
15513         {
15514           if (sizeflag & DFLAG)
15515             {
15516               op = get32 ();
15517               mask = 0xffffffff;
15518             }
15519           else
15520             {
15521               op = get16 ();
15522               mask = 0xfffff;
15523             }
15524           used_prefixes |= (prefixes & PREFIX_DATA);
15525         }
15526       break;
15527     case w_mode:
15528       mask = 0xfffff;
15529       op = get16 ();
15530       break;
15531     case const_1_mode:
15532       if (intel_syntax)
15533         oappend ("1");
15534       return;
15535     default:
15536       oappend (INTERNAL_DISASSEMBLER_ERROR);
15537       return;
15538     }
15539
15540   op &= mask;
15541   scratchbuf[0] = '$';
15542   print_operand_value (scratchbuf + 1, 1, op);
15543   oappend_maybe_intel (scratchbuf);
15544   scratchbuf[0] = '\0';
15545 }
15546
15547 static void
15548 OP_I64 (int bytemode, int sizeflag)
15549 {
15550   bfd_signed_vma op;
15551   bfd_signed_vma mask = -1;
15552
15553   if (address_mode != mode_64bit)
15554     {
15555       OP_I (bytemode, sizeflag);
15556       return;
15557     }
15558
15559   switch (bytemode)
15560     {
15561     case b_mode:
15562       FETCH_DATA (the_info, codep + 1);
15563       op = *codep++;
15564       mask = 0xff;
15565       break;
15566     case v_mode:
15567       USED_REX (REX_W);
15568       if (rex & REX_W)
15569         op = get64 ();
15570       else
15571         {
15572           if (sizeflag & DFLAG)
15573             {
15574               op = get32 ();
15575               mask = 0xffffffff;
15576             }
15577           else
15578             {
15579               op = get16 ();
15580               mask = 0xfffff;
15581             }
15582           used_prefixes |= (prefixes & PREFIX_DATA);
15583         }
15584       break;
15585     case w_mode:
15586       mask = 0xfffff;
15587       op = get16 ();
15588       break;
15589     default:
15590       oappend (INTERNAL_DISASSEMBLER_ERROR);
15591       return;
15592     }
15593
15594   op &= mask;
15595   scratchbuf[0] = '$';
15596   print_operand_value (scratchbuf + 1, 1, op);
15597   oappend_maybe_intel (scratchbuf);
15598   scratchbuf[0] = '\0';
15599 }
15600
15601 static void
15602 OP_sI (int bytemode, int sizeflag)
15603 {
15604   bfd_signed_vma op;
15605
15606   switch (bytemode)
15607     {
15608     case b_mode:
15609     case b_T_mode:
15610       FETCH_DATA (the_info, codep + 1);
15611       op = *codep++;
15612       if ((op & 0x80) != 0)
15613         op -= 0x100;
15614       if (bytemode == b_T_mode)
15615         {
15616           if (address_mode != mode_64bit
15617               || !((sizeflag & DFLAG) || (rex & REX_W)))
15618             {
15619               /* The operand-size prefix is overridden by a REX prefix.  */
15620               if ((sizeflag & DFLAG) || (rex & REX_W))
15621                 op &= 0xffffffff;
15622               else
15623                 op &= 0xffff;
15624           }
15625         }
15626       else
15627         {
15628           if (!(rex & REX_W))
15629             {
15630               if (sizeflag & DFLAG)
15631                 op &= 0xffffffff;
15632               else
15633                 op &= 0xffff;
15634             }
15635         }
15636       break;
15637     case v_mode:
15638       /* The operand-size prefix is overridden by a REX prefix.  */
15639       if ((sizeflag & DFLAG) || (rex & REX_W))
15640         op = get32s ();
15641       else
15642         op = get16 ();
15643       break;
15644     default:
15645       oappend (INTERNAL_DISASSEMBLER_ERROR);
15646       return;
15647     }
15648
15649   scratchbuf[0] = '$';
15650   print_operand_value (scratchbuf + 1, 1, op);
15651   oappend_maybe_intel (scratchbuf);
15652 }
15653
15654 static void
15655 OP_J (int bytemode, int sizeflag)
15656 {
15657   bfd_vma disp;
15658   bfd_vma mask = -1;
15659   bfd_vma segment = 0;
15660
15661   switch (bytemode)
15662     {
15663     case b_mode:
15664       FETCH_DATA (the_info, codep + 1);
15665       disp = *codep++;
15666       if ((disp & 0x80) != 0)
15667         disp -= 0x100;
15668       break;
15669     case v_mode:
15670       USED_REX (REX_W);
15671       if ((sizeflag & DFLAG) || (rex & REX_W))
15672         disp = get32s ();
15673       else
15674         {
15675           disp = get16 ();
15676           if ((disp & 0x8000) != 0)
15677             disp -= 0x10000;
15678           /* In 16bit mode, address is wrapped around at 64k within
15679              the same segment.  Otherwise, a data16 prefix on a jump
15680              instruction means that the pc is masked to 16 bits after
15681              the displacement is added!  */
15682           mask = 0xffff;
15683           if ((prefixes & PREFIX_DATA) == 0)
15684             segment = ((start_pc + codep - start_codep)
15685                        & ~((bfd_vma) 0xffff));
15686         }
15687       if (!(rex & REX_W))
15688         used_prefixes |= (prefixes & PREFIX_DATA);
15689       break;
15690     default:
15691       oappend (INTERNAL_DISASSEMBLER_ERROR);
15692       return;
15693     }
15694   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
15695   set_op (disp, 0);
15696   print_operand_value (scratchbuf, 1, disp);
15697   oappend (scratchbuf);
15698 }
15699
15700 static void
15701 OP_SEG (int bytemode, int sizeflag)
15702 {
15703   if (bytemode == w_mode)
15704     oappend (names_seg[modrm.reg]);
15705   else
15706     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
15707 }
15708
15709 static void
15710 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
15711 {
15712   int seg, offset;
15713
15714   if (sizeflag & DFLAG)
15715     {
15716       offset = get32 ();
15717       seg = get16 ();
15718     }
15719   else
15720     {
15721       offset = get16 ();
15722       seg = get16 ();
15723     }
15724   used_prefixes |= (prefixes & PREFIX_DATA);
15725   if (intel_syntax)
15726     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
15727   else
15728     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
15729   oappend (scratchbuf);
15730 }
15731
15732 static void
15733 OP_OFF (int bytemode, int sizeflag)
15734 {
15735   bfd_vma off;
15736
15737   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
15738     intel_operand_size (bytemode, sizeflag);
15739   append_seg ();
15740
15741   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
15742     off = get32 ();
15743   else
15744     off = get16 ();
15745
15746   if (intel_syntax)
15747     {
15748       if (!active_seg_prefix)
15749         {
15750           oappend (names_seg[ds_reg - es_reg]);
15751           oappend (":");
15752         }
15753     }
15754   print_operand_value (scratchbuf, 1, off);
15755   oappend (scratchbuf);
15756 }
15757
15758 static void
15759 OP_OFF64 (int bytemode, int sizeflag)
15760 {
15761   bfd_vma off;
15762
15763   if (address_mode != mode_64bit
15764       || (prefixes & PREFIX_ADDR))
15765     {
15766       OP_OFF (bytemode, sizeflag);
15767       return;
15768     }
15769
15770   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
15771     intel_operand_size (bytemode, sizeflag);
15772   append_seg ();
15773
15774   off = get64 ();
15775
15776   if (intel_syntax)
15777     {
15778       if (!active_seg_prefix)
15779         {
15780           oappend (names_seg[ds_reg - es_reg]);
15781           oappend (":");
15782         }
15783     }
15784   print_operand_value (scratchbuf, 1, off);
15785   oappend (scratchbuf);
15786 }
15787
15788 static void
15789 ptr_reg (int code, int sizeflag)
15790 {
15791   const char *s;
15792
15793   *obufp++ = open_char;
15794   used_prefixes |= (prefixes & PREFIX_ADDR);
15795   if (address_mode == mode_64bit)
15796     {
15797       if (!(sizeflag & AFLAG))
15798         s = names32[code - eAX_reg];
15799       else
15800         s = names64[code - eAX_reg];
15801     }
15802   else if (sizeflag & AFLAG)
15803     s = names32[code - eAX_reg];
15804   else
15805     s = names16[code - eAX_reg];
15806   oappend (s);
15807   *obufp++ = close_char;
15808   *obufp = 0;
15809 }
15810
15811 static void
15812 OP_ESreg (int code, int sizeflag)
15813 {
15814   if (intel_syntax)
15815     {
15816       switch (codep[-1])
15817         {
15818         case 0x6d:      /* insw/insl */
15819           intel_operand_size (z_mode, sizeflag);
15820           break;
15821         case 0xa5:      /* movsw/movsl/movsq */
15822         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15823         case 0xab:      /* stosw/stosl */
15824         case 0xaf:      /* scasw/scasl */
15825           intel_operand_size (v_mode, sizeflag);
15826           break;
15827         default:
15828           intel_operand_size (b_mode, sizeflag);
15829         }
15830     }
15831   oappend_maybe_intel ("%es:");
15832   ptr_reg (code, sizeflag);
15833 }
15834
15835 static void
15836 OP_DSreg (int code, int sizeflag)
15837 {
15838   if (intel_syntax)
15839     {
15840       switch (codep[-1])
15841         {
15842         case 0x6f:      /* outsw/outsl */
15843           intel_operand_size (z_mode, sizeflag);
15844           break;
15845         case 0xa5:      /* movsw/movsl/movsq */
15846         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15847         case 0xad:      /* lodsw/lodsl/lodsq */
15848           intel_operand_size (v_mode, sizeflag);
15849           break;
15850         default:
15851           intel_operand_size (b_mode, sizeflag);
15852         }
15853     }
15854   /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
15855      default segment register DS is printed.  */
15856   if (!active_seg_prefix)
15857     active_seg_prefix = PREFIX_DS;
15858   append_seg ();
15859   ptr_reg (code, sizeflag);
15860 }
15861
15862 static void
15863 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15864 {
15865   int add;
15866   if (rex & REX_R)
15867     {
15868       USED_REX (REX_R);
15869       add = 8;
15870     }
15871   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
15872     {
15873       all_prefixes[last_lock_prefix] = 0;
15874       used_prefixes |= PREFIX_LOCK;
15875       add = 8;
15876     }
15877   else
15878     add = 0;
15879   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
15880   oappend_maybe_intel (scratchbuf);
15881 }
15882
15883 static void
15884 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15885 {
15886   int add;
15887   USED_REX (REX_R);
15888   if (rex & REX_R)
15889     add = 8;
15890   else
15891     add = 0;
15892   if (intel_syntax)
15893     sprintf (scratchbuf, "db%d", modrm.reg + add);
15894   else
15895     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
15896   oappend (scratchbuf);
15897 }
15898
15899 static void
15900 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15901 {
15902   sprintf (scratchbuf, "%%tr%d", modrm.reg);
15903   oappend_maybe_intel (scratchbuf);
15904 }
15905
15906 static void
15907 OP_R (int bytemode, int sizeflag)
15908 {
15909   /* Skip mod/rm byte.  */
15910   MODRM_CHECK;
15911   codep++;
15912   OP_E_register (bytemode, sizeflag);
15913 }
15914
15915 static void
15916 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15917 {
15918   int reg = modrm.reg;
15919   const char **names;
15920
15921   used_prefixes |= (prefixes & PREFIX_DATA);
15922   if (prefixes & PREFIX_DATA)
15923     {
15924       names = names_xmm;
15925       USED_REX (REX_R);
15926       if (rex & REX_R)
15927         reg += 8;
15928     }
15929   else
15930     names = names_mm;
15931   oappend (names[reg]);
15932 }
15933
15934 static void
15935 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15936 {
15937   int reg = modrm.reg;
15938   const char **names;
15939
15940   USED_REX (REX_R);
15941   if (rex & REX_R)
15942     reg += 8;
15943   if (vex.evex)
15944     {
15945       if (!vex.r)
15946         reg += 16;
15947     }
15948
15949   if (need_vex
15950       && bytemode != xmm_mode
15951       && bytemode != xmmq_mode
15952       && bytemode != evex_half_bcst_xmmq_mode
15953       && bytemode != ymm_mode
15954       && bytemode != scalar_mode)
15955     {
15956       switch (vex.length)
15957         {
15958         case 128:
15959           names = names_xmm;
15960           break;
15961         case 256:
15962           if (vex.w
15963               || (bytemode != vex_vsib_q_w_dq_mode
15964                   && bytemode != vex_vsib_q_w_d_mode))
15965             names = names_ymm;
15966           else
15967             names = names_xmm;
15968           break;
15969         case 512:
15970           names = names_zmm;
15971           break;
15972         default:
15973           abort ();
15974         }
15975     }
15976   else if (bytemode == xmmq_mode
15977            || bytemode == evex_half_bcst_xmmq_mode)
15978     {
15979       switch (vex.length)
15980         {
15981         case 128:
15982         case 256:
15983           names = names_xmm;
15984           break;
15985         case 512:
15986           names = names_ymm;
15987           break;
15988         default:
15989           abort ();
15990         }
15991     }
15992   else if (bytemode == ymm_mode)
15993     names = names_ymm;
15994   else
15995     names = names_xmm;
15996   oappend (names[reg]);
15997 }
15998
15999 static void
16000 OP_EM (int bytemode, int sizeflag)
16001 {
16002   int reg;
16003   const char **names;
16004
16005   if (modrm.mod != 3)
16006     {
16007       if (intel_syntax
16008           && (bytemode == v_mode || bytemode == v_swap_mode))
16009         {
16010           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16011           used_prefixes |= (prefixes & PREFIX_DATA);
16012         }
16013       OP_E (bytemode, sizeflag);
16014       return;
16015     }
16016
16017   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
16018     swap_operand ();
16019
16020   /* Skip mod/rm byte.  */
16021   MODRM_CHECK;
16022   codep++;
16023   used_prefixes |= (prefixes & PREFIX_DATA);
16024   reg = modrm.rm;
16025   if (prefixes & PREFIX_DATA)
16026     {
16027       names = names_xmm;
16028       USED_REX (REX_B);
16029       if (rex & REX_B)
16030         reg += 8;
16031     }
16032   else
16033     names = names_mm;
16034   oappend (names[reg]);
16035 }
16036
16037 /* cvt* are the only instructions in sse2 which have
16038    both SSE and MMX operands and also have 0x66 prefix
16039    in their opcode. 0x66 was originally used to differentiate
16040    between SSE and MMX instruction(operands). So we have to handle the
16041    cvt* separately using OP_EMC and OP_MXC */
16042 static void
16043 OP_EMC (int bytemode, int sizeflag)
16044 {
16045   if (modrm.mod != 3)
16046     {
16047       if (intel_syntax && bytemode == v_mode)
16048         {
16049           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16050           used_prefixes |= (prefixes & PREFIX_DATA);
16051         }
16052       OP_E (bytemode, sizeflag);
16053       return;
16054     }
16055
16056   /* Skip mod/rm byte.  */
16057   MODRM_CHECK;
16058   codep++;
16059   used_prefixes |= (prefixes & PREFIX_DATA);
16060   oappend (names_mm[modrm.rm]);
16061 }
16062
16063 static void
16064 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16065 {
16066   used_prefixes |= (prefixes & PREFIX_DATA);
16067   oappend (names_mm[modrm.reg]);
16068 }
16069
16070 static void
16071 OP_EX (int bytemode, int sizeflag)
16072 {
16073   int reg;
16074   const char **names;
16075
16076   /* Skip mod/rm byte.  */
16077   MODRM_CHECK;
16078   codep++;
16079
16080   if (modrm.mod != 3)
16081     {
16082       OP_E_memory (bytemode, sizeflag);
16083       return;
16084     }
16085
16086   reg = modrm.rm;
16087   USED_REX (REX_B);
16088   if (rex & REX_B)
16089     reg += 8;
16090   if (vex.evex)
16091     {
16092       USED_REX (REX_X);
16093       if ((rex & REX_X))
16094         reg += 16;
16095     }
16096
16097   if ((sizeflag & SUFFIX_ALWAYS)
16098       && (bytemode == x_swap_mode
16099           || bytemode == d_swap_mode
16100           || bytemode == dqw_swap_mode
16101           || bytemode == d_scalar_swap_mode
16102           || bytemode == q_swap_mode
16103           || bytemode == q_scalar_swap_mode))
16104     swap_operand ();
16105
16106   if (need_vex
16107       && bytemode != xmm_mode
16108       && bytemode != xmmdw_mode
16109       && bytemode != xmmqd_mode
16110       && bytemode != xmm_mb_mode
16111       && bytemode != xmm_mw_mode
16112       && bytemode != xmm_md_mode
16113       && bytemode != xmm_mq_mode
16114       && bytemode != xmm_mdq_mode
16115       && bytemode != xmmq_mode
16116       && bytemode != evex_half_bcst_xmmq_mode
16117       && bytemode != ymm_mode
16118       && bytemode != d_scalar_mode
16119       && bytemode != d_scalar_swap_mode
16120       && bytemode != q_scalar_mode
16121       && bytemode != q_scalar_swap_mode
16122       && bytemode != vex_scalar_w_dq_mode)
16123     {
16124       switch (vex.length)
16125         {
16126         case 128:
16127           names = names_xmm;
16128           break;
16129         case 256:
16130           names = names_ymm;
16131           break;
16132         case 512:
16133           names = names_zmm;
16134           break;
16135         default:
16136           abort ();
16137         }
16138     }
16139   else if (bytemode == xmmq_mode
16140            || bytemode == evex_half_bcst_xmmq_mode)
16141     {
16142       switch (vex.length)
16143         {
16144         case 128:
16145         case 256:
16146           names = names_xmm;
16147           break;
16148         case 512:
16149           names = names_ymm;
16150           break;
16151         default:
16152           abort ();
16153         }
16154     }
16155   else if (bytemode == ymm_mode)
16156     names = names_ymm;
16157   else
16158     names = names_xmm;
16159   oappend (names[reg]);
16160 }
16161
16162 static void
16163 OP_MS (int bytemode, int sizeflag)
16164 {
16165   if (modrm.mod == 3)
16166     OP_EM (bytemode, sizeflag);
16167   else
16168     BadOp ();
16169 }
16170
16171 static void
16172 OP_XS (int bytemode, int sizeflag)
16173 {
16174   if (modrm.mod == 3)
16175     OP_EX (bytemode, sizeflag);
16176   else
16177     BadOp ();
16178 }
16179
16180 static void
16181 OP_M (int bytemode, int sizeflag)
16182 {
16183   if (modrm.mod == 3)
16184     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
16185     BadOp ();
16186   else
16187     OP_E (bytemode, sizeflag);
16188 }
16189
16190 static void
16191 OP_0f07 (int bytemode, int sizeflag)
16192 {
16193   if (modrm.mod != 3 || modrm.rm != 0)
16194     BadOp ();
16195   else
16196     OP_E (bytemode, sizeflag);
16197 }
16198
16199 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
16200    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
16201
16202 static void
16203 NOP_Fixup1 (int bytemode, int sizeflag)
16204 {
16205   if ((prefixes & PREFIX_DATA) != 0
16206       || (rex != 0
16207           && rex != 0x48
16208           && address_mode == mode_64bit))
16209     OP_REG (bytemode, sizeflag);
16210   else
16211     strcpy (obuf, "nop");
16212 }
16213
16214 static void
16215 NOP_Fixup2 (int bytemode, int sizeflag)
16216 {
16217   if ((prefixes & PREFIX_DATA) != 0
16218       || (rex != 0
16219           && rex != 0x48
16220           && address_mode == mode_64bit))
16221     OP_IMREG (bytemode, sizeflag);
16222 }
16223
16224 static const char *const Suffix3DNow[] = {
16225 /* 00 */        NULL,           NULL,           NULL,           NULL,
16226 /* 04 */        NULL,           NULL,           NULL,           NULL,
16227 /* 08 */        NULL,           NULL,           NULL,           NULL,
16228 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
16229 /* 10 */        NULL,           NULL,           NULL,           NULL,
16230 /* 14 */        NULL,           NULL,           NULL,           NULL,
16231 /* 18 */        NULL,           NULL,           NULL,           NULL,
16232 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
16233 /* 20 */        NULL,           NULL,           NULL,           NULL,
16234 /* 24 */        NULL,           NULL,           NULL,           NULL,
16235 /* 28 */        NULL,           NULL,           NULL,           NULL,
16236 /* 2C */        NULL,           NULL,           NULL,           NULL,
16237 /* 30 */        NULL,           NULL,           NULL,           NULL,
16238 /* 34 */        NULL,           NULL,           NULL,           NULL,
16239 /* 38 */        NULL,           NULL,           NULL,           NULL,
16240 /* 3C */        NULL,           NULL,           NULL,           NULL,
16241 /* 40 */        NULL,           NULL,           NULL,           NULL,
16242 /* 44 */        NULL,           NULL,           NULL,           NULL,
16243 /* 48 */        NULL,           NULL,           NULL,           NULL,
16244 /* 4C */        NULL,           NULL,           NULL,           NULL,
16245 /* 50 */        NULL,           NULL,           NULL,           NULL,
16246 /* 54 */        NULL,           NULL,           NULL,           NULL,
16247 /* 58 */        NULL,           NULL,           NULL,           NULL,
16248 /* 5C */        NULL,           NULL,           NULL,           NULL,
16249 /* 60 */        NULL,           NULL,           NULL,           NULL,
16250 /* 64 */        NULL,           NULL,           NULL,           NULL,
16251 /* 68 */        NULL,           NULL,           NULL,           NULL,
16252 /* 6C */        NULL,           NULL,           NULL,           NULL,
16253 /* 70 */        NULL,           NULL,           NULL,           NULL,
16254 /* 74 */        NULL,           NULL,           NULL,           NULL,
16255 /* 78 */        NULL,           NULL,           NULL,           NULL,
16256 /* 7C */        NULL,           NULL,           NULL,           NULL,
16257 /* 80 */        NULL,           NULL,           NULL,           NULL,
16258 /* 84 */        NULL,           NULL,           NULL,           NULL,
16259 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
16260 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
16261 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
16262 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
16263 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
16264 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
16265 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
16266 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
16267 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
16268 /* AC */        NULL,           NULL,           "pfacc",        NULL,
16269 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
16270 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
16271 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
16272 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
16273 /* C0 */        NULL,           NULL,           NULL,           NULL,
16274 /* C4 */        NULL,           NULL,           NULL,           NULL,
16275 /* C8 */        NULL,           NULL,           NULL,           NULL,
16276 /* CC */        NULL,           NULL,           NULL,           NULL,
16277 /* D0 */        NULL,           NULL,           NULL,           NULL,
16278 /* D4 */        NULL,           NULL,           NULL,           NULL,
16279 /* D8 */        NULL,           NULL,           NULL,           NULL,
16280 /* DC */        NULL,           NULL,           NULL,           NULL,
16281 /* E0 */        NULL,           NULL,           NULL,           NULL,
16282 /* E4 */        NULL,           NULL,           NULL,           NULL,
16283 /* E8 */        NULL,           NULL,           NULL,           NULL,
16284 /* EC */        NULL,           NULL,           NULL,           NULL,
16285 /* F0 */        NULL,           NULL,           NULL,           NULL,
16286 /* F4 */        NULL,           NULL,           NULL,           NULL,
16287 /* F8 */        NULL,           NULL,           NULL,           NULL,
16288 /* FC */        NULL,           NULL,           NULL,           NULL,
16289 };
16290
16291 static void
16292 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16293 {
16294   const char *mnemonic;
16295
16296   FETCH_DATA (the_info, codep + 1);
16297   /* AMD 3DNow! instructions are specified by an opcode suffix in the
16298      place where an 8-bit immediate would normally go.  ie. the last
16299      byte of the instruction.  */
16300   obufp = mnemonicendp;
16301   mnemonic = Suffix3DNow[*codep++ & 0xff];
16302   if (mnemonic)
16303     oappend (mnemonic);
16304   else
16305     {
16306       /* Since a variable sized modrm/sib chunk is between the start
16307          of the opcode (0x0f0f) and the opcode suffix, we need to do
16308          all the modrm processing first, and don't know until now that
16309          we have a bad opcode.  This necessitates some cleaning up.  */
16310       op_out[0][0] = '\0';
16311       op_out[1][0] = '\0';
16312       BadOp ();
16313     }
16314   mnemonicendp = obufp;
16315 }
16316
16317 static struct op simd_cmp_op[] =
16318 {
16319   { STRING_COMMA_LEN ("eq") },
16320   { STRING_COMMA_LEN ("lt") },
16321   { STRING_COMMA_LEN ("le") },
16322   { STRING_COMMA_LEN ("unord") },
16323   { STRING_COMMA_LEN ("neq") },
16324   { STRING_COMMA_LEN ("nlt") },
16325   { STRING_COMMA_LEN ("nle") },
16326   { STRING_COMMA_LEN ("ord") }
16327 };
16328
16329 static void
16330 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16331 {
16332   unsigned int cmp_type;
16333
16334   FETCH_DATA (the_info, codep + 1);
16335   cmp_type = *codep++ & 0xff;
16336   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
16337     {
16338       char suffix [3];
16339       char *p = mnemonicendp - 2;
16340       suffix[0] = p[0];
16341       suffix[1] = p[1];
16342       suffix[2] = '\0';
16343       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16344       mnemonicendp += simd_cmp_op[cmp_type].len;
16345     }
16346   else
16347     {
16348       /* We have a reserved extension byte.  Output it directly.  */
16349       scratchbuf[0] = '$';
16350       print_operand_value (scratchbuf + 1, 1, cmp_type);
16351       oappend_maybe_intel (scratchbuf);
16352       scratchbuf[0] = '\0';
16353     }
16354 }
16355
16356 static void
16357 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
16358           int sizeflag ATTRIBUTE_UNUSED)
16359 {
16360   /* mwait %eax,%ecx  */
16361   if (!intel_syntax)
16362     {
16363       const char **names = (address_mode == mode_64bit
16364                             ? names64 : names32);
16365       strcpy (op_out[0], names[0]);
16366       strcpy (op_out[1], names[1]);
16367       two_source_ops = 1;
16368     }
16369   /* Skip mod/rm byte.  */
16370   MODRM_CHECK;
16371   codep++;
16372 }
16373
16374 static void
16375 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
16376             int sizeflag ATTRIBUTE_UNUSED)
16377 {
16378   /* monitor %eax,%ecx,%edx"  */
16379   if (!intel_syntax)
16380     {
16381       const char **op1_names;
16382       const char **names = (address_mode == mode_64bit
16383                             ? names64 : names32);
16384
16385       if (!(prefixes & PREFIX_ADDR))
16386         op1_names = (address_mode == mode_16bit
16387                      ? names16 : names);
16388       else
16389         {
16390           /* Remove "addr16/addr32".  */
16391           all_prefixes[last_addr_prefix] = 0;
16392           op1_names = (address_mode != mode_32bit
16393                        ? names32 : names16);
16394           used_prefixes |= PREFIX_ADDR;
16395         }
16396       strcpy (op_out[0], op1_names[0]);
16397       strcpy (op_out[1], names[1]);
16398       strcpy (op_out[2], names[2]);
16399       two_source_ops = 1;
16400     }
16401   /* Skip mod/rm byte.  */
16402   MODRM_CHECK;
16403   codep++;
16404 }
16405
16406 static void
16407 BadOp (void)
16408 {
16409   /* Throw away prefixes and 1st. opcode byte.  */
16410   codep = insn_codep + 1;
16411   oappend ("(bad)");
16412 }
16413
16414 static void
16415 REP_Fixup (int bytemode, int sizeflag)
16416 {
16417   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
16418      lods and stos.  */
16419   if (prefixes & PREFIX_REPZ)
16420     all_prefixes[last_repz_prefix] = REP_PREFIX;
16421
16422   switch (bytemode)
16423     {
16424     case al_reg:
16425     case eAX_reg:
16426     case indir_dx_reg:
16427       OP_IMREG (bytemode, sizeflag);
16428       break;
16429     case eDI_reg:
16430       OP_ESreg (bytemode, sizeflag);
16431       break;
16432     case eSI_reg:
16433       OP_DSreg (bytemode, sizeflag);
16434       break;
16435     default:
16436       abort ();
16437       break;
16438     }
16439 }
16440
16441 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
16442    "bnd".  */
16443
16444 static void
16445 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16446 {
16447   if (prefixes & PREFIX_REPNZ)
16448     all_prefixes[last_repnz_prefix] = BND_PREFIX;
16449 }
16450
16451 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
16452    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
16453  */
16454
16455 static void
16456 HLE_Fixup1 (int bytemode, int sizeflag)
16457 {
16458   if (modrm.mod != 3
16459       && (prefixes & PREFIX_LOCK) != 0)
16460     {
16461       if (prefixes & PREFIX_REPZ)
16462         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16463       if (prefixes & PREFIX_REPNZ)
16464         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16465     }
16466
16467   OP_E (bytemode, sizeflag);
16468 }
16469
16470 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
16471    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
16472  */
16473
16474 static void
16475 HLE_Fixup2 (int bytemode, int sizeflag)
16476 {
16477   if (modrm.mod != 3)
16478     {
16479       if (prefixes & PREFIX_REPZ)
16480         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16481       if (prefixes & PREFIX_REPNZ)
16482         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16483     }
16484
16485   OP_E (bytemode, sizeflag);
16486 }
16487
16488 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
16489    "xrelease" for memory operand.  No check for LOCK prefix.   */
16490
16491 static void
16492 HLE_Fixup3 (int bytemode, int sizeflag)
16493 {
16494   if (modrm.mod != 3
16495       && last_repz_prefix > last_repnz_prefix
16496       && (prefixes & PREFIX_REPZ) != 0)
16497     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16498
16499   OP_E (bytemode, sizeflag);
16500 }
16501
16502 static void
16503 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
16504 {
16505   USED_REX (REX_W);
16506   if (rex & REX_W)
16507     {
16508       /* Change cmpxchg8b to cmpxchg16b.  */
16509       char *p = mnemonicendp - 2;
16510       mnemonicendp = stpcpy (p, "16b");
16511       bytemode = o_mode;
16512     }
16513   else if ((prefixes & PREFIX_LOCK) != 0)
16514     {
16515       if (prefixes & PREFIX_REPZ)
16516         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16517       if (prefixes & PREFIX_REPNZ)
16518         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16519     }
16520
16521   OP_M (bytemode, sizeflag);
16522 }
16523
16524 static void
16525 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
16526 {
16527   const char **names;
16528
16529   if (need_vex)
16530     {
16531       switch (vex.length)
16532         {
16533         case 128:
16534           names = names_xmm;
16535           break;
16536         case 256:
16537           names = names_ymm;
16538           break;
16539         default:
16540           abort ();
16541         }
16542     }
16543   else
16544     names = names_xmm;
16545   oappend (names[reg]);
16546 }
16547
16548 static void
16549 CRC32_Fixup (int bytemode, int sizeflag)
16550 {
16551   /* Add proper suffix to "crc32".  */
16552   char *p = mnemonicendp;
16553
16554   switch (bytemode)
16555     {
16556     case b_mode:
16557       if (intel_syntax)
16558         goto skip;
16559
16560       *p++ = 'b';
16561       break;
16562     case v_mode:
16563       if (intel_syntax)
16564         goto skip;
16565
16566       USED_REX (REX_W);
16567       if (rex & REX_W)
16568         *p++ = 'q';
16569       else
16570         {
16571           if (sizeflag & DFLAG)
16572             *p++ = 'l';
16573           else
16574             *p++ = 'w';
16575           used_prefixes |= (prefixes & PREFIX_DATA);
16576         }
16577       break;
16578     default:
16579       oappend (INTERNAL_DISASSEMBLER_ERROR);
16580       break;
16581     }
16582   mnemonicendp = p;
16583   *p = '\0';
16584
16585 skip:
16586   if (modrm.mod == 3)
16587     {
16588       int add;
16589
16590       /* Skip mod/rm byte.  */
16591       MODRM_CHECK;
16592       codep++;
16593
16594       USED_REX (REX_B);
16595       add = (rex & REX_B) ? 8 : 0;
16596       if (bytemode == b_mode)
16597         {
16598           USED_REX (0);
16599           if (rex)
16600             oappend (names8rex[modrm.rm + add]);
16601           else
16602             oappend (names8[modrm.rm + add]);
16603         }
16604       else
16605         {
16606           USED_REX (REX_W);
16607           if (rex & REX_W)
16608             oappend (names64[modrm.rm + add]);
16609           else if ((prefixes & PREFIX_DATA))
16610             oappend (names16[modrm.rm + add]);
16611           else
16612             oappend (names32[modrm.rm + add]);
16613         }
16614     }
16615   else
16616     OP_E (bytemode, sizeflag);
16617 }
16618
16619 static void
16620 FXSAVE_Fixup (int bytemode, int sizeflag)
16621 {
16622   /* Add proper suffix to "fxsave" and "fxrstor".  */
16623   USED_REX (REX_W);
16624   if (rex & REX_W)
16625     {
16626       char *p = mnemonicendp;
16627       *p++ = '6';
16628       *p++ = '4';
16629       *p = '\0';
16630       mnemonicendp = p;
16631     }
16632   OP_M (bytemode, sizeflag);
16633 }
16634
16635 /* Display the destination register operand for instructions with
16636    VEX. */
16637
16638 static void
16639 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16640 {
16641   int reg;
16642   const char **names;
16643
16644   if (!need_vex)
16645     abort ();
16646
16647   if (!need_vex_reg)
16648     return;
16649
16650   reg = vex.register_specifier;
16651   if (vex.evex)
16652     {
16653       if (!vex.v)
16654         reg += 16;
16655     }
16656
16657   if (bytemode == vex_scalar_mode)
16658     {
16659       oappend (names_xmm[reg]);
16660       return;
16661     }
16662
16663   switch (vex.length)
16664     {
16665     case 128:
16666       switch (bytemode)
16667         {
16668         case vex_mode:
16669         case vex128_mode:
16670         case vex_vsib_q_w_dq_mode:
16671         case vex_vsib_q_w_d_mode:
16672           names = names_xmm;
16673           break;
16674         case dq_mode:
16675           if (vex.w)
16676             names = names64;
16677           else
16678             names = names32;
16679           break;
16680         case mask_bd_mode:
16681         case mask_mode:
16682           names = names_mask;
16683           break;
16684         default:
16685           abort ();
16686           return;
16687         }
16688       break;
16689     case 256:
16690       switch (bytemode)
16691         {
16692         case vex_mode:
16693         case vex256_mode:
16694           names = names_ymm;
16695           break;
16696         case vex_vsib_q_w_dq_mode:
16697         case vex_vsib_q_w_d_mode:
16698           names = vex.w ? names_ymm : names_xmm;
16699           break;
16700         case mask_bd_mode:
16701         case mask_mode:
16702           names = names_mask;
16703           break;
16704         default:
16705           abort ();
16706           return;
16707         }
16708       break;
16709     case 512:
16710       names = names_zmm;
16711       break;
16712     default:
16713       abort ();
16714       break;
16715     }
16716   oappend (names[reg]);
16717 }
16718
16719 /* Get the VEX immediate byte without moving codep.  */
16720
16721 static unsigned char
16722 get_vex_imm8 (int sizeflag, int opnum)
16723 {
16724   int bytes_before_imm = 0;
16725
16726   if (modrm.mod != 3)
16727     {
16728       /* There are SIB/displacement bytes.  */
16729       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
16730         {
16731           /* 32/64 bit address mode */
16732           int base = modrm.rm;
16733
16734           /* Check SIB byte.  */
16735           if (base == 4)
16736             {
16737               FETCH_DATA (the_info, codep + 1);
16738               base = *codep & 7;
16739               /* When decoding the third source, don't increase
16740                  bytes_before_imm as this has already been incremented
16741                  by one in OP_E_memory while decoding the second
16742                  source operand.  */
16743               if (opnum == 0)
16744                 bytes_before_imm++;
16745             }
16746
16747           /* Don't increase bytes_before_imm when decoding the third source,
16748              it has already been incremented by OP_E_memory while decoding
16749              the second source operand.  */
16750           if (opnum == 0)
16751             {
16752               switch (modrm.mod)
16753                 {
16754                   case 0:
16755                     /* When modrm.rm == 5 or modrm.rm == 4 and base in
16756                        SIB == 5, there is a 4 byte displacement.  */
16757                     if (base != 5)
16758                       /* No displacement. */
16759                       break;
16760                   case 2:
16761                     /* 4 byte displacement.  */
16762                     bytes_before_imm += 4;
16763                     break;
16764                   case 1:
16765                     /* 1 byte displacement.  */
16766                     bytes_before_imm++;
16767                     break;
16768                 }
16769             }
16770         }
16771       else
16772         {
16773           /* 16 bit address mode */
16774           /* Don't increase bytes_before_imm when decoding the third source,
16775              it has already been incremented by OP_E_memory while decoding
16776              the second source operand.  */
16777           if (opnum == 0)
16778             {
16779               switch (modrm.mod)
16780                 {
16781                 case 0:
16782                   /* When modrm.rm == 6, there is a 2 byte displacement.  */
16783                   if (modrm.rm != 6)
16784                     /* No displacement. */
16785                     break;
16786                 case 2:
16787                   /* 2 byte displacement.  */
16788                   bytes_before_imm += 2;
16789                   break;
16790                 case 1:
16791                   /* 1 byte displacement: when decoding the third source,
16792                      don't increase bytes_before_imm as this has already
16793                      been incremented by one in OP_E_memory while decoding
16794                      the second source operand.  */
16795                   if (opnum == 0)
16796                     bytes_before_imm++;
16797
16798                   break;
16799                 }
16800             }
16801         }
16802     }
16803
16804   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
16805   return codep [bytes_before_imm];
16806 }
16807
16808 static void
16809 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
16810 {
16811   const char **names;
16812
16813   if (reg == -1 && modrm.mod != 3)
16814     {
16815       OP_E_memory (bytemode, sizeflag);
16816       return;
16817     }
16818   else
16819     {
16820       if (reg == -1)
16821         {
16822           reg = modrm.rm;
16823           USED_REX (REX_B);
16824           if (rex & REX_B)
16825             reg += 8;
16826         }
16827       else if (reg > 7 && address_mode != mode_64bit)
16828         BadOp ();
16829     }
16830
16831   switch (vex.length)
16832     {
16833     case 128:
16834       names = names_xmm;
16835       break;
16836     case 256:
16837       names = names_ymm;
16838       break;
16839     default:
16840       abort ();
16841     }
16842   oappend (names[reg]);
16843 }
16844
16845 static void
16846 OP_EX_VexImmW (int bytemode, int sizeflag)
16847 {
16848   int reg = -1;
16849   static unsigned char vex_imm8;
16850
16851   if (vex_w_done == 0)
16852     {
16853       vex_w_done = 1;
16854
16855       /* Skip mod/rm byte.  */
16856       MODRM_CHECK;
16857       codep++;
16858
16859       vex_imm8 = get_vex_imm8 (sizeflag, 0);
16860
16861       if (vex.w)
16862           reg = vex_imm8 >> 4;
16863
16864       OP_EX_VexReg (bytemode, sizeflag, reg);
16865     }
16866   else if (vex_w_done == 1)
16867     {
16868       vex_w_done = 2;
16869
16870       if (!vex.w)
16871           reg = vex_imm8 >> 4;
16872
16873       OP_EX_VexReg (bytemode, sizeflag, reg);
16874     }
16875   else
16876     {
16877       /* Output the imm8 directly.  */
16878       scratchbuf[0] = '$';
16879       print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
16880       oappend_maybe_intel (scratchbuf);
16881       scratchbuf[0] = '\0';
16882       codep++;
16883     }
16884 }
16885
16886 static void
16887 OP_Vex_2src (int bytemode, int sizeflag)
16888 {
16889   if (modrm.mod == 3)
16890     {
16891       int reg = modrm.rm;
16892       USED_REX (REX_B);
16893       if (rex & REX_B)
16894         reg += 8;
16895       oappend (names_xmm[reg]);
16896     }
16897   else
16898     {
16899       if (intel_syntax
16900           && (bytemode == v_mode || bytemode == v_swap_mode))
16901         {
16902           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16903           used_prefixes |= (prefixes & PREFIX_DATA);
16904         }
16905       OP_E (bytemode, sizeflag);
16906     }
16907 }
16908
16909 static void
16910 OP_Vex_2src_1 (int bytemode, int sizeflag)
16911 {
16912   if (modrm.mod == 3)
16913     {
16914       /* Skip mod/rm byte.   */
16915       MODRM_CHECK;
16916       codep++;
16917     }
16918
16919   if (vex.w)
16920     oappend (names_xmm[vex.register_specifier]);
16921   else
16922     OP_Vex_2src (bytemode, sizeflag);
16923 }
16924
16925 static void
16926 OP_Vex_2src_2 (int bytemode, int sizeflag)
16927 {
16928   if (vex.w)
16929     OP_Vex_2src (bytemode, sizeflag);
16930   else
16931     oappend (names_xmm[vex.register_specifier]);
16932 }
16933
16934 static void
16935 OP_EX_VexW (int bytemode, int sizeflag)
16936 {
16937   int reg = -1;
16938
16939   if (!vex_w_done)
16940     {
16941       vex_w_done = 1;
16942
16943       /* Skip mod/rm byte.  */
16944       MODRM_CHECK;
16945       codep++;
16946
16947       if (vex.w)
16948         reg = get_vex_imm8 (sizeflag, 0) >> 4;
16949     }
16950   else
16951     {
16952       if (!vex.w)
16953         reg = get_vex_imm8 (sizeflag, 1) >> 4;
16954     }
16955
16956   OP_EX_VexReg (bytemode, sizeflag, reg);
16957 }
16958
16959 static void
16960 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,
16961              int sizeflag ATTRIBUTE_UNUSED)
16962 {
16963   /* Skip the immediate byte and check for invalid bits.  */
16964   FETCH_DATA (the_info, codep + 1);
16965   if (*codep++ & 0xf)
16966     BadOp ();
16967 }
16968
16969 static void
16970 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16971 {
16972   int reg;
16973   const char **names;
16974
16975   FETCH_DATA (the_info, codep + 1);
16976   reg = *codep++;
16977
16978   if (bytemode != x_mode)
16979     abort ();
16980
16981   if (reg & 0xf)
16982       BadOp ();
16983
16984   reg >>= 4;
16985   if (reg > 7 && address_mode != mode_64bit)
16986     BadOp ();
16987
16988   switch (vex.length)
16989     {
16990     case 128:
16991       names = names_xmm;
16992       break;
16993     case 256:
16994       names = names_ymm;
16995       break;
16996     default:
16997       abort ();
16998     }
16999   oappend (names[reg]);
17000 }
17001
17002 static void
17003 OP_XMM_VexW (int bytemode, int sizeflag)
17004 {
17005   /* Turn off the REX.W bit since it is used for swapping operands
17006      now.  */
17007   rex &= ~REX_W;
17008   OP_XMM (bytemode, sizeflag);
17009 }
17010
17011 static void
17012 OP_EX_Vex (int bytemode, int sizeflag)
17013 {
17014   if (modrm.mod != 3)
17015     {
17016       if (vex.register_specifier != 0)
17017         BadOp ();
17018       need_vex_reg = 0;
17019     }
17020   OP_EX (bytemode, sizeflag);
17021 }
17022
17023 static void
17024 OP_XMM_Vex (int bytemode, int sizeflag)
17025 {
17026   if (modrm.mod != 3)
17027     {
17028       if (vex.register_specifier != 0)
17029         BadOp ();
17030       need_vex_reg = 0;
17031     }
17032   OP_XMM (bytemode, sizeflag);
17033 }
17034
17035 static void
17036 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17037 {
17038   switch (vex.length)
17039     {
17040     case 128:
17041       mnemonicendp = stpcpy (obuf, "vzeroupper");
17042       break;
17043     case 256:
17044       mnemonicendp = stpcpy (obuf, "vzeroall");
17045       break;
17046     default:
17047       abort ();
17048     }
17049 }
17050
17051 static struct op vex_cmp_op[] =
17052 {
17053   { STRING_COMMA_LEN ("eq") },
17054   { STRING_COMMA_LEN ("lt") },
17055   { STRING_COMMA_LEN ("le") },
17056   { STRING_COMMA_LEN ("unord") },
17057   { STRING_COMMA_LEN ("neq") },
17058   { STRING_COMMA_LEN ("nlt") },
17059   { STRING_COMMA_LEN ("nle") },
17060   { STRING_COMMA_LEN ("ord") },
17061   { STRING_COMMA_LEN ("eq_uq") },
17062   { STRING_COMMA_LEN ("nge") },
17063   { STRING_COMMA_LEN ("ngt") },
17064   { STRING_COMMA_LEN ("false") },
17065   { STRING_COMMA_LEN ("neq_oq") },
17066   { STRING_COMMA_LEN ("ge") },
17067   { STRING_COMMA_LEN ("gt") },
17068   { STRING_COMMA_LEN ("true") },
17069   { STRING_COMMA_LEN ("eq_os") },
17070   { STRING_COMMA_LEN ("lt_oq") },
17071   { STRING_COMMA_LEN ("le_oq") },
17072   { STRING_COMMA_LEN ("unord_s") },
17073   { STRING_COMMA_LEN ("neq_us") },
17074   { STRING_COMMA_LEN ("nlt_uq") },
17075   { STRING_COMMA_LEN ("nle_uq") },
17076   { STRING_COMMA_LEN ("ord_s") },
17077   { STRING_COMMA_LEN ("eq_us") },
17078   { STRING_COMMA_LEN ("nge_uq") },
17079   { STRING_COMMA_LEN ("ngt_uq") },
17080   { STRING_COMMA_LEN ("false_os") },
17081   { STRING_COMMA_LEN ("neq_os") },
17082   { STRING_COMMA_LEN ("ge_oq") },
17083   { STRING_COMMA_LEN ("gt_oq") },
17084   { STRING_COMMA_LEN ("true_us") },
17085 };
17086
17087 static void
17088 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17089 {
17090   unsigned int cmp_type;
17091
17092   FETCH_DATA (the_info, codep + 1);
17093   cmp_type = *codep++ & 0xff;
17094   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
17095     {
17096       char suffix [3];
17097       char *p = mnemonicendp - 2;
17098       suffix[0] = p[0];
17099       suffix[1] = p[1];
17100       suffix[2] = '\0';
17101       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
17102       mnemonicendp += vex_cmp_op[cmp_type].len;
17103     }
17104   else
17105     {
17106       /* We have a reserved extension byte.  Output it directly.  */
17107       scratchbuf[0] = '$';
17108       print_operand_value (scratchbuf + 1, 1, cmp_type);
17109       oappend_maybe_intel (scratchbuf);
17110       scratchbuf[0] = '\0';
17111     }
17112 }
17113
17114 static void
17115 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
17116              int sizeflag ATTRIBUTE_UNUSED)
17117 {
17118   unsigned int cmp_type;
17119
17120   if (!vex.evex)
17121     abort ();
17122
17123   FETCH_DATA (the_info, codep + 1);
17124   cmp_type = *codep++ & 0xff;
17125   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
17126      If it's the case, print suffix, otherwise - print the immediate.  */
17127   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
17128       && cmp_type != 3
17129       && cmp_type != 7)
17130     {
17131       char suffix [3];
17132       char *p = mnemonicendp - 2;
17133
17134       /* vpcmp* can have both one- and two-lettered suffix.  */
17135       if (p[0] == 'p')
17136         {
17137           p++;
17138           suffix[0] = p[0];
17139           suffix[1] = '\0';
17140         }
17141       else
17142         {
17143           suffix[0] = p[0];
17144           suffix[1] = p[1];
17145           suffix[2] = '\0';
17146         }
17147
17148       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
17149       mnemonicendp += simd_cmp_op[cmp_type].len;
17150     }
17151   else
17152     {
17153       /* We have a reserved extension byte.  Output it directly.  */
17154       scratchbuf[0] = '$';
17155       print_operand_value (scratchbuf + 1, 1, cmp_type);
17156       oappend_maybe_intel (scratchbuf);
17157       scratchbuf[0] = '\0';
17158     }
17159 }
17160
17161 static const struct op pclmul_op[] =
17162 {
17163   { STRING_COMMA_LEN ("lql") },
17164   { STRING_COMMA_LEN ("hql") },
17165   { STRING_COMMA_LEN ("lqh") },
17166   { STRING_COMMA_LEN ("hqh") }
17167 };
17168
17169 static void
17170 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
17171               int sizeflag ATTRIBUTE_UNUSED)
17172 {
17173   unsigned int pclmul_type;
17174
17175   FETCH_DATA (the_info, codep + 1);
17176   pclmul_type = *codep++ & 0xff;
17177   switch (pclmul_type)
17178     {
17179     case 0x10:
17180       pclmul_type = 2;
17181       break;
17182     case 0x11:
17183       pclmul_type = 3;
17184       break;
17185     default:
17186       break;
17187     }
17188   if (pclmul_type < ARRAY_SIZE (pclmul_op))
17189     {
17190       char suffix [4];
17191       char *p = mnemonicendp - 3;
17192       suffix[0] = p[0];
17193       suffix[1] = p[1];
17194       suffix[2] = p[2];
17195       suffix[3] = '\0';
17196       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
17197       mnemonicendp += pclmul_op[pclmul_type].len;
17198     }
17199   else
17200     {
17201       /* We have a reserved extension byte.  Output it directly.  */
17202       scratchbuf[0] = '$';
17203       print_operand_value (scratchbuf + 1, 1, pclmul_type);
17204       oappend_maybe_intel (scratchbuf);
17205       scratchbuf[0] = '\0';
17206     }
17207 }
17208
17209 static void
17210 MOVBE_Fixup (int bytemode, int sizeflag)
17211 {
17212   /* Add proper suffix to "movbe".  */
17213   char *p = mnemonicendp;
17214
17215   switch (bytemode)
17216     {
17217     case v_mode:
17218       if (intel_syntax)
17219         goto skip;
17220
17221       USED_REX (REX_W);
17222       if (sizeflag & SUFFIX_ALWAYS)
17223         {
17224           if (rex & REX_W)
17225             *p++ = 'q';
17226           else
17227             {
17228               if (sizeflag & DFLAG)
17229                 *p++ = 'l';
17230               else
17231                 *p++ = 'w';
17232               used_prefixes |= (prefixes & PREFIX_DATA);
17233             }
17234         }
17235       break;
17236     default:
17237       oappend (INTERNAL_DISASSEMBLER_ERROR);
17238       break;
17239     }
17240   mnemonicendp = p;
17241   *p = '\0';
17242
17243 skip:
17244   OP_M (bytemode, sizeflag);
17245 }
17246
17247 static void
17248 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17249 {
17250   int reg;
17251   const char **names;
17252
17253   /* Skip mod/rm byte.  */
17254   MODRM_CHECK;
17255   codep++;
17256
17257   if (vex.w)
17258     names = names64;
17259   else
17260     names = names32;
17261
17262   reg = modrm.rm;
17263   USED_REX (REX_B);
17264   if (rex & REX_B)
17265     reg += 8;
17266
17267   oappend (names[reg]);
17268 }
17269
17270 static void
17271 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17272 {
17273   const char **names;
17274
17275   if (vex.w)
17276     names = names64;
17277   else
17278     names = names32;
17279
17280   oappend (names[vex.register_specifier]);
17281 }
17282
17283 static void
17284 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17285 {
17286   if (!vex.evex
17287       || (bytemode != mask_mode && bytemode != mask_bd_mode))
17288     abort ();
17289
17290   USED_REX (REX_R);
17291   if ((rex & REX_R) != 0 || !vex.r)
17292     {
17293       BadOp ();
17294       return;
17295     }
17296
17297   oappend (names_mask [modrm.reg]);
17298 }
17299
17300 static void
17301 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17302 {
17303   if (!vex.evex
17304       || (bytemode != evex_rounding_mode
17305           && bytemode != evex_sae_mode))
17306     abort ();
17307   if (modrm.mod == 3 && vex.b)
17308     switch (bytemode)
17309       {
17310       case evex_rounding_mode:
17311         oappend (names_rounding[vex.ll]);
17312         break;
17313       case evex_sae_mode:
17314         oappend ("{sae}");
17315         break;
17316       default:
17317         break;
17318       }
17319 }