1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright (C) 1988-2020 Free Software Foundation, Inc.
4 This file is part of the GNU opcodes library.
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
24 modified by John Hassey (hassey@dg-rtp.dg.com)
25 x86-64 support added by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
28 /* The main tables describing the instructions is essentially a copy
29 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
30 Programmers Manual. Usually, there is a capital letter, followed
31 by a small letter. The capital letter tell the addressing mode,
32 and the small letter tells about the operand size. Refer to
33 the Intel manual for details. */
36 #include "disassemble.h"
38 #include "opcode/i386.h"
39 #include "libiberty.h"
40 #include "safe-ctype.h"
44 static int print_insn (bfd_vma
, disassemble_info
*);
45 static void dofloat (int);
46 static void OP_ST (int, int);
47 static void OP_STi (int, int);
48 static int putop (const char *, int);
49 static void oappend (const char *);
50 static void append_seg (void);
51 static void OP_indirE (int, int);
52 static void print_operand_value (char *, int, bfd_vma
);
53 static void OP_E_register (int, int);
54 static void OP_E_memory (int, int);
55 static void print_displacement (char *, bfd_vma
);
56 static void OP_E (int, int);
57 static void OP_G (int, int);
58 static bfd_vma
get64 (void);
59 static bfd_signed_vma
get32 (void);
60 static bfd_signed_vma
get32s (void);
61 static int get16 (void);
62 static void set_op (bfd_vma
, int);
63 static void OP_Skip_MODRM (int, int);
64 static void OP_REG (int, int);
65 static void OP_IMREG (int, int);
66 static void OP_I (int, int);
67 static void OP_I64 (int, int);
68 static void OP_sI (int, int);
69 static void OP_J (int, int);
70 static void OP_SEG (int, int);
71 static void OP_DIR (int, int);
72 static void OP_OFF (int, int);
73 static void OP_OFF64 (int, int);
74 static void ptr_reg (int, int);
75 static void OP_ESreg (int, int);
76 static void OP_DSreg (int, int);
77 static void OP_C (int, int);
78 static void OP_D (int, int);
79 static void OP_T (int, int);
80 static void OP_MMX (int, int);
81 static void OP_XMM (int, int);
82 static void OP_EM (int, int);
83 static void OP_EX (int, int);
84 static void OP_EMC (int,int);
85 static void OP_MXC (int,int);
86 static void OP_MS (int, int);
87 static void OP_XS (int, int);
88 static void OP_M (int, int);
89 static void OP_VEX (int, int);
90 static void OP_VexR (int, int);
91 static void OP_VexW (int, int);
92 static void OP_Rounding (int, int);
93 static void OP_REG_VexI4 (int, int);
94 static void OP_VexI4 (int, int);
95 static void PCLMUL_Fixup (int, int);
96 static void VPCMP_Fixup (int, int);
97 static void VPCOM_Fixup (int, int);
98 static void OP_0f07 (int, int);
99 static void OP_Monitor (int, int);
100 static void OP_Mwait (int, int);
101 static void NOP_Fixup1 (int, int);
102 static void NOP_Fixup2 (int, int);
103 static void OP_3DNowSuffix (int, int);
104 static void CMP_Fixup (int, int);
105 static void BadOp (void);
106 static void REP_Fixup (int, int);
107 static void SEP_Fixup (int, int);
108 static void BND_Fixup (int, int);
109 static void NOTRACK_Fixup (int, int);
110 static void HLE_Fixup1 (int, int);
111 static void HLE_Fixup2 (int, int);
112 static void HLE_Fixup3 (int, int);
113 static void CMPXCHG8B_Fixup (int, int);
114 static void XMM_Fixup (int, int);
115 static void FXSAVE_Fixup (int, int);
117 static void MOVSXD_Fixup (int, int);
119 static void OP_Mask (int, int);
122 /* Points to first byte not fetched. */
123 bfd_byte
*max_fetched
;
124 bfd_byte the_buffer
[MAX_MNEM_SIZE
];
127 OPCODES_SIGJMP_BUF bailout
;
137 enum address_mode address_mode
;
139 /* Flags for the prefixes for the current instruction. See below. */
142 /* REX prefix the current instruction. See below. */
144 /* Bits of REX we've already used. */
146 /* Mark parts used in the REX prefix. When we are testing for
147 empty prefix (for 8bit register REX extension), just mask it
148 out. Otherwise test for REX bit is excuse for existence of REX
149 only in case value is nonzero. */
150 #define USED_REX(value) \
155 rex_used |= (value) | REX_OPCODE; \
158 rex_used |= REX_OPCODE; \
161 /* Flags for prefixes which we somehow handled when printing the
162 current instruction. */
163 static int used_prefixes
;
165 /* Flags stored in PREFIXES. */
166 #define PREFIX_REPZ 1
167 #define PREFIX_REPNZ 2
168 #define PREFIX_LOCK 4
170 #define PREFIX_SS 0x10
171 #define PREFIX_DS 0x20
172 #define PREFIX_ES 0x40
173 #define PREFIX_FS 0x80
174 #define PREFIX_GS 0x100
175 #define PREFIX_DATA 0x200
176 #define PREFIX_ADDR 0x400
177 #define PREFIX_FWAIT 0x800
179 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
180 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
182 #define FETCH_DATA(info, addr) \
183 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
184 ? 1 : fetch_data ((info), (addr)))
187 fetch_data (struct disassemble_info
*info
, bfd_byte
*addr
)
190 struct dis_private
*priv
= (struct dis_private
*) info
->private_data
;
191 bfd_vma start
= priv
->insn_start
+ (priv
->max_fetched
- priv
->the_buffer
);
193 if (addr
<= priv
->the_buffer
+ MAX_MNEM_SIZE
)
194 status
= (*info
->read_memory_func
) (start
,
196 addr
- priv
->max_fetched
,
202 /* If we did manage to read at least one byte, then
203 print_insn_i386 will do something sensible. Otherwise, print
204 an error. We do that here because this is where we know
206 if (priv
->max_fetched
== priv
->the_buffer
)
207 (*info
->memory_error_func
) (status
, start
, info
);
208 OPCODES_SIGLONGJMP (priv
->bailout
, 1);
211 priv
->max_fetched
= addr
;
215 /* Possible values for prefix requirement. */
216 #define PREFIX_IGNORED_SHIFT 16
217 #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
218 #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
219 #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
220 #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
221 #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
223 /* Opcode prefixes. */
224 #define PREFIX_OPCODE (PREFIX_REPZ \
228 /* Prefixes ignored. */
229 #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \
230 | PREFIX_IGNORED_REPNZ \
231 | PREFIX_IGNORED_DATA)
233 #define XX { NULL, 0 }
234 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
236 #define Eb { OP_E, b_mode }
237 #define Ebnd { OP_E, bnd_mode }
238 #define EbS { OP_E, b_swap_mode }
239 #define EbndS { OP_E, bnd_swap_mode }
240 #define Ev { OP_E, v_mode }
241 #define Eva { OP_E, va_mode }
242 #define Ev_bnd { OP_E, v_bnd_mode }
243 #define EvS { OP_E, v_swap_mode }
244 #define Ed { OP_E, d_mode }
245 #define Edq { OP_E, dq_mode }
246 #define Edqw { OP_E, dqw_mode }
247 #define Edqb { OP_E, dqb_mode }
248 #define Edb { OP_E, db_mode }
249 #define Edw { OP_E, dw_mode }
250 #define Edqd { OP_E, dqd_mode }
251 #define Eq { OP_E, q_mode }
252 #define indirEv { OP_indirE, indir_v_mode }
253 #define indirEp { OP_indirE, f_mode }
254 #define stackEv { OP_E, stack_v_mode }
255 #define Em { OP_E, m_mode }
256 #define Ew { OP_E, w_mode }
257 #define M { OP_M, 0 } /* lea, lgdt, etc. */
258 #define Ma { OP_M, a_mode }
259 #define Mb { OP_M, b_mode }
260 #define Md { OP_M, d_mode }
261 #define Mo { OP_M, o_mode }
262 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
263 #define Mq { OP_M, q_mode }
264 #define Mv { OP_M, v_mode }
265 #define Mv_bnd { OP_M, v_bndmk_mode }
266 #define Mx { OP_M, x_mode }
267 #define Mxmm { OP_M, xmm_mode }
268 #define Gb { OP_G, b_mode }
269 #define Gbnd { OP_G, bnd_mode }
270 #define Gv { OP_G, v_mode }
271 #define Gd { OP_G, d_mode }
272 #define Gdq { OP_G, dq_mode }
273 #define Gm { OP_G, m_mode }
274 #define Gva { OP_G, va_mode }
275 #define Gw { OP_G, w_mode }
276 #define Ib { OP_I, b_mode }
277 #define sIb { OP_sI, b_mode } /* sign extened byte */
278 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
279 #define Iv { OP_I, v_mode }
280 #define sIv { OP_sI, v_mode }
281 #define Iv64 { OP_I64, v_mode }
282 #define Id { OP_I, d_mode }
283 #define Iw { OP_I, w_mode }
284 #define I1 { OP_I, const_1_mode }
285 #define Jb { OP_J, b_mode }
286 #define Jv { OP_J, v_mode }
287 #define Jdqw { OP_J, dqw_mode }
288 #define Cm { OP_C, m_mode }
289 #define Dm { OP_D, m_mode }
290 #define Td { OP_T, d_mode }
291 #define Skip_MODRM { OP_Skip_MODRM, 0 }
293 #define RMeAX { OP_REG, eAX_reg }
294 #define RMeBX { OP_REG, eBX_reg }
295 #define RMeCX { OP_REG, eCX_reg }
296 #define RMeDX { OP_REG, eDX_reg }
297 #define RMeSP { OP_REG, eSP_reg }
298 #define RMeBP { OP_REG, eBP_reg }
299 #define RMeSI { OP_REG, eSI_reg }
300 #define RMeDI { OP_REG, eDI_reg }
301 #define RMrAX { OP_REG, rAX_reg }
302 #define RMrBX { OP_REG, rBX_reg }
303 #define RMrCX { OP_REG, rCX_reg }
304 #define RMrDX { OP_REG, rDX_reg }
305 #define RMrSP { OP_REG, rSP_reg }
306 #define RMrBP { OP_REG, rBP_reg }
307 #define RMrSI { OP_REG, rSI_reg }
308 #define RMrDI { OP_REG, rDI_reg }
309 #define RMAL { OP_REG, al_reg }
310 #define RMCL { OP_REG, cl_reg }
311 #define RMDL { OP_REG, dl_reg }
312 #define RMBL { OP_REG, bl_reg }
313 #define RMAH { OP_REG, ah_reg }
314 #define RMCH { OP_REG, ch_reg }
315 #define RMDH { OP_REG, dh_reg }
316 #define RMBH { OP_REG, bh_reg }
317 #define RMAX { OP_REG, ax_reg }
318 #define RMDX { OP_REG, dx_reg }
320 #define eAX { OP_IMREG, eAX_reg }
321 #define AL { OP_IMREG, al_reg }
322 #define CL { OP_IMREG, cl_reg }
323 #define zAX { OP_IMREG, z_mode_ax_reg }
324 #define indirDX { OP_IMREG, indir_dx_reg }
326 #define Sw { OP_SEG, w_mode }
327 #define Sv { OP_SEG, v_mode }
328 #define Ap { OP_DIR, 0 }
329 #define Ob { OP_OFF64, b_mode }
330 #define Ov { OP_OFF64, v_mode }
331 #define Xb { OP_DSreg, eSI_reg }
332 #define Xv { OP_DSreg, eSI_reg }
333 #define Xz { OP_DSreg, eSI_reg }
334 #define Yb { OP_ESreg, eDI_reg }
335 #define Yv { OP_ESreg, eDI_reg }
336 #define DSBX { OP_DSreg, eBX_reg }
338 #define es { OP_REG, es_reg }
339 #define ss { OP_REG, ss_reg }
340 #define cs { OP_REG, cs_reg }
341 #define ds { OP_REG, ds_reg }
342 #define fs { OP_REG, fs_reg }
343 #define gs { OP_REG, gs_reg }
345 #define MX { OP_MMX, 0 }
346 #define XM { OP_XMM, 0 }
347 #define XMScalar { OP_XMM, scalar_mode }
348 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
349 #define XMM { OP_XMM, xmm_mode }
350 #define TMM { OP_XMM, tmm_mode }
351 #define XMxmmq { OP_XMM, xmmq_mode }
352 #define EM { OP_EM, v_mode }
353 #define EMS { OP_EM, v_swap_mode }
354 #define EMd { OP_EM, d_mode }
355 #define EMx { OP_EM, x_mode }
356 #define EXbwUnit { OP_EX, bw_unit_mode }
357 #define EXw { OP_EX, w_mode }
358 #define EXd { OP_EX, d_mode }
359 #define EXdS { OP_EX, d_swap_mode }
360 #define EXq { OP_EX, q_mode }
361 #define EXqS { OP_EX, q_swap_mode }
362 #define EXx { OP_EX, x_mode }
363 #define EXxS { OP_EX, x_swap_mode }
364 #define EXxmm { OP_EX, xmm_mode }
365 #define EXymm { OP_EX, ymm_mode }
366 #define EXtmm { OP_EX, tmm_mode }
367 #define EXxmmq { OP_EX, xmmq_mode }
368 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
369 #define EXxmm_mb { OP_EX, xmm_mb_mode }
370 #define EXxmm_mw { OP_EX, xmm_mw_mode }
371 #define EXxmm_md { OP_EX, xmm_md_mode }
372 #define EXxmm_mq { OP_EX, xmm_mq_mode }
373 #define EXxmmdw { OP_EX, xmmdw_mode }
374 #define EXxmmqd { OP_EX, xmmqd_mode }
375 #define EXymmq { OP_EX, ymmq_mode }
376 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
377 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
378 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
379 #define MS { OP_MS, v_mode }
380 #define XS { OP_XS, v_mode }
381 #define EMCq { OP_EMC, q_mode }
382 #define MXC { OP_MXC, 0 }
383 #define OPSUF { OP_3DNowSuffix, 0 }
384 #define SEP { SEP_Fixup, 0 }
385 #define CMP { CMP_Fixup, 0 }
386 #define XMM0 { XMM_Fixup, 0 }
387 #define FXSAVE { FXSAVE_Fixup, 0 }
389 #define Vex { OP_VEX, vex_mode }
390 #define VexW { OP_VexW, vex_mode }
391 #define VexScalar { OP_VEX, vex_scalar_mode }
392 #define VexScalarR { OP_VexR, vex_scalar_mode }
393 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
394 #define VexGdq { OP_VEX, dq_mode }
395 #define VexTmm { OP_VEX, tmm_mode }
396 #define XMVexI4 { OP_REG_VexI4, x_mode }
397 #define XMVexScalarI4 { OP_REG_VexI4, scalar_mode }
398 #define VexI4 { OP_VexI4, 0 }
399 #define PCLMUL { PCLMUL_Fixup, 0 }
400 #define VPCMP { VPCMP_Fixup, 0 }
401 #define VPCOM { VPCOM_Fixup, 0 }
403 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
404 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
405 #define EXxEVexS { OP_Rounding, evex_sae_mode }
407 #define XMask { OP_Mask, mask_mode }
408 #define MaskG { OP_G, mask_mode }
409 #define MaskE { OP_E, mask_mode }
410 #define MaskBDE { OP_E, mask_bd_mode }
411 #define MaskVex { OP_VEX, mask_mode }
413 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
414 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
415 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
416 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
418 #define MVexSIBMEM { OP_M, vex_sibmem_mode }
420 /* Used handle "rep" prefix for string instructions. */
421 #define Xbr { REP_Fixup, eSI_reg }
422 #define Xvr { REP_Fixup, eSI_reg }
423 #define Ybr { REP_Fixup, eDI_reg }
424 #define Yvr { REP_Fixup, eDI_reg }
425 #define Yzr { REP_Fixup, eDI_reg }
426 #define indirDXr { REP_Fixup, indir_dx_reg }
427 #define ALr { REP_Fixup, al_reg }
428 #define eAXr { REP_Fixup, eAX_reg }
430 /* Used handle HLE prefix for lockable instructions. */
431 #define Ebh1 { HLE_Fixup1, b_mode }
432 #define Evh1 { HLE_Fixup1, v_mode }
433 #define Ebh2 { HLE_Fixup2, b_mode }
434 #define Evh2 { HLE_Fixup2, v_mode }
435 #define Ebh3 { HLE_Fixup3, b_mode }
436 #define Evh3 { HLE_Fixup3, v_mode }
438 #define BND { BND_Fixup, 0 }
439 #define NOTRACK { NOTRACK_Fixup, 0 }
441 #define cond_jump_flag { NULL, cond_jump_mode }
442 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
444 /* bits in sizeflag */
445 #define SUFFIX_ALWAYS 4
453 /* byte operand with operand swapped */
455 /* byte operand, sign extend like 'T' suffix */
457 /* operand size depends on prefixes */
459 /* operand size depends on prefixes with operand swapped */
461 /* operand size depends on address prefix */
465 /* double word operand */
467 /* double word operand with operand swapped */
469 /* quad word operand */
471 /* quad word operand with operand swapped */
473 /* ten-byte operand */
475 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
476 broadcast enabled. */
478 /* Similar to x_mode, but with different EVEX mem shifts. */
480 /* Similar to x_mode, but with yet different EVEX mem shifts. */
482 /* Similar to x_mode, but with disabled broadcast. */
484 /* Similar to x_mode, but with operands swapped and disabled broadcast
487 /* 16-byte XMM operand */
489 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
490 memory operand (depending on vector length). Broadcast isn't
493 /* Same as xmmq_mode, but broadcast is allowed. */
494 evex_half_bcst_xmmq_mode
,
495 /* XMM register or byte memory operand */
497 /* XMM register or word memory operand */
499 /* XMM register or double word memory operand */
501 /* XMM register or quad word memory operand */
503 /* 16-byte XMM, word, double word or quad word operand. */
505 /* 16-byte XMM, double word, quad word operand or xmm word operand. */
507 /* 32-byte YMM operand */
509 /* quad word, ymmword or zmmword memory operand. */
511 /* 32-byte YMM or 16-byte word operand */
515 /* d_mode in 32bit, q_mode in 64bit mode. */
517 /* pair of v_mode operands */
523 /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode. */
525 /* operand size depends on REX prefixes. */
527 /* registers like dq_mode, memory like w_mode, displacements like
528 v_mode without considering Intel64 ISA. */
532 /* bounds operand with operand swapped */
534 /* 4- or 6-byte pointer operand */
537 /* v_mode for indirect branch opcodes. */
539 /* v_mode for stack-related opcodes. */
541 /* non-quad operand size depends on prefixes */
543 /* 16-byte operand */
545 /* registers like dq_mode, memory like b_mode. */
547 /* registers like d_mode, memory like b_mode. */
549 /* registers like d_mode, memory like w_mode. */
551 /* registers like dq_mode, memory like d_mode. */
553 /* normal vex mode */
556 /* Operand size depends on the VEX.W bit, with VSIB dword indices. */
557 vex_vsib_d_w_dq_mode
,
558 /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */
560 /* Operand size depends on the VEX.W bit, with VSIB qword indices. */
561 vex_vsib_q_w_dq_mode
,
562 /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */
564 /* mandatory non-vector SIB. */
567 /* scalar, ignore vector length. */
569 /* like vex_mode, ignore vector length. */
571 /* Operand size depends on the VEX.W bit, ignore vector length. */
572 vex_scalar_w_dq_mode
,
574 /* Static rounding. */
576 /* Static rounding, 64-bit mode only. */
577 evex_rounding_64_mode
,
578 /* Supress all exceptions. */
581 /* Mask register operand. */
583 /* Mask register operand. */
651 #define FLOAT NULL, { { NULL, FLOATCODE } }, 0
653 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0
654 #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P
655 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
656 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
657 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
658 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
659 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
660 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
661 #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
662 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
663 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
664 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
665 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
666 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
667 #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I))
668 #define EVEX_LEN_TABLE(I) DIS386 (USE_EVEX_LEN_TABLE, (I))
706 REG_VEX_0F3849_X86_64_P_0_W_0_M_1
,
711 REG_0FXOP_09_12_M_1_L_0
,
789 MOD_VEX_0F3849_X86_64_P_0_W_0
,
790 MOD_VEX_0F3849_X86_64_P_2_W_0
,
791 MOD_VEX_0F3849_X86_64_P_3_W_0
,
792 MOD_VEX_0F384B_X86_64_P_1_W_0
,
793 MOD_VEX_0F384B_X86_64_P_2_W_0
,
794 MOD_VEX_0F384B_X86_64_P_3_W_0
,
795 MOD_VEX_0F385C_X86_64_P_1_W_0
,
796 MOD_VEX_0F385E_X86_64_P_0_W_0
,
797 MOD_VEX_0F385E_X86_64_P_1_W_0
,
798 MOD_VEX_0F385E_X86_64_P_2_W_0
,
799 MOD_VEX_0F385E_X86_64_P_3_W_0
,
809 MOD_VEX_0F12_PREFIX_0
,
810 MOD_VEX_0F12_PREFIX_2
,
812 MOD_VEX_0F16_PREFIX_0
,
813 MOD_VEX_0F16_PREFIX_2
,
816 MOD_VEX_W_0_0F41_P_0_LEN_1
,
817 MOD_VEX_W_1_0F41_P_0_LEN_1
,
818 MOD_VEX_W_0_0F41_P_2_LEN_1
,
819 MOD_VEX_W_1_0F41_P_2_LEN_1
,
820 MOD_VEX_W_0_0F42_P_0_LEN_1
,
821 MOD_VEX_W_1_0F42_P_0_LEN_1
,
822 MOD_VEX_W_0_0F42_P_2_LEN_1
,
823 MOD_VEX_W_1_0F42_P_2_LEN_1
,
824 MOD_VEX_W_0_0F44_P_0_LEN_1
,
825 MOD_VEX_W_1_0F44_P_0_LEN_1
,
826 MOD_VEX_W_0_0F44_P_2_LEN_1
,
827 MOD_VEX_W_1_0F44_P_2_LEN_1
,
828 MOD_VEX_W_0_0F45_P_0_LEN_1
,
829 MOD_VEX_W_1_0F45_P_0_LEN_1
,
830 MOD_VEX_W_0_0F45_P_2_LEN_1
,
831 MOD_VEX_W_1_0F45_P_2_LEN_1
,
832 MOD_VEX_W_0_0F46_P_0_LEN_1
,
833 MOD_VEX_W_1_0F46_P_0_LEN_1
,
834 MOD_VEX_W_0_0F46_P_2_LEN_1
,
835 MOD_VEX_W_1_0F46_P_2_LEN_1
,
836 MOD_VEX_W_0_0F47_P_0_LEN_1
,
837 MOD_VEX_W_1_0F47_P_0_LEN_1
,
838 MOD_VEX_W_0_0F47_P_2_LEN_1
,
839 MOD_VEX_W_1_0F47_P_2_LEN_1
,
840 MOD_VEX_W_0_0F4A_P_0_LEN_1
,
841 MOD_VEX_W_1_0F4A_P_0_LEN_1
,
842 MOD_VEX_W_0_0F4A_P_2_LEN_1
,
843 MOD_VEX_W_1_0F4A_P_2_LEN_1
,
844 MOD_VEX_W_0_0F4B_P_0_LEN_1
,
845 MOD_VEX_W_1_0F4B_P_0_LEN_1
,
846 MOD_VEX_W_0_0F4B_P_2_LEN_1
,
858 MOD_VEX_W_0_0F91_P_0_LEN_0
,
859 MOD_VEX_W_1_0F91_P_0_LEN_0
,
860 MOD_VEX_W_0_0F91_P_2_LEN_0
,
861 MOD_VEX_W_1_0F91_P_2_LEN_0
,
862 MOD_VEX_W_0_0F92_P_0_LEN_0
,
863 MOD_VEX_W_0_0F92_P_2_LEN_0
,
864 MOD_VEX_0F92_P_3_LEN_0
,
865 MOD_VEX_W_0_0F93_P_0_LEN_0
,
866 MOD_VEX_W_0_0F93_P_2_LEN_0
,
867 MOD_VEX_0F93_P_3_LEN_0
,
868 MOD_VEX_W_0_0F98_P_0_LEN_0
,
869 MOD_VEX_W_1_0F98_P_0_LEN_0
,
870 MOD_VEX_W_0_0F98_P_2_LEN_0
,
871 MOD_VEX_W_1_0F98_P_2_LEN_0
,
872 MOD_VEX_W_0_0F99_P_0_LEN_0
,
873 MOD_VEX_W_1_0F99_P_0_LEN_0
,
874 MOD_VEX_W_0_0F99_P_2_LEN_0
,
875 MOD_VEX_W_1_0F99_P_2_LEN_0
,
880 MOD_VEX_0FF0_PREFIX_3
,
897 MOD_EVEX_0F12_PREFIX_0
,
898 MOD_EVEX_0F12_PREFIX_2
,
900 MOD_EVEX_0F16_PREFIX_0
,
901 MOD_EVEX_0F16_PREFIX_2
,
909 MOD_EVEX_0F382A_P_1_W_1
,
911 MOD_EVEX_0F383A_P_1_W_0
,
919 MOD_EVEX_0F38C6_REG_1
,
920 MOD_EVEX_0F38C6_REG_2
,
921 MOD_EVEX_0F38C6_REG_5
,
922 MOD_EVEX_0F38C6_REG_6
,
923 MOD_EVEX_0F38C7_REG_1
,
924 MOD_EVEX_0F38C7_REG_2
,
925 MOD_EVEX_0F38C7_REG_5
,
926 MOD_EVEX_0F38C7_REG_6
939 RM_0F1E_P_1_MOD_3_REG_7
,
940 RM_0FAE_REG_6_MOD_3_P_0
,
942 RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0
948 PREFIX_0F01_REG_3_RM_1
,
949 PREFIX_0F01_REG_5_MOD_0
,
950 PREFIX_0F01_REG_5_MOD_3_RM_0
,
951 PREFIX_0F01_REG_5_MOD_3_RM_1
,
952 PREFIX_0F01_REG_5_MOD_3_RM_2
,
953 PREFIX_0F01_REG_7_MOD_3_RM_2
,
991 PREFIX_0FAE_REG_0_MOD_3
,
992 PREFIX_0FAE_REG_1_MOD_3
,
993 PREFIX_0FAE_REG_2_MOD_3
,
994 PREFIX_0FAE_REG_3_MOD_3
,
995 PREFIX_0FAE_REG_4_MOD_0
,
996 PREFIX_0FAE_REG_4_MOD_3
,
997 PREFIX_0FAE_REG_5_MOD_3
,
998 PREFIX_0FAE_REG_6_MOD_0
,
999 PREFIX_0FAE_REG_6_MOD_3
,
1000 PREFIX_0FAE_REG_7_MOD_0
,
1005 PREFIX_0FC7_REG_6_MOD_0
,
1006 PREFIX_0FC7_REG_6_MOD_3
,
1007 PREFIX_0FC7_REG_7_MOD_3
,
1062 PREFIX_VEX_0F3849_X86_64
,
1063 PREFIX_VEX_0F384B_X86_64
,
1064 PREFIX_VEX_0F385C_X86_64
,
1065 PREFIX_VEX_0F385E_X86_64
,
1176 THREE_BYTE_0F38
= 0,
1203 VEX_LEN_0F12_P_0_M_0
= 0,
1204 VEX_LEN_0F12_P_0_M_1
,
1205 #define VEX_LEN_0F12_P_2_M_0 VEX_LEN_0F12_P_0_M_0
1207 VEX_LEN_0F16_P_0_M_0
,
1208 VEX_LEN_0F16_P_0_M_1
,
1209 #define VEX_LEN_0F16_P_2_M_0 VEX_LEN_0F16_P_0_M_0
1245 VEX_LEN_0FAE_R_2_M_0
,
1246 VEX_LEN_0FAE_R_3_M_0
,
1256 VEX_LEN_0F3849_X86_64_P_0_W_0_M_0
,
1257 VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0
,
1258 VEX_LEN_0F3849_X86_64_P_2_W_0_M_0
,
1259 VEX_LEN_0F3849_X86_64_P_3_W_0_M_0
,
1260 VEX_LEN_0F384B_X86_64_P_1_W_0_M_0
,
1261 VEX_LEN_0F384B_X86_64_P_2_W_0_M_0
,
1262 VEX_LEN_0F384B_X86_64_P_3_W_0_M_0
,
1264 VEX_LEN_0F385C_X86_64_P_1_W_0_M_0
,
1265 VEX_LEN_0F385E_X86_64_P_0_W_0_M_0
,
1266 VEX_LEN_0F385E_X86_64_P_1_W_0_M_0
,
1267 VEX_LEN_0F385E_X86_64_P_2_W_0_M_0
,
1268 VEX_LEN_0F385E_X86_64_P_3_W_0_M_0
,
1308 VEX_LEN_0FXOP_08_85
,
1309 VEX_LEN_0FXOP_08_86
,
1310 VEX_LEN_0FXOP_08_87
,
1311 VEX_LEN_0FXOP_08_8E
,
1312 VEX_LEN_0FXOP_08_8F
,
1313 VEX_LEN_0FXOP_08_95
,
1314 VEX_LEN_0FXOP_08_96
,
1315 VEX_LEN_0FXOP_08_97
,
1316 VEX_LEN_0FXOP_08_9E
,
1317 VEX_LEN_0FXOP_08_9F
,
1318 VEX_LEN_0FXOP_08_A3
,
1319 VEX_LEN_0FXOP_08_A6
,
1320 VEX_LEN_0FXOP_08_B6
,
1321 VEX_LEN_0FXOP_08_C0
,
1322 VEX_LEN_0FXOP_08_C1
,
1323 VEX_LEN_0FXOP_08_C2
,
1324 VEX_LEN_0FXOP_08_C3
,
1325 VEX_LEN_0FXOP_08_CC
,
1326 VEX_LEN_0FXOP_08_CD
,
1327 VEX_LEN_0FXOP_08_CE
,
1328 VEX_LEN_0FXOP_08_CF
,
1329 VEX_LEN_0FXOP_08_EC
,
1330 VEX_LEN_0FXOP_08_ED
,
1331 VEX_LEN_0FXOP_08_EE
,
1332 VEX_LEN_0FXOP_08_EF
,
1333 VEX_LEN_0FXOP_09_01
,
1334 VEX_LEN_0FXOP_09_02
,
1335 VEX_LEN_0FXOP_09_12_M_1
,
1336 VEX_LEN_0FXOP_09_82_W_0
,
1337 VEX_LEN_0FXOP_09_83_W_0
,
1338 VEX_LEN_0FXOP_09_90
,
1339 VEX_LEN_0FXOP_09_91
,
1340 VEX_LEN_0FXOP_09_92
,
1341 VEX_LEN_0FXOP_09_93
,
1342 VEX_LEN_0FXOP_09_94
,
1343 VEX_LEN_0FXOP_09_95
,
1344 VEX_LEN_0FXOP_09_96
,
1345 VEX_LEN_0FXOP_09_97
,
1346 VEX_LEN_0FXOP_09_98
,
1347 VEX_LEN_0FXOP_09_99
,
1348 VEX_LEN_0FXOP_09_9A
,
1349 VEX_LEN_0FXOP_09_9B
,
1350 VEX_LEN_0FXOP_09_C1
,
1351 VEX_LEN_0FXOP_09_C2
,
1352 VEX_LEN_0FXOP_09_C3
,
1353 VEX_LEN_0FXOP_09_C6
,
1354 VEX_LEN_0FXOP_09_C7
,
1355 VEX_LEN_0FXOP_09_CB
,
1356 VEX_LEN_0FXOP_09_D1
,
1357 VEX_LEN_0FXOP_09_D2
,
1358 VEX_LEN_0FXOP_09_D3
,
1359 VEX_LEN_0FXOP_09_D6
,
1360 VEX_LEN_0FXOP_09_D7
,
1361 VEX_LEN_0FXOP_09_DB
,
1362 VEX_LEN_0FXOP_09_E1
,
1363 VEX_LEN_0FXOP_09_E2
,
1364 VEX_LEN_0FXOP_09_E3
,
1365 VEX_LEN_0FXOP_0A_12
,
1377 EVEX_LEN_0F3819_W_0
,
1378 EVEX_LEN_0F3819_W_1
,
1379 EVEX_LEN_0F381A_W_0_M_0
,
1380 EVEX_LEN_0F381A_W_1_M_0
,
1381 EVEX_LEN_0F381B_W_0_M_0
,
1382 EVEX_LEN_0F381B_W_1_M_0
,
1384 EVEX_LEN_0F385A_W_0_M_0
,
1385 EVEX_LEN_0F385A_W_1_M_0
,
1386 EVEX_LEN_0F385B_W_0_M_0
,
1387 EVEX_LEN_0F385B_W_1_M_0
,
1388 EVEX_LEN_0F38C6_R_1_M_0
,
1389 EVEX_LEN_0F38C6_R_2_M_0
,
1390 EVEX_LEN_0F38C6_R_5_M_0
,
1391 EVEX_LEN_0F38C6_R_6_M_0
,
1392 EVEX_LEN_0F38C7_R_1_M_0_W_0
,
1393 EVEX_LEN_0F38C7_R_1_M_0_W_1
,
1394 EVEX_LEN_0F38C7_R_2_M_0_W_0
,
1395 EVEX_LEN_0F38C7_R_2_M_0_W_1
,
1396 EVEX_LEN_0F38C7_R_5_M_0_W_0
,
1397 EVEX_LEN_0F38C7_R_5_M_0_W_1
,
1398 EVEX_LEN_0F38C7_R_6_M_0_W_0
,
1399 EVEX_LEN_0F38C7_R_6_M_0_W_1
,
1400 EVEX_LEN_0F3A00_W_1
,
1401 EVEX_LEN_0F3A01_W_1
,
1406 EVEX_LEN_0F3A18_W_0
,
1407 EVEX_LEN_0F3A18_W_1
,
1408 EVEX_LEN_0F3A19_W_0
,
1409 EVEX_LEN_0F3A19_W_1
,
1410 EVEX_LEN_0F3A1A_W_0
,
1411 EVEX_LEN_0F3A1A_W_1
,
1412 EVEX_LEN_0F3A1B_W_0
,
1413 EVEX_LEN_0F3A1B_W_1
,
1415 EVEX_LEN_0F3A21_W_0
,
1417 EVEX_LEN_0F3A23_W_0
,
1418 EVEX_LEN_0F3A23_W_1
,
1419 EVEX_LEN_0F3A38_W_0
,
1420 EVEX_LEN_0F3A38_W_1
,
1421 EVEX_LEN_0F3A39_W_0
,
1422 EVEX_LEN_0F3A39_W_1
,
1423 EVEX_LEN_0F3A3A_W_0
,
1424 EVEX_LEN_0F3A3A_W_1
,
1425 EVEX_LEN_0F3A3B_W_0
,
1426 EVEX_LEN_0F3A3B_W_1
,
1427 EVEX_LEN_0F3A43_W_0
,
1433 VEX_W_0F41_P_0_LEN_1
= 0,
1434 VEX_W_0F41_P_2_LEN_1
,
1435 VEX_W_0F42_P_0_LEN_1
,
1436 VEX_W_0F42_P_2_LEN_1
,
1437 VEX_W_0F44_P_0_LEN_0
,
1438 VEX_W_0F44_P_2_LEN_0
,
1439 VEX_W_0F45_P_0_LEN_1
,
1440 VEX_W_0F45_P_2_LEN_1
,
1441 VEX_W_0F46_P_0_LEN_1
,
1442 VEX_W_0F46_P_2_LEN_1
,
1443 VEX_W_0F47_P_0_LEN_1
,
1444 VEX_W_0F47_P_2_LEN_1
,
1445 VEX_W_0F4A_P_0_LEN_1
,
1446 VEX_W_0F4A_P_2_LEN_1
,
1447 VEX_W_0F4B_P_0_LEN_1
,
1448 VEX_W_0F4B_P_2_LEN_1
,
1449 VEX_W_0F90_P_0_LEN_0
,
1450 VEX_W_0F90_P_2_LEN_0
,
1451 VEX_W_0F91_P_0_LEN_0
,
1452 VEX_W_0F91_P_2_LEN_0
,
1453 VEX_W_0F92_P_0_LEN_0
,
1454 VEX_W_0F92_P_2_LEN_0
,
1455 VEX_W_0F93_P_0_LEN_0
,
1456 VEX_W_0F93_P_2_LEN_0
,
1457 VEX_W_0F98_P_0_LEN_0
,
1458 VEX_W_0F98_P_2_LEN_0
,
1459 VEX_W_0F99_P_0_LEN_0
,
1460 VEX_W_0F99_P_2_LEN_0
,
1469 VEX_W_0F381A_M_0_L_1
,
1476 VEX_W_0F3849_X86_64_P_0
,
1477 VEX_W_0F3849_X86_64_P_2
,
1478 VEX_W_0F3849_X86_64_P_3
,
1479 VEX_W_0F384B_X86_64_P_1
,
1480 VEX_W_0F384B_X86_64_P_2
,
1481 VEX_W_0F384B_X86_64_P_3
,
1484 VEX_W_0F385A_M_0_L_0
,
1485 VEX_W_0F385C_X86_64_P_1
,
1486 VEX_W_0F385E_X86_64_P_0
,
1487 VEX_W_0F385E_X86_64_P_1
,
1488 VEX_W_0F385E_X86_64_P_2
,
1489 VEX_W_0F385E_X86_64_P_3
,
1511 VEX_W_0FXOP_08_85_L_0
,
1512 VEX_W_0FXOP_08_86_L_0
,
1513 VEX_W_0FXOP_08_87_L_0
,
1514 VEX_W_0FXOP_08_8E_L_0
,
1515 VEX_W_0FXOP_08_8F_L_0
,
1516 VEX_W_0FXOP_08_95_L_0
,
1517 VEX_W_0FXOP_08_96_L_0
,
1518 VEX_W_0FXOP_08_97_L_0
,
1519 VEX_W_0FXOP_08_9E_L_0
,
1520 VEX_W_0FXOP_08_9F_L_0
,
1521 VEX_W_0FXOP_08_A6_L_0
,
1522 VEX_W_0FXOP_08_B6_L_0
,
1523 VEX_W_0FXOP_08_C0_L_0
,
1524 VEX_W_0FXOP_08_C1_L_0
,
1525 VEX_W_0FXOP_08_C2_L_0
,
1526 VEX_W_0FXOP_08_C3_L_0
,
1527 VEX_W_0FXOP_08_CC_L_0
,
1528 VEX_W_0FXOP_08_CD_L_0
,
1529 VEX_W_0FXOP_08_CE_L_0
,
1530 VEX_W_0FXOP_08_CF_L_0
,
1531 VEX_W_0FXOP_08_EC_L_0
,
1532 VEX_W_0FXOP_08_ED_L_0
,
1533 VEX_W_0FXOP_08_EE_L_0
,
1534 VEX_W_0FXOP_08_EF_L_0
,
1540 VEX_W_0FXOP_09_C1_L_0
,
1541 VEX_W_0FXOP_09_C2_L_0
,
1542 VEX_W_0FXOP_09_C3_L_0
,
1543 VEX_W_0FXOP_09_C6_L_0
,
1544 VEX_W_0FXOP_09_C7_L_0
,
1545 VEX_W_0FXOP_09_CB_L_0
,
1546 VEX_W_0FXOP_09_D1_L_0
,
1547 VEX_W_0FXOP_09_D2_L_0
,
1548 VEX_W_0FXOP_09_D3_L_0
,
1549 VEX_W_0FXOP_09_D6_L_0
,
1550 VEX_W_0FXOP_09_D7_L_0
,
1551 VEX_W_0FXOP_09_DB_L_0
,
1552 VEX_W_0FXOP_09_E1_L_0
,
1553 VEX_W_0FXOP_09_E2_L_0
,
1554 VEX_W_0FXOP_09_E3_L_0
,
1560 EVEX_W_0F12_P_0_M_1
,
1563 EVEX_W_0F16_P_0_M_1
,
1683 EVEX_W_0F38C7_R_1_M_0
,
1684 EVEX_W_0F38C7_R_2_M_0
,
1685 EVEX_W_0F38C7_R_5_M_0
,
1686 EVEX_W_0F38C7_R_6_M_0
,
1711 typedef void (*op_rtn
) (int bytemode
, int sizeflag
);
1720 unsigned int prefix_requirement
;
1723 /* Upper case letters in the instruction names here are macros.
1724 'A' => print 'b' if no register operands or suffix_always is true
1725 'B' => print 'b' if suffix_always is true
1726 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
1728 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
1729 suffix_always is true
1730 'E' => print 'e' if 32-bit form of jcxz
1731 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
1732 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
1733 'H' => print ",pt" or ",pn" branch hint
1736 'K' => print 'd' or 'q' if rex prefix is present.
1738 'M' => print 'r' if intel_mnemonic is false.
1739 'N' => print 'n' if instruction has no wait "prefix"
1740 'O' => print 'd' or 'o' (or 'q' in Intel mode)
1741 'P' => behave as 'T' except with register operand outside of suffix_always
1743 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
1745 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
1746 'S' => print 'w', 'l' or 'q' if suffix_always is true
1747 'T' => print 'w', 'l'/'d', or 'q' if instruction has an operand size
1748 prefix or if suffix_always is true.
1751 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
1752 'X' => print 's', 'd' depending on data16 prefix (for XMM)
1754 'Z' => print 'q' in 64bit mode and 'l' otherwise, if suffix_always is true.
1755 '!' => change condition from true to false or from false to true.
1756 '%' => add 1 upper case letter to the macro.
1757 '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size
1758 prefix or suffix_always is true (lcall/ljmp).
1759 '@' => in 64bit mode for Intel64 ISA or if instruction
1760 has no operand sizing prefix, print 'q' if suffix_always is true or
1761 nothing otherwise; behave as 'P' in all other cases
1763 2 upper case letter macros:
1764 "XY" => print 'x' or 'y' if suffix_always is true or no register
1765 operands and no broadcast.
1766 "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
1767 register operands and no broadcast.
1768 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
1769 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand, cond
1770 being false, or no operand at all in 64bit mode, or if suffix_always
1772 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
1773 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
1774 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
1775 "DQ" => print 'd' or 'q' depending on the VEX.W bit
1776 "BW" => print 'b' or 'w' depending on the VEX.W bit
1777 "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
1778 an operand size prefix, or suffix_always is true. print
1779 'q' if rex prefix is present.
1781 Many of the above letters print nothing in Intel mode. See "putop"
1784 Braces '{' and '}', and vertical bars '|', indicate alternative
1785 mnemonic strings for AT&T and Intel. */
1787 static const struct dis386 dis386
[] = {
1789 { "addB", { Ebh1
, Gb
}, 0 },
1790 { "addS", { Evh1
, Gv
}, 0 },
1791 { "addB", { Gb
, EbS
}, 0 },
1792 { "addS", { Gv
, EvS
}, 0 },
1793 { "addB", { AL
, Ib
}, 0 },
1794 { "addS", { eAX
, Iv
}, 0 },
1795 { X86_64_TABLE (X86_64_06
) },
1796 { X86_64_TABLE (X86_64_07
) },
1798 { "orB", { Ebh1
, Gb
}, 0 },
1799 { "orS", { Evh1
, Gv
}, 0 },
1800 { "orB", { Gb
, EbS
}, 0 },
1801 { "orS", { Gv
, EvS
}, 0 },
1802 { "orB", { AL
, Ib
}, 0 },
1803 { "orS", { eAX
, Iv
}, 0 },
1804 { X86_64_TABLE (X86_64_0E
) },
1805 { Bad_Opcode
}, /* 0x0f extended opcode escape */
1807 { "adcB", { Ebh1
, Gb
}, 0 },
1808 { "adcS", { Evh1
, Gv
}, 0 },
1809 { "adcB", { Gb
, EbS
}, 0 },
1810 { "adcS", { Gv
, EvS
}, 0 },
1811 { "adcB", { AL
, Ib
}, 0 },
1812 { "adcS", { eAX
, Iv
}, 0 },
1813 { X86_64_TABLE (X86_64_16
) },
1814 { X86_64_TABLE (X86_64_17
) },
1816 { "sbbB", { Ebh1
, Gb
}, 0 },
1817 { "sbbS", { Evh1
, Gv
}, 0 },
1818 { "sbbB", { Gb
, EbS
}, 0 },
1819 { "sbbS", { Gv
, EvS
}, 0 },
1820 { "sbbB", { AL
, Ib
}, 0 },
1821 { "sbbS", { eAX
, Iv
}, 0 },
1822 { X86_64_TABLE (X86_64_1E
) },
1823 { X86_64_TABLE (X86_64_1F
) },
1825 { "andB", { Ebh1
, Gb
}, 0 },
1826 { "andS", { Evh1
, Gv
}, 0 },
1827 { "andB", { Gb
, EbS
}, 0 },
1828 { "andS", { Gv
, EvS
}, 0 },
1829 { "andB", { AL
, Ib
}, 0 },
1830 { "andS", { eAX
, Iv
}, 0 },
1831 { Bad_Opcode
}, /* SEG ES prefix */
1832 { X86_64_TABLE (X86_64_27
) },
1834 { "subB", { Ebh1
, Gb
}, 0 },
1835 { "subS", { Evh1
, Gv
}, 0 },
1836 { "subB", { Gb
, EbS
}, 0 },
1837 { "subS", { Gv
, EvS
}, 0 },
1838 { "subB", { AL
, Ib
}, 0 },
1839 { "subS", { eAX
, Iv
}, 0 },
1840 { Bad_Opcode
}, /* SEG CS prefix */
1841 { X86_64_TABLE (X86_64_2F
) },
1843 { "xorB", { Ebh1
, Gb
}, 0 },
1844 { "xorS", { Evh1
, Gv
}, 0 },
1845 { "xorB", { Gb
, EbS
}, 0 },
1846 { "xorS", { Gv
, EvS
}, 0 },
1847 { "xorB", { AL
, Ib
}, 0 },
1848 { "xorS", { eAX
, Iv
}, 0 },
1849 { Bad_Opcode
}, /* SEG SS prefix */
1850 { X86_64_TABLE (X86_64_37
) },
1852 { "cmpB", { Eb
, Gb
}, 0 },
1853 { "cmpS", { Ev
, Gv
}, 0 },
1854 { "cmpB", { Gb
, EbS
}, 0 },
1855 { "cmpS", { Gv
, EvS
}, 0 },
1856 { "cmpB", { AL
, Ib
}, 0 },
1857 { "cmpS", { eAX
, Iv
}, 0 },
1858 { Bad_Opcode
}, /* SEG DS prefix */
1859 { X86_64_TABLE (X86_64_3F
) },
1861 { "inc{S|}", { RMeAX
}, 0 },
1862 { "inc{S|}", { RMeCX
}, 0 },
1863 { "inc{S|}", { RMeDX
}, 0 },
1864 { "inc{S|}", { RMeBX
}, 0 },
1865 { "inc{S|}", { RMeSP
}, 0 },
1866 { "inc{S|}", { RMeBP
}, 0 },
1867 { "inc{S|}", { RMeSI
}, 0 },
1868 { "inc{S|}", { RMeDI
}, 0 },
1870 { "dec{S|}", { RMeAX
}, 0 },
1871 { "dec{S|}", { RMeCX
}, 0 },
1872 { "dec{S|}", { RMeDX
}, 0 },
1873 { "dec{S|}", { RMeBX
}, 0 },
1874 { "dec{S|}", { RMeSP
}, 0 },
1875 { "dec{S|}", { RMeBP
}, 0 },
1876 { "dec{S|}", { RMeSI
}, 0 },
1877 { "dec{S|}", { RMeDI
}, 0 },
1879 { "push{!P|}", { RMrAX
}, 0 },
1880 { "push{!P|}", { RMrCX
}, 0 },
1881 { "push{!P|}", { RMrDX
}, 0 },
1882 { "push{!P|}", { RMrBX
}, 0 },
1883 { "push{!P|}", { RMrSP
}, 0 },
1884 { "push{!P|}", { RMrBP
}, 0 },
1885 { "push{!P|}", { RMrSI
}, 0 },
1886 { "push{!P|}", { RMrDI
}, 0 },
1888 { "pop{!P|}", { RMrAX
}, 0 },
1889 { "pop{!P|}", { RMrCX
}, 0 },
1890 { "pop{!P|}", { RMrDX
}, 0 },
1891 { "pop{!P|}", { RMrBX
}, 0 },
1892 { "pop{!P|}", { RMrSP
}, 0 },
1893 { "pop{!P|}", { RMrBP
}, 0 },
1894 { "pop{!P|}", { RMrSI
}, 0 },
1895 { "pop{!P|}", { RMrDI
}, 0 },
1897 { X86_64_TABLE (X86_64_60
) },
1898 { X86_64_TABLE (X86_64_61
) },
1899 { X86_64_TABLE (X86_64_62
) },
1900 { X86_64_TABLE (X86_64_63
) },
1901 { Bad_Opcode
}, /* seg fs */
1902 { Bad_Opcode
}, /* seg gs */
1903 { Bad_Opcode
}, /* op size prefix */
1904 { Bad_Opcode
}, /* adr size prefix */
1906 { "pushP", { sIv
}, 0 },
1907 { "imulS", { Gv
, Ev
, Iv
}, 0 },
1908 { "pushP", { sIbT
}, 0 },
1909 { "imulS", { Gv
, Ev
, sIb
}, 0 },
1910 { "ins{b|}", { Ybr
, indirDX
}, 0 },
1911 { X86_64_TABLE (X86_64_6D
) },
1912 { "outs{b|}", { indirDXr
, Xb
}, 0 },
1913 { X86_64_TABLE (X86_64_6F
) },
1915 { "joH", { Jb
, BND
, cond_jump_flag
}, 0 },
1916 { "jnoH", { Jb
, BND
, cond_jump_flag
}, 0 },
1917 { "jbH", { Jb
, BND
, cond_jump_flag
}, 0 },
1918 { "jaeH", { Jb
, BND
, cond_jump_flag
}, 0 },
1919 { "jeH", { Jb
, BND
, cond_jump_flag
}, 0 },
1920 { "jneH", { Jb
, BND
, cond_jump_flag
}, 0 },
1921 { "jbeH", { Jb
, BND
, cond_jump_flag
}, 0 },
1922 { "jaH", { Jb
, BND
, cond_jump_flag
}, 0 },
1924 { "jsH", { Jb
, BND
, cond_jump_flag
}, 0 },
1925 { "jnsH", { Jb
, BND
, cond_jump_flag
}, 0 },
1926 { "jpH", { Jb
, BND
, cond_jump_flag
}, 0 },
1927 { "jnpH", { Jb
, BND
, cond_jump_flag
}, 0 },
1928 { "jlH", { Jb
, BND
, cond_jump_flag
}, 0 },
1929 { "jgeH", { Jb
, BND
, cond_jump_flag
}, 0 },
1930 { "jleH", { Jb
, BND
, cond_jump_flag
}, 0 },
1931 { "jgH", { Jb
, BND
, cond_jump_flag
}, 0 },
1933 { REG_TABLE (REG_80
) },
1934 { REG_TABLE (REG_81
) },
1935 { X86_64_TABLE (X86_64_82
) },
1936 { REG_TABLE (REG_83
) },
1937 { "testB", { Eb
, Gb
}, 0 },
1938 { "testS", { Ev
, Gv
}, 0 },
1939 { "xchgB", { Ebh2
, Gb
}, 0 },
1940 { "xchgS", { Evh2
, Gv
}, 0 },
1942 { "movB", { Ebh3
, Gb
}, 0 },
1943 { "movS", { Evh3
, Gv
}, 0 },
1944 { "movB", { Gb
, EbS
}, 0 },
1945 { "movS", { Gv
, EvS
}, 0 },
1946 { "movD", { Sv
, Sw
}, 0 },
1947 { MOD_TABLE (MOD_8D
) },
1948 { "movD", { Sw
, Sv
}, 0 },
1949 { REG_TABLE (REG_8F
) },
1951 { PREFIX_TABLE (PREFIX_90
) },
1952 { "xchgS", { RMeCX
, eAX
}, 0 },
1953 { "xchgS", { RMeDX
, eAX
}, 0 },
1954 { "xchgS", { RMeBX
, eAX
}, 0 },
1955 { "xchgS", { RMeSP
, eAX
}, 0 },
1956 { "xchgS", { RMeBP
, eAX
}, 0 },
1957 { "xchgS", { RMeSI
, eAX
}, 0 },
1958 { "xchgS", { RMeDI
, eAX
}, 0 },
1960 { "cW{t|}R", { XX
}, 0 },
1961 { "cR{t|}O", { XX
}, 0 },
1962 { X86_64_TABLE (X86_64_9A
) },
1963 { Bad_Opcode
}, /* fwait */
1964 { "pushfP", { XX
}, 0 },
1965 { "popfP", { XX
}, 0 },
1966 { "sahf", { XX
}, 0 },
1967 { "lahf", { XX
}, 0 },
1969 { "mov%LB", { AL
, Ob
}, 0 },
1970 { "mov%LS", { eAX
, Ov
}, 0 },
1971 { "mov%LB", { Ob
, AL
}, 0 },
1972 { "mov%LS", { Ov
, eAX
}, 0 },
1973 { "movs{b|}", { Ybr
, Xb
}, 0 },
1974 { "movs{R|}", { Yvr
, Xv
}, 0 },
1975 { "cmps{b|}", { Xb
, Yb
}, 0 },
1976 { "cmps{R|}", { Xv
, Yv
}, 0 },
1978 { "testB", { AL
, Ib
}, 0 },
1979 { "testS", { eAX
, Iv
}, 0 },
1980 { "stosB", { Ybr
, AL
}, 0 },
1981 { "stosS", { Yvr
, eAX
}, 0 },
1982 { "lodsB", { ALr
, Xb
}, 0 },
1983 { "lodsS", { eAXr
, Xv
}, 0 },
1984 { "scasB", { AL
, Yb
}, 0 },
1985 { "scasS", { eAX
, Yv
}, 0 },
1987 { "movB", { RMAL
, Ib
}, 0 },
1988 { "movB", { RMCL
, Ib
}, 0 },
1989 { "movB", { RMDL
, Ib
}, 0 },
1990 { "movB", { RMBL
, Ib
}, 0 },
1991 { "movB", { RMAH
, Ib
}, 0 },
1992 { "movB", { RMCH
, Ib
}, 0 },
1993 { "movB", { RMDH
, Ib
}, 0 },
1994 { "movB", { RMBH
, Ib
}, 0 },
1996 { "mov%LV", { RMeAX
, Iv64
}, 0 },
1997 { "mov%LV", { RMeCX
, Iv64
}, 0 },
1998 { "mov%LV", { RMeDX
, Iv64
}, 0 },
1999 { "mov%LV", { RMeBX
, Iv64
}, 0 },
2000 { "mov%LV", { RMeSP
, Iv64
}, 0 },
2001 { "mov%LV", { RMeBP
, Iv64
}, 0 },
2002 { "mov%LV", { RMeSI
, Iv64
}, 0 },
2003 { "mov%LV", { RMeDI
, Iv64
}, 0 },
2005 { REG_TABLE (REG_C0
) },
2006 { REG_TABLE (REG_C1
) },
2007 { X86_64_TABLE (X86_64_C2
) },
2008 { X86_64_TABLE (X86_64_C3
) },
2009 { X86_64_TABLE (X86_64_C4
) },
2010 { X86_64_TABLE (X86_64_C5
) },
2011 { REG_TABLE (REG_C6
) },
2012 { REG_TABLE (REG_C7
) },
2014 { "enterP", { Iw
, Ib
}, 0 },
2015 { "leaveP", { XX
}, 0 },
2016 { "{l|}ret{|f}%LP", { Iw
}, 0 },
2017 { "{l|}ret{|f}%LP", { XX
}, 0 },
2018 { "int3", { XX
}, 0 },
2019 { "int", { Ib
}, 0 },
2020 { X86_64_TABLE (X86_64_CE
) },
2021 { "iret%LP", { XX
}, 0 },
2023 { REG_TABLE (REG_D0
) },
2024 { REG_TABLE (REG_D1
) },
2025 { REG_TABLE (REG_D2
) },
2026 { REG_TABLE (REG_D3
) },
2027 { X86_64_TABLE (X86_64_D4
) },
2028 { X86_64_TABLE (X86_64_D5
) },
2030 { "xlat", { DSBX
}, 0 },
2041 { "loopneFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2042 { "loopeFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2043 { "loopFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2044 { "jEcxzH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2045 { "inB", { AL
, Ib
}, 0 },
2046 { "inG", { zAX
, Ib
}, 0 },
2047 { "outB", { Ib
, AL
}, 0 },
2048 { "outG", { Ib
, zAX
}, 0 },
2050 { X86_64_TABLE (X86_64_E8
) },
2051 { X86_64_TABLE (X86_64_E9
) },
2052 { X86_64_TABLE (X86_64_EA
) },
2053 { "jmp", { Jb
, BND
}, 0 },
2054 { "inB", { AL
, indirDX
}, 0 },
2055 { "inG", { zAX
, indirDX
}, 0 },
2056 { "outB", { indirDX
, AL
}, 0 },
2057 { "outG", { indirDX
, zAX
}, 0 },
2059 { Bad_Opcode
}, /* lock prefix */
2060 { "icebp", { XX
}, 0 },
2061 { Bad_Opcode
}, /* repne */
2062 { Bad_Opcode
}, /* repz */
2063 { "hlt", { XX
}, 0 },
2064 { "cmc", { XX
}, 0 },
2065 { REG_TABLE (REG_F6
) },
2066 { REG_TABLE (REG_F7
) },
2068 { "clc", { XX
}, 0 },
2069 { "stc", { XX
}, 0 },
2070 { "cli", { XX
}, 0 },
2071 { "sti", { XX
}, 0 },
2072 { "cld", { XX
}, 0 },
2073 { "std", { XX
}, 0 },
2074 { REG_TABLE (REG_FE
) },
2075 { REG_TABLE (REG_FF
) },
2078 static const struct dis386 dis386_twobyte
[] = {
2080 { REG_TABLE (REG_0F00
) },
2081 { REG_TABLE (REG_0F01
) },
2082 { "larS", { Gv
, Ew
}, 0 },
2083 { "lslS", { Gv
, Ew
}, 0 },
2085 { "syscall", { XX
}, 0 },
2086 { "clts", { XX
}, 0 },
2087 { "sysret%LQ", { XX
}, 0 },
2089 { "invd", { XX
}, 0 },
2090 { PREFIX_TABLE (PREFIX_0F09
) },
2092 { "ud2", { XX
}, 0 },
2094 { REG_TABLE (REG_0F0D
) },
2095 { "femms", { XX
}, 0 },
2096 { "", { MX
, EM
, OPSUF
}, 0 }, /* See OP_3DNowSuffix. */
2098 { PREFIX_TABLE (PREFIX_0F10
) },
2099 { PREFIX_TABLE (PREFIX_0F11
) },
2100 { PREFIX_TABLE (PREFIX_0F12
) },
2101 { MOD_TABLE (MOD_0F13
) },
2102 { "unpcklpX", { XM
, EXx
}, PREFIX_OPCODE
},
2103 { "unpckhpX", { XM
, EXx
}, PREFIX_OPCODE
},
2104 { PREFIX_TABLE (PREFIX_0F16
) },
2105 { MOD_TABLE (MOD_0F17
) },
2107 { REG_TABLE (REG_0F18
) },
2108 { "nopQ", { Ev
}, 0 },
2109 { PREFIX_TABLE (PREFIX_0F1A
) },
2110 { PREFIX_TABLE (PREFIX_0F1B
) },
2111 { PREFIX_TABLE (PREFIX_0F1C
) },
2112 { "nopQ", { Ev
}, 0 },
2113 { PREFIX_TABLE (PREFIX_0F1E
) },
2114 { "nopQ", { Ev
}, 0 },
2116 { "movZ", { Em
, Cm
}, 0 },
2117 { "movZ", { Em
, Dm
}, 0 },
2118 { "movZ", { Cm
, Em
}, 0 },
2119 { "movZ", { Dm
, Em
}, 0 },
2120 { X86_64_TABLE (X86_64_0F24
) },
2122 { X86_64_TABLE (X86_64_0F26
) },
2125 { "movapX", { XM
, EXx
}, PREFIX_OPCODE
},
2126 { "movapX", { EXxS
, XM
}, PREFIX_OPCODE
},
2127 { PREFIX_TABLE (PREFIX_0F2A
) },
2128 { PREFIX_TABLE (PREFIX_0F2B
) },
2129 { PREFIX_TABLE (PREFIX_0F2C
) },
2130 { PREFIX_TABLE (PREFIX_0F2D
) },
2131 { PREFIX_TABLE (PREFIX_0F2E
) },
2132 { PREFIX_TABLE (PREFIX_0F2F
) },
2134 { "wrmsr", { XX
}, 0 },
2135 { "rdtsc", { XX
}, 0 },
2136 { "rdmsr", { XX
}, 0 },
2137 { "rdpmc", { XX
}, 0 },
2138 { "sysenter", { SEP
}, 0 },
2139 { "sysexit", { SEP
}, 0 },
2141 { "getsec", { XX
}, 0 },
2143 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38
, PREFIX_OPCODE
) },
2145 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A
, PREFIX_OPCODE
) },
2152 { "cmovoS", { Gv
, Ev
}, 0 },
2153 { "cmovnoS", { Gv
, Ev
}, 0 },
2154 { "cmovbS", { Gv
, Ev
}, 0 },
2155 { "cmovaeS", { Gv
, Ev
}, 0 },
2156 { "cmoveS", { Gv
, Ev
}, 0 },
2157 { "cmovneS", { Gv
, Ev
}, 0 },
2158 { "cmovbeS", { Gv
, Ev
}, 0 },
2159 { "cmovaS", { Gv
, Ev
}, 0 },
2161 { "cmovsS", { Gv
, Ev
}, 0 },
2162 { "cmovnsS", { Gv
, Ev
}, 0 },
2163 { "cmovpS", { Gv
, Ev
}, 0 },
2164 { "cmovnpS", { Gv
, Ev
}, 0 },
2165 { "cmovlS", { Gv
, Ev
}, 0 },
2166 { "cmovgeS", { Gv
, Ev
}, 0 },
2167 { "cmovleS", { Gv
, Ev
}, 0 },
2168 { "cmovgS", { Gv
, Ev
}, 0 },
2170 { MOD_TABLE (MOD_0F50
) },
2171 { PREFIX_TABLE (PREFIX_0F51
) },
2172 { PREFIX_TABLE (PREFIX_0F52
) },
2173 { PREFIX_TABLE (PREFIX_0F53
) },
2174 { "andpX", { XM
, EXx
}, PREFIX_OPCODE
},
2175 { "andnpX", { XM
, EXx
}, PREFIX_OPCODE
},
2176 { "orpX", { XM
, EXx
}, PREFIX_OPCODE
},
2177 { "xorpX", { XM
, EXx
}, PREFIX_OPCODE
},
2179 { PREFIX_TABLE (PREFIX_0F58
) },
2180 { PREFIX_TABLE (PREFIX_0F59
) },
2181 { PREFIX_TABLE (PREFIX_0F5A
) },
2182 { PREFIX_TABLE (PREFIX_0F5B
) },
2183 { PREFIX_TABLE (PREFIX_0F5C
) },
2184 { PREFIX_TABLE (PREFIX_0F5D
) },
2185 { PREFIX_TABLE (PREFIX_0F5E
) },
2186 { PREFIX_TABLE (PREFIX_0F5F
) },
2188 { PREFIX_TABLE (PREFIX_0F60
) },
2189 { PREFIX_TABLE (PREFIX_0F61
) },
2190 { PREFIX_TABLE (PREFIX_0F62
) },
2191 { "packsswb", { MX
, EM
}, PREFIX_OPCODE
},
2192 { "pcmpgtb", { MX
, EM
}, PREFIX_OPCODE
},
2193 { "pcmpgtw", { MX
, EM
}, PREFIX_OPCODE
},
2194 { "pcmpgtd", { MX
, EM
}, PREFIX_OPCODE
},
2195 { "packuswb", { MX
, EM
}, PREFIX_OPCODE
},
2197 { "punpckhbw", { MX
, EM
}, PREFIX_OPCODE
},
2198 { "punpckhwd", { MX
, EM
}, PREFIX_OPCODE
},
2199 { "punpckhdq", { MX
, EM
}, PREFIX_OPCODE
},
2200 { "packssdw", { MX
, EM
}, PREFIX_OPCODE
},
2201 { "punpcklqdq", { XM
, EXx
}, PREFIX_DATA
},
2202 { "punpckhqdq", { XM
, EXx
}, PREFIX_DATA
},
2203 { "movK", { MX
, Edq
}, PREFIX_OPCODE
},
2204 { PREFIX_TABLE (PREFIX_0F6F
) },
2206 { PREFIX_TABLE (PREFIX_0F70
) },
2207 { REG_TABLE (REG_0F71
) },
2208 { REG_TABLE (REG_0F72
) },
2209 { REG_TABLE (REG_0F73
) },
2210 { "pcmpeqb", { MX
, EM
}, PREFIX_OPCODE
},
2211 { "pcmpeqw", { MX
, EM
}, PREFIX_OPCODE
},
2212 { "pcmpeqd", { MX
, EM
}, PREFIX_OPCODE
},
2213 { "emms", { XX
}, PREFIX_OPCODE
},
2215 { PREFIX_TABLE (PREFIX_0F78
) },
2216 { PREFIX_TABLE (PREFIX_0F79
) },
2219 { PREFIX_TABLE (PREFIX_0F7C
) },
2220 { PREFIX_TABLE (PREFIX_0F7D
) },
2221 { PREFIX_TABLE (PREFIX_0F7E
) },
2222 { PREFIX_TABLE (PREFIX_0F7F
) },
2224 { "joH", { Jv
, BND
, cond_jump_flag
}, 0 },
2225 { "jnoH", { Jv
, BND
, cond_jump_flag
}, 0 },
2226 { "jbH", { Jv
, BND
, cond_jump_flag
}, 0 },
2227 { "jaeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2228 { "jeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2229 { "jneH", { Jv
, BND
, cond_jump_flag
}, 0 },
2230 { "jbeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2231 { "jaH", { Jv
, BND
, cond_jump_flag
}, 0 },
2233 { "jsH", { Jv
, BND
, cond_jump_flag
}, 0 },
2234 { "jnsH", { Jv
, BND
, cond_jump_flag
}, 0 },
2235 { "jpH", { Jv
, BND
, cond_jump_flag
}, 0 },
2236 { "jnpH", { Jv
, BND
, cond_jump_flag
}, 0 },
2237 { "jlH", { Jv
, BND
, cond_jump_flag
}, 0 },
2238 { "jgeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2239 { "jleH", { Jv
, BND
, cond_jump_flag
}, 0 },
2240 { "jgH", { Jv
, BND
, cond_jump_flag
}, 0 },
2242 { "seto", { Eb
}, 0 },
2243 { "setno", { Eb
}, 0 },
2244 { "setb", { Eb
}, 0 },
2245 { "setae", { Eb
}, 0 },
2246 { "sete", { Eb
}, 0 },
2247 { "setne", { Eb
}, 0 },
2248 { "setbe", { Eb
}, 0 },
2249 { "seta", { Eb
}, 0 },
2251 { "sets", { Eb
}, 0 },
2252 { "setns", { Eb
}, 0 },
2253 { "setp", { Eb
}, 0 },
2254 { "setnp", { Eb
}, 0 },
2255 { "setl", { Eb
}, 0 },
2256 { "setge", { Eb
}, 0 },
2257 { "setle", { Eb
}, 0 },
2258 { "setg", { Eb
}, 0 },
2260 { "pushP", { fs
}, 0 },
2261 { "popP", { fs
}, 0 },
2262 { "cpuid", { XX
}, 0 },
2263 { "btS", { Ev
, Gv
}, 0 },
2264 { "shldS", { Ev
, Gv
, Ib
}, 0 },
2265 { "shldS", { Ev
, Gv
, CL
}, 0 },
2266 { REG_TABLE (REG_0FA6
) },
2267 { REG_TABLE (REG_0FA7
) },
2269 { "pushP", { gs
}, 0 },
2270 { "popP", { gs
}, 0 },
2271 { "rsm", { XX
}, 0 },
2272 { "btsS", { Evh1
, Gv
}, 0 },
2273 { "shrdS", { Ev
, Gv
, Ib
}, 0 },
2274 { "shrdS", { Ev
, Gv
, CL
}, 0 },
2275 { REG_TABLE (REG_0FAE
) },
2276 { "imulS", { Gv
, Ev
}, 0 },
2278 { "cmpxchgB", { Ebh1
, Gb
}, 0 },
2279 { "cmpxchgS", { Evh1
, Gv
}, 0 },
2280 { MOD_TABLE (MOD_0FB2
) },
2281 { "btrS", { Evh1
, Gv
}, 0 },
2282 { MOD_TABLE (MOD_0FB4
) },
2283 { MOD_TABLE (MOD_0FB5
) },
2284 { "movz{bR|x}", { Gv
, Eb
}, 0 },
2285 { "movz{wR|x}", { Gv
, Ew
}, 0 }, /* yes, there really is movzww ! */
2287 { PREFIX_TABLE (PREFIX_0FB8
) },
2288 { "ud1S", { Gv
, Ev
}, 0 },
2289 { REG_TABLE (REG_0FBA
) },
2290 { "btcS", { Evh1
, Gv
}, 0 },
2291 { PREFIX_TABLE (PREFIX_0FBC
) },
2292 { PREFIX_TABLE (PREFIX_0FBD
) },
2293 { "movs{bR|x}", { Gv
, Eb
}, 0 },
2294 { "movs{wR|x}", { Gv
, Ew
}, 0 }, /* yes, there really is movsww ! */
2296 { "xaddB", { Ebh1
, Gb
}, 0 },
2297 { "xaddS", { Evh1
, Gv
}, 0 },
2298 { PREFIX_TABLE (PREFIX_0FC2
) },
2299 { MOD_TABLE (MOD_0FC3
) },
2300 { "pinsrw", { MX
, Edqw
, Ib
}, PREFIX_OPCODE
},
2301 { "pextrw", { Gdq
, MS
, Ib
}, PREFIX_OPCODE
},
2302 { "shufpX", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
2303 { REG_TABLE (REG_0FC7
) },
2305 { "bswap", { RMeAX
}, 0 },
2306 { "bswap", { RMeCX
}, 0 },
2307 { "bswap", { RMeDX
}, 0 },
2308 { "bswap", { RMeBX
}, 0 },
2309 { "bswap", { RMeSP
}, 0 },
2310 { "bswap", { RMeBP
}, 0 },
2311 { "bswap", { RMeSI
}, 0 },
2312 { "bswap", { RMeDI
}, 0 },
2314 { PREFIX_TABLE (PREFIX_0FD0
) },
2315 { "psrlw", { MX
, EM
}, PREFIX_OPCODE
},
2316 { "psrld", { MX
, EM
}, PREFIX_OPCODE
},
2317 { "psrlq", { MX
, EM
}, PREFIX_OPCODE
},
2318 { "paddq", { MX
, EM
}, PREFIX_OPCODE
},
2319 { "pmullw", { MX
, EM
}, PREFIX_OPCODE
},
2320 { PREFIX_TABLE (PREFIX_0FD6
) },
2321 { MOD_TABLE (MOD_0FD7
) },
2323 { "psubusb", { MX
, EM
}, PREFIX_OPCODE
},
2324 { "psubusw", { MX
, EM
}, PREFIX_OPCODE
},
2325 { "pminub", { MX
, EM
}, PREFIX_OPCODE
},
2326 { "pand", { MX
, EM
}, PREFIX_OPCODE
},
2327 { "paddusb", { MX
, EM
}, PREFIX_OPCODE
},
2328 { "paddusw", { MX
, EM
}, PREFIX_OPCODE
},
2329 { "pmaxub", { MX
, EM
}, PREFIX_OPCODE
},
2330 { "pandn", { MX
, EM
}, PREFIX_OPCODE
},
2332 { "pavgb", { MX
, EM
}, PREFIX_OPCODE
},
2333 { "psraw", { MX
, EM
}, PREFIX_OPCODE
},
2334 { "psrad", { MX
, EM
}, PREFIX_OPCODE
},
2335 { "pavgw", { MX
, EM
}, PREFIX_OPCODE
},
2336 { "pmulhuw", { MX
, EM
}, PREFIX_OPCODE
},
2337 { "pmulhw", { MX
, EM
}, PREFIX_OPCODE
},
2338 { PREFIX_TABLE (PREFIX_0FE6
) },
2339 { PREFIX_TABLE (PREFIX_0FE7
) },
2341 { "psubsb", { MX
, EM
}, PREFIX_OPCODE
},
2342 { "psubsw", { MX
, EM
}, PREFIX_OPCODE
},
2343 { "pminsw", { MX
, EM
}, PREFIX_OPCODE
},
2344 { "por", { MX
, EM
}, PREFIX_OPCODE
},
2345 { "paddsb", { MX
, EM
}, PREFIX_OPCODE
},
2346 { "paddsw", { MX
, EM
}, PREFIX_OPCODE
},
2347 { "pmaxsw", { MX
, EM
}, PREFIX_OPCODE
},
2348 { "pxor", { MX
, EM
}, PREFIX_OPCODE
},
2350 { PREFIX_TABLE (PREFIX_0FF0
) },
2351 { "psllw", { MX
, EM
}, PREFIX_OPCODE
},
2352 { "pslld", { MX
, EM
}, PREFIX_OPCODE
},
2353 { "psllq", { MX
, EM
}, PREFIX_OPCODE
},
2354 { "pmuludq", { MX
, EM
}, PREFIX_OPCODE
},
2355 { "pmaddwd", { MX
, EM
}, PREFIX_OPCODE
},
2356 { "psadbw", { MX
, EM
}, PREFIX_OPCODE
},
2357 { PREFIX_TABLE (PREFIX_0FF7
) },
2359 { "psubb", { MX
, EM
}, PREFIX_OPCODE
},
2360 { "psubw", { MX
, EM
}, PREFIX_OPCODE
},
2361 { "psubd", { MX
, EM
}, PREFIX_OPCODE
},
2362 { "psubq", { MX
, EM
}, PREFIX_OPCODE
},
2363 { "paddb", { MX
, EM
}, PREFIX_OPCODE
},
2364 { "paddw", { MX
, EM
}, PREFIX_OPCODE
},
2365 { "paddd", { MX
, EM
}, PREFIX_OPCODE
},
2366 { "ud0S", { Gv
, Ev
}, 0 },
2369 static const unsigned char onebyte_has_modrm
[256] = {
2370 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2371 /* ------------------------------- */
2372 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2373 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2374 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2375 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2376 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2377 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2378 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2379 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2380 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2381 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2382 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2383 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2384 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2385 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2386 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2387 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
2388 /* ------------------------------- */
2389 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2392 static const unsigned char twobyte_has_modrm
[256] = {
2393 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2394 /* ------------------------------- */
2395 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2396 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2397 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2398 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2399 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2400 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2401 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2402 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2403 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2404 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2405 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2406 /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2407 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2408 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2409 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2410 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 /* ff */
2411 /* ------------------------------- */
2412 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2415 static char obuf
[100];
2417 static char *mnemonicendp
;
2418 static char scratchbuf
[100];
2419 static unsigned char *start_codep
;
2420 static unsigned char *insn_codep
;
2421 static unsigned char *codep
;
2422 static unsigned char *end_codep
;
2423 static int last_lock_prefix
;
2424 static int last_repz_prefix
;
2425 static int last_repnz_prefix
;
2426 static int last_data_prefix
;
2427 static int last_addr_prefix
;
2428 static int last_rex_prefix
;
2429 static int last_seg_prefix
;
2430 static int fwait_prefix
;
2431 /* The active segment register prefix. */
2432 static int active_seg_prefix
;
2433 #define MAX_CODE_LENGTH 15
2434 /* We can up to 14 prefixes since the maximum instruction length is
2436 static int all_prefixes
[MAX_CODE_LENGTH
- 1];
2437 static disassemble_info
*the_info
;
2445 static unsigned char need_modrm
;
2455 int register_specifier
;
2462 int mask_register_specifier
;
2468 static unsigned char need_vex
;
2476 /* If we are accessing mod/rm/reg without need_modrm set, then the
2477 values are stale. Hitting this abort likely indicates that you
2478 need to update onebyte_has_modrm or twobyte_has_modrm. */
2479 #define MODRM_CHECK if (!need_modrm) abort ()
2481 static const char **names64
;
2482 static const char **names32
;
2483 static const char **names16
;
2484 static const char **names8
;
2485 static const char **names8rex
;
2486 static const char **names_seg
;
2487 static const char *index64
;
2488 static const char *index32
;
2489 static const char **index16
;
2490 static const char **names_bnd
;
2492 static const char *intel_names64
[] = {
2493 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2494 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2496 static const char *intel_names32
[] = {
2497 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
2498 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
2500 static const char *intel_names16
[] = {
2501 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
2502 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
2504 static const char *intel_names8
[] = {
2505 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2507 static const char *intel_names8rex
[] = {
2508 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2509 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2511 static const char *intel_names_seg
[] = {
2512 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2514 static const char *intel_index64
= "riz";
2515 static const char *intel_index32
= "eiz";
2516 static const char *intel_index16
[] = {
2517 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2520 static const char *att_names64
[] = {
2521 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2522 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2524 static const char *att_names32
[] = {
2525 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2526 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2528 static const char *att_names16
[] = {
2529 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2530 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2532 static const char *att_names8
[] = {
2533 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2535 static const char *att_names8rex
[] = {
2536 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2537 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2539 static const char *att_names_seg
[] = {
2540 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2542 static const char *att_index64
= "%riz";
2543 static const char *att_index32
= "%eiz";
2544 static const char *att_index16
[] = {
2545 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2548 static const char **names_mm
;
2549 static const char *intel_names_mm
[] = {
2550 "mm0", "mm1", "mm2", "mm3",
2551 "mm4", "mm5", "mm6", "mm7"
2553 static const char *att_names_mm
[] = {
2554 "%mm0", "%mm1", "%mm2", "%mm3",
2555 "%mm4", "%mm5", "%mm6", "%mm7"
2558 static const char *intel_names_bnd
[] = {
2559 "bnd0", "bnd1", "bnd2", "bnd3"
2562 static const char *att_names_bnd
[] = {
2563 "%bnd0", "%bnd1", "%bnd2", "%bnd3"
2566 static const char **names_xmm
;
2567 static const char *intel_names_xmm
[] = {
2568 "xmm0", "xmm1", "xmm2", "xmm3",
2569 "xmm4", "xmm5", "xmm6", "xmm7",
2570 "xmm8", "xmm9", "xmm10", "xmm11",
2571 "xmm12", "xmm13", "xmm14", "xmm15",
2572 "xmm16", "xmm17", "xmm18", "xmm19",
2573 "xmm20", "xmm21", "xmm22", "xmm23",
2574 "xmm24", "xmm25", "xmm26", "xmm27",
2575 "xmm28", "xmm29", "xmm30", "xmm31"
2577 static const char *att_names_xmm
[] = {
2578 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
2579 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
2580 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
2581 "%xmm12", "%xmm13", "%xmm14", "%xmm15",
2582 "%xmm16", "%xmm17", "%xmm18", "%xmm19",
2583 "%xmm20", "%xmm21", "%xmm22", "%xmm23",
2584 "%xmm24", "%xmm25", "%xmm26", "%xmm27",
2585 "%xmm28", "%xmm29", "%xmm30", "%xmm31"
2588 static const char **names_ymm
;
2589 static const char *intel_names_ymm
[] = {
2590 "ymm0", "ymm1", "ymm2", "ymm3",
2591 "ymm4", "ymm5", "ymm6", "ymm7",
2592 "ymm8", "ymm9", "ymm10", "ymm11",
2593 "ymm12", "ymm13", "ymm14", "ymm15",
2594 "ymm16", "ymm17", "ymm18", "ymm19",
2595 "ymm20", "ymm21", "ymm22", "ymm23",
2596 "ymm24", "ymm25", "ymm26", "ymm27",
2597 "ymm28", "ymm29", "ymm30", "ymm31"
2599 static const char *att_names_ymm
[] = {
2600 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
2601 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
2602 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
2603 "%ymm12", "%ymm13", "%ymm14", "%ymm15",
2604 "%ymm16", "%ymm17", "%ymm18", "%ymm19",
2605 "%ymm20", "%ymm21", "%ymm22", "%ymm23",
2606 "%ymm24", "%ymm25", "%ymm26", "%ymm27",
2607 "%ymm28", "%ymm29", "%ymm30", "%ymm31"
2610 static const char **names_zmm
;
2611 static const char *intel_names_zmm
[] = {
2612 "zmm0", "zmm1", "zmm2", "zmm3",
2613 "zmm4", "zmm5", "zmm6", "zmm7",
2614 "zmm8", "zmm9", "zmm10", "zmm11",
2615 "zmm12", "zmm13", "zmm14", "zmm15",
2616 "zmm16", "zmm17", "zmm18", "zmm19",
2617 "zmm20", "zmm21", "zmm22", "zmm23",
2618 "zmm24", "zmm25", "zmm26", "zmm27",
2619 "zmm28", "zmm29", "zmm30", "zmm31"
2621 static const char *att_names_zmm
[] = {
2622 "%zmm0", "%zmm1", "%zmm2", "%zmm3",
2623 "%zmm4", "%zmm5", "%zmm6", "%zmm7",
2624 "%zmm8", "%zmm9", "%zmm10", "%zmm11",
2625 "%zmm12", "%zmm13", "%zmm14", "%zmm15",
2626 "%zmm16", "%zmm17", "%zmm18", "%zmm19",
2627 "%zmm20", "%zmm21", "%zmm22", "%zmm23",
2628 "%zmm24", "%zmm25", "%zmm26", "%zmm27",
2629 "%zmm28", "%zmm29", "%zmm30", "%zmm31"
2632 static const char **names_tmm
;
2633 static const char *intel_names_tmm
[] = {
2634 "tmm0", "tmm1", "tmm2", "tmm3",
2635 "tmm4", "tmm5", "tmm6", "tmm7"
2637 static const char *att_names_tmm
[] = {
2638 "%tmm0", "%tmm1", "%tmm2", "%tmm3",
2639 "%tmm4", "%tmm5", "%tmm6", "%tmm7"
2642 static const char **names_mask
;
2643 static const char *intel_names_mask
[] = {
2644 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
2646 static const char *att_names_mask
[] = {
2647 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
2650 static const char *names_rounding
[] =
2658 static const struct dis386 reg_table
[][8] = {
2661 { "addA", { Ebh1
, Ib
}, 0 },
2662 { "orA", { Ebh1
, Ib
}, 0 },
2663 { "adcA", { Ebh1
, Ib
}, 0 },
2664 { "sbbA", { Ebh1
, Ib
}, 0 },
2665 { "andA", { Ebh1
, Ib
}, 0 },
2666 { "subA", { Ebh1
, Ib
}, 0 },
2667 { "xorA", { Ebh1
, Ib
}, 0 },
2668 { "cmpA", { Eb
, Ib
}, 0 },
2672 { "addQ", { Evh1
, Iv
}, 0 },
2673 { "orQ", { Evh1
, Iv
}, 0 },
2674 { "adcQ", { Evh1
, Iv
}, 0 },
2675 { "sbbQ", { Evh1
, Iv
}, 0 },
2676 { "andQ", { Evh1
, Iv
}, 0 },
2677 { "subQ", { Evh1
, Iv
}, 0 },
2678 { "xorQ", { Evh1
, Iv
}, 0 },
2679 { "cmpQ", { Ev
, Iv
}, 0 },
2683 { "addQ", { Evh1
, sIb
}, 0 },
2684 { "orQ", { Evh1
, sIb
}, 0 },
2685 { "adcQ", { Evh1
, sIb
}, 0 },
2686 { "sbbQ", { Evh1
, sIb
}, 0 },
2687 { "andQ", { Evh1
, sIb
}, 0 },
2688 { "subQ", { Evh1
, sIb
}, 0 },
2689 { "xorQ", { Evh1
, sIb
}, 0 },
2690 { "cmpQ", { Ev
, sIb
}, 0 },
2694 { "pop{P|}", { stackEv
}, 0 },
2695 { XOP_8F_TABLE (XOP_09
) },
2699 { XOP_8F_TABLE (XOP_09
) },
2703 { "rolA", { Eb
, Ib
}, 0 },
2704 { "rorA", { Eb
, Ib
}, 0 },
2705 { "rclA", { Eb
, Ib
}, 0 },
2706 { "rcrA", { Eb
, Ib
}, 0 },
2707 { "shlA", { Eb
, Ib
}, 0 },
2708 { "shrA", { Eb
, Ib
}, 0 },
2709 { "shlA", { Eb
, Ib
}, 0 },
2710 { "sarA", { Eb
, Ib
}, 0 },
2714 { "rolQ", { Ev
, Ib
}, 0 },
2715 { "rorQ", { Ev
, Ib
}, 0 },
2716 { "rclQ", { Ev
, Ib
}, 0 },
2717 { "rcrQ", { Ev
, Ib
}, 0 },
2718 { "shlQ", { Ev
, Ib
}, 0 },
2719 { "shrQ", { Ev
, Ib
}, 0 },
2720 { "shlQ", { Ev
, Ib
}, 0 },
2721 { "sarQ", { Ev
, Ib
}, 0 },
2725 { "movA", { Ebh3
, Ib
}, 0 },
2732 { MOD_TABLE (MOD_C6_REG_7
) },
2736 { "movQ", { Evh3
, Iv
}, 0 },
2743 { MOD_TABLE (MOD_C7_REG_7
) },
2747 { "rolA", { Eb
, I1
}, 0 },
2748 { "rorA", { Eb
, I1
}, 0 },
2749 { "rclA", { Eb
, I1
}, 0 },
2750 { "rcrA", { Eb
, I1
}, 0 },
2751 { "shlA", { Eb
, I1
}, 0 },
2752 { "shrA", { Eb
, I1
}, 0 },
2753 { "shlA", { Eb
, I1
}, 0 },
2754 { "sarA", { Eb
, I1
}, 0 },
2758 { "rolQ", { Ev
, I1
}, 0 },
2759 { "rorQ", { Ev
, I1
}, 0 },
2760 { "rclQ", { Ev
, I1
}, 0 },
2761 { "rcrQ", { Ev
, I1
}, 0 },
2762 { "shlQ", { Ev
, I1
}, 0 },
2763 { "shrQ", { Ev
, I1
}, 0 },
2764 { "shlQ", { Ev
, I1
}, 0 },
2765 { "sarQ", { Ev
, I1
}, 0 },
2769 { "rolA", { Eb
, CL
}, 0 },
2770 { "rorA", { Eb
, CL
}, 0 },
2771 { "rclA", { Eb
, CL
}, 0 },
2772 { "rcrA", { Eb
, CL
}, 0 },
2773 { "shlA", { Eb
, CL
}, 0 },
2774 { "shrA", { Eb
, CL
}, 0 },
2775 { "shlA", { Eb
, CL
}, 0 },
2776 { "sarA", { Eb
, CL
}, 0 },
2780 { "rolQ", { Ev
, CL
}, 0 },
2781 { "rorQ", { Ev
, CL
}, 0 },
2782 { "rclQ", { Ev
, CL
}, 0 },
2783 { "rcrQ", { Ev
, CL
}, 0 },
2784 { "shlQ", { Ev
, CL
}, 0 },
2785 { "shrQ", { Ev
, CL
}, 0 },
2786 { "shlQ", { Ev
, CL
}, 0 },
2787 { "sarQ", { Ev
, CL
}, 0 },
2791 { "testA", { Eb
, Ib
}, 0 },
2792 { "testA", { Eb
, Ib
}, 0 },
2793 { "notA", { Ebh1
}, 0 },
2794 { "negA", { Ebh1
}, 0 },
2795 { "mulA", { Eb
}, 0 }, /* Don't print the implicit %al register, */
2796 { "imulA", { Eb
}, 0 }, /* to distinguish these opcodes from other */
2797 { "divA", { Eb
}, 0 }, /* mul/imul opcodes. Do the same for div */
2798 { "idivA", { Eb
}, 0 }, /* and idiv for consistency. */
2802 { "testQ", { Ev
, Iv
}, 0 },
2803 { "testQ", { Ev
, Iv
}, 0 },
2804 { "notQ", { Evh1
}, 0 },
2805 { "negQ", { Evh1
}, 0 },
2806 { "mulQ", { Ev
}, 0 }, /* Don't print the implicit register. */
2807 { "imulQ", { Ev
}, 0 },
2808 { "divQ", { Ev
}, 0 },
2809 { "idivQ", { Ev
}, 0 },
2813 { "incA", { Ebh1
}, 0 },
2814 { "decA", { Ebh1
}, 0 },
2818 { "incQ", { Evh1
}, 0 },
2819 { "decQ", { Evh1
}, 0 },
2820 { "call{@|}", { NOTRACK
, indirEv
, BND
}, 0 },
2821 { MOD_TABLE (MOD_FF_REG_3
) },
2822 { "jmp{@|}", { NOTRACK
, indirEv
, BND
}, 0 },
2823 { MOD_TABLE (MOD_FF_REG_5
) },
2824 { "push{P|}", { stackEv
}, 0 },
2829 { "sldtD", { Sv
}, 0 },
2830 { "strD", { Sv
}, 0 },
2831 { "lldt", { Ew
}, 0 },
2832 { "ltr", { Ew
}, 0 },
2833 { "verr", { Ew
}, 0 },
2834 { "verw", { Ew
}, 0 },
2840 { MOD_TABLE (MOD_0F01_REG_0
) },
2841 { MOD_TABLE (MOD_0F01_REG_1
) },
2842 { MOD_TABLE (MOD_0F01_REG_2
) },
2843 { MOD_TABLE (MOD_0F01_REG_3
) },
2844 { "smswD", { Sv
}, 0 },
2845 { MOD_TABLE (MOD_0F01_REG_5
) },
2846 { "lmsw", { Ew
}, 0 },
2847 { MOD_TABLE (MOD_0F01_REG_7
) },
2851 { "prefetch", { Mb
}, 0 },
2852 { "prefetchw", { Mb
}, 0 },
2853 { "prefetchwt1", { Mb
}, 0 },
2854 { "prefetch", { Mb
}, 0 },
2855 { "prefetch", { Mb
}, 0 },
2856 { "prefetch", { Mb
}, 0 },
2857 { "prefetch", { Mb
}, 0 },
2858 { "prefetch", { Mb
}, 0 },
2862 { MOD_TABLE (MOD_0F18_REG_0
) },
2863 { MOD_TABLE (MOD_0F18_REG_1
) },
2864 { MOD_TABLE (MOD_0F18_REG_2
) },
2865 { MOD_TABLE (MOD_0F18_REG_3
) },
2866 { MOD_TABLE (MOD_0F18_REG_4
) },
2867 { MOD_TABLE (MOD_0F18_REG_5
) },
2868 { MOD_TABLE (MOD_0F18_REG_6
) },
2869 { MOD_TABLE (MOD_0F18_REG_7
) },
2871 /* REG_0F1C_P_0_MOD_0 */
2873 { "cldemote", { Mb
}, 0 },
2874 { "nopQ", { Ev
}, 0 },
2875 { "nopQ", { Ev
}, 0 },
2876 { "nopQ", { Ev
}, 0 },
2877 { "nopQ", { Ev
}, 0 },
2878 { "nopQ", { Ev
}, 0 },
2879 { "nopQ", { Ev
}, 0 },
2880 { "nopQ", { Ev
}, 0 },
2882 /* REG_0F1E_P_1_MOD_3 */
2884 { "nopQ", { Ev
}, 0 },
2885 { "rdsspK", { Edq
}, PREFIX_OPCODE
},
2886 { "nopQ", { Ev
}, 0 },
2887 { "nopQ", { Ev
}, 0 },
2888 { "nopQ", { Ev
}, 0 },
2889 { "nopQ", { Ev
}, 0 },
2890 { "nopQ", { Ev
}, 0 },
2891 { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7
) },
2897 { MOD_TABLE (MOD_0F71_REG_2
) },
2899 { MOD_TABLE (MOD_0F71_REG_4
) },
2901 { MOD_TABLE (MOD_0F71_REG_6
) },
2907 { MOD_TABLE (MOD_0F72_REG_2
) },
2909 { MOD_TABLE (MOD_0F72_REG_4
) },
2911 { MOD_TABLE (MOD_0F72_REG_6
) },
2917 { MOD_TABLE (MOD_0F73_REG_2
) },
2918 { MOD_TABLE (MOD_0F73_REG_3
) },
2921 { MOD_TABLE (MOD_0F73_REG_6
) },
2922 { MOD_TABLE (MOD_0F73_REG_7
) },
2926 { "montmul", { { OP_0f07
, 0 } }, 0 },
2927 { "xsha1", { { OP_0f07
, 0 } }, 0 },
2928 { "xsha256", { { OP_0f07
, 0 } }, 0 },
2932 { "xstore-rng", { { OP_0f07
, 0 } }, 0 },
2933 { "xcrypt-ecb", { { OP_0f07
, 0 } }, 0 },
2934 { "xcrypt-cbc", { { OP_0f07
, 0 } }, 0 },
2935 { "xcrypt-ctr", { { OP_0f07
, 0 } }, 0 },
2936 { "xcrypt-cfb", { { OP_0f07
, 0 } }, 0 },
2937 { "xcrypt-ofb", { { OP_0f07
, 0 } }, 0 },
2941 { MOD_TABLE (MOD_0FAE_REG_0
) },
2942 { MOD_TABLE (MOD_0FAE_REG_1
) },
2943 { MOD_TABLE (MOD_0FAE_REG_2
) },
2944 { MOD_TABLE (MOD_0FAE_REG_3
) },
2945 { MOD_TABLE (MOD_0FAE_REG_4
) },
2946 { MOD_TABLE (MOD_0FAE_REG_5
) },
2947 { MOD_TABLE (MOD_0FAE_REG_6
) },
2948 { MOD_TABLE (MOD_0FAE_REG_7
) },
2956 { "btQ", { Ev
, Ib
}, 0 },
2957 { "btsQ", { Evh1
, Ib
}, 0 },
2958 { "btrQ", { Evh1
, Ib
}, 0 },
2959 { "btcQ", { Evh1
, Ib
}, 0 },
2964 { "cmpxchg8b", { { CMPXCHG8B_Fixup
, q_mode
} }, 0 },
2966 { MOD_TABLE (MOD_0FC7_REG_3
) },
2967 { MOD_TABLE (MOD_0FC7_REG_4
) },
2968 { MOD_TABLE (MOD_0FC7_REG_5
) },
2969 { MOD_TABLE (MOD_0FC7_REG_6
) },
2970 { MOD_TABLE (MOD_0FC7_REG_7
) },
2976 { MOD_TABLE (MOD_VEX_0F71_REG_2
) },
2978 { MOD_TABLE (MOD_VEX_0F71_REG_4
) },
2980 { MOD_TABLE (MOD_VEX_0F71_REG_6
) },
2986 { MOD_TABLE (MOD_VEX_0F72_REG_2
) },
2988 { MOD_TABLE (MOD_VEX_0F72_REG_4
) },
2990 { MOD_TABLE (MOD_VEX_0F72_REG_6
) },
2996 { MOD_TABLE (MOD_VEX_0F73_REG_2
) },
2997 { MOD_TABLE (MOD_VEX_0F73_REG_3
) },
3000 { MOD_TABLE (MOD_VEX_0F73_REG_6
) },
3001 { MOD_TABLE (MOD_VEX_0F73_REG_7
) },
3007 { MOD_TABLE (MOD_VEX_0FAE_REG_2
) },
3008 { MOD_TABLE (MOD_VEX_0FAE_REG_3
) },
3010 /* REG_VEX_0F3849_X86_64_P_0_W_0_M_1 */
3012 { RM_TABLE (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0
) },
3014 /* REG_VEX_0F38F3 */
3017 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1
) },
3018 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2
) },
3019 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3
) },
3021 /* REG_0FXOP_09_01_L_0 */
3024 { "blcfill", { VexGdq
, Edq
}, 0 },
3025 { "blsfill", { VexGdq
, Edq
}, 0 },
3026 { "blcs", { VexGdq
, Edq
}, 0 },
3027 { "tzmsk", { VexGdq
, Edq
}, 0 },
3028 { "blcic", { VexGdq
, Edq
}, 0 },
3029 { "blsic", { VexGdq
, Edq
}, 0 },
3030 { "t1mskc", { VexGdq
, Edq
}, 0 },
3032 /* REG_0FXOP_09_02_L_0 */
3035 { "blcmsk", { VexGdq
, Edq
}, 0 },
3040 { "blci", { VexGdq
, Edq
}, 0 },
3042 /* REG_0FXOP_09_12_M_1_L_0 */
3044 { "llwpcb", { Edq
}, 0 },
3045 { "slwpcb", { Edq
}, 0 },
3047 /* REG_0FXOP_0A_12_L_0 */
3049 { "lwpins", { VexGdq
, Ed
, Id
}, 0 },
3050 { "lwpval", { VexGdq
, Ed
, Id
}, 0 },
3053 #include "i386-dis-evex-reg.h"
3056 static const struct dis386 prefix_table
[][4] = {
3059 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} }, 0 },
3060 { "pause", { XX
}, 0 },
3061 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} }, 0 },
3062 { NULL
, { { NULL
, 0 } }, PREFIX_IGNORED
}
3065 /* PREFIX_0F01_REG_3_RM_1 */
3067 { "vmmcall", { Skip_MODRM
}, 0 },
3068 { "vmgexit", { Skip_MODRM
}, 0 },
3070 { "vmgexit", { Skip_MODRM
}, 0 },
3073 /* PREFIX_0F01_REG_5_MOD_0 */
3076 { "rstorssp", { Mq
}, PREFIX_OPCODE
},
3079 /* PREFIX_0F01_REG_5_MOD_3_RM_0 */
3081 { "serialize", { Skip_MODRM
}, PREFIX_OPCODE
},
3082 { "setssbsy", { Skip_MODRM
}, PREFIX_OPCODE
},
3084 { "xsusldtrk", { Skip_MODRM
}, PREFIX_OPCODE
},
3087 /* PREFIX_0F01_REG_5_MOD_3_RM_1 */
3092 { "xresldtrk", { Skip_MODRM
}, PREFIX_OPCODE
},
3095 /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
3098 { "saveprevssp", { Skip_MODRM
}, PREFIX_OPCODE
},
3101 /* PREFIX_0F01_REG_7_MOD_3_RM_2 */
3103 { "monitorx", { { OP_Monitor
, 0 } }, 0 },
3104 { "mcommit", { Skip_MODRM
}, 0 },
3109 { "wbinvd", { XX
}, 0 },
3110 { "wbnoinvd", { XX
}, 0 },
3115 { "movups", { XM
, EXx
}, PREFIX_OPCODE
},
3116 { "movss", { XM
, EXd
}, PREFIX_OPCODE
},
3117 { "movupd", { XM
, EXx
}, PREFIX_OPCODE
},
3118 { "movsd", { XM
, EXq
}, PREFIX_OPCODE
},
3123 { "movups", { EXxS
, XM
}, PREFIX_OPCODE
},
3124 { "movss", { EXdS
, XM
}, PREFIX_OPCODE
},
3125 { "movupd", { EXxS
, XM
}, PREFIX_OPCODE
},
3126 { "movsd", { EXqS
, XM
}, PREFIX_OPCODE
},
3131 { MOD_TABLE (MOD_0F12_PREFIX_0
) },
3132 { "movsldup", { XM
, EXx
}, PREFIX_OPCODE
},
3133 { MOD_TABLE (MOD_0F12_PREFIX_2
) },
3134 { "movddup", { XM
, EXq
}, PREFIX_OPCODE
},
3139 { MOD_TABLE (MOD_0F16_PREFIX_0
) },
3140 { "movshdup", { XM
, EXx
}, PREFIX_OPCODE
},
3141 { MOD_TABLE (MOD_0F16_PREFIX_2
) },
3146 { MOD_TABLE (MOD_0F1A_PREFIX_0
) },
3147 { "bndcl", { Gbnd
, Ev_bnd
}, 0 },
3148 { "bndmov", { Gbnd
, Ebnd
}, 0 },
3149 { "bndcu", { Gbnd
, Ev_bnd
}, 0 },
3154 { MOD_TABLE (MOD_0F1B_PREFIX_0
) },
3155 { MOD_TABLE (MOD_0F1B_PREFIX_1
) },
3156 { "bndmov", { EbndS
, Gbnd
}, 0 },
3157 { "bndcn", { Gbnd
, Ev_bnd
}, 0 },
3162 { MOD_TABLE (MOD_0F1C_PREFIX_0
) },
3163 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3164 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3165 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3170 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3171 { MOD_TABLE (MOD_0F1E_PREFIX_1
) },
3172 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3173 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3178 { "cvtpi2ps", { XM
, EMCq
}, PREFIX_OPCODE
},
3179 { "cvtsi2ss{%LQ|}", { XM
, Edq
}, PREFIX_OPCODE
},
3180 { "cvtpi2pd", { XM
, EMCq
}, PREFIX_OPCODE
},
3181 { "cvtsi2sd{%LQ|}", { XM
, Edq
}, 0 },
3186 { MOD_TABLE (MOD_0F2B_PREFIX_0
) },
3187 { MOD_TABLE (MOD_0F2B_PREFIX_1
) },
3188 { MOD_TABLE (MOD_0F2B_PREFIX_2
) },
3189 { MOD_TABLE (MOD_0F2B_PREFIX_3
) },
3194 { "cvttps2pi", { MXC
, EXq
}, PREFIX_OPCODE
},
3195 { "cvttss2si", { Gdq
, EXd
}, PREFIX_OPCODE
},
3196 { "cvttpd2pi", { MXC
, EXx
}, PREFIX_OPCODE
},
3197 { "cvttsd2si", { Gdq
, EXq
}, PREFIX_OPCODE
},
3202 { "cvtps2pi", { MXC
, EXq
}, PREFIX_OPCODE
},
3203 { "cvtss2si", { Gdq
, EXd
}, PREFIX_OPCODE
},
3204 { "cvtpd2pi", { MXC
, EXx
}, PREFIX_OPCODE
},
3205 { "cvtsd2si", { Gdq
, EXq
}, PREFIX_OPCODE
},
3210 { "ucomiss",{ XM
, EXd
}, 0 },
3212 { "ucomisd",{ XM
, EXq
}, 0 },
3217 { "comiss", { XM
, EXd
}, 0 },
3219 { "comisd", { XM
, EXq
}, 0 },
3224 { "sqrtps", { XM
, EXx
}, PREFIX_OPCODE
},
3225 { "sqrtss", { XM
, EXd
}, PREFIX_OPCODE
},
3226 { "sqrtpd", { XM
, EXx
}, PREFIX_OPCODE
},
3227 { "sqrtsd", { XM
, EXq
}, PREFIX_OPCODE
},
3232 { "rsqrtps",{ XM
, EXx
}, PREFIX_OPCODE
},
3233 { "rsqrtss",{ XM
, EXd
}, PREFIX_OPCODE
},
3238 { "rcpps", { XM
, EXx
}, PREFIX_OPCODE
},
3239 { "rcpss", { XM
, EXd
}, PREFIX_OPCODE
},
3244 { "addps", { XM
, EXx
}, PREFIX_OPCODE
},
3245 { "addss", { XM
, EXd
}, PREFIX_OPCODE
},
3246 { "addpd", { XM
, EXx
}, PREFIX_OPCODE
},
3247 { "addsd", { XM
, EXq
}, PREFIX_OPCODE
},
3252 { "mulps", { XM
, EXx
}, PREFIX_OPCODE
},
3253 { "mulss", { XM
, EXd
}, PREFIX_OPCODE
},
3254 { "mulpd", { XM
, EXx
}, PREFIX_OPCODE
},
3255 { "mulsd", { XM
, EXq
}, PREFIX_OPCODE
},
3260 { "cvtps2pd", { XM
, EXq
}, PREFIX_OPCODE
},
3261 { "cvtss2sd", { XM
, EXd
}, PREFIX_OPCODE
},
3262 { "cvtpd2ps", { XM
, EXx
}, PREFIX_OPCODE
},
3263 { "cvtsd2ss", { XM
, EXq
}, PREFIX_OPCODE
},
3268 { "cvtdq2ps", { XM
, EXx
}, PREFIX_OPCODE
},
3269 { "cvttps2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3270 { "cvtps2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3275 { "subps", { XM
, EXx
}, PREFIX_OPCODE
},
3276 { "subss", { XM
, EXd
}, PREFIX_OPCODE
},
3277 { "subpd", { XM
, EXx
}, PREFIX_OPCODE
},
3278 { "subsd", { XM
, EXq
}, PREFIX_OPCODE
},
3283 { "minps", { XM
, EXx
}, PREFIX_OPCODE
},
3284 { "minss", { XM
, EXd
}, PREFIX_OPCODE
},
3285 { "minpd", { XM
, EXx
}, PREFIX_OPCODE
},
3286 { "minsd", { XM
, EXq
}, PREFIX_OPCODE
},
3291 { "divps", { XM
, EXx
}, PREFIX_OPCODE
},
3292 { "divss", { XM
, EXd
}, PREFIX_OPCODE
},
3293 { "divpd", { XM
, EXx
}, PREFIX_OPCODE
},
3294 { "divsd", { XM
, EXq
}, PREFIX_OPCODE
},
3299 { "maxps", { XM
, EXx
}, PREFIX_OPCODE
},
3300 { "maxss", { XM
, EXd
}, PREFIX_OPCODE
},
3301 { "maxpd", { XM
, EXx
}, PREFIX_OPCODE
},
3302 { "maxsd", { XM
, EXq
}, PREFIX_OPCODE
},
3307 { "punpcklbw",{ MX
, EMd
}, PREFIX_OPCODE
},
3309 { "punpcklbw",{ MX
, EMx
}, PREFIX_OPCODE
},
3314 { "punpcklwd",{ MX
, EMd
}, PREFIX_OPCODE
},
3316 { "punpcklwd",{ MX
, EMx
}, PREFIX_OPCODE
},
3321 { "punpckldq",{ MX
, EMd
}, PREFIX_OPCODE
},
3323 { "punpckldq",{ MX
, EMx
}, PREFIX_OPCODE
},
3328 { "movq", { MX
, EM
}, PREFIX_OPCODE
},
3329 { "movdqu", { XM
, EXx
}, PREFIX_OPCODE
},
3330 { "movdqa", { XM
, EXx
}, PREFIX_OPCODE
},
3335 { "pshufw", { MX
, EM
, Ib
}, PREFIX_OPCODE
},
3336 { "pshufhw",{ XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3337 { "pshufd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3338 { "pshuflw",{ XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3343 {"vmread", { Em
, Gm
}, 0 },
3345 {"extrq", { XS
, Ib
, Ib
}, 0 },
3346 {"insertq", { XM
, XS
, Ib
, Ib
}, 0 },
3351 {"vmwrite", { Gm
, Em
}, 0 },
3353 {"extrq", { XM
, XS
}, 0 },
3354 {"insertq", { XM
, XS
}, 0 },
3361 { "haddpd", { XM
, EXx
}, PREFIX_OPCODE
},
3362 { "haddps", { XM
, EXx
}, PREFIX_OPCODE
},
3369 { "hsubpd", { XM
, EXx
}, PREFIX_OPCODE
},
3370 { "hsubps", { XM
, EXx
}, PREFIX_OPCODE
},
3375 { "movK", { Edq
, MX
}, PREFIX_OPCODE
},
3376 { "movq", { XM
, EXq
}, PREFIX_OPCODE
},
3377 { "movK", { Edq
, XM
}, PREFIX_OPCODE
},
3382 { "movq", { EMS
, MX
}, PREFIX_OPCODE
},
3383 { "movdqu", { EXxS
, XM
}, PREFIX_OPCODE
},
3384 { "movdqa", { EXxS
, XM
}, PREFIX_OPCODE
},
3387 /* PREFIX_0FAE_REG_0_MOD_3 */
3390 { "rdfsbase", { Ev
}, 0 },
3393 /* PREFIX_0FAE_REG_1_MOD_3 */
3396 { "rdgsbase", { Ev
}, 0 },
3399 /* PREFIX_0FAE_REG_2_MOD_3 */
3402 { "wrfsbase", { Ev
}, 0 },
3405 /* PREFIX_0FAE_REG_3_MOD_3 */
3408 { "wrgsbase", { Ev
}, 0 },
3411 /* PREFIX_0FAE_REG_4_MOD_0 */
3413 { "xsave", { FXSAVE
}, 0 },
3414 { "ptwrite{%LQ|}", { Edq
}, 0 },
3417 /* PREFIX_0FAE_REG_4_MOD_3 */
3420 { "ptwrite{%LQ|}", { Edq
}, 0 },
3423 /* PREFIX_0FAE_REG_5_MOD_3 */
3425 { "lfence", { Skip_MODRM
}, 0 },
3426 { "incsspK", { Edq
}, PREFIX_OPCODE
},
3429 /* PREFIX_0FAE_REG_6_MOD_0 */
3431 { "xsaveopt", { FXSAVE
}, PREFIX_OPCODE
},
3432 { "clrssbsy", { Mq
}, PREFIX_OPCODE
},
3433 { "clwb", { Mb
}, PREFIX_OPCODE
},
3436 /* PREFIX_0FAE_REG_6_MOD_3 */
3438 { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0
) },
3439 { "umonitor", { Eva
}, PREFIX_OPCODE
},
3440 { "tpause", { Edq
}, PREFIX_OPCODE
},
3441 { "umwait", { Edq
}, PREFIX_OPCODE
},
3444 /* PREFIX_0FAE_REG_7_MOD_0 */
3446 { "clflush", { Mb
}, 0 },
3448 { "clflushopt", { Mb
}, 0 },
3454 { "popcntS", { Gv
, Ev
}, 0 },
3459 { "bsfS", { Gv
, Ev
}, 0 },
3460 { "tzcntS", { Gv
, Ev
}, 0 },
3461 { "bsfS", { Gv
, Ev
}, 0 },
3466 { "bsrS", { Gv
, Ev
}, 0 },
3467 { "lzcntS", { Gv
, Ev
}, 0 },
3468 { "bsrS", { Gv
, Ev
}, 0 },
3473 { "cmpps", { XM
, EXx
, CMP
}, PREFIX_OPCODE
},
3474 { "cmpss", { XM
, EXd
, CMP
}, PREFIX_OPCODE
},
3475 { "cmppd", { XM
, EXx
, CMP
}, PREFIX_OPCODE
},
3476 { "cmpsd", { XM
, EXq
, CMP
}, PREFIX_OPCODE
},
3479 /* PREFIX_0FC7_REG_6_MOD_0 */
3481 { "vmptrld",{ Mq
}, 0 },
3482 { "vmxon", { Mq
}, 0 },
3483 { "vmclear",{ Mq
}, 0 },
3486 /* PREFIX_0FC7_REG_6_MOD_3 */
3488 { "rdrand", { Ev
}, 0 },
3490 { "rdrand", { Ev
}, 0 }
3493 /* PREFIX_0FC7_REG_7_MOD_3 */
3495 { "rdseed", { Ev
}, 0 },
3496 { "rdpid", { Em
}, 0 },
3497 { "rdseed", { Ev
}, 0 },
3504 { "addsubpd", { XM
, EXx
}, 0 },
3505 { "addsubps", { XM
, EXx
}, 0 },
3511 { "movq2dq",{ XM
, MS
}, 0 },
3512 { "movq", { EXqS
, XM
}, 0 },
3513 { "movdq2q",{ MX
, XS
}, 0 },
3519 { "cvtdq2pd", { XM
, EXq
}, PREFIX_OPCODE
},
3520 { "cvttpd2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3521 { "cvtpd2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3526 { "movntq", { Mq
, MX
}, PREFIX_OPCODE
},
3528 { MOD_TABLE (MOD_0FE7_PREFIX_2
) },
3536 { MOD_TABLE (MOD_0FF0_PREFIX_3
) },
3541 { "maskmovq", { MX
, MS
}, PREFIX_OPCODE
},
3543 { "maskmovdqu", { XM
, XS
}, PREFIX_OPCODE
},
3548 { "movbeS", { Gv
, Mv
}, PREFIX_OPCODE
},
3550 { "movbeS", { Gv
, Mv
}, PREFIX_OPCODE
},
3551 { "crc32A", { Gdq
, Eb
}, PREFIX_OPCODE
},
3556 { "movbeS", { Mv
, Gv
}, PREFIX_OPCODE
},
3558 { "movbeS", { Mv
, Gv
}, PREFIX_OPCODE
},
3559 { "crc32Q", { Gdq
, Ev
}, PREFIX_OPCODE
},
3564 { MOD_TABLE (MOD_0F38F6_PREFIX_0
) },
3565 { "adoxS", { Gdq
, Edq
}, PREFIX_OPCODE
},
3566 { "adcxS", { Gdq
, Edq
}, PREFIX_OPCODE
},
3573 { MOD_TABLE (MOD_0F38F8_PREFIX_1
) },
3574 { MOD_TABLE (MOD_0F38F8_PREFIX_2
) },
3575 { MOD_TABLE (MOD_0F38F8_PREFIX_3
) },
3578 /* PREFIX_VEX_0F10 */
3580 { "vmovups", { XM
, EXx
}, 0 },
3581 { "vmovss", { XMScalar
, VexScalarR
, EXxmm_md
}, 0 },
3582 { "vmovupd", { XM
, EXx
}, 0 },
3583 { "vmovsd", { XMScalar
, VexScalarR
, EXxmm_mq
}, 0 },
3586 /* PREFIX_VEX_0F11 */
3588 { "vmovups", { EXxS
, XM
}, 0 },
3589 { "vmovss", { EXdS
, VexScalarR
, XMScalar
}, 0 },
3590 { "vmovupd", { EXxS
, XM
}, 0 },
3591 { "vmovsd", { EXqS
, VexScalarR
, XMScalar
}, 0 },
3594 /* PREFIX_VEX_0F12 */
3596 { MOD_TABLE (MOD_VEX_0F12_PREFIX_0
) },
3597 { "vmovsldup", { XM
, EXx
}, 0 },
3598 { MOD_TABLE (MOD_VEX_0F12_PREFIX_2
) },
3599 { "vmovddup", { XM
, EXymmq
}, 0 },
3602 /* PREFIX_VEX_0F16 */
3604 { MOD_TABLE (MOD_VEX_0F16_PREFIX_0
) },
3605 { "vmovshdup", { XM
, EXx
}, 0 },
3606 { MOD_TABLE (MOD_VEX_0F16_PREFIX_2
) },
3609 /* PREFIX_VEX_0F2A */
3612 { "vcvtsi2ss{%LQ|}", { XMScalar
, VexScalar
, Edq
}, 0 },
3614 { "vcvtsi2sd{%LQ|}", { XMScalar
, VexScalar
, Edq
}, 0 },
3617 /* PREFIX_VEX_0F2C */
3620 { "vcvttss2si", { Gdq
, EXxmm_md
, EXxEVexS
}, 0 },
3622 { "vcvttsd2si", { Gdq
, EXxmm_mq
, EXxEVexS
}, 0 },
3625 /* PREFIX_VEX_0F2D */
3628 { "vcvtss2si", { Gdq
, EXxmm_md
, EXxEVexR
}, 0 },
3630 { "vcvtsd2si", { Gdq
, EXxmm_mq
, EXxEVexR
}, 0 },
3633 /* PREFIX_VEX_0F2E */
3635 { "vucomisX", { XMScalar
, EXxmm_md
, EXxEVexS
}, PREFIX_OPCODE
},
3637 { "vucomisX", { XMScalar
, EXxmm_mq
, EXxEVexS
}, PREFIX_OPCODE
},
3640 /* PREFIX_VEX_0F2F */
3642 { "vcomisX", { XMScalar
, EXxmm_md
, EXxEVexS
}, PREFIX_OPCODE
},
3644 { "vcomisX", { XMScalar
, EXxmm_mq
, EXxEVexS
}, PREFIX_OPCODE
},
3647 /* PREFIX_VEX_0F41 */
3649 { VEX_LEN_TABLE (VEX_LEN_0F41_P_0
) },
3651 { VEX_LEN_TABLE (VEX_LEN_0F41_P_2
) },
3654 /* PREFIX_VEX_0F42 */
3656 { VEX_LEN_TABLE (VEX_LEN_0F42_P_0
) },
3658 { VEX_LEN_TABLE (VEX_LEN_0F42_P_2
) },
3661 /* PREFIX_VEX_0F44 */
3663 { VEX_LEN_TABLE (VEX_LEN_0F44_P_0
) },
3665 { VEX_LEN_TABLE (VEX_LEN_0F44_P_2
) },
3668 /* PREFIX_VEX_0F45 */
3670 { VEX_LEN_TABLE (VEX_LEN_0F45_P_0
) },
3672 { VEX_LEN_TABLE (VEX_LEN_0F45_P_2
) },
3675 /* PREFIX_VEX_0F46 */
3677 { VEX_LEN_TABLE (VEX_LEN_0F46_P_0
) },
3679 { VEX_LEN_TABLE (VEX_LEN_0F46_P_2
) },
3682 /* PREFIX_VEX_0F47 */
3684 { VEX_LEN_TABLE (VEX_LEN_0F47_P_0
) },
3686 { VEX_LEN_TABLE (VEX_LEN_0F47_P_2
) },
3689 /* PREFIX_VEX_0F4A */
3691 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0
) },
3693 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2
) },
3696 /* PREFIX_VEX_0F4B */
3698 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0
) },
3700 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2
) },
3703 /* PREFIX_VEX_0F51 */
3705 { "vsqrtps", { XM
, EXx
}, 0 },
3706 { "vsqrtss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
3707 { "vsqrtpd", { XM
, EXx
}, 0 },
3708 { "vsqrtsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
3711 /* PREFIX_VEX_0F52 */
3713 { "vrsqrtps", { XM
, EXx
}, 0 },
3714 { "vrsqrtss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
3717 /* PREFIX_VEX_0F53 */
3719 { "vrcpps", { XM
, EXx
}, 0 },
3720 { "vrcpss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
3723 /* PREFIX_VEX_0F58 */
3725 { "vaddps", { XM
, Vex
, EXx
}, 0 },
3726 { "vaddss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
3727 { "vaddpd", { XM
, Vex
, EXx
}, 0 },
3728 { "vaddsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
3731 /* PREFIX_VEX_0F59 */
3733 { "vmulps", { XM
, Vex
, EXx
}, 0 },
3734 { "vmulss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
3735 { "vmulpd", { XM
, Vex
, EXx
}, 0 },
3736 { "vmulsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
3739 /* PREFIX_VEX_0F5A */
3741 { "vcvtps2pd", { XM
, EXxmmq
}, 0 },
3742 { "vcvtss2sd", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
3743 { "vcvtpd2ps%XY",{ XMM
, EXx
}, 0 },
3744 { "vcvtsd2ss", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
3747 /* PREFIX_VEX_0F5B */
3749 { "vcvtdq2ps", { XM
, EXx
}, 0 },
3750 { "vcvttps2dq", { XM
, EXx
}, 0 },
3751 { "vcvtps2dq", { XM
, EXx
}, 0 },
3754 /* PREFIX_VEX_0F5C */
3756 { "vsubps", { XM
, Vex
, EXx
}, 0 },
3757 { "vsubss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
3758 { "vsubpd", { XM
, Vex
, EXx
}, 0 },
3759 { "vsubsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
3762 /* PREFIX_VEX_0F5D */
3764 { "vminps", { XM
, Vex
, EXx
}, 0 },
3765 { "vminss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
3766 { "vminpd", { XM
, Vex
, EXx
}, 0 },
3767 { "vminsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
3770 /* PREFIX_VEX_0F5E */
3772 { "vdivps", { XM
, Vex
, EXx
}, 0 },
3773 { "vdivss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
3774 { "vdivpd", { XM
, Vex
, EXx
}, 0 },
3775 { "vdivsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
3778 /* PREFIX_VEX_0F5F */
3780 { "vmaxps", { XM
, Vex
, EXx
}, 0 },
3781 { "vmaxss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
3782 { "vmaxpd", { XM
, Vex
, EXx
}, 0 },
3783 { "vmaxsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
3786 /* PREFIX_VEX_0F6F */
3789 { "vmovdqu", { XM
, EXx
}, 0 },
3790 { "vmovdqa", { XM
, EXx
}, 0 },
3793 /* PREFIX_VEX_0F70 */
3796 { "vpshufhw", { XM
, EXx
, Ib
}, 0 },
3797 { "vpshufd", { XM
, EXx
, Ib
}, 0 },
3798 { "vpshuflw", { XM
, EXx
, Ib
}, 0 },
3801 /* PREFIX_VEX_0F7C */
3805 { "vhaddpd", { XM
, Vex
, EXx
}, 0 },
3806 { "vhaddps", { XM
, Vex
, EXx
}, 0 },
3809 /* PREFIX_VEX_0F7D */
3813 { "vhsubpd", { XM
, Vex
, EXx
}, 0 },
3814 { "vhsubps", { XM
, Vex
, EXx
}, 0 },
3817 /* PREFIX_VEX_0F7E */
3820 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1
) },
3821 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2
) },
3824 /* PREFIX_VEX_0F7F */
3827 { "vmovdqu", { EXxS
, XM
}, 0 },
3828 { "vmovdqa", { EXxS
, XM
}, 0 },
3831 /* PREFIX_VEX_0F90 */
3833 { VEX_LEN_TABLE (VEX_LEN_0F90_P_0
) },
3835 { VEX_LEN_TABLE (VEX_LEN_0F90_P_2
) },
3838 /* PREFIX_VEX_0F91 */
3840 { VEX_LEN_TABLE (VEX_LEN_0F91_P_0
) },
3842 { VEX_LEN_TABLE (VEX_LEN_0F91_P_2
) },
3845 /* PREFIX_VEX_0F92 */
3847 { VEX_LEN_TABLE (VEX_LEN_0F92_P_0
) },
3849 { VEX_LEN_TABLE (VEX_LEN_0F92_P_2
) },
3850 { VEX_LEN_TABLE (VEX_LEN_0F92_P_3
) },
3853 /* PREFIX_VEX_0F93 */
3855 { VEX_LEN_TABLE (VEX_LEN_0F93_P_0
) },
3857 { VEX_LEN_TABLE (VEX_LEN_0F93_P_2
) },
3858 { VEX_LEN_TABLE (VEX_LEN_0F93_P_3
) },
3861 /* PREFIX_VEX_0F98 */
3863 { VEX_LEN_TABLE (VEX_LEN_0F98_P_0
) },
3865 { VEX_LEN_TABLE (VEX_LEN_0F98_P_2
) },
3868 /* PREFIX_VEX_0F99 */
3870 { VEX_LEN_TABLE (VEX_LEN_0F99_P_0
) },
3872 { VEX_LEN_TABLE (VEX_LEN_0F99_P_2
) },
3875 /* PREFIX_VEX_0FC2 */
3877 { "vcmpps", { XM
, Vex
, EXx
, CMP
}, 0 },
3878 { "vcmpss", { XMScalar
, VexScalar
, EXxmm_md
, CMP
}, 0 },
3879 { "vcmppd", { XM
, Vex
, EXx
, CMP
}, 0 },
3880 { "vcmpsd", { XMScalar
, VexScalar
, EXxmm_mq
, CMP
}, 0 },
3883 /* PREFIX_VEX_0FD0 */
3887 { "vaddsubpd", { XM
, Vex
, EXx
}, 0 },
3888 { "vaddsubps", { XM
, Vex
, EXx
}, 0 },
3891 /* PREFIX_VEX_0FE6 */
3894 { "vcvtdq2pd", { XM
, EXxmmq
}, 0 },
3895 { "vcvttpd2dq%XY", { XMM
, EXx
}, 0 },
3896 { "vcvtpd2dq%XY", { XMM
, EXx
}, 0 },
3899 /* PREFIX_VEX_0FF0 */
3904 { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3
) },
3907 /* PREFIX_VEX_0F3849_X86_64 */
3909 { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_0
) },
3911 { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_2
) },
3912 { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_3
) },
3915 /* PREFIX_VEX_0F384B_X86_64 */
3918 { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_1
) },
3919 { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_2
) },
3920 { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_3
) },
3923 /* PREFIX_VEX_0F385C_X86_64 */
3926 { VEX_W_TABLE (VEX_W_0F385C_X86_64_P_1
) },
3930 /* PREFIX_VEX_0F385E_X86_64 */
3932 { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_0
) },
3933 { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_1
) },
3934 { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_2
) },
3935 { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_3
) },
3938 /* PREFIX_VEX_0F38F5 */
3940 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0
) },
3941 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1
) },
3943 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3
) },
3946 /* PREFIX_VEX_0F38F6 */
3951 { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3
) },
3954 /* PREFIX_VEX_0F38F7 */
3956 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0
) },
3957 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1
) },
3958 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2
) },
3959 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3
) },
3962 /* PREFIX_VEX_0F3AF0 */
3967 { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3
) },
3970 #include "i386-dis-evex-prefix.h"
3973 static const struct dis386 x86_64_table
[][2] = {
3976 { "pushP", { es
}, 0 },
3981 { "popP", { es
}, 0 },
3986 { "pushP", { cs
}, 0 },
3991 { "pushP", { ss
}, 0 },
3996 { "popP", { ss
}, 0 },
4001 { "pushP", { ds
}, 0 },
4006 { "popP", { ds
}, 0 },
4011 { "daa", { XX
}, 0 },
4016 { "das", { XX
}, 0 },
4021 { "aaa", { XX
}, 0 },
4026 { "aas", { XX
}, 0 },
4031 { "pushaP", { XX
}, 0 },
4036 { "popaP", { XX
}, 0 },
4041 { MOD_TABLE (MOD_62_32BIT
) },
4042 { EVEX_TABLE (EVEX_0F
) },
4047 { "arpl", { Ew
, Gw
}, 0 },
4048 { "movs", { { OP_G
, movsxd_mode
}, { MOVSXD_Fixup
, movsxd_mode
} }, 0 },
4053 { "ins{R|}", { Yzr
, indirDX
}, 0 },
4054 { "ins{G|}", { Yzr
, indirDX
}, 0 },
4059 { "outs{R|}", { indirDXr
, Xz
}, 0 },
4060 { "outs{G|}", { indirDXr
, Xz
}, 0 },
4065 /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode. */
4066 { REG_TABLE (REG_80
) },
4071 { "{l|}call{P|}", { Ap
}, 0 },
4076 { "retP", { Iw
, BND
}, 0 },
4077 { "ret@", { Iw
, BND
}, 0 },
4082 { "retP", { BND
}, 0 },
4083 { "ret@", { BND
}, 0 },
4088 { MOD_TABLE (MOD_C4_32BIT
) },
4089 { VEX_C4_TABLE (VEX_0F
) },
4094 { MOD_TABLE (MOD_C5_32BIT
) },
4095 { VEX_C5_TABLE (VEX_0F
) },
4100 { "into", { XX
}, 0 },
4105 { "aam", { Ib
}, 0 },
4110 { "aad", { Ib
}, 0 },
4115 { "callP", { Jv
, BND
}, 0 },
4116 { "call@", { Jv
, BND
}, 0 }
4121 { "jmpP", { Jv
, BND
}, 0 },
4122 { "jmp@", { Jv
, BND
}, 0 }
4127 { "{l|}jmp{P|}", { Ap
}, 0 },
4130 /* X86_64_0F01_REG_0 */
4132 { "sgdt{Q|Q}", { M
}, 0 },
4133 { "sgdt", { M
}, 0 },
4136 /* X86_64_0F01_REG_1 */
4138 { "sidt{Q|Q}", { M
}, 0 },
4139 { "sidt", { M
}, 0 },
4142 /* X86_64_0F01_REG_2 */
4144 { "lgdt{Q|Q}", { M
}, 0 },
4145 { "lgdt", { M
}, 0 },
4148 /* X86_64_0F01_REG_3 */
4150 { "lidt{Q|Q}", { M
}, 0 },
4151 { "lidt", { M
}, 0 },
4156 { "movZ", { Em
, Td
}, 0 },
4161 { "movZ", { Td
, Em
}, 0 },
4164 /* X86_64_VEX_0F3849 */
4167 { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64
) },
4170 /* X86_64_VEX_0F384B */
4173 { PREFIX_TABLE (PREFIX_VEX_0F384B_X86_64
) },
4176 /* X86_64_VEX_0F385C */
4179 { PREFIX_TABLE (PREFIX_VEX_0F385C_X86_64
) },
4182 /* X86_64_VEX_0F385E */
4185 { PREFIX_TABLE (PREFIX_VEX_0F385E_X86_64
) },
4189 static const struct dis386 three_byte_table
[][256] = {
4191 /* THREE_BYTE_0F38 */
4194 { "pshufb", { MX
, EM
}, PREFIX_OPCODE
},
4195 { "phaddw", { MX
, EM
}, PREFIX_OPCODE
},
4196 { "phaddd", { MX
, EM
}, PREFIX_OPCODE
},
4197 { "phaddsw", { MX
, EM
}, PREFIX_OPCODE
},
4198 { "pmaddubsw", { MX
, EM
}, PREFIX_OPCODE
},
4199 { "phsubw", { MX
, EM
}, PREFIX_OPCODE
},
4200 { "phsubd", { MX
, EM
}, PREFIX_OPCODE
},
4201 { "phsubsw", { MX
, EM
}, PREFIX_OPCODE
},
4203 { "psignb", { MX
, EM
}, PREFIX_OPCODE
},
4204 { "psignw", { MX
, EM
}, PREFIX_OPCODE
},
4205 { "psignd", { MX
, EM
}, PREFIX_OPCODE
},
4206 { "pmulhrsw", { MX
, EM
}, PREFIX_OPCODE
},
4212 { "pblendvb", { XM
, EXx
, XMM0
}, PREFIX_DATA
},
4216 { "blendvps", { XM
, EXx
, XMM0
}, PREFIX_DATA
},
4217 { "blendvpd", { XM
, EXx
, XMM0
}, PREFIX_DATA
},
4219 { "ptest", { XM
, EXx
}, PREFIX_DATA
},
4225 { "pabsb", { MX
, EM
}, PREFIX_OPCODE
},
4226 { "pabsw", { MX
, EM
}, PREFIX_OPCODE
},
4227 { "pabsd", { MX
, EM
}, PREFIX_OPCODE
},
4230 { "pmovsxbw", { XM
, EXq
}, PREFIX_DATA
},
4231 { "pmovsxbd", { XM
, EXd
}, PREFIX_DATA
},
4232 { "pmovsxbq", { XM
, EXw
}, PREFIX_DATA
},
4233 { "pmovsxwd", { XM
, EXq
}, PREFIX_DATA
},
4234 { "pmovsxwq", { XM
, EXd
}, PREFIX_DATA
},
4235 { "pmovsxdq", { XM
, EXq
}, PREFIX_DATA
},
4239 { "pmuldq", { XM
, EXx
}, PREFIX_DATA
},
4240 { "pcmpeqq", { XM
, EXx
}, PREFIX_DATA
},
4241 { MOD_TABLE (MOD_0F382A
) },
4242 { "packusdw", { XM
, EXx
}, PREFIX_DATA
},
4248 { "pmovzxbw", { XM
, EXq
}, PREFIX_DATA
},
4249 { "pmovzxbd", { XM
, EXd
}, PREFIX_DATA
},
4250 { "pmovzxbq", { XM
, EXw
}, PREFIX_DATA
},
4251 { "pmovzxwd", { XM
, EXq
}, PREFIX_DATA
},
4252 { "pmovzxwq", { XM
, EXd
}, PREFIX_DATA
},
4253 { "pmovzxdq", { XM
, EXq
}, PREFIX_DATA
},
4255 { "pcmpgtq", { XM
, EXx
}, PREFIX_DATA
},
4257 { "pminsb", { XM
, EXx
}, PREFIX_DATA
},
4258 { "pminsd", { XM
, EXx
}, PREFIX_DATA
},
4259 { "pminuw", { XM
, EXx
}, PREFIX_DATA
},
4260 { "pminud", { XM
, EXx
}, PREFIX_DATA
},
4261 { "pmaxsb", { XM
, EXx
}, PREFIX_DATA
},
4262 { "pmaxsd", { XM
, EXx
}, PREFIX_DATA
},
4263 { "pmaxuw", { XM
, EXx
}, PREFIX_DATA
},
4264 { "pmaxud", { XM
, EXx
}, PREFIX_DATA
},
4266 { "pmulld", { XM
, EXx
}, PREFIX_DATA
},
4267 { "phminposuw", { XM
, EXx
}, PREFIX_DATA
},
4338 { "invept", { Gm
, Mo
}, PREFIX_DATA
},
4339 { "invvpid", { Gm
, Mo
}, PREFIX_DATA
},
4340 { "invpcid", { Gm
, M
}, PREFIX_DATA
},
4419 { "sha1nexte", { XM
, EXxmm
}, PREFIX_OPCODE
},
4420 { "sha1msg1", { XM
, EXxmm
}, PREFIX_OPCODE
},
4421 { "sha1msg2", { XM
, EXxmm
}, PREFIX_OPCODE
},
4422 { "sha256rnds2", { XM
, EXxmm
, XMM0
}, PREFIX_OPCODE
},
4423 { "sha256msg1", { XM
, EXxmm
}, PREFIX_OPCODE
},
4424 { "sha256msg2", { XM
, EXxmm
}, PREFIX_OPCODE
},
4426 { "gf2p8mulb", { XM
, EXxmm
}, PREFIX_DATA
},
4440 { "aesimc", { XM
, EXx
}, PREFIX_DATA
},
4441 { "aesenc", { XM
, EXx
}, PREFIX_DATA
},
4442 { "aesenclast", { XM
, EXx
}, PREFIX_DATA
},
4443 { "aesdec", { XM
, EXx
}, PREFIX_DATA
},
4444 { "aesdeclast", { XM
, EXx
}, PREFIX_DATA
},
4464 { PREFIX_TABLE (PREFIX_0F38F0
) },
4465 { PREFIX_TABLE (PREFIX_0F38F1
) },
4469 { MOD_TABLE (MOD_0F38F5
) },
4470 { PREFIX_TABLE (PREFIX_0F38F6
) },
4473 { PREFIX_TABLE (PREFIX_0F38F8
) },
4474 { MOD_TABLE (MOD_0F38F9
) },
4482 /* THREE_BYTE_0F3A */
4494 { "roundps", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4495 { "roundpd", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4496 { "roundss", { XM
, EXd
, Ib
}, PREFIX_DATA
},
4497 { "roundsd", { XM
, EXq
, Ib
}, PREFIX_DATA
},
4498 { "blendps", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4499 { "blendpd", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4500 { "pblendw", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4501 { "palignr", { MX
, EM
, Ib
}, PREFIX_OPCODE
},
4507 { "pextrb", { Edqb
, XM
, Ib
}, PREFIX_DATA
},
4508 { "pextrw", { Edqw
, XM
, Ib
}, PREFIX_DATA
},
4509 { "pextrK", { Edq
, XM
, Ib
}, PREFIX_DATA
},
4510 { "extractps", { Edqd
, XM
, Ib
}, PREFIX_DATA
},
4521 { "pinsrb", { XM
, Edqb
, Ib
}, PREFIX_DATA
},
4522 { "insertps", { XM
, EXd
, Ib
}, PREFIX_DATA
},
4523 { "pinsrK", { XM
, Edq
, Ib
}, PREFIX_DATA
},
4557 { "dpps", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4558 { "dppd", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4559 { "mpsadbw", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4561 { "pclmulqdq", { XM
, EXx
, PCLMUL
}, PREFIX_DATA
},
4593 { "pcmpestrm!%LQ", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4594 { "pcmpestri!%LQ", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4595 { "pcmpistrm", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4596 { "pcmpistri", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4714 { "sha1rnds4", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4716 { "gf2p8affineqb", { XM
, EXxmm
, Ib
}, PREFIX_DATA
},
4717 { "gf2p8affineinvqb", { XM
, EXxmm
, Ib
}, PREFIX_DATA
},
4735 { "aeskeygenassist", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4775 static const struct dis386 xop_table
[][256] = {
4928 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_85
) },
4929 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_86
) },
4930 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_87
) },
4938 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8E
) },
4939 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8F
) },
4946 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_95
) },
4947 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_96
) },
4948 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_97
) },
4956 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9E
) },
4957 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9F
) },
4961 { "vpcmov", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
4962 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A3
) },
4965 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A6
) },
4983 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_B6
) },
4995 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C0
) },
4996 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C1
) },
4997 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C2
) },
4998 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C3
) },
5008 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC
) },
5009 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD
) },
5010 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE
) },
5011 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF
) },
5044 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC
) },
5045 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED
) },
5046 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE
) },
5047 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF
) },
5071 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_01
) },
5072 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_02
) },
5090 { MOD_TABLE (MOD_VEX_0FXOP_09_12
) },
5214 { VEX_W_TABLE (VEX_W_0FXOP_09_80
) },
5215 { VEX_W_TABLE (VEX_W_0FXOP_09_81
) },
5216 { VEX_W_TABLE (VEX_W_0FXOP_09_82
) },
5217 { VEX_W_TABLE (VEX_W_0FXOP_09_83
) },
5232 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_90
) },
5233 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_91
) },
5234 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_92
) },
5235 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_93
) },
5236 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_94
) },
5237 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_95
) },
5238 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_96
) },
5239 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_97
) },
5241 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_98
) },
5242 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_99
) },
5243 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9A
) },
5244 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9B
) },
5287 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C1
) },
5288 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C2
) },
5289 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C3
) },
5292 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C6
) },
5293 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C7
) },
5298 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_CB
) },
5305 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D1
) },
5306 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D2
) },
5307 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D3
) },
5310 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D6
) },
5311 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D7
) },
5316 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_DB
) },
5323 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E1
) },
5324 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E2
) },
5325 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E3
) },
5379 { "bextrS", { Gdq
, Edq
, Id
}, 0 },
5381 { VEX_LEN_TABLE (VEX_LEN_0FXOP_0A_12
) },
5651 static const struct dis386 vex_table
[][256] = {
5673 { PREFIX_TABLE (PREFIX_VEX_0F10
) },
5674 { PREFIX_TABLE (PREFIX_VEX_0F11
) },
5675 { PREFIX_TABLE (PREFIX_VEX_0F12
) },
5676 { MOD_TABLE (MOD_VEX_0F13
) },
5677 { "vunpcklpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
5678 { "vunpckhpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
5679 { PREFIX_TABLE (PREFIX_VEX_0F16
) },
5680 { MOD_TABLE (MOD_VEX_0F17
) },
5700 { "vmovapX", { XM
, EXx
}, PREFIX_OPCODE
},
5701 { "vmovapX", { EXxS
, XM
}, PREFIX_OPCODE
},
5702 { PREFIX_TABLE (PREFIX_VEX_0F2A
) },
5703 { MOD_TABLE (MOD_VEX_0F2B
) },
5704 { PREFIX_TABLE (PREFIX_VEX_0F2C
) },
5705 { PREFIX_TABLE (PREFIX_VEX_0F2D
) },
5706 { PREFIX_TABLE (PREFIX_VEX_0F2E
) },
5707 { PREFIX_TABLE (PREFIX_VEX_0F2F
) },
5728 { PREFIX_TABLE (PREFIX_VEX_0F41
) },
5729 { PREFIX_TABLE (PREFIX_VEX_0F42
) },
5731 { PREFIX_TABLE (PREFIX_VEX_0F44
) },
5732 { PREFIX_TABLE (PREFIX_VEX_0F45
) },
5733 { PREFIX_TABLE (PREFIX_VEX_0F46
) },
5734 { PREFIX_TABLE (PREFIX_VEX_0F47
) },
5738 { PREFIX_TABLE (PREFIX_VEX_0F4A
) },
5739 { PREFIX_TABLE (PREFIX_VEX_0F4B
) },
5745 { MOD_TABLE (MOD_VEX_0F50
) },
5746 { PREFIX_TABLE (PREFIX_VEX_0F51
) },
5747 { PREFIX_TABLE (PREFIX_VEX_0F52
) },
5748 { PREFIX_TABLE (PREFIX_VEX_0F53
) },
5749 { "vandpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
5750 { "vandnpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
5751 { "vorpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
5752 { "vxorpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
5754 { PREFIX_TABLE (PREFIX_VEX_0F58
) },
5755 { PREFIX_TABLE (PREFIX_VEX_0F59
) },
5756 { PREFIX_TABLE (PREFIX_VEX_0F5A
) },
5757 { PREFIX_TABLE (PREFIX_VEX_0F5B
) },
5758 { PREFIX_TABLE (PREFIX_VEX_0F5C
) },
5759 { PREFIX_TABLE (PREFIX_VEX_0F5D
) },
5760 { PREFIX_TABLE (PREFIX_VEX_0F5E
) },
5761 { PREFIX_TABLE (PREFIX_VEX_0F5F
) },
5763 { "vpunpcklbw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5764 { "vpunpcklwd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5765 { "vpunpckldq", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5766 { "vpacksswb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5767 { "vpcmpgtb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5768 { "vpcmpgtw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5769 { "vpcmpgtd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5770 { "vpackuswb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5772 { "vpunpckhbw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5773 { "vpunpckhwd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5774 { "vpunpckhdq", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5775 { "vpackssdw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5776 { "vpunpcklqdq", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5777 { "vpunpckhqdq", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5778 { VEX_LEN_TABLE (VEX_LEN_0F6E
) },
5779 { PREFIX_TABLE (PREFIX_VEX_0F6F
) },
5781 { PREFIX_TABLE (PREFIX_VEX_0F70
) },
5782 { REG_TABLE (REG_VEX_0F71
) },
5783 { REG_TABLE (REG_VEX_0F72
) },
5784 { REG_TABLE (REG_VEX_0F73
) },
5785 { "vpcmpeqb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5786 { "vpcmpeqw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5787 { "vpcmpeqd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5788 { VEX_LEN_TABLE (VEX_LEN_0F77
) },
5794 { PREFIX_TABLE (PREFIX_VEX_0F7C
) },
5795 { PREFIX_TABLE (PREFIX_VEX_0F7D
) },
5796 { PREFIX_TABLE (PREFIX_VEX_0F7E
) },
5797 { PREFIX_TABLE (PREFIX_VEX_0F7F
) },
5817 { PREFIX_TABLE (PREFIX_VEX_0F90
) },
5818 { PREFIX_TABLE (PREFIX_VEX_0F91
) },
5819 { PREFIX_TABLE (PREFIX_VEX_0F92
) },
5820 { PREFIX_TABLE (PREFIX_VEX_0F93
) },
5826 { PREFIX_TABLE (PREFIX_VEX_0F98
) },
5827 { PREFIX_TABLE (PREFIX_VEX_0F99
) },
5850 { REG_TABLE (REG_VEX_0FAE
) },
5873 { PREFIX_TABLE (PREFIX_VEX_0FC2
) },
5875 { VEX_LEN_TABLE (VEX_LEN_0FC4
) },
5876 { VEX_LEN_TABLE (VEX_LEN_0FC5
) },
5877 { "vshufpX", { XM
, Vex
, EXx
, Ib
}, PREFIX_OPCODE
},
5889 { PREFIX_TABLE (PREFIX_VEX_0FD0
) },
5890 { "vpsrlw", { XM
, Vex
, EXxmm
}, PREFIX_DATA
},
5891 { "vpsrld", { XM
, Vex
, EXxmm
}, PREFIX_DATA
},
5892 { "vpsrlq", { XM
, Vex
, EXxmm
}, PREFIX_DATA
},
5893 { "vpaddq", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5894 { "vpmullw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5895 { VEX_LEN_TABLE (VEX_LEN_0FD6
) },
5896 { MOD_TABLE (MOD_VEX_0FD7
) },
5898 { "vpsubusb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5899 { "vpsubusw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5900 { "vpminub", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5901 { "vpand", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5902 { "vpaddusb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5903 { "vpaddusw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5904 { "vpmaxub", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5905 { "vpandn", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5907 { "vpavgb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5908 { "vpsraw", { XM
, Vex
, EXxmm
}, PREFIX_DATA
},
5909 { "vpsrad", { XM
, Vex
, EXxmm
}, PREFIX_DATA
},
5910 { "vpavgw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5911 { "vpmulhuw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5912 { "vpmulhw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5913 { PREFIX_TABLE (PREFIX_VEX_0FE6
) },
5914 { MOD_TABLE (MOD_VEX_0FE7
) },
5916 { "vpsubsb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5917 { "vpsubsw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5918 { "vpminsw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5919 { "vpor", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5920 { "vpaddsb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5921 { "vpaddsw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5922 { "vpmaxsw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5923 { "vpxor", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5925 { PREFIX_TABLE (PREFIX_VEX_0FF0
) },
5926 { "vpsllw", { XM
, Vex
, EXxmm
}, PREFIX_DATA
},
5927 { "vpslld", { XM
, Vex
, EXxmm
}, PREFIX_DATA
},
5928 { "vpsllq", { XM
, Vex
, EXxmm
}, PREFIX_DATA
},
5929 { "vpmuludq", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5930 { "vpmaddwd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5931 { "vpsadbw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5932 { VEX_LEN_TABLE (VEX_LEN_0FF7
) },
5934 { "vpsubb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5935 { "vpsubw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5936 { "vpsubd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5937 { "vpsubq", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5938 { "vpaddb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5939 { "vpaddw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5940 { "vpaddd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5946 { "vpshufb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5947 { "vphaddw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5948 { "vphaddd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5949 { "vphaddsw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5950 { "vpmaddubsw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5951 { "vphsubw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5952 { "vphsubd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5953 { "vphsubsw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5955 { "vpsignb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5956 { "vpsignw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5957 { "vpsignd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5958 { "vpmulhrsw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5959 { VEX_W_TABLE (VEX_W_0F380C
) },
5960 { VEX_W_TABLE (VEX_W_0F380D
) },
5961 { VEX_W_TABLE (VEX_W_0F380E
) },
5962 { VEX_W_TABLE (VEX_W_0F380F
) },
5967 { VEX_W_TABLE (VEX_W_0F3813
) },
5970 { VEX_LEN_TABLE (VEX_LEN_0F3816
) },
5971 { "vptest", { XM
, EXx
}, PREFIX_DATA
},
5973 { VEX_W_TABLE (VEX_W_0F3818
) },
5974 { VEX_LEN_TABLE (VEX_LEN_0F3819
) },
5975 { MOD_TABLE (MOD_VEX_0F381A
) },
5977 { "vpabsb", { XM
, EXx
}, PREFIX_DATA
},
5978 { "vpabsw", { XM
, EXx
}, PREFIX_DATA
},
5979 { "vpabsd", { XM
, EXx
}, PREFIX_DATA
},
5982 { "vpmovsxbw", { XM
, EXxmmq
}, PREFIX_DATA
},
5983 { "vpmovsxbd", { XM
, EXxmmqd
}, PREFIX_DATA
},
5984 { "vpmovsxbq", { XM
, EXxmmdw
}, PREFIX_DATA
},
5985 { "vpmovsxwd", { XM
, EXxmmq
}, PREFIX_DATA
},
5986 { "vpmovsxwq", { XM
, EXxmmqd
}, PREFIX_DATA
},
5987 { "vpmovsxdq", { XM
, EXxmmq
}, PREFIX_DATA
},
5991 { "vpmuldq", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5992 { "vpcmpeqq", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5993 { MOD_TABLE (MOD_VEX_0F382A
) },
5994 { "vpackusdw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5995 { MOD_TABLE (MOD_VEX_0F382C
) },
5996 { MOD_TABLE (MOD_VEX_0F382D
) },
5997 { MOD_TABLE (MOD_VEX_0F382E
) },
5998 { MOD_TABLE (MOD_VEX_0F382F
) },
6000 { "vpmovzxbw", { XM
, EXxmmq
}, PREFIX_DATA
},
6001 { "vpmovzxbd", { XM
, EXxmmqd
}, PREFIX_DATA
},
6002 { "vpmovzxbq", { XM
, EXxmmdw
}, PREFIX_DATA
},
6003 { "vpmovzxwd", { XM
, EXxmmq
}, PREFIX_DATA
},
6004 { "vpmovzxwq", { XM
, EXxmmqd
}, PREFIX_DATA
},
6005 { "vpmovzxdq", { XM
, EXxmmq
}, PREFIX_DATA
},
6006 { VEX_LEN_TABLE (VEX_LEN_0F3836
) },
6007 { "vpcmpgtq", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6009 { "vpminsb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6010 { "vpminsd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6011 { "vpminuw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6012 { "vpminud", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6013 { "vpmaxsb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6014 { "vpmaxsd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6015 { "vpmaxuw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6016 { "vpmaxud", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6018 { "vpmulld", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6019 { VEX_LEN_TABLE (VEX_LEN_0F3841
) },
6023 { "vpsrlv%DQ", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6024 { VEX_W_TABLE (VEX_W_0F3846
) },
6025 { "vpsllv%DQ", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6028 { X86_64_TABLE (X86_64_VEX_0F3849
) },
6030 { X86_64_TABLE (X86_64_VEX_0F384B
) },
6045 { VEX_W_TABLE (VEX_W_0F3858
) },
6046 { VEX_W_TABLE (VEX_W_0F3859
) },
6047 { MOD_TABLE (MOD_VEX_0F385A
) },
6049 { X86_64_TABLE (X86_64_VEX_0F385C
) },
6051 { X86_64_TABLE (X86_64_VEX_0F385E
) },
6081 { VEX_W_TABLE (VEX_W_0F3878
) },
6082 { VEX_W_TABLE (VEX_W_0F3879
) },
6103 { MOD_TABLE (MOD_VEX_0F388C
) },
6105 { MOD_TABLE (MOD_VEX_0F388E
) },
6108 { "vpgatherd%DQ", { XM
, MVexVSIBDWpX
, Vex
}, PREFIX_DATA
},
6109 { "vpgatherq%DQ", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
}, PREFIX_DATA
},
6110 { "vgatherdp%XW", { XM
, MVexVSIBDWpX
, Vex
}, PREFIX_DATA
},
6111 { "vgatherqp%XW", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
}, PREFIX_DATA
},
6114 { "vfmaddsub132p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6115 { "vfmsubadd132p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6117 { "vfmadd132p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6118 { "vfmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, PREFIX_DATA
},
6119 { "vfmsub132p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6120 { "vfmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, PREFIX_DATA
},
6121 { "vfnmadd132p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6122 { "vfnmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, PREFIX_DATA
},
6123 { "vfnmsub132p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6124 { "vfnmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, PREFIX_DATA
},
6132 { "vfmaddsub213p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6133 { "vfmsubadd213p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6135 { "vfmadd213p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6136 { "vfmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, PREFIX_DATA
},
6137 { "vfmsub213p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6138 { "vfmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, PREFIX_DATA
},
6139 { "vfnmadd213p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6140 { "vfnmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, PREFIX_DATA
},
6141 { "vfnmsub213p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6142 { "vfnmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, PREFIX_DATA
},
6150 { "vfmaddsub231p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6151 { "vfmsubadd231p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6153 { "vfmadd231p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6154 { "vfmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, PREFIX_DATA
},
6155 { "vfmsub231p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6156 { "vfmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, PREFIX_DATA
},
6157 { "vfnmadd231p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6158 { "vfnmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, PREFIX_DATA
},
6159 { "vfnmsub231p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6160 { "vfnmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, PREFIX_DATA
},
6178 { VEX_W_TABLE (VEX_W_0F38CF
) },
6192 { VEX_LEN_TABLE (VEX_LEN_0F38DB
) },
6193 { "vaesenc", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6194 { "vaesenclast", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6195 { "vaesdec", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6196 { "vaesdeclast", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6218 { VEX_LEN_TABLE (VEX_LEN_0F38F2
) },
6219 { REG_TABLE (REG_VEX_0F38F3
) },
6221 { PREFIX_TABLE (PREFIX_VEX_0F38F5
) },
6222 { PREFIX_TABLE (PREFIX_VEX_0F38F6
) },
6223 { PREFIX_TABLE (PREFIX_VEX_0F38F7
) },
6237 { VEX_LEN_TABLE (VEX_LEN_0F3A00
) },
6238 { VEX_LEN_TABLE (VEX_LEN_0F3A01
) },
6239 { VEX_W_TABLE (VEX_W_0F3A02
) },
6241 { VEX_W_TABLE (VEX_W_0F3A04
) },
6242 { VEX_W_TABLE (VEX_W_0F3A05
) },
6243 { VEX_LEN_TABLE (VEX_LEN_0F3A06
) },
6246 { "vroundps", { XM
, EXx
, Ib
}, PREFIX_DATA
},
6247 { "vroundpd", { XM
, EXx
, Ib
}, PREFIX_DATA
},
6248 { "vroundss", { XMScalar
, VexScalar
, EXxmm_md
, Ib
}, PREFIX_DATA
},
6249 { "vroundsd", { XMScalar
, VexScalar
, EXxmm_mq
, Ib
}, PREFIX_DATA
},
6250 { "vblendps", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
6251 { "vblendpd", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
6252 { "vpblendw", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
6253 { "vpalignr", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
6259 { VEX_LEN_TABLE (VEX_LEN_0F3A14
) },
6260 { VEX_LEN_TABLE (VEX_LEN_0F3A15
) },
6261 { VEX_LEN_TABLE (VEX_LEN_0F3A16
) },
6262 { VEX_LEN_TABLE (VEX_LEN_0F3A17
) },
6264 { VEX_LEN_TABLE (VEX_LEN_0F3A18
) },
6265 { VEX_LEN_TABLE (VEX_LEN_0F3A19
) },
6269 { VEX_W_TABLE (VEX_W_0F3A1D
) },
6273 { VEX_LEN_TABLE (VEX_LEN_0F3A20
) },
6274 { VEX_LEN_TABLE (VEX_LEN_0F3A21
) },
6275 { VEX_LEN_TABLE (VEX_LEN_0F3A22
) },
6291 { VEX_LEN_TABLE (VEX_LEN_0F3A30
) },
6292 { VEX_LEN_TABLE (VEX_LEN_0F3A31
) },
6293 { VEX_LEN_TABLE (VEX_LEN_0F3A32
) },
6294 { VEX_LEN_TABLE (VEX_LEN_0F3A33
) },
6300 { VEX_LEN_TABLE (VEX_LEN_0F3A38
) },
6301 { VEX_LEN_TABLE (VEX_LEN_0F3A39
) },
6309 { "vdpps", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
6310 { VEX_LEN_TABLE (VEX_LEN_0F3A41
) },
6311 { "vmpsadbw", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
6313 { "vpclmulqdq", { XM
, Vex
, EXx
, PCLMUL
}, PREFIX_DATA
},
6315 { VEX_LEN_TABLE (VEX_LEN_0F3A46
) },
6318 { "vpermil2ps", { XM
, Vex
, EXx
, XMVexI4
, VexI4
}, PREFIX_DATA
},
6319 { "vpermil2pd", { XM
, Vex
, EXx
, XMVexI4
, VexI4
}, PREFIX_DATA
},
6320 { VEX_W_TABLE (VEX_W_0F3A4A
) },
6321 { VEX_W_TABLE (VEX_W_0F3A4B
) },
6322 { VEX_W_TABLE (VEX_W_0F3A4C
) },
6340 { "vfmaddsubps", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6341 { "vfmaddsubpd", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6342 { "vfmsubaddps", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6343 { "vfmsubaddpd", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6345 { VEX_LEN_TABLE (VEX_LEN_0F3A60
) },
6346 { VEX_LEN_TABLE (VEX_LEN_0F3A61
) },
6347 { VEX_LEN_TABLE (VEX_LEN_0F3A62
) },
6348 { VEX_LEN_TABLE (VEX_LEN_0F3A63
) },
6354 { "vfmaddps", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6355 { "vfmaddpd", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6356 { "vfmaddss", { XMScalar
, VexScalar
, EXxmm_md
, XMVexScalarI4
}, PREFIX_DATA
},
6357 { "vfmaddsd", { XMScalar
, VexScalar
, EXxmm_mq
, XMVexScalarI4
}, PREFIX_DATA
},
6358 { "vfmsubps", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6359 { "vfmsubpd", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6360 { "vfmsubss", { XMScalar
, VexScalar
, EXxmm_md
, XMVexScalarI4
}, PREFIX_DATA
},
6361 { "vfmsubsd", { XMScalar
, VexScalar
, EXxmm_mq
, XMVexScalarI4
}, PREFIX_DATA
},
6372 { "vfnmaddps", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6373 { "vfnmaddpd", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6374 { "vfnmaddss", { XMScalar
, VexScalar
, EXxmm_md
, XMVexScalarI4
}, PREFIX_DATA
},
6375 { "vfnmaddsd", { XMScalar
, VexScalar
, EXxmm_mq
, XMVexScalarI4
}, PREFIX_DATA
},
6376 { "vfnmsubps", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6377 { "vfnmsubpd", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6378 { "vfnmsubss", { XMScalar
, VexScalar
, EXxmm_md
, XMVexScalarI4
}, PREFIX_DATA
},
6379 { "vfnmsubsd", { XMScalar
, VexScalar
, EXxmm_mq
, XMVexScalarI4
}, PREFIX_DATA
},
6468 { VEX_W_TABLE (VEX_W_0F3ACE
) },
6469 { VEX_W_TABLE (VEX_W_0F3ACF
) },
6487 { VEX_LEN_TABLE (VEX_LEN_0F3ADF
) },
6507 { PREFIX_TABLE (PREFIX_VEX_0F3AF0
) },
6527 #include "i386-dis-evex.h"
6529 static const struct dis386 vex_len_table
[][2] = {
6530 /* VEX_LEN_0F12_P_0_M_0 / VEX_LEN_0F12_P_2_M_0 */
6532 { "vmovlpX", { XM
, Vex
, EXq
}, 0 },
6535 /* VEX_LEN_0F12_P_0_M_1 */
6537 { "vmovhlps", { XM
, Vex
, EXq
}, 0 },
6540 /* VEX_LEN_0F13_M_0 */
6542 { "vmovlpX", { EXq
, XM
}, PREFIX_OPCODE
},
6545 /* VEX_LEN_0F16_P_0_M_0 / VEX_LEN_0F16_P_2_M_0 */
6547 { "vmovhpX", { XM
, Vex
, EXq
}, 0 },
6550 /* VEX_LEN_0F16_P_0_M_1 */
6552 { "vmovlhps", { XM
, Vex
, EXq
}, 0 },
6555 /* VEX_LEN_0F17_M_0 */
6557 { "vmovhpX", { EXq
, XM
}, PREFIX_OPCODE
},
6560 /* VEX_LEN_0F41_P_0 */
6563 { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1
) },
6565 /* VEX_LEN_0F41_P_2 */
6568 { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1
) },
6570 /* VEX_LEN_0F42_P_0 */
6573 { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1
) },
6575 /* VEX_LEN_0F42_P_2 */
6578 { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1
) },
6580 /* VEX_LEN_0F44_P_0 */
6582 { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0
) },
6584 /* VEX_LEN_0F44_P_2 */
6586 { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0
) },
6588 /* VEX_LEN_0F45_P_0 */
6591 { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1
) },
6593 /* VEX_LEN_0F45_P_2 */
6596 { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1
) },
6598 /* VEX_LEN_0F46_P_0 */
6601 { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1
) },
6603 /* VEX_LEN_0F46_P_2 */
6606 { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1
) },
6608 /* VEX_LEN_0F47_P_0 */
6611 { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1
) },
6613 /* VEX_LEN_0F47_P_2 */
6616 { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1
) },
6618 /* VEX_LEN_0F4A_P_0 */
6621 { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1
) },
6623 /* VEX_LEN_0F4A_P_2 */
6626 { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1
) },
6628 /* VEX_LEN_0F4B_P_0 */
6631 { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1
) },
6633 /* VEX_LEN_0F4B_P_2 */
6636 { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1
) },
6641 { "vmovK", { XMScalar
, Edq
}, PREFIX_DATA
},
6646 { "vzeroupper", { XX
}, 0 },
6647 { "vzeroall", { XX
}, 0 },
6650 /* VEX_LEN_0F7E_P_1 */
6652 { "vmovq", { XMScalar
, EXxmm_mq
}, 0 },
6655 /* VEX_LEN_0F7E_P_2 */
6657 { "vmovK", { Edq
, XMScalar
}, 0 },
6660 /* VEX_LEN_0F90_P_0 */
6662 { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0
) },
6665 /* VEX_LEN_0F90_P_2 */
6667 { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0
) },
6670 /* VEX_LEN_0F91_P_0 */
6672 { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0
) },
6675 /* VEX_LEN_0F91_P_2 */
6677 { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0
) },
6680 /* VEX_LEN_0F92_P_0 */
6682 { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0
) },
6685 /* VEX_LEN_0F92_P_2 */
6687 { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0
) },
6690 /* VEX_LEN_0F92_P_3 */
6692 { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0
) },
6695 /* VEX_LEN_0F93_P_0 */
6697 { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0
) },
6700 /* VEX_LEN_0F93_P_2 */
6702 { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0
) },
6705 /* VEX_LEN_0F93_P_3 */
6707 { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0
) },
6710 /* VEX_LEN_0F98_P_0 */
6712 { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0
) },
6715 /* VEX_LEN_0F98_P_2 */
6717 { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0
) },
6720 /* VEX_LEN_0F99_P_0 */
6722 { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0
) },
6725 /* VEX_LEN_0F99_P_2 */
6727 { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0
) },
6730 /* VEX_LEN_0FAE_R_2_M_0 */
6732 { "vldmxcsr", { Md
}, 0 },
6735 /* VEX_LEN_0FAE_R_3_M_0 */
6737 { "vstmxcsr", { Md
}, 0 },
6742 { "vpinsrw", { XM
, Vex
, Edqw
, Ib
}, PREFIX_DATA
},
6747 { "vpextrw", { Gdq
, XS
, Ib
}, PREFIX_DATA
},
6752 { "vmovq", { EXqS
, XMScalar
}, PREFIX_DATA
},
6757 { "vmaskmovdqu", { XM
, XS
}, PREFIX_DATA
},
6760 /* VEX_LEN_0F3816 */
6763 { VEX_W_TABLE (VEX_W_0F3816_L_1
) },
6766 /* VEX_LEN_0F3819 */
6769 { VEX_W_TABLE (VEX_W_0F3819_L_1
) },
6772 /* VEX_LEN_0F381A_M_0 */
6775 { VEX_W_TABLE (VEX_W_0F381A_M_0_L_1
) },
6778 /* VEX_LEN_0F3836 */
6781 { VEX_W_TABLE (VEX_W_0F3836
) },
6784 /* VEX_LEN_0F3841 */
6786 { "vphminposuw", { XM
, EXx
}, PREFIX_DATA
},
6789 /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_0 */
6791 { "ldtilecfg", { M
}, 0 },
6794 /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0 */
6796 { "tilerelease", { Skip_MODRM
}, 0 },
6799 /* VEX_LEN_0F3849_X86_64_P_2_W_0_M_0 */
6801 { "sttilecfg", { M
}, 0 },
6804 /* VEX_LEN_0F3849_X86_64_P_3_W_0_M_0 */
6806 { "tilezero", { TMM
, Skip_MODRM
}, 0 },
6809 /* VEX_LEN_0F384B_X86_64_P_1_W_0_M_0 */
6811 { "tilestored", { MVexSIBMEM
, TMM
}, 0 },
6813 /* VEX_LEN_0F384B_X86_64_P_2_W_0_M_0 */
6815 { "tileloaddt1", { TMM
, MVexSIBMEM
}, 0 },
6818 /* VEX_LEN_0F384B_X86_64_P_3_W_0_M_0 */
6820 { "tileloadd", { TMM
, MVexSIBMEM
}, 0 },
6823 /* VEX_LEN_0F385A_M_0 */
6826 { VEX_W_TABLE (VEX_W_0F385A_M_0_L_0
) },
6829 /* VEX_LEN_0F385C_X86_64_P_1_W_0_M_0 */
6831 { "tdpbf16ps", { TMM
, EXtmm
, VexTmm
}, 0 },
6834 /* VEX_LEN_0F385E_X86_64_P_0_W_0_M_0 */
6836 { "tdpbuud", {TMM
, EXtmm
, VexTmm
}, 0 },
6839 /* VEX_LEN_0F385E_X86_64_P_1_W_0_M_0 */
6841 { "tdpbsud", {TMM
, EXtmm
, VexTmm
}, 0 },
6844 /* VEX_LEN_0F385E_X86_64_P_2_W_0_M_0 */
6846 { "tdpbusd", {TMM
, EXtmm
, VexTmm
}, 0 },
6849 /* VEX_LEN_0F385E_X86_64_P_3_W_0_M_0 */
6851 { "tdpbssd", {TMM
, EXtmm
, VexTmm
}, 0 },
6854 /* VEX_LEN_0F38DB */
6856 { "vaesimc", { XM
, EXx
}, PREFIX_DATA
},
6859 /* VEX_LEN_0F38F2 */
6861 { "andnS", { Gdq
, VexGdq
, Edq
}, PREFIX_OPCODE
},
6864 /* VEX_LEN_0F38F3_R_1 */
6866 { "blsrS", { VexGdq
, Edq
}, PREFIX_OPCODE
},
6869 /* VEX_LEN_0F38F3_R_2 */
6871 { "blsmskS", { VexGdq
, Edq
}, PREFIX_OPCODE
},
6874 /* VEX_LEN_0F38F3_R_3 */
6876 { "blsiS", { VexGdq
, Edq
}, PREFIX_OPCODE
},
6879 /* VEX_LEN_0F38F5_P_0 */
6881 { "bzhiS", { Gdq
, Edq
, VexGdq
}, 0 },
6884 /* VEX_LEN_0F38F5_P_1 */
6886 { "pextS", { Gdq
, VexGdq
, Edq
}, 0 },
6889 /* VEX_LEN_0F38F5_P_3 */
6891 { "pdepS", { Gdq
, VexGdq
, Edq
}, 0 },
6894 /* VEX_LEN_0F38F6_P_3 */
6896 { "mulxS", { Gdq
, VexGdq
, Edq
}, 0 },
6899 /* VEX_LEN_0F38F7_P_0 */
6901 { "bextrS", { Gdq
, Edq
, VexGdq
}, 0 },
6904 /* VEX_LEN_0F38F7_P_1 */
6906 { "sarxS", { Gdq
, Edq
, VexGdq
}, 0 },
6909 /* VEX_LEN_0F38F7_P_2 */
6911 { "shlxS", { Gdq
, Edq
, VexGdq
}, 0 },
6914 /* VEX_LEN_0F38F7_P_3 */
6916 { "shrxS", { Gdq
, Edq
, VexGdq
}, 0 },
6919 /* VEX_LEN_0F3A00 */
6922 { VEX_W_TABLE (VEX_W_0F3A00_L_1
) },
6925 /* VEX_LEN_0F3A01 */
6928 { VEX_W_TABLE (VEX_W_0F3A01_L_1
) },
6931 /* VEX_LEN_0F3A06 */
6934 { VEX_W_TABLE (VEX_W_0F3A06_L_1
) },
6937 /* VEX_LEN_0F3A14 */
6939 { "vpextrb", { Edqb
, XM
, Ib
}, PREFIX_DATA
},
6942 /* VEX_LEN_0F3A15 */
6944 { "vpextrw", { Edqw
, XM
, Ib
}, PREFIX_DATA
},
6947 /* VEX_LEN_0F3A16 */
6949 { "vpextrK", { Edq
, XM
, Ib
}, PREFIX_DATA
},
6952 /* VEX_LEN_0F3A17 */
6954 { "vextractps", { Edqd
, XM
, Ib
}, PREFIX_DATA
},
6957 /* VEX_LEN_0F3A18 */
6960 { VEX_W_TABLE (VEX_W_0F3A18_L_1
) },
6963 /* VEX_LEN_0F3A19 */
6966 { VEX_W_TABLE (VEX_W_0F3A19_L_1
) },
6969 /* VEX_LEN_0F3A20 */
6971 { "vpinsrb", { XM
, Vex
, Edqb
, Ib
}, PREFIX_DATA
},
6974 /* VEX_LEN_0F3A21 */
6976 { "vinsertps", { XM
, Vex
, EXd
, Ib
}, PREFIX_DATA
},
6979 /* VEX_LEN_0F3A22 */
6981 { "vpinsrK", { XM
, Vex
, Edq
, Ib
}, PREFIX_DATA
},
6984 /* VEX_LEN_0F3A30 */
6986 { MOD_TABLE (MOD_VEX_0F3A30_L_0
) },
6989 /* VEX_LEN_0F3A31 */
6991 { MOD_TABLE (MOD_VEX_0F3A31_L_0
) },
6994 /* VEX_LEN_0F3A32 */
6996 { MOD_TABLE (MOD_VEX_0F3A32_L_0
) },
6999 /* VEX_LEN_0F3A33 */
7001 { MOD_TABLE (MOD_VEX_0F3A33_L_0
) },
7004 /* VEX_LEN_0F3A38 */
7007 { VEX_W_TABLE (VEX_W_0F3A38_L_1
) },
7010 /* VEX_LEN_0F3A39 */
7013 { VEX_W_TABLE (VEX_W_0F3A39_L_1
) },
7016 /* VEX_LEN_0F3A41 */
7018 { "vdppd", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
7021 /* VEX_LEN_0F3A46 */
7024 { VEX_W_TABLE (VEX_W_0F3A46_L_1
) },
7027 /* VEX_LEN_0F3A60 */
7029 { "vpcmpestrm!%LQ", { XM
, EXx
, Ib
}, PREFIX_DATA
},
7032 /* VEX_LEN_0F3A61 */
7034 { "vpcmpestri!%LQ", { XM
, EXx
, Ib
}, PREFIX_DATA
},
7037 /* VEX_LEN_0F3A62 */
7039 { "vpcmpistrm", { XM
, EXx
, Ib
}, PREFIX_DATA
},
7042 /* VEX_LEN_0F3A63 */
7044 { "vpcmpistri", { XM
, EXx
, Ib
}, PREFIX_DATA
},
7047 /* VEX_LEN_0F3ADF */
7049 { "vaeskeygenassist", { XM
, EXx
, Ib
}, PREFIX_DATA
},
7052 /* VEX_LEN_0F3AF0_P_3 */
7054 { "rorxS", { Gdq
, Edq
, Ib
}, 0 },
7057 /* VEX_LEN_0FXOP_08_85 */
7059 { VEX_W_TABLE (VEX_W_0FXOP_08_85_L_0
) },
7062 /* VEX_LEN_0FXOP_08_86 */
7064 { VEX_W_TABLE (VEX_W_0FXOP_08_86_L_0
) },
7067 /* VEX_LEN_0FXOP_08_87 */
7069 { VEX_W_TABLE (VEX_W_0FXOP_08_87_L_0
) },
7072 /* VEX_LEN_0FXOP_08_8E */
7074 { VEX_W_TABLE (VEX_W_0FXOP_08_8E_L_0
) },
7077 /* VEX_LEN_0FXOP_08_8F */
7079 { VEX_W_TABLE (VEX_W_0FXOP_08_8F_L_0
) },
7082 /* VEX_LEN_0FXOP_08_95 */
7084 { VEX_W_TABLE (VEX_W_0FXOP_08_95_L_0
) },
7087 /* VEX_LEN_0FXOP_08_96 */
7089 { VEX_W_TABLE (VEX_W_0FXOP_08_96_L_0
) },
7092 /* VEX_LEN_0FXOP_08_97 */
7094 { VEX_W_TABLE (VEX_W_0FXOP_08_97_L_0
) },
7097 /* VEX_LEN_0FXOP_08_9E */
7099 { VEX_W_TABLE (VEX_W_0FXOP_08_9E_L_0
) },
7102 /* VEX_LEN_0FXOP_08_9F */
7104 { VEX_W_TABLE (VEX_W_0FXOP_08_9F_L_0
) },
7107 /* VEX_LEN_0FXOP_08_A3 */
7109 { "vpperm", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7112 /* VEX_LEN_0FXOP_08_A6 */
7114 { VEX_W_TABLE (VEX_W_0FXOP_08_A6_L_0
) },
7117 /* VEX_LEN_0FXOP_08_B6 */
7119 { VEX_W_TABLE (VEX_W_0FXOP_08_B6_L_0
) },
7122 /* VEX_LEN_0FXOP_08_C0 */
7124 { VEX_W_TABLE (VEX_W_0FXOP_08_C0_L_0
) },
7127 /* VEX_LEN_0FXOP_08_C1 */
7129 { VEX_W_TABLE (VEX_W_0FXOP_08_C1_L_0
) },
7132 /* VEX_LEN_0FXOP_08_C2 */
7134 { VEX_W_TABLE (VEX_W_0FXOP_08_C2_L_0
) },
7137 /* VEX_LEN_0FXOP_08_C3 */
7139 { VEX_W_TABLE (VEX_W_0FXOP_08_C3_L_0
) },
7142 /* VEX_LEN_0FXOP_08_CC */
7144 { VEX_W_TABLE (VEX_W_0FXOP_08_CC_L_0
) },
7147 /* VEX_LEN_0FXOP_08_CD */
7149 { VEX_W_TABLE (VEX_W_0FXOP_08_CD_L_0
) },
7152 /* VEX_LEN_0FXOP_08_CE */
7154 { VEX_W_TABLE (VEX_W_0FXOP_08_CE_L_0
) },
7157 /* VEX_LEN_0FXOP_08_CF */
7159 { VEX_W_TABLE (VEX_W_0FXOP_08_CF_L_0
) },
7162 /* VEX_LEN_0FXOP_08_EC */
7164 { VEX_W_TABLE (VEX_W_0FXOP_08_EC_L_0
) },
7167 /* VEX_LEN_0FXOP_08_ED */
7169 { VEX_W_TABLE (VEX_W_0FXOP_08_ED_L_0
) },
7172 /* VEX_LEN_0FXOP_08_EE */
7174 { VEX_W_TABLE (VEX_W_0FXOP_08_EE_L_0
) },
7177 /* VEX_LEN_0FXOP_08_EF */
7179 { VEX_W_TABLE (VEX_W_0FXOP_08_EF_L_0
) },
7182 /* VEX_LEN_0FXOP_09_01 */
7184 { REG_TABLE (REG_0FXOP_09_01_L_0
) },
7187 /* VEX_LEN_0FXOP_09_02 */
7189 { REG_TABLE (REG_0FXOP_09_02_L_0
) },
7192 /* VEX_LEN_0FXOP_09_12_M_1 */
7194 { REG_TABLE (REG_0FXOP_09_12_M_1_L_0
) },
7197 /* VEX_LEN_0FXOP_09_82_W_0 */
7199 { "vfrczss", { XM
, EXd
}, 0 },
7202 /* VEX_LEN_0FXOP_09_83_W_0 */
7204 { "vfrczsd", { XM
, EXq
}, 0 },
7207 /* VEX_LEN_0FXOP_09_90 */
7209 { "vprotb", { XM
, EXx
, VexW
}, 0 },
7212 /* VEX_LEN_0FXOP_09_91 */
7214 { "vprotw", { XM
, EXx
, VexW
}, 0 },
7217 /* VEX_LEN_0FXOP_09_92 */
7219 { "vprotd", { XM
, EXx
, VexW
}, 0 },
7222 /* VEX_LEN_0FXOP_09_93 */
7224 { "vprotq", { XM
, EXx
, VexW
}, 0 },
7227 /* VEX_LEN_0FXOP_09_94 */
7229 { "vpshlb", { XM
, EXx
, VexW
}, 0 },
7232 /* VEX_LEN_0FXOP_09_95 */
7234 { "vpshlw", { XM
, EXx
, VexW
}, 0 },
7237 /* VEX_LEN_0FXOP_09_96 */
7239 { "vpshld", { XM
, EXx
, VexW
}, 0 },
7242 /* VEX_LEN_0FXOP_09_97 */
7244 { "vpshlq", { XM
, EXx
, VexW
}, 0 },
7247 /* VEX_LEN_0FXOP_09_98 */
7249 { "vpshab", { XM
, EXx
, VexW
}, 0 },
7252 /* VEX_LEN_0FXOP_09_99 */
7254 { "vpshaw", { XM
, EXx
, VexW
}, 0 },
7257 /* VEX_LEN_0FXOP_09_9A */
7259 { "vpshad", { XM
, EXx
, VexW
}, 0 },
7262 /* VEX_LEN_0FXOP_09_9B */
7264 { "vpshaq", { XM
, EXx
, VexW
}, 0 },
7267 /* VEX_LEN_0FXOP_09_C1 */
7269 { VEX_W_TABLE (VEX_W_0FXOP_09_C1_L_0
) },
7272 /* VEX_LEN_0FXOP_09_C2 */
7274 { VEX_W_TABLE (VEX_W_0FXOP_09_C2_L_0
) },
7277 /* VEX_LEN_0FXOP_09_C3 */
7279 { VEX_W_TABLE (VEX_W_0FXOP_09_C3_L_0
) },
7282 /* VEX_LEN_0FXOP_09_C6 */
7284 { VEX_W_TABLE (VEX_W_0FXOP_09_C6_L_0
) },
7287 /* VEX_LEN_0FXOP_09_C7 */
7289 { VEX_W_TABLE (VEX_W_0FXOP_09_C7_L_0
) },
7292 /* VEX_LEN_0FXOP_09_CB */
7294 { VEX_W_TABLE (VEX_W_0FXOP_09_CB_L_0
) },
7297 /* VEX_LEN_0FXOP_09_D1 */
7299 { VEX_W_TABLE (VEX_W_0FXOP_09_D1_L_0
) },
7302 /* VEX_LEN_0FXOP_09_D2 */
7304 { VEX_W_TABLE (VEX_W_0FXOP_09_D2_L_0
) },
7307 /* VEX_LEN_0FXOP_09_D3 */
7309 { VEX_W_TABLE (VEX_W_0FXOP_09_D3_L_0
) },
7312 /* VEX_LEN_0FXOP_09_D6 */
7314 { VEX_W_TABLE (VEX_W_0FXOP_09_D6_L_0
) },
7317 /* VEX_LEN_0FXOP_09_D7 */
7319 { VEX_W_TABLE (VEX_W_0FXOP_09_D7_L_0
) },
7322 /* VEX_LEN_0FXOP_09_DB */
7324 { VEX_W_TABLE (VEX_W_0FXOP_09_DB_L_0
) },
7327 /* VEX_LEN_0FXOP_09_E1 */
7329 { VEX_W_TABLE (VEX_W_0FXOP_09_E1_L_0
) },
7332 /* VEX_LEN_0FXOP_09_E2 */
7334 { VEX_W_TABLE (VEX_W_0FXOP_09_E2_L_0
) },
7337 /* VEX_LEN_0FXOP_09_E3 */
7339 { VEX_W_TABLE (VEX_W_0FXOP_09_E3_L_0
) },
7342 /* VEX_LEN_0FXOP_0A_12 */
7344 { REG_TABLE (REG_0FXOP_0A_12_L_0
) },
7348 #include "i386-dis-evex-len.h"
7350 static const struct dis386 vex_w_table
[][2] = {
7352 /* VEX_W_0F41_P_0_LEN_1 */
7353 { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1
) },
7354 { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1
) },
7357 /* VEX_W_0F41_P_2_LEN_1 */
7358 { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1
) },
7359 { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1
) }
7362 /* VEX_W_0F42_P_0_LEN_1 */
7363 { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1
) },
7364 { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1
) },
7367 /* VEX_W_0F42_P_2_LEN_1 */
7368 { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1
) },
7369 { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1
) },
7372 /* VEX_W_0F44_P_0_LEN_0 */
7373 { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1
) },
7374 { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1
) },
7377 /* VEX_W_0F44_P_2_LEN_0 */
7378 { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1
) },
7379 { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1
) },
7382 /* VEX_W_0F45_P_0_LEN_1 */
7383 { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1
) },
7384 { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1
) },
7387 /* VEX_W_0F45_P_2_LEN_1 */
7388 { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1
) },
7389 { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1
) },
7392 /* VEX_W_0F46_P_0_LEN_1 */
7393 { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1
) },
7394 { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1
) },
7397 /* VEX_W_0F46_P_2_LEN_1 */
7398 { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1
) },
7399 { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1
) },
7402 /* VEX_W_0F47_P_0_LEN_1 */
7403 { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1
) },
7404 { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1
) },
7407 /* VEX_W_0F47_P_2_LEN_1 */
7408 { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1
) },
7409 { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1
) },
7412 /* VEX_W_0F4A_P_0_LEN_1 */
7413 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1
) },
7414 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1
) },
7417 /* VEX_W_0F4A_P_2_LEN_1 */
7418 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1
) },
7419 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1
) },
7422 /* VEX_W_0F4B_P_0_LEN_1 */
7423 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1
) },
7424 { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1
) },
7427 /* VEX_W_0F4B_P_2_LEN_1 */
7428 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1
) },
7431 /* VEX_W_0F90_P_0_LEN_0 */
7432 { "kmovw", { MaskG
, MaskE
}, 0 },
7433 { "kmovq", { MaskG
, MaskE
}, 0 },
7436 /* VEX_W_0F90_P_2_LEN_0 */
7437 { "kmovb", { MaskG
, MaskBDE
}, 0 },
7438 { "kmovd", { MaskG
, MaskBDE
}, 0 },
7441 /* VEX_W_0F91_P_0_LEN_0 */
7442 { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0
) },
7443 { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0
) },
7446 /* VEX_W_0F91_P_2_LEN_0 */
7447 { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0
) },
7448 { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0
) },
7451 /* VEX_W_0F92_P_0_LEN_0 */
7452 { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0
) },
7455 /* VEX_W_0F92_P_2_LEN_0 */
7456 { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0
) },
7459 /* VEX_W_0F93_P_0_LEN_0 */
7460 { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0
) },
7463 /* VEX_W_0F93_P_2_LEN_0 */
7464 { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0
) },
7467 /* VEX_W_0F98_P_0_LEN_0 */
7468 { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0
) },
7469 { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0
) },
7472 /* VEX_W_0F98_P_2_LEN_0 */
7473 { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0
) },
7474 { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0
) },
7477 /* VEX_W_0F99_P_0_LEN_0 */
7478 { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0
) },
7479 { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0
) },
7482 /* VEX_W_0F99_P_2_LEN_0 */
7483 { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0
) },
7484 { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0
) },
7488 { "vpermilps", { XM
, Vex
, EXx
}, PREFIX_DATA
},
7492 { "vpermilpd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
7496 { "vtestps", { XM
, EXx
}, PREFIX_DATA
},
7500 { "vtestpd", { XM
, EXx
}, PREFIX_DATA
},
7504 { "vcvtph2ps", { XM
, EXxmmq
}, PREFIX_DATA
},
7507 /* VEX_W_0F3816_L_1 */
7508 { "vpermps", { XM
, Vex
, EXx
}, PREFIX_DATA
},
7512 { "vbroadcastss", { XM
, EXxmm_md
}, PREFIX_DATA
},
7515 /* VEX_W_0F3819_L_1 */
7516 { "vbroadcastsd", { XM
, EXxmm_mq
}, PREFIX_DATA
},
7519 /* VEX_W_0F381A_M_0_L_1 */
7520 { "vbroadcastf128", { XM
, Mxmm
}, PREFIX_DATA
},
7523 /* VEX_W_0F382C_M_0 */
7524 { "vmaskmovps", { XM
, Vex
, Mx
}, PREFIX_DATA
},
7527 /* VEX_W_0F382D_M_0 */
7528 { "vmaskmovpd", { XM
, Vex
, Mx
}, PREFIX_DATA
},
7531 /* VEX_W_0F382E_M_0 */
7532 { "vmaskmovps", { Mx
, Vex
, XM
}, PREFIX_DATA
},
7535 /* VEX_W_0F382F_M_0 */
7536 { "vmaskmovpd", { Mx
, Vex
, XM
}, PREFIX_DATA
},
7540 { "vpermd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
7544 { "vpsravd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
7547 /* VEX_W_0F3849_X86_64_P_0 */
7548 { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_0_W_0
) },
7551 /* VEX_W_0F3849_X86_64_P_2 */
7552 { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_2_W_0
) },
7555 /* VEX_W_0F3849_X86_64_P_3 */
7556 { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_3_W_0
) },
7559 /* VEX_W_0F384B_X86_64_P_1 */
7560 { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_1_W_0
) },
7563 /* VEX_W_0F384B_X86_64_P_2 */
7564 { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_2_W_0
) },
7567 /* VEX_W_0F384B_X86_64_P_3 */
7568 { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_3_W_0
) },
7572 { "vpbroadcastd", { XM
, EXxmm_md
}, PREFIX_DATA
},
7576 { "vpbroadcastq", { XM
, EXxmm_mq
}, PREFIX_DATA
},
7579 /* VEX_W_0F385A_M_0_L_0 */
7580 { "vbroadcasti128", { XM
, Mxmm
}, PREFIX_DATA
},
7583 /* VEX_W_0F385C_X86_64_P_1 */
7584 { MOD_TABLE (MOD_VEX_0F385C_X86_64_P_1_W_0
) },
7587 /* VEX_W_0F385E_X86_64_P_0 */
7588 { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_0_W_0
) },
7591 /* VEX_W_0F385E_X86_64_P_1 */
7592 { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_1_W_0
) },
7595 /* VEX_W_0F385E_X86_64_P_2 */
7596 { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_2_W_0
) },
7599 /* VEX_W_0F385E_X86_64_P_3 */
7600 { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_3_W_0
) },
7604 { "vpbroadcastb", { XM
, EXxmm_mb
}, PREFIX_DATA
},
7608 { "vpbroadcastw", { XM
, EXxmm_mw
}, PREFIX_DATA
},
7612 { "vgf2p8mulb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
7615 /* VEX_W_0F3A00_L_1 */
7617 { "vpermq", { XM
, EXx
, Ib
}, PREFIX_DATA
},
7620 /* VEX_W_0F3A01_L_1 */
7622 { "vpermpd", { XM
, EXx
, Ib
}, PREFIX_DATA
},
7626 { "vpblendd", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
7630 { "vpermilps", { XM
, EXx
, Ib
}, PREFIX_DATA
},
7634 { "vpermilpd", { XM
, EXx
, Ib
}, PREFIX_DATA
},
7637 /* VEX_W_0F3A06_L_1 */
7638 { "vperm2f128", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
7641 /* VEX_W_0F3A18_L_1 */
7642 { "vinsertf128", { XM
, Vex
, EXxmm
, Ib
}, PREFIX_DATA
},
7645 /* VEX_W_0F3A19_L_1 */
7646 { "vextractf128", { EXxmm
, XM
, Ib
}, PREFIX_DATA
},
7650 { "vcvtps2ph", { EXxmmq
, XM
, EXxEVexS
, Ib
}, PREFIX_DATA
},
7653 /* VEX_W_0F3A38_L_1 */
7654 { "vinserti128", { XM
, Vex
, EXxmm
, Ib
}, PREFIX_DATA
},
7657 /* VEX_W_0F3A39_L_1 */
7658 { "vextracti128", { EXxmm
, XM
, Ib
}, PREFIX_DATA
},
7661 /* VEX_W_0F3A46_L_1 */
7662 { "vperm2i128", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
7666 { "vblendvps", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
7670 { "vblendvpd", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
7674 { "vpblendvb", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
7679 { "vgf2p8affineqb", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
7684 { "vgf2p8affineinvqb", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
7686 /* VEX_W_0FXOP_08_85_L_0 */
7688 { "vpmacssww", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7690 /* VEX_W_0FXOP_08_86_L_0 */
7692 { "vpmacsswd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7694 /* VEX_W_0FXOP_08_87_L_0 */
7696 { "vpmacssdql", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7698 /* VEX_W_0FXOP_08_8E_L_0 */
7700 { "vpmacssdd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7702 /* VEX_W_0FXOP_08_8F_L_0 */
7704 { "vpmacssdqh", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7706 /* VEX_W_0FXOP_08_95_L_0 */
7708 { "vpmacsww", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7710 /* VEX_W_0FXOP_08_96_L_0 */
7712 { "vpmacswd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7714 /* VEX_W_0FXOP_08_97_L_0 */
7716 { "vpmacsdql", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7718 /* VEX_W_0FXOP_08_9E_L_0 */
7720 { "vpmacsdd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7722 /* VEX_W_0FXOP_08_9F_L_0 */
7724 { "vpmacsdqh", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7726 /* VEX_W_0FXOP_08_A6_L_0 */
7728 { "vpmadcsswd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7730 /* VEX_W_0FXOP_08_B6_L_0 */
7732 { "vpmadcswd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7734 /* VEX_W_0FXOP_08_C0_L_0 */
7736 { "vprotb", { XM
, EXx
, Ib
}, 0 },
7738 /* VEX_W_0FXOP_08_C1_L_0 */
7740 { "vprotw", { XM
, EXx
, Ib
}, 0 },
7742 /* VEX_W_0FXOP_08_C2_L_0 */
7744 { "vprotd", { XM
, EXx
, Ib
}, 0 },
7746 /* VEX_W_0FXOP_08_C3_L_0 */
7748 { "vprotq", { XM
, EXx
, Ib
}, 0 },
7750 /* VEX_W_0FXOP_08_CC_L_0 */
7752 { "vpcomb", { XM
, Vex
, EXx
, VPCOM
}, 0 },
7754 /* VEX_W_0FXOP_08_CD_L_0 */
7756 { "vpcomw", { XM
, Vex
, EXx
, VPCOM
}, 0 },
7758 /* VEX_W_0FXOP_08_CE_L_0 */
7760 { "vpcomd", { XM
, Vex
, EXx
, VPCOM
}, 0 },
7762 /* VEX_W_0FXOP_08_CF_L_0 */
7764 { "vpcomq", { XM
, Vex
, EXx
, VPCOM
}, 0 },
7766 /* VEX_W_0FXOP_08_EC_L_0 */
7768 { "vpcomub", { XM
, Vex
, EXx
, VPCOM
}, 0 },
7770 /* VEX_W_0FXOP_08_ED_L_0 */
7772 { "vpcomuw", { XM
, Vex
, EXx
, VPCOM
}, 0 },
7774 /* VEX_W_0FXOP_08_EE_L_0 */
7776 { "vpcomud", { XM
, Vex
, EXx
, VPCOM
}, 0 },
7778 /* VEX_W_0FXOP_08_EF_L_0 */
7780 { "vpcomuq", { XM
, Vex
, EXx
, VPCOM
}, 0 },
7782 /* VEX_W_0FXOP_09_80 */
7784 { "vfrczps", { XM
, EXx
}, 0 },
7786 /* VEX_W_0FXOP_09_81 */
7788 { "vfrczpd", { XM
, EXx
}, 0 },
7790 /* VEX_W_0FXOP_09_82 */
7792 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_82_W_0
) },
7794 /* VEX_W_0FXOP_09_83 */
7796 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_83_W_0
) },
7798 /* VEX_W_0FXOP_09_C1_L_0 */
7800 { "vphaddbw", { XM
, EXxmm
}, 0 },
7802 /* VEX_W_0FXOP_09_C2_L_0 */
7804 { "vphaddbd", { XM
, EXxmm
}, 0 },
7806 /* VEX_W_0FXOP_09_C3_L_0 */
7808 { "vphaddbq", { XM
, EXxmm
}, 0 },
7810 /* VEX_W_0FXOP_09_C6_L_0 */
7812 { "vphaddwd", { XM
, EXxmm
}, 0 },
7814 /* VEX_W_0FXOP_09_C7_L_0 */
7816 { "vphaddwq", { XM
, EXxmm
}, 0 },
7818 /* VEX_W_0FXOP_09_CB_L_0 */
7820 { "vphadddq", { XM
, EXxmm
}, 0 },
7822 /* VEX_W_0FXOP_09_D1_L_0 */
7824 { "vphaddubw", { XM
, EXxmm
}, 0 },
7826 /* VEX_W_0FXOP_09_D2_L_0 */
7828 { "vphaddubd", { XM
, EXxmm
}, 0 },
7830 /* VEX_W_0FXOP_09_D3_L_0 */
7832 { "vphaddubq", { XM
, EXxmm
}, 0 },
7834 /* VEX_W_0FXOP_09_D6_L_0 */
7836 { "vphadduwd", { XM
, EXxmm
}, 0 },
7838 /* VEX_W_0FXOP_09_D7_L_0 */
7840 { "vphadduwq", { XM
, EXxmm
}, 0 },
7842 /* VEX_W_0FXOP_09_DB_L_0 */
7844 { "vphaddudq", { XM
, EXxmm
}, 0 },
7846 /* VEX_W_0FXOP_09_E1_L_0 */
7848 { "vphsubbw", { XM
, EXxmm
}, 0 },
7850 /* VEX_W_0FXOP_09_E2_L_0 */
7852 { "vphsubwd", { XM
, EXxmm
}, 0 },
7854 /* VEX_W_0FXOP_09_E3_L_0 */
7856 { "vphsubdq", { XM
, EXxmm
}, 0 },
7859 #include "i386-dis-evex-w.h"
7862 static const struct dis386 mod_table
[][2] = {
7865 { "leaS", { Gv
, M
}, 0 },
7870 { RM_TABLE (RM_C6_REG_7
) },
7875 { RM_TABLE (RM_C7_REG_7
) },
7879 { "{l|}call^", { indirEp
}, 0 },
7883 { "{l|}jmp^", { indirEp
}, 0 },
7886 /* MOD_0F01_REG_0 */
7887 { X86_64_TABLE (X86_64_0F01_REG_0
) },
7888 { RM_TABLE (RM_0F01_REG_0
) },
7891 /* MOD_0F01_REG_1 */
7892 { X86_64_TABLE (X86_64_0F01_REG_1
) },
7893 { RM_TABLE (RM_0F01_REG_1
) },
7896 /* MOD_0F01_REG_2 */
7897 { X86_64_TABLE (X86_64_0F01_REG_2
) },
7898 { RM_TABLE (RM_0F01_REG_2
) },
7901 /* MOD_0F01_REG_3 */
7902 { X86_64_TABLE (X86_64_0F01_REG_3
) },
7903 { RM_TABLE (RM_0F01_REG_3
) },
7906 /* MOD_0F01_REG_5 */
7907 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0
) },
7908 { RM_TABLE (RM_0F01_REG_5_MOD_3
) },
7911 /* MOD_0F01_REG_7 */
7912 { "invlpg", { Mb
}, 0 },
7913 { RM_TABLE (RM_0F01_REG_7_MOD_3
) },
7916 /* MOD_0F12_PREFIX_0 */
7917 { "movlpX", { XM
, EXq
}, 0 },
7918 { "movhlps", { XM
, EXq
}, 0 },
7921 /* MOD_0F12_PREFIX_2 */
7922 { "movlpX", { XM
, EXq
}, 0 },
7926 { "movlpX", { EXq
, XM
}, PREFIX_OPCODE
},
7929 /* MOD_0F16_PREFIX_0 */
7930 { "movhpX", { XM
, EXq
}, 0 },
7931 { "movlhps", { XM
, EXq
}, 0 },
7934 /* MOD_0F16_PREFIX_2 */
7935 { "movhpX", { XM
, EXq
}, 0 },
7939 { "movhpX", { EXq
, XM
}, PREFIX_OPCODE
},
7942 /* MOD_0F18_REG_0 */
7943 { "prefetchnta", { Mb
}, 0 },
7946 /* MOD_0F18_REG_1 */
7947 { "prefetcht0", { Mb
}, 0 },
7950 /* MOD_0F18_REG_2 */
7951 { "prefetcht1", { Mb
}, 0 },
7954 /* MOD_0F18_REG_3 */
7955 { "prefetcht2", { Mb
}, 0 },
7958 /* MOD_0F18_REG_4 */
7959 { "nop/reserved", { Mb
}, 0 },
7962 /* MOD_0F18_REG_5 */
7963 { "nop/reserved", { Mb
}, 0 },
7966 /* MOD_0F18_REG_6 */
7967 { "nop/reserved", { Mb
}, 0 },
7970 /* MOD_0F18_REG_7 */
7971 { "nop/reserved", { Mb
}, 0 },
7974 /* MOD_0F1A_PREFIX_0 */
7975 { "bndldx", { Gbnd
, Mv_bnd
}, 0 },
7976 { "nopQ", { Ev
}, 0 },
7979 /* MOD_0F1B_PREFIX_0 */
7980 { "bndstx", { Mv_bnd
, Gbnd
}, 0 },
7981 { "nopQ", { Ev
}, 0 },
7984 /* MOD_0F1B_PREFIX_1 */
7985 { "bndmk", { Gbnd
, Mv_bnd
}, 0 },
7986 { "nopQ", { Ev
}, 0 },
7989 /* MOD_0F1C_PREFIX_0 */
7990 { REG_TABLE (REG_0F1C_P_0_MOD_0
) },
7991 { "nopQ", { Ev
}, 0 },
7994 /* MOD_0F1E_PREFIX_1 */
7995 { "nopQ", { Ev
}, 0 },
7996 { REG_TABLE (REG_0F1E_P_1_MOD_3
) },
7999 /* MOD_0F2B_PREFIX_0 */
8000 {"movntps", { Mx
, XM
}, PREFIX_OPCODE
},
8003 /* MOD_0F2B_PREFIX_1 */
8004 {"movntss", { Md
, XM
}, PREFIX_OPCODE
},
8007 /* MOD_0F2B_PREFIX_2 */
8008 {"movntpd", { Mx
, XM
}, PREFIX_OPCODE
},
8011 /* MOD_0F2B_PREFIX_3 */
8012 {"movntsd", { Mq
, XM
}, PREFIX_OPCODE
},
8017 { "movmskpX", { Gdq
, XS
}, PREFIX_OPCODE
},
8020 /* MOD_0F71_REG_2 */
8022 { "psrlw", { MS
, Ib
}, PREFIX_OPCODE
},
8025 /* MOD_0F71_REG_4 */
8027 { "psraw", { MS
, Ib
}, PREFIX_OPCODE
},
8030 /* MOD_0F71_REG_6 */
8032 { "psllw", { MS
, Ib
}, PREFIX_OPCODE
},
8035 /* MOD_0F72_REG_2 */
8037 { "psrld", { MS
, Ib
}, PREFIX_OPCODE
},
8040 /* MOD_0F72_REG_4 */
8042 { "psrad", { MS
, Ib
}, PREFIX_OPCODE
},
8045 /* MOD_0F72_REG_6 */
8047 { "pslld", { MS
, Ib
}, PREFIX_OPCODE
},
8050 /* MOD_0F73_REG_2 */
8052 { "psrlq", { MS
, Ib
}, PREFIX_OPCODE
},
8055 /* MOD_0F73_REG_3 */
8057 { "psrldq", { XS
, Ib
}, PREFIX_DATA
},
8060 /* MOD_0F73_REG_6 */
8062 { "psllq", { MS
, Ib
}, PREFIX_OPCODE
},
8065 /* MOD_0F73_REG_7 */
8067 { "pslldq", { XS
, Ib
}, PREFIX_DATA
},
8070 /* MOD_0FAE_REG_0 */
8071 { "fxsave", { FXSAVE
}, 0 },
8072 { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3
) },
8075 /* MOD_0FAE_REG_1 */
8076 { "fxrstor", { FXSAVE
}, 0 },
8077 { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3
) },
8080 /* MOD_0FAE_REG_2 */
8081 { "ldmxcsr", { Md
}, 0 },
8082 { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3
) },
8085 /* MOD_0FAE_REG_3 */
8086 { "stmxcsr", { Md
}, 0 },
8087 { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3
) },
8090 /* MOD_0FAE_REG_4 */
8091 { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0
) },
8092 { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3
) },
8095 /* MOD_0FAE_REG_5 */
8096 { "xrstor", { FXSAVE
}, PREFIX_OPCODE
},
8097 { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3
) },
8100 /* MOD_0FAE_REG_6 */
8101 { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0
) },
8102 { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3
) },
8105 /* MOD_0FAE_REG_7 */
8106 { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0
) },
8107 { RM_TABLE (RM_0FAE_REG_7_MOD_3
) },
8111 { "lssS", { Gv
, Mp
}, 0 },
8115 { "lfsS", { Gv
, Mp
}, 0 },
8119 { "lgsS", { Gv
, Mp
}, 0 },
8123 { "movntiS", { Edq
, Gdq
}, PREFIX_OPCODE
},
8126 /* MOD_0FC7_REG_3 */
8127 { "xrstors", { FXSAVE
}, 0 },
8130 /* MOD_0FC7_REG_4 */
8131 { "xsavec", { FXSAVE
}, 0 },
8134 /* MOD_0FC7_REG_5 */
8135 { "xsaves", { FXSAVE
}, 0 },
8138 /* MOD_0FC7_REG_6 */
8139 { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0
) },
8140 { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3
) }
8143 /* MOD_0FC7_REG_7 */
8144 { "vmptrst", { Mq
}, 0 },
8145 { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3
) }
8150 { "pmovmskb", { Gdq
, MS
}, 0 },
8153 /* MOD_0FE7_PREFIX_2 */
8154 { "movntdq", { Mx
, XM
}, 0 },
8157 /* MOD_0FF0_PREFIX_3 */
8158 { "lddqu", { XM
, M
}, 0 },
8162 { "movntdqa", { XM
, Mx
}, PREFIX_DATA
},
8165 /* MOD_VEX_0F3849_X86_64_P_0_W_0 */
8166 { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0
) },
8167 { REG_TABLE (REG_VEX_0F3849_X86_64_P_0_W_0_M_1
) },
8170 /* MOD_VEX_0F3849_X86_64_P_2_W_0 */
8171 { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0
) },
8174 /* MOD_VEX_0F3849_X86_64_P_3_W_0 */
8176 { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0
) },
8179 /* MOD_VEX_0F384B_X86_64_P_1_W_0 */
8180 { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0
) },
8183 /* MOD_VEX_0F384B_X86_64_P_2_W_0 */
8184 { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0
) },
8187 /* MOD_VEX_0F384B_X86_64_P_3_W_0 */
8188 { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0
) },
8191 /* MOD_VEX_0F385C_X86_64_P_1_W_0 */
8193 { VEX_LEN_TABLE (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0
) },
8196 /* MOD_VEX_0F385E_X86_64_P_0_W_0 */
8198 { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0
) },
8201 /* MOD_VEX_0F385E_X86_64_P_1_W_0 */
8203 { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0
) },
8206 /* MOD_VEX_0F385E_X86_64_P_2_W_0 */
8208 { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0
) },
8211 /* MOD_VEX_0F385E_X86_64_P_3_W_0 */
8213 { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0
) },
8217 { "wrussK", { M
, Gdq
}, PREFIX_DATA
},
8220 /* MOD_0F38F6_PREFIX_0 */
8221 { "wrssK", { M
, Gdq
}, PREFIX_OPCODE
},
8224 /* MOD_0F38F8_PREFIX_1 */
8225 { "enqcmds", { Gva
, M
}, PREFIX_OPCODE
},
8228 /* MOD_0F38F8_PREFIX_2 */
8229 { "movdir64b", { Gva
, M
}, PREFIX_OPCODE
},
8232 /* MOD_0F38F8_PREFIX_3 */
8233 { "enqcmd", { Gva
, M
}, PREFIX_OPCODE
},
8237 { "movdiri", { Edq
, Gdq
}, PREFIX_OPCODE
},
8241 { "bound{S|}", { Gv
, Ma
}, 0 },
8242 { EVEX_TABLE (EVEX_0F
) },
8246 { "lesS", { Gv
, Mp
}, 0 },
8247 { VEX_C4_TABLE (VEX_0F
) },
8251 { "ldsS", { Gv
, Mp
}, 0 },
8252 { VEX_C5_TABLE (VEX_0F
) },
8255 /* MOD_VEX_0F12_PREFIX_0 */
8256 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0
) },
8257 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1
) },
8260 /* MOD_VEX_0F12_PREFIX_2 */
8261 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2_M_0
) },
8265 { VEX_LEN_TABLE (VEX_LEN_0F13_M_0
) },
8268 /* MOD_VEX_0F16_PREFIX_0 */
8269 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0
) },
8270 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1
) },
8273 /* MOD_VEX_0F16_PREFIX_2 */
8274 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2_M_0
) },
8278 { VEX_LEN_TABLE (VEX_LEN_0F17_M_0
) },
8282 { "vmovntpX", { Mx
, XM
}, PREFIX_OPCODE
},
8285 /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
8287 { "kandw", { MaskG
, MaskVex
, MaskE
}, 0 },
8290 /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
8292 { "kandq", { MaskG
, MaskVex
, MaskE
}, 0 },
8295 /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
8297 { "kandb", { MaskG
, MaskVex
, MaskE
}, 0 },
8300 /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
8302 { "kandd", { MaskG
, MaskVex
, MaskE
}, 0 },
8305 /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
8307 { "kandnw", { MaskG
, MaskVex
, MaskE
}, 0 },
8310 /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
8312 { "kandnq", { MaskG
, MaskVex
, MaskE
}, 0 },
8315 /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
8317 { "kandnb", { MaskG
, MaskVex
, MaskE
}, 0 },
8320 /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
8322 { "kandnd", { MaskG
, MaskVex
, MaskE
}, 0 },
8325 /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
8327 { "knotw", { MaskG
, MaskE
}, 0 },
8330 /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
8332 { "knotq", { MaskG
, MaskE
}, 0 },
8335 /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
8337 { "knotb", { MaskG
, MaskE
}, 0 },
8340 /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
8342 { "knotd", { MaskG
, MaskE
}, 0 },
8345 /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
8347 { "korw", { MaskG
, MaskVex
, MaskE
}, 0 },
8350 /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
8352 { "korq", { MaskG
, MaskVex
, MaskE
}, 0 },
8355 /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
8357 { "korb", { MaskG
, MaskVex
, MaskE
}, 0 },
8360 /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
8362 { "kord", { MaskG
, MaskVex
, MaskE
}, 0 },
8365 /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
8367 { "kxnorw", { MaskG
, MaskVex
, MaskE
}, 0 },
8370 /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
8372 { "kxnorq", { MaskG
, MaskVex
, MaskE
}, 0 },
8375 /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
8377 { "kxnorb", { MaskG
, MaskVex
, MaskE
}, 0 },
8380 /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
8382 { "kxnord", { MaskG
, MaskVex
, MaskE
}, 0 },
8385 /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
8387 { "kxorw", { MaskG
, MaskVex
, MaskE
}, 0 },
8390 /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
8392 { "kxorq", { MaskG
, MaskVex
, MaskE
}, 0 },
8395 /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
8397 { "kxorb", { MaskG
, MaskVex
, MaskE
}, 0 },
8400 /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
8402 { "kxord", { MaskG
, MaskVex
, MaskE
}, 0 },
8405 /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
8407 { "kaddw", { MaskG
, MaskVex
, MaskE
}, 0 },
8410 /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
8412 { "kaddq", { MaskG
, MaskVex
, MaskE
}, 0 },
8415 /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
8417 { "kaddb", { MaskG
, MaskVex
, MaskE
}, 0 },
8420 /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
8422 { "kaddd", { MaskG
, MaskVex
, MaskE
}, 0 },
8425 /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
8427 { "kunpckwd", { MaskG
, MaskVex
, MaskE
}, 0 },
8430 /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
8432 { "kunpckdq", { MaskG
, MaskVex
, MaskE
}, 0 },
8435 /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
8437 { "kunpckbw", { MaskG
, MaskVex
, MaskE
}, 0 },
8442 { "vmovmskpX", { Gdq
, XS
}, PREFIX_OPCODE
},
8445 /* MOD_VEX_0F71_REG_2 */
8447 { "vpsrlw", { Vex
, XS
, Ib
}, PREFIX_DATA
},
8450 /* MOD_VEX_0F71_REG_4 */
8452 { "vpsraw", { Vex
, XS
, Ib
}, PREFIX_DATA
},
8455 /* MOD_VEX_0F71_REG_6 */
8457 { "vpsllw", { Vex
, XS
, Ib
}, PREFIX_DATA
},
8460 /* MOD_VEX_0F72_REG_2 */
8462 { "vpsrld", { Vex
, XS
, Ib
}, PREFIX_DATA
},
8465 /* MOD_VEX_0F72_REG_4 */
8467 { "vpsrad", { Vex
, XS
, Ib
}, PREFIX_DATA
},
8470 /* MOD_VEX_0F72_REG_6 */
8472 { "vpslld", { Vex
, XS
, Ib
}, PREFIX_DATA
},
8475 /* MOD_VEX_0F73_REG_2 */
8477 { "vpsrlq", { Vex
, XS
, Ib
}, PREFIX_DATA
},
8480 /* MOD_VEX_0F73_REG_3 */
8482 { "vpsrldq", { Vex
, XS
, Ib
}, PREFIX_DATA
},
8485 /* MOD_VEX_0F73_REG_6 */
8487 { "vpsllq", { Vex
, XS
, Ib
}, PREFIX_DATA
},
8490 /* MOD_VEX_0F73_REG_7 */
8492 { "vpslldq", { Vex
, XS
, Ib
}, PREFIX_DATA
},
8495 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
8496 { "kmovw", { Ew
, MaskG
}, 0 },
8500 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
8501 { "kmovq", { Eq
, MaskG
}, 0 },
8505 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
8506 { "kmovb", { Eb
, MaskG
}, 0 },
8510 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
8511 { "kmovd", { Ed
, MaskG
}, 0 },
8515 /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
8517 { "kmovw", { MaskG
, Edq
}, 0 },
8520 /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
8522 { "kmovb", { MaskG
, Edq
}, 0 },
8525 /* MOD_VEX_0F92_P_3_LEN_0 */
8527 { "kmovK", { MaskG
, Edq
}, 0 },
8530 /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
8532 { "kmovw", { Gdq
, MaskE
}, 0 },
8535 /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
8537 { "kmovb", { Gdq
, MaskE
}, 0 },
8540 /* MOD_VEX_0F93_P_3_LEN_0 */
8542 { "kmovK", { Gdq
, MaskE
}, 0 },
8545 /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
8547 { "kortestw", { MaskG
, MaskE
}, 0 },
8550 /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
8552 { "kortestq", { MaskG
, MaskE
}, 0 },
8555 /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
8557 { "kortestb", { MaskG
, MaskE
}, 0 },
8560 /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
8562 { "kortestd", { MaskG
, MaskE
}, 0 },
8565 /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
8567 { "ktestw", { MaskG
, MaskE
}, 0 },
8570 /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
8572 { "ktestq", { MaskG
, MaskE
}, 0 },
8575 /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
8577 { "ktestb", { MaskG
, MaskE
}, 0 },
8580 /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
8582 { "ktestd", { MaskG
, MaskE
}, 0 },
8585 /* MOD_VEX_0FAE_REG_2 */
8586 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0
) },
8589 /* MOD_VEX_0FAE_REG_3 */
8590 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0
) },
8595 { "vpmovmskb", { Gdq
, XS
}, PREFIX_DATA
},
8599 { "vmovntdq", { Mx
, XM
}, PREFIX_DATA
},
8602 /* MOD_VEX_0FF0_PREFIX_3 */
8603 { "vlddqu", { XM
, M
}, 0 },
8606 /* MOD_VEX_0F381A */
8607 { VEX_LEN_TABLE (VEX_LEN_0F381A_M_0
) },
8610 /* MOD_VEX_0F382A */
8611 { "vmovntdqa", { XM
, Mx
}, PREFIX_DATA
},
8614 /* MOD_VEX_0F382C */
8615 { VEX_W_TABLE (VEX_W_0F382C_M_0
) },
8618 /* MOD_VEX_0F382D */
8619 { VEX_W_TABLE (VEX_W_0F382D_M_0
) },
8622 /* MOD_VEX_0F382E */
8623 { VEX_W_TABLE (VEX_W_0F382E_M_0
) },
8626 /* MOD_VEX_0F382F */
8627 { VEX_W_TABLE (VEX_W_0F382F_M_0
) },
8630 /* MOD_VEX_0F385A */
8631 { VEX_LEN_TABLE (VEX_LEN_0F385A_M_0
) },
8634 /* MOD_VEX_0F388C */
8635 { "vpmaskmov%DQ", { XM
, Vex
, Mx
}, PREFIX_DATA
},
8638 /* MOD_VEX_0F388E */
8639 { "vpmaskmov%DQ", { Mx
, Vex
, XM
}, PREFIX_DATA
},
8642 /* MOD_VEX_0F3A30_L_0 */
8644 { "kshiftr%BW", { MaskG
, MaskE
, Ib
}, PREFIX_DATA
},
8647 /* MOD_VEX_0F3A31_L_0 */
8649 { "kshiftr%DQ", { MaskG
, MaskE
, Ib
}, PREFIX_DATA
},
8652 /* MOD_VEX_0F3A32_L_0 */
8654 { "kshiftl%BW", { MaskG
, MaskE
, Ib
}, PREFIX_DATA
},
8657 /* MOD_VEX_0F3A33_L_0 */
8659 { "kshiftl%DQ", { MaskG
, MaskE
, Ib
}, PREFIX_DATA
},
8662 /* MOD_VEX_0FXOP_09_12 */
8664 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_12_M_1
) },
8667 #include "i386-dis-evex-mod.h"
8670 static const struct dis386 rm_table
[][8] = {
8673 { "xabort", { Skip_MODRM
, Ib
}, 0 },
8677 { "xbeginT", { Skip_MODRM
, Jdqw
}, 0 },
8681 { "enclv", { Skip_MODRM
}, 0 },
8682 { "vmcall", { Skip_MODRM
}, 0 },
8683 { "vmlaunch", { Skip_MODRM
}, 0 },
8684 { "vmresume", { Skip_MODRM
}, 0 },
8685 { "vmxoff", { Skip_MODRM
}, 0 },
8686 { "pconfig", { Skip_MODRM
}, 0 },
8690 { "monitor", { { OP_Monitor
, 0 } }, 0 },
8691 { "mwait", { { OP_Mwait
, 0 } }, 0 },
8692 { "clac", { Skip_MODRM
}, 0 },
8693 { "stac", { Skip_MODRM
}, 0 },
8697 { "encls", { Skip_MODRM
}, 0 },
8701 { "xgetbv", { Skip_MODRM
}, 0 },
8702 { "xsetbv", { Skip_MODRM
}, 0 },
8705 { "vmfunc", { Skip_MODRM
}, 0 },
8706 { "xend", { Skip_MODRM
}, 0 },
8707 { "xtest", { Skip_MODRM
}, 0 },
8708 { "enclu", { Skip_MODRM
}, 0 },
8712 { "vmrun", { Skip_MODRM
}, 0 },
8713 { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1
) },
8714 { "vmload", { Skip_MODRM
}, 0 },
8715 { "vmsave", { Skip_MODRM
}, 0 },
8716 { "stgi", { Skip_MODRM
}, 0 },
8717 { "clgi", { Skip_MODRM
}, 0 },
8718 { "skinit", { Skip_MODRM
}, 0 },
8719 { "invlpga", { Skip_MODRM
}, 0 },
8722 /* RM_0F01_REG_5_MOD_3 */
8723 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0
) },
8724 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_1
) },
8725 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2
) },
8729 { "rdpkru", { Skip_MODRM
}, 0 },
8730 { "wrpkru", { Skip_MODRM
}, 0 },
8733 /* RM_0F01_REG_7_MOD_3 */
8734 { "swapgs", { Skip_MODRM
}, 0 },
8735 { "rdtscp", { Skip_MODRM
}, 0 },
8736 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2
) },
8737 { "mwaitx", { { OP_Mwait
, eBX_reg
} }, PREFIX_OPCODE
},
8738 { "clzero", { Skip_MODRM
}, 0 },
8739 { "rdpru", { Skip_MODRM
}, 0 },
8742 /* RM_0F1E_P_1_MOD_3_REG_7 */
8743 { "nopQ", { Ev
}, 0 },
8744 { "nopQ", { Ev
}, 0 },
8745 { "endbr64", { Skip_MODRM
}, PREFIX_OPCODE
},
8746 { "endbr32", { Skip_MODRM
}, PREFIX_OPCODE
},
8747 { "nopQ", { Ev
}, 0 },
8748 { "nopQ", { Ev
}, 0 },
8749 { "nopQ", { Ev
}, 0 },
8750 { "nopQ", { Ev
}, 0 },
8753 /* RM_0FAE_REG_6_MOD_3 */
8754 { "mfence", { Skip_MODRM
}, 0 },
8757 /* RM_0FAE_REG_7_MOD_3 */
8758 { "sfence", { Skip_MODRM
}, 0 },
8762 /* RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0 */
8763 { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0
) },
8767 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
8769 /* We use the high bit to indicate different name for the same
8771 #define REP_PREFIX (0xf3 | 0x100)
8772 #define XACQUIRE_PREFIX (0xf2 | 0x200)
8773 #define XRELEASE_PREFIX (0xf3 | 0x400)
8774 #define BND_PREFIX (0xf2 | 0x400)
8775 #define NOTRACK_PREFIX (0x3e | 0x100)
8777 /* Remember if the current op is a jump instruction. */
8778 static bfd_boolean op_is_jump
= FALSE
;
8783 int newrex
, i
, length
;
8788 last_lock_prefix
= -1;
8789 last_repz_prefix
= -1;
8790 last_repnz_prefix
= -1;
8791 last_data_prefix
= -1;
8792 last_addr_prefix
= -1;
8793 last_rex_prefix
= -1;
8794 last_seg_prefix
= -1;
8796 active_seg_prefix
= 0;
8797 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
8798 all_prefixes
[i
] = 0;
8801 /* The maximum instruction length is 15bytes. */
8802 while (length
< MAX_CODE_LENGTH
- 1)
8804 FETCH_DATA (the_info
, codep
+ 1);
8808 /* REX prefixes family. */
8825 if (address_mode
== mode_64bit
)
8829 last_rex_prefix
= i
;
8832 prefixes
|= PREFIX_REPZ
;
8833 last_repz_prefix
= i
;
8836 prefixes
|= PREFIX_REPNZ
;
8837 last_repnz_prefix
= i
;
8840 prefixes
|= PREFIX_LOCK
;
8841 last_lock_prefix
= i
;
8844 prefixes
|= PREFIX_CS
;
8845 last_seg_prefix
= i
;
8846 active_seg_prefix
= PREFIX_CS
;
8849 prefixes
|= PREFIX_SS
;
8850 last_seg_prefix
= i
;
8851 active_seg_prefix
= PREFIX_SS
;
8854 prefixes
|= PREFIX_DS
;
8855 last_seg_prefix
= i
;
8856 active_seg_prefix
= PREFIX_DS
;
8859 prefixes
|= PREFIX_ES
;
8860 last_seg_prefix
= i
;
8861 active_seg_prefix
= PREFIX_ES
;
8864 prefixes
|= PREFIX_FS
;
8865 last_seg_prefix
= i
;
8866 active_seg_prefix
= PREFIX_FS
;
8869 prefixes
|= PREFIX_GS
;
8870 last_seg_prefix
= i
;
8871 active_seg_prefix
= PREFIX_GS
;
8874 prefixes
|= PREFIX_DATA
;
8875 last_data_prefix
= i
;
8878 prefixes
|= PREFIX_ADDR
;
8879 last_addr_prefix
= i
;
8882 /* fwait is really an instruction. If there are prefixes
8883 before the fwait, they belong to the fwait, *not* to the
8884 following instruction. */
8886 if (prefixes
|| rex
)
8888 prefixes
|= PREFIX_FWAIT
;
8890 /* This ensures that the previous REX prefixes are noticed
8891 as unused prefixes, as in the return case below. */
8895 prefixes
= PREFIX_FWAIT
;
8900 /* Rex is ignored when followed by another prefix. */
8906 if (*codep
!= FWAIT_OPCODE
)
8907 all_prefixes
[i
++] = *codep
;
8915 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
8919 prefix_name (int pref
, int sizeflag
)
8921 static const char *rexes
[16] =
8926 "rex.XB", /* 0x43 */
8928 "rex.RB", /* 0x45 */
8929 "rex.RX", /* 0x46 */
8930 "rex.RXB", /* 0x47 */
8932 "rex.WB", /* 0x49 */
8933 "rex.WX", /* 0x4a */
8934 "rex.WXB", /* 0x4b */
8935 "rex.WR", /* 0x4c */
8936 "rex.WRB", /* 0x4d */
8937 "rex.WRX", /* 0x4e */
8938 "rex.WRXB", /* 0x4f */
8943 /* REX prefixes family. */
8960 return rexes
[pref
- 0x40];
8980 return (sizeflag
& DFLAG
) ? "data16" : "data32";
8982 if (address_mode
== mode_64bit
)
8983 return (sizeflag
& AFLAG
) ? "addr32" : "addr64";
8985 return (sizeflag
& AFLAG
) ? "addr16" : "addr32";
8990 case XACQUIRE_PREFIX
:
8992 case XRELEASE_PREFIX
:
8996 case NOTRACK_PREFIX
:
9003 static char op_out
[MAX_OPERANDS
][100];
9004 static int op_ad
, op_index
[MAX_OPERANDS
];
9005 static int two_source_ops
;
9006 static bfd_vma op_address
[MAX_OPERANDS
];
9007 static bfd_vma op_riprel
[MAX_OPERANDS
];
9008 static bfd_vma start_pc
;
9011 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
9012 * (see topic "Redundant prefixes" in the "Differences from 8086"
9013 * section of the "Virtual 8086 Mode" chapter.)
9014 * 'pc' should be the address of this instruction, it will
9015 * be used to print the target address if this is a relative jump or call
9016 * The function returns the length of this instruction in bytes.
9019 static char intel_syntax
;
9020 static char intel_mnemonic
= !SYSV386_COMPAT
;
9021 static char open_char
;
9022 static char close_char
;
9023 static char separator_char
;
9024 static char scale_char
;
9032 static enum x86_64_isa isa64
;
9034 /* Here for backwards compatibility. When gdb stops using
9035 print_insn_i386_att and print_insn_i386_intel these functions can
9036 disappear, and print_insn_i386 be merged into print_insn. */
9038 print_insn_i386_att (bfd_vma pc
, disassemble_info
*info
)
9042 return print_insn (pc
, info
);
9046 print_insn_i386_intel (bfd_vma pc
, disassemble_info
*info
)
9050 return print_insn (pc
, info
);
9054 print_insn_i386 (bfd_vma pc
, disassemble_info
*info
)
9058 return print_insn (pc
, info
);
9062 print_i386_disassembler_options (FILE *stream
)
9064 fprintf (stream
, _("\n\
9065 The following i386/x86-64 specific disassembler options are supported for use\n\
9066 with the -M switch (multiple options should be separated by commas):\n"));
9068 fprintf (stream
, _(" x86-64 Disassemble in 64bit mode\n"));
9069 fprintf (stream
, _(" i386 Disassemble in 32bit mode\n"));
9070 fprintf (stream
, _(" i8086 Disassemble in 16bit mode\n"));
9071 fprintf (stream
, _(" att Display instruction in AT&T syntax\n"));
9072 fprintf (stream
, _(" intel Display instruction in Intel syntax\n"));
9073 fprintf (stream
, _(" att-mnemonic\n"
9074 " Display instruction in AT&T mnemonic\n"));
9075 fprintf (stream
, _(" intel-mnemonic\n"
9076 " Display instruction in Intel mnemonic\n"));
9077 fprintf (stream
, _(" addr64 Assume 64bit address size\n"));
9078 fprintf (stream
, _(" addr32 Assume 32bit address size\n"));
9079 fprintf (stream
, _(" addr16 Assume 16bit address size\n"));
9080 fprintf (stream
, _(" data32 Assume 32bit data size\n"));
9081 fprintf (stream
, _(" data16 Assume 16bit data size\n"));
9082 fprintf (stream
, _(" suffix Always display instruction suffix in AT&T syntax\n"));
9083 fprintf (stream
, _(" amd64 Display instruction in AMD64 ISA\n"));
9084 fprintf (stream
, _(" intel64 Display instruction in Intel64 ISA\n"));
9088 static const struct dis386 bad_opcode
= { "(bad)", { XX
}, 0 };
9090 /* Get a pointer to struct dis386 with a valid name. */
9092 static const struct dis386
*
9093 get_valid_dis386 (const struct dis386
*dp
, disassemble_info
*info
)
9095 int vindex
, vex_table_index
;
9097 if (dp
->name
!= NULL
)
9100 switch (dp
->op
[0].bytemode
)
9103 dp
= ®_table
[dp
->op
[1].bytemode
][modrm
.reg
];
9107 vindex
= modrm
.mod
== 0x3 ? 1 : 0;
9108 dp
= &mod_table
[dp
->op
[1].bytemode
][vindex
];
9112 dp
= &rm_table
[dp
->op
[1].bytemode
][modrm
.rm
];
9115 case USE_PREFIX_TABLE
:
9118 /* The prefix in VEX is implicit. */
9124 case REPE_PREFIX_OPCODE
:
9127 case DATA_PREFIX_OPCODE
:
9130 case REPNE_PREFIX_OPCODE
:
9140 int last_prefix
= -1;
9143 /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
9144 When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
9146 if ((prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0)
9148 if (last_repz_prefix
> last_repnz_prefix
)
9151 prefix
= PREFIX_REPZ
;
9152 last_prefix
= last_repz_prefix
;
9157 prefix
= PREFIX_REPNZ
;
9158 last_prefix
= last_repnz_prefix
;
9161 /* Check if prefix should be ignored. */
9162 if ((((prefix_table
[dp
->op
[1].bytemode
][vindex
].prefix_requirement
9163 & PREFIX_IGNORED
) >> PREFIX_IGNORED_SHIFT
)
9168 if (vindex
== 0 && (prefixes
& PREFIX_DATA
) != 0)
9171 prefix
= PREFIX_DATA
;
9172 last_prefix
= last_data_prefix
;
9177 used_prefixes
|= prefix
;
9178 all_prefixes
[last_prefix
] = 0;
9181 dp
= &prefix_table
[dp
->op
[1].bytemode
][vindex
];
9184 case USE_X86_64_TABLE
:
9185 vindex
= address_mode
== mode_64bit
? 1 : 0;
9186 dp
= &x86_64_table
[dp
->op
[1].bytemode
][vindex
];
9189 case USE_3BYTE_TABLE
:
9190 FETCH_DATA (info
, codep
+ 2);
9192 dp
= &three_byte_table
[dp
->op
[1].bytemode
][vindex
];
9194 modrm
.mod
= (*codep
>> 6) & 3;
9195 modrm
.reg
= (*codep
>> 3) & 7;
9196 modrm
.rm
= *codep
& 7;
9199 case USE_VEX_LEN_TABLE
:
9216 dp
= &vex_len_table
[dp
->op
[1].bytemode
][vindex
];
9219 case USE_EVEX_LEN_TABLE
:
9239 dp
= &evex_len_table
[dp
->op
[1].bytemode
][vindex
];
9242 case USE_XOP_8F_TABLE
:
9243 FETCH_DATA (info
, codep
+ 3);
9244 rex
= ~(*codep
>> 5) & 0x7;
9246 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
9247 switch ((*codep
& 0x1f))
9253 vex_table_index
= XOP_08
;
9256 vex_table_index
= XOP_09
;
9259 vex_table_index
= XOP_0A
;
9263 vex
.w
= *codep
& 0x80;
9264 if (vex
.w
&& address_mode
== mode_64bit
)
9267 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
9268 if (address_mode
!= mode_64bit
)
9270 /* In 16/32-bit mode REX_B is silently ignored. */
9274 vex
.length
= (*codep
& 0x4) ? 256 : 128;
9275 switch ((*codep
& 0x3))
9280 vex
.prefix
= DATA_PREFIX_OPCODE
;
9283 vex
.prefix
= REPE_PREFIX_OPCODE
;
9286 vex
.prefix
= REPNE_PREFIX_OPCODE
;
9292 dp
= &xop_table
[vex_table_index
][vindex
];
9295 FETCH_DATA (info
, codep
+ 1);
9296 modrm
.mod
= (*codep
>> 6) & 3;
9297 modrm
.reg
= (*codep
>> 3) & 7;
9298 modrm
.rm
= *codep
& 7;
9300 /* No XOP encoding so far allows for a non-zero embedded prefix. Avoid
9301 having to decode the bits for every otherwise valid encoding. */
9306 case USE_VEX_C4_TABLE
:
9308 FETCH_DATA (info
, codep
+ 3);
9309 rex
= ~(*codep
>> 5) & 0x7;
9310 switch ((*codep
& 0x1f))
9316 vex_table_index
= VEX_0F
;
9319 vex_table_index
= VEX_0F38
;
9322 vex_table_index
= VEX_0F3A
;
9326 vex
.w
= *codep
& 0x80;
9327 if (address_mode
== mode_64bit
)
9334 /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
9335 is ignored, other REX bits are 0 and the highest bit in
9336 VEX.vvvv is also ignored (but we mustn't clear it here). */
9339 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
9340 vex
.length
= (*codep
& 0x4) ? 256 : 128;
9341 switch ((*codep
& 0x3))
9346 vex
.prefix
= DATA_PREFIX_OPCODE
;
9349 vex
.prefix
= REPE_PREFIX_OPCODE
;
9352 vex
.prefix
= REPNE_PREFIX_OPCODE
;
9358 dp
= &vex_table
[vex_table_index
][vindex
];
9360 /* There is no MODRM byte for VEX0F 77. */
9361 if (vex_table_index
!= VEX_0F
|| vindex
!= 0x77)
9363 FETCH_DATA (info
, codep
+ 1);
9364 modrm
.mod
= (*codep
>> 6) & 3;
9365 modrm
.reg
= (*codep
>> 3) & 7;
9366 modrm
.rm
= *codep
& 7;
9370 case USE_VEX_C5_TABLE
:
9372 FETCH_DATA (info
, codep
+ 2);
9373 rex
= (*codep
& 0x80) ? 0 : REX_R
;
9375 /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
9377 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
9378 vex
.length
= (*codep
& 0x4) ? 256 : 128;
9379 switch ((*codep
& 0x3))
9384 vex
.prefix
= DATA_PREFIX_OPCODE
;
9387 vex
.prefix
= REPE_PREFIX_OPCODE
;
9390 vex
.prefix
= REPNE_PREFIX_OPCODE
;
9396 dp
= &vex_table
[dp
->op
[1].bytemode
][vindex
];
9398 /* There is no MODRM byte for VEX 77. */
9401 FETCH_DATA (info
, codep
+ 1);
9402 modrm
.mod
= (*codep
>> 6) & 3;
9403 modrm
.reg
= (*codep
>> 3) & 7;
9404 modrm
.rm
= *codep
& 7;
9408 case USE_VEX_W_TABLE
:
9412 dp
= &vex_w_table
[dp
->op
[1].bytemode
][vex
.w
? 1 : 0];
9415 case USE_EVEX_TABLE
:
9419 FETCH_DATA (info
, codep
+ 4);
9420 /* The first byte after 0x62. */
9421 rex
= ~(*codep
>> 5) & 0x7;
9422 vex
.r
= *codep
& 0x10;
9423 switch ((*codep
& 0xf))
9428 vex_table_index
= EVEX_0F
;
9431 vex_table_index
= EVEX_0F38
;
9434 vex_table_index
= EVEX_0F3A
;
9438 /* The second byte after 0x62. */
9440 vex
.w
= *codep
& 0x80;
9441 if (vex
.w
&& address_mode
== mode_64bit
)
9444 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
9447 if (!(*codep
& 0x4))
9450 switch ((*codep
& 0x3))
9455 vex
.prefix
= DATA_PREFIX_OPCODE
;
9458 vex
.prefix
= REPE_PREFIX_OPCODE
;
9461 vex
.prefix
= REPNE_PREFIX_OPCODE
;
9465 /* The third byte after 0x62. */
9468 /* Remember the static rounding bits. */
9469 vex
.ll
= (*codep
>> 5) & 3;
9470 vex
.b
= (*codep
& 0x10) != 0;
9472 vex
.v
= *codep
& 0x8;
9473 vex
.mask_register_specifier
= *codep
& 0x7;
9474 vex
.zeroing
= *codep
& 0x80;
9476 if (address_mode
!= mode_64bit
)
9478 /* In 16/32-bit mode silently ignore following bits. */
9487 dp
= &evex_table
[vex_table_index
][vindex
];
9489 FETCH_DATA (info
, codep
+ 1);
9490 modrm
.mod
= (*codep
>> 6) & 3;
9491 modrm
.reg
= (*codep
>> 3) & 7;
9492 modrm
.rm
= *codep
& 7;
9494 /* Set vector length. */
9495 if (modrm
.mod
== 3 && vex
.b
)
9524 if (dp
->name
!= NULL
)
9527 return get_valid_dis386 (dp
, info
);
9531 get_sib (disassemble_info
*info
, int sizeflag
)
9533 /* If modrm.mod == 3, operand must be register. */
9535 && ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
9539 FETCH_DATA (info
, codep
+ 2);
9540 sib
.index
= (codep
[1] >> 3) & 7;
9541 sib
.scale
= (codep
[1] >> 6) & 3;
9542 sib
.base
= codep
[1] & 7;
9547 print_insn (bfd_vma pc
, disassemble_info
*info
)
9549 const struct dis386
*dp
;
9551 char *op_txt
[MAX_OPERANDS
];
9553 int sizeflag
, orig_sizeflag
;
9555 struct dis_private priv
;
9558 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
9559 if ((info
->mach
& bfd_mach_i386_i386
) != 0)
9560 address_mode
= mode_32bit
;
9561 else if (info
->mach
== bfd_mach_i386_i8086
)
9563 address_mode
= mode_16bit
;
9564 priv
.orig_sizeflag
= 0;
9567 address_mode
= mode_64bit
;
9569 if (intel_syntax
== (char) -1)
9570 intel_syntax
= (info
->mach
& bfd_mach_i386_intel_syntax
) != 0;
9572 for (p
= info
->disassembler_options
; p
!= NULL
; )
9574 if (CONST_STRNEQ (p
, "amd64"))
9576 else if (CONST_STRNEQ (p
, "intel64"))
9578 else if (CONST_STRNEQ (p
, "x86-64"))
9580 address_mode
= mode_64bit
;
9581 priv
.orig_sizeflag
|= AFLAG
| DFLAG
;
9583 else if (CONST_STRNEQ (p
, "i386"))
9585 address_mode
= mode_32bit
;
9586 priv
.orig_sizeflag
|= AFLAG
| DFLAG
;
9588 else if (CONST_STRNEQ (p
, "i8086"))
9590 address_mode
= mode_16bit
;
9591 priv
.orig_sizeflag
&= ~(AFLAG
| DFLAG
);
9593 else if (CONST_STRNEQ (p
, "intel"))
9596 if (CONST_STRNEQ (p
+ 5, "-mnemonic"))
9599 else if (CONST_STRNEQ (p
, "att"))
9602 if (CONST_STRNEQ (p
+ 3, "-mnemonic"))
9605 else if (CONST_STRNEQ (p
, "addr"))
9607 if (address_mode
== mode_64bit
)
9609 if (p
[4] == '3' && p
[5] == '2')
9610 priv
.orig_sizeflag
&= ~AFLAG
;
9611 else if (p
[4] == '6' && p
[5] == '4')
9612 priv
.orig_sizeflag
|= AFLAG
;
9616 if (p
[4] == '1' && p
[5] == '6')
9617 priv
.orig_sizeflag
&= ~AFLAG
;
9618 else if (p
[4] == '3' && p
[5] == '2')
9619 priv
.orig_sizeflag
|= AFLAG
;
9622 else if (CONST_STRNEQ (p
, "data"))
9624 if (p
[4] == '1' && p
[5] == '6')
9625 priv
.orig_sizeflag
&= ~DFLAG
;
9626 else if (p
[4] == '3' && p
[5] == '2')
9627 priv
.orig_sizeflag
|= DFLAG
;
9629 else if (CONST_STRNEQ (p
, "suffix"))
9630 priv
.orig_sizeflag
|= SUFFIX_ALWAYS
;
9632 p
= strchr (p
, ',');
9637 if (address_mode
== mode_64bit
&& sizeof (bfd_vma
) < 8)
9639 (*info
->fprintf_func
) (info
->stream
,
9640 _("64-bit address is disabled"));
9646 names64
= intel_names64
;
9647 names32
= intel_names32
;
9648 names16
= intel_names16
;
9649 names8
= intel_names8
;
9650 names8rex
= intel_names8rex
;
9651 names_seg
= intel_names_seg
;
9652 names_mm
= intel_names_mm
;
9653 names_bnd
= intel_names_bnd
;
9654 names_xmm
= intel_names_xmm
;
9655 names_ymm
= intel_names_ymm
;
9656 names_zmm
= intel_names_zmm
;
9657 names_tmm
= intel_names_tmm
;
9658 index64
= intel_index64
;
9659 index32
= intel_index32
;
9660 names_mask
= intel_names_mask
;
9661 index16
= intel_index16
;
9664 separator_char
= '+';
9669 names64
= att_names64
;
9670 names32
= att_names32
;
9671 names16
= att_names16
;
9672 names8
= att_names8
;
9673 names8rex
= att_names8rex
;
9674 names_seg
= att_names_seg
;
9675 names_mm
= att_names_mm
;
9676 names_bnd
= att_names_bnd
;
9677 names_xmm
= att_names_xmm
;
9678 names_ymm
= att_names_ymm
;
9679 names_zmm
= att_names_zmm
;
9680 names_tmm
= att_names_tmm
;
9681 index64
= att_index64
;
9682 index32
= att_index32
;
9683 names_mask
= att_names_mask
;
9684 index16
= att_index16
;
9687 separator_char
= ',';
9691 /* The output looks better if we put 7 bytes on a line, since that
9692 puts most long word instructions on a single line. Use 8 bytes
9694 if ((info
->mach
& bfd_mach_l1om
) != 0)
9695 info
->bytes_per_line
= 8;
9697 info
->bytes_per_line
= 7;
9699 info
->private_data
= &priv
;
9700 priv
.max_fetched
= priv
.the_buffer
;
9701 priv
.insn_start
= pc
;
9704 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
9712 start_codep
= priv
.the_buffer
;
9713 codep
= priv
.the_buffer
;
9715 if (OPCODES_SIGSETJMP (priv
.bailout
) != 0)
9719 /* Getting here means we tried for data but didn't get it. That
9720 means we have an incomplete instruction of some sort. Just
9721 print the first byte as a prefix or a .byte pseudo-op. */
9722 if (codep
> priv
.the_buffer
)
9724 name
= prefix_name (priv
.the_buffer
[0], priv
.orig_sizeflag
);
9726 (*info
->fprintf_func
) (info
->stream
, "%s", name
);
9729 /* Just print the first byte as a .byte instruction. */
9730 (*info
->fprintf_func
) (info
->stream
, ".byte 0x%x",
9731 (unsigned int) priv
.the_buffer
[0]);
9741 sizeflag
= priv
.orig_sizeflag
;
9743 if (!ckprefix () || rex_used
)
9745 /* Too many prefixes or unused REX prefixes. */
9747 i
< (int) ARRAY_SIZE (all_prefixes
) && all_prefixes
[i
];
9749 (*info
->fprintf_func
) (info
->stream
, "%s%s",
9751 prefix_name (all_prefixes
[i
], sizeflag
));
9757 FETCH_DATA (info
, codep
+ 1);
9758 two_source_ops
= (*codep
== 0x62) || (*codep
== 0xc8);
9760 if (((prefixes
& PREFIX_FWAIT
)
9761 && ((*codep
< 0xd8) || (*codep
> 0xdf))))
9763 /* Handle prefixes before fwait. */
9764 for (i
= 0; i
< fwait_prefix
&& all_prefixes
[i
];
9766 (*info
->fprintf_func
) (info
->stream
, "%s ",
9767 prefix_name (all_prefixes
[i
], sizeflag
));
9768 (*info
->fprintf_func
) (info
->stream
, "fwait");
9774 unsigned char threebyte
;
9777 FETCH_DATA (info
, codep
+ 1);
9779 dp
= &dis386_twobyte
[threebyte
];
9780 need_modrm
= twobyte_has_modrm
[*codep
];
9785 dp
= &dis386
[*codep
];
9786 need_modrm
= onebyte_has_modrm
[*codep
];
9790 /* Save sizeflag for printing the extra prefixes later before updating
9791 it for mnemonic and operand processing. The prefix names depend
9792 only on the address mode. */
9793 orig_sizeflag
= sizeflag
;
9794 if (prefixes
& PREFIX_ADDR
)
9796 if ((prefixes
& PREFIX_DATA
))
9802 FETCH_DATA (info
, codep
+ 1);
9803 modrm
.mod
= (*codep
>> 6) & 3;
9804 modrm
.reg
= (*codep
>> 3) & 7;
9805 modrm
.rm
= *codep
& 7;
9809 memset (&vex
, 0, sizeof (vex
));
9811 if (dp
->name
== NULL
&& dp
->op
[0].bytemode
== FLOATCODE
)
9813 get_sib (info
, sizeflag
);
9818 dp
= get_valid_dis386 (dp
, info
);
9819 if (dp
!= NULL
&& putop (dp
->name
, sizeflag
) == 0)
9821 get_sib (info
, sizeflag
);
9822 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
9825 op_ad
= MAX_OPERANDS
- 1 - i
;
9827 (*dp
->op
[i
].rtn
) (dp
->op
[i
].bytemode
, sizeflag
);
9828 /* For EVEX instruction after the last operand masking
9829 should be printed. */
9830 if (i
== 0 && vex
.evex
)
9832 /* Don't print {%k0}. */
9833 if (vex
.mask_register_specifier
)
9836 oappend (names_mask
[vex
.mask_register_specifier
]);
9846 /* Clear instruction information. */
9849 the_info
->insn_info_valid
= 0;
9850 the_info
->branch_delay_insns
= 0;
9851 the_info
->data_size
= 0;
9852 the_info
->insn_type
= dis_noninsn
;
9853 the_info
->target
= 0;
9854 the_info
->target2
= 0;
9857 /* Reset jump operation indicator. */
9861 int jump_detection
= 0;
9863 /* Extract flags. */
9864 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
9866 if ((dp
->op
[i
].rtn
== OP_J
)
9867 || (dp
->op
[i
].rtn
== OP_indirE
))
9868 jump_detection
|= 1;
9869 else if ((dp
->op
[i
].rtn
== BND_Fixup
)
9870 || (!dp
->op
[i
].rtn
&& !dp
->op
[i
].bytemode
))
9871 jump_detection
|= 2;
9872 else if ((dp
->op
[i
].bytemode
== cond_jump_mode
)
9873 || (dp
->op
[i
].bytemode
== loop_jcxz_mode
))
9874 jump_detection
|= 4;
9877 /* Determine if this is a jump or branch. */
9878 if ((jump_detection
& 0x3) == 0x3)
9881 if (jump_detection
& 0x4)
9882 the_info
->insn_type
= dis_condbranch
;
9884 the_info
->insn_type
=
9885 (dp
->name
&& !strncmp(dp
->name
, "call", 4))
9886 ? dis_jsr
: dis_branch
;
9890 /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
9891 are all 0s in inverted form. */
9892 if (need_vex
&& vex
.register_specifier
!= 0)
9894 (*info
->fprintf_func
) (info
->stream
, "(bad)");
9895 return end_codep
- priv
.the_buffer
;
9898 switch (dp
->prefix_requirement
)
9901 /* If only the data prefix is marked as mandatory, its absence renders
9902 the encoding invalid. Most other PREFIX_OPCODE rules still apply. */
9903 if (need_vex
? !vex
.prefix
: !(prefixes
& PREFIX_DATA
))
9905 (*info
->fprintf_func
) (info
->stream
, "(bad)");
9906 return end_codep
- priv
.the_buffer
;
9908 used_prefixes
|= PREFIX_DATA
;
9911 /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
9912 unused, opcode is invalid. Since the PREFIX_DATA prefix may be
9913 used by putop and MMX/SSE operand and may be overridden by the
9914 PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
9917 ? vex
.prefix
== REPE_PREFIX_OPCODE
9918 || vex
.prefix
== REPNE_PREFIX_OPCODE
9920 & (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0)
9922 & (PREFIX_REPZ
| PREFIX_REPNZ
)) == 0)
9924 ? vex
.prefix
== DATA_PREFIX_OPCODE
9926 & (PREFIX_REPZ
| PREFIX_REPNZ
| PREFIX_DATA
))
9928 && (used_prefixes
& PREFIX_DATA
) == 0))
9929 || (vex
.evex
&& dp
->prefix_requirement
!= PREFIX_DATA
9930 && !vex
.w
!= !(used_prefixes
& PREFIX_DATA
)))
9932 (*info
->fprintf_func
) (info
->stream
, "(bad)");
9933 return end_codep
- priv
.the_buffer
;
9938 /* Check if the REX prefix is used. */
9939 if ((rex
^ rex_used
) == 0 && !need_vex
&& last_rex_prefix
>= 0)
9940 all_prefixes
[last_rex_prefix
] = 0;
9942 /* Check if the SEG prefix is used. */
9943 if ((prefixes
& (PREFIX_CS
| PREFIX_SS
| PREFIX_DS
| PREFIX_ES
9944 | PREFIX_FS
| PREFIX_GS
)) != 0
9945 && (used_prefixes
& active_seg_prefix
) != 0)
9946 all_prefixes
[last_seg_prefix
] = 0;
9948 /* Check if the ADDR prefix is used. */
9949 if ((prefixes
& PREFIX_ADDR
) != 0
9950 && (used_prefixes
& PREFIX_ADDR
) != 0)
9951 all_prefixes
[last_addr_prefix
] = 0;
9953 /* Check if the DATA prefix is used. */
9954 if ((prefixes
& PREFIX_DATA
) != 0
9955 && (used_prefixes
& PREFIX_DATA
) != 0
9957 all_prefixes
[last_data_prefix
] = 0;
9959 /* Print the extra prefixes. */
9961 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
9962 if (all_prefixes
[i
])
9965 name
= prefix_name (all_prefixes
[i
], orig_sizeflag
);
9968 prefix_length
+= strlen (name
) + 1;
9969 (*info
->fprintf_func
) (info
->stream
, "%s ", name
);
9972 /* Check maximum code length. */
9973 if ((codep
- start_codep
) > MAX_CODE_LENGTH
)
9975 (*info
->fprintf_func
) (info
->stream
, "(bad)");
9976 return MAX_CODE_LENGTH
;
9979 obufp
= mnemonicendp
;
9980 for (i
= strlen (obuf
) + prefix_length
; i
< 6; i
++)
9983 (*info
->fprintf_func
) (info
->stream
, "%s", obuf
);
9985 /* The enter and bound instructions are printed with operands in the same
9986 order as the intel book; everything else is printed in reverse order. */
9987 if (intel_syntax
|| two_source_ops
)
9991 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
9992 op_txt
[i
] = op_out
[i
];
9994 if (intel_syntax
&& dp
&& dp
->op
[2].rtn
== OP_Rounding
9995 && dp
->op
[3].rtn
== OP_E
&& dp
->op
[4].rtn
== NULL
)
9997 op_txt
[2] = op_out
[3];
9998 op_txt
[3] = op_out
[2];
10001 for (i
= 0; i
< (MAX_OPERANDS
>> 1); ++i
)
10003 op_ad
= op_index
[i
];
10004 op_index
[i
] = op_index
[MAX_OPERANDS
- 1 - i
];
10005 op_index
[MAX_OPERANDS
- 1 - i
] = op_ad
;
10006 riprel
= op_riprel
[i
];
10007 op_riprel
[i
] = op_riprel
[MAX_OPERANDS
- 1 - i
];
10008 op_riprel
[MAX_OPERANDS
- 1 - i
] = riprel
;
10013 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
10014 op_txt
[MAX_OPERANDS
- 1 - i
] = op_out
[i
];
10018 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
10022 (*info
->fprintf_func
) (info
->stream
, ",");
10023 if (op_index
[i
] != -1 && !op_riprel
[i
])
10025 bfd_vma target
= (bfd_vma
) op_address
[op_index
[i
]];
10027 if (the_info
&& op_is_jump
)
10029 the_info
->insn_info_valid
= 1;
10030 the_info
->branch_delay_insns
= 0;
10031 the_info
->data_size
= 0;
10032 the_info
->target
= target
;
10033 the_info
->target2
= 0;
10035 (*info
->print_address_func
) (target
, info
);
10038 (*info
->fprintf_func
) (info
->stream
, "%s", op_txt
[i
]);
10042 for (i
= 0; i
< MAX_OPERANDS
; i
++)
10043 if (op_index
[i
] != -1 && op_riprel
[i
])
10045 (*info
->fprintf_func
) (info
->stream
, " # ");
10046 (*info
->print_address_func
) ((bfd_vma
) (start_pc
+ (codep
- start_codep
)
10047 + op_address
[op_index
[i
]]), info
);
10050 return codep
- priv
.the_buffer
;
10053 static const char *float_mem
[] = {
10128 static const unsigned char float_mem_mode
[] = {
10203 #define ST { OP_ST, 0 }
10204 #define STi { OP_STi, 0 }
10206 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
10207 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
10208 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
10209 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
10210 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
10211 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
10212 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
10213 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
10214 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
10216 static const struct dis386 float_reg
[][8] = {
10219 { "fadd", { ST
, STi
}, 0 },
10220 { "fmul", { ST
, STi
}, 0 },
10221 { "fcom", { STi
}, 0 },
10222 { "fcomp", { STi
}, 0 },
10223 { "fsub", { ST
, STi
}, 0 },
10224 { "fsubr", { ST
, STi
}, 0 },
10225 { "fdiv", { ST
, STi
}, 0 },
10226 { "fdivr", { ST
, STi
}, 0 },
10230 { "fld", { STi
}, 0 },
10231 { "fxch", { STi
}, 0 },
10241 { "fcmovb", { ST
, STi
}, 0 },
10242 { "fcmove", { ST
, STi
}, 0 },
10243 { "fcmovbe",{ ST
, STi
}, 0 },
10244 { "fcmovu", { ST
, STi
}, 0 },
10252 { "fcmovnb",{ ST
, STi
}, 0 },
10253 { "fcmovne",{ ST
, STi
}, 0 },
10254 { "fcmovnbe",{ ST
, STi
}, 0 },
10255 { "fcmovnu",{ ST
, STi
}, 0 },
10257 { "fucomi", { ST
, STi
}, 0 },
10258 { "fcomi", { ST
, STi
}, 0 },
10263 { "fadd", { STi
, ST
}, 0 },
10264 { "fmul", { STi
, ST
}, 0 },
10267 { "fsub{!M|r}", { STi
, ST
}, 0 },
10268 { "fsub{M|}", { STi
, ST
}, 0 },
10269 { "fdiv{!M|r}", { STi
, ST
}, 0 },
10270 { "fdiv{M|}", { STi
, ST
}, 0 },
10274 { "ffree", { STi
}, 0 },
10276 { "fst", { STi
}, 0 },
10277 { "fstp", { STi
}, 0 },
10278 { "fucom", { STi
}, 0 },
10279 { "fucomp", { STi
}, 0 },
10285 { "faddp", { STi
, ST
}, 0 },
10286 { "fmulp", { STi
, ST
}, 0 },
10289 { "fsub{!M|r}p", { STi
, ST
}, 0 },
10290 { "fsub{M|}p", { STi
, ST
}, 0 },
10291 { "fdiv{!M|r}p", { STi
, ST
}, 0 },
10292 { "fdiv{M|}p", { STi
, ST
}, 0 },
10296 { "ffreep", { STi
}, 0 },
10301 { "fucomip", { ST
, STi
}, 0 },
10302 { "fcomip", { ST
, STi
}, 0 },
10307 static char *fgrps
[][8] = {
10310 "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10315 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10320 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
10325 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
10330 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
10335 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
10340 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10345 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
10346 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
10351 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10356 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10361 swap_operand (void)
10363 mnemonicendp
[0] = '.';
10364 mnemonicendp
[1] = 's';
10369 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED
,
10370 int sizeflag ATTRIBUTE_UNUSED
)
10372 /* Skip mod/rm byte. */
10378 dofloat (int sizeflag
)
10380 const struct dis386
*dp
;
10381 unsigned char floatop
;
10383 floatop
= codep
[-1];
10385 if (modrm
.mod
!= 3)
10387 int fp_indx
= (floatop
- 0xd8) * 8 + modrm
.reg
;
10389 putop (float_mem
[fp_indx
], sizeflag
);
10392 OP_E (float_mem_mode
[fp_indx
], sizeflag
);
10395 /* Skip mod/rm byte. */
10399 dp
= &float_reg
[floatop
- 0xd8][modrm
.reg
];
10400 if (dp
->name
== NULL
)
10402 putop (fgrps
[dp
->op
[0].bytemode
][modrm
.rm
], sizeflag
);
10404 /* Instruction fnstsw is only one with strange arg. */
10405 if (floatop
== 0xdf && codep
[-1] == 0xe0)
10406 strcpy (op_out
[0], names16
[0]);
10410 putop (dp
->name
, sizeflag
);
10415 (*dp
->op
[0].rtn
) (dp
->op
[0].bytemode
, sizeflag
);
10420 (*dp
->op
[1].rtn
) (dp
->op
[1].bytemode
, sizeflag
);
10424 /* Like oappend (below), but S is a string starting with '%'.
10425 In Intel syntax, the '%' is elided. */
10427 oappend_maybe_intel (const char *s
)
10429 oappend (s
+ intel_syntax
);
10433 OP_ST (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
10435 oappend_maybe_intel ("%st");
10439 OP_STi (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
10441 sprintf (scratchbuf
, "%%st(%d)", modrm
.rm
);
10442 oappend_maybe_intel (scratchbuf
);
10445 /* Capital letters in template are macros. */
10447 putop (const char *in_template
, int sizeflag
)
10452 unsigned int l
= 0, len
= 0;
10455 for (p
= in_template
; *p
; p
++)
10459 if (l
>= sizeof (last
) || !ISUPPER (*p
))
10478 while (*++p
!= '|')
10479 if (*p
== '}' || *p
== '\0')
10485 while (*++p
!= '}')
10497 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
10506 if (sizeflag
& SUFFIX_ALWAYS
)
10509 else if (l
== 1 && last
[0] == 'L')
10511 if (address_mode
== mode_64bit
10512 && !(prefixes
& PREFIX_ADDR
))
10525 if (intel_syntax
&& !alt
)
10527 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
10529 if (sizeflag
& DFLAG
)
10530 *obufp
++ = intel_syntax
? 'd' : 'l';
10532 *obufp
++ = intel_syntax
? 'w' : 's';
10533 used_prefixes
|= (prefixes
& PREFIX_DATA
);
10537 if (intel_syntax
|| !(sizeflag
& SUFFIX_ALWAYS
))
10540 if (modrm
.mod
== 3)
10546 if (sizeflag
& DFLAG
)
10547 *obufp
++ = intel_syntax
? 'd' : 'l';
10550 used_prefixes
|= (prefixes
& PREFIX_DATA
);
10556 case 'E': /* For jcxz/jecxz */
10557 if (address_mode
== mode_64bit
)
10559 if (sizeflag
& AFLAG
)
10565 if (sizeflag
& AFLAG
)
10567 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
10572 if ((prefixes
& PREFIX_ADDR
) || (sizeflag
& SUFFIX_ALWAYS
))
10574 if (sizeflag
& AFLAG
)
10575 *obufp
++ = address_mode
== mode_64bit
? 'q' : 'l';
10577 *obufp
++ = address_mode
== mode_64bit
? 'l' : 'w';
10578 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
10582 if (intel_syntax
|| (obufp
[-1] != 's' && !(sizeflag
& SUFFIX_ALWAYS
)))
10584 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
10588 if (!(rex
& REX_W
))
10589 used_prefixes
|= (prefixes
& PREFIX_DATA
);
10594 if ((prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_CS
10595 || (prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_DS
)
10597 used_prefixes
|= prefixes
& (PREFIX_CS
| PREFIX_DS
);
10600 if (prefixes
& PREFIX_DS
)
10616 if (intel_mnemonic
!= cond
)
10620 if ((prefixes
& PREFIX_FWAIT
) == 0)
10623 used_prefixes
|= PREFIX_FWAIT
;
10629 else if (intel_syntax
&& (sizeflag
& DFLAG
))
10633 if (!(rex
& REX_W
))
10634 used_prefixes
|= (prefixes
& PREFIX_DATA
);
10637 if (address_mode
== mode_64bit
10638 && (isa64
== intel64
|| (rex
& REX_W
)
10639 || !(prefixes
& PREFIX_DATA
)))
10641 if (sizeflag
& SUFFIX_ALWAYS
)
10645 /* Fall through. */
10649 if (((need_modrm
&& modrm
.mod
== 3) || !cond
)
10650 && !(sizeflag
& SUFFIX_ALWAYS
))
10652 /* Fall through. */
10654 if ((!(rex
& REX_W
) && (prefixes
& PREFIX_DATA
))
10655 || ((sizeflag
& SUFFIX_ALWAYS
)
10656 && address_mode
!= mode_64bit
))
10658 *obufp
++ = (sizeflag
& DFLAG
) ?
10659 intel_syntax
? 'd' : 'l' : 'w';
10660 used_prefixes
|= (prefixes
& PREFIX_DATA
);
10662 else if (sizeflag
& SUFFIX_ALWAYS
)
10665 else if (l
== 1 && last
[0] == 'L')
10667 if ((prefixes
& PREFIX_DATA
)
10669 || (sizeflag
& SUFFIX_ALWAYS
))
10676 if (sizeflag
& DFLAG
)
10677 *obufp
++ = intel_syntax
? 'd' : 'l';
10680 used_prefixes
|= (prefixes
& PREFIX_DATA
);
10690 if (intel_syntax
&& !alt
)
10693 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
10699 if (sizeflag
& DFLAG
)
10700 *obufp
++ = intel_syntax
? 'd' : 'l';
10703 used_prefixes
|= (prefixes
& PREFIX_DATA
);
10707 else if (l
== 1 && last
[0] == 'D')
10708 *obufp
++ = vex
.w
? 'q' : 'd';
10709 else if (l
== 1 && last
[0] == 'L')
10711 if (cond
? modrm
.mod
== 3 && !(sizeflag
& SUFFIX_ALWAYS
)
10712 : address_mode
!= mode_64bit
)
10719 else if((address_mode
== mode_64bit
&& need_modrm
&& cond
)
10720 || (sizeflag
& SUFFIX_ALWAYS
))
10721 *obufp
++ = intel_syntax
? 'd' : 'l';
10730 else if (sizeflag
& DFLAG
)
10739 if (intel_syntax
&& !p
[1]
10740 && ((rex
& REX_W
) || (sizeflag
& DFLAG
)))
10742 if (!(rex
& REX_W
))
10743 used_prefixes
|= (prefixes
& PREFIX_DATA
);
10751 if (sizeflag
& SUFFIX_ALWAYS
)
10757 if (sizeflag
& DFLAG
)
10761 used_prefixes
|= (prefixes
& PREFIX_DATA
);
10765 else if (l
== 1 && last
[0] == 'L')
10767 if (address_mode
== mode_64bit
10768 && !(prefixes
& PREFIX_ADDR
))
10783 else if (l
== 1 && last
[0] == 'L')
10798 /* operand size flag for cwtl, cbtw */
10807 else if (sizeflag
& DFLAG
)
10811 if (!(rex
& REX_W
))
10812 used_prefixes
|= (prefixes
& PREFIX_DATA
);
10818 if (last
[0] == 'X')
10819 *obufp
++ = vex
.w
? 'd': 's';
10820 else if (last
[0] == 'B')
10821 *obufp
++ = vex
.w
? 'w': 'b';
10832 ? vex
.prefix
== DATA_PREFIX_OPCODE
10833 : prefixes
& PREFIX_DATA
)
10836 used_prefixes
|= PREFIX_DATA
;
10842 if (l
== 1 && last
[0] == 'X')
10847 || ((modrm
.mod
== 3 || vex
.b
) && !(sizeflag
& SUFFIX_ALWAYS
)))
10849 switch (vex
.length
)
10869 /* These insns ignore ModR/M.mod: Force it to 3 for OP_E(). */
10871 if (!intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
10872 *obufp
++ = address_mode
== mode_64bit
? 'q' : 'l';
10874 else if (l
== 1 && last
[0] == 'X')
10876 if (!need_vex
|| !vex
.evex
)
10879 || ((modrm
.mod
== 3 || vex
.b
) && !(sizeflag
& SUFFIX_ALWAYS
)))
10881 switch (vex
.length
)
10902 if (isa64
== intel64
&& (rex
& REX_W
))
10908 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
10910 if (sizeflag
& DFLAG
)
10914 used_prefixes
|= (prefixes
& PREFIX_DATA
);
10923 mnemonicendp
= obufp
;
10928 oappend (const char *s
)
10930 obufp
= stpcpy (obufp
, s
);
10936 /* Only print the active segment register. */
10937 if (!active_seg_prefix
)
10940 used_prefixes
|= active_seg_prefix
;
10941 switch (active_seg_prefix
)
10944 oappend_maybe_intel ("%cs:");
10947 oappend_maybe_intel ("%ds:");
10950 oappend_maybe_intel ("%ss:");
10953 oappend_maybe_intel ("%es:");
10956 oappend_maybe_intel ("%fs:");
10959 oappend_maybe_intel ("%gs:");
10967 OP_indirE (int bytemode
, int sizeflag
)
10971 OP_E (bytemode
, sizeflag
);
10975 print_operand_value (char *buf
, int hex
, bfd_vma disp
)
10977 if (address_mode
== mode_64bit
)
10985 sprintf_vma (tmp
, disp
);
10986 for (i
= 0; tmp
[i
] == '0' && tmp
[i
+ 1]; i
++);
10987 strcpy (buf
+ 2, tmp
+ i
);
10991 bfd_signed_vma v
= disp
;
10998 /* Check for possible overflow on 0x8000000000000000. */
11001 strcpy (buf
, "9223372036854775808");
11015 tmp
[28 - i
] = (v
% 10) + '0';
11019 strcpy (buf
, tmp
+ 29 - i
);
11025 sprintf (buf
, "0x%x", (unsigned int) disp
);
11027 sprintf (buf
, "%d", (int) disp
);
11031 /* Put DISP in BUF as signed hex number. */
11034 print_displacement (char *buf
, bfd_vma disp
)
11036 bfd_signed_vma val
= disp
;
11045 /* Check for possible overflow. */
11048 switch (address_mode
)
11051 strcpy (buf
+ j
, "0x8000000000000000");
11054 strcpy (buf
+ j
, "0x80000000");
11057 strcpy (buf
+ j
, "0x8000");
11067 sprintf_vma (tmp
, (bfd_vma
) val
);
11068 for (i
= 0; tmp
[i
] == '0'; i
++)
11070 if (tmp
[i
] == '\0')
11072 strcpy (buf
+ j
, tmp
+ i
);
11076 intel_operand_size (int bytemode
, int sizeflag
)
11080 && (bytemode
== x_mode
11081 || bytemode
== evex_half_bcst_xmmq_mode
))
11084 oappend ("QWORD PTR ");
11086 oappend ("DWORD PTR ");
11095 oappend ("BYTE PTR ");
11100 oappend ("WORD PTR ");
11103 if (address_mode
== mode_64bit
&& isa64
== intel64
)
11105 oappend ("QWORD PTR ");
11108 /* Fall through. */
11110 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
11112 oappend ("QWORD PTR ");
11115 /* Fall through. */
11121 oappend ("QWORD PTR ");
11122 else if (bytemode
== dq_mode
)
11123 oappend ("DWORD PTR ");
11126 if (sizeflag
& DFLAG
)
11127 oappend ("DWORD PTR ");
11129 oappend ("WORD PTR ");
11130 used_prefixes
|= (prefixes
& PREFIX_DATA
);
11134 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
11136 oappend ("WORD PTR ");
11137 if (!(rex
& REX_W
))
11138 used_prefixes
|= (prefixes
& PREFIX_DATA
);
11141 if (sizeflag
& DFLAG
)
11142 oappend ("QWORD PTR ");
11144 oappend ("DWORD PTR ");
11145 used_prefixes
|= (prefixes
& PREFIX_DATA
);
11148 if (!(sizeflag
& DFLAG
) && isa64
== intel64
)
11149 oappend ("WORD PTR ");
11151 oappend ("DWORD PTR ");
11152 used_prefixes
|= (prefixes
& PREFIX_DATA
);
11157 oappend ("DWORD PTR ");
11161 oappend ("QWORD PTR ");
11164 if (address_mode
== mode_64bit
)
11165 oappend ("QWORD PTR ");
11167 oappend ("DWORD PTR ");
11170 if (sizeflag
& DFLAG
)
11171 oappend ("FWORD PTR ");
11173 oappend ("DWORD PTR ");
11174 used_prefixes
|= (prefixes
& PREFIX_DATA
);
11177 oappend ("TBYTE PTR ");
11181 case evex_x_gscat_mode
:
11182 case evex_x_nobcst_mode
:
11186 switch (vex
.length
)
11189 oappend ("XMMWORD PTR ");
11192 oappend ("YMMWORD PTR ");
11195 oappend ("ZMMWORD PTR ");
11202 oappend ("XMMWORD PTR ");
11205 oappend ("XMMWORD PTR ");
11208 oappend ("YMMWORD PTR ");
11211 case evex_half_bcst_xmmq_mode
:
11215 switch (vex
.length
)
11218 oappend ("QWORD PTR ");
11221 oappend ("XMMWORD PTR ");
11224 oappend ("YMMWORD PTR ");
11234 switch (vex
.length
)
11239 oappend ("BYTE PTR ");
11249 switch (vex
.length
)
11254 oappend ("WORD PTR ");
11264 switch (vex
.length
)
11269 oappend ("DWORD PTR ");
11279 switch (vex
.length
)
11284 oappend ("QWORD PTR ");
11294 switch (vex
.length
)
11297 oappend ("WORD PTR ");
11300 oappend ("DWORD PTR ");
11303 oappend ("QWORD PTR ");
11313 switch (vex
.length
)
11316 oappend ("DWORD PTR ");
11319 oappend ("QWORD PTR ");
11322 oappend ("XMMWORD PTR ");
11332 switch (vex
.length
)
11335 oappend ("QWORD PTR ");
11338 oappend ("YMMWORD PTR ");
11341 oappend ("ZMMWORD PTR ");
11351 switch (vex
.length
)
11355 oappend ("XMMWORD PTR ");
11362 oappend ("OWORD PTR ");
11364 case vex_scalar_w_dq_mode
:
11369 oappend ("QWORD PTR ");
11371 oappend ("DWORD PTR ");
11373 case vex_vsib_d_w_dq_mode
:
11374 case vex_vsib_q_w_dq_mode
:
11381 oappend ("QWORD PTR ");
11383 oappend ("DWORD PTR ");
11387 switch (vex
.length
)
11390 oappend ("XMMWORD PTR ");
11393 oappend ("YMMWORD PTR ");
11396 oappend ("ZMMWORD PTR ");
11403 case vex_vsib_q_w_d_mode
:
11404 case vex_vsib_d_w_d_mode
:
11405 if (!need_vex
|| !vex
.evex
)
11408 switch (vex
.length
)
11411 oappend ("QWORD PTR ");
11414 oappend ("XMMWORD PTR ");
11417 oappend ("YMMWORD PTR ");
11425 if (!need_vex
|| vex
.length
!= 128)
11428 oappend ("DWORD PTR ");
11430 oappend ("BYTE PTR ");
11436 oappend ("QWORD PTR ");
11438 oappend ("WORD PTR ");
11448 OP_E_register (int bytemode
, int sizeflag
)
11450 int reg
= modrm
.rm
;
11451 const char **names
;
11457 if ((sizeflag
& SUFFIX_ALWAYS
)
11458 && (bytemode
== b_swap_mode
11459 || bytemode
== bnd_swap_mode
11460 || bytemode
== v_swap_mode
))
11487 names
= address_mode
== mode_64bit
? names64
: names32
;
11490 case bnd_swap_mode
:
11499 if (address_mode
== mode_64bit
&& isa64
== intel64
)
11504 /* Fall through. */
11506 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
11512 /* Fall through. */
11522 else if (bytemode
!= v_mode
&& bytemode
!= v_swap_mode
)
11526 if (sizeflag
& DFLAG
)
11530 used_prefixes
|= (prefixes
& PREFIX_DATA
);
11534 if (!(sizeflag
& DFLAG
) && isa64
== intel64
)
11538 used_prefixes
|= (prefixes
& PREFIX_DATA
);
11541 names
= (address_mode
== mode_64bit
11542 ? names64
: names32
);
11543 if (!(prefixes
& PREFIX_ADDR
))
11544 names
= (address_mode
== mode_16bit
11545 ? names16
: names
);
11548 /* Remove "addr16/addr32". */
11549 all_prefixes
[last_addr_prefix
] = 0;
11550 names
= (address_mode
!= mode_32bit
11551 ? names32
: names16
);
11552 used_prefixes
|= PREFIX_ADDR
;
11562 names
= names_mask
;
11567 oappend (INTERNAL_DISASSEMBLER_ERROR
);
11570 oappend (names
[reg
]);
11574 OP_E_memory (int bytemode
, int sizeflag
)
11577 int add
= (rex
& REX_B
) ? 8 : 0;
11583 /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */
11585 && bytemode
!= x_mode
11586 && bytemode
!= xmmq_mode
11587 && bytemode
!= evex_half_bcst_xmmq_mode
)
11605 if (address_mode
!= mode_64bit
)
11615 case vex_scalar_w_dq_mode
:
11616 case vex_vsib_d_w_dq_mode
:
11617 case vex_vsib_d_w_d_mode
:
11618 case vex_vsib_q_w_dq_mode
:
11619 case vex_vsib_q_w_d_mode
:
11620 case evex_x_gscat_mode
:
11621 shift
= vex
.w
? 3 : 2;
11624 case evex_half_bcst_xmmq_mode
:
11628 shift
= vex
.w
? 3 : 2;
11631 /* Fall through. */
11635 case evex_x_nobcst_mode
:
11637 switch (vex
.length
)
11651 /* Make necessary corrections to shift for modes that need it. */
11652 if (bytemode
== xmmq_mode
11653 || bytemode
== evex_half_bcst_xmmq_mode
11654 || (bytemode
== ymmq_mode
&& vex
.length
== 128))
11656 else if (bytemode
== xmmqd_mode
)
11658 else if (bytemode
== xmmdw_mode
)
11673 shift
= vex
.w
? 1 : 0;
11684 intel_operand_size (bytemode
, sizeflag
);
11687 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
11689 /* 32/64 bit address mode */
11699 int addr32flag
= !((sizeflag
& AFLAG
)
11700 || bytemode
== v_bnd_mode
11701 || bytemode
== v_bndmk_mode
11702 || bytemode
== bnd_mode
11703 || bytemode
== bnd_swap_mode
);
11704 const char **indexes64
= names64
;
11705 const char **indexes32
= names32
;
11715 vindex
= sib
.index
;
11721 case vex_vsib_d_w_dq_mode
:
11722 case vex_vsib_d_w_d_mode
:
11723 case vex_vsib_q_w_dq_mode
:
11724 case vex_vsib_q_w_d_mode
:
11734 switch (vex
.length
)
11737 indexes64
= indexes32
= names_xmm
;
11741 || bytemode
== vex_vsib_q_w_dq_mode
11742 || bytemode
== vex_vsib_q_w_d_mode
)
11743 indexes64
= indexes32
= names_ymm
;
11745 indexes64
= indexes32
= names_xmm
;
11749 || bytemode
== vex_vsib_q_w_dq_mode
11750 || bytemode
== vex_vsib_q_w_d_mode
)
11751 indexes64
= indexes32
= names_zmm
;
11753 indexes64
= indexes32
= names_ymm
;
11760 haveindex
= vindex
!= 4;
11769 /* mandatory non-vector SIB must have sib */
11770 if (bytemode
== vex_sibmem_mode
)
11776 rbase
= base
+ add
;
11784 if (address_mode
== mode_64bit
&& !havesib
)
11787 if (riprel
&& bytemode
== v_bndmk_mode
)
11795 FETCH_DATA (the_info
, codep
+ 1);
11797 if ((disp
& 0x80) != 0)
11799 if (vex
.evex
&& shift
> 0)
11812 && address_mode
!= mode_16bit
)
11814 if (address_mode
== mode_64bit
)
11818 /* Without base nor index registers, zero-extend the
11819 lower 32-bit displacement to 64 bits. */
11820 disp
= (unsigned int) disp
;
11827 /* In 32-bit mode, we need index register to tell [offset]
11828 from [eiz*1 + offset]. */
11833 havedisp
= (havebase
11835 || (havesib
&& (haveindex
|| scale
!= 0)));
11838 if (modrm
.mod
!= 0 || base
== 5)
11840 if (havedisp
|| riprel
)
11841 print_displacement (scratchbuf
, disp
);
11843 print_operand_value (scratchbuf
, 1, disp
);
11844 oappend (scratchbuf
);
11848 oappend (!addr32flag
? "(%rip)" : "(%eip)");
11852 if ((havebase
|| haveindex
|| needindex
|| needaddr32
|| riprel
)
11853 && (address_mode
!= mode_64bit
11854 || ((bytemode
!= v_bnd_mode
)
11855 && (bytemode
!= v_bndmk_mode
)
11856 && (bytemode
!= bnd_mode
)
11857 && (bytemode
!= bnd_swap_mode
))))
11858 used_prefixes
|= PREFIX_ADDR
;
11860 if (havedisp
|| (intel_syntax
&& riprel
))
11862 *obufp
++ = open_char
;
11863 if (intel_syntax
&& riprel
)
11866 oappend (!addr32flag
? "rip" : "eip");
11870 oappend (address_mode
== mode_64bit
&& !addr32flag
11871 ? names64
[rbase
] : names32
[rbase
]);
11874 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
11875 print index to tell base + index from base. */
11879 || (havebase
&& base
!= ESP_REG_NUM
))
11881 if (!intel_syntax
|| havebase
)
11883 *obufp
++ = separator_char
;
11887 oappend (address_mode
== mode_64bit
&& !addr32flag
11888 ? indexes64
[vindex
] : indexes32
[vindex
]);
11890 oappend (address_mode
== mode_64bit
&& !addr32flag
11891 ? index64
: index32
);
11893 *obufp
++ = scale_char
;
11895 sprintf (scratchbuf
, "%d", 1 << scale
);
11896 oappend (scratchbuf
);
11900 && (disp
|| modrm
.mod
!= 0 || base
== 5))
11902 if (!havedisp
|| (bfd_signed_vma
) disp
>= 0)
11907 else if (modrm
.mod
!= 1 && disp
!= -disp
)
11911 disp
= - (bfd_signed_vma
) disp
;
11915 print_displacement (scratchbuf
, disp
);
11917 print_operand_value (scratchbuf
, 1, disp
);
11918 oappend (scratchbuf
);
11921 *obufp
++ = close_char
;
11924 else if (intel_syntax
)
11926 if (modrm
.mod
!= 0 || base
== 5)
11928 if (!active_seg_prefix
)
11930 oappend (names_seg
[ds_reg
- es_reg
]);
11933 print_operand_value (scratchbuf
, 1, disp
);
11934 oappend (scratchbuf
);
11938 else if (bytemode
== v_bnd_mode
11939 || bytemode
== v_bndmk_mode
11940 || bytemode
== bnd_mode
11941 || bytemode
== bnd_swap_mode
)
11948 /* 16 bit address mode */
11949 used_prefixes
|= prefixes
& PREFIX_ADDR
;
11956 if ((disp
& 0x8000) != 0)
11961 FETCH_DATA (the_info
, codep
+ 1);
11963 if ((disp
& 0x80) != 0)
11965 if (vex
.evex
&& shift
> 0)
11970 if ((disp
& 0x8000) != 0)
11976 if (modrm
.mod
!= 0 || modrm
.rm
== 6)
11978 print_displacement (scratchbuf
, disp
);
11979 oappend (scratchbuf
);
11982 if (modrm
.mod
!= 0 || modrm
.rm
!= 6)
11984 *obufp
++ = open_char
;
11986 oappend (index16
[modrm
.rm
]);
11988 && (disp
|| modrm
.mod
!= 0 || modrm
.rm
== 6))
11990 if ((bfd_signed_vma
) disp
>= 0)
11995 else if (modrm
.mod
!= 1)
11999 disp
= - (bfd_signed_vma
) disp
;
12002 print_displacement (scratchbuf
, disp
);
12003 oappend (scratchbuf
);
12006 *obufp
++ = close_char
;
12009 else if (intel_syntax
)
12011 if (!active_seg_prefix
)
12013 oappend (names_seg
[ds_reg
- es_reg
]);
12016 print_operand_value (scratchbuf
, 1, disp
& 0xffff);
12017 oappend (scratchbuf
);
12020 if (vex
.evex
&& vex
.b
12021 && (bytemode
== x_mode
12022 || bytemode
== xmmq_mode
12023 || bytemode
== evex_half_bcst_xmmq_mode
))
12026 || bytemode
== xmmq_mode
12027 || bytemode
== evex_half_bcst_xmmq_mode
)
12029 switch (vex
.length
)
12032 oappend ("{1to2}");
12035 oappend ("{1to4}");
12038 oappend ("{1to8}");
12046 switch (vex
.length
)
12049 oappend ("{1to4}");
12052 oappend ("{1to8}");
12055 oappend ("{1to16}");
12065 OP_E (int bytemode
, int sizeflag
)
12067 /* Skip mod/rm byte. */
12071 if (modrm
.mod
== 3)
12072 OP_E_register (bytemode
, sizeflag
);
12074 OP_E_memory (bytemode
, sizeflag
);
12078 OP_G (int bytemode
, int sizeflag
)
12081 const char **names
;
12091 oappend (names8rex
[modrm
.reg
+ add
]);
12093 oappend (names8
[modrm
.reg
+ add
]);
12096 oappend (names16
[modrm
.reg
+ add
]);
12101 oappend (names32
[modrm
.reg
+ add
]);
12104 oappend (names64
[modrm
.reg
+ add
]);
12107 if (modrm
.reg
> 0x3)
12112 oappend (names_bnd
[modrm
.reg
]);
12122 oappend (names64
[modrm
.reg
+ add
]);
12123 else if (bytemode
!= v_mode
&& bytemode
!= movsxd_mode
)
12124 oappend (names32
[modrm
.reg
+ add
]);
12127 if (sizeflag
& DFLAG
)
12128 oappend (names32
[modrm
.reg
+ add
]);
12130 oappend (names16
[modrm
.reg
+ add
]);
12131 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12135 names
= (address_mode
== mode_64bit
12136 ? names64
: names32
);
12137 if (!(prefixes
& PREFIX_ADDR
))
12139 if (address_mode
== mode_16bit
)
12144 /* Remove "addr16/addr32". */
12145 all_prefixes
[last_addr_prefix
] = 0;
12146 names
= (address_mode
!= mode_32bit
12147 ? names32
: names16
);
12148 used_prefixes
|= PREFIX_ADDR
;
12150 oappend (names
[modrm
.reg
+ add
]);
12153 if (address_mode
== mode_64bit
)
12154 oappend (names64
[modrm
.reg
+ add
]);
12156 oappend (names32
[modrm
.reg
+ add
]);
12160 if ((modrm
.reg
+ add
) > 0x7)
12165 oappend (names_mask
[modrm
.reg
+ add
]);
12168 oappend (INTERNAL_DISASSEMBLER_ERROR
);
12181 FETCH_DATA (the_info
, codep
+ 8);
12182 a
= *codep
++ & 0xff;
12183 a
|= (*codep
++ & 0xff) << 8;
12184 a
|= (*codep
++ & 0xff) << 16;
12185 a
|= (*codep
++ & 0xffu
) << 24;
12186 b
= *codep
++ & 0xff;
12187 b
|= (*codep
++ & 0xff) << 8;
12188 b
|= (*codep
++ & 0xff) << 16;
12189 b
|= (*codep
++ & 0xffu
) << 24;
12190 x
= a
+ ((bfd_vma
) b
<< 32);
12198 static bfd_signed_vma
12201 bfd_signed_vma x
= 0;
12203 FETCH_DATA (the_info
, codep
+ 4);
12204 x
= *codep
++ & (bfd_signed_vma
) 0xff;
12205 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
12206 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
12207 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
12211 static bfd_signed_vma
12214 bfd_signed_vma x
= 0;
12216 FETCH_DATA (the_info
, codep
+ 4);
12217 x
= *codep
++ & (bfd_signed_vma
) 0xff;
12218 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
12219 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
12220 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
12222 x
= (x
^ ((bfd_signed_vma
) 1 << 31)) - ((bfd_signed_vma
) 1 << 31);
12232 FETCH_DATA (the_info
, codep
+ 2);
12233 x
= *codep
++ & 0xff;
12234 x
|= (*codep
++ & 0xff) << 8;
12239 set_op (bfd_vma op
, int riprel
)
12241 op_index
[op_ad
] = op_ad
;
12242 if (address_mode
== mode_64bit
)
12244 op_address
[op_ad
] = op
;
12245 op_riprel
[op_ad
] = riprel
;
12249 /* Mask to get a 32-bit address. */
12250 op_address
[op_ad
] = op
& 0xffffffff;
12251 op_riprel
[op_ad
] = riprel
& 0xffffffff;
12256 OP_REG (int code
, int sizeflag
)
12263 case es_reg
: case ss_reg
: case cs_reg
:
12264 case ds_reg
: case fs_reg
: case gs_reg
:
12265 oappend (names_seg
[code
- es_reg
]);
12277 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
12278 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
12279 s
= names16
[code
- ax_reg
+ add
];
12281 case ah_reg
: case ch_reg
: case dh_reg
: case bh_reg
:
12283 /* Fall through. */
12284 case al_reg
: case cl_reg
: case dl_reg
: case bl_reg
:
12286 s
= names8rex
[code
- al_reg
+ add
];
12288 s
= names8
[code
- al_reg
];
12290 case rAX_reg
: case rCX_reg
: case rDX_reg
: case rBX_reg
:
12291 case rSP_reg
: case rBP_reg
: case rSI_reg
: case rDI_reg
:
12292 if (address_mode
== mode_64bit
12293 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
12295 s
= names64
[code
- rAX_reg
+ add
];
12298 code
+= eAX_reg
- rAX_reg
;
12299 /* Fall through. */
12300 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
12301 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
12304 s
= names64
[code
- eAX_reg
+ add
];
12307 if (sizeflag
& DFLAG
)
12308 s
= names32
[code
- eAX_reg
+ add
];
12310 s
= names16
[code
- eAX_reg
+ add
];
12311 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12315 s
= INTERNAL_DISASSEMBLER_ERROR
;
12322 OP_IMREG (int code
, int sizeflag
)
12334 case al_reg
: case cl_reg
:
12335 s
= names8
[code
- al_reg
];
12344 /* Fall through. */
12345 case z_mode_ax_reg
:
12346 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
12350 if (!(rex
& REX_W
))
12351 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12354 s
= INTERNAL_DISASSEMBLER_ERROR
;
12361 OP_I (int bytemode
, int sizeflag
)
12364 bfd_signed_vma mask
= -1;
12369 FETCH_DATA (the_info
, codep
+ 1);
12379 if (sizeflag
& DFLAG
)
12389 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12405 oappend (INTERNAL_DISASSEMBLER_ERROR
);
12410 scratchbuf
[0] = '$';
12411 print_operand_value (scratchbuf
+ 1, 1, op
);
12412 oappend_maybe_intel (scratchbuf
);
12413 scratchbuf
[0] = '\0';
12417 OP_I64 (int bytemode
, int sizeflag
)
12419 if (bytemode
!= v_mode
|| address_mode
!= mode_64bit
|| !(rex
& REX_W
))
12421 OP_I (bytemode
, sizeflag
);
12427 scratchbuf
[0] = '$';
12428 print_operand_value (scratchbuf
+ 1, 1, get64 ());
12429 oappend_maybe_intel (scratchbuf
);
12430 scratchbuf
[0] = '\0';
12434 OP_sI (int bytemode
, int sizeflag
)
12442 FETCH_DATA (the_info
, codep
+ 1);
12444 if ((op
& 0x80) != 0)
12446 if (bytemode
== b_T_mode
)
12448 if (address_mode
!= mode_64bit
12449 || !((sizeflag
& DFLAG
) || (rex
& REX_W
)))
12451 /* The operand-size prefix is overridden by a REX prefix. */
12452 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
12460 if (!(rex
& REX_W
))
12462 if (sizeflag
& DFLAG
)
12470 /* The operand-size prefix is overridden by a REX prefix. */
12471 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
12477 oappend (INTERNAL_DISASSEMBLER_ERROR
);
12481 scratchbuf
[0] = '$';
12482 print_operand_value (scratchbuf
+ 1, 1, op
);
12483 oappend_maybe_intel (scratchbuf
);
12487 OP_J (int bytemode
, int sizeflag
)
12491 bfd_vma segment
= 0;
12496 FETCH_DATA (the_info
, codep
+ 1);
12498 if ((disp
& 0x80) != 0)
12503 if ((sizeflag
& DFLAG
)
12504 || (address_mode
== mode_64bit
12505 && ((isa64
== intel64
&& bytemode
!= dqw_mode
)
12506 || (rex
& REX_W
))))
12511 if ((disp
& 0x8000) != 0)
12513 /* In 16bit mode, address is wrapped around at 64k within
12514 the same segment. Otherwise, a data16 prefix on a jump
12515 instruction means that the pc is masked to 16 bits after
12516 the displacement is added! */
12518 if ((prefixes
& PREFIX_DATA
) == 0)
12519 segment
= ((start_pc
+ (codep
- start_codep
))
12520 & ~((bfd_vma
) 0xffff));
12522 if (address_mode
!= mode_64bit
12523 || (isa64
!= intel64
&& !(rex
& REX_W
)))
12524 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12527 oappend (INTERNAL_DISASSEMBLER_ERROR
);
12530 disp
= ((start_pc
+ (codep
- start_codep
) + disp
) & mask
) | segment
;
12532 print_operand_value (scratchbuf
, 1, disp
);
12533 oappend (scratchbuf
);
12537 OP_SEG (int bytemode
, int sizeflag
)
12539 if (bytemode
== w_mode
)
12540 oappend (names_seg
[modrm
.reg
]);
12542 OP_E (modrm
.mod
== 3 ? bytemode
: w_mode
, sizeflag
);
12546 OP_DIR (int dummy ATTRIBUTE_UNUSED
, int sizeflag
)
12550 if (sizeflag
& DFLAG
)
12560 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12562 sprintf (scratchbuf
, "0x%x:0x%x", seg
, offset
);
12564 sprintf (scratchbuf
, "$0x%x,$0x%x", seg
, offset
);
12565 oappend (scratchbuf
);
12569 OP_OFF (int bytemode
, int sizeflag
)
12573 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
12574 intel_operand_size (bytemode
, sizeflag
);
12577 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
12584 if (!active_seg_prefix
)
12586 oappend (names_seg
[ds_reg
- es_reg
]);
12590 print_operand_value (scratchbuf
, 1, off
);
12591 oappend (scratchbuf
);
12595 OP_OFF64 (int bytemode
, int sizeflag
)
12599 if (address_mode
!= mode_64bit
12600 || (prefixes
& PREFIX_ADDR
))
12602 OP_OFF (bytemode
, sizeflag
);
12606 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
12607 intel_operand_size (bytemode
, sizeflag
);
12614 if (!active_seg_prefix
)
12616 oappend (names_seg
[ds_reg
- es_reg
]);
12620 print_operand_value (scratchbuf
, 1, off
);
12621 oappend (scratchbuf
);
12625 ptr_reg (int code
, int sizeflag
)
12629 *obufp
++ = open_char
;
12630 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
12631 if (address_mode
== mode_64bit
)
12633 if (!(sizeflag
& AFLAG
))
12634 s
= names32
[code
- eAX_reg
];
12636 s
= names64
[code
- eAX_reg
];
12638 else if (sizeflag
& AFLAG
)
12639 s
= names32
[code
- eAX_reg
];
12641 s
= names16
[code
- eAX_reg
];
12643 *obufp
++ = close_char
;
12648 OP_ESreg (int code
, int sizeflag
)
12654 case 0x6d: /* insw/insl */
12655 intel_operand_size (z_mode
, sizeflag
);
12657 case 0xa5: /* movsw/movsl/movsq */
12658 case 0xa7: /* cmpsw/cmpsl/cmpsq */
12659 case 0xab: /* stosw/stosl */
12660 case 0xaf: /* scasw/scasl */
12661 intel_operand_size (v_mode
, sizeflag
);
12664 intel_operand_size (b_mode
, sizeflag
);
12667 oappend_maybe_intel ("%es:");
12668 ptr_reg (code
, sizeflag
);
12672 OP_DSreg (int code
, int sizeflag
)
12678 case 0x6f: /* outsw/outsl */
12679 intel_operand_size (z_mode
, sizeflag
);
12681 case 0xa5: /* movsw/movsl/movsq */
12682 case 0xa7: /* cmpsw/cmpsl/cmpsq */
12683 case 0xad: /* lodsw/lodsl/lodsq */
12684 intel_operand_size (v_mode
, sizeflag
);
12687 intel_operand_size (b_mode
, sizeflag
);
12690 /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
12691 default segment register DS is printed. */
12692 if (!active_seg_prefix
)
12693 active_seg_prefix
= PREFIX_DS
;
12695 ptr_reg (code
, sizeflag
);
12699 OP_C (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
12707 else if (address_mode
!= mode_64bit
&& (prefixes
& PREFIX_LOCK
))
12709 all_prefixes
[last_lock_prefix
] = 0;
12710 used_prefixes
|= PREFIX_LOCK
;
12715 sprintf (scratchbuf
, "%%cr%d", modrm
.reg
+ add
);
12716 oappend_maybe_intel (scratchbuf
);
12720 OP_D (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
12729 sprintf (scratchbuf
, "dr%d", modrm
.reg
+ add
);
12731 sprintf (scratchbuf
, "%%db%d", modrm
.reg
+ add
);
12732 oappend (scratchbuf
);
12736 OP_T (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
12738 sprintf (scratchbuf
, "%%tr%d", modrm
.reg
);
12739 oappend_maybe_intel (scratchbuf
);
12743 OP_MMX (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
12745 int reg
= modrm
.reg
;
12746 const char **names
;
12748 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12749 if (prefixes
& PREFIX_DATA
)
12758 oappend (names
[reg
]);
12762 OP_XMM (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
12764 int reg
= modrm
.reg
;
12765 const char **names
;
12777 && bytemode
!= xmm_mode
12778 && bytemode
!= xmmq_mode
12779 && bytemode
!= evex_half_bcst_xmmq_mode
12780 && bytemode
!= ymm_mode
12781 && bytemode
!= tmm_mode
12782 && bytemode
!= scalar_mode
)
12784 switch (vex
.length
)
12791 || (bytemode
!= vex_vsib_q_w_dq_mode
12792 && bytemode
!= vex_vsib_q_w_d_mode
))
12804 else if (bytemode
== xmmq_mode
12805 || bytemode
== evex_half_bcst_xmmq_mode
)
12807 switch (vex
.length
)
12820 else if (bytemode
== tmm_mode
)
12830 else if (bytemode
== ymm_mode
)
12834 oappend (names
[reg
]);
12838 OP_EM (int bytemode
, int sizeflag
)
12841 const char **names
;
12843 if (modrm
.mod
!= 3)
12846 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
12848 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
12849 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12851 OP_E (bytemode
, sizeflag
);
12855 if ((sizeflag
& SUFFIX_ALWAYS
) && bytemode
== v_swap_mode
)
12858 /* Skip mod/rm byte. */
12861 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12863 if (prefixes
& PREFIX_DATA
)
12872 oappend (names
[reg
]);
12875 /* cvt* are the only instructions in sse2 which have
12876 both SSE and MMX operands and also have 0x66 prefix
12877 in their opcode. 0x66 was originally used to differentiate
12878 between SSE and MMX instruction(operands). So we have to handle the
12879 cvt* separately using OP_EMC and OP_MXC */
12881 OP_EMC (int bytemode
, int sizeflag
)
12883 if (modrm
.mod
!= 3)
12885 if (intel_syntax
&& bytemode
== v_mode
)
12887 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
12888 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12890 OP_E (bytemode
, sizeflag
);
12894 /* Skip mod/rm byte. */
12897 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12898 oappend (names_mm
[modrm
.rm
]);
12902 OP_MXC (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
12904 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12905 oappend (names_mm
[modrm
.reg
]);
12909 OP_EX (int bytemode
, int sizeflag
)
12912 const char **names
;
12914 /* Skip mod/rm byte. */
12918 if (modrm
.mod
!= 3)
12920 OP_E_memory (bytemode
, sizeflag
);
12935 if ((sizeflag
& SUFFIX_ALWAYS
)
12936 && (bytemode
== x_swap_mode
12937 || bytemode
== d_swap_mode
12938 || bytemode
== q_swap_mode
))
12942 && bytemode
!= xmm_mode
12943 && bytemode
!= xmmdw_mode
12944 && bytemode
!= xmmqd_mode
12945 && bytemode
!= xmm_mb_mode
12946 && bytemode
!= xmm_mw_mode
12947 && bytemode
!= xmm_md_mode
12948 && bytemode
!= xmm_mq_mode
12949 && bytemode
!= xmmq_mode
12950 && bytemode
!= evex_half_bcst_xmmq_mode
12951 && bytemode
!= ymm_mode
12952 && bytemode
!= tmm_mode
12953 && bytemode
!= vex_scalar_w_dq_mode
)
12955 switch (vex
.length
)
12970 else if (bytemode
== xmmq_mode
12971 || bytemode
== evex_half_bcst_xmmq_mode
)
12973 switch (vex
.length
)
12986 else if (bytemode
== tmm_mode
)
12996 else if (bytemode
== ymm_mode
)
13000 oappend (names
[reg
]);
13004 OP_MS (int bytemode
, int sizeflag
)
13006 if (modrm
.mod
== 3)
13007 OP_EM (bytemode
, sizeflag
);
13013 OP_XS (int bytemode
, int sizeflag
)
13015 if (modrm
.mod
== 3)
13016 OP_EX (bytemode
, sizeflag
);
13022 OP_M (int bytemode
, int sizeflag
)
13024 if (modrm
.mod
== 3)
13025 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
13028 OP_E (bytemode
, sizeflag
);
13032 OP_0f07 (int bytemode
, int sizeflag
)
13034 if (modrm
.mod
!= 3 || modrm
.rm
!= 0)
13037 OP_E (bytemode
, sizeflag
);
13040 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
13041 32bit mode and "xchg %rax,%rax" in 64bit mode. */
13044 NOP_Fixup1 (int bytemode
, int sizeflag
)
13046 if ((prefixes
& PREFIX_DATA
) != 0
13049 && address_mode
== mode_64bit
))
13050 OP_REG (bytemode
, sizeflag
);
13052 strcpy (obuf
, "nop");
13056 NOP_Fixup2 (int bytemode
, int sizeflag
)
13058 if ((prefixes
& PREFIX_DATA
) != 0
13061 && address_mode
== mode_64bit
))
13062 OP_IMREG (bytemode
, sizeflag
);
13065 static const char *const Suffix3DNow
[] = {
13066 /* 00 */ NULL
, NULL
, NULL
, NULL
,
13067 /* 04 */ NULL
, NULL
, NULL
, NULL
,
13068 /* 08 */ NULL
, NULL
, NULL
, NULL
,
13069 /* 0C */ "pi2fw", "pi2fd", NULL
, NULL
,
13070 /* 10 */ NULL
, NULL
, NULL
, NULL
,
13071 /* 14 */ NULL
, NULL
, NULL
, NULL
,
13072 /* 18 */ NULL
, NULL
, NULL
, NULL
,
13073 /* 1C */ "pf2iw", "pf2id", NULL
, NULL
,
13074 /* 20 */ NULL
, NULL
, NULL
, NULL
,
13075 /* 24 */ NULL
, NULL
, NULL
, NULL
,
13076 /* 28 */ NULL
, NULL
, NULL
, NULL
,
13077 /* 2C */ NULL
, NULL
, NULL
, NULL
,
13078 /* 30 */ NULL
, NULL
, NULL
, NULL
,
13079 /* 34 */ NULL
, NULL
, NULL
, NULL
,
13080 /* 38 */ NULL
, NULL
, NULL
, NULL
,
13081 /* 3C */ NULL
, NULL
, NULL
, NULL
,
13082 /* 40 */ NULL
, NULL
, NULL
, NULL
,
13083 /* 44 */ NULL
, NULL
, NULL
, NULL
,
13084 /* 48 */ NULL
, NULL
, NULL
, NULL
,
13085 /* 4C */ NULL
, NULL
, NULL
, NULL
,
13086 /* 50 */ NULL
, NULL
, NULL
, NULL
,
13087 /* 54 */ NULL
, NULL
, NULL
, NULL
,
13088 /* 58 */ NULL
, NULL
, NULL
, NULL
,
13089 /* 5C */ NULL
, NULL
, NULL
, NULL
,
13090 /* 60 */ NULL
, NULL
, NULL
, NULL
,
13091 /* 64 */ NULL
, NULL
, NULL
, NULL
,
13092 /* 68 */ NULL
, NULL
, NULL
, NULL
,
13093 /* 6C */ NULL
, NULL
, NULL
, NULL
,
13094 /* 70 */ NULL
, NULL
, NULL
, NULL
,
13095 /* 74 */ NULL
, NULL
, NULL
, NULL
,
13096 /* 78 */ NULL
, NULL
, NULL
, NULL
,
13097 /* 7C */ NULL
, NULL
, NULL
, NULL
,
13098 /* 80 */ NULL
, NULL
, NULL
, NULL
,
13099 /* 84 */ NULL
, NULL
, NULL
, NULL
,
13100 /* 88 */ NULL
, NULL
, "pfnacc", NULL
,
13101 /* 8C */ NULL
, NULL
, "pfpnacc", NULL
,
13102 /* 90 */ "pfcmpge", NULL
, NULL
, NULL
,
13103 /* 94 */ "pfmin", NULL
, "pfrcp", "pfrsqrt",
13104 /* 98 */ NULL
, NULL
, "pfsub", NULL
,
13105 /* 9C */ NULL
, NULL
, "pfadd", NULL
,
13106 /* A0 */ "pfcmpgt", NULL
, NULL
, NULL
,
13107 /* A4 */ "pfmax", NULL
, "pfrcpit1", "pfrsqit1",
13108 /* A8 */ NULL
, NULL
, "pfsubr", NULL
,
13109 /* AC */ NULL
, NULL
, "pfacc", NULL
,
13110 /* B0 */ "pfcmpeq", NULL
, NULL
, NULL
,
13111 /* B4 */ "pfmul", NULL
, "pfrcpit2", "pmulhrw",
13112 /* B8 */ NULL
, NULL
, NULL
, "pswapd",
13113 /* BC */ NULL
, NULL
, NULL
, "pavgusb",
13114 /* C0 */ NULL
, NULL
, NULL
, NULL
,
13115 /* C4 */ NULL
, NULL
, NULL
, NULL
,
13116 /* C8 */ NULL
, NULL
, NULL
, NULL
,
13117 /* CC */ NULL
, NULL
, NULL
, NULL
,
13118 /* D0 */ NULL
, NULL
, NULL
, NULL
,
13119 /* D4 */ NULL
, NULL
, NULL
, NULL
,
13120 /* D8 */ NULL
, NULL
, NULL
, NULL
,
13121 /* DC */ NULL
, NULL
, NULL
, NULL
,
13122 /* E0 */ NULL
, NULL
, NULL
, NULL
,
13123 /* E4 */ NULL
, NULL
, NULL
, NULL
,
13124 /* E8 */ NULL
, NULL
, NULL
, NULL
,
13125 /* EC */ NULL
, NULL
, NULL
, NULL
,
13126 /* F0 */ NULL
, NULL
, NULL
, NULL
,
13127 /* F4 */ NULL
, NULL
, NULL
, NULL
,
13128 /* F8 */ NULL
, NULL
, NULL
, NULL
,
13129 /* FC */ NULL
, NULL
, NULL
, NULL
,
13133 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
13135 const char *mnemonic
;
13137 FETCH_DATA (the_info
, codep
+ 1);
13138 /* AMD 3DNow! instructions are specified by an opcode suffix in the
13139 place where an 8-bit immediate would normally go. ie. the last
13140 byte of the instruction. */
13141 obufp
= mnemonicendp
;
13142 mnemonic
= Suffix3DNow
[*codep
++ & 0xff];
13144 oappend (mnemonic
);
13147 /* Since a variable sized modrm/sib chunk is between the start
13148 of the opcode (0x0f0f) and the opcode suffix, we need to do
13149 all the modrm processing first, and don't know until now that
13150 we have a bad opcode. This necessitates some cleaning up. */
13151 op_out
[0][0] = '\0';
13152 op_out
[1][0] = '\0';
13155 mnemonicendp
= obufp
;
13158 static const struct op simd_cmp_op
[] =
13160 { STRING_COMMA_LEN ("eq") },
13161 { STRING_COMMA_LEN ("lt") },
13162 { STRING_COMMA_LEN ("le") },
13163 { STRING_COMMA_LEN ("unord") },
13164 { STRING_COMMA_LEN ("neq") },
13165 { STRING_COMMA_LEN ("nlt") },
13166 { STRING_COMMA_LEN ("nle") },
13167 { STRING_COMMA_LEN ("ord") }
13170 static const struct op vex_cmp_op
[] =
13172 { STRING_COMMA_LEN ("eq_uq") },
13173 { STRING_COMMA_LEN ("nge") },
13174 { STRING_COMMA_LEN ("ngt") },
13175 { STRING_COMMA_LEN ("false") },
13176 { STRING_COMMA_LEN ("neq_oq") },
13177 { STRING_COMMA_LEN ("ge") },
13178 { STRING_COMMA_LEN ("gt") },
13179 { STRING_COMMA_LEN ("true") },
13180 { STRING_COMMA_LEN ("eq_os") },
13181 { STRING_COMMA_LEN ("lt_oq") },
13182 { STRING_COMMA_LEN ("le_oq") },
13183 { STRING_COMMA_LEN ("unord_s") },
13184 { STRING_COMMA_LEN ("neq_us") },
13185 { STRING_COMMA_LEN ("nlt_uq") },
13186 { STRING_COMMA_LEN ("nle_uq") },
13187 { STRING_COMMA_LEN ("ord_s") },
13188 { STRING_COMMA_LEN ("eq_us") },
13189 { STRING_COMMA_LEN ("nge_uq") },
13190 { STRING_COMMA_LEN ("ngt_uq") },
13191 { STRING_COMMA_LEN ("false_os") },
13192 { STRING_COMMA_LEN ("neq_os") },
13193 { STRING_COMMA_LEN ("ge_oq") },
13194 { STRING_COMMA_LEN ("gt_oq") },
13195 { STRING_COMMA_LEN ("true_us") },
13199 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
13201 unsigned int cmp_type
;
13203 FETCH_DATA (the_info
, codep
+ 1);
13204 cmp_type
= *codep
++ & 0xff;
13205 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
))
13208 char *p
= mnemonicendp
- 2;
13212 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
13213 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
13216 && cmp_type
< ARRAY_SIZE (simd_cmp_op
) + ARRAY_SIZE (vex_cmp_op
))
13219 char *p
= mnemonicendp
- 2;
13223 cmp_type
-= ARRAY_SIZE (simd_cmp_op
);
13224 sprintf (p
, "%s%s", vex_cmp_op
[cmp_type
].name
, suffix
);
13225 mnemonicendp
+= vex_cmp_op
[cmp_type
].len
;
13229 /* We have a reserved extension byte. Output it directly. */
13230 scratchbuf
[0] = '$';
13231 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
13232 oappend_maybe_intel (scratchbuf
);
13233 scratchbuf
[0] = '\0';
13238 OP_Mwait (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
13240 /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx */
13243 strcpy (op_out
[0], names32
[0]);
13244 strcpy (op_out
[1], names32
[1]);
13245 if (bytemode
== eBX_reg
)
13246 strcpy (op_out
[2], names32
[3]);
13247 two_source_ops
= 1;
13249 /* Skip mod/rm byte. */
13255 OP_Monitor (int bytemode ATTRIBUTE_UNUSED
,
13256 int sizeflag ATTRIBUTE_UNUSED
)
13258 /* monitor %{e,r,}ax,%ecx,%edx" */
13261 const char **names
= (address_mode
== mode_64bit
13262 ? names64
: names32
);
13264 if (prefixes
& PREFIX_ADDR
)
13266 /* Remove "addr16/addr32". */
13267 all_prefixes
[last_addr_prefix
] = 0;
13268 names
= (address_mode
!= mode_32bit
13269 ? names32
: names16
);
13270 used_prefixes
|= PREFIX_ADDR
;
13272 else if (address_mode
== mode_16bit
)
13274 strcpy (op_out
[0], names
[0]);
13275 strcpy (op_out
[1], names32
[1]);
13276 strcpy (op_out
[2], names32
[2]);
13277 two_source_ops
= 1;
13279 /* Skip mod/rm byte. */
13287 /* Throw away prefixes and 1st. opcode byte. */
13288 codep
= insn_codep
+ 1;
13293 REP_Fixup (int bytemode
, int sizeflag
)
13295 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
13297 if (prefixes
& PREFIX_REPZ
)
13298 all_prefixes
[last_repz_prefix
] = REP_PREFIX
;
13305 OP_IMREG (bytemode
, sizeflag
);
13308 OP_ESreg (bytemode
, sizeflag
);
13311 OP_DSreg (bytemode
, sizeflag
);
13320 SEP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
13322 if ( isa64
!= amd64
)
13327 mnemonicendp
= obufp
;
13331 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
13335 BND_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
13337 if (prefixes
& PREFIX_REPNZ
)
13338 all_prefixes
[last_repnz_prefix
] = BND_PREFIX
;
13341 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
13345 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED
,
13346 int sizeflag ATTRIBUTE_UNUSED
)
13348 if (active_seg_prefix
== PREFIX_DS
13349 && (address_mode
!= mode_64bit
|| last_data_prefix
< 0))
13351 /* NOTRACK prefix is only valid on indirect branch instructions.
13352 NB: DATA prefix is unsupported for Intel64. */
13353 active_seg_prefix
= 0;
13354 all_prefixes
[last_seg_prefix
] = NOTRACK_PREFIX
;
13358 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
13359 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
13363 HLE_Fixup1 (int bytemode
, int sizeflag
)
13366 && (prefixes
& PREFIX_LOCK
) != 0)
13368 if (prefixes
& PREFIX_REPZ
)
13369 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
13370 if (prefixes
& PREFIX_REPNZ
)
13371 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
13374 OP_E (bytemode
, sizeflag
);
13377 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
13378 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
13382 HLE_Fixup2 (int bytemode
, int sizeflag
)
13384 if (modrm
.mod
!= 3)
13386 if (prefixes
& PREFIX_REPZ
)
13387 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
13388 if (prefixes
& PREFIX_REPNZ
)
13389 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
13392 OP_E (bytemode
, sizeflag
);
13395 /* Similar to OP_E. But the 0xf3 prefixes should be displayed as
13396 "xrelease" for memory operand. No check for LOCK prefix. */
13399 HLE_Fixup3 (int bytemode
, int sizeflag
)
13402 && last_repz_prefix
> last_repnz_prefix
13403 && (prefixes
& PREFIX_REPZ
) != 0)
13404 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
13406 OP_E (bytemode
, sizeflag
);
13410 CMPXCHG8B_Fixup (int bytemode
, int sizeflag
)
13415 /* Change cmpxchg8b to cmpxchg16b. */
13416 char *p
= mnemonicendp
- 2;
13417 mnemonicendp
= stpcpy (p
, "16b");
13420 else if ((prefixes
& PREFIX_LOCK
) != 0)
13422 if (prefixes
& PREFIX_REPZ
)
13423 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
13424 if (prefixes
& PREFIX_REPNZ
)
13425 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
13428 OP_M (bytemode
, sizeflag
);
13432 XMM_Fixup (int reg
, int sizeflag ATTRIBUTE_UNUSED
)
13434 const char **names
;
13438 switch (vex
.length
)
13452 oappend (names
[reg
]);
13456 FXSAVE_Fixup (int bytemode
, int sizeflag
)
13458 /* Add proper suffix to "fxsave" and "fxrstor". */
13462 char *p
= mnemonicendp
;
13468 OP_M (bytemode
, sizeflag
);
13471 /* Display the destination register operand for instructions with
13475 OP_VEX (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
13478 const char **names
;
13483 reg
= vex
.register_specifier
;
13484 vex
.register_specifier
= 0;
13485 if (address_mode
!= mode_64bit
)
13487 else if (vex
.evex
&& !vex
.v
)
13490 if (bytemode
== vex_scalar_mode
)
13492 oappend (names_xmm
[reg
]);
13496 if (bytemode
== tmm_mode
)
13498 /* All 3 TMM registers must be distinct. */
13503 /* This must be the 3rd operand. */
13504 if (obufp
!= op_out
[2])
13506 oappend (names_tmm
[reg
]);
13507 if (reg
== modrm
.reg
|| reg
== modrm
.rm
)
13508 strcpy (obufp
, "/(bad)");
13511 if (modrm
.reg
== modrm
.rm
|| modrm
.reg
== reg
|| modrm
.rm
== reg
)
13514 && (modrm
.reg
== modrm
.rm
|| modrm
.reg
== reg
))
13515 strcat (op_out
[0], "/(bad)");
13517 && (modrm
.rm
== modrm
.reg
|| modrm
.rm
== reg
))
13518 strcat (op_out
[1], "/(bad)");
13524 switch (vex
.length
)
13530 case vex_vsib_q_w_dq_mode
:
13531 case vex_vsib_q_w_d_mode
:
13547 names
= names_mask
;
13560 case vex_vsib_q_w_dq_mode
:
13561 case vex_vsib_q_w_d_mode
:
13562 names
= vex
.w
? names_ymm
: names_xmm
;
13571 names
= names_mask
;
13574 /* See PR binutils/20893 for a reproducer. */
13586 oappend (names
[reg
]);
13590 OP_VexR (int bytemode
, int sizeflag
)
13592 if (modrm
.mod
== 3)
13593 OP_VEX (bytemode
, sizeflag
);
13597 OP_VexW (int bytemode
, int sizeflag
)
13599 OP_VEX (bytemode
, sizeflag
);
13603 /* Swap 2nd and 3rd operands. */
13604 strcpy (scratchbuf
, op_out
[2]);
13605 strcpy (op_out
[2], op_out
[1]);
13606 strcpy (op_out
[1], scratchbuf
);
13611 OP_REG_VexI4 (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
13614 const char **names
= names_xmm
;
13616 FETCH_DATA (the_info
, codep
+ 1);
13619 if (bytemode
!= x_mode
&& bytemode
!= scalar_mode
)
13623 if (address_mode
!= mode_64bit
)
13626 if (bytemode
== x_mode
&& vex
.length
== 256)
13629 oappend (names
[reg
]);
13633 /* Swap 3rd and 4th operands. */
13634 strcpy (scratchbuf
, op_out
[3]);
13635 strcpy (op_out
[3], op_out
[2]);
13636 strcpy (op_out
[2], scratchbuf
);
13641 OP_VexI4 (int bytemode ATTRIBUTE_UNUSED
,
13642 int sizeflag ATTRIBUTE_UNUSED
)
13644 scratchbuf
[0] = '$';
13645 print_operand_value (scratchbuf
+ 1, 1, codep
[-1] & 0xf);
13646 oappend_maybe_intel (scratchbuf
);
13650 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
,
13651 int sizeflag ATTRIBUTE_UNUSED
)
13653 unsigned int cmp_type
;
13658 FETCH_DATA (the_info
, codep
+ 1);
13659 cmp_type
= *codep
++ & 0xff;
13660 /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
13661 If it's the case, print suffix, otherwise - print the immediate. */
13662 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
)
13667 char *p
= mnemonicendp
- 2;
13669 /* vpcmp* can have both one- and two-lettered suffix. */
13683 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
13684 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
13688 /* We have a reserved extension byte. Output it directly. */
13689 scratchbuf
[0] = '$';
13690 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
13691 oappend_maybe_intel (scratchbuf
);
13692 scratchbuf
[0] = '\0';
13696 static const struct op xop_cmp_op
[] =
13698 { STRING_COMMA_LEN ("lt") },
13699 { STRING_COMMA_LEN ("le") },
13700 { STRING_COMMA_LEN ("gt") },
13701 { STRING_COMMA_LEN ("ge") },
13702 { STRING_COMMA_LEN ("eq") },
13703 { STRING_COMMA_LEN ("neq") },
13704 { STRING_COMMA_LEN ("false") },
13705 { STRING_COMMA_LEN ("true") }
13709 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED
,
13710 int sizeflag ATTRIBUTE_UNUSED
)
13712 unsigned int cmp_type
;
13714 FETCH_DATA (the_info
, codep
+ 1);
13715 cmp_type
= *codep
++ & 0xff;
13716 if (cmp_type
< ARRAY_SIZE (xop_cmp_op
))
13719 char *p
= mnemonicendp
- 2;
13721 /* vpcom* can have both one- and two-lettered suffix. */
13735 sprintf (p
, "%s%s", xop_cmp_op
[cmp_type
].name
, suffix
);
13736 mnemonicendp
+= xop_cmp_op
[cmp_type
].len
;
13740 /* We have a reserved extension byte. Output it directly. */
13741 scratchbuf
[0] = '$';
13742 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
13743 oappend_maybe_intel (scratchbuf
);
13744 scratchbuf
[0] = '\0';
13748 static const struct op pclmul_op
[] =
13750 { STRING_COMMA_LEN ("lql") },
13751 { STRING_COMMA_LEN ("hql") },
13752 { STRING_COMMA_LEN ("lqh") },
13753 { STRING_COMMA_LEN ("hqh") }
13757 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED
,
13758 int sizeflag ATTRIBUTE_UNUSED
)
13760 unsigned int pclmul_type
;
13762 FETCH_DATA (the_info
, codep
+ 1);
13763 pclmul_type
= *codep
++ & 0xff;
13764 switch (pclmul_type
)
13775 if (pclmul_type
< ARRAY_SIZE (pclmul_op
))
13778 char *p
= mnemonicendp
- 3;
13783 sprintf (p
, "%s%s", pclmul_op
[pclmul_type
].name
, suffix
);
13784 mnemonicendp
+= pclmul_op
[pclmul_type
].len
;
13788 /* We have a reserved extension byte. Output it directly. */
13789 scratchbuf
[0] = '$';
13790 print_operand_value (scratchbuf
+ 1, 1, pclmul_type
);
13791 oappend_maybe_intel (scratchbuf
);
13792 scratchbuf
[0] = '\0';
13797 MOVSXD_Fixup (int bytemode
, int sizeflag
)
13799 /* Add proper suffix to "movsxd". */
13800 char *p
= mnemonicendp
;
13825 oappend (INTERNAL_DISASSEMBLER_ERROR
);
13832 OP_E (bytemode
, sizeflag
);
13836 OP_Mask (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
13839 || (bytemode
!= mask_mode
&& bytemode
!= mask_bd_mode
))
13843 if ((rex
& REX_R
) != 0 || !vex
.r
)
13849 oappend (names_mask
[modrm
.reg
]);
13853 OP_Rounding (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
13855 if (modrm
.mod
== 3 && vex
.b
)
13858 case evex_rounding_64_mode
:
13859 if (address_mode
!= mode_64bit
)
13864 /* Fall through. */
13865 case evex_rounding_mode
:
13866 oappend (names_rounding
[vex
.ll
]);
13868 case evex_sae_mode
: